branch_name stringclasses 149 values | text stringlengths 23 89.3M | directory_id stringlengths 40 40 | languages listlengths 1 19 | num_files int64 1 11.8k | repo_language stringclasses 38 values | repo_name stringlengths 6 114 | revision_id stringlengths 40 40 | snapshot_id stringlengths 40 40 |
|---|---|---|---|---|---|---|---|---|
refs/heads/main | <repo_name>Gomerinho/E-CommerceGaming<file_sep>/ecommercegaming/app/Http/Controllers/ProductController.php
<?php
namespace App\Http\Controllers;
use Illuminate\Http\Request;
use App\Models\Product as Product;
use App\Models\Review as Review;
use Illuminate\Support\Facades\DB;
use Illuminate\Support\Str;
class ProductController extends Controller
{
public function form() //Affichage du formulaire
{
if (auth()->user()->is_admin) { //Uniquement pour les admins connectés
return view('Products/addProduct');
}
}
public function addProduct(Request $request) //Ajouter un jeu
{
if ($request->hasFile('file')) {
$destinationPath = '/public/image/product'; //Destination de l'image du jeu
$image = $request->file('file'); //On récupère l'image
$imageName = Str::random(10) . "." . $image->getClientOriginalExtension(); //Création d'un nom aléatoire
$path = $request->file('file')->storeAs($destinationPath, $imageName); //Stockage de l'image
Product::create([
'name' => request('name'),
'desc' => request('desc'),
'price' => request('price'),
'stock' => request('stock'),
'activation_code' => request('activation_code'),
'img_product' => $imageName,
]); //Création du produit
flash('Vous avez ajouté un jeu')->success();
return redirect('/admin/product');
}
flash("Vous n'avez pas renseigner tout les champs")->error();
return back();
}
public function productPage(Request $request)
{
$id = $request->id;
$product = Product::where('id', $id)->first();
$reviews = DB::table('reviews')
->where('product_id', request('id'))
->join('users', 'user_id', '=', 'users.id')
->select('reviews.*', 'users.name')
->get(); //On récupère les reviews qui correspondent au Jeu afficher
foreach ($product as $products) { //Ce for each permet de créer une moyenne de la note
$rate = DB::table('reviews')
->where('product_id', request('id'))
->avg('star');
$rate = round($rate, 1); //Round permet d'arround à 1 décimal
}
return view('Products/product', [
'id' => $product->id,
'product' => $product,
'review' => $reviews,
'rate' => $rate
]); //Retourne la vue avec toutes les données
}
public function search()
{
$search = request('search');
if ($search != "") {
$products = Product::where('name', 'LIKE', '%' . $search . '%')->get();
if ($products != null) {
return view('Products/search', [
'products' => $products
]);
} else {
flash('Aucun jeu correspondant')->error();
return redirect('/');
}
} else {
return back();
}
}
}
<file_sep>/ecommercegaming/app/Http/Controllers/VenteController.php
<?php
namespace App\Http\Controllers;
use App;
use Illuminate\Http\Request;
use Illuminate\Support\Facades\Mail;
use PDF;
use App\Models\Vente as Vente;
use App\Models\User as User;
use App\Models\Product as Product;
use Illuminate\Support\Facades\Storage;
use App\Mail\Vente as VenteMail;
class VenteController extends Controller
{
public function index()
{
$ventes = Vente::where('user_id', '=', auth()->user()->id)->get(); //On récupère toutes les ventes correspondant à l'utilisateur
foreach ($ventes as $vente) {
$product = $vente->product; //on crée une variable produit qui correspond au produit de la vente
$user = $vente->user; //on crée une variable user qui correspond a l'user de la vente
}
return view('Vente/index', [
'user' => $user,
'ventes' => $ventes,
'product' => $product
]); //On renvoie la vue avec toutes les ventes, les produits et l'user
}
public function achat()
{
//Je commence par défubur notre produit
$product_id = request('id');
$product = Product::where('id', '=', $product_id)->first();
$price = $product->price; //On récupère le prix
$ventes = Vente::where('user_id', '=', auth()->user()->id)->where('product_id', '=', $product->id)->first(); //on cherche les ventes correspondante au produit
if (isset($ventes)) { //Si une vente existe alors l'utilisateur ne peux pas acheter le jeux
flash('Vous avez déjà acheté le jeu')->error();
return back();
}
if (auth()->user()->wallet > $price && $product->stock > 0) { //On vérifie le stock et l'argent
Vente::create([
'invoice_path' => '/',
'product_id' => $product->id,
'user_id' => auth()->user()->id
]); //Si tout est bon , on crée une vente
$stock = $product->stock - 1;
$product->update([
'stock' => $stock
]);
$user = auth()->user(); //Initialisation de l'user
$user->wallet -= $price; //On lui retire le prix du produit
$user->save();
auth()->user()->update([
'wallet' => $user->wallet
]);
$vente = Vente::latest()->first(); //On récupère la dernière vente (celle en cours)
$path = 'public/invoice/' . auth()->user()->id . '/facture' . $vente->id . '.pdf'; //Création du chemin du fichier pdf
$vente->update([
'invoice_path' => $path,
]); //On update la colonne vers le chemin du fichier pdf (pour le récupérer dans la page admin)
$pdf = App::make('dompdf.wrapper'); //Création du pdf
$content = $pdf->loadView('Mail/vente', [
'user' => auth()->user(),
'product' => $product,
'vente' => $vente
])->download()->getOriginalContent(); //Contenu du pdf provient de la vue vente pour le stockage en interne
$pdfmails = PDF::loadView('Mail/vente', [
'user' => auth()->user(),
'product' => $product,
'vente' => $vente
]); //Création du fichier pour l'envoie du mail
Storage::put($path, $content); //Stockage du fichier
$messages = new VenteMail(auth()->user(), $product, $vente); //Création de notre message dans le mail
$messages->attachData($pdfmails->output(), "facture.pdf"); //on attach le fichier au message
Mail::to(auth()->user()->email)->send($messages); //Envoi du mail
flash('Votre achat a été effectué, un mail va vous être envoyé')->success(); //Renvoie une alerte de succes
return redirect('/dashboard');
} else {
flash("Vous n'avez pas assez de crédit ou le stock est épuisé! ")->error(); //Si il n'a pas assez d'agent ou le stock est épuisé
return back();
}
}
}
<file_sep>/ecommercegaming/app/Http/Controllers/UsersController.php
<?php
namespace App\Http\Controllers;
use Illuminate\Http\Request;
use App\Models\User as User;
class UsersController extends Controller
{
public function index()
{
$utilisateurs = User::all();
return view('Users/utilisateurs', [
'utilisateurs' => $utilisateurs
]);
}
}
<file_sep>/README.md
# E-CommerceGaming
Projet Technologies WEB B2
Ce Projet a pour objectif de réaliser un site e-commercer.
Dans ce cite nous pouvons Ajouter des jeux en ventes.
Avoir un profil modifiabel.
Il y a un panneau administrateur pour gérer toutes les données du sites.
GOMES <NAME> & PANNETRAT Mathieu
La base de donnée est fourni.
<file_sep>/ecommercegaming/app/Http/Controllers/AdminController.php
<?php
namespace App\Http\Controllers;
use Illuminate\Http\Request;
use App\Models\User as User;
use App\Models\Product as Product;
use App\Models\Vente as Vente;
use Carbon\Carbon;
class AdminController extends Controller
{
public function adminPanel()
{
$date = \Carbon\Carbon::today()->subDays(7); //Permet de récupérer les 7 derniers jours
$users = User::all();
$userscount = User::all()->count(); //Compte tout les utilisateurs du site
$userscount7 = User::where('created_at', '>=', $date)
->count(); //Les utilisateurs inscrit dans les 7 derniers jours
$ventes = Vente::All(); //On récupère toutes les ventes effectué
if (auth()->check()) { //Vérification que l'utilisateur est connecté
if (auth()->user()->is_admin) { //Vérification que l'utilisateur est administrateur
return view('Admin/adminPanel', [
'users' => $users,
'userscount' => $userscount,
'userscount7' => $userscount7,
'ventes' => $ventes
]);
} else {
flash('Vous devez être administrateur pour accéder à cette page')->error();
return redirect('/dashboard');
}
} elseif (auth()->guest()) {
flash('Vous devez être connecté pour accéder a cette page')->error();
return redirect('/inscription');
}
}
public function modifyUserForm()
{
$user = User::where('id', '=', request('id'))->first(); //ON récupère l'utilisateur qui correspond
$ventes = Vente::where('user_id', '=', request('id'))->get();
if (auth()->user()->is_admin) {
return view('Admin/modifyUser', [
'user' => $user,
'ventes' => $ventes
]);
}
}
public function modifyUser()
{
$users = User::all();
$user = User::where('id', '=', request('id'))->first();
if ($user->email == request('email')) {
request()->validate([
'name' => ['required'],
'email' => ['required'],
'birthdate' => ['required'],
'wallet' => ['required'],
'is_admin' => ['required'],
]);
} else {
request()->validate([
'name' => ['required'],
'email' => ['required', 'unique:users'],
'birthdate' => ['required'],
'wallet' => ['required'],
'is_admin' => ['required'],
]);
}
$user->update([
'name' => request('name'),
'email' => request('email'),
'birthdate' => request('birthdate'),
'wallet' => request('wallet'),
'is_admin' => request('is_admin'),
]);
flash("Vous avez modifier l'utilisateur : " . $user->name . ".")->success();
return redirect('/admin');
}
public function productIndex()
{
$products = Product::All();
$user = Product::where('id', '=', request('id'))->first();
$productcount = $products->count();
if (auth()->user()->is_admin) {
return view('Admin/adminProduct', [
'products' => $products,
'productcount' => $productcount
]);
}
}
public function modifyProductForm()
{
$product = Product::where('id', '=', request('id'))->first();
if (auth()->user()->is_admin) {
return view('Admin/modifyProduct', [
'product' => $product
]);
}
}
public function modifyProduct(Request $request)
{
$products = Product::all();
$product = Product::where('id', '=', request('id'))->first();
request()->validate([
'name' => ['required'],
'desc' => ['required',],
'stock' => ['required'],
'price' => ['required'],
'activation_code' => ['required'],
]);
if (null !== request('file')) { //Permet de vérifier si on change l'image ou non
$destinationPath = '/public/image/product';
$imageName = request('img_product');
$request->file('file')->storeAs($destinationPath, $imageName);
$product->update([
'img_product' => $imageName,
'name' => request('name'),
'desc' => request('desc'),
'stock' => request('stock'),
'price' => request('price'),
'activation_code' => request('activation_code'),
]);
} else {
$product->update([
'name' => request('name'),
'desc' => request('desc'),
'stock' => request('stock'),
'price' => request('price'),
'activation_code' => request('activation_code'),
]);
}
flash("Vous avez modifier le jeu : " . $product->name . ".")->success();
return redirect('/admin/product');
}
}
<file_sep>/ecommercegaming/app/Http/Controllers/AccountController.php
<?php
namespace App\Http\Controllers;
use Illuminate\Http\Request;
use App\Models\User as User;
use App\Models\Product as Product;
use App\Models\Vente as Vente;
class AccountController extends Controller
{
public function dashboard() //affichage du profil
{
$ventes = Vente::where('user_id', '=', auth()->user()->id)->get();
// if (isset($ventes)) {
// foreach ($ventes as $vente) {
// $product = $vente->product;
// }
return view('Users/dashboard', [
'user' => auth()->user(),
'ventes' => $ventes
]);
// }
if (auth()->check()) {
} elseif (auth()->guest()) {
flash('Vous devez être connecté pour accéder a cette page')->error();
return redirect('/inscription');
}
}
public function signout() //deconnexion
{
auth()->logout();
flash('Vous êtes déconnecté.')->success();
return redirect('/inscription');
}
public function birthdate() //Changement de la date de naissance
{
$user = auth()->user();
$user->birthdate = request('date');
$user->save();
auth()->user()->update([
'birthdate' => $user->birthdate
]);
flash('Votre date de naissance a été changée.')->success();
return redirect('/dashboard');
}
public function email_modification() //Modification de l'email
{
request()->validate([
'email' => ['required', 'email', 'unique:users'],
]);
$user = auth()->user();
$user->email = request('email');
$user->save();
flash('Votre adresse mail a bien été changée.')->success();
return view('Users/dashboard', [
'user' => auth()->user(),
]);
}
public function password_modification() //Modification du mot de passe
{
request()->validate([
'password' => ['required', 'min:8', 'confirmed'],
'password_confirmation' => ['required']
]);
$user = auth()->user();
$user->password = <PASSWORD>(request('password'));
$user->save();
// OU
// auth()->user()->update([
// 'password' => <PASSWORD>(request('password')),
// ]);
flash('Votre mot de passse a bien été modifiié ')->success();
return redirect('/dashboard');
}
}
<file_sep>/ecommercegaming/public/js/datatables-demo.js
/******/ (() => { // webpackBootstrap
/*!**********************************************!*\
!*** ./resources/js/demo/datatables-demo.js ***!
\**********************************************/
// Call the dataTables jQuery plugin
/******/ })()
;<file_sep>/ecommercegaming/app/Http/Controllers/InscriptionController.php
<?php
namespace App\Http\Controllers;
use Illuminate\Http\Request;
use App\Models\User as User;
class InscriptionController extends Controller
{
public function verification() //Vérification et création de l'user
{
request()->validate([
'email' => ['required', 'email', 'unique:users'],
'password' => ['<PASSWORD>', '<PASSWORD>', '<PASSWORD>'],
'password_confirmation' => ['<PASSWORD>']
]); //On vérifie que les données entrées sont bonne et valide les critères requis
User::create([
'email' => request('email'),
'password' => <PASSWORD>(request('password')),
'name' => request('name'),
'birthdate' => request('birthdate'),
]); //Création de l'user dans la base de donnée
flash('success', 'Vous êtes inscrit, connectez vous !');
return redirect('/inscription');
}
public function formulaire() //Affichage du formulaire
{
return view('inscription');
}
}
<file_sep>/ecommercegaming/routes/web.php
<?php
use App\Http\Controllers\UsersController;
use App\Http\Controllers\InscriptionController;
use App\Http\Controllers\AccountController;
use App\Http\Controllers\ProductController;
use App\Http\Controllers\ConnexionController;
use App\Http\Controllers\ReviewController;
use App\Http\Controllers\AdminController;
use App\Http\Controllers\VenteController;
use App\Http\Controllers\PdfController;
use Illuminate\Support\Facades\Route;
use Illuminate\Support\Facades\File;
use Illuminate\Support\Facades\Storage;
use App\Models\User as User;
use App\Models\Product as Product;
use App\Models\Review as Review;
use Illuminate\Database\Eloquent\Collection;
/*
|--------------------------------------------------------------------------
| Web Routes
|--------------------------------------------------------------------------
|
| Here is where you can register web routes for your application. These
| routes are loaded by the RouteServiceProvider within a group which
| contains the "web" middleware group. Now create something great!
|
*/
Route::get('/', function () { //Affichage des produits dans la page d'acceuil
$products = Product::simplePaginate(6); //Systeme de pagination
$reviews = Review::all();
return view('welcome', [
'products' => $products,
'reviews' => $reviews,
]);
});
Route::post('/inscription', [InscriptionController::class, 'verification']);
Route::get('/inscription', [InscriptionController::class, 'formulaire']);
Route::get('users', [UsersController::class, 'index']);
Route::post('/connexion', [ConnexionController::class, 'traitement']);
Route::get('/dashboard', [AccountController::class, 'dashboard']);
Route::get('/signout', [AccountController::class, 'signout']);
Route::post('/email_modification', [AccountController::class, 'email_modification']);
Route::post('/password_modification', [AccountController::class, 'password_modification']);
Route::post('/birthdate', [AccountController::class, 'birthdate']);
Route::get('/addProduct', [ProductController::class, 'form']);
Route::post('/addProduct', [ProductController::class, 'addProduct']);
Route::get('/product/{id}', [ProductController::class, 'productPage']);
Route::get('/comment/{id}', [ReviewController::class, 'commentPage']);
Route::post('/addReview', [ReviewController::class, 'addReview']);
Route::get('/admin', [AdminController::class, 'adminPanel']);
Route::get('/vente', [VenteController::class, 'index']);
Route::post('/vente', [VenteController::class, 'achat']);
Route::get('/admin/modifyUser/{id}', [AdminController::class, 'modifyUserForm']);
Route::post('/admin/modifyUser', [AdminController::class, 'modifyUser']);
Route::get('/admin/product', [AdminController::class, 'productIndex']);
Route::get('/admin/modifyProduct/{id}', [AdminController::class, 'modifyProductForm']);
Route::post('/admin/modifyProduct', [AdminController::class, 'modifyProduct']);
Route::get('/facture', [PdfController::class, 'open']);
Route::post('/search', [ProductController::class, 'search']);
<file_sep>/ecommercegaming/app/Mail/Vente.php
<?php
namespace App\Mail;
use Illuminate\Bus\Queueable;
use Illuminate\Contracts\Queue\ShouldQueue;
use Illuminate\Mail\Mailable;
use Illuminate\Queue\SerializesModels;
class Vente extends Mailable
{
use Queueable, SerializesModels;
/**
* Create a new message instance.
*
* @return void
*/
public $user;
public $product;
public $vente;
public function __construct($user, $product, $vente)
{
$this->user = $user;
$this->product = $product;
$this->vente = $vente;
}
/**
* Build the message.
*
* @return $this
*/
public function build()
{
return $this
->subject("Facture d'achat du jeu " . $this->product->name)
->view('Mail/vente');
}
}
| 1b5f31f925d616354cd3fb0bd5ade8ea4b314239 | [
"Markdown",
"JavaScript",
"PHP"
] | 10 | PHP | Gomerinho/E-CommerceGaming | c2d626c4fdf3b4bc3044ae49005f407e347b73c1 | 390d91b9ba20d54b7e17b2caa9b418ea684b908c |
refs/heads/master | <repo_name>rvllfil/smarthouse<file_sep>/led_telegrambot/led_telegrambot.ino
#include "CTBot.h"
CTBot myBot;
String ssid = "CAMPERNIQUE"; // REPLACE mySSID WITH YOUR WIFI SSID
String pass = "<PASSWORD>"; // REPLACE myPassword YOUR WIFI PASSWORD, IF ANY
String token = "<KEY>"; // REPLACE myToken WITH YOUR TELEGRAM BOT TOKEN
uint32_t chat_id = 358016920;
// Relay
uint8_t led1 = 16; //D0
uint8_t led2 = 5; //D1
uint8_t led3 = 4; //D2
uint8_t led4 = 0; //D3
// PIR
uint8_t pir = 14; // D5
int statusPIR = 0; // status logical
int data = 0; // variabel temporary utk menampung data PIR
// LED
int led_wifi = 12;
int led_pir = 15;
void setup() {
// set the pin connected to the LED to act as output pin
pinMode(led1, OUTPUT);
pinMode(led2, OUTPUT);
pinMode(led3, OUTPUT);
pinMode(led4, OUTPUT);
pinMode(led_wifi, OUTPUT);
pinMode(led_pir, OUTPUT);
digitalWrite(led1, HIGH);
digitalWrite(led2, HIGH);
digitalWrite(led3, HIGH);
digitalWrite(led4, HIGH);
digitalWrite(led_wifi, HIGH);
digitalWrite(led_pir, HIGH);
pinMode(pir, INPUT); // set pin 2 sbg input
// initialize the Serial
Serial.begin(115200);
Serial.println("Starting TelegramBot...");
// connect the ESP8266 to the desired access point
myBot.wifiConnect(ssid, pass);
// set the telegram bot token
myBot.setTelegramToken(token);
// check if all things are ok
if (myBot.testConnection()) {
Serial.println("\nWiFi Connected");
digitalWrite(led_wifi, LOW);
}
else
Serial.println("\nWiFi Not Connected");
}
void sendTelegramMessage()
{
Serial.println("Kirim pesan ke Telegram");
delay(200);
String message = "Sensor mendeteksi objek ....";
message.concat("\n");
message.concat("WASPADA !!!");
message.concat("\n");
if(myBot.sendMessage(chat_id, message)){
Serial.println("Pesan telah dikirim ke TELEGRAM");
delay(1000);
}
else Serial.println("gagal kirim..");
}
void loop() {
// SENSOR PIR
data = digitalRead(pir); // baca input dr Vout
if (data == HIGH) { // cek jika ada pergerakan
Serial.println("Sensor PIR Aktif");
sendTelegramMessage(); // nyalakan led indikator di board Arduino
Serial.println("Motion detected!"); //buat monitor ke laptop
digitalWrite(led_pir, LOW);
delay(1000);
digitalWrite(led_pir, HIGH);
delay(1000);
}
else {
digitalWrite(led_pir, HIGH);
}
// statusPIR = HIGH; //diset high spy tdk mendeteksi terus
// } else {
// if ((data == LOW) && (statusPIR == HIGH)){
// Serial.println("Motion ended!"); //buat monitor ke laptop
// statusPIR = LOW;
// }
// }
// KONTROL LAMPU
// a variable to store telegram message data
TBMessage msg;
// if there is an incoming message...
if (myBot.getNewMessage(msg)) {
// LED 1
if (msg.text.equalsIgnoreCase("l1 on")) { // if the received message is "l1 on"...
digitalWrite(led1, LOW); // turn on the LED
myBot.sendMessage(msg.sender.id, "Lampu 1 Menyala"); // notify the sender
}
else if (msg.text.equalsIgnoreCase("l1 off")) { // if the received message is "l1 off"...
digitalWrite(led1, HIGH); // turn off the led
myBot.sendMessage(msg.sender.id, "<NAME>"); // notify the sender
}
// LED 2
else if (msg.text.equalsIgnoreCase("l2 on")) { // if the received message is "l2 on"...
digitalWrite(led2, LOW); // turn on the LED
myBot.sendMessage(msg.sender.id, "<NAME>"); // notify the sender
}
else if (msg.text.equalsIgnoreCase("l2 off")) { // if the received message is "l2 off"...
digitalWrite(led2, HIGH); // turn off the led
myBot.sendMessage(msg.sender.id, "<NAME>"); // notify the sender
}
// LED 3
else if (msg.text.equalsIgnoreCase("l3 on")) { // if the received message is "l3 on"...
digitalWrite(led3, LOW); // turn on the LED
myBot.sendMessage(msg.sender.id, "<NAME>"); // notify the sender
}
else if (msg.text.equalsIgnoreCase("l3 off")) { // if the received message is "l3 off"...
digitalWrite(led3, HIGH); // turn off the led
myBot.sendMessage(msg.sender.id, "<NAME>"); // notify the sender
}
// LED 4
else if (msg.text.equalsIgnoreCase("l4 on")) { // if the received message is "l4 on"...
digitalWrite(led4, LOW); // turn on the LED
myBot.sendMessage(msg.sender.id, "<NAME>"); // notify the sender
}
else if (msg.text.equalsIgnoreCase("l4 off")) { // if the received message is "l4 off"...
digitalWrite(led4, HIGH); // turn off the led
myBot.sendMessage(msg.sender.id, "<NAME>"); // notify the sender
}
// ALL LED 4
else if (msg.text.equalsIgnoreCase("all on")) { // if the received message is "l4 on"...
digitalWrite(led1, LOW);
digitalWrite(led2, LOW);
digitalWrite(led3, LOW);
digitalWrite(led4, LOW); // turn on the LED
myBot.sendMessage(msg.sender.id, "<NAME>"); // notify the sender
}
else if (msg.text.equalsIgnoreCase("all off")) { // if the received message is "l4 off"...
digitalWrite(led1, HIGH);
digitalWrite(led2, HIGH);
digitalWrite(led3, HIGH);
digitalWrite(led4, HIGH); // turn off the led
myBot.sendMessage(msg.sender.id, "<NAME>"); // notify the sender
}
else { // otherwise...
// generate the message for the sender
String reply;
reply = (String)"Welcome " + msg.sender.username + (String)". Try l1 on or l1 off.";
myBot.sendMessage(msg.sender.id, reply); // and send it
}
}
// wait 500 milliseconds
delay(500);
}
| 5bf6540ffe5021b406cedb3fca2b5923c66eeb9a | [
"C++"
] | 1 | C++ | rvllfil/smarthouse | 706b7dbc47b43a9359e262f4599711219e3c4398 | 384f3ff92a98f39cce2f1ec7a4f4cd8aa0a6c61d |
refs/heads/master | <file_sep>using System;
namespace ReturnTest
{
class ReturnTest
{
static double CalculateArea(int r)
{
double area = r * r * Math.PI;
return area;
}
static void Main(string[] args)
{
string s = Console.ReadLine();
int radious = int.Parse(s);
Console.WriteLine($"The area is {CalculateArea(radious)}");
}
}
}
| 3a6e12e60875cf811659e4e5349008feaa2e1dc3 | [
"C#"
] | 1 | C# | SoumayKantiDas/ReturnTest | d6555764efa91501c2be929e426c8264ae8206f7 | e3251a581531d426de25f51980c46f53e6efab5e |
refs/heads/main | <repo_name>SoftArch/ROS2-Devcontainer<file_sep>/.devcontainer/Dockerfile
FROM dorowu/ubuntu-desktop-lxde-vnc:focal
LABEL maintainer="SoftArch<<EMAIL>>"
ENV DEBIAN_FRONTEND noninteractive
RUN echo "Set disable_coredump false" >> /etc/sudo.conf
RUN echo "Acquire::Check-Valid-Until \"false\";\nAcquire::Check-Date \"false\";" | cat > /etc/apt/apt.conf.d/10no--check-valid-until
RUN apt-get update -q && \
apt-get upgrade -yq && \
apt-get install -yq wget curl git build-essential vim sudo lsb-release locales bash-completion tzdata gosu && \
rm -rf /var/lib/apt/lists/*
RUN useradd --create-home --home-dir /home/ubuntu --shell /bin/bash --user-group --groups adm,sudo ubuntu && \
echo ubuntu:ubuntu | chpasswd && \
echo "ubuntu ALL=(ALL) NOPASSWD:ALL" >> /etc/sudoers
COPY ./setup/ros-foxy-desktop.sh /ros-foxy-desktop.sh
RUN mkdir -p /tmp/ros_setup_scripts_ubuntu && mv /ros-foxy-desktop.sh /tmp/ros_setup_scripts_ubuntu/ && \
gosu ubuntu /tmp/ros_setup_scripts_ubuntu/ros-foxy-desktop.sh && \
rm -rf /var/lib/apt/lists/*
ENV USER ubuntu<file_sep>/workspace/simple_app/src/drive_test/drive_test/drive.py
import rclpy
from rclpy.node import Node
from lgsvl_msgs.msg import VehicleControlData, SignalArray
class Drive(Node):
def __init__(self):
self.go = False
super().__init__('drive')
self.publisher_ = self.create_publisher(VehicleControlData, '/lgsvl/vehicle_control_cmd', 10)
timer_period = 0.1 # seconds
self.timer = self.create_timer(timer_period, self.timer_callback)
self.i = 0
# Subscribe Signal Sensor
self.subscription = self.create_subscription(
SignalArray,
'/lgsvl/signal',
self.signal_callback,10)
def timer_callback(self):
msg = VehicleControlData()
if(self.go):
msg.acceleration_pct = 0.3
msg.braking_pct = 0.0
else:
msg.acceleration_pct = 0.0
msg.braking_pct = 0.7
self.publisher_.publish(msg)
self.get_logger().info('Publishing %d' % self.i)
self.i += 1
def signal_callback(self, msg):
if(len(msg.signals) > 0):
self.go = msg.signals[0].label == "green"
def main(args=None):
rclpy.init(args=args)
drive = Drive()
rclpy.spin(drive)
# Destroy the node explicitly
# (optional - otherwise it will be done automatically
# when the garbage collector destroys the node object)
drive.destroy_node()
rclpy.shutdown()
if __name__ == '__main__':
main()
<file_sep>/README.md
# ROS2-Devcontainer
ROS2 Codesapce with lgsvl-bridge
| a25dd829e506f85bdcb0fd1a3cf3c8944d497cf6 | [
"Markdown",
"Python",
"Dockerfile"
] | 3 | Dockerfile | SoftArch/ROS2-Devcontainer | 3db2e51ecf79a54b4428b593a3a7dc16dfa1b4c9 | 4a06c3584aaaef1d36aca5661bb049d6d0d9b80b |
refs/heads/master | <repo_name>raiavincent/Speedtest<file_sep>/piSpeedtest.py
import speedtest
from datetime import datetime
import pandas as pd
s = speedtest.Speedtest()
megabit = 1000000
speedDict = {}
today = datetime.today()
date = today.strftime("%m/%d/%y")
dayOfWeek = today.strftime('%A')
print(dayOfWeek)
now = datetime.now()
currentTime = now.strftime("%H:%M:%S")
print(currentTime)
print(date)
# currentMonth = datetime.now().month
currentMonth = now.strftime('%B')
print(currentMonth)
dayOfMonth = datetime.today().day
print(dayOfMonth)
currentYear = now.year
print(currentYear)
currentHour = now.hour
print(currentHour)
print('Getting your speeds, hot rod.')
download = s.download()
upload = s.upload()
downloadMbps = round(download/megabit,1)
uploadMbps = round(upload/megabit,1)
print('My download speed is:', downloadMbps,'Mbps.')
print('My upload speed is:', uploadMbps,'Mbps.')
# speedDict['Now'] = now # considering dropping bc a) it gets truncated and b) its not entirely necessary
speedDict['Time'] = currentTime
speedDict['Month'] = currentMonth
speedDict['Weekday'] = dayOfWeek
speedDict['Day'] = dayOfMonth
speedDict['Year'] = currentYear
speedDict['Hour'] = currentHour
speedDict['Download'] = downloadMbps
speedDict['Upload'] = uploadMbps
print(speedDict)
speedColumns = ['Time','Month','Weekday','Day','Year','Hour','Download','Upload']
df = pd.DataFrame(columns=speedColumns)
df = df.append(speedDict,ignore_index=True)
print(df)
df.to_csv('Test file.csv')<file_sep>/piSpeedtestSchedule.py
import speedtest
from datetime import datetime
import pandas as pd
import schedule
import time
s = speedtest.Speedtest()
megabit = 1000000
speedColumns = ['Time','Month','Weekday','Day','Year','Hour','Download','Upload']
df = pd.DataFrame(columns=speedColumns)
def getSpeeds():
speedDict = {}
today = datetime.today()
date = today.strftime("%m/%d/%y")
dayOfWeek = today.strftime('%A')
now = datetime.now()
currentTime = now.strftime("%H:%M:%S")
currentMonth = now.strftime('%B')
dayOfMonth = datetime.today().day
currentYear = now.year
currentHour = now.hour
print('Getting your speeds, hot rod.')
download = s.download()
upload = s.upload()
downloadMbps = round(download/megabit,1)
uploadMbps = round(upload/megabit,1)
print('My download speed is:', downloadMbps,'Mbps.')
print('My upload speed is:', uploadMbps,'Mbps.')
speedDict['Time'] = currentTime
speedDict['Month'] = currentMonth
speedDict['Weekday'] = dayOfWeek
speedDict['Day'] = dayOfMonth
speedDict['Year'] = currentYear
speedDict['Hour'] = currentHour
speedDict['Download'] = downloadMbps
speedDict['Upload'] = uploadMbps
global df
df = df.append(speedDict,ignore_index=True)
dateString = datetime.strftime(datetime.now(), '%Y_%m_%d')
df.to_csv('Speeds as of ' + dateString + '.csv')
print('Speeds gathered, dataframe updated, saved to csv.')
schedule.every(15).minutes.do(getSpeeds)
while True:
schedule.run_pending()
time.sleep(1)<file_sep>/requirements.txt
schedule==0.6.0
pandas==0.25.3
speedtest_cli==2.1.2
speedtest==0.0.1
| 71b5aacd840b6853a0480b0126cfac4e9cb3c9ba | [
"Python",
"Text"
] | 3 | Python | raiavincent/Speedtest | f0918478f7198a322322de8bb98c5870ed3e2b12 | 5e0534a091b45318871ad54bcad5201c35d78f2c |
refs/heads/master | <repo_name>torenunez/ExData_Plotting1<file_sep>/plot2.R
#---------------------------------------------------------------------------------------------------
# Coursera - <NAME> School of Public Health
# Exploratory Data Analysis
#---------------------------------------------------------------------------------------------------
# Description: Course Project 1 - Plot 2
# Student: <NAME>
# Created: 2015-08-09
#---------------------------------------------------------------------------------------------------
##---------------------------------------------------------------------------
## Setup
##---------------------------------------------------------------------------
library(lubridate)
##---------------------------------------------------------------------------
## Load Data
##---------------------------------------------------------------------------
all_power_data = read.table(
file = "household_power_consumption.txt",
header = TRUE,
sep = ";",
)
##---------------------------------------------------------------------------
## Clean Data
##---------------------------------------------------------------------------
power_data <- all_power_data[all_power_data$Date %in% c("1/2/2007","2/2/2007"),]
power_data[power_data=="?"] <- NA
power_data$Date <- as.Date(power_data$Date, "%d/%m/%Y")
power_data$Time <- ymd_hms(paste(as.character(power_data$Date),as.character(power_data$Time)))
cols <- seq(3,9)
power_data[,cols] <- apply(power_data[,cols], 2, function(x) as.numeric(x))
##---------------------------------------------------------------------------
## Plot Data
##---------------------------------------------------------------------------
##reset in case working betweeen plots
par(mfrow = c(1,1))
##plot
with(power_data, plot(Time, Global_active_power, type = "l", xlab = NA, ylab = "Global Active Power (kilowatts)"))
##out to device
dev.copy(png, file = "plot2.png")
dev.off()
<file_sep>/plot1.R
#---------------------------------------------------------------------------------------------------
# Coursera - <NAME> School of Public Health
# Exploratory Data Analysis
#---------------------------------------------------------------------------------------------------
# Description: Course Project 1 - Plot 1
# Student: <NAME>
# Created: 2015-08-09
#---------------------------------------------------------------------------------------------------
##---------------------------------------------------------------------------
## Load Data
##---------------------------------------------------------------------------
all_power_data = read.table(
file = "household_power_consumption.txt",
header = TRUE,
sep = ";",
)
##---------------------------------------------------------------------------
## Clean Data
##---------------------------------------------------------------------------
power_data <- all_power_data[all_power_data$Date %in% c("1/2/2007","2/2/2007"),]
power_data[power_data=="?"] <- NA
power_data$Date <- as.Date(power_data$Date, "%d/%m/%Y")
power_data$Time <- ymd_hms(paste(as.character(power_data$Date),as.character(power_data$Time)))
cols <- seq(3,9)
power_data[,cols] <- apply(power_data[,cols], 2, function(x) as.numeric(x))
##---------------------------------------------------------------------------
## Plot Data
##---------------------------------------------------------------------------
##reset in case working betweeen plots
par(mfrow = c(1,1))
##plot
hist(
power_data$Global_active_power,
col = "red",
xlab = "Global Active Power (kilowatts)",
main = "Global Active Power"
)
##out to device
dev.copy(png, file = "plot1.png")
dev.off()
<file_sep>/plot3.R
#---------------------------------------------------------------------------------------------------
# Coursera - <NAME> School of Public Health
# Exploratory Data Analysis
#---------------------------------------------------------------------------------------------------
# Description: Course Project 1 - Plot 3
# Student: <NAME>
# Created: 2015-08-09
#---------------------------------------------------------------------------------------------------
##---------------------------------------------------------------------------
## Setup
##---------------------------------------------------------------------------
library(lubridate)
##---------------------------------------------------------------------------
## Load Data
##---------------------------------------------------------------------------
all_power_data <- read.table(
file = "household_power_consumption.txt",
header = TRUE,
sep = ";",
)
##---------------------------------------------------------------------------
## Clean Data
##---------------------------------------------------------------------------
power_data <- all_power_data[all_power_data$Date %in% c("1/2/2007","2/2/2007"),]
power_data[power_data=="?"] <- NA
power_data$Date <- as.Date(power_data$Date, "%d/%m/%Y")
power_data$Time <- ymd_hms(paste(as.character(power_data$Date),as.character(power_data$Time)))
cols <- seq(3,9)
power_data[,cols] <- apply(power_data[,cols], 2, function(x) as.numeric(x))
##---------------------------------------------------------------------------
## Plot Data
##---------------------------------------------------------------------------
##reset in case working betweeen plots
par(mfrow = c(1,1))
##plot
with(power_data, plot(Time, Sub_metering_1, type = "n", xlab = NA, ylab = "Energy sub metering"))
with(power_data, lines(Time, Sub_metering_1, col = "black"))
with(power_data, lines(Time, Sub_metering_2, col = "red"))
with(power_data, lines(Time, Sub_metering_3, col = "blue"))
legend(x = "topright", legend = c("Sub_metering_1","Sub_metering_2","Sub_metering_3"), col = c("black","red","blue"), lty = 1, cex = 0.7)
##out to device
dev.copy(png, file = "plot3.png")
dev.off()
| a372d3a8b3c76f2f88427a78dc2dd7bb7356d23f | [
"R"
] | 3 | R | torenunez/ExData_Plotting1 | da1557b63062c436217493d1563b455fdef0a1d6 | 91e75d114f4da8fed2de6055ffa01293b9523177 |
refs/heads/master | <repo_name>sushamajarange/MyFirstRailsApp<file_sep>/app/views/statuses/show.json.jbuilder
json.extract! @status, :id, :name, :sontent, :created_at, :updated_at
| 97ffec3e971e8fc2cb78b6040d3f98ada8fcbbe7 | [
"Ruby"
] | 1 | Ruby | sushamajarange/MyFirstRailsApp | f913871f51ee3642a5919ac2c10586b6581e8556 | a15f4106b26920298c66e49250e81cf8a5cd4920 |
refs/heads/main | <repo_name>keansteeves/test2<file_sep>/testing.R
testing
testing
ksdse
sdfsddfgsdgf
sdfgsdfg | 3e63ddd806e3903d9fd28ababb0d55c76b6516a6 | [
"R"
] | 1 | R | keansteeves/test2 | f49de9b89beda242ffd117d6ba21e447d82b2e6d | 8762fb0d66fef8c27d7cf504ac37ab0f83a5b74e |
refs/heads/master | <file_sep>package com.calculator.impl;
import com.calculator.*;
import org.junit.Before;
import org.junit.Test;
import static org.junit.Assert.assertEquals;
import static org.junit.Assert.assertNull;
public class TestDefaultVwapCalculator {
private static final double EPSILON = 0.000001d;
private DefaultVwapCalculator vwapCalculator;
@Before
public void setUp() {
vwapCalculator = new DefaultVwapCalculator();
}
@Test
public void testCalculatingVwapPriceFollowTheFormula() {
// First update for instrument0 from market0
MarketUpdate marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, 1000);
TwoWayPrice twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, 1000);
// Second update for instrument0 from market1
marketUpdate = createMarketDataUpdate(Market.MARKET1, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 2000, 2000);
// Third update for instrument0 from market49
marketUpdate = createMarketDataUpdate(Market.MARKET49, Instrument.INSTRUMENT0, State.FIRM, 0.11, 0.21, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.FIRM, 0.103333, 0.203333, 3000, 3000);
// First update for instrument19 from market10
marketUpdate = createMarketDataUpdate(Market.MARKET10, Instrument.INSTRUMENT19, State.FIRM, 0.1, 0.2, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT19, State.FIRM, 0.1, 0.2, 1000, 1000);
// Second update for instrument19 from market11
marketUpdate = createMarketDataUpdate(Market.MARKET11, Instrument.INSTRUMENT19, State.FIRM, 0.1, 0.2, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT19, State.FIRM, 0.1, 0.2, 2000, 2000);
// Third update for instrument19 from market41
marketUpdate = createMarketDataUpdate(Market.MARKET41, Instrument.INSTRUMENT19, State.FIRM, 0.11, 0.21, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT19, State.FIRM, 0.103333, 0.203333, 3000, 3000);
}
@Test
public void testOnlyTheLatestMarketUpdateTakesEffect() {
// First update for instrument0 from market0
MarketUpdate marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, 1000);
TwoWayPrice twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, 1000);
// Second update for instrument0 from market1
marketUpdate = createMarketDataUpdate(Market.MARKET1, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 2000, 2000);
// third update for instrument0 from market0 again, the first update shall no longer take effect
marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, State.FIRM, 0.11, 0.21, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.FIRM, 0.105, 0.205, 2000, 2000);
}
@Test
public void testResultIsIndicativeIfAnyMarketUpdateIsIndicative() {
// First update for instrument0 from market0, state is firm
MarketUpdate marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, 1000);
TwoWayPrice twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, 1000);
// Second update for instrument0 from market1, state is indicative
marketUpdate = createMarketDataUpdate(Market.MARKET1, Instrument.INSTRUMENT0, State.INDICATIVE, 0.1, 0.2, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.INDICATIVE, 0.1, 0.2, 2000, 2000);
// third update for instrument0 from market0 again, state is indicative
marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, State.INDICATIVE, 0.11, 0.21, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.INDICATIVE, 0.105, 0.205, 2000, 2000);
// Fourth update for instrument0 from market1, state is firm, but expect the result is still indicative
marketUpdate = createMarketDataUpdate(Market.MARKET1, Instrument.INSTRUMENT0, State.FIRM, 0.11, 0.21, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.INDICATIVE, 0.11, 0.21, 2000, 2000);
// third update for instrument0 from market0 again, state is firm, expect the result state changes back to firm
marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
verifyTwoWayPrice(twoWayPrice, Instrument.INSTRUMENT0, State.FIRM, 0.105, 0.205, 2000, 2000);
}
/**
* Just for reference of the exercise, System output is:
* Invalid market update - MockedMarketUpdate{market=null, twoWayPrice=DefaultTwoWayPrice{instrument=INSTRUMENT0, state=FIRM, bidPrice=0.1, offerPrice=0.2, bidAmount=1000.0, offerAmount=1000.0}}
* Invalid market update - MockedMarketUpdate{market=MARKET0, twoWayPrice=null}
* Invalid market update - MockedMarketUpdate{market=MARKET0, twoWayPrice=DefaultTwoWayPrice{instrument=null, state=FIRM, bidPrice=0.1, offerPrice=0.2, bidAmount=1000.0, offerAmount=1000.0}}
* Invalid market update - MockedMarketUpdate{market=MARKET0, twoWayPrice=DefaultTwoWayPrice{instrument=INSTRUMENT0, state=null, bidPrice=0.1, offerPrice=0.2, bidAmount=1000.0, offerAmount=1000.0}}
* Invalid market update - MockedMarketUpdate{market=MARKET0, twoWayPrice=DefaultTwoWayPrice{instrument=INSTRUMENT0, state=FIRM, bidPrice=NaN, offerPrice=0.2, bidAmount=1000.0, offerAmount=1000.0}}
* Invalid market update - MockedMarketUpdate{market=MARKET0, twoWayPrice=DefaultTwoWayPrice{instrument=INSTRUMENT0, state=FIRM, bidPrice=0.1, offerPrice=0.0, bidAmount=1000.0, offerAmount=1000.0}}
* Invalid market update - MockedMarketUpdate{market=MARKET0, twoWayPrice=DefaultTwoWayPrice{instrument=INSTRUMENT0, state=FIRM, bidPrice=0.1, offerPrice=0.2, bidAmount=-1000.0, offerAmount=1000.0}}
* Invalid market update - MockedMarketUpdate{market=MARKET0, twoWayPrice=DefaultTwoWayPrice{instrument=INSTRUMENT0, state=FIRM, bidPrice=0.1, offerPrice=0.2, bidAmount=1000.0, offerAmount=NaN}}
*/
@Test
public void testInvalidMarketUpdateReturnNull() {
// Input market is null
MarketUpdate marketUpdate = createMarketDataUpdate(null, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, 1000);
TwoWayPrice twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
assertNull(twoWayPrice);
// Input TwoWayPrice is null
marketUpdate = new MockedMarketUpdate(Market.MARKET0, null);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
assertNull(twoWayPrice);
// Input instrument is null
marketUpdate = createMarketDataUpdate(Market.MARKET0, null, State.FIRM, 0.1, 0.2, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
assertNull(twoWayPrice);
// Input state is null
marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, null, 0.1, 0.2, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
assertNull(twoWayPrice);
// Input bidPrice is NaN
marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, State.FIRM, Double.NaN, 0.2, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
assertNull(twoWayPrice);
// Input offerPrice is 0
marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.0, 1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
assertNull(twoWayPrice);
// Input bidAmount is negative
marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, -1000, 1000);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
assertNull(twoWayPrice);
// Input offerAmount is NaN
marketUpdate = createMarketDataUpdate(Market.MARKET0, Instrument.INSTRUMENT0, State.FIRM, 0.1, 0.2, 1000, Double.NaN);
twoWayPrice = vwapCalculator.applyMarketUpdate(marketUpdate);
assertNull(twoWayPrice);
}
private MarketUpdate createMarketDataUpdate(Market market,
Instrument instrument,
State state,
double bidPrice,
double offerPrice,
double bidAmount,
double offerAmount) {
DefaultTwoWayPrice twoWayPrice = new DefaultTwoWayPrice();
twoWayPrice.setInstrument(instrument);
twoWayPrice.setState(state);
twoWayPrice.setBidPrice(bidPrice);
twoWayPrice.setOfferPrice(offerPrice);
twoWayPrice.setBidAmount(bidAmount);
twoWayPrice.setOfferAmount(offerAmount);
return new MockedMarketUpdate(market, twoWayPrice);
}
private void verifyTwoWayPrice(TwoWayPrice twoWayPrice,
Instrument instrument,
State state,
double bidPrice,
double offerPrice,
double bidAmount,
double offerAmount) {
assertEquals(instrument, twoWayPrice.getInstrument());
assertEquals(state, twoWayPrice.getState());
assertEquals(bidPrice, twoWayPrice.getBidPrice(), EPSILON);
assertEquals(offerPrice, twoWayPrice.getOfferPrice(), EPSILON);
assertEquals(bidAmount, twoWayPrice.getBidAmount(), EPSILON);
assertEquals(offerAmount, twoWayPrice.getOfferAmount(), EPSILON);
}
}
<file_sep>package com.calculator.impl;
import com.calculator.*;
/**
* Default implementation of VWAP two-way price for input {@link MarketUpdate}
*
* For any given market, only the most recent price should be included in the VWAP calculation.
* The process calling applyMarketUpdate() must be single threaded.
* If any one MarketUpdate used in deriving the VWAP is indicative, the calculated TwoWayPrice should also be marked as indicative, otherwise it is firm.
*
* The VWAP two-way price for an instrument is defined as:
* Bid = Sum(Market Bid Price * Market Bid Amount)/ Sum(Market Bid Amount)
* Offer = Sum(Market Offer Price * Market Offer Amount)/ Sum(Market Offer Amount)
*/
public class DefaultVwapCalculator implements Calculator {
private final Instrument[] INSTRUMENTS = Instrument.values();
private final SingleInstrumentVwapCalculator[] singleInstrumentCalculators = new SingleInstrumentVwapCalculator[INSTRUMENTS.length];
private final StringBuilder errorBuilder = new StringBuilder();
public DefaultVwapCalculator() {
for (int i=0;i<singleInstrumentCalculators.length;i++) {
singleInstrumentCalculators[i] = new SingleInstrumentVwapCalculator(INSTRUMENTS[i]);
}
}
@Override
public TwoWayPrice applyMarketUpdate(final MarketUpdate twoWayMarketPrice) {
if (!isValidMarketUpdate(twoWayMarketPrice)){
// Due to lack of context in this exercise so I simply handle the exception case with System.out.println().
// And I assume the implementation of MarketUpdate has rewritten toString() properly.
// In real world we can choose to log error/throw exception/raise system alert, etc., according to the context.
errorBuilder.setLength(0);
errorBuilder.append("Invalid market update - ").append(twoWayMarketPrice);
System.out.println(errorBuilder.toString());
return null;
}
Instrument instrument = twoWayMarketPrice.getTwoWayPrice().getInstrument();
return singleInstrumentCalculators[instrument.ordinal()].calculate(twoWayMarketPrice);
}
/**
* Validate the MarketUpdate. Consider price and amount shall always be positive. One-sided market is not valid.
* @param twoWayMarketPrice
* @return
*/
boolean isValidMarketUpdate(MarketUpdate twoWayMarketPrice) {
if (twoWayMarketPrice == null || twoWayMarketPrice.getMarket() == null) {
return false;
}
TwoWayPrice price = twoWayMarketPrice.getTwoWayPrice();
return price != null
&& price.getInstrument() != null
&& price.getState() != null
&& (!Double.isNaN(price.getBidPrice()) && price.getBidPrice() > 0.0d)
&& (!Double.isNaN(price.getOfferPrice()) && price.getOfferPrice() > 0.0d)
&& (!Double.isNaN(price.getBidAmount()) && price.getBidAmount() > 0.0d)
&& (!Double.isNaN(price.getOfferAmount()) && price.getOfferAmount() > 0.0d);
}
/**
* The VWAP two-way price calculator for each instrument
* Assume input {@link MarketUpdate} is validated and always on the same instrument
*/
private class SingleInstrumentVwapCalculator {
private final MutableTwoWayPrice result = new DefaultTwoWayPrice();
// cache for market updates which are currently taking effect
private final MutableTwoWayPrice[] marketPriceCache = new MutableTwoWayPrice[Market.values().length];
private double bidPriceAmountSum = 0.0d;
private double bidAmountSum = 0.0d;
private double offerPriceAmountSum = 0.0d;
private double offerAmountSum = 0.0d;
// counter for indicative market, if positive then result state is INDICATIVE
private int indicativeCounter = 0;
SingleInstrumentVwapCalculator(Instrument instrument) {
result.setInstrument(instrument);
for (int i=0;i<marketPriceCache.length;i++) {
marketPriceCache[i] = new DefaultTwoWayPrice();
}
}
TwoWayPrice calculate(final MarketUpdate marketUpdate) {
TwoWayPrice marketPriceUpdate = marketUpdate.getTwoWayPrice();
MutableTwoWayPrice lastMarketPrice = marketPriceCache[marketUpdate.getMarket().ordinal()];
bidAmountSum = bidAmountSum - lastMarketPrice.getBidAmount() + marketPriceUpdate.getBidAmount();
offerAmountSum = offerAmountSum - lastMarketPrice.getOfferAmount() + marketPriceUpdate.getOfferAmount();
bidPriceAmountSum = bidPriceAmountSum - lastMarketPrice.getBidPrice() * lastMarketPrice.getBidAmount()
+ marketPriceUpdate.getBidPrice() * marketPriceUpdate.getBidAmount();
offerPriceAmountSum = offerPriceAmountSum - lastMarketPrice.getOfferPrice() * lastMarketPrice.getOfferAmount()
+ marketPriceUpdate.getOfferPrice() * marketPriceUpdate.getOfferAmount();
if (marketPriceUpdate.getState() != lastMarketPrice.getState()) {
indicativeCounter = marketPriceUpdate.getState() == State.INDICATIVE ? indicativeCounter + 1 : indicativeCounter - 1;
}
lastMarketPrice.copy(marketPriceUpdate);
result.setBidPrice(bidPriceAmountSum/bidAmountSum);
result.setOfferPrice(offerPriceAmountSum/offerAmountSum);
result.setBidAmount(bidAmountSum);
result.setOfferAmount(offerAmountSum);
result.setState(indicativeCounter > 0 ? State.INDICATIVE : State.FIRM);
return result;
}
}
}
<file_sep>package com.calculator;
public enum Side {
BID,
OFFER
}
<file_sep>package com.calculator.impl;
import com.calculator.Instrument;
import com.calculator.State;
import com.calculator.TwoWayPrice;
/**
* An extended mutable interface from {@link TwoWayPrice} to allow modifying of the price properties.
*/
public interface MutableTwoWayPrice extends TwoWayPrice {
void setInstrument(Instrument instrument);
void setState(State state);
void setBidPrice(double bidPrice);
void setOfferPrice(double offerPrice);
void setBidAmount(double bidAmount);
void setOfferAmount(double offerAmount);
void copy(TwoWayPrice copyFrom);
}
<file_sep>package com.calculator;
public enum State {
FIRM,
INDICATIVE
}
<file_sep>package com.calculator;
/**
* The VWAP twp way price calculator for instrument of the {@link MarketUpdate} passed in
*/
public interface Calculator {
/**
* @param twoWayMarketPrice is the MarketUpdate input
* @return The VWAP twp way price calculator for instrument of the input
*/
TwoWayPrice applyMarketUpdate(final MarketUpdate twoWayMarketPrice);
}
<file_sep>package com.calculator.impl;
import com.calculator.Market;
import com.calculator.MarketUpdate;
import com.calculator.TwoWayPrice;
/**
* Simple implementation for {@link MarketUpdate} for test use
*/
public class MockedMarketUpdate implements MarketUpdate {
Market market;
MutableTwoWayPrice twoWayPrice;
MockedMarketUpdate(Market market, MutableTwoWayPrice twoWayPrice){
this.market = market;
this.twoWayPrice = twoWayPrice;
}
@Override
public Market getMarket() {
return market;
}
@Override
public TwoWayPrice getTwoWayPrice() {
return twoWayPrice;
}
@Override
public String toString() {
return "MockedMarketUpdate{" +
"market=" + market +
", twoWayPrice=" + twoWayPrice +
"}";
}
}
| 82cebee52046fb430494ee5b3d7e9f77d323be68 | [
"Java"
] | 7 | Java | czf86123/VWAPCalculator | 32d1acd3a6511b63280cbcbf7a8e8adfc993526a | f9500e4a7f3bfb733ea8ce139643f12f0a6234f2 |
refs/heads/master | <repo_name>Rishabh-1999/Web-Development-Examples<file_sep>/AJAX/scipt.js
var data=[];
var table=document.getElementById('table');
var xhr=new XMLHttpRequest();
xhr.open("GET","https://api.github.com/users?since=1",true);
xhr.onload=function()
{
var dataString=xhr.responseText;
data=JSON.parse(dataString);
console.log(data);
for(i in data)
{
addToDom(data[i]);
}
xhr.send();
}
function addToDom(obj)
{
var tr1=document.createElement('tr');
var td0=document.createElement('img');
td0.setAttribute("src",obj.avatar_url);
td0.setAttribute("style","width:200px; height:200px;");
tr1.appendChild(td0);
var td1=document.createElement('td');
td1.innerHTML=obj.login;
tr1.appendChild(td1);
var td2=document.createElement('td');
td2.innerHTML=obj.id;
tr1.appendChild(td2);
var td3=document.createElement('td');
var a1=document.createElement('a');
a1.setAttribute("href",obj.html_url);
a1.innerHTML=obj.html_url;
td3.append(a1);
tr1.appendChild(td3);
var td4=document.createElement('td');;
var a2=document.createElement('a');
a2.setAttribute("href",obj.html_url);
a2.innerHTML=obj.html_url;
td4.append(a2);
tr1.appendChild(td4);
table.appendChild(tr1);
}<file_sep>/Counter-Using-HTML-CSS-JS/README.md
### Counter_Using_HTML_CSS_JS
<br>
<h4>A stop watch or Counter made from HTML , CSS and JavaScript .<h4>
<br><br>
<img src="https://user-images.githubusercontent.com/38128234/56496474-35a26880-6517-11e9-9903-4cec42b5f6b0.jpg" width="250px" height="250px">
<h4 align="right">Made By Rishabh</h4>
<file_sep>/Manage Product/showProduct-js.js
var cart=[];
var cartID=1;
var products=[];
var productId=1;
var loginName;
function load() { //onload function
var tempArrayProducts = localStorage.getItem("Products");
loginName=sessionStorage.getItem("currentAccount_name");
if(loginName==null)
{
window.open ('login.html','_self',false)
}
else
console.log("login success");
var tempArrayCart = localStorage.getItem(loginName+"Carts");
document.getElementById('login_h1').innerHTML="Hi, "+loginName;
if(tempArrayProducts!=null)
{
products = JSON.parse(tempArrayProducts);
for(var i=0;i<products.length;i++)
{
addtoListDOM(products[i]);
}
productId=products.length+1;
}
if(tempArrayCart!=null)
{
cart= JSON.parse(tempArrayCart);
cartID=cart.length;
}
console.log(products);
}
var logout=document.getElementById('logout');
logout.addEventListener("click",function()
{
sessionStorage.setItem("currentAccount_name",null);
sessionStorage.setItem("currentAccount_emailid",null);
window.open ('login.html','_self',false);
});
// Function to display show product
var divTableProducts = document.getElementById("tableShowProduct");
function addtoListDOM(objProduct) {
var tr1=document.createElement('tr');
var td1=document.createElement('td');
td1.setAttribute("id","productId"+productId);
td1.innerHTML=objProduct.Id;
tr1.appendChild(td1);
var td2=document.createElement('td');
td2.innerHTML=objProduct.Name;
td2.setAttribute("id","productName"+productId);
tr1.appendChild(td2);
var td3=document.createElement('td');
td3.innerHTML=objProduct.Price;
td3.setAttribute("id","productPrice"+productId);
tr1.appendChild(td3);
var td4=document.createElement('td');
td4.setAttribute("id","productInput"+productId);
var input=document.createElement('input');
input.setAttribute("type","textbox");
input.setAttribute("id","input"+productId);
td4.appendChild(input);
tr1.appendChild(td4);
var td5=document.createElement('td');
var btn=document.createElement('button');
btn.innerHTML="Add to cart";
btn.setAttribute("id","btn" +productId);
td5.appendChild(btn);
tr1.appendChild(td5);
btn.addEventListener("click",function(event)
{
var selectedProductIndex = td1.innerHTML;
console.log(selectedProductIndex);
addToCartArray(selectedProductIndex);
});
divTableProducts.appendChild(tr1);
productId++;
}
function addToCartArray(selectedProductIndex) {
var objProduct = new Object();
objProduct.Id = cartID;
var id=document.getElementById("productId"+selectedProductIndex).innerHTML;
objProduct.Name = document.getElementById("productName"+selectedProductIndex).innerHTML;
objProduct.Price = document.getElementById("productPrice"+selectedProductIndex).innerHTML;
var quantity=document.getElementById("input"+selectedProductIndex);
objProduct.Quantity = document.getElementById("input"+selectedProductIndex).value;
quantity.value="";
cart.push(objProduct);
var temp = JSON.stringify(cart);
localStorage.setItem(loginName+"Carts", temp);
cartID++;
update(id,quantity);
}
function update(id,q)
{
var new1=products[id-1];
new1.Quantity=new1.Quantity-q;
products[id-1]=new1;
var temp = JSON.stringify(products);
localStorage.setItem("Products", temp);
}<file_sep>/MOUSE EVENT/Move object using mouse-js.js
var body=document.getElementById('bb');
var box=document.getElementById('input1');
box.addEventListener("mousemove",function(event)
{
box.setAttribute("style","background-color: green");
console.log(1);
});
body.addEventListener("mousemove",function(event)
{
var x=event.pageY+'px';
var y=event.pageX+'px';
box.setAttribute("style",`top: ${x}; left: ${y}`);
console.log(box);
});
box.addEventListener("mouseout",function(event){
box.setAttribute("style","background-color: red;color:black");
console.log(2);
});<file_sep>/BMI-Calculator-HTML/README.md
# BMI-Calculator-HTML
webpage to find BMI of adult Person
Features
---------
- Open Source
- Help to find BMI of **Adult Person**
- Calculation done Using Data from trusted website.
Data
----
> Data is According to Adult and taken from trusted website.
<h3 align="right">Made By Rishabh</h3>
<file_sep>/TODO LIST/TODO LIST USING ON ENTER-js.js
var parent = document.getElementById("list");
var input = document.getElementById("data");
input.onkeyup=function add(event) {
var code=event.keyCode;
console.log(code);
if(code==13)
{
if(input.value=="")
alert("Enter value");
else
{
var ele = document.createElement("LI");
var btn=document.createElement("button");
btn.setAttribute("style","float:right;");
var value=input.value;
ele.innerHTML=value;
btn.innerHTML="-";
parent.appendChild(ele);
ele.appendChild(btn);
btn.onclick=function()
{
parent.removeChild(ele);
}
input.value="";
}
}
}<file_sep>/README.md
# Web Development Example
These are few Web page model I did while learning web development.
<file_sep>/Snake-Game-Web/README.md
# Snake-Game-HTML
Simple But Classic Snake Game Using **JavaScript** in Web.
How To Use ?
------------
- Open or Run _Game.html_
- Start the game by Entering Keyword 'Up' or _'Arrow Up'_
- Use _'Arrow Up'_ to Move upward , _'Arrow left'_ to move left , _'Arrow right'_ to move Right and _'Arrow down'_ to move Down
- Collect the food items to increase Score by 10 each
- Enjoy the Game
Instructions
------------
- Up -> _'Arrow Up'_
- Left -> _'Arrow left'_
- Right -> _'Arrow right'_
- Down -> _'Arrow Down'_
Preview
---------
<img src="https://user-images.githubusercontent.com/38128234/61591149-a7ef1b80-abe0-11e9-9562-cea5203c1207.jpg">
<file_sep>/Counter-Using-HTML-CSS-JS/js/script.js
var inputTime = document.getElementById('inputTime');
var btn_play = document.getElementById('btn_play');
var btn_pause = document.getElementById('btn_pause');
var time=0;
var interval;
// Function to add 10 sec in timmer
inputTime.addEventListener("click",function() {
time=time+10;
inputTime.setAttribute("value",time);
});
// Function to start timmer
btn_play.addEventListener("click",function() {
time--;
interval = setInterval(function() {
inputTime.setAttribute("value",time);
time--;
if(time==-1){
alert("Time UP!");
time=0;
inputTime.setAttribute("value","0");
clearInterval(interval);
}
},1000);
});
// Function to perform pause or reset Timmer
btn_pause.addEventListener("click",function(){
inputTime.setAttribute("value","0");
time=0;
console.log(time);
clearInterval(interval);
});
<file_sep>/Manage Product/login-js.js
var tempLogin=[];
var resg=document.getElementById("register");
var login_div=document.getElementById("login_div");
// Function onload
function load() {
resg.setAttribute("style", "visibility : hidden;");
var m = localStorage.getItem("login");
if(m!=null)
tempLogin = JSON.parse(m);
}
var changedisplay=document.getElementById("changedisplay");
changedisplay.addEventListener("click",function()
{
resg.setAttribute("style", "visibility : visible;");
login_div.setAttribute("style", "visibility : hidden;");
});
//Function on login button
var btn=document.getElementById("login_btn");
btn.addEventListener("click", function()
{
var login_userid=document.getElementById("login_userid").value;
var login_password=document.getElementById("login_password").value;
if(tempLogin!=null)
{
var i;
for(i=0;i<tempLogin.length;i++)
{
if(tempLogin[i].userid==login_userid)
{
if(tempLogin[i].password==<PASSWORD>)
{
var ObjCurrentAccount = new Object();
ObjCurrentAccount.username=tempLogin[i].username;
ObjCurrentAccount.userid=tempLogin[i].userid;
ObjCurrentAccount.password=tempLogin[i].password;
sessionStorage.setItem("currentAccount_name",ObjCurrentAccount.username);
sessionStorage.setItem("currentAccount_emailid",ObjCurrentAccount.userid);
window.open ('showProduct.html','_self',false);
return ;
//console.log(ObjCurrentAccount);
}
else
{
alert("Password is incorrect");
return ;
}
}
}
if(i==tempLogin.length)
alert("Check your details");
}
else
{
alert("register first");
}
});
//Function on Register Button
var resgister_btn=document.getElementById("resgister_btn");
resgister_btn.addEventListener("click",function()
{
var register_name=document.getElementById("register_name").value;
var register_userid=document.getElementById("register_userid").value;
var register_password1=document.getElementById("register_password1").value;
var register_password2=document.getElementById("register_password2").value;
if(register_name=="" || register_userid=="" || register_password1=="" || register_password2=="")
{
alert("Check Details");
return ;
}
if(register_password1!=register_password2)
{
alert("Check Password");
}
else
{
var obj=new Object();
obj.username=register_name;
obj.userid=register_userid;
obj.password=<PASSWORD>;
tempLogin.push(obj);
var myJSON = JSON.stringify(tempLogin);
localStorage.setItem("login", myJSON);
resg.setAttribute("style", "visibility : hidden;");
login_div.setAttribute("style", "visibility : visible;");
}
});
<file_sep>/30DaysOfJS/Custom Video Player/scripts.js
const player = document.querySelector(".player");
const video = document.querySelector(".viewer");
const progressBar = document.querySelector(".progress");
const progressBarFilled = document.querySelector(".progress__filled")
const playBtn = document.querySelector(".toggle");
const sliders = document.querySelectorAll(".player__slider");
const skipBtns = document.querySelectorAll(".player__button");
let isMouseDown = false;
function handlePlay(e) {
if(video.paused)
video.play();
else
video.pause();
}
function updateBtn() {
playBtn.textContent = this.paused ? '►' : '❚ ❚';
}
function skipVideo(e) {
video.currentTime += parseFloat(this.dataset.skip);
}
function handleSlide() {
video[this.name] = this.value;
}
function updateProgress(e) {
video.currentTime = (e.offsetX / progressBar.offsetWidth) * video.duration;
}
function updateProgressBar() {
progressBarFilled.style.flexBasis = (video.currentTime / video.duration) * 100 + "%";
}
video.addEventListener("click", handlePlay);
playBtn.addEventListener("click", handlePlay);
video.addEventListener("play", updateBtn);
video.addEventListener("pause", updateBtn);
skipBtns.forEach(btn => btn.addEventListener("click", skipVideo))
sliders.forEach(slider => slider.addEventListener("change", handleSlide))
progressBar.addEventListener("click", updateProgress);
progressBar.addEventListener("mousedown", () => isMouseDown = true)
progressBar.addEventListener("mouseup", () => isMouseDown = false)
progressBar.addEventListener("mousemove", () => isMouseDown && updateProgress);
video.addEventListener('timeupdate', updateProgressBar); | aa44c66d533f39356360a73353e8998769302e62 | [
"JavaScript",
"Markdown"
] | 11 | JavaScript | Rishabh-1999/Web-Development-Examples | 95a01bc2507ddff297a97e35cebb8ee921868d1b | e6c79db9b3042a92feea9e55ff13961cda9ee7dd |
refs/heads/master | <file_sep>// import images from directory
import Mercedes1 from '../images/mercedes_1.jpg';
import Mercedes2 from '../images/mercedes_2.jpg';
import Mercedes3 from '../images/mercedes_3.jpg';
import Mercedes4 from '../images/mercedes_4.jpg';
import Internal1 from '../images/internal-1.jpg';
import Internal2 from '../images/internal-2.jpg';
// create const and export , array object images desc, title
export const images = [
{ title: "Mercedes 2022 - Mercedes 1:", desc: "Mercedes 2022, Car Sporting", img: Mercedes1 },
{ title: "Mercedes 2022 - Mercedes 2:", desc: "Mercedes 2022, Car Sporting", img: Mercedes2 },
{ title: "Mercedes 2022 - Mercedes 3:", desc: "Mercedes 2022, Car Sporting", img: Mercedes3 },
{ title: "Mercedes 2022 - Mercedes 4:", desc: "Mercedes 2022, Car Sporting", img: Mercedes4 },
{ title: "Mercedes 2022 - Internal-1:", desc: "Mercedes 2022 Internal Car", img: Internal1 },
{ title: "Mercedes 2022 - Internal-2:", desc: "Mercedes 2022 Internal Car", img: Internal2 },
]<file_sep>import React, { useState } from 'react'
import { BiLeftArrow, BiRightArrow } from 'react-icons/bi'
import './Carousel.css'
import { images } from '../Helpers/CarouselData'
function Carousel() {
const [carImage, setCarImage] = useState(0)
return (
<div className="carousel">
<div className="__images" style={{ backgroundImage: `url(${images[carImage].img})` }}>
<div className="__left" onClick={() => { carImage > 0 && setCarImage (carImage - 1) }}>
<BiLeftArrow />
</div>
<div className="content">
<h1 className="__title">{images[carImage].title}</h1>
<p className="__desc">{images[carImage].desc}</p>
</div>
<div className="__right" onClick={() => { carImage < images.length - 1 && setCarImage (carImage + 1) }}>
<BiRightArrow />
</div>
</div>
</div>
)
}
export default Carousel | fe2e0108add0d36e32fe32bf5240a08319064e28 | [
"JavaScript"
] | 2 | JavaScript | rodrigosantosdev/Carousel-Reactjs | c6c48a923f8e9d19f2d0e20a3faf5a0cf023f2f7 | 6aa06b297954be8e96f16aea43f52dda078e2f3a |
refs/heads/master | <file_sep>package com.example.europe2012;
import java.util.ArrayList;
import java.util.HashMap;
import java.util.List;
import android.app.Activity;
import android.app.AlertDialog;
import android.content.DialogInterface;
import android.content.DialogInterface.OnClickListener;
import android.os.Bundle;
import android.view.Menu;
import android.view.View;
import android.widget.AdapterView;
import android.widget.AdapterView.OnItemClickListener;
import android.widget.ExpandableListView;
import android.widget.ImageView;
import android.widget.ListView;
import android.widget.SimpleAdapter;
import com.example.read_xml.data.XMLParser2;
import com.example.read_xml.entity.Europe2012;
public class MainActivity extends Activity {
private ListView listView=null;
private List<HashMap<String, String>>imgsHashMaps=null;
private Europe2012 europe2012=null;
@Override
protected void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.activity_main);
//从XML数据读取欧洲杯信息
XMLParser2 parser=XMLParser2.getInstance(MainActivity.this);
europe2012 = parser.getEurope2012();
//获取国家名字
String[] countryStrings=getResources().getStringArray(R.array.country);
/**
* 通过名字获取资源id
*
* getResources().
public int getIdentifier (String name, String defType, String defPackage)
*/
imgsHashMaps=new ArrayList<HashMap<String,String>>();
for (int i = 0; i <countryStrings.length; i+=4) {
HashMap<String, String>map=new HashMap<String, String>();
for (int j = 0; j < 4; j++) {
map.put("icon_"+(j+1),countryStrings[i+j]);
map.put("name_"+(j+1),countryStrings[i+j]);
}
imgsHashMaps.add(map);
}
listView=(ListView) findViewById(R.id.main_listView);
/**
* layout:R.layout.listlayout
* "icon":R.id.imageView1
* "name":R.id.textView1
*/
SimpleAdapter simpleAdapter=
new SimpleAdapter
(
this, imgsHashMaps,
R.layout.activity_main_listview,
new String[]{
"icon_1","name_1",
"icon_2","name_2",
"icon_3","name_3",
"icon_4","name_4"},
new int[]{
R.id.imageView1_1,R.id.textView1_1,
R.id.imageView1_2,R.id.textView1_2,
R.id.imageView2_1,R.id.textView2_1,
R.id.imageView2_2,R.id.textView2_2}
)
{
@Override
public void setViewImage(ImageView v, String value) {
// TODO Auto-generated method stub
super.setViewImage(v, value);
//res文件夹下的drawable文件夹里有 名字为 value.toLowerCase()的资源
int rsId=MainActivity.this.getResources().getIdentifier(value.toLowerCase(), "drawable", MainActivity.this.getPackageName());
v.setBackgroundResource(rsId);
}
};
listView.setAdapter(simpleAdapter);
listView.setOnItemClickListener(new OnItemClickListener() {
@Override
public void onItemClick(AdapterView<?> arg0, View arg1, int arg2,
long arg3) {
// TODO Auto-generated method stub
//为对话框创建ExpandableListView
ExpandableListView expandableListView=new ExpandableListView(MainActivity.this);
EuropeCupExpandableListViewAdapter adapter=new EuropeCupExpandableListViewAdapter(MainActivity.this,europe2012.getGroups().get(arg2));
expandableListView.setAdapter(adapter);
//绑定ExpandableListView子项的点击事件
AlertDialog.Builder builder=new AlertDialog.Builder(MainActivity.this);
builder.setView(expandableListView)
.setIcon(R.drawable.ic_menu_largetiles)
.setTitle("EuropeCup Group "+europe2012.getGroups().get(arg2).getName());
final AlertDialog groupDetailDialog=builder.create();
groupDetailDialog.setButton(DialogInterface.BUTTON_POSITIVE, "确定", new OnClickListener() {
@Override
public void onClick(DialogInterface dialog, int which) {
// TODO Auto-generated method stub
groupDetailDialog.dismiss();
}
});
groupDetailDialog.show();
}
});
}
@Override
public boolean onCreateOptionsMenu(Menu menu) {
// Inflate the menu; this adds items to the action bar if it is present.
getMenuInflater().inflate(R.menu.main, menu);
return true;
}
}
<file_sep>package com.example.read_xml.entity;
public class Team {
private String name=null;
private String A=null;
private String D=null;
private String F=null;
private String L=null;
private String Pts=null;
private String W=null;
public String getName() {
return name;
}
public void setName(String name) {
this.name = name;
}
public String getA() {
return A;
}
public void setA(String a) {
A = a;
}
public String getD() {
return D;
}
public void setD(String d) {
D = d;
}
public String getF() {
return F;
}
public void setF(String f) {
F = f;
}
public String getL() {
return L;
}
public void setL(String l) {
L = l;
}
public String getPts() {
return Pts;
}
public void setPts(String pts) {
Pts = pts;
}
public String getW() {
return W;
}
public void setW(String w) {
W = w;
}
}
<file_sep>package com.example.read_xml.entity;
import java.util.ArrayList;
import java.util.HashMap;
public class Group {
private String name=null;
private ArrayList<Team> teams=null;
private ArrayList<Game>games=null;
private HashMap<String, ArrayList<Game>> searchBufferHashMap=null;
public String getName() {
return name;
}
public void setName(String name) {
this.name = name;
}
public ArrayList<Team> getTeams() {
return teams;
}
public void setTeams(ArrayList<Team> teams) {
this.teams = teams;
}
public ArrayList<Game> getGames() {
return games;
}
public void setGames(ArrayList<Game> games) {
this.games = games;
}
public Game getLastGame()
{
if (games.size()==0) {
return null;
}
return games.get(games.size()-1);
}
public ArrayList<Game>findGamesByTeamName(String name)
{
if (searchBufferHashMap==null) {
searchBufferHashMap=new HashMap<String, ArrayList<Game>>();
}
ArrayList<Game>returnGames=searchBufferHashMap.get(name);
if (returnGames==null) {
returnGames=new ArrayList<Game>();
for (Game game : this.games) {
if (game.getHome_name().equals(name)||game.getAway_name().equals(name)) {
returnGames.add(game);
}
}
searchBufferHashMap.put(name, returnGames);
}
return returnGames;
}
}
<file_sep>package com.example.read_xml.entity;
import android.widget.ListView;
import android.widget.TextView;
public class GameListViewHolder {
public TextView textView=null;
public ListView homePlayerListView=null;
public ListView awayPlayerListView=null;
}
<file_sep>EuropeCup2012
=============
android EuropeCup2012
Related Post : http://haozi.freetzi.com/software/android/513.html
Author : haozi
Url : http://haozi.freetzi.com
College : China University Of Geoscience 中国地质大学（武汉）
<file_sep>package com.example.read_xml.data;
import java.io.IOException;
import java.util.ArrayList;
import org.xmlpull.v1.XmlPullParserException;
import android.content.Context;
import android.content.res.XmlResourceParser;
import com.example.europe2012.R;
import com.example.read_xml.entity.Away;
import com.example.read_xml.entity.Europe2012;
import com.example.read_xml.entity.Game;
import com.example.read_xml.entity.Group;
import com.example.read_xml.entity.Home;
import com.example.read_xml.entity.Player;
import com.example.read_xml.entity.Team;
public class XMLParser2 {
private static XMLParser2 instance=null;
private static XmlResourceParser parser=null;
private Europe2012 europe2012=null;
private XMLParser2(Context context)
{
parser=context.getResources().getXml(R.xml.europe_cup);
}
public static XMLParser2 getInstance(Context context)
{
if (instance==null) {
instance=new XMLParser2(context);
}
return instance;
}
public Europe2012 getEurope2012()
{
if (europe2012==null) {
try {
String name=null;
boolean isHome=false;
while (parser.getEventType()!=XmlResourceParser.END_DOCUMENT) {
if (parser.getEventType()==XmlResourceParser.START_TAG) {
name=parser.getName();
if (name.equals("europe_cup")) {
europe2012=new Europe2012();
ArrayList<Group>groups=new ArrayList<Group>();
europe2012.setGroups(groups);
}
else if (name.equals("group")) {
Group group =new Group();
ArrayList<Team>teams=new ArrayList<Team>();
ArrayList<Game>games=new ArrayList<Game>();
group.setName(parser.getAttributeValue(null, "name"));
group.setGames(games);
group.setTeams(teams);
europe2012.getGroups().add(group);
}
else if (name.equals("team")) {
Team team=new Team();
team.setA(parser.getAttributeValue(null, "A"));
team.setD(parser.getAttributeValue(null, "D"));
team.setF(parser.getAttributeValue(null, "F"));
team.setL(parser.getAttributeValue(null, "L"));
team.setName(parser.getAttributeValue(null, "name"));
team.setPts(parser.getAttributeValue(null, "Pts"));
team.setW(parser.getAttributeValue(null, "W"));
europe2012.getLastGroup().getTeams().add(team);
}
else if (name.equals("game")) {
Game game=new Game();
Home home=new Home();
Away away = new Away();
game.setAway_name(parser.getAttributeValue(null, "away"));
game.setHome_name(parser.getAttributeValue(null, "home"));
game.setDate(parser.getAttributeValue(null, "date"));
game.setResult(parser.getAttributeValue(null, "result"));
game.setAway(away);
game.setHome(home);
europe2012.getLastGroup().getGames().add(game);
}
else if (name.equals("home")) {
ArrayList<Player>players=new ArrayList<Player>();
europe2012.getLastGroup().getLastGame().getHome().setPlayers(players);
isHome=true;
}
else if (name.equals("away")) {
ArrayList<Player>players=new ArrayList<Player>();
europe2012.getLastGroup().getLastGame().getAway().setPlayers(players);
isHome=false;
}
else if (name.equals("player")) {
Player player=new Player();
player.setEvent(parser.getAttributeValue(null, "event"));
player.setName(parser.getAttributeValue(null, "name"));
player.setTime(parser.getAttributeValue(null, "time"));
if (isHome) {
europe2012.getLastGroup().getLastGame().getHome().getPlayers().add(player);
}
else {
europe2012.getLastGroup().getLastGame().getAway().getPlayers().add(player);
}
}
}
parser.next();
}
} catch (XmlPullParserException e) {
// TODO Auto-generated catch block
e.printStackTrace();
} catch (IOException e) {
// TODO Auto-generated catch block
e.printStackTrace();
}
}
return europe2012;
}
}
| 73648d24af006b9b31878f97dfe7d21766ae9cc4 | [
"Markdown",
"Java"
] | 6 | Java | haozzzzzzzz/EuropeCup2012 | 0d14b0533f9c61d716230fdaadcbd93e986abe22 | e01408a5d82fd447c4b7d1cfb9c1ef57cc46c2ce |
refs/heads/master | <file_sep>#include <fstream>
#include <vector>
#include <iostream>
#include <string>
#include <vector>
#include <unordered_map>
#include <unordered_set>
#include <iterator>
#include "data_parse.h"
using namespace std;
Parser::Parser(string stream_file){
packetNum = 0;
entryNum = 0;
ackNum = 0;
fillNum = 0;
ifstream is (stream_file, ios::in | ios::binary);
if(is){
is.seekg (0, is.end);
int length = is.tellg();
is.seekg (0, is.beg);
char * buffer = new char [length];
is.read (buffer,length);
string stream(buffer,length);
string marker = "ST";
string termination = "DBDBDBDB";
bool flag = true;
int i = 0;
while(i<length){
string start = stream.substr(i,2);
if(start.compare("ST")==0){
packetNum++;
i+=2;
int type = buffer[i];
i+=20;
switch(type){
case 1:
entryNum++;
handleEntryMessage(buffer, i);
break;
case 2:
ackNum++;
handleAckMessage(buffer, i);
break;
case 3:
fillNum++;
handleFillMessage(buffer, i);
break;
}
int found = stream.find(termination, i);//find termination
if(found!=string::npos){
i =found+8;
}
}else{
i++;
}
}
}
}
void Parser::handleFillMessage(char* buffer, int& begin){ //start from the positon of order_id of fill message
FillMessage fm;
int sumOfQty = 0;
fm.order_id = readALE(buffer, begin, 4);//read order id
begin+=8;
sumOfQty+=readALE(buffer,begin,4);
fm.fill_qty = sumOfQty;
int no_of_contras = buffer[begin++];
for(int k = 0; k < no_of_contras; k++){
begin+=4;
sumOfQty+=readALE(buffer,begin,4);
}
fm.qty=sumOfQty;
fillMessageList.push_back(fm);
}
void Parser::handleAckMessage(char* buffer, int& begin){//start from the position of order_id of ack message
unsigned int orderId = readALE(buffer, begin, 4);
unsigned long clientId = readALE(buffer, begin, 8);
order_client[orderId] = clientId;
order_status[orderId] = buffer[begin++];
}
void Parser::handleEntryMessage(char* buffer, int& begin){//start from the position of price of entry message
begin+=8;
EtryMessage entryMessage;
entryMessage.qty = readALE(buffer, begin, 4);
string instrument = "";
for(int k = 0; k < 10; k++){
instrument+=buffer[begin++];
}
int side = buffer[begin++];
unsigned long clientId = readALE(buffer, begin, 8);
unsigned int time_in_force = buffer[begin++];
string trader = "";
trader+=buffer[begin];
trader+=buffer[begin+1];
trader+=buffer[begin+2];
begin+=3;
entryMessage.instrument=instrument;
entryMessage.side=side;
entryMessage.client_id=clientId;
entryMessage.time_in_force=time_in_force;
entryMessage.trader=trader;
client_entry[clientId]=entryMessage;
}
/*read in Little-endian*/
unsigned long Parser::readALE(char* buffer, int& begin, int size){
int half = size/2;
unsigned long res = 0;
for(int k = half-1; k>=0; k--){
res+=buffer[begin+k];
if(k!=0)
res<<8;
}
begin+=half;
res<<(8*half);
unsigned long res_temp = 0;
for(int k = half-1; k>=0;k--){
res_temp+=buffer[begin+k];
if(k!=0)
res_temp<<8;
}
begin+=half;
res+=res_temp;
return res;
}
string Parser::mostActiveTrader(){
for(vector<FillMessage>::iterator itr = fillMessageList.begin(); itr!=fillMessageList.end();itr++){
unsigned int order_id = (*itr).order_id;
unsigned int qty = (*itr).qty;
unsigned long clientId = order_client[order_id];
string trader_tag = client_entry[clientId].trader;
if(trader_qty.count(trader_tag)>0){
trader_qty[trader_tag]+=qty;
}else{
trader_qty[trader_tag]=qty;
}
}
int largestFilledVolume = 0;
string mostActiveTrader="";
for(auto i=trader_qty.begin();i!=trader_qty.end();++i){
if(i->second>largestFilledVolume){
largestFilledVolume = i->second;
mostActiveTrader=i->first;
}
}
return mostActiveTrader;
}
string Parser::mostLiquidityTrader(){
for(auto itr = order_status.begin(); itr!=order_status.end();++itr){
if(itr->second==1){
unsigned long clientId = order_client[itr->first];
if(client_entry.count(clientId)>0&&client_entry[clientId].time_in_force==2){
if(trader_GFDvolume.count(client_entry[clientId].trader)>0){
trader_GFDvolume[client_entry[clientId].trader]+=client_entry[clientId].qty;
}else{
trader_GFDvolume[client_entry[clientId].trader]=client_entry[clientId].qty;
}
}
}
}
int largestGFDvolume = 0;
string mostLiquidityTrader = "";
for(auto i = trader_GFDvolume.begin();i!=trader_GFDvolume.end();++i){
if(i->second>largestGFDvolume){
largestGFDvolume = i->second;
mostLiquidityTrader = i->first;
}
}
return mostLiquidityTrader;
}
void Parser::tradesPerInstrument(){
for(vector<FillMessage>::iterator itr = fillMessageList.begin(); itr!=fillMessageList.end();itr++){
unsigned int order_id = (*itr).order_id;
unsigned int volume = (*itr).fill_qty;
unsigned long clientId = order_client[order_id];
string instrument = client_entry[clientId].instrument;
if(instrument_volume.count(instrument)>0){
instrument_volume[instrument]+=volume;
}else{
instrument_volume[instrument]=volume;
}
}
}
int Parser::getPacketNum(){
return this->packetNum;
}
int Parser::getEntryNum(){
return this->entryNum;
}
int Parser::getAckNum(){
return this->ackNum;
}
int Parser::getFillNum(){
return this->fillNum;
}
int main(int argc, char *argv[]){
if(argc>2||argc<2)
cout<<"please enter correct argument"<<endl;
else{
string file_stream = argv[1];
Parser parser(file_stream);//Q1,2
int total_packets = parser.getPacketNum();
int order_entry_msg_count = parser.getEntryNum();
int order_ack_msg_count = parser.getAckNum();
int order_fill_msg_count = parser.getFillNum();
string most_active_trader_tag = parser.mostActiveTrader();
string most_liquidity_trader_tag = parser.mostLiquidityTrader();
//printf("%u,%u,%u,%u,%s,&s",total_packets,order_entry_msg_count,order_ack_msg_count,order_fill_msg_count,most_active_trader_tag,most_liquidity_trader_tag);
cout<<total_packets<<", "<<order_entry_msg_count<<", "<<order_ack_msg_count<<", "<<order_fill_msg_count<<", "<<most_active_trader_tag<<", "<<most_liquidity_trader_tag<<", ";
parser.tradesPerInstrument();
for(auto itr = parser.instrument_volume.begin();itr!=parser.instrument_volume.end();++itr){
cout<<itr->first<<":"<<itr->second<<", ";
}
}
}<file_sep>#include <string>
using namespace std;
typedef struct{
string instrument;
unsigned int qty;//uint32
int side;//unit8 1=buy, 2=sell
unsigned long client_id;//uint64 *
unsigned int time_in_force;//uint8, 1=IOC, 2=GFD
string trader;
}EtryMessage;
typedef struct{
unsigned int order_id;//uint 32 *
unsigned long client_id;//uint 64
unsigned int order_status;//1=good, 2=reject
}AckMessage;
typedef struct{
unsigned int order_id;//uint 32 *
unsigned int qty;//uint 32
unsigned int fill_qty;
}FillMessage;
class Parser{
private:
int packetNum;
int entryNum;
int ackNum;
int fillNum;
vector<FillMessage> fillMessageList;
unordered_map<unsigned int,unsigned long> order_client;
unordered_map<unsigned long, EtryMessage> client_entry;
unordered_map<string, unsigned int>trader_qty;
unordered_map<unsigned int,unsigned int>order_status;
unordered_map<string, int>trader_GFDvolume;
void handleFillMessage(char* buffer, int& begin);
void handleAckMessage(char* buffer, int& begin);
void handleEntryMessage(char* buffer, int& begin);
public:
Parser(string stream_file);
unordered_map<string,unsigned int> instrument_volume;
static unsigned long readALE(char* buffer, int& begin, int size);
int getPacketNum();
int getEntryNum();
int getAckNum();
int getFillNum();
string mostActiveTrader();
string mostLiquidityTrader();
void tradesPerInstrument();
};
| 534404114286a36ec79bd7d08c4a49d186dd31be | [
"C++"
] | 2 | C++ | khuang2/data_parser | ed70e054a2f69be4b21dabe71274b4af3ada4323 | cd71d212ad437d40ca86a7e962b7636ddc5b3d79 |
refs/heads/master | <file_sep>LogoDetection
=============
CS6301 - Video Analytics - Real time object tracking and detection
###Description
---
This project was built using OpenCV Library and it can identify any person who is wearing a UT Dallas logo t-shirt in real-time video.
###Features
---
- Real time UT Dallas T-Shirt identification
- Tracking multiple humanbeings
- Displays the movement of the person wearing the T-shirt with UT Dallas logo
<file_sep>// Final Project - I
//People detection - Using HOG and SIFT/SURF
#include <stdio.h>
#include <iostream>
#include <opencv2/opencv.hpp>
#include "opencv2/core/core.hpp"
#include "opencv2/features2d/features2d.hpp"
#include <opencv2/nonfree/nonfree.hpp>
#include "opencv2/highgui/highgui.hpp"
#include "opencv2/imgproc/imgproc.hpp"
#include "opencv2/calib3d/calib3d.hpp"
#define FRAME_WIDTH 640
#define FRAME_HEIGHT 480
using namespace std;
using namespace cv;
int main(int argc, const char * argv[]) {
// load the UTD logo image here
Mat UTDlogo = imread("UTDLogo4.jpg", CV_LOAD_IMAGE_GRAYSCALE);
// detect key points using SURF
int minHessian = 500;
SiftFeatureDetector detector(minHessian);
vector<KeyPoint> logo_KeyPoint;
detector.detect(UTDlogo, logo_KeyPoint);
// calculate descriptors
SiftDescriptorExtractor extractor;
Mat logo_Descriptor;
extractor.compute(UTDlogo, logo_KeyPoint, logo_Descriptor);
FlannBasedMatcher matcher;
VideoCapture cap(0);
cap.set(CV_CAP_PROP_FRAME_WIDTH, FRAME_WIDTH);
cap.set(CV_CAP_PROP_FRAME_HEIGHT, FRAME_HEIGHT);
if (!cap.isOpened()) {
return -1;
}
// Use HOG's people detector to get a bounding box around the person on the live video capture
Mat img;
namedWindow("opencv", CV_WINDOW_AUTOSIZE);
HOGDescriptor hog;
hog.setSVMDetector(HOGDescriptor::getDefaultPeopleDetector());
vector<Point> centroidCollections;
Mat lastScene;
int counter = 0;
// keep capturing the video until esc key is pressed
while (true) {
cap >> img;
cap >> lastScene;
Mat person_Descriptor, person_matches;
vector<KeyPoint> person_KeyPoint;
vector<vector<DMatch> > matches;
vector<DMatch> good_matches;
if (img.empty())
continue;
// use the HOG's built in function to get a bounding box around the detected person
vector<Rect> found, found_filtered;
hog.detectMultiScale(img, found, 0, Size(4, 4), Size(32, 32), 1.05, 2);
size_t i, j;
for (i = 0; i < found.size(); i++) {
Rect r = found[i];
for (j = 0; j < found.size(); j++) {
if (j != i && (r & found[j]) == r)
break;
}
if (j == found.size())
found_filtered.push_back(r);
}
// store the detected person and store it in a Mat
Mat person;
// bounding box's top left and bottom right corner
int tl_x;
int tl_y;
int br_x;
int br_y;
// Detected person are stored in found_filtered
if (found_filtered.size() > 0) {
for (i = 0; i < found_filtered.size(); i++) {
Rect r = found_filtered[i];
r.x = r.x + cvRound(r.width * 0.1);
r.width = cvRound(r.width * 0.8);
r.y = r.y + cvRound(r.height * 0.07);
r.height = cvRound(r.height * 0.8);
// modify the bounding box
// if the detected person's bounding box is not drawn completely
// make changes to the top left corner or the bottom right corner
// co-ordinates
tl_x = r.tl().x;
tl_y = r.tl().y;
br_x = r.br().x;
br_y = r.br().y;
if (tl_x < 1) {
tl_x = 1;
}
if (tl_y < 1) {
tl_y = 1;
}
if (br_x > FRAME_WIDTH) {
br_x = FRAME_WIDTH;
}
if (br_y > FRAME_HEIGHT) {
br_y = FRAME_HEIGHT;
}
cout << "Filter size " << found_filtered.size() << endl;
cout << tl_x << "," << tl_y << " | " << br_x - tl_x << ","
<< br_y - tl_y << endl;
person = img(Rect(tl_x, tl_y, br_x - tl_x, br_y - tl_y));
// find cetroid of the person, which will be used later for drawing the path
Point rectCentroid;
rectCentroid.x = ((br_x - tl_y) / 2);
rectCentroid.y = ((br_y - tl_y) / 2);
Mat personGrayScale;
cvtColor(person, personGrayScale, CV_BGR2GRAY);
detector.detect(personGrayScale, person_KeyPoint);
extractor.compute(personGrayScale, person_KeyPoint, person_Descriptor);
// if the person descriptor is empty, go to the next frame
if (!(person_Descriptor.empty())) {
matcher.knnMatch(logo_Descriptor, person_Descriptor,
matches, 2);
for (int i = 0;
i
< min(person_Descriptor.rows - 1,
(int) matches.size()); i++) {
if ((matches[i][0].distance
< 0.7 * (matches[i][1].distance))
&& ((int) matches[i].size() <= 2
&& (int) matches[i].size() > 0)) {
good_matches.push_back(matches[i][0]);
}
}
cout << "Good Matches: " << good_matches.size() << endl;
if (good_matches.size() > 3) {
//draw a white rectangle around the person wearing the UTD Logo tShirt
rectangle(img, r.tl(), r.br(), Scalar(255, 255, 255),
3);
centroidCollections.push_back(rectCentroid);
} else {
// draw a green rectangle around the person
rectangle(img, r.tl(), r.br(), Scalar(0, 255, 0), 3);
}
} else {
cout << "Person Descriptor is empty !!!" << endl;
cout << "Skipping current frame" << endl;
}
}
}
imshow("opencv", img);
counter = counter + 1;
if (waitKey(10) >= 0)
break;
}
// trace the centroids to draw the path traversed by the person wearing the UTD logo tShirt
while (true) {
for (int i = 0; i < centroidCollections.size() - 1; i++) {
// draw i and i+1th point
Point a, b;
a.x = centroidCollections[i].x;
a.y = centroidCollections[i].y;
b.x = centroidCollections[i + 1].x;
b.y = centroidCollections[i + 1].y;
line(lastScene, a, b, Scalar(255, 255, 255), 3, 8, 0);
}
imshow("Traversed Path", lastScene);
if (waitKey(10) >= 0)
break;
}
return 0;
}
| af5a511a716b7e165c7a45ed0197c7ab381f78d2 | [
"Markdown",
"C++"
] | 2 | Markdown | yutuotuo/LogoDetection | e45403afdad573a1d94e6fcbd04e9f2ecbe328b6 | 3ee9a283fb2c22b571ffd0863e532db6bcaeca10 |
refs/heads/master | <file_sep># BDEadmin
BDE Administrator for dBase4Linux
<file_sep>#include <QMessageBox>
#include "mainwindow.h"
#include "ui_mainwindow.h"
#include "dialog.h"
#include "ui_dialog.h"
MainWindow::MainWindow(QWidget *parent) :
QMainWindow(parent),
ui(new Ui::MainWindow)
{
ui->setupUi(this);
ui->DefTable->setColumnWidth(0,142);
ui->DefTable->setColumnWidth(1,142);
}
MainWindow::~MainWindow()
{
delete ui;
}
void MainWindow::on_actionAbout_Qt_triggered()
{
QMessageBox::aboutQt(this);
}
void MainWindow::on_actionAbout_BDE_Administrator_triggered()
{
auto * dlg = new Dialog;
dlg->exec();
delete dlg;
}
| cd86120fe69e1d635c99816da8d3637d8d731488 | [
"Markdown",
"C++"
] | 2 | Markdown | paule32/BDEadmin | 9d8dd1a577e66c84a61f4a603e327aa5940f6478 | c0cb84f2ea3c0247891057200900a431966fd192 |
refs/heads/master | <repo_name>shanestockall/GenericPeerReviews<file_sep>/README.md
#Sending out Peer Reviews
1. Download Canvas Gradebook
2. Delete every column that isn't ID and Netid, save as gradebook.csv
3. Run fixroster.py in terminal
4. Download submissions from Canvas, unzip into ./submissions
5. Run peerreviews.py in terminal
6. You should now have a master.csv - this matches canvas ID to 3 other Canvas IDs -- peer reviewer to peer reviewees. In ./to_send there are now zipfiles with 3 other zipfiles, the containing zip is the canvas id of the reviewer, the 3 contained zips are the canvas ids of the reviewees.
7. Edit the globals EMAIL, PASSWORD, and ASSIGNMENT in senfiles.py to reflect the email you wish to send the email from and the assignment you're sending the review files from
8. It might be good to send a test email, replace recipient in line 53 with EMAIL. Run sendfiles.py, get through one loop of the code, and then ctrl+c to exit. You should now have an email with what the first person in the list will see.
9. Replace EMAIL with recipient in line 53 to send it to the class.
10. Run sendfiles.py in terminal
Congrats! You just sent peer reviews to everyone in the class. :) <file_sep>/fixroster.py
import pandas as pd
import json
import fileinput
import sys
def main():
for line in fileinput.input('./gradebook.csv', inplace=1):
sys.stdout.write(line.lower())
for line in fileinput.input('./caesarroster.csv', inplace=1):
sys.stdout.write(line.lower())
caesarCSV = open("./caesarroster.csv")
canvasCSV = open("./gradebook.csv")
a = pd.read_csv(caesarCSV)
b = pd.read_csv(canvasCSV)
merged = a.merge(b, on='netid')
merged.to_csv("roster.csv", index=False)
if __name__ == '__main__':
main()
<file_sep>/sendfiles.py
import smtplib
from os.path import basename
from email.mime.application import MIMEApplication
from email.mime.multipart import MIMEMultipart
from email.mime.text import MIMEText
from email.utils import COMMASPACE, formatdate
import os
import pandas
import time
# Your email and password here, as strings
EMAIL = ""
PASSWORD = ""
# The name of the assignment (e.g. Homework 1) - used in lines 55, 57
ASSIGNMENT = ""
def main():
roster = pandas.read_csv('roster.csv')
emails = list(roster.email)
student_ids = list(roster.id)
list_ids = []
for file in os.listdir('./tosend/'):
list_ids.append(file[1:-5])
student_ids = map(str, student_ids)
print list_ids
print student_ids
for student_id in list_ids:
if student_id in student_ids:
for student in student_ids:
if str(student) == student_id:
index = student_ids.index(student)
email = emails[index]
try:
print 'sending files to ' + str(email)
send_mail(email, student_ids[index])
except:
time.sleep(300)
list_ids.append(student_ids[index])
continue
def send_mail(recipient, id):
msg = MIMEMultipart()
msg['From'] = "EMAIL"
msg['To'] = recipient
msg['Date'] = formatdate(localtime=True)
msg['Subject'] = "Peer Reviews for " + ASSIGNMENT
text = "Hello, " + recipient[:-25] + ". Please find attached your peer reviews for " + ASSIGNMENT +". You should use the rubric and CSV template on Canvas to grade. These will be due " + DATE
msg.attach(MIMEText(text))
f = open("./tosend/_" + id + "_.zip", "rb")
part = MIMEApplication(
f.read(),
Name="./tosend/_" + id + "_.zip")
# After the file is closed
part['Content-Disposition'] = 'attachment; filename=%s' % str(id) + ".zip"
msg.attach(part)
s = smtplib.SMTP('smtp.gmail.com', 587)
s.ehlo()
s.starttls()
s.login("EMAIL", "<PASSWORD>")
s.sendmail("EMAIL", recipient, msg.as_string())
s.close()
if __name__ == '__main__':
main()
<file_sep>/peerreviews.py
import glob
import os
import csv
from zipfile import ZipFile
import re
import random
# get list of submissions
listFiles = glob.glob("./submissions/*.zip")
# initialize list of students
listStudents = []
# call a write file
writeFileName = "master.csv"
writeFile = open(writeFileName, 'w+')
writeFile.write("Grader ID, Peer Reviews \n")
random.shuffle(listFiles)
# rename to only include student id
for i in range(0, len(listFiles)):
file = listFiles[i]
print "file = " + str(file)
studentID = re.search("_[0-9]{4,6}_", str(file)).group(0)
# memoize student IDs, because we're good little programmers
listStudents.append(str(studentID))
print 'ID: ' + str(studentID)
os.rename(file, './submissions/' + str(studentID) + ".zip")
file = './submissions/' + str(studentID) + ".zip"
listFiles[i] = file
for i in range(0, len(listFiles)):
studentID = listStudents[i]
peerReviews = []
reviewFiles = []
# prep zip file
with ZipFile('./tosend/' + studentID + '.zip', 'w') as myZip:
# the case where the list wraps
if listStudents[i] == listStudents[-1]:
peerReviews = listStudents[0:3]
reviewFiles = listFiles[0:3]
elif listStudents[i] == listStudents[-2]:
peerReviews = listStudents[0:2] + [listStudents[i + 1]]
reviewFiles = listFiles[0:2] + [listStudents[i + 1]]
elif listStudents[i] == listStudents[-3]:
peerReviews = [listStudents[0]] + listStudents[i + 1: i + 3]
reviewFiles = [listFiles[0]] + listFiles[i + 1: i + 3]
# the list doesn't wrap
else:
peerReviews = listStudents[i+1:i+4]
reviewFiles = listFiles[i+1:i+4]
# write review files to zip archive
for file in reviewFiles:
try:
myZip.write(file)
# the last one throws an exception, but the file still gets made, so we can pass it
except Exception as e:
pass
myZip.close()
# add pairs to CSV for logging purposes
writeFile.write(studentID + ", " + str(peerReviews) + "\n")
| f6c35ba2c880af480d81bba137bc5b671e6a36b8 | [
"Markdown",
"Python"
] | 4 | Markdown | shanestockall/GenericPeerReviews | 8b77c2ec5867f441f648c7bbe20d8825938c46ef | 2692d9a1c768866400568c719f588e21cc307f3c |
refs/heads/master | <repo_name>adambabik/whac-a-mole<file_sep>/js/script.js
;(function () {
'use strict';
var app = angular.module('whacMole', []);
/**
* randomInt
* @return {Number} Random integer between 0 and 100
*/
function randomInt() {
return (Math.random() * 100) | 0;
}
/**
* Game Constructor
* @constructor
* @param {Object} $rootScope
*/
function Game($rootScope) {
this.$rootScope = $rootScope;
this._frameBound = this._frame.bind(this);
this._timeout = 0;
this.reset(true);
}
// length of a round
Game.TIMER = 30;
// update time in ms
Game.TM_FRAME = 1000;
// points for hitting a mole
Game.POINTS = 10;
/**
* Reset the state of the game
* @param {Boolean} hard tells whether it should be a reset of all props
*/
Game.prototype.reset = function (hard) {
clearTimeout(this._timeout);
this.running = false;
// score per round
this.score = 0;
// current level
this.level = 1;
this.timer = Game.TIMER;
this.moles = [
0, 0, 0,
0, 0, 0,
0, 0, 0
];
if (hard) {
this.overall = 0;
}
};
/**
* Start the logic of the game
*/
Game.prototype.start = function () {
this.running = true;
this._timeout = setTimeout(this._frameBound, Game.TM_FRAME);
};
/**
* Stop the logig of a game.
* Also trigger hard reset.
*/
Game.prototype.stop = function () {
this.reset(true);
};
/**
* Logic after hitting a mole.
* The mole must be visible.
* @param {Number} idx index of a mole
*/
Game.prototype.hit = function (idx) {
if (this.moles[idx]) {
this.moles[idx] = 0;
this.score += Game.POINTS;
}
};
/**
* Trigger one turn of a logic.
* @private
*/
Game.prototype._frame = function () {
this.timer -= 1;
this._logic();
this.$rootScope.$broadcast('game:tick');
if (this.running) {
this._timeout = setTimeout(this._frameBound, Game.TM_FRAME);
}
};
/**
* Main logic
* @private
*/
Game.prototype._logic = function () {
// number of visible mols
var out = this.moles.filter(function (mole) {
return mole;
}).length;
var n = 9,
idx = 0,
mole = 0,
show = 0;
while (n--) {
idx = randomInt() % 9;
mole = this.moles[idx];
// mole is out, check if it wants to hide
if (mole && out > 1 && randomInt() % 2) {
out -= 1;
this.moles[idx] = 0;
}
// mole is in, check if it wants to show
else if (!mole && out < 3 && randomInt() % 3 === 0) {
out += 1;
this.moles[idx] = 1;
}
}
var win, currLevel;
if (this.timer === 0) {
win = this.score >= this._limit();
currLevel = this.level;
this.overall += this.score;
this.$rootScope.$broadcast('game:result', win, this.score, this._limit(), currLevel, this.overall);
this.reset(!win);
if (win) {
this.level = currLevel + 1;
this.running = true;
}
}
};
/**
* Return limit of points per level.
* @return {Number}
*/
Game.prototype._limit = function () {
return (this.level + 1) * 5 * Game.POINTS;
};
// Define an instance of the game per $injetor.
app.factory('game', ['$rootScope', function ($rootScope) {
return new Game($rootScope);
}]);
/**
* ControlsCtrl
* Account for UI controls.
* @param {Object} $scope
* @param {Object} game
*/
function ControlsCtrl($scope, game) {
// Start or stop the game
$scope.startOrStop = function ($event) {
if (game.running) {
game.stop();
} else {
game.start();
}
};
}
ControlsCtrl.$inject = ['$scope', 'game'];
app.controller('ControlsCtrl', ControlsCtrl);
/**
* BoardCtrl
* @param {Object} $scope
* @param {Object} game
*/
function BoardCtrl($scope, game) {
$scope.hit = function ($index) {
game.hit($index);
};
}
BoardCtrl.$inject = ['$scope', 'game'];
app.controller('BoardCtrl', BoardCtrl);
/**
* GameCtrl
* @param {Object} $scope
* @param {Object} game
*/
function GameCtrl($scope, game) {
$scope.game = game;
// trigger UI update (if needed) after a tick of the game
$scope.$on('game:tick', function () {
$scope.$apply();
});
$scope.$on('game:result', function (event, win, score, limit, level, overall) {
$scope.$apply(function () {
if (win) {
alert("WIN! Got " + score + "!");
} else {
alert("LOSE! Got " + score + " of " + limit + " points in level " + level + "! Overall " + overall);
}
});
});
}
GameCtrl.$inject = ['$scope', 'game'];
app.controller('GameCtrl', GameCtrl);
// hole directive
app.directive('hole', function () {
return {
restrict: 'E',
template: '<div class="col-xs-4 hole">' +
'<div class="circle">' +
'<div class="mole" ng-show="show" ng-click="onHit({ $index: index })"></div>' +
'</div>' +
'</div>',
replace: true,
scope: {
show: '@',
index: '@',
onHit: '&'
}
};
});
}());
<file_sep>/README.md
whac-a-mole
===========
Whac-A-Mole powered by AngularJS. Sample application for article in Software Developer Journal.
| 8aad59d625bc1ef03125dfd0a32b8e4fdbb30fb9 | [
"JavaScript",
"Markdown"
] | 2 | JavaScript | adambabik/whac-a-mole | 74f293c9f1562e279413e6bec11cb07eb16c566f | ff4670e937caaea4db1e357cba4b43975cf76e10 |
refs/heads/master | <file_sep>#PHP-FlexPart
FlexPart is a lightweight PHP Framework without dependencies that works by assuming websites are made out of nested blocks. It helps development by making websites easily scalable, efficiently cacheable (fast), extremely dynamic, flexible, reliable and easy to debug.
There will be a repository to hold a fully operational website built with this framework, but currently it is not operational.
#Blocks
Each block is a html element that can have other blocks inside, as well as content. Each block has a XML configuration file which describes its behaviours and optionally it's style.
For example, a block on a page can be defined by the following configuration file:
````xml
<block>
<tag>div</tag> <!-- Optional, but that's the default value -->
<name>index</name>
<content>
<block>menu</block>
<block>body</block>
<block>footer</block>
</content>
</block>
````
The description above describes `div` block that instances 3 other blocks as its content, each of the instanced blocks will have their own configuration file. This block can be instanced in PHP by the following snippet:
````php
<?php
require_once __DIR__ . "/FlexPart/include.php"; // An include file that includes the framework
$config_dir = __DIR__ . "/FlexPart/config/";
$cache_dir = __DIR__ . "/FlexPart/cache/";
$log_file = __DIR__ . "/FlexPart/log.txt"; // Optional log file
$app = new \Rossato\FlexPart($config_dir, $cache_dir, $log_file);
echo $app->getPageFromBlock("index");
?>
````
Note that all nested blocks will also be interpreted and shown in the resulting file.
If we didn't use any styling in the blocks of our website, we could just use `$app->asHTML("index")` to get the block as HTML.
#Block tags and names
Each block is by default a <div> element. This can be reconfigured by the `tag` in the configuration, like so: `<tag>input</tag>`.
Block names are unique identifiers for blocks of a website and are used to instanciate a block.
If a block name is not specified, the filename (without the extension) will be used instead.
They are composed of letters, numbers, dots and slashes. Anything else will throw an InvalidBlockNameException during the parsing of the blocks.
If you specify styling in the configuration file, the classname of the block will be it's name (unless you overwrite this by configurating a specific classname).
Having the same name and classname is useful for debugging: If you need to edit a block, be it's structure or style, its classname will lead you to the file of the block.
#Block Content
Blocks can have either other blocks, raw text, associated files or all of these at the same time:
````xml
<block>
<name>block</name>
<content>
<raw>Hello world!<raw> <!-- This is mostly for tests and debugging only -->
<file>/../random-external-folder/index.php</file> <!-- There will be no caching for the 'index.php' file -->
<block>another-block</block>
</content>
</block>
````
Results into a content of:
````html
<div class="block">Hello world!
{{content of index.php file}}
<div class="another-block">content of another block</div>
</div>
````
The newlines were added for conveniance, they are not included in the real output.
#Style
The CSS namespace has a tendency to become polluted as projects grow and stylesheets can go up to thousands of lines in a project.
This framework introduces an **optional** way of organizing style that aims to move styling out of a general file and onto these configuration files, the framework then condenses this styling into a single file and is able to do css minifying and other cache-tricks to fasten the loading of a webpage.
A good grasp of CSS is advised to anyone using this framework, as it can be very useful.
##Conditional Styling
Suppose you have a webpage that must behave differently according to the device width:
````xml
<block><name>hello-world</name>
<style>
<default>
display: inline-block;
position: fixed;
width: 100px;
</default>
<desktop>
display: block;
width: auto;
top: 0;
</desktop>
<tablet>
top: 50%;
left: 0;
</tablet>
<mobile>
bottom: 0;
</mobile>
</style>
</block>
````
If we abstract the css compression that the framework does by default, we would be generating the following style file:
````css
/* Others blocks default definitions goes here */
.hello-world {
display: inline-block;
position: fixed;
width: 100px;
}
@media screen and (min-width: 900px) {
/* Others blocks desktop definitions goes here */
.hello-world {
display: block;
width: auto;
top: 0;
}
}
@media screen and (min-width: 500px) and (max-width: 900px) {
/* Others blocks tablet definitions goes here */
.hello-world {
top: 50%;
left: 0;
}
}
@media screen and (max-width: 500px) {
.hello-world {
bottom: 0;
}
}
````
It's also possible to configure raw style to be freely added onto the style file, for when you need to use selectors or any other new CSS specification unhandled by the framework:
````xml
<block>
<name>my-block</name>
<style>
<default>
display: flex;
</default>
<desktop>width: 400px;</desktop>
<tablet>width: 200px</mobile>
<raw>
.my-block::after:hover {
content: "Click me!";
}
</raw>
</style>
</block>
````
Alternatively, if you would rather create your own style file and manually put on the page, you must assign classes and/or ids to a block at its configuration file:
<style>
<name>my-block</name>
<class>my-class my-other-class</class>
<id>hello_world</id>
</style>
You must specify a class name because the block name is only used as the classname if you specify something in the `<style>` tag.
##Cache Invalidation
Everytime the style of a block is modified in a configuration file the cache files must be purged. This can be done manually by deleting the cache folder or programatically by the use of the `app->purgeCache()` method.
There is **no** automatic cache purging, the style is solid once it is generated and **MUST** be purged when necessary.
You can put the `purgeCache` method on your main index.php file during development to always purge the styling, BUT YOU MUST **NOT FORGET** THIS ON, as it will heavily influence website performance.
#Inspiration
I first say a need for this type of framework when I was working as a Magento developer. Magento is an E-commerce solution in which one of its aspect is a system that enables pages to be built in blocks, each calling other child blocks.
However, I wanted to extract that usefulnes and extend that into something simpler, more abstract and easier to use.
#License
Still working on it.<file_sep><?php
/*
* PHP-FlexPart (https://github.com/GuilhermeRossato/PHP-FlexPart)
* Licensed under the MIT License (https://opensource.org/licenses/MIT)
*/
namespace GuilhermeRossato\FlexPart;
require_once __DIR__ . '/Exceptions.php';
class Block {
public function __construct($name, $style) {
$this->name = $name;
$this->style = (object) array();
if ($style instanceof \SimpleXMLElement) {
foreach ($style as $root=>$value) {
if ($root === "style") {
foreach ($value as $index=>$value) {
if ($index == "default" || $index == "desktop" || $index == "tablet" || $index == "mobile" || $index == "custom") {
$this->style->$index = Block::minifyCssContent((string)$value);
} else {
trigger_error("Unhandled style child element \"{$index}\" on block \"{$name}\"", E_USER_ERROR);
}
}
} else {
echo "Can't handle {$root}<br>";
}
}
}
}
public static function minifyCssContent($content) {
$mode = 0;
$clean = preg_replace("/(\r\n|\t|\n|\r)/m","", $content);
$exploded = str_split($clean);
$filtered = "";
foreach($exploded as $char) {
if ($mode == 0 || $mode == 2 || $mode === 1) {
if ($mode === 1) {
$mode = 5;
} elseif ($char == ":") {
$mode = 1;
} elseif ($char === "/" && $mode === 0) {
$mode = 2;
} elseif ($char === "*" && $mode === 2) {
$mode = 3;
} elseif ($mode === 2) {
$mode = 0;
}
if ($char !== ' ') {
$filtered .= $char;
}
} elseif ($mode === 5) {
if ($char == ";") {
$mode = 0;
}
$filtered .= $char;
} elseif ($mode === 3 || $mode == 4) {
if ($char === "*" && $mode === 3) {
$mode = 4;
} else if ($char === "/" && $mode === 4) {
$mode = 0;
$filtered .= "/";
continue;
} else if ($mode === 4) {
$mode = 3;
}
$filtered .= $char;
}
};
return $filtered;
}
}<file_sep><?php
/*
* PHP-FlexPart (https://github.com/GuilhermeRossato/PHP-FlexPart)
* Licensed under the MIT License (https://opensource.org/licenses/MIT)
*/
namespace GuilhermeRossato\FlexPart;
class FGException extends \Exception {}
class FolderNotFoundException extends FGException {}
class CouldNotScanFolderException extends FGException {}
class CouldNotOpenFileException extends FGException {}
class InvalidBlockException extends FGException {}
<file_sep><?php
/*
* PHP-FlexPart (https://github.com/GuilhermeRossato/PHP-FlexPart)
* Licensed under the MIT License (https://opensource.org/licenses/MIT)
*/
namespace GuilhermeRossato\FlexPart;
require_once __DIR__ . '/Exceptions.php';
final class Parser {
//public fileSizeLimit = 1048576;
public function __construct() {
$this->fileSizeLimit = 1048576;
}
public function assign($file) {
$this->file = $file;
}
public function assert($condition, $errMessage = '') {
if (!$condition) {
throw new InvalidBlockException($errMessage." - Error while parsing {$this->file}");
}
}
public function assertBlock($b) {
$name = (string)$b->name;
$this->assert(!empty($name), "Block name must be defined");
$this->assert(is_string($name), "Block name must be a string");
$this->assert(!preg_match('/[^A-Za-z0-9\-\.]/', $name), "The only characters allowed on a block name are letters, numbers, commas and dots");
}
public function extractNameFromFile() {
return pathinfo($this->file, PATHINFO_FILENAME);
}
public function parse() {
$content = file_get_contents($this->file, null, null, null, $this->fileSizeLimit);
if (!$content) {
throw new CouldNotOpenFileException($file);
}
libxml_use_internal_errors(true);
$object = simplexml_load_string($content, null, LIBXML_NOBLANKS | LIBXML_NOEMPTYTAG | LIBXML_NONET);
if (!$object) {
throw new InvalidBlockException("Invalid XML structure for block for {$this->file}");
}
$object->fileName = $this->file;
if (!isset($object->name) || empty((string)$object->name))
$object->name = $this->extractNameFromFile($this->file);
$this->assertBlock($object);
$block = new Block((string) $object->name, $object->style);
return $block;
}
}<file_sep><?php
/*
* PHP-FlexPart (https://github.com/GuilhermeRossato/PHP-FlexPart)
* Licensed under the MIT License (https://opensource.org/licenses/MIT)
*/
namespace GuilhermeRossato\FlexPart;
require_once __DIR__ . '/Exceptions.php';
final class PageBuilder {
private $metas = array(
'<meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1">',
'<meta name="viewport" content="width=device-width, initial-scale=1.0">',
'<meta http-equiv="Content-Type" content="text/html; charset=utf-8">',
'<meta name="description" content="Internal Page">',
'<meta name="keywords" content="intranet internal page">',
'<meta name="robots" content="INDEX,FOLLOW">'
);
private $styles = array();
private $scripts = array();
private $name = "unnamed page";
public function __construct($name) {
$this->name = $name;
$this->lang = 'pt';
$this->bodyClass = 'index';
}
public function addMeta($str) {
array_push($this->metas, $str);
}
public function addStyle($link) {
array_push($this->styles, "<link href='{$link}' type='text/css' rel='stylesheet'>");
}
public function addScript($link) {
array_push($this->scripts, "<script type='text/javascript' src='{$link}'></script>");
}
private function getHtmlHead() {
$str = "<head>\n";
$str .= join("\n", $this->metas)."\n";
$str .= join("\n", $this->styles)."\n";
$str .= join("\n", $this->scripts)."\n";
$str .= "<title>{$this->name}</title>\n";
$str .= "</head>\n";
return $str;
}
private function getHtmlBody($content) {
return "<body class='{$this->bodyClass}'>\n{$content}\n</body>\n";
}
public function getHtml($content) {
$str = "<!DOCTYPE html>\n<html lang='{$this->lang}'>\n";
$str .= $this->getHtmlHead();
$str .= $this->getHtmlBody($content);
$str .= "</html>";
}
}<file_sep><?php
/*
* PHP-FlexPart (https://github.com/GuilhermeRossato/PHP-FlexPart)
* Licensed under the MIT License (https://opensource.org/licenses/MIT)
*/
namespace GuilhermeRossato\FlexPart;
require_once __DIR__ . '/Exceptions.php';
final class Controller {
public $minifyCss = false;
public $combineCss = false;
private $rootBlocks = array();
private $allBlocks = array();
public function __construct($layoutDir, $cacheDir) {
if (!is_dir($layoutDir)) {
throw new FolderNotFoundException($layoutDir);
}
if (isset($cacheDir) && !is_dir($cacheDir)) {
throw new FolderNotFoundException($cacheDir);
}
$this->layoutDir = $layoutDir;
$this->cacheDir = $cacheDir;
}
public function getLayout($blockName = 'root') {
}
public function generateStyleFile() {
$defaults = array();
$grouped = array();
foreach ($this->allBlocks as $block) {
foreach ($block->style as $index=>$style) {
if (!empty($style)) {
if ($index === "default") {
$defaults[] = ".{$block->name}{{$style}}";
} else {
if (!isset($grouped{$index}) || !is_array($grouped{$index})) {
$grouped{$index} = array();
}
$grouped{$index}[] = array(
'name' => $block->name,
'content' => $style
);
}
}
}
}
$fileContent = array();
$fileContent[] = "/* ALL EDITS ON THIS FILE WILL BE LOST ON STYLE CACHE PURGE */\n\n";
$fileContent[] = implode("\n",$defaults)."\n";
foreach ($grouped as $type=>$group) {
if ($type === "desktop") {
$fileContent[] = "@media (min-width: 760px) {\n";
} else if ($type === "tablet") {
$fileContent[] = "@media (min-width: 560px) and (max-width: 860px) {\n";
} else if ($type === "mobile") {
$fileContent[] = "@media (max-width: 560px) {\n";
} else {
$fileContent[] = "@media (max-width: 230px) {\n";
}
foreach ($group as $index=>$block) {
$fileContent[] = ".".$block["name"]."{".($block["content"])."}\n";
//$fileContent .= "block: {$block["name"]}\n";
}
$fileContent[] = "}\n";
}
echo "File to save: ".$this->cacheDir."/style.css<br>";
echo getcwd();
echo "<br>";
file_put_contents($this->cacheDir."/style.css", $fileContent);
//echo "<pre>".implode("",$fileContent)."</pre>";
}
public function process($hash = '') {
$files = $this->getDirectories($this->layoutDir);
$parser = new Parser();
foreach ($files as $file) {
$parser->assign($this->layoutDir.$file);
array_push($this->allBlocks, $parser->parse());
}
}
private function getDirectories($dir) {
$result = array();
$cdir = scandir($dir);
if (!$cdir) {
throw new CouldNotScanFolderException();
}
foreach ($cdir as $key => $value) {
if (!in_array($value,array(".",".."))) {
if (is_dir($dir . DIRECTORY_SEPARATOR . $value)) {
$result[$value] = dirToArray($dir . DIRECTORY_SEPARATOR . $value);
} else {
$result[] = $value;
}
}
}
return $result;
}
public function getAllBlocks() {
return $this->allBlocks;
}
}<file_sep><?php
require_once __DIR__ . '/src/Block.php';
require_once __DIR__ . '/src/Parser.php';
require_once __DIR__ . '/src/PageBuilder.php';
require_once __DIR__ . '/src/Controller.php'; | 84c1048a00b6666a0ec35686ffbb0105b2171163 | [
"Markdown",
"PHP"
] | 7 | Markdown | GuilhermeRossato/PHP-FlexPart | 1133b0c75f2e8b0e92133afb974bb5bd6be8ba3c | ba4df8e60c11e2479354ea8fa605f952beb30c44 |
refs/heads/master | <repo_name>rieskyams/TOS-1<file_sep>/TOS-A/lala.sh
python data.py | awk -F " : " '{print $1}' > nrp.txt
readarray nrp < nrp.txt
rm nrp.txt
el=${#nrp[@]}
cd 2016-09-08\:2016-09-14/
for (( i=0;i<el;i++)); do
nrp[$i]=${nrp[$i]:0:8}
if [ -d ${nrp[$i]} ]; then
cd ${nrp[$i]}
jum=$(git log --pretty=format:"%ad" --since=$1 --until=$2 | grep -c ".*")
cd ../
nilai=0
if [ $jum -gt 4 ];then
nilai=100
elif [ $jum -eq 4 ]; then
nilai=85
elif [ $jum -eq 3 ]; then
nilai=75
elif [ $jum -eq 2 ]; then
nilai=68
elif [ $jum -eq 1 ]; then
nilai=60
fi
echo ${nrp[$i]}-$nilai
echo ${nrp[$i]}-$nilai >> ../$1":"$2.txt
fi
done
| 53a30f8d33fdaba5e7c50b960c5c5f127878c2d6 | [
"Shell"
] | 1 | Shell | rieskyams/TOS-1 | 1f092030a51bcf1b24c8cd116e4f00e4437c7d80 | 5fdc2be2f40104d0f1b91de9bb32096822ea2e2e |
refs/heads/main | <file_sep>import { Component, OnInit } from '@angular/core';
import { HttpClient } from '@angular/common/http';
import { Router } from '@angular/router';
@Component({
selector: 'app-form',
templateUrl: './form.component.html',
styleUrls: ['./form.component.css']
})
export class FormComponent implements OnInit {
requestResult: any;
error: boolean = false;
errorAlertText: string;
constructor(private http: HttpClient, private _router: Router) { }
ngOnInit(): void {
localStorage.clear();
}
submitForm(event: any, email: string, password: string): void {
event.preventDefault();
const requestUrl: string = 'https://core.nekta.cloud/api/auth/login';
const requestBody: object = { email: email.trim(), password: <PASSWORD>(), personal_data_access: true };
if (email.trim() != '' && password.trim() != '') {
this.http.post(requestUrl, requestBody)
.subscribe((result) => {
this.error = false;
this.requestResult = result;
localStorage.setItem('access_token', this.requestResult.data.access_token);
this._router.navigate(['list']);
},
error => {
this.error = error;
this.errorAlertText = 'Что-то пошло не так...';
}
);
} else {
this.error = true;
this.errorAlertText = 'Заполните поля.';
}
}
}
<file_sep>import { Component, OnInit } from '@angular/core';
import { HttpClient, HttpHeaders } from '@angular/common/http';
@Component({
selector: 'app-list',
templateUrl: './list.component.html',
styleUrls: ['./list.component.css']
})
export class ListComponent implements OnInit {
requestResult: any;
error: boolean = false;
paginationPage: number = 1;
paginationPageSize: number = 10;
constructor(private http: HttpClient) { }
ngOnInit(): void {
const access_token: string = localStorage.getItem('access_token');
const requestUrl: string = 'https://core.nekta.cloud/api/device/metering_devices';
const requestBody: object = {
page: 1, last_page: 0, sort_field: "id", sort: "desc", search_string: null, device_state: "all", is_archived: false, paginate: false,
append_fields: ["active_polling", "attributes", "tied_point"], per_page: 10
};
const headers = new HttpHeaders({'Authorization': `Bearer ${access_token}` });
const requestOptions = { headers: headers };
this.http.post(requestUrl, requestBody, requestOptions)
.subscribe((result) => {
this.error = false;
this.requestResult = result;
},
error => this.error = error
);
}
}
| 327104b52abd64a039f9c855974a2785b16204a0 | [
"TypeScript"
] | 2 | TypeScript | RubanDenis/Nekta-test | a400e4c357535296bd5d24e3e02f639c73706355 | efd668c4054620b36f24313d6580604977831072 |
refs/heads/master | <file_sep>package RestassuredTests;
import java.util.HashMap;
import java.util.Map;
import static org.hamcrest.Matchers.*;
import static io.restassured.RestAssured.*;
import org.testng.Assert;
import org.testng.annotations.BeforeClass;
import org.testng.annotations.Test;
import io.restassured.RestAssured;
import io.restassured.response.Response;
public class Demo4_deletedRequest {
int id = 5;
@Test
public void deletedata()
{
RestAssured.baseURI="http://dummy.restapiexample.com/api/v1";
RestAssured.basePath="/delete/1";
Response response=
given()
.when()
.delete()
.then()
.statusCode(200)
.statusLine("HTTP/1.1 200 OK")
.body("status",equalTo("success"))
.log().all()
.extract().response();
String JsonString = response.asString();
Assert.assertEquals(JsonString.contains("successfully! deleted Records"), true);
}
}
<file_sep>package RestassuredTests;
import org.testng.annotations.BeforeClass;
import org.testng.annotations.Test;
import io.restassured.RestAssured;
import static io.restassured.RestAssured.*;
import static org.hamcrest.Matchers.*;
public class Demo1_Get_request {
@Test
public void postdata()
{
RestAssured.baseURI=" http://dummy.restapiexample.com";
RestAssured.basePath="/api/v1/employees";
given()
.when()
.get()
.then()
.statusCode(200)
.statusLine("HTTP/1.1 200 OK");
}
// @Test
// public void getweatherdetails()
// {
// given()
// .when()
// .get("http://restapi.demoqa.com/utilities/weather/city/bangalore")
// .then()
// .statusCode(200)
// .statusLine("HTTP/1.1 200 OK")
// .body("City",equalTo("Bengaluru"))
// .and()
// .body("WindDirectionDegree",equalTo("220 Degree"))
// .header("content-type","application/json")
// .and()
// .header("content-length",hasSize(166));
//
//
//
// }
//
// @Test
// public void getreqresdetails()
// {
// given()
// .when()
// .get("https://reqres.in/api/users?page=2")
// .then()
// .statusCode(200)
// .statusLine("HTTP/1.1 200 OK")
// .body("data.id",equalTo("7"))
// .and()
// .body("last_name",equalTo("Funke"))
// .header("content-type","application/json")
// .and()
// .header("content-length",hasSize(166));
//
//
//
// }
//
}
<file_sep>package RestassuredTests;
import org.apache.commons.lang3.RandomStringUtils;
public class Restutils {
// body data for post
// {
//
// "FirstName":"kkk",
// "LastName":"yyy",
// "UserName":"qwe34",
// "Password":"<PASSWORD>",
// "Email":"<EMAIL>"
//
//}
private static String firstname;
private static String lastname;
private static String username;
private static String password;
private static String email;
public static String getFirstname() {
String generateStringFirstName = RandomStringUtils.randomAlphabetic(1);
return ("krishna"+generateStringFirstName);
}
public static String getLastname() {
String generateStringLastname = RandomStringUtils.randomAlphabetic(1);
return ("uppara"+generateStringLastname);
}
public static String getUsername() {
String generateStringUsername = RandomStringUtils.randomAlphabetic(1);
return ("uppara"+generateStringUsername);
}
public static String getPassword() {
String generateStringPassword = RandomStringUtils.randomAlphabetic(1);
return ("uppara"+generateStringPassword);
}
public static String getEmail() {
String generateStringEmail = RandomStringUtils.randomAlphabetic(1);
return ("uppara"+generateStringEmail);
}
public static String getSalary() {
String generateStringSalary = RandomStringUtils.randomNumeric(5);
return ("uppara"+generateStringSalary);
}
public static String getAge() {
String generateStringAge = RandomStringUtils.randomNumeric(2);
return ("uppara"+generateStringAge);
}
}
| a412bd95a7f45eaebc480d8a9c89e71381677e91 | [
"Java"
] | 3 | Java | krishna-uppara/Restassured-with-cucumber | 2fa53ebaade26a1e417bf58a1b2f4685ca9fb986 | 9e55fbe56505a351f33f7c107b08b7a9dde3fbc2 |
refs/heads/master | <file_sep>require 'test_helper'
class WhoopsieTest < ActiveSupport::TestCase
test "truth" do
assert_kind_of Module, Whoopsie
end
end
<file_sep>$:.push File.expand_path("../lib", __FILE__)
# Maintain your gem's version:
require "whoopsie/version"
# Describe your gem and declare its dependencies:
Gem::Specification.new do |s|
s.name = "whoopsie"
s.version = Whoopsie::VERSION
s.authors = ["<NAME>"]
s.email = ["<EMAIL>"]
s.homepage = "https://github.com/OXOS/whoopsie"
s.summary = "Server+client error notifications for OXOS apps"
s.description = "ExceptionNotification for email notifications + TraceKit for catching client-side errors"
s.license = "MIT"
s.files = Dir["{app,config,db,lib}/**/*", "MIT-LICENSE", "Rakefile", "README.rdoc"]
s.test_files = Dir["test/**/*"]
s.add_dependency "rails", ">= 4.2.3", "<= 5.0.0"
s.add_dependency "exception_notification", "~> 4.0.1"
s.add_development_dependency "sqlite3", "~> 1.3.4"
s.add_development_dependency "jquery-rails", "~> 4.0.3"
end
<file_sep>= Whoopsie
This project rocks and uses MIT-LICENSE.<file_sep>require "exception_notification"
require "whoopsie/engine"
require "whoopsie/railtie"
module Whoopsie
def self.report_and_swallow
yield
rescue StandardError => e
handle_exception(e)
end
def self.handle_exception(exception, data = {})
if Rails.application.config.whoopsie.enable
ExceptionNotifier.notify_exception(exception, data)
else
raise exception
end
end
end
<file_sep>class ErrorsController < ApplicationController
skip_before_action :verify_authenticity_token
class JavaScriptError < StandardError
end
newrelic_ignore if defined?(NewRelic) && respond_to?(:newrelic_ignore)
def create
if Rails.application.config.whoopsie.enable
exception = JavaScriptError.new(params[:error_report][:message])
report = params[:error_report]
report.merge!(params[:extra]) if params[:extra]
ExceptionNotifier.notify_exception exception, env: request.env, data: report
render plain: "error acknowledged"
else
render plain: "error ignored"
end
end
def bang
raise "boom!"
end
def ping
app_name = Rails.application.engine_name
db_status = (ActiveRecord::Base.connection.tables.length > 0) ? "ok" : "empty"
render plain: "#{app_name} #{db_status}"
end
end
| 0c7b16f3fa186254467a0944f1a553a2caeff038 | [
"RDoc",
"Ruby"
] | 5 | Ruby | christiaandegroot/whoopsie | ca7f77cfe2bcf607a13bd695643a63512c7b4d2f | bb42b859fab1cd4459a56bff962ed8b074977e0d |
refs/heads/master | <file_sep># MKT
MKT.js is an Exchange Price Service , Stocks , Cryptocurrency,Stock prediction and more \
This package contains hundreds of currencies, cryptocurrencies and stocks prices.\
6,096 coin , 283,037 TRADING PAIRS , 31 News Provider It also works with the TensorFlow Read more here [Read more about crypto-compare service](https://min-api.cryptocompare.com/faq)
for market forecasting / stock prediction using RNN and also works on the visualizing of stocks data using canvas.js
## Dependencies
- Neural Networks (brain.js)
- Tensorflow Framework (tensorflow.js)
- Data visualization (canvas.js)
- Main Api ( min-api.cryptocompare.com )
### Get started :
```
npm i @mkt-eg/mkt
```
#### 1 - Get Full details response (multiaple fsym & tsym)
```
const { MKT } = require('@mkt-eg/mkt')
const mkt = new MKT(
'bbbc22c3a13c74456a6d4bb7ba5745476ebfdc81c867fc240258122b78eb6a6f'
)
const data = mkt
.exchange({
fsym: 'BTC',
tsyms: 'USD',
type: 'full'
})
.then(response => {
console.log(JSON.stringify(response.data))
})
.catch(error => {
console.log(error)
})
// JSON OUTPUT
/*
{
"RAW":{
"BTC":{
"USD":{
"TYPE":"5",
"MARKET":"CCCAGG",
"FROMSYMBOL":"BTC",
"TOSYMBOL":"USD",
"FLAGS":"2",
"PRICE":9885.11,
"LASTUPDATE":1563398729,
"LASTVOLUME":0.1,
"LASTVOLUMETO":986.6100000000001,
"LASTTRADEID":"379345663",
"VOLUMEDAY":93692.97987050914,
"VOLUMEDAYTO":893517565.3549776,
"VOLUME24HOUR":104598.9946433591,
"VOLUME24HOURTO":997000834.8997525,
"OPENDAY":9423.44,
"HIGHDAY":9982.24,
"LOWDAY":9086.51,
"OPEN24HOUR":9649.99,
"HIGH24HOUR":9988.35,
"LOW24HOUR":9076.48,
"LASTMARKET":"Bitfinex",
"VOLUMEHOUR":2210.51459713301,
"VOLUMEHOURTO":21755061.31969251,
"OPENHOUR":9692.2,
"HIGHHOUR":9943.53,
"LOWHOUR":9663.39,
"TOPTIERVOLUME24HOUR":101424.52271706509,
"TOPTIERVOLUME24HOURTO":966363837.9391046,
"CHANGE24HOUR":235.1200000000008,
"CHANGEPCT24HOUR":2.436479208786753,
"CHANGEDAY":461.6700000000001,
"CHANGEPCTDAY":4.899166334162472,
"SUPPLY":17823212,
"MKTCAP":176184411173.32,
"TOTALVOLUME24H":720083.9899007804,
"TOTALVOLUME24HTO":7081137716.36884,
"TOTALTOPTIERVOLUME24H":425384.18596477184,
"TOTALTOPTIERVOLUME24HTO":4168740744.7056427,
"IMAGEURL":"/media/19633/btc.png"
}
}
},
"DISPLAY":{
"BTC":{
"USD":{
"FROMSYMBOL":"Ƀ",
"TOSYMBOL":"$",
"MARKET":"CryptoCompare Index",
"PRICE":"$ 9,885.11",
"LASTUPDATE":"Just now",
"LASTVOLUME":"Ƀ 0.1000",
"LASTVOLUMETO":"$ 986.61",
"LASTTRADEID":"379345663",
"VOLUMEDAY":"Ƀ 93,693.0",
"VOLUMEDAYTO":"$ 893,517,565.4",
"VOLUME24HOUR":"Ƀ 104,599.0",
"VOLUME24HOURTO":"$ 997,000,834.9",
"OPENDAY":"$ 9,423.44",
"HIGHDAY":"$ 9,982.24",
"LOWDAY":"$ 9,086.51",
"OPEN24HOUR":"$ 9,649.99",
"HIGH24HOUR":"$ 9,988.35",
"LOW24HOUR":"$ 9,076.48",
"LASTMARKET":"Bitfinex",
"VOLUMEHOUR":"Ƀ 2,210.51",
"VOLUMEHOURTO":"$ 21,755,061.3",
"OPENHOUR":"$ 9,692.20",
"HIGHHOUR":"$ 9,943.53",
"LOWHOUR":"$ 9,663.39",
"TOPTIERVOLUME24HOUR":"Ƀ 101,424.5",
"TOPTIERVOLUME24HOURTO":"$ 966,363,837.9",
"CHANGE24HOUR":"$ 235.12",
"CHANGEPCT24HOUR":"2.44",
"CHANGEDAY":"$ 461.67",
"CHANGEPCTDAY":"4.90",
"SUPPLY":"Ƀ 17,823,212.0",
"MKTCAP":"$ 176.18 B",
"TOTALVOLUME24H":"Ƀ 720.08 K",
"TOTALVOLUME24HTO":"$ 7.08 B",
"TOTALTOPTIERVOLUME24H":"Ƀ 425.38 K",
"TOTALTOPTIERVOLUME24HTO":"$ 4.17 B",
"IMAGEURL":"/media/19633/btc.png"
}
}
}
}
*/
```
#### 2 - Get Single price response (Single Ftsym only)
```
const { MKT } = require('@mkt-eg/mkt')
const mkt = new MKT(
'bbbc22c3a13c74456a6d4bb7ba5745476ebfdc81c867fc240258122b78eb6a6f'
)
const data = mkt
.exchange({
fsym: 'BTC', // Single Fysm only
tsyms: 'USD,EGP', // Multiaple Tsyms is allowed
type: 'single'
})
.then(response => {
console.log(JSON.stringify(response.data))
})
.catch(error => {
console.log(error)
})
// JSON OUTPUT
{
"USD":9888.01,
"EGP":182256.26
}
```
#### 3 - Get Multiaple price response
```
const { MKT } = require('@mkt-eg/mkt')
const mkt = new MKT(
'bbbc22c3a13c74456a6d4bb7ba5745476ebfdc81c867fc240258122b78eb6a6f'
)
const data = mkt
.exchange({
fsym: 'BTC,ETH', // Single Fysm only
tsyms: 'USD,EGP', // Multiaple Tsyms is allowed
type: 'multi'
})
.then(response => {
console.log(JSON.stringify(response.data))
})
.catch(error => {
console.log(error)
})
// JSON OUTPUT
{
"BTC":{
"USD":9906.65,
"EGP":182256.26
},
"ETH":{
"USD":215.27,
"EGP":3964.07
}
}
```
#### 3 - Historical Day/hour/minute OHLCV
Get open, high, low, close, volumefrom and volumeto from the daily historical data.The values are based on 00:00 GMT time. It uses BTC conversion if data is not available because the coin is not trading in the specified currency. If you want to get all the available historical data, you can use limit=2000 and keep going back in time using the toTs param. You can then keep requesting batches using: &limit=2000&toTs={the earliest timestamp received}.
* apiType parms : 'day' or 'hour' or 'minute'
* you can left some parameter empty its okay
* to know more about Request Params please read [Here](https://min-api.cryptocompare.com/documentation?key=Historical&cat=dataHistoday)
```
const MKT = new module.exports.MKT('bbbc22c3a13c74456a6d4bb7ba5745476ebfdc81c867fc240258122b78eb6a6f')
MKT.historical({
sympolPrice: 'true',
e: 'CCCAGG',
fsym: 'BTC',
tsyms: 'USD',
type: 'single',
aggregate: '1',
aggregatePredictableTimePeriods: true,
limit: 100,
allData: 'false',
extraParams: 'NotAvailable',
sign: 'false',
apiType: 'hour'
}).then((results)=>{
console.log(results.data)
})
// JSON OUTPUT
/*
{
"Response":"Success",
"Type":100,
"Aggregated":false,
"Data":[
{
"time":1563526800,
"close":10358.27,
"high":10406.85,
"low":10277.92,
"open":10376.84,
"volumefrom":2507.84,
"volumeto":25941945.52
},
{
"time":1563530400,
"close":10342.75,
"high":10402.72,
"low":10271.27,
"open":10358.27,
"volumefrom":2464.21,
"volumeto":25476339.6
},
{
"time":1563534000,
"close":10297.03,
"high":10412.81,
"low":10287.51,
"open":10342.75,
"volumefrom":2049.12,
"volumeto":21172424.41
},
{
"time":1563537600,
"close":10506.18,
"high":10654.99,
"low":10234.52,
"open":10297.03,
"volumefrom":5671.63,
"volumeto":59565785.39
},
{
"time":1563541200,
"close":10319.53,
"high":10510.44,
"low":10135.16,
"open":10506.18,
"volumefrom":7043.95,
"volumeto":72409649.25
},
{
"time":1563544800,
"close":10341.37,
"high":10425.08,
"low":10284.69,
"open":10319.53,
"volumefrom":1326,
"volumeto":13724171.79
}
],
"TimeTo":1563544800,
"TimeFrom":1563526800,
"FirstValueInArray":true,
"ConversionType":{
"type":"direct",
"conversionSymbol":""
},
"RateLimit":{
},
"HasWarning":false
}
*/
```
## Some of the ideas I put forward and you can get started:
- Add processing of natural languages to increase confidence in prices that have been predicted
- Add simulation of the investment process and the development of some strategies of trades.
- Monitor the markets and manufacture a global dashboard.
- add simples and examples using MKT.JS
## contributions
- For the first contributor you can delete the file and be the first shareholder (I left it to you)
- For the rest, if you think of an idea, you should make pull request and apply it immediately.
Author : <NAME>
<file_sep>const axios = require('axios')
module.exports = {
get: (link) => {
return new Promise((resolve, reject) => {
// Make a request for a user with a given ID
axios
.get(link)
.then((response) => {
// handle success
resolve(response)
}).catch((error) => {
// handle error
reject(error)
})
})
}
}
| 2b504c1a7e0c2ad8aff83a6778c9ef51919dbc29 | [
"Markdown",
"JavaScript"
] | 2 | Markdown | ahmedHusseinF/MKT | acc97526602616124066b6a0fba83b2c2f7316a2 | 60516791bca84ac815bb21bf51786669e973fb0e |
refs/heads/master | <repo_name>yudenichaa/NeuralNetworkResults<file_sep>/main.py
import os
import sys
from PyQt5 import QtWidgets
from AerialRoadsWidget import AerialRoadsWidget
os.environ['TF_CPP_MIN_LOG_LEVEL'] = '3'
if __name__ == '__main__':
app = QtWidgets.QApplication(sys.argv)
app.setStyle(QtWidgets.QStyleFactory.create("Fusion"))
aerial_roads_widget = AerialRoadsWidget()
aerial_roads_widget.show()
sys.exit(app.exec())
<file_sep>/network.py
from segmentation_models.losses import bce_jaccard_loss
from segmentation_models.metrics import iou_score
import numpy as np
from keras.models import load_model
from albumentations import Resize
from skimage.transform import resize
import tensorflow as tf
from tensorflow.python.keras.backend import set_session
def get_model(model_path):
session = tf.Session()
graph = tf.get_default_graph()
set_session(session)
model = load_model(
model_path,
custom_objects={
'binary_crossentropy_plus_jaccard_loss': bce_jaccard_loss,
'iou_score': iou_score
})
return model, graph, session
def get_prediction(model, graph, session, image):
with graph.as_default():
set_session(session)
image_data = image.astype(np.float32) / 255
image_data = scale_and_reshape_image(image_data)
prediction = model.predict(image_data)
prediction_image = prediction.reshape(image_data.shape[1], image_data.shape[2])
return prediction_image * 255
def scale_and_reshape_image(image_data, max_image_size=1500):
width_scale_factor = image_data.shape[0] / max_image_size
height_scale_factor = image_data.shape[1] / max_image_size
scale_factor = max(width_scale_factor, height_scale_factor)
if scale_factor > 1:
image_data = resize(image_data,
(image_data.shape[0] // scale_factor,
image_data.shape[1] // scale_factor),
anti_aliasing=True)
augmented = Resize(height=(image_data.shape[0] // 32) * 32,
width=(image_data.shape[1] // 32) * 32)(image=image_data)
image_data = augmented['image']
image_data = image_data.reshape(1, image_data.shape[0], image_data.shape[1], 3).astype(np.float32)
return image_data
<file_sep>/requirements.txt
absl-py==0.9.0
albumentations==0.4.6
astor==0.8.1
cycler==0.10.0
decorator==4.4.2
efficientnet==1.0.0
gast==0.2.2
google-pasta==0.2.0
grpcio==1.30.0
h5py==2.10.0
image-classifiers==1.0.0
imageio==2.9.0
imgaug==0.4.0
importlib-metadata==1.7.0
Keras==2.3.1
Keras-Applications==1.0.8
Keras-Preprocessing==1.1.2
kiwisolver==1.1.0
Markdown==3.2.2
matplotlib==3.0.3
networkx==2.4
numpy==1.18.5
opencv-python==4.3.0.36
opencv-python-headless==4.3.0.36
opt-einsum==3.3.0
Pillow==7.2.0
protobuf==3.12.2
pyparsing==2.4.7
PyQt5==5.9.2
PyQt5-stubs==5.14.2.2
python-dateutil==2.8.1
PyWavelets==1.1.1
PyYAML==5.3.1
qimage2ndarray==1.8.3
scikit-image==0.15.0
scipy==1.4.1
segmentation-models==1.0.1
Shapely==1.7.0
sip==4.19.8
six==1.15.0
tensorboard==1.15.0
tensorflow-estimator==1.15.1
tensorflow-gpu==1.15.0
termcolor==1.1.0
Werkzeug==1.0.1
wrapt==1.12.1
zipp==1.2.0
<file_sep>/AerialRoadsWidget.py
import os
from PyQt5 import QtWidgets, QtCore, QtGui
from keras.engine.training import Model
from network import get_model, get_prediction
from tensorflow.python.framework.ops import Graph
from tensorflow.python.client.session import Session
from qimage2ndarray import array2qimage
from numpy import ndarray
from skimage.io import imread
class GetModelThread(QtCore.QThread):
signal_model_loaded = QtCore.pyqtSignal(Model, Graph, Session)
def __init__(self, model_path):
QtCore.QThread.__init__(self)
self.model_path = model_path
def __del__(self):
self.wait()
def run(self):
model, graph, session = get_model(self.model_path)
self.signal_model_loaded.emit(model, graph, session)
class GetPredictionsThread(QtCore.QThread):
signal_calculations_complete = QtCore.pyqtSignal(ndarray)
def __init__(self, model, graph, session, image):
QtCore.QThread.__init__(self)
self.model = model
self.graph = graph
self.session = session
self.image = image
def __del__(self):
self.wait()
def run(self):
prediction = get_prediction(
self.model, self.graph,
self.session, self.image)
self.signal_calculations_complete.emit(prediction)
class AerialRoadsWidget(QtWidgets.QWidget):
def _btn_choose_network_clicked(self):
model_file_name = QtWidgets.QFileDialog.getOpenFileName(
self, 'Выберите модель',
QtCore.QDir.currentPath(),
'Keras model files (*.h5)')[0]
if model_file_name:
self.model_loading_thread = GetModelThread(model_file_name)
self.model_loading_thread.signal_model_loaded.connect(self.slot_model_loaded)
self.model_loading_thread.start()
self.show_loading_indicator('Загрузка модели')
def slot_model_loaded(self, model, graph, session):
self.model = model
self.graph = graph
self.session = session
self.hide_loading_indicator()
def _btn_choose_folder_clicked(self):
if not self.model:
QtWidgets.QMessageBox.information(self, 'Информация', 'Модель не выбрана')
return
directory = QtWidgets.QFileDialog.getExistingDirectory(
self, 'Выберите папку с изображениями',
QtCore.QDir.currentPath())
if directory:
self.image_paths = []
for file in sorted(os.listdir(directory)):
if QtCore.QFileInfo(file).suffix() in ('png', 'jpg', 'jpeg', 'tiff'):
self.image_paths.append(os.path.join(directory, file))
self.current_image_index = 0
self.start_calculations()
def start_calculations(self):
image = imread(self.image_paths[self.current_image_index])
self.calculations_thread = GetPredictionsThread(
self.model, self.graph,
self.session, image)
self.calculations_thread.signal_calculations_complete.connect(self.slot_calculations_complete)
self.calculations_thread.start()
self.image = array2qimage(image)
self.set_label_image(self.lbl_input_image_data, self.image)
self.lbl_output_image_data.setMovie(self.loading_animation)
self.loading_animation.start()
def slot_calculations_complete(self, prediction):
self.prediction = array2qimage(prediction)
self.loading_animation.stop()
self.set_label_image(self.lbl_output_image_data, self.prediction)
def _btn_back_clicked(self):
if len(self.image_paths) == 0:
QtWidgets.QMessageBox.information(self, 'Информация', 'Выберите папку с изображениями')
return
if self.current_image_index == len(self.image_paths) - 1:
self.current_image_index = 0
else:
self.current_image_index += 1
self.start_calculations()
def _btn_next_clicked(self):
if len(self.image_paths) == 0:
QtWidgets.QMessageBox.information(self, 'Информация', 'Выберите папку с изображениями')
return
if self.current_image_index == 0:
self.current_image_index = len(self.image_paths) - 1
else:
self.current_image_index -= 1
self.start_calculations()
def _btn_restart_clicked(self):
if len(self.image_paths) == 0:
QtWidgets.QMessageBox.information(self, 'Информация', 'Выберите папку с изображениями')
return
self.current_image_index = 0
self.start_calculations()
def resizeEvent(self, event):
self.setWindowState(QtCore.Qt.WindowMaximized)
super().resizeEvent(event)
def show_loading_indicator(self, message):
self.layout_buttons.setContentsMargins(0, 0, 0, 0)
self.lbl_loading.setText(message)
self.lbl_loading_animation.setVisible(True)
self.lbl_loading.setVisible(True)
self.loading_animation.start()
def hide_loading_indicator(self):
self.layout_buttons.setContentsMargins(0, 0, 0, 25)
self.lbl_loading_animation.setVisible(False)
self.lbl_loading.setVisible(False)
self.loading_animation.stop()
@staticmethod
def set_button_icon(button, image):
icon = QtGui.QIcon(image)
button.setIcon(icon)
button.setIconSize(image.rect().size())
def set_label_image(self, label, image):
label.setPixmap(QtGui.QPixmap.fromImage(image).scaled(
self.image_label_size,
QtCore.Qt.KeepAspectRatio,
QtCore.Qt.SmoothTransformation
))
def __init__(self, parent=None):
super().__init__(parent)
self.setWindowTitle('Технополис "ЭРА"')
self.setWindowIcon(QtGui.QIcon('images/logo_era.ico'))
self.setWindowState(QtCore.Qt.WindowFullScreen)
self.image_label_size = QtCore.QSize(940, 880)
self.model = None
self.graph = None
self.session = None
self.calculations_thread = None
self.model_loading_thread = None
self.image_paths = []
self.image = None
self.prediction = None
self.current_image_index = 0
palette = self.palette()
palette.setColor(QtGui.QPalette.Background, QtCore.Qt.white)
self.setAutoFillBackground(True)
self.setPalette(palette)
btn_choose_folder = QtWidgets.QPushButton()
btn_choose_folder.setFlat(True)
btn_choose_network = QtWidgets.QPushButton()
btn_choose_network.setFlat(True)
btn_restart = QtWidgets.QPushButton()
btn_restart.setFlat(True)
btn_back = QtWidgets.QPushButton()
btn_back.setFlat(True)
btn_next = QtWidgets.QPushButton()
btn_next.setFlat(True)
folder_button_image = QtGui.QPixmap('images/folder_image48x48.png')
network_button_image = QtGui.QPixmap('images/net48x48.png')
restart_button_image = QtGui.QPixmap('images/restart48x48.png')
back_button_image = QtGui.QPixmap('images/back48x48.png')
next_button_image = QtGui.QPixmap('images/next48x48.png')
AerialRoadsWidget.set_button_icon(btn_choose_folder, folder_button_image)
AerialRoadsWidget.set_button_icon(btn_choose_network, network_button_image)
AerialRoadsWidget.set_button_icon(btn_restart, restart_button_image)
AerialRoadsWidget.set_button_icon(btn_back, back_button_image)
AerialRoadsWidget.set_button_icon(btn_next, next_button_image)
btn_choose_folder.clicked.connect(self._btn_choose_folder_clicked)
btn_choose_network.clicked.connect(self._btn_choose_network_clicked)
btn_restart.clicked.connect(self._btn_restart_clicked)
btn_back.clicked.connect(self._btn_back_clicked)
btn_next.clicked.connect(self._btn_next_clicked)
label_font = QtGui.QFont('IMPACT', 13)
lbl_input_image = QtWidgets.QLabel('Исходное изображение')
lbl_input_image.setAlignment(QtCore.Qt.AlignCenter)
lbl_input_image.setFont(label_font)
lbl_output_image = QtWidgets.QLabel('Результат обработки')
lbl_output_image.setAlignment(QtCore.Qt.AlignCenter)
lbl_output_image.setFont(label_font)
self.lbl_loading = QtWidgets.QLabel()
self.lbl_loading.setVisible(False)
self.lbl_loading.setContentsMargins(0, 35, 0, 0)
self.lbl_loading.setFont(label_font)
self.lbl_loading.setAlignment(QtCore.Qt.AlignCenter)
self.lbl_loading_animation = QtWidgets.QLabel()
self.lbl_loading_animation.setVisible(False)
self.lbl_loading_animation.setAlignment(QtCore.Qt.AlignCenter)
self.loading_animation = QtGui.QMovie('images/loading.gif')
self.lbl_loading_animation.setMovie(self.loading_animation)
self.lbl_input_image_data = QtWidgets.QLabel()
self.lbl_output_image_data = QtWidgets.QLabel()
self.lbl_input_image_data.setMaximumSize(self.image_label_size)
self.lbl_output_image_data.setMaximumSize(self.image_label_size)
self.lbl_input_image_data.setPixmap(QtGui.QPixmap('images/no_image.png').scaled(
self.image_label_size,
QtCore.Qt.KeepAspectRatio,
QtCore.Qt.SmoothTransformation
))
self.lbl_output_image_data.setPixmap(QtGui.QPixmap('images/no_image.png').scaled(
self.image_label_size,
QtCore.Qt.KeepAspectRatio,
QtCore.Qt.SmoothTransformation
))
self.layout_buttons = QtWidgets.QHBoxLayout()
self.layout_buttons.setContentsMargins(0, 0, 0, 25)
self.layout_buttons.setAlignment(QtCore.Qt.AlignCenter)
self.layout_buttons.addWidget(btn_choose_network)
self.layout_buttons.addWidget(btn_choose_folder)
self.layout_buttons.addWidget(btn_back)
self.layout_buttons.addWidget(btn_next)
self.layout_buttons.addWidget(btn_restart)
layout_input_image = QtWidgets.QVBoxLayout()
layout_input_image.setAlignment(QtCore.Qt.AlignTop | QtCore.Qt.AlignHCenter)
layout_input_image.addWidget(lbl_input_image)
layout_input_image.addWidget(self.lbl_input_image_data)
layout_output_image = QtWidgets.QVBoxLayout()
layout_output_image.setAlignment(QtCore.Qt.AlignTop | QtCore.Qt.AlignHCenter)
layout_output_image.addWidget(lbl_output_image)
layout_output_image.addWidget(self.lbl_output_image_data)
layout_images = QtWidgets.QHBoxLayout()
layout_images.addLayout(layout_input_image)
layout_images.addLayout(layout_output_image)
layout_main = QtWidgets.QVBoxLayout()
layout_main.setAlignment(QtCore.Qt.AlignTop)
layout_main.addLayout(self.layout_buttons)
layout_main.addWidget(self.lbl_loading)
layout_main.addWidget(self.lbl_loading_animation)
layout_main.addLayout(layout_images)
self.setLayout(layout_main)
| c17204a5a1aace620946390f2877a7e1f3ca7fb9 | [
"Python",
"Text"
] | 4 | Python | yudenichaa/NeuralNetworkResults | 3868e052e4254dd7d96d8f60d59e468969e4e58e | 22b1ea851e54819aef74911ffd32db96686aaf4f |
refs/heads/master | <repo_name>nghti/Scss_for_ant<file_sep>/src/index.js
import './assets/scss/main.scss'
console.log('app loaded');<file_sep>/README.md
## Project setup
```
yarn install
```
### Compiles and create file build
```
yarn dev
```
### Compiles and minifies for production
```
yarn build
```
### Run project
```
yarn start
```
| 116965e492daef4b710e9d5fd3c6c6a0e89fdc0d | [
"JavaScript",
"Markdown"
] | 2 | JavaScript | nghti/Scss_for_ant | 59ad3c07fdec636b219f1ece73f20b0848d1cf54 | d408adf8ac6f02cc53a1c0d08311f895156fd52e |
refs/heads/master | <repo_name>D-Singh11/Would-you-rather<file_sep>/src/middleware/index.js
import thunk from 'redux-thunk';
import { applyMiddleware } from 'redux';
import logger from './logger';
/**
* @description It is used to create a root middleware by combining all other
* middleware functions using applyMiddleware() function provided by 'redux library.
* @param {functon} thunk
* @param {function} logger
* @return {function} rootMiddleware
*/
export default applyMiddleware(
thunk,
logger
);<file_sep>/src/components/NavBar.js
import React, { Component } from 'react';
import { NavLink } from 'react-router-dom';
class Nav extends Component {
render() {
return (
<nav className="nav">
<ul>
<li>
<NavLink to="/" exact activeClassName="active">
Homepage
</NavLink>
</li>
<li>
<NavLink to="/add" activeClassName="active">
Add question
</NavLink>
</li>
<li>
<NavLink to="/leaderboard" activeClassName="active">
Leaderboard
</NavLink>
</li>
<li className="right">
<NavLink to="/" activeClassName="active"
onClick={this.props.handleLogOut}>
LogOut
</NavLink>
</li>
</ul>
</nav>
)
}
}
export default Nav;
<file_sep>/src/components/Question.js
import React, { Component } from 'react';
import { connect } from 'react-redux';
import { Link } from 'react-router-dom';
class Question extends Component {
/**
* @description Renders the Poll component to DOM
*/
render() {
const { author, optionOne, id } = this.props;
return (
<div className="col s12 m7">
<div className="card horizontal card-panel hoverable">
<div className="card-image">
<img src={this.props.avatarURL} alt="avatar of user" />
<span className="card-title">{author}</span>
</div>
<div className="card-stacked">
<div className="card-content center">
<h3 className=" blue-grey-text">Would you rather?</h3>
<span>{optionOne.text} <br /> OR ..</span>
</div>
<Link to={`/questions/${id}`} className="white-text">
<div className="card-action amber lighten-2">
<p className="center ">
<b>{this.props.type === 'unanswered' ? 'Poll' : 'See details'}</b>
</p>
</div>
</Link>
</div>
</div>
</div>
)
}
}
/**
* @description This function is used to specify what state is needed in the component from
redux store. It is then passed as parameter to connect function. It is executed
in the the body of connect() provided by 'react-redux' library.
@param {Object} users
@param {Object} questions
@param {string} authedUser
@param {object} props
@returns {object} question details
*/
function mapStateToProps({ users, questions, authedUser }, props) {
const question = questions[props.id];
const author = questions[props.id].author;
const avatarURL = users[author].avatarURL;
return {
...question,
author,
avatarURL
};
}
/**
* @description connect() used to connect Question Component to store and request
state from it.
@param {function} mapStateToProps
@param {Component} Question
@returns {Component} ConnectedComponent
*/
export default connect(mapStateToProps)(Question);
<file_sep>/src/components/QuestionList.js
import React, { Component } from 'react';
import Question from './Question';
import { connect } from 'react-redux';
class QuestionList extends Component {
/**
* @description Renders the Poll component to DOM
*/
render() {
return (
<ul className="collection" key={this.props.type}>
{this.props.qIds.map(id => {
return (
<li className="collection-item" key={id}>
< Question id={id} type={this.props.type} />
</li>
)
})}
</ul>
)
}
}
/**
* @description This function is used to specify what state is needed in the component from
redux store. It is then passed as parameter to connect function. It is executed
in the the body of connect() provided by 'react-redux' library.
@param {Object} users
@param {Object} questions
@param {string} authedUser
@param {object} props
@returns {array} qIds
*/
function mapPropsToState({ users, questions, authedUser }, props) {
const user = users[authedUser];
const answers = Object.keys(user.answers);
const qIds = props.type === 'answered'
? answers.sort((a, b) => questions[b].timestamp - questions[a].timestamp)
: Object.keys(questions).filter(qId => !answers.includes(qId));
return {
qIds
};
}
/**
* @description connect() used to connect QuestionList Component to store and request
state from it.
@param {function} mapStateToProps
@param {Component} QuestionList
@returns {Component} ConnectedComponent
*/
export default connect(mapPropsToState)(QuestionList);
<file_sep>/src/components/PageNotFound.js
import React, { Component } from 'react';
import { Link } from 'react-router-dom';
class PageNotFound extends Component {
/**
* @description Renders the PageNotFound component to DOM
*/
render() {
return (
<div className="container">
<h3>Page not found</h3>
<div className="card z-depth-5 center">
<div className="card-action center">
<Link to="/" className="btn">Go back</Link>
</div>
<div className="card-image">
<img src="https://media.giphy.com/media/UoeaPqYrimha6rdTFV/giphy.gif" alt="page not found" />
</div>
<div className="card-content">
<span>Page you tried to access does not exist. It could be because of incorrect URL</span>
</div>
</div>
</div>
)
}
}
export default PageNotFound;
<file_sep>/src/middleware/logger.js
/**
* @description Custom middleware called logger used to log the action type,
* and state of store before and after the action is complete.
* @param {object} store
* @returns {function}
*/
const logger = (store) => (next) => (action) => {
console.group(action.type);
console.log('State before action', store.getState());
const result = next(action);
console.log('State after action', store.getState());
console.groupEnd();
return result;
};
export default logger;<file_sep>/src/components/LeaderBoard.js
import React, { Component } from 'react';
import { connect } from 'react-redux';
import Leader from './Leader';
class LeaderBoard extends Component {
render() {
return (
<div>
<h3>LeaderBoard</h3>
<ul className="collection">
{this.props.leaders.map(leader => {
return (
<li className="collection-item" key={leader.name}>
<Leader leader={leader} />
</li>
)
})}
</ul>
</div>
)
}
}
/**
* @description This function is used to specify what state is needed in the component from
redux store. It is then passed as parameter to connect function. It is executed
in the the body of connect() provided by 'react-redux' library.
@param {Object} state
@returns {array} leaders
*/
function mapStaeToProps(state) {
const userKeys = Object.keys(state.users);
const leaders = userKeys.map(id => {
const userQuesIds = state.users[id].questions;
const userAnswers = Object.keys(state.users[id].answers);
return {
'questions': userQuesIds.length,
'answers': userAnswers.length,
'avatarURL': state.users[id].avatarURL,
'name': state.users[id].name,
'total': userAnswers.length + userQuesIds.length,
};
});
return {
leaders: leaders.sort((a, b) => b.total - a.total)
};
}
/**
* @description connect() used to connect Poll Component to store and request
state from it.
@param {function} mapStateToProps
@param {Component} LeaderBoard
@returns {Component} ConnectedComponent
*/
export default connect(mapStaeToProps)(LeaderBoard);
<file_sep>/src/reducers/authedUser.js
import { SET_AUTHED_USER } from '../actions/authedUser';
/**
* @description Reducer function used by redux store to update the
* authedUser state in store by applying action passed as second parameter.
* @param {string} authedUser
* @returns {object} action
* @returns {string} authedUser
*/
export default function authedUser(authedUser = null, action) {
switch (action.type) {
case SET_AUTHED_USER:
return action.id;
default:
return authedUser;
}
}<file_sep>/README.md
# Would you rather Project
## Introduction
Would You Rather, is a web app that lets its users play the `Would You Rather?` game. The game asks user a question in the form: `Would you rather [option A] or [option B] ?`.
This application solidify the understanding of `React and Redux` to improve the predictability of application’s state. It emphasizes on the state management through a central `redux` store instead of handling state by React components. It is developed by following Redux's rules for `getting, listening, and updating` the store.
Application provides following functionality to its users:
* See questions they have and haven’t answered
* Answer questions
* See how other people have voted
* Create new questions
* See the ranking of users on the leaderboard
## Installation Instructions
Install all dependency node modules by navigating to `would-you-rather` directory and using following command in terminal :
>$ npm install
Next, start the application by running following command in terminal :
>$ npm start
To view application, open a browser and type specified URL in the URL menu :
>http://localhost:3000
## Database
The `_DATA.js` file represents a fake database and methods that provides access to the data.
There are two types of objects stored in our database:
* Users
* Questions
### Users
Users include:
| Attribute | Type | Description |
|-----------------|------------------|------------------- |
| id | String | The user’s unique identifier |
| name | String | The user’s first name and last name |
| avatarURL | String | The path to the image file |
| questions | Array | A list of ids of the polling questions this user created|
| answers | Object | The object's keys are the ids of each question this user answered. The value of each key is the answer the user selected. It can be either `'optionOne'` or `'optionTwo'` since each question has two options.
### Questions
Questions include:
| Attribute | Type | Description |
|-----------------|------------------|-------------------|
| id | String | The question’s unique identifier |
| author | String | The author’s unique identifier |
| timestamp | String | The time when the question was created|
| optionOne | Object | The first voting option|
| optionTwo | Object | The second voting option|
### Voting Options
Voting options are attached to questions. They include:
| Attribute | Type | Description |
|-----------------|------------------|-------------------|
| votes | Array | A list that contains the id of each user who voted for that option|
| text | String | The text of the option |
## Backend Server
The provided file [`api.js`](src/utils/api.js) contains the methods to perform necessary operations on the backend:
* [`getInitialData`](#getInitialData)
* [`saveQuestion`](#saveQuestion)
* [`saveAnswer`](#saveAnswer)
### `getInitialData`
Method Signature:
```js
getInitialData()
```
*Description*: Get all of the existing users and questions from the database.
*Return Value*:
* Returns a Promise which resolves to a JSON object containing users and questions objects.
* `users` Object where the key is the user’s id and the value is the user object.
* `questions` Object where the key is the question’s id and the value is the question object
### `saveQuestion`
Method Signature:
```js
saveQuestion(question)
```
*Description*: Save the polling question in the database.
*Parameters*: Object that includes the following properties: `author`, `optionOneText`, and `optionTwoText`. More details about these properties:
| Attribute | Type | Description |
|-----------------|------------------|-------------------|
| author | String | The id of the user who posted the question|
| optionOneText| String | The text of the first option |
| optionTwoText | String | The text of the second option |
*Return Value*: An object that has the following properties: `id`, `author`, `optionOne`, `optionTwo`, `timestamp`. More details about these properties:
| Attribute | Type | Description |
|-----------------|------------------|-------------------|
| id | String | The id of the question that was posted|
| author | String | The id of the user who posted the question|
| optionOne | Object | The object has a text property and a votes property, which stores an array of the ids of the users who voted for that option|
| optionTwo | Object | The object has a text property and a votes property, which stores an array of the ids of the users who voted for that option|
|timestamp|String | The time when the question was created|
### `saveAnswer`
Method Signature:
```js
saveAnswer(info)
```
*Description*: Save the answer to a particular polling question in the database.
*Parameters*: Object that contains the following properties: `authedUser`, `qid`, and `answer`. More details about these properties:
| Attribute | Type | Description |
|-----------------|------------------|-------------------|
| authedUser | String | The id of the user who answered the question|
| qid | String | The id of the question that was answered|
| answer | String | The option the user selected. The value should be either `"optionOne"` or `"optionTwo"`|
<file_sep>/src/actions/questions.js
import { saveAnswer, saveQuestion } from '../utils/api';
import { showLoading, hideLoading } from 'react-redux-loading';
import { saveUserAnswerAction } from './users';
export const RECEIVE_QUESTIONS = 'RECEIVE_QUESTIONS';
export const SAVE_ANSWER = 'SAVE_ANSWER';
export const ADD_QUESTION = 'ADD_QUESTION';
/**
* @description Action creator used to craete action for RECEIVE_QUESTIONS event
* @param {object} questions
* @returns {object} action
*/
export function setQuestionsAction(questions) {
return {
type: RECEIVE_QUESTIONS,
questions
};
}
/**
* @description Action creator used to craete action for SAVE_ANSWER event
* @param {object} question
* @returns {object} action
*/
function saveAnswerAction(question) {
return {
type: SAVE_ANSWER,
question
};
}
/**
* @description Action creator used to craete action for ADD_QUESTION event
* @param {object} question
* @returns {object} action
*/
function addQuestionAction(question) {
return {
type: ADD_QUESTION,
question
};
}
/**
* @description Thunked Action creator used to make asynchornous API
* call to save answer. Dispatches actions used to saveAnswerAction()
* and saveUserAnswerAction().
* @param {string} qId
* @param {object} answer
* @returns {function}
*/
export function handleSaveAnswer(qid, answer) {
return (dispatch, getState) => {
const authedUser = getState().authedUser;
dispatch(showLoading());
return saveAnswer({
authedUser,
qid,
answer
}).then(response=>{
dispatch(saveAnswerAction({ authedUser, qid, answer }));
dispatch(saveUserAnswerAction({ authedUser, qid, answer }));
dispatch(hideLoading());
})
.catch(error => {
dispatch(hideLoading());
alert('Error - Answer not saved Try again');
});
};
}
/**
* @description Thunked action creator used to make asynchornous API
* call to add/save new question.
* Dispatches action addQuestionAction() used to add question to redux store.
* @param {object} question
* @returns {function}
*/
export function handleAddQuestion(question) {
return (dispatch) => {
dispatch(showLoading());
return saveQuestion(question).then(savedQuestion => {
dispatch(addQuestionAction(savedQuestion));
dispatch(hideLoading());
});
};
}<file_sep>/src/actions/authedUser.js
export const SET_AUTHED_USER = 'SET_AUTHED_USER';
/**
* @description Action creator used to craete action for SET_AUTHED_USER event
* @param {string} id
* @returns {object} action
*/
export function setAuthedUserAction(id) {
return {
type: SET_AUTHED_USER,
id
};
}<file_sep>/src/actions/users.js
export const RECEIVE_USERS = 'RECEIVE_USERS';
export const SAVE_USER_ANSWER = 'SAVE_USER_ANSWER';
/**
* @description Action creator used to craete action for RECEIVE_USERS event
* @param {object} users
* @returns {object} action
*/
export function setUsersAction(users) {
return {
type: RECEIVE_USERS,
users
};
}
/**
* @description Action creator used to craete action for SAVE_USER_ANSWER event.
* It is used to add the new answer to the user's information/details.
* @param {object} question
* @returns {object} action
*/
export function saveUserAnswerAction(question) {
return {
type: SAVE_USER_ANSWER,
question
};
}<file_sep>/src/actions/shared.js
import { setUsersAction } from './users';
import { setQuestionsAction } from './questions';
import { getInitialData } from '../utils/api';
import { showLoading, hideLoading } from 'react-redux-loading';
/**
* @description Thunked Action creator used to make asynchornous API
* call to get initial data from database needed to set initial state of redux store.
* Dispatch actions used to upadte users and questions state in store.
* @returns {function}
*/
export function handleInitialData() {
return (dispatch) => {
dispatch(showLoading());
return getInitialData().then(data => {
const { users, questions } = data;
dispatch(setUsersAction(users));
dispatch(setQuestionsAction(questions));
dispatch(hideLoading());
});
};
}<file_sep>/src/components/Leader.js
import React from 'react'
const Leader = ({ leader }) => {
let stars = [];
for (let i = 0; i < leader.answers + leader.questions; i++) {
stars.push(<i className="material-icons amber" key={i}>stars</i>)
}
return (
<div>
<div className="row">
<div className="col s6 offset-s3">
<div className="card card-panel hoverable center">
<div className="card-image">
<img src={leader.avatarURL} alt="leader avatar" />
<p className="flow-text">{leader.name}</p>
{stars}
</div>
<div className="card-content">
<p>Questions posted : {leader.questions}</p>
<p>Answered : {leader.answers}</p>
<p>Score : {leader.answers + leader.questions}</p>
</div>
</div>
</div>
</div>
</div>
)
}
export default Leader;
<file_sep>/src/reducers/users.js
import { RECEIVE_USERS, SAVE_USER_ANSWER } from '../actions/users';
/**
* @description Reducer function used by redux store to update the
* users state in store by applying action passed as second parameter.
* @param {object} state
* @param {object} action
* @returns {object} state
*/
export default function users(state = {}, action) {
switch (action.type) {
case RECEIVE_USERS:
return {
...state,
...action.users
};
case SAVE_USER_ANSWER:
return {
...state,
[action.question.authedUser]: {
...state[action.question.authedUser],
answers: {
...state[action.question.authedUser].answers,
[action.question.qid]: action.question.answer
}
}
};
default:
return state;
}
}<file_sep>/src/reducers/index.js
import users from './users';
import questions from './questions';
import authedUser from './authedUser';
import { combineReducers } from 'redux';
import { loadingBarReducer } from 'react-redux-loading';
/**
* @description It is used to create a root reducer by combining all other
* reducer using combineReducers() function provided by 'redux library.
* @param {object} allreducers
* @param {function} rootreducer
*/
export default combineReducers({
users,
questions,
authedUser,
loadingBar: loadingBarReducer
});<file_sep>/src/components/NewQuestion.js
import React, { Component } from 'react';
import { handleAddQuestion } from '../actions/questions';
import { connect } from 'react-redux';
class NewQuestion extends Component {
/**
* @description It is used to add a new question to the backend
* and into the redux store. It reads the user unputs from the form and
* calls dispatch() of redux store which uses thunked action creator
* handleAddQuestion() to update state of store and backend database.
* This event handler also redirects user to home route using history object of route.
* @param {event} event
* @returns {array} books
*/
handleSubmit = (event) => {
event.preventDefault();
if (this.optionOne.value.trim() && this.optionTwo.value.trim()) {
this.props.dispatch(handleAddQuestion({
optionOneText: this.optionOne.value.trim(),
optionTwoText: this.optionTwo.value.trim(),
author: this.props.authedUser
}));
this.props.history.push('/');
}
else {
alert("Provide both options to save new question");
}
};
/**
* @description Renders the NewQuestion component to DOM
*/
render() {
return (
<div className="newQuestion row center">
<h3>Would you rather?</h3>
<form onSubmit={this.handleSubmit} className="col s6 offset-s3">
<label htmlFor="optionOne">Option one</label>
<input type="text"
placeholder="add first option"
ref={(optionOne) => this.optionOne = optionOne}
/>
<label htmlFor="optionTwo">Option two</label>
<input type="text"
placeholder="add second option"
ref={(optionTwo) => this.optionTwo = optionTwo}
/>
<button type="submit" className="btn-large amber center">
Save
</button>
</form>
</div>
)
}
}
/**
* @description connect() used to connect NewQuestionComponent to store and request
state from it.
@param {function} arrow function
@param {Component} NewQuestion
@returns {Component} ConnectedComponent
*/
export default connect((state => {
return {
authedUser: state.authedUser
}
}))(NewQuestion);
| da4a675a5213921deb7c11e7b869ed0b578fd173 | [
"JavaScript",
"Markdown"
] | 17 | JavaScript | D-Singh11/Would-you-rather | d1950681c2687b02fd5d5757c3d73fb0beb57ef2 | c00cf4af028f75370b17378dde71e053efb7f5d3 |
refs/heads/master | <file_sep>require'pry'
class TicTacToe
WIN_COMBINATIONS = [[0,1,2], [3,4,5], [6,7,8], [0,3,6], [1,4,7], [2,5,8], [0,4,8], [2,4,6]]
def initialize
@board = Array.new(9, " ")
end
def display_board
puts(" #{@board[0]} | #{@board[1]} | #{@board[2]} ")
puts("-----------")
puts(" #{@board[3]} | #{@board[4]} | #{@board[5]} ")
puts("-----------")
puts(" #{@board[6]} | #{@board[7]} | #{@board[8]} ")
end
def input_to_index(num)
num.to_i-1
end
def move(index, token = "X")
@board[index] = token
end
def position_taken?(index)
@board[index] != " "
end
def valid_move?(index)
index.between?(0,8) && !position_taken?(index)
end
def turn
puts "Please input number between 1-9:"
user_input = gets.strip
index = input_to_index(user_input)
cp = current_player
if valid_move?(index)
move(index, cp)
else
turn
end
display_board
end
def turn_count
counter = 0
@board.each{|x| counter+=1 if x!=" "; }
counter
end
def current_player
turn_count.even? ? "X" : "O"
end
def won?
WIN_COMBINATIONS.each do |win_combination|
position_1 = @board[win_combination[0]]
position_2 = @board[win_combination[1]]
position_3 = @board[win_combination[2]]
if position_1 == "X" && position_2 == "X" && position_3 == "X"
return win_combination
elsif position_1 =="O" && position_2 == "O" && position_3 == "O"
return win_combination
end
end
nil
end
def full?
9== @board.count{|position| position == "X" || position == "O"}
end
def draw?
!won? && full?
end
def over?
won? || full?
end
def winner
if won? != false
WIN_COMBINATIONS.each do |win_combination|
position_1 = @board[win_combination[0]]
position_2 = @board[win_combination[1]]
position_3 = @board[win_combination[2]]
if position_1 == "X" && position_2 == "X" && position_3 == "X"
return "X"
elsif position_1 =="O" && position_2 == "O" && position_3 == "O"
return "O"
end
end
nil
end
end
def play
turn until over? || draw?
puts draw? ? "Cat's Game!" : "Congratulations #{winner}!"
end
end
| 4a6f934fd333befcf0af2171e7064d54135ba157 | [
"Ruby"
] | 1 | Ruby | dwandrew/oo-tic-tac-toe-onl01-seng-ft-052620 | b2c2f33121f0887bba4368ee17ab129394f3efe2 | 6d8501e3390eba8a40b8c73809c1a7b1848fdf62 |
refs/heads/master | <file_sep>const MongoClient=require('mongodb').MongoClient;
MongoClient.connect('mongodb://localhost:27017/',{ useNewUrlParser: true },(err,client)=>{
if(err){
console.log('Could not connect!');
}
else {
console.log('Connected to database');
const db=client.db('TodoApp');
/*db.collection('Todos').insertOne({
Author: 'Sourav',
CourseName: 'Using Node with Mongo Db'
},(err,res)=>{
if(err){
return console.log('Could not insert');
}
console.log(JSON.stringify(res.ops,undefined,2));
});*/
db.collection('Users').insertOne({
Name:'Sourav',
Age: 27,
Location: 'Fargo'
},(err,res)=>{
if(err){
return console.log('Could not insert');
}
console.log(JSON.stringify(res.ops,undefined,2));
})
}
client.close();
});
<file_sep>"# mongodb-app"
<file_sep>const {MongoClient,ObjectId}=require('mongodb');
MongoClient.connect('mongodb://localhost:27017/',{ useNewUrlParser: true },(err,client)=>{
if(err){
return console.log('Could not connect to the database');
}
const db=client.db('TodoApp');
db.collection('Users').find(
{Name:'Sourav'}).toArray()
.then((docs)=>{
console.log(JSON.stringify(docs,undefined,2))
}).catch((err)=>{
console.log('Could not fetch data');
})
client.close();
}) | ebf8ba8645e05677e4e95a2ca403d1605e6b9eef | [
"JavaScript",
"Markdown"
] | 3 | JavaScript | sarkarsourav86/mongodb-app | 1b0fa1623ae006bcd75eb5801b8654c24627aeed | 8a2d713712d086f84fe11687edb9f5ad2408fbaf |
refs/heads/master | <repo_name>frontend-qin/java<file_sep>/admin_token_interceptor/src/main/java/com/admin/entity/User.java
package com.admin.entity;
import lombok.Data;
import java.util.Date;
@Data
public class User {
private Long id;
private String account;
private String password;
private Integer type;
private Date create;
}<file_sep>/README.md
# spring_boot_study
## 成果展示
<img src="./api.jpg">
<file_sep>/spring_boot_token/src/main/java/com/token/service/impl/UserServiceImpl.java
package com.token.service.impl;
import com.token.entity.User;
import com.token.service.IUserService;
import org.springframework.stereotype.Service;
@Service
public class UserServiceImpl implements IUserService {
@Override
public boolean checkUserInfo(String account, String password) {
String username = "lisi";
String pwd = "<PASSWORD>";
return username.equals(account) && pwd.equals(password) ? true : false;
}
@Override
public User getUserInfo(User user) {
return null;
}
}
<file_sep>/spring_cloud/README.md
#### project 目录
```bash
|-- changgou-parent ## 父工程
|-- changgou-common ## 公共方法
|-- changgou-common-db ## 微服务网关模块
|-- changgou-eureka ## 微服务注册中心
|-- changgou-gateway ## 微服务网关
|-- changgou-gateway ## 微服务网关模块
|-- changgou-service ## 微服务各个模块
|-- changgou-service-goods ## 微服务商品模块
|-- changgou-service-api ## 微服务javaBean, Feign, 熔断
|-- changgou-service--goods-api ## 微服务javaBean, Feign, 熔断
|-- changgou-web ## 视图页面
```
<file_sep>/admin_token_interceptor/src/main/java/com/admin/controller/UserController.java
package com.admin.controller;
import com.admin.entity.Token;
import com.admin.entity.User;
import com.admin.service.UserService;
import com.admin.utils.JwtToken;
import com.admin.utils.Result;
import com.admin.utils.SHAEncrypt;
import com.admin.utils.StatusCode;
import org.springframework.beans.factory.annotation.Autowired;
import org.springframework.web.bind.annotation.*;
import java.security.NoSuchAlgorithmException;
@RestController
@RequestMapping("user")
@CrossOrigin
public class UserController {
@Autowired
private UserService userService;
@Autowired
private JwtToken jwtToken;
@PostMapping("login")
public Result<Object> login(@RequestBody User user) throws NoSuchAlgorithmException {
// 1. 去数据库 匹配账号和密码
User account = this.userService.selectUserByAccount(user);
// 获取加密的密码
String shaStr = SHAEncrypt.getSHAStr(user.getPassword());
// 比较数据库查询的密码和输入的密码是否 一样
if(shaStr.equals(account.getPassword())){
account.setPassword(null);
// 生成token
String token = jwtToken.generateToken(account.getId(), account.getAccount());
System.out.println(token);
Token.saveToken = token;
// 创.建新的tokenUser对象
Token utoken = new Token();
utoken.setId(account.getId());
utoken.setAccount(account.getAccount());
utoken.setToken(token);
utoken.setType(account.getType());
return new Result<Object>(StatusCode.OK,"登录成功", utoken);
}
return new Result<Object>(StatusCode.ERROR,"账号或密码错误", "");
}
/**
* 创建一个账户
* @param user
* @return
* @throws NoSuchAlgorithmException
*/
@PostMapping("insert")
public Result<String> createUser(@RequestBody User user) throws NoSuchAlgorithmException {
// 先去数据库查找有木有该账户
User account = this.userService.selectUserByAccount(user);
// 如果为null , 说明不存在
if(account == null){
// 对密码进行加密
String pwd = SHAEncrypt.getSHAStr(user.getPassword());
user.setPassword(pwd);
System.out.println(user.toString());
this.userService.insertUser(user);
return new Result<String>(StatusCode.OK, "创建成功", "");
}
return new Result<String>(StatusCode.ERROR, "该用户已经存在", "");
}
}
<file_sep>/spring_boot_token/src/main/java/com/token/utils/TokenUtil.java
package com.token.utils;
import com.auth0.jwt.JWT;
import com.auth0.jwt.JWTVerifier;
import com.auth0.jwt.algorithms.Algorithm;
import com.auth0.jwt.exceptions.JWTCreationException;
import com.auth0.jwt.exceptions.JWTDecodeException;
import com.auth0.jwt.exceptions.JWTVerificationException;
import com.auth0.jwt.interfaces.DecodedJWT;
import java.util.Date;
import java.util.HashMap;
import java.util.Map;
import java.util.UUID;
public class TokenUtil {
/**
* 过期时间15秒
*/
protected static final long EXPIRE_TIME = 15 * 1000;
/**
* token私钥, 每次调用都使用UUID 重新生成一个私钥
*/
protected static final String PRIVATE_SECRET = UUID.randomUUID().toString();
// 参考文档： https://github.com/auth0/java-jwt
/**
* 签发签名 token
*
* @param account 用户账号
* @param userId 账号id
* @return String 的 token签名
*/
public static String signToken(String account, String userId) {
try {
// 过期时间
Date date = new Date(System.currentTimeMillis() + EXPIRE_TIME);
// 参考: https://github.com/auth0/java-jwt#create-and-sign-a-token
// 私钥及加密 using HS256
Algorithm algorithm = Algorithm.HMAC256(PRIVATE_SECRET);
// 头信息 setting
Map<String, Object> header = new HashMap<String, Object>(2); // 暂定设置容量为 2
header.put("type", "JWT");
header.put("alg", "HS256");
// 生成签名, 带上参数
String token = JWT.create()
.withHeader(header)
.withClaim("loginname", account)
.withClaim("userId", userId)
.withExpiresAt(date)
.sign(algorithm);
// 返回 生成的 token 字符串
return token;
} catch (JWTCreationException e) {
return null;
}
}
// 参考: https://github.com/auth0/java-jwt#verify-a-token
/**
* 验证 token
*
* @param token 生成的token信息
* @return 返回 boolean值 (true 有效 | false 失效)
*/
public static boolean virfityToken(String token) {
try {
Algorithm algorithm = Algorithm.HMAC256(PRIVATE_SECRET);
JWTVerifier verifier = JWT.require(algorithm).build(); //Reusable verifier instance
DecodedJWT jwt = verifier.verify(token);
return true;
} catch (JWTVerificationException exception) {
return false;
}
}
/**
* 解析 token
* @param token 生成的token
* @return 返回 DecodedJWT对象
*/
public static DecodedJWT ParsingToken(String token) {
try {
DecodedJWT jwt = JWT.decode(token);
return jwt;
} catch (JWTDecodeException exception) {
return null;
}
}
}
<file_sep>/spring_boot_token/src/main/java/com/token/entity/UserToken.java
package com.token.entity;
import lombok.Data;
@Data
public class UserToken extends User {
private String token;
}
<file_sep>/admin_token_interceptor/src/main/java/com/admin/service/impl/UserServiceImpl.java
package com.admin.service.impl;
import com.admin.entity.User;
import com.admin.mapper.UserMapper;
import com.admin.service.UserService;
import org.springframework.beans.factory.annotation.Autowired;
import org.springframework.stereotype.Service;
@Service
public class UserServiceImpl implements UserService {
@Autowired
private UserMapper userMapper;
@Override
public User selectUserByAccount(User user) {
return this.userMapper.selectUserByAccount(user);
}
@Override
public void insertUser(User user) {
this.userMapper.insertUser(user);
}
}
<file_sep>/spring_boot_token/README.md
##### token 签发
#### 依赖
[java_token](!https://github.com/auth0/java-jwt)
#### 项目目录
```bash
|-- com.token
|-- controller
|-- UserController.java # user模块的路由请求
|-- entity # 实体对象
|-- User
|-- UserToken
|-- interceptor # 拦截器
|-- RequestInterceptor # 拦截器过滤器及自定义拦截配置生效
|-- RouterInterceptor # 自定义路由请求拦截器
|-- service
|-- impl
|-- UserServiceImpl # user模块下的业务逻辑实现
|-- IUserService # 接口
|-- utils
|-- ResultUtil # 统一返回给前端的结果集
|-- StatusCode # 返回的状态码
|-- TokenUtil # token 生成， 验证， 解析方法
```
### 请求
```bash
http:localhost:8080/user/login
- type： post
- body: {account:"lisi", password:"<PASSWORD>"}
- response: {code:"", message:"", data: ""}
```
```bash
http:localhost:8080/user/shops
- type： get
- params: {}
- response: {code:"", message:"", data: ""}
```
<img src="./1.jpg"/>
<img src="./2.jpg"/>
<img src="./3.jpg"/> <file_sep>/admin_token_interceptor/src/main/java/com/admin/utils/SHAEncrypt.java
package com.admin.utils;
import java.math.BigInteger;
import java.security.MessageDigest;
import java.security.NoSuchAlgorithmException;
/**
* SHA 密码加密
*/
public class SHAEncrypt {
/**
* 直接获取加密后的字符串
* @param password 传入的密码
* @return 加密后的字符串
* @throws NoSuchAlgorithmException
*/
public static String getSHAStr(String password) throws NoSuchAlgorithmException {
MessageDigest md = MessageDigest.getInstance("SHA");
md.update(password.getBytes());
return new BigInteger(md.digest()).toString(32);
}
}
<file_sep>/spring_boot_mybatis_crud/src/main/resources/student.sql
CREATE TABLE `student` (
`id` int(11) NOT NULL AUTO_INCREMENT,
`name` varchar(20) DEFAULT NULL,
`age` int(11) DEFAULT NULL,
`money` bigint(255) DEFAULT NULL,
`gender` int(1) DEFAULT NULL,
`score` int(5) DEFAULT NULL,
`class_name` varchar(15) DEFAULT NULL,
PRIMARY KEY (`id`)
) ENGINE=InnoDB AUTO_INCREMENT=11 DEFAULT CHARSET=utf8;<file_sep>/spring_cloud/changgou-parent/changgou-service-api/changgou-service-goods-api/src/main/java/com/goods/pojo/Brand.java
package com.goods.pojo;
import lombok.Data;
import javax.persistence.Id;
import javax.persistence.Table;
@Table(name ="tb_brand")
@Data
public class Brand {
@Id
private Long id;
private String name;
private String image;
private String letter;
private Integer seq;
}
<file_sep>/admin_token_interceptor/src/main/java/com/admin/service/UserService.java
package com.admin.service;
import com.admin.entity.User;
public interface UserService {
User selectUserByAccount(User user);
void insertUser(User user);
}
| bd5cc4dd8b8b98842a27942eaedcb775f2e7d830 | [
"Markdown",
"Java",
"SQL"
] | 13 | Java | frontend-qin/java | 38012e54957bfd26f8aaa5d05f34159abf37573c | aee7f3558f3413f22e8f82f4134a0007610ce32f |
refs/heads/main | <repo_name>natamartya/DigimonHunterProject<file_sep>/src/main/java/com/example/uxproject/patamonDetails.java
package com.example.projectux;
import androidx.appcompat.app.AlertDialog;
import androidx.appcompat.app.AppCompatActivity;
import android.os.Bundle;
import android.view.View;
import android.widget.Button;
import android.widget.EditText;
public class patamonDetails extends AppCompatActivity {
int qtyPatamon;
Button orderBtn;
@Override
protected void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.activity_patamon_details);
initPatamon();
orderBtn.setOnClickListener(new View.OnClickListener() {
@Override
public void onClick(View v) {
if(qtyPatamon < 1 || qtyPatamon > 20){
AlertDialog.Builder dialog = new AlertDialog.Builder(patamonDetails.this);
dialog.setTitle("Error!");
dialog.setMessage("Quantity should be between 1-20!");
dialog.show();
}
else{
AlertDialog.Builder dialog = new AlertDialog.Builder(patamonDetails.this);
dialog.setTitle("Congratulations!");
dialog.setMessage("You have successfully ordered!");
dialog.show();
}
}
});
}
private void initPatamon(){
qtyPatamon = R.id.qtyPatamon;
orderBtn = findViewById(R.id.orderBtn);
}
}
<file_sep>/src/main/java/com/example/uxproject/homegold.java
package com.example.uxproject;
import androidx.appcompat.app.AppCompatActivity;
import android.content.Intent;
import android.os.Bundle;
import android.view.View;
import android.widget.Button;
import android.widget.ImageButton;
import android.widget.Toast;
public class homegold extends AppCompatActivity {
@Override
protected void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.activity_homegold);
ImageButton logoutButton = (ImageButton)findViewById(R.id.logoutBtn);
logoutButton.setOnClickListener(new View.OnClickListener() {
@Override
public void onClick(View v) {
Intent intentI = new Intent(homegold.this, MainActivity.class);
startActivity(intentI);
finish();
Toast.makeText(homegold.this, "Successfully Logout", Toast.LENGTH_SHORT).show();
}
});
// ImageButton digimonButton = (ImageButton)findViewById(R.id.digimonBtn);
// digimonButton.setOnClickListener(new View.OnClickListener() {
// @Override
// public void onClick(View v) {
// Intent intentI = new Intent(homegold.this, digimonPage.class);
// startActivity(intentI);
// }
// });
//
// ImageButton contactusButton = (ImageButton)findViewById(R.id.contactusBtn);
// contactusButton.setOnClickListener(new View.OnClickListener() {
// @Override
// public void onClick(View v) {
// Intent intentI = new Intent(homegold.this, contactusPage.class);
// startActivity(intentI);
// }
// });
Button bronzeButton = (Button) findViewById(R.id.bronzeBtn);
bronzeButton.setOnClickListener(new View.OnClickListener() {
@Override
public void onClick(View v) {
Intent intentI = new Intent(homegold.this, home.class);
startActivity(intentI);
}
});
Button silverButton = (Button) findViewById(R.id.silverBtn);
silverButton.setOnClickListener(new View.OnClickListener() {
@Override
public void onClick(View v) {
Intent intentI = new Intent(homegold.this, homesilver.class);
startActivity(intentI);
}
});
}
}
<file_sep>/src/main/java/com/example/uxproject/home.java
package com.example.uxproject;
import androidx.appcompat.app.AppCompatActivity;
import android.content.Intent;
import android.os.Bundle;
import android.view.View;
import android.widget.Button;
import android.widget.ImageButton;
import android.widget.Toast;
public class home extends AppCompatActivity {
@Override
protected void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.activity_home);
ImageButton logoutButton = (ImageButton)findViewById(R.id.logoutBtn);
logoutButton.setOnClickListener (new View.OnClickListener(){
@Override
public void onClick(View v) {
Intent intentL = new Intent(home.this, MainActivity.class);
startActivity(intentL);
finish();
Toast.makeText(home.this, "Successfully Logout", Toast.LENGTH_SHORT).show();
}
});
// ImageButton digimonButton = (ImageButton)findViewById(R.id.digimonBtn);
// digimonButton.setOnClickListener (new View.OnClickListener(){
//
// @Override
// public void onClick(View v) {
// Intent intentL = new Intent(home.this, digimonPage.class);
// startActivity(intentL);
// }
// });
//
// ImageButton contactusButton = (ImageButton)findViewById(R.id.contactusBtn);
//
// contactusButton.setOnClickListener (new View.OnClickListener(){
//
// @Override
// public void onClick(View v) {
// Intent intentL = new Intent(home.this, contactusPage.class);
// startActivity(intentL);
// }
// });
Button silverButton = (Button)findViewById(R.id.silverBtn);
silverButton.setOnClickListener(new View.OnClickListener(){
@Override
public void onClick(View v) {
Intent intentL = new Intent(home.this, homesilver.class);
startActivity(intentL);
}
});
Button goldButton = (Button)findViewById(R.id.goldBtn);
goldButton.setOnClickListener(new View.OnClickListener(){
@Override
public void onClick(View v) {
Intent intentL = new Intent(home.this, homegold.class);
startActivity(intentL);
}
});
}
}
| 7f2ea8cf67a68b5e604e37890874446aee828566 | [
"Java"
] | 3 | Java | natamartya/DigimonHunterProject | 39265c5cc4ba7670e909c065a85932a7ab2dd1c0 | 853a5ca68c7996ec8fbc6b062ed1ce1df3571a6c |
refs/heads/main | <repo_name>devtitaro/python-marathon<file_sep>/README.md
# python-marathon
This repository that will contain all the python programs I will build for the purpose of mastering the python programming language.
<file_sep>/console_calculator.py
# Author: <NAME>
# Twitter: devtitaro_
# Facebook: devtitaro
# Aim: Creating a console based calculator in python using incremental development
# Import the math module
import math
# Create the addition function
def addition(param1, param2):
# Evaluate the result and assign it's value to a variable
result = param1 + param2
# Return the result
return result
# Create the main function
def main():
print('Hello World!') | 56e8b820bed058c7ab5e78e8d4be2a4597a1152c | [
"Markdown",
"Python"
] | 2 | Markdown | devtitaro/python-marathon | 1a3deaa22ce078f779554a76072d65ff41988a0b | 69bbafa3a5c42fb9fef793487790dd2c5ba3a7ae |
refs/heads/master | <file_sep>class WeatherReading:
def __init__(self, weather_type, reading, day):
self.weather_type = weather_type
self.reading = reading
self.day = day
def get_weather_type(self):
return self.weather_type
def __str__(self):
return str(self.day) + '|' +self.weather_type + '|' + str(self.reading)<file_sep>from markov import *
from linear_learner import *
from weather_model import *
from normal_distribution import *
import pdb
class WeatherModelCreater:
def __init__(self,weather_records):
self.weather_records = weather_records
def create_model_from_data(self):
states = [States.Rainy,States.Sunny]
transitionProbabilities = [[0.8,0.2],
[0.6,0.4]]
weather_markov_chain = MarkovChain(states, transitionProbabilities)
humidity_learner = LinearLearner(self.weather_records.get_temperature_readings(), self.weather_records.get_humidity_readings())
humidity_model = humidity_learner.learn()
rainy_records = self.weather_records.get_rainy_day_records()
sunny_records = self.weather_records.get_sunny_day_records()
rainy_sd = rainy_records.temperature_standard_deviation()
sunny_sd = sunny_records.temperature_standard_deviation()
rainy_mean = rainy_records.temperature_mean()
sunny_mean = sunny_records.temperature_mean()
rainy_normal_dist = NormalDistribution(rainy_mean,rainy_sd)
sunny_normal_dist = NormalDistribution(sunny_mean,sunny_sd)
weather_model = WeatherModel(weather_markov_chain, humidity_model, rainy_normal_dist, sunny_normal_dist)
return weather_model
<file_sep>from io.weather_record_parser import WeatherRecordParser
from models.weather_model_creator import WeatherModelCreater
from weather_generator import WeatherGenerator
from io.input_reader import InputReader
def print_sequence(city, weather_sequence):
for weather_reading in weather_sequence:
print(str(city) + '|'+ str(weather_reading))
if __name__=='__main__':
input_args = InputReader().load()
for city in input_args.city_data.keys():
weather_record_parser = WeatherRecordParser( input_args.city_data[city] )
weather_records = weather_record_parser.parse_weather_records()
weather_model_creator = WeatherModelCreater(weather_records)
weather_model = weather_model_creator.create_model_from_data()
weather_generator = WeatherGenerator(city, weather_model)
weather_sequence = weather_generator.generate_weather_sequence(input_args.sequence_count, input_args.start_date)
print_sequence(city, weather_sequence)
<file_sep>from scipy import stats
from linear_model import LinearModel
class LinearLearner:
def __init__(self, training_x,training_y):
self.training_x = training_x
self.training_y = training_y
def learn(self):
slope,intercept,r,p,s_err = stats.linregress(self.training_x, self.training_y)
return LinearModel(slope, intercept)
<file_sep># Weather-generator
##### Generate reasonably realistic weather sequences
Language : Python 2.7
* I. External libraries used in the solution :
* Numpy
* for manipulation of the datasets
* random sampling from the transition probabilities of the markov chain with random.choice function
* random sampling from the normal distribution
* Scipy
* for parameter estimation of the linear model using simple linear regression
* Pytest : for unit tests
* II. General(and weak) relations between weather variables utilised in the toy model :
* Precipitation inversely proportional to Temperature
* Relative Humidity inversely proportional to Temperature (water holding capacity of air increases with temperature thereby reducing rh)
* Pressure inversely proportional to Elevation
* III. Model details / approach taken :
* Weather evolves over time. The kind of weather on day n has a dependency on the weather on day n-1. For eg: if it rains today, there is a higher probability of having rain tomorrow as well than tomorrow being very hot. This weather evolution over time is captured using a two state Markov chain, with sensible transition probabilities (Rainy day -> Sunny day for eg.) .
* Once the weather type is sampled from the markov chain , temperature is generated from a normal distribution with mean & standard deviation calculated from the previous year data (Temperature here is assumed to be normally distributed given a weather type , which is a simplifying assumption)
* Humidity is then derived from Temperature using the fact that humidity is inversely proportional to Temperature (See II) .This is modeled using a linear model whose parameters are calculated from previous year data using linear regression . The two parameters of the model are slope & the intercept , which define a "y = m*x +c" linear relation. scipy is used for the parameter estimation.
* IV. Code/Folder structure
* models : has classes which abstracts the mathematical models used like MarkovChain , LinearModel etc
* domain : the domain classes like WeatherRecord , City etc
* io : all classes which deals with reading the input , parsing the data files used for parameter estimation
* tests : unit tests
* data : all the data files for each city in a IATACODE.csv format
* V. Further Improvements :
* Estimating Markov chain transition probabilities from data
* Add more states to the chain like Cloudy / Snowy etc
* Use of time series models like Moving Average/autoregressive models(ARIMA) for better modelling of weather variables
* Better modelling of temperature by including more physical parameters
* Including topographical features of the place into the model explicitly
* VI. Notes
* Data from 5 cities are included
* test_input file contains the city names for which weather has to be generated. If the corresponding city's previous year weather data is missing, Sydneys (SYD) data file will be used for parameter estimation
Instructions to run :
i) Run tests
pip install -r requirements-test.txt
py.test 'tests'
ii) Run program
pip install -r requirements.txt
python GenerateWeather.py
or
python GenerateWeather.py |sequence_length|
* Note : Default Sequence length is 10
* Output format :
City_Code|Coordinates|Date|Temperature|Humidity
* Sample Output :
~~~
PER|-31.56,115.58,20|2016-07-03|Sunny|25.2|46.8
PER|-31.56,115.58,20|2016-07-04|Rainy|12.3|70.5
PER|-31.56,115.58,20|2016-07-05|Sunny|14.1|67.3
ADL|-34.56,138.31,30|2016-07-03|Rainy|20.8|71.4
ADL|-34.56,138.31,30|2016-07-04|Rainy|28.0|76.2
ADL|-34.56,138.31,30|2016-07-05|Sunny|27.6|75.9
SYD|-33.86,151.12,39|2016-07-03|Sunny|11.6|63.3
SYD|-33.86,151.12,39|2016-07-04|Rainy|20.7|64.4
SYD|-33.86,151.12,39|2016-07-05|Rainy|17.0|63.9
DRW|-12.24,130.52,34|2016-07-03|Sunny|26.4|64.0
DRW|-12.24,130.52,34|2016-07-04|Rainy|26.9|65.2
DRW|-12.24,130.52,34|2016-07-05|Sunny|30.2|74.4
BNE|-27.23,153.07,35|2016-07-03|Rainy|25.8|74.7
BNE|-27.23,153.07,35|2016-07-04|Rainy|25.2|74.3
BNE|-27.23,153.07,35|2016-07-05|Rainy|21.4|71.8
<file_sep>import numpy as np
import random
class MarkovChain:
def __init__(self, states, transition_probabilities):
self.states = states
self.transition_probabilities = transition_probabilities
def forecast_next(self, previous_state):
transition_pos = self.states.index(previous_state)
next_state = np.random.choice(self.states, p=self.transition_probabilities[transition_pos])
return next_state<file_sep># abstracts a very simple linear model of the form y = m*x + c
class LinearModel:
def __init__(self, slope, intercept):
self.m = slope
self.c = intercept
def predict(self, x):
return self.m * x + self.c
<file_sep>from unittest import TestCase
from domain.weather_record import WeatherRecord
from domain.weather_reading import WeatherReading
from datetime import date
class TestWeatherReading(TestCase):
def test_should_give_correct_string_format(self):
weather_record = WeatherRecord([100], [85],23)
weather_reading = WeatherReading('Rainy',weather_record, date(2015,1,14))
self.assertEquals('2015-01-14|Rainy|100|85' , str(weather_reading))<file_sep>from unittest import TestCase
from unittest.mock import patch
from domain.weather_record import WeatherRecord
class TestWeatherRecord(TestCase):
def test_should_flag_rainy_day_when_precipitation_beyond_limit(self):
weather_record = WeatherRecord(100, 85,23)
self.assertTrue(weather_record.is_rainy())
def test_should_flag_rainy_day_when_precipitation_below_limit(self):
weather_record = WeatherRecord(100, 85,12)
self.assertFalse(weather_record.is_rainy())<file_sep>import csv
from domain.weather_record import WeatherRecords,WeatherRecord
class WeatherRecordParser:
def __init__(self, data_file):
self.data_file = data_file
self.columns_to_read = ['Mean TemperatureC', ' Mean Humidity', ' Mean Sea Level PressurehPa', 'Precipitationmm']
def parse_weather_records(self):
reader=csv.DictReader(open(self.data_file, 'r'))
records = [ [ float(record[column]) for column in self.columns_to_read] for record in list(reader) ]
weather_records = WeatherRecords( list(map( lambda record: WeatherRecord(record[0], record[1], record[3]) , records)) )
return weather_records
<file_sep>import numpy as np
class WeatherRecord:
def __init__(self, mean_temperature = 0, mean_humidity = 0, precipitation = 0):
self.mean_temperature = mean_temperature
self.mean_humidity = mean_humidity
self.precipitation = precipitation
def temperature(self):
return self.mean_temperature
def humidity(self):
return self.mean_humidity
def is_rainy(self):
return self.precipitation > 15
def __str__(self):
return str( np.around(self.temperature()[0],1) ) + '|' + str(np.around(self.humidity()[0],1))
class WeatherRecords:
def __init__(self,records):
self.records = records
def get_temperature_readings(self):
return [ record.temperature() for record in self.records]
def get_humidity_readings(self):
return [ record.humidity() for record in self.records]
def get_rainy_day_records(self):
return WeatherRecords([record for record in self.records if record.is_rainy()])
def get_sunny_day_records(self):
return WeatherRecords([record for record in self.records if not record.is_rainy()])
def temperature_mean(self):
return np.array(self.get_temperature_readings()).mean()
def temperature_standard_deviation(self):
return np.array(self.get_temperature_readings()).std() <file_sep>from unittest import TestCase
from models.markov import MarkovChain
class TestMarkovChain(TestCase):
def test_should_return_next_state_when_transition_probability_is_one(self):
markov_chain = MarkovChain([1,2], [[0,1],
[1,0]])
next_state = markov_chain.forecast_next(1)
self.assertEquals(2, next_state)
def test_should_stay_in_current_state_when_transition_probability_is_zero(self):
markov_chain = MarkovChain([1,2], [[1,0],
[1,0]])
next_state = markov_chain.forecast_next(1)
self.assertEquals(1, next_state)<file_sep>from domain.city import City
import os
import sys
from datetime import date
DEFAULT_CITY = 'SYD'
DEFAULT_DAYS_COUNT = 10
DEFAULT_START_DATE = date.today()
DATA_DIRECTORY = 'data'
class Input:
def __init__(self,sequence_count, city_data, start_date):
self.sequence_count = sequence_count
self.city_data = city_data
self.start_date = start_date
class InputReader:
def load_input_cities(self):
test_file_lines = open('test_input.data','r').readlines()
cities = [ City(test_line.strip().split('|')[0], test_line.strip().split('|')[1]) for test_line in test_file_lines]
return cities
def get_past_data_file_for_city(self, city):
file_name = self.construct_data_file_name(city)
if(os.path.isfile(file_name)):
return file_name
else:
return self.construct_data_file_name(DEFAULT_CITY)
def get_sequence_count(self,):
return int(sys.argv[1]) if(len(sys.argv) > 1) else DEFAULT_DAYS_COUNT
def construct_data_file_name(self, city):
file_name = city.get_code()+'.csv'
return os.path.join(DATA_DIRECTORY, file_name)
def load(self):
cities = self.load_input_cities()
city_data = {}
for city in cities:
city_data[city] = self.get_past_data_file_for_city(city)
return Input(self.get_sequence_count(), city_data, DEFAULT_START_DATE)<file_sep>class City:
def __init__(self, code, coordinates):
self.code = code
self.coordinates = coordinates
def get_code(self):
return self.code
def __str__(self):
return str(self.code) + '|' + str(self.coordinates)<file_sep>from unittest import TestCase
from unittest.mock import patch
from models.linear_model import LinearModel
class TestLinearModel(TestCase):
def test_should_return_identity_values_for_slope_one_and_intercept_zero(self):
linear_model = LinearModel(1, 0)
self.assertEquals(11, linear_model.predict(11))
<file_sep>from domain.weather_record import WeatherRecords,WeatherRecord
from domain.weather_reading import WeatherReading
class States:
Rainy = 'Rainy'
Sunny = 'Sunny'
class WeatherModel:
def __init__(self,weather_markov_chain, humidity_model, rainy_normal_dist, sunny_normal_dist):
self.weather_markov_chain = weather_markov_chain
self.humidity_model = humidity_model
self.state_temperature_dists = {
States.Sunny : sunny_normal_dist,
States.Rainy : rainy_normal_dist,
}
def generate_next_reading(self, previous_state, day):
next_weather_type = self.weather_markov_chain.forecast_next(previous_state)
temperature = self.state_temperature_dists[next_weather_type].get_sample()
humidity = self.humidity_model.predict(temperature)
return WeatherReading(next_weather_type, WeatherRecord(temperature, humidity), day )
<file_sep>import random
from models.weather_model import WeatherModel,States
from datetime import timedelta
class WeatherGenerator:
def __init__(self, city, weather_model):
self.city = city
self.weather_model = weather_model
def generate_weather_sequence(self, no_days, start_date):
weather_sequence = []
states = [States.Rainy,States.Sunny]
current_state = random.choice(states)
current_day = start_date
for day in range(no_days):
next_reading = self.weather_model.generate_next_reading(current_state, current_day)
weather_sequence.append(next_reading)
current_state = next_reading.get_weather_type()
current_day = current_day + timedelta(days=1)
return weather_sequence
<file_sep>import numpy as np
import pdb
class NormalDistribution:
def __init__(self, mean, sd):
self.mean = mean
self.sd = sd
def get_sample(self):
# pdb.set_trace()
return np.random.normal(self.mean, self.sd, 1) | 1f26d812d663436c780ef02c3bc1f372aa0ddbaf | [
"Markdown",
"Python"
] | 18 | Python | hari-sree/weather-generator | 5519a3b5118c63371274884b5ee3eb0f2aad6231 | 75827153b51b6ef33c4e1abef8112474805d4b39 |
refs/heads/master | <file_sep>
[](https://github.com/herophilus/rtg_score/blob/master/example/Example_qPCR.ipynb)
# Rank-To-Group (RTG) score evaluates contribution of confounders
<img src="https://github.com/System1Bio/rtg_score/blob/master/example/confounder_contribution.png?raw=true" width="500" />
Batch, cell line, donor, plate, reprogramming, protocol — these and other confounding factors influence cell cultures *in vitro*.
RTG score tracks contribution of different factors to variability by estimating how **R**ank maps **T**o **G**roup.
Scoring relies on ranking by similarity, so there are no explicit or implicit assumptions of linearity.
RTG perfectly works with both well-interpretable data (gene expressions, cell types)
and embeddings provided by deep learning.
## Usage
`rtg_score` is a Python package. Installation:
```bash
pip install rtg_score
```
RTG score requires two DataFrames: one with confounds and one with embeddings (or other features, e.g. gene expressions)
```python
from rtg_score import compute_RTG_score
# following code corresponds to computing an element of the figure above
# (exclude same organoid_id and batch+donor)
score = compute_RTG_score(
metadata=confounders_metadata,
include_confounders=['batch', 'donor'],
exclude_confounders=['organoid_id'],
embeddings=qpcr_delta_ct,
)
```
Use `compute_RTG_contribution_matrix` to compute multiple RTG scores in a bulk . <br />
Example + code for plotting are available in [`example`](https://github.com/System1Bio/rtg_score/blob/master/example/Example_qPCR.ipynb) subfolder.
## Parameters
- `metadata` - DataFrame with confounding variables
- sample_id, batch, donor, clone, plate, etc.
- `embeddings` - numerical description of samples (DataFrame or 2d array).
- Examples: qPCR delta Cts, deep learning embeddings, cell types fractions
- `metric` - how to define similarity?
- use `euclidean` for qPCR and various embeddings
and `hellinger` for cell type distributions
- included and excluded confounders in example:
- including ['donor', 'batch'] and excluding ['clone', 'plate'] will estimate
how similar are samples with same donor **and** same batch,
while omitting pairs which have same clone **or** grown on the same plate
- most use-cases are simple, like include batch effect while exclude plate,
but framework is very flexible
## Example analysis
[Preprint](https://www.biorxiv.org/content/10.1101/2020.08.26.251611v1) demonstrates application of RTG score to multimodal analysis of cerebral organoids,
and demonstrates which conclusions can be drawn.
See [`example`](https://github.com/System1Bio/rtg_score/blob/master/example/Example_qPCR.ipynb) subfolder for an actual code.
<file_sep>from itertools import combinations
import numpy as np
import pandas as pd
from rtg_score import compute_RTG_contribution_matrix
def test_random_contributions(n_samples=1000, n_metadata_columns=3, n_categories=10, n_features=10):
rng = np.random.RandomState(42)
metadata = pd.DataFrame(
data=rng.randint(0, n_categories, size=[n_samples, n_metadata_columns]),
columns=[f'Conf{i}' for i in range(1, 1 + n_metadata_columns)]
)
# all elements are positive, to allow hellinger's distance computation
embeddings = rng.uniform(0, 1, size=[n_samples, n_features])
include_confounders_dict = {
'Conf1': ['Conf1'],
'Conf2': ['Conf2'],
'Conf12': ['Conf1', 'Conf2'],
}
exclude_confounders_dict = {
'Conf2': ['Conf2'],
'Conf3': ['Conf3'],
'Conf13': ['Conf3', 'Conf1'],
}
# check that all
dataframes = {
metric: compute_RTG_contribution_matrix(
metadata,
include_confounders_dict=include_confounders_dict,
exclude_confounders_dict=exclude_confounders_dict,
metric=metric,
embeddings=embeddings,
)
for metric in ['euclidean', 'hellinger', 'cosine']
}
# verify all scores are close to 0.5
for metric, metric_df in dataframes.items():
assert np.max(abs(metric_df - 0.5).stack().dropna()) < 0.05
for metric1, metric2 in combinations(dataframes.keys(), r=2):
assert not np.allclose(dataframes[metric1], dataframes[metric2], equal_nan=True)
<file_sep>from setuptools import setup
setup(
name="rtg_score",
version='0.1.0',
description="Analysis of confounders by Rank-to-Group scores",
long_description=open('README.md', encoding='utf-8').read(),
long_description_content_type='text/markdown',
author='<NAME>, System1 Biosciences',
packages=['rtg_score'],
classifiers=[
'Intended Audience :: Science/Research',
'Programming Language :: Python :: 3 ',
],
keywords='variability analysis, variability decomposition, contributing factors',
install_requires=[
'numpy',
'scipy',
'pandas',
'scikit-learn',
],
)<file_sep>from rtg_score import compute_RTG_contribution_matrix, compute_RTG_score
import pandas as pd
import numpy as np
from pathlib import Path
repo_root = Path(__file__).parent.parent
def prepare_qpcr():
filename = repo_root / 'example/expression_data.csv'
expression_with_metadata = pd.read_csv(filename, sep='\t')
expression_with_metadata.head()
genes_expression = expression_with_metadata[
['Gene1', 'Gene2', 'Gene3', 'Gene4', 'Gene5', 'Gene6', 'Gene7', 'Gene8']].copy()
# compute delta Ct
genes_delta_ct = genes_expression.sub(genes_expression['Gene1'], axis=0).drop(columns='Gene1')
# normalize contribution of each gene
genes_delta_ct_normalized = genes_delta_ct.div(genes_delta_ct.std())
return expression_with_metadata, genes_delta_ct_normalized
def test_against_reference():
expression_with_metadata, genes_delta_ct_normalized = prepare_qpcr()
for use_fast in [True, False, 'auto']:
contribution_matrix = compute_RTG_contribution_matrix(
expression_with_metadata,
include_confounders_dict={
'batch': ['batch'],
'donor': ['donor'],
'clone': ['clone'],
'batch+\ndonor': ['batch', 'donor'],
'batch+\nclone': ['batch', 'clone'],
},
exclude_confounders_dict={
'exclude same\norganoid': ['organoid_id'],
'exclude same\nclone': ['clone'],
'exclude same\ndonor': ['donor'],
'exclude same\nbatch': ['batch'],
},
embeddings=genes_delta_ct_normalized,
use_fast_computations=use_fast,
)
reference_result = {
'batch': {'exclude same\norganoid': 0.5995943128819183,
'exclude same\nclone': 0.581381293631887,
'exclude same\ndonor': 0.5717474846071052,
'exclude same\nbatch': np.nan},
'donor': {'exclude same\norganoid': 0.6627428876496726,
'exclude same\nclone': 0.602667260670832,
'exclude same\ndonor': np.nan,
'exclude same\nbatch': 0.623785995680053},
'clone': {'exclude same\norganoid': 0.7234854098248196,
'exclude same\nclone': np.nan,
'exclude same\ndonor': np.nan,
'exclude same\nbatch': 0.6606615343718841},
'batch+\ndonor': {'exclude same\norganoid': 0.8121230673103979,
'exclude same\nclone': 0.6930298371813395,
'exclude same\ndonor': np.nan,
'exclude same\nbatch': np.nan},
'batch+\nclone': {'exclude same\norganoid': 0.9372202606462032,
'exclude same\nclone': np.nan,
'exclude same\ndonor': np.nan,
'exclude same\nbatch': np.nan}
}
assert np.allclose(pd.DataFrame(reference_result), contribution_matrix, equal_nan=True)
def test_internal_agreement():
expression_with_metadata, genes_delta_ct_normalized = prepare_qpcr()
scores = compute_RTG_contribution_matrix(
expression_with_metadata,
include_confounders_dict={
'batch': ['batch'],
'donor': ['donor'],
'clone': ['clone'],
'clone+donor': ['clone', 'donor']
},
exclude_confounders_dict={
'exclude donor': ['donor'],
'exclude clone+donor': ['clone', 'donor'],
'exclude batch': ['batch'],
'exclude batch+organoid_id': ['batch', 'organoid_id'],
},
embeddings=genes_delta_ct_normalized,
)
# exclusion works as union
assert scores.loc['exclude donor'].equals(scores.loc['exclude clone+donor'])
assert scores.loc['exclude batch'].equals(scores.loc['exclude batch+organoid_id'])
# inclusion works as intersection
assert scores['clone'].equals(scores['clone+donor'])
<file_sep>"""
RTG score:
statistical tool to check contribution of confounding variables to biological models.
Works with any modality
"""
from typing import List, Dict
import numpy as np
import pandas as pd
from scipy.stats import mannwhitneyu
from sklearn.metrics import roc_auc_score, pairwise_distances as sklearn_pairwise_distances
__version__ = '0.1.0'
class InputErrorRTG(RuntimeError):
"""Generic error caused by incorrect input"""
pass
def to_codes(array):
"""replace categories with unique integer codes"""
return np.unique(array, return_inverse=True)[1]
def to_codes_str_series(array):
"""replace categories with unique string codes"""
return pd.Series(to_codes(array)).map(str)
def compute_pairwise_distances(
n_samples,
embeddings=None,
pairwise_distances=None,
metric='euclidean',
):
if (pairwise_distances is None) + (embeddings is None) != 1:
raise RuntimeError('Embeddings or pairwise_distances should be provided (only one, not both)')
if pairwise_distances is None:
embeddings = np.asarray(embeddings)
assert np.ndim(embeddings) == 2, 'embeddings should be 2-dimensional metric [n_samples, n_features]'
assert len(embeddings) == n_samples, 'number of embeddings should be the same as number of rows in metadata'
if metric == 'hellinger':
if np.min(embeddings) < 0:
raise InputErrorRTG('Hellinger distance requires non-negative elements in embedding')
return sklearn_pairwise_distances(np.sqrt(embeddings), metric='euclidean')
return sklearn_pairwise_distances(embeddings, metric=metric)
else:
if metric != 'euclidean':
raise RuntimeWarning(f'Passed metric ({metric}) not used as distances are passed')
assert pairwise_distances.shape == (n_samples, n_samples), 'wrong shape of distances passed'
return pairwise_distances
def compute_mannwhitneyu_roc_auc_score(x, y):
x, y = x[~np.isnan(x)], y[~np.isnan(y)]
if len(x) > 0 and len(y) > 0:
res = mannwhitneyu(x, y, alternative='greater')
return res.statistic / len(x) / len(y)
else:
return np.nan
def compute_RTG_score(
metadata: pd.DataFrame,
include_confounders: List[str],
exclude_confounders: List[str],
*,
embeddings=None,
metric='euclidean',
pairwise_distances=None,
method: str = 'RTG',
minimal_n_samples=30,
use_fast_computations='auto',
) -> float:
"""
Compute (single) RTG score.
:param metadata: DataFrame with confounds (may contain additional variables) of shape [n_samples, n_variables].
Examples of variables: clone, donor, batch, plate, position on a plate
:param include_confounders: list of confounders to estimate their joint contribution
Example: pass ['batch', 'donor']
:param exclude_confounders: list of confounders to exclude,
Example: ['clone', 'plate']
Explanation: if ['batch', 'donor'] are included while ['clone', 'plate'] are excluded, we measure how much
samples with the same batch AND donor, but different clones AND different plates are similar to each other.
:param embeddings: numerical description of each sample. DataFrame or np.array of shape [n_sample, n_features].
Order of embeddings should match order of rows in metadata
:param metric: distance used to evaluate similarity. Possible choices are:
- 'euclidean', relevant e.g. for delta Ct gene expression or for different embeddings
- 'hellinger', relevant e.g. for cell type fractions in scRNA-seq
- 'cosine', frequently more appropriate for DL embeddings
- other distances from scipy and sklearn are supported
:param pairwise_distances: alternatively distances between all the pairs can be readily provided.
np.array of shape [n_samples, n_samples] (in this case, don't pass embeddings and metric)
:param method: either 'RTG', 'mannwhitneyu_per_sample', or 'mannwhitneyu_pooled'.
'RTG' is currently 10x faster and the recommended method; others are for research purposes.
:param minimal_n_samples: number of samples that can provide ranking (otherwise function returns NaN).
E.g. if both include and exclude are the same confounders, or if latter includes former, there are no elements
that can provide ranking.
:param use_fast_computations: use faster approximate computations (ignore ties in distances),
use if you don't have duplicates in the data and at least a couple of real-valued features
:return: score or NaN
NaN (Not-a-Number) if too few samples can provide ranking.
"""
n_samples = len(metadata)
pairwise_distances = compute_pairwise_distances(n_samples, embeddings, pairwise_distances, metric=metric)
for column in [*include_confounders, *exclude_confounders]:
if metadata[column].isna().sum() > 0:
raise RuntimeError(f'Metadata has Nones in "{column}"')
if len(include_confounders) == 0 or len(exclude_confounders) == 0:
raise InputErrorRTG(f'include_confounders and exclude_confounders should be non-empty')
inc_cat = ''
for category in include_confounders:
inc_cat = inc_cat + '_' + to_codes_str_series(metadata[category])
exc_indices_collection = [
to_codes(metadata[category]) for category in exclude_confounders
]
# recoding for simpler comparison
inc_indices = to_codes(inc_cat)
# compute target and mask
target = inc_indices[:, np.newaxis] == inc_indices[np.newaxis, :]
mask = True
for exc_indices in exc_indices_collection:
mask = mask & (exc_indices[:, np.newaxis] != exc_indices[np.newaxis, :])
if method == 'mannwhitneyu_per_sample':
mask = np.triu(mask, 1)
scores = []
in_group = mask & target
out_group = mask & ~target
for sample_idx, sample_dist in enumerate(pairwise_distances):
in_group_dist = sample_dist[in_group[sample_idx, :]]
out_group_dist = sample_dist[out_group[sample_idx, :]]
score = compute_mannwhitneyu_roc_auc_score(
-in_group_dist,
-out_group_dist
)
scores.append(score)
return np.nanmean(scores)
elif method == 'mannwhiteneyu_pooled':
mask = np.triu(mask, 1)
return compute_mannwhitneyu_roc_auc_score(
-pairwise_distances[mask & target].flatten(),
-pairwise_distances[mask & ~target].flatten()
)
elif method == 'RTG':
if use_fast_computations == 'auto':
use_fast_computations: bool = n_samples > 300
if use_fast_computations:
has_ones = (mask & target).any(axis=1)
has_zeros = (mask & ~target).any(axis=1)
good_rows = np.where(has_ones & has_zeros)[0]
if len(good_rows) < minimal_n_samples:
return np.nan
roc_auc_scores = []
for start in range(0, len(good_rows), 1000):
distances = pairwise_distances[good_rows[start: start + 1000]]
order_y = np.argsort(-distances, axis=1)
order_x = good_rows[start: start + 1000][:, None]
target_rows = target[order_x, order_y]
mask_rows = mask[order_x, order_y]
fraction_of_zeros_covered = (mask_rows & ~target_rows).astype('float32')
fraction_of_zeros_covered = np.cumsum(fraction_of_zeros_covered, axis=1)
fraction_of_zeros_covered /= fraction_of_zeros_covered[:, [-1]]
scores = (fraction_of_zeros_covered * mask_rows * target_rows).sum(axis=1)
scores /= (mask_rows & target_rows).astype('float32').sum(axis=1)
roc_auc_scores += list(scores)
return np.mean(roc_auc_scores)
else:
aucs = []
for sample in range(n_samples):
mask = True
for exc_indices in exc_indices_collection:
mask = mask & (exc_indices != exc_indices[sample])
target = inc_indices == inc_indices[sample]
distances = pairwise_distances[sample]
if len(set(target[mask])) == 2:
aucs.append(roc_auc_score(target[mask], -distances[mask]))
if len(aucs) < minimal_n_samples:
return np.nan
else:
return float(np.mean(aucs))
else:
raise RuntimeError(f'Unknown method {method}')
def fast_roc_auc(target, distances):
order = np.argsort(distances)
target = target[order].astype('bool')
fraction_of_zeros_covered = (target == 0).astype('float32')
fraction_of_zeros_covered = np.cumsum(fraction_of_zeros_covered)
fraction_of_zeros_covered /= fraction_of_zeros_covered[-1]
roc_auc_score = fraction_of_zeros_covered[target].mean()
return roc_auc_score
def compute_RTG_contribution_matrix(
metadata: pd.DataFrame,
include_confounders_dict: Dict[str, List[str]],
exclude_confounders_dict: Dict[str, List[str]],
*,
embeddings=None,
metric='euclidean',
pairwise_distances=None,
method='RTG',
minimal_n_samples=30,
use_fast_computations='auto',
):
"""
Compute RTG scores for multiple combinations of included and excluded confounding variables.
:param metadata: DataFrame with confounds (may contain additional variables) of shape [n_samples, n_variables].
Examples of variables: clone, donor, batch, plate, position on a plate
:param include_confounders_dict: dictionary with confounders and their combinations,
Example: {
'only donor': ['donor'],
'donor&batch': ['donor', 'batch']
}
:param exclude_confounders_dict: dictionary with confounders and their combinations
Example: {
'exclude same donor': ['donor'],
'exclude same clone': ['clone']
}
Score is computed for all pairs of included and excluded confounding variables.
:param embeddings: numerical description of each sample. DataFrame or np.array of shape [n_sample, n_features].
Order of embeddings should match order of rows in metadata
:param metric: distance used to evaluate similarity. Possible choices are:
- 'euclidean', relevant e.g. for delta Ct gene expression or for different embeddings
- 'hellinger', relevant e.g. for cell type fractions in scRNA-seq
- 'cosine', frequently more appropriate for DL embeddings
- other distances from scipy and sklearn are supported
:param method: either 'RTG', 'mannwhitneyu_per_sample', or 'mannwhitneyu_pooled'.
'RTG' is currently 10x faster and the recommended method; others are for research purposes.
:param pairwise_distances: alternatively distances between all the pairs can be readily provided.
np.array of shape [n_samples, n_samples] (in this case, don't pass embeddings and metric)
:param minimal_n_samples: number of samples that can provide ranking (otherwise function returns NaN).
E.g. if both include and exclude are the same confounders, or if latter includes former, there are no elements
that can provide ranking.
:param use_fast_computations: use faster approximate computations (ignore ties in distances),
use if you don't have duplicates in the data and at least a couple of real-valued features
:return: resulting scores are organized in pd.DataFrame (NaN elements mean not enough statistics)
"""
n_samples = len(metadata)
pairwise_distances = compute_pairwise_distances(n_samples, embeddings, pairwise_distances, metric=metric)
results = {}
for col_name, included in include_confounders_dict.items():
for row_name, excluded in exclude_confounders_dict.items():
results.setdefault(col_name, {})[row_name] = compute_RTG_score(
metadata=metadata,
include_confounders=included,
exclude_confounders=excluded,
pairwise_distances=pairwise_distances,
method=method,
minimal_n_samples=minimal_n_samples,
use_fast_computations=use_fast_computations,
)
return pd.DataFrame(results)
<file_sep>import nbformat
import nbformat
from nbconvert.preprocessors import ExecutePreprocessor
from pathlib import Path
def run_notebook(notebook_filename):
with open(notebook_filename) as f:
nb = nbformat.read(f, as_version=4)
ep = ExecutePreprocessor(timeout=600, kernel_name='python3')
notebook_folder = Path(notebook_filename).parent
ep.preprocess(nb, {'metadata': {'path': notebook_folder}})
# for reference: saving output notebook after running
# with open('executed_notebook.ipynb', 'w', encoding='utf-8') as f:
# nbformat.write(nb, f)
def test_notebook():
notebook_path = Path(__file__).parent.parent / 'example' / 'Example_qPCR.ipynb'
run_notebook(notebook_path)
| cc1c20a4b5a9a49c7d522a8d130c494432966155 | [
"Markdown",
"Python"
] | 6 | Markdown | herophilus/rtg_score | 5fdc5e32610fcad949702ea67c9a3c44c944e403 | fe8353d3daaaa44a68a4bfda53be7497191e7d0f |
refs/heads/main | <repo_name>pongsirichatkaew/project-template-react<file_sep>/src/components/buttons/PurchaseButton.js
import React from "react"
import styled from "styled-components"
import { Caption2, SmallText } from "../styles/TextStyles"
import { Link } from "gatsby"
import credit from "../../../static/images/icons/credit.svg"
import ring from "../../../static/images/icons/icon-ring.svg"
export default function PurchaseButton(props) {
const { title, subtitle } = props
return (
<Link to="/page-2">
<Wrapper>
<IconWrapper>
<Icon src={credit}></Icon>
<Ring src={ring} />
</IconWrapper>
<TextWrapper>
<Title>{title || "Get Pro Access"}</Title>
<SubTitle>{subtitle || "$19 per month"}</SubTitle>
</TextWrapper>
</Wrapper>
</Link>
)
}
const Wrapper = styled.div`
width: 280px;
height: 77px;
padding: 12px;
background: linear-gradient(180deg, #ffffff 0%, #d9dfff 100%);
border: 0.5px solid rgba(255, 255, 255, 0.5);
box-shadow: 0px 1px 3px rgba(0, 0, 0, 0.1),
0px 20px 40px rgba(23, 0, 102, 0.2);
backdrop-filter: blur(30px);
border-radius: 20px;
display: grid;
grid-template-columns: 53px auto;
/* */
align-items: center;
gap: 20px;
/* transition: 1s cubic-bezier(0.075, 0.82, 0.165, 1); */
/* ALL CHILD ELEMENT */
/* DANGEROUS */
*,
& {
transition: 1s cubic-bezier(0.075, 0.82, 0.165, 1);
}
:hover {
box-shadow: 0px 1px 3px rgba(0, 0, 0, 0.1),
0px 30px 60px rgba(23, 0, 102, 0.5);
/* transform: translateY(-3px) scale(1.2) rotate(10deg) skew(10deg); */
transform: translateY(-3px);
.icon {
transform: scale(1.2);
}
}
`
const TextWrapper = styled.div`
display: grid;
gap: 4px;
`
const Title = styled(Caption2)`
color: black;
`
const SubTitle = styled(SmallText)`
color: black;
opacity: 0.7;
`
const Icon = styled.img`
width: 29px;
height: 29px;
`
const Ring = styled.img`
position: absolute;
top: -15px;
left: -16px;
/* SELECTED ELEMENT NEED TO BE DECLARE BEFORE */
/* & = self wrapper and ring inside that */
${Wrapper}: hover & {
transform: rotate(30deg) scale(1.2) translate(1px, 1px);
}
`
const IconWrapper = styled.div`
width: 45px;
height: 45px;
background: linear-gradient(200.44deg, #4316db 13.57%, #9076e7 98.38%);
box-shadow: 0px 10px 20px rgba(182, 153, 255, 0.3);
border-radius: 50%;
display: grid;
justify-content: center;
align-content: center;
justify-self: center;
position: relative;
${Wrapper}:hover & {
filter: hue-rotate(10deg);
}
`
<file_sep>/src/components/backgrounds/WaveBackground.js
import React from "react"
import styled from "styled-components"
import wave1 from "../../../static/images/waves/hero-wave1.svg"
import wave2 from "../../../static/images/waves/hero-wave2.svg"
import wave3 from "../../../static/images/waves/hero-wave3.svg"
export default function WaveBackground() {
return (
<Wrapper>
<Background />
<Wave src={wave1} style={{ top: "0" }} />
<Wave src={wave2} style={{ top: "350px" }} />
<Wave src={wave3} style={{ top: "550px" }} />
</Wrapper>
)
}
const Wrapper = styled.div`
position: relative;
`
const Wave = styled.img`
position: absolute;
z-index: -1;
`
const Background = styled.div`
background: linear-gradient(180deg, #4316db 0%, #9076e7 100%);
position: absolute;
width: 100%;
height: 800px;
z-index: -1;
`
<file_sep>/src/components/sections/HeroSection.js
import React from "react"
// import { Link } from "gatsby"
// Components
import PurchaseButton from "../buttons/PurchaseButton"
import MockupAnimation from "../animations/MockupAnimation"
import WaveBackground from "../backgrounds/WaveBackground"
import styled, { keyframes } from "styled-components"
import { H1, MediumText } from "../styles/TextStyles"
import { themes } from "../styles/ColorStyles"
const HeroSection = () => {
console.log("themes", themes)
return (
<Wrapper>
<WaveBackground />
<ContentWrapper>
<TextWrapper>
<Title>
Design <br /> and code <span>React</span> apps
</Title>
<Description></Description>
<PurchaseButton
title="Start Learning"
subtitle="120+ hours of video"
/>
</TextWrapper>
<MockupAnimation />
</ContentWrapper>
</Wrapper>
)
}
export default HeroSection
const animation = keyframes`
0% { opacity: 0; transform: translateY(-10px); filter: blur(10px); }
80% { opacity: 0.5; transform: translateY(-10px); filter: blur(10px); }
100% { opacity: 1; transform: translateY(0px); filter: blur(0px); }
/* from { opacity: 0; transform: translateY(-10px); filter: blur(10px); }
to { opacity: 1; transform: translateY(0px); filter: blur(0px); } */
`
const Wrapper = styled.div`
/* background: linear-gradient(180deg, #4316db 0%, #9076e7 100%); */
overflow: hidden;
`
const ContentWrapper = styled.div`
max-width: 1234px;
padding: 200px 30px;
margin: 0 auto;
display: grid;
grid-template-columns: 360px auto;
`
const TextWrapper = styled.div`
max-width: 360px;
display: grid;
gap: 30px;
/* SELECT ONLY CHILDREN */
> * {
opacity: 0;
animation: ${animation} 1s forwards;
:nth-child(1) {
animation-delay: 0s;
}
:nth-child(2) {
animation-delay: 0.2s;
}
:nth-child(3) {
animation-delay: 0.4s;
}
}
`
const Title = styled(H1)`
color: ${themes.dark.text1};
background: linear-gradient(180deg, #730040 0%, #301cbe 100%);
background-clip: text;
-webkit-background-clip: text;
color: transparent;
span {
background: linear-gradient(180deg, #ffd7ff 0%, #ffb6ff 100%);
background-clip: text;
-webkit-background-clip: text;
color: transparent;
}
/* animation: ${animation} 1s 0.2s forwards; */
`
const Description = styled(MediumText)``
| 055535e9a3559bdcd6319f0d4199d0f968136b99 | [
"JavaScript"
] | 3 | JavaScript | pongsirichatkaew/project-template-react | 876f37881543141d39fc611137193d797dd6e218 | f72817ab9859f2c13c0db14250a47985e49d922d |
refs/heads/master | <repo_name>SmoothCriminals/Kalaha<file_sep>/KalahServer/client_Java/aiThread.java
class aiThread extends Thread {
public boolean isDone = false;
public int aiChoice = -1;
public char[] board;
public int depth;
private MinMax myMinMax;
public void run() {
//System.out.println("MinMaxStart!");
myMinMax = new MinMax(depth, board);
aiChoice = myMinMax.evaluation();
//System.out.println("MinMaxFinished!");
//try {
//sleep(100);
//} catch(InterruptedException e) {
//choice}
isDone = true;
System.out.println("Depth: "+depth+" calculated!");
}
}<file_sep>/KalahServer/client_Java/MinMax.java
import java.util.*;
public class MinMax{
AiNodeMaster bestBoard;
int nodeDepth;
boolean first = true;
public int nodeCount = 0;
public MinMax(int _depth, char[] _board){
nodeDepth = _depth;
AiNodeMaster tree;
tree = new AiNodeMaster(null, _board, (short)0, (char)10, (short)-32700, (short)32700);
bestBoard = tree;
DLS2(tree, _depth, (int)_board[14], _board);
}
public int evaluation(){
while(bestBoard.getParent().getChoise() != 10){
bestBoard = bestBoard.getParent();
}
return bestBoard.getChoise();
}
public void DLS2(AiNodeMaster node, int depth, int Max, char[] _board) {
char childBoard[];
short childNodeValue = (short)0;
int counter = 0;
boolean end = false;
if (depth > 0) {
for (int i = 1; i<7; i++) {
childBoard = node.move((short)i, (short)_board[14], _board.clone());
if (!Arrays.equals(childBoard, _board)) {
if (MaxNode(Max, _board)) {
node.setAlpha(alphaBeta(node, depth, Max, (short)-32700, (short)32700));
if (Max == 1) {
childNodeValue = (short)(node.getNodeValue() + ((childBoard[7] - childBoard[0])));
}
else{
childNodeValue = (short)(node.getNodeValue() + ((childBoard[0] - childBoard[7])));
}
}
else {
node.setBeta(alphaBeta(node, depth, Max, (short)-32700, (short)32700));
if (Max == 1) {
childNodeValue = (short)(node.getNodeValue() - ((childBoard[0] - childBoard[7])));
}
else{
childNodeValue = (short)(node.getNodeValue() - ((childBoard[7] - childBoard[0])));
}
}
if (node.getAlpha() >= node.getBeta()) {
end = true;
}
if(!end){
node.childNode.add(new AiNodeMaster(node, childBoard, childNodeValue, (char)i, node.getAlpha(), node.getBeta() ));
//System.out.println("Value: "+childNodeValue+" choise: "+i+" Depth: "+depth+" Alpha"+node.getAlpha()+" Beta: "+node.getBeta());
if (depth == nodeDepth && counter == 0 && first) {
bestBoard = node.childNode.get(counter);
first = false;
}
if (bestBoard.getNodeValue() < childNodeValue) {
//System.out.println(" the best choise is: "+i);
bestBoard = node.childNode.get(counter);
}
counter++;
nodeCount++;
DLS2(node.childNode.get(counter-1), depth-1, Max, childBoard);
}
else{
//System.out.println("break");
}
}
}
}
}
public boolean MaxNode(int Max, char[] _board){
if ((int)_board[14] == Max){
return true;
}
else{
return false;
}
}
public short alphaBeta(AiNodeMaster node, int depth, int Max, short alpha, short beta){
if (depth == 0) {
return node.getNodeValue();
}
if (MaxNode(Max, node.getBoard())) {
for (int i = 0; i < node.childNode.size(); i++) {
alpha = max(alpha, alphaBeta(node.childNode.get(i), depth-1, Max, alpha, beta));
if (alpha >= beta) {
break;
}
}
return alpha;
}
else{
for (int i = 0; i < node.childNode.size(); i++) {
beta = min(beta, alphaBeta(node.childNode.get(i), depth-1, Max, alpha, beta));
if (alpha >= beta) {
break;
}
}
return beta;
}
}
public short max(short m1, short m2){
if (m2 > m1) {
return m2;
}
else{
return m1;
}
}
public short min(short m1, short m2){
if (m2 < m1) {
return m2;
}
else{
return m1;
}
}
} | 401abfb940dcb75df55ad550e4dad56ca4e1a20a | [
"Java"
] | 2 | Java | SmoothCriminals/Kalaha | 745e869640ef0e93c8b5f209b30aafdebcdc014d | 203359113a686a8261114462d5ad9910ce4d8a1c |
refs/heads/master | <file_sep>import { Injectable } from '@angular/core';
import { BehaviorSubject, throwError } from 'rxjs';
import { HttpClient, HttpErrorResponse } from '@angular/common/http';
import { Router } from '@angular/router';
import { catchError, tap, take, map } from 'rxjs/operators';
import { User } from '@shared/models/User.model';
export interface IAuthResponseData {
displayName?: string;
kind: string;
idToken: string;
email: string;
refreshToken: string;
expiresIn: string;
localId: string;
registered?: boolean;
}
@Injectable({providedIn: 'root'})
export class AuthService {
apiKey: string = "AIzaSyClV8ZL-Pd-tWEoM7dy7BZOUi-4lI1gO3w";
private expirationTimer: any;
user = new BehaviorSubject<User>(null);
constructor(
// private config: ConfigService,
private http: HttpClient,
private router: Router
) {}
getAuthorizationToken() {
return localStorage.getItem('uid') ? JSON.parse(localStorage.getItem('uid'))._token : '<PASSWORD>';
}
isAuthenticated() {
return localStorage.getItem('uid') ? true : false;
}
login(username: string, password: string) {
return this.http
.post<IAuthResponseData>(`https://identitytoolkit.googleapis.com/v1/accounts:signInWithPassword?key=${this.apiKey}`, {
email: username,
password: <PASSWORD>,
returnSecureToken: true
})
.pipe(
catchError(this.handleError),
tap(res => {
const expiresIn = new Date(new Date().getTime() + (12 * 3600 * 1000) + (+res.expiresIn * 1000));
const user = new User(res.email, res.localId, res.idToken, expiresIn);
this.user.next(user);
this.autologout((+res.expiresIn * 1000) + (12 * 3600 * 1000));
if (localStorage.getItem('uid')) localStorage.removeItem('uid');
localStorage.setItem('uid', JSON.stringify(user));
})
);
}
autologin() {
const storedUser: {username: string, id: string, _token: string, _tokenExpiresAt: string } = JSON.parse(localStorage.getItem('uid'));
if (!storedUser) {
return;
}
const loadeduser = new User(storedUser.username, storedUser.id, storedUser._token, new Date(storedUser._tokenExpiresAt));
if (loadeduser.token) {
const duration = new Date(storedUser._tokenExpiresAt).getTime() - new Date().getTime();
this.user.next(loadeduser);
this.autologout(duration);
}
}
logout() {
this.user.next(null);
localStorage.removeItem('uid');
localStorage.setItem('uid', JSON.stringify({error: 'User logged out.'}));
this.router.navigate(['/auth']);
if (this.expirationTimer) {
clearTimeout(this.expirationTimer);
}
this.expirationTimer = null;
}
autologout(duration: number) {
this.expirationTimer = setTimeout(() => {
this.logout();
localStorage.setItem('uid', JSON.stringify({error: 'Session expired.'}));
}, duration);
}
private handleError(errorResponse: HttpErrorResponse) {
console.log(errorResponse)
let errorMessage = "Unknown error";
if (!errorResponse.error || !errorResponse.error.error) {
return throwError(errorMessage);
}
switch (errorResponse.error.error.message) {
case 'EMAIL_NOT_FOUND':
errorMessage = 'Username does not exist.';
break;
case 'INVALID_PASSWORD':
errorMessage = 'Invalid password.';
break;
}
return throwError(errorMessage);
}
}<file_sep>export interface IPrice {
id?: string;
price: number;
fuel: string;
from?: {
seconds: number,
nanoseconds: number
},
to?: {
seconds: number,
nanoseconds: number
},
published?: boolean;
}<file_sep>export class User {
constructor(public username: string, public id: string, private _token: string, private _tokenExpiresAt: Date) {}
get token() {
if (!this._tokenExpiresAt || new Date() > this._tokenExpiresAt) {
localStorage.removeItem('uid');
localStorage.setItem('uid', JSON.stringify({error: 'Session expired.'}));
return null;
}
return this._token;
}
}<file_sep>import { NgModule } from '@angular/core';
import { Routes, RouterModule } from '@angular/router';
import { CommonModule } from '@angular/common';
import 'moment/locale/cs';
import { MomentModule } from 'ngx-moment';
import { NgxChartsModule } from '@swimlane/ngx-charts';
import { PipesModule } from '@core/pipes.module';
import { DialogsModule } from '@shared/dialogs/dialogs.module';
import { NbTabsetModule, NbIconModule, NbListModule, NbButtonModule, NbInputModule, NbDatepickerModule, NbWindowModule } from '@nebular/theme';
import { DashboardComponent } from './dashboard/dashboard.component';
import { AddPriceComponent } from '@shared/dialogs/add-price/add-price.component';
import { AuthGuard } from '@core/services/auth.guard';
// Routing
const routes: Routes = [
{
path: '',
canActivateChild: [AuthGuard],
component: DashboardComponent
}
]
@NgModule({
declarations: [
DashboardComponent,
AddPriceComponent
],
imports: [
CommonModule,
MomentModule,
NbWindowModule.forRoot(),
NbInputModule,
NbButtonModule,
NbDatepickerModule,
NbListModule,
NbTabsetModule,
NbIconModule,
NgxChartsModule,
PipesModule,
DialogsModule,
RouterModule.forChild(routes)
],
entryComponents: [
AddPriceComponent
],
exports: [
]
})
export class DashboardModule { }
<file_sep>import { Component, OnInit, OnDestroy, ChangeDetectionStrategy, ɵSWITCH_COMPILE_DIRECTIVE__POST_R3__ } from '@angular/core';
import { map, takeUntil, tap } from 'rxjs/operators';
import { Observable, Subject } from 'rxjs';
import { NbWindowService } from '@nebular/theme';
import { curveNatural } from 'd3-shape';
import { IPrice } from '@shared/models/IPrice';
import { PricesService } from '@core/services/prices.service';
import { AddPriceComponent } from '@shared/dialogs/add-price/add-price.component'
import { AuthService } from '@core/services/auth.service';
import { environment, v } from '@env/environment';
@Component({
changeDetection: ChangeDetectionStrategy.OnPush,
selector: 'fuel-price-dashboard',
templateUrl: './dashboard.component.html',
styleUrls: ['./dashboard.component.scss']
})
export class DashboardComponent implements OnInit, OnDestroy {
public appVersion = v;
public isLogged: boolean = false;
private latestSubject = new Subject<void>();
private historySubject = new Subject<void>();
public latest: {[key: string]: IPrice};
public $prices: Observable<IPrice[]>;
public $chartPrices: Observable<any[]>;
public chartConfig = {};
constructor(
private pricesService: PricesService,
private windowService: NbWindowService,
private authService: AuthService
) {
}
ngOnInit() {
this.getPrices();
this.getLatestPrices();
this.setChart();
this.$chartPrices = this.getChartData();
this.isLogged = this.authService.isAuthenticated();
}
ngOnDestroy() {
this.latestSubject.next();
this.latestSubject.complete();
this.historySubject.next();
this.historySubject.complete();
}
filterPriceOlderWeek(price: any) {
const beforeWeek = new Date(new Date().setDate(new Date().getDate() - 7));
return price.from < beforeWeek ? true : false;
}
filterPriceByCrude(price: any) {
return price.fuel === 'crude' ? true : false;
}
filterPriceByPetrol(price: any) {
return price.fuel === 'petrol' ? true : false;
}
trackByFn(index, item) {
return item.id;
}
getPrices() {
this.$prices = this.pricesService.getPrices().pipe(
map(data => {
return data.map((c: any) => {
return {
id: c.payload.doc.id,
...c.payload.doc.data(),
from: new Date(+c.payload.doc.get('from').toDate()),
to: new Date(c.payload.doc.get('to').toDate())
} as IPrice;
});
})
)
}
getLatestPrices(period: number = 7) {
this.$prices.pipe(
takeUntil(this.latestSubject),
map(data => {
return data.filter((item: any) => {
const beforeWeekDate = new Date(new Date().setDate(new Date().getDate() - period));
const publishDate = new Date(item.from);
// return latest price only
if (publishDate > beforeWeekDate) {
return item;
}
});
})
).subscribe(data => {
this.latest = data.reduce((obj, oitem) => {
const { fuel, ...rest } = oitem;
return {
...obj,
[fuel]: rest
}
}, {});
});
}
setChart() {
this.chartConfig = {
colorScheme: {
domain: ['#5AA454', '#E44D25']
},
// view: [420, 120],
legend: false,
showLabels: false,
animations: true,
autoScale: true,
yScaleMin: 20,
yScaleMax: 40,
curve: curveNatural,
xAxis: false,
yAxis: false,
showYAxisLabel: true,
showXAxisLabel: true
}
}
getChartData() {
return this.$prices.pipe(
takeUntil(this.historySubject),
map(data => {
return data.filter((item: any) => {
const publishDate = new Date(item.from);
if (publishDate < new Date()) {
return item;
}
});
}),
map(data => {
let crudePrices = [];
let petrolPrices = [];
data.forEach((oitem) => {
const { fuel, ...rest } = oitem;
if (fuel == 'crude') {
crudePrices.push(rest)
}
if (fuel == 'petrol') {
petrolPrices.push(rest)
}
});
return [{
"name": "Nafta",
"series": crudePrices.map(item => {
return {
"name": item.from,
"value": item.price
}
}),
},
{
"name": "Benzin",
"series": petrolPrices.map(item => {
return {
"name": item.from,
"value": item.price
}
})
}];
})
)
}
onAdd($event) {
const windowRef = this.windowService.open(AddPriceComponent, {
hasBackdrop: true,
windowClass: 'stretch',
context: {
latestCrudePrice: this.latest.crude.price,
latestPetrolPrice: this.latest.petrol.price
}
});
}
}
<file_sep>import { Injectable } from '@angular/core';
import { AngularFirestore } from '@angular/fire/firestore';
import 'firebase/firestore';
import { IPrice } from '@shared/models/IPrice';
@Injectable({
providedIn: 'root'
})
export class PricesService {
private collectionId: string = 'prices';
constructor(
public firestore: AngularFirestore
) { }
getPrices() {
return this.firestore.collection(this.collectionId, ref => ref.orderBy('from', 'desc')).snapshotChanges();
}
addPrice(price: IPrice) {
return this.firestore.collection(this.collectionId).add(price);
}
}
<file_sep>import { environment } from '@env/environment';
import { BrowserModule } from '@angular/platform-browser';
import { HttpClientModule } from '@angular/common/http';
import { BrowserAnimationsModule } from '@angular/platform-browser/animations';
import { NgModule, LOCALE_ID, DEFAULT_CURRENCY_CODE } from '@angular/core';
import { registerLocaleData } from '@angular/common';
import localeCs from '@angular/common/locales/cs';
registerLocaleData(localeCs);
import { FormsModule, ReactiveFormsModule } from '@angular/forms';
import { NbThemeModule, NbLayoutModule, NbWindowModule, NbDatepickerModule } from '@nebular/theme';
import { NbEvaIconsModule } from '@nebular/eva-icons';
import { AngularFireModule } from '@angular/fire';
import { AngularFireDatabaseModule } from '@angular/fire/database';
import { AngularFirestoreModule } from '@angular/fire/firestore';
import { AppRoutingModule } from './app-routing.module';
import { AuthService } from './core/services/auth.service';
import { httpInterceptorProviders } from './core/http-interceptors';
import { HttpErrorService } from './core/services/http-error.service';
import { AppComponent } from './app.component';
import { MasterHeaderComponent } from './core/components/master-header/master-header.component';
import { MasterFooterComponent } from './core/components/master-footer/master-footer.component';
@NgModule({
declarations: [
AppComponent,
MasterHeaderComponent,
MasterFooterComponent,
],
imports: [
BrowserModule,
FormsModule,
ReactiveFormsModule,
HttpClientModule,
AppRoutingModule,
BrowserAnimationsModule,
AngularFireModule.initializeApp(environment.firebase),
AngularFireDatabaseModule,
AngularFirestoreModule,
NbThemeModule.forRoot({ name: 'tbdi' }),
NbWindowModule.forRoot(),
NbDatepickerModule.forRoot(),
NbLayoutModule,
NbEvaIconsModule
],
providers: [
httpInterceptorProviders,
AuthService,
HttpErrorService,
{ provide: DEFAULT_CURRENCY_CODE, useValue: 'CZK' },
{ provide: LOCALE_ID, useValue: 'cs'}
],
entryComponents: [],
bootstrap: [AppComponent]
})
export class AppModule { }
<file_sep>import { Component, OnInit, ViewChild, Input, AfterViewInit, ElementRef } from '@angular/core';
import * as moment from 'moment';
import { FormGroup, FormBuilder } from '@angular/forms';
import { PricesService } from '@core/services/prices.service';
import { NbWindowRef } from '@nebular/theme';
@Component({
selector: 'app-add-price',
templateUrl: './add-price.component.html',
styleUrls: ['./add-price.component.scss']
})
export class AddPriceComponent implements OnInit, AfterViewInit {
public addPriceForm: FormGroup;
@Input() latestCrudePrice: number;
@Input() latestPetrolPrice: number;
@Input() initialFromDate: Date = new Date(new Date().setDate(new Date().getDate() + 1));
@Input() initialToDate: Date = new Date(new Date().setDate(new Date().getDate() + 7));
@ViewChild('fromDate') fromDate: any;
@ViewChild('toDate') toDate: any;
@ViewChild('focusEl') focusEl: ElementRef;
constructor(
private formBuilder: FormBuilder,
private priceService: PricesService,
protected windowRef: NbWindowRef
) { }
ngOnInit(): void {
this.addPriceForm = this.formBuilder.group({
crude: this.formBuilder.control(this.latestCrudePrice),
petrol: this.formBuilder.control(this.latestPetrolPrice),
from: this.formBuilder.control(this.initialFromDate),
to: this.formBuilder.control(this.initialToDate)
}, {
updateOn: 'change'
})
}
ngAfterViewInit() {
this.focusEl.nativeElement.focus();
}
onAdd() {
// console.log(this.addPriceForm)
if (this.addPriceForm.valid) {
let { from, to, crude, petrol } = this.addPriceForm.value;
from = moment(from, moment.defaultFormat).toDate();
to = moment(to, moment.defaultFormat).toDate();
this.priceService.addPrice({
from, to,
price: petrol,
fuel: 'petrol',
published: true
});
this.priceService.addPrice({
from, to,
price: crude,
fuel: 'crude',
published: true
});
}
this.windowRef.close();
}
onClose() {
this.windowRef.close();
}
onFromDateChanged(changeEvent) {
const updatedToDate = new Date(new Date().setDate(new Date(changeEvent.target.value).getDate() + 6));
// this.toDate.hostRef.nativeElement.value = updatedToDate.toLocaleDateString('cs-CZ');
this.addPriceForm.controls['to'].setValue(moment(updatedToDate).format('YYYY-MM-DD'));
}
}
<file_sep>import { name, version } from '../../package.json';
export const environment = {
production: true,
firebase: {
apiKey: "AIzaSyClV8ZL-Pd-tWEoM7dy7BZOUi-4lI1gO3w",
authDomain: "tbdi-1533558054559.firebaseapp.com",
databaseURL: "https://tbdi-1533558054559.firebaseio.com",
projectId: "tbdi-1533558054559",
storageBucket: "tbdi-1533558054559.appspot.com",
messagingSenderId: "475612045706",
appId: "1:475612045706:web:fa39b9b6dbf821e4692873",
measurementId: "G-F1R7WXH1BZ"
}
};
export const v = version;
<file_sep>import { Component, OnInit, ViewChild, AfterViewInit, ElementRef } from '@angular/core';
import { FormGroup, FormBuilder } from '@angular/forms';
import { AuthService } from '@core/services/auth.service';
import { Router } from '@angular/router';
@Component({
selector: 'app-login',
templateUrl: './login.component.html',
styleUrls: ['./login.component.scss']
})
export class LoginComponent implements OnInit, AfterViewInit {
public busy: boolean = false;
public error: String;
@ViewChild('focusEl', { static: true }) focusEl: ElementRef;
public loginForm: FormGroup;
constructor(
private fb: FormBuilder,
private router: Router,
private authService: AuthService
) { }
ngOnInit() {
this.loginForm = this.fb.group({
username: this.fb.control('<EMAIL>'),
password: this.fb.control('<PASSWORD>')
})
}
ngAfterViewInit() {
this.focusEl.nativeElement.focus();
}
onLogin() {
const formData = this.loginForm.value;
this.busy = true;
this.authService.login(formData.username, formData.password).subscribe(
response => {
this.busy = false;
this.router.navigate(['/dashboard']);
},
errorMessage => {
this.error = errorMessage;
this.busy = false;
});
}
}
| a8f33e3156f3a0ce1e1cd3792aeab40160705342 | [
"TypeScript"
] | 10 | TypeScript | knrk/tbdi-fuel-prices | 84c5fdfa62e05bf6e03e0e52103e23b02e3798ae | c141c6a7f82207a72d0283ba40d06eaf5d4f540c |
refs/heads/master | <repo_name>winteriscome/AI<file_sep>/README.md
# AI
自己学习的一些算法，记录在这里以便于自己回顾学习
<file_sep>/bubble.php
<?php
$a = array(45, 54, 8, 23, 6, 12, 99);
print_r($a);
function bubble($date){
for ($i=0; $i < count($date); $i++) {
# code...
for ($j=0; $j < count($date) - $i -1; $j++) {
# code..
if ($date[$j] > $date[$j +1]) {
# code...
$temp = $date[$j];
$date[$j] = $date[$j +1];
$date[$j +1] = $temp;
}
}
}
return $date;
}
print_r(bubble($a));
?><file_sep>/get_files.php
<?php
function listDir($dir = '.'){
if($handle = opendir($dir)){
while(false !== ($file = readdir($handle)))
{
if($file == '.'|| $file == '..'){
continue;
}
if(is_dir($sub_dir = realpath($dir.'/'.$file)))
{
echo 'FILE IN PATH:'.$dir.':'.$file."\n";
listDir($sub_dir);
}
else{
echo 'FILE:'.$file."\n";
}
}
closedir($handle);
}
}
listDir('.');
?> | 875453b6d4e52f2bb10b6748f7c06e7f67fb1454 | [
"Markdown",
"PHP"
] | 3 | Markdown | winteriscome/AI | b893b47d0e12c22805f3a9cf51f925376753324b | 63a008b735a18d93285733d7d2775b6fe6a21e41 |
refs/heads/master | <repo_name>weiqiangzheng/jing_install<file_sep>/app/src/main/java/test/install/MainActivity.java
package test.install;
import android.os.Bundle;
import android.support.v7.app.AppCompatActivity;
import android.view.View;
import android.widget.Button;
public class MainActivity extends AppCompatActivity implements View.OnClickListener{
Button install,delete;
@Override
protected void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(test.packmanager.R.layout.activity_main);
}
@Override
public void onClick(final View v) {
new Thread(new Runnable() {
@Override
public void run() {
switch (v.getId()){
case test.packmanager.R.id.install:
InstallUtil.J_install(MainActivity.this,"test","test.packmanager");//静默安装
break;
case test.packmanager.R.id.delete:
InstallUtil.J_uninstall(MainActivity.this,"test.client");//静默卸载
break;
case test.packmanager.R.id.install2:
InstallUtil.install(MainActivity.this,"test");//普通安装
break;
case test.packmanager.R.id.uninstall2:
InstallUtil.uninstall(MainActivity.this,"test.client");//普通卸载
break;
case test.packmanager.R.id.install_root:
InstallUtil.J_installRoot("test");//需要root的静默安装
break;
case test.packmanager.R.id.uninstall_root:
InstallUtil.J_uninstallRoot("test.client");
break;
case test.packmanager.R.id.install3:
InstallUtil.JF_install(MainActivity.this,"test","test.packmanager");//反射方式
break;
case test.packmanager.R.id.uninstall3:
InstallUtil.JF_uninstall(MainActivity.this,"test.client");//反射方式
break;
}
}
}).start();
}
}
| 11b5deb0e99ad7ee7e7ff02db5cb79d578a85dd3 | [
"Java"
] | 1 | Java | weiqiangzheng/jing_install | 9eba265de41c44369dafff08eb94cea67a16a127 | 73fe6f896fe1fd9f7384a66caf5307b7575153c9 |
refs/heads/master | <file_sep>from mymodule import myfunc
myfunc() # this is the first commit | e6a25ba12cb0273cde81a0f12e34feb779faac81 | [
"Python"
] | 1 | Python | singhjagriti/pythonproject | f93ff10d9169a60db1e1b9a3591bb9213ef1c88a | 6adf8550b415fc46d2200c0cbb0ccbb2012387b3 |
refs/heads/master | <file_sep># Burger Sequelized
In this assignment, I Sequelized the Burger app that I made last week.
<file_sep>// Pull in the Burger model
var db = require("../models");
var express = require("express");
var router = express.Router();
// Retrieve the list of all burgers in the database
router.get("/", function(req, res) {
console.log("bat");
// findAll returns all entries for a table when used with no options
db.Burgers.findAll({}).then(function(data) {
var hbsObject = { burgers: data};
res.render("index", hbsObject);
})
.catch(function(error) {
console.log(error.message);
res.status(500).json({ error: error.message });
});
});
// Create a new burger entry
router.post("/", function(req, res) {
console.log("turtle");
db.Burgers.create({
burger_name: req.body.burger_name},
{devoured: req.body.devoured
}).then(function() {
res.redirect("/");
})
.catch(function(error) {
console.log(error.message);
res.status(500).json({ error: error.message });
})
});
// Update an existing burger entry
router.put("/:id", function(req, res) {
console.log("happy");
db.Burgers.update({devoured: req.body.devoured}, {
where: {id: req.params.id}
}).then(function(data) {
res.redirect('/');
})
.catch(function(error) {
console.log(error.message);
res.status(500).json({ error: error.message });
})
});
module.exports = router;<file_sep>INSERT INTO burgers(burger_name) VALUES ('Juicy Lucy');
INSERT INTO burgers(burger_name) VALUES ('Slider');
INSERT INTO burgers(burger_name) VALUES ('Veggie Burger');
INSERT INTO burgers(burger_name) VALUES ('Hawaii Burger');
INSERT INTO burgers(burger_name) VALUES ('Chili Burger'); | 5fbc604a62d0942bab95e44a40630aac07c466b1 | [
"Markdown",
"SQL",
"JavaScript"
] | 3 | Markdown | kvirant/burgersSequelized | ced1f619ef211f13f8267f5aeae252f2ca9a8472 | efe81dfaaa10869e19d927ee8343ddf8f9644af5 |
refs/heads/master | <repo_name>wjzmm/c<file_sep>/practice/十进制转二进制/tenToTwo.cpp
#include <stdio.h>
/*
* 采用递归将十进制转换为二进制
*/
void tenToTwo(int n);
void to_binary(unsigned long n);
int main(){
int number = 45;
tenToTwo(number);
return 0;
}
void tenToTwo(int n){
/* if (n % 2 == 1){
printf("1");
} else {
printf("0");
}*/
printf("%d", n % 2);
if (n > 1) {
tenToTwo(n / 2);
}
return ;
}
/*
* 标准程序
*/
void to_binary(unsigned long n){
if(n > 1){
to_binary(n / 2);
}
printf("%d", n % 2);
return ;
}<file_sep>/README.md
# c
about c learning
2015年9月23日10:22:13
| 62b4efc3e78703865128d3a96aa53fa995f5ea71 | [
"Markdown",
"C++"
] | 2 | C++ | wjzmm/c | a7a89aaa763756c5107e4a7c71c35a474f222748 | 19f3dd03dc6d42dbe217be22729a776593eae34c |
refs/heads/master | <repo_name>DeshawnN/python-progs<file_sep>/vowel_counter.py
def main():
print 'Welcome to my vowel counting python program.'
print 'Please enter the string that you wish to count the vowels of: '
player_input = str(raw_input()).lower()
vowel_counter(player_input)
def vowel_counter(string):
vowels = ('a', 'e', 'i', 'o', 'u')
vowel_count = 0
for letter in string:
if letter == letter in vowels:
vowel_count += 1
else:
pass
print vowel_count
main()<file_sep>/palindrome_checker.py
def main():
print 'Please enter a string and I\'ll let you know if its a palindrome or not: '
palindrome = raw_input().lower()
p_check(palindrome)
def p_check(string):
is_palindrome = False
if string == string[::-1]:
is_palindrome = True
else:
pass
if is_palindrome == True:
print 'Yes, %s is a Palindrome' %string
else:
print 'Sorry, %s isn\'t a palindrome.' %string
reset()
def reset():
print 'Try again? press y or n'
user_input = raw_input()
if user_input == 'y':
main()
elif user_input == 'n':
print 'Thanks for trying my program!'
quit()
else:
'Invalid Selection'
reset()
main()<file_sep>/README.md
# Misc Python Progs
==============
Hello and Welcome to my **Python** Program repository.
Here you can find miscellaneous programs I've made in python.
I also dabble a bit in Web Development, feel free to check out my Github pages site at:
https://DeshawnN.github.io/
I know other programming languages such as **C/C++**, a little **Ruby**, a tiny bit of **Java**, and
I'm currently studying some **mobile/android** frameworks. And as such, in the future I'll try to ensure that
the programs and modules are ported over to those other languages.
Anyways, Thanks for stopping by, and I wish you all well.
## Changelog
### April
#### 19th
Created the repository
### May
#### 14th
Adds the scripts(s): String Reverser, Vowel Counter, Palindrome Checker, Word Counter
#### 17th
Adds the script: FizzBuzzinator
#### 19th
Adds the script: File Organizer
## Code Overview
### Strings
#### String Reverser
This is a simple program I whipped up during my lunch break.
It works like this, You'll be prompted to enter a string and it will reverse your string and display it.
#### Vowel Counter
This program counts the like the String reverser, takes a string at a user input prompt, then it counts the number of vowels in that string and outputs the number.
#### Palindrome Checker
This program takes in a user inputted string and checks if it is the same backwards as it is forward.
#### Word Counter
This program takes in a user inputted string and counts however many words are in the string and outputs the number.
### Algorithms
#### FizzBuzzinator
This program is a little bit more complex than anything in my strings section.
This program was designed from the ground up to help people struggling to understand the logic behind the FizzBuzz problem by letting them make their own custom problems without having to muck around with any code.
Currently it's a bit bare, but I'll keep adding to it until I'm satisfied with it.
### Misc
#### File Organizer
The Documentation for that an be found in its own folder.<file_sep>/word_counter.py
#This Program can count the number of words in a string or a .txt file.
word_count = 0
def main():
global word_count
word_count = 0
print 'Please enter a String or filename'
print 'If the file isn\'t in the same directory as the program, be sure to enter the full path! (e.g. C:/xxxx.txt, or E:/xxxxxxx/xxxx.txt'
string = raw_input()
if string[-4:] == '.txt':
read_file(string)
else:
for word in string.split():
if word.isalpha() == True:
word_count += 1
else:
pass
print 'There are ' + str(word_count) + ' words in that string.'
reset()
def read_file(file):
global word_count
word_count = 0
f = open(file, 'r')
for line in f:
print line
f.close()
f = open(file, 'r')
for word in f.read().split():
word_count += 1
print 'There are ' + str(word_count) + ' words in that file.'
f.close()
reset()
def reset():
print 'Would you like to count another string? (Press y or n)'
user_input = raw_input()
if user_input == 'y':
main()
elif user_input == 'n':
print 'Thank you for trying my program, Goodbye!'
quit()
else:
print 'Invalid input!'
reset()
main()<file_sep>/FizzBuzzinator.py
num_array = [num for num in range(13)]
fizz_counter, buzz_counter, fizzbuzz_counter = 0, 0, 0
fizz_nums, buzz_nums, fizzbuzz_nums = [], [], []
def main():
print 'Welcome to the FizzBuzzinator!'
fizzbuzz_gen()
def fizzbuzz_gen():
print 'Please enter a two different numbers (from 1 to 12) seperated by a comma \',\' (and no spaces!): '
inp = raw_input()
inp = inp.split(',')
for num in num_array:
if inp[0] != num in num_array:
inp[0] = 3
if inp[1] != num in num_array:
inp[1] = 5
x,y = inp
x,y = int(x),int(y)
print 'Now type in any 2 numbers you would like to create a range of seperated by a comma (and no spaces!): '
inp = raw_input()
inp = inp.split(',')
ran1, ran2 = inp
ran1, ran2 = int(ran1), int(ran2)
if ran1 > ran2 and ran1 <= 101:
_range = range(ran1, ran2, -1)
elif ran2 > ran1 and ran2 <= 101:
_range = range(ran1, ran2)
elif ran1 > ran2 and ran1 >= 101:
_range = xrange(ran1, ran2, -1)
else:
_range = xrange(ran1, ran2)
for num in _range:
if x > y:
if num % y == 0 and num % y == 0:
print str(num) + ' FizzBuzz'
fizzbuzz_counter += 1
fizzbuzz_nums.append(num)
fizz_counter += 1
fizz_nums.append(num)
buzz_counter += 1
buzz_nums.append(num)
elif num % y == 0:
print str(num) + ' Fizz'
fizz_counter += 1
fizz_nums.append(num)
elif num % x == 0:
print str(num) + ' Buzz'
buzz_counter += 1
buzz_nums.append(num)
else:
print num
else:
if num % x == 0 and num % y == 0:
print str(num) + ' FizzBuzz'
fizzbuzz_counter += 1
fizzbuzz_nums.append(num)
fizz_counter += 1
fizz_nums.append(num)
buzz_counter += 1
buzz_nums.append(num)
elif num % x == 0:
print str(num) + ' Fizz'
fizz_counter += 1
fizz_nums.append(num)
elif num % y == 0:
print str(num) + ' Buzz'
buzz_counter += 1
buzz_nums.append(num)
else:
print num
print 'Number of Fizz ticks: ' + str(fizz_counter)
print 'Numbers that Ticked Fizz:', fizz_nums
print 'Number of Buzz ticks: ' + str(buzz_counter)
print 'Numbers that Ticked Buzz:', buzz_nums
print 'Number of FizzBuzz ticks: ' + str(fizzbuzz_counter)
print 'Numbers that Ticked FizzBuzz:', fizzbuzz_nums
main()<file_sep>/tax-calc.py
price = float(input('Please enter the price of the item: '))
tax = float(input('Please enter your local sales tax: '))
total = ((tax / 100) * price) + price
print('Your item\'s price is: $' + str(round(total, 2)))
<file_sep>/string-reverser.py
string = ''
def intro():
'''
Prints an introduction message to the screen, takes in user input and assigns it to the global string function,
and then calls the string reversing function.
'''
global string
print 'Welcome to my string reverser program'
print 'With this program you can reverse any string you\'ve entered in the prompt'
string = raw_input('So Please enter the string you want to reverse: ')
str_rev()
def str_rev():
'''
Pulls the global string function assigned with string assigned by the intro() function, reverses it and
'''
global string
rev_string = string[::-1]
print rev_string
reset()
def reset():
cont = raw_input('Would you like to reverse another string? (Press y or n): ').lower()
if cont == 'y':
intro()
elif cont == 'n':
print 'Thanks you for running my program, Goodbye!'
quit()
else:
print 'Invalid selection!'
reset()
intro()<file_sep>/File Organizer/file_organizer.py
import os, glob, shutil, unicodedata
# Change to directory
print 'Please Enter the path to the directory you want to organize (or Press enter to organize current directory): '
directory = raw_input()
if directory == '':
directory = os.getcwd()
os.chdir(directory)
# Images
image_dir = './Images'
image_types = (u'*.jpg', u'*.jpeg', u'*.gif', u'*.png')
# Videos
video_dir = './Videos'
video_types = (u'*.mp4', u'*.avi', u'*.webm', u'*.flv', u'*.mkv', u'*.mpg')
# Music
music_dir = './Music'
music_types = (u'*.mp3', u'*.flac', u'*.wav')
# Documents
doc_dir = './Documents'
doc_types = (u'*.docx', u'*.txt', u'*.pdf', u'*.csv')
# Programs
prog_dir = './Programs'
prog_types = (u'*.exe', u'*.iso', u'*.msi')
# Zipped files
comp_dir = './Compressed'
comp_types = (u'*.zip', u'*.rar', u'*.gz', u'*.7z')
# Adobe files
adobe_dir = './Adobe'
adobe_types = (u'*.psd', u'*.psb', u'*.ai')
# Misc files
misc_dir = './Miscellaneous'
misc_types = (u'*.torrent', u'*.log')
# Directories to create tuple
directories_to_create = (image_dir, video_dir, music_dir, doc_dir, prog_dir, comp_dir, adobe_dir, misc_dir)
# If Directory doesn't exist, make directory.
for dirs in directories_to_create:
if not os.path.exists(dirs):
os.makedirs(dirs)
# Do nothing
else:
pass
# Grab files
images, videos, music, documents, programs, compressed, adobe, misc = [], [], [], [], [], [], [], []
for files in image_types:
images.extend(glob.glob(files))
for image in images:
# If aleady in a folder with Images in the name, skip moving files.
if image_dir[2::] in os.getcwd():
break
try:
shutil.move(image, image_dir)
except:
continue
for files in video_types:
videos.extend(glob.glob(files))
for video in videos:
# If aleady in a folder with Video in the name, skip moving files.
if video_dir[2::] in os.getcwd():
break
try:
shutil.move(video, video_dir)
except:
continue
for files in music_types:
music.extend(glob.glob(files))
for music_file in music:
# If aleady in a folder with Music in the name, skip moving files.
if music_dir[2::] in os.getcwd():
break
try:
shutil.move(music_file, music_dir)
except:
continue
for files in doc_types:
documents.extend(glob.glob(files))
for document in documents:
# If aleady in a folder with Documents in the name, skip moving files.
if doc_dir[2::] in os.getcwd():
break
try:
shutil.move(document, doc_dir)
except:
continue
for files in prog_types:
programs.extend(glob.glob(files))
for program in programs:
# If aleady in a folder with Programs in the name, skip moving files.
if prog_dir[2::] in os.getcwd():
break
try:
shutil.move(program, prog_dir)
except:
continue
for files in comp_types:
compressed.extend(glob.glob(files))
for zipped in compressed:
# If aleady in a folder with Compressed in the name, skip moving files.
if comp_dir[2::] in os.getcwd():
break
try:
shutil.move(zipped, comp_dir)
except:
continue
for files in adobe_types:
adobe.extend(glob.glob(files))
for ado_file in adobe:
# If aleady in a folder with Adobe in the name, skip moving files.
if adobe_dir[2::] in os.getcwd():
break
try:
shutil.move(ado_file, adobe_dir)
except:
continue
for files in misc_types:
misc.extend(glob.glob(files))
for misc_file in misc:
# If aleady in a folder with Miscellaneous in the name, skip moving files.
if misc_dir[2::] in os.getcwd():
break
try:
shutil.move(misc_file, misc_dir)
except:
continue
# If at the end of the scripts execution a created folder remains empty, delete that folder.
for dirs in directories_to_create:
if os.listdir(dirs) == []:
os.rmdir(dirs)<file_sep>/File Organizer/README.md
# File Organizer
## Documentation
### Overview
An Intermediate project, a file organizing script.
Not much else can be said about it, input a directory (or just press enter at the prompt to target your current working directory, i.e. the folder the script is in), and the script then creates folders for your file types, e.g. Music, Video, Images, etc. and moves your files to those respective folders. Don't worry about the folder's it creates, they'll instantly be deleted if they remain empty by the end of the script's runtime.
### Instructions
1. Run the Script
2. At the prompt enter the path to the directory you want to organize.
3. ????
4. Profit
It's that simple. | 47d5e622124cba2bfce51925ba97a45a0d7e73e9 | [
"Markdown",
"Python"
] | 9 | Python | DeshawnN/python-progs | c6b7bccd51cd2b3fa4a9a8d902eb3be9c8d973d9 | 1fb0f31c5761e6fc647624c678bae0915d0209b2 |
refs/heads/master | <repo_name>SadatIssah/polistas<file_sep>/shop/classes/product.php
<?php
include_once (dirname(__FILE__).'../../lib/database.php');
include_once (dirname(__FILE__).'../../helper/format.php');
?>
<?php
class Product{
private $db;
private $fm;
public function __construct()
{
$this->db = new Database();
$this->fm = new Format();
}
/**
* add product with image link to database
*
* @param [data] $data
* @param [file] $file
* @return void
*/
public function addproduct($data, $file){
$product_name = mysqli_real_escape_string($this->db->link,$data['product_name']);
$catID = mysqli_real_escape_string($this->db->link,$data['catID']);
$brandID = mysqli_real_escape_string($this->db->link,$data['brandID']);
$descr = mysqli_real_escape_string($this->db->link,$data['descr']);
$price = mysqli_real_escape_string($this->db->link,$data['price']);
$type = mysqli_real_escape_string($this->db->link,$data['typ']);
$permited = array('jpg','png','jpeg','gif');
$file_name = $file['img']['name'];
$file_size = $file['img']['size'];
$file_temp = $file['img']['tmp_name'];
$div = explode('.', $file_name);
$file_ext = strtolower(end($div));
$unique_image = substr(md5(time()), 0, 10).'.'.$file_ext;
$uploaded_image = "../upload/".$unique_image;
$image_name = "upload/".$unique_image;
if ($product_name == "" || $catID == "" || $brandID == "" || $descr == "" || $price == "" || $type == "" ) {
$msg = "<span class='error'>Field Must Not be empty .</span> ";
return $msg;
}else{
if (!empty($file_name)) {
if ($file_size > 1054589) {
echo "<span class='error'>Image Size should be less then 1MB .</span>";
}elseif (in_array($file_ext, $permited) === false) {
echo "<span class='error'> You can Upload Only".implode(',', $permited)."</span>";
} else{
move_uploaded_file($file_temp, $uploaded_image);
$query = "INSERT INTO shop_product(product_name,catID,brandID,descr,price,img,typ) VALUES('$product_name','$catID','$brandID','$descr','$price','$image_name','$type')";
$insert = $this->db->insert($query);
if($insert){
$msg = "<span style='color:green; font:18px;'>Added Successfully</span>";
return $msg ;
}else{
$msg ="<span style='color:red; font:18px;'>Not Inserted</span>";
return $msg;}
}
}
}
}
/**
* get all products from database
*/
public function productDisplay(){
$query = "SELECT shop_product.*, shop_category.catName, shop_brand.brand_name
FROM shop_product
INNER JOIN shop_category
ON shop_product.catID = shop_category.catID
INNER JOIN shop_brand
ON shop_product.brandID = shop_brand.brandID";
$result = $this->db->select($query);
return $result;
}
public function getProductbyID($product_id){
$query = "SELECT * FROM shop_product WHERE productID = '$product_id'";
$result = $this->db->select($query);
return $result;
}
/**
* function to update product product
*
* @param [data] $data
* @param [file] $file
* @param [id] $id
* @return void
*/
public function updateproduct($data, $file, $id){
$productName = mysqli_real_escape_string($this->db->link, $data['product_name'] );
$catId = mysqli_real_escape_string($this->db->link, $data['catID'] );
$brandId = mysqli_real_escape_string($this->db->link, $data['brandID'] );
$body = mysqli_real_escape_string($this->db->link, $data['descr'] );
$price = mysqli_real_escape_string($this->db->link, $data['price'] );
$type = mysqli_real_escape_string($this->db->link, $data['typ'] );
$permited = array('jpg','png','jpeg','gif');
$file_name = $file['img']['name'];
$file_size = $file['img']['size'];
$file_temp = $file['img']['tmp_name'];
$div = explode('.', $file_name);
$file_ext = strtolower(end($div));
$unique_image = substr(md5(time()), 0, 10).'.'.$file_ext;
$uploaded_image = "../upload/".$unique_image;
$image_name = "upload/".$unique_image;
if ($productName == "" || $catId == "" || $brandId == "" || $body == "" || $price == "" || $type == "" ) {
$msg = "<span class='error'>Field Must Not be empty .</span> ";
return $msg;
}else {
if (!empty($file_name)) {
if ($file_size > 1054589) {
echo "<span class='error'>Image Size should be less then 1MB .</span>";
}elseif (in_array($file_ext, $permited) === false) {
echo "<span class='error'> You can Upload Only".implode(',', $permited)."</span>";
} else{
move_uploaded_file($file_temp, $uploaded_image);
$query = "UPDATE shop_product
SET
product_name = '$productName',
catID = '$catId',
brandID = '$brandId',
descr = '$body',
price = '$price',
img = '$image_name',
typ = '$type'
WHERE productID = '$id' ";
$updated_row = $this->db->update($query);
if ($updated_row) {
$msg = "<span style='color:green; font:18px;'>Updated Successfully</span>";
return $msg;
}else {
$msg = "<span style='color:red; font:18px;'>Product Not Updated .</span> ";
return $msg;
}
}
} else{
$query = "UPDATE shop_product
SET
product_name = '$productName',
catID = '$catId',
brandID = '$brandId',
descr = '$body',
price = '$price',
typ = '$type'
WHERE productID = '$id' ";
$updated_row = $this->db->update($query);
if ($updated_row) {
$msg = "<span style='color:green; font:18px;'>Updated Successfully.</span> ";
return $msg;
}else {
$msg = "<span style='color:red; font:18px;'>Product Not Updated .</span> ";
return $msg;
}
}
}
}
/**
* delete a product from admin dashboard
*
* @param [int] $cdelete
* @return void
*/
public function deletbyID($cdelete){
$query = "SELECT * FROM shop_product WHERE productID = '$cdelete' ";
$getinfo = $this->db->select($query);
if ($getinfo) {
while ($delImg = $getinfo->fetch_assoc()) {
$dellink = $delImg['img'];
unlink($dellink);
}
}
$deletequery = "DELETE FROM shop_product WHERE productID = '$cdelete' ";
$deletedata = $this->db->delete($deletequery);
if ($deletedata) {
$msg = "<span class='success'>Product Deleted Successfully.</span> ";
return $msg;
}else {
$msg = "<span class='error'>Product Not Deleted .</span> ";
return $msg;
}
}
/**
* display featured products from database
*
* @return void
*/
public function displayFeaturedProducts(){
$query = "SELECT * FROM shop_product WHERE typ='0' ORDER BY productId DESC LIMIT 6 ";
$result = $this->db->select($query);
return $result;
}
/**
* display new products in home
*
* @return void
*/
public function displayNewProducts(){
$query = "SELECT * FROM shop_product ORDER BY productID DESC LIMIT 4 ";
$result = $this->db->select($query);
return $result;
}
/**
* Undocumented function
*
* @param [int] $product_id
* @return void
*/
public function displaySingleProduct($product_id){
$query = "SELECT shop_product.*, shop_category.catName, shop_brand.brand_name
FROM shop_product
INNER JOIN shop_category
ON shop_product.catID = shop_category.catID
INNER JOIN shop_brand
ON shop_product.brandID = shop_brand.brandID
AND shop_product.productID = $product_id
ORDER BY shop_product.productID DESC";
$result = $this->db->select($query);
return $result;
}
public function searchProduct($search){
$query = "SELECT * FROM shop_product WHERE product_name LIKE '%$search%' OR descr LIKE '%$search%' ";
$result = $this->db->select($query);
return $result;
}
public function displayAllProducts(){
$query = "SELECT * FROM shop_product LIMIT 20 ";
$result = $this->db->select($query);
return $result;
}
}
?><file_sep>/shop/admin/views/brandlist.php
<?php require (dirname(__FILE__).'/../inc/header.php');?>
<?php require (dirname(__FILE__).'/../inc/sidebar.php');?>
<?php require (dirname(__FILE__).'/../../classes/brand.php');?>
<?php
$brand = new Brand();
if(isset($_GET['delbrand'])){
$bdelete = $_GET['delbrand'];
$delbrand = $brand->deletbyID($bdelete);
}
?>
<div class="grid_10">
<div class="box round first grid">
<h2>Category List</h2>
<div class="block">
<?php
if(isset($delbrand)){
echo $delbrand;
}
?>
<table class="data display datatable" id="example">
<thead>
<tr>
<th>ID</th>
<th>Brand Name</th>
<th>Action</th>
</tr>
</thead>
<tbody>
<?php
$getbrand = $brand->brandDisplay();
if($getbrand){
while($result = $getbrand->fetch_assoc()){
?>
<tr class="odd gradeX">
<td><?php echo $result['brandID'];?></td>
<td><?php echo $result['brand_name'];?></td>
<td><a href="brandedit.php?brandid=<?php echo $result['brandID']; ?>">Edit</a>
|| <a onclick = "return confirm('Sure want to delete?')" href="?delbrand=<?php echo $result['brandID'];?>">Delete</a></td>
</tr>
<?php } } ?>
</tbody>
</table>
</div>
</div>
</div>
<script type="text/javascript">
$(document).ready(function () {
setupLeftMenu();
$('.datatable').dataTable();
setSidebarHeight();
});
</script>
<?php include '../inc/footer.php';?>
<file_sep>/chat/pages/test.php
<?php
include("../database/db.php");
$username = $_REQUEST['username'];
$user_name = $_REQUEST['user_name'];
?>
<?php
$update_msg = mysqli_query($con, "UPDATE chat_msg SET msg_status='read' WHERE sender_name='$username'
AND receiver_name='$user_name'");
$sel_msg = "select * from chat_msg where (sender_name='$user_name' AND receiver_name='$username') OR
(receiver_name='$user_name' AND sender_name='$username') ORDER by 1 ASC";
$run_msg = mysqli_query($con,$sel_msg);
while($row=mysqli_fetch_array($run_msg)){
$sender_username = $row['sender_name'];
$receiver_username = $row['receiver_name'];
$msg_content = $row['msg_content'];
$msg_status = $row['msg_status'];
$msg_date = $row['msg_date'];
?>
<ul>
<?php
if($user_name == $sender_username AND $username == $receiver_username){
echo"
<li>
<div class='rightside-right-chat'>
<span style='color: #fff'> $user_name <small>$msg_date</small> </span><br><br>
<p>$msg_content</p>
</div>
</li>
";
}
else if($user_name == $receiver_username AND $username == $sender_username){
echo"
<li>
<div class='rightside-left-chat'>
<span style='color: #fff'> $username <small>$msg_date</small> </span><br><br>
<p>$msg_content</p>
</div>
</li>
";
}
?>
</ul>
<?php
}
?>
<file_sep>/chat/functions/findFriends.php
<?php
$con = mysqli_connect("localhost","root","","db_polista") or die("Connection was not established");
function search_user(){
global $con;
if(isset($_GET['search_btn'])){
$search_query = htmlentities($_GET['search_query']);
$get_user = "select * from chat_users where first_name like '%$search_query%' or country like '%$search_query%'";
}
else{
$get_user = "select * from chat_users ORDER BY country,first_name DESC LIMIT 5";
}
$run_user = mysqli_query($con,$get_user);
// var_dump($run_user);
while($row_user = mysqli_fetch_assoc($run_user)){
$user_name = $row_user['first_name'];
$user_profile = $row_user['profile'];
$country = $row_user['country'];
$gender = $row_user['gender'];
//now displaying all at once
echo "
<div class='card'>
<img src='$user_profile'>
<h1>$user_name</h1>
<p class='title'>$country</p>
<p>$gender</p>
<form method='post'>
<p><button name='add'>Chat with $user_name</button></p>
</form>
</div><br><br>
";
if(isset($_POST['add'])){
echo "<script>window.open('../pages/home.php?user_name=$user_name','_self')</script>";
}
}
}
?><file_sep>/shop/classes/membership.php
<?php
include_once (dirname(__FILE__).'../../lib/database.php');
include_once (dirname(__FILE__).'../../helper/format.php');
?>
<?php
class Members{
private $db;
private $fm;
public function __construct()
{
$this->db = new Database();
$this->fm = new Format();
}
public function membersDisplay(){
$query = "SELECT * from chat_users";
$result = $this->db->select($query);
return $result;
}
public function passReset($email, $namel){
// generate a unique random token of length 100
$token = bin2hex(random_bytes(50));
// store token in the password-reset database table against the user's email
$sql = "INSERT INTO pass_reset(email, token) VALUES ('$email', '$token')";
$results = $this->db->insert($sql);
$query = "UPDATE chat_users SET approval = 'approved' WHERE email = '$email'";
$results1 = $this->db->insert($query);
// Send email to user with the token in a link they can click on
require 'PHPMailerAutoload.php';
$mail = new PHPMailer;
//$mail->SMTPDebug = 4; // Enable verbose debug output
$mail->isSMTP(); // Set mailer to use SMTP
$mail->Host = 'smtp.gmail.com'; // Specify main and backup SMTP servers
$mail->SMTPAuth = true; // Enable SMTP authentication
$mail->Username = '<EMAIL>'; // SMTP username
$mail->Password = '<PASSWORD>'; // SMTP password
$mail->SMTPSecure = 'tls'; // Enable TLS encryption, `ssl` also accepted
$mail->Port = 587; // TCP port to connect to
$mail->setFrom('<EMAIL>', 'African Polistas');
$mail->addAddress($email); // Add a recipient
// $mail->addReplyTo('<EMAIL>', 'Information');
// $mail->addCC('<EMAIL>');
// $mail->addBCC('<EMAIL>');
//$mail->addAttachment('/var/tmp/file.tar.gz'); // Add attachments
//$mail->addAttachment('/tmp/image.jpg', 'new.jpg'); // Optional name
$mail->isHTML(true); // Set email format to HTML
$mail->Subject = 'Password Reset';
$mail->Body = nl2br("Hi there"."\n you have being accepted as a member of African Polista. As a member, you will have access to our secured chat portal where you get to interact with other club members "."\n click on this <a href=\"localhost/chat/pages/new_pass.php?token=" . $token . "\">link</a> to reset your password on our site");
$mail->AltBody = nl2br("Hi there"."\n you have being accepted as a member of African Polista. As a member, you will have access to our secured chat portal where you get to interact with other club members "."\n click on this <a href=\"localhost/chat/pages/new_pass.php?token=" . $token . "\">link</a> to reset your password on our site");
if(!$mail->send()) {
$msg = "<span class='error'>User not Removed.</span>";
return $msg;
} else {
$msg = "<span class='success'>Email Sent Successfully.</span>";
return $msg;
}
}
public function deletbyID($cdelete){
$deletequery = "DELETE FROM chat_users WHERE ID = '$cdelete' ";
$deletedata = $this->db->delete($deletequery);
if ($deletedata) {
$msg = "<span class='success'>User Removed Successfully.</span> ";
return $msg;
}else {
$msg = "<span class='error'>User Not Removed .</span> ";
return $msg;
}
}
}
?><file_sep>/shop/pages/onlinepayment.php
<?php include '../inc/header.php'; ?>
<?php
$login_session = Session::get("userlogin");
if ($login_session == false) {
header("Location:login.php");
}
?>
<?php
//if (isset($_GET['order_id']) && $_GET['order_id'] == 'mtn' ) {
$customer_Id = Session::get("userId");
$total_amount = Session::get("sum");
//$vendor = $_GET['order_id'];
$transaID = rand(8, 12);
// $process_payment = $cart->processPayment($customer_Id, $total_amount,$vendor);
//$ordeAdded = $cart->add_order($customer_Id);
//$delcartData = $cart->deleteCustomerCartDetails();
//header("Location:onlinesuccess.php");
//}
?>
<?php
if (isset($_GET['order_id']) && $_GET['order_id'] == 'Vodafone' ) {
$customer_Id = Session::get("userId");
$total_amount = Session::get("sum");
$vendor = $_GET['order_id'];
$process_payment = $cart->processPayment($customer_Id, $total_amount,$vendor);
// header("Location:onlinesuccess.php");
}
?>
<?php
if (isset($_GET['order_id']) && $_GET['order_id'] == 'airtelTigo' ) {
$customer_Id = Session::get("userId");
$total_amount = Session::get("sum");
$vendor = $_GET['order_id'];
$process_payment = $cart->processPayment($customer_Id, $total_amount,$vendor);
//header("Location:onlinesuccess.php");
}
?>
<style>
.division{width: 50%;float: left;}
.tblone{width: 500px; margin: 0 auto; border: 2px solid #ddd; font-size: 13px;}
.tblone tr td{text-align: justify;}
.tbltwo{float:right;text-align:left; width: 50%;border: 2px solid #ddd;margin-right: 40px;margin-top: 12px;}
.tbltwo tr td{text-align: justify; padding: 5px 10px;}
.ordernow a{width:150px;margin: 5px auto 0;padding: 7px 0; text-align: center;display: block;background: #555;border: 1px solid #333;color: #fff;border-radius: 3px;font-size: 25px; margin-bottom: 40px;}
</style>
<div class="main">
<div class="content">
<div class="section group">
<div class="division">
<table class="tblone">
<tr>
<td>Sl</td>
<td>Product</td>
<td>Price</td>
<td>Quantity</td>
<td>Total</td>
</tr>
<?php
$sum = 0;
$get_cart_product = $cart->displayCartData();
if ($get_cart_product) {
$i = 0;
$sum = 0;
$qty = 0;
while ($result = $get_cart_product->fetch_assoc()) {
$i++;
?>
<tr>
<td><?php echo $i; ?></td>
<td><?php echo $result['product_name']; ?></td>
<td>GHC <?php echo $result['price']; ?></td>
<td> <?php echo $result['qty']; ?></td>
<td>
</td>
<td>GHC
<?php
$total = $result['price'] * $result['qty'];
echo $total;
?>
</td>
</tr>
<?php
$qty = $qty + $result['qty'];
$sum = $sum + $total;
Session::set("sum", $sum);
?>
<?php } } ?>
</table>
<table class="tbltwo">
<tr>
<th>Grand Total :</th>
<td>GHC
<?php
$gtotal = $sum;
echo $gtotal;
?> </td>
</tr>
</table>
</div>
<div class="division">
<?php
$id = Session::get('userId');
$get_customer_data = $customer->retrieveCustomerDetails($id);
if ($get_customer_data) {
while ($result = $get_customer_data->fetch_assoc()) {
$number = $result['phone'];
?>
<table class="tblone">
<tr>
<td colspan="3"> <h2> Your Profile Details </h2> </td>
</tr>
<tr>
<td width="20%"> Name </td>
<td width="5%"> : </td>
<td> <?php echo $result['fname']." ".$result['lname']; ?> </td>
</tr>
<tr>
<td> Phone </td>
<td> : </td>
<td> <?php echo $result['phone']; ?> </td>
</tr>
<tr>
<td> Email </td>
<td> : </td>
<td> <?php echo $result['email']; ?> </td>
</tr>
<tr>
<td> Address </td>
<td> : </td>
<td> <?php echo $result['addr']; ?> </td>
</tr>
<tr>
<td> City </td>
<td> : </td>
<td><?php echo $result['city']; ?> </td>
</tr>
<tr>
<td> Zipcode </td>
<td> : </td>
<td> <?php echo $result['zip']; ?> </td>
</tr>
<tr>
<td> Country </td>
<td> : </td>
<td> <?php echo $result['country']; ?> </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td><a href="editprofile.php"> Update Details </a> </td>
</tr>
</table>
<?php } } ?>
</div>
<?php
$total_amount = Session::get("sum");
//$vendor = $_GET['order_id'];
$transaID = rand(12,20);
echo"<a href='#' onclick='mtn($transaID, $total_amount, $number)'><img src='../images/mtn.jpg' style='width: 100px; height:80px'></a>
|<a href='#' onclick='tigo($transaID, $total_amount, $number)'><img src='../images/tigo.jpg' style='width: 100px; height:80px'></a>
|<a href='#' onclick='vodafone($transaID, $total_amount, $number)'><img src='../images/voda.jpg' style='width: 100px; height:80px'></a>";
?>
</div>
</div>
<?php include '../inc/footer.php'; ?><file_sep>/shop/classes/brand.php
<?php
include_once (dirname(__FILE__).'../../lib/database.php');
include_once (dirname(__FILE__).'../../helper/format.php');
?>
<?php
class Brand{
private $db;
private $fm;
public function __construct()
{
$this->db = new Database();
$this->fm = new Format();
}
/**
* add Brand item
*
* @param [text] $brandName
* @return void
*/
public function addBrabd($brandName){
$brandName = $this->fm->validation($brandName);
$brandName = mysqli_real_escape_string($this->db->link,$brandName);
if(empty($brandName)){
$msg = "Must Not be Empty";
return $msg;
}else{
$query = "INSERT INTO shop_brand(brand_name) VALUES('$brandName')";
$insert = $this->db->insert($query);
if($insert){
$msg = "<span style='color:green; font:18px;'>Added Successfully</span>";
return $msg ;
}else{
$msg ="<span style='color:red; font:18px;'>Not Inserted</span>";
return $msg;}
}
}
/**
* get all brand items from database
*/
public function brandDisplay(){
$query = "SELECT * FROM shop_brand";
$result = $this->db->select($query);
return $result;
}
/**
* get brand by id
*
* @param [int] $brand_id
* @return void
*/
public function getBrandbyId($brand_id){
$query = "SELECT * FROM shop_brand WHERE brandID = '$brand_id'";
$result = $this->db->select($query);
return $result;
}
/**
* update brand item
*
* @param [int] $brand_id
* @param [text] $brandName
* @return void
*/
public function updateBrand($brand_id, $brandName){
$brandName = $this->fm->validation($brandName);
$brandName = mysqli_real_escape_string($this->db->link,$brandName);
if(empty($brandName)){
$msg = "Must Not be Empty";
return $msg;
}else{
$query = "UPDATE shop_brand SET brand_name='$brandName' WHERE brandID='$brand_id'";
$insert = $this->db->update($query);
if($insert){
$msg = "<span style='color:green; font:18px;'>Updated Successfully</span>";
return $msg ;
}else{
$catmsg ="<span style='color:red; font:18px;'>Not Updated</span>";
return $msg;}
}
}
public function deletbyID($id){
$query = "DELETE FROM shop_brand WHERE brandID='$id'";
$result = $this->db->delete($query);
if($result){
$msg = "<span style='color:green; font:18px;'>Deleted Successfully</span>";
return $msg ;
}else{
$msg ="<span style='color:red; font:18px;'>Not Deleted</span>";
return $msg;}
}
}
?><file_sep>/shop/inc/header.php
<?php
header("Access-Control-Allow-Origin: *");
// header("Access-Control-Allow-Headers: X-Requested-With");
?>
<?php
include (dirname(__FILE__).'/../lib/session.php');
Session::init();
include (dirname(__FILE__).'/../lib/database.php');
include (dirname(__FILE__).'/../helper/format.php');
spl_autoload_register(function($class){
include_once "../classes/".$class.".php";
});
$db = new Database();
$fm = new Format();
$product = new Product();
$cart = new shopCart();
$customer = new Customers();
?>
<?php
if (isset($_GET['sid'])) {
Session::destroy();
$delDate = $cart->deleteCustomerCartDetails();
}
?>
<?php ?>
<!DOCTYPE php>
<head>
<title>Polista Stores</title>
<meta http-equiv="Content-Type" content="text/php; charset=utf-8" />
<meta name="viewport" content="width=device-width, initial-scale=1, maximum-scale=1">
<link href="../css/style.css" rel="stylesheet" type="text/css" media="all"/>
<link href="../css/menu.css" rel="stylesheet" type="text/css" media="all"/>
<script src="../js/jquerymain.js"></script>
<script type="text/javascript" href="https://code.jquery.com/jquery-3.4.1.min.js"></script>
<!-- <script src="../js/script.js" type="text/javascript"></script> -->
<!-- <script type="text/javascript" src="../js/jquery-1.7.2.min.js"></script> -->
<!-- <script type="text/javascript" src="../js/nav.js"></script>
<script type="text/javascript" src="../js/move-top.js"></script>
<script type="text/javascript" src="../js/easing.js"></script>
<script type="text/javascript" src="../js/nav-hover.js"></script> -->
<script type="text/javascript" src="../js/payment.js"></script>
<link href='http://fonts.googleapis.com/css?family=Monda' rel='stylesheet' type='text/css'>
<link href='http://fonts.googleapis.com/css?family=Doppio+One' rel='stylesheet' type='text/css'>
<?php
// header('Access-Control-Allow-Methods: GET, POST');
// header("Access-Control-Allow-Headers: X-Requested-With");
?>
<!-- <script type="text/javascript">
$(document).ready(function($){
$('#dc_mega-menu-orange').dcMegaMenu({rowItems:'4',speed:'fast',effect:'fade'});
});
</script> -->
</head>
<body>
<div class="wrap">
<div class="header_top">
<div class="logo">
<a href="../index.php"><img src="../images/poli_logo.jpg" style="width: 200px; height:80px" alt="" /></a>
</div>
<div class="header_top_right">
<div class="search_box">
<form action="search.php" method="get">
<input type="text" placeholder="Search for Products" name="search">
<input type="submit" value="SEARCH">
</form>
</div>
<div>
<div class="cart1"><a href="cart.php"><img src="../images/orange-shopping-cart-md.png" style="width: 120px; height:35px" alt="" /></a></div>
</div>
<div class="login"><?php $login = Session::get("userlogin");
if ($login == false) { ?>
<a href="login.php"><img src="../images/login1.png" style="width: 120px; height:35px" alt="" /></a>
<?php }else { ?>
<a href="?sid=<?php Session::get('userID')?>"><img src="../images/logout.png" style="width: 120px; height:35px" alt="" /></a>
<?php } ?>
</div>
<div class="clear"></div>
</div>
<div class="clear"></div>
</div>
<div class="menu">
<ul id="dc_mega-menu-orange" class="dc_mm-orange">
<li><a href="../index.php">Home</a></li>
<li><a href="products.php">Products</a> </li>
<?Php
$cartcheck = $cart->displayCartData();
if($cartcheck){ ?>
<li><a href="cart.php">Cart</a></li>
<li><a href="payment.php">Payment</a></li>
<?php }?>
<?Php
$login = Session::get("userlogin");
if($login == true){ ?>
<li><a href="profile.php">Profile</a></li>
<?php }?>
<?php
$userId = Session::get("userId");
$chkOrder = $cart->checkOrder($userId);
if ($chkOrder) { ?>
<li><a href="order.php">Orders</a></li>
<?php } ?>
<li><a href="contact.php">Contact</a> </li>
<div class="clear"></div>
</ul>
</div><file_sep>/shop/inc/indexheader.php
<?php
include (dirname(__FILE__).'/../lib/session.php');
Session::init();
include (dirname(__FILE__).'/../lib/database.php');
include (dirname(__FILE__).'/../helper/format.php');
spl_autoload_register(function($class){
include_once "classes/".$class.".php";
});
$db = new Database();
$fm = new Format();
$product = new Product();
$cart = new shopCart();
?>
<?php
if (isset($_GET['sid'])) {
Session::destroy1();
$delDate = $cart->deleteCustomerCartDetails();
}
?>
<?php ?>
<!DOCTYPE php>
<head>
<title>Polista Stores</title>
<meta http-equiv="Content-Type" content="text/php; charset=utf-8" />
<meta name="viewport" content="width=device-width, initial-scale=1, maximum-scale=1">
<link href="css/style.css" rel="stylesheet" type="text/css" media="all"/>
<link href="css/menu.css" rel="stylesheet" type="text/css" media="all"/>
<script src="js/jquerymain.js"></script>
<script src="js/script.js" type="text/javascript"></script>
<script type="text/javascript" src="js/jquery-1.7.2.min.js"></script>
<script type="text/javascript" src="js/nav.js"></script>
<script type="text/javascript" src="js/move-top.js"></script>
<script type="text/javascript" src="js/easing.js"></script>
<script type="text/javascript" src="js/nav-hover.js"></script>
<link href='http://fonts.googleapis.com/css?family=Monda' rel='stylesheet' type='text/css'>
<link href='http://fonts.googleapis.com/css?family=Doppio+One' rel='stylesheet' type='text/css'>
<script type="text/javascript">
$(document).ready(function($){
$('#dc_mega-menu-orange').dcMegaMenu({rowItems:'4',speed:'fast',effect:'fade'});
});
</script>
</head>
<body>
<div class="wrap">
<div class="header_top">
<div class="logo">
<a href="index.php"><img src="images/poli_logo.jpg" style="width: 200px; height:80px" alt="" /></a>
</div>
<div class="header_top_right">
<div class="search_box">
<form action="pages/search.php" method="get">
<input type="text" placeholder="Search for Products" name="search">
<input type="submit" value="SEARCH">
</form>
</div>
<div>
<div class="cart1"><a href="pages/cart.php"><img src="images/orange-shopping-cart-md.png" style="width: 120px; height:35px" alt="" /></a></div>
</div>
<div class="login"><?php $login = Session::get("userlogin");
if ($login == false) { ?>
<a href="pages/login.php"><img src="images/login1.png" style="width: 120px; height:35px" alt="" /></a>
<?php }else { ?>
<a href="?sid=<?php Session::get('userID')?>"><img src="images/logout.png" style="width: 120px; height:35px" alt="" /></a>
<?php } ?>
</div>
<div class="clear"></div>
</div>
<div class="clear"></div>
</div>
<div class="menu">
<ul id="dc_mega-menu-orange" class="dc_mm-orange">
<li><a href="index.php">Home</a></li>
<li><a href="pages/products.php">Products</a> </li>
<?Php
$cartcheck = $cart->displayCartData();
if($cartcheck){ ?>
<li><a href="pages/cart.php">Cart</a></li>
<li><a href="pages/payment.php">Payment</a></li>
<?php }?>
<?Php
$login = Session::get("userlogin");
if($login == true){ ?>
<li><a href="pages/profile.php">Profile</a></li>
<?php }?>
<?php
$userId = Session::get("userId");
$chkOrder = $cart->checkOrder($userId);
if ($chkOrder) { ?>
<li><a href="pages/order.php">Orders</a></li>
<?php } ?>
<li><a href="pages/contact.php">Contact</a> </li>
<div class="clear"></div>
</ul>
</div><file_sep>/shop/js/payment.js
function mtn(transaID, total_amount, number) {
$.ajax({
url: 'https://pay.npontu.com/api/pay',
type: 'post',
dataType: "jsonp",
data: {
number: number,
vendor: 'mtn',
uid: 'polista',
pass: '<PASSWORD>',
tp: transaID,
cbk: 'http://localhost/polista/shop/pages/onlinepayment.php',
amt: total_amount,
msg: 'PaymentForPurchase',
trans_type: 'debit'
},
success: function(data) {
console.log(data);
},
});
}
function tigo(transaID, total_amount, number) {
$.ajax({
url: 'https://pay.npontu.com/api/pay?',
type: 'post',
data: {
number: number,
vendor: 'tigo',
uid: 'polista',
pass: '<PASSWORD>',
tp: transaID,
cbk: 'er',
amt: total_amount,
msg: 'PaymentForPurchase',
trans_type: 'debit'
},
success: function() {
}
});
}
function vodafone(transaID, total_amount, number) {
$.ajax({
url: 'https://pay.npontu.com/api/pay?',
type: 'post',
data: {
number: number,
vendor: 'vodafone',
uid: 'polista',
pass: '<PASSWORD>',
tp: transaID,
cbk: 'er',
amt: total_amount,
msg: 'PaymentForPurchase',
vou: '422572322',
trans_type: 'debit'
},
success: function() {
}
});
}<file_sep>/shop/index.php
<?php include('inc/indexheader.php'); ?>
<?php
$product = new Product();
$category1 = new Category();
?>
<?php include('inc/slider.php'); ?>
<div class="main">
<div class="content">
<div class="content_top">
<div class="heading">
<h3 style="color:#F7C221;">Feature Products</h3>
</div>
<div class="clear"></div>
</div>
<div class="section group">
<?php
$festuredProducts = $product->displayFeaturedProducts();
if ($festuredProducts) {
while ($result = $festuredProducts->fetch_assoc()) {
?>
<div class="grid_1_of_4 images_1_of_4">
<a href="pages/preview.php?proid=<?php echo $result['productID']; ?>">
<img style="width: 300px; height:200px" src="admin/<?php echo $result['img']; ?>" alt="" /></a>
<h2><?php echo $result['product_name']; ?> </h2>
<p><?php echo $result['descr']; ?></p>
<p><span class="price">GHC<?php echo $result['price']; ?></span></p>
<div class="button"><span><a href="pages/preview.php?proid=<?php echo $result['productID']; ?>" class="details">Details</a></span></div>
</div>
<?php } } ?>
</div>
<div class="content_bottom">
<div class="heading">
<h3 style="color:#F7C221;">Latest Release</h3>
</div>
<div class="clear"></div>
</div>
<div class="section group">
<?php
$newProducts = $product->displayNewProducts();
if ($newProducts) {
while ($result = $newProducts->fetch_assoc()) {
?>
<div class="grid_1_of_4 images_1_of_4">
<a href="pages/preview.php?proid=<?php echo $result['productID']; ?>">
<img style="width: 300px; height:200px" src="admin/<?php echo $result['img']; ?>" alt="" /></a>
<h2><?php echo $result['product_name']; ?> </h2>
<p><span class="price">GHC<?php echo $result['price']; ?></span></p>
<p><?php echo $result['descr']; ?></p>
<div class="button"><span><a href="pages/preview.php?proid=<?php echo $result['productID']; ?>" class="details">Details</a></span></div>
</div>
<?php } } ?>
</div>
</div>
</div>
</div>
</div>
<?php include('inc/indexfooter.php'); ?><file_sep>/index.php
<?php include('inc/header.php'); ?>
<div class="brand-promotion">
<div class="container">
<div class="media row">
<div class="col-sm-4">
<div class="brand-content wow fadeIn animated" style="visibility: visible; -webkit-animation: fadeIn 700ms 300ms;">
<i class="fa fa-lightbulb-o fa-4x pull-left"></i>
<div class="media-body">
<h2>Ask Us Anything</h2>
<p>Lorem ipsum dolor sit amet, consectetur adipiscing elit Curabitur euismod enim a metus adipiscing aliquam. </p>
</div>
</div>
</div>
<div class="col-sm-4">
<div class="brand-content wow fadeIn animated" style="visibility: visible; -webkit-animation: fadeIn 700ms 400ms;">
<i class="fas fa-horse fa-4x pull-left"></i>
<div class="media-body">
<h2>Brand & Identity</h2>
<p>Lorem ipsum dolor sit amet, consectetur adipiscing elit Curabitur euismod enim a metus.</p>
</div>
</div>
</div>
<div class="col-sm-4">
<div class="brand-content wow fadeIn animated" style="visibility: visible; -webkit-animation: fadeIn 700ms 500ms;">
<i class="fa fa-life-ring fa-3x pull-left aria-hidden='true' "></i>
<div class="media-body">
<h2>Full Support</h2>
<p>Lorem ipsum dolor sit amet, consectetur adipiscing elit Curabitur euismod enim a metus adipiscing aliquam.</p>
</div>
</div>
</div>
</div>
</div>
</div>
<!--/SLIDER SECTION -->
<section id="home" class="sliderwrapper clearfix">
<div class="tp-banner-container">
<div class="tp-banner">
<ul>
<li data-transition="fade" data-slotamount="7" data-masterspeed="1500">
<!-- MAIN IMAGE -->
<img src="demos/horse1.jpg" alt="slidebg1" data-bgfit="cover" data-bgposition="center center" data-bgrepeat="no-repeat">
<div class="tp-dottedoverlay twoxtwo"></div>
<!-- LAYER NR. 3 -->
<div class="tp-caption rev-video customin customout start" data-x="center" data-hoffset="0" data-y="140" data-customin="x:0;y:0;z:0;rotationX:90;rotationY:0;rotationZ:0;scaleX:1;scaleY:1;skewX:0;skewY:0;opacity:0;transformPerspective:200;transformOrigin:50% 0%;"
data-customout="x:0;y:0;z:0;rotationX:0;rotationY:0;rotationZ:0;scaleX:0.75;scaleY:0.75;skewX:0;skewY:0;opacity:0;transformPerspective:600;transformOrigin:50% 50%;" data-speed="1000" data-start="500" data-easing="Back.easeInOut"
data-endspeed="300">
<hr class="topline">
<h2> <br> Weekdays <br> Weekends</h2>
<hr class="bottomline">
</div>
<!-- LAYER NR. 4 -->
<div class="tp-caption rev-video2 customin customout start" data-x="center" data-hoffset="0" data-y="340" data-customin="x:0;y:0;z:0;rotationX:90;rotationY:0;rotationZ:0;scaleX:1;scaleY:1;skewX:0;skewY:0;opacity:0;transformPerspective:200;transformOrigin:50% 0%;"
data-customout="x:0;y:0;z:0;rotationX:0;rotationY:0;rotationZ:0;scaleX:0.75;scaleY:0.75;skewX:0;skewY:0;opacity:0;transformPerspective:600;transformOrigin:50% 50%;" data-speed="2200" data-start="500" data-easing="Back.easeInOut"
data-endspeed="300">
<p> Horse Riding<br> School </p>
</div>
</li>
<li data-transition="fade" data-slotamount="7" data-masterspeed="1500">
<!-- MAIN IMAGE -->
<img src="demos/horse2.jpg" alt="slidebg2" data-bgfit="cover" data-bgposition="center center" data-bgrepeat="no-repeat">
<div class="tp-dottedoverlay twoxtwo"></div>
<!-- LAYER NR. 3 -->
<div class="tp-caption rev-video skewfromleft customout" data-x="center" data-y="140" data-customout="x:0;y:0;z:0;rotationX:0;rotationY:0;rotationZ:0;scaleX:0.75;scaleY:0.75;skewX:0;skewY:0;opacity:0;transformPerspective:600;transformOrigin:50% 50%;"
data-speed="800" data-start="1500" data-easing="Power4.easeOut" data-endspeed="300" data-endeasing="Power1.easeIn" data-captionhidden="on" style="z-index: 6">
<hr class="topline">
<h2>International <br> Competetions</h2>
<hr class="bottomline">
</div>
<!-- LAYER NR. 4 -->
<div class="tp-caption rev-video2 skewfromright customout" data-x="center" data-hoffset="0" data-y="340" data-customout="x:0;y:0;z:0;rotationX:0;rotationY:0;rotationZ:0;scaleX:0.75;scaleY:0.75;skewX:0;skewY:0;opacity:0;transformPerspective:600;transformOrigin:50% 50%;"
data-speed="800" data-start="1700" data-easing="Power4.easeOut" data-endspeed="300" data-endeasing="Power1.easeIn" data-captionhidden="on" style="z-index: 7">
<p>Endless Possibilities</p>
</div>
</li>
<li data-transition="fade" data-slotamount="7" data-masterspeed="1500">
<!-- MAIN IMAGE -->
<img src="demos/horse3.jpg" alt="slidebg3" data-bgfit="cover" data-bgposition="center center" data-bgrepeat="no-repeat">
<div class="tp-dottedoverlay twoxtwo"></div>
<!-- LAYER NR. 3 -->
<div class="tp-caption rev-video skewfromleft customout" data-x="center" data-y="140" data-customout="x:0;y:0;z:0;rotationX:0;rotationY:0;rotationZ:0;scaleX:0.75;scaleY:0.75;skewX:0;skewY:0;opacity:0;transformPerspective:600;transformOrigin:50% 50%;"
data-speed="800" data-start="1500" data-easing="Power4.easeOut" data-endspeed="300" data-endeasing="Power1.easeIn" data-captionhidden="on" style="z-index: 6">
<hr class="topline">
<h2>Horse<br>Stabling</h2>
<hr class="bottomline">
</div>
<!-- LAYER NR. 4 -->
<div class="tp-caption rev-video2 skewfromright customout" data-x="center" data-hoffset="0" data-y="340" data-customout="x:0;y:0;z:0;rotationX:0;rotationY:0;rotationZ:0;scaleX:0.75;scaleY:0.75;skewX:0;skewY:0;opacity:0;transformPerspective:600;transformOrigin:50% 50%;"
data-speed="800" data-start="1700" data-easing="Power4.easeOut" data-endspeed="300" data-endeasing="Power1.easeIn" data-captionhidden="on" style="z-index: 7">
<p>And we Take Good Care of Your Horses</p>
</div>
</li>
</ul>
<div class="tp-bannertimer"></div>
</div>
</div>
</section>
<!-- end slider-wrapper -->
<!--/ ABOUT SECTION -->
<section id="about" class="about-wrapper">
<div class="clearfix">
<div class="widget-wrapper">
<div class="container">
<div data-scroll-reveal="enter from the bottom after 0.3s" class="title text-center">
</div>
</div>
<!-- end col-lg-6 -->
</div>
<!-- end widget -->
</div>
<!-- end col-lg-6 -->
</div>
<!-- end container -->
</div>
</section>
<!-- End About Section -->
<!--/ COUNT SECTION -->
<section id="count_parallax" class="parallax" data-stellar-background-ratio="0.6" data-stellar-vertical-offset="20">
<div class="overlay">
<div class="container">
<div class="stat f-container">
<div class="f-element col-lg-3 col-md-3 col-sm-6 col-xs-12">
<div class="milestone-counter">
<i class="fa fa-user fa-3x"></i>
<span class="stat-count highlight">122</span>
<div class="milestone-details">Happy Members</div>
</div>
</div>
<div class="f-element col-lg-3 col-md-3 col-sm-6 col-xs-12">
<div class="milestone-counter">
<i class="fas fa-horse fa-3x"></i>
<span class="stat-count highlight">100</span>
<div class="milestone-details">Horses</div>
</div>
</div>
<div class="f-element col-lg-3 col-md-3 col-sm-6 col-xs-12">
<div class="milestone-counter">
<i class="fa fa-trophy fa-3x"></i>
<span class="stat-count highlight">14</span>
<div class="milestone-details">Awards Win</div>
</div>
</div>
<div class="f-element col-lg-3 col-md-3 col-sm-6 col-xs-12">
<div class="milestone-counter">
<i class="fa fa-flag fa-3x"></i>
<span class="stat-count highlight">7</span>
<div class="milestone-details">Countries Represented</div>
</div>
</div>
</div>
<!-- stat -->
</div>
<!-- end container -->
</div>
<!-- end overlay -->
</section>
<!--/ SERVICE SECTION -->
<section id="services" class="white-wrapper">
<div class="container">
<div class="title text-center">
<h2>Services we offer</h2>
<p><NAME>ESTIBULUM VOLUTPAT MORB</p>
<hr>
</div>
<!-- end title -->
<div class="row">
<div data-scroll-reveal="enter from the bottom after 0.3s" class="col-lg-4 col-md-4 col-sm-8 col-xs-12">
<div class="service-box">
<div class="service-border"><i class="fas fa-horse alignleft" style="font-size:44px"></i></div>
<h3>Riding School</h3>
<p>Quisque est enim lacinia lobortis da viverra interdum, quam. In sagittis, eros faucibus ullamcorper nibh dolor</p>
</div>
</div>
<div data-scroll-reveal="enter from the bottom after 0.6s" class="col-lg-4 col-md-4 col-sm-8 col-xs-12">
<div class="service-box">
<div class="service-border"><i class="fas fa-horse alignleft" style="font-size:44px"></i></div>
<h3>Stabling</h3>
<p>Quisque est enim lacinia lobortis da viverra interdum, quam. In sagittis, eros faucibus ullamcorper nibh dolor</p>
</div>
</div>
<div data-scroll-reveal="enter from the bottom after 0.9s" class="col-lg-4 col-md-4 col-sm-8 col-xs-12">
<div class="service-box">
<div class="service-border"><i class="fa fa-support alignleft"></i></div>
<h3>24/7 SUPPORT</h3>
<p>Quisque est enim lacinia lobortis da viverra interdum, quam. In sagittis, eros faucibus ullamcorper nibh dolor</p>
</div>
</div>
</div>
<!-- end row 1 -->
<div class="row">
<div data-scroll-reveal="enter from the bottom after 1.2s" class="col-lg-4 col-md-4 col-sm-8 col-xs-12">
<div class="service-box">
<div class="service-border"><i class="fa fa-truck alignleft"></i></div>
<h3>Horse Transportation</h3>
<p>Quisque est enim lacinia lobortis da viverra interdum, quam. In sagittis, eros faucibus ullamcorper nibh dolor</p>
</div>
</div>
<div data-scroll-reveal="enter from the bottom after 1.5s" class="col-lg-4 col-md-4 col-sm-8 col-xs-12">
<div class="service-box">
<div class="service-border"><i class="fa fa-shopping-cart alignleft"></i></div>
<h3>ONLINE SHOPPING</h3>
<p>Quisque est enim lacinia lobortis da viverra interdum, quam. In sagittis, eros faucibus ullamcorper nibh dolor</p>
</div>
</div>
<div data-scroll-reveal="enter from the bottom after 1.8s" class="col-lg-4 col-md-4 col-sm-8 col-xs-12">
<div class="service-box">
<div class="service-border"><i class="fa fa-gears alignleft"></i></div>
<h3>SOCIAL MEDIA</h3>
<p>Quisque est enim lacinia lobortis da viverra interdum, quam. In sagittis, eros faucibus ullamcorper nibh dolor</p>
</div>
</div>
</div>
</div>
<!-- end container -->
</section>
<!-- Service and Testimonial End -->
<!--/ SKILL SECTION -->
<!-- End Skill parallax -->
</div>
<!-- end column 1 -->
<!--/ VIDEO PARALLAX SECTINO -->
<section class="videobg clearfix text-center">
<a id="volume" onclick="$('#bgndVideo').toggleVolume()"><i class="fa fa-volume-down"></i></a>
<a id="bgndVideo" class="player" data-property="{videoURL:'https://www.youtube.com/watch?v=pTXUhx5jQGs',containment:'body',autoPlay:true, mute:true, startAt:33, opacity:1}">youtube</a>
<div class="videooverlay" data-scroll-reveal="enter from the bottom after 0.4s">
<div class="container">
<div class="general-title text-center">
<h3>Video Background Support</h3>
<p>This is an another awesome feature!</p>
</div>
</div>
<!-- end container -->
</div>
<!-- end overlay -->
</section>
<!--/ Video Parallex End -->
<!--/ PORTFOLIO SECTION -->
<section id="works" class="dark-wrapper">
<div class="container">
<div class="title text-center">
<h2>Our Best</h2>
<p>ETIAM DIGNISSIM LEO VESTIBULUM VOLUTPAT MORB</p>
<hr>
</div>
<!-- end title -->
<div class="text-center clearfix">
<nav class="portfolio-filter">
<ul>
<li><a class="btn btn-primary" href="#" data-filter="*"><span></span>All</a></li>
<li><a class="btn btn-primary" href="#" data-filter=".photography">Competetions</a></li>
<li><a class="btn btn-primary" href="#" data-filter=".webdesign">Horse Riding School</a></li>
<li><a class="btn btn-primary" href="#" data-filter=".logo">Horses</a></li>
</ul>
</nav>
</div>
<div class="norow">
<div class="masonry_wrapper" data-scroll-reveal="enter from the bottom after 0.5s">
<div class="item entry item-h2 photography print">
<img src="demos/work_01.jpg" alt="" class="img-responsive">
<div class="hovereffect">
<a data-gal="prettyPhoto[product-gallery]" rel="bookmark" href="demos/work_01.jpg"><span class="icon"><i class="fa fa-plus"></i></span></a>
<div class="buttons">
<h4>Portfolio Work</h4>
<h5>WEB DESIGN, LOGO, PRINT, VIDEO</h5>
</div>
<!-- end buttons -->
</div>
<!-- end hovereffect -->
</div>
<div class="item entry item-h2 webdesign print">
<img src="demos/work_02.jpg" alt="" class="img-responsive">
<div class="hovereffect">
<a data-gal="prettyPhoto[product-gallery]" rel="bookmark" href="demos/work_02.jpg"><span class="icon"><i class="fa fa-plus"></i></span></a>
<div class="buttons">
<h4>Portfolio Work</h4>
<h5>WEB DESIGN, LOGO, PRINT, VIDEO</h5>
</div>
<!-- end buttons -->
</div>
<!-- end hovereffect -->
</div>
<div class="item entry item-h2 videos print">
<img src="demos/work_03.jpg" alt="" class="img-responsive">
<div class="hovereffect">
<a data-gal="prettyPhoto[product-gallery]" rel="bookmark" href="demos/work_03.jpg"><span class="icon"><i class="fa fa-plus"></i></span></a>
<div class="buttons">
<h4>Portfolio Work</h4>
<h5>WEB DESIGN, LOGO, PRINT, VIDEO</h5>
</div>
<!-- end buttons -->
</div>
<!-- end hovereffect -->
</div>
<div class="item entry item-h2 photography">
<img src="demos/work_04.jpg" alt="" class="img-responsive">
<div class="hovereffect">
<a data-gal="prettyPhoto[product-gallery]" rel="bookmark" href="demos/work_04.jpg"><span class="icon"><i class="fa fa-plus"></i></span></a>
<div class="buttons">
<h4>Portfolio Work</h4>
<h5>WEB DESIGN, LOGO, PRINT, VIDEO</h5>
</div>
<!-- end buttons -->
</div>
<!-- end hovereffect -->
</div>
<div class="item entry item-h2 videos">
<img src="demos/work_05.jpg" alt="" class="img-responsive">
<div class="hovereffect">
<a data-gal="prettyPhoto[product-gallery]" rel="bookmark" href="demos/work_05.jpg"><span class="icon"><i class="fa fa-plus"></i></span></a>
<div class="buttons">
<h4>Portfolio Work</h4>
<h5>WEB DESIGN, LOGO, PRINT, VIDEO</h5>
</div>
<!-- end buttons -->
</div>
<!-- end hovereffect -->
</div>
<div class="item entry item-h2 webdesign">
<img src="demos/work_06.jpg" alt="" class="img-responsive">
<div class="hovereffect">
<a data-gal="prettyPhoto[product-gallery]" rel="bookmark" href="demos/work_06.jpg"><span class="icon"><i class="fa fa-plus"></i></span></a>
<div class="buttons">
<h4>Portfolio Work</h4>
<h5>WEB DESIGN, LOGO, PRINT, VIDEO</h5>
</div>
<!-- end buttons -->
</div>
<!-- end hovereffect -->
</div>
</div>
<!-- end portfolio-masonry -->
</div>
<!-- end row -->
</div>
<!-- end Container-->
</section>
<!-- end work -->
<!--/ CONTACT AND MAP SECTION -->
<section id="contact" class="contact-wrapper">
<div class="title text-center">
<h2>Contact Us</h2>
<p><NAME>IBULUM VOLUTPAT MORB</p>
<hr>
</div>
<!-- end title -->
<div class="container">
<div class="title text-center">
<div class="clearfix"></div>
<div class="col-lg-4 col-md-4 col-sm-12 col-xs-12">
<div class="contact-box" data-scroll-reveal="enter from the bottom after 0.6s">
<a title="" href="#"><i class="fa fa-envelope-o aligncenter"></i></a>
<h2><EMAIL></h2>
</div>
</div>
<div class="col-lg-4 col-md-4 col-sm-12 col-xs-12">
<div class="contact-box" data-scroll-reveal="enter from the bottom after 0.6s">
<a title="" href="#"><i class="fa fa-map-marker aligncenter"></i></a>
<h2>ATLAS PTY LTD, MELBOURNE, AUSTRALIA </h2>
</div>
</div>
<div class="col-lg-4 col-md-4 col-sm-12 col-xs-12">
<div class="contact-box" data-scroll-reveal="enter from the bottom after 0.6s">
<a title="" href="#"><i class="fa fa-phone aligncenter"></i></a>
<h2>+8 ATLAS 6666 </h2>
</div>
</div>
</div>
<!-- end title -->
</div>
<!-- end container -->
</section>
<!--/ Contact End -->
<!--/ FOOTER SECTION-->
<?php include('inc/footer.php'); ?>
<script>
(function($) {
var $container = $('.masonry_wrapper'),
colWidth = function() {
var w = $container.width(),
columnNum = 1,
columnWidth = 0;
if (w > 1200) {
columnNum = 3;
} else if (w > 900) {
columnNum = 3;
} else if (w > 600) {
columnNum = 2;
} else if (w > 300) {
columnNum = 1;
}
columnWidth = Math.floor(w / columnNum);
$container.find('.item').each(function() {
var $item = $(this),
multiplier_w = $item.attr('class').match(/item-w(\d)/),
multiplier_h = $item.attr('class').match(/item-h(\d)/),
width = multiplier_w ? columnWidth * multiplier_w[1] - 4 : columnWidth - 4,
height = multiplier_h ? columnWidth * multiplier_h[1] * 0.5 - 4 : columnWidth * 0.5 - 4;
$item.css({
width: width,
height: height
});
});
return columnWidth;
}
function refreshWaypoints() {
setTimeout(function() {}, 1000);
}
$('nav.portfolio-filter ul li a').on('click', function() {
var selector = $(this).attr('data-filter');
$container.isotope({
filter: selector
}, refreshWaypoints());
$('nav.portfolio-filter ul li a').removeClass('active');
$(this).addClass('active');
return false;
});
function setPortfolio() {
setColumns();
$container.isotope('reLayout');
}
isotope = function() {
$container.isotope({
resizable: true,
itemSelector: '.item',
masonry: {
columnWidth: colWidth(),
gutterWidth: 0
}
});
};
isotope();
$(window).smartresize(isotope);
}(jQuery));
</script>
<!-- SLIDER REVOLUTION 4.x SCRIPTS -->
<script type="text/javascript" src="rs-plugin/js/jquery.themepunch.plugins.min.js"></script>
<script type="text/javascript" src="rs-plugin/js/jquery.themepunch.revolution.min.js"></script>
<script type="text/javascript">
var revapi;
jQuery(document).ready(function() {
revapi = jQuery('.tp-banner').revolution({
delay: 9000,
startwidth: 1170,
startheight: 500,
hideThumbs: 10,
fullWidth: "off",
fullScreen: "on",
fullScreenOffsetContainer: ""
});
}); //ready
</script>
<!-- Animation Scripts-->
<script src="js/scrollReveal.js"></script>
<script>
(function($) {
"use strict"
window.scrollReveal = new scrollReveal();
})(jQuery);
</script>
<!-- Portofolio Pretty photo JS -->
<script src="js/jquery.prettyPhoto.js"></script>
<script type="text/javascript">
(function($) {
"use strict";
jQuery('a[data-gal]').each(function() {
jQuery(this).attr('rel', jQuery(this).data('gal'));
});
jQuery("a[data-gal^='prettyPhoto']").prettyPhoto({
animationSpeed: 'slow',
slideshow: false,
overlay_gallery: false,
theme: 'light_square',
social_tools: false,
deeplinking: false
});
})(jQuery);
</script>
<!-- Video Player o-->
<script src="js/jquery.mb.YTPlayer.js"></script>
<script type="text/javascript">
(function($) {
"use strict"
$(".player").mb_YTPlayer();
})(jQuery);
</script>
<script>
function myFunction() {
var dots = document.getElementById("dots");
var moreText = document.getElementById("more");
var btnText = document.getElementById("myBtn");
if (dots.style.display === "none") {
dots.style.display = "inline";
btnText.innerHTML = "Read more";
moreText.style.display = "none";
} else {
dots.style.display = "none";
btnText.innerHTML = "Read less";
moreText.style.display = "inline";
}
}
</script>
</body>
</html>
<file_sep>/shop/admin/views/customer.php
<?php require (dirname(__FILE__).'/../inc/header.php');?>
<?php require (dirname(__FILE__).'/../inc/sidebar.php');?>
<?php require (dirname(__FILE__).'/../../classes/customers.php');?>
<?php
if (!isset($_GET['custId']) || $_GET['custId'] == NULL ) {
echo "<script>window.location = 'adminorderpage.php'; </script>";
}else {
$id = $_GET['custId'];
}
?>
<?php
if ($_SERVER['REQUEST_METHOD'] == 'POST') {
echo "<script>window.location = 'adminorderpage.php'; </script>";
}
?>
<div class="grid_10">
<div class="box round first grid">
<h2>Customer Details</h2>
<div class="block copyblock">
<?php
$cus = new Customers();
$getCust = $cus->retrieveCustomerDetails($id);
if ($getCust) {
while ($result = $getCust->fetch_assoc()) {
?>
<form action=" " method="post">
<table class="form">
<tr>
<td> Customer Name </td>
<td>
<input type="text" readonly="readonly" value="<?php echo $result['fname'] ." ".$result['lname']; ?>" class="medium" />
</td>
</tr>
<tr>
<td> Customer Address </td>
<td>
<input type="text" readonly="readonly" value="<?php echo $result['addr']; ?>" class="medium" />
</td>
</tr>
<tr>
<td> Customer City </td>
<td>
<input type="text" readonly="readonly" value="<?php echo $result['city']; ?>" class="medium" />
</td>
</tr>
<tr>
<td> Customer Country </td>
<td>
<input type="text" readonly="readonly" value="<?php echo $result['country']; ?>" class="medium" />
</td>
</tr>
<tr>
<td> Customer Zip </td>
<td>
<input type="text" readonly="readonly" value="<?php echo $result['zip']; ?>" class="medium" />
</td>
</tr>
<tr>
<td> Customer Phone </td>
<td>
<input type="text" readonly="readonly" value="<?php echo $result['phone']; ?>" class="medium" />
</td>
</tr>
<tr>
<td> Customer Email </td>
<td>
<input type="text" readonly="readonly" value="<?php echo $result['email']; ?>" class="medium" />
</td>
</tr>
<tr>
<td>
<input type="submit" name="submit" Value="Ok" />
</td>
</tr>
</table>
</form>
<?php } } ?>
</div>
</div>
</div>
<?php require (dirname(__FILE__).'/../inc/footer.php');?><file_sep>/shop/pages/preview.php
<?php include('../inc/header.php'); ?>
<?php
$pd = new Product();
$cartobject = new ShopCart();
$category1 = new Category();
?>
<?php
if (!isset($_GET['proid']) || $_GET['proid'] == NULL ) {
echo "<script>window.location = '404.php'; </script> ";
}else{
$product_id = $_GET['proid'];
}
?>
<?php //listen to add to cart submit button
if ($_SERVER['REQUEST_METHOD'] == 'POST' && isset($_POST['sub'])) {
$qty1 = $_POST['qty'];
$cart1 = $cartobject->cartadd($qty1, $product_id);
}
?>
<?php
$getPd = $pd->displaySingleProduct($product_id);
?>
<div class="main">
<div class="content">
<div class="section group">
<div class="cont-desc span_1_of_2">
<?php
$displaySingle = $pd->displaySingleProduct($product_id);
if ($displaySingle) {
while ($result = $displaySingle->fetch_assoc()) {
?>
<div class="grid images_3_of_2">
<img style="width: 300px; height:200px" src="../admin/<?php echo $result['img']; ?>" alt="" />
</div>
<div class="desc span_3_of_2">
<h2><?php echo $result['product_name'];?> </h2>
<p><?php echo $result['descr'];?></p>
<div class="price">
<p>Price: <span>GHC<?php echo $result['price'];?></span></p>
<p>Category: <span><?php echo $result['catName'];?></span></p>
<p>Brand:<span><?php echo $result['brand_name'];?></span></p>
</div>
<div class="add-cart">
<form action=" " method="post">
<input type="number" class="buyfield" name="qty" value="1"/>
<input type="submit" class="buysubmit" name="sub" value="Add to Cart"/>
</form>
</div>
<?php if(isset($cart1)){
echo $cart1;
}?>
</div>
<div class="product-desc">
<h2>Product Details</h2>
<?php echo $result['descr'];?>
</div>
<?php } } ?>
</div>
<div class="rightsidebar span_3_of_1">
<h2>CATEGORIES</h2>
<ul>
<?php
$catdisplay = $category1->catDisplay();
if ($catdisplay) {
while ($result = $catdisplay->fetch_assoc()) {
?>
<li><a href="productbycat.php?catID=<?php echo $result['catID']; ?>"><?php echo $result['catName']; ?></a></li>
<?php } } ?>
</ul>
</div>
</div>
</div>
</div>
<div class="footer">
<div class="wrapper">
<div class="section group">
<div class="col_1_of_4 span_1_of_4">
<h4>Information</h4>
<ul>
<li><a href="#">About Us</a></li>
<li><a href="#">Customer Service</a></li>
<li><a href="#"><span>Advanced Search</span></a></li>
<li><a href="#">Orders and Returns</a></li>
<li><a href="#"><span>Contact Us</span></a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>Why buy from us</h4>
<ul>
<li><a href="about.php">About Us</a></li>
<li><a href="faq.php">Customer Service</a></li>
<li><a href="#">Privacy Policy</a></li>
<li><a href="contact.php"><span>Site Map</span></a></li>
<li><a href="preview-2.php"><span>Search Terms</span></a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>My account</h4>
<ul>
<li><a href="contact.php">Sign In</a></li>
<li><a href="cart.php">View Cart</a></li>
<li><a href="#">My Wishlist</a></li>
<li><a href="#">Track My Order</a></li>
<li><a href="faq.php">Help</a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>Contact</h4>
<ul>
<li><span><EMAIL></span></li>
<li><span>www.easylearningbd.com</span></li>
</ul>
<div class="social-icons">
<h4>Follow Us</h4>
<ul>
<li class="facebook"><a href="#" target="_blank"> </a></li>
<li class="twitter"><a href="#" target="_blank"> </a></li>
<li class="googleplus"><a href="#" target="_blank"> </a></li>
<li class="contact"><a href="#" target="_blank"> </a></li>
<div class="clear"></div>
</ul>
</div>
</div>
</div>
<div class="copy_right">
<p>easy Learning project & All rights Reseverd </p>
</div>
</div>
</div>
<script type="text/javascript">
$(document).ready(function() {
/*
var defaults = {
containerID: 'toTop', // fading element id
containerHoverID: 'toTopHover', // fading element hover id
scrollSpeed: 1200,
easingType: 'linear'
};
*/
$().UItoTop({ easingType: 'easeOutQuart' });
});
</script>
<a href="#" id="toTop" style="display: block;"><span id="toTopHover" style="opacity: 1;"></span></a>
</body>
</php>
<file_sep>/shop/admin/views/memberEdit.php
<?php require (dirname(__FILE__).'/../inc/header.php');?>
<?php require (dirname(__FILE__).'/../inc/sidebar.php');?>
<?php require (dirname(__FILE__).'/../../classes/membership.php');?>
<?php
if(!isset($_GET['uid']) || $_GET['uid'] == NULL){
echo "<script>window.location = 'user_profile.php'; </script>";
}
else{
$member_id = $_GET['uid'];
}
?>
<?php
$member = new Members();
// if($_SERVER['REQUEST_METHOD'] == 'POST' && isset($_POST['submitt'])){
// $update = $prod->updateproduct($_POST, $_FILES,$product_id);
// }
?>
<div class="grid_10">
<div class="box round first grid">
<h2>Update User Info</h2>
<div class="block">
<?php
// if(isset($update)){
// echo $update;
// }
?>
<?php
$memberbyID = $member->getMemberbyID($member_id);
if($memberbyID){
while($value = $memberbyID->fetch_assoc()){
?>
<form action="" method="post" enctype="multipart/form-data">
<table class="form">
<tr>
<td>
<label>First Name</label>
</td>
<td>
<input type="text" value = "<?php echo $value['first_name']?>" name="first_name" class="medium" />
</td>
</tr>
<tr>
<td>
<label>Last Name</label>
</td>
<td>
<input type="text" value = "<?php echo $value['last_name']?>" name="last_name" class="medium" />
</td>
</tr>
<tr>
<td>
<label>Phone</label>
</td>
<td>
<input type="text" value = "<?php echo $value['phone']?>" name="phone" class="medium" />
</td>
</tr>
<tr>
<td>
<label>Email</label>
</td>
<td>
<textarea class="tinymce" name="email" ><?php echo $value['email'] ?></textarea>
</td>
</tr>
<tr>
<td>
<label>Country</label>
</td>
<td>
<input type="text" name="country" value = "<?php echo $value['price']?>" class="medium" />
</td>
</tr>
<tr>
<td>
<label>Upload Image</label>
</td>
<td>
<img src="<?php echo '../'.$value['img'];?>" height=40px; width=60px;>
<input type="file" name="img" value = "<?php echo $value['img']?>"/>
</td>
</tr>
<tr>
<td>
<label>Product Type</label>
</td>
<td>
<select id="select" name="typ">
<option>Select Type</option>
<?php
if($value['typ'] == 0){?>
<option selected = "selected" value="0">Featured</option>
<option value="1">Non-Featured</option>
<?php } else {?>
}
<option value="0">Featured</option>
<option selected = "selected" value="1">Non-Featured</option>
<?php } ?>
</select>
</td>
</tr>
<tr>
<td></td>
<td>
<input type="submit" name="submitt" Value="Save" />
</td>
</tr>
</table>
</form>
<?php } } ?>
</div>
</div>
</div>
<!-- Load TinyMCE -->
<script src="/../js/tiny-mce/jquery.tinymce.js" type="text/javascript"></script>
<script type="text/javascript">
$(document).ready(function () {
setupTinyMCE();
setDatePicker('date-picker');
$('input[type="checkbox"]').fancybutton();
$('input[type="radio"]').fancybutton();
});
</script>
<!-- Load TinyMCE -->
<?php require (dirname(__FILE__).'/../inc/footer.php');?>
<file_sep>/shop/classes/shopCart.php
<?php
include_once (dirname(__FILE__).'../../lib/database.php');
include_once (dirname(__FILE__).'../../helper/format.php');
?>
<?php
class ShopCart{
private $db;
private $fm;
public function __construct()
{
$this->db = new Database();
$this->fm = new Format();
}
/**
* add to cart
*
* @param [int] $qty
* @param [int] $product_id
* @return void
*/
public function cartadd($qty, $product_id){
$session_id = session_id();
$squery = "SELECT * FROM shop_product WHERE productID = '$product_id'";
$result = $this->db->select($squery);
$result2 = $result->fetch_assoc();
$product_name = $result2['product_name'];
$price = $result2['price'];
$image = $result2['img'];
$query2 = "SELECT * FROM shop_cart WHERE productID = '$product_id' AND sessionID ='$session_id'";
$ifexist = $this->db->select($query2);
if($ifexist) {
$msg = "<span style='color: red; font-size: 18px;'>In Cart Already!</span>";
return $msg;
}else {
$query = "INSERT INTO shop_cart(sessionID, productID, product_name, price, qty, img)
VALUES ('$session_id','$product_id','$product_name','$price','$qty','$image')";
$inserted_row = $this->db->insert($query);
if ($inserted_row) {
header("Location:cart.php");
}else {
header("Location:404.php");
}
}
}
/**
* update cart quantity function
*
* @param [id] $cart_ID
* @param [int] $quant
* @return void
*/
public function cartquantupdat($cart_ID, $quant){
$query = "UPDATE shop_cart
SET
qty = '$quant'
WHERE cartID = '$cart_ID' ";
$update = $this->db->update($query);
if ($update) {
header("Location:cart.php");
}else {
$msg = "<span style='color: red; font-size: 18px;'>Not updated</span>";
return $msg;
}
}
/**
* display cart data
*
* @return void
*/
public function displayCartData(){
$sessionId = session_id();
$query = "SELECT * FROM shop_cart WHERE sessionID ='$sessionId' ";
$result = $this->db->select($query);
return $result;
}
/**
* Undocumented function
*
* @param [type] $id
* @return void
*/
public function deleteCartItem($id){
$deletequery = "DELETE FROM shop_cart WHERE cartID = '$id' ";
$deletedata = $this->db->delete($deletequery);
if ($deletedata) {
$msg = "<span style='color: green; font-size: 18px;'>Delete Success</span>";
return $msg;
}else {
$msg = "<span style='color: red; font-size: 18px;'>Product Not Deleted .</span> ";
return $msg;
}
}
/**
* display products by category
*
* @param [int] $cart_id
* @return void
*/
public function displayProductstByCat($cart_id){
$query = "SELECT * FROM shop_product WHERE catID ='$cart_id' ";
$result = $this->db->select($query);
return $result;
}
public function deleteCustomerCartDetails() {
$sId = session_id();
$query = "DELETE FROM shop_cart WHERE sessionID ='$sId'";
$this->db->delete($query);
}
public function add_order($customer_Id){
$sId = session_id();
$query = "SELECT * FROM shop_cart WHERE sessionID ='$sId' ";
$getProduct = $this->db->select($query);
if ($getProduct) {
while ($result = $getProduct->fetch_assoc()) {
$productId = $result['productID'];
$productName = $result['product_name'];
$quantity = $result['qty'];
$price = $result['price'];
$image = $result['img'];
$query = "INSERT INTO shop_orders(userID, productID, product_name, qty, price, img)
VALUES ('$customer_Id','$productId','$productName','$quantity','$price','$image')";
$inserted_row = $this->db->insert($query);
}
}
}
public function customer_order_details($Id){
$query = "SELECT * FROM shop_orders WHERE userID ='$Id' ORDER BY productID DESC ";
$result = $this->db->select($query);
return $result;
}
public function checkOrder($userId){
$query = "SELECT * FROM shop_orders WHERE userID ='$userId' ";
$result = $this->db->select($query);
return $result;
}
public function getAllOrderProduct(){
$query = "SELECT * FROM shop_orderS ORDER BY time ";
$result = $this->db->select($query);
return $result;
}
public function shipProduct($id,$time,$price){
$id = mysqli_real_escape_string($this->db->link, $id );
$date = mysqli_real_escape_string($this->db->link, $time );
$price = mysqli_real_escape_string($this->db->link, $price );
$query = "UPDATE shop_orders
SET
status = '1'
WHERE userID = '$id' AND time='$date' AND price='$price'";
$this->db->update($query);
}
public function deleteShippedProduct($id,$time,$price){
$id = mysqli_real_escape_string($this->db->link, $id );
$date = mysqli_real_escape_string($this->db->link, $time );
$price = mysqli_real_escape_string($this->db->link, $price );
$query = "DELETE FROM shop_orders WHERE userID = '$id' AND time='$date' AND price='$price'";
$this->db->delete($query);
}
public function processPayment($customer_Id,$total_amount, $vendor){
$query = "SELECT * FROM shop_users WHERE userID ='$customer_Id' ";
$getProduct = $this->db->select($query);
if ($getProduct) {
$result = $getProduct->fetch_assoc();
$number = $result['phone'];
}
//API URL
$url = "https://pay.npontu.com/api/pay";
//create a new cURL resource
$ch = curl_init();
//randomly generated transactionID
$transaID = rand(8, 12);
//setup request to send json via POST
if($vendor == 'Vodafone'){
$data = array(
'number' => $number,
'vendor' => $vendor,
'uid' => 'polista',
'pass' => '<PASSWORD>',
'tp' => $transaID,
'cbk' => '192.168.127.12',
'amt' => $total_amount,
'msg' => 'Payment to Polista for purchase made',
'vou' =>'422572322',
'trans_type'=>'debit'
);}
else{
$data = array(
'number' => $number,
'vendor' => $vendor,
'uid' => 'polista',
'pass' => '<PASSWORD>',
'tp' => $transaID,
'cbk' => '',
'amt' => $total_amount,
'msg' => 'Payment to Polista for purchase made',
'trans_type'=>'debit'
);
}
$payload = json_encode($data);
curl_setopt($ch, CURLOPT_URL,$url);
//attach encoded JSON string to the POST fields
curl_setopt($ch, CURLOPT_POSTFIELDS, $payload);
//set the content type to application/json
curl_setopt($ch, CURLOPT_HTTPHEADER, array('Content-Type:application/json'));
//return response instead of outputting
curl_setopt($ch, CURLOPT_RETURNTRANSFER, true);
//execute the POST request
$result = curl_exec($ch);
//return $result;
//close cURL resource
curl_close($ch);
}
}
?><file_sep>/chat/pages/home.php
<!DOCTYPE html>
<?php
session_start();
include("../database/db.php");
if(!isset($_SESSION['user_email'])){
header("location: ../pages/signin.php");
}
?>
<html>
<head>
<script src="https://ajax.googleapis.com/ajax/libs/jquery/3.4.1/jquery.min.js"></script>
<link rel="stylesheet" type="text/css" href="https://maxcdn.bootstrapcdn.com/bootstrap/3.3.7/css/bootstrap.min.css">
<link rel="stylesheet" type="text/css" href="../css/home.css">
<link rel="stylesheet" type="text/css" href="https://maxcdn.bootstrapcdn.com/font-awesome/4.7.0/css/font-awesome.min.css">
</head>
<body>
<div class="container main-section">
<div class="row">
<div class="col-md-3 col-sm-3 col-xs-12 left-sidebar">
<div class="input-group searchbox">
<div class="input-group-btn">
<center><a href="../include/find_friends.php"><button class="btn btn-default search-icon" name="search_user" type="submit">Add new user</button></a></center>
</div>
</div>
<div class="left-chat">
<ul>
<?php include("../functions/get_users_data.php"); ?>
</ul>
</div>
</div>
<div class="col-md-9 col-sm-9 col-xs-12 right-sidebar">
<div class="row">
<!-- getting the user information who is logged in -->
<?php
$user = $_SESSION['user_email'];
$get_user = "select * from chat_users where email='$user'";
$run_user = mysqli_query($con,$get_user);
$row=mysqli_fetch_array($run_user);
$user_id = $row['ID'];
$user_name = $row['first_name'];
?>
<!-- getting the user data on which user click -->
<?php
if(isset($_GET['user_name'])){
global $con;
$get_username = $_GET['user_name'];
$get_user = "select * from chat_users where first_name='$get_username'";
$run_user = mysqli_query($con,$get_user);
$row_user=mysqli_fetch_array($run_user);
$username = $row_user['first_name'];
$user_profile_image = $row_user['profile'];
}
$total_messages = "select * from chat_msg where (sender_name='$user_name' AND receiver_name='$username')
OR (receiver_name='$user_name' AND sender_name='$username')";
$run_messages = mysqli_query($con,$total_messages);
$total = mysqli_num_rows($run_messages);
?>
<div class="col-md-12 right-header">
<div class="right-header-img">
<img src=<?php echo"$user_profile_image";?>>
</div>
<div class="right-header-detail">
<form method="post">
<p><?php echo"$username";?></p>
<span><?php echo $total; ?> messages</span>   
<button name="logout" class="btn btn-danger">Logout</button>
</form>
<?php
if(isset($_POST['logout'])){
$update_msg = mysqli_query($con, "UPDATE chat_users SET login ='Offline' WHERE first_name='$user_name'");
header("Location:logout.php");
exit();
}
?>
</div>
</div>
</div>
<div class="row" >
<div id="scrolling_to_bottom" class="col-md-12 right-header-contentChat" style="background-color: #3A3A3A;">
</div>
</div>
<div class="row">
<div class="col-md-12 right-chat-textbox">
<form method="post">
<input autocomplete="off" type="text" id ="msg" name="msg_content" placeholder="Write your message...">
<input autocomplete="off" type="hidden" id ="user1" value="<?php echo($username); ?>">
<input autocomplete="off" type="hidden" id ="user2" value="<?php echo($user_name); ?>">
<input autocomplete="off" type="hidden" id ="success" value="<?php echo "home.php?user_name=".($username); ?>">
<a class='btn1' id ="id"><button>send</button></a>
<!-- // <a href='#' onclick='send11($U)'><button class='btn' name='submit' ><i class='fa fa-telegram'></i></button></a> -->
</form>
</div>
</div>
</div>
</div>
</div>
<?php
// if(isset($_POST['submit'])){
// $msg = htmlentities($_POST['msg_content']);
// if($msg == ""){
// echo"
// <div class='alert alert-danger'>
// <strong><center>Message was unable to send!</center></strong>
// </div>
// ";
// }else if(strlen($msg) > 100){
// echo"
// <div class='alert alert-danger'>
// <strong><center>Message is Too long! Use only 100 characters</center></strong>
// </div>
// ";
// }
// else{
// $insert = "insert into chat_msg(sender_name,receiver_name,msg_content,msg_status,msg_date)
// values ('$user_name','$username','$msg','unread',NOW())";
// $run_insert = mysqli_query($con,$insert);
// }
// }
?>
<script>
// $('#scrolling_to_bottom').animate({
// scrollTop: $('#scrolling_to_bottom').get(0).scrollHeight}, 1000);
</script>
<script>
var user1 = $("#user1").val();
var user2 = $("#user2").val();
$(function() {
setInterval(startRefresh, 0.1);
});
function startRefresh() {
$.get('test.php',{username: user1, user_name: user2 }, function(data) {
//alert(data);
$('#scrolling_to_bottom').html(data);
scroll();
});
}
function scroll(){
$('#scrolling_to_bottom').animate({
scrollTop: $('#scrolling_to_bottom').get(0).scrollHeight}, 0.001);
}
</script>
<script type="text/javascript">
$(document).ready(function(){
var height = $(window).height();
$('.left-chat').css('height', (height - 92) + 'px');
$('.right-header-contentChat').css('height', (height - 163) + 'px');
});
</script>
<script type="text/javascript" src="../js/main.js"></script>
</body>
</html>
<file_sep>/shop/admin/views/brandadd.php
<?php require (dirname(__FILE__).'/../inc/header.php');?>
<?php require (dirname(__FILE__).'/../inc/sidebar.php');?>
<?php require (dirname(__FILE__).'/../../classes/brand.php');?>
<?php
$brand = new Brand();
if($_SERVER['REQUEST_METHOD'] == 'POST'){
$brand_name = $_POST['brandName'];
$addbrand = $brand->addBrabd($brand_name);
}
?>
<div class="grid_10">
<div class="box round first grid">
<h2>Add New Brand</h2>
<div class="block copyblock">
<?php
if(isset($addbrand)){
echo $addbrand;
}
?>
<form method="post", action=" ">
<table class="form">
<tr>
<td>
<input type="text" placeholder="Enter Brand Name..." class="medium" name="brandName"/>
</td>
</tr>
<tr>
<td>
<input type="submit" name="submit" Value="Save" />
</td>
</tr>
</table>
</form>
</div>
</div>
</div>
<?php require (dirname(__FILE__).'/../inc/footer.php');?><file_sep>/functions/members.php
<?php
// connect to database
$db = mysqli_connect('localhost', 'root', '', 'db_polista');
if (isset($_POST['submit'])) {
$fname = $_POST['f_name'];
$lname = $_POST['l_name'];
$phone = $_POST['phone'];
$email = $_POST['email'];
$gender = $_POST['gender'];
$country = $_POST['country'];
if(empty($fname) || empty($lname) || empty($phone) || empty($email) || empty($gender) || empty($country)){
}
else{
$query = "INSERT INTO chat_users(first_name, last_name, phone, gender,country,email)
VALUES('$fname', '$lname', '$phone', '$gender','$country', '$email')";
$results = mysqli_query($db, $query);
// Send email to user with the token in a link they can click on
require 'PHPMailerAutoload.php';
$mail = new PHPMailer;
//$mail->SMTPDebug = 4; // Enable verbose debug output
$mail->isSMTP(); // Set mailer to use SMTP
$mail->Host = 'smtp.gmail.com'; // Specify main and backup SMTP servers
$mail->SMTPAuth = true; // Enable SMTP authentication
$mail->Username = '<EMAIL>'; // SMTP username
$mail->Password = '<PASSWORD>'; // SMTP password
$mail->SMTPSecure = 'tls'; // Enable TLS encryption, `ssl` also accepted
$mail->Port = 587; // TCP port to connect to
$mail->setFrom('<EMAIL>', 'African Polistas');
$mail->addAddress($email); // Add a recipient
// $mail->addReplyTo('<EMAIL>', 'Information');
// $mail->addCC('<EMAIL>');
// $mail->addBCC('<EMAIL>');
//$mail->addAttachment('/var/tmp/file.tar.gz');
//$mail->addAttachment('/tmp/image.jpg', 'new.jpg');
$mail->isHTML(true);
$mail->Subject = 'Membership Registration';
$mail->Body = "Hi " .$fname. " \n Thank you for registering to be a member of African Polistas, a team member
will be intouch shortly to process your request. Should you be accepted as a member, you will have access
to use our chat portal where you can interact with other members. Thank you";
$mail->AltBody = "Hi" .$fname. "Thank you for registering to be a member of African Polistas, a team member
will be intouch shortly to process your request. Should you be accepted as a member, you will have access
to use our chat portal where you can interact with other members. Thank you";
if(!$mail->send()) {
echo 'Message could not be sent.';
echo 'Mailer Error: ' . $mail->ErrorInfo;
} else {
//echo 'Message has been sent';
}
header('location: index.php');
}
}
?><file_sep>/chat/functions/signin_user.php
<?php
session_start();
include("../database/db.php");
if(isset($_POST['sign_in'])){
$email = $_POST['email'];
$pass = md5($_POST['pass']);
$query = "select * from chat_users where email ='$email' AND pass ='$pass'";
$result = mysqli_query($con,$query);
$check_user = mysqli_num_rows($result);
if($check_user==1){
$_SESSION['user_email']=$email;
$update_msg = mysqli_query($con, "UPDATE chat_users SET login='Online' WHERE email='$email'");
$user = $_SESSION['user_email'];
$get_user = "select * from chat_users where email='$user'";
$run_user = mysqli_query($con,$get_user);
$row=mysqli_fetch_array($run_user);
$user_name = $row['first_name'];
echo "<script>window.open('home.php?user_name=$user_name','_self')</script>";
}
else {
echo "
<div class='alert alert-danger'>
<strong>Check your email and password!</strong>
</div>
";
}
}
?><file_sep>/shop/admin/views/adminorderpage.php
<?php require (dirname(__FILE__).'/../inc/header.php');?>
<?php require (dirname(__FILE__).'/../inc/sidebar.php');?>
<?php require (dirname(__FILE__).'/../../classes/shopCart.php');?>
<?php $cart = new ShopCart();?>
<?php
if (isset($_GET['shipid'])) {
$id = $_GET['shipid'];
$price = $_GET['price'];
$time = $_GET['time'];
$ship = $cart->shipProduct($id,$time,$price);
}
?>
<?php
if (isset($_GET['delproid'])) {
$id = $_GET['delproid'];
$price = $_GET['price'];
$time = $_GET['time'];
$delOrder = $cart->deleteShippedProduct($id,$time,$price);
}
?>
<div class="grid_10">
<div class="box round first grid">
<h2>Customer Order</h2>
<div class="block">
<table class="data display datatable" id="example">
<thead>
<tr>
<th>Order ID</th>
<th>Order Date</th>
<th>Product</th>
<th>quantity</th>
<th>Price</th>
<th>Customer ID</th>
<th>Address</th>
<th>Action</th>
</tr>
</thead>
<tbody>
<?php
$allOrders = $cart->getAllOrderProduct();
if ($allOrders) {
while ($result = $allOrders->fetch_assoc()) {
?>
<tr class="odd gradeX">
<td><?php echo $result['orderID']; ?></td>
<td><?php echo $result['time']; ?></td>
<td><?php echo $result['product_name']; ?></td>
<td><?php echo $result['qty']; ?></td>
<td><?php echo $result['price']; ?></td>
<td><?php echo $result['userID']; ?></td>
<td><a href="customer.php?custId=<?php echo $result['userID']; ?>"> View Address</a></td>
<?php if ($result['status'] == '0') { ?>
<td><a href="?shipid=<?php echo $result['userID']; ?>&price=<?php echo $result['price']; ?>&time=<?php echo $result['time']; ?>">Shipped</a></td>
<?php } else { ?>
<td><a href="?delproid=<?php echo $result['userID']; ?>&price=<?php echo $result['price']; ?>&time=<?php echo $result['time']; ?>">Remove</a></td>
<?php } ?>
</tr>
<?php } } ?>
</tbody>
</table>
</div>
</div>
</div>
<script type="text/javascript">
$(document).ready(function () {
setupLeftMenu();
$('.datatable').dataTable();
setSidebarHeight();
});
</script>
<?php require (dirname(__FILE__).'/../inc/footer.php');?><file_sep>/shop/pages/contact.php
<?php include('../inc/header.php'); ?>
<div class="main">
<div class="content">
<div class="support">
<div class="support_desc">
<h3>Live Support</h3>
<p><span>24 hours | 7 days a week | 365 days a year Live Technical Support</span></p>
<p> It is a long established fact that a reader will be distracted by the readable content of a page when looking at its layout. The point of using Lorem Ipsum is that it has a more-or-less normal distribution of letters.There are many variations of passages of Lorem Ipsum available, but the majority have suffered alteration in some form, by injected humour, or randomised words which don't look even slightly believable. If you are going to use a passage of Lorem Ipsum, you need to be sure there isn't anything embarrassing hidden in the middle of text.</p>
</div>
<img src="web/images/contact.png" alt="" />
<div class="clear"></div>
</div>
<div class="section group">
<div class="col span_2_of_3">
<div class="contact-form">
<h2>Contact Us</h2>
<form>
<div>
<span><label>NAME</label></span>
<span><input type="text" value=""></span>
</div>
<div>
<span><label>E-MAIL</label></span>
<span><input type="text" value=""></span>
</div>
<div>
<span><label>MOBILE.NO</label></span>
<span><input type="text" value=""></span>
</div>
<div>
<span><label>SUBJECT</label></span>
<span><textarea> </textarea></span>
</div>
<div>
<span><input type="submit" value="SUBMIT"></span>
</div>
</form>
</div>
</div>
<div class="col span_1_of_3">
<div class="company_address">
<h2>Company Information :</h2>
<p>500 Lorem Ipsum Dolor Sit,</p>
<p>22-56-2-9 Sit Amet, Lorem,</p>
<p>USA</p>
<p>Phone:(00) 222 666 444</p>
<p>Fax: (000) 000 00 00 0</p>
<p>Email: <span><EMAIL></span></p>
<p>Follow on: <span>Facebook</span>, <span>Twitter</span></p>
</div>
</div>
</div>
</div>
</div>
</div>
<div class="footer">
<div class="wrapper">
<div class="section group">
<div class="col_1_of_4 span_1_of_4">
<h4>Information</h4>
<ul>
<li><a href="#">About Us</a></li>
<li><a href="#">Customer Service</a></li>
<li><a href="#"><span>Advanced Search</span></a></li>
<li><a href="#">Orders and Returns</a></li>
<li><a href="#"><span>Contact Us</span></a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>Why buy from us</h4>
<ul>
<li><a href="about.html">About Us</a></li>
<li><a href="faq.html">Customer Service</a></li>
<li><a href="#">Privacy Policy</a></li>
<li><a href="contact.html"><span>Site Map</span></a></li>
<li><a href="preview-2.html"><span>Search Terms</span></a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>My account</h4>
<ul>
<li><a href="contact.html">Sign In</a></li>
<li><a href="index.html">View Cart</a></li>
<li><a href="#">My Wishlist</a></li>
<li><a href="#">Track My Order</a></li>
<li><a href="faq.html">Help</a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>Contact</h4>
<ul>
<li><span><EMAIL></span></li>
<li><span>www.easylearningbd.com</span></li>
</ul>
<div class="social-icons">
<h4>Follow Us</h4>
<ul>
<li class="facebook"><a href="#" target="_blank"> </a></li>
<li class="twitter"><a href="#" target="_blank"> </a></li>
<li class="googleplus"><a href="#" target="_blank"> </a></li>
<li class="contact"><a href="#" target="_blank"> </a></li>
<div class="clear"></div>
</ul>
</div>
</div>
</div>
<div class="copy_right">
<p>easy Learning project & All rights Reseverd </p>
</div>
</div>
</div>
<script type="text/javascript">
$(document).ready(function() {
/*
var defaults = {
containerID: 'toTop', // fading element id
containerHoverID: 'toTopHover', // fading element hover id
scrollSpeed: 1200,
easingType: 'linear'
};
*/
$().UItoTop({ easingType: 'easeOutQuart' });
});
</script>
<a href="#" id="toTop" style="display: block;"><span id="toTopHover" style="opacity: 1;"></span></a>
</body>
</html>
<file_sep>/shop/classes/category.php
<?php
//include_once('../lib/database.php');
include_once (dirname(__FILE__).'../../lib/database.php');
include_once (dirname(__FILE__).'../../helper/format.php');
?>
<?php
class Category{
private $db;
private $fm;
public function __construct()
{
$this->db = new Database();
$this->fm = new Format();
}
/**
* add category item
*
* @param [text] $catName
* @return void
*/
public function addCat($catName){
$catName = $this->fm->validation($catName);
$catName = mysqli_real_escape_string($this->db->link,$catName);
if(empty($catName)){
$catmsg = "Must Not be Empty";
return $catmsg;
}else{
$query = "INSERT INTO shop_category(catName) VALUES('$catName')";
$catInsert = $this->db->insert($query);
if($catInsert){
$catmsg = "<span style='color:green; font:18px;'>Added Successfully</span>";
return $catmsg ;
}else{
$catmsg ="<span style='color:red; font:18px;'>Not Inserted</span>";
return $catmsg;}
}
}
/**
* get all category items from database
*/
public function catDisplay(){
$query = "SELECT * FROM shop_category";
$result = $this->db->select($query);
return $result;
}
/**
* get category by id
*
* @param [int] $cat_id
* @return void
*/
public function getCatbyId($cat_id){
$query = "SELECT * FROM shop_category WHERE catID = '$cat_id'";
$result = $this->db->select($query);
return $result;
}
/**
* update category item
*
* @param [int] $cat_id
* @param [text] $catName
* @return void
*/
public function updateCat($cat_id, $catName){
$catName = $this->fm->validation($catName);
$catName = mysqli_real_escape_string($this->db->link,$catName);
if(empty($catName)){
$catmsg = "Must Not be Empty";
return $catmsg;
}else{
$query = "UPDATE shop_category SET catName='$catName' WHERE catID='$cat_id'";
$catInsert = $this->db->update($query);
if($catInsert){
$catmsg = "<span style='color:green; font:18px;'>Updated Successfully</span>";
return $catmsg ;
}else{
$catmsg ="<span style='color:red; font:18px;'>Not Updated</span>";
return $catmsg;}
}
}
public function deletbyID($id){
$query = "DELETE FROM shop_category WHERE catID='$id'";
$result = $this->db->delete($query);
if($result){
$catmsg = "<span style='color:green; font:18px;'>Deleted Successfully</span>";
return $catmsg ;
}else{
$catmsg ="<span style='color:red; font:18px;'>Not Deleted</span>";
return $catmsg;}
}
}
?><file_sep>/shop/pages/cart.php
<?php include('../inc/header.php'); ?>
<?php
$cartobject = new ShopCart();
?>
<?php
if ($_SERVER['REQUEST_METHOD'] == 'POST') {
$quant = $_POST['qty'];
$cart_ID = $_POST['cartID'];
if($quant <= 0){
echo "<script type='text/javascript'>alert('Zero or Negative quantity not allowed');</script>";
}
else{
$cartUpdate = $cartobject->cartquantupdat($cart_ID, $quant);
}
}
?>
<?php
if (isset($_GET['del'])) {
$id = $_GET['del'];
$delete = $cartobject->deleteCartItem($id);
}
?>
<div class="main">
<div class="content">
<div class="cartoption">
<div class="cartpage">
<h2>Your Cart</h2>
<?Php
if(isset($delete)){
echo $delete;
}
?>
<table class="tblone">
<tr>
<th width="20%">Product Name</th>
<th width="10%">Image</th>
<th width="15%">Price</th>
<th width="25%">Quantity</th>
<th width="20%">Total Price</th>
<th width="10%">Action</th>
</tr>
<?php
$cart_data = $cartobject ->displayCartData();
$total = 0;
if($cart_data){
while($result = $cart_data->fetch_assoc()){
?>
<tr>
<td><?php echo $result['product_name'] ?></td>
<td><img style="width: 200px; height:40px" src="<?php echo '../admin/'.$result['img']?>" alt=""/></td>
<td>GHC. <?php echo $result['price']?></td>
<td>
<form action="" method="post">
<input type="number" name="qty" value="<?php echo $result['qty']?>"/>
<input type="hidden" name="cartID" value="<?php echo $result['cartID']?>"/>
<input type="submit" name="submit" value="Update"/>
</form>
<?php
if (isset($cartUpdate)) {
echo $cartUpdate;
}
?>
</td>
<?php $sub_total = $result['price'] * $result['qty'];
$total = $total + $sub_total;?>
<td>GHC <?php echo $sub_total; ?></td>
<td><a onclick="return confirm('sure want to Delete');" href="?del=<?php echo $result['cartID']; ?>">Delete</a></td>
</tr>
<?php } }?>
</table>
<table style="float:right;text-align:left;" width="40%">
<tr>
<th>Grand Total :</th>
<td>GHC. <?php echo $total?> </td>
</tr>
</table>
</div>
<div class="shopping">
<div class="shopleft">
<a href="../index.php"> <img src="../images/shop.png" alt="" /></a>
</div>
<div class="shopright">
<a href="payment.php"> <img src="../images/check.png" alt="" /></a>
</div>
</div>
</div>
<div class="clear"></div>
</div>
</div>
</div>
<div class="footer">
<div class="wrapper">
<div class="section group">
<div class="col_1_of_4 span_1_of_4">
<h4>Information</h4>
<ul>
<li><a href="#">About Us</a></li>
<li><a href="#">Customer Service</a></li>
<li><a href="#"><span>Advanced Search</span></a></li>
<li><a href="#">Orders and Returns</a></li>
<li><a href="#"><span>Contact Us</span></a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>Why buy from us</h4>
<ul>
<li><a href="about.html">About Us</a></li>
<li><a href="faq.html">Customer Service</a></li>
<li><a href="#">Privacy Policy</a></li>
<li><a href="contact.html"><span>Site Map</span></a></li>
<li><a href="preview-2.html"><span>Search Terms</span></a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>My account</h4>
<ul>
<li><a href="contact.html">Sign In</a></li>
<li><a href="index.html">View Cart</a></li>
<li><a href="#">My Wishlist</a></li>
<li><a href="#">Track My Order</a></li>
<li><a href="faq.html">Help</a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>Contact</h4>
<ul>
<li><span><EMAIL></span></li>
<li><span>www.easylearningbd.com</span></li>
</ul>
<div class="social-icons">
<h4>Follow Us</h4>
<ul>
<li class="facebook"><a href="#" target="_blank"> </a></li>
<li class="twitter"><a href="#" target="_blank"> </a></li>
<li class="googleplus"><a href="#" target="_blank"> </a></li>
<li class="contact"><a href="#" target="_blank"> </a></li>
<div class="clear"></div>
</ul>
</div>
</div>
</div>
<div class="copy_right">
<p>easy Learning project & All rights Reseverd </p>
</div>
</div>
</div>
<script type="text/javascript">
$(document).ready(function() {
/*
var defaults = {
containerID: 'toTop', // fading element id
containerHoverID: 'toTopHover', // fading element hover id
scrollSpeed: 1200,
easingType: 'linear'
};
*/
$().UItoTop({ easingType: 'easeOutQuart' });
});
</script>
<a href="#" id="toTop" style="display: block;"><span id="toTopHover" style="opacity: 1;"></span></a>
</body>
</html>
<file_sep>/views/ridingSchool.php
<?php include('functions/members.php'); ?>
<!DOCTYPE html>
<html>
<head>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<meta name="description" content="">
<meta name="author" content="">
<title>African Polista</title>
<!-- Bootstrap -->
<link rel="stylesheet" href="css/bootstrap.css">
<!-- end Google Font -->
<link href='http://fonts.googleapis.com/css?family=Raleway:400,500,600,700,800,300' rel='stylesheet' type='text/css'>
<link href='http://fonts.googleapis.com/css?family=Oswald:400,500,600,700,800,300' rel='stylesheet' type='text/css'>
<script src='https://kit.fontawesome.com/a076d05399.js'></script>
<!-- owl carousel SLIDER -->
<link rel="stylesheet" href="css/owl.carousel.css">
<!-- end awesome icons -->
<link rel="stylesheet" href="css/font-awesome.css">
<!-- lightbox -->
<link href="css/prettyPhoto.css" rel="stylesheet">
<style>
#more {display: none;}
</style>
<!-- Animation Effect CSS -->
<link rel="stylesheet" href="css/animation.css">
<!-- Main Stylesheet CSS -->
<link rel="stylesheet" href="style.css">
<!-- HTML5 shim and Respond.js IE8 support of HTML5 elements and media queries -->
<!--[if lt IE 9]>
<script src="js/html5shiv.js"></script>
<script src="js/respond.min.js"></script>
<![endif]-->
<!-- SLIDER REVOLUTION 4.x CSS SETTINGS -->
<link rel="stylesheet" type="text/css" href="rs-plugin/css/settings.css" media="screen" />
</head>
<body data-spy="scroll" data-offset="25">
<div class="animationload">
<div class="loader">Loading...</div>
</div>
<!-- End Preloader -->
<!--/HEADER SECTION -->
<header class="header" style="background: black">
<div class="container">
<div class="navbar navbar-default" role="navigation">
<div class="container-fluid">
<div class="navbar-header">
<button type="button" class="navbar-toggle" data-toggle="collapse" data-target=".navbar-collapse">
<span class="sr-only">Toggle navigation</span>
<span class="icon-bar"></span>
<span class="icon-bar"></span>
<span class="icon-bar"></span>
</button>
<a href="index.php" class="navbar-brand">African <br> <span class="slogo">Polistas <span></a>
</div>
<!-- end navbar-header -->
<div class="navbar-collapse collapse">
<ul class="nav navbar-nav navbar-left">
<li><a data-scroll href="membership.php" class="int-collapse-menu">Membership</a></li>
<li><a data-scroll href="shop" class="int-collapse-menu" target="_blank">Visit Our Shop</a></li>
</ul>
</div>
<!--/.nav-collapse -->
</div>
<!--/.container-fluid -->
</div>
</div>
<!-- end container -->
</header>
<!-- end header -->
<section id="contact" class="contact-wrapper">
<div class="title text-center">
<h2>.</h2>
<h2>Membership Registration</h2>
<p><NAME> MORB</p>
<hr>
</div>
<!-- end title -->
<!-- end container -->
</section>
<!--PRICING SECTION -->
<section id="pricing" class="dark-wrapper">
<div class="container">
<div class="title text-center">
<h2>Pricing Structure</h2>
</div>
<!-- end title -->
<div class="row text-center">
<div class="col-lg-3 col-md-3 col-sm-6 col-xs-12" data-effect="helix">
<div class="pricing-box">
<span class="hideme"><i class="fa fa-star bigstar"></i></span>
<div class="title">
<h3>Standard</h3>
</div>
<div class="price">
<p class="price-value"><sub>$</sub> 99</p>
<p class="price-month">Per month</p>
</div>
<ul class="pricing clearfix">
<li>10 Pages Website</li>
<li>1 Domain</li>
<li>2 Sub Domains</li>
<li>3 MySQL DBs</li>
<li>2 Emails</li>
</ul>
<a class="jtbtn" href="#">order now</a>
</div>
<!-- Pricing Box -->
</div>
<!-- Column 1 -->
<div class="col-lg-3 col-md-3 col-sm-6 col-xs-12" data-effect="helix">
<div class="pricing-box">
<span class="hideme"><i class="fa fa-star bigstar"></i></span>
<div class="title">
<h3>Premium</h3>
</div>
<div class="price">
<p class="price-value"><sub>$</sub>149</p>
<p class="price-month">Per month</p>
</div>
<ul class="pricing clearfix">
<li>150 Mb Storage</li>
<li>1 Domain</li>
<li>2 Sub Domains</li>
<li>3 MySQL DBs</li>
<li>2 Emails</li>
</ul>
<a class="jtbtn" href="#">order now</a>
</div>
<!-- Pricing Box -->
</div>
<!-- Column 2 -->
<div class="col-lg-3 col-md-3 col-sm-6 col-xs-12" data-effect="helix">
<div class="pricing-box">
<span class="hideme"><i class="fa fa-star bigstar"></i></span>
<div class="title">
<h3>delux</h3>
</div>
<div class="price">
<p class="price-value"><sub>$</sub>199</p>
<p class="price-month">Per month</p>
</div>
<ul class="pricing clearfix">
<li>150 Mb Storage</li>
<li>1 Domain</li>
<li>2 Sub Domains</li>
<li>3 MySQL DBs</li>
<li>2 Emails</li>
</ul>
<a class="jtbtn" href="#">order now</a>
</div>
<!-- Pricing Box -->
</div>
<!-- Column 3 -->
<div class="col-lg-3 col-md-3 col-sm-6 col-xs-12" data-effect="helix">
<div class="pricing-box">
<span class="hideme"><i class="fa fa-star bigstar"></i></span>
<div class="title">
<h3>corporate</h3>
</div>
<div class="price">
<p class="price-value"><sub>$</sub>299</p>
<p class="price-month">Per month</p>
</div>
<ul class="pricing clearfix">
<li>150 Mb Storage</li>
<li>1 Domain</li>
<li>2 Sub Domains</li>
<li>3 MySQL DBs</li>
<li>2 Emails</li>
</ul>
<a class="jtbtn" href="#">order now</a>
</div>
<!-- Pricing Box -->
</div>
<!-- Column 4 -->
</div>
<!-- end row -->
</div>
<!-- end container -->
</section>
<!-- End Pricing -->
<section id="footer" class="footer-wrapper text-center">
<div class="container">
<div class="title text-center" data-scroll-reveal="enter from the bottom after 0.5s">
<div class="aligncenter">
<a href="index.html" class="navbar-brand">ATLAS <br> <span class="slogo">CREATIVE <span></a>
<div class="socialFooter">
<a href="#"><i class="fa fa-facebook"></i></a>
<a href="#"><i class="fa fa-twitter"></i></a>
<a href="#"><i class="fa fa-linkedin"></i></a>
<a href="#"><i class="fa fa-flickr"></i></a>
<a href="#"><i class="fa fa-pinterest"></i></a>
<a href="#"><i class="fa fa-youtube"></i></a>
</div>
<p>Designed by © 2015 Polistas</p>
<a data-scroll-reveal="enter from the bottom after 0.3s" href="#home"><i class="fa fa-angle-up"></i></a>
</div>
</div>
</section>
<!--/ Footer End -->
<!-- SECTION CLOSED -->
<script src="http://maps.google.com/maps/api/js?sensor=false"></script>
<script src="js/jquery.js"></script>
<script src="js/bootstrap.js"></script>
<script src="js/smooth-scroll.js"></script>
<script src="js/jquery.parallax-1.1.3.js"></script>
<script src="js/jquery.easypiechart.min.js"></script>
<script src="js/owl.carousel.js"></script>
<script src="js/jquery.jigowatt.js"></script>
<script src="js/custom.js"></script>
<script src="js/jquery.unveilEffects.js"></script>
<script src="js/jquery.isotope.min.js"></script>
<script>
(function($) {
var $container = $('.masonry_wrapper'),
colWidth = function() {
var w = $container.width(),
columnNum = 1,
columnWidth = 0;
if (w > 1200) {
columnNum = 3;
} else if (w > 900) {
columnNum = 3;
} else if (w > 600) {
columnNum = 2;
} else if (w > 300) {
columnNum = 1;
}
columnWidth = Math.floor(w / columnNum);
$container.find('.item').each(function() {
var $item = $(this),
multiplier_w = $item.attr('class').match(/item-w(\d)/),
multiplier_h = $item.attr('class').match(/item-h(\d)/),
width = multiplier_w ? columnWidth * multiplier_w[1] - 4 : columnWidth - 4,
height = multiplier_h ? columnWidth * multiplier_h[1] * 0.5 - 4 : columnWidth * 0.5 - 4;
$item.css({
width: width,
height: height
});
});
return columnWidth;
}
function refreshWaypoints() {
setTimeout(function() {}, 1000);
}
$('nav.portfolio-filter ul li a').on('click', function() {
var selector = $(this).attr('data-filter');
$container.isotope({
filter: selector
}, refreshWaypoints());
$('nav.portfolio-filter ul li a').removeClass('active');
$(this).addClass('active');
return false;
});
function setPortfolio() {
setColumns();
$container.isotope('reLayout');
}
isotope = function() {
$container.isotope({
resizable: true,
itemSelector: '.item',
masonry: {
columnWidth: colWidth(),
gutterWidth: 0
}
});
};
isotope();
$(window).smartresize(isotope);
}(jQuery));
</script>
<!-- SLIDER REVOLUTION 4.x SCRIPTS -->
<script type="text/javascript" src="rs-plugin/js/jquery.themepunch.plugins.min.js"></script>
<script type="text/javascript" src="rs-plugin/js/jquery.themepunch.revolution.min.js"></script>
<script type="text/javascript">
var revapi;
jQuery(document).ready(function() {
revapi = jQuery('.tp-banner').revolution({
delay: 9000,
startwidth: 1170,
startheight: 500,
hideThumbs: 10,
fullWidth: "off",
fullScreen: "on",
fullScreenOffsetContainer: ""
});
}); //ready
</script>
<!-- Animation Scripts-->
<script src="js/scrollReveal.js"></script>
<script>
(function($) {
"use strict"
window.scrollReveal = new scrollReveal();
})(jQuery);
</script>
<!-- Portofolio Pretty photo JS -->
<script src="js/jquery.prettyPhoto.js"></script>
<script type="text/javascript">
(function($) {
"use strict";
jQuery('a[data-gal]').each(function() {
jQuery(this).attr('rel', jQuery(this).data('gal'));
});
jQuery("a[data-gal^='prettyPhoto']").prettyPhoto({
animationSpeed: 'slow',
slideshow: false,
overlay_gallery: false,
theme: 'light_square',
social_tools: false,
deeplinking: false
});
})(jQuery);
</script>
<!-- Video Player o-->
<script src="js/jquery.mb.YTPlayer.js"></script>
<script type="text/javascript">
(function($) {
"use strict"
$(".player").mb_YTPlayer();
})(jQuery);
</script>
<script>
function myFunction() {
var dots = document.getElementById("dots");
var moreText = document.getElementById("more");
var btnText = document.getElementById("myBtn");
if (dots.style.display === "none") {
dots.style.display = "inline";
btnText.innerHTML = "Read more";
moreText.style.display = "none";
} else {
dots.style.display = "none";
btnText.innerHTML = "Read less";
moreText.style.display = "inline";
}
}
</script>
</body>
</html>
<file_sep>/chat/functions/process_msg.php
<?php
$con = mysqli_connect("localhost","root","","db_polista");
$email1 = $_SESSION['user_email'];
$user_name = $_POST['user_name'];
$username = $_POST['username'];
$msg = htmlentities($_POST['msg_content']);
if($msg == ""){
echo"
<div class='alert alert-danger'>
<strong><center>Message was unable to send!</center></strong>
</div>
";
}else if(strlen($msg) > 100){
echo"
<div class='alert alert-danger'>
<strong><center>Message is Too long! Use only 100 characters</center></strong>
</div>
";
}
else{
$insert = "insert into chat_msg(sender_name,receiver_name,msg_content,msg_status,msg_date)
values ('$user_name','$username','$msg','unread',NOW())";
$run_insert = mysqli_query($con,$insert);
}
?><file_sep>/chat/js/main.js
$(document).ready(function() {
$(".btn1 button").on("click", function() {
var msg = $("#msg").val();
var user1 = $("#user1").val();
var user2 = $("#user2").val();
var succ = $("#success").val();
$.ajax({
url: '../functions/process_msg.php',
type: 'post',
data: {
msg_content: msg,
username: user1,
user_name: user2
},
success: function() {
window.location.href = succ;
}
})
});
});
function getContent() {
return new Promise(function(resolve, reject) {
var url = 'home.php';
$.ajax({
url: url,
success: function(data) {
resolve(data);
},
error: function(err) {
reject(err);
}
});
});
}<file_sep>/shop/inc/slider.php
<div class="header_bottom">
<div class="header_bottom_left">
<div class="section group">
<div class="rightsidebar1 span_3_of_1">
<h1>CATEGORIES</h1>
<ul>
<?php
$catdisplay = $category1->catDisplay();
if ($catdisplay) {
while ($result = $catdisplay->fetch_assoc()) {
?>
<li><a href="pages/productbycat.php?catID=<?php echo $result['catID']; ?>"><?php echo $result['catName']; ?></a></li>
<?php } } ?>
</ul>
</div>
</div>
<div class="clear"></div>
</div>
<div class="header_bottom_right_images">
<!-- FlexSlider -->
<section class="slider">
<div class="flexslider">
<ul class="slides">
<?php
$newProducts = $product->displayNewProducts();
if ($newProducts) {
while ($result = $newProducts->fetch_assoc()) {
?>
<li>
<a href="pages/preview.php?proid=<?php echo $result['productID']; ?>">
<img style="width: 600px; height:200px" src="admin/<?php echo $result['img']; ?>" alt="" /></a>
</li>
<?php } } ?>
</ul>
</div>
</section>
<!-- FlexSlider -->
</div>
<div class="clear"></div>
</div><file_sep>/shop/lib/session.php
<?php
/**
*session class
*/
class Session{
public static function init(){
session_start();
}
/**
* set session variables
*
* @param [session key] $key
* @param [session value] $val
* @return void
*/
public static function set($key, $val){
$_SESSION[$key] = $val;
}
/**
* get session value by applying session key
*
* @param [session key] $key
* @return void
*/
public static function get($key){
if(isset($_SESSION[$key])){
return $_SESSION[$key];
}
else{
return false;
}
}
/**
* check if session is false and return to login page
*
* @return void
*/
public static function checkSession(){
self::init();
if(self::get("adminlogin") == false){
self::destroy();
header("Location:login.php");
}
}
/**
* destroy session
*
* @return void
*/
public static function destroy(){
session_destroy();
header("Location:login.php");
}
public static function destroy1(){
session_destroy();
header("Location:pages/login.php");
}
/**
* check if login is true
*
* @return void
*/
public static function checklogin(){
self::init();
if(self::get("adminlogin") == true){
header("Location:dashboard.php");
}
}
}
?><file_sep>/shop/pages/login.php
<?php include('../inc/header.php'); ?>
<?php
$login = Session::get("userlogin");
if ($login == true) {
header("Location:payment.php");
}
?>
<?php
if ($_SERVER['REQUEST_METHOD'] == 'POST' && isset($_POST['reg']) ) {
$customer1 = $customer->userRegistration($_POST);
}
?>
<?php
if ($_SERVER['REQUEST_METHOD'] == 'POST' && isset($_POST['login']) ) {
$Login = $customer->userLogin($_POST);
}
?>
<div class="main">
<div class="content">
<div class="login_panel">
<h3>Existing Customers</h3>
<p>Sign in with the form below.</p>
<?php
if (isset($Login)) {
echo $Login;
}
?>
<form method="post" id="member">
<input name="email" type="email" placeholder="email" class="field" style="font-size: 12px;
color:B3B1B1;
padding: 8px;
outline: none;
margin: 5px 0;
width: 230px">
<input name="pass" type="<PASSWORD>" placeholder="<PASSWORD>" class="field" >
<div class="buttons"><div><button class="grey" name="login" >Sign In</button></div></div>
</form>
<p class="note">If you forgot your passoword just enter your email and click <a href="#">here</a></p>
</div>
<div class="register_account">
<h3>Register New Account</h3>
<?php
if (isset($customer1)) {
echo $customer1;
}
?>
<form method="post">
<table>
<tbody>
<tr>
<td>
<div>
<input type="text" name = "fname" placeholder="First Name">
</div>
<div>
<input type="text" name="lname" placeholder="Last Name">
</div>
<div>
<input type="text" name="city" placeholder="City">
</div>
<div>
<input type="text" name = "zip" placeholder="Zip">
</div>
<div>
<input type="email" name = "email" placeholder="email"
style="font-size: 12px;
color:B3B1B1;
padding: 8px;
outline: none;
margin: 5px 0;
width: 340px">
</div>
</td>
<td>
<div>
<input type="text" name="addr" placeholder="Address">
</div>
<div>
<input type="text" name="country" placeholder="Country">
<div>
<input type="text" name="phone" placeholder="Phone Number">
</div>
<div>
<input type="<PASSWORD>" name="pass" placeholder="<PASSWORD>" style="font-size: 12px;
color:B3B1B1;
padding: 8px;
outline: none;
margin: 5px 0;
width: 340px" >
</div>
</td>
</tr>
</tbody></table>
<div class="search"><div><button class="grey" type="submit" name="reg">Create Account</button></div></div>
<p class="terms">By clicking 'Create Account' you agree to the <a href="#">Terms & Conditions</a>.</p>
<div class="clear"></div>
</form>
</div>
<div class="clear"></div>
</div>
</div>
</div>
<div class="footer">
<div class="wrapper">
<div class="section group">
<div class="col_1_of_4 span_1_of_4">
<h4>Information</h4>
<ul>
<li><a href="#">About Us</a></li>
<li><a href="#">Customer Service</a></li>
<li><a href="#"><span>Advanced Search</span></a></li>
<li><a href="#">Orders and Returns</a></li>
<li><a href="#"><span>Contact Us</span></a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>Why buy from us</h4>
<ul>
<li><a href="about.html">About Us</a></li>
<li><a href="faq.html">Customer Service</a></li>
<li><a href="#">Privacy Policy</a></li>
<li><a href="contact.html"><span>Site Map</span></a></li>
<li><a href="preview-2.html"><span>Search Terms</span></a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>My account</h4>
<ul>
<li><a href="contact.html">Sign In</a></li>
<li><a href="index.html">View Cart</a></li>
<li><a href="#">My Wishlist</a></li>
<li><a href="#">Track My Order</a></li>
<li><a href="faq.html">Help</a></li>
</ul>
</div>
<div class="col_1_of_4 span_1_of_4">
<h4>Contact</h4>
<ul>
<li><span><EMAIL></span></li>
<li><span>www.easylearningbd.com</span></li>
</ul>
<div class="social-icons">
<h4>Follow Us</h4>
<ul>
<li class="facebook"><a href="#" target="_blank"> </a></li>
<li class="twitter"><a href="#" target="_blank"> </a></li>
<li class="googleplus"><a href="#" target="_blank"> </a></li>
<li class="contact"><a href="#" target="_blank"> </a></li>
<div class="clear"></div>
</ul>
</div>
</div>
</div>
<div class="copy_right">
<p>easy Learning project & All rights Reseverd </p>
</div>
</div>
</div>
<script type="text/javascript">
$(document).ready(function() {
/*
var defaults = {
containerID: 'toTop', // fading element id
containerHoverID: 'toTopHover', // fading element hover id
scrollSpeed: 1200,
easingType: 'linear'
};
*/
$().UItoTop({ easingType: 'easeOutQuart' });
});
</script>
<a href="#" id="toTop" style="display: block;"><span id="toTopHover" style="opacity: 1;"></span></a>
</body>
</html>
<file_sep>/shop/pages/profile.php
<?php include '../inc/header.php'; ?>
<style>
.tblone{width: 550px; margin: 0 auto; border: 2px solid #ddd; }
.tblone tr td{text-align: justify;}
</style>
<div class="main">
<div class="content">
<div class="section group">
<?php
$user_id = Session::get('userId');
$getdata = $customer->retrieveCustomerDetails($user_id);
if ($getdata) {
while ($result = $getdata->fetch_assoc()) {
?>
<table class="tblone">
<tr>
<td colspan="3"> <h2> Your Profile Details </h2> </td>
</tr>
<tr>
<td width="20%"> First Name </td>
<td width="5%"> : </td>
<td> <?php echo $result['fname']; ?> </td>
</tr>
<tr>
<td width="20%"> Last Name </td>
<td width="5%"> : </td>
<td> <?php echo $result['lname']; ?> </td>
</tr>
<tr>
<td> Phone </td>
<td> : </td>
<td> <?php echo $result['phone']; ?> </td>
</tr>
<tr>
<td> Email </td>
<td> : </td>
<td> <?php echo $result['email']; ?> </td>
</tr>
<tr>
<td> Address </td>
<td> : </td>
<td> <?php echo $result['addr']; ?> </td>
</tr>
<tr>
<td> City </td>
<td> : </td>
<td><?php echo $result['city']; ?> </td>
</tr>
</tr>
<tr>
<td> Zipcode </td>
<td> : </td>
<td> <?php echo $result['zip']; ?> </td>
</tr>
<tr>
<td> Country </td>
<td> : </td>
<td> <?php echo $result['country']; ?> </td>
</tr>
<tr> <td> </td>
<td> </td>
<td><a href="editprofile.php"> Update Details </a> </td>
</tr>
</table>
<?php } } ?>
</div>
</div>
</div>
<?php include '../inc/footer.php'; ?><file_sep>/shop/pages/order.php
<?php include '../inc/header.php'; ?>
<?php
$login = Session::get("userlogin");
if ($login == false) {
header("Location:login.php");
}
?>
<div class="main">
<div class="content">
<div class="section group">
<h2> <span>Your Order Details</span> </h2>
<table class="tblone">
<tr>
<th>Product Name</th>
<th>Image</th>
<th>Quantity</th>
<th>Total Price</th>
<th>Date Ordered</th>
<th>Status</th>
<th>Action</th>
</tr>
<?php
$user_Id = Session::get("userId");
$getCustomerOrder = $cart->customer_order_details($user_Id);
if ($getCustomerOrder) {
while ($result = $getCustomerOrder->fetch_assoc()) {
?>
<tr>
<td><?php echo $result['product_name']; ?></td>
<td><img style="width: 100px; height:40px" src="../admin/<?php echo $result['img']; ?>" alt=""/></td>
<td> <?php echo $result['qty']; ?></td>
<td>GHC
<?php
$total = $result['price'] * $result['qty'];
echo $total;
?>
</td>
<td><?php echo $result['time']; ?></td>
<td>
<?php
if ($result['status'] == '0') {
echo "Pending";
}else {
echo "Shipped";
}
?>
</td>
<?php
if ($result['status'] == '1') { ?>
<td><a onclick="return confirm('Sure want to Delete?');" href=" ">X</a></td>
<?php }else { ?>
<td>N/A </td>
<?php } ?>
</tr>
<?php } } ?>
</table>
</div>
<div class="clear"></div>
</div>
</div>
</div>
<?php include '../inc/footer.php'; ?><file_sep>/shop/admin/views/user_profile.php
<?php require (dirname(__FILE__).'/../inc/header.php');?>
<?php require (dirname(__FILE__).'/../inc/sidebar.php');?>
<?php require (dirname(__FILE__).'/../../classes/membership.php');?>
<?php
$members = new Members();
if(isset($_GET['uid'])){
$email = $_GET['uid'];
$namel = Session::get("namee");
$delbrand = $members->passReset($email,$namel);
}
?>
<?php
if(isset($_GET['deluser'])){
$cdelete = $_GET['deluser'];
$delmember = $members->deletbyID($cdelete);
}
?>
<div class="grid_10">
<div class="box round first grid">
<h2>User Profile</h2>
<?php
if(isset($delmember)){
echo $delmember;
}
?>
<?php
if(isset($delbrand)){
echo $delbrand;
}
?>
<div class="block">
<table class="data display datatable" id="example">
<thead>
<tr>
<th>ID</th>
<th>First Name</th>
<th>Last Name</th>
<th>Phone Number</th>
<th>Email</th>
<th>Country</th>
<th>Status</th>
<th>Login</th>
<th>Action</th>
</tr>
</thead>
<tbody>
<?php
$getmembers = $members->membersDisplay();
if($getmembers){
while($result = $getmembers->fetch_assoc()){
?>
<tr class="gradeU">
<td><?php echo $result['ID'];?></td>
<td><?php echo $result['first_name'] ?></td>
<td><?php echo $result['last_name'];?></td>
<td><?php echo $result['phone'];?></td>
<td><?php echo $result['email'];?></td>
<td><?php echo $result['country'];?></td>
<td><?php echo $result['approval'];?></td>
<td><?php echo $result['login'];?></td>
<td><a href="?uid=<?php echo $result['email']; ?>">Password Set</a>
|| <a onclick="return confirm('Are you sure to delete')"
href="?deluser=<?php echo $result['ID']; ?>">Remove</a></td>
</tr>
<?php }}?>
</tbody>
</table>
</div>
</div>
</div>
<script type="text/javascript">
$(document).ready(function () {
setupLeftMenu();
$('.datatable').dataTable();
setSidebarHeight();
});
</script>
<?php include '../inc/footer.php';?>
<file_sep>/shop/classes/customers.php
<?php
include_once (dirname(__FILE__).'../../lib/database.php');
include_once (dirname(__FILE__).'../../helper/format.php');
?>
<?php
class Customers{
private $db;
private $fm;
public function __construct()
{
$this->db = new Database();
$this->fm = new Format();
}
public function userRegistration($data){
$fname = mysqli_real_escape_string($this->db->link, $data['fname'] );
$lname = mysqli_real_escape_string($this->db->link, $data['lname'] );
$address = mysqli_real_escape_string($this->db->link, $data['addr'] );
$city = mysqli_real_escape_string($this->db->link, $data['city'] );
$country = mysqli_real_escape_string($this->db->link, $data['country'] );
$zip = mysqli_real_escape_string($this->db->link, $data['zip'] );
$phone = mysqli_real_escape_string($this->db->link, $data['phone'] );
$email = mysqli_real_escape_string($this->db->link, $data['email'] );
$pass = mysqli_real_escape_string($this->db->link, md5($data['pass']));
if ($fname == "" || $lname =="" || $address == "" || $city == "" || $country == "" || $zip == "" || $phone == "" || $email == "" || $pass == "" ) {
$msg = "<span style='color: red; font-size: 18px;'>Field must not be empty!</span>";
return $msg;
}
$check_mail = "SELECT * FROM shop_users WHERE email='$email' LIMIT 1";
$mailchk = $this->db->select($check_mail);
if ($mailchk != false) {
$msg = "<span style='color: red; font-size: 18px;'>Mail already registered!</span>";
return $msg;
}else {
$query = "INSERT INTO shop_users(fname,lname,city, zip, email,addr, country, phone, pass)
VALUES('$fname','$lname','$city','$zip','$email','$address','$country','$phone','$pass')";
$insert = $this->db->insert($query);
if ($insert) {
$msg = "<span style='color: Green; font-size: 18px;'>Account Created Successfully.</span> ";
return $msg;
}else {
$msg = "<span style='color: red; font-size: 18px;'>Account Not Created</span> ";
return $msg;
}
}
}
public function userLogin($data){
$email = mysqli_real_escape_string($this->db->link, $data['email'] );
$pass = mysqli_real_escape_string($this->db->link, md5($data['pass']));
if ($email == "" || $pass == "" ) {
$msg = "<span style='color: red; font-size: 18px;'>Field Must Not be empty .</span> ";
return $msg;
}
$query = "SELECT * FROM shop_users WHERE email='$email' AND pass='$pass' ";
$result = $this->db->select($query);
if ($result != false) {
$value = $result->fetch_assoc();
Session::set("userlogin", true);
Session::set("userId", $value['userID']);
Session::set("userName", $value['Fname']);
header("Location:payment.php");
}else {
$msg = "<span style='color: red; font-size: 18px;'>Email Or Password Not Matched</span> ";
return $msg;
}
}
public function retrieveCustomerDetails($id){
$query = "SELECT * FROM shop_users WHERE userID ='$id' ";
$result = $this->db->select($query);
return $result;
}
public function customerDetailsUpdate($data, $user_id){
$fname = mysqli_real_escape_string($this->db->link, $data['fname'] );
$lname = mysqli_real_escape_string($this->db->link, $data['lname'] );
$address = mysqli_real_escape_string($this->db->link, $data['address'] );
$city = mysqli_real_escape_string($this->db->link, $data['city'] );
$country = mysqli_real_escape_string($this->db->link, $data['country'] );
$zip = mysqli_real_escape_string($this->db->link, $data['zip'] );
$phone = mysqli_real_escape_string($this->db->link, $data['phone'] );
$email = mysqli_real_escape_string($this->db->link, $data['email'] );
if ($fname == "" || $lname == "" || $address == "" || $city == "" || $country == "" || $zip == "" || $phone == "" || $email == "" ) {
$msg = "<span style='color: red; font-size: 18px;'>Field Must Not be empty .</span> ";
return $msg;
} else {
$query = "UPDATE shop_users
SET
fname = '$fname',
lname = '$lname',
addr = '$address',
city = '$city',
country = '$country',
zip = '$zip',
phone = '$phone',
email = '$email'
WHERE userID = '$user_id' ";
$update_row = $this->db->update($query);
if ($update_row) {
$msg = "<span style='color: green; font-size: 18px;'>Customer Data Updated Successfully.</span> ";
return $msg;
}else {
$msg = "<span style='color: red; font-size: 18px;'>Customer Data Not Updated .</span> ";
return $msg;
}
}
}
}
?><file_sep>/chat/functions/pass_forgot_reset.php
<?php
session_start();
$errors = [];
$user_id = "";
// connect to database
$db = mysqli_connect('localhost', 'root', '', 'db_polista');
if (isset($_GET['token'])) {
$_SESSION['token']=mysqli_real_escape_string($db,$_GET['token']);
}
if (isset($_POST['reset-password'])) {
$email = $_POST['email'];
// ensure that the user exists on our system
$query = "SELECT email, approval FROM chat_users WHERE email='$email' and approval ='approved'";
$results = mysqli_query($db, $query);
if (empty($email)) {
array_push($errors, "Your email is required");
}else if(mysqli_num_rows($results) <= 0) {
array_push($errors, "Sorry, no user exists on our system with that email");
}
// generate a unique random token of length 100
$token = bin2hex(random_bytes(50));
if (count($errors) == 0) {
// store token in the password-reset database table against the user's email
$sql = "INSERT INTO pass_reset(email, token) VALUES ('$email', '$token')";
$results = mysqli_query($db, $sql);
// Send email to user with the token in a link they can click on
require 'PHPMailerAutoload.php';
$mail = new PHPMailer;
//$mail->SMTPDebug = 4; // Enable verbose debug output
$mail->isSMTP(); // Set mailer to use SMTP
$mail->Host = 'smtp.gmail.com'; // Specify main and backup SMTP servers
$mail->SMTPAuth = true; // Enable SMTP authentication
$mail->Username = '<EMAIL>'; // SMTP username
$mail->Password = '<PASSWORD>'; // SMTP password
$mail->SMTPSecure = 'tls'; // Enable TLS encryption, `ssl` also accepted
$mail->Port = 587; // TCP port to connect to
$mail->setFrom('<EMAIL>', 'African Polistas');
$mail->addAddress($email); // Add a recipient
// $mail->addReplyTo('<EMAIL>', 'Information');
// $mail->addCC('<EMAIL>');
// $mail->addBCC('<EMAIL>');
//$mail->addAttachment('/var/tmp/file.tar.gz'); // Add attachments
//$mail->addAttachment('/tmp/image.jpg', 'new.jpg'); // Optional name
$mail->isHTML(true); // Set email format to HTML
$mail->Subject = 'Password Reset';
$mail->Body = "Hi there, click on this <a href=\"localhost/chat/pages/new_pass.php?token=" . $token . "\">link</a> to reset your password on our site";
$mail->AltBody = "Hi there, click on this <a href=\"localhost/chat/pages/new_pass.php=" . $token . "\">link</a> to reset your password on our site";
if(!$mail->send()) {
echo 'Message could not be sent.';
echo 'Mailer Error: ' . $mail->ErrorInfo;
} else {
//echo 'Message has been sent';
}
header('location: pending.php?email=' . $email);
}
}
// ENTER A NEW PASSWORD
if (isset($_POST['new_password'])) {
$new_pass = $_POST['new_pass'];
$new_pass_c = $_POST['new_pass_c'];
// Grab to token that came from the email link
$token = $_SESSION['token'];
if (empty($new_pass) || empty($new_pass_c)) array_push($errors, "Password is required");
if ($new_pass !== $new_pass_c) array_push($errors, "Password do not match");
if (count($errors) == 0) {
// select email address of user from the password_reset table
$sql = "SELECT email FROM pass_reset WHERE token='$token' LIMIT 1";
$results = mysqli_query($db, $sql);
$email = mysqli_fetch_assoc($results)['email'];
if ($email) {
$new_pass = md5($new_pass);
$sql = "UPDATE chat_users SET pass='<PASSWORD>' WHERE email='$email'";
$results = mysqli_query($db, $sql);
header('location: signin.php');
}
}
}
?> | bd2670b83996362a416db41d1672fb8c8fdfaa6e | [
"JavaScript",
"PHP"
] | 35 | PHP | SadatIssah/polistas | 4802e633ddd3bc6b7d5d9cc888a2959dd2b31fe2 | 53dd9111c69b125ecb143b2f5bfbd8cf22aee8b0 |
refs/heads/main | <repo_name>ginaesps/prograDist<file_sep>/apirest2020-main/app/routes/ventas.js
//var ventaController=require('../controllers/ventaController');
var router = require('express').Router()
router.get('/search', function(req, res) {
// ventaController.search(req,res);
})
router.get('/', function(req, res) {
// ventaController.list(req,res);
})
router.get('/:id', function(req, res) {
// ventaController.find(req,res);
})
router.post('/', function(req, res) {
// ventaController.create(req,res);
})
//url:puerto/api/clientes
module.exports = router
<file_sep>/apirest2020-main/app/routes/productos.js
var productoController=require('../controllers/productoController');
var router = require('express').Router()
router.get('/search/:id', function(req, res) {
//res.json({ message: 'Vas a buscar un producto'})
productoController.search(req,res);
})
router.get('/', function(req, res) {
//res.json({ message: 'Estás conectado a la API. Recurso: clientes' })
productoController.list(req,res);
})
router.get('/:id', function(req, res) {
//res.json({ message: 'Vas a obtener la clientes con id ' + req.params.id })
productoController.find(req,res);
})
router.post('/', function(req, res) {
//res.json({ message: 'Vas a añadir un cliente' })
productoController.create(req,res);
})
router.put('/:id', function(req, res) {
//res.json({ message: 'Vas a actualizar el cliente con id ' + req.params.id })
productoController.edit(req,res);
})
//url:puerto/api/clientes
module.exports = router
<file_sep>/apirest2020-main/app/routes/index.js
var router = require('express').Router()
//var ventas = require('./ventas')
//router.use('/ventas', ventas)
var productos = require('./productos')
router.use('/productos', productos)
router.get('/', function (req, res) {
res.status(200).json({ message: 'Estás conectado a nuestra API' })
})
//localhost:1339/api
module.exports = router<file_sep>/apirest2020-main/app/models/venta.js
class venta{
constructor(fecha,total,rfc){
this.id=null;
this.fecha=fecha;
this.total=total;
this.rfc=rfc;
}
}
module.exports=venta;<file_sep>/apirest2020-main/app/models/detalle_venta.js
class detalle_venta{
constructor(id_venta, id_producto, cantidad, costo){
this.id_venta=id_venta;
this.id_producto=id_producto;
this.cantidad=cantidad;
this.costo=costo;
this.monto_venta=cantidad*costo;
}
}
module.exports=detalle_venta; | 9a676137db93cd5cad0a0d50d653f8923e1a61c6 | [
"JavaScript"
] | 5 | JavaScript | ginaesps/prograDist | fa77a92845579dd6b4476b1e03b91f189103273d | adbaaedb174327958d133d61b2caf4b7c2977b89 |
refs/heads/master | <repo_name>francklemoine/letsencrypt<file_sep>/docker-entrypoint.sh
#!/bin/bash
set -e
MAXDOMAIN=9
# set EMAIL and DOMAIN arrays
for (( i=1; i<=${MAXDOMAIN}; i++ )); do
if [[ -v EMAIL${i} && -v DOMAIN${i} ]]; then
fullmai="EMAIL${i}"
fulldom="DOMAIN${i}"
EMAIL_ARRAY[${i}]=${!fullmai//[[:space:]]/}
DOMAIN_ARRAY[${i}]=${!fulldom//[[:space:]]/}
fi
done
# one email/domain at least must be defined
if [[ -z "${EMAIL_ARRAY[*]}" || -z "${DOMAIN_ARRAY[*]}" ]]; then
echo >&2 'Notice: undefined variable(s) EMAIL1..9 or DOMAIN1..9! - skipping ...'
exit 1
fi
for (( i=1; i<=${#DOMAIN_ARRAY[@]}; i++ )); do
if [[ ! -d "/etc/letsencrypt/live/${DOMAIN_ARRAY[$i]}" ]]; then
mkdir /var/www/${DOMAIN_ARRAY[$i]}
# letsencrypt cert
if /opt/letsencrypt/letsencrypt-auto certonly \
--text \
--no-self-upgrade \
--agree-tos \
--email ${EMAIL_ARRAY[$i]} \
--rsa-key-size 4096 \
--webroot \
--webroot-path /var/www/${DOMAIN_ARRAY[$i]} \
--domain ${DOMAIN_ARRAY[$i]}
then
# Echo quickstart guide to logs
echo
echo '================================================================================='
echo "Your ${DOMAIN_ARRAY[$i]} letsencrypt container is now ready to use!"
echo '================================================================================='
echo
# configure cron
[[ -f "/etc/cron.d/${DOMAIN_ARRAY[$i]//./-}" ]] && rm -f /etc/cron.d/${DOMAIN_ARRAY[$i]//./-}
echo -e "10 ${i} * * 0 root /opt/letsencrypt/letsencrypt-auto renew --no-self-upgrade >>/var/log/letsencrypt_${DOMAIN_ARRAY[$i]}.log\n" >>/etc/cron.d/${DOMAIN_ARRAY[$i]//./-}
echo -e "40 ${i} * * 0 root /usr/local/bin/bunch_certificate.sh \"${DOMAIN_ARRAY[$i]}\"\n" >>/etc/cron.d/${DOMAIN_ARRAY[$i]//./-}
# Bunch the certs for the first time
/usr/local/bin/bunch_certificate.sh "${DOMAIN_ARRAY[$i]}"
else
echo
echo '================================================================================='
echo "Your ${DOMAIN_ARRAY[$i]} letsencrypt container can't get certificates!"
echo '================================================================================='
echo
fi
rm -fR /var/www/${DOMAIN_ARRAY[$i]}
else
# configure cron
[[ -f "/etc/cron.d/${DOMAIN_ARRAY[$i]/.//-}" ]] && rm -f /etc/cron.d/${DOMAIN_ARRAY[$i]//./-}
echo -e "10 ${i} * * 0 root /opt/letsencrypt/letsencrypt-auto renew --no-self-upgrade >>/var/log/letsencrypt_${DOMAIN_ARRAY[$i]}.log\n" >>/etc/cron.d/${DOMAIN_ARRAY[$i]//./-}
echo -e "40 ${i} * * 0 root /usr/local/bin/bunch_certificate.sh \"${DOMAIN_ARRAY[$i]}\"\n" >>/etc/cron.d/${DOMAIN_ARRAY[$i]//./-}
# Bunch the certs
/usr/local/bin/bunch_certificate.sh "${DOMAIN_ARRAY[$i]}"
fi
done
case "$@" in
bash|/bin/bash)
/bin/bash
;;
*)
/usr/sbin/cron -f -L 15
exit 0
;;
esac
<file_sep>/README.md
# letsencrypt
Docker image with letsencrypt
<file_sep>/Dockerfile
# DESCRIPTION: letsencrypt within a container
# BUILD: docker build -t flem/letsencrypt .
# RUN: docker run -d \
# -e EMAIL1=<EMAIL>
# -e DOMAIN1=www.domain.tld
# flem/letsencrypt
FROM debian:jessie
MAINTAINER <NAME> <<EMAIL>>
# properly setup debian sources
ENV DEBIAN_FRONTEND=noninteractive
RUN buildDeps=' \
git \
ca-certificates \
cron \
' \
set -x \
&& apt-get -y update \
&& apt-get -y upgrade \
&& apt-get install -y --no-install-recommends $buildDeps \
&& update-ca-certificates \
&& git config --global http.sslVerify false \
&& git clone https://github.com/letsencrypt/letsencrypt /opt/letsencrypt \
&& /opt/letsencrypt/letsencrypt-auto --os-packages-only \
&& apt-get clean autoclean \
&& rm -rf /var/lib/apt/lists/* \
&& rm -rf /tmp/*
COPY bunch_certificate.sh /usr/local/bin
COPY docker-entrypoint.sh /
RUN chmod +x /docker-entrypoint.sh \
&& chmod +x /usr/local/bin/bunch_certificate.sh
VOLUME ["/etc/letsencrypt", "/var/www"]
ENTRYPOINT ["/docker-entrypoint.sh"]
| b4b3dba81418e00d427cb9f90f7ceed67921c196 | [
"Markdown",
"Dockerfile",
"Shell"
] | 3 | Shell | francklemoine/letsencrypt | 580c1f071d40c6e83c06d23fc887d14be6930de7 | b354db57e18b3895b6667395d18f6960f3eb54b0 |
refs/heads/main | <file_sep>using System.Collections;
using System.Collections.Generic;
using UnityEngine;
public class BallControl : MonoBehaviour
{
private Rigidbody2D rigidBody2D; //deklarasi variabel bola rigidbody2d
// besar gaya awal dorongan bola
public float xInitialForce;
public float yInitialForce;
public float speed;
private Vector2 trajectoryOrigin; // Titik asal lintasan bola saat ini
void ResetBall ()
{
transform.position = Vector2.zero; // Reset posisi menjadi (0,0)
rigidBody2D.velocity = Vector2.zero; // Reset kecepatan menjadi (0,0)
}
void PushBall ()
{
// Menentukan nilai komponen y dari gaya dorong antara -yInitialForce dan yInitialForce
rigidBody2D.velocity = rigidBody2D.velocity.normalized*speed;
// Menentukan nilai acak antara 0(inklusif) dan 2 (eklusif)
float randomDirection = Random.Range(0,2);
// nilai < 1 = bola gerak ke kiri
if (randomDirection < 1.0f )
{
//gunakan gaya untuk menggerakkan bola
rigidBody2D.AddForce(new Vector2(-xInitialForce, yInitialForce));
}
else
{
rigidBody2D.AddForce(new Vector2(xInitialForce, yInitialForce));
}
}
void RestartGame()
{
//Kembalikan bola ke posisi semula
ResetBall();
// Setelah 2s, berikan gaya pada bola
Invoke("PushBall", 2);
}
// Start is called before the first frame update
void Start()
{
rigidBody2D =GetComponent<Rigidbody2D>();
RestartGame(); //Mulai game
trajectoryOrigin = transform.position;
}
// Ketika bola beranjak dari sebuah tumbukan, rekam titik tumbukan tersebut
void OnCollisionExit2D(Collision2D collision)
{
trajectoryOrigin = transform.position;
}
// Untuk mengakses informasi titik asal lintasan
public Vector2 TrajectoryOrigin
{
get { return trajectoryOrigin;}
}
// Update is called once per frame
void FixedUpdate()
{
rigidBody2D.velocity = Vector2.ClampMagnitude(rigidBody2D.velocity, speed);
}
}
| 27147bbf7166e8d918398c9c0ed532cc4e847035 | [
"C#"
] | 1 | C# | aidilafandi/Pong | 7122f89f90e5ab6ebc526610c360cefb9f28a4ee | 8d2ef6fcb6525ea276d3d5c66b6e4b8788b02028 |
refs/heads/main | <repo_name>Elliacoj/Exo-50-JS-Les-bases-variables<file_sep>/script4.js
let Var1 = prompt("Votre nom:");
let Var2 = prompt("Votre prénom:");
let Var3 = prompt("Votre ville:");
alert ("Votre nom: " + Var1 +"\n" + "Votre prénom: " + Var2 +"\n" + "Votre ville: " + Var3);<file_sep>/exo 2/script2.js
let Var1;
let Var2;
let Var3;
Var1 = "Nom: Doe";
Var2 = "Prénom: John";
Var3 = "Ville: New-York";
alert (Var1 +"\n" + Var2 +"\n" + Var3);
| 7491c9c1c1974b983cf7746eb76ffead083d3685 | [
"JavaScript"
] | 2 | JavaScript | Elliacoj/Exo-50-JS-Les-bases-variables | a4c3b05373a4afe66ad5ae9b4b4d586ab1abbab5 | ef511f688e3853992f56c4313073c58f73c4de0b |
refs/heads/master | <file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
$customerId=$_GET['customer'];
$sql = "SELECT `name`, `cnic`, `id`, `date`, `image` FROM `person` WHERE id=".$customerId."";
$person=queryReceive($sql);
$sql = "SELECT a.id, a.address_city, a.address_town, a.address_street_no, a.address_house_no, a.person_id FROM address as a inner JOIN person p ON a.person_id=p.id
WHERE a.person_id=$customerId
ORDER by a.person_id;";
$address=queryReceive($sql);
$sql="SELECT n.number, n.id, n.is_number_active, n.person_id FROM number as n inner JOIN person as p ON p.id=n.person_id
WHERE p.id=$customerId
order BY n.id";
$numbers=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container " style="margin-top:150px" >
<h3 align="center">
Customer Preview
</h3>
<form id="changeImage">
<?php
echo '<input name="customerid" hidden value="'.$_GET["customer"].'">';
?>
<input name="image" hidden value="<?php echo $person[0][4] ?>">
<div class=" form-group row">
<img src="<?php echo $person[0][4];?> " style="height: 20vh" class="img-thumbnail figure-img" alt="image is not set">
</div>
<div class="form-group row">
<label class="form-check-label col-3">image:</label>
<input name="image" id="submitImage" type="file" class="form-control float-right btn-warning col-9">
</div>
</form>
<form id="form" >
<?php
echo '<input id="customerId" type="number" hidden value="'.$_GET["customer"].'">';
?>
<div class="col-12" id="number_records">
<?php
for($i=0;$i<count($numbers);$i++)
{
echo '
<div class="form-group row" id="Each_number_row_'.$numbers[$i][1].'">
<label class="col-3 col-form-label" for="number_'.$numbers[$i][1].'">Phone no:</label>
<input class=" numberchange allnumber form-control col-7" type="text" name="number[]" value="'.$numbers[$i][0].'" id="number_'.$numbers[$i][1].'" data-columne="number" data-columneid='.$numbers[$i][1].'>
<input class="form-control btn btn-danger col-2 remove_number " id="remove_numbers_'.$numbers[$i][1].'" data-removenumber="'.$numbers[$i][1].'" value="-">
</div>';
}
?>
</div>
<div class="form-group row" >
<label for="newNumber" class="col-form-label col-3">New Number</label>
<input id="newNumber" name="newNumber"class="form-control col-7" >
<input type="button" value="+" class="col-2 btn-success form-control" id="newadd">
</div>
<div class="form-group row">
<label for="name" class="col-form-label col-3"> Name:</label>
<?php
echo'<input type="text" id="name" name="name" class=" personchange form-control col-9" value="'.$person[0][0].'" data-columne="name">';
?>
</div>
<div class="form-group row">
<label for="cnic" class="col-form-label col-3"> CNIC:</label>
<?php
echo '
<input type="number" id="cnic" name="cnic" class=" personchange form-control col-9" value="'.$person[0][1].'" data-columne="cnic">';
?>
</div>
<h3 align="center"> Address</h3>
<div class="form-group row">
<label for="city" class="col-form-label col-3"> City:</label>
<?php
echo '<input type="text" id="city" name="city" class=" addresschange form-control col-9" value="'.$address[0][1].'" data-columne="address_city">';
?>
</div>
<div class="form-group row">
<label for="area" class="col-form-label col-3"> Area/ Block:</label>
<?php
echo '<input type="text" id="area" name="area" class=" addresschange form-control col-9" value="'.$address[0][2].'" data-columne="address_town">';
?>
</div>
<div class="form-group row">
<label for="streetNo" class="col-form-label col-3">Street No :</label>
<?php
echo ' <input type="number" id="streetNo" name="streetNo" class=" addresschange form-control col-9" value="'.$address[0][3].'" data-columne="address_street_no">';
?>
</div>
<div class="form-group row">
<label for="houseNo" class="col-form-label col-3">House No:</label>
<?php
echo '<input type="number" id="houseNo" name="houseNo" class=" addresschange form-control col-9" value="'.$address[0][4].'" data-columne="address_house_no">';
?>
</div>
<div class="col-12 shadow">
<h4 align="center">Customer personality</h4>
<?php
$sql='SELECT py.personality,py.rating FROM person as p INNER join orderTable as ot
on p.id=ot.person_id
INNER JOIN payment as py
on ot.id=py.orderTable_id
WHERE
p.id='.$customerId.'';
$personalitydetails=queryReceive($sql);
for ($k=0;$k<count($personalitydetails);$k++)
{
echo '
<p class=" mb-3 form-control">'.$personalitydetails[$k][0].' <span class="float-right border-danger border font-weight-bold">Rating: '.$personalitydetails[$k][1].' </span> </p>';
}
?>
</div>
<div class="form-group row mb-3 p-4">
<?php
if(isset($_GET['option']))
{
if($_GET['option']=="orderCreate")
{
echo '
<a href="/Catering/customer/CustomerCreate.php" class="col-6 form-control btn btn-danger" id="cancel">Not this customer</a>
<a href="/Catering/order/orderCreate.php?customer='.$customerId.'" class="col-6 form-control btn btn-outline-primary" id="submit">Next</a>';
}
else if(($_GET['option']=="orderCreate") || ($_GET['option']=="CustomerCreate"))
{
echo '
<a href="/Catering/customer/CustomerCreate.php?option=customerEdit" class="col-6 form-control btn btn-danger" id="cancel">Not this customer</a>
<a href="/Catering/order/orderCreate.php?customer='.$customerId.'&option=customerEdit" class="col-6 form-control btn btn-outline-primary" id="submit">Order Create</a>';
}
else if($_GET['option']=="customerAndOrderalreadyHave")
{
echo '
<a href="/Catering/customer/CustomerCreate.php" class="col-6 form-control btn btn-danger" id="cancel">Not this customer</a>
<a href="/Catering/order/orderEdit.php?order='.$_GET['order'].'&customer='.$_GET['customer'].'&option=customerEdit" class="col-6 form-control btn btn-outline-primary" id="submit">Edit order</a>';
}
else if($_GET['option']=="PreviewOrder")
{
echo '<a href="/Catering/order/PreviewOrder.php?order='.$_GET['order'].'" class="col-6 form-control btn btn-outline-primary" >DONE</a>';
}
}
?>
</div>
</form>
</div>
<script>
$(document).ready(function ()
{
var customerid=$("#customerId").val();
function execute_person_address(column,text,type)
{
$.ajax({
url: "customerEditServer.php",
data:{columnname:column,value:text,edittype:type,option:"change",customerid:customerid},
dataType:"text",
method:"POST",
success:function (data) {
if(data!='')
{
alert(data);
}
}
});
}
function execute_number(column,text,type,id)
{
$.ajax({
url: "customerEditServer.php",
data:{columnname:column,value:text,edittype:type,id:id,option:"change",customerid:customerid},
dataType:"text",
method:"POST",
success:function (data) {
if(data!='') {
alert(data);
}
}
});
}
$(document).on('change','.addresschange',function () {
//address change
var column=$(this).data("columne");
var text=$(this).val();
execute_person_address(column,text,1);
});
$(document).on('change','.personchange',function () {
//personchange change
var column=$(this).data("columne");
var text=$(this).val();
execute_person_address(column,text,2);
});
$(document).on('change','.numberchange',function () {
//numberchange change
var column=$(this).data("columne");
var id=$(this).data("columneid");
var text=$(this).val();
execute_number(column,text,3,id);
});
$("#newadd").click(function ()
{
var numberText=$('#newNumber').val();
$.ajax({
url: "customerEditServer.php",
data:{option:"addNumber",number:numberText,customerid:customerid},
dataType:"text",
method:"POST",
success:function (data) {
if(data!='')
{
alert(data);
}
else
{
location.reload()
}
}
});
});
$(document).on("click",".remove_number",function () {
var id=$(this).data("removenumber");
$.ajax({
url: "customerEditServer.php",
data:{ id:id,option:"deleteNumber"},
dataType:"text",
method:"POST",
success:function (data) {
if(data!='')
{
alert(data);
}
else
{
$("#Each_number_row_"+id).remove();
}
}
});
});
$("#submitImage").change(function () {
var formData=new FormData($("#changeImage")[0]);
formData.append("option","changeImage");
$.ajax({
url:"customerEditServer.php",
method:"POST",
data:formData,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
location.reload();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-07
* Time: 13:49
*/
include_once ("../connection/connect.php");
$dishDetailId=$_SESSION['tempid'];
$sql='SELECT `describe`, `price`, `quantity`, `dish_id` FROM `dish_detail` WHERE id='.$dishDetailId.'';
$dishDetailOfDetai=queryReceive($sql);
$dishId=$dishDetailOfDetai[0][3];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(http://tongil.com.au/wp-content/uploads/2018/02/ingredients.jpg);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 class="text-dark"><i class="fas fa-file-word fa-3x mr-2 "></i>Dish Edit</h3>
</div>
</div>
<div class="container">
<?php
$display='';
$sql = 'SELECT d.id,d.name,d.image FROM dish as d WHERE d.id=' . $dishId . '';
$dishDetail = queryReceive($sql);
$display .= '
<form class="col-12" id="form">
<div class="card shadow-lg p-4 mb-4 border col-12">';
$image='';
if(file_exists('../images/dishImages/'.$dishDetail[0][2])&&($dishDetail[0][2]!=""))
{
$image= '../images/dishImages/'.$dishDetail[0][2];
}
else
{
$image='https://www.pngkey.com/png/detail/430-4307759_knife-fork-and-plate-vector-icon-dishes-png.png';
}
$display.='<div class="row">
<div class="col-6 m-auto card-body">
<img src="'.$image.'" style="height: 20vh;width: 100%">
<p class="card-header">'.$dishDetail[0][1].'</p>
</div>
</div>';
$display.='<input hidden id="dishDetailID" value="'.$dishDetailId.'">
';
$sql = 'SELECT an.id,an.quantity,a.name FROM dish_detail as dd inner join attribute_name as an
on dd.id=an.dish_detail_id
INNER join attribute as a
on a.id=an.attribute_id
WHERE dd.id='.$dishDetailId.'';
$attributeDetail = queryReceive($sql);
for ($j = 0; $j < count($attributeDetail); $j++) {
$display .= ' <div class="form-group row">
<label class="col-form-label">' . $attributeDetail[$j][2] . '</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-sticky-note"></i></span>
</div>
<input data-attributeid="'. $attributeDetail[$j][0] .'" class=" attributeChange form-control" type="number" value="'. $attributeDetail[$j][1] .'">
</div>
</div>';
}
$display .= ' <div class="form-group row">
<label class="col-form-label">each price</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-money-bill-alt"></i></span>
</div>
<input data-column="price" class="dishDetailChange form-control" type="number" value="'.$dishDetailOfDetai[0][1].'">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Quantity</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-sort-amount-up"></i></span>
</div>
<input data-column="quantity" class="dishDetailChange form-control" type="number" value="'.$dishDetailOfDetai[0][2].'">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">describe</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-comments"></i></span>
</div>
<input data-column="describe" class="dishDetailChange form-control" type="text" value="'.$dishDetailOfDetai[0][0].'"></input>
</div>
</div>
<div class="form-group row justify-content-center">';
if(isset($_GET['option']))
{
if($_GET['option']=="Allselected")
{
$display.='
<button id="cancel_dish" type="button" class="cancelForm form-control btn col-5 btn-danger" value="dish cancel"><i class="fas fa-trash-alt"></i>Delete</button>
<a href="AllSelectedDishes.php?order='.$_GET['order'].'&option=PreviewOrder" class="submitForm form-control btn col-5 btn-primary"><i class="fas fa-check "></i>Done</a>
';
}
}
else
{
$display .= '<button id="ok" type="button" class="submitForm form-control btn col-5 btn-primary" value="ok"><i class="fas fa-check "></i>OK</button>
<button id="cancel_dish" type="button" class="cancelForm form-control btn col-5 btn-danger" value="dish cancel"><i class="fas fa-trash-alt"></i>Delete</button>
';
}
$display.='</div>
</div>
</form>';
echo $display;
?>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$(document).on('change','.attributeChange',function () {
var attributeid=$(this).data('attributeid');
var valueAttribute=$(this).val();
$.ajax({
url:"dishServer.php",
data:{attributeid:attributeid,value:valueAttribute,option:"attributeChange"},
method:"POST",
dataType:"text",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!="")
{
alert(data);
}
}
});
}) ;
$(document).on('change','.dishDetailChange',function () {
var dishDetailId=$("#dishDetailID").val();
var columnName=$(this).data("column");
var columnValue=$(this).val();
$.ajax({
url:"dishServer.php",
data: {dishDetailId:dishDetailId,columnName:columnName,columnValue:columnValue,option:"dishDetailChange" },
dataType: "text",
method:"POST",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!="")
{
alert(data);
}
}
});
});
$('#cancel_dish').click(function ()
{
var dishDetailId=$("#dishDetailID").val();
$.ajax({
url:"dishServer.php",
data: {dishDetailId:dishDetailId,option:"deleteDish" },
dataType: "text",
method:"POST",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!="")
{
alert(data);
}
else
{
window.location.href="AllSelectedDishes.php>";
}
}
});
});
$('#ok').click(function ()
{
window.location.href="AllSelectedDishes.php";
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
include_once ("../connection/printOrderDetail.php");
if(!isset($_SESSION['order']))
{
header("location:../user/userDisplay.php");
}
if(isset($_GET['action']))
{
$orderId=$_SESSION['order'];
$currentdate = (string) date_create()->format('Y-m-d:H:i:s');
//$currentdate=date('now');
//$currentdate="";
if($_GET['action']=="see")
{
action($_COOKIE['username'],$currentdate,$orderId,"I");
exit();
}
else
{
action($_COOKIE['username'],$currentdate,$orderId,"D");
exit();
}
}
$hallid="";
$cateringid='';
$orderId="";
if(isset($_SESSION['order']))
{
$orderId=$_SESSION['order'];
$sql='SELECT od.hall_id,od.catering_id FROM orderDetail as od WHERE od.id='.$orderId.'';
$result=queryReceive($sql);
if($result[0][0]!="")
{
$hallid=$result[0][0];
}
else
{
$cateringid=$result[0][1];
}
}
$sql='SELECT (SELECT p.name FROM person as p WHERE p.id=od.person_id),od.person_id,(SELECT p.image FROM person as p WHERE p.id=od.person_id) FROM orderDetail as od WHERE od.id='.$orderId.'';
$orderDetailPerson= queryReceive($sql);
$customerID=$orderDetailPerson[0][1];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://www.myofficeapps.com/wp-content/uploads/2017/10/streamline-process.jpg);background-size:100% 130%;background-repeat: no-repeat">
<div class="card-body text-center" style="opacity: 0.7 ;background: #fdfdff;">
<h3 ><i class="fas fa-book fa-2x mr-2"></i>Order informations </h3>
</div>
</div>
<div class="row justify-content-center col-12" style="margin-top: -60px">
<div class="card text-center card-header">
<img src="<?php
if(file_exists('../images/customerimage/'.$orderDetailPerson[0][2])&&($orderDetailPerson[0][2]!=""))
{
echo '../images/customerimage/'.$orderDetailPerson[0][2];
}
else
{
echo 'https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
?> " style="height: 20vh;" class="figure-img rounded-circle" alt="image is not set">
<h5 ><?php
echo $orderDetailPerson[0][0];
?></h5>
<label >Order ID:<?php
echo $orderId;
?></label>
</div>
</div>
<div class="container row m-auto">
<a href="?action=see " class="h-25 col-5 shadow text-dark m-2 text-center fa-5x" resource=""><i class="fas fa-eye"></i><h4>See Bill / Preview order</h4></a>
<a href="?action=Download" class="h-25 col-5 shadow text-dark m-2 text-center fa-5x" download><i class="fas fa-cloud-download-alt"></i><h4>Download Bill</h4></a>
<a href="../customer/customerEdit.php?action=preview" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-user-edit fa-5x"></i><h4>Customer Preview</h4></a>
<?php
if($hallid!="")
{
//1 hall order edit //2 make hall order to user displaye
echo '<a href="../company/hallBranches/EdithallOrder.php" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-cart-arrow-down fa-5x"></i><h4>Order Edit</h4></a>';
}
else
{
//catering order editor //2 make catering order to user displaye
echo '<a href="orderEdit.php?action=preview" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-cart-arrow-down fa-5x"></i><h4>Order edit</h4></a>';
}
?>
<a href="../user/userDisplay.php" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-grip-horizontal fa-5x"></i><h4>User Display</h4></a>
<a href="../dish/AllSelectedDishes.php" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-file-word fa-5x"></i><h4>Bill Detail/ extend </h4></a>
<a href="../payment/paymentHistory.php" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-history fa-5x"></i><h4>Payment History</h4></a>
<a href="../payment/getPayment.php" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="far fa-money-bill-alt fa-5x"></i><h4>Get payment from customer</h4></a>
<a href="../payment/paymentDisplaySend.php" class="h-25 col-5 shadow text-dark m-2 text-center"> <i class="fas fa-share-alt fa-5x"></i><h4>Transfer payment <p>(user to user)</p> </h4></a>
<a href="../payment/transferPaymentReceive.php" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-clipboard-check fa-5x"></i><h4>Payment Receiving Request <p>(user to user)</p> </h4></a>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
if(isset($_COOKIE["companyid"]))
{
header('location:../company/companyRegister/companydisplay.php');
exit();
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/loader.css">
<style>
</style>
</head>
<body style="background-image: url(https://www.saracarboni.com/wp-content/uploads/2017/02/4-wedding-reception-1.jpg);background-size:100% 100%;">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container">
<div class="card-header"></div>
<div class="col-sm-12 col-xl-6 col-md-8 col-12 m-auto card badge-dark" style="background-color: rgba(0,0,0,0.7) !important;">
<h1 CLASS="mb-5 mt-5"><i class="fas fa-sign-in-alt"></i> Sign in</h1>
<form class="col-12" id="formLogin">
<div class="form-group row">
<label class="col-form-label">User Name</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user"></i></span>
</div>
<input type="text" class="form-control" name="username" placeholder="Username">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Password</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-key"></i></span>
</div>
<input type="<PASSWORD>" class="form-control" name="password" placeholder="<PASSWORD>">
</div>
</div>
<div class="form-group row">
<button id="login" type="button" class="form-control btn btn-success" value="Sign in"><i class="fas fa-sign-in-alt"></i> Sign in</button>
</div>
</form>
</div>
</div>
<div class="card-header"></div>
<div class="card-header"></div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$('#login').click(function ()
{
var formdata=new FormData($("#formLogin")[0]);
formdata.append("option","login");
$.ajax({
url:"userServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
}
else
{
location.reload();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-10
* Time: 11:50
*/
include_once ("../connection/connect.php");
if(isset($_POST["option"]))
{
if($_POST['option']=="login")
{
$userName=$_POST['username'];
$password=$_POST['password'];
$sql='SELECT u.id,u.isOwner,u.company_id,(SELECT p.image FROM person as p WHERE p.id=u.person_id) FROM user as u WHERE (u.username="'.$userName.'")AND(u.password="'.$password.'")';
$userDetail=queryReceive($sql);
if(count($userDetail)==0)
{
echo "please user is not registerd";
}
else
{
setcookie('userid',$userDetail[0][0] , time() + (86400 * 30), "/");
setcookie("isOwner",$userDetail[0][1],time() + (86400 * 30), "/");
setcookie("username",$userName,time() + (86400 * 30), "/");
setcookie("companyid",$userDetail[0][2],time() + (86400 * 30), "/");
setcookie("userimage",$userDetail[0][3],time() + (86400 * 30), "/");
/*$_SESSION['userid']=$_COOKIE['userid'];
$_SESSION['isOwner']=$_COOKIE['isOwner'];
$_SESSION['username']=$_COOKIE['username'];
$_SESSION['companyid']=$_COOKIE['companyid'];
$_SESSION['userimage']=$_COOKIE['userimage'];
$_SESSION['userid']=$userDetail[0][0];
$_SESSION['isOwner']=$userDetail[0][1];
$_SESSION['username']=$userName;
$_SESSION['companyid']=$userDetail[0][2];
$_SESSION['userimage']=$userDetail[0][3];*/
}
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
if(isset($_GET['action']))
{
$_SESSION['order']=$_GET['order'];
$_SESSION['customer']=$_GET['customer'];
header("location:/Catering/order/PreviewOrder.php");
}
$hallid="";
$cateringid="";
$hallorcater="";
$order_info=$_GET['order_status'];
$order_status=$order_info;
if(isset($_SESSION['branchtype']))
{
if($_SESSION['branchtype']=="hall")
{
$hallid=$_SESSION['branchtypeid'];
}
else
{
$cateringid=$_SESSION['branchtypeid'];
}
}
if(!empty($hallid))
{
$hallorcater="(od.hall_id=".$hallid.")";
$order_status='(od.status_hall="'.$order_status.'")';
}
else
{
$hallorcater="(od.catering_id=".$cateringid.")";
$order_status='(od.status_catering="'.$order_status.'")';
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/complete.css">
<style>
.newcolor
{
background: #E0EAFC; /* fallback for old browsers */
background: -webkit-linear-gradient(to left, #CFDEF3, #E0EAFC); /* Chrome 10-25, Safari 5.1-6 */
background: linear-gradient(to left, #CFDEF3, #E0EAFC); /* W3C, IE 10+/ Edge, Firefox 16+, Chrome 26+, Opera 12+, Safari 7+ */
}
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://university.daraz.pk/pluginfile.php/26/course/section/10/Order%20Fulfilment-01.png);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 class="text-dark"> <i class="fas fa-search-plus fa-3x"></i>Find Orders</h3>
<p> Check <?php echo $order_info." order and "?> all orders</p>
<button data-display="hide" id="searchBtn" class="btn-warning btn justify-content-center "><i class="fas fa-search"></i>Search Order</button>
</div>
</div>
<div class="container">
<form class="col-12 shadow mb-4 newcolor card " id="formId1" style="display: none">
<div class="form-group row">
<label class="col-form-label"> Customer name</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user"></i></span>
</div>
<input name="p_name" type="text" class="changeColumn form-control" placeholder="or customer name etc ali,....">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Customer CNIC</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-id-card"></i></span>
</div>
<input name="p_cnic" type="number" class="changeColumn form-control" placeholder="or cnic 23212xxxxx">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Customer ID</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-id-card"></i></span>
</div>
<input name="p_id" type="number" class="changeColumn form-control" placeholder="customer ID 1,2,3,4,.....">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Customer phone</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-mobile-alt"></i></span>
</div>
<input name="n_number" type="text" class="changeColumn form-control" placeholder="number 03231xxxxxx">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Booking Date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-calendar-alt"></i></span>
</div>
<input name="od_booking_date" type="date" class="changeColumn form-control">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Destination Date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-business-time"></i></span>
</div>
<input name="od_destination_date" type="date" class="changeColumn form-control">
</div>
</div>
<div class="form-group row">
<label class="col-form-label ">order status</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-eye"></i></span>
</div>
<select name="<?php
if($hallid=="")
{
echo "od_status_catering";
}
else
{
echo "od_status_hall";
}
?>" class="changeColumn form-control">
<option value="None">None</option>
<?php
$OrderStatus=array("Running","Cancel","Delieved","Clear");
for($i=0;$i<count($OrderStatus);$i++)
{
echo '<option value='.$OrderStatus[$i].'>'.$OrderStatus[$i].'</option>';
}
?>
</select>
</div>
</div>
<div class="form-group row justify-content-center">
<button type="button" class="form-control btn-success col-6"><i class="fas fa-search"></i>Find</button>
</div>
</form>
<div id="recordsAll">
<?php
$sql='SELECT od.id,(SELECT p.name FROM person as p WHERE p.id=od.person_id),(SELECT p.image FROM person as p WHERE p.id=od.person_id),od.destination_date,od.destination_time,od.status_hall,od.status_catering,od.hall_id,od.catering_id,(SELECT hp.package_name FROM hallprice as hp WHERE hp.id=od.hallprice_id),od.person_id FROM orderDetail as od WHERE '.$hallorcater.' AND '.$order_status.'';
$orderdetail=queryReceive($sql);
$display='';
for ($i=0;$i<count($orderdetail);$i++)
{
$display.='
<a href="?action=preview&order='.$orderdetail[$i][0].'&customer='.$orderdetail[$i][10].'';
$display.='" class="col-12 row shadow m-3 newcolor">
<img src="';
if(file_exists($orderdetail[$i][2]))
{
$display.= $orderdetail[$i][2];
}
else
{
$display.="https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png";
}
$display.='"class="col-3 p-0">
<div class="col-9">
<label class="col-12">Order id:<i class="text-secondary">'.$orderdetail[$i][0].'</i> </label>
<label class="col-12">Name: <i class="text-secondary">'.$orderdetail[$i][1].'</i></label>
<label class="col-12">Date: <i class="text-secondary">'.$orderdetail[$i][3].'</i></label>
</div>
<label class="col-12">Time: <i class="text-secondary">';
if(!empty($hallid))
{
//if order is hall order timing
if ($orderdetail[$i][4] == "09:00:00")
{
$display .= "Morning";
} else if ($orderdetail[$i][4] == "12:00:00") {
$display .= "Afternoon";
} else
{
$display .= "18:00:00";
}
}
else
{
//catering order
$display.=$orderdetail[$i][4];
}
$display.='</i></label>';
if($orderdetail[$i][7]!="")
{
//if order is hall
$display .= '<label class="col-12">Per Head:<i class="text-secondary">';
if ($orderdetail[$i][9] != "")
{
//hall is booked wth food+seaating
$display.=$orderdetail[$i][9].' Food+Seating';
} else
{
//hall is book only seating
$display.='Only Seating';
}
$display.='</i> </label>';
}
if(($orderdetail[$i][6]!="")&&($orderdetail[$i][8]!=""))
{
//catering status
$display.='
<label class="col-12">Catering Status:<i class="text-secondary">'.$orderdetail[$i][6].'</i> </label>';
}
if(($orderdetail[$i][5]!="")&&($orderdetail[$i][7]!=""))
{
//hall status
$display.='
<label class="col-12">Hall Status:<i class="text-secondary">'.$orderdetail[$i][5].'</i> </label>';
}
$display.='</a>';
}
echo $display;
?>
</div>
<!-- <a href="#" class="col-12 btn-outline-danger row shadow m-3">-->
<!-- <img src="../gmail.png" class="col-3 p-0">-->
<!-- <div class="col-9">-->
<!-- <label class="col-12">order id:<i class="text-secondary">1</i> </label>-->
<!-- <label class="col-12">Name: <i class="text-secondary"><NAME></i></label>-->
<!-- <label class="col-12">date: <i class="text-secondary">12:9:21</i></label>-->
<!-- </div>-->
<!-- <label class="col-12">time: <i class="text-secondary">1</i></label>-->
<!-- <label class="col-12">catering status:<i class="text-secondary">1</i> </label>-->
<!-- <label class="col-12">Hall status:<i class="text-secondary">1</i> </label>-->
<!-- </a>-->
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$(document).on("change",'.changeColumn',function (e)
{
e.preventDefault();
var formdata=new FormData($('#formId1')[0]);
formdata.append("hallorcater","<?php echo $hallorcater;?>");
$.ajax({
url:"FindOrderServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
$("#recordsAll").html(data);
}
});
});
$("#searchBtn").click(function () {
var display=$(this).data("display");
if(display=="hide")
{
$("#formId1").show('slow');
$(this).data("display","show");
}
else
{
$("#formId1").hide('slow');
$(this).data("display","hide");
}
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-03
* Time: 17:20
*/
include_once ("../connection/connect.php");
if(isset($_POST['option']))
{
if($_POST['option']=="customerCreate")
{
$image='';
if(!empty($_FILES['image']["name"]))
{
$image = "../images/customerimage/" . $_FILES['image']['name'];
$resultimage = ImageUploaded($_FILES, $image);//$dishimage is destination file location;
if ($resultimage != "") {
print_r($resultimage);
exit();
}
$image =$_FILES['image']['name'];
}
$name = trim($_POST['name']);
$numberArray = $_POST['number'];
$cnic = chechIsEmpty($_POST['cnic']);
$city = chechIsEmpty($_POST['city']);
$area = chechIsEmpty($_POST['area']);
$streetNo = chechIsEmpty($_POST['streetNo']);
$houseNo = chechIsEmpty($_POST['houseNo']);
$date = date('Y-m-d');
$sql = 'INSERT INTO `person`(`name`, `cnic`, `id`, `date`, `image`) VALUES ("'.$name.'","'.$cnic.'",NULL,"'.$date.'","'.$image.'")';
querySend($sql);
$last_id = mysqli_insert_id($connect);
$sql='INSERT INTO `address`(`id`, `address_street_no`, `address_house_no`, `person_id`, `address_city`, `address_town`) VALUES (NULL,"'.$streetNo.'","'.$houseNo.'",'.$last_id.',"'.$city.'","'.$area.'")';
querySend($sql);
for ($i = 0; $i < count($numberArray); $i++) {
$sql='INSERT INTO `number`(`number`, `id`, `is_number_active`, `person_id`) VALUES ("'.$numberArray[$i].'",NULL,1,'.$last_id.')';
querySend($sql);
}
$customerId = $last_id;
$_SESSION['customer']=$customerId;
}
else
{
//if($_POST['option']=="customerExist")
$value=$_POST['value'];
$sql='SELECT n.person_id FROM number as n WHERE n.number="'.$value.'"';
$customerexist=queryReceive($sql);
if(count($customerexist)>0)
{
//echo $customerexist[0][0];
$_SESSION['customer']=$customerexist[0][0];
echo "customerexist";
}
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
$hallid=$_GET['hallid']=1;
$cateringid=$_GET['cateringid']='';
$hallorcater="";
$order_status=$_GET['order_status'];
if(!empty($hallid))
{
$hallorcater="(od.hall_id=".$hallid.")";
$order_status='(od.status_hall="'.$order_status.'")';
}
else
{
$hallorcater="(od.catering_id=".$cateringid.")";
$order_status='(od.status_catering="'.$order_status.'")';
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0px;
padding: 0px;
}
</style>
</head>
<body class="alert-light">
<div class="container" style="margin-top:150px">
<h1 align="center"> Orders</h1>
<form class="col-12 shadow card mb-4" id="formId1" style="display: none">
<h2>Search order :</h2>
<div class="form-group row">
<label class="col-form-label col-4"> customer name</label>
<input name="p_name" type="text" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> customer CNIC</label>
<input name="p_cnic" type="number" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> customer ID</label>
<input name="p_id" type="number" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> customer phone</label>
<input name="n_number" type="text" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4">booking Date</label>
<input name="od_booking_date" type="date" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> destination date</label>
<input name="od_destination_date" type="date" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4">order status</label>
<select name="<?php
if($hallid=="")
{
echo "od_status_catering";
}
else
{
echo "od_status_hall";
}
?>" class="changeColumn form-control col-8 ">
<option value="None">None</option>
<?php
$OrderStatus=array("Running","Cancel","Delieved","Clear");
for($i=0;$i<count($OrderStatus);$i++)
{
echo '<option value='.$OrderStatus[$i].'>'.$OrderStatus[$i].'</option>';
}
?>
</select>
</div>
<div class="form-group row">
<a href="/Catering/user/userDisplay.php" class="col-4 form-control btn-danger">cancel</a>
<button type="button" class="col-4 form-control btn-success">Find</button>
</div>
</form>
<h3 align="center" ><button data-display="hide" id="searchBtn" class="btn-outline-info btn float-left ">Search Order</button>display records</h3>
<div id="recordsAll">
<?php
$sql='SELECT od.id,(SELECT p.name FROM person as p WHERE p.id=od.person_id),(SELECT p.image FROM person as p WHERE p.id=od.person_id),od.destination_date,od.destination_time,od.status_hall,od.status_catering,od.hall_id,od.catering_id,(SELECT hp.package_name FROM hallprice as hp WHERE hp.id=od.hallprice_id) FROM orderDetail as od WHERE '.$hallorcater.' AND '.$order_status.'';
$orderdetail=queryReceive($sql);
$display='';
for ($i=0;$i<count($orderdetail);$i++)
{
$display.='
<a href="#'.$orderdetail[$i][0].'" class="col-12 row shadow m-3">
<img src="';
if(file_exists($orderdetail[$i][2]))
{
$display.= $orderdetail[$i][2];
}
else
{
$display.="../gmail.png";
}
$display.='"class="col-3 p-0">
<div class="col-9">
<label class="col-12">Order id:<i class="text-secondary">'.$orderdetail[$i][0].'</i> </label>
<label class="col-12">Name: <i class="text-secondary">'.$orderdetail[$i][1].'</i></label>
<label class="col-12">Date: <i class="text-secondary">'.$orderdetail[$i][3].'</i></label>
</div>
<label class="col-12">Time: <i class="text-secondary">';
if(!empty($hallid))
{
//if order is hall order timing
if ($orderdetail[$i][4] == "09:00:00")
{
$display .= "Morning";
} else if ($orderdetail[$i][4] == "12:00:00") {
$display .= "Afternoon";
} else
{
$display .= "18:00:00";
}
}
else
{
//catering order
$display.=$orderdetail[$i][4];
}
$display.='</i></label>';
if($orderdetail[$i][7]!="")
{
//if order is hall
$display .= '<label class="col-12">Per Head:<i class="text-secondary">';
if ($orderdetail[$i][9] != "")
{
//hall is booked wth food+seaating
$display.=$orderdetail[$i][9].' Food+Seating';
} else
{
//hall is book only seating
$display.='Only Seating';
}
$display.='</i> </label>';
}
if(($orderdetail[$i][6]!="")&&($orderdetail[$i][8]!=""))
{
//catering status
$display.='
<label class="col-12">Catering Status:<i class="text-secondary">'.$orderdetail[$i][6].'</i> </label>';
}
if(($orderdetail[$i][5]!="")&&($orderdetail[$i][7]!=""))
{
//hall status
$display.='
<label class="col-12">Hall Status:<i class="text-secondary">'.$orderdetail[$i][5].'</i> </label>';
}
$display.='</a>';
}
echo $display;
?>
</div>
<!-- <a href="#" class="col-12 btn-outline-danger row shadow m-3">-->
<!-- <img src="../gmail.png" class="col-3 p-0">-->
<!-- <div class="col-9">-->
<!-- <label class="col-12">order id:<i class="text-secondary">1</i> </label>-->
<!-- <label class="col-12">Name: <i class="text-secondary"><NAME></i></label>-->
<!-- <label class="col-12">date: <i class="text-secondary">12:9:21</i></label>-->
<!-- </div>-->
<!-- <label class="col-12">time: <i class="text-secondary">1</i></label>-->
<!-- <label class="col-12">catering status:<i class="text-secondary">1</i> </label>-->
<!-- <label class="col-12">Hall status:<i class="text-secondary">1</i> </label>-->
<!-- </a>-->
</div>
<script>
$(document).ready(function () {
$(document).on("change",'.changeColumn',function (e)
{
e.preventDefault();
var formdata=new FormData($('#formId1')[0]);
formdata.append("hallorcater","<?php echo $hallorcater;?>");
$.ajax({
url:"FindOrderServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
$("#recordsAll").html(data);
// console.log(data);
}
});
});
$("#searchBtn").click(function () {
var display=$(this).data("display");
if(display=="hide")
{
$("#formId1").show('slow');
$(this).data("display","show");
}
else
{
$("#formId1").hide('slow');
$(this).data("display","hide");
}
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-10
* Time: 14:04
*/
session_start();
if(!isset($_SESSION['username']))
{
header("location:userLogin.php");
exit();
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container p-0 " style="margin-top:200px" >
<div class="col-12 shadow card p-0 ">
<!-- $OrderStatus=array("running","cancel","delieved","clear");-->
<h1 align="center" class="col-12">User Desplay</h1>
<div class="form-group row">
<a href="/customer/CustomerCreate.php?option=userDisplay" class="text-center col-6 form-control btn-primary">Order Create</a>
<a href="/order/FindOrder.php?is_active=0" class="text-center col-6 form-control btn-primary">Running Order</a>
</div>
<div class="form-group row">
<a href="/order/FindOrder.php?is_active=2" class="col-6 text-center form-control btn-primary">deliver Orders</a>
<a href="/order/FindOrder.php?is_active=3" class="col-6 text-center form-control btn-primary">Clear Orders</a>
</div>
<div class="form-group row">
<a href="/order/FindOrder.php?is_active=1" class="col-6 text-center form-control btn-primary">Cancel Orders</a>
<a href="/payment/transferPaymentReceive.php?option=userDisplay" class="col-6 text-center form-control btn-primary">Receive payment</a>
</div>
<div class="form-group row">
<a href="/system/dish/dishesDetail.php" class="col-6 text-center form-control btn-primary">System Guideline Dishes</a>
<a href="/system/user/usercreate.php" class="col-6 text-center form-control btn-primary">User Create</a>
</div>
<div class="form-group row">
<a href="/user/logout.php" class="col-6 text-center form-control btn-primary">Log out</a>
</div>
</div>
</div>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-06
* Time: 16:48
*/
include_once ("../connection/connect.php");
if((!isset($_POST['dishid']))&&($_GET['order']))
{
header("location:AllSelectedDishes.php?order=".$_GET['order']."");
exit();
}
$orderId=$_GET['order'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<div class="container" style="margin-top:150px">
<h1 align="center">Create dishes</h1>
<input hidden type="number" id="orderIdindish" value="<?php echo $_GET["order"];?>">
<?php
$dishesId=$_POST['dishid'];
$types=$_POST['types'];
$totalDishes=0;
$display='';
$number=0;
for ($i=0;$i<count($types);$i++)
{
$totalDishes+=$types[$i];
for ($k=$types[$i];$k>0;$k--)
{
$value=$dishesId[$i];
$sql = 'SELECT d.id,d.name FROM dish as d WHERE d.id=' . $value . '';
$dishDetail = queryReceive($sql);
$display .= '
<form id="form_' . $number . '">
<div class="border shadow-lg p-4 mb-4 bg-white col-12">
<h2 align="center">' . $dishDetail[0][1] . '</h2>
<input hidden type="number" name="dishId" value="' . $value . '">';
$sql = 'SELECT a.id,a.name FROM attribute as a INNER JOIN dish as d
on d.id=a.dish_id
WHERE (d.id=' . $value . ') AND (ISNULL(a.isExpire))';
$attributeDetail = queryReceive($sql);
for ($j = 0; $j < count($attributeDetail); $j++) {
$display .= ' <div class="form-group row">
<label class="col-form-label col-4">' . $attributeDetail[$j][1] . '</label>
<input hidden name="attributeId[]" value="' . $attributeDetail[$j][0] . '">
<input name="attributeValue[]" class="form-control col-8" type="number">
</div>';
}
$display .= ' <div class="form-group row">
<label class="col-form-label col-4">each price</label>
<input name="each_price" class="form-control col-8" type="number">
</div>
<div class="form-group row">
<label class="col-form-label col-4">Quantity</label>
<input name="quantity" class="form-control col-8" type="number">
</div>
<div class="form-group row">
<label class="col-form-label col-4">describe</label>
<textarea name="describe" class="form-control col-8" type="text"></textarea>
</div>
<div class="form-group row">
<input type="button" data-formid="' . $number . '" class="cancelForm form-control btn col-4 btn-danger" value="cancel">
<input type="button" data-formid="' . $number . '" class="submitForm form-control btn col-4 btn-primary" value="submit">
</div>
</div>
</form>';
$number++;
}
}
echo $display;
echo '<h4 align="center">total number of dishes<input readonly type="number" id="totalRemaing" value='.$totalDishes.'></h4>';
?>
</div>
<script>
$(document).ready(function ()
{
var totalitems= $("#totalRemaing").val();
function redirect()
{
totalitems--;
if(totalitems==0)
{
var orderid=$("#orderIdindish").val();
window.location.href="/Catering/dish/AllSelectedDishes.php?order="+orderid;
}
}
$(document).on('click','.submitForm',function ()
{
var orderid=$("#orderIdindish").val();
var id=$(this).data("formid");
var formdata=new FormData($("#form_"+id)[0]);
formdata.append("option",'createDish');
$.ajax({
url:"dishServer.php?order="+orderid,
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
$("#form_"+id).remove();
redirect();
}
}
});
});
$(document).on('click','.cancelForm',function () {
var id=$(this).data("formid");
$("#form_"+id).remove();
redirect();
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-11
* Time: 16:25
*/
include_once ("../../../connection/connect.php");
if(isset($_POST['option']))
{
if($_POST["option"]=="addDishsystem")
{
$dishname=chechIsEmpty($_POST['dishname']);
$cateringid=$_POST['cateringid'];
$dishimage='';
if(!empty($_FILES['image']["name"]))
{
$dishimage = "../../../images/dishImages/" . $_FILES['image']['name'];
$resultimage = ImageUploaded($_FILES, $dishimage);//$dishimage is destination file location;
if ($resultimage != "") {
print_r($resultimage);
exit();
}
}
$dishtype='';
if($_POST["dishtype"]=="others")
{
$dishtypename=$_POST['otherdishType'];
$sql='INSERT INTO `dish_type`(`id`, `name`, `isExpire`,`catering_id`) VALUES (NULL,"'.$dishtypename.'",NULL,'.$cateringid.')';
querySend($sql);
$dishtype=mysqli_insert_id($connect);
}
else
{
$dishtype=$_POST["dishtype"];
}
$sql='INSERT INTO `dish`(`name`, `id`, `image`, `isExpire`, `dish_type_id`,`catering_id`) VALUES ("'.$dishname.'",NULL,"'.$dishimage.'",NULL,'.$dishtype.','.$cateringid.')';
querySend($sql);
$dishid=mysqli_insert_id($connect);
if(isset($_POST['attribute']))
{
$addAttributes = $_POST['attribute'];
for ($i = 0; $i < count($addAttributes); $i++) {
$sql = 'INSERT INTO `attribute`(`name`, `id`, `isExpire`, `dish_id`) VALUES ("'.$addAttributes[$i].'",NULL,NULL,'.$dishid.')';
querySend($sql);
}
}
}
else if($_POST['option']=="attributesCreate")
{
$dishid=$_POST["dishid"];
if(!isset($_POST['attribute']))
{
exit();
}
$addAttributes=$_POST['attribute'];
for($i=0;$i<count($addAttributes);$i++)
{
$sql='INSERT INTO `attribute`(`name`, `id`, `dish_id`, `isExpire`) VALUES ("'.$addAttributes[$i].'",NULL,'.$dishid.',NULL)';
querySend($sql);
}
}
else if($_POST['option']=="dishchanges")
{
$dishid=$_POST['dishid'];
$column=$_POST['column'];
$text=chechIsEmpty($_POST['text']);
$sql='UPDATE `dish` SET '.$column.'="'.$text.'" WHERE id='.$dishid.'';
querySend($sql);
}
else if($_POST['option']=='changeAttributes')
{
$attributeid=$_POST['attributeid'];
$text=chechIsEmpty($_POST['text']);
$sql='UPDATE `attribute` SET `name`="'.$text.'" WHERE id='.$attributeid.'';
querySend($sql);
}
else if($_POST['option']=="RemoveAttribute")
{
$attributeid=$_POST['attributeid'];
$timestamp = date('Y-m-d H:i:s');
$sql='UPDATE attribute as a SET a.isExpire="'.$timestamp.'" WHERE a.id='.$attributeid.'';
querySend($sql);
}
else if($_POST['option']=="ExpireDish")
{
$timestamp = date('Y-m-d H:i:s');
$dishid=$_POST['dishid'];
$value=$_POST['value'];
if($value=="Show dish")
{
$sql='UPDATE dish as d SET d.isExpire=NULL WHERE d.id='.$dishid.'';
}
else
{
$sql='UPDATE dish as d SET d.isExpire="'.$timestamp.'" WHERE d.id='.$dishid.'';
}
querySend($sql);
}
else if($_POST['option']=="changeDishType")
{
$id=$_POST['id'];
$value=chechIsEmpty($_POST['value']);
$sql='UPDATE dish_type as dt SET dt.name="'.$value.'" WHERE dt.id='.$id.'';
querySend($sql);
}
else if($_POST['option']=="Delele_Dish_Type")
{
$id=$_POST['id'];
$value=chechIsEmpty($_POST['value']);
if($value=="Disable")
{
$timestamp = date('Y-m-d H:i:s');
$sql = 'UPDATE dish_type as dt SET dt.isExpire="' . $timestamp . '" WHERE dt.id=' . $id . '';
}
else
{
$sql = 'UPDATE dish_type as dt SET dt.isExpire=NULL WHERE dt.id=' . $id . '';
}
querySend($sql);
}
else if ($_POST['option']=="changeImage")
{
if(empty($_FILES['image']["name"]))
{
exit();
}
$dishId=$_POST['dishId'];
$dishimage="../../../images/dishImages/".$_FILES['image']['name'];
$resultimage=ImageUploaded($_FILES,$dishimage);//$dishimage is destination file location;
if($resultimage!="")
{
print_r($resultimage);
exit();
}
$sql='UPDATE `dish` SET image="'.$dishimage.'" WHERE id='.$dishId.'';
querySend($sql);
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-10
* Time: 11:50
*/
include_once ("../connection/connect.php");
session_start();
if(isset($_POST["option"]))
{
if($_POST['option']=="login")
{
$userName=$_POST['username'];
$password=$_POST['password'];
$sql='SELECT u.id,u.isOwner FROM user as u WHERE (u.username="'.$userName.'")AND(u.password="'.$password.'")';
$userDetail=queryReceive($sql);
if(count($userDetail)==0)
{
echo "please user is not registerd";
}
else
{
$_SESSION['userid']=$userDetail[0][0];
$_SESSION['isOwner']=$userDetail[0][1];
$_SESSION['username']=$userName;
}
}
}
?><file_sep><?php
///**
// * Created by PhpStorm.
// * User: shahzadmiraj
// * Date: 2019-09-01
// * Time: 21:31
// */
//
//
//?>
<!--<!DOCTYPE html>-->
<!--<head>-->
<!-- <meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">-->
<!-- <link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">-->
<!-- <script src="../../jquery-3.3.1.js"></script>-->
<!-- <script type="text/javascript" src="../../bootstrap.min.js"></script>-->
<!-- <meta charset="utf-8">-->
<!-- <link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">-->
<!-- <script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>-->
<!-- <script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>-->
<!---->
<!-- <style>-->
<!-- *{-->
<!-- margin:auto;-->
<!-- padding: auto;-->
<!-- }-->
<!-- </style>-->
<!--</head>-->
<!--<body >-->
<div class=" btn-danger w-100 shadow fixed-top ">
<h1 align="center">Welcome to New Kashmir Food Center</h1>
<h3 align="center " class="text-capitalize">
<?php
if(isset($_SESSION['username']))
{
echo '<span class="btn-light shadow font-weight-bold btn col-4">'.$_SESSION['username'].'</span>';
}
?>
</h3>
<a href="/user/userLogin.php" class="btn btn-warning">Home Page</a>
</div>
<!---->
<!--<script>-->
<!---->
<!---->
<!--</script>-->
<!--</body>-->
<!--</html>-->
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../../connection/connect.php");
if (!isset($_COOKIE['companyid']))
{
header("location:../../user/userLogin.php");
}
if(!isset($_GET['catering']))
{
header("location:./../companyRegister/companyEdit.php");
}
$encoded=$_GET['catering'];
$id=base64url_decode($encoded);
if((!is_numeric($id))||$id=="")
{
header("location:../../companyRegister/companyEdit.php");
}
$cateringid=$id;
if(isset($_GET['dishdetail']))
{
$encodedDishId=base64url_encode($_GET['dishid']);
header("location:EditDish.php?dish=".$encodedDishId."&catering=".$encoded."");
}
$sql = 'SELECT `name`, `expire`, `image`, `location_id` FROM `catering` WHERE id=' . $cateringid . '';
$cateringdetail = queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../../bootstrap.min.css">
<script src="../../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../../webdesign/header/header.php");
?>
<div class="jumbotron shadow text-center " style="background-image: url(<?php
if((file_exists('../../../images/catering/'.$cateringdetail[0][2])) &&($cateringdetail[0][2]!=""))
{
echo "'../../../images/catering/".$cateringdetail[0][2]."'";
}
else
{
echo "https://www.liberaldictionary.com/wp-content/uploads/2019/02/cater-4956.jpg";
}
?>
);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-body " style="opacity: 0.7 ;background: white;">
<h1 class="display-5 text-center"><i class="fas fa-hamburger fa-3x"></i><?php echo $cateringdetail[0][0];?> Dishes info</h1>
<p class="lead">Edit dishes information,dishes type,images and others </p>
<h1 class="text-center"> <a href="../../companyRegister/companyEdit.php" class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container">
<h1 class="font-weight-bold">System Dish info </h1>
<hr>
<h3 align="center"> Dish Type information</h3>
<div class="col-12 form-group row font-weight-bold border">
<label class="col-9 col-form-label "><i class="fas fa-utensils mr-1"></i>Name Dish type</label>
<label class="col-3 col-form-label ">Detail</label>
</div>
<div class="col-12">
<?php
$sql='SELECT `id`, `name`, `isExpire` FROM `dish_type` WHERE catering_id='.$cateringid.'';
$dishTypes=queryReceive($sql);
$Display='';
for($i=0;$i<count($dishTypes);$i++)
{
$Display.= '<div class="form-group row border " id="Delele_Dish_Type_'.$dishTypes[$i][0].'">
<input data-dishtypeid="'.$dishTypes[$i][0].'" value="'.$dishTypes[$i][1].'" class="changeDishType col-9 form-control ">
<input data-dishtypeid="'.$dishTypes[$i][0].'" class=" btn Delele_Dish_Type col-3 form-control ';
if($dishTypes[$i][2]=="")
{
$Display.='btn-primary ';
}
else
{
$Display.=' btn-danger ';
}
$Display.=' " value="';
if($dishTypes[$i][2]=="")
{
$Display.='Disable';
}
else
{
$Display.='Enable';
}
$Display.= '"></div>';
}
echo $Display;
?>
</div>
<div class="col-12 row mb-4">
<h3 class="rounded mx-auto d-block m-4 col-6" align="center"> Dish information</h3>
<a href="addDish.php?catering=<?php echo $encoded;?>" class="float-right btn btn-success col-4 form-control mt-4">Add dish +</a>
</div>
<hr>
<div class="col-12 card shadow mb-2 p-4 ">
<?php
$sql='SELECT id,name FROM dish_type WHERE catering_id='.$cateringid.'';
$dishTypes=queryReceive($sql);
$Display='';
$display='<div class="form-group row ">';
for($j=0;$j<count($dishTypes);$j++)
{
$display.='<h4 class="col-12 newcolor" align="center">'.$dishTypes[$j][1].'</h4>';
$sql = 'SELECT d.name, d.id, (SELECT dt.name from dish_type as dt WHERE dt.id=d.dish_type_id),(SELECT dt.isExpire from dish_type as dt WHERE dt.id=d.dish_type_id), d.isExpire,d.image FROM dish as d WHERE dish_type_id=' . $dishTypes[$j][0] . ' ';
$Dishes = queryReceive($sql);
for ($i = 0; $i < count($Dishes); $i++) {
$display .= '<a href="?dishdetail=yes&dishid=' . $Dishes[$i][1]. '&catering='.$encoded.'" class="col-sm-12 col-md-6 col-xl-4 border">
<img src="';
if(file_exists('../../../images/dishImages/'.$Dishes[$i][5])&&($Dishes[$i][5]!=""))
{
$display.='../../../images/dishImages/'.$Dishes[$i][5];
}
else
{
$display.='https://www.pngkey.com/png/detail/430-4307759_knife-fork-and-plate-vector-icon-dishes-png.png';
}
$display.='" style="height: 20vh" class="col-12">
<p class="col-12 p-0" ><i class="fas fa-utensils mr-1"></i>' . $Dishes[$i][0] . '</p>
<i class="col-12 ';
if (($Dishes[$i][3] == "") && ($Dishes[$i][4] == "")) {
$display .= " text-primary ";
} else {
$display .= "text-danger ";
}
$display .= '">';
if ($Dishes[$i][3] != "") {
$display .= $Dishes[$i][2] . " Diable ";
}
if ($Dishes[$i][4] != "") {
$display .= " Dish Diable ";
}
$display .= '</i>
</a>';
}
}
$display.='</div>';
echo $display;
?>
</div>
</div>
<?php
include_once ("../../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
$(document).on("change",".changeDishType",function ()
{
var id=$(this).data("dishtypeid");
var value=$(this).val();
$.ajax({
url:"dishServer.php",
data:{id:id,value:value,option:"changeDishType"},
dataType:"text",
method:"POST",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!="")
{
alert(data);
}
else
{
location.reload();
}
}
});
});
$(document).on("click",".Delele_Dish_Type",function ()
{
var id=$(this).data("dishtypeid");
var value=$(this).val();
$.ajax({
url:"dishServer.php",
data:{value:value,id:id,option:"Delele_Dish_Type"},
dataType:"text",
method:"POST",
beforeSend: function()
{
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!="")
{
alert(data);
}
else
{
location.reload();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
session_start();
if(isset($_COOKIE["userid"]))
{
$_SESSION['userid']= $_COOKIE['userid'];
$_SESSION['isOwner']=$_COOKIE['isOwner'];
$_SESSION['username']=$_COOKIE['username'];
header('location:userDisplay.php');
exit();
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="container "style="background-color:rgba(244,181,7,0.62) " >
<div class="badge-danger col-12 shadow fixed-top " >
<h1 align="center">Welcome to</h1>
<h4 align="center"> New Kashmir Food Center</h4>
</div>
<div class="col-12 card badge-dark" style="margin-top:150px;" >
<h1 align="center">User Login</h1>
<form class="col-12" id="formLogin">
<div class="form-group row">
<label class="col-form-label col-5">UserName</label>
<input type="text" class="col-7 form-control" name="username">
</div>
<div class="form-group row">
<label class="col-form-label col-5">Password</label>
<input type="<PASSWORD>" class="col-7 form-control" name="password">
</div>
<div class="form-group row">
<input id="login" type="button" class="form-control btn btn-success" value="logIN">
</div>
</form>
</div>
<script>
$(document).ready(function () {
$('#login').click(function ()
{
var formdata=new FormData($("#formLogin")[0]);
formdata.append("option","login");
$.ajax({
url:"userServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
location.reload();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-15
* Time: 13:36
*/
session_start();
session_destroy();
header("location:userLogin.php");
exit();
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include ("../../connection/connect.php");
$companyid=$_COOKIE['companyid'];
$hallBranches='';
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<style>
form
{
margin: 5%;
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://thumbs.dreamstime.com/z/wedding-hall-decoration-reception-party-35933352.jpg);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-body text-center" style="opacity: 0.7 ;background: white;">
<h1 class="display-5 "><i class="fas fa-registered"></i> Hall Branch Register</h1>
<p class="lead">Free register Hall branches and also get free software . Book your order easily</p>
<a href="../companyRegister/companyEdit.php " class="col-6 btn btn-info"> <i class="fas fa-city mr-2"></i>Edit Company</a>
</div>
</div>
<form class="card-body ">
<div class="form-group row">
<label class="col-form-label">Hall Branch Name:</label>
<!-- <input name="hallname" class="form-control col-8" type="text">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-place-of-worship"></i></span>
</div>
<input id="hallname" name="hallname" type="text" class="form-control" placeholder="Hall Branch Name">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Hall Type:</label>
<!--<select name="halltype" class="form-control col-8">
<option value="1">Marquee</option>
<option value="2">Hall</option>
<option value="3">Deera /Open area</option>
</select>-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fab fa-accusoft"></i></span>
</div>
<select name="halltype" class="form-control">
<option value="0">Marquee</option>
<option value="1">Hall</option>
<option value="2">Deera /Open area</option>
</select>
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Hall Branch Image:</label>
<!-- <input name="image" class="form-control col-8" type="file">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera-retro"></i></span>
</div>
<input name="image" type="file" class="form-control">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"><i class="fas fa-map-marker-alt"></i> Hall Branch Address</label>
</div>
<div class="form-group row">
<label class="col-form-label ">Maximum Capacity of guests in hall:</label>
<!-- <input name="capacity" class="form-control col-4" type="number">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-users"></i></span>
</div>
<input name="capacity" type="number" class="form-control" placeholder="Maximum Capacity of guests in hall">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">No of Partition in Hall:</label>
<!-- <input name="partition" class="form-control col-4" type="number">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-columns"></i></span>
</div>
<input name="partition" type="number" class="form-control" placeholder="No of Partition in Hall">
</div>
</div>
<div class="form-inline form-group">
<input name="parking" class="form-check-input " type="checkbox">
<label class="form-check-label "><i class="fas fa-parking"></i> Have Your own parking</label>
</div>
<div class="form-group row">
<!-- <input id="cancel" type="button" class="btn btn-danger col-4 form-control" value="cancel">-->
<!-- <input id="submit" type="button" class=" btn btn-success col-4 form-control" value="Submit">-->
<button id="cancel" type="button" class="btn btn-danger col-4 form-control" value="Cancel"><span class="fas fa-window-close "></span>Cancel</button>
<button id="submit" type="button" class=" btn btn-success col-4 form-control" value="Submit"><i class="fas fa-check "></i>Submit</button>
</div>
</form>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$('#submit').click(function ()
{
if($.trim($("#hallname").val()).length==0)
{
alert("hall name must enter");
return false;
}
var formdata = new FormData($("form")[0]);
formdata.append("option", "CreateHall");
formdata.append("companyid",<?php echo $companyid;?>);
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data)
{
if(data!="")
{
alert(data);
return false;
}
else
{
window.history.back();
}
}
});
});
$("#cancel").click(function ()
{
window.history.back();
});
});
</script>
</body>
</html>
<file_sep>-- MySQL Script generated by MySQL Workbench
-- Sat Sep 28 23:47:50 2019
-- Model: New Model Version: 1.0
-- MySQL Workbench Forward Engineering
SET @OLD_UNIQUE_CHECKS=@@UNIQUE_CHECKS, UNIQUE_CHECKS=0;
SET @OLD_FOREIGN_KEY_CHECKS=@@FOREIGN_KEY_CHECKS, FOREIGN_KEY_CHECKS=0;
SET @OLD_SQL_MODE=@@SQL_MODE, SQL_MODE='TRADITIONAL,ALLOW_INVALID_DATES';
-- -----------------------------------------------------
-- Schema mydb
-- -----------------------------------------------------
-- -----------------------------------------------------
-- Schema a111
-- -----------------------------------------------------
-- -----------------------------------------------------
-- Schema a111
-- -----------------------------------------------------
CREATE SCHEMA IF NOT EXISTS `a111` DEFAULT CHARACTER SET utf8mb4 ;
USE `a111` ;
-- -----------------------------------------------------
-- Table `a111`.`person`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`person` ;
CREATE TABLE IF NOT EXISTS `a111`.`person` (
`name` VARCHAR(30) NULL,
`cnic` VARCHAR(30) NULL,
`id` INT(11) NOT NULL AUTO_INCREMENT,
`date` DATE NULL,
`image` TEXT(200) NULL DEFAULT NULL,
PRIMARY KEY (`id`))
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`address`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`address` ;
CREATE TABLE IF NOT EXISTS `a111`.`address` (
`id` INT(11) NOT NULL AUTO_INCREMENT,
`address_city` VARCHAR(50) NULL DEFAULT 'lahore',
`address_town` VARCHAR(50) NULL,
`address_street_no` INT(11) NULL DEFAULT NULL,
`address_house_no` INT(11) NULL DEFAULT NULL,
`person_id` INT(11) NULL,
PRIMARY KEY (`id`),
INDEX `fk_address_person1_idx` (`person_id` ASC),
CONSTRAINT `fk_address_person1`
FOREIGN KEY (`person_id`)
REFERENCES `a111`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`location`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`location` ;
CREATE TABLE IF NOT EXISTS `a111`.`location` (
`id` INT NOT NULL,
`logitude` FLOAT NULL,
`lagitude` FLOAT NULL,
`expire` DATETIME NULL,
PRIMARY KEY (`id`))
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`user`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`user` ;
CREATE TABLE IF NOT EXISTS `a111`.`user` (
`id` INT NOT NULL AUTO_INCREMENT,
`username` VARCHAR(45) NULL,
`password` VARCHAR(30) NULL,
`person_id` INT(11) NOT NULL,
`isExpire` DATETIME NULL DEFAULT NULL,
`isowner` TINYINT NULL DEFAULT 0,
`company_id` INT NULL,
PRIMARY KEY (`id`),
INDEX `fk_user_person1_idx` (`person_id` ASC),
INDEX `fk_user_company1_idx` (`company_id` ASC),
CONSTRAINT `fk_user_person1`
FOREIGN KEY (`person_id`)
REFERENCES `a111`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_user_company1`
FOREIGN KEY (`company_id`)
REFERENCES `a111`.`company` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`company`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`company` ;
CREATE TABLE IF NOT EXISTS `a111`.`company` (
`id` INT NOT NULL AUTO_INCREMENT,
`name` VARCHAR(45) NULL,
`expire` DATETIME NULL,
`user_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_company_user1_idx` (`user_id` ASC),
CONSTRAINT `fk_company_user1`
FOREIGN KEY (`user_id`)
REFERENCES `a111`.`user` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`catering`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`catering` ;
CREATE TABLE IF NOT EXISTS `a111`.`catering` (
`id` INT NOT NULL AUTO_INCREMENT,
`name` VARCHAR(100) NULL,
`expire` DATETIME NULL,
`image` VARCHAR(45) NULL,
`location_id` INT NOT NULL,
`company_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_catering_location1_idx` (`location_id` ASC),
INDEX `fk_catering_company1_idx` (`company_id` ASC),
CONSTRAINT `fk_catering_location1`
FOREIGN KEY (`location_id`)
REFERENCES `a111`.`location` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_catering_company1`
FOREIGN KEY (`company_id`)
REFERENCES `a111`.`company` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`number`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`number` ;
CREATE TABLE IF NOT EXISTS `a111`.`number` (
`number` VARCHAR(30) NULL,
`id` INT(11) NOT NULL AUTO_INCREMENT,
`is_number_active` TINYINT NULL DEFAULT 1,
`person_id` INT(11) NOT NULL,
`catering_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_number_person1_idx` (`person_id` ASC),
INDEX `fk_number_catering1_idx` (`catering_id` ASC),
CONSTRAINT `fk_number_person1`
FOREIGN KEY (`person_id`)
REFERENCES `a111`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_number_catering1`
FOREIGN KEY (`catering_id`)
REFERENCES `a111`.`catering` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`orderTable`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`orderTable` ;
CREATE TABLE IF NOT EXISTS `a111`.`orderTable` (
`id` INT(11) NOT NULL AUTO_INCREMENT,
`total_amount` INT(11) NULL DEFAULT 0,
`order_comments` TEXT NULL DEFAULT NULL,
`total_person` INT NULL,
`is_active` INT NULL DEFAULT 0,
`destination_date` DATE NULL,
`booking_date` DATE NULL,
`destination_time` TIME(6) NULL,
`address_id` INT(11) NULL,
`extre_charges` INT NULL,
`person_id` INT(11) NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_order_address1_idx` (`address_id` ASC),
INDEX `fk_order_person1_idx` (`person_id` ASC),
CONSTRAINT `fk_order_address1`
FOREIGN KEY (`address_id`)
REFERENCES `a111`.`address` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_order_person1`
FOREIGN KEY (`person_id`)
REFERENCES `a111`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`dish_type`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`dish_type` ;
CREATE TABLE IF NOT EXISTS `a111`.`dish_type` (
`id` INT NOT NULL AUTO_INCREMENT,
`name` VARCHAR(45) NULL,
`isExpire` DATETIME NULL DEFAULT NULL,
`catering_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_dish_type_catering1_idx` (`catering_id` ASC),
CONSTRAINT `fk_dish_type_catering1`
FOREIGN KEY (`catering_id`)
REFERENCES `a111`.`catering` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`dish`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`dish` ;
CREATE TABLE IF NOT EXISTS `a111`.`dish` (
`name` VARCHAR(30) NULL,
`id` INT NOT NULL AUTO_INCREMENT,
`image` VARCHAR(300) NULL,
`dish_type_id` INT NOT NULL,
`isExpire` DATETIME NULL DEFAULT NULL,
`catering_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_dish_dish_type1_idx` (`dish_type_id` ASC),
INDEX `fk_dish_catering1_idx` (`catering_id` ASC),
CONSTRAINT `fk_dish_dish_type1`
FOREIGN KEY (`dish_type_id`)
REFERENCES `a111`.`dish_type` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_dish_catering1`
FOREIGN KEY (`catering_id`)
REFERENCES `a111`.`catering` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`attribute`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`attribute` ;
CREATE TABLE IF NOT EXISTS `a111`.`attribute` (
`name` VARCHAR(45) NULL,
`id` INT NOT NULL AUTO_INCREMENT,
`dish_id` INT NOT NULL,
`isExpire` DATETIME NULL DEFAULT NULL,
PRIMARY KEY (`id`),
INDEX `fk_attribute_dish1_idx` (`dish_id` ASC),
CONSTRAINT `fk_attribute_dish1`
FOREIGN KEY (`dish_id`)
REFERENCES `a111`.`dish` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`dish_detail`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`dish_detail` ;
CREATE TABLE IF NOT EXISTS `a111`.`dish_detail` (
`id` INT NOT NULL AUTO_INCREMENT,
`describe` TEXT(300) NULL,
`price` INT NULL,
`expire_date` DATETIME NULL,
`quantity` INT NULL,
`dish_id` INT NOT NULL,
`orderTable_id` INT(11) NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_dish_detail_dish1_idx` (`dish_id` ASC),
INDEX `fk_dish_detail_orderTable1_idx` (`orderTable_id` ASC),
CONSTRAINT `fk_dish_detail_dish1`
FOREIGN KEY (`dish_id`)
REFERENCES `a111`.`dish` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_dish_detail_orderTable1`
FOREIGN KEY (`orderTable_id`)
REFERENCES `a111`.`orderTable` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`attribute_name`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`attribute_name` ;
CREATE TABLE IF NOT EXISTS `a111`.`attribute_name` (
`id` INT NOT NULL AUTO_INCREMENT,
`quantity` INT NULL,
`attribute_id` INT NOT NULL,
`dish_detail_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_attribute_name_attribute1_idx` (`attribute_id` ASC),
INDEX `fk_attribute_name_dish_detail1_idx` (`dish_detail_id` ASC),
CONSTRAINT `fk_attribute_name_attribute1`
FOREIGN KEY (`attribute_id`)
REFERENCES `a111`.`attribute` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_attribute_name_dish_detail1`
FOREIGN KEY (`dish_detail_id`)
REFERENCES `a111`.`dish_detail` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`payment`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`payment` ;
CREATE TABLE IF NOT EXISTS `a111`.`payment` (
`id` INT NOT NULL AUTO_INCREMENT,
`amount` INT NULL,
`nameCustomer` VARCHAR(45) NULL,
`receive` DATETIME NULL,
`personality` TEXT(300) NULL,
`rating` INT NULL,
`IsReturn` TINYINT NULL,
`user_id` INT NOT NULL,
`orderTable_id` INT(11) NOT NULL,
`sendingStatus` INT NULL DEFAULT 0,
PRIMARY KEY (`id`),
INDEX `fk_payment_user1_idx` (`user_id` ASC),
INDEX `fk_payment_orderTable1_idx` (`orderTable_id` ASC),
CONSTRAINT `fk_payment_user1`
FOREIGN KEY (`user_id`)
REFERENCES `a111`.`user` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_payment_orderTable1`
FOREIGN KEY (`orderTable_id`)
REFERENCES `a111`.`orderTable` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`transfer`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`transfer` ;
CREATE TABLE IF NOT EXISTS `a111`.`transfer` (
`id` INT NOT NULL AUTO_INCREMENT,
`Isconfirm` DATETIME NULL,
`senderTimeDate` DATETIME NULL,
`payment_id` INT NOT NULL,
`user_id` INT NOT NULL,
`Isget` TINYINT NULL,
PRIMARY KEY (`id`),
INDEX `fk_transfer_payment1_idx` (`payment_id` ASC),
INDEX `fk_transfer_user1_idx` (`user_id` ASC),
CONSTRAINT `fk_transfer_payment1`
FOREIGN KEY (`payment_id`)
REFERENCES `a111`.`payment` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_transfer_user1`
FOREIGN KEY (`user_id`)
REFERENCES `a111`.`user` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`hall`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`hall` ;
CREATE TABLE IF NOT EXISTS `a111`.`hall` (
`id` INT NOT NULL AUTO_INCREMENT,
`name` VARCHAR(45) NULL,
`min_guests` INT NULL,
`max_guests` INT NULL,
`function_per_Day` VARCHAR(45) NULL,
`noOfPartitions` INT NULL,
`ownParking` TINYINT NULL,
`expire` DATETIME NULL,
`image` TEXT(200) NULL,
`hallType` VARCHAR(45) NULL,
`location_id` INT NOT NULL,
`company_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_hall_location1_idx` (`location_id` ASC),
INDEX `fk_hall_company1_idx` (`company_id` ASC),
CONSTRAINT `fk_hall_location1`
FOREIGN KEY (`location_id`)
REFERENCES `a111`.`location` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_hall_company1`
FOREIGN KEY (`company_id`)
REFERENCES `a111`.`company` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`images`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`images` ;
CREATE TABLE IF NOT EXISTS `a111`.`images` (
`id` INT NOT NULL AUTO_INCREMENT,
`image` TEXT(200) NULL,
`expire` DATETIME NULL,
`catering_id` INT NULL,
`hall_id` INT NULL,
PRIMARY KEY (`id`),
INDEX `fk_images_catering1_idx` (`catering_id` ASC),
INDEX `fk_images_hall1_idx` (`hall_id` ASC),
CONSTRAINT `fk_images_catering1`
FOREIGN KEY (`catering_id`)
REFERENCES `a111`.`catering` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_images_hall1`
FOREIGN KEY (`hall_id`)
REFERENCES `a111`.`hall` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`systemITems`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`systemITems` ;
CREATE TABLE IF NOT EXISTS `a111`.`systemITems` (
`id` INT NOT NULL AUTO_INCREMENT,
`name` VARCHAR(45) NULL,
`images` VARCHAR(200) NULL,
`expire` DATETIME NULL,
PRIMARY KEY (`id`))
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`item`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`item` ;
CREATE TABLE IF NOT EXISTS `a111`.`item` (
`id` INT NOT NULL AUTO_INCREMENT,
`name` VARCHAR(45) NULL,
`image` VARCHAR(200) NULL,
`expire` DATETIME NULL,
`prizeSytem` INT NULL,
`hall_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_item_hall1_idx` (`hall_id` ASC),
CONSTRAINT `fk_item_hall1`
FOREIGN KEY (`hall_id`)
REFERENCES `a111`.`hall` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`hallprice`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`hallprice` ;
CREATE TABLE IF NOT EXISTS `a111`.`hallprice` (
`id` INT NOT NULL AUTO_INCREMENT,
`month` VARCHAR(45) NULL,
`isFood` TINYINT NULL,
`price` INT NULL,
`describe` TEXT(200) NULL,
`dayTime` INT NULL,
`expire` DATETIME NULL,
`hall_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_hallprice_hall1_idx` (`hall_id` ASC),
CONSTRAINT `fk_hallprice_hall1`
FOREIGN KEY (`hall_id`)
REFERENCES `a111`.`hall` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`menu`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`menu` ;
CREATE TABLE IF NOT EXISTS `a111`.`menu` (
`id` INT NOT NULL AUTO_INCREMENT,
`dishname` VARCHAR(45) NULL,
`image` TEXT(100) NULL,
`expire` DATETIME NULL,
`hallprice_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_menu_hallprice1_idx` (`hallprice_id` ASC),
CONSTRAINT `fk_menu_hallprice1`
FOREIGN KEY (`hallprice_id`)
REFERENCES `a111`.`hallprice` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`orderDetail`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`orderDetail` ;
CREATE TABLE IF NOT EXISTS `a111`.`orderDetail` (
`id` INT NOT NULL AUTO_INCREMENT,
`orderTable_id` INT(11) NOT NULL,
`hall_id` INT NULL,
`catering_id` INT NULL,
`isHallOrCatering` TINYINT NULL,
`orderDetailcol` VARCHAR(45) NULL,
`hallprice_id` INT NULL,
PRIMARY KEY (`id`),
INDEX `fk_orderDetail_orderTable1_idx` (`orderTable_id` ASC),
INDEX `fk_orderDetail_hall1_idx` (`hall_id` ASC),
INDEX `fk_orderDetail_catering1_idx` (`catering_id` ASC),
INDEX `fk_orderDetail_hallprice1_idx` (`hallprice_id` ASC),
CONSTRAINT `fk_orderDetail_orderTable1`
FOREIGN KEY (`orderTable_id`)
REFERENCES `a111`.`orderTable` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_orderDetail_hall1`
FOREIGN KEY (`hall_id`)
REFERENCES `a111`.`hall` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_orderDetail_catering1`
FOREIGN KEY (`catering_id`)
REFERENCES `a111`.`catering` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_orderDetail_hallprice1`
FOREIGN KEY (`hallprice_id`)
REFERENCES `a111`.`hallprice` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`order_items`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`order_items` ;
CREATE TABLE IF NOT EXISTS `a111`.`order_items` (
`id` INT NOT NULL AUTO_INCREMENT,
`expire` DATETIME NULL,
`item_id` INT NULL,
`orderDetail_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_order_items_item1_idx` (`item_id` ASC),
INDEX `fk_order_items_orderDetail1_idx` (`orderDetail_id` ASC),
CONSTRAINT `fk_order_items_item1`
FOREIGN KEY (`item_id`)
REFERENCES `a111`.`item` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_order_items_orderDetail1`
FOREIGN KEY (`orderDetail_id`)
REFERENCES `a111`.`orderDetail` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`systemDishType`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`systemDishType` ;
CREATE TABLE IF NOT EXISTS `a111`.`systemDishType` (
`id` INT NOT NULL AUTO_INCREMENT,
`name` VARCHAR(45) NULL,
`isExpire` DATETIME NULL DEFAULT NULL,
PRIMARY KEY (`id`))
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`systemDish`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`systemDish` ;
CREATE TABLE IF NOT EXISTS `a111`.`systemDish` (
`name` VARCHAR(30) NULL,
`id` INT NOT NULL AUTO_INCREMENT,
`image` VARCHAR(300) NULL,
`isExpire` DATETIME NULL DEFAULT NULL,
`systemDishType_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_systemDish_systemDishType1_idx` (`systemDishType_id` ASC),
CONSTRAINT `fk_systemDish_systemDishType1`
FOREIGN KEY (`systemDishType_id`)
REFERENCES `a111`.`systemDishType` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`SystemAttribute`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `a111`.`SystemAttribute` ;
CREATE TABLE IF NOT EXISTS `a111`.`SystemAttribute` (
`name` VARCHAR(45) NULL,
`id` INT NOT NULL AUTO_INCREMENT,
`isExpire` DATETIME NULL DEFAULT NULL,
`systemDish_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_SystemAttribute_systemDish1_idx` (`systemDish_id` ASC),
CONSTRAINT `fk_SystemAttribute_systemDish1`
FOREIGN KEY (`systemDish_id`)
REFERENCES `a111`.`systemDish` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
SET SQL_MODE=@OLD_SQL_MODE;
SET FOREIGN_KEY_CHECKS=@OLD_FOREIGN_KEY_CHECKS;
SET UNIQUE_CHECKS=@OLD_UNIQUE_CHECKS;
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include ("../../connection/connect.php");
$cateringid=$_POST['cateringid']=1;
$sql='SELECT `name`, `expire`, `image`, `location_id` FROM `catering` WHERE id='.$cateringid.'';
$cateringdetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0;
padding: 0;
}
</style>
</head>
<body>
<h1 align="center">Setting OF Catering</h1>
<img src="
<?php
if(file_exists("../".$cateringdetail[0][2]) &&($cateringdetail[0][2]!=""))
{
echo "../".$cateringdetail[0][2];
}
else
{
echo "../../gmail.png";
}
?>
" class="rounded mx-auto d-block m-4" alt="..." style="height: 30vh">
<form id="formcatering">
<input type="number" hidden name="cateringid" value="<?php echo $cateringid; ?>">
<input type="text" hidden name="previousimage" value="<?php echo $cateringdetail[0][2]; ?>">
<div class="form-group row">
<label class="col-form-label col-4">Catering Branch Name:</label>
<input name="cateringname" class="form-control col-8" type="text" value="<?php echo $cateringdetail[0][0]; ?>">
</div>
<div class="form-group row">
<label class="col-form-label col-4">Catering Branch Image:</label>
<input name="image" class="form-control col-8" type="file">
</div>
<div class="form-group row">
<label class="col-form-label col-4">Catering Branch Address</label>
</div>
<div class="form-group row col-12 mb-5">
<input id="expirecatering" type="button" class="rounded mx-auto d-block btn btn-outline-danger col-5 " value="Expire catering">
<input id="submiteditcatering" type="button" class="rounded mx-auto d-block btn btn-primary col-5 " value="Submit">
</div>
</form>
<script>
$(document).ready(function ()
{
$("#submiteditcatering").click(function () {
var formdata = new FormData($("#formcatering")[0]);
formdata.append("option", "cateringedit");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data) {
if (data != '')
{
alert(data);
return false;
} else
{
location.reload();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-15
* Time: 11:41
*/
header("location:Catering/user/userLogin.php");
exit();
//echo '<a href="user/userLogin.php">hello world</a>';
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../connection/connect.php");
if(!isset($_COOKIE['companyid']))
{
header("location:../../user/userLogin.php");
}
if(!isset($_GET['catering']))
{
header("location:../companyRegister/companyEdit.php");
}
$encoded=$_GET['catering'];
$id=base64url_decode($encoded);
if((!is_numeric($id))||$id=="")
{
header("location:../companyRegister/companyEdit.php");
}
$cateringid=$id;
$sql='SELECT `name`, `expire`, `image`, `location_id` FROM `catering` WHERE id='.$cateringid.'';
$cateringdetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow text-center" style="background-image: url(<?php
if((file_exists('../../images/catering/'.$cateringdetail[0][2])) &&($cateringdetail[0][2]!=""))
{
echo "'../../images/catering/".$cateringdetail[0][2]."'";
}
else
{
echo "https://www.liberaldictionary.com/wp-content/uploads/2019/02/cater-4956.jpg";
}
?>
);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-body " style="opacity: 0.7 ;background: white;">
<h1 class="display-5 text-center"><i class="fas fa-images fa-3x"></i><?php echo $cateringdetail[0][0];?> Gallery</h1>
<p class="lead">View and upload picture of dishes </p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php" class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container">
<h1 class="font-weight-light text-lg-left mt-4 mb-3">Gallery</h1>
<form action="" method="POST" enctype="multipart/form-data" class="form-inline">
<input type="file" name="userfile[]" value="" multiple="" class="col-8 btn btn-light">
<input type="submit" name="submit" value="Upload" class="btn btn-success col-4">
</form>
<?php
if(isset($_FILES['userfile']))
{
$file_array=reArray($_FILES['userfile']);
$Distination='';
for ($i=0;$i<count($file_array);$i++)
{
$Distination= '../../images/catering/'.$file_array[$i]['name'];
$error=MutipleUploadFile($file_array[$i],$Distination);
if(count($error)>0)
{
echo '<h4 class="badge-danger">'.$file_array[$i]['name'].'.'.$error[0].'</h4>';
}
else
{
$sql='INSERT INTO `images`(`id`, `image`, `expire`, `catering_id`, `hall_id`) VALUES (NULL,"'.$Distination.'",NULL,'.$cateringid.',NULL)';
querySend($sql);
}
}
unset($_FILES['userfile']);
}
?>
<hr class="mt-3 mb-5 border-white">
<div class="row text-center text-lg-left">
<?php
$sql='SELECT `id`, `image` FROM `images` WHERE catering_id='.$cateringid.'' ;
echo showGallery($sql);
?>
</div>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
});
</script>
</body>
</html><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 14:15
*/
//
//if(!isset($_GET["user_id"]) && !isset($_GET["order"]))
//{
// echo 'orderDetail id and user id is not GET';
// exit();
//}
include_once ("../connection/connect.php");
$userId=$_COOKIE['userid'];
$orderDetail_id=$_SESSION['order'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<style>
</style>
</head>
<body >
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://insidesmallbusiness.com.au/wp-content/uploads/2018/12/bigstock-204968347.jpg);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-body text-center" style="opacity: 0.7 ;background: #fdfdff;">
<h3 ><i class="far fa-money-bill-alt fa-1x mr-3"></i>Get payment from customer </h3>
</div>
</div>
<div class="row justify-content-center col-12" style="margin-top: -60px">
<div class="card text-center card-header">
<img src="<?php
if($_GET['image']=="")
{
echo 'https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
else
{
echo $_GET['image'];
}
?> " style="height: 20vh;" class="figure-img rounded-circle" alt="image is not set">
<h5 ><?php
echo $_GET['name'];
?></h5>
<label >Order ID:<?php
echo $orderDetail_id;
?></label>
</div>
</div>
<div class="container">
<form class="col-12 shadow card-body" id="from2">
<input hidden name="user_id" value="<?php
echo $userId;
?>">
<input hidden name="orderDetail_id" value="<?php
echo $orderDetail_id;
?>">
<div class="form-group row">
<label class="col-form-label">Name</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user"></i></span>
</div>
<input type="text" name="name" class="form-control" placeholder="person name etc Ali,Hassan,....">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Amount</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-money-bill-alt"></i></span>
</div>
<input type="number" name="Amount" class="form-control" placeholder="amount total etc 1200xxx">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Status amount</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-exchange-alt"></i></span>
</div>
<select name="status" class="custom-select">
<option value="0">Get Amount </option>
<option value="1">Return Amount</option>
</select>
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Rating Customer</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-star"></i></span>
</div>
<span id="showRange" class="form-control col-2"></span>
<input id="rangeInput" step="1" type="range" max="5" min="1" value="3" name="rating" class="col-6">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">personality</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-comments"></i></span>
</div>
<textarea type="text" name="personality" class="form-control" placeholder="comment on customer personality"></textarea>
</div>
</div>
<div class="form-group row justify-content-center m-auto">
<a href="/Catering/order/PreviewOrder.php?order=<?php echo $orderDetail_id;?>" class="form-control col-4 btn-danger btn"><i class="fas fa-times-circle"></i>Cancel</a>
<button id="submitBtnfrom" type="submit" class="form-control col-4 btn-primary btn"><i class="fas fa-check "></i>Submit</button>
</div>
</form>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$('#showRange').html($("#rangeInput").val())
$("#rangeInput").change(function () {
$('#showRange').html($("#rangeInput").val());
});
$("#submitBtnfrom").click(function (e) {
e.preventDefault();
var formdata=new FormData($("#from2")[0]);
formdata.append("option","GetPayment");
$.ajax({
url:"paymentServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
});
</script>
</body>
</html>
<file_sep>
<div class="container">
<h1 class="font-weight-light mt-4 mb-0">Comments</h1>
<hr class="mt-2 mb-3">
<div class="row bootstrap snippets">
<div class="col-md-12 col-md-offset-2 col-sm-12 m-auto">
<div class="comment-wrapper">
<div class="panel panel-info ">
<form id="commentform">
<?php
echo '<input hidden type="number" name="hallid" value="'.$hallid.'">';
?>
<div class="panel-body">
<textarea name="comment" class="form-control" placeholder="write a comment..." rows="3"></textarea>
<br>
<div class="input-group mb-2">
<div class="input-group-prepend">
<div class="input-group-text"><i class="fas fa-comments"></i></div>
</div>
<input name="email" type="email" class="form-control " placeholder="Email">
</div>
<button id="btncoment" type="button" class="btn btn-info pull-right float-right col-5">Post</button>
</form>
<?php
$display='';
$sql='SELECT `hall_id`, `catering_id`, `id`, `comment`, `email`, `datetime`, `expire` FROM `comments` WHERE (hall_id='.$hallid.')&&(ISNULL(expire))';
$commentresult=queryReceive($sql);
for ($i=0;$i<count($commentresult);$i++)
{
$display.='
<div class="clearfix"></div>
<hr>
<ul class="media-list text-white">
<li class="media">
<a href="#" class="pull-left">
<img src="https://bootdey.com/img/Content/user_1.jpg" alt="" class="img-circle">
</a>
<div class="media-body">
<span class="text-muted pull-right">
<small class="text-dark">'.$commentresult[$i][5].'</small>
</span>
<strong class="text-warning">@'.$commentresult[$i][4].'</strong>
<p>
'.$commentresult[$i][3].'
</p>
</div>
</li>
</ul>
';
}
echo $display;
?>
<!--
<div class="clearfix"></div>
<hr>
<ul class="media-list">
<li class="media">
<a href="#" class="pull-left">
<img src="https://bootdey.com/img/Content/user_1.jpg" alt="" class="img-circle">
</a>
<div class="media-body">
<span class="text-muted pull-right">
<small class="text-muted">30 min ago</small>
</span>
<strong class="text-success">@MartinoMont</strong>
<p>
Lorem ipsum dolor sit amet, consectetur adipiscing elit.
Lorem ipsum dolor sit amet,
</p>
</div>
</li>
</ul>-->
</div>
</div>
</div>
</div>
</div>
</div>
<script>
$(document).ready(function () {
$("#btncoment").click(function ()
{
var formdata = new FormData($("#commentform")[0]);
formdata.append("option", "commentAdd");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data)
{
location.reload();
}
});
}) ;
});
</script>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include ("../../connection/connect.php");
$hallid=$_GET['hallid'];
$orderid=$_GET['order'];
$sql='SELECT `id`, `hall_id`, `catering_id`, (SELECT hp.isFood from hallprice as hp WHERE hp.id=orderDetail.hallprice_id),
`user_id`, `sheftCatering`, `sheftHall`, `sheftCateringUser`,
`sheftHallUser`, `address_id`, `person_id`, `total_amount`,
`total_person`, `status_hall`, `destination_date`,
`booking_date`, `destination_time`, `status_catering`,
`notice`,`describe`,(SELECT hp.describe from hallprice as hp WHERE hp.id=orderDetail.hallprice_id),hallprice_id,(SELECT hp.price from hallprice as hp WHERE hp.id=orderDetail.hallprice_id) FROM `orderDetail` WHERE id='.$orderid.'';
$detailorder=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="container" >
<h1 align="center">Order Create of Hall</h1>
<form class="form">
<div class="form-group row">
<label class="col-form-label col-4">No of Guests</label>
<input name="guests" type="number" class="form-control col-8" value="<?php echo $detailorder[0][12]; ?>">
</div>
<div class="form-group row">
<label class="col-form-label col-4">Date</label>
<input id="date" name="date" type="date" class="checkpackage form-control col-8" value="<?php echo $detailorder[0][14]; ?>">
</div>
<div class="form-group row">
<label class="col-form-label col-4">Time</label>
<select id="time" name="time" class="checkpackage form-control col-8">
<?php
///////set time
if($detailorder[0][16]=="09:00:00")
{
//morning
echo '
<option value="Morning">Morning</option>
<option value="Afternoon">Afternoon</option>
<option value="Evening">Evening</option>';
}
else if($detailorder[0][16]=="12:00:00")
{
//afternoon
echo '
<option value="Afternoon">Afternoon</option>
<option value="Morning">Morning</option>
<option value="Evening">Evening</option>';
}
else
{
//evening
echo '
<option value="Evening">Evening</option>
<option value="Morning">Morning</option>
<option value="Afternoon">Afternoon</option>';
}
?>
</select>
</div>
<div class="form-group row">
<label class="col-form-label col-4">Per Head With</label>
<select id="perheadwith" name="perheadwith" class="checkpackage form-control col-8">
<?php
if($detailorder[0][3]==0)
{
// only seating
echo '
<option value="0">Only seating</option>
<option value="1">Food + Seating</option>';
}
else
{
//food and seating
echo '
<option value="1">Food + Seating</option>
<option value="0">Only seating</option>';
}
?>
</select>
</div>
<div id="groupofpackages" class="col-12 alert-warning shadow">
</div>
<div id="selectmenu" class="alert-info m-2 form-group row shadow" >
</div>
<div class="form-group row">
<label class="col-form-label col-4">Describe /Comments</label>
<textarea name="describe" class="form-control col-8"><?php echo $detailorder[0][19]; ?></textarea>
</div>
<div class="form-group row">
<label class="col-form-label col-4">Total amount:</label>
<input name="totalamount" type="number" class="form-control col-8" value="<?php echo $detailorder[0][11]; ?>">
</div>
<?php
$status=array("Running","Deliever","Cancel","Clear");
$display='
<div class="form-group row">
<label class="col-form-label col-4">Order status</label>
<select name="orderStatus" class=" form-control col-8">
<option value="'.$detailorder[0][13].'">'.$detailorder[0][13].'</option>';
for($i=0;$i<count($status);$i++)
{
if($status[$i]!=$detailorder[0][13])
{
$display.='<option value="'.$status[$i].'">'.$status[$i].'</option>';
}
}
$display.=' </select>
</div>';
echo $display;
?>
<div class="form-group row">
<label class="col-form-label col-4">Booked date</label>
<input readonly type="date" class="form-control col-8" value="<?php echo $detailorder[0][15]; ?>">
</div>
<div class="form-group row">
<input id="cancel" type="button" class=" col-4 btn btn-danger" value="Cancel">
<input id="submitform" type="button" class=" col-4 btn btn-success" value="Save">
</div>
</form>
<script>
$(document).ready(function () {
$("#cancel").click(function ()
{
window.history.back();
});
function checkpackage(date, time, perheadwith)
{
if ((date != "") && (time != "") && (perheadwith != "")) {
return 1;
}
return 0;
}
$(".checkpackage").change(function () {
var date = $("#date").val();
var month = new Date(date).getMonth();
var time = $("#time").val();
var perheadwith = $("#perheadwith").val();
$("#selectmenu").html("");
if (!checkpackage(date, time, perheadwith))
{
return false;
}
var formdata = new FormData;
formdata.append("date",date);
formdata.append("month", month);
formdata.append("time", time);
formdata.append("perheadwith", perheadwith);
formdata.append("option", "checkpackages1");
formdata.append("hallid",<?php echo $hallid;?>);
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data)
{
$("#groupofpackages").html(data);
}
});
});
function menushow(packageid,describe)
{
var formdata = new FormData;
formdata.append("packageid", packageid);
formdata.append("option", "viewmenu");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data)
{
$("#selectmenu").html(data);
$("#selectmenu").append("<h3 align='center' class='col-12'>Menu Description</h3><p class='col-12'>"+describe+"</p>");
}
});
}
menushow(<?php echo $detailorder[0][21]; ?>,"<?php echo $detailorder[0][20]; ?>"+"<span class='btn-danger'> .... with price is <?php echo $detailorder[0][22]; ?></span>");
$(document).on("click","input[type=radio]",function ()
{
var packageid=$("input[name='defaultExampleRadios']:checked").val();
if($("#perheadwith").val()!="1")
return false;
var describe=$("#describe"+packageid).val();
menushow(packageid,describe);
});
var packageid=<?php echo $detailorder[0][21]; ?>;
$("#submitform").click(function ()
{
var date = $("#date").val();
var time = $("#time").val();
var perheadwith = $("#perheadwith").val();
if (!checkpackage(date, time, perheadwith))
{
alert("Please select Date,Time and Per Head");
return false;
}
if($(".checkclasshas")[0])
{
packageid=$("input[name='defaultExampleRadios']:checked").val();
if(!packageid)
{
alert("Please select Package From Package Detail");
return false;
}
}
var formdata = new FormData($("form")[0]);
formdata.append("perheadwith",perheadwith);
formdata.append("packageid", packageid);
formdata.append("order",<?php echo $orderid; ?>);
formdata.append("option", "Edithallorder");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data)
{
if(data!="")
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-27
* Time: 17:29
*/
include_once ("../../connection/connect.php");
if(!isset($_COOKIE['companyid']))
{
header("location:../../user/userLogin.php");
}
$companyid=$_COOKIE['companyid'];
$CateringBranches=1;
$sql='SELECT name,id FROM systemDishType WHERE ISNULL(isExpire)';
$dishType=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<style>
form
{
margin: 5%;
}
.jumbotron
{
background-color: rgba(253, 253, 255, 0.95);
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://www.hnfc.com.my/data1/images/slide2.jpg);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-body " style="opacity: 0.7 ;background: white;">
<h1 class="display-5 text-center"><i class="fas fa-registered"></i> Catering Branches</h1>
<p class="lead">Free register catering branches and also get free software . Book your order easily</p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php " class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<?php
$H=0;
for($M=0;$M<$CateringBranches;$M++)
{
echo '<div class=" jumbotron container card-body border shadow mb-4" id="removeform'.$M.'">';
$M++;
echo '<h1 align="center"><i class="fas fa-utensils"></i> <i class="fas fa-registered"></i>Catering Registeration '.$M.'</h1>';
$M--;
echo '<form id="formsubmit'.$M.'" >';
?>
<div class="form-group row ">
<label class="col-form-label">Catering Branch name:</label>
<!-- <input name="namecatering" type="text" class="form-control col-8">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-utensils"></i></span>
</div>
<input placeholder="Catering Branch name" name="namecatering" type="text" class="form-control">
</div>
</div>
<div class="form-group row">
<label class="col-form-label ">Catering Branch Image:</label>
<!-- <input name="image" type="file" class="form-control col-8">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input name="image" type="file" class="form-control">
</div>
</div>
<div class="col-5">
<p> Map of address</p>
</div>
<h3 align="center"><i class="far fa-hand-pointer"></i> Select Dishes</h3>
<div class="form-group row">
<?php
$display = '';
for ($i = 0; $i < count($dishType); $i++) {
$display = '<h1 align="center" class="col-12">' . $dishType[$i][0] . '</h1>';
$sql = 'SELECT `name`, `id`, `image` FROM `systemDish` WHERE ISNULL(isExpire)AND
systemDishType_id=' . $dishType[$i][1] . '';
$dishDetail = queryReceive($sql);
for ($j = 0; $j < count($dishDetail); $j++) {
$display .= '
<div class="col-4 shadow border btn-outline-warning m-2">
<input id="dishtypename' .$H. '" hidden type="text" name="dishtypename[]" value="' . $dishType[$i][0] . '">
<input id="dishid' .$H. '" hidden type="number" name="dishid[]" value="' . $dishDetail[$j][1] . '">
<input id="dishname' . $H . '" name="dishname[]" hidden value="' . $dishDetail[$j][0] . '">
<input id="image' . $H. '" name="image[]" hidden value="' . $dishDetail[$j][2] . '">
<img class="col-12" src="' . $dishDetail[$j][2] . '" style="height: 20vh" >
<p class="col-12"> ' . $dishDetail[$j][0] . '</p>
<input data-dishshow="' .$H. '" type="button" class="selectdish form-control col-12 btn-danger" value="Remove">
</div>';
$H++;
}
}
echo $display;
?>
</div>
<div class="form-group row mt-3">
<button data-formid="<?php echo $M; ?>" type="button" class="cancelform btn btn-outline-danger col-5 form-control " value="cancel" ><span class="fas fa-window-close "></span> Cancel</button>
<button data-formid="<?php echo $M; ?>" type="button" class="submitform btn btn-primary col-5 form-control" value="submit"><i class="fas fa-check "></i> Submit</button>
</div>
</form>
<?php
echo '</div>';
}
?>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
var NoCatering="<?php echo $CateringBranches;?>";
$(document).on("click",".selectdish",function ()
{
var id=$(this).data("dishshow");
var value=$(this).val();
if(value=="Remove")
{
$("#dishtypename"+id).attr("name","");
$("#dishid"+id).attr("name","");
$("#dishname"+id).attr("name","");
$("#image"+id).attr("name","");
$(this).val("Select");
$(this).removeClass("btn-danger");
$(this).addClass("btn-success");
}
else
{
$("#dishtypename"+id).attr("name","dishtypename[]");
$("#dishid"+id).attr("name","dishid[]");
$("#dishname"+id).attr("name","dishname[]");
$("#image"+id).attr("name","image[]");
$(this).val("Remove");
$(this).removeClass("btn-success");
$(this).addClass("btn-danger");
}
});
$(".submitform").click(function () {
var formid=$(this).data("formid");
var formdata=new FormData($("#formsubmit"+formid)[0]);
formdata.append("option","createCatering");
formdata.append("companyid",<?php echo $companyid;?>);
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!="")
{
alert(data);
return false;
}
else
{
window.history.back();
}
}
});
});
$(".cancelform").click(function ()
{
window.history.back();
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 23:30
*/
include_once ("../connection/connect.php");
$userId=$_GET['user_id'];
$paymentId=$_GET['payment'];
$orderid=$_GET['order'];
$sql='SELECT `id`, `amount`, `nameCustomer`, `receive`, `IsReturn`,`sendingStatus` FROM `payment` WHERE id='.$paymentId.'';
$paymentDetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container" style="margin-top:180px">
<div class="col-12 shadow card">
<h1 align="center">Send payment To User</h1>
<div class="form-group row">
<label class="col-4 col-form-label"> User </label>
<select id="userIdlabel" class="col-8">
<option value="none">None</option>
<?php
$sql='SELECT id, username FROM user WHERE id !='.$userId.' ';
$userDetail=queryReceive($sql);
for($y=0;$y<count($userDetail);$y++)
{
echo '<option value='.$userDetail[$y][0].'>'.$userDetail[$y][1].'</option>';
}
?>
</select>
</div>
<div class="form-group row">
<label class="col-4 col-form-label"> payment ID</label>
<input readonly value="<?php echo $paymentDetail[0][0]; ?>" id="paymentId" class="col-8 form-control">
</div>
<div class="form-group row">
<label class="col-4 col-form-label"> Amount</label>
<label class="col-8 col-form-label"> <?php
echo $paymentDetail[0][1];
?></label>
</div>
<div class="form-group row">
<label class="col-4 col-form-label"> customer Name</label>
<label class="col-8 col-form-label"> <?php
echo $paymentDetail[0][2];
?></label>
</div>
<div class="form-group row">
<label class="col-4 col-form-label"> Receive Date</label>
<label class="col-8 col-form-label"> <?php
echo $paymentDetail[0][3];
?></label>
</div>
<div class="form-group row">
<label class="col-4 col-form-label"> payment Status</label>
<label class="col-8 col-form-label"> <?php
if($paymentDetail[0][4]==0)
{
echo "Get amount to customer";
}
else
{
echo "return amount to customer";
}
?></label>
</div>
<div class="form-group row">
<a href="/payment/transferPayment.php?order=<?php echo $orderid; ?>&user_id=<?php echo $userId;?> " class="col-6 btn btn-danger "> Cancel</a>
<input id="paymentsend" type="button" class="col-6 btn btn-success" value="<?php
if($paymentDetail[0][5]==0)
{
echo "Send";
}
else if ($paymentDetail[0][5]==1)
{
echo "Confirming";
}
else
{
echo "not part of this";
}
?>">
</div>
</div>
</div>
<script>
//window.history.back();
$(document).ready(function () {
$("#paymentsend") .click(function () {
var btnsender=$(this).val();
if(btnsender=='Send')
{
var userID=$("#userIdlabel").val();
if(userID=='none')
{
alert("please select User");
return false;
}
var paymentId=$("#paymentId").val();
$.ajax({
url:"paymentServer.php",
data:{useid:userID,paymentId:paymentId,option:"paymentsend"} ,
dataType:"text",
method:"POST",
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.location.href="/payment/transferPayment.php?order=<?php echo $orderid;?>&user_id=<?php echo $userId;?>";
}
}
});
}
else if(btnsender=='Confirming')
{
alert("your request has been sent to the next user so please wait for it");
window.location.href="/payment/transferPayment.php?order=<?php echo $orderid; ?>&user_id=<?php echo $userId;?>";
}
});
});
</script>
</body>
</html>
<file_sep><?php
include_once ("../../connection/connect.php");
$hallid=$_GET['hallid']=2;
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
*{
margin:0;
padding:0;
}
</style>
</head>
<body class="container" style="width: 100%;">
<h1 align="center">Hall information</h1>
<h3 align="center">Hall Branch Name:</h3>
<h4 align="center">Food+Seating price</h4>
<?php
$daytimearray=array("Morning","Afternoon","Evening");
for ($k=0;$k<count($daytimearray);$k++)
{
?>
<div class="shadow card p-2 mb-4">
<h2 align="center"><?php echo $daytimearray[$k]; ?></h2>
<table class="table table-bordered table-striped table-danger " style="width: 200%">
<thead>
<tr>
<th scope="col">
Month
</th>
<th scope="col">
Add New Pakages
</th>
</tr>
</thead>
<tbody>
<?php
$display='';
$monthsArray = array('January', 'February', 'March', 'April', 'May', 'June', 'July', 'August', 'September', 'October', 'November', 'December');
for ($m = 0; $m < count($monthsArray); $m++)
{
$display.='
<tr>
<td>
'.$monthsArray[$m].'
</td>
<td>
<a href="addnewpackage.php?hallid='.$hallid.'&month='.$monthsArray[$m].'&daytime='.$daytimearray[$k].'" class="btn btn-success">Add
New Pakages</a>
</td>';
$sql='SELECT `id`,`expire`, `package_name` FROM `hallprice` WHERE (hall_id='.$hallid.')
AND (isFood=1) AND (dayTime="'.$daytimearray[$k].'") AND (month="'.$monthsArray[$m].'")';
$allpackages=queryReceive($sql);
for ($g = 0; $g < count($allpackages); $g++)
{
$display.='<td>
<a href="#packageid='.$allpackages[$g][0].'" class="btn btn-primary w-100">'.$allpackages[$g][2].' ';
if($allpackages[$g][1]!=NULL)
{
$display.= " Expire";
}
$display.='</a>
</td>';
}
$display.='</tr>';
}
echo $display;
?>
</tbody>
</table>
</div>
<?php
}
?>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 14:15
*/
include_once ("../connection/connect.php");
$userId='';
$orderDetail_id="";
if(!isset($_GET['option']))
{
$userId = $_GET['user_id'];
$orderDetail_id = $_GET['order'];
}
$userId = $_SESSION['userid'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container" style="margin-top:150px">
<div id="from3">
<h1 align="center">your payments Receive Requests</h1>
<?php
if(!isset($_GET['option']))
{
echo '
<a class="btn-success form-control col-4 " href="/Catering/order/PreviewOrder.php?order='.$orderDetail_id.'"> <- Preview Order</a>';
}
else
{
echo '
<a class="btn-success form-control col-4 " href="/Catering/user/userDisplay.php"> <- Preview Order</a>';
}
?>
<div class="form-group row border">
<label class="font-weight-bold col-2 col-form-label">ID</label>
<label class="font-weight-bold col-4 col-form-label">User</label>
<label class="font-weight-bold col-4 col-form-label">Send Date</label>
<label class="font-weight-bold col-2 col-form-label">View</label>
</div>
<?php
if(!isset($_GET['option']))
{
$sql = 'SELECT py.id,(SELECT u.username FROM user as u WHERE u.id=py.user_id) as username,py.amount,py.nameCustomer,py.IsReturn,t.senderTimeDate,py.receive,t.id,py.sendingStatus FROM orderDetail as ot INNER join payment as py on ot.id=py.orderDetail_id INNER join transfer as t on py.id=t.payment_id where (ot.id=' . $orderDetail_id . ') AND (t.user_id=' . $userId . ')AND (py.sendingStatus in (1,2))
';
}
else
{
//userDisplay
$sql = 'SELECT py.id,(SELECT u.username FROM user as u WHERE u.id=py.user_id) as username,py.amount,py.nameCustomer,py.IsReturn,t.senderTimeDate,py.receive,t.id,py.sendingStatus FROM orderDetail as ot INNER join payment as py on ot.id=py.orderDetail_id INNER join transfer as t on py.id=t.payment_id where (t.user_id=' . $userId . ') AND (py.sendingStatus in (1,2))
';
}
$paymentDetail=queryReceive($sql);
$displayDetailOfPayment='';
for($l=0;$l<count($paymentDetail);$l++)
{
$displayDetailOfPayment= '<div class="form-group row border">
<label class="col-2 col-form-label">'.$paymentDetail[$l][0].'</label>
<label class="col-4 col-form-label">'.$paymentDetail[$l][1].'</label>
<label class="col-4 col-form-label">'.$paymentDetail[$l][5].'</label>
<input type="button" data-formid="formDetail'.$l.'" class="showDetail col-2 form-control btn-primary" value="Detail">
</div>
<form class="allforms col-12 card shadow " id="formDetail'.$l.'" style="background-color:gainsboro;display: none">
<div class="form-group row">
<label class="col-4 col-form-label">payment id</label>
<label class="col-6 col-form-label">'.$paymentDetail[$l][0].'</label>
</div>
<div class="form-group row">
<label class="col-4 col-form-label">User Name</label>
<label class="col-6 col-form-label">'.$paymentDetail[$l][1].'</label>
</div>
<div class="form-group row">
<label class="col-4 col-form-label">Amount</label>
<label class="col-6 col-form-label">'.$paymentDetail[$l][2].'</label>
</div>
<div class="form-group row">
<label class="col-4 col-form-label">Customer name</label>
<label class="col-6 col-form-label">'.$paymentDetail[$l][3].'</label>
</div>
<div class="form-group row">
<label class="col-4 col-form-label">payment Status</label>
<label class="col-6 col-form-label">';
if($paymentDetail[$l][4]==0)
{
$displayDetailOfPayment.= "Get amount from customer";
}
else
{
$displayDetailOfPayment.= "return amount to customer";
}
$displayDetailOfPayment.='</label>
</div>
<div class="form-group row">
<label class="col-4 col-form-label">User Get amount Date</label>
<label class="col-6 col-form-label">'.$paymentDetail[$l][6].'</label>
</div>
<div class="form-group row">
<label class="col-4 col-form-label">User senting amount Date</label>
<label class="col-6 col-form-label">'.$paymentDetail[$l][5].'</label>
</div>
<div class="form-group row">';
if($paymentDetail[$l][8]==1)
{
$displayDetailOfPayment.= '<input data-paymentid="'.$paymentDetail[$l][0].'" data-tranferid="'.$paymentDetail[$l][7].'" type="button" class="configration col-6 form-control btn btn-danger" value="unconfirm">
<input data-paymentid="'.$paymentDetail[$l][0].'" data-tranferid="'.$paymentDetail[$l][7].'" type="button" class="configration col-6 form-control btn btn-success" value="confirm">';
}
else if($paymentDetail[$l][8]==2)
{
$displayDetailOfPayment.='<input type="button" class="confirmed btn btn-info col-6" value="confirmed">';
}
$displayDetailOfPayment.='</div>
</form>
';
}
echo $displayDetailOfPayment;
?>
</div>
</div>
<script>
$(document).ready(function () {
var previous='';
$('.showDetail').click(function ()
{
var formid=$(this).data("formid");
var value=$(this).val();
if((previous!=formid)&& (previous!=''))
{
$("#"+previous).val("Detail");
$("#"+previous).hide('slow');
}
previous=formid;
if(value=="Detail")
{
$(this).val("preview");
$("#"+formid).show('slow');
}
else if(value=="preview")
{
$(this).val("Detail");
$("#"+formid).hide('slow');
}
});
$(".configration").click(function ()
{
var tranferid=$(this).data("tranferid");
var paymentid=$(this).data("paymentid");
var value=$(this).val();
$.ajax({
url:"paymentServer.php",
data:{paymentid:paymentid,value:value,tranferid:tranferid,option:"paymentconfigration"} ,
dataType:"text",
method:"POST",
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
location.reload(true);
}
}
});
});
$(".confirmed").click(function () {
alert("The payment has been confirmed by you");
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-03
* Time: 17:20
*/
include_once ("../connection/connect.php");
if(isset($_POST['option']))
{
if($_POST['option']=="customerCreate")
{
$name = trim($_POST['name']);
$numberArray = $_POST['number'];
$cnic = $_POST['cnic'];
$city = $_POST['city'];
$area = $_POST['area'];
$streetNo = $_POST['streetNo'];
$houseNo = $_POST['houseNo'];
$date = date('Y-m-d');
$sql = 'INSERT INTO `person`(`name`, `cnic`, `id`, `date`) VALUES ("' . $name . '","' . $cnic . '",NULL,"' . $date . '")';
querySend($sql);
$last_id = mysqli_insert_id($connect);
$sql='INSERT INTO `address`(`id`, `address_street_no`, `address_house_no`, `person_id`, `address_city`, `address_town`) VALUES (NULL,"'.$streetNo.'","'.$houseNo.'",'.$last_id.',"'.$city.'","'.$area.'")';
querySend($sql);
for ($i = 0; $i < count($numberArray); $i++) {
$sql='INSERT INTO `number`(`number`, `id`, `is_number_active`, `person_id`) VALUES ("'.$numberArray[$i].'",NULL,1,'.$last_id.')';
querySend($sql);
}
$customerId = $last_id;
echo json_decode($customerId);
}
else if($_POST['option']=="customerExist")
{
$value=$_POST['value'];
$sql='SELECT n.person_id FROM number as n WHERE n.number="'.$value.'"';
$customerexist=queryReceive($sql);
if(count($customerexist)>0)
{
echo $customerexist[0][0];
}
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-07
* Time: 11:31
*/
$orderId=$_GET['order'];
include_once ("../connection/connect.php");
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body>
<div class="container" style="margin-top:150px">
<h4 align="center"> Selected Dishes / items Detail</h4>
<?php
$sql="SELECT DISTINCT ot.id, (SELECT p.name FROM person as p WHERE p.id=ot.person_id), (SELECT sum(py.amount) FROM payment as py WHERE (py.IsReturn=0)AND(py.orderDetail_id=ot.id)) ,ot.id,ot.total_amount, (SELECT SUM(dd.price*dd.quantity) FROM dish_detail as dd WHERE dd.orderDetail_id=ot.id) FROM orderDetail as ot LEFT join payment as py on ot.id=py.orderDetail_id WHERE ot.id=".$orderId."";
$details=queryReceive($sql);
echo '
<div class="col-12 shadow card mb-3">
<div class="form-group row">
<label class="col-6 form-check-label">order Id </label>
<label class="col-6 form-check-label"> '.$details[0][0].'</label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label">customer name </label>
<label class="col-6 form-check-label">'.$details[0][1].' </label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label"> received amount</label>
<label class="col-6 form-check-label">'.(int)$details[0][2].' </label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label"> System Amount</label>
<label class="col-6 form-check-label"> '.(int)$details[0][5].'</label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label"> remaining system amount</label>
<label class="col-6 form-check-label">'.(int) ($details[0][5]-$details[0][2]).' </label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label"> your demanded amount</label>
<label class="col-6 form-check-label">'.(int) $details[0][4].' </label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label">remaining demand amount </label>
<label class="col-6 form-check-label"> '.(int) ($details[0][4]-$details[0][2]).'</label>
</div>
</div>
';
?>
<div class="form-group row border ">
<label class="font-weight-bold border-right col-2 ">dish name</label>
<label class=" font-weight-bold border-right col-3 ">quantity</label>
<label class=" font-weight-bold border-right col-2 ">each price</label>
<label class="font-weight-bold border-right col-2 ">total</label>
<label class=" font-weight-bold col-2 ">Detail</label>
</div>
<?php
$sql='SELECT dd.id,d.name,dd.quantity,dd.price,d.id FROM dish_detail as dd INNER JOIN
dish as d
on d.id=dd.dish_id
where
(dd.orderDetail_id='.$orderId.') AND ISNULL(dd.expire_date)';
$totalAmount=0;
$dishesDetail=queryReceive($sql);
for($i=0;$i<count($dishesDetail);$i++)
{
$totalAmount+=(int)$dishesDetail[$i][2]*(int)$dishesDetail[$i][3];
echo '<div class=" row border ">
<label class="border-right col-form-label col-3">'.$dishesDetail[$i][1].'</label>
<label class=" border-right col-form-label col-2">'.$dishesDetail[$i][2].'</label>
<label class="border-right col-form-label col-2">'.$dishesDetail[$i][3].'</label>
<label class=" border-right col-form-label col-2">'.(int)$dishesDetail[$i][2]*(int)$dishesDetail[$i][3].'</label>
<a href="/Catering/dish/dishPreview.php?dishId='.$dishesDetail[$i][4].'&dishDetailId='.$dishesDetail[$i][0].'&order='.$_GET['order'].'&option=Allselected" class="detailBtn form-control btn-primary col-2">Detail</a>
</div>';
}
?>
<div class="col-12 row ">
<a href="/Catering/order/PreviewOrder.php?order=<?php echo $_GET['order'];?>" class="form-control btn-info col-5">Order Preview</a>
<a href="/Catering/dish/dishDisplay.php?order=<?php echo $_GET['order'];?>" class="form-control btn-success col-5">dish Add +</a>
</div>
</div>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-05
* Time: 22:10
*/
include_once ("../connection/connect.php");
if($_POST['option']=="orderChange")
{
$columnName=$_POST['column_name'];
$coumnText=chechIsEmpty($_POST['value']);
$orderId=$_POST['orderid'];
$sql='UPDATE orderDetail as od SET od.'.$columnName.'="'.$coumnText.'" WHERE od.id='.$orderId.'';
querySend($sql);
}
else if($_POST['option']=="addressChange")
{
$columnName=$_POST['column_name'];
$coumnText=chechIsEmpty($_POST['value']);
$addressId=$_POST['addressId'];
$sql='UPDATE `address` SET '.$columnName.'="'.$coumnText.'" WHERE id='.$addressId.'';
querySend($sql);
}
?><file_sep><?php
/*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::*/
/*:: :*/
/*:: This routine calculates the distance between two points (given the :*/
/*:: latitude/longitude of those points). It is being used to calculate :*/
/*:: the distance between two locations using GeoDataSource(TM) Products :*/
/*:: :*/
/*:: Definitions: :*/
/*:: South latitudes are negative, east longitudes are positive :*/
/*:: :*/
/*:: Passed to function: :*/
/*:: lat1, lon1 = Latitude and Longitude of point 1 (in decimal degrees) :*/
/*:: lat2, lon2 = Latitude and Longitude of point 2 (in decimal degrees) :*/
/*:: unit = the unit you desire for results :*/
/*:: where: 'M' is statute miles (default) :*/
/*:: 'K' is kilometers :*/
/*:: 'N' is nautical miles :*/
/*:: Worldwide cities and other features databases with latitude longitude :*/
/*:: are available at https://www.geodatasource.com :*/
/*:: :*/
/*:: For enquiries, please contact <EMAIL> :*/
/*:: :*/
/*:: Official Web site: https://www.geodatasource.com :*/
/*:: :*/
/*:: GeoDataSource.com (C) All Rights Reserved 2018 :*/
/*:: :*/
/*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::*/
function distance($lat1, $lon1, $lat2, $lon2, $unit)
{
if (($lat1 == $lat2) && ($lon1 == $lon2)) {
return 0;
}
else {
$theta = $lon1 - $lon2;
$dist = sin(deg2rad($lat1)) * sin(deg2rad($lat2)) + cos(deg2rad($lat1)) * cos(deg2rad($lat2)) * cos(deg2rad($theta));
$dist = acos($dist);
$dist = rad2deg($dist);
$miles = $dist * 60 * 1.1515;
$unit = strtoupper($unit);
if ($unit == "K") {
return ($miles * 1.609344);
} else if ($unit == "N") {
return ($miles * 0.8684);
} else {
return $miles;
}
}
}
function SortDistance($lat,$lon,$country)
{
$sql="SELECT h.id,l.latitude,l.longitude FROM hall as h INNER join location as l on (h.location_id=l.id) WHERE (ISNULL(h.expire))AND(l.country='$country')";
$data=queryReceive($sql);
// $data=array(
// array(1,13.232,134.34),
//
// array(2,23.232,234.34),
//
// array(3,31.5204,74.3587),
//
// array(4,43.232,44.34),
//
// );
$placeid=array();
$distance=array();
for($i=0;$i<count($data);$i++)
{
$placeid[$i]=$data[$i][0];
$distance[$i]= distance($data[$i][1], $data[$i][2], $lat, $lon, "K");
$distance[$i]=round($distance[$i], 2);
$data[$i][3]=$distance[$i];
}
array_multisort($distance, SORT_ASC, $placeid, SORT_ASC, $data);
return $data;
}
/*echo distance(31.5204, 74.3587, 33.6844, 73.0479, "M") . " Miles<br>";
echo distance(31.5204, 74.3587, 33.6844, 73.0479, "K") . " Kilometers<br>";
echo distance(31.5204, 74.3587, 33.6844, 73.0479, "N") . " Nautical Miles<br>";*/
?>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../connection/connect.php");
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="container" style="margin-top:150px">
<form>
<div class="col-12 shadow card p-4">
<div class="form-group row">
<!-- <a href="#" class="form-control col-3 btn-warning"> Previous</a>-->
<span class="font-weight-bold text-center col-9 form-control"> Add Dish in System</span>
</div>
<div class="form-group row">
<label class="col-4 col-form-label">Dish Name</label>
<input name="dishname" class="col-8 form-control" type="text">
</div>
<div class="form-group row">
<label class="col-4 col-form-label">Dish Image</label>
<input name="image" class="col-8 form-control" type="file">
</div>
<div class="form-group row">
<label class="col-4 col-form-label">Attribute Name</label>
<input id="attributetext" class="col-6 form-control" type="text">
<input id="addAttribute" type="button" class="col-2 form-control btn-primary" value="+">
</div>
<div class="col-12" id="attributeHere">
</div>
<div class="form-group row">
<label class="col-4 col-form-label">Dish Type</label>
<select id="dishtype" name="dishtype" class="col-8 form-control">
<?php $sql='SELECT `id`, `name` FROM `systemDishType` WHERE ISNULL(isExpire)' ;
$dish_type=queryReceive($sql);
for($i=0;$i<count($dish_type);$i++)
{
echo '<option value="'.$dish_type[$i][0].'">'.$dish_type[$i][1].'</option>';
}
echo '<option value="others">others</option>'
?>
</select>
</div>
<div id="showdishtype" class="row" style="display: none">
<label class="col-4 form-check-label">Other Dish Type</label>
<input type="text" name="otherdishType" class="col-8 form-control">
</div>
<div class="form-group row">
<a href="dishesDetail.php" class="col-4 form-control btn-danger"> Cancel</a>
<input id="submit" type="button" value="Submit" class="col-8 form-control btn-success">
</div>
</div>
</form>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
function checkdishType()
{
if($("#dishtype").val()!="others")
{
$("#showdishtype").hide('slow');
}
else
{
$("#showdishtype").show('slow');
}
}
$("#dishtype").change(function ()
{
checkdishType();
});
checkdishType();
var rows=0;
$("#addAttribute").click(function ()
{
var text=$("#attributetext").val();
$("#attributeHere").append('<div class="form-group row" id="removeid_'+rows+'">\n' +
' <label class="col-4 col-form-label">Attribute Name</label>\n' +
' <input value="'+text+'" name="attribute[]" class="col-6 form-control" type="text">\n' +
' <input data-removeid="'+rows+'" type="button" class="col-2 form-control btn-danger removeattribute" value="-">\n' +
' </div>');
$("#attributetext").val("");
rows++;
}) ;
$(document).on('click','.removeattribute',function ()
{
var id=$(this).data("removeid");
$("#removeid_"+id).remove();
});
$("#submit").click(function (e) {
e.preventDefault();
var formdata=new FormData($("form")[0]);
formdata.append("option","addDishsystem");//addDishsystem
$.ajax({
url:"dishServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.location.href="dishesDetail.php";
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
include_once ('../../connection/connect.php');
if(!isset($_GET['hall']))
{
header("location:../companyRegister/companyEdit.php");
}
$encoded=$_GET['hall'];
$id=base64url_decode($encoded);
if((!is_numeric($id))||($id==""))
{
header("location:../companyRegister/companyEdit.php");
}
if(isset($_GET['action']))
{
if($_GET['action']=="expire")
{
$date=date('Y-m-d H:i:s');
$sql='UPDATE `hall` SET `expire`="'.$date.'" WHERE id='.$id.'';
}
else
{
$sql='UPDATE `hall` SET `expire`=NULL WHERE id='.$id.'';
}
querySend($sql);
header("location:daytimeAll.php?hall=".$encoded."");
}
$hallid='';
$companyid='';
$hallid=$id;
$companyid=$_COOKIE['companyid'];
$sql='SELECT `name`, `max_guests`, `noOfPartitions`, `ownParking`, `expire`, `image`, `hallType`, `location_id` FROM `hall` WHERE id='.$hallid.'';
$halldetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
#formhall
{
margin: 5%;;
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron jumbotron-fluid text-center" style="background-image: url(<?php
if((file_exists('../../images/hall/'.$halldetail[0][5]))&&($halldetail[0][5]!=""))
{
echo "'../../images/hall/".$halldetail[0][5]."'";
}
else
{
echo "https://www.pakvenues.com/system/halls/cover_images/000/000/048/original/Umar_Marriage_Hall_lahore.jpg?1566758537";
}
?>);background-repeat: no-repeat ;background-size: 100% 100%">
<div class="container" style="background-color: white;opacity: 0.7">
<h1 class="display-4"><i class="fas fa-cogs fa-1x"></i> <?php echo $halldetail[0][0]; ?></h1>
<p class="lead">Edit Hall infomation name ,location,pictures....</p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php " class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container">
<h1> Hall Setting </h1>
<hr class="mt-2 mb-3 border-white">
<form class="shadow card-body" id="formhall" >
<input type="number" hidden name="hallid" value="<?php echo $hallid; ?>">
<input type="text" hidden name="previousimage" value="<?php echo $halldetail[0][5]; ?>">
<div class="form-group row">
<label class="col-form-label ">Hall Branch Name:</label>
<!-- <input name="hallname" class="form-control col-8" type="text" value="--><?php //echo $halldetail[0][0]; ?><!--">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-place-of-worship"></i></span>
</div>
<input name="hallname" type="text" class="form-control" value="<?php echo $halldetail[0][0]; ?>">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Hall Type:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fab fa-accusoft"></i></span>
</div>
<select name="halltype" class="form-control">
<?php
$halltype=array("Marquee","Hall","Deera /Open area");
echo '<option value="'.$halldetail[0][6].'">'.$halltype[$halldetail[0][6]].'</option>';
for($i=0;$i<count($halltype);$i++)
{
if($i!=$halldetail[0][6])
{
echo '<option value="'.$i.'">'.$halltype[$i].'</option>';
}
}
?>
</select>
</div>
</div>
<div class="form-group row">
<label class="col-form-label ">Hall Branch Image:</label>
<!-- <input name="image" class="form-control col-8" type="file">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera-retro"></i></span>
</div>
<input name="image" type="file" class="form-control">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"><i class="fas fa-map-marker-alt"> </i>Hall Branch Address</label>
</div>
<div class="form-group row">
<label class="col-form-label">Maximum Capacity of guests in hall:</label>
<!-- <input name="capacity" class="form-control col-4" type="number" value="--><?php //echo $halldetail[0][1]; ?><!--">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-users"></i></span>
</div>
<input type="number" value="<?php echo $halldetail[0][1]; ?>" class="form-control" name="capacity">
</div>
</div>
<div class="form-group row">
<label class="col-form-label ">No of Partition in Hall:</label>
<!-- <input name="partition" class="form-control col-4" type="number" value="--><?php //echo $halldetail[0][2]; ?><!--">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-columns"></i></span>
</div>
<input name="partition" type="number" class="form-control" value="<?php echo $halldetail[0][2]; ?>">
</div>
</div>
<div class="form-group row">
<!-- <input name="parking" class="form-check-input" type="checkbox" --><?php //if($halldetail[0][3]==1){ echo "checked";} ?><!-- >-->
<!-- <label class="form-check-label ">Have Your own parking</label>-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text">
<input name="parking" class="form-check-input " type="checkbox" <?php if($halldetail[0][3]==1){ echo "checked";} ?> ><i class="fas fa-parking"></i>
</span>
</div>
<label class="form-check-label ml-3"> Have Your own parking</label>
</div>
</div>
<div class="form-group row mb-5">
<?php
if($halldetail[0][4]=="")
{
echo '<a href="?action=expire&hall='.$encoded.'" class="btn btn-danger col-6">Expire</a>';
}
else
{
echo '<a href="?action=active&hall='.$encoded.'" class="btn btn-warning col-6">Active</a>';
}
?>
<button id="submitedithall" type="button" class="rounded mx-auto d-block btn btn-primary col-6 " value="Submit"> <i class="fas fa-check "></i>Save</button>
</div>
</form>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
$("#submitedithall").click(function ()
{
var formdata=new FormData($("#formhall")[0]);
formdata.append("option","halledit");
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
return false;
}
else
{
window.history.back();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 14:52
*/
include_once ("../connection/connect.php");
if(!isset($_SESSION['order']))
{
header("location:../user/userDisplay.php");
}
if(isset($_POST['option']))
{
if($_POST['option']=='GetPayment')
{
$name=$_POST['name'];
$amount=chechIsEmpty($_POST['Amount']);
$status=chechIsEmpty($_POST['status']);
$rating=chechIsEmpty($_POST['rating']);
$personality=$_POST['personality'];
$userId=$_POST['user_id'];
$orderDetail_id=$_POST['orderDetail_id'];
$dateTime=date('Y-m-d H:i:s');
$sql='INSERT INTO `payment`(`id`, `amount`, `nameCustomer`, `receive`, `personality`, `rating`, `IsReturn`, `orderDetail_id`, `user_id`, `sendingStatus`) VALUES (NULL,'.$amount.',"'.$name.'","'.$dateTime.'","'.$personality.'",'.$rating.','.$status.','.$orderDetail_id.','.$userId.',0)';
querySend($sql);
}
else if($_POST['option']=='paymentsend')
{
$useid=$_POST['useid'];
$paymentId=$_POST['paymentId'];
$dateTime=date('Y-m-d H:i:s');
$sql='INSERT INTO `transfer`(`id`, `Isconfirm`, `senderTimeDate`, `payment_id`, `user_id`,`Isget`) VALUES (NULL,NULL,"'.$dateTime.'",'.$paymentId.','.$useid.',0)';
querySend($sql);
$sql='UPDATE payment as py SET py.sendingStatus=1 WHERE py.id='.$paymentId.'';
querySend($sql);
}
else if($_POST['option']=='paymentconfigration')
{
$paymentid=$_POST["paymentid"];
$tranferid=$_POST['tranferid'];
$dateTime=date('Y-m-d H:i:s');
if ($_POST['value'] == "unconfirm")
{
$sql='UPDATE transfer as t SET t.Isconfirm="'.$dateTime.'" WHERE t.id='.$tranferid.'';
querySend($sql);
$sql='UPDATE payment as py SET py.sendingStatus=0 WHERE py.id='.$paymentid.'';
querySend($sql);
} else if ($_POST['value'] == "confirm")
{
$sql='UPDATE transfer as t SET t.Isconfirm="'.$dateTime.'",t.Isget=1 WHERE t.id='.$tranferid.'';
querySend($sql);
$sql='UPDATE payment as py SET py.sendingStatus=2 WHERE py.id='.$paymentid.'';
querySend($sql);
}
}
}<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2020-01-05
* Time: 16:37
*/
//session are customerid,typebranch,branchtypeid,tempid,2ndpage,order
setcookie('customerid',"" , time() - (86400 * 30), "/",
$_SERVER["SERVER_NAME"]);
setcookie("typebranch","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("branchtypeid","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("tempid","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("2ndpage","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("order","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);<file_sep>-- MySQL Script generated by MySQL Workbench
-- Sun Sep 1 18:11:01 2019
-- Model: New Model Version: 1.0
-- MySQL Workbench Forward Engineering
SET @OLD_UNIQUE_CHECKS=@@UNIQUE_CHECKS, UNIQUE_CHECKS=0;
SET @OLD_FOREIGN_KEY_CHECKS=@@FOREIGN_KEY_CHECKS, FOREIGN_KEY_CHECKS=0;
SET @OLD_SQL_MODE=@@SQL_MODE, SQL_MODE='TRADITIONAL,ALLOW_INVALID_DATES';
-- -----------------------------------------------------
-- Schema mydb
-- -----------------------------------------------------
-- -----------------------------------------------------
-- Schema a111
-- -----------------------------------------------------
-- -----------------------------------------------------
-- Schema a111
-- -----------------------------------------------------
CREATE SCHEMA IF NOT EXISTS `a111` DEFAULT CHARACTER SET utf8mb4 ;
USE `a111` ;
-- -----------------------------------------------------
-- Table `a111`.`person`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`person` (
`name` VARCHAR(25) NOT NULL,
`cnic` VARCHAR(13) NOT NULL,
`id` INT(11) NOT NULL AUTO_INCREMENT,
`date` DATE NULL,
PRIMARY KEY (`id`),
UNIQUE INDEX `cnic` (`cnic` ASC))
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`address`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`address` (
`id` INT(11) NOT NULL AUTO_INCREMENT,
`address_city` VARCHAR(20) NOT NULL DEFAULT 'lahore',
`address_town` VARCHAR(30) NOT NULL,
`address_street_no` INT(11) NULL DEFAULT NULL,
`address_house_no` INT(11) NULL DEFAULT NULL,
`person_id` INT(11) NULL,
PRIMARY KEY (`id`),
INDEX `fk_address_person1_idx` (`person_id` ASC),
CONSTRAINT `fk_address_person1`
FOREIGN KEY (`person_id`)
REFERENCES `a111`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`number`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`number` (
`number` VARCHAR(11) NOT NULL,
`id` INT(11) NOT NULL AUTO_INCREMENT,
`is_number_active` TINYINT NOT NULL DEFAULT 1,
`person_id` INT(11) NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_number_person1_idx` (`person_id` ASC),
CONSTRAINT `fk_number_person1`
FOREIGN KEY (`person_id`)
REFERENCES `a111`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`order`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`order` (
`destination_date` DATE NULL,
`id` INT(11) NOT NULL AUTO_INCREMENT,
`total_amount` INT(11) NULL DEFAULT 0,
`order_comments` TEXT NULL DEFAULT NULL,
`total_person` INT NOT NULL,
`is_active` INT NOT NULL DEFAULT 1,
`destination_date` DATE NULL,
`booking_date` DATE NULL,
`destination_time` TIME(6) NULL,
`address_id` INT(11) NOT NULL,
`extre_charges` INT NULL,
`person_id` INT(11) NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_order_address1_idx` (`address_id` ASC),
INDEX `fk_order_person1_idx` (`person_id` ASC),
CONSTRAINT `fk_order_address1`
FOREIGN KEY (`address_id`)
REFERENCES `a111`.`address` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_order_person1`
FOREIGN KEY (`person_id`)
REFERENCES `a111`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`dish_type`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`dish_type` (
`id` INT NOT NULL AUTO_INCREMENT,
`name` VARCHAR(45) NULL,
PRIMARY KEY (`id`))
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`dish`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`dish` (
`name` VARCHAR(30) NULL,
`id` INT NOT NULL AUTO_INCREMENT,
`image` VARCHAR(50) NULL,
`dish_type_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_dish_dish_type1_idx` (`dish_type_id` ASC),
CONSTRAINT `fk_dish_dish_type1`
FOREIGN KEY (`dish_type_id`)
REFERENCES `a111`.`dish_type` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`attribute`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`attribute` (
`name` INT NULL,
`id` INT NOT NULL AUTO_INCREMENT,
`image` VARCHAR(45) NULL,
`dish_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_attribute_dish1_idx` (`dish_id` ASC),
CONSTRAINT `fk_attribute_dish1`
FOREIGN KEY (`dish_id`)
REFERENCES `a111`.`dish` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`dish_detail`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`dish_detail` (
`id` INT NOT NULL AUTO_INCREMENT,
`describe` TEXT(300) NULL,
`price` INT NULL,
`expire_date` DATETIME NULL,
`quantity` VARCHAR(45) NULL,
`dish_id` INT NOT NULL,
`order_id` INT(11) NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_dish_detail_dish1_idx` (`dish_id` ASC),
INDEX `fk_dish_detail_order1_idx` (`order_id` ASC),
CONSTRAINT `fk_dish_detail_dish1`
FOREIGN KEY (`dish_id`)
REFERENCES `a111`.`dish` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_dish_detail_order1`
FOREIGN KEY (`order_id`)
REFERENCES `a111`.`order` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`attribute_name`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`attribute_name` (
`id` INT NOT NULL AUTO_INCREMENT,
`quantity` INT NULL,
`attribute_id` INT NOT NULL,
`dish_detail_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_attribute_name_attribute1_idx` (`attribute_id` ASC),
INDEX `fk_attribute_name_dish_detail1_idx` (`dish_detail_id` ASC),
CONSTRAINT `fk_attribute_name_attribute1`
FOREIGN KEY (`attribute_id`)
REFERENCES `a111`.`attribute` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_attribute_name_dish_detail1`
FOREIGN KEY (`dish_detail_id`)
REFERENCES `a111`.`dish_detail` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`order_status`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`order_status` (
`id` INT NOT NULL AUTO_INCREMENT,
`name` VARCHAR(45) NULL,
PRIMARY KEY (`id`))
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`user`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`user` (
`id` INT NOT NULL AUTO_INCREMENT,
`username` VARCHAR(45) NULL,
`password` VARCHAR(10) NULL,
`person_id` INT(11) NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_user_person1_idx` (`person_id` ASC),
CONSTRAINT `fk_user_person1`
FOREIGN KEY (`person_id`)
REFERENCES `a111`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`change_status`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`change_status` (
`id` INT NOT NULL AUTO_INCREMENT,
`order_id` INT(11) NOT NULL,
`order_status_id` INT NOT NULL,
`user_id` INT NOT NULL,
`dateTime` DATETIME(6) NULL,
PRIMARY KEY (`id`),
INDEX `fk_change_status_order1_idx` (`order_id` ASC),
INDEX `fk_change_status_order_status1_idx` (`order_status_id` ASC),
INDEX `fk_change_status_user1_idx` (`user_id` ASC),
CONSTRAINT `fk_change_status_order1`
FOREIGN KEY (`order_id`)
REFERENCES `a111`.`order` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_change_status_order_status1`
FOREIGN KEY (`order_status_id`)
REFERENCES `a111`.`order_status` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_change_status_user1`
FOREIGN KEY (`user_id`)
REFERENCES `a111`.`user` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`payment`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`payment` (
`id` INT NOT NULL AUTO_INCREMENT,
`amount` INT NULL,
`nameCustomer` VARCHAR(45) NULL,
`receive` DATETIME NULL,
`personality` TEXT(300) NULL,
`rating` INT NULL,
`IsReturn` BLOB NULL,
`order_id` INT(11) NOT NULL,
`user_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_payment_order1_idx` (`order_id` ASC),
INDEX `fk_payment_user1_idx` (`user_id` ASC),
CONSTRAINT `fk_payment_order1`
FOREIGN KEY (`order_id`)
REFERENCES `a111`.`order` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_payment_user1`
FOREIGN KEY (`user_id`)
REFERENCES `a111`.`user` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `a111`.`transfer`
-- -----------------------------------------------------
CREATE TABLE IF NOT EXISTS `a111`.`transfer` (
`id` INT NOT NULL AUTO_INCREMENT,
`Isconfirm` DATETIME NULL,
`senderTimeDate` DATETIME NULL,
`payment_id` INT NOT NULL,
`user_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_transfer_payment1_idx` (`payment_id` ASC),
INDEX `fk_transfer_user1_idx` (`user_id` ASC),
CONSTRAINT `fk_transfer_payment1`
FOREIGN KEY (`payment_id`)
REFERENCES `a111`.`payment` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_transfer_user1`
FOREIGN KEY (`user_id`)
REFERENCES `a111`.`user` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
SET SQL_MODE=@OLD_SQL_MODE;
SET FOREIGN_KEY_CHECKS=@OLD_FOREIGN_KEY_CHECKS;
SET UNIQUE_CHECKS=@OLD_UNIQUE_CHECKS;
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-05
* Time: 17:56
*/
include_once ("../connection/connect.php");
$userid=$_SESSION['userid'];
if(!isset($_POST['function']))
{
echo "option in order is not created";
exit();
}
$customerId=$_GET['customer'];
if($_POST['function']=="add") {
$persons = chechIsEmpty($_POST['persons']);
$time = '';
if (empty($_POST['time'])) {
$time = "NULL";
} else {
$time = '"' . $_POST['time'] . '"';
}
$date = '';
if (empty($_POST['date'])) {
$date="NULL";
}
else
{
$date='"'.$_POST['date'].'"';
}
$area=$_POST['area'];
$streetno=chechIsEmpty($_POST['streetno']);
$houseno=chechIsEmpty($_POST['houseno']);
$describe=$_POST['describe'];
$currentDate=date('Y-m-d');
$CurrenttimeDate = date('Y-m-d H:i:s');
$sql='INSERT INTO `address`(`id`, `address_street_no`, `address_house_no`, `person_id`, `address_city`, `address_town`) VALUES (NULL,"'.$streetno.'","'.$houseno.'","'.$customerId.'","lahore","'.$area.'")';
querySend($sql);
$address_id=mysqli_insert_id($connect);
$sql='INSERT INTO `orderTable`(`id`, `total_amount`, `order_comments`, `total_person`, `is_active`, `destination_date`, `booking_date`, `destination_time`, `address_id`, `extre_charges`, `person_id`) VALUES (NULL,0,"'.$describe.'","'.$persons.'",0,'.$date.',"'.$currentDate.'",'.$time.',"'.$address_id.'",0,"'.$customerId.'")';
querySend($sql);
$ordeID=mysqli_insert_id($connect);
echo json_decode($ordeID);
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-15
* Time: 13:36
*/
session_start();
session_destroy();
setcookie('userid',"" , time() - (86400 * 30), "/");
setcookie("isOwner","",time() - (86400 * 30), "/");
setcookie("username","",time() - (86400 * 30), "/");
setcookie("companyid","",time() -(86400 * 30), "/");
setcookie("userimage","",time() - (86400 * 30), "/");
header("location:/Catering/index.php");
exit();
?><file_sep>
<?php
include_once ('../../connection/connect.php');
$hallid=$_GET['hallid'];
$packageid=$_GET['packageid'];
$date=$_GET['date'];
$time=$_GET['time'];
$sql='SELECT `name`, `max_guests`, `noOfPartitions`, `ownParking`,`image`, `hallType`, `location_id` FROM `hall` WHERE id='.$hallid.'';
$hallinformations=queryReceive($sql);
$sql='SELECT u.username,p.name,n.number,p.image from company as c INNER JOIN hall as h
on (h.company_id=c.id)
LEFT JOIN user as u
on (c.user_id=u.id)
left join person as p
on (u.person_id=p.id)
left JOIN number as n
on (p.id=n.person_id)
WHERE h.id='.$hallid.'';
$owndetail=queryReceive($sql);
$sql='SELECT `isFood`, `price`, `describe`,`package_name` FROM `hallprice` WHERE id='.$packageid.'';
$packagedtail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link href="https://fonts.googleapis.com/icon?family=Material+Icons" rel="stylesheet">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<style>
html body{
width: 100%;
height: 100%;
margin-top:20px;
}
.comment-wrapper .panel-body {
max-height:650px;
overflow:auto;
}
.comment-wrapper .media-list .media img {
width:64px;
height:64px;
border:2px solid #e5e7e8;
}
.comment-wrapper .media-list .media {
border-bottom:1px dashed #efefef;
margin-bottom:25px;
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(
<?php
if(file_exists($hallinformations[0][4]))
{
echo $hallinformations[0][4];
}
else
{
echo "https://weddingspot-prod-s3-1.s3.amazonaws.com/__sized__/images/venues/2218/Royal-Palm-Banquet-Hall-Farmingdale-NY-2c26ce40-b77e-404c-afb9-aae846a77332-97450e389c42885476f1fbe9bc5bca5a.jpg";
}
?>);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-body text-center" style="opacity: 0.7 ;background: white;">
<h1 class="display-5 "><i class="fas fa-place-of-worship"></i> <?php echo $hallinformations[0][0];?></h1>
<p class="lead">Free Order Booking</p>
</div>
</div>
<div class="container">
<h1 class="font-weight-light text-lg-left mt-4 mb-0">Package Detail</h1>
<hr class="mt-2 mb-3">
<div class="card p-3 border-0">
<h1 class="m-3 text-danger text-right">
<i class="far fa-money-bill-alt mr-3"></i>RS:<i> <?php echo $packagedtail[0][1];?> </i>
</h1>
<h3 class="m-3 ">
<i class="far fa-calendar-alt"></i>Date:<span class="text-info"><?php echo $date;?></span>
</h3>
<h3 class="m-3 ">
<i class="fas fa-clock"></i>Time:<span class="text-info"><?php echo $time;?></span>
</h3>
<?php
if($packagedtail[0][0]==0)
{
//if food is not
echo '<h3 class="m-3 ">
<i class="material-icons">
airline_seat_recline_normal
</i>with Seating
</h3>';
}
else
{
//if food
echo ' <h5 class="m-3 ">
<i class="material-icons">
fastfood
</i>package name: <span class="text-info">'.$packagedtail[0][3].'</span>
</h5>
<p class="d-block m-3 ">
<i class="far fa-clipboard"></i>
<span class="font-weight-bold text-info">Menu Note:</span>
'.$packagedtail[0][2].'
</p>
';
}
?>
</div>
<?php
$sql='SELECT `id`, `dishname`, `image` FROM `menu` WHERE ISNULL(expire) && (hallprice_id='.$packageid.')';
$menudetail=queryReceive($sql);
if($packagedtail[0][0]==1)
{
//if food then show dishes
$display = '
<div class="container">
<h2 class="font-weight-light text-center text-lg-left mt-4 mb-0">Menu</h2>
<hr class="mt-2 mb-5">
<div class="row text-center text-lg-left">
';
for ($i = 0; $i < count($menudetail); $i++) {
$display .= '
<div class="col-lg-3 col-md-4 col-6">
<a href="#' . $menudetail[$i][0] . '" class="d-block mb-4 h-100">
<img class="img-fluid img-thumbnail" src="' . $menudetail[$i][2] . '" alt="" style="width: 100%;height: 20vh">
<h3>' . $menudetail[$i][1] . '</h3>
</a>
</div>';
}
$display .= '
</div>
</div>';
echo $display;
}
?>
<!--<div class="container">
<h2 class="font-weight-light text-center text-lg-left mt-4 mb-0">Menu</h2>
<hr class="mt-2 mb-5">
<div class="row text-center text-lg-left">
<div class="col-lg-3 col-md-4 col-6">
<a href="#" class="d-block mb-4 h-100">
<img class="img-fluid img-thumbnail" src="https://source.unsplash.com/pWkk7iiCoDM/400x300" alt="">
<h3>sdsddsfds</h3>
</a>
</div>
</div>
</div>-->
</div>
<div class="container" >
<h1 class="font-weight-light text-lg-left mt-4 mb-0">Hall Information</h1>
<hr class="mt-2 mb-5">
<div class="row card-body mb-2">
<div class="container p-0">
<div class="row">
<img src="<?php
if(file_exists($owndetail[0][3]))
{
echo $owndetail[0][3];
}
else
{
echo "https://cdn.pixabay.com/photo/2016/04/25/07/49/man-1351346_960_720.png";
}
?> " class="img-thumbnail" style="width: 200px">
<h4 class="m-3"><span class="text-white">Name: <?php echo $owndetail[0][1];?></span></h4>
</div>
<?php
$display='';
for($i=0;$i<count($owndetail);$i++)
{
$display.='<h5 class="m-3">
<i class="fas fa-phone-volume"></i>
Phone No:<span class="text-white"> '.$owndetail[$i][2].'</span></h5>';
}
echo $display;
?>
<h5 class="m-3">
<i class="fas fa-users"></i>
Maximum Guest: <span class="text-white"><?php echo $hallinformations[0][0];?></span></h5>
<h5 class="m-3">
<i class="fas fa-columns"></i>
Number of partitions: <span class="text-white"><?php echo $hallinformations[0][0];?></span></h5>
<h5 class="m-3">
<i class="fas fa-parking"></i>Parking : <span class="text-white"><?php
if($hallinformations[0][0]==1)
{
echo " Yes";
}
else
{
echo " NO";
}
?>
</span> </h5>
<h5 class="m-3">
<i class="fas fa-archway"></i>
Hall Type: <span class="text-white"><?php
$halltype=array("Marquee","Hall","Deera /Open area");
echo $halltype[$hallinformations[0][5]];
?> </span></h5>
</div>
</div>
</div>
<div class="container">
<h1 class="font-weight-light text-lg-left mt-5 mb-3">Gallery</h1>
<form action="" method="POST" enctype="multipart/form-data" class="form-inline">
<input type="file" name="userfile[]" value="" multiple="" class="col-8 btn btn-light">
<input id="submitmultiphotos" type="submit" name="submit" value="Upload" class="btn btn-success col-4">
</form>
<?php
if(isset($_FILES['userfile']))
{
$file_array=reArray($_FILES['userfile']);
$Distination='';
for ($i=0;$i<count($file_array);$i++)
{
$Distination= '../../images/hall/'.$file_array[$i]['name'];
$error=MutipleUploadFile($file_array[$i],$Distination);
if(count($error)>0)
{
echo '<h4 class="badge-danger">'.$file_array[$i]['name'].'.'.$error[0].'</h4>';
}
else
{
$sql='INSERT INTO `images`(`id`, `image`, `expire`, `catering_id`, `hall_id`) VALUES (NULL,"'.$Distination.'",NULL,NULL,'.$hallid.')';
querySend($sql);
}
}
unset($_FILES['userfile']);
}
?>
<hr class="mt-3 mb-5">
<div class="row text-center text-lg-left">
<?php
$sql='SELECT `id`, `image` FROM `images` WHERE hall_id='.$hallid.'' ;
echo showGallery($sql);
?>
</div>
</div>
<?php
include_once ("comment.php");
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
$("#submitmultiphotos").change(function (e)
{
e.preventDefault();
var formData=new FormData($(this)[0]);
$.ajax({
url:"",
method:"POST",
data:formData,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
location.reload();
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-07
* Time: 11:31
*/
include_once ("../connection/connect.php");
$orderId=$_SESSION['order'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/complete.css">
<style>
</style>
</head>
<body class="text-white">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://qph.fs.quoracdn.net/main-qimg-b1822af85b86aabaa253ad7948880cb7);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 class="text-dark"><i class="fas fa-file-word fa-3x mr-2 "></i>BILL DETAIL</h3>
</div>
</div>
<div class="container">
<div class="row justify-content-center col-12" style="margin-top: -60px">
<div class="card text-center card-header">
<img src="
<?php
$sql="SELECT DISTINCT ot.id, (SELECT p.name FROM person as p WHERE p.id=ot.person_id), (SELECT sum(py.amount) FROM payment as py WHERE (py.IsReturn=0)AND(py.orderDetail_id=ot.id)) ,ot.id,ot.total_amount, (SELECT SUM(dd.price*dd.quantity) FROM dish_detail as dd WHERE dd.orderDetail_id=ot.id),(SELECT p.image FROM person as p WHERE p.id=ot.person_id) FROM orderDetail as ot LEFT join payment as py on ot.id=py.orderDetail_id WHERE ot.id=".$orderId."";
$details=queryReceive($sql);
if($details[0][6]=="")
{
echo 'https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
else
{
echo $details[0][6];
}
?> " style="height: 20vh;" class="figure-img rounded-circle" alt="image is not set">
<h5 ><?php
echo $details[0][1];
?></h5>
<label >Order ID:<?php
echo $details[0][0];
?></label>
</div>
</div>
<?php
echo '
<div class="col-12 shadow card-header mb-3 border">
<div class="form-group row">
<label class="col-6 form-check-label"> received amount</label>
<label class="col-6 form-check-label">'.(int)$details[0][2].' </label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label"> System Amount</label>
<label class="col-6 form-check-label"> '.(int)$details[0][5].'</label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label"> remaining system amount</label>
<label class="col-6 form-check-label">'.(int) ($details[0][5]-$details[0][2]).' </label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label"> your demanded amount</label>
<label class="col-6 form-check-label">'.(int) $details[0][4].' </label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label">remaining demand amount </label>
<label class="col-6 form-check-label"> '.(int) ($details[0][4]-$details[0][2]).'</label>
</div>
</div>
';
?>
<div class="col-12" style="overflow: auto">
<div class="form-group row border">
<label class="font-weight-bold border-right col-3 "><h1 class="fas fa-concierge-bell mr-2"></h1> dish name</label>
<label class=" font-weight-bold border-right col-3 "><h1 class="fas fa-hashtag mr-2"></h1>quantity</label>
<label class=" font-weight-bold border-right col-3 "><h1 class="far fa-money-bill-alt mr-2"></h1>each price</label>
<label class="font-weight-bold border-right col-3 "><h1 class="fas fa-list-alt mr-2"></h1>total</label>
</div>
<?php
$sql='SELECT dd.id,d.name,dd.quantity,dd.price,d.id FROM dish_detail as dd INNER JOIN
dish as d
on d.id=dd.dish_id
where
(dd.orderDetail_id='.$orderId.') AND ISNULL(dd.expire_date)';
$totalAmount=0;
$dishesDetail=queryReceive($sql);
for($i=0;$i<count($dishesDetail);$i++)
{
$totalAmount+=(int)$dishesDetail[$i][2]*(int)$dishesDetail[$i][3];
echo '
<a href="/Catering/dish/dishPreview.php?dishId='.$dishesDetail[$i][4].'&dishDetailId='.$dishesDetail[$i][0].'&order='.$orderId.'&option=Allselected" class="row card-body border text-white p-0 shadow" >
<label class="border-right col-form-label col-3">'.$dishesDetail[$i][1].'</label>
<label class="border-right col-form-label col-3">'.$dishesDetail[$i][2].'</label>
<label class="border-right col-form-label col-3">'.$dishesDetail[$i][3].'</label>
<label class="border-right col-form-label col-3">'.(int)$dishesDetail[$i][2]*(int)$dishesDetail[$i][3].'</label>
</a>';
}
?>
</div>
<div class="col-12 row justify-content-center mt-4 ">
<a href="/Catering/dish/dishDisplay.php" class="form-control btn-success col-5"><i class="fas fa-concierge-bell"></i>dish Add +</a>
<a class="nav-link btn btn-warning col-5" href="/Catering/order/PreviewOrder.php"><i class="fas fa-shopping-cart"></i> Order Preview</a>
</div>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:25
*/
session_start();
date_default_timezone_set("asia/karachi");
$connect=mysqli_connect('localhost',"root","","a111");
//$connect=mysqli_connect("localhost","id10884474_shahzad","11111","id10884474_catering");
if(!$connect)
{
echo "fail connection";
}
if (mysqli_connect_errno())
{
printf("Connect failed: %s\n", mysqli_connect_error());
exit();
}
function queryReceive($sql)
{
global $connect;
$result = mysqli_query($connect, $sql);
if (!$result)
{
echo $sql;
echo("Error description: " . mysqli_error($connect));
}else
{
return mysqli_fetch_all($result);
}
}
function querySend($sql)
{
global $connect;
$result = mysqli_query($connect, $sql);
if (!$result)
{
echo $sql;
echo("Error description: " . mysqli_error($connect));
}
}
function chechIsEmpty($value)
{
if($value=="")
{
return 0;
}
return $value;
}
function arrayCheckIsEmpty($valuesArray)
{
for ($a=0;$a<count($valuesArray);$a++)
{
if($valuesArray[$a]=="")
{
$valuesArray[$a]=0;
}
}
return $valuesArray;
}
function ImageUploaded($File,$DestinationFile)
{
if(isset($File['image']))// name=image
{
$errors= array();
$file_size = $File['image']['size'];
$file_tmp = $File['image']['tmp_name'];
$file_type = $File['image']['type'];
$passbyreference=explode('.',$File['image']['name']);
$file_ext=strtolower(end($passbyreference));
$extensions= array("jpeg","jpg","png");
if(in_array($file_ext,$extensions)=== false){
$errors[]="extension not allowed, please choose a JPEG or PNG file.";
}
if($file_size > 2097152)
{
$errors[]='File size must be excately 2 MB';
}
// if (file_exists($DestinationFile))
// {
// $errors[]= "Sorry, file already exists.";
// }
if(empty($errors)==true)
{
move_uploaded_file($file_tmp,$DestinationFile);
return "";
}else{
return $errors;
}
}
return "";
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2020-01-06
* Time: 17:28
*/
header('location:dish/dishesDetail.php');
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include ("../../connection/connect.php");
$companyid=$_COOKIE['companyid'];
//session_destroy();
if(isset($_SESSION['order']))
{
unset($_SESSION['order']);
}
if(isset($_SESSION['customer']))
{
unset($_SESSION['customer']);
}
if(isset($_GET['branchtype']))
{
if($_GET['branchtype']=="hall")
{
$_SESSION['branchtype']="hall";
}
else
{
$_SESSION['branchtype']="catering";
}
$_SESSION['branchtypeid']=$_GET['branchtypeid'];
header("location:../../user/userDisplay.php");
}
$sql='SELECT c.name FROM company as c WHERE c.id='.$companyid.'';
$companydetail=queryReceive($sql);
$sql='SELECT `id`, `name`,`image` FROM `hall` WHERE ISNULL(expire) AND (company_id='.$companyid.')';
$halls=queryReceive($sql);
$sql='SELECT `id`, `name`,`image` FROM `catering` WHERE ISNULL(expire) AND (company_id='.$companyid.')';
$caterings=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<style>
#hallbranches
{
width: 100%;/*
height: 50vh;
overflow: auto;*/
background-size: 100% 100%;
}
#cateringbranches
{
width: 100%;
/* height: 50vh;
overflow: auto;*/
background-size: 100% 100%;
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow " style="background-image: url(https://i2.wp.com/findlawyer.com.ng/wp-content/uploads/2018/05/Pros-and-Cons-of-Working-at-Large-Companies.jpg?resize=1024%2C512&ssl=1);background-size:100% 115%;background-repeat: no-repeat;">
<div class="card-body text-center" style="opacity: 0.7 ;background: white;">
<h1 class="display-5 "><i class="fas fa-city mr-2"></i><?php echo $companydetail[0][0];?></h1>
<p>check your orders of hall and as well as catering</p>
<?php
if($_COOKIE['isOwner']==1)
{
echo ' <h1 class="text-center"> <a href="companyEdit.php" class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
';
}
?>
</div>
</div>
<h1><i class="fas fa-place-of-worship"></i>Hall Branches</h1>
<hr class="border border-white">
<div class="col-12 m-1 mb-5 form-group row shadow" id="hallbranches" >
<?php
$display='';
for ($i=0;$i<count($halls);$i++)
{
$display.= '
<a href="?branchtype=hall&branchtypeid='.$halls[$i][0].'"
class="col-sm-12 col-md-4 col-xl-3 m-2 shadow border text-white" >
<img class="card-img-top col-12 p-0" src="';
if(file_exists($halls[$i][2]))
{
$display.=$halls[$i][2];
}
else
{
$display.='data:image/jpeg;base64,/9j/4AAQSkZJRgABAQAAAQ<KEY>AAAAAAAAABEQIhEjFBMi<KEY>EQMRAD8ARE2YOcKYxvfksOuNHxS+LFQoMDGNqzwElLfE4zbTLPHugFJVdFwsxLgtmQ3f+Mc+M6b5XscmWkJNEqUc2<KEY>';
}
$display.='" alt="Card image" style="height: 25vh" >
<h4 align="center" class="alert-dark"><i class="fas fa-place-of-worship mr-1"></i>'.$halls[$i][1].'</h4>
</a>';
}
echo $display;
?>
</div>
<h2><i class="fas fa-utensils mr-2"></i>Catering Branches</h2>
<hr class="border border-white">
<div class="col-12 m-1 mb-5 form-group row shadow border " id="cateringbranches" >
<?php
$display='';
for ($i=0;$i<count($caterings);$i++)
{
$display.= '
<a href="?branchtype=catering&branchtypeid='.$caterings[$i][0].'" class="col-sm-12 col-md-4 col-xl-3 m-2 border text-white">
<img class="card-img-top col-12 p-0" src="';
if(file_exists($caterings[$i][2])&&($caterings[$i][2]!=""))
{
$display.=$caterings[$i][2];
}
else
{
$display.='data:image/jpeg;base64,/9j/4AAQSkZJRgABAQAAAQABAAD/2wCEAAkGBxEQEBIQDxITFRIREBUVGBMXFxUZFxMSFhYWGBUSFRUZHiogGxolGxMZITIhJyk3Li4uFyEzODMsNygxMysBCgoKDQ0NFQ8PFS0ZFRkrKysrKy0tNysrKzcrLSs3KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrK//AABEIAMkA+wMBIgACEQEDEQH/xAAcAAEAAgIDAQAAAAAAAAAAAAAABgcEBQECAwj/xABSEAABAwIDBAUHBA0JBwUAAAABAAIDBBEFEiEGBzHwEyJBUWEUFlVxgZGSk6HT4hUjMkJUYnSCsbKzwdEIM1JTZHJzw+E0NURjZYPxFyUmNkP/xAAVAQEBAAAAAAAAAAAAAAAAAAAAAf/EABQRAQAAAAAAAAAAAAAAAAAAAAD/2gAMAwEAAhEDEQA/ALxREQEREBERAREQEREBERAREQEREBERAREQEREBERAREQEREBERAREQEREBERAREQEREBERAREQEREBERAREQEREBERARE<KEY>';
}
$display.='" alt="Card image" style="height: 25vh ;background-size:150% 140%;">
<h4 align="center" class="alert-dark"><i class="fas fa-utensils mr-2"></i>'.$caterings[$i][1].'</h4>
</a>';
}
echo $display;
?>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
</script>
</body>
</html>
<file_sep><?php
include_once ("../../connection/connect.php");
$hallname=$_GET['hallname'];
$month=$_GET['month'];
$daytime=$_GET['daytime'];
$hallid=$_SESSION['tempid'];
$companyid=$_COOKIE['companyid'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<style>
form
{
margin: 5%;
}
#selectedmenu
{
background: #F09819; /* fallback for old browsers */
background: -webkit-linear-gradient(to right, #EDDE5D, #F09819); /* Chrome 10-25, Safari 5.1-6 */
background: linear-gradient(to right, #EDDE5D, #F09819); /* W3C, IE 10+/ Edge, Firefox 16+, Chrome 26+, Opera 12+, Safari 7+ */
}
#selectmenu
{
background: #9796f0; /* fallback for old browsers */
background: -webkit-linear-gradient(to right, #fbc7d4, #9796f0); /* Chrome 10-25, Safari 5.1-6 */
background: linear-gradient(to right, #fbc7d4, #9796f0); /* W3C, IE 10+/ Edge, Firefox 16+, Chrome 26+, Opera 12+, Safari 7+ */
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://thumbs.dreamstime.com/z/spicy-dishes-dinner-menu-icon-design-grilled-chicken-curry-sauce-vegetable-stew-pasta-pesto-sauce-ham-curry-84629311.jpg);background-size:100% 115%;background-repeat: no-repeat;">
<div class="card-body text-center" style="opacity: 0.7 ;background: white;">
<h1 class="display-5 "><i class="fas fa-plus-square"></i>Add new Package</h1>
<ol class="list-unstyled">
<li><i class="fas fa-place-of-worship"></i>Hall name:<?php echo $hallname;?></li>
<li><i class="fas fa-table"></i>Month:<?php echo $month?></li>
<li><i class="far fa-clock"></i>Daytime:<?php echo $daytime;?></li>
</ol>
</div>
</div>
<div class="container">
<form id="submitpackage" >
<?php
echo '<input hidden type="text" name="month" value="'.$month.'">
<input hidden type="text" name="daytime" value="'.$daytime.'">
<input hidden type="text" name="hallid" value="'.$hallid.'">
';
?>
<div class="form-group row">
<lable class="col-form-label">Same as previous Packages</lable>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-hamburger"></i></span>
</div>
<select id="perivious" name="perivious" class="form-control">
<option value="none">None</option>
<?php
$sql='SELECT hp.package_name,hp.id,hp.price FROM company as c INNER join hall as h on(h.company_id=c.id) INNER join hallprice as hp on (hp.hall_id=h.id) WHERE ISNULL(c.expire) && ISNULL(h.expire) && ISNULL(hp.expire) &&(hp.isFood=1) &&(c.id='.$_COOKIE['companyid'].') GROUP BY(hp.package_name)';
$packages=queryReceive($sql);
for($i=0;$i<count($packages);$i++)
{
echo '<option value="'.$packages[$i][1].'">'.$packages[$i][0].' with Price '.$packages[$i][2].' </option>';
}
?>
</select>
</div>
</div>
<div id="shownonperivious">
<div class="form-group row">
<lable class="col-form-label">Packages Name</lable>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-hamburger"></i></span>
</div>
<input name="packagename" class="form-control" type="text" placeholder="chicken menu,mutton menu">
</div>
</div>
<div class="form-group row">
<lable class="col-form-label">Packages Rate per head</lable>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-money-bill-alt"></i></span>
</div>
<input name="rate" class="form-control" type="number" placeholder="Price like 1000 per head">
</div>
</div>
<div class="form-group row">
<lable class="col-form-label">Packages Description</lable>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-comments"></i></span>
</div>
<textarea name="describe" class="form-control" placeholder="describe package information for client" ></textarea>
</div>
</div>
<h3 align="center"><i class="fas fa-thumbs-up"></i> Selected Menu of Your Package</h3>
<div id="selectedmenu" class="row form-group m-0" style="overflow:auto;width: 100% ;height: 40vh">
</div>
</div>
<div class="col-12 mt-2 row">
<button id="btncancel" type="button" value="Cancel" class="btn btn-danger col-5 float-right"><span class="fas fa-window-close "></span>Cancel</button>
<button id="btnsubmit" type="button" value="Submit" class="btn btn-primary col-5 float-right"><i class="fas fa-check "></i>Submit</button>
</div>
</form>
<hr class="border">
<h3 align="center" class="mt-5"><i class="far fa-hand-pointer mr-2"></i>Select Dishes</h3>
<!-- Button trigger modal -->
<div class="form-group row">
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-search"></i></span>
</div>
<input id="searchdish" class="form-control" type="text" placeholder="Search dish">
<button type="button" class="btn btn-primary float-right col-4" data-toggle="modal" data-target="#exampleModal">
ADD dish
</button>
</div>
</div>
<div id="selectmenu" class="border m-2 p-0 row" style="overflow:auto;width: 100% ;height: 50vh" >
<?php
$sql = 'SELECT `name`, `id`, `image` FROM `systemDish` WHERE ISNULL(isExpire)';
echo dishesOfPakage($sql);
?>
</div>
<!-- Modal -->
<div class="modal fade" id="exampleModal" tabindex="-1" role="dialog" aria-labelledby="exampleModalLabel" aria-hidden="true">
<div class="modal-dialog" role="document">
<div class="modal-content">
<div class="modal-header">
<h5 class="modal-title" id="exampleModalLabel">Modal title</h5>
<button type="button" class="close" data-dismiss="modal" aria-label="Close">
<span aria-hidden="true">×</span>
</button>
</div>
<div class="modal-body">
<form id="formDishaddss">
<div class="form-group row">
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-hamburger"></i></span>
</div>
<input id="dishnameadd" name="dishname" class="form-control" type="text" placeholder="Dish Name Enter">
</div>
</div>
<div class="form-group row">
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input name="image" class="form-control" type="file">
</div>
</div>
</form>
</div>
<div class="modal-footer">
<button type="button" class="btn btn-secondary" data-dismiss="modal">Close</button>
<button type="button" id="submitformDishadd" class="btn btn-primary float-right">Save changes</button>
</div>
</div>
</div>
</div>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
var numbers=0;
$(document).on("click",".touchdish",function ()
{
var text='';
var value=$(this).val();
var id=$(this).data("dishid");
var image=$(this).data("image");
var dishname=$(this).data("dishname");
if(value=="Remove")
{
$("#dishtempid"+id).remove();
}
else
{
text="<div id=\"dishtempid"+numbers+"\" class=\"col-4 alert-danger border m-1 form-group p-0\" style=\"height: 30vh;\" >\n" +
" <img src=\""+image+"\" class=\"col-12\" style=\"height: 15vh\">\n" +
" <p class=\"col-form-label\" class=\"form-control col-12\">"+dishname+"</p>\n" +
" <input data-dishid=\""+numbers+"\" type=\"button\" value=\"Remove\" class=\"form-control col-12 touchdish btn btn-danger\">\n" +
" <input hidden type=\"text\" name=\"dishname[]\" value=\""+dishname+"\">\n" +
" <input hidden type=\"text\" name=\"image[]\" value=\""+image+"\">\n" +
" </div>";
numbers++;
$("#selectedmenu").append(text);
}
});
$("#perivious").change(function ()
{
if($(this).val()!="none")
{
$("#shownonperivious").hide('slow');
}
else
{
$("#shownonperivious").show('slow');
}
});
$("#btnsubmit").click(function ()
{
var formdata=new FormData($('#submitpackage')[0]);
formdata.append("option","CreatePackage");
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
$("#btncancel").click(function () {
window.history.back();
});
$('#myModal').on('shown.bs.modal', function () {
$('#myInput').trigger('focus')
});
$("#submitformDishadd").click(function (e)
{
e.preventDefault();
if($.trim($("#dishnameadd").val()).length==0)
{
alert("please enter dish name");
return false;
}
var formdata = new FormData($("form")[1]);
formdata.append("option","formDishadd");
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
$("#selectmenu").html(data);
$("form")[1].reset();
$('#exampleModal').modal('toggle');
}
});
});
$("#searchdish").keyup(function () {
var dishname=$(this).val();
var formdata=new FormData();
formdata.append("option","dishpredict");
formdata.append("dishname",dishname);
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
$("#selectmenu").html(data);
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../../connection/connect.php");
$cateringid=$_SESSION['tempid'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../../bootstrap.min.css">
<script src="../../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../../webdesign/css/complete.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../../webdesign/header/header.php");
?>
<div class="jumbotron shadow text-center" style="background-image: url(https://shaadishopblog.files.wordpress.com/2015/10/indian-wedding-punjabi-jain-kunal-shveta-bride-groom-hotel-irvine-global-photography-lehenga-sherwani-sera-manohar-delhi-palace-indian-food.jpg?w=720&h=480);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-body " style="opacity: 0.7 ;background: white;">
<h1 class="display-5 text-center"><i class="fas fa-utensils fa-3x mr-1"></i> Add new Dish</h1>
<p class="lead">Add new dish such as chieken biryan,halwa ...</p>
</div>
</div>
<div class="container">
<form>
<input type="number" hidden name="cateringid" value="<?php echo $cateringid;?>">
<div class="form-group row">
<label class="col-form-label">Dish Name</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input name="dishname" class="form-control" type="text" placeholder="Dish name etc chicken biryan">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Dish Image</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input name="image" class="form-control" type="file">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Attribute Name</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input id="attributetext" class="form-control" type="text" placeholder="etc rice,chieken ,... ">
<input id="addAttribute" type="button" class="col-2 form-control btn-primary" value="+">
</div>
</div>
<div class="col-12" id="attributeHere">
</div>
<div class="form-group row">
<label class="col-form-label">Dish Type</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<select id="dishtype" name="dishtype" class="form-control">
<?php
$sql='SELECT `id`, `name` FROM `dish_type` WHERE (ISNULL(isExpire))AND(catering_id='.$cateringid.')';
$dish_type=queryReceive($sql);
for($i=0;$i<count($dish_type);$i++)
{
echo '<option value="'.$dish_type[$i][0].'">'.$dish_type[$i][1].'</option>';
}
echo '<option value="others">others</option>'
?>
</select>
</div>
</div>
<div id="showdishtype" class="row" style="display: none">
<label class="form-check-label">Other Dish Type</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input type="text" name="otherdishType" class="form-control" placeholder="add new dish type">
</div>
</div>
<div class="form-group row justify-content-center">
<button id="cancel" type="button" class="col-5 form-control btn-danger btn" value="cancel"><span class="fas fa-window-close "></span> Cancel</button>
<button id="submit" type="button" value="Submit" class="col-5 form-control btn-success btn"><i class="fas fa-check "></i> Submit</button>
</div>
</form>
</div>
<?php
include_once ("../../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
function checkdishType()
{
if($("#dishtype").val()!="others")
{
$("#showdishtype").hide('slow');
}
else
{
$("#showdishtype").show('slow');
}
}
$("#dishtype").change(function ()
{
checkdishType();
});
checkdishType();
var rows=0;
$("#addAttribute").click(function ()
{
var text=$("#attributetext").val();
$("#attributeHere").append('<div class="form-group row" id="removeid_'+rows+'">\n' +
' <label class="col-4 col-form-label">Attribute Name</label>\n' +
' <input value="'+text+'" name="attribute[]" class="col-6 form-control" type="text">\n' +
' <input data-removeid="'+rows+'" type="button" class="col-2 form-control btn-danger removeattribute" value="-">\n' +
' </div>');
$("#attributetext").val("");
rows++;
}) ;
$(document).on('click','.removeattribute',function ()
{
var id=$(this).data("removeid");
$("#removeid_"+id).remove();
});
$("#submit").click(function (e) {
e.preventDefault();
var formdata=new FormData($("form")[0]);
formdata.append("option","addDishsystem");//addDishsystem
$.ajax({
url:"dishServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
$("#cancel").click(function (e)
{
window.history.back();
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../connection/connect.php");
if(isset($_GET['action']))
{
if($_GET['action']=="expire")
{
$date=date('Y-m-d H:i:s');
$sql='UPDATE `catering` SET `expire`="'.$date.'" WHERE id='.$_SESSION['tempid'].'';
}
else
{
$sql='UPDATE `catering` SET `expire`=NULL WHERE id='.$_SESSION['tempid'].'';
}
querySend($sql);
header("location:../companyRegister/companyEdit.php");
}
if(isset($_GET['dishdetail']))
{
$_SESSION['2ndpage']=$_GET['dishid'];
header("location:dish/EditDish.php");
}
$cateringid=$_SESSION['tempid'];
$sql='SELECT `name`, `expire`, `image`, `location_id` FROM `catering` WHERE id='.$cateringid.'';
$cateringdetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow text-center" style="background-image: url(<?php
if(file_exists('../'.$cateringdetail[0][2]) &&($cateringdetail[0][2]!=""))
{
echo '../'.$cateringdetail[0][2];
}
else
{
echo "https://www.hnfc.com.my/data1/images/slide2.jpg";
}
?>
);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-body " style="opacity: 0.7 ;background: white;">
<h1 class="display-5 text-center"><i class="fas fa-utensils fa-3x mr-1"></i><?php echo $cateringdetail[0][0];?> Edit Catering Branches</h1>
<p class="lead">Edit dishes information,dishes type,images and others </p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php" class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container" >
<form id="formcatering">
<input type="number" hidden name="cateringid" value="<?php echo $cateringid; ?>">
<input type="text" hidden name="previousimage" value="<?php echo $cateringdetail[0][2]; ?>">
<div class="form-group row">
<label class="col-form-label ">Catering Branch Name:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-utensils"></i></span>
</div>
<input name="cateringname" class="form-control" type="text" value="<?php echo $cateringdetail[0][0]; ?>">
</div>
</div>
<div class="form-group row">
<label class="col-form-label ">Catering Branch Image:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input name="image" class="form-control" type="file">
</div>
</div>
<div class="form-group row">
<h3 align="center"> <i class="fas fa-map-marker-alt"></i>Address(optional)</h3>
</div>
<div class="form-group row col-12 mb-5">
<?php
if($cateringdetail[0][1]=="")
{
echo '<a href="?action=expire" class="btn btn-danger col-6">Expire</a>';
}
else
{
echo '<a href="?action=active" class="btn btn-warning col-6">Active</a>';
}
?>
<button id="submiteditcatering" type="button" class="rounded mx-auto d-block btn btn-primary col-5 " value="Submit"><i class="fas fa-check "></i>Submit</button>
</div>
</form>
<h1 class="font-weight-bold">System Dish info </h1>
<hr>
<h3 align="center"> Dish Type information</h3>
<div class="col-12 form-group row font-weight-bold border">
<label class="col-9 col-form-label "><i class="fas fa-utensils mr-1"></i>Name Dish type</label>
<label class="col-3 col-form-label ">Detail</label>
</div>
<div class="col-12" style="height: 25vh;overflow:auto">
<?php
$sql='SELECT `id`, `name`, `isExpire` FROM `dish_type` WHERE catering_id='.$cateringid.'';
$dishTypes=queryReceive($sql);
$Display='';
for($i=0;$i<count($dishTypes);$i++)
{
$Display.= '<div class="form-group row border " id="Delele_Dish_Type_'.$dishTypes[$i][0].'">
<input data-dishtypeid="'.$dishTypes[$i][0].'" value="'.$dishTypes[$i][1].'" class="changeDishType col-9 form-control ">
<input data-dishtypeid="'.$dishTypes[$i][0].'" class=" btn Delele_Dish_Type col-3 form-control ';
if($dishTypes[$i][2]=="")
{
$Display.='btn-primary ';
}
else
{
$Display.=' btn-danger ';
}
$Display.=' " value="';
if($dishTypes[$i][2]=="")
{
$Display.='Disable';
}
else
{
$Display.='Enable';
}
$Display.= '"></div>';
}
echo $Display;
?>
</div>
<div class="col-12 row mb-4">
<h3 class="rounded mx-auto d-block m-4 col-6" align="center"> Dish information</h3>
<a href="dish/addDish.php" class="float-right btn btn-success col-4 form-control mt-4">Add dish +</a>
</div>
<hr>
<div class="col-12 card shadow mb-2 p-4 ">
<?php
$sql='SELECT id,name FROM dish_type WHERE catering_id='.$cateringid.'';
$dishTypes=queryReceive($sql);
$Display='';
$display='<div class="form-group row " style="height: 50vh;overflow:auto">';
for($j=0;$j<count($dishTypes);$j++)
{
$display.='<h4 class="col-12 newcolor" align="center">'.$dishTypes[$j][1].'</h4>';
$sql = 'SELECT d.name, d.id, (SELECT dt.name from dish_type as dt WHERE dt.id=d.dish_type_id),(SELECT dt.isExpire from dish_type as dt WHERE dt.id=d.dish_type_id), d.isExpire,d.image FROM dish as d WHERE dish_type_id=' . $dishTypes[$j][0] . ' ';
$Dishes = queryReceive($sql);
for ($i = 0; $i < count($Dishes); $i++) {
$display .= '<a href="?dishdetail=yes&dishid=' . $Dishes[$i][1] . '&cateringid='.$cateringid.'" class="col-sm-12 col-md-6 col-xl-4 border">
<img src="';
if(file_exists(substr($Dishes[$i][5],3))&&($Dishes[$i][5]!=""))
{
$display.=substr($Dishes[$i][5],3);
}
else
{
$display.='../../gmail.png';
}
$display.='" style="height: 20vh" class="col-12">
<p class="col-12 p-0" ><i class="fas fa-utensils mr-1"></i>' . $Dishes[$i][0] . '</p>
<i class="col-12 ';
if (($Dishes[$i][3] == "") && ($Dishes[$i][4] == "")) {
$display .= " text-primary ";
} else {
$display .= "text-danger ";
}
$display .= '">';
if ($Dishes[$i][3] != "") {
$display .= $Dishes[$i][2] . " Diable ";
}
if ($Dishes[$i][4] != "") {
$display .= " Dish Diable ";
}
$display .= '</i>
</a>';
}
}
$display.='</div>';
echo $display;
?>
</div>
</div>
<div class="container">
<h1 class="font-weight-light text-lg-left mt-4 mb-3">Gallery</h1>
<form action="" method="POST" enctype="multipart/form-data" class="form-inline">
<input type="file" name="userfile[]" value="" multiple="" class="col-8 btn btn-light">
<input type="submit" name="submit" value="Upload" class="btn btn-success col-4">
</form>
<?php
if(isset($_FILES['userfile']))
{
$file_array=reArray($_FILES['userfile']);
$Distination='';
for ($i=0;$i<count($file_array);$i++)
{
$Distination= '../../images/catering/'.$file_array[$i]['name'];
$error=MutipleUploadFile($file_array[$i],$Distination);
if(count($error)>0)
{
echo '<h4 class="badge-danger">'.$file_array[$i]['name'].'.'.$error[0].'</h4>';
}
else
{
$sql='INSERT INTO `images`(`id`, `image`, `expire`, `catering_id`, `hall_id`) VALUES (NULL,"'.$Distination.'",NULL,'.$cateringid.',NULL)';
querySend($sql);
}
}
unset($_FILES['userfile']);
}
?>
<hr class="mt-3 mb-5 border-white">
<div class="row text-center text-lg-left" style="height: 70vh;overflow: auto">
<?php
$sql='SELECT `id`, `image` FROM `images` WHERE catering_id='.$cateringid.'' ;
echo showGallery($sql);
?>
</div>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$(document).on("change",".changeDishType",function ()
{
var id=$(this).data("dishtypeid");
var value=$(this).val();
$.ajax({
url:"dish/dishServer.php",
data:{id:id,value:value,option:"changeDishType"},
dataType:"text",
method:"POST",
success:function (data)
{
if(data!="")
{
alert(data);
}
}
});
});
$(document).on("click",".Delele_Dish_Type",function ()
{
var id=$(this).data("dishtypeid");
var value=$(this).val();
$.ajax({
url:"dish/dishServer.php",
data:{value:value,id:id,option:"Delele_Dish_Type"},
dataType:"text",
method:"POST",
success:function (data)
{
if(data!="")
{
alert(data);
}
else
{
location.reload();
}
}
});
});
$("#submiteditcatering").click(function () {
var formdata = new FormData($("#formcatering")[0]);
formdata.append("option", "cateringedit");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data) {
if (data != '')
{
alert(data);
return false;
} else
{
window.location.href="../companyRegister/companyEdit.php";
}
}
});
});
});
</script>
</body>
</html><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
if(!isset($_GET['is_active']))
{
exit();
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container" style="margin-top:150px">
<h1 align="center"> Orders</h1>
<form class="col-12 shadow card mb-4" id="formId1" style="display: none">
<h2>Search order :</h2>
<div class="form-group row">
<label class="col-form-label col-4"> customer name</label>
<input name="p_name" type="text" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> customer CNIC</label>
<input name="p_cnic" type="number" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> customer ID</label>
<input name="p_id" type="number" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> customer phone</label>
<input name="n_number" type="text" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4">booking Date</label>
<input name="ot_booking_date" type="date" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> destination date</label>
<input name="ot_destination_date" type="date" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4">order status</label>
<select name="ot_is_active" class="changeColumn form-control col-8 ">
<option value="None">None</option>
<?php
$OrderStatus=array("running","cancel","delieved","clear");
for($i=0;$i<count($OrderStatus);$i++)
{
echo '<option value='.$i.'>'.$OrderStatus[$i].'</option>';
}
?>
</select>
</div>
<div class="form-group row">
<a href="/Catering/user/userDisplay.php" class="col-4 form-control btn-danger">cancel</a>
<button type="button" class="col-4 form-control btn-success">Find</button>
</div>
</form>
<h3 align="center" ><button data-display="hide" id="searchBtn" class="btn-outline-info btn float-left ">Search Order</button>display records</h3>
<div id="recordsAll">
<?php
$sql='SELECT p.id,p.name,ot.destination_date,ot.id FROM person as p INNER join number as n on p.id=n.person_id
INNER join orderTable as ot
on p.id=ot.person_id
WHERE
ot.is_active='.$_GET['is_active'].'
ORDER BY ot.destination_date DESC';
$records=queryReceive($sql);
$displayRecord='';
if(count($records)>0)
{
$displayRecord .= '<div class="form-group row border mb-0 p-1">
<label class="font-weight-bold col-form-label col-2">order Id</label>
<label class="font-weight-bold col-form-label col-5">customer Name</label>
<label class="font-weight-bold col-form-label col-3">destination Date</label>
<label class="font-weight-bold col-form-label col-2">Detail</label>
</div>';
for ($j=0;$j<count($records);$j++)
{
$displayRecord .= ' <div class="form-group row border">
<label class="col-form-label col-2">'.$records[$j][3].'</label>
<label class="col-form-label col-5">'.$records[$j][1].'</label>
<label class="col-form-label col-3">'.$records[$j][2].'</label>
<a href="/Catering/order/PreviewOrder.php?order='.$records[$j][3].'" class="btn-primary col-2 form-control ">Detail</a>
</div>';
}
}
else
{
$displayRecord = '<h2 align="center">Not Found</h2>';
}
echo $displayRecord
?>
</div>
</div>
<script>
$(document).ready(function () {
$(document).on("change",'.changeColumn',function (e)
{
e.preventDefault();
var formdata=new FormData($('#formId1')[0]);
$.ajax({
url:"FindOrderServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
$("#recordsAll").html(data);
// console.log(data);
}
});
});
$("#searchBtn").click(function () {
var display=$(this).data("display");
if(display=="hide")
{
$("#formId1").show('slow');
$(this).data("display","show");
}
else
{
$("#formId1").hide('slow');
$(this).data("display","hide");
}
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
session_start();
if(isset($_SESSION["userid"]))
{
header('location:userDisplay.php');
exit();
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body>
<div class="badge-danger w-100 shadow fixed-top " style="height: 170px">
<h1 align="center">Welcome to</h1>
<h2 align="center"> New Kashmir Food Center</h2>
</div>
<div class="container badge-dark p-0 " style="margin-top:180px" >
<h1 align="center">User Login</h1>
<form class="" id="formLogin">
<div class="form-group row">
<label class="col-form-label col-4">User Name</label>
<input type="text" class="col-8 form-control" name="username">
</div>
<div class="form-group row">
<label class="col-form-label col-4">Password</label>
<input type="<PASSWORD>" class="col-8 form-control" name="password">
</div>
<div class="form-group row">
<input id="login" type="button" class="form-control btn btn-success" value="logIN">
</div>
</form>
</div>
<script>
$(document).ready(function () {
$('#login').click(function ()
{
var formdata=new FormData($("#formLogin")[0]);
formdata.append("option","login");
$.ajax({
url:"userServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
location.reload();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
include_once ("../../connection/connect.php");
$packageid=$_GET['packageid'];
$hallid=$_GET['hallid'];
$companyid=$_GET['companyid'];
$hallBranches=$_GET['hallBranches'];
$sql='SELECT `id`, `month`, `isFood`, `price`, `describe`, `dayTime`, `expire`, `hall_id`, `package_name` FROM `hallprice` WHERE id='.$packageid.'';
$packageDetail=queryReceive($sql);
$sql='SELECT name,id FROM systemDishType WHERE ISNULL(isExpire)';
$dishtype=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0;
padding: 0;
}
</style>
</head>
<body>
<h1 align="center">Add new Package</h1>
<div class="form-group row">
<lable class="col-4 col-form-label">Packages Name</lable>
<input data-columnname="package_name" class="packagechange col-8 form-control" type="text" value="<?php echo $packageDetail[0][8]?>">
</div>
<div class="form-group row">
<lable class="col-4 col-form-label">Packages Rate per head</lable>
<input data-columnname="price" class="packagechange col-3 form-control" type="number" value="<?php echo $packageDetail[0][3]?>">
</div>
<div class="form-group row">
<lable class="col-4 col-form-label">Packages Description</lable>
<input data-columnname="describe" type="text" class="packagechange col-6 form-control" value="<?php echo $packageDetail[0][4]?>" >
</div>
<form id="submitpackage">
<h3 align="center"> Selected Menu of Package</h3>
<div id="selectedmenu" class="alert-warning row form-group shadow" style="height: 40vh">
<?php
$sql='SELECT `id`, `dishname`, `image`, `expire`, `hallprice_id` FROM `menu` WHERE (hallprice_id='.$packageid.') AND ISNULL(expire)';
$menuDetail=queryReceive($sql);
for($i=0;$i<count($menuDetail);$i++)
{
echo '
<div id="alreadydishid'.$menuDetail[$i][0].'" class="col-3 alert-danger border m-2 form-group" style="height: 30vh;" >
<img src="'.$menuDetail[$i][2].'" class="col-12" style="height: 15vh">
<p class="col-form-label" class="form-control col-12">'.$menuDetail[$i][1].'</p>
<input data-dishid="'.$menuDetail[$i][0].'" type="button" value="Remove" class="form-control alreadydishid col-12 btn btn-success">
</div>';
}
?>
</div>
<div class="col-12">
<input id="btncancel" type="button" value="<?php
if($packageDetail[0][6]==NULL)
{
echo "Click Expire";
}
else
{
echo "Click Show";
}
?>" class="btn btn-danger col-4">
<input id="btnsubmit" type="button" value="OK" class="btn btn-primary col-4">
</div>
</form>
<h3 align="center" class="mt-5">Select Dishes</h3>
<div id="selectmenu" class="alert-dark border m-2 form-group row shadow" >
<?php
for ($i=0;$i<count($dishtype);$i++)
{
$sql = 'SELECT `name`, `id`, `image` FROM `systemDish` WHERE ISNULL(isExpire) AND (systemDishType_id=' . $dishtype[$i][1] . ') ';
$dishdetail=queryReceive($sql);
for ($j=0;$j<count($dishdetail);$j++)
{
echo '
<div id="dishid'.$dishdetail[$j][1].'" class="col-3 alert-danger border m-2 form-group" style="height: 30vh;" >
<img src="'.$dishdetail[$j][2].'" class="col-12" style="height: 15vh">
<p class="col-form-label" class="form-control col-12">'.$dishdetail[$j][0].'</p>
<input data-dishid="'.$dishdetail[$j][1].'" type="button" value="Select" class="form-control col-12 touchdish btn btn-success">
<input hidden type="text" name="dishname[]" value="'.$dishdetail[$j][0].'">
<input hidden type="text" name="image[]" value="'.$dishdetail[$j][2].'">
</div>';
}
}
?>
</div>
<script>
$(document).ready(function () {
$(".packagechange").change(function () {
var columnname=$(this).data("columnname");
var value=$(this).val();
var formdata=new FormData;
formdata.append("option","packagechange");
formdata.append("packageid",<?php echo $packageid;?>);
formdata.append("value",value);
formdata.append("columnname",columnname);
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
$(document).on("click",".touchdish",function ()
{
var value=$(this).val();
var id=$(this).data("dishid");
if(value=="Remove")
{
$(this).val("Select");
var text=$("#dishid"+id)[0].outerHTML;
$("#dishid"+id).remove();
$("#selectmenu").append(text);
}
else
{
$(this).val("Remove");
var text=$("#dishid"+id)[0].outerHTML;
$("#dishid"+id).remove();
$("#selectedmenu").append(text);
}
}) ;
$("#btnsubmit").click(function ()
{
var formdata=new FormData($('#submitpackage')[0]);
formdata.append("option","Extendmenu");
formdata.append("packageid",<?php echo $packageid;?>)
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
$("#btncancel").click(function ()
{ var value=$(this).val();
var formdata=new FormData;
formdata.append("option","ExpireBtn");
formdata.append("packageid",<?php echo $packageid;?>);
formdata.append("expirevalue",value);
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
$(".alreadydishid").click(function ()
{
var id= $(this).data("dishid");
$.ajax({
url:"../companyServer.php",
method:"POST",
data:{option:"alreadydishremove",id:id},
dataType:"text",
success:function (data)
{
if(data!="")
{
alert(data);
}
else
{
$("#alreadydishid"+id).remove();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../connection/connect.php");
$dishID=$_GET['dishid'];
$sql='SELECT d.name,(SELECT dt.name FROM dish_type as dt WHERE dt.id=d.dish_type_id), d.image, d.dish_type_id, d.isExpire FROM dish as d WHERE d.id='.$dishID.'';
$dishDetail=queryReceive($sql);
$sql='SELECT `name`, `id`, `dish_id`, `isExpire` FROM `attribute` WHERE ISNULL(isExpire) AND (dish_id='.$dishID.')';
$attributes=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once("../../webdesign/header/headerclient.php");
?>
<div class="container" style="margin-top:150px">
<div class="col-12 shadow card p-4">
<input id="dishid" type="number" hidden value="<?php echo $dishID; ?>">
<div class="form-group row">
<a href="/Catering/system/dish/dishesDetail.php" class=" form-control col-4 btn-warning">Previous</a>
<span class="font-weight-bold text-center col-9 form-control"> Edit Dish in System</span>
</div>
<div class="form-group row">
<img style="height: 30vh " src="<?php echo $dishDetail[0][2]; ?>" class="col-8 form-control" alt="Image is not set" >
</div>
<div class="form-group row">
<label class="col-4 col-form-label">Dish Name</label>
<input data-column="name" value="<?php echo $dishDetail[0][0]; ?>" class="dishchange col-8 form-control" type="text">
</div>
<form id="formImage">
<div class="form-group row">
<label class="col-4 col-form-label"> Changes images</label>
<input id="dishImage" name="image" class="col-8 form-control" type="file">
<input type="text" hidden name="imagepath" value="<?php echo $dishDetail[0][2]; ?>">
</div>
</form>
<div class="form-group row">
<label class="col-4 col-form-label">Dish Type</label>
<select data-column="dish_type_id" class="dishchange col-8 form-control">
<?php
echo '<option value="'.$dishDetail[0][3].'">'.$dishDetail[0][1].'</option>';
$sql='SELECT `id`, `name` FROM `dish_type` WHERE id!='.$dishDetail[0][3].'' ;
$dish_type=queryReceive($sql);
//print_r($dish_type);
for($i=0;$i<count($dish_type);$i++)
{
echo '<option value="'.$dish_type[$i][0].'">'.$dish_type[$i][1].'</option>';
}
?>
</select>
</div>
<div class="col-12 card mb-3 p-4" id="existAttributes">
<h4 align="center">Exist Attributes</h4>
<?php
for($i=0;$i<count($attributes);$i++)
{
echo ' <div class="form-group row " id="delete_'.$attributes[$i][1].'">
<label class="col-4 col-form-label">Attribute Name</label>
<input data-attributeid="'.$attributes[$i][1].'" value="'.$attributes[$i][0].'" class="changeAttributes col-6 form-control" type="text">
<input data-attributeid="'.$attributes[$i][1].'" type="button" class="RemoveAttribute col-2 form-control btn-secondary" value="-">
</div>';
}
?>
</div>
<h4 align="center">New attribute</h4>
<div class="form-group row">
<label class="col-4 col-form-label">Attribute Name</label>
<input id="attributetext" class="col-6 form-control" type="text">
<input id="addAttribute" type="button" class="col-2 form-control btn-primary" value="+">
</div>
<form id="formAttribute">
<div class="col-12" id="attributeHere">
</div>
</form>
<div class="form-group row">
<?php
if($dishDetail[0][4]=="")
{
echo '<input id="RemoveDish" type="button" class=" col-4 form-control btn-danger" value="Hide dish">';
}
else
{
echo '<input id="RemoveDish" type="button" class=" col-4 form-control btn-primary " value="Show dish">';
}
?>
<input id="submit" type="button" value="Submit" class="col-8 form-control btn-success">
</div>
</div>
</div>
<script>
//window.history.back();
$(document).ready(function ()
{
var dishid=$("#dishid").val();
$("#RemoveDish").click(function ()
{
var value=$(this).val();
$.ajax({
url:"dishServer.php",
method:"POST",
data:{value:value,dishid:dishid,option:"ExpireDish"},
dataType:"text",
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.location.href="/Catering/system/dish/dishesDetail.php";
}
}
});
});
var rows=0;
$("#addAttribute").click(function ()
{
var text=$("#attributetext").val();
$("#attributeHere").append('<div class="col-12 form-group row" id="removeid_'+rows+'">\n' +
' <label class="col-4 col-form-label">Attribute Name</label>\n' +
' <input value="'+text+'" name="attribute[]" class="col-6 form-control" type="text">\n' +
' <input data-removeid="'+rows+'" type="button" class="col-2 form-control btn-danger removeattribute" value="-">\n' +
' </div>');
$("#attributetext").val("");
rows++;
}) ;
$(document).on('click','.removeattribute',function ()
{
var id=$(this).data("removeid");
$("#removeid_"+id).remove();
});
$("#submit").click(function (e)
{
e.preventDefault();
var dishid=$("#dishid").val();
var formdata=new FormData($("#formAttribute")[0]);
formdata.append("option","attributesCreate");
formdata.append("dishid",dishid);
$.ajax({
url:"dishServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.location.href="/Catering/system/dish/dishesDetail.php";
}
}
});
});
$(document).on("change",'.changeAttributes',function () {
var attributeid=$(this).data("attributeid");
var text=$(this).val();
$.ajax({
url:"dishServer.php",
method: "POST",
data: {attributeid:attributeid,text:text,option:"changeAttributes"},
dataType:"text",
success:function (data)
{
if(data!='')
{
alert(data);
}
}
});
});
$(document).on("click",'.RemoveAttribute',function () {
var attributeid=$(this).data("attributeid");
$.ajax({
url:"dishServer.php",
method: "POST",
data: {attributeid:attributeid,option:"RemoveAttribute"},
dataType:"text",
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
$("#delete_"+attributeid).remove();
}
}
});
});
$(document).on("change",'.dishchange',function () {
var dishid=$("#dishid").val();
var column=$(this).data("column");
var text=$(this).val();
$.ajax({
url:"dishServer.php",
method: "POST",
data: {dishid:dishid,column:column,text:text,option:"dishchanges"},
dataType:"text",
success:function (data)
{
if(data!='')
{
alert(data);
}
}
});
});
$("#dishImage").change(function ()
{
var formData=new FormData($("#formImage")[0]);
formData.append("dishId",dishid);
formData.append("option","changeImage");
$.ajax({
url:"dishServer.php",
method:"POST",
data:formData,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
location.reload();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-07
* Time: 13:49
*/
include_once ("../connection/connect.php");
$orderid=$_GET['order'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container" style="margin-top:180px">
<h1 align="center">Preview of Dish</h1>
<?php
$display='';
$dishId=$_GET['dishId'];
$dishDetailId=$_GET['dishDetailId'];
$sql = 'SELECT d.id,d.name FROM dish as d WHERE d.id=' . $dishId . '';
$dishDetail = queryReceive($sql);
$display .= '
<form class="col-12" id="form">
<div class="border shadow-lg p-4 mb-4 bg-white col-12">
<h2 align="center">' . $dishDetail[0][1] . '</h2>
<input hidden id="dishDetailID" value="'.$dishDetailId.'">
';
$sql = 'SELECT an.id,an.quantity,a.name FROM dish_detail as dd inner join attribute_name as an
on dd.id=an.dish_detail_id
INNER join attribute as a
on a.id=an.attribute_id
WHERE dd.id='.$dishDetailId.'';
$attributeDetail = queryReceive($sql);
for ($j = 0; $j < count($attributeDetail); $j++) {
$display .= ' <div class="form-group row">
<label class="col-form-label col-4">' . $attributeDetail[$j][2] . '</label>
<input data-attributeid="'. $attributeDetail[$j][0] .'" class=" attributeChange form-control col-8" type="number" value="'. $attributeDetail[$j][1] .'">
</div>';
}
$sql='SELECT `describe`, `price`, `quantity` FROM `dish_detail` WHERE id='.$dishDetailId.'';
$dishDetailOfDetai=queryReceive($sql);
$display .= ' <div class="form-group row">
<label class="col-form-label col-4">each price</label>
<input data-column="price" class="dishDetailChange form-control col-8" type="number" value="'.$dishDetailOfDetai[0][1].'">
</div>
<div class="form-group row">
<label class="col-form-label col-4">Quantity</label>
<input data-column="quantity" class="dishDetailChange form-control col-8" type="number" value="'.$dishDetailOfDetai[0][2].'">
</div>
<div class="form-group row">
<label class="col-form-label col-4">describe</label>
<input data-column="describe" class="dishDetailChange form-control col-8" type="text" value="'.$dishDetailOfDetai[0][0].'"></input>
</div>
<div class="form-group row">';
if(isset($_GET['option']))
{
if($_GET['option']=="Allselected")
{
$display.='<a href="/dish/AllSelectedDishes.php?order='.$_GET['order'].'&option=PreviewOrder" class="submitForm form-control btn col-4 btn-primary">Done</a>
<input id="cancel_dish" type="button" class="cancelForm form-control btn col-4 btn-danger" value="dish cancel">';
}
}
else
{
$display .= '<input id="cancel_dish" type="button" class="cancelForm form-control btn col-4 btn-danger" value="dish cancel">
<input id="ok" type="button" class="submitForm form-control btn col-4 btn-primary" value="ok">';
}
$display.='</div>
</div>
</form>';
echo $display;
?>
</div>
<script>
$(document).ready(function () {
$(document).on('change','.attributeChange',function () {
var attributeid=$(this).data('attributeid');
var valueAttribute=$(this).val();
$.ajax({
url:".php",
data:{attributeid:attributeid,value:valueAttribute,option:"attributeChange"},
method:"POST",
dataType:"text",
success:function (data)
{
if(data!="")
{
alert(data);
}
}
});
}) ;
$(document).on('change','.dishDetailChange',function () {
var dishDetailId=$("#dishDetailID").val();
var columnName=$(this).data("column");
var columnValue=$(this).val();
$.ajax({
url:".php",
data: {dishDetailId:dishDetailId,columnName:columnName,columnValue:columnValue,option:"dishDetailChange" },
dataType: "text",
method:"POST",
success:function (data) {
if(data!="")
{
console.log(data);
}
}
});
});
$('#cancel_dish').click(function ()
{
var dishDetailId=$("#dishDetailID").val();
$.ajax({
url:".php",
data: {dishDetailId:dishDetailId,option:"deleteDish" },
dataType: "text",
method:"POST",
success:function (data) {
if(data!="")
{
console.log(data);
}
else
{
window.location.href="/dish/AllSelectedDishes.php?order=<?php echo json_decode($orderid);?>";
}
}
});
});
$('#ok').click(function ()
{
window.location.href="/dish/AllSelectedDishes.php?order=<?php echo json_decode($orderid);?>";
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
$userId=$_COOKIE['userid'];
$orderDetail_id=$_SESSION['order'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://primerevenue.com/wp-content/uploads/2016/08/News_New-Blogs_005blog-understanding-early-payment-discount-terms.jpg);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-body text-center" style="opacity: 0.7 ;background: #fdfdff;">
<h3 ><i class="fas fa-history fa-2x mr-2"></i> Payment History </h3>
<h5>All history of transfer payments</h5>
</div>
</div>
<div class="row justify-content-center col-12" style="margin-top: -60px">
<div class="card text-center card-header">
<img src="<?php
if($_GET['image']=="")
{
echo 'https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
else
{
echo $_GET['image'];
}
?> " style="height: 20vh;" class="figure-img rounded-circle" alt="image is not set">
<h5 ><?php
echo $_GET['name'];
?></h5>
<label >Order ID:<?php
echo $orderDetail_id;
?></label>
</div>
</div>
<div class="container">
<div class="col-12 shadow border card" style="background-color: #80bdff">
<?php
$sql='SELECT py.id,(SELECT u.username FROM user as u where u.id=py.user_id) as sender,
(SELECT u.username FROM user as u where u.id=t.user_id) as receiver,py.amount,
t.senderTimeDate,t.Isconfirm,py.receive,py.nameCustomer,py.IsReturn,t.Isget
FROM orderDetail as ot INNER JOIN payment as py
on ot.id=py.orderDetail_id
INNER join transfer as t
on py.id=t.payment_id
WHERE (ot.id='.$orderDetail_id.')';
$historyPayment=queryReceive($sql);
$display='';
for($k=0;$k<count($historyPayment);$k++)
{
$display.=' <div class="col-12 shadow border card-body mt-3" >
<div class="form-group row" >
<label class="col-4 col-form-label" > Payment Id </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][0].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Sender User </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][1].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Receive User </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][2].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Amount</label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][3].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Sending Date </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][4].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Receiving Date </label >
<label class="col-8 col-form-label" > ';
if($historyPayment[$k][5]=="")
{
$display.= "request has delivered for confirm to user";
}
else
{
$display.= $historyPayment[$k][5];
}
$display.= ' </label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Geting payment Date </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][6].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Customer Name </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][7].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > payment status </label >
<label class="col-8 col-form-label" > ';
if($historyPayment[$k][8]==0)
{
$display.='get payment from customer';
}
else
{
$display.='return payment to customer';
}
$display.='</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > transfer Status </label >
<label class="col-8 col-form-label" > ';
if($historyPayment[$k][9]==0)
{
$display.="not confirm";
}
else
{
$display.="yes,I get the amount from user";
}
$display.= '
</label >
</div >
</div >';
echo $display;
}
?>
</div>
<h1 align = "center" >Your received Payment </h1 >
<div class="col-12">
<?php
$sql='SELECT py.id,(SELECT u.username FROM user as u where u.id=py.user_id), py.amount,py.receive,py.nameCustomer,py.IsReturn FROM orderDetail as ot INNER JOIN payment as py on ot.id=py.orderDetail_id WHERE (ot.id='.$orderDetail_id.') AND (py.sendingStatus=0)';
$WhyPayment=queryReceive($sql);
$display='';
for($t=0;$t<count($WhyPayment);$t++)
{
$display.='<div class="col-12 shadow border card-body mb-3" >
<div class="form-group row" >
<label class="col-4 col-form-label" > Payment Id </label >
<label class="col-8 col-form-label" > '.$WhyPayment[$t][0].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > User Name </label >
<label class="col-8 col-form-label" > '.$WhyPayment[$t][1].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Amount</label >
<label class="col-8 col-form-label" > '.$WhyPayment[$t][2].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Receiving Date </label >
<label class="col-8 col-form-label" > '.$WhyPayment[$t][3].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Customer Name </label >
<label class="col-8 col-form-label" > '.$WhyPayment[$t][4].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > payment status </label >
<label class="col-8 col-form-label" > ';
if($WhyPayment[$t][5]==0)
{
$display.='get payment from customer';
}
else
{
$display.='return payment to customer';
}
$display.='</label >
</div >
</div >';
}
echo $display;
?>
</div>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container" style="margin-top:150px" >
<form id="form">
<p align="center" class="col-12 mb-4">
Customer create
</p>
<input id="customer" hidden value="">
<div class="form-group row">
<label for="number" class="col-3 col-form-label">Phone no:</label>
<input id="number"class="allnumber form-control col-7" type="number" name="number[]" >
<input type="button" class="form-control btn-primary col-2" id="Add_btn" value="+">
</div>
<div class="col-12 border mb-3 " id="number_records">
</div>
<div class="form-group row">
<label for="name" class="col-form-label col-3">Name:</label>
<input type="text" id="name" name="name"class="form-control col-9" >
</div>
<div class="form-group row">
<label for="name" class="col-form-label col-3">Image:</label>
<input type="file" name="image" class="form-control col-9" >
</div>
<div class="form-group row">
<label for="cnic" class="col-form-label col-3">CNIC:</label>
<input type="number" id="cnic" name="cnic" class="form-control col-9" >
</div>
<h3 align="center"> Address</h3>
<div class="form-group row">
<label for="city" class="col-form-label col-3">City:</label>
<input type="text" id="city" name="city" class="form-control col-9" >
</div>
<div class="form-group row">
<label for="area" class="col-form-label col-3">Area/ Block:</label>
<input type="text" id="area" name="area" class="form-control col-9">
</div>
<div class="form-group row">
<label for="streetNo" class="col-form-label col-3">Street No :</label>
<input type="number" id="streetNo" name="streetNo" class="form-control col-9">
</div>
<div class="form-group row">
<label for="houseNo" class="col-form-label col-3">House No:</label>
<input type="number" id="houseNo" name="houseNo" class="form-control col-9">
</div>
<div class="form-group row col-12">
<?php
if(isset($_GET['option']))
{
if($_GET['option']=="userDisplay")
{
echo '
<button class="col-5 form-control btn btn-danger" id="cancelCustomer">cancel</button>
<button class="col-5 form-control btn btn-outline-primary" id="submit">submit</button>';
}
else
{
echo '
<a href="/Catering/user/userDisplay.php" class=" col-5 form-control btn btn-danger">cancel</a>
<button class="col-5 form-control btn btn-outline-primary" id="submit">submit</button>';
}
}
else
{
echo '
<a href="/Catering/user/userDisplay.php" class=" col-5 form-control btn btn-danger">cancel</a>
<button class="col-5 form-control btn btn-outline-primary" id="submit">submit</button>';
}
?>
</div>
</form>
</div>
<script>
$(document).ready(function ()
{
$(document).on("change",".allnumber",function ()
{
//number exist
var value=$(this).val();
$.ajax({
url:"customerBookingServer.php",
data:{value:value,option:"customerExist"},
dataType:"text",
method: "POST",
success:function (data)
{
if((!($.isNumeric(data))) && (data==""))
{
return false;
}
else
{
window.location.href="/Catering/customer/customerEdit.php?customer="+data+"&option=CustomerCreate";
}
}
});
});
$("#cancelCustomer").click(function (e)
{
e.preventDefault();
window.history.back();
return false;
});
var number=0;
$('.number_records').map(function () {
number++;
}).get().join();
$("#Add_btn").click(function ()
{
if(number>1)
{
alert("no of numbers not more then 3");
return false;
}
$("#number_records").append("<div class=\"form-group row\" id=\"Each_number_row_"+number+"\">\n" +
" <label for=\"number_"+number+"\" class=\"col-2 col-form-label\">#</label>\n" +
" <input id=\"number_"+number+"\" class=\"allnumber form-control col-8\" type=\"number\" name=\"number[]\">\n" +
" <input class=\"form-control btn btn-danger col-2 remove_number \" id=\"remove_numbers_"+number+"\" data-removenumber=\""+number+"\" value=\"-\">\n" +
" </div>");
number++;
});
$(document).on("click",".remove_number",function () {
var id=$(this).data("removenumber");
$("#Each_number_row_"+id).remove();
number--;
});
$("#submit").click(function (e) {
e.preventDefault();
if($.trim($("#number").val())=="")
{
alert("number must be enter");
return false;
}
if($.trim($("#name").val())=="")
{
alert("name must be enter");
return false;
}
var formdata=new FormData($('form')[0]);
formdata.append("option","customerCreate");
$.ajax({
url:"customerBookingServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(!($.isNumeric(data)))
{
alert(data);
return false;
}
else
{
window.location.href="/Catering/order/orderCreate.php?customer="+data+"&option=CustomerCreate";
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-18
* Time: 10:45
*/
include_once ("../connection/connect.php");
if(isset($_GET['action']))
{
$_SESSION['order']=$_GET['order'];
$_SESSION['customer']=$_GET['customer'];
header("location:../order/PreviewOrder.php");
}
$hallid="";
$cateringid='';
if(isset($_SESSION['branchtype']))
{
if($_SESSION['branchtype']=="hall")
{
$hallid=$_SESSION['branchtypeid'];
}
else
{
$cateringid=$_SESSION['branchtypeid'];
}
}
$hallorcater='';
if(!empty($hallid))
{
$hallorcater="(od.hall_id=".$hallid.")";
}
else
{
$hallorcater="(od.catering_id=".$cateringid.")";
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/complete.css">
<style>
.newcolor
{
background: #77A1D3; /* fallback for old browsers */
background: -webkit-linear-gradient(to right, #E684AE, #79CBCA, #77A1D3); /* Chrome 10-25, Safari 5.1-6 */
background: linear-gradient(to right, #E684AE, #79CBCA, #77A1D3); /* W3C, IE 10+/ Edge, Firefox 16+, Chrome 26+, Opera 12+, Safari 7+ */
}
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://www.opengovguide.com/wp-content/uploads/2019/07/RM_Banner_Large.jpg);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 class="text-dark"> <i class="fab fa-amazon-pay fa-2x"></i>Records managements</h3>
<p>Check All orders remaining amount,total amount,Event Guru system calculated amount </p>
<button data-display="hide" id="searchBtn" class="btn-warning btn justify-content-center "><i class="fas fa-search"></i>Search Order</button>
</div>
</div>
<div class="container">
<form class="col-12 shadow mb-4 newcolor card " id="formId1" style="display: none">
<div class="form-group row">
<label class="col-form-label"> Customer name</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user"></i></span>
</div>
<input name="p_name" type="text" class="changeColumn form-control" placeholder="or customer name etc ali,....">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Customer CNIC</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-id-card"></i></span>
</div>
<input name="p_cnic" type="number" class="changeColumn form-control" placeholder="or cnic 23212xxxxx">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Customer ID</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-id-card"></i></span>
</div>
<input name="p_id" type="number" class="changeColumn form-control" placeholder="customer ID 1,2,3,4,.....">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Customer phone</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-mobile-alt"></i></span>
</div>
<input name="n_number" type="text" class="changeColumn form-control" placeholder="number 03231xxxxxx">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Booking Date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-calendar-alt"></i></span>
</div>
<input name="od_booking_date" type="date" class="changeColumn form-control">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Destination Date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-business-time"></i></span>
</div>
<input name="od_destination_date" type="date" class="changeColumn form-control">
</div>
</div>
<div class="form-group row">
<label class="col-form-label ">order status</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-eye"></i></span>
</div>
<select name="<?php
if($hallid=="")
{
echo "od_status_catering";
}
else
{
echo "od_status_hall";
}
?>" class="changeColumn form-control">
<option value="None">None</option>
<?php
$OrderStatus=array("Running","Cancel","Delieved","Clear");
for($i=0;$i<count($OrderStatus);$i++)
{
echo '<option value='.$OrderStatus[$i].'>'.$OrderStatus[$i].'</option>';
}
?>
</select>
</div>
</div>
<div class="form-group row justify-content-center">
<button type="button" class="form-control btn-success col-6"><i class="fas fa-search"></i>Find</button>
</div>
</form>
<div class="w-100" id="recordsAll1">
<?php
$sql="SELECT DISTINCT od.id, (SELECT p.name FROM person as p WHERE p.id=od.person_id), (SELECT sum(py.amount) FROM payment as py WHERE (py.IsReturn=0)AND(py.orderDetail_id=od.id)) ,od.total_amount,od.total_amount, (SELECT SUM(dd.price*dd.quantity) FROM dish_detail as dd WHERE dd.orderDetail_id=od.id),od.status_catering,od.status_hall,od.person_id FROM orderDetail as od LEFT join payment as py on od.id=py.orderDetail_id where ".$hallorcater."";
echo showRemainings($sql);
?>
</div>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$(document).on("click",".clickable-row",function ()
{
window.location = $(this).data("href");
});
$(document).on("change",'.changeColumn',function (e)
{
e.preventDefault();
var formdata=new FormData($('#formId1')[0]);
formdata.append("hallorcater","<?php echo $hallorcater;?>");
$.ajax({
url:"RemainingFinderServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
$("#recordsAll1").html(data);
}
});
});
$("#searchBtn").click(function () {
var display=$(this).data("display");
if(display=="hide")
{
$("#formId1").show('slow');
$(this).data("display","show");
}
else
{
$("#formId1").hide('slow');
$(this).data("display","hide");
}
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-03
* Time: 17:20
*/
include_once ("../../connection/connect.php");
$companyid=$_COOKIE['companyid'];
if(isset($_POST['option']))
{
if($_POST['option']=="createUser")
{
$username=chechIsEmpty($_POST['username']);
$password=chechIsEmpty($_POST['password']);
$sql='SELECT u.id FROM user as u WHERE (u.password="'.$password.'") AND (u.username="'.$username.'")';
$userExist=queryReceive($sql);
if(count($userExist)!=0)
{
echo "user is already exist";
exit();
}
$image='';
if(!empty($_FILES['image']["name"]))
{
$image = "../../images/users/" . $_FILES['image']['name'];
$resultimage = ImageUploaded($_FILES, $image);//$dishimage is destination file location;
if ($resultimage != "") {
print_r($resultimage);
exit();
}
$image =$_FILES['image']['name'];
}
$name = trim($_POST['name']);
$numberArray = $_POST['number'];
$isowner=0;
if(isset($_POST['isowner']))
{
if($_POST['isowner']=="yes")
{
$isowner=1;
}
}
$cnic = $_POST['cnic'];
$city = $_POST['city'];
$area = $_POST['area'];
$streetNo = chechIsEmpty($_POST['streetNo']);
$houseNo = chechIsEmpty($_POST['houseNo']);
$date = date('Y-m-d');
$sql = 'INSERT INTO `person`(`name`, `cnic`, `id`, `date`, `image`) VALUES ("'.$name.'","'.$cnic.'",NULL,"'.$date.'","'.$image.'")';
querySend($sql);
$last_id = mysqli_insert_id($connect);
$sql="INSERT INTO `address` (`id`, `address_street_no`, `address_house_no`, `person_id`, `address_city`, `address_town`) VALUES (NULL, '".$streetNo."', '".$houseNo."', '".$last_id."', '".$city."', '".$area."');";
querySend($sql);
for ($i=0;$i<count($numberArray);$i++)
{
$sql = "INSERT INTO `number`(`number`, `id`, `is_number_active`, `person_id`) VALUES ('".$numberArray[$i]."',NULL,1,$last_id)";
querySend($sql);
}
$customerId = $last_id;
$sql='INSERT INTO `user`(`id`, `username`, `password`, `person_id`, `isExpire`,`isowner`,`company_id`) VALUES (NULL,"'.$username.'","'.$password.'",'.$customerId.',NULL,"'.$isowner.'",'.$companyid.')';
querySend($sql);
}
if($_POST['option']=="change")
{
$customerId = $_POST['customerid'];
$column_name = $_POST['columnname'];
$text = chechIsEmpty($_POST['value']);
$number_table = $_POST['edittype'];
if ($number_table == 1) {
//address table change
$sql = 'UPDATE address as a SET a.' . $column_name . '="' . $text . '" WHERE a.person_id=' . $customerId . ' ';
querySend($sql);
} else if ($number_table == 2) {
//person change table change
$sql = 'UPDATE person as p SET p.' . $column_name . '="' . $text . '" WHERE p.id=' . $customerId . ' ';
querySend($sql);
} else if ($number_table == 3) {
//number table change
$numberId = $_POST['id'];
$sql = 'UPDATE number as n SET n.' . $column_name . '="' . $text . '" WHERE (n.person_id=' . $customerId . ') AND (n.id=' . $numberId . ')';
querySend($sql);
}
}
else if($_POST['option']=="deleteNumber")
{
$id=$_POST['id'];
$sql='DELETE FROM number WHERE id='.$id.'';
querySend($sql);
}
else if($_POST['option']=="addNumber")
{
$customerId = $_POST['customerid'];
$numberText=$_POST['number'];
$sql='INSERT INTO `number`(`number`, `id`, `is_number_active`, `person_id`) VALUES ("'.$numberText.'",NULL,1,"'.$customerId.'")';
querySend($sql);
}
else if($_POST['option']=="changeImage")
{
$customerid=$_POST['customerid'];
$previouspath=$_POST['image'];
$image="../../images/users/".$_FILES['image']['name'];
$resultimage=ImageUploaded($_FILES,$image);//$dishimage is destination file location;
if($resultimage!="")
{
print_r($resultimage);
exit();
}
$image=$_FILES['image']['name'];
$sql='UPDATE person as p SET p.image="'.$image.'" WHERE p.id='.$customerid.';';
querySend($sql);
if (file_exists($previouspath))
{
$deleted = unlink($previouspath);
}
}
else if ($_POST['option']=="authorChange")
{
$userid=$_POST['userid'];
$username=$_POST['username'];
$password=$_POST['<PASSWORD>'];
$password1=$_POST['<PASSWORD>'];
// $isowner=0;
// if(isset($_POST['isowner']))
// {
// $isowner=1;
// }
if(strlen($username)<5)
{
echo "username must be greater then 5 letters";
exit();
}
if(strlen($password)<5)
{
echo "Password must be greater then 5 letters";
exit();
}
if($password!=$password1)
{
echo "Password does not match";
exit();
}
$sql='SELECT u.id FROM user as u WHERE (u.password="'.$password.'") AND (u.username="'.$username.'")';
$userExist=queryReceive($sql);
if(count($userExist)!=0)
{
echo "user is already exist";
exit();
}
$sql='UPDATE `user` SET `username`="'.$username.'",`password`="'.$password.'" WHERE id='.$userid.'';
querySend($sql);
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-27
* Time: 17:29
*/
include_once ("../../connection/connect.php");
$comapnyId=$_POST['companyid']=2;
$CateringBranches=$_POST['CateringBranches']=2;
$hallBranches=$_POST['hallBranches']=2;
if($CateringBranches==0)
{
header("location:../hallBranches/hallRegister.php?hallBranches=$hallBranches&comapnyId=$comapnyId");
exit();
}
$sql='SELECT name,id FROM systemDishType WHERE ISNULL(isExpire)';
$dishType=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0;
padding: 0;
}
</style>
</head>
<body>
<?php
$H=0;
for($M=0;$M<$CateringBranches;$M++)
{
echo '<div class="col-12 border shadow mb-4" id="removeform'.$M.'">';
$M++;
echo '<h1 align="center"> Catering Registeration '.$M.'</h1>';
$M--;
echo '<form id="formsubmit'.$M.'" >';
?>
<div class="form-group row">
<label class="col-form-label col-4">Catering Branch name:</label>
<input name="namecatering" type="text" class="form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4">Catering Branch Image:</label>
<input name="image" type="file" class="form-control col-8">
</div>
<div class="col-5">
<p> Map of address</p>
</div>
<h3 align="center"> select Dishes</h3>
<?php
$display = '';
for ($i = 0; $i < count($dishType); $i++) {
$display = '<h1 align="center">' . $dishType[$i][0] . '</h1>';
$sql = 'SELECT `name`, `id`, `image` FROM `systemDish` WHERE ISNULL(isExpire)AND
systemDishType_id=' . $dishType[$i][1] . '';
$dishDetail = queryReceive($sql);
for ($j = 0; $j < count($dishDetail); $j++) {
$display .= '
<div class="col-4 table-bordered">
<input id="dishtypename' .$H. '" hidden type="text" name="dishtypename[]" value="' . $dishType[$i][0] . '">
<input id="dishid' .$H. '" hidden type="number" name="dishid[]" value="' . $dishDetail[$j][1] . '">
<input id="dishname' . $H . '" name="dishname[]" hidden value="' . $dishDetail[$j][0] . '">
<input id="image' . $H. '" name="image[]" hidden value="' . $dishDetail[$j][2] . '">
<img class="col-12" src="' . $dishDetail[$j][2] . '" style="height: 20vh" >
<p class="col-12"> ' . $dishDetail[$j][0] . '</p>
<input data-dishshow="' .$H. '" type="button" class="selectdish form-control col-12 btn-danger" value="Remove">
</div>';
$H++;
}
}
echo $display;
?>
<div class="form-group row mt-3">
<input data-formid="<?php echo $M; ?>" type="button" class="cancelform btn btn-outline-danger col-5 form-control " value="cancel">
<input data-formid="<?php echo $M; ?>" type="button" class="submitform btn btn-primary col-5 form-control" value="submit">
</div>
</form>
<?php
echo '</div>';
}
?>
<script>
$(document).ready(function () {
var NoCatering=<?php echo $CateringBranches;?>;
$(document).on("click",".selectdish",function ()
{
var id=$(this).data("dishshow");
var value=$(this).val();
if(value=="Remove")
{
$("#dishtypename"+id).attr("name","");
$("#dishid"+id).attr("name","");
$("#dishname"+id).attr("name","");
$("#image"+id).attr("name","");
$(this).val("Select");
$(this).removeClass("btn-danger");
$(this).addClass("btn-success");
}
else
{
$("#dishtypename"+id).attr("name","dishtypename[]");
$("#dishid"+id).attr("name","dishid[]");
$("#dishname"+id).attr("name","dishname[]");
$("#image"+id).attr("name","image[]");
$(this).val("Remove");
$(this).removeClass("btn-success");
$(this).addClass("btn-danger");
}
});
function nextpage(formid)
{
$("#removeform"+formid).remove();
NoCatering--;
if(NoCatering<=0)
{
window.location.href="../hallBranches/hallRegister.php?hallBranches=<?php echo $hallBranches; ?>&comapnyId=<?php echo $comapnyId; ?>";
}
}
$(".submitform").click(function () {
var formid=$(this).data("formid");
var formdata=new FormData($("#formsubmit"+formid)[0]);
formdata.append("option","createCatering");
formdata.append("companyid",<?php echo $comapnyId;?>);
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!="")
{
alert(data);
return false;
}
else
{
nextpage(formid);
}
}
});
});
$(".cancelform").click(function ()
{
var formid=$(this).data("formid");
nextpage(formid);
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 23:30
*/
include_once ("../connection/connect.php");
if(!isset($_SESSION['order']))
{
header("location:../user/userDisplay.php");
}
$userId=$_COOKIE['userid'];
$orderid=$_SESSION['order'];
$companyid=$_COOKIE['companyid'];
$sql='SELECT (SELECT p.name FROM person as p WHERE p.id=od.person_id),od.person_id,(SELECT p.image FROM person as p WHERE p.id=od.person_id) FROM orderDetail as od WHERE od.id='.$orderid.'';
$orderDetailPerson= queryReceive($sql);
$customerID=$orderDetailPerson[0][1];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="../webdesign/css/loader.css">
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://as1.ftcdn.net/jpg/02/48/64/56/500_F_248645634_PXszpu8MVoW8P6wXxD5yEEInauZjrFc7.jpg);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 class="text-dark"> <i class="fas fa-share-alt fa-3x"></i> transfer payment</h3>
<p >You can transfer your payment to another user</p>
</div>
</div>
<div class="container">
<div class="row justify-content-center col-12" style="margin-top: -60px">
<div class="card text-center card-header">
<img src="<?php
if(file_exists('../images/customerimage/'.$orderDetailPerson[0][2])&&($orderDetailPerson[0][2]!=""))
{
echo '../images/customerimage/'.$orderDetailPerson[0][2];
}
else
{
echo 'https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
?> " style="height: 20vh;" class="figure-img rounded-circle" alt="image is not set">
<h5 ><?php
echo $orderDetailPerson[0][0];
?></h5>
<label >Order ID:<?php
echo $orderid;
?></label>
</div>
</div>
<?php
$sql='SELECT py.id FROM payment as py
WHERE (py.user_id='.$userId.') AND (py.orderDetail_id='.$orderid.') AND (py.sendingStatus in (0,1)) order BY
py.receive DESC';
$Yourpayment=queryReceive($sql);
for ($i=0;$i<count($Yourpayment);$i++)
{
$sql = 'SELECT `id`, `amount`, `nameCustomer`, `receive`, `IsReturn`,`sendingStatus` FROM `payment` WHERE id=' . $Yourpayment[$i][0] . '';
$paymentDetail = queryReceive($sql);
?>
<div class="card-header shadow-lg col-12 border mt-5">
<div class="form-group row">
<label class="col-form-label"> payment ID</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-id-card"></i></span>
</div>
<h1 class="col-form-label"> <?php
echo $paymentDetail[0][0];
?></h1>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> User </label>
<div class="input-group mb-3 input-group-lg ">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user"></i></span>
</div>
<select id="userIdlabel<?php
echo $paymentDetail[0][0];
?>" class="form-control">
<option value="none">None</option>
<?php
$sql = 'SELECT id, username FROM user WHERE (id !=' . $userId . ') AND (company_id=' . $companyid . ') ';
$userDetail = queryReceive($sql);
for ($y = 0; $y < count($userDetail); $y++) {
echo '<option value=' . $userDetail[$y][0] . '>' . $userDetail[$y][1] . '</option>';
}
?>
</select>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Amount</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-money-bill-alt"></i></span>
</div>
<h1 class="col-form-label"> <?php
echo $paymentDetail[0][1];
?></h1>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> customer Name</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user-edit"></i></span>
</div>
<label class="col-form-label"> <?php
echo $paymentDetail[0][2];
?></label>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Receive Date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-calendar-alt"></i></span>
</div>
<label class="col-form-label"> <?php
echo $paymentDetail[0][3];
?></label>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> payment Status</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-exchange-alt"></i></span>
</div>
<label class="col-form-label"> <?php
if ($paymentDetail[0][4] == 0) {
echo "Get amount to customer";
} else {
echo "return amount to customer";
}
?></label>
</div>
</div>
<div class="form-group row">
<input data-paymentid="<?php echo $paymentDetail[0][0]; ?>" type="button"
class="paymentsend col-6 btn btn-success" value="<?php
if ($paymentDetail[0][5] == 0) {
echo "Send";
} else if ($paymentDetail[0][5] == 1) {
echo "Confirming";
} else {
echo "not part of this";
}
?>">
</div>
</div>
<?php
}
?>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
//window.history.back();
$(document).ready(function () {
$(".paymentsend") .click(function () {
var btnsender=$(this).val();
var paymentId=$(this).data("paymentid");
if(btnsender=='Send')
{
var userID=$("#userIdlabel"+paymentId).val();
if(userID=='none')
{
alert("please select User");
return false;
}
$.ajax({
url:"paymentServer.php",
data:{useid:userID,paymentId:paymentId,option:"paymentsend"} ,
dataType:"text",
method:"POST",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
}
else
{
window.location.reload();
}
}
});
}
else if(btnsender=='Confirming')
{
alert("your request has been sent to the next user so please wait for it");
}
});
});
</script>
</body>
</html>
<file_sep><?php
include_once ('../../connection/connect.php');
if(!isset($_SESSION['tempid']))
{
header("location:../companyRegister/companyEdit.php");
}
if(isset($_GET['action']))
{
if($_GET['action']=="expire")
{
$date=date('Y-m-d H:i:s');
$sql='UPDATE `hall` SET `expire`="'.$date.'" WHERE id='.$_SESSION['tempid'].'';
}
else
{
$sql='UPDATE `hall` SET `expire`=NULL WHERE id='.$_SESSION['tempid'].'';
}
querySend($sql);
header("location:../companyRegister/companyEdit.php");
}
if(isset($_GET['editpackage']))
{
$_SESSION['2ndpage']=$_GET['packageid'];
header("location:Editpackage.php?hallname=".$_GET['hallname']."&month=".$_GET['month']."&daytime=".$_GET['daytime']."");
}
$hallid='';
$companyid='';
$hallid=$_SESSION['tempid'];
$companyid=$_COOKIE['companyid'];
$sql='SELECT `name`, `max_guests`, `noOfPartitions`, `ownParking`, `expire`, `image`, `hallType`, `location_id` FROM `hall` WHERE id='.$hallid.'';
$halldetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<style>
#formhall
{
margin: 5%;;
}
#showDaytimes
{
background: #dd3e54; /* fallback for old browsers */
background: -webkit-linear-gradient(to right, #6be585, #dd3e54); /* Chrome 10-25, Safari 5.1-6 */
background: linear-gradient(to right, #6be585, #dd3e54); /* W3C, IE 10+/ Edge, Firefox 16+, Chrome 26+, Opera 12+, Safari 7+ */
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron jumbotron-fluid text-center" style="background-image: url(<?php
if(file_exists("../".$halldetail[0][5])&&($halldetail[0][5]!=""))
{
echo "../".$halldetail[0][5];
}
else
{
echo "https://www.pakvenues.com/system/halls/cover_images/000/000/048/original/Umar_Marriage_Hall_lahore.jpg?1566758537";
}
?>);background-repeat: no-repeat ;background-size: 100% 100%">
<div class="container" style="background-color: white;opacity: 0.7">
<h1 class="display-4"><i class="fas fa-place-of-worship"></i><?php echo $halldetail[0][0]; ?></h1>
<p class="lead">You can control hall setting and also month wise prize list.Prize list consist of per head with food and per head only seating .</p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php " class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container">
<h1> Hall Setting </h1>
<hr class="mt-2 mb-3 border-white">
<form class="shadow card-body" id="formhall" >
<input type="number" hidden name="hallid" value="<?php echo $hallid; ?>">
<input type="text" hidden name="previousimage" value="<?php echo $halldetail[0][5]; ?>">
<div class="form-group row">
<label class="col-form-label ">Hall Branch Name:</label>
<!-- <input name="hallname" class="form-control col-8" type="text" value="--><?php //echo $halldetail[0][0]; ?><!--">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-place-of-worship"></i></span>
</div>
<input name="hallname" type="text" class="form-control" value="<?php echo $halldetail[0][0]; ?>">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Hall Type:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fab fa-accusoft"></i></span>
</div>
<select name="halltype" class="form-control">
<?php
$halltype=array("Marquee","Hall","Deera /Open area");
echo '<option value="'.$halldetail[0][6].'">'.$halltype[$halldetail[0][6]].'</option>';
for($i=0;$i<count($halltype);$i++)
{
if($i!=$halldetail[0][6])
{
echo '<option value="'.$i.'">'.$halltype[$i].'</option>';
}
}
?>
</select>
</div>
</div>
<div class="form-group row">
<label class="col-form-label ">Hall Branch Image:</label>
<!-- <input name="image" class="form-control col-8" type="file">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera-retro"></i></span>
</div>
<input name="image" type="file" class="form-control">
</div>
</div>
<div class="form-group row">
<label class="col-form-label"><i class="fas fa-map-marker-alt"> </i>Hall Branch Address</label>
</div>
<div class="form-group row">
<label class="col-form-label">Maximum Capacity of guests in hall:</label>
<!-- <input name="capacity" class="form-control col-4" type="number" value="--><?php //echo $halldetail[0][1]; ?><!--">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-users"></i></span>
</div>
<input type="number" value="<?php echo $halldetail[0][1]; ?>" class="form-control" name="capacity">
</div>
</div>
<div class="form-group row">
<label class="col-form-label ">No of Partition in Hall:</label>
<!-- <input name="partition" class="form-control col-4" type="number" value="--><?php //echo $halldetail[0][2]; ?><!--">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-columns"></i></span>
</div>
<input name="partition" type="number" class="form-control" value="<?php echo $halldetail[0][2]; ?>">
</div>
</div>
<div class="form-group row">
<!-- <input name="parking" class="form-check-input" type="checkbox" --><?php //if($halldetail[0][3]==1){ echo "checked";} ?><!-- >-->
<!-- <label class="form-check-label ">Have Your own parking</label>-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text">
<input name="parking" class="form-check-input " type="checkbox" <?php if($halldetail[0][3]==1){ echo "checked";} ?> ><i class="fas fa-parking"></i>
</span>
</div>
<label class="form-check-label ml-3"> Have Your own parking</label>
</div>
</div>
<div class="form-group row mb-5">
<?php
if($halldetail[0][4]=="")
{
echo '<a href="?action=expire" class="btn btn-danger col-6">Expire</a>';
}
else
{
echo '<a href="?action=active" class="btn btn-warning col-6">Active</a>';
}
?>
<button id="submitedithall" type="button" class="rounded mx-auto d-block btn btn-primary col-6 " value="Submit"> <i class="fas fa-check "></i>Save</button>
</div>
</form>
<h1>Prize list Setting</h1>
<hr class="mt-2 mb-3 border-white">
<div class="form-group row ">
<div data-daytime="Morning" class="col-4 daytime p-0 "style="height: 25vh">
<div class="card-header">
<img class="rounded-circle" src="https://www.incimages.com/uploaded_files/image/970x450/getty_503667408_2000133320009280259_352507.jpg" style="height: 20vh;width: 100%;">
<p align="center" >Morning Prize list</p>
</div>
</div>
<div data-daytime="Afternoon" class=" daytime col-4 p-0"style="height: 25vh">
<div class="card-header">
<img class="rounded-circle" src="https://www.ellieteramoto.com/wordpress/wp-content/uploads/2018/11/the-sun-and-lake-kussharo-hokkaido-japan.jpg" style="height: 20vh;width: 100%">
<p align="center" >Afternoon Prize list</p>
</div>
</div>
<div data-daytime="Evening" class=" daytime col-4 p-0"style="height: 25vh">
<div class="card-header">
<img class="rounded-circle" src="https://www.murals.shop/1777-thickbox_default/starry-sky-half-moon-scenic-cloudscape-wall-mural.jpg" style="height: 20vh;width: 100%">
<p align="center" >Evening Prize list</p>
</div>
</div>
</div>
<div class="border" id="showDaytimes" style="margin-top: 20%;height: 90vh;width:100%; overflow: auto">
</div>
<div class="container">
<h1 class="font-weight-light text-lg-left mt-4 mb-3">Gallery</h1>
<form action="" method="POST" enctype="multipart/form-data" class="form-inline">
<input type="file" name="userfile[]" value="" multiple="" class="col-8 btn btn-light">
<input type="submit" name="submit" value="Upload" class="btn btn-success col-4">
</form>
<?php
if(isset($_FILES['userfile']))
{
$file_array=reArray($_FILES['userfile']);
$Distination='';
for ($i=0;$i<count($file_array);$i++)
{
$Distination= '../../images/hall/'.$file_array[$i]['name'];
$error=MutipleUploadFile($file_array[$i],$Distination);
if(count($error)>0)
{
echo '<h4 class="badge-danger">'.$file_array[$i]['name'].'.'.$error[0].'</h4>';
}
else
{
$sql='INSERT INTO `images`(`id`, `image`, `expire`, `catering_id`, `hall_id`) VALUES (NULL,"'.$Distination.'",NULL,NULL,'.$hallid.')';
querySend($sql);
}
}
unset($_FILES['userfile']);
}
?>
<hr class="mt-3 mb-5 border-white">
<div class="row text-center text-lg-left" style="height: 70vh;overflow: auto">
<?php
$sql='SELECT `id`, `image` FROM `images` WHERE hall_id='.$hallid.'' ;
echo showGallery($sql);
?>
</div>
</div>
</div>
<?php
include_once ("comment.php");
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
function showdaytimelist(daytime)
{
var formdata=new FormData();
formdata.append("option","showdaytimelist");
formdata.append("daytime",daytime);
formdata.append("hallid","<?php echo $hallid; ?>");
formdata.append("companyid","<?php echo $companyid;?>");
formdata.append("hallname","<?php echo $halldetail[0][0]; ?>")
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
$("#showDaytimes").html(data);
}
});
}
$(".daytime").click(function ()
{
var daytime=$(this).data("daytime");
showdaytimelist(daytime);
}) ;
showdaytimelist("Morning");
$(document).on("change",".changeSeating",function () {
var id=$(this).data("menuid");
var value=$(this).val();
var formdata=new FormData();
formdata.append("option","changeSeating");
formdata.append("packageid",id);
formdata.append("value",value);
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
return false;
}
}
});
}) ;
$("#submitedithall").click(function ()
{
var formdata=new FormData($("#formhall")[0]);
formdata.append("option","halledit");
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
return false;
}
else
{
window.location.href="../companyRegister/companyEdit.php";
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-03
* Time: 17:20
*/
include_once ("../connection/connect.php");
if(isset($_POST['option']))
{
if($_POST['option']=="createUser")
{
$username=chechIsEmpty($_POST['username']);
$password=chechIsEmpty($_POST['password']);
$sql='SELECT u.id FROM user as u WHERE (u.password="'.$password.'") AND (u.username="'.$username.'")';
$userExist=queryReceive($sql);
if(count($userExist)!=0)
{
echo "user is already exist";
exit();
}
$name = trim($_POST['name']);
$numberArray = $_POST['number'];
$isowner=1;
$cnic = $_POST['cnic'];
$city = $_POST['city'];
$area = $_POST['area'];
$streetNo = chechIsEmpty($_POST['streetNo']);
$houseNo = chechIsEmpty($_POST['houseNo']);
$date = date('Y-m-d');
$sql='INSERT INTO `person`(`name`, `cnic`, `id`, `date`) VALUES ("'.$name.'","'.$cnic.'",NULL,"'.$date.'")';
querySend($sql);
$last_id = mysqli_insert_id($connect);
$sql="INSERT INTO `address` (`id`, `address_street_no`, `address_house_no`, `person_id`, `address_city`, `address_town`) VALUES (NULL, '".$streetNo."', '".$houseNo."', '".$last_id."', '".$city."', '".$area."');";
querySend($sql);
for ($i=0;$i<count($numberArray);$i++)
{
$sql = "INSERT INTO `number`(`number`, `id`, `is_number_active`, `person_id`) VALUES ('".$numberArray[$i]."',NULL,1,$last_id)";
querySend($sql);
}
$customerId = $last_id;
$sql='INSERT INTO `user`(`id`, `username`, `password`, `person_id`, `isExpire`,`isowner`, `company_id`) VALUES (NULL,"'.$username.'","'.$password.'",'.$customerId.',NULL,"'.$isowner.'",NULL)';
querySend($sql);
$userid = mysqli_insert_id($connect);
$sql='INSERT INTO `company`(`id`, `name`, `expire`, `user_id`) VALUES (NULL,"'.$_POST['companyName'].'",NULL,'.$userid.')';
querySend($sql);
$companyid=mysqli_insert_id($connect);
echo $companyid;
}
else if($_POST['option']=="createCatering")
{
$companyid=$_POST['companyid'];
$namecatering=$_POST['namecatering'];
$Cateringimage='';
$sql=(string) "";
if(!empty($_FILES['image']["name"]))
{
$Cateringimage = "../../images/catering/" . $_FILES['image']['name'];
$resultimage = ImageUploaded($_FILES, $Cateringimage);//$dishimage is destination file location;
if ($resultimage != "") {
print_r($resultimage);
exit();
}
}
$sql='INSERT INTO `catering`(`id`, `name`, `expire`, `image`, `location_id`, `company_id`) VALUES (NULL,"'.$namecatering.'",NULL,"'.$Cateringimage.'",NULL,'.$companyid.')';
querySend($sql);
$cateringid=mysqli_insert_id($connect);
if(!isset($_POST['dishtypename']))
{
exit();
}
$dishtypename=$_POST['dishtypename'];
$dishtypeid='';
$dishid=$_POST['dishid'];
$dishname=$_POST['dishname'];
$image=$_POST['image'];
for($i=0;$i<count($dishtypename);$i++)
{
$sql='SELECT `id` FROM `dish_type` WHERE (name="'.$dishtypename[$i].'") AND (catering_id='.$cateringid.')';
$detail=queryReceive($sql);
if(count($detail)>0)
{
$dishtypeid=$detail[0][0];
}
else
{
$sql='INSERT INTO `dish_type`(`id`, `name`, `isExpire`, `catering_id`) VALUES (NULL,"'.$dishtypename[$i].'",NULL,'.$cateringid.')';
querySend($sql);
$dishtypeid=mysqli_insert_id($connect);
}
$sql='INSERT INTO `dish`(`name`, `id`, `image`, `dish_type_id`, `isExpire`, `catering_id`) VALUES ("'.$dishname[$i].'",NULL,"'.$image[$i].'",'.$dishtypeid.',NULL,'.$cateringid.')';
querySend($sql);
$idDishe=mysqli_insert_id($connect);
$sql='SELECT `name` FROM `SystemAttribute` WHERE ISNULL(isExpire) AND (systemDish_id='.$dishid[$i].')';
$detailAttributes=queryReceive($sql);
for($j=0;$j<count($detailAttributes);$j++)
{
$sql='INSERT INTO `attribute`(`name`, `id`, `dish_id`, `isExpire`) VALUES ("'.$detailAttributes[$j][0].'",NULL,'.$idDishe.',NULL)';
querySend($sql);
}
}
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include ("../../connection/connect.php");
$companyid=$_GET['companyid'];
$hallBranches=$_GET['hallBranches'];
if($hallBranches==0)
{
//go to display company detail
header("Location:../companyRegister/companydisplay.php?companyid=".$companyid."");
exit();
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0px;
padding:0px;
}
</style>
</head>
<body class="container" >
<h1 align="center">
Hall Branches Register
</h1>
<form>
<div class="form-group row">
<label class="col-form-label col-4">Hall Branch Name:</label>
<input name="hallname" class="form-control col-8" type="text">
</div>
<div class="form-group row">
<label class="col-form-label col-4">Hall Type:</label>
<select name="halltype" class="form-control col-8">
<option value="1">Marquee</option>
<option value="2">Hall</option>
<option value="3">Deera /Open area</option>
</select>
</div>
<div class="form-group row">
<label class="col-form-label col-4">Hall Branch Image:</label>
<input name="image" class="form-control col-8" type="file">
</div>
<div class="form-group row">
<label class="col-form-label col-4">Hall Branch Address</label>
</div>
<div class="form-group row">
<label class="col-form-label col-8">Maximum Capacity of guests in hall:</label>
<input name="capacity" class="form-control col-4" type="number">
</div>
<div class="form-group row">
<label class="col-form-label col-8">No of Partition in Hall:</label>
<input name="partition" class="form-control col-4" type="number">
</div>
<div class="form-inline form-group">
<input name="parking" class="form-check-input " type="checkbox">
<label class="form-check-label ">Have Your own parking</label>
</div>
<div class="form-group row">
<input id="cancel" type="button" class="btn btn-danger col-4 form-control" value="cancel">
<input id="submit" type="button" class=" btn btn-success col-4 form-control" value="Submit">
</div>
</form>
<script>
$(document).ready(function () {
$('#submit').click(function () {
var formdata = new FormData($("form")[0]);
formdata.append("option", "CreateHall");
formdata.append("companyid",<?php echo $companyid;?>);
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data)
{
if(!($.isNumeric(data)))
{
alert(data);
}
else
{
//hall detail
window.location.href="daytimeAll.php?companyid=<?php echo $companyid; ?>&hallid="+data+"&hallBranches=<?php $hallBranches--; echo $hallBranches;?>";
}
}
});
});
$("#cancel").click(function ()
{
//remove one hall
window.location.href="?hallBranches=<?php $hallBranches--; echo $hallBranches;?>&companyid=<?php echo $companyid;?>";
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../connection/connect.php");
if(!isset($_COOKIE['companyid']))
{
header("location:../../user/userLogin.php");
}
if(!isset($_GET['catering']))
{
header("location:../companyRegister/companyEdit.php");
}
$encoded=$_GET['catering'];
$id=base64url_decode($encoded);
if((!is_numeric($id))||$id=="")
{
header("location:../companyRegister/companyEdit.php");
}
$cateringid=$id;
$sql='SELECT `name`, `expire`, `image`, `location_id` FROM `catering` WHERE id='.$cateringid.'';
$cateringdetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow text-center" style="background-image: url(<?php
if((file_exists('../../images/catering/'.$cateringdetail[0][2])) &&($cateringdetail[0][2]!=""))
{
echo "'../../images/catering/".$cateringdetail[0][2]."'";
}
else
{
echo "https://www.liberaldictionary.com/wp-content/uploads/2019/02/cater-4956.jpg";
}
?>
);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-body " style="opacity: 0.7 ;background: white;">
<h1 class="display-5 text-center"><i class="fas fa-utensils fa-3x mr-1"></i><?php echo $cateringdetail[0][0];?> Edit Catering Branches</h1>
<p class="lead">Edit dishes information,dishes type,images and others </p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php" class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container row m-auto">
<a href="infoCatering.php?catering=<?php echo $encoded;?>" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-cogs fa-5x"></i><h4>Change info</h4></a>
<a href="gallerycatering.php?catering=<?php echo $encoded;?>" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-images fa-5x"></i> <h4>Gallery</h4></a>
<a href="dish/dishesInfo.php?catering=<?php echo $encoded;?>" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-hamburger fa-5x"></i><h4>Dishes Setting</h4></a>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
});
</script>
</body>
</html><file_sep>
<?php
include_once ("../connection/connect.php");
//2//2
if(!isset($_SESSION['order']))
{
header("location:../user/userDisplay.php");
}
$userId=$_COOKIE['userid'];
$orderid=$_SESSION['order'];
$companyid=$_COOKIE['companyid'];
$sql='SELECT (SELECT p.name FROM person as p WHERE p.id=od.person_id),od.person_id,(SELECT p.image FROM person as p WHERE p.id=od.person_id) FROM orderDetail as od WHERE od.id='.$orderid.'';
$orderDetailPerson= queryReceive($sql);
$customerID=$orderDetailPerson[0][1];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="../webdesign/css/loader.css">
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://instabug.com/blog/wp-content/uploads/2018/05/SurveysRequests_2-02.jpg);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 class="text-dark"> <i class="fas fa-clipboard-check fa-3x"></i> Payment Receiving Request</h3>
<p >Other user is requesting to you to confirm their payments</p>
</div>
</div>
<div class="container">
<div class="row justify-content-center col-12" style="margin-top: -60px">
<div class="card text-center card-header">
<img src="<?php
if(file_exists('../images/customerimage/'.$orderDetailPerson[0][2])&&($orderDetailPerson[0][2]!=""))
{
echo '../images/customerimage/'.$orderDetailPerson[0][2];
}
else
{
echo 'https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
?> " style="height: 20vh;" class="figure-img rounded-circle" alt="image is not set">
<h5 ><?php
echo $orderDetailPerson[0][0];
?></h5>
<label >Order ID:<?php
echo $orderid;
?></label>
</div>
</div>
<?php
$sql = 'SELECT py.id,(SELECT u.username FROM user as u WHERE u.id=py.user_id) as username,py.amount,py.nameCustomer,py.IsReturn,t.senderTimeDate,py.receive,t.id,py.sendingStatus FROM orderDetail as ot INNER join payment as py on ot.id=py.orderDetail_id INNER join transfer as t on py.id=t.payment_id where (ot.id=' . $orderid . ') AND (t.user_id=' . $userId . ')AND (py.sendingStatus in (0,1,2))
';
$Yourpayment=queryReceive($sql);
for ($i=0;$i<count($Yourpayment);$i++)
{
$sql = 'SELECT `id`, `amount`, `nameCustomer`, `receive`, `IsReturn`,`sendingStatus` FROM `payment` WHERE id=' . $Yourpayment[$i][0] . '';
$paymentDetail = queryReceive($sql);
?>
<div class="card-header shadow-lg col-12 border mt-5">
<div class="form-group row">
<label class="col-form-label"> payment ID</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-id-card"></i></span>
</div>
<h1 class="col-form-label"> <?php
echo $paymentDetail[0][0];
?></h1>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> User </label>
<div class="input-group mb-3 input-group-lg ">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user"></i></span>
</div>
<label class="col-form-label"> <?php
echo $Yourpayment[$i][1];
?></label>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Amount</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-money-bill-alt"></i></span>
</div>
<h1 class="col-form-label"> <?php
echo $paymentDetail[0][1];
?></h1>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> customer Name</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user-edit"></i></span>
</div>
<label class="col-form-label"> <?php
echo $paymentDetail[0][2];
?></label>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> Receive Date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-calendar-alt"></i></span>
</div>
<label class="col-form-label"> <?php
echo $paymentDetail[0][3];
?></label>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> payment Status</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-exchange-alt"></i></span>
</div>
<label class="col-form-label"> <?php
if ($paymentDetail[0][4] == 0) {
echo "Get amount to customer";
} else {
echo "return amount to customer";
}
?></label>
</div>
</div>
<div class="form-group row">
<label class="col-form-label"> User Send to you on Data</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-calendar-alt"></i></span>
</div>
<label class="col-form-label"> <?php
echo $Yourpayment[$i][5];
?></label>
</div>
</div>
<div class="form-group row">
<?php
$displayDetailOfPayment='';
if($Yourpayment[$i][8]==1)
{
$displayDetailOfPayment.= '<input data-paymentid="'.$Yourpayment[$i][0].'" data-tranferid="'.$Yourpayment[$i][7].'" type="button" class="configration col-6 form-control btn btn-danger" value="unconfirm">
<input data-paymentid="'.$Yourpayment[$i][0].'" data-tranferid="'.$Yourpayment[$i][7].'" type="button" class="configration col-6 form-control btn btn-success" value="confirm">';
}
else if($Yourpayment[$i][8]==2)
{
$displayDetailOfPayment.='<input type="button" class="confirmed btn btn-info col-6" value="confirmed">';
}
else if($Yourpayment[$i][8]==0)
{
$displayDetailOfPayment.='<input type="button" class="Unconfirmed btn btn-light col-8" value="Unconfirmed">';
}
echo $displayDetailOfPayment;
?>
</div>
</div>
<?php
}
?>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$(".configration").click(function ()
{
var tranferid=$(this).data("tranferid");
var paymentid=$(this).data("paymentid");
var value=$(this).val();
$.ajax({
url:"paymentServer.php",
data:{paymentid:paymentid,value:value,tranferid:tranferid,option:"paymentconfigration"} ,
dataType:"text",
method:"POST",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
}
else
{
location.reload(true);
}
}
});
});
$(".confirmed").click(function () {
alert("The payment has been confirmed by you");
});
$(".Unconfirmed").click(function () {
alert("The payment has been Unconfirmed by you");
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:25
*/
//session are customerid,typebranch,typebranchid,tempid,2ndpage,order
//cookies are userid,username,companyid,userimage,isOwner
//
//$OrderStatus=array("Running","Cancel","Delieved","Clear");
//
session_start();
date_default_timezone_set("Asia/Karachi");
//date_default_timezone_get();
$connect=mysqli_connect('localhost',"root","","a111");
//$connect=mysqli_connect("localhost","id10884474_shahzad","11111","id10884474_catering");
if(!$connect)
{
echo "fail connection";
}
if (mysqli_connect_errno())
{
printf("Connect failed: %s\n", mysqli_connect_error());
exit();
}
function queryReceive($sql)
{
global $connect;
$result = mysqli_query($connect, $sql);
if (!$result)
{
echo $sql;
echo("Error description: " . mysqli_error($connect));
}else
{
return mysqli_fetch_all($result);
}
}
function querySend($sql)
{
global $connect;
$result = mysqli_query($connect, $sql);
if (!$result)
{
echo $sql;
echo("Error description: " . mysqli_error($connect));
}
}
function chechIsEmpty($value)
{
if($value=="")
{
return 0;
}
return $value;
}
function arrayCheckIsEmpty($valuesArray)
{
for ($a=0;$a<count($valuesArray);$a++)
{
if($valuesArray[$a]=="")
{
$valuesArray[$a]=0;
}
}
return $valuesArray;
}
function ImageUploaded($File,$DestinationFile)
{
if(isset($File['image']))// name=image
{
$errors= array();
$file_size = $File['image']['size'];
$file_tmp = $File['image']['tmp_name'];
$file_type = $File['image']['type'];
$passbyreference=explode('.',$File['image']['name']);
$file_ext=strtolower(end($passbyreference));
$extensions= array("jpeg","jpg","png");
if(in_array($file_ext,$extensions)=== false){
$errors[]="extension not allowed, please choose a JPEG or PNG file.";
}
if($file_size > 2097152)
{
$errors[]='File size must be excately 2 MB';
}
// if (file_exists($DestinationFile))
// {
// $errors[]= "Sorry, file already exists.";
// }
if(empty($errors)==true)
{
move_uploaded_file($file_tmp,$DestinationFile);
return "";
}else{
return $errors;
}
}
return "";
}
function showarray($arrays)
{
echo '<pre>';
print_r($arrays);
echo '</pre>';
}
function reArray($file_post)
{
$file_ary=array();
$file_count=count($file_post['name']);
$file_key=array_keys($file_post);
for ($i=0;$i<$file_count;$i++)
{
foreach ($file_key as $key)
{
$file_ary[$i][$key]=$file_post[$key][$i];
}
}
return $file_ary;
}
function MutipleUploadFile($File,$DestinationFile)
{
$errors= array();
$file_size = $File['size'];
$file_tmp = $File['tmp_name'];
$file_type = $File['type'];
$passbyreference=explode('.',$File['name']);
$file_ext=strtolower(end($passbyreference));
$extensions= array("jpeg","jpg","png","mp4");
if(in_array($file_ext,$extensions)=== false){
$errors[]="extension not allowed, please choose a JPEG or PNG file or MP4 or JPEG.";
}
if($file_size > 10097152)
{
$errors[]='File size must be excately 2 MB';
}
// if (file_exists($DestinationFile))
// {
// $errors[]= "Sorry, file already exists.";
// }
if(empty($errors)==true)
{
move_uploaded_file($file_tmp,$DestinationFile);
return $errors;
}else{
return $errors;
}
}
function showGallery($sql)
{
$result=queryReceive($sql);
$source='';
$display='';
$extensions= array("jpeg","jpg","png");
for($k=0;$k<count($result);$k++)
{
if(file_exists($result[$k][1]))
{
$passbyreference = explode('.', $result[$k][1]);
$file_ext = strtolower(end($passbyreference));
if (in_array($file_ext, $extensions) === true) {
//image file
$display .= '
<div class="col-lg-4 col-md-6 col-12 mb-2 mt-2">
<a href="#" class="d-block mb-4 h-100">
<img class="img-fluid img-thumbnail" src="' . $result[$k][1] . '" alt="">
</a>
</div>';
} else {
//video file
$source = $result[$k][1];
$video = substr_replace($source, "", -4);
$display .= '
<div class="col-lg-4 col-md-6 col-12 mb-2 mt-2">
<div class="embed-responsive embed-responsive-16by9 d-block mb-4 h-100">
<video width="320" height="440" controls class="card" >
<source src="' . $video . '.mp4" type="video/mp4">
<source src="' . $video . '.ogg" type="video/ogg">
Your browser does not support the video tag.
</video>
</div>
</div>
';
}
}
}
return $display;
}
function dishesOfPakage($sql)
{
$dishdetail = queryReceive($sql);
$display='';
for ($j = 0; $j < count($dishdetail); $j++)
{
$display.= '
<div id="dishid' . $dishdetail[$j][1] . '" class="col-4 alert-danger border m-1 form-group p-0" style="height: 30vh;" >
<img src="' . $dishdetail[$j][2] . '" class="col-12" style="height: 15vh">
<p class="col-form-label" class="form-control col-12">' . $dishdetail[$j][0] . '</p>
<input data-image="' . $dishdetail[$j][2] . '" data-dishname="' . $dishdetail[$j][0] . '" data-dishid="' . $dishdetail[$j][1] . '" type="button" value="Select" class="form-control col-12 touchdish btn btn-success">
<input hidden type="text" name="dishname[]" value="' . $dishdetail[$j][0] . '">
<input hidden type="text" name="image[]" value="' . $dishdetail[$j][2] . '">
</div>';
}
return $display;
}
function showRemainings($sql)
{
$display='<table class="table table-striped newcolor table-responsive" style="width: 100%;">
<thead class="font-weight-bold">
<tr>
<th scope="col"><h1 class="fas fa-id-card col-12"></h1>order Id</th>
<th scope="col"><h1 class="fas fa-user col-12"></h1>customer Name</th>
<th scope="col"><h1 class="far fa-eye col-12"></h1>order status</th>
<th scope="col"><h1 class="fab fa-amazon-pay col-12"></h1>received amount</th>
<th scope="col">System Amount</th>
<th scope="col">remaining system amount </th>
<th scope="col"><h1 class="far fa-money-bill-alt col-12"></h1>your demanded amount</th>
<th scope="col">remaining demand amount</th>
</tr>
</thead>
<tbody>';
$details=queryReceive($sql);
for ($i=0;$i<count($details);$i++)
{
$display.='<tr data-href="?action=preview&order='.$details[$i][0].'&customer='.$details[$i][0].'" class="clickable-row">
<td scope="row">'.$details[$i][0].'</td>
<td>'.$details[$i][1].'</td>
<td>';
if(!empty($hallid))
{
//if order status is hall
$display.=$details[$i][7];
}
else
{
//if order status is catering
$display.=$details[$i][6];
}
$display.='</td>
<td>'.(int)$details[$i][2].'</td>
<td>'.(int)$details[$i][5].'</td>
<td> '.(int) ($details[$i][5]-$details[$i][2]).'</td>
<td>'.(int) $details[$i][4].'</td>
<td>'.(int) ($details[$i][4]-$details[$i][2]).'</td>
';
$display.='</tr>';
}
$display.='
</tbody>
</table>';
return $display;
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
$cateringid=$_SESSION['branchtypeid'];
$customer=$_SESSION['customer'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<style>
</style>
</head>
<body >
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://cdn.flatworldsolutions.com/featured-images/outsource-outbound-call-center-services.jpg);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 ><i class="fas fa-cart-plus fa-2x"></i>Order Booking </h3>
</div>
</div>
<div class="container ">
<form class="card-body">
<input type="number" hidden name="customer" value=<?php echo $customer;?> >
<input type="number" hidden name="cateringid" value="<?php echo $cateringid;?>">
<div class="form-group row">
<label for="persons" class="col-form-label"> No of guests</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-users"></i></span>
</div>
<input type="number" name="persons" id="persons" class="form-control" placeholder="etc 250,300,....persons">
</div>
</div>
<div class="form-group row">
<label for="time" class="col-form-label">Delivery Time</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-clock"></i></span>
</div>
<input type="time" name="time" id="time" class="form-control">
</div>
</div>
<div class="form-group row">
<label for="date" class="col-form-label">Delivery Date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-calendar-alt"></i></span>
</div>
<input type="date" name="date" id="date" class="form-control">
</div>
</div>
<h3 align="center"> <i class="fas fa-map-marker-alt mr-2"></i>Delivery Address(optional)</h3>
<div class="form-group row">
<label for="area" class="col-form-label">Area / Block </label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-city"></i></span>
</div>
<input type="text" name="area" id="area" class="form-control" placeholder="block address ..">
</div>
</div>
<div class="form-group row">
<label for="streetNO" class="col-form-label">Street no #</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-road"></i></span>
</div>
<input type="number" name="streetno" id="streetNO" class="form-control" placeholder="street no 1,2,3....">
</div>
</div>
<div class="form-group row">
<label for="houseno" class="col-form-label">House no# </label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-street-view"></i></span>
</div>
<input type="number" name="houseno" id="houseno" class="form-control" placeholder="house no 1,2,.....">
</div>
</div>
<div class="form-group row">
<label for="describe" class="col-form-label">Describe order </label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-comments"></i></span>
</div>
<textarea id="describe" name="describe" class="form-control form-control" placeholder="order comment /requirements"></textarea>
</div>
</div>
<div class="form-group row justify-content-center">
<a href="/Catering/customer/customerEdit.php" class="form-control col-5 btn btn-danger"><i class="fas fa-arrow-left"></i>Edit Customer</a>
<button type="button" id="submit" class="form-control col-5 btn-success"><i class="fas fa-check "></i> Submit</button>
</div>
</form>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
$("#submit").click(function (e)
{
e.preventDefault();
var formdata=new FormData($('form')[0]);
formdata.append('function',"add");
$.ajax({
url:"orderServer.php",
data:formdata,
method:"POST",
contentType: false,
processData: false,
dataType:"text",
success:function (data)
{
if(data!="")
{
alert(data);
}
else
{
window.location.href="../dish/dishDisplay.php";
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
function queryReceive($sql)
{
global $connect;
$result = mysqli_query($connect, $sql);
if (!$result) {
echo("Error description: " . mysqli_error($connect));
}else{
return mysqli_fetch_all($result);
}
}
function querySend($sql)
{
global $connect;
$result = mysqli_query($connect, $sql);
if (!$result) {
echo("Error description: " . mysqli_error($connect));
}
}
$sql='SELECT `id`, `name` FROM `dish_type` WHERE 1';
$dishTypeDetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding:auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container" style="margin-top:180px">
<form class="card" id="formid" method="post" action="dishCreate.php?order=<?php echo $_GET['order'];?>&option=dishDisplay">
<div class="col-12" id="selected">
<div class="form-group row border">
<label class="text-center col-form-label col-7">Dish Name</label>
<label class="text-center col-form-label col-3">No of kind</label>
<label class=" text-center col-form-label col-2">Delete</label>
</div>
</div>
<div class="form-group row col-12 ">
<?php
if(isset($_GET['option']))
{
if($_GET['option']=="orderCreate")
{
echo '<a href="/order/orderEdit.php?order='.$_GET['order'].'&customer='.$_GET['customer'].'&option=dishDisplay" class="col-5 form-control btn btn-danger">Edit Order</a>';
}
else if($_GET['option']=="orderEdit")
{
echo '<button id="cancelDish" type="button" class="col-5 btn btn-danger form-control">Edit order</button>';
}
}
else
{
echo '<button id="cancelDish" type="button" class="col-5 btn btn-danger form-control">Edit order</button>';
}
?>
<button id="submit" type="submit" class="btn-success form-control btn col-5">Submit</button>
</div>
</form>
<div class="card" style="margin-top: 20px">
<?php
$display='';
for($i=0;$i<count($dishTypeDetail);$i++)
{
$display.='<div class="col-12">
<h2 align="center"> '.$dishTypeDetail[$i][1].'</h2>
<div class="col-12 row ">';
$sql='SELECT `name`, `id`, `image`, `dish_type_id` FROM `dish` WHERE dish_type_id='.$dishTypeDetail[$i][0].'';
$dishDetail=queryReceive($sql);
for ($j=0;$j<count($dishDetail);$j++)
{
$display .= ' <div class="card shadow-lg bg-white " style="width:200px;">
<img class="card-img-top" src="../gmail.png" alt="Card image">
<div class="card-body">
<label class="card-title co">' . $dishDetail[$j][0] . '</label>
<button type="button" data-dishname="'. $dishDetail[$j][0] .'" data-dishid="'. $dishDetail[$j][1] .'" class="add btn btn-primary col-12">Select</button>
</div></div>';
}
$display.='</div>';
}
echo $display;
?>
</div>
</div>
<script>
$(document).ready(function () {
$(document).on('click','.add',function () {
var dishName=$(this).data("dishname");
var dishId=$(this).data("dishid");
$('#selected').append('\n' +
' <div class="form-group row " id="dishid_'+dishId+'">\n' +
' <h2 class="form-control col-7">'+dishName+'</h2>\n' +
' <input type="number" value="1" name="types[]" class="form-control col-3">\n' +
' <input type="number" hidden name="dishid[]" value="'+dishId+'">\n' +
' <input type="button" class="remove form-control col-2 btn-primary" data-dishid="'+dishId+'" value="-">\n' +
' </div>');
}) ;
$(document).on('click','.remove',function () {
var id=$(this).data("dishid");
$("#dishid_"+id).remove();
});
$("#cancelDish").click(function () {
window.history.back();
return false;
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
$userId=$_GET['user_id'];
$orderDetail_id=$_GET['order'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<div class="container" style="margin-top:150px">
<h1 align="center">payment History</h1>
<a class="btn-success form-control col-4 " href="/Catering/order/PreviewOrder.php?order=<?php echo $orderDetail_id; ?>"> <- Preview Order</a>
<div class="col-12 shadow border card" style="background-color: #80bdff">
<?php
$sql='SELECT py.id,(SELECT u.username FROM user as u where u.id=py.user_id) as sender,
(SELECT u.username FROM user as u where u.id=t.user_id) as receiver,py.amount,
t.senderTimeDate,t.Isconfirm,py.receive,py.nameCustomer,py.IsReturn,t.Isget
FROM orderDetail as ot INNER JOIN payment as py
on ot.id=py.orderDetail_id
INNER join transfer as t
on py.id=t.payment_id
WHERE (ot.id='.$orderDetail_id.')';
$historyPayment=queryReceive($sql);
$display='';
for($k=0;$k<count($historyPayment);$k++)
{
$display.=' <div class="col-12 shadow border card" >
<div class="form-group row" >
<label class="col-4 col-form-label" > Payment Id </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][0].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Sender User </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][1].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Receive User </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][2].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Amount</label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][3].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Sending Date </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][4].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Receiving Date </label >
<label class="col-8 col-form-label" > ';
if($historyPayment[$k][5]=="")
{
$display.= "request has delivered for confirm to user";
}
else
{
$display.= $historyPayment[$k][5];
}
$display.= ' </label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Geting payment Date </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][6].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Customer Name </label >
<label class="col-8 col-form-label" > '.$historyPayment[$k][7].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > payment status </label >
<label class="col-8 col-form-label" > ';
if($historyPayment[$k][8]==0)
{
$display.='get payment from customer';
}
else
{
$display.='return payment to customer';
}
$display.='</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > transfer Status </label >
<label class="col-8 col-form-label" > ';
if($historyPayment[$k][9]==0)
{
$display.="not confirm";
}
else
{
$display.="yes,I get the amount from user";
}
$display.= '
</label >
</div >
</div >';
echo $display;
}
?>
</div>
<h1 align = "center" > Payment user have on to it </h1 >
<div class="col-12 shadow border card" style="background-color: #c69500" >
<?php
$sql='SELECT py.id,(SELECT u.username FROM user as u where u.id=py.user_id), py.amount,py.receive,py.nameCustomer,py.IsReturn FROM orderDetail as ot INNER JOIN payment as py on ot.id=py.orderDetail_id WHERE (ot.id='.$orderDetail_id.') AND (py.sendingStatus=0)';
$WhyPayment=queryReceive($sql);
$display='';
for($t=0;$t<count($WhyPayment);$t++)
{
$display.='<div class="col-12 shadow border card mb-3" >
<div class="form-group row" >
<label class="col-4 col-form-label" > Payment Id </label >
<label class="col-8 col-form-label" > '.$WhyPayment[$t][0].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > User Name </label >
<label class="col-8 col-form-label" > '.$WhyPayment[$t][1].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Amount</label >
<label class="col-8 col-form-label" > '.$WhyPayment[$t][2].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Receiving Date </label >
<label class="col-8 col-form-label" > '.$WhyPayment[$t][3].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > Customer Name </label >
<label class="col-8 col-form-label" > '.$WhyPayment[$t][4].'</label >
</div >
<div class="form-group row" >
<label class="col-4 col-form-label" > payment status </label >
<label class="col-8 col-form-label" > ';
if($WhyPayment[$t][5]==0)
{
$display.='get payment from customer';
}
else
{
$display.='return payment to customer';
}
$display.='</label >
</div >
</div >';
}
echo $display;
?>
</div>
</div>
<script>
</script>
</body>
</html>
<file_sep>
<?php
//../cateringBranches/cateringEDIT.php?
//../../system/user/userEdit.php?
include_once ("../../connection/connect.php");
if(!isset($_COOKIE['companyid']))
{
header("location:../../user/userLogin.php");
}
if(isset($_GET['action']))
{
//$_SESSION['tempid']=$_GET['id'];
$id=base64url_encode($_GET['id']);
if($_GET['action']=="user")
{
//user
header("location:../../system/user/userEdit.php?id=".$id."");
}
else if($_GET['action']=="hall")
{
//hall
header("location:../hallBranches/daytimeAll.php?hall=".$id."");
}
else
{
//catering
header("location:../cateringBranches/cateringEDIT.php?catering=".$id."");
}
}
$companyid=$_COOKIE['companyid'];
$sql='SELECT `id`, `name`, `expire`, `user_id` FROM `company` WHERE id='.$companyid.'';
$companydetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
#hallbranches
{
width: 100%;/*
height: 50vh;
overflow: auto;*/
background-size: 100% 100%;
margin: auto;
}
#cateringbranches
{
width: 100%;
/*height: 50vh;
overflow: auto;*/
background-size: 100% 100%;
margin: auto;
}
#userbranches
{
width: 100%;
/*height: 50vh;
overflow: auto;*/
background-size: 100% 100%;
margin: auto;
}
</style>
</head>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow " style="background-image: url(https://i2.wp.com/findlawyer.com.ng/wp-content/uploads/2018/05/Pros-and-Cons-of-Working-at-Large-Companies.jpg?resize=1024%2C512&ssl=1);background-size:100% 115%;background-repeat: no-repeat;">
<div class="card-body text-center" style="opacity: 0.7 ;background: white;">
<h1 class="display-5 "><i class="fas fa-city mr-2"></i><?php echo $companydetail[0][1];?><br>Edit your company</h1>
<p>setting you company of hall branches,catering branches ,user informations ,packages edit</p>
<h1 class="text-center"> <a href="../companyRegister/companydisplay.php" class="col-6 btn btn-warning "> <i class="fas fa-city mr-2"></i>My Company</a></h1>
</div>
</div>
<div class="container">
<!--USERS-->
<div class="col-12 row mt-5">
<h2 align="center" class="col-7"> <i class="fas fa-user mr-1"></i> Users</h2>
<a href="../../system/user/usercreate.php" class="btn btn-success col-5"><i class="fas fa-user-plus"></i> Add User</a>
</div>
<hr class="border border-white">
<div class="form-group row shadow m-auto newcolor" id="userbranches">
<?php
$sql='SELECT u.id, u.username, u.isExpire,(SELECT p.image FROM person as p WHERE p.id=u.person_id) FROM user as u WHERE u.company_id='.$companyid.'';
$users=queryReceive($sql);
$display='';
for($i=0;$i<count($users);$i++)
{
$display.='
<a href="?action=user&id='.$users[$i][0].'" class="col-sm-12 col-md-4 col-xl-3 m-2">
<div class="card col-12 rounded-circle shadow" style="height: 25vh" >
<img class="card-img-top col-12 rounded-circle" src="';
if(file_exists('../../images/users/'.$users[$i][3])&&($users[$i][3]!=""))
{
$display.='../../images/users/'.$users[$i][3];
}
else
{
$display.='https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
$display.='" alt="Card image" >
</div>
<h4 align="center" ><i class="fas fa-user mr-1"></i> '.$users[$i][1].'</h4>';
if($users[$i][2]!="")
{
$display.='
<i>Expire</i>';
}
$display.='</a>';
}
echo $display;
?>
</div>
<!--Hall Branches-->
<div class="col-12 mt-5 row">
<h2 align="center" class=" col-6"> <i class="fas fa-place-of-worship mr-2"></i> Halls</h2>
<a href="../hallBranches/hallRegister.php" class="btn btn-success col-6"><i class="fas fa-plus"></i><i class="fas fa-place-of-worship mr-2"></i>Add Hall</a>
</div>
<hr class="border border-white">
<div class="form-group row shadow newcolor " id="hallbranches">
<?php
$sql='SELECT `id`, `name`, `expire`, `image` FROM `hall` WHERE company_id='.$companyid.'';
$halldetails=queryReceive($sql);
$display='';
for($i=0;$i<count($halldetails);$i++)
{
$display.='
<a href="?action=hall&id='.$halldetails[$i][0].'" class="col-sm-12 col-md-4 col-xl-3 m-2">
<div class="card col-12 rounded-circle shadow" style="height: 25vh" >
<img class="card-img-top col-12 rounded-circle" src="';
if((file_exists('../../images/hall/'.$halldetails[$i][3]))&&($halldetails[$i][3]!=""))
{
$display.= "../../images/hall/".$halldetails[$i][3];
}
else
{
$display.='https://thumbs.dreamstime.com/z/wedding-hall-decoration-reception-party-35933352.jpg';
}
$display.='" alt="Card image" >
</div>
<h4 align="center" ><i class="fas fa-place-of-worship mr-1"></i>'.$halldetails[$i][1].'</h4>';
if($halldetails[$i][2]!="")
{
$display.='
<i>Expire</i>';
}
$display.='</a>';
}
echo $display;
?>
</div>
<!--Catering Branches-->
<div class="col-12 mt-5 row">
<h2 align="center" class="col-7"> <i class="fas fa-utensils"></i> Caterings</h2>
<a href="../cateringBranches/catering.php" class="btn btn-success col-5"><i class="fas fa-plus"></i> <i class="fas fa-utensils"></i> Add Catering</a>
</div>
<hr class="border border-white">
<div class="form-group row shadow newcolor" id="cateringbranches">
<?php
$sql='SELECT `id`, `name`, `expire`, `image` FROM `catering` WHERE company_id='.$companyid.'';
$cateringdetails=queryReceive($sql);
$display='';
for($i=0;$i<count($cateringdetails);$i++)
{
$display.='
<a href="?action=catering&id='.$cateringdetails[$i][0].'" class="col-sm-12 col-md-4 col-xl-3 m-2">
<div class="card col-12 rounded-circle shadow" style="height: 25vh" >
<img class="card-img-top col-12 rounded-circle" src="';
if((file_exists('../../images/catering/'.$cateringdetails[$i][3]))&&($cateringdetails[$i][3]!=""))
{
$display.= "../../images/catering/".$cateringdetails[$i][3];
}
else
{
$display.='https://www.liberaldictionary.com/wp-content/uploads/2019/02/cater-4956.jpg';
}
$display.='" alt="Card image" >
</div>
<h4 align="center"><i class="fas fa-utensils mr-1"></i>'.$cateringdetails[$i][1].'</h4>';
if($cateringdetails[$i][2]!="")
{
$display.='
<i>Expire</i>';
}
$display.='</a>';
}
echo $display;
?>
</div>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include ("../../connection/connect.php");
$hallid=$_SESSION['branchtypeid'];
$orderid=$_SESSION['order'];
$sql='SELECT `id`, `hall_id`, `catering_id`, (SELECT hp.isFood from hallprice as hp WHERE hp.id=orderDetail.hallprice_id),
`user_id`, `sheftCatering`, `sheftHall`, `sheftCateringUser`,
`sheftHallUser`, `address_id`, `person_id`, `total_amount`,
`total_person`, `status_hall`, `destination_date`,
`booking_date`, `destination_time`, `status_catering`,
`notice`,`describe`,(SELECT hp.describe from hallprice as hp WHERE hp.id=orderDetail.hallprice_id),hallprice_id,(SELECT hp.price from hallprice as hp WHERE hp.id=orderDetail.hallprice_id) FROM `orderDetail` WHERE id='.$orderid.'';
$detailorder=queryReceive($sql);
$sql='SELECT c.id, c.name,c.image FROM catering as c WHERE c.company_id=(SELECT h.company_id from hall as h where h.id='.$hallid.') AND (ISNULL(c.expire))';
$cateringids=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://cdn.flatworldsolutions.com/featured-images/outsource-outbound-call-center-services.jpg);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 ><i class="fas fa-cart-arrow-down fa-3x mr-2"></i>Edit order</h3>
</div>
</div>
<div class="container card-header shadow">
<form class="form">
<div class="form-group row">
<label class="col-form-label">No of Guests</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-users"></i></span>
</div>
<input name="guests" type="number" class="form-control" value="<?php echo $detailorder[0][12]; ?>">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-calendar-alt"></i></span>
</div>
<input id="date" name="date" type="date" class="checkpackage form-control" value="<?php echo $detailorder[0][14]; ?>">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Time</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-clock"></i></span>
</div>
<select id="time" name="time" class="checkpackage form-control">
<?php
///////set time
if($detailorder[0][16]=="09:00:00")
{
//morning
echo '
<option value="Morning">Morning</option>
<option value="Afternoon">Afternoon</option>
<option value="Evening">Evening</option>';
}
else if($detailorder[0][16]=="12:00:00")
{
//afternoon
echo '
<option value="Afternoon">Afternoon</option>
<option value="Morning">Morning</option>
<option value="Evening">Evening</option>';
}
else
{
//evening
echo '
<option value="Evening">Evening</option>
<option value="Morning">Morning</option>
<option value="Afternoon">Afternoon</option>';
}
?>
</select>
</div>
</div>
<div class="form-group row">
<label class="col-form-label ">Per Head With</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-utensils"></i></span>
</div>
<select id="perheadwith" name="perheadwith" class="checkpackage form-control">
<?php
if($detailorder[0][3]==0)
{
// only seating
echo '
<option value="0">Only seating</option>
<option value="1">Food + Seating</option>';
}
else
{
//food and seating
echo '
<option value="1">Food + Seating</option>
<option value="0">Only seating</option>';
}
?>
</select>
</div>
</div>
<?php
if(count($cateringids)>0)
{
$display = '
<div class="form-group row" id="cateringid">
<label class="col-form-label ">Catereing Branch</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-utensils"></i></span>
</div>
<select name="cateringid" class="form-control">
';
if($detailorder[0][2]!="")
{
$sql = 'SELECT `id`, `name` FROM `catering` WHERE id=' . $detailorder[0][2] . '';
$selectedcatering = queryReceive($sql);
$display .= '
<option value="' . $selectedcatering[0][0] . '">' . $selectedcatering[0][1] . '</option>';
for ($i = 0; $i < count($cateringids); $i++) {
if ($selectedcatering[0][0] != $cateringids[$i][0]) {
$display .= '
<option value="' . $cateringids[$i][0] . '">' . $cateringids[$i][1] . '</option>';
}
}
}
else
{
for ($i = 0; $i < count($cateringids); $i++)
{
$display .= '
<option value="' . $cateringids[$i][0] . '">' . $cateringids[$i][1] . '</option>';
}
}
$display .= '
</select>
</div>
</div>';
echo $display;
}
?>
<div id="groupofpackages" class="col-12 alert-warning shadow">
</div>
<div id="selectmenu" class="alert-info m-2 form-group row shadow" >
</div>
<div class="form-group row">
<label class="col-form-label">Describe /Comments</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-comments"></i></span>
</div>
<textarea name="describe" class="form-control"><?php echo $detailorder[0][19]; ?></textarea></textarea>
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Total amount:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-money-bill-alt"></i></span>
</div>
<input name="totalamount" type="number" class="form-control" value="<?php echo $detailorder[0][11]; ?>">
</div>
</div>
<?php
$status=array("Running","Deliever","Cancel","Clear");
$display='
<div class="form-group row">
<label class="col-form-label">Order status</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-eye"></i></span>
</div>';
$display.=' <select name="orderStatus" class=" form-control">
<option value="'.$detailorder[0][13].'">'.$detailorder[0][13].'</option>';
for($i=0;$i<count($status);$i++)
{
if($status[$i]!=$detailorder[0][13])
{
$display.='<option value="'.$status[$i].'">'.$status[$i].'</option>';
}
}
$display.=' </select>
</div>
</div>';
echo $display;
?>
<div class="form-group row">
<label class="col-form-label">Booked date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-business-time"></i></span>
</div>
<input readonly type="date" class="form-control" value="<?php echo $detailorder[0][15]; ?>">
</div>
</div>
<div class="form-group row justify-content-center">
<button id="cancel" type="button" class=" col-4 btn btn-danger" value="Cancel"><i class="fas fa-arrow-circle-left"></i>back</button>
<button id="submitform" type="button" class=" col-4 btn btn-success" value="Save"><i class="fas fa-check "></i>Save</button>
</div>
</form>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
function barnches()
{
var perheadwith = $("#perheadwith").val();
if(perheadwith==1)
{
$("#cateringid").show();
}
else
{
$("#cateringid").hide();
}
}
$("#perheadwith").change(function ()
{
barnches();
});
barnches();
$("#cancel").click(function ()
{
window.history.back();
});
function checkpackage(date, time, perheadwith)
{
if ((date != "") && (time != "") && (perheadwith != "")) {
return 1;
}
return 0;
}
$(".checkpackage").change(function () {
var date = $("#date").val();
var month = new Date(date).getMonth();
var time = $("#time").val();
var perheadwith = $("#perheadwith").val();
$("#selectmenu").html("");
if (!checkpackage(date, time, perheadwith))
{
return false;
}
var formdata = new FormData;
formdata.append("date",date);
formdata.append("month", month);
formdata.append("time", time);
formdata.append("perheadwith", perheadwith);
formdata.append("option", "checkpackages1");
formdata.append("hallid",<?php echo $hallid;?>);
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data)
{
if(perheadwith==1)
{
if (data == "")
{
$("#submitform").hide("slow");
$("#groupofpackages").html(data+"<h1 class='text-danger'>No Packages found:so order not submit</h1>");
} else {
$("#groupofpackages").html(data);
$("#submitform").show("slow");
}
}
else
{
$("#groupofpackages").html(data);
$("#submitform").show("slow");
}
}
});
});
function menushow(packageid,describe)
{
var formdata = new FormData;
formdata.append("packageid", packageid);
formdata.append("option", "viewmenu");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data)
{
$("#selectmenu").html(data);
$("#selectmenu").append("<h3 align='center' class='col-12'>Menu Description</h3><p class='col-12'>"+describe+"</p>");
}
});
}
menushow(<?php echo $detailorder[0][21]; ?>,"<?php echo $detailorder[0][20]; ?>"+"<span class='btn-danger'> .... with price is <?php echo $detailorder[0][22]; ?></span>");
$(document).on("click","input[type=radio]",function ()
{
var packageid=$("input[name='defaultExampleRadios']:checked").val();
if($("#perheadwith").val()!="1")
return false;
var describe=$("#describe"+packageid).val();
menushow(packageid,describe);
});
var packageid=<?php echo $detailorder[0][21]; ?>;
$("#submitform").click(function ()
{
var date = $("#date").val();
var time = $("#time").val();
var perheadwith = $("#perheadwith").val();
if (!checkpackage(date, time, perheadwith))
{
alert("Please select Date,Time and Per Head");
return false;
}
if($(".checkclasshas")[0])
{
packageid=$("input[name='defaultExampleRadios']:checked").val();
if(!packageid)
{
alert("Please select Package From Package Detail");
return false;
}
}
var formdata = new FormData($("form")[0]);
formdata.append("perheadwith",perheadwith);
formdata.append("packageid", packageid);
formdata.append("order",<?php echo $orderid; ?>);
formdata.append("option", "Edithallorder");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
success: function (data)
{
if(data!="")
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-03
* Time: 17:20
*/
include_once ("../../connection/connect.php");
if(isset($_POST['option']))
{
if($_POST['option']=="createUser")
{
$username=chechIsEmpty($_POST['username']);
$password=chechIsEmpty($_POST['password']);
$sql='SELECT u.id FROM user as u WHERE (u.password="'.$password.'") AND (u.username="'.$username.'")';
$userExist=queryReceive($sql);
if(count($userExist)!=0)
{
echo "user is already exist";
exit();
}
$name = trim($_POST['name']);
$numberArray = $_POST['number'];
$isowner=0;
if(isset($_POST['isowner']))
{
if($_POST['isowner']=="yes")
{
$isowner=1;
}
}
$cnic = $_POST['cnic'];
$city = $_POST['city'];
$area = $_POST['area'];
$streetNo = chechIsEmpty($_POST['streetNo']);
$houseNo = chechIsEmpty($_POST['houseNo']);
$date = date('Y-m-d');
$sql='INSERT INTO `person`(`name`, `cnic`, `id`, `date`) VALUES ("'.$name.'","'.$cnic.'",NULL,"'.$date.'")';
querySend($sql);
$last_id = mysqli_insert_id($connect);
$sql="INSERT INTO `address` (`id`, `address_street_no`, `address_house_no`, `person_id`, `address_city`, `address_town`) VALUES (NULL, '".$streetNo."', '".$houseNo."', '".$last_id."', '".$city."', '".$area."');";
querySend($sql);
for ($i=0;$i<count($numberArray);$i++)
{
$sql = "INSERT INTO `number`(`number`, `id`, `is_number_active`, `person_id`) VALUES ('".$numberArray[$i]."',NULL,1,$last_id)";
querySend($sql);
}
$customerId = $last_id;
$sql='INSERT INTO `user`(`id`, `username`, `password`, `person_id`, `isExpire`,`isowner`) VALUES (NULL,"'.$username.'","'.$password.'",'.$customerId.',NULL,"'.$isowner.'")';
querySend($sql);
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include ("../../connection/connect.php");
if(!isset($_COOKIE['companyid']))
{
header("location:../../user/userLogin.php");
}
$companyid=$_COOKIE['companyid'];
if(isset($_SESSION['order']))
{
unset($_SESSION['order']);
}
if(isset($_SESSION['customer']))
{
unset($_SESSION['customer']);
}
if(isset($_GET['branchtype']))
{
if($_GET['branchtype']=="hall")
{
$_SESSION['branchtype']="hall";
}
else
{
$_SESSION['branchtype']="catering";
}
$_SESSION['branchtypeid']=$_GET['branchtypeid'];
header("location:../../user/userDisplay.php");
}
$sql='SELECT c.name FROM company as c WHERE c.id='.$companyid.'';
$companydetail=queryReceive($sql);
$sql='SELECT `id`, `name`,`image` FROM `hall` WHERE ISNULL(expire) AND (company_id='.$companyid.')';
$halls=queryReceive($sql);
$sql='SELECT `id`, `name`,`image` FROM `catering` WHERE ISNULL(expire) AND (company_id='.$companyid.')';
$caterings=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
#hallbranches
{
width: 100%;/*
height: 50vh;
overflow: auto;*/
background-size: 100% 100%;
}
#cateringbranches
{
width: 100%;
/* height: 50vh;
overflow: auto;*/
background-size: 100% 100%;
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow " style="background-image: url(https://i2.wp.com/findlawyer.com.ng/wp-content/uploads/2018/05/Pros-and-Cons-of-Working-at-Large-Companies.jpg?resize=1024%2C512&ssl=1);background-size:100% 115%;background-repeat: no-repeat;">
<div class="card-body text-center" style="opacity: 0.7 ;background: white;">
<h1 class="display-5 "><i class="fas fa-city mr-2"></i><?php echo $companydetail[0][0];?></h1>
<p>check your orders of hall and as well as catering</p>
<?php
if($_COOKIE['isOwner']==1)
{
echo ' <h1 class="text-center"> <a href="companyEdit.php" class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
';
}
?>
</div>
</div>
<h1><i class="fas fa-place-of-worship"></i>Hall Branches</h1>
<hr class="border border-white">
<div class="col-12 m-1 mb-5 form-group row shadow" id="hallbranches" >
<?php
$display='';
for ($i=0;$i<count($halls);$i++)
{
$display.= '
<a href="?branchtype=hall&branchtypeid='.$halls[$i][0].'"
class="col-sm-12 col-md-4 col-xl-3 m-2 shadow border text-white" >
<img class="card-img-top col-12 p-0" src="';
if((file_exists('../../images/hall/'.$halls[$i][2]))&&($halls[$i][2]!=""))
{
$display.= "../../images/hall/".$halls[$i][2];
}
else
{
$display.='https://thumbs.dreamstime.com/z/wedding-hall-decoration-reception-party-35933352.jpg';
}
$display.='" alt="Card image" style="height: 25vh" >
<h4 align="center" class="alert-dark"><i class="fas fa-place-of-worship mr-1"></i>'.$halls[$i][1].'</h4>
</a>';
}
echo $display;
?>
</div>
<h2><i class="fas fa-utensils mr-2"></i>Catering Branches</h2>
<hr class="border border-white">
<div class="col-12 m-1 mb-5 form-group row shadow border " id="cateringbranches" >
<?php
$display='';
for ($i=0;$i<count($caterings);$i++)
{
$display.= '
<a href="?branchtype=catering&branchtypeid='.$caterings[$i][0].'" class="col-sm-12 col-md-4 col-xl-3 m-2 border text-white">
<img class="card-img-top col-12 p-0" src="';
if((file_exists('../../images/catering/'.$caterings[$i][2]))&&($caterings[$i][2]!=""))
{
$display.= "../../images/catering/".$caterings[$i][2];
}
else
{
$display.='https://www.liberaldictionary.com/wp-content/uploads/2019/02/cater-4956.jpg';
}
$display.='" alt="Card image" style="height: 25vh ;background-size:150% 140%;">
<h4 align="center" class="alert-dark"><i class="fas fa-utensils mr-2"></i>'.$caterings[$i][1].'</h4>
</a>';
}
echo $display;
?>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
</script>
</body>
</html>
<file_sep>-- MySQL Script generated by MySQL Workbench
-- Wed Sep 18 22:16:18 2019
-- Model: New Model Version: 1.0
-- MySQL Workbench Forward Engineering
SET @OLD_UNIQUE_CHECKS=@@UNIQUE_CHECKS, UNIQUE_CHECKS=0;
SET @OLD_FOREIGN_KEY_CHECKS=@@FOREIGN_KEY_CHECKS, FOREIGN_KEY_CHECKS=0;
SET @OLD_SQL_MODE=@@SQL_MODE, SQL_MODE='TRADITIONAL,ALLOW_INVALID_DATES';
-- -----------------------------------------------------
-- Schema mydb
-- -----------------------------------------------------
-- -----------------------------------------------------
-- Schema id10884474_catering
-- -----------------------------------------------------
-- -----------------------------------------------------
-- Schema id10884474_catering
-- -----------------------------------------------------
CREATE SCHEMA IF NOT EXISTS `id10884474_catering` DEFAULT CHARACTER SET utf8mb4 ;
USE `id10884474_catering` ;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`person`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`person` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`person` (
`name` VARCHAR(30) NULL,
`cnic` VARCHAR(30) NULL,
`id` INT(11) NOT NULL AUTO_INCREMENT,
`date` DATE NULL,
`image` TEXT(200) NULL DEFAULT NULL,
PRIMARY KEY (`id`))
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`address`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`address` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`address` (
`id` INT(11) NOT NULL AUTO_INCREMENT,
`address_city` VARCHAR(50) NULL DEFAULT 'lahore',
`address_town` VARCHAR(50) NULL,
`address_street_no` INT(11) NULL DEFAULT NULL,
`address_house_no` INT(11) NULL DEFAULT NULL,
`person_id` INT(11) NULL,
PRIMARY KEY (`id`),
INDEX `fk_address_person1_idx` (`person_id` ASC),
CONSTRAINT `fk_address_person1`
FOREIGN KEY (`person_id`)
REFERENCES `id10884474_catering`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`number`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`number` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`number` (
`number` VARCHAR(30) NULL,
`id` INT(11) NOT NULL AUTO_INCREMENT,
`is_number_active` TINYINT NULL DEFAULT 1,
`person_id` INT(11) NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_number_person1_idx` (`person_id` ASC),
CONSTRAINT `fk_number_person1`
FOREIGN KEY (`person_id`)
REFERENCES `id10884474_catering`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`orderTable`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`orderTable` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`orderTable` (
`id` INT(11) NOT NULL AUTO_INCREMENT,
`total_amount` INT(11) NULL DEFAULT 0,
`order_comments` TEXT NULL DEFAULT NULL,
`total_person` INT NULL,
`is_active` INT NULL DEFAULT 0,
`destination_date` DATE NULL,
`booking_date` DATE NULL,
`destination_time` TIME(6) NULL,
`address_id` INT(11) NOT NULL,
`extre_charges` INT NULL,
`person_id` INT(11) NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_order_address1_idx` (`address_id` ASC),
INDEX `fk_order_person1_idx` (`person_id` ASC),
CONSTRAINT `fk_order_address1`
FOREIGN KEY (`address_id`)
REFERENCES `id10884474_catering`.`address` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_order_person1`
FOREIGN KEY (`person_id`)
REFERENCES `id10884474_catering`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`dish_type`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`dish_type` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`dish_type` (
`id` INT NOT NULL AUTO_INCREMENT,
`name` VARCHAR(45) NULL,
`isExpire` DATETIME NULL DEFAULT NULL,
PRIMARY KEY (`id`))
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`dish`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`dish` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`dish` (
`name` VARCHAR(30) NULL,
`id` INT NOT NULL AUTO_INCREMENT,
`image` VARCHAR(300) NULL,
`dish_type_id` INT NOT NULL,
`isExpire` DATETIME NULL DEFAULT NULL,
PRIMARY KEY (`id`),
INDEX `fk_dish_dish_type1_idx` (`dish_type_id` ASC),
CONSTRAINT `fk_dish_dish_type1`
FOREIGN KEY (`dish_type_id`)
REFERENCES `id10884474_catering`.`dish_type` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`attribute`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`attribute` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`attribute` (
`name` VARCHAR(45) NULL,
`id` INT NOT NULL AUTO_INCREMENT,
`dish_id` INT NOT NULL,
`isExpire` DATETIME NULL DEFAULT NULL,
PRIMARY KEY (`id`),
INDEX `fk_attribute_dish1_idx` (`dish_id` ASC),
CONSTRAINT `fk_attribute_dish1`
FOREIGN KEY (`dish_id`)
REFERENCES `id10884474_catering`.`dish` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`dish_detail`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`dish_detail` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`dish_detail` (
`id` INT NOT NULL AUTO_INCREMENT,
`describe` TEXT(300) NULL,
`price` INT NULL,
`expire_date` DATETIME NULL,
`quantity` INT NULL,
`dish_id` INT NOT NULL,
`orderTable_id` INT(11) NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_dish_detail_dish1_idx` (`dish_id` ASC),
INDEX `fk_dish_detail_orderTable1_idx` (`orderTable_id` ASC),
CONSTRAINT `fk_dish_detail_dish1`
FOREIGN KEY (`dish_id`)
REFERENCES `id10884474_catering`.`dish` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_dish_detail_orderTable1`
FOREIGN KEY (`orderTable_id`)
REFERENCES `id10884474_catering`.`orderTable` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`attribute_name`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`attribute_name` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`attribute_name` (
`id` INT NOT NULL AUTO_INCREMENT,
`quantity` INT NULL,
`attribute_id` INT NOT NULL,
`dish_detail_id` INT NOT NULL,
PRIMARY KEY (`id`),
INDEX `fk_attribute_name_attribute1_idx` (`attribute_id` ASC),
INDEX `fk_attribute_name_dish_detail1_idx` (`dish_detail_id` ASC),
CONSTRAINT `fk_attribute_name_attribute1`
FOREIGN KEY (`attribute_id`)
REFERENCES `id10884474_catering`.`attribute` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_attribute_name_dish_detail1`
FOREIGN KEY (`dish_detail_id`)
REFERENCES `id10884474_catering`.`dish_detail` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`user`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`user` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`user` (
`id` INT NOT NULL AUTO_INCREMENT,
`username` VARCHAR(45) NULL,
`password` VARCHAR(30) NULL,
`person_id` INT(11) NOT NULL,
`isExpire` DATETIME NULL DEFAULT NULL,
`isowner` TINYINT NULL DEFAULT 0,
PRIMARY KEY (`id`),
INDEX `fk_user_person1_idx` (`person_id` ASC),
CONSTRAINT `fk_user_person1`
FOREIGN KEY (`person_id`)
REFERENCES `id10884474_catering`.`person` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`payment`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`payment` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`payment` (
`id` INT NOT NULL AUTO_INCREMENT,
`amount` INT NULL,
`nameCustomer` VARCHAR(45) NULL,
`receive` DATETIME NULL,
`personality` TEXT(300) NULL,
`rating` INT NULL,
`IsReturn` TINYINT NULL,
`user_id` INT NOT NULL,
`orderTable_id` INT(11) NOT NULL,
`sendingStatus` INT NULL DEFAULT 0,
PRIMARY KEY (`id`),
INDEX `fk_payment_user1_idx` (`user_id` ASC),
INDEX `fk_payment_orderTable1_idx` (`orderTable_id` ASC),
CONSTRAINT `fk_payment_user1`
FOREIGN KEY (`user_id`)
REFERENCES `id10884474_catering`.`user` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_payment_orderTable1`
FOREIGN KEY (`orderTable_id`)
REFERENCES `id10884474_catering`.`orderTable` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
-- -----------------------------------------------------
-- Table `id10884474_catering`.`transfer`
-- -----------------------------------------------------
DROP TABLE IF EXISTS `id10884474_catering`.`transfer` ;
CREATE TABLE IF NOT EXISTS `id10884474_catering`.`transfer` (
`id` INT NOT NULL AUTO_INCREMENT,
`Isconfirm` DATETIME NULL,
`senderTimeDate` DATETIME NULL,
`payment_id` INT NOT NULL,
`user_id` INT NOT NULL,
`Isget` TINYINT NULL,
PRIMARY KEY (`id`),
INDEX `fk_transfer_payment1_idx` (`payment_id` ASC),
INDEX `fk_transfer_user1_idx` (`user_id` ASC),
CONSTRAINT `fk_transfer_payment1`
FOREIGN KEY (`payment_id`)
REFERENCES `id10884474_catering`.`payment` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION,
CONSTRAINT `fk_transfer_user1`
FOREIGN KEY (`user_id`)
REFERENCES `id10884474_catering`.`user` (`id`)
ON DELETE NO ACTION
ON UPDATE NO ACTION)
ENGINE = InnoDB;
SET SQL_MODE=@OLD_SQL_MODE;
SET FOREIGN_KEY_CHECKS=@OLD_FOREIGN_KEY_CHECKS;
SET UNIQUE_CHECKS=@OLD_UNIQUE_CHECKS;
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../connection/connect.php");
if(isset($_GET['action']))
{
if($_GET['action']=="expire")
{
$date=date('Y-m-d H:i:s');
$sql='UPDATE `user` SET `isExpire`="'.$date.'" WHERE id='.$_SESSION['tempid'].'';
}
else
{
$sql='UPDATE `user` SET `isExpire`=NULL WHERE id='.$_SESSION['tempid'].'';
}
querySend($sql);
header("location:../../company/companyRegister/companyEdit.php");
}
$userid=$_SESSION['tempid'];
$sql='SELECT `username`, `password`, `person_id`, `isExpire`, `isowner` FROM `user` WHERE id='.$userid.'';
$userdetail=queryReceive($sql);
$customerId=$userdetail[0][2];
$sql = "SELECT `name`, `cnic`, `id`, `date`, `image` FROM `person` WHERE id=".$customerId."";
$person=queryReceive($sql);
$sql = "SELECT a.id, a.address_city, a.address_town, a.address_street_no, a.address_house_no, a.person_id FROM address as a inner JOIN person p ON a.person_id=p.id
WHERE a.person_id=$customerId
ORDER by a.person_id;";
$address=queryReceive($sql);
$sql="SELECT n.number, n.id, n.is_number_active, n.person_id FROM number as n inner JOIN person as p ON p.id=n.person_id
WHERE p.id=$customerId
order BY n.id";
$numbers=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<style>
</style>
</head>
<body >
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://jumpcloud.com/wp-content/uploads/2017/01/function-of-identity-as-a-service.jpg);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-body text-center" style="opacity: 0.7 ;background: #fdfdff;">
<h3 ><i class="fas fa-user fa-4x"></i> Edit <?php echo $person[0][0]; ?> User </h3>
<p>Edit Exiting user </p>
<a href="../../company/companyRegister/companyEdit.php" class="col-6 btn btn-info"> <i class="fas fa-city mr-2"></i>Edit Company</a>
</div>
</div>
<div class="container ">
<form id="changeImage" class="col-12" style="margin-top: -50px">
<?php
echo '<input name="customerid" hidden value="'.$customerId.'">';
?>
<input name="image" hidden value="<?php echo $person[0][4] ?>">
<div class=" form-group row justify-content-center">
<img src="<?php
if(file_exists($person[0][4]))
{
echo $person[0][4];
}
else
{
echo "https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png";
}
?> " style="height: 30vh" alt="image is not set">
</div>
<div class="form-group row justify-content-center">
<label class="form-check-label">Change user image:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input name="image" id="submitImage" type="file" class="form-control float-right btn-warning col-9">
</div>
</div>
</form>
<form class="col-12 card shadow p-4 mb-3" id="authorchanging">
<h3 align="center"> Create LogIn form</h3>
<input hidden name="userid" value="<?php echo $userid;?>">
<div class="form-group row">
<label for="username" class="col-form-label ">User Name</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user"></i></span>
</div>
<input type="text" id="username" name="username" class="form-control" value="<?php echo $userdetail[0][0];?>">
</div>
</div>
<div class="form-group row">
<label for="password" class="col-form-label">Password</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-key"></i></span>
</div>
<input type="text" id="password" name="password" class="form-control" value="<?php echo $userdetail[0][1];?>">
</div>
</div>
<div class="form-group row">
<label for="password1" class="col-form-label ">Confirm Password</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-key"></i></span>
</div>
<input type="text" id="password1" name="password1" class="form-control" value="<?php echo $userdetail[0][1];?>">
</div>
</div>
<div class="col-12 row justify-content-center">
<?php
if($userdetail[0][3]=="")
{
echo '<a href="?action=expire" class="btn btn-danger col-6">Expire</a>';
}
else
{
echo '<a href="?action=active" class="btn btn-warning col-6">Active</a>';
}
?>
<input id="authorbtn" type="button" class="float-right btn btn-outline-primary col-6" value="Save">
</div>
</form>
<form id="form" >
<?php
echo '<input id="customerId" type="number" hidden value="'.$customerId.'">';
?>
<div class="col-12" id="number_records">
<?php
for($i=0;$i<count($numbers);$i++)
{
echo '
<div class="form-group row" id="Each_number_row_'.$numbers[$i][1].'">
<label class="col-3 col-form-label" for="number_'.$numbers[$i][1].'"><i class="fas fa-phone-volume"></i>Phone no:</label>
<input class=" numberchange allnumber form-control col-7" type="text" name="number[]" value="'.$numbers[$i][0].'" id="number_'.$numbers[$i][1].'" data-columne="number" data-columneid='.$numbers[$i][1].'>
<input class="form-control btn btn-danger col-2 remove_number " id="remove_numbers_'.$numbers[$i][1].'" data-removenumber="'.$numbers[$i][1].'" value="-">
</div>';
}
?>
</div>
<div class="form-group row" >
<label for="newNumber" class="col-form-label">New Number</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-phone-volume"></i></span>
</div>
<input id="newNumber" name="newNumber"class="form-control" >
<input type="button" value="+" class="col-2 btn-success form-control" id="newadd">
</div>
</div>
<div class="form-group row">
<label for="name" class="col-form-label"> Name:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-address-book"></i></span>
</div>
<?php
echo'<input type="text" id="name" name="name" class=" personchange form-control" value="'.$person[0][0].'" data-columne="name">';
?>
</div>
</div>
<div class="form-group row">
<label for="cnic" class="col-form-label"> CNIC:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-id-card"></i></span>
</div>
<?php
echo '
<input type="number" id="cnic" name="cnic" class=" personchange form-control col-9" value="'.$person[0][1].'" data-columne="cnic">';
?>
</div>
</div>
<h3 align="center"><i class="fas fa-map-marker-alt"></i> Address (optional)</h3>
<div class="form-group row">
<label for="city" class="col-form-label"> City:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-city"></i></span>
</div>
<?php
echo '<input type="text" id="city" name="city" class=" addresschange form-control" value="'.$address[0][1].'" data-columne="address_city">';
?>
</div>
</div>
<div class="form-group row">
<label for="area" class="col-form-label"> Area/ Block:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-road"></i></span>
</div>
<?php
echo '<input type="text" id="area" name="area" class=" addresschange form-control " value="'.$address[0][2].'" data-columne="address_town">';
?>
</div>
</div>
<div class="form-group row">
<label for="streetNo" class="col-form-label">Street No :</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-street-view"></i></span>
</div>
<?php
echo ' <input type="number" id="streetNo" name="streetNo" class=" addresschange form-control " value="'.$address[0][3].'" data-columne="address_street_no">';
?>
</div>
</div>
<div class="form-group row">
<label for="houseNo" class="col-form-label">House No:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-home"></i></span>
</div>
<?php
echo '<input type="number" id="houseNo" name="houseNo" class=" addresschange form-control" value="'.$address[0][4].'" data-columne="address_house_no">';
?>
</div>
</div>
<div class="col-12 shadow">
<h4 align="center">Customer personality</h4>
<?php
$sql='SELECT py.personality,py.rating FROM person as p INNER join orderDetail as od
on p.id=od.person_id
INNER JOIN payment as py
on od.id=py.orderDetail_id
WHERE
p.id='.$customerId.'';
$personalitydetails=queryReceive($sql);
for ($k=0;$k<count($personalitydetails);$k++)
{
echo '
<p class=" mb-3 form-control">'.$personalitydetails[$k][0].' <span class="float-right border-danger border font-weight-bold">Rating: '.$personalitydetails[$k][1].' </span> </p>';
}
?>
</div>
</form>
<div class="form-group row justify-content-center">
<button class="col-6 form-control btn btn-danger" id="Doneform"><i class="fas fa-check "></i>Done</button>
</div>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
var customerid=$("#customerId").val();
function execute_person_address(column,text,type)
{
$.ajax({
url: "userServer.php",
data:{columnname:column,value:text,edittype:type,option:"change",customerid:customerid},
dataType:"text",
method:"POST",
success:function (data)
{
if(data!='')
{
alert(data);
}
}
});
}
function execute_number(column,text,type,id)
{
$.ajax({
url: "userServer.php",
data:{columnname:column,value:text,edittype:type,id:id,option:"change",customerid:customerid},
dataType:"text",
method:"POST",
success:function (data)
{
if(data!='')
{
alert(data);
}
}
});
}
$(document).on('change','.addresschange',function () {
//address change
var column=$(this).data("columne");
var text=$(this).val();
execute_person_address(column,text,1);
});
$(document).on('change','.personchange',function () {
//personchange change
var column=$(this).data("columne");
var text=$(this).val();
execute_person_address(column,text,2);
});
$(document).on('change','.numberchange',function () {
//numberchange change
var column=$(this).data("columne");
var id=$(this).data("columneid");
var text=$(this).val();
execute_number(column,text,3,id);
});
$("#newadd").click(function ()
{
var numberText=$('#newNumber').val();
$.ajax({
url: "userServer.php",
data:{option:"addNumber",number:numberText,customerid:customerid},
dataType:"text",
method:"POST",
success:function (data) {
if(data!='')
{
alert(data);
}
else
{
location.reload()
}
}
});
});
$(document).on("click",".remove_number",function () {
var id=$(this).data("removenumber");
$.ajax({
url: "userServer.php",
data:{ id:id,option:"deleteNumber"},
dataType:"text",
method:"POST",
success:function (data) {
if(data!='')
{
alert(data);
}
else
{
$("#Each_number_row_"+id).remove();
}
}
});
});
$("#submitImage").change(function () {
var formData=new FormData($("#changeImage")[0]);
formData.append("option","changeImage");
$.ajax({
url:"userServer.php",
method:"POST",
data:formData,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
location.reload();
}
}
});
});
$("#authorbtn").click(function ()
{
if(!(($("#username").val().length>5) && ($("#username").length<9)))
{
alert("Username must be 6 to 8 letters")
return false;
}
if(!(($("#password").val().length>5) && ($("#password").length<9)))
{
alert("password must be 6 to 8 letters")
return false;
}
var formdata=new FormData($("#authorchanging")[0]);
formdata.append("option","authorChange");
$.ajax({
url:"userServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
$("#Doneform").click(function () {
window.history.back();
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-10
* Time: 11:50
*/
include_once ("../connection/connect.php");
if(isset($_POST["option"]))
{
if($_POST['option']=="login")
{
$userName=$_POST['username'];
$password=$_POST['password'];
$sql='SELECT u.id,u.isOwner FROM user as u WHERE (u.username="'.$userName.'")AND(u.password="'.$password.'")';
$userDetail=queryReceive($sql);
if(count($userDetail)==0)
{
echo "please user is not registerd";
}
else
{
setcookie('userid',$userDetail[0][0] , time() + (86400 * 30), "/");
setcookie("isOwner",$userDetail[0][1],time() + (86400 * 30), "/");
setcookie("username",$userName,time() + (86400 * 30), "/");
}
}
}
?><file_sep><?php
include_once ('../../connection/connect.php');
if(!isset($_GET['hall']))
{
header("location:../companyRegister/companyEdit.php");
}
$encoded=$_GET['hall'];
$id=base64url_decode($encoded);
if((!is_numeric($id))||$id=="")
{
header("location:../companyRegister/companyEdit.php");
}
if(isset($_GET['editpackage']))
{
$packageEncoded=base64url_decode($_GET['packageid']);
header("location:Editpackage.php?hallname=".$_GET['hallname']."&month=".$_GET['month']."&daytime=".$_GET['daytime']."&hall=".$encoded."&pack=".$packageEncoded."");
}
$hallid='';
$companyid='';
$hallid=$id;
$companyid=$_COOKIE['companyid'];
$sql='SELECT `name`, `max_guests`, `noOfPartitions`, `ownParking`, `expire`, `image`, `hallType`, `location_id` FROM `hall` WHERE id='.$hallid.'';
$halldetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
#showDaytimes
{
background: #dd3e54; /* fallback for old browsers */
background: -webkit-linear-gradient(to right, #6be585, #dd3e54); /* Chrome 10-25, Safari 5.1-6 */
background: linear-gradient(to right, #6be585, #dd3e54); /* W3C, IE 10+/ Edge, Firefox 16+, Chrome 26+, Opera 12+, Safari 7+ */
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron jumbotron-fluid text-center" style="background-image: url(<?php
if((file_exists('../../images/hall/'.$halldetail[0][5]))&&($halldetail[0][5]!=""))
{
echo "'../../images/hall/".$halldetail[0][5]."'";
}
else
{
echo "https://www.pakvenues.com/system/halls/cover_images/000/000/048/original/Umar_Marriage_Hall_lahore.jpg?1566758537";
}
?>);background-repeat: no-repeat ;background-size: 100% 100%">
<div class="container" style="background-color: white;opacity: 0.7">
<h1 class="display-4"><i class="fas fa-clipboard-list fa-1x"></i> <?php echo $halldetail[0][0]; ?></h1>
<p class="lead">You can manage month wise prize list.Prize list consist of per head with food and per head only seating .</p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php " class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container">
<h1>Prize list Setting</h1>
<hr class="mt-2 mb-3 border-white">
<div class="form-group row ">
<div data-daytime="Morning" class="col-4 daytime p-0"style="height: 25vh">
<div class="card-header">
<img class="rounded-circle" src="https://www.incimages.com/uploaded_files/image/970x450/getty_503667408_2000133320009280259_352507.jpg" style="height: 20vh;width: 100%;">
<p align="center" >Morning Prize list</p>
</div>
</div>
<div data-daytime="Afternoon" class=" daytime col-4 p-0"style="height: 25vh">
<div class="card-header">
<img class="rounded-circle" src="https://www.ellieteramoto.com/wordpress/wp-content/uploads/2018/11/the-sun-and-lake-kussharo-hokkaido-japan.jpg" style="height: 20vh;width: 100%">
<p align="center" >Afternoon Prize list</p>
</div>
</div>
<div data-daytime="Evening" class=" daytime col-4 p-0"style="height: 25vh">
<div class="card-header">
<img class="rounded-circle" src="https://www.murals.shop/1777-thickbox_default/starry-sky-half-moon-scenic-cloudscape-wall-mural.jpg" style="height: 20vh;width: 100%">
<p align="center" >Evening Prize list</p>
</div>
</div>
</div>
<div class="border" id="showDaytimes">
</div>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
function showdaytimelist(daytime)
{
var formdata=new FormData();
formdata.append("option","showdaytimelist");
formdata.append("daytime",daytime);
formdata.append("hallid","<?php echo $hallid; ?>");
formdata.append("companyid","<?php echo $companyid;?>");
formdata.append("hallname","<?php echo $halldetail[0][0]; ?>")
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
$("#showDaytimes").hide().html(data).show('slow');
}
});
}
$(".daytime").click(function ()
{
var daytime=$(this).data("daytime");
showdaytimelist(daytime);
}) ;
showdaytimelist("Morning");
$(document).on("change",".changeSeating",function () {
var id=$(this).data("menuid");
var value=$(this).val();
var formdata=new FormData();
formdata.append("option","changeSeating");
formdata.append("packageid",id);
formdata.append("value",value);
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
return false;
}
}
});
}) ;
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
//include ("../connection/connect.php");
//date_default_timezone_set("asia/karachi");
//mysqli_insert_id($connect);
// //$timestamp = date('Y-m-d H:i:s');
// $date = date('Y-m-d');
//$timeSet=date('H:i',time($orderDetail[0][7]));
function queryReceive($sql)
{
global $connect;
$result = mysqli_query($connect, $sql);
if (!$result) {
echo("Error description: " . mysqli_error($connect));
}else{
return mysqli_fetch_all($result);
}
}
// $.ajax({
// url:"customerBookingServer.php",
// method:"POST",
// data:formdatd,
// contentType: false,
// processData: false,
// success:function (data)
// {
// console.log(data);
// }
// });
function querySend($sql)
{
global $connect;
$result = mysqli_query($connect, $sql);
if (!$result) {
echo("Error description: " . mysqli_error($connect));
}
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0;
padding: 0;
}
</style>
</head>
<body>
<p>hellooo header</p>
<script>
//window.history.back();
/*var previous='';
$('.showDetail').click(function ()
{
var formid=$(this).data("formid");
var value=$(this).val();
if((previous!=formid)&& (previous!=''))
{
$("#"+previous).val("Detail");
$("#"+previous).hide('slow');
}
previous=formid;
if(value=="Detail")
{
$(this).val("preview");
$("#"+formid).show('slow');
}
else if(value=="preview")
{
$(this).val("Detail");
$("#"+formid).hide('slow');
}
});
$('.allnumber').map(function () {
var data=$(this).val();
console.log(data);
}).get().join();
*/
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../connection/connect.php");
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once("../../webdesign/header/headerclient.php");
?>
<div class="container" style="margin-top:150px">
<h1 class="font-weight-bold " align="center">System Dish info </h1>
<div class="col-12 card shadow mb-3 p-5">
<h3 align="center"> Dish Type information</h3>
<div class="form-group row font-weight-bold border">
<label class="col-9 col-form-label ">Name Dish type</label>
<label class="col-3 col-form-label ">Detail</label>
</div>
<div class="form-group row border">
<input id="addDishtypeValue" class="col-9 form-control " placeholder="Add new Dish type">
<button id="addDishtype" class="col-3 btn-success col-form-label ">Add +</button>
</div>
<?php
$sql='SELECT dt.id, dt.name,dt.isExpire FROM dish_type as dt';
$dishTypes=queryReceive($sql);
$Display='';
for($i=0;$i<count($dishTypes);$i++)
{
$Display.= '<div class="form-group row border " id="Delele_Dish_Type_'.$dishTypes[$i][0].'">
<input data-dishtypeid="'.$dishTypes[$i][0].'" value="'.$dishTypes[$i][1].'" class="changeDishType col-9 form-control ">
<input data-dishtypeid="'.$dishTypes[$i][0].'" class=" btn Delele_Dish_Type col-3 form-control ';
if($dishTypes[$i][2]=="")
{
$Display.='btn-primary ';
}
else
{
$Display.=' btn-danger ';
}
$Display.=' " value="';
if($dishTypes[$i][2]=="")
{
$Display.='Disable';
}
else
{
$Display.='Enable';
}
$Display.= '"></div>';
}
echo $Display;
?>
</div>
<div class="col-12 card shadow mb-2 p-4 ">
<h3 align="center"> Dish information <a href="/Catering/system/dish/addDish.php" class=" btn-outline-primary btn form-control ">Add dish +</a>
</h3>
<div class="form-group row font-weight-bold border">
<label class="col-4 col-form-label ">Dish Id</label>
<label class="col-5 col-form-label " >Dish Name </label>
<label class="col-3 col-form-label ">Detail</label>
</div>
<?php
$sql='SELECT d.name, d.id, (SELECT dt.name from dish_type as dt WHERE dt.id=d.dish_type_id),(SELECT dt.isExpire from dish_type as dt WHERE dt.id=d.dish_type_id), d.isExpire FROM dish as d WHERE 1 ';
$Dishes=queryReceive($sql);
$display='';
for($i=0;$i<count($Dishes);$i++)
{
$display.= '<div class="form-group row border">
<label class="col-2 col-form-label ">'.$Dishes[$i][1].'</label>
<label class="col-6 col-form-label " > '.$Dishes[$i][0].'</label>
<a href="/Catering/system/dish/EditDish.php?dishid='.$Dishes[$i][1].'" class="col-4 form-control btn ';
if(($Dishes[$i][3]=="")&&($Dishes[$i][4]==""))
{
$display.=" btn-primary ";
}
else
{
$display.=" btn-danger ";
}
$display.='">';
if($Dishes[$i][3]!="")
{
$display.=$Dishes[$i][2]." Diable ";
}
if($Dishes[$i][4]!="")
{
$display.=" Dish Diable ";
}
if(($Dishes[$i][3]=="")&&($Dishes[$i][4]==""))
{
$display.=" Detail ";
}
$display.='</a>
</div>';
}
echo $display;
?>
</div>
</div>
<script>
$(document).ready(function () {
$(document).on("change",".changeDishType",function ()
{
var id=$(this).data("dishtypeid");
var value=$(this).val();
$.ajax({
url:"dishServer.php",
data:{id:id,value:value,option:"changeDishType"},
dataType:"text",
method:"POST",
success:function (data)
{
if(data!="")
{
alert(data);
}
}
});
});
$(document).on("click",".Delele_Dish_Type",function ()
{
var id=$(this).data("dishtypeid");
var value=$(this).val();
$.ajax({
url:"dishServer.php",
data:{value:value,id:id,option:"Delele_Dish_Type"},
dataType:"text",
method:"POST",
success:function (data)
{
if(data!="")
{
alert(data);
}
else
{
location.reload();
}
}
});
});
$("#addDishtype").click(function () {
var value=$("#addDishtypeValue").val();
$.ajax({
url:"dishServer.php",
data:{value:value,option:"addDishtype"},
dataType:"text",
method:"POST",
success:function (data)
{
if(data!="")
{
alert(data);
}
else
{
location.reload();
}
}
});
});
});
</script>
</body>
</html><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include ("../../connection/connect.php");
if(!isset($_SESSION['customer']))
{
header("location:../../customer/CustomerCreate.php");
}
$hallid=$_SESSION['branchtypeid'];
$personid=$_SESSION['customer'];
$userid=$_COOKIE['userid'];
$sql='SELECT c.id, c.name,c.image FROM catering as c WHERE c.company_id=(SELECT h.company_id from hall as h where h.id='.$hallid.') AND (ISNULL(c.expire))';
$cateringids=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
form
{
margin: 5%;
font-weight: bold;
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://cdn.flatworldsolutions.com/featured-images/outsource-outbound-call-center-services.jpg);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 ><i class="fas fa-cart-plus fa-2x"></i>Order Booking </h3>
</div>
</div>
<form class="form container">
<input type="number" hidden name="hallid" value="<?php echo $hallid;?>">
<input type="number" hidden name="personid" value="<?php echo $personid;?>">
<input type="number" hidden name="userid" value="<?php echo $userid;?>">
<div class="form-group row">
<label class="col-form-label">No of Guests</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-users"></i></span>
</div>
<input name="guests" type="number" class="form-control" placeholder="etc 250,300,....persons">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-calendar-alt"></i></span>
</div>
<input id="date" name="date" type="date" class="checkpackage form-control">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Time</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-clock"></i></span>
</div>
<select id="time" name="time" class="checkpackage form-control">
<option value="Morning">Morning</option>
<option value="Afternoon">Afternoon</option>
<option value="Evening">Evening</option>
</select>
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Per Head With</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-utensils"></i></span>
</div>
<select id="perheadwith" name="perheadwith" class="checkpackage form-control">
<option value="0">Only seating</option>
<option value="1">Food + Seating</option>
</select>
</div>
</div>
<?php
if(count($cateringids)>0)
{
$display = '
<div class="form-group row" id="cateringid">
<label class="col-form-label ">Catereing Branch</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-utensils"></i></span>
</div>
<select name="cateringid" class="form-control">
';
for ($i = 0; $i < count($cateringids); $i++) {
$display .= '
<option value="' . $cateringids[$i][0] . '">' . $cateringids[$i][1] . '</option>';
}
$display .= '
</select>
</div>
</div>';
echo $display;
}
?>
<div id="groupofpackages" class="col-12 alert-warning shadow">
</div>
<div id="selectmenu" class="alert-info m-2 form-group row shadow" >
</div>
<div class="form-group row">
<label class="col-form-label">Describe /Comments</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-comments"></i></span>
</div>
<textarea name="describe" class="form-control" placeholder="order comments /describe"></textarea>
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Total amount:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-money-bill-alt"></i></span>
</div>
<input name="totalamount" type="number" class="form-control" placeholder="etc 10000,20000 total amount">
</div>
</div>
<div class="form-group row justify-content-center shadow">
<!--
edit customer 17
-->
<a href="../../customer/customerEdit.php" class=" col-5 btn btn-danger" ><i class="fas fa-arrow-circle-left"></i>Edit customer</a>
<button id="submitform" type="button" class=" col-4 btn btn-success" value="Submit"><i class="fas fa-check "></i>Submit</button>
</div>
</form>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
function barnches()
{
var perheadwith = $("#perheadwith").val();
if(perheadwith==1)
{
$("#cateringid").show();
}
else
{
$("#cateringid").hide();
}
}
$("#perheadwith").change(function ()
{
barnches();
});
barnches();
function checkpackage(date, time, perheadwith) {
if ((date != "") && (time != "") && (perheadwith != "")) {
return 1;
}
return 0;
}
$(".checkpackage").change(function () {
var date = $("#date").val();
var month = new Date(date).getMonth();
var time = $("#time").val();
var perheadwith = $("#perheadwith").val();
if (!checkpackage(date, time, perheadwith)) {
return false;
}
var formdata = new FormData;
formdata.append("date",date);
formdata.append("month", month);
formdata.append("time", time);
formdata.append("perheadwith", perheadwith);
formdata.append("option", "checkpackages1");
formdata.append("hallid",<?php echo $hallid;?>);
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(perheadwith==1)
{
if (data == "")
{
$("#submitform").hide("slow");
$("#groupofpackages").html(data+"<h1 class='text-danger'>No Packages found:so order not submit</h1>");
} else {
$("#groupofpackages").html(data);
$("#submitform").show("slow");
}
}
else
{
$("#groupofpackages").html(data);
$("#submitform").show("slow");
}
}
});
});
$(document).on("click","input[type=radio]",function () {
var packageid=$("input[name='defaultExampleRadios']:checked").val();
if($("#perheadwith").val()!="1")
return false;
var describe=$("#describe"+packageid).val();
var formdata = new FormData;
formdata.append("packageid", packageid);
formdata.append("option", "viewmenu");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
$("#selectmenu").html(data);
$("#selectmenu").append("<h3 align='center' class='col-12'>Menu Description</h3><p class='col-12'>"+describe+"</p>");
}
});
});
$("#submitform").click(function ()
{
var packageid='';
var date = $("#date").val();
var time = $("#time").val();
var perheadwith = $("#perheadwith").val();
if (!checkpackage(date, time, perheadwith))
{
alert("Please select Date,Time and Per Head");
return false;
}
if($(".checkclasshas")[0])
{
packageid=$("input[name='defaultExampleRadios']:checked").val();
if(!packageid)
{
alert("please select Package From Package Detail");
return false;
}
}
var formdata = new FormData($("form")[0]);
formdata.append("packageid", packageid);
formdata.append("option", "createOrderofHall");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!="")
{
alert(data);
}
else
{
window.location.href="../../order/PreviewOrder.php";
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-05
* Time: 13:39
*/
session_start();
include_once ("../connection/connect.php");
if(isset($_POST['option']))
{
if($_POST['option']=="change")
{
if (isset($_SESSION['customer']))
{
$customerId = $_SESSION['customer'];
$column_name = $_POST['columnname'];
$text = $_POST['value'];
$number_table = $_POST['edittype'];
if ($number_table == 1) {
//address table change
$sql = 'UPDATE address as a SET a.' . $column_name . '="' . $text . '" WHERE a.person_id=' . $customerId . ' ';
querySend($sql);
} else if ($number_table == 2) {
//person change table change
$sql = 'UPDATE person as p SET p.' . $column_name . '="' . $text . '" WHERE p.id=' . $customerId . ' ';
querySend($sql);
} else if ($number_table == 3) {
//number table change
$numberId = $_POST['id'];
$sql = 'UPDATE number as n SET n.' . $column_name . '="' . $text . '" WHERE (n.person_id=' . $customerId . ') AND (n.id=' . $numberId . ')';
querySend($sql);
}
}
}
else if($_POST['option']=="deleteNumber")
{
$id=$_POST['id'];
$sql='DELETE FROM number WHERE id='.$id.'';
querySend($sql);
}
else if($_POST['option']=="addNumber")
{
if (isset($_SESSION['customer']))
{
$customerId = $_SESSION['customer'];
$numberText=$_POST['number'];
$sql='INSERT INTO `number`(`number`, `id`, `is_number_active`, `person_id`) VALUES ("'.$numberText.'",NULL,1,"'.$customerId.'")';
querySend($sql);
}
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 01:51
*/
include_once ("../connection/connect.php");
$hallorcater=$_POST['hallorcater'];
$sql='SELECT
DISTINCT
od.id,p.name,p.image,od.destination_date,od.destination_time,od.status_hall,od.status_catering,od.hall_id,od.catering_id,hp.package_name,p.id FROM orderDetail as od INNER JOIN person as p
on (p.id=od.person_id)
left JOIN number as n
on (p.id=n.person_id)
left JOIN hallprice as hp
on (od.hallprice_id=hp.id)
WHERE
';
if(isset($_POST['p_name']))
{
if($_POST['p_name']!='')
$sql.=' (p.name LIKE "%'.$_POST["p_name"].'%") AND ';
}
if(isset($_POST['p_cnic']))
{
if($_POST['p_cnic']!='')
$sql.=' (p.cnic LIKE "%'.$_POST["p_cnic"].'%") AND ';
}
if(isset($_POST['p_id']))
{
if($_POST['p_id']!='')
$sql.=' (p.id ='.$_POST["p_id"].') AND ';
}
if(isset($_POST['n_number']))
{
if($_POST['n_number']!='')
$sql.=' (n.number LIKE "%'.$_POST["n_number"].'%") AND ';
}
if(isset($_POST['od_booking_date']))
{
if($_POST['od_booking_date']!='')
$sql.=' (od.booking_date = "'.$_POST["od_booking_date"].'") AND ';
}
if(isset($_POST['od_destination_date']))
{
if($_POST['od_destination_date']!='')
$sql.=' (od.destination_date ="'.$_POST["od_destination_date"].'") AND ';
}
if(isset($_POST['od_status_catering']))
{
if($_POST['od_status_catering']!='None')
$sql.=' (od.status_catering = "'.$_POST["od_status_catering"].'") AND ';
}
if(isset($_POST['od_status_hall']))
{
if($_POST['od_status_hall']!='None')
$sql.=' (od.status_hall = "'.$_POST["od_status_hall"].'") AND ';
}
$sql.=''.$hallorcater.'
order by
od.destination_date DESC';
$orderdetail=queryReceive($sql);
$display='';
for ($i=0;$i<count($orderdetail);$i++)
{
$display.='
<a href="?action=preview&order='.$orderdetail[$i][0].'&customer='.$orderdetail[$i][10].'" class="col-12 row shadow m-3 newcolor">
<img src="';
if(file_exists('../images/customerimage/'.$orderdetail[$i][2])&&($orderdetail[$i][2]!=""))
{
$display.='../images/customerimage/'.$orderdetail[$i][2];
}
else
{
$display.='https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
$display.='"class="col-3 p-0">
<div class="col-9">
<label class="col-12">Order id:<i class="text-secondary">'.$orderdetail[$i][0].'</i> </label>
<label class="col-12">Name: <i class="text-secondary">'.$orderdetail[$i][1].'</i></label>
<label class="col-12">Date: <i class="text-secondary">'.$orderdetail[$i][3].'</i></label>
</div>
<label class="col-12">Time: <i class="text-secondary">';
if(!empty($hallid))
{
//if order is hall order timing
if ($orderdetail[$i][4] == "09:00:00")
{
$display .= "Morning";
} else if ($orderdetail[$i][4] == "12:00:00") {
$display .= "Afternoon";
} else
{
$display .= "18:00:00";
}
}
else
{
//catering order
$display.=$orderdetail[$i][4];
}
$display.='</i></label>';
if($orderdetail[$i][7]!="")
{
//if order is hall
$display .= '<label class="col-12">Per Head:<i class="text-secondary">';
if ($orderdetail[$i][9] != "")
{
//hall is booked wth food+seaating
$display.=$orderdetail[$i][9].' Food+Seating';
} else
{
//hall is book only seating
$display.='Only Seating';
}
$display.='</i> </label>';
}
if(($orderdetail[$i][6]!="")&&($orderdetail[$i][8]!=""))
{
//catering status
$display.='
<label class="col-12">Catering Status:<i class="text-secondary">'.$orderdetail[$i][6].'</i> </label>';
}
if(($orderdetail[$i][5]!="")&&($orderdetail[$i][7]!=""))
{
//hall status
$display.='
<label class="col-12">Hall Status:<i class="text-secondary">'.$orderdetail[$i][5].'</i> </label>';
}
$display.='</a>';
}
echo $display;
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-07
* Time: 11:31
*/
$orderId=$_GET['order'];
include_once ("../connection/connect.php");
session_start();
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container" style="margin-top:180px">
<h1 align="center"> Selected Dishes / items Detail</h1>
<div class="col-12 border">
<div class=" row">
<label class="font-weight-bold border-right col-1">No</label>
<label class="font-weight-bold border-right col-3">dish name</label>
<label class=" font-weight-bold border-right col-2">quantity</label>
<label class=" font-weight-bold border-right col-2">each price</label>
<label class="font-weight-bold border-right col-2">total</label>
<label class=" font-weight-bold col-2">Detail</label>
</div>
<?php
$sql='SELECT dd.id,d.name,dd.quantity,dd.price,d.id FROM dish_detail as dd INNER JOIN
dish as d
on d.id=dd.dish_id
where
(dd.orderTable_id='.$orderId.') AND ISNULL(dd.expire_date)';
$totalAmount=0;
$dishesDetail=queryReceive($sql);
for($i=0;$i<count($dishesDetail);$i++)
{
$totalAmount+=(int)$dishesDetail[$i][2]*(int)$dishesDetail[$i][3];
echo '<div class=" row border ">
<label class="border-right col-form-label col-1">'.$i.'</label>
<label class="border-right col-form-label col-3">'.$dishesDetail[$i][1].'</label>
<label class=" border-right col-form-label col-2">'.$dishesDetail[$i][2].'</label>
<label class="border-right col-form-label col-2">'.$dishesDetail[$i][3].'</label>
<label class=" border-right col-form-label col-2">'.(int)$dishesDetail[$i][2]*(int)$dishesDetail[$i][3].'</label>
<a href="/dish/dishPreview.php?dishId='.$dishesDetail[$i][4].'&dishDetailId='.$dishesDetail[$i][0].'&order='.$_GET['order'].'&option=Allselected" class="detailBtn form-control btn-primary col-2">Detail</a>
</div>';
}
?>
</div>
<div class="col-12 p-3">
<div class="col-12 row">
<label class=" border col-form-label col-8"> dishes total amount</label>
<label class=" border col-form-label col-4">
<?php
echo $totalAmount;
$sql='SELECT `total_amount`,`extre_charges` FROM `orderTable` WHERE id='.$orderId.'';
$orderDetail=queryReceive($sql);
?>
</label>
</div>
<div class="col-12 row">
<label class=" border col-form-label col-8"> extra charges</label>
<label class=" border col-form-label col-4">
<?php
echo $orderDetail[0][1];
?>
</label>
</div>
<div class="col-12 row">
<label class=" border col-form-label col-8"> charges with amount</label>
<label class=" border col-form-label col-4">
<?php
echo $orderDetail[0][1]+$totalAmount;
?>
</label>
</div>
<div class="col-12 row">
<label class=" border col-form-label col-8"> your demand amount</label>
<label class=" border col-form-label col-4">
<?php
echo $orderDetail[0][0];
?>
</label>
</div>
</div>
<div class="col-12 row ">
<a href="/order/PreviewOrder.php?order=<?php echo $_GET['order'];?>" class="form-control btn-info col-5">Order Preview</a>
<a href="/dish/dishDisplay.php?order=<?php echo $_GET['order'];?>" class="form-control btn-success col-5">dish Add +</a>
</div>
</div>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../connection/connect.php");
if(!isset($_COOKIE['companyid']))
{
header("location:../../user/userLogin.php");
}
if(!isset($_GET['catering']))
{
header("location:../companyRegister/companyEdit.php");
}
$encoded=$_GET['catering'];
$id=base64url_decode($encoded);
if((!is_numeric($id))||$id=="")
{
header("location:../companyRegister/companyEdit.php");
}
$cateringid=$id;
if(isset($_GET['action']))
{
if($_GET['action']=="expire")
{
$date=date('Y-m-d H:i:s');
$sql='UPDATE `catering` SET `expire`="'.$date.'" WHERE id='.$cateringid.'';
}
else
{
$sql='UPDATE `catering` SET `expire`=NULL WHERE id='.$cateringid.'';
}
querySend($sql);
header("location:cateringEDIT.php?catering=".$encoded."");
}
$sql='SELECT `name`, `expire`, `image`, `location_id` FROM `catering` WHERE id='.$cateringid.'';
$cateringdetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow text-center" style="background-image: url(<?php
if((file_exists('../../images/catering/'.$cateringdetail[0][2])) &&($cateringdetail[0][2]!=""))
{
echo "'../../images/catering/".$cateringdetail[0][2]."'";
}
else
{
echo "https://www.liberaldictionary.com/wp-content/uploads/2019/02/cater-4956.jpg";
}
?>
);background-size:100% 100%;background-repeat: no-repeat">
<div class="card-body " style="opacity: 0.7 ;background: white;">
<h1 class="display-5 text-center"><i class="fas fa-cogs fa-3x"></i> <?php echo $cateringdetail[0][0];?></h1>
<p class="lead">Edit Catering infomation name ,location,pictures... </p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php" class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container" >
<form id="formcatering">
<input type="number" hidden name="cateringid" value="<?php echo $cateringid; ?>">
<input type="text" hidden name="previousimage" value="<?php echo $cateringdetail[0][2]; ?>">
<div class="form-group row">
<label class="col-form-label ">Catering Branch Name:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-utensils"></i></span>
</div>
<input name="cateringname" class="form-control" type="text" value="<?php echo $cateringdetail[0][0]; ?>">
</div>
</div>
<div class="form-group row">
<label class="col-form-label ">Catering Branch Image:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input name="image" class="form-control" type="file">
</div>
</div>
<div class="form-group row">
<h3 align="center"> <i class="fas fa-map-marker-alt"></i>Address(optional)</h3>
</div>
<div class="form-group row col-12 mb-5">
<?php
if($cateringdetail[0][1]=="")
{
echo '<a href="?action=expire&catering='.$encoded.'" class="btn btn-danger col-6">Expire</a>';
}
else
{
echo '<a href="?action=active&catering='.$encoded.'" class="btn btn-warning col-6">Active</a>';
}
?>
<button id="submiteditcatering" type="button" class="rounded mx-auto d-block btn btn-primary col-5 " value="Submit"><i class="fas fa-check "></i>Submit</button>
</div>
</form>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
$("#submiteditcatering").click(function () {
var formdata = new FormData($("#formcatering")[0]);
formdata.append("option", "cateringedit");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if (data != '')
{
alert(data);
return false;
} else
{
window.history.back();
}
}
});
});
});
</script>
</body>
</html><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-05
* Time: 13:39
*/
include_once ("../connection/connect.php");
if(isset($_POST['option']))
{
if($_POST['option']=="change")
{
$customerId = $_POST['customerid'];
$column_name = $_POST['columnname'];
$text = chechIsEmpty($_POST['value']);
$number_table = $_POST['edittype'];
if ($number_table == 1) {
//address table change
$sql = 'UPDATE address as a SET a.' . $column_name . '="' . $text . '" WHERE a.person_id=' . $customerId . ' ';
querySend($sql);
} else if ($number_table == 2) {
//person change table change
$sql = 'UPDATE person as p SET p.' . $column_name . '="' . $text . '" WHERE p.id=' . $customerId . ' ';
querySend($sql);
} else if ($number_table == 3) {
//number table change
$numberId = $_POST['id'];
$sql = 'UPDATE number as n SET n.' . $column_name . '="' . $text . '" WHERE (n.person_id=' . $customerId . ') AND (n.id=' . $numberId . ')';
querySend($sql);
}
}
else if($_POST['option']=="deleteNumber")
{
$id=$_POST['id'];
$sql='DELETE FROM number WHERE id='.$id.'';
querySend($sql);
}
else if($_POST['option']=="addNumber")
{
$customerId = $_POST['customerid'];
$numberText=$_POST['number'];
$sql='INSERT INTO `number`(`number`, `id`, `is_number_active`, `person_id`) VALUES ("'.$numberText.'",NULL,1,"'.$customerId.'")';
querySend($sql);
}
else if($_POST['option']=="changeImage")
{
$customerid=$_POST['customerid'];
$previouspath=$_POST['image'];
$image="../images/customerimage/".$_FILES['image']['name'];
$resultimage=ImageUploaded($_FILES,$image);//$dishimage is destination file location;
if($resultimage!="")
{
print_r($resultimage);
exit();
}
$image=$_FILES['image']['name'];
$sql='UPDATE person as p SET p.image="'.$image.'" WHERE p.id='.$customerid.';';
querySend($sql);
if (file_exists($previouspath))
{
$deleted = unlink($previouspath);
}
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2020-01-05
* Time: 16:38
*/
setcookie('userid',"" , time() + (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("isOwner","",time() + (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("username","",time() + (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("companyid","",time() +(86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("userimage","",time() + (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
<file_sep><?php
include_once ('../../connection/connect.php');
if(!isset($_GET['hall']))
{
header("location:../companyRegister/companyEdit.php");
}
$encoded=$_GET['hall'];
$id=base64url_decode($encoded);
if((!is_numeric($id))||$id=="")
{
header("location:../companyRegister/companyEdit.php");
}
$hallid='';
$companyid='';
$hallid=$id;
$companyid=$_COOKIE['companyid'];
$sql='SELECT `name`, `max_guests`, `noOfPartitions`, `ownParking`, `expire`, `image`, `hallType`, `location_id` FROM `hall` WHERE id='.$hallid.'';
$halldetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron jumbotron-fluid text-center" style="background-image: url(<?php
if((file_exists('../../images/hall/'.$halldetail[0][5]))&&($halldetail[0][5]!=""))
{
echo "'../../images/hall/".$halldetail[0][5]."'";
}
else
{
echo "https://www.pakvenues.com/system/halls/cover_images/000/000/048/original/Umar_Marriage_Hall_lahore.jpg?1566758537";
}
?>);background-repeat: no-repeat ;background-size: 100% 100%">
<div class="container" style="background-color: white;opacity: 0.7">
<h1 class="display-4"><i class="fas fa-images fa-1x"></i> <?php echo $halldetail[0][0]; ?></h1>
<p class="lead">View and upload picture of hall </p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php " class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container">
<h1 class="font-weight-light text-lg-left mt-4 mb-3">Gallery</h1>
<form action="" method="POST" enctype="multipart/form-data" class="form-inline">
<input type="file" name="userfile[]" value="" multiple="" class="col-8 btn btn-light">
<input type="submit" name="submit" value="Upload" class="btn btn-success col-4">
</form>
<?php
if(isset($_FILES['userfile']))
{
$file_array=reArray($_FILES['userfile']);
$Distination='';
for ($i=0;$i<count($file_array);$i++)
{
$Distination= '../../images/hall/'.$file_array[$i]['name'];
$error=MutipleUploadFile($file_array[$i],$Distination);
if(count($error)>0)
{
echo '<h4 class="badge-danger">'.$file_array[$i]['name'].'.'.$error[0].'</h4>';
}
else
{
$sql='INSERT INTO `images`(`id`, `image`, `expire`, `catering_id`, `hall_id`) VALUES (NULL,"'.$Distination.'",NULL,NULL,'.$hallid.')';
querySend($sql);
}
}
unset($_FILES['userfile']);
}
?>
<hr class="mt-3 mb-5 border-white">
<div class="row text-center text-lg-left">
<?php
$sql='SELECT `id`, `image` FROM `images` WHERE hall_id='.$hallid.'' ;
echo showGallery($sql);
?>
</div>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
$orderId=$_SESSION['order'];
$sql='SELECT `id`, `total_amount`, `describe`, `total_person`, `status_catering`, `destination_date`, `booking_date`, `destination_time`, `address_id`, `person_id` FROM `orderDetail` WHERE id='.$orderId.'';
$orderDetail=queryReceive($sql);
$addressId=$orderDetail[0][8];
$sql='SELECT `id`, `address_city`, `address_town`, `address_street_no`, `address_house_no`, `person_id` FROM `address` WHERE id='.$addressId.'';
$addresDetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://cdn.flatworldsolutions.com/featured-images/outsource-outbound-call-center-services.jpg);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 ><i class="fas fa-cart-plus fa-2x"></i>Order Edit </h3>
</div>
</div>
<div class="container">
<form class="card-body">
<?php
echo '<input id="orderid" type="number" hidden value="'.$orderId.'">';
?>
<div class="form-group row">
<label for="persons" class="col-form-label"> no of guests</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-users"></i></span>
</div>
<input data-column="total_person" type="number" name="persons" id="persons" class="order form-control" value="<?php echo $orderDetail[0][3];?>">
</div>
</div>
<div class="form-group row">
<label for="time" class="col-form-label">delivery Time</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-clock"></i></span>
</div>
<input data-column="destination_time" type="time" name="time" id="time" class="order form-control" value="<?php echo $orderDetail[0][7];?>">
</div>
</div>
<div class="form-group row">
<label for="date" class="col-form-label">delivery Date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-calendar-alt"></i></span>
</div>
<input data-column="destination_date" type="date" name="date" id="date" class="order change form-control" value="<?php echo $orderDetail[0][5];?>">
</div>
</div>
<div class="form-group row">
<label for="describe" class="col-form-label">describe order </label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-comments"></i></span>
</div>
<textarea data-column="describe" class="order change form-control form-control" ><?php echo $orderDetail[0][2];?></textarea>
</div>
</div>
<div class="form-group row">
<label for="orderStatus" class="col-form-label">Order Status </label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-eye"></i></span>
</div>
<select data-column="status_catering" class="order form-control form-control">
<?php
$OrderStatus=array("Running","Cancel","Delieved","Clear");
echo '<option value='.$orderDetail[0][4].'>'.$orderDetail[0][4].'</option>';
for($i=0;$i<count($OrderStatus);$i++)
{
if($orderDetail[0][4]!=$OrderStatus[$i])
{
echo '<option value='.$OrderStatus[$i].'>'.$OrderStatus[$i].'</option>';
}
}
?>
</select>
</div>
</div>
<h3 align="center"> <i class="fas fa-map-marker-alt mr-2"></i>Delivery Address(optional)</h3>
<div class="form-group row">
<label for="area" class="col-form-label">area / block </label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-city"></i></span>
</div>
<input data-column="address_town" type="text" data-addressid=<?php echo $addressId;?> name="area" id="area" class=" address form-control" value="<?php echo $addresDetail[0][2];?>">
</div>
</div>
<div class="form-group row">
<label for="streetNO" class="col-form-label">Street no #</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-road"></i></span>
</div>
<input data-column="address_street_no" type="number" data-addressid=<?php echo $addressId;?> name="streetno" id="streetNO" class=" address form-control" value=<?php echo $addresDetail[0][3];?>>
</div>
</div>
<div class="form-group row">
<label for="houseno" class="col-form-label">house no# </label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-street-view"></i></span>
</div>
<input data-column="address_house_no" type="number" data-addressid=<?php echo $addressId;?> name="houseno" id="houseno" class=" address form-control" value=<?php echo $addresDetail[0][4];?>>
</div>
</div>
<div class="form-group row">
<label class="form-check-label" for="total_amount">total amount</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-money-bill-alt"></i></span>
</div>
<input data-column="total_amount" type="number" class="order form-control" id="total_amount" value=<?php echo $orderDetail[0][1];?>>
</div>
</div>
<div class="form-group row">
<label class="form-check-label" for="booking_date">order booking date</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-business-time"></i></span>
</div>
<input type="date" readonly class="form-control" id="booking_date" value="<?php echo $orderDetail[0][6];?>">
</div>
</div>
<div class="form-group row justify-content-center">
<?php
/* if(isset($_GET['option']))
{
if($_GET['option']=="dishDisplay")
{
echo '
<a href="/Catering/customer/customerEdit.php?order='.$_GET['order'].'&customer='.$_GET['customer'].'&option=customerAndOrderalreadyHave" id="cancel" class="form-control col-6 btn btn-danger"> <i class="fas fa-arrow-left"></i>Customer Edit</a>
<a href="/Catering/dish/dishDisplay.php?order='.$_GET['order'].'" id="submit" class="form-control col-6 btn-success"><i class="fas fa-check "></i> Display Dish</a>';
}
else if($_GET['option']=="customerEdit")
{
echo '
<a href="/Catering/customer/customerEdit.php?order='.$_GET['order'].'&customer='.$_GET['customer'].'&option=customerAndOrderalreadyHave" id="cancel" class="form-control col-6 btn btn-danger"><i class="fas fa-arrow-left"></i> Customer Edit</a>
<a href="/Catering/dish/dishDisplay.php?order='.$_GET['order'].'&option=orderEdit" id="submit" class="form-control col-6 btn-success"><i class="fas fa-check "></i> Display Dish</a>';
}
else if($_GET['option']=="PreviewOrder")
{
echo '<input type="button" id="btnbackhistory" class="col-6 form-control btn btn-outline-primary" value="Done">';
}
}*/
//14,11
if(isset($_GET['action']))
{
echo '
<a href="../order/PreviewOrder.php" class="m-auto col-6 form-control btn btn-danger"><i class="fas fa-check "></i> Done</a>';
}
else
{
echo '
<a href="/Catering/customer/customerEdit.php" id="cancel" class="form-control col-6 btn btn-danger"> <i class="fas fa-arrow-left"></i>Customer Edit</a>
<a href="/Catering/dish/dishDisplay.php" id="submit" class="form-control col-6 btn-success"><i class="fas fa-check "></i> Display Dish</a>';
}
?>
</div>
</form>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
var orderid= $("#orderid").val();
$(document).on("change",'.order',function () {
var columnName=$(this).data("column");
var text=$(this).val();
$.ajax({
url: "orderEditServer.php",
data:{column_name:columnName,value:text,option:'orderChange',orderid:orderid},
dataType:"text",
method:"POST",
success:function (data) {
if(data!='')
{
alert(data);
}
}
});
});
$(document).on("change",'.address',function () {
var columnName=$(this).data("column");
var addressId=$(this).data("addressid");
var text=$(this).val();
$.ajax({
url: "orderEditServer.php",
data:{column_name:columnName,value:text,option:'addressChange',addressId:addressId},
dataType:"text",
method:"POST",
success:function (data) {
if(data!='')
{
alert(data);
}
}
});
});
$("#btnbackhistory").click(function () {
window.history.back();
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 01:51
*/
include_once ("../connection/connect.php");
$hallorcater=$_POST['hallorcater'];
$sql="SELECT DISTINCT od.id,p.name, (SELECT sum(py.amount) FROM payment as py WHERE (py.IsReturn=0)AND(py.orderDetail_id=od.id)) ,od.total_amount,od.total_amount, (SELECT SUM(dd.price*dd.quantity) FROM dish_detail as dd WHERE dd.orderDetail_id=od.id),od.status_catering,od.status_hall,od.person_id FROM orderDetail as od LEFT join payment as py on (od.id=py.orderDetail_id) left JOIN person as p
on (p.id=od.person_id) LEFT join number as n
on (p.id=n.person_id) where ";
if(isset($_POST['p_name']))
{
if($_POST['p_name']!='')
$sql.=' (p.name LIKE "%'.$_POST["p_name"].'%") AND ';
}
if(isset($_POST['p_cnic']))
{
if($_POST['p_cnic']!='')
$sql.=' (p.cnic LIKE "%'.$_POST["p_cnic"].'%") AND ';
}
if(isset($_POST['p_id']))
{
if($_POST['p_id']!='')
$sql.=' (p.id ='.$_POST["p_id"].') AND ';
}
if(isset($_POST['n_number']))
{
if($_POST['n_number']!='')
$sql.=' (n.number LIKE "%'.$_POST["n_number"].'%") AND ';
}
if(isset($_POST['od_booking_date']))
{
if($_POST['od_booking_date']!='')
$sql.=' (od.booking_date = "'.$_POST["od_booking_date"].'") AND ';
}
if(isset($_POST['od_destination_date']))
{
if($_POST['od_destination_date']!='')
$sql.=' (od.destination_date ="'.$_POST["od_destination_date"].'") AND ';
}
if(isset($_POST['od_status_catering']))
{
if($_POST['od_status_catering']!='None')
$sql.=' (od.status_catering = "'.$_POST["od_status_catering"].'") AND ';
}
if(isset($_POST['od_status_hall']))
{
if($_POST['od_status_hall']!='None')
$sql.=' (od.status_hall = "'.$_POST["od_status_hall"].'") AND ';
}
$sql.=''.$hallorcater.'
order by
od.destination_date DESC';
echo showRemainings($sql);
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-07
* Time: 11:31
*/
include_once ("../connection/connect.php");
if(!isset($_SESSION['order']))
{
header("location:../user/userDisplay.php");
}
if(isset($_GET['action']))
{
$_SESSION['tempid']=$_GET['action'];
header("location:dishPreview.php");
}
$orderId=$_SESSION['order'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="../webdesign/css/loader.css">
<style>
</style>
</head>
<body class="text-white">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://qph.fs.quoracdn.net/main-qimg-b1822af85b86aabaa253ad7948880cb7);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 class="text-dark"><i class="fas fa-file-word fa-3x mr-2 "></i>BILL DETAIL</h3>
</div>
</div>
<div class="container">
<div class="row justify-content-center col-12" style="margin-top: -60px">
<div class="card text-center card-header">
<img src="
<?php
$sql="SELECT DISTINCT ot.id, (SELECT p.name FROM person as p WHERE p.id=ot.person_id), (SELECT sum(py.amount) FROM payment as py WHERE (py.IsReturn=0)AND(py.orderDetail_id=ot.id)) ,ot.id,ot.total_amount, (SELECT SUM(dd.price*dd.quantity) FROM dish_detail as dd WHERE dd.orderDetail_id=ot.id),(SELECT p.image FROM person as p WHERE p.id=ot.person_id) FROM orderDetail as ot LEFT join payment as py on ot.id=py.orderDetail_id WHERE ot.id=".$orderId."";
$details=queryReceive($sql);
if($details[0][6]=="")
{
echo 'https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
else
{
echo $details[0][6];
}
?> " style="height: 20vh;" class="figure-img rounded-circle" alt="image is not set">
<h5 ><?php
echo $details[0][1];
?></h5>
<label >Order ID:<?php
echo $details[0][0];
?></label>
</div>
</div>
<?php
echo '
<div class="col-12 shadow card-header mb-3 border">
<div class="form-group row">
<label class="col-6 form-check-label"> received amount</label>
<label class="col-6 form-check-label">'.(int)$details[0][2].' </label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label"> System Amount</label>
<label class="col-6 form-check-label"> '.(int)$details[0][5].'</label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label"> remaining system amount</label>
<label class="col-6 form-check-label">'.(int) ($details[0][5]-$details[0][2]).' </label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label"> your demanded amount</label>
<label class="col-6 form-check-label">'.(int) $details[0][4].' </label>
</div>
<div class="form-group row">
<label class="col-6 form-check-label">remaining demand amount </label>
<label class="col-6 form-check-label"> '.(int) ($details[0][4]-$details[0][2]).'</label>
</div>
</div>
';
?>
<div style="overflow:auto;width:auto" >
<table class="table table-striped table-dark">
<thead>
<tr>
<th scope="col">#</th>
<th scope="col"><h1 class="fas fa-concierge-bell"></h1><br> DishName</th>
<th scope="col"><h1 class="fas fa-hashtag "></h1><br>Quantity</th>
<th scope="col"><h1 class="far fa-money-bill-alt"></h1><br>Each price</th>
<th scope="col"><h1 class="fas fa-list-alt"></h1><br>Total price</th>
</tr>
</thead>
<tbody>
<?php
$sql='SELECT dd.id,d.name,dd.quantity,dd.price,d.id FROM dish_detail as dd INNER JOIN
dish as d
on d.id=dd.dish_id
where
(dd.orderDetail_id='.$orderId.') AND ISNULL(dd.expire_date)';
$totalAmount=0;
$dishesDetail=queryReceive($sql);
for($i=0;$i<count($dishesDetail);$i++)
{
$totalAmount+=(int)$dishesDetail[$i][2]*(int)$dishesDetail[$i][3];
echo '
<tr class="dishdetail" data-id="'.$dishesDetail[$i][0].'">
<th scope="row">'.($i+1).'</th>
<td>'.$dishesDetail[$i][1].'</td>
<td>'.$dishesDetail[$i][2].'</td>
<td>'.$dishesDetail[$i][3].'</td>
<td>'.(int)$dishesDetail[$i][2]*(int)$dishesDetail[$i][3].'</td>
</tr>
';
}
?>
</tbody>
</table>
</div>
<div class="col-12 row justify-content-center ">
<a href="dishDisplay.php" class="form-control btn-success col-6"><i class="fas fa-concierge-bell"></i>dish Add +</a>
<a class="nav-link btn btn-warning col-6 form-control" href="../order/PreviewOrder.php"><i class="fas fa-shopping-cart"></i> Order Preview</a>
</div>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$(".dishdetail").click(function ()
{
var id=$(this).data("id");
window.location.href="?action="+id;
});
});
</script>
</body>
</html>
<file_sep>
<?php
//../cateringBranches/cateringEDIT.php?
//../../system/user/userEdit.php?
include_once ("../../connection/connect.php");
if(!isset($_COOKIE['companyid']))
{
header("location:../../user/userLogin.php");
}
if(isset($_GET['action']))
{
$_SESSION['tempid']=$_GET['id'];
if($_GET['action']=="user")
{
//user
header("location:../../system/user/userEdit.php");
}
else if($_GET['action']=="hall")
{
//hall
header("location:../hallBranches/daytimeAll.php");
}
else
{
//catering
header("location:../cateringBranches/cateringEDIT.php");
}
}
$companyid=$_COOKIE['companyid'];
$sql='SELECT `id`, `name`, `expire`, `user_id` FROM `company` WHERE id='.$companyid.'';
$companydetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<style>
#hallbranches
{
width: 100%;/*
height: 50vh;
overflow: auto;*/
background-size: 100% 100%;
margin: auto;
}
#cateringbranches
{
width: 100%;
/*height: 50vh;
overflow: auto;*/
background-size: 100% 100%;
margin: auto;
}
#userbranches
{
width: 100%;
/*height: 50vh;
overflow: auto;*/
background-size: 100% 100%;
margin: auto;
}
</style>
</head>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow " style="background-image: url(https://i2.wp.com/findlawyer.com.ng/wp-content/uploads/2018/05/Pros-and-Cons-of-Working-at-Large-Companies.jpg?resize=1024%2C512&ssl=1);background-size:100% 115%;background-repeat: no-repeat;">
<div class="card-body text-center" style="opacity: 0.7 ;background: white;">
<h1 class="display-5 "><i class="fas fa-city mr-2"></i><?php echo $companydetail[0][1];?><br>Edit your company</h1>
<p>setting you company of hall branches,catering branches ,user informations ,packages edit</p>
<h1 class="text-center"> <a href="../companyRegister/companydisplay.php" class="col-6 btn btn-warning "> <i class="fas fa-city mr-2"></i>My Company</a></h1>
</div>
</div>
<div class="container">
<!--USERS-->
<div class="col-12 row mt-5">
<h2 align="center" class="col-7"> <i class="fas fa-user mr-1"></i> Users</h2>
<a href="../../system/user/usercreate.php" class="btn btn-success col-5"><i class="fas fa-user-plus"></i> Add User</a>
</div>
<hr class="border border-white">
<div class="form-group row shadow m-auto newcolor" id="userbranches">
<?php
$sql='SELECT u.id, u.username, u.isExpire,(SELECT p.image FROM person as p WHERE p.id=u.person_id) FROM user as u WHERE u.company_id='.$companyid.'';
$users=queryReceive($sql);
$display='';
for($i=0;$i<count($users);$i++)
{
$display.='
<a href="?action=user&id='.$users[$i][0].'" class="col-sm-12 col-md-4 col-xl-3 m-2">
<div class="card col-12 rounded-circle shadow" style="height: 25vh" >
<img class="card-img-top col-12 rounded-circle" src="';
if(file_exists($users[$i][3])&&($users[$i][3]!=""))
{
$display.=$users[$i][3];
}
else
{
$display.='https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
$display.='" alt="Card image" >
</div>
<h4 align="center" ><i class="fas fa-user mr-1"></i> '.$users[$i][1].'</h4>';
if($users[$i][2]!="")
{
$display.='
<i>Expire</i>';
}
$display.='</a>';
}
echo $display;
?>
</div>
<!--Hall Branches-->
<div class="col-12 mt-5 row">
<h2 align="center" class=" col-6"> <i class="fas fa-place-of-worship mr-2"></i> Halls</h2>
<a href="../hallBranches/hallRegister.php" class="btn btn-success col-6"><i class="fas fa-plus"></i><i class="fas fa-place-of-worship mr-2"></i>Add Hall</a>
</div>
<hr class="border border-white">
<div class="form-group row shadow newcolor " id="hallbranches">
<?php
$sql='SELECT `id`, `name`, `expire`, `image` FROM `hall` WHERE company_id='.$companyid.'';
$halldetails=queryReceive($sql);
$display='';
for($i=0;$i<count($halldetails);$i++)
{
$display.='
<a href="?action=hall&id='.$halldetails[$i][0].'" class="col-sm-12 col-md-4 col-xl-3 m-2">
<div class="card col-12 rounded-circle shadow" style="height: 25vh" >
<img class="card-img-top col-12 rounded-circle" src="';
if(file_exists('../'.$halldetails[$i][3])&&($halldetails[$i][3]!=''))
{
$display.='../'.$halldetails[$i][3];
}
else
{
$display.='data:image/jpeg;base64,/9j/4AAQSkZJRgABAQAAAQABAAD/2wCEAAkGBxMTEhUTExQWFhUXGRobGBgYGB4bGBsbGhoeGB0dGBoaHygiGB8mGxgaIjEhJSkrLi4vGiAzODMtNygtLisBCgoKDg0OGhAQGi0lHSUtLS0tLS0tLS0tLS0tLS0tLS0tLS0rLS0tLS0tLS0tLS0tLS0tLS0tLS0tLSstLS0tLf/AABEIAMUBAAMBIgACEQEDEQH/xAAcAAACAgMBAQAAAAAAAAAAAAAFBgMEAQIHAAj/xABQEAABAgMFBAcEBQcJBgcBAAABAhEAAyEEEjFBUQUGYXETIoGRobHwBxQywSNC0eHxFSRDUmJysjM0U3OCg6LC0hYl<KEY>';
}
$display.='" alt="Card image" >
</div>
<h4 align="center" ><i class="fas fa-place-of-worship mr-1"></i>'.$halldetails[$i][1].'</h4>';
if($halldetails[$i][2]!="")
{
$display.='
<i>Expire</i>';
}
$display.='</a>';
}
echo $display;
?>
</div>
<!--Catering Branches-->
<div class="col-12 mt-5 row">
<h2 align="center" class="col-7"> <i class="fas fa-utensils"></i> Caterings</h2>
<a href="../cateringBranches/catering.php" class="btn btn-success col-5"><i class="fas fa-plus"></i> <i class="fas fa-utensils"></i> Add Catering</a>
</div>
<hr class="border border-white">
<div class="form-group row shadow newcolor" id="cateringbranches">
<?php
$sql='SELECT `id`, `name`, `expire`, `image` FROM `catering` WHERE company_id='.$companyid.'';
$cateringdetails=queryReceive($sql);
$display='';
for($i=0;$i<count($cateringdetails);$i++)
{
$display.='
<a href="?action=catering&id='.$cateringdetails[$i][0].'" class="col-sm-12 col-md-4 col-xl-3 m-2">
<div class="card col-12 rounded-circle shadow" style="height: 25vh" >
<img class="card-img-top col-12 rounded-circle" src="';
if(file_exists('../'.$cateringdetails[$i][3])&&($cateringdetails[$i][3]!=''))
{
$display.='../'.$cateringdetails[$i][3];
}
else
{
$display.='data:image/jpeg;base64,/9j/4AAQSkZJRgABAQAAAQABAAD/2wCE<KEY>QEREBERAREQEREBERAREQ<KEY>//<KEY>IiAiIgIiICIiAiIgIiICIiAiIgIiICIiAiIgIiICIiAiIgIiICIiAiIgIiICIiAiIgIiICIiD//Z';
}
$display.='" alt="Card image" >
</div>
<h4 align="center"><i class="fas fa-utensils mr-1"></i>'.$cateringdetails[$i][1].'</h4>';
if($cateringdetails[$i][2]!="")
{
$display.='
<i>Expire</i>';
}
$display.='</a>';
}
echo $display;
?>
</div>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-15
* Time: 11:41
*/
include_once ("connection/connect.php");
if((isset($_COOKIE['companyid']))&&(!isset($_GET['action'])))
{
header("location:company/companyRegister/companydisplay.php");
}
include_once ("connection/indexEdit.php");
?>
<!DOCTYPE html>
<head>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<meta http-equiv="x-ua-compatible" content="ie=edge">
<script src="jquery-3.3.1.js"></script>
<link rel="stylesheet" type="text/css" href="bootstrap.min.css">
<script type="text/javascript" src="bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="https://cdnjs.cloudflare.com/ajax/libs/font-awesome/4.7.0/css/font-awesome.min.css">
<link href="https://fonts.googleapis.com/icon?family=Material+Icons" rel="stylesheet">
<link rel="stylesheet" href="webdesign/css/complete.css">
<link rel="stylesheet" href="webdesign/css/loader.css">
<style>
.carousel-item img
{
margin: 0;
height: 60vh;
}
.carousel-caption
{
background-color: rgba(253, 248, 239, 0.6);
font-weight: bold;
color: rgba(0, 0, 0, 1);
}
.checked {
color: orange;
}
.pictures {
position: relative;
text-align: center;
color: white;
}
.top-right {
position: absolute;
top: 8px;
right: 16px;
}
</style>
</head>
<body>
<?php
include_once ("webdesign/header/header.php");
?>
<div class="bd-example">
<div id="carouselExampleCaptions" class="carousel slide" data-ride="carousel">
<ol class="carousel-indicators">
<li data-target="#carouselExampleCaptions" data-slide-to="0" class="active"></li>
<li data-target="#carouselExampleCaptions" data-slide-to="1" class="active"></li>
<li data-target="#carouselExampleCaptions" data-slide-to="2" class="active"></li>
</ol>
<div class="carousel-inner">
<div class="carousel-item active">
<img src="style1.jpg" class="d-block w-100" alt="...">
<div class="carousel-caption ">
<h5 class="display-4">Hall Booking</h5>
<p>book your nearest Hall,Marquee and Dera and get 10% discount</p>
</div>
</div>
<div class="carousel-item ">
<img src="dolar.jpeg" class="d-block w-100" alt="...">
<div class="carousel-caption ">
<h5 class="display-4">Free Company Register</h5>
<p>Register hall and catering company and get free software</p>
</div>
</div>
<div class="carousel-item ">
<img src="https://indiebookbutler.com/wp-content/uploads/2015/08/Free.jpg" class="d-block w-100" alt="...">
<div class="carousel-caption ">
<div class="col-12 p-0 m-0">
<!-- Links -->
<h4 class="text-uppercase font-weight-bold">Software Features</h4>
<hr class="deep-purple accent-2 mb-4 mt-0 d-inline-block mx-auto" style="width: 60px;">
<p>
<a href="company/companyRegister/companyRegister.php" class="text-dark">Marquee Management software</a>
</p>
<p>
<a href="company/companyRegister/companyRegister.php" class="text-dark">Hall Management software</a>
</p>
<p>
<a href="company/companyRegister/companyRegister.php" class="text-dark">Catering Management software</a>
</p>
<p>
<a href="company/companyRegister/companyRegister.php" class="text-dark">Dera / Open area Management software</a>
</p>
</div>
</div>
</div>
</div>
<a class="carousel-control-prev" href="#carouselExampleCaptions" role="button" data-slide="prev">
<span class="carousel-control-prev-icon" aria-hidden="true"></span>
<span class="sr-only">Previous</span>
</a>
<a class="carousel-control-next" href="#carouselExampleCaptions" role="button" data-slide="next">
<span class="carousel-control-next-icon" aria-hidden="true"></span>
<span class="sr-only">Next</span>
</a>
</div>
</div>
<div class="container">
<div class="jumbotron card card-image mr-5 ml-5 transparencyjumbo " style="margin-top: -15px;background-repeat: no-repeat; background-size: cover;">
<form method="get" action="">
<div class="text-white text-center row" >
<div class="input-group mb-2 mr-sm-2">
<div class="input-group-prepend">
<div class="input-group-text"><i class="fas fa-clock"></i></div>
</div>
<select name="daytime" class="custom-select " size="1">
<option value="09:00:00">Morning Time </option>
<option value="12:00:00">Afternoon Time</option>
<option value="18:00:00">Evening Time</option>
</select>
</div>
</div>
<div class="text-white text-center row" >
<div class="input-group mb-2 mr-sm-2">
<div class="input-group-prepend">
<div class="input-group-text"><i class="far fa-calendar-alt"></i></div>
</div>
<input required name="Date" type="date" class="form-control py-0" id="inlineFormInputGroupUsername2" placeholder="Booking Date">
</div>
</div>
<div class="text-white text-center row" >
<div class="input-group mb-2 mr-sm-2">
<div class="input-group-prepend">
<div class="input-group-text"><i class="fas fa-utensils"></i></div>
</div>
<select name="perhead" class="custom-select " size="1">
<option value="0">Per head Only Seating</option>
<option value="1">Per head Seating + Food</option>
</select>
</div>
</div>
<div class="m-auto">
<button value="submit" type="submit" class="btn btn-danger"><i class="fas fa-check"></i>
Submit</button>
</div>
</form>
</div>
<div class="row" >
<?php
//echo hallAll();
//echo HallUserDesire("2013-03-15",0,"09:00:00");
if(isset($_GET["Date"]))
{
echo HallUserDesire($_GET["Date"],$_GET["perhead"],$_GET["daytime"]);
}
else
{
echo hallAll();
}
?>
</div>
</div>
<?php
include_once ("webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$('.carousel').carousel({
interval: 5000
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-10
* Time: 14:04
*/
session_start();
if(!isset($_SESSION['username']))
{
header("location:userLogin.php");
exit();
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light container">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="col-12 " style="margin-top:150px" >
<div class="shadow card p-2 badge-warning">
<!-- $OrderStatus=array("running","cancel","delieved","clear");-->
<h1 align="center" class="col-12">User Desplay</h1>
<a href="/Catering/customer/CustomerCreate.php?option=userDisplay" class="mb-1 text-center form-control btn-primary">Order Create</a>
<a href="/Catering/order/FindOrder.php?is_active=0" class="mb-1 text-center form-control btn-primary">Running Order</a>
<a href="/Catering/order/FindOrder.php?is_active=2" class="mb-1 text-center form-control btn-primary">deliver Orders</a>
<a href="/Catering/order/FindOrder.php?is_active=3" class="mb-1 text-center form-control btn-primary">Clear Orders</a>
<a href="/Catering/order/FindOrder.php?is_active=1" class="mb-1 text-center form-control btn-primary">Cancel Orders</a>
<a href="/Catering/payment/transferPaymentReceive.php?option=userDisplay" class="mb-1 text-center form-control btn-primary">Receive payment</a>
<a href="/Catering/system/dish/dishesDetail.php" class="mb-1 text-center form-control btn-primary">Guideline Dishes</a>
<a href="/Catering/system/user/usercreate.php" class="mb-1 text-center form-control btn-primary">User Create</a>
<a href="/Catering/payment/RemainingAmount.php" class="mb-1 text-center form-control btn-primary">Remaining payments</a>
<a href="/Catering/user/logout.php" class="mb-1 text-center form-control btn-primary">Log out</a>
</div>
</div>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-15
* Time: 11:41
*/
//
//header("location:Catering/user/userLogin.php");
//exit();
////echo '<a href="user/userLogin.php">hello world</a>';
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="bootstrap.min.css">
<script src="jquery-3.3.1.js"></script>
<script type="text/javascript" src="bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0;
padding: 0;
}
</style>
</head>
<body>
<a href="company/companyRegister/companyRegister.php" class="col-3 btn btn-outline-danger">Company Register</a>
<a href="company/companyRegister/companydisplay.php?companyid=3" class="col-3 btn btn-outline-danger">Log in</a>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-18
* Time: 10:45
*/
include_once ("../connection/connect.php");
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container" style="margin-top:150px">
<form class="col-12 shadow card mb-4" id="formId1" style="display: none">
<h2>Search order :</h2>
<div class="form-group row">
<label class="col-form-label col-4"> customer name</label>
<input name="p_name" type="text" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> customer CNIC</label>
<input name="p_cnic" type="number" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> customer ID</label>
<input name="p_id" type="number" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> customer phone</label>
<input name="n_number" type="text" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4">booking Date</label>
<input name="ot_booking_date" type="date" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4"> destination date</label>
<input name="ot_destination_date" type="date" class="changeColumn form-control col-8">
</div>
<div class="form-group row">
<label class="col-form-label col-4">order status</label>
<select name="ot_is_active" class="changeColumn form-control col-8 ">
<option value="None">None</option>
<?php
$OrderStatus=array("running","cancel","delieved","clear");
for($i=0;$i<count($OrderStatus);$i++)
{
echo '<option value='.$i.'>'.$OrderStatus[$i].'</option>';
}
?>
</select>
</div>
<div class="form-group row">
<a href="/Catering/payment/RemainingAmount.php" class="col-4 form-control btn-danger">cancel</a>
<button type="button" class="col-4 form-control btn-success">Find</button>
</div>
</form>
<h4 align="center" ><button data-display="hide" id="searchBtn" class="btn-outline-info btn float-left ">Search Order</button>Payments Records</h4>
<div class="w-100" id="recordsAll1">
<table class="table table-bordered table-responsive" style="width: 100%;">
<tbody class="font-weight-bold">
<td >order Id</td>
<td>customer Name</td>
<td>received amount</td>
<td>System Amount</td>
<td>remaining system amount </td>
<td>your demanded amount</td>
<td>remaining demand amount</td>
</tbody>
<?php
//$OrderStatus=array("running","cancel","delieved","clear");
$sql="SELECT DISTINCT ot.id, (SELECT p.name FROM person as p WHERE p.id=ot.person_id), (SELECT sum(py.amount) FROM payment as py WHERE (py.IsReturn=0)AND(py.orderDetail_id=ot.id)) ,ot.extre_charges,ot.total_amount, (SELECT SUM(dd.price*dd.quantity) FROM dish_detail as dd WHERE dd.orderDetail_id=ot.id) FROM orderDetail as ot LEFT join payment as py on ot.id=py.orderDetail_id WHERE ot.is_active in(0,2)";
$details=queryReceive($sql);
//print_r($details);
$display='';
for ($i=0;$i<count($details);$i++)
{
$display.=' <tr data-orderid="'.$details[$i][0].'" class="orderDetail">
<td >'.$details[$i][0].'</td>
<td>'.$details[$i][1].'</td>
<td>'.(int)$details[$i][2].'</td>
<td>'.(int)$details[$i][5].'</td>
<td> '.(int) ($details[$i][5]-$details[$i][2]).'</td>
<td>'.(int) $details[$i][4].'</td>
<td>'.(int) ($details[$i][4]-$details[$i][2]).'</td>
';
$display.='</tr>';
}
echo $display;
?>
</table>
</div>
</div>
<script>
$(document).ready(function () {
$(document).on("click",".orderDetail",function ()
{
var orderid=$(this).data("orderid");
location.href="/Catering/order/PreviewOrder.php?order="+orderid;
});
$(document).on("change",'.changeColumn',function (e)
{
e.preventDefault();
var formdata=new FormData($('#formId1')[0]);
$.ajax({
url:"RemainingFinderServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
$("#recordsAll1").html(data);
}
});
});
$("#searchBtn").click(function () {
var display=$(this).data("display");
if(display=="hide")
{
$("#formId1").show('slow');
$(this).data("display","show");
}
else
{
$("#formId1").hide('slow');
$(this).data("display","hide");
}
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 14:15
*/
if(!isset($_GET["user_id"]) && !isset($_GET["order"]))
{
echo 'orderTable id and user id is not GET';
exit();
}
$userId=$_GET['user_id'];
$orderTable_id=$_GET['order'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container" style="margin-top:180px">
<form class="col-12 card shadow" id="from2">
<input hidden name="user_id" value="<?php
echo $userId;
?>">
<input hidden name="orderTable_id" value="<?php
echo $orderTable_id;
?>">
<h1 align="center"> Get Payment</h1>
<div class="form-group row">
<label class="col-4 col-form-label">Name</label>
<input type="text" name="name" class="col-8 form-control">
</div>
<div class="form-group row">
<label class="col-4 col-form-label">Amount</label>
<input type="number" name="Amount" class="col-8 form-control">
</div>
<div class="form-group row">
<label class="col-4 col-form-label">Status amount</label>
<select name="status" class="custom-select col-8">
<option value="0">Get Amount</option>
<option value="1">Return Amount</option>
</select>
</div>
<div class="form-group row">
<label class="col-4 col-form-label">Rating Customer</label>
<span id="showRange" class="form-control col-2"></span>
<input id="rangeInput" step="1" type="range" max="5" min="1" value="3" name="rating" class="form-control col-6">
</div>
<div class="form-group row">
<label class="col-4 col-form-label">personality</label>
<textarea type="text" name="personality" class="col-8 form-control"></textarea>
</div>
<div class="form-group row">
<a href="/order/PreviewOrder.php?order=<?php echo $orderTable_id;?>" class="form-control col-3 btn-danger">cancel</a>
<button id="submitBtnfrom" type="submit" class="form-control col-3 btn-primary">Submit</button>
</div>
</form>
</div>
<script>
$(document).ready(function () {
$('#showRange').html($("#rangeInput").val());
$("#rangeInput").change(function () {
$('#showRange').html($("#rangeInput").val());
});
$("#submitBtnfrom").click(function (e) {
e.preventDefault();
var formdata=new FormData($("#from2")[0]);
formdata.append("option","GetPayment");
$.ajax({
url:"paymentServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
});
</script>
</body>
</html>
<file_sep><?php
$hallid='';
$cateringid='';
if(isset($_GET['hallid']))
$hallid =$_GET['hallid'];
if(isset($_GET['cateringid']))
$cateringid=$_GET['cateringid'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light container">
<div class="col-12 " style="margin-top:150px" >
<div class="shadow card p-2 badge-warning">
<!-- $OrderStatus=array("running","cancel","delieved","clear");-->
<h1 align="center" class="col-12">User Desplay</h1>
<a href="/Catering/customer/CustomerCreate.php?option=userDisplay&hallid=<?php echo $hallid;?>&cateringid=<?php echo $cateringid;?>" class="mb-1 text-center form-control btn-primary">Order Create</a>
<a href="/Catering/order/FindOrder.php?order_status=Running" class="mb-1 text-center form-control btn-primary">Running Order</a>
<a href="/Catering/order/FindOrder.php?order_status=Deliever" class="mb-1 text-center form-control btn-primary">Deliever Orders</a>
<a href="/Catering/order/FindOrder.php?order_status=Clear" class="mb-1 text-center form-control btn-primary">Clear Orders</a>
<a href="/Catering/order/FindOrder.php?order_status=Cancel" class="mb-1 text-center form-control btn-primary">Cancel Orders</a>
<a href="/Catering/payment/transferPaymentReceive.php?option=userDisplay" class="mb-1 text-center form-control btn-primary">Receive payment</a>
<a href="/Catering/system/dish/dishesDetail.php" class="mb-1 text-center form-control btn-primary">Guideline Dishes</a>
<a href="/Catering/system/user/usercreate.php" class="mb-1 text-center form-control btn-primary">User Create</a>
<a href="/Catering/payment/RemainingAmount.php" class="mb-1 text-center form-control btn-primary">Remaining payments</a>
<a href="/Catering/user/logout.php" class="mb-1 text-center form-control btn-primary">Log out</a>
</div>
</div>
<script>
</script>
</body>
</html>
<file_sep><?php
include_once ('../../connection/connect.php');
if(!isset($_GET['hall']))
{
header("location:../companyRegister/companyEdit.php");
}
$encoded=$_GET['hall'];
$id=base64url_decode($encoded);
if((!is_numeric($id))||$id=="")
{
header("location:../companyRegister/companyEdit.php");
}
$hallid='';
$companyid='';
$hallid=$id;
$companyid=$_COOKIE['companyid'];
$sql='SELECT `name`, `max_guests`, `noOfPartitions`, `ownParking`, `expire`, `image`, `hallType`, `location_id` FROM `hall` WHERE id='.$hallid.'';
$halldetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron jumbotron-fluid text-center" style="background-image: url(<?php
if((file_exists('../../images/hall/'.$halldetail[0][5]))&&($halldetail[0][5]!=""))
{
echo "'../../images/hall/".$halldetail[0][5]."'";
}
else
{
echo "https://www.pakvenues.com/system/halls/cover_images/000/000/048/original/Umar_Marriage_Hall_lahore.jpg?1566758537";
}
?>);background-repeat: no-repeat ;background-size: 100% 100%">
<div class="container" style="background-color: white;opacity: 0.7">
<h1 class="display-4"><i class="fas fa-comments fa-1x"></i> <?php echo $halldetail[0][0]; ?></h1>
<p class="lead">you can see what the user comment on you customer.</p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php " class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container">
<h1 class="font-weight-light mt-4 mb-0">Comments</h1>
<hr class="mt-2 mb-3">
<div class="row bootstrap snippets">
<div class="col-md-12 col-md-offset-2 col-sm-12 m-auto">
<div class="comment-wrapper">
<div class="panel panel-info ">
<form id="commentform">
<?php
echo '<input hidden type="number" name="hallid" value="'.$hallid.'">';
?>
<div class="panel-body">
<textarea name="comment" class="form-control" placeholder="write a comment..." rows="3"></textarea>
<br>
<div class="input-group mb-2">
<div class="input-group-prepend">
<div class="input-group-text"><i class="fas fa-comments"></i></div>
</div>
<input name="email" type="email" class="form-control " placeholder="Email">
</div>
<button id="btncoment" type="button" class="btn btn-info pull-right float-right col-5">Post</button>
</form>
<?php
$display='';
$sql='SELECT `hall_id`, `catering_id`, `id`, `comment`, `email`, `datetime`, `expire` FROM `comments` WHERE (hall_id='.$hallid.')&&(ISNULL(expire))';
$commentresult=queryReceive($sql);
for ($i=0;$i<count($commentresult);$i++)
{
$display.='
<div class="clearfix"></div>
<hr>
<ul class="media-list text-white">
<li class="media">
<a href="#" class="pull-left">
<img src="https://bootdey.com/img/Content/user_1.jpg" alt="" class="img-circle">
</a>
<div class="media-body">
<span class="text-muted pull-right">
<small class="text-dark">'.$commentresult[$i][5].'</small>
</span>
<strong class="text-warning">@'.$commentresult[$i][4].'</strong>
<p>
'.$commentresult[$i][3].'
</p>
</div>
</li>
</ul>
';
}
echo $display;
?>
</div>
</div>
</div>
</div>
</div>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
$("#btncoment").click(function ()
{
var formdata = new FormData($("#commentform")[0]);
formdata.append("option", "commentAdd");
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
location.reload();
}
});
}) ;
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-03
* Time: 17:20
*/
include_once ("../connection/connect.php");
function createOnlyAllSeating($hallid,$daytime)
{
$monthsArray=array('January', 'February', 'March', 'April', 'May', 'June', 'July', 'August', 'September', 'October', 'November', 'December');
for($i=0;$i<count($monthsArray);$i++)
{
$sql='INSERT INTO `hallprice`(`id`, `month`, `isFood`, `price`, `describe`, `dayTime`, `expire`, `hall_id`, `package_name`) VALUES (NULL,"'.$monthsArray[$i].'",0,0,NULL,"'.$daytime.'",NULL,'.$hallid.',NULL)';
querySend($sql);
}
}
if(isset($_POST['option']))
{
if($_POST['option']=="createUser")
{
$username=chechIsEmpty($_POST['username']);
$password=chechIsEmpty($_POST['password']);
$sql='SELECT u.id FROM user as u WHERE (u.password="'.$password.'") AND (u.username="'.$username.'")';
$userExist=queryReceive($sql);
if(count($userExist)!=0)
{
echo "user is already exist";
exit();
}
$image='';
if(!empty($_FILES['image']["name"]))
{
$image = "../images/users/" . $_FILES['image']['name'];
$resultimage = ImageUploaded($_FILES, $image);//$dishimage is destination file location;
if ($resultimage != "") {
print_r($resultimage);
exit();
}
$image = "../../images/users/" . $_FILES['image']['name'];
}
$name = trim($_POST['name']);
$numberArray = $_POST['number'];
$isowner=1;
$cnic = $_POST['cnic'];
$city = $_POST['city'];
$area = $_POST['area'];
$streetNo = chechIsEmpty($_POST['streetNo']);
$houseNo = chechIsEmpty($_POST['houseNo']);
$date = date('Y-m-d');
$sql='INSERT INTO `person`(`name`, `cnic`, `id`, `date`, `image`) VALUES ("'.$name.'","'.$cnic.'",NULL,"'.$date.'","'.$image.'")';
querySend($sql);
$last_id = mysqli_insert_id($connect);
$sql="INSERT INTO `address` (`id`, `address_street_no`, `address_house_no`, `person_id`, `address_city`, `address_town`) VALUES (NULL, '".$streetNo."', '".$houseNo."', '".$last_id."', '".$city."', '".$area."');";
querySend($sql);
for ($i=0;$i<count($numberArray);$i++)
{
$sql = "INSERT INTO `number`(`number`, `id`, `is_number_active`, `person_id`) VALUES ('".$numberArray[$i]."',NULL,1,$last_id)";
querySend($sql);
}
$customerId = $last_id;
$sql='INSERT INTO `user`(`id`, `username`, `password`, `person_id`, `isExpire`,`isowner`, `company_id`) VALUES (NULL,"'.$username.'","'.$password.'",'.$customerId.',NULL,"'.$isowner.'",NULL)';
querySend($sql);
$userid = mysqli_insert_id($connect);
$sql='INSERT INTO `company`(`id`, `name`, `expire`, `user_id`) VALUES (NULL,"'.$_POST['companyName'].'",NULL,'.$userid.')';
querySend($sql);
$companyid=mysqli_insert_id($connect);
$sql='UPDATE user as u SET u.company_id='.$companyid.' WHERE u.id='.$userid.'';
querySend($sql);
setcookie('userid',$userid , time() + (86400 * 30), "/");
setcookie("isOwner",1,time() + (86400 * 30), "/");
setcookie("username",$username,time() + (86400 * 30), "/");
setcookie("companyid",$companyid,time() + (86400 * 30), "/");
setcookie("userimage",$image,time() + (86400 * 30), "/");
}
else if($_POST['option']=="createCatering")
{
$companyid=$_POST['companyid'];
$namecatering=$_POST['namecatering'];
$Cateringimage='';
$sql='';
if(!empty($_FILES['image']["name"]))
{
$Cateringimage = "../images/catering/" . $_FILES['image']['name'];
$resultimage = ImageUploaded($_FILES, $Cateringimage);//$dishimage is destination file location;
if ($resultimage != "") {
print_r($resultimage);
exit();
}
}
$sql='INSERT INTO `catering`(`id`, `name`, `expire`, `image`, `location_id`, `company_id`) VALUES (NULL,"'.$namecatering.'",NULL,"'.$Cateringimage.'",NULL,'.$companyid.')';
querySend($sql);
$cateringid=mysqli_insert_id($connect);
if(!isset($_POST['dishtypename']))
{
exit();
}
$dishtypename=$_POST['dishtypename'];
$dishtypeid='';
$dishid=$_POST['dishid'];
$dishname=$_POST['dishname'];
$image=$_POST['image'];
for($i=0;$i<count($dishtypename);$i++)
{
$sql='SELECT `id` FROM `dish_type` WHERE (name="'.$dishtypename[$i].'") AND (catering_id='.$cateringid.')';
$detail=queryReceive($sql);
if(count($detail)>0)
{
$dishtypeid=$detail[0][0];
}
else
{
$sql='INSERT INTO `dish_type`(`id`, `name`, `isExpire`, `catering_id`) VALUES (NULL,"'.$dishtypename[$i].'",NULL,'.$cateringid.')';
querySend($sql);
$dishtypeid=mysqli_insert_id($connect);
}
$sql='INSERT INTO `dish`(`name`, `id`, `image`, `dish_type_id`, `isExpire`, `catering_id`) VALUES ("'.$dishname[$i].'",NULL,"'.$image[$i].'",'.$dishtypeid.',NULL,'.$cateringid.')';
querySend($sql);
$idDishe=mysqli_insert_id($connect);
$sql='SELECT `name` FROM `SystemAttribute` WHERE ISNULL(isExpire) AND (systemDish_id='.$dishid[$i].')';
$detailAttributes=queryReceive($sql);
for($j=0;$j<count($detailAttributes);$j++)
{
$sql='INSERT INTO `attribute`(`name`, `id`, `dish_id`, `isExpire`) VALUES ("'.$detailAttributes[$j][0].'",NULL,'.$idDishe.',NULL)';
querySend($sql);
}
}
}
else if($_POST['option']=="CreateHall")
{
$companyid=$_POST['companyid'];
$hallname=$_POST['hallname'];
$hallimage='';
if(!empty($_FILES['image']["name"]))
{
$hallimage = "../images/hall/" . $_FILES['image']['name'];
$resultimage = ImageUploaded($_FILES, $hallimage);//$dishimage is destination file location;
if ($resultimage != "")
{
print_r($resultimage);
exit();
}
}
$daytime='';
$parking=0;
if(isset($_POST['parking']))
{
$parking=1;
}
$halltype=$_POST['halltype'];
$capacity=chechIsEmpty($_POST['capacity']);
$partition=chechIsEmpty($_POST['partition']);
$sql='INSERT INTO `hall`(`id`, `name`, `max_guests`, `function_per_Day`, `noOfPartitions`, `ownParking`, `expire`, `image`, `hallType`, `location_id`, `company_id`) VALUES (NULL,"'.$hallname.'",'.$capacity.',"'.$daytime.'",'.$partition.','.$parking.',NULL,"'.$hallimage.'",'.$halltype.',NULL,'.$companyid.')';
querySend($sql);
$hallid=mysqli_insert_id($connect);
$daytimearray=array("Morning","Afternoon","Evening");
for($i=0;$i<count($daytimearray);$i++)
{
createOnlyAllSeating($hallid,$daytimearray[$i]);
}
}
else if($_POST['option']=='createOnlyseating')
{
$hallid=$_POST['hallid'];
$daytime=$_POST['daytime'];
createOnlyAllSeating($hallid,$daytime);
}
else if($_POST['option']=="CreatePackage")
{
if($_POST['perivious']!="none")
{
$packid=$_POST['perivious'];
$month=$_POST['month'];
$daytime=$_POST['daytime'];
$hallid=$_POST['hallid'];
$sql='SELECT `id`, `month`, `isFood`, `price`, `describe`, `dayTime`, `expire`, `hall_id`, `package_name` FROM `hallprice` WHERE id='.$packid.'';
$result=queryReceive($sql);
$sql='INSERT INTO `hallprice`(`id`, `month`, `isFood`, `price`, `describe`, `dayTime`, `expire`, `hall_id`, `package_name`) VALUES (NULL,"'.$month.'",1,'.$result[0][3].',"'.$result[0][4].'","'.$daytime.'",NULL,'.$hallid.',"'.$result[0][8].'")';
querySend($sql);
$last_id=mysqli_insert_id($connect);
$sql='SELECT `id`, `dishname`, `image`, `expire`, `hallprice_id` FROM `menu` WHERE ISNULL(expire) &&(hallprice_id='.$packid.')';
$result=queryReceive($sql);
for($i=0;$i<count($result);$i++)
{
$sql='INSERT INTO `menu`(`id`, `dishname`, `image`, `expire`, `hallprice_id`) VALUES (NULL,"'.$result[$i][1].'","'.$result[$i][2].'",NULL,'.$last_id.')';
querySend($sql);
}
exit();
}
if(!isset($_POST['dishname']))
{
exit();
}
$dishnames=$_POST['dishname'];
$image=$_POST['image'];
$month=$_POST['month'];
$daytime=$_POST['daytime'];
$hallid=$_POST['hallid'];
$packagename=$_POST['packagename'];
$rate=chechIsEmpty($_POST['rate']);
$describe=$_POST['describe'];
$sql='INSERT INTO `hallprice`(`id`, `month`, `isFood`, `price`, `describe`, `dayTime`, `expire`, `hall_id`, `package_name`) VALUES (NULL,"'.$month.'",1,'.$rate.',"'.$describe.'","'.$daytime.'",NULL,'.$hallid.',"'.$packagename.'")';
querySend($sql);
$id=mysqli_insert_id($connect);
for ($i=0;$i<count($dishnames);$i++)
{
$sql='INSERT INTO `menu`(`id`, `dishname`, `image`, `expire`, `hallprice_id`) VALUES (NULL,"'.$dishnames[$i].'","'.$image[$i].'",NULL,'.$id.')';
querySend($sql);
}
}
else if($_POST['option']=="showdaytimelist")
{
$hallname=$_POST['hallname'];
$hallid=$_POST['hallid'];
$daytime=$_POST['daytime'];
$companyid=$_POST['companyid'];
$monthsArray = array('January', 'February', 'March', 'April', 'May', 'June', 'July', 'August', 'September', 'October', 'November', 'December');
$display='<table class="col-12 border-white border">
<thead>
<tr>
<th scope="col" >
<h4 align="center"><i class="fas fa-list-ol mr-3"></i>'.$daytime.' Prize list</h4>
</th>
</tr>
</thead>
<tbody>';
for($i=0;$i<count($monthsArray);$i++)
{
$sql='SELECT `id`,`price` FROM `hallprice` WHERE (hall_id='.$hallid.')AND (isFood=0) AND (dayTime="'.$daytime.'") AND ISNULL(expire)
AND (month="'.$monthsArray[$i].'")';
$detailList=queryReceive($sql);
$display.='
<tr>
<td scope="col" >
<h4 align="center">'.$monthsArray[$i].'</h4>
<div class="alert-light col-12 card">
<div class="form-group row col-12 p-0 ">
<label class="col-form-label col-4"> Prize Only Seating </label>
<div class="input-group input-group-lg col-8">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-money-bill-alt"></i></span>
</div>
<input data-menuid="'.$detailList[0][0].'" class="changeSeating form-control" type="number" value="'.$detailList[0][1].'">
</div>
</div>
<h3 align="center" class="col-12 mt-3">List of packages with Food</h3>
<a href="addnewpackage.php?hallname='.$hallname.'&month='.$monthsArray[$i].'&daytime='.$daytime.'" class="form-control btn-primary col-12 text-center"><i class="fas fa-plus-square"></i> Add New Package</a>
<div class="form-group row ">';
$sql='SELECT `id`,`expire`, `package_name` FROM `hallprice` WHERE (hall_id='.$hallid.')
AND (dayTime="'.$daytime.'") AND (month="'.$monthsArray[$i].'") AND (isFood=1)';
$ALLpackages=queryReceive($sql);
for ($j=0;$j<count($ALLpackages);$j++)
{
// $display.=' <a href="?editpackage=yes&hallname='.$hallname.'&month='.$monthsArray[$i].'&daytime='.$daytime.'&packageid='.$ALLpackages[$j][0].'" class="form-control btn-success col-4 text-center m-2"> '.$ALLpackages[$j][2].'';
// if($ALLpackages[$j][1]!=NULL)
// {
// $display.=' Expired';
// }
// $display.='</a>';
if($ALLpackages[$j][1]!="")
{
$display.= '<a href="?editpackage=yes&hallname='.$hallname.'&month='.$monthsArray[$i].'&daytime='.$daytime.'&packageid='.$ALLpackages[$j][0].'" class="btn btn-danger col-sm-4 col-md-3 col-xl-3 m-1">'.$ALLpackages[$j][2].'</a>';
}
else
{
$display.= '<a href="?editpackage=yes&hallname='.$hallname.'&month='.$monthsArray[$i].'&daytime='.$daytime.'&packageid='.$ALLpackages[$j][0].'" class="btn btn-warning col-sm-4 col-md-3 col-xl-3 m-1">'.$ALLpackages[$j][2].'</a>';
}
}
$display.='</div></div>
</td>
</tr>';
}
$display.='
</tbody>
</table>';
echo $display;
}
else if($_POST['option']=="changeSeating")
{
$packageid=$_POST['packageid'];
$value=chechIsEmpty($_POST['value']);
$sql='UPDATE `hallprice` SET price='.$value.' WHERE id='.$packageid.'';
querySend($sql);
}
else if($_POST['option']=="ExpireBtn")
{
$packageid=$_POST['packageid'];
$expirevalue=$_POST['expirevalue'];
if($expirevalue=="Click Expire")
{
$dayAndTime=date('Y-m-d H:i:s');
$sql='UPDATE `hallprice` SET expire="'.$dayAndTime.'" WHERE id='.$packageid.'';
}
else
{
$sql='UPDATE `hallprice` SET expire=NULL WHERE id='.$packageid.'';
}
querySend($sql);
}
else if($_POST['option']=="packagechange")
{
$packageid=$_POST['packageid'];
$columnname=$_POST['columnname'];
$value=$_POST['value'];
$sql='UPDATE hallprice as hp SET hp.'.$columnname.' ="'.$value.'" WHERE hp.id='.$packageid.'';
querySend($sql);
}
else if($_POST['option']=="alreadydishremove")
{
$id=$_POST['id'];
$dayAndTime=date('Y-m-d H:i:s');
$sql='UPDATE `menu` SET expire="'.$dayAndTime.'" WHERE id='.$id.'';
querySend($sql);
}
else if($_POST['option']=="Extendmenu")
{
$packageid=$_POST['packageid'];
if(!isset($_POST['dishname']))
{
exit();
}
$dishnames=$_POST['dishname'];
$image=$_POST['image'];
for($i=0;$i<count($dishnames);$i++)
{
$sql='INSERT INTO `menu`(`id`, `dishname`, `image`, `expire`, `hallprice_id`) VALUES (NULL,"'.$dishnames[$i].'","'.$image[$i].'",NULL,'.$packageid.')';
querySend($sql);
}
}
else if($_POST['option']=="checkpackages1")
{
$monthno=$_POST['month'];
$date=$_POST['date'];
$time=$_POST['time'];
$perheadwith=$_POST['perheadwith'];
$hallid=$_POST['hallid'];
$monthsArray = array('January', 'February', 'March', 'April', 'May', 'June', 'July', 'August', 'September', 'October', 'November', 'December');
$month=$monthsArray[$monthno];
$sql='SELECT `id`, `package_name`,`price`,`describe` FROM `hallprice` WHERE ISNULL(expire) AND (month="'.$month.'") AND (dayTime="'.$time.'") And (isFood='.$perheadwith.') AND (hall_id='.$hallid.')';
$detailpackage=queryReceive($sql);
if(($perheadwith==1)&&(!(count($detailpackage)>0)))
{
exit();
}
$display='<h3 align="center">Packages Detail </h3>';
if($perheadwith==1)
{
//with food menu
for ($i=0;$i<count($detailpackage);$i++)
{
$display.=' <div class="checkclasshas custom-control custom-radio form-group ">
<input type="radio" data-describe="'.$detailpackage[$i][0].'" value="'.$detailpackage[$i][0].'" class="changeradio custom-control-input" id="defaultUnchecked'.$i.'" name="defaultExampleRadios">
<label class="custom-control-label" for="defaultUnchecked'.$i.'">'.$detailpackage[$i][1].' package with Rs='.$detailpackage[$i][2].' price</label>
</div>
<input hidden id="describe'.$detailpackage[$i][0].'" type="text" value="'.$detailpackage[$i][3].'">';
}
}
else
{
//with seating menu
$display.=' <div class="checkclasshas custom-control custom-radio form-group ">
<input type="radio" value="'.$detailpackage[0][0].'" class="custom-control-input" id="defaultUnchecked" name="defaultExampleRadios" checked>
<label class="custom-control-label" for="defaultUnchecked"> Only Seating price = '.$detailpackage[0][2].'</label>
</div>';
}
if($time=="Morning")
{
$time="09:00:00";
}
else if($time=="Afternoon")
{
$time="12:00:00";
}
else {
$time="18:00:00";
}
$sql='SELECT id FROM orderDetail as od WHERE (od.booking_date= "'.$date.'") AND (od.destination_time="'.$time.'") AND (od.sheftHall="Running") AND (od.hall_id='.$hallid.')';
$detailhalls=queryReceive($sql);
if(count($detailhalls)>0)
{
$display.='<h4 class="btn-outline-danger">Already '.count($detailhalls).' function has booked</h4>';
for ($i=0;$i<count($detailhalls);$i++)
{
$display.='<p>'.($i+1).' function booked with '.$detailhalls[$i][0].' Guests</p>';
}
}
echo $display;
}
else if($_POST['option']=="viewmenu")
{
$packageid=$_POST['packageid'];
$sql='SELECT `dishname`, `image` FROM `menu` WHERE (hallprice_id='.$packageid.') AND ISNULL(expire)';
$menu=queryReceive($sql);
$display='<h4 align="center" class="col-12">Menu</h4>';
for ($i=0;$i<count($menu);$i++)
{
$display.='
<div class="col-3 alert-danger shadow border m-2 form-group rounded" style="height: 30vh;" >
<img src="'.$menu[$i][1].'" class="col-12 " style="height: 15vh">
<p class="col-form-label" class="form-control col-12">'.$menu[$i][0].'</p>
</div>';
}
echo $display;
}
else if($_POST['option']=="createOrderofHall")
{
$packageid='';
if(isset($_POST['packageid']))
$packageid=$_POST['packageid'];
$hallid=$_POST['hallid'];
$userid=$_POST['userid'];
$personid=$_POST['personid'];
$guests=chechIsEmpty($_POST['guests']);
$date=$_POST['date'];
$time=$_POST['time'];
$perheadwith=$_POST['perheadwith'];
$describe=$_POST['describe'];
$totalamount=chechIsEmpty($_POST['totalamount']);
$currentdate=date('Y-m-d');
if($time=="Morning")
{
$time="9:00";
}
else if($time=="Afternoon")
{
$time="12:00";
}
else {
$time="18:00";
}
$catering="";
$notice="";
if($perheadwith==1)
{
$catering="Running";
$notice="alert";
}
$sql='INSERT INTO `orderDetail`(`id`, `hall_id`, `catering_id`, `hallprice_id`, `user_id`,
`sheftCatering`, `sheftHall`, `sheftCateringUser`, `sheftHallUser`, `address_id`, `person_id`,
`total_amount`, `total_person`, `status_hall`, `destination_date`, `booking_date`, `destination_time`,
`status_catering`, `notice`,`describe`)
VALUES (NULL,'.$hallid.',NULL,'.$packageid.','.$userid.',NULL,
NULL,NULL,NULL,NULL,'.$personid.','.$totalamount.','.$guests.',"Running","'.$date.'","'.$currentdate.'",
"'.$time.'","'.$catering.'","'.$notice.'","'.$describe.'")';
querySend($sql);
$_SESSION['order']=mysqli_insert_id($connect);
}
else if($_POST['option']=="Edithallorder")
{
$order=$_POST['order'];
$packageid='';
if(isset($_POST['packageid']))
$packageid=$_POST['packageid'];
$guests=chechIsEmpty($_POST['guests']);
$date=$_POST['date'];
$time=$_POST['time'];
$perheadwith=$_POST['perheadwith'];
$cateringid='NULL';
if(isset($_POST['cateringid']) &&($perheadwith==1))
{
$cateringid=$_POST['cateringid'];
}
$describe=$_POST['describe'];
$totalamount=chechIsEmpty($_POST['totalamount']);
$catering="";
$notice="";
if($time=="Morning")
{
$time="9:00:00";
}
else if($time=="Afternoon")
{
$time="12:00:00";
}
else if($time=="Evening")
{
$time="18:00:00";
}
$orderStatus=$_POST['orderStatus'];
if($perheadwith==0)
{
//just cancel of catering /../
$catering="Cancel";
$notice="";
}
else
{
$catering=$orderStatus;
if($catering=="Running")
$notice="alert";
}
$sql='UPDATE `orderDetail` SET `catering_id`='.$cateringid.',`hallprice_id`='.$packageid.',
`total_amount`='.$totalamount.',`total_person`='.$guests.',`status_hall`
="'.$orderStatus.'",`destination_date`="'.$date.'",`destination_time`="'.$time.'",
`status_catering`="'.$catering.'",`notice`="'.$notice.'",`describe`="'.$describe.'"
WHERE id='.$order.'';
querySend($sql);
}
else if($_POST['option']=="halledit")
{
$hallid=$_POST['hallid'];
$hallname=$_POST['hallname'];
$hallimage=$_POST['previousimage'];
if(!empty($_FILES['image']["name"]))
{
$hallimage = "../images/hall/" . $_FILES['image']['name'];
$resultimage = ImageUploaded($_FILES, $hallimage);//$dishimage is destination file location;
if ($resultimage != "")
{
print_r($resultimage);
exit();
}
}
$daytime='';
$parking=0;
if(isset($_POST['parking']))
{
$parking=1;
}
$halltype=$_POST['halltype'];
$capacity=chechIsEmpty($_POST['capacity']);
$partition=chechIsEmpty($_POST['partition']);
$sql='UPDATE `hall` SET `name`="'.$hallname.'",`max_guests`='.$capacity.',`noOfPartitions`='.$partition.',`ownParking`='.$parking.',`image`="'.$hallimage.'",`hallType`='.$halltype.' WHERE id='.$hallid.'';
querySend($sql);
}
else if($_POST['option']=="cateringedit")
{
$cateringid=$_POST['cateringid'];
$cateringname=$_POST['cateringname'];
$cateringimage=$_POST['previousimage'];
if(!empty($_FILES['image']["name"]))
{
$cateringimage = "../images/catering/" . $_FILES['image']['name'];
$resultimage = ImageUploaded($_FILES, $cateringimage);//$dishimage is destination file location;
if ($resultimage != "")
{
print_r($resultimage);
exit();
}
}
$sql='UPDATE `catering` SET `name`="'.$cateringname.'",`image`="'.$cateringimage.'" WHERE id='.$cateringid.'';
querySend($sql);
}
else if($_POST['option']=="formDishadd")
{
$dishname=chechIsEmpty($_POST['dishname']);
$dishimage='';
if(!empty($_FILES['image']["name"]))
{
$dishimage = "../images/dishImages/" . $_FILES['image']['name'];
$resultimage = ImageUploaded($_FILES, $dishimage);//$dishimage is destination file location;
if ($resultimage != "") {
print_r($resultimage);
exit();
}
$dishimage = "../../images/dishImages/" . $_FILES['image']['name'];
}
$sql='INSERT INTO `systemDish`(`name`, `id`, `image`, `isExpire`, `systemDishType_id`) VALUES ("'.$dishname.'",NULL,"'.$dishimage.'",NULL,NULL)';
querySend($sql);
$sql = 'SELECT `name`, `id`, `image` FROM `systemDish` WHERE ISNULL(isExpire) ';
echo dishesOfPakage($sql);
}
else if($_POST['option']=="Showdishessystem")
{
$sql = 'SELECT `name`, `id`, `image` FROM `systemDish` WHERE ISNULL(isExpire) ';
echo dishesOfPakage($sql);
}
else if($_POST['option']=="commentAdd")
{
$hallid=$_POST['hallid'];
$comments=$_POST['comment'];
$email=$_POST['email'];
$currentdatetime=date('Y-m-d H:i:s');
$sql='INSERT INTO `comments`(`hall_id`, `catering_id`, `id`, `comment`, `email`, `datetime`, `expire`) VALUES ('.$hallid.',NULL,NULL,"'.$comments.'","'.$email.'","'.$currentdatetime.'",NULL)';
querySend($sql);
}
else if($_POST['option']=="dishpredict")
{
$dishname=$_POST['dishname'];
$sql='SELECT `name`, `id`, `image` FROM `systemDish` WHERE ISNULL(isExpire) AND name LIKE "%'.$dishname.'%"';
echo dishesOfPakage($sql);
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
$hallid="";
$cateringid='';
if(isset($_GET['hallid']))
$hallid=$_GET['hallid'];
if(isset($_GET['cateringid']))
$cateringid=$_GET['cateringid'];
$orderId=$_GET['order'];
$_SESSION['userid']=1;
$sql='SELECT (SELECT p.name FROM person as p WHERE p.id=od.person_id),od.person_id FROM orderDetail as od WHERE od.id='.$orderId.'';
$orderDetailPerson= queryReceive($sql);
$customerID=$orderDetailPerson[0][1];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<div class="container" style="margin-top:150px">
<h1 align="center">Order Preview</h1>
<div class="col-12 shadow card p-3">
<h4 class="col-12">
<div class="form-group row">
<label class="col-form-label col-6">Customer Name</label>
<label class="col-form-label col-6"><?php
echo $orderDetailPerson[0][0];
?></label>
</div>
<div class="form-group row">
<label class="col-form-label col-6">Order ID</label>
<label class="col-form-label col-6"><?php
echo $orderId;
?></label>
</div>
</h4>
<a href="/Catering/customer/customerEdit.php?customer=<?php echo $customerID;?>&order=<?php echo $orderId;?>&option=PreviewOrder" class=" mb-1 text-center form-control btn-success">Customer Preview</a>
<?php
if($hallid!='')
{
//hall order edit
echo '<a href="../company/hallBranches/EdithallOrder.php?hallid='.$hallid.'&order='.$orderId.'" class="text-center mb-1 form-control btn-success">Hall order Edit</a>';
}
else
{
//catering order editor
echo '<a href="/Catering/order/orderEdit.php?order='.$orderId.'&option=PreviewOrder" class="text-center mb-1 form-control btn-success">Order Preview</a>
';
}
?>
<a href="/Catering/dish/AllSelectedDishes.php?order=<?php echo $orderId;?>&option=PreviewOrder" class=" mb-1 text-center form-control btn-success">Bill detail</a>
<a href="/Catering/payment/paymentHistory.php?user_id=<?php echo $_SESSION['userid'];?>&order=<?php echo $orderId;?>" class=" mb-1 text-center form-control btn-success">Payment History</a>
<a href="/Catering/payment/getPayment.php?user_id=<?php echo $_SESSION['userid'];?>&order=<?php echo $orderId;?>" class=" mb-1 text-center form-control btn-success">Get payment</a>
<a href="/Catering/payment/transferPayment.php?user_id=<?php echo $_SESSION['userid'];?>&order=<?php echo $orderId;?>" class=" mb-1 text-center form-control btn-success">Transfer payment</a>
<a href="/Catering/payment/transferPaymentReceive.php?user_id=<?php echo $_SESSION['userid'];?>&order=<?php echo $orderId;?>" class=" mb-1 text-center form-control btn-success">Receive payment</a>
<a href="/Catering/user/userDisplay.php" class=" mb-1 text-center form-control btn-success">User Display</a>
</div>
</div>
<script>
</script>
</body>
</html>
<file_sep><?php
include_once ('../../connection/connect.php');
if(!isset($_GET['hall']))
{
header("location:../companyRegister/companyEdit.php");
}
$encoded=$_GET['hall'];
$id=base64url_decode($encoded);
if((!is_numeric($id))||$id=="")
{
header("location:../companyRegister/companyEdit.php");
}
$hallid='';
$companyid='';
$hallid=$id;
$companyid=$_COOKIE['companyid'];
$sql='SELECT `name`, `max_guests`, `noOfPartitions`, `ownParking`, `expire`, `image`, `hallType`, `location_id` FROM `hall` WHERE id='.$hallid.'';
$halldetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
#formhall
{
margin: 5%;;
}
#showDaytimes
{
background: #dd3e54; /* fallback for old browsers */
background: -webkit-linear-gradient(to right, #6be585, #dd3e54); /* Chrome 10-25, Safari 5.1-6 */
background: linear-gradient(to right, #6be585, #dd3e54); /* W3C, IE 10+/ Edge, Firefox 16+, Chrome 26+, Opera 12+, Safari 7+ */
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron jumbotron-fluid text-center" style="background-image: url(<?php
if((file_exists('../../images/hall/'.$halldetail[0][5]))&&($halldetail[0][5]!=""))
{
echo "'../../images/hall/".$halldetail[0][5]."'";
}
else
{
echo "https://www.pakvenues.com/system/halls/cover_images/000/000/048/original/Umar_Marriage_Hall_lahore.jpg?1566758537";
}
?>);background-repeat: no-repeat ;background-size: 100% 100%">
<div class="container" style="background-color: white;opacity: 0.7">
<h1 class="display-4"><i class="fas fa-place-of-worship"></i><?php echo $halldetail[0][0]; ?></h1>
<p class="lead">You can control hall setting and also month wise prize list.Prize list consist of per head with food and per head only seating .</p>
<h1 class="text-center"> <a href="../companyRegister/companyEdit.php " class="col-6 btn btn-info "> <i class="fas fa-city mr-2"></i>Edit Company</a></h1>
</div>
</div>
<div class="container row m-auto">
<a href="hallInfo.php?hall=<?php echo $encoded;?>" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-cogs fa-5x"></i><h4> Change info</h4></a>
<a href="galleryhall.php?hall=<?php echo $encoded;?>" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-images fa-5x"></i> <h4> Gallery</h4></a>
<a href="HallprizeLists.php?hall=<?php echo $encoded;?>" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-clipboard-list fa-5x"></i> <h4> Prize list</h4></a>
<a href="comment.php?hall=<?php echo $encoded;?>" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-comments fa-5x"></i> <h4> Comments</h4></a>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-06
* Time: 23:08
*/
include_once ("../connection/connect.php");
if(!isset($_POST['option']))
{
echo "option is not created";
exit();
}
$orderId='';
if(isset($_SESSION['order']))
{
$orderId=$_SESSION['order'];
}
if($_POST['option']=='createDish')
{
$dishId=$_POST['dishId'];
$attributesId=array();
$attributesValue=array();
if(isset($_POST['attributeId']))
{
$attributesId=$_POST['attributeId'];
$attributesValue=$_POST['attributeValue'];
}
$each_price=chechIsEmpty($_POST['each_price']);
$quantity=chechIsEmpty($_POST['quantity']);
$describe=$_POST['describe'];
$CurrentDateTime=date('Y-m-d H:i:s');
$sql='INSERT INTO `dish_detail`(`id`, `describe`, `price`, `expire_date`, `quantity`, `dish_id`, `orderDetail_id`)VALUES(NULL,"'.$describe.'","'.$each_price.'",NULL,"'.$quantity.'",'.$dishId.','.$orderId.')';
querySend($sql);
$dishDetailId=mysqli_insert_id($connect);
for ($i=0;$i<count($attributesId);$i++)
{
$sql='INSERT INTO `attribute_name`(`id`, `quantity`, `attribute_id`, `dish_detail_id`)
VALUES (NULL,"'.$attributesValue[$i].'",'.$attributesId[$i].','.$dishDetailId.')';
querySend($sql);
}
}
else if($_POST["option"]=='attributeChange')
{
$attributeid=$_POST['attributeid'];
$valueAttribute=chechIsEmpty($_POST['value']);
$sql='UPDATE attribute_name as an SET an.quantity ='.$valueAttribute.' WHERE an.id='.$attributeid.'';
querySend($sql);
}
else if($_POST['option']=='dishDetailChange')
{
$dishDetailId=$_POST['dishDetailId'];
$columnName=$_POST['columnName'];
$columnValue=chechIsEmpty($_POST['columnValue']);
$sql='UPDATE dish_detail as dd SET dd.'.$columnName.'="'.$columnValue.'" WHERE dd.id='.$dishDetailId.'';
querySend($sql);
}
else if($_POST['option']=='deleteDish')
{
$dishDetailId=$_POST['dishDetailId'];
$currentDate=date('Y-m-d H:i:s');
$sql='UPDATE dish_detail as dd SET dd.expire_date="'.$currentDate.'" WHERE dd.id='.$dishDetailId.'';
querySend($sql);
}
else if($_POST['option']=="viewmenu")
{
$packageid=$_POST['packageid'];
$sql='SELECT `dishname`, `image` FROM `menu` WHERE (hallprice_id='.$packageid.') AND ISNULL(expire)';
$menu=queryReceive($sql);
$display='<h4 align="center" class="col-12">Menu</h4>';
for ($i=0;$i<count($menu);$i++)
{
$display.='
<div class="col-3 alert-danger shadow border m-2 form-group rounded" style="height: 30vh;" >
<img src="'.substr($menu[$i][1],3).'" class="col-12 " style="height: 15vh">
<p class="col-form-label" class="form-control col-12">'.$menu[$i][0].'</p>
</div>';
}
echo $display;
}<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2020-01-05
* Time: 16:39
*/
setcookie('userid',"" , time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("isOwner","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("username","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("companyid","",time() -(86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("userimage","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie('customerid',"" , time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("typebranch","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("branchtypeid","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("tempid","",time() -(86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("2ndpage","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
setcookie("order","",time() - (86400 * 30), "/",$_SERVER["SERVER_NAME"]);
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 01:51
*/
include_once ("../connection/connect.php");
$sql='SELECT p.id,p.name,ot.destination_date,ot.id FROM person as p INNER join number as n on p.id=n.person_id
INNER join orderTable as ot
on p.id=ot.person_id where ';
if(isset($_POST['p_name']))
{
if($_POST['p_name']!='')
$sql.=' (p.name LIKE "%'.$_POST["p_name"].'%") AND ';
}
if(isset($_POST['p_cnic']))
{
if($_POST['p_cnic']!='')
$sql.=' (p.cnic LIKE "%'.$_POST["p_cnic"].'%") AND ';
}
if(isset($_POST['p_id']))
{
if($_POST['p_id']!='')
$sql.=' (p.id ='.$_POST["p_id"].') AND ';
}
if(isset($_POST['n_number']))
{
if($_POST['n_number']!='')
$sql.=' (n.number LIKE "%'.$_POST["n_number"].'%") AND ';
}
if(isset($_POST['ot_booking_date']))
{
if($_POST['ot_booking_date']!='')
$sql.=' (ot.booking_date = "'.$_POST["ot_booking_date"].'") AND ';
}
if(isset($_POST['ot_destination_date']))
{
if($_POST['ot_destination_date']!='')
$sql.=' (ot.destination_date ="'.$_POST["ot_destination_date"].'") AND ';
}
if(isset($_POST['ot_is_active']))
{
if($_POST['ot_is_active']!='None')
$sql.=' (ot.is_active = '.$_POST["ot_is_active"].') AND ';
}
$sql.=' (p.id IS NOT NULL)
order by
ot.destination_date DESC';
$records=queryReceive($sql);
if(count($records)>0)
{
$displayRecord = '
<div class="form-group row border mb-0 p-1">
<label class="font-weight-bold col-form-label col-2">order Id</label>
<label class="font-weight-bold col-form-label col-5">customer Name</label>
<label class="font-weight-bold col-form-label col-3">destination Date</label>
<label class="font-weight-bold col-form-label col-2">Detail</label>
</div>';
for ($j=0;$j<count($records);$j++)
{
$displayRecord .= ' <div class="form-group row border">
<label class="col-form-label col-2">'.$records[$j][3].'</label>
<label class="col-form-label col-5">'.$records[$j][1].'</label>
<label class="col-form-label col-3">'.$records[$j][2].'</label>
<a href="/Catering/order/PreviewOrder.php?order='.$records[$j][3].'" class="btn-primary col-2 form-control ">Detail</a>
</div>';
}
}
else
{
$displayRecord = '<h2 align="center">Not Found</h2>';
}
echo $displayRecord
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
$order=$_SESSION['order'];
$sql='SELECT od.hallprice_id,(SELECT hp.describe from hallprice as hp WHERE hp.id=od.hallprice_id),(SELECT hp.isFood from hallprice as hp WHERE hp.id=od.hallprice_id),od.catering_id FROM orderDetail as od
WHERE od.id='.$order.'';
$hallpackage=queryReceive($sql);
$cateringid=$hallpackage[0][3];
$sql='SELECT dt.id, dt.name FROM dish_type as dt WHERE ISNULL(dt.isExpire) AND (dt.catering_id='.$cateringid.')';
$dishTypeDetail=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://maunewsonline.uitvconnect.com/wp-content/uploads/2017/10/indian-food.jpg);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 ><i class="fas fa-concierge-bell fa-3x"></i>Select Dishes </h3>
</div>
</div>
<div id="selectmenu" class="alert-info m-2 form-group row shadow" >
</div>
<form class="card-header container border mb-5 " id="formid" method="post" action="dishCreate.php">
<div class="col-12" id="selected">
<div class="form-group row">
<label class="text-center col-form-label col-8"><i class="fas fa-concierge-bell fa-2x col-12"></i>Dish Name</label>
<label class="text-center col-form-label col-3" hidden> <i class="fas fa-sort-amount-up fa-2x col-12"></i>Types</label>
<label class=" text-center col-form-label col-4"><i class="fas fa-trash-alt fa-2x col-12"></i>Delete</label>
</div>
</div>
<div class="form-group row col-12 justify-content-center ">
<?php
/* if(isset($_GET['option']))
{
if($_GET['option']=="orderCreate")
{
echo '<a href="../order/orderEdit.php?order='.$_GET['order'].'&customer='.$_GET['customer'].'&option=dishDisplay" class="col-5 form-control btn btn-danger"><i class="fas fa-arrow-left"></i>Edit Order</a>';
}
else if($_GET['option']=="orderEdit")
{
echo '<button id="cancelDish" type="button" class="col-5 btn btn-danger form-control"><i class="fas fa-arrow-left"></i>Edit order</button>';
}
}
else
{
echo '<button id="cancelDish" type="button" class="col-5 btn btn-danger form-control"><i class="fas fa-arrow-left"></i>Edit order</button>';
}*/
//10
//13
?>
<!-- <button id="cancelDish" type="button" class="col-5 btn btn-danger form-control"><i class="fas fa-arrow-left"></i>Edit order</button>
-->
<a href="../order/orderEdit.php" type="button" class="col-6 btn btn-danger form-control"><i class="fas fa-arrow-left"></i>Edit order</a>
<button id="submit" type="submit" class="btn-success form-control btn col-6"><i class="fas fa-check "></i>Submit</button>
</div>
</form>
<div class="container">
<?php
$display='';
for($i=0;$i<count($dishTypeDetail);$i++)
{
$display.='<h2 data-dishtype="'.$i.'" data-display="hide" align="center " class="dishtypes col-12 btn-warning"> '.$dishTypeDetail[$i][1].'</h2>';
$sql='SELECT `name`, `id`, `image`, `dish_type_id` FROM `dish` WHERE (dish_type_id='.$dishTypeDetail[$i][0].') AND (ISNULL(isExpire)) AND(catering_id='.$cateringid.')';
$dishDetail=queryReceive($sql);
$display.='<div id="dishtype'.$i.'" class="row" style="display: none">';
for ($j=0;$j<count($dishDetail);$j++)
{
$display .= '
<div class="col-5 m-2 m-sm-auto shadow-lg p-3 bg-white rounded" >';
$image = substr($dishDetail[$j][2], 6);
if(!file_exists($image))
{
$image='https://vector.me/files/images/1/4/145000/icon_food_bowl_plate_dan_outline_symbol_silhouette_cartoon_dish_free_knife_logo_fork_plates_cartoons_spoon_dinner_iammisc_spoons_forks_knives_sendok_garpu_diner_piring.jpg';
}
$display.='<img class="card-img-top " src="'.$image.'" alt="Card image" style="height: 100px" >
<p class="font-weight-bold p-0 card-title col-12
">' . $dishDetail[$j][0] . '</p>
<button type="button" data-dishname="'. $dishDetail[$j][0] .'" data-dishid="'. $dishDetail[$j][1] .'" class="add col-12 mb-0 btn btn-primary">Select</button>
</div>';
}
$display.='</div>';
}
echo $display;
?>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function () {
$(document).on('click','.add',function () {
var dishName=$(this).data("dishname");
var dishId=$(this).data("dishid");
$('#selected').append('\n' +
' <div class="form-group row " id="dishid_'+dishId+'">\n' +
' <h2 class="col-8 border">'+dishName+'</h2>\n' +
' <input type="number" hidden value="1" name="types[]" class="form-control col-3">\n' +
' <input type="number" hidden name="dishid[]" value="'+dishId+'">\n' +
' <button type="button" class="remove border-white form-control col-4 btn-danger" data-dishid="'+dishId+'"><i class="fas fa-trash-alt"></i></button>\n' +
' </div>');
}) ;
$(document).on('click','.remove',function () {
var id=$(this).data("dishid");
$("#dishid_"+id).remove();
});
$("#cancelDish").click(function () {
window.history.back();
return false;
});
$(document).on("click",".dishtypes",function () {
var display=$(this).data("display");
var IdDisplay=$(this).data("dishtype");
if(display=="hide")
{
$("#dishtype"+IdDisplay).show('slow');
$(this).data("display","show");
}
else
{
$("#dishtype"+IdDisplay).hide('slow');
$(this).data("display","hide");
}
});
function menushow(packageid,describe)
{
var formdata = new FormData;
formdata.append("packageid", packageid);
formdata.append("option", "viewmenu");
$.ajax({
url: "dishServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!="")
{
$("#selectmenu").html('<h1 align="center" class=\'col-12\'>Package Menu</h1>');
$("#selectmenu").append(data);
$("#selectmenu").append("<h3 align='center' class='col-12'>Menu Description</h3><p class='col-12'>" + describe + "</p>");
}
}
});
}
<?php
if($hallpackage[0][2]==1)
{
echo 'menushow(' . $hallpackage[0][0] . ',' . $hallpackage[0][1] . ');';
}
?>
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
if(!isset($_SESSION['customer']))
{
header("location:CustomerCreate.php");
}
$customerId="";
$customerId=$_SESSION['customer'];
$hallid="";
$cateringid='';
if(isset($_SESSION['typebranch']))
{
if($_SESSION['typebranch']=="hall")
{
$hallid=$_SESSION['branchtypeid'];
}
else
{
$cateringid=$_SESSION['branchtypeid'];
}
}
$sql = "SELECT `name`, `cnic`, `id`, `date`, `image` FROM `person` WHERE id=".$customerId."";
$person=queryReceive($sql);
$sql = "SELECT a.id, a.address_city, a.address_town, a.address_street_no, a.address_house_no, a.person_id FROM address as a inner JOIN person p ON a.person_id=p.id
WHERE a.person_id=$customerId
ORDER by a.person_id;";
$address=queryReceive($sql);
$sql="SELECT n.number, n.id, n.is_number_active, n.person_id FROM number as n inner JOIN person as p ON p.id=n.person_id
WHERE p.id=$customerId
order BY n.id";
$numbers=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(https://www.livechatinc.com/wp-content/uploads/2017/01/customer-centric@2x.png);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-body text-center" style="opacity: 0.7 ;background: white;">
<h3 ><i class="fas fa-user-edit"></i>Edit Customer info </h3>
</div>
</div>
<form id="changeImage" class="col-12 row justify-content-center" style="margin-top: -60px">
<?php
echo '<input name="customerid" hidden value="'.$customerId.'">';
?>
<input name="image" hidden value="<?php echo $person[0][4] ?>">
<img src="<?php
if(file_exists('../images/customerimage/'.$person[0][4])&&($person[0][4]!=""))
{
echo '../images/customerimage/'.$person[0][4];
}
else
{
echo 'https://www.pavilionweb.com/wp-content/uploads/2017/03/man-300x300.png';
}
?> " style="height: 30vh;" class="img-thumbnail figure-img rounded-circle" alt="image is not set">
<div class="form-group row col-12 justify-content-center ">
<label class="form-check-label ">change image:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input name="image" id="submitImage" type="file" class="form-control">
</div>
</div>
</form>
<div class="container card-body" >
<form id="form" >
<?php
echo '<input id="customerId" type="number" hidden value="'.$customerId.'">';
?>
<div id="number_records">
<?php
for($i=0;$i<count($numbers);$i++)
{
echo '
<div class="form-group row" id="Each_number_row_'.$numbers[$i][1].'">
<label class="col-form-label" for="number_'.$numbers[$i][1].'">Phone no:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-phone-volume"></i></span>
</div>
<input class=" numberchange allnumber form-control " type="text" name="number[]" value="'.$numbers[$i][0].'" id="number_'.$numbers[$i][1].'" data-columne="number" data-columneid='.$numbers[$i][1].'>
<input class="form-control btn btn-danger remove_number col-3 " id="remove_numbers_'.$numbers[$i][1].'" data-removenumber="'.$numbers[$i][1].'" value="-">
</div>
</div>';
}
?>
</div>
<div class="form-group row" >
<label for="newNumber" class="col-form-label">New Number</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-mobile-alt"></i></span>
</div>
<input id="newNumber" name="newNumber"class="form-control" placeholder="New number 092xxxxx" >
<input type="button" value="+" class="col-3 btn-success form-control" id="newadd">
</div>
</div>
<div class="form-group row">
<label for="name" class="col-form-label"> Name:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user"></i></span>
</div>
<?php
echo'<input type="text" id="name" name="name" class=" personchange form-control" value="'.$person[0][0].'" data-columne="name">';
?>
</div>
</div>
<div class="form-group row">
<label for="cnic" class="col-form-label "> CNIC:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-id-card"></i></span>
</div>
<?php
echo '
<input type="number" id="cnic" name="cnic" class=" personchange form-control " value="'.$person[0][1].'" data-columne="cnic">';
?>
</div>
</div>
<h3 align="center"> <i class="fas fa-map-marker-alt"></i>Address(optional)</h3>
<div class="form-group row">
<label for="city" class="col-form-label"> City:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-city"></i></span>
</div>
<?php
echo '<input type="text" id="city" name="city" class=" addresschange form-control" value="'.$address[0][1].'" data-columne="address_city">';
?>
</div>
</div>
<div class="form-group row">
<label for="area" class="col-form-label "> Area/ Block:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-road"></i></span>
</div>
<?php
echo '<input type="text" id="area" name="area" class=" addresschange form-control " value="'.$address[0][2].'" data-columne="address_town">';
?>
</div>
</div>
<div class="form-group row">
<label for="streetNo" class="col-form-label ">Street No :</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-street-view"></i></span>
</div>
<?php
echo ' <input type="number" id="streetNo" name="streetNo" class=" addresschange form-control" value="'.$address[0][3].'" data-columne="address_street_no">';
?>
</div>
</div>
<div class="form-group row">
<label for="houseNo" class="col-form-label ">House No:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-home"></i></span>
</div>
<?php
echo '<input type="number" id="houseNo" name="houseNo" class=" addresschange form-control" value="'.$address[0][4].'" data-columne="address_house_no">';
?>
</div>
</div>
<div class="col-12 shadow">
<h4 align="center"><i class="fas fa-user-tag mr-2"></i>Customer personality</h4>
<?php
$sql='SELECT py.personality,py.rating FROM person as p INNER join orderDetail as od
on p.id=od.person_id
INNER JOIN payment as py
on od.id=py.orderDetail_id
WHERE
p.id='.$customerId.'';
$personalitydetails=queryReceive($sql);
for ($k=0;$k<count($personalitydetails);$k++)
{
echo '
<p class=" mb-3 form-control">'.$personalitydetails[$k][0].' <span class="float-right border-danger border font-weight-bold">Rating: '.$personalitydetails[$k][1].' </span> </p>';
}
?>
</div>
<div class="form-group row mb-3 p-4">
<?php
/* if(isset($_GET['option']))
{
if($_GET['option']=="orderCreate")
{
echo '
<a href="CustomerCreate.php" class="col-6 form-control btn btn-danger" id="cancel">Not this customer</a>
<a href="../order/orderCreate.php?customer='.$customerId.'" class="col-6 form-control btn btn-outline-primary" id="submit"><i class="fas fa-check "></i>Next</a>';
}
else if(($_GET['option']=="orderCreate") || ($_GET['option']=="CustomerCreate"))
{
echo '
<a href="CustomerCreate.php?option=customerEdit" class="col-6 form-control btn btn-danger" id="cancel">Not this customer</a>
<a href="../order/orderCreate.php?customer='.$customerId.'&option=customerEdit" class="col-6 form-control btn btn-outline-primary" id="submit">Order Create</a>';
}
else if($_GET['option']=="customerAndOrderalreadyHave")
{
echo '
<a href="CustomerCreate.php" class="col-6 form-control btn btn-danger" id="cancel">Not this customer</a>
<a href="../order/orderEdit.php?order='.$_GET['order'].'&customer='.$_GET['customer'].'&option=customerEdit" class="m-auto col-6 form-control btn btn-primary" id="submit">Edit order</a>';
}
else if($_GET['option']=="PreviewOrder")
{
echo '<input type="button" id="btnbackhistory" class="m-auto col-6 form-control btn btn-primary" value="Done">';
}
else if($_GET['option']=="hallorder")
{
echo '
<a href="../company/hallBranches/hallorder.php?customer='.$customerId.'&hallid='.$_GET['hallid'].'" class="btn btn-warning m-auto col-6"><i class="fas fa-check "></i>Done</a>';
}
else if($_GET['option']=="hallCustomer")
{
echo '
<input type="button" id="btnbackhistory" class="m-auto col-6 form-control btn btn-danger" value="Not this Customer">
<a href="../company/hallBranches/hallorder.php" class="btn btn-success m-auto col-6"><i class="fas fa-check "></i>Done</a>';
}
}*/
if(isset($_GET['action']))
{
echo '
<a href="../order/PreviewOrder.php" class="m-auto col-6 form-control btn btn-danger"><i class="fas fa-check "></i> Done</a>';
}
else if($_SESSION['branchtype']=="hall")
{
//hall
if(!isset($_SESSION['order']))
{
//16 new order of hall
echo '
<a href="CustomerCreate.php" class="m-auto col-6 form-control btn btn-danger"><i class="fas fa-window-close"></i> Not this Customer</a>
<a href="../company/hallBranches/hallorder.php" class="btn btn-success m-auto col-6"><i class="fas fa-check "></i>Create hall order</a>
';
}
else
{
}
}
else
{
//catering
if(!isset($_SESSION['order']))
{
//not order create
//7 go to create order of catering
echo '
<a href="CustomerCreate.php" class="m-auto col-6 form-control btn btn-danger"><i class="fas fa-window-close"></i> Not this Customer</a>
<a href="../order/orderCreate.php" class="col-6 form-control btn btn-outline-primary" id="submit"><i class="fas fa-check "></i> Order Create</a>
';
}
else
{
//order of catering is created
//15 oder of catering edit
echo '
<a href="CustomerCreate.php" class="m-auto col-6 form-control btn btn-danger"><i class="fas fa-window-close"></i> Not this Customer</a>
<a href="../order/orderEdit.php" class="m-auto col-6 form-control btn btn-primary"><i class="fas fa-check "></i> Edit order</a>';
}
}
//6 not this customer
?>
</div>
</form>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
var customerid=$("#customerId").val();
function execute_person_address(column,text,type)
{
$.ajax({
url: "customerEditServer.php",
data:{columnname:column,value:text,edittype:type,option:"change",customerid:customerid},
dataType:"text",
method:"POST",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
}
}
});
}
function execute_number(column,text,type,id)
{
$.ajax({
url: "customerEditServer.php",
data:{columnname:column,value:text,edittype:type,id:id,option:"change",customerid:customerid},
dataType:"text",
method:"POST",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='') {
alert(data);
}
}
});
}
$(document).on('change','.addresschange',function () {
//address change
var column=$(this).data("columne");
var text=$(this).val();
execute_person_address(column,text,1);
});
$(document).on('change','.personchange',function () {
//personchange change
var column=$(this).data("columne");
var text=$(this).val();
execute_person_address(column,text,2);
});
$(document).on('change','.numberchange',function () {
//numberchange change
var column=$(this).data("columne");
var id=$(this).data("columneid");
var text=$(this).val();
execute_number(column,text,3,id);
});
$("#newadd").click(function ()
{
var numberText=$('#newNumber').val();
$.ajax({
url: "customerEditServer.php",
data:{option:"addNumber",number:numberText,customerid:customerid},
dataType:"text",
method:"POST",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
}
else
{
location.reload()
}
}
});
});
$(document).on("click",".remove_number",function () {
var id=$(this).data("removenumber");
$.ajax({
url: "customerEditServer.php",
data:{ id:id,option:"deleteNumber"},
dataType:"text",
method:"POST",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
}
else
{
$("#Each_number_row_"+id).remove();
}
}
});
});
$("#submitImage").change(function () {
var formData=new FormData($("#changeImage")[0]);
formData.append("option","changeImage");
$.ajax({
url:"customerEditServer.php",
method:"POST",
data:formData,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
}
else
{
location.reload();
}
}
});
});
$("#btnbackhistory").click(function () {
window.history.back();
});
});
</script>
</body>
</html>
<file_sep><?php
include_once ('../../connection/connect.php');
$hallid=$_GET['hallid'];
$companyid=$_GET['companyid'];
$hallBranches=$_GET['hallBranches'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0;
padding: 0;
}
</style>
</head>
<body class="container">
<h1 align="center">Setting OF Hall</h1>
<div class="form-group row ">
<div data-daytime="Morning" class="col-4 daytime "style="height: 25vh">
<div class="card-header">
<img src="../../gmail.png" style="height: 20vh;width: 100%">
<p align="center" >Morning Prize list</p>
</div>
</div>
<div data-daytime="Afternoon" class=" daytime col-4"style="height: 25vh">
<div class="card-header">
<img src="../../gmail.png" style="height: 20vh;width: 100%">
<p align="center" >Afternoon Prize list</p>
</div>
</div>
<div data-daytime="Evening" class=" daytime col-4"style="height: 25vh">
<div class="card-header">
<img src="../../gmail.png" style="height: 20vh;width: 100%">
<p align="center" >Evening Prize list</p>
</div>
</div>
</div>
<div class="shadow" id="showDaytimes" style="margin-top: 20%;width: 100%">
</div>
<div class="form-group row">
<a href="hallRegister.php?companyid=<?php echo $companyid;?>&hallBranches=<?php echo $hallBranches;?>" class="btn btn-outline-success col-5"> Save And Next </a>
</div>
<!---->
<!--<tr>-->
<!-- <td scope="col" >-->
<!-- <h4 align="center">Months</h4>-->
<!-- <div class="form-group row p-2 shadow btn-light">-->
<!-- <label class="col-form-label col-6 font-weight-bold"> Prize Only Seating </label>-->
<!-- <input class="form-control col-6" type="number">-->
<!-- <h3 align="center" class="col-12 mt-3">List of prize with Food</h3>-->
<!-- <a href="#" class="form-control btn-primary col-12 text-center"> Add New Package</a>-->
<!-- <a href="#" class="form-control btn-success col-4 text-center m-2"> Package name</a>-->
<!-- </div>-->
<!-- </td>-->
<!--</tr>-->
<script>
$(document).ready(function ()
{
$(".daytime").click(function ()
{
var daytime=$(this).data("daytime");
var formdata=new FormData();
formdata.append("option","showdaytimelist");
formdata.append("daytime",daytime);
formdata.append("hallid",<?php echo $hallid; ?>);
formdata.append("companyid",<?php echo $companyid;?>);
formdata.append("hallBranches",<?php echo $hallBranches;?>)
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
$("#showDaytimes").html(data);
}
});
}) ;
$(document).on("change",".changeSeating",function () {
var id=$(this).data("menuid");
var value=$(this).val();
var formdata=new FormData();
formdata.append("option","changeSeating");
formdata.append("packageid",id);
formdata.append("value",value);
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
return false;
}
}
});
}) ;
});
</script>
</body>
</html>
<file_sep><?php
include_once ("../../connection/connect.php");
$month=$_GET['month'];
$daytime=$_GET['daytime'];
$hallid=$_GET['hallid'];
$companyid=$_GET['companyid'];
$hallBranches=$_GET['hallBranches'];
$sql='SELECT name,id FROM systemDishType WHERE ISNULL(isExpire)';
$dishtype=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0;
padding: 0;
}
</style>
</head>
<body>
<h1 align="center">Add new Package</h1>
<form id="submitpackage">
<?php
echo '<input hidden type="text" name="month" value="'.$month.'">
<input hidden type="text" name="daytime" value="'.$daytime.'">
<input hidden type="text" name="hallid" value="'.$hallid.'">
';
?>
<div class="form-group row">
<lable class="col-4 col-form-label">Packages Name</lable>
<input name="packagename" class="col-8 form-control" type="text">
</div>
<div class="form-group row">
<lable class="col-4 col-form-label">Packages Rate per head</lable>
<input name="rate" class="col-3 form-control" type="number">
</div>
<div class="form-group row">
<lable class="col-4 col-form-label">Packages Description</lable>
<textarea name="describe" class="col-6 form-control" ></textarea>
</div>
<h3 align="center"> Selected Menu of Package</h3>
<div id="selectedmenu" class="alert-warning row form-group shadow" style="height: 40vh">
</div>
<div class="col-12">
<input id="btncancel" type="button" value="Cancel" class="btn btn-danger col-4">
<input id="btnsubmit" type="button" value="Submit" class="btn btn-primary col-4">
</div>
</form>
<h3 align="center" class="mt-5">Select Dishes</h3>
<div id="selectmenu" class="alert-dark border m-2 form-group row shadow" >
<?php
for ($i=0;$i<count($dishtype);$i++)
{
$sql = 'SELECT `name`, `id`, `image` FROM `systemDish` WHERE ISNULL(isExpire) AND (systemDishType_id=' . $dishtype[$i][1] . ') ';
$dishdetail=queryReceive($sql);
for ($j=0;$j<count($dishdetail);$j++)
{
echo '
<div id="dishid'.$dishdetail[$j][1].'" class="col-3 alert-danger border m-2 form-group" style="height: 30vh;" >
<img src="'.$dishdetail[$j][2].'" class="col-12" style="height: 15vh">
<p class="col-form-label" class="form-control col-12">'.$dishdetail[$j][0].'</p>
<input data-dishid="'.$dishdetail[$j][1].'" type="button" value="Select" class="form-control col-12 touchdish btn btn-success">
<input hidden type="text" name="dishname[]" value="'.$dishdetail[$j][0].'">
<input hidden type="text" name="image[]" value="'.$dishdetail[$j][2].'">
</div>';
}
}
?>
</div>
<script>
$(document).ready(function () {
$(document).on("click",".touchdish",function ()
{
var value=$(this).val();
var id=$(this).data("dishid");
if(value=="Remove")
{
$(this).val("Select");
var text=$("#dishid"+id)[0].outerHTML;
$("#dishid"+id).remove();
$("#selectmenu").append(text);
}
else
{
$(this).val("Remove");
var text=$("#dishid"+id)[0].outerHTML;
$("#dishid"+id).remove();
$("#selectedmenu").append(text);
}
}) ;
$("#btnsubmit").click(function ()
{
var formdata=new FormData($('#submitpackage')[0]);
formdata.append("option","CreatePackage");
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!='')
{
alert(data);
}
else
{
window.history.back();
}
}
});
});
$("#btncancel").click(function () {
window.history.back();
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-05
* Time: 17:56
*/
include_once ("../connection/connect.php");
$userid=$_COOKIE['userid'];
if(!isset($_POST['function'])) //add customer
{
echo "option in order is not created";
exit();
}
if($_POST['function']=="add") {
$customerId=$_POST['customer'];
$cateringid=$_POST['cateringid'];
$persons = chechIsEmpty($_POST['persons']);
$time = '';
if (empty($_POST['time'])) {
$time = "NULL";
} else {
$time = '"' . $_POST['time'] . '"';
}
$date = '';
if (empty($_POST['date'])) {
$date="NULL";
}
else
{
$date='"'.$_POST['date'].'"';
}
$area=$_POST['area'];
$streetno=chechIsEmpty($_POST['streetno']);
$houseno=chechIsEmpty($_POST['houseno']);
$describe=$_POST['describe'];
$currentDate=date('Y-m-d');
$CurrenttimeDate = date('Y-m-d H:i:s');
$sql='INSERT INTO `address`(`id`, `address_street_no`, `address_house_no`, `person_id`, `address_city`, `address_town`) VALUES (NULL,"'.$streetno.'","'.$houseno.'","'.$customerId.'","lahore","'.$area.'")';
querySend($sql);
$address_id=mysqli_insert_id($connect);
$sql='INSERT INTO `orderDetail`(`id`, `hall_id`, `catering_id`, `hallprice_id`,
`user_id`, `sheftCatering`, `sheftHall`, `sheftCateringUser`, `sheftHallUser`,
`address_id`, `person_id`,
`total_amount`, `total_person`, `status_hall`, `destination_date`, `booking_date`,
`destination_time`, `status_catering`, `notice`,`describe`) VALUES
(NULL,NULL,'.$cateringid.',NULL,'.$userid.',NULL,NULL,NULL,
NULL,'.$address_id.','.$customerId.',0,'.$persons.',NULL,'.$date.',"'.$currentDate.'",
'.$time.',"Running","","'.$describe.'")';
querySend($sql);
$ordeID=mysqli_insert_id($connect);
$_SESSION['order']=$ordeID;
}
?><file_sep>
<?php
include_once ("connect.php");
include_once ("findDistance.php");
function hallAll()
{
$hallIds=SortDistance(33.6844,73.0479,"Pakistan");
$monthsArray = array('January', 'February', 'March', 'April', 'May', 'June', 'July', 'August', 'September', 'October', 'November', 'December');
$currentdate=date("Y/m/d");
$maxDate = new DateTime('now');
$maxDate->modify('+1 month'); // or you can use '-90 day' for deduct
$NextMonthNo=$maxDate->format('m');
$NextMonthNo=$NextMonthNo-1;
$maxDate = $maxDate->format('Y-m-d');
$CurrentMonthNo=date('m');
$CurrentMonthNo=$CurrentMonthNo-1;
$display='';
for($i=0;$i<count($hallIds);$i++)
{
$sql = 'SELECT h.id,h.image,h.name,h.max_guests,hp.id,hp.month,hp.isFood,hp.price,hp.dayTime,hp.package_name,h.hallType FROM hall as h INNER join hallprice as hp
ON
(h.id=hp.hall_id)
left join orderDetail as od on (h.id=od.hall_id)
WHERE
(h.id='.$hallIds[$i][0].')AND
((od.hall_id IS NULL) or ((od.status_hall="Cancel")AND
(od.destination_date between "' . $currentdate . '" AND "' . $maxDate . '" ))) AND (ISNULL(h.expire)) AND
((ISNULL(hp.expire)) AND ((hp.month="' . $monthsArray[$CurrentMonthNo] . '")or (hp.month="' . $monthsArray[$NextMonthNo] . '"))) limit 20
';
$display.=showHalls($sql,$hallIds[$i][3]);
}
return $display;
}
function HallUserDesire($currentdate,$perHead,$dayTime)
{
$time=$dayTime;
if($dayTime=="09:00:00")
$dayTime="Morning";
else if($dayTime=="12:00:00")
$dayTime="Afternoon";
else
$dayTime="Evening";
$hallIds=SortDistance(33.6844,73.0479,"Pakistan");
$monthsArray = array('January', 'February', 'March', 'April', 'May', 'June', 'July', 'August', 'September', 'October', 'November', 'December');
$date=date_create($currentdate);
$CurrentMonthNo=(int) date_format($date,'m')-1;
$display='';
for($i=0;$i<count($hallIds);$i++)
{
$sql = 'SELECT h.id,h.image,h.name,h.max_guests,hp.id,hp.month,hp.isFood,hp.price,hp.dayTime,hp.package_name,h.hallType FROM hall as h INNER join hallprice as hp
ON
(h.id=hp.hall_id)
left join orderDetail as od on (h.id=od.hall_id)
WHERE
(h.id='.$hallIds[$i][0].')AND(hp.isFood='.$perHead.')AND
((od.hall_id IS NULL) or ((od.status_hall="Cancel")AND
(od.destination_date="'.$currentdate.'" ) AND od.destination_time="'.$time.'")) AND (ISNULL(h.expire)) AND
((ISNULL(hp.expire)) AND (hp.month="' . $monthsArray[$CurrentMonthNo] . '")AND (hp.month="' . $monthsArray[$CurrentMonthNo] . '")AND (hp.dayTime="'.$dayTime.'")) limit 20
';
$display.=showHalls($sql,$hallIds[$i][3]);
}
return $display;
}
function showHalls($sql,$Distance)
{
$halltype=array("Marquee","Hall","Deera /Open area");
$display = '';
$AllHalls=queryReceive($sql);
for ($i=0;$i<count($AllHalls);$i++)
{
$display.='
<a href="company/hallBranches/hallclient.php?hallid='.$AllHalls[$i][0].'&packageid='.$AllHalls[$i][4].'&date='.$AllHalls[$i][5].'&time='.$AllHalls[$i][8].'" class="card-header transparencyjumbo col-sm-11 col-md-6 col-xl-4">
<!-- Card image -->
<div class="view overlay">
<div class="container pictures">
<img src="';
if(file_exists('images/hall/'.$AllHalls[$i][1]) &&($AllHalls[$i][1]!=""))
{
$display.="images/hall/".$AllHalls[$i][1];
}
else
{
$display.='https://thumbs.dreamstime.com/z/wedding-hall-decoration-reception-party-35933352.jpg';
}
$display.='" alt="Snow" style="width:100%;height: 100%">
<h5 class="top-right text-dark font-weight-bold"> ';
$display.=$Distance;
$display.=' Km</h5>
</div>
</div>
<!-- Card content -->
<div class="card-body">
<!-- Title -->
<h4 class="card-title font-weight-bold text-center"> '.$AllHalls[$i][2].'</h4>
<!-- Data -->
<span class="fa fa-star checked"></span>
<span class="fa fa-star checked"></span>
<span class="fa fa-star checked"></span>
<span class="fa fa-star"></span>
<span class="fa fa-star"></span>
<h3 class="text-right"><i class="far fa-money-bill-alt"></i><span class="font-weight-bold"> RS:<i class="text-warning"> '.$AllHalls[$i][7].' </i></span></h3>
<h4><i class="fas fa-clock"></i> Time <span class="text-warning">'.$AllHalls[$i][8].'</span> </h4>
<h4><i class="far fa-calendar-alt"></i> Month <span class="text-warning">'.$AllHalls[$i][5].'</span></h4>
<h4><i class="fas fa-users"></i> Max Guests <span class="text-warning">'.$AllHalls[$i][3].'</span></h4>
<h4><i class="fab fa-accusoft"></i> Hall Type: <span class="text-warning">'.$halltype[$AllHalls[$i][10]].'</span></h4>';
if( $AllHalls[$i][6]==0)
{
$display.='
<h4><i class="material-icons">airline_seat_recline_normal</i> <span class="text-warning">with Seating</span></h4>';
}
else
{
$display.='
<h4><i class="material-icons">fastfood</i> package name <span class="text-warning">'.$AllHalls[$i][9].'</span></h4>';
}
$display.='</div>
</a>';
}
return $display;
}
?>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../connection/connect.php");
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<div class="container" style="margin-top:150px">
<h1 class="font-weight-bold " align="center">System Dish info </h1>
<div class="col-12 card shadow mb-3 p-5">
<h3 align="center"> Dish Type information</h3>
<div class="form-group row font-weight-bold border">
<label class="col-9 col-form-label ">Name Dish type</label>
<label class="col-3 col-form-label ">Detail</label>
</div>
<?php
$sql='SELECT `id`, `name`, `isExpire` FROM `systemDishType` WHERE 1';
$dishTypes=queryReceive($sql);
$Display='';
for($i=0;$i<count($dishTypes);$i++)
{
$Display.= '<div class="form-group row border " id="Delele_Dish_Type_'.$dishTypes[$i][0].'">
<input data-dishtypeid="'.$dishTypes[$i][0].'" value="'.$dishTypes[$i][1].'" class="changeDishType col-9 form-control ">
<input data-dishtypeid="'.$dishTypes[$i][0].'" class=" btn Delele_Dish_Type col-3 form-control ';
if($dishTypes[$i][2]=="")
{
$Display.='btn-primary ';
}
else
{
$Display.=' btn-danger ';
}
$Display.=' " value="';
if($dishTypes[$i][2]=="")
{
$Display.='Disable';
}
else
{
$Display.='Enable';
}
$Display.= '"></div>';
}
echo $Display;
?>
</div>
<div class="col-12 card shadow mb-2 p-4 ">
<h3 align="center"> Dish information <a href="addDish.php" class=" btn-outline-primary btn form-control ">Add dish +</a>
</h3>
<?php
$sql='SELECT d.name, d.id, (SELECT dt.name from systemDishType as dt WHERE dt.id=d.systemDishType_id),(SELECT dt.isExpire from systemDishType as dt WHERE dt.id=d.systemDishType_id), d.isExpire,d.image FROM systemDish as d WHERE 1 ';
$Dishes=queryReceive($sql);
$display='<div class="form-group row">';
for($i=0;$i<count($Dishes);$i++)
{
$display.= '<div class="card col-4">
<img src="'.$Dishes[$i][5].'" style="height: 20vh">
<label class="col-12 form-check-label" > '.$Dishes[$i][0].'</label>
<a href="EditDish.php?dishid='.$Dishes[$i][1].'" class="col-12 form-control btn ';
if(($Dishes[$i][3]=="")&&($Dishes[$i][4]==""))
{
$display.=" btn-primary ";
}
else
{
$display.=" btn-danger ";
}
$display.='">';
if($Dishes[$i][3]!="")
{
$display.=$Dishes[$i][2]." Diable ";
}
if($Dishes[$i][4]!="")
{
$display.=" Dish Diable ";
}
if(($Dishes[$i][3]=="")&&($Dishes[$i][4]==""))
{
$display.=" Detail ";
}
$display.='</a>
</div>';
}
$display.='</div>';
echo $display;
?>
</div>
</div>
<script>
$(document).ready(function () {
$(document).on("change",".changeDishType",function ()
{
var id=$(this).data("dishtypeid");
var value=$(this).val();
$.ajax({
url:"dishServer.php",
data:{id:id,value:value,option:"changeDishType"},
dataType:"text",
method:"POST",
success:function (data)
{
if(data!="")
{
alert(data);
}
}
});
});
$(document).on("click",".Delele_Dish_Type",function ()
{
var id=$(this).data("dishtypeid");
var value=$(this).val();
$.ajax({
url:"dishServer.php",
data:{value:value,id:id,option:"Delele_Dish_Type"},
dataType:"text",
method:"POST",
success:function (data)
{
if(data!="")
{
alert(data);
}
else
{
location.reload();
}
}
});
});
});
</script>
</body>
</html><file_sep>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<style>
form
{
margin: 5%;
font-weight: bold;
}
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="jumbotron shadow " style="background-image: url(https://i2.wp.com/findlawyer.com.ng/wp-content/uploads/2018/05/Pros-and-Cons-of-Working-at-Large-Companies.jpg?resize=1024%2C512&ssl=1);background-size:100% 115%;background-repeat: no-repeat;">
<div class="text-center transparencyjumbo">
<h1 class="text-center"><i class="fas fa-registered"></i> Free Company Register</h1>
</div>
</div>
<div class="container">
<div class="transparencyinputs">
<form>
<div class="form-group row">
<label class="form-check-label">Company Name</label>
<!-- <input id="companyName" class="form-control" type="text" name="companyName">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text" ><i class="fas fa-building"></i>
</span>
</div>
<input placeholder="Your Company Name" id="companyName" class="form-control" type="text" name="companyName">
</div>
</div>
<div class="form-group row">
<label for="username" class="col-form-label ">User Name</label>
<!-- <input type="text" id="username" name="username" class="form-control ">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-user"></i></span>
</div>
<input placeholder="<NAME>" type="text" id="username" name="username" class="form-control">
</div>
</div>
<div class="form-group row">
<label for="password" class="col-form-label ">Password</label>
<!-- <input type="text" id="password" name="password" class="form-control ">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-key"></i></span>
</div>
<input placeholder="<PASSWORD>" type="text" id="password" name="password" class="form-control">
</div>
</div>
<div class="form-group row">
<label for="password1" class="col-form-label ">Confirm Password</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-key"></i></span>
</div>
<input type="text" id="<PASSWORD>" name="password1" class="form-control" placeholder="Confirm password">
</div>
</div>
<div class="form-group row">
<label for="number" class="col-form-label">Phone no:</label>
<!-- <input type="number" id="number" class="allnumber form-control col-8" name="number[]" >-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-phone-volume"></i></span>
</div>
<input placeholder="Phone no" id="number" type="number" class="form-control allnumber" name="number[]">
<input type="button" class="col-3 btn-primary" id="Add_btn" value="+">
</div>
</div>
<div class="col-12" id="number_records">
</div>
<div class="form-group row">
<label for="name" class="col-form-label"> Name:</label>
<!-- <input type="text" id="name" name="name" class="form-control " >-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-address-book"></i></span>
</div>
<input placeholder="<NAME>" type="text" id="name" name="name" class="form-control">
</div>
</div>
<div class="form-group row">
<label for="name" class="col-form-label">Image:</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-camera"></i></span>
</div>
<input type="file" name="image" class="form-control" >
</div>
</div>
<div class="form-group row">
<label for="cnic" class="col-form-label "> CNIC:</label>
<!-- <input type="number" id="cnic" name="cnic" class="form-control" >-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="far fa-id-card"></i></span>
</div>
<input placeholder="your CNIC" type="number" id="cnic" name="cnic" class="form-control">
</div>
</div>
<h3 align="center"><i class="fas fa-map-marker-alt"></i> Address (optional)</h3>
<div class="form-group row">
<label for="city" class="col-form-label "> City:</label>
<!-- <input type="text" id="city" name="city" class="form-control " >-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-city"></i></span>
</div>
<input placeholder="City" type="text" id="city" name="city" class="form-control">
</div>
</div>
<div class="form-group row">
<label for="area" class="col-form-label "> Area/ Block:</label>
<!-- <input type="text" id="area" name="area" class="form-control ">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-road"></i></span>
</div>
<input placeholder="Area/ Block" type="text" id="area" name="area" class="form-control">
</div>
</div>
<div class="form-group row">
<label for="streetNo" class="col-form-label ">Street No :</label>
<!-- <input type="number" id="streetNo" name="streetNo" class="form-control">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-street-view"></i></span>
</div>
<input placeholder="Street No" type="number" id="streetNo" name="streetNo" class="form-control">
</div>
</div>
<div class="form-group row">
<label for="houseNo" class="col-form-label ">House No:</label>
<!-- <input type="number" id="houseNo" name="houseNo" class="form-control">-->
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-home"></i></span>
</div>
<input placeholder="House No" type="number" id="houseNo" name="houseNo" class="form-control">
</div>
</div>
<div class="form-group row">
<button class="col-6 form-control btn btn-danger" id="cancelCustomer"><i class="fas fa-window-close"></i>Cancel</button>
<button class="col-6 form-control btn btn-outline-primary" id="submit"><i class="fas fa-check "></i>Submit</button>
</div>
</form>
</div>
</div>
<!--
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text">Large</span>
</div>
<input type="text" class="form-control">
</div>-->
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
var number=0;
$('.number_records').map(function () {
number++;
}).get().join();
$("#Add_btn").click(function ()
{
if(number>1)
{
alert("no of numbers not more then 3");
return false;
}
$("#number_records").append("<div class=\"form-group row\" id=\"Each_number_row_"+number+"\">\n" +
" <label for=\"number_"+number+"\" class=\"col-2 col-form-label\">Phone no:</label>\n" +
" <input id=\"number_"+number+"\" class=\"allnumber form-control col-8\" type=\"number\" name=\"number[]\">\n" +
" <input class=\"form-control btn btn-danger col-2 remove_number \" id=\"remove_numbers_"+number+"\" data-removenumber=\""+number+"\" value=\"-\">\n" +
" </div>");
number++;
});
$(document).on("click",".remove_number",function () {
var id=$(this).data("removenumber");
$("#Each_number_row_"+id).remove();
number--;
});
$("#submit").click(function (e)
{
e.preventDefault();
if(!(($("#username").val().length>5) && ($("#username").length<9)))
{
alert("Username must be 6 to 8 letters");
return false;
}
if(!(($("#password").val().length>5) && ($("#password").length<9)))
{
alert("password must be 6 to 8 letters");
return false;
}
if($("#password1").val()!=($("#password").val()))
{
alert("password does not match");
return false;
}
if($.trim($("#number").val())=="")
{
alert("number must be enter");
return false;
}
if($.trim($("#name").val())=="")
{
alert("name must be enter");
return false;
}
var formdata=new FormData($('form')[0]);
formdata.append("option","createUser");
$.ajax({
url:"../companyServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
success:function (data)
{
if(data!="")
{
alert(data);
return false;
}
else
{
window.location.href='companydisplay.php';
}
}
});
});
});
</script>
</body>
</html><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 01:51
*/
include_once ("../connection/connect.php");
$sql='SELECT DISTINCT ot.id, (SELECT p.name FROM person as p WHERE p.id=ot.person_id), (SELECT sum(py.amount) FROM payment as py WHERE (py.IsReturn=0)AND(py.orderTable_id=ot.id)) ,ot.extre_charges,ot.total_amount, (SELECT SUM(dd.price*dd.quantity) FROM dish_detail as dd WHERE dd.orderTable_id=ot.id) FROM person as p INNER JOIN orderTable as ot
on p.id=ot.person_id
LEFT join payment as py on ot.id=py.orderTable_id WHERE ';
if(isset($_POST['p_name']))
{
if($_POST['p_name']!='')
$sql.=' (p.name LIKE "%'.$_POST["p_name"].'%") AND ';
}
if(isset($_POST['p_cnic']))
{
if($_POST['p_cnic']!='')
$sql.=' (p.cnic LIKE "%'.$_POST["p_cnic"].'%") AND ';
}
if(isset($_POST['p_id']))
{
if($_POST['p_id']!='')
$sql.=' (p.id ='.$_POST["p_id"].') AND ';
}
if(isset($_POST['n_number']))
{
if($_POST['n_number']!='')
$sql.=' (n.number LIKE "%'.$_POST["n_number"].'%") AND ';
}
if(isset($_POST['ot_booking_date']))
{
if($_POST['ot_booking_date']!='')
$sql.=' (ot.booking_date = "'.$_POST["ot_booking_date"].'") AND ';
}
if(isset($_POST['ot_destination_date']))
{
if($_POST['ot_destination_date']!='')
$sql.=' (ot.destination_date ="'.$_POST["ot_destination_date"].'") AND ';
}
if(isset($_POST['ot_is_active']))
{
if($_POST['ot_is_active']!='None')
$sql.=' (ot.is_active = '.$_POST["ot_is_active"].') AND ';
}
$sql.=' (p.id IS NOT NULL)
order by
ot.destination_date DESC';
$details=queryReceive($sql);
$display='<table class="table table-bordered table-responsive" style="width: 100%;">
<tbody class="font-weight-bold">
<td >order Id</td>
<td>customer Name</td>
<td>received amount</td>
<td>System Amount</td>
<td>remaining system amount </td>
<td>your demanded amount</td>
<td>remaining demand amount</td>
</tbody>';
for ($i=0;$i<count($details);$i++)
{
$display.=' <tr data-orderid="'.$details[$i][0].'" class="orderDetail">
<td >'.$details[$i][0].'</td>
<td>'.$details[$i][1].'</td>
<td>'.(int)$details[$i][2].'</td>
<td>'.(int)$details[$i][5].'</td>
<td> '.(int) ($details[$i][5]-$details[$i][2]).'</td>
<td>'.(int) $details[$i][4].'</td>
<td>'.(int) ($details[$i][4]-$details[$i][2]).'</td>
';
$display.='</tr>';
}
$display.='</table>';
echo $display;
?><file_sep><?php
include_once ("../connection/connect.php");
$hallid='';
$cateringid='';
if(isset($_SESSION['branchtype']))
{
if($_SESSION['branchtype']=="hall")
{
$hallid=$_SESSION['branchtypeid'];
}
else
{
$cateringid=$_SESSION['branchtypeid'];
}
}
else
{
header("location:../company/companyRegister/companydisplay.php");
}
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<?php
$display='';
if($_SESSION['branchtype']=="hall")
{
//hall
$sql='SELECT name,image FROM `hall` WHERE id='.$hallid.'';
$hallinfo=queryReceive($sql);
$display.= '<div class="jumbotron shadow" style="background-image: url(';
if($hallinfo[0][1]=="")
{
$display.='https://thumbs.dreamstime.com/z/wedding-hall-decoration-reception-party-35933352.jpg';
}
else
{
$display.=$hallinfo[0][1];
}
$display.=');background-size:100% 115%;background-repeat: no-repeat">
<div class="card-body text-center" style="opacity: 0.7 ;background: white;">
<h1 class="display-5 ">'.$hallinfo[0][0].'</h1>
<h3><i class="fas fa-tasks mr-3"></i>User Display</h3>
<p class="lead">Trace your orders and payments </p>
</div>
</div>';
}
else
{
//catering
$sql='SELECT `name`, `image` FROM `catering` WHERE id='.$cateringid.'';
$cateringinfo=queryReceive($sql);
$display.= '<div class="jumbotron shadow" style="background-image: url(';
if($cateringinfo[0][1]=="")
{
$display.='https://cdn2.vectorstock.com/i/1000x1000/38/86/wedding-catering-services-word-concept-banner-vector-24983886.jpg';
}
else
{
$display.=$cateringinfo[0][1];
}
$display.=');background-size:100% 115%;background-repeat: no-repeat">
<div class="card-body text-center" style="opacity: 0.7 ;background: white;">
<h1 class="display-5 ">'.$cateringinfo[0][0].'</h1>
<h3><i class="fas fa-tasks mr-3"></i>User Display</h3>
<p class="lead">.Trace your orders and payments</p>
</div>
</div>';
}
echo $display;
?>
<div class="container row m-auto">
<!-- $OrderStatus=array("running","cancel","delieved","clear");-->
<a href="../customer/CustomerCreate.php" class="h-25 col-5 shadow text-dark m-2 text-center">
<i class="fas fa-cart-plus fa-5x"></i><h3>Order Create</h3></a>
<a href="../order/FindOrder.php?order_status=Today_Orders" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-book-reader fa-5x"></i><h3>Today Orders</h3></a>
<a href="../order/FindOrder.php?order_status=Running" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-cart-arrow-down fa-5x"></i><h3>Running Order</h3></a>
<a href="../order/FindOrder.php?order_status=Delieved" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-truck fa-5x"></i><h3>Deliever Orders</h3></a>
<a href="../order/FindOrder.php?order_status=Clear" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="far fa-thumbs-up fa-5x"></i><h3>Clear Orders</h3></a>
<a href="../order/FindOrder.php?order_status=Cancel" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="far fa-trash-alt fa-5x"></i><h3>Cancel Orders</h3></a>
<!-- <a href="/public_html/payment/transferPaymentReceive.php?option=userDisplay" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fas fa-money-bill-alt fa-5x"></i><h3>Receive payment</h3></a>-->
<!-- <a href="/public_html/system/dish/dishesDetail.php" class="h-25 col-6"><h1>Guideline Dishes</h1></a>
<a href="/public_html/system/user/usercreate.php" class="h-25 col-6"><h1>User Create</h1></a>
-->
<a href="../payment/RemainingAmount.php" class="h-25 col-5 shadow text-dark m-2 text-center"><i class="fab fa-amazon-pay fa-5x"></i><h3>All Orders Payments info</h3></a>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
</script>
</body>
</html>
<file_sep>
<!--<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<script src="../../jquery-3.3.1.js"></script>
<link rel="stylesheet" type="text/css" href="/public_html/../bootstrap.min.css">
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
</head>
<body >-->
<div id="preloader">
<div id="loader"></div>
</div>
<nav class="navbar navbar-expand-lg navbar-dark bg-dark fixed-top" style="background: #ee0979; /* fallback for old browsers */
background: -webkit-linear-gradient(to right, #ff6a00, #ee0979); /* Chrome 10-25, Safari 5.1-6 */
background: linear-gradient(to right, #ff6a00, #ee0979);/* W3C, IE 10+/ Edge, Firefox 16+, Chrome 26+, Opera 12+, Safari 7+ */
">
<div class="container">
<h6 class="navbar-brand" href="#"><img src="/public_html/gmail.png" style="width: 70px"> <span class="navbar-text font-weight-bold text-white">Event Guru</span></h6>
<button class="navbar-toggler" type="button" data-toggle="collapse" data-target="#navbarSupportedContent" aria-controls="navbarSupportedContent" aria-expanded="false" aria-label="Toggle navigation">
<span class="navbar-toggler-icon"></span>
</button>
<div class="collapse navbar-collapse" id="navbarSupportedContent">
<ul class="navbar-nav mr-auto w-100 justify-content-end">
<li class="nav-item ">
<a class="nav-link" href="/public_html/index.php?action=home"><i class="fas fa-home"></i> Home <span class="sr-only">(current)</span></a>
</li>
<?php
if(isset($_COOKIE["userid"]))
{
echo '
<li class="nav-item active">
<a class="nav-link" href="/public_html/company/companyRegister/companydisplay.php"><i class="fas fa-building"></i> My Company<span class="sr-only">(current)</span></a>
</li>
';
}
?>
<?php
if(!isset($_COOKIE["userid"]))
{
echo '
<li class="nav-item ">
<a class="nav-link" href="/public_html/company/companyRegister/companyRegister.php"><i class="far fa-registered"></i> Company Register<span class="sr-only">(current)</span></a>
</li>';
}
?>
<!--<li class="nav-item dropdown">
<a class="nav-link dropdown-toggle" href="#" id="navbarDropdown" role="button" data-toggle="dropdown" aria-haspopup="true" aria-expanded="false">
<i class="fas fa-shopping-cart"></i> Order Preview
</a>
<div class="dropdown-menu" aria-labelledby="navbarDropdown">
<a class="dropdown-item" href="#">Action</a>
<a class="dropdown-item" href="#">Another action</a>
<div class="dropdown-divider"></div>
<a class="dropdown-item" href="#">Something else here</a>
</div>
</li>-->
<?php
if(!isset($_COOKIE["userid"]))
{
echo '
<li class="nav-item">
<a class="nav-link" href="/public_html/user/userLogin.php"><i class="fas fa-sign-in-alt"></i> Sign in</a>
</li>';
}
?>
<?php
if(isset($_SESSION["order"]))
{
echo '
<li class="nav-item">
<a class="nav-link" href="/public_html/order/PreviewOrder.php"><i class="fas fa-shopping-cart"></i> Order Preview</a>
</li>';
}
if(isset($_SESSION['order']))
{
echo ' <a class="nav-link" href="/public_html/user/userDisplay.php" ><i class="fas fa-grip-horizontal"></i> User Display</a>';
}
?>
<?php
if(isset($_COOKIE["userid"]))
{
echo '
<li class="nav-item">
<a class="nav-link" href="/public_html/user/logout.php"><i class="fas fa-sign-out-alt"></i> Sign out</a>
</li>
<li class="nav-item active">
<a class="nav-link" href="/public_html/company/companyRegister/companyEdit.php"><i class="fas fa-globe-europe"></i> Edit Company</a>
</li>
';
}
?>
<li class="nav-item">
<a class="nav-link" href="/public_html/user/userLogin.php?action=admin"><i class="fas fa-users-cog"></i>Admin</a>
</li>
</ul>
</div>
</div>
</nav>
<div style="margin-top: 80px">
</div>
<!--
<script>
</script>
</body>
</html>-->
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include ("../../connection/connect.php");
$companyid=$_GET['companyid'];
$sql='SELECT `id`, `name`,`image` FROM `hall` WHERE ISNULL(expire) AND (company_id='.$companyid.')';
$halls=queryReceive($sql);
$sql='SELECT `id`, `name`,`image` FROM `catering` WHERE ISNULL(expire) AND (company_id='.$companyid.')';
$caterings=queryReceive($sql);
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0;
padding: 0;
}
</style>
</head>
<body>
<h1 align=" center">Company Name</h1>
<div class="col-12 m-1 mb-5 form-group row shadow alert-warning " >
<h1 align="center" class="col-12">Branches of Hall</h1>
<?php
$display='';
for ($i=0;$i<count($halls);$i++)
{
$display.= '
<a href="../../user/userDisplay.php?hallid='.$halls[$i][0].'" class="col-5 m-2">
<div class="card col-12 rounded-circle shadow" style="height: 25vh" >
<img class="card-img-top col-12 rounded-circle" src="';
if(file_exists($halls[$i][2]))
{
$display.=$halls[$i][2];
}
else
{
$display.='../../gmail.png';
}
$display.='" alt="Card image" >
</div>
<h4 align="center" >'.$halls[$i][1].'</h4>
</a>';
}
echo $display;
?>
</div>
<div class="col-12 m-1 mb-5 form-group row shadow alert-success " >
<h1 align="center" class="col-12">Branches of Catering</h1>
<?php
$display='';
for ($i=0;$i<count($caterings);$i++)
{
$display.= '
<a href="../../user/userDisplay.php?cateringid='.$caterings[$i][0].'" class="col-5 m-2">
<div class="card col-12 rounded-circle shadow" style="height: 25vh" >
<img class="card-img-top col-12 rounded-circle" src="';
if(file_exists($caterings[$i][2]))
{
$display.=$caterings[$i][2];
}
else
{
$display.='../../gmail.png';
}
$display.='" alt="Card image" >
</div>
<h4 align="center" >'.$caterings[$i][1].'</h4>
</a>';
}
echo $display;
?>
</div>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-08
* Time: 14:15
*/
include_once ("../connection/connect.php");
$userId=$_GET['user_id'];
$orderDetail_id=$_GET['order'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<div class="container" style="margin-top:150px">
<div id="from3">
<h1 align="center">your payments</h1>
<a class="btn-success form-control col-4 " href="/Catering/order/PreviewOrder.php?order=<?php echo $orderDetail_id; ?>"> <- Preview Order</a>
<div class="form-group row border">
<label class="font-weight-bold col-2 col-form-label">ID</label>
<label class="font-weight-bold col-4 col-form-label">Amount</label>
<label class="font-weight-bold col-4 col-form-label">Date</label>
<label class="font-weight-bold col-2 col-form-label">Send</label>
</div>
<?php
$sql='SELECT py.id,py.amount,py.receive FROM payment as py
WHERE (py.user_id='.$userId.') AND (py.orderDetail_id='.$orderDetail_id.') AND (py.sendingStatus in (0,1)) order BY
py.receive DESC';
$paymentDetail=queryReceive($sql);
for($l=0;$l<count($paymentDetail);$l++)
{
echo '<div class="form-group row border">
<label class="col-2 col-form-label">'.$paymentDetail[$l][0].'</label>
<label class="col-3 col-form-label">'.$paymentDetail[$l][1].'</label>
<label class="col-5 col-form-label">'.$paymentDetail[$l][2].'</label>
<a href="/Catering/payment/paymentDisplaySend.php?user_id='.$userId.'&payment='.$paymentDetail[$l][0].'&order='.$orderDetail_id.'" class="col-2 form-control btn-primary">Send</a>
</div>';
}
?>
</div>
</div>
<script>
$(document).ready(function () {
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-06
* Time: 16:48
*/
include_once ("../connection/connect.php");
if((!isset($_POST['dishid']))&&($_SESSION['order']))
{
header("location:AllSelectedDishes.php");
exit();
}
$orderId=$_SESSION['order'];
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../webdesign/css/complete.css">
<link rel="stylesheet" href="../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="jumbotron shadow" style="background-image: url(http://tongil.com.au/wp-content/uploads/2018/02/ingredients.jpg);background-size:100% 115%;background-repeat: no-repeat">
<div class="card-header text-center" style="opacity: 0.7 ;background: white;">
<h3 class="text-dark"><i class="fas fa-file-word fa-3x mr-2 "></i>Dishes Create</h3>
</div>
</div>
<div class="container">
<input hidden type="number" id="orderIdindish" value="<?php echo $orderId;?>">
<?php
$dishesId=$_POST['dishid'];
$types=$_POST['types'];
$totalDishes=0;
$display='';
$number=0;
for ($i=0;$i<count($types);$i++)
{
$totalDishes+=$types[$i];
for ($k=$types[$i];$k>0;$k--)
{
$value=$dishesId[$i];
$sql = 'SELECT d.id,d.name,d.image FROM dish as d WHERE d.id=' . $value . '';
$dishDetail = queryReceive($sql);
$display .= '
<form id="form_' . $number . '">
<div class="card shadow-lg p-4 mb-4 border col-12">';
$image = substr($dishDetail[0][2], 6);
if(!file_exists($image))
{
$image='https://vector.me/files/images/1/4/145000/icon_food_bowl_plate_dan_outline_symbol_silhouette_cartoon_dish_free_knife_logo_fork_plates_cartoons_spoon_dinner_iammisc_spoons_forks_knives_sendok_garpu_diner_piring.jpg';
}
$display.='<div class="row">
<div class="col-6 m-auto card-body">
<img src="'.$image.'" style="height: 20vh;width: 100%">
<p class="card-header">'.$dishDetail[0][1].'</p>
</div>
</div>';
// <h2 align="center">' . $dishDetail[0][1] . '</h2>
$display.='<input hidden type="number" name="dishId" value="' . $value . '">';
$sql = 'SELECT a.id,a.name FROM attribute as a INNER JOIN dish as d
on d.id=a.dish_id
WHERE (d.id=' . $value . ') AND (ISNULL(a.isExpire))';
$attributeDetail = queryReceive($sql);
for ($j = 0; $j < count($attributeDetail); $j++) {
$display .= ' <div class="form-group row">
<label class="col-form-label">' . $attributeDetail[$j][1] . '</label>
<input hidden name="attributeId[]" value="' . $attributeDetail[$j][0] . '">
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-sticky-note"></i></span>
</div>
<input name="attributeValue[]" class="form-control" type="number" placeholder="etc rice,mutton,..">
</div>
</div>';
}
$display .= ' <div class="form-group row">
<label class="col-form-label">each price</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-money-bill-alt"></i></span>
</div>
<input name="each_price" class="form-control" type="number" placeholder="etc one dish price 1000xx">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">Quantity</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-sort-amount-up"></i></span>
</div>
<input name="quantity" class="form-control" type="number" placeholder="how many dishes 1,2,3,...">
</div>
</div>
<div class="form-group row">
<label class="col-form-label">describe</label>
<div class="input-group mb-3 input-group-lg">
<div class="input-group-prepend">
<span class="input-group-text"><i class="fas fa-comments"></i></span>
</div>
<textarea name="describe" class="form-control" type="text" placeholder="important comments for dish"></textarea>
</div>
</div>
<div class="form-group row justify-content-center">
<button type="button" data-formid="' . $number . '" class="cancelForm form-control btn col-5 btn-danger" value="cancel"><i class="fas fa-trash-alt"></i>Cancel</button>
<button type="button" data-formid="' . $number . '" class="submitForm form-control btn col-5 btn-primary" value="submit"><i class="fas fa-check "></i>Submit</button>
</div>
</div>
</form>';
$number++;
}
}
echo $display;
echo '<h4 align="center">total number of dishes<input readonly type="number" id="totalRemaing" value='.$totalDishes.'></h4>';
?>
</div>
<?php
include_once ("../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
var totalitems= $("#totalRemaing").val();
function redirect()
{
totalitems--;
if(totalitems==0)
{
window.location.href="AllSelectedDishes.php";
}
}
$(document).on('click','.submitForm',function ()
{
var id=$(this).data("formid");
var formdata=new FormData($("#form_"+id)[0]);
formdata.append("option",'createDish');
$.ajax({
url:"dishServer.php",
method:"POST",
data:formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
}
else
{
$("#form_"+id).remove();
redirect();
}
}
});
});
$(document).on('click','.cancelForm',function () {
var id=$(this).data("formid");
$("#form_"+id).remove();
redirect();
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../connection/connect.php");
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="/Catering/bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:auto;
padding: auto;
}
</style>
</head>
<body class="alert-light">
<?php
include_once ("../webdesign/header/header.php");
?>
<div class="container" style="margin-top:150px">
<h1 align="center"> Order Create</h1>
<form>
<input type="number" hidden id="customeridForm" value=<?php echo $_GET['customer'];?> >
<div class="form-group row">
<label for="persons" class="col-4 col-form-label"> no of guests</label>
<input type="number" name="persons" id="persons" class="col-8 form-control">
</div>
<div class="form-group row">
<label for="time" class="col-4 col-form-label">delivery Time</label>
<input type="time" name="time" id="time" class="col-8 form-control">
</div>
<div class="form-group row">
<label for="date" class="col-4 col-form-label">delivery Date</label>
<input type="date" name="date" id="date" class="col-8 form-control">
</div>
<h3 align="center"> Deliver Address</h3>
<div class="form-group row">
<label for="area" class="col-4 col-form-label">area / block </label>
<input type="text" name="area" id="area" class="col-8 form-control">
</div>
<div class="form-group row">
<label for="streetNO" class="col-4 col-form-label">Street no #</label>
<input type="number" name="streetno" id="streetNO" class="col-8 form-control">
</div>
<div class="form-group row">
<label for="houseno" class="col-4 col-form-label">house no# </label>
<input type="number" name="houseno" id="houseno" class="col-8 form-control">
</div>
<div class="form-group row">
<label for="describe" class="col-4 col-form-label">describe order </label>
<textarea id="describe" name="describe" class="form-control col-8 form-control"></textarea>
</div>
<div class="form-group row">
<?php
if(isset($_GET['option']))
{
if(($_GET['option']=="CustomerCreate")||($_GET['option']=="customerEdit"))
{
echo '<a href="/Catering/customer/customerEdit.php?customer='.$_GET['customer'].'&option=orderCreate" class="form-control col-4 btn btn-danger">Edit Customer</a>';
}
}
else
{
echo '
<button type="button" id=\'cancelorder\'class="form-control col-4 btn btn-danger"> cancel</button>';
}
?>
<button type="button" id="submit" class="form-control col-4 btn-success"> submit</button>
</div>
</form>
</div>
<script>
$(document).ready(function ()
{
$("#submit").click(function (e)
{
e.preventDefault();
var customerid=$("#customeridForm").val();
var formdata=new FormData($('form')[0]);
formdata.append('function',"add");
$.ajax({
url:"orderServer.php?customer="+customerid,
data:formdata,
method:"POST",
contentType: false,
processData: false,
dataType:"text",
success:function (data)
{
if(!($.isNumeric(data)))
{
alert(data);
}
else
{
window.location.href="/Catering/dish/dishDisplay.php?order="+data+"&customer="+customerid+"&option=orderCreate";
}
}
});
});
$("#cancelorder").click(function () {
window.history.back();
return false;
});
});
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:25
*/
date_default_timezone_set("asia/karachi");
$connect=mysqli_connect('localhost',"root","","a111");
//$connect=mysqli_connect("localhost","id10884474_shahzad","11111","id10884474_catering");
if(!$connect)
{
echo "fail connection";
}
if (mysqli_connect_errno())
{
printf("Connect failed: %s\n", mysqli_connect_error());
exit();
}
function queryReceive($sql)
{
global $connect;
$result = mysqli_query($connect, $sql);
if (!$result)
{
echo("Error description: " . mysqli_error($connect));
}else{
return mysqli_fetch_all($result);
}
}
function querySend($sql)
{
global $connect;
$result = mysqli_query($connect, $sql);
if (!$result)
{
echo $sql;
echo("Error description: " . mysqli_error($connect));
}
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-28
* Time: 20:23
*/
echo "wwewew";
?><file_sep><?php
$hallid=$_POST['hallid']=2;
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
*{
margin:0;
padding: 0;
}
</style>
</head>
<body>
<h1 align="center">Hall information</h1>
<h3 align="center">Hall Branch Name:</h3>
<h4 align="center">Only seating price</h4>
<?php
$daytimearray=array("Morning","Afternoon","Evening");
for ($k=0;$k<count($daytimearray);$k++)
{
?>
<div class="shadow card p-2 mb-4" id="formdisplay<?php echo $daytimearray[$k]; ?>">
<form id="form<?php echo $daytimearray[$k]; ?>">
<h4 align="center"><?php echo $daytimearray[$k]; ?></h4>
<input hidden type="text" name="daytime" value="<?php echo $daytimearray[$k]; ?>">
<table class=" table table-striped table-danger ">
<thead>
<tr>
<th scope="col">
Months
</th>
<th scope="col">
Price per head
</th>
</tr>
</thead>
<tbody>
<?php
$monthsArray = array('January', 'February', 'March', 'April', 'May', 'June', 'July', 'August', 'September', 'October', 'November', 'December');
for ($m = 0; $m < count($monthsArray); $m++) {
echo '
<tr>
<th scope="row">' . $monthsArray[$m] . '</th>
<td><input type="number" name="month[]" value="0"></td>
</tr>
';
}
?>
<tr>
<td colspan="2">
<input data-formid='<?php echo $daytimearray[$k]; ?>' type="button" value="submit"
class="btnsubmit btn btn-success form-control">
</td>
</tr>
</tbody>
</table>
</form>
</div>
<?php
}
?>
<script>
$(document).ready(function () {
var formno=3;
var hallid=<?php echo $hallid;?>;
$(".btnsubmit").click(function ()
{
var id=$(this).data("formid");
var formdata=new FormData($('#form'+id)[0]);
formdata.append("option","createOnlyseating");
formdata.append("hallid",hallid);
$.ajax({
url: "../companyServer.php",
method: "POST",
data: formdata,
contentType: false,
processData: false,
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!='')
{
alert(data);
}
else
{
$('#formdisplay'+id).hide('slow');
formno--;
if(formno==0)
{
window.location.href="RegisterFoodMenu.php?hallid="+hallid+"";
}
}
}
});
}) ;
});
</script>
</body>
</html>
<file_sep><?php
$hallid=$_GET['hallid']=1;
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../bootstrap.min.css">
<script src="../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<style>
*{
margin:0;
padding: 0;
}
</style>
</head>
<body>
<h1 align="center">Hall Display</h1>
<a href=""></a>
<script>
</script>
</body>
</html>
<file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-06
* Time: 23:08
*/
include_once ("../connection/connect.php");
session_start();
if(!isset($_POST['option']))
{
echo "option is not created";
exit();
}
$orderId='';
if(isset($_GET['order']))
{
$orderId=$_GET['order'];
}
if($_POST['option']=='createDish')
{
$dishId=$_POST['dishId'];
$attributesId=$_POST['attributeId'];
$attributesValue=$_POST['attributeValue'];
$each_price=$_POST['each_price'];
$quantity=$_POST['quantity'];
$describe=$_POST['describe'];
$CurrentDateTime=date('Y-m-d H:i:s');
$sql='INSERT INTO `dish_detail`(`id`, `describe`, `price`, `expire_date`, `quantity`, `dish_id`, `orderTable_id`)VALUES(NULL,"'.$describe.'","'.$each_price.'",NULL,"'.$quantity.'",'.$dishId.','.$orderId.')';
querySend($sql);
$dishDetailId=mysqli_insert_id($connect);
for ($i=0;$i<count($attributesId);$i++)
{
$sql='INSERT INTO `attribute_name`(`id`, `quantity`, `attribute_id`, `dish_detail_id`)
VALUES (NULL,"'.$attributesValue[$i].'",'.$attributesId[$i].','.$dishDetailId.')';
querySend($sql);
}
}
else if($_POST["option"]=='attributeChange')
{
$attributeid=$_POST['attributeid'];
$valueAttribute=$_POST['value'];
$sql='UPDATE attribute_name as an SET an.quantity ='.$valueAttribute.' WHERE an.id='.$attributeid.'';
querySend($sql);
}
else if($_POST['option']=='dishDetailChange')
{
$dishDetailId=$_POST['dishDetailId'];
$columnName=$_POST['columnName'];
$columnValue=$_POST['columnValue'];
$sql='UPDATE dish_detail as dd SET dd.'.$columnName.'="'.$columnValue.'" WHERE dd.id='.$dishDetailId.'';
querySend($sql);
}
else if($_POST['option']=='deleteDish')
{
$dishDetailId=$_POST['dishDetailId'];
$currentDate=date('Y-m-d H:i:s');
$sql='UPDATE dish_detail as dd SET dd.expire_date="'.$currentDate.'" WHERE dd.id='.$dishDetailId.'';
querySend($sql);
}<file_sep><?php
include_once ('connect.php');
require('../fpdf181/fpdf.php');
class PDF extends FPDF
{
function HeaderCompany($branchinfo,$owerinfo)
{
// Logo
// $this->Image('../gmail.png',10,6,20);
// Arial bold 15
$this->SetFont('Arial','B',10);
// Move to the right
$this->Cell(80);
// Title
$this->Cell(30,10,$branchinfo[0][0],1,1,'C');
$displaynum=$branchinfo[0][0]." company # : ";
for($i=0;$i<count($owerinfo)&&($i!=3);$i++)
{
if($owerinfo[$i][1]!="")
{
//$displaynum .= $owerinfo[$i][0] . " " . $owerinfo[$i][1] . " | ";
$displaynum .= $owerinfo[$i][1] . " , ";
}
}
$this->Cell(189,10,$displaynum,0,1,"C");
}
// Page footer
function Footer()
{
// Position at 1.5 cm from bottom
$this->SetY(-15);
// Arial italic 8
$this->SetFont('Arial','I',9);
$this->Cell(189,0,"",1,1);
$this->Image('../gmail.png', 5, $this->GetY(), 12);
$this->Cell(0,10,"Event Guru (website:www.eventguru.com) , (Gmail:<EMAIL>) , (whatsapp:0923350498004) ".'Page '.$this->PageNo().'/{nb}',0,1,'R');
}
function cateringorderPrint($detailorder,$person,$numbers,$addresDetail,$dishDetail,$address,$totalReceivedPayment,$branchinfo,$owerinfo,$userName,$printDate)
{
$this->HeaderCompany($branchinfo,$owerinfo);
$this->Cell(189,10,'Information ',1,1,'C');
$displayDateTime="order status : ".$detailorder[0][17]." , Date : ". $detailorder[0][14]." , Time :".$detailorder[0][16]." , persons ".$detailorder[0][12];
$this->Cell(30,10,$displayDateTime,0,1);
if($detailorder[0][19]!="")
{
$text='Description : '.$detailorder[0][19];
$nb=$this->WordWrap($text,189);
$this->Write(10,$text);
$this->Cell(189,10,"",0,1);
}
$displayaddress="Delivering Address : ".$addresDetail[0][1]." , ".$addresDetail[0][2]." , ".$addresDetail[0][3]." , ".$addresDetail[0][4];
$this->Cell(30,10,'<NAME> ',0,0);
$this->Cell(30,10,$person[0][0],0,1);
$this->Cell(189,10,$displayaddress,0,1);
$numberdis="customer # ";
for($i=0;($i<count($numbers)&&($i!=3));$i++)
{
$numberdis.=$numbers[0][$i]." ,";
}
$this->Cell(189,10,$numberdis,0,1);
$this->Cell(45,10,"User Name : ",0,0);
$this->Cell(45,10,$userName,0,0);
$this->Cell(45,10,"Printed Date:",0,0);
$this->Cell(45,10,$printDate,0,1);
//$this->Cell(189,10,$displayaddress,0,1);
$this->Cell(189,10,"Catering Order",1,1,"C");
//order billing
$this->Cell(64,10,"<NAME>",1,0);
$this->Cell(40,10,"quantity",1,0);
$this->Cell(40,10,"price",1,0);
$this->Cell(45,10,"total price",1,1);
$systemCalculate=0;
for($i=0;$i<count($dishDetail);$i++)
{
$this->Cell(64,10,$dishDetail[$i][5],0,0);
$this->Cell(40,13,$dishDetail[$i][3],1,0);
$this->Cell(40,13,$dishDetail[$i][2],1,0);
$systemCalculate+=$dishDetail[$i][3]*$dishDetail[$i][2];
$this->Cell(45,13,$systemCalculate,1,1);
// detail of dish attributes
$sql='SELECT a.name,an.quantity FROM attribute_name as an INNER join attribute as a
on
(an.attribute_id=a.id)
WHERE
(an.dish_detail_id='.$dishDetail[$i][0].')
';
$attributeDetail=queryReceive($sql);
$display='';
for($j=0;$j<count($attributeDetail);$j++)
{
$display.=$attributeDetail[$j][0]."=".$attributeDetail[$j][1]." , ";
}
$display.=$dishDetail[$i][1];
$this->Cell(189,3,$display,0,1);
$this->Cell(189,0,"",1,1);
}
$this->Cell(144,10,"total Amount= ",1,0);
$this->Cell(45,10,$systemCalculate,1,1);
$this->Cell(144,10,"receive Amount= ",1,0);
$this->Cell(45,10,$totalReceivedPayment[0][0],1,1);
$this->Cell(144,10,"Remaining Amount ",1,0);
$this->Cell(45,10,$systemCalculate-$totalReceivedPayment[0][0],1,1);
$this->Cell(144,10,"your Demanded Amount= ",1,0);
$this->Cell(45,10,$detailorder[0][11],1,1);
$this->Cell(144,10,"your Demanded Remaining Amount ",1,0);
$this->Cell(45,10,$detailorder[0][11]-$totalReceivedPayment[0][0],1,1);
}
function hallorderPrint($detailorder,$person,$numbers,$menu,$totalReceivedPayment,$branchinfo,$owerinfo,$userName,$printDate)
{
$this->HeaderCompany($branchinfo,$owerinfo);
$this->Cell(189,10,'Information ',1,1,'C');
//$displayDateTime="order status : ".$detailorder[0][13]." , Date : ". $detailorder[0][14]." , Time :".$detailorder[0][16]." , persons ".$detailorder[0][12];
$this->Cell(30,10,'Customer Name ',0,0);
$this->Cell(30,10,$person[0][0],0,1);
$numberdis="customer # ";
for($i=0;($i<count($numbers)&&($i!=3));$i++)
{
$numberdis.=$numbers[0][$i]." ,";
}
$this->Cell(189,10,$numberdis,0,1);
$this->Cell(45,10,"User Name : ",0,0);
$this->Cell(45,10,$userName,0,0);
$this->Cell(45,10,"Printed Date:",0,0);
$this->Cell(45,10,$printDate,0,1);
$this->Cell(189,10,"Order Detail",1,1,"C");
$this->Cell(45,10,"No of Guest : ",0,0);
$this->Cell(45,10,$detailorder[0][12],0,0);
$this->Cell(45,10,"Deliver Date : ",0,0);
$this->Cell(45,10,$detailorder[0][14],0,1);
$this->Cell(45,10,"Hall Timing : ",0,0);
$this->Cell(45,10,$detailorder[0][16],0,0);
$this->Cell(45,10,"per Head : ",0,0);
$this->Cell(45,10,$detailorder[0][3],0,1);
$this->Cell(45,10,"current Order Status : ",0,0);
$this->Cell(45,10,$detailorder[0][13],0,0);
$this->Cell(45,10,"booked Date : ",0,0);
$this->Cell(45,10,$detailorder[0][15],0,1);
if($detailorder[0][19]!="")
{
$text='Description : '.$detailorder[0][19];
$nb=$this->WordWrap($text,189);
$this->Write(10,$text);
$this->Cell(189,10,"",0,1);
}
$this->Cell(189,10,"Payments Detial : ",1,1,"C");
$this->Cell(45,10,"Total Amount : ",0,0);
$this->Cell(45,10,$detailorder[0][11],0,0);
$this->Cell(45,10,"Per Head Rate :",0,0);
if($detailorder[0][12]==0)
$detailorder[0][12]=1;
$this->Cell(45,10,$detailorder[0][11]/$detailorder[0][12],0,1);
$this->Cell(45,10,"Received Amount : ",0,0);
$this->Cell(45,10,$totalReceivedPayment[0][0],0,0);
$this->Cell(45,10,"Remaining Amount :",0,0);
$this->Cell(45,10, ($detailorder[0][11]-$totalReceivedPayment[0][0]),0,1);
if($detailorder[0][3]==1)
{
//menu if per head with food
$this->Cell(189,10,"Package Detail ",1,1,"C");
$x=0;
for($i=0;$i<count($menu);$i++)
{
if((($i+1)%4)==0)
{
$x=1;
}
else
{
$x=0;
}
$this->Cell(45,10,$menu[$i][0],0,$x);
}
$this->Cell(189,10,"",0,1);
$this->Cell(189,10,"Description : ".$detailorder[0][20],0,1);
}
}
function billing($userName,$printDate,$orderId)
{
//order 9 catering hall 1
// $orderId=9;
$sql='SELECT `id`, `hall_id`, `catering_id`, (SELECT hp.isFood from hallprice as hp WHERE hp.id=orderDetail.hallprice_id),
`user_id`, `sheftCatering`, `sheftHall`, `sheftCateringUser`,
`sheftHallUser`, `address_id`, `person_id`, `total_amount`,
`total_person`, `status_hall`, `destination_date`,
`booking_date`, `destination_time`, `status_catering`,
`notice`,`describe`,(SELECT hp.describe from hallprice as hp WHERE hp.id=orderDetail.hallprice_id),hallprice_id,(SELECT hp.price from hallprice as hp WHERE hp.id=orderDetail.hallprice_id) FROM `orderDetail` WHERE id='.$orderId.'';
$detailorder = queryReceive($sql);
$sql='SELECT sum(py.amount) FROM payment as py WHERE (py.IsReturn=0)AND(py.orderDetail_id='.$orderId.')';
$totalReceivedPayment=queryReceive($sql);
//customer information
$sql = "SELECT `name`, `cnic`, `id`, `date`, `image` FROM `person` WHERE id=".$detailorder[0][10]."";
$person=queryReceive($sql);
//numbers
$sql="SELECT n.number, n.id, n.is_number_active, n.person_id FROM number as n inner JOIN person as p ON p.id=n.person_id
WHERE p.id='".$person[0][2]."' order BY n.id";
$numbers=queryReceive($sql);
if($detailorder[0][1]=="")
{
//catering order
$sql = 'SELECT `id`, `address_city`, `address_town`, `address_street_no`, `address_house_no`, `person_id` FROM `address` WHERE id="'.$detailorder[0][9].'"';
$addresDetail = queryReceive($sql);
$sql='SELECT `name`,`company_id` FROM `catering` WHERE id='.$detailorder[0][2].'';
$branchinfo=queryReceive($sql);
//catering owener info
$sql='SELECT p.name,n.number FROM company as c INNER join user as u
on (c.user_id=u.id)
INNER join person as p
on (p.id=u.person_id)
INNER join number as n
on (p.id=n.person_id)
WHERE
(c.id='.$branchinfo[0][1].')
AND
(n.is_number_active=1)
';
$owerinfo=queryReceive($sql);
//detail of order dish
$sql='SELECT id,`describe`, `price`, `quantity`, `dish_id`,(SELECT d.name FROM dish as d WHERE d.id=dish_id ) FROM `dish_detail` WHERE (orderDetail_id='.$orderId.')AND(ISNULL(expire_date))';
$dishDetail=queryReceive($sql);
//person address
$sql = "SELECT a.id, a.address_city, a.address_town, a.address_street_no, a.address_house_no, a.person_id FROM address as a inner JOIN person p ON a.person_id=p.id
WHERE a.person_id=".$detailorder[0][10]."
ORDER by a.person_id;";
$address=queryReceive($sql);
$this->cateringorderPrint($detailorder,$person,$numbers,$addresDetail,$dishDetail,$address,$totalReceivedPayment,$branchinfo,$owerinfo,$userName,$printDate);
}
else
{
//hall order
$sql='SELECT `name`, `company_id` FROM `hall` WHERE id='.$detailorder[0][1].'';
$branchinfo=queryReceive($sql);
//catering owener info
$sql='SELECT p.name,n.number FROM company as c INNER join user as u
on (c.user_id=u.id)
INNER join person as p
on (p.id=u.person_id)
INNER join number as n
on (p.id=n.person_id)
WHERE
(c.id='.$branchinfo[0][1].')
AND
(n.is_number_active=1)
';
$owerinfo=queryReceive($sql);
$menu=array();
if($detailorder[0][3]==1)
{
//with menu
$sql = 'SELECT `dishname`, `image` FROM `menu` WHERE (hallprice_id='.$detailorder[0][21] . ') AND ISNULL(expire)';
$menu = queryReceive($sql);
}
$this->hallorderPrint($detailorder,$person,$numbers,$menu,$totalReceivedPayment,$branchinfo,$owerinfo,$userName,$printDate);
}
}
function WordWrap(&$text, $maxwidth)
{
$text = trim($text);
if ($text==='')
return 0;
$space = $this->GetStringWidth(' ');
$lines = explode("\n", $text);
$text = '';
$count = 0;
foreach ($lines as $line)
{
$words = preg_split('/ +/', $line);
$width = 0;
foreach ($words as $word)
{
$wordwidth = $this->GetStringWidth($word);
if ($wordwidth > $maxwidth)
{
// Word is too long, we cut it
for($i=0; $i<strlen($word); $i++)
{
$wordwidth = $this->GetStringWidth(substr($word, $i, 1));
if($width + $wordwidth <= $maxwidth)
{
$width += $wordwidth;
$text .= substr($word, $i, 1);
}
else
{
$width = $wordwidth;
$text = rtrim($text)."\n".substr($word, $i, 1);
$count++;
}
}
}
elseif($width + $wordwidth <= $maxwidth)
{
$width += $wordwidth + $space;
$text .= $word.' ';
}
else
{
$width = $wordwidth + $space;
$text = rtrim($text)."\n".$word.' ';
$count++;
}
}
$text = rtrim($text)."\n";
$count++;
}
$text = rtrim($text);
return $count;
}
}
function action($userName,$printDate,$orderid,$action)
{
// Instanciation of inherited class
$pdf = new PDF('P',"mm","A4");
$pdf->AliasNbPages();
$pdf->AddPage();
$pdf->SetFont('Times','',8);
$pdf->billing($userName,$printDate,$orderid);
//$pdf->Output($action,"orderid".$orderid."date".$printDate);
$pdf->Cell(189,10,"",0,1);
$pdf->Cell(45,20,"Company User signature",0,0,"C");
$pdf->Cell(45,20,"",1,0);
$pdf->Cell(45,20,"Customer signature",0,0,"C");
$pdf->Cell(45,20,"",1,1);
$pdf->Output($action,"orderid".$orderid."date".$printDate.".pdf");
}
?><file_sep><?php
/**
* Created by PhpStorm.
* User: shahzadmiraj
* Date: 2019-09-01
* Time: 21:31
*/
include_once ("../../connection/connect.php");
?>
<!DOCTYPE html>
<head>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<link rel="stylesheet" type="text/css" href="../../bootstrap.min.css">
<script src="../../jquery-3.3.1.js"></script>
<script type="text/javascript" src="../../bootstrap.min.js"></script>
<meta charset="utf-8">
<link rel="stylesheet" href="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/css/bootstrap.min.css">
<script src="https://cdnjs.cloudflare.com/ajax/libs/popper.js/1.14.7/umd/popper.min.js"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.3.1/js/bootstrap.min.js"></script>
<link rel="stylesheet" href="https://use.fontawesome.com/releases/v5.8.2/css/all.css">
<link rel="stylesheet" href="../../webdesign/css/complete.css">
<link rel="stylesheet" href="../../webdesign/css/loader.css">
<style>
</style>
</head>
<body>
<?php
include_once ("../../webdesign/header/header.php");
?>
<div class="container">
<h1 class="font-weight-bold">System Dish info </h1>
<hr>
<h3 align="center"> Dish Type information</h3>
<div class="col-12 form-group row font-weight-bold border">
<label class="col-9 col-form-label "><i class="fas fa-utensils mr-1"></i>Name Dish type</label>
<label class="col-3 col-form-label ">Detail</label>
</div>
<div class="col-12">
<?php
$sql='SELECT `id`, `name`, `isExpire` FROM `systemDishType` WHERE 1';
$dishTypes=queryReceive($sql);
$Display='';
for($i=0;$i<count($dishTypes);$i++)
{
$Display.= '<div class="form-group row border " id="Delele_Dish_Type_'.$dishTypes[$i][0].'">
<input data-dishtypeid="'.$dishTypes[$i][0].'" value="'.$dishTypes[$i][1].'" class="changeDishType col-9 form-control ">
<input data-dishtypeid="'.$dishTypes[$i][0].'" class=" btn Delele_Dish_Type col-3 form-control ';
if($dishTypes[$i][2]=="")
{
$Display.='btn-primary ';
}
else
{
$Display.=' btn-danger ';
}
$Display.=' " value="';
if($dishTypes[$i][2]=="")
{
$Display.='Disable';
}
else
{
$Display.='Enable';
}
$Display.= '"></div>';
}
echo $Display;
?>
</div>
<div class="col-12 row mb-4">
<h3 class="rounded mx-auto d-block m-4 col-6" align="center"> Dish information</h3>
<a href="addDish.php" class="float-right btn btn-success col-4 form-control mt-4">Add dish +</a>
</div>
<hr>
<div class="container card">
<?php
$sql='SELECT `id`, `name`, `isExpire` FROM `systemDishType` WHERE 1';
$dishTypes=queryReceive($sql);
$Display='';
$display='<div class="form-group row " style="height: 50vh;overflow:auto">';
for($j=0;$j<count($dishTypes);$j++)
{
$display.='<h4 class="col-12 newcolor" align="center">'.$dishTypes[$j][1].'</h4>';
$sql='SELECT d.name, d.id, (SELECT dt.name from systemDishType as dt WHERE dt.id=d.systemDishType_id),(SELECT dt.isExpire from systemDishType as dt WHERE dt.id=d.systemDishType_id), d.isExpire,d.image FROM systemDish as d WHERE d.systemDishType_id='.$dishTypes[$j][0].' ';
$Dishes = queryReceive($sql);
for ($i = 0; $i < count($Dishes); $i++) {
$display .= '<a href="EditDish.php?dishid=' . $Dishes[$i][1] . '" class="col-sm-12 col-md-6 col-xl-4 border">
<img src="';
if(file_exists('../../images/dishImages/'.$Dishes[$i][5])&&($Dishes[$i][5]!=""))
{
$display.='../../images/dishImages/'.$Dishes[$i][5];
}
else
{
$display.='https://www.pngkey.com/png/detail/430-4307759_knife-fork-and-plate-vector-icon-dishes-png.png';
}
$display.='" style="height: 20vh" class="col-12">
<p class="col-12 p-0" ><i class="fas fa-utensils mr-1"></i>' . $Dishes[$i][0] . '</p>
<i class="col-12 ';
if (($Dishes[$i][3] == "") && ($Dishes[$i][4] == "")) {
$display .= " text-primary ";
} else {
$display .= "text-danger ";
}
$display .= '">';
if ($Dishes[$i][3] != "") {
$display .= $Dishes[$i][2] . " Diable ";
}
if ($Dishes[$i][4] != "") {
$display .= " Dish Diable ";
}
$display .= '</i>
</a>';
}
}
$display.='</div>';
echo $display;
?>
</div>
</div>
<?php
include_once ("../../webdesign/footer/footer.php");
?>
<script>
$(document).ready(function ()
{
$(document).on("change",".changeDishType",function ()
{
var id=$(this).data("dishtypeid");
var value=$(this).val();
$.ajax({
url:"dishServer.php",
data:{id:id,value:value,option:"changeDishType"},
dataType:"text",
method:"POST",
beforeSend: function() {
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!="")
{
alert(data);
}
else
{
location.reload();
}
}
});
});
$(document).on("click",".Delele_Dish_Type",function ()
{
var id=$(this).data("dishtypeid");
var value=$(this).val();
$.ajax({
url:"dishServer.php",
data:{value:value,id:id,option:"Delele_Dish_Type"},
dataType:"text",
method:"POST",
beforeSend: function()
{
$("#preloader").show();
},
success:function (data)
{
$("#preloader").hide();
if(data!="")
{
alert(data);
}
else
{
location.reload();
}
}
});
});
});
</script>
</body>
</html> | de42682d8a27bb198acd11a9993626e164e806e9 | [
"SQL",
"PHP"
] | 124 | PHP | shahzadmiraj/catering | 8400dbcd199774ebe3c5258f97cc5dd65d396dca | 5ed57e9b260d08851f5873d1465277a040710c87 |
refs/heads/master | <file_sep><div class="row">
<div class="col-md-6">
<?php
$servers = lxd2_servers();
echo "<table class=\"table table-striped\">";
echo "<thead><tr><th>Container</th><th>IP address</th><th>Status</th><th>Start/Stop</th></tr></thead>";
foreach( $servers->metadata as $server ){
$start = microtime(true);
$s = lxd2_command( $server) ;
$stop = microtime(true);
echo "<tr>";
echo "<td class=\"col-md-3\">" . $s->metadata->name . "</td>";
echo "<td class=\"col-md-3\"></td>";
if( $s->metadata->status == "Running"){
echo "<td class=\"col-md-2\"><i class=\"fa fa-lg fa-power-off text-success\" aria-hidden=\"true\"></i></td>";
}
if( $s->metadata->status == "Stopped"){
echo "<td class=\"col-md-2\"><i class=\"fa fa-lg fa-power-off text-danger\" aria-hidden=\"true\"></i></td>";
}
if( $s->metadata->status == "Running"){
echo "<td class=\"col-md-4\"><a href='?a=stop&server={$s->metadata->name}'><button class=\"btn btn-default\"><i class=\"fa fa-lg fa-power-off\" aria-hidden=\"true\"></i></button></a> <a href='?a=stop&server={$s->metadata->name}'><button class=\"btn btn-default\"><i class=\"fa fa-lg fa-cog\" aria-hidden=\"true\"></i></button></a> <a href='?a=stop&server={$s->metadata->name}'><button class=\"btn btn-default\"><i class=\"fa fa-lg fa-trash\" aria-hidden=\"true\"></i></button></a></td>";
}
if( $s->metadata->status == "Stopped"){
echo "<td class=\"col-md-4\"><a href='?a=start&server={$s->metadata->name}'><button class=\"btn btn-default\"><i class=\"fa fa-lg fa-power-off\" aria-hidden=\"true\"></i></button></a> <a href='?a=start&server={$s->metadata->name}'><button class=\"btn btn-default\"><i class=\"fa fa-lg fa-cog\" aria-hidden=\"true\"></i></button></a> <a href='?a=start&server={$s->metadata->name}'><button class=\"btn btn-default\"><i class=\"fa fa-lg fa-trash\" aria-hidden=\"true\"></i></button></a></td>";
}
echo "</tr>";
}
echo "</table>";
?>
</div>
<div class="col-md-6">
</div>
</div>
<file_sep><?php
function lxd2_environmentInfo(){
return lxd2_command("/1.0");
}
function lxd2_servers(){
return lxd2_command("/1.0/containers");
}
function lxd2_server_stop( $server ){
return lxd2_command( "/1.0/containers/$server/state", array( "action" => "stop" ));
}
function lxd2_server_start( $server ){
return lxd2_command( "/1.0/containers/$server/state", array( "action" => "start" ));
}
function lxd2_server_snapshot( $server ){
return lxd2_command( "/1.0/containers/$server/snapshots");
}
function lxd2_server_delete( $server ){
return lxd2_command( "/1.0/containers/$server", false, true );
}
function lxd2_command( $command = "", $actions = false, $delete = false, $snapshot = false ){
$req = curl_init();
curl_setopt($req, CURLOPT_URL, "https://lexdee.bayton.org:8443" . $command );
curl_setopt($req, CURLOPT_SSLKEY, "../client.key");
curl_setopt($req, CURLOPT_SSLCERT, "../client.crt");
curl_setopt($req, CURLOPT_SSL_VERIFYPEER, false);
curl_setopt($req, CURLOPT_SSL_VERIFYHOST, false );
curl_setopt($req, CURLOPT_RETURNTRANSFER, true);
if( $actions ){
curl_setopt($req, CURLOPT_CUSTOMREQUEST, "PUT");
curl_setopt($req, CURLOPT_POSTFIELDS, json_encode($actions) );
}
if( $delete ){
curl_setopt($req, CURLOPT_CUSTOMREQUEST, "DELETE");
}
if( $snapshot ){
curl_setopt($req, CURLOPT_CUSTOMREQUEST, "POST");
}
$data = curl_exec($req);
$error = curl_error( $req );
curl_close($req);
if( $error != ""){
return $error;
} else {
return json_decode( $data );
}
}
?>
<file_sep><?php
$today = date("dmy");
$servers = lxd2_servers();
echo "<div class=\"row\">";
foreach( $servers->metadata as $server ){
$start = microtime(true);
$s = lxd2_command( $server) ;
$stop = microtime(true);
echo "<div class=\"col-md-3\">";
echo "<div class=\"panel panel-default col-md-12 panel-lxd\">";
echo "<div class=\"panel-heading\">" . $s->metadata->name . "</div>";
echo "<img class=\"panel-img\" src=\"resources/img/os-banners/ub-place.png\"></img>";
echo "<div class=\"panel-body\">";
if( $s->metadata->status == "Running"){
echo "<p>Status: <i class=\"fa fa-lg fa-power-off text-success\" aria-hidden=\"true\"></i></br>";
}
if( $s->metadata->status == "Stopped"){
echo "<p>Status: <i class=\"fa fa-lg fa-power-off text-danger\" aria-hidden=\"true\"></i></br>";
}
echo "Address: 192.168.0.242</br>";
echo "Created: 23.05.2016</p>";
if( $s->metadata->status == "Running"){
echo "<a href='?a=stop&server={$s->metadata->name}'><button class=\"btn btn-default\"><i class=\"fa fa-lg fa-power-off\" aria-hidden=\"true\"></i></button></a>
<button class=\"btn btn-default\" data-toggle=\"modal\" data-target=\"#lxd-settings\"><i class=\"fa fa-lg fa-cog\" aria-hidden=\"true\"></i></button>
<a href='?a=snapshot&server={$s->metadata->name}'><button class=\"btn btn-default\"><i class=\"fa fa-lg fa-copy\" aria-hidden=\"true\"></i></button></a>
<button class=\"btn btn-default\" data-toggle=\"modal\" data-target=\"#lxd-delete\"><i class=\"fa fa-lg fa-trash\" aria-hidden=\"true\"></i></button></a>";
}
if( $s->metadata->status == "Stopped"){
echo "<a href='?a=start&server={$s->metadata->name}'><button class=\"btn btn-default\"><i class=\"fa fa-lg fa-power-off\" aria-hidden=\"true\"></i></button></a>
<button class=\"btn btn-default\" data-toggle=\"modal\" data-target=\"#lxd-settings\"><i class=\"fa fa-lg fa-cog\" aria-hidden=\"true\"></i></button></a>
<a href='?a=snapshot&server={$s->metadata->name}&name=$today'><button class=\"btn btn-default\"><i class=\"fa fa-lg fa-copy\" aria-hidden=\"true\"></i></button></a>
<button class=\"btn btn-default\" data-toggle=\"modal\" data-target=\"#lxd-delete\"><i class=\"fa fa-lg fa-trash\" aria-hidden=\"true\"></i></button>";
}
echo "</div>";
echo "</div>";
echo "</div>";
}
?></div>
<!-- Settings Modal -->
<div class="modal fade" id="lxd-settings" tabindex="-1" role="dialog" aria-labelledby="myModalLabel">
<div class="modal-dialog" role="document">
<div class="modal-content">
<div class="modal-header">
<button type="button" class="close" data-dismiss="modal" aria-label="Close"><span aria-hidden="true">×</span></button>
<h4 class="modal-title" id="myModalLabel">Modal title</h4>
</div>
<div class="modal-body">
...
</div>
<div class="modal-footer">
<button type="button" class="btn btn-default" data-dismiss="modal">Close</button>
<button type="button" class="btn btn-primary">Save changes</button>
</div>
</div>
</div>
</div>
<!-- Delete Modal -->
<div class="modal fade" id="lxd-delete" tabindex="-1" role="dialog" aria-labelledby="myModalLabel">
<div class="modal-dialog" role="document">
<div class="modal-content">
<div class="modal-header">
<button type="button" class="close" data-dismiss="modal" aria-label="Close"><span aria-hidden="true">×</span></button>
<h4 class="modal-title" id="myModalLabel">Delete container?</h4>
</div>
<div class="modal-body">
<p>Are you sure you wish to permanently delete this container? This action is <strong>irreversible</strong>.</p>
</div>
<div class="modal-footer">
<button type="button" class="btn btn-default" data-dismiss="modal">Cancel</button>
<?php echo "<a href='?a=delete&server={$s->metadata->name}'><button type=\"button\" class=\"btn btn-danger\">Confirm</button></a>" ?>
</div>
</div>
</div>
</div>
<file_sep><?php
require( "helpers/init.php" );
error_reporting(E_ALL);
ini_set('display_errors', '1');
require( "connectors/lxd2.php");
if(isset($_GET['a']))
switch( $_GET['a'] ){
case "stop":
if( $_GET['server'] != ""){
prp( lxd2_server_stop( $_GET['server'] ) );
}
break;
case "start":
if( $_GET['server'] != ""){
prp( lxd2_server_start( $_GET['server'] ) );
}
break;
case "snapshot":
if( $_GET['server'] != ""){
prp( lxd2_server_snapshot( $_GET['server'], $_GET['name'] ) );
}
break;
}
$servers = lxd2_servers();
echo "<table>";
foreach( $servers->metadata as $server ){
$start = microtime(true);
$s = lxd2_command( $server) ;
$stop = microtime(true);
echo "<tr>";
echo "<td>" . $s->metadata->name . "</td>";
echo "<td>" . $s->metadata->status . "</td>";
if( $s->metadata->status == "Running"){
echo "<td><a href='?a=stop&server={$s->metadata->name}'>stop</a></td>";
}
if( $s->metadata->status == "Stopped"){
echo "<td><a href='?a=start&server={$s->metadata->name}'>start</a></td>";
}
echo "</tr>";
}
echo "</table>";
prp( $s );
?>
<file_sep>
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="utf-8">
<meta http-equiv="X-UA-Compatible" content="IE=edge">
<meta name="viewport" content="width=device-width, initial-scale=1">
<!-- The above 3 meta tags *must* come first in the head; any other head content must come *after* these tags -->
<meta name="description" content="">
<meta name="author" content="">
<link rel="apple-touch-icon" sizes="57x57" href="resources/favicons/apple-touch-icon-57x57.png">
<link rel="apple-touch-icon" sizes="60x60" href="resources/favicons/apple-touch-icon-60x60.png">
<link rel="apple-touch-icon" sizes="72x72" href="resources/favicons/apple-touch-icon-72x72.png">
<link rel="apple-touch-icon" sizes="76x76" href="resources/favicons/apple-touch-icon-76x76.png">
<link rel="apple-touch-icon" sizes="114x114" href="resources/favicons/apple-touch-icon-114x114.png">
<link rel="apple-touch-icon" sizes="120x120" href="resources/favicons/apple-touch-icon-120x120.png">
<link rel="apple-touch-icon" sizes="144x144" href="resources/favicons/apple-touch-icon-144x144.png">
<link rel="apple-touch-icon" sizes="152x152" href="resources/favicons/apple-touch-icon-152x152.png">
<link rel="apple-touch-icon" sizes="180x180" href="resources/favicons/apple-touch-icon-180x180.png">
<link rel="icon" type="image/png" href="resources/favicons/favicon-32x32.png" sizes="32x32">
<link rel="icon" type="image/png" href="resources/favicons/favicon-194x194.png" sizes="194x194">
<link rel="icon" type="image/png" href="resources/favicons/favicon-96x96.png" sizes="96x96">
<link rel="icon" type="image/png" href="resources/favicons/android-chrome-192x192.png" sizes="192x192">
<link rel="icon" type="image/png" href="resources/favicons/favicon-16x16.png" sizes="16x16">
<link rel="manifest" href="resources/favicons/manifest.json">
<link rel="mask-icon" href="resources/favicons/safari-pinned-tab.svg" color="#5bbad5">
<meta name="msapplication-TileColor" content="#da532c">
<meta name="msapplication-TileImage" content="resources/favicons/mstile-144x144.png">
<meta name="theme-color" content="#1da2db">
<title>LXD management interface</title>
<!-- Bootstrap core CSS -->
<link href="resources/bootstrap/css/bootstrap.min.css" rel="stylesheet">
<link href="https://maxcdn.bootstrapcdn.com/font-awesome/4.6.3/css/font-awesome.min.css" rel="stylesheet" integrity="<KEY>" crossorigin="anonymous">
<!-- Bayton additional CSS -->
<link href="resources/css/bayton.css" rel="stylesheet">
<!-- HTML5 shim and Respond.js for IE8 support of HTML5 elements and media queries -->
<!--[if lt IE 9]>
<script src="https://oss.maxcdn.com/html5shiv/3.7.2/html5shiv.min.js"></script>
<script src="https://oss.maxcdn.com/respond/1.4.2/respond.min.js"></script>
<![endif]-->
</head>
<body>
<?php include "modules/nav.php" ?>
<?php
require( "helpers/init.php" );
error_reporting(E_ALL);
ini_set('display_errors', '1');
require( "connectors/lxd2.php");
?>
<div class="container">
<div class="row">
<div class="col-md-4">
<?php
require( "modules/lxd2-functioncalls.php");
?>
</div>
</div>
</div>
<div class="container page-top">
<div class="row">
<div class="col-md-12">
<div class="panel panel-default">
<div class="panel-body">
<div class="search-form">
<div class="row">
<div class="col-md-9">
<div class="form-group">
<div class="col-md-7">
<input type="text" class="form-control" placeholder="Container name...">
</div>
<div class="col-md-5">
<select class="form-control">
<option>Select...</option>
<option>Ubuntu 16.04 LTS</option>
<option>Ubuntu 15.10</option>
<option>Ubuntu 14.04 LTS</option>
<option>Debian Jessie</option>
<option>CentOS 7</option>
</select>
</div>
</div>
</div>
<div class="col-md-3">
<a class="btn btn-primary btn-block" href="/companies/add" data-toggle="modal" data-target="#editModal">
<i class="fa fa-plus"></i>
<span>Add</span>
</a>
</div>
</div>
</div>
</div>
</div>
</div>
</div>
<!-- The grid view and modals -->
<?php include "modules/jblxd-grid.php" ?>
<!-- The table view and status message -->
<!--?php include "jblxd-table.php" ?-->
<div class="row">
<div class="col-md-12">
<?php
prp( $s );
?>
</div>
</div>
<!-- /.container --></div>
<!-- Bootstrap core JavaScript
================================================== -->
<!-- Placed at the end of the document so the pages load faster -->
<script src="https://ajax.googleapis.com/ajax/libs/jquery/1.11.3/jquery.min.js"></script>
<script>window.jQuery || document.write('<script src="/bootstrap/js/vendor/jquery.min.js"><\/script>')</script>
<script src="/resources/bootstrap/js/bootstrap.min.js"></script>
</body>
</html>
<file_sep>A PHP-based management interface for LXD.
jblxd.php is the current landing page.
| e85334132e935106a5875f0db3ece9ee16fa3c17 | [
"Markdown",
"PHP"
] | 6 | PHP | grsmith-projects/lexdee | 1490eea037154f6917e7ed527f187dfa8d451f26 | 9e3c9400fdb671f1761afdbec4d6441683760121 |
refs/heads/main | <file_sep>// To change theme of chat window
let changeTheme = document.getElementById('cTheme');
changeTheme.addEventListener('click', () => {
console.log('Clicked');
let themeLink = document.getElementsByTagName('link')[0];
console.log(themeLink);
console.log(themeLink.href);
console.log(changeTheme.innerText);
if (themeLink.href == 'https://chatappmaster.herokuapp.com/css/green.css') {
themeLink.href = 'https://chatappmaster.herokuapp.com/css/purple.css';
changeTheme.innerText = 'Green Theme';
} else if (themeLink.href == 'https://chatappmaster.herokuapp.com/css/purple.css') {
themeLink.href = 'https://chatappmaster.herokuapp.com/css/green.css';
changeTheme.innerText = 'Purple Theme';
}
});
// To hide/ show menu
let burger = document.getElementById('burger');
let left = document.querySelector('.left');
let right = document.querySelector('.right');
burger.addEventListener('click', () => {
left.classList.toggle('visible');
right.classList.toggle('notVisible');
});<file_sep>// Idea for now is to use user from USERS in server site
// and get display message body and message input from here
console.log('Joined to client');
const socket = io();
let displayMessage = document.querySelector('.displayMessage');
let messageInp = document.getElementById('messageInp');
let sendMsg = document.getElementById('sendMsg');
let Room = document.getElementsByClassName('room')[0];
let UName = document.getElementsByClassName('uname')[0];
let loc1 = document.getElementById('location1');
let loc2 = document.getElementById('location2');
var audio = new Audio('/sound/ting.mp3');
window.onload = function () {
var url = document.location.href;
data = url.split('?')
params = data[1].split('&');
username = params[0].split('=')[1];
room = params[1].split('=')[1];
Room.innerHTML = `# ${room}`;
UName.innerHTML = username
}
const appendAnnounce = (message, position) => {
// message announcement
// Its only for Announcement
const messageElement = document.createElement('div');
messageElement.innerText = message;
messageElement.classList.add('message');
messageElement.classList.add(position);
displayMessage.append(messageElement);
}
const appendURL = (userName, locationLink, position) => {
// Its only for location
const date = new Date();
const Hour = date.getHours();
const Min = date.getMinutes();
let elementMessage = document.createElement('div');
elementMessage.classList.add('message');
elementMessage.classList.add(position);
let elementDetails = document.createElement('div');
elementDetails.classList.add('details');
let elementUsername = document.createElement('div');
elementUsername.classList.add('username');
elementUsername.innerHTML = userName;
elementDetails.appendChild(elementUsername);
let elementTime = document.createElement('div');
elementTime.classList.add('time');
elementTime.innerHTML = `${Hour}:${Min}`;
elementDetails.appendChild(elementTime);
elementMessage.appendChild(elementDetails);
let elementHr = document.createElement('hr');
elementMessage.appendChild(elementHr);
// #####################################################
const messageLoc = document.createElement('div');
messageLoc.classList.add('message');
messageLoc.classList.add(position);
const locLink = document.createElement('a');
locLink.setAttribute('href', locationLink);
locLink.setAttribute('target', '_blank');
locLink.innerText = 'click here';
messageLoc.appendChild(locLink);
// ######################################
elementMessage.appendChild(messageLoc);
displayMessage.appendChild(elementMessage);
if (position == 'msg-left') {
audio.play();
}
displayMessage.scrollTop = displayMessage.scrollHeight - displayMessage.clientHeight;
}
const appendMessage = (userName, message, position) => {
// message msg-right msg-left announcement
if (/\S/.test(message)) {
const date = new Date();
const Hour = date.getHours();
const Min = date.getMinutes();
console.log(Hour, Min);
console.log('Add message');
let elementMessage = document.createElement('div');
elementMessage.classList.add('message');
elementMessage.classList.add(position);
let elementDetails = document.createElement('div');
elementDetails.classList.add('details');
let elementUsername = document.createElement('div');
elementUsername.classList.add('username');
elementUsername.innerHTML = userName;
elementDetails.appendChild(elementUsername);
let elementTime = document.createElement('div');
elementTime.classList.add('time');
elementTime.innerHTML = `${Hour}:${Min}`;
elementDetails.appendChild(elementTime);
elementMessage.appendChild(elementDetails);
let elementHr = document.createElement('hr');
elementMessage.appendChild(elementHr);
let elementMsgText = document.createElement('div');
elementMsgText.classList.add('text');
elementMsgText.setAttribute("id", "msg-text");
elementMsgText.innerHTML = message;
elementMessage.appendChild(elementMsgText);
displayMessage.appendChild(elementMessage);
if (position == 'msg-left') {
audio.play();
}
displayMessage.scrollTop = displayMessage.scrollHeight - displayMessage.clientHeight;
}
}
sendMsg.addEventListener('click', () => {
console.log("Clicked on send");
const message = messageInp.value;
console.log(message);
appendMessage(`You`, `${message}`, 'msg-right');
socket.emit('send', message);
messageInp.value = '';
})
loc1.addEventListener('click', () => {
let longitude;
let latitude;
if (navigator.geolocation) {
navigator.geolocation.getCurrentPosition((position) => {
console.log(position);
longitude = position.coords.longitude;
latitude = position.coords.latitude;
console.log(longitude);
console.log(latitude);
url = `http://www.google.com/maps/place/${latitude},${longitude}`
console.log(url);
appendURL('You', url, 'msg-right');
socket.emit('sendURL', url);
})
} else {
console.log('Error : Not available')
}
});
loc2.addEventListener('click', () => {
let longitude;
let latitude;
if (navigator.geolocation) {
navigator.geolocation.getCurrentPosition((position) => {
console.log(position);
longitude = position.coords.longitude;
latitude = position.coords.latitude;
console.log(longitude);
console.log(latitude);
url = `http://www.google.com/maps/place/${latitude},${longitude}`
console.log(url);
appendURL('You', url, 'msg-right');
socket.emit('sendURL', url);
})
} else {
console.log('Error : Not available')
}
});
socket.emit('new-user-joined');
socket.on('user-joined', name1 => {
appendAnnounce(`${name1} joined the chat`, 'announcement');
})
socket.on('receive', data => {
appendMessage(`${data.name}`, `${data.message}`, 'msg-left');
})
socket.on('receiveURL', data => {
appendURL(data.name, data.urlLink, 'msg-left');
})
socket.on('left', name => {
appendAnnounce(`${name} left the chat`, 'announcement');
}) | 69032795f5dc5c8ac4f4f8a166fe9cfca975ee9a | [
"JavaScript"
] | 2 | JavaScript | akshata200/ChatApp | 11f1359aadb00464c690c74665a603feb2dda4b8 | e5f47eb228d2d0f5bdc2cd425d9370f906802ca4 |
refs/heads/master | <repo_name>kasperlewau/toggl-timer-current<file_sep>/index.js
module.exports = require('./lib/toggl-timer-current');
<file_sep>/README.md
# toggl-timer-current
> Get the currently running toggl timer
## Install
```sh
$ npm install toggl-timer-current --save
```
## Usage
```js
var togglCurrent = require('toggl-timer-current');
togglCurrent(apiToken).then(timer => {
console.log(timer); // {}
});
togglCurrent(email, password).then(timer => {
console.log(timer); // {}
});
```
### API
#### togglCurrent(token, [password])
##### token
Type: `string`
Either your [Toggl API token](https://toggl.com/app/profile), or your Toggl email.
> In the case of email, the second parameter (password) is **not** optional.
##### password
Type: `string`
Your password at Toggl. Necessary if you forego your API token and authenticate using
your email instead.
## License
MIT
| fd2162e96aa17f3ff5152ee563792988a4e5adfc | [
"JavaScript",
"Markdown"
] | 2 | JavaScript | kasperlewau/toggl-timer-current | ea659e9d86ed921068fe7ec064dea1e611efc0b6 | 868e7079e509eb28b3255ba387dda2d5ee62fd55 |
refs/heads/master | <repo_name>gre90r/JAXB-Example<file_sep>/src/main/java/de/gre90r/jaxbdemo/service/BookService.java
package de.gre90r.jaxbdemo.service;
import de.gre90r.jaxbdemo.model.Book;
public interface BookService {
// /**
// * writes xml from book object into file
// * @param book will be written as xml
// */
// void marshalToXmlFile(Book book);
/**
* writes xml from book object
* @param book will be written as xml
* @return xml as string of book
*/
String marshalToString(Book book);
/**
* create book xml from title and author
* @param title book title
* @param author book author
* @return book as xml string
*/
String marshalToXmlString(String title, String author);
}
<file_sep>/src/test/java/de/gre90r/jaxbdemo/service/BookServiceTest.java
package de.gre90r.jaxbdemo.service;
import static org.junit.jupiter.api.Assertions.*;
import java.util.Date;
import javax.xml.bind.JAXBException;
import org.junit.jupiter.api.BeforeAll;
import org.junit.jupiter.api.Test;
import de.gre90r.jaxbdemo.model.Book;
import de.gre90r.jaxbdemo.service.impl.BookServiceImpl;
class BookServiceTest {
private static BookService bookService;
@BeforeAll
static void setup() throws JAXBException {
bookService = new BookServiceImpl();
}
/*******************/
/* marshalToString */
/*******************/
@Test
void marshalToString() {
Book book = new Book(1, "<NAME>", "<NAME>", new Date());
String res = bookService.marshalToString(book);
assertTrue(res.contains("<book id="));
assertTrue(res.contains("<title>"));
assertTrue(res.contains("<author>"));
assertFalse(res.contains("<date>")); // transient field
System.out.println(res);
}
}
<file_sep>/README.md
# JAXB Demo
the index.jsp offers to create a book and let it be displayed as xml
# 1 Environment
runs on a wildfly application server which is started by maven
# 2 Build and run
* buildAndRun.bat
* go to `http://localhost:8080/jaxb-demo/index.jsp`
* run test
* src/test/java/de.gre90r.jaxbdemo.service/BookServiceTest.java
| c2f712822009a41c9bffc5d8187f50c20f531674 | [
"Markdown",
"Java"
] | 3 | Java | gre90r/JAXB-Example | 88259648173cbb84ba7315164d183f1ffc50e914 | 603f3bebe2acbb12ea8fb4d656a080994f28a80e |
refs/heads/master | <repo_name>ofekbs/CyberProject-1<file_sep>/TextBox.py
import pygame
from pygame.locals import *
class TextBox:
def __init__(self, x, y, width, surf):
self.box = pygame.Rect(x, y, width, 100)
pygame.draw.rect(surf, (255, 0, 0), self.box)
<file_sep>/Room.py
from Screen import Screen
class Room(Screen):
def __init__(self, room_id, bg_image, path, out):
Screen.__init__(self, room_id, bg_image)
self.path = path
self.out = out
self.players = []
<file_sep>/World.py
import pygame
from pygame.locals import *
class World:
def __init__(self): # Hello World!
self.SIZE = (640, 480)
self.SURF = pygame.display.set_mode(self.SIZE)
self.cur_screen = None
<file_sep>/Player.py
from World import World
class Player:
def __init__(self, username, is_male, items, level, join_date, is_admin, room_id, room_pos):
self.username = username
self.is_male = is_male
self.items = items
self.level = level
self.join_date = join_date
self.is_admin = is_admin
self.room_id = room_id
self.room_pos = room_pos
<file_sep>/Item.py
from World import World
class Item:
def __init__(self, image, name, id, is_male, is_used, min_level):
self.image = image
self.name = name
self.id = id
self.is_male = is_male
self.is_used = is_used
self.min_level = min_level
<file_sep>/README.md
# CyberProject
Final project in cyber class.
<file_sep>/Login.py
import pygame
from pygame.locals import *
import sys
import TextBox
pygame.init()
DISPLAY_SURF = pygame.display.set_mode((640, 480))
pygame.display.set_caption("Cyber!")
tb = TextBox.TextBox(100, 100, 300, DISPLAY_SURF)
while True:
for event in pygame.event.get():
if event.type == QUIT:
pygame.quit()
sys.exit()
pygame.display.update()
<file_sep>/Screen.py
from World import World
class Screen:
def __init__(self, screen_id, image):
self.screen_id = screen_id
self.image = image
| aca3d319e7b6bd6e857d3cfa674fc3b35d740c28 | [
"Markdown",
"Python"
] | 8 | Python | ofekbs/CyberProject-1 | 973f54ac2886ecf7d969c7ef1661a9bfb7c7d4d7 | 648d93ce67991c990636eb2835dd0374ebd7ea40 |
refs/heads/master | <repo_name>trandinhson2112cntt/Web_Datamining_Hutech<file_sep>/Web_Datamining/Web_Datamining.Web/Areas/Admin/Controllers/LopsController.cs
using System;
using System.Collections.Generic;
using System.Data;
using System.Data.Entity;
using System.Linq;
using System.Net;
using System.Web;
using System.Web.Mvc;
using Web_Datamining.Data;
using Web_Datamining.Models;
namespace Web_Datamining.Web.Areas.Admin.Controllers
{
public class LopsController : Controller
{
private WebDbContext db = new WebDbContext();
// GET: Admin/Lops
public ActionResult Index()
{
var lops = db.Lops.Include(l => l.ChuyenNganh).Include(l => l.HeDaoTao).Include(l => l.KhoaHoc);
return View(lops.ToList());
}
// GET: Admin/Lops/Details/5
public ActionResult Details(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
Lop lop = db.Lops.Find(id);
if (lop == null)
{
return HttpNotFound();
}
return View(lop);
}
// GET: Admin/Lops/Create
public ActionResult Create()
{
ViewBag.MaChuyenNganh = new SelectList(db.ChuyenNganhs, "MaChuyenNganh", "TenChuyenNganh");
ViewBag.MaHeDaoTao = new SelectList(db.HeDaoTaos, "MaHeDaoTao", "TenHeDaoTao");
ViewBag.MaKhoaHoc = new SelectList(db.KhoaHocs, "MaKhoaHoc", "NamHoc");
return View();
}
// POST: Admin/Lops/Create
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Create([Bind(Include = "ID_Lop,MaChuyenNganh,MaHeDaoTao,MaKhoaHoc,TenLop")] Lop lop)
{
if (ModelState.IsValid)
{
db.Lops.Add(lop);
db.SaveChanges();
return RedirectToAction("Index");
}
ViewBag.MaChuyenNganh = new SelectList(db.ChuyenNganhs, "MaChuyenNganh", "TenChuyenNganh", lop.MaChuyenNganh);
ViewBag.MaHeDaoTao = new SelectList(db.HeDaoTaos, "MaHeDaoTao", "TenHeDaoTao", lop.MaHeDaoTao);
ViewBag.MaKhoaHoc = new SelectList(db.KhoaHocs, "MaKhoaHoc", "NamHoc", lop.MaKhoaHoc);
return View(lop);
}
// GET: Admin/Lops/Edit/5
public ActionResult Edit(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
Lop lop = db.Lops.Find(id);
if (lop == null)
{
return HttpNotFound();
}
ViewBag.MaChuyenNganh = new SelectList(db.ChuyenNganhs, "MaChuyenNganh", "TenChuyenNganh", lop.MaChuyenNganh);
ViewBag.MaHeDaoTao = new SelectList(db.HeDaoTaos, "MaHeDaoTao", "TenHeDaoTao", lop.MaHeDaoTao);
ViewBag.MaKhoaHoc = new SelectList(db.KhoaHocs, "MaKhoaHoc", "NamHoc", lop.MaKhoaHoc);
return View(lop);
}
// POST: Admin/Lops/Edit/5
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Edit([Bind(Include = "ID_Lop,MaChuyenNganh,MaHeDaoTao,MaKhoaHoc,TenLop")] Lop lop)
{
if (ModelState.IsValid)
{
db.Entry(lop).State = EntityState.Modified;
db.SaveChanges();
return RedirectToAction("Index");
}
ViewBag.MaChuyenNganh = new SelectList(db.ChuyenNganhs, "MaChuyenNganh", "TenChuyenNganh", lop.MaChuyenNganh);
ViewBag.MaHeDaoTao = new SelectList(db.HeDaoTaos, "MaHeDaoTao", "TenHeDaoTao", lop.MaHeDaoTao);
ViewBag.MaKhoaHoc = new SelectList(db.KhoaHocs, "MaKhoaHoc", "NamHoc", lop.MaKhoaHoc);
return View(lop);
}
// GET: Admin/Lops/Delete/5
public ActionResult Delete(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
Lop lop = db.Lops.Find(id);
if (lop == null)
{
return HttpNotFound();
}
return View(lop);
}
// POST: Admin/Lops/Delete/5
[HttpPost, ActionName("Delete")]
[ValidateAntiForgeryToken]
public ActionResult DeleteConfirmed(int id)
{
Lop lop = db.Lops.Find(id);
db.Lops.Remove(lop);
db.SaveChanges();
return RedirectToAction("Index");
}
protected override void Dispose(bool disposing)
{
if (disposing)
{
db.Dispose();
}
base.Dispose(disposing);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/ToHopMon.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("ToHopMon")]
public class ToHopMon
{
[Key]
[StringLength(5)]
public string MaToHop { get; set; }
[StringLength(20)]
public string Mon1 { get; set; }
[StringLength(20)]
public string Mon2 { get; set; }
[StringLength(20)]
public string Mon3 { get; set; }
public virtual ICollection<DSNguyenVong> DSNguyenVong { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Migrations/201810180303564_AddTableChuongTrinhDaoTao.cs
namespace Web_Datamining.Data.Migrations
{
using System;
using System.Data.Entity.Migrations;
public partial class AddTableChuongTrinhDaoTao : DbMigration
{
public override void Up()
{
CreateTable(
"dbo.ChungTrinhDaoTao",
c => new
{
KhoaID = c.Int(nullable: false),
HocKyID = c.Int(nullable: false),
MonHocID = c.Int(nullable: false),
HocKy_ID_HocKi = c.Int(),
Khoa_MaKhoa = c.String(maxLength: 10),
MonHoc_MaMon = c.String(maxLength: 10),
})
.PrimaryKey(t => new { t.KhoaID, t.HocKyID, t.MonHocID })
.ForeignKey("dbo.HocKy", t => t.HocKy_ID_HocKi)
.ForeignKey("dbo.Khoa", t => t.Khoa_MaKhoa)
.ForeignKey("dbo.MonHoc", t => t.MonHoc_MaMon)
.Index(t => t.HocKy_ID_HocKi)
.Index(t => t.Khoa_MaKhoa)
.Index(t => t.MonHoc_MaMon);
}
public override void Down()
{
DropForeignKey("dbo.ChungTrinhDaoTao", "MonHoc_MaMon", "dbo.MonHoc");
DropForeignKey("dbo.ChungTrinhDaoTao", "Khoa_MaKhoa", "dbo.Khoa");
DropForeignKey("dbo.ChungTrinhDaoTao", "HocKy_ID_HocKi", "dbo.HocKy");
DropIndex("dbo.ChungTrinhDaoTao", new[] { "MonHoc_MaMon" });
DropIndex("dbo.ChungTrinhDaoTao", new[] { "Khoa_MaKhoa" });
DropIndex("dbo.ChungTrinhDaoTao", new[] { "HocKy_ID_HocKi" });
DropTable("dbo.ChungTrinhDaoTao");
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/ChuongTrinhDaoTao.cs
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
using Web_Datamining.Models;
namespace Web_Datamining.Models
{
[Table("ChuongTrinhDaoTao")]
public class ChuongTrinhDaoTao
{
[Key]
[Column(Order = 0)]
public string MaKhoa { get; set; }
[Key]
[Column(Order = 1)]
public int ID_HocKi { get; set; }
[Key]
[Column(Order = 2)]
public string MaMon { get; set; }
[ForeignKey("MaKhoa")]
public virtual Khoa Khoa { get; set; }
[ForeignKey("ID_HocKi")]
public virtual HocKy HocKy { get; set; }
[ForeignKey("MaMon")]
public virtual MonHoc MonHoc { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Web/Areas/Admin/Controllers/ImportExcelController.cs
using LinqToExcel;
using System;
using System.Collections.Generic;
using System.Data;
using System.Data.Entity.Validation;
using System.Data.OleDb;
using System.Linq;
using System.Web;
using System.Web.Mvc;
using Web_Datamining.Data;
using Web_Datamining.Models;
namespace Web_Datamining.Web.Areas.Admin.Controllers
{
public class ImportExcelController : Controller
{
public ActionResult Index()
{
return View();
}
// GET: ImportExcel
public FileResult DownloadExcelSinhVienForMat()
{
string path = "/ExcelFormat/Students.xlsx";
return File(path, "application/vnd.ms-excel", "Students.xlsx");
}
[HttpPost]
public ActionResult UploadExcelSinhVien(SinhVien students, HttpPostedFileBase FileUpload)
{
WebDbContext db = new WebDbContext();
List<string> data = new List<string>();
if (FileUpload != null)
{
// tdata.ExecuteCommand("truncate table OtherCompanyAssets");
if (FileUpload.ContentType == "application/vnd.ms-excel" || FileUpload.ContentType == "application/vnd.openxmlformats-officedocument.spreadsheetml.sheet")
{
string filename = FileUpload.FileName;
string targetpath = Server.MapPath("~/ExcelFormat/");
FileUpload.SaveAs(targetpath + filename);
string pathToExcelFile = targetpath + filename;
var connectionString = "";
if (filename.EndsWith(".xls"))
{
connectionString = string.Format("Provider=Microsoft.Jet.OLEDB.4.0; data source={0}; Extended Properties=Excel 8.0;", pathToExcelFile);
}
else if (filename.EndsWith(".xlsx"))
{
connectionString = string.Format("Provider=Microsoft.ACE.OLEDB.12.0;Data Source={0};Extended Properties=\"Excel 12.0 Xml;HDR=YES;IMEX=1\";", pathToExcelFile);
}
var adapter = new OleDbDataAdapter("SELECT * FROM [Sheet1$]", connectionString);
var ds = new DataSet();
try
{
adapter.Fill(ds, "ExcelTable");
}
catch(Exception ex)
{
ViewBag.ErrorMessage = "Excel file has wrong format. Please try another one.";
}
DataTable dtable = ds.Tables["ExcelTable"];
string sheetName = "Sheet1";
var excelFile = new ExcelQueryFactory(pathToExcelFile);
var artistAlbums = from a in excelFile.Worksheet<SinhVien>(sheetName) select a;
foreach (var a in artistAlbums)
{
try
{
if (a.MSSV != "" && a.MaHoSo != 0 && a.ID_Lop != 0)
{
SinhVien TU = new SinhVien();
TU.MSSV = a.MSSV;
TU.MaHoSo = a.MaHoSo;
TU.CoVanHocTap = a.CoVanHocTap;
TU.ID_Lop = a.ID_Lop;
db.SinhViens.Add(TU);
db.SaveChanges();
}
else
{
data.Add("<ul>");
if (a.MSSV == "" || a.MSSV == null) data.Add("<li> MSSV is required</li>");
if (a.MaHoSo == 0 || a.MaHoSo == null) data.Add("<li> MaHoSo is required</li>");
if (a.ID_Lop == 0 || a.ID_Lop == null) data.Add("<li>IP_Lop is required</li>");
data.Add("</ul>");
data.ToArray();
return Json(data, JsonRequestBehavior.AllowGet);
}
}
catch (DbEntityValidationException ex)
{
foreach (var entityValidationErrors in ex.EntityValidationErrors)
{
foreach (var validationError in entityValidationErrors.ValidationErrors)
{
Response.Write("Property: " + validationError.PropertyName + " Error: " + validationError.ErrorMessage);
}
}
}
}
//deleting excel file from folder
if ((System.IO.File.Exists(pathToExcelFile)))
{
System.IO.File.Delete(pathToExcelFile);
}
return RedirectToAction("Index","SinhViens");
}
else
{
//alert message for invalid file format
data.Add("<ul>");
data.Add("<li> Only Excel file format is allowed </li>");
data.Add("</ul>");
data.ToArray();
return Json(data, JsonRequestBehavior.AllowGet);
}
}
else
{
data.Add("<ul>");
if (FileUpload == null) data.Add("<li> Please choose Excel file </li>");
data.Add("</ul>");
data.ToArray();
return Json(data, JsonRequestBehavior.AllowGet);
}
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Migrations/201810180320224_EditNameTableChuongTrinhDaoTao.cs
namespace Web_Datamining.Data.Migrations
{
using System;
using System.Data.Entity.Migrations;
public partial class EditNameTableChuongTrinhDaoTao : DbMigration
{
public override void Up()
{
RenameTable(name: "dbo.ChungTrinhDaoTao", newName: "ChuongTrinhDaoTao");
}
public override void Down()
{
RenameTable(name: "dbo.ChuongTrinhDaoTao", newName: "ChungTrinhDaoTao");
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Service/Khoa.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Data.Repositories;
using Web_Datamining.Models;
namespace Web_Datamining.Service
{
public interface IKhoaService
{
Khoa Add(Khoa Khoa);
void Update(Khoa Khoa);
Khoa Delete(int id);
Khoa DeleteItem(Khoa item);
IEnumerable<Khoa> GetAll();
IEnumerable<Khoa> GetAll(string keyword);
Khoa GetById(int id);
void Save();
}
public class KhoaService : IKhoaService
{
private IKhoaRepository _KhoaRepository;
private IUnitOfWork _unitOfWork;
public KhoaService(IKhoaRepository KhoaRepository, IUnitOfWork unitOfWork)
{
this._KhoaRepository = KhoaRepository;
this._unitOfWork = unitOfWork;
}
public Khoa Add(Khoa Khoa)
{
return _KhoaRepository.Add(Khoa);
}
public Khoa Delete(int id)
{
return _KhoaRepository.Delete(id);
}
public Khoa DeleteItem(Khoa item)
{
return _KhoaRepository.Delete(item);
}
public IEnumerable<Khoa> GetAll()
{
return _KhoaRepository.GetAll();
}
public IEnumerable<Khoa> GetAll(string keyword)
{
if (!string.IsNullOrEmpty(keyword))
{
return _KhoaRepository.GetMulti(x => x.TenKhoa.Contains(keyword));
}
else
{
return _KhoaRepository.GetAll();
}
}
public Khoa GetById(int id)
{
return _KhoaRepository.GetSingleById(id);
}
public void Save()
{
_unitOfWork.Commit();
}
public void Update(Khoa Khoa)
{
_KhoaRepository.Update(Khoa);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Web/Api/DataController.cs
using AutoMapper;
using System.Collections.Generic;
using System.Linq;
using System.Net;
using System.Net.Http;
using System.Web.Mvc;
using Web_Datamining.Models;
using Web_Datamining.Service;
using Web_Datamining.Web.Infrastructure.Core;
using Web_Datamining.Web.Models;
namespace Web_Datamining.Web.Api
{
[RoutePrefix("api/data")]
[AllowCrossSiteJson]
public class DataController : ApiControllerBase
{
#region Contructor
private IKhoaService _khoaService;
private IMonHocService _monHocService;
public DataController(IErrorService errorService, IKhoaService khoaService, IMonHocService monHocService) : base(errorService)
{
this._khoaService = khoaService;
this._monHocService = monHocService;
}
#endregion Contructor
#region Api lấy sử dụng lấy danh sách tất cả các khoa
[Route("getallkhoa")]
[HttpGet]
public HttpResponseMessage GetAllKhoa(HttpRequestMessage request)
{
return CreateHttpResponse(request, () =>
{
int totalRow = 0;
var model = _khoaService.GetAll();
totalRow = model.Count();
var query = model.OrderByDescending(x => x.TenKhoa);
var responseData = Mapper.Map<IEnumerable<Khoa>, List<KhoaViewModel>>(query);
var response = request.CreateResponse(HttpStatusCode.OK, responseData);
return response;
});
}
#endregion Api lấy sử dụng lấy danh sách tất cả các khoa
#region Api lấy sử dụng lấy danh sách tất cả các môn học
[Route("getallmonhoc")]
[HttpGet]
public HttpResponseMessage GetAllMonHoc(HttpRequestMessage request)
{
return CreateHttpResponse(request, () =>
{
int totalRow = 0;
var model = _monHocService.GetAll();
totalRow = model.Count();
var query = model.OrderByDescending(x => x.TenMon);
var responseData = Mapper.Map<IEnumerable<MonHoc>, List<MonHocViewModel>>(query);
var response = request.CreateResponse(HttpStatusCode.OK, responseData);
return response;
});
}
#endregion Api lấy sử dụng lấy danh sách tất cả các môn học
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/LuatXetTuyenRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface ILoaiLuatnRepository : IRepository<LoaiLuat>
{
}
public class LoaiLuatRepository : RepositoryBase<LoaiLuat>, ILoaiLuatnRepository
{
public LoaiLuatRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Migrations/201810210735069_TaoKhoaNgoaiMaKhoaTableLop_Khoa.cs
namespace Web_Datamining.Data.Migrations
{
using System;
using System.Data.Entity.Migrations;
public partial class TaoKhoaNgoaiMaKhoaTableLop_Khoa : DbMigration
{
public override void Up()
{
AddColumn("dbo.MonHoc", "MaKhoa", c => c.String(maxLength: 10));
AddColumn("dbo.Lop", "MaKhoa", c => c.String(maxLength: 10));
CreateIndex("dbo.MonHoc", "MaKhoa");
CreateIndex("dbo.Lop", "MaKhoa");
AddForeignKey("dbo.Lop", "MaKhoa", "dbo.Khoa", "MaKhoa");
AddForeignKey("dbo.MonHoc", "MaKhoa", "dbo.Khoa", "MaKhoa");
}
public override void Down()
{
DropForeignKey("dbo.MonHoc", "MaKhoa", "dbo.Khoa");
DropForeignKey("dbo.Lop", "MaKhoa", "dbo.Khoa");
DropIndex("dbo.Lop", new[] { "MaKhoa" });
DropIndex("dbo.MonHoc", new[] { "MaKhoa" });
DropColumn("dbo.Lop", "MaKhoa");
DropColumn("dbo.MonHoc", "MaKhoa");
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/LuatRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface ILuatRepository : IRepository<Luat>
{
}
public class LuatRepository : RepositoryBase<Luat>, ILuatRepository
{
public LuatRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Model/Models/NganhTheoBo.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("NganhTheoBo")]
public class NganhTheoBo
{
[Key]
[StringLength(50)]
public string MaNganh { get; set; }
[StringLength(50)]
public string TeNganh { get; set; }
public virtual ICollection<DSNguyenVong> DSNguyenVong { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/NganhTheoBoRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface INganhTheoBoRepository : IRepository<NganhTheoBo>
{
}
public class NganhTheoBoRepository : RepositoryBase<NganhTheoBo>, INganhTheoBoRepository
{
public NganhTheoBoRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/Areas/Admin/Controllers/LuatXetTuyensController.cs
using System;
using System.Collections.Generic;
using System.Data;
using System.Data.Entity;
using System.Linq;
using System.Net;
using System.Web;
using System.Web.Mvc;
using Web_Datamining.Data;
using Web_Datamining.Models;
namespace Web_Datamining.Web.Areas.Admin.Controllers
{
//public class LuatXetTuyensController : Controller
//{
// private WebDbContext db = new WebDbContext();
// // GET: Admin/LuatXetTuyens
// public ActionResult Index()
// {
// return View(db.LuatXetTuyens.ToList());
// }
// // GET: Admin/LuatXetTuyens/Details/5
// public ActionResult Details(int? id)
// {
// if (id == null)
// {
// return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
// }
// LoaiLuat luatXetTuyen = db.LuatXetTuyens.Find(id);
// if (luatXetTuyen == null)
// {
// return HttpNotFound();
// }
// return View(luatXetTuyen);
// }
// // GET: Admin/LuatXetTuyens/Create
// public ActionResult Create()
// {
// return View();
// }
// // POST: Admin/LuatXetTuyens/Create
// // To protect from overposting attacks, please enable the specific properties you want to bind to, for
// // more details see http://go.microsoft.com/fwlink/?LinkId=317598.
// [HttpPost]
// [ValidateAntiForgeryToken]
// public ActionResult Create([Bind(Include = "Id,X,Y,Support,Confidence")] LoaiLuat luatXetTuyen)
// {
// if (ModelState.IsValid)
// {
// db.LuatXetTuyens.Add(luatXetTuyen);
// db.SaveChanges();
// return RedirectToAction("Index");
// }
// return View(luatXetTuyen);
// }
// // GET: Admin/LuatXetTuyens/Edit/5
// public ActionResult Edit(int? id)
// {
// if (id == null)
// {
// return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
// }
// LuatXetTuyen luatXetTuyen = db.LuatXetTuyens.Find(id);
// if (luatXetTuyen == null)
// {
// return HttpNotFound();
// }
// return View(luatXetTuyen);
// }
// // POST: Admin/LuatXetTuyens/Edit/5
// // To protect from overposting attacks, please enable the specific properties you want to bind to, for
// // more details see http://go.microsoft.com/fwlink/?LinkId=317598.
// [HttpPost]
// [ValidateAntiForgeryToken]
// public ActionResult Edit([Bind(Include = "Id,X,Y,Support,Confidence")] LuatXetTuyen luatXetTuyen)
// {
// if (ModelState.IsValid)
// {
// db.Entry(luatXetTuyen).State = EntityState.Modified;
// db.SaveChanges();
// return RedirectToAction("Index");
// }
// return View(luatXetTuyen);
// }
// // GET: Admin/LuatXetTuyens/Delete/5
// public ActionResult Delete(int? id)
// {
// if (id == null)
// {
// return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
// }
// LuatXetTuyen luatXetTuyen = db.LuatXetTuyens.Find(id);
// if (luatXetTuyen == null)
// {
// return HttpNotFound();
// }
// return View(luatXetTuyen);
// }
// // POST: Admin/LuatXetTuyens/Delete/5
// [HttpPost, ActionName("Delete")]
// [ValidateAntiForgeryToken]
// public ActionResult DeleteConfirmed(int id)
// {
// LuatXetTuyen luatXetTuyen = db.LuatXetTuyens.Find(id);
// db.LuatXetTuyens.Remove(luatXetTuyen);
// db.SaveChanges();
// return RedirectToAction("Index");
// }
// protected override void Dispose(bool disposing)
// {
// if (disposing)
// {
// db.Dispose();
// }
// base.Dispose(disposing);
// }
//}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/HuyenRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IHuyenRepository : IRepository<Huyen>
{
}
public class HuyenRepository : RepositoryBase<Huyen>, IHuyenRepository
{
public HuyenRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/Apriori/clssApriori.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
namespace Web_Datamining.Web
{
class clssApriori
{
public static ClssItemCollection DoApriori(ClssItemCollection db, double supportThreshold)
{
clssItemSet I = db.GetUniqueItems();
ClssItemCollection L = new ClssItemCollection(); // tập dữ liệu phổ biến
ClssItemCollection Li = new ClssItemCollection();//tập dữ liệu
ClssItemCollection Ci = new ClssItemCollection(); //tập dữ liệu được lược bớt
//Duyệt sự lặp lại đầu tiên của phần tử trong tập dữ liệu
foreach (string item in I)
{
Ci.Add(new clssItemSet() { item });
}
//Sự lặp lại các lần kế tiếp
int k = 2;
while (Ci.Count != 0)
{
//Lấy Li từ Ci (phần tử được lược bỏ)
Li.Clear();
foreach (clssItemSet itemset in Ci)
{
itemset.Support = db.FindSupport(itemset);
if (itemset.Support >= supportThreshold)
{
Li.Add(itemset);
L.Add(itemset);
}
}
Ci.Clear();
Ci.AddRange(clssBit.FindSubsets(Li.GetUniqueItems(), k));
k += 1;
}
return (L);
}
public static List<ClssRules> Mine(ClssItemCollection db, ClssItemCollection L, double confidenceThreshold)
{
List<ClssRules> allRules = new List<ClssRules>();
foreach (clssItemSet itemset in L)
{
ClssItemCollection subsets = clssBit.FindSubsets(itemset, 0);
foreach (clssItemSet subset in subsets)
{
double confidence = (db.FindSupport(itemset) / db.FindSupport(subset)) * 100.0;
if (confidence >= confidenceThreshold)
{
ClssRules rule = new ClssRules();
rule.X.AddRange(subset);
rule.Y.AddRange(itemset.Remove(subset));
rule.Support = db.FindSupport(itemset);
rule.Confidence = confidence;
if (rule.X.Count > 0 && rule.Y.Count > 0)
{
allRules.Add(rule);
}
}
}
}
return (allRules);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Web/Areas/Admin/Controllers/HuyensController.cs
using System;
using System.Collections.Generic;
using System.Data;
using System.Data.Entity;
using System.Linq;
using System.Net;
using System.Web;
using System.Web.Mvc;
using Web_Datamining.Data;
using Web_Datamining.Models;
namespace Web_Datamining.Web.Areas.Admin.Controllers
{
public class HuyensController : Controller
{
private WebDbContext db = new WebDbContext();
// GET: Admin/Huyens
public ActionResult Index()
{
var huyens = db.Huyens.Include(h => h.Tinh);
return View(huyens.ToList());
}
// GET: Admin/Huyens/Details/5
public ActionResult Details(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
Huyen huyen = db.Huyens.Find(id);
if (huyen == null)
{
return HttpNotFound();
}
return View(huyen);
}
// GET: Admin/Huyens/Create
public ActionResult Create()
{
ViewBag.MaTinh = new SelectList(db.Tinhs, "MaTinh", "TenTinh");
return View();
}
// POST: Admin/Huyens/Create
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Create([Bind(Include = "MaHuyen,MaTinh,khuvuc,TenHuyen")] Huyen huyen)
{
if (ModelState.IsValid)
{
db.Huyens.Add(huyen);
db.SaveChanges();
return RedirectToAction("Index");
}
ViewBag.MaTinh = new SelectList(db.Tinhs, "MaTinh", "TenTinh", huyen.MaTinh);
return View(huyen);
}
// GET: Admin/Huyens/Edit/5
public ActionResult Edit(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
Huyen huyen = db.Huyens.Find(id);
if (huyen == null)
{
return HttpNotFound();
}
ViewBag.MaTinh = new SelectList(db.Tinhs, "MaTinh", "TenTinh", huyen.MaTinh);
return View(huyen);
}
// POST: Admin/Huyens/Edit/5
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Edit([Bind(Include = "MaHuyen,MaTinh,khuvuc,TenHuyen")] Huyen huyen)
{
if (ModelState.IsValid)
{
db.Entry(huyen).State = EntityState.Modified;
db.SaveChanges();
return RedirectToAction("Index");
}
ViewBag.MaTinh = new SelectList(db.Tinhs, "MaTinh", "TenTinh", huyen.MaTinh);
return View(huyen);
}
// GET: Admin/Huyens/Delete/5
public ActionResult Delete(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
Huyen huyen = db.Huyens.Find(id);
if (huyen == null)
{
return HttpNotFound();
}
return View(huyen);
}
// POST: Admin/Huyens/Delete/5
[HttpPost, ActionName("Delete")]
[ValidateAntiForgeryToken]
public ActionResult DeleteConfirmed(int id)
{
Huyen huyen = db.Huyens.Find(id);
db.Huyens.Remove(huyen);
db.SaveChanges();
return RedirectToAction("Index");
}
protected override void Dispose(bool disposing)
{
if (disposing)
{
db.Dispose();
}
base.Dispose(disposing);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/Khoa.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("Khoa")]
public class Khoa
{
[Key]
[StringLength(10)]
public string MaKhoa { get; set; }
[StringLength(50)]
public string TenKhoa { get; set; }
public virtual ICollection<ChuyenNganh> ChuyenNganh { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/DSNguyenVongRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IDSNguyenVongRepository : IRepository<DSNguyenVong>
{
}
public class DSNguyenVongRepository : RepositoryBase<DSNguyenVong>, IDSNguyenVongRepository
{
public DSNguyenVongRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Model/Models/Tinh.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("Tinh")]
public class Tinh
{
[Key]
[DatabaseGenerated(DatabaseGeneratedOption.None)]
public int MaTinh { get; set; }
[StringLength(50)]
public string TenTinh { get; set; }
[StringLength(20)]
public string KhuVuc { get; set; }
public virtual ICollection<Huyen> Huyen { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/ChuyenNganh.cs
namespace Web_Datamining.Models
{
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
[Table("ChuyenNganh")]
public class ChuyenNganh
{
[Key]
[StringLength(10)]
public string MaChuyenNganh { get; set; }
[StringLength(50)]
public string TenChuyenNganh { get; set; }
[Required]
[StringLength(10)]
public string MaKhoa { get; set; }
public virtual Khoa Khoa { get; set; }
public virtual ICollection<Lop> Lop { get; set; }
}
}<file_sep>/Web_Datamining/Web_Datamining.Model/Models/Luat.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("Luat")]
public class Luat
{
[Key]
public int Id { get; set; }
[StringLength(100)]
public string X { get; set; }
[StringLength(100)]
public string Y { get; set; }
public decimal? Support { get; set; }
public decimal? Confidence { get; set; }
public int? LuatId { get; set; }
[ForeignKey("LuatId")]
public virtual LoaiLuat LoaiLuat { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Web/Mappings/AutoMapperConfiguration.cs
using AutoMapper;
using System;
using System.Collections.Generic;
using System.Linq;
using System.Web;
using Web_Datamining.Models;
using Web_Datamining.Web.Models;
namespace Web_Datamining.Web.Mappings
{
public class AutoMapperConfiguration
{
public static void Configure()
{
Mapper.CreateMap<Luat, LuatViewModel>();
Mapper.CreateMap<Khoa, KhoaViewModel>();
Mapper.CreateMap<MonHoc, MonHocViewModel>();
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/Areas/Admin/Controllers/DiemCTHKiesController.cs
using System;
using System.Collections.Generic;
using System.Data;
using System.Data.Entity;
using System.Linq;
using System.Net;
using System.Web;
using System.Web.Mvc;
using Web_Datamining.Data;
using Web_Datamining.Models;
namespace Web_Datamining.Web.Areas.Admin.Controllers
{
public class DiemCTHKiesController : Controller
{
private WebDbContext db = new WebDbContext();
// GET: Admin/DiemCTHKies
public ActionResult Index()
{
var diemCTHKys = db.DiemCTHKys.Include(d => d.DiemHocKy).Include(d => d.MonHoc);
return View(diemCTHKys.ToList());
}
// GET: Admin/DiemCTHKies/Details/5
public ActionResult Details(string id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DiemCTHKy diemCTHKy = db.DiemCTHKys.Find(id);
if (diemCTHKy == null)
{
return HttpNotFound();
}
return View(diemCTHKy);
}
// GET: Admin/DiemCTHKies/Create
public ActionResult Create()
{
ViewBag.MSSV = new SelectList(db.DiemHocKys, "MSSV", "MSSV");
ViewBag.MaMon = new SelectList(db.MonHocs, "MaMon", "TenMon");
return View();
}
// POST: Admin/DiemCTHKies/Create
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Create([Bind(Include = "MaMon,MSSV,ID_HocKi,DiemTH,DiemQT,DiemThi1,DiemThi2,TiLeDiemTH,TiLeDiemQT,TiLeDiemThi1,TiLeDiemThi2,DiemTKHe10,DiemTKHe4,DiemTKChu")] DiemCTHKy diemCTHKy)
{
if (ModelState.IsValid)
{
db.DiemCTHKys.Add(diemCTHKy);
db.SaveChanges();
return RedirectToAction("Index");
}
ViewBag.MSSV = new SelectList(db.DiemHocKys, "MSSV", "MSSV", diemCTHKy.MSSV);
ViewBag.MaMon = new SelectList(db.MonHocs, "MaMon", "TenMon", diemCTHKy.MaMon);
return View(diemCTHKy);
}
// GET: Admin/DiemCTHKies/Edit/5
public ActionResult Edit(string id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DiemCTHKy diemCTHKy = db.DiemCTHKys.Find(id);
if (diemCTHKy == null)
{
return HttpNotFound();
}
ViewBag.MSSV = new SelectList(db.DiemHocKys, "MSSV", "MSSV", diemCTHKy.MSSV);
ViewBag.MaMon = new SelectList(db.MonHocs, "MaMon", "TenMon", diemCTHKy.MaMon);
return View(diemCTHKy);
}
// POST: Admin/DiemCTHKies/Edit/5
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Edit([Bind(Include = "MaMon,MSSV,ID_HocKi,DiemTH,DiemQT,DiemThi1,DiemThi2,TiLeDiemTH,TiLeDiemQT,TiLeDiemThi1,TiLeDiemThi2,DiemTKHe10,DiemTKHe4,DiemTKChu")] DiemCTHKy diemCTHKy)
{
if (ModelState.IsValid)
{
db.Entry(diemCTHKy).State = EntityState.Modified;
db.SaveChanges();
return RedirectToAction("Index");
}
ViewBag.MSSV = new SelectList(db.DiemHocKys, "MSSV", "MSSV", diemCTHKy.MSSV);
ViewBag.MaMon = new SelectList(db.MonHocs, "MaMon", "TenMon", diemCTHKy.MaMon);
return View(diemCTHKy);
}
// GET: Admin/DiemCTHKies/Delete/5
public ActionResult Delete(string id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DiemCTHKy diemCTHKy = db.DiemCTHKys.Find(id);
if (diemCTHKy == null)
{
return HttpNotFound();
}
return View(diemCTHKy);
}
// POST: Admin/DiemCTHKies/Delete/5
[HttpPost, ActionName("Delete")]
[ValidateAntiForgeryToken]
public ActionResult DeleteConfirmed(string id)
{
DiemCTHKy diemCTHKy = db.DiemCTHKys.Find(id);
db.DiemCTHKys.Remove(diemCTHKy);
db.SaveChanges();
return RedirectToAction("Index");
}
protected override void Dispose(bool disposing)
{
if (disposing)
{
db.Dispose();
}
base.Dispose(disposing);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/SinhVien.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("SinhVien")]
public class SinhVien
{
[Key]
[StringLength(15)]
public string MSSV { get; set; }
public int MaHoSo { get; set; }
[Column(TypeName = "ntext")]
public string CoVanHocTap { get; set; }
public int ID_Lop { get; set; }
public virtual ICollection<DiemHocKy> DiemHocKy { get; set; }
public virtual HoSoXetTuyen HoSoXetTuyen { get; set; }
public virtual Lop Lop { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Web/Models/MonHocViewModel.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Web;
namespace Web_Datamining.Web.Models
{
public class MonHocViewModel
{
public string MaMon { get; set; }
public string MaKhoa { get; set; }
public string TenMon { get; set; }
public bool? TichLuy { get; set; }
public double? DiemDat { get; set; }
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Migrations/201811250650425_KhaoSat.cs
namespace Web_Datamining.Data.Migrations
{
using System;
using System.Data.Entity.Migrations;
public partial class KhaoSat : DbMigration
{
public override void Up()
{
CreateTable(
"dbo.KhaoSat",
c => new
{
Id = c.Int(nullable: false, identity: true),
CMND = c.String(nullable: false, maxLength: 15),
Khoi = c.String(maxLength: 5),
DiemMon1 = c.Decimal(precision: 18, scale: 2),
DiemMon2 = c.Decimal(precision: 18, scale: 2),
DiemMon3 = c.Decimal(precision: 18, scale: 2),
})
.PrimaryKey(t => t.Id);
}
public override void Down()
{
DropTable("dbo.KhaoSat");
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/WebDbContext.cs
using System.Data.Entity;
using Web_Datamining.Model.Models;
using Web_Datamining.Models;
namespace Web_Datamining.Data
{
public class WebDbContext : DbContext
{
public WebDbContext() : base("WebDataminingConnection")
{
this.Configuration.LazyLoadingEnabled = false;
}
public DbSet<ChuyenNganh> ChuyenNganhs { get; set; }
public DbSet<DiemCTHKy> DiemCTHKys { get; set; }
public DbSet<DiemHocKy> DiemHocKys { get; set; }
public DbSet<DiemXetTuyen> DiemXetTuyens { get; set; }
public DbSet<DSNguyenVong> DSNguyenVongs { get; set; }
public DbSet<HeDaoTao> HeDaoTaos { get; set; }
public DbSet<HocKy> HocKys { get; set; }
public DbSet<HoSoXetTuyen> HoSoXetTuyens { get; set; }
public DbSet<Huyen> Huyens { get; set; }
public DbSet<Khoa> Khoas { get; set; }
public DbSet<KhoaHoc> KhoaHocs { get; set; }
public DbSet<Lop> Lops { get; set; }
public DbSet<Luat> Luats { get; set; }
public DbSet<LoaiLuat> LoaiLuats { get; set; }
public DbSet<MonHoc> MonHocs { get; set; }
public DbSet<NganhTheoBo> NganhTheoBos { get; set; }
public DbSet<SinhVien> SinhViens { get; set; }
public DbSet<Tinh> Tinhs { get; set; }
public DbSet<ToHopMon> ToHopMons { get; set; }
public DbSet<TruongTHPT> TruongTHPTs { get; set; }
public DbSet<Error> Errors { get; set; }
public DbSet<ChuongTrinhDaoTao> ChuongTrinhDaoTaos { get; set; }
public DbSet<KhaoSat> KhaoSat { get; set; }
public static WebDbContext Create()
{
return new WebDbContext();
}
protected override void OnModelCreating(DbModelBuilder modelBuilder)
{
base.OnModelCreating(modelBuilder);
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Migrations/201810081409155_InitDatabase.cs
namespace Web_Datamining.Data.Migrations
{
using System.Data.Entity.Migrations;
public partial class InitDatabase : DbMigration
{
public override void Up()
{
CreateTable(
"dbo.ChuyenNganh",
c => new
{
MaChuyenNganh = c.String(nullable: false, maxLength: 10),
TenChuyenNganh = c.String(maxLength: 50),
MaKhoa = c.String(nullable: false, maxLength: 10),
})
.PrimaryKey(t => t.MaChuyenNganh)
.ForeignKey("dbo.Khoa", t => t.MaKhoa, cascadeDelete: true)
.Index(t => t.MaKhoa);
CreateTable(
"dbo.Khoa",
c => new
{
MaKhoa = c.String(nullable: false, maxLength: 10),
TenKhoa = c.String(maxLength: 50),
})
.PrimaryKey(t => t.MaKhoa);
CreateTable(
"dbo.Lop",
c => new
{
ID_Lop = c.Int(nullable: false),
MaChuyenNganh = c.String(nullable: false, maxLength: 10),
MaHeDaoTao = c.String(nullable: false, maxLength: 10),
MaKhoaHoc = c.Int(nullable: false),
TenLop = c.String(maxLength: 10),
})
.PrimaryKey(t => t.ID_Lop)
.ForeignKey("dbo.ChuyenNganh", t => t.MaChuyenNganh, cascadeDelete: true)
.ForeignKey("dbo.HeDaoTao", t => t.MaHeDaoTao, cascadeDelete: true)
.ForeignKey("dbo.KhoaHoc", t => t.MaKhoaHoc, cascadeDelete: true)
.Index(t => t.MaChuyenNganh)
.Index(t => t.MaHeDaoTao)
.Index(t => t.MaKhoaHoc);
CreateTable(
"dbo.HeDaoTao",
c => new
{
MaHeDaoTao = c.String(nullable: false, maxLength: 10),
TenHeDaoTao = c.String(maxLength: 50),
})
.PrimaryKey(t => t.MaHeDaoTao);
CreateTable(
"dbo.KhoaHoc",
c => new
{
MaKhoaHoc = c.Int(nullable: false),
NamHoc = c.String(maxLength: 10),
})
.PrimaryKey(t => t.MaKhoaHoc);
CreateTable(
"dbo.SinhVien",
c => new
{
MSSV = c.String(nullable: false, maxLength: 15),
MaHoSo = c.Int(nullable: false),
CoVanHocTap = c.String(storeType: "ntext"),
ID_Lop = c.Int(nullable: false),
})
.PrimaryKey(t => t.MSSV)
.ForeignKey("dbo.HoSoXetTuyen", t => t.MaHoSo, cascadeDelete: true)
.ForeignKey("dbo.Lop", t => t.ID_Lop, cascadeDelete: true)
.Index(t => t.MaHoSo)
.Index(t => t.ID_Lop);
CreateTable(
"dbo.DiemHocKy",
c => new
{
MSSV = c.String(nullable: false, maxLength: 15),
ID_HocKi = c.Int(nullable: false),
SoTCDK = c.Int(),
SoTCD = c.Int(),
SoTCTL = c.Int(),
DiemTBTLHe4 = c.Double(),
})
.PrimaryKey(t => new { t.MSSV, t.ID_HocKi })
.ForeignKey("dbo.HocKy", t => t.ID_HocKi, cascadeDelete: true)
.ForeignKey("dbo.SinhVien", t => t.MSSV, cascadeDelete: true)
.Index(t => t.MSSV)
.Index(t => t.ID_HocKi);
CreateTable(
"dbo.DiemCTHKy",
c => new
{
MaMon = c.String(nullable: false, maxLength: 10),
MSSV = c.String(nullable: false, maxLength: 15),
ID_HocKi = c.Int(nullable: false),
DiemTH = c.Double(),
DiemQT = c.Double(),
DiemThi1 = c.Double(),
DiemThi2 = c.Double(),
TiLeDiemTH = c.Double(),
TiLeDiemQT = c.Double(),
TiLeDiemThi1 = c.Double(),
TiLeDiemThi2 = c.Double(),
DiemTKHe10 = c.Double(),
DiemTKHe4 = c.Double(),
DiemTKChu = c.String(maxLength: 50),
})
.PrimaryKey(t => new { t.MaMon, t.MSSV, t.ID_HocKi })
.ForeignKey("dbo.DiemHocKy", t => new { t.MSSV, t.ID_HocKi }, cascadeDelete: true)
.ForeignKey("dbo.MonHoc", t => t.MaMon, cascadeDelete: true)
.Index(t => t.MaMon)
.Index(t => new { t.MSSV, t.ID_HocKi });
CreateTable(
"dbo.MonHoc",
c => new
{
MaMon = c.String(nullable: false, maxLength: 10),
TenMon = c.String(maxLength: 50),
TichLuy = c.Boolean(),
DiemDat = c.Double(),
})
.PrimaryKey(t => t.MaMon);
CreateTable(
"dbo.HocKy",
c => new
{
ID_HocKi = c.Int(nullable: false),
NamHoc = c.String(maxLength: 10),
KyHoc = c.Int(),
})
.PrimaryKey(t => t.ID_HocKi);
CreateTable(
"dbo.HoSoXetTuyen",
c => new
{
MaHoSo = c.Int(nullable: false),
MaTruongTHPT = c.Int(nullable: false),
CMDN = c.String(maxLength: 15),
NgaySinh = c.DateTime(storeType: "smalldatetime"),
HoTen = c.String(maxLength: 50),
GioiTinh = c.Int(),
DanToc = c.String(maxLength: 30),
TinhTrangTrungTuyen = c.Int(),
DXT_ID = c.Int(nullable: false),
})
.PrimaryKey(t => t.MaHoSo)
.ForeignKey("dbo.DiemXetTuyen", t => t.DXT_ID, cascadeDelete: true)
.ForeignKey("dbo.TruongTHPT", t => t.MaTruongTHPT, cascadeDelete: true)
.Index(t => t.MaTruongTHPT)
.Index(t => t.DXT_ID);
CreateTable(
"dbo.DiemXetTuyen",
c => new
{
DXT_ID = c.Int(nullable: false, identity: true),
DiemToan = c.Double(),
DiemVan = c.Double(),
DiemLy = c.Double(),
DiemHoa = c.Double(),
DiemSinh = c.Double(),
DiemDia = c.Double(),
DiemGDCD = c.Double(),
DiemNN = c.Double(),
HinhThucXetTuyen = c.Boolean(),
})
.PrimaryKey(t => t.DXT_ID);
CreateTable(
"dbo.DSNguyenVong",
c => new
{
MaHoSo = c.Int(nullable: false),
ThuTuNV = c.Int(nullable: false),
MaToHop = c.String(nullable: false, maxLength: 5),
MaNganh = c.String(nullable: false, maxLength: 50),
MaTDH = c.String(maxLength: 10),
TrangThaiNV = c.String(maxLength: 10),
})
.PrimaryKey(t => new { t.MaHoSo, t.ThuTuNV })
.ForeignKey("dbo.HoSoXetTuyen", t => t.MaHoSo, cascadeDelete: true)
.ForeignKey("dbo.NganhTheoBo", t => t.MaNganh, cascadeDelete: true)
.ForeignKey("dbo.ToHopMon", t => t.MaToHop, cascadeDelete: true)
.Index(t => t.MaHoSo)
.Index(t => t.MaToHop)
.Index(t => t.MaNganh);
CreateTable(
"dbo.NganhTheoBo",
c => new
{
MaNganh = c.String(nullable: false, maxLength: 50),
TeNganh = c.String(maxLength: 50),
})
.PrimaryKey(t => t.MaNganh);
CreateTable(
"dbo.ToHopMon",
c => new
{
MaToHop = c.String(nullable: false, maxLength: 5),
Mon1 = c.String(maxLength: 20),
Mon2 = c.String(maxLength: 20),
Mon3 = c.String(maxLength: 20),
})
.PrimaryKey(t => t.MaToHop);
CreateTable(
"dbo.TruongTHPT",
c => new
{
MaTruongTHPT = c.Int(nullable: false),
MaHuyen = c.Int(nullable: false),
MaTinh = c.Int(nullable: false),
TenTruong = c.String(maxLength: 50),
})
.PrimaryKey(t => t.MaTruongTHPT)
.ForeignKey("dbo.Huyen", t => new { t.MaHuyen, t.MaTinh }, cascadeDelete: true)
.Index(t => new { t.MaHuyen, t.MaTinh });
CreateTable(
"dbo.Huyen",
c => new
{
MaHuyen = c.Int(nullable: false),
MaTinh = c.Int(nullable: false),
khuvuc = c.String(maxLength: 20),
TenHuyen = c.String(maxLength: 50),
})
.PrimaryKey(t => new { t.MaHuyen, t.MaTinh })
.ForeignKey("dbo.Tinh", t => t.MaTinh, cascadeDelete: true)
.Index(t => t.MaTinh);
CreateTable(
"dbo.Tinh",
c => new
{
MaTinh = c.Int(nullable: false),
TenTinh = c.String(maxLength: 50),
KhuVuc = c.String(maxLength: 20),
})
.PrimaryKey(t => t.MaTinh);
CreateTable(
"dbo.Luat",
c => new
{
Id = c.Int(nullable: false, identity: true),
X = c.String(maxLength: 100),
Y = c.String(maxLength: 100),
Support = c.Decimal(precision: 18, scale: 2),
Confidence = c.Decimal(precision: 18, scale: 2),
})
.PrimaryKey(t => t.Id);
CreateTable(
"dbo.LuatXetTuyen",
c => new
{
Id = c.Int(nullable: false, identity: true),
X = c.String(maxLength: 100),
Y = c.String(maxLength: 100),
Support = c.Decimal(precision: 18, scale: 2),
Confidence = c.Decimal(precision: 18, scale: 2),
})
.PrimaryKey(t => t.Id);
}
public override void Down()
{
DropForeignKey("dbo.SinhVien", "ID_Lop", "dbo.Lop");
DropForeignKey("dbo.TruongTHPT", new[] { "MaHuyen", "MaTinh" }, "dbo.Huyen");
DropForeignKey("dbo.Huyen", "MaTinh", "dbo.Tinh");
DropForeignKey("dbo.HoSoXetTuyen", "MaTruongTHPT", "dbo.TruongTHPT");
DropForeignKey("dbo.SinhVien", "MaHoSo", "dbo.HoSoXetTuyen");
DropForeignKey("dbo.DSNguyenVong", "MaToHop", "dbo.ToHopMon");
DropForeignKey("dbo.DSNguyenVong", "MaNganh", "dbo.NganhTheoBo");
DropForeignKey("dbo.DSNguyenVong", "MaHoSo", "dbo.HoSoXetTuyen");
DropForeignKey("dbo.HoSoXetTuyen", "DXT_ID", "dbo.DiemXetTuyen");
DropForeignKey("dbo.DiemHocKy", "MSSV", "dbo.SinhVien");
DropForeignKey("dbo.DiemHocKy", "ID_HocKi", "dbo.HocKy");
DropForeignKey("dbo.DiemCTHKy", "MaMon", "dbo.MonHoc");
DropForeignKey("dbo.DiemCTHKy", new[] { "MSSV", "ID_HocKi" }, "dbo.DiemHocKy");
DropForeignKey("dbo.Lop", "MaKhoaHoc", "dbo.KhoaHoc");
DropForeignKey("dbo.Lop", "MaHeDaoTao", "dbo.HeDaoTao");
DropForeignKey("dbo.Lop", "MaChuyenNganh", "dbo.ChuyenNganh");
DropForeignKey("dbo.ChuyenNganh", "MaKhoa", "dbo.Khoa");
DropIndex("dbo.Huyen", new[] { "MaTinh" });
DropIndex("dbo.TruongTHPT", new[] { "MaHuyen", "MaTinh" });
DropIndex("dbo.DSNguyenVong", new[] { "MaNganh" });
DropIndex("dbo.DSNguyenVong", new[] { "MaToHop" });
DropIndex("dbo.DSNguyenVong", new[] { "MaHoSo" });
DropIndex("dbo.HoSoXetTuyen", new[] { "DXT_ID" });
DropIndex("dbo.HoSoXetTuyen", new[] { "MaTruongTHPT" });
DropIndex("dbo.DiemCTHKy", new[] { "MSSV", "ID_HocKi" });
DropIndex("dbo.DiemCTHKy", new[] { "MaMon" });
DropIndex("dbo.DiemHocKy", new[] { "ID_HocKi" });
DropIndex("dbo.DiemHocKy", new[] { "MSSV" });
DropIndex("dbo.SinhVien", new[] { "ID_Lop" });
DropIndex("dbo.SinhVien", new[] { "MaHoSo" });
DropIndex("dbo.Lop", new[] { "MaKhoaHoc" });
DropIndex("dbo.Lop", new[] { "MaHeDaoTao" });
DropIndex("dbo.Lop", new[] { "MaChuyenNganh" });
DropIndex("dbo.ChuyenNganh", new[] { "MaKhoa" });
DropTable("dbo.LuatXetTuyen");
DropTable("dbo.Luat");
DropTable("dbo.Tinh");
DropTable("dbo.Huyen");
DropTable("dbo.TruongTHPT");
DropTable("dbo.ToHopMon");
DropTable("dbo.NganhTheoBo");
DropTable("dbo.DSNguyenVong");
DropTable("dbo.DiemXetTuyen");
DropTable("dbo.HoSoXetTuyen");
DropTable("dbo.HocKy");
DropTable("dbo.MonHoc");
DropTable("dbo.DiemCTHKy");
DropTable("dbo.DiemHocKy");
DropTable("dbo.SinhVien");
DropTable("dbo.KhoaHoc");
DropTable("dbo.HeDaoTao");
DropTable("dbo.Lop");
DropTable("dbo.Khoa");
DropTable("dbo.ChuyenNganh");
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/Areas/Admin/Controllers/DiemHocKiesController.cs
using System;
using System.Collections.Generic;
using System.Data;
using System.Data.Entity;
using System.Linq;
using System.Net;
using System.Web;
using System.Web.Mvc;
using Web_Datamining.Data;
using Web_Datamining.Models;
namespace Web_Datamining.Web.Areas.Admin.Controllers
{
public class DiemHocKiesController : Controller
{
private WebDbContext db = new WebDbContext();
// GET: Admin/DiemHocKies
public ActionResult Index()
{
var diemHocKys = db.DiemHocKys.Include(d => d.HocKy).Include(d => d.SinhVien);
return View(diemHocKys.ToList());
}
// GET: Admin/DiemHocKies/Details/5
public ActionResult Details(string id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DiemHocKy diemHocKy = db.DiemHocKys.Find(id);
if (diemHocKy == null)
{
return HttpNotFound();
}
return View(diemHocKy);
}
// GET: Admin/DiemHocKies/Create
public ActionResult Create()
{
ViewBag.ID_HocKi = new SelectList(db.HocKys, "ID_HocKi", "NamHoc");
ViewBag.MSSV = new SelectList(db.SinhViens, "MSSV", "CoVanHocTap");
return View();
}
// POST: Admin/DiemHocKies/Create
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Create([Bind(Include = "MSSV,ID_HocKi,SoTCDK,SoTCD,SoTCTL,DiemTBTLHe4")] DiemHocKy diemHocKy)
{
if (ModelState.IsValid)
{
db.DiemHocKys.Add(diemHocKy);
db.SaveChanges();
return RedirectToAction("Index");
}
ViewBag.ID_HocKi = new SelectList(db.HocKys, "ID_HocKi", "NamHoc", diemHocKy.ID_HocKi);
ViewBag.MSSV = new SelectList(db.SinhViens, "MSSV", "CoVanHocTap", diemHocKy.MSSV);
return View(diemHocKy);
}
// GET: Admin/DiemHocKies/Edit/5
public ActionResult Edit(string id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DiemHocKy diemHocKy = db.DiemHocKys.Find(id);
if (diemHocKy == null)
{
return HttpNotFound();
}
ViewBag.ID_HocKi = new SelectList(db.HocKys, "ID_HocKi", "NamHoc", diemHocKy.ID_HocKi);
ViewBag.MSSV = new SelectList(db.SinhViens, "MSSV", "CoVanHocTap", diemHocKy.MSSV);
return View(diemHocKy);
}
// POST: Admin/DiemHocKies/Edit/5
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Edit([Bind(Include = "MSSV,ID_HocKi,SoTCDK,SoTCD,SoTCTL,DiemTBTLHe4")] DiemHocKy diemHocKy)
{
if (ModelState.IsValid)
{
db.Entry(diemHocKy).State = EntityState.Modified;
db.SaveChanges();
return RedirectToAction("Index");
}
ViewBag.ID_HocKi = new SelectList(db.HocKys, "ID_HocKi", "NamHoc", diemHocKy.ID_HocKi);
ViewBag.MSSV = new SelectList(db.SinhViens, "MSSV", "CoVanHocTap", diemHocKy.MSSV);
return View(diemHocKy);
}
// GET: Admin/DiemHocKies/Delete/5
public ActionResult Delete(string id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DiemHocKy diemHocKy = db.DiemHocKys.Find(id);
if (diemHocKy == null)
{
return HttpNotFound();
}
return View(diemHocKy);
}
// POST: Admin/DiemHocKies/Delete/5
[HttpPost, ActionName("Delete")]
[ValidateAntiForgeryToken]
public ActionResult DeleteConfirmed(string id)
{
DiemHocKy diemHocKy = db.DiemHocKys.Find(id);
db.DiemHocKys.Remove(diemHocKy);
db.SaveChanges();
return RedirectToAction("Index");
}
protected override void Dispose(bool disposing)
{
if (disposing)
{
db.Dispose();
}
base.Dispose(disposing);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Web/Api/LuatHocTapController.cs
using AutoMapper;
using System.Collections.Generic;
using System.Linq;
using System.Net;
using System.Net.Http;
using System.Web.Http;
using Web_Datamining.Data;
using Web_Datamining.Models;
using Web_Datamining.Service;
using Web_Datamining.Web.Infrastructure.Core;
using Web_Datamining.Web.Models;
namespace Web_Datamining.Web.Api
{
[RoutePrefix("api/luathoctap")]
[AllowCrossSiteJson]
public class LuatHocTapController : ApiControllerBase
{
#region Contructor
private ILuatService _luatService;
public LuatHocTapController(IErrorService errorService, ILuatService luatService) : base(errorService)
{
this._luatService = luatService;
}
//Db classitem hỗ trợ thuật toán apriori
private ClssItemCollection db = new ClssItemCollection();
#endregion Contructor
#region Api lấy sử dụng luật
[Route("getall")]
[HttpGet]
public HttpResponseMessage GetAll(HttpRequestMessage request, int idLoaiLuat)
{
return CreateHttpResponse(request, () =>
{
int totalRow = 0;
var model = _luatService.GetAll(idLoaiLuat);
totalRow = model.Count();
var query = model.OrderByDescending(x => x.X);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(query);
var response = request.CreateResponse(HttpStatusCode.OK, responseData);
return response;
});
}
#endregion Api lấy sử dụng luật
#region Api tìm kiếm luật xét tuyển
[Route("findrules")]
[HttpGet]
public HttpResponseMessage FindRules(HttpRequestMessage request, int idLoaiLuat, string keyword)
{
return CreateHttpResponse(request, () =>
{
int totalRow = 0;
var model = _luatService.GetAll(idLoaiLuat, keyword);
totalRow = model.Count();
var query = model.OrderByDescending(x => x.X);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(query);
var response = request.CreateResponse(HttpStatusCode.OK, responseData);
return response;
});
}
#endregion Api tìm kiếm luật xét tuyển
#region Api Xóa luật
[Route("deleterule")]
[HttpGet]
public HttpResponseMessage DeleteRule(HttpRequestMessage request, int keyword)
{
return CreateHttpResponse(request, () =>
{
var item = _luatService.GetById(keyword);
var model = _luatService.DeleteItem(item);
_luatService.Save();
var response = request.CreateResponse(HttpStatusCode.OK, "Xóa thành công");
return response;
});
}
#endregion Api xóa luật
//********************************************
#region Api tạo danh sach luật: Khoa => Môn học vượt
[Route("create")]
[HttpGet]
[AllowAnonymous]
public HttpResponseMessage Create(HttpRequestMessage request, int idLoaiLuat, double sup, double con)
{
return CreateHttpResponse(request, () =>
{
HttpResponseMessage response = null;
if (!ModelState.IsValid)
{
response = request.CreateResponse(HttpStatusCode.BadRequest, ModelState);
}
else
{
List<ClssRules> allRules = GetRulesXetTuyen(sup, con);
//Xóa những dữ liệu luật cũ theo idLoaiLuat
var listLuatTheoIdLoaiLuat = _luatService.GetAll(idLoaiLuat);
foreach (var item in listLuatTheoIdLoaiLuat)
{
_luatService.DeleteItem(item);
}
_luatService.Save();
//Đẩy danh sach các luật vào cơ sở dữ liệu
foreach (ClssRules rule in allRules)
{
Luat luat = new Luat
{
X = rule.X.ToString(),
Y = rule.Y.ToString(),
Support = (decimal)rule.Support,
Confidence = (decimal)rule.Confidence,
LuatId = idLoaiLuat //Thêm loại luật để phân biệt giữa các luật
};
_luatService.Add(luat);
}
_luatService.Save();
var newListLuat = _luatService.GetAll(idLoaiLuat);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(newListLuat);
response = request.CreateResponse(HttpStatusCode.Created, responseData);
}
return response;
});
}
#endregion Api tạo danh sach luật: Khoa => Môn học vượt
#region Hàm lấy ra danh sách các luật: Khoa => Môn học vượt
public List<ClssRules> GetRulesXetTuyen(double sup, double con)
{
WebDbContext dbContext = new WebDbContext();
var dataListView = (from CTDT in dbContext.ChuongTrinhDaoTaos
from dcthk in dbContext.DiemCTHKys
from sv in dbContext.SinhViens
from dhk in dbContext.DiemHocKys
where dcthk.MSSV == sv.MSSV
&&
!(from ct in dbContext.ChuongTrinhDaoTaos
where sv.Lop.Khoa.MaKhoa == ct.MaKhoa && ct.ID_HocKi == dcthk.ID_HocKi
select new
{
ct.MaMon
}).Contains(new { MaMon = dcthk.MaMon })
select new
{
sv.Lop.Khoa.TenKhoa,
dcthk.MonHoc.TenMon,
sv.MSSV
}).Distinct().ToList();
string result = "";
foreach (var item in dataListView)
{
db.Add(new clssItemSet()
{
item.TenMon,
item.TenKhoa
});
}
clssItemSet uniqueItems = db.GetUniqueItems();
ClssItemCollection L = clssApriori.DoApriori(db, sup);
List<ClssRules> allRules = clssApriori.Mine(db, L, con);
result = "\n" + allRules.Count + " rules \n";
return allRules;
}
#endregion Hàm lấy ra danh sách các luật: Khoa => Môn học vượt
//********************************************
#region Ham lay ra danh sach cac luat:Khoa =>Mon cai thien
public List<ClssRules> LuatCaiThien(double sup, double con)
{
//double minSupport = Double.Parse(formCollection["MinSupport"]);
//double minConfidence = Double.Parse(formCollection["MinConfidence"]);
WebDbContext dbContext = new WebDbContext();
var dataListView = (from a in (
(from dcthk in dbContext.DiemCTHKys
from sv in dbContext.SinhViens
where
dcthk.MSSV == sv.MSSV
select new
{
dcthk.MaMon,
dcthk.MSSV,
dcthk.DiemTKHe4,
dcthk.MonHoc.TenMon,
sv.Lop.Khoa.TenKhoa
}))
group a by new
{
a.MaMon,
a.MSSV,
a.TenMon,
a.TenKhoa
} into g
where g.Count() > 1
select new
{
g.Key.TenMon,
g.Key.TenKhoa
}).ToList();
string result = "";
foreach (var item in dataListView)
{
db.Add(new clssItemSet()
{
item.TenMon,
item.TenKhoa
});
}
clssItemSet uniqueItems = db.GetUniqueItems();
ClssItemCollection L = clssApriori.DoApriori(db, sup);
List<ClssRules> allRules = clssApriori.Mine(db, L, con);
result = "\n" + allRules.Count + " rules \n";
return allRules;
}
#endregion Ham lay ra danh sach cac luat:Khoa =>Mon cai thien
#region Api tao danh sach luat: Khoa =>Mon cai thien
[Route("createcaithien")]
[HttpGet]
[AllowAnonymous]
public HttpResponseMessage CreateCaiThien(HttpRequestMessage request, int idLoaiLuat, double sup, double con)
{
return CreateHttpResponse(request, () =>
{
HttpResponseMessage response = null;
if (!ModelState.IsValid)
{
response = request.CreateResponse(HttpStatusCode.BadRequest, ModelState);
}
else
{
List<ClssRules> allRules = LuatCaiThien(sup, con);
//Xóa những dữ liệu luật cũ theo idLoaiLuat
var listLuatTheoIdLoaiLuat = _luatService.GetAll(idLoaiLuat);
foreach (var item in listLuatTheoIdLoaiLuat)
{
_luatService.DeleteItem(item);
}
_luatService.Save();
//Đẩy danh sach các luật vào cơ sở dữ liệu
foreach (ClssRules rule in allRules)
{
Luat luat = new Luat
{
X = rule.X.ToString(),
Y = rule.Y.ToString(),
Support = (decimal)rule.Support,
Confidence = (decimal)rule.Confidence,
LuatId = idLoaiLuat //Thêm loại luật để phân biệt giữa các luật
};
_luatService.Add(luat);
}
_luatService.Save();
var newListLuat = _luatService.GetAll(idLoaiLuat);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(newListLuat);
response = request.CreateResponse(HttpStatusCode.Created, responseData);
}
return response;
});
}
#endregion Api tao danh sach luat: Khoa =>Mon cai thien
//********************************************
#region Api tạo danh sach luật: Môn học cải thiện => Điểm tăng
[Route("CreateDiemTangCaiThien")]
[HttpGet]
[AllowAnonymous]
public HttpResponseMessage CreateDiemTangCaiThien(HttpRequestMessage request, int idLoaiLuat, double sup, double con)
{
return CreateHttpResponse(request, () =>
{
HttpResponseMessage response = null;
if (!ModelState.IsValid)
{
response = request.CreateResponse(HttpStatusCode.BadRequest, ModelState);
}
else
{
List<ClssRules> allRules = GetRulesHocCaiThien(sup, con);
//Xóa những dữ liệu luật cũ theo idLoaiLuat
var listLuatTheoIdLoaiLuat = _luatService.GetAll(idLoaiLuat);
foreach (var item in listLuatTheoIdLoaiLuat)
{
_luatService.DeleteItem(item);
}
_luatService.Save();
//Đẩy danh sach các luật vào cơ sở dữ liệu
foreach (ClssRules rule in allRules)
{
Luat luat = new Luat
{
X = rule.X.ToString(),
Y = rule.Y.ToString(),
Support = (decimal)rule.Support,
Confidence = (decimal)rule.Confidence,
LuatId = idLoaiLuat //Thêm loại luật để phân biệt giữa các luật
};
_luatService.Add(luat);
}
_luatService.Save();
var newListLuat = _luatService.GetAll(idLoaiLuat);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(newListLuat);
response = request.CreateResponse(HttpStatusCode.Created, responseData);
}
return response;
});
}
#endregion Api tạo danh sach luật: Môn học cải thiện => Điểm tăng
#region Hàm lấy ra danh sách các luật: Môn cải thiện => điểm tăng
public List<ClssRules> GetRulesHocCaiThien(double sup, double con)
{
WebDbContext dbContext = new WebDbContext();
var dataListView = ((from a in (
(from dcthk in dbContext.DiemCTHKys
where
dcthk.DiemTKHe10 >= dcthk.MonHoc.DiemDat
select new
{
dcthk.MSSV,
dcthk.MonHoc.MaMon,
dcthk.DiemTKHe10,
dcthk.MonHoc.TenMon,
dcthk.ID_HocKi
}))
group a by new
{
a.MSSV,
a.MaMon,
a.TenMon
} into g
where (g.Max(p => p.DiemTKHe10) - g.Min(p => p.DiemTKHe10)) > 0
select new
{
g.Key.MSSV,
g.Key.MaMon,
g.Key.TenMon,
chechlech = (double?)(g.Max(p => p.DiemTKHe10) - g.Min(p => p.DiemTKHe10))
})).ToList();
string result = "";
foreach (var item in dataListView)
{
db.Add(new clssItemSet()
{
item.TenMon,
item.chechlech.ToString()
});
}
clssItemSet uniqueItems = db.GetUniqueItems();
ClssItemCollection L = clssApriori.DoApriori(db, sup);
List<ClssRules> allRules = clssApriori.Mine(db, L, con);
result = "\n" + allRules.Count + " rules \n";
return allRules;
}
#endregion Hàm lấy ra danh sách các luật: Môn cải thiện => điểm tăng
//********************************************
#region Api tạo danh sach luật: Môn học vượt => Điểm tăng
[Route("CreateDiemTangHocVuot")]
[HttpGet]
[AllowAnonymous]
public HttpResponseMessage CreateDiemTangHocVuot(HttpRequestMessage request, int idLoaiLuat, double sup, double con)
{
return CreateHttpResponse(request, () =>
{
HttpResponseMessage response = null;
if (!ModelState.IsValid)
{
response = request.CreateResponse(HttpStatusCode.BadRequest, ModelState);
}
else
{
List<ClssRules> allRules = GetRulesHocVuot(sup, con);
//Xóa những dữ liệu luật cũ theo idLoaiLuat
var listLuatTheoIdLoaiLuat = _luatService.GetAll(idLoaiLuat);
foreach (var item in listLuatTheoIdLoaiLuat)
{
_luatService.DeleteItem(item);
}
_luatService.Save();
//Đẩy danh sach các luật vào cơ sở dữ liệu
foreach (ClssRules rule in allRules)
{
Luat luat = new Luat
{
X = rule.X.ToString(),
Y = rule.Y.ToString(),
Support = (decimal)rule.Support,
Confidence = (decimal)rule.Confidence,
LuatId = idLoaiLuat //Thêm loại luật để phân biệt giữa các luật
};
_luatService.Add(luat);
}
_luatService.Save();
var newListLuat = _luatService.GetAll(idLoaiLuat);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(newListLuat);
response = request.CreateResponse(HttpStatusCode.Created, responseData);
}
return response;
});
}
#endregion Api tạo danh sach luật: Môn học vượt => Điểm tăng
#region Hàm lấy ra danh sách các luật: Môn học vượt => điểm tăng
public List<ClssRules> GetRulesHocVuot(double sup, double con)
{
WebDbContext dbContext = new WebDbContext();
var dataListView = ((from CTDT in dbContext.ChuongTrinhDaoTaos
from dcthk in dbContext.DiemCTHKys
where
!
(from ct in dbContext.ChuongTrinhDaoTaos
where
ct.MaKhoa == dcthk.DiemHocKy.SinhVien.Lop.ChuyenNganh.Khoa.MaKhoa &&
ct.ID_HocKi == dcthk.ID_HocKi
select new
{
ct.MaMon
}).Contains(new { MaMon = dcthk.MaMon })
select new
{
dcthk.MaMon,
dcthk.DiemHocKy.SinhVien.MSSV,
dcthk.DiemTKHe10,
dcthk.MonHoc.TenMon,
dcthk.ID_HocKi
})).Distinct().ToList();
string result = "";
foreach (var item in dataListView)
{
db.Add(new clssItemSet()
{
item.TenMon,
item.DiemTKHe10.ToString()
});
}
clssItemSet uniqueItems = db.GetUniqueItems();
ClssItemCollection L = clssApriori.DoApriori(db, sup);
List<ClssRules> allRules = clssApriori.Mine(db, L, con);
result = "\n" + allRules.Count + " rules \n";
return allRules;
}
#endregion Hàm lấy ra danh sách các luật: Môn học vượt => điểm tăng
//********************************************
}
}<file_sep>/Web_Datamining/Web_Datamining.Service/LuatService.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Data.Repositories;
using Web_Datamining.Models;
namespace Web_Datamining.Service
{
public interface ILuatService
{
Luat Add(Luat Luat);
void Update(Luat Luat);
Luat Delete(int id);
Luat DeleteItem(Luat item);
IEnumerable<Luat> GetAll();
IEnumerable<Luat> GetAll(int idLoaiLuat);
IEnumerable<Luat> GetAll(int idLoaiLuat, string keyword,string dt);
IEnumerable<Luat> GetAll(int idLoaiLuat, string keyword);
Luat GetById(int id);
void Save();
}
public class LuatService : ILuatService
{
private ILuatRepository _LuatRepository;
private IUnitOfWork _unitOfWork;
public LuatService(ILuatRepository LuatRepository, IUnitOfWork unitOfWork)
{
ILuatRepository luatRepository = LuatRepository;
this._LuatRepository = LuatRepository;
this._unitOfWork = unitOfWork;
}
public Luat Add(Luat Luat)
{
return _LuatRepository.Add(Luat);
}
public Luat Delete(int id)
{
return _LuatRepository.Delete(id);
}
public Luat DeleteItem(Luat item)
{
return _LuatRepository.Delete(item);
}
public IEnumerable<Luat> GetAll()
{
return _LuatRepository.GetAll();
}
public IEnumerable<Luat> GetAll(int idLoaiLuat)
{
var listLuat = _LuatRepository.GetMulti(x => x.LuatId == idLoaiLuat);
if (listLuat == null)
{
return _LuatRepository.GetAll();
}
else
{
return listLuat;
}
}
public IEnumerable<Luat> GetAll(int idLoaiLuat, string keyword,string dt)
{
var listLuat = _LuatRepository.GetMulti(x => x.LuatId == idLoaiLuat && (x.X.Contains(keyword) || x.Y.Contains(keyword)) && (x.X.Contains(dt) || x.Y.Contains(dt)));
if (listLuat == null)
{
return _LuatRepository.GetAll();
}
else
{
return listLuat;
}
}
public IEnumerable<Luat> GetAll(int idLoaiLuat, string keyword)
{
var listLuat = _LuatRepository.GetMulti(x => x.LuatId == idLoaiLuat && (x.X.Contains(keyword) || x.Y.Contains(keyword)));
if (listLuat == null)
{
return _LuatRepository.GetAll();
}
else
{
return listLuat;
}
}
//public IEnumerable<Luat> GetAll(int idLoaiLuat, string keyword)
//{
// throw new NotImplementedException();
//}
public Luat GetById(int id)
{
return _LuatRepository.GetSingleById(id);
}
public void Save()
{
_unitOfWork.Commit();
}
public void Update(Luat Luat)
{
_LuatRepository.Update(Luat);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/Huyen.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("Huyen")]
public class Huyen
{
[Key]
[Column(Order = 0)]
[DatabaseGenerated(DatabaseGeneratedOption.None)]
public int MaHuyen { get; set; }
[Key]
[Column(Order = 1)]
[DatabaseGenerated(DatabaseGeneratedOption.None)]
public int MaTinh { get; set; }
[StringLength(20)]
public string khuvuc { get; set; }
[StringLength(50)]
public string TenHuyen { get; set; }
public virtual Tinh Tinh { get; set; }
public virtual ICollection<TruongTHPT> TruongTHPT { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/DSNguyenVong.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("DSNguyenVong")]
public class DSNguyenVong
{
[Key]
[Column(Order = 0)]
public int MaHoSo { get; set; }
[Key]
[Column(Order = 1)]
public int ThuTuNV { get; set; }
[Required]
[StringLength(5)]
public string MaToHop { get; set; }
[Required]
[StringLength(50)]
public string MaNganh { get; set; }
[StringLength(10)]
public string MaTDH { get; set; }
public int DiemTong { get; set; }
[StringLength(10)]
public string TrangThaiNV { get; set; }
public virtual HoSoXetTuyen HoSoXetTuyen { get; set; }
public virtual NganhTheoBo NganhTheoBo { get; set; }
public virtual ToHopMon ToHopMon { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Web/Areas/Admin/Controllers/TinhsController.cs
using System;
using System.Collections.Generic;
using System.Data;
using System.Data.Entity;
using System.Linq;
using System.Net;
using System.Web;
using System.Web.Mvc;
using Web_Datamining.Data;
using Web_Datamining.Models;
namespace Web_Datamining.Web.Areas.Admin.Controllers
{
public class TinhsController : Controller
{
private WebDbContext db = new WebDbContext();
// GET: Admin/Tinhs
public ActionResult Index()
{
return View(db.Tinhs.ToList());
}
// GET: Admin/Tinhs/Details/5
public ActionResult Details(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
Tinh tinh = db.Tinhs.Find(id);
if (tinh == null)
{
return HttpNotFound();
}
return View(tinh);
}
// GET: Admin/Tinhs/Create
public ActionResult Create()
{
return View();
}
// POST: Admin/Tinhs/Create
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Create([Bind(Include = "MaTinh,TenTinh,KhuVuc")] Tinh tinh)
{
if (ModelState.IsValid)
{
db.Tinhs.Add(tinh);
db.SaveChanges();
return RedirectToAction("Index");
}
return View(tinh);
}
// GET: Admin/Tinhs/Edit/5
public ActionResult Edit(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
Tinh tinh = db.Tinhs.Find(id);
if (tinh == null)
{
return HttpNotFound();
}
return View(tinh);
}
// POST: Admin/Tinhs/Edit/5
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Edit([Bind(Include = "MaTinh,TenTinh,KhuVuc")] Tinh tinh)
{
if (ModelState.IsValid)
{
db.Entry(tinh).State = EntityState.Modified;
db.SaveChanges();
return RedirectToAction("Index");
}
return View(tinh);
}
// GET: Admin/Tinhs/Delete/5
public ActionResult Delete(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
Tinh tinh = db.Tinhs.Find(id);
if (tinh == null)
{
return HttpNotFound();
}
return View(tinh);
}
// POST: Admin/Tinhs/Delete/5
[HttpPost, ActionName("Delete")]
[ValidateAntiForgeryToken]
public ActionResult DeleteConfirmed(int id)
{
Tinh tinh = db.Tinhs.Find(id);
db.Tinhs.Remove(tinh);
db.SaveChanges();
return RedirectToAction("Index");
}
protected override void Dispose(bool disposing)
{
if (disposing)
{
db.Dispose();
}
base.Dispose(disposing);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/LopRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface ILopRepository : IRepository<Lop>
{
}
public class LopRepository : RepositoryBase<Lop>, ILopRepository
{
public LopRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Infrastructure/IDbFactory.cs
using System;
namespace Web_Datamining.Data.Infrastructure
{
public interface IDbFactory : IDisposable
{
WebDbContext Init();
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/Apriori/clssItemSet.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
namespace Web_Datamining.Web
{
public class clssItemSet : List<string>
{
/// <summary>
/// Độ hỗ trợ của luật
/// </summary>
public double Support { get; set; }
/// <summary>
/// Kiểm tra
/// </summary>
/// <param name="itemset"></param>
/// <returns></returns>
public bool Contains(clssItemSet itemset)
{
return (this.Intersect(itemset).Count() == itemset.Count);
}
public clssItemSet Remove(clssItemSet itemset)
{
clssItemSet removed = new clssItemSet();
removed.AddRange(from item in this
where !itemset.Contains(item)
select item);
return (removed);
}
public override string ToString()
{
return (string.Join(", ", this.ToArray()) + (this.Support > 0 ? " (support: " + Math.Round(this.Support, 2) + "%)" : string.Empty));
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/DiemXetTuyen.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("DiemXetTuyen")]
public class DiemXetTuyen
{
[Key]
[DatabaseGenerated(DatabaseGeneratedOption.Identity)]
public int DXT_ID { get; set; }
public double? DiemToan { get; set; }
public double? DiemVan { get; set; }
public double? DiemLy { get; set; }
public double? DiemHoa { get; set; }
public double? DiemSinh { get; set; }
public double? DiemDia { get; set; }
public double? DiemGDCD { get; set; }
public double? DiemNN { get; set; }
public bool? HinhThucXetTuyen { get; set; }
public virtual ICollection<HoSoXetTuyen> HoSoXetTuyen { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/HocKy.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("HocKy")]
public class HocKy
{
[Key]
[DatabaseGenerated(DatabaseGeneratedOption.None)]
public int ID_HocKi { get; set; }
[StringLength(10)]
public string NamHoc { get; set; }
public int? KyHoc { get; set; }
public virtual ICollection<DiemHocKy> DiemHocKy { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Migrations/201810180310058_EditTableChuognTrinhDaoTao.cs
namespace Web_Datamining.Data.Migrations
{
using System;
using System.Data.Entity.Migrations;
public partial class EditTableChuognTrinhDaoTao : DbMigration
{
public override void Up()
{
DropForeignKey("dbo.ChungTrinhDaoTao", "HocKy_ID_HocKi", "dbo.HocKy");
DropForeignKey("dbo.ChungTrinhDaoTao", "Khoa_MaKhoa", "dbo.Khoa");
DropForeignKey("dbo.ChungTrinhDaoTao", "MonHoc_MaMon", "dbo.MonHoc");
DropIndex("dbo.ChungTrinhDaoTao", new[] { "HocKy_ID_HocKi" });
DropIndex("dbo.ChungTrinhDaoTao", new[] { "Khoa_MaKhoa" });
DropIndex("dbo.ChungTrinhDaoTao", new[] { "MonHoc_MaMon" });
RenameColumn(table: "dbo.ChungTrinhDaoTao", name: "HocKy_ID_HocKi", newName: "ID_HocKi");
RenameColumn(table: "dbo.ChungTrinhDaoTao", name: "Khoa_MaKhoa", newName: "MaKhoa");
RenameColumn(table: "dbo.ChungTrinhDaoTao", name: "MonHoc_MaMon", newName: "MaMon");
DropPrimaryKey("dbo.ChungTrinhDaoTao");
AlterColumn("dbo.ChungTrinhDaoTao", "ID_HocKi", c => c.Int(nullable: false));
AlterColumn("dbo.ChungTrinhDaoTao", "MaKhoa", c => c.String(nullable: false, maxLength: 10));
AlterColumn("dbo.ChungTrinhDaoTao", "MaMon", c => c.String(nullable: false, maxLength: 10));
AddPrimaryKey("dbo.ChungTrinhDaoTao", new[] { "MaKhoa", "ID_HocKi", "MaMon" });
CreateIndex("dbo.ChungTrinhDaoTao", "MaKhoa");
CreateIndex("dbo.ChungTrinhDaoTao", "ID_HocKi");
CreateIndex("dbo.ChungTrinhDaoTao", "MaMon");
AddForeignKey("dbo.ChungTrinhDaoTao", "ID_HocKi", "dbo.HocKy", "ID_HocKi", cascadeDelete: true);
AddForeignKey("dbo.ChungTrinhDaoTao", "MaKhoa", "dbo.Khoa", "MaKhoa", cascadeDelete: true);
AddForeignKey("dbo.ChungTrinhDaoTao", "MaMon", "dbo.MonHoc", "MaMon", cascadeDelete: true);
DropColumn("dbo.ChungTrinhDaoTao", "KhoaID");
DropColumn("dbo.ChungTrinhDaoTao", "HocKyID");
DropColumn("dbo.ChungTrinhDaoTao", "MonHocID");
}
public override void Down()
{
AddColumn("dbo.ChungTrinhDaoTao", "MonHocID", c => c.Int(nullable: false));
AddColumn("dbo.ChungTrinhDaoTao", "HocKyID", c => c.Int(nullable: false));
AddColumn("dbo.ChungTrinhDaoTao", "KhoaID", c => c.Int(nullable: false));
DropForeignKey("dbo.ChungTrinhDaoTao", "MaMon", "dbo.MonHoc");
DropForeignKey("dbo.ChungTrinhDaoTao", "MaKhoa", "dbo.Khoa");
DropForeignKey("dbo.ChungTrinhDaoTao", "ID_HocKi", "dbo.HocKy");
DropIndex("dbo.ChungTrinhDaoTao", new[] { "MaMon" });
DropIndex("dbo.ChungTrinhDaoTao", new[] { "ID_HocKi" });
DropIndex("dbo.ChungTrinhDaoTao", new[] { "MaKhoa" });
DropPrimaryKey("dbo.ChungTrinhDaoTao");
AlterColumn("dbo.ChungTrinhDaoTao", "MaMon", c => c.String(maxLength: 10));
AlterColumn("dbo.ChungTrinhDaoTao", "MaKhoa", c => c.String(maxLength: 10));
AlterColumn("dbo.ChungTrinhDaoTao", "ID_HocKi", c => c.Int());
AddPrimaryKey("dbo.ChungTrinhDaoTao", new[] { "KhoaID", "HocKyID", "MonHocID" });
RenameColumn(table: "dbo.ChungTrinhDaoTao", name: "MaMon", newName: "MonHoc_MaMon");
RenameColumn(table: "dbo.ChungTrinhDaoTao", name: "MaKhoa", newName: "Khoa_MaKhoa");
RenameColumn(table: "dbo.ChungTrinhDaoTao", name: "ID_HocKi", newName: "HocKy_ID_HocKi");
CreateIndex("dbo.ChungTrinhDaoTao", "MonHoc_MaMon");
CreateIndex("dbo.ChungTrinhDaoTao", "Khoa_MaKhoa");
CreateIndex("dbo.ChungTrinhDaoTao", "HocKy_ID_HocKi");
AddForeignKey("dbo.ChungTrinhDaoTao", "MonHoc_MaMon", "dbo.MonHoc", "MaMon");
AddForeignKey("dbo.ChungTrinhDaoTao", "Khoa_MaKhoa", "dbo.Khoa", "MaKhoa");
AddForeignKey("dbo.ChungTrinhDaoTao", "HocKy_ID_HocKi", "dbo.HocKy", "ID_HocKi");
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Web/Api/LuatPhongDaoTaoController.cs
using AutoMapper;
using System.Collections.Generic;
using System.Linq;
using System.Net;
using System.Net.Http;
using System.Web.Http;
using Web_Datamining.Data;
using Web_Datamining.Models;
using Web_Datamining.Service;
using Web_Datamining.Web.Infrastructure.Core;
using Web_Datamining.Web.Models;
namespace Web_Datamining.Web.Api
{
[RoutePrefix("api/luatphongdaotao")]
[AllowCrossSiteJson]
public class LuatPhongDaoTaoController : ApiControllerBase
{
#region Contructor
private ILuatService _luatService;
public LuatPhongDaoTaoController(IErrorService errorService, ILuatService luatService) : base(errorService)
{
this._luatService = luatService;
}
//Db classitem hỗ trợ thuật toán apriori
private ClssItemCollection db = new ClssItemCollection();
#endregion Contructor
#region Api lấy sử dụng luật: Nhập học + Đậu => Khu vực
[Route("getall")]
[HttpGet]
public HttpResponseMessage GetAll(HttpRequestMessage request, int idLoaiLuat)
{
return CreateHttpResponse(request, () =>
{
int totalRow = 0;
var model = _luatService.GetAll(idLoaiLuat);
totalRow = model.Count();
var query = model.OrderByDescending(x => x.X);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(query);
var response = request.CreateResponse(HttpStatusCode.OK, responseData);
return response;
});
}
#endregion Api lấy sử dụng luật: Nhập học + Đậu => Khu vực
#region Api tìm kiếm luật xét tuyển
[Route("findrules")]
[HttpGet]
public HttpResponseMessage FindRules(HttpRequestMessage request, int idLoaiLuat, string keyword)
{
return CreateHttpResponse(request, () =>
{
int totalRow = 0;
var model = _luatService.GetAll(idLoaiLuat, keyword);
totalRow = model.Count();
var query = model.OrderByDescending(x => x.X);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(query);
var response = request.CreateResponse(HttpStatusCode.OK, responseData);
return response;
});
}
#endregion Api tìm kiếm luật xét tuyển
#region Api Xóa luật
[Route("deleterule")]
[HttpGet]
public HttpResponseMessage DeleteRule(HttpRequestMessage request, int keyword)
{
return CreateHttpResponse(request, () =>
{
var item = _luatService.GetById(keyword);
var model = _luatService.DeleteItem(item);
_luatService.Save();
var response = request.CreateResponse(HttpStatusCode.OK, "Xóa thành công");
return response;
});
}
#endregion Api xóa luật
#region Api tạo danh sach luật: Nhập học + Đậu => Khu vực
[Route("createkhuvucnhaphoc")]
[HttpGet]
[AllowAnonymous]
public HttpResponseMessage CreateKhuVucNhapHoc(HttpRequestMessage request, int idLoaiLuat, double sup, double con)
{
return CreateHttpResponse(request, () =>
{
HttpResponseMessage response = null;
if (!ModelState.IsValid)
{
response = request.CreateResponse(HttpStatusCode.BadRequest, ModelState);
}
else
{
List<ClssRules> allRules = GetRulesNhapHocDau_KhuVuc(sup, con);
//Xóa những dữ liệu luật cũ theo idLoaiLuat
var listLuatTheoIdLoaiLuat = _luatService.GetAll(idLoaiLuat);
foreach (var item in listLuatTheoIdLoaiLuat)
{
_luatService.DeleteItem(item);
}
_luatService.Save();
//Đẩy danh sach các luật vào cơ sở dữ liệu
foreach (ClssRules rule in allRules)
{
Luat luat = new Luat
{
X = rule.X.ToString(),
Y = rule.Y.ToString(),
Support = (decimal)rule.Support,
Confidence = (decimal)rule.Confidence,
LuatId = idLoaiLuat //Thêm loại luật để phân biệt giữa các luật
};
_luatService.Add(luat);
}
_luatService.Save();
var newListLuat = _luatService.GetAll(idLoaiLuat);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(newListLuat);
response = request.CreateResponse(HttpStatusCode.Created, responseData);
}
return response;
});
}
#endregion
#region Hàm lấy ra danh sách các luật: Nhập học + Đậu => Khu vực
public List<ClssRules> GetRulesNhapHocDau_KhuVuc(double sup, double con)
{
//double minSupport = Double.Parse(formCollection["MinSupport"]);
//double minConfidence = Double.Parse(formCollection["MinConfidence"]);
WebDbContext dbContext = new WebDbContext();
var dataListView = ((
from HoSoXetTuyens in dbContext.HoSoXetTuyens
from Tinhs in dbContext.Tinhs
from DSNguyenVongs in dbContext.DSNguyenVongs
from NganhTheoBo in dbContext.NganhTheoBos
where
HoSoXetTuyens.TruongTHPT.MaTinh == Tinhs.MaTinh &&
//HoSoXetTuyens.TinhTrangTrungTuyen == 1 &&
//thinh update API
HoSoXetTuyens.MaHoSo == DSNguyenVongs.MaHoSo && //Thinh Add for new rules: Dia diem => Nganh Hoc
DSNguyenVongs.MaNganh == NganhTheoBo.MaNganh //Thinh Add for new rules: Dia diem => Nganh Hoc
//(from SinhViens in dbContext.SinhViens
// select new
// {
// SinhViens.MaHoSo
// }).Contains(new { MaHoSo = HoSoXetTuyens.MaHoSo })
select new
{
HoSoXetTuyens.CMDN,
TinhTrangTrungTuyen = (int?)HoSoXetTuyens.TinhTrangTrungTuyen,
Tinhs.TenTinh,
TinhTrang = "Nhập học",
TenNganh = NganhTheoBo.TeNganh//Thinh ADd for new rule: Dia diem => Nganh Hoc
}
//).Union
//(
// from HoSoXetTuyens in dbContext.HoSoXetTuyens
// from Tinhs in dbContext.Tinhs
// where
// HoSoXetTuyens.TruongTHPT.MaTinh == Tinhs.MaTinh &&
// HoSoXetTuyens.TinhTrangTrungTuyen == 1 &&
// !
// (from SinhViens in dbContext.SinhViens
// select new
// {
// SinhViens.MaHoSo
// }).Contains(new { MaHoSo = HoSoXetTuyens.MaHoSo })
// select new
// {
// CMDN = HoSoXetTuyens.CMDN,
// TinhTrangTrungTuyen = (int?)HoSoXetTuyens.TinhTrangTrungTuyen,
// TenTinh = Tinhs.TenTinh,
// TinhTrang = "Không nhập học"
// }
)).ToList();
string result = "";
foreach (var item in dataListView)
{
db.Add(new clssItemSet()
{
item.TenTinh,
item.TenNganh
});
}
clssItemSet uniqueItems = db.GetUniqueItems();
ClssItemCollection L = clssApriori.DoApriori(db, sup);
List<ClssRules> allRules = clssApriori.Mine(db, L, con);
result = "\n" + allRules.Count + " rules \n";
return allRules;
}
#endregion
//********************************************
#region Api tạo danh sach luật: Hình thức xét tuyển => <NAME>c
[Route("createhinhthuckhuvuc")]
[HttpGet]
[AllowAnonymous]
public HttpResponseMessage Create(HttpRequestMessage request, int idLoaiLuat, double sup, double con)
{
return CreateHttpResponse(request, () =>
{
HttpResponseMessage response = null;
if (!ModelState.IsValid)
{
response = request.CreateResponse(HttpStatusCode.BadRequest, ModelState);
}
else
{
List<ClssRules> allRules = GetRulesXetTuyen(sup, con);
//Xóa những dữ liệu luật cũ theo idLoaiLuat
var listLuatTheoIdLoaiLuat = _luatService.GetAll(idLoaiLuat);
foreach (var item in listLuatTheoIdLoaiLuat)
{
_luatService.DeleteItem(item);
}
_luatService.Save();
//Đẩy danh sach các luật vào cơ sở dữ liệu
foreach (ClssRules rule in allRules)
{
Luat luat = new Luat
{
X = rule.X.ToString(),
Y = rule.Y.ToString(),
Support = (decimal)rule.Support,
Confidence = (decimal)rule.Confidence,
LuatId = idLoaiLuat //Thêm loại luật để phân biệt giữa các luật
};
_luatService.Add(luat);
}
_luatService.Save();
var newListLuat = _luatService.GetAll(idLoaiLuat);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(newListLuat);
response = request.CreateResponse(HttpStatusCode.Created, responseData);
}
return response;
});
}
#endregion Api tạo danh sach luật: Hình thức xét tuyển => Khu vực
#region Hàm lấy ra danh sách các luật: Hình thức xét tuyển => Khu vực
public List<ClssRules> GetRulesXetTuyen(double sup, double con)
{
//double minSupport = Double.Parse(formCollection["MinSupport"]);
//double minConfidence = Double.Parse(formCollection["MinConfidence"]);
WebDbContext dbContext = new WebDbContext();
var dataListView = (from HoSoXetTuyens in dbContext.HoSoXetTuyens
from Tinhs in dbContext.Tinhs
where
HoSoXetTuyens.TruongTHPT.MaTinh == Tinhs.MaTinh
select new
{
HoSoXetTuyens.CMDN,
HoSoXetTuyens.TruongTHPT.TenTruong,
Tinhs.TenTinh,
HinhThucXetTuyen = (bool?)HoSoXetTuyens.DiemXetTuyen.HinhThucXetTuyen
}).ToList();
string result = "";
foreach (var item in dataListView)
{
db.Add(new clssItemSet()
{
(item.HinhThucXetTuyen == true ? "Thi tuyển" : "Học bạ"),
item.TenTinh
});
}
clssItemSet uniqueItems = db.GetUniqueItems();
ClssItemCollection L = clssApriori.DoApriori(db, sup);
List<ClssRules> allRules = clssApriori.Mine(db, L, con);
result = "\n" + allRules.Count + " rules \n";
return allRules;
}
#endregion Hàm lấy ra danh sách các luật: Hình thức xét tuyển => Khu vực
}
}<file_sep>/Web_Datamining/Web_Datamining.Model/Models/Lop.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("Lop")]
public class Lop
{
[Key]
[DatabaseGenerated(DatabaseGeneratedOption.None)]
public int ID_Lop { get; set; }
[Required]
[StringLength(10)]
public string MaChuyenNganh { get; set; }
[Required]
[StringLength(10)]
public string MaHeDaoTao { get; set; }
public int MaKhoaHoc { get; set; }
[StringLength(10)]
public string TenLop { get; set; }
public string MaKhoa { get; set; }
[ForeignKey("MaKhoa")]
public virtual Khoa Khoa { get; set; }
public virtual ChuyenNganh ChuyenNganh { get; set; }
public virtual HeDaoTao HeDaoTao { get; set; }
public virtual KhoaHoc KhoaHoc { get; set; }
public virtual ICollection<SinhVien> SinhVien { get; set; }
}
}
<file_sep>/README.md
# Web_Datamining_Hutech
Project Đồ án cơ sở + chuyên ngành
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/KhoaHocRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IKhoaHocRepository : IRepository<KhoaHoc>
{
}
public class KhoaHocRepository : RepositoryBase<KhoaHoc>, IKhoaHocRepository
{
public KhoaHocRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/DiemHocKyRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IDiemHocKyRepository : IRepository<DiemHocKy>
{
}
public class DiemHocKyRepository : RepositoryBase<DiemHocKy>, IDiemHocKyRepository
{
public DiemHocKyRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/ChuyenNganhRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IChuyenNganhRepository : IRepository<ChuyenNganh>
{
}
public class ChuyenNganRepository : RepositoryBase<ChuyenNganh>, IChuyenNganhRepository
{
public ChuyenNganRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Model/Models/KhaoSat.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
namespace Web_Datamining.Model.Models
{
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
[Table("KhaoSat")]
public class KhaoSat
{
[Key]
[DatabaseGenerated(DatabaseGeneratedOption.Identity)]
public int Id { get; set; }
[StringLength(15)]
[Required]
public string CMND { get; set; }
[StringLength(5)]
public string Khoi { get; set; }
public decimal? DiemMon1 { get; set; }
public decimal? DiemMon2 { get; set; }
public decimal? DiemMon3 { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/HocKyRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IHocKyRepository : IRepository<HocKy>
{
}
public class HocKyRepository : RepositoryBase<HocKy>, IHocKyRepository
{
public HocKyRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Model/Models/DiemHocKy.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("DiemHocKy")]
public class DiemHocKy
{
public int? SoTCDK { get; set; }
[Key]
[Column(Order = 0)]
[StringLength(15)]
public string MSSV { get; set; }
[Key]
[Column(Order = 1)]
public int ID_HocKi { get; set; }
public int? SoTCD { get; set; }
public int? SoTCTL { get; set; }
public double? DiemTBTLHe4 { get; set; }
public virtual ICollection<DiemCTHKy> DiemCTHKy { get; set; }
public virtual HocKy HocKy { get; set; }
public virtual SinhVien SinhVien { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Service/MonHoc.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Data.Repositories;
using Web_Datamining.Models;
namespace Web_Datamining.Service
{
public interface IMonHocService
{
MonHoc Add(MonHoc MonHoc);
void Update(MonHoc MonHoc);
MonHoc Delete(int id);
MonHoc DeleteItem(MonHoc item);
IEnumerable<MonHoc> GetAll();
IEnumerable<MonHoc> GetAll(string keyword);
MonHoc GetById(int id);
void Save();
}
public class MonHocService : IMonHocService
{
private IMonHocRepository _MonHocRepository;
private IUnitOfWork _unitOfWork;
public MonHocService(IMonHocRepository MonHocRepository, IUnitOfWork unitOfWork)
{
this._MonHocRepository = MonHocRepository;
this._unitOfWork = unitOfWork;
}
public MonHoc Add(MonHoc MonHoc)
{
return _MonHocRepository.Add(MonHoc);
}
public MonHoc Delete(int id)
{
return _MonHocRepository.Delete(id);
}
public MonHoc DeleteItem(MonHoc item)
{
return _MonHocRepository.Delete(item);
}
public IEnumerable<MonHoc> GetAll()
{
return _MonHocRepository.GetAll();
}
public IEnumerable<MonHoc> GetAll(string keyword)
{
if (!string.IsNullOrEmpty(keyword))
{
return _MonHocRepository.GetMulti(x => x.TenMon.Contains(keyword));
}
else
{
return _MonHocRepository.GetAll();
}
}
public MonHoc GetById(int id)
{
return _MonHocRepository.GetSingleById(id);
}
public void Save()
{
_unitOfWork.Commit();
}
public void Update(MonHoc MonHoc)
{
_MonHocRepository.Update(MonHoc);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Web/Models/KhoaViewModel.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Web;
namespace Web_Datamining.Web.Models
{
public class KhoaViewModel
{
public string MaKhoa { get; set; }
public string TenKhoa { get; set; }
}
}<file_sep>/Web_Datamining/Web_Datamining.Model/Models/DiemCTHKy.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("DiemCTHKy")]
public class DiemCTHKy
{
[Key]
[Column(Order = 0)]
[StringLength(10)]
public string MaMon { get; set; }
public double? DiemTH { get; set; }
public double? DiemQT { get; set; }
public double? DiemThi1 { get; set; }
public double? DiemThi2 { get; set; }
public double? TiLeDiemTH { get; set; }
public double? TiLeDiemQT { get; set; }
public double? TiLeDiemThi1 { get; set; }
public double? TiLeDiemThi2 { get; set; }
public double? DiemTKHe10 { get; set; }
public double? DiemTKHe4 { get; set; }
[StringLength(50)]
public string DiemTKChu { get; set; }
[Key]
[Column(Order = 1)]
[StringLength(15)]
public string MSSV { get; set; }
[Key]
[Column(Order = 2)]
public int ID_HocKi { get; set; }
public virtual DiemHocKy DiemHocKy { get; set; }
public virtual MonHoc MonHoc { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/HeDaoTaoRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IHeDaoTaoRepository : IRepository<HeDaoTao>
{
}
public class HeDaoTaoRepository : RepositoryBase<HeDaoTao>, IHeDaoTaoRepository
{
public HeDaoTaoRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/Areas/Admin/Controllers/DiemXetTuyensController.cs
using System;
using System.Collections.Generic;
using System.Data;
using System.Data.Entity;
using System.Linq;
using System.Net;
using System.Web;
using System.Web.Mvc;
using Web_Datamining.Data;
using Web_Datamining.Models;
namespace Web_Datamining.Web.Areas.Admin.Controllers
{
public class DiemXetTuyensController : Controller
{
private WebDbContext db = new WebDbContext();
// GET: Admin/DiemXetTuyens
public ActionResult Index()
{
return View(db.DiemXetTuyens.ToList());
}
// GET: Admin/DiemXetTuyens/Details/5
public ActionResult Details(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DiemXetTuyen diemXetTuyen = db.DiemXetTuyens.Find(id);
if (diemXetTuyen == null)
{
return HttpNotFound();
}
return View(diemXetTuyen);
}
// GET: Admin/DiemXetTuyens/Create
public ActionResult Create()
{
return View();
}
// POST: Admin/DiemXetTuyens/Create
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Create([Bind(Include = "DXT_ID,DiemToan,DiemVan,DiemLy,DiemHoa,DiemSinh,DiemDia,DiemGDCD,DiemNN,HinhThucXetTuyen")] DiemXetTuyen diemXetTuyen)
{
if (ModelState.IsValid)
{
db.DiemXetTuyens.Add(diemXetTuyen);
db.SaveChanges();
return RedirectToAction("Index");
}
return View(diemXetTuyen);
}
// GET: Admin/DiemXetTuyens/Edit/5
public ActionResult Edit(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DiemXetTuyen diemXetTuyen = db.DiemXetTuyens.Find(id);
if (diemXetTuyen == null)
{
return HttpNotFound();
}
return View(diemXetTuyen);
}
// POST: Admin/DiemXetTuyens/Edit/5
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Edit([Bind(Include = "DXT_ID,DiemToan,DiemVan,DiemLy,DiemHoa,DiemSinh,DiemDia,DiemGDCD,DiemNN,HinhThucXetTuyen")] DiemXetTuyen diemXetTuyen)
{
if (ModelState.IsValid)
{
db.Entry(diemXetTuyen).State = EntityState.Modified;
db.SaveChanges();
return RedirectToAction("Index");
}
return View(diemXetTuyen);
}
// GET: Admin/DiemXetTuyens/Delete/5
public ActionResult Delete(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DiemXetTuyen diemXetTuyen = db.DiemXetTuyens.Find(id);
if (diemXetTuyen == null)
{
return HttpNotFound();
}
return View(diemXetTuyen);
}
// POST: Admin/DiemXetTuyens/Delete/5
[HttpPost, ActionName("Delete")]
[ValidateAntiForgeryToken]
public ActionResult DeleteConfirmed(int id)
{
DiemXetTuyen diemXetTuyen = db.DiemXetTuyens.Find(id);
db.DiemXetTuyens.Remove(diemXetTuyen);
db.SaveChanges();
return RedirectToAction("Index");
}
protected override void Dispose(bool disposing)
{
if (disposing)
{
db.Dispose();
}
base.Dispose(disposing);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Service/KhaoSatService.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Data.Repositories;
using Web_Datamining.Model.Models;
namespace Web_Datamining.Service
{
public interface IKhaoSatService
{
KhaoSat Add(KhaoSat KhaoSat);
void Update(KhaoSat KhaoSat);
KhaoSat Delete(int id);
KhaoSat DeleteItem(KhaoSat item);
IEnumerable<KhaoSat> GetAll();
IEnumerable<KhaoSat> GetAll(int idKhaoSat);
void Save();
}
public class KhaoSatService : IKhaoSatService
{
private IKhaoSatRepository _KhaoSatRepository;
private IUnitOfWork _unitOfWork;
public KhaoSatService(IKhaoSatRepository KhaoSatRepository, IUnitOfWork unitOfWork)
{
this._KhaoSatRepository = KhaoSatRepository;
this._unitOfWork = unitOfWork;
}
public KhaoSat Add(KhaoSat KhaoSat)
{
return _KhaoSatRepository.Add(KhaoSat);
}
public KhaoSat Delete(int id)
{
return _KhaoSatRepository.Delete(id);
}
public KhaoSat DeleteItem(KhaoSat item)
{
return _KhaoSatRepository.Add(item);
}
public IEnumerable<KhaoSat> GetAll()
{
return _KhaoSatRepository.GetAll();
}
public IEnumerable<KhaoSat> GetAll(int idKhaoSat)
{
var listKhaoSat = _KhaoSatRepository.GetMulti(x => x.Id == idKhaoSat);
if (listKhaoSat == null)
{
return _KhaoSatRepository.GetAll();
}
else
{
return listKhaoSat;
}
}
public void Save()
{
_unitOfWork.Commit();
}
public void Update(KhaoSat KhaoSat)
{
_KhaoSatRepository.Update(KhaoSat);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/KhaoSatRepository.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Model.Models;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IKhaoSatRepository : IRepository<KhaoSat>
{
}
public class KhaoSatRepository : RepositoryBase<KhaoSat>, IKhaoSatRepository
{
public KhaoSatRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/MonHocRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IMonHocRepository : IRepository<MonHoc>
{
}
public class MonHocRepository : RepositoryBase<MonHoc>, IMonHocRepository
{
public MonHocRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/HoSoXetTuyenRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IHoSoXetTuyenRepository : IRepository<HoSoXetTuyen>
{
}
public class HoSoXetTuyenRepository : RepositoryBase<HoSoXetTuyen>, IHoSoXetTuyenRepository
{
public HoSoXetTuyenRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/Api/KhaoSatController.cs
using AutoMapper;
using System.Collections.Generic;
using System.Linq;
using System.Net;
using System.Net.Http;
using System.Web.Http;
using Web_Datamining.Data;
using Web_Datamining.Model.Models;
using Web_Datamining.Models;
using Web_Datamining.Service;
using Web_Datamining.Web.Infrastructure.Core;
using Web_Datamining.Web.Models;
namespace Web_Datamining.Web.Api
{
[RoutePrefix("api/Khaosat")]
[AllowCrossSiteJson]
public class KhaoSatController : ApiControllerBase
{
#region Contructor
private IKhaoSatService _khaosatService;
public KhaoSatController(IErrorService errorService, IKhaoSatService khaosatService) : base(errorService)
{
this._khaosatService = khaosatService;
}
#endregion Contructor
[Route("create")]
[HttpGet]
[AllowAnonymous]
public HttpResponseMessage Create(HttpRequestMessage request, string cmnd,string khoi,double d1,double d2,double d3)
{
return CreateHttpResponse(request, () =>
{
HttpResponseMessage response = null;
if (!ModelState.IsValid)
{
response = request.CreateResponse(HttpStatusCode.BadRequest, ModelState);
}
else
{
//THEM kHAO SAT
KhaoSat KhaoSat = new KhaoSat
{
CMND = cmnd.ToString(),
Khoi = khoi.ToString(),
DiemMon1 = (decimal)d1,
DiemMon2 = (decimal)d2,
DiemMon3 = (decimal)d3,
};
_khaosatService.Add(KhaoSat);
_khaosatService.Save();
response = Request.CreateResponse("Them Thanh Cong");
}
return response;
});
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Model/Models/KhoaHoc.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("KhoaHoc")]
public class KhoaHoc
{
[Key]
[DatabaseGenerated(DatabaseGeneratedOption.None)]
public int MaKhoaHoc { get; set; }
[StringLength(10)]
public string NamHoc { get; set; }
public virtual ICollection<Lop> Lop { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Web/Models/LuatXetTuyenViewModel.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Web;
namespace Web_Datamining.Web.Models
{
public class LuatXetTuyenViewModel
{
public int Id { get; set; }
public string X { get; set; }
public string Y { get; set; }
public decimal? Support { get; set; }
public decimal? Confidence { get; set; }
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/Areas/Admin/Controllers/DSNguyenVongsController.cs
using System;
using System.Collections.Generic;
using System.Data;
using System.Data.Entity;
using System.Linq;
using System.Net;
using System.Web;
using System.Web.Mvc;
using Web_Datamining.Data;
using Web_Datamining.Models;
namespace Web_Datamining.Web.Areas.Admin.Controllers
{
public class DSNguyenVongsController : Controller
{
private WebDbContext db = new WebDbContext();
// GET: Admin/DSNguyenVongs
public ActionResult Index()
{
var dSNguyenVongs = db.DSNguyenVongs.Include(d => d.HoSoXetTuyen).Include(d => d.NganhTheoBo).Include(d => d.ToHopMon);
return View(dSNguyenVongs.ToList());
}
// GET: Admin/DSNguyenVongs/Details/5
public ActionResult Details(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DSNguyenVong dSNguyenVong = db.DSNguyenVongs.Find(id);
if (dSNguyenVong == null)
{
return HttpNotFound();
}
return View(dSNguyenVong);
}
// GET: Admin/DSNguyenVongs/Create
public ActionResult Create()
{
ViewBag.MaHoSo = new SelectList(db.HoSoXetTuyens, "MaHoSo", "CMDN");
ViewBag.MaNganh = new SelectList(db.NganhTheoBos, "MaNganh", "TeNganh");
ViewBag.MaToHop = new SelectList(db.ToHopMons, "MaToHop", "Mon1");
return View();
}
// POST: Admin/DSNguyenVongs/Create
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Create([Bind(Include = "MaHoSo,ThuTuNV,MaToHop,MaNganh,MaTDH,TrangThaiNV")] DSNguyenVong dSNguyenVong)
{
if (ModelState.IsValid)
{
db.DSNguyenVongs.Add(dSNguyenVong);
db.SaveChanges();
return RedirectToAction("Index");
}
ViewBag.MaHoSo = new SelectList(db.HoSoXetTuyens, "MaHoSo", "CMDN", dSNguyenVong.MaHoSo);
ViewBag.MaNganh = new SelectList(db.NganhTheoBos, "MaNganh", "TeNganh", dSNguyenVong.MaNganh);
ViewBag.MaToHop = new SelectList(db.ToHopMons, "MaToHop", "Mon1", dSNguyenVong.MaToHop);
return View(dSNguyenVong);
}
// GET: Admin/DSNguyenVongs/Edit/5
public ActionResult Edit(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DSNguyenVong dSNguyenVong = db.DSNguyenVongs.Find(id);
if (dSNguyenVong == null)
{
return HttpNotFound();
}
ViewBag.MaHoSo = new SelectList(db.HoSoXetTuyens, "MaHoSo", "CMDN", dSNguyenVong.MaHoSo);
ViewBag.MaNganh = new SelectList(db.NganhTheoBos, "MaNganh", "TeNganh", dSNguyenVong.MaNganh);
ViewBag.MaToHop = new SelectList(db.ToHopMons, "MaToHop", "Mon1", dSNguyenVong.MaToHop);
return View(dSNguyenVong);
}
// POST: Admin/DSNguyenVongs/Edit/5
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Edit([Bind(Include = "MaHoSo,ThuTuNV,MaToHop,MaNganh,MaTDH,TrangThaiNV")] DSNguyenVong dSNguyenVong)
{
if (ModelState.IsValid)
{
db.Entry(dSNguyenVong).State = EntityState.Modified;
db.SaveChanges();
return RedirectToAction("Index");
}
ViewBag.MaHoSo = new SelectList(db.HoSoXetTuyens, "MaHoSo", "CMDN", dSNguyenVong.MaHoSo);
ViewBag.MaNganh = new SelectList(db.NganhTheoBos, "MaNganh", "TeNganh", dSNguyenVong.MaNganh);
ViewBag.MaToHop = new SelectList(db.ToHopMons, "MaToHop", "Mon1", dSNguyenVong.MaToHop);
return View(dSNguyenVong);
}
// GET: Admin/DSNguyenVongs/Delete/5
public ActionResult Delete(int? id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
DSNguyenVong dSNguyenVong = db.DSNguyenVongs.Find(id);
if (dSNguyenVong == null)
{
return HttpNotFound();
}
return View(dSNguyenVong);
}
// POST: Admin/DSNguyenVongs/Delete/5
[HttpPost, ActionName("Delete")]
[ValidateAntiForgeryToken]
public ActionResult DeleteConfirmed(int id)
{
DSNguyenVong dSNguyenVong = db.DSNguyenVongs.Find(id);
db.DSNguyenVongs.Remove(dSNguyenVong);
db.SaveChanges();
return RedirectToAction("Index");
}
protected override void Dispose(bool disposing)
{
if (disposing)
{
db.Dispose();
}
base.Dispose(disposing);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/TruongTHPT.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("TruongTHPT")]
public class TruongTHPT
{
[Key]
[DatabaseGenerated(DatabaseGeneratedOption.None)]
public int MaTruongTHPT { get; set; }
public int MaHuyen { get; set; }
public int MaTinh { get; set; }
[StringLength(50)]
public string TenTruong { get; set; }
public virtual ICollection<HoSoXetTuyen> HoSoXetTuyen { get; set; }
public virtual Huyen Huyen { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/TinhRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface ITinhRepository : IRepository<Tinh>
{
}
public class TinhRepository : RepositoryBase<Tinh>, ITinhRepository
{
public TinhRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/LuatModel/ListViewXetTuyen.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Web;
namespace Web_Datamining.Web.LuatModel
{
public class ListViewXetTuyen
{
public int MaHoSo { get; set; }
public string HoTen { get; set; }
public string GioiTinh { get; set; }
public string TinhTrangTrungTuyen { get; set; }
public string TongDiem { get; set; }
public string KhoaXetTuyen { get; set; }
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/KhoaRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IKhoaRepository : IRepository<Khoa>
{
}
public class KhoaRepository : RepositoryBase<Khoa>, IKhoaRepository
{
public KhoaRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/TruongTHPTRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface ITruongTHPTRepository : IRepository<TruongTHPT>
{
}
public class TruongTHPTRepository : RepositoryBase<TruongTHPT>, ITruongTHPTRepository
{
public TruongTHPTRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/SinhVienRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface ISinhVienBoRepository : IRepository<SinhVien>
{
}
public class SinhVienRepository : RepositoryBase<SinhVien>, ISinhVienBoRepository
{
public SinhVienRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Service/LuatXetTuyenService.cs
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Data.Repositories;
using Web_Datamining.Models;
namespace Web_Datamining.Service
{
//public interface ILoaiLuatService
//{
// LoaiLuat Add(LoaiLuat LoaiLuat);
// void Update(LoaiLuat LoaiLuat);
// LoaiLuat Delete(int id);
// LoaiLuat DeleteItem(LoaiLuat item);
// IEnumerable<LoaiLuat> GetAll();
// IEnumerable<LoaiLuat> GetAll(string keyword);
// LoaiLuat GetById(int id);
// void Save();
//}
//public class LoaiLuatService : ILoaiLuatService
//{
// private ILoaiLuatnRepository _LoaiLuatRepository;
// private IUnitOfWork _unitOfWork;
// public LoaiLuatService(ILoaiLuatnRepository LoaiLuatRepository, IUnitOfWork unitOfWork)
// {
// this._LoaiLuatRepository = LoaiLuatRepository;
// this._unitOfWork = unitOfWork;
// }
// public LoaiLuat Add(LoaiLuat LoaiLuat)
// {
// return _LoaiLuatRepository.Add(LoaiLuat);
// }
// public LoaiLuat Delete(int id)
// {
// return _LoaiLuatRepository.Delete(id);
// }
// public LoaiLuat DeleteItem(LoaiLuat item)
// {
// return _LoaiLuatRepository.Delete(item);
// }
// public IEnumerable<LoaiLuat> GetAll()
// {
// return _LoaiLuatRepository.GetAll();
// }
// public IEnumerable<LoaiLuat> GetAll(string keyword)
// {
// if (!string.IsNullOrEmpty(keyword))
// {
// return _LoaiLuatRepository.GetMulti(x => x.X.Contains(keyword) || x.Y.Contains(keyword));
// }
// else
// {
// return _LoaiLuatRepository.GetAll();
// }
// }
// public LoaiLuat GetById(int id)
// {
// return _LoaiLuatRepository.GetSingleById(id);
// }
// public void Save()
// {
// _unitOfWork.Commit();
// }
// public void Update(LoaiLuat LoaiLuat)
// {
// _LoaiLuatRepository.Update(LoaiLuat);
// }
//}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/DiemCTHKyRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IDiemCTHKyRepository : IRepository<DiemCTHKy>
{
}
public class DiemCTHKyRepository : RepositoryBase<DiemCTHKy>, IDiemCTHKyRepository
{
public DiemCTHKyRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/ToHopMonRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IToHopMonRepository : IRepository<ToHopMon>
{
}
public class ToHopMonRepository : RepositoryBase<ToHopMon>, IToHopMonRepository
{
public ToHopMonRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/Areas/Admin/Controllers/HeDaoTaosController.cs
using System;
using System.Collections.Generic;
using System.Data;
using System.Data.Entity;
using System.Linq;
using System.Net;
using System.Web;
using System.Web.Mvc;
using Web_Datamining.Data;
using Web_Datamining.Models;
namespace Web_Datamining.Web.Areas.Admin.Controllers
{
public class HeDaoTaosController : Controller
{
private WebDbContext db = new WebDbContext();
// GET: Admin/HeDaoTaos
public ActionResult Index()
{
return View(db.HeDaoTaos.ToList());
}
// GET: Admin/HeDaoTaos/Details/5
public ActionResult Details(string id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
HeDaoTao heDaoTao = db.HeDaoTaos.Find(id);
if (heDaoTao == null)
{
return HttpNotFound();
}
return View(heDaoTao);
}
// GET: Admin/HeDaoTaos/Create
public ActionResult Create()
{
return View();
}
// POST: Admin/HeDaoTaos/Create
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Create([Bind(Include = "MaHeDaoTao,TenHeDaoTao")] HeDaoTao heDaoTao)
{
if (ModelState.IsValid)
{
db.HeDaoTaos.Add(heDaoTao);
db.SaveChanges();
return RedirectToAction("Index");
}
return View(heDaoTao);
}
// GET: Admin/HeDaoTaos/Edit/5
public ActionResult Edit(string id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
HeDaoTao heDaoTao = db.HeDaoTaos.Find(id);
if (heDaoTao == null)
{
return HttpNotFound();
}
return View(heDaoTao);
}
// POST: Admin/HeDaoTaos/Edit/5
// To protect from overposting attacks, please enable the specific properties you want to bind to, for
// more details see http://go.microsoft.com/fwlink/?LinkId=317598.
[HttpPost]
[ValidateAntiForgeryToken]
public ActionResult Edit([Bind(Include = "MaHeDaoTao,TenHeDaoTao")] HeDaoTao heDaoTao)
{
if (ModelState.IsValid)
{
db.Entry(heDaoTao).State = EntityState.Modified;
db.SaveChanges();
return RedirectToAction("Index");
}
return View(heDaoTao);
}
// GET: Admin/HeDaoTaos/Delete/5
public ActionResult Delete(string id)
{
if (id == null)
{
return new HttpStatusCodeResult(HttpStatusCode.BadRequest);
}
HeDaoTao heDaoTao = db.HeDaoTaos.Find(id);
if (heDaoTao == null)
{
return HttpNotFound();
}
return View(heDaoTao);
}
// POST: Admin/HeDaoTaos/Delete/5
[HttpPost, ActionName("Delete")]
[ValidateAntiForgeryToken]
public ActionResult DeleteConfirmed(string id)
{
HeDaoTao heDaoTao = db.HeDaoTaos.Find(id);
db.HeDaoTaos.Remove(heDaoTao);
db.SaveChanges();
return RedirectToAction("Index");
}
protected override void Dispose(bool disposing)
{
if (disposing)
{
db.Dispose();
}
base.Dispose(disposing);
}
}
}
<file_sep>/Web_Datamining/Web_Datamining.Model/Models/HoSoXetTuyen.cs
namespace Web_Datamining.Models
{
using System;
using System.Collections.Generic;
using System.ComponentModel.DataAnnotations;
using System.ComponentModel.DataAnnotations.Schema;
using System.Data.Entity.Spatial;
[Table("HoSoXetTuyen")]
public class HoSoXetTuyen
{
[Key]
[DatabaseGenerated(DatabaseGeneratedOption.None)]
public int MaHoSo { get; set; }
public int MaTruongTHPT { get; set; }
[StringLength(15)]
public string CMDN { get; set; }
[Column(TypeName = "smalldatetime")]
public DateTime? NgaySinh { get; set; }
[StringLength(50)]
public string HoTen { get; set; }
public int? GioiTinh { get; set; }
[StringLength(30)]
public string DanToc { get; set; }
public int? TinhTrangTrungTuyen { get; set; }
public int DXT_ID { get; set; }
public virtual DiemXetTuyen DiemXetTuyen { get; set; }
public virtual ICollection<DSNguyenVong> DSNguyenVong { get; set; }
public virtual TruongTHPT TruongTHPT { get; set; }
public virtual ICollection<SinhVien> SinhVien { get; set; }
}
}
<file_sep>/Web_Datamining/Web_Datamining.Data/Repositories/DiemXetTuyenRepository.cs
using Web_Datamining.Data.Infrastructure;
using Web_Datamining.Models;
namespace Web_Datamining.Data.Repositories
{
public interface IDiemXetTuyenRepository : IRepository<DiemXetTuyen>
{
}
public class DiemXetTuyenRepository : RepositoryBase<DiemXetTuyen>, IDiemXetTuyenRepository
{
public DiemXetTuyenRepository(IDbFactory dbFactory) : base(dbFactory)
{
}
}
}<file_sep>/Web_Datamining/Web_Datamining.Web/Api/LuatXetTuyenController.cs
using AutoMapper;
using System;
using System.Collections.Generic;
using System.Linq;
using System.Net;
using System.Net.Http;
using System.Web.Http;
using Web_Datamining.Data;
using Web_Datamining.Models;
using Web_Datamining.Service;
using Web_Datamining.Web.Infrastructure.Core;
using Web_Datamining.Web.Models;
namespace Web_Datamining.Web.Api
{
[RoutePrefix("api/luatxettuyen")]
[AllowCrossSiteJson]
public class LuatXetTuyenController : ApiControllerBase
{
#region Contructor
private ILuatService _luatService;
public LuatXetTuyenController(IErrorService errorService, ILuatService luatService) : base(errorService)
{
this._luatService = luatService;
}
//Db classitem hỗ trợ thuật toán apriori
private ClssItemCollection db = new ClssItemCollection();
#endregion Contructor
#region Api lấy sử dụng luật
[Route("getall")]
[HttpGet]
public HttpResponseMessage GetAll(HttpRequestMessage request, int idLoaiLuat)
{
return CreateHttpResponse(request, () =>
{
int totalRow = 0;
var model = _luatService.GetAll(idLoaiLuat);
totalRow = model.Count();
var query = model.OrderByDescending(x => x.X);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(query);
var response = request.CreateResponse(HttpStatusCode.OK, responseData);
return response;
});
}
#endregion Api lấy sử dụng luật
#region Api tìm kiếm luật xét tuyển (Loai+keyword+diemtong)
[Route("findrules")]
[HttpGet]
public HttpResponseMessage FindRules(HttpRequestMessage request, int idLoaiLuat,string keyword,string dt)
{
//float diemtong = float.Parse(dt);
//diemtong = (float)Math.Round(diemtong, 0);
//dt = diemtong.ToString();
return CreateHttpResponse(request, () =>
{
int totalRow = 0;
var model = _luatService.GetAll(idLoaiLuat,keyword,dt);
totalRow = model.Count();
var query = model.OrderByDescending(x => x.X);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(query);
var response = request.CreateResponse(HttpStatusCode.OK, responseData);
return response;
});
}
#endregion Api tìm kiếm luật xét tuyển
#region Api tìm kiếm luật xét tuyển (Loai+keyword)
[Route("findrules1")]
[HttpGet]
public HttpResponseMessage FindRules1(HttpRequestMessage request, int idLoaiLuat, string keyword)
{
return CreateHttpResponse(request, () =>
{
int totalRow = 0;
var model = _luatService.GetAll(idLoaiLuat, keyword);
totalRow = model.Count();
var query = model.OrderByDescending(x => x.X);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(query);
var response = request.CreateResponse(HttpStatusCode.OK, responseData);
return response;
});
}
#endregion Api tìm kiếm luật xét tuyển
#region Api Xóa luật
[Route("deleterule")]
[HttpGet]
public HttpResponseMessage DeleteRule(HttpRequestMessage request, int keyword)
{
return CreateHttpResponse(request, () =>
{
var item = _luatService.GetById(keyword);
var model = _luatService.DeleteItem(item);
_luatService.Save();
var response = request.CreateResponse(HttpStatusCode.OK, "Xóa thành công");
return response;
});
}
#endregion Api xóa luật
//********************************************
#region Ham lay ra ds cac luat :Hoc ba: Nganh=> diem xet tuyen
public List<ClssRules> XTHocBa(double sup, double con)
{
//double minSupport = Double.Parse(formCollection["MinSupport"]);
//double minConfidence = Double.Parse(formCollection["MinConfidence"]);
WebDbContext dbContext = new WebDbContext();
var dataListView = (from ds in dbContext.DSNguyenVongs
where
ds.HoSoXetTuyen.DiemXetTuyen.HinhThucXetTuyen == false &&
ds.HoSoXetTuyen.TinhTrangTrungTuyen == 1
select new
{
ds.NganhTheoBo.TeNganh,
TongDiem = (ds.DiemTong < 30) ? (ds.DiemTong > 27) ? "[28,29,30]"
: (ds.DiemTong > 24) ? "[25,26,27]"
: (ds.DiemTong > 21) ? "[22,23,24]"
: (ds.DiemTong > 18) ? "[19,20,21]"
: (ds.DiemTong > 15) ? "[16,17,18]"
: "[0..12,13,14,15]" : ""
}).ToList();
string result = "";
foreach (var item in dataListView)
{
db.Add(new clssItemSet()
{
item.TeNganh,
Convert.ToString(item.TongDiem)
});
}
clssItemSet uniqueItems = db.GetUniqueItems();
ClssItemCollection L = clssApriori.DoApriori(db, sup);
List<ClssRules> allRules = clssApriori.Mine(db, L, con);
result = "\n" + allRules.Count + " rules \n";
return allRules;
}
#endregion Ham lay ra ds cac luat :Hoc ba: Nganh=> diem xet tuyen
#region Api tao ds luat : hoc ba: Nganh=>Diem xet tuyen
[Route("createxthb")]
[HttpGet]
[AllowAnonymous]
public HttpResponseMessage CreateXTHB(HttpRequestMessage request, int idLoaiLuat, double sup, double con)
{
return CreateHttpResponse(request, () =>
{
HttpResponseMessage response = null;
if (!ModelState.IsValid)
{
response = request.CreateResponse(HttpStatusCode.BadRequest, ModelState);
}
else
{
List<ClssRules> allRules = XTHocBa(sup, con);
//Xóa những dữ liệu luật cũ theo idLoaiLuat
var listLuatTheoIdLoaiLuat = _luatService.GetAll(idLoaiLuat);
foreach (var item in listLuatTheoIdLoaiLuat)
{
_luatService.DeleteItem(item);
}
_luatService.Save();
//Đẩy danh sach các luật vào cơ sở dữ liệu
foreach (ClssRules rule in allRules)
{
Luat luat = new Luat
{
X = rule.X.ToString(),
Y = rule.Y.ToString(),
Support = (decimal)rule.Support,
Confidence = (decimal)rule.Confidence,
LuatId = idLoaiLuat //Thêm loại luật để phân biệt giữa các luật
};
_luatService.Add(luat);
}
_luatService.Save();
var newListLuat = _luatService.GetAll(idLoaiLuat);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(newListLuat);
response = request.CreateResponse(HttpStatusCode.Created, responseData);
}
return response;
});
}
#endregion Api tao ds luat : hoc ba: Nganh=>Diem xet tuyen
//*****************
#region Ham lay ra ds cac luat :Thi Tuyen: Nganh=> diem xet tuyen
public List<ClssRules> ThiTuyen(double sup, double con)
{
//double minSupport = Double.Parse(formCollection["MinSupport"]);
//double minConfidence = Double.Parse(formCollection["MinConfidence"]);
WebDbContext dbContext = new WebDbContext();
var dataListView = (from ds in dbContext.DSNguyenVongs
where
ds.HoSoXetTuyen.DiemXetTuyen.HinhThucXetTuyen == false &&
ds.HoSoXetTuyen.TinhTrangTrungTuyen == 1
select new
{
ds.NganhTheoBo.TeNganh,
TongDiem = (ds.DiemTong < 30) ? (ds.DiemTong > 27) ? "[28,29,30]"
: (ds.DiemTong > 24) ? "[25,26,27]"
: (ds.DiemTong > 21) ? "[22,23,24]"
: (ds.DiemTong > 18) ? "[19,20,21]"
: (ds.DiemTong > 15) ? "[16,17,18]"
: "[0..12,13,14,15]" : ""
}).ToList();
string result = "";
foreach (var item in dataListView)
{
db.Add(new clssItemSet()
{
item.TeNganh,
Convert.ToString(item.TongDiem)
});
}
clssItemSet uniqueItems = db.GetUniqueItems();
ClssItemCollection L = clssApriori.DoApriori(db, sup);
List<ClssRules> allRules = clssApriori.Mine(db, L, con);
result = "\n" + allRules.Count + " rules \n";
return allRules;
}
#endregion Ham lay ra ds cac luat :Thi Tuyen: Nganh=> diem xet tuyen
#region Api tao ds luat : hoc ba: Nganh=>Diem xet tuyen
[Route("createthituyen")]
[HttpGet]
[AllowAnonymous]
public HttpResponseMessage CreateThiTuyen(HttpRequestMessage request, int idLoaiLuat, double sup, double con)
{
return CreateHttpResponse(request, () =>
{
HttpResponseMessage response = null;
if (!ModelState.IsValid)
{
response = request.CreateResponse(HttpStatusCode.BadRequest, ModelState);
}
else
{
List<ClssRules> allRules = ThiTuyen(sup, con);
//Xóa những dữ liệu luật cũ theo idLoaiLuat
var listLuatTheoIdLoaiLuat = _luatService.GetAll(idLoaiLuat);
foreach (var item in listLuatTheoIdLoaiLuat)
{
_luatService.DeleteItem(item);
}
_luatService.Save();
//Đẩy danh sach các luật vào cơ sở dữ liệu
foreach (ClssRules rule in allRules)
{
Luat luat = new Luat
{
X = rule.X.ToString(),
Y = rule.Y.ToString(),
Support = (decimal)rule.Support,
Confidence = (decimal)rule.Confidence,
LuatId = idLoaiLuat //Thêm loại luật để phân biệt giữa các luật
};
_luatService.Add(luat);
}
_luatService.Save();
var newListLuat = _luatService.GetAll(idLoaiLuat);
var responseData = Mapper.Map<IEnumerable<Luat>, List<LuatViewModel>>(newListLuat);
response = request.CreateResponse(HttpStatusCode.Created, responseData);
}
return response;
});
}
#endregion Api tao ds luat : hoc ba: Thi Tuyển =>Diem xet tuyen
}
} | ac0883fd45437c5caf97640465d41ba5216a8c5b | [
"Markdown",
"C#"
] | 76 | C# | trandinhson2112cntt/Web_Datamining_Hutech | 239561bb18fefbc2819c0722dd3a31784df32cfc | 424a1896d10de4fca2c3287a59fe8bf114667154 |
refs/heads/master | <repo_name>Eraldo-Pessoal/star-wars-planets<file_sep>/src/main/java/br/com/eraldoborel/starwarsplanets/repository/PlanetaRepository.java
package br.com.eraldoborel.starwarsplanets.repository;
import java.util.Optional;
import org.springframework.data.mongodb.repository.MongoRepository;
import br.com.eraldoborel.starwarsplanets.model.Planeta;
public interface PlanetaRepository extends MongoRepository<Planeta, String> {
Optional<Planeta> findByNomeIgnoreCase(String nome);
Optional<Planeta> findByNomeIgnoreCaseAndIdNot(String nome, String id);
Optional<Planeta> findOptionalById(String id);
}
<file_sep>/src/test/java/br/com/eraldoborel/starwarsplanets/service/PlanetaServiceTest.java
package br.com.eraldoborel.starwarsplanets.service;
import static org.junit.Assert.assertEquals;
import static org.mockito.Mockito.never;
import static org.mockito.Mockito.verify;
import static org.mockito.Mockito.when;
import java.util.Optional;
import org.junit.Before;
import org.junit.Test;
import org.junit.runner.RunWith;
import org.springframework.beans.factory.annotation.Autowired;
import org.springframework.boot.test.mock.mockito.MockBean;
import org.springframework.context.annotation.Bean;
import org.springframework.context.annotation.Configuration;
import org.springframework.test.context.junit4.SpringRunner;
import br.com.eraldoborel.starwarsplanets.model.Planeta;
import br.com.eraldoborel.starwarsplanets.repository.PlanetaRepository;
import br.com.eraldoborel.starwarsplanets.service.exceptions.NomeDuplicadoException;
import br.com.eraldoborel.starwarsplanets.service.exceptions.PlanetaNaoEncontradoException;
import br.com.eraldoborel.starwarsplanets.service.impl.PlanetaServiceImpl;
@RunWith(SpringRunner.class)
public class PlanetaServiceTest {
@MockBean
private PlanetaRepository repository;
@MockBean
private AparicoesFilmesSWService aparicoesFilmesSWService;
@Autowired
private PlanetaService servico;
private Planeta planeta;
@Configuration
static class someConfig {
@Bean
PlanetaService serv( ) {
return new PlanetaServiceImpl();
}
}
@Before
public void setUp() throws Exception {
//servico = new PlanetaServiceImpl(repository, aparicoesFilmesSWService);
planeta = new Planeta("Terra");
when(repository.findByNomeIgnoreCase(planeta.getNome())).thenReturn(Optional.empty());
}
@Test
public void salvar_planeta() throws Exception {
servico.criar(planeta);
verify(repository).save(planeta);
}
@Test(expected = NomeDuplicadoException.class)
public void nao_salvar_dois_planetas_com_mesmo_nome() throws Exception {
when(repository.findByNomeIgnoreCase(planeta.getNome())).thenReturn(Optional.of(planeta));
servico.criar(planeta);
verify(repository, never()).save(planeta);
}
@Test
public void retorna_planeta_pelo_nome() throws Exception {
when(repository.findByNomeIgnoreCase(planeta.getNome())).thenReturn(Optional.of(planeta));
Planeta planeta_encontrado = servico.buscar_por_nome(planeta.getNome());
assertEquals(planeta.getNome(), planeta_encontrado.getNome());
}
@Test(expected = PlanetaNaoEncontradoException.class)
public void dispara_erro_quando_nao_encontra_planeta_pelo_nome() throws Exception {
servico.buscar_por_nome(planeta.getNome());
}
}
<file_sep>/src/main/java/br/com/eraldoborel/starwarsplanets/service/impl/PlanetaServiceImpl.java
package br.com.eraldoborel.starwarsplanets.service.impl;
import java.util.List;
import java.util.Optional;
import org.springframework.beans.factory.annotation.Autowired;
import org.springframework.stereotype.Service;
import br.com.eraldoborel.starwarsplanets.model.Planeta;
import br.com.eraldoborel.starwarsplanets.repository.PlanetaRepository;
import br.com.eraldoborel.starwarsplanets.service.AparicoesFilmesSWService;
import br.com.eraldoborel.starwarsplanets.service.PlanetaService;
import br.com.eraldoborel.starwarsplanets.service.exceptions.ApiSWIndisponivelException;
import br.com.eraldoborel.starwarsplanets.service.exceptions.NomeDuplicadoException;
import br.com.eraldoborel.starwarsplanets.service.exceptions.PlanetaNaoEncontradoException;
@Service
public class PlanetaServiceImpl implements PlanetaService {
@Autowired
private PlanetaRepository repository;
@Autowired
private AparicoesFilmesSWService aparicoesFilmesSWService;
@Override
public Planeta criar(Planeta planeta) throws NomeDuplicadoException, ApiSWIndisponivelException {
Optional<Planeta> resultado = repository.findByNomeIgnoreCase(planeta.getNome());
if (resultado.isPresent()) {
throw new NomeDuplicadoException("Já existe planeta cadastrado com o nome '" + planeta.getNome() + "'");
}
int qtde_aparicoes = aparicoesFilmesSWService.getNumeroAparicoes(planeta.getNome());
planeta.setQuantidadeAparicoesFilmes(qtde_aparicoes);
return repository.save(planeta);
}
@Override
public Planeta buscar_por_nome(String nome) throws PlanetaNaoEncontradoException {
Optional<Planeta> resultado = repository.findByNomeIgnoreCase(nome);
return resultado.orElseThrow(() -> new PlanetaNaoEncontradoException("Não existe planeta com o nome '" + nome + "'"));
}
@Override
public void apagar(String id) throws PlanetaNaoEncontradoException {
buscar_por_id(id);
repository.delete(id);
}
@Override
public Planeta buscar_por_id(String id) throws PlanetaNaoEncontradoException {
Optional<Planeta> resultado = repository.findOptionalById(id);
return resultado.orElseThrow(() -> new PlanetaNaoEncontradoException("Não existe planeta com o id '" + id + "'"));
}
@Override
public List<Planeta> findAll() {
return repository.findAll();
}
@Override
public Planeta atualizar(Planeta planeta) throws PlanetaNaoEncontradoException, NomeDuplicadoException, ApiSWIndisponivelException {
String id = planeta.getId();
Planeta planeta_existente = buscar_por_id(id );
Optional<Planeta> resultado = repository.findByNomeIgnoreCaseAndIdNot(planeta.getNome(), id);
if (resultado.isPresent()) {
throw new NomeDuplicadoException("Já existe planeta cadastrado com o nome '" + planeta.getNome() + "'");
}
int qtde_aparicoes = aparicoesFilmesSWService.getNumeroAparicoes(planeta.getNome());
planeta_existente.setNome(planeta.getNome());
planeta_existente.setClima(planeta.getClima());
planeta_existente.setTerreno(planeta.getTerreno());
planeta_existente.setQuantidadeAparicoesFilmes(qtde_aparicoes);
return repository.save(planeta_existente);
}
}
<file_sep>/src/it/java/br/com/eraldoborel/starwarsplanets/resource/PlanetaResourceTest.java
package br.com.eraldoborel.starwarsplanets.resource;
import static io.restassured.RestAssured.given;
import static org.hamcrest.CoreMatchers.startsWith;
import static org.hamcrest.Matchers.equalTo;
import static org.springframework.test.web.client.match.MockRestRequestMatchers.method;
import static org.springframework.test.web.client.match.MockRestRequestMatchers.requestTo;
import static org.springframework.test.web.client.response.MockRestResponseCreators.withUnauthorizedRequest;
import org.junit.Test;
import org.springframework.http.HttpMethod;
import org.springframework.http.HttpStatus;
import org.springframework.test.web.client.MockRestServiceServer;
import br.com.eraldoborel.starwarsplanets.StarWarsPlanetsBaseIntegrationTests;
import br.com.eraldoborel.starwarsplanets.model.Planeta;
import io.restassured.http.ContentType;
public class PlanetaResourceTest extends StarWarsPlanetsBaseIntegrationTests {
@Test
public void procura_pessoa_pelo_nome() {
given()
.pathParam("nome", "terra")
.when()
.get("/planetas/nome/{nome}/")
.then()
.log().body().and()
.statusCode(HttpStatus.OK.value())
.body("nome", equalTo("Terra"));
}
@Test
public void nao_encontra_pessoa_pelo_nome() {
given()
.pathParam("nome", "terrarrr")
.when()
.get("/planetas/nome/{nome}/")
.then()
.log().body()
.and()
.statusCode(HttpStatus.NOT_FOUND.value())
.body("erro", equalTo("Não existe planeta com o nome 'terrarrr'"));
}
@Test
public void salva_planeta() {
Planeta alderaan = new Planeta("Alderaan");
given()
.request()
.header("Accept", ContentType.ANY)
.header("Content-type", ContentType.JSON)
.body(alderaan)
.when()
.post("/planetas/")
.then()
.log().headers()
.and()
.log().body()
.and()
.statusCode(HttpStatus.CREATED.value())
.header("Location", startsWith("http://localhost:" + porta + "/planetas/"))
.body("nome", equalTo("Alderaan"))
.body("quantidadeAparicoesFilmes", equalTo(2));
}
@Test
public void nao_salva_planeta_com_nome_duplicado() {
Planeta terra2 = new Planeta("Terra");
given()
.request()
.header("Accept", ContentType.ANY)
.header("Content-type", ContentType.JSON)
.body(terra2)
.when()
.post("/planetas/")
.then()
.log().body()
.and()
.statusCode(HttpStatus.BAD_REQUEST.value())
.body("erro", equalTo("Já existe planeta cadastrado com o nome 'Terra'"));
}
@Test
public void remover_planeta() {
Planeta plutao = new Planeta("Plutão");
plutao = repository.save(plutao);
given()
.pathParam("id", plutao.getId())
.when()
.delete("/planetas/{id}/")
.then()
.log().body()
.and()
.statusCode(HttpStatus.OK.value())
.body("mensagem", equalTo("Planeta com o id '" + plutao.getId() + "' foi removido com sucesso."));
}
@Test
public void erro_ao_remover_planeta_nao_encontrado() {
given()
.pathParam("id", "ID0")
.when()
.delete("/planetas/{id}/")
.then()
.log().body()
.and()
.statusCode(HttpStatus.NOT_FOUND.value())
.body("erro", equalTo("Não existe planeta com o id 'ID0'"));
}
@Test
public void procura_pessoa_pelo_id() {
given()
.pathParam("id", terra.getId())
.when()
.get("/planetas/{id}/")
.then()
.log().body().and()
.statusCode(HttpStatus.OK.value())
.body("nome", equalTo("Terra"));
}
@Test
public void erro_ao_procurar_pessoa_pelo_id_que_nao_existe() {
given()
.pathParam("id", "ID0")
.when()
.get("/planetas/{id}/")
.then()
.log().body()
.and()
.statusCode(HttpStatus.NOT_FOUND.value())
.body("erro", equalTo("Não existe planeta com o id 'ID0'"));
}
@Test
public void listar_planetas() {
given()
.when()
.get("/planetas/")
.then()
.log().body().and()
.statusCode(HttpStatus.OK.value())
.body("[0].nome", equalTo("Terra"))
.body("[1].nome", equalTo("Saturno"))
.body("[2].nome", equalTo("Tatooine"));
}
@Test
public void atualizar_planeta() {
Planeta terra2 = new Planeta("Terra");
terra2.setId(terra.getId());
terra2.setClima("Temperado");
given()
.request()
.header("Accept", ContentType.ANY)
.header("Content-type", ContentType.JSON)
.body(terra2)
.when()
.put("/planetas/")
.then()
.log().headers()
.and()
.log().body()
.and()
.statusCode(HttpStatus.OK.value())
.header("Location", startsWith("http://localhost:" + porta + "/planetas/"))
.body("id", equalTo(terra.getId()))
.body("nome", equalTo("Terra"))
.body("clima", equalTo("Temperado"))
.body("quantidadeAparicoesFilmes", equalTo(1));
}
@Test
public void erro_ao_atualizar_planeta_que_nao_existe() {
Planeta terra2 = new Planeta("Terra");
terra2.setId("ID0");
terra2.setClima("Temperado");
given()
.request()
.header("Accept", ContentType.ANY)
.header("Content-type", ContentType.JSON)
.body(terra2)
.when()
.put("/planetas/")
.then()
.log().body()
.and()
.statusCode(HttpStatus.NOT_FOUND.value())
.body("erro", equalTo("Não existe planeta com o id 'ID0'"));
}
@Test
public void erro_ao_atualizar_planeta_gerando_duplicidade_de_nome() {
String nome = tatooine.getNome();
Planeta terra2 = new Planeta(nome);
terra2.setId(terra.getId());
terra2.setClima("Temperado");
given()
.request()
.header("Accept", ContentType.ANY)
.header("Content-type", ContentType.JSON)
.body(terra2)
.when()
.put("/planetas/")
.then()
.log().body()
.and()
.statusCode(HttpStatus.BAD_REQUEST.value())
.body("erro", equalTo("Já existe planeta cadastrado com o nome '" + nome + "'"));
}
@Test
public void api_sw_falha_ao_atualizar_planeta() {
mockServer = MockRestServiceServer.createServer(restTemplate);
mockServer.expect(requestTo(startsWith("https://swapi.co/")))
.andExpect(method(HttpMethod.GET))
.andRespond(
withUnauthorizedRequest()
);
String nome = tatooine.getNome();
Planeta terra2 = new Planeta(nome);
terra2.setId(tatooine.getId());
terra2.setClima("Temperado");
given()
.request()
.header("Accept", ContentType.ANY)
.header("Content-type", ContentType.JSON)
.body(terra2)
.when()
.put("/planetas/")
.then()
.log().body()
.and()
.statusCode(HttpStatus.INTERNAL_SERVER_ERROR.value())
.body("erro", equalTo("Erro interno"));
}
@Test
public void api_sw_falha_ao_salvar_planeta() {
mockServer = MockRestServiceServer.createServer(restTemplate);
mockServer.expect(requestTo(startsWith("https://swapi.co/")))
.andExpect(method(HttpMethod.GET))
.andRespond(
withUnauthorizedRequest()
);
Planeta terra2 = new Planeta("TerraNova");
given()
.request()
.header("Accept", ContentType.ANY)
.header("Content-type", ContentType.JSON)
.body(terra2)
.when()
.post("/planetas/")
.then()
.log().body()
.and()
.statusCode(HttpStatus.INTERNAL_SERVER_ERROR.value())
.body("erro", equalTo("Erro interno"));
}
}
<file_sep>/README.md
# API - Planetas de Star Wars
## Tecnologias Empregadas
1. MongoDB
2. Spring Boot
3. Rest Assured
4. Maven
## Testes unitários
* Baseados em JUnit.
* Local ``src/test/java``.
## Testes de integração
* Fazem uso de um banco de dados mongoDB que é carregado em memória automaticamente. Ao fim da execução dos testes o banco é automaticamente desativado e destruído.
* Fazem uso de um server que gera um *stub* para as requisições feitas para a API SW.
* Local ``src/it/java``.
## Aplicação
1. Instalar banco de dados mongo escutando na porta default (27017).
2. Executar a classe br.com.eraldoborel.starwarsplanets.StarWarsPlanetsApplication.
3. Em [http://localhost:8080](http://localhost:8080) temos uma página que descreve a assinatura da API. Esta página foi gerada automaticamente a partir do arquivo *api_planetas.yaml* na plataforma [swagger.io](http://swagger.io).
<file_sep>/src/it/java/br/com/eraldoborel/starwarsplanets/repository/PlanetaRepositoryTests.java
package br.com.eraldoborel.starwarsplanets.repository;
import static org.assertj.core.api.Assertions.assertThat;
import java.util.Optional;
import org.junit.Test;
import br.com.eraldoborel.starwarsplanets.model.Planeta;
public class PlanetaRepositoryTests extends br.com.eraldoborel.starwarsplanets.StarWarsPlanetsBaseIntegrationTests {
@Test (expected = Exception.class)
public void nao_salvar_planeta_com_nome_igual() {
Planeta planeta = new Planeta("Terra");
repository.save(planeta);
}
@Test
public void encontrar_planeta_pelo_nome() {
Optional<Planeta> optional = repository.findByNomeIgnoreCase("terra");
assertThat(optional.isPresent()).isTrue();
assertThat(optional.get().getNome()).isEqualTo("Terra");
}
@Test
public void nao_encontrar_planeta_pelo_nome() {
Optional<Planeta> optional = repository.findByNomeIgnoreCase("marte");
assertThat(optional.isPresent()).isFalse();
}
}
<file_sep>/src/main/resources/application.properties
spring.data.mongodb.uri=mongodb://localhost:27017/starwarsplanets
swapi.url=https://swapi.co/api/planets/<file_sep>/src/test/java/br/com/eraldoborel/starwarsplanets/service/AparicoesFilmesSWServiceTest.java
package br.com.eraldoborel.starwarsplanets.service;
import static org.assertj.core.api.Assertions.assertThat;
import static org.mockito.Mockito.verify;
import static org.mockito.Mockito.when;
import java.util.ArrayList;
import java.util.Arrays;
import org.junit.Before;
import org.junit.Test;
import org.junit.runner.RunWith;
import org.mockito.Mockito;
import org.springframework.beans.factory.annotation.Autowired;
import org.springframework.beans.factory.config.PropertyPlaceholderConfigurer;
import org.springframework.boot.test.mock.mockito.MockBean;
import org.springframework.context.annotation.Bean;
import org.springframework.context.annotation.Configuration;
import org.springframework.core.io.ClassPathResource;
import org.springframework.test.context.junit4.SpringJUnit4ClassRunner;
import org.springframework.web.client.ResourceAccessException;
import org.springframework.web.client.RestTemplate;
import br.com.eraldoborel.starwarsplanets.model.apisw.Planet;
import br.com.eraldoborel.starwarsplanets.model.apisw.Result;
import br.com.eraldoborel.starwarsplanets.service.exceptions.ApiSWIndisponivelException;
import br.com.eraldoborel.starwarsplanets.service.impl.AparicoesFilmesSWServiceImpl;
@RunWith(SpringJUnit4ClassRunner.class)
public class AparicoesFilmesSWServiceTest {
@Autowired
private AparicoesFilmesSWService aparicoesFilmesSWService;
@MockBean
private RestTemplate restTemplate;
private Result result;
private Planet tatooine;
@Configuration
static class someConfig {
@Bean
PropertyPlaceholderConfigurer propConfig() {
PropertyPlaceholderConfigurer ppc = new PropertyPlaceholderConfigurer();
ppc.setLocation(new ClassPathResource("application-test.properties"));
return ppc;
}
@Bean
AparicoesFilmesSWService serv( ) {
return new AparicoesFilmesSWServiceImpl();
}
}
@Before
public void setUp() throws Exception {
tatooine = new Planet();
tatooine.setName("Tatooine");
tatooine.setFilms(Arrays.asList(
"https://swapi.co/api/films/5/",
"https://swapi.co/api/films/4/",
"https://swapi.co/api/films/6/",
"https://swapi.co/api/films/3/",
"https://swapi.co/api/films/1/"
));
result = new Result();
result.setResults(Arrays.asList(tatooine));
when(restTemplate.getForObject(Mockito.anyString(), Mockito.any())).thenReturn(result);
}
@Test
public void obtem_quantidade_aparicoes_de_um_planeta() throws Exception {
int quantidade = aparicoesFilmesSWService.getNumeroAparicoes("tatooine");
assertThat(quantidade).isEqualTo(5);
verify(restTemplate).getForObject("https://swapi.co/api/planets/?search=tatooine", Result.class);
}
@Test
public void obtem_quantidade_aparicoes_de_um_planeta_quando_retorna_uma_lista() throws Exception {
Planet terra = new Planet();
terra.setName("Terra");
terra.setFilms(Arrays.asList("https://swapi.co/api/films/1/"));
result.setResults(Arrays.asList(terra , tatooine));
int quantidade = aparicoesFilmesSWService.getNumeroAparicoes("tatooine");
assertThat(quantidade).isEqualTo(5);
verify(restTemplate).getForObject("https://swapi.co/api/planets/?search=tatooine", Result.class);
}
@Test
public void obtem_quantidade_zero_de_aparicoes_caso_nao_exista_no_cadastro() throws Exception {
result.setResults(new ArrayList<Planet>());
when(restTemplate.getForObject(Mockito.anyString(), Mockito.any())).thenReturn(result);
int quantidade = aparicoesFilmesSWService.getNumeroAparicoes("tatooine2");
assertThat(quantidade).isEqualTo(0);
verify(restTemplate).getForObject("https://swapi.co/api/planets/?search=tatooine2", Result.class);
}
@Test(expected=ApiSWIndisponivelException.class)
public void dispara_erro_quando_api_esta_fora() throws Exception {
when(restTemplate.getForObject(Mockito.anyString(), Mockito.any())).thenThrow(new ResourceAccessException(null));
aparicoesFilmesSWService.getNumeroAparicoes("tatooine");
}
}
<file_sep>/src/main/java/br/com/eraldoborel/starwarsplanets/model/Planeta.java
package br.com.eraldoborel.starwarsplanets.model;
import org.springframework.data.annotation.Id;
import org.springframework.data.mongodb.core.index.Indexed;
import org.springframework.data.mongodb.core.mapping.Document;
@Document(collection = "planeta")
public class Planeta {
public Planeta() {
}
public Planeta(String nome) {
this.nome = nome;
}
@Id
private String id;
@Indexed(unique = true)
private String nome;
private String clima;
private String terreno;
private int quantidadeAparicoesFilmes = 0;
public String getId() {
return id;
}
public void setId(String id) {
this.id = id;
}
public String getNome() {
return nome;
}
public void setNome(String nome) {
this.nome = nome;
}
public String getClima() {
return clima;
}
public void setClima(String clima) {
this.clima = clima;
}
public String getTerreno() {
return terreno;
}
public void setTerreno(String terreno) {
this.terreno = terreno;
}
public int getQuantidadeAparicoesFilmes() {
return quantidadeAparicoesFilmes;
}
public void setQuantidadeAparicoesFilmes(int quantidadeAparicoesFilmes) {
this.quantidadeAparicoesFilmes = quantidadeAparicoesFilmes;
}
}
<file_sep>/src/main/java/br/com/eraldoborel/starwarsplanets/resource/PlanetaResource.java
package br.com.eraldoborel.starwarsplanets.resource;
import java.net.URI;
import java.util.List;
import javax.servlet.http.HttpServletResponse;
import org.springframework.beans.factory.annotation.Autowired;
import org.springframework.http.HttpStatus;
import org.springframework.http.ResponseEntity;
import org.springframework.web.bind.annotation.DeleteMapping;
import org.springframework.web.bind.annotation.ExceptionHandler;
import org.springframework.web.bind.annotation.PathVariable;
import org.springframework.web.bind.annotation.PostMapping;
import org.springframework.web.bind.annotation.PutMapping;
import org.springframework.web.bind.annotation.RequestBody;
import org.springframework.web.bind.annotation.RequestMapping;
import org.springframework.web.bind.annotation.RestController;
import org.springframework.web.servlet.support.ServletUriComponentsBuilder;
import br.com.eraldoborel.starwarsplanets.model.Planeta;
import br.com.eraldoborel.starwarsplanets.service.PlanetaService;
import br.com.eraldoborel.starwarsplanets.service.exceptions.ApiSWIndisponivelException;
import br.com.eraldoborel.starwarsplanets.service.exceptions.NomeDuplicadoException;
import br.com.eraldoborel.starwarsplanets.service.exceptions.PlanetaNaoEncontradoException;
@RestController
@RequestMapping("/planetas")
public class PlanetaResource {
@Autowired
private PlanetaService servico;
@RequestMapping
public ResponseEntity<List<Planeta>> listar() throws PlanetaNaoEncontradoException {
List<Planeta> planetas = servico.findAll();
return new ResponseEntity<List<Planeta>>(planetas, HttpStatus.OK);
}
@RequestMapping("/nome/{nome}/")
public ResponseEntity<Planeta> buscarPorNome(@PathVariable("nome") String nome) throws PlanetaNaoEncontradoException {
Planeta planeta = servico.buscar_por_nome(nome);
return new ResponseEntity<Planeta>(planeta, HttpStatus.OK);
}
@RequestMapping("/{id}/")
public ResponseEntity<Planeta> buscarPorId(@PathVariable("id") String id) throws PlanetaNaoEncontradoException {
Planeta planeta = servico.buscar_por_id(id);
return new ResponseEntity<Planeta>(planeta, HttpStatus.OK);
}
@PostMapping
public ResponseEntity<Planeta> criar(@RequestBody Planeta planeta, HttpServletResponse response) throws NomeDuplicadoException, ApiSWIndisponivelException {
Planeta planetaSalvo = servico.criar(planeta);
URI url = ServletUriComponentsBuilder
.fromCurrentRequestUri().path("/{id}/")
.buildAndExpand(planetaSalvo.getId()).toUri();
response.setHeader("Location", url.toASCIIString());
return new ResponseEntity<Planeta>(planetaSalvo, HttpStatus.CREATED);
}
@PutMapping("/")
public ResponseEntity<Planeta> atualizar(@RequestBody Planeta planeta, HttpServletResponse response) throws NomeDuplicadoException, PlanetaNaoEncontradoException, ApiSWIndisponivelException {
Planeta planetaSalvo = servico.atualizar(planeta);
URI url = ServletUriComponentsBuilder
.fromCurrentRequestUri().path("/{id}/")
.buildAndExpand(planetaSalvo.getId()).toUri();
response.setHeader("Location", url.toASCIIString());
return new ResponseEntity<Planeta>(planetaSalvo, HttpStatus.OK);
}
@DeleteMapping("/{id}/")
public ResponseEntity<Mensagem> remover(@PathVariable("id") String id) throws PlanetaNaoEncontradoException {
servico.apagar(id);
Mensagem mensagem = new Mensagem("Planeta com o id '" + id + "' foi removido com sucesso.");
return new ResponseEntity<Mensagem>(mensagem , HttpStatus.OK);
}
@ExceptionHandler({ApiSWIndisponivelException.class})
public ResponseEntity<Erro> handleApiSWIndisponivelException (ApiSWIndisponivelException e) {
Erro erro = new Erro(e.getMessage());
return new ResponseEntity<Erro>(erro , HttpStatus.INTERNAL_SERVER_ERROR);
}
@ExceptionHandler({NomeDuplicadoException.class})
public ResponseEntity<Erro> handleNomeDuplicadoException (NomeDuplicadoException e) {
Erro erro = new Erro(e.getMensagem());
return new ResponseEntity<Erro>(erro , HttpStatus.BAD_REQUEST);
}
@ExceptionHandler({PlanetaNaoEncontradoException.class})
public ResponseEntity<Erro> handlePlanetaNaoEncontrado (PlanetaNaoEncontradoException e) {
Erro erro = new Erro(e.getMensagem());
return new ResponseEntity<Erro>(erro , HttpStatus.NOT_FOUND);
}
class Erro {
private String erro;
public Erro(String erro) {
super();
this.erro = erro;
}
public String getErro() {
return erro;
}
public void setErro(String erro) {
this.erro = erro;
}
}
class Mensagem {
private final String mensagem;
public Mensagem(String mensagem) {
super();
this.mensagem = mensagem;
}
public String getMensagem() {
return mensagem;
}
}
}
<file_sep>/src/main/java/br/com/eraldoborel/starwarsplanets/service/impl/AparicoesFilmesSWServiceImpl.java
package br.com.eraldoborel.starwarsplanets.service.impl;
import org.apache.http.conn.ssl.NoopHostnameVerifier;
import org.apache.http.impl.client.CloseableHttpClient;
import org.apache.http.impl.client.HttpClients;
import org.springframework.beans.factory.annotation.Autowired;
import org.springframework.beans.factory.annotation.Value;
import org.springframework.context.annotation.Bean;
import org.springframework.http.client.HttpComponentsClientHttpRequestFactory;
import org.springframework.stereotype.Service;
import org.springframework.web.client.RestTemplate;
import br.com.eraldoborel.starwarsplanets.model.apisw.Planet;
import br.com.eraldoborel.starwarsplanets.model.apisw.Result;
import br.com.eraldoborel.starwarsplanets.service.AparicoesFilmesSWService;
import br.com.eraldoborel.starwarsplanets.service.exceptions.ApiSWIndisponivelException;
@Service
public class AparicoesFilmesSWServiceImpl implements AparicoesFilmesSWService {
@Autowired
private RestTemplate restTemplate;
@Value("${swapi.url}")
private String url;
@Override
public int getNumeroAparicoes(String nome) throws ApiSWIndisponivelException {
try{
Result result = restTemplate.getForObject(url + "?search=" + nome, Result.class);
for (Planet planet: result.getResults()) {
if (planet.getName().equalsIgnoreCase(nome)) {
return planet.getFilms().size();
}
}
return 0;
} catch (Exception e) {
throw new ApiSWIndisponivelException();
}
}
@Bean
private RestTemplate restTemplate() {
CloseableHttpClient httpClient = HttpClients.custom().setSSLHostnameVerifier(new NoopHostnameVerifier()).build();
HttpComponentsClientHttpRequestFactory useApacheHttpClient = new HttpComponentsClientHttpRequestFactory();
useApacheHttpClient.setHttpClient(httpClient);
return new RestTemplate(useApacheHttpClient);
}
}
<file_sep>/src/main/java/br/com/eraldoborel/starwarsplanets/model/apisw/Result.java
package br.com.eraldoborel.starwarsplanets.model.apisw;
import java.util.List;
import com.fasterxml.jackson.annotation.JsonIgnoreProperties;
@JsonIgnoreProperties(ignoreUnknown = true)
public class Result {
private List<Planet> results;
public Result(List<Planet> results) {
super();
this.results = results;
}
public Result() {
super();
}
public List<Planet> getResults() {
return results;
}
public void setResults(List<Planet> results) {
this.results = results;
}
} | 812a642ea9f22a067b54a9bcb7ec4354d91ca101 | [
"Markdown",
"Java",
"INI"
] | 12 | Java | Eraldo-Pessoal/star-wars-planets | b51d24444617fead6cd93132836f0cc6b46079c0 | e1fcc2fb5cd912fc48af30af2965563920fd8fca |
refs/heads/main | <repo_name>duytrinhvn/spx<file_sep>/Data/DbInitializer.cs
using Microsoft.AspNetCore.Identity;
using Microsoft.EntityFrameworkCore;
using Microsoft.Extensions.DependencyInjection;
using SPX.Data;
using SPX.Models;
using System;
using System.Collections.Generic;
using System.Linq;
using System.Threading.Tasks;
namespace Week2_IdentitySystem.Data
{
public static class DbInitializer
{
public static async Task<int> SeedUsersAndRoles(IServiceProvider serviceProvider)
{
// create the database if it doesn't exist
var context = serviceProvider.GetRequiredService<ApplicationDbContext>();
context.Database.Migrate();
var roleManager = serviceProvider.GetRequiredService<RoleManager<IdentityRole>>();
var userManager = serviceProvider.GetRequiredService<UserManager<ApplicationUser>>();
// Check if roles already exist and exit if there are
if (roleManager.Roles.Count() > 0)
return 1; // should log an error message here
// Seed roles
int result = await SeedRoles(roleManager);
if (result != 0)
return 2; // should log an error message here
// Check if users already exist and exit if there are
if (userManager.Users.Count() > 0)
return 3; // should log an error message here
// Seed users
result = await SeedUsers(userManager);
if (result != 0)
return 4; // should log an error message here
return 0;
}
public static async Task<int> SeedData(IServiceProvider serviceProvider)
{
// create the database if it doesn't exist
var context = serviceProvider.GetRequiredService<ApplicationDbContext>();
context.Database.Migrate();
// Seed Sport Categories
if (!context.SportCategories.Any())
{
var categories = new List<SportCategory> {
new SportCategory
{
Id = Guid.NewGuid(),
Name = "Soccer"
},
new SportCategory
{
Id = Guid.NewGuid(),
Name = "Basketball"
},
new SportCategory
{
Id = Guid.NewGuid(),
Name = "Cricket"
}
};
await context.SportCategories.AddRangeAsync(categories);
var result = await context.SaveChangesAsync();
}
// Seed Leagues
if (!context.Leagues.Any())
{
var leagues = new List<League> {
new League
{
Id = Guid.NewGuid(),
Name = "Bundesliga",
Description = "Bundesliga is a professional association football league in Germany. At the top of the German football league system, the Bundesliga is Germany's primary football competition."
},
new League
{
Id = Guid.NewGuid(),
Name = "<NAME>",
Description = "La Liga is the men's top professional football division of the Spanish football league system."
},
new League
{
Id = Guid.NewGuid(),
Name = "NBA",
Description = "The National Basketball Association is a professional basketball league in North America. The league is composed of 30 teams and is one of the four major professional sports leagues in the United States and Canada. It is the premier men's professional basketball league in the world."
},
};
await context.Leagues.AddRangeAsync(leagues);
await context.SaveChangesAsync();
}
// Seed Teams
if (!context.Teams.Any())
{
var laliga_league = (from league in context.Leagues
where league.Name == "La Liga"
select league).FirstOrDefault();
var bundesliga_league = (from league in context.Leagues
where league.Name == "Bundesliga"
select league).FirstOrDefault();
var soccer_sport = (from sport in context.SportCategories
where sport.Name == "Soccer"
select sport).FirstOrDefault();
var teams = new List<Team> {
new Team
{
Id = Guid.NewGuid(),
Name = "<NAME>",
Description = "Barcelona and colloquially known as Barça, is a Spanish professional football club based in Barcelona, that competes in La Liga, the top flight of Spanish football.",
League = laliga_league,
SportCategory = soccer_sport
},
new Team
{
Id = Guid.NewGuid(),
Name = "<NAME>",
Description = "<NAME>unich is a German professional sports club based in Munich, Bavaria. It is best known for its professional football team, which plays in the Bundesliga, the top tier of the German football league system.",
League = bundesliga_league,
SportCategory = soccer_sport
},
new Team
{
Id = Guid.NewGuid(),
Name = "<NAME>",
Description = "<NAME>, BVB, or simply Dortmund, is a German professional sports club based in Dortmund, North Rhine-Westphalia.",
League = bundesliga_league,
SportCategory = soccer_sport
},
};
await context.Teams.AddRangeAsync(teams);
await context.SaveChangesAsync();
}
if (!context.Buckets.Any())
{
var buckets = new List<Bucket>
{
new Bucket
{
Id = Guid.NewGuid(),
Name = "Top 3 Soccer Teams",
Description = "The 3 best performers in the Soccer sport",
Price = 2000
}
};
await context.Buckets.AddRangeAsync(buckets);
await context.SaveChangesAsync();
}
if (!context.BucketTeamConnections.Any())
{
var soccer_bucket = (from bucket in context.Buckets
where bucket.Name == "Top 3 Soccer Teams"
select bucket).FirstOrDefault();
var barca_team = (from team in context.Teams
where team.Name == "FC Barcelona"
select team).FirstOrDefault();
var dortmund_team = (from team in context.Teams
where team.Name == "<NAME>"
select team).FirstOrDefault();
var bayern_team = (from team in context.Teams
where team.Name == "FC Bayern Munich"
select team).FirstOrDefault();
var bucketTeamConnections = new List<BucketTeamConnection>
{
new BucketTeamConnection
{
Id = Guid.NewGuid(),
Bucket = soccer_bucket,
Team = barca_team
},
new BucketTeamConnection
{
Id = Guid.NewGuid(),
Bucket = soccer_bucket,
Team = dortmund_team
},
new BucketTeamConnection
{
Id = Guid.NewGuid(),
Bucket = soccer_bucket,
Team = bayern_team
},
};
await context.BucketTeamConnections.AddRangeAsync(bucketTeamConnections);
var result = await context.SaveChangesAsync();
}
return 0;
}
private static async Task<int> SeedRoles(RoleManager<IdentityRole> roleManager)
{
// Create Admin Role
var result = await roleManager.CreateAsync(new IdentityRole("Admin"));
if (!result.Succeeded)
return 1; // should log an error message here
// Create Member Role
result = await roleManager.CreateAsync(new IdentityRole("Investor"));
if (!result.Succeeded)
return 2; // should log an error message here
return 0;
}
private static async Task<int> SeedUsers(UserManager<ApplicationUser> userManager)
{
// Create Admin User
var adminUser = new ApplicationUser
{
UserName = "<EMAIL>",
Email = "<EMAIL>",
FirstName = "The",
LastName = "Admin",
EmailConfirmed = true
};
var result = await userManager.CreateAsync(adminUser, "<PASSWORD>");
if (!result.Succeeded)
return 1; // should log an error message here
// Assign user to Admin role
result = await userManager.AddToRoleAsync(adminUser, "Admin");
if (!result.Succeeded)
return 2; // should log an error message here
// Create Member User
var memberUser = new ApplicationUser
{
UserName = "<EMAIL>",
Email = "<EMAIL>",
FirstName = "The",
LastName = "Investor",
EmailConfirmed = true
};
result = await userManager.CreateAsync(memberUser, "<PASSWORD>");
if (!result.Succeeded)
return 3; // should log an error message here
// Assign user to Member role
result = await userManager.AddToRoleAsync(memberUser, "Investor");
if (!result.Succeeded)
return 4; // should log an error message here
return 0;
}
}
}
<file_sep>/ViewModels/InvestmentsListViewModel.cs
using SPX.Models;
using System;
using System.Collections.Generic;
using System.Linq;
using System.Threading.Tasks;
namespace SPX.ViewModels
{
public class InvestmentsListViewModel
{
public IEnumerable<Interest> Interests { get; set; }
public IEnumerable<Bucket> Buckets { get; set; }
}
}
<file_sep>/Areas/Identity/IdentityHostingStartup.cs
using System;
using Microsoft.AspNetCore.Hosting;
using Microsoft.AspNetCore.Identity;
using Microsoft.AspNetCore.Identity.UI;
using Microsoft.EntityFrameworkCore;
using Microsoft.Extensions.Configuration;
using Microsoft.Extensions.DependencyInjection;
using SPX.Data;
using SPX.Models;
[assembly: HostingStartup(typeof(SPX.Areas.Identity.IdentityHostingStartup))]
namespace SPX.Areas.Identity
{
public class IdentityHostingStartup : IHostingStartup
{
public void Configure(IWebHostBuilder builder)
{
builder.ConfigureServices((context, services) => {
});
}
}
}<file_sep>/README.md
## Current State
- Buckets page (Admin): Create/Read/Update/Delete buckets
- Teams page (Admin): Create/Read/Update/Delete teams
- Invest page (Investor): See all the available buckets that match their favorite sport teams
- Login/Logout:
- Authentication: User can register for an Investor account using the User Interface. The Admin account have to be created by adding codes to Data/DbInitializer.cs file.
- Authorization: Filters the content users can see based on their roles
- The Buckets page and Teams page can only be available when user logins as an Admin
- The Invest page can only be available when user logins as an Investors
- Default Roles and Users seeded:
- There are two roles, "Admin" and "Investor".
- Default User accounts for testing:
- <EMAIL> - <PASSWORD>
- <EMAIL> - <PASSWORD>
## Next State
- Investing activities: Investors will be able to start trading shares after they accept the available buckets in the Invest page.
| f5ce0f2cfdccf8cae4c039247965ab317b4771ad | [
"Markdown",
"C#"
] | 4 | C# | duytrinhvn/spx | c3ac58bd04fa5c9410d3f8555011d6d86a9f71d1 | 4f572db55363d24b4314f74a18fe3edcbc6b3438 |
refs/heads/master | <file_sep>puts "EventManager Initialized!"
lines = File.readlines "event_attendees.csv"
lines.each do |line|
columns = line.split(",")
name = columns[2]
puts name
end
| ba469ecd2c7edf9f9d51573c4e6ccdde8ed9ecdf | [
"Ruby"
] | 1 | Ruby | Em01/event_manager | 0b31a6e80f4d40b556a9e895226001cc9bf8fe1c | badc74b749d1e917b23f4372b7bd328f78ea633d |
refs/heads/master | <file_sep>#OneGraph
Codifying an entire system in a single structure, with each level of granularity a single zoom away.<file_sep>"use strict"
var helpers = {
title: function(options) {
let viewName = options.data.exphbs.view;
let capitalisedViewName = viewName[0].toUpperCase() + viewName.slice(1);
return 'OneGraph - ' + capitalisedViewName;
}
};
module.exports = helpers;<file_sep>"use strict";
const express = require('express');
const exphbs = require('express-handlebars');
const helpers = require('./helpers.js');
const app = express();
const hbs = exphbs.create({
defaultLayout: 'main',
helpers: helpers
});
app.engine('handlebars', hbs.engine);
app.set('view engine', 'handlebars');
app.use('/static', express.static(__dirname + '/public'));
app.get('/', function(req, res) {
res.render('dashboard');
});
const port = Number(process.env.PORT || 5000);
app.listen(port); | c4f3875c6bb962e84efb4d9abfd898771b5a868d | [
"Markdown",
"JavaScript"
] | 3 | Markdown | JonNorman/OneGraph | 18217199ce4458427aaeaa85f274a671b453d0a9 | 0f58d60e631206bf29608f15bbd8235364fe87f6 |
refs/heads/master | <repo_name>SoftwareDesign2017/assignment-1-stefaniasucitu<file_sep>/BankDesk/src/main/java/service/client/ClientServiceImpl.java
package service.client;
import model.Account;
import model.Client;
import model.builder.ClientBuilder;
import model.validation.ClientValidator;
import model.validation.Notification;
import repository.EntityNotFoundException;
import repository.account.AccountRepository;
import repository.accountsManagement.ClientAccountRepository;
import repository.client.ClientRepository;
import java.util.Collections;
import java.util.List;
public class ClientServiceImpl implements ClientService {
private final ClientRepository repository;
private final ClientAccountRepository clientAccountRepository;
private final AccountRepository accountRepository;
public ClientServiceImpl(ClientRepository repository, ClientAccountRepository clientAccountRepository, AccountRepository accountRepository) {
this.repository = repository;
this.clientAccountRepository = clientAccountRepository;
this.accountRepository = accountRepository;
}
@Override
public List<Client> findAll() {
return repository.findAll();
}
@Override
public Notification<Client> findById(Long id) throws EntityNotFoundException {
return repository.findById(id);
}
@Override
public Notification<Boolean> addNewClient(Long id, String first, String last, String CNP, String card, String address) {
Client client = new ClientBuilder()
.setFirstName(first)
.setLastName(last)
.setCNP(CNP)
.setIdCard(card)
.setAddress(address)
.build();
ClientValidator clientValidator = new ClientValidator(client);
boolean clientValid = clientValidator.validate();
//List<Account> accounts = clientAccountRepository.findAccountsforClient(client.getId());
//client.setAccounts(accounts);
Notification<Boolean> saveClientNotification = new Notification<>();
if (!clientValid) {
clientValidator.getErrors().forEach(saveClientNotification::addError);
saveClientNotification.setResult(Boolean.FALSE);
return saveClientNotification;
} else {
saveClientNotification.setResult(repository.save(client));
return saveClientNotification;
}
}
@Override
public Notification<Boolean> updateClient(Long id, String first, String last, String CNP, String card, String address) {
Client client = new ClientBuilder()
.setFirstName(first)
.setLastName(last)
.setCNP(CNP)
.setIdCard(card)
.setAddress(address)
.build();
ClientValidator clientValidator = new ClientValidator(client);
boolean clientValid = clientValidator.validate();
Notification<Boolean> updateClientNotification = new Notification<>();
client.setId(id);
if (!clientValid) {
clientValidator.getErrors().forEach(updateClientNotification::addError);
updateClientNotification.setResult(Boolean.FALSE);
return updateClientNotification;
} else {
updateClientNotification.setResult(repository.update(client));
return updateClientNotification;
}
}
@Override
public Notification<Boolean> deleteClient(Long id, String first, String last, String CNP, String card, String address) {
Client client = new ClientBuilder()
.setFirstName(first)
.setLastName(last)
.setCNP(CNP)
.setIdCard(card)
.setAddress(address)
.build();
Notification<Boolean> deleteClientNotification = new Notification<>();
client.setId(id);
deleteClientNotification.setResult(repository.removeById(client));
return deleteClientNotification;
}
@Override
public Notification<Client> findByName(String first, String last) {// throws EntityNotFoundException {
return repository.findByName(first, last);
}
@Override
public Notification<Boolean> addAccountForClient(Long idClient, Long idAccount) {
Client client = repository.findById(idClient).getResult();
Account account = accountRepository.findById(idAccount).getResult();
Notification<Boolean> addAccountForClientNotification = new Notification<>();
addAccountForClientNotification.setResult(clientAccountRepository.addAccountToClient(client, Collections.singletonList(account)));
return addAccountForClientNotification;
}
}
<file_sep>/BankDesk/src/test/java/repository/ClientAccountRepositoryTest.java
package repository;
import database.DBConnectionFactory;
import model.Account;
import model.Client;
import model.builder.AccountBuilder;
import model.builder.ClientBuilder;
import org.joda.time.DateTime;
import org.junit.Assert;
import org.junit.Before;
import org.junit.Test;
import repository.account.AccountRepository;
import repository.account.AccountRepositoryMySql;
import repository.accountsManagement.ClientAccountRepository;
import repository.accountsManagement.ClientAccountRepositoryMySql;
import repository.client.ClientRepository;
import repository.client.ClientRepositoryMySql;
import java.sql.Connection;
import java.util.Collections;
import java.util.List;
/**
* Created by Stefi on 03-Apr-17.
*/
public class ClientAccountRepositoryTest {
private static ClientRepository clientRepository;
private static ClientAccountRepository clientAccountRepository;
private static AccountRepository accountRepository;
@Before
public void setUp() throws Exception {
Connection connection = new DBConnectionFactory().getConnectionWrapper(true).getConnection();
clientRepository = new ClientRepositoryMySql(connection, clientAccountRepository);
accountRepository = new AccountRepositoryMySql(connection);
clientAccountRepository = new ClientAccountRepositoryMySql(connection, accountRepository);
}
@Test
public void addAccountToClient() throws Exception {
String firstName = "Preume";
String lastName = "Nume";
String CNP = "2950726314003";
String Card = "1234569874";
String address = "addrblabla";
Client clientTest = new ClientBuilder()
.setFirstName(firstName)
.setLastName(lastName)
.setCNP(CNP)
.setAddress(address)
.setIdCard(Card)
.build();
clientRepository.save(clientTest);
String type = "saving";
DateTime date = new DateTime();
Account account = new AccountBuilder()
.setDateOfCreation(date)
.setMoney(0)
.setType(type)
.build();
accountRepository.save(account);
Assert.assertTrue(clientAccountRepository.addAccountToClient(clientTest, Collections.singletonList(account)));
}
@Test
public void removeAccountForClient() throws Exception {
String type = "saving";
DateTime date = new DateTime();
Account account = new AccountBuilder()
.setDateOfCreation(date)
.setMoney(0)
.setType(type)
.build();
accountRepository.save(account);
Assert.assertTrue(clientAccountRepository.removeAccountForClient(account));
}
@Test
public void findAccountsForClient() throws Exception {
String firstName = "Preume";
String lastName = "Nume";
String CNP = "2950726314003";
String Card = "1234569874";
String address = "addrblabla";
Client clientTest = new ClientBuilder()
.setFirstName(firstName)
.setLastName(lastName)
.setCNP(CNP)
.setAddress(address)
.setIdCard(Card)
.build();
clientRepository.save(clientTest);
List<Account> accounts = clientAccountRepository.findAccountsforClient(clientTest.getId());
Assert.assertNotNull(accounts);
}
}
<file_sep>/BankDesk/src/main/java/controller/UserViewController.java
package controller;
import model.Account;
import model.Client;
import model.User;
import model.validation.Notification;
import org.joda.time.DateTime;
import service.account.AccountService;
import service.client.ClientService;
import service.user.UserService;
import view.UserView;
import javax.swing.*;
import javax.swing.table.DefaultTableModel;
import java.awt.event.ActionEvent;
import java.awt.event.ActionListener;
import java.util.List;
public class UserViewController {
private final UserView userView;
private final AccountService accountService;
private final ClientService clientService;
private final Long currentUserID;
private final UserService userService;
public UserViewController(UserView userView, AccountService accountService, ClientService clientService,UserService userService,Long currentUserID) {
this.userView = userView;
this.accountService = accountService;
this.clientService = clientService;
this.userService=userService;
this.currentUserID=currentUserID;
userView.setAddNewAccountButtonListener(new AddNewAccountButtonListener());
userView.setAddNewClientButtonListener(new AddNewClientButtonListener());
userView.setUpdateAccountButtonListener(new UpdateAccountButtonListener());
userView.setUpdateClientButtonListener(new UpdateClientButtonListener());
userView.setDeleteAccountButtonListener(new DeleteAccountButtonListener());
userView.setViewClientButtonListener(new ViewClientButtonListener());
userView.setViewAllClientsButtonListener(new ViewAllClientsButtonLister());
userView.setTransferButtonListener(new TransferButtonLister());
userView.setViewAccountButtonListener(new ViewAccountButtonLister());
}
private class AddNewAccountButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
String firstNameClient = userView.getFirstName();
String lastNameClient = userView.getLastName();
String type = userView.getAccountType();
DateTime date = new org.joda.time.DateTime();
Client client;
Notification<Account> addNewAccountNotification = accountService.addNewAccount(type, date);
Account addedAccount = addNewAccountNotification.getResult();
client = clientService.findByName(firstNameClient, lastNameClient).getResult();
Notification<Boolean> addAccountForClientNotification = clientService.addAccountForClient(client.getId(), addedAccount.getId());
if (addNewAccountNotification.hasErrors()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
addNewAccountNotification.getFormattedErrors());
} else {
if (!addAccountForClientNotification.getResult()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
"Add operation not successful, please try again later.");
} else {
JOptionPane.showMessageDialog(userView.getContentPane(), "new account added successful!");
userService.addOperation(currentUserID,"added new account");
}
}
}
}
private class AddNewClientButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
String firstNameClient = userView.getFirstName();
String lastNameClient = userView.getLastName();
String CNP = userView.getCNP();
String card = userView.getCard();
String address = userView.getAddress();
Notification<Boolean> addClientNotification = clientService.addNewClient(null, firstNameClient, lastNameClient,
CNP, card, address);
if (addClientNotification.hasErrors()) {
JOptionPane.showMessageDialog(userView.getContentPane(), addClientNotification.getFormattedErrors());
} else {
if (!addClientNotification.getResult()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
"Client add not successful, please try again later.");
} else {
JOptionPane.showMessageDialog(userView.getContentPane(), "Client added successful!");
userService.addOperation(currentUserID,"added new client");
}
}
}
}
private class UpdateAccountButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
Long idAccount = Long.parseLong(userView.getAccounId());
Float money = Float.parseFloat(userView.getSum());
String operation = userView.getOperation();
Notification<Boolean> updateAccountNotification = accountService.updateAccount(idAccount, money, operation);
if (updateAccountNotification.hasErrors()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
updateAccountNotification.getFormattedErrors());
} else {
if (!updateAccountNotification.getResult()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
"Update not successful, please try again later.");
} else {
JOptionPane.showMessageDialog(userView.getContentPane(), "Update successful!");
userService.addOperation(currentUserID,"updated account");
}
}
}
}
private class DeleteAccountButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
Long idAccount = Long.parseLong(userView.getAccounId());
Notification<Boolean> deleteAccountNotification = accountService.removeAccount(idAccount);
if (deleteAccountNotification.hasErrors()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
deleteAccountNotification.getFormattedErrors());
} else {
if (!deleteAccountNotification.getResult()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
"Delete not successful, please try again later.");
} else {
JOptionPane.showMessageDialog(userView.getContentPane(), "Delete successful!");
userService.addOperation(currentUserID,"delete account");
}
}
}
}
private class UpdateClientButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
String firstNameClient = userView.getFirstName();
String lastNameClient = userView.getLastName();
String card = userView.getCard();
String cnp = userView.getCNP();
String address = userView.getAddress();
Notification<Boolean> updateClientNotification = clientService.updateClient(null, firstNameClient, lastNameClient,
cnp, card, address);
if (updateClientNotification.hasErrors()) {
JOptionPane.showMessageDialog(userView.getContentPane(), updateClientNotification.getFormattedErrors());
} else {
if (!updateClientNotification.getResult()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
"Update not successful, please try again later.");
} else {
JOptionPane.showMessageDialog(userView.getContentPane(), "Update successful!");
userService.addOperation(currentUserID,"updated client");
}
}
}
}
private class ViewClientButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
String firstNameClient = userView.getFirstName();
String lastNameClient = userView.getLastName();
Client client = clientService.findByName(firstNameClient, lastNameClient).getResult();
Notification<Client> findClientNotification;
findClientNotification = clientService.findByName(firstNameClient, lastNameClient);
if (findClientNotification.hasErrors()) {
JOptionPane.showMessageDialog(userView.getContentPane(), findClientNotification.getFormattedErrors());
} else {
if (findClientNotification.getResult() != null)
JOptionPane.showMessageDialog(userView.getContentPane(),
"Client not found, please try again later.");
else {
String[] columnNames={"id","first name","last name", "CNP","idCard","address"};
DefaultTableModel tableModel = new DefaultTableModel( columnNames, 0);
JTable table=new JTable(tableModel);
Object[] data={client.getId(),client.getFirstName(),client.getLastName(),client.getCNP(),client.getIdCard(),client.getAddress()};
tableModel.addRow(data);
JOptionPane.showMessageDialog(null,new JScrollPane(table));
userService.addOperation(currentUserID,"view client");
}
}
}
}
private class ViewAllClientsButtonLister implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
List<Client> allClients = clientService.findAll();
String[] columnNames={"id","first name","last name", "CNP","idCard","address"};
DefaultTableModel tableModel = new DefaultTableModel( columnNames, 0);
JTable table=new JTable(tableModel);
for (Client client: allClients
) {
Object[] data={client.getId(),client.getFirstName(),client.getLastName(),client.getCNP(),client.getIdCard(),client.getAddress()};
tableModel.addRow(data);
}
JOptionPane.showMessageDialog(null,new JScrollPane(table));
userService.addOperation(currentUserID,"displayed all clients");
}
}
private class TransferButtonLister implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
Long fromId = Long.parseLong(userView.getFromAccount());
Long toId = Long.parseLong(userView.getToAccount());
Float sum = Float.parseFloat(userView.getSum());
Notification<Boolean> transferMoneyNotification = accountService.transferMoney(fromId, toId, sum);
if (transferMoneyNotification.hasErrors()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
transferMoneyNotification.getFormattedErrors());
} else {
if (!transferMoneyNotification.getResult()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
"Transfer not successful, please try again later.");
} else {
JOptionPane.showMessageDialog(userView.getContentPane(), "Transfer successful!");
userService.addOperation(currentUserID,"transfer money");
}
}
}
}
private class ViewAccountButtonLister implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
Long accountId = Long.parseLong(userView.getAccounId());
Notification<Account> accountFoundNotification = accountService.findById(accountId);
if (accountFoundNotification.hasErrors()) {
JOptionPane.showMessageDialog(userView.getContentPane(),
accountFoundNotification.getFormattedErrors());
} else {
if (accountFoundNotification.getResult() == null) {
JOptionPane.showMessageDialog(userView.getContentPane(),
"Account not found.");
} else {
JOptionPane.showMessageDialog(userView.getContentPane(), "Account successful!");
Account account=accountFoundNotification.getResult();
String[] columnNames={"id","type","money","date"};
DefaultTableModel tableModel = new DefaultTableModel( columnNames, 0);
JTable table=new JTable(tableModel);
Object[] data={account.getId(),account.getType(),account.getMoney(),account.getDateOfCreation()};
tableModel.addRow(data);
JOptionPane.showMessageDialog(null,new JScrollPane(table));
userService.addOperation(currentUserID,"view account");
}
}
}
}
}
<file_sep>/BankDesk/build.gradle
/*
* This build file was auto generated by running the Gradle 'init' task
* by 'Stefi' at '3/26/17 4:00 PM' with Gradle 3.0
*
* This generated file contains a sample Java project to get you started.
* For more details take a look at the Java Quickstart chapter in the Gradle
* user guide available at https://docs.gradle.org/3.0/userguide/tutorial_java_projects.html
*/
apply plugin: 'java'
apply plugin: 'eclipse'
apply plugin: 'application'
mainClassName = 'Launcher'
sourceCompatibility =1.8
targetCompatibility =1.8
repositories {
mavenCentral()
}
jar {
baseName = 'gs-gradle'
version = '0.1.0'
}
dependencies {
testCompile group: 'junit', name: 'junit', version: '4.11'
compile group: 'joda-time', name: 'joda-time', version: '2.3'
compile group: 'mysql', name: 'mysql-connector-java', version: '5.1.6'
compile group: 'org.apache.commons', name: 'commons-lang3', version: '3.1'
compile 'junit:junit:4.12'
}
<file_sep>/BankDesk/src/main/java/view/WelcomeLoginView.java
package view;
import javax.swing.*;
import java.awt.*;
import java.awt.event.ActionListener;
public class WelcomeLoginView extends JFrame {
private static final long serialVersionUID = 1L;
public JFrame frame;
private JTextField usernameField;
private JPasswordField passwordField;
private JButton btnLogin;
public WelcomeLoginView() {
initialize();
}
/**
* Launch the application.
*/
public void display() {
EventQueue.invokeLater(new Runnable() {
@Override
public void run() {
try {
WelcomeLoginView window = new WelcomeLoginView();
window.frame.setVisible(true);
} catch (Exception e) {
e.printStackTrace();
}
}
});
}
private void initialize() {
frame = new JFrame();
frame.setBounds(100, 100, 450, 300);
frame.setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE);
GridBagLayout gridBagLayout = new GridBagLayout();
gridBagLayout.columnWidths = new int[]{0, 0, 0, 0, 0, 0, 0, 0};
gridBagLayout.rowHeights = new int[]{0, 0, 0, 0, 0, 0, 0, 0};
gridBagLayout.columnWeights = new double[]{0.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, Double.MIN_VALUE};
gridBagLayout.rowWeights = new double[]{0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, Double.MIN_VALUE};
frame.getContentPane().setLayout(gridBagLayout);
JLabel lblWelcome = new JLabel("Welcome!");
GridBagConstraints gbc_lblWelcome = new GridBagConstraints();
gbc_lblWelcome.insets = new Insets(0, 0, 5, 5);
gbc_lblWelcome.gridx = 4;
gbc_lblWelcome.gridy = 1;
frame.getContentPane().add(lblWelcome, gbc_lblWelcome);
JLabel lblUsername = new JLabel("Username");
GridBagConstraints gbc_lblUsername = new GridBagConstraints();
gbc_lblUsername.anchor = GridBagConstraints.EAST;
gbc_lblUsername.insets = new Insets(0, 0, 5, 5);
gbc_lblUsername.gridx = 3;
gbc_lblUsername.gridy = 3;
frame.getContentPane().add(lblUsername, gbc_lblUsername);
usernameField = new JTextField();
GridBagConstraints gbc_textField = new GridBagConstraints();
gbc_textField.insets = new Insets(0, 0, 5, 5);
gbc_textField.fill = GridBagConstraints.HORIZONTAL;
gbc_textField.gridx = 4;
gbc_textField.gridy = 3;
frame.getContentPane().add(usernameField, gbc_textField);
usernameField.setColumns(10);
JLabel lblPassword = new JLabel("<PASSWORD>");
GridBagConstraints gbc_lblPassword = new GridBagConstraints();
gbc_lblPassword.anchor = GridBagConstraints.EAST;
gbc_lblPassword.insets = new Insets(0, 0, 5, 5);
gbc_lblPassword.gridx = 3;
gbc_lblPassword.gridy = 4;
frame.getContentPane().add(lblPassword, gbc_lblPassword);
passwordField = new JPasswordField();
GridBagConstraints gbc_passwordField = new GridBagConstraints();
gbc_passwordField.insets = new Insets(0, 0, 5, 5);
gbc_passwordField.fill = GridBagConstraints.HORIZONTAL;
gbc_passwordField.gridx = 4;
gbc_passwordField.gridy = 4;
frame.getContentPane().add(passwordField, gbc_passwordField);
btnLogin = new JButton("Login");
GridBagConstraints gbc_btnLogin = new GridBagConstraints();
gbc_btnLogin.insets = new Insets(0, 0, 0, 5);
gbc_btnLogin.gridx = 4;
gbc_btnLogin.gridy = 6;
frame.getContentPane().add(btnLogin, gbc_btnLogin);
frame.setDefaultCloseOperation(WindowConstants.EXIT_ON_CLOSE);
frame.setVisible(true);
}
public String getUsername() {
return usernameField.getText();
}
public String getPassword() {
return passwordField.getText();
}
public void setLoginButtonListener(ActionListener LoginButtonListener) {
btnLogin.addActionListener(LoginButtonListener);
}
}
<file_sep>/BankDesk/src/main/java/repository/accountsManagement/ClientAccountRepositoryMySql.java
package repository.accountsManagement;
import model.Account;
import model.Client;
import repository.account.AccountRepository;
import java.sql.*;
import java.util.ArrayList;
import java.util.List;
public class ClientAccountRepositoryMySql implements ClientAccountRepository {
private final Connection connection;
private final AccountRepository accountRepository;
public ClientAccountRepositoryMySql(Connection connection, AccountRepository accountRepository) {
this.connection = connection;
this.accountRepository = accountRepository;
}
@Override
public boolean addAccountToClient(Client client, List<Account> accounts) {
try {
for (Account account : accounts) {
PreparedStatement insertClientAccount = connection.prepareStatement(
"INSERT INTO `bank`.`client_account` VALUES (null, ?, ?);");
insertClientAccount.setLong(1, client.getId());
insertClientAccount.setLong(2, account.getId());
insertClientAccount.executeUpdate();
return true;
}
} catch (SQLException e) {
e.printStackTrace();
}
return false;
}
@Override
public boolean removeAccountForClient(Account account) {
try {
PreparedStatement deleteClientAccount = connection.prepareStatement("DELETE FROM `bank`.`client_account` where idaccount=?;");
deleteClientAccount.setLong(1, account.getId());
deleteClientAccount.executeUpdate();
return true;
} catch (SQLException e) {
e.printStackTrace();
}
return false;
}
@Override
public List<Account> findAccountsforClient(Long clientID) {
try {
List<Account> accounts = new ArrayList<>();
Statement statement = connection.createStatement();
String getAccounts = "Select * from`bank`.`client_account` where idclient=" + clientID;
ResultSet result = statement.executeQuery(getAccounts);
while (result.next()) {
long accountId = result.getLong("idaccount");
accounts.add(accountRepository.findById(accountId).getResult());
}
return accounts;
} catch (SQLException e) {
e.printStackTrace();
}
return null;
}
}
<file_sep>/BankDesk/src/main/java/service/account/AccountService.java
package service.account;
import model.Account;
import model.validation.Notification;
import org.joda.time.DateTime;
import java.util.List;
public interface AccountService {
List<Account> findAll();
Notification<Account> findById(Long id);
Notification<Account> addNewAccount(String type, DateTime date);
Notification<Boolean> transferMoney(Long formID, Long toID, Float sum);
Notification<Boolean> updateAccount(Long ID, Float sum, String operation);
Notification<Boolean> removeAccount(Long id);
void removeAll();
}
<file_sep>/BankDesk/src/main/java/view/AdminView.java
package view;
import javax.swing.*;
import java.awt.*;
import java.awt.event.ActionListener;
public class AdminView {
public JFrame frame;
private JTextField tfusername;
private JTextField tfpassword;
private JButton btnAddEmployee;
private JButton btnUpdateEmployee;
private JButton btnViewEmployee;
private JButton btnDeleteEmployee;
private JButton btnViewAllEmployees;
private JButton btnGenerateReport;
public AdminView() {
initialize();
}
/**
* Launch the application.
*/
public void display() {
EventQueue.invokeLater(new Runnable() {
@Override
public void run() {
try {
AdminView window = new AdminView();
window.frame.setVisible(true);
} catch (Exception e) {
e.printStackTrace();
}
}
});
}
private void initialize() {
frame = new JFrame();
frame.setBounds(100, 100, 644, 398);
frame.setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE);
GridBagLayout gridBagLayout = new GridBagLayout();
gridBagLayout.columnWidths = new int[]{82, 125, 0, 0, 0, 0, 0, 0};
gridBagLayout.rowHeights = new int[]{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
gridBagLayout.columnWeights = new double[]{0.0, 1.0, 1.0, 0.0, 0.0, 0.0, 0.0, Double.MIN_VALUE};
gridBagLayout.rowWeights = new double[]{0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, Double.MIN_VALUE};
frame.getContentPane().setLayout(gridBagLayout);
JLabel lblWelcome = new JLabel("Welcome Mr. Admin!");
GridBagConstraints gbc_lblWelcome = new GridBagConstraints();
gbc_lblWelcome.gridwidth = 3;
gbc_lblWelcome.insets = new Insets(0, 0, 5, 5);
gbc_lblWelcome.gridx = 2;
gbc_lblWelcome.gridy = 1;
frame.getContentPane().add(lblWelcome, gbc_lblWelcome);
JLabel lblOperations = new JLabel("Operations");
GridBagConstraints gbc_lblOperations = new GridBagConstraints();
gbc_lblOperations.insets = new Insets(0, 0, 5, 5);
gbc_lblOperations.gridx = 2;
gbc_lblOperations.gridy = 3;
frame.getContentPane().add(lblOperations, gbc_lblOperations);
JLabel lblNewLabel = new JLabel("Employee Info");
GridBagConstraints gbc_lblNewLabel = new GridBagConstraints();
gbc_lblNewLabel.insets = new Insets(0, 0, 5, 5);
gbc_lblNewLabel.gridx = 1;
gbc_lblNewLabel.gridy = 4;
frame.getContentPane().add(lblNewLabel, gbc_lblNewLabel);
JLabel lblName = new JLabel("Name");
GridBagConstraints gbc_lblName = new GridBagConstraints();
gbc_lblName.anchor = GridBagConstraints.EAST;
gbc_lblName.insets = new Insets(0, 0, 5, 5);
gbc_lblName.gridx = 1;
gbc_lblName.gridy = 5;
frame.getContentPane().add(lblName, gbc_lblName);
tfusername = new JTextField();
GridBagConstraints gbc_textField = new GridBagConstraints();
gbc_textField.gridwidth = 2;
gbc_textField.insets = new Insets(0, 0, 5, 5);
gbc_textField.fill = GridBagConstraints.HORIZONTAL;
gbc_textField.gridx = 2;
gbc_textField.gridy = 5;
frame.getContentPane().add(tfusername, gbc_textField);
tfusername.setColumns(10);
btnAddEmployee = new JButton("Add Employee");
GridBagConstraints gbc_btnAddEmployee = new GridBagConstraints();
gbc_btnAddEmployee.insets = new Insets(0, 0, 5, 5);
gbc_btnAddEmployee.gridx = 5;
gbc_btnAddEmployee.gridy = 5;
frame.getContentPane().add(btnAddEmployee, gbc_btnAddEmployee);
JLabel lblPassword = new JLabel("<PASSWORD>");
GridBagConstraints gbc_lblPassword = new GridBagConstraints();
gbc_lblPassword.anchor = GridBagConstraints.EAST;
gbc_lblPassword.insets = new Insets(0, 0, 5, 5);
gbc_lblPassword.gridx = 1;
gbc_lblPassword.gridy = 6;
frame.getContentPane().add(lblPassword, gbc_lblPassword);
tfpassword = new JTextField();
GridBagConstraints gbc_textField_1 = new GridBagConstraints();
gbc_textField_1.gridwidth = 2;
gbc_textField_1.insets = new Insets(0, 0, 5, 5);
gbc_textField_1.fill = GridBagConstraints.HORIZONTAL;
gbc_textField_1.gridx = 2;
gbc_textField_1.gridy = 6;
frame.getContentPane().add(tfpassword, gbc_textField_1);
tfpassword.setColumns(10);
btnUpdateEmployee = new JButton("Update Employee");
GridBagConstraints gbc_btnUpdateEmployee = new GridBagConstraints();
gbc_btnUpdateEmployee.insets = new Insets(0, 0, 5, 5);
gbc_btnUpdateEmployee.gridx = 5;
gbc_btnUpdateEmployee.gridy = 6;
frame.getContentPane().add(btnUpdateEmployee, gbc_btnUpdateEmployee);
btnViewEmployee = new JButton("View Employee");
GridBagConstraints gbc_btnViewEmployee = new GridBagConstraints();
gbc_btnViewEmployee.insets = new Insets(0, 0, 5, 5);
gbc_btnViewEmployee.gridx = 5;
gbc_btnViewEmployee.gridy = 7;
frame.getContentPane().add(btnViewEmployee, gbc_btnViewEmployee);
btnViewAllEmployees = new JButton("View All Employees");
GridBagConstraints gbc_btnViewAllEmployees = new GridBagConstraints();
gbc_btnViewAllEmployees.insets = new Insets(0, 0, 5, 5);
gbc_btnViewAllEmployees.gridx = 1;
gbc_btnViewAllEmployees.gridy = 8;
frame.getContentPane().add(btnViewAllEmployees, gbc_btnViewAllEmployees);
btnDeleteEmployee = new JButton("Delete Employee");
GridBagConstraints gbc_btnDeleteEmployee = new GridBagConstraints();
gbc_btnDeleteEmployee.insets = new Insets(0, 0, 5, 5);
gbc_btnDeleteEmployee.gridx = 5;
gbc_btnDeleteEmployee.gridy = 8;
frame.getContentPane().add(btnDeleteEmployee, gbc_btnDeleteEmployee);
btnGenerateReport = new JButton("Generate Report");
GridBagConstraints gbc_btnGenerateReport = new GridBagConstraints();
gbc_btnGenerateReport.insets = new Insets(0, 0, 0, 5);
gbc_btnGenerateReport.gridx = 1;
gbc_btnGenerateReport.gridy = 9;
frame.getContentPane().add(btnGenerateReport, gbc_btnGenerateReport);
}
public String getUsername() {
return tfusername.getText();
}
public String getPassword() {
return tfpassword.getText();
}
////SET action listeners
public void setAddButtonListener(ActionListener AddButtonListener) {
btnAddEmployee.addActionListener(AddButtonListener);
}
public void setUpdateButtonListener(ActionListener UpdateButtonListener) {
btnUpdateEmployee.addActionListener(UpdateButtonListener);
}
public void setDeleteButtonListener(ActionListener DeleteButtonListener) {
btnDeleteEmployee.addActionListener(DeleteButtonListener);
}
public void setViewButtonListener(ActionListener ViewButtonListener) {
btnViewEmployee.addActionListener(ViewButtonListener);
}
public void setViewAllButtonListener(ActionListener ViewAllButtonListener) {
btnViewAllEmployees.addActionListener(ViewAllButtonListener);
}
public void setGenerateReportButtonListener(ActionListener GenerateReportButtonListener) {
btnGenerateReport.addActionListener(GenerateReportButtonListener);
}
}
<file_sep>/BankDesk/src/main/java/repository/client/ClientRepository.java
package repository.client;
import model.Client;
import model.validation.Notification;
import java.util.List;
public interface ClientRepository {
List<Client> findAll();
Notification<Client> findById(Long id);
Notification<Client> findByName(String first, String last);
boolean save(Client client);
boolean update(Client client);
boolean removeById(Client client);
void removeAll();
}
<file_sep>/BankDesk/src/main/java/database/SQLTableCreationFactory.java
package database;
import static database.Constants.Tables.*;
public class SQLTableCreationFactory {
public String getCreateSQLforTable(String table) {
switch (table) {
case USER:
return "CREATE TABLE IF NOT EXISTS `bank`.`user` (" + "`id` INT NOT NULL AUTO_INCREMENT,"
+ "`username` VARCHAR(200) NOT NULL," + "`password` VARCHAR(64) NOT NULL," + "PRIMARY KEY (`id`),"
+ "UNIQUE INDEX `username_UNIQUE` (`username` ASC)," + "UNIQUE INDEX `id_UNIQUE` (`id` ASC))"
+ "ENGINE = InnoDB";
case CLIENT:
return "CREATE TABLE IF NOT EXISTS `bank`.`client` (" + "`id` INT NOT NULL AUTO_INCREMENT, "
+ "`firstName` VARCHAR(200) NOT NULL, " + "`lastName` VARCHAR(200) NOT NULL, "
+ "`CNP` VARCHAR(13) NOT NULL, " + "`idCard` VARCHAR(16) NOT NULL, "
+ "`address` VARCHAR(200) NOT NULL, " + " PRIMARY KEY (`id`)) " + "ENGINE = InnoDB";
case ACCOUNT:
return "CREATE TABLE IF NOT EXISTS `bank`.`account` (" + " `id` INT NOT NULL AUTO_INCREMENT,"
+ "`type` VARCHAR(45) NOT NULL," + " `money` FLOAT NULL," + "`dateOfCreation` DATE NULL,"
+ "`Accountcol` VARCHAR(45) NULL," + " PRIMARY KEY (`id`))" + "ENGINE = InnoDB";
case ROLE:
return "CREATE TABLE IF NOT EXISTS `bank`.`role` (" + "`id` INT NOT NULL AUTO_INCREMENT,"
+ " `role` VARCHAR(100) NOT NULL," + "PRIMARY KEY (`id`))" + "ENGINE = InnoDB";
case RIGHT:
return "CREATE TABLE IF NOT EXISTS `bank`.`right` (" + "`id` INT NOT NULL AUTO_INCREMENT,"
+ "`right` VARCHAR(100) NULL," + "PRIMARY KEY (`id`))" + "ENGINE = InnoDB";
case ROLE_RIGHT:
return "CREATE TABLE IF NOT EXISTS `bank`.`role_right` ( " + " `id` INT NOT NULL AUTO_INCREMENT,"
+ " `role_id` INT NOT NULL," + " `right_id` INT NOT NULL," + " PRIMARY KEY (`id`),"
+ " INDEX `ID_role_idx` (`role_id` ASC)," + " INDEX `ID_right_idx` (`right_id` ASC),"
+ " CONSTRAINT `ID_role`" + " FOREIGN KEY (`role_id`)" + " REFERENCES `bank`.`role` (`id`)"
+ " ON DELETE CASCADE" + " ON UPDATE CASCADE," + " CONSTRAINT `ID_right`"
+ " FOREIGN KEY (`right_id`)" + " REFERENCES `bank`.`right` (`id`)" + " ON DELETE CASCADE"
+ " ON UPDATE CASCADE)" + "ENGINE = InnoDB";
case USER_ROLE:
return "CREATE TABLE IF NOT EXISTS `bank`.`user_role` ( " + "`id` INT NOT NULL AUTO_INCREMENT,"
+ "`user_id` INT NOT NULL," + " `role_id` INT NOT NULL," + " PRIMARY KEY (`id`),"
+ " INDEX `user_id_idx` (`user_id` ASC)," + " INDEX `role_id_idx` (`role_id` ASC),"
+ " CONSTRAINT `user_id`" + " FOREIGN KEY (`user_id`)" + " REFERENCES `bank`.`user` (`id`)"
+ " ON DELETE CASCADE" + " ON UPDATE CASCADE," + " CONSTRAINT `role_id`"
+ " FOREIGN KEY (`role_id`)" + " REFERENCES `bank`.`role` (`id`)" + " ON DELETE CASCADE"
+ " ON UPDATE CASCADE)" + "ENGINE = InnoDB";
case CLIENT_ACCOUNT:
return "CREATE TABLE IF NOT EXISTS `bank`.`client_account` (" + " `idclient_account` INT NOT NULL,"
+ " `idclient` INT NULL," + " `idaccount` INT NULL," + " PRIMARY KEY (`idclient_account`),"
+ " INDEX `idClient_idx` (`idclient` ASC)," + " INDEX `idAccount_idx` (`idaccount` ASC),"
+ "CONSTRAINT `idClient`" + " FOREIGN KEY (`idclient`)" + " REFERENCES `bank`.`client` (`id`)"
+ " ON DELETE CASCADE" + " ON UPDATE CASCADE," + " CONSTRAINT `idAccount`"
+ " FOREIGN KEY (`idaccount`)" + " REFERENCES `bank`.`account` (`id`)" + " ON DELETE CASCADE"
+ " ON UPDATE CASCADE)" + "ENGINE = InnoDB";
default:
return "";
}
}
}
<file_sep>/BankDesk/src/main/java/controller/AdminViewController.java
package controller;
import model.User;
import model.validation.Notification;
import service.user.UserService;
import view.AdminView;
import javax.swing.*;
import javax.swing.table.DefaultTableModel;
import java.awt.event.ActionEvent;
import java.awt.event.ActionListener;
import java.util.List;
public class AdminViewController {
private final AdminView adminView;
private final UserService userService;
public AdminViewController(AdminView adminView, UserService userService) {
this.adminView = adminView;
this.userService = userService;
adminView.setAddButtonListener(new AddButtonListener());
adminView.setDeleteButtonListener(new DeleteButtonListener());
adminView.setGenerateReportButtonListener(new GenerateReportButtonListener());
adminView.setUpdateButtonListener(new UpdateButtonListener());
adminView.setViewAllButtonListener(new ViewAllButtonListener());
adminView.setViewButtonListener(new ViewButtonListener());
}
private class AddButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
String username = adminView.getUsername();
String password = <PASSWORD>();
Notification<Boolean> addNotification = userService.register(username, password);
if (addNotification.hasErrors()) {
JOptionPane.showMessageDialog(adminView.frame.getContentPane(), addNotification.getFormattedErrors());
} else {
if (!addNotification.getResult()) {
JOptionPane.showMessageDialog(adminView.frame.getContentPane(),
"Registration not successful, please try again later.");
} else {
JOptionPane.showMessageDialog(adminView.frame.getContentPane(), "Registration successful!");
}
}
}
}
private class DeleteButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent e) {
String username = adminView.getUsername();
Notification<Boolean> deleteNotification = userService.remove(username);
if (deleteNotification.hasErrors()) {
JOptionPane.showMessageDialog(adminView.frame.getContentPane(),
deleteNotification.getFormattedErrors());
} else {
JOptionPane.showMessageDialog(adminView.frame.getContentPane(), "Deletion successful!");
}
}
}
private class GenerateReportButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent arg0) {
String username = adminView.getUsername();
User user = userService.findByName(username).getResult();
List<String> report = userService.getOperations(user.getId());
String[] columnNames = {"operation"};
DefaultTableModel tableModel = new DefaultTableModel(columnNames, 0);
JTable table = new JTable(tableModel);
for (String currentOperation : report
) {
Object[] data = {currentOperation};
tableModel.addRow(data);
}
JOptionPane.showMessageDialog(null, new JScrollPane(table));
}
}
private class UpdateButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent arg0) {
// TODO Auto-generated method stub
//Not really used
}
}
private class ViewAllButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent arg0) {
List<User> allUsers = userService.findAll();
String[] columnNames = {"id", "username"};
DefaultTableModel tableModel = new DefaultTableModel(columnNames, 0);
JTable table = new JTable(tableModel);
for (User user : allUsers
) {
Object[] data = {user.getId(), user.getUsername()};
tableModel.addRow(data);
}
JOptionPane.showMessageDialog(null, new JScrollPane(table));
}
}
private class ViewButtonListener implements ActionListener {
@Override
public void actionPerformed(ActionEvent arg0) {
String userName = adminView.getUsername();
User user = userService.findByName(userName).getResult();
String[] columnNames = {"id", "username"};
DefaultTableModel tableModel = new DefaultTableModel(columnNames, 0);
JTable table = new JTable(tableModel);
Object[] data = {user.getId(), user.getUsername()};
tableModel.addRow(data);
JOptionPane.showMessageDialog(null, new JScrollPane(table));
}
}
}
<file_sep>/BankDesk/src/main/java/service/package-info.java
/**
* @author Stefi
*/
/**
* @author Stefi
*
*/
package service;<file_sep>/BankDesk/src/test/java/repository/ClientRepositoryTest.java
package repository;
import database.DBConnectionFactory;
import model.Client;
import model.builder.ClientBuilder;
import model.validation.ClientValidator;
import org.junit.Assert;
import org.junit.Before;
import org.junit.Test;
import repository.account.AccountRepository;
import repository.account.AccountRepositoryMySql;
import repository.accountsManagement.ClientAccountRepository;
import repository.accountsManagement.ClientAccountRepositoryMySql;
import repository.client.ClientRepository;
import repository.client.ClientRepositoryMySql;
import java.sql.Connection;
import java.util.List;
/**
* Created by Stefi on 03-Apr-17.
*/
public class ClientRepositoryTest {
private static ClientRepository clientRepository;
private static ClientAccountRepository clientAccountRepository;
private static AccountRepository accountRepository;
@Before
public void setUp() throws Exception {
Connection connection = new DBConnectionFactory().getConnectionWrapper(true).getConnection();
clientRepository = new ClientRepositoryMySql(connection, clientAccountRepository);
accountRepository = new AccountRepositoryMySql(connection);
clientAccountRepository = new ClientAccountRepositoryMySql(connection, accountRepository);
}
@Test
public void save() throws Exception {
String firstName = "Preume";
String lastName = "Nume";
String CNP = "2950726314003";
String Card = "1234569874";
String address = "addrblabla";
Client clientTest = new ClientBuilder()
.setFirstName(firstName)
.setLastName(lastName)
.setCNP(CNP)
.setAddress(address)
.setIdCard(Card)
.build();
ClientValidator clientValidator = new ClientValidator(clientTest);
boolean clientValid = clientValidator.validate();
if (clientValid) {
Assert.assertTrue(clientRepository.save(clientTest));
}
}
@Test
public void findAll() throws Exception {
List<Client> clients = clientRepository.findAll();
Assert.assertNotNull(clients);
}
@Test
public void findById() throws Exception {
String firstName = "Preume";
String lastName = "Nume";
String CNP = "2950726314003";
String Card = "1234569874";
String address = "addrblabla";
Client clientTest = new ClientBuilder()
.setFirstName(firstName)
.setLastName(lastName)
.setCNP(CNP)
.setAddress(address)
.setIdCard(Card)
.build();
clientRepository.save(clientTest);
Client client = clientRepository.findById(clientTest.getId()).getResult();
Assert.assertNotNull(client);
}
@Test
public void findByName() throws Exception {
String firstName = "Preume";
String lastName = "Nume";
String CNP = "2950726314003";
String Card = "1234569874";
String address = "addrblabla";
Client clientTest = new ClientBuilder()
.setFirstName(firstName)
.setLastName(lastName)
.setCNP(CNP)
.setAddress(address)
.setIdCard(Card)
.build();
clientRepository.save(clientTest);
Assert.assertNotNull(clientRepository.findByName(firstName, lastName).getResult());
}
@Test
public void update() throws Exception {
String firstName = "Preume";
String lastName = "Nume";
String CNP = "2950726314003";
String Card = "1234569874";
String address = "addrblabla";
Client clientTest = new ClientBuilder()
.setFirstName(firstName)
.setLastName(lastName)
.setCNP(CNP)
.setAddress(address)
.setIdCard(Card)
.build();
clientRepository.save(clientTest);
String newAddress = "new home";
clientTest.setAddress(newAddress);
Assert.assertTrue(clientRepository.update(clientTest));
}
@Test
public void remove() throws Exception {
String firstName = "Preume";
String lastName = "Nume";
String CNP = "2950726314003";
String Card = "1234569874";
String address = "addrblabla";
Client clientTest = new ClientBuilder()
.setFirstName(firstName)
.setLastName(lastName)
.setCNP(CNP)
.setAddress(address)
.setIdCard(Card)
.build();
clientRepository.save(clientTest);
Assert.assertTrue(clientRepository.removeById(clientTest));
}
@Test
public void removeAll() throws Exception {
clientRepository.removeAll();
List<Client> clients = clientRepository.findAll();
Assert.assertTrue(clients.isEmpty());
}
}
<file_sep>/BankDesk/src/test/java/repository/UserRepositoryTest.java
package repository;
/**
* Created by Stefi on 30-Mar-17.
*/
import database.DBConnectionFactory;
import model.Role;
import model.User;
import model.builder.UserBuilder;
import model.validation.UserValidator;
import org.junit.Assert;
import org.junit.Before;
import org.junit.Test;
import repository.security.RightsRolesRepository;
import repository.security.RightsRolesRepositoryMySql;
import repository.user.UserRepository;
import repository.user.UserRepositoryMySql;
import java.sql.Connection;
import java.util.Collections;
import java.util.List;
import static database.Constants.Roles.EMPLOYEE;
public class UserRepositoryTest {
private static UserRepository userRepository;
private static RightsRolesRepository rightsRolesRepository;
@Before
public void setUp() throws Exception {
Connection connection = new DBConnectionFactory().getConnectionWrapper(true).getConnection();
rightsRolesRepository = new RightsRolesRepositoryMySql(connection);
userRepository = new UserRepositoryMySql(connection, rightsRolesRepository);
}
@Test
public void findAll() throws Exception {
List<User> users = userRepository.findAll();
Assert.assertNotNull(users);
}
@Test
public void findById() throws Exception {
String username = "<EMAIL>";
String password = "<PASSWORD>!";
Role employeeRole = rightsRolesRepository.findRolebyTitle("Employee");
User userTest = new UserBuilder()
.setUsername(username)
.setPassword(<PASSWORD>)
.setRoles(Collections.singletonList(employeeRole))
.build();
userRepository.save(userTest);
Long idToFind = userTest.getId();
User user = userRepository.findById(idToFind).getResult();
Assert.assertNotNull(user);
}
@Test
public void findByUsernameAndPassword() throws Exception {
String username = "<EMAIL>";
String password = "<PASSWORD>!";
Role employeeRole = rightsRolesRepository.findRolebyTitle("Employee");
User userTest = new UserBuilder()
.setUsername(username)
.setPassword(<PASSWORD>)
.setRoles(Collections.singletonList(employeeRole))
.build();
userRepository.save(userTest);
User user = userRepository.findByUsernameAndPassword(username, password).getResult();
Assert.assertNotNull(user);
}
@Test
public void findByIdAndPassword() throws Exception {
String username = "<EMAIL>";
String password = "<PASSWORD>!";
Role employeeRole = rightsRolesRepository.findRolebyTitle("Employee");
User userTest = new UserBuilder()
.setUsername(username)
.setPassword(<PASSWORD>)
.setRoles(Collections.singletonList(employeeRole))
.build();
userRepository.save(userTest);
User user = userRepository.findByUsernameAndPassword(username, password).getResult();
Assert.assertNotNull(user);
}
@Test
public void save() throws Exception {
String username = "<EMAIL>";
String password = "<PASSWORD>!";
Role employeeRole = rightsRolesRepository.findRolebyTitle(EMPLOYEE);
User userTest = new UserBuilder()
.setUsername(username)
.setPassword(<PASSWORD>)
.setRoles(Collections.singletonList(employeeRole))
.build();
UserValidator userValidator = new UserValidator(userTest);
boolean userValid = userValidator.validate();
if (userValid) {
Assert.assertTrue(userRepository.save(userTest));
}
}
@Test
public void update() throws Exception {
String username = "<EMAIL>";
String password = "<PASSWORD>!";
Role employeeRole = rightsRolesRepository.findRolebyTitle(EMPLOYEE);
User userTest = new UserBuilder()
.setUsername(username)
.setPassword(<PASSWORD>)
.setRoles(Collections.singletonList(employeeRole))
.build();
userRepository.save(userTest);
String newPassword = "<PASSWORD>@";
userTest.setPassword(newPassword);
Assert.assertTrue(userRepository.update(userTest));
}
@Test
public void remove() throws Exception {
String username = "<EMAIL>";
String password = "<PASSWORD>!";
Role employeeRole = rightsRolesRepository.findRolebyTitle(EMPLOYEE);
User userTest = new UserBuilder()
.setUsername(username)
.setPassword(<PASSWORD>)
.setRoles(Collections.singletonList(employeeRole))
.build();
userRepository.save(userTest);
Assert.assertTrue(userRepository.remove(userTest));
}
@Test
public void removeAll() throws Exception {
userRepository.removeAll();
List<User> user = userRepository.findAll();
Assert.assertTrue(user.isEmpty());
}
}
<file_sep>/BankDesk/src/main/java/repository/account/AccountRepositoryMySql.java
package repository.account;
import model.Account;
import model.builder.AccountBuilder;
import model.validation.Notification;
import org.joda.time.DateTime;
import java.sql.*;
import java.util.ArrayList;
import java.util.List;
public class AccountRepositoryMySql implements AccountRepository {
private final Connection connection;
public AccountRepositoryMySql(Connection connection) {
this.connection = connection;
}
@Override
public List<Account> findAll() {
List<Account> accounts = new ArrayList<>();
try {
Statement statement = connection.createStatement();
String sql = "Select * from bank.account";
ResultSet result = statement.executeQuery(sql);
while (result.next()) {
accounts.add(new AccountBuilder().setType(result.getString("type")).setMoney(result.getFloat("money"))
.setDateOfCreation(new DateTime(result.getDate("dateOfCreation"))).build());
}
return accounts;
} catch (SQLException e) {
e.printStackTrace();
}
return null;
}
@Override
public boolean save(Account account) {
try {
PreparedStatement insertStatement = connection.prepareStatement("INSERT INTO bank.account values (null,?,?,?)");
insertStatement.setString(1, account.getType());
insertStatement.setFloat(2, account.getMoney());
insertStatement.setDate(3, new java.sql.Date(account.getDateOfCreation().toDate().getTime()));
insertStatement.executeUpdate();
ResultSet result = insertStatement.getGeneratedKeys();
result.next();
long accountId = result.getLong(1);
account.setId(accountId);
return true;
} catch (SQLException e) {
e.printStackTrace();
return false;
}
}
@Override
public boolean update(Account account) {
try {
PreparedStatement updateAccountStatement = connection
.prepareStatement("UPDATE bank.account SET money=? WHERE id=? ");
updateAccountStatement.setFloat(1, account.getMoney());
updateAccountStatement.setLong(2, account.getId());
updateAccountStatement.executeUpdate();
return true;
} catch (SQLException e) {
e.printStackTrace();
return false;
}
}
@Override
public boolean removeById(Account account) {
try {
PreparedStatement removeStatement = connection.prepareStatement("Delete FROM bank.account where id=?");
removeStatement.setLong(1, account.getId());
removeStatement.executeUpdate();
return true;
} catch (SQLException e) {
e.printStackTrace();
}
return false;
}
@Override
public void removeAll() {
try {
Statement statement = connection.createStatement();
String sql = "DELETE from account where id>=0";
statement.executeUpdate(sql);
} catch (SQLException e) {
e.printStackTrace();
}
}
@Override
public Notification<Account> findById(Long id) {
Notification<Account> findByid = new Notification<>();
try {
Statement statement = connection.createStatement();
String fetch = "Select * from bank.account where `id`=\'" + id + "\'";
ResultSet ResultSet = statement.executeQuery(fetch);
ResultSet.next();
Account account = new AccountBuilder()
.setId(ResultSet.getLong("id"))
.setType(ResultSet.getString("type"))
.setMoney(ResultSet.getFloat("money"))
.setDateOfCreation(new DateTime(ResultSet.getDate("dateOfCreation"))).build();
findByid.setResult(account);
return findByid;
} catch (SQLException e) {
e.printStackTrace();
findByid.addError("Entity not found");
return findByid;
}
}
}
| d072cf438ff55f52db2f493c4b5eb35ce1ea0c8f | [
"Java",
"Gradle"
] | 15 | Java | SoftwareDesign2017/assignment-1-stefaniasucitu | 066e6986f9f0f24087b90f329a06dbae04631f9e | e849d73b5e2c68b26bf86c4356db7cf37cfaa006 |
refs/heads/master | <file_sep>import requests
url_endpoint = 'http://api.noobtest.id/dummy/v1/users/8'
query = {"email": "<EMAIL>","name": "Maitimo"}
response = requests.put(url_endpoint, json=query)
print(response.status_code)
print(response.text)<file_sep>import requests
url_endpoint = 'http://api.noobtest.id/dummy/v1/users'
response = requests.get(url_endpoint)
print(response.text)<file_sep>import requests
import pytest
import json
import jsonpath
def test_getuser():
url_endpoint = 'http://api.noobtest.id/dummy/v1/users/1'
response = requests.get(url_endpoint)
Code = response.status_code
assert Code == 200
json_response = json.loads(response.text)
Name = jsonpath.jsonpath(json_response, 'name')
assert Name[0] == 'broto'
def test_postuser():
url_endpoint = 'http://api.noobtest.id/dummy/v1/users'
query = {"email": "<EMAIL>", "name": "<NAME>"}
response = requests.post(url_endpoint, json=query)
Code = response.status_code
assert Code == 200
json_response = json.loads(response.text)
Name = jsonpath.jsonpath(json_response, 'name')
assert Name[0] == '<NAME>'<file_sep>import requests
import pytest
import json
import jsonpath
def test_postjson():
url_endpoint = 'http://api.noobtest.id/dummy/v1/users'
file = open('D:\Code\CODING ID\API_TEST\post.json', 'r')
req_json = json.loads(file.read())
response = requests.post(url_endpoint, json=req_json)
Code = response.status_code
assert Code == 200
json_response = json.loads(response.text)
Name = jsonpath.jsonpath(json_response, 'name')
assert Name[0] == 'Rapael'<file_sep>import requests
url_endpoint = 'http://api.noobtest.id/dummy/v1/users/3'
response = requests.delete(url_endpoint)
print(response.status_code)
print(response.text)<file_sep>requests == 2.26.0
pytest == 6.2.5<file_sep>import requests
url_endpoint = 'http://api.noobtest.id/dummy/v1/users'
query = {"email": "<EMAIL>","name": "Rafael"}
response = requests.post(url_endpoint, json=query)
print(response.status_code)
print(response.text)
| ffeb5535188be13c519a6aa27fb0a8157015bba7 | [
"Python",
"Text"
] | 7 | Python | havidri/Python_API_Automation | 0c5fa75cd74a27488861dac4273ce7b5e6b6451b | f394c40d8765b8cc0ce645fd1ca0fb5d7221590f |
refs/heads/master | <file_sep>const express = require('express');
const resultController = require('./../controllers/resultController');
const router = express.Router();
router.get('/results', resultController.getResults);
router.post('/results', resultController.postResults);
module.exports = router;<file_sep>const express = require('express');
const passport = require('passport');
const usersController = require('./../controllers/usersController');
const adminController = require('./../controllers/adminController');
const userHelper = require('./../helpers/userHelper');
const router = express.Router();
router.get('/dashboard', adminController.adminPage);
router.post('/uploadFile', adminController.uploadUserPhoto, adminController.resizeUserPhoto);
router.post('/dashboard', adminController.adminPostPage);
module.exports = router;
<file_sep>const express = require('express');
const privatechatController = require('./../controllers/privatechatController');
const router = express.Router();
router.get('/chat/:name', privatechatController.getchatPage);
router.post('/chat/:name', privatechatController.chatPostPage);
module.exports = router;
<file_sep>const _ = require('lodash');
const User = require('../models/usersModel');
const Club = require('../models/clubModel');
const Message = require('../models/messageModel');
const groupMessage = require('../models/groupchatMessageModel');
module.exports.getOverviewPage = async(req, res, next) => {
const name = req.params.name;
const userData = await User.findOne({ 'username': name }).populate('request.userId');
const messages = await Message.aggregate(
[{ $match: { $or: [
{'senderName': req.user.username },
{'receiverName': req.user.username}] }},
{ $sort: {'createdAt': -1 }},
{
$group: {
"_id":{
"last_message_between":{
$cond: [
{
$gt: [
{$substr: ["$senderName", 0, 1]},
{$substr: ["$receiverName", 0, 1]}
]
},
{ $concat: ["$senderName", " and ", "$receiverName"]},
{ $concat: ["$receiverName", " and ", "$senderName"]}
]
}
}, "body": {$first:"$$ROOT"}
}
}]
);
res.render('user/overview', { title: 'Footballkik - Overview', user: req.user, dat: userData, chat:messages });
};
// module.exports.getOverviewPostPage = async(req, res, next) => {
// try{
// if(req.body.receiver){
// await User.update(
// {
// 'username': req.body.receiver,
// 'request.userId': { $ne: req.user._id},
// 'friendsList.friendId': {$ne: req.user._id}
// },
// {
// $push: { request: {
// userId: req.user._id,
// username: req.user.username
// }},
// $inc: {totalRequest: 1}
// });
// await User.update({
// 'username': req.user.username,
// 'sentRequest.username': {$ne: req.body.receiver}
// },
// {
// $push: {
// sentRequest: {
// username: req.body.receiver
// }
// }
// });
// res.redirect('/profile/'+req.params.name);
// }
// if(req.body.senderId){
// await User.update({
// '_id': req.user._id,
// 'friendsList.friendId': {$ne: req.body.senderId}
// },{
// $push: {friendsList: {
// friendId: req.body.senderId,
// friendName: req.body.senderName
// }},
// $pull: { request: {
// userId: req.body.senderId,
// username: req.body.senderName
// }},
// $inc: { totalRequest: -1 }
// }, (err) => {
// if(err){
// console.log(err);
// }
// });
// await User.update({
// '_id': req.body.senderId,
// 'friendsList.friendId': {$ne: req.user._id}
// },{
// $push: {friendsList: {
// friendId: req.user._id,
// friendName: req.user.username
// }},
// $pull: { sentRequest: {
// username: req.user.username
// }},
// }, (err) => {
// if(err){
// console.log(err);
// }
// });
// res.redirect('/profile/'+req.params.name);
// }
// if(req.body.user_Id){
// await User.update({
// '_id': req.user._id,
// 'request.userId': {$eq: req.body.user_Id}
// },{
// $pull: { request: {
// userId: req.body.user_Id
// }},
// $inc: { totalRequest: -1 }
// }, (err) => {
// if(err){
// console.log(err);
// }
// });
// await User.update({
// '_id': req.body.user_Id,
// 'sentRequest.username': {$eq: req.user.username}
// },{
// $pull: { sentRequest: {
// username: req.user.username
// }},
// }, (err) => {
// if(err){
// console.log(err);
// }
// });
// res.redirect('/profile/'+req.params.name);
// }
// if(req.body.chatId){
// const updateM = await Message.update({
// '_id': req.body.chatId
// },{
// "isRead": true
// });
// res.redirect('/profile/'+req.params.name);
// }
// }catch(err){
// console.log(err);
// }
// };
<file_sep>const express = require('express');
const homeController = require('./../controllers/homeController');
const router = express.Router();
router.get('/home', homeController.homePage);
router.post('/home', homeController.postHomePage);
router.get('/logout', homeController.logout);
module.exports = router;
<file_sep>const passport = require('passport');
module.exports.indexPage = (req, res) => {
const errors = req.flash('error');
return res.render('index', {
title: 'FootballKik | Login',
messages: errors,
hasErrors: errors.length > 0
});
};
module.exports.getSignup = (req, res) => {
const errors = req.flash('error');
return res.render('signup', {
title: 'FootballKik | Signup',
messages: errors,
hasErrors: errors.length > 0
});
};
module.exports.postSignup = passport.authenticate('local.signup', {
successRedirect: '/home',
failureRedirect: '/signup',
failureFlash: true
});
module.exports.postLogin = passport.authenticate('local.login', {
successRedirect: '/home',
failureRedirect: '/',
failureFlash: true
});
<file_sep>const multer = require('multer');
const sharp = require('sharp');
const _ = require('lodash');
const User = require('../models/usersModel');
const Club = require('../models/clubModel');
const Message = require('../models/messageModel');
module.exports.footballNews = async(req, res, next) => {
res.render('news/footballnews', { title: 'Footballkik - Latest News', user: req.user});
};
<file_sep>const express = require('express');
const membersController = require('../controllers/membersController');
const router = express.Router();
router.get('/members', membersController.viewMembers);
router.post('/members', membersController.searchMembers);
module.exports = router;<file_sep>const _ = require('lodash');
const User = require('../models/usersModel');
const Club = require('../models/clubModel');
const Message = require('../models/messageModel');
module.exports.getchatPage = async (req, res, next) => {
const name = req.params.name;
const userData = await User.findOne({ 'username': req.user.username }).populate('request.userId');
const messages = await Message.aggregate(
[{ $match: { $or: [
{'senderName': req.user.username },
{'receiverName': req.user.username}] }},
{ $sort: {'createdAt': -1 }},
{
$group: {
"_id":{
"last_message_between":{
$cond: [
{
$gt: [
{$substr: ["$senderName", 0, 1]},
{$substr: ["$receiverName", 0, 1]}
]
},
{ $concat: ["$senderName", " and ", "$receiverName"]},
{ $concat: ["$receiverName", " and ", "$senderName"]}
]
}
}, "body": {$first:"$$ROOT"}
}
}]
);
const myMessagesFromFriends = await Message.find({'$or': [
{'senderName': req.user.username },
{'receiverName': req.user.username }
]}).populate('sender').populate('receiver');
const params = req.params.name.split('.');
const nameParams = params[0];
res.render('private/privatechat', { title: 'Footballkik - Private Chat', user: req.user, chat:messages ,groupName: name, dat: userData, chats: myMessagesFromFriends, name: nameParams });
};
module.exports.chatPostPage = async(req, res, next) => {
try{
const params = req.params.name.split('.');
const nameParams = params[0];
const nameRegex = new RegExp("^"+nameParams.toLowerCase(), "i");
if(req.body.message){
const receiverData = await User.findOne({ 'username': { $regex: nameRegex }});
const newMessage = new Message();
newMessage.sender = req.user._id;
newMessage.receiver = receiverData._id;
newMessage.senderName = req.user.username;
newMessage.receiverName = receiverData.username;
newMessage.message = req.body.message;
newMessage.userImage = req.user.userImage;
newMessage.createdAt = new Date();
await newMessage.save((err, result)=>{
if(err){
return next(err);
}
console.log(result);
});
res.redirect('/chat/'+req.params.name);
}
if(req.body.chatId){
const updateM = await Message.update({
'_id': req.body.chatId
},{
"isRead": true
});
res.redirect('/chat/'+req.params.name);
}
}catch(err){
console.log(err);
}
};<file_sep>const express = require('express');
const interestController = require('./../controllers/interestController');
const router = express.Router();
router.get('/settings/interests', interestController.getInterestPage);
router.post('/settings/interests', interestController.postInterestPage);
module.exports = router;
<file_sep>const express = require('express');
const overviewController = require('./../controllers/overviewController');
const router = express.Router();
router.get('/profile/:name', overviewController.getOverviewPage);
//router.post('/profile/:name', overviewController.getOverviewPostPage);
module.exports = router;
<file_sep>const express = require('express');
const passport = require('passport');
const usersController = require('./../controllers/usersController');
const userHelper = require('./../helpers/userHelper');
const router = express.Router();
router.get('/', usersController.indexPage);
router.get('/signup', usersController.getSignup);
router.get('/auth/facebook', passport.authenticate('facebook', {scope:"email"}));
router.get('/auth/facebook/callback', passport.authenticate('facebook',
{ successRedirect: '/home', failureRedirect: '/signup' }));
// router.get('/auth/twitter', passport.authenticate('twitter', {scope:"email"}));
// router.get('/auth/twitter/callback',
// passport.authenticate('twitter', { successRedirect: '/home',
// failureRedirect: '/signup' }));
router.get('/auth/google', passport.authenticate('google', {
scope: ['https://www.googleapis.com/auth/plus.login',
'https://www.googleapis.com/auth/userinfo.email'
]
}));
router.get('/auth/google/callback', passport.authenticate('google', {
successRedirect: '/home',
failureRedirect: '/signup'
}));
router.post('/signup', userHelper.SignUpValidation, usersController.postSignup);
router.post('/', userHelper.LoginValidation, usersController.postLogin);
module.exports = router;
<file_sep>const _ = require('lodash');
const multer = require('multer');
const sharp = require('sharp');
const User = require('../models/usersModel');
const Club = require('../models/clubModel');
const Message = require('../models/messageModel');
const groupMessage = require('../models/groupchatMessageModel');
const multerStroage = multer.memoryStorage();
const multerFilter = (req, file, cb) => {
if (file.mimetype.startsWith('image')) {
cb(null, true);
} else {
const err = new Error('Not an image! please upload only images.');
err.statusCode = 400;
err.status = 'fail';
cb(err, false);
}
};
const upload = multer({
storage: multerStroage,
fileFilter: multerFilter
});
exports.uploadUserPhoto = upload.single('upload');
exports.resizeUserPhoto = async(req, res, next) => {
try{
if (!req.file) return next();
req.file.filename = `${req.file.originalname}`;
await sharp(req.file.buffer)
.resize(300, 300)
.toFile(`public/profileUploads/${req.file.filename}`);
}catch(err) {
console.log(err);
}
next();
};
module.exports.getProfilePage = async(req, res, next) => {
const name = req.params.name;
const userData = await User.findOne({ 'username': req.user.username }).populate('request.userId');
const messages = await Message.aggregate(
[{ $match: { $or: [
{'senderName': req.user.username },
{'receiverName': req.user.username}] }},
{ $sort: {'createdAt': -1 }},
{
$group: {
"_id":{
"last_message_between":{
$cond: [
{
$gt: [
{$substr: ["$senderName", 0, 1]},
{$substr: ["$receiverName", 0, 1]}
]
},
{ $concat: ["$senderName", " and ", "$receiverName"]},
{ $concat: ["$receiverName", " and ", "$senderName"]}
]
}
}, "body": {$first:"$$ROOT"}
}
}]
);
res.render('user/profile', { title: 'Footballkik - Profile', user: req.user, groupName: name, dat: userData, chat:messages });
};
module.exports.postProfilePage = async(req, res, next) => {
try{
if(req.body.receiver){
await User.update(
{
'username': req.body.receiver,
'request.userId': { $ne: req.user._id},
'friendsList.friendId': {$ne: req.user._id}
},
{
$push: { request: {
userId: req.user._id,
username: req.user.username
}},
$inc: {totalRequest: 1}
});
await User.update({
'username': req.user.username,
'sentRequest.username': {$ne: req.body.receiver}
},
{
$push: {
sentRequest: {
username: req.body.receiver
}
}
});
res.redirect('/settings/profile');
}
if(req.body.senderId){
await User.update({
'_id': req.user._id,
'friendsList.friendId': {$ne: req.body.senderId}
},{
$push: {friendsList: {
friendId: req.body.senderId,
friendName: req.body.senderName
}},
$pull: { request: {
userId: req.body.senderId,
username: req.body.senderName
}},
$inc: { totalRequest: -1 }
}, (err) => {
if(err){
console.log(err);
}
});
await User.update({
'_id': req.body.senderId,
'friendsList.friendId': {$ne: req.user._id}
},{
$push: {friendsList: {
friendId: req.user._id,
friendName: req.user.username
}},
$pull: { sentRequest: {
username: req.user.username
}},
}, (err) => {
if(err){
console.log(err);
}
});
res.redirect('/settings/profile');
}
if(req.body.user_Id){
await User.update({
'_id': req.user._id,
'request.userId': {$eq: req.body.user_Id}
},{
$pull: { request: {
userId: req.body.user_Id
}},
$inc: { totalRequest: -1 }
}, (err) => {
if(err){
console.log(err);
}
});
await User.update({
'_id': req.body.user_Id,
'sentRequest.username': {$eq: req.user.username}
},{
$pull: { sentRequest: {
username: req.user.username
}},
}, (err) => {
if(err){
console.log(err);
}
});
res.redirect('/settings/profile');
}
if(req.body.chatId){
const updateM = await Message.update({
'_id': req.body.chatId
},{
"isRead": true
});
res.redirect('/settings/profile');
}
const user1 = await User.findOne({ '_id': req.user._id });
if(req.body.upload === null || req.body.upload === ''){
const user1Update = await User.update({
'_id': req.user._id
},{
username: req.body.username,
fullname: req.body.fullname,
country: req.body.country,
mantra: req.body.mantra,
gender: req.body.gender,
userImage: user1.userImage
},{
upsert: true,
new: true
});
console.log(user1Update);
res.redirect('/settings/profile');
}else if(req.body.upload !== null || req.body.upload !== ''){
const user1Update = await User.update({
'_id': req.user._id
},{
username: req.body.username,
fullname: req.body.fullname,
country: req.body.country,
mantra: req.body.mantra,
gender: req.body.gender,
userImage: req.body.upload
},{
upsert: true,
new: true
});
console.log(user1Update);
res.redirect('/settings/profile');
}
}catch(err){
console.log(err);
}
};<file_sep>const _ = require('lodash');
const User = require('../models/usersModel');
const Club = require('../models/clubModel');
const Message = require('../models/messageModel');
const groupMessage = require('../models/groupchatMessageModel');
module.exports.viewMembers = async(req, res, next) => {
const allUsers = await User.find({});
const dataChunk = [];
const chunkSzie = 4;
for(let i = 0 ; i< allUsers.length; i+=chunkSzie){
dataChunk.push(allUsers.slice(i, i+chunkSzie));
}
res.render('members', { title: 'Footballkik - Members', user: req.user, chunks: dataChunk });
};
module.exports.searchMembers = async(req, res, next) => {
const regex = new RegExp(req.body.username, "gi");
const allUsers = await User.find({ 'username': regex});
const dataChunk = [];
const chunkSzie = 4;
for(let i = 0 ; i< allUsers.length; i+=chunkSzie){
dataChunk.push(allUsers.slice(i, i+chunkSzie));
}
res.render('members', { title: 'Footballkik - Members', user: req.user, chunks: dataChunk });
};<file_sep>const passport = require('passport')
const TwitterStrategy = require('passport-twitter').Strategy;
const User = require('../models/usersModel');
const Secret = require('./../secret/secretFile');
const flash = require('connect-flash');
passport.serializeUser((user, done) => {
done(null, user.id);
});
passport.deserializeUser((id, done) => {
User.findById(id, (err, user) => {
done(err, user);
});
});
passport.use(new TwitterStrategy({
consumerKey: Secret.google.clientID,
consumerSecret: Secret.google.clientSecret,
callbackURL: "http://localhost:3000/auth/twitter/callback"
},
function (token, tokenSecret, profile, done){
User.findOne({ twitter: profile.id }, (err, user) => {
if(err){
return done(err);
}
if(user) {
return done(null, user);
}else {
console.log(profile, token, tokenSecret);
// const newUser = new User();
// newUser.twiiter = profile.id;
// newUser.fullname = profile.displayName;
// newUser.email = profile.emails[0].value;
// newUser.userImage = profile._json.image.url;
// newUser.save((err)=>{
// if(err){
// return done(err);
// }
// return done(null, newUser);
// });
}
})
}));
| f3cc202c445a865e6ecf63af0878662792cf6feb | [
"JavaScript"
] | 15 | JavaScript | sherifwahballa1/footballKik | 700afdcf5ab94782a1aaf147a523e479cf138362 | 97f36fe754605d7b87252de9bc44ac076ad2aa17 |
refs/heads/main | <repo_name>adamayoung/AuthenticationKit<file_sep>/Sources/AuthenticationKit/Models/AuthState.swift
//
// AuthState.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import AppAuth
import Combine
import Foundation
public final class AuthState {
private let authState: OIDAuthState
public private(set) var jwt: JWT?
public var lastIDToken: String? {
authState.lastTokenResponse?.idToken
}
public var lastAccessToken: String? {
authState.lastTokenResponse?.accessToken
}
init(state: OIDAuthState) {
self.authState = state
self.jwt = JWT(fromAccessToken: authState.lastTokenResponse?.accessToken,
or: authState.lastTokenResponse?.idToken)
}
public func performAction() -> AnyPublisher<String?, Error> {
if jwt?.isExpired ?? false {
print("Token expired - refreshing")
authState.setNeedsTokenRefresh()
}
return authState.performActionPublisher()
.map { JWT(fromAccessToken: $0.0, or: $0.1) }
.handleEvents(receiveOutput: { self.jwt = $0 })
.map { $0?.rawValue }
.mapError { AuthenticationError.cannotRefreshToken(error: $0) }
.eraseToAnyPublisher()
}
}
extension AuthState: Codable {
private enum CodingKeys: String, CodingKey {
case authState
}
public convenience init(from decoder: Decoder) throws {
let container = try decoder.container(keyedBy: CodingKeys.self)
let stateData = try container.decode(Data.self, forKey: .authState)
// swiftlint:disable force_cast
let state = try NSKeyedUnarchiver.unarchiveTopLevelObjectWithData(stateData) as! OIDAuthState
// swiftlint:enable force_cast
self.init(state: state)
}
public func encode(to encoder: Encoder) throws {
var container = encoder.container(keyedBy: CodingKeys.self)
let stateData = try NSKeyedArchiver.archivedData(withRootObject: authState, requiringSecureCoding: true)
try container.encode(stateData, forKey: .authState)
}
}
<file_sep>/Sources/AuthenticationKit/Extensions/OIDAuthorizationRequest+Extension.swift
//
// OIDAuthorizationRequest+Extension.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import AppAuth
import Foundation
extension OIDAuthorizationRequest {
convenience init(configuration: OIDServiceConfiguration, providerConfiguration: OIDProviderConfiguration,
loginHint: String?, redirectURL: URL) {
let identityProviderType = IdentityProviderType(wellKnownEndpoint: providerConfiguration.wellKnownEndpoint)
var scopes = [OIDScopeOpenID, OIDScopeEmail]
scopes.append(contentsOf: providerConfiguration.additionalScopes)
if case .azureADB2C = identityProviderType {
scopes.append("offline_access")
}
var additionalParameters = providerConfiguration.additionalParameters
additionalParameters["prompt"] = "login"
if let loginHint = loginHint {
additionalParameters["login_hint"] = loginHint
}
self.init(configuration: configuration, clientId: providerConfiguration.clientID, scopes: scopes,
redirectURL: redirectURL, responseType: OIDResponseTypeCode,
additionalParameters: additionalParameters)
}
}
<file_sep>/Package.swift
// swift-tools-version:5.2
// The swift-tools-version declares the minimum version of Swift required to build this package.
import PackageDescription
let package = Package(
name: "AuthenticationKit",
platforms: [
.macOS(.v10_15), .iOS(.v13), .tvOS(.v13), .watchOS(.v6)
],
products: [
.library(name: "AuthenticationKit", targets: ["AuthenticationKit"])
],
dependencies: [
.package(name: "AppAuth", url: "https://github.com/openid/AppAuth-iOS.git", from: "1.4.0")
],
targets: [
.target(name: "AuthenticationKit", dependencies: ["AppAuth"]),
.testTarget(name: "AuthenticationKitTests", dependencies: ["AuthenticationKit"])
]
)
<file_sep>/Sources/AuthenticationKit/Extensions/OIDAuthorizationService+Combine.swift
//
// OIDAuthorizationService+Combine.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import AppAuth
import Combine
import Foundation
extension OIDAuthorizationService {
static func discoverConfigurationPublisher(forDiscoveryURL discoveryURL: URL) -> AnyPublisher<OIDServiceConfiguration?, Error> {
Future<OIDServiceConfiguration?, Error> { promise in
OIDAuthorizationService.discoverConfiguration(forDiscoveryURL: discoveryURL) { configuration, error in
if let error = error {
promise(.failure(error))
return
}
promise(.success(configuration))
}
}
.eraseToAnyPublisher()
}
}
<file_sep>/Sources/AuthenticationKit/Models/JWT+Claims.swift
//
// JWT+Claims.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import Foundation
extension JWT {
public func claim(name: String) -> Claim {
let value = self.body[name]
return Claim(value: value)
}
public var expiresAt: Date? {
return claim(name: "exp").date
}
public var issuer: String? {
return claim(name: "iss").string
}
public var subject: String? {
return claim(name: "sub").string
}
public var audience: [String]? {
return claim(name: "aud").array
}
public var issuedAt: Date? {
return claim(name: "iat").date
}
public var notBefore: Date? {
return claim(name: "nbf").date
}
public var identifier: String? {
return claim(name: "jti").string
}
public var expired: Bool {
guard let date = self.expiresAt else {
return false
}
return date.compare(Date()) != ComparisonResult.orderedDescending
}
public var email: String? {
if let email = claim(name: "upn").string {
return email
}
if let emails = claim(name: "emails").value as? [String], let email = emails.first {
return email
}
if let email = claim(name: "email").string {
return email
}
return nil
}
}
<file_sep>/Sources/AuthenticationKit/Models/Claim.swift
//
// Claim.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import Foundation
public struct Claim {
public let value: Any?
public var rawValue: Any? {
value
}
public var string: String? {
value as? String
}
public var double: Double? {
let double: Double?
if let string = self.string {
double = Double(string)
} else {
double = self.value as? Double
}
return double
}
public var integer: Int? {
let integer: Int?
if let string = self.string {
integer = Int(string)
} else if let double = self.value as? Double {
integer = Int(double)
} else {
integer = self.value as? Int
}
return integer
}
public var date: Date? {
guard let timestamp: TimeInterval = self.double else {
return nil
}
return Date(timeIntervalSince1970: timestamp)
}
public var array: [String]? {
if let array = value as? [String] {
return array
}
if let value = self.string {
return [value]
}
return nil
}
}
<file_sep>/Tests/AuthenticationKitTests/AuthenticationKitTests.swift
//
// OIDAuthorizationServiceTests.swift
// OIDAuthenticationTests
//
// Created by <NAME> on 23/09/2019.
//
@testable import AuthenticationKit
import XCTest
final class AuthenticationKitTests: XCTestCase {
func test() { }
}
extension AuthenticationKitTests {
static var allTests = [
("test", test)
]
}
<file_sep>/Tests/LinuxMain.swift
import XCTest
import AuthenticationKitTests
var tests = [XCTestCaseEntry]()
tests += AuthenticationKitTests.allTests()
XCTMain(tests)
<file_sep>/Sources/AuthenticationKit/AuthenticationService.swift
//
// AuthenticationService.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import AppAuth
import Combine
import Foundation
public final class AuthenticationService {
private static var currentAuthorizationFlow: OIDExternalUserAgentSession?
public init() { }
public func signIn(configuration: OIDProviderConfigurationRepresentable, redirectURL: URL,
loginHint: String? = nil) -> AnyPublisher<AuthState, Error> {
let providerConfiguration = configuration.oidProviderConfigurationValue()
return OIDAuthorizationService.discoverConfigurationPublisher(forDiscoveryURL: providerConfiguration.wellKnownEndpoint)
.tryMap { serviceConfiguration -> OIDAuthorizationRequest in
guard let serviceConfiguration = serviceConfiguration else {
throw AuthenticationError.noServiceConfiguration
}
return OIDAuthorizationRequest(configuration: serviceConfiguration,
providerConfiguration: providerConfiguration, loginHint: loginHint,
redirectURL: redirectURL)
}
.flatMap { Self.authStatePublisher(byPresenting: $0) }
.tryMap { authState -> AuthState in
guard let authState = authState else {
throw AuthenticationError.noAuthState
}
return AuthState(state: authState)
}
.eraseToAnyPublisher()
}
}
extension AuthenticationService {
private static func authStatePublisher(byPresenting request: OIDAuthorizationRequest) -> AnyPublisher<OIDAuthState?, Error> {
Future<OIDAuthState?, Error> { promise in
let rootViewController = UIApplication.shared.windows.first!.rootViewController!
Self.currentAuthorizationFlow = OIDAuthState.authState(byPresenting: request, presenting: rootViewController) { authState, error in
if let error = error {
promise(.failure(error))
Self.currentAuthorizationFlow = nil
return
}
promise(.success(authState))
Self.currentAuthorizationFlow = nil
}
}
.eraseToAnyPublisher()
}
}
<file_sep>/Sources/AuthenticationKit/AuthenticationError.swift
//
// AuthenticationError.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
public enum AuthenticationError: Error {
case noServiceConfiguration
case noAuthState
case cannotRefreshToken(error: Error)
}
<file_sep>/Sources/AuthenticationKit/Extensions/OIDAuthState+Combine.swift
//
// OIDAuthState.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import AppAuth
import Combine
import Foundation
extension OIDAuthState {
func performActionPublisher() -> AnyPublisher<(String?, String?), Error> {
Future<(String?, String?), Error> { promise in
self.performAction { accessToken, idToken, error in
if let error = error {
promise(.failure(error))
return
}
promise(.success((accessToken, idToken)))
}
}
.eraseToAnyPublisher()
}
}
<file_sep>/Sources/AuthenticationKit/Extensions/String+Base64.swift
//
// String+Base64.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import Foundation
extension String {
func base64UrlDecoded() -> Data? {
var base64 = self
.replacingOccurrences(of: "-", with: "+")
.replacingOccurrences(of: "_", with: "/")
let length = Double(base64.lengthOfBytes(using: .utf8))
let requiredLength = 4 * ceil(length / 4.0)
let paddingLength = requiredLength - length
if paddingLength > 0 {
let padding = "".padding(toLength: Int(paddingLength), withPad: "=", startingAt: 0)
base64 += padding
}
return Data(base64Encoded: base64, options: .ignoreUnknownCharacters)
}
}
<file_sep>/Sources/AuthenticationKit/Models/OIDProviderConfiguration.swift
//
// OIDProviderConfiguration.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import Foundation
public struct OIDProviderConfiguration {
public let wellKnownEndpoint: URL
public let clientID: String
public let additionalScopes: Set<String>
public let additionalParameters: [String: String]
public init(wellKnownEndpoint: URL, clientID: String, additionalScopes: Set<String> = [],
additionalParameters: [String: String] = [:]) {
self.wellKnownEndpoint = wellKnownEndpoint
self.clientID = clientID
self.additionalScopes = additionalScopes
self.additionalParameters = additionalParameters
}
}
extension OIDProviderConfiguration: Equatable { }
public protocol OIDProviderConfigurationRepresentable {
func oidProviderConfigurationValue() -> OIDProviderConfiguration
}
extension OIDProviderConfiguration: OIDProviderConfigurationRepresentable {
public func oidProviderConfigurationValue() -> OIDProviderConfiguration {
self
}
}
<file_sep>/Sources/AuthenticationKit/Models/IdentityProviderType.swift
//
// IdentityProviderType.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import Foundation
public enum IdentityProviderType {
case azureAD
case azureADB2C
case google
case other
}
extension IdentityProviderType {
init(wellKnownEndpoint: URL) {
if wellKnownEndpoint.absoluteString.starts(with: WellKnownEndpointPrefix.azureADB2C) {
self = .azureADB2C
return
}
if
let components = URLComponents(url: wellKnownEndpoint, resolvingAgainstBaseURL: false),
let host = components.host,
host.hasSuffix(".\(WellKnownEndpointPrefix.azureADB2CDomain)")
{
self = .azureADB2C
return
}
if wellKnownEndpoint.absoluteString.starts(with: WellKnownEndpointPrefix.azureAD) {
self = .azureAD
return
}
if wellKnownEndpoint.absoluteString == WellKnownEndpointPrefix.google {
self = .google
return
}
self = .other
}
private enum WellKnownEndpointPrefix {
static let azureAD = "https://login.microsoftonline.com/"
static let azureADB2C = "https://login.microsoftonline.com/tfp/"
static let azureADB2CDomain = "b2clogin.com"
static let google = "https://accounts.google.com/.well-known/openid-configuration"
}
}
<file_sep>/Sources/AuthenticationKit/Models/JWT.swift
//
// JWT.swift
// AuthenticationKit
//
// Created by <NAME> on 25/06/2020.
//
import Foundation
public struct JWT {
private static let expireTimeWindow: TimeInterval = (5 * 60) // 5 minutes
public let header: [String: Any]
public let body: [String: Any]
public let signature: String?
public let rawValue: String
public init(jwt: String) throws {
let parts = jwt.components(separatedBy: ".")
guard parts.count == 3 else {
throw JWTError.invalidPartCount(jwt, parts.count)
}
self.header = try JWT.decodeJWTPart(parts[0])
self.body = try JWT.decodeJWTPart(parts[1])
self.signature = parts[2]
self.rawValue = jwt
}
private static func decodeJWTPart(_ value: String) throws -> [String: Any] {
guard let bodyData = value.base64UrlDecoded() else {
throw JWTError.invalidBase64Url(value)
}
guard
let json = try? JSONSerialization.jsonObject(with: bodyData, options: []),
let payload = json as? [String: Any]
else {
throw JWTError.invalidJSON(value)
}
return payload
}
public init(data: Data) throws {
guard let jwt = String(data: data, encoding: .utf8) else {
throw JWTError.invalidData
}
try self.init(jwt: jwt)
}
}
extension JWT {
init?(fromAccessToken accessToken: String?, or idToken: String?) {
if let accessToken = accessToken, let jwt = JWT(rawValue: accessToken) {
self = jwt
return
}
if let idToken = idToken, let jwt = JWT(rawValue: idToken) {
self = jwt
return
}
return nil
}
}
extension JWT {
public var isExpired: Bool {
guard let expiresAt = expiresAt else {
return true
}
return expiresAt.timeIntervalSinceNow < Self.expireTimeWindow
}
public var shouldRenewBy: Date {
guard let expiresAt = expiresAt else {
return Date()
}
return expiresAt.addingTimeInterval(-Self.expireTimeWindow)
}
public var shouldRenew: Bool {
return shouldRenewBy.timeIntervalSinceNow < 0
}
}
extension JWT: RawRepresentable {
public typealias RawValue = String
public init?(rawValue: String) {
try? self.init(jwt: rawValue)
}
}
extension JWT: CustomStringConvertible {
public var description: String {
rawValue
}
}
public enum JWTError: LocalizedError {
case invalidData
case invalidBase64Url(String)
case invalidJSON(String)
case invalidPartCount(String, Int)
}
extension JWTError {
public var localizedDescription: String {
switch self {
case .invalidData:
return NSLocalizedString("Malformed jwt token", comment: "Malformed jwt token")
case .invalidJSON(let value):
return NSLocalizedString("Malformed jwt token, failed to parse JSON value from base64Url \(value)",
comment: "Invalid JSON value inside base64Url")
case .invalidPartCount(let jwt, let parts):
return NSLocalizedString("Malformed jwt token \(jwt) has \(parts) parts when it should have 3 parts",
comment: "Invalid amount of jwt parts")
case .invalidBase64Url(let value):
return NSLocalizedString("Malformed jwt token, failed to decode base64Url value \(value)",
comment: "Invalid JWT token base64Url value")
}
}
}
| fa39bc1412910eef87e5c6eb379e672423b74648 | [
"Swift"
] | 15 | Swift | adamayoung/AuthenticationKit | b2cdd1b70c3cde3a2496014150dfcf88d633af47 | 12676ee38de32af907f37768cea2372a69e48a80 |
refs/heads/master | <file_sep><?php
namespace Ogilo\PhoneBook\Console;
use Illuminate\Console\Command;
use Ogilo\PhoneBook\Models\Contact;
class PhoneBookCommand extends Command
{
/**
* The name and signature of the console command.
*
* @var string
*/
protected $signature = 'phonebook {--fix}';
/**
* The console command description.
*
* @var string
*/
protected $description = 'PhoneBook console toolset';
/**
* Create a new command instance.
*
* @return void
*/
public function __construct()
{
parent::__construct();
}
/**
* Execute the console command.
*
* @return mixed
*/
public function handle()
{
if($this->option('fix')){
$start = new \DateTime();
$this->comment('[ '.$start->format('d-m-Y H:i:s').' ] Started cleaning contact names');
$contacts = Contact::all();
$count = false;
$counter = 0;
$bar = $this->output->createProgressBar(count($contacts));
foreach ($contacts as $key => $contact) {
$display_name = explode(" ",$contact->display_name);
foreach ($display_name as $key => $value) {
$display_name[$key] = trim($value);
}
$first_name = trim($contact->first_name);
$last_name = trim($contact->last_name);
if (!empty($first_name) && !empty($display_name[1])) {
if (strlen($first_name) > strlen($display_name[1])) {
$display_name[1] = $first_name;
}elseif(strlen($display_name[1]) > strlen($first_name)){
$first_name = $display_name[1];
}
$count = true
}
if (!empty($last_name) && !empty($display_name[0])) {
if (strlen($last_name) > strlen($display_name[0])) {
$display_name[0] = $last_name;
}elseif(strlen($display_name[0]) > strlen($last_name)){
$last_name = $display_name[0];
}
$count = true
}
$contact->first_name = $first_name;
$contact->last_name = $last_name;
$contact->display_name = implode(" ",$display_name);
$contact->save();
if($count){
$counter++;
$count = false;
}
$bar->advance();
}
$bar->finish();
$stop = new \DateTime();
$duration = $stop->diff($start);
$this->comment('[ '.$stop->format('d-m-Y H:i:s').' ] Finished cleaning '.$count.'contact names in '.$duration->format('%I Minute(s) %S Second(s)'));
}
}
}
<file_sep><?php
namespace Ogilo\PhoneBook;
use Illuminate\Support\ServiceProvider;
use Ogilo\PhoneBook\Console\PhoneBookCommand;
/**
*
*/
class PhoneBookServiceProvider extends ServiceProvider
{
protected $commands = [
'Ogilo\PhoneBook\Console\InstallComand'
];
function register()
{
// print(config('app.name').' in register()');
$this->app->bind('phonebook',function($app){
return new PhoneBook;
});
}
public function boot()
{
config(['admin.menu.admin-phonebook'=>'PhoneBook']);
if ($this->app->runningInConsole()) {
$this->commands([
PhoneBookCommand::class,
// UpdateCommand::class
]);
}
require_once(__DIR__.'/Support/helpers.php');
$this->loadRoutesFrom(__DIR__.'/../routes/web.php');
$this->loadRoutesFrom(__DIR__.'/../routes/api.php');
$this->loadViewsFrom(__DIR__.'/../resources/views','phonebook');
$this->loadMigrationsFrom(__DIR__.'/../database/migrations');
$this->publishes([
__DIR__.'/../database/seeds' => database_path('seeds/vendor/phonebook'),
], 'phonebook-database');
$this->publishes([
__DIR__.'/../public/img' => public_path('vendor/phonebook/img'),
__DIR__.'/../public/css' => public_path('vendor/phonebook/css'),
__DIR__.'/../public/js' => public_path('vendor/phonebook/js'),
__DIR__.'/../config/phonebook.php' => config_path(''),
], 'phonebook-public');
$this->publishes([
__DIR__.'/../resources/views'=>resource_path('views/vendor/phonebook')
],'phonebook-views');
}
}
<file_sep><?php
Route::group(['as'=>'admin','prefix'=>'admin','middleware'=>'web','namespace'=>'Ogilo\PhoneBook\Http\Controllers'],function(){
Route::group(['as'=>'-phonebook','prefix'=>'phonebook','middleware'=>'auth:admin'],function(){
Route::get('',['as'=>'','uses'=>'PhoneBookController@getDashboard']);
Route::post('upload',['as'=>'-upload','uses'=>'PhoneBookController@postUpload']);
Route::group(['as'=>'-contacts','prefix'=>'contacts','middleware'=>'auth:admin'],function(){
Route::get('',['as'=>'','uses'=>'ContactController@getContacts']);
Route::post('vcard',['as'=>'-vcard','uses'=>'ContactController@postVcard']);
Route::get('delete/{id}',['as'=>'-delete','uses'=>'ContactController@postDelete']);
Route::get('view/{id}',['as'=>'-view','uses'=>'ContactController@getContact']);
Route::post('add',['as'=>'-add','uses'=>'ContactController@postAdd']);
});
});
});
<file_sep><?php
namespace Ogilo\PhoneBook\Models;
use Illuminate\Database\Eloquent\Model;
class Telephone extends Model
{
public function contact()
{
return $this->belongsTo(Contact::class);
}
public function getValueAttribute($value)
{
return clean_isdn($value);
}
}
<file_sep><?php
namespace Ogilo\PhoneBook\Http\Controllers;
use App\Http\Controllers\Controller;
use Illuminate\Http\Request;
use Ogilo\PhoneBook\Models\Contact;
use Ogilo\PhoneBook\Models\Telephone;
use Ogilo\PhoneBook\Models\Email;
use Ogilo\PhoneBook\Models\Address;
use Validator;
use Auth;
class PhoneBookController extends Controller
{
function __construct(){
$this->page = new \Ogilo\AdminMd\Models\Page;
}
/**
* Display a listing of the resource.
*
* @return \Illuminate\Http\Response
*/
public function getDashboard()
{
$contacts = Contact::with('telephones')->orderBy('first_name','ASC')->get();
// dump($contacts);
return view('phonebook::dashboard', compact('contacts'));
}
public function postUpload(Request $request)
{
$validator = Validator::make($request->all(),[
'file'=>'required|file'
]);
if ($validator->fails()) {
return redirect()
->back()
->withErrors($validator)
->with('global-warning','Your file failed validation. Please check and try again');
}
$file = $request->file('file');
$ext = $file->guessClientExtension();
// dd($ext);
if ($ext == 'csv') {
$str = file_get_contents($file->getRealPath());
$contacts = preg_split("/[\n]/", $str);
$headers = explode(', ', array_slice($contacts, 0,1)[0]);
// dd($headers);
$contacts = array_slice($contacts, 1,count($contacts));
foreach ($contacts as $key => $value) {
try {
if($value){
$row = str_getcsv($value);
if(!(empty($row[0]) && empty($row[1]) && empty($row[2]))){
$contact = Contact::where('first_name',$row[0] ?? '')
->where('last_name',$row[1] ?? '')
->where('display_name',$row[2] ?? '')
->first();
// dd(compact('row','headers'));
if(is_null($contact)){
$contact = new Contact;
$first_name = "";
if(empty($row[0])){
$n = explode(' ', trim(trim($row[2],'.')));
$first_name = $n[array_key_first($n)];
}else{
$first_name = $row[0];
}
$contact->first_name = $first_name;
$last_name = "";
if(empty($row[1])){
if(isset($row[2])){
$n = explode(' ', trim(trim($row[2],'.')));
$last_name = array_key_last($n)==1 ? $n[array_key_last($n)] : '';
}
}else{
$last_name = $row[1];
}
$contact->last_name = $last_name;
$contact->display_name = isset($row[2]) && !empty($row[2]) ? $row[2] : trim($row[0].' '. (isset($row[1]) ? $row[1] : ''));
$contact->save();
}
if(isset($row[7]) && !empty($row[7])){
$tel = Telephone::where('value',clean_isdn(str_replace('-','',$row[7])))->get();
if($tel->count() === 0){
$telephone = new Telephone;
$telephone->value = clean_isdn(str_replace('-','',$row[7]));
$telephone->type = 'Work Phone';
$contact->telephones()->save($telephone);
}
}
if(isset($row[8]) && !empty($row[8])){
$tel = Telephone::where('value',clean_isdn(str_replace('-','',$row[8])))->get();
if($tel->count() === 0){
$telephone = new Telephone;
$telephone->value = clean_isdn(str_replace('-','',$row[8]));
$telephone->type = 'Home Phone';
$contact->telephones()->save($telephone);
}
}
if(isset($row[11]) && !empty($row[11])){
$tel = Telephone::where('value',clean_isdn(str_replace('-','',$row[11])))->get();
if($tel->count() === 0){
$telephone = new Telephone;
$telephone->value = clean_isdn(str_replace('-','',$row[11]));
$telephone->type = 'Mobile Number';
$contact->telephones()->save($telephone);
}
}
}
}
} catch (Exception $e) {
dump($e);
}
// if($key == 199)
// break;
}
} elseif($ext=='vcard') {
$str = file_get_contents($file->getRealPath());
$contacts = preg_split("/(END:VCARD)/", preg_replace("/(BEGIN:VCARD\n)/","",$str));
// dd($contacts);
foreach ($contacts as $key => $value) {
try {
if($value){
$row = preg_split("/[\n]/", $value);
$tels = array_values(preg_grep("/^TEL:*/i", $row));
$emails = preg_grep("/^EMAIL:*/i", $row);
$addresses = preg_grep("/^ADR;*/i", $row);
$ar_display_name = array_values(preg_grep("/^FN:*/i", $row));
$display_name = ltrim(isset($ar_display_name[0]) ? $ar_display_name[0] : '',"FN:");
$names = array_values(preg_grep("/^N:*/i", $row));
$names = preg_split("/[;]/",ltrim(current($names),"N:"));
// dd($names);
$pt = preg_split("/PHOTO;/",$value);
$photo = isset($pt[1]) ? $pt[1] : '';
if(!(empty($names[0]) && empty($names[1]) && empty($display_name))){
$first_name = "";
if(empty($names[0])){
$n = explode(' ', trim(trim($display_name,'.')));
$first_name = $n[array_key_first($n)];
}else{
$first_name = $names[0];
}
$last_name = "";
if(empty($names[1])){
if(isset($display_name)){
$n = explode(' ', trim(trim($display_name,'.')));
$last_name = array_key_last($n)==1 ? $n[array_key_last($n)] : '';
}
}else{
$last_name = $names[1];
}
$contact = Contact::where('first_name',$first_name)
->where('last_name',$last_name)
->where('display_name',$display_name)
->first();
// dd(compact('row','headers'));
if(is_null($contact)){
$contact = new Contact;
$contact->first_name = $first_name;
$contact->last_name = $last_name;
$contact->display_name = isset($display_name) && !empty($display_name) ? $display_name : trim($names[0].' '. (isset($names[1]) ? $names[1] : ''));
$contact->photo = $photo;
$contact->save();
}
foreach ($tels as $key => $item) {
$tl = preg_split("/[:]/",ltrim($item,"TEL;"));
// dd($tl);
$phone_no = $tl[1];
$type = $tl[0];
if(isset($phone_no) && !empty($type)){
$tel = Telephone::where('value',clean_isdn($phone_no))->get();
if($tel->count() === 0){
$telephone = new Telephone;
$telephone->value = clean_isdn($phone_no);
$telephone->type = $type;
$contact->telephones()->save($telephone);
}
}
}
foreach ($emails as $key => $item) {
$m = preg_split("/[:]/",$item);
$mail = $m[1];
$type = $m[0];
if(isset($mail) && !empty($type)){
$email = Email::where('value',$mail)->get();
if($email->count() === 0){
$email = new Email;
$email->value = $mail;
$email->type = $type;
$contact->emails()->save($email);
}
}
}
foreach ($addresses as $key => $item) {
$m = preg_split("/[:]/",$item);
$adr = $m[1];
$type = $m[0];
if(isset($adr) && !empty($type)){
$address = Address::where('value',$adr)->get();
if($address->count() === 0){
$address = new Address;
$address->value = $adr;
$address->type = $type;
$contact->addresses()->save($address);
}
}
}
}
}
} catch (Exception $e) {
dump($e);
}
// if($key == 199)
// break;
}
}
return redirect()
->back()
->with('global-success','Contacts Upload complete');
// dd($contacts);
}
}
<file_sep><?php
namespace Ogilo\PhoneBook\Models;
use Illuminate\Database\Eloquent\Model;
class Contact extends Model
{
public function emails()
{
return $this->hasMany(Email::class);
}
public function telephones()
{
return $this->hasMany(Telephone::class);
}
public function addresses()
{
return $this->hasMany(Address::class);
}
public function getFirstNameAttribute($value)
{
return ucwords(strtolower($value));
}
public function getLastNameAttribute($value)
{
return ucwords(strtolower($value));
}
public function getDisplayNameAttribute($value)
{
return ucwords(strtolower($value));
}
}
<file_sep><?php
namespace Ogilo\PhoneBook\Http\Controllers;
use App\Http\Controllers\Controller;
use Illuminate\Http\Request;
use Ogilo\PhoneBook\Models\Contact;
use JeroenDesloovere\VCard\VCard;
use Validator;
use Auth;
use Storage;
class ContactController extends Controller
{
function __construct(){
$this->page = new \Ogilo\AdminMd\Models\Page;
}
/**
* Display a listing of the resource.
*
* @return \Illuminate\Http\Response
*/
public function getContacts(Request $request)
{
$contacts = $request->has('page') ? Contact::has('telephones')->orderBy('display_name')->paginate() : Contact::has('telephones')->orderBy('display_name')->paginate(9999);
return view('phonebook::contacts.index',compact('contacts'));
}
/**
* Display a listing of the resource.
*
* @return \Illuminate\Http\Response
*/
public function postAdd(Request $request)
{
dd($request->all());
$contacts = Contact::all();
return view('phonebook::contacts.index',compact('contacts'));
}
public function postVcard(Request $request)
{
$validator = Validator::make($request->all(),[
'contact'=>'required'
]);
if ($validator->fails()) {
$errors = $validator->errors()->all();
return redirect()
->back()
->withErrors($validator)
->with('global-warning','<h4>You have a prloblem. Please check and try again</h4>'.make_html_list($errors,'ul'));
}
$contact = $request->contact;
$contacts = Contact::has('telephones')->with('telephones','emails','addresses')->whereIn('id',$contact)->orderBy('display_name')->get();
$contents = '';
$headers = null;
foreach ($contacts as $key => $contact) {
$vcard = new VCard();
$vcard->addName($contact->first_name,$contact->last_name);
foreach ($contact->telephones as $key => $tel) {
$vcard->addPhoneNumber($tel->value,$tel->type);
}
foreach ($contact->emails as $key => $email) {
$vcard->addEmail($email->value);
}
$contents .= $vcard->getOutput();
// return $vcard->download();
// dd($contents);
$headers = $vcard->getHeaders(true);
}
// $contents = view('phonebook::vcard.index',compact('contacts'));
Storage::put('contacts.vcf', $contents);
return response()->download(storage_path('app/contacts.vcf'));
}
public function postDelete($id)
{
$validator = Validator::make(compact('id'),[
'id'=>'required|exists:contacts'
]);
if ($validator->fails()) {
$errors = $validator->errors()->all();
// dd($errors);
return redirect()
->back()
->withErrors($validator)
->with('global-warning','<h4>Validation error</h4>'.make_html_list($errors,'ul'));
}
$contact = Contact::find($id);
$contact->telephones()->delete();
$contact->emails()->delete();
$contact->addresses()->delete();
$contact->delete();
return redirect()
->back()
->with('global-success','Contact Deleted');
}
}
| f01700262eb68445ef3d13bc635f6da51da33261 | [
"PHP"
] | 7 | PHP | gogilo2003/phonebook | 02b38cf1e6f3158f5f811b634c848daabef0c4e8 | f3d3f17bf6df4a0133343e2d3ff4f99e7461389b |
refs/heads/master | <file_sep>from random import *
import time
race_words=["awesome.","cool.","good choice.","really.","come on.","horible choice."]
class_words=["boring.","ok.","not bad.","soso.","good.","meh."]
print("Welcome to troll")
print("Choose a race")
print("1: Dwarven")
print("2: Elven")
print("3: Human")
print("4: Gnomes")
monster = ({"attack":1,"defence":1,"damage":2,"hp":3,"armor":8})
race = input()
if race == "1":
print("The Dwarven,",choice(race_words))
race_dict = ({"defence":1,"attack":1,"damage":2,"hp":23,"armor":5})
if race == "2":
print("The Elven,",choice(race_words))
race_dict = ({"armor":2})
if race == "3":
print("The Humans,",choice(race_words))
if race == "4":
print("The Gnomes,",choice(race_words))
time.sleep(1)
print("Choose a class")
print("1: Fighter")
print("2: Rogue")
print("3: Bard")
print("4: Ranger")
_class = input()
if _class == "1":
print("A Fighter,",choice(class_words))
if _class == "2":
print("A Rogue,",choice(class_words))
if _class == "3":
print("A Bard,",choice(class_words))
if _class == "4":
print("A Ranger,",choice(class_words))
time.sleep(1)
def player_attack():
monster["hp"]-= race_dict["damage"]
monster["hp"]+=monster["defence"]
print(monster["hp"])
def monster_attack():
race_dict["hp"]-=monster["damage"]
race_dict["hp"]+=race_dict["defence"]
print(race_dict["hp"])
def battle():
while race_dict["hp"] > 0 and monster["hp"] > 0:
player_attack()
monster_attack()
time.sleep(1)
battle()
if race_dict["hp"] > monster["hp"]:
print("Player wins")
else:
print("Monster wins") | aea6fc5f39ef551c912c3085902ccdf91c5ca623 | [
"Python"
] | 1 | Python | ollieokp/Troll | 1e672ff78bf56c4db178c59bd294389f614c9526 | 6fc078b52734b3f2a937d11fec82425b5b78b3e2 |
refs/heads/master | <repo_name>observo/MageOAuth<file_sep>/examples/magento.php
<?php
use OAuth\OAuth1\Service\Magento;
use OAuth\Common\Storage\Session;
use OAuth\Common\Consumer\Credentials;
require_once __DIR__ . '/bootstrap.php';
$storage = new Session();
$credentials = new Credentials(
$servicesCredentials['magento']['key'],
$servicesCredentials['magento']['secret'],
$currentUri->getAbsoluteUri()
);
$bbService = $serviceFactory->createService('Magento', $credentials, $storage);
print_r($bbService);
if (!empty($_GET['oauth_token'])) {
$token = $storage->retrieveAccessToken('Magento');
// This was a callback request from BitBucket, get the token
$bbService->requestAccessToken(
$_GET['oauth_token'],
$_GET['oauth_verifier'],
$token->getRequestTokenSecret()
);
// Send a request now that we have access token
$result = json_decode($bbService->request('user/repositories'));
echo('The first repo in the list is ' . $result[0]->name);
} elseif (!empty($_GET['go']) && $_GET['go'] === 'go') {
// extra request needed for oauth1 to request a request token :-)
$token = $bbService->requestRequestToken();
$url = $bbService->getAuthorizationUri(array('oauth_token' => $token->getRequestToken()));
header('Location: ' . $url);
} else {
$url = $currentUri->getRelativeUri() . '?go=go';
echo "<a href='$url'>Login with Magento!</a>";
}
| 63baac30376ef1a8c11041698da99b7dc8eab409 | [
"PHP"
] | 1 | PHP | observo/MageOAuth | 33ae80f8af2c8733e3305a384c0c045a149a9a3b | 257f45c6d70f7ae75488a83d9f78489b4f77bbc6 |
refs/heads/master | <repo_name>lukesoguero/coin-jar-counter<file_sep>/app/src/main/java/com/example/android/coinjarcounter/MainActivity.java
package com.example.android.coinjarcounter;
import android.app.Activity;
import android.app.AlertDialog;
import android.content.DialogInterface;
import android.content.Intent;
import android.os.Bundle;
import android.support.design.widget.FloatingActionButton;
import android.support.design.widget.Snackbar;
import android.support.v7.app.AppCompatActivity;
import android.support.v7.widget.Toolbar;
import android.view.View;
import android.view.Menu;
import android.view.MenuItem;
import android.widget.EditText;
public class MainActivity extends AppCompatActivity {
public static final String JAR_NAME_EXTRA = "com.example.android.coinjarcounter.Jar Name";
public static final String JAR_ID_EXTRA = "com.example.android.coinjarcounter.Jar ID";
public static final String JAR_TOTAL_EXTRA = "com.example.android.coinjarcounter.Jar Total";
public static final String JAR_CODE_EXTRA = "com.example.android.coinjarcounter.Jar Code";
@Override
protected void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.activity_main);
Toolbar toolbar = (Toolbar) findViewById(R.id.toolbar);
setSupportActionBar(toolbar);
FloatingActionButton fab = (FloatingActionButton) findViewById(R.id.fab);
fab.setOnClickListener(new View.OnClickListener() {
@Override
public void onClick(View view) {
AlertDialog.Builder alert = new AlertDialog.Builder(MainActivity.this);
alert.setTitle("Name Jar");
alert.setMessage("You may rename later");
// Set an EditText view to get user input
final EditText input = new EditText(MainActivity.this);
alert.setView(input);
alert.setPositiveButton("Ok", new DialogInterface.OnClickListener() {
public void onClick(DialogInterface dialog, int whichButton) {
String jarName = input.getText().toString();
Intent intent = new Intent(MainActivity.this, JarActivity.class);
intent.putExtra(MainActivity.JAR_NAME_EXTRA, jarName);
intent.putExtra(MainActivity.JAR_CODE_EXTRA, 0);
startActivity(intent);
}
});
alert.setNegativeButton("Cancel", new DialogInterface.OnClickListener() {
public void onClick(DialogInterface dialog, int whichButton) {
// Canceled.
}
});
alert.show();
}
});
}
@Override
public boolean onCreateOptionsMenu(Menu menu) {
// Inflate the menu; this adds items to the action bar if it is present.
getMenuInflater().inflate(R.menu.menu_main, menu);
return true;
}
@Override
public boolean onOptionsItemSelected(MenuItem item) {
// Handle action bar item clicks here. The action bar will
// automatically handle clicks on the Home/Up button, so long
// as you specify a parent activity in AndroidManifest.xml.
int id = item.getItemId();
//noinspection SimplifiableIfStatement
if (id == R.id.action_settings) {
return true;
}
return super.onOptionsItemSelected(item);
}
}
<file_sep>/app/src/main/java/com/example/android/coinjarcounter/JarDbAdapter.java
package com.example.android.coinjarcounter;
import android.content.ContentValues;
import android.content.Context;
import android.database.Cursor;
import android.database.sqlite.SQLiteDatabase;
import android.database.sqlite.SQLiteOpenHelper;
import java.util.ArrayList;
/**
* Created by lukes_000 on 8/6/2016.
*/
public class JarDbAdapter {
private static final String DATABASE_NAME = "jar.db";
private static final int DATABASE_VERSION = 1;
public static final String JAR_TABLE = "jar";
public static final String COLUMN_ID = "_id";
public static final String COLUMN_TOTAL = "total";
public static final String COLUMN_NAME = "name";
private String[] allColumns = { COLUMN_ID, COLUMN_TOTAL, COLUMN_NAME };
public static final String CREATE_TABLE_JAR = "create table " + JAR_TABLE + " ( "
+ COLUMN_ID + " integer primary key autoincrement, "
+ COLUMN_TOTAL + " double not null, "
+ COLUMN_NAME + " text not null " + ")";
private SQLiteDatabase sqlDB;
private Context context;
private JarDbHelper jarDbHelper;
public JarDbAdapter(Context ctx){
context = ctx;
}
public JarDbAdapter open() throws android.database.SQLException {
jarDbHelper = new JarDbHelper(context);
sqlDB = jarDbHelper.getWritableDatabase();
return this;
}
public void close() {
jarDbHelper.close();
}
public Jar createJar(String name, double total) {
ContentValues values = new ContentValues();
values.put(COLUMN_NAME, name);
values.put(COLUMN_TOTAL, total);
long insertId = sqlDB.insert(JAR_TABLE, null, values);
Cursor cursor = sqlDB.query(JAR_TABLE, allColumns, COLUMN_ID + " = " + insertId, null, null, null, null);
cursor.moveToFirst();
Jar newJar = cursorToJar(cursor);
cursor.close();
return newJar;
}
public long updateJar(long idToUpdate, double newTotal) {
ContentValues values = new ContentValues();
values.put(COLUMN_TOTAL, newTotal);
return sqlDB.update(JAR_TABLE, values, COLUMN_ID + " = " + idToUpdate, null);
}
public long deleteJar(long idToDelete) {
return sqlDB.delete(JAR_TABLE, COLUMN_ID + " = " + idToDelete, null);
}
public ArrayList<Jar> getAllJars(){
ArrayList<Jar> jars = new ArrayList<Jar>();
Cursor cursor = sqlDB.query(JAR_TABLE, allColumns, null, null, null, null, null );
for(cursor.moveToLast(); !cursor.isBeforeFirst(); cursor.moveToPrevious()) {
Jar jar = cursorToJar(cursor);
jars.add(jar);
}
cursor.close();
return jars;
}
private Jar cursorToJar(Cursor cursor) {
Jar newJar = new Jar( cursor.getString(2), cursor.getDouble(1), cursor.getLong(0));
return newJar;
}
private static class JarDbHelper extends SQLiteOpenHelper{
JarDbHelper(Context ctx) {
super(ctx, DATABASE_NAME, null, DATABASE_VERSION);
}
@Override
public void onCreate(SQLiteDatabase db){
db.execSQL(CREATE_TABLE_JAR);
}
@Override
public void onUpgrade(SQLiteDatabase db, int oldVersion, int newVersion) {
db.execSQL("DROP TABLE IF EXISTS " + JAR_TABLE);
onCreate(db);
}
}
}
<file_sep>/app/src/main/java/com/example/android/coinjarcounter/JarAdapter.java
package com.example.android.coinjarcounter;
import android.app.Activity;
import android.view.LayoutInflater;
import android.view.View;
import android.view.ViewGroup;
import android.widget.ArrayAdapter;
import android.widget.TextView;
import java.text.NumberFormat;
import java.util.ArrayList;
/**
* Created by lukes_000 on 8/2/2016.
*/
public class JarAdapter extends ArrayAdapter<Jar> {
public JarAdapter(Activity context, ArrayList<Jar> jars) {
super(context, 0, jars);
}
@Override
public View getView(int position, View convertView, ViewGroup parent) {
View listItemView = convertView;
if (listItemView == null) {
listItemView = LayoutInflater.from(getContext()).inflate(
R.layout.jar_list_item, parent, false);
}
Jar jar = getItem(position);
TextView jarName = (TextView) listItemView.findViewById(R.id.jarName);
jarName.setText(jar.getJarName());
TextView total = (TextView) listItemView.findViewById(R.id.total_list_item);
total.setText(NumberFormat.getCurrencyInstance().format(jar.getJarTotal()));
return listItemView;
}
}
| e1d68bf3177ae197b6d293908ab9005c410913ba | [
"Java"
] | 3 | Java | lukesoguero/coin-jar-counter | 2194242ce926173cc06ce09559fbcc1fd3f42d69 | b8a95ca0a55fa32dbfff0bc1eb85d32a456b36e0 |
refs/heads/master | <file_sep>/**
* Created by sorap on 4/7/2016.
*/
import { Mongo } from 'meteor/mongo'
export const Tasks = new Mongo.Collection('tasks'); | 72e7a00616d6b9a3c563f5b457ec3fc5b5571fca | [
"JavaScript"
] | 1 | JavaScript | khongnaw/meteor-1.3-todo-tutorial | b6f81a895cb8cbf657eb8939472031a780d951af | 76c2db32c0b3d3e9f113f4072c159b3e829fc46b |
refs/heads/master | <file_sep>package com.snow.night.googleemarket.manager;
import android.app.ActivityManager;
import java.util.concurrent.BlockingQueue;
import java.util.concurrent.Executor;
import java.util.concurrent.Executors;
import java.util.concurrent.LinkedBlockingDeque;
import java.util.concurrent.RejectedExecutionHandler;
import java.util.concurrent.ThreadFactory;
import java.util.concurrent.ThreadPoolExecutor;
import java.util.concurrent.TimeUnit;
/**
* Created by Administrator on 2016/4/21.
*/
public class ThreadManager {
//懒汉式 单例模式
private static ThreadManager threadManager;
private final ThreadPoolExecutor executor;
private static int corePoolSize = Runtime.getRuntime().availableProcessors()*2+1;
private static int maximumPoolSize = corePoolSize;
//int corePoolSize 核心线程数 一般为 cpu核心数*2+1；
//私有化构造函数,创建静态的实例对象，提供一个静态的获取实例对象方法 双重判空
private ThreadManager(int corePoolSize,int maximumPoolSize){
//通过构造函数创建线程池的类
executor = new ThreadPoolExecutor(corePoolSize,
maximumPoolSize,
10,
TimeUnit.SECONDS,
new LinkedBlockingDeque(),
Executors.defaultThreadFactory(),
new ThreadPoolExecutor.AbortPolicy());
};
public static ThreadManager getInstance(){
//双重判空
if(threadManager ==null){
synchronized (ThreadManager.class){
if(threadManager == null){
threadManager = new ThreadManager(corePoolSize,maximumPoolSize);
}
}
}
return threadManager;
};
/**
* 执行任务的方法 调用线程池中执行任务的方法
* @param task
*/
public void execute (Runnable task){
if(task == null){
return;
}
if(executor != null && !executor.isShutdown()){
executor.execute(task);
}
}
public void cancel(Runnable task){
if(task == null){
return;
}
if(executor != null && !executor.isShutdown()){
executor.getQueue().remove(task);
}
}
}
<file_sep>package com.snow.night.googleemarket.fragment;
import android.os.SystemClock;
import android.view.View;
import com.snow.night.googleemarket.R;
import com.snow.night.googleemarket.base.BaseFragment;
/**
* Created by Administrator on 2016/4/13.
*/
public class GameFragment extends BaseFragment {
@Override
public String getTitle() {
return "游戏";
}
@Override
public View getContentView() {
return null;
}
@Override
public int getContentViewById() {
return R.layout.fragmentbase;
}
@Override
public void initview() {
}
@Override
public void initdata() {
rootview.showFail();
}
@Override
public void initlistener() {
} @Override
protected void onPostExecute(int requestType, Object o) {
switch (requestType){
case REQUEST_INIT_DATA:
break;
}
}
@Override
protected Object doInBackground(int requestType) {
switch (requestType){
case REQUEST_INIT_DATA:
break;
}
return null;
}
}
<file_sep>package com.snow.night.googleemarket.utils;
import android.os.SystemClock;
import android.text.TextUtils;
import com.snow.night.googleemarket.MyApplication;
import com.snow.night.googleemarket.net.HttpHelper;
import java.io.BufferedReader;
import java.io.BufferedWriter;
import java.io.CharArrayWriter;
import java.io.File;
import java.io.FileNotFoundException;
import java.io.FileReader;
import java.io.FileWriter;
import java.io.IOException;
import java.io.UnsupportedEncodingException;
import java.io.Writer;
import java.net.URL;
import java.net.URLEncoder;
import java.util.ArrayList;
import java.util.Collections;
import java.util.HashMap;
import java.util.Set;
/**
* 根据给定的url和params获取json
* Created by Administrator on 2016/4/15.
*/
public class NetUtil {
public static String getjson(String url, HashMap<String, String> params) {
//拼接URl和params
String requestUrl = createRequestUrl(url,params);
String json = getJsonFromLocal(requestUrl);
if(TextUtils.isEmpty(json)){
json = getJsonFromNet(requestUrl);
}else{
LogUtil.e(NetUtil.class,"本地数据");
}
LogUtil.e(NetUtil.class,json);
return json;
}
/**
* 从本地获取缓冲数据
* @param requestUrl
* @return
*/
private static String getJsonFromLocal(String requestUrl) {
File catchfile = getcatchfile(requestUrl);
if(!catchfile.exists())
{
return null;
}
BufferedReader br=null;
try {
br = new BufferedReader(new FileReader(catchfile));
String validTimeString = br.readLine();
long validtime = Long.parseLong(validTimeString);
//缓冲数据在有效期内时 将其读取出来
if(System.currentTimeMillis()<validtime)
{ //将数据读到buffer字符数组中 在将其写入字符内存中
CharArrayWriter writer = new CharArrayWriter();
char[] buffer =new char[2048];
int len;
if((len = br.read(buffer))!= -1){
writer.write(buffer,0,len);
}
return writer.toString();
}
} catch (Exception e) {
e.printStackTrace();
}finally {
IOUtils.close(br);
}
return null;
}
/**
* 根据给定的请求地址从网络获取数据
* @param requestUrl
* @return
*/
private static String getJsonFromNet(String requestUrl) {
HttpHelper.HttpResult httpResult = HttpHelper.get(requestUrl);
if(httpResult!= null){
String json = httpResult.getString();
// saveJson2Local(json,requestUrl);
// LogUtil.e(NetUtil.class ,json);
return json;
}
return null;
}
/**
* 把json数据保存到本地
* @param json
* @param requestUrl
*/
private static void saveJson2Local(String json, String requestUrl) {
if(TextUtils.isEmpty(json)){
return;
}
BufferedWriter bw = null;
try {
File catchfile = getcatchfile(requestUrl);
bw = new BufferedWriter(new FileWriter(catchfile));
long tenMinutes = 10*60*1000;
long validTime = System.currentTimeMillis()+ tenMinutes;
bw.write(String.valueOf(validTime)); //将有效期写入第一行
bw.newLine();
bw.write(json);
bw.flush();
} catch (IOException e) {
e.printStackTrace();
}finally {
IOUtils.close(bw);
}
}
/**
* 用来获取保存json数据的文件
* @param requestUrl
* @return
*/
private static File getcatchfile(String requestUrl) {
String filename;
try {
filename = URLEncoder.encode(requestUrl,"UTF-8"); //防止乱码情况的发生
File file = new File(MyApplication.getContext().getCacheDir(),filename);
return file;
} catch (UnsupportedEncodingException e) {
e.printStackTrace();
}
return null;
}
/**
* 根据给定的url和params 完成请求路径
* @param url
* @param params
* @return
*/
private static String createRequestUrl(String url, HashMap<String, String> params) {
//取出set集合中的keyset键值对
String requesturl;
if(params != null){
Set<String> keySet = params.keySet();
//由于键值对是无序的 但我们的请求路径是有序的 而且保存文件时
// 也需要路径来命名 如果路径名不唯一 将会取不到缓冲数据 将keyset转换成arraylist
ArrayList<String> keys = new ArrayList(keySet);
//然后通过collection工具类对 keys 进行排序
Collections.sort(keys);
//index=0&name=zs&age=45
StringBuffer sb = new StringBuffer();
for (String key: keys) {
sb.append("&").append(key).append("=").append(params.get(key));
}
sb.deleteCharAt(0);
requesturl = url + "?" +sb.toString();
}else{
requesturl= url;
}
return requesturl;
}
}
<file_sep>package com.snow.night.googleemarket.adapter;
import android.support.design.internal.ForegroundLinearLayout;
import android.support.v4.view.PagerAdapter;
import android.view.View;
import android.view.ViewGroup;
import android.widget.ImageView;
import android.widget.TextView;
import com.snow.night.googleemarket.MyApplication;
import com.snow.night.googleemarket.R;
import com.snow.night.googleemarket.net.Urls;
import com.snow.night.googleemarket.utils.LogUtil;
import org.xutils.x;
import java.util.ArrayList;
/**
* Created by Administrator on 2016/4/17.
*/
public class BannerAdapterSelf extends PagerAdapter{
private ArrayList<String> imageUrls ;
private ArrayList<ImageView> picViews = new ArrayList<ImageView>() ;
public BannerAdapterSelf(ArrayList<String> imageUrls) {
this.imageUrls = imageUrls;
for (String imageUrl: imageUrls) {
ImageView imageView = new ImageView(MyApplication.getContext());
imageView.setScaleType(ImageView.ScaleType.FIT_XY);
imageView.setBackgroundResource(R.drawable.ic_default);
picViews.add(imageView);
}
}
@Override
public int getCount() {
return imageUrls.size()*1000*50;
}
@Override
public boolean isViewFromObject(View view, Object object) {
return view == object;
}
@Override
public void destroyItem(ViewGroup container, int position, Object object) {
container.removeView((View) object);
}
@Override
public Object instantiateItem(ViewGroup container, int position) {
position = position% imageUrls.size();
ImageView imageView = picViews.get(position);
String url = Urls.IMAGE + "?name="+imageUrls.get(position);
LogUtil.e(this,url);
x.image().bind(imageView,url);
container.addView(imageView);
return imageView;
}
}
<file_sep>package com.snow.night.googleemarket.base;
import android.support.v7.widget.RecyclerView;
import android.view.View;
import android.view.ViewGroup;
import android.widget.BaseAdapter;
import android.widget.TextView;
import java.util.ArrayList;
/**
* Created by Administrator on 2016/4/14.
*/
public abstract class MyBaseAdapter<T> extends BaseAdapter{
protected ArrayList<T> datas;
public MyBaseAdapter(ArrayList<T> datas) {
this.datas = datas;
}
public ArrayList<T> getData(){
if(datas == null)
{
datas = new ArrayList<T>();
}
return datas;
}
@Override
public int getCount() {
return datas == null ? 0 : datas.size();
}
@Override
public Object getItem(int position) {
return datas.get(position);
}
@Override
public long getItemId(int position) {
return position;
}
public View getView(int position, View convertView, ViewGroup parent) {
Object viewHolder;
if(convertView == null)
{
convertView = View.inflate(parent.getContext(),
getLayoutResId(position),null);
viewHolder = createHolder(convertView,position);
convertView.setTag(viewHolder);
}else{
viewHolder = convertView.getTag();
}
T data =datas.get(position);
showdata(position,viewHolder,data);
return convertView;
}
protected abstract int getLayoutResId(int position);
protected abstract Object createHolder(View convertView, int position);
protected abstract void showdata(int position, Object viewHolder, T data);
}
<file_sep>package com.snow.night.googleemarket.adapter;
import com.snow.night.googleemarket.bean.DownLoadInfo;
import com.snow.night.googleemarket.manager.DownLoadManager;
import android.content.Context;
import android.view.View;
import android.view.ViewGroup;
import android.widget.BaseAdapter;
import android.widget.FrameLayout;
import android.widget.ImageView;
import android.widget.LinearLayout;
import android.widget.RatingBar;
import android.widget.TextView;
import com.snow.night.googleemarket.MyApplication;
import com.snow.night.googleemarket.R;
import com.snow.night.googleemarket.base.MyBaseAdapter;
import com.snow.night.googleemarket.bean.HomeBean;
import com.snow.night.googleemarket.net.Urls;
import com.snow.night.googleemarket.utils.CommonUtils;
import com.snow.night.googleemarket.view.ProgressArc;
import org.xutils.x;
import java.util.ArrayList;
import java.util.Formatter;
/**
* Created by Administrator on 2016/4/14.
*/
public class HomeListAdapter extends MyBaseAdapter<HomeBean.Appinfo>{
private HomeBean.Appinfo downloadhelp;
private ProgressArc progressArc;
public HomeListAdapter(ArrayList<HomeBean.Appinfo> datas) {
super(datas);
}
@Override
public int getLayoutResId(int position) {
return R.layout.item_homefragment_applist;
}
@Override
public Object createHolder(View convertView, int position) {
ViewHolder viewHolder = new ViewHolder();
viewHolder.tv_title = (TextView) convertView.findViewById(R.id.tv_homefragment_item_title);
viewHolder.tv_size = (TextView) convertView.findViewById(R.id.tv_homefragment_item_size);
viewHolder.tv_desc = (TextView) convertView.findViewById(R.id.tv_homefragment_item_desc);
viewHolder.iv_icon= (ImageView) convertView.findViewById(R.id.iv_homefragment_listitem_icon);
viewHolder.rb_rating = (RatingBar) convertView.findViewById(R.id.rb_homefragment_item_rating);
viewHolder.ll_download = (LinearLayout) convertView.findViewById(R.id.ll_homefragment_item_download);
viewHolder.fl_download_logo= (FrameLayout) convertView.findViewById(R.id.fl_download_logo);
viewHolder.tv_progress = (TextView) convertView.findViewById(R.id.tv_download_progress);
progressArc = new ProgressArc(MyApplication.getContext());
progressArc.setArcDiameter(CommonUtils.dip2px(27));
progressArc.setBackgroundResource(R.drawable.ic_download);
progressArc.setProgressColor(R.color.selfblue);
viewHolder.fl_download_logo.addView(progressArc);
viewHolder.pa_progressArcSelf = progressArc;
return viewHolder;
}
@Override
protected void showdata(int position, Object viewHolder, final HomeBean.Appinfo data) {
ViewHolder holder = (ViewHolder) viewHolder;
Context context = ((ViewHolder) viewHolder).tv_title.getContext();
String url = Urls.IMAGE + "?name="+data.getIconUrl();
x.image().bind(((ViewHolder) viewHolder).iv_icon,url);
holder.tv_title.setText(data.getName());
holder.tv_size.setText(android.text.format.Formatter.formatFileSize(context,data.getSize()));
holder.tv_desc.setText(data.getDes());
holder.rb_rating.setRating(data.getStars());
holder.ll_download.setOnClickListener(new View.OnClickListener() {
@Override
public void onClick(View v) {
lldownloadclick(data);
}
});
registDownloadObserver(data,holder,position);
}
/**
* 点击事件的响应方法
* @param data
*/
private void lldownloadclick(HomeBean.Appinfo data) {
DownLoadManager downLoadManager = DownLoadManager.getInstance();
DownLoadInfo downLoadInfo = downLoadManager.getdownloadinfo(data.getId());
if(downLoadInfo == null){
downLoadManager.download(data);
}else{
switch (downLoadInfo.getState()) {
case DownLoadManager.DOWNLOAD_STATE_DOWNLOADING:
case DownLoadManager.DOWNLOAD_STATE_WAITING:
downLoadManager.pause(data);
break;
case DownLoadManager.DOWNLOAD_STATE_PAUSE:
case DownLoadManager.DOWNLOAD_STATE_ERROR:
downLoadManager.download(data);
break;
case DownLoadManager.DOWNLOAD_STATE_SUCCESS:
downLoadManager.install(data);
break;
}
}
}
static class ViewHolder{
TextView tv_title;
TextView tv_size;
TextView tv_desc;
TextView tv_progress;
ImageView iv_icon;
RatingBar rb_rating;
LinearLayout ll_download;
FrameLayout fl_download_logo;
ProgressArc pa_progressArcSelf;
}
/**
* 注册观察者
*/
public void registDownloadObserver(final HomeBean.Appinfo downloaddata, final ViewHolder holder,int position) {
DownLoadManager.getInstance().registObserver(new DownLoadManager.DownLoadObserver() {
@Override
public void onDownLoadinfoChange(DownLoadInfo info) {
if(info.getId().equals(downloaddata.getId())){
//根据状态，更新界面
processState(info,holder);
}
}
});
}
/**
* 根据状态，更新界面
* @param downLoadInfo
*/
private void processState(DownLoadInfo downLoadInfo,ViewHolder holder) {
//progress = 当前下载的大小 / 总大小
float progress = downLoadInfo.getCurrentposition()*1f/downLoadInfo.getSize();
int progressInt = (int) (progress*100);
switch (downLoadInfo.getState()) {
case DownLoadManager.DOWNLOAD_STATE_DOWNLOADING:
//显示进度，显示百分比
//设置ProgressArc的下载style
holder.pa_progressArcSelf.setStyle(ProgressArc.PROGRESS_STYLE_DOWNLOADING);
holder.pa_progressArcSelf.setProgress(progress, true);
holder.pa_progressArcSelf.setBackgroundResource(R.drawable.ic_pause);
holder.tv_progress.setText(progressInt+"%");
break;
case DownLoadManager.DOWNLOAD_STATE_ERROR:
//文字该为重新下载
holder.pa_progressArcSelf.setStyle(ProgressArc.PROGRESS_STYLE_NO_PROGRESS);
holder.pa_progressArcSelf.setBackgroundResource(R.drawable.ic_redownload);
holder.tv_progress.setText("重下");
break;
case DownLoadManager.DOWNLOAD_STATE_PAUSE:
//文字改为 继续下载
holder.pa_progressArcSelf.setStyle(ProgressArc.PROGRESS_STYLE_NO_PROGRESS);
holder.pa_progressArcSelf.setBackgroundResource(R.drawable.ic_resume);
holder.tv_progress.setText("继续");
break;
case DownLoadManager.DOWNLOAD_STATE_SUCCESS:
//文字改为 安装
holder.pa_progressArcSelf.setStyle(ProgressArc.PROGRESS_STYLE_NO_PROGRESS);
holder.pa_progressArcSelf.setBackgroundResource(R.drawable.ic_install);
holder.tv_progress.setText("安装");
break;
case DownLoadManager.DOWNLOAD_STATE_WAITING:
//文字改为 等待
holder.tv_progress.setText("等待");
holder.pa_progressArcSelf.setStyle(ProgressArc.PROGRESS_STYLE_DOWNLOADING);
holder.pa_progressArcSelf.setProgress(progress, true);
holder.pa_progressArcSelf.setBackgroundResource(R.drawable.ic_download);
break;
}
}
}
<file_sep>package com.snow.night.googleemarket.utils;
/**
* Created by Administrator on 2016/4/19.
*/
public interface Keys {
String PACKAGE_NAME ="packagename" ;
}
<file_sep>package com.snow.night.googleemarket.adapter;
import android.view.View;
import android.widget.ImageView;
import android.widget.LinearLayout;
import android.widget.TextView;
import android.widget.Toast;
import com.snow.night.googleemarket.MyApplication;
import com.snow.night.googleemarket.R;
import com.snow.night.googleemarket.base.MyBaseAdapter;
import com.snow.night.googleemarket.bean.CategoryBean;
import com.snow.night.googleemarket.bean.CategoryBean.CategoryInfo;
import com.snow.night.googleemarket.net.Urls;
import org.xutils.x;
import java.util.ArrayList;
/**
* Created by Administrator on 2016/4/18.
*/
public class CategoryAdapter extends MyBaseAdapter<Object> {
private static final int DATE_TYPE_TITLE = 0;
private static final int DATA_TYPE_PIC =1;
public CategoryAdapter(ArrayList<Object> datas) {
super(datas);
}
@Override
protected int getLayoutResId(int position) {
return getItemViewType(position)==DATA_TYPE_PIC? R.layout.item_category_pic:R.layout.item_category_title;
}
@Override
protected Object createHolder(View convertView, int position) {
ViewHolder viewHolder = new ViewHolder();
int type = getItemViewType(position);
if(type ==DATE_TYPE_TITLE){
viewHolder.tv_title = (TextView) convertView;
}else{
LinearLayout containner = (LinearLayout) convertView;
//第一个子条目
viewHolder.ll_1 = (LinearLayout) containner.getChildAt(0);
//第二个子条目
viewHolder.ll_2 = (LinearLayout) containner.getChildAt(1);
//第三个子条目
viewHolder.ll_3 = (LinearLayout) containner.getChildAt(2);
}
return viewHolder;
}
@Override
protected void showdata(int position, Object viewHolder, Object data) {
int type = getItemViewType(position);
ViewHolder holder = (ViewHolder) viewHolder;
if(type ==DATE_TYPE_TITLE){
holder.tv_title.setText((String)data);
}else{
// CategoryInfo info =( (CategoryInfo)(((ArrayList)data).get(position)));
CategoryInfo info =( (CategoryInfo)data);
String url1 = Urls.IMAGE + "?name=" + info.getUrl1();
String url2 = Urls.IMAGE + "?name=" + info.getUrl2();
String url3 = Urls.IMAGE + "?name=" + info.getUrl3();
x.image().bind((ImageView) holder.ll_1.getChildAt(0),url1);
x.image().bind((ImageView) holder.ll_2.getChildAt(0),url2);
x.image().bind((ImageView) holder.ll_3.getChildAt(0),url3);
((TextView)holder.ll_1.getChildAt(1)).setText(info.getName1());
((TextView)holder.ll_2.getChildAt(1)).setText(info.getName2());
((TextView)holder.ll_3.getChildAt(1)).setText(info.getName3());
holder.ll_1.setOnClickListener(monOnClickListener);
holder.ll_2.setOnClickListener(monOnClickListener);
holder.ll_3.setOnClickListener(monOnClickListener);
}
}
View.OnClickListener monOnClickListener = new View.OnClickListener() {
@Override
public void onClick(View v) {
LinearLayout linearLayout = (LinearLayout) v;
TextView text= (TextView) linearLayout.getChildAt(1);
Toast.makeText(MyApplication.getContext(),text.getText(),Toast.LENGTH_SHORT).show();
}
};
@Override
public int getItemViewType(int position) {
Object data = datas.get(position);
return data instanceof String ? DATE_TYPE_TITLE: DATA_TYPE_PIC;
}
@Override
public int getViewTypeCount() {
return 2;
}
static class ViewHolder{
TextView tv_title;
LinearLayout ll_1;
LinearLayout ll_2;
LinearLayout ll_3;
}
}
| e6d3933b83cedae64a80a3b8191d2d6a2115c0b4 | [
"Java"
] | 8 | Java | ghb609840612/GoogleeMarket | 41d33b515e78d8ec37609a679e8e2fa2ab42fbe3 | f8e5cb652d55936d7ba8b589f235a6ea334bf37b |
refs/heads/master | <file_sep>/*
* @Author: 徐嘉晖
* @Date: 2019-11-25 14:49:52
* @Last Modified by: 徐嘉晖
* @Last Modified time: 2019-12-02 16:43:45
*/
$(function(){
//nav鼠标事件
$('.nav ul li').hover(function() {
$(this).children('.bar').show();
}, function() {
$(this).children('.bar').hide();
});
//搜索框显示隐藏
$('.glyphicon-search').click(function(event) {
$('.header .nav ul').fadeToggle(500);
$('.header .header-search').fadeToggle(500);
return false;
});
$('.icon-cross-fill').click(function(event) {
$('.header .header-search').fadeOut(500);
$('.header .nav ul').fadeIn(500);
return false;
});
$(document).click(function(event) {
var popup=$('.header .header-search')
if(!popup.is(event.target) && popup.has(event.target).length == 0){
$('.header .header-search').fadeOut(500);
$('.header .nav ul').fadeIn(500);
}
});
//登录模态框
$('.glyphicon-cloud-download').click(function(event) {
$('.login-box').show();
});
$('.login-box .close-box').click(function(event) {
$('.login-box').hide();
});
// 测导航
var f=$('.footerbase').offset().top;
$(window).scroll(function(event) {
var d=document.documentElement.clientHeight;
var h=$(this).scrollTop();
if(h>=f-d-60){
$('.content .slider').css('bottom', $('.footerbase').innerHeight()-($(document).height() - $(document).scrollTop() - document.documentElement.clientHeight - 30)+'px');
}else{
$('.content .slider').css('bottom', '30px');
}
});
$(window).scroll(function(event) {
var h=$(this).scrollTop();
if(h>$('.content').height()*0.5){
$('.content .slider').show();
}else{
$('.content .slider').hide();
}
});
$('.content .slider').click(function(event) {
$('body,html').animate({'scrollTop':'0px'}, 500)
});
})<file_sep>/*
* @Author: 徐嘉晖
* @Date: 2019-11-27 15:39:48
* @Last Modified by: 徐嘉晖
* @Last Modified time: 2019-12-02 16:44:27
*/
$(function(){
//banner轮播
var n=1;
$('.banner .top-banner .left').click(function(event) {
n++;
if(n>6){
$('.banner .top-banner ul').css('margin-left','-1380px');
n=2;
}
$('.banner .top-banner ul').stop().animate({'margin-left':-n*1380+'px'}, 500);
});
$('.banner .top-banner .right').click(function(event) {
n--;
if(n<0){
$('.banner .top-banner ul').css('margin-left','-6900px');
n=4;
}
$('.banner .top-banner ul').stop().animate({'margin-left':-n*1380+'px'}, 500);
});
var timer;
function banner(){
clearInterval(timer);
timer=setInterval(function(){
n++;
if(n>6){
$('.banner .top-banner ul').css('margin-left','-1380px');
n=2;
}
$('.banner .top-banner ul').stop().animate({'margin-left':-n*1380+'px'}, 500);
},2000)
}
banner();
$('.banner .top-banner').hover(function() {
clearInterval(timer)
}, function() {
banner();
});
//topNav
$('.topNav ul li').hover(function() {
$(this).children('.navhide').show();
}, function() {
$(this).children('.navhide').hide();
});
//subNav定位
var h1=$('.subNav').offset().top
$(window).scroll(function(event) {
var h=$(this).scrollTop();
// console.log(h);
// console.log(h1);
if (h>=h1) {
$('.subNav').css({
position: 'fixed',
top: '0'
});
}
else{
$('.subNav').css('position', '');
}
});
//advbanner轮播
var m=0;
$('.content-footer .right').click(function(event) {
m++;
if(m>1){
m=0;
}
$('.content-footer .advbanner ul').css('margin-left', -m*1400+'px');
});
})
<file_sep>/*
* @Author: 徐嘉晖
* @Date: 2019-11-29 14:30:51
* @Last Modified by: 徐嘉晖
* @Last Modified time: 2019-11-29 14:31:34
*/
$(function(){
var h1=$('.subNav').offset().top
$(window).scroll(function(event) {
var h=$(this).scrollTop();
console.log(h);
console.log(h1);
if (h>=h1) {
$('.subNav').css({
position: 'fixed',
top: '0'
});
}
else{
$('.subNav').css('position', '');
}
});
})
<file_sep>/*
* @Author: 徐嘉晖
* @Date: 2019-11-28 19:41:53
* @Last Modified by: 徐嘉晖
* @Last Modified time: 2019-11-29 10:00:22
*/
$(function(){
var h=$('.content-left').offset().top;
var c=$('.content').height();
var l=$('.content-left').height();
console.log(c-h)
$(window).scroll(function(event) {
var w=$(window).scrollTop();
if(w>=h){
$('.content-left').css({
position: 'fixed',
top: '0'
});
}
if(w>=c-l+h){
$('.content-left').css({
position:'absolute',
top: c-l+'px'
});
}
else if(w<=h){
$('.content-left').css({
position: 'absolute',
top: '40px'
});
}
});
})<file_sep>/*
* @Author: 徐嘉晖
* @Date: 2019-11-27 19:04:32
* @Last Modified by: 徐嘉晖
* @Last Modified time: 2019-11-27 19:35:53
*/
$(function(){
$('.content .safe>.right .top a').hover(function() {
var s=$(this).attr('text');
$(this).text(''+s+'').css({
backgroundColor: '#ffe300',
backgroundImage: 'none'
});
}, function() {
$(this).text('').css({
backgroundColor: '',
backgroundImage: ''
});
});
}) | 336bb0ebcd2c9e49dcaf5661863fd4ca0b0384b5 | [
"JavaScript"
] | 5 | JavaScript | GalaxyEquality/zhanku | 8736fdeeb3fb66dc7fb46496b72acdfd50b6c7b3 | 298d9a42aed2244995fee54f63ff761b34254e84 |
refs/heads/master | <repo_name>audwinoyong/aip-week3<file_sep>/aip-week3-react/src/App.js
import React, { Component } from 'react';
import logo from './logo.svg';
import './App.css';
class App extends Component {
constructor(props) {
super(props)
this.state = {
number: 3
}
}
onChangeNext = () => {
this.setState( { number: this.state.number - 1 })
}
renderNextButton = () => {
if (this.state.number !== 0) {
return <button onClick={() => this.onChangeNext()}>Next</button>
}
return
}
render() {
const mappedNumber = this.state.number === 0 ? 'Liftoff!' : this.state.number;
return (
<div style={{ padding: 30 }}>
<h1>{mappedNumber}</h1>
{this.renderNextButton()}
</div>
);
}
}
export default App;
| 7a264b1d08a74e025c65da0f2702c884c9d51fbd | [
"JavaScript"
] | 1 | JavaScript | audwinoyong/aip-week3 | bd3603ce4d12687b743520211761f15a98a9c2bc | 47a22f19dbf41cd6ed6b4675e4389521076b2e99 |
refs/heads/master | <repo_name>JohnyMoSwag/sdc-reset<file_sep>/sdc-reset.go
package main
// Importing required packages
import (
"bufio"
"fmt"
"io/ioutil"
"os/user"
"os"
"os/exec"
"strconv"
"strings"
"path/filepath"
"regexp"
"runtime"
)
var clear map[string]func() //create a map for storing clear funcs
func init() {
clear = make(map[string]func()) //Initialize it
clear["darwin"] = func() {
cmd := exec.Command("clear") //Mac example, its tested
cmd.Stdout = os.Stdout
cmd.Run()
}
clear["linux"] = func() {
cmd := exec.Command("clear") //Linux example, its tested
cmd.Stdout = os.Stdout
cmd.Run()
}
clear["windows"] = func() {
cmd := exec.Command("cmd", "/c", "cls") //Windows example it is untested, but I think its working
cmd.Stdout = os.Stdout
cmd.Run()
}
}
func CallClear() {
value, ok := clear[runtime.GOOS] //runtime.GOOS -> linux, windows, darwin etc.
if ok { //if we defined a clear func for that platform:
value() //we execute it
} else { //unsupported platform
panic("Your platform is unsupported! I can't clear terminal screen :(")
}
fmt.Println("Stamps.com LRT Reset 0.2.0") // Printing header
fmt.Println("--------------------------")
}
func display_options(options []string, msg string) string {
reader := bufio.NewReader(os.Stdin)
for {
CallClear() // Clear prompt/terminal
for count, option := range options { // Printing options to console
fmt.Println(count + 1, option)
}
fmt.Print(msg, "\n--> ")
text, _ := reader.ReadString('\n') // Get input from user
text = strings.TrimSpace(text) // Removing whitespace
choice, err := strconv.Atoi(text) // Convert string to int
if err != nil { // User didn't enter a number
fmt.Print(err)
fmt.Println("Invalid option. Press Enter to continue")
reader.ReadLine()
continue
}
if choice > len(options) { // User enter number greater then available options
fmt.Println("Invalid option. Press Enter to continue")
reader.ReadLine()
continue
}
if choice < 1 { // User entered 0
fmt.Println("Invalid option. Press Enter to continue")
reader.ReadLine()
continue
}
return options[choice - 1] // Return option specified by user input
}
}
func list_dir_contents(dir string) []string {
var f_names []string // Creating empty list
files, _ := ioutil.ReadDir(dir) // Reading contents of directory
for _, f := range files {
f_names = append(f_names, f.Name()) // Converting byte array to string
}
return f_names // Return list of directory contents
}
func versioned_folder() string {
usr, err := user.Current() // Getting current users home directory
if err != nil { // Exit if error
panic(err)
}
// Build path to versioned folder
ACCT_DIR := filepath.Join(usr.HomeDir, "AppData", "Roaming",
"Stamps.com Internet Postage",
"Profiles", "versioned")
return ACCT_DIR // Return versioned folder path
}
func xml_path(acct string, profile string) string {
// given account number & profile name, create path to profile.xml
return filepath.Join(versioned_folder(), acct, profile)
}
func get_acct_numbers() []string {
files := list_dir_contents(versioned_folder()) // List contents of versioned folder
return files // Return contents of versioned folder
}
func get_profiles(dir string) []string {
// List contents of account folder
profiles := list_dir_contents(filepath.Join(versioned_folder(), dir))
// Return contents of versioned folder in slice/list
return profiles
}
func read_reset_write(path string) {
// compiling regular expression
re := regexp.MustCompile("LastRefreshTimePreviousSession=\".*\"")
data, err := ioutil.ReadFile(path) // Reading file into memory
if err != nil { // Exit if error
panic(err)
}
s := "LastRefreshTimePreviousSession=\"\""
str_data := re.ReplaceAllString(string(data), s)
b_data := []byte(str_data) // convert string to byte array
ioutil.WriteFile(path, b_data, 0644) // write refreshed profile data back to file
}
func main() {
// Get a list of accounts
accounts := get_acct_numbers()
// Display list of accounts to user for selection
account := display_options(accounts, "Please choose account & press Enter")
// Get contents of account folder
profiles := get_profiles(account)
// Display list of profile.xml's to user for selection
profile := display_options(profiles, "Please choose Profile & press Enter")
// Building full path to xml file
path := xml_path(account, profile)
// Read xml file, reset LRT, write xml file
read_reset_write(path)
}
<file_sep>/docs/requirements.txt
JMS-Utils==0.6.2
PyInstaller==2.1
<file_sep>/docs/index.rst
.. Stamps.com SDC Reset documentation master file, created by
sphinx-quickstart on Tue Feb 24 22:29:32 2015.
You can adapt this file completely to your liking, but it should at least
contain the root `toctree` directive.
Stamps.com LRT Reset's documentation!
=====================================
Usage
*****
1. Choose an account number, then press enter. In the screen-shot below, valid choices are 1-11.
.. image:: _static/1.jpg
:width: 300pt
2. Choose a profile & press enter. The profile will be reset & the application will quit. In the screen-shot below valid choices are 1 or 2.
.. image:: _static/2.jpg
:width: 300pt
Please email me with any questions, comments and/or suggestions. <EMAIL>
How to compile
**************
You must have GO installed. UPX is optional but recommended since it greatly reduces executable size.
*From the command prompt*::
> go build sdc-reset.go # Compiling source with go's compiler
> upx --best --ultra-brute sdc-reset.exe # Compressing executable
For more information on the GO language & UPX visit their respective site below.
Go: https://golang.org
UPX: http://upx.sourceforge.net
Change Log
**********
v0.2.0 - GOing GOing GOne
-------------------------
.. image:: _static/gopherbw.png
:width: 50pt
Rewritten in go
Benefits:
Faster application launch
About 80% smaller executable size
v0.1.0
------
Inital Release
.. toctree::
:maxdepth: 2
| 3b6ef9671995915b59078fd3e092b6d66b68c76e | [
"Text",
"Go",
"reStructuredText"
] | 3 | Go | JohnyMoSwag/sdc-reset | ff83ed26169f9282467c1f89e79dbc75ff509df2 | 134cc3f00a246d0f8b395c01b0571a6ea04b5cb7 |
refs/heads/master | <file_sep>import React from 'react';
import {
AppRegistry,
asset,
Pano,
Text,
View,
VrButton,
Image
} from 'react-vr';
export default class WelcomeToVR extends React.Component {
constructor() {
super();
this.state = {
textColor: 'white',
backImage: 'chess-world.jpg'
};
}
changeBackImage(PlaceId){
if(PlaceId == 1){
this.setState({backImage: 'Paris.jpg'})
}else if(PlaceId == 2){
this.setState({backImage: 'Arizona.jpg'})
}else if(PlaceId == 3){
this.setState({backImage: 'Liberia.jpg'})
}
}
render() {
return (
<View>
<Pano source={asset(this.state.backImage)}/>
<View style={{
flex: 1,
flexDirection: 'row',
width: 5,
alignItems: 'stretch',
transform: [{translate: [-2.5, 0, -5]}],
}}>
<VrButton
onClick={()=>this.changeBackImage(1)}
style={{flex: 1}}>
<Text style={{fontSize: 0.2, textAlign: 'center', margin: 0.1, height: 0.3, backgroundColor: '#777879'}}>Go to Paris!</Text>
</VrButton>
<VrButton
onClick={()=>this.changeBackImage(2)}
style={{flex: 1}}>
<Text style={{fontSize: 0.2, textAlign: 'center', margin: 0.1, height: 0.3, backgroundColor: '#777879'}}>Go to Arizona!</Text>
</VrButton>
<VrButton
onClick={()=>this.changeBackImage(3)}
style={{flex: 1}}>
<Text style={{fontSize: 0.2, textAlign: 'center', margin: 0.1, height: 0.3, backgroundColor: '#777879'}}>Go to Liberia!</Text>
</VrButton>
</View>
</View>
);
}
};
AppRegistry.registerComponent('WelcomeToVR', () => WelcomeToVR);
| 7166f471e70bdc0e386868e9990c77bba527e58f | [
"JavaScript"
] | 1 | JavaScript | entaku19890818/WelcomeToVR | 445949a53b8533e6442749814cb8cc23158034a6 | b328f7f80cff36db0945e9801111fcaed485e7c7 |
refs/heads/master | <file_sep>import React from 'react';
import './App.css';
import SearchComponent from './search-widget/SearchComponent';
const queryString = require('query-string');
function App() {
let queryParamInUrl = null;
const parsed = queryString.parseUrl(window.location.href);
console.log(parsed)
if(parsed.query && parsed.query.query !== undefined){
queryParamInUrl = parsed.query.query;
}
return (
<div className="App">
<SearchComponent
query={queryParamInUrl}
/>
</div>
);
}
export default App;
| ae8547229c12b503084d2e03ccbbdba6af4469b9 | [
"JavaScript"
] | 1 | JavaScript | pallavipathak1603/news-search-widget | 6249b7b65304da2b8bcb65ccc3dbefae8e173fbf | dca3ceefc34ef72ffa550e2118f2424692fe197c |
refs/heads/master | <repo_name>learn-academy-2020-alpha/week-1-assessment-RudyBecker<file_sep>/js-testing.test.js
// --------------------1a) Create a test for a function called addThemUp that takes two numbers as arguments and returns the sum.
describe("addThemUp", () => {
test ("takes two numbers as arguments and returns sum", () => {
expect(addThemUp(1,2)).toEqual(3);
})
})
// --------------------1b) See the test fail. THEN write the code to make the test pass.
const addThemUp = (a,b) => {
return a+b;
}
console.log(addThemUp(4,5))
// --------------------2a) Create a test for a function called triangleArea that takes the base and the height of a triange and returns the area. The area of a triange is the base times the height divided by two.
describe("triangleArea", () => {
test(" base * height divided by 2", () => {
expect(triangleArea(3,3)).toEqual(4.5);
})
})
// --------------------2b) See the test fail. THEN write the code to make the test pass.
const triangleArea = (x,y) => {
return (x+y/2);
}
console.log(triangleArea(5,7))<file_sep>/js-intro.md
# ASSESSMENT 1: INTRO TO JAVASCRIPT
## Tech Interview Practice Questions
Answer the following questions. First, without external resources. Challenge yourself to answer from memory. Then, research the question to expand on your answer. Even if you feel you have answered the question completely on your own, there is always something more to learn.
1. What is a function? Why would you use one?
Your answer: A function is a code you write that completes an action on an agrument/input based on the parameters you set within your code. You would use a function if you need
a reaction to happen based on the value you have the system evaluate to run an action on.
Researched answer:
A JavaScript function is a block of code designed to perform a particular task. Functions have a designated name, a list of parameters enclosed in parenthesis and separated by commas,
and a JavaScript statement that defines the function enclosed in curly brackets. A function can be invoked or run when an event occurs (when a user clicks a button), when it is invoked
or called from prior Javascript code, or invoked automaticaly by itself. A function can be used various times to yielf different results.
2. What is the difference between map and filter?
Your answer: .map and .filter are both actions that can access array or objects in different ways. .filter will change the length of the array while .map will keep the integrity and length of the array.
Researched answer:
.filter() returns a subset of the elements from the original array, while .map() produces an array with new, different entries based on the elements in the original array.
The filter() method creates an array filled with all array elements that pass a test implemented by the provided function. The filter method is well suited for particular instances where the user
must identify certain items in an array that share a common characteristic.The map() method creates a new array with the results of calling a function for every array element. The map method allows items
in an array to be manipulated to the user’s preference, returning the conclusion of the chosen manipulation in an entirely new array.
3. What is the difference between console.log() and return?
Your answer: console.log() is a tool for developers to see the desired result of the code they write. "return" is used in code as a way for the argument to exit the code if it meets the desired
parameters. Frequently after the word "return" actions are written out in the code as to what should happen to the argument that is entered.
Researched answer:
The console.log() outputs a message to the web console. The message may be a single string (with optional substitution values), or it may be any one or more JavaScript objects.
The console.log() is a function in JavaScript which is used to print any kind of variables defined before in it or to just print any message that needs to be displayed to the user.
The return statement stops the execution of a function and returns a value from that function.
4. In regards to functions, what is an argument?
Your answer: An argument is any data type (boolean, string, number, object etc.) that is entered into a function to be processed by that function. It is the information that the function
may or may not act on depending on the parameters set by the programmer writing the code.
Researched answer:
Arguments are values passed to the function when it is invoked.
5. Give a brief description of proper pair programming techniques. What are the roles of each person?
Your answer: Pair Programming is a very effective learning method that involves 2 programmers working collaboratively together to create effective and functional code. There are two
positions the navigator and the driver. The Navigator is the one that uses the mouse and keyboard while the driver is the one who voices out what the navigator should do. When utilizing
pair programming it is important for each person to have patience, persistence, an open mind, respect for each other learning process, and teamwork.
Researched answer:
Pair programming is an agile software development technique in which two programmers work together at one workstation. One, the driver, writes code while the other, the observer or navigator,
reviews each line of code as it is typed in. The two programmers switch roles frequently.
6. What is TDD? Describe the work flow associated with TDD.
Your answer: I do not know what TDD is.
Researched answer:
Test-driven development is a software development process that relies on the repetition of a very short development cycle: requirements are turned into very specific test cases, then the code
is improved so that the tests pass.Test-Driven Development starts with designing and developing tests for every small functionality of an application. In TDD approach, first, the test is developed
which specifies and validates what the code will do. TDD means "Test Driven Development". The primary goal of TDD is to make the code clearer, simple and bug-free.
7. What is something we did in class this week you found helpful?
Your answer:
Working on this assessment assignment was EXTREMELY helpful. Placing myself in front of an assignment by myself to research all aspects to achieve the code to work was super effective in
my learning process.
I enjoyed working with pairs, sometimes my partner was more experienced then me and I learned alot from them, sometimes I was more experienced than my partner and I could teach them. Both
models were very effective for me. The more we can switch pairs the better (at least a new pair each day).
I enjoyed the end of week question wrap up.
## Looking Ahead: Terms for Next Week
Define the following terms to the best of your ability.
- React
Your answer:
I believe it is a programming language or framework created by Facebook.
Researched answer:
React is a declarative, efficient, and flexible JavaScript library for building user interfaces. It lets you compose complex UIs from small and isolated pieces of code called “components”.
- Yarn
Your answer:
It is a method of retrieving specific data.
Researched answer:
Yarn is a package manager for your code. It allows you to use and share (e.g. JavaScript) code with other developers from around the world.Code is shared through something called a package
(sometimes referred to as a module). A package contains all the code being shared as well as a package.json file which describes the package.
- React State
Your answer:
I don't know what React State is.
Researched answer:
The heart of every React component is its “state”, an object that determines how that component renders & behaves. In other words, “state” is what allows you to create components that
are dynamic and interactive. Ice to Water analogy where if you change the value of the temperature you can put the ice or water into a different state.
- CRUD
Your answer: I don't know what CRUD is.
Researched answer: Create, Read, Update, Delete.
| 6e02d40caebcb46e3ebf8a846e1c6cc6dc17e727 | [
"JavaScript",
"Markdown"
] | 2 | JavaScript | learn-academy-2020-alpha/week-1-assessment-RudyBecker | 84f20062bfde5c3a5c4a057453857454399db75f | fcd80460ae935324f0d7752842779f378987ab1a |
refs/heads/master | <file_sep># SwiftOpen
this is a Swift primary curriculum for iOS
<file_sep>//
// main.swift
// simple4
//
// Created by xianingzhong on 15/4/11.
// Copyright (c) 2015年 xianingzhong. All rights reserved.
//
import Foundation
//1、字典 Swift 的字典使用时需要具体规定具体可以存储健和值类型,必须提前定义清楚，方法是通过显性类型标注或者类型推断
var person = ["age":18,
"name": "jack"]
//updateValue(forKe:) 方法在这个健不存在对应的值的时候设置值或者存在时更新已存在的值。和上面的下标方法不一样，这个方法返回更新值之前的原值。这样方便我们检查更新是否成功
if let oldName = person.updateValue("Tom", forKey: "name"){
// println("原来的值:\(oldName)")
}
//println(person)
//2、removeValueForKey 方法也可以用来在字典中移除键值对
//person.removeValueForKey("age")
//println(person)
//3、每一个字典中的数据项都是由（key, value） 元组形式返回，并且我们可以使用临时常量或者变量来分解这些元组；
for (key, value) in person{
// println("\(key):\(value)")//字典是无序的，遍历的时候不能保证顺序
}
//声明字典
var dic = Dictionary<String, Int>()
dic["年龄"] = 16
dic = [:]//空字典
//println(dic)
//通过常量或者变量决定数组（字典）是否可变
//控制流
let base=3
let power=10
var answer=1
for _ in 1...power{ //下划线符号_ (替代循环中的变量) 能够忽略具体的值，并且不提供循环遍历时对值的访问
answer *= base
}
//println(answer)
//5、Switch
let count = 3_000_000_000_000
let contedThings = "start in the milky way"
var naturalCount:String
switch count{
case 0:
naturalCount = "no"
fallthrough
case 1...3:
naturalCount = "a few"
fallthrough
case 4...9:
naturalCount = "several"
fallthrough
case 10...99:
naturalCount = "tens of"
fallthrough
case 100...999:
naturalCount = "hundreds of"
fallthrough
case 100...999_999:
naturalCount = "thousands of"
fallthrough
default:
naturalCount = "millions and millons of"
}
println(naturalCount)
<file_sep>//
// main.swift
// simple3
//
// Created by xianingzhong on 15/4/11.
// Copyright (c) 2015年 xianingzhong. All rights reserved.
//
import Foundation
//1、
var a=3
var b=4
//if a==b {
//
//}
//2、溢出运算符 &+ , &- ....
var c=UInt8.min
c=c&-1
//println(c)
//3、对浮点数求余数
var rem = 10%2.3
//println(rem)
//4. 空合并运算符 （a??b）将对可选类型a进行判断，如果a 包含一个值就进行解封。否则就返回一个默认值b
// a、表达式a 必须是可选类型 b、默认值b的类型必须要和a储存值的类型保持一致
let words = "hello"
var say:String? = ""
var content = say ?? words
//println(content)
//5、 闭区间运算符 a...b； 半开区间运算符 a..<b(包括a但是不包括b) m没有空格 遍历数组或者字典
for i in 1..<5{
println(i)
}
//6、字符串
var str1 = "老夏"
var str2 = String() //初始化字符串实例
var str3 = str1 + "你好"//用+ 拼接
str1 += "niubi" //用+＝ 将字符串拼接到自身
//println(str1)
let char:Character = "1"
str1.append(char)
println(str1)
//count()函数 获取字符串的字符个数
println("str3 has \(count(str3)) chars")
//直接用 == 判断字符串是否相同
let quotation = "same"
let sanmequ = "same"
if quotation == sanmequ {
println("xiangtong")
}
var food = ["Fruits:apple",
"Fruits:orange",
"Fruits:banana",
"Fruits:tomato",
"Fruits:potato"]//数组
//检查字符串是否拥有特定前缀/后缀。两个方法均需要以字符串作为参数传入并传出Boolean值
for fru in food {
if fru.hasPrefix("Fruits"){
// println(fru)
}
if fru.hasSuffix("o"){
// println(fru)
}
}
//7、数组
food.append("Vegatable:aaaaa")//使用append 方法添加新的数据项
food[0...2] = ["ss","nn"] //根据下标替换 但是不能在数组尾部添加新项
food.insert("Meat", atIndex: 0)//添加新项
//println(food)
//使用removeAtIndex方法来移除数组中的某一项
//把数组中的最后一项移除，可以使用removeLast 方法
//使用构造语法来创建一个由特定数据构成的空数组
var someInt = [Int]()
println("someInts is of Type [Int] \(someInt.count) items")
//创建特定大小并且所有数据都被默认的构造方法 浮点型 3个
var ThreeDouble = [Double](count: 3, repeatedValue: 0.0)
<file_sep>//
// main.swift
// simple5
//
// Created by xianingzhong on 15/4/11.
// Copyright (c) 2015年 xianingzhong. All rights reserved.
//
import Foundation
//1、函数
func sayHello(personName: String)->String{
return "Hello,"+personName + "!"
}
//println(sayHello("laoxia"))
func LehgthNumber(start:Int , end:Int)->Int{
return end-start
}
//println(LehgthNumber(5,7))
//局部参数名 例如personName 只能在函数体内部使用，外部参数名写在局部参数名之前,用空格分隔
//toString 外部参数名 s2是内部参数名
//s1 通过加# 既是外部参数名也是内部参数名
func join(#s1: String, toString s2: String , withJoiner joiner:String)->String{
return s1 + joiner + s2
}
//println(join(s1: "hello", toString: "world", withJoiner: ","))
//如果 joiner 的值没有被指定，函数会使用默认值（" "）当你未给带默认值的参数提供外部参数名时，Swift会自动提供外部名字。此时外部参数名与局部参数名一致
//没有指定返回类型的函数返回Void ,Void与空的元组是一样的
func addTwoInts(a:Int, b:Int)->Int{
return a+b
}
func multiplyTowInts(a:Int, b:Int)->Int{
return a*b
}
//定义一个叫做 mathFunction 的变量， 类型是一个有两个Int 型的参数并返回一个Int型的值的函数
var mathFunction:(Int, Int)->Int = addTwoInts
//println("Result:\(mathFunction(2,3))")
//第二种
func printMathResult(mathFunction:(Int, Int)->Int, a:Int, b:Int){
println("Result:\(mathFunction(a,b))")
}
printMathResult(addTwoInts, 3, 5)
//类
class Person{
var name = "this"
var age = 19
var height = 172.5
func produce(){
age++
}
}
//结构体、类和枚举能够定义方法
<file_sep>//
// main.swift
// simple2
//
// Created by xianingzhong on 15/4/11.
// Copyright (c) 2015年 xianingzhong. All rights reserved.
//
import Foundation
println("Hello, World!")
//1、类型转换
let a:UInt8 = 10
let b:UInt16 = 100
//运算需要类型相同
println("\(UInt16(a) + b)")
let sa = 3
let pi = 3.1415
let add = Double(sa)+pi
println(add)
//2、类型别名 给现有的类型定义别的名字
typealias AudioSample = UInt16
var maxValue = AudioSample.min
println(maxValue)
//3、元组 把多个值组合成一个复合值 元组内的值 可以是任何类型
let people = (18,"woshilaoxia") //组合
let (age, name) = people //分解
println("The age is \(age)")
println("The name is \(name)")
//如果需要分解的部分值忽略的部分可以用下划线 _ 标记
let (justAge, _) = people
println("The age is \(justAge)")
//可以用下标来访问元组中单个元素
println("\(people.0)")
println("\(people.1)")
//定义元组的时候 给单个元组命名
let rec = (w:10, h:20)
println("\(rec.w)")
println("\(rec.h)")
println(rec.w)
//4、可选类型：处理值可能缺失的情况
let Str = "1234"
let converNumber = Str.toInt()
println(converNumber) //converNumber 是optional Int 或者 Int?
if converNumber != nil {
println(converNumber!)//加个！可选值的强制解析 表示可选值有值可以使用 强制解析会出错
}
//可选绑定 代替上面强制解析取值 可以用在if 或者While语句中来对可选类型的值进行判断并把值赋给一个常亮或者变量
if let actualNumber = Str.toInt(){
println(actualNumber)
}
//nil 表示一个确定的值，表示值确实
var serviceCode: Int? = 404
serviceCode = nil //现在 serviceCode 不包含值
var sunny:String? //不赋值自动置nil
//隐式解析可选类型 : 第一次被赋值之后，可以确定一个可选类型总会有值，不要在变量没有值的时候使用
var possibleStr: String! = "laoxianiubi"
println(possibleStr)
//5、断言 调试代码
let age2 = -10
assert(age2>=0, "年龄要大于0")
<file_sep>//
// main.swift
// simple
//
// Created by xianingzhong on 15/4/11.
// Copyright (c) 2015年 xianingzhong. All rights reserved.
//
import Foundation
println("Hello, World!")
//基本数据类型：Int 整型， Double 和Float 浮点型，Bool 布尔值， String 文本型数据， Array 数组， Dictionary字典
//常量 let， 变量 var
let con = 100
var avi = 30
avi = 40
//一行中声明多个常亮或者变量，用逗号隔开
var a=3,b=4,c=5
//类型标注:如果声明的同时赋了初始值 并不需要类型标注
var who:String
who = "laoxia"
println(who)
//变量和常亮的命名 ： 不能包含数字符号，箭头，连线与制表符，不能以数字开头
let 你好 = "哈哈能用中文"
println(你好)
var 😊 = "笑了"
println(😊)
var 眼睛 = "👀"
println(眼睛)
println()//输出结果换行
print()//输出结果不换行
//字符串插值 \转义 类似OC %@
var apples = 10;
var oranges = 4;
println("I have \(apples + oranges) fruits")
//Swift的分号可有可无 但是在一行内写多条独立语句必须要用分号 | 2829af921c74e04ea31d1db7fbfa6a1430d5a1b4 | [
"Markdown",
"Swift"
] | 6 | Markdown | xianignzhong/SwiftOpen | 7b7f47ac9c884a020169abfa708f81aeb0731124 | 5a9b96cac9e4778da2a5c5464952c619df5ebbfc |
refs/heads/main | <file_sep>from turtle import Screen, Turtle
from snake import Snake
from food import Food
from scoreboard import ScoreBoard
import time
screen = Screen()
screen.setup(width=600, height=600)
screen.bgcolor("black")
screen.tracer(0)
score_board = ScoreBoard()
snake = Snake()
food = Food()
screen.listen()
screen.onkeypress(snake.up, "Up")
screen.onkeypress(snake.down, "Down")
screen.onkeypress(snake.left, "Left")
screen.onkeypress(snake.right, "Right")
game_is_on = True
score_board.score = 0
while game_is_on:
time.sleep(0.1)
screen.update()
snake.move()
# Detect collision with the food
if snake.segments[0].distance(food) < 15:
food.refresh()
snake.extend()
score_board.increase_score()
# Detect collision with the wall
if snake.segments[0].xcor() > 290 or snake.segments[0].xcor() < -290 or snake.segments[0].ycor() > 290 or \
snake.segments[0].ycor() < -290:
game_is_on = False
score_board.game_over()
# Detect collision with the tail
for i in range(1, len(snake.segments), 1):
if snake.segments[0].distance(snake.segments[i]) <= 10:
game_is_on = False
score_board.game_over()
screen.exitonclick()<file_sep>from turtle import Turtle
UP = 90
LEFT = 180
DOWN = 270
RIGHT = 0
class Snake:
def __init__(self):
self.segments = []
self.create()
def create(self):
for i in range(3):
segment = Turtle("square")
segment.color("white")
segment.penup()
self.segments.append(segment)
x_cor, y_cor = 0, 0
for segment in self.segments:
segment.goto(x_cor, y_cor)
x_cor -= 20
def extend(self):
segment = Turtle("square")
segment.color("white")
segment.penup()
new_position = self.segments[-1].position()
segment.goto(new_position)
self.segments.append(segment)
def move(self):
for seg_num in range(len(self.segments) - 1, 0, -1):
new_xcor = self.segments[seg_num - 1].xcor()
new_ycor = self.segments[seg_num - 1].ycor()
self.segments[seg_num].goto(new_xcor, new_ycor)
self.segments[0].forward(20)
def up(self):
if self.segments[0].heading() != DOWN:
self.segments[0].setheading(UP)
def left(self):
if self.segments[0].heading() != RIGHT:
self.segments[0].setheading(LEFT)
def down(self):
if self.segments[0].heading() != UP:
self.segments[0].setheading(DOWN)
def right(self):
if self.segments[0].heading() != LEFT:
self.segments[0].setheading(RIGHT) | 14d5bb57d83fa525cadb871485e23bf2f83895dc | [
"Python"
] | 2 | Python | Meet12350/Python | e29286b9c64537c34fc245d41866a3559aead8e3 | 6a5b88a637acd6c316f88e676bf8d8b73808f837 |
refs/heads/master | <file_sep>BINDIR = bin
SERVER_BINARY = micro-chat-server
CLIENT_BINARY = micro-chat-client
$(BINDIR):
if [ ! -d $@ ]; then mkdir -p $@; fi
CFLAGS = -std=c99 -O3 -Wall
LDFLAGS = -pthread -lulfius
.PHONY: build
build: $(BINDIR)/$(SERVER_BINARY)
$(BINDIR)/$(SERVER_BINARY): clean
$(CC) -o $(BINDIR)/$@ server/*.c $(LDFLAGS)
$(BINDIR)/$(CLIENT_BINARY): clean
$(CC) -o $(BINDIR)/$@ *.c $(LDFLAGS)
.PHONY: test
test:
# unimplemented
.PHONY: clean
clean:
rm -f bin/*
<file_sep>#include <stdlib.h>
#include <ulfius.h>
#include "../logger.h"
#define DEFAULT_PORT 9000
/* Add client to queue */
// void
// queue_add(client_t *cl)
// {
// pthread_mutex_lock(&clients_mutex);
// for (int i = 0; i < MAX_CLIENTS; ++i) {
// if (!clients[i]) {
// clients[i] = cl;
// break;
// }
// }
// pthread_mutex_unlock(&clients_mutex);
// }
// /* Delete client from queue */
// void
// queue_delete(int uid)
// {
// pthread_mutex_lock(&clients_mutex);
// for (int i = 0; i < MAX_CLIENTS; ++i) {
// if (clients[i]) {
// if (clients[i]->uid == uid) {
// clients[i] = NULL;
// break;
// }
// }
// }
// pthread_mutex_unlock(&clients_mutex);
// }
#if defined(U_DISABLE_WEBSOCKET)
int
main()
{
fprintf(stderr, "error: websocket not supported. please recompile ulfius with websocket support\n");
return 1;
}
#else
int callback_websocket (const struct _u_request * request, struct _u_response * response, void * user_data);
int callback_websocket_echo (const struct _u_request * request, struct _u_response * response, void * user_data);
int callback_websocket_file (const struct _u_request * request, struct _u_response * response, void * user_data);
void websocket_onclose_file_callback (const struct _u_request * request,
struct _websocket_manager * websocket_manager,
void * websocket_onclose_user_data) {
y_log_message(Y_LOG_LEVEL_DEBUG, "websocket_onclose_file_callback");
}
/**
* websocket_onclose_callback
* onclose callback function
* Used to clear data after the websocket connection is closed
*/
void websocket_onclose_callback (const struct _u_request * request,
struct _websocket_manager * websocket_manager,
void * websocket_onclose_user_data) {
if (websocket_onclose_user_data != NULL) {
y_log_message(Y_LOG_LEVEL_DEBUG, "websocket_onclose_user_data is %s", websocket_onclose_user_data);
o_free(websocket_onclose_user_data);
}
}
void websocket_echo_message_callback (const struct _u_request * request,
struct _websocket_manager * websocket_manager,
const struct _websocket_message * last_message,
void * websocket_incoming_message_user_data) {
y_log_message(Y_LOG_LEVEL_DEBUG, "Incoming message, rsv: 0x%02x, opcode: 0x%02x, mask: %d, len: %zu, text payload '%.*s'", last_message->rsv, last_message->opcode, last_message->has_mask, last_message->data_len, last_message->data_len, last_message->data);
if (ulfius_websocket_send_message(websocket_manager, last_message->opcode, last_message->data_len, last_message->data) != U_OK) {
//y_log_message(Y_LOG_LEVEL_ERROR, "Error ulfius_websocket_send_message");
}
}
/**
* websocket_manager_callback
* send 5 text messages and 1 ping for 11 seconds, then closes the websocket
*/
void
websocket_manager_callback(const struct _u_request * request,
struct _websocket_manager * websocket_manager,
void * websocket_manager_user_data) {
if (websocket_manager_user_data != NULL) {
//y_log_message(Y_LOG_LEVEL_DEBUG, "websocket_manager_user_data is %s", websocket_manager_user_data);
}
// Send text message without fragmentation
if (ulfius_websocket_wait_close(websocket_manager, 2000) == U_WEBSOCKET_STATUS_OPEN) {
if (ulfius_websocket_send_message(websocket_manager, U_WEBSOCKET_OPCODE_TEXT, o_strlen("Message without fragmentation from server"), "Message without fragmentation from server") != U_OK) {
//y_log_message(Y_LOG_LEVEL_ERROR, "Error send message without fragmentation");
}
}
// Send text message with fragmentation for ulfius clients only, browsers seem to dislike fragmented messages
if (o_strncmp(u_map_get(request->map_header, "User-Agent"), U_WEBSOCKET_USER_AGENT, o_strlen(U_WEBSOCKET_USER_AGENT)) == 0 &&
ulfius_websocket_wait_close(websocket_manager, 2000) == U_WEBSOCKET_STATUS_OPEN) {
if (ulfius_websocket_send_fragmented_message(websocket_manager, U_WEBSOCKET_OPCODE_TEXT, o_strlen("Message with fragmentation from server"), "Message with fragmentation from server", 5) != U_OK) {
//y_log_message(Y_LOG_LEVEL_ERROR, "Error send message with fragmentation");
}
}
// Send ping message
if (ulfius_websocket_wait_close(websocket_manager, 2000) == U_WEBSOCKET_STATUS_OPEN) {
if (ulfius_websocket_send_message(websocket_manager, U_WEBSOCKET_OPCODE_PING, 0, NULL) != U_OK) {
//y_log_message(Y_LOG_LEVEL_ERROR, "Error send ping message");
}
}
// Send binary message without fragmentation
if (ulfius_websocket_wait_close(websocket_manager, 2000) == U_WEBSOCKET_STATUS_OPEN) {
if (ulfius_websocket_send_message(websocket_manager, U_WEBSOCKET_OPCODE_BINARY, o_strlen("Message without fragmentation from server"), "Message without fragmentation from server") != U_OK) {
//y_log_message(Y_LOG_LEVEL_ERROR, "Error send binary message without fragmentation");
}
}
// Send JSON message without fragmentation
#ifndef U_DISABLE_JANSSON
if (ulfius_websocket_wait_close(websocket_manager, 2000) == U_WEBSOCKET_STATUS_OPEN) {
json_t * message = json_pack("{ss}", "send", "JSON message without fragmentation");
if (ulfius_websocket_send_json_message(websocket_manager, message) != U_OK) {
//y_log_message(Y_LOG_LEVEL_ERROR, "Error send JSON message without fragmentation");
}
json_decref(message);
}
#endif
//y_log_message(Y_LOG_LEVEL_DEBUG, "Closing websocket_manager_callback");
}
/**
* websocket_incoming_message_callback
* Read incoming message and prints it on the console
*/
void websocket_incoming_message_callback (const struct _u_request * request,
struct _websocket_manager * websocket_manager,
const struct _websocket_message * last_message,
void * websocket_incoming_message_user_data) {
if (websocket_incoming_message_user_data != NULL) {
//y_log_message(Y_LOG_LEVEL_DEBUG, "websocket_incoming_message_user_data is %s", websocket_incoming_message_user_data);
}
//y_log_message(Y_LOG_LEVEL_DEBUG, "Incoming message, rsv: 0x%02x, opcode: 0x%02x, mask: %d, len: %zu", last_message->rsv, last_message->opcode, last_message->has_mask, last_message->data_len);
if (last_message->opcode == U_WEBSOCKET_OPCODE_TEXT) {
//y_log_message(Y_LOG_LEVEL_DEBUG, "text payload '%.*s'", last_message->data_len, last_message->data);
} else if (last_message->opcode == U_WEBSOCKET_OPCODE_BINARY) {
//y_log_message(Y_LOG_LEVEL_DEBUG, "binary payload");
}
}
void websocket_manager_file_callback(const struct _u_request * request,
struct _websocket_manager * websocket_manager,
void * websocket_manager_user_data) {
y_log_message(Y_LOG_LEVEL_DEBUG, "Opening websocket_manager_file_callback");
for (;;) {
sleep(1);
if (websocket_manager == NULL || !websocket_manager->connected) {
break;
}
}
y_log_message(Y_LOG_LEVEL_DEBUG, "Closing websocket_manager_file_callback");
}
/**
* websocket_incoming_message_callback
* Read incoming message and prints it on the console
*/
void websocket_incoming_message_callback (const struct _u_request * request,
struct _websocket_manager * websocket_manager,
const struct _websocket_message * last_message,
void * websocket_incoming_message_user_data) {
if (websocket_incoming_message_user_data != NULL) {
y_log_message(Y_LOG_LEVEL_DEBUG, "websocket_incoming_message_user_data is %s", websocket_incoming_message_user_data);
}
y_log_message(Y_LOG_LEVEL_DEBUG, "Incoming message, rsv: 0x%02x, opcode: 0x%02x, mask: %d, len: %zu", last_message->rsv, last_message->opcode, last_message->has_mask, last_message->data_len);
if (last_message->opcode == U_WEBSOCKET_OPCODE_TEXT) {
y_log_message(Y_LOG_LEVEL_DEBUG, "text payload '%.*s'", last_message->data_len, last_message->data);
} else if (last_message->opcode == U_WEBSOCKET_OPCODE_BINARY) {
y_log_message(Y_LOG_LEVEL_DEBUG, "binary payload");
}
}
void websocket_echo_message_callback (const struct _u_request * request,
struct _websocket_manager * websocket_manager,
const struct _websocket_message * last_message,
void * websocket_incoming_message_user_data) {
y_log_message(Y_LOG_LEVEL_DEBUG, "Incoming message, rsv: 0x%02x, opcode: 0x%02x, mask: %d, len: %zu, text payload '%.*s'", last_message->rsv, last_message->opcode, last_message->has_mask, last_message->data_len, last_message->data_len, last_message->data);
if (ulfius_websocket_send_message(websocket_manager, last_message->opcode, last_message->data_len, last_message->data) != U_OK) {
y_log_message(Y_LOG_LEVEL_ERROR, "Error ulfius_websocket_send_message");
}
}
void websocket_incoming_file_callback (const struct _u_request * request,
struct _websocket_manager * websocket_manager,
const struct _websocket_message * last_message,
void * websocket_incoming_message_user_data) {
char * my_message = msprintf("Incoming file %p, rsv: 0x%02x, opcode: 0x%02x, mask: %d, len: %zu", last_message, last_message->rsv, last_message->opcode, last_message->has_mask, last_message->data_len);
y_log_message(Y_LOG_LEVEL_DEBUG, my_message);
ulfius_websocket_send_message(websocket_manager, U_WEBSOCKET_OPCODE_TEXT, o_strlen(my_message), my_message);
o_free(my_message);
}
/**
* Ulfius main callback function that simply calls the websocket manager and closes
*/
int callback_websocket (const struct _u_request * request, struct _u_response * response, void * user_data) {
char * websocket_user_data = o_strdup("my_user_data");
int ret;
if ((ret = ulfius_set_websocket_response(response, NULL, NULL, &websocket_manager_callback, websocket_user_data, &websocket_incoming_message_callback, websocket_user_data, &websocket_onclose_callback, websocket_user_data)) == U_OK) {
ulfius_add_websocket_deflate_extension(response);
return U_CALLBACK_CONTINUE;
} else {
return U_CALLBACK_ERROR;
}
}
int callback_websocket_echo (const struct _u_request * request, struct _u_response * response, void * user_data) {
char * websocket_user_data = o_strdup("my_user_data");
int ret;
y_log_message(Y_LOG_LEVEL_DEBUG, "Client connected to echo websocket");
if ((ret = ulfius_set_websocket_response(response, NULL, NULL, NULL, NULL, &websocket_echo_message_callback, websocket_user_data, &websocket_onclose_callback, websocket_user_data)) == U_OK) {
ulfius_add_websocket_deflate_extension(response);
return U_CALLBACK_CONTINUE;
} else {
return U_CALLBACK_ERROR;
}
}
int callback_websocket_file (const struct _u_request * request, struct _u_response * response, void * user_data) {
int ret;
if ((ret = ulfius_set_websocket_response(response, NULL, NULL, &websocket_manager_file_callback, NULL, &websocket_incoming_file_callback, NULL, &websocket_onclose_file_callback, NULL)) == U_OK) {
ulfius_add_websocket_deflate_extension(response);
return U_CALLBACK_CONTINUE;
} else {
return U_CALLBACK_ERROR;
}
}
int
main(int argc, char **argv)
{
int port = 0;
int c;
if (argc != 0) {
while ((c = getopt(argc, argv, "p:c:k:hv")) != -1) {
switch (c) {
case 'p':
port = ator(optarg);
break;
case 'h':
break;
case 'v':
break;
case 'c':
break;
case 'k':
break;
default:
abort();
}
}
}
if (!port) {
port = DEFAULT_PORT;
}
log_init(stdout);
log(LOG_INFO, log_string("msg", "starting micro-chat"), log_int("port", port));
struct _u_request request;
struct _u_response response;
struct _websocket_client_handler websocket_client_handler = {NULL, NULL};
char *url;
sprintf(url, "wss://localhost:%d", port);
ulfius_init_request(&request);
ulfius_init_response(&response);
if (ulfius_set_websocket_request(&request, url, "protocol", "permessage-deflate") == U_OK) {
ulfius_add_websocket_client_deflate_extension(&websocket_client_handler);
request.check_server_certificate = 0;
if (ulfius_open_websocket_client_connection(&request, &websocket_manager_callback, websocket_user_data, &websocket_incoming_message_callback, websocket_user_data, &websocket_onclose_callback, websocket_user_data, &websocket_client_handler, &response) == U_OK) {
//y_log_message(Y_LOG_LEVEL_DEBUG, "Wait for user to press <enter> to close the program");
getchar();
ulfius_websocket_client_connection_close(&websocket_client_handler);
//y_log_message(Y_LOG_LEVEL_DEBUG, "Websocket closed");
} else {
//y_log_message(Y_LOG_LEVEL_ERROR, "Error ulfius_open_websocket_client_connection");
o_free(websocket_user_data);
}
} else {
//y_log_message(Y_LOG_LEVEL_ERROR, "Error ulfius_set_websocket_request");
o_free(websocket_user_data);
}
ulfius_clean_request(&request);
ulfius_clean_response(&response);
return 0;
}
#endif
| ddc7584ff406b9d5adf7d0bc28fd18b7bb956be2 | [
"C",
"Makefile"
] | 2 | Makefile | briandowns/micro-chat | a254f4ea436b68375ea59bb92ac11ea6b187e152 | f64a77093e59f61948d5e6a7b14a04c1aaed7595 |
refs/heads/master | <file_sep>// Inspired by Rust Book Final Project
use std::thread;
use std::sync::mpsc;
use std::sync::mpsc::TrySendError;
use std::sync::Arc;
use std::sync::Mutex;
pub struct ThreadPool {
sender: mpsc::SyncSender<Job>,
receiver: Arc<Mutex<mpsc::Receiver<Job>>>,
id: usize, // available for debugging
}
trait FnBox {
fn call(self: Box<Self>);
}
impl<F: FnOnce()> FnBox for F {
fn call(self: Box<F>) {
(*self)()
}
}
type Job = Box<dyn FnBox + Send + 'static>;
impl ThreadPool {
/// Create a new ThreadPool.
pub fn new( ) -> ThreadPool {
let (sender, receiver) = mpsc::sync_channel(0); // rendezvous channel
let receiver = Arc::new(Mutex::new(receiver));
ThreadPool { sender, receiver, id:0 }
}
/// Execute a function in a thread.
pub fn execute<F>(&self, f: F) -> Result< (), () >
where F: FnOnce() + Send + 'static
{
let job = Box::new(f);
match self.sender.try_send(job) {
Ok(_) => Ok( () ), // rendezvous successful, job delivered
Err(e) => match e {
TrySendError::Full(job) => { // no worker available; give birth to a new one
let receiver = self.receiver.clone();
thread::spawn(move || {
job.call();
loop {
match receiver.lock().unwrap().recv() {
Ok(job) => { job.call(); },
Err(_) => { return; }
}
}
} );
Ok( () )
},
TrySendError::Disconnected(_) => Err( () )
}
}
}
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
/// run_multiple_tasks - check that they all execute and complete
fn run_multiple_tasks() {
assert_eq!(2 + 2, 4);
}
#[test]
/// run_multiple_tasks with significant sleeps
/// - check that they all execute and complete in time less than sum(sleeps)
fn run_multiple_sleepy_tasks() {
// do something!
assert_eq!(4 + 4, 8);
}
#[test]
/// run_multiple_tasks which block on external channel
/// - check that they execute and complete independently
fn run_multiple_blocking_tasks() {
// do something!
assert_eq!(4 + 2, 6);
}
}
| 1049998f4387a5b64143a78ee2764f2baca8fec5 | [
"Rust"
] | 1 | Rust | GregDavidson/unmanaged-thread-pool | d1b25daa521a228792b110a37aa8694f9cc0b77d | b1a1668bd4567c491743818371e150a0b32ed9c1 |
refs/heads/master | <file_sep>import pygame
pygame.init()
screen = pygame.display.set_mode((800, 800))
pygame.display.set_caption("Test")
screen.fill((255, 211, 0))
pygame.display.flip()
class Hero(pygame.sprite.Sprite):
def __init__(self, x, filename):
pygame.sprite.Sprite.__init__(self)
self.image = pygame.image.load('').convert_alpha()
self.rect = self.image.get_rect(center=(x, 0))
run = True
while run:
for event in pygame.event.get():
if event.type == pygame.QUIT:
run = False
pygame.quit() | fe83b3ea2e1d751ae62cf10cb75adffbcee8ca6b | [
"Python"
] | 1 | Python | Svetkina/pygame | 85c008cb611b5049f8b0997d0b2debd276e96b67 | c4401d396ca0400dac85d35e08ace02681df5073 |
refs/heads/master | <repo_name>hmtmcse/spring-boot-elasticsearch<file_sep>/settings.gradle
rootProject.name = 'spring-boot-elasticsearch'
<file_sep>/src/main/java/com/hmtmcse/sbes/springbootelasticsearch/repository/DepartmentRepository.java
package com.hmtmcse.sbes.springbootelasticsearch.repository;
import com.hmtmcse.sbes.springbootelasticsearch.entity.Department;
import org.springframework.data.elasticsearch.repository.ElasticsearchRepository;
import java.util.List;
public interface DepartmentRepository extends ElasticsearchRepository<Department, String> {
List<Department> findByName(String name);
}
<file_sep>/readme.md
# Official Document
* https://docs.spring.io/spring-data/elasticsearch/docs/current/reference/html/<file_sep>/src/main/java/com/hmtmcse/sbes/springbootelasticsearch/entity/Department.java
package com.hmtmcse.sbes.springbootelasticsearch.entity;
import lombok.Data;
import org.springframework.data.annotation.Id;
import org.springframework.data.elasticsearch.annotations.Document;
@Data
@Document(indexName = "department")
public class Department {
@Id
public String id;
public String name;
public String code;
public String description;
public String uuid;
}
| d2c2f75fd5b7cc405d53e84b15190d82434aaf05 | [
"Markdown",
"Java",
"Gradle"
] | 4 | Gradle | hmtmcse/spring-boot-elasticsearch | 465096ec8bf8618fe51c5d8a9b8024bc314befc1 | 8d6dcbcc55ed9434ee77398a7753ebaf468507ed |
refs/heads/master | <file_sep>using System;
using Microsoft.VisualStudio.TestTools.UnitTesting;
using Librarie.Data.Entities;
namespace Library.Test
{
[TestClass]
public class ScorServiceTest
{
public IScoreService _scoreService;
[TestInitialize]
public void Init()
{
_scoreService = new ScoreService();
}
[TestMethod]
public void ComputeScore_BookTypeSFBookScore5UserScore1_ShouldBe51()
{
//Arrange
var book = new Book()
{
Type = "SF",
Score = 5
};
const int userScore = 1;
//Act
int result = _scoreService.ComputeScore(book, userScore);
//Assert
Assert.AreEqual(51, result);
}
[TestMethod]
public void ComputeScore_BookTypeSFBookScore2UserScore20_ShouldBe40()
{
//Arrange
var book = new Book()
{
Type = "SF",
Score = 2
};
const int userScore = 20;
//Act
int result = _scoreService.ComputeScore(book, userScore);
//Assert
Assert.AreEqual(40, result);
}
[TestMethod]
public void ComputeScore_BookTypeSFBookScore2UserScore0_ShouldBe20()
{
//Arrange
var book = new Book()
{
Type = "SF",
Score = 2
};
const int userScore = 0;
//Act
int result = _scoreService.ComputeScore(book, userScore);
//Assert
Assert.AreEqual(20, result);
}
[TestMethod]
public void ComputeScore_BookScore2UserScore1_ShouldBe3()
{
//Arrange
var book = new Book()
{
Type = "*",
Score = 2
};
const int userScore = 1;
//Act
int result = _scoreService.ComputeScore(book, userScore);
//Assert
Assert.AreEqual(3, result);
}
[TestMethod]
public void ComputeScore_BookTypeCopiiBookScore1UserScore5_ShouldBe7()
{
//Arrange
var book = new Book()
{
Type = "Copii",
Score = 1
};
const int userScore = 5;
//Act
int result = _scoreService.ComputeScore(book, userScore);
//Assert
Assert.AreEqual(7, result);
}
[TestMethod]
public void ComputeScore_BookTypeCopiiBookScore2UserScore0_ShouldBe4()
{
//Arrange
var book = new Book()
{
Type = "Copii",
Score = 2
};
const int userScore = 0;
//Act
int result = _scoreService.ComputeScore(book, userScore);
//Assert
Assert.AreEqual(4, result);
}
}
internal class ScoreService : IScoreService
{
public int ComputeScore(Book book, int userScore)
{
if(book.Type == "SF")
{
return 10 * book.Score + userScore;
}
else
{
if (book.Type == "Copii")
{
return 2 * book.Score + userScore;
}
}
return book.Score + userScore;
}
}
public interface IScoreService
{
int ComputeScore(Book book, int userScore);
}
}
<file_sep>using System;
using System.Collections.Generic;
using System.Linq;
using System.Threading.Tasks;
using Librarie.Data.Entities;
namespace Librarie.Models.LibraryViewModels
{
public class LibraryViewModel
{
private List<Book> books1;
public InformationsViewModel informations { set; get; }
public List<BookViewModel> books { set; get; }
public List<Tranzaction> tranzactions { set; get; }
public LibraryViewModel()
{
informations = new InformationsViewModel();
books = new List<BookViewModel>();
}
public LibraryViewModel(List<Book> Books)
{
informations = new InformationsViewModel();
books = new List<BookViewModel>();
foreach(var book in Books)
{
var bookViewModel = new BookViewModel()
{
id = book.id,
title = book.title,
author = book.author,
numberOfCopies = book.numberOfCopies
};
books.Add(bookViewModel);
}
tranzactions = new List<Tranzaction>();
}
public LibraryViewModel(List<Book> Books, List<Tranzaction> Tranzactions)
{
informations = new InformationsViewModel();
books = new List<BookViewModel>();
foreach(var book in Books)
{
var bookViewModel = new BookViewModel()
{
id = book.id,
title = book.title,
author = book.author,
numberOfCopies = book.numberOfCopies
};
books.Add(bookViewModel);
}
tranzactions = new List<Tranzaction>();
foreach(var tranzaction in Tranzactions)
{
var tranzactie = new Tranzaction()
{
Id = tranzaction.Id,
UserId = tranzaction.UserId,
BookId = tranzaction.BookId
};
tranzactions.Add(tranzactie);
}
}
}
}
<file_sep>using System;
using System.Collections.Generic;
using System.Linq;
using System.Threading.Tasks;
using Librarie.Data.Entities;
using Librarie.Data;
using Microsoft.EntityFrameworkCore;
namespace Librarie.Services
{
public class LibraryService : ILibraryService
{
private ApplicationDbContext _applicationDbService;
public LibraryService(ApplicationDbContext applicationDbService)
{
_applicationDbService = applicationDbService;
}
public List<Book> GetBooks()
{
return _applicationDbService.Books.ToList();
}
public List<Tranzaction> GetTranzactions()
{
return _applicationDbService.Tranzactions.Include(item => item.User).ToList();
}
public bool Borrow(string userId, int id)
{
_applicationDbService.Tranzactions.Add(new Tranzaction
{
UserId = userId,
BookId = id
});
var book = _applicationDbService.Books.Single(t => t.id == id);
book.numberOfCopies--;
_applicationDbService.Books.Update(book);
return _applicationDbService.SaveChanges() == 2;
}
public bool Return(int id,string userId)
{
var tranzaction = _applicationDbService.Tranzactions.Single(t => t.BookId == id && t.UserId == userId);
var book = _applicationDbService.Books.Single(t => t.id == id);
book.numberOfCopies++;
_applicationDbService.Books.Update(book);
_applicationDbService.Tranzactions.Remove(tranzaction);
return _applicationDbService.SaveChanges() == 2;
}
}
}
<file_sep>using System;
using System.Collections.Generic;
using System.Linq;
using System.Threading.Tasks;
namespace Librarie.Models.LibraryViewModels
{
public class BorrowViewModel
{
public bool isSuccessful { get; set; }
public string BookName { get; set; }
}
}
<file_sep>using System;
using System.Collections.Generic;
using System.Linq;
using System.Threading.Tasks;
namespace Librarie.Models.LibraryViewModels
{
public class BookViewModel
{
public int id { set; get; }
public String title { set; get; }
public String author { set; get; }
public int numberOfCopies { set; get; }
}
}
<file_sep>using System;
using System.Collections.Generic;
using System.Linq;
using System.Threading.Tasks;
namespace Librarie.Models.LibraryViewModels
{
public class InformationsViewModel
{
public int NumberOfBooks { set; get; }
public DateTime Date { set; get; }
}
}
<file_sep>using System;
using System.Collections.Generic;
using System.Linq;
using System.Threading.Tasks;
using Librarie.Models;
using Microsoft.AspNetCore.Mvc;
using Librarie.Models.LibraryViewModels;
using Librarie.Services;
using Microsoft.AspNetCore.Authorization;
using System.Security.Claims;
namespace Librarie.Controllers
{
[Authorize]
public class LibraryController : Controller
{
private ILibraryService _libraryService;
public LibraryController(ILibraryService libraryService)
{
_libraryService = libraryService;
}
public IActionResult Index()
{
var books = _libraryService.GetBooks(); //luam cartile din DB prin intermediul unui LibraryService
var tranzactions = _libraryService.GetTranzactions();
var model = new LibraryViewModel(books,tranzactions);
model.informations.NumberOfBooks = model.books.Count;
model.informations.Date = DateTime.Now;
return View(model);
}
public IActionResult Borrow(int id)
{
var userId = HttpContext.User.FindFirstValue(ClaimTypes.NameIdentifier);
bool isSuccessful = _libraryService.Borrow(userId, id);
var book = _libraryService.GetBooks().Single(item => item.id == id);
var borrowViewModel = new BorrowViewModel
{
isSuccessful = isSuccessful,
BookName = book.title
};
return View(borrowViewModel);
}
public IActionResult Return(int id)
{
var userId = HttpContext.User.FindFirstValue(ClaimTypes.NameIdentifier);
bool isSuccessful = _libraryService.Return(id, userId);
var returnViewModel = new ReturnViewModel()
{
IsSuccessful = isSuccessful,
BookName = _libraryService.GetBooks().Single(t => t.id == id)?.title
};
return View(returnViewModel);
}
}
}<file_sep>using Librarie.Data.Entities;
using System;
using System.Collections.Generic;
using System.Linq;
using System.Threading.Tasks;
namespace Librarie.Services
{
public interface ILibraryService
{
List<Book> GetBooks();
List<Tranzaction> GetTranzactions();
bool Borrow(string userId, int id);
bool Return(int id, string userId);
}
}
| 9402cbc8a9746c8523bee28bf3ca01c894323cf0 | [
"C#"
] | 8 | C# | CosminLivinti/Practica-2017 | f46844e68336917e73c01bcd348775f749feaa35 | a8bbe57279f949468212a3279975301ccd696ae4 |
refs/heads/master | <file_sep>angular.module('app', ['ionic'])
.config(function($stateProvider, $urlRouterProvider){
'use strict';
$stateProvider
.state('tabs', {
url: '/tabs',
abstract: true,
templateUrl: 'views/tabs.html',
controller: 'TabsCtrl'
})
.state('tabs.twitts', {
url: '/twitts',
views: {
'twitts-tab': {
templateUrl: 'views/twitts.html',
controller: 'TwittsCtrl'
}
}
})
.state('tabs.twitt', {
url: '/twitt/:id',
views: {
'twitts-tab': {
templateUrl: 'views/twitt.html',
controller: 'TwittCtrl'
}
}
})
.state('tabs.notifications', {
url: '/notifications',
views: {
'notifications-tab': {
templateUrl: 'views/notifications.html',
controller: 'NotificationsCtrl'
}
}
})
.state('tabs.profil', {
url: '/profil',
views: {
'profil-tab': {
templateUrl: 'views/profil.html',
controller: 'ProfilCtrl'
}
}
});
$urlRouterProvider.otherwise('/tabs/twitts');
})
.run(function($ionicPlatform) {
'use strict';
$ionicPlatform.ready(function() {
if(window.cordova && window.cordova.plugins.Keyboard) {
cordova.plugins.Keyboard.hideKeyboardAccessoryBar(true);
}
if(window.StatusBar) {
StatusBar.styleDefault();
}
});
});
<file_sep># Twitter app
Ionic composant tour building a twitter client.
Find explications on my [blog post](http://loic.knuchel.org/blog/2015/02/26/faire-un-client-twitter-avec-ionic/) (french).
App Screenshot :
## Getting started
- [Install Ionic](http://ionicframework.com/getting-started/)
- `git clone https://github.com/loicknuchel/blog-twitter-app` : Clone this repo
- `cd blog-twitter-app && ionic serve` : launch app on desktop
- go to [http://127.0.0.1:8100/](http://127.0.0.1:8100/)
Run on device :
- `ionic plugin add org.apache.cordova.device org.apache.cordova.console com.ionic.keyboard` : add standard plugins
- `ionic add platform [android/ios]` : app wanted platform
- `ionic run android` : run on your device (will launch emulator if device is not found)
| 51e0ec565fcb5b9c4d4150e38343cd28e8acedde | [
"JavaScript",
"Markdown"
] | 2 | JavaScript | loicknuchel/blog-twitter-app | 02c37f3e1728e6d360e5199dae58b6f0559aa2ee | 357239dc1e4351741680185a6ca8d39d766a1ed4 |
refs/heads/master | <repo_name>lybf/MPSquare<file_sep>/app/src/main/java/net/lybf/chat/utils/ChatException.java
package net.lybf.chat.utils;
import android.util.Log;
public class ChatException extends Exception
{
public static final int REFRESH_FAILED=1;
public static final int COUNT_FAILED=2;
private int code;
private String msg;
private String TAG="ChatException";
public ChatException(String info){
super(info);
if(info!=null)
this.msg=info;
this.code=0;
}
public ChatException(Exception e){
super(e);
this.msg="其他错误";
this.code=0;
}
public ChatException(String info,int code){
super(info);
this.msg=info;
this.code=code;
}
public ChatException(Exception e,String msg){
super(msg,e);
if(msg!=null)
this.msg=msg;
this.code=0;
}
public ChatException(Throwable e,String msg){
super(msg,e);
if(msg!=null)
this.msg=msg;
this.code=0;
}
public ChatException(Exception e,int code,String message){
super(message,e);
if(code>-1)
this.code=code;
if(message!=null)
this.msg=message;
}
public int getCode(){
return this.code;
}
public String getMessage(){
return this.msg;
}
public String toString(){
return String.format("code:%s,error:%s",code,msg);
}
@Override
public void printStackTrace(){
StringBuilder build=new StringBuilder();
build.append(new StackTraceInfo().init(this).getMessage().toString());
Log.e(TAG,build.toString());
}
}
<file_sep>/app/src/main/java/net/lybf/chat/maps/MainTools.java
package net.lybf.chat.maps;
import android.graphics.Bitmap;
public class MainTools
{
//CreatedAt 2017/4/22 13:00
private String TAG;
private Bitmap draw;
private String describe;
public MainTools setTAG(String Tag){
this.TAG=Tag;
return this;
}
public String getTAG(){
return this.TAG;
}
public MainTools setBitmap(Bitmap draw){
this.draw=draw;
return this;
}
public Bitmap getBitmap(){
return this.draw;
}
public MainTools setDescribe(String describe){
this.describe=describe;
return this;
}
public String getDescribe(){
return this.describe;
}
}
<file_sep>/app/src/main/java/net/lybf/chat/utils/CommentCount.java
package net.lybf.chat.utils;
import cn.bmob.v3.BmobQuery;
import cn.bmob.v3.exception.BmobException;
import cn.bmob.v3.listener.CountListener;
import net.lybf.chat.bmob.Comment;
import net.lybf.chat.system.Utils;
import net.lybf.chat.bmob.Post;
public class CommentCount
{
private Post id;
private CommentCountListener listener;
public interface CommentCountListener
{
void done(int i,BmobException e);
}
public CommentCount setPost(Post postid){
id=postid;
return this;
}
public void count(CommentCountListener listene){
this.listener=listene;
BmobQuery<Comment> bmobQuery= new BmobQuery<Comment>();
bmobQuery.addWhereEqualTo("post",id);
boolean cache=bmobQuery.hasCachedResult(Comment.class);
Class css=this.getClass();
Utils.print(css,"has cache:"+cache);
if(new Network().isConnected())
bmobQuery.setCachePolicy(BmobQuery.CachePolicy.NETWORK_ELSE_CACHE);
else
bmobQuery.setCachePolicy(BmobQuery.CachePolicy.CACHE_ONLY);
bmobQuery.count(Comment.class,new CountListener(){
@Override
public void done(Integer p1,BmobException p2){
if(p2==null){
Utils.print(String.format("帖子id:%s评论数:%s\n",id,p1));
listener.done(p1,null);
}else{
Utils.print(String.format("帖子id:%s评论数:%s\n",id,p1));
listener.done(0,p2);
}
}
});
}
}
<file_sep>/app/src/main/java/net/lybf/chat/receiver/PushMessage.java
package net.lybf.chat.receiver;
import android.app.Notification;
import android.app.NotificationManager;
import android.app.PendingIntent;
import android.content.BroadcastReceiver;
import android.content.Context;
import android.content.Intent;
import android.os.Bundle;
import android.support.v4.app.NotificationCompat;
import android.util.Log;
import android.widget.Toast;
import net.lybf.chat.MainApplication;
import net.lybf.chat.R;
import net.lybf.chat.system.Utils;
import net.lybf.chat.ui.MainActivity;
public class PushMessage extends BroadcastReceiver
{
@Override
public void onReceive(Context context,Intent intent){
MainApplication app= (MainApplication)context.getApplicationContext();
app.getLogcat().println(this,"接收到推送信息");
String action=intent.getAction();
Bundle bun=intent.getBundleExtra("data");
Utils.print(this.getClass(),"action:"+action);
if(action.equals("cn.bmob.push.action.MESSAGE"))
pushMessage(context,intent.getStringExtra("msg"));
else if(action.equals("net.lybf.chat.action.push"))
updateApp(context,bun.getString("title"),bun.getString("message"),null);
}
public void pushMessage(Context context,String message){
Log.i("MPSquare","收到的推送消息："+message);
Toast.makeText(context.getApplicationContext(),""+message,Toast.LENGTH_LONG).show();
Intent i = new Intent();
i.setClass(context,MainActivity.class);
i.setFlags(Intent.FLAG_ACTIVITY_SINGLE_TOP);
PendingIntent pi = PendingIntent.getActivity(context,0,i,0);
NotificationCompat.Builder mBuilder =new NotificationCompat.Builder(context)
.setTicker("MPSquare收到消息推送")
.setSmallIcon(R.drawable.ic_launcher)
.setContentTitle("消息")
.setContentText(message)
.setAutoCancel(true)
.setDefaults(Notification.DEFAULT_SOUND|Notification.DEFAULT_VIBRATE)
.setContentIntent(pi);
// 发送通知
NotificationManager nm = (NotificationManager) context.getSystemService(Context.NOTIFICATION_SERVICE);
Notification n = mBuilder.build();
nm.notify(message.hashCode(),n);
}
private void updateApp(Context context,String title,String text,String ApkFile){
Intent intent= new Intent();
intent.setClass(context,MainActivity.class);
intent.setFlags(Intent.FLAG_ACTIVITY_SINGLE_TOP);
PendingIntent Pi=
PendingIntent.getActivity(context,0,intent,0);
NotificationCompat.Builder mBuilder =new NotificationCompat.Builder(context)
.setTicker("应用更新")
.setSmallIcon(R.drawable.ic_launcher)
.setContentTitle(title)
.setContentText(text)
.setAutoCancel(true)
.setDefaults(Notification.DEFAULT_SOUND|Notification.DEFAULT_VIBRATE)
.setContentIntent(Pi);
// 发送通知
NotificationManager nm = (NotificationManager) context.getSystemService(context.NOTIFICATION_SERVICE);
Notification nms= mBuilder.build();
String str=title+text+ApkFile;
nm.notify(str.hashCode(),nms);
}
}
<file_sep>/app/src/main/java/net/lybf/chat/utils/UserManager.java
package net.lybf.chat.utils;
import android.content.Context;
import android.graphics.Bitmap;
import cn.bmob.v3.BmobQuery;
import cn.bmob.v3.BmobUser;
import cn.bmob.v3.datatype.BmobFile;
import cn.bmob.v3.exception.BmobException;
import cn.bmob.v3.listener.DownloadFileListener;
import cn.bmob.v3.listener.FindListener;
import com.squareup.picasso.Picasso;
import java.io.File;
import java.io.IOException;
import net.lybf.chat.bmob.MyUser;
import net.lybf.chat.system.Paths;
import net.lybf.chat.system.Utils;
public class UserManager
{
//CreatedAt 2017/4/29/2:03
private MyUser use;
private Context ctx;
private UserManager(){
}
public UserManager(Context ctx){
this.ctx=ctx;
}
public UserManager(Context context,MyUser user){
this.ctx=context;
this.use=user;
}
public static UserManager with(Context context){
return new UserManager(context);
}
public static UserManager with(Context context,MyUser user){
return new UserManager(context,user);
}
public static MyUser getCurrentUser(){
MyUser user=BmobUser.getCurrentUser(MyUser.class);
return user;
}
public UserManager setUser(MyUser use){
this.use=use;
return this;
}
public UserManager DownLoadIcon(){
DownLoadIcon(this.use);
return this;
}
public UserManager DownLoadIcon(MyUser user,DownloadFileListener listener){
BmobFile file=user.getIcon();
if(file!=null){
File fp=new File(Paths.USER_PATH+"/"+user.getObjectId()+"/head/"+file.getFilename());
file.download(fp,listener);
}
return this;
}
public UserManager DownLoadIcon(MyUser user){
if(user!=null){
BmobFile file=user.getIcon();
if(file==null)
return this;
final String filename=file.getFilename();
File f=new File(Paths.USER_PATH+"/"+user.getObjectId()+"/head/"+filename);
if(!f.exists()){
file.download(f,new DownloadFileListener(){
@Override
public void done(String p1,BmobException p2){
if(p2==null){
print(filename+" DownloadSuccess");
}else{
print(filename+" DownloadError -->"+p2.toString());
}
}
@Override
public void onProgress(Integer p1,long p2){}
});
}
}
return this;
}
public Bitmap getIcon(){
return getIcon(use);
}
public Bitmap getIcon(MyUser user){
if(user==null)
return null;
BmobFile file=user.getIcon();
if(file==null)
return null;
final String filename=file.getFilename();
File f=new File(Paths.USER_PATH+"/"+user.getObjectId()+"/head/"+filename);
if(!f.exists())
DownLoadIcon(user);
Bitmap mp = null;
if(f.exists()){
try{
mp=Picasso.with(ctx).load(f).get();
}
catch(IOException e){
e.printStackTrace();
}
}
return mp;
}
public File getIconFile(){
return getIconFile(use);
}
public File getIconFile(MyUser user){
if(user==null)
return null;
BmobFile file=user.getIcon();
if(file==null)
return null;
final String filename=file.getFilename();
File f=new File(Paths.USER_PATH+"/"+user.getObjectId()+"/head/"+filename);
if(!f.exists())
DownLoadIcon(user);
return f;
}
public boolean isEmailVerified(){
return isEmailVerified(use);
}
/*
邮箱是否验证过
*/
public static boolean isEmailVerified(MyUser user){
boolean verify=false;
if(!(user.getEmail()==null))
if(user.getEmailVerified())
verify=true;
return verify;
}
/*
以用户名查询用户信息
*/
public static void queryUserByName(String name,FindListener<MyUser> listener){
queryUserByKeyValue("username",name,listener);
}
/*
以用户唯一id查询用户信息
*/
public static void queryUserById(String id,FindListener<MyUser> listener){
queryUserByKeyValue("objectid",id,listener);
}
/*
以key-value形式查询用户信息
*/
public static void queryUserByKeyValue(String key,String value,FindListener<MyUser> listener){
BmobQuery<MyUser> query=new BmobQuery<MyUser>();
query.addWhereEqualTo(key,value);
query.findObjects(listener);
}
private void print(String e){
Utils.print(this.getClass(),e);
}
}
<file_sep>/app/src/main/java/net/lybf/chat/bmob/Comment.java
package net.lybf.chat.bmob;
import cn.bmob.v3.BmobObject;
import java.util.ArrayList;
import java.util.List;
import net.lybf.chat.bmob.MyUser;
import net.lybf.chat.bmob.images;
public class Comment extends BmobObject
{
//内容
private String content;
//图1～图3
private images image,image2,image3;
//所属贴子
private Post post;
//用户
private MyUser user;
public Comment(){
}
public Comment(String content,images image,images image2,
images image3,Post post,MyUser user){
this.content=content;
this.image=image;
this.image2=image2;
this.image3=image3;
this.post=post;
this.user=user;
}
//获取内容
public String getMessage(){
return content;
}
//修改内容(设置内容)
public void setMessage(String str){
content=str;
}
//获取用户
public MyUser getUser(){
return user;
}
//设置用户
public void setUser(MyUser user){
this.user=user;
}
//获取所属贴子
public Post getPost(){
return post;
}
//设置所属贴子
public void setPost(Post p){
this.post=p;
}
//获取图片1
public images getImage(){
if(image!=null)
return image;
return null;
}
//设置图1
public void setImage(images f){
image=f;
}
public images getImage2(){
return image2;
}
public void setImage2(images f){
image2=f;
}
public images getImage3(){
return image3;
}
public void setImage3(images f){
image3=f;
}
public List<images> getImages(){
List<images> list=new ArrayList<images>();
list.add(image);
list.add(image2);
list.add(image3);
try{
for(int c=list.size()-1;c>0;c--){
if(list.get(c)==null){
list.remove(c);
}
}
}catch(Exception e){
e.printStackTrace();
}
return list;
}
}
<file_sep>/app/src/main/java/net/lybf/chat/maps/Robot.java
package net.lybf.chat.maps;
import java.util.ArrayList;
import net.lybf.chat.maps.RobotList;
public class Robot
{
//CreatedAt 2017/4/23 16:50
public static final int FLAG_ROBOT=0;
public static final int FLAG_MYSELF=1;
private int flag;
private int code;
private String text;
private String url;
private String name;
private ArrayList<RobotList> list;
public Robot setName(String name){
this.name=name;
return this;
}
public String getName(){
return this.name;
}
public Robot setFlag(int flag){
this.flag=flag;
return this;
}
public int getFlag(){
return this.flag;
}
public Robot setCode(int code){
this.code=code;
return this;
}
public int getCode(){
return this.code;
}
public Robot setText(String text){
this.text=text;
return this;
}
public String getText(){
return this.text;
}
public Robot setUrl(String url){
this.url=url;
return this;
}
public String getUrl(){
return this.url;
}
public Robot setList(ArrayList<RobotList> list){
this.list=list;
return this;
}
public ArrayList<RobotList> getList(){
return this.list;
}
}
<file_sep>/app/build.gradle
apply plugin: 'com.android.application'
applicationId 'net.lybf.chat'
android {
compileSdkVersion 19
buildToolsVersion "25.0.0"
sourceSets{
main.jniLibs.srcDirs = ['jnilibs']
}
defaultConfig {
applicationId "net.lybf.chat"
minSdkVersion 19
targetSdkVersion 23
versionCode 8
versionName "1.4.4"
}
signingConfigs {
release {
storeFile file("/sdcard/lybf.jks")
storePassword "<PASSWORD>"
keyAlias "lybf"
keyPassword "<PASSWORD>"
}
debug {
storeFile file("/sdcard/lybf.jks")
storePassword "<PASSWORD>"
keyAlias "lybf"
keyPassword "<PASSWORD>"
}
}
buildTypes {
release {
minifyEnabled false
proguardFiles getDefaultProguardFile('proguard-android.txt'), 'proguard-rules.pro'
}
debug {
proguardFiles getDefaultProguardFile('proguard-android.txt'), 'proguard-rules.pro'
minifyEnabled true
}
}
packagingOptions{
}
lintOptions{
abortOnError false;
}
}
dependencies {
compile project(':app:SwipeBackLayout')
compile project(':app:MaterialDesign')
compile 'com.android.support:support-v4:23.4.0'
compile 'com.android.support:cardview-v7:23.4.0'
compile 'com.android.support:design:23.4.0'
compile 'com.android.support:appcompat-v7:23.4.0'
compile fileTree(dir: 'libs', include: ['*.jar'])
}
<file_sep>/app/src/main/java/net/lybf/chat/utils/Network.java
package net.lybf.chat.utils;
import android.content.Context;
import android.net.ConnectivityManager;
import android.net.NetworkInfo;
import java.io.BufferedReader;
import java.io.IOException;
import java.io.InputStreamReader;
import java.io.OutputStreamWriter;
import java.net.HttpURLConnection;
import java.net.URL;
import net.lybf.chat.MainApplication;
import net.lybf.chat.maps.Robot;
public class Network
{
private Context ctx;
public Network(Context c){
ctx=c;
}
public Network(){
ctx=new MainApplication().getContext();
}
public boolean isConnected(){
ConnectivityManager cm=(ConnectivityManager) ctx.getSystemService(Context.CONNECTIVITY_SERVICE);
NetworkInfo info=cm.getActiveNetworkInfo();
if(info!=null)
return info.isConnected();
else
return false;
}
public boolean isConnectedOrConnecting(){
ConnectivityManager cm = (ConnectivityManager) ctx.getSystemService(Context.CONNECTIVITY_SERVICE);
NetworkInfo netInfo = cm.getActiveNetworkInfo();
if(netInfo!=null&&netInfo.isConnectedOrConnecting())
return true;
else
return false;
}
public interface TuLingRobotListener
{
void done(Robot robot);
}
//发送Post
public void sendPost(final String param,final String url){
new Thread(new Thread(){
public void run(){
OutputStreamWriter out = null;
BufferedReader in = null;
StringBuilder result = new StringBuilder();
try{
URL realUrl = new URL(url);
HttpURLConnection conn = (HttpURLConnection) realUrl
.openConnection();
conn.setDoOutput(true);
conn.setDoInput(true);
conn.setUseCaches(false);
conn.setRequestMethod("POST");
conn.setConnectTimeout(50000);
conn.setReadTimeout(50000);
conn.setRequestProperty("Content-Type","application/json");
conn.setRequestProperty("Accept","application/json");
conn.setRequestProperty("Authorization","token");
conn.setRequestProperty("tag","htc_new");
conn.connect();
out=new OutputStreamWriter(conn.getOutputStream(),"UTF-8");
out.write(param);
out.flush();
out.close();
//
in=new BufferedReader(new InputStreamReader(
conn.getInputStream(),"UTF-8"));
String line = "";
while((line=in.readLine())!=null){
result.append(line);
}
}catch(Exception e){
e.printStackTrace();
}finally{
try{
if(out!=null){
out.close();
}
if(in!=null){
in.close();
}
}catch(IOException ex){
ex.printStackTrace();
}
}
}
}
).start();
//return robot;
}
}
<file_sep>/app/src/main/java/net/lybf/chat/system/settings.java
package net.lybf.chat.system;
import android.content.Context;
import android.icu.text.SimpleDateFormat;
import android.icu.util.TimeZone;
import com.google.gson.Gson;
import com.google.gson.GsonBuilder;
import com.google.gson.JsonElement;
import com.google.gson.JsonParser;
import java.io.File;
import java.io.FileInputStream;
import java.io.FileOutputStream;
import java.io.InputStream;
import java.util.Date;
import net.lybf.chat.MainApplication;
import net.lybf.chat.utils.Logcat;
import net.lybf.chat.utils.StackTraceInfo;
import org.json.JSONException;
import org.json.JSONObject;
public class settings
{
//根
private JSONObject root;
//Context
private static Context ctx;
//文件
private static File file;
//设置文件路径
private static final String path=Paths.SETTINGS_PATH;
//Assets-main.json
private static final String res="settings/main.json";
private static Logcat logcat;
private static settings settings;;
private settings(){
if(logcat==null)
logcat=MainApplication.getInstance().getLogcat();
}
public static settings getInstance(){
if(settings==null)
settings=new settings();
return settings;
}
public void init(Context context){
this.ctx=context;
init();
}
private synchronized void init(){
file=new File(path);
if(!file.getParentFile().exists())
file.getParentFile().mkdirs();
if(!file.exists()){
try{
InputStream input=ctx.getAssets().open(res);
FileOutputStream out=new FileOutputStream(file);
byte[] by=new byte[input.available()];
input.read(by);
root=new JSONObject(new String(by));
Date d=new Date(System.currentTimeMillis());
SimpleDateFormat p=new SimpleDateFormat(BmobUtils.BMOB_DATE_TYPE);
p.setTimeZone(TimeZone.getTimeZone("GMT+08:00"));
String date=p.format(d);
root.put("updatedAt",date);
root.put("createdAt",date);
save();
// out.write(format(ar.toString()).getBytes());
}catch(Exception e){
print(e);
}
}
importSettings(this.file);
// importSettings(file);
}
public synchronized void importSettings(File file){
if(file.exists()&&file.length()>0){
try{
InputStream in=new FileInputStream(file);
byte[] b=new byte[in.available()];
in.read(b);
root=new JSONObject(new String(b));
in.close();
}catch(Exception e){
print(e);
}
}else{
init();
}
}
public synchronized void setRandomBackground(boolean can)throws JSONException{
set("RandomBackground",can);
save();
}
public boolean getRandomBackground(){
boolean b= get("RandomBackground");
return b;
}
public boolean isDark(){
boolean b=get("DarkTheme");
return b;
}
public synchronized void setDarkTheme(boolean b)throws JSONException{
set("DarkTheme",b);
save();
}
public String getUpdatedAt(){
return (String)get("updatedAt");
}
public String getCreatedAt(){
return (String)get("createdAt");
}
private synchronized void set(String key,Object object){
try{
root.put(key,object);
}catch(JSONException e){
e.printStackTrace();
logcat.println(this,StackTraceInfo.getMessage(e).toString());
}
}
private synchronized Object get(String key){
Object result = null;
try{
result=root.opt(key);
}catch(Exception e){
e.printStackTrace();
logcat.println(this,StackTraceInfo.getMessage(e).toString());
}
return result;
}
public void refresh(){
init();
}
public String format(){
String result=format(root.toString());
return result;
}
public String format(String string){
Date d=new Date(System.currentTimeMillis());
SimpleDateFormat p=new SimpleDateFormat(BmobUtils.BMOB_DATE_TYPE);
p.setTimeZone(TimeZone.getTimeZone("GMT+08:00"));
String date=p.format(d);
print("date:"+date);
try{
root.put("updatedAt",""+date);
}catch(JSONException e){
Utils.print(this.getClass(),e);
}
Gson gson3 = new GsonBuilder().setPrettyPrinting().create();
JsonParser jp = new JsonParser();
JsonElement je = jp.parse(""+string);
String format= gson3.toJson(je);
return format;
}
public synchronized void save(){
try{
FileOutputStream out=new FileOutputStream(file);
out.write(format().getBytes());
}catch(Exception e){
print(e);
}
}
public interface SaveListener
{
void done(Exception e);
}
private SaveListener savelistener;
public synchronized void save(SaveListener listener){
savelistener=listener;
try{
FileOutputStream out=new FileOutputStream(file);
out.write(format().getBytes());
if(savelistener!=null)
savelistener.done(null);
}catch(Exception e){
print(e);
savelistener.done(e);
}
}
private void print(Object o){
Utils.print(this.getClass(),o);
}
}
<file_sep>/app/src/main/java/net/lybf/chat/services/MyAccessibilityServer.java
package net.lybf.chat.services;
import android.accessibilityservice.AccessibilityService;
import android.content.Intent;
import android.content.res.Configuration;
import android.database.DatabaseErrorHandler;
import android.database.sqlite.SQLiteDatabase;
import android.view.KeyEvent;
import android.view.accessibility.AccessibilityEvent;
import java.io.FileInputStream;
import java.io.FileNotFoundException;
import java.io.FileOutputStream;
public class MyAccessibilityServer extends AccessibilityService
{
@Override
public void onStart(Intent intent,int startId){
super.onStart(intent,startId);
}
@Override
public void onCreate(){
super.onCreate();
}
@Override
public void onDestroy(){
super.onDestroy();
}
@Override
public void onTaskRemoved(Intent rootIntent){
super.onTaskRemoved(rootIntent);
}
@Override
public void onConfigurationChanged(Configuration newConfig){
super.onConfigurationChanged(newConfig);
}
@Override
public FileInputStream openFileInput(String name)throws FileNotFoundException{
return super.openFileInput(name);
}
@Override
public FileOutputStream openFileOutput(String name,int mode)
throws FileNotFoundException{
return super.openFileOutput(name,mode);
}
@Override
public int onStartCommand(Intent intent,int flags,int startId){
return super.onStartCommand(intent,flags,startId);
}
@Override
public SQLiteDatabase openOrCreateDatabase(String name,int mode,SQLiteDatabase.CursorFactory factory){
return super.openOrCreateDatabase(name,mode,factory);
}
@Override
public SQLiteDatabase openOrCreateDatabase(String name,int mode,SQLiteDatabase.CursorFactory factory,DatabaseErrorHandler errorHandler){
return super.openOrCreateDatabase(name,mode,factory,errorHandler);
}
@Override
protected void onServiceConnected(){
super.onServiceConnected();
}
@Override
public boolean onUnbind(Intent intent){
return super.onUnbind(intent);
}
@Override
public void onRebind(Intent intent){
super.onRebind(intent);
}
@Override
protected boolean onGesture(int gestureId){
return super.onGesture(gestureId);
}
@Override
protected boolean onKeyEvent(KeyEvent event){
return super.onKeyEvent(event);
}
@Override
public void onAccessibilityEvent(AccessibilityEvent event){
}
@Override
public void onInterrupt(){
}
}
<file_sep>/app/src/main/java/net/lybf/chat/ui/SettingsActivity.java
package net.lybf.chat.ui;
import android.content.Context;
import android.os.Bundle;
import android.support.v7.app.ActionBar;
import android.support.v7.widget.Toolbar;
import android.view.MenuItem;
import android.widget.FrameLayout;
import java.util.HashMap;
import net.lybf.chat.MainApplication;
import net.lybf.chat.R;
import net.lybf.chat.activity.MPSActivity;
import net.lybf.chat.fragment.SettingsFragment;
import net.lybf.chat.system.ActivityResultCode;
import net.lybf.chat.system.Utils;
import net.lybf.chat.system.settings;
import org.json.JSONException;
public class SettingsActivity extends MPSActivity
{
// settings set;
public static Context ctx;
private MainApplication app;
private settings set;
private SettingsFragment sf;
private HashMap<String,Object> hash;
@Override
protected void onCreate(Bundle savedInstanceState){
super.onCreate(savedInstanceState);
ctx=this;
app=(MainApplication) getApplication();
set=app.getSettings();
// onRetainCustomNonConfigurationInstance();
hash=(HashMap<String,Object>) getLastCustomNonConfigurationInstance();
if(hash==null)
hash=onRetainCustomNonConfigurationInstance();
initView();
}
@Override
protected void onPause(){
super.onPause();
}
@Override
protected void onDestroy(){
if(hash.get("theme")!=set.isDark())
this.setResult(ActivityResultCode.SETTINGS_CHANGE);
super.onDestroy();
}
@Override
public HashMap<String,Object> onRetainCustomNonConfigurationInstance(){
super.onRetainCustomNonConfigurationInstance();
HashMap<String,Object> hm=new HashMap<String,Object>();
hm.put("theme",set.isDark());
System.out.println("HashMap init");
return hm;
}
@Override
public void onSaveInstanceState(Bundle outState){
super.onSaveInstanceState(outState);
}
public void initView(){
// set=app.getSettings();
if(set.isDark()){
setTheme(R.style.DarkTheme);
}else{
setTheme(R.style.LightTheme);
}
setContentView(R.layout.activity_settings);
init();
}
private Toolbar bar;
private FrameLayout fm;
public void init(){
bar=(Toolbar)findViewById(R.id.toolbar_settings);
setSupportActionBar(bar);
ActionBar ab= getSupportActionBar();
ab.setDisplayHomeAsUpEnabled(true);
try{
fm=(FrameLayout)findViewById(R.id.settings_framelayout);
sf=new SettingsFragment();
//getFragmentManager().beginTransaction().hide(sf);
getFragmentManager().beginTransaction().replace(R.id.settings_framelayout,sf).commit();
sf.setContext(this);
sf.setThemeChangeListener(new SettingsFragment.ThemeChange(){
public void change(boolean bool){
try{
set.setDarkTheme(bool);
// set.updateTheme();
set.save(new settings.SaveListener(){
@Override
public void done(Exception e){
if(e==null)
print("Success");
else
new Utils().print(this.getClass(),e);
}
});
}catch(JSONException e){
new Utils().print(this.getClass(),e);
}
recreate();
SettingsActivity.this.setResult(ActivityResultCode.SETTINGS_CHANGE);
}
});
}catch(Exception e){
print(e);
}
}
@Override
public void onBackPressed(){
if(hash.get("theme")!=set.isDark())
setResult(ActivityResultCode.SETTINGS_CHANGE);
this.finish();
super.onBackPressed();
}
@Override
public boolean onOptionsItemSelected(MenuItem item){
switch(item.getItemId()){
case android.R.id.home:
if(hash.get("theme")!=set.isDark())
this.setResult(ActivityResultCode.SETTINGS_CHANGE);
finish();
break;
}
return super.onOptionsItemSelected(item);
}
private void print(Object e){
Utils.print(this.getClass(),e);
// new Utils().print(this.getClass(),e);
}
}
<file_sep>/app/src/main/java/net/lybf/chat/activity/MPSActivity.java
package net.lybf.chat.activity;
import android.app.ActionBar;
import android.os.Build;
import android.os.Bundle;
import android.support.v4.widget.DrawerLayout;
import android.view.WindowManager;
import me.imid.swipebacklayout.lib.app.SwipeBackActivity;
import net.lybf.chat.MainApplication;
import net.lybf.chat.R;
import net.lybf.chat.system.settings;
import net.lybf.chat.utils.Logcat;
import static net.lybf.chat.system.Utils.print;
import android.graphics.Color;
public class MPSActivity extends SwipeBackActivity/* AppCompatActivity*/
{
//Created by lybf on 2017/7/23 13:34
public static final String TAG="MPSActivity";
//单例
private static MainApplication application;
//设置
private static settings settings;
//日志记录
private static Logcat logcat;
private static boolean autoDark=false;
@Override
protected void onCreate(Bundle savedInstanceState){
super.onCreate(savedInstanceState);
init();
}
private void init(){
application=(MainApplication)getApplication();
if(application==null){
print(this.getClass(),"Application cast error");
application=MainApplication.getInstance();
}
settings=application.getSettings();
// application.init();
logcat=application.getLogcat();
}
protected void onStop(){
application=null;
settings=null;
logcat=null;
super.onStop();
}
//刷新数据
public void refreshData(){
init();
}
public void fitsSystemWindow(DrawerLayout view,boolean bool){
if(Build.VERSION.SDK_INT>=Build.VERSION_CODES.KITKAT){
if(Build.VERSION.SDK_INT<Build.VERSION_CODES.LOLLIPOP){
//将侧边栏顶部延伸至status bar
view.setFitsSystemWindows(bool);
//将主页面顶部延伸至status bar;
view.setClipToPadding(false);
}
}
}
public void fitsSystemWindow(DrawerLayout view,boolean isTranslucent,boolean bool){
if(Build.VERSION.SDK_INT>=Build.VERSION_CODES.KITKAT){
WindowManager.LayoutParams localLayoutParams = getWindow().getAttributes();
if(isTranslucent)
localLayoutParams.flags=(WindowManager.LayoutParams.FLAG_TRANSLUCENT_STATUS|localLayoutParams.flags);
if(Build.VERSION.SDK_INT<Build.VERSION_CODES.LOLLIPOP){
//将侧边栏顶部延伸至status bar
view.setFitsSystemWindows(bool);
//将主页面顶部延伸至status bar;
view.setClipToPadding(false);
}
}
}
public void fitsSystemWindow(DrawerLayout view,int color,boolean bool){
if(Build.VERSION.SDK_INT>=Build.VERSION_CODES.KITKAT){
setStatusBarColor(color);
if(Build.VERSION.SDK_INT<Build.VERSION_CODES.LOLLIPOP){
//将侧边栏顶部延伸至status bar
view.setFitsSystemWindows(bool);
//将主页面顶部延伸至status bar;
view.setClipToPadding(false);
}
}
}
protected void setStatusBarColor(int color){
if(Build.VERSION.SDK_INT>=Build.VERSION_CODES.KITKAT){
getWindow().setStatusBarColor(color);
}
}
protected void autoDark(boolean bool){
this.autoDark=bool;
if(autoDark){
if(settings.isDark()){
setTheme(R.style.DarkTheme);
}else{
setTheme(R.style.LightTheme);
}
}
}
protected void hideActionBar(boolean bool){
ActionBar bar=getActionBar();
if(bar==null)
return;
if(bool)
bar.hide();
else
bar.show();
}
protected MainApplication getMainApplication(){
if(application==null){
init();
}
return this.application;
}
protected Logcat getLogcat(){
if(logcat==null){
init();
}
return this.logcat;
}
protected settings getSettings(){
if(settings==null){
init();
}
return this.settings;
}
}
<file_sep>/app/src/main/java/net/lybf/chat/ui/FlashLightActivity.java
package net.lybf.chat.ui;
import android.content.Context;
import android.graphics.Bitmap;
import android.hardware.Camera;
import android.os.Bundle;
import android.os.Handler;
import android.os.Message;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.ImageButton;
import android.widget.RadioGroup;
import android.widget.Toast;
import net.lybf.chat.R;
import net.lybf.chat.activity.MPSActivity;
import net.lybf.chat.system.Colors;
import net.lybf.chat.utils.BitmapTools;
public class FlashLightActivity extends MPSActivity
{
//Created by lybf on 2017/8/2 21:03
//相机
private static Camera camera=null;
private static boolean isOpen=false;
private ImageButton mswitch;
private static BitmapTools bm;
private static Context ctx;
private RadioGroup radiogroup;
public static int id = 0;
private FlashLightActivity.Flashlight flashlight;
private Camera.Parameters par;
@Override
protected void onCreate(Bundle savedInstanceState){
super.onCreate(savedInstanceState);
super.autoDark(true);
setContentView(R.layout.activity_flashlight);
ctx=this;
bm=new BitmapTools();
initView();
}
private void initView(){
radiogroup=(RadioGroup)findViewById(R.id.flashlight_radioGroup);
radiogroup.setOnCheckedChangeListener(new RadioGroup.OnCheckedChangeListener(){
@Override
public void onCheckedChanged(RadioGroup view,int id){
View v=view.findViewById(id);
if(!v.isPressed()){
return;
}
FlashLightActivity.this.id=id;
}
});
mswitch=(ImageButton)findViewById(R.id.flashlight_switchMode);
closeIcon();
flashlight=new Flashlight();
mswitch.setOnClickListener(new OnClickListener(){
public void onClick(View v){
switch(id){
case R.id.flashlight_mode_common:
flashlight.common();
break;
case R.id.flashlight_mode_sos:
if(!isOpen){
isOpen=true;
openIcon();
flashlight.sos();
}else{
closeIcon();
isOpen=false;
closeFlashLight();
}
break;
default:
// flashlight.common();
break;
}
}
});
init();
}
@Override
protected void onDestroy(){
if(camera!=null){
isOpen=false;
closeFlashLight();
//camera.release();
}
camera=null;
Toast.makeText(this,"已经为你自动关闭手电筒",Toast.LENGTH_SHORT).show();
super.onDestroy();
}
private void init(){
camera=Camera.open();
par=camera.getParameters();
}
private class Flashlight
{
public void common(){
if(!isOpen){
isOpen=true;
openIcon();
openFlashLight();
try{
Thread.sleep(100);
}catch(InterruptedException e){
e.printStackTrace();
}
}else{
isOpen=false;
closeIcon();
closeFlashLight();
try{
Thread.sleep(100);
}catch(InterruptedException e){
e.printStackTrace();
}
}
}
Handler h=new Handler(){
@Override
public void handleMessage(Message msg){
super.handleMessage(msg);
switch(msg.what){
case 0:
openFlashLight();
break;
case 1:
closeFlashLight();
break;
}
}
};
public void sos(){
new Thread(new Thread(){
public boolean check(){
if(!isOpen)return true;
return false;
}
public void run(){
while(isOpen){
try{
for(int i=0;i<3;i++){
if(!isOpen)return;
h.sendEmptyMessage(0);
if(!isOpen){
h.sendEmptyMessage(1);
return;
}
this.sleep(500);
h.sendEmptyMessage(1);
this.sleep(500);
}
this.sleep(1500);
for(int i=0;i<3;i++){
h.sendEmptyMessage(0);
if(!isOpen){
h.sendEmptyMessage(1);
return;
}
this.sleep(1000);
h.sendEmptyMessage(1);
this.sleep(1000);
}
this.sleep(2000);
}catch(Exception e){
e.printStackTrace();
}
}
}
}).start();
}
}
private void openIcon(){
if(getSettings().isDark()){
Bitmap p= bm.load(ctx.getResources(),R.drawable.ic_flashlight);
mswitch.setImageBitmap(bm.setColor(Colors.gray,Colors.white,p));
}else{
mswitch.setImageBitmap(bm.load(ctx.getResources(),R.drawable.ic_flashlight));
}
}
private void closeIcon(){
if(getSettings().isDark()){
Bitmap p=bm.load(ctx.getResources(),R.drawable.ic_flashlight_off);
mswitch.setImageBitmap(bm.setColor(Colors.gray,Colors.white,p));
}else{
mswitch.setImageBitmap(bm.load(ctx.getResources(),R.drawable.ic_flashlight_off));
}
}
private void openFlashLight(){
if(camera==null)
camera=camera.open();
if(par==null)
par=camera.getParameters();
par.setFlashMode(par.FLASH_MODE_TORCH);
camera.setParameters(par);
camera.startPreview();
}
private void closeFlashLight(){
if(camera==null)
camera=camera.open();
if(par==null)
par=camera.getParameters();
par.setFlashMode(par.FLASH_MODE_OFF);
camera.stopPreview();
camera.release();
camera=null;
}
}
<file_sep>/app/src/main/java/net/lybf/chat/system/update.java
package net.lybf.chat.system;
import com.google.gson.Gson;
import com.google.gson.GsonBuilder;
import com.google.gson.JsonElement;
import com.google.gson.JsonParser;
import org.json.JSONException;
import org.json.JSONObject;
public class update
{
public static final Number TYPE_HTML=0;
public static final Number TYPE_TEXT=1;
private String objectid;
private Number showType;
private String content;
private String apkurl;
private Number versionCode;
private String versionName;
private Number level;
private String createdAt;
private String updatedAt;
private String title;
public update setObjecId(String Id){
this.objectid=Id;
return this;
}
public String getObjectId(){
return this.objectid;
}
public update setTitle(String title){
this.title=title;
return this;
}
public String getTitle(){
return this.title;
}
public update setShowType(Number i){
this.showType=i;
return this;
}
public Number getShowType(){
return this.showType;
}
public update setContent(String content){
this.content=content;
return this;
}
public String getContent(){
return this.content;
}
public update setApkUrl(String url){
this.apkurl=url;
return this;
}
public String getApkUrl(){
return this.apkurl;
}
public update setVersionCode(Number num){
this.versionCode=num;
return this;
}
public Number getVersionCode(){
return this.versionCode;
}
public update setVersionName(String name){
this.versionName=name;
return this;
}
public String getVersionName(){
return this.versionName;
}
public update setLevel(Number num){
this.level=num;
return this;
}
public Number getLevel(){
return this.level;
}
public update setCreatedAt(String created){
this.createdAt=created;
return this;
}
public String getCreatedAt(){
return this.createdAt;
}
public update setUpdatedAt(String update){
this.updatedAt=update;
return this;
}
public String getUpdatedAt(){
return this.updatedAt;
}
public JSONObject toJson(){
String str=new Gson().toJson(this);
JSONObject json = null;
try{
json=new JSONObject(str);
}catch(JSONException e){
}
return json;
}
public String toString(){
Gson gson3 = new GsonBuilder().setPrettyPrinting().create();
JsonParser jp = new JsonParser();
JsonElement je = jp.parse(""+toJson());
String format= gson3.toJson(je);
return format;
}
}
<file_sep>/app/src/main/java/net/lybf/chat/system/ActivityResultCode.java
package net.lybf.chat.system;
public class ActivityResultCode
{
public static final int USER_REFRESH=9999;
public static final int USER_LOGIN=10000;
public static final int USER_LOGOUT=10001;
public static final int SETTINGS_CHANGE=10002;
}
<file_sep>/app/src/main/java/net/lybf/chat/utils/SignaTure.java
package net.lybf.chat.utils;
import android.content.Context;
import android.content.pm.PackageInfo;
import android.content.pm.PackageManager;
import android.content.pm.Signature;
import android.text.TextUtils;
import net.lybf.chat.MainApplication;
import net.lybf.chat.system.Utils;
public class SignaTure
{
private StringBuilder builder;
private Context ctx;
private String pkgname;
private PackageManager manager;
private PackageInfo packageInfo;
private String signature;
private Signature[] signatures;
private MainApplication mApplication;
public SignaTure(){
mApplication=new MainApplication();
ctx=mApplication.getContext();
}
public SignaTure setPackageName(String packagename){
pkgname=packagename;
return this;
}
public String getSignature(){
builder=new StringBuilder();
boolean isEmpty = TextUtils.isEmpty(pkgname);
manager=ctx.getPackageManager();
if(isEmpty){
return "应用程序的包名不能为空!";
}else{
try{
packageInfo=manager.getPackageInfo(pkgname,PackageManager.GET_SIGNATURES);
signatures=packageInfo.signatures;
for(Signature signature : signatures){
builder.append(signature);
}
signature=builder.toString();
}catch(Exception e){
StackTraceInfo stm=new StackTraceInfo();
stm.init(e);
Utils.print(this.getClass(),stm.getMessage().toString());
}
}
return builder.toString();
}
}
<file_sep>/app/src/main/java/net/lybf/chat/utils/TuLingRobot.java
package net.lybf.chat.utils;
import android.content.Context;
import android.os.Handler;
import android.os.Message;
import cn.bmob.v3.BmobUser;
import java.io.BufferedReader;
import java.io.IOException;
import java.io.InputStreamReader;
import java.io.OutputStreamWriter;
import java.net.HttpURLConnection;
import java.net.URL;
import java.util.ArrayList;
import java.util.Random;
import net.lybf.chat.MainApplication;
import net.lybf.chat.bmob.MyUser;
import net.lybf.chat.maps.Robot;
import net.lybf.chat.maps.RobotList;
import net.lybf.chat.system.Utils;
import org.json.JSONArray;
import org.json.JSONException;
import org.json.JSONObject;
public class TuLingRobot
{
//CreatedAt 2017/4/24 16:00
private static MyUser user;
private static final String key="b6b3d000e00d4580a0b0eaf3a1236bd9";
private static MainApplication app;
private static Context ctx;
private static String id;
private static TuLingRobot.TuLingRobotListener listener;
private static final int success=100;
private Network net;
public TuLingRobot(){
init();
user=BmobUser.getCurrentUser(MyUser.class);
}
public TuLingRobot(MyUser user){
init();
this.user=user;
}
private void init(){
this.app=new MainApplication();
this.ctx=app.getContext();
this.net=new Network(ctx);
}
public interface TuLingRobotListener
{
void done(Robot robot);
}
public void setUserID(String id){
if(id!=null){
this.id=id;
}else{
Random r= new Random();
String str="";
for(int i=0;i<18;i++){
str+=r.nextInt(999);
}
if(str.length()>15){
str=str.substring(0,15);
}
this.id=str;
Utils.print(this.getClass(),str);
}
}
public void send(String message,TuLingRobotListener listener){
this.listener=listener;
String url="http://www.tuling123.com/openapi/api";
JSONObject obj=new JSONObject();
try{
obj.put("key",key);
obj.put("info",message);
obj.put("userid",id);
}catch(JSONException e){
e.printStackTrace();
}
sendPost(obj.toString(),url);
// return sendPost(obj.toString(),url);
}
private Handler handler=new Handler(){
@Override
public void handleMessage(Message msg){
super.handleMessage(msg);
switch(msg.what){
case success:
if(listener!=null){
listener.done((Robot)msg.obj);
}
break;
}
}
};
//发送Post
public void sendPost(final String param,final String url){
new Thread(new Thread(){
public void run(){
OutputStreamWriter out = null;
BufferedReader in = null;
StringBuilder result = new StringBuilder();
try{
URL realUrl = new URL(url);
HttpURLConnection conn = (HttpURLConnection) realUrl
.openConnection();
conn.setDoOutput(true);
conn.setDoInput(true);
conn.setUseCaches(false);
conn.setRequestMethod("POST");
conn.setConnectTimeout(50000);
conn.setReadTimeout(50000);
conn.setRequestProperty("Content-Type","application/json");
conn.setRequestProperty("Accept","application/json");
conn.setRequestProperty("Authorization","token");
conn.setRequestProperty("tag","htc_new");
conn.connect();
out=new OutputStreamWriter(conn.getOutputStream(),"UTF-8");
out.write(param);
out.flush();
out.close();
//
in=new BufferedReader(new InputStreamReader(
conn.getInputStream(),"UTF-8"));
String line = "";
while((line=in.readLine())!=null){
result.append(line);
}
}catch(Exception e){
e.printStackTrace();
}finally{
try{
if(out!=null){
out.close();
}
if(in!=null){
in.close();
}
}catch(IOException ex){
ex.printStackTrace();
}
}
JSONObject json = null;
Robot robot = null;
try{
if(!result.toString().equals("")){
json=new JSONObject(result.toString());
json.put("name","聊天机器人");
}else{
json=new JSONObject("{\"name\":\"系统\",\"code\":404,\"text\":\"未知错误\"}");
if(!net.isConnected()){
json.put("text","网络似乎出了点问题～请检查你的网络！");
}
}
robot=new Robot();
robot.setFlag(robot.FLAG_ROBOT);
robot.setName(""+json.opt("name"));
robot.setCode(json.opt("code"))
.setText(""+json.opt("text"))
.setUrl(""+json.opt("url"));
try{
JSONArray array=(JSONArray) json.opt("list");
if(array!=null){
ArrayList<RobotList> l=new ArrayList<RobotList>();
for(int i=0;i<array.length();i++){
JSONObject obj=(JSONObject) array.opt(i);
if(obj!=null){
RobotList list=new RobotList();
//new Gson().fromJson(obj.toString(),RobotList.class);
list.setArticle(""+obj.opt("article"))
.setDetailUrl(""+obj.opt("detailurl"))
.setFlag(0)
.setIcon(""+obj.opt("icon"))
.setInfo(""+obj.opt("info"))
.setName(""+obj.opt("name"))
.setSource(""+obj.opt("source"));
l.add(list);
}//end if
}//end for
if(l.size()>0)
robot.setList(l);
}//end if
}catch(Exception e){
e.printStackTrace();
}//end try
}catch(JSONException e){
e.printStackTrace();
}
Message msg=handler.obtainMessage();
msg.what=success;
msg.obj=robot;
handler.sendMessage(msg);
/* if(listener!=null){
listener.done(robot);
}*/
}
}
).start();
//return robot;
}
}
<file_sep>/app/src/main/java/net/lybf/chat/utils/chat.java
package net.lybf.chat.utils;
import android.content.Context;
public class chat
{
static{
System.loadLibrary("chat");
}
public native String getKey();
public native boolean BmobInitialize(Context context);
}
<file_sep>/app/src/main/java/net/lybf/chat/bmob/MyUser.java
package net.lybf.chat.bmob;
import cn.bmob.v3.BmobInstallation;
import cn.bmob.v3.BmobUser;
import cn.bmob.v3.datatype.BmobFile;
//用户类
public class MyUser extends BmobUser
{
//头像
private BmobFile icon;
//描述，个性标签
private String describe;
//黑名单？
private boolean BlackName;
//vip级别
private Integer vip;
//管理员
private boolean op;
//超级管理员
private boolean superop;
//设备 绑定设备
private BmobInstallation device;
public MyUser(){
}
public MyUser(BmobFile icon,String objectId,String name,
String describe,boolean BlackName,
Integer vip,boolean op,boolean superop,
BmobInstallation device,String updatedAt,String createdAt){
setObjectId(objectId);
setUsername(name);
setUpdatedAt(updatedAt);
setCreatedAt(createdAt);
this.icon=icon;
this.describe=describe;
this.BlackName=BlackName;
this.vip=vip;
this.op=op;
this.superop=superop;
this.device=device;
}
//获取vip级别
public Integer getVipLevel(){
return this.vip;
}
//是否是管理员
public boolean isOP(){
return this.op;
}
//是否是超级管理员
public boolean isSuperOp(){
return this.superop;
}
//获取头像
public BmobFile getIcon(){
return this.icon;
}
//修改头像
public MyUser setIcon(BmobFile f){
this.icon=f;
return this;
}
//获取描述
public String getdescribe(){
return this.describe;
}
//是否是黑名单
public boolean isBlackName(){
return this.BlackName;
}
public MyUser setDevice(BmobInstallation Installation){
this.device=Installation;
return this;
}
public BmobInstallation getDevice(){
return this.device;
}
}
<file_sep>/app/src/main/java/net/lybf/chat/utils/Logcat.java
package net.lybf.chat.utils;
import java.io.File;
import java.io.FileOutputStream;
import java.io.IOException;
import java.util.Date;
import net.lybf.chat.system.Paths;
import static net.lybf.chat.system.Utils.getClassName;
import static net.lybf.chat.system.Utils.print;
import java.io.FileNotFoundException;
public class Logcat
{
//单例
private static Logcat INSTANCE;
//路径
private static String path;
//日志文件
private static File file;
private static FileOutputStream out;
private Logcat(){
// init();
}
public static Logcat getInstance(){
if(INSTANCE==null)
INSTANCE=new Logcat();
return INSTANCE;
}
public synchronized void init(){
Date date=new Date(System.currentTimeMillis());
String name=DateTools.format(date,"yyyy-MM-dd");
path=Paths.LOGCHAT_CRASH+"/"+name+".logcat";
File d=new File(path);
if(!d.getParentFile().exists())
d.getParentFile().mkdirs();
file=d;
try{
d.createNewFile();
}
catch(IOException e){
e.printStackTrace();
}
try{
out=new FileOutputStream(file,true);
// out.write("############Start##########\n".getBytes());
}
catch(Exception e){
e.printStackTrace();
}
}
public synchronized void println(Object thisz,Object object){
String str="@date="+getTime()+"|||||@class="+getClassName(thisz)+"|||||@info="+object.toString();
write(this.out,str);
}
public synchronized void println(Object object){
String str="@date="+getTime()+"|||||@info="+object.toString();
print(str);
write(this.out,str);
}
public synchronized void println(File file,Object thiz,Object info){
String str="@date="+getTime()+"|||||@info="+getClassName(thiz)+info.toString();
try{
write(new FileOutputStream(file),str);
}
catch(FileNotFoundException e){
e.printStackTrace();
}
}
private synchronized void write(FileOutputStream out,String string){
try{
if(out!=null){
out.write((string+"\n").getBytes());
out.close();
}else return;
}
catch(Exception e){
e.printStackTrace();
}
}
public static String getTime(){
String time=DateTools.format(System.currentTimeMillis(),"yyy/MM/dd HH:mm:ss:SSS");
return time;
}
public synchronized void close() throws IOException{
out.write("###########End##########\n\n\n".getBytes());
out.close();
out=null;
System.gc();
}
public synchronized void newWrite() throws Exception{
out=new FileOutputStream(file,true);
out.write("############Start##########\n".getBytes());
}
}
<file_sep>/app/src/main/java/net/lybf/chat/utils/DateTools.java
package net.lybf.chat.utils;
import java.text.SimpleDateFormat;
import java.util.Date;
import java.util.TimeZone;
import net.lybf.chat.system.Utils;
public class DateTools
{
public static final String TIME_YEAR="yyyy";
public static final String TIME_MOTHER="MM";
public static final String TIME_DAY="dd";
public static final String TIME_HOURS="HH";
public static final String TIME_MINUTES="mm";
public static final String TIME_SECONDS="ss";
public static final String TIME_MILLISECOND="SSS";
public static String format(Date date,String pattern){
return new SimpleDateFormat(pattern).format(date);
}
public static String format(long date,String pattern){
Date dat=new Date(date);
return new SimpleDateFormat(pattern).format(dat);
}
public static Date String2Date(String date,String type){
SimpleDateFormat f=new SimpleDateFormat();
f.applyPattern(type);
Date dat = null;
try{
dat=f.parse(date);
}catch(Exception e){
Utils.print("DateTools.class",e);
}
return dat;
}
public static Date getDate(String date,String pattern){
SimpleDateFormat f=new SimpleDateFormat();
f.applyPattern(pattern);
Date dat = null;
try{
dat=f.parse(date);
}catch(Exception e){
Utils.print("net.lybf.chat.utils.DateTools",e);
}
return dat;
}
public static long getLong(Date date){
if(date!=null)
return date.getTime();
return 0;
}
public static long getLong(String date,String pattern){
Date dt=getDate(date,pattern);
return dt.getTime();
}
public static String date(Date startDate){
Date endDate=new Date(System.currentTimeMillis());
if(startDate==null||endDate==null)
return null;
long timeLong = endDate.getTime()-startDate.getTime();
if(timeLong<60*1000)
return timeLong/1000+"秒前";
else if(timeLong<60*60*1000){
timeLong=timeLong/1000/60;
return timeLong+"分钟前";
}else if(timeLong<60*60*24*1000){
timeLong=timeLong/60/60/1000;
return timeLong+"小时前";
}else if(timeLong<60*60*24*1000*7){
timeLong=timeLong/1000/60/60/24;
return timeLong+"天前";
}else if(timeLong<60*60*24*1000*7*4){
timeLong=timeLong/1000/60/60/24/7;
return timeLong+"周前";
}else if(startDate.getYear()==endDate.getYear()){
SimpleDateFormat sdf=new SimpleDateFormat("MM/dd HH:mm");
sdf.setTimeZone(TimeZone.getTimeZone("GMT+08:00"));
return sdf.format(startDate);
}else{
SimpleDateFormat sdf = new SimpleDateFormat("yyyy-MM-dd HH:mm:ss");
sdf.setTimeZone(TimeZone.getTimeZone("GMT+08:00"));
return sdf.format(startDate);
}
}
}
<file_sep>/app/src/main/java/net/lybf/chat/system/Paths.java
package net.lybf.chat.system;
public class Paths
{
public static final String DIR_PATH="/sdcard/lybf/MPSquare";
public static final String DATA_PATH="/sdcard/lybf/MPSquare/.data";
public static final String USER_PATH="/sdcard/lybf/MPSquare/.user";
public static final String SETTINGS_PATH="/sdcard/lybf/MPSquare/.settings/main.json";
public static final String SETTINGS_PKG_PATH="/sdcard/lybf/MPSquare/.settings";
public static final String LOG_ROBOT_CHAT="/sdcard/lybf/MPSquare/.chatLog";
public static final String LOGCHAT_CRASH="/sdcard/lybf/MPSquare/.logcat";
}
<file_sep>/app/src/main/java/net/lybf/chat/ui/AboutActivity.java
package net.lybf.chat.ui;
import android.content.ClipboardManager;
import android.content.Context;
import android.content.DialogInterface;
import android.content.Intent;
import android.content.pm.PackageInfo;
import android.content.pm.PackageManager;
import android.os.Bundle;
import android.support.design.widget.Snackbar;
import android.support.v7.app.AlertDialog;
import android.support.v7.widget.Toolbar;
import android.text.Html;
import android.text.util.Linkify;
import android.view.MenuItem;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
import android.widget.TextView;
import cn.bmob.v3.BmobQuery;
import cn.bmob.v3.exception.BmobException;
import cn.bmob.v3.listener.FindListener;
import java.util.List;
import net.lybf.chat.MainApplication;
import net.lybf.chat.R;
import net.lybf.chat.activity.MPSActivity;
import net.lybf.chat.bmob.ErrorMessage;
import net.lybf.chat.bmob.UpdateLog;
import net.lybf.chat.system.Utils;
import net.lybf.chat.system.settings;
import net.lybf.chat.system.update;
import net.lybf.chat.utils.Network;
public class AboutActivity extends MPSActivity/*AppCompatActivity*/
{
private Context ctx;
private Toolbar bar;
private TextView Name;
private TextView Describe;
private Network net;
private PackageManager pm ;
private PackageInfo pi ;
private Button CheckUpdate;
private Button Updatelog;
private settings set;
private MainApplication app;
@Override
protected void onCreate(Bundle savedInstanceState){
super.onCreate(savedInstanceState);
net=new Network(this);
ctx=this;
app=getMainApplication();
set=getSettings();
if(set.isDark()){
setTheme(R.style.DarkTheme);
}else{
setTheme(R.style.LightTheme);
}
setContentView(R.layout.activity_about);
pm=ctx.getPackageManager();
try{
pi=pm.getPackageInfo(ctx.getPackageName(),0);
}catch(Exception e){
print(e);
}
bar=(Toolbar)findViewById(R.id.about_toolbar);
setSupportActionBar(bar);
getSupportActionBar().setDisplayHomeAsUpEnabled(true);
Name=(TextView)findViewById(R.id.about_name);
Describe=(TextView)findViewById(R.id.about_describe);
CheckUpdate=(Button)findViewById(R.id.about_checkupdate);
CheckUpdate.setOnClickListener(new OnClickListener(){
@Override
public void onClick(View p1){
update();
}
});
Updatelog=(Button)findViewById(R.id.about_updatelog);
Updatelog.setOnClickListener(new OnClickListener(){
@Override
public void onClick(View p1){
startActivity(new Intent(ctx,UpdateLogActivity.class));
}
});
try{
Name.setText(Name.getText().toString()+pi.versionName.toString()+"("+pi.versionCode+")");
}catch(Exception e){
print(e);
}
}
@Override
public boolean onOptionsItemSelected(MenuItem item){
switch(item.getItemId()){
case android.R.id.home:
this.finish();
break;
}
return true;
}
private void update(){
if(net.isConnectedOrConnecting()){
print("\n检测更新中\n");
BmobQuery<UpdateLog> q = new BmobQuery<UpdateLog>();
q.order("-createdAt");
// q.setLimit(50);
q.findObjects(new FindListener<UpdateLog>() {
@Override
public void done(List<UpdateLog> object,BmobException er){
if(er==null){
print("\n检测更新成功\n");
//if(object.size()<
UpdateLog l=object.get(0);
if(l!=null){
update up=new update();
up.setApkUrl(l.getApkFile());
up.setContent(l.getMessage());
up.setCreatedAt(l.getCreatedAt());
up.setLevel(l.getLevel());
up.setShowType(l.getShowType().intValue());
up.setUpdatedAt(l.getUpdatedAt());
up.setVersionCode(l.getVersionCode());
up.setVersionName(l.getVersionName());
up.setTitle(l.getTile());
try{
int i=pi.versionCode;
String ii=pi.versionName;
if(i-up.getVersionCode().intValue()<0){
showAppUpdateMessage(up);
}
}catch(Exception e){
print(e);
}
}
}else{
Snackbar.make(bar,"什么事也没发生",Snackbar.LENGTH_SHORT).show();
print(new ErrorMessage().getMessage(er.getErrorCode()));
}
}
}
);
}else{
}
}
private void showAppUpdateMessage(update u){
final String str=("版本号:"+u.getVersionCode()
+"\n版本名:"+u.getVersionName()
+"\n更新时间:"+u.getUpdatedAt()
+"\n创建时间:"+u.getCreatedAt())+"\n更新内容:\n";
final String content=u.getContent();
final String download="\n\n下载地址:"+u.getApkUrl();
TextView tv=new TextView(ctx);
tv.setAutoLinkMask(Linkify.ALL);
tv.setSaveEnabled(true);
tv.setSelected(true);
if(u.getShowType().intValue()==update.TYPE_HTML.intValue()){
tv.setText(Html.fromHtml(str.replaceAll("\n","<br></br>")+content+download.replaceAll("\n","<br></br>")));
}else{
tv.setText(downloadMessage=str+content+download);
}
new AlertDialog.Builder(ctx)
.setTitle(u.getTitle())
.setView(tv)
.setPositiveButton("下载",null)
.setNegativeButton("复制",new DownloadApp()
)
.setNeutralButton("关闭",null)
.show();
}
private String downloadMessage;
private class DownloadApp implements DialogInterface.OnClickListener
{
@Override
public void onClick(DialogInterface p1,int p2){
ClipboardManager clip=(ClipboardManager)getSystemService(ctx.CLIPBOARD_SERVICE);
clip.setText(downloadMessage);
}
}
private void print(Object p0){
new Utils().print(this.getClass(),p0);
}
}
<file_sep>/app/src/main/java/net/lybf/chat/services/MusicListener.java
package net.lybf.chat.services;
import android.media.MediaPlayer;
/*
@author:lybf
@date:2017-10-14 01:13
*/
public interface MusicListener
{
public void onSeekComplete(MediaPlayer mediaPlayer);
public void onCompletion(MediaPlayer mediaPlayer);
}
<file_sep>/app/src/main/java/net/lybf/chat/bmob/UpdateLog.java
package net.lybf.chat.bmob;
import cn.bmob.v3.BmobObject;
//应用更新类
public class UpdateLog extends BmobObject
{
//版本号
private Number versionCode;
//版本名
private String versionName;
//安装包地址
private String Apk;
//标题
private String title;
//更新内容
private String describe;
/*更新级别如下
1:普通升级
2:建议升级
3:强制升级*/
private Number level;
private Number showType;
public Number getShowType(){
return this.showType;
}
//获取版本名
public String getVersionName(){
return versionName;
}
//获取更新级别
public Number getLevel(){
return level==-1?0:level;
}
//获取版本号
public Number getVersionCode(){
return versionCode;
}
//获取下载地址
public String getApkFile(){
return Apk;
}
//获取标题
public String getTile(){
return title;
}
//获取更新信息
public String getMessage(){
return describe;
}
}
<file_sep>/app/src/main/java/net/lybf/chat/behavior/BehaviorDefault.java
package net.lybf.chat.behavior;
import android.content.Context;
import android.support.design.widget.CoordinatorLayout;
import android.support.design.widget.FloatingActionButton;
import android.support.v4.view.ViewCompat;
import android.util.AttributeSet;
import android.view.View;
/**
* Created by lybf on 2017/9/10.
*/
public class BehaviorDefault extends FloatingActionButton.Behavior
{
public BehaviorDefault(Context context,AttributeSet attrs){
super();
}
@Override
public boolean onStartNestedScroll(final CoordinatorLayout coordinatorLayout,final FloatingActionButton child,
final View directTargetChild,final View target,final int nestedScrollAxes){
return nestedScrollAxes==ViewCompat.SCROLL_AXIS_VERTICAL
||super.onStartNestedScroll(coordinatorLayout,child,directTargetChild,target,nestedScrollAxes);
}
@Override
public void onNestedScroll(final CoordinatorLayout coordinatorLayout,final FloatingActionButton child,
final View target,final int dxConsumed,final int dyConsumed,
final int dxUnconsumed,final int dyUnconsumed){
super.onNestedScroll(coordinatorLayout,child,target,dxConsumed,dyConsumed,dxUnconsumed,dyUnconsumed);
if(dyConsumed>0&&child.getVisibility()==View.VISIBLE){
child.hide();
}else if(dyConsumed<0&&child.getVisibility()!=View.VISIBLE){
child.show();
}
}
}
<file_sep>/app/src/main/java/net/lybf/chat/adapter/PhotosPickerAdapter.java
package net.lybf.chat.adapter;
import android.content.Context;
import android.support.v7.widget.RecyclerView;
import android.view.LayoutInflater;
import android.view.View;
import android.view.ViewGroup;
import android.widget.ImageView;
import com.squareup.picasso.LruCache;
import java.io.File;
import java.util.ArrayList;
import java.util.List;
import net.lybf.chat.R;
public class PhotosPickerAdapter extends RecyclerView.Adapter<PhotosPickerAdapter.ViewHolder>
{
private Context ctx;
//缓存
private LruCache cache;
//图片
private List<File> list;
public PhotosPickerAdapter(Context ctx){
this. ctx=ctx;
this.list=new ArrayList<File>();
//cache=new LinkedHashMap<String, Bitmap>();
}
public PhotosPickerAdapter(Context ctx,List<File> photos){
this.ctx=ctx;
this.list=photos;
}
public void addItem(int position,File file){
list.add(position,file);
notifyItemInserted(position);
}
public void removeItem(int position){
list.remove(position);
notifyItemRemoved(position);
}
public void clear(){
list.clear();
}
public File getFile(int position){
return list.get(position);
}
public List<File> getList(){
return this.list;
}
@Override
public ViewHolder onCreateViewHolder(ViewGroup viewGroup,int viewType){
View view = LayoutInflater.from(ctx).inflate(R.layout.item_main_post,viewGroup,false);
ViewHolder vh = new ViewHolder(view);
return vh;
}
@Override
public void onBindViewHolder(ViewHolder viewHolder,int p2){
}
@Override
public int getItemCount(){
return 0;
}
public class ViewHolder extends RecyclerView.ViewHolder
{
public ImageView image;
public ViewHolder(View view){
super(view);
}
}
}
<file_sep>/app/src/main/java/net/lybf/chat/adapter/MainPagerAdaptet.java
package net.lybf.chat.adapter;
import android.support.v4.view.PagerAdapter;
import android.view.View;
import android.view.ViewGroup;
import java.util.List;
public class MainPagerAdaptet extends PagerAdapter
{
private String[] mTitles;
private List<View> views;
public MainPagerAdaptet(String[] mTitles,List<View> views){
this.mTitles=mTitles;
this.views=views;
}
@Override
public int getCount(){
return views.size();
}
@Override
public CharSequence getPageTitle(int position){
return mTitles[position];
}
public View getItem(int position){
return views.get(position);
}
@Override
public boolean isViewFromObject(View p1,Object p2){
return p1==p2;
}
public void destroyItem(ViewGroup view, int position, Object object) {
view.removeView(views.get(position));
}
@Override
public Object instantiateItem(ViewGroup view, int position) {
view.addView(views.get(position));
return views.get(position);
}
}
| 4601a2a6d5785107980e9ebb548ba34007c78d71 | [
"Java",
"Gradle"
] | 29 | Java | lybf/MPSquare | ec3281341b0274315c2f81fdc8187d60117513cb | 7eeffa09d3ccbcf1db1f2ae6ca9d78fe6d23ac37 |
refs/heads/master | <repo_name>Marie-Donnie/ThingsMover<file_sep>/ThingsMover/ThingsMover.lua
-------------------------------------------------------------------------------
-- Initialize Variables
-------------------------------------------------------------------------------
local utils = Epsilon.utils
local messages = utils.messages
local server = utils.server
local tabs = utils.tabs
local main = Epsilon.main
local OPmoveLength, OPmoveWidth, OPmoveHeight, OPmoveModifier, MessageCount, ObjectClarifier, SpawnClarifier, ScaleClarifier, RotateClarifier = 0, 0, 0, 1, 0, false, false, false, false
BINDING_HEADER_OBJECTMANIP, SLASH_SHOWCLOSE1, SLASH_SHOWCLOSE2 = "Things Mover", "/thingsm", "/tm"
function loadMasterTable()
if not OPMasterTable then OPMasterTable = {} end
if not OPMasterTable.Options then OPMasterTable.Options = {} end
if not OPMasterTable.Options["debug"] then OPMasterTable.Options["debug"] = false end
if not OPMasterTable.Options["SliderStep"] then OPMasterTable.Options["SliderStep"] = 0.01 end
if not OPMasterTable.Options["locked"] then OPMasterTable.Options["locked"] = false end
if not OPMasterTable.ParamPresetKeys then OPMasterTable.ParamPresetKeys = {"Building Tile","Fine Positioning"} end
if not OPMasterTable.ParamPresetContent then OPMasterTable.ParamPresetContent = {
["Building Tile"] = {
["ObjectID"] = false,
["Length"] = 4,
["Width"] = 4,
["Height"] = 0.25,
["Scale"] = 1,
},
["Fine Positioning"] = {
["ObjectID"] = false,
["Length"] = 0.01,
["Width"] = 0.01,
["Height"] = 0.01,
["Scale"] = 1,
},
}
end
if not OPMasterTable.RotPresetKeys then OPMasterTable.RotPresetKeys = {"Reset (0,0,0)"} end
if not OPMasterTable.RotPresetContent then
OPMasterTable.RotPresetContent = {
["Reset (0,0,0)"] = {
["RotX"] = 0,
["RotY"] = 0,
["RotZ"] = 0,
},
}
end
end
loadMasterTable()
OPFramesAreLoaded = false
FrameLoadingPoints = 0
OPSaveType = nil
ObjectSelectLineCount = 3
function ThingToMove()
if ObjectToggle:GetChecked() then
return "go"
end
if ObjectGroupToggle:GetChecked() then
return "go group"
end
if NPCToggle:GetChecked() then
return "npc"
end
end
function ClientShowRotate(guid,roll,pitch,yaw)
C_Epsilon.RotateObject(guid,roll,pitch,yaw)
end
function OPInitializeLoading()
FrameLoadingPoints = FrameLoadingPoints+1
if FrameLoadingPoints >= 3 then
OPFramesAreLoaded = true
FrameLoadingPoints = 0
if OPMasterTable.Options["debug"] then
dprint("Frames Loaded: Rotation Enabled.")
end
end
end
local OPloginhandle = CreateFrame("frame","OPloginhandle");
OPloginhandle:RegisterEvent("PLAYER_LOGIN");
OPloginhandle:SetScript("OnEvent", function()
OPMiniMapLoadIt()
loadMasterTable()
end);
local OPAddonDetect = CreateFrame("frame","OPAddonDetect");
OPAddonDetect:RegisterEvent("ADDON_LOADED");
OPAddonDetect:SetScript("OnEvent", function(self,event,name)
if name == "ThingsMover" then
--Quickly Show / Hide the Frame on Start-Up to initialize everything for key bindings
OPMainFrame:Show()
OPMainFrame:Hide()
end
end);
function OPMiniMapSaveIt()
local point, relativeTo, relativePoint, xOffset, yOffset = ObjectManipulator_MinimapButton:GetPoint()
OPMasterTable.Options["MinimapButtonSavePoint"] = strjoin(" ", point, "Minimap", relativePoint, xOffset, yOffset)
end
function OPMiniMapLoadIt()
if OPMasterTable.Options["MinimapButtonSavePoint"] ~= nil and OPMasterTable.Options["MinimapButtonSavePoint"] ~= "" then
local point, relativeTo, relativePoint, xOffset, yOffset = strsplit(" ", OPMasterTable.Options["MinimapButtonSavePoint"])
ObjectManipulator_MinimapButton:SetPoint(point, "Minimap", relativePoint, xOffset, yOffset)
end
end
-------------------------------------------------------------------------------
-- Simple Chat Functions
-------------------------------------------------------------------------------
local function cmd(text)
SendChatMessage("."..text, "GUILD");
end
local function eprint(text)
local line = strmatch(debugstack(2),":(%d+):")
if line then
print("|cffFFD700 ObjectMover Error @ "..line..": "..text.."|r")
else
print("|cffFFD700 ObjectMover @ ERROR: "..text.."|r")
print(debugstack(2))
end
end
local function dprint(text)
local line = strmatch(debugstack(2),":(%d+):")
if line then
print("|cffFFD700 ObjectMover DEBUG "..line..": "..text.."|r")
else
print("|cffFFD700 ObjectMover DEBUG: "..text.."|r")
print(debugstack(2))
end
end
-------------------------------------------------------------------------------
-- Main Functions
-------------------------------------------------------------------------------
--Check to make sure entry is valid
function CheckIfValid(Box, IsNotObjectID, Function)
if IsNotObjectID then
if Box:GetText() == Box:GetText():match("%d+") or Box:GetText() == Box:GetText():match("%d+%.%d+") or Box:GetText() == Box:GetText():match("%.%d+") then
if Function then Function() else return true end
--If we don't want to find an object ID, and the box's text isn't illegal, e.g. ".1d-2.*+", and if we want to run a function, then run the function, else if we don't want to run a function, just tell them that the box's text is legal
end
elseif not IsNotObjectID and Box:GetText() == Box:GetText():match("%d+") then
if Function then Function() else return true end
--If we want to find an object ID, and the box's text is an object ID, and if we want to run a function, then run the function, else if we don't want to run a function, just tell them that the box's text is legal
end
end
--Get Object ID Function
function OPGetObject()
OPObjectIDBox:SetText(tonumber(lastSelectedObjectID))
if OPMasterTable.Options["debug"] then dprint("Obejct ID Box updated to: "..tonumber(lastSelectedObjectID)) end;
end
--Update Internal Dimensions for movement when used, factoring in scale, double and halve options
function updateDimensions(val)
if OPHalveToggle:GetChecked() == true then OPmoveModifier = 0.5
elseif OPBifoldToggle:GetChecked() == true then OPmoveModifier = 2
else OPmoveModifier = 1 end
if ScaleObject:GetChecked() == true and ScaleObject:IsEnabled() then
if val == "length" then if tonumber(OPLengthBox:GetText()) ~= nil then OPmoveLength = (tonumber(OPLengthBox:GetText())*tonumber(OPScaleBox:GetText())*OPmoveModifier) end end
if val == "width" then if tonumber(OPWidthBox:GetText()) ~= nil then OPmoveWidth = (tonumber(OPWidthBox:GetText())*tonumber(OPScaleBox:GetText())*OPmoveModifier) end end
if val == "height" then if tonumber(OPHeightBox:GetText()) ~= nil then OPmoveHeight = (tonumber(OPHeightBox:GetText())*tonumber(OPScaleBox:GetText())*OPmoveModifier) end end
else
if val == "length" then if tonumber(OPLengthBox:GetText()) ~= nil then OPmoveLength = tonumber(OPLengthBox:GetText())*OPmoveModifier end end
if val == "width" then if tonumber(OPWidthBox:GetText()) ~= nil then OPmoveWidth = tonumber(OPWidthBox:GetText())*OPmoveModifier end end
if val == "height" then if tonumber(OPHeightBox:GetText()) ~= nil then OPmoveHeight = tonumber(OPHeightBox:GetText())*OPmoveModifier end end
end
end
function OPForward()
updateDimensions("length")
if OPmoveLength and OPmoveLength ~= "" and OPmoveLength ~= 0 and OPmoveLength ~= nil then
if OPMoveObjectInstead:GetChecked() then
if RelativeToPlayer:GetChecked() then
--OPMoveRelative("forward")
cmd(ThingToMove().." relative forward "..OPmoveLength)
else
cmd(ThingToMove().." move for "..OPmoveLength)
end
else
cmd("gps for "..OPmoveLength)
end
if SpawnonMove:GetChecked() == true then
OPSpawn()
end
if OPMasterTable.Options["debug"] then
dprint("Moving "..OPmoveLength.." units forward.")
end
else
print("ObjectMover | Invalid Move Length, please check your Object Parameters.")
end
end
function OPBackward()
updateDimensions("length")
if OPmoveLength and OPmoveLength ~= "" and OPmoveLength ~= 0 and OPmoveLength ~= nil then
if OPMoveObjectInstead:GetChecked() == true then
if RelativeToPlayer:GetChecked() then
--OPMoveRelative("back")
cmd(ThingToMove().." relative back "..OPmoveLength)
else
cmd(ThingToMove().." move back "..OPmoveLength)
end
else
cmd("gps back "..OPmoveLength)
end
if SpawnonMove:GetChecked() == true then
OPSpawn()
end
if OPMasterTable.Options["debug"] then
dprint("Moving "..OPmoveLength.." units backwards.")
end
else
print("ObjectMover | Invalid Move Length, please check your Object Parameters.")
end
end
function OPLeft()
updateDimensions("width")
if OPmoveWidth and OPmoveWidth ~= "" and OPmoveWidth ~= 0 and OPmoveWidth ~= nil then
if OPMoveObjectInstead:GetChecked() == true then
if RelativeToPlayer:GetChecked() then
--OPMoveRelative("left")
cmd(ThingToMove().." relative left "..OPmoveWidth)
else
cmd(ThingToMove().." move left "..OPmoveWidth)
end
else
cmd("gps left "..OPmoveWidth)
end
if SpawnonMove:GetChecked() == true then
OPSpawn()
end
if OPMasterTable.Options["debug"] then
dprint("Moving "..OPmoveWidth.." units left.")
end
else
print("ObjectMover | Invalid Move Width, please check your Object Parameters.")
end
end
function OPRight()
updateDimensions("width")
if OPmoveWidth and OPmoveWidth ~= "" and OPmoveWidth ~= 0 and OPmoveWidth ~= nil then
if OPMoveObjectInstead:GetChecked() == true then
if RelativeToPlayer:GetChecked() then
--OPMoveRelative("right")
cmd(ThingToMove().." relative right "..OPmoveWidth)
else
cmd(ThingToMove().." move right "..OPmoveWidth)
end
else
cmd("gps right "..OPmoveWidth)
end
if SpawnonMove:GetChecked() == true then
OPSpawn()
end
if OPMasterTable.Options["debug"] then
dprint("Moving "..OPmoveWidth.." units right.")
end
else
print("ObjectMover | Invalid Move Width, please check your Object Parameters.")
end
end
function OPUp()
updateDimensions("height")
if OPmoveHeight and OPmoveHeight ~= "" and OPmoveHeight ~= 0 and OPmoveHeight ~= nil then
if OPMoveObjectInstead:GetChecked() == true then
cmd(ThingToMove().." move up "..OPmoveHeight)
else
cmd("gps up "..OPmoveHeight)
end
if SpawnonMove:GetChecked() == true then
OPSpawn()
end
if OPMasterTable.Options["debug"] then
dprint("Moving "..OPmoveHeight.." units up.")
end
else
print("ObjectMover | Invalid Move Height, please check your Object Parameters.")
end
end
function OPDown()
updateDimensions("height")
if OPmoveHeight and OPmoveHeight ~= "" and OPmoveHeight ~= 0 and OPmoveHeight ~= nil then
if OPMoveObjectInstead:GetChecked() == true then
cmd(ThingToMove().." move down "..OPmoveHeight)
else
cmd("gps down "..OPmoveHeight)
end
if SpawnonMove:GetChecked() == true then
OPSpawn()
end
if OPMasterTable.Options["debug"] then
dprint("Moving "..OPmoveHeight.." units down.")
end
else
cprint("Invalid Move Height, please check your Object Parameters.")
end
end
function OPSpawn()
if CheckIfValid(OPObjectIDBox) then
SpawnClarifier = true
--Check if we have an object ID in the object ID box, if we do, spawn it
SendChatMessage(".go spawn "..OPObjectIDBox:GetText())
end
if ScaleObject:GetChecked() == true and ScaleObject:IsEnabled() then
--Do we want to scale it?
ScaleClarifier = true
C_Timer.After(0.5, function() SendChatMessage(".go scale "..OPScaleBox:GetText()) end) -- Delay the scale because scaling immediately after spawn doesn't save on server restart
end
end
function OPTeletoObject()
SendChatMessage(".go go")
end
function EnableBoxes(Box1, Box2)
--This is just to cut down on the xml size when enabling and disabling the Halve and Bifold checkboxes via binding - make sure we're not both checked
if Box1:GetChecked() then
Box1:SetChecked(false)
else
Box1:SetChecked(true)
end
if Box2:GetChecked() then
Box2:SetChecked(false)
end
end
function OPRotateObject()
--if RotateClarifier == false then
RotateClarifier = true
--end
local RotationX = OPRotationSliderX:GetValue()
local RotationY = OPRotationSliderY:GetValue()
local RotationZ = OPRotationSliderZ:GetValue()
if RotationX < 0 then RotationX = 0; if OPMasterTable.Options["debug"] then print("RotX < 0, Made 0") end; end
if RotationY < 0 then RotationY = 0; if OPMasterTable.Options["debug"] then print("RotY < 0, Made 0") end; end
if RotationZ < 0 then RotationZ = 0; if OPMasterTable.Options["debug"] then print("RotZ < 0, Made 0") end; end
if ObjectToggle:GetChecked() then
cmd("go rot "..RotationX.." "..RotationY.." "..RotationZ)
else
cmd(ThingToMove().." turn "..RotationZ)
end
end
function roundToNthDecimal(num, n)
local mult = 10^(n or 0)
return math.floor(num * mult+0.5) / mult
end
-------------------------------------------------------------------------------
-- Save / Load Pre-set System
-------------------------------------------------------------------------------
function OPShowParamSaveMenu()
OPMainSaveFrameTitleText:SetText("Save Parameters Pre-set Name:")
OPMainSaveFrame:Show()
OPSaveType = "param"
end
function OPShowRotSaveMenu()
OPMainSaveFrameTitleText:SetText("Save Rotation Pre-set Name:")
OPMainSaveFrame:Show()
OPSaveType = "rot"
end
function OPSaveMenuActualSave()
local opsavename = OPMainSaveFrameEditBox:GetText()
if opsavename == "" or opsavename == " " or not opsavename:find("%S") then
opsavename = nil
end
if OPSaveType == "param" and opsavename then
--Do Saving for Param Here
OPSaveMenuParamSave(opsavename)
elseif OPSaveType == "rot" and opsavename then
--Do Saving for Rotation Here
OPSaveMenuRotSave(opsavename)
elseif not opsavename then
message("Please enter a valid name!\n\rNames must contain at least one non-space character.")
else
print("ObjectMover: There was an error saving your pre-set. Please use '/reload' and try again. If this persists, please report it as a bug.")
end
end
--Para Saving
function OPSaveMenuParamSave(name)
if OPMasterTable.ParamPresetKeys then
for k,v in ipairs(OPMasterTable.ParamPresetKeys) do
if v == name then
if not confirmPSaveOverwrite then
message("The name specified conflicts with an already saved Parameter Pre-set name. Hit save again to confirm that you wish to overwrite the previous save.")
confirmPSaveOverwrite = true
confirmPSaveOverwriteName = name
return
elseif confirmPSaveOverwrite then
if name == confirmPSaveOverwriteName then
confirmPSaveOverwrite = false
OPSaveMenuParamSaveForReal(name,false)
else
message("The name specified conflicts with an already saved Parameter Pre-set name. Hit save again to confirm that you wish to overwrite the previous save.")
confirmPSaveOverwrite = true
confirmPSaveOverwriteName = name
end
return
else
print("Error: You tried to save with the same name as another Parameter Pre-set save, and an error occurred internally. Please remember how you did this and report it as a bug. Thanks you.")
return
end
return
end
end
OPSaveMenuParamSaveForReal(name,true)
end
end
function OPSaveMenuParamSaveForReal(name,newKey)
if newKey then
table.insert(OPMasterTable.ParamPresetKeys, name)
newKey = false
end
OPMasterTable.ParamPresetContent[name] = {}
OPMasterTable.ParamPresetContent[name].ObjectID = OPObjectIDBox:GetText()
OPMasterTable.ParamPresetContent[name].Length = OPLengthBox:GetText()
OPMasterTable.ParamPresetContent[name].Width = OPWidthBox:GetText()
OPMasterTable.ParamPresetContent[name].Height = OPHeightBox:GetText()
OPMasterTable.ParamPresetContent[name].Scale = OPScaleBox:GetText()
print("ObjectMover: Saved new Parameter Pre-set with name: "..name)
OPMainSaveFrame:Hide()
end
-- Rot Saving
function OPSaveMenuRotSave(name)
if OPMasterTable.RotPresetKeys then
for k,v in ipairs(OPMasterTable.RotPresetKeys) do -- Scan all our current saved rotation preset and confirm if we're overwriting one
if v == name then -- if already saved name == new save name
if not confirmRSaveOverwrite then -- If this is the first time, we'll do this, otherwise go to the second step
message("The name specified conflicts with an already saved Rotation Pre-set name. Hit save again confirm that you wish to overwrite the previous save.") -- Warn the user about overwriting a current preset
confirmRSaveOverwrite = true -- save that we've already warned them
confirmRSaveOverwriteName = name -- keep the name in memory, so that if they close the menu and then save as a new name, we know to recheck again
return
elseif confirmRSaveOverwrite then -- if we're in the confirmation state
if name == confirmRSaveOverwriteName then -- if the name matches the last warned overwrite name
confirmRSaveOverwrite = false -- reset the check so we're back to normal
OPSaveMenuRotSaveForReal(name,false) -- Save the actual preset yay!
else -- if the name they're trying to save no longer matches the last warned name, we need to re-warn them that this name is also still taken!!
message("The name specified conflicts with an already saved Rotation Pre-set name. Hit save again to confirm that you wish to overwrite the previous save.")
confirmRSaveOverwrite = true -- Set the check to true again to make sure
confirmRSaveOverwriteName = name -- and keep the new name in memory again, just incase they change it again
end
return
else
print("Error: You tried to save with the same name as another Rotation Save, and an error occurred internally. Please remember how you did this and report it as a bug. Thanks you.")
return
end
return
end
end
OPSaveMenuRotSaveForReal(name,true)
end
end
function OPSaveMenuRotSaveForReal(name,newKey)
if newKey then
table.insert(OPMasterTable.RotPresetKeys, name)
newKey = false
end
OPMasterTable.RotPresetContent[name] = {}
OPMasterTable.RotPresetContent[name].RotX = OPRotationSliderX:GetValue()
OPMasterTable.RotPresetContent[name].RotY = OPRotationSliderY:GetValue()
OPMasterTable.RotPresetContent[name].RotZ = OPRotationSliderZ:GetValue()
print("ObjectMover: Saved new Rotation Pre-set with name: "..name)
OPMainSaveFrame:Hide()
end
-- DropDown Load Boxes
function OPCreateLoadDropDownMenus()
--Param Loading
local paramPresetDropSelect = CreateFrame("Frame", "paramPresetDropDownMenu", OPPanel2, "UIDropDownMenuTemplate")
paramPresetDropSelect:SetPoint("LEFT", OPParamSaveButton, "RIGHT", -15, -1)
paramPresetDropSelect:SetScript("OnEnter",function()
GameTooltip:SetOwner(paramPresetDropSelect, "ANCHOR_LEFT")
paramPresetDropSelect.Timer = C_Timer.NewTimer(0.7,function()
GameTooltip:SetText("Select a previously saved parameter pre-set to load.\n\rYou can use '/opdelparam Name' in chat (where Name is the pre-set name, case sensitive) to delete any of these pre-sets including the default ones.", nil, nil, nil, nil, true)
GameTooltip:Show()
end)
end)
paramPresetDropSelect:SetScript("OnLeave",function()
GameTooltip_Hide()
paramPresetDropSelect.Timer:Cancel()
end)
local function ParamPresetOnClick(self)
UIDropDownMenu_SetSelectedID(paramPresetDropSelect, self:GetID())
if self.value ~= "Select a Preset" then
_OPMTPPC = OPMasterTable.ParamPresetContent[self.value]
if _OPMTPPC.ObjectID and tostring(_OPMTPPC.ObjectID) ~= "" and tostring(_OPMTPPC.ObjectID) ~= "0" then
OPObjectIDBox:SetText(OPMasterTable.ParamPresetContent[self.value].ObjectID)
end
if _OPMTPPC.Length and tostring(_OPMTPPC.Length) ~= "" and tostring(_OPMTPPC.Length) ~= "0" then
OPLengthBox:SetText(OPMasterTable.ParamPresetContent[self.value].Length)
end
if _OPMTPPC.Width and tostring(_OPMTPPC.Width) ~= "" and tostring(_OPMTPPC.Width) ~= "0" then
OPWidthBox:SetText(OPMasterTable.ParamPresetContent[self.value].Width)
end
if _OPMTPPC.Height and tostring(_OPMTPPC.Height) ~= "" and tostring(_OPMTPPC.Height) ~= "0" then
OPHeightBox:SetText(OPMasterTable.ParamPresetContent[self.value].Height)
end
if _OPMTPPC.Scale and tostring(_OPMTPPC.Scale) ~= "" and tostring(_OPMTPPC.Scale) ~= "0" then
OPScaleBox:SetText(OPMasterTable.ParamPresetContent[self.value].Scale)
end
if OPMasterTable.Options["debug"] then
dprint("Tried to load Param Pre-set: "..self.value)
end
end
end
local function paramPresetInitialize(self,level)
local info = UIDropDownMenu_CreateInfo()
for k,v in ipairs(OPMasterTable.ParamPresetKeys) do
info = UIDropDownMenu_CreateInfo()
info.text = v
info.value = v
info.func = ParamPresetOnClick
UIDropDownMenu_AddButton(info,level)
end
end
UIDropDownMenu_Initialize(paramPresetDropSelect, paramPresetInitialize)
UIDropDownMenu_SetWidth(paramPresetDropSelect, 65);
UIDropDownMenu_SetButtonWidth(paramPresetDropSelect, 80)
UIDropDownMenu_SetSelectedID(paramPresetDropSelect, 0)
UIDropDownMenu_JustifyText(paramPresetDropSelect, "LEFT")
UIDropDownMenu_SetText(paramPresetDropSelect, "Load")
paramPresetDropDownMenuText:SetFontObject("GameFontWhiteTiny2")
local fontName,fontHeight,fontFlags = paramPresetDropDownMenuText:GetFont()
paramPresetDropDownMenuText:SetFont(fontName, 6)
-- Rot Loading
local rotPresetDropSelect = CreateFrame("Frame", "rotPresetDropDownMenu", OPPanel4, "UIDropDownMenuTemplate")
rotPresetDropSelect:SetPoint("LEFT", OPRotSaveButton, "RIGHT", -15, -1)
rotPresetDropSelect:SetScript("OnEnter",function()
GameTooltip:SetOwner(rotPresetDropSelect, "ANCHOR_LEFT")
rotPresetDropSelect.Timer = C_Timer.NewTimer(0.7,function()
GameTooltip:SetText("Select a previously saved rotation pre-set to load.\n\rYou can use '/opdelrot Name' in chat (where Name is the pre-set name, case sensitive) to delete any of these pre-sets including the default ones.", nil, nil, nil, nil, true)
GameTooltip:Show()
end)
end)
rotPresetDropSelect:SetScript("OnLeave",function()
GameTooltip_Hide()
rotPresetDropSelect.Timer:Cancel()
end)
local function RotPresetOnClick(self)
UIDropDownMenu_SetSelectedID(rotPresetDropSelect, self:GetID())
if self.value ~= "Select a Preset" then
local origx, origy, origz = OPRotationSliderX:GetValue(), OPRotationSliderY:GetValue(), OPRotationSliderZ:GetValue()
_OPMTRPC = OPMasterTable.RotPresetContent[self.value]
if _OPMTRPC.RotX and tostring(_OPMTRPC.RotX) ~= "" and tonumber(_OPMTRPC.RotX) >= 0 then
OPRotationSliderX:SetValue(tonumber(OPMasterTable.RotPresetContent[self.value].RotX))
end
if _OPMTRPC.RotY and tostring(_OPMTRPC.RotY) ~= "" and tonumber(_OPMTRPC.RotY) >= 0 then
OPRotationSliderY:SetValue(tonumber(OPMasterTable.RotPresetContent[self.value].RotY))
end
if _OPMTRPC.RotZ and tostring(_OPMTRPC.RotZ) ~= "" and tonumber(_OPMTRPC.RotZ) >= 0 then
OPRotationSliderZ:SetValue(tonumber(OPMasterTable.RotPresetContent[self.value].RotZ))
end
if OPMasterTable.Options["debug"] then
dprint("Tried to load Rot Pre-set: "..self.value)
dprint(origx.." | "..origy.." | "..origz)
end
if origx == OPRotationSliderX:GetValue() and origy == OPRotationSliderY:GetValue() and origz == OPRotationSliderZ:GetValue() then
OPRotateObject();
OPIMFUCKINGROTATINGDONTSPAMME = true
OPClearRotateChatFilter()
if OPMasterTable.Options["debug"] then
dprint("Loaded the same as whatever it is currently, so we're gonna apply the rotation anyways!")
end
end
end
end
local function rotPresetInitialize(self,level)
local info = UIDropDownMenu_CreateInfo()
for k,v in ipairs(OPMasterTable.RotPresetKeys) do
info = UIDropDownMenu_CreateInfo()
info.text = v
info.value = v
info.func = RotPresetOnClick
UIDropDownMenu_AddButton(info,level)
end
end
UIDropDownMenu_Initialize(rotPresetDropSelect, rotPresetInitialize)
UIDropDownMenu_SetWidth(rotPresetDropSelect, 65)
--UIDropDownMenu_SetHeight(rotPresetDropSelect, 24)
UIDropDownMenu_SetButtonWidth(rotPresetDropSelect, 80)
UIDropDownMenu_SetSelectedID(rotPresetDropSelect, 0)
UIDropDownMenu_JustifyText(rotPresetDropSelect, "LEFT")
UIDropDownMenu_SetText(rotPresetDropSelect, "Load")
rotPresetDropDownMenuText:SetFontObject("GameFontWhiteTiny2")
local fontName,fontHeight,fontFlags = rotPresetDropDownMenuText:GetFont()
rotPresetDropDownMenuText:SetFont(fontName, 6)
--rotPresetDropSelect:SetHeight(24)
end
-------------------------------------------------------------------------------
-- Message Filters
-------------------------------------------------------------------------------
function OPClearRotateChatFilter()
if RotateClarifier then
OPIMFUCKINGROTATINGDONTSPAMME = false
C_Timer.After(0.25, OPClearRotateChatFilterDontSpamIfStillRotating);
end
end
function OPClearRotateChatFilterDontSpamIfStillRotating()
if OPIMFUCKINGROTATINGDONTSPAMME ~= true then
RotateClarifier = false
end
end
function RunChecks(Message)
local clearmsg = gsub(Message,"|cff%x%x%x%x%x%x","");
-- GObject Rotate Message Filter
if RotateClarifier and Message:gsub("|.........",""):find("rotated") then
if OPMasterTable.Options["debug"] then
dprint("RotateClarifier Caught Message")
end
return true
-- GObject Spawn Message Filter
elseif SpawnClarifier and clearmsg:find("[Spawned gameobject|Map:|Syntax|was not found|You do not have]") then
if clearmsg:find("Spawned gameobject") then
if OPMasterTable.Options["debug"] then
dprint("SpawnClarifier Caught SPAWNED Message")
end
return true
elseif clearmsg:find("Map:") then
SpawnClarifier = false
if OPMasterTable.Options["debug"] then
dprint("SpawnClarifier Caught MAP Message")
end
return true
elseif clearmsg:find("[Syntax|was not found|You do not have]") then
SpawnClarifier = false
if OPMasterTable.Options["debug"] then
dprint("SpawnClarifier Caught Syntax or Failure, Disabled.")
end
end
-- GObject Scale Message Filter
elseif ScaleClarifier and clearmsg:find("[Syntax|was not found|You do not have|Incorrect|GameObject .* has been set to scale]") then
if clearmsg:find("Syntax") or clearmsg:find("was not found") or clearmsg:find("You do not have") or clearmsg:find("Incorrect") then
ScaleClarifier = false
if OPMasterTable.Options["debug"] then
dprint("ScaleClarifier Caught Syntax or Failure, Disabled.")
end
return false
elseif clearmsg:find("GameObject .* has been set to scale") then
ScaleClarifier = false
if OPMasterTable.Options["debug"] then
dprint("ScaleClarifier Caught SCALE Message")
end
return true
end
else
if OPMasterTable.Options["debug"] then
dprint("No Clarifier Caught this, so lets let it pass")
end
return false
end
end
function Filter(Self,Event,Message)
local clearmsg = gsub(Message,"|cff%x%x%x%x%x%x","");
if clearmsg:find("[Selected|Spawned] gameobject") then
lastSelectedObjectID = clearmsg:match("[Selected|Spawned] gameobject .* - (.*)%]")
if OPMasterTable.Options["debug"] then
dprint("Last Selected|Spawned Object = "..tostring(lastSelectedObjectID))
end
end
---------- Auto Update Rotation CAPTURES ----------
if OPRotAutoUpdate:GetChecked()==true and not RotateClarifier then -- Is the AutoUpdate Rot enabled? (Check if RotateClarifier is enabled - if it is, we don't do anything as to not impact the sliders functioning normally)
if clearmsg:find("You have rotated .* [%X%Y%Z]+") then -- Did we get a rotated object message?
dontFuckingRotate = true -- Stop the sliders from actually causing a rotation
if clearmsg:find("X:") then
OPRotationSliderX:SetValueStep(0.0001)
OPRotationSliderX:SetValue(clearmsg:match("X: (%-?%d*%.%d*)"))
if OPMasterTable.Options["debug"] then
dprint("Set Slider X to "..clearmsg:match("X: (%-?%d*%.%d*)"))
end
end
if clearmsg:find("Y:") then
OPRotationSliderY:SetValueStep(0.0001)
OPRotationSliderY:SetValue(clearmsg:match("Y: (%-?%d*%.%d*)"))
if OPMasterTable.Options["debug"] then
dprint("Set Slider Y to "..clearmsg:match("Y: (%-?%d*%.%d*)"))
end
end
if clearmsg:find("Z:") then
OPRotationSliderZ:SetValueStep(0.0001)
OPRotationSliderZ:SetValue(clearmsg:match("Z: (%-?%d*%.%d*)"))
if OPMasterTable.Options["debug"] then
dprint("Set Slider Z to "..clearmsg:match("Z: (%-?%d*%.%d*)"))
end
end
dontFuckingRotate = false -- Allow sliders to cause rotation again
end
if clearmsg:find("Pitch: %-?%d*%.%d*|r, Roll: %-?%d*%.%d*|r, Yaw/Turn: %-?%d*%.%d*|r") then
local pitch = clearmsg:match("Pitch: (%-?%d*%.%d*)|r, Roll: %-?%d*%.%d*|r, Yaw/Turn: %-?%d*%.%d*|r")
local roll = clearmsg:match("Pitch: %-?%d*%.%d*|r, Roll: (%-?%d*%.%d*)|r, Yaw/Turn: %-?%d*%.%d*|r")
local yaw = clearmsg:match("Pitch: %-?%d*%.%d*|r, Roll: %-?%d*%.%d*|r, Yaw/Turn: (%-?%d*%.%d*)|r")
dontFuckingRotate = true
OPRotationSliderX:SetValueStep(0.0001)
OPRotationSliderY:SetValueStep(0.0001)
OPRotationSliderZ:SetValueStep(0.0001)
OPRotationSliderX:SetValue(roll)
OPRotationSliderY:SetValue(pitch)
OPRotationSliderZ:SetValue(yaw)
dontFuckingRotate = false
if OPMasterTable.Options["debug"] then
dprint("Roll: "..roll.." | Pitch: "..pitch.." | Turn: "..yaw)
end
end
end
------------------------------------------------
---- Handling Hiding Messages to avoid Spam ----
if ObjectClarifier or SpawnClarifier or ScaleClarifier or RotateClarifier then
--Check to see if we sent a request and we don't want to see messages
if OPShowMessages:GetChecked() ~= true then
if (RunChecks(Message)) then
return true
end
else
RunChecks(Message)
end
end
end
--Apply filter
ChatFrame_AddMessageEventFilter("CHAT_MSG_SYSTEM", Filter)
-------------------------------------------------------------------------------
-- Slash Command Handlers
-------------------------------------------------------------------------------
function SlashCmdList.SHOWCLOSE()
if not OPMainFrame:IsShown() then
OPMainFrame:Show()
else
OPMainFrame:Hide()
end
end
SLASH_OPDEBUG1 = '/opdebug';
function SlashCmdList.OPDEBUG(msg, editbox) -- 4.
if msg:find("clarifier") then
dprint("RotateClarifier = "..tostring(RotateClarifier).." | SpawnClarifier = "..tostring(SpawnClarifier).." | ObjectClarifier = "..tostring(ObjectClarifier).." | ScaleClarifier = "..tostring(ScaleClarifier))
else
OPMasterTable.Options["debug"] = not OPMasterTable.Options["debug"]
dprint("Object Mover Debug Set to: "..tostring(OPMasterTable.Options["debug"]))
end
end
SLASH_OPDELPARAM1 = '/opdelparam';
function SlashCmdList.OPDELPARAM(msg, editbox) -- 4.
if msg then
for k,v in ipairs(OPMasterTable.ParamPresetKeys) do
if msg == v then
table.remove(OPMasterTable.ParamPresetKeys, k)
OPMasterTable.ParamPresetContent[msg] = nil
print("ObjectMover: Deleting Parameter Pre-set "..msg)
else
if OPMasterTable.Options["debug"] then
dprint(""..msg.." is not a saved Param Pre-set?")
end
end
end
else
print("ObjectMover SYNTAX: '/opdelparam [name of Parameter Pre-set to delete]'")
end
end
SLASH_OPDELROT1 = '/opdelrot';
function SlashCmdList.OPDELROT(msg, editbox) -- 4.
if msg then
for k,v in ipairs(OPMasterTable.RotPresetKeys) do
if msg == v then
table.remove(OPMasterTable.RotPresetKeys, k)
OPMasterTable.RotPresetContent[msg] = nil
print("ObjectMover: Deleting Rotation Pre-set: "..msg)
else
if OPMasterTable.Options["debug"] then
dprint(""..msg.." is not a saved Rot Pre-set?")
end
end
end
else
print("ObjectMover SYNTAX: '/opdelparam [name of Parameter Pre-set to delete]'")
end
end
<file_sep>/README.md
# ObjectMover
World of Warcraft Addon designed for use on servers running the Enteleaie Core that helps users place, move, and manipulate game objects.
## Installation
Drag the "ObjectMover" addon to your Epsilon/\_retail_/Interface/Addons/ folder.
Launch the game, and login. In bottom left of Character Select, click "Addons" and then ensure ObjectMover is enabled. Use "/om", "/obj" or click on the button on the MiniMap once ingame to show the GUI. (Can be dragged around to reposition anywhere around the minimap).
https://forums.epsilonwow.net/topic/467-addon-convenientcommands-objectmover/
| f8ec4866525bb605e1013bb12d48588bc39fe62e | [
"Markdown",
"Lua"
] | 2 | Lua | Marie-Donnie/ThingsMover | 4eb6f0c937abc756b6a3e6384dd266142b175e15 | c4852d79ed9131eab34cb2bb7d7f0b89115636b6 |
refs/heads/master | <repo_name>ericbellet/recomendacion-modelos<file_sep>/src/generate_ROC.R
generate_ROC <- function(scores, real, target){
# Genera una curva de ROC.
#
# Args:
# scores: Los scores por instancia (no necesariamente ordenados).
# real: La verdadera clase de las instancias.
# target: La clase target. En el caso de que nclass > 2 entonces haga un enfoque 1 vs all.
#
# Returns:
# Genera la curva ROC.
#En caso que hayan 2 clases nada mas.
if (length(unique(real)) <= 2){
df <- data.frame(scores,real)
df <- df[order(df$scores, decreasing = TRUE),]
graficador(df$scores, df$real, target)
}else{
#En caso que hayan mas de 2 clases.
clases <- unique(real)
clases <- clases[!clases %in% target]
#-------------1 vs all---------------------
for (i in 1:length(clases)) {
#Se toma el valor positivo como uno solo, y los demas como negativos.
df <- data.frame(scores,real)
class1 <- df[df$real == target,]
class2 <- df[df$real == clases[i],]
df <- merge(x = class1, y = class2, all = TRUE)
df <- df[order(df$scores, decreasing = TRUE),]
graficador(df$scores, df$real, target)
}
}#endif
}#endfunction
graficador <- function(scores, real, target){
# Genera una curva de ROC.
#
# Args:
# scores: Los scores por instancia (no necesariamente ordenados).
# real: La verdadera clase de las instancias.
# target: La clase target. En el caso de que nclass > 2 entonces haga un enfoque 1 vs all.
#
# Returns:
# Genera la curva ROC.
divy <- 1/length(which(real==target))
divx <- 1/(length(real)-length(which(real==target)))
contx <- 0
conty <- 0
negativaclase <- unique(real)
negativaclase <- negativaclase[!negativaclase %in% target]
plot(x=NULL,y=NULL,xlim=c(0, 1), ylim=c(0, 1), xlab="False positive rate", ylab="True positive rate",main=paste("Clase target:",target,".","Clase negativa:", negativaclase[1],"."))
lines(x = c(0,1), y = c(0,1), col = "blue")
puntosx <<- c(contx)
puntosy <<- c(conty)
id <- order(puntosx)
i <- 1
while (i != (length(scores)+1)){
puntosx <<- c(puntosx, contx)
puntosy <<- c(puntosy, conty)
#Existen varios elementos con el mismo score??
samescore <- length(which(scores==scores[i]))
if (samescore > 1){
contador <- 0
contxORIGEN <- contx
contyORIGEN <- conty
points(contx, conty, col = "red")
while (contador != samescore ) {
#Si es target
if (real[i] == target){
#points(contx, conty, col = "red")
conty <- conty + divy
}else{
#Si es negativo
#points(contx, conty, col = "red")
contx <- contx + divx
}
#capaz hay que restar
i <- i + 1
contador <- contador + 1
}#endwhile
lines(x = c(contxORIGEN, contx) , y = c(contyORIGEN,conty), col = "green")
}else{
#Si es target
if (real[i] == target){
points(contx, conty, col = "red")
lines(x = c(contx, contx), y = c(conty, conty + divy) , col = "green")
conty <- conty + divy
i <- i + 1
}else{
#Si es negativo
points(contx, conty, col = "red")
lines(x = c(contx, contx + divx) , y = c(conty,conty), col = "green")
contx <- contx + divx
i <- i + 1
}
}
}#endfor
#Grafico el ultimo punto.
puntosx <<- c(puntosx,1)
puntosy <<- c(puntosy,1)
points(1, 1, col = "red")
lines(x = c(contx, 1), y = c(conty, 1) , col = "green")
#???legend("bottomright", title = paste("ROC area:",auc(puntosx, puntosy)))
}#endgraficador
#EJEMPLO PIAZZA
y = c(2, 2, 1, 2, 2, 2, 2, 1, 2, 1, 2, 1, 2, 1, 1, 1, 2, 1, 1, 1)
scores = c(0.9, 0.8, 0.7, 0.6, 0.55, 0.54, 0.53, 0.52, 0.5, 0.5, 0.5, 0.5, 0.38, 0.37, 0.36, 0.35, 0.34, 0.33, 0.30, 0.1)
target = 2
#Llamando a la funcion.
generate_ROC(scores, y, 2)
setwd("C:/Users/Eric/Desktop/recomendacion-modelos/")
#EJEMPLO PAPER 1
ejemplo <- read.csv("data/roc1.csv")
generate_ROC(ejemplo$scores, ejemplo$real, "p")
#EJEMPLO PAPER 2
ejemplo <- read.csv("data/roc2.csv")
generate_ROC(ejemplo$scores, ejemplo$real, "p")
#EJEMPLO PAPER 3
ejemplo <- read.csv("data/roc3.csv")
generate_ROC(ejemplo$scores, ejemplo$real, "p")
#scores = c(0.90, 0.80, 0.70, 0.60, 0.55, 0.54, 0.53, 0.53, 0.53, 0.53, 0.53, 0.53, 0.53, 0.37, 0.36,
# 0.35, 0.34, 0.33, 0.30, 0.10)
#c("p","e", "n", "p", "p", "p", "n", "e", "p", "n", "p","n", "e", "r", "n", "n", "r", "n", "p", "r")
<file_sep>/README.md
# [Sistema de recomendacion y evaluacion de modelos <NAME>](https://github.com/ericbellet/recomendacion-modelos)
## Tabla de contenido
* [Contenido](#contenido)
* [Referencias](#referencias)
* [Integrantes](#integrantes)
### Contenido
* En la carpeta docs -> Tarea_4.pdf.
* En la carpeta docs -> ROCintro.pdf.
* En la carpeta docs -> informe.pdf
#### Se encuentran las distintas implementaciones, generate_ROC.R permite la evaluacion de modelos y recomendacion.R permite el sistema de recomendaciones
* En la carpeta src -> generate_ROC
* En la carpeta src -> recomendacion
#### Se encuentran los distintas datasets, periodico.csv es usado para el sistema de recomendaciones y roc1.csv, roc2.csv y roc3.cs son usados para la evaluacion de modelos.
* En la carpeta data -> ejemplo.csv.
* En la carpeta data -> periodico.csv.
* En la carpeta data -> roc1.csv.
* En la carpeta data -> roc2.csv.
* En la carpeta data -> roc3.csv.
#### Se encuentran las distintas aplicaciones hechas en Shiny.
* En la carpeta shiny -> generate_rocSHINY
### Referencias
* http://www.bioinf.jku.at/software/apcluster/APCluster-Webinar.pdf
* http://sedici.unlp.edu.ar/bitstream/handle/10915/42405/Documento_completo.pdf?sequence=1
* http://masteres.ugr.es/moea/pages/curso201415/tfm1415/sancheznavarro_tfm/!
*
## Integrantes
**<NAME>**<file_sep>/shiny/generate_rocSHINY.R
require(shiny)
####################CAMBIAR###################
setwd("C:/Users/Eric/Desktop/recomendacion-modelos")
##############################################
source("src/generate_ROC.r")
runApp(
list(
ui = fluidPage(
headerPanel('Generador de curvas ROC'),
sidebarPanel(
fileInput('file1', 'Seleccione el .csv para generar la curva ROC'),
textInput("target", label="Target", value="Introduzca el target"),
actionButton("addButton", "GENERAR CURVA DE ROC"),
p('En la carpeta data hay 3 datasets con los que puede probar, si quiere introducir otro .csv asegurese que el nombre de la columna de los scores sea "scores" y el de las clases "real".'),
p("roc1.csv es el ejemplo del paper (las clases son p y n), roc2.csv es el ejemplo de piazza (las clases son p y n) y roc3.csv posee varias clases n, p, e y r. ")
),
mainPanel(
uiOutput("plots")
)),
server = function(input, output) {
dataset <- eventReactive(input$addButton, {
inFile <- input$file1
df <- read.csv(inFile$datapath)
df$target <- input$target
return(df)
})
output$plots <- renderUI({
df <- dataset()
n <- length(unique(df$real))-1
plot_output_list <- lapply(1:n, function(i) {
plotname <- paste("plot", i, sep="")
plotOutput(plotname, height = 580, width = 550)
})
do.call(tagList, plot_output_list)
})
observe({
df <- dataset()
n <- length(unique(df$real))-1
real = df$real
scores = df$scores
target = df$target[1]
clases <- unique(real)
clases <- clases[!clases %in% target]
for (i in 1:length(clases)) {
local({
#Se toma el valor positivo como uno solo, y los demas como negativos.
df <- data.frame(scores,real)
class1 <- df[df$real == target,]
class2 <- df[df$real == clases[i],]
df <- merge(x = class1, y = class2, all = TRUE)
df <- df[order(df$scores, decreasing = TRUE),]
r <- df$real
s <- df$scores
plotname <- paste("plot", i, sep="")
output[[plotname]] <- renderPlot({
re = r
sco = s
generate_ROC(sco, re,target)
})
})#endlocal
}
})
}
)
)<file_sep>/src/recomendacion.R
###############CAMBIAR##########################
setwd("C:/Users/Eric/Desktop/recomendacion-modelos/")
################################################
install = function(pkg)
{
# Si ya está instalado, no lo instala.
if (!require(pkg, character.only = TRUE)) {
install.packages(pkg)
if (!require(pkg, character.only = TRUE)) stop(paste("load failure:", pkg))
}
}
#Instalo automaticamente los paquetes.
install('arules')
install('arulesViz')
install('apcluster')
#Cargo las librerias.
library(arules)
library(arulesViz)
library(apcluster)
##-------------------------------LECTURA -----------------------------------
ejemplo <- read.csv("data/ejemplo.csv")
periodico <- read.csv("data/periodico.csv")
#CREA LA COLUMNA ARTICLES
#------------------FUNCTION genArticles-----------------
genArticles <- function(articles){
# Genera la columna articles utilizando la columna items.
#
# Args:
# articles: Son arreglos númericos que representan los items (EJ: {item1,item9,item63} -> 1,9,63)
#
# Returns:
# Retorna la columna articles.
articulo <- ""
for (i in 1:length(articles)) {
if (as.integer(articles[i]) <= 9 & as.integer(articles[i]) >= 1){
articulo <- paste(articulo, gsub(" ","",paste("deportes/articulo",articles[i])))
}
if (as.integer(articles[i]) <= 18 & as.integer(articles[i]) >= 10){
articulo <- paste(articulo, gsub(" ","",paste("politica/articulo",(as.integer(articles[i])-9))))
}
if (as.integer(articles[i]) <= 27 & as.integer(articles[i]) >= 19){
articulo <- paste(articulo, gsub(" ","",paste("variedades/articulo",(as.integer(articles[i])-18))))
}
if (as.integer(articles[i]) <= 36 & as.integer(articles[i]) >= 28){
articulo <- paste(articulo, gsub(" ","",paste("internacional/articulo",(as.integer(articles[i])-27))))
}
if (as.integer(articles[i]) <= 45 & as.integer(articles[i]) >= 37){
articulo <- paste(articulo, gsub(" ","",paste("nacionales/articulo",(as.integer(articles[i])-36))))
}
if (as.integer(articles[i]) <= 54 & as.integer(articles[i]) >= 46){
articulo <- paste(articulo, gsub(" ","",paste("sucesos/articulo",(as.integer(articles[i])-45))))
}
if (as.integer(articles[i]) <= 63 & as.integer(articles[i]) >= 55){
articulo <- paste(articulo, gsub(" ","",paste("comunidad/articulo",(as.integer(articles[i])-54))))
}
if (as.integer(articles[i]) <= 72 & as.integer(articles[i]) >= 64){
articulo <- paste(articulo, gsub(" ","",paste("negocios/articulo",(as.integer(articles[i])-63))))
}
if (as.integer(articles[i]) <= 81 & as.integer(articles[i]) >= 73){
articulo <- paste(articulo, gsub(" ","",paste("opinion/articulo",(as.integer(articles[i])-72))))
}
}
return(articulo)
}
#--------------END FUNCTION genArticles-----------------
genArticles2 <- function(articles){
# Genera la columna articles utilizando la columna items.
#
# Args:
# articles: Son arreglos númericos que representan los items (EJ: {item1,item9,item63} -> 1,9,63)
#
# Returns:
# Retorna la columna articles.
articulo <- ""
for (i in 1:length(articles)) {
if (as.integer(articles[i]) <= 9 & as.integer(articles[i]) >= 1){
articulo <- paste(articulo, gsub(" ","",paste("deportes")))
}
if (as.integer(articles[i]) <= 18 & as.integer(articles[i]) >= 10){
articulo <- paste(articulo, gsub(" ","",paste("politica")))
}
if (as.integer(articles[i]) <= 27 & as.integer(articles[i]) >= 19){
articulo <- paste(articulo, gsub(" ","",paste("variedades")))
}
if (as.integer(articles[i]) <= 36 & as.integer(articles[i]) >= 28){
articulo <- paste(articulo, gsub(" ","",paste("internacional")))
}
if (as.integer(articles[i]) <= 45 & as.integer(articles[i]) >= 37){
articulo <- paste(articulo, gsub(" ","",paste("nacionales")))
}
if (as.integer(articles[i]) <= 54 & as.integer(articles[i]) >= 46){
articulo <- paste(articulo, gsub(" ","",paste("sucesos")))
}
if (as.integer(articles[i]) <= 63 & as.integer(articles[i]) >= 55){
articulo <- paste(articulo, gsub(" ","",paste("comunidad")))
}
if (as.integer(articles[i]) <= 72 & as.integer(articles[i]) >= 64){
articulo <- paste(articulo, gsub(" ","",paste("negocios")))
}
if (as.integer(articles[i]) <= 81 & as.integer(articles[i]) >= 73){
articulo <- paste(articulo, gsub(" ","",paste("opinion")))
}
}
return(paste(unique(unlist(strsplit(articulo, " "))), sep="", collapse=", "))
}
#--------------END FUNCTION genArticles-----------------
#LLENA LA MATRIZ DE TRANSACCIONES,
#------------------FUNCTION llenar-----------------
llenar <- function(periodico,fila){
# Llena la matriz de transacciones con 1 en caso de que el usuario observo los articulos.
#
# Args:
# periodico: Recibe los items.
# fila: recibe una fila vacia.
#
# Returns:
# Retorna la matriz de transacciones llena.
items <- as.numeric(unlist(strsplit(gsub("[{}item]","",unlist(periodico)), ",")))
fila[items]=1
return(fila)
}
#--------------END FUNCTION llenar-----------------
#------------------FUNCTION recomendar-----------------
recomendar <- function(n, matriz){
#plot(rules,method="graph",interactive=TRUE,shading=NA)
#plot(rules, measure=c("support","lift"), shading="confidence");
#plot(rules, shading="order", control=list(main ="Two-key plot"));
rules <- apriori(matriz,parameter = list(support = 0.1, confidence = 0.0))
reglas <- subset(rules, subset = lhs %ain% n )
len <- length(reglas)
div <- 0.1
cont <- 0
#En el caso que no se generaron reglas con ese soporte, voy disminuyendo el soporte
while (len == 0){
div <- div /10
rules <- apriori(matriz,parameter = list(support = div, confidence = 0.0))
reglas <- subset(rules, subset = lhs %ain% n )
len <- length(reglas)
cont <- cont + 1
#Un criterio de parada ya que puede ser infinito
if (cont == 7){
break()
}
}
if (length(reglas)==0){
trendigtop<-inspect(rules@rhs)
return(row.names(sort(table(trendigtop),decreasing=TRUE))[1])
}else{
confianzaAlta <-sort(reglas, decreasing = TRUE,
na.last = NA,by = "confidence",
order = FALSE)
#Obtengo la confianza maxima para luego tomar todos los articulos que posean esa confianza
maxConfianza <- max(quality((confianzaAlta))[2])
#Posiciones que poseen la misma confianza.
confianzaAlta<- subset(confianzaAlta, subset = confidence == maxConfianza)
#Ahora ordeno por soporte las que tienen la confianza mas alta
soportealto <- (sort(confianzaAlta, decreasing = TRUE,
na.last = NA,by = "support",
order = FALSE)[1])
articulorecomendar <- inspect(soportealto@rhs[1])
return(articulorecomendar$items[1])
}
}
#------------------END FUNCTION recomendar-----------------
##---------------------------PARTE 1--------------------------------
##----------------------------GENERACION DE ARTICULOS---------------------------------
#1. Modifcar su dataset de tal manera que no se lean los identificadores de los artículos
#como itemN sino por su tipo de contenido contenido/articuloN.
#Ejemplo: {item1, item10, item81}
#es la transacción {deportes/articulo1, politica
#/articulo1, opinion/articulo9}.
#deportes 1-9
#politica 10-18
#variedades 19-27
#internacional 28-36
#nacionales 37-45
#sucesos 46-54
#comunidad 55-63
#negocios 64-72
#opinion 73-81
#Cambio el nombre de la columna para que tenga coherencia con el ejemplo dado.
colnames(periodico)[5] <- "items"
#Creo la columna de los articulos
periodico$articles <- periodico$items
periodico$individual <- periodico$items
#Se sabe que el portal ofrece 9 tipos de contenidos
#y nos ofrecen solo información de 9 artículos.
#Obtengo el numero de los articulos.
periodico$articles <- strsplit(gsub("[{}item]","",periodico$articles), ",")
periodico$individual<- strsplit(gsub("[{}item]","",periodico$individual), ",")
periodico$individual <- lapply(periodico$individual, genArticles2)
periodico$individual <- substring(periodico$individual, 2)
#Modifico el dataset con las condiciones dadas.
periodico$articles <- lapply(periodico$articles, genArticles)
#Convierto los espacios en ,
periodico$articles <- gsub(" ",",",periodico$articles)
#Elimino la primer valor del string.
periodico$articles <- substring(periodico$articles, 2)
#Calculo el tiempo totan el segundos que dura el usuario en la pagina.
periodico$tiempototal <- difftime(periodico$exit, periodico$entry, units = "secs")
##-------------------------------FIN PARTE 1--------------------------------
#GENERACION DE MATRIZ DE TRANSACCIONES Y DETECTAR USUARIOS ROBOTS
#Generar la matriz de transacciones para recomendar articulos.
#fila es un row inicializado en 0.
fila <- matrix(data = 0, nrow = 1, ncol = 81)
#Lleno la matriz con 1 donde un usuario observo un articulo
matriz <- lapply(periodico$items, llenar,fila)
#Transformo matriz en una matrix.
matriz <- matrix(unlist(matriz), byrow=T, ncol=81)
#Nombro las columnas
colnames(matriz) <- c(gsub(" ","",paste("deportes/articulo",1:9)),gsub(" ","",paste("politica/articulo",1:9)),
gsub(" ","",paste("variedades/articulo",1:9)), gsub(" ","",paste("internacional/articulo",1:9)),
gsub(" ","",paste("nacionales/articulo",1:9)), gsub(" ","",paste("sucesos/articulo",1:9)),
gsub(" ","",paste("comunidad/articulo",1:9)), gsub(" ","",paste("negocios/articulo",1:9)),
gsub(" ","",paste("opinion/articulo",1:9)))
#-------------------------------TRANSACCIONES BOTS---------------------------------------
#El número de posibles transacciones bot que tienen en su dataset
#(ellos aceptan que si una persona ve un artículo más de 20 segundos entonces no es un bot).
periodico$numItems <- rowSums(matriz)
numerobots <- periodico[periodico$numItems >= periodico$tiempototal/20,]
print(paste("El numero de transacciones bot es:",nrow(numerobots)))
periodicoSinBots <- periodico[-numerobots$X,]
#Utilizamos la matriz de transacciones sin las transacciones bots.
matriz <- matriz[-numerobots$X,]
##-------------------------------PARTE 2------------------------------------
#2. Conocer los tipos de usuarios que ingresan a su página (ellos creen que
#son 8 tipos de usuarios) y tratar de determinar la proporción de cada tipo de usuario.
#GENERACION DE MATRIZ DE TRANSACCIONES
#Matriz de transacciones para detectar grupos
#matrix2 <- matrix(data = 0, nrow = nrow(matriz), ncol = 9)
#matrix2[,1] <- rowSums(matriz[,1:9])
#matrix2[,2] <- rowSums(matriz[,10:18])
#matrix2[,3] <- rowSums(matriz[,19:27])
#matrix2[,4] <- rowSums(matriz[,28:36])
# matrix2[,5] <- rowSums(matriz[,37:45])
#matrix2[,6] <- rowSums(matriz[,46:54])
# matrix2[,7] <- rowSums(matriz[,55:63])
# matrix2[,8] <- rowSums(matriz[,64:72])
# matrix2[,9] <- rowSums(matriz[,73:81])
# matrix2[,1] <- apply(matriz[,1:9],1,max)
# matrix2[,2] <- apply(matriz[,10:18],1,max)
# matrix2[,3] <- apply(matriz[,19:27],1,max)
# matrix2[,4] <- apply(matriz[,28:36],1,max)
# matrix2[,5] <- apply(matriz[,37:45],1,max)
# matrix2[,6] <- apply(matriz[,46:54],1,max)
# matrix2[,7] <- apply(matriz[,55:63],1,max)
# matrix2[,8] <- apply(matriz[,64:72],1,max)
# matrix2[,9] <- apply(matriz[,73:81],1,max)
#colnames(matrix2) <- c("deportes","politica","variedades","internacional","nacionales", "sucesos","comunidad","negocios","opinion")
kmedias <- kmeans(matriz, 8,algorithm = "Hartigan-Wong")
periodicoSinBots$cluster <- kmedias$cluster
table(periodicoSinBots$cluster)
#Calculamos la matriz de similaridad utilizando el inverso del error cuadrado (distancia euclidea).
sim <- crossprod(matriz)
sim <- sim / sqrt(sim)
#Corremos la affinity propagation
clust_ap <- apcluster(sim)
show(clust_ap)
matriz <<- as(matriz, "transactions")
rules <- apriori(matriz,parameter = list(support = 0.000008019181883, confidence = 1.0))
plot(rules, method = "grouped", control = list(k = 8))
#ruledf = data.frame(
# lhs = labels(lhs(rules)),
# rhs = labels(rhs(rules)))
##-------------------------------FIN PARTE 2------------------------------------
##-------------------------------PARTE 3------------------------------------
#3. Dado un usuario nuevo que haya ingresado a n artículos (n variable),
#poder recomendar un artículo n+1 y así aumentar el compromiso del cliente
#con su portal web. Como usted sabe, para poder calcular las reglas necesita
#como entrada MinSupport y MinConfianza. Sin embargo, el cliente desconoce cuáles
#son estos valores en consecuencia es tarea de usted determinar y justi???car los
#mismos de acuerdo a su criterio
print("Introduzca los n articulos:")
#n <- c("deportes/articulo1","internacional/articulo1", "comunidad/articulo1")
#n <- c("deportes/articulo6","deportes/articulo9")
n <- c("deportes/articulo6","internacional/articulo9")
articuloARecomendar <- recomendar(n, matriz)
print(paste("El artículo que se recomienda es:", articuloARecomendar))
##-------------------------------FIN PARTE 3--------------------------------
##-------------------------------PARTE 4------------------------------------
#4. Conocer las 10 visitas con mayor tiempo de estadía en la página y
#las 10 visitas con menor tiempo de estadía en la página.
timemayor10 <- periodicoSinBots[order(periodicoSinBots$tiempototal,decreasing = T),][1:10,c(1,7)]
print("10 visitas con mayor tiempo de estadía en la página:")
print(timemayor10)
timemenor10 <- periodicoSinBots[order(periodicoSinBots$tiempototal,decreasing = F),][1:10,c(1,7)]
print("10 visitas con menor tiempo de estadía en la página:")
print(timemenor10)
##-------------------------------FIN PARTE 4--------------------------------
##-------------------------------PARTE 5------------------------------------
top10 <- sort(itemFrequency(matriz, type = "absolute"),decreasing = T)[1:10]
print("Los 10 articulos con mayor numero de apariciones son:")
print(top10)
itemFrequencyPlot(matriz,topN=10,type="absolute", main ="Los 10 articulos con mayor numero de apariciones.")
#5. Conocer las 10 transacciones con mayor número de apariciones en el dataset
MatrizSinBots = split(periodicoSinBots$articles,periodicoSinBots$X)
MatrizSinBots = as(MatrizSinBots,"transactions")
top10transacciones <- sort(itemFrequency(MatrizSinBots, type = "absolute"),decreasing = T)[1:10]
print("Las 10 transacciones con mayor numero de apariciones son:")
print(top10transacciones)
itemFrequencyPlot(MatrizSinBots,topN=10,type="absolute", main = "Las 10 transacciones con mayor numero de apariciones.")
<file_sep>/src/informe.Rmd
---
title: "Sistemas de recomendación y evaluación de modelos"
author: "<NAME>"
date: "18 mayo 2016"
output: html_document
---
```{r setup, include=FALSE}
knitr::opts_chunk$set(echo = TRUE)
```
#Sistemas de recomendación
## Introducción
El siguiente sistema de recomendación esta basado en en 131000 transacciones de artículos de un periódico, donde existen 9 artículos por cada contenido, los cuales son:
* Deportes.
* Politica.
* Variedades.
* Internacional.
* Nacionales.
* Sucesos.
* Comunidad.
* Negocios.
* Opinión.
## Arules
Se utilizó el paquete arules de R para poder generar reglas de asociación.
```{r, echo=FALSE, results='hide', include=FALSE}
###############CAMBIAR##########################
setwd("C:/Users/Eric/Desktop/recomendacion-modelos/")
################################################
install = function(pkg)
{
# Si ya está instalado, no lo instala.
if (!require(pkg, character.only = TRUE)) {
install.packages(pkg)
if (!require(pkg, character.only = TRUE)) stop(paste("load failure:", pkg))
}
}
install('arules')
install('arulesViz')
install('apcluster')
#Cargo las librerias.
library(arules)
library(arulesViz)
library(apcluster)
##-------------------------------LECTURA -----------------------------------
ejemplo <- read.csv("data/ejemplo.csv")
periodico <- read.csv("data/periodico.csv")
```
##Primera parte
Modificar su dataset de tal manera que no se lean los identificadores de los artículos como itemN sino por su tipo de contenido contenido/articuloN. Ejemplo: {item1, item10, item81} es la transacción {deportes/articulo1, politica/articulo1, opinion/articulo9}.
Para modificar el dataset dada estas condiciones se realizó lo siguiente:
* Se cambio el nombre la columna 5 y se creó la columna **articles** y se llenó con vectores númericos que representan los items que observó el usuario.
```{r}
#Cambio el nombre de la columna para que tenga coherencia con el ejemplo dado.
colnames(periodico)[5] <- "items"
#Creo la columna de los articulos
periodico$articles <- periodico$items
#Se sabe que el portal ofrece 9 tipos de contenidos
#y nos ofrecen solo información de 9 artículos.
#Obtengo el numero de los articulos.
periodico$articles <- strsplit(gsub("[{}item]","",periodico$articles), ",")
```
* Dado los vectores de cada fila de la columna *articles* se modificó para que tuviera el formato *contenido/articuloN* utilizando la función genArticles.
```{r}
genArticles <- function(articles){
# Genera la columna articles utilizando los items.
#
# Args:
# articles: Son arreglos númericos que representan los items (EJ: {item1,item9,item63} -> 1,9,63)
#
# Returns:
# Retorna la columna articles.
articulo <- ""
for (i in 1:length(articles)) {
if (as.integer(articles[i]) <= 9 & as.integer(articles[i]) >= 1){
articulo <- paste(articulo, gsub(" ","",paste("deportes/articulo",articles[i])))
}
if (as.integer(articles[i]) <= 18 & as.integer(articles[i]) >= 10){
articulo <- paste(articulo, gsub(" ","",paste("politica/articulo",(as.integer(articles[i])-9))))
}
if (as.integer(articles[i]) <= 27 & as.integer(articles[i]) >= 19){
articulo <- paste(articulo, gsub(" ","",paste("variedades/articulo",(as.integer(articles[i])-18))))
}
if (as.integer(articles[i]) <= 36 & as.integer(articles[i]) >= 28){
articulo <- paste(articulo, gsub(" ","",paste("internacional/articulo",(as.integer(articles[i])-27))))
}
if (as.integer(articles[i]) <= 45 & as.integer(articles[i]) >= 37){
articulo <- paste(articulo, gsub(" ","",paste("nacionales/articulo",(as.integer(articles[i])-36))))
}
if (as.integer(articles[i]) <= 54 & as.integer(articles[i]) >= 46){
articulo <- paste(articulo, gsub(" ","",paste("sucesos/articulo",(as.integer(articles[i])-45))))
}
if (as.integer(articles[i]) <= 63 & as.integer(articles[i]) >= 55){
articulo <- paste(articulo, gsub(" ","",paste("comunidad/articulo",(as.integer(articles[i])-54))))
}
if (as.integer(articles[i]) <= 72 & as.integer(articles[i]) >= 64){
articulo <- paste(articulo, gsub(" ","",paste("negocios/articulo",(as.integer(articles[i])-63))))
}
if (as.integer(articles[i]) <= 81 & as.integer(articles[i]) >= 73){
articulo <- paste(articulo, gsub(" ","",paste("opinion/articulo",(as.integer(articles[i])-72))))
}
}
return(articulo)
}
#Modifico el dataset con las condiciones dadas.
periodico$articles <- lapply(periodico$articles, genArticles)
```
* Finalmente se realizan modificaciones en la columna articles para que tengan el formato adecuado y se calcula el tiempo total que estuvó un usuario observando los artículos.
```{r}
#Convierto los espacios en ,
periodico$articles <- gsub(" ",",",periodico$articles)
#Elimino la primer valor del string.
periodico$articles <- substring(periodico$articles, 2)
#Calculo el tiempo totan el segundos que dura el usuario en la pagina.
periodico$tiempototal <- difftime(periodico$exit, periodico$entry, units = "secs")
```
Este es el resultado de la primera parte.
```{r}
head(periodico[,c(1,5,6,7)])
```
## Generación de matriz de transacciones
Para poder generar las reglas utilizando el paquete **arules** es necesario tener una matriz de transacciones, para crearla se realizó lo siguiente.
Se utilizó la función **llenar**, el cual dado lo un vector númerico que representa los items va llenando con 1 aquellos artículos que el usuario observó.
```{r}
#Generar la matriz de transacciones.
#fila es un row inicializado en 0.
fila <- matrix(data = 0, nrow = 1, ncol = 81)
#------------------FUNCTION llenar-----------------
llenar <- function(periodico,fila){
# Llena la matriz de transacciones con 1 en caso de que el usuario observo los articulos.
#
# Args:
# periodico: Recibe los items.
# fila: recibe una fila vacia.
#
# Returns:
# Retorna la matriz de transacciones llena.
items <- as.numeric(unlist(strsplit(gsub("[{}item]","",unlist(periodico)), ",")))
fila[items]=1
return(fila)
}
#--------------END FUNCTION llenar-----------------
#Lleno la matriz con 1 donde un usuario observo un articulo
matriz <- lapply(periodico$items, llenar,fila)
```
Transformo el resultado obtenido por la función **llenar** en una matriz y se le asigna el nombre correspondiente a cada columna.
```{r}
#Transformo matriz en una matrix.
matriz <- matrix(unlist(matriz), byrow=T, ncol=81)
#Nombro las columnas
colnames(matriz) <- c(gsub(" ","",paste("deportes/articulo",1:9)),gsub(" ","",paste("politica/articulo",1:9)),
gsub(" ","",paste("variedades/articulo",1:9)), gsub(" ","",paste("internacional/articulo",1:9)),
gsub(" ","",paste("nacionales/articulo",1:9)), gsub(" ","",paste("sucesos/articulo",1:9)),
gsub(" ","",paste("comunidad/articulo",1:9)), gsub(" ","",paste("negocios/articulo",1:9)),
gsub(" ","",paste("opinion/articulo",1:9)))
```
## Detección de usuarios bots
El periódico tiene sospechas de que existen bots que están ganando dinero al hacer clicks en artículos con promociones. En consecuencia, le piden a usted que realice un análisis exploratorio sobre las transacciones para determinar el número de posibles transacciones bot que tienen en su dataset (ellos aceptan que si una persona ve un artículo más de 20 segundos entonces no es un bot).
Para calcular el número de articulos que observó un usuario se suman las filas de la matriz de transacciones, y luego utilizando el **tiempo total** de un usuario observando los artículos, se calcula cuales son los usuarios **bots** bajo el criterio si una persona ve un artículo 20 segundos o menos entonces es un bot.
```{r}
#El número de posibles transacciones bot que tienen en su dataset
#(ellos aceptan que si una persona ve un artículo más de 20 segundos entonces no es un bot).
periodico$numItems <- rowSums(matriz)
numerobots <- periodico[periodico$numItems >= periodico$tiempototal/20,]
print(paste("El numero de transacciones bot es:",nrow(numerobots)))
```
Finalmente nos interesa generar las reglas de asociación sin los usuarios bots, por lo tanto se eliminan del dataset y de la matriz de transacciones.
```{r}
periodicoSinBots <- periodico[-numerobots$X,]
#Utilizamos la matriz de transacciones sin las transacciones bots.
matriz <- matriz[-numerobots$X,]
#Matriz de transacciones
mm <- matriz
matriz <- as(matriz, "transactions")
```
## Segunda parte
Conocer los tipos de usuarios que ingresan a su página (ellos creen que son 8 tipos de usuarios) y tratar de determinar la proporción de cada tipo de usuario.
En esta fase existen 2 enfoques, el primero es ver los tipos de usuarios solamente por el tipo de **contenido** que ven y el segundo por **contenido y artículo**. Mi criterio fue hacerlo por **contenido y artículo** ya que me parece más específico, por ejemplo: supongamos que deportes/articulo1 habla sobre beisbol, deportes/artículo2 habla sobre fútbol, es distinto un tipo de usuario que solo por contenido (deportes) a uno por **contenido/artículo**.
Si agrupamos utilizando el **lhs** de las reglas, obtenemos estos 8 grupos:
```{r}
rules <- apriori(matriz,parameter = list(support = 0.000008019181883, confidence = 1.0))
plot(rules, method = "grouped", control = list(k = 8))
```
Utilizando **kmedias** usando el algoritmo de **Harting-Wong** se obtiene la siguiente proporción de cada cluster:
```{r}
kmedias <- kmeans(mm, 8,algorithm = "Hartigan-Wong")
periodicoSinBots$cluster <- kmedias$cluster
table(periodicoSinBots$cluster)
```
Luego probamos con clusterización mediante **propagación por afinidad** que toma como conjunto de datos principal similitudes entre los datos. El objetivo es minimizar los errores al cuadrado, cada similaridad se establece como el inverso del error cuadrado (distancia euclídea). Este es un algoritmo de agrupamiento, (clustering), dado un conjunto de puntos y una medida de similaridad entre ellos, proporciona grupos de puntos similares y además para cada grupo da un ejemplar representativo. La medida de similaridad es la información mutua entre cada par de variables aleatorias, la cual expresa la información que ellas comparten.
El número de grupos o clusters no se determina de antemano, sino que es entregado por el algoritmo de propagación de afinidades. El tamaño de cada cluster determina obviamente el número de factores que aparecen en cada distribución marginal y por lo tanto el número de parámetros a estimar.
Podemos observar que utilizando clusterización mediante la propagación por afinidad detecta **8 clusters** donde los tipos de usuarios son los siguientes:
* deportes-articulos1.
* variedades-articulo4.
* sucesos-articulo1.
* sucesos-articulo6.
* negocios-articulo4.
* negocios-articulo-7.
* opinion-articulo4.
* opinion-articulo7.
```{r}
#Calculamos la matriz de similaridad utilizando el inverso del error cuadrado (distancia euclidea).
sim <- crossprod(mm)
sim <- sim / sqrt(sim)
#Corremos la affinity propagation
clust_ap <- apcluster(sim)
show(clust_ap)
```
##Tercera parte
Dado un usuario nuevo que haya ingresado a n artículos (n variable), poder recomendar un artículo n+1 y así aumentar el compromiso del cliente con su portal web. Como usted sabe, para poder calcular las reglas necesita como entrada MinSupport y MinCofianza. Sin embargo, el cliente desconoce cuáles son estos valores en consecuencia es tarea de usted determinar y justficar los mismos de acuerdo a su criterio.
Para recomendar un artículo n + 1 a un usuario se utilizó reglas de asociación. La función implementada es **recomendar** que recibe la matriz de transacciones y el n que representa los artículos ingresados por el usuario. Se generan las reglas con el algoritmo **apriori** con un soporte alto y una confianza baja, en caso de no encontrar un **lhs** en las reglas generadas se va disminuyendo el soporte hasta que se generen reglas, en el caso que no se generen reglas en una cantidad de iteraciones, se recomienda el **rhs** o artículo más popular o que tenga mayor número de apariciones. En el caso que si se generan reglas, se ordenan por confianza de mayor a menor, luego se toman todas las reglas que tengan la misma **confianza máxima** y se ordenan por **soporte** de mayor a menor y finalmente se recomienda el artículo que tenga mayor soporte. En otras palabras se toman las reglas que tengan la confianza máxima y luego la que tenga mayor soporte.
```{r eval=FALSE}
recomendar <- function(n, matriz){
#plot(rules,method="graph",interactive=TRUE,shading=NA)
#plot(rules, measure=c("support","lift"), shading="confidence");
#plot(rules, shading="order", control=list(main ="Two-key plot"));
rules <- apriori(matriz,parameter = list(support = 0.1, confidence = 0.0))
reglas <- subset(rules, subset = lhs %ain% n )
len <- length(reglas)
div <- 0.1
cont <- 0
#En el caso que no se generaron reglas con ese soporte, voy disminuyendo el soporte
while (len == 0){
div <- div /10
rules <- apriori(matriz,parameter = list(support = div, confidence = 0.0))
reglas <- subset(rules, subset = lhs %ain% n )
len <- length(reglas)
cont <- cont + 1
#Un criterio de parada ya que puede ser infinito
if (cont == 7){
break()
}
}
if (length(reglas)==0){
trendigtop<-inspect(rules@rhs)
return(row.names(sort(table(trendigtop),decreasing=TRUE))[1])
}else{
confianzaAlta <-sort(reglas, decreasing = TRUE,
na.last = NA,by = "confidence",
order = FALSE)
#Obtengo la confianza maxima para luego tomar todos los articulos que posean esa confianza
maxConfianza <- max(quality((confianzaAlta))[2])
#Posiciones que poseen la misma confianza.
confianzaAlta<- subset(confianzaAlta, subset = confidence == maxConfianza)
#Ahora ordeno por soporte las que tienen la confianza mas alta
soportealto <- (sort(confianzaAlta, decreasing = TRUE,
na.last = NA,by = "support",
order = FALSE)[1])
articulorecomendar <- inspect(soportealto@rhs[1])
return(articulorecomendar$items[1])
}
}
n <- c("deportes/articulo6","internacional/articulo9")
articuloARecomendar <- recomendar(n, matriz)
```
```{r, include=F}
recomendar <- function(n, matriz){
#plot(rules,method="graph",interactive=TRUE,shading=NA)
#plot(rules, measure=c("support","lift"), shading="confidence");
#plot(rules, shading="order", control=list(main ="Two-key plot"));
rules <- apriori(matriz,parameter = list(support = 0.1, confidence = 0.0))
reglas <- subset(rules, subset = lhs %ain% n )
len <- length(reglas)
div <- 0.1
cont <- 0
#En el caso que no se generaron reglas con ese soporte, voy disminuyendo el soporte
while (len == 0){
div <- div /10
rules <- apriori(matriz,parameter = list(support = div, confidence = 0.0))
reglas <- subset(rules, subset = lhs %ain% n )
len <- length(reglas)
cont <- cont + 1
#Un criterio de parada ya que puede ser infinito
if (cont == 7){
break()
}
}
if (length(reglas)==0){
trendigtop<-inspect(rules@rhs)
return(row.names(sort(table(trendigtop),decreasing=TRUE))[1])
}else{
confianzaAlta <-sort(reglas, decreasing = TRUE,
na.last = NA,by = "confidence",
order = FALSE)
#Obtengo la confianza maxima para luego tomar todos los articulos que posean esa confianza
maxConfianza <- max(quality((confianzaAlta))[2])
#Posiciones que poseen la misma confianza.
confianzaAlta<- subset(confianzaAlta, subset = confidence == maxConfianza)
#Ahora ordeno por soporte las que tienen la confianza mas alta
soportealto <- (sort(confianzaAlta, decreasing = TRUE,
na.last = NA,by = "support",
order = FALSE)[1])
articulorecomendar <- inspect(soportealto@rhs[1])
return(articulorecomendar$items[1])
}
}
n <- c("deportes/articulo6","internacional/articulo9")
articuloARecomendar <- recomendar(n, matriz)
```
```{r}
print(paste("El artículo que se recomienda es:", articuloARecomendar))
```
## Cuarta parte
Conocer las 10 visitas con mayor tiempo de estadía en la página y las 10 visitas con menor tiempo de estadía en la página.
* Las 10 visitas con mayor tiempo de estadía en la página:
```{r}
timemayor10 <- periodicoSinBots[order(periodicoSinBots$tiempototal,decreasing = T),][1:10,c(1,7)]
print("10 visitas con mayor tiempo de estadía en la página:")
print(timemayor10)
```
* Las 10 visitas con menor tiempo de estadía en la página:
```{r}
timemenor10 <- periodicoSinBots[order(periodicoSinBots$tiempototal,decreasing = F),][1:10,c(1,7)]
print("10 visitas con menor tiempo de estadía en la página:")
print(timemenor10)
```
## Quinta parte
Conocer las 10 transacciones con mayor número de apariciones en el dataset.
* Los 10 articulos con mayor numero de apariciones.
```{r}
top10 <- sort(itemFrequency(matriz, type = "absolute"),decreasing = T)[1:10]
print("Los 10 articulos con mayor numero de apariciones son:")
print(top10)
itemFrequencyPlot(matriz,topN=10,type="absolute", main ="Los 10 articulos con mayor numero de apariciones.")
```
```{r}
#TRANSACCIONES:
```
* Las 10 transacciones con mayor número de apariciones en el dataset.
```{r}
MatrizSinBots = split(periodicoSinBots$articles,periodicoSinBots$X)
MatrizSinBots = as(MatrizSinBots,"transactions")
top10transacciones <- sort(itemFrequency(MatrizSinBots, type = "absolute"),decreasing = T)[1:10]
print("Las 10 transacciones con mayor numero de apariciones son:")
print(top10transacciones)
itemFrequencyPlot(MatrizSinBots,topN=10,type="absolute", main = "Las 10 transacciones con mayor numero de apariciones.")
```
# Evaluación de modelos
Las curvas ROC(Receiver Operating Characteristics) son grá???cos usados como técnica de visualización, organización y selección de clasi???cadores basados en su rendimiento.Los parámetros de gra???cador son:
1. Los scores por instancia (no necesariamente ordenados).
2. La verdadera clase de las instancias.
3. La clase target. En el caso de que nclass > 2 entonces haga un enfoque 1 vs all.
```{r eval=FALSE}
generate_ROC <- function(scores, real, target){
# Genera una curva de ROC.
#
# Args:
# scores: Los scores por instancia (no necesariamente ordenados).
# real: La verdadera clase de las instancias.
# target: La clase target. En el caso de que nclass > 2 entonces haga un enfoque 1 vs all.
#
# Returns:
# Genera la curva ROC.
#En caso que hayan 2 clases nada mas.
if (length(unique(real)) <= 2){
df <- data.frame(scores,real)
df <- df[order(df$scores, decreasing = TRUE),]
graficador(df$scores, df$real, target)
}else{
#En caso que hayan mas de 2 clases.
clases <- unique(real)
clases <- clases[!clases %in% target]
#-------------1 vs all---------------------
for (i in 1:length(clases)) {
#Se toma el valor positivo como uno solo, y los demas como negativos.
df <- data.frame(scores,real)
class1 <- df[df$real == target,]
class2 <- df[df$real == clases[i],]
df <- merge(x = class1, y = class2, all = TRUE)
df <- df[order(df$scores, decreasing = TRUE),]
graficador(df$scores, df$real, target)
}
}#endif
}#endfunction
```
La función graficador va graficando los puntos y uniendo las líneas.
```{r eval=FALSE}
graficador <- function(scores, real, target){
# Genera una curva de ROC.
#
# Args:
# scores: Los scores por instancia (no necesariamente ordenados).
# real: La verdadera clase de las instancias.
# target: La clase target. En el caso de que nclass > 2 entonces haga un enfoque 1 vs all.
#
# Returns:
# Genera la curva ROC.
divy <- 1/length(which(real==target))
divx <- 1/(length(real)-length(which(real==target)))
contx <- 0
conty <- 0
negativaclase <- unique(real)
negativaclase <- negativaclase[!negativaclase %in% target]
plot(x=NULL,y=NULL,xlim=c(0, 1), ylim=c(0, 1), xlab="False positive rate", ylab="True positive rate",main=paste("Clase target:",target,".","Clase negativa:", negativaclase[1],"."))
lines(x = c(0,1), y = c(0,1), col = "blue")
puntosx <<- c(contx)
puntosy <<- c(conty)
id <- order(puntosx)
i <- 1
while (i != (length(scores)+1)){
puntosx <<- c(puntosx, contx)
puntosy <<- c(puntosy, conty)
#Existen varios elementos con el mismo score??
samescore <- length(which(scores==scores[i]))
if (samescore > 1){
contador <- 0
contxORIGEN <- contx
contyORIGEN <- conty
points(contx, conty, col = "red")
while (contador != samescore ) {
#Si es target
if (real[i] == target){
#points(contx, conty, col = "red")
conty <- conty + divy
}else{
#Si es negativo
#points(contx, conty, col = "red")
contx <- contx + divx
}
#capaz hay que restar
i <- i + 1
contador <- contador + 1
}#endwhile
lines(x = c(contxORIGEN, contx) , y = c(contyORIGEN,conty), col = "green")
}else{
#Si es target
if (real[i] == target){
points(contx, conty, col = "red")
lines(x = c(contx, contx), y = c(conty, conty + divy) , col = "green")
conty <- conty + divy
i <- i + 1
}else{
#Si es negativo
points(contx, conty, col = "red")
lines(x = c(contx, contx + divx) , y = c(conty,conty), col = "green")
contx <- contx + divx
i <- i + 1
}
}
}#endfor
#Grafico el ultimo punto.
puntosx <<- c(puntosx,1)
puntosy <<- c(puntosy,1)
points(1, 1, col = "red")
lines(x = c(contx, 1), y = c(conty, 1) , col = "green")
#???legend("bottomright", title = paste("ROC area:",auc(puntosx, puntosy)))
}#endgraficador
```
En la carpeta **shiny** se encuentra la aplicación hecha en shiny de esta parte. | 7cb9cbe67eadcaa1c18cada9e62e08462edf7567 | [
"Markdown",
"R",
"RMarkdown"
] | 5 | R | ericbellet/recomendacion-modelos | e919311eb1e536fa5e7e18ffea87827cf5eba68d | 3e90f60f5f6e63f518dfc9454f640ec09d7b1881 |
refs/heads/master | <file_sep>def counter_maker():
count = 0
def counter():
nonlocal count
count += 1
print(count)
return counter
my_counter = counter_maker()
your_counter = counter_maker()
my_counter()
my_counter()
my_counter()
my_counter()
your_counter()
your_counter()
your_counter()
your_counter()
<file_sep>function counterMaker() {
let count = 0
function counter() {
count++
console.log(count)
}
return counter
}
myCounter = counterMaker()
yourCounter = counterMaker()
myCounter()
myCounter()
myCounter()
myCounter()
yourCounter()
yourCounter()
yourCounter()
yourCounter()
| 8adeff662bbd75d982bf9ed308157a1079f8734f | [
"JavaScript",
"Python"
] | 2 | Python | rob-3/nonlocal-python-example | c86afa3612b978250eeaf9306ee24d2da6667772 | 87a5cdc5b5c16cca20e0b42844cd4172a4b4587f |
refs/heads/master | <file_sep>package com.dadashow.countriesappkotlin.view
import android.os.Bundle
import androidx.fragment.app.Fragment
import android.view.LayoutInflater
import android.view.View
import android.view.ViewGroup
import androidx.databinding.DataBindingUtil
import androidx.lifecycle.Observer
import androidx.lifecycle.ViewModelProvider
import com.dadashow.countriesappkotlin.R
import com.dadashow.countriesappkotlin.databinding.FragmentCountryBinding
import com.dadashow.countriesappkotlin.util.downloadImageFromUrl
import com.dadashow.countriesappkotlin.util.placeholderProgressBar
import com.dadashow.countriesappkotlin.viewmodel.CountryViewModel
import kotlinx.android.synthetic.main.fragment_country.*
class CountryFragment : Fragment() {
private lateinit var viewModel : CountryViewModel
private lateinit var databinding : FragmentCountryBinding
var countryUuid =0
override fun onCreateView(
inflater: LayoutInflater, container: ViewGroup?,
savedInstanceState: Bundle?
): View? {
// Inflate the layout for this fragment
databinding=DataBindingUtil.inflate(inflater,R.layout.fragment_country,container,false)
return databinding.root
}
override fun onViewCreated(view: View, savedInstanceState: Bundle?) {
super.onViewCreated(view, savedInstanceState)
arguments?.let{
countryUuid=CountryFragmentArgs.fromBundle(it).countryUuid
}
viewModel=ViewModelProvider(this).get(CountryViewModel::class.java)
viewModel.getDataFromRoom(countryUuid)
observeLiveData()
}
fun observeLiveData(){
viewModel.country.observe(viewLifecycleOwner, Observer {country->
country?.let {
databinding.country=country
// countryName.text=it.countryName
// countryCapital.text=it.countryCapital
// countryCurrency.text=it.countryCurrency
// countryLanguage.text=it.countryLanguage
// countryRegion.text=it.countryRegion
// context?.let {
// countryImage.downloadImageFromUrl(country.imageUrl!!, placeholderProgressBar(it))
// }
}
})
}
}<file_sep>package com.dadashow.countriesappkotlin.view
import android.os.Bundle
import androidx.fragment.app.Fragment
import android.view.LayoutInflater
import android.view.View
import android.view.ViewGroup
import androidx.lifecycle.Observer
import androidx.lifecycle.ViewModel
import androidx.lifecycle.ViewModelProvider
import androidx.recyclerview.widget.LinearLayoutManager
import com.dadashow.countriesappkotlin.R
import com.dadashow.countriesappkotlin.adapter.CountryAdapter
import com.dadashow.countriesappkotlin.viewmodel.FeedViewModel
import kotlinx.android.synthetic.main.fragment_feed.*
class FeedFragment : Fragment() {
private var adapter=CountryAdapter(arrayListOf())
private lateinit var viewModel:FeedViewModel
override fun onCreateView(
inflater: LayoutInflater, container: ViewGroup?,
savedInstanceState: Bundle?
): View? {
// Inflate the layout for this fragment
return inflater.inflate(R.layout.fragment_feed, container, false)
}
override fun onViewCreated(view: View, savedInstanceState: Bundle?) {
super.onViewCreated(view, savedInstanceState)
viewModel=ViewModelProvider(this).get(FeedViewModel::class.java)
viewModel.refreshData()
countryList.layoutManager=LinearLayoutManager(context)
countryList.adapter=adapter
observeLiveData()
swipeRefreshLayout.setOnRefreshListener {
countryList.visibility=View.INVISIBLE
countryError.visibility=View.INVISIBLE
countryLoading.visibility=View.VISIBLE
viewModel.refreshDataFromAPI()
swipeRefreshLayout.isRefreshing=false
}
}
fun observeLiveData(){
viewModel.countries.observe(viewLifecycleOwner, Observer { countries->
countries?.let {
countryList.visibility=View.VISIBLE
adapter.uptadeList(ArrayList(countries))
}
})
viewModel.countryErrr.observe(viewLifecycleOwner, Observer { countryError1->
countryError1?.let {
if (it){
countryError.visibility=View.VISIBLE
countryList.visibility=View.INVISIBLE
}else{
countryError.visibility=View.INVISIBLE
}
}
})
viewModel.countryLoading.observe(viewLifecycleOwner, Observer {
it?.let {
if (it){
countryLoading.visibility=View.VISIBLE
countryList.visibility=View.INVISIBLE
}else{
countryLoading.visibility=View.INVISIBLE
}
}
})
}
}<file_sep>rootProject.name = "CountriesAppKotlin"
include ':app'
<file_sep>package com.dadashow.countriesappkotlin.viewmodel
import android.app.Application
import androidx.lifecycle.MutableLiveData
import androidx.lifecycle.ViewModel
import com.dadashow.countriesappkotlin.model.Country
import com.dadashow.countriesappkotlin.service.CountryDatabase
import kotlinx.coroutines.launch
class CountryViewModel(application: Application) : BaseViewModel(application) {
var country=MutableLiveData<Country>()
fun getDataFromRoom(uuid:Int){
launch {
val dao=CountryDatabase(getApplication()).countryDao()
country.value=dao.getCountry(uuid)
}
}
}<file_sep>package com.dadashow.countriesappkotlin.adapter
import android.view.LayoutInflater
import android.view.View
import android.view.ViewGroup
import androidx.databinding.DataBindingUtil
import androidx.navigation.Navigation
import androidx.recyclerview.widget.RecyclerView
import com.dadashow.countriesappkotlin.R
import com.dadashow.countriesappkotlin.databinding.ItemCountryBinding
import com.dadashow.countriesappkotlin.model.Country
import com.dadashow.countriesappkotlin.util.downloadImageFromUrl
import com.dadashow.countriesappkotlin.util.placeholderProgressBar
import com.dadashow.countriesappkotlin.view.FeedFragmentDirections
import kotlinx.android.synthetic.main.item_country.view.*
class CountryAdapter(var countryList:ArrayList<Country>):
RecyclerView.Adapter<CountryAdapter.CountryViewHolder>(),CountryClickListener {
class CountryViewHolder(var view:ItemCountryBinding):RecyclerView.ViewHolder(view.root){
}
override fun onCreateViewHolder(parent: ViewGroup, viewType: Int): CountryViewHolder {
var inflater=LayoutInflater.from(parent.context)
//var view=inflater.inflate(R.layout.item_country,parent,false);
val view=DataBindingUtil.inflate<ItemCountryBinding>(inflater,R.layout.item_country,parent,false)
return CountryViewHolder(view)
}
override fun onBindViewHolder(holder: CountryViewHolder, position: Int) {
holder.view.country=countryList[position]
holder.view.listener=this
// holder.view.name.text= countryList[position].countryName
// holder.view.region.text= countryList[position].countryRegion
// holder.view.setOnClickListener {
// var action=FeedFragmentDirections.actionFeedFragmentToCountryFragment(countryList[position].uuid)
// Navigation.findNavController(it).navigate(action)
// }
// holder.view.imageView.downloadImageFromUrl(countryList[position].imageUrl!!,
// placeholderProgressBar(holder.view.context))
}
override fun getItemCount(): Int {
return countryList.size
}
fun uptadeList(newcountryList:ArrayList<Country>){
countryList.clear()
countryList.addAll(newcountryList)
notifyDataSetChanged()
}
override fun onCountryClicked(view: View) {
var action=FeedFragmentDirections.actionFeedFragmentToCountryFragment(view.countryUuidTextView.text.toString().toInt())
Navigation.findNavController(view).navigate(action)
}
}<file_sep>package com.dadashow.countriesappkotlin.adapter
import android.view.View
interface CountryClickListener {
fun onCountryClicked(view: View)
} | daac6ae1f9962b60c0de076be434e7bbe2fbab0f | [
"Kotlin",
"Gradle"
] | 6 | Kotlin | Suleyman1406/CountriesAppKotlin | 7103ebf8b9f557958cc4db400fc1bc990e4eb9dd | 800ece562a71ff816dcc775af8d7884b26d2a23c |
refs/heads/master | <file_sep>import React, { Component } from "react";
import axios from "axios";
class LandingPage extends Component {
constructor(props) {
super(props);
this.state = {
posts: [],
};
}
componentDidMount() {
this.getPosts();
}
getPosts() {
axios.get("/posts").then((res) => {
if (res.data.success) {
this.setState({
posts: res.data.posts,
});
console.log(this.state.posts);
}
});
}
onDelete = (id) => {
axios.delete(`/posts/delete/${id}`).then((res) => {
alert(res.data.title + " has been deleted successfully");
this.getPosts();
});
};
filterContent(posts, searchTerm) {
const result = posts.filter(
(post) =>
post.title.toLowerCase().includes(searchTerm) ||
post.description.toLowerCase().includes(searchTerm) ||
post.postCategory.toLowerCase().includes(searchTerm)
);
this.setState({ posts: result });
}
handleTextSearch = (e) => {
const searchTerm = e.currentTarget.value;
axios.get("/posts").then((res) => {
if (res.data.success) {
this.filterContent(res.data.posts, searchTerm);
}
});
};
render() {
return (
<div className="container">
<div className="row">
<div className="col-lg-9 mt-2 mb-2">
<h4>All Posts</h4>
</div>
<div className="col-lg-3 mt-2 mb-2">
<input
className="form-control"
type="search"
placeholder="Search"
name="searchTerm"
onChange={this.handleTextSearch}
></input>
</div>
</div>
<table class="table">
<thead>
<tr>
<th scope="col">#</th>
<th scope="col">TITLE</th>
<th scope="col">DESCRIPTION</th>
<th scope="col">CATEGORY</th>
<th scope="col">ACTIONS</th>
</tr>
</thead>
<tbody>
{this.state.posts.map((post, index) => (
<tr>
<th scope="row">{index}</th>
<td>
<a href={`/posts/${post._id}`}>{post.title}</a>
</td>
<td dangerouslySetInnerHTML={{ __html: post.description }}></td>
<td>{post.postCategory}</td>
<td>
<a className="btn btn-warning" href={`/edit/${post._id}`}>
<i className="fas fa-edit"></i> EDIT
</a>
<a
className="btn btn-danger"
href="#"
onClick={() => this.onDelete(post._id)}
>
<i className="far fa-trash-alt"></i> DELETE
</a>
</td>
</tr>
))}
</tbody>
</table>
<button className="btn btn-dark text-white">
<a href="/add">Add New Post</a>
</button>
</div>
);
}
}
export default LandingPage;
| 9258054b634d95b902ef1ef7e04066ac16d958a9 | [
"JavaScript"
] | 1 | JavaScript | niharika1723/mern-crud-app | fdbd0085a421c55b696760509efd32283a0eae75 | 0ddbd82de1de6ddec3cf873c8e10e5c6e64d15de |
refs/heads/master | <file_sep>use fixedbitset::FixedBitSet;
use std::fmt::Debug;
use super::{LinkItem, LinkIter, Network, Node, NodeIndex, NodeType};
pub struct CycleDetector<
'a,
N: NodeType + 'a,
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
> {
nodes: &'a [Node<N, EXTID>],
links: &'a [LinkItem<L, EXTID>],
nodes_to_visit: Vec<usize>,
seen_nodes: FixedBitSet,
dirty: bool,
}
impl<
'a,
N: NodeType + 'a,
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
> CycleDetector<'a, N, L, EXTID> {
pub fn new(network: &'a Network<N, L, EXTID>) -> CycleDetector<'a, N, L, EXTID> {
CycleDetector {
nodes: &network.nodes,
links: &network.links,
nodes_to_visit: Vec::new(),
seen_nodes: FixedBitSet::with_capacity(network.nodes.len()),
dirty: false,
}
}
// The algorithm used in `Network.link_would_cycle` and
// `Network.find_random_unconnected_link_no_cycle`. This is mostly extracted to avoid
// repetetive memory allocations in `find_random_unconnected_link_no_cycle`.
pub fn link_would_cycle(
&mut self,
source_node_idx: NodeIndex,
target_node_idx: NodeIndex,
) -> bool {
let path_from = target_node_idx.index();
let path_to = source_node_idx.index();
assert!(path_from != path_to);
let nodes = self.nodes;
let nodes_to_visit = &mut self.nodes_to_visit;
let seen_nodes = &mut self.seen_nodes;
if self.dirty {
nodes_to_visit.clear();
seen_nodes.clear();
}
self.dirty = true;
// We start at the from the target_node and iterate all paths from there.
// If we hit the source node, the addition of this link would lead towards
// a cycle. Otherwise not.
nodes_to_visit.push(path_from);
seen_nodes.insert(path_from);
while let Some(visit_node) = nodes_to_visit.pop() {
for (_, out_link) in LinkIter::new(nodes[visit_node].links.head, self.links) {
let next_node = out_link.target_node_idx.index();
if !seen_nodes.contains(next_node) {
if next_node == path_to {
// We found a path to `path_to`. We have found a cycle.
return true;
}
seen_nodes.insert(next_node);
nodes_to_visit.push(next_node)
}
}
}
// We haven't found a cycle.
return false;
}
}
<file_sep># acyclic-network-rs
Construction and representation of acyclic networks (in Rust)
<file_sep>extern crate fixedbitset;
extern crate rand;
mod cycle_detector;
use cycle_detector::CycleDetector;
use fixedbitset::FixedBitSet;
use rand::Rng;
use std::fmt::Debug;
pub trait NodeType: Clone + Debug + Send + Sized + PartialEq + Eq {
/// Whether or not the node allows incoming connections
fn accept_incoming_links(&self) -> bool;
/// Whether or not the node allows outgoing connections
fn accept_outgoing_links(&self) -> bool;
}
/// Every node or link contains an external id. This id is
/// never modified by this library.
#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
pub struct ExternalId(pub usize);
/// Newtype wrapping a node index. The node index is
/// used as an internal index into the node array.
/// It can become unstable in case of removal of nodes.
#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
pub struct NodeIndex(usize);
/// Newtype wrapping a link index.
#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
pub struct LinkIndex(usize);
impl NodeIndex {
#[inline(always)]
pub fn index(&self) -> usize {
self.0
}
pub fn new(index: usize) -> Self {
NodeIndex(index)
}
}
impl LinkIndex {
#[inline(always)]
pub fn index(&self) -> usize {
self.0
}
}
// Wraps a Link for use in a double linked list
#[derive(Clone, Debug)]
struct LinkItem<L, EXTID>
where
L: Copy + Debug + Send + Sized,
EXTID: Copy + Debug + Send + Sized + Ord,
{
prev: Option<LinkIndex>,
next: Option<LinkIndex>,
link: Link<L, EXTID>,
}
pub struct LinkIter<'a, L, EXTID>
where
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
{
next_link_idx: Option<LinkIndex>,
link_array: &'a [LinkItem<L, EXTID>],
}
impl<'a, L, EXTID> LinkIter<'a, L, EXTID>
where
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
{
fn new(link_idx_opt: Option<LinkIndex>, link_array: &'a [LinkItem<L, EXTID>]) -> Self {
LinkIter {
next_link_idx: link_idx_opt,
link_array: link_array,
}
}
}
impl<'a, L, EXTID> Iterator for LinkIter<'a, L, EXTID>
where
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
{
type Item = (LinkIndex, &'a Link<L, EXTID>);
fn next(&mut self) -> Option<Self::Item> {
match self.next_link_idx {
Some(idx) => {
let item = &self.link_array[idx.index()];
self.next_link_idx = item.next;
return Some((idx, &item.link));
}
None => {
return None;
}
}
}
}
pub struct LinkRefIter<'a, N, L, EXTID>
where
N: NodeType + 'a,
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
{
next_link_idx: Option<LinkIndex>,
network: &'a Network<N, L, EXTID>,
}
/// A LinkRefItem includes a pointer to the network,
/// as such, it is read only.
pub struct LinkRefItem<'a, N, L, EXTID>
where
N: NodeType + 'a,
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
{
link: &'a Link<L, EXTID>,
network: &'a Network<N, L, EXTID>,
}
impl<'a, N, L, EXTID> LinkRefItem<'a, N, L, EXTID>
where
N: NodeType + 'a,
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
{
pub fn link(&self) -> &Link<L, EXTID> {
self.link
}
pub fn network(&self) -> &Network<N, L, EXTID> {
self.network
}
pub fn external_link_id(&self) -> EXTID {
self.link.external_link_id()
}
pub fn source_node(&self) -> &Node<N, EXTID> {
self.network.node(self.link.source_node_idx)
}
pub fn target_node(&self) -> &Node<N, EXTID> {
self.network.node(self.link.target_node_idx)
}
pub fn external_source_node_id(&self) -> EXTID {
self.source_node().external_node_id()
}
pub fn external_target_node_id(&self) -> EXTID {
self.target_node().external_node_id()
}
}
impl<'a, N, L, EXTID> LinkRefIter<'a, N, L, EXTID>
where
N: NodeType + 'a,
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
{
fn new(link_idx_opt: Option<LinkIndex>, network: &'a Network<N, L, EXTID>) -> Self {
LinkRefIter {
next_link_idx: link_idx_opt,
network: network,
}
}
}
impl<'a, N, L, EXTID> Iterator for LinkRefIter<'a, N, L, EXTID>
where
N: NodeType + 'a,
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
{
type Item = (LinkRefItem<'a, N, L, EXTID>);
fn next(&mut self) -> Option<Self::Item> {
match self.next_link_idx {
Some(idx) => {
let item = &self.network.links[idx.index()];
self.next_link_idx = item.next;
return Some(LinkRefItem {
link: &item.link,
network: &self.network,
});
}
None => {
return None;
}
}
}
}
#[derive(Clone, Debug)]
pub struct Link<L, EXTID>
where
L: Copy + Debug + Send + Sized,
EXTID: Copy + Debug + Send + Sized + Ord,
{
source_node_idx: NodeIndex,
target_node_idx: NodeIndex,
weight: L,
external_link_id: EXTID,
// the activeness of a link has no influence on the
// cycle detection.
active: bool,
}
impl<L, EXTID> Link<L, EXTID>
where
L: Copy + Debug + Send + Sized,
EXTID: Copy + Debug + Send + Sized + Ord,
{
#[inline(always)]
pub fn external_link_id(&self) -> EXTID {
self.external_link_id
}
#[inline(always)]
pub fn source_node_index(&self) -> NodeIndex {
self.source_node_idx
}
#[inline(always)]
pub fn target_node_index(&self) -> NodeIndex {
self.target_node_idx
}
#[inline(always)]
pub fn is_active(&self) -> bool {
self.active
}
#[inline(always)]
pub fn weight(&self) -> L {
self.weight
}
#[inline(always)]
pub fn set_weight(&mut self, new_weight: L) {
self.weight = new_weight;
}
}
#[derive(Clone, Debug)]
struct List {
head: Option<LinkIndex>,
tail: Option<LinkIndex>,
}
impl List {
fn empty() -> Self {
List {
head: None,
tail: None,
}
}
fn iter<'a, L, EXTID>(&self, link_array: &'a [LinkItem<L, EXTID>]) -> LinkIter<'a, L, EXTID>
where
L: Copy + Debug + Send + Sized + 'a,
EXTID: Copy + Debug + Send + Sized + Ord + 'a,
{
LinkIter::new(self.head, link_array)
}
}
#[derive(Clone, Debug)]
pub struct Node<N: NodeType, EXTID: Copy + Debug + Send + Sized + Ord = ExternalId> {
node_type: N,
external_node_id: EXTID,
links: List,
// in and out degree counts disabled links!
in_degree: u32,
out_degree: u32,
}
impl<N: NodeType, EXTID: Copy + Debug + Send + Sized + Ord> Node<N, EXTID> {
pub fn node_type(&self) -> &N {
&self.node_type
}
pub fn set_node_type(&mut self, node_type: N) {
self.node_type = node_type;
}
pub fn external_node_id(&self) -> EXTID {
self.external_node_id
}
pub fn degree(&self) -> usize {
self.in_degree as usize + self.out_degree as usize
}
pub fn in_degree(&self) -> u32 {
self.in_degree
}
pub fn out_degree(&self) -> u32 {
self.out_degree
}
pub fn in_out_degree(&self) -> (u32, u32) {
(self.in_degree, self.out_degree)
}
}
/// A directed, acylic network.
#[derive(Clone, Debug)]
pub struct Network<
N: NodeType,
L: Copy + Debug + Send + Sized,
EXTID: Copy + Debug + Send + Sized + Ord = ExternalId,
> {
nodes: Vec<Node<N, EXTID>>,
links: Vec<LinkItem<L, EXTID>>, // XXX: Rename to link_items
link_count: usize,
active_link_count: usize,
}
impl<N: NodeType, L: Copy + Debug + Send + Sized, EXTID: Copy + Debug + Send + Sized + Ord>
Network<N, L, EXTID> {
pub fn new() -> Network<N, L, EXTID> {
Network {
nodes: Vec::new(),
links: Vec::new(),
link_count: 0,
active_link_count: 0,
}
}
#[inline]
pub fn node_count(&self) -> usize {
self.nodes.len()
}
#[inline]
pub fn link_count(&self) -> usize {
self.link_count
}
#[inline(always)]
pub fn node(&self, node_idx: NodeIndex) -> &Node<N, EXTID> {
&self.nodes[node_idx.index()]
}
#[inline(always)]
pub fn node_mut(&mut self, node_idx: NodeIndex) -> &mut Node<N, EXTID> {
&mut self.nodes[node_idx.index()]
}
#[inline(always)]
fn link_item(&self, link_idx: LinkIndex) -> &LinkItem<L, EXTID> {
&self.links[link_idx.index()]
}
#[inline(always)]
pub fn link(&self, link_idx: LinkIndex) -> &Link<L, EXTID> {
&self.link_item(link_idx).link
}
#[inline(always)]
pub fn link_mut(&mut self, link_idx: LinkIndex) -> &mut Link<L, EXTID> {
&mut (self.links[link_idx.index()].link)
}
#[inline(always)]
pub fn nodes(&self) -> &[Node<N, EXTID>] {
&self.nodes
}
#[inline]
pub fn each_node_with_index<F>(&self, mut f: F)
where
F: FnMut(&Node<N, EXTID>, NodeIndex),
{
for (i, node) in self.nodes.iter().enumerate() {
f(node, NodeIndex(i));
}
}
#[inline]
pub fn link_iter_for_node<'a>(&'a self, node_idx: NodeIndex) -> LinkIter<'a, L, EXTID> {
self.node(node_idx).links.iter(&self.links)
}
#[inline]
pub fn link_ref_iter_for_node<'a>(
&'a self,
node_idx: NodeIndex,
) -> LinkRefIter<'a, N, L, EXTID> {
LinkRefIter::new(self.node(node_idx).links.head, self)
}
#[inline]
pub fn each_active_forward_link_of_node<F>(&self, node_idx: NodeIndex, mut f: F)
where
F: FnMut(NodeIndex, L),
{
for (_, link) in self.link_iter_for_node(node_idx) {
if link.active {
f(link.target_node_idx, link.weight);
}
}
}
#[inline]
pub fn each_link_ref<F>(&self, mut f: F)
where
F: FnMut(LinkRefItem<N, L, EXTID>),
{
for link_item in &self.links[..] {
f(LinkRefItem {
link: &&link_item.link,
network: self,
});
}
}
#[inline]
pub fn each_link_mut<F>(&mut self, mut f: F)
where
F: FnMut(&mut Link<L, EXTID>),
{
for link_item in &mut self.links[..] {
f(&mut link_item.link);
}
}
fn inactive_link_count(&self) -> usize {
assert!(self.link_count >= self.active_link_count);
self.link_count - self.active_link_count
}
/// # Complexity
///
/// O(number of links)
pub fn random_inactive_link_index<R: Rng>(&self, rng: &mut R) -> Option<LinkIndex> {
let n = self.inactive_link_count();
assert!(n <= self.link_count);
if n > 0 {
let mut nth_link: usize = rng.gen_range(0, n);
for node in self.nodes.iter() {
for (link_idx, link) in node.links.iter(&self.links) {
if !link.is_active() {
if nth_link > 0 {
nth_link -= 1;
} else {
return Some(link_idx);
}
}
}
}
}
return None;
}
/// # Complexity
///
/// O(number of links)
pub fn random_active_link_index<R: Rng>(&self, rng: &mut R) -> Option<LinkIndex> {
let n = self.active_link_count;
assert!(n <= self.link_count);
if n > 0 {
let mut nth_link: usize = rng.gen_range(0, n);
for node in self.nodes.iter() {
for (link_idx, link) in node.links.iter(&self.links) {
if link.is_active() {
if nth_link > 0 {
nth_link -= 1;
} else {
return Some(link_idx);
}
}
}
}
}
return None;
}
/// # Complexity
///
/// O(1)
pub fn random_link_index<R: Rng>(&self, rng: &mut R) -> Option<LinkIndex> {
let n = self.link_count;
if n > 0 {
let link_idx: usize = rng.gen_range(0, n);
return Some(LinkIndex(link_idx));
}
return None;
}
/// Removes all outgoing links of node `node_idx`.
///
/// XXX: This can be optimized.
///
/// # Complexity
///
/// O(k), where `k` is the number of edges of `node_idx`.
pub fn remove_all_outgoing_links_of_node(&mut self, node_idx: NodeIndex) {
let n = self.node(node_idx).out_degree as usize;
for _ in 0..n {
let link_index = self.node(node_idx).links.head.unwrap();
self.remove_link_at(link_index);
}
assert!(self.node(node_idx).links.head.is_none());
assert!(self.node(node_idx).links.tail.is_none());
assert!(self.node(node_idx).out_degree == 0);
}
/// Removes all incoming links to node `node_idx`.
///
/// XXX: This can be optimized.
pub fn remove_all_incoming_links_of_node(&mut self, node_idx: NodeIndex) {
let n = self.node(node_idx).in_degree as usize;
if n == 0 {
// If a node does not have any incoming links, we are done!
return;
}
// for each node other than `node_idx` try to delete a link to node_idx.
for src in 0..self.node_count() {
let src_idx = NodeIndex(src);
if src_idx != node_idx {
if let Some(link_index) = self.find_link_index_exact(src_idx, node_idx) {
self.remove_link_at(link_index);
}
}
}
assert!(self.node(node_idx).in_degree == 0);
}
/// Removes all links to and from node `node_idx`.
pub fn remove_all_inout_links_of_node(&mut self, node_idx: NodeIndex) {
self.remove_all_outgoing_links_of_node(node_idx);
self.remove_all_incoming_links_of_node(node_idx);
}
/// Remove the node with index `node_idx` including
/// all incoming and outgoing links.
///
/// Moves the last node in the nodes array into the empty
/// place and rewires all links. As such, this is a quite
/// heavy operation!
///
/// # Danger!
///
/// The external NodeIndex of the last node is changed!
///
/// # Complexity
///
/// Worst case O(e), where `e` is the total number of edges in the graph.
///
pub fn remove_node(&mut self, node_idx: NodeIndex) {
let node_count = self.nodes.len();
assert!(node_idx.index() < node_count);
assert!(node_count > 0);
self.remove_all_inout_links_of_node(node_idx);
let last_idx = NodeIndex(node_count - 1);
if node_idx == last_idx {
// the node is the last! simply pop it off from the end of the array!
let _node = self.nodes.pop();
} else {
// the node is not the last. move the node at `last_idx` into our position.
let _node = self.nodes.swap_remove(node_idx.index());
// then substitute `last_idx` by `node_idx` in every edge.
for link_item in self.links.iter_mut() {
if link_item.link.target_node_idx == last_idx {
link_item.link.target_node_idx = node_idx;
}
if link_item.link.source_node_idx == last_idx {
link_item.link.source_node_idx = node_idx;
}
}
}
assert!(self.node_count() == node_count - 1);
}
/// Adds a new node to the network with type `node_type` and the associated
/// id `external_node_id`. The `external_node_id` is stored in the node and
/// can be retrieved later on.
///
pub fn add_node(&mut self, node_type: N, external_node_id: EXTID) -> NodeIndex {
let node_idx = NodeIndex(self.nodes.len());
self.nodes.push(Node {
node_type: node_type,
external_node_id: external_node_id,
links: List::empty(),
in_degree: 0,
out_degree: 0,
});
return node_idx;
}
/// Returns a random link between two unconnected nodes, which would not
/// introduce
/// a cycle. Return None is no such exists.
pub fn find_random_unconnected_link_no_cycle<R: Rng>(
&self,
rng: &mut R,
) -> Option<(NodeIndex, NodeIndex)> {
let n = self.nodes.len();
let idx = &|i, j| i * n + j;
let mut adj_matrix = FixedBitSet::with_capacity(n * n);
// Build up a binary, undirected adjacency matrix of the graph.
// Every unset bit in the adj_matrix will be a potential link.
for (i, node) in self.nodes.iter().enumerate() {
for (_, link) in node.links.iter(&self.links) {
let j = link.target_node_idx.index();
adj_matrix.insert(idx(i, j));
// include the link of reverse direction, because this would
// create a cycle anyway.
adj_matrix.insert(idx(j, i));
}
}
let adj_matrix = adj_matrix; // make immutable
// We now test all potential links of every node in the graph, if it would
// introduce a cycle. For that, we shuffle the node indices (`node_order`).
// in random order.
// XXX: Remove deleted nodes
let mut node_order: Vec<_> = (0..n).into_iter().collect();
let mut edge_order: Vec<_> = (0..n).into_iter().collect();
rng.shuffle(&mut node_order);
let node_order = node_order; // make immutable
let mut cycler = CycleDetector::new(self);
for &i in &node_order {
rng.shuffle(&mut edge_order);
for &j in &edge_order {
if i != j && !adj_matrix.contains(idx(i, j)) {
// The link (i, j) neither is reflexive, nor exists.
let ni = NodeIndex(i);
let nj = NodeIndex(j);
if self.valid_link(ni, nj).is_ok() && !cycler.link_would_cycle(ni, nj) {
// If the link is valid and does not create a cycle, we are done!
return Some((ni, nj));
}
}
}
}
return None;
}
/// Returns true if the introduction of this directed link would lead towards a
/// cycle.
pub fn link_would_cycle(&self, source_node_idx: NodeIndex, target_node_idx: NodeIndex) -> bool {
if source_node_idx == target_node_idx {
return true;
}
CycleDetector::new(self).link_would_cycle(source_node_idx, target_node_idx)
}
// Check if the link is valid. Doesn't check for cycles.
pub fn valid_link(
&self,
source_node_idx: NodeIndex,
target_node_idx: NodeIndex,
) -> Result<(), &'static str> {
if source_node_idx == target_node_idx {
return Err("Loops are not allowed");
}
if !self.nodes[source_node_idx.index()]
.node_type
.accept_outgoing_links()
{
return Err("Node does not allow outgoing links");
}
if !self.nodes[target_node_idx.index()]
.node_type
.accept_incoming_links()
{
return Err("Node does not allow incoming links");
}
Ok(())
}
fn allocate_link_item(&mut self, link_item: LinkItem<L, EXTID>) -> LinkIndex {
let new_link_idx = LinkIndex(self.links.len());
self.links.push(link_item);
return new_link_idx;
}
pub fn disable_link_index(&mut self, link_idx: LinkIndex) -> bool {
if self.link(link_idx).is_active() {
self.active_link_count -= 1;
self.link_mut(link_idx).active = false;
return true;
} else {
return false;
}
}
pub fn enable_link_index(&mut self, link_idx: LinkIndex) -> bool {
if !self.link(link_idx).is_active() {
self.active_link_count += 1;
self.link_mut(link_idx).active = true;
return true;
} else {
return false;
}
}
pub fn disable_link(&mut self, source_node_idx: NodeIndex, target_node_idx: NodeIndex) -> bool {
if let Some(link_idx) = self.find_link_index_exact(source_node_idx, target_node_idx) {
return self.disable_link_index(link_idx);
}
return false;
}
pub fn enable_link(&mut self, source_node_idx: NodeIndex, target_node_idx: NodeIndex) -> bool {
if let Some(link_idx) = self.find_link_index_exact(source_node_idx, target_node_idx) {
return self.enable_link_index(link_idx);
}
return false;
}
pub fn first_link_of_node(&self, node_idx: NodeIndex) -> Option<&Link<L, EXTID>> {
self.node(node_idx)
.links
.head
.map(|link_idx| self.link(link_idx))
}
pub fn last_link_of_node(&self, node_idx: NodeIndex) -> Option<&Link<L, EXTID>> {
self.node(node_idx)
.links
.tail
.map(|link_idx| self.link(link_idx))
}
fn append(&mut self, node_idx: NodeIndex, link: Link<L, EXTID>) -> LinkIndex {
match (
self.node(node_idx).links.head,
self.node(node_idx).links.tail,
) {
(None, None) => {
// append onto empty list
let new_link_idx = self.allocate_link_item(LinkItem {
link: link,
prev: None,
next: None,
});
self.node_mut(node_idx).links = List {
head: Some(new_link_idx),
tail: Some(new_link_idx),
};
return new_link_idx;
}
(Some(_), Some(tail)) => {
let new_link_idx = self.allocate_link_item(LinkItem {
link: link,
prev: Some(tail),
next: None,
});
assert!(self.links[tail.index()].next == None);
self.links[tail.index()].next = Some(new_link_idx);
self.node_mut(node_idx).links.tail = Some(new_link_idx);
return new_link_idx;
}
_ => panic!(),
}
}
fn prepend(&mut self, node_idx: NodeIndex, link: Link<L, EXTID>) -> LinkIndex {
match (
self.node(node_idx).links.head,
self.node(node_idx).links.tail,
) {
(None, None) => {
// prepend to empty list. same as append
let new_link_idx = self.allocate_link_item(LinkItem {
link: link,
prev: None,
next: None,
});
self.node_mut(node_idx).links = List {
head: Some(new_link_idx),
tail: Some(new_link_idx),
};
return new_link_idx;
}
(Some(head), Some(_tail)) => {
let new_link_idx = self.allocate_link_item(LinkItem {
link: link,
prev: None,
next: Some(head),
});
assert!(self.links[head.index()].prev == None);
self.links[head.index()].prev = Some(new_link_idx);
self.node_mut(node_idx).links.head = Some(new_link_idx);
return new_link_idx;
}
_ => panic!(),
}
}
pub fn add_link(
&mut self,
source_node_idx: NodeIndex,
target_node_idx: NodeIndex,
weight: L,
external_link_id: EXTID,
) -> LinkIndex {
self.add_link_with_active(
source_node_idx,
target_node_idx,
weight,
external_link_id,
true,
)
}
// This will destroy the ordering relation of links.
// Do not mix with `add_link` or `add_link_with_active`.
pub fn add_link_unordered(
&mut self,
source_node_idx: NodeIndex,
target_node_idx: NodeIndex,
weight: L,
external_link_id: EXTID,
) -> LinkIndex {
if let Err(err) = self.valid_link(source_node_idx, target_node_idx) {
panic!(err);
}
self.link_count += 1;
self.active_link_count += 1;
self.node_mut(source_node_idx).out_degree += 1;
self.node_mut(target_node_idx).in_degree += 1;
let link = Link {
source_node_idx: source_node_idx,
target_node_idx: target_node_idx,
external_link_id: external_link_id,
weight: weight,
active: true,
};
return self.append(source_node_idx, link);
}
// Note: Doesn't check for cycles (except in the simple reflexive case).
// Note that we keep the list of links sorted according to it's
// external_link_id.
// XXX: Need test cases.
pub fn add_link_with_active(
&mut self,
source_node_idx: NodeIndex,
target_node_idx: NodeIndex,
weight: L,
external_link_id: EXTID,
active: bool,
) -> LinkIndex {
if let Err(err) = self.valid_link(source_node_idx, target_node_idx) {
panic!(err);
}
self.link_count += 1;
if active {
self.active_link_count += 1;
}
self.node_mut(source_node_idx).out_degree += 1;
self.node_mut(target_node_idx).in_degree += 1;
let link = Link {
source_node_idx: source_node_idx,
target_node_idx: target_node_idx,
external_link_id: external_link_id,
weight: weight,
active: active,
};
match self.find_link_index_insert_before(source_node_idx, target_node_idx, external_link_id)
{
None => {
if let Some(tail) = self.node(source_node_idx).links.tail {
// check if last element is equal
if self.link(tail).target_node_idx == target_node_idx {
assert!(self.link(tail).external_link_id == external_link_id);
panic!("Duplicate link");
}
}
// append at end.
return self.append(source_node_idx, link);
}
Some(idx) => {
match self.link_item(idx).prev {
None => {
return self.prepend(source_node_idx, link);
}
Some(insert_after) => {
// check if previous element is not equal
if self.link(insert_after).target_node_idx == target_node_idx {
assert!(self.link(insert_after).external_link_id == external_link_id);
panic!("Duplicate link");
}
let new_link_idx = self.allocate_link_item(LinkItem {
link: link,
prev: Some(insert_after),
next: Some(idx),
});
self.links[insert_after.index()].next = Some(new_link_idx);
self.links[idx.index()].prev = Some(new_link_idx);
return new_link_idx;
}
}
}
}
}
// Returns the index of the first element whoose external link id >
// `external_link_id`.
fn find_link_index_insert_before(
&self,
source_node_idx: NodeIndex,
_target_node_idx: NodeIndex,
external_link_id: EXTID,
) -> Option<LinkIndex> {
// the links are sorted according to their external link id.
let mut link_iter = self.link_iter_for_node(source_node_idx);
for (idx, link) in &mut link_iter {
if link.external_link_id() > external_link_id {
return Some(idx);
}
}
return None;
}
pub fn has_link(&self, source_node_idx: NodeIndex, target_node_idx: NodeIndex) -> bool {
self.find_link_index_exact(source_node_idx, target_node_idx)
.is_some()
}
fn find_link_index_exact(
&self,
source_node_idx: NodeIndex,
target_node_idx: NodeIndex,
) -> Option<LinkIndex> {
for (link_idx, link) in self.link_iter_for_node(source_node_idx) {
// We found the node we are looking for.
if link.target_node_idx == target_node_idx {
return Some(link_idx);
}
}
return None;
}
/// Remove the link at index `link_index`.
pub fn remove_link_at(&mut self, link_index: LinkIndex) {
let found_idx = link_index;
let source_node_idx = self.link(found_idx).source_node_idx;
let target_node_idx = self.link(found_idx).target_node_idx;
if self.link(found_idx).is_active() {
self.active_link_count -= 1;
}
// remove item from chain
match (
self.link_item(found_idx).prev,
self.link_item(found_idx).next,
) {
(None, None) => {
// Item is the only element of the list.
assert!(self.node(source_node_idx).links.head == Some(found_idx));
assert!(self.node(source_node_idx).links.tail == Some(found_idx));
self.node_mut(source_node_idx).links = List::empty();
}
(None, Some(next)) => {
// Item is the first element in the list, followed by some other element.
assert!(self.links[next.index()].prev == Some(found_idx));
assert!(self.node(source_node_idx).links.head == Some(found_idx));
assert!(self.node(source_node_idx).links.tail != Some(found_idx));
self.node_mut(source_node_idx).links.head = Some(next);
self.links[next.index()].prev = None;
}
(Some(prev), None) => {
// Item is the last element of the list, preceded by some other element.
assert!(self.links[prev.index()].next == Some(found_idx));
assert!(self.node(source_node_idx).links.tail == Some(found_idx));
assert!(self.node(source_node_idx).links.head != Some(found_idx));
// make the previous element the new tail
self.node_mut(source_node_idx).links.tail = Some(prev);
self.links[prev.index()].next = None;
}
(Some(prev), Some(next)) => {
// Item is somewhere in the middle of the list. We don't have to
// update the head or tail pointers.
assert!(self.node(source_node_idx).links.head != Some(found_idx));
assert!(self.node(source_node_idx).links.tail != Some(found_idx));
assert!(self.links[prev.index()].next == Some(found_idx));
assert!(self.links[next.index()].prev == Some(found_idx));
self.links[prev.index()].next = Some(next);
self.links[next.index()].prev = Some(prev);
}
}
self.links[found_idx.index()].next = None;
self.links[found_idx.index()].prev = None;
// swap the item with the last one.
let old_idx = LinkIndex(self.links.len() - 1);
if found_idx == old_idx {
// if we are the last element, we can just pop it
let old = self.links.pop().unwrap();
debug_assert!(old.link.source_node_idx == source_node_idx);
debug_assert!(old.link.target_node_idx == target_node_idx);
} else {
let old = self.links.swap_remove(found_idx.index());
debug_assert!(old.link.source_node_idx == source_node_idx);
debug_assert!(old.link.target_node_idx == target_node_idx);
// We have to change the linking of the newly at position `found_idx` placed
// element.
let new_idx = found_idx;
// change the next pointer of the previous element
let new_source_node_idx = self.link(new_idx).source_node_idx;
match (self.link_item(new_idx).prev, self.link_item(new_idx).next) {
(None, None) => {
// the moved element was the only element in the list.
assert!(self.node(new_source_node_idx).links.head == Some(old_idx));
assert!(self.node(new_source_node_idx).links.tail == Some(old_idx));
// Update both head and tail to the new element index.
self.node_mut(new_source_node_idx).links = List {
head: Some(new_idx),
tail: Some(new_idx),
};
}
(None, Some(next)) => {
// Item is the first element in the list, followed by some other element.
assert!(self.links[next.index()].prev == Some(old_idx));
assert!(self.node(new_source_node_idx).links.head == Some(old_idx));
assert!(self.node(new_source_node_idx).links.tail != Some(old_idx));
self.node_mut(new_source_node_idx).links.head = Some(new_idx);
self.links[next.index()].prev = Some(new_idx);
}
(Some(prev), None) => {
// Item is the last element of the list, preceded by some other element.
assert!(self.links[prev.index()].next == Some(old_idx));
assert!(self.node(new_source_node_idx).links.tail == Some(old_idx));
assert!(self.node(new_source_node_idx).links.head != Some(old_idx));
// make the previous element the new tail
self.node_mut(new_source_node_idx).links.tail = Some(new_idx);
self.links[prev.index()].next = Some(new_idx);
}
(Some(prev), Some(next)) => {
// Item is somewhere in the middle of the list. We don't have to
// update the head or tail pointers.
assert!(self.node(new_source_node_idx).links.head != Some(old_idx));
assert!(self.node(new_source_node_idx).links.tail != Some(old_idx));
assert!(self.links[prev.index()].next == Some(old_idx));
assert!(self.links[next.index()].prev == Some(old_idx));
self.links[prev.index()].next = Some(new_idx);
self.links[next.index()].prev = Some(new_idx);
}
}
}
assert!(self.node(source_node_idx).out_degree > 0);
assert!(self.node(target_node_idx).in_degree > 0);
self.node_mut(source_node_idx).out_degree -= 1;
self.node_mut(target_node_idx).in_degree -= 1;
self.link_count -= 1;
}
/// Remove the first link that matches `source_node_idx` and `target_node_idx`.
/// XXX
pub fn remove_link(&mut self, source_node_idx: NodeIndex, target_node_idx: NodeIndex) -> bool {
if let Some(found_idx) = self.find_link_index_exact(source_node_idx, target_node_idx) {
debug_assert!(self.link(found_idx).source_node_idx == source_node_idx);
debug_assert!(self.link(found_idx).target_node_idx == target_node_idx);
self.remove_link_at(found_idx);
return true;
} else {
// link was not found
return false;
}
}
}
#[cfg(test)]
mod tests {
use rand;
use super::{ExternalId, Network, NodeIndex, NodeType};
#[derive(Clone, Debug, PartialEq, Eq)]
enum NodeT {
Input,
Hidden,
Output,
}
impl NodeType for NodeT {
fn accept_incoming_links(&self) -> bool {
match *self {
NodeT::Input => false,
_ => true,
}
}
fn accept_outgoing_links(&self) -> bool {
match *self {
NodeT::Output => false,
_ => true,
}
}
}
#[test]
fn test_cycle() {
let mut g = Network::new();
let i1 = g.add_node(NodeT::Input, ExternalId(1));
let h1 = g.add_node(NodeT::Hidden, ExternalId(2));
let h2 = g.add_node(NodeT::Hidden, ExternalId(3));
assert_eq!(true, g.valid_link(i1, i1).is_err());
assert_eq!(true, g.valid_link(h1, h1).is_err());
assert_eq!(true, g.valid_link(h1, i1).is_err());
assert_eq!(Ok(()), g.valid_link(i1, h1));
assert_eq!(Ok(()), g.valid_link(i1, h2));
assert_eq!(Ok(()), g.valid_link(h1, h2));
assert_eq!((0, 0), g.node(i1).in_out_degree());
assert_eq!((0, 0), g.node(h1).in_out_degree());
assert_eq!((0, 0), g.node(h2).in_out_degree());
g.add_link(i1, h1, 0.0, ExternalId(1));
assert_eq!((0, 1), g.node(i1).in_out_degree());
assert_eq!((1, 0), g.node(h1).in_out_degree());
assert_eq!((0, 0), g.node(h2).in_out_degree());
assert_eq!(true, g.link_would_cycle(h1, i1));
assert_eq!(false, g.link_would_cycle(i1, h1));
assert_eq!(false, g.link_would_cycle(i1, h2));
assert_eq!(true, g.link_would_cycle(i1, i1));
assert_eq!(false, g.link_would_cycle(h1, h2));
assert_eq!(false, g.link_would_cycle(h2, h1));
assert_eq!(false, g.link_would_cycle(h2, i1));
g.add_link(h1, h2, 0.0, ExternalId(2));
assert_eq!((0, 1), g.node(i1).in_out_degree());
assert_eq!((1, 1), g.node(h1).in_out_degree());
assert_eq!((1, 0), g.node(h2).in_out_degree());
assert_eq!(true, g.link_would_cycle(h2, i1));
assert_eq!(true, g.link_would_cycle(h1, i1));
assert_eq!(true, g.link_would_cycle(h2, h1));
assert_eq!(false, g.link_would_cycle(i1, h2));
}
#[test]
fn test_find_random_unconnected_link_no_cycle() {
let mut g = Network::new();
let i1 = g.add_node(NodeT::Input, ExternalId(1));
let o1 = g.add_node(NodeT::Output, ExternalId(2));
let o2 = g.add_node(NodeT::Output, ExternalId(3));
let mut rng = rand::thread_rng();
let link = g.find_random_unconnected_link_no_cycle(&mut rng);
assert_eq!(true, link.is_some());
let l = link.unwrap();
assert!((i1, o1) == l || (i1, o2) == l);
g.add_link(i1, o2, 0.0, ExternalId(1));
let link = g.find_random_unconnected_link_no_cycle(&mut rng);
assert_eq!(true, link.is_some());
assert_eq!((i1, o1), link.unwrap());
g.add_link(i1, o1, 0.0, ExternalId(2));
let link = g.find_random_unconnected_link_no_cycle(&mut rng);
assert_eq!(false, link.is_some());
}
#[test]
fn test_remove_link() {
let mut g = Network::new();
let i1 = g.add_node(NodeT::Input, ExternalId(1));
let h1 = g.add_node(NodeT::Hidden, ExternalId(2));
let h2 = g.add_node(NodeT::Hidden, ExternalId(3));
g.add_link(i1, h1, 0.0, ExternalId(2));
g.add_link(i1, h2, 0.0, ExternalId(1));
assert_eq!(
ExternalId(1),
g.first_link_of_node(i1).unwrap().external_link_id()
);
assert_eq!(
ExternalId(2),
g.last_link_of_node(i1).unwrap().external_link_id()
);
assert_eq!(2, g.node(i1).out_degree());
assert_eq!(1, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(2, g.link_count());
assert_eq!(true, g.remove_link(i1, h1));
assert_eq!(1, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(1, g.link_count());
assert_eq!(
ExternalId(1),
g.first_link_of_node(i1).unwrap().external_link_id()
);
assert_eq!(
ExternalId(1),
g.last_link_of_node(i1).unwrap().external_link_id()
);
assert_eq!(false, g.remove_link(i1, h1));
assert_eq!(1, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(1, g.link_count());
assert_eq!(
ExternalId(1),
g.first_link_of_node(i1).unwrap().external_link_id()
);
assert_eq!(
ExternalId(1),
g.last_link_of_node(i1).unwrap().external_link_id()
);
assert_eq!(true, g.remove_link(i1, h2));
assert_eq!(0, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(0, g.node(h2).in_degree());
assert_eq!(0, g.link_count());
assert!(g.first_link_of_node(i1).is_none());
assert!(g.last_link_of_node(i1).is_none());
// XXX: test for sort order
}
#[test]
fn test_add_remove_link_unordered() {
let mut g = Network::new();
let i1 = g.add_node(NodeT::Input, ());
let h1 = g.add_node(NodeT::Hidden, ());
let h2 = g.add_node(NodeT::Hidden, ());
g.add_link_unordered(i1, h1, 0.0, ());
g.add_link_unordered(i1, h2, 0.0, ());
assert_eq!(h1, g.first_link_of_node(i1).unwrap().target_node_idx);
assert_eq!(h2, g.last_link_of_node(i1).unwrap().target_node_idx);
assert_eq!(2, g.node(i1).out_degree());
assert_eq!(1, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(2, g.link_count());
assert_eq!(true, g.remove_link(i1, h1));
assert_eq!(1, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(1, g.link_count());
assert_eq!(h2, g.first_link_of_node(i1).unwrap().target_node_idx);
assert_eq!(h2, g.last_link_of_node(i1).unwrap().target_node_idx);
assert_eq!(false, g.remove_link(i1, h1));
assert_eq!(1, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(1, g.link_count());
assert_eq!(h2, g.first_link_of_node(i1).unwrap().target_node_idx);
assert_eq!(h2, g.last_link_of_node(i1).unwrap().target_node_idx);
assert_eq!(true, g.remove_link(i1, h2));
assert_eq!(0, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(0, g.node(h2).in_degree());
assert_eq!(0, g.link_count());
assert!(g.first_link_of_node(i1).is_none());
assert!(g.last_link_of_node(i1).is_none());
}
#[test]
fn test_remove_all_outgoing_links() {
let mut g = Network::new();
let i1 = g.add_node(NodeT::Input, ());
let h1 = g.add_node(NodeT::Hidden, ());
let h2 = g.add_node(NodeT::Hidden, ());
let o1 = g.add_node(NodeT::Output, ());
g.add_link_unordered(i1, h1, 0.0, ());
g.add_link_unordered(i1, h2, 0.0, ());
g.add_link_unordered(h1, o1, 0.0, ());
g.add_link_unordered(h2, o1, 0.0, ());
assert_eq!(2, g.node(i1).out_degree());
assert_eq!(1, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(2, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(4, g.link_count());
g.remove_all_outgoing_links_of_node(i1);
assert!(g.first_link_of_node(i1).is_none());
assert!(g.last_link_of_node(i1).is_none());
assert_eq!(0, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(0, g.node(h2).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(2, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(2, g.link_count());
}
#[test]
fn test_remove_all_incoming_links() {
let mut g = Network::new();
let i1 = g.add_node(NodeT::Input, ());
let h1 = g.add_node(NodeT::Hidden, ());
let h2 = g.add_node(NodeT::Hidden, ());
let o1 = g.add_node(NodeT::Output, ());
g.add_link_unordered(i1, h1, 0.0, ());
g.add_link_unordered(i1, h2, 0.0, ());
g.add_link_unordered(h1, o1, 0.0, ());
g.add_link_unordered(h2, o1, 0.0, ());
assert_eq!(2, g.node(i1).out_degree());
assert_eq!(1, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(2, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(4, g.link_count());
assert!(g.first_link_of_node(i1).is_some());
assert!(g.last_link_of_node(i1).is_some());
g.remove_all_incoming_links_of_node(i1);
assert_eq!(2, g.node(i1).out_degree());
assert_eq!(1, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(2, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(4, g.link_count());
assert!(g.first_link_of_node(i1).is_some());
assert!(g.last_link_of_node(i1).is_some());
g.remove_all_incoming_links_of_node(h1);
assert_eq!(1, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(2, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(3, g.link_count());
assert!(g.first_link_of_node(i1).is_some());
assert!(g.last_link_of_node(i1).is_some());
g.remove_all_incoming_links_of_node(h2);
assert_eq!(0, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(0, g.node(h2).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(2, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(2, g.link_count());
assert!(g.first_link_of_node(i1).is_none());
assert!(g.last_link_of_node(i1).is_none());
}
#[test]
fn test_remove_all_inout_links() {
let mut g = Network::new();
let i1 = g.add_node(NodeT::Input, ());
let h1 = g.add_node(NodeT::Hidden, ());
let h2 = g.add_node(NodeT::Hidden, ());
let o1 = g.add_node(NodeT::Output, ());
g.add_link_unordered(i1, h1, 0.0, ());
g.add_link_unordered(i1, h2, 0.0, ());
g.add_link_unordered(h1, o1, 0.0, ());
g.add_link_unordered(h2, o1, 0.0, ());
assert_eq!(2, g.node(i1).out_degree());
assert_eq!(1, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(2, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(4, g.link_count());
g.remove_all_inout_links_of_node(i1);
assert!(g.first_link_of_node(i1).is_none());
assert!(g.last_link_of_node(i1).is_none());
assert_eq!(0, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(0, g.node(h2).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(2, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(2, g.link_count());
g.remove_all_inout_links_of_node(h1);
assert_eq!(0, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(0, g.node(h2).in_degree());
assert_eq!(0, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(1, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(1, g.link_count());
g.remove_all_inout_links_of_node(o1);
assert_eq!(0, g.node(i1).out_degree());
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(0, g.node(h2).in_degree());
assert_eq!(0, g.node(h1).out_degree());
assert_eq!(0, g.node(h2).out_degree());
assert_eq!(0, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(0, g.link_count());
}
#[test]
fn test_remove_node() {
let mut g = Network::new();
let i1 = g.add_node(NodeT::Input, ());
let h1 = g.add_node(NodeT::Hidden, ());
let h2 = g.add_node(NodeT::Hidden, ());
let o1 = g.add_node(NodeT::Output, ());
g.add_link_unordered(i1, h1, 0.0, ());
g.add_link_unordered(i1, h2, 0.0, ());
g.add_link_unordered(h1, o1, 0.0, ());
g.add_link_unordered(h2, o1, 0.0, ());
assert_eq!(2, g.node(i1).out_degree());
assert_eq!(1, g.node(h1).in_degree());
assert_eq!(1, g.node(h2).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(2, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(4, g.link_count());
assert_eq!(4, g.node_count());
assert_eq!(NodeIndex(0), i1);
assert_eq!(NodeIndex(3), o1);
g.remove_node(i1);
let o1 = i1;
drop(i1);
assert_eq!(NodeIndex(0), o1);
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(0, g.node(h2).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(h2).out_degree());
assert_eq!(2, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(2, g.link_count());
assert_eq!(3, g.node_count());
assert_eq!(NodeIndex(2), h2);
g.remove_node(h2);
drop(h2);
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(1, g.node(h1).out_degree());
assert_eq!(1, g.node(o1).in_degree());
assert_eq!(0, g.node(o1).out_degree());
assert_eq!(1, g.link_count());
assert_eq!(2, g.node_count());
assert_eq!(NodeIndex(0), o1);
g.remove_node(o1);
let h1 = o1;
drop(o1);
assert_eq!(NodeIndex(0), h1);
assert_eq!(0, g.node(h1).in_degree());
assert_eq!(0, g.node(h1).out_degree());
assert_eq!(0, g.link_count());
assert_eq!(1, g.node_count());
assert_eq!(NodeIndex(0), h1);
g.remove_node(h1);
assert_eq!(0, g.node_count());
}
}
<file_sep>[package]
name = "acyclic-network"
version = "0.2.0"
authors = ["<NAME> <<EMAIL>>"]
license = "MIT"
repository = "https://github.com/mneumann/acyclic-network-rs"
description = "Acyclic network representation and construction"
keywords = ["graph", "network", "net"]
include = ["src/*.rs", "Cargo.toml", "LICENSE", "README.md"]
[dependencies]
rand = "0.4"
fixedbitset = "0.1"
| 6a088e987f4a6db870ac63e764b06f3d5a158f57 | [
"Markdown",
"Rust",
"TOML"
] | 4 | Rust | mneumann/acyclic-network-rs | 6d36d5628f00bffb7aabcb72bec8b89d91cf9d4d | 93cfa74f2988bdd2aea01f4a24e47c055c135537 |
refs/heads/master | <file_sep>
import java.util.Scanner;
public class TheSumBetweenTwoNumbers
{
public static void main(String[] args)
{
Scanner reader = new Scanner(System.in);
System.out.println("First:");
int from = Integer.parseInt(reader.nextLine());
System.out.println("Second:");
int until = Integer.parseInt(reader.nextLine());
int num=from;
int sum =0;
while (num<=until)
{
sum = sum+num;
num++;
}
System.out.println("The sum is "+sum);
}
}
<file_sep># PQTM_JAVA
Aqui colgare los ejercicios realizados durante el curso de PQTM JAVA en CIFO La Violeta
| b1d7c6dd40d16e5b6ab5a4398750aaa680891f80 | [
"Markdown",
"Java"
] | 2 | Java | LionelSebastian/PQTM_JAVA | d4ac54b40e9cd6947733c7edc51bbe31bf4459fe | 190b67c283a2eae33f7d6b73c8579ef0e1cccf6f |
refs/heads/master | <repo_name>mehikmat/PyHadoop<file_sep>/README.md
PyHadoop
========
Python based Hadoop command-line interface
How to install?
---------------
```
$> sudo pip install pyhadoop
```
What is this?
--------------
It's very samll app.
Actaully I have built it for myself to automate daily tasks related to hadoop.
You cat get benefited from it too.
Usage:
-------
```
pyhadoop -h : for help
pyhadoop start : starts hadoop
pyhadoop stop : stops hadoop
```
<file_sep>/setup.py
# meta file for project distribution
import os, sys
from setuptools import setup
# Utility function to read the README file.
# Used for the long_description. It's nice, because now
# 1) we have a top level README.md file and
# 2) it's easier to type in the README file than to put a raw
# string in below ...
def read(fname):
return open(os.path.join(os.path.dirname(__file__), fname)).read()
setup(
name = 'pyhadoop',
packages = ['pyhadoop'], # this must be the same as the name above
version = '0.1',
description = 'Python based hadoop command-line interface',
author = 'mehikmat',
author_email = '<EMAIL>',
license = "MIT",
platforms = ["any"],
url = 'https://github.com/mehikmat/PyHadoop', # use the URL to the github repo
download_url = 'https://github.com/mehikmat/PyHadoop/tarball/0.1', # I'll explain this in a second
keywords = ['hadoop', 'python', 'command-line'], # arbitrary keywords
long_description=open('README.md').read(),
classifiers=[
"Development Status :: 5 - Production/Stable",
"Topic :: Utilities",
"License :: OSI Approved :: MIT License",
],
entry_points={
"console_scripts": [
"pyhadoop=pyhadoop:main",
"pyhadoop%s=pyhadoop:main" % sys.version[:1],
"pyhadoop%s=pyhadoop:main" % sys.version[:3],
],
},
)<file_sep>/pyhadoop/__init__.py
import argparse
import sys
import os
from resources import command_map
__author__ = 'hikmat'
"""
Module docstring.
This serves as a long usage message.
"""
HADOOP_HOME = ""
def set_vars():
global HADOOP_HOME
HADOOP_HOME = os.getenv("HADOOP_HOME","NULL")
def validate_vars():
if HADOOP_HOME == "NULL":
print("HADOOP_HOME has not been set. Please set it.")
exit()
def main():
set_vars()
validate_vars()
parser = argparse.ArgumentParser(description='Processes commands aganist hadoop')
parser.add_argument("command", help='hadoop command to be executed')
args = parser.parse_args()
cmd = args.command
cmd_exec=''
if cmd in command_map.keys():
cmd_exec = command_map[cmd]
else:
print("Oops!!! Unknown command!!!")
print("Valid commands are:")
print("========================")
print("$> pyhadoop start")
print("$> pyhadoop stop")
print("$> pyhadoop cp src dest")
print("$> pyhadoop mv src dest")
print("========================\n")
sys.exit(1)
cmd_exec = cmd_exec.replace("$HADOOP_HOME",HADOOP_HOME)
print("Executing {} .........".format(cmd_exec))
os.system(cmd_exec)
if __name__ == '__main__':
sys.exit(main())<file_sep>/pyhadoop/resources.py
# command map
command_map = {
"start" : "$HADOOP_HOME/sbin/start-all.sh",
"stop" : "$HADOOP_HOME/sbin/stop-all.sh",
"cp" : "$HADOOP_HOME/bin/hadoop fs -cp",
"rm" : "$HADOOP_HOME/bin/hadoop fs -rmr",
"ls" : "$HADOOP_HOME/bin/hadoop fs -ls",
}
<file_sep>/pyhadoop/__main__.py
import sys
if __package__ == '':
import os
path = os.path.dirname(os.path.dirname(__file__))
sys.path.insert(0, path)
import pyhadoop
if __name__ == '__main__':
sys.exit(pyhadoop.main())
| 9dd8c9ae6c780eb8c10e0855b531056e0a329fcc | [
"Markdown",
"Python"
] | 5 | Markdown | mehikmat/PyHadoop | f72cade2c7f79679b9b4d5b6204cfaf9b9530cb7 | b07fe10974f5dfd2b37896a1da609ac4fda03572 |
refs/heads/master | <file_sep><?php
$conexion = mysqli_connect('localhost','root','','tienda');
//$conexion = mysqli_connect('localhost','id453697_xx1196','11221133','id453697_wayu');
<file_sep><!DOCTYPE html>
<html lang="en">
<head>
<!-- Required meta tags always come first -->
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
<meta http-equiv="x-ua-compatible" content="ie=edge">
<!-- Bootstrap CSS -->
<link rel="stylesheet" href="css/bootstrap-flex.min.css">
<script src="https://use.fontawesome.com/5765211a64.js"></script>
<link href="https://fonts.googleapis.com/css?family=Montserrat" rel="stylesheet">
<link rel="stylesheet" href="css/app.css">
</head>
<body>
<!-- Header -->
<header id="header-container">
<div class="container">
<div class="row flex-items-xs-middle flex-items-xs-between">
<div class="col-xs-6">
<h1 class="pull-xs-left">Bag Store</h1>
</div>
<div class="col-xs-3">
<button class="navbar-toggler pull-xs-right hidden-sm-up" type="button" data-toggle="collapse" data-target="#navMenu" aria-controls="navMenu" aria-expanded="false" aria-label="Toggle navigation">
☰
</button>
</div>
</div>
</div>
</header>
<!-- /Header -->
<!-- Menu -->
<div id="menu-container">
<nav id="navMenu" class="navbar-toggleable-xs navbar navbar-light collapse">
<div class="container">
<div class="row">
<div class="col-xs-12 col-md-4">
<div class="nav-container text-xs-center text-md-left">
<ul class="nav navbar-nav">
<li class="nav-item text-xs-center active">
<a class="nav-link" href="#">Home <span class="sr-only">(current)</span></a>
</li>
<li class="nav-item text-xs-center">
<a class="nav-link" href="catalogo.html">Catálogo</a>
</li>
<li class="nav-item text-xs-center">
<a class="nav-link" href="#">Carrito</a>
</li>
<li class="nav-item hidden-sm-up text-xs-center">
<a class="nav-link" href="#">Login</a>
</li>
</ul>
</div>
</div>
<div class="col-md-6 col-xs-12 offset-md-2 hidden-xs-down">
<form>
<div class="input-group">
<input type="text" class="form-control" placeholder="¿Encontró lo que buscaba?">
<span class="input-group-btn">
<button class="btn btn-platzi" type="button">
<span class="hidden-sm-down">Buscar</span>
<i class="fa fa-search hidden-md-up"></i>
</button>
</span>
</div>
</form>
</div>
</div>
</div>
</nav>
<div id="search-bar" class="container hidden-sm-up">
<div class="row">
<div class="col-xs-12">
<form>
<div class="input-group">
<input type="text" class="form-control" placeholder="¿Encontró lo que buscaba?">
<span class="input-group-btn">
<button class="btn btn-platzi" type="button">
<span class="hidden-sm-down">Buscar</span>
<i class="fa fa-search hidden-md-up"></i>
</button>
</span>
</div>
</form>
</div>
</div>
</div>
</div>
<!-- /Menu -->
<!-- Carousel -->
<div id="carousel-container">
<div id="productsCarousel" class="carousel slide" data-ride="carousel">
<ol class="carousel-indicators">
<li data-target="#productsCarousel" data-slide-to="0" class="active"></li>
<li data-target="#productsCarousel" data-slide-to="1"></li>
<li data-target="#productsCarousel" data-slide-to="2"></li>
</ol>
<?php
include 'conexion.php';
$sql="select * from productos";
$query=mysqli_query($conexion,$sql);
while ($query){
?>
<div class="carousel-inner" role="listbox">
<div class="carousel-item active">
<img src="images/<?php echo $query[imagen]; ?>" alt="First slide">
<div class="carousel-caption">
<h3>Primer producto</h3>
<p class="hidden-sm-down">Con este producto egestas, nisi a efficitur porttitor, libero nisi viverra arcu, semper accumsan lectus est sit amet diam. Donec eget massa in arcu mattis laoreet id vel libero. Etiam tristique fermentum sem</p>
</div>
</div>
</div>
<?php
}
?>
<a class="left carousel-control" href="#productsCarousel" role="button" data-slide="prev">
<span class="icon-prev" aria-hidden="true"></span>
<span class="sr-only">Previous</span>
</a>
<a class="right carousel-control" href="#productsCarousel" role="button" data-slide="next">
<span class="icon-next" aria-hidden="true"></span>
<span class="sr-only">Next</span>
</a>
</div>
</div>
<!-- /Carousel -->
<!-- Información -->
<div id="info-container">
<div class="container">
<div class="row flex-items-xs-middle">
<div class="col-md-4">
<img src="images/calidad.png" alt="Calidad" class="img-fluid">
<h4>Calidad</h4>
</div>
<div class="col-md-4">
<img src="images/envio.png" alt="Envío gratis" class="img-fluid">
<h4>Envío gratis</h4>
</div>
<div class="col-md-4">
<img src="images/soporte.png" alt="Soporte" class="img-fluid">
<h4>Soporte 24hs</h4>
</div>
</div>
</div>
</div>
<!-- /Información -->
<!-- Footer -->
<div id="footer-container">
<div class="container">
<div class="row text-xs-center text-sm-left">
<div class="col-md-4">
<form id="suscribeForm" action="#" method="POST">
<h4 class="text-uppercase">¿Quiés recibir todas las novedades?</h4>
<div class="form-group">
<input type="email" class="form-control" id="email" aria-describedby="emailHelp" placeholder="<EMAIL>" name="email">
<small id="emailHelp" class="form-text text-muted">No compartiremos tu información con nadie más</small>
</div>
<button type="submit" class="btn btn-primary form-text">Suscribirme</button>
</form>
</div>
<div class="col-md-3 offset-md-5">
<h4 class="navigation">Navegación</h4>
<ul class="nav">
<li class="nav-item"><a class="nav-link" href="#">Home</a></li>
<li class="nav-item"><a class="nav-link" href="#">Productos</a></li>
<li class="nav-item"><a class="nav-link" href="#">Carrito</a></li>
<li class="nav-item"><a class="nav-link" href="#">Login</a></li>
<li class="nav-item"><a class="nav-link" href="#">FAQ</a></li>
<li class="nav-item"><a class="nav-link" href="#">Contacto</a></li>
</ul>
</div>
</div>
</div>
</div>
<!-- /Footer -->
<!-- jQuery first, then Tether, then Bootstrap JS. -->
<script src="https://ajax.googleapis.com/ajax/libs/jquery/3.0.0/jquery.min.js" integrity="<KEY>" crossorigin="anonymous"></script>
<script src="https://cdnjs.cloudflare.com/ajax/libs/tether/1.2.0/js/tether.min.js" integrity="<KEY>" crossorigin="anonymous"></script>
<script src="https://maxcdn.bootstrapcdn.com/bootstrap/4.0.0-alpha.3/js/bootstrap.min.js" integrity="<KEY>" crossorigin="anonymous"></script>
<script src="js/app.js"></script>
</body>
</html>
| 9f54ba0a0e53ad4e7881f221838bd81b6d0c280f | [
"PHP"
] | 2 | PHP | xx1196/Tienda-php | 900eea6c96f44d263762ca09180f338570a22c80 | 130400dd943bd5eb3a08ad9846a81765899fc968 |
refs/heads/master | <repo_name>scottshotgg/express-lex<file_sep>/go.mod
module github.com/scottshotgg/express-lex
go 1.12
require (
github.com/pkg/errors v0.9.1
github.com/scottshotgg/express-token v0.0.0-20230327011102-da006d30a2eb
)
<file_sep>/test/lex_test.go
package lex_test
import (
"encoding/json"
"fmt"
"os"
"testing"
lex "github.com/scottshotgg/express-lex"
token "github.com/scottshotgg/express-token"
)
var (
l *lex.Lexer
// TODO: one thing the old lexer architecture fixed was the space at the end
simpleTest = `
package something
i++
c {
int i = 0;
}
import "me"
include "me"
// 🔥 comments r kewl 🔥
var 👌 = "hey, it's \"me\" 😏" + 5 + 10.2/* WOAH YEAH */ ;
string pokemans = "Woah! That's super effective!"
floatyMcFloatFace := -66.67383824732894
object 宇宙カウボーイ = {
космос: "ковбой"
}
char[] bae_toe_ven = "i got luv 4 tha street"
宇宙カウボーイ["космос"] = bae_toe_ven + 666
char[] me
interface i = {}`
)
func TestNew(t *testing.T) {
l = lex.New(simpleTest)
fmt.Printf("Lexer: %+v\n", l)
}
func TestLex(t *testing.T) {
TestNew(t)
lexemes, err := l.Lex()
if err != nil {
panic(err)
}
// fmt.Printf("lexemes: %+v\n", lexemes)
for i, lexeme := range lexemes {
fmt.Println("i", i, lexeme)
}
lexemeJSON, err := json.Marshal(lexemes)
if err != nil {
fmt.Println("jsonErr", err)
}
fmt.Println(string(lexemeJSON))
}
func TestNewFromFile(t *testing.T) {
lexer, err := lex.NewFromFile("../test/programs/struct.expr")
if err != nil {
fmt.Println("NewFromFile", err)
os.Exit(9)
}
lexTokens, err := lexer.Lex()
if err != nil {
fmt.Println("LexErr", err)
os.Exit(9)
}
token.PrintTokens(lexTokens, "\t")
}
| 2e958c904e1a38fdb26c6ba8e4e0c1b5a340cb59 | [
"Go",
"Go Module"
] | 2 | Go Module | scottshotgg/express-lex | c6a28a8eb8a300873b390c1cf5577c1e019406cd | f52d495d4e14f64d4802496cbaaf8fef3b7d9fc1 |
refs/heads/master | <file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<script type="text/javascript">
$(document).ready(function(){
$(".icon_delete").click(function(){
var products_amount = $(this).next("input[type='hidden']").val();
if (products_amount > 0) {
alert("Không thể xoá công dụng đang chứa sản phẩm");
return false;
} else {
if(!window.confirm("Chắc chắn muốn xoá công dụng này?")){
return false;
}
}
});
});
</script>
<div id="effects_list">
<a href="index.php?controller=salesmanager&resources=effect&action=new" class="btn btn-success">Thêm</a>
<table class="table table-hover table-bordered">
<thead>
<tr>
<th class="index">STT</th>
<th class="effect_name">Tên công dụng</th>
<th class="products_amount">Số lượng sản phẩm</th>
<th class="edit">Sửa</th>
<th class="del">Xoá</th>
</tr>
</thead>
<tbody>
<?php
if($data['data'] == ""){
echo "<tr>";
echo "<td colspan='5'>Chưa có dữ liệu</td>";
echo "</tr>";
}else{
$stt = 1;
foreach($data['data'] as $item){
echo "<tr>";
echo "<td>$stt</td>";
echo "<td>$item[content]</td>";
echo "<td>".number_format($item['products_amount'])."</td>";
echo "<td><a href='index.php?controller=salesmanager&resources=effect&action=edit&oeid=$item[oeid]'><span class='icon_edit'></span></a></td>";
if($item['oeid'] == 1){
echo "<td> </td>";
}else{
echo "<td><a href='index.php?controller=salesmanager&resources=effect&action=destroy&oeid=$item[oeid]'><span class='icon_delete'></span><input type='hidden' value='$item[products_amount]'></a></td>";
}
echo "</tr>";
$stt++;
}
}
?>
</tbody>
</table>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$pid = $_GET['pid'];
$mproduct = new Model_Product;
$mproduct->select("pid, name, quantity, oeid");
$data['data'] = $mproduct->getProductById($pid);
$data['current_page'] = $_GET['page'];
if(isset($_POST['ok'])){
$quantity = $change = "";
if(empty($_POST['add_quantity']) && empty($_POST['subtract_quantity'])){
$data['error'][] = "Chưa nhập số lượng thay đổi";
}else{
if(empty($_POST['add_quantity'])){
$quantity = $_POST['subtract_quantity'];
$change = "down";
}else{
$quantity = $_POST['add_quantity'];
$change = "up";
}
}
if($quantity){
$mproduct->updateProductAmount($pid, $quantity, $change);
$meffect = new Model_Effect;
$meffect->changeAmountWhenUpdateProductAmount($data['data']['oeid'], $quantity, $change);
redirect("index.php?controller=salesmanager&resources=product&page=$data[current_page]");
}
}
$data['title_tag'] = "Cập nhật số lượng sản phẩm";
loadview("salesmanager/product/quantity_update", $data);
<file_sep><?php
$oeid = $_GET['oeid'];
$meffect = new Model_Effect;
$meffect->select("oeid, content");
if(isset($_POST['ok'])){
$effect = "";
if(empty($_POST['txteffect'])){
$data['error'][] = "Tên công dụng không được để trống";
}else{
$effect = $_POST['txteffect'];
}
if($effect){
$check_data = array(
"oeid <>" => $oeid,
"content =" => $effect
);
$meffect->select("oeid, content");
if($meffect->checkEffect($check_data) == true){
$meffect->where("oeid = '$oeid'");
$update_data = array("content" => $effect);
$meffect->updateEffect($update_data);
redirect("index.php?controller=salesmanager&resources=effect&action=index");
}else{
$data['error'][] = "Tên công dụng đã tồn tại, vui lòng chọn tên khác";
}
}
}
$data['data'] = $meffect->getEffectById($oeid);
$data['title_tag'] = "Chỉnh sửa công dụng";
loadview("salesmanager/effect/edit", $data);
<file_sep><?php
$data = "";
if(isset($_POST['ok'])){
$effect = "";
if(empty($_POST['txteffect'])){
$data['error'][] = "Vui lòng nhập tên công dụng mới";
}else{
$effect = $_POST['txteffect'];
}
if($effect){
$meffect = new Model_Effect;
$meffect->where("content = '$effect'");
$meffect->select("content");
if($meffect->checkEffect() == true){
$input_data = array("content" => $effect);
$meffect->addEffect($input_data);
redirect("index.php?controller=salesmanager&resources=effect&action=index");
}else{
$data['error'][] = "Tên công dụng đã tồn tại, vui lòng chọn tên khác";
}
}
}
$data['title_tag'] = "Thêm công dụng mới";
loadview("salesmanager/effect/new", $data);
<file_sep><?php
if(isset($_GET['action'])){
switch($_GET['action']){
case "index": require("controllers/salesmanager/remark/index.php"); break;
case "accept": require("controllers/salesmanager/remark/accept.php"); break;
case "cancel": require("controllers/salesmanager/remark/cancel.php"); break;
}
}else{
require("controllers/salesmanager/remark/index.php");
}
<file_sep><?php
$per_page = 7;
$muser = new Model_User;
$muser->listUser();
$users_amount = $muser->num_rows();
$data['page'] = ceil($users_amount / $per_page);
$muser->order("uid", "DESC");
if (isset($_GET['page'])) {
$data['current_page'] = $_GET['page'];
$start = $per_page * ($data['current_page'] - 1);
$muser->limit($per_page, $start);
} else {
$muser->limit($per_page);
$data['current_page'] = 1;
}
$data['user'] = $muser->listUser();
if (!empty($data['user'])) {
$minvoice = new Model_Invoice;
$minvoice->select("iid");
$mremark = new Model_Remark;
$mremark->select("remid");
$i = 0;
foreach ($data['user'] as $item) {
if ($item['level'] == 1) {
$invoices_amount = $minvoice->countInvoiceByUid($item['uid']);
$data['user'][$i]['invoices_amount'] = $invoices_amount;
$remarks_amount = $mremark->countRemarkByUid($item['uid']);
$data['user'][$i]['remarks_amount'] = $remarks_amount;
} else {
$data['user'][$i]['invoices_amount'] = $data['user'][$i]['remarks_amount'] = 0;
}
$i++;
}
}
$data['title_tag'] = "Quản lý thành viên";
loadview("admin/user/index", $data);
<file_sep><?php
if(isset($_GET['action'])){
switch($_GET['action']){
case "new": require("controllers/user/address/new.php"); break;
case "list_district_ajax": require("controllers/user/address/list_district_ajax.php"); break;
case "list_commune_ajax": require("controllers/user/address/list_commune_ajax.php"); break;
case "destroy": require("controllers/user/address/destroy.php"); break;
case "edit": require("controllers/user/address/edit.php"); break;
}
}
<file_sep><?php
loadview("layouts/header", $data);
?>
<script type="text/javascript">
$(document).ready(function(){
$("#ask_and_answer #aaa_left table tr:last-child td").css("border-bottom", "none");
});
</script>
<div id="ask_and_answer" style="width: 1000px; margin: auto; min-height: 257px;">
<div id="aaa_left">
<table>
<?php
if (empty($data['qanda'])) {
echo "<tr>";
echo "<td>Chưa có câu hỏi nào</td>";
echo "</tr>";
} else {
foreach ($data['qanda'] as $item) {
echo "<tr>";
echo "<td>";
echo "<p><span style='font-weight: bold;'>Hỏi:</span> $item[content]</p>";
echo "<p><span style='font-weight: bold;'>Trả lời:</span><br>$item[answer]</p>";
echo "</td>";
echo "</tr>";
}
}
?>
</table>
</div>
<div id="aaa_right">
<p style="font-weight: bold; font-size: 12pt;">Vui lòng đặt câu hỏi của bạn tại đây:</p>
<p><i>(Chúng tôi sẽ phản hồi câu hỏi của bạn trong thời gian sớm nhất có thể)</i></p>
<form action='index.php?controller=ask_and_answer&action=new' method='post'>
<textarea cols="20" rows="6" name="question" required="required" class="form-control" style="resize: none;" placeholder="Viết câu hỏi của bạn..."></textarea>
<input type="submit" name="ok" value="Gửi" class="btn btn-primary" style="margin: 10px 0 0 237px; padding: 3px 20px;">
</form>
</div>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
class Model_District extends Model{
protected $_table = "districts";
public function listDistrictByProvid($provid){
$this->where("provid = '$provid'");
$this->getData($this->_table);
return $this->fetchAll();
}
public function getDistrictById($id){
$this->where("distid = '$id'");
$this->getData($this->_table);
return $this->fetch();
}
}
<file_sep><?php
loadview("layouts/header", $data);
?>
<div id="view_invoice_detail" style="min-height: 257px;">
<a href="index.php?controller=user&resources=invoice&action=index&uid=17" class="btn btn-info">← Danh sách hoá đơn</a>
<div class="products_list">
<table class="table table-hover table-bordered">
<thead>
<tr>
<th style="width: 60px;">STT</th>
<th>Tên sản phẩm</th>
<th style="width: 130px;">Số lượng</th>
<th style="width: 170px;">Thành tiền</th>
</tr>
</thead>
<tbody>
<?php
$stt = 1;
foreach ($data['product'] as $item) {
echo "<tr>";
echo "<td>$stt</td>";
echo "<td><a href='index.php?controller=product&action=show&pid=$item[pid]'>$item[name]</a></td>";
echo "<td>$item[quantity]</td>";
echo "<td>".number_format($item['price'] * $item['quantity'])." ₫</td>";
echo "</tr>";
$stt++;
}
?>
<tr style="font-weight: bold;">
<td colspan='2'>Tổng cộng</td>
<td><?php echo number_format($data['invoice']['products_amount']); ?></td>
<td style="color: #f00;"><?php echo number_format($data['invoice']['total']); ?> ₫</td>
</tr>
</tbody>
</table>
</div>
<div class="respective_addr">
<p style="font-size: 11pt; font-weight: bold;">Địa chỉ giao hàng</p>
<div>
<?php
if (!empty($data['addr'])) {
echo "<p style='font-size: 12pt; font-weight: bold;'>".$data['addr']['fullname']."</p>";
echo "<p>Địa chỉ: ".$data['addr']['address'].", ".$data['addr']['comm_name'].", ".$data['addr']['dist_name'].", ".$data['addr']['prov_name']."</p>";
echo "<p>Số điện thoại: ".$data['addr']['telephone']."</p>";
} else {
echo "<p>Địa chỉ sẽ được cập nhật sau khi đặt hàng</p>";
}
?>
</div>
</div>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<script type="text/javascript">
$(document).ready(function(){
$("#increase_product").keyup(function(){
if($(this).val() != ""){
$("#decrease_product").attr("disabled", "disabled");
}else{
if ($("#update_quantity_current_amount").val() > 0)
$("#decrease_product").removeAttr("disabled");
}
});
$("#decrease_product").keyup(function(){
if($(this).val() != ""){
$("#increase_product").attr("disabled", "disabled");
}else{
$("#increase_product").removeAttr("disabled");
}
});
$("input[type='submit']").click(function(){
var pattern = /^[0-9]+$/;
if ($("#increase_product").val() != "") {
var change_amount = $("#increase_product").val();
if ((pattern.test(change_amount) == false) || (change_amount == 0)) {
alert("Số lượng nhập vào không hợp lệ");
$("#increase_product").val("");
$("#decrease_product").removeAttr("disabled");
return false;
}
} else {
var change_amount = $("#decrease_product").val();
if ((pattern.test(change_amount) == false) || (change_amount == 0)) {
alert("Số lượng nhập vào không hợp lệ");
$("#decrease_product").val("");
$("#increase_product").removeAttr("disabled");
return false;
} else {
if (parseInt(change_amount) > parseInt($("#update_quantity_current_amount").val())) {
alert("Số lượng bớt đi không được lớn hơn số lượng hiện có");
return false;
}
}
}
});
});
</script>
<div id="update_product_quantity">
<div class="error">
<?php
if(!empty($data['error'])){
echo "<ul>";
foreach($data['error'] as $err){
echo "<li>$err</li>";
}
echo "</ul>";
}
?>
</div>
<?php
echo "<form action='index.php?controller=salesmanager&resources=product&action=quantity_update&pid=".$data['data']['pid']."&page=$data[current_page]' method='post'>";
?>
<form action="index.php?controller=salesmanager&resources=product&action=quantity_update&pid=<?php echo $data['data']['pid']; ?>&page=<?php ?>" method="post">
<table>
<tr>
<td>Tên sản phẩm</td>
<td style="color: brown; font-weight: bold;"><?php echo $data['data']['name']; ?></td>
</tr>
<tr>
<td>Số lượng hiện có</td>
<td style="color: brown; font-weight: bold;"><?php echo number_format($data['data']['quantity']); ?></td>
<?php
echo "<input type='hidden' id='update_quantity_current_amount' value='".$data['data']['quantity']."'>";
?>
</tr>
<tr>
<td>Bạn muốn thêm</td>
<td><input type="text" name="add_quantity" class="form-control" id="increase_product" /> <span>sản phẩm</span></td>
</tr>
<tr>
<td>hoặc bớt</td>
<td><input type="text" name="subtract_quantity" class="form-control" id="decrease_product" <?php if ($data['data']['quantity'] == 0) echo "disabled='disabled'"; ?> /> <span>sản phẩm</span></td>
</tr>
<tr>
<td></td>
<td><input type="submit" name="ok" value="Cập nhật" class="btn btn-primary" /></td>
</tr>
</table>
</form>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
class Model_Question extends Model{
protected $_table = "questions";
public function addQuestion($data){
$this->insert($this->_table, $data);
}
public function listQuestion(){
$this->getData($this->_table);
return $this->fetchAll();
}
public function getQuestionByQid($qid){
$this->where("qid = '$qid'");
$this->getData($this->_table);
return $this->fetch();
}
public function updateQuestion($data){
$this->update($this->_table, $data);
}
}
<file_sep><?php
loadview("layouts/header", $data);
?>
<script type="text/javascript">
$(document).ready(function(){
$("#slider .carousel-inner .item:first-child").addClass("active");
});
</script>
<div id="info">
<?php
if (empty($data['news']) || count($data['news']) < 3) {
echo "<img src='https://api.fnkr.net/testimg/630x300/?text=slider here' alt=''>";
} else {
echo "<div id='slider'>";
echo "<div id='carousel-example-generic' class='carousel slide' data-ride='carousel'>";
// <!-- Indicators -->
echo "<ol class='carousel-indicators'>";
echo "<li data-target='#carousel-example-generic' data-slide-to='0' class='active'></li>";
echo "<li data-target='#carousel-example-generic' data-slide-to='1'></li>";
echo "<li data-target='#carousel-example-generic' data-slide-to='2'></li>";
echo "</ol>";
// <!-- Wrapper for slides -->
echo "<div class='carousel-inner' role='listbox'>";
foreach ($data['news'] as $item) {
echo "<div class='item'>";
echo "<a href='index.php?controller=news&action=show&nid=$item[nid]'><img src='assets/images/news/$item[poster]' style='width: 630px; height: 300px;'></a>";
echo "<div class='carousel-caption'>";
echo "<h2 style='padding: 5px; border-radius: 15px; background-color: rgba(0, 0, 0, 0.5);'>$item[title]</h2>";
echo "</div>";
echo "</div>";
}
echo "</div>";
// <!-- Controls -->
echo "<a class='left carousel-control' href='#carousel-example-generic' role='button' data-slide='prev'>";
echo "<span class='glyphicon glyphicon-chevron-left' aria-hidden='true'></span>";
echo "<span class='sr-only'>Previous</span>";
echo "</a>";
echo "<a class='right carousel-control' href='#carousel-example-generic' role='button' data-slide='next'>";
echo "<span class='glyphicon glyphicon-chevron-right' aria-hidden='true'></span>";
echo "<span class='sr-only'>Next</span>";
echo "</a>";
echo "</div>";
echo "</div>";
}
?>
<!-- SLIDER -->
<div id="ads">
<div id="up_ads">
<a href="index.php?controller=ask_and_answer"><img src="assets/images/system/consult.png"></a>
</div>
<div id="down_ads">
<p>Đăng ký nhận thông báo từ website</p>
<form>
<input type="text" placeholder="Email của bạn" class="form-control">
<button class="btn btn-info">Đăng ký</button>
</form>
</div>
</div>
</div>
<div class="clr"></div>
<div id="main">
<div id="main_left">
<h3>SẢN PHẨM BÁN CHẠY</h3>
<ul style='border-top: 2px solid #FDD504;'>
<?php
if(empty($data['main_left'])){
echo "<li style='font-size: 12pt;'>Chưa có sản phẩm nào</li>";
}else{
foreach($data['main_left'] as $item){
echo "<li>";
echo "<div class='thumbnail'>";
echo "<a href='index.php?controller=product&action=show&pid=$item[pid]'><img src='assets/images/products/$item[image]'></a>";
echo "</div>";
echo "<div class='abstract_info'>";
$input_day = date("Y/m/d", strtotime($item['created_at']));
$day = (strtotime(date("Y/m/d")) - strtotime($input_day)) / (60 * 60 * 24);
if ($day < 15) {
echo "<a href='index.php?controller=product&action=show&pid=$item[pid]'>$item[name]</a><img src='assets/images/system/new.gif' style='margin: 0 0 3px 5px;'>";
} else {
echo "<a href='index.php?controller=product&action=show&pid=$item[pid]'>$item[name]</a>";
}
echo "<p></p>";
echo "</div>";
echo "</li>";
}
}
?>
</ul>
</div>
<div id="main_right">
<?php
if(empty($data['main_right'])){
echo "<p style='margin: 10px; font-size: 12pt;'>Chưa có sản phẩm nào</p>";
}else{
foreach($data['main_right'] as $item){
echo "<div class='product'>";
echo "<a href='index.php?controller=product&action=show&pid=$item[pid]'>";
echo "<img src='assets/images/products/$item[image]' />";
echo "<h2 class='product_name'>$item[name]</h2>";
echo "<p class='product_price'>".number_format($item['price'])."₫</p>";
echo "</a>";
echo "</div>";
}
}
?>
</div>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
if($_SESSION['level'] == 1){
loadview("layouts/header", $data);
}else{
loadview("layouts/simple_header", $data);
}
if($_SESSION['level'] != 1){
echo "<div id='back_to_main_page'>";
if($_SESSION['level'] == 2){
echo "<a href='index.php?controller=salesmanager' class='btn btn-info'>← Đi đến trang quản lý</a>";
}else{
echo "<a href='index.php?controller=admin' class='btn btn-info'>← Đi đến trang quản lý</a>";
}
echo "</div>";
}
?>
<script type="text/javascript">
function check_delete_addr(){
if (!window.confirm("Bạn chắc chắn muốn xoá sổ địa này?")) return false;
}
</script>
<div id="user_profile" style="min-height: 365px;">
<!-- Nav tabs -->
<ul class="nav nav-tabs" role="tablist">
<li role="presentation" <?php if(empty($data['error'])) echo "class='active'"; ?>><a href="#home" aria-controls="home" role="tab" data-toggle="tab">Thông tin chung</a></li>
<li role="presentation" <?php if(!empty($data['error'])) echo "class='active'"; ?>><a href="#profile" aria-controls="profile" role="tab" data-toggle="tab">Chỉnh sửa hồ sơ</a></li>
</ul>
<!-- Tab panes -->
<div class="tab-content">
<div role="tabpanel" class="tab-pane <?php if(empty($data['error'])) echo "active"; ?>" id="home">
<div id="account_info">
<span style="display: block;">Tài khoản</span>
<table>
<tr>
<td>Tên người dùng:</td>
<td><?php echo $data['data']['name']; ?></td>
</tr>
<tr>
<td>Email:</td>
<td><?php echo $data['data']['email']; ?></td>
</tr>
<tr>
<td>Loại tài khoản:</td>
<td>
<?php
switch($data['data']['level']){
case "1": echo "Thành viên"; break;
case "2": echo "<span style='color: blue; font-weight: bold;'>Quản lý bán hàng</span>"; break;
case "3": echo "<span style='color: red; font-weight: bold;'>Quản trị viên</span>"; break;
}
?>
</td>
</tr>
</table>
</div>
<div class="clr"></div>
<?php
if($_SESSION['level'] == 1){
echo "<div id='address_list' style='position: relative;'>";
echo "<span>Sổ địa chỉ</span> <a href='index.php?controller=user&resources=address&action=new' class='btn btn-success' style='position: absolute; padding: 3px; right: 14px;'>Tạo địa chỉ mới</a>";
echo "<div class='clr' style='height: 10px;'></div>";
if($data['addr'] != ""){
foreach ($data['addr'] as $item) {
echo "<div class='address_register' style='position: relative;'>";
echo "<h4>$item[fullname]</h4>";
echo "<p>Địa chỉ: $item[address], $item[comm_name], $item[dist_name], $item[prov_name]</p>";
echo "<p>Điện thoại: $item[telephone]</p>";
echo "<a href='index.php?controller=user&resources=address&action=destroy&addrid=$item[addrid]' onclick='return check_delete_addr();' style='display: block; position: absolute; right: 50px; bottom: 12px;'><span class='icon_delete'></span></a>";
echo "<a href='index.php?controller=user&resources=address&action=edit&addrid=$item[addrid]' style='display: block; position: absolute; bottom: 10px; right: 5px;'><span class='btn btn-default' style='padding: 3px 5px;'>Sửa</span></a>";
echo "</div>";
}
} else {
echo "<div class='address_register' style='position: relative;'>";
echo "Chưa có sổ địa chỉ nào";
echo "</div>";
}
echo "</div>";
}
?>
</div>
<div role="tabpanel" class="tab-pane <?php if(!empty($data['error'])) echo "active"; ?>" id="profile">
<form action="index.php?controller=user&uid=<?php echo $data['data']['uid']; ?>" method="post" enctype="multipart/form-data">
<table>
<tr>
<td>Hình đại diện</td>
<td>
<img src="assets/images/users/<?php echo $data['data']['avatar']; ?>" style="width: 100px; height: 100px; margin-bottom: 5px;" />
<div class="clr"></div>
<span>Chọn ảnh khác</span>
<input type="file" name="avatar" />
</td>
</tr>
<tr>
<td>Tên người dùng</td>
<td><input type="text" name="txtname" class="form-control" value="<?php echo $data['data']['name']; ?>" /></td>
</tr>
<tr>
<td>Mật khẩu cũ</td>
<td><input type="password" name="old_pass" class="form-control" /></td>
</tr>
<tr>
<td>Mật khẩu mới</td>
<td><input type="password" name="new_pass" class="form-control" /></td>
</tr>
<tr>
<td>Nhắc lại mật khẩu mới</td>
<td><input type="password" name="renew_pass" class="form-control" /></td>
</tr>
<tr>
<td></td>
<td><input type="submit" name="ok" value="Cập nhật" class="btn btn-primary" /></td>
</tr>
</table>
</form>
<div class="error">
<?php
if(!empty($data['error'])){
echo "<ul>";
foreach($data['error'] as $err){
echo "<li>$err</li>";
}
echo "</ul>";
}
?>
</div>
</div>
</div>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
class Model_Answer extends Model{
protected $_table = "answers";
public function getAnswerByQid($qid){
$this->where("qid = '$qid'");
$this->getData($this->_table);
return $this->fetch();
}
public function addAnswer($data){
$this->insert($this->_table, $data);
}
}
<file_sep><?php
$data = "";
$mquestion = new Model_Question;
$mquestion->order("qid", "DESC");
$data['data'] = $mquestion->listQuestion();
if(!empty($data['data'])) {
$manswer = new Model_Answer;
$i = 0;
foreach ($data['data'] as $item) {
if ($item['is_responded'] == "1") {
$output = $manswer->getAnswerByQid($item['qid']);
$data['data'][$i]['answer'] = $output['content'];
} else {
$data['data'][$i]['answer'] = "";
}
$i++;
}
}
$data['title_tag'] = "Hỏi đáp";
loadview("salesmanager/ask_and_answer/index", $data);
<file_sep><?php
$data = "";
$_SESSION['is_remain'] = 0;
if(isset($_SESSION['level'])){
$minvoicedetail = new Model_InvoiceDetail;
$minvoicedetail->order("idid", "DESC");
$data['detail'] = $minvoicedetail->listInvoiceDetail($_SESSION['iid']);
if (!empty($data['detail'])) {
$mproduct = new Model_Product;
$mproduct->select("quantity");
$i = 0;
foreach ($data['detail'] as $item) {
$remain_amount = $mproduct->getProductById($item['pid']);
if ($item['quantity'] > $remain_amount['quantity']) {
$data['detail'][$i]['check'] = $remain_amount['quantity'];
$_SESSION['is_remain']++;
} else {
$data['detail'][$i]['check'] = -1;
}
$i++;
}
}
}
$data['title_tag'] = "Giỏ hàng";
loadview("cart/show", $data);
<file_sep><?php
session_start();
require("assets/config/database.php");
require("assets/config/function.php");
if (isset($_SESSION['level']) && ($_SESSION['level'] == 1)) {
if ($_SESSION['total'] > 0) {
$minvoice = new Model_Invoice;
$minvoice->where(array("uid =" => $_SESSION['uid'], "status =" => "1"));
$minvoice->select("total");
$current_total = $minvoice->getTotal();
$_SESSION['total'] = $current_total['total'];
}
}
if(isset($_GET['controller'])){
switch($_GET['controller']){
case "static_page": require("controllers/static_page.php"); break;
case "user": require("controllers/user/user.php"); break;
case "session": require("controllers/session/session.php"); break;
case "admin": require("controllers/admin/admin.php"); break;
case "salesmanager": require("controllers/salesmanager/salesmanager.php"); break;
case "product": require("controllers/product/product.php"); break;
case "cart": require("controllers/cart/cart.php"); break;
case "news": require("controllers/news/news.php"); break;
case "ask_and_answer": require("controllers/ask_and_answer/ask_and_answer.php"); break;
}
}else{
if(isset($_SESSION['level']) && ($_SESSION['level'] == 2)){
redirect("index.php?controller=salesmanager");
}elseif(isset($_SESSION['level']) && ($_SESSION['level'] == 3)){
redirect("index.php?controller=admin");
}else{
$mproduct = new Model_Product;
$mproduct->order("pid", "DESC");
$mproduct->limit("12");
$data['main_right'] = $mproduct->listProduct();
$mproduct->order("sold", "DESC");
$mproduct->where("sold > '0'");
$mproduct->limit("6");
$data['main_left'] = $mproduct->listProduct();
$mnews = new Model_News;
$mnews->order("nid", "DESC");
$mnews->limit("3");
$data['news'] = $mnews->listNews();
loadview("static_pages/home", $data);
}
}
<file_sep><?php
class Model_Commune extends Model{
protected $_table = "communes";
public function listCommuneByDistid($distid){
$this->where("distid = '$distid'");
$this->getData($this->_table);
return $this->fetchAll();
}
public function getCommuneById($id){
$this->where("commid = '$id'");
$this->getData($this->_table);
return $this->fetch();
}
}
<file_sep><!DOCTYPE html>
<html>
<head>
<meta charset="utf-8" />
<meta http-equiv="X-UA-Compatible" content="IE=edge" />
<title>
<?php
if (!empty($data['title_tag'])) {
echo "$data[title_tag] | Quỳnh Phương Herbal Tea";
} else {
echo "Quỳnh Phương Herbal Tea";
}
?>
</title>
<meta name="viewport" content="width=device-width, initial-scale=1, maximum-scale=1, user-scalable=no" />
<link rel="shortcut icon" type="image/x-icon" href="assets/images/system/favicon.ico" />
<link rel="stylesheet" type="text/css" href="assets/stylesheets/bootstrap.min.css" />
<link rel="stylesheet" type="text/css" href="assets/stylesheets/custom.css" />
<link rel="stylesheet" type="text/css" href="assets/stylesheets/btn_top.css" />
<?php
if($_SESSION['level'] == 3){
echo "<link rel='stylesheet' type='text/css' href='assets/stylesheets/admin.css' />";
}
if($_SESSION['level'] == 2){
echo "<link rel='stylesheet' type='text/css' href='assets/stylesheets/salesmanager.css' />";
}
?>
<script type="text/javascript" src="assets/javascripts/jquery.min.js"></script>
<script type="text/javascript" src="assets/ckeditor/ckeditor.js"></script>
</head>
<body>
<div class="website" <?php if($_GET['controller'] == "salesmanager") echo "id='salesmanager_mainpage'"; ?>>
<div id="top">
<div id="top_left">
<ul>
<li id="email">Email: <EMAIL></li>
<li id="hotline">Hotline: 0164.418.3238</li>
</ul>
</div>
<script type="text/javascript">
$(document).ready(function(){
$("#navigation li").hover(function(){
$(this).find("ul:first").toggle();
});
});
</script>
<div id="top_right">
<?php
echo "<div id='current_user'>";
echo "<ul id='navigation'>";
echo "<li>Xin chào <span style='font-weight: bold;'>$_SESSION[name]</span></li>";
echo "<li class='mini_menu'><img src='assets/images/users/$_SESSION[avatar]'>";
echo "<ul>";
echo "<li style='border-top: none;'><a href='index.php?controller=user&uid=$_SESSION[uid]' class='mini_account'>Tài khoản</a></li>";
echo "<li><a href='index.php?controller=session&action=destroy' class='mini_logout'>Đăng xuất</a></li>";
echo "</ul>";
echo "</li>";
echo "</ul>";
echo "</div>";
?>
</div>
</div>
<!-- TOP -->
<div class="clr"></div>
<file_sep><?php
$meffect = new Model_Effect;
$meffect->order("oeid", "DESC");
$data['data'] = $meffect->listEffect();
$data['title_tag'] = "Công dụng nổi bật";
loadview("salesmanager/effect/index", $data);
<file_sep><?php
$addrid = $_GET['addrid'];
$maddressregister = new Model_AddressRegister;
$maddressregister->select("uid");
$addrreg_info = $maddressregister->getAddressRegisterById($addrid);
$maddressregister->deleteAddressRegister($addrid);
redirect("index.php?controller=user&uid=$addrreg_info[uid]");
<file_sep><?php
class Model_Effect extends Model{
protected $_table = "outstanding_effects";
public function addEffect($data){
$this->insert($this->_table, $data);
}
public function listEffect(){
$this->getData($this->_table);
return $this->fetchAll();
}
public function deleteEffect($id){
$this->where("oeid = '$id'");
$this->delete($this->_table);
}
public function checkEffect($data = ""){
if(is_array($data)){
$this->where($data);
}
$this->getData($this->_table);
if($this->num_rows() == 1){
return false;
}else{
return true;
}
}
public function getEffectById($id){
$this->where("oeid = '$id'");
$this->getData($this->_table);
return $this->fetch();
}
public function updateEffect($data){
$this->update($this->_table, $data);
}
public function updateAmount($id, $quantity){
$this->select("products_amount");
$data = $this->getEffectById($id);
$data['products_amount'] += $quantity;
$input_data = array("products_amount" => $data['products_amount']);
$this->updateEffect($input_data);
}
public function changeAmountWhenEditProduct($old_id, $amount, $new_id){
$this->select("products_amount");
$data_old = $this->getEffectById($old_id);
$data_old['products_amount'] -= $amount;
$input_data_old = array("products_amount" => $data_old['products_amount']);
$this->updateEffect($input_data_old);
$data_new = $this->getEffectById($new_id);
$data_new['products_amount'] += $amount;
$input_data_new = array("products_amount" => $data_new['products_amount']);
$this->updateEffect($input_data_new);
}
public function changeAmountWhenUpdateProductAmount($id, $amount, $change){
$this->select("products_amount");
$data = $this->getEffectById($id);
if($change == "up"){
$data['products_amount'] += $amount;
}else{
$data['products_amount'] -= $amount;
}
$input_data = array("products_amount" => $data['products_amount']);
$this->updateEffect($input_data);
}
public function updateAfterOrder($oeid, $quantity){
$this->select("products_amount");
$output = $this->getEffectById($oeid);
$output['products_amount'] -= $quantity;
$update_data = array("products_amount" => $output['products_amount']);
$this->updateEffect($update_data);
}
}
<file_sep><?php
$data = "";
$meffect = new Model_Effect;
$meffect->select("oeid, content");
$data['data'] = $meffect->listEffect();
if(isset($_POST['ok'])){
$name = $price = $description = $outstanding_effect = $packing_method = $quantity = $image = "";
if(empty($_POST['txtname'])){
$data['error'][] = "Chưa nhập TÊN";
}else{
$name = $_POST['txtname'];
}
if(empty($_POST['quantity'])){
$data['error'][] = "Chưa nhập SỐ LƯỢNG";
}else{
$quantity = $_POST['quantity'];
}
if(empty($_POST['price'])){
$data['error'][] = "Chưa nhập GIÁ";
}else{
$price = $_POST['price'];
}
if(empty($_POST['description'])){
$data['error'][] = "Chưa nhập MÔ TẢ CHI TIẾT";
}else{
$description = $_POST['description'];
}
$outstanding_effect = $_POST['outstanding_effect'];
$packing_method = $_POST['packing_method'];
if(empty($_FILES['image']['name'])){
$image = "none";
}else{
$image = $_FILES['image']['name'];
}
if($name && $price && $description && $outstanding_effect && $packing_method && $quantity && $image){
$mproduct = new Model_Product;
$mproduct->where("name = '$name'");
$mproduct->select("name");
if($mproduct->checkProduct() == true){
$input_data = array(
"name" => $name,
"price" => $price,
"quantity" => $quantity,
"packing_method" => $packing_method,
"description" => $description,
"oeid" => $outstanding_effect
);
if($image != "none"){
$input_data['image'] = $image;
move_uploaded_file($_FILES['image']['tmp_name'], "assets/images/products/".$_FILES['image']['name']);
}
$meffect->updateAmount($outstanding_effect, $quantity);
$mproduct->addProduct($input_data);
redirect("index.php?controller=salesmanager&resources=product&action=index");
}else{
$data['error'][] = "Kho hàng ĐÃ CÓ sản phẩm này";
}
}
}
$data['title_tag'] = "Thêm sản phẩm";
loadview("salesmanager/product/new", $data);
<file_sep><?php
if(isset($_POST['ok'])){
$uid = $_POST['uid'];
$pid = $_POST['pid'];
$name = $_POST['name'];
$price = $_POST['price'];
$quantity = $_POST['quantity'];
$image = $_POST['image'];
$subtotal = $price * $quantity;
$_SESSION['products_amount'] += $quantity;
$_SESSION['total'] += $subtotal;
$minvoice = new Model_Invoice;
$minvoicedetail = new Model_InvoiceDetail;
if($_SESSION['iid'] > 0){
// cap nhat gio hang
$minvoice->where("iid = '$_SESSION[iid]'");
$invoice_update_data = array(
"products_amount" => $_SESSION['products_amount'],
"total" => $_SESSION['total']
);
$minvoice->updateInvoice($invoice_update_data);
$check_result = $minvoicedetail->checkProductExistence($_SESSION[iid], $pid);
if(is_array($check_result)){
// da co san pham trong gio hang, cap nhat
$minvoicedetail->where("idid = '$check_result[idid]'");
$check_result['quantity'] += $quantity;
$detail_update_data = array("quantity" => $check_result['quantity']);
$minvoicedetail->updateInvoiceDetail($detail_update_data);
}else{
// chua co san pham trong gio hang, them moi
$detail_input_data = array(
"name" => $name,
"price" => $price,
"quantity" => $quantity,
"image" => $image,
"iid" => $_SESSION['iid'],
"pid" => $pid
);
$minvoicedetail->addInvoiceDetail($detail_input_data);
}
}else{
// tao gio hang moi
$invoice_input_data = array(
"products_amount" => $quantity,
"total" => $subtotal,
"uid" => $uid,
);
$minvoice->addInvoice($invoice_input_data);
$invoice_abstract = array(
"status =" => "1",
"uid =" => $uid
);
$_SESSION['iid'] = $minvoice->getInvoiceId($invoice_abstract);
// them san pham vao gio hang moi tao
$detail_input_data = array(
"name" => $name,
"price" => $price,
"quantity" => $quantity,
"image" => $image,
"iid" => $_SESSION['iid'],
"pid" => $pid
);
$minvoicedetail->addInvoiceDetail($detail_input_data);
}
redirect("http://localhost/www/herbal_tea/index.php?controller=cart");
}
<file_sep><?php
$idid = $_GET['idid'];
$minvoicedetail = new Model_InvoiceDetail;
$minvoicedetail->select("price, quantity, iid");
$product_info = $minvoicedetail->getInvoiceDetailById($idid);
$_SESSION['products_amount'] -= $product_info['quantity'];
$_SESSION['total'] -= $product_info['price'] * $product_info['quantity'];
$minvoicedetail->deleteInvoiceDetail($idid);
$minvoice = new Model_Invoice;
if($_SESSION['total'] == 0){
// neu total = 0, xoa hoa don
$_SESSION['iid'] = 0;
$minvoice->deleteInvoice($product_info['iid']);
}else{
// cap nhat lai hoa don
$minvoice->where("iid = '$product_info[iid]'");
$invoice_update = array(
"products_amount" => $_SESSION['products_amount'],
"total" => $_SESSION['total']
);
$minvoice->updateInvoice($invoice_update);
}
redirect("index.php?controller=cart");
<file_sep><?php
$distid = $_GET['distid'];
$mcommune = new Model_Commune;
$data['commune'] = $mcommune->listCommuneByDistid($distid);
echo "<option value='0'>Chọn Xã/Phường</option>";
foreach ($data['commune'] as $item) {
echo "<option value='$item[commid]'>$item[name]</option>";
}
<file_sep><?php
class Model_Product extends Model{
protected $_table = "products";
public function addProduct($data){
$this->insert($this->_table, $data);
}
public function listProduct(){
$this->getData($this->_table);
return $this->fetchAll();
}
public function deleteProduct($id){
$this->where("pid = '$id'");
$this->delete($this->_table);
}
public function getProductById($id){
$this->where("pid = '$id'");
$this->getData($this->_table);
return $this->fetch();
}
public function checkProduct($data = ""){
if(is_array($data)){
$this->where($data);
}
$this->getData($this->_table);
if($this->num_rows() == 1){
return false;
}else{
return true;
}
}
public function updateProduct($data){
$this->update($this->_table, $data);
}
public function updateProductAmount($id, $amount, $change){
$this->select("quantity");
$data = $this->getProductById($id);
if($change == "up"){
$data['quantity'] += $amount;
}else{
$data['quantity'] -= $amount;
}
$input_data = array("quantity" => $data['quantity']);
$this->updateProduct($input_data);
}
public function updateAfterOrder($pid, $quantity){
$this->select("quantity, sold, oeid");
$output = $this->getProductById($pid);
$output['quantity'] -= $quantity;
$output['sold'] += $quantity;
$update_data = array("quantity" => $output['quantity'], "sold" => $output['sold']);
$this->updateProduct($update_data);
return $output['oeid'];
}
public function updateAfterAcceptRemark($pid, $score){
$this->select("rating, rating_times");
$current_status = $this->getProductById($pid);
$new_times = $current_status['rating_times'] + 1;
$new_total_score = $current_status['rating_times'] * $current_status['rating'] + $score;
$new_score = round($new_total_score / $new_times);
$update_data = array("rating" => $new_score, "rating_times" => $new_times);
$this->updateProduct($update_data);
}
public function searchProduct($keyword){
$this->select("pid, name, price, image");
$this->where("name LIKE '%$keyword%'");
$this->getData($this->_table);
return $this->fetchAll();
}
public function countProductsType() {
$this->getData($this->_table);
return $this->num_rows();
}
public function statProduct() {
$this->getData($this->_table);
return $this->fetch();
}
}
<file_sep><?php
$pid = $_GET['pid'];
$data = "";
$data['current_page'] = $_GET['page'];
$mproduct = new Model_Product;
$meffect = new Model_Effect;
$meffect->select("oeid, content");
$data['effect'] = $meffect->listEffect();
$data['product'] = $mproduct->getProductById($pid);
if(isset($_POST['ok'])){
$name = $outstanding_effect = $packing_method = $price = $image = $description = "";
if(empty($_POST['txtname'])){
$data['error'][] = "Vui lòng không xoá TÊN";
}else{
$name = $_POST['txtname'];
}
$outstanding_effect = $_POST['outstanding_effect'];
$packing_method = $_POST['packing_method'];
if(empty($_POST['price'])){
$data['error'][] = "Vui lòng không xoá GIÁ";
}else{
$price = $_POST['price'];
}
if(!empty($_FILES['image']['name'])){
$image = $_FILES['image']['name'];
}else{
$image = "none";
}
if(empty($_POST['description'])){
$data['error'][] = "Vui lòng không xoá MÔ TẢ CHI TIẾT";
}else{
$description = $_POST['description'];
}
if($name && $outstanding_effect && $packing_method && $price && $image && $description){
$check_data = array(
"name =" => $name,
"pid <>" => $pid
);
$mproduct->select("pid");
if($mproduct->checkProduct($check_data) == true){
$mproduct->select("price");
$old_price = $mproduct->getProductById($pid);
$input_data = array(
"name" => $name,
"packing_method" => $packing_method,
"description" => $description
);
if ($old_price['price'] != $price) {
$input_data['price'] = $price;
$price_diff = $price - $old_price['price'];
// update invoices table and invoice_details table
$minvoice = new Model_Invoice;
$minvoice->select("iid, total");
$minvoice->where("status = '1'");
$invoices_data = $minvoice->listInvoice();
$minvoicedetail = new Model_InvoiceDetail;
$update_invoice_detail = array("price" => $price);
foreach ($invoices_data as $item) {
$minvoicedetail->where(array("iid =" => $item['iid'], "pid =" => $pid));
$product_quantity_in_cart = $minvoicedetail->getQuantity();
if (!empty($product_quantity_in_cart)) {
$minvoicedetail->updateInvoiceDetail($update_invoice_detail);
$new_total = $item['total'] + $price_diff * $product_quantity_in_cart['quantity'];
$minvoice->where(array("iid =" => $item['iid'], "status =" => "1"));
$update_invoice = array("total" => $new_total);
$minvoice->updateInvoice($update_invoice);
}
}
}
if($image != "none"){
$input_data['image'] = $image;
move_uploaded_file($_FILES['image']['tmp_name'], "assets/images/products/".$_FILES['image']['name']);
}
if($outstanding_effect != $data['product']['oeid']){
$input_data['oeid'] = $outstanding_effect;
$meffect->changeAmountWhenEditProduct($data['product']['oeid'], $data['product']['quantity'], $outstanding_effect);
}
$mproduct->where("pid = '$pid'");
$mproduct->updateProduct($input_data);
redirect("index.php?controller=salesmanager&resources=product&page=$data[current_page]");
}else{
$data['error'][] = "TRÙNG TÊN với sản phẩm khác";
}
}
}
$data['title_tag'] = "Chỉnh sửa sản phẩm";
loadview("salesmanager/product/edit", $data);
<file_sep><div id="salesmanager_mainpage_wrapper">
<div id="left_content">
<div id="left_menu">
<ul>
<li><a href="index.php?controller=salesmanager">Trang chính</a></li>
<li><a href="javascript:void(0)">Trà thảo dược</a>
<ul class="submenu">
<li><a href="index.php?controller=salesmanager&resources=product">Kho hàng</a></li>
<li><a href="index.php?controller=salesmanager&resources=effect">Công dụng nổi bật</a></li>
<li><a href="index.php?controller=salesmanager&resources=invoice">Đơn hàng</a></li>
</ul>
</li>
<li><a href="index.php?controller=salesmanager&resources=news">Tin tức</a></li>
<li><a href="index.php?controller=salesmanager&resources=ask_and_answer">Hỏi đáp</a></li>
<li><a href="index.php?controller=salesmanager&resources=remark">Ý kiến người dùng</a></li>
</ul>
</div>
<script type="text/javascript">
$(document).ready(function(){
$("#left_menu > ul > li > a").hover(function(){
//$(this).next(".submenu").slideToggle();
});
});
</script>
</div>
<div id="right_content" style="min-height: 489px;">
<div id="sub_navbar">
<ul>
<li><a href="index.php?controller=salesmanager">Trang chính</a></li>
<?php
if(isset($_GET['resources'])){
switch($_GET['resources']){
case "product": echo "<li><a href='index.php?controller=salesmanager&resources=product'>> Kho hàng</a></li>"; break;
case "effect": echo "<li><a href='index.php?controller=salesmanager&resources=effect'>> Công dụng nổi bật</a></li>"; break;
case "invoice": echo "<li><a href='index.php?controller=salesmanager&resources=invoice'>> Đơn hàng</a></li>"; break;
case "news": echo "<li><a href='index.php?controller=salesmanager&resources=news'>> Tin tức</a></li>"; break;
case "remark": echo "<li><a href='index.php?controller=salesmanager&resources=remark'>> Ý kiến người dùng</a></li>"; break;
case "ask_and_answer": echo "<li><a href='index.php?controller=salesmanager&resources=ask_and_answer'>> Hỏi đáp</a></li>"; break;
}
}
if(isset($_GET['action'])){
switch($_GET['action']){
case "new": echo "<li>> Thêm</li>"; break;
case "edit": echo "<li>> Sửa</li>"; break;
case "quantity_update": echo "<li>> Cập nhật số lượng</li>"; break;
case "show": echo "<li>> Xem chi tiết</li>"; break;
case "answer": echo "<li>> Trả lời</li>"; break;
}
}
?>
</ul>
</div>
<div class="clr"></div>
<div id="right_content_detail">
<file_sep><?php
$idid = $_GET['idid'];
$new_quantity = $_POST['quantity'];
$minvoicedetail = new Model_InvoiceDetail;
$minvoicedetail->select("price, quantity, iid");
$current_product = $minvoicedetail->getInvoiceDetailById($idid);
$changed_amount = $new_quantity - $current_product['quantity'];
// cap nhat chi tiet hoa don
$detail_update = array("quantity" => $new_quantity);
$minvoicedetail->updateInvoiceDetail($detail_update);
// cap nhat hoa don
$minvoice = new Model_Invoice;
$_SESSION['products_amount'] += $changed_amount;
$_SESSION['total'] += $changed_amount * $current_product['price'];
$invoice_update = array(
"products_amount" => $_SESSION['products_amount'],
"total" => $_SESSION['total']
);
$minvoice->where("iid = '$current_product[iid]'");
$minvoice->updateInvoice($invoice_update);
redirect("index.php?controller=cart");
<file_sep><?php
loadview("layouts/header", $data);
?>
<div id="my_invoices_list" style="min-height: 242px;">
<p>Danh sách đơn hàng của bạn</p>
<table class='table table-bordered table-hover' style='width: 650px; margin-bottom: 30px;'>
<thead>
<tr>
<th style='width: 100px;'>Mã đơn hàng</th>
<th>Thời điểm đặt hàng</th>
<th style='width: 150px;'>Số lượng sản phẩm</th>
<th>Tổng cộng</th>
<th style='width: 160px;'>Trạng thái</th>
</tr>
</thead>
<tbody>
<?php
if(!empty($data['invoices'])) {
foreach ($data['invoices'] as $item) {
echo "<tr>";
echo "<td><a href='index.php?controller=user&resources=invoice&action=show&iid=$item[iid]'>$item[iid]</a></td>";
if (empty($item['order_date'])) {
echo "<td>cập nhật sau</td>";
} else {
echo "<td>".date("d/m/Y", strtotime($item['order_date']))."</td>";
}
echo "<td>".number_format($item['products_amount'])."</td>";
echo "<td>".number_format($item['total'])." ₫</td>";
if ($item['status'] == 1) {
echo "<td class='warning'>Đang mua hàng</td>";
} elseif ($item['status'] == 2) {
echo "<td class='bg-primary'>Đặt hàng thành công</td>";
} elseif ($item['status'] == 3) {
echo "<td class='info'>Đang xử lý</td>";
} elseif ($item['status'] == 4) {
echo "<td class='success'>Giao hàng thành công</td>";
}
echo "</tr>";
}
} else {
echo "<tr>";
echo "<td colspan='5'>Chưa có đơn hàng nào</td>";
echo "</tr>";
}
?>
</tbody>
</table>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
loadview("layouts/header", $data);
?>
<script type="text/javascript">
$(document).ready(function(){
$("#via_atm").change(function(){
$(".atm_account_info").slideDown();
});
$("#in_place").change(function(){
$(".atm_account_info").slideUp();
});
});
</script>
<div id="cart_payment">
<div id="payment_method">
<p style="font-size: 12pt; font-weight: bold;">Bước 3. Chọn hình thức thanh toán</p>
<div id="type_of_payment_method">
<form action="index.php?controller=cart&action=payment" method="post">
<table class="table-hover">
<tr>
<td style="padding: 0px 5px;"><input type="radio" name="payment_method" value="1" id="in_place"></td>
<td style="padding: 0px 5px;"><label for="in_place">Thanh toán khi nhận hàng</label></td>
</tr>
<tr>
<td style="padding: 0px 5px;"><input type="radio" name="payment_method" value="2" id="via_atm" <?php if(!empty($data['atm'])) echo "checked='checked'"; ?>></td>
<td style="padding: 0px 5px;"><label for="via_atm">Thanh toán qua thẻ ATM</label></td>
</tr>
<tr>
<td colspan="2" style="padding-left: 70px;">
<div class="atm_account_info" <?php if(!empty($data['atm'])) echo "style='display: block;'"; ?>>
<table>
<tr>
<td>Tên chủ tài khoản</td>
<td><input type="text" name="account_holder" class="form-control" style="width: 230px;"></td>
</tr>
<tr>
<td>Số tài khoản</td>
<td><input type="text" name="account_number" class="form-control" style="width: 230px;"></td>
</tr>
<tr>
<td><NAME></td>
<td><input type="text" name="bank" class="form-control" style="width: 230px;"></td>
</tr>
</table>
</div>
</td>
</tr>
<tr>
<td colspan="2"><input type="submit" name="ok" class="btn btn-danger" style="padding: 10px 30px;" value="ĐẶT MUA"> (Vui lòng kiểm tra lại đơn hàng trước khi đặt mua)</td>
</tr>
</table>
<?php
echo "<input type='hidden' name='addrid' value='".$data['data']['addrid']."'>";
echo "<input type='hidden' name='fullname' value='".$data['data']['fullname']."'>";
echo "<input type='hidden' name='address' value='".$data['data']['address']."'>";
echo "<input type='hidden' name='comm_name' value='".$data['data']['comm_name']."'>";
echo "<input type='hidden' name='dist_name' value='".$data['data']['dist_name']."'>";
echo "<input type='hidden' name='prov_name' value='".$data['data']['prov_name']."'>";
echo "<input type='hidden' name='telephone' value='".$data['data']['telephone']."'>";
?>
</form>
</div>
<div class="error">
<?php
if(!empty($data['error'])) {
echo "<ul>";
foreach ($data['error'] as $item) {
echo "<li>$item</li>";
}
echo "</ul>";
}
?>
</div>
</div>
<div id="addr_invoice_detail">
<div class="addr_info">
<p style="font-weight: bold; font-size: 11pt;"> 2. Địa chỉ giao hàng</p>
<a href="index.php?controller=cart&action=shipping"><span>Sửa</span></a>
<?php
echo "<p style='font-weight: bold; font-size: 12pt;'>".$data['data']['fullname']."</p>";
echo "<p>Địa chỉ: ".$data['data']['address'].", ".$data['data']['comm_name'].", ".$data['data']['dist_name'].", ".$data['data']['prov_name']."</p>";
echo "<p>Số điện thoại: ".$data['data']['telephone']."</p>";
?>
</div>
<div class="invoice_detail_info">
<p style="font-weight: bold; font-size: 11pt;">1. Giỏ hàng (<?php echo $_SESSION['products_amount']; ?> sản phẩm)</p>
<a href="index.php?controller=cart"><span style="font-weight: normal;">Sửa</span></a>
<table style="margin-left: 50px;">
<?php
foreach ($data['product'] as $item) {
echo "<tr>";
echo "<td style='width: 150px;'><span>$item[quantity] x</span> <a href='index.php?controller=product&action=show&pid=$item[pid]' class='product_in_cart'>$item[name]</a></td>";
echo "<td>".number_format($item['price'] * $item['quantity'])." ₫</td>";
echo "</tr>";
}
?>
<tr>
<td><span>Tổng cộng</span></td>
<td><span style="font-size: 13pt; color: #f00;"><?php echo number_format($_SESSION['total']); ?> ₫</span></td>
</tr>
</table>
</div>
</div>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
loadview("layouts/header", $data);
?>
<div id="cart_shipping" style="min-height: 257px;">
<p style="font-size: 12pt; font-weight: bold;">Bước 2. Chọn địa chỉ giao hàng</p>
<?php
if (!empty($data['addr'])) {
foreach ($data['addr'] as $item) {
echo "<div class='shipping_address'>";
echo "<form action='index.php?controller=cart&action=payment' method='post'>";
echo "<p style='font-weight: bold; font-size: 11pt;'>$item[fullname]</p>";
echo "<p>Địa chỉ: $item[address], $item[comm_name], $item[dist_name], $item[prov_name]</p>";
echo "<p>Số điện thoại: $item[telephone]</p>";
echo "<input type='hidden' name='addrid' value='$item[addrid]'>";
echo "<input type='hidden' name='fullname' value='$item[fullname]'>";
echo "<input type='hidden' name='address' value='$item[address]'>";
echo "<input type='hidden' name='comm_name' value='$item[comm_name]'>";
echo "<input type='hidden' name='dist_name' value='$item[dist_name]'>";
echo "<input type='hidden' name='prov_name' value='$item[prov_name]'>";
echo "<input type='hidden' name='telephone' value='$item[telephone]'>";
echo "<input type='submit' class='btn' value='Giao hàng đến địa chỉ này'>";
echo "</form>";
echo "</div>";
}
echo "<div class='clr'></div>";
echo "<p style='margin-left: 20px;'>Chỉnh sửa sổ địa chỉ <a href='index.php?controller=user&uid=$_SESSION[uid]'>tại đây</a></p>";
} else {
echo "<p id='no_addr'>Bạn chưa có địa chỉ giao hàng. Vui lòng <a href='index.php?controller=user&resources=address&action=new'>tạo sổ địa chỉ mới</a>.</p>";
}
?>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$data = "";
if(isset($_POST['ok'])){
$email = $pass = "";
if(empty($_POST['txtemail'])){
$data['error'][] = "Email không được để trống";
}else{
$email = $_POST['txtemail'];
// $email = addslashes($_POST['txtemail']); // xu ly o php
// $email = mysql_escape_string($_POST['txtemail']); // xu ly o php
}
if(empty($_POST['txtpass'])){
$data['error'][] = "Mật khẩu không được để trống";
}else{
$pass = $_POST['txtpass'];
}
if($email && $pass){
$pass = md5($pass);
$muser = new Model_User;
$email = mysql_real_escape_string($email); // xu ly o mysql, sau khi da ket noi db
$arr = array("email =" => $email, "password =" => $pass);
$muser->where($arr);
if($muser->checkUser() == false){
$info = $muser->fetch();
$_SESSION['uid'] = $info['uid'];
$_SESSION['avatar'] = $info['avatar'];
$_SESSION['name'] = $info['name'];
$_SESSION['level'] = $info['level'];
if($_SESSION['level'] == 1){
$minvoice = new Model_Invoice;
$cart_info = $minvoice->checkAfterLogin($_SESSION['uid']);
if($cart_info == false){
// chua co gio hang moi
$_SESSION['iid'] = 0;
$_SESSION['products_amount'] = 0;
$_SESSION['total'] = 0;
}else{
// co gio hang chua thanh toan
$_SESSION['iid'] = $cart_info['iid'];
$_SESSION['products_amount'] = $cart_info['products_amount'];
$_SESSION['total'] = $cart_info['total'];
}
redirect("http://localhost/www/herbal_tea/");
}elseif($_SESSION['level'] == 2){
redirect("http://localhost/www/herbal_tea/index.php?controller=salesmanager");
}else{
redirect("http://localhost/www/herbal_tea/index.php?controller=admin");
}
}else{
$data['error'][] = "Email hoặc mật khẩu không chính xác";
}
}
}
$data['title_tag'] = "Đăng nhập";
loadview("sessions/new", $data);
<file_sep><?php
class Model_Province extends Model{
protected $_table = "provinces";
public function listProvince(){
$this->getData($this->_table);
return $this->fetchAll();
}
public function getProvinceById($id){
$this->where("provid = '$id'");
$this->getData($this->_table);
return $this->fetch();
}
}
<file_sep><?php
loadview("layouts/header", $data);
?>
<div>
<form id="signup_form" action="index.php?controller=user&action=signup" method="post">
<?php
if(!empty($data['error'])){
echo "<div class='error'>";
echo "<ul>";
foreach($data['error'] as $err){
echo "<li>$err</li>";
}
echo "</ul>";
echo "</div>";
}
?>
<table>
<tr>
<td>Tên người dùng <span style='color: red;'>*</span></td>
<td style="width: 300px;"><input type="text" name="txtuser" class="form-control" id="signup_txtuser"></td>
</tr>
<tr>
<td>Email <span style='color: red;'>*</span></td>
<td style="width: 300px;"><input type="text" name="txtemail" class="form-control" id="signup_txtemail"></td>
</tr>
<tr>
<td>Mật khẩu <span style='color: red;'>*</span></td>
<td style="width: 300px;"><input type="password" name="tx<PASSWORD>" class="form-control" id="signup_txtpass"></td>
</tr>
<tr>
<td>Xác nhận mật khẩu <span style='color: red;'>*</span></td>
<td style="width: 300px;"><input type="password" name="tx<PASSWORD>" class="form-control" id="signup_txtpass2"></td>
</tr>
<tr>
<td></td>
<td><input type="submit" name="ok" value="Đăng ký" class="btn btn-info" id="signup_ok"></td>
</tr>
<tr>
<td></td>
<td>Đã có tài khoản? <a href="index.php?controller=session&action=new">Đăng nhập</a></td>
</tr>
</table>
</form>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
class Model_Remark extends Model{
protected $_table = "remarks";
public function addRemark($data){
$this->insert($this->_table, $data);
}
public function getRemarkByPid($pid){
$condition = array("pid=" => $pid, "is_approved=" => "1");
$this->where($condition);
$this->getData($this->_table);
return $this->fetchAll();
}
public function listRemark(){
$this->getData($this->_table);
return $this->fetchAll();
}
public function updateRemark($data){
$this->update($this->_table, $data);
}
public function getRemarkByRemid($remid){
$this->where("remid = '$remid'");
$this->getData($this->_table);
return $this->fetch();
}
public function countRemarkByUid($uid) {
$this->where("uid = '$uid'");
$this->getData($this->_table);
return $this->num_rows();
}
}
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<fieldset id="view_statistics">
<legend>Tóm tắt tình hình kinh doanh</legend>
<div class='stat_revenue'>
<p>* Doanh thu tháng này: <span style="font-weight: bold; color: red;"><?php echo number_format($data['avenue']['current_month_total']['sum(total)']); ?> ₫</span></p>
<p>* Tổng doanh thu: <span style="font-weight: bold;"><?php echo number_format($data['avenue']['total']['sum(total)']); ?> ₫</span></p>
</div>
<div class='stat_accounts'>
<table>
<tr>
<td>* Hệ thống hiện có <span style='font-weight: bold;'><?php echo number_format($data['user']['all']); ?></span> tài khoản, bao gồm:</td>
</tr>
<tr>
<td>
<ul style='margin-left: 30px;'>
<li><?php echo number_format($data['user']['member']); ?> <span style='font-weight: bold;'>thành viên</span></li>
<li><?php echo number_format($data['user']['salesmanager']); ?> <span style='font-weight: bold; color: blue;'>quản lý bán hàng</span></li>
<li><?php echo number_format($data['user']['admin']); ?> <span style='font-weight: bold; color: red;'>quản trị viên</span></li>
</ul>
</td>
</tr>
</table>
</div>
<div class='stat_products'>
<table>
<tr>
<td>* Thông tin sản phẩm</td>
</tr>
<tr>
<td>
<ul style='margin-left: 30px;'>
<li>Số loại sản phẩm: <?php echo number_format($data['product']['types_amount']); ?></li>
<li>Hiện có: <?php echo number_format($data['product']['is_present_amount']['sum(quantity)']); ?></li>
<li>Đã bán: <?php echo number_format($data['product']['sold_amount']['sum(sold)']); ?></li>
</ul>
</td>
</tr>
</table>
</div>
</fieldset>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
if(isset($_SESSION['level']) && ($_SESSION['level'] == 3)){
if(isset($_GET['resources'])){
switch($_GET['resources']){
case "user": require("controllers/admin/user/user.php"); break;
}
}else{
require("controllers/admin/user/index.php");
}
}else{
if(isset($_SESSION['level']) && ($_SESSION['level'] == 2)){
redirect("http://localhost/www/herbal_tea/index.php?controller=salesmanager");
}else{
redirect("http://localhost/www/herbal_tea/");
}
}
<file_sep><?php
loadview("layouts/header", $data);
?>
<div id="show_news" style="min-height: 252px;">
<?php
echo "<h1 style='font-size: 20pt;'>".$data['news']['title']."</h1>";
$timestamp = strtotime($data['news']['created_at']);
echo "<p>Đăng ngày ".date("d/m/Y", $timestamp)."</p>";
echo "<div id='news_content'>";
echo $data['news']['content'];
echo "</div>";
?>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
if(isset($_GET['action'])) {
switch ($_GET['action']) {
case "new": require("controllers/ask_and_answer/new.php"); break;
case "index": require("controllers/ask_and_answer/index.php"); break;
}
} else {
require("controllers/ask_and_answer/index.php");
}
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<div id="add_edit_product_interface">
<form action="index.php?controller=salesmanager&resources=product&action=new" method="post" enctype="multipart/form-data">
<table>
<tr>
<td style="width: 130px;">Tên sản phẩm</td>
<td><input type="text" name="txtname" class="form-control" style="width: 400px;" /></td>
</tr>
<tr>
<td>Công dụng nổi bật</td>
<td>
<select name="outstanding_effect" class="form-control" style="width: 400px;">
<?php
foreach($data['data'] as $item){
echo "<option value='$item[oeid]'>$item[content]</option>";
}
?>
</select>
</td>
</tr>
<tr>
<td>Quy cách đóng gói</td>
<td>
<select name="packing_method" class="form-control" style="width: 150px;">
<option value='1'>Lọ thuỷ tinh</option>
<option value='2'>Gói to</option>
<option value='3'>Gói nhỏ</option>
</select>
</td>
</tr>
<tr>
<td>Số lượng</td>
<td><input type="text" name="quantity" class="form-control" style="width: 90px;" /></td>
</tr>
<tr>
<td>Giá</td>
<td><input type="text" name="price" class="form-control" style="width: 90px; float: left;" /> <span style="float: left; padding: 7px;">đồng</span></td>
</tr>
<tr>
<td>Hình ảnh</td>
<td><input type="file" name="image" /></td>
</tr>
<tr>
<td>Mô tả chi tiết</td>
<td>
<textarea rows="15" cols="70" class="form-control" style="resize: none;" name="description"></textarea>
</td>
</tr>
<script type="text/javascript">
CKEDITOR.replace('description');
</script>
<tr>
<td></td>
<td><input type="submit" name="ok" value="Thêm sản phẩm mới" class="btn btn-primary" /></td>
</tr>
</table>
</form>
<div class="error">
<?php
if(!empty($data['error'])){
echo "<ul>";
foreach($data['error'] as $err){
echo "<li>$err</li>";
}
echo "</ul>";
}
?>
</div>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$data = "";
$uid = $_GET['uid'];
$muser = new Model_User;
$muser->where("uid = '$uid'");
$data['data'] = $muser->showUser();
$maddressregister = new Model_AddressRegister;
$mcommune = new Model_Commune;
$mdistrict = new Model_District;
$mprovince = new Model_Province;
$data['addr'] = $maddressregister->listAddressRegisterByUid($uid);
if($data['addr'] != "") {
$i = 0;
foreach ($data['addr'] as $item){
$comm_info = $mcommune->getCommuneById($item['commid']);
$data['addr'][$i]['comm_name'] = $comm_info['name'];
$dist_info = $mdistrict->getDistrictById($comm_info['distid']);
$data['addr'][$i]['dist_name'] = $dist_info['name'];
$prov_info = $mprovince->getProvinceById($dist_info['provid']);
$data['addr'][$i]['prov_name'] = $prov_info['name'];
$i++;
}
}
if(isset($_POST['ok'])){
$name = $new_pass = $avatar = "";
if(empty($_POST['txtname'])){
$data['error'][] = "Tên người dùng không được để trống";
}else{
$name = $_POST['txtname'];
}
if(!empty($_POST['new_pass'])){
if(empty($_POST['old_pass'])){
$data['error'][] = "Vui lòng nhập mật khẩu cũ";
}else{
if(md5($_POST['old_pass']) != $data['data']['password']){
$data['error'][] = "Mật khẩu cũ không đúng";
}else{
if($_POST['new_pass'] != $_POST['renew_pass']){
$data['error'][] = "Mật khẩu mới và xác nhận mật khẩu mới không khớp";
}else{
$new_pass = $_POST['new_pass'];
}
}
}
}else{
$new_pass = "<PASSWORD>";
}
if(empty($_FILES['avatar']['name'])){
$avatar = "none";
}else{
$avatar = $_FILES['avatar']['name'];
}
if($name && $new_pass && $avatar){
$input_data = array(
"name" => $name
);
$_SESSION['name'] = $name;
if($new_pass != "none"){
$input_data['password'] = md5($new_<PASSWORD>);
}
if($avatar != "none"){
$input_data['avatar'] = $avatar;
$_SESSION['avatar'] = $avatar;
move_uploaded_file($_FILES['avatar']['tmp_name'], "assets/images/users/".$_FILES['avatar']['name']);
}
$muser->updateUser($input_data);
redirect("index.php?controller=user&uid=$uid");
}
}
$data['title_tag'] = "Tài khoản";
loadview("user/account", $data);
<file_sep><?php
if(isset($_GET['action'])){
switch($_GET['action']){
case "index": require("controllers/admin/user/index.php"); break;
case "destroy": require("controllers/admin/user/destroy.php"); break;
case "edit": require("controllers/admin/user/edit.php"); break;
case "index_ajax": require("controllers/admin/user/index_ajax.php"); break;
case "mdestroy": require("controllers/admin/user/mdestroy.php"); break;
}
}else{
require("controllers/admin/user/index.php");
}
<file_sep><?php
class Model_InvoiceDetail extends Model{
protected $_table = "invoice_details";
public function addInvoiceDetail($data){
$this->insert($this->_table, $data);
}
public function checkProductExistence($iid, $pid){
$check_data = array("iid =" => $iid, "pid =" => $pid);
$this->where($check_data);
$this->select("idid, quantity");
$this->getData($this->_table);
if($this->num_rows() == 1){
return $this->fetch();
}else{
return false;
}
}
public function updateInvoiceDetail($data){
$this->update($this->_table, $data);
}
public function listInvoiceDetail($iid){
$this->where("iid = '$iid'");
$this->getData($this->_table);
return $this->fetchAll();
}
public function getInvoiceDetailById($idid){
$this->where("idid = '$idid'");
$this->getData($this->_table);
return $this->fetch();
}
public function deleteInvoiceDetail($idid){
$this->where("idid = '$idid'");
$this->delete($this->_table);
}
public function getQuantity() {
$this->select("quantity");
$this->getData($this->_table);
return $this->fetch();
}
}
<file_sep><?php
$data = "";
$minvoice = new Model_Invoice;
$minvoice->select("iid, products_amount, total, order_date, status");
$minvoice->order("iid", "DESC");
$data['invoices'] = $minvoice->getInvoiceByUid($_SESSION['uid']);
$data['title_tag'] = "Danh sách đơn hàng thành viên";
loadview("user/invoice/index", $data);
<file_sep><?php
$oeid = $_GET['oeid'];
$meffect = new Model_Effect;
$meffect->deleteEffect($oeid);
redirect("index.php?controller=salesmanager&resources=effect&action=index");
<file_sep><?php
if(isset($_GET['action'])){
switch($_GET['action']){
case "index": require("controllers/product/index.php"); break;
case "show": require("controllers/product/show.php"); break;
case "search": require("controllers/product/search.php"); break;
}
}else{
require("controllers/product/index.php");
}
<file_sep><?php
loadview("layouts/header");
?>
<div id="success_order">
<p>Đặt hàng thành công!</p>
<p>Cảm ơn bạn đã lựa chọn sản phẩm của chúng tôi.</p>
<p style="margin-bottom: 95px;">Chúng tôi sẽ liên lạc qua điện thoại trong vòng 24 giờ để xác thực thông tin và giao hàng đến quý khách.</p>
<p><a href="index.php" class="btn btn-default">Chuyển đến trang chủ</a><span style="display: inline-block; width: 50px;"></span><a href="index.php?controller=product" class="btn btn-default">Tiếp tục mua sắm</a></p>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<div id="question_answer_list">
<table class="table table-hover table-bordered">
<thead>
<tr>
<th style="width: 60px;">STT</th>
<th style="width: 110px;">Thời điểm hỏi</th>
<th style="width: 300px;">Câu hỏi</th>
<th>Câu trả lời</th>
<th style="width: 70px;">Trả lời</th>
</tr>
</thead>
<tbody>
<?php
if(empty($data['data'])) {
echo "<tr>";
echo "<td colspan='5'>Chưa có dữ liệu</td>";
echo "</tr>";
} else {
$stt = 1;
foreach ($data['data'] as $item) {
echo "<tr>";
echo "<td>$stt</td>";
$timestamp = date("d/m/Y", strtotime($item['created_at']));
echo "<td>$timestamp</td>";
echo "<td style='text-align: justify;'>$item[content]</td>";
if (empty($item['answer'])) {
echo "<td>N/A</td>";
echo "<td><a href='index.php?controller=salesmanager&resources=ask_and_answer&action=answer&qid=$item[qid]'><span class='reply'></span></a></td>";
} else {
echo "<td style='text-align: justify;'>$item[answer]</td>";
echo "<td></td>";
}
echo "</tr>";
$stt++;
}
}
?>
</tbody>
</table>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep>function check_delete(){
if(!window.confirm("Chắc chắn muốn xoá thành viên này?")) return false;
}
function check_change_level(){
if(!window.confirm("Chắc chắn muốn chuyển đổi loại tài khoản?")) return false;
}
$(document).ready(function(){
$("#users_filter").change(function(){
level = $(this).val();
$.ajax({
url:"index.php?controller=admin&resources=user&action=index_ajax",
type:"get",
data:"level="+level,
async:true,
success:function(result){
$("#users_list").html(result);
}
});
return false;
});
countu = 0;
$("input[type='checkbox']").click(function(){
order = $(this).attr("data-old-order");
is_check = $(this).prop("checked");
if (is_check == true) {
countu++;
$(this).closest("tr").css("background", "#FCD79F");
$("#delete_all").removeAttr("disabled");
$(this).attr("checked", "checked");
$(this).attr("data-id");
$(this).attr("data-new-order", order);
$("#delete_all").attr("href", "#");
} else {
countu--;
$(this).closest("tr").css("background", "#fff");
$(this).removeAttr("checked");
$(this).attr("data-new-order", "");
if (countu == 0) {
$("#delete_all").attr("disabled", "disabled").attr("href", "javascript:void(0)");
}
}
})
$("#delete_all").click(function(){
a = $(this).attr("href");
if (a != "javascript:void(0)") {
// xoa nhieu user
list_user = "";
j = 1;
for (i=1; i<8; i++) {
userid = $("tbody input[data-new-order='"+i+"']").attr("data-id");
if (userid != undefined) {
if (j == countu) {
list_user = list_user+"\""+i+"\":\""+userid+"\"";
} else {
list_user = list_user+"\""+i+"\":\""+userid+"\",";
}
j++;
}
}
list_user = "{"+list_user+"}";
cf = "";
if (countu == 1) {
cf = "Bạn chắc chắn muốn xoá tài khoản này?";
} else {
cf = "Bạn chắc chắn muốn xoá "+countu+" tài khoản này?";
}
if (!window.confirm(cf)) {
return false;
} else {
cpage = $("table").attr("data-page");
$(this).attr("href", "http://localhost/www/herbal_tea/index.php?controller=admin&resources=user&action=destroy&data="+list_user+"&page="+cpage);
}
}
})
});
<file_sep># Webshop_2016
Construct e-commerce system
Product: herbal tea
<file_sep><?php
loadview("layouts/header", $data);
?>
<script type="text/javascript">
$(document).ready(function(){
$('.push_product').click(function(){
current_value = $(this).next('input[type=text]').val();
$(this).next('input[type=text]').val(++current_value);
});
$('.pop_product').click(function(){
current_value = $(this).prev('input[type=text]').val();
$(this).prev('input[type=text]').val(--current_value);
});
});
function check_delete_product(){
if(!window.confirm('Bạn chắc chắn muốn xoá sản phẩm này khỏi giỏ hàng?')) return false;
}
function change_text_amount(id) {
var pattern = /^[0-9]+$/;
var old_value = document.getElementById("hidden"+id).value;
var new_value = document.getElementById(id).value;
if (pattern.test(new_value) == false) {
alert("Số lượng thay đổi không hợp lệ");
document.getElementById(id).value = old_value;
return false;
} else {
if (new_value == 0) {
alert("Số lượng sản phẩm phải lớn hơn 0");
document.getElementById(id).value = old_value;
return false;
} else {
return true;
}
}
}
</script>
<div id="my_cart" style="min-height: 252px;">
<div id="pending_product">
<span>
<b>Giỏ hàng</b> (
<?php
if(isset($_SESSION['products_amount'])){
echo number_format($_SESSION['products_amount']);
}else{
echo "0";
}
?>
sản phẩm)
</span>
<?php
if(isset($_SESSION['level'])){
if($_SESSION['products_amount'] > 0){
echo "<table class='table'>";
echo "<tr>";
echo "<td class='first_row' style='width: 160px;'></td>";
echo "<td class='first_row'></td>";
echo "<td class='first_row' style='width: 150px;'>Giá mua</td>";
echo "<td class='first_row' style='width: 140px;'>Số lượng</td>";
echo "</tr>";
foreach($data['detail'] as $item){
echo "<tr>";
echo "<td><img src='assets/images/products/$item[image]' /></td>";
echo "<td class='name_and_delete'>";
echo "<h2><a href='index.php?controller=product&action=show&pid=$item[pid]'>$item[name]</a></h2>";
echo "<a href='index.php?controller=cart&action=destroy_product&idid=$item[idid]' onclick='return check_delete_product();'><span class='icon_delete'>Xoá</span></a><br>";
if ($item['check'] != -1) {
if ($item['check'] > 0) {
echo "<p style='color: #fff; background: brown; padding: 5px; margin-top: 10px; border-radius: 5px; display: inline-block;'>Chỉ còn $item[check] sản phẩm</p>";
} else {
echo "<p style='color: #fff; background: #B8860B; padding: 5px; margin-top: 10px; border-radius: 5px; display: inline-block;'>Hết hàng</p>";
}
}
echo "</td>";
echo "<td class='net_price'>".number_format($item['price'])." ₫</td>";
echo "<td style='padding: 20px 0;'>";
echo "<form action='index.php?controller=cart&action=edit&idid=$item[idid]' method='post'>";
if($item['quantity'] < 10){
echo "<select class='form-control' name='quantity' onchange='this.form.submit();'>";
for($i = 1; $i < 10; $i++){
if($item['quantity'] == $i){
echo "<option value='$i' selected='selected'>$i</option>";
}else{
echo "<option value='$i'>$i</option>";
}
}
echo "<option value='10'>10+</option>";
echo "</select>";
}else{
echo "<input type='submit' value='' class='push_product' />";
echo "<input type='text' name='quantity' value='$item[quantity]' id='$item[idid]' onchange='if(change_text_amount($item[idid])) this.form.submit();' class='form-control' style='width: 60px; float: left;' />";
echo "<input type='submit' value='' class='pop_product' />";
echo "<input type='hidden' value='$item[quantity]' id='hidden".$item['idid']."'>";
}
echo "</form>";
echo "</td>";
echo "</tr>";
}
echo "</table>";
}
}
?>
</div>
<div id="make_order">
<?php
if(isset($_SESSION['level']) && ($_SESSION['products_amount'] > 0)){
if ($_SESSION['is_remain'] == 0) {
echo "<a href='index.php?controller=cart&action=shipping' class='btn btn-danger' >TIẾN HÀNH ĐẶT HÀNG</a>";
} else {
echo "<a href='javascript:void(0);' class='btn btn-danger' disabled >TIẾN HÀNH ĐẶT HÀNG</a>";
echo "<p style='font-size:12pt; margin-top:10px;'>Giỏ hàng có <b>$_SESSION[is_remain]</b> loại sản phẩm không đủ số lượng đáp ứng</p>";
}
}
?>
</div>
<div class="clr"></div>
<div id="continue_buying">
<a href="index.php?controller=product" class="btn btn-default">Tiếp tục mua sắm</a>
</div>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
loadview("layouts/header", $data);
loadview("user/address/form", $data);
loadview("layouts/footer");
?>
<file_sep><?php
$data = "";
$mprovince = new Model_Province;
$data['province'] = $mprovince->listProvince();
if(isset($_POST['ok'])){
$uid = $_GET['uid'];
$fullname = $telephone = $commune = $address = "";
if(empty($_POST['fullname'])){
$data['error'][] = "Chưa nhập họ tên";
}else{
$fullname = $_POST['fullname'];
}
if(empty($_POST['telephone'])){
$data['error'][] = "Chưa nhập số điện thoại";
}else{
$telephone = $_POST['telephone'];
}
if($_POST['province'] == 0){
$data['error'][] = "Chưa chọn tỉnh/thành";
}
if($_POST['district'] == 0){
$data['error'][] = "Chưa chọn quận/huyện";
}
if($_POST['commune'] == 0){
$data['error'][] = "Chưa chọn xã/phường";
}else{
$commune = $_POST['commune'];
}
if(empty($_POST['address'])){
$data['error'][] = "Chưa nhập địa chỉ";
}else{
$address = $_POST['address'];
}
if($fullname && $telephone && $commune && $address) {
$input_data = array(
"fullname" => $fullname,
"telephone" => $telephone,
"address" => $address,
"commid" => $commune,
"uid" => $uid
);
$maddressregister = new Model_AddressRegister;
$maddressregister->addAddressRegister($input_data);
redirect("index.php?controller=user&uid=$uid");
}
}
$data['title_tag'] = "Tạo địa chỉ mới";
loadview("user/address/new", $data);
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<div id="list_invoice_detail">
<div id="left_list_invoice_detail">
<p><span style="font-weight: bold;">Mã đơn hàng:</span> <?php echo $data['invoice']['iid']; ?></p>
<table class="table table-hover table-bordered">
<thead>
<tr>
<th style="width: 50px;">STT</th>
<th style="width: 200px;">Tên sản phẩm</th>
<th style="width: 120px;">Số lượng</th>
<th>Thành tiền</th>
</tr>
</thead>
<tbody>
<?php
$stt = 1;
foreach ($data['invoice_detail'] as $item) {
echo "<tr>";
echo "<td>$stt</td>";
echo "<td>$item[name]</td>";
echo "<td>".number_format($item['quantity'])."</td>";
echo "<td>".number_format($item['quantity'] * $item['price'])." ₫</td>";
echo "</tr>";
$stt++;
}
?>
<tr style="font-weight: bold;">
<td colspan="2">Tổng cộng</td>
<td><?php echo number_format($data['invoice']['products_amount']); ?></td>
<td style="color: #f00;"><?php echo number_format($data['invoice']['total']); ?> ₫</td>
</tr>
</tbody>
</table>
</div>
<div id="right_list_invoice_detail">
<?php
$status = $data['invoice']['status'];
if ($status == 1) {
echo "<p>Trạng thái: <span class='in_buying'>đang mua hàng</span></p>";
} else {
switch ($status) {
case "2": echo "<p>Trạng thái: <span class='ordered'>đã đặt hàng</span></p>"; break;
case "3": echo "<p>Trạng thái: <span class='in_progressing'>đang xử lý</span></p>"; break;
case "4": echo "<p>Trạng thái: <span class='success_delivery'>giao hàng thành công</span></p>"; break;
}
$timestamp = strtotime($data['invoice']['order_date']);
echo "<p>Thời điểm đặt hàng: <span style='font-weight: normal;'>".date("H:i", $timestamp)." ngày ".date("d:m:Y", $timestamp)."</span></p>";
echo "<p>Địa chỉ giao hàng</p>";
echo "<div>";
echo "<p style='font-weight: bold; font-size: 12pt;'>".$data['addr']['fullname']."</p>";
echo "<p>Địa chỉ: ".$data['addr']['address'].", ".$data['addr']['comm_name'].", ".$data['addr']['dist_name'].", ".$data['addr']['prov_name']."</p>";
echo "<p style='margin-bottom: 0px;'>Số điện thoại: ".$data['addr']['telephone']."</p>";
echo "</div>";
if ($data['invoice']['payment_method'] == 1) {
echo "<p>Hình thức thanh toán: tiền mặt</p>";
} else {
echo "<p>Hình thức thanh toán: chuyển khoản</p>";
echo "<div>";
echo "<p>Tên chủ tài khoản: ".$data['invoice']['account_holder']."</p>";
echo "<p>Số thẻ: ".$data['invoice']['account_number']."</p>";
echo "<p style='margin-bottom: 0px;'>Ngân hàng: ".$data['invoice']['bank']."</p>";
echo "</div>";
}
}
?>
</div>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$data = "";
$nid = $_GET['nid'];
$mnews = new Model_News;
$data['news'] = $mnews->getNewsByNid($nid);
$data['title_tag'] = $data['news']['title'];
loadview("news/show", $data);
<file_sep><?php
$data = "";
$mquestion = new Model_Question;
$mquestion->where("is_responded = '1'");
$mquestion->order("qid", "DESC");
$data['qanda'] = $mquestion->listQuestion();
if(!empty($data['qanda'])) {
$manswer = new Model_Answer;
$i = 0;
foreach ($data['qanda'] as $item) {
$answer_info = $manswer->getAnswerByQid($item['qid']);
$data['qanda'][$i]['answer'] = $answer_info['content'];
$i++;
}
}
$data['title_tag'] = "Hỏi đáp - Tư vấn sức khoẻ";
loadview("ask_and_answer/index", $data);
<file_sep><?php
loadview("layouts/header", $data);
?>
<script type="text/javascript">
function add(){
var current_amount = document.getElementById("amount").value;
document.getElementById("amount").value = parseInt(current_amount) + 1;
}
function minus(){
var current_amount = document.getElementById("amount").value;
if(current_amount > 1){
document.getElementById("amount").value = parseInt(current_amount) - 1;
}
}
function getAmount(remain){
var pattern = /^[0-9]+$/;
var current_amount = document.getElementById("amount").value;
if (pattern.test(current_amount) == false) {
alert("Số lượng đặt mua không hợp lệ");
document.getElementById("amount").value = 1;
return false;
} else {
if (current_amount == 0) {
alert("Vui lòng đặt mua ít nhất 1 sản phẩm");
document.getElementById("amount").value = 1;
return false;
} else {
if (current_amount > remain) {
alert("Số lượng sản phẩm hiện có không đủ đáp ứng");
document.getElementById("amount").value = remain;
return false;
} else {
document.getElementById("hidden_amount").value = current_amount;
}
}
}
}
</script>
<div id="show_product">
<div id="product_image">
<img src="assets/images/products/<?php echo $data['product']['image']; ?>" />
</div>
<div id="product_abstract_info">
<table style="width: 300px;">
<tr>
<td colspan="2"><h1><?php echo $data['product']['name']; ?></h1></td>
</tr>
<tr>
<td colspan="2" style="color: green; font-weight: bold; font-size: 18pt;"><?php echo number_format($data['product']['price']); ?> ₫</td>
</tr>
<?php
if($data['product']['quantity'] == 0){
echo "<tr>";
echo "<td colspan='2'><span>Hết hàng</span></td>";
echo "</tr>";
}elseif(($data['product']['quantity'] > 0) && ($data['product']['quantity'] <= 15)){
echo "<tr>";
echo "<td colspan='2'>Chỉ còn ".$data['product']['quantity']." sản phẩm</td>";
echo "</tr>";
}
$rating_times = $data['product']['rating_times'];
echo "<tr>";
if ($rating_times == 0) {
echo "<td>";
for ($i=1; $i<6; $i++){
echo "<img src='assets/images/system/gray_star.png' style='width: 16px; height: 16px;'>";
}
echo "</td>";
echo "<td>(0 đánh giá)</td>";
} else {
$rating = $data['product']['rating'];
echo "<td>";
for ($i=1; $i<=$rating; $i++) {
echo "<img src='assets/images/system/star.png' style='width: 16px; height: 16px;'>";
}
for ($i=$rating+1; $i<6; $i++) {
echo "<img src='assets/images/system/gray_star.png' style='width: 16px; height: 16px;'>";
}
echo "</td>";
echo "<td>($rating_times đánh giá)</td>";
}
echo "</tr>";
?>
<?php
if(isset($_SESSION['level'])){
echo "<tr>";
echo "<td colspan='2' style='line-height: 34px;'>";
echo "Số lượng đặt mua";
if($data['product']['quantity'] == 0){
echo "<input type='button' id='minus' onclick='return minus();' disabled='disabled' />";
echo "<input type='text' id='amount' value='1' class='form-control' style='width: 60px; float: right;' disabled='disabled' />";
echo "<input type='button' id='add' onclick='return add();' disabled='disabled' />";
}else{
echo "<input type='button' id='minus' onclick='return minus();' />";
echo "<input type='text' id='amount' value='1' class='form-control' style='width: 60px; float: right;' />";
echo "<input type='button' id='add' onclick='return add();' />";
}
echo "</td>";
echo "</tr>";
echo "<tr>";
echo "<td colspan='2'>";
echo "<form action='index.php?controller=cart&action=add_product' method='post'>";
echo "<input type='hidden' name='uid' value='$_SESSION[uid]' />";
echo "<input type='hidden' name='pid' value='".$data['product']['pid']."' />";
echo "<input type='hidden' name='name' value='".$data['product']['name']."' />";
echo "<input type='hidden' name='quantity' id='hidden_amount' />";
echo "<input type='hidden' name='price' value='".$data['product']['price']."' />";
echo "<input type='hidden' name='image' value='".$data['product']['image']."' />";
if($data['product']['quantity'] == 0){
echo "<input type='submit' name='ok' value='Thêm vào giỏ hàng' class='btn btn-danger' disabled='disabled' />";
}else{
echo "<input type='submit' name='ok' value='Thêm vào giỏ hàng' onclick='return getAmount(".$data['product']['quantity'].");' class='btn btn-danger' />";
}
echo "</form>";
echo "</td>";
echo "</tr>";
}else{
echo "<tr>";
echo "<td colspan='2'><span id='login_for_buying'><a href='index.php?controller=session&action=new'>Vui lòng đăng nhập để mua hàng</a></span></td>";
echo "</tr>";
}
?>
</table>
</div>
<div class="clr"></div>
<div id="product_detail">
<span>Giới thiệu sản phẩm</span>
<div>
<?php
echo $data['product']['description'];
?>
</div>
</div>
<script type="text/javascript">
$(document).ready(function(){
$("button").click(function(){
a = $(this).val();
for(i=1; i<=a; i++){
$(":first-child", "button[value='"+i+"']").hide();
}
b = parseInt(a) + 1;
for(i=b; i<=5; i++) {
$(":first-child", "button[value='"+i+"']").show();
}
$("#vote_result").val(a);
});
});
</script>
<div id="remark_and_reply">
<div id="your_remark">
<span>Nhận xét của bạn</span>
<?php
if(!isset($_SESSION['level'])) {
echo "<span id='login_to_remark'><a href='index.php?controller=session&action=new'>Vui lòng đăng nhập để nhận xét</a></span>";
}
?>
<div class="clr"></div>
<p style="font-style: italic; margin-top: 10px;">(Đánh giá và bình luận của bạn sẽ được ban quản trị website duyệt trước khi hiển thị)</p>
<table style="float: left;">
<tr>
<td><b style="display: block; float: left;">1. Đánh giá của bạn về sản phẩm này:</b>
<div style="float: left; margin: -6px 0 0 10px;">
<button value="1" <?php if(!isset($_SESSION['level'])) echo "disabled='disabled'"; ?>><img src="assets/images/system/gray_star.png"></button>
<button value="2" <?php if(!isset($_SESSION['level'])) echo "disabled='disabled'"; ?>><img src="assets/images/system/gray_star.png"></button>
<button value="3" <?php if(!isset($_SESSION['level'])) echo "disabled='disabled'"; ?>><img src="assets/images/system/gray_star.png"></button>
<button value="4" <?php if(!isset($_SESSION['level'])) echo "disabled='disabled'"; ?>><img src="assets/images/system/gray_star.png"></button>
<button value="5" <?php if(!isset($_SESSION['level'])) echo "disabled='disabled'"; ?>><img src="assets/images/system/gray_star.png"></button>
</div>
</td>
</tr>
<tr>
<td><b>2. Viết bình luận của bạn:</b></td>
</tr>
<form action="index.php?controller=product&action=show&pid=<?php echo $data['product']['pid']; ?>" method="post">
<tr>
<td>
<textarea cols="50" rows="8" name="content" class="form-control" placeholder="Bình luận của bạn về sản phẩm này" <?php if(!isset($_SESSION['level'])) echo "disabled='disabled'"; ?>></textarea>
</td>
</tr>
<tr>
<td style="text-align: right;">
<input type="hidden" name="score" id="vote_result" value="0">
<input type="submit" name="ok" value="Gửi nhận xét" class="btn btn-info" <?php if(!isset($_SESSION['level'])) echo "disabled='disabled'"; ?>>
</td>
</tr>
</form>
</table>
<div class="error" style="float: right; padding: 0;">
<?php
if(!empty($data['error'])) {
echo "<ul>";
foreach ($data['error'] as $item) {
echo "<li>$item</li>";
}
echo "</ul>";
}
?>
</div>
</div>
<div class="clr"></div>
<div id="remark_and_reply_list">
<span>Khách hàng nhận xét về sản phẩm</span>
<?php
if(empty($data['remark'])) {
echo "<p>Chưa có nhận xét nào về sản phẩm này</p>";
} else {
foreach ($data['remark'] as $item) {
echo "<div class='customer_remark'>";
echo "<table>";
echo "<tr>";
echo "<td>";
echo "<img src='assets/images/users/$item[avatar]' style='margin: 20px 55px 10px;' />";
echo "<p style='margin: 0; font-weight: bold;'>$item[name]</p>";
echo "</td>";
echo "<td style='border-left: 1px solid #E7E7E7; text-align: justify; padding: 0 35px; font-size: 11pt;'>";
echo "<p>";
for ($i=1; $i<=$item['rating']; $i++){
echo "<img src='assets/images/system/star.png' style='width: 16px; height: 16px;'>";
}
for($i=$item['rating']+1; $i<=5; $i++){
echo "<img src='assets/images/system/gray_star.png' style='width: 16px; height: 16px;'>";
}
echo "</p>";
echo $item['content'];
echo "</td>";
echo "</tr>";
echo "</table>";
echo "</div>";
}
}
?>
</div>
</div>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$meffect = new Model_Effect;
$meffect->order("oeid", "DESC");
$data['effect'] = $meffect->listEffect();
$per_page = 12;
$mproduct = new Model_Product;
if(isset($_GET['oeid']) && $_GET['oeid'] != 0) {
$mproduct->where("oeid = '$_GET[oeid]'");
}
$mproduct->listProduct();
$data['items_amount'] = $mproduct->num_rows();
$data['page'] = ceil($data['items_amount'] / $per_page);
$mproduct->order("pid", "DESC");
if(isset($_GET['page'])) {
$data['current_page'] = $_GET['page'];
$start = $per_page * ($data['current_page'] - 1);
$mproduct->limit($per_page, $start);
} else {
$mproduct->limit($per_page);
$data['current_page'] = 1;
}
$data['product'] = $mproduct->listProduct();
$data['title_tag'] = "Trà thảo dược";
loadview("product/index", $data);
<file_sep><?php
if(isset($_GET['resources'])){
switch($_GET['resources']){
case "address": require("controllers/user/address/address.php"); break;
case "invoice": require("controllers/user/invoice/invoice.php"); break;
}
}else{
if(isset($_GET['action'])){
switch($_GET['action']){
case "signup": require("controllers/user/signup.php"); break;
}
}else{
require("controllers/user/account.php");
}
}
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<div id="reply_question">
<form action="index.php?controller=salesmanager&resources=ask_and_answer&action=answer&qid=<?php echo $data['question']['qid']; ?>" method="post">
<table style="margin: 0;">
<tr>
<td><b>Câu hỏi</b></td>
<td><?php echo $data['question']['content']; ?></td>
</tr>
<tr>
<td><b>Câu trả lời</b></td>
<td>
<textarea cols="70" rows="7" name="reply" class="form-control" style="resize: none;" required="required"></textarea>
</td>
</tr>
<tr>
<td></td>
<td><input type="submit" name="ok" value="Trả lời" class="btn btn-primary"></td>
</tr>
</table>
</form>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
if(isset($_POST['ok'])) {
$question = $_POST['question'];
$input_data = array("content" => $question);
$mquestion = new Model_Question;
$mquestion->addQuestion($input_data);
redirect("index.php?controller=ask_and_answer");
}
<file_sep><?php
class Model_News extends Model{
protected $_table = "news";
public function addNews($data){
$this->insert($this->_table, $data);
}
public function listNews(){
$this->getData($this->_table);
return $this->fetchAll();
}
public function deleteNews($nid){
$this->where("nid = '$nid'");
$this->delete($this->_table);
}
public function getNewsByNid($nid){
$this->where("nid = '$nid'");
$this->getData($this->_table);
return $this->fetch();
}
public function udpateNews($data){
$this->update($this->_table, $data);
}
}
<file_sep><?php
class Model_Invoice extends Model{
protected $_table = "invoices";
public function addInvoice($data){
$this->insert($this->_table, $data);
}
public function checkAfterLogin($id){
$check_data = array("uid =" => $id, "status =" => "1");
$this->where($check_data);
$this->select("iid, products_amount, total");
$this->getData($this->_table);
if($this->num_rows() == "1"){
return $this->fetch();
}else{
return false;
}
}
public function updateInvoice($data){
$this->update($this->_table, $data);
}
public function getInvoiceId($data){
$this->select("iid");
$this->where($data);
$this->getData($this->_table);
$output = $this->fetch();
return $output['iid'];
}
public function deleteInvoice($iid){
$this->where("iid = '$iid'");
$this->delete($this->_table);
}
public function getInvoiceByUid($uid){
$this->where("uid = '$uid'");
$this->getData($this->_table);
return $this->fetchAll();
}
public function getInvoiceByIid($iid){
$this->where("iid = '$iid'");
$this->getData($this->_table);
return $this->fetch();
}
public function listInvoice(){
$this->getData($this->_table);
return $this->fetchAll();
}
public function updateInvoiceStatus($iid){
$this->select("status");
$status = $this->getInvoiceByIid($iid);
$status['status'] += 1;
$update_data = array("status" => $status['status']);
$this->updateInvoice($update_data);
}
public function countInvoiceByUid($uid) {
$this->where("uid = '$uid'");
$this->getData($this->_table);
return $this->num_rows();
}
public function statInvoice() {
$this->getData($this->_table);
return $this->fetch();
}
public function currentMonthTotal() {
$year = date("Y");
$month = date("m");
$condition = array(
"year(order_date) =" => $year,
"month(order_date) =" => $month,
"status =" => "4"
);
$this->where($condition);
$this->getData($this->_table);
return $this->fetch();
}
public function getTotal() {
$this->select("total");
$this->getData($this->_table);
return $this->fetch();
}
}
<file_sep><script type="text/javascript">
$(document).ready(function(){
$("#province").change(function(){
provid = $(this).val();
$.ajax({
url:"index.php?controller=user&resources=address&action=list_district_ajax",
type:"get",
data:"provid="+provid,
async:true,
success:function(result){
$("#district").html(result);
}
});
});
$("#district").change(function(){
distid = $(this).val();
$.ajax({
url:"index.php?controller=user&resources=address&action=list_commune_ajax",
type:"get",
data:"distid="+distid,
async:true,
success:function(result){
$("#commune").html(result);
}
});
});
});
</script>
<div id="create_edit_addr">
<a href="index.php?controller=user&uid=<?php echo $_SESSION['uid']; ?>" class="btn btn-info" style="position: absolute; top: 33px; left: 20px; padding: 3px;">← Tài khoản</a>
<div id="addr_form">
<?php
if($_GET['action'] == "new") {
echo "<p style='font-weight: bold; font-size: 11pt; margin-left: 150px;'>Tạo địa chỉ mới</p>";
echo "<form action='index.php?controller=user&resources=address&action=new&uid=$_SESSION[uid]' method='post'>";
} else {
echo "<p style='font-weight: bold; font-size: 11pt; margin-left: 150px;'>Chỉnh sửa địa chỉ</p>";
echo "<form action='index.php?controller=user&resources=address&action=edit&addrid=".$data['addr']['addrid']."' method='post'>";
}
?>
<table>
<tr>
<td style="width: 110px;">Họ và tên</td>
<td style="width: 300px;">
<input type="text" name="fullname" class="form-control" <?php if(isset($data['addr'])) echo "value='".$data['addr']['fullname']."'"; ?>>
</td>
</tr>
<tr>
<td>Số điện thoại</td>
<td>
<input type="text" name="telephone" class="form-control" <?php if(isset($data['addr'])) echo "value='".$data['addr']['telephone']."'"; ?>>
</td>
</tr>
<tr>
<td>Tỉnh/Thành</td>
<td>
<select class="form-control" name="province" id="province">
<option value="0">Chọn Tỉnh/Thành phố</option>
<?php
foreach ($data['province'] as $item) {
if (isset($data['addr']) && ($data['addr']['provid'] == $item['provid'])){
echo "<option value='$item[provid]' selected='selected'>$item[name]</option>";
} else {
echo "<option value='$item[provid]'>$item[name]</option>";
}
}
?>
</select>
</td>
</tr>
<tr>
<td>Quận/Huyện</td>
<td>
<select class="form-control" name="district" id="district">
<option value="0">Chọn Quận/Huyện</option>
<?php
if(isset($data['district'])) {
foreach ($data['district'] as $item) {
if ($data['addr']['distid'] == $item['distid']){
echo "<option value='$item[distid]' selected='selected'>$item[name]</option>";
} else {
echo "<option value='$item[distid]'>$item[name]</option>";
}
}
}
?>
</select>
</td>
</tr>
<tr>
<td>Xã/Phường</td>
<td>
<select class="form-control" name="commune" id="commune">
<option value="0">Chọn Xã/Phường</option>
<?php
if(isset($data['commune'])) {
foreach ($data['commune'] as $item) {
if ($data['addr']['commid'] == $item['commid']) {
echo "<option value='$item[commid]' selected='selected'>$item[name]</option>";
} else {
echo "<option value='$item[commid]'>$item[name]</option>";
}
}
}
?>
</select>
</td>
</tr>
<tr>
<td>Địa chỉ</td>
<td>
<textarea cols="30" rows="3" name="address" class="form-control" style="resize: none;"><?php if(isset($data['addr'])) echo $data['addr']['address']; ?></textarea>
</td>
</tr>
<tr>
<td></td>
<td>
<input type="submit" name="ok" value="<?php if($_GET['action'] == "new"){ echo "Thêm địa chỉ"; } else { echo "Cập nhật"; } ?>" class="btn btn-primary">
</td>
</tr>
</table>
</form>
</div>
<div class="error">
<?php
if(!empty($data['error'])){
echo "<ul>";
foreach ($data['error'] as $err){
echo "<li>$err</li>";
}
echo "</ul>";
}
?>
</div>
</div>
<file_sep><?php
$data = "";
$iid = $_GET['iid'];
$minvoice = new Model_Invoice;
$data['invoice'] = $minvoice->getInvoiceByIid($iid);
$minvoicedetail = new Model_InvoiceDetail;
$minvoicedetail->order("idid", "DESC");
$minvoicedetail->select("name, price, quantity");
$data['invoice_detail'] = $minvoicedetail->listInvoiceDetail($iid);
$maddressregister = new Model_AddressRegister;
$data['addr'] = $maddressregister->getAddressRegisterById($data['invoice']['addrid']);
$mcommune = new Model_Commune;
$data['comm_info'] = $mcommune->getCommuneById($data['addr']['commid']);
$data['addr']['comm_name'] = $data['comm_info']['name'];
$mdistrict = new Model_District;
$data['dist_info'] = $mdistrict->getDistrictById($data['comm_info']['distid']);
$data['addr']['dist_name'] = $data['dist_info']['name'];
$mprovince = new Model_Province;
$data['prov_info'] = $mprovince->getProvinceById($data['dist_info']['provid']);
$data['addr']['prov_name'] = $data['prov_info']['name'];
$data['title_tag'] = "Xem chi tiết đơn hàng";
loadview("salesmanager/invoice/show", $data);
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<script type="text/javascript">
function update_remark(){
if(!window.confirm("Bạn chắc chắn chấp nhận bình luận này?")) return false;
}
function reject_remark(){
if(!window.confirm("Bạn chắc chắn muốn huỷ bình luận này?")) return false;
}
</script>
<div id="remarks_list">
<table class="table table-hover table-bordered">
<thead>
<tr>
<th style="width: 50px;">STT</th>
<th style="width: 90px; padding-bottom: 8px;">Thời điểm bình luận</th>
<th style="width: 160px;">Sản phẩm</th>
<th style="width: 72px;">Đánh giá</th>
<th>Nội dung</th>
<th style="width: 85px;">Trạng thái</th>
<th style="width: 90px;">Duyệt</th>
</tr>
</thead>
<tbody>
<?php
if(empty($data['data'])) {
echo "<tr>";
echo "<td colspan='7'>Chưa có đánh giá nào từ phía người dùng</td>";
echo "</tr>";
} else {
$stt = 1;
foreach ($data['data'] as $item) {
echo "<tr>";
echo "<td>$stt</td>";
echo "<td>".date("d/m/Y", strtotime($item['created_at']))."</td>";
echo "<td>$item[product_name]</td>";
$score = $item['rating'];
switch ($score) {
case "1": echo "<td><span class='one_star'>1 sao</span></td>"; break;
case "2": echo "<td><span class='two_star'>2 sao</span></td>"; break;
case "3": echo "<td><span class='three_star'>3 sao</span></td>"; break;
case "4": echo "<td><span class='four_star'>4 sao</span></td>"; break;
case "5": echo "<td><span class='five_star'>5 sao</span></td>"; break;
}
echo "<td style='text-align: justify;'>$item[content]</td>";
$status = $item['is_approved'];
switch ($status) {
case "0":
echo "<td><span class='pending_remark'>chờ duyệt</span></td>";
echo "<td><a href='index.php?controller=salesmanager&resources=remark&action=accept&remid=$item[remid]' onclick='return update_remark();'><span class='icon_accept'></span></a><a href='index.php?controller=salesmanager&resources=remark&action=cancel&remid=$item[remid]' onclick='return reject_remark();'><span class='icon_abort'></span></a></td>";
break;
case "1":
echo "<td><span class='accepted_remark'>đã duyệt</span></td>";
echo "<td></td>";
break;
case "2":
echo "<td><span class='canceled_remark'>huỷ</span></td>";
echo "<td></td>";
break;
}
echo "</tr>";
$stt++;
}
}
?>
</tbody>
</table>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
function __autoload($url){
$url = strtolower($url);
$url = str_replace("_", "/", $url);
$url = str_replace("model", "models", $url);
require("$url.php");
}
function loadview($url, $data = ""){
require("views/$url.php");
}
function redirect($url){
header("location:$url");
exit();
}
date_default_timezone_set("Asia/Ho_Chi_Minh");
<file_sep><?php
loadview("layouts/header", $data);
?>
<div id="search_result" style="width: 1000px; margin: auto; min-height: 257px;">
<?php
if($data['products'] == "") {
echo "<p style='font-weight: bold; font-size: 14pt; margin: 10px 0 20px 0px;'>Không tìm thấy sản phẩm nào với từ khoá '$data[keyword]'</p>";
echo "<a href='index.php'>Quay lại trang chủ</a>";
} else {
$a = count($data['products']);
echo "<p style='font-weight: bold; font-size: 14pt; margin: 10px 0 20px 10px;'>Tìm thấy $a sản phẩm với từ khoá '$data[keyword]'</p>";
foreach ($data['products'] as $item) {
echo "<div class='product'>";
echo "<a href='index.php?controller=product&action=show&pid=$item[pid]'>";
echo "<img src='assets/images/products/$item[image]' />";
echo "<h2 class='product_name'>$item[name]</h2>";
echo "<p class='product_price'>".number_format($item['price'])."₫</p>";
echo "</a>";
echo "</div>";
}
}
?>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$data = "";
$muser = new Model_User;
$muser->select("uid");
$data['user']['all'] = $muser->countUser();
$muser->where("level = '1'");
$data['user']['member'] = $muser->countUser();
$muser->where("level = '2'");
$data['user']['salesmanager'] = $muser->countUser();
$muser->where("level = '3'");
$data['user']['admin'] = $muser->countUser();
$mproduct = new Model_Product;
$mproduct->select('pid');
$data['product']['types_amount'] = $mproduct->countProductsType();
$mproduct->select('sum(quantity)');
$data['product']['is_present_amount'] = $mproduct->statProduct();
$mproduct->select('sum(sold)');
$data['product']['sold_amount'] = $mproduct->statProduct();
$minvoice = new Model_Invoice;
$minvoice->where("status = '4'");
$minvoice->select("sum(total)");
$data['avenue']['total'] = $minvoice->statInvoice();
$data['avenue']['current_month_total'] = $minvoice->currentMonthTotal();
$data['title_tag'] = "Quản lý kinh doanh";
loadview("salesmanager/mainpage", $data);
<file_sep><?php
if(isset($_GET['action'])){
switch($_GET['action']){
case "home": loadview("static_pages/home", $data); break;
case "guide":
$data['title_tag'] = "Hướng dẫn mua hàng";
loadview("static_pages/guide", $data); break;
case "intro":
$data['title_tag'] = "Giới thiệu";
loadview("static_pages/intro", $data); break;
case "agency_register":
$data['title_tag'] = "Đăng ký làm đại lý";
loadview("static_pages/agency_register", $data); break;
}
}else{
}
<file_sep><div id="news_form">
<?php
if(isset($data['news'])) {
echo "<form action='index.php?controller=salesmanager&resources=news&action=edit&nid=".$data['news']['nid']."' method='post' enctype='multipart/form-data'>";
} else {
echo "<form action='index.php?controller=salesmanager&resources=news&action=new' method='post' enctype='multipart/form-data'>";
}
?>
<table>
<tr>
<td>Tiêu đề</td>
<td><input type="text" name="title" class="form-control" <?php if(isset($data['news'])) echo "value='".$data['news']['title']."';" ?>></td>
</tr>
<?php
if(isset($data['news'])) {
echo "<tr>";
echo "<td>Ảnh minh hoạ</td>";
echo "<td><img src='assets/images/news/".$data['news']['poster']."' style='width: 315px; height: 150px;'></td>";
echo "</tr>";
echo "<tr>";
echo "<td>Chọn ảnh khác</td>";
echo "<td><input type='file' name='image'></td>";
echo "</tr>";
} else {
echo "<tr>";
echo "<td>Ảnh minh hoạ</td>";
echo "<td><input type='file' name='image'></td>";
echo "</tr>";
}
?>
<tr>
<td>Nội dung</td>
<td>
<textarea cols="80" rows="15" name="content" class="form-control" style="resize: none;"><?php if (isset($data['news'])) echo $data['news']['content']; ?></textarea>
</td>
</tr>
<script type="text/javascript">
CKEDITOR.replace("content");
</script>
<tr>
<td></td>
<td><input type="submit" name="ok" value="<?php if(isset($data['news'])){ echo "Chỉnh sửa bài viết"; } else { echo "Thêm bài viết mới"; } ?>" class="btn btn-primary"></td>
</tr>
</table>
</form>
<div class="error">
<?php
if(!empty($data['error'])) {
echo "<ul>";
foreach ($data['error'] as $item) {
echo "<li>$item</li>";
}
echo "</ul>";
}
?>
</div>
</div>
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<div id="add_effect_interface">
<form action="index.php?controller=salesmanager&resources=effect&action=new" method="post">
<table>
<tr>
<td style="font-size: 11pt;">Tên công dụng</td>
<td style="width: 400px;"><input type="text" name="txteffect" class="form-control" /></td>
</tr>
<tr>
<td></td>
<td><input type="submit" value="Thêm" class="btn btn-primary" name="ok" /></td>
</tr>
</table>
<?php
if(!empty($data['error'])){
echo "<div class='error'>";
echo "<ul>";
foreach($data['error'] as $err){
echo "<li>$err</li>";
}
echo "</ul>";
echo "</div>";
}
?>
</form>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$mremark = new Model_Remark;
$mremark->order("remid", "DESC");
$data['data'] = $mremark->listRemark();
if(!empty($data['data'])){
$i = 0;
$mproduct = new Model_Product;
$mproduct->select("name");
foreach($data['data'] as $item){
$product_info = $mproduct->getProductById($item['pid']);
$data['data'][$i]['product_name'] = $product_info['name'];
$i++;
}
}
$data['title_tag'] = "Ý kiến người dùng";
loadview("salesmanager/remark/index", $data);
<file_sep><?php
$per_page = 10;
$mproduct = new Model_Product;
$mproduct->listProduct();
$products_amount = $mproduct->num_rows();
$data['page'] = ceil($products_amount / $per_page);
$mproduct->order("pid", "DESC");
if (isset($_GET['page'])) {
$data['current_page'] = $_GET['page'];
$start = $per_page * ($data['current_page'] - 1);
$mproduct->limit($per_page, $start);
} else {
$mproduct->limit($per_page);
$data['current_page'] = 1;
}
$data['product'] = $mproduct->listProduct();
$data['title_tag'] = "Kho hàng";
loadview("salesmanager/product/index", $data);
<file_sep><?php
$data = "";
if(isset($_POST['ok'])){
$user = $email = $pass = "";
if(empty($_POST['txtuser'])){
$data['error'][] = "Tên người dùng không được để trống";
}else{
$user = $_POST['txtuser'];
}
if(empty($_POST['txtemail'])){
$data['error'][] = "Email không được để trống";
}else{
$email = $_POST['txtemail'];
}
if(empty($_POST['txtpass'])){
$data['error'][] = "Mật khẩu không được để trống";
}else{
if($_POST['txtpass'] != $_POST['txtpass2']){
$data['error'][] = "Mật khẩu và xác nhận mật khẩu không khớp";
}else{
$pass = $_POST['txtpass'];
}
}
if($user && $email && $pass){
$muser = new Model_User;
$muser->where("email = '$email'");
$muser->select("email");
if($muser->checkUser() == true){
$pass = md5($pass);
$input_data = array("name" => $user, "email" => $email, "password" => $<PASSWORD>);
$muser->addUser($input_data);
redirect("index.php?controller=session&action=new");
}else{
$data['error'][] = "Email đã tồn tại, vui lòng chọn email khác";
}
}
}
$data['title_tag'] = "Đăng ký";
loadview("static_pages/signup", $data);
<file_sep><?php
$data = "";
if(isset($_POST['ok'])) {
if (!empty($_POST['keyword'])) {
$keyword = $_POST['keyword'];
$mproduct = new Model_Product;
$data['products'] = $mproduct->searchProduct($keyword);
} else {
redirect("index.php");
}
}
$data['keyword'] = $keyword;
$data['title_tag'] = "Kết quả tìm kiếm với từ khoá '$keyword'";
loadview("product/search", $data);
<file_sep><?php
loadview("layouts/header", $data);
?>
<script type="text/javascript">
$(document).ready(function(){
$("#list_news div:last-child").css("border-bottom", "none");
});
</script>
<div id="list_news" style="min-height: 252px;">
<?php
if (empty($data['news'])) {
echo "<p>Chưa có bài viết nào</p>";
} else {
foreach ($data['news'] as $item) {
echo "<div class='news_item'>";
echo "<div class='poster'>";
echo "<a href='index.php?controller=news&action=show&nid=$item[nid]'><img src='assets/images/news/$item[poster]' style='width: 210px; height: 100px;'></a>";
echo "</div>";
echo "<div class='news_abstract_info'>";
echo "<a href='index.php?controller=news&action=show&nid=$item[nid]'><h2 style='margin: 0 0 3px 0; font-size: 16pt;'>$item[title]</h2></a>";
$timestamp = strtotime($item['created_at']);
echo "<p>Đăng ngày ".date("d/m/Y", $timestamp)."</p>";
echo "</div>";
echo "<div class='clr'></div>";
echo "</div>";
}
}
?>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$remid = $_GET['remid'];
$mremark = new Model_Remark;
$mremark->where("remid = '$remid'");
$update_data = array("is_approved" => "2");
$mremark->updateRemark($update_data);
redirect("index.php?controller=salesmanager&resources=remark&action=index");
<file_sep><?php
$nid = $_GET['nid'];
$mnews = new Model_News;
$data['news'] = $mnews->getNewsByNid($nid);
if(isset($_POST['ok'])) {
$title = $content = $image = "";
if (empty($_POST['title'])) {
$data['error'][] = "Không xoá tiêu đề";
} else {
$title = $_POST['title'];
}
if (empty($_POST['content'])) {
$data['error'][] = "Không xoá nội dung";
} else {
$content = $_POST['content'];
}
if ($_FILES['image']['name']) {
$image = $_FILES['image']['name'];
} else {
$image = "none";
}
if ($title && $content && $image) {
$update_data = array(
"title" => $title,
"content" => $content
);
if ($image != "none") {
$update_data['poster'] = $image;
move_uploaded_file($_FILES['image']['tmp_name'], "assets/images/news/".$_FILES['image']['name']);
}
$mnews->udpateNews($update_data);
redirect("index.php?controller=salesmanager&resources=news&action=index");
}
}
$data['title_tag'] = "Chỉnh sửa bài viết";
loadview("salesmanager/news/edit", $data);
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<script type="text/javascript">
function update_status() {
if (!window.confirm("Bạn chắc chắn muốn cập nhật trạng thái của đơn hàng này?")) return false;
}
</script>
<div id="manage_invoices">
<div id="all_invoices" style="min-height: 364px;">
<table class="table table-hover table-bordered">
<thead>
<tr>
<th style="width: 80px; padding-bottom: 17px;">STT</th>
<th style="width: 100px; padding-bottom: 17px;">Mã đơn hàng</th>
<th style="width: 80px;">Số lượng sản phẩm</th>
<th style="padding-bottom: 17px;">Tổng cộng</th>
<th style="width: 100px;">Hình thức thanh toán</th>
<th style="width: 150px; padding-bottom: 17px;">Thời điểm đặt hàng</th>
<th style="width: 163px; padding-bottom: 17px;">Trạng thái</th>
<th style="width: 135px; padding-bottom: 17px;">Cập nhật trạng thái</th>
</tr>
</thead>
<tbody>
<?php
if (!empty($data['invoice'])) {
$stt = ($data['current_page'] - 1) * 10 + 1;
foreach ($data['invoice'] as $item) {
echo "<tr>";
echo "<td>$stt</td>";
echo "<td><a href='index.php?controller=salesmanager&resources=invoice&action=show&iid=$item[iid]' class='view_invoice_detail'>$item[iid]</a></td>";
echo "<td>".number_format($item['products_amount'])."</td>";
echo "<td>".number_format($item['total'])." ₫</td>";
$payment_method = $item['payment_method'];
if ($payment_method == 0) {
echo "<td>N/A</td>";
} elseif ($payment_method == 1) {
echo "<td><span class='money'></span></td>";
} elseif ($payment_method == 2) {
echo "<td><span class='atm_card'></span></td>";
}
if (empty($item['order_date'])) {
echo "<td>N/A</td>";
} else {
$timestamp = strtotime($item['order_date']);
echo "<td>".date("H:i", $timestamp)." ngày ".date("d/m/Y", $timestamp)."</td>";
}
$status = $item['status'];
switch ($status) {
case "1":
echo "<td><span class='in_buying'>đang mua hàng</span></td>";
echo "<td></td>";
break;
case "2":
echo "<td><span class='ordered'>đã đặt hàng</span></td>";
echo "<td><a href='index.php?controller=salesmanager&resources=invoice&action=edit&iid=$item[iid]&page=$data[current_page]' onclick='return update_status();'><span class='icon_update'></span></a></td>";
break;
case "3":
echo "<td><span class='in_progressing'>đang xử lý</span></td>";
echo "<td><a href='index.php?controller=salesmanager&resources=invoice&action=edit&iid=$item[iid]&page=$data[current_page]' onclick='return update_status();'><span class='icon_update'></span></a></td>";
break;
case "4":
echo "<td><span class='success_delivery'>giao hàng thành công</span></td>";
echo "<td></td>";
break;
}
echo "</tr>";
$stt++;
}
} else {
echo "<tr>";
echo "<td colspan='8'>Chưa có đơn hàng nào</td>";
echo "</tr>";
}
?>
</tbody>
</table>
</div>
<nav aria-label="Page navigation" style="position: relative; height: 50px;">
<ul class="pagination" style="position: absolute; right: 0px; bottom: 0px;">
<?php
if ($data['current_page'] == 1) {
echo "<li class='disabled'>";
echo "<span aria-hidden='true'>«</span>";
echo "</li>";
} else {
$prev = $data['current_page'] - 1;
echo "<li>";
echo "<a href='index.php?controller=salesmanager&resources=invoice&page=$prev' aria-label='Previous'>";
echo "<span aria-hidden='true'>«</span>";
echo "</a>";
echo "</li>";
}
for ($i = 1; $i <= $data['page']; $i++) {
if ($i == $data['current_page']) {
echo "<li class='active'><a href='javascript: void(0)'>$i</a></li>";
} else {
echo "<li><a href='index.php?controller=salesmanager&resources=invoice&page=$i'>$i</a></li>";
}
}
if ($data['current_page'] == $data['page']) {
echo "<li class='disabled'>";
echo "<span aria-hidden='true'>»</span>";
echo "</li>";
} else {
$next = $data['current_page'] + 1;
echo "<li>";
echo "<a href='index.php?controller=salesmanager&resources=invoice&page=$next' aria-label='Next'>";
echo "<span aria-hidden='true'>»</span>";
echo "</a>";
echo "</li>";
}
?>
</ul>
</nav>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$pid = $_GET['pid'];
$mproduct = new Model_Product;
$data['product'] = $mproduct->getProductById($pid);
$mremark = new Model_Remark;
$mremark->order("remid", "DESC");
$data['remark'] = $mremark->getRemarkByPid($pid);
if (!empty($data['remark'])) {
$muser = new Model_User;
$muser->select("name, avatar");
$i = 0;
foreach ($data['remark'] as $item) {
$muser->where("uid = '$item[uid]'");
$user_info = $muser->showUser();
$data['remark'][$i]['name']= $user_info['name'];
$data['remark'][$i]['avatar'] = $user_info['avatar'];
$i++;
}
}
if(isset($_POST['ok'])) {
$score = $content = "";
if(empty($_POST['score'])){
$data['error'][] = "Vui lòng đánh giá sản phẩm";
} else {
$score = $_POST['score'];
}
if(empty($_POST['content'])){
$data['error'][] = "Vui lòng viết bình luận về sản phẩm";
} else {
$content = htmlspecialchars($_POST['content']);
}
if($score && $content){
$input_data = array(
"rating" => $score,
"content" => $content,
"uid" => $_SESSION['uid'],
"pid" => $pid,
"created_at" => date("Y:m:d")
);
$mremark->addRemark($input_data);
redirect("index.php?controller=product&action=show&pid=$pid");
}
}
$data['title_tag'] = $data['product']['name'];
loadview("product/show", $data);
<file_sep><?php
loadview("layouts/simple_header", $data);
?>
<script type="text/javascript" src="assets/javascripts/admin.js"></script>
<div id="admin_mainpage">
<div id="admin_filter" style="margin-bottom: 0px;">
<form>
<span>Hiển thị người dùng</span>
<select id='users_filter' class='form-control'>
<option value='0'>-- Tất cả --</option>
<option value='1'>Tài khoản thường</option>
<option value='2' style='font-weight: bold; color: blue;'>Quản lý bán hàng</option>
<option value='3' style='font-weight: bold; color: red;'>Quản trị viên</option>
</select>
</form>
</div>
<div id="users_list" style="min-height: 362px;">
<div style="width: 930px; margin: auto; position: relative; height: 28px; margin-bottom: 10px;">
<a id="delete_all" href="javascript:void(0)" class="btn btn-danger" disabled="disabled" style="position: absolute; right: 0; padding: 3px 12px;">Xoá</a>
</div>
<table class="table table-bordered" data-page="<?php echo $data['current_page']; ?>">
<thead>
<tr>
<th class='index'>STT</th>
<th class='name'>Tên</th>
<th class='email'>Email</th>
<th class='level'>Loại tài khoản</th>
<th style="width: 100px;">Số lượng đơn hàng</th>
<th style="width: 90px;">Số lượt bình luận</th>
<th class='change_level'>Chuyển đổi tài khoản</th>
<th class='del'>Xoá</th>
<th class='check'></th>
</tr>
</thead>
<tbody>
<?php
if (empty($data['user'])) {
echo "<tr>";
echo "<td colspan='9'>Chưa có dữ liệu</td>";
echo "</tr>";
} else {
$stt = ($data['current_page'] - 1) * 7 + 1;
$i = 1;
foreach($data['user'] as $item){
echo "<tr>";
echo "<td>$stt</td>";
echo "<td>$item[name]</td>";
echo "<td>$item[email]</td>";
if($item['level'] == 1){
echo "<td>Thường</td>";
echo "<td>".number_format($item['invoices_amount'])."</td>";
echo "<td>".number_format($item['remarks_amount'])."</td>";
if ($item['invoices_amount'] == 0 && $item['remarks_amount'] == 0) {
echo "<td><a href='index.php?controller=admin&resources=user&action=edit&uid=$item[uid]&level=$item[level]&page=$data[current_page]' onclick='return check_change_level();'><span class='icon_change_level'></span></td>";
echo "<td><a href='index.php?controller=admin&resources=user&action=destroy&uid=$item[uid]&page=$data[current_page]' onclick='return check_delete();'><span class='icon_delete'></span></a></td>";
echo "<td class='lcheckbox'><input type='checkbox' data-id='$item[uid]' data-old-order='$i' data-new-order=''></td>";
} else {
echo "<td></td>";
echo "<td></td>";
echo "<td></td>";
}
}elseif($item['level'] == 2){
echo "<td style='color: blue; font-weight: bold;'>Quản lý bán hàng</td>";
echo "<td> </td>";
echo "<td> </td>";
echo "<td><a href='index.php?controller=admin&resources=user&action=edit&uid=$item[uid]&level=$item[level]&page=$data[current_page]' onclick='return check_change_level();'><span class='icon_change_level'></span></td>";
echo "<td> </td>";
echo "<td> </td>";
}else{
echo "<td style='color: red; font-weight: bold;'>Quản trị viên</td>";
echo "<td> </td>";
echo "<td> </td>";
echo "<td> </td>";
echo "<td> </td>";
echo "<td> </td>";
}
echo "</tr>";
$stt++;
$i++;
}
}
?>
</tbody>
</table>
</div>
<nav aria-label="Page navigation" style="position: relative; height: 50px;">
<ul class="pagination" style="position: absolute; right: 32px; bottom: 0px;">
<?php
if ($data['current_page'] == 1) {
echo "<li class='disabled'>";
echo "<span aria-hidden='true'>«</span>";
echo "</li>";
} else {
$prev = $data['current_page'] - 1;
echo "<li>";
echo "<a href='index.php?controller=admin&resources=user&page=$prev' aria-label='Previous'>";
echo "<span aria-hidden='true'>«</span>";
echo "</a>";
echo "</li>";
}
for($i = 1; $i <= $data['page']; $i++) {
if ($i == $data['current_page']) {
echo "<li class='active'><a href='javascript: void(0)'>$i</a></li>";
} else {
echo "<li><a href='index.php?controller=admin&resources=user&page=$i'>$i</a></li>";
}
}
if ($data['current_page'] == $data['page']) {
echo "<li class='disabled'>";
echo "<span aria-hidden='true'>»</span>";
echo "</li>";
} else {
$next = $data['current_page'] + 1;
echo "<li>";
echo "<a href='index.php?controller=admin&resources=user&page=$next' aria-label='Next'>";
echo "<span aria-hidden='true'>»</span>";
echo "</a>";
echo "</li>";
}
?>
</ul>
</nav>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep> <?php
if(isset($_SESSION['level']) && ($_SESSION['level'] == 2)){
if($_GET['controller'] == "salesmanager"){
echo "</div>";
echo "</div>";
echo "</div>";
}
}
?>
<div class="clr"></div>
<div id="footer">
<ul>
<li><NAME></li>
<li>Sản phẩm từ thiên nhiên</li>
<li>Copyright 2016 © <EMAIL></li>
</ul>
</div>
<div class="footer">
<a class="btn-top" href="javascript:void(0);" title="Top"></a>
</div>
<script type="text/javascript" src="assets/javascripts/bootstrap.min.js"></script>
<script type="text/javascript" src="assets/javascripts/btn_top.js"></script>
</div>
</body>
</html>
<file_sep><?php
$data = "";
if(isset($_POST['ok'])) {
$title = $image = $content = "";
if(empty($_POST['title'])) {
$data['error'][] = "Chưa nhập tiêu đề";
} else {
$title = $_POST['title'];
}
if(empty($_FILES['image']['name'])) {
$data['error'][] = "Chưa chọn ảnh minh hoạ";
} else {
$image = $_FILES['image']['name'];
}
if(empty($_POST['content'])) {
$data['error'][] = "Chưa nhập nội dung";
} else {
$content = $_POST['content'];
}
if ($title && $image && $content) {
$input_data = array(
"title" => $title,
"poster" => $image,
"content" => $content,
"created_at" => date("Y:m:d H:i:s")
);
$mnews = new Model_News;
$mnews->addNews($input_data);
move_uploaded_file($_FILES['image']['tmp_name'], "assets/images/news/".$_FILES['image']['name']);
redirect("index.php?controller=salesmanager&resources=news&action=index");
}
}
$data['title_tag'] = "Thêm bài viết mới";
loadview("salesmanager/news/new", $data);
<file_sep><!DOCTYPE html>
<html>
<head>
<meta charset="utf-8" />
<meta http-equiv="X-UA-Compatible" content="IE=edge" />
<title>
<?php
if (!empty($data['title_tag'])) {
echo "$data[title_tag] | Quỳnh Phương Herbal Tea";
} else {
echo "Quỳnh Phương Herbal Tea";
}
?>
</title>
<meta name="viewport" content="width=device-width, initial-scale=1, maximum-scale=1, user-scalable=no" />
<link rel="shortcut icon" type="image/x-icon" href="assets/images/system/favicon.ico" />
<link rel="stylesheet" type="text/css" href="assets/stylesheets/bootstrap.min.css" />
<link rel="stylesheet" type="text/css" href="assets/stylesheets/custom.css" />
<link rel="stylesheet" type="text/css" href="assets/stylesheets/btn_top.css" />
<link rel="stylesheet" type="text/css" href="assets/stylesheets/frontend.css" />
<script type="text/javascript" src="assets/javascripts/jquery.min.js"></script>
</head>
<body>
<div class="website">
<div id="top">
<div id="top_left">
<ul>
<li id="email">Email: <EMAIL></li>
<li id="hotline">Hotline: 0164.418.3238</li>
</ul>
</div>
<script type="text/javascript">
$(document).ready(function(){
$("#navigation li").hover(function(){
$(this).find("ul:first").toggle();
});
$("#navigation .mini_menu").mouseenter(function(){
$("#highlight").show();
});
$("#navigation .mini_menu").mouseleave(function(){
$("#highlight").hide();
});
});
</script>
<div id="top_right">
<?php
if(isset($_SESSION['level']) && ($_SESSION['level'] == 1)){
echo "<div id='current_user'>";
echo "<ul id='navigation'>";
echo "<li>Xin chào <span style='font-weight: bold;'>$_SESSION[name]</span></li>";
echo "<li class='mini_menu'><img src='assets/images/users/$_SESSION[avatar]'>";
echo "<ul>";
echo "<li style='border-top: none;'><a href='index.php?controller=user&uid=$_SESSION[uid]' class='mini_account'>Tài khoản</a></li>";
echo "<li><a href='index.php?controller=user&resources=invoice&action=index&uid=$_SESSION[uid]' class='mini_invoices'>Đơn hàng</a></li>";
echo "<li><a href='index.php?controller=session&action=destroy' class='mini_logout'>Đăng xuất</a></li>";
echo "</ul>";
echo "</li>";
echo "</ul>";
echo "</div>";
}else{
echo "<ul class='visitor'>";
echo "<li id='signup'><a href='index.php?controller=user&action=signup'>Đăng ký</a></li>";
echo "<li id='vertical_slash'>|</li>";
echo "<li id='login'><a href='index.php?controller=session&action=new'>Đăng nhập</a></li>";
echo "</ul>";
}
?>
</div>
</div>
<!-- TOP -->
<div id="highlight"></div>
<div class="clr"></div>
<div id="header">
<div id="logo"><a href="http://localhost/www/herbal_tea/"><img src="assets/images/system/logo.jpg"></a></div>
<div id="search">
<form action='index.php?controller=product&action=search' method='post'>
<input type='text' name='keyword' placeholder='Nhập tên sản phẩm...' class='form-control' />
<input type='submit' name='ok' value='TÌM KIẾM' />
</form>
</div>
<div id="cart">
<a href="index.php?controller=cart"><img src="assets/images/system/cart.png"></a>
<div id="info_cart">
<?php
if(isset($_SESSION['level'])){
echo "<p>".number_format($_SESSION['products_amount'])." sản phẩm</p>";
echo "<p>".number_format($_SESSION['total'])." đồng</p>";
}else{
echo "<p>0 sản phẩm</p>";
echo "<p>0 đồng</p>";
}
?>
</div>
</div>
<div id="feature">
<ul>
<li id='assurance'>Uy tín, chất lượng</li>
<li id='delivery'>Giao hàng toàn quốc</li>
</ul>
</div>
</div>
<!-- HEADER -->
<div class="clr"></div>
<div id="menu">
<ul>
<img src="assets/images/system/home.png">
<li style="border-left:1px dotted #666;">
<a href="http://localhost/www/herbal_tea/">Trang chủ</a>
</li>
<li><a href="index.php?controller=product">Trà thảo dược</a></li>
<li><a href="index.php?controller=static_page&action=guide">Hướng dẫn mua hàng</a></li>
<li><a href="index.php?controller=news">Tin tức</a></li>
<li><a href="index.php?controller=static_page&action=agency_register">Đăng ký làm đại lý</a></li>
<li><a href="https://www.facebook.com/QuynhPhuongHerbalTea/" target="_blank">Fanpage</a></li>
<li><a href="index.php?controller=static_page&action=intro">Giới thiệu</a></li>
</ul>
</div>
<!-- MENU -->
<div class="clr"></div>
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
loadview("salesmanager/news/form", $data);
loadview("layouts/footer");
<file_sep><?php
loadview("layouts/header", $data);
?>
<div id="buy_product_guide" style="width: 1000px; margin: auto; min-height: 252px;">
<h2>Hướng dẫn mua hàng</h2>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
if(isset($_GET['action'])) {
switch($_GET['action']) {
case "show": require("controllers/news/show.php"); break;
}
} else {
require("controllers/news/index.php");
}
<file_sep><?php
loadview("layouts/header", $data);
?>
<script type="text/javascript">
$(document).ready(function(){
$("#user_product_filter").change(function(){
oeid = $("#user_product_filter").val();
$("#products_filter form").attr("action", "index.php?controller=product&page=1&oeid="+oeid+"");
$("#products_filter form").submit();
});
});
</script>
<div id="list_products_page" style="min-height: 252px;">
<div id="products_filter">
<form method="post">
<span>Hiển thị sản phẩm theo công dụng nổi bật</span>
<select class="form-control" style="width: 350px; float: left;" id="user_product_filter">
<option value='0'>-- Tất cả --</option>
<?php
if (isset($_GET['oeid'])) {
$choosen_oeid = $_GET['oeid'];
} else {
$choosen_oeid = 0;
}
foreach($data['effect'] as $item){
if ($item['oeid'] == $choosen_oeid) {
echo "<option value='$item[oeid]' selected='selected'>$item[content]</option>";
} else {
echo "<option value='$item[oeid]'>$item[content]</option>";
}
}
?>
</select>
</form>
</div>
<div id="products_list">
<?php
if(empty($data['product'])){
echo "<p style='margin: 10px; font-size: 12pt;'>Chưa có sản phẩm nào</p>";
}else{
foreach($data['product'] as $item){
echo "<div class='product'>";
echo "<a href='index.php?controller=product&action=show&pid=$item[pid]'>";
echo "<img src='assets/images/products/$item[image]' />";
echo "<h2 class='product_name'>$item[name]</h2>";
echo "<p class='product_price'>".number_format($item['price'])."₫</p>";
echo "</a>";
echo "</div>";
}
}
?>
</div>
<div class="clr"></div>
<nav aria-label="Page navigation" style="position: relative; height: 77px;">
<ul class="pagination" style="position: absolute; right: 0px; bottom: 0px;">
<?php
if ($data['current_page'] == 1) {
echo "<li class='disabled'>";
echo "<span aria-hidden='true'>«</span>";
echo "</li>";
} else {
$prev = $data['current_page'] - 1;
echo "<li>";
if(isset($_GET['oeid'])) {
echo "<a href='index.php?controller=product&page=$prev&oeid=$choosen_oeid' aria-label='Previous'>";
} else {
echo "<a href='index.php?controller=product&page=$prev' aria-label='Previous'>";
}
echo "<span aria-hidden='true'>«</span>";
echo "</a>";
echo "</li>";
}
for ($i = 1; $i <= $data['page']; $i++) {
if ($i == $data['current_page']) {
echo "<li class='active'><a href='javascript: void(0)'>$i</a></li>";
} else {
if(isset($_GET['oeid'])) {
echo "<li><a href='index.php?controller=product&page=$i&oeid=$choosen_oeid'>$i</a></li>";
} else {
echo "<li><a href='index.php?controller=product&page=$i'>$i</a></li>";
}
}
}
if ($data['current_page'] == $data['page']) {
echo "<li class='disabled'>";
echo "<span aria-hidden='true'>»</span>";
echo "</li>";
} else {
$next = $data['current_page'] + 1;
echo "<li>";
if(isset($_GET['oeid'])) {
echo "<a href='index.php?controller=product&page=$next&oeid=$choosen_oeid' aria-label='Next'>";
} else {
echo "<a href='index.php?controller=product&page=$next' aria-label='Next'>";
}
echo "<span aria-hidden='true'>»</span>";
echo "</a>";
echo "</li>";
}
?>
</ul>
</nav>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$nid = $_GET['nid'];
$mnews = new Model_News;
$mnews->deleteNews($nid);
redirect("index.php?controller=salesmanager&resources=news&action=index");
<file_sep><?php
loadview("layouts/header", $data);
?>
<div id="become_agency" style="width: 1000px; margin: auto; min-height: 252px;">
<h2>Đăng ký làm đại lý</h2>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
require("../assets/library/PHPExcel.php");
$objPHPExcel = new PHPExcel();
$objPHPExcel->setActiveSheetIndex(0)
->setCellValue("A1", "Mã sản phẩm")
->setCellValue("B1", "Tên sản phẩm")
->setCellValue("C1", "Giá")
->setCellValue("D1", "Số lượng")
->setCellValue("E1", "Quy cách đóng gói")
->setCellValue("F1", "Mô tả")
->setCellValue("G1", "Ngày nhập kho")
->setCellValue("H1", "Điểm bình chọn")
->setCellValue("I1", "Số lần bình chọn")
->setCellValue("J1", "Đã bán")
->setCellValue("K1", "Mã công dụng nổi bật");
$conn = mysql_connect("localhost", "root", "");
mysql_select_db("herbal_tea", $conn);
mysql_set_charset("utf8", $conn);
$result = mysql_query("SELECT * FROM products");
$product_info = "";
while ($data = mysql_fetch_assoc($result)) {
$product_info[] = $data;
}
//set gia tri cho cac cot du lieu
$i = 2;
$packing_method = "";
foreach ($product_info as $item) {
switch ($item['packing_method']) {
case "1": $packing_method = "Lọ thuỷ tinh"; break;
case "2": $packing_method = "Gói to"; break;
case "3": $packing_method = "Gói nhỏ"; break;
}
$objPHPExcel->setActiveSheetIndex(0)
->setCellValue("A".$i, $item['pid'])
->setCellValue("B".$i, $item['name'])
->setCellValue("C".$i, $item['price'])
->setCellValue("D".$i, $item['quantity'])
->setCellValue("E".$i, $packing_method)
->setCellValue("F".$i, $item['description'])
->setCellValue("G".$i, date("d/m/Y H:i", strtotime($item['created_at'])))
->setCellValue("H".$i, $item['rating'])
->setCellValue("I".$i, $item['rating_times'])
->setCellValue("J".$i, $item['sold'])
->setCellValue("K".$i, $item['oeid']);
$i++;
}
//ghi du lieu vao file, định dạng file excel 2007
$objWriter = PHPExcel_IOFactory::createWriter($objPHPExcel, "Excel2007");
$full_path = "../assets/export/product.xlsx";//duong dan file
$objWriter->save($full_path);
// download file vua duoc tao ra
// mo file o che do doc nhi phan
$fn = "product.xlsx";
// mo file o che do doc nhi phan
$f = fopen("../assets/export/".$fn, "rb");
// bao cho trinh duyet biet noi dung tra ve o dang nhi phan
header("Content-Type:application/octet-stream");
// thong bao dung luong file muon download
header("Content-Length:".filesize("../assets/export/$fn"));
// thong bao ten file va file can duoc download chu ko mo truc tiep tren trinh duyet
header("Content-Disposition:attachment; filename=$fn");
// doc noi dung file va tra lai cho tirnh duyet xu ly
fpassthru($f);
// ket thuc download, dong file
fclose($f);
header("location:index.php?controller=salesmanager&resources=product");
exit();
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<div id="add_edit_product_interface">
<?php
echo "<form action='index.php?controller=salesmanager&resources=product&action=edit&pid=".$data['product']['pid']."&page=$data[current_page]' method='post' enctype='multipart/form-data'>";
?>
<form action="index.php?controller=salesmanager&resources=product&action=edit&pid=<?php echo $data['product']['pid']; ?>" method="post" enctype="multipart/form-data">
<table>
<tr>
<td style="width: 130px;">Tên sản phẩm</td>
<td><input type="text" name="txtname" class="form-control" style="width: 400px;" value="<?php echo $data['product']['name']; ?>" /></td>
</tr>
<tr>
<td>Công dụng nổi bật</td>
<td>
<select name="outstanding_effect" class="form-control" style="width: 400px;">
<?php
foreach($data['effect'] as $item){
if($data['product']['oeid'] == $item['oeid']){
echo "<option value='$item[oeid]' selected='selected'>$item[content]</option>";
}else{
echo "<option value='$item[oeid]'>$item[content]</option>";
}
}
?>
</select>
</td>
</tr>
<tr>
<td>Quy cách đóng gói</td>
<td>
<select name="packing_method" class="form-control" style="width: 150px;">
<option value='1' <?php if($data['product']['packing_method'] == 1) echo "selected='selected'"; ?>>Lọ thuỷ tinh</option>
<option value='2' <?php if($data['product']['packing_method'] == 2) echo "selected='selected'"; ?>>Gói to</option>
<option value='3' <?php if($data['product']['packing_method'] == 3) echo "selected='selected'"; ?>>Gói nhỏ</option>
</select>
</td>
</tr>
<tr>
<td>Giá</td>
<td><input type="text" name="price" class="form-control" style="width: 90px; float: left;" value="<?php echo $data['product']['price']; ?>" /> <span style="float: left; padding: 7px;">đồng</span></td>
</tr>
<tr>
<td>Hình ảnh</td>
<td>
<img src="assets/images/products/<?php echo $data['product']['image']; ?>" style="width: 400px; height: 300px;">
</td>
</tr>
<tr>
<td>Chọn ảnh khác</td>
<td><input type="file" name="image" /></td>
</tr>
<tr>
<td>Mô tả chi tiết</td>
<td>
<textarea rows="15" cols="70" class="form-control" style="resize: none;" name="description"><?php echo $data['product']['description']; ?></textarea>
</td>
</tr>
<script type="text/javascript">
CKEDITOR.replace('description');
</script>
<tr>
<td></td>
<td><input type="submit" name="ok" value="Cập nhật thông tin sản phẩm" class="btn btn-primary" /></td>
</tr>
</table>
</form>
<div class="error">
<?php
if(!empty($data['error'])){
echo "<ul>";
foreach($data['error'] as $err){
echo "<li>$err</li>";
}
echo "</ul>";
}
?>
</div>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$maddressregister = new Model_AddressRegister;
$mcommune = new Model_Commune;
$mdistrict = new Model_District;
$mprovince = new Model_Province;
$data['addr'] = $maddressregister->listAddressRegisterByUid($_SESSION['uid']);
if($data['addr'] != "") {
$i = 0;
foreach ($data['addr'] as $item){
$comm_info = $mcommune->getCommuneById($item['commid']);
$data['addr'][$i]['comm_name'] = $comm_info['name'];
$dist_info = $mdistrict->getDistrictById($comm_info['distid']);
$data['addr'][$i]['dist_name'] = $dist_info['name'];
$prov_info = $mprovince->getProvinceById($dist_info['provid']);
$data['addr'][$i]['prov_name'] = $prov_info['name'];
$i++;
}
}
$data['title_tag'] = "Chọn địa chỉ giao hàng";
loadview("cart/shipping", $data);
<file_sep><?php
if(isset($_GET['action'])){
switch($_GET['action']){
case "new": require("controllers/session/new.php"); break;
case "destroy": require("controllers/session/destroy.php"); break;
}
}else{
}
<file_sep><?php
$data = "";
$per_page = 10;
$minvoice = new Model_Invoice;
$minvoice->listInvoice();
$invoices_amount = $minvoice->num_rows();
$data['page'] = ceil($invoices_amount / $per_page);
$minvoice->order("iid", "DESC");
if (isset($_GET['page'])) {
$data['current_page'] = $_GET['page'];
$start = $per_page * ($data['current_page'] - 1);
$minvoice->limit($per_page, $start);
} else {
$minvoice->limit($per_page);
$data['current_page'] = 1;
}
$data['invoice'] = $minvoice->listInvoice();
$data['title_tag'] = "Danh sách đơn hàng";
loadview("salesmanager/invoice/index", $data);
<file_sep><?php
$data = "";
$addrid = $_GET['addrid'];
$maddressregister = new Model_AddressRegister;
$data['addr'] = $maddressregister->getAddressRegisterById($addrid);
$mcommune = new Model_Commune;
$comm_info = $mcommune->getCommuneById($data['addr']['commid']);
$data['addr']['distid'] = $comm_info['distid'];
$data['commune'] = $mcommune->listCommuneByDistid($comm_info['distid']);
$mdistrict = new Model_District;
$dist_info = $mdistrict->getDistrictById($comm_info['distid']);
$data['addr']['provid'] = $dist_info['provid'];
$data['district'] = $mdistrict->listDistrictByProvid($dist_info['provid']);
$mprovince = new Model_Province;
$data['province'] = $mprovince->listProvince();
if(isset($_POST['ok'])) {
$fullname = $telephone = $province = $district = $commune = $address = "";
if(empty($_POST['fullname'])){
$data['error'][] = "Họ tên không được để trống";
}else{
$fullname = $_POST['fullname'];
}
if(empty($_POST['telephone'])){
$data['error'][] = "Số điện thoại không được để trống";
}else{
$telephone = $_POST['telephone'];
}
if($_POST['province'] == 0){
$data['error'][] = "Chưa chọn tỉnh/thành";
} else {
$province = $_POST['province'];
}
if($_POST['district'] == 0){
$data['error'][] = "Chưa chọn quận/huyện";
} else {
$district = $_POST['district'];
}
if($_POST['commune'] == 0){
$data['error'][] = "Chưa chọn xã/phường";
}else{
$commune = $_POST['commune'];
}
if(empty($_POST['address'])){
$data['error'][] = "Địa chỉ không được để trống";
}else{
$address = $_POST['address'];
}
if ($fullname && $telephone && $province && $district && $commune && $address) {
$update_data = array(
"fullname" => $fullname,
"telephone"=> $telephone,
"address" => $address,
"commid" => $commune
);
$maddressregister->updateAddressRegister($update_data);
redirect("index.php?controller=user&uid=".$data['addr']['uid']."");
}
}
$data['title_tag'] = "Chỉnh sửa địa chỉ";
loadview("user/address/new", $data);
<file_sep><?php
$pid = $_GET['pid'];
$current_page = $_GET['page'];
$mproduct = new Model_Product;
$mproduct->deleteProduct($pid);
redirect("index.php?controller=salesmanager&resources=product&page=$current_page");
<file_sep><?php
if(isset($_GET['action'])){
switch($_GET['action']){
case "index": require("controllers/salesmanager/news/index.php"); break;
case "new": require("controllers/salesmanager/news/new.php"); break;
case "destroy": require("controllers/salesmanager/news/destroy.php"); break;
case "edit": require("controllers/salesmanager/news/edit.php"); break;
}
}else{
require("controllers/salesmanager/news/index.php");
}
<file_sep><?php
move_uploaded_file($_FILES['import_data']['tmp_name'], "../assets/import/product.xlsx");
require("../assets/library/PHPExcel.php");
$conn = mysql_connect("localhost", "root", "");
mysql_select_db("herbal_tea", $conn);
mysql_set_charset("utf8", $conn);
$filename = "../assets/import/product.xlsx";
$inputFileType = PHPExcel_IOFactory::identify($filename);
$objReader = PHPExcel_IOFactory::createReader($inputFileType);
$objReader->setReadDataOnly(true);
/** Load $filename to a PHPExcel Object **/
$objPHPExcel = $objReader->load("$filename");
$total_sheets = $objPHPExcel->getSheetCount();
$allSheetName = $objPHPExcel->getSheetNames();
$objWorksheet = $objPHPExcel->setActiveSheetIndex(0);
$highestRow = $objWorksheet->getHighestRow();
$highestColumn = $objWorksheet->getHighestColumn();
$highestColumnIndex = PHPExcel_Cell::columnIndexFromString($highestColumn);
$arraydata = array();
for ($row = 2; $row <= $highestRow;++$row) {
for ($col = 0; $col <$highestColumnIndex;++$col) {
$value=$objWorksheet->getCellByColumnAndRow($col, $row)->getValue();
$arraydata[$row-2][$col]=$value;
}
}
// update products table
$oe_change = "";
$sql = "SELECT oeid, products_amount FROM outstanding_effects";
$query = mysql_query($sql);
while ($data_oe = mysql_fetch_assoc($query)) {
$key = $data_oe['oeid'];
$amount = $data_oe['products_amount'];
$oe_change[$key] = $amount;
}
foreach ($arraydata as $item) {
switch ($item[4]) {
case "Lọ thuỷ tinh": $item[4] = 1; break;
case "Gói to": $item[4] = 2; break;
case "Gói nhỏ": $item[4] = 3; break;
}
if (empty($item[0])) {
// them san pham moi
$oe_change[1] += $item[3];
$sql = "INSERT INTO products(name, price, quantity, packing_method, description) VALUES('$item[1]', '$item[2]', '$item[3]', '$item[4]', '$item[5]')";
} else {
// chinh sua san pham
$sql = "SELECT price, quantity FROM products WHERE pid='$item[0]'";
$query = mysql_query($sql);
$data_pr = mysql_fetch_assoc($query);
$diff_quantity = $item[3] - $data_pr['quantity'];
$diff_price = $item[2] - $data_pr['price'];
if ($diff_quantity != 0) {
$key = $item[10];
$oe_change[$key] += $diff_quantity;
if ($diff_price != 0) {
// cap nhat bang invoices va bang invoice_details
$sql = "SELECT invoices.iid, idid, total, price, quantity FROM invoices INNER JOIN invoice_details ON invoices.iid = invoice_details.iid WHERE status='1' AND pid='$item[0]'";
$query = mysql_query($sql); // co the co nhieu ban ghi
while ($update_cart = mysql_fetch_assoc($query)) {
$sql = "UPDATE invoice_details SET price='$item[2]' WHERE idid='$update_cart[idid]'";
mysql_query($sql);
$new_total = $update_cart['total'] + $diff_price * $update_cart['quantity'];
$sql = "UPDATE invoices SET total='$new_total' WHERE iid='$update_cart[iid]'";
mysql_query($sql);
}
$sql = "UPDATE products SET name='$item[1]', price='$item[2]', quantity='$item[3]', packing_method='$item[4]', description='$item[5]' WHERE pid='$item[0]'";
} else {
$sql = "UPDATE products SET name='$item[1]', quantity='$item[3]', packing_method='$item[4]', description='$item[5]' WHERE pid='$item[0]'";
}
} else {
if ($diff_price != 0) {
// cap nhat bang invoices va bang invoice_details
$sql = "SELECT invoices.iid, idid, total, price, quantity FROM invoices INNER JOIN invoice_details ON invoices.iid = invoice_details.iid WHERE status='1' AND pid='$item[0]'";
$query = mysql_query($sql); // co the co nhieu ban ghi
while ($update_cart = mysql_fetch_assoc($query)) {
$sql = "UPDATE invoice_details SET price='$item[2]' WHERE idid='$update_cart[idid]'";
mysql_query($sql);
$new_total = $update_cart['total'] + $diff_price * $update_cart['quantity'];
$sql = "UPDATE invoices SET total='$new_total' WHERE iid='$update_cart[iid]'";
mysql_query($sql);
}
$sql = "UPDATE products SET name='$item[1]', price='$item[2]', packing_method='$item[4]', description='$item[5]' WHERE pid='$item[0]'";
} else {
$sql = "UPDATE products SET name='$item[1]', packing_method='$item[4]', description='$item[5]' WHERE pid='$item[0]'";
}
}
}
mysql_query($sql);
}
// update outstanding_effects table
foreach ($oe_change as $k => $v) {
$sql = "UPDATE outstanding_effects SET products_amount='$v' WHERE oeid='$k'";
mysql_query($sql);
}
header("location:http://localhost/www/herbal_tea/index.php?controller=salesmanager&resources=product");
exit();
<file_sep><?php
loadview("cart/order");
<file_sep><?php
loadview("layouts/header", $data);
?>
<div id="about_us" style="width: 1000px; margin: auto; min-height: 252px;">
<h2>Giới thiệu</h2>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
class Model_User extends Model{
protected $_table = "users";
public function addUser($data){
$this->insert($this->_table, $data);
}
public function checkUser(){
$this->getData($this->_table);
if($this->num_rows() == 1){
return false;
}else{
return true;
}
}
public function listUser(){
$this->getData($this->_table);
return $this->fetchAll();
}
public function deleteUser($id){
$this->where("uid = '$id'");
$this->delete($this->_table);
}
public function updateUser($data){
$this->update($this->_table, $data);
}
public function showUser(){
$this->getData($this->_table);
return $this->fetch();
}
public function countUser() {
$this->getData($this->_table);
return $this->num_rows();
}
}
<file_sep><?php
$current_page = $_GET['page'];
$muser = new Model_User;
$maddressregister = new Model_AddressRegister;
if (isset($_GET['uid'])) {
$uid = $_GET['uid'];
$muser->deleteUser($uid);
$maddressregister->deletedeleteAddressRegisterByUid($uid);
} else {
$data = $_GET['data'];
$data = json_decode($data, true);
foreach ($data as $item) {
$muser->deleteUser($item);
$maddressregister->deletedeleteAddressRegisterByUid($item);
}
}
redirect("http://localhost/www/herbal_tea/index.php?controller=admin&resources=user&page=$current_page");
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<script type="text/javascript">
$(document).ready(function(){
$(".icon_delete").click(function(){
var sold = $(this).next("input[type='hidden']").val();
if (sold > 0) {
alert("Không thể xoá sản phẩm đã được bán ra");
return false;
} else {
if(!window.confirm("Chắc chắn muốn xoá sản phẩm này?")){
return false;
}
}
});
});
</script>
<div id="other_action">
<form id="product_filter">
<table>
<tr>
<td colspan="2"><i>Tiêu chí hiển thị sản phẩm:</i></td>
</tr>
<tr>
<td style="padding: 0 40px 0 5px;">Tình trạng</td>
<td style="padding-bottom: 0;">Số lượng đã bán</td>
</tr>
<tr>
<td style="padding-right: 40px;">
<select class="form-control">
<option>-- Tất cả --</option>
<option style="color: #0362C5; font-weight: bold;">còn hàng</option>
<option style="color: #EC971F; font-weight: bold;">sắp hết</option>
<option style="color: #C9302C; font-weight: bold;">hết hàng</option>
</select>
</td>
<td>
<select class="form-control">
<option>-----</option>
<option>nhiều nhất > ít nhất</option>
<option>ít nhất > nhiều nhất</option>
</select>
</td>
</tr>
</table>
</form>
<form id="search_product">
<table>
<tr>
<td><i>Tìm kiếm sản phẩm</i></td>
<td><input type="text" name="" class="form-control" placeholder="Nhập tên sản phẩm" /></td>
<td><input type="submit" name="ok" value="Tìm" class="btn btn-primary" /></td>
</tr>
</table>
</form>
<script type="text/javascript">
$(document).ready(function(){
$("#import_submit").click(function(){
file_name = $("#import_file").val();
if(file_name == ""){
alert("Vui lòng chọn file để nhập dữ liệu");
return false;
}
});
});
</script>
<form id="import_product" action="models/import.php" method="post" enctype="multipart/form-data">
<table>
<tr>
<td><i>Nhập liệu từ file Excel</i></td>
<td><input type="file" name="import_data" id="import_file" /></td>
<td><input type="submit" name="ok" value="Nhập liệu" class="btn btn-primary" id="import_submit" /></td>
</tr>
</table>
</form>
</div>
<div class="clr"></div>
<div id="product_list">
<a href="index.php?controller=salesmanager&resources=product&action=new" class="btn btn-success">Thêm</a>
<a href="models/export.php" class="btn btn-danger" style="margin-left: 30px;">Xuất dữ liệu ra file Excel</a>
<table class="table table-hover table-bordered">
<thead>
<tr>
<th class="index">STT</th>
<th class="product_name">Tên sản phẩm</th>
<th class="product_price">Giá</th>
<th class="product_status">Tình trạng</th>
<th class="sold_quantity">Đã bán</th>
<th class="current_quantity">Hiện có</th>
<th class="update_quantity" style="padding-bottom: 8px;">Cập nhật số lượng</th>
<th class="edit">Sửa</th>
<th class="del">Xoá</th>
<th class="check"> </th>
</tr>
</thead>
<tbody>
<?php
if(empty($data['product'])){
echo "<tr>";
echo "<td colspan='10'>Chưa có sản phẩm nào</td>";
echo "</tr>";
}else{
$stt = ($data['current_page'] - 1) * 10 + 1;
foreach($data['product'] as $item){
echo "<tr>";
echo "<td>$stt</td>";
echo "<td>$item[name]</td>";
if($item['packing_method'] == 1){
echo "<td>".number_format($item['price'])." <span style='color: red;'>₫</span> / lọ thuỷ tinh</td>";
}elseif($item['packing_method'] == 2){
echo "<td>".number_format($item['price'])." <span style='color: red;'>₫</span> / gói to</td>";
}else{
echo "<td>".number_format($item['price'])." <span style='color: red;'>₫</span> / gói nhỏ</td>";
}
if($item['quantity'] > 50){
echo "<td><span class='remain'>còn hàng</span></td>";
}elseif((0 < $item['quantity']) && ($item['quantity'] <= 50)){
echo "<td><span class='running_out'>sắp hết</span></td>";
}else{
echo "<td><span class='out_of_stock'>hết hàng</span></td>";
}
echo "<td>".number_format($item['sold'])."</td>";
echo "<td>".number_format($item['quantity'])."</td>";
echo "<td><a href='index.php?controller=salesmanager&resources=product&action=quantity_update&pid=$item[pid]&page=$data[current_page]'><span class='icon_update'></span></a></td>";
echo "<td><a href='index.php?controller=salesmanager&resources=product&action=edit&pid=$item[pid]&page=$data[current_page]'><span class='icon_edit'></span></a></td>";
echo "<td><a href='index.php?controller=salesmanager&resources=product&action=destroy&pid=$item[pid]&page=$data[current_page]'><span class='icon_delete'></span><input type='hidden' value='$item[sold]'></a></td>";
echo "<td><input type='checkbox' /></td>";
echo "</tr>";
$stt++;
}
}
?>
</tbody>
</table>
<nav aria-label="Page navigation" style="position: relative; height: 77px;">
<ul class="pagination" style="position: absolute; right: 0px; bottom: 0px;">
<?php
if ($data['current_page'] == 1) {
echo "<li class='disabled'>";
echo "<span aria-hidden='true'>«</span>";
echo "</li>";
} else {
$prev = $data['current_page'] - 1;
echo "<li>";
echo "<a href='index.php?controller=salesmanager&resources=product&page=$prev' aria-label='Previous'>";
echo "<span aria-hidden='true'>«</span>";
echo "</a>";
echo "</li>";
}
for ($i = 1; $i <= $data['page']; $i++) {
if ($i == $data['current_page']) {
echo "<li class='active'><a href='javascript: void(0)'>$i</a></li>";
} else {
echo "<li><a href='index.php?controller=salesmanager&resources=product&page=$i'>$i</a></li>";
}
}
if ($data['current_page'] == $data['page']) {
echo "<li class='disabled'>";
echo "<span aria-hidden='true'>»</span>";
echo "</li>";
} else {
$next = $data['current_page'] + 1;
echo "<li>";
echo "<a href='index.php?controller=salesmanager&resources=product&page=$next' aria-label='Next'>";
echo "<span aria-hidden='true'>»</span>";
echo "</a>";
echo "</li>";
}
?>
</ul>
</nav>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$uid = $_GET['uid'];
$level = $_GET['level'];
$current_page = $_GET['page'];
$muser = new Model_User;
$muser->where("uid = '$uid'");
if($level == 1){
$data = array("level" => "2");
}else{
$data = array("level" => "1");
}
$muser->updateUser($data);
redirect("http://localhost/www/herbal_tea/index.php?controller=admin&resources=user&page=$current_page");
<file_sep><?php
if (isset($_GET['action'])) {
switch ($_GET['action']) {
case "index": require("controllers/user/invoice/index.php"); break;
case "show": require("controllers/user/invoice/show.php"); break;
}
} else {
require("controllers/user/invoice/index.php");
}
<file_sep><?php
$qid = $_GET['qid'];
$mquestion = new Model_Question;
$data['question'] = $mquestion->getQuestionByQid($qid);
if(isset($_POST['ok'])) {
$answer = $_POST['reply'];
$manswer = new Model_Answer;
$input_data = array("content" => $answer, "qid" => $qid);
$manswer->addAnswer($input_data);
$update_question = array("is_responded" => "1");
$mquestion->updateQuestion($update_question);
redirect("index.php?controller=salesmanager&resources=ask_and_answer");
}
$data['title_tag'] = "Trả lời khách hàng";
loadview("salesmanager/ask_and_answer/answer", $data);
<file_sep><?php
if(isset($_GET['action'])){
switch($_GET['action']){
case "add_product": require("controllers/cart/add_product.php"); break;
case "destroy_product": require("controllers/cart/destroy_product.php"); break;
case "edit": require("controllers/cart/edit.php"); break;
case "shipping": require("controllers/cart/shipping.php"); break;
case "payment": require("controllers/cart/payment.php"); break;
case "order": require("controllers/cart/order.php"); break;
}
}else{
require("controllers/cart/show.php");
}
<file_sep><?php
$level = $_GET['level'];
$muser = new Model_User;
$muser->order("uid", "DESC");
if($level != 0){
$muser->where("level = '$level'");
}
$data = $muser->listUser();
?>
<table class="table table-hover table-bordered">
<thead>
<tr>
<th class='index'>STT</th>
<th class='name'>Tên</th>
<th class='email'>Email</th>
<th class='level'>Loại tài khoản</th>
<th class='change_level'>Chuyển đổi tài khoản</th>
<th class='del'>Xoá</th>
<th class='check'></th>
</tr>
</thead>
<tbody>
<?php
if($data == ""){
echo "<tr>";
echo "<td colspan='8'>Không có dữ liệu</td>";
echo "</tr>";
}else{
$stt = 1;
foreach($data as $item){
echo "<tr>";
echo "<td>$stt</td>";
echo "<td>$item[name]</td>";
echo "<td>$item[email]</td>";
if($item['level'] == 1){
echo "<td>Thường</td>";
echo "<td><a href='index.php?controller=admin/user&action=edit&uid=$item[uid]&level=$item[level]' onclick='return check_change_level();'><span class='icon_change_level'></span></td>";
echo "<td><a href='index.php?controller=admin/user&action=destroy&uid=$item[uid]' onclick='return check_delete();'><span class='icon_delete'></span></a></td>";
echo "<td><input type='checkbox'></td>";
}elseif($item['level'] == 2){
echo "<td style='color: blue; font-weight: bold;'>Quản lý bán hàng</td>";
echo "<td><a href='index.php?controller=admin/user&action=edit&uid=$item[uid]&level=$item[level]' onclick='return check_change_level();'><span class='icon_change_level'></span></td>";
echo "<td> </td>";
echo "<td> </td>";
}else{
echo "<td style='color: red; font-weight: bold;'>Quản trị viên</td>";
echo "<td> </td>";
echo "<td> </td>";
echo "<td> </td>";
}
echo "</tr>";
$stt++;
}
}
?>
</tbody>
</table>
<file_sep><?php
loadview("layouts/header", $data);
?>
<div style="min-height: 257px;">
<form id="login_form" action="index.php?controller=session&action=new" method="post">
<?php
if(!empty($data['error'])){
echo "<div class='error'>";
echo "<ul>";
foreach($data['error'] as $err){
echo "<li>$err</li>";
}
echo "</ul>";
echo "</div>";
}
?>
<table>
<tr>
<td>Email <span style='color: red;'>*</span></td>
<td style="width: 300px;"><input type="text" name="txtemail" class="form-control"></td>
</tr>
<tr>
<td>Mật khẩu <span style='color: red;'>*</span></td>
<td style="width: 300px;"><input type="password" name="txtpass" class="form-control"></td>
</tr>
<tr>
<td style="padding-top: 0;"></td>
<td style="padding-top: 0;"><a href="#">Quên mật khẩu?</a></td>
</tr>
<tr>
<td></td>
<td><input type="submit" name="ok" value="Đăng nhập" class="btn btn-info"></td>
</tr>
<tr>
<td></td>
<td>Chưa có tài khoản? <a href="index.php?controller=user&action=signup">Đăng ký</a></td>
</tr>
</table>
</form>
</div>
<?php
if(isset($data['err'])){
foreach($data['err'] as $value){
echo "$value<br />";
}
}
loadview("layouts/footer");
?>
<file_sep><?php
$data = "";
$mnews = new Model_News;
$mnews->order("nid", "DESC");
$data['news'] = $mnews->listNews();
$data['title_tag'] = "Tin tức";
loadview("news/index", $data);
<file_sep><?php
$provid = $_GET['provid'];
$mdistrict = new Model_District;
$data['district'] = $mdistrict->listDistrictByProvid($provid);
echo "<option value='0'>Chọn Quận/Huyện</option>";
foreach ($data['district'] as $item){
echo "<option value='$item[distid]'>$item[name]</option>";
}
<file_sep><?php
$data = "";
$data['addr'] = "";
$iid = $_GET['iid'];
$minvoice = new Model_Invoice;
$minvoice->select("products_amount, total, addrid");
$data['invoice'] = $minvoice->getInvoiceByIid($iid);
if ($data['invoice']['addrid'] != 0) {
$maddressregister = new Model_AddressRegister;
$data['addr'] = $maddressregister->getAddressRegisterById($data['invoice']['addrid']);
$mcommune = new Model_Commune;
$data['comm_info'] = $mcommune->getCommuneById($data['addr']['commid']);
$data['addr']['comm_name'] = $data['comm_info']['name'];
$mdistrict = new Model_District;
$data['dist_info'] = $mdistrict->getDistrictById($data['comm_info']['distid']);
$data['addr']['dist_name'] = $data['dist_info']['name'];
$mprovince = new Model_Province;
$data['prov_info'] = $mprovince->getProvinceById($data['dist_info']['provid']);
$data['addr']['prov_name'] = $data['prov_info']['name'];
}
$minvoicedetail = new Model_InvoiceDetail;
$minvoicedetail->select("name, price, quantity, pid");
$minvoicedetail->order("idid", "DESC");
$data['product'] = $minvoicedetail->listInvoiceDetail($iid);
$data['title_tag'] = "Chi tiết đơn hàng thành viên";
loadview("user/invoice/show", $data);
<file_sep><?php
if(isset($_GET['action'])){
switch($_GET['action']){
case "answer": require("controllers/salesmanager/ask_and_answer/answer.php"); break;
}
}else{
require("controllers/salesmanager/ask_and_answer/index.php");
}
<file_sep><?php
if(isset($_GET['action'])){
switch($_GET['action']){
case "index": require("controllers/salesmanager/product/index.php"); break;
case "new": require("controllers/salesmanager/product/new.php"); break;
case "destroy": require("controllers/salesmanager/product/destroy.php"); break;
case "edit": require("controllers/salesmanager/product/edit.php"); break;
case "quantity_update": require("controllers/salesmanager/product/quantity_update.php"); break;
}
}else{
require("controllers/salesmanager/product/index.php");
}
<file_sep><?php
$data = "";
$data['data']['addrid'] = $_POST['addrid'];
$data['data']['fullname'] = $_POST['fullname'];
$data['data']['address'] = $_POST['address'];
$data['data']['comm_name'] = $_POST['comm_name'];
$data['data']['dist_name'] = $_POST['dist_name'];
$data['data']['prov_name'] = $_POST['prov_name'];
$data['data']['telephone'] = $_POST['telephone'];
$minvoicedetail = new Model_InvoiceDetail;
$minvoicedetail->select("name, price, quantity, pid");
$minvoicedetail->order("idid", "DESC");
$data['product'] = $minvoicedetail->listInvoiceDetail($_SESSION['iid']);
if (isset($_POST['ok'])) {
$payment_method = $account_holder = $account_number = $bank = "";
if (empty($_POST['payment_method'])) {
$data['error'][] = "Vui lòng chọn hình thức thanh toán";
} else {
$payment_method = $_POST['payment_method'];
if ($payment_method == 2) {
$data['atm'] = "checking";
if (empty($_POST['account_holder'])) {
$data['error'][] = "Vui lòng điền tên chủ tài khoản";
} else {
$account_holder = $_POST['account_holder'];
}
if (empty($_POST['account_number'])) {
$data['error'][] = "Vui lòng điền số tài khoản";
} else {
$account_number = $_POST['account_number'];
}
if(empty($_POST['bank'])) {
$data['error'][] = "Vui lòng nhập tên ngân hàng";
} else {
$bank = $_POST['bank'];
}
} else {
$account_holder = $account_number = $bank = "none";
}
}
if ($payment_method && $account_holder && $account_number && $bank) {
// update invoices table
$update_invoices = array(
"payment_method" => $payment_method,
"status" => "2",
"addrid" => $data['data']['addrid'],
"order_date" => date("Y:m:d H:i:s")
);
if ($payment_method == 2) {
$update_invoices['account_holder'] = $account_holder;
$update_invoices['account_number'] = $account_number;
$update_invoices['bank'] = $bank;
}
$minvoice = new Model_Invoice;
$minvoice->where("iid = '$_SESSION[iid]'");
$minvoice->updateInvoice($update_invoices);
// update products table and outstanding_effects
$mproduct = new Model_Product;
$meffect = new Model_Effect;
foreach ($data['product'] as $p) {
$oeid = $mproduct->updateAfterOrder($p['pid'], $p['quantity']);
$meffect->updateAfterOrder($oeid, $p['quantity']);
}
$_SESSION['iid'] = 0;
$_SESSION['products_amount'] = 0;
$_SESSION['total'] = 0;
redirect("index.php?controller=cart&action=order");
}
}
$data['title_tag'] = "Thanh toán";
loadview("cart/payment", $data);
<file_sep><?php
if(isset($_SESSION['level']) && ($_SESSION['level'] == 2)){
if(isset($_GET['resources'])){
switch($_GET['resources']){
case "product": require("controllers/salesmanager/product/product.php"); break;
case "effect": require("controllers/salesmanager/effect/effect.php"); break;
case "invoice": require("controllers/salesmanager/invoice/invoice.php"); break;
case "request": require("controllers/salesmanager/request/request.php"); break;
case "news": require("controllers/salesmanager/news/news.php"); break;
case "ask_and_answer": require("controllers/salesmanager/ask_and_answer/ask_and_answer.php"); break;
case "remark": require("controllers/salesmanager/remark/remark.php"); break;
}
}else{
require("controllers/salesmanager/mainpage.php");
}
}else{
if(isset($_SESSION['level']) && ($_SESSION['level'] == 3)){
redirect("http://localhost/www/herbal_tea/index.php?controller=admin");
}else{
redirect("http://localhost/www/herbal_tea/");
}
}
<file_sep><?php
loadview("layouts/simple_header", $data);
loadview("salesmanager/nav_bar");
?>
<script type="text/javascript">
function check_delete_news(){
if (!window.confirm("Bạn chắc chắn muốn xoá bài viết này?")) return false;
}
</script>
<div id="news_list">
<a href="index.php?controller=salesmanager&resources=news&action=new" class="btn btn-success" style="margin-bottom: 20px;">Thêm bài viết mới</a>
<table class="table table-hover table-bordered" style="width: 700px;">
<thead>
<tr>
<th style="width: 50px;">STT</th>
<th style="width: 160px;">Ngày đăng bài</th>
<th>Tiêu đề</th>
<th style="width: 50px;">Sửa</th>
<th style="width: 50px;">Xoá</th>
</tr>
</thead>
<tbody>
<?php
if (empty($data['news'])) {
echo "<tr>";
echo "<td colspan='5'>Chưa có bài viết nào</td>";
echo "</tr>";
} else {
$stt = 1;
foreach ($data['news'] as $item) {
echo "<tr>";
echo "<td>$stt</td>";
$timestamp = strtotime($item['created_at']);
echo "<td>".date("H:i", $timestamp)." ngày ".date("d/m/Y", $timestamp)."</td>";
echo "<td>$item[title]</td>";
echo "<td><a href='index.php?controller=salesmanager&resources=news&action=edit&nid=$item[nid]'><span class='icon_edit'></span></a></td>";
echo "<td><a href='index.php?controller=salesmanager&resources=news&action=destroy&nid=$item[nid]' onclick='return check_delete_news();'><span class='icon_delete'></span></a></td>";
echo "</tr>";
$stt++;
}
}
?>
</tbody>
</table>
</div>
<?php
loadview("layouts/footer");
?>
<file_sep><?php
$remid = $_GET['remid'];
$mremark = new Model_Remark;
$mremark->where("remid = '$remid'");
$update_data = array("is_approved" => "1");
$mremark->updateRemark($update_data);
$mremark->select("rating, pid");
$remark_info = $mremark->getRemarkByRemid($remid);
$mproduct = new Model_Product;
$mproduct->updateAfterAcceptRemark($remark_info['pid'], $remark_info['rating']);
redirect("index.php?controller=salesmanager&resources=remark&action=index");
<file_sep><?php
class Model_AddressRegister extends Model{
protected $_table = "address_registers";
public function addAddressRegister($data){
$this->insert($this->_table, $data);
}
public function listAddressRegisterByUid($uid){
$this->where("uid = '$uid'");
$this->getData($this->_table);
return $this->fetchAll();
}
public function deleteAddressRegister($id){
$this->where("addrid = '$id'");
$this->delete($this->_table);
}
public function getAddressRegisterById($id){
$this->where("addrid = '$id'");
$this->getData($this->_table);
return $this->fetch();
}
public function updateAddressRegister($data){
$this->update($this->_table, $data);
}
public function deletedeleteAddressRegisterByUid($uid) {
$this->where("uid = '$uid'");
$this->delete($this->_table);
}
}
<file_sep><?php
$iid = $_GET['iid'];
$current_page = $_GET['page'];
$minvoice = new Model_Invoice;
$minvoice->updateInvoiceStatus($iid);
redirect("index.php?controller=salesmanager&resources=invoice&page=$current_page");
<file_sep><?php
session_destroy();
redirect("http://localhost/www/herbal_tea/");
| b9180755342f51cdaa2361cdf1b5702574a38886 | [
"JavaScript",
"Markdown",
"PHP"
] | 126 | PHP | hungnh103/herbal_tea | fb0226d56094104ac8f8be1543fd23cc6f3ec5b6 | 2e6ae05e81c1a47789c858cb54c55fbdbdab2938 |
refs/heads/master | <repo_name>Yasmine-SOUISSI/select-country-state-city-geonames<file_sep>/src/App.js
import React, { useState } from "react";
import { CssBaseline, Container, Grid } from "@material-ui/core/";
import { makeStyles } from "@material-ui/core/styles";
import GeoLocation from "./GeoLocation";
const useStyles = makeStyles(theme => ({
form: {
width: "100%", // Fix IE 11 issue.
marginTop: theme.spacing(3)
}
}));
const App = () => {
const classes = useStyles();
const [country, setCountry] = useState("");
const [state, setState] = useState("");
const [city, setCity] = useState("");
console.log({
country,
state,
city
});
return (
<Container component="main" maxWidth="lg">
<CssBaseline />
<div className={classes.paper}>
<form className={classes.form}>
<Grid container spacing={2}>
<Grid item xs={12} sm={4}>
<GeoLocation
locationTitle="Country"
isCountry
onChange={setCountry}
/>
</Grid>
<Grid item xs={12} sm={4}>
<GeoLocation
locationTitle="State"
onChange={setState}
geoId={country}
/>
</Grid>
<Grid item xs={12} sm={4}>
<GeoLocation
locationTitle="City"
onChange={setCity}
geoId={state}
/>
</Grid>
</Grid>
</form>
</div>
</Container>
);
};
export default App;
| 423b963a9d21e5589a985e0309816659475b5955 | [
"JavaScript"
] | 1 | JavaScript | Yasmine-SOUISSI/select-country-state-city-geonames | e035761626844b246739041bfbef45016ad2d93f | adac2faeb823253cfc99c13cb24f5c4cb663c45d |
refs/heads/master | <repo_name>TimNal/OmitRep<file_sep>/src/fi/taapeli/xmlutils/Test/test_merge_custom_filters.py
'''
Created on 16.11.2016
@author: Timo
'''
from xmlutils import merge_custom_filters
from xmlutils.merge_custom_filters import main
if __name__ == '__main__':
merge_custom_filters.main(["merge_custom_filters", "C:/Temp/filters"])<file_sep>/src/fi/taapeli/xmlutils/merge_custom_filters.py
'''
Created on 13.11.2016
@author: Someone / Timo
'''
#import os, os.path, sys
import sys
import glob
from sys import argv
from xml.etree import ElementTree
def main(argv):
path = argv[1]
xml_files = glob.glob(path +"/*.xml")
xml_element_tree = None
for xml_file in xml_files:
data1 = ElementTree.parse(xml_file)
data = data1.getroot()
# print ElementTree.tostring(data)
for result in data.iter('filters'):
if xml_element_tree is None:
xml_element_tree = data
insertion_point = xml_element_tree.findall("./filters")[0]
else:
insertion_point.extend(result)
if xml_element_tree is not None:
print(ElementTree.tostring(xml_element_tree))
if __name__ == '__main__':
sys.exit(main(argv))
<file_sep>/README.md
# OmitRep
Something for myself only
<file_sep>/src/fi/taapeli/json/BuildGrampsSourcesJson.py
'''
Created on 31.10.2016
@author: Timo
'''
import argparse
import json
def process_input(args):
if args.add_commas: sep = None
outFile = open(args.output_json,"w",encoding=args.encoding)
for line in open(args.input_sources,encoding=args.encoding):
line = line.strip()
tkns = line.split(None,2)
outLine = process_source(args,tkns)
outFile.write(line + "\n")
outFile.close()
def process_source(args,line):
return line
def main():
process_input()
if __name__ == '__main__':
pass
print("Starting...")<file_sep>/src/fi/taapeli/GrampsClasses.py
'''
Created on 31.10.2016
@author: Timo
'''
import json
class Source:
'''
classdocs
'''
def toJSON(self):
return json.dumps(self, default=lambda o: o.__dict__,
sort_keys=True)
def __init__(self):
'''
Constructor
'''
self._class = 'Source'
self.author = ''
self.pubinfo = ''
self.gramps_id = 'S900001'
self.title = 'Angelniemi Kuolleet 1749-1777'
self.change = ''
self.private = 'False'
self.handle = 'd<PASSWORD>'
self.srcattr_list = []
self.note_list = []
self.reporef_list = []<file_sep>/src/fi/taapeli/json/write_json_records1.py
'''
Created on 8.11.2016
@author: Timo
'''
'''
from fi.genealogia.taapeli.jsonutils.CreateGrampsObject import buildTag, \
buildRepository, buildSource
'''
import sys
from fi.genealogia.taapeli.json.CreateGrampsObject import CreateGrampsObject
def give_idno(pfx, idno):
idno =idno + 1
return(pfx + str(idno))
def main(argv = ["aaa", "C:/Temp/"]):
if argv is None:
argv = sys.argv
if len(argv) != 2:
print("Wrong number of arguments")
return 8
tag = None
repository = None
source = None
repository_idno = 500000
source_idno = 500000
fdir = argv[1]
print("File directory for program " + argv[0] + " is " + fdir)
cgo = CreateGrampsObject()
try:
with open(fdir + "JsonIn.json", "w") as j_out:
with open(fdir + "Tags.txt", "r") as t_in:
for line in t_in:
ttext = line.strip('\n ')
# print(ttext)
tag = cgo.buildTag(ttext)
print(tag.to_struct(), file=j_out)
break
with open(fdir + "Repositories.txt", "r") as r_in:
for line in r_in:
rtext = line.strip('\n ')
# print(rtext)
repository_idno = repository_idno + 1
ridno = 'R' + str(repository_idno)
repository = cgo.buildRepository(ridno, rtext, tag, 4)
print(repository.to_struct(), file=j_out)
break
with open(fdir + "Sources.txt", "r") as s_in:
for line in s_in:
stext = line.strip('\n ')
# print(stext)
source_idno = source_idno + 1
sidno = 'S' + str(source_idno)
source = cgo.buildSource(sidno, stext, tag, repository)
print(source.to_struct(), file=j_out)
# break
except IOError:
print(IOError.winerror)
print("IOError in j_out handling")
return 8
if __name__ == '__main__':
sys.exit(main())
| 766058cb720c9f842d9529450b3480be8a23ab94 | [
"Markdown",
"Python"
] | 6 | Python | TimNal/OmitRep | 504b8266b2e71bf9e3793907f560b4bc5a0f8461 | 8e9b3d63826e718a48cc0f3565aa09d6c4daa48b |
refs/heads/master | <repo_name>fluorine21/quantum_time_sync<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_7/src/xusbpsu_local.h
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_local.h
* @addtogroup usbpsu_v1_7
* @{
* @details
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.0 pm 03/23/20 First release
*
* </pre>
*
*****************************************************************************/
#ifndef XUSBPSU_LOCAL_H /* Prevent circular inclusions */
#define XUSBPSU_LOCAL_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xusbpsu.h"
/************************** Constant Definitions *****************************/
#ifdef XUSBPSU_HIBERNATION_ENABLE
#define XUSBPSU_NON_STICKY_SAVE_RETRIES 500U
#define XUSBPSU_PWR_STATE_RETRIES 1500U
#define XUSBPSU_CTRL_RDY_RETRIES 5000U
#define XUSBPSU_TIMEOUT 1000U
#endif
/************************** Function Prototypes ******************************/
/*
* Functions in xusbpsu.c
*/
/** @cond INTERNAL */
s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode);
u8 XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr);
s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
XusbPsuLinkStateChange State);
/** @endcond */
/*
* Functions in xusbpsu_device.c
*/
/** @cond INTERNAL */
s32 XUsbPsu_WaitClearTimeout(struct XUsbPsu *InstancePtr, u32 Offset,
u32 BitMask, u32 Timeout);
s32 XUsbPsu_WaitSetTimeout(struct XUsbPsu *InstancePtr, u32 Offset,
u32 BitMask, u32 Timeout);
u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex);
s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr);
void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr);
/** @endcond */
/*
* Functions in xusbpsu_command.c
*/
/** @cond INTERNAL */
struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr);
s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
u32 Cmd, struct XUsbPsu_EpParams *Params);
/** @endcond */
/*
* Functions in xusbpsu_ephandler.c
*/
/** @cond INTERNAL */
void XUsbPsu_EpTransferDeactive(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
u8 Dir);
void XUsbPsu_SaveEndpointState(struct XUsbPsu *InstancePtr,
struct XUsbPsu_Ep *Ept);
void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event);
void XUsbPsu_EpXferNotReady(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event);
/** @endcond */
/*
* Functions in xusbpsu_endpoint.c
*/
/** @cond INTERNAL */
u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
u8 Dir);
s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum,
u8 Dir);
s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
u16 Size, u8 Type, u8 Restore);
s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
/** @endcond */
/*
* Functions in xusbpsu_controltransfer.c
*/
/** @cond INTERNAL */
void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event);
void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr);
s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size);
s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event);
void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
struct XUsbPsu_Ep *Ept);
void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event);
/** @endcond */
/*
* Functions in xusbpsu_ep0handler.c
*/
/** @cond INTERNAL */
s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr);
void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event);
void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event);
s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr,
u32 BufferLen);
s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length);
/** @endcond */
/*
* Functions in xusbpsu_event.c
*/
/** @cond INTERNAL */
void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr);
void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr);
void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr);
void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr,
u32 EvtInfo);
void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr,
const union XUsbPsu_Event *Event);
/** @endcond */
/*
* Functions in xusbpsu_intr.c
*/
/** @cond INTERNAL */
void XUsbPsu_EpEvent(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event);
void XUsbPsu_DeviceEvent(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Devt *Event);
void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr);
void XUsbPsu_ClearStallAllEp(struct XUsbPsu *InstancePtr);
void XUsbPsu_StopActiveTransfers(struct XUsbPsu *InstancePtr);
/** @endcond */
/*
* Hibernation Functions
*/
#ifdef XUSBPSU_HIBERNATION_ENABLE
/** @cond INTERNAL */
void XUsbPsu_InitHibernation(struct XUsbPsu *InstancePtr);
void XUsbPsu_HibernationIntr(struct XUsbPsu *InstancePtr);
s32 XUsbPsu_SetupScratchpad(struct XUsbPsu *InstancePtr, u8 *ScratchBuf);
s32 XUsbPsu_RestartEp(struct XUsbPsu *InstancePtr, u8 EpNum);
s32 XUsbPsu_RestoreEp0(struct XUsbPsu *InstancePtr);
s32 XUsbPsu_RestoreEps(struct XUsbPsu *InstancePtr);
s32 XUsbPsu_SendGadgetGenericCmd(struct XUsbPsu *InstancePtr, u32 cmd,
u32 param);
void XUsbPsu_HibernationStateIntr(struct XUsbPsu *InstancePtr);
s32 XUsbPsu_CoreRegRestore(struct XUsbPsu *InstancePtr);
/** @endcond */
#endif /* XUSBPSU_HIBERNATION_ENABLE */
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */
/** @} */
<file_sep>/python_drivers/socket_server_test.py
# -*- coding: utf-8 -*-
"""
Created on Mon Jul 6 17:16:49 2020
@author: tianlab01
"""
import socket
s = socket.socket()
host = socket.gethostname() # Get local machine name
s.bind((host, 25565))
#Start listening for a connection
s.listen(5)
c, addr = s.accept()
c.settimeout(2)
print("Got connection")<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_user_startup.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_config.h"
#include "xpfw_core.h"
#include "xpfw_events.h"
#include "xpfw_module.h"
#include "xpfw_user_startup.h"
#include "xpfw_mod_dap.h"
#include "xpfw_mod_legacy.h"
#include "xpfw_mod_em.h"
#include "xpfw_mod_pm.h"
#include "xpfw_mod_rtc.h"
#include "xpfw_mod_sched.h"
#include "xpfw_mod_stl.h"
#include "xpfw_mod_wdt.h"
#include "xpfw_mod_common.h"
#include "xpfw_mod_ultra96.h"
#include "xpfw_mod_rpu.h"
#if defined (XPAR_LPD_IS_CACHE_COHERENT) || defined (XPAR_FPD_IS_CACHE_COHERENT) || defined (XPAR_PL_IS_CACHE_COHERENT)
/*****************************************************************************
*
* Enable the broadcasting of Inner Shareable transactions for APU.
*
* @param None.
*
* @return None.
*
******************************************************************************/
static void XPfw_Enable_Inner_Shareable_Broadcast(void)
{
u32 val = XPfw_Read32(LPD_SLCR_LPD_APU);
val |= (1U << LPD_SLCR_LPD_APU_BRDC_INNER_SHIFT);
XPfw_Write32(LPD_SLCR_LPD_APU , val);
}
#endif
void XPfw_UserStartUp(void)
{
#if defined (XPAR_LPD_IS_CACHE_COHERENT) || defined (XPAR_FPD_IS_CACHE_COHERENT) || defined (XPAR_PL_IS_CACHE_COHERENT)
/*
* LPD/FPD peripheral is configured to use CCI,
* enable the broadcasting of inner shareable transactions
*/
XPfw_Enable_Inner_Shareable_Broadcast();
#endif
ModStlInit();
ModRtcInit();
ModEmInit();
ModPmInit();
(void)ModSchInit();
ModDapInit();
ModLegacyInit();
ModWdtInit();
ModRpuInit();
#ifdef ENABLE_CUSTOM_MOD
/*
* This ModCustomInit function is a placeholder to the user
* for creating his own module. Define the symbol ENABLE_CUSTOM_MOD,
* add the custom source code and recompile the firmware.
* Refer "Creating a custom module" section in
* Chapter:10 platform management unit firmware of UG1137.
*/
ModCustomInit();
#endif
ModUltra96Init();
ModCommonInit();
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/client/pm_defs.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef PM_DEFS_H_
#define PM_DEFS_H_
#include "xpm_nodeid.h"
#include "xpm_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* NOTE: All macros defined in this file is to just maintain the
* compatibility with existing ZynqMP application.
* This macros will be deprecated in future.
*/
#warning This file will be deprecated in future. Please use xpm_defs.h.
#define NODE_APU PM_POWER_ACPU_0
#define NODE_APU_0 PM_DEV_ACPU_0
#define NODE_APU_1 PM_DEV_ACPU_1
#define NODE_RPU PM_POWER_RPU0_0
#define NODE_RPU_0 PM_DEV_RPU0_0
#define NODE_RPU_1 PM_DEV_RPU0_1
#define NODE_PLD PM_POWER_PLD
#define NODE_FPD PM_POWER_FPD
#define NODE_OCM_BANK_0 PM_DEV_OCM_0
#define NODE_OCM_BANK_1 PM_DEV_OCM_1
#define NODE_OCM_BANK_2 PM_DEV_OCM_2
#define NODE_OCM_BANK_3 PM_DEV_OCM_3
#define NODE_TCM_0_A PM_DEV_TCM_0_A
#define NODE_TCM_0_B PM_DEV_TCM_0_B
#define NODE_TCM_1_A PM_DEV_TCM_1_A
#define NODE_TCM_1_B PM_DEV_TCM_1_B
#define NODE_L2 PM_DEV_L2_BANK_0
#define NODE_USB_0 PM_DEV_USB_0
#define NODE_TTC_0 PM_DEV_TTC_0
#define NODE_TTC_1 PM_DEV_TTC_1
#define NODE_TTC_2 PM_DEV_TTC_2
#define NODE_TTC_3 PM_DEV_TTC_3
#define NODE_ETH_0 PM_DEV_GEM_0
#define NODE_ETH_1 PM_DEV_GEM_1
#define NODE_UART_0 PM_DEV_UART_0
#define NODE_UART_1 PM_DEV_UART_1
#define NODE_SPI_0 PM_DEV_SPI_0
#define NODE_SPI_1 PM_DEV_SPI_1
#define NODE_I2C_0 PM_DEV_I2C_0
#define NODE_I2C_1 PM_DEV_I2C_1
#define NODE_SD_0 PM_DEV_SDIO_0
#define NODE_SD_1 PM_DEV_SDIO_1
#define NODE_ADMA PM_DEV_ADMA_0
#define NODE_QSPI PM_DEV_QSPI
#define NODE_GPIO PM_DEV_GPIO
#define NODE_CAN_0 PM_DEV_CAN_FD_0
#define NODE_CAN_1 PM_DEV_CAN_FD_1
#define NODE_APLL PM_CLOCK_APLL
#define NODE_RPLL PM_CLOCK_RPLL
#define NODE_DDR PM_DEV_DDR_0
#define NODE_RTC PM_DEV_RTC
#define NODE_LPD PM_POWER_LPD
#define NODE_PL PM_DEV_PL_0
#define XILPM_RESET_SWDT_CRF PM_RST_SWDT_FPD
#define XILPM_RESET_ACPU1_PWRON PM_RST_ACPU_1_POR
#define XILPM_RESET_ACPU0_PWRON PM_RST_ACPU_0_POR
#define XILPM_RESET_APU_L2 PM_RST_ACPU_L2
#define XILPM_RESET_ACPU1 PM_RST_ACPU_1
#define XILPM_RESET_ACPU0 PM_RST_ACPU_0
#define XILPM_RESET_GEM0 PM_RST_GEM_0
#define XILPM_RESET_GEM1 PM_RST_GEM_1
#define XILPM_RESET_QSPI PM_RST_QSPI
#define XILPM_RESET_UART0 PM_RST_UART_0
#define XILPM_RESET_UART1 PM_RST_UART_1
#define XILPM_RESET_SPI0 PM_RST_SPI_0
#define XILPM_RESET_SPI1 PM_RST_SPI_1
#define XILPM_RESET_SDIO0 PM_RST_SDIO_0
#define XILPM_RESET_SDIO1 PM_RST_SDIO_1
#define XILPM_RESET_CAN0 PM_RST_CAN_FD_0
#define XILPM_RESET_CAN1 PM_RST_CAN_FD_1
#define XILPM_RESET_I2C0 PM_RST_I2C_0
#define XILPM_RESET_I2C1 PM_RST_I2C_1
#define XILPM_RESET_TTC0 PM_RST_TTC_0
#define XILPM_RESET_TTC1 PM_RST_TTC_1
#define XILPM_RESET_TTC2 PM_RST_TTC_2
#define XILPM_RESET_TTC3 PM_RST_TTC_3
#define XILPM_RESET_SWDT_CRL PM_RST_SWDT_LPD
#define XILPM_RESET_ADMA PM_RST_ADMA
#define XILPM_RESET_GPIO PM_RST_GPIO_LPD
#define XILPM_RESET_TIMESTAMP PM_RST_TIMESTAMP
#define XILPM_RESET_RPU_R50 PM_RST_R5_0
#define XILPM_RESET_RPU_R51 PM_RST_R5_1
#define XILPM_RESET_RPU_AMBA PM_RST_RPU_AMBA
#define XILPM_RESET_OCM PM_RST_OCM
#define XILPM_RESET_RPU_PGE PM_RST_RPU_ISLAND
#define XILPM_RESET_IPI PM_RST_IPI
#define XILPM_RESET_SYSMON PM_RST_SYSMON_LPD
#define XILPM_RESET_LPD_SWDT PM_RST_SWDT_LPD
#define XILPM_RESET_FPD PM_RST_FPD
#define XILPM_RESET_RPU_DBG1 PM_RST_RPU1_DBG
#define XILPM_RESET_RPU_DBG0 PM_RST_RPU0_DBG
#define XILPM_RESET_DBG_LPD PM_RST_DBG_LPD
#define XILPM_RESET_DBG_FPD PM_RST_DBG_FPD
#define XILPM_RESET_PS_ONLY PM_RST_PS_SRST
#define XILPM_RESET_PL PM_RST_PL_SRST
#define PM_CLOCK_RPLL PM_CLK_RPLL
#define PM_CLOCK_APLL PM_CLK_APLL
#define PM_CLOCK_RPLL_TO_FPD PM_CLK_RPLL_TO_XPD
#define PM_CLOCK_APLL_TO_LPD PM_CLK_APLL_TO_XPD
#define PM_CLOCK_ACPU PM_CLK_ACPU
#define PM_CLOCK_DBG_FPD PM_CLK_DBG_FPD
#define PM_CLOCK_DBG_LPD PM_CLK_DBG_LPD
#define PM_CLOCK_DBG_TRACE PM_CLK_DBG_TRACE
#define PM_CLOCK_DBG_TSTMP PM_CLK_DBG_TSTMP
#define PM_CLOCK_LPD_SWITCH PM_CLK_LPD_TOP_SWITCH
#define PM_CLOCK_LPD_LSBUS PM_CLK_LPD_LSBUS
#define PM_CLOCK_USB0_BUS_REF PM_CLK_USB0_BUS_REF
#define PM_CLOCK_USB0 PM_CLK_USB_SUSPEND
#define PM_CLOCK_IOU_SWITCH PM_CLK_IOU_SWITCH
#define PM_CLOCK_GEM_TSU_REF PM_CLK_GEM_TSU_REF
#define PM_CLOCK_GEM_TSU PM_CLK_GEM_TSU
#define PM_CLOCK_GEM0_TX PM_CLK_GEM0_TX
#define PM_CLOCK_GEM1_TX PM_CLK_GEM1_TX
#define PM_CLOCK_GEM0_RX PM_CLK_GEM0_RX
#define PM_CLOCK_GEM1_RX PM_CLK_GEM1_RX
#define PM_CLOCK_QSPI_REF PM_CLK_QSPI_REF
#define PM_CLOCK_SDIO0_REF PM_CLK_SDIO0_REF
#define PM_CLOCK_SDIO1_REF PM_CLK_SDIO1_REF
#define PM_CLOCK_UART0_REF PM_CLK_UART0_REF
#define PM_CLOCK_UART1_REF PM_CLK_UART1_REF
#define PM_CLOCK_SPI0_REF PM_CLK_SPI0_REF
#define PM_CLOCK_SPI1_REF PM_CLK_SPI1_REF
#define PM_CLOCK_I2C0_REF PM_CLK_I2C0_REF
#define PM_CLOCK_I2C1_REF PM_CLK_I2C1_REF
#define PM_CLOCK_CAN0_REF PM_CLK_CAN0_REF
#define PM_CLOCK_CAN1_REF PM_CLK_CAN1_REF
#define PM_CLOCK_ADMA_REF PM_CLK_ADMA
#define PM_CLOCK_TIMESTAMP_REF PM_CLK_TIMESTAMP_REF
#define PM_CLOCK_PL0_REF PM_CLK_PMC_PL0_REF
#define PM_CLOCK_PL1_REF PM_CLK_PMC_PL1_REF
#define PM_CLOCK_PL2_REF PM_CLK_PMC_PL2_REF
#define PM_CLOCK_PL3_REF PM_CLK_PMC_PL3_REF
#define PM_CLOCK_WDT PM_CLK_WDT
#define PM_CLOCK_RPLL_INT PM_CLK_RPU_PLL
#define PM_CLOCK_RPLL_PRE_SRC PM_CLK_RPU_PRESRC
#define PM_CLOCK_RPLL_INT_MUX PM_CLK_RPU_PLL_OUT
#define PM_CLOCK_RPLL_POST_SRC PM_CLK_RPU_POSTCLK
#define PM_CLOCK_APLL_INT PM_CLK_APU_PLL
#define PM_CLOCK_APLL_PRE_SRC PM_CLK_APU_PRESRC
#define PM_CLOCK_APLL_INT_MUX PM_CLK_APU_PLL_OUT
#define PM_CLOCK_APLL_POST_SRC PM_CLK_RPU_POSTCLK
#define PM_CLOCK_ACPU_FULL PM_CLK_ACPU
#define PM_CLOCK_GEM0_REF PM_CLK_GEM0_REF
#define PM_CLOCK_GEM1_REF PM_CLK_GEM1_REF
/* Reset action IDs */
#define XILPM_RESET_ACTION_RELEASE PM_RESET_ACTION_RELEASE
#define XILPM_RESET_ACTION_ASSERT PM_RESET_ACTION_ASSERT
#define XILPM_RESET_ACTION_PULSE PM_RESET_ACTION_PULSE
/* Requirement limits */
#define MAX_CAPABILITY XPM_MAX_CAPABILITY
#define MAX_LATENCY XPM_MAX_LATENCY
#define MAX_QOS XPM_MAX_QOS
#define MIN_CAPABILITY XPM_MIN_CAPABILITY
#define MIN_LATENCY XPM_MIN_LATENCY
#define MIN_QOS XPM_MIN_QOS
/* System shutdown macros */
#define PMF_SHUTDOWN_TYPE_SHUTDOWN PM_SHUTDOWN_TYPE_SHUTDOWN
#define PMF_SHUTDOWN_TYPE_RESET PM_SHUTDOWN_TYPE_RESET
#define PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM PM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM
#define PMF_SHUTDOWN_SUBTYPE_PS_ONLY PM_SHUTDOWN_SUBTYPE_RST_PS_ONLY
#define PMF_SHUTDOWN_SUBTYPE_SYSTEM PM_SHUTDOWN_SUBTYPE_RST_SYSTEM
/* Error codes */
#define XST_PM_INTERNAL XPM_PM_INTERNAL
#define XST_PM_CONFLICT XPM_PM_CONFLICT
#define XST_PM_NO_ACCESS XPM_PM_NO_ACCESS
#define XST_PM_INVALID_NODE XPM_PM_INVALID_NODE
#define XST_PM_DOUBLE_REQ XPM_PM_DOUBLE_REQ
#define XST_PM_ABORT_SUSPEND XPM_PM_ABORT_SUSPEND
#define XST_PM_TIMEOUT XPM_PM_TIMEOUT
#define XST_PM_NODE_USED XPM_PM_NODE_USED
/* Callback IDs */
/* NOTE: This macros are currently not supported for Versal. It may come in future */
#define PM_NOTIFY_STL_NO_OP (34U)
/**
* PM Acknowledge Request Types
*/
/* TODO: Add support for this macros in future */
enum XPmRequestAck {
REQUEST_ACK_NO = 1,
REQUEST_ACK_BLOCKING,
REQUEST_ACK_NON_BLOCKING,
REQUEST_ACK_CB_CERROR,
};
#ifdef __cplusplus
}
#endif
#endif /* PM_DEFS_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/ipi.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _IPI_H_
#define _IPI_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* IPI Base Address
*/
#define IPI_BASEADDR ((u32)0XFF300000U)
#define IPI_PMU_0_ISR ( ( IPI_BASEADDR ) + ((u32)0X00030010U) )
#define IPI_PMU_1_ISR ( ( IPI_BASEADDR ) + ((u32)0X00031010U) )
#define IPI_PMU_2_ISR ( ( IPI_BASEADDR ) + ((u32)0X00032010U) )
#define IPI_PMU_3_ISR ( ( IPI_BASEADDR ) + ((u32)0X00033010U) )
#define IPI_CTRL ( ( IPI_BASEADDR ) + ((u32)0x00080000U) )
#ifdef __cplusplus
}
#endif
#endif /* _IPI_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_interrupts.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_interrupts.h"
#include "xpfw_events.h"
#include "xpfw_core.h"
#include "xil_exception.h"
#include "xpfw_error_manager.h"
#include "pmu_lmb_bram.h"
/**
* InterruptRegister holds the state of the IRQ Enable Register
*
* @note IRQ_ENABLE register is write-only, So its state is stored here
*/
static u32 InterruptRegsiter;
static void XPfw_NullHandler(void)
{
/**
* This should never be called.
*/
XPfw_Printf(DEBUG_ERROR,"Error: NullHandler Triggered!\r\n");
}
static void XPfw_PmuRamCEHandler(void)
{
XPfw_Printf(DEBUG_DETAILED,"PMU RAM Correctable ECC occurred!\r\n");
/* Clear the interrupt */
XPfw_Write32(PMU_LMB_BRAM_ECC_STATUS_REG, PMU_LMB_BRAM_CE_MASK);
}
static void XPfw_InterruptPwrUpHandler(void)
{
XStatus Status = XPfw_CoreDispatchEvent(XPFW_EV_REQ_PWRUP);
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_DETAILED,"Warning: Failed to dispatch Event ID:"
" %d\r\n",XPFW_EV_REQ_PWRUP);
}
}
static void XPfw_InterruptPwrDnHandler(void)
{
XStatus Status = XPfw_CoreDispatchEvent(XPFW_EV_REQ_PWRDN);
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_DETAILED,"Warning: Failed to dispatch Event ID:"
" %d\r\n",XPFW_EV_REQ_PWRDN);
}
}
static void XPfw_InterruptIsolationHandler(void)
{
XStatus Status = XPfw_CoreDispatchEvent(XPFW_EV_REQ_ISOLATION);
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_DETAILED,"Warning: Failed to dispatch Event ID:"
" %d\r\n",XPFW_EV_REQ_ISOLATION);
}
}
static void XPfw_InterruptGpi0Handler(void)
{
XStatus Status = XPfw_CoreDispatchEvent(XPFW_EV_MB_FAULT);
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_DETAILED,"Warning: Failed to dispatch Event ID:"
" %d\r\n",XPFW_EV_MB_FAULT);
}
}
static void XPfw_InterruptGpi1Handler(void)
{
u32 EventId;
for (EventId = XPFW_EV_APB_AIB_ERROR; EventId <= XPFW_EV_ACPU_0_WAKE;
++EventId) {
u32 RegMask = XPfw_EventGetRegMask(EventId);
u32 GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI1);
if ((GpiRegVal & RegMask) == RegMask) {
/* Dispatch the event to Registered Modules */
XStatus Status = XPfw_CoreDispatchEvent(EventId);
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_DETAILED,"Warning: "
"Failed to dispatch Event ID: %lu\r\n", EventId);
}
}
}
}
static void XPfw_InterruptGpi2Handler(void)
{
u32 EventId;
for (EventId = XPFW_EV_VCC_INT_FP_DISCONNECT;
EventId <= XPFW_EV_ACPU_0_SLEEP; ++EventId) {
u32 RegMask = XPfw_EventGetRegMask(EventId);
u32 GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI2);
if ((GpiRegVal & RegMask) == RegMask) {
/* Dispatch the event to Registered Modules */
XStatus Status = XPfw_CoreDispatchEvent(EventId);
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_DETAILED,"Warning: "
"Failed to dispatch Event ID: %lu\r\n", EventId);
}
}
}
}
static void XPfw_InterruptGpi3Handler(void)
{
u32 EventId;
for (EventId = XPFW_EV_PL_GPI_31;
EventId <= XPFW_EV_PL_GPI_0; ++EventId) {
u32 RegMask = XPfw_EventGetRegMask(EventId);
u32 GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI3);
if ((GpiRegVal & RegMask) == RegMask) {
/* Dispatch the event to Registered Modules */
XStatus Status = XPfw_CoreDispatchEvent(EventId);
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_DETAILED,"Warning: "
"Failed to dispatch Event ID: %lu\r\n", EventId);
}
}
}
}
static void XPfw_InterruptRtcAlaramHandler(void)
{
if (XST_SUCCESS != XPfw_CoreDispatchEvent(XPFW_EV_RTC_ALARM)) {
XPfw_Printf(DEBUG_DETAILED,"Warning: Failed to dispatch "
"Event ID: %d\r\n", XPFW_EV_RTC_ALARM);
}
}
static void XPfw_InterruptRtcSecondsmHandler(void)
{
if (XST_SUCCESS != XPfw_CoreDispatchEvent(XPFW_EV_RTC_SECONDS)) {
XPfw_Printf(DEBUG_DETAILED,"Warning: Failed to dispatch "
"Event ID: %d\r\n", XPFW_EV_RTC_SECONDS);
}
}
static void XPfw_Pit1Handler(void)
{
XPfw_CoreTickHandler();
}
static void XPfw_Ipi0Handler(void)
{
u32 Mask;
XStatus Status;
Mask = XPfw_Read32(IPI_PMU_0_ISR);
Status = XPfw_CoreDispatchIpi(0U, Mask);
XPfw_Write32(IPI_PMU_0_ISR, Mask);
/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_ERROR,"Error: Unhandled IPI received\r\n");
}
}
static void XPfw_Ipi1Handler(void)
{
u32 Mask;
XStatus Status;
Mask = XPfw_Read32(IPI_PMU_1_ISR);
Status = XPfw_CoreDispatchIpi(1U, Mask);
XPfw_Write32(IPI_PMU_1_ISR, Mask);
/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_ERROR,"Error: Unhandled IPI received\r\n");
}
}
static void XPfw_Ipi2Handler(void)
{
u32 Mask;
XStatus Status;
Mask = XPfw_Read32(IPI_PMU_2_ISR);
Status = XPfw_CoreDispatchIpi(2U, Mask);
XPfw_Write32(IPI_PMU_2_ISR, Mask);
/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_ERROR,"Error: Unhandled IPI received\r\n");
}
}
static void XPfw_Ipi3Handler(void)
{
u32 Mask;
XStatus Status;
Mask = XPfw_Read32(IPI_PMU_3_ISR);
Status = XPfw_CoreDispatchIpi(3U, Mask);
XPfw_Write32(IPI_PMU_3_ISR, Mask);
/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_ERROR,"Error: Unhandled IPI received\r\n");
}
}
static struct HandlerTable g_TopLevelInterruptTable[] = {
{PMU_IOMODULE_IRQ_PENDING_GPI1_MASK, XPfw_InterruptGpi1Handler},
{PMU_IOMODULE_IRQ_PENDING_IPI0_MASK, XPfw_Ipi0Handler},
{PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_MASK, XPfw_InterruptRtcAlaramHandler},
{PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_MASK, XPfw_InterruptRtcSecondsmHandler},
{PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_MASK, XPfw_PmuRamCEHandler},
{PMU_IOMODULE_IRQ_PENDING_INV_ADDR_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_IPI3_MASK, XPfw_Ipi3Handler},
{PMU_IOMODULE_IRQ_PENDING_IPI2_MASK, XPfw_Ipi2Handler},
{PMU_IOMODULE_IRQ_PENDING_IPI1_MASK, XPfw_Ipi1Handler},
{PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_MASK, XPfw_InterruptPwrUpHandler},
{PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_MASK, XPfw_InterruptPwrDnHandler},
{PMU_IOMODULE_IRQ_PENDING_ISO_REQ_MASK, XPfw_InterruptIsolationHandler},
{PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_GPI3_MASK, XPfw_InterruptGpi3Handler},
{PMU_IOMODULE_IRQ_PENDING_GPI2_MASK, XPfw_InterruptGpi2Handler},
{PMU_IOMODULE_IRQ_PENDING_GPI0_MASK, XPfw_InterruptGpi0Handler},
{PMU_IOMODULE_IRQ_PENDING_PIT3_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_PIT2_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_PIT1_MASK, XPfw_Pit1Handler},
{PMU_IOMODULE_IRQ_PENDING_PIT0_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_MASK, XPfw_NullHandler}
};
void XPfw_InterruptInit(void)
{
XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, 0U);
Xil_ExceptionDisable();
XPfw_Write32(PMU_IOMODULE_IRQ_ACK, 0xffffffffU);
InterruptRegsiter = PMU_IOMODULE_IRQ_ENABLE_CSU_PMU_SEC_LOCK_MASK;
}
void XPfw_InterruptStart(void)
{
XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, InterruptRegsiter);
Xil_ExceptionEnable();
}
void XPfw_InterruptHandler(void)
{
u32 l_IrqReg;
u32 l_index;
if (XST_SUCCESS == XPfw_CoreIsReady()) {
/* Latch the IRQ_PENDING register into a local variable */
l_IrqReg = XPfw_Read32(PMU_IOMODULE_IRQ_PENDING);
/* Loop through the Handler Table and handle the trigger interrupts */
for (l_index = 0U; l_index < ARRAYSIZE(g_TopLevelInterruptTable);
l_index++) {
if ((l_IrqReg & g_TopLevelInterruptTable[l_index].Mask)
== g_TopLevelInterruptTable[l_index].Mask) {
/* Call the Handler */
g_TopLevelInterruptTable[l_index].Handler();
/* ACK the Interrupt */
XPfw_Write32(PMU_IOMODULE_IRQ_ACK,
g_TopLevelInterruptTable[l_index].Mask);
}
}
/* Disable and Enable PMU interrupts in PMU Global register.
* This will re-generated any interrupt which is generated while
* serving the other interrupt
*/
XPfw_PulseErrorInt();
} else {
/* We shouldn't be here before Init, but we are.. So disable the Interrupts */
/* Init will enable only the required interrupts */
XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, 0U);
XPfw_Write32(PMU_IOMODULE_IRQ_ACK, 0xffffffffU);
}
}
void XPfw_InterruptDisable(u32 Mask)
{
InterruptRegsiter = InterruptRegsiter & (~Mask);
XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, InterruptRegsiter);
}
void XPfw_InterruptEnable(u32 Mask)
{
InterruptRegsiter = InterruptRegsiter | Mask;
XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, InterruptRegsiter);
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/common/xpm_nodeid.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*
* This is an automatically generated file from script.
* Please do not modify this!
*/
#ifndef XPM_NODEID_H_
#define XPM_NODEID_H_
/* Power Nodes */
#define PM_POWER_PMC (0x4208001U)
#define PM_POWER_LPD (0x4210002U)
#define PM_POWER_FPD (0x420c003U)
#define PM_POWER_NOC (0x4214004U)
#define PM_POWER_ME (0x421c005U)
#define PM_POWER_PLD (0x4220006U)
#define PM_POWER_CPM (0x4218007U)
#define PM_POWER_PL_SYSMON (0x4208008U)
#define PM_POWER_RPU0_0 (0x4104009U)
#define PM_POWER_GEM0 (0x410400aU)
#define PM_POWER_GEM1 (0x410400bU)
#define PM_POWER_OCM_0 (0x410400cU)
#define PM_POWER_OCM_1 (0x410400dU)
#define PM_POWER_OCM_2 (0x410400eU)
#define PM_POWER_OCM_3 (0x410400fU)
#define PM_POWER_TCM_0_A (0x4104010U)
#define PM_POWER_TCM_0_B (0x4104011U)
#define PM_POWER_TCM_1_A (0x4104012U)
#define PM_POWER_TCM_1_B (0x4104013U)
#define PM_POWER_ACPU_0 (0x4104014U)
#define PM_POWER_ACPU_1 (0x4104015U)
#define PM_POWER_L2_BANK_0 (0x4104016U)
#define PM_POWER_XRAM_0 (0x4124017U)
#define PM_POWER_XRAM_1 (0x4124018U)
#define PM_POWER_XRAM_2 (0x4124019U)
#define PM_POWER_XRAM_3 (0x412401aU)
#define PM_POWER_XRAM_4 (0x412401bU)
#define PM_POWER_XRAM_5 (0x412401cU)
#define PM_POWER_XRAM_6 (0x412401dU)
#define PM_POWER_XRAM_7 (0x412401eU)
#define PM_POWER_XRAM_8 (0x412401fU)
#define PM_POWER_XRAM_9 (0x4124020U)
#define PM_POWER_XRAM_10 (0x4124021U)
#define PM_POWER_XRAM_11 (0x4124022U)
#define PM_POWER_XRAM_12 (0x4124023U)
#define PM_POWER_XRAM_13 (0x4124024U)
#define PM_POWER_XRAM_14 (0x4124025U)
#define PM_POWER_XRAM_15 (0x4124026U)
#define PM_POWER_CPM5 (0x4218027U)
/* Reset Nodes */
#define PM_RST_PMC_POR (0xc30c001U)
#define PM_RST_PMC (0xc410002U)
#define PM_RST_PS_POR (0xc30c003U)
#define PM_RST_PL_POR (0xc30c004U)
#define PM_RST_NOC_POR (0xc30c005U)
#define PM_RST_FPD_POR (0xc30c006U)
#define PM_RST_ACPU_0_POR (0xc30c007U)
#define PM_RST_ACPU_1_POR (0xc30c008U)
#define PM_RST_OCM2_POR (0xc30c009U)
#define PM_RST_PS_SRST (0xc41000aU)
#define PM_RST_PL_SRST (0xc41000bU)
#define PM_RST_NOC (0xc41000cU)
#define PM_RST_NPI (0xc41000dU)
#define PM_RST_SYS_RST_1 (0xc41000eU)
#define PM_RST_SYS_RST_2 (0xc41000fU)
#define PM_RST_SYS_RST_3 (0xc410010U)
#define PM_RST_FPD (0xc410011U)
#define PM_RST_PL0 (0xc410012U)
#define PM_RST_PL1 (0xc410013U)
#define PM_RST_PL2 (0xc410014U)
#define PM_RST_PL3 (0xc410015U)
#define PM_RST_APU (0xc410016U)
#define PM_RST_ACPU_0 (0xc410017U)
#define PM_RST_ACPU_1 (0xc410018U)
#define PM_RST_ACPU_L2 (0xc410019U)
#define PM_RST_ACPU_GIC (0xc41001aU)
#define PM_RST_RPU_ISLAND (0xc41001bU)
#define PM_RST_RPU_AMBA (0xc41001cU)
#define PM_RST_R5_0 (0xc41001dU)
#define PM_RST_R5_1 (0xc41001eU)
#define PM_RST_SYSMON_PMC_SEQ_RST (0xc41001fU)
#define PM_RST_SYSMON_PMC_CFG_RST (0xc410020U)
#define PM_RST_SYSMON_FPD_CFG_RST (0xc410021U)
#define PM_RST_SYSMON_FPD_SEQ_RST (0xc410022U)
#define PM_RST_SYSMON_LPD (0xc410023U)
#define PM_RST_PDMA_RST1 (0xc410024U)
#define PM_RST_PDMA_RST0 (0xc410025U)
#define PM_RST_ADMA (0xc410026U)
#define PM_RST_TIMESTAMP (0xc410027U)
#define PM_RST_OCM (0xc410028U)
#define PM_RST_OCM2_RST (0xc410029U)
#define PM_RST_IPI (0xc41002aU)
#define PM_RST_SBI (0xc41002bU)
#define PM_RST_LPD (0xc41002cU)
#define PM_RST_QSPI (0xc10402dU)
#define PM_RST_OSPI (0xc10402eU)
#define PM_RST_SDIO_0 (0xc10402fU)
#define PM_RST_SDIO_1 (0xc104030U)
#define PM_RST_I2C_PMC (0xc104031U)
#define PM_RST_GPIO_PMC (0xc104032U)
#define PM_RST_GEM_0 (0xc104033U)
#define PM_RST_GEM_1 (0xc104034U)
#define PM_RST_SPARE (0xc104035U)
#define PM_RST_USB_0 (0xc104036U)
#define PM_RST_UART_0 (0xc104037U)
#define PM_RST_UART_1 (0xc104038U)
#define PM_RST_SPI_0 (0xc104039U)
#define PM_RST_SPI_1 (0xc10403aU)
#define PM_RST_CAN_FD_0 (0xc10403bU)
#define PM_RST_CAN_FD_1 (0xc10403cU)
#define PM_RST_I2C_0 (0xc10403dU)
#define PM_RST_I2C_1 (0xc10403eU)
#define PM_RST_GPIO_LPD (0xc10403fU)
#define PM_RST_TTC_0 (0xc104040U)
#define PM_RST_TTC_1 (0xc104041U)
#define PM_RST_TTC_2 (0xc104042U)
#define PM_RST_TTC_3 (0xc104043U)
#define PM_RST_SWDT_FPD (0xc104044U)
#define PM_RST_SWDT_LPD (0xc104045U)
#define PM_RST_USB (0xc104046U)
#define PM_RST_DPC (0xc208047U)
#define PM_RST_PMCDBG (0xc208048U)
#define PM_RST_DBG_TRACE (0xc208049U)
#define PM_RST_DBG_FPD (0xc20804aU)
#define PM_RST_DBG_TSTMP (0xc20804bU)
#define PM_RST_RPU0_DBG (0xc20804cU)
#define PM_RST_RPU1_DBG (0xc20804dU)
#define PM_RST_HSDP (0xc20804eU)
#define PM_RST_DBG_LPD (0xc20804fU)
#define PM_RST_CPM_POR (0xc30c050U)
#define PM_RST_CPM (0xc410051U)
#define PM_RST_CPMDBG (0xc208052U)
#define PM_RST_PCIE_CFG (0xc410053U)
#define PM_RST_PCIE_CORE0 (0xc410054U)
#define PM_RST_PCIE_CORE1 (0xc410055U)
#define PM_RST_PCIE_DMA (0xc410056U)
#define PM_RST_CMN (0xc410057U)
#define PM_RST_L2_0 (0xc410058U)
#define PM_RST_L2_1 (0xc410059U)
#define PM_RST_ADDR_REMAP (0xc41005aU)
#define PM_RST_CPI0 (0xc41005bU)
#define PM_RST_CPI1 (0xc41005cU)
#define PM_RST_XRAM (0xc30c05dU)
#define PM_RST_AIE_ARRAY (0xc10405eU)
#define PM_RST_AIE_SHIM (0xc10405fU)
/* Clock nodes */
#define PM_CLK_PMC_PLL (0x8104001U)
#define PM_CLK_APU_PLL (0x8104002U)
#define PM_CLK_RPU_PLL (0x8104003U)
#define PM_CLK_CPM_PLL (0x8104004U)
#define PM_CLK_NOC_PLL (0x8104005U)
#define PM_CLK_PMC_PRESRC (0x8208007U)
#define PM_CLK_PMC_POSTCLK (0x8208008U)
#define PM_CLK_PMC_PLL_OUT (0x8208009U)
#define PM_CLK_PPLL (0x820800aU)
#define PM_CLK_NOC_PRESRC (0x820800bU)
#define PM_CLK_NOC_POSTCLK (0x820800cU)
#define PM_CLK_NOC_PLL_OUT (0x820800dU)
#define PM_CLK_NPLL (0x820800eU)
#define PM_CLK_APU_PRESRC (0x820800fU)
#define PM_CLK_APU_POSTCLK (0x8208010U)
#define PM_CLK_APU_PLL_OUT (0x8208011U)
#define PM_CLK_APLL (0x8208012U)
#define PM_CLK_RPU_PRESRC (0x8208013U)
#define PM_CLK_RPU_POSTCLK (0x8208014U)
#define PM_CLK_RPU_PLL_OUT (0x8208015U)
#define PM_CLK_RPLL (0x8208016U)
#define PM_CLK_CPM_PRESRC (0x8208017U)
#define PM_CLK_CPM_POSTCLK (0x8208018U)
#define PM_CLK_CPM_PLL_OUT (0x8208019U)
#define PM_CLK_CPLL (0x820801aU)
#define PM_CLK_PPLL_TO_XPD (0x820801bU)
#define PM_CLK_NPLL_TO_XPD (0x820801cU)
#define PM_CLK_APLL_TO_XPD (0x820801dU)
#define PM_CLK_RPLL_TO_XPD (0x820801eU)
#define PM_CLK_EFUSE_REF (0x820801fU)
#define PM_CLK_SYSMON_REF (0x8208020U)
#define PM_CLK_IRO_SUSPEND_REF (0x8208021U)
#define PM_CLK_USB_SUSPEND (0x8208022U)
#define PM_CLK_SWITCH_TIMEOUT (0x8208023U)
#define PM_CLK_RCLK_PMC (0x8208024U)
#define PM_CLK_RCLK_LPD (0x8208025U)
#define PM_CLK_WDT (0x8208026U)
#define PM_CLK_TTC0 (0x8208027U)
#define PM_CLK_TTC1 (0x8208028U)
#define PM_CLK_TTC2 (0x8208029U)
#define PM_CLK_TTC3 (0x820802aU)
#define PM_CLK_GEM_TSU (0x820802bU)
#define PM_CLK_GEM_TSU_LB (0x820802cU)
#define PM_CLK_MUXED_IRO_DIV2 (0x820802dU)
#define PM_CLK_MUXED_IRO_DIV4 (0x820802eU)
#define PM_CLK_PSM_REF (0x820802fU)
#define PM_CLK_GEM0_RX (0x8208030U)
#define PM_CLK_GEM0_TX (0x8208031U)
#define PM_CLK_GEM1_RX (0x8208032U)
#define PM_CLK_GEM1_TX (0x8208033U)
#define PM_CLK_CPM_CORE_REF (0x8208034U)
#define PM_CLK_CPM_LSBUS_REF (0x8208035U)
#define PM_CLK_CPM_DBG_REF (0x8208036U)
#define PM_CLK_CPM_AUX0_REF (0x8208037U)
#define PM_CLK_CPM_AUX1_REF (0x8208038U)
#define PM_CLK_QSPI_REF (0x8208039U)
#define PM_CLK_OSPI_REF (0x820803aU)
#define PM_CLK_SDIO0_REF (0x820803bU)
#define PM_CLK_SDIO1_REF (0x820803cU)
#define PM_CLK_PMC_LSBUS_REF (0x820803dU)
#define PM_CLK_I2C_REF (0x820803eU)
#define PM_CLK_TEST_PATTERN_REF (0x820803fU)
#define PM_CLK_DFT_OSC_REF (0x8208040U)
#define PM_CLK_PMC_PL0_REF (0x8208041U)
#define PM_CLK_PMC_PL1_REF (0x8208042U)
#define PM_CLK_PMC_PL2_REF (0x8208043U)
#define PM_CLK_PMC_PL3_REF (0x8208044U)
#define PM_CLK_CFU_REF (0x8208045U)
#define PM_CLK_SPARE_REF (0x8208046U)
#define PM_CLK_NPI_REF (0x8208047U)
#define PM_CLK_HSM0_REF (0x8208048U)
#define PM_CLK_HSM1_REF (0x8208049U)
#define PM_CLK_SD_DLL_REF (0x820804aU)
#define PM_CLK_FPD_TOP_SWITCH (0x820804bU)
#define PM_CLK_FPD_LSBUS (0x820804cU)
#define PM_CLK_ACPU (0x820804dU)
#define PM_CLK_DBG_TRACE (0x820804eU)
#define PM_CLK_DBG_FPD (0x820804fU)
#define PM_CLK_LPD_TOP_SWITCH (0x8208050U)
#define PM_CLK_ADMA (0x8208051U)
#define PM_CLK_LPD_LSBUS (0x8208052U)
#define PM_CLK_CPU_R5 (0x8208053U)
#define PM_CLK_CPU_R5_CORE (0x8208054U)
#define PM_CLK_CPU_R5_OCM (0x8208055U)
#define PM_CLK_CPU_R5_OCM2 (0x8208056U)
#define PM_CLK_IOU_SWITCH (0x8208057U)
#define PM_CLK_GEM0_REF (0x8208058U)
#define PM_CLK_GEM1_REF (0x8208059U)
#define PM_CLK_GEM_TSU_REF (0x820805aU)
#define PM_CLK_USB0_BUS_REF (0x820805bU)
#define PM_CLK_UART0_REF (0x820805cU)
#define PM_CLK_UART1_REF (0x820805dU)
#define PM_CLK_SPI0_REF (0x820805eU)
#define PM_CLK_SPI1_REF (0x820805fU)
#define PM_CLK_CAN0_REF (0x8208060U)
#define PM_CLK_CAN1_REF (0x8208061U)
#define PM_CLK_I2C0_REF (0x8208062U)
#define PM_CLK_I2C1_REF (0x8208063U)
#define PM_CLK_DBG_LPD (0x8208064U)
#define PM_CLK_TIMESTAMP_REF (0x8208065U)
#define PM_CLK_DBG_TSTMP (0x8208066U)
#define PM_CLK_CPM_TOPSW_REF (0x8208067U)
#define PM_CLK_USB3_DUAL_REF (0x8208068U)
#define PM_CLK_REF_CLK (0x830c06aU)
#define PM_CLK_PL_ALT_REF_CLK (0x830c06bU)
#define PM_CLK_MUXED_IRO (0x830c06cU)
#define PM_CLK_PL_EXT (0x830c06dU)
#define PM_CLK_PL_LB (0x830c06eU)
#define PM_CLK_MIO_50_OR_51 (0x830c06fU)
#define PM_CLK_MIO_24_OR_25 (0x830c070U)
#define PM_CLK_EMIO (0x830c071U)
#define PM_CLK_MIO (0x830c072U)
#define PM_CLK_XRAM_MAIN_CLK (0x8208074U)
#define PM_CLK_XRAM_APB (0x8208075U)
/* MIO nodes */
#define PM_STMIC_LMIO_0 (0x14104001U)
#define PM_STMIC_LMIO_1 (0x14104002U)
#define PM_STMIC_LMIO_2 (0x14104003U)
#define PM_STMIC_LMIO_3 (0x14104004U)
#define PM_STMIC_LMIO_4 (0x14104005U)
#define PM_STMIC_LMIO_5 (0x14104006U)
#define PM_STMIC_LMIO_6 (0x14104007U)
#define PM_STMIC_LMIO_7 (0x14104008U)
#define PM_STMIC_LMIO_8 (0x14104009U)
#define PM_STMIC_LMIO_9 (0x1410400aU)
#define PM_STMIC_LMIO_10 (0x1410400bU)
#define PM_STMIC_LMIO_11 (0x1410400cU)
#define PM_STMIC_LMIO_12 (0x1410400dU)
#define PM_STMIC_LMIO_13 (0x1410400eU)
#define PM_STMIC_LMIO_14 (0x1410400fU)
#define PM_STMIC_LMIO_15 (0x14104010U)
#define PM_STMIC_LMIO_16 (0x14104011U)
#define PM_STMIC_LMIO_17 (0x14104012U)
#define PM_STMIC_LMIO_18 (0x14104013U)
#define PM_STMIC_LMIO_19 (0x14104014U)
#define PM_STMIC_LMIO_20 (0x14104015U)
#define PM_STMIC_LMIO_21 (0x14104016U)
#define PM_STMIC_LMIO_22 (0x14104017U)
#define PM_STMIC_LMIO_23 (0x14104018U)
#define PM_STMIC_LMIO_24 (0x14104019U)
#define PM_STMIC_LMIO_25 (0x1410401aU)
#define PM_STMIC_PMIO_0 (0x1410801bU)
#define PM_STMIC_PMIO_1 (0x1410801cU)
#define PM_STMIC_PMIO_2 (0x1410801dU)
#define PM_STMIC_PMIO_3 (0x1410801eU)
#define PM_STMIC_PMIO_4 (0x1410801fU)
#define PM_STMIC_PMIO_5 (0x14108020U)
#define PM_STMIC_PMIO_6 (0x14108021U)
#define PM_STMIC_PMIO_7 (0x14108022U)
#define PM_STMIC_PMIO_8 (0x14108023U)
#define PM_STMIC_PMIO_9 (0x14108024U)
#define PM_STMIC_PMIO_10 (0x14108025U)
#define PM_STMIC_PMIO_11 (0x14108026U)
#define PM_STMIC_PMIO_12 (0x14108027U)
#define PM_STMIC_PMIO_13 (0x14108028U)
#define PM_STMIC_PMIO_14 (0x14108029U)
#define PM_STMIC_PMIO_15 (0x1410802aU)
#define PM_STMIC_PMIO_16 (0x1410802bU)
#define PM_STMIC_PMIO_17 (0x1410802cU)
#define PM_STMIC_PMIO_18 (0x1410802dU)
#define PM_STMIC_PMIO_19 (0x1410802eU)
#define PM_STMIC_PMIO_20 (0x1410802fU)
#define PM_STMIC_PMIO_21 (0x14108030U)
#define PM_STMIC_PMIO_22 (0x14108031U)
#define PM_STMIC_PMIO_23 (0x14108032U)
#define PM_STMIC_PMIO_24 (0x14108033U)
#define PM_STMIC_PMIO_25 (0x14108034U)
#define PM_STMIC_PMIO_26 (0x14108035U)
#define PM_STMIC_PMIO_27 (0x14108036U)
#define PM_STMIC_PMIO_28 (0x14108037U)
#define PM_STMIC_PMIO_29 (0x14108038U)
#define PM_STMIC_PMIO_30 (0x14108039U)
#define PM_STMIC_PMIO_31 (0x1410803aU)
#define PM_STMIC_PMIO_32 (0x1410803bU)
#define PM_STMIC_PMIO_33 (0x1410803cU)
#define PM_STMIC_PMIO_34 (0x1410803dU)
#define PM_STMIC_PMIO_35 (0x1410803eU)
#define PM_STMIC_PMIO_36 (0x1410803fU)
#define PM_STMIC_PMIO_37 (0x14108040U)
#define PM_STMIC_PMIO_38 (0x14108041U)
#define PM_STMIC_PMIO_39 (0x14108042U)
#define PM_STMIC_PMIO_40 (0x14108043U)
#define PM_STMIC_PMIO_41 (0x14108044U)
#define PM_STMIC_PMIO_42 (0x14108045U)
#define PM_STMIC_PMIO_43 (0x14108046U)
#define PM_STMIC_PMIO_44 (0x14108047U)
#define PM_STMIC_PMIO_45 (0x14108048U)
#define PM_STMIC_PMIO_46 (0x14108049U)
#define PM_STMIC_PMIO_47 (0x1410804aU)
#define PM_STMIC_PMIO_48 (0x1410804bU)
#define PM_STMIC_PMIO_49 (0x1410804cU)
#define PM_STMIC_PMIO_50 (0x1410804dU)
#define PM_STMIC_PMIO_51 (0x1410804eU)
/* Device Nodes */
#define PM_DEV_PLD_0 (0x18700000U)
#define PM_DEV_PMC_PROC (0x18104001U)
#define PM_DEV_PSM_PROC (0x18108002U)
#define PM_DEV_ACPU_0 (0x1810c003U)
#define PM_DEV_ACPU_1 (0x1810c004U)
#define PM_DEV_RPU0_0 (0x18110005U)
#define PM_DEV_RPU0_1 (0x18110006U)
#define PM_DEV_OCM_0 (0x18314007U)
#define PM_DEV_OCM_1 (0x18314008U)
#define PM_DEV_OCM_2 (0x18314009U)
#define PM_DEV_OCM_3 (0x1831400aU)
#define PM_DEV_TCM_0_A (0x1831800bU)
#define PM_DEV_TCM_0_B (0x1831800cU)
#define PM_DEV_TCM_1_A (0x1831800dU)
#define PM_DEV_TCM_1_B (0x1831800eU)
#define PM_DEV_L2_BANK_0 (0x1831c00fU)
#define PM_DEV_DDR_0 (0x18320010U)
#define PM_DEV_DDR_1 (0x18320011U)
#define PM_DEV_DDR_2 (0x18320012U)
#define PM_DEV_DDR_3 (0x18320013U)
#define PM_DEV_DDR_4 (0x18320014U)
#define PM_DEV_DDR_5 (0x18320015U)
#define PM_DEV_DDR_6 (0x18320016U)
#define PM_DEV_DDR_7 (0x18320017U)
#define PM_DEV_USB_0 (0x18224018U)
#define PM_DEV_GEM_0 (0x18224019U)
#define PM_DEV_GEM_1 (0x1822401aU)
#define PM_DEV_SPI_0 (0x1822401bU)
#define PM_DEV_SPI_1 (0x1822401cU)
#define PM_DEV_I2C_0 (0x1822401dU)
#define PM_DEV_I2C_1 (0x1822401eU)
#define PM_DEV_CAN_FD_0 (0x1822401fU)
#define PM_DEV_CAN_FD_1 (0x18224020U)
#define PM_DEV_UART_0 (0x18224021U)
#define PM_DEV_UART_1 (0x18224022U)
#define PM_DEV_GPIO (0x18224023U)
#define PM_DEV_TTC_0 (0x18224024U)
#define PM_DEV_TTC_1 (0x18224025U)
#define PM_DEV_TTC_2 (0x18224026U)
#define PM_DEV_TTC_3 (0x18224027U)
#define PM_DEV_SWDT_LPD (0x18224028U)
#define PM_DEV_SWDT_FPD (0x18224029U)
#define PM_DEV_OSPI (0x1822402aU)
#define PM_DEV_QSPI (0x1822402bU)
#define PM_DEV_GPIO_PMC (0x1822402cU)
#define PM_DEV_I2C_PMC (0x1822402dU)
#define PM_DEV_SDIO_0 (0x1822402eU)
#define PM_DEV_SDIO_1 (0x1822402fU)
#define PM_DEV_PL_0 (0x18224030U)
#define PM_DEV_PL_1 (0x18224031U)
#define PM_DEV_PL_2 (0x18224032U)
#define PM_DEV_PL_3 (0x18224033U)
#define PM_DEV_RTC (0x18224034U)
#define PM_DEV_ADMA_0 (0x18224035U)
#define PM_DEV_ADMA_1 (0x18224036U)
#define PM_DEV_ADMA_2 (0x18224037U)
#define PM_DEV_ADMA_3 (0x18224038U)
#define PM_DEV_ADMA_4 (0x18224039U)
#define PM_DEV_ADMA_5 (0x1822403aU)
#define PM_DEV_ADMA_6 (0x1822403bU)
#define PM_DEV_ADMA_7 (0x1822403cU)
#define PM_DEV_IPI_0 (0x1822403dU)
#define PM_DEV_IPI_1 (0x1822403eU)
#define PM_DEV_IPI_2 (0x1822403fU)
#define PM_DEV_IPI_3 (0x18224040U)
#define PM_DEV_IPI_4 (0x18224041U)
#define PM_DEV_IPI_5 (0x18224042U)
#define PM_DEV_IPI_6 (0x18224043U)
#define PM_DEV_SOC (0x18428044U)
#define PM_DEV_DDRMC_0 (0x18520045U)
#define PM_DEV_DDRMC_1 (0x18520046U)
#define PM_DEV_DDRMC_2 (0x18520047U)
#define PM_DEV_DDRMC_3 (0x18520048U)
#define PM_DEV_GT_0 (0x1862c049U)
#define PM_DEV_GT_1 (0x1862c04aU)
#define PM_DEV_GT_2 (0x1862c04bU)
#define PM_DEV_GT_3 (0x1862c04cU)
#define PM_DEV_GT_4 (0x1862c04dU)
#define PM_DEV_GT_5 (0x1862c04eU)
#define PM_DEV_GT_6 (0x1862c04fU)
#define PM_DEV_GT_7 (0x1862c050U)
#define PM_DEV_GT_8 (0x1862c051U)
#define PM_DEV_GT_9 (0x1862c052U)
#define PM_DEV_GT_10 (0x1862c053U)
#define PM_DEV_EFUSE_CACHE (0x18330054U)
#define PM_DEV_AMS_ROOT (0x18224055U)
#define PM_DEV_XRAM_0 (0x18334056U)
#define PM_DEV_XRAM_1 (0x18334057U)
#define PM_DEV_XRAM_2 (0x18334058U)
#define PM_DEV_XRAM_3 (0x18334059U)
#define PM_DEV_XRAM_4 (0x1833405aU)
#define PM_DEV_XRAM_5 (0x1833405bU)
#define PM_DEV_XRAM_6 (0x1833405cU)
#define PM_DEV_XRAM_7 (0x1833405dU)
#define PM_DEV_XRAM_8 (0x1833405eU)
#define PM_DEV_XRAM_9 (0x1833405fU)
#define PM_DEV_XRAM_10 (0x18334060U)
#define PM_DEV_XRAM_11 (0x18334061U)
#define PM_DEV_XRAM_12 (0x18334062U)
#define PM_DEV_XRAM_13 (0x18334063U)
#define PM_DEV_XRAM_14 (0x18334064U)
#define PM_DEV_XRAM_15 (0x18334065U)
#define PM_DEV_GTM_0 (0x1862c066U)
#define PM_DEV_GTM_1 (0x1862c067U)
#define PM_DEV_GTM_2 (0x1862c068U)
#define PM_DEV_GTM_3 (0x1862c069U)
#define PM_DEV_GTM_4 (0x1862c06aU)
#define PM_DEV_GTYP_0 (0x1862c06bU)
#define PM_DEV_GTYP_1 (0x1862c06cU)
#define PM_DEV_GTYP_2 (0x1862c06dU)
#define PM_DEV_GTYP_CPM5_0 (0x1862c06eU)
#define PM_DEV_GTYP_CPM5_1 (0x1862c06fU)
#define PM_DEV_GTYP_CPM5_2 (0x1862c070U)
#define PM_DEV_GTYP_CPM5_3 (0x1862c071U)
#define PM_DEV_AIE (0x18224072U)
#define PM_DEV_IPI_PMC (0x18224073U)
/* Subsystem Nodes */
#define PM_SUBSYS_DEFAULT (0x1c000000U)
#define PM_SUBSYS_PMC (0x1c000001U)
/* Isolation Nodes */
#define PM_ISO_FPD_PL_TEST (0x20000000U)
#define PM_ISO_FPD_PL (0x20000001U)
#define PM_ISO_FPD_SOC (0x20000002U)
#define PM_ISO_LPD_CPM_DFX (0x20000003U)
#define PM_ISO_LPD_CPM (0x20000004U)
#define PM_ISO_LPD_PL_TEST (0x20000005U)
#define PM_ISO_LPD_PL (0x20000006U)
#define PM_ISO_LPD_SOC (0x20000007U)
#define PM_ISO_PMC_LPD_DFX (0x20000008U)
#define PM_ISO_PMC_LPD (0x20000009U)
#define PM_ISO_PMC_PL_CFRAME (0x2000000aU)
#define PM_ISO_PMC_PL_TEST (0x2000000bU)
#define PM_ISO_PMC_PL (0x2000000cU)
#define PM_ISO_PMC_SOC_NPI (0x2000000dU)
#define PM_ISO_PMC_SOC (0x2000000eU)
#define PM_ISO_PL_SOC (0x2000000fU)
#define PM_ISO_VCCAUX_SOC (0x20000010U)
#define PM_ISO_VCCRAM_SOC (0x20000011U)
#define PM_ISO_VCCAUX_VCCRAM (0x20000012U)
#define PM_ISO_PL_CPM_PCIEA0_ATTR (0x20000013U)
#define PM_ISO_PL_CPM_PCIEA1_ATTR (0x20000014U)
#define PM_ISO_PL_CPM_RST_CPI0 (0x20000015U)
#define PM_ISO_PL_CPM_RST_CPI1 (0x20000016U)
#define PM_ISO_GEM_TSU_CLK (0x20000017U)
#define PM_ISO_GEM0_TXRX_CLK (0x20000018U)
#define PM_ISO_GEM1_TXRX_CLK (0x20000019U)
#define PM_ISO_CPM5_PL (0x2000001aU)
#define PM_ISO_CPM5_PL_AXIMM (0x2000001bU)
#define PM_ISO_CPM5_PL_CHI0 (0x2000001cU)
#define PM_ISO_CPM5_PL_CHI1 (0x2000001dU)
#define PM_ISO_CPM5_PL_TST (0x2000001eU)
#define PM_ISO_CPM5_PL_PCIEA0_MPIO (0x2000001fU)
#define PM_ISO_CPM5_PL_PCIEA1_MPIO (0x20000020U)
#define PM_ISO_CPM5_RAM (0x20000021U)
#define PM_ISO_LPD_CPM5 (0x20000022U)
#define PM_ISO_LPD_CPM5_DFX (0x20000023U)
#define PM_ISO_XRAM_PL_AXI0 (0x20000024U)
#define PM_ISO_XRAM_PL_AXI1 (0x20000025U)
#define PM_ISO_XRAM_PL_AXI2 (0x20000026U)
#define PM_ISO_XRAM_PL_AXILITE (0x20000027U)
#define PM_ISO_XRAM_PL_FABRIC (0x20000028U)
#endif /* XPM_NODEID_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_qspi.h
/*
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#ifndef PM_QSPI_H_
#define PM_QSPI_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_common.h"
#ifdef XPAR_PSU_QSPI_0_DEVICE_ID
/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
#define QSPIPSU_DEVICE_ID XPAR_XQSPIPSU_0_DEVICE_ID
#define QSPIDMA_DST_CTRL (XPAR_XQSPIPSU_0_BASEADDR + 0x80CU)
#endif
s32 PmQspiInit(void);
s32 PmQspiWrite(u8 *WriteBufrPtr, u32 ByteCount);
s32 PmQspiRead(u32 ByteCount, u8 *ReadBfrPtr);
s32 PmQspiHWInit(void);
#ifdef __cplusplus
}
#endif
#endif /* PM_QSPI_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/uart0.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _UART0_H_
#define _UART0_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* UART0 Base Address
*/
#define UART0_BASEADDR ((u32)0XFF000000U)
/**
* Register: UART0_CONTROL_REG0
*/
#define UART0_CONTROL_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000000U) )
#define UART0_CONTROL_REG0_STPBRK_SHIFT 8
#define UART0_CONTROL_REG0_STPBRK_WIDTH 1
#define UART0_CONTROL_REG0_STPBRK_MASK ((u32)0X00000100U)
#define UART0_CONTROL_REG0_STTBRK_SHIFT 7
#define UART0_CONTROL_REG0_STTBRK_WIDTH 1
#define UART0_CONTROL_REG0_STTBRK_MASK ((u32)0X00000080U)
#define UART0_CONTROL_REG0_RSTTO_SHIFT 6
#define UART0_CONTROL_REG0_RSTTO_WIDTH 1
#define UART0_CONTROL_REG0_RSTTO_MASK ((u32)0X00000040U)
#define UART0_CONTROL_REG0_TXDIS_SHIFT 5
#define UART0_CONTROL_REG0_TXDIS_WIDTH 1
#define UART0_CONTROL_REG0_TXDIS_MASK ((u32)0X00000020U)
#define UART0_CONTROL_REG0_TXEN_SHIFT 4
#define UART0_CONTROL_REG0_TXEN_WIDTH 1
#define UART0_CONTROL_REG0_TXEN_MASK ((u32)0X00000010U)
#define UART0_CONTROL_REG0_RXDIS_SHIFT 3
#define UART0_CONTROL_REG0_RXDIS_WIDTH 1
#define UART0_CONTROL_REG0_RXDIS_MASK ((u32)0X00000008U)
#define UART0_CONTROL_REG0_RXEN_SHIFT 2
#define UART0_CONTROL_REG0_RXEN_WIDTH 1
#define UART0_CONTROL_REG0_RXEN_MASK ((u32)0X00000004U)
#define UART0_CONTROL_REG0_TXRES_SHIFT 1
#define UART0_CONTROL_REG0_TXRES_WIDTH 1
#define UART0_CONTROL_REG0_TXRES_MASK ((u32)0X00000002U)
#define UART0_CONTROL_REG0_RXRES_SHIFT 0
#define UART0_CONTROL_REG0_RXRES_WIDTH 1
#define UART0_CONTROL_REG0_RXRES_MASK ((u32)0X00000001U)
/**
* Register: UART0_MODE_REG0
*/
#define UART0_MODE_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000004U) )
#define UART0_MODE_REG0_WSIZE_SHIFT 12
#define UART0_MODE_REG0_WSIZE_WIDTH 2
#define UART0_MODE_REG0_WSIZE_MASK ((u32)0X00003000U)
#define UART0_MODE_REG0_IRMODE_SHIFT 11
#define UART0_MODE_REG0_IRMODE_WIDTH 1
#define UART0_MODE_REG0_IRMODE_MASK ((u32)0X00000800U)
#define UART0_MODE_REG0_UCLKEN_SHIFT 10
#define UART0_MODE_REG0_UCLKEN_WIDTH 1
#define UART0_MODE_REG0_UCLKEN_MASK ((u32)0X00000400U)
#define UART0_MODE_REG0_CHMODE_SHIFT 8
#define UART0_MODE_REG0_CHMODE_WIDTH 2
#define UART0_MODE_REG0_CHMODE_MASK ((u32)0X00000300U)
#define UART0_MODE_REG0_NBSTOP_SHIFT 6
#define UART0_MODE_REG0_NBSTOP_WIDTH 2
#define UART0_MODE_REG0_NBSTOP_MASK ((u32)0X000000C0U)
#define UART0_MODE_REG0_PAR_SHIFT 3
#define UART0_MODE_REG0_PAR_WIDTH 3
#define UART0_MODE_REG0_PAR_MASK ((u32)0X00000038U)
#define UART0_MODE_REG0_CHRL_SHIFT 1
#define UART0_MODE_REG0_CHRL_WIDTH 2
#define UART0_MODE_REG0_CHRL_MASK ((u32)0X00000006U)
#define UART0_MODE_REG0_CLKS_SHIFT 0
#define UART0_MODE_REG0_CLKS_WIDTH 1
#define UART0_MODE_REG0_CLKS_MASK ((u32)0X00000001U)
/**
* Register: UART0_INTRPT_EN_REG0
*/
#define UART0_INTRPT_EN_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000008U) )
#define UART0_INTRPT_EN_REG0_RBRK_SHIFT 13
#define UART0_INTRPT_EN_REG0_RBRK_WIDTH 1
#define UART0_INTRPT_EN_REG0_RBRK_MASK ((u32)0X00002000U)
#define UART0_INTRPT_EN_REG0_TOVR_SHIFT 12
#define UART0_INTRPT_EN_REG0_TOVR_WIDTH 1
#define UART0_INTRPT_EN_REG0_TOVR_MASK ((u32)0X00001000U)
#define UART0_INTRPT_EN_REG0_TNFUL_SHIFT 11
#define UART0_INTRPT_EN_REG0_TNFUL_WIDTH 1
#define UART0_INTRPT_EN_REG0_TNFUL_MASK ((u32)0X00000800U)
#define UART0_INTRPT_EN_REG0_TTRIG_SHIFT 10
#define UART0_INTRPT_EN_REG0_TTRIG_WIDTH 1
#define UART0_INTRPT_EN_REG0_TTRIG_MASK ((u32)0X00000400U)
#define UART0_INTRPT_EN_REG0_DMSI_SHIFT 9
#define UART0_INTRPT_EN_REG0_DMSI_WIDTH 1
#define UART0_INTRPT_EN_REG0_DMSI_MASK ((u32)0X00000200U)
#define UART0_INTRPT_EN_REG0_TIMEOUT_SHIFT 8
#define UART0_INTRPT_EN_REG0_TIMEOUT_WIDTH 1
#define UART0_INTRPT_EN_REG0_TIMEOUT_MASK ((u32)0X00000100U)
#define UART0_INTRPT_EN_REG0_PARE_SHIFT 7
#define UART0_INTRPT_EN_REG0_PARE_WIDTH 1
#define UART0_INTRPT_EN_REG0_PARE_MASK ((u32)0X00000080U)
#define UART0_INTRPT_EN_REG0_FRAME_SHIFT 6
#define UART0_INTRPT_EN_REG0_FRAME_WIDTH 1
#define UART0_INTRPT_EN_REG0_FRAME_MASK ((u32)0X00000040U)
#define UART0_INTRPT_EN_REG0_ROVR_SHIFT 5
#define UART0_INTRPT_EN_REG0_ROVR_WIDTH 1
#define UART0_INTRPT_EN_REG0_ROVR_MASK ((u32)0X00000020U)
#define UART0_INTRPT_EN_REG0_TFUL_SHIFT 4
#define UART0_INTRPT_EN_REG0_TFUL_WIDTH 1
#define UART0_INTRPT_EN_REG0_TFUL_MASK ((u32)0X00000010U)
#define UART0_INTRPT_EN_REG0_TEMPTY_SHIFT 3
#define UART0_INTRPT_EN_REG0_TEMPTY_WIDTH 1
#define UART0_INTRPT_EN_REG0_TEMPTY_MASK ((u32)0X00000008U)
#define UART0_INTRPT_EN_REG0_RFUL_SHIFT 2
#define UART0_INTRPT_EN_REG0_RFUL_WIDTH 1
#define UART0_INTRPT_EN_REG0_RFUL_MASK ((u32)0X00000004U)
#define UART0_INTRPT_EN_REG0_REMPTY_SHIFT 1
#define UART0_INTRPT_EN_REG0_REMPTY_WIDTH 1
#define UART0_INTRPT_EN_REG0_REMPTY_MASK ((u32)0X00000002U)
#define UART0_INTRPT_EN_REG0_RTRIG_SHIFT 0
#define UART0_INTRPT_EN_REG0_RTRIG_WIDTH 1
#define UART0_INTRPT_EN_REG0_RTRIG_MASK ((u32)0X00000001U)
/**
* Register: UART0_INTRPT_DIS_REG0
*/
#define UART0_INTRPT_DIS_REG0 ( ( UART0_BASEADDR ) + ((u32)0X0000000CU) )
#define UART0_INTRPT_DIS_REG0_RBRK_SHIFT 13
#define UART0_INTRPT_DIS_REG0_RBRK_WIDTH 1
#define UART0_INTRPT_DIS_REG0_RBRK_MASK ((u32)0X00002000U)
#define UART0_INTRPT_DIS_REG0_TOVR_SHIFT 12
#define UART0_INTRPT_DIS_REG0_TOVR_WIDTH 1
#define UART0_INTRPT_DIS_REG0_TOVR_MASK ((u32)0X00001000U)
#define UART0_INTRPT_DIS_REG0_TNFUL_SHIFT 11
#define UART0_INTRPT_DIS_REG0_TNFUL_WIDTH 1
#define UART0_INTRPT_DIS_REG0_TNFUL_MASK ((u32)0X00000800U)
#define UART0_INTRPT_DIS_REG0_TTRIG_SHIFT 10
#define UART0_INTRPT_DIS_REG0_TTRIG_WIDTH 1
#define UART0_INTRPT_DIS_REG0_TTRIG_MASK ((u32)0X00000400U)
#define UART0_INTRPT_DIS_REG0_DMSI_SHIFT 9
#define UART0_INTRPT_DIS_REG0_DMSI_WIDTH 1
#define UART0_INTRPT_DIS_REG0_DMSI_MASK ((u32)0X00000200U)
#define UART0_INTRPT_DIS_REG0_TIMEOUT_SHIFT 8
#define UART0_INTRPT_DIS_REG0_TIMEOUT_WIDTH 1
#define UART0_INTRPT_DIS_REG0_TIMEOUT_MASK ((u32)0X00000100U)
#define UART0_INTRPT_DIS_REG0_PARE_SHIFT 7
#define UART0_INTRPT_DIS_REG0_PARE_WIDTH 1
#define UART0_INTRPT_DIS_REG0_PARE_MASK ((u32)0X00000080U)
#define UART0_INTRPT_DIS_REG0_FRAME_SHIFT 6
#define UART0_INTRPT_DIS_REG0_FRAME_WIDTH 1
#define UART0_INTRPT_DIS_REG0_FRAME_MASK ((u32)0X00000040U)
#define UART0_INTRPT_DIS_REG0_ROVR_SHIFT 5
#define UART0_INTRPT_DIS_REG0_ROVR_WIDTH 1
#define UART0_INTRPT_DIS_REG0_ROVR_MASK ((u32)0X00000020U)
#define UART0_INTRPT_DIS_REG0_TFUL_SHIFT 4
#define UART0_INTRPT_DIS_REG0_TFUL_WIDTH 1
#define UART0_INTRPT_DIS_REG0_TFUL_MASK ((u32)0X00000010U)
#define UART0_INTRPT_DIS_REG0_TEMPTY_SHIFT 3
#define UART0_INTRPT_DIS_REG0_TEMPTY_WIDTH 1
#define UART0_INTRPT_DIS_REG0_TEMPTY_MASK ((u32)0X00000008U)
#define UART0_INTRPT_DIS_REG0_RFUL_SHIFT 2
#define UART0_INTRPT_DIS_REG0_RFUL_WIDTH 1
#define UART0_INTRPT_DIS_REG0_RFUL_MASK ((u32)0X00000004U)
#define UART0_INTRPT_DIS_REG0_REMPTY_SHIFT 1
#define UART0_INTRPT_DIS_REG0_REMPTY_WIDTH 1
#define UART0_INTRPT_DIS_REG0_REMPTY_MASK ((u32)0X00000002U)
#define UART0_INTRPT_DIS_REG0_RTRIG_SHIFT 0
#define UART0_INTRPT_DIS_REG0_RTRIG_WIDTH 1
#define UART0_INTRPT_DIS_REG0_RTRIG_MASK ((u32)0X00000001U)
/**
* Register: UART0_INTRPT_MASK_REG0
*/
#define UART0_INTRPT_MASK_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000010U) )
#define UART0_INTRPT_MASK_REG0_RBRK_SHIFT 13
#define UART0_INTRPT_MASK_REG0_RBRK_WIDTH 1
#define UART0_INTRPT_MASK_REG0_RBRK_MASK ((u32)0X00002000U)
#define UART0_INTRPT_MASK_REG0_TOVR_SHIFT 12
#define UART0_INTRPT_MASK_REG0_TOVR_WIDTH 1
#define UART0_INTRPT_MASK_REG0_TOVR_MASK ((u32)0X00001000U)
#define UART0_INTRPT_MASK_REG0_TNFUL_SHIFT 11
#define UART0_INTRPT_MASK_REG0_TNFUL_WIDTH 1
#define UART0_INTRPT_MASK_REG0_TNFUL_MASK ((u32)0X00000800U)
#define UART0_INTRPT_MASK_REG0_TTRIG_SHIFT 10
#define UART0_INTRPT_MASK_REG0_TTRIG_WIDTH 1
#define UART0_INTRPT_MASK_REG0_TTRIG_MASK ((u32)0X00000400U)
#define UART0_INTRPT_MASK_REG0_DMSI_SHIFT 9
#define UART0_INTRPT_MASK_REG0_DMSI_WIDTH 1
#define UART0_INTRPT_MASK_REG0_DMSI_MASK ((u32)0X00000200U)
#define UART0_INTRPT_MASK_REG0_TIMEOUT_SHIFT 8
#define UART0_INTRPT_MASK_REG0_TIMEOUT_WIDTH 1
#define UART0_INTRPT_MASK_REG0_TIMEOUT_MASK ((u32)0X00000100U)
#define UART0_INTRPT_MASK_REG0_PARE_SHIFT 7
#define UART0_INTRPT_MASK_REG0_PARE_WIDTH 1
#define UART0_INTRPT_MASK_REG0_PARE_MASK ((u32)0X00000080U)
#define UART0_INTRPT_MASK_REG0_FRAME_SHIFT 6
#define UART0_INTRPT_MASK_REG0_FRAME_WIDTH 1
#define UART0_INTRPT_MASK_REG0_FRAME_MASK ((u32)0X00000040U)
#define UART0_INTRPT_MASK_REG0_ROVR_SHIFT 5
#define UART0_INTRPT_MASK_REG0_ROVR_WIDTH 1
#define UART0_INTRPT_MASK_REG0_ROVR_MASK ((u32)0X00000020U)
#define UART0_INTRPT_MASK_REG0_TFUL_SHIFT 4
#define UART0_INTRPT_MASK_REG0_TFUL_WIDTH 1
#define UART0_INTRPT_MASK_REG0_TFUL_MASK ((u32)0X00000010U)
#define UART0_INTRPT_MASK_REG0_TEMPTY_SHIFT 3
#define UART0_INTRPT_MASK_REG0_TEMPTY_WIDTH 1
#define UART0_INTRPT_MASK_REG0_TEMPTY_MASK ((u32)0X00000008U)
#define UART0_INTRPT_MASK_REG0_RFUL_SHIFT 2
#define UART0_INTRPT_MASK_REG0_RFUL_WIDTH 1
#define UART0_INTRPT_MASK_REG0_RFUL_MASK ((u32)0X00000004U)
#define UART0_INTRPT_MASK_REG0_REMPTY_SHIFT 1
#define UART0_INTRPT_MASK_REG0_REMPTY_WIDTH 1
#define UART0_INTRPT_MASK_REG0_REMPTY_MASK ((u32)0X00000002U)
#define UART0_INTRPT_MASK_REG0_RTRIG_SHIFT 0
#define UART0_INTRPT_MASK_REG0_RTRIG_WIDTH 1
#define UART0_INTRPT_MASK_REG0_RTRIG_MASK ((u32)0X00000001U)
/**
* Register: UART0_CHNL_INT_STS_REG0
*/
#define UART0_CHNL_INT_STS_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000014U) )
#define UART0_CHNL_INT_STS_REG0_RBRK_SHIFT 13
#define UART0_CHNL_INT_STS_REG0_RBRK_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_RBRK_MASK ((u32)0X00002000U)
#define UART0_CHNL_INT_STS_REG0_TOVR_SHIFT 12
#define UART0_CHNL_INT_STS_REG0_TOVR_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_TOVR_MASK ((u32)0X00001000U)
#define UART0_CHNL_INT_STS_REG0_TNFUL_SHIFT 11
#define UART0_CHNL_INT_STS_REG0_TNFUL_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_TNFUL_MASK ((u32)0X00000800U)
#define UART0_CHNL_INT_STS_REG0_TTRIG_SHIFT 10
#define UART0_CHNL_INT_STS_REG0_TTRIG_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_TTRIG_MASK ((u32)0X00000400U)
#define UART0_CHNL_INT_STS_REG0_DMSI_SHIFT 9
#define UART0_CHNL_INT_STS_REG0_DMSI_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_DMSI_MASK ((u32)0X00000200U)
#define UART0_CHNL_INT_STS_REG0_TIMEOUT_SHIFT 8
#define UART0_CHNL_INT_STS_REG0_TIMEOUT_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_TIMEOUT_MASK ((u32)0X00000100U)
#define UART0_CHNL_INT_STS_REG0_PARE_SHIFT 7
#define UART0_CHNL_INT_STS_REG0_PARE_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_PARE_MASK ((u32)0X00000080U)
#define UART0_CHNL_INT_STS_REG0_FRAME_SHIFT 6
#define UART0_CHNL_INT_STS_REG0_FRAME_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_FRAME_MASK ((u32)0X00000040U)
#define UART0_CHNL_INT_STS_REG0_ROVR_SHIFT 5
#define UART0_CHNL_INT_STS_REG0_ROVR_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_ROVR_MASK ((u32)0X00000020U)
#define UART0_CHNL_INT_STS_REG0_TFUL_SHIFT 4
#define UART0_CHNL_INT_STS_REG0_TFUL_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_TFUL_MASK ((u32)0X00000010U)
#define UART0_CHNL_INT_STS_REG0_TEMPTY_SHIFT 3
#define UART0_CHNL_INT_STS_REG0_TEMPTY_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_TEMPTY_MASK ((u32)0X00000008U)
#define UART0_CHNL_INT_STS_REG0_RFUL_SHIFT 2
#define UART0_CHNL_INT_STS_REG0_RFUL_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_RFUL_MASK ((u32)0X00000004U)
#define UART0_CHNL_INT_STS_REG0_REMPTY_SHIFT 1
#define UART0_CHNL_INT_STS_REG0_REMPTY_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_REMPTY_MASK ((u32)0X00000002U)
#define UART0_CHNL_INT_STS_REG0_RTRIG_SHIFT 0
#define UART0_CHNL_INT_STS_REG0_RTRIG_WIDTH 1
#define UART0_CHNL_INT_STS_REG0_RTRIG_MASK ((u32)0X00000001U)
/**
* Register: UART0_BAUD_RATE_GEN_REG0
*/
#define UART0_BAUD_RATE_GEN_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000018U) )
#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0
#define UART0_BAUD_RATE_GEN_REG0_CD_WIDTH 16
#define UART0_BAUD_RATE_GEN_REG0_CD_MASK ((u32)0X0000FFFFU)
/**
* Register: UART0_RCVR_TIMEOUT_REG0
*/
#define UART0_RCVR_TIMEOUT_REG0 ( ( UART0_BASEADDR ) + ((u32)0X0000001CU) )
#define UART0_RCVR_TIMEOUT_REG0_RTO_SHIFT 0
#define UART0_RCVR_TIMEOUT_REG0_RTO_WIDTH 8
#define UART0_RCVR_TIMEOUT_REG0_RTO_MASK ((u32)0X000000FFU)
/**
* Register: UART0_RCVR_FIFO_TRIGGER_LEVEL0
*/
#define UART0_RCVR_FIFO_TRIGGER_LEVEL0 ( ( UART0_BASEADDR ) + ((u32)0X00000020U) )
#define UART0_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_SHIFT 0
#define UART0_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_WIDTH 6
#define UART0_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_MASK ((u32)0X0000003FU)
/**
* Register: UART0_MODEM_CTRL_REG0
*/
#define UART0_MODEM_CTRL_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000024U) )
#define UART0_MODEM_CTRL_REG0_FCM_SHIFT 5
#define UART0_MODEM_CTRL_REG0_FCM_WIDTH 1
#define UART0_MODEM_CTRL_REG0_FCM_MASK ((u32)0X00000020U)
#define UART0_MODEM_CTRL_REG0_RTS_SHIFT 1
#define UART0_MODEM_CTRL_REG0_RTS_WIDTH 1
#define UART0_MODEM_CTRL_REG0_RTS_MASK ((u32)0X00000002U)
#define UART0_MODEM_CTRL_REG0_DTR_SHIFT 0
#define UART0_MODEM_CTRL_REG0_DTR_WIDTH 1
#define UART0_MODEM_CTRL_REG0_DTR_MASK ((u32)0X00000001U)
/**
* Register: UART0_MODEM_STS_REG0
*/
#define UART0_MODEM_STS_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000028U) )
#define UART0_MODEM_STS_REG0_FCMS_SHIFT 8
#define UART0_MODEM_STS_REG0_FCMS_WIDTH 1
#define UART0_MODEM_STS_REG0_FCMS_MASK ((u32)0X00000100U)
#define UART0_MODEM_STS_REG0_DCD_SHIFT 7
#define UART0_MODEM_STS_REG0_DCD_WIDTH 1
#define UART0_MODEM_STS_REG0_DCD_MASK ((u32)0X00000080U)
#define UART0_MODEM_STS_REG0_RI_SHIFT 6
#define UART0_MODEM_STS_REG0_RI_WIDTH 1
#define UART0_MODEM_STS_REG0_RI_MASK ((u32)0X00000040U)
#define UART0_MODEM_STS_REG0_DSR_SHIFT 5
#define UART0_MODEM_STS_REG0_DSR_WIDTH 1
#define UART0_MODEM_STS_REG0_DSR_MASK ((u32)0X00000020U)
#define UART0_MODEM_STS_REG0_CTS_SHIFT 4
#define UART0_MODEM_STS_REG0_CTS_WIDTH 1
#define UART0_MODEM_STS_REG0_CTS_MASK ((u32)0X00000010U)
#define UART0_MODEM_STS_REG0_DDCD_SHIFT 3
#define UART0_MODEM_STS_REG0_DDCD_WIDTH 1
#define UART0_MODEM_STS_REG0_DDCD_MASK ((u32)0X00000008U)
#define UART0_MODEM_STS_REG0_TERI_SHIFT 2
#define UART0_MODEM_STS_REG0_TERI_WIDTH 1
#define UART0_MODEM_STS_REG0_TERI_MASK ((u32)0X00000004U)
#define UART0_MODEM_STS_REG0_DDSR_SHIFT 1
#define UART0_MODEM_STS_REG0_DDSR_WIDTH 1
#define UART0_MODEM_STS_REG0_DDSR_MASK ((u32)0X00000002U)
#define UART0_MODEM_STS_REG0_DCTS_SHIFT 0
#define UART0_MODEM_STS_REG0_DCTS_WIDTH 1
#define UART0_MODEM_STS_REG0_DCTS_MASK ((u32)0X00000001U)
/**
* Register: UART0_CHANNEL_STS_REG0
*/
#define UART0_CHANNEL_STS_REG0 ( ( UART0_BASEADDR ) + ((u32)0X0000002CU) )
#define UART0_CHANNEL_STS_REG0_RBRK_SHIFT 15
#define UART0_CHANNEL_STS_REG0_RBRK_WIDTH 1
#define UART0_CHANNEL_STS_REG0_RBRK_MASK ((u32)0X00008000U)
#define UART0_CHANNEL_STS_REG0_TNFUL_SHIFT 14
#define UART0_CHANNEL_STS_REG0_TNFUL_WIDTH 1
#define UART0_CHANNEL_STS_REG0_TNFUL_MASK ((u32)0X00004000U)
#define UART0_CHANNEL_STS_REG0_TTRIG_SHIFT 13
#define UART0_CHANNEL_STS_REG0_TTRIG_WIDTH 1
#define UART0_CHANNEL_STS_REG0_TTRIG_MASK ((u32)0X00002000U)
#define UART0_CHANNEL_STS_REG0_FDELT_SHIFT 12
#define UART0_CHANNEL_STS_REG0_FDELT_WIDTH 1
#define UART0_CHANNEL_STS_REG0_FDELT_MASK ((u32)0X00001000U)
#define UART0_CHANNEL_STS_REG0_TACTIVE_SHIFT 11
#define UART0_CHANNEL_STS_REG0_TACTIVE_WIDTH 1
#define UART0_CHANNEL_STS_REG0_TACTIVE_MASK ((u32)0X00000800U)
#define UART0_CHANNEL_STS_REG0_RACTIVE_SHIFT 10
#define UART0_CHANNEL_STS_REG0_RACTIVE_WIDTH 1
#define UART0_CHANNEL_STS_REG0_RACTIVE_MASK ((u32)0X00000400U)
#define UART0_CHANNEL_STS_REG0_DMSI_SHIFT 9
#define UART0_CHANNEL_STS_REG0_DMSI_WIDTH 1
#define UART0_CHANNEL_STS_REG0_DMSI_MASK ((u32)0X00000200U)
#define UART0_CHANNEL_STS_REG0_TIMEOUT_SHIFT 8
#define UART0_CHANNEL_STS_REG0_TIMEOUT_WIDTH 1
#define UART0_CHANNEL_STS_REG0_TIMEOUT_MASK ((u32)0X00000100U)
#define UART0_CHANNEL_STS_REG0_PARE_SHIFT 7
#define UART0_CHANNEL_STS_REG0_PARE_WIDTH 1
#define UART0_CHANNEL_STS_REG0_PARE_MASK ((u32)0X00000080U)
#define UART0_CHANNEL_STS_REG0_FRAME_SHIFT 6
#define UART0_CHANNEL_STS_REG0_FRAME_WIDTH 1
#define UART0_CHANNEL_STS_REG0_FRAME_MASK ((u32)0X00000040U)
#define UART0_CHANNEL_STS_REG0_ROVR_SHIFT 5
#define UART0_CHANNEL_STS_REG0_ROVR_WIDTH 1
#define UART0_CHANNEL_STS_REG0_ROVR_MASK ((u32)0X00000020U)
#define UART0_CHANNEL_STS_REG0_TFUL_SHIFT 4
#define UART0_CHANNEL_STS_REG0_TFUL_WIDTH 1
#define UART0_CHANNEL_STS_REG0_TFUL_MASK ((u32)0X00000010U)
#define UART0_CHANNEL_STS_REG0_TEMPTY_SHIFT 3
#define UART0_CHANNEL_STS_REG0_TEMPTY_WIDTH 1
#define UART0_CHANNEL_STS_REG0_TEMPTY_MASK ((u32)0X00000008U)
#define UART0_CHANNEL_STS_REG0_RFUL_SHIFT 2
#define UART0_CHANNEL_STS_REG0_RFUL_WIDTH 1
#define UART0_CHANNEL_STS_REG0_RFUL_MASK ((u32)0X00000004U)
#define UART0_CHANNEL_STS_REG0_REMPTY_SHIFT 1
#define UART0_CHANNEL_STS_REG0_REMPTY_WIDTH 1
#define UART0_CHANNEL_STS_REG0_REMPTY_MASK ((u32)0X00000002U)
#define UART0_CHANNEL_STS_REG0_RTRIG_SHIFT 0
#define UART0_CHANNEL_STS_REG0_RTRIG_WIDTH 1
#define UART0_CHANNEL_STS_REG0_RTRIG_MASK ((u32)0X00000001U)
/**
* Register: UART0_TX_RX_FIFO0
*/
#define UART0_TX_RX_FIFO0 ( ( UART0_BASEADDR ) + ((u32)0X00000030U) )
#define UART0_TX_RX_FIFO0_FIFO_SHIFT 0
#define UART0_TX_RX_FIFO0_FIFO_WIDTH 8
#define UART0_TX_RX_FIFO0_FIFO_MASK ((u32)0X000000FFU)
/**
* Register: UART0_BAUD_RATE_DIVIDER_REG0
*/
#define UART0_BAUD_RATE_DIVIDER_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000034U) )
#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0
#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_WIDTH 8
#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK ((u32)0X000000FFU)
/**
* Register: UART0_FLOW_DELAY_REG0
*/
#define UART0_FLOW_DELAY_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000038U) )
#define UART0_FLOW_DELAY_REG0_FDEL_SHIFT 0
#define UART0_FLOW_DELAY_REG0_FDEL_WIDTH 6
#define UART0_FLOW_DELAY_REG0_FDEL_MASK ((u32)0X0000003FU)
/**
* Register: UART0_IR_MIN_RCV_PULSE_WDTH0
*/
#define UART0_IR_MIN_RCV_PULSE_WDTH0 ( ( UART0_BASEADDR ) + ((u32)0X0000003CU) )
#define UART0_IR_MIN_RCV_PULSE_WDTH0_PMN_SHIFT 0
#define UART0_IR_MIN_RCV_PULSE_WDTH0_PMN_WIDTH 16
#define UART0_IR_MIN_RCV_PULSE_WDTH0_PMN_MASK ((u32)0X0000FFFFU)
/**
* Register: UART0_IR_TRANSMITTED_PULSE_WDTH0
*/
#define UART0_IR_TRANSMITTED_PULSE_WDTH0 ( ( UART0_BASEADDR ) + ((u32)0X00000040U) )
#define UART0_IR_TRANSMITTED_PULSE_WDTH0_PWID_SHIFT 0
#define UART0_IR_TRANSMITTED_PULSE_WDTH0_PWID_WIDTH 8
#define UART0_IR_TRANSMITTED_PULSE_WDTH0_PWID_MASK ((u32)0X000000FFU)
/**
* Register: UART0_TX_FIFO_TRIGGER_LEVEL0
*/
#define UART0_TX_FIFO_TRIGGER_LEVEL0 ( ( UART0_BASEADDR ) + ((u32)0X00000044U) )
#define UART0_TX_FIFO_TRIGGER_LEVEL0_TTRIG_SHIFT 0
#define UART0_TX_FIFO_TRIGGER_LEVEL0_TTRIG_WIDTH 6
#define UART0_TX_FIFO_TRIGGER_LEVEL0_TTRIG_MASK ((u32)0X0000003FU)
/**
* Register: UART0_RX_FIFO_BYTE_STATUS
*/
#define UART0_RX_FIFO_BYTE_STATUS ( ( UART0_BASEADDR ) + ((u32)0X00000048U) )
#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_SHIFT 11
#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_MASK ((u32)0X00000800U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_SHIFT 10
#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_MASK ((u32)0X00000400U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_SHIFT 9
#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_MASK ((u32)0X00000200U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_SHIFT 8
#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_MASK ((u32)0X00000100U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_SHIFT 7
#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_MASK ((u32)0X00000080U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_SHIFT 6
#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_MASK ((u32)0X00000040U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_SHIFT 5
#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_MASK ((u32)0X00000020U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_SHIFT 4
#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_MASK ((u32)0X00000010U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_SHIFT 3
#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_MASK ((u32)0X00000008U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_SHIFT 2
#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_MASK ((u32)0X00000004U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_SHIFT 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_MASK ((u32)0X00000002U)
#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_SHIFT 0
#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_WIDTH 1
#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_MASK ((u32)0X00000001U)
#ifdef __cplusplus
}
#endif
#endif /* _UART0_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_cpmdomain.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_common.h"
#include "xpm_cpmdomain.h"
#include "xpm_regs.h"
#include "xpm_bisr.h"
#include "xpm_power.h"
#include "sleep.h"
#include "xpm_device.h"
#define XPM_HC_CPM_OPS 0U
#define XPM_HC_CPM5_OPS 1U
#define XPM_CPM_OPS_MAX 2U
/* Define CPM5_GTYP device */
#define XPM_NODEIDX_DEV_GTYP_CPM5_MIN XPM_NODEIDX_DEV_GTYP_CPM5_0
#define XPM_NODEIDX_DEV_GTYP_CPM5_MAX XPM_NODEIDX_DEV_GTYP_CPM5_3
static u32 GtyAddresses[XPM_NODEIDX_DEV_GTYP_CPM5_MAX -
XPM_NODEIDX_DEV_GTYP_CPM5_MIN + 1] = {0};
static XStatus CpmInitStart(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
XPm_CpmDomain *Cpm;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
Cpm = (XPm_CpmDomain *)XPmPower_GetById(PM_POWER_CPM);
if (NULL == Cpm) {
goto done;
}
/* Remove isolation to allow scan_clear on CPM */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_CPM_DFX, FALSE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* CPM POR control is not valid for ES1 platforms so skip. It is taken care by hw */
if(!(PLATFORM_VERSION_SILICON == Platform && PLATFORM_VERSION_SILICON_ES1 == PlatformVersion))
{
/* Remove POR for CPM */
/*Status = XPmReset_AssertbyId(PM_RST_CPM_POR,
(u32)PM_RESET_ACTION_RELEASE);*/
/*TODO: Topology is not passing cpm reset register
right now, so hard coded for now */
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_ECO_OFFSET, 0);
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_LOCK_OFFSET, 1);
}
done:
return Status;
}
static XStatus Cpm5InitStart(u32 *Args, u32 NumofArgs)
{
XStatus Status = XPM_ERR_INIT_START;
XPm_CpmDomain *Cpm;
u32 i;
XPm_Device* Device = NULL;
/* This function does not use any args */
(void)Args;
(void)NumofArgs;
Cpm = (XPm_CpmDomain *)XPmPower_GetById(PM_POWER_CPM5);
if (NULL == Cpm) {
Status = XPM_INVALID_PWRDOMAIN;
goto done;
}
/* Remove POR for CPM5 */
/* lpd_cpm5_por_n reset maps to PM_RST_OCM2_POR */
Status = XPmReset_AssertbyId(PM_RST_OCM2_POR, (u32)PM_RESET_ACTION_RELEASE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Remove isolation between CPM5 and LPD */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_CPM5_DFX, FALSE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Initialize Array with GTYP Base Addresses*/
for (i = 0; i < ARRAY_SIZE(GtyAddresses); ++i) {
Device = XPmDevice_GetById(GT_DEVID((u32)XPM_NODEIDX_DEV_GTYP_CPM5_MIN + i));
if (NULL != Device) {
GtyAddresses[i] = Device->Node.BaseAddress;
}
}
done:
return Status;
}
static XStatus CpmInitFinish(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
Status = XST_SUCCESS;
return Status;
}
static XStatus CpmScanClear(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
XPm_CpmDomain *Cpm;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
/* Scan clear should be skipped for ES1 platforms */
if ((PLATFORM_VERSION_SILICON != Platform) || (PLATFORM_VERSION_SILICON == Platform && PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
Status = XST_SUCCESS;
goto done;
}
Cpm = (XPm_CpmDomain *)XPmPower_GetById(PM_POWER_CPM);
if (NULL == Cpm) {
Status = XST_FAILURE;
goto done;
}
/* Unlock PCSR */
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
/* Run scan clear on CPM */
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_MASK_OFFSET,
CPM_PCSR_PCR_SCAN_CLEAR_TRIGGER_MASK);
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_PCR_OFFSET,
CPM_PCSR_PCR_SCAN_CLEAR_TRIGGER_MASK);
Status = XPm_PollForMask(Cpm->CpmPcsrBaseAddr + CPM_PCSR_PSR_OFFSET,
CPM_PCSR_PSR_SCAN_CLEAR_DONE_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_PollForMask(Cpm->CpmPcsrBaseAddr + CPM_PCSR_PSR_OFFSET,
CPM_PCSR_PSR_SCAN_CLEAR_PASS_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Pulse CPM POR */
Status = XPmReset_AssertbyId(PM_RST_CPM_POR,
(u32)PM_RESET_ACTION_PULSE);
/* Unwrite trigger bits */
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_MASK_OFFSET,
CPM_PCSR_PCR_SCAN_CLEAR_TRIGGER_MASK);
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_PCR_OFFSET, 0);
/* Lock PCSR */
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_LOCK_OFFSET, 1);
done:
return Status;
}
static XStatus Cpm5ScanClear(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XPM_ERR_SCAN_CLR;
XPm_CpmDomain *Cpm;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
Cpm = (XPm_CpmDomain *)XPmPower_GetById(PM_POWER_CPM5);
if (NULL == Cpm) {
Status = XPM_INVALID_PWRDOMAIN;
goto done;
}
/* Unlock PCSR */
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
/* Run scan clear on CPM */
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_MASK_OFFSET,
CPM_PCSR_PCR_SCAN_CLEAR_TRIGGER_MASK);
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_PCR_OFFSET,
CPM_PCSR_PCR_SCAN_CLEAR_TRIGGER_MASK);
/* Wait for Scan Clear do be done */
Status = XPm_PollForMask(Cpm->CpmPcsrBaseAddr + CPM_PCSR_PSR_OFFSET,
CPM_PCSR_PSR_SCAN_CLEAR_DONE_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Check if Scan Clear Passed */
Status = XPm_PollForMask(Cpm->CpmPcsrBaseAddr + CPM_PCSR_PSR_OFFSET,
CPM_PCSR_PSR_SCAN_CLEAR_PASS_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Disable writes to PCR */
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_MASK_OFFSET,
0x0);
/* Lock PCSR */
PmOut32(Cpm->CpmPcsrBaseAddr + CPM_PCSR_LOCK_OFFSET, 1);
done:
return Status;
}
static XStatus CpmBisr(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
/* Bisr */
Status = XPmBisr_Repair(CPM_TAG_ID);
done:
return Status;
}
static XStatus Cpm5Bisr(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
/* Bisr on CPM5 PD*/
Status = XPmBisr_Repair(CPM5_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
/* Bisr on GTYP_CPM5 */
Status = XPmBisr_Repair(CPM5_GTYP_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
static XStatus CpmMbistClear(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
XPm_CpmDomain *Cpm;
u32 RegValue;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
Cpm = (XPm_CpmDomain *)XPmPower_GetById(PM_POWER_CPM);
if (NULL == Cpm) {
Status = XST_FAILURE;
goto done;
}
/* Unlock Writes */
PmOut32(Cpm->CpmSlcrSecureBaseAddr + CPM_SLCR_SECURE_WPROT0_OFFSET, 0);
/* Trigger Mbist */
PmOut32(Cpm->CpmSlcrSecureBaseAddr +
CPM_SLCR_SECURE_OD_MBIST_RESET_N_OFFSET, 0xFF);
PmOut32(Cpm->CpmSlcrSecureBaseAddr +
CPM_SLCR_SECURE_OD_MBIST_SETUP_OFFSET, 0xFF);
PmOut32(Cpm->CpmSlcrSecureBaseAddr +
CPM_SLCR_SECURE_OD_MBIST_PG_EN_OFFSET, 0xFF);
/* Wait till its done */
Status = XPm_PollForMask(Cpm->CpmSlcrSecureBaseAddr +
CPM_SLCR_SECURE_OD_MBIST_DONE_OFFSET,
0xFF, XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Check status */
PmIn32(Cpm->CpmSlcrSecureBaseAddr + CPM_SLCR_SECURE_OD_MBIST_GO_OFFSET,
RegValue);
if (0xFFU != (RegValue & 0xFFU)) {
Status = XST_FAILURE;
goto done;
}
/* Unwrite trigger bits */
PmOut32(Cpm->CpmSlcrSecureBaseAddr +
CPM_SLCR_SECURE_OD_MBIST_RESET_N_OFFSET, 0x0);
PmOut32(Cpm->CpmSlcrSecureBaseAddr +
CPM_SLCR_SECURE_OD_MBIST_SETUP_OFFSET, 0x0);
PmOut32(Cpm->CpmSlcrSecureBaseAddr +
CPM_SLCR_SECURE_OD_MBIST_PG_EN_OFFSET, 0x0);
/* Lock Writes */
PmOut32(Cpm->CpmSlcrSecureBaseAddr + CPM_SLCR_SECURE_WPROT0_OFFSET, 1);
done:
return Status;
}
static XStatus Cpm5GtypMbist(u32 BaseAddress)
{
XStatus Status = XST_FAILURE;
PmOut32(BaseAddress + GTY_PCSR_MASK_OFFSET, GTY_PCSR_MEM_CLEAR_TRIGGER_MASK);
PmOut32(BaseAddress + GTY_PCSR_CONTROL_OFFSET,
GTY_PCSR_MEM_CLEAR_TRIGGER_MASK);
Status = XPm_PollForMask(BaseAddress + GTY_PCSR_STATUS_OFFSET,
GTY_PCSR_STATUS_MEM_CLEAR_DONE_MASK, XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_PollForMask(BaseAddress + GTY_PCSR_STATUS_OFFSET,
GTY_PCSR_STATUS_MEM_CLEAR_PASS_MASK, XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Unwrite Trigger bits */
PmOut32(BaseAddress + GTY_PCSR_MASK_OFFSET, GTY_PCSR_MEM_CLEAR_TRIGGER_MASK);
PmOut32(BaseAddress + GTY_PCSR_CONTROL_OFFSET, 0);
done:
return Status;
}
static XStatus Cpm5MbistClear(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XPM_ERR_MBIST_CLR;
XPm_CpmDomain *Cpm;
u32 RegValue, i;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
Cpm = (XPm_CpmDomain *)XPmPower_GetById(PM_POWER_CPM5);
if (NULL == Cpm) {
Status = XPM_INVALID_PWRDOMAIN;
goto done;
}
/* Disable write protection */
PmOut32(Cpm->CpmSlcrSecureBaseAddr + CPM5_SLCR_SECURE_WPROTS_OFFSET, 0);
/* Trigger MBIST for all controllers */
/* This step can be broken down into stages to reduce power
* consumption. However, clear action is performed in parallel by
* MBIST Controllers */
PmOut32(Cpm->CpmSlcrSecureBaseAddr + CPM5_SLCR_SECURE_OD_MBIST_TRIGGER_OFFSET,
CPM5_SLCR_SECURE_OD_MBIST_TRIGGER_MASK);
/* Poll for done */
/* If trigger action is performed in stages, then break down this step */
Status = XPm_PollForMask(Cpm->CpmSlcrSecureBaseAddr + CPM5_SLCR_SECURE_OD_MBIST_DONE_OFFSET,
CPM5_SLCR_SECURE_OD_MBIST_DONE_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Check Status */
PmIn32(Cpm->CpmSlcrSecureBaseAddr + CPM5_SLCR_SECURE_OD_MBIST_PASSOUT_OFFSET,
RegValue);
if ((CPM5_SLCR_SECURE_OD_MBIST_PASSOUT_MASK & RegValue) !=
CPM5_SLCR_SECURE_OD_MBIST_PASSOUT_MASK) {
Status = XST_FAILURE;
goto done;
}
/* Cleanup Operation. Unwrite trigger bit and enable write protection */
PmOut32(Cpm->CpmSlcrSecureBaseAddr + CPM5_SLCR_SECURE_OD_MBIST_TRIGGER_OFFSET,
0x0);
PmOut32(Cpm->CpmSlcrSecureBaseAddr + CPM5_SLCR_SECURE_WPROTS_OFFSET,
0x1);
for (i = 0; 0U != GtyAddresses[i]; ++i) {
PmOut32(GtyAddresses[i] + GTY_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
/* Mbist */
Status = Cpm5GtypMbist(GtyAddresses[i]);
if (Status != XST_SUCCESS) {
PmErr("ERROR: CPM5 GTYP Mem clear failed\n\r");
PmOut32(GtyAddresses[i] + GTY_PCSR_LOCK_OFFSET, 1);
goto done;
}
PmOut32(GtyAddresses[i] + GTY_PCSR_LOCK_OFFSET, 1);
}
done:
return Status;
}
static struct XPm_PowerDomainOps CpmOps[XPM_CPM_OPS_MAX] = {
[XPM_HC_CPM_OPS] = {
.InitStart = CpmInitStart,
.InitFinish = CpmInitFinish,
.ScanClear = CpmScanClear,
.Bisr = CpmBisr,
.Mbist = CpmMbistClear,
},
[XPM_HC_CPM5_OPS] = {
.InitStart = Cpm5InitStart,
.InitFinish = CpmInitFinish,
.ScanClear = Cpm5ScanClear,
.Bisr = Cpm5Bisr,
.Mbist = Cpm5MbistClear,
},
};
XStatus XPmCpmDomain_Init(XPm_CpmDomain *CpmDomain, u32 Id, u32 BaseAddress,
XPm_Power *Parent, u32 *OtherBaseAddresses,
u32 OtherBaseAddressesCnt)
{
XStatus Status = XST_FAILURE;
struct XPm_PowerDomainOps *Ops = NULL;
if (Id == PM_POWER_CPM) {
Ops = &CpmOps[XPM_HC_CPM_OPS];
} else if (Id == PM_POWER_CPM5) {
Ops = &CpmOps[XPM_HC_CPM5_OPS];
} else {
Status = XPM_INVALID_PWRDOMAIN;
goto done;
}
Status = XPmPowerDomain_Init(&CpmDomain->Domain, Id, BaseAddress, Parent, Ops);
if (XST_SUCCESS != Status) {
goto done;
}
/* Make sure enough base addresses are being passed */
if (4U <= OtherBaseAddressesCnt) {
CpmDomain->CpmSlcrBaseAddr = OtherBaseAddresses[0];
CpmDomain->CpmSlcrSecureBaseAddr = OtherBaseAddresses[1];
CpmDomain->CpmPcsrBaseAddr = OtherBaseAddresses[2];
CpmDomain->CpmCrCpmBaseAddr = OtherBaseAddresses[3];
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/pm_client.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*
* CONTENT
* File is specific for each PU instance and must exist in order to
* port Power Management code for some new PU.
* Contains PU specific macros and macros to be defined depending on
* the execution environment.
*/
#ifndef PM_CLIENT_H
#define PM_CLIENT_H
#include "xil_exception.h"
#include "xil_io.h"
#include "pm_apu.h"
#include "pm_defs.h"
#include "pm_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define pm_print(MSG, ...) xil_printf("APU: "MSG,##__VA_ARGS__)
#ifdef __cplusplus
}
#endif
#endif /* PM_CLIENT_H */
<file_sep>/vitis_workspace/test_proj_ethernet/src/platform_config.h
#ifndef __PLATFORM_CONFIG_H_
#define __PLATFORM_CONFIG_H_
#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR
#define PLATFORM_ZYNQMP
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_mem.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_defs.h"
#include "xplmi_dma.h"
#include "xpm_regs.h"
#include "xpm_device.h"
#include "xpm_powerdomain.h"
#include "xpm_mem.h"
#include "xpm_rpucore.h"
#define XPM_TCM_BASEADDRESS_MODE_OFFSET 0x80000U
#define XPM_NODEIDX_DEV_DDRMC_MIN XPM_NODEIDX_DEV_DDRMC_0
#define XPM_NODEIDX_DEV_DDRMC_MAX XPM_NODEIDX_DEV_DDRMC_3
static const XPm_StateCap XPmDDRDeviceStates[] = {
{
.State = (u8)XPM_DEVSTATE_UNUSED,
.Cap = XPM_MIN_CAPABILITY,
}, {
.State = (u8)XPM_DEVSTATE_RUNTIME_SUSPEND,
.Cap = (u32)PM_CAP_CONTEXT,
}, {
.State = (u8)XPM_DEVSTATE_RUNNING,
.Cap = XPM_MAX_CAPABILITY | PM_CAP_UNUSABLE,
},
};
static const XPm_StateTran XPmDDRDevTransitions[] = {
{
.FromState = (u32)XPM_DEVSTATE_RUNNING,
.ToState = (u32)XPM_DEVSTATE_UNUSED,
.Latency = XPM_DEF_LATENCY,
}, {
.FromState = (u32)XPM_DEVSTATE_UNUSED,
.ToState = (u32)XPM_DEVSTATE_RUNNING,
.Latency = XPM_DEF_LATENCY,
}, {
.FromState = (u32)XPM_DEVSTATE_RUNTIME_SUSPEND,
.ToState = (u32)XPM_DEVSTATE_RUNNING,
.Latency = XPM_DEF_LATENCY,
}, {
.FromState = (u32)XPM_DEVSTATE_RUNNING,
.ToState = (u32)XPM_DEVSTATE_RUNTIME_SUSPEND,
.Latency = XPM_DEF_LATENCY,
},
};
static XStatus XPmDDRDevice_EnterSelfRefresh(void)
{
XStatus Status = XST_FAILURE;
XPm_Device *Device;
u32 BaseAddress;
u32 Reg, IsActive;
u32 i;
for (i = (u32)XPM_NODEIDX_DEV_DDRMC_MIN; i <= (u32)XPM_NODEIDX_DEV_DDRMC_MAX;
i++) {
Device = XPmDevice_GetById(DDRMC_DEVID(i));
if (NULL == Device) {
continue;
}
BaseAddress = Device->Node.BaseAddress;
PmIn32(BaseAddress + NPI_PCSR_CONTROL_OFFSET, IsActive);
if (DDRMC_UB_PCSR_CONTROL_PCOMPLETE_MASK != (IsActive & DDRMC_UB_PCSR_CONTROL_PCOMPLETE_MASK)) {
continue;
}
/* Unlock DDRMC UB */
Reg = BaseAddress + NPI_PCSR_LOCK_OFFSET;
XPm_Out32(Reg, NPI_PCSR_UNLOCK_VAL);
/* Enable self-refresh */
Reg = BaseAddress + DDRMC_UB_PMC2UB_INTERRUPT_OFFSET;
XPm_Out32(Reg, DDRMC_UB_PMC2UB_INTERRUPT_SPARE_0_MASK);
Reg = BaseAddress + DDRMC_UB_UB2PMC_ACK_OFFSET;
Status = XPm_PollForMask(Reg, DDRMC_UB_UB2PMC_ACK_SPARE_0_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
PmErr("Failed to enter self-refresh controller %x!\r\n",i);
Reg = BaseAddress + NPI_PCSR_LOCK_OFFSET;
XPm_Out32(Reg, 0);
goto done;
}
XPm_Out32(Reg, 0);
Reg = BaseAddress + DDRMC_UB_UB2PMC_DONE_OFFSET;
Status = XPm_PollForMask(Reg, DDRMC_UB_UB2PMC_DONE_SPARE_0_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
PmErr("Failed to enter self-refresh controller %x!\r\n",i);
Reg = BaseAddress + NPI_PCSR_LOCK_OFFSET;
XPm_Out32(Reg, 0);
goto done;
}
XPm_Out32(Reg, 0);
Reg = BaseAddress + NPI_PCSR_LOCK_OFFSET;
XPm_Out32(Reg, 0);
}
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus XPmDDRDevice_ExitSelfRefresh(void)
{
XStatus Status = XST_FAILURE;
XPm_Device *Device;
u32 BaseAddress;
u32 Reg, IsActive;
u32 i;
for (i = (u32)XPM_NODEIDX_DEV_DDRMC_MIN; i <= (u32)XPM_NODEIDX_DEV_DDRMC_MAX;
i++) {
Device = XPmDevice_GetById(DDRMC_DEVID(i));
if (NULL == Device) {
continue;
}
BaseAddress = Device->Node.BaseAddress;
PmIn32(BaseAddress + NPI_PCSR_CONTROL_OFFSET, IsActive);
if (DDRMC_UB_PCSR_CONTROL_PCOMPLETE_MASK != (IsActive & DDRMC_UB_PCSR_CONTROL_PCOMPLETE_MASK)) {
continue;
}
/* Unlock DDRMC UB */
Reg = BaseAddress + NPI_PCSR_LOCK_OFFSET;
XPm_Out32(Reg, NPI_PCSR_UNLOCK_VAL);
/* Disable self-refresh */
Reg = BaseAddress + DDRMC_UB_PMC2UB_INTERRUPT_OFFSET;
XPm_Out32(Reg, DDRMC_UB_PMC2UB_INTERRUPT_SR_EXIT_MASK);
Reg = BaseAddress + DDRMC_UB_UB2PMC_ACK_OFFSET;
Status = XPm_PollForMask(Reg, DDRMC_UB_UB2PMC_ACK_SR_EXIT_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
PmErr("Failed to exit self-refresh controller %x!\r\n",i);
Reg = BaseAddress + NPI_PCSR_LOCK_OFFSET;
XPm_Out32(Reg, 0);
goto done;
}
XPm_Out32(Reg, 0);
Reg = BaseAddress + DDRMC_UB_UB2PMC_DONE_OFFSET;
Status = XPm_PollForMask(Reg, DDRMC_UB_UB2PMC_DONE_SR_EXIT_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
PmErr("Failed to exit self-refresh controller %x!\r\n",i);
Reg = BaseAddress + NPI_PCSR_LOCK_OFFSET;
XPm_Out32(Reg, 0);
goto done;
}
XPm_Out32(Reg, 0);
Reg = BaseAddress + NPI_PCSR_LOCK_OFFSET;
XPm_Out32(Reg, 0);
}
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus HandleDDRDeviceState(XPm_Device* const Device, const u32 NextState)
{
XStatus Status = XST_FAILURE;
switch (Device->Node.State) {
case (u8)XPM_DEVSTATE_UNUSED:
if ((u32)XPM_DEVSTATE_RUNNING == NextState) {
Status = XPmDevice_BringUp(Device);
} else {
Status = XST_SUCCESS;
}
break;
case (u8)XPM_DEVSTATE_RUNNING:
if ((u32)XPM_DEVSTATE_UNUSED == NextState) {
Status = Device->HandleEvent(&Device->Node,
XPM_DEVEVENT_SHUTDOWN);
} else {
Status = XST_SUCCESS;
}
if ((u32)XPM_DEVSTATE_RUNTIME_SUSPEND == NextState) {
Status = XPmDDRDevice_EnterSelfRefresh();
}
break;
case (u8)XPM_DEVSTATE_RUNTIME_SUSPEND:
if ((u32)XPM_DEVSTATE_RUNNING == NextState) {
Status = XPmDDRDevice_ExitSelfRefresh();
}
break;
default:
Status = XST_FAILURE;
break;
}
return Status;
}
static const XPm_DeviceFsm XPmDDRDeviceFsm = {
DEFINE_DEV_STATES(XPmDDRDeviceStates),
DEFINE_DEV_TRANS(XPmDDRDevTransitions),
.EnterState = HandleDDRDeviceState,
};
static const XPm_StateCap XPmMemDeviceStates[] = {
{
.State = (u8)XPM_DEVSTATE_UNUSED,
.Cap = XPM_MIN_CAPABILITY,
}, {
.State = (u8)XPM_DEVSTATE_RUNNING,
.Cap = PM_CAP_ACCESS | PM_CAP_CONTEXT,
},
};
static const XPm_StateTran XPmMemDevTransitions[] = {
{
.FromState = (u32)XPM_DEVSTATE_RUNNING,
.ToState = (u32)XPM_DEVSTATE_UNUSED,
.Latency = XPM_DEF_LATENCY,
}, {
.FromState = (u32)XPM_DEVSTATE_UNUSED,
.ToState = (u32)XPM_DEVSTATE_RUNNING,
.Latency = XPM_DEF_LATENCY,
},
};
static void TcmEccInit(XPm_MemDevice *Tcm, u32 Mode)
{
u32 Size = Tcm->EndAddress - Tcm->StartAddress;
u32 Id = Tcm->Device.Node.Id;
u32 Base = Tcm->StartAddress;
if (PM_DEV_TCM_1_A == Id || PM_DEV_TCM_1_B == Id) {
if (XPM_RPU_MODE_LOCKSTEP == Mode) {
Base -= XPM_TCM_BASEADDRESS_MODE_OFFSET;
}
}
if (0U != Size) {
s32 Status = XPlmi_EccInit(Base, Size);
if (XST_SUCCESS != Status) {
PmWarn("Error %d in EccInit of 0x%x\r\n", Status, Tcm->Device.Node.Id);
}
}
return;
}
static XStatus HandleTcmDeviceState(XPm_Device* Device, u32 NextState)
{
XStatus Status = XST_FAILURE;
XPm_Device *Rpu0Device = XPmDevice_GetById(PM_DEV_RPU0_0);
XPm_Device *Rpu1Device = XPmDevice_GetById(PM_DEV_RPU0_1);
u32 Id = Device->Node.Id;
u32 Mode;
switch (Device->Node.State) {
case (u8)XPM_DEVSTATE_UNUSED:
if ((u32)XPM_DEVSTATE_RUNNING == NextState) {
Status = XPmDevice_BringUp(Device);
if (XST_SUCCESS != Status) {
goto done;
}
/* Request the RPU clocks. Here both core having same RPU clock */
Status = XPmClock_Request(Rpu0Device->ClkHandles);
if (XST_SUCCESS != Status) {
goto done;
}
/* TCM is only accessible when the RPU is powered on and out of reset and is in halted state
* so bring up RPU too when TCM is requested*/
XPm_RpuGetOperMode(PM_DEV_RPU0_0, &Mode);
if (XPM_RPU_MODE_SPLIT == Mode) {
if ((PM_DEV_TCM_0_A == Id ||
PM_DEV_TCM_0_B == Id) &&
((u8)XPM_DEVSTATE_RUNNING !=
Rpu0Device->Node.State)) {
Status = XPmRpuCore_Halt(Rpu0Device);
if (XST_SUCCESS != Status) {
goto done;
}
}
if ((PM_DEV_TCM_1_A == Id ||
PM_DEV_TCM_1_B == Id) &&
((u8)XPM_DEVSTATE_RUNNING !=
Rpu1Device->Node.State)) {
Status = XPmRpuCore_Halt(Rpu1Device);
if (XST_SUCCESS != Status) {
goto done;
}
}
}
if (XPM_RPU_MODE_LOCKSTEP == Mode)
{
if ((PM_DEV_TCM_0_A == Id ||
PM_DEV_TCM_0_B == Id ||
PM_DEV_TCM_1_A == Id ||
PM_DEV_TCM_1_B == Id) &&
((u8)XPM_DEVSTATE_RUNNING !=
Rpu0Device->Node.State)) {
Status = XPmRpuCore_Halt(Rpu0Device);
if (XST_SUCCESS != Status) {
goto done;
}
}
}
/* Tcm should be ecc initialized */
TcmEccInit((XPm_MemDevice *)Device, Mode);
}
Status = XST_SUCCESS;
break;
case (u8)XPM_DEVSTATE_RUNNING:
if ((u32)XPM_DEVSTATE_UNUSED == NextState) {
Status = Device->HandleEvent(&Device->Node,
XPM_DEVEVENT_SHUTDOWN);
if (XST_SUCCESS != Status) {
goto done;
}
/* Release the RPU clocks. Here both core having same RPU clock */
Status = XPmClock_Release(Rpu0Device->ClkHandles);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XST_SUCCESS;
break;
default:
Status = XST_FAILURE;
break;
}
done:
return Status;
}
static const XPm_DeviceFsm XPmTcmDeviceFsm = {
DEFINE_DEV_STATES(XPmMemDeviceStates),
DEFINE_DEV_TRANS(XPmMemDevTransitions),
.EnterState = HandleTcmDeviceState,
};
static XStatus HandleMemDeviceState(XPm_Device* const Device, const u32 NextState)
{
XStatus Status = XST_FAILURE;
switch (Device->Node.State) {
case (u8)XPM_DEVSTATE_UNUSED:
if ((u32)XPM_DEVSTATE_RUNNING == NextState) {
Status = XPmDevice_BringUp(Device);
} else {
Status = XST_SUCCESS;
}
break;
case (u8)XPM_DEVSTATE_RUNNING:
if ((u32)XPM_DEVSTATE_UNUSED == NextState) {
Status = Device->HandleEvent(&Device->Node,
XPM_DEVEVENT_SHUTDOWN);
} else {
Status = XST_SUCCESS;
}
break;
default:
Status = XST_FAILURE;
break;
}
return Status;
}
static const XPm_DeviceFsm XPmMemDeviceFsm = {
DEFINE_DEV_STATES(XPmMemDeviceStates),
DEFINE_DEV_TRANS(XPmMemDevTransitions),
.EnterState = HandleMemDeviceState,
};
XStatus XPmMemDevice_Init(XPm_MemDevice *MemDevice,
u32 Id,
u32 BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock, XPm_ResetNode *Reset, u32 MemStartAddress,
u32 MemEndAddress)
{
XStatus Status = XST_FAILURE;
u32 Type = NODETYPE(Id);
Status = XPmDevice_Init(&MemDevice->Device, Id, BaseAddress, Power, Clock,
Reset);
if (XST_SUCCESS != Status) {
goto done;
}
MemDevice->StartAddress = MemStartAddress;
MemDevice->EndAddress = MemEndAddress;
switch (Type) {
case (u32)XPM_NODETYPE_DEV_DDR:
MemDevice->Device.DeviceFsm = &XPmDDRDeviceFsm;
break;
case (u32)XPM_NODETYPE_DEV_TCM:
MemDevice->Device.DeviceFsm = &XPmTcmDeviceFsm;
break;
default:
MemDevice->Device.DeviceFsm = &XPmMemDeviceFsm;
break;
}
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilfpga_v5_2/src/interface/versal/xilfpga_versal.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilfpga_versal.h
* @addtogroup xfpga_apis XilFPGA APIs
* @{
*
* The XILFPGA library for Versal provides the interface to the application to
* configure the programmable logic (PL) though the PS.
*
* - Supported Features:
* - Partial Bitstream loading.
*
* # Xilfpga_PL library Interface modules {#xilfpgapllib}
* Xilfpga_PL library uses the below major components to configure the PL
* through PS.
* - xilmailbox library is used to transfer the actual Bit stream file from
* the PS to PL.
*
* @note XilFPGA library is capable of loading only .pdi format files into PL.
* The library does not support other file formats.
*
*
* ## Initialization & Writing Bitstream {#xilinit}
*
* Use the u32 XFpga_PL_BitSream_Load(); function to initialize the driver
* and load the Bitstream.
*
* @{
* @cond xilfpga_internal
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- ---- -------- --------------------------------------------------------
* 5.2 Nava 05/12/19 Added Versal platform support.
* 5.2 Nava 14/02/20 Removed unwanted header file inclusion.
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XILFPGA_VERSAL_H
#define XILFPGA_VERSAL_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/**
* Structure to store the PL Write Image details.
*
* @BitstreamAddr Bitstream image base address for Normal PDI LOAD.
* Image Id for Deferred PDI LOAD.
* @AddrPtr_Size Unused
* @Flags Flags are used to specify the type of Bitstream file.
* * BIT(0) - Bitstream type
* * 0 - Normal PDI Load
* * 1 - Deferred PDI Load
*
*/
typedef struct {
UINTPTR BitstreamAddr;
UINTPTR AddrPtr_Size;
u32 Flags;
}XFpga_Write;
/**
* Structure to store the PL Image details.
*
* @ReadbackAddr Address which is used to store the PL readback data.
* @ConfigReg Configuration register value to be returned (or)
* The number of Fpga configuration frames to read
*/
typedef struct {
UINTPTR ReadbackAddr;
u32 ConfigReg_NumFrames;
}XFpga_Read;
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* XILFPGA_VERSAL_H */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pmbus.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PMBUS_H_
#define XPM_PMBUS_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xparameters.h"
#ifdef XPAR_XIICPS_1_DEVICE_ID
#include "xiicps.h"
/****************************** PMBus Commands *******************************/
#define OPERATION 0x01
#define ON_OFF_CONFIG 0x02
/* Operation */
#define PM_OP_POWER_UP 0x80
#define PM_OP_POWER_DOWN 0x00
#define PM_OP_SOFT_OFF 0x40
/* On_off_config */
#define OP_POW_CTRL_CONFIG 0x1A
/************************** Function Declarations ***************************/
XStatus XPmBus_WriteByte(XIicPs *Iic, u16 SlaveAddr, u8 Command, u8 Byte);
XStatus XPmBus_WriteWord(XIicPs *Iic, u16 SlaveAddr, u8 Command, u16 Word);
XStatus XPmBus_ReadData(XIicPs *Iic, u8 *Buffer, u16 SlaveAddr,
u8 Command, s32 ByteCount);
#ifdef __cplusplus
}
#endif
#endif /* XPAR_XIICPS_1_DEVICE_ID */
#endif /* XPM_PMBUS_H_ */
<file_sep>/vitis_workspace/test_proj_plat/export/test_proj_plat/sw/test_proj_plat/standalone_domain/bspinclude/include/xipipsu_buf.h
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xipipsu_buf.h
* @addtogroup ipipsu_v2_6
* @{
* @details
*
* This is the header file for implementation of IPIPSU driver get buffer functions.
* Inter Processor Interrupt (IPI) is used for communication between
* different processors.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- --------------------------------------------------
* 2.6 sd 04/02/20 Restructured the code for more readability and modularity
* </pre>
*
*****************************************************************************/
#ifndef XIPIPSU_BUF_H_
#define XIPIPSU_BUF_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "xstatus.h"
/************************** Function Prototypes *****************************/
u32* XIpiPsu_GetBufferAddress(XIpiPsu *InstancePtr, u32 SrcCpuMask,
u32 DestCpuMask, u32 BufferType);
u32 XIpiPsu_GetBufferIndex(const XIpiPsu *InstancePtr, u32 CpuMask);
#ifdef __cplusplus
}
#endif
#endif /* XIPIPSU_BUF_H_ */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/versal/xsecure_sha.c
/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_sha.c
*
* This file contains the implementation of the interface functions for SHA
* driver. Refer to the header file xsecure_sha.h for more detailed information.
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.2 har 03/20/20 Initial release
*
* </pre>
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsecure_error.h"
#include "xsecure_sha_hw.h"
#include "xil_assert.h"
#include "xsecure_sha.h"
#include "xil_util.h"
/************************** Constant Definitions *****************************/
#define XSECURE_SHA3_HASH_LENGTH_IN_BITS (384U)
#define XSECURE_SHA3_HASH_LENGTH_IN_WORDS \
(XSECURE_SHA3_HASH_LENGTH_IN_BITS / 32U)
/* Nist padding masks */
#define XSECURE_SHA3_START_NIST_PADDING_MASK (0x06U)
#define XSECURE_SHA3_END_NIST_PADDING_MASK (0x80U)
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* @brief
* This inline function waits till SHA3 completes its operation.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
*
* @return
* - XST_SUCCESS if the SHA3 completes its operation.
* - XST_FAILURE if a timeout has occurred.
*
******************************************************************************/
inline u32 XSecure_Sha3WaitForDone(XSecure_Sha3 *InstancePtr)
{
return Xil_WaitForEvent((InstancePtr)->BaseAddress + XSECURE_SHA3_DONE_OFFSET,
XSECURE_SHA3_DONE_DONE,
XSECURE_SHA3_DONE_DONE,
XSECURE_SHA_TIMEOUT_MAX);
}
/************************** Function Prototypes ******************************/
static u32 XSecure_Sha3DmaTransfer(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size, u8 IsLast);
static u32 XSecure_Sha3DataUpdate(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size, u8 IsLastUpdate);
static void XSecure_Sha3NistPadd(XSecure_Sha3 *InstancePtr, u8 *Dst,
u32 MsgLen);
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/****************************************************************************/
/**
* @brief
* This function initializes a XSecure_Sha3 structure with the default values
* required for operating the SHA3 cryptographic engine.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param DmaPtr Pointer to the XPmcDma instance.
*
* @return XST_SUCCESS if initialization was successful
*
* @note The base address is initialized directly with value from
* xsecure_hw.h
*
*****************************************************************************/
u32 XSecure_Sha3Initialize(XSecure_Sha3 *InstancePtr, XPmcDma* DmaPtr)
{
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(DmaPtr != NULL);
InstancePtr->BaseAddress = XSECURE_SHA3_BASE;
InstancePtr->Sha3Len = 0U;
InstancePtr->DmaPtr = DmaPtr;
InstancePtr->IsLastUpdate = FALSE;
XSecure_SssInitialize(&(InstancePtr->SssInstance));
InstancePtr->Sha3State = XSECURE_SHA3_INITIALIZED;
return XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* This function is to notify this is the last update of data where sha padding
* is also been included along with the data in the next update call.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
*
* @return XST_SUCCESS if last update can be accepted
*
*
*****************************************************************************/
u32 XSecure_Sha3LastUpdate(XSecure_Sha3 *InstancePtr)
{
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED);
InstancePtr->IsLastUpdate = TRUE;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* Generate padding for the NIST SHA-3
*
* @param InstancePtr is a pointer to the XSecure_Sha3 instance.
* @param Dst is the pointer to location where padding is to be applied
* @param MsgLen is the length of padding in bytes
*
* @return None
*
* @note None
*
******************************************************************************/
static void XSecure_Sha3NistPadd(XSecure_Sha3 *InstancePtr, u8 *Dst, u32 MsgLen)
{
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsgLen != 0U);
(void)memset(Dst, 0, MsgLen);
Dst[0] = XSECURE_SHA3_START_NIST_PADDING_MASK;
Dst[MsgLen -1U] |= XSECURE_SHA3_END_NIST_PADDING_MASK;
}
/*****************************************************************************/
/**
* @brief
* This function configures Secure Stream Switch and starts the SHA-3 engine.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
*
* @return None
*
*
******************************************************************************/
void XSecure_Sha3Start(XSecure_Sha3 *InstancePtr)
{
/* Asserts validate the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->Sha3State == XSECURE_SHA3_INITIALIZED);
InstancePtr->Sha3Len = 0U;
InstancePtr->IsLastUpdate = FALSE;
InstancePtr->PartialLen = 0U;
(void)memset(InstancePtr->PartialData, 0, XSECURE_SHA3_BLOCK_LEN);
/* Reset SHA3 engine. */
XSecure_ReleaseReset(InstancePtr->BaseAddress,
XSECURE_SHA3_RESET_OFFSET);
/* Start SHA3 engine. */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_SHA3_START_OFFSET,
XSECURE_SHA3_START_START);
InstancePtr->Sha3State = XSECURE_SHA3_ENGINE_STARTED;
}
/*****************************************************************************/
/**
* @brief
* This function updates the SHA3 engine with the input data.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Data Pointer to the input data for hashing.
* @param Size Size of the input data in bytes.
*
* @return
* - XST_SUCCESS if the update is successful
* - XST_FAILURE if there is a failure in SSS config
*
******************************************************************************/
u32 XSecure_Sha3Update(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size)
{
u32 DataSize;
u32 TransferredBytes;
u32 Status = (u32)XST_FAILURE;
/* Asserts validate the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED);
InstancePtr->Sha3Len += Size;
DataSize = Size;
TransferredBytes = 0U;
/*
* PMC DMA can transfer Max 0x7FFFFFF no of words(0x1FFFFFFC bytes)
* at a time .So if the data sent more than that will be handled
* in the next update internally
*/
while (DataSize > XSECURE_PMC_DMA_MAX_TRANSFER) {
Status = XSecure_Sha3DataUpdate(InstancePtr,
(Data + TransferredBytes),
XSECURE_PMC_DMA_MAX_TRANSFER, 0);
if (Status != (u32)XST_SUCCESS){
goto END;
}
DataSize = DataSize - XSECURE_PMC_DMA_MAX_TRANSFER;
TransferredBytes = TransferredBytes +
XSECURE_PMC_DMA_MAX_TRANSFER;
}
Status = XSecure_Sha3DataUpdate(InstancePtr, (Data + TransferredBytes),
DataSize, (u8)InstancePtr->IsLastUpdate);
END:
if (Status != XST_SUCCESS) {
/* Set SHA under reset on failure condition */
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_SHA3_RESET_OFFSET);
InstancePtr->Sha3State = XSECURE_SHA3_INITIALIZED;
}
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function updates SHA3 engine with final data which includes SHA3
* padding and reads final hash on complete data.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Hash Pointer to location where resulting hash will
* be written
*
* @return
* - XST_SUCCESS if finished without any errors
* - XST_FAILURE if Sha3PadType is other than KECCAK or NIST
*
*****************************************************************************/
u32 XSecure_Sha3Finish(XSecure_Sha3 *InstancePtr, u8 *Hash)
{
u32 PadLen;
u32 Status = (u32)XST_FAILURE;
u32 Size;
/* Asserts validate the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Hash != NULL);
Xil_AssertNonvoid(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED);
PadLen = InstancePtr->Sha3Len % XSECURE_SHA3_BLOCK_LEN;
if (InstancePtr->IsLastUpdate != TRUE) {
PadLen = (PadLen == 0U)?(XSECURE_SHA3_BLOCK_LEN) :
(XSECURE_SHA3_BLOCK_LEN - PadLen);
XSecure_Sha3NistPadd(InstancePtr,
&InstancePtr->PartialData[InstancePtr->PartialLen],
PadLen);
Size = PadLen + InstancePtr->PartialLen;
Status = XSecure_Sha3DmaTransfer(InstancePtr,
(u8*)InstancePtr->PartialData,
Size, 1U);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
}
else {
Size = InstancePtr->PartialLen;
if (Size != 0x0U) {
Status = XST_FAILURE;
goto END;
}
}
/* Check the SHA3 DONE bit. */
Status = XSecure_Sha3WaitForDone(InstancePtr);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* If requested, read out the Hash in reverse order. */
if (Hash != NULL)
{
XSecure_Sha3ReadHash(InstancePtr, Hash);
}
END:
if (Size > 0x0U) {
(void)memset((void*)InstancePtr->PartialData, 0, Size);
}
/* Set SHA under reset */
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_SHA3_RESET_OFFSET);
InstancePtr->Sha3State = XSECURE_SHA3_INITIALIZED;
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function calculates the SHA-3 digest on the given input data.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param In Pointer to the input data for hashing
* @param Size Size of the input data
* @param Out Pointer to location where resulting hash will
* be written.
*
* @return
* - XST_SUCCESS if digest calculation done successfully
* - XST_FAILURE if any error from Sha3Update or Sha3Finish.
*
******************************************************************************/
u32 XSecure_Sha3Digest(XSecure_Sha3 *InstancePtr, const u8 *In, const u32 Size,
u8 *Out)
{
u32 Status = (u32)XST_FAILURE;
/* Asserts validate the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Out != NULL);
XSecure_Sha3Start(InstancePtr);
Status = XSecure_Sha3Update(InstancePtr, In, Size);
if (Status != (u32)XST_SUCCESS){
goto END;
}
Status = XSecure_Sha3Finish(InstancePtr, Out);
if (Status != (u32)XST_SUCCESS){
goto END;
}
END:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function reads the SHA3 hash of the data and it can be called
* between calls to XSecure_Sha3Update.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Hash Pointer to a buffer in which read hash will be
* stored.
*
* @return None
*
******************************************************************************/
void XSecure_Sha3ReadHash(XSecure_Sha3 *InstancePtr, u8 *Hash)
{
u32 Index;
u32 RegVal;
u32 *HashPtr = (u32 *)Hash;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Hash != NULL);
Xil_AssertVoid(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED);
for (Index = 0U; Index < XSECURE_SHA3_HASH_LENGTH_IN_WORDS; Index++)
{
RegVal = XSecure_ReadReg(InstancePtr->BaseAddress,
XSECURE_SHA3_DIGEST_0_OFFSET + (Index * 4U));
HashPtr[XSECURE_SHA3_HASH_LENGTH_IN_WORDS - Index - 1] = RegVal;
}
}
/*****************************************************************************/
/**
* @brief
* This function Transfers Data through Dma
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Data Pointer to the input data need to be transferred.
* @param Size Size of the input data in bytes.
*
* @return
* - XST_SUCCESS if the update is successful
* - XST_FAILURE if there an error occurs
*
******************************************************************************/
static u32 XSecure_Sha3DmaTransfer(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size, u8 IsLast)
{
u32 Status = (u32)XST_FAILURE;
/* Asserts validate the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Configure the SSS for SHA3 hashing. */
Status = XSecure_SssSha(&(InstancePtr->SssInstance),
InstancePtr->DmaPtr->Config.DeviceId);
if (Status != (u32)XST_SUCCESS){
goto ENDF;
}
XPmcDma_Transfer(InstancePtr->DmaPtr, XPMCDMA_SRC_CHANNEL,
(UINTPTR)Data, (u32)Size/4U, IsLast);
/* Checking the PMC DMA done bit should be enough. */
Status = XPmcDma_WaitForDoneTimeout(InstancePtr->DmaPtr,
XPMCDMA_SRC_CHANNEL);
if (Status != (u32)XST_SUCCESS) {
goto ENDF;
}
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(InstancePtr->DmaPtr, XPMCDMA_SRC_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
ENDF:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function updates hash for data block of size <= 512MB.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Data Pointer to the input data for hashing.
* @param Size Size of the input data in bytes.
*
* @return
* - XST_SUCCESS if the update is successful
* - XST_FAILURE if there is a failure
*
******************************************************************************/
static u32 XSecure_Sha3DataUpdate(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size, u8 IsLastUpdate)
{
u32 RemainingDataLen;
u32 DmableDataLen;
const u8 *DmableData;
u8 IsLast;
u32 Status = (u32)XST_FAILURE;
u32 PrevPartialLen;
u8 *PartialData;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED);
PrevPartialLen = InstancePtr->PartialLen;
PartialData = InstancePtr->PartialData;
RemainingDataLen = Size + PrevPartialLen;
IsLast = FALSE;
while(RemainingDataLen >= XSECURE_SHA3_BLOCK_LEN)
{
/* Handle Partial data and non dword aligned data address */
if ((PrevPartialLen != 0U) ||
(((UINTPTR)Data & XPMCDMA_ADDR_LSB_MASK) != 0U)) {
XSecure_MemCpy((void *)&PartialData[PrevPartialLen],
(void *)Data,
XSECURE_SHA3_BLOCK_LEN - PrevPartialLen);
DmableData = PartialData;
DmableDataLen = XSECURE_SHA3_BLOCK_LEN;
Data += XSECURE_SHA3_BLOCK_LEN - PrevPartialLen;
RemainingDataLen = RemainingDataLen - DmableDataLen;
}
else {
/* Process data of size in multiple of dwords */
DmableData = Data;
DmableDataLen = RemainingDataLen -
(RemainingDataLen % XSECURE_SHA3_BLOCK_LEN);
Data += DmableDataLen;
RemainingDataLen -= DmableDataLen;
}
if ((RemainingDataLen == 0U) && (IsLastUpdate == TRUE)) {
IsLast = TRUE;
}
Status = XSecure_Sha3DmaTransfer(InstancePtr, DmableData,
DmableDataLen, IsLast);
if (Status != (u32)XST_SUCCESS){
(void)memset(&InstancePtr->PartialData, 0,
sizeof(InstancePtr->PartialData));
goto END;
}
PrevPartialLen = 0U;
}
/* Handle remaining data during processing of next data chunk or during
data padding */
if(RemainingDataLen > 0U) {
XSecure_MemCpy((void *)(PartialData + PrevPartialLen), (void *)Data,
(RemainingDataLen - PrevPartialLen));
}
InstancePtr->PartialLen = RemainingDataLen;
(void)memset(&InstancePtr->PartialData[RemainingDataLen], 0,
sizeof(InstancePtr->PartialData) - RemainingDataLen);
Status = (u32) XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
*
* @brief This function performs known answer test(KAT) on SHA crypto engine.
*
* @param SecureSha3 Pointer to the XSecure_Sha3 instance.
*
* @return
* - XST_SUCCESS when KAT Pass
* - Error code on failure
*
******************************************************************************/
u32 XSecure_Sha3Kat(XSecure_Sha3 *SecureSha3)
{
u32 Status = (u32) XSECURE_SHA3_KAT_FAILED_ERROR;
u32 Index;
u8 OutVal[XSECURE_HASH_SIZE_IN_BYTES] = {0U};
u8 ExpectedHash[XSECURE_HASH_SIZE_IN_BYTES] = {
0x86U, 0x89U, 0xACU, 0xE3U, 0xA5U, 0xF9U, 0xF5U, 0x71U, 0xD6U,
0xBBU, 0xCDU, 0x1CU, 0xE2U, 0xD4U, 0x18U, 0xD8U, 0xF6U, 0xCFU,
0x76U, 0x82U, 0x56U, 0xDDU, 0x35U, 0x6DU, 0xB9U, 0xD6U, 0x1DU,
0x58U, 0xCFU, 0xCBU, 0x96U, 0xEBU, 0x49U, 0xC6U, 0xB9U, 0xDDU,
0xE3U, 0xA1U, 0x6EU, 0x63U, 0x5EU, 0x4BU, 0x61U, 0xB7U, 0x79U,
0xB1U, 0xFEU, 0x8EU
};
u32 DataValue[XSECURE_SHA3_BLOCK_LEN/4U] = {
0xA1D1199EU, 0xB9278FF8U, 0xCA22EDA5U, 0xB51272AAU,
0xA583A2F7U, 0x9513A099U, 0x1380DF32U, 0x4305F9A6U,
0x26E7DF18U, 0x1C4B3315U, 0xA84AF20EU, 0x7447560CU,
0x9580FB9FU, 0x0FE44017U, 0x9C25F0F7U, 0xA90D22A7U,
0xA2155D69U, 0x6F34008EU, 0x3FF5E1EAU, 0x84CC3585U,
0x3EAAB093U, 0x7DCFEDA7U, 0x21E00F23U, 0xE539A9F3U,
0x9C84DB7BU, 0x801ABECDU
};
XSecure_Sha3Start(SecureSha3);
Status = XSecure_Sha3LastUpdate(SecureSha3);
if (Status != (u32)XST_SUCCESS) {
Status = XSECURE_SHA3_LAST_UPDATE_ERROR;
goto END;
}
Status = XSecure_Sha3Update(SecureSha3, (u8 *)DataValue,
XSECURE_SHA3_BLOCK_LEN);
if (Status != (u32)XST_SUCCESS) {
Status = XSECURE_SHA3_PMC_DMA_UPDATE_ERROR;
goto END;
}
Status = XSecure_Sha3WaitForDone(SecureSha3);
if (Status != (u32)XST_SUCCESS) {
Status = XSECURE_SHA3_TIMEOUT_ERROR;
goto END;
}
XSecure_Sha3ReadHash(SecureSha3, (u8 *)OutVal);
for(Index = 0U; Index <XSECURE_HASH_SIZE_IN_BYTES; Index++) {
if (OutVal[Index] != ExpectedHash[Index]) {
Status = XSECURE_SHA3_KAT_FAILED_ERROR;
goto END;
}
}
Status = (u32)XST_SUCCESS;
END:
XSecure_SetReset(SecureSha3->BaseAddress,
XSECURE_SHA3_RESET_OFFSET);
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilsecure_v4_2/src/Makefile
###############################################################################
# Copyright (c) 2013 - 2020 Xilinx, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
###############################################################################
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS =
LIB=libxilsecure.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
SECURE_DIR = .
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
SECURE_SRCS := $(wildcard *.c)
SECURE_OBJS = $(addprefix $(SECURE_DIR)/, $(SECURE_SRCS:%.c=%.o))
INCLUDEFILES := $(wildcard *.h)
ifeq ($(notdir $(COMPILER)) , iccarm)
EXTRA_ARCHIVE_FLAGS=--create
else
ifeq ($(notdir $(COMPILER)) , armclang)
EXTRA_ARCHIVE_FLAGS=-rc
else
EXTRA_ARCHIVE_FLAGS=rc
endif
endif
libs: libxilsecure.a
libxilsecure.a: print_msg_secure $(SECURE_OBJS)
ifneq ("$(wildcard $(SECURE_DIR)/$(LIB))","")
cp $(SECURE_DIR)/$(LIB) $(RELEASEDIR)
$(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} ${SECURE_OBJS}
else
$(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} ${SECURE_OBJS}
endif
print_msg_secure:
@echo "Compiling XilSecure Library"
.PHONY: include
include: libxilsecure_includes
libxilsecure_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf $(SECURE_DIR)/${OBJECTS}
rm -rf ${RELEASEDIR}/${LIB}
$(SECURE_DIR)/%.o: $(SECURE_DIR)/%.c $(INCLUDEFILES)
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -c $< -o $@
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/include/xilfpga.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilfpga.h
* @addtogroup xfpga_apis XilFPGA APIs
* @{
*
* Xilfpga Error format:
* Lower level Errors + Interface specific Errors + Xilfpga top layer Errors
*----------------------------------------------------------------------------
* Lower level Errors | Interface Specific Errors | Xilfpga top layer Errors
* (other libarier | (PCAP Interface) |
* or drivers | |
* Used by xilfpga) | |
* ----------------------------------------------------------------------------
* 31 - 16 bits | 15 - 8 bits | 7 - 0 bits
* ----------------------------------------------------------------------------
* Xilfpga Top Layer:
* The functionality exist in this layers is completely Interface agnostic.
* It provides a unique interface to load the Bitstream across multiple
* platforms.(ie; ZynqMP)
*
* Interface Specific layer:
* This layer is responsible for providing the interface specific related
* errors.
* -->In Case of ZynqMp, it provides the errors related to PCAP Interface.
*
* Xilfpga lower layer:
* This layer is responsible for providing the Error related to the lower
* level drivers used by Interface layer.
*
* @{
* @cond xilfpga_internal
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.2 Nava 08/06/16 Refactor the xilfpga library to support
* different PL programming Interfaces.
* 4.2 adk 11/07/18 Added support for readback of PL configuration data.
* 4.2 Nava 16/08/18 Modified the PL data handling Logic to support
* different PL programming interfaces.
* 4.2 adk 28/08/18 Fixed misra-c required standard violations.
* 4.2 Nava 15/09/18 Fixed global function call-backs issue.
* 5.0 Nava 11/05/18 Added full bitstream loading support for versal Platform.
* 5.0 Div 21/01/19 Fixed misra-c required standard violations.
* 5.0 Nava 06/02/19 Remove redundant API's from the interface agnostic layer
* and make the existing API's generic to support both
* ZynqMP and versal platforms.
* 5.0 Nava 26/02/19 Update the data handling logic to avoid the code
* duplication
* 5.0 sne 27/03/19 Fixed misra-c violations.
* 5.0 Nava 29/03/19 Removed vesal platform related changes.As per the new
* design, the Bitstream loading for versal platform is
* done by PLM based on the CDO's data exists in the PDI
* images. So there is no need of xilfpga API's for versal
* platform to configure the PL.
* 5.2 Nava 05/12/19 Added Versal platform support.
* 5.2 Nava 14/02/20 Added Bitstream loading support by using IPI services
* for ZynqMP platform.
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XILFPGA_H
#define XILFPGA_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_io.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_printf.h"
#include "xparameters.h"
#include "xfpga_config.h"
/**************************** Type Definitions *******************************/
/**
* @XFpga_ValidateBitstream: validate the Bitstream header before
* programming the PL
* @xilfpga_PreConfig: prepare the FPGA to receive confuration data
* @xilfpga_WriteToPl: write count bytes of configuration data to
* the FPGA
* @xilfpga_PostConfig: set FPGA to operating state after writing
* is done
* @XFpga_GetInterfaceStatus: Provides the STATUS of PL programming interface
* @Xfpga_GetConfigReg: Returns the value of the specified configuration
* register
* @XFpga_GetConfigData: Provides the FPGA readback data.
* @PLInfo: Which is used to store the secure image data.
* @WriteInfo: XFpga_Write structure which is used to store the PL Write
* Image details.
* @ReadInfo: XFpga_Read structure which is used to store the PL Image
* readback details
*/
typedef struct XFpgatag{
u32 (*XFpga_ValidateBitstream)(struct XFpgatag *InstancePtr);
u32 (*XFpga_PreConfig)(struct XFpgatag *InstancePtr);
u32 (*XFpga_WriteToPl)(struct XFpgatag *InstancePtr);
u32 (*XFpga_PostConfig)(struct XFpgatag *InstancePtr);
#ifndef versal
u32 (*XFpga_GetInterfaceStatus)(void);
u32 (*XFpga_GetConfigReg)(const struct XFpgatag *InstancePtr);
u32 (*XFpga_GetConfigData)(const struct XFpgatag *InstancePtr);
#ifndef XFPGA_SECURE_IPI_MODE_EN
XFpga_Info PLInfo;
#endif
XFpga_Read ReadInfo;
#endif
XFpga_Write WriteInfo;
}XFpga;
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XFPGA_SUCCESS (0x0U)
#define XFPGA_FAILURE (0x1U)
#define XFPGA_VALIDATE_ERROR (0x2U)
#define XFPGA_PRE_CONFIG_ERROR (0x3U)
#define XFPGA_WRITE_BITSTREAM_ERROR (0x4U)
#define XFPGA_POST_CONFIG_ERROR (0x5U)
#define XFPGA_OPS_NOT_IMPLEMENTED (0x6U)
#define XFPGA_INPROGRESS (0x7U)
#define XFPGA_FULLBIT_EN (0x00000000U)
#define XFPGA_PARTIAL_EN (0x00000001U)
#define XFPGA_AUTHENTICATION_DDR_EN (0x00000002U)
#define XFPGA_AUTHENTICATION_OCM_EN (0x00000004U)
#define XFPGA_ENCRYPTION_USERKEY_EN (0x00000008U)
#define XFPGA_ENCRYPTION_DEVKEY_EN (0x00000010U)
#define XFPGA_ONLY_BIN_EN (0x00000020U)
/* FPGA invalid interface status */
#define XFPGA_INVALID_INTERFACE_STATUS (0xFFFFFFFFU)
#ifndef versal
#define XFPGA_SECURE_FLAGS ( \
XFPGA_AUTHENTICATION_DDR_EN \
| XFPGA_AUTHENTICATION_OCM_EN \
| XFPGA_ENCRYPTION_USERKEY_EN \
| XFPGA_ENCRYPTION_DEVKEY_EN \
)
#define XFPGA_AUTH_ENC_USERKEY_DDR ( \
XFPGA_AUTHENTICATION_DDR_EN \
| XFPGA_ENCRYPTION_USERKEY_EN \
)
#define XFPGA_AUTH_ENC_DEVKEY_DDR ( \
XFPGA_AUTHENTICATION_DDR_EN \
| XFPGA_ENCRYPTION_DEVKEY_EN \
)
#define XFPGA_AUTH_ENC_USERKEY_OCM ( \
XFPGA_AUTHENTICATION_OCM_EN \
| XFPGA_ENCRYPTION_USERKEY_EN \
)
#define XFPGA_AUTH_ENC_DEVKEY_OCM ( \
XFPGA_AUTHENTICATION_OCM_EN \
| XFPGA_ENCRYPTION_DEVKEY_EN \
)
#endif
#define Xfpga_Printf(DebugType, ...) \
if ((DebugType) != 0U) \
{xil_printf (__VA_ARGS__); }
#define XFPGA_ERR_MASK (0xFFU)
#define XFPGA_ERR_INTERFACE_MASK (0xFFFFFF00U)
#define XFPGA_UPDATE_ERR(XfpgaErr, InterfaceErr) \
(((InterfaceErr)&XFPGA_ERR_INTERFACE_MASK) + \
((XfpgaErr)&XFPGA_ERR_MASK))
/** @endcond*/
/************************** Function Prototypes ******************************/
u32 XFpga_Initialize(XFpga *InstancePtr);
u32 XFpga_PL_BitStream_Load(XFpga *InstancePtr,
UINTPTR BitstreamImageAddr,
UINTPTR AddrPtr_Size, u32 Flags);
u32 XFpga_PL_Preconfig(XFpga *InstancePtr);
u32 XFpga_PL_Write(XFpga *InstancePtr,UINTPTR BitstreamImageAddr,
UINTPTR AddrPtr_Size, u32 Flags);
u32 XFpga_PL_PostConfig(XFpga *InstancePtr);
u32 XFpga_PL_ValidateImage(XFpga *InstancePtr,
UINTPTR BitstreamImageAddr,
UINTPTR AddrPtr_Size, u32 Flags);
#ifndef versal
u32 XFpga_GetPlConfigData(XFpga *InstancePtr, UINTPTR ReadbackAddr,
u32 ConfigReg_NumFrames);
u32 XFpga_GetPlConfigReg(XFpga *InstancePtr, UINTPTR ReadbackAddr,
u32 ConfigReg_NumFrames);
u32 XFpga_InterfaceStatus(XFpga *InstancePtr);
#endif
#ifdef __cplusplus
}
#endif
#endif /* XILFPGA_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/rtc.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _RTC_H_
#define _RTC_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* RTC Base Address
*/
#define RTC_BASEADDR ((u32)0XFFA60000U)
/**
* Register: RTC_SET_TIME_WRITE
*/
#define RTC_SET_TIME_WRITE ( ( RTC_BASEADDR ) + ((u32)0X00000000U) )
#define RTC_SET_TIME_WRITE_VALUE_SHIFT 0
#define RTC_SET_TIME_WRITE_VALUE_WIDTH 32
#define RTC_SET_TIME_WRITE_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RTC_SET_TIME_READ
*/
#define RTC_SET_TIME_READ ( ( RTC_BASEADDR ) + ((u32)0X00000004U) )
#define RTC_SET_TIME_READ_VALUE_SHIFT 0
#define RTC_SET_TIME_READ_VALUE_WIDTH 32
#define RTC_SET_TIME_READ_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RTC_CALIB_WRITE
*/
#define RTC_CALIB_WRITE ( ( RTC_BASEADDR ) + ((u32)0X00000008U) )
#define RTC_CALIB_WRITE_FRACTION_EN_SHIFT 20
#define RTC_CALIB_WRITE_FRACTION_EN_WIDTH 1
#define RTC_CALIB_WRITE_FRACTION_EN_MASK ((u32)0X00100000U)
#define RTC_CALIB_WRITE_FRACTION_DATA_SHIFT 16
#define RTC_CALIB_WRITE_FRACTION_DATA_WIDTH 4
#define RTC_CALIB_WRITE_FRACTION_DATA_MASK ((u32)0X000F0000U)
#define RTC_CALIB_WRITE_MAX_TICK_SHIFT 0
#define RTC_CALIB_WRITE_MAX_TICK_WIDTH 16
#define RTC_CALIB_WRITE_MAX_TICK_MASK ((u32)0X0000FFFFU)
/**
* Register: RTC_CALIB_READ
*/
#define RTC_CALIB_READ ( ( RTC_BASEADDR ) + ((u32)0X0000000CU) )
#define RTC_CALIB_READ_FRACTION_EN_SHIFT 20
#define RTC_CALIB_READ_FRACTION_EN_WIDTH 1
#define RTC_CALIB_READ_FRACTION_EN_MASK ((u32)0X00100000U)
#define RTC_CALIB_READ_FRACTION_DATA_SHIFT 16
#define RTC_CALIB_READ_FRACTION_DATA_WIDTH 4
#define RTC_CALIB_READ_FRACTION_DATA_MASK ((u32)0X000F0000U)
#define RTC_CALIB_READ_MAX_TICK_SHIFT 0
#define RTC_CALIB_READ_MAX_TICK_WIDTH 16
#define RTC_CALIB_READ_MAX_TICK_MASK ((u32)0X0000FFFFU)
/**
* Register: RTC_CURRENT_TIME
*/
#define RTC_CURRENT_TIME ( ( RTC_BASEADDR ) + ((u32)0X00000010U) )
#define RTC_CURRENT_TIME_VALUE_SHIFT 0
#define RTC_CURRENT_TIME_VALUE_WIDTH 32
#define RTC_CURRENT_TIME_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RTC_CURRENT_TICK
*/
#define RTC_CURRENT_TICK ( ( RTC_BASEADDR ) + ((u32)0X00000014U) )
#define RTC_CURRENT_TICK_VALUE_SHIFT 0
#define RTC_CURRENT_TICK_VALUE_WIDTH 16
#define RTC_CURRENT_TICK_VALUE_MASK ((u32)0X0000FFFFU)
/**
* Register: RTC_ALARM
*/
#define RTC_ALARM ( ( RTC_BASEADDR ) + ((u32)0X00000018U) )
#define RTC_ALARM_VALUE_SHIFT 0
#define RTC_ALARM_VALUE_WIDTH 32
#define RTC_ALARM_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RTC_RTC_INT_STATUS
*/
#define RTC_RTC_INT_STATUS ( ( RTC_BASEADDR ) + ((u32)0X00000020U) )
#define RTC_RTC_INT_STATUS_ALARM_SHIFT 1
#define RTC_RTC_INT_STATUS_ALARM_WIDTH 1
#define RTC_RTC_INT_STATUS_ALARM_MASK ((u32)0X00000002U)
#define RTC_RTC_INT_STATUS_SECONDS_SHIFT 0
#define RTC_RTC_INT_STATUS_SECONDS_WIDTH 1
#define RTC_RTC_INT_STATUS_SECONDS_MASK ((u32)0X00000001U)
/**
* Register: RTC_RTC_INT_MASK
*/
#define RTC_RTC_INT_MASK ( ( RTC_BASEADDR ) + ((u32)0X00000024U) )
#define RTC_RTC_INT_MASK_ALARM_SHIFT 1
#define RTC_RTC_INT_MASK_ALARM_WIDTH 1
#define RTC_RTC_INT_MASK_ALARM_MASK ((u32)0X00000002U)
#define RTC_RTC_INT_MASK_SECONDS_SHIFT 0
#define RTC_RTC_INT_MASK_SECONDS_WIDTH 1
#define RTC_RTC_INT_MASK_SECONDS_MASK ((u32)0X00000001U)
/**
* Register: RTC_RTC_INT_EN
*/
#define RTC_RTC_INT_EN ( ( RTC_BASEADDR ) + ((u32)0X00000028U) )
#define RTC_RTC_INT_EN_ALARM_SHIFT 1
#define RTC_RTC_INT_EN_ALARM_WIDTH 1
#define RTC_RTC_INT_EN_ALARM_MASK ((u32)0X00000002U)
#define RTC_RTC_INT_EN_SECONDS_SHIFT 0
#define RTC_RTC_INT_EN_SECONDS_WIDTH 1
#define RTC_RTC_INT_EN_SECONDS_MASK ((u32)0X00000001U)
/**
* Register: RTC_RTC_INT_DIS
*/
#define RTC_RTC_INT_DIS ( ( RTC_BASEADDR ) + ((u32)0X0000002CU) )
#define RTC_RTC_INT_DIS_ALARM_SHIFT 1
#define RTC_RTC_INT_DIS_ALARM_WIDTH 1
#define RTC_RTC_INT_DIS_ALARM_MASK ((u32)0X00000002U)
#define RTC_RTC_INT_DIS_SECONDS_SHIFT 0
#define RTC_RTC_INT_DIS_SECONDS_WIDTH 1
#define RTC_RTC_INT_DIS_SECONDS_MASK ((u32)0X00000001U)
/**
* Register: RTC_ADDR_ERROR
*/
#define RTC_ADDR_ERROR ( ( RTC_BASEADDR ) + ((u32)0X00000030U) )
#define RTC_ADDR_ERROR_STATUS_SHIFT 0
#define RTC_ADDR_ERROR_STATUS_WIDTH 1
#define RTC_ADDR_ERROR_STATUS_MASK ((u32)0X00000001U)
/**
* Register: RTC_ADDR_ERROR_INT_MASK
*/
#define RTC_ADDR_ERROR_INT_MASK ( ( RTC_BASEADDR ) + ((u32)0X00000034U) )
#define RTC_ADDR_ERROR_INT_MASK_MASK_SHIFT 0
#define RTC_ADDR_ERROR_INT_MASK_MASK_WIDTH 1
#define RTC_ADDR_ERROR_INT_MASK_MASK_MASK ((u32)0X00000001U)
/**
* Register: RTC_ADDR_ERROR_INT_EN
*/
#define RTC_ADDR_ERROR_INT_EN ( ( RTC_BASEADDR ) + ((u32)0X00000038U) )
#define RTC_ADDR_ERROR_INT_EN_MASK_SHIFT 0
#define RTC_ADDR_ERROR_INT_EN_MASK_WIDTH 1
#define RTC_ADDR_ERROR_INT_EN_MASK_MASK ((u32)0X00000001U)
/**
* Register: RTC_ADDR_ERROR_INT_DIS
*/
#define RTC_ADDR_ERROR_INT_DIS ( ( RTC_BASEADDR ) + ((u32)0X0000003CU) )
#define RTC_ADDR_ERROR_INT_DIS_MASK_SHIFT 0
#define RTC_ADDR_ERROR_INT_DIS_MASK_WIDTH 1
#define RTC_ADDR_ERROR_INT_DIS_MASK_MASK ((u32)0X00000001U)
/**
* Register: RTC_CONTROL
*/
#define RTC_CONTROL ( ( RTC_BASEADDR ) + ((u32)0X00000040U) )
#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31
#define RTC_CONTROL_BATTERY_DISABLE_WIDTH 1
#define RTC_CONTROL_BATTERY_DISABLE_MASK ((u32)0X80000000U)
#define RTC_CONTROL_OSC_CNTRL_SHIFT 24
#define RTC_CONTROL_OSC_CNTRL_WIDTH 4
#define RTC_CONTROL_OSC_CNTRL_MASK ((u32)0X0F000000U)
#define RTC_CONTROL_SLVERR_ENABLE_SHIFT 0
#define RTC_CONTROL_SLVERR_ENABLE_WIDTH 1
#define RTC_CONTROL_SLVERR_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: RTC_SAFETY_CHK
*/
#define RTC_SAFETY_CHK ( ( RTC_BASEADDR ) + ((u32)0X00000050U) )
#define RTC_SAFETY_CHK_REG_SHIFT 0
#define RTC_SAFETY_CHK_REG_WIDTH 32
#define RTC_SAFETY_CHK_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RTC_ECO
*/
#define RTC_ECO ( ( RTC_BASEADDR ) + ((u32)0X00000060U) )
#define RTC_ECO_REG_SHIFT 0
#define RTC_ECO_REG_WIDTH 32
#define RTC_ECO_REG_MASK ((u32)0XFFFFFFFFU)
#ifdef __cplusplus
}
#endif
#endif /* _RTC_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/zynqmp/client/common/pm_api_sys.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file pm_api_sys.h
* PM API System implementation
* @addtogroup xpm_apis XilPM APIs
*
* @{
*****************************************************************************/
#ifndef PM_API_SYS_H
#define PM_API_SYS_H
#include <xil_types.h>
#include <xstatus.h>
#include <xipipsu.h>
#include "pm_defs.h"
#include "pm_common.h"
#ifdef __cplusplus
extern "C" {
#endif
XStatus XPm_InitXilpm(XIpiPsu *IpiInst);
void XPm_SuspendFinalize(void);
enum XPmBootStatus XPm_GetBootStatus(void);
/* System-level API function declarations */
XStatus XPm_RequestSuspend(const enum XPmNodeId target,
const enum XPmRequestAck ack,
const u32 latency,
const u8 state);
XStatus XPm_SelfSuspend(const enum XPmNodeId nid,
const u32 latency,
const u8 state,
const u64 address);
XStatus XPm_ForcePowerDown(const enum XPmNodeId target,
const enum XPmRequestAck ack);
XStatus XPm_AbortSuspend(const enum XPmAbortReason reason);
XStatus XPm_RequestWakeUp(const enum XPmNodeId target,
const bool setAddress,
const u64 address,
const enum XPmRequestAck ack);
XStatus XPm_SetWakeUpSource(const enum XPmNodeId target,
const enum XPmNodeId wkup_node,
const u8 enable);
XStatus XPm_SystemShutdown(u32 type, u32 subtype);
XStatus XPm_SetConfiguration(const u32 address);
XStatus XPm_InitFinalize(void);
/* Callback API function */
/*
* pm_init_suspend - Init suspend callback arguments (save for custom handling)
*/
struct pm_init_suspend {
volatile bool received; /**< Has init suspend callback been received/handled */
enum XPmSuspendReason reason; /**< Reason of initializing suspend */
u32 latency; /**< Maximum allowed latency */
u32 state; /**< Targeted sleep/suspend state */
u32 timeout; /**< Period of time the client has to response */
};
/*
* pm_acknowledge - Acknowledge callback arguments (save for custom handling)
*/
struct pm_acknowledge {
volatile bool received; /**< Has acknowledge argument been received? */
enum XPmNodeId node; /**< Node argument about which the acknowledge is */
XStatus status; /**< Acknowledged status */
u32 opp; /**< Operating point of node in question */
};
/**
* XPm_Notifier - Notifier structure registered with a callback by app
*/
typedef struct XPm_Ntfier {
/**
* Custom callback handler to be called when the notification is
* received. The custom handler would execute from interrupt
* context, it shall return quickly and must not block! (enables
* event-driven notifications)
*/
void (*const callback)(struct XPm_Ntfier* const notifier);
enum XPmNodeId node; /**< Node argument (the node to receive notifications about) */
enum XPmNotifyEvent event; /**< Event argument (the event type to receive notifications about) */
u32 flags; /**< Flags */
/**
* Operating point of node in question. Contains the value updated
* when the last event notification is received. User shall not
* modify this value while the notifier is registered.
*/
volatile u32 oppoint;
/**
* How many times the notification has been received - to be used
* by application (enables polling). User shall not modify this
* value while the notifier is registered.
*/
volatile u32 received;
/**
* Pointer to next notifier in linked list. Must not be modified
* while the notifier is registered. User shall not ever modify
* this value.
*/
struct XPm_Ntfier* next;
} XPm_Notifier;
/**
* XPm_NodeStatus - struct containing node status information
*/
typedef struct XPm_NdStatus {
u32 status; /**< Node power state */
u32 requirements; /**< Current requirements asserted on the node (slaves only) */
u32 usage; /**< Usage information (which master is currently using the slave) */
} XPm_NodeStatus;
/********************************************************************/
/*
* Global data declarations
********************************************************************/
extern struct pm_init_suspend pm_susp;
extern struct pm_acknowledge pm_ack;
void XPm_InitSuspendCb(const enum XPmSuspendReason reason,
const u32 latency,
const u32 state,
const u32 timeout);
void XPm_AcknowledgeCb(const enum XPmNodeId node,
const XStatus status,
const u32 oppoint);
void XPm_NotifyCb(const enum XPmNodeId node,
const enum XPmNotifyEvent event,
const u32 oppoint);
/* API functions for managing PM Slaves */
XStatus XPm_RequestNode(const enum XPmNodeId node,
const u32 capabilities,
const u32 qos,
const enum XPmRequestAck ack);
XStatus XPm_ReleaseNode(const enum XPmNodeId node);
XStatus XPm_SetRequirement(const enum XPmNodeId nid,
const u32 capabilities,
const u32 qos,
const enum XPmRequestAck ack);
XStatus XPm_SetMaxLatency(const enum XPmNodeId node,
const u32 latency);
/* Miscellaneous API functions */
XStatus XPm_GetApiVersion(u32 *version);
XStatus XPm_GetNodeStatus(const enum XPmNodeId node,
XPm_NodeStatus *const nodestatus);
XStatus XPm_RegisterNotifier(XPm_Notifier* const notifier);
XStatus XPm_UnregisterNotifier(XPm_Notifier* const notifier);
XStatus XPm_GetOpCharacteristic(const enum XPmNodeId node,
const enum XPmOpCharType type,
u32* const result);
/* Direct-Control API functions */
XStatus XPm_ResetAssert(const enum XPmReset reset,
const enum XPmResetAction resetaction);
XStatus XPm_ResetGetStatus(const enum XPmReset reset, u32 *status);
XStatus XPm_MmioWrite(const u32 address, const u32 mask, const u32 value);
XStatus XPm_MmioRead(const u32 address, u32 *const value);
/* Clock API */
XStatus XPm_ClockEnable(const enum XPmClock clock);
XStatus XPm_ClockDisable(const enum XPmClock clock);
XStatus XPm_ClockGetStatus(const enum XPmClock clock, u32 *const status);
XStatus XPm_ClockSetDivider(const enum XPmClock clock, const u32 divider);
XStatus XPm_ClockGetDivider(const enum XPmClock clock, u32 *const divider);
XStatus XPm_ClockSetParent(const enum XPmClock clock,
const enum XPmClock parent);
XStatus XPm_ClockGetParent(const enum XPmClock clock,
enum XPmClock *const parent);
XStatus XPm_ClockSetRate(const enum XPmClock clock, const u32 rate);
XStatus XPm_ClockGetRate(const enum XPmClock clock, u32 *const rate);
/* PLL API */
XStatus XPm_PllSetParameter(const enum XPmNodeId node,
const enum XPmPllParam parameter,
const u32 value);
XStatus XPm_PllGetParameter(const enum XPmNodeId node,
const enum XPmPllParam parameter,
u32 *const value);
XStatus XPm_PllSetMode(const enum XPmNodeId node, const enum XPmPllMode mode);
XStatus XPm_PllGetMode(const enum XPmNodeId node, enum XPmPllMode* const mode);
/* PIN Mux control API */
XStatus XPm_PinCtrlRequest(const u32 pin);
XStatus XPm_PinCtrlRelease(const u32 pin);
XStatus XPm_PinCtrlSetFunction(const u32 pin, const enum XPmPinFn fn);
XStatus XPm_PinCtrlGetFunction(const u32 pin, enum XPmPinFn* const fn);
XStatus XPm_PinCtrlSetParameter(const u32 pin,
const enum XPmPinParam param,
const u32 value);
XStatus XPm_PinCtrlGetParameter(const u32 pin,
const enum XPmPinParam param,
u32* const value);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* PM_API_SYS_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/usbpsu_v1_7/src/xusbpsu_command.c
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_command.c
* @addtogroup usbpsu_v1_7
* @{
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 pm 03/03/20 First release
* </pre>
*
*****************************************************************************/
/***************************** Include Files *********************************/
#include "xusbpsu_endpoint.h"
#include "xusbpsu_local.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
* Returns zeroed parameters to be used by Endpoint commands
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return Zeroed Params structure pointer.
*
* @note None.
*
*****************************************************************************/
struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr)
{
if (InstancePtr == NULL) {
return NULL;
}
InstancePtr->EpParams.Param0 = 0x00U;
InstancePtr->EpParams.Param1 = 0x00U;
InstancePtr->EpParams.Param2 = 0x00U;
return &InstancePtr->EpParams;
}
/****************************************************************************/
/**
* @brief
* Enables Endpoint for sending/receiving data.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEpNum is USB endpoint number.
* @param Dir is direction of endpoint
* - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
* @param Maxsize is size of Endpoint size.
* @param Type is Endpoint type Control/Bulk/Interrupt/Isoc.
* @param Restore should be true if saved state should be restored;
* typically this would be false
*
* @return XST_SUCCESS else XST_FAILURE.
*
* @note None.
*
****************************************************************************/
s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
u16 Maxsize, u8 Type, u8 Restore)
{
struct XUsbPsu_Ep *Ept;
struct XUsbPsu_Trb *TrbStHw, *TrbLink;
u32 RegVal;
u32 PhyEpNum;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
(Dir == XUSBPSU_EP_DIR_OUT));
Xil_AssertNonvoid((Maxsize >= 64U) && (Maxsize <= 1024U));
PhyEpNum = XUSBPSU_PhysicalEp(UsbEpNum, Dir);
Ept = &InstancePtr->eps[PhyEpNum];
Ept->UsbEpNum = UsbEpNum;
Ept->Direction = Dir;
Ept->Type = Type;
Ept->MaxSize = Maxsize;
Ept->PhyEpNum = (u8)PhyEpNum;
Ept->CurUf = 0U;
if (InstancePtr->IsHibernated == FALSE) {
Ept->TrbEnqueue = 0U;
Ept->TrbDequeue = 0U;
}
if (((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U)
|| (InstancePtr->IsHibernated == TRUE)) {
if (XUsbPsu_StartEpConfig(InstancePtr, UsbEpNum,
Dir) == XST_FAILURE) {
return XST_FAILURE;
}
}
if (XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize,
Type, Restore) == XST_FAILURE) {
return XST_FAILURE;
}
if (((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U)
|| (InstancePtr->IsHibernated == TRUE)) {
if (XUsbPsu_SetXferResource(InstancePtr, UsbEpNum,
Dir) == XST_FAILURE) {
return XST_FAILURE;
}
Ept->EpStatus |= XUSBPSU_EP_ENABLED;
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
RegVal |= XUSBPSU_DALEPENA_EP(Ept->PhyEpNum);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
/* Following code is only applicable for ISO XFER */
TrbStHw = &Ept->EpTrb[0U];
/* Link TRB. The HWO bit is never reset */
TrbLink = &Ept->EpTrb[NO_OF_TRB_PER_EP];
memset(TrbLink, 0x00U, sizeof(struct XUsbPsu_Trb));
TrbLink->BufferPtrLow = (UINTPTR)TrbStHw;
TrbLink->BufferPtrHigh = ((UINTPTR)TrbStHw >> 16U) >> 16U;
TrbLink->Ctrl |= XUSBPSU_TRBCTL_LINK_TRB;
TrbLink->Ctrl |= XUSBPSU_TRB_CTRL_HWO;
/* flush the link trb */
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)TrbLink,
sizeof(struct XUsbPsu_Trb));
}
}
return XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Disables Endpoint.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEpNum is USB endpoint number.
* @param Dir is direction of endpoint
* - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
*
* @return XST_SUCCESS else XST_FAILURE.
*
* @note None.
*
****************************************************************************/
s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
{
u32 RegVal;
u8 PhyEpNum;
struct XUsbPsu_Ep *Ept;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
(Dir == XUSBPSU_EP_DIR_OUT));
PhyEpNum = XUSBPSU_PhysicalEp(UsbEpNum, Dir);
Ept = &InstancePtr->eps[PhyEpNum];
/* make sure HW endpoint isn't stalled */
if ((Ept->EpStatus & XUSBPSU_EP_STALL) != (u32)0U) {
XUsbPsu_EpClearStall(InstancePtr, Ept->UsbEpNum,
Ept->Direction);
}
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
RegVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
Ept->Type = 0U;
Ept->EpStatus = 0U;
Ept->MaxSize = 0U;
Ept->TrbEnqueue = 0U;
Ept->TrbDequeue = 0U;
return XST_SUCCESS;
}
/****************************************************************************/
/**
* Sends Endpoint command to Endpoint.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEpNum is USB endpoint number.
* @param Dir is direction of endpoint
* - XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
* @param Cmd is Endpoint command.
* @param Params is Endpoint command parameters.
*
* @return XST_SUCCESS else XST_FAILURE.
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
u32 Cmd, struct XUsbPsu_EpParams *Params)
{
u32 PhyEpNum;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
(Dir == XUSBPSU_EP_DIR_OUT));
PhyEpNum = XUSBPSU_PhysicalEp(UsbEpNum, Dir);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR0(PhyEpNum),
Params->Param0);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR1(PhyEpNum),
Params->Param1);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR2(PhyEpNum),
Params->Param2);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum),
Cmd | XUSBPSU_DEPCMD_CMDACT);
if (XUsbPsu_WaitClearTimeout(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum),
XUSBPSU_DEPCMD_CMDACT, 500U) == (s32)XST_FAILURE) {
return (s32)XST_FAILURE;
}
return (s32)XST_SUCCESS;
}
#ifdef XUSBPSU_HIBERNATION_ENABLE
/*****************************************************************************/
/**
* Send generic command for gadget
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
* @param cmd is command to be sent
* @param param is parameter for the command, to be written in DGCMDPAR
* register
*
* @return
* - XST_SUCCESS on success
* - XST_FAILURE on timeout
* - XST_REGISTER_ERROR on status error
*
* @note None.
*
******************************************************************************/
s32 XUsbPsu_SendGadgetGenericCmd(struct XUsbPsu *InstancePtr, u32 cmd,
u32 param)
{
u32 RegVal, retry = 500U;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DGCMDPAR, param);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DGCMD,
cmd | XUSBPSU_DGCMD_CMDACT);
while (retry > 0U) {
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DGCMD);
if ((RegVal & XUSBPSU_DGCMD_CMDACT) == (u32)0U) {
if (XUSBPSU_DGCMD_STATUS(RegVal) != (u32)0U) {
return (s32)XST_REGISTER_ERROR;
}
return (s32)XST_SUCCESS;
}
retry = retry - 1U;
}
return (s32)XST_FAILURE;
}
#endif /* XUSBPSU_HIBERNATION_ENABLE */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/include/xavbuf_clk.h
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/******************************************************************************/
/**
*
* @file xavbuf_clk.h
*
* This header file contains the identifiers and low-level driver functions (or
* macros) that can be used to configure PLL to generate required frequency.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 mh 06/24/17 Initial release.
* 2.1 tu 12/29/17 LPD and FPD offsets adjusted
* </pre>
*
*******************************************************************************/
#ifndef XAVBUF_CLK_H_
#define XAVBUF_CLK_H_
/******************************* Include Files ********************************/
#include "xavbuf_hw.h"
#include "xstatus.h"
#include "sleep.h"
/****************************** Type Definitions ******************************/
/**
* This enum enumerates various PLL
*/
enum PLL{
APLL = 0,
DPLL = 1,
VPLL = 2,
IOPLL = 3,
RPLL = 4
};
/**
* This typedef enumerates various variables used to configure Pll
*/
typedef struct {
u64 BaseAddress;
u64 Fractional;
u64 RefClkFreqhz;
u32 Divider;
u8 Offset;
u8 ClkDividBy2;
u8 ExtDivider0;
u8 ExtDivider1;
u8 ExtDividerCnt;
u8 DomainSwitchDiv;
u8 FracIntegerFBDIV;
u8 IntegerFBDIV;
u8 InputRefClk;
u8 Fpd;
u8 Pll;
}XAVBuf_Pll;
/**************************** Function Prototypes *****************************/
int XAVBuf_SetPixelClock(u64 FreqHz);
int XAVBuf_SetAudioClock(u64 FreqHz);
#endif /* XAVBUF_CLK_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_mmio_access.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
#include "pm_master.h"
#include "pm_mmio_access.h"
#include "crl_apb.h"
#include "crf_apb.h"
#include "pmu_iomodule.h"
#include "afi.h"
#include "pmu_global.h"
#include "csu.h"
#include "csudma.h"
#include "rsa.h"
#include "rsa_core.h"
#define WRITE_PERM_SHIFT 16U
#define MMIO_ACCESS_RO(m) (m)
#define MMIO_ACCESS_RW(m) ((m) | ((m) << WRITE_PERM_SHIFT))
#define MMIO_ACCESS_WO(m) ((m) << WRITE_PERM_SHIFT)
enum mmio_access_type {
MMIO_ACCESS_TYPE_READ,
MMIO_ACCESS_TYPE_WRITE,
};
/**
* PmAccessRegion - Structure containing information about memory access
permissions
* @startAddr Starting address of the memory region
* @endAddr Ending address of the memory region
* @access Access control bitmask (1 bit per master, see 'pmAllMasters')
*/
typedef struct PmAccessRegion {
const u32 startAddr;
const u32 endAddr;
const u32 access;
} PmAccessRegion;
static const PmAccessRegion pmAccessTable[] = {
/* Module clock controller full power domain (CRF_APB) */
{
.startAddr = CRF_APB_BASEADDR + 0x20U,
.endAddr = CRF_APB_BASEADDR + 0x63U,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
{
.startAddr = CRF_APB_BASEADDR + 0x70U,
.endAddr = CRF_APB_BASEADDR + 0x7bU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
{
.startAddr = CRF_APB_BASEADDR + 0x84U,
.endAddr = CRF_APB_BASEADDR + 0xbfU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* Module clock controller low power domain (CRL_APB) */
{
.startAddr = CRL_APB_BASEADDR + 0x20U,
.endAddr = CRL_APB_BASEADDR + 0x73U,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
{
.startAddr = CRL_APB_BASEADDR + 0x7CU,
.endAddr = CRL_APB_BASEADDR + 0x8CU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
{
.startAddr = CRL_APB_BASEADDR + 0xa4U,
.endAddr = CRL_APB_BASEADDR + 0xa7U,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
{
.startAddr = CRL_APB_BASEADDR + 0xb4U,
.endAddr = CRL_APB_BASEADDR + 0x12bU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU's global Power Status register*/
{
.startAddr = PMU_GLOBAL_PWR_STATE,
.endAddr = PMU_GLOBAL_PWR_STATE,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* PMU's global gen storage */
{
.startAddr = PMU_GLOBAL_GLOBAL_GEN_STORAGE0,
.endAddr = PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* IOU SLCR Registers required for Linux */
{
.startAddr = IOU_SLCR_BASE,
.endAddr = IOU_SLCR_BASE + 0x2FFU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
{
.startAddr = IOU_SLCR_BASE + 0x304U,
.endAddr = IOU_SLCR_BASE + 0x524U,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* RO access to CRL_APB required for Linux CCF */
{
.startAddr = CRL_APB_BASEADDR,
.endAddr = CRL_APB_BASEADDR + 0x288U,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RO access to CRF_APB required for Linux CCF */
{
.startAddr = CRF_APB_BASEADDR,
.endAddr = CRF_APB_BASEADDR + 0x108U,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* Boot pin control register */
{
.startAddr = CRL_APB_BASEADDR + 0x250U,
.endAddr = CRL_APB_BASEADDR + 0x250U,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* FPD Lock status register */
{
.startAddr = PMU_LOCAL_DOMAIN_ISO_CNTRL,
.endAddr = PMU_LOCAL_DOMAIN_ISO_CNTRL,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
#ifdef XPAR_VCU_0_BASEADDR
/* VCU SLCR register */
{
.startAddr = XPAR_VCU_0_BASEADDR + 0x40024U,
.endAddr = XPAR_VCU_0_BASEADDR + 0x40060U,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
#endif
/* Software controlled FPD resets register */
{
.startAddr = CRF_APB_BASEADDR + 0x100U,
.endAddr = CRF_APB_BASEADDR + 0x100U,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* Software controlled LPD resets register */
{
.startAddr = CRL_APB_BASEADDR + 0x23cU,
.endAddr = CRL_APB_BASEADDR +0x23cU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* FPD_SLCR AFI_FS Register */
{
.startAddr = FPD_SLCR_AFI_FS_REG,
.endAddr = FPD_SLCR_AFI_FS_REG,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* LPD SLCR AFI_FS Register */
{
.startAddr = LPD_SLCR_AFI_FS,
.endAddr = LPD_SLCR_AFI_FS,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* AFI FM 0 Registers */
{
.startAddr = AFI_FM0_BASEADDR,
.endAddr = AFI_FM0_BASEADDR + 0xF0CU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* AFI FM 1 Registers */
{
.startAddr = AFI_FM1_BASEADDR,
.endAddr = AFI_FM1_BASEADDR + 0xF0CU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* AFI FM 2 Registers */
{
.startAddr = AFI_FM2_BASEADDR,
.endAddr = AFI_FM2_BASEADDR + 0xF0CU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* AFI FM 3 Registers */
{
.startAddr = AFI_FM3_BASEADDR,
.endAddr = AFI_FM3_BASEADDR + 0xF0CU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* AFI FM 4 Registers */
{
.startAddr = AFI_FM4_BASEADDR,
.endAddr = AFI_FM4_BASEADDR + 0xF0CU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* AFI FM 5 Registers */
{
.startAddr = AFI_FM5_BASEADDR,
.endAddr = AFI_FM5_BASEADDR + 0xF0CU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* AFI FM 6 Registers */
{
.startAddr = AFI_FM6_BASEADDR,
.endAddr = AFI_FM6_BASEADDR + 0xF0CU,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK),
},
/* CSU Status register */
{
.startAddr = CSU_BASEADDR,
.endAddr = CSU_BASEADDR,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU multi-boot register*/
{
.startAddr = CSU_MULTI_BOOT,
.endAddr = CSU_MULTI_BOOT,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU tamper-trig register */
{
.startAddr = CSU_TAMPER_TRIG,
.endAddr = CSU_TAMPER_TRIG,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU ft-status register*/
{
.startAddr = CSU_FT_STATUS,
.endAddr = CSU_FT_STATUS,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU jtag-chain-status register*/
{
.startAddr = CSU_JTAG_CHAIN_STATUS,
.endAddr = CSU_JTAG_CHAIN_STATUS,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU Device IDCODE and Version Registers */
{
.startAddr = CSU_IDCODE,
.endAddr = CSU_VERSION,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU rom-digest registers */
{
.startAddr = CSU_ROM_DIGEST_0,
.endAddr = CSU_ROM_DIGEST_11,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU aes-status register */
{
.startAddr = CSU_AES_STATUS,
.endAddr = CSU_AES_STATUS,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU pcap-status register */
{
.startAddr = CSU_PCAP_STATUS_REG,
.endAddr = CSU_PCAP_STATUS_REG,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU_GLOBAL registers*/
{
.startAddr = PMU_GLOBAL_GLOBAL_CNTRL,
.endAddr = PMU_GLOBAL_SAFETY_CHK,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Golbal_Req_Iso_Status register */
{
.startAddr = PMU_GLOBAL_REQ_ISO_STATUS,
.endAddr = PMU_GLOBAL_REQ_ISO_STATUS,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Req_SwRst_Status register */
{
.startAddr = PMU_GLOBAL_REQ_SWRST_STATUS,
.endAddr = PMU_GLOBAL_REQ_SWRST_STATUS,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Csu_br_error register */
{
.startAddr = PMU_GLOBAL_CSU_BR_ERROR,
.endAddr = PMU_GLOBAL_CSU_BR_ERROR,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Safety_Chk register */
{
.startAddr = PMU_GLOBAL_SAFETY_CHK,
.endAddr = PMU_GLOBAL_SAFETY_CHK,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
#ifdef SECURE_ACCESS
/*CSU ctrl, sss-cfg, dma-reset registers */
{
.startAddr = CSU_CTRL,
.endAddr = CSU_DMA_RESET,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU isr register*/
{
.startAddr = CSU_ISR,
.endAddr = CSU_ISR,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU imr register*/
{
.startAddr = CSU_IMR,
.endAddr = CSU_IMR,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU ier register*/
{
.startAddr = CSU_IER,
.endAddr = CSU_JTAG_CHAIN_CFG,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU idr register*/
{
.startAddr = CSU_IDR,
.endAddr = CSU_IDR,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU jtag register*/
{
.startAddr = CSU_JTAG_SEC,
.endAddr = CSU_JTAG_DAP_CFG,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU AES registers*/
{
.startAddr = CSU_AES_KEY_SRC,
.endAddr = CSU_AES_KUP_WR,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU AES KUP registers*/
{
.startAddr = CSU_AES_KUP_0,
.endAddr = CSU_AES_KUP_7,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU IV registers*/
{
.startAddr = CSU_AES_IV_0,
.endAddr = CSU_AES_IV_3,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU sha_start register*/
{
.startAddr = CSU_SHA_START,
.endAddr = CSU_SHA_START,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU sha_reset register*/
{
.startAddr = CSU_SHA_RESET,
.endAddr = CSU_SHA_RESET,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU Sha registers */
{
.startAddr = CSU_SHA_DONE,
.endAddr = CSU_SHA_DIGEST_11,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* CSU pcap registers*/
{
.startAddr = CSU_PCAP_PROG_REG,
.endAddr = CSU_PCAP_RESET_REG,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/*CSU tamper-status register */
{
.startAddr = CSU_TAMPER_STATUS,
.endAddr = CSU_TAMPER_STATUS,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/*CSU csu-tamper_0-12 registers */
{
.startAddr = CSU_TAMPER_0,
.endAddr = CSU_TAMPER_12,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/*CSUDMA registers*/
{
.startAddr = CSUDMA_BASEADDR,
.endAddr = CSUDMA_CSUDMA_FUTURE_ECO,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA wr_data registers */
{
.startAddr = RSA_BASEADDR,
.endAddr = RSA_WR_ADDR,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA rd_data registers */
{
.startAddr = RSA_RD_DATA_0,
.endAddr = RSA_RD_DATA_5,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA rd_address registers */
{
.startAddr = RSA_RD_ADDR,
.endAddr = RSA_RD_ADDR,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA cfg and isr registers */
{
.startAddr = RSA_RSA_CFG,
.endAddr = RSA_RSA_ISR,
.access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA imr registers */
{
.startAddr = RSA_RSA_IMR,
.endAddr = RSA_RSA_IMR,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA ier and idr registers */
{
.startAddr = RSA_RSA_IER,
.endAddr = RSA_RSA_IDR,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA_CORE wr_data and wr_address registers */
{
.startAddr = RSA_CORE_BASEADDR,
.endAddr = RSA_CORE_RSA_WR_ADDR,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA_CORE rd_data registers */
{
.startAddr = RSA_CORE_RSA_RD_DATA,
.endAddr = RSA_CORE_RSA_RD_DATA,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA_CORE rd_addr and ctrl registers */
{
.startAddr = RSA_CORE_RSA_RD_ADDR,
.endAddr = RSA_CORE_CTRL,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA_CORE status registers */
{
.startAddr = RSA_CORE_STATUS,
.endAddr = RSA_CORE_STATUS,
.access = MMIO_ACCESS_RO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* RSA_CORE minv registers */
{
.startAddr = RSA_CORE_MINV0,
.endAddr = RSA_CORE_MINV3,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU global ctrl, ps-ctrl, apu_power_status_init,
* mem_ctrl registers and addr_error_status registers
*/
{
.startAddr = PMU_GLOBAL_GLOBAL_CNTRL,
.endAddr = PMU_GLOBAL_ADDR_ERROR_STATUS,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU addr_err_int_en and addr_err_int_dis registers */
{
.startAddr = PMU_GLOBAL_ADDR_ERROR_INT_EN,
.endAddr = PMU_GLOBAL_ADDR_ERROR_INT_DIS,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU DDR_CTRL register */
{
.startAddr = PMU_GLOBAL_DDR_CNTRL,
.endAddr = PMU_GLOBAL_DDR_CNTRL,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU RAM_RET_CTRL registers */
{
.startAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.endAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Req_Pwrup_Status registers */
{
.startAddr = PMU_GLOBAL_REQ_PWRUP_STATUS,
.endAddr = PMU_GLOBAL_REQ_PWRUP_STATUS,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Req_Pwrup_Int_En ,Req_Pwrup_Int_Dis and
* Req_Pwrup_Int_Trig registers*/
{
.startAddr = PMU_GLOBAL_REQ_PWRUP_INT_EN,
.endAddr = PMU_GLOBAL_REQ_PWRUP_TRIG,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Req_Pwrdw_status registers*/
{
.startAddr = PMU_GLOBAL_REQ_PWRDWN_STATUS,
.endAddr = PMU_GLOBAL_REQ_PWRDWN_STATUS,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Req_Pwrdwn_Int_En , Req_PwrDwn_Int_Dis and
* Req_PwrDwn_Int_Trig registers
*/
{
.startAddr = PMU_GLOBAL_REQ_PWRDWN_INT_EN,
.endAddr = PMU_GLOBAL_REQ_PWRDWN_TRIG,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Req_Iso_Int_En, Req_Iso_Int_Dis and
* Req_Iso_Int_Trig registers */
{
.startAddr = PMU_GLOBAL_REQ_ISO_INT_EN,
.endAddr = PMU_GLOBAL_REQ_ISO_TRIG,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Req_SwRst_Int_En, Req_SwRst_Int_Dis and
* Req_SwRst_Int_Trig registers */
{
.startAddr = PMU_GLOBAL_REQ_SWRST_INT_EN,
.endAddr = PMU_GLOBAL_REQ_SWRST_TRIG,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Error_Status_1 register */
{
.startAddr = PMU_GLOBAL_ERROR_STATUS_1,
.endAddr = PMU_GLOBAL_ERROR_STATUS_1 ,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Error_Int_En_1 , Error_Int_Dis_1 and
* Error_Status_2 registers */
{
.startAddr = PMU_GLOBAL_ERROR_INT_EN_1,
.endAddr = PMU_GLOBAL_ERROR_STATUS_2,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Error_Int_En_2 and Error_Int_Dis_2 registers */
{
.startAddr = PMU_GLOBAL_ERROR_INT_EN_2,
.endAddr = PMU_GLOBAL_ERROR_INT_DIS_2,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Error_Por_En_1 and Error_Por_Dis_1 registers */
{
.startAddr = PMU_GLOBAL_ERROR_POR_EN_1,
.endAddr = PMU_GLOBAL_ERROR_POR_DIS_1 ,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Error_Por_En_2 and Error_Por_Dis_2 registers */
{
.startAddr = PMU_GLOBAL_ERROR_POR_EN_2,
.endAddr = PMU_GLOBAL_ERROR_POR_DIS_2 ,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Error_Srst_En_1 and Error_Srst_Dis_1 registers */
{
.startAddr = PMU_GLOBAL_ERROR_SRST_EN_1,
.endAddr = PMU_GLOBAL_ERROR_SRST_DIS_1,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Error_Srst_En_2 and Error_Srst_Dis_2 registers */
{
.startAddr = PMU_GLOBAL_ERROR_SRST_EN_2,
.endAddr = PMU_GLOBAL_ERROR_SRST_DIS_2,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Error_Sig_En_1 and Error_Sig_Dis_1 registers */
{
.startAddr = PMU_GLOBAL_ERROR_SIG_EN_1,
.endAddr = PMU_GLOBAL_ERROR_SIG_DIS_1,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Error_Sig_En_2 and Error_Sig_Dis_2 registers */
{
.startAddr = PMU_GLOBAL_ERROR_SIG_EN_2,
.endAddr = PMU_GLOBAL_ERROR_SIG_DIS_2,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Error_En_1 and Error_En_2 registers */
{
.startAddr = PMU_GLOBAL_ERROR_EN_1,
.endAddr = PMU_GLOBAL_ERROR_EN_2,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Aib_Ctrl register */
{
.startAddr = PMU_GLOBAL_AIB_CNTRL,
.endAddr = PMU_GLOBAL_AIB_CNTRL,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Global_Reset register */
{
.startAddr = PMU_GLOBAL_GLOBAL_RESET,
.endAddr = PMU_GLOBAL_GLOBAL_RESET,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Safety_Gate register */
{
.startAddr = PMU_GLOBAL_SAFETY_GATE,
.endAddr = PMU_GLOBAL_SAFETY_GATE,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
/* PMU Mbist_Reset, Mbist_Pg_En and Mbist_Setup registers */
{
.startAddr = PMU_GLOBAL_MBIST_RST,
.endAddr = PMU_GLOBAL_MBIST_SETUP,
.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
IPI_PMU_0_IER_RPU_0_MASK |
IPI_PMU_0_IER_RPU_1_MASK),
},
#endif
};
/**
* PmGetMmioAccess() - Retrieve access info for a particular address
* @master Master who requests access permission
* @address Address to write/read
* @type Type of access (read or write)
*
* @return Return true if master's IPI bit was present in the access region
* table
*/
static bool PmGetMmioAccess(const PmMaster *const master, const u32 address,
enum mmio_access_type type)
{
u32 i;
bool permission = false;
if (NULL == master) {
goto done;
}
for (i = 0U; i < ARRAY_SIZE(pmAccessTable); i++) {
if ((address >= pmAccessTable[i].startAddr) &&
(address <= pmAccessTable[i].endAddr)) {
u32 mask = master->ipiMask;
if (MMIO_ACCESS_TYPE_WRITE == type) {
mask <<= WRITE_PERM_SHIFT;
}
permission = !!(pmAccessTable[i].access & mask);
if (permission) {
break;
}
}
}
done:
return permission;
}
bool PmGetMmioAccessRead(const PmMaster *const master, const u32 address)
{
return PmGetMmioAccess(master, address, MMIO_ACCESS_TYPE_READ);
}
bool PmGetMmioAccessWrite(const PmMaster *const master, const u32 address)
{
return PmGetMmioAccess(master, address, MMIO_ACCESS_TYPE_WRITE);
}
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/xsecure_rsa_core.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_rsa_core.h
* This file contains zynqmp specific RSA core APIs.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.0 vns 03/09/19 Initial release
* 4.1 kpt 01/07/20 Added Macros for all the Magic Numbers
* in xsecure_rsa_core.c
* 4.2 kpt 03/26/20 Added Error code XSECURE_RSA_ZEROIZE_ERROR
*
* </pre>
*
******************************************************************************/
#ifndef XSECURE_RSA_CORE_H
#define XSECURE_RSA_CORE_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xsecure_utils.h"
/************************** Constant Definitions ****************************/
#define XSECURE_RSA_FAILED 0x1U /**< RSA Failed Error Code */
#define XSECURE_RSA_DATA_VALUE_ERROR 0x2U /**< for RSA private decryption
* data should be lesser than
* modulus */
#define XSECURE_RSA_ZEROIZE_ERROR 0x80U /**< for RSA zeroization Error*/
#define XSECURE_HASH_TYPE_SHA3 (48U) /**< SHA-3 hash size */
#define XSECURE_HASH_TYPE_SHA2 (32U) /**< SHA-2 hash size */
#define XSECURE_FSBL_SIG_SIZE (512U)/**< FSBL signature size */
#define XSECURE_RSA_MAX_BUFF (6U) /**< RSA RAM Write Buffers */
#define XSECURE_RSA_MAX_RD_WR_CNT (22U) /**< No of writes or reads to RSA RAM Buffers */
#define XSECURE_RSA_BYTE_MASK (0XFFU) /**< RSA BYTE MASK */
#define XSECURE_RSA_BYTE_SHIFT (8U) /**< RSA BYTE */
#define XSECURE_RSA_HWORD_SHIFT (16U) /**< RSA HWORD */
#define XSECURE_RSA_SWORD_SHIFT (24U) /**< RSA SWORD */
/* Key size in bytes */
#define XSECURE_RSA_512_KEY_SIZE (512U/8U) /**< RSA 512 key size */
#define XSECURE_RSA_576_KEY_SIZE (576U/8U) /**< RSA 576 key size */
#define XSECURE_RSA_704_KEY_SIZE (704U/8U) /**< RSA 704 key size */
#define XSECURE_RSA_768_KEY_SIZE (768U/8U) /**< RSA 768 key size */
#define XSECURE_RSA_992_KEY_SIZE (992U/8U) /**< RSA 992 key size */
#define XSECURE_RSA_1024_KEY_SIZE (1024U/8U) /**< RSA 1024 key size */
#define XSECURE_RSA_1152_KEY_SIZE (1152U/8U) /**< RSA 1152 key size */
#define XSECURE_RSA_1408_KEY_SIZE (1408U/8U) /**< RSA 1408 key size */
#define XSECURE_RSA_1536_KEY_SIZE (1536U/8U) /**< RSA 1536 key size */
#define XSECURE_RSA_1984_KEY_SIZE (1984U/8U) /**< RSA 1984 key size */
#define XSECURE_RSA_2048_KEY_SIZE (2048U/8U) /**< RSA 2048 key size */
#define XSECURE_RSA_3072_KEY_SIZE (3072U/8U) /**< RSA 3072 key size */
#define XSECURE_RSA_4096_KEY_SIZE (4096U/8U) /**< RSA 4096 key size */
/* Key size in words */
#define XSECURE_RSA_512_SIZE_WORDS (16) /**< RSA 512 Size in words */
#define XSECURE_RSA_576_SIZE_WORDS (18) /**< RSA 576 Size in words */
#define XSECURE_RSA_704_SIZE_WORDS (22) /**< RSA 704 Size in words */
#define XSECURE_RSA_768_SIZE_WORDS (24) /**< RSA 768 Size in words */
#define XSECURE_RSA_992_SIZE_WORDS (31) /**< RSA 992 Size in words */
#define XSECURE_RSA_1024_SIZE_WORDS (32) /**< RSA 1024 Size in words */
#define XSECURE_RSA_1152_SIZE_WORDS (36) /**< RSA 1152 Size in words */
#define XSECURE_RSA_1408_SIZE_WORDS (44) /**< RSA 1408 Size in words */
#define XSECURE_RSA_1536_SIZE_WORDS (48) /**< RSA 1536 Size in words */
#define XSECURE_RSA_1984_SIZE_WORDS (62) /**< RSA 1984 Size in words */
#define XSECURE_RSA_2048_SIZE_WORDS (64) /**< RSA 2048 Size in words */
#define XSECURE_RSA_3072_SIZE_WORDS (96) /**< RSA 3072 Size in words */
#define XSECURE_RSA_4096_SIZE_WORDS (128U) /**< RSA 4096 Size in words */
#define XSECURE_CSU_RSA_RAM_EXPO (0U) /**< bit for RSA RAM Exponent */
#define XSECURE_CSU_RSA_RAM_MOD (1U) /**< bit for RSA RAM modulus */
#define XSECURE_CSU_RSA_RAM_DIGEST (2U) /**< bit for RSA RAM Digest */
#define XSECURE_CSU_RSA_RAM_SPAD (3U) /**< bit for RSA RAM SPAD */
#define XSECURE_CSU_RSA_RAM_RES_Y (4U) /**< bit for RSA RAM Result(Y) */
#define XSECURE_CSU_RSA_RAM_RES_Q (5U) /**< bit for RSA RAM Result(Q) */
#define XSECURE_RSA_SIGN_ENC 0U /**< RSA encryption flag */
#define XSECURE_RSA_SIGN_DEC 1U /**< RSA decryption flag */
/** @name Control Register
*
* The Control register (CR) controls the major functions of the device.
* It is used to set the function to be implemented by the RSA device in
* the next iteration.
*
* Control Register Bit Definition
*/
#define XSECURE_CSU_RSA_CONTROL_512 (0x00U) /**< RSA 512 Length Code */
#define XSECURE_CSU_RSA_CONTROL_576 (0x10U) /**< RSA 576 Length Code */
#define XSECURE_CSU_RSA_CONTROL_704 (0x20U) /**< RSA 704 Length Code */
#define XSECURE_CSU_RSA_CONTROL_768 (0x30U) /**< RSA 768 Length Code */
#define XSECURE_CSU_RSA_CONTROL_992 (0x40U) /**< RSA 992 Length Code */
#define XSECURE_CSU_RSA_CONTROL_1024 (0x50U) /**< RSA 1024 Length Code */
#define XSECURE_CSU_RSA_CONTROL_1152 (0x60U) /**< RSA 1152 Length Code */
#define XSECURE_CSU_RSA_CONTROL_1408 (0x70U) /**< RSA 1408 Length Code */
#define XSECURE_CSU_RSA_CONTROL_1536 (0x80U) /**< RSA 1536 Length Code */
#define XSECURE_CSU_RSA_CONTROL_1984 (0x90U) /**< RSA 1984 Length Code */
#define XSECURE_CSU_RSA_CONTROL_2048 (0xA0U) /**< RSA 2048 Length Code */
#define XSECURE_CSU_RSA_CONTROL_3072 (0xB0U) /**< RSA 3072 Length Code */
#define XSECURE_CSU_RSA_CONTROL_4096 (0xC0U) /**< RSA 4096 Length Code */
#define XSECURE_CSU_RSA_CONTROL_DCA (0x08U) /**< Abort Operation */
#define XSECURE_CSU_RSA_CONTROL_NOP (0x00U) /**< No Operation */
#define XSECURE_CSU_RSA_CONTROL_EXP (0x01U) /**< Exponentiation Opcode */
#define XSECURE_CSU_RSA_CONTROL_EXP_PRE (0x05U) /**< Expo. using R*R mod M */
#define XSECURE_CSU_RSA_CONTROL_MASK (XSECURE_CSU_RSA_CONTROL_4096 + \
XSECURE_CSU_RSA_CONTROL_EXP_PRE)
/** @name RSA status Register
*
* The Status Register(SR) indicates the current state of RSA device.
*
* Status Register Bit Definition
*/
#define XSECURE_CSU_RSA_STATUS_DONE (0x1U) /**< Operation Done */
#define XSECURE_CSU_RSA_STATUS_BUSY (0x2U) /**< RSA busy */
#define XSECURE_CSU_RSA_STATUS_ERROR (0x4U) /**< Error */
#define XSECURE_CSU_RSA_STATUS_PROG_CNT (0xF8U) /**< Progress Counter */
/* @}*/
typedef enum {
XSECURE_RSA_UNINITIALIZED = 0,
XSECURE_RSA_INITIALIZED
} XSecure_RsaState;
/***************************** Type Definitions ******************************/
/**
* The RSA driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
u32 BaseAddress; /**< Device Base Address */
u8* Mod; /**< Modulus */
u8* ModExt; /**< Precalc. R sq. mod N */
u8* ModExpo; /**< Exponent */
u8 EncDec; /**< 0 for signature verification and 1 for generation */
u32 SizeInWords;/** RSA key size in words */
XSecure_RsaState RsaState;
} XSecure_Rsa;
/***************************** Function Prototypes ***************************/
/* ZynqMP specific RSA core initialization function */
u32 XSecure_RsaCfgInitialize(XSecure_Rsa *InstancePtr);
/* ZynqMP specific RSA core encryption/decryption function */
u32 XSecure_RsaOperation(XSecure_Rsa *InstancePtr, u8 *Input,
u8 *Result, u8 EncDecFlag, u32 Size);
/* ZynqMP specific function for selection of PKCS padding */
u8* XSecure_RsaGetTPadding();
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_RSA_CORE_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_reset.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_RESET_H_
#define XPM_RESET_H_
#include "xpm_node.h"
#include "xpm_common.h"
#include "xpm_subsystem.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MAX_RESET_PARENTS (3U)
/* All reset types */
typedef enum {
XPM_RSTTYPE_POR,
XPM_RSTTYPE_SYS,
XPM_RSTTYPE_PERIPH,
XPM_RSTTYPE_DBG,
}XPm_ResetType;
/* All reset Ops types */
typedef enum {
XPM_RSTOPS_GENRERIC=1,
XPM_RSTOPS_CUSTOM,
XPM_RSTOPS_MAX,
}XPm_ResetOpsType;
typedef enum XPmResetActions XPm_ResetActions;
typedef struct XPm_ResetNode XPm_ResetNode;
typedef struct XPm_ResetHandle XPm_ResetHandle;
/**
* xPmResetOps - Reset operations
* @SetState Assert or release reset line
* @GetState Get current status of reset line
*/
typedef struct XPmResetOps {
XStatus (*const SetState)(XPm_ResetNode *Rst, const u32 Action);
u32 (*const GetState)(XPm_ResetNode *Rst);
} XPm_ResetOps;
/**
* XPm_ResetHandle - This models reset/device pair.
*/
struct XPm_ResetHandle {
XPm_ResetNode *Reset; /**< Reset used by device */
struct XPm_DeviceNode *Device; /**< Device which uses the reset */
XPm_ResetHandle *NextReset; /**< Next handle of same device */
XPm_ResetHandle *NextDevice; /**< Next handle of same reset */
};
/**
* The reset class. This is the base class for all the reset nodes.
*/
struct XPm_ResetNode {
XPm_Node Node;
u16 Parents[MAX_RESET_PARENTS]; /**< List of Parent Reset Index */
uint8_t Shift;
uint8_t Width;
XPm_ResetOps *Ops;
XPm_ResetHandle *RstHandles; /**< Pointer to the reset/device pairs */
};
#define MAX_RESETS XPM_NODEIDX_RST_MAX
#define XPM_RST_STATE_DEASSERTED 0U
#define XPM_RST_STATE_ASSERTED 1U
/************************** Function Prototypes ******************************/
XStatus XPmReset_AddNode(u32 Id, u32 ControlReg, u8 Shift, u8 Width, u8 ResetType, u8 NumParents, u32* Parents);
XPm_ResetNode* XPmReset_GetById(u32 ResetId);
XStatus XPmReset_AssertbyId(u32 ResetId, const u32 Action);
int XPmReset_CheckPermissions(XPm_Subsystem *Subsystem, u32 ResetId);
int XPmReset_SystemReset(void);
#ifdef __cplusplus
}
#endif
#endif /* XPM_RESET_H_ */
<file_sep>/python_drivers/pulse_gen_test.py
# -*- coding: utf-8 -*-
"""
Created on Fri Jul 10 17:01:34 2020
@author: tianlab01
"""
import pulse_gen
import time
pg = pulse_gen.pulse_gen("COM4")
#minbias 3.94V
#try pinging the board
if(pg.ping_board()):
print("Failed to connect to board!")
else:
print("Connection to board is up!")
#Set the period to something reasonable
pg.set_period(200)
#pg.set_amplitude(0x1FFF)
pg.set_amplitude(0x7FFF)
pg.set_pulse_len(16)
#List of values to send
# for j in range(0, 20):
# for i in range(0,15):
# pg.load_pulse(j, i)
#Send the pulses with 10 leading ticks, 5 dead ticks
#pg.sync_and_stream(40, 20)
print("Blasting...")
# while(1):
# try:
# pg.toggle_phase_meas(65535)
# #time.sleep(0.5)
# except:
# print("exiting...")
# break
#res = pg.get_busy()
#print("Busy w/o phase meas was: " + str(res))
#pg.toggle_phase_meas(65535)
pg.phase_meas_on()
#res = pg.get_busy()
#print("Busy w/ phase meas was: " + str(res))
time.sleep(5)
import pdb; pdb.set_trace()
pg.phase_meas_off()
pg.close_board()<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pslpdomain.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PSLPDOMAIN_H_
#define XPM_PSLPDOMAIN_H_
#include "xpm_powerdomain.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* PMC_ANALOG Base Address
*/
#define PMC_ANALOG_BASEADDR 0XF1160000U
/**
* Register: PMC_ANALOG_OD_MBIST_RST
*/
#define PMC_ANALOG_OD_MBIST_RST ( ( PMC_ANALOG_BASEADDR ) + 0X00020100U )
#define PMC_ANALOG_OD_MBIST_RST_LPD_IOU_MASK 0X00000040U
#define PMC_ANALOG_OD_MBIST_RST_LPD_RPU_MASK 0X00000020U
#define PMC_ANALOG_OD_MBIST_RST_LPD_MASK 0X00000010U
/**
* Register: PMC_ANALOG_OD_MBIST_PG_EN
*/
#define PMC_ANALOG_OD_MBIST_PG_EN ( ( PMC_ANALOG_BASEADDR ) + 0X00020104U )
#define PMC_ANALOG_OD_MBIST_PG_EN_LPD_IOU_MASK 0X00000040U
#define PMC_ANALOG_OD_MBIST_PG_EN_LPD_RPU_MASK 0X00000020U
#define PMC_ANALOG_OD_MBIST_PG_EN_LPD_MASK 0X00000010U
/**
* Register: PMC_ANALOG_OD_MBIST_SETUP
*/
#define PMC_ANALOG_OD_MBIST_SETUP ( ( PMC_ANALOG_BASEADDR ) + 0X00020108U )
#define PMC_ANALOG_OD_MBIST_SETUP_LPD_IOU_MASK 0X00000040U
#define PMC_ANALOG_OD_MBIST_SETUP_LPD_RPU_MASK 0X00000020U
#define PMC_ANALOG_OD_MBIST_SETUP_LPD_MASK 0X00000010U
/**
* Register: PMC_ANALOG_OD_MBIST_DONE
*/
#define PMC_ANALOG_OD_MBIST_DONE ( ( PMC_ANALOG_BASEADDR ) + 0X00020110U )
#define PMC_ANALOG_OD_MBIST_DONE_LPD_IOU_MASK 0X00000040U
#define PMC_ANALOG_OD_MBIST_DONE_LPD_RPU_MASK 0X00000020U
#define PMC_ANALOG_OD_MBIST_DONE_LPD_MASK 0X00000010U
/**
* Register: PMC_ANALOG_OD_MBIST_GOOD
*/
#define PMC_ANALOG_OD_MBIST_GOOD ( ( PMC_ANALOG_BASEADDR ) + 0X00020114U )
#define PMC_ANALOG_OD_MBIST_GOOD_LPD_IOU_MASK 0X00000040U
#define PMC_ANALOG_OD_MBIST_GOOD_LPD_RPU_MASK 0X00000020U
#define PMC_ANALOG_OD_MBIST_GOOD_LPD_MASK 0X00000010U
/**
* Register: PMC_ANALOG_SCAN_CLEAR_TRIGGER
*/
#define PMC_ANALOG_SCAN_CLEAR_TRIGGER ( ( PMC_ANALOG_BASEADDR ) + 0X00020120U )
#define PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_IOU_MASK 0X00000040U
#define PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_RPU_MASK 0X00000020U
#define PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_MASK 0X00000010U
#define PMC_ANALOG_SCAN_CLEAR_TRIGGER_NOC_MASK 0X00000100U
/**
* Register: PMC_ANALOG_SCAN_CLEAR_DONE
*/
#define PMC_ANALOG_SCAN_CLEAR_DONE ( ( PMC_ANALOG_BASEADDR ) + 0X00020128U )
#define PMC_ANALOG_SCAN_CLEAR_DONE_LPD_IOU_MASK 0X00000040U
#define PMC_ANALOG_SCAN_CLEAR_DONE_LPD_RPU_MASK 0X00000020U
#define PMC_ANALOG_SCAN_CLEAR_DONE_LPD_MASK 0X00000010U
/**
* Register: PMC_ANALOG_SCAN_CLEAR_PASS
*/
#define PMC_ANALOG_SCAN_CLEAR_PASS ( ( PMC_ANALOG_BASEADDR ) + 0X0002012CU )
#define PMC_ANALOG_SCAN_CLEAR_PASS_LPD_IOU_MASK 0X00000040U
#define PMC_ANALOG_SCAN_CLEAR_PASS_LPD_RPU_MASK 0X00000020U
#define PMC_ANALOG_SCAN_CLEAR_PASS_LPD_MASK 0X00000010U
/**
* Register: PMC_ANALOG_LBIST_ENABLE
*/
#define PMC_ANALOG_LBIST_ENABLE ( ( PMC_ANALOG_BASEADDR ) + 0X00020200U )
#define PMC_ANALOG_LBIST_ENABLE_LPD_RPU_MASK 0X00000002U
#define PMC_ANALOG_LBIST_ENABLE_LPD_MASK 0X00000001U
/**
* Register: PMC_ANALOG_LBIST_RST_N
*/
#define PMC_ANALOG_LBIST_RST_N ( ( PMC_ANALOG_BASEADDR ) + 0X00020204U )
#define PMC_ANALOG_LBIST_RST_N_LPD_RPU_MASK 0X00000002U
#define PMC_ANALOG_LBIST_RST_N_LPD_MASK 0X00000001U
/**
* Register: PMC_ANALOG_LBIST_ISOLATION_EN
*/
#define PMC_ANALOG_LBIST_ISOLATION_EN ( ( PMC_ANALOG_BASEADDR ) + 0X00020208U )
#define PMC_ANALOG_LBIST_ISOLATION_EN_LPD_RPU_MASK 0X00000002U
#define PMC_ANALOG_LBIST_ISOLATION_EN_LPD_MASK 0X00000001U
/**
* Register: PMC_ANALOG_LBIST_DONE
*/
#define PMC_ANALOG_LBIST_DONE ( ( PMC_ANALOG_BASEADDR ) + 0X00020210U )
#define PMC_ANALOG_LBIST_DONE_LPD_RPU_MASK 0X00000002U
#define PMC_ANALOG_LBIST_DONE_LPD_MASK 0X00000001U
#define LPD_BISR_DONE BIT(0)
#define LPD_BISR_DATA_COPIED BIT(1)
typedef struct XPm_PsLpDomain XPm_PsLpDomain;
/**
* The PS low power domain node class.
*/
struct XPm_PsLpDomain {
XPm_PowerDomain Domain; /**< Power domain node base class */
u32 LpdIouSlcrBaseAddr; /**< LPD IOU SLCR Base address */
u32 LpdSlcrBaseAddr; /**< LPD SLCR Base address */
u32 LpdSlcrSecureBaseAddr; /**< LPD SLCR Secure base address */
u8 LpdBisrFlags;
};
/************************** Function Prototypes ******************************/
XStatus XPmPsLpDomain_Init(XPm_PsLpDomain *PsLpd, u32 Id, u32 BaseAddress,
XPm_Power *Parent, u32 *OtherBaseAddresses,
u32 OtherBaseAddressesCnt);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_PSLPDOMAIN_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/usbpsu_v1_7/src/xusbpsu_event.c
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_event.c
* @addtogroup usbpsu_v1_7
* @{
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 pm 03/03/20 First release
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xusbpsu_local.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
* Endpoint event handler.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is endpoint Event occurred in the core.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_EpEvent(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event)
{
struct XUsbPsu_Ep *Ept;
u32 Epnum;
Epnum = Event->Epnumber;
Ept = &InstancePtr->eps[Epnum];
if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
return;
}
if ((Epnum == (u32)0U) || (Epnum == (u32)1U)) {
XUsbPsu_Ep0Intr(InstancePtr, Event);
return;
}
/* Handle other end point events */
switch (Event->Endpoint_Event) {
case XUSBPSU_DEPEVT_XFERCOMPLETE:
case XUSBPSU_DEPEVT_XFERINPROGRESS:
XUsbPsu_EpXferComplete(InstancePtr, Event);
break;
case XUSBPSU_DEPEVT_XFERNOTREADY:
XUsbPsu_EpXferNotReady(InstancePtr, Event);
break;
default:
/* Made for Misra-C Compliance. */
break;
}
}
/****************************************************************************/
/**
* Device event handler for device specific events.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is the Device Event occurred in core.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_DeviceEvent(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Devt *Event)
{
switch (Event->Type) {
case XUSBPSU_DEVICE_EVENT_DISCONNECT:
XUsbPsu_DisconnectIntr(InstancePtr);
break;
case XUSBPSU_DEVICE_EVENT_RESET:
XUsbPsu_ResetIntr(InstancePtr);
break;
case XUSBPSU_DEVICE_EVENT_CONNECT_DONE:
XUsbPsu_ConnDoneIntr(InstancePtr);
break;
case XUSBPSU_DEVICE_EVENT_WAKEUP:
break;
case XUSBPSU_DEVICE_EVENT_HIBER_REQ:
#ifdef XUSBPSU_HIBERNATION_ENABLE
if (InstancePtr->HasHibernation == TRUE) {
XUsbPsu_HibernationIntr(InstancePtr);
}
#endif
break;
case XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE:
XUsbPsu_LinkStsChangeIntr(InstancePtr,
Event->Event_Info);
break;
case XUSBPSU_DEVICE_EVENT_EOPF:
break;
case XUSBPSU_DEVICE_EVENT_SOF:
break;
case XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR:
break;
case XUSBPSU_DEVICE_EVENT_CMD_CMPL:
break;
case XUSBPSU_DEVICE_EVENT_OVERFLOW:
break;
default:
/* Made for Misra-C Compliance. */
break;
}
}
/****************************************************************************/
/**
* Processes events in an Event Buffer.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr)
{
struct XUsbPsu_EvtBuffer *Evt;
union XUsbPsu_Event Event = {0U};
u32 RegVal;
Evt = &InstancePtr->Evt;
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr,
(u32)XUSBPSU_EVENT_BUFFERS_SIZE);
}
while (Evt->Count > 0U) {
Event.Raw = *(UINTPTR *)((UINTPTR)Evt->BuffAddr + Evt->Offset);
/*
* Process the event received
*/
XUsbPsu_EventHandler(InstancePtr, &Event);
/* don't process anymore events if core is hibernated */
if (InstancePtr->IsHibernated == TRUE) {
return;
}
Evt->Offset = (Evt->Offset + 4U) % XUSBPSU_EVENT_BUFFERS_SIZE;
Evt->Count -= 4U;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 4U);
}
Evt->Count = 0U;
Evt->Flags &= ~XUSBPSU_EVENT_PENDING;
/* Unmask event interrupt */
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U));
RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U), RegVal);
}
#ifdef XUSBPSU_HIBERNATION_ENABLE
/****************************************************************************/
/**
* Processes link state events for hibernation.
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_HibernationStateIntr(struct XUsbPsu *InstancePtr)
{
u32 RegVal, link_state;
u8 enter_hiber = (u8)0U;
link_state = XUsbPsu_GetLinkState(InstancePtr);
switch (link_state) {
case XUSBPSU_LINK_STATE_RESET:
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
RegVal &= ~XUSBPSU_DCFG_DEVADDR_MASK;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DSTS, RegVal);
if (XUsbPsu_SetLinkState(InstancePtr, XUSBPSU_LINK_STATE_RECOV)
== XST_FAILURE) {
xil_printf("Failed to put link in Recovery\r\n");
return;
}
break;
case XUSBPSU_LINK_STATE_SS_DIS:
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
enter_hiber = (u8)1U;
break;
case XUSBPSU_LINK_STATE_U3:
/* enter hibernation again */
enter_hiber = (u8)1U;
break;
default:
if (XUsbPsu_SetLinkState(InstancePtr, XUSBPSU_LINK_STATE_RECOV)
== XST_FAILURE) {
xil_printf("Failed to put link in Recovery\r\n");
return;
}
break;
};
if (XUsbPsu_RestoreEps(InstancePtr) == XST_FAILURE) {
xil_printf("Failed to restore EPs\r\n");
return;
}
InstancePtr->IsHibernated = 0U;
if (enter_hiber == (u8)1U) {
XUsbPsu_HibernationIntr(InstancePtr);
return;
}
}
#endif /* XUSBPSU_HIBERNATION_ENABLE */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/ddrcpsu_v1_2/src/xddrcpsu.h
/*******************************************************************************
* Copyright (C) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xddcrpsu.h
* @addtogroup ddrcpsu_v1_2
* @{
* @details
*
* The Xilinx DdrcPsu driver. This driver supports the Xilinx ddrcpsu
* IP core.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 ssc 04/28/16 First Release.
* 1.1 adk 04/08/16 Export DDR freq to xparameters.h file.
*
* </pre>
*
*******************************************************************************/
#ifndef XDDRCPS_H_
/* Prevent circular inclusions by using protection macros. */
#define XDDRCPS_H_
/******************************* Include Files ********************************/
#endif /* XDDRCPS_H_ */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_ipi.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_IPI_H_
#define XPM_IPI_H_
#include "xpm_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PAYLOAD_ARG_CNT (8U)
#define RESPONSE_ARG_CNT (8U)
#define PM_IPI_TIMEOUT (~0U)
#ifdef XPAR_XIPIPSU_0_DEVICE_ID
#define PSM_IPI_INT_MASK XPAR_XIPIPS_TARGET_PSV_PSM_0_CH0_MASK
#else
#define PSM_IPI_INT_MASK (0U)
#endif /* XPAR_XIPIPSU_0_DEVICE_ID */
XStatus XPm_IpiSend(u32 IpiMask, u32 *Payload);
XStatus XPm_IpiReadStatus(u32 IpiMask);
/*
* XSDB master IPI-5 mask
*/
#define XSDB_IPI_INT_MASK (0x00000080U)
#ifdef __cplusplus
}
#endif
#endif /* XPM_IPI_H_ */
<file_sep>/c_drivers/drivers/rf.c
#include "rf.h"
#include "xrfdc.h"
#include "xparameters.h"
#include "xil_printf.h"
#include "platform.h"
XRFdc RFdcInst; /* RFdc driver instance */
u8 rf_clock_status;//0 if ok, 0xFF if bad
/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
#define RFDC_DEVICE_ID XPAR_XRFDC_0_DEVICE_ID
#ifndef __BAREMETAL__
#define BUS_NAME "platform"
#define RFDC_DEV_NAME "a0000000.usp_rf_data_converter"
#endif
/****************************************************************************/
/**
*
* This function runs a test on the RFSoC data converter device using the
* driver APIs.
* This function does the following tasks:
* - Initialize the RFdc device driver instance
* - Set the Decoder Mode.
* - Get the Decoder Mode
* - Compare Set and Get settings
*
* @param RFdcDeviceId is the XPAR_<XRFDC_instance>_DEVICE_ID value
* from xparameters.h.
*
* @return
* - XRFDC_SUCCESS if the example has completed successfully.
* - XRFDC_FAILURE if the example has failed.
*
* @note None
*
****************************************************************************/
uint8_t rf_init()
{
rf_clock_status = 0xFF;
print("Running RF self test...\r\n");
if(rf_self_test() == XRFDC_SUCCESS)
{
print("Self test success!\r\n");
}
else
{
print("Self test failed!\r\n");
}
print("Checking data paths...\r\n");
u16 tile_num = 0;
for(tile_num = 0; tile_num < 3; tile_num++){
//Check the ADC path
if(XRFdc_IsADCDigitalPathEnabled(&RFdcInst, tile_num, 0))
{
xil_printf("ADC data path enabled for tile %x\r\n", tile_num);
}
else
{
xil_printf("ADC data path disabled for tile %x\r\n", tile_num);
}
//Check the DAC path
if(XRFdc_IsDACDigitalPathEnabled(&RFdcInst, tile_num, 0))
{
xil_printf("DAC data path enabled for tile %x\r\n", tile_num);
}
else
{
xil_printf("DAC data path disabled for tile %x\r\n", tile_num);
}
}
return 0;
}
//Returns 0 if clock is active
u8 get_rf_clock_status()
{
return rf_clock_status;
}
int rf_self_test()
{
u16 RFdcDeviceId = RFDC_DEVICE_ID;
int Status;
u16 Tile;
u16 Block;
XRFdc_Config *ConfigPtr;
XRFdc *RFdcInstPtr = &RFdcInst;
u32 SetFabricRate;
u32 GetFabricRate;
#ifndef __BAREMETAL__
struct metal_device *device;
struct metal_io_region *io;
int ret = 0;
#endif
struct metal_init_params init_param = METAL_INIT_DEFAULTS;
if (metal_init(&init_param)) {
printf("ERROR: Failed to run metal initialization\n");
return XRFDC_FAILURE;
}
/* Initialize the RFdc driver. */
ConfigPtr = XRFdc_LookupConfig(RFdcDeviceId);
if (ConfigPtr == NULL) {
return XRFDC_FAILURE;
}
Status = XRFdc_CfgInitialize(RFdcInstPtr, ConfigPtr);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
#ifndef __BAREMETAL__
ret = metal_device_open(BUS_NAME, RFDC_DEV_NAME, &device);
if (ret) {
printf("ERROR: Failed to open device a0000000.usp_rf_data_converter.\n");
return XRFDC_FAILURE;
}
/* Map RFDC device IO region */
io = metal_device_io_region(device, 0);
if (!io) {
printf("ERROR: Failed to map RFDC region for %s.\n",
device->name);
return XRFDC_FAILURE;
}
RFdcInstPtr->device = device;
RFdcInstPtr->io = io;
#endif
SetFabricRate = 0x8;
Tile = 0x0;
for (Block = 0; Block <4; Block++) {
if (XRFdc_IsDACBlockEnabled(RFdcInstPtr, Tile, Block)) {
Status = XRFdc_SetFabWrVldWords(RFdcInstPtr, Tile, Block, SetFabricRate);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
Status = XRFdc_GetFabWrVldWords(RFdcInstPtr, XRFDC_DAC_TILE,
Tile, Block, &GetFabricRate);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
Status = CompareFabricRate(SetFabricRate, GetFabricRate);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
}
SetFabricRate = 0x4;
if (XRFdc_IsADCBlockEnabled(RFdcInstPtr, Tile, Block)) {
if (RFdcInstPtr->ADC4GSPS == XRFDC_ADC_4GSPS) {
if ((Block == 2) || (Block == 3))
continue;
else if (Block == 1) {
if (XRFdc_IsADCBlockEnabled(RFdcInstPtr, Tile, 2) == 0)
continue;
}
}
Status = XRFdc_SetFabRdVldWords(RFdcInstPtr, Tile, Block, SetFabricRate);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
Status = XRFdc_GetFabRdVldWords(RFdcInstPtr, XRFDC_ADC_TILE,
Tile, Block, &GetFabricRate);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
Status = CompareFabricRate(SetFabricRate, GetFabricRate);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
}
}
u16 tile_num = 0;
for(tile_num = 0; tile_num < 4; tile_num++){
Status = XRFdc_Reset(RFdcInstPtr, XRFDC_ADC_TILE, tile_num);
if (Status != XRFDC_SUCCESS) {
//return XRFDC_FAILURE;
xil_printf("No clock for ADC tile %x\r\n", tile_num);
}
else
{
xil_printf("Clock found for ADC tile %x\r\n", tile_num);
}
Status = XRFdc_Reset(RFdcInstPtr, XRFDC_DAC_TILE, tile_num);
if (Status != XRFDC_SUCCESS) {
xil_printf("No clock for DAC tile %x\r\n", tile_num);
}
else
{
xil_printf("Clock found for DAC tile %x\r\n", tile_num);
rf_clock_status = 0;//We now have a working clock
}
}
for (Block = 0; Block <4; Block++) {
if (XRFdc_IsDACBlockEnabled(RFdcInstPtr, Tile, Block)) {
Status = XRFdc_GetFabWrVldWords(RFdcInstPtr, XRFDC_DAC_TILE,
Tile, Block, &GetFabricRate);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
if (GetFabricRate == 0x8) {
return XRFDC_FAILURE;
}
}
if (XRFdc_IsADCBlockEnabled(RFdcInstPtr, Tile, Block)) {
if (RFdcInstPtr->ADC4GSPS == XRFDC_ADC_4GSPS) {
if ((Block == 2) || (Block == 3))
continue;
else if (Block == 1) {
if (XRFdc_IsADCBlockEnabled(RFdcInstPtr, Tile, 2) == 0)
continue;
}
}
Status = XRFdc_GetFabRdVldWords(RFdcInstPtr, XRFDC_ADC_TILE,
Tile, Block, &GetFabricRate);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
if (GetFabricRate == 0x4) {
return XRFDC_FAILURE;
}
}
}
return XRFDC_SUCCESS;
}
/****************************************************************************/
/*
*
* This function compares the two Fabric Rate variables and return 0 if
* same and returns 1 if not same.
*
* @param SetFabricRate Fabric Rate value set.
* @param GetFabricRate Fabric Rate value get.
*
* @return
* - 0 if both structures are same.
* - 1 if both structures are not same.
*
* @note None
*
*****************************************************************************/
int CompareFabricRate(u32 SetFabricRate, u32 GetFabricRate)
{
if (SetFabricRate == GetFabricRate)
return 0;
else
return 1;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_extern.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#ifndef PM_EXTERN_H_
#define PM_EXTERN_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
typedef struct PmSlave PmSlave;
/*********************************************************************
* Global data declarations
********************************************************************/
extern PmSlave pmSlaveExternDevice_g;
/*********************************************************************
* Function declarations
********************************************************************/
s32 PmExternWakeMasters(void);
#ifdef __cplusplus
}
#endif
#endif /* PM_EXTERN_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_pinctrl.c
/*
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "pm_common.h"
#include "pm_slave.h"
#include "pm_periph.h"
#include "pm_usb.h"
#include "pm_requirement.h"
#include "pm_pinctrl.h"
#define PINMUX_FN(name, fn, sel, do) \
{ \
.select = sel, \
.fid = fn, \
PIN_##do \
}
#define PIN_NULL \
.slaves = NULL, \
.slavesCnt = 0U
#define PIN_BIND(c) \
.slaves = c, \
.slavesCnt = ARRAY_SIZE(c)
#define PINMUX(id) \
static u8 pinMux##id[]
#define PINMUX_REF(pinmux) \
{ \
.pinMux = pinmux, \
.pinMuxSize = ARRAY_SIZE(pinmux), \
}
#define FID(name) PINCTRL_FUNC_##name
#define DEFINE_PIN(id) \
{ \
.pinMuxArr = pinMux##id, \
.owner = 0U, \
}
#define PM_PIN_PARAM_RO (1U << 0U)
#define PM_PIN_PARAM_2_BITS (1U << 1U)
#define PM_PIN_PARAM_PER_REG 26U
#define IOU_SLCR_BANK0_CTRL0 (IOU_SLCR_BASE + 0x138U)
#define IOU_SLCR_BANK0_CTRL1 (IOU_SLCR_BASE + 0x154U)
#define PM_IOU_SLCR_BANK_OFFSET (IOU_SLCR_BANK0_CTRL1 - IOU_SLCR_BANK0_CTRL0)
#define PM_PIN_PARAM_GET_ADDR(pinId, regOffset) \
(IOU_SLCR_BANK0_CTRL0 + \
PM_IOU_SLCR_BANK_OFFSET * (pinId / PM_PIN_PARAM_PER_REG) + regOffset)
#define IOU_SLCR_BANK1_CTRL5 (IOU_SLCR_BASE + 164U)
#define FIX_BANK1_CTRL5(shift) \
shift = ((shift < 12U) ? (shift + 14U) : (shift - 12U))
#define SWAP_BITS_BANK1_CTRL5(val) \
val = ((val & 0x3FFFU) << 12U) | ((val >> 14U) & 0xFFFU)
/**
* PmPinMuxFn - PIN mux function model
* @slaves Pointer to the array of associated slaves
* @slavesCnt Number of elements in 'slaves' array
* @fid Function ID
* @select Select value
*/
typedef struct PmPinMuxFn {
const PmSlave** const slaves;
const u8 slavesCnt;
const u8 fid;
const u8 select;
} PmPinMuxFn;
/**
* PmMioPin - MIO PIN model
* @pinMuxArr Array of mux function ids
* @owner IPI mask of the master which requested PIN control
*/
typedef struct PmMioPin {
u8* pinMuxArr;
u32 owner;
} PmMioPin;
/**
* PmPinParam - PIN parameter structure
* @offset Register offset
* @flags Parameter flags
*/
typedef struct PmPinParam {
const u8 offset;
const u8 flags;
} PmPinParam;
static const PmSlave* pmCan0Slaves[] = { &pmSlaveCan0_g };
static const PmSlave* pmCan1Slaves[] = { &pmSlaveCan1_g };
static const PmSlave* pmGpioSlaves[] = { &pmSlaveGpio_g };
static const PmSlave* pmI2C0Slaves[] = { &pmSlaveI2C0_g };
static const PmSlave* pmI2C1Slaves[] = { &pmSlaveI2C1_g };
static const PmSlave* pmQSpiSlaves[] = { &pmSlaveQSpi_g };
static const PmSlave* pmSpi0Slaves[] = { &pmSlaveSpi0_g };
static const PmSlave* pmSpi1Slaves[] = { &pmSlaveSpi1_g };
static const PmSlave* pmSD0Slaves[] = { &pmSlaveSD0_g };
static const PmSlave* pmSD1Slaves[] = { &pmSlaveSD1_g };
static const PmSlave* pmNandSlaves[] = { &pmSlaveNand_g };
static const PmSlave* pmTtc0Slaves[] = { &pmSlaveTtc0_g };
static const PmSlave* pmTtc1Slaves[] = { &pmSlaveTtc1_g };
static const PmSlave* pmTtc2Slaves[] = { &pmSlaveTtc2_g };
static const PmSlave* pmTtc3Slaves[] = { &pmSlaveTtc3_g };
static const PmSlave* pmUart0Slaves[] = { &pmSlaveUart0_g };
static const PmSlave* pmUart1Slaves[] = { &pmSlaveUart1_g };
static const PmSlave* pmUsb0Slaves[] = { &pmSlaveUsb0_g.slv };
static const PmSlave* pmUsb1Slaves[] = { &pmSlaveUsb1_g.slv };
static const PmSlave* pmSwdt1Slaves[] = { &pmSlaveFpdWdt_g };
static const PmSlave* pmPcieSlaves[] = { &pmSlavePcie_g };
static const PmSlave* pmDPSlaves[] = { &pmSlaveDP_g };
static const PmSlave* pmEth0Slaves[] = { &pmSlaveEth0_g };
static const PmSlave* pmEth1Slaves[] = { &pmSlaveEth1_g };
static const PmSlave* pmEth2Slaves[] = { &pmSlaveEth2_g };
static const PmSlave* pmEth3Slaves[] = { &pmSlaveEth3_g };
static const PmSlave* pmGemTsuSlaves[] = { &pmSlaveEth0_g,
&pmSlaveEth1_g,
&pmSlaveEth2_g,
&pmSlaveEth3_g };
PmPinMuxFn PmPinMuxFunArr[] = {
PINMUX_FN(Can0, FID(CAN0), 0x20U, BIND(pmCan0Slaves)),
PINMUX_FN(Can1, FID(CAN1), 0x20U, BIND(pmCan1Slaves)),
PINMUX_FN(Eth0, FID(ETHERNET0), 0x02U, BIND(pmEth0Slaves)),
PINMUX_FN(Eth1, FID(ETHERNET1), 0x02U, BIND(pmEth1Slaves)),
PINMUX_FN(Eth2, FID(ETHERNET2), 0x02U, BIND(pmEth2Slaves)),
PINMUX_FN(Eth3, FID(ETHERNET3), 0x02U, BIND(pmEth3Slaves)),
PINMUX_FN(GemTsu, FID(GEMTSU0), 0x02U, BIND(pmGemTsuSlaves)),
PINMUX_FN(Gpio, FID(GPIO0), 0x00U, BIND(pmGpioSlaves)),
PINMUX_FN(I2C0, FID(I2C0), 0x40U, BIND(pmI2C0Slaves)),
PINMUX_FN(I2C1, FID(I2C1), 0x40U, BIND(pmI2C1Slaves)),
PINMUX_FN(Mdio0, FID(MDIO0), 0x60U, BIND(pmEth0Slaves)),
PINMUX_FN(Mdio1, FID(MDIO1), 0x80U, BIND(pmEth1Slaves)),
PINMUX_FN(Mdio2, FID(MDIO2), 0xA0U, BIND(pmEth2Slaves)),
PINMUX_FN(Mdio3, FID(MDIO3), 0xC0U, BIND(pmEth3Slaves)),
PINMUX_FN(QSpi, FID(QSPI0), 0x02U, BIND(pmQSpiSlaves)),
PINMUX_FN(QSpiFbClk, FID(QSPI_FBCLK),0x02U, BIND(pmQSpiSlaves)),
PINMUX_FN(QSpiSS, FID(QSPI_SS), 0x02U, BIND(pmQSpiSlaves)),
PINMUX_FN(Spi0, FID(SPI0), 0x80U, BIND(pmSpi0Slaves)),
PINMUX_FN(Spi1, FID(SPI1), 0x80U, BIND(pmSpi1Slaves)),
PINMUX_FN(Spi0SS, FID(SPI0_SS), 0x80U, BIND(pmSpi0Slaves)),
PINMUX_FN(Spi1SS, FID(SPI1_SS), 0x80U, BIND(pmSpi1Slaves)),
PINMUX_FN(Sdio0, FID(SDIO0), 0x08U, BIND(pmSD0Slaves)),
PINMUX_FN(Sdio0Pc, FID(SDIO0_PC), 0x08U, BIND(pmSD0Slaves)),
PINMUX_FN(Sdio0Cd, FID(SDIO0_CD), 0x08U, BIND(pmSD0Slaves)),
PINMUX_FN(Sdio0Wp, FID(SDIO0_WP), 0x08U, BIND(pmSD0Slaves)),
PINMUX_FN(Sdio1, FID(SDIO1), 0x10U, BIND(pmSD1Slaves)),
PINMUX_FN(Sdio1Pc, FID(SDIO1_PC), 0x10U, BIND(pmSD1Slaves)),
PINMUX_FN(Sdio1Cd, FID(SDIO1_CD), 0x10U, BIND(pmSD1Slaves)),
PINMUX_FN(Sdio1Wp, FID(SDIO1_WP), 0x10U, BIND(pmSD1Slaves)),
PINMUX_FN(Nand, FID(NAND0), 0x04U, BIND(pmNandSlaves)),
PINMUX_FN(NandCe, FID(NAND0_CE), 0x04U, BIND(pmNandSlaves)),
PINMUX_FN(NandRb, FID(NAND0_RB), 0x04U, BIND(pmNandSlaves)),
PINMUX_FN(NandDqs, FID(NAND0_DQS), 0x04U, BIND(pmNandSlaves)),
PINMUX_FN(Ttc0Clk, FID(TTC0_CLK), 0xA0U, BIND(pmTtc0Slaves)),
PINMUX_FN(Ttc0Wav, FID(TTC0_WAV), 0xA0U, BIND(pmTtc0Slaves)),
PINMUX_FN(Ttc1Clk, FID(TTC1_CLK), 0xA0U, BIND(pmTtc1Slaves)),
PINMUX_FN(Ttc1Wav, FID(TTC1_WAV), 0xA0U, BIND(pmTtc1Slaves)),
PINMUX_FN(Ttc2Clk, FID(TTC2_CLK), 0xA0U, BIND(pmTtc2Slaves)),
PINMUX_FN(Ttc2Wav, FID(TTC2_WAV), 0xA0U, BIND(pmTtc2Slaves)),
PINMUX_FN(Ttc3Clk, FID(TTC3_CLK), 0xA0U, BIND(pmTtc3Slaves)),
PINMUX_FN(Ttc3Wav, FID(TTC3_WAV), 0xA0U, BIND(pmTtc3Slaves)),
PINMUX_FN(Uart0, FID(UART0), 0xC0U, BIND(pmUart0Slaves)),
PINMUX_FN(Uart1, FID(UART1), 0xC0U, BIND(pmUart1Slaves)),
PINMUX_FN(Usb0, FID(USB0), 0x04U, BIND(pmUsb0Slaves)),
PINMUX_FN(Usb1, FID(USB1), 0x04U, BIND(pmUsb1Slaves)),
PINMUX_FN(Swdt0Clk, FID(SWDT0_CLK), 0x60U, NULL),
PINMUX_FN(Swdt0Rst, FID(SWDT0_RST), 0x60U, NULL),
PINMUX_FN(Swdt1Clk, FID(SWDT1_CLK), 0x60U, BIND(pmSwdt1Slaves)),
PINMUX_FN(Swdt1Rst, FID(SWDT1_RST), 0x60U, BIND(pmSwdt1Slaves)),
PINMUX_FN(Pmu, FID(PMU0), 0x08U, NULL),
PINMUX_FN(Pcie, FID(PCIE0), 0x04U, BIND(pmPcieSlaves)),
PINMUX_FN(Csu, FID(CSU0), 0x18U, NULL),
PINMUX_FN(Dp, FID(DPAUX0), 0x18U, BIND(pmDPSlaves)),
PINMUX_FN(PJtag, FID(PJTAG0), 0x60U, NULL),
PINMUX_FN(Trace, FID(TRACE0), 0xE0U, NULL),
PINMUX_FN(TraceClk, FID(TRACE0_CLK),0xE0U, NULL),
PINMUX_FN(TestScan, FID(TESTSCAN0), 0x10U, NULL),
};
/*
* Mux select data is defined as follows:
*
* L0_SEL[0], L0_SEL[1],
* L1_SEL[0], L1_SEL[1],
* L2_SEL[0], L2_SEL[1], L2_SEL[2], L2_SEL[3],
* L3_SEL[0], L3_SEL[1], L3_SEL[2], L3_SEL[3],
* L3_SEL[4], L3_SEL[5], L3_SEL[6], L3_SEL[7],
* MAX_FUNCTION
*
* Note: L0_SEL[0], L1_SEL[0], and L2_SEL[0] are always reserved. If an element
* in a pattern (matrix) above is missing an empty place is preserved to be able
* to easily compare definitions with spec.
*/
PINMUX(0) = { FID(QSPI0),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI0), FID(TTC3_CLK), FID(UART1), FID(TRACE0_CLK),
MAX_FUNCTION
};
PINMUX(1) = { FID(QSPI0),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI0_SS), FID(TTC3_WAV), FID(UART1), FID(TRACE0_CLK),
MAX_FUNCTION
};
PINMUX(2) = { FID(QSPI0),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI0_SS), FID(TTC2_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(3) = { FID(QSPI0),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI0_SS), FID(TTC2_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(4) = { FID(QSPI0),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI0), FID(TTC1_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(5) = { FID(QSPI_SS),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI0), FID(TTC1_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(6) = { FID(QSPI_FBCLK),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI1), FID(TTC0_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(7) = { FID(QSPI_SS),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI1_SS), FID(TTC0_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(8) = { FID(QSPI0),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI1_SS), FID(TTC3_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(9) = { FID(QSPI0),
FID(NAND0_CE),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI1_SS), FID(TTC3_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(10) = { FID(QSPI0),
FID(NAND0_RB),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI1), FID(TTC2_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(11) = { FID(QSPI0),
FID(NAND0_RB),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI1), FID(TTC2_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(12) = { FID(QSPI0),
FID(NAND0_DQS),
FID(TESTSCAN0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI0), FID(TTC1_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(13) = {
FID(NAND0),
FID(SDIO0), FID(TESTSCAN0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI0_SS), FID(TTC1_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(14) = {
FID(NAND0),
FID(SDIO0), FID(TESTSCAN0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI0_SS), FID(TTC0_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(15) = {
FID(NAND0),
FID(SDIO0), FID(TESTSCAN0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI0_SS), FID(TTC0_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(16) = {
FID(NAND0),
FID(SDIO0), FID(TESTSCAN0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI0), FID(TTC3_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(17) = {
FID(NAND0),
FID(SDIO0), FID(TESTSCAN0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI0), FID(TTC3_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(18) = {
FID(NAND0),
FID(SDIO0), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI1), FID(TTC2_CLK), FID(UART0),
MAX_FUNCTION
};
PINMUX(19) = {
FID(NAND0),
FID(SDIO0), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI1_SS), FID(TTC2_WAV), FID(UART0),
MAX_FUNCTION
};
PINMUX(20) = {
FID(NAND0),
FID(SDIO0), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI1_SS), FID(TTC1_CLK), FID(UART1),
MAX_FUNCTION
};
PINMUX(21) = {
FID(NAND0),
FID(SDIO0), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI1_SS), FID(TTC1_WAV), FID(UART1),
MAX_FUNCTION
};
PINMUX(22) = {
FID(NAND0),
FID(SDIO0), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI1), FID(TTC0_CLK), FID(UART0),
MAX_FUNCTION
};
PINMUX(23) = {
FID(NAND0),
FID(SDIO0_PC), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI1), FID(TTC0_WAV), FID(UART0),
MAX_FUNCTION
};
PINMUX(24) = {
FID(NAND0),
FID(SDIO0_CD), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(TTC3_CLK), FID(UART1),
MAX_FUNCTION
};
PINMUX(25) = {
FID(NAND0),
FID(SDIO0_WP), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(TTC3_WAV), FID(UART1),
MAX_FUNCTION
};
PINMUX(26) = { FID(ETHERNET0),
FID(NAND0_CE),
FID(PMU0), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI0), FID(TTC2_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(27) = { FID(ETHERNET0),
FID(NAND0_RB),
FID(PMU0), FID(TESTSCAN0), FID(DPAUX0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI0_SS), FID(TTC2_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(28) = { FID(ETHERNET0),
FID(NAND0_RB),
FID(PMU0), FID(TESTSCAN0), FID(DPAUX0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI0_SS), FID(TTC1_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(29) = { FID(ETHERNET0),
FID(PCIE0),
FID(PMU0), FID(TESTSCAN0), FID(DPAUX0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI0_SS), FID(TTC1_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(30) = { FID(ETHERNET0),
FID(PCIE0),
FID(PMU0), FID(TESTSCAN0), FID(DPAUX0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI0), FID(TTC0_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(31) = { FID(ETHERNET0),
FID(PCIE0),
FID(PMU0), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI0), FID(TTC0_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(32) = { FID(ETHERNET0),
FID(NAND0_DQS),
FID(PMU0), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI1), FID(TTC3_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(33) = { FID(ETHERNET0),
FID(PCIE0),
FID(PMU0), FID(TESTSCAN0), FID(CSU0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI1_SS), FID(TTC3_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(34) = { FID(ETHERNET0),
FID(PCIE0),
FID(PMU0), FID(TESTSCAN0), FID(DPAUX0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI1_SS), FID(TTC2_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(35) = { FID(ETHERNET0),
FID(PCIE0),
FID(PMU0), FID(TESTSCAN0), FID(DPAUX0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI1_SS), FID(TTC2_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(36) = { FID(ETHERNET0),
FID(PCIE0),
FID(PMU0), FID(TESTSCAN0), FID(DPAUX0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI1), FID(TTC1_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(37) = { FID(ETHERNET0),
FID(PCIE0),
FID(PMU0), FID(TESTSCAN0), FID(DPAUX0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI1), FID(TTC1_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(38) = { FID(ETHERNET1),
FID(SDIO0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI0), FID(TTC0_CLK), FID(UART0), FID(TRACE0_CLK),
MAX_FUNCTION
};
PINMUX(39) = { FID(ETHERNET1),
FID(SDIO0_CD), FID(SDIO1),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI0_SS), FID(TTC0_WAV), FID(UART0), FID(TRACE0_CLK),
MAX_FUNCTION
};
PINMUX(40) = { FID(ETHERNET1),
FID(SDIO0), FID(SDIO1),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI0_SS), FID(TTC3_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(41) = { FID(ETHERNET1),
FID(SDIO0), FID(SDIO1),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI0_SS), FID(TTC3_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(42) = { FID(ETHERNET1),
FID(SDIO0), FID(SDIO1),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI0), FID(TTC2_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(43) = { FID(ETHERNET1),
FID(SDIO0), FID(SDIO1_PC),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI0), FID(TTC2_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(44) = { FID(ETHERNET1),
FID(SDIO0), FID(SDIO1_WP),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI1), FID(TTC1_CLK), FID(UART1),
MAX_FUNCTION
};
PINMUX(45) = { FID(ETHERNET1),
FID(SDIO0), FID(SDIO1_CD),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI1_SS), FID(TTC1_WAV), FID(UART1),
MAX_FUNCTION
};
PINMUX(46) = { FID(ETHERNET1),
FID(SDIO0), FID(SDIO1),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI1_SS), FID(TTC0_CLK), FID(UART0),
MAX_FUNCTION
};
PINMUX(47) = { FID(ETHERNET1),
FID(SDIO0), FID(SDIO1),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI1_SS), FID(TTC0_WAV), FID(UART0),
MAX_FUNCTION
};
PINMUX(48) = { FID(ETHERNET1),
FID(SDIO0), FID(SDIO1),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI1), FID(TTC3_CLK), FID(UART1),
MAX_FUNCTION
};
PINMUX(49) = { FID(ETHERNET1),
FID(SDIO0_PC), FID(SDIO1),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI1), FID(TTC3_WAV), FID(UART1),
MAX_FUNCTION
};
PINMUX(50) = { FID(GEMTSU0),
FID(SDIO0_WP), FID(SDIO1),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(MDIO1), FID(TTC2_CLK), FID(UART0),
MAX_FUNCTION
};
PINMUX(51) = { FID(GEMTSU0),
FID(SDIO0_WP), FID(SDIO1),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(MDIO1), FID(TTC2_WAV), FID(UART0),
MAX_FUNCTION
};
PINMUX(52) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI0), FID(TTC1_CLK), FID(UART1), FID(TRACE0_CLK),
MAX_FUNCTION
};
PINMUX(53) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI0_SS), FID(TTC1_WAV), FID(UART1), FID(TRACE0_CLK),
MAX_FUNCTION
};
PINMUX(54) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI0_SS), FID(TTC0_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(55) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI0_SS), FID(TTC0_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(56) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI0), FID(TTC3_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(57) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI0), FID(TTC3_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(58) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI1), FID(TTC2_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(59) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(PJTAG0),
FID(SPI1_SS), FID(TTC2_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(60) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI1_SS), FID(TTC1_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(61) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(PJTAG0),
FID(SPI1_SS), FID(TTC1_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(62) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI1), FID(TTC0_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(63) = { FID(ETHERNET2),
FID(USB0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI1), FID(TTC0_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(64) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI0), FID(TTC3_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(65) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0_CD),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI0_SS), FID(TTC3_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(66) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI0_SS), FID(TTC2_CLK), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(67) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI0_SS), FID(TTC2_WAV), FID(UART0), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(68) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI0), FID(TTC1_CLK), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(69) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0), FID(SDIO1_WP),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI0), FID(TTC1_WAV), FID(UART1), FID(TRACE0),
MAX_FUNCTION
};
PINMUX(70) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0), FID(SDIO1_PC),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI1), FID(TTC0_CLK), FID(UART0),
MAX_FUNCTION
};
PINMUX(71) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0), FID(SDIO1),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI1_SS), FID(TTC0_WAV), FID(UART0),
MAX_FUNCTION
};
PINMUX(72) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0), FID(SDIO1),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_CLK),
FID(SPI1_SS), FID(UART1),
MAX_FUNCTION
};
PINMUX(73) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0), FID(SDIO1),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(SWDT1_RST),
FID(SPI1_SS), FID(UART1),
MAX_FUNCTION
};
PINMUX(74) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0), FID(SDIO1),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_CLK),
FID(SPI1), FID(UART0),
MAX_FUNCTION
};
PINMUX(75) = { FID(ETHERNET3),
FID(USB1),
FID(SDIO0_PC), FID(SDIO1),
FID(GPIO0), FID(CAN0), FID(I2C0), FID(SWDT0_RST),
FID(SPI1), FID(UART0),
MAX_FUNCTION
};
PINMUX(76) = {
FID(SDIO0_WP), FID(SDIO1),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(MDIO0),
FID(MDIO1), FID(MDIO2), FID(MDIO3),
MAX_FUNCTION
};
PINMUX(77) = {
FID(SDIO1_CD),
FID(GPIO0), FID(CAN1), FID(I2C1), FID(MDIO0),
FID(MDIO1), FID(MDIO2), FID(MDIO3),
MAX_FUNCTION
};
static PmMioPin pmPinMuxCtrl[] = {
DEFINE_PIN(0), DEFINE_PIN(1), DEFINE_PIN(2), DEFINE_PIN(3),
DEFINE_PIN(4), DEFINE_PIN(5), DEFINE_PIN(6), DEFINE_PIN(7),
DEFINE_PIN(8), DEFINE_PIN(9),
DEFINE_PIN(10), DEFINE_PIN(11), DEFINE_PIN(12), DEFINE_PIN(13),
DEFINE_PIN(14), DEFINE_PIN(15), DEFINE_PIN(16), DEFINE_PIN(17),
DEFINE_PIN(18), DEFINE_PIN(19),
DEFINE_PIN(20), DEFINE_PIN(21), DEFINE_PIN(22), DEFINE_PIN(23),
DEFINE_PIN(24), DEFINE_PIN(25), DEFINE_PIN(26), DEFINE_PIN(27),
DEFINE_PIN(28), DEFINE_PIN(29),
DEFINE_PIN(30), DEFINE_PIN(31), DEFINE_PIN(32), DEFINE_PIN(33),
DEFINE_PIN(34), DEFINE_PIN(35), DEFINE_PIN(36), DEFINE_PIN(37),
DEFINE_PIN(38), DEFINE_PIN(39),
DEFINE_PIN(40), DEFINE_PIN(41), DEFINE_PIN(42), DEFINE_PIN(43),
DEFINE_PIN(44), DEFINE_PIN(45), DEFINE_PIN(46), DEFINE_PIN(47),
DEFINE_PIN(48), DEFINE_PIN(49),
DEFINE_PIN(50), DEFINE_PIN(51), DEFINE_PIN(52), DEFINE_PIN(53),
DEFINE_PIN(54), DEFINE_PIN(55), DEFINE_PIN(56), DEFINE_PIN(57),
DEFINE_PIN(58), DEFINE_PIN(59),
DEFINE_PIN(60), DEFINE_PIN(61), DEFINE_PIN(62), DEFINE_PIN(63),
DEFINE_PIN(64), DEFINE_PIN(65), DEFINE_PIN(66), DEFINE_PIN(67),
DEFINE_PIN(68), DEFINE_PIN(69),
DEFINE_PIN(70), DEFINE_PIN(71), DEFINE_PIN(72), DEFINE_PIN(73),
DEFINE_PIN(74), DEFINE_PIN(75), DEFINE_PIN(76), DEFINE_PIN(77),
};
static PmPinParam pmPinParams[] = {
[PINCTRL_CONFIG_SLEW_RATE] = {
.offset = 0x14U,
.flags = 0U,
},
[PINCTRL_CONFIG_BIAS_STATUS] = {
.offset = 0x10U,
.flags = 0U,
},
[PINCTRL_CONFIG_PULL_CTRL] = {
.offset = 0xCU,
.flags = 0U,
},
[PINCTRL_CONFIG_SCHMITT_CMOS] = {
.offset = 0x8U,
.flags = 0U,
},
[PINCTRL_CONFIG_DRIVE_STRENGTH] = {
.offset = 0x0U,
.flags = PM_PIN_PARAM_2_BITS,
},
[PINCTRL_CONFIG_VOLTAGE_STATUS] = {
.offset = 0x18U,
.flags = PM_PIN_PARAM_RO,
},
};
/**
* PmPinCtrlRequestInt() - Request PIN control
* @ipiMask IPI mask of the master
* @pinId ID of the pin in question
*
* @return XST_SUCCESS if successfully requested
* XST_INVALID_PARAM if pinId argument is not valid
* XST_PM_NO_ACCESS if PIN control is already requested by another
* master
*/
s32 PmPinCtrlRequestInt(const u32 ipiMask, const u32 pinId)
{
s32 status = XST_SUCCESS;
if (pinId >= ARRAY_SIZE(pmPinMuxCtrl)) {
status = XST_INVALID_PARAM;
goto done;
}
if (0U != pmPinMuxCtrl[pinId].owner) {
if (ipiMask == pmPinMuxCtrl[pinId].owner) {
goto done;
}
status = XST_PM_NO_ACCESS;
goto done;
}
pmPinMuxCtrl[pinId].owner = ipiMask;
done:
return status;
}
/**
* PmPinCtrlReleaseInt() - Release PIN control
* @ipiMask IPI mask of the master
* @pinId ID of the pin in question
*
* @return XST_SUCCESS if successfully released
* XST_INVALID_PARAM if pinId argument is not valid
* XST_FAILURE if PIN control has not been previously requested
*/
s32 PmPinCtrlReleaseInt(const u32 ipiMask, const u32 pinId)
{
s32 status = XST_SUCCESS;
if (pinId >= ARRAY_SIZE(pmPinMuxCtrl)) {
status = XST_INVALID_PARAM;
goto done;
}
if (ipiMask != pmPinMuxCtrl[pinId].owner) {
status = XST_FAILURE;
goto done;
}
pmPinMuxCtrl[pinId].owner = 0U;
done:
return status;
}
/**
* PmPinCtrlGetFunctionInt() - Get currently configured PIN function
* @pinId ID of the PIN
* @fnId Location to store function ID
*
* @return XST_SUCCESS if function is get
* XST_INVALID_PARAM if provided argument is invalid
* XST_PM_INTERNAL if function cannot be mapped
*/
s32 PmPinCtrlGetFunctionInt(const u32 pinId, u32* const fnId)
{
s32 status = XST_PM_INTERNAL;
u32 reg, i;
u8 *pinMuxArr;
if (pinId >= ARRAY_SIZE(pmPinMuxCtrl)) {
status = XST_INVALID_PARAM;
goto done;
}
reg = XPfw_Read32(IOU_SLCR_BASE + (4U * pinId));
pinMuxArr = pmPinMuxCtrl[pinId].pinMuxArr;
for (i = 0U; pinMuxArr[i] != MAX_FUNCTION; i++) {
if (PmPinMuxFunArr[pinMuxArr[i]].select == reg) {
*fnId = PmPinMuxFunArr[pinMuxArr[i]].fid;
status = XST_SUCCESS;
break;
}
};
done:
return status;
}
/**
* PmPinCtrlCheckPerms() - Check if master has permission to control the PIN
* @ipiMask IPI mask of the target master
* @pinId ID of the target PIN
*
* @return XST_SUCCESS is master is allowed to control the PIN
* XST_INVALID_PARAM if pinId is invalid
* XST_PM_NO_ACCESS if master is no allowed to control the PIN
*/
s32 PmPinCtrlCheckPerms(const u32 ipiMask, const u32 pinId)
{
s32 status = XST_SUCCESS;
if (pinId >= ARRAY_SIZE(pmPinMuxCtrl)) {
status = XST_INVALID_PARAM;
goto done;
}
/* If the pin has not been previously requested return error */
if (ipiMask != pmPinMuxCtrl[pinId].owner) {
status = XST_PM_NO_ACCESS;
goto done;
}
done:
return status;
}
/**
* PmPinCtrlSetFunctionInt() - Set PIN function
* @master Master that attempts to set the PIN function
* @pinId ID of the PIN
* @fnId Function ID
*
* @return XST_SUCCESS if function is get
* XST_INVALID_PARAM if provided argument is invalid
* XST_PM_INTERNAL if function cannot be mapped base on current
* configuration
*/
s32 PmPinCtrlSetFunctionInt(const PmMaster* const master, const u32 pinId,
const u32 fnId)
{
s32 status = XST_INVALID_PARAM;
u32 val = 0U;
u32 i;
u32 s;
u8 *pinMuxArr = pmPinMuxCtrl[pinId].pinMuxArr;
for (i = 0U; pinMuxArr[i] != MAX_FUNCTION; i++) {
PmPinMuxFn *fn = &PmPinMuxFunArr[pinMuxArr[i]];
if (fn->fid != fnId) {
continue;
}
/* Found function, now check if the master can set it */
status = XST_SUCCESS;
val = fn->select;
for (s = 0U; s < fn->slavesCnt; s++) {
PmRequirement* req = PmRequirementGet(master,
fn->slaves[s]);
/*
* If there is not struct master is not allowed to use
* the slave that is associated with the target pin fn.
*/
if (NULL == req) {
status = XST_PM_NO_ACCESS;
break;
}
}
break;
};
if (XST_SUCCESS == status) {
XPfw_Write32(IOU_SLCR_BASE + (4U * pinId), val);
}
return status;
}
/**
* PmPinCtrlGetParam() - Get PIN configuration parameter value
* @pinId ID of the PIN
* @paramId ID of the PIN parameter
* @value Location to store the parameter value
*
* @return XST_SUCCESS or
* XST_INVALID_PARAM if provided argument is invalid
*
* @note See note in PmPinCtrlSetParam().
*/
s32 PmPinCtrlGetParam(const u32 pinId, const u32 paramId, u32* const value)
{
s32 status = XST_SUCCESS;
u32 addr, val, shift;
if ((paramId >= ARRAY_SIZE(pmPinParams)) ||
(pinId >= ARRAY_SIZE(pmPinMuxCtrl))) {
status = XST_INVALID_PARAM;
goto done;
}
shift = pinId % PM_PIN_PARAM_PER_REG;
addr = PM_PIN_PARAM_GET_ADDR(pinId, pmPinParams[paramId].offset);
val = XPfw_Read32(addr);
if (IOU_SLCR_BANK1_CTRL5 == addr) {
SWAP_BITS_BANK1_CTRL5(val);
}
*value = (val >> shift) & 0x1U;
if (0U != (PM_PIN_PARAM_2_BITS & pmPinParams[paramId].flags)) {
addr += 4U;
val = XPfw_Read32(addr);
val = (val >> shift) & 0x1U;
*value = (*value << 1U) | val;
}
done:
return status;
}
/**
* PmPinCtrlSetParam() - Set PIN configuration parameter value
* @ipiMask IPI mask of the master that initiated the request
* @pinId ID of the PIN
* @paramId ID of the PIN parameter
* @value Parameter value to be set
*
* @return XST_INVALID_PARAM if an argument is not valid
* XST_SUCCESS otherwise
*
* @note In bank1 ctrl5, pins are not mapped with sequential order.
* Pin 38 to 51 are mapped with BIT[0:13], Pin 26 to 37 are mapped
* with BIT[14:25].
*/
s32 PmPinCtrlSetParam(const u32 pinId, const u32 paramId, const u32 value)
{
s32 status = XST_INVALID_PARAM;
u32 addr, shift;
if (0U != (PM_PIN_PARAM_RO & pmPinParams[paramId].flags)) {
goto done;
}
if (0U != (PM_PIN_PARAM_2_BITS & pmPinParams[paramId].flags)) {
if (value > 3U) {
goto done;
}
} else {
if (value > 1U) {
goto done;
}
}
status = XST_SUCCESS;
shift = pinId % PM_PIN_PARAM_PER_REG;
addr = PM_PIN_PARAM_GET_ADDR(pinId, pmPinParams[paramId].offset);
if (IOU_SLCR_BANK1_CTRL5 == addr) {
FIX_BANK1_CTRL5(shift);
}
if (0U == (PM_PIN_PARAM_2_BITS & pmPinParams[paramId].flags)) {
XPfw_RMW32(addr, 1U << shift, value << shift);
/* When setting pull up/down we need to enable pull as well */
if (paramId == PINCTRL_CONFIG_PULL_CTRL) {
addr = PM_PIN_PARAM_GET_ADDR(pinId,
pmPinParams[PINCTRL_CONFIG_PULL_CTRL].offset);
if (addr == IOU_SLCR_BANK1_CTRL5) {
FIX_BANK1_CTRL5(shift);
}
XPfw_RMW32(addr, 1U << shift, value << shift);
}
} else {
/* Write value[0] at address + 4 and value[1] at address */
XPfw_RMW32(addr + 4U, 1U << shift, (value & 0x1U) << shift);
XPfw_RMW32(addr, 1U << shift, ((value & 0x2U) >> 1U) << shift);
}
done:
return status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_bisr.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_BISR_H_
#define XPM_BISR_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xpm_common.h"
#define LPD_TAG_ID 0x03
#define FPD_TAG_ID 0x04
#define CPM_TAG_ID 0x05
#define XRAM_TAG_ID 0x06
#define CPM5_TAG_ID 0x07
#define MEA_TAG_ID 0x08
#define MEB_TAG_ID 0x09
#define MEC_TAG_ID 0x0A
#define DDRMC_TAG_ID 0x0B
#define GTY_TAG_ID 0x0C
#define DCMAC_TAG_ID 0x0D
#define ILKN_TAG_ID 0x0E
#define MRMAC_TAG_ID 0x0F
#define SDFEC_TAG_ID 0x10
#define BRAM_TAG_ID 0x11
#define URAM_TAG_ID 0x12
#define CPM5_GTYP_TAG_ID 0x17
#define GTYP_TAG_ID 0x18
#define GTM_TAG_ID 0x19
#define PCSR_UNLOCK_VAL (0xF9E8D7C6U)
XStatus XPmBisr_Repair(u32 TagId);
XStatus XPmBisr_NidbLaneRepair(void);
int XPmBisr_TriggerLpd(void);
#ifdef __cplusplus
}
#endif
#endif /* XPM_BISR_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_config.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPFW_CONFIG_H_
#define XPFW_CONFIG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xparameters.h"
/************* User Configurable Options ***************/
/* PMUFW print levels */
#define XPFW_PRINT_VAL (1U)
#define XPFW_DEBUG_ERROR_VAL (0U)
#define XPFW_DEBUG_DETAILED_VAL (0U)
/**
* PMUFW Debug options
*/
#if XPFW_PRINT_VAL
#define XPFW_PRINT
#endif
#if XPFW_DEBUG_ERROR_VAL
#define XPFW_DEBUG_ERROR
#endif
#if XPFW_DEBUG_DETAILED_VAL
#define XPFW_DEBUG_DETAILED
#endif
/* PMU clock frequency in Hz */
#ifndef XPFW_CFG_PMU_CLK_FREQ
#define XPFW_CFG_PMU_CLK_FREQ XPAR_CPU_CORE_CLOCK_FREQ_HZ
#endif
/* Let the MB sleep when it is Idle in Main Loop */
#define SLEEP_WHEN_IDLE
/*
* PMU Firmware code include options
*
* PMU Firmware by default disables some functionality and enables some
* Here we are listing all the build flags with the default option.
* User can modify these flags to enable or disable any module/functionality
* - ENABLE_PM : Enables Power Management Module
* - ENABLE_EM : Enables Error Management Module
* - ENABLE_SCHEDULER : Enables the scheduler
* - ENABLE_MOD_ULTRA96 : Enables support for Ultra96 power button
* - ENABLE_RECOVERY : Enables WDT based restart of APU sub-system
* - ENABLE_RECOVERY_RESET_SYSTEM : Enables WDT based restart of system
* - ENABLE_RECOVERY_RESET_PS_ONLY : Enables WDT based restart of PS
* - ENABLE_ESCALATION : Enables escalation of sub-system restart to
* SRST/PS-only if the first restart attempt fails
* - ENABLE_WDT : Enables WDT based restart functionality for PMU
* - ENABLE_STL : Enables STL Module
* - ENABLE_RTC_TEST : Enables RTC Event Handler Test Module
* - ENABLE_IPI_CRC_VAL : Enables CRC calculation for IPI messages
* - ENABLE_FPGA_LOAD : Enables FPGA bit stream loading feature
* - ENABLE_SECURE : Enables security features
* - XPU_INTR_DEBUG_PRINT_ENABLE : Enables debug for XMPU/XPPU functionality
*
* - PM_LOG_LEVEL : Enables print based debug functions for PM. Possible
* values are: 1 (alerts), 2 (errors), 3 (warnings),
* 4 (info). Higher numbers include the debug scope of
* lower number, i.e. enabling 3 (warnings) also enables
* 1 (alerts) and 2 (errors).
* - IDLE_PERIPHERALS : Enables idling peripherals before PS or System reset
* - ENABLE_NODE_IDLING : Enables idling and reset of nodes before force
* of a sub-system
* - DEBUG_MODE : This macro enables PM debug prints if XPFW_DEBUG_DETAILED
* macro is also defined
* - ENABLE_POS : Enables Power Off Suspend feature
* - ENABLE_DDR_SR_WR : Enables DDR self refresh over warm restart feature
* - ENABLE_UNUSED_RPU_PWR_DWN : Enables unused RPU power down feature
* - DISABLE_CLK_PERMS : Disable clock permission checking (it is not safe
* to ever disable clock permission checking). Do this at
* your own responsibility.
* - ENABLE_EFUSE_ACCESS : Enables efuse access feature
* - USE_DDR_FOR_APU_RESTART : If this macro is enabled, PMU writes FSBL image
* to DDR from OCM if FSBL is running on APU. This is to free-up
* OCM memory for other uses.
* - ENABLE_RPU_RUN_MODE: Enables RPU monitoring module
*
* These macros are specific to ZCU100 design where it uses GPO1[2] as a
* board power line and
* - PMU_MIO_INPUT_PIN : Enables board shutdown related code for ZCU100
* - BOARD_SHUTDOWN_PIN : Tells board shutdown pin. In case of ZCU100,
* GPO1[2] is the board power line.
* - BOARD_SHUTDOWN_PIN_STATE : Tells what should be the state of board power
* line when system shutdown request comes
*/
#define ENABLE_PM_VAL (1U)
#define ENABLE_EM_VAL (0U)
#define ENABLE_SCHEDULER_VAL (1U)
#define ENABLE_MOD_ULTRA96_VAL (0U)
#define ENABLE_RECOVERY_VAL (0U)
#define ENABLE_RECOVERY_RESET_SYSTEM_VAL (0U)
#define ENABLE_RECOVERY_RESET_PS_ONLY_VAL (0U)
#define ENABLE_ESCALATION_VAL (0U)
#define CHECK_HEALTHY_BOOT_VAL (0U)
#define ENABLE_WDT_VAL (0U)
#define ENABLE_CUSTOM_MOD_VAL (0U)
#define ENABLE_STL_VAL (0U)
#define ENABLE_RTC_TEST_VAL (0U)
#define ENABLE_IPI_CRC_VAL (0U)
#define ENABLE_FPGA_LOAD_VAL (1U)
#define ENABLE_FPGA_READ_CONFIG_DATA_VAL (1U)
#define ENABLE_FPGA_READ_CONFIG_REG_VAL (1U)
#define ENABLE_SECURE_VAL (1U)
#define ENABLE_EFUSE_ACCESS (0U)
#define XPU_INTR_DEBUG_PRINT_ENABLE_VAL (0U)
#define PM_LOG_LEVEL_VAL (0U)
#define IDLE_PERIPHERALS_VAL (0U)
#define ENABLE_NODE_IDLING_VAL (0U)
#define DEBUG_MODE_VAL (0U)
#define ENABLE_POS_VAL (0U)
#define ENABLE_DDR_SR_WR_VAL (0U)
#define DISABLE_CLK_PERMS_VAL (0U)
#define ENABLE_UNUSED_RPU_PWR_DWN_VAL (1U)
#define PMU_MIO_INPUT_PIN_VAL (0U)
#define BOARD_SHUTDOWN_PIN_VAL (0U)
#define BOARD_SHUTDOWN_PIN_STATE_VAL (0U)
#define CONNECT_PMU_GPO_2_VAL (1U)
#define CONNECT_PMU_GPO_3_VAL (1U)
#define CONNECT_PMU_GPO_4_VAL (1U)
#define CONNECT_PMU_GPO_5_VAL (1U)
#define SECURE_ACCESS_VAL (0U)
#define USE_DDR_FOR_APU_RESTART_VAL (1U)
#define ENABLE_RPU_RUN_MODE_VAL (0U)
/*
* XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT
* Default watchdog timeout
*
* XPFW_CFG_PMU_FPGA_WDT_TIMEOUT
* This watchdog timeout is applied during bitstream download, provided
* its value is greater than XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT
*
* XPFW_CFG_PMU_SHA3_WDT_TIMEOUT
* This watchdog timeout is applied during SHA3 request, provided
* its value is greater than XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT
*
* XPFW_CFG_PMU_RSA_WDT_TIMEOUT
* This watchdog timeout is applied during RSA request, provided
* its value is greater than XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT
*
* XPFW_CFG_PMU_AES_WDT_TIMEOUT
* This watchdog timeout is applied during AES request, provided
* its value is greater than XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT
*
* XPFW_CFG_PMU_SECURE_IMAGE_WDT_TIMEOUT
* This watchdog timeout is applied during secure image download, provided
* its value is greater than XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT
*
*/
#define XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT (90U) /* ms */
#define XPFW_CFG_PMU_FPGA_WDT_TIMEOUT (500U) /* ms */
#define XPFW_CFG_PMU_SHA3_WDT_TIMEOUT (500U) /* ms */
#define XPFW_CFG_PMU_RSA_WDT_TIMEOUT (500U) /* ms */
#define XPFW_CFG_PMU_AES_WDT_TIMEOUT (500U) /* ms */
#define XPFW_CFG_PMU_SECURE_IMG_LOAD_WDT_TIMEOUT (500U) /* ms */
#if ENABLE_PM_VAL
#define ENABLE_PM
#endif
#if ENABLE_EM_VAL
#define ENABLE_EM
#endif
#if ENABLE_SCHEDULER_VAL
#define ENABLE_SCHEDULER
#endif
#if ENABLE_MOD_ULTRA96_VAL
#define ENABLE_MOD_ULTRA96
#endif
#if ENABLE_RECOVERY_VAL
#define ENABLE_RECOVERY
#endif
#if ENABLE_RECOVERY_RESET_SYSTEM_VAL
#define ENABLE_RECOVERY_RESET_SYSTEM
#endif
#if ENABLE_RECOVERY_RESET_PS_ONLY_VAL
#define ENABLE_RECOVERY_RESET_PS_ONLY
#endif
#if ENABLE_ESCALATION_VAL
#define ENABLE_ESCALATION
#endif
#if CHECK_HEALTHY_BOOT_VAL
#define CHECK_HEALTHY_BOOT
#endif
#if ENABLE_WDT_VAL
#define ENABLE_WDT
#endif
#if ENABLE_CUSTOM_MOD_VAL
#define ENABLE_CUSTOM_MOD
#endif
#if ENABLE_STL_VAL
#define ENABLE_STL
#endif
#if ENABLE_RTC_TEST_VAL
#define ENABLE_RTC_TEST
#endif
#if ENABLE_RPU_RUN_MODE_VAL
#define ENABLE_RPU_RUN_MODE
#endif
#if ENABLE_FPGA_LOAD_VAL
#define ENABLE_FPGA_LOAD
#endif
#if ENABLE_FPGA_READ_CONFIG_DATA_VAL
#define ENABLE_FPGA_READ_CONFIG_DATA
#endif
#if ENABLE_FPGA_READ_CONFIG_REG_VAL
#define ENABLE_FPGA_READ_CONFIG_REG
#endif
#if ENABLE_SECURE_VAL
#define ENABLE_SECURE
#endif
#if ENABLE_IPI_CRC_VAL
#define ENABLE_IPI_CRC
#endif
#if XPU_INTR_DEBUG_PRINT_ENABLE_VAL
#define XPU_INTR_DEBUG_PRINT_ENABLE
#endif
#if PM_LOG_LEVEL_VAL > 0
#define PM_LOG_LEVEL PM_LOG_LEVEL_VAL
#endif
#if IDLE_PERIPHERALS_VAL
#define IDLE_PERIPHERALS
#endif
#if ENABLE_NODE_IDLING_VAL
#define ENABLE_NODE_IDLING
#endif
#if DEBUG_MODE_VAL
#define DEBUG_MODE
#endif
#ifdef XPAR_PSU_DDRC_0_DEVICE_ID
#if ENABLE_POS_VAL
#define ENABLE_POS
#endif
#else
#ifdef ENABLE_POS
#error "Error: POS feature is not supported in DDR less design"
#endif
#endif
#ifdef XPAR_PSU_DDRC_0_DEVICE_ID
#if ENABLE_DDR_SR_WR_VAL
#define ENABLE_DDR_SR_WR
#endif
#else
#ifdef ENABLE_DDR_SR_WR
#error "Error: DDR_SR_WR feature is not supported in DDR less design"
#endif
#endif
#if DISABLE_CLK_PERMS_VAL
#define DISABLE_CLK_PERMS
#endif
#if ENABLE_UNUSED_RPU_PWR_DWN_VAL
#define ENABLE_UNUSED_RPU_PWR_DWN
#endif
#if PMU_MIO_INPUT_PIN_VAL
#define PMU_MIO_INPUT_PIN 0U
#endif
#if BOARD_SHUTDOWN_PIN_VAL
#define BOARD_SHUTDOWN_PIN 2U
#endif
#if BOARD_SHUTDOWN_PIN_STATE_VAL
#define BOARD_SHUTDOWN_PIN_STATE 0U
#endif
#if SECURE_ACCESS_VAL
#define SECURE_ACCESS
#endif
#if ENABLE_EFUSE_ACCESS
#define EFUSE_ACCESS
#endif
/* FPD WDT recovery action */
#ifdef ENABLE_RECOVERY
#define SWDT_EM_ACTION EM_ACTION_CUSTOM
#else
#define SWDT_EM_ACTION EM_ACTION_SRST
#endif
#ifdef ENABLE_POS
#define ENABLE_POS_QSPI
#endif
#if CONNECT_PMU_GPO_2_VAL
#define CONNECT_PMU_GPO_2
#endif
#if CONNECT_PMU_GPO_3_VAL
#define CONNECT_PMU_GPO_3
#endif
#if CONNECT_PMU_GPO_4_VAL
#define CONNECT_PMU_GPO_4
#endif
#if CONNECT_PMU_GPO_5_VAL
#define CONNECT_PMU_GPO_5
#endif
#if USE_DDR_FOR_APU_RESTART_VAL
#define USE_DDR_FOR_APU_RESTART
#endif
#ifdef __cplusplus
}
#endif
#endif /* XPFW_CONFIG_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_core.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_default.h"
#include "xpfw_core.h"
#include "xpfw_events.h"
#include "xpfw_interrupts.h"
#include "xpfw_ipi_manager.h"
#include "pmu_lmb_bram.h"
#include "xsysmonpsu_hw.h"
#include "csu.h"
#include "rsa.h"
#include "crf_apb.h"
#include "afi.h"
#include "pm_node_idle.h"
#include "pm_csudma.h"
#include "pm_qspi.h"
#define CORE_IS_READY ((u16)0x5AFEU)
#define CORE_IS_DEAD ((u16)0xDEADU)
static XPfw_Core_t XPfwCore = { .IsReady = CORE_IS_DEAD };
/* Declare the Core Pointer as constant, since we don't intend to change it */
static XPfw_Core_t * const CorePtr = &XPfwCore;
XStatus XPfw_CoreInit(u32 Options)
{
u32 Index;
XStatus Status;
if (CorePtr == NULL) {
Status = XST_FAILURE;
goto Done;
}
XPfw_InterruptInit();
/* Clear the DONT_SLEEP bit */
XPfw_RMW32(PMU_GLOBAL_GLOBAL_CNTRL,
PMU_GLOBAL_GLOBAL_CNTRL_DONT_SLEEP_MASK, 0U);
CorePtr->ModCount = (u8)0U;
for (Index = 0U; Index < ARRAYSIZE(CorePtr->ModList); Index++) {
Status = XPfw_ModuleInit(&CorePtr->ModList[Index], (u8) 0U);
/* If there was an error, then just get out of here */
if (XST_SUCCESS != Status) {
goto Done;
}
}
Status = XPfw_SchedulerInit(&CorePtr->Scheduler,
PMU_IOMODULE_PIT1_PRELOAD);
if (XST_SUCCESS != Status) {
goto Done;
}
Status = XPfw_IpiManagerInit();
Done:
return Status;
}
XStatus XPfw_CoreConfigure(void)
{
u32 Idx;
XStatus Status;
if (CorePtr != NULL) {
for (Idx = 0U; Idx < CorePtr->ModCount; Idx++) {
if (CorePtr->ModList[Idx].CfgInitHandler != NULL) {
CorePtr->ModList[Idx].CfgInitHandler(&CorePtr->ModList[Idx],
NULL, 0U);
}
}
/* We are ready to take interrupts now */
CorePtr->IsReady = CORE_IS_READY;
/* Clear IPI0 status and Enable IPI0 */
XPfw_Write32(IPI_PMU_0_ISR, MASK32_ALL_HIGH);
XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_IPI0_MASK);
/* Enable slave error for peripherals used by PMU */
XPfw_EnableSlvErr();
/* Clear PMU LMB BRAM ECC status and Enable this interrupt */
XPfw_Write32(PMU_LMB_BRAM_ECC_STATUS_REG, PMU_LMB_BRAM_CE_MASK);
XPfw_Write32(PMU_LMB_BRAM_ECC_IRQ_EN_REG, PMU_LMB_BRAM_CE_MASK);
XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_CORRECTABLE_ECC_MASK);
XPfw_InterruptStart();
/* Set the FW_IS_PRESENT bit to flag that PMUFW is up and ready */
XPfw_RMW32(PMU_GLOBAL_GLOBAL_CNTRL, PMU_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_MASK,
PMU_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_MASK);
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
return Status;
}
void XPfw_EnableSlvErr(void)
{
#ifdef ENABLE_NODE_IDLING
#if defined XPAR_PSU_GDMA_0_DEVICE_ID || \
defined XPAR_PSU_ADMA_0_DEVICE_ID
u32 XZdma_BaseAddr;
u8 Channel;
#endif
#endif
/* Enable SLVERR for IPI */
XPfw_Write32(IPI_CTRL, SLVERR_MASK);
/*Enable SLVERR for IOU SLCR */
XPfw_Write32(IOU_SLCR_CTRL, SLVERR_MASK);
/* Enable SLVERR for PMU GLOBAL registers */
XPfw_RMW32(PMU_GLOBAL_GLOBAL_CNTRL, PMU_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_MASK,
PMU_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_MASK);
/* Enable SLVERR for AMS */
XPfw_RMW32(XSYSMONPSU_BASEADDR, XSYSMONPSU_MISC_SLVERR_EN_MASK,
XSYSMONPSU_MISC_SLVERR_EN_MASK);
/* Enable SLVERR for CRL_APB */
XPfw_Write32(CRL_APB_BASEADDR, CRL_APB_ERR_CTRL_SLVERR_ENABLE_MASK);
/* Enable SLVERR for CSU_CTRL */
XPfw_RMW32(CSU_CTRL, CSU_CTRL_SLVERR_ENABLE_MASK,
CSU_CTRL_SLVERR_ENABLE_MASK);
/* Enable SLVERR for LPD_SLCR */
XPfw_Write32(LPD_SLCR_CTRL, LPD_SLCR_CTRL_SLVERR_ENABLE_MASK);
/* Enable SLVERR for RSA */
XPfw_RMW32(RSA_RSA_CFG, RSA_RSA_CFG_SLVERR_EN_MASK,
RSA_RSA_CFG_SLVERR_EN_MASK);
/* Enable SLVERR for CRF_APB */
XPfw_Write32(CRF_APB_ERR_CTRL, CRF_APB_ERR_CTRL_SLVERR_ENABLE_MASK);
/* Enable SLVERR for FPD SLCR */
XPfw_Write32(FPD_SLCR_CTRL, SLVERR_MASK);
/* Enable SLVERR for XPPU_SINK */
XPfw_Write32(XPPU_SINK_ERR_CTRL, SLVERR_MASK);
/* Enable SLVERR for BBRAM */
XPfw_Write32(BBRAM_SLVERR_REG, SLVERR_MASK);
#ifdef ENABLE_NODE_IDLING
#ifdef XPAR_XDPPSU_0_DEVICE_ID
#ifdef XPAR_XDPDMA_0_DEVICE_ID
/* Enable SLVERR */
XPfw_Write32(XPAR_XDPPSU_0_BASEADDR, SLVERR_MASK);
#endif
#endif
#ifdef XPAR_PSU_GDMA_0_DEVICE_ID
XZdma_BaseAddr = XPAR_PSU_GDMA_0_BASEADDR;
for (Channel = 0; Channel < XZDMA_NUM_CHANNEL; Channel++) {
/* Enable SLVERR */
XPfw_Write32(XZdma_BaseAddr, SLVERR_MASK);
XZdma_BaseAddr += XZDMA_CH_OFFSET;
}
#endif
#ifdef XPAR_PSU_ADMA_0_DEVICE_ID
XZdma_BaseAddr = XPAR_PSU_ADMA_0_BASEADDR;
for (Channel = 0; Channel < XZDMA_NUM_CHANNEL; Channel++) {
/* Enable SLVERR */
XPfw_Write32(XZdma_BaseAddr, SLVERR_MASK);
XZdma_BaseAddr += XZDMA_CH_OFFSET;
}
#endif
#endif
/* Enable SLVERR for CSUDMA */
XPfw_RMW32(CSUDMA_SRC_CTRL, CSUDMA_APB_ERR_RESP_MASK,
CSUDMA_APB_ERR_RESP_MASK);
XPfw_RMW32(CSUDMA_DEST_CTRL, CSUDMA_APB_ERR_RESP_MASK,
CSUDMA_APB_ERR_RESP_MASK);
#if defined ENABLE_POS_QSPI || \
defined XPAR_PSU_QSPI_0_DEVICE_ID
/* Enable SLVERR */
XPfw_RMW32(QSPIDMA_DST_CTRL, XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK,
XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK);
#endif
}
XStatus XPfw_CoreDispatchEvent(u32 EventId)
{
XStatus Status;
u32 Idx;
u32 CallCount = 0U;
if ((CorePtr != NULL) && (EventId < XPFW_EV_MAX)) {
for (Idx = 0U; Idx < CorePtr->ModCount; Idx++) {
/**
* Check if Mod[Idx] and event handler are registered for this event
*/
if (((XPfw_EventGetModMask(EventId) & ((u32) 1U << Idx))
== ((u32) 1U << Idx)) && CorePtr->ModList[Idx].EventHandler != NULL) {
CorePtr->ModList[Idx].EventHandler(&CorePtr->ModList[Idx],
EventId);
CallCount++;
}
}
}
/* XPfw_Printf(DEBUG_INFO,"%s: Event(%d) dispatched to %d Mods\r\n",
* __func__, EventId,CallCount); */
if (CallCount > 0U) {
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
return Status;
}
XStatus XPfw_CoreDispatchIpi(u32 IpiNum, u32 SrcMask)
{
XStatus Status;
u32 Idx;
u32 MaskIndex;
u32 CallCount = 0U;
u32 Payload[XPFW_IPI_MAX_MSG_LEN] = {0U};
if ((CorePtr == NULL) || (IpiNum > 3U)) {
Status = XST_FAILURE;
goto Done;
}
/* For each of the IPI sources */
for (MaskIndex = 0U; MaskIndex < XPFW_IPI_MASK_COUNT; MaskIndex++) {
/* Check if the Mask is set */
if ((SrcMask & IpiMaskList[MaskIndex]) != 0U) {
/* If set, read the message into buffer */
Status = XPfw_IpiReadMessage(IpiMaskList[MaskIndex],
&Payload[0], XPFW_IPI_MAX_MSG_LEN);
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_ERROR, "IPI payload read error\r\n");
goto Done;
}
/* Dispatch based on IPI ID (MSB 16 bits of Word-0) of the module */
for (Idx = 0U; Idx < CorePtr->ModCount; Idx++) {
/* If API ID matches and IpiHandler is set */
if ( (CorePtr->ModList[Idx].IpiId == (Payload[0] >> 16U)) &&
(CorePtr->ModList[Idx].IpiHandler != NULL)) {
/* Call the module's IPI handler */
CorePtr->ModList[Idx].IpiHandler(&CorePtr->ModList[Idx],
IpiNum, IpiMaskList[MaskIndex],
&Payload[0], XPFW_IPI_MAX_MSG_LEN);
CallCount++;
}
}
}
}
if (CallCount > 0U) {
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
Done:
return Status;
}
const XPfw_Module_t *XPfw_CoreCreateMod(void)
{
const XPfw_Module_t *ModPtr;
if (CorePtr != NULL) {
if (CorePtr->ModCount < XPFW_MAX_MOD_COUNT) {
CorePtr->ModList[CorePtr->ModCount].ModId = CorePtr->ModCount;
ModPtr = &CorePtr->ModList[CorePtr->ModCount];
CorePtr->ModCount++;
} else {
ModPtr = NULL;
}
} else {
ModPtr = NULL;
}
return ModPtr;
}
XStatus XPfw_CoreScheduleTask(const XPfw_Module_t *ModPtr, u32 Interval,
VoidFunction_t CallbackRef)
{
XStatus Status;
if ((ModPtr != NULL) && (CorePtr != NULL)) {
Status = XPfw_SchedulerAddTask(&CorePtr->Scheduler, ModPtr->ModId,
Interval, CallbackRef);
} else {
Status = XST_FAILURE;
}
return Status;
}
s32 XPfw_CoreRemoveTask(const XPfw_Module_t *ModPtr, u32 Interval,
VoidFunction_t CallbackRef)
{
s32 Status;
if ((ModPtr == NULL) || (CorePtr == NULL)) {
Status = XST_FAILURE;
goto Done;
}
Status = XPfw_SchedulerRemoveTask(&CorePtr->Scheduler, ModPtr->ModId,
Interval, CallbackRef);
Done:
return Status;
}
void XPfw_CoreTickHandler(void)
{
if(CorePtr != NULL){
XPfw_SchedulerTickHandler(&CorePtr->Scheduler);
}
else {
XPfw_Printf(DEBUG_ERROR,"ERROR: NULL pointer to Core\r\n");
}
}
XStatus XPfw_CoreIsReady(void)
{
XStatus Status;
if (CorePtr != NULL) {
if (CORE_IS_READY == CorePtr->IsReady) {
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
} else {
Status = XST_FAILURE;
}
return Status;
}
XStatus XPfw_CoreLoop(void)
{
if(CORE_IS_READY == CorePtr->IsReady)
{
#ifdef ENABLE_SCHEDULER
if(XPfw_SchedulerStart(&CorePtr->Scheduler) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,"Warning: Scheduler has failed to"
"Start\r\n");
} else {
XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_PIT1_MASK);
}
#endif
do {
#ifdef SLEEP_WHEN_IDLE
/*Sleep. Will be waken up when a interrupt occurs*/
mb_sleep();
#endif
#ifdef ENABLE_SCHEDULER
if(TRUE == CorePtr->Scheduler.Enabled){
XPfw_SchedulerProcess(&CorePtr->Scheduler);
}
#endif
} while (1);
}
/* If we reach this point then there was an error */
return (XStatus)XST_FAILURE;
}
void XPfw_CorePrintStats(void)
{
if(CorePtr != NULL) {
XPfw_Printf(DEBUG_DETAILED,
"######################################################\r\n");
XPfw_Printf(DEBUG_DETAILED,"Module Count: %d (%d)\r\n", CorePtr->ModCount,
XPFW_MAX_MOD_COUNT);
XPfw_Printf(DEBUG_DETAILED,"Scheduler State: %s\r\n",
((CorePtr->Scheduler.Enabled == TRUE)?"ENABLED":"DISABLED"));
XPfw_Printf(DEBUG_DETAILED,"Scheduler Ticks: %lu\r\n",
CorePtr->Scheduler.Tick);
XPfw_Printf(DEBUG_DETAILED,
"######################################################\r\n");
}
}
XStatus XPfw_CoreRegisterEvent(const XPfw_Module_t *ModPtr, u32 EventId)
{
XStatus Status;
if (NULL == ModPtr) {
Status = XST_FAILURE;
} else {
Status = XPfw_EventAddOwner(ModPtr->ModId, EventId);
}
return Status;
}
XStatus XPfw_CoreDeRegisterEvent(const XPfw_Module_t *ModPtr, u32 EventId)
{
XStatus Status;
if (NULL == ModPtr) {
Status = XST_FAILURE;
} else {
Status = XPfw_EventRemoveOwner(ModPtr->ModId, EventId);
}
return Status;
}
XStatus XPfw_CoreStopScheduler(void)
{
XStatus Status;
if(CorePtr != NULL) {
Status = XPfw_SchedulerStop(&CorePtr->Scheduler);
XPfw_InterruptDisable(PMU_IOMODULE_IRQ_ENABLE_PIT1_MASK);
} else {
Status = XST_FAILURE;
}
return Status;
}
XStatus XPfw_CoreSetCfgHandler(const XPfw_Module_t *ModPtr, XPfwModCfgInitHandler_t CfgHandler)
{
XStatus Status;
if ((ModPtr != NULL) && (CorePtr != NULL)) {
if (ModPtr->ModId < CorePtr->ModCount) {
CorePtr->ModList[ModPtr->ModId].CfgInitHandler = CfgHandler;
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
} else {
Status = XST_FAILURE;
}
return Status;
}
XStatus XPfw_CoreSetEventHandler(const XPfw_Module_t *ModPtr, XPfwModEventHandler_t EventHandlerFn)
{
XStatus Status;
if ((ModPtr != NULL) && (CorePtr != NULL)) {
if (ModPtr->ModId < CorePtr->ModCount) {
CorePtr->ModList[ModPtr->ModId].EventHandler = EventHandlerFn;
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
} else {
Status = XST_FAILURE;
}
return Status;
}
XStatus XPfw_CoreSetIpiHandler(const XPfw_Module_t *ModPtr, XPfwModIpiHandler_t IpiHandlerFn, u16 IpiId)
{
XStatus Status;
if ((ModPtr != NULL) && (CorePtr != NULL)) {
if (ModPtr->ModId < CorePtr->ModCount) {
CorePtr->ModList[ModPtr->ModId].IpiHandler = IpiHandlerFn;
CorePtr->ModList[ModPtr->ModId].IpiId = IpiId;
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
} else {
Status = XST_FAILURE;
}
return Status;
}
void XPfw_Exception_Handler(void)
{
XPfw_Printf(DEBUG_PRINT_ALWAYS, "Received exception\r\n"
"MSR: 0x%x, EAR: 0x%x, EDR: 0x%x, ESR: 0x%x\r\n",
mfmsr(), mfear(), mfedr(), mfesr());
/* Write error occurrence to PERS register and trigger FW Error1 */
XPfw_RMW32(PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5, HW_EXCEPTION_RECEIVED,
HW_EXCEPTION_RECEIVED);
XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK);
XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
0x0U);
while(1);
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pldomain.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_common.h"
#include "xpm_pldomain.h"
#include "xpm_device.h"
#include "xpm_domain_iso.h"
#include "xpm_regs.h"
#include "xpm_reset.h"
#include "xpm_bisr.h"
#include "xpm_pmc.h"
#include "xparameters.h"
#include "sleep.h"
#define XPM_NODEIDX_DEV_GT_MIN XPM_NODEIDX_DEV_GT_0
#define XPM_NODEIDX_DEV_GT_MAX XPM_NODEIDX_DEV_GT_10
#define XPM_NODEIDX_DEV_GTM_MIN XPM_NODEIDX_DEV_GTM_0
#define XPM_NODEIDX_DEV_GTM_MAX XPM_NODEIDX_DEV_GTM_4
#define XPM_NODEIDX_DEV_GTYP_MIN XPM_NODEIDX_DEV_GTYP_0
#define XPM_NODEIDX_DEV_GTYP_MAX XPM_NODEIDX_DEV_GTYP_2
#define PLHCLEAN_EARLY_BOOT 0U
#define PLHCLEAN_INIT_NODE 1U
//If TRIM_CRAM[31:0]=0 (FUSE not programmed). Then set rw_read_voltages to 0.61V + 0.625V
#define CRAM_TRIM_RW_READ_VOLTAGE 0x0600019FU
static XCframe CframeIns={0}; /* CFRAME Driver Instance */
static XCfupmc CfupmcIns={0}; /* CFU Driver Instance */
static u32 PlpdHouseCleanBypass = 0;
u32 HcleanDone = 0;
static XStatus PldInitFinish(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_SUCCESS;
(void)Args;
(void)NumOfArgs;
return Status;
}
static XStatus PldGtyMbist(u32 BaseAddress)
{
XStatus Status = XST_FAILURE;
PmOut32(BaseAddress + GTY_PCSR_MASK_OFFSET, GTY_PCSR_MEM_CLEAR_TRIGGER_MASK);
PmOut32(BaseAddress + GTY_PCSR_CONTROL_OFFSET, GTY_PCSR_MEM_CLEAR_TRIGGER_MASK);
Status = XPm_PollForMask(BaseAddress + GTY_PCSR_STATUS_OFFSET, GTY_PCSR_STATUS_MEM_CLEAR_DONE_MASK, XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_PollForMask(BaseAddress + GTY_PCSR_STATUS_OFFSET, GTY_PCSR_STATUS_MEM_CLEAR_PASS_MASK, XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Unwrite trigger bits */
PmOut32(BaseAddress + GTY_PCSR_MASK_OFFSET, GTY_PCSR_MEM_CLEAR_TRIGGER_MASK);
PmOut32(BaseAddress + GTY_PCSR_CONTROL_OFFSET, 0);
done:
return Status;
}
static void PldApplyTrim(u32 TrimType)
{
u32 TrimVal;
Xuint128 VggTrim={0};
XPm_Device *EfuseCache = XPmDevice_GetById(PM_DEV_EFUSE_CACHE);
if (NULL == EfuseCache) {
goto done;
}
/* Read the corresponding efuse registers for TRIM values */
switch (TrimType)
{
/* Read VGG trim efuse registers */
case XPM_PL_TRIM_VGG:
{
PmIn32(EfuseCache->Node.BaseAddress + EFUSE_CACHE_TRIM_CFRM_VGG_0_OFFSET,
VggTrim.Word0);
PmIn32(EfuseCache->Node.BaseAddress + EFUSE_CACHE_TRIM_CFRM_VGG_1_OFFSET,
VggTrim.Word1);
PmIn32(EfuseCache->Node.BaseAddress + EFUSE_CACHE_TRIM_CFRM_VGG_2_OFFSET,
VggTrim.Word2);
XCframe_VggTrim(&CframeIns, &VggTrim);
}
break;
/* Read CRAM trim efuse registers */
case XPM_PL_TRIM_CRAM:
{
PmIn32(EfuseCache->Node.BaseAddress + EFUSE_CACHE_TRIM_CRAM_OFFSET,
TrimVal);
/* if eFUSE is not programmed,
then set rw_read_voltages to 0.61V + 0.625V by writing */
if ((TrimVal == 0U) && (PLATFORM_VERSION_SILICON == Platform) && (PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
TrimVal = CRAM_TRIM_RW_READ_VOLTAGE;
}
XCframe_CramTrim(&CframeIns, TrimVal);
}
break;
/* Read BRAM trim efuse registers */
case XPM_PL_TRIM_BRAM:
{
PmIn32(EfuseCache->Node.BaseAddress + EFUSE_CACHE_TRIM_BRAM_OFFSET,
TrimVal);
XCframe_BramTrim(&CframeIns, TrimVal);
}
break;
/* Read URAM trim efuse registers */
case XPM_PL_TRIM_URAM:
{
PmIn32(EfuseCache->Node.BaseAddress + EFUSE_CACHE_TRIM_URAM_OFFSET,
TrimVal);
XCframe_UramTrim(&CframeIns, TrimVal);
}
break;
default:
{
/* Added due to MISRA */
PmDbg("[%d] Default case in switch\r\n", __LINE__);
break;
}
}
done:
return;
}
static void PldCfuLock(XPm_PlDomain *Pld, u32 Enable)
{
static u32 PrevLockState=1U;
if (1U == Enable) {
/* Lock CFU writes */
PmOut32(Pld->CfuApbBaseAddr + CFU_APB_CFU_PROTECT_OFFSET, PrevLockState);
} else {
PmIn32(Pld->CfuApbBaseAddr + CFU_APB_CFU_PROTECT_OFFSET, PrevLockState);
/* Unlock CFU writes */
PmOut32(Pld->CfuApbBaseAddr + CFU_APB_CFU_PROTECT_OFFSET, 0);
}
return;
}
static XStatus PldCfuInit(void)
{
XStatus Status = XST_FAILURE;
XCfupmc_Config *Config;
if (0U != CfupmcIns.IsReady) {
Status = XST_SUCCESS;
goto done;
}
/*
* Initialize the CFU driver so that it's ready to use
* look up the configuration in the config table,
* then initialize it.
*/
Config = XCfupmc_LookupConfig((u16)XPAR_XCFUPMC_0_DEVICE_ID);
if (NULL == Config) {
Status = XST_FAILURE;
goto done;
}
Status = XCfupmc_CfgInitialize(&CfupmcIns, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
goto done;
}
/*
* Performs the self-test to check hardware build.
*/
Status = XCfupmc_SelfTest(&CfupmcIns);
if (Status != XST_SUCCESS) {
goto done;
}
done:
return Status;
}
static XStatus PldCframeInit(void)
{
XStatus Status = XST_FAILURE;
XCframe_Config *Config;
if (0U != CframeIns.IsReady) {
Status = XST_SUCCESS;
goto done;
}
/*
* Initialize the Cframe driver so that it's ready to use
* look up the configuration in the config table,
* then initialize it.
*/
Config = XCframe_LookupConfig((u16)XPAR_XCFRAME_0_DEVICE_ID);
if (NULL == Config) {
Status = XST_FAILURE;
goto done;
}
Status = XCframe_CfgInitialize(&CframeIns, Config, Config->BaseAddress);
if (XST_SUCCESS != Status) {
goto done;
}
/*
* Performs the self-test to check hardware build.
*/
Status = XCframe_SelfTest(&CframeIns);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
static XStatus GtyHouseClean(void)
{
XStatus Status = XPM_ERR_HC_PL;
unsigned int i;
XPm_Device *Device;
u32 GtyAddresses[XPM_NODEIDX_DEV_GT_MAX - XPM_NODEIDX_DEV_GT_MIN + 1 +
XPM_NODEIDX_DEV_GTM_MAX - XPM_NODEIDX_DEV_GTM_MIN + 1 +
XPM_NODEIDX_DEV_GTYP_MAX - XPM_NODEIDX_DEV_GTYP_MIN + 1] = {0};
u32 GtySize = (u32)XPM_NODEIDX_DEV_GT_MAX - (u32)XPM_NODEIDX_DEV_GT_MIN + 1U;
u32 GtmSize = (u32)XPM_NODEIDX_DEV_GTM_MAX - (u32)XPM_NODEIDX_DEV_GTM_MIN + 1U;
u32 GtypSize = (u32)XPM_NODEIDX_DEV_GTYP_MAX - (u32)XPM_NODEIDX_DEV_GTYP_MIN + 1U;
/* Store GTY Addresses */
for (i = 0; i < GtySize; i++) {
Device = XPmDevice_GetByIndex((u32)XPM_NODEIDX_DEV_GT_MIN + i);
if (NULL != Device) {
GtyAddresses[i] = Device->Node.BaseAddress;
}
}
/* Store GTM Addresses */
for (i = 0; i < GtmSize; i++) {
Device = XPmDevice_GetByIndex((u32)XPM_NODEIDX_DEV_GTM_MIN + i);
if (NULL != Device) {
GtyAddresses[i + GtySize] = Device->Node.BaseAddress;
}
}
/* Store GTYP Addresses */
for (i = 0; i < GtypSize; i++) {
Device = XPmDevice_GetByIndex((u32)XPM_NODEIDX_DEV_GTYP_MIN + i);
if (NULL != Device) {
GtyAddresses[i + GtySize + GtmSize] = Device->Node.BaseAddress;
}
}
for (i = 0; i < ARRAY_SIZE(GtyAddresses) && (0U != GtyAddresses[i]); i++) {
PmOut32(GtyAddresses[i] + GTY_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
/* Deassert INITCTRL */
PmOut32(GtyAddresses[i] + GTY_PCSR_MASK_OFFSET,
GTY_PCSR_INITCTRL_MASK);
PmOut32(GtyAddresses[i] + GTY_PCSR_CONTROL_OFFSET, 0);
PmOut32(GtyAddresses[i] + GTY_PCSR_LOCK_OFFSET, 1);
}
if (0U == PlpdHouseCleanBypass) {
/* Bisr repair - Bisr should be triggered only for Addresses for which repair
* data is found and so not calling in loop. Trigger is handled in below routine
* */
Status = XPmBisr_Repair(GTY_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmBisr_Repair(GTM_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmBisr_Repair(GTYP_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
for (i = 0; i < ARRAY_SIZE(GtyAddresses) && (0U != GtyAddresses[i]); i++) {
PmOut32(GtyAddresses[i] + GTY_PCSR_LOCK_OFFSET,
PCSR_UNLOCK_VAL);
/* Mbist */
Status = PldGtyMbist(GtyAddresses[i]);
if (XST_SUCCESS != Status) {
/* Gt Mem clear is found to be failing on some parts.
Just print message and return not to break execution */
PmInfo("ERROR: GT Mem clear Failed\r\n");
Status = XST_SUCCESS;
PmOut32(GtyAddresses[i] + GTY_PCSR_LOCK_OFFSET, 1);
goto done;
}
PmOut32(GtyAddresses[i] + GTY_PCSR_LOCK_OFFSET, 1);
}
}
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus PlHouseClean(u32 TriggerTime)
{
XStatus Status = XST_FAILURE;
XPm_PlDomain *Pld;
u32 Value;
if (PLHCLEAN_EARLY_BOOT == TriggerTime) {
/* Enable ROWON */
XCframe_WriteCmd(&CframeIns, XCFRAME_FRAME_BCAST,
XCFRAME_CMD_REG_ROWON);
/* HCLEANR type 3,4,5,6 */
XCframe_WriteCmd(&CframeIns, XCFRAME_FRAME_BCAST,
XCFRAME_CMD_REG_HCLEANR);
/* HB BISR REPAIR */
Status = XPmBisr_Repair(DCMAC_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmBisr_Repair(ILKN_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmBisr_Repair(MRMAC_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmBisr_Repair(SDFEC_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
/* BRAM/URAM repair */
Status = XPmBisr_Repair(BRAM_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmBisr_Repair(URAM_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
/* HCLEAN type 0,1,2 */
XCframe_WriteCmd(&CframeIns, XCFRAME_FRAME_BCAST,
XCFRAME_CMD_REG_HCLEAN);
} else {
Pld = (XPm_PlDomain *)XPmPower_GetById(PM_POWER_PLD);
if (NULL == Pld) {
goto done;
}
/* Poll for house clean completion */
XPlmi_Printf(DEBUG_INFO, "INFO: %s : Waiitng for PL HC complete....", __func__);
while ((XPm_In32(Pld->CfuApbBaseAddr + CFU_APB_CFU_STATUS_OFFSET) &
(u32)CFU_APB_CFU_STATUS_HC_COMPLETE_MASK) !=
(u32)CFU_APB_CFU_STATUS_HC_COMPLETE_MASK) {};
XPlmi_Printf(DEBUG_INFO, "Done\r\n");
/* VGG TRIM */
PldApplyTrim(XPM_PL_TRIM_VGG);
/* CRAM TRIM */
PldApplyTrim(XPM_PL_TRIM_CRAM);
/* BRAM/URAM TRIM */
PldApplyTrim(XPM_PL_TRIM_BRAM);
PldApplyTrim(XPM_PL_TRIM_URAM);
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
/* LAGUNA REPAIR - not needed for now */
/* There is no status for Bisr done in hard ip. But we must ensure
* BISR is complete before scan clear */
/*TBD - Wait for how long?? Wei to confirm with DFT guys */
/* Fake read */
/* each register is 128 bits long so issue 4 reads */
XPlmi_Printf(DEBUG_INFO, "INFO: %s : CFRAME Fake Read...", __func__);
PmIn32(Pld->Cframe0RegBaseAddr + 0U, Value);
PmIn32(Pld->Cframe0RegBaseAddr + 4U, Value);
PmIn32(Pld->Cframe0RegBaseAddr + 8U, Value);
PmIn32(Pld->Cframe0RegBaseAddr + 12U, Value);
XPlmi_Printf(DEBUG_INFO, "Done\r\n");
/* PL scan clear / MBIST */
PmOut32(Pld->CfuApbBaseAddr + CFU_APB_CFU_MASK_OFFSET,
CFU_APB_CFU_FGCR_SC_HBC_TRIGGER_MASK);
PmOut32(Pld->CfuApbBaseAddr + CFU_APB_CFU_FGCR_OFFSET,
CFU_APB_CFU_FGCR_SC_HBC_TRIGGER_MASK);
/* Poll for status */
XPlmi_Printf(DEBUG_INFO, "INFO: %s : Wait for Hard Block Scan Clear / MBIST complete...", __func__);
Status = XPm_PollForMask(Pld->CfuApbBaseAddr + CFU_APB_CFU_STATUS_OFFSET,
CFU_APB_CFU_STATUS_SCAN_CLEAR_DONE_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
XPlmi_Printf(DEBUG_INFO, "ERROR\r\n");
/** HACK: Continuing even if CFI SC is not completed for ES1 */
if ((PLATFORM_VERSION_SILICON == Platform) && (PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
Status = XST_SUCCESS;
} else {
goto done;
}
}
else {
XPlmi_Printf(DEBUG_INFO, "Done\r\n");
}
/* Check if Scan Clear Passed */
if ((XPm_In32(Pld->CfuApbBaseAddr + CFU_APB_CFU_STATUS_OFFSET) &
(u32)CFU_APB_CFU_STATUS_SCAN_CLEAR_PASS_MASK) !=
(u32)CFU_APB_CFU_STATUS_SCAN_CLEAR_PASS_MASK) {
XPlmi_Printf(DEBUG_GENERAL, "ERROR: %s: Hard Block Scan Clear / MBIST FAILED\r\n", __func__);
/** HACK: Continuing even if CFI SC is not pass for ES1 */
if ((PLATFORM_VERSION_SILICON == Platform) && (PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
Status = XST_SUCCESS;
} else {
goto done;
}
}
/* Unwrite trigger bits for PL scan clear / MBIST */
PmOut32(Pld->CfuApbBaseAddr + CFU_APB_CFU_MASK_OFFSET,
CFU_APB_CFU_FGCR_SC_HBC_TRIGGER_MASK);
PmOut32(Pld->CfuApbBaseAddr + CFU_APB_CFU_FGCR_OFFSET, 0);
}
/* Compilation warning fix */
(void)Value;
done:
return Status;
}
static XStatus PldInitStart(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
XPm_PlDomain *Pld;
u32 PlPowerUpTime=0;
(void)Args;
(void)NumOfArgs;
/* If PL power is still not up, return error as PLD cant
be initialized */
if (1U != HcleanDone) {
/* Check if vccint, vccaux, vccint_ram is 1 */
while (XST_SUCCESS != XPmPower_CheckPower(PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_PL_MASK |
PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_RAM_MASK |
PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_MASK)) {
/** Wait for PL power up */
usleep(10);
PlPowerUpTime++;
if (PlPowerUpTime > XPM_POLL_TIMEOUT)
{
XPlmi_Printf(DEBUG_GENERAL, "ERROR: PL Power Up TimeOut\n\r");
Status = XST_FAILURE;
/* TODO: Request PMC to power up all required rails and wait for the acknowledgement.*/
goto done;
}
}
/* Add delay to stabilize the voltage rails. Need to check exact amount of time. */
usleep(250);
Status = XPmPlDomain_InitandHouseclean();
if (XST_SUCCESS != Status) {
goto done;
}
}
Pld = (XPm_PlDomain *)XPmPower_GetById(PM_POWER_PLD);
if (NULL == Pld) {
Status = XST_FAILURE;
goto done;
}
/* Remove PL-SOC isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_SOC, FALSE_IMMEDIATE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Remove PMC-SOC isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_SOC_NPI, FALSE_IMMEDIATE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Unlock CFU writes */
PldCfuLock(Pld, 0U);
if(0U == PlpdHouseCleanBypass) {
Status = PlHouseClean(PLHCLEAN_INIT_NODE);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = PldCfuInit();
if (XST_SUCCESS != Status) {
goto done;
}
if (PLATFORM_VERSION_SILICON == Platform) {
/*House clean GTY*/
Status = GtyHouseClean();
if (XST_SUCCESS != Status) {
XPlmi_Printf(DEBUG_GENERAL, "ERROR: %s : GTY HC failed", __func__);
}
}
Pld = (XPm_PlDomain *)XPmPower_GetById(PM_POWER_PLD);
if (NULL == Pld) {
Status = XST_FAILURE;
goto done;
}
/* Set init_complete */
PmOut32(Pld->CfuApbBaseAddr + CFU_APB_CFU_MASK_OFFSET,
CFU_APB_CFU_FGCR_INIT_COMPLETE_MASK);
PmOut32(Pld->CfuApbBaseAddr + CFU_APB_CFU_FGCR_OFFSET,
CFU_APB_CFU_FGCR_INIT_COMPLETE_MASK);
/* Enable the global signals */
XCfupmc_SetGlblSigEn(&CfupmcIns, (u8 )TRUE);
if (XST_SUCCESS == XPmPower_CheckPower( PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_RAM_MASK |
PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_MASK)) {
/* Remove vccaux-vccram domain isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_VCCAUX_VCCRAM, FALSE_IMMEDIATE);
if (XST_SUCCESS != Status) {
goto done;
}
}
if (XST_SUCCESS == XPmPower_CheckPower( PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_RAM_MASK |
PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_SOC_MASK)) {
/* Remove vccaux-vccram domain isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_VCCRAM_SOC, FALSE_IMMEDIATE);
if (XST_SUCCESS != Status) {
goto done;
}
}
XCfupmc_GlblSeqInit(&CfupmcIns);
/* Lock CFU writes */
PldCfuLock(Pld, 1U);
done:
return Status;
}
/*****************************************************************************/
/**
* @brief This function initializes and performs housecleaning for PL domain
*
* @param None
*
* @return XST_FAILURE if error / XST_SUCCESS if success
*
*****************************************************************************/
XStatus XPmPlDomain_InitandHouseclean(void)
{
XStatus Status = XST_FAILURE;
u32 Version;
XPm_Pmc *Pmc;
u32 VoltageRailMask = (PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_PL_MASK |
PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_RAM_MASK |
PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_MASK);
/* Skip if already done */
if (0U != HcleanDone) {
Status = XST_SUCCESS;
goto done;
}
/* Proceed only if vccint, vccaux, vccint_ram is 1 */
Status = XPmPower_CheckPower(VoltageRailMask);
if (XST_SUCCESS != Status) {
goto done;
}
/* Remove POR for PL */
Status = XPmReset_AssertbyId(PM_RST_PL_POR, (u32)PM_RESET_ACTION_RELEASE);
if (XST_SUCCESS != Status) {
goto done;
}
Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
if (NULL == Pmc) {
Status = XST_FAILURE;
goto done;
}
PmIn32(PMC_TAP_VERSION, Version);
PlatformVersion = ((Version & PMC_TAP_VERSION_PLATFORM_VERSION_MASK) >>
PMC_TAP_VERSION_PLATFORM_VERSION_SHIFT);
Platform = ((Version & PMC_TAP_VERSION_PLATFORM_MASK) >>
PMC_TAP_VERSION_PLATFORM_SHIFT);
/* Check if housecleaning needs to be bypassed */
if (PLATFORM_VERSION_FCV == Platform) {
PlpdHouseCleanBypass = 1;
}
if((PLATFORM_VERSION_SILICON == Platform) && (PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
/*
* EDT-995767: Theres a bug with ES1, due to which a small
* percent (<2%) of device may miss pl_por_b during power,
* which could result CFRAME wait up in wrong state. The work
* around requires to toggle PL_POR twice after PL supplies is
* up.
*/
/* Toggle PL POR */
Status = XPmReset_AssertbyId(PM_RST_PL_POR, (u32)PM_RESET_ACTION_PULSE);
if (XST_SUCCESS != Status) {
goto done;
}
/*
* Clear sticky ERROR and interrupt status (They are not
* cleared by PL_POR). Otherwise, once ERROR/interrupt is
* enabled by PLM, PLM may behave incorrectly.
*/
XPm_Write32(Pmc->PmcGlobalBaseAddr +
PMC_GLOBAL_GIC_PROXY_BASE_OFFSET +
GIC_PROXY_GROUP_OFFSET(3U) +
GIC_PROXY_IRQ_STATUS_OFFSET,
GICP3_CFRAME_SEU_MASK | GICP3_CFU_MASK);
XPm_Write32(Pmc->PmcGlobalBaseAddr +
PMC_GLOBAL_ERR1_STATUS_OFFSET,
PMC_GLOBAL_ERR1_STATUS_CFU_MASK |
PMC_GLOBAL_ERR1_STATUS_CFRAME_MASK);
XPm_Write32(Pmc->PmcGlobalBaseAddr +
PMC_GLOBAL_ERR2_STATUS_OFFSET,
PMC_GLOBAL_ERR2_STATUS_CFI_MASK |
PMC_GLOBAL_ERR2_STATUS_CFRAME_SEU_CRC_MASK |
PMC_GLOBAL_ERR2_STATUS_CFRAME_SEU_ECC_MASK);
}
/* Check for PL PowerUp */
Status = XPm_PollForMask(Pmc->PmcGlobalBaseAddr +
PMC_GLOBAL_PL_STATUS_OFFSET,
PMC_GLOBAL_PL_STATUS_POR_PL_B_MASK,
XPM_POLL_TIMEOUT);
if(XST_SUCCESS != Status) {
goto done;
}
/* Remove SRST for PL */
Status = XPmReset_AssertbyId(PM_RST_PL_SRST, (u32)PM_RESET_ACTION_RELEASE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = PldCframeInit();
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_PL_CFRAME,
FALSE_IMMEDIATE);
if (XST_SUCCESS != Status) {
goto done;
}
if(0U == PlpdHouseCleanBypass) {
Status = PlHouseClean(PLHCLEAN_EARLY_BOOT);
if (XST_SUCCESS != Status) {
goto done;
}
}
/* Set the flag */
HcleanDone = 1;
done:
return Status;
}
static struct XPm_PowerDomainOps PldOps = {
.InitStart = PldInitStart,
.InitFinish = PldInitFinish,
.PlHouseclean = NULL,
};
static XStatus (*HandlePowerEvent)(XPm_Node *Node, u32 Event);
static XStatus HandlePlDomainEvent(XPm_Node *Node, u32 Event)
{
XStatus Status = XST_FAILURE;
XPm_Power *Power = (XPm_Power *)Node;
PmDbg("State=%d, Event=%d\n\r", Node->State, Event);
switch (Node->State)
{
case (u8)XPM_POWER_STATE_ON:
if ((u32)XPM_POWER_EVENT_PWR_UP == Event) {
Status = XST_SUCCESS;
Power->UseCount++;
} else if ((u32)XPM_POWER_EVENT_PWR_DOWN == Event) {
Status = XST_SUCCESS;
Power->UseCount--;
Node->State = (u8)XPM_POWER_STATE_OFF;
} else {
Status = XST_FAILURE;
}
break;
case (u8)XPM_POWER_STATE_OFF:
if ((u32)XPM_POWER_EVENT_PWR_UP == Event) {
Status = XST_SUCCESS;
Power->UseCount++;
Node->State = (u8)XPM_POWER_STATE_ON;
} else if ((u32)XPM_POWER_EVENT_PWR_DOWN == Event) {
Status = XST_SUCCESS;
Power->UseCount--;
} else {
Status = XST_FAILURE;
}
break;
default:
PmWarn("Wrong state %d for event %d\n",
Node->State, Event);
break;
}
return Status;
}
XStatus XPmPlDomain_Init(XPm_PlDomain *PlDomain, u32 Id, u32 BaseAddress,
XPm_Power *Parent, u32 *OtherBaseAddresses,
u32 OtherBaseAddressCnt)
{
XStatus Status = XST_FAILURE;
Status = XPmPowerDomain_Init(&PlDomain->Domain, Id, BaseAddress, Parent, &PldOps);
if (XST_SUCCESS != Status) {
goto done;
}
PlDomain->Domain.Power.Node.State = (u8)XPM_POWER_STATE_OFF;
PlDomain->Domain.Power.UseCount = 1;
HandlePowerEvent = PlDomain->Domain.Power.HandleEvent;
PlDomain->Domain.Power.HandleEvent = HandlePlDomainEvent;
/* Make sure enough base addresses are being passed */
if (2U <= OtherBaseAddressCnt) {
PlDomain->CfuApbBaseAddr = OtherBaseAddresses[0];
PlDomain->Cframe0RegBaseAddr = OtherBaseAddresses[1];
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/rfdc_v8_0/src/xrfdc_sinit.c
/******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrfdc_sinit.c
* @addtogroup rfdc_v8_0
* @{
*
* The implementation of the XRFdc component's static initialization
* functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.0 sk 05/16/17 Initial release
* 5.0 mus 08/17/18 Updated XRFdc_LookupConfig to make use of device
* tree instead of xrfdc_g.c, to obtain
* XRFdc_Config for provided device id.It is being
* achieved through "param-list" property in RFDC
* device node, it will be having 1:1 mapping with
* the XRFdc_Config structure. Said changes
* have been done, to remove the xparameters.h
* dependency from RFDC Linux user space driver.
* 7.0 cog 05/13/19 Formatting changes.
* cog 07/25/19 Added new XRFdc_RegisterMetal() API to register
* RFDC with Libmetal.
* cog 08/02/19 Formatting changes.
* 8.0 cog 02/10/20 Updated addtogroup.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xrfdc.h"
#ifdef __BAREMETAL__
#include "xparameters.h"
#else
#include <dirent.h>
#include <arpa/inet.h>
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __BAREMETAL__
extern XRFdc_Config XRFdc_ConfigTable[];
#else
static XRFdc_Config *XRFdc_ConfigTablePtr = NULL;
#endif
#ifndef __BAREMETAL__
/*****************************************************************************/
/**
*
* Compare two strings in the reversed order.This function compares only
* the last "Count" number of characters of Str1Ptr and Str2Ptr.
*
* @param Str1Ptr is base address of first string
* @param Str2Ptr is base address of second string
* @param Count is number of last characters to be compared between
* Str1Ptr and Str2Ptr
*
* @return
* 0 if last "Count" number of bytes matches between Str1Ptr and
* Str2Ptr, else difference in unmatched character.
*
*@note None.
*
******************************************************************************/
static s32 XRFdc_Strrncmp(const char *Str1Ptr, const char *Str2Ptr, size_t Count)
{
u16 Len1 = strlen(Str1Ptr);
u16 Len2 = strlen(Str2Ptr);
u8 Diff;
for (; Len1 && Len2; Len1--, Len2--) {
if ((Diff = Str1Ptr[Len1 - 1] - Str2Ptr[Len2 - 1]) != 0) {
return Diff;
}
if (--Count == 0) {
return 0;
}
}
return (Len1 - Len2);
}
/*****************************************************************************/
/**
*
* Traverse "/sys/bus/platform/device" directory, to find RFDC device entry,
* corresponding to provided device id. If device entry corresponding to said
* device id is found, store it in output buffer DevNamePtr.
*
* @param DevNamePtr is base address of char array, where device name
* will be stored
* @param DevId contains the ID of the device to look up the
* RFDC device name entry in "/sys/bus/platform/device"
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if device entry not found for given device id.
*
*@note None.
*
******************************************************************************/
s32 XRFdc_GetDeviceNameByDeviceId(char *DevNamePtr, u16 DevId)
{
s32 Status = XRFDC_FAILURE;
u32 Data = 0;
char CompatibleString[NAME_MAX];
struct metal_device *DevicePtr;
DIR *DirPtr;
struct dirent *DirentPtr;
char Len = strlen(XRFDC_COMPATIBLE_STRING);
char SignLen = strlen(XRFDC_SIGNATURE);
DirPtr = opendir(XRFDC_PLATFORM_DEVICE_DIR);
if (DirPtr) {
while ((DirentPtr = readdir(DirPtr)) != NULL) {
if (XRFdc_Strrncmp(DirentPtr->d_name, XRFDC_SIGNATURE, SignLen) == 0) {
Status = metal_device_open("platform", DirentPtr->d_name, &DevicePtr);
if (Status) {
metal_log(METAL_LOG_ERROR, "\n Failed to open device %s", DirentPtr->d_name);
continue;
}
Status = metal_linux_get_device_property(DevicePtr, XRFDC_COMPATIBLE_PROPERTY,
CompatibleString, Len);
if (Status < 0) {
metal_log(METAL_LOG_ERROR, "\n Failed to read device tree property");
} else if (strncmp(CompatibleString, XRFDC_COMPATIBLE_STRING, Len) == 0) {
Status = metal_linux_get_device_property(DevicePtr, XRFDC_CONFIG_DATA_PROPERTY,
&Data, XRFDC_DEVICE_ID_SIZE);
if (Status < 0) {
metal_log(METAL_LOG_ERROR, "\n Failed to read device tree property");
} else if (Data == DevId) {
strcpy(DevNamePtr, DirentPtr->d_name);
Status = XRFDC_SUCCESS;
metal_device_close(DevicePtr);
break;
}
}
metal_device_close(DevicePtr);
}
}
}
return Status;
}
#endif
/*****************************************************************************/
/**
*
* Looks up the device configuration based on the unique device ID. A table
* contains the configuration info for each device in the system.
*
* @param DeviceId contains the ID of the device to look up the
* configuration for.
*
* @return
*
* A pointer to the configuration found or NULL if the specified device ID was
* not found. See xrfdc.h for the definition of XRFdc_Config.
*
* @note None.
*
******************************************************************************/
XRFdc_Config *XRFdc_LookupConfig(u16 DeviceId)
{
XRFdc_Config *CfgPtr = NULL;
#ifndef __BAREMETAL__
s32 Status = 0;
u32 NumInstances;
struct metal_device *Deviceptr;
char DeviceName[NAME_MAX];
Status = XRFdc_GetDeviceNameByDeviceId(DeviceName, DeviceId);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Invalid device id %d", DeviceId);
goto RETURN_PATH2;
}
Status = metal_device_open(XRFDC_BUS_NAME, DeviceName, &Deviceptr);
if (Status) {
metal_log(METAL_LOG_ERROR, "\n Failed to open device %s", DeviceName);
goto RETURN_PATH2;
}
if (XRFdc_ConfigTablePtr == NULL) {
Status = metal_linux_get_device_property(Deviceptr, XRFDC_NUM_INSTANCES_PROPERTY, &NumInstances,
XRFDC_NUM_INST_SIZE);
if (Status < 0) {
metal_log(METAL_LOG_ERROR, "\n Failed to read device tree property %s\r\n",
XRFDC_NUM_INSTANCES_PROPERTY);
goto RETURN_PATH1;
}
XRFdc_ConfigTablePtr = (XRFdc_Config *)malloc(ntohl(NumInstances) * XRFDC_CONFIG_DATA_SIZE);
if (XRFdc_ConfigTablePtr == NULL) {
metal_log(METAL_LOG_ERROR, "\n Failed to allocate memory for XRFdc_ConfigTablePtr");
goto RETURN_PATH1;
}
}
Status = metal_linux_get_device_property(Deviceptr, XRFDC_CONFIG_DATA_PROPERTY, &XRFdc_ConfigTablePtr[DeviceId],
XRFDC_CONFIG_DATA_SIZE);
if (Status == XRFDC_SUCCESS) {
CfgPtr = &XRFdc_ConfigTablePtr[DeviceId];
} else {
metal_log(METAL_LOG_ERROR, "\n Failed to read device tree property %s", XRFDC_CONFIG_DATA_PROPERTY);
}
RETURN_PATH1:
metal_device_close(Deviceptr);
RETURN_PATH2:
#else
u32 Index;
for (Index = 0U; Index < (u32)XPAR_XRFDC_NUM_INSTANCES; Index++) {
if (XRFdc_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XRFdc_ConfigTable[Index];
break;
}
}
#endif
return (XRFdc_Config *)CfgPtr;
}
/*****************************************************************************/
/**
*
* Register/open the deviceand map RFDC to the IO region.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param DeviceId contains the ID of the device to register/map
* @param DevicePtr is a pointer to the metal device.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_RegisterMetal(XRFdc *InstancePtr, u16 DeviceId, struct metal_device **DevicePtr)
{
s32 Status;
#ifndef __BAREMETAL__
char DeviceName[100];
#endif
Xil_AssertNonvoid(InstancePtr != NULL);
#ifdef __BAREMETAL__
Xil_AssertNonvoid(DevicePtr != NULL);
Status = metal_register_generic_device(*DevicePtr);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Failed to register device");
goto RETURN_PATH;
}
Status = metal_device_open(XRFDC_BUS_NAME, XRFDC_DEV_NAME, DevicePtr);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Failed to open device usp_rf_data_converter");
goto RETURN_PATH;
}
#else
Status = XRFdc_GetDeviceNameByDeviceId(DeviceName, DeviceId);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Failed to find rfdc device with device id %d", DeviceId);
goto RETURN_PATH;
}
Status = metal_device_open(XRFDC_BUS_NAME, DeviceName, DevicePtr);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Failed to open device %s.\n", DeviceName);
goto RETURN_PATH;
}
#endif
/* Map RFDC device IO region */
InstancePtr->io = metal_device_io_region(*DevicePtr, DeviceId);
if (InstancePtr->io == NULL) {
metal_log(METAL_LOG_ERROR, "\n Failed to map RFDC region for %s.\n", (*DevicePtr)->name);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
InstancePtr->device = *DevicePtr;
Status = XRFDC_SUCCESS;
RETURN_PATH:
return (u32)Status;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_config.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
#include "pm_config.h"
#include "xil_types.h"
#include "xstatus.h"
#include "pm_common.h"
#include "pm_defs.h"
#include "pm_master.h"
#include "pm_slave.h"
#include "pm_reset.h"
#include "pm_requirement.h"
#include "pm_node.h"
#include "pm_system.h"
#include "pm_pll.h"
typedef s32 (*const PmConfigSectionHandler)(u32* const addr);
static s32 PmConfigSlaveSectionHandler(u32* const addr);
static s32 PmConfigMasterSectionHandler(u32* const addr);
static s32 PmConfigPreallocSectionHandler(u32* const addr);
static s32 PmConfigPowerSectionHandler(u32* const addr);
static s32 PmConfigResetSectionHandler(u32* const addr);
static s32 PmConfigShutdownSectionHandler(u32* const addr);
static s32 PmConfigSetConfigSectionHandler(u32* const addr);
static s32 PmConfigGpoSectionHandler(u32* const addr);
/*********************************************************************
* Macros
********************************************************************/
#define PM_CONFIG_GPO_2_ENABLE_MASK BIT(10U)
#define PM_CONFIG_GPO_3_ENABLE_MASK BIT(11U)
#define PM_CONFIG_GPO_4_ENABLE_MASK BIT(12U)
#define PM_CONFIG_GPO_5_ENABLE_MASK BIT(13U)
/* Section IDs (must match to what PCW generates) */
#define PM_CONFIG_MASTER_SECTION_ID 0x101U
#define PM_CONFIG_SLAVE_SECTION_ID 0x102U
#define PM_CONFIG_PREALLOC_SECTION_ID 0x103U
#define PM_CONFIG_POWER_SECTION_ID 0x104U
#define PM_CONFIG_RESET_SECTION_ID 0x105U
#define PM_CONFIG_SHUTDOWN_SECTION_ID 0x106U
#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U
#define PM_CONFIG_GPO_SECTION_ID 0x108U
/* Size in bytes of one data field in configuration object */
#define PM_CONFIG_WORD_SIZE 4U
#define PM_CONFIG_OBJECT_LOADED 0x1U
#define PM_CONFIG_GPO_MASK (BIT(5U) | BIT(4U) | BIT(3U) | BIT(2U))
/* Default number of sections in configuration object */
#define DEFAULT_SECTIONS_NUM 7U
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmConfigSection - Information about the section
* @id Section identifier
* @handler Handler for processing section data from the object
*/
typedef struct {
const u32 id;
PmConfigSectionHandler handler;
} PmConfigSection;
static PmConfigSection pmConfigSections[] = {
{
.id = PM_CONFIG_MASTER_SECTION_ID,
.handler = PmConfigMasterSectionHandler,
}, {
.id = PM_CONFIG_SLAVE_SECTION_ID,
.handler = PmConfigSlaveSectionHandler,
}, {
.id = PM_CONFIG_PREALLOC_SECTION_ID,
.handler = PmConfigPreallocSectionHandler,
}, {
.id = PM_CONFIG_POWER_SECTION_ID,
.handler = PmConfigPowerSectionHandler,
}, {
.id = PM_CONFIG_RESET_SECTION_ID,
.handler = PmConfigResetSectionHandler,
}, {
.id = PM_CONFIG_SHUTDOWN_SECTION_ID,
.handler = PmConfigShutdownSectionHandler,
}, {
.id = PM_CONFIG_SET_CONFIG_SECTION_ID,
.handler = PmConfigSetConfigSectionHandler,
}, {
.id = PM_CONFIG_GPO_SECTION_ID,
.handler = PmConfigGpoSectionHandler,
},
};
/**
* PmConfig - Configuration object data
* @configPerms ORed masks of masters which are allowed to load the object
* @flags Flags: bit(0) - set if the configuration object is loaded
* @secNumber Number of sections in configuration object
*/
typedef struct {
u32 configPerms;
u8 flags;
u32 secNumber;
} PmConfig;
/*
* The first configuration object can be loaded only by APU or RPU_0. Later,
* the loading depends on the permissions specified in the set config section
* in the provided object. If zero permissions are given, the loading of
* configuration is locked-down.
*/
static PmConfig pmConfig = {
.configPerms = IPI_PMU_0_IER_APU_MASK | IPI_PMU_0_IER_RPU_0_MASK,
.flags = 0U,
.secNumber = DEFAULT_SECTIONS_NUM,
};
/**
* PmConfigObjectIsLoaded() - Check if the configuration object is loaded
* @return True if the object is loaded, false otherwise
*/
inline bool PmConfigObjectIsLoaded(void)
{
return 0U != (pmConfig.flags & PM_CONFIG_OBJECT_LOADED);
}
/**
* PmConfigReadNext() - Read the next word from configuration object
*
* @return The word read from object
*
* @note As the side effect, the nextAddr value is incremented
*/
static u32 PmConfigReadNext(u32* const addr)
{
u32 val;
val = XPfw_Read32(*addr);
*addr += PM_CONFIG_WORD_SIZE;
return val;
}
/**
* PmConfigSkipWords() - Skip reading a number of words
* @addr Current address to increase by the number of skipped words
* @words Number of words to skip
*/
static void PmConfigSkipWords(u32* const addr, const u32 words)
{
*addr += words * PM_CONFIG_WORD_SIZE;
}
/**
* PmConfigMasterSectionHandler() - Read and process masters section
* @addr Start address of the section in configuration object
*
* @return XST_SUCCESS if section is loaded successfully, XST_FAILURE
* otherwise
*/
static s32 PmConfigMasterSectionHandler(u32* const addr)
{
s32 status = XST_SUCCESS;
u32 i, mastersCnt;
mastersCnt = PmConfigReadNext(addr);
for (i = 0U; i < mastersCnt; i++) {
u32 nodeId;
PmMaster* master;
PmMasterConfig config;
nodeId = PmConfigReadNext(addr);
master = PmMasterGetPlaceholder(nodeId);
if (NULL == master) {
PmErr("Unknown master #%lu\r\n", nodeId);
status = XST_FAILURE;
goto done;
}
config.ipiMask = PmConfigReadNext(addr);
config.suspendTimeout = PmConfigReadNext(addr);
config.suspendPerms = PmConfigReadNext(addr);
config.wakePerms = PmConfigReadNext(addr);
PmMasterSetConfig(master, &config);
}
done:
return status;
}
/**
* PmConfigSlaveSectionHandler() - Read and process slaves section
* @addr Start address of the section in configuration object
*
* @return XST_SUCCESS if section is loaded successfully, XST_FAILURE
* otherwise
*/
static s32 PmConfigSlaveSectionHandler(u32* const addr)
{
s32 status = XST_SUCCESS;
u32 i, slavesCnt;
slavesCnt = PmConfigReadNext(addr);
for (i = 0U; i < slavesCnt; i++) {
u32 nodeId, usagePolicy, usagePerms;
PmSlave* slave;
nodeId = PmConfigReadNext(addr);
slave = (PmSlave*)PmNodeGetSlave(nodeId);
if (NULL == slave) {
PmErr("Unknown slave #%lu\r\n", nodeId);
status = XST_FAILURE;
goto done;
}
usagePolicy = PmConfigReadNext(addr);
usagePerms = PmConfigReadNext(addr);
status = PmSlaveSetConfig(slave, usagePolicy, usagePerms);
if (XST_SUCCESS != status) {
PmErr("%s config failed\r\n", slave->node.name);
goto done;
}
}
done:
return status;
}
/**
* PmConfigPreallocForMaster() - Process preallocation for the master
* @master Master whose preallocated slaves are to be processed
* @addr Start address of the prealloc subsection in the configuration
* object
* @return XST_SUCCESS if preallocated slaves are processed correctly,
* XST_FAILURE otherwise
*/
static s32 PmConfigPreallocForMaster(const PmMaster* const master,
u32* const addr)
{
s32 status = XST_SUCCESS;
u32 i, preallocCnt;
preallocCnt = PmConfigReadNext(addr);
for (i = 0U; i < preallocCnt; i++) {
u32 nodeId, flags, currReq, defReq;
PmSlave* slave;
PmRequirement* req;
/* Get slave by node ID */
nodeId = PmConfigReadNext(addr);
slave = (PmSlave*)PmNodeGetSlave(nodeId);
if (NULL == slave) {
PmErr("Unknown slave #%lu\r\n", nodeId);
status = XST_FAILURE;
goto done;
}
/* Get the requirement structure for master/slave pair */
req = PmRequirementGet(master, slave);
if (NULL == req) {
PmErr("Invalid (%s, %s) pair\r\n", master->name,
slave->node.name);
status = XST_FAILURE;
goto done;
}
flags = PmConfigReadNext(addr);
currReq = PmConfigReadNext(addr);
defReq = PmConfigReadNext(addr);
status = PmRequirementSetConfig(req, flags, currReq, defReq);
if (XST_SUCCESS != status) {
goto done;
}
}
done:
return status;
}
/**
* PmConfigPreallocSectionHandler() - Read and process section containing
* information about the preallocated slaves
* @addr Start address of the section in configuration object
*
* @return XST_SUCCESS if section is loaded successfully, XST_FAILURE
* otherwise
*/
static s32 PmConfigPreallocSectionHandler(u32* const addr)
{
s32 status = XST_SUCCESS;
u32 i, mastersCnt;
mastersCnt = PmConfigReadNext(addr);
for (i = 0U; i < mastersCnt; i++) {
u32 ipiMask;
PmMaster* master;
/* Get the master by specified IPI mask */
ipiMask = PmConfigReadNext(addr);
master = PmGetMasterByIpiMask(ipiMask);
if (NULL == master) {
PmErr("Unknown master (ipi=0x%lx)\r\n", ipiMask);
status = XST_FAILURE;
goto done;
}
status = PmConfigPreallocForMaster(master, addr);
if (XST_SUCCESS != status) {
goto done;
}
}
done:
return status;
}
/**
* PmConfigPowerSectionHandler() - Read and process power section
* @addr Start address of the section in configuration object
*
* @return XST_SUCCESS if section is loaded successfully, XST_FAILURE
* otherwise
*/
static s32 PmConfigPowerSectionHandler(u32* const addr)
{
s32 status = XST_SUCCESS;
u32 i, powersCnt;
powersCnt = PmConfigReadNext(addr);
for (i = 0U; i < powersCnt; i++) {
u32 powerId;
PmPower* power;
powerId = PmConfigReadNext(addr);
power = (PmPower*)PmNodeGetPower(powerId);
if (NULL == power) {
PmErr("Unknown power #%lu\r\n", powerId);
status = XST_FAILURE;
goto done;
}
power->forcePerms = PmConfigReadNext(addr);
}
done:
return status;
}
/**
* PmConfigResetSectionHandler() - Read and process reset section
* @addr Start address of the section in configuration object
*
* @return XST_SUCCESS if section is loaded successfully, XST_FAILURE
* otherwise
*/
static s32 PmConfigResetSectionHandler(u32* const addr)
{
s32 status = XST_SUCCESS;
u32 i, resetsCnt;
resetsCnt = PmConfigReadNext(addr);
for (i = 0U; i < resetsCnt; i++) {
u32 resetId, permissions;
resetId = PmConfigReadNext(addr);
permissions = PmConfigReadNext(addr);
status = PmResetSetConfig(resetId, permissions);
if (XST_SUCCESS != status) {
PmErr("Unknown reset #%lu\r\n", resetId);
goto done;
}
}
done:
return status;
}
/**
* PmConfigShutdownSectionHandler() - Read and process shutdown section
* @addr Start address of the section in configuration object
*
* @return XST_SUCCESS if section is loaded successfully, XST_FAILURE
* otherwise
*/
static s32 PmConfigShutdownSectionHandler(u32* const addr)
{
s32 status = XST_SUCCESS;
/* Shutdown section doesn't have shutdown types information */
PmConfigSkipWords(addr, 1);
return status;
}
/**
* PmConfigSetConfigSectionHandler() - Read and process set configuration
* section
* @addr Start address of the section in configuration object
*
* @return XST_SUCCESS always
*/
static s32 PmConfigSetConfigSectionHandler(u32* const addr)
{
pmConfig.configPerms = PmConfigReadNext(addr);
return XST_SUCCESS;
}
/**
* PmConfigHeaderHandler() - Read and process header of config object
* @addr Start address of the header in configuration object
*/
static void PmConfigHeaderHandler(u32* const addr)
{
u32 remWords;
/* Read number of remaining words in header */
remWords = PmConfigReadNext(addr);
/* If there is words in header, get number of sections in object */
if (remWords > 0U) {
pmConfig.secNumber = PmConfigReadNext(addr);
remWords--;
}
/* Skip the remaining words in header */
PmConfigSkipWords(addr, remWords);
}
/**
* PmConfigGpoSectionHandler() - Read and process GPO section
* @addr Start address of the section in configuration object
*
* @return XST_SUCCESS always
*/
static s32 PmConfigGpoSectionHandler(u32* const addr)
{
u32 gpoState, reg;
gpoState = PmConfigReadNext(addr);
reg = XPfw_Read32(PMU_LOCAL_GPO1_READ);
reg &= ~PM_CONFIG_GPO_MASK;
reg |= (gpoState & PM_CONFIG_GPO_MASK);
XPfw_Write32(PMU_IOMODULE_GPO1, reg);
#ifdef CONNECT_PMU_GPO_2
if ((gpoState & PM_CONFIG_GPO_2_ENABLE_MASK) != 0U) {
XPfw_RMW32((IOU_SLCR_BASE + IOU_SLCR_MIO_PIN_34_OFFSET),
0x000000FEU, 0x00000008U);
}
#endif
#ifdef CONNECT_PMU_GPO_3
if ((gpoState & PM_CONFIG_GPO_3_ENABLE_MASK) != 0U) {
XPfw_RMW32((IOU_SLCR_BASE + IOU_SLCR_MIO_PIN_35_OFFSET),
0x000000FEU, 0x00000008U);
}
#endif
#ifdef CONNECT_PMU_GPO_4
if ((gpoState & PM_CONFIG_GPO_4_ENABLE_MASK) != 0U) {
XPfw_RMW32((IOU_SLCR_BASE + IOU_SLCR_MIO_PIN_36_OFFSET),
0x000000FEU, 0x00000008U);
}
#endif
#ifdef CONNECT_PMU_GPO_5
if ((gpoState & PM_CONFIG_GPO_5_ENABLE_MASK) != 0U) {
XPfw_RMW32((IOU_SLCR_BASE + IOU_SLCR_MIO_PIN_37_OFFSET),
0x000000FEU, 0x00000008U);
}
#endif
return XST_SUCCESS;
}
/**
* PmConfigClear() - Clear previous PFW configuration
*/
static void PmConfigClear(void)
{
PmMasterClearConfig();
PmResetClearConfig();
PmNodeClearConfig();
pmConfig.configPerms = 0U;
pmConfig.secNumber = DEFAULT_SECTIONS_NUM;
}
/**
* PmConfigGetSectionById() - Get section struct based on section ID
* @sid Section ID to look for
*
* @return Pointer to the section structure or NULL if not found
*/
static PmConfigSection* PmConfigGetSectionById(const u32 sid)
{
PmConfigSection* sec = NULL;
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmConfigSections); i++) {
if (sid == pmConfigSections[i].id) {
sec = &pmConfigSections[i];
break;
}
}
return sec;
}
/**
* PmConfigPllPermsWorkaround() - Workaround for configuring PLL permissions
*
* @note This is a workaround for PMU-FW not knowing who should be given
* permission to control a PLL, and also which PLLs. Currently, the DP driver in
* linux requires direct control to VPLL (for video) and RPLL (for audio). This
* information should be provided in configuration object. Since that's not
* possible, the information has to be hard-coded here. Hopefully this
* workaround will be removed in future. Thereby, it is required here to assume
* that if APU has permission to use the DP it should be automatically given
* permissions to directly control VPLL and RPLL.
*/
static void PmConfigPllPermsWorkaround(void)
{
PmMaster* apu = PmMasterGetPlaceholder(NODE_APU);
PmSlave* dp = (PmSlave*)PmNodeGetSlave(NODE_DP);
PmRequirement* req;
if ((NULL == apu) || (NULL == dp)) {
goto done;
}
req = PmRequirementGet(apu, dp);
if (NULL == req) {
goto done;
}
PmPllOpenAccess(&pmVpll_g, apu->ipiMask);
PmPllOpenAccess(&pmRpll_g, apu->ipiMask);
done:
return;
}
/**
* PmConfigLoadObject() - Load information provided in configuration object
* @address Start address of the configuration object
* @callerIpi IPI mask of the master who called set configuration API
*
* @return Status of loading information from configuration object
*/
s32 PmConfigLoadObject(const u32 address, const u32 callerIpi)
{
s32 status = XST_SUCCESS;
u32 currAddr = address;
u32 i;
/* Check for permissions to load the configuration object */
if (0U == (callerIpi & pmConfig.configPerms)) {
PmWarn("No permission to set config\r\n");
status = XST_PM_NO_ACCESS;
goto ret;
}
PmConfigClear();
status = PmSystemRequirementAdd();
if (XST_SUCCESS != status) {
goto done;
}
/* Read and process header from the object */
PmConfigHeaderHandler(&currAddr);
/* Read and process each section from the object */
for (i = 0U; i < pmConfig.secNumber; i++) {
PmConfigSection* section;
u32 sectionId;
sectionId = PmConfigReadNext(&currAddr);
section = PmConfigGetSectionById(sectionId);
if ((NULL == section) || (NULL == section->handler)) {
PmAlert("Unknown section #%lu\r\n", sectionId);
status = XST_FAILURE;
goto done;
}
status = section->handler(&currAddr);
if (XST_SUCCESS != status) {
goto done;
}
}
done:
if (XST_SUCCESS == status) {
pmConfig.flags |= PM_CONFIG_OBJECT_LOADED;
PmConfigPllPermsWorkaround();
status = PmNodeInit();
PmNodeForceDownUnusable();
} else {
pmConfig.flags &= ~PM_CONFIG_OBJECT_LOADED;
}
ret:
return status;
}
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/rsa.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _RSA_H_
#define _RSA_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* RSA Base Address
*/
#define RSA_BASEADDR 0XFFCE002C
/**
* Register: RSA_WR_DATA_0
*/
#define RSA_WR_DATA_0 ( ( RSA_BASEADDR ) + 0X00000000 )
#define RSA_WR_DATA_0_WR_DATA_SHIFT 0
#define RSA_WR_DATA_0_WR_DATA_WIDTH 32
#define RSA_WR_DATA_0_WR_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_WR_DATA_1
*/
#define RSA_WR_DATA_1 ( ( RSA_BASEADDR ) + 0X00000004 )
#define RSA_WR_DATA_1_WR_DATA_SHIFT 0
#define RSA_WR_DATA_1_WR_DATA_WIDTH 32
#define RSA_WR_DATA_1_WR_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_WR_DATA_2
*/
#define RSA_WR_DATA_2 ( ( RSA_BASEADDR ) + 0X00000008 )
#define RSA_WR_DATA_2_WR_DATA_SHIFT 0
#define RSA_WR_DATA_2_WR_DATA_WIDTH 32
#define RSA_WR_DATA_2_WR_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_WR_DATA_3
*/
#define RSA_WR_DATA_3 ( ( RSA_BASEADDR ) + 0X0000000C )
#define RSA_WR_DATA_3_WR_DATA_SHIFT 0
#define RSA_WR_DATA_3_WR_DATA_WIDTH 32
#define RSA_WR_DATA_3_WR_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_WR_DATA_4
*/
#define RSA_WR_DATA_4 ( ( RSA_BASEADDR ) + 0X00000010 )
#define RSA_WR_DATA_4_WR_DATA_SHIFT 0
#define RSA_WR_DATA_4_WR_DATA_WIDTH 32
#define RSA_WR_DATA_4_WR_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_WR_DATA_5
*/
#define RSA_WR_DATA_5 ( ( RSA_BASEADDR ) + 0X00000014 )
#define RSA_WR_DATA_5_WR_DATA_SHIFT 0
#define RSA_WR_DATA_5_WR_DATA_WIDTH 32
#define RSA_WR_DATA_5_WR_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_WR_ADDR
*/
#define RSA_WR_ADDR ( ( RSA_BASEADDR ) + 0X00000018 )
#define RSA_WR_ADDR_WR_ADDR_SHIFT 0
#define RSA_WR_ADDR_WR_ADDR_WIDTH 32
#define RSA_WR_ADDR_WR_ADDR_MASK 0XFFFFFFFF
/**
* Register: RSA_RD_DATA_0
*/
#define RSA_RD_DATA_0 ( ( RSA_BASEADDR ) + 0X0000001C )
#define RSA_RD_DATA_0_RD_DATA_SHIFT 0
#define RSA_RD_DATA_0_RD_DATA_WIDTH 32
#define RSA_RD_DATA_0_RD_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_RD_DATA_1
*/
#define RSA_RD_DATA_1 ( ( RSA_BASEADDR ) + 0X00000020 )
#define RSA_RD_DATA_1_RD_DATA_SHIFT 0
#define RSA_RD_DATA_1_RD_DATA_WIDTH 32
#define RSA_RD_DATA_1_RD_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_RD_DATA_2
*/
#define RSA_RD_DATA_2 ( ( RSA_BASEADDR ) + 0X00000024 )
#define RSA_RD_DATA_2_RD_DATA_SHIFT 0
#define RSA_RD_DATA_2_RD_DATA_WIDTH 32
#define RSA_RD_DATA_2_RD_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_RD_DATA_3
*/
#define RSA_RD_DATA_3 ( ( RSA_BASEADDR ) + 0X00000028 )
#define RSA_RD_DATA_3_RD_DATA_SHIFT 0
#define RSA_RD_DATA_3_RD_DATA_WIDTH 32
#define RSA_RD_DATA_3_RD_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_RD_DATA_4
*/
#define RSA_RD_DATA_4 ( ( RSA_BASEADDR ) + 0X0000002C )
#define RSA_RD_DATA_4_RD_DATA_SHIFT 0
#define RSA_RD_DATA_4_RD_DATA_WIDTH 32
#define RSA_RD_DATA_4_RD_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_RD_DATA_5
*/
#define RSA_RD_DATA_5 ( ( RSA_BASEADDR ) + 0X00000030 )
#define RSA_RD_DATA_5_RD_DATA_SHIFT 0
#define RSA_RD_DATA_5_RD_DATA_WIDTH 32
#define RSA_RD_DATA_5_RD_DATA_MASK 0XFFFFFFFF
/**
* Register: RSA_RD_ADDR
*/
#define RSA_RD_ADDR ( ( RSA_BASEADDR ) + 0X00000034 )
#define RSA_RD_ADDR_RD_ADDR_SHIFT 0
#define RSA_RD_ADDR_RD_ADDR_WIDTH 32
#define RSA_RD_ADDR_RD_ADDR_MASK 0XFFFFFFFF
/**
* Register: RSA_RSA_CFG
*/
#define RSA_RSA_CFG ( ( RSA_BASEADDR ) + 0X00000038 )
#define RSA_RSA_CFG_RD_ENDIANNESS_SHIFT 2
#define RSA_RSA_CFG_RD_ENDIANNESS_WIDTH 1
#define RSA_RSA_CFG_RD_ENDIANNESS_MASK 0X00000004
#define RSA_RSA_CFG_WR_ENDIANNESS_SHIFT 1
#define RSA_RSA_CFG_WR_ENDIANNESS_WIDTH 1
#define RSA_RSA_CFG_WR_ENDIANNESS_MASK 0X00000002
#define RSA_RSA_CFG_SLVERR_EN_SHIFT 0
#define RSA_RSA_CFG_SLVERR_EN_WIDTH 1
#define RSA_RSA_CFG_SLVERR_EN_MASK 0X00000001
/**
* Register: RSA_RSA_ISR
*/
#define RSA_RSA_ISR ( ( RSA_BASEADDR ) + 0X0000003C )
#define RSA_RSA_ISR_APB_SLVERR_SHIFT 0
#define RSA_RSA_ISR_APB_SLVERR_WIDTH 1
#define RSA_RSA_ISR_APB_SLVERR_MASK 0X00000001
/**
* Register: RSA_RSA_IMR
*/
#define RSA_RSA_IMR ( ( RSA_BASEADDR ) + 0X00000040 )
#define RSA_RSA_IMR_APB_SLVERR_SHIFT 0
#define RSA_RSA_IMR_APB_SLVERR_WIDTH 1
#define RSA_RSA_IMR_APB_SLVERR_MASK 0X00000001
/**
* Register: RSA_RSA_IER
*/
#define RSA_RSA_IER ( ( RSA_BASEADDR ) + 0X00000044 )
#define RSA_RSA_IER_APB_SLVERR_SHIFT 0
#define RSA_RSA_IER_APB_SLVERR_WIDTH 1
#define RSA_RSA_IER_APB_SLVERR_MASK 0X00000001
/**
* Register: RSA_RSA_IDR
*/
#define RSA_RSA_IDR ( ( RSA_BASEADDR ) + 0X00000048 )
#define RSA_RSA_IDR_APB_SLVERR_SHIFT 0
#define RSA_RSA_IDR_APB_SLVERR_WIDTH 1
#define RSA_RSA_IDR_APB_SLVERR_MASK 0X00000001
#ifdef __cplusplus
}
#endif
#endif /* _RSA_H_ */
<file_sep>/python_drivers/james_utils.py
# -*- coding: utf-8 -*-
"""
Created on Thu Jul 16 14:44:28 2020
@author: tianlab01
"""
import socket
import random
import math as Math
import matplotlib as plt
#Constants for Alice and Bob
ALICE_PORT = "COM4"
BOB_PORT = "COM9"
#Channel definitions for Alice and Bob, can all be set to a single channel if you're just doing key transmission
ALICE_CHANNEL_SEND = 4
ALICE_CHANNEL_RECEIVE = 4
BOB_CHANNEL_SEND = 4
BOB_CHANNEL_RECEIVE = 4
#TDC_THRESHOLD = 0.1 #100mV for SNSPDs
TDC_THRESHOLD = 0.1 #600mV for just FPGA
TDC_CHANNEL_LIST = (1,2,3,4)
#TDC_CHANNEL_LIST = (2,3,4) # for just fpga
PERIOD_THRESHOLD = 0.1 #If the measured and expected periods differ by more than this fracion then decode fails
SYNC_PERIOD_THRESHOLD = 0.01#Tighter for determining which sync pulses are valid
LOG_TO_FILE = 0
logfile = "received_pulse_streams_optical_2_9_test.txt"
INFER_TICK = 0 #If 1, next tick will be inferred from decoded value, do not use
#Timestamps denoting decode failiure
FAIL_TIMESTAMP_NO_PHOTON = 99999999999999
FAIL_TIMESTAMP_BAD_RANGE = 99999999999998
FAIL_TIMESTAMP_NEG_OFFSET = 99999999999997
TIMESTAMP_BYTE_LEN = 20
#Rerutns list of bytes object
def timestamps_to_bytes(list_of_timestamps):
byte_array = []
for l in list_of_timestamps:
res = int(l).to_bytes(TIMESTAMP_BYTE_LEN, byteorder='big', signed = False)
byte_array += list(res)
return byte_array
#Converts a list of bytes into a list of timestamps, 20 bytes per timestamp
def bytes_to_timestamps(byte_array):
#byte_array = list(b_a)
timestamp_list = []
if(len(byte_array) % 20 != 0):
print("Error, byte array for bytes_to_timestamp was of the wrong size")
return []
for i in range(0, len(byte_array), TIMESTAMP_BYTE_LEN):
ts_b = byte_array[i:i+TIMESTAMP_BYTE_LEN]
res = int.from_bytes(ts_b, byteorder='big', signed = False)
timestamp_list.append(res)
return timestamp_list
#Returns -1 on fail
#Should only be called internally
def receive_timestamp(sck):
#Receive and reconstruct the whole number
res = receive_bytes(sck, TIMESTAMP_BYTE_LEN)
if(res == -1 or res == -2 or res == -3):
print("Timed out waiting for timestamp")
return -1
return int.from_bytes(res, byteorder='big', signed = False)
#Sends a timestamp
#Should only be called internally
def send_timestamp(sck, ts):
ts_bs = int(ts).to_bytes(TIMESTAMP_BYTE_LEN, byteorder='big', signed = False)
#Then send the number itself
sck.send(ts_bs)
return
#Receives a user-defined number of bytes from an open socket c
#Returns bytestream on success
#Returns -1 on timeout
#Returns -2 on dead socket
#Returns -3 on other error
def receive_bytes(c, num_bytes):
byte_res = []
while(1):
try:
num_bytes_to_receive = num_bytes - len(byte_res)
if(num_bytes_to_receive > 1024):
num_bytes_to_receive = 1024
#res = c.recv(1024)
res = c.recv(num_bytes_to_receive)
if(len(res) > 0):
#copy all bytes into the result array
#for b in res:
byte_res += list(res)
#If we have all of the bytes
if(len(byte_res) >= num_bytes):
return byte_res
else:
print("Received an empty byte array from socket, socket is probably closed...")
return -2
except socket.timeout:
#print("Timed out while waiting for bytes...")
return -1
#except Exception as e:
#print("Unknown error occured while waiting for bytes")
#return -3
#Used for randomly deleting pulses in dummy pulse list generation for algorithm testing
def random_percent(percent=50):
if(percent == 0):
return 0
return random.randrange(100) < percent
#Record for keeping track of suspected synchronization pulses
class sync_pulse:
val = 0 #timestamp value
diffs = [] #List of differences to every other possible sync pulse
def __init__(self, v):
self.val = v
self.diffs = []
#Converts a value to be encoded to a coarse and fine offset used by the FPGA
def val_to_coarse_fine(val, bin_size):
offset = val_to_offset(val, bin_size)
c = Math.floor(offset / 4000)
f = Math.floor((offset/250)%16)
return c,f
#Converts a value to an offset in picoseconds
def val_to_offset(val, bin_size):
return (val * bin_size) + (0.5 * bin_size)
#Converts an offset value from the last bin start in picoseconds to the encoded value
def offset_to_val(offset, bin_number, bin_size):
if(offset > bin_number * bin_size):
#print("Error, received photon outside of allowed range, should not happen here")
return FAIL_TIMESTAMP_BAD_RANGE
val = Math.floor(offset/bin_size)
return val
#Checks two keys against eachother and returns number of succesfully transmittred values
#Tries all permutations of key allignment and returns the best result
def check_results(sent, recv):
correct = 0
#loop through all offsets
for offset in range(-1*(len(recv) - 1), len(recv)):
#Loop through sent string
c = 0
for j in range(0, len(sent)):
#Calculate the relative index for recv
recv_i = j + offset
#If we're in the correct range
if(recv_i > -1 and recv_i < len(recv)):
#Compare these two values and update c
if(sent[j] == recv[recv_i]):
c += 1
if(c > correct):
correct = c
return correct
def remove_duplicate_pulses(pulse_list, expected_period):
pulse_list_final = []
i = 0
num_dupes = 0
while(i < len(pulse_list)):
#If the difference between this pulse and the next pulse is relatively small
if(i < len(pulse_list)-1 and pulse_list[i+1]-pulse_list[i] < (expected_period * 0.1)):
#Replace the pulse with a single average of the two
average_timestamp = (pulse_list[i] + pulse_list[i+1])/2
pulse_list_final.append(average_timestamp)
i += 2
num_dupes += 1
else:
#Otherwise keep it
pulse_list_final.append(pulse_list[i])
i += 1
#print("Removed " + str(num_dupes) + " duplicate pulses from pulse list")
return pulse_list_final
#Decodes a list of pulses sourced from the TDC
#expected encoded pulses is the number of these we expect to find
#All units in picoseconds
def decode_pulse_list(pulses, expected_period, expected_bin_num, expected_bin_size, expected_num_sync_pulses, missing_timestamp_limit = 100, look_for_entangled_pair = 0):
#Used later on to get correct timestamp for entangled pulse
orig_pulses = pulses.copy()
print("Starting decode")
#pre-thing to do is subtract out offset
pulses.sort()
ofs = pulses[0]
for i in range(0, len(pulses)):
pulses[i] -= ofs
if(LOG_TO_FILE):
file = open(logfile,'a')
new_line = "period = " + str(expected_period) + ", bin_num = " + str(expected_bin_num) + ", length = " + str(len(pulses)) +"\n"
for p in pulses:
new_line += str(p) + ","
file.write(new_line + "\n")
file.close()
#return [1], 0, 0, 0
#Fist thing to do is figure out where the sync pulses end and encoded pulses start
# max_diff = 0
# max_diff_pos = 0
# for i in range(0, len(pulses)-1):
# d = pulses[i+1] - pulses[i]
# if(d > max_diff):
# max_diff = d
# max_diff_pos = i
# first_encoded_pulse_pos = max_diff_pos + 1;
#Find the first difference between two pulses which is close to the period
# for i in range(0, len(pulses)-1):
# diff = pulses[i+1] - pulses[i]
# tol = abs((diff - expected_period))/expected_period
# if(tol < PERIOD_THRESHOLD):
# first_sync_pulse_index = i
# break
#Experimental pulse preprocessing to remove double counts
pulses = remove_duplicate_pulses(pulses, expected_period)
#find one of the sync pulses
small_delay_cnt = 0
last_known_sync_pulse = 0
for i in range(0, len(pulses)-1):
if(small_delay_cnt > 3):
last_known_sync_pulse = i
break
diff = pulses[i+1] - pulses[i]
if(diff < expected_period * 3):
small_delay_cnt += 1
else:
small_delay_cnt = 0
if(last_known_sync_pulse == 0):
print("Error, unable to find first sync pulse, aborting")
return [0], 0, 0, 0, 0
#Walk backwards to the first sync pulse
j = last_known_sync_pulse
first_sync_pulse_index = 0
while(j > 5):
diff = pulses[j] - pulses[j-1]
j = j - 1
if(diff > expected_period*3):
first_sync_pulse_index = j+2
break
end_of_sync_pulses_timestamp = pulses[first_sync_pulse_index] + (expected_period * (expected_num_sync_pulses+5))
first_encoded_pulse_pos = 0
for i in range(first_sync_pulse_index, len(pulses)):
if(pulses[i] > end_of_sync_pulses_timestamp):
first_encoded_pulse_pos = i
break
if(first_encoded_pulse_pos == 0):
print("Cannot determine index of first encoded pulse, aborting")
return [0], 0, 0, 0, 0
#print("Done separating list of pulses")
#Now we're going to create objects for each pulse which store a list of their time differences to every other sync pulse
#If any pulse has two differences which are close enough to the expected period then we'll mark those as valid
#Now we calculate the period based on the measured differences of the first max_diff_pos pulses
sync_pulse_vals = pulses[first_sync_pulse_index:first_encoded_pulse_pos]
period_diffs = []
sync_pulse_objs= []
for i in range(0, len(sync_pulse_vals)):
#Create a new object for pulse i
spo = sync_pulse(sync_pulse_vals[i])
for j in range(0, len(sync_pulse_vals)):
if (j != i):
d = abs(sync_pulse_vals[j] - sync_pulse_vals[i])
period_diffs.append(d)
spo.diffs.append(d)#Append this also to the list for this pulse
#Record that pulse in our list
sync_pulse_objs.append(spo)
periods_final = []
for p in period_diffs:
#If this period is within allowable limits
thresh = abs(p - expected_period) / expected_period
if(thresh < PERIOD_THRESHOLD):
periods_final.append(p)
#If we end up with no successfull period measurement
if(len(periods_final) == 0):
print("Error, could not identify any synchronization pulses")
return [0], 0, 0, 0, 0
#Calculate the measured period
measured_period = sum(periods_final) / len(periods_final)
#adjust the bin size to match
measured_bin_size = (measured_period/expected_period) * expected_bin_size
#print("Measured period was " + str(measured_period) + ", measured bin size was " + str(measured_bin_size))
#Now go through the list of sync pulses and determine if they are valid
valid_sync_pulses = []
for sp in sync_pulse_objs:
num_valid_diffs = 0
#Loop through differences and look for those that meet threshold
for d in sp.diffs:
#If this pulse is too close to a dark count then throw it out
#if(d < (measured_period * 0.5)):
# num_valid_diffs = 0
# break
thresh = abs(d - measured_period)/measured_period
if(thresh < SYNC_PERIOD_THRESHOLD):
num_valid_diffs += 1
#If we have exactly two differences that meet the threshold
if(num_valid_diffs == 2):
#Add it to the list of valid pulses
valid_sync_pulses.append(sp.val)
#If there were no valid sync pulses then we fail
if(len(valid_sync_pulses) < 1):
print("Cannot decode pulse list, not enough valid sync pulses!")
return [0], 0, 0, 0, 0
#print("Found " + str(len(valid_sync_pulses)) + " valid sync pulses")
#now we figure out which was the last valid pulse
valid_sync_pulse_timestamps = []
last_valid_sync_pulse = 0
cnt = 0
for p in valid_sync_pulses:
cnt += 1
valid_sync_pulse_timestamps.append(p)
if(p > last_valid_sync_pulse):
last_valid_sync_pulse = p
#Select a sync pulse from somewhere in the middle
#if(cnt > 79):
# break
#The first encoded pulse is actually a synchrionization photon, so we're saving and returning it to the user and skipping the decode for it
entangled_pulse_timestamp = orig_pulses[first_encoded_pulse_pos]
#If this pulse is not far enough from the rest of the pulses we treat it as an encoded pulse instead
#Or we don't care about entangled pulses
if( (abs(entangled_pulse_timestamp - orig_pulses[first_encoded_pulse_pos+1]) < measured_period*3) or look_for_entangled_pair == 0):
encoded_pulses = pulses[first_encoded_pulse_pos:len(pulses)]
if(look_for_entangled_pair == 1):
print("Unable to determine which encoded pluse was an entangled photon.")
else:
print("Skipped looking for entagled pair")
entangled_pulse_timestamp = 0
else:
encoded_pulses = pulses[first_encoded_pulse_pos+1:len(pulses)]
#Fail if there are no encoded pulses to decode
if(len(encoded_pulses) < 1):
print("Cannot decode pulse list, no encoded pulses found!")
return [0], 0, 0, 0, 0
#FOR TESTING PURPOSES ONLY
#measured_period = expected_period
#last_valid_sync_pulse -= 8000
#measured_bin_size = 16000
#Now we know where the last valid clock tick was, so we extrapolate to determine the start of the first bin set
while(encoded_pulses[0] - last_valid_sync_pulse > measured_period):
last_valid_sync_pulse += measured_period
#Experimental correction routine
#Assumes the stream starts with 0s
# if(encoded_pulses[0] - last_valid_sync_pulse > (measured_bin_size * expected_bin_num)):
# last_valid_sync_pulse += measured_period
# while(last_valid_sync_pulse > encoded_pulses[0]):
# last_valid_sync_pulse -= (measured_bin_size/2)
decoded_vals = []
encoded_pulse_index = 0
bin_start_timestamps = [last_valid_sync_pulse]
missing_count = 0
while(last_valid_sync_pulse < max(encoded_pulses) and missing_count < missing_timestamp_limit):
#Take care of empty bin sets here
while(encoded_pulses[encoded_pulse_index] - last_valid_sync_pulse > measured_period and missing_count < missing_timestamp_limit):
last_valid_sync_pulse += measured_period
bin_start_timestamps.append(last_valid_sync_pulse)
decoded_vals.append(FAIL_TIMESTAMP_NO_PHOTON)
missing_count += 1
#We always assume the first pulse here is valid
offset = encoded_pulses[encoded_pulse_index] - last_valid_sync_pulse;
#Append the decoded value to our next index
v = offset_to_val(offset, expected_bin_num, measured_bin_size)
decoded_vals.append(v)
if(v == FAIL_TIMESTAMP_BAD_RANGE):
missing_count += 1
else:
missing_count = 0
#Figure out the next valid timestamp
last_valid_sync_pulse += measured_period
bin_start_timestamps.append(last_valid_sync_pulse)
encoded_pulse_index += 1
#If we're not on the last pulse
if(encoded_pulse_index < len(encoded_pulses)):
#while the next pulse is before last_valid_sync_pulse and there is a next pulse
while(encoded_pulse_index + 1 < len(encoded_pulses) and encoded_pulses[encoded_pulse_index] < last_valid_sync_pulse):
encoded_pulse_index += 1
#otherwise we're done
else:
break
return decoded_vals, bin_start_timestamps, end_of_sync_pulses_timestamp, entangled_pulse_timestamp, valid_sync_pulse_timestamps
#Generates a dummy list of pulses used to test the decode algorithm
#period in ps
#loss rate between 0 and 100
#num dark counts is number of dark coutns to inject
#bin size in ps
def generate_pulse_list(period, num_sync, num_dead, num_bins, bin_size, vals, loss_rate, num_dark_counts):
random.seed()
pulse_list = [0]
#Adding sync pulses
for i in range(0, num_sync-1):
pulse_list.append(pulse_list[-1] + period)
#Time period in which we're looking to insert a pulse
bin_ptr = pulse_list[-1] + (period * num_dead)#Adding dead pulses here
bin_offset = bin_size / 2
#Adding encoded values
for v in vals:
#Figure out the encoding based on current period
encoded_val = (v * bin_size) + bin_offset + bin_ptr
bin_ptr += period#Go to the next bin
pulse_list.append(encoded_val)
#Loss Function
pulse_list_final = []
for p in pulse_list:
#If we sho333
if(not random_percent(loss_rate)):
pulse_list_final.append(p)
#dark count addition
for i in range(0, num_dark_counts):
val = random.choice(pulse_list_final)#Get a random valid pulse
val += random.randint(period*(-2), period*2)#Offset it by some ammmount
pulse_list_final.append(val)#Add it back in
#Make sure the timestamps are in order
pulse_list_final.sort()
return pulse_list_final
# #pulses must be a sorted list
# #expected encoded pulses is the number of these we expect to find
# def decode_pulse_list(pulses, expected_period, expected_bin_num, expected_bin_size):
# print("Starting decode")
# #pre-thing to do is subtract out offset
# pulses.sort()
# ofs = pulses[0]
# for i in range(0, len(pulses)):
# pulses[i] -= ofs
# if(LOG_TO_FILE):
# file = open(logfile,'a')
# new_line = ""
# for p in pulses:
# new_line += str(p) + ","
# file.write(new_line + "\n")
# file.close()
# return [1]
# #Fist thing to do is figure out where the sync pulses end and encoded pulses start
# max_diff = 0
# max_diff_pos = 0
# for i in range(0, len(pulses)-1):
# d = pulses[i+1] - pulses[i]
# if(d > max_diff):
# max_diff = d
# max_diff_pos = i
# first_encoded_pulse_pos = max_diff_pos + 1;
# print("Done separating list of pulses")
# #Now we're going to create objects for each pulse which store a list of their time differences to every other sync pulse
# #If any pulse has two differences which are close enough to the expected period then we'll mark those as valid
# #Now we calculate the period based on the measured differences of the first max_diff_pos pulses
# sync_pulse_vals = pulses[0:max_diff_pos+1]
# period_diffs = []
# sync_pulse_objs= []
# for i in range(0, len(sync_pulse_vals)):
# #Create a new object for pulse i
# spo = sync_pulse(sync_pulse_vals[i])
# for j in range(0, len(sync_pulse_vals)):
# if (j != i):
# d = abs(sync_pulse_vals[j] - sync_pulse_vals[i])
# period_diffs.append(d)
# spo.diffs.append(d)#Append this also to the list for this pulse
# #Record that pulse in our list
# sync_pulse_objs.append(spo)
# periods_final = []
# for p in period_diffs:
# #If this period is within allowable limits
# thresh = abs(p - expected_period) / expected_period
# if(thresh < PERIOD_THRESHOLD):
# periods_final.append(p)
# #If we end up with no successfull period measurement
# if(len(periods_final) == 0):
# print("Error, could not identify any synchronization pulses")
# return []
# #Calculate the measured period
# measured_period = sum(periods_final) / len(periods_final)
# #adjust the bin size to match
# measured_bin_size = (measured_period/expected_period) * expected_bin_size
# print("Measured period was " + str(measured_period) + ", measured bin size was " + str(measured_bin_size))
# #Now go through the list of sync pulses and determine if they are valid
# valid_sync_pulses = []
# for sp in sync_pulse_objs:
# num_valid_diffs = 0
# #Loop through differences and look for those that meet threshold
# for d in sp.diffs:
# thresh = abs(d - measured_period)/measured_period
# if(thresh < SYNC_PERIOD_THRESHOLD):
# num_valid_diffs += 1
# #If we have exactly two differences that meet the threshold
# if(num_valid_diffs == 2):
# #Add it to the list of valid pulses
# valid_sync_pulses.append(sp.val)
# #If there were no valid sync pulses then we fail
# if(len(valid_sync_pulses) < 1):
# print("Cannot decode pulse list, not enough valid sync pulses!")
# return []
# print("Found " + str(len(valid_sync_pulses)) + " valid sync pulses")
# #now we figure out which was the last valid pulse
# last_valid_sync_pulse = 0
# for p in valid_sync_pulses:
# if(p > last_valid_sync_pulse):
# last_valid_sync_pulse = p
# encoded_pulses = pulses[first_encoded_pulse_pos:len(pulses)]
# #Fail if there are no encoded pulses to decode
# if(len(encoded_pulses) < 1):
# print("Cannot decode pulse list, no encoded pulses found!")
# return []
# #Now we know where the last valid clock tick was, so we extrapolate to determine the start of the first bin set
# while(encoded_pulses[0] - last_valid_sync_pulse > measured_period):
# last_valid_sync_pulse += measured_period
# decoded_vals = []
# encoded_pulse_index = 0
# #While we haven't run out of pulses to decode and we haven't decoded more than the expected number
# #while(last_valid_sync_pulse < max(encoded_pulses) and encoded_pulse_index < expected_encoded_pulses):
# while(last_valid_sync_pulse < max(encoded_pulses)):
# #Take care of empty bin sets here
# while(encoded_pulses[encoded_pulse_index] - last_valid_sync_pulse > measured_period):
# last_valid_sync_pulse += measured_period
# decoded_vals.append(FAIL_TIMESTAMP_NO_PHOTON)
# #We always assume the first pulse here is valid
# offset = encoded_pulses[encoded_pulse_index] - last_valid_sync_pulse;
# #Append the decoded value to our next index
# decoded_vals.append(offset_to_val(offset, expected_bin_num, measured_bin_size))
# #Figure out the next valid timestamp
# last_valid_sync_pulse += measured_period
# encoded_pulse_index += 1
# #If we're not on the last pulse
# if(encoded_pulse_index < len(encoded_pulses)):
# #while the next pulse is before last_valid_sync_pulse and there is a next pulse
# while(encoded_pulse_index + 1 < len(encoded_pulses) and encoded_pulses[encoded_pulse_index] < last_valid_sync_pulse):
# encoded_pulse_index += 1
# #otherwise we're done
# else:
# break
# return decoded_vals
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/zynqmp/client/rpu/pm_client.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*
* CONTENT
* File is specific for each PU instance and must exist in order to
* port Power Management code for some new PU.
* Contains PU specific macros and macros to be defined depending on
* the execution environment.
*/
#ifndef PM_CLIENT_H
#define PM_CLIENT_H
#include <xil_exception.h>
#include <xil_io.h>
#include "pm_rpu.h"
#include "pm_defs.h"
#include "pm_common.h"
#ifdef __cplusplus
extern "C" {
#endif
const char* XPm_GetMasterName(void);
#ifdef DEBUG_MODE
#if defined (__GNUC__)
#define pm_print(MSG, ...) xil_printf("%s: "MSG, \
XPm_GetMasterName(), ##__VA_ARGS__)
#elif defined (__ICCARM__)
#define pm_print xil_printf
#endif
#else
#define pm_print(...) {}
#endif
#ifdef __cplusplus
}
#endif
#endif /* PM_CLIENT_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/versal/xsecure_aes.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_aes.c
*
* This file contains AES hardware interface APIs
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -------------------------------------------------------
* 4.0 vns 04/24/2019 Initial release
* 4.1 vns 08/06/2019 Added AES encryption APIs
* har 08/21/2019 Fixed MISRA C violations
* vns 08/23/2019 Initialized status variables
* 4.2 har 01/03/2020 Added checks for return value of XSecure_SssAes
* vns 02/10/2020 Added DPA CM enable/disable function
* rpo 02/27/2020 Removed function prototype and static keyword of
* XSecure_AesKeyLoad, XSecure_AesWaitForDone functions
* har 03/01/2020 Added code to soft reset once key decryption is done
* rpo 03/23/2020 Replaced timeouts with WaitForEvent and code clean up
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsecure_utils.h"
#include "xsecure_aes.h"
#include "xsecure_aes_core_hw.h"
#include "xil_util.h"
#include "xsecure_error.h"
/************************** Constant Definitions *****************************/
#define XSECURE_MAX_KEY_SOURCES XSECURE_AES_EXPANDED_KEYS
#define XSECURE_AES_DISABLE_KUP_IV_UPDATE (0x0U)
#define XSECURE_ENABLE_BYTE_SWAP (0x1U)
#define XSECURE_DISABLE_BYTE_SWAP (0x0U)
/**************************** Type Definitions *******************************/
typedef struct {
u32 RegOffset;
u32 KeySrcSelVal;
u8 UsrWrAllowed;
u8 DecAllowed;
u8 EncAllowed;
u8 KeyDecSrcAllowed;
u32 KeyDecSrcSelVal;
u32 KeyClearVal;
} XSecure_AesKeyLookup;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static u32 XSecure_AesWaitForDone(XSecure_Aes *InstancePtr);
static u32 XSecure_AesKeyLoad(XSecure_Aes *InstancePtr,
XSecure_AesKeySrc KeySrc, XSecure_AesKeySize KeySize);
static void XSecure_AesPmcDmaCfgEndianness(XPmcDma *InstancePtr,
XPmcDma_Channel Channel, u8 EndianType);
static u32 XSecure_AesKekWaitForDone(XSecure_Aes *InstancePtr);
static u32 XSecure_AesDpaCmDecryptKat(XSecure_Aes *AesInstance,
u32 *KeyPtr, u32 *DataPtr, u32 *OutputPtr);
/************************** Variable Definitions *****************************/
static const XSecure_AesKeyLookup AesKeyLookupTbl [XSECURE_MAX_KEY_SOURCES] =
{
/* BBRAM_KEY */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_BBRAM_KEY,
FALSE,
TRUE,
TRUE,
TRUE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_INVALID_CFG
},
/* BBRAM_RED_KEY */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_BBRAM_RD_KEY,
FALSE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_KEY_DEC_SEL_BBRAM_RED,
XSECURE_AES_KEY_CLEAR_BBRAM_RED_KEY_MASK
},
/* BH_KEY */
{ XSECURE_AES_BH_KEY_0_OFFSET,
XSECURE_AES_KEY_SEL_BH_KEY,
TRUE,
TRUE,
TRUE,
TRUE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_BH_KEY_MASK
},
/* BH_RED_KEY */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_BH_RD_KEY,
FALSE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_KEY_DEC_SEL_BH_RED,
XSECURE_AES_KEY_CLEAR_BH_RED_KEY_MASK
},
/* EFUSE_KEY */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_EFUSE_KEY,
FALSE,
TRUE,
TRUE,
TRUE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_EFUSE_KEY_MASK
},
/* EFUSE_RED_KEY */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_EFUSE_RED_KEY,
FALSE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_KEY_DEC_SEL_EFUSE_RED,
XSECURE_AES_KEY_CLEAR_EFUSE_RED_KEY_MASK
},
/* EFUSE_USER_KEY_0 */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_EFUSE_USR_KEY0,
FALSE,
TRUE,
TRUE,
TRUE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_EFUSE_USER_KEY_0_MASK
},
/* EFUSE_USER_KEY_1 */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_EFUSE_USR_KEY1,
FALSE,
TRUE,
TRUE,
TRUE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_EFUSE_USER_KEY_1_MASK
},
/* EFUSE_USER_RED_KEY_0 */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_EFUSE_USR_RD_KEY0,
FALSE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_KEY_DEC_SEL_EFUSE_USR0_RED,
XSECURE_AES_KEY_CLEAR_EFUSE_USER_RED_KEY_0_MASK
},
/* EFUSE_USER_RED_KEY_1 */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_EFUSE_USR_RD_KEY1,
FALSE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_KEY_DEC_SEL_EFUSE_USR1_RED,
XSECURE_AES_KEY_CLEAR_EFUSE_USER_RED_KEY_1_MASK
},
/* KUP_KEY */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_KUP_KEY,
FALSE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_KUP_KEY_MASK
},
/* FAMILY_KEY */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_FAMILY_KEY,
FALSE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_INVALID_CFG
},
/* PUF_KEY */
{ XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_SEL_PUF_KEY,
FALSE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_PUF_KEY_MASK
},
/* USER_KEY_0 */
{ XSECURE_AES_USER_KEY_0_0_OFFSET,
XSECURE_AES_KEY_SEL_USR_KEY_0,
TRUE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_USER_KEY_0_MASK
},
/* USER_KEY_1 */
{ XSECURE_AES_USER_KEY_1_0_OFFSET,
XSECURE_AES_KEY_SEL_USR_KEY_1,
TRUE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_USER_KEY_1_MASK
},
/* USER_KEY_2 */
{ XSECURE_AES_USER_KEY_2_0_OFFSET,
XSECURE_AES_KEY_SEL_USR_KEY_2,
TRUE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_USER_KEY_2_MASK
},
/* USER_KEY_3 */
{ XSECURE_AES_USER_KEY_3_0_OFFSET,
XSECURE_AES_KEY_SEL_USR_KEY_3,
TRUE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_USER_KEY_3_MASK
},
/* USER_KEY_4 */
{ XSECURE_AES_USER_KEY_4_0_OFFSET,
XSECURE_AES_KEY_SEL_USR_KEY_4,
TRUE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_USER_KEY_4_MASK
},
/* USER_KEY_5 */
{ XSECURE_AES_USER_KEY_5_0_OFFSET,
XSECURE_AES_KEY_SEL_USR_KEY_6,
TRUE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_USER_KEY_5_MASK
},
/* USER_KEY_6 */
{ XSECURE_AES_USER_KEY_6_0_OFFSET,
XSECURE_AES_KEY_SEL_USR_KEY_6,
TRUE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_USER_KEY_6_MASK
},
/* USER_KEY_7 */
{ XSECURE_AES_USER_KEY_7_0_OFFSET,
XSECURE_AES_KEY_SEL_USR_KEY_7,
TRUE,
TRUE,
TRUE,
FALSE,
XSECURE_AES_INVALID_CFG,
XSECURE_AES_KEY_CLEAR_USER_KEY_7_MASK
}
};
/*****************************************************************************/
/**
* @brief
* This function initializes the instance pointer.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param PmcDmaPtr Pointer to the XPmcDma instance.
*
* @return XST_SUCCESS if initialization was successful.
*
* @note All the inputs are accepted in little endian format, but AES
* engine accepts the data in big endianness, this will be taken
* care while passing data to AES engine.
*
******************************************************************************/
u32 XSecure_AesInitialize(XSecure_Aes *InstancePtr, XPmcDma *PmcDmaPtr)
{
u32 Status = (u32)XST_FAILURE;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(PmcDmaPtr != NULL);
/* Initialize the instance */
InstancePtr->BaseAddress = XSECURE_AES_BASEADDR;
InstancePtr->PmcDmaPtr = PmcDmaPtr;
InstancePtr->AesState = XSECURE_AES_INITIALIZED;
/* Clear all key zeroization register */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_KEY_CLEAR_OFFSET, XSECURE_AES_KEY_CLEAR_ALL_AES_KEYS);
XSecure_SssInitialize(&(InstancePtr->SssInstance));
XSecure_ReleaseReset(InstancePtr->BaseAddress,
XSECURE_AES_SOFT_RST_OFFSET);
Status = XST_SUCCESS;
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function enables or disables DPA counter measures in AES engine based
* on user input.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param DpaCmCfg User choice to enable/disable DPA CM.
* - TRUE - to enable AES DPA counter measure (Default setting)
* - FALSE - to disable AES DPA counter measure
*
* @return
* - XSECURE_AES_DPA_CM_NOT_SUPPORTED if DPA CM is disbaled on chip.
* (Enabling/Disabling in AES engine does not impact functionality)
* - XST_SUCCESS if configuration is success.
*
******************************************************************************/
u32 XSecure_AesSetDpaCm(XSecure_Aes *InstancePtr, u32 DpaCmCfg)
{
u32 Status = (u32)XST_FAILURE;
u32 ReadReg;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((DpaCmCfg == TRUE) ||
(DpaCmCfg == FALSE));
/* Chip has DPA CM support */
if ((XSecure_In32(XSECURE_EFUSE_SECURITY_MISC1) &
XSECURE_EFUSE_DPA_CM_DIS_MASK) == 0x00U) {
/* Disable/enable DPA CM inside AES engine */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_CM_EN_OFFSET, DpaCmCfg);
/* Verify status of CM */
ReadReg = XSecure_ReadReg(InstancePtr->BaseAddress,
XSECURE_AES_STATUS_OFFSET);
ReadReg = (ReadReg & XSECURE_AES_STATUS_CM_ENABLED_MASK) >>
XSECURE_AES_STATUS_CM_ENABLED_SHIFT;
if (ReadReg == DpaCmCfg) {
Status = (u32)XST_SUCCESS;
}
}
else {
Status = (u32)XSECURE_AES_DPA_CM_NOT_SUPPORTED;
}
return Status;
}
/*****************************************************************************/
/**
*
* @brief
* This function writes the key provided into the specified AES key registers.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param KeySrc Key Source to be selected to which provided
* key should be updated.
* - XSECURE_AES_USER_KEY_0
* - XSECURE_AES_USER_KEY_1
* - XSECURE_AES_USER_KEY_2
* - XSECURE_AES_USER_KEY_3
* - XSECURE_AES_USER_KEY_4
* - XSECURE_AES_USER_KEY_5
* - XSECURE_AES_USER_KEY_6
* - XSECURE_AES_USER_KEY_7
* - XSECURE_AES_BH_KEY
* @param KeySize A variable of type XSecure_AesKeySize, which
* holds the size of the input key to be written.
* - XSECURE_AES_KEY_SIZE_128 for 128 bit key size
* - XSECURE_AES_KEY_SIZE_256 for 256 bit key size
* @param KeyAddr Address of a buffer which should contain
* the key to be written.
*
* @return
* - XST_SUCCESS on successful written
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesWriteKey(XSecure_Aes *InstancePtr, XSecure_AesKeySrc KeySrc,
XSecure_AesKeySize KeySize, u64 KeyAddr)
{
u32 Offset;
u32 Index = 0U;
u32 *Key;
u32 KeySizeInWords;
u32 Status = (u32)XST_FAILURE;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(AesKeyLookupTbl[KeySrc].UsrWrAllowed == TRUE);
Xil_AssertNonvoid((XSECURE_AES_KEY_SIZE_128 == KeySize) ||
(XSECURE_AES_KEY_SIZE_256 == KeySize));
Xil_AssertNonvoid(KeyAddr != 0x00U);
Key = (u32 *)(INTPTR)KeyAddr;
if ((XSECURE_AES_BH_KEY == KeySrc) &&
(XSECURE_AES_KEY_SIZE_128 == KeySize)) {
Status = XST_FAILURE;
goto END;
}
if (XSECURE_AES_KEY_SIZE_128 == KeySize) {
KeySizeInWords = XSECURE_AES_KEY_SIZE_128BIT_WORDS;
}
else {
KeySizeInWords = XSECURE_AES_KEY_SIZE_256BIT_WORDS;
}
Offset = AesKeyLookupTbl[KeySrc].RegOffset;
if (Offset == XSECURE_AES_INVALID_CFG) {
Status = XST_FAILURE;
goto END;
}
Offset = Offset + (KeySizeInWords * XSECURE_WORD_SIZE) -
XSECURE_WORD_SIZE;
for (Index = 0U; Index < KeySizeInWords; Index++) {
XSecure_WriteReg(InstancePtr->BaseAddress, Offset,
Xil_Htonl(Key[Index]));
Offset = Offset - XSECURE_WORD_SIZE;
}
Status = XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
* This function decrypts the key which is in KEK/Obfuscated key form and
* exist in either of the boot header/Efuse/BBRAM and updates the mentioned
* destination red key register with corresponding red key.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param KeyType The source of key to be used for decryption
* - XSECURE_BLACK_KEY
* - XSECURE_OBFUSCATED_KEY
* @param DecKeySrc Select key source which holds KEK and needs to be
* decrypted
* @param DstKeySrc Select the key in which decrypted red key should be
* updated
* @param IvAddr Address of IV holding buffer for decryption
* of the key.
* @param KeySize A variable of type XSecure_AesKeySize, which
* specifies the size of the key.
* - XSECURE_AES_KEY_SIZE_128 for 128 bit key size
* - XSECURE_AES_KEY_SIZE_256 for 256 bit key size
*
* @return
* - XST_SUCCESS on successful key decryption.
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesKekDecrypt(XSecure_Aes *InstancePtr, XSecure_AesKekType KeyType,
XSecure_AesKeySrc DecKeySrc,
XSecure_AesKeySrc DstKeySrc, u64 IvAddr, u32 KeySize)
{
u32 Status = (u32)XST_FAILURE;
XSecure_AesKeySrc KeySrc;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((KeyType == XSECURE_BLACK_KEY) ||
(KeyType == XSECURE_OBFUSCATED_KEY));
if ((AesKeyLookupTbl[DecKeySrc].KeyDecSrcAllowed != TRUE) ||
(AesKeyLookupTbl[DstKeySrc].KeyDecSrcSelVal ==
XSECURE_AES_INVALID_CFG)) {
Status = XST_INVALID_PARAM;
goto END;
}
XSecure_ReleaseReset(InstancePtr->BaseAddress,
XSECURE_AES_SOFT_RST_OFFSET);
/* Configure the SSS for AES. */
if (InstancePtr->PmcDmaPtr->Config.DeviceId == 0) {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_DMA0);
}
else {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA1, XSECURE_SSS_DMA1);
}
if (Status != (u32)XST_SUCCESS) {
goto END;
}
if (KeyType == XSECURE_OBFUSCATED_KEY) {
KeySrc = XSECURE_AES_FAMILY_KEY;
}
else if (KeyType == XSECURE_BLACK_KEY) {
KeySrc = XSECURE_AES_PUF_KEY;
}
else {
Status = XST_FAILURE;
goto END;
}
Status = XSecure_AesKeyLoad(InstancePtr, KeySrc, KeySize);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Start the message. */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_START_MSG_OFFSET,
XSECURE_AES_START_MSG_VAL_MASK);
/* Enable PMC DMA Src channel for byte swapping.*/
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_ENABLE_BYTE_SWAP);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_DATA_SWAP_OFFSET, 0x1U);
/* Push IV into the AES engine. */
XPmcDma_64BitTransfer(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL,
IvAddr, IvAddr >> 32, XSECURE_SECURE_GCM_TAG_SIZE/4U, (u8)1);
XPmcDma_WaitForDone(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_DATA_SWAP_OFFSET, 0x0U);
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
/* Select key decryption */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_KEY_DEC_OFFSET, XSECURE_AES_KEY_DEC_MASK);
/* Decrypt selection */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_KEY_DEC_SEL_OFFSET,
AesKeyLookupTbl[DstKeySrc].KeyDecSrcSelVal);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_KEY_SEL_OFFSET,
AesKeyLookupTbl[DecKeySrc].KeySrcSelVal);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_KEY_DEC_TRIG_OFFSET, (u32)0x1);
/* Wait for AES Decryption completion. */
Status = XSecure_AesKekWaitForDone(InstancePtr);
if(Status != (u32)XST_SUCCESS)
{
Status = (u32)XST_FAILURE;
goto END;
}
END:
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_AES_SOFT_RST_OFFSET);
/* Select key decryption */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_KEY_DEC_OFFSET, 0U);
return Status;
}
/*****************************************************************************/
/**
*
* @brief
* This function initializes the AES engine for decryption.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param KeySrc Key Source for decryption of the data.
* @param KeySize Size of the AES key to be used for decryption.
* - XSECURE_AES_KEY_SIZE_128 for 128 bit key size
* - XSECURE_AES_KEY_SIZE_256 for 256 bit key size
* @param IvAddr Address to the buffer holding IV.
*
* @return
* - XST_SUCCESS on successful init
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesDecryptInit(XSecure_Aes *InstancePtr, XSecure_AesKeySrc KeySrc,
XSecure_AesKeySize KeySize, u64 IvAddr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(KeySrc < XSECURE_MAX_KEY_SOURCES);
Xil_AssertNonvoid((KeySize == XSECURE_AES_KEY_SIZE_128) ||
(KeySize == XSECURE_AES_KEY_SIZE_256));
Xil_AssertNonvoid(IvAddr != 0x00U);
Xil_AssertNonvoid(InstancePtr->AesState != XSECURE_AES_UNINITIALIZED);
/* Key selected does not allow decryption */
if (AesKeyLookupTbl[KeySrc].DecAllowed == FALSE) {
Status = XST_FAILURE;
goto END;
}
/* Configure AES for decryption */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_MODE_OFFSET, 0x0);
/* Configure the SSS for AES. */
if (InstancePtr->PmcDmaPtr->Config.DeviceId == 0) {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_DMA0);
}
else {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA1, XSECURE_SSS_DMA1);
}
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Load key for decryption */
Status = XSecure_AesKeyLoad(InstancePtr, KeySrc, KeySize);
if (Status != XST_SUCCESS) {
goto END;
}
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_DATA_SWAP_OFFSET, XSECURE_AES_DATA_SWAP_VAL_MASK);
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_ENABLE_BYTE_SWAP);
/* Start the message. */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_START_MSG_OFFSET,
XSECURE_AES_START_MSG_VAL_MASK);
/* Push IV */
XPmcDma_64BitTransfer(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL,
IvAddr, IvAddr >> 32,
XSECURE_SECURE_GCM_TAG_SIZE/XSECURE_WORD_SIZE, 0U);
XPmcDma_WaitForDone(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL);
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_DISABLE_BYTE_SWAP);
/* Update the state */
InstancePtr->AesState = XSECURE_AES_DECRYPT_INITIALIZED;
Status = XST_SUCCESS;
END:
if (Status != (u32)XST_SUCCESS) {
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_AES_SOFT_RST_OFFSET);
}
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function is used to update the AES engine for decryption with provided
* data and stores the decrypted data at specified address.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param InDataAddr Address of the encrypted data which needs to be
* decrypted.
* @param OutDataAddr Address of output buffer where the decrypted
* to be updated.
* @param Size Size of data to be decrypted in bytes,
* whereas number of bytes provided should be multiples of 4.
* @param IsLastChunk If this is the last update of data to be
* decrypted, this parameter should be set to TRUE otherwise FALSE.
*
* @return
* - XST_SUCCESS on successful decryption of the data.
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesDecryptUpdate(XSecure_Aes *InstancePtr, u64 InDataAddr,
u64 OutDataAddr, u32 Size, u8 IsLastChunk)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((Size % XSECURE_WORD_SIZE) == 0x00U);
Xil_AssertNonvoid((IsLastChunk == TRUE) || (IsLastChunk == FALSE));
Xil_AssertNonvoid(InstancePtr->AesState ==
XSECURE_AES_DECRYPT_INITIALIZED);
/* Enable PMC DMA Src and Dst channels for byte swapping.*/
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_ENABLE_BYTE_SWAP);
if ((u32)OutDataAddr != XSECURE_AES_NO_CFG_DST_DMA) {
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL, XSECURE_ENABLE_BYTE_SWAP);
}
/* Configure the SSS for AES. */
if (InstancePtr->PmcDmaPtr->Config.DeviceId == 0) {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_DMA0);
}
else {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA1, XSECURE_SSS_DMA1);
}
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Configure destination */
if ((u32)OutDataAddr != XSECURE_AES_NO_CFG_DST_DMA) {
XPmcDma_64BitTransfer(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL,
OutDataAddr, OutDataAddr >> 32,
Size/XSECURE_WORD_SIZE, 0);
}
XPmcDma_64BitTransfer(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL,
InDataAddr, InDataAddr >> 32,
Size/XSECURE_WORD_SIZE, IsLastChunk);
/* Wait for the SRC DMA completion. */
XPmcDma_WaitForDone(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL);
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
if ((u32)OutDataAddr != XSECURE_AES_NO_CFG_DST_DMA) {
/* Wait for the DST DMA completion. */
XPmcDma_WaitForDone(InstancePtr->PmcDmaPtr, XPMCDMA_DST_CHANNEL);
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(InstancePtr->PmcDmaPtr, XPMCDMA_DST_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
}
/* Clear endianness */
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_DISABLE_BYTE_SWAP);
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL, XSECURE_DISABLE_BYTE_SWAP);
Status = (u32)XST_SUCCESS;
END:
if (Status != (u32)XST_SUCCESS) {
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_AES_SOFT_RST_OFFSET);
}
return Status;
}
/*****************************************************************************/
/**
*
* @brief
* This function verifies the GCM tag provided for the data decrypted
* till the point.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param GcmTagAddr Address of a buffer which should holds
* GCM Tag.
*
* @return
* - XST_SUCCESS on successful GCM tag verification
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesDecryptFinal(XSecure_Aes *InstancePtr, u64 GcmTagAddr)
{
u32 Status = (u32)XST_FAILURE;
u32 NextBlkLen = 0U;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(GcmTagAddr != 0x00U);
Xil_AssertNonvoid(InstancePtr->AesState ==
XSECURE_AES_DECRYPT_INITIALIZED);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_DATA_SWAP_OFFSET, 0x1U);
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_ENABLE_BYTE_SWAP);
/* Configure the SSS for AES. */
if (InstancePtr->PmcDmaPtr->Config.DeviceId == 0) {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_DMA0);
}
else {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA1, XSECURE_SSS_DMA1);
}
if (Status != (u32)XST_SUCCESS) {
goto END;
}
XPmcDma_64BitTransfer(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, GcmTagAddr, GcmTagAddr >> 32,
XSECURE_SECURE_GCM_TAG_SIZE/XSECURE_WORD_SIZE, 0);
/* Wait for the Src DMA completion. */
XPmcDma_WaitForDone(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL);
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
/* Wait for AES Decryption completion. */
Status = XSecure_AesWaitForDone(InstancePtr);
if (Status != XST_SUCCESS) {
goto END;
}
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_DISABLE_BYTE_SWAP);
/* Get the AES status to know if GCM check passed. */
Status = XSecure_ReadReg(InstancePtr->BaseAddress,
XSECURE_AES_STATUS_OFFSET);
Status &= XSECURE_AES_STATUS_GCM_TAG_PASS_MASK;
if (Status != XSECURE_AES_STATUS_GCM_TAG_PASS_MASK) {
Status = XSECURE_AES_GCM_TAG_MISMATCH;
goto END;
}
else {
Status = XST_SUCCESS;
}
Status = XSecure_AesGetNxtBlkLen(InstancePtr, &NextBlkLen);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
END:
if ((NextBlkLen == 0U) || (Status != (u32)XST_SUCCESS)) {
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_AES_SOFT_RST_OFFSET);
}
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_DATA_SWAP_OFFSET, 0x0U);
return Status;
}
/*****************************************************************************/
/**
*
* @brief
* This function decrypts the size (length) number of bytes of the passed in
* InDataAddr (source) buffer and stores the decrypted data in the OutDataAddr
* (destination) buffer and verifies GcmTagAddr.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param InDataAddr Address of the encrypted data which needs to be
* decrypted.
* @param OutDataAddr Address of output buffer where the decrypted
* to be updated.
* @param Size Size of data to be decrypted in bytes,
* whereas number of bytes provided should be multiples of 4.
* @param GcmTagAddr Address of a buffer which should contain
* GCM Tag.
*
* @return
* - XST_SUCCESS on successful GCM tag verification
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesDecryptData(XSecure_Aes *InstancePtr, u64 InDataAddr,
u64 OutDataAddr, u32 Size, u64 GcmTagAddr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((Size % XSECURE_WORD_SIZE) == 0x00U);
Xil_AssertNonvoid(GcmTagAddr != 0x00U);
Xil_AssertNonvoid(InstancePtr->AesState ==
XSECURE_AES_DECRYPT_INITIALIZED);
/* Update AES engine with data */
Status = XSecure_AesDecryptUpdate(InstancePtr, InDataAddr, OutDataAddr,
Size, TRUE);
if (Status != XST_SUCCESS) {
goto END;
}
/* Verify GCM tag */
Status = XSecure_AesDecryptFinal(InstancePtr, GcmTagAddr);
if (Status != XST_SUCCESS) {
goto END;
}
END:
return Status;
}
/*****************************************************************************/
/**
*
* @brief
* This function initializes the AES engine for encryption.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param KeySrc Key Source for encryption.
* @param KeySize Size of the AES key to be used for encryption.
* - XSECURE_AES_KEY_SIZE_128 for 128 bit key size
* - XSECURE_AES_KEY_SIZE_256 for 256 bit key size
* @param IvAddr Address to the buffer holding IV.
*
* @return
* - XST_SUCCESS on successful init
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesEncryptInit(XSecure_Aes *InstancePtr, XSecure_AesKeySrc KeySrc,
XSecure_AesKeySize KeySize, u64 IvAddr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(KeySrc < XSECURE_MAX_KEY_SOURCES);
Xil_AssertNonvoid((KeySize == XSECURE_AES_KEY_SIZE_128) ||
(KeySize == XSECURE_AES_KEY_SIZE_256));
Xil_AssertNonvoid(IvAddr != 0x00U);
Xil_AssertNonvoid(InstancePtr->AesState != XSECURE_AES_UNINITIALIZED);
/* Key selected does not allow Encryption */
if (AesKeyLookupTbl[KeySrc].EncAllowed == FALSE) {
Status = XST_FAILURE;
goto END;
}
/* Configure AES for Encryption */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_MODE_OFFSET, XSECURE_AES_MODE_ENC_DEC_N_MASK);
/* Configure the SSS for AES. */
if (InstancePtr->PmcDmaPtr->Config.DeviceId == 0) {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_DMA0);
}
else {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA1, XSECURE_SSS_DMA1);
}
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Load key for encryption */
Status = XSecure_AesKeyLoad(InstancePtr, KeySrc, KeySize);
if (Status != XST_SUCCESS) {
goto END;
}
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_DATA_SWAP_OFFSET, XSECURE_AES_DATA_SWAP_VAL_MASK);
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_ENABLE_BYTE_SWAP);
/* Start the message. */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_START_MSG_OFFSET,
XSECURE_AES_START_MSG_VAL_MASK);
/* Push IV */
XPmcDma_64BitTransfer(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL,
IvAddr, IvAddr >> 32,
XSECURE_SECURE_GCM_TAG_SIZE/XSECURE_WORD_SIZE, 0U);
XPmcDma_WaitForDone(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL);
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_DISABLE_BYTE_SWAP);
/* Update the state */
InstancePtr->AesState = XSECURE_AES_ENCRYPT_INITIALIZED;
END:
if (Status != (u32)XST_SUCCESS) {
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_AES_SOFT_RST_OFFSET);
}
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function is used to update the AES engine for encryption with provided
* data and stores the decrypted data at specified address.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param InDataAddr Address of the encrypted data which needs to be
* encrypted.
* @param OutDataAddr Address of output buffer where the encrypted data
* to be updated.
* @param Size Size of data to be encrypted in bytes,
* whereas number of bytes provided should be multiples of 4.
* @param IsLastChunk If this is the last update of data to be
* encrypted, this parameter should be set to TRUE otherwise FALSE.
*
* @return
* - XST_SUCCESS on successful encryption of the data.
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesEncryptUpdate(XSecure_Aes *InstancePtr, u64 InDataAddr,
u64 OutDataAddr, u32 Size, u8 IsLastChunk)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((Size % XSECURE_WORD_SIZE) == 0x00U);
Xil_AssertNonvoid((IsLastChunk == TRUE) || (IsLastChunk == FALSE));
Xil_AssertNonvoid(InstancePtr->AesState ==
XSECURE_AES_ENCRYPT_INITIALIZED);
/* Enable PMC DMA Src and Dst channels for byte swapping.*/
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_ENABLE_BYTE_SWAP);
if ((u32)OutDataAddr != XSECURE_AES_NO_CFG_DST_DMA) {
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL, XSECURE_ENABLE_BYTE_SWAP);
}
/* Configure the SSS for AES. */
if (InstancePtr->PmcDmaPtr->Config.DeviceId == 0) {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_DMA0);
}
else {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA1, XSECURE_SSS_DMA1);
}
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Configure destination */
if ((u32)OutDataAddr != XSECURE_AES_NO_CFG_DST_DMA) {
XPmcDma_64BitTransfer(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL,
OutDataAddr, OutDataAddr >> 32U,
Size/XSECURE_WORD_SIZE, FALSE);
}
XPmcDma_64BitTransfer(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL,
InDataAddr, InDataAddr >> 32U,
Size/XSECURE_WORD_SIZE, IsLastChunk);
/* Wait for the SRC DMA completion. */
XPmcDma_WaitForDone(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL);
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(InstancePtr->PmcDmaPtr, XPMCDMA_SRC_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
if ((u32)OutDataAddr != XSECURE_AES_NO_CFG_DST_DMA) {
/* Wait for the DST DMA completion. */
XPmcDma_WaitForDone(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL);
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
}
/* Clear endianness */
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_DISABLE_BYTE_SWAP);
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL, XSECURE_DISABLE_BYTE_SWAP);
Status = (u32)XST_SUCCESS;
END:
if (Status != (u32)XST_SUCCESS) {
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_AES_SOFT_RST_OFFSET);
}
return Status;
}
/*****************************************************************************/
/**
*
* @brief
* This function updates the GCM tag for the encrypted data.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param GcmTagAddr Address to the buffer of GCM tag size, where the API
* updates GCM tag.
*
* @return
* - XST_SUCCESS on successful GCM tag updation
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesEncryptFinal(XSecure_Aes *InstancePtr, u64 GcmTagAddr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(GcmTagAddr != 0x00U);
Xil_AssertNonvoid(InstancePtr->AesState ==
XSECURE_AES_ENCRYPT_INITIALIZED);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_DATA_SWAP_OFFSET,
XSECURE_AES_DATA_SWAP_VAL_MASK);
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL, XSECURE_ENABLE_BYTE_SWAP);
/* Configure the SSS for AES. */
if (InstancePtr->PmcDmaPtr->Config.DeviceId == 0) {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_DMA0);
}
else {
Status = XSecure_SssAes(&InstancePtr->SssInstance,
XSECURE_SSS_DMA1, XSECURE_SSS_DMA1);
}
if (Status != (u32)XST_SUCCESS) {
goto END;
}
XPmcDma_64BitTransfer(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL,
GcmTagAddr, GcmTagAddr >> 32,
XSECURE_SECURE_GCM_TAG_SIZE/XSECURE_WORD_SIZE, 0);
/* Wait for the DST DMA completion. */
XPmcDma_WaitForDone(InstancePtr->PmcDmaPtr, XPMCDMA_DST_CHANNEL);
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(InstancePtr->PmcDmaPtr, XPMCDMA_DST_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
/* Wait for AES Decryption completion. */
Status = XSecure_AesWaitForDone(InstancePtr);
if (Status != XST_SUCCESS) {
goto END;
}
XSecure_AesPmcDmaCfgEndianness(InstancePtr->PmcDmaPtr,
XPMCDMA_DST_CHANNEL, XSECURE_DISABLE_BYTE_SWAP);
END:
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_AES_SOFT_RST_OFFSET);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_DATA_SWAP_OFFSET, 0x0U);
return Status;
}
/*****************************************************************************/
/**
*
* @brief
* This function encrypts size (length) number of bytes of the passed in
* InDataAddr (source) buffer and stores the encrypted data along with its
* associated 16 byte tag in the OutDataAddr (destination) buffer and
* GcmTagAddr (buffer) respectively.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param InDataAddr Address of the data which needs to be
* encrypted.
* @param OutDataAddr Address of output buffer where the encrypted data
* to be updated.
* @param Size Size of data to be encrypted in bytes,
* whereas number of bytes provided should be multiples of 4.
*
* @return
* - XST_SUCCESS on successful encryption.
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesEncryptData(XSecure_Aes *InstancePtr, u64 InDataAddr,
u64 OutDataAddr, u32 Size, u64 GcmTagAddr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((Size % XSECURE_WORD_SIZE) == 0x00U);
Xil_AssertNonvoid(GcmTagAddr != 0x00U);
Xil_AssertNonvoid(InstancePtr->AesState ==
XSECURE_AES_ENCRYPT_INITIALIZED);
/* Update the data to AES engine */
Status = XSecure_AesEncryptUpdate(InstancePtr, InDataAddr, OutDataAddr,
Size, TRUE);
if (Status != XST_SUCCESS) {
goto END;
}
/* Call Encrypt final */
Status = XSecure_AesEncryptFinal(InstancePtr, GcmTagAddr);
if (Status != XST_SUCCESS) {
goto END;
}
END:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function waits for AES engine completes key loading.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
*
* @return
* - XST_SUCCESS if the AES engine completes key loading.
* - XST_FAILURE if a timeout has occurred.
*
******************************************************************************/
static u32 XSecure_AesWaitKeyLoad(XSecure_Aes *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Status = Xil_WaitForEvent(((InstancePtr)->BaseAddress +
XSECURE_AES_STATUS_OFFSET),
XSECURE_AES_STATUS_KEY_INIT_DONE_MASK,
XSECURE_AES_STATUS_KEY_INIT_DONE_MASK,
XSECURE_AES_TIMEOUT_MAX);
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function sets AES engine to update key and IV during decryption of
* secure header or footer of encrypted partition.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param Config
* - TRUE - to enable KUP and IV update
* - FALSE -to disable KUP and IV update
*
* @return
* - XST_SUCCESS on successful configuration.
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesCfgKupIv(XSecure_Aes *InstancePtr, u32 Config)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((Config == FALSE) ||
(Config == TRUE));
if (Config == XSECURE_AES_DISABLE_KUP_IV_UPDATE) {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_KUP_WR_OFFSET, XSECURE_AES_DISABLE_KUP_IV_UPDATE);
}
else {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_KUP_WR_OFFSET,
(XSECURE_AES_KUP_WR_KEY_SAVE_MASK |
XSECURE_AES_KUP_WR_IV_SAVE_MASK));
}
Status = XST_SUCCESS;
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function gives the AES next block length after decryption of PDI block
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param Size Pointer to a 32 bit variable where next block
* length will be updated.
*
* @return XST_SUCCESS on successful configuration.
*
******************************************************************************/
u32 XSecure_AesGetNxtBlkLen(XSecure_Aes *InstancePtr, u32 *Size)
{
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Size != NULL);
*Size = Xil_Htonl(XSecure_ReadReg(InstancePtr->BaseAddress,
XSECURE_AES_IV_3_OFFSET)) * 4;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* @brief
* This function configures and loads AES key from selected key source.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param KeySrc Variable is of type XSecure_AesKeySrc
* which mentiones the key source to be loaded into AES engine.
* @param KeySize Size of the key selected.
*
* @return
* - XST_SUCCESS on successful key load
* - Error code on failure.
*
******************************************************************************/
u32 XSecure_AesKeyLoad(XSecure_Aes *InstancePtr, XSecure_AesKeySrc KeySrc,
XSecure_AesKeySize KeySize)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(KeySrc < XSECURE_MAX_KEY_SOURCES);
Xil_AssertNonvoid((KeySize == XSECURE_AES_KEY_SIZE_128) ||
(KeySize == XSECURE_AES_KEY_SIZE_256));
/* Load Key Size */
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_AES_KEY_SIZE_OFFSET, KeySize);
/* AES key source selection */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_KEY_SEL_OFFSET,
AesKeyLookupTbl[KeySrc].KeySrcSelVal);
/* Trig loading of key. */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_AES_KEY_LOAD_OFFSET,
XSECURE_AES_KEY_LOAD_VAL_MASK);
/* Wait for AES key loading.*/
Status = XSecure_AesWaitKeyLoad(InstancePtr);
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function waits for AES completion.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
*
* @return
* - XST_SUCCESS on successful key load
* - Error code on failure.
*
******************************************************************************/
u32 XSecure_AesWaitForDone(XSecure_Aes *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Status = Xil_WaitForEvent(((InstancePtr)->BaseAddress +
XSECURE_AES_STATUS_OFFSET),
XSECURE_AES_STATUS_DONE_MASK,
XSECURE_AES_STATUS_DONE_MASK,
XSECURE_AES_TIMEOUT_MAX);
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function waits for AES key decryption completion.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
*
* @return
* - XST_SUCCESS on success
* - Error code on failure.
*
******************************************************************************/
static u32 XSecure_AesKekWaitForDone(XSecure_Aes *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Status = Xil_WaitForEvent(((InstancePtr)->BaseAddress +
XSECURE_AES_STATUS_OFFSET),
XSECURE_AES_STATUS_BLK_KEY_DEC_DONE_MASK,
XSECURE_AES_STATUS_BLK_KEY_DEC_DONE_MASK,
XSECURE_AES_TIMEOUT_MAX);
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function zeroizes the selected AES key storage register.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param KeySrc Select the key source which needs to be zeroized.
*
* @return
* - XST_SUCCESS when key zeroization is success.
* - Error code on failure
*
******************************************************************************/
u32 XSecure_AesKeyZero(XSecure_Aes *InstancePtr, XSecure_AesKeySrc KeySrc)
{
u32 KeyClearVal;
u32 Status = (u32)XST_FAILURE;
u32 Mask;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid (KeySrc <= XSECURE_AES_EXPANDED_KEYS);
if (KeySrc == XSECURE_AES_EXPANDED_KEYS) {
Mask = XSECURE_AES_KEY_CLEAR_AES_KEY_ZEROIZE_MASK;
}
else if (AesKeyLookupTbl[KeySrc].KeyClearVal != 0xFFFFFFFF) {
Mask = AesKeyLookupTbl[KeySrc].KeyClearVal;
}
else {
Status = XST_INVALID_PARAM;
goto END;
}
KeyClearVal = XSecure_ReadReg(InstancePtr->BaseAddress,
XSECURE_AES_KEY_CLEAR_OFFSET);
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_AES_KEY_CLEAR_OFFSET,
(KeyClearVal | Mask));
Status = Xil_WaitForEvent(((InstancePtr)->BaseAddress +
XSECURE_AES_KEY_ZEROED_STATUS_OFFSET),
Mask,
Mask,
XSECURE_AES_TIMEOUT_MAX);
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_AES_KEY_CLEAR_OFFSET,
KeyClearVal);
if (Status != (u32)XST_SUCCESS) {
Status = XSECURE_AES_KEY_CLEAR_ERROR;
}
END:
return Status;
}
/******************************************************************************/
/**
*
* @brief
* This is a helper function to enable/disable byte swapping feature of PMC DMA
*
* @param InstancePtr Pointer to the XPmcDma instance.
* @param Channel Channel Type - XPMCDMA_SRC_CHANNEL
* XPMCDMA_DST_CHANNEL
* @param EndianType 1 : Enable Byte Swapping
* 0 : Disable Byte Swapping
*
* @return None
*
******************************************************************************/
static void XSecure_AesPmcDmaCfgEndianness(XPmcDma *InstancePtr,
XPmcDma_Channel Channel,
u8 EndianType)
{
XPmcDma_Configure ConfigValues = {0};
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
XPmcDma_GetConfig(InstancePtr, Channel, &ConfigValues);
ConfigValues.EndianType = EndianType;
XPmcDma_SetConfig(InstancePtr, Channel, &ConfigValues);
}
/*****************************************************************************/
/**
* @brief This function performs known answer test(KAT) on AES engine.
*
* @param InstancePtr Pointer to the XSecure_Aes instance
*
* @return
* - XST_SUCCESS when KAT Pass
* - Error code on failure
*
*****************************************************************************/
u32 XSecure_AesDecryptKat(XSecure_Aes *AesInstance)
{
u32 Status = (u32)XST_FAILURE;
u32 Index;
u32 Key[8U] = {<KEY>, <KEY>, <KEY> , 0x1A2D14EDU,
0x4D3B0A53U, 0xF3C6E1AEU, 0xAFC2447AU, 0x7B534D99U};
u32 Iv[4U] = {0xCCF8E3B9U, 0x11F11746U, 0xD58C03AFU, 0x00000000U};
u32 Message[4U] = {0xF9ECC5AEU, 0x92B9B870U, 0x31299331U, 0xC4182756U};
u32 GcmTag[4U] = {0xC3CFB3E5U, 0x49D4FBCAU, 0xD90B2BFCU, 0xC87DBE9BU};
u32 Output[4U] = {0x9008CFD4U, 0x3882AA74U, 0xD635531U, 0x6C1C1F47U};
u32 DstVal[4U];
/* Write AES key */
Status = XSecure_AesWriteKey(AesInstance, XSECURE_AES_USER_KEY_0,
XSECURE_AES_KEY_SIZE_256, (UINTPTR)Key);
if (Status != (u32)XST_SUCCESS) {
Status = XSECURE_AES_KAT_WRITE_KEY_FAILED_ERROR;
goto END;
}
Status = XSecure_AesDecryptInit(AesInstance, XSECURE_AES_USER_KEY_0,
XSECURE_AES_KEY_SIZE_256, (UINTPTR)Iv);
if (Status != (u32)XST_SUCCESS) {
Status = XSECURE_AES_KAT_DECRYPT_INIT_FAILED_ERROR;
goto END;
}
Status = XSecure_AesDecryptData(AesInstance, (UINTPTR)Message,
(UINTPTR)DstVal, XSECURE_SECURE_GCM_TAG_SIZE, (UINTPTR)GcmTag);
if (Status != (u32)XST_SUCCESS) {
Status = XSECURE_AES_KAT_GCM_TAG_MISMATCH_ERROR;
goto END;
}
/* Initialized to error */
Status = XSECURE_AES_KAT_DATA_MISMATCH_ERROR;
for (Index = 0U; Index < XSECURE_AES_BUFFER_SIZE; Index++) {
if (DstVal[Index] != Output[Index]) {
/* Comparison failure of decrypted data */
goto END;
}
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
* @brief This function performs KAT on AES core with DPACM enabled
*
* @param AesInstance InstancePtr Pointer to the XSecure_Aes instance
*
* @param KeyPtr Key Pointer
*
* @param DataPtr Data Pointer
*
* @param OutputPtr Output where the decrypted data to be stored
*
* @return
* - Returns the error codes
* - Returns XST_SUCCESS on success
*
*****************************************************************************/
static u32 XSecure_AesDpaCmDecryptKat(XSecure_Aes *AesInstance, u32 *KeyPtr, u32 *DataPtr, u32 *OutputPtr)
{
u32 Status = (u32)XST_FAILURE;
u32 Index;
/* Configure AES for Encryption */
XSecure_WriteReg(AesInstance->BaseAddress,
XSECURE_AES_MODE_OFFSET, XSECURE_AES_MODE_ENC);
/* Configure AES in split mode */
XSecure_WriteReg(AesInstance->BaseAddress, XSECURE_AES_SPLIT_CFG_OFFSET,
(XSECURE_AES_SPLIT_CFG_KEY_SPLIT |
XSECURE_AES_SPLIT_CFG_DATA_SPLIT));
/* Write Key mask value */
for (Index = 0U; Index < XSECURE_AES_KEY_SIZE_256BIT_WORDS; Index++) {
XSecure_WriteReg(AesInstance->BaseAddress,
XSECURE_AES_KEY_MASK_INDEX + (u8)(Index * (u8)XSECURE_WORD_SIZE),
0x0U);
}
/* Write AES key */
Status = XSecure_AesWriteKey(AesInstance, XSECURE_AES_USER_KEY_0,
XSECURE_AES_KEY_SIZE_256, (UINTPTR)KeyPtr);
if (Status != XST_SUCCESS) {
Status = XSECURE_AESDPACM_KAT_WRITE_KEY_FAILED_ERROR;
goto END;
}
Status = XSecure_AesKeyLoad(AesInstance, XSECURE_AES_USER_KEY_0,
XSECURE_AES_KEY_SIZE_256);
if (Status != (u32)XST_SUCCESS) {
Status = XSECURE_AESDPACM_KAT_KEYLOAD_FAILED_ERROR;
goto END;
}
Status = XSecure_SssAes(&AesInstance->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_DMA0);
if(Status != (u32)XST_SUCCESS) {
Status = XSECURE_AESDPACM_SSS_CFG_FAILED_ERROR;
goto END;
}
/* Start the message. */
XSecure_WriteReg(AesInstance->BaseAddress, XSECURE_AES_START_MSG_OFFSET,
XSECURE_AES_START_MSG_VAL_MASK);
XSecure_WriteReg(AesInstance->BaseAddress, XSECURE_AES_DATA_SWAP_OFFSET,
XSECURE_AES_DATA_SWAP_VAL_MASK);
/* Enable PMC DMA Src channel for byte swapping.*/
XSecure_AesPmcDmaCfgEndianness(AesInstance->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_AES_DATA_SWAP_VAL_MASK);
/* Enable PMC DMA Dst channel for byte swapping.*/
XSecure_AesPmcDmaCfgEndianness(AesInstance->PmcDmaPtr,
XPMCDMA_DST_CHANNEL, XSECURE_AES_DATA_SWAP_VAL_MASK);
/* Configure the PMC DMA Tx/Rx for the incoming Block. */
XPmcDma_Transfer(AesInstance->PmcDmaPtr, XPMCDMA_DST_CHANNEL,
(UINTPTR)OutputPtr, XSECURE_AES_DMA_SIZE, XSECURE_AES_DMA_LAST_WORD_DISABLE);
XPmcDma_Transfer(AesInstance->PmcDmaPtr, XPMCDMA_SRC_CHANNEL,
(UINTPTR)DataPtr, XSECURE_AES_DMA_SIZE, XSECURE_AES_DMA_LAST_WORD_ENABLE);
XPmcDma_WaitForDone(AesInstance->PmcDmaPtr, XPMCDMA_DST_CHANNEL);
Status = XSecure_AesWaitForDone(AesInstance);
if (Status != (u32)XST_SUCCESS) {
Status = XSECURE_AESDPACM_KAT_FAILED_ERROR;
goto END;
}
XSecure_AesPmcDmaCfgEndianness(AesInstance->PmcDmaPtr,
XPMCDMA_SRC_CHANNEL, XSECURE_AES_DATA_SWAP_VAL_DISABLE);
/* Disable PMC DMA Dst channel for byte swapping. */
XSecure_AesPmcDmaCfgEndianness(AesInstance->PmcDmaPtr,
XPMCDMA_DST_CHANNEL, XSECURE_AES_DATA_SWAP_VAL_DISABLE);
XSecure_WriteReg(AesInstance->BaseAddress, XSECURE_AES_DATA_SWAP_OFFSET,
XSECURE_AES_DATA_SWAP_VAL_DISABLE);
END:
XPmcDma_IntrClear(AesInstance->PmcDmaPtr, XPMCDMA_DST_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
/* Acknowledge the transfer has completed */
XPmcDma_IntrClear(AesInstance->PmcDmaPtr, XPMCDMA_SRC_CHANNEL,
XPMCDMA_IXR_DONE_MASK);
/* Configure AES in split mode */
XSecure_WriteReg(AesInstance->BaseAddress, XSECURE_AES_SPLIT_CFG_OFFSET,
XSECURE_AES_SPLIT_CFG_DATA_KEY_DISABLE);
/* AES reset */
XSecure_SetReset(AesInstance->BaseAddress, XSECURE_AES_SOFT_RST_OFFSET);
return Status;
}
/*****************************************************************************/
/**
* @brief This function performs known answer test(KAT) on AES engine
* to confirm DPA counter measures is working fine.
*
* @param AesInstance Pointer to the XSecure_Aes instance
*
* @return
* - XST_SUCCESS when KAT Pass
* - Error code on failure
*
*****************************************************************************/
u32 XSecure_AesDecryptCmKat(XSecure_Aes *AesInstance)
{
u32 Status = (u32)XST_FAILURE;
u32 Ct0[4U];
u32 MiC0[4U];
u32 Ct1[4U];
u32 MiC1[4U];
u32 Output0[16U];
u32 Output1[16U];
u32 Key0[8U];
u32 Data0[16U];
u32 Key1[8U];
u32 Data1[16U];
u32 *RM0 = &Output0[0U];
u32 *R0 = &Output0[4U];
u32 *Mm0 = &Output0[8U];
u32 *M0 = &Output0[12U];
u32 *RM1 = &Output1[0U];
u32 *R1 = &Output1[4U];
u32 *Mm1 = &Output1[8U];
u32 *M1 = &Output1[12U];
Key0[0] = Xil_Htonl(<KEY>);
Key0[1] = Xil_Htonl(<KEY>);
Key0[2] = Xil_Htonl(<KEY>);
Key0[3] = Xil_Htonl(0xE463765FU);
Key0[4] = Xil_Htonl(<KEY>);
Key0[5] = Xil_Htonl(0x09A4551BU);
Key0[6] = Xil_Htonl(<KEY>);
Key0[7] = Xil_Htonl(0xEDA087B6U);
Data0[0] = 0U;
Data0[1] = 0U;
Data0[2] = 0U;
Data0[3] = 0U;
Data0[4] = Xil_Htonl(0xCF37C286U);
Data0[5] = Xil_Htonl(0xC18AD4EAU);
Data0[6] = Xil_Htonl(0x3D0BA6A0U);
Data0[7] = 0U;
Data0[8] = 0U;
Data0[9] = 0U;
Data0[10] = 0U;
Data0[11] = 0U;
Data0[12] = Xil_Htonl(0x2D328124U);
Data0[13] = Xil_Htonl(0xA8D58D56U);
Data0[14] = Xil_Htonl(0xD0775EEDU);
Data0[15] = Xil_Htonl(0x93DE1A88U);
Key1[0] = Xil_Htonl(0x8A02A33BU);
Key1[1] = Xil_Htonl(0xDF87E784U);
Key1[2] = Xil_Htonl(0x<KEY>);
Key1[3] = Xil_Htonl(0xC8727E70U);
Key1[4] = Xil_Htonl(0x4F4FD08CU);
Key1[5] = Xil_Htonl(0<KEY>);
Key1[6] = Xil_Htonl(0<KEY>);
Key1[7] = Xil_Htonl(0xD3CEDEE9U);
Data1[0] = 0U;
Data1[1] = 0U;
Data1[2] = 0U;
Data1[3] = 0U;
Data1[4] = Xil_Htonl(0x599F5896U);
Data1[5] = Xil_Htonl(0x851C968EU);
Data1[6] = Xil_Htonl(0xD808323BU);
Data1[7] = 0U;
Data1[8] = 0U;
Data1[9] = 0U;
Data1[10] = 0U;
Data1[11] = 0U;
Data1[12] = Xil_Htonl(0x4ADE8B32U);
Data1[13] = Xil_Htonl(0xD56723FBU);
Data1[14] = Xil_Htonl(0x8F65CE40U);
Data1[15] = Xil_Htonl(0x825E27C9U);
/*
* In DPA counter measure KAT modify CT and
* MiC values with expected output
*/
Ct0[0] = Xil_Htonl(0x3B0A0267U);
Ct0[1] = Xil_Htonl(0xF6ECDE3AU);
Ct0[2] = Xil_Htonl(0x78B30903U);
Ct0[3] = Xil_Htonl(0xEBD4CA6EU);
Ct1[0] = Xil_Htonl(0xCB913379U);
Ct1[1] = Xil_Htonl(0x6B907565U);
Ct1[2] = Xil_Htonl(0x7840421AU);
Ct1[3] = Xil_Htonl(0x46022B63U);
MiC0[0] = Xil_Htonl(0x1FD20064U);
MiC0[1] = Xil_Htonl(0x09FC6363U);
MiC0[2] = Xil_Htonl(0x79F3D406U);
MiC0[3] = Xil_Htonl(0x7ECA0988U);
MiC1[0] = Xil_Htonl(0xA79E453CU);
MiC1[1] = Xil_Htonl(0x6FAD8A5AU);
MiC1[2] = Xil_Htonl(0x4C2A8E87U);
MiC1[3] = Xil_Htonl(0x821C7F88U);
/* Test 1 */
Status = XSecure_AesDpaCmDecryptKat(AesInstance, Key0, Data0, Output0);
if (Status != XST_SUCCESS) {
goto END;
}
/* Initialize AES driver */
Status = XSecure_AesInitialize(AesInstance, AesInstance->PmcDmaPtr);
if (Status != XST_SUCCESS) {
goto END;
}
Status = XSecure_AesDpaCmDecryptKat(AesInstance, Key1, Data1, Output1);
if (Status != XST_SUCCESS) {
goto END;
}
if (((*(RM0) == 0U) && (*(RM0 + 1U) == 0U) && (*(RM0 + 2U) == 0U) &&
(*(RM0 + 3U) == 0U)) ||
((RM0[0U] == RM1[0U]) && (RM0[1U] == RM1[1U]) &&
(RM0[2U] == RM1[2U]) && (RM0[3U] == RM1[3U])) ||
((RM0[0U] == Mm0[0U]) && (RM0[1U] == Mm0[1U]) &&
(RM0[2U] == Mm0[2U]) && (RM0[3U] == Mm0[3U])) ||
((RM0[0U] == Mm1[0U]) && (RM0[1U] == Mm1[1U]) &&
(RM0[2U] == Mm1[2U]) && (RM0[3U] == Mm1[3U]))) {
Status = XSECURE_AESDPACM_KAT_CHECK1_FAILED_ERROR;
goto END;
}
if (((*(RM1) == 0U) && (*(RM1 + 1U) == 0U) && (*(RM1 + 2U) == 0U) &&
(*(RM1 + 3U) == 0U)) ||
((RM1[0U] == RM0[0U]) && (RM1[1U] == RM0[1U]) &&
(RM1[2U] == RM0[2U]) && (RM1[3U] == RM0[3U])) ||
((RM1[0U] == Mm0[0U]) && (RM1[1U] == Mm0[1U]) &&
(RM1[2U] == Mm0[2U]) && (RM1[3U] == Mm0[3U])) ||
((RM1[0U] == Mm1[0U]) && (RM1[1U] == Mm1[1]) &&
(RM1[2U] == Mm1[2U]) && (RM1[3U] == Mm1[3U]))) {
Status = XSECURE_AESDPACM_KAT_CHECK2_FAILED_ERROR;
goto END;
}
if (((*(Mm0) == 0U) && (*(Mm0 + 1U) == 0U) && (*(Mm0 + 2U) == 0U) &&
(*(Mm0 + 3U) == 0U)) ||
((Mm0[0U] == RM0[0U]) && (Mm0[1U] == RM0[1U]) &&
(Mm0[2U] == RM0[2U]) && (Mm0[3U] == RM0[3U])) ||
((Mm0[0U] == RM1[0U]) && (Mm0[1U] == RM1[1U]) &&
(Mm0[2U] == RM1[2U]) && (Mm0[3U] == RM1[3U])) ||
((Mm0[0U] == Mm1[0U]) && (Mm0[1U] == Mm1[1U]) &&
(Mm0[2U] == Mm1[2U]) && (Mm0[3U] == Mm1[3U]))) {
Status = XSECURE_AESDPACM_KAT_CHECK3_FAILED_ERROR;
goto END;
}
if (((*(Mm1) == 0U) && (*(Mm1 + 1U) == 0U) && (*(Mm1 + 2U) == 0U) &&
(*(Mm1 + 3U) == 0U)) ||
((Mm1[0U] == RM0[0U]) && (Mm1[1U] == RM0[1U]) &&
(Mm1[2U] == RM0[2U]) && (Mm1[3U] == RM0[3U])) ||
((Mm1[0U] == RM1[0U]) && (Mm1[1U] == RM1[1U]) &&
(Mm1[2U] == RM1[2U]) && (Mm1[3U] == RM1[3U])) ||
((Mm1[0U] == Mm0[0U]) && (Mm1[1U] == Mm0[1U]) &&
(Mm1[2U] == Mm0[2U]) && (Mm1[3U] == Mm0[3U]))) {
Status = XSECURE_AESDPACM_KAT_CHECK4_FAILED_ERROR;
goto END;
}
if ((((R0[0U] ^ RM0[0U]) != Ct0[0U]) || ((R0[1U] ^ RM0[1U]) != Ct0[1U]) ||
((R0[2U] ^ RM0[2U]) != Ct0[2U]) || ((R0[3U] ^ RM0[3U]) != Ct0[3U])) ||
(((M0[0U] ^ Mm0[0U]) != MiC0[0U]) || ((M0[1U] ^ Mm0[1U]) != MiC0[1U]) ||
((M0[2U] ^ Mm0[2U]) != MiC0[2U]) || ((M0[3U] ^ Mm0[3U]) != MiC0[3U])) ||
(((R1[0U] ^ RM1[0U]) != Ct1[0U]) || ((R1[1U] ^ RM1[1U]) != Ct1[1U]) ||
((R1[2U] ^ RM1[2U]) != Ct1[2U]) || ((R1[3U] ^ RM1[3U]) != Ct1[3U])) ||
(((M1[0U] ^ Mm1[0U]) != MiC1[0U]) || ((M1[1U] ^ Mm1[1U]) != MiC1[1U]) ||
((M1[2U] ^ Mm1[2U]) != MiC1[2U]) || ((M1[3U] ^ Mm1[3U]) != MiC1[3U]))) {
Status = XSECURE_AESDPACM_KAT_CHECK5_FAILED_ERROR;
goto END;
}
Status = XST_SUCCESS;
END:
return Status;
}
<file_sep>/python_drivers/alice_encoded_photon_data_collector.py
# -*- coding: utf-8 -*-
"""
Created on Thu Jul 23 12:15:05 2020
@author: tianlab01
"""
import time
import time_sync
import james_utils
import tdc_wrapper
import random
server_ip = "192.168.56.1"
tdc = tdc_wrapper.tdc_wrapper(3,0,tdc_wrapper.MODE_CLIENT,"192.168.56.1")
ts = time_sync.time_sync(james_utils.ALICE_PORT, server_ip, time_sync.CLIENT, tdc)
logfile = "time_sync_stats.csv"
#log file format is num, val sent, val received, error (1 if yes), successfully deccoded (1 if yess)
count = 0
#Encoding scheme values
bin_size = 100000 #in ps
bin_number = 4#can encode values between 0 and 15
period = 2000000 #in ps
res = 0
res += ts.set_bin_size(bin_size)
res += ts.set_bin_number(bin_number)
res += ts.set_period(period)
if(res):
print("Failed to set encoding parameters, aborting..")
elif(ts.relative_time_sync()):
print("Relative time synchronization failed, aborting...")
else:
print("Relative time synchronization success!")
#Set the bin number and bin length
while(1):
try:
rand_val = random.randint(0,bin_number - 1)
file = open(logfile,'a')
if(ts.relative_time_sync()):
print("Relative time sync failed")
continue
ret_val = ts.send_encoded_photon(rand_val)
error = 0
if(ret_val == -1):
error = 1
succ = 0
if(ret_val == rand_val):
print("Photon decode success, sent " + str(rand_val) + ", got " + str(ret_val))
succ = 1
else:
print("Photon decode failed, sent " + str(rand_val) + ", got " + str(ret_val))
new_line = str(count) + ", " + str(rand_val) + ", " + str(ret_val) + ", " + str(error) + ", " + str(succ) + "\n"
file.write(new_line)
file.close()
count += 1
print("Waiting 5 seconds...")
time.sleep(5)
except KeyboardInterrupt:
print("Exiting")
break<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_psm_api.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PSM_API_H_
#define XPM_PSM_API_H_
#include "xil_types.h"
#include "xstatus.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PM_PSM_TO_PLM_EVENT (1U)
#define PSM_API_MIN PM_PSM_TO_PLM_EVENT
#define PSM_API_MAX PM_PSM_TO_PLM_EVENT
#define PSM_API_DIRECT_PWR_DWN (1U)
#define PSM_API_DIRECT_PWR_UP (2U)
#define PSM_API_FPD_HOUSECLEAN (3U)
enum ProcDeviceId {
ACPU_0,
ACPU_1,
RPU0_0,
RPU0_1,
PROC_DEV_MAX,
};
struct PsmToPlmEvent_t {
u32 Version; /* Version of the event structure */
u32 Event[PROC_DEV_MAX];
};
void XPm_PsmModuleInit(void);
XStatus XPm_PwrDwnEvent(const u32 DeviceId);
XStatus XPm_WakeUpEvent(const u32 DeviceId);
XStatus XPm_DirectPwrUp(const u32 DeviceId);
XStatus XPm_DirectPwrDwn(const u32 DeviceId);
#ifdef __cplusplus
}
#endif
#endif /* XPM_PSM_API_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilsecure_v4_2/src/common/xsecure_utils.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_utils.h
* @addtogroup xsecure_common_apis XILSECURE_UTILITIES
* @{
* @cond xsecure_internal
* This file contains common APIs which are used across the library.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 4.0 vns 03/12/19 Initial Release
* 4.1 kal 05/20/19 Updated doxygen tags
* psl 08/05/19 Fixed MISRA-C violation
* 4.2 har 01/06/20 Added macro XSecure_Out32
* kpt 01/07/20 Added Macro XSECURE_WORD_SIZE common for
* both AES and RSA
* har 03/26/20 Removed code for SSS configuration
* </pre>
* @endcond
******************************************************************************/
#ifndef XSECURE_UTILS_H_
#define XSECURE_UTILS_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "xparameters.h"
#include "xil_types.h"
#include "sleep.h"
#include "xstatus.h"
#include "xil_assert.h"
#include "xil_mem.h"
/************************** Constant Definitions ****************************/
#define XSECURE_RESET_SET (1U) /**< To set the core into reset */
#define XSECURE_RESET_UNSET (0U)
/**< To take the core out of reset */
#define XSECURE_TIMEOUT_MAX (0x1FFFFFU)
#define XSECURE_WORD_SIZE (4U) /**< WORD size in BYTES */
#define XSECURE_WORD_IN_BITS (32U)/**< WORD size in BITS */
/***************************** Type Definitions******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/* Backward compatibility */
#define XSecure_MemCpy Xil_MemCpy
/*****************************************************************************/
/**
* Read from the register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the base address of
* the device.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XSecure_ReadReg(u32 BaseAddress, u16 RegOffset)
*
******************************************************************************/
static inline u32 XSecure_ReadReg(u32 BaseAddress, u16 RegOffset)
{
u32 Status;
Status = Xil_In32(BaseAddress + RegOffset);
return Status;
}
/***************************************************************************/
/**
* Write to the register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the base address of
* the device.
* @param RegisterValue is the value to be written to the register
*
* @return None.
*
* @note C-Style signature:
* void XSecure_WriteReg(u32 BaseAddress, u16 RegOffset,
* u16 RegisterValue)
*
******************************************************************************/
static inline void XSecure_WriteReg(u32 BaseAddress,
u32 RegOffset, u32 RegisterValue)
{
Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue));
}
#define XSecure_In32 Xil_In32
#define XSecure_In64 Xil_In64
#define XSecure_Out32 Xil_Out32
#define XSecure_Out64 Xil_Out64
#define XSecure_SecureOut32 Xil_SecureOut32
/************************** Function Prototypes ******************************/
void XSecure_SetReset(u32 BaseAddress, u32 Offset);
void XSecure_ReleaseReset(u32 BaseAddress, u32 Offset);
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_UTILS_H_ */
/**@}*/
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/lpd_slcr.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _LPD_SLCR_H_
#define _LPD_SLCR_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* LPD_SLCR Base Address
*/
#define LPD_SLCR_BASEADDR ((u32)0XFF410000U)
/**
* Register: LPD_SLCR_WPROT0
*/
#define LPD_SLCR_WPROT0 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000000U) )
#define LPD_SLCR_WPROT0_ACTIVE_SHIFT 0
#define LPD_SLCR_WPROT0_ACTIVE_WIDTH 1
#define LPD_SLCR_WPROT0_ACTIVE_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_CTRL
*/
#define LPD_SLCR_CTRL ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000004U) )
#define LPD_SLCR_CTRL_SLVERR_ENABLE_SHIFT 0
#define LPD_SLCR_CTRL_SLVERR_ENABLE_WIDTH 1
#define LPD_SLCR_CTRL_SLVERR_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ISR
*/
#define LPD_SLCR_ISR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000008U) )
#define LPD_SLCR_ISR_ADDR_DECODE_ERR_SHIFT 0
#define LPD_SLCR_ISR_ADDR_DECODE_ERR_WIDTH 1
#define LPD_SLCR_ISR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_IMR
*/
#define LPD_SLCR_IMR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000000CU) )
#define LPD_SLCR_IMR_ADDR_DECODE_ERR_SHIFT 0
#define LPD_SLCR_IMR_ADDR_DECODE_ERR_WIDTH 1
#define LPD_SLCR_IMR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_IER
*/
#define LPD_SLCR_IER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000010U) )
#define LPD_SLCR_IER_ADDR_DECODE_ERR_SHIFT 0
#define LPD_SLCR_IER_ADDR_DECODE_ERR_WIDTH 1
#define LPD_SLCR_IER_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_IDR
*/
#define LPD_SLCR_IDR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000014U) )
#define LPD_SLCR_IDR_ADDR_DECODE_ERR_SHIFT 0
#define LPD_SLCR_IDR_ADDR_DECODE_ERR_WIDTH 1
#define LPD_SLCR_IDR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ITR
*/
#define LPD_SLCR_ITR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000018U) )
#define LPD_SLCR_ITR_ADDR_DECODE_ERR_SHIFT 0
#define LPD_SLCR_ITR_ADDR_DECODE_ERR_WIDTH 1
#define LPD_SLCR_ITR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ECO
*/
#define LPD_SLCR_ECO ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000001CU) )
#define LPD_SLCR_ECO_FIELD_SHIFT 0
#define LPD_SLCR_ECO_FIELD_WIDTH 32
#define LPD_SLCR_ECO_FIELD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_PERSISTENT0
*/
#define LPD_SLCR_PERSISTENT0 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000020U) )
#define LPD_SLCR_PERSISTENT0_REG_SHIFT 0
#define LPD_SLCR_PERSISTENT0_REG_WIDTH 32
#define LPD_SLCR_PERSISTENT0_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_PERSISTENT1
*/
#define LPD_SLCR_PERSISTENT1 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000024U) )
#define LPD_SLCR_PERSISTENT1_REG_SHIFT 0
#define LPD_SLCR_PERSISTENT1_REG_WIDTH 32
#define LPD_SLCR_PERSISTENT1_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_PERSISTENT2
*/
#define LPD_SLCR_PERSISTENT2 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000028U) )
#define LPD_SLCR_PERSISTENT2_REG_SHIFT 0
#define LPD_SLCR_PERSISTENT2_REG_WIDTH 32
#define LPD_SLCR_PERSISTENT2_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_PERSISTENT3
*/
#define LPD_SLCR_PERSISTENT3 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000002CU) )
#define LPD_SLCR_PERSISTENT3_REG_SHIFT 0
#define LPD_SLCR_PERSISTENT3_REG_WIDTH 32
#define LPD_SLCR_PERSISTENT3_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_PERSISTENT4
*/
#define LPD_SLCR_PERSISTENT4 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000030U) )
#define LPD_SLCR_PERSISTENT4_REG_SHIFT 0
#define LPD_SLCR_PERSISTENT4_REG_WIDTH 32
#define LPD_SLCR_PERSISTENT4_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_PERSISTENT5
*/
#define LPD_SLCR_PERSISTENT5 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000034U) )
#define LPD_SLCR_PERSISTENT5_REG_SHIFT 0
#define LPD_SLCR_PERSISTENT5_REG_WIDTH 32
#define LPD_SLCR_PERSISTENT5_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_PERSISTENT6
*/
#define LPD_SLCR_PERSISTENT6 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000038U) )
#define LPD_SLCR_PERSISTENT6_REG_SHIFT 0
#define LPD_SLCR_PERSISTENT6_REG_WIDTH 32
#define LPD_SLCR_PERSISTENT6_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_PERSISTENT7
*/
#define LPD_SLCR_PERSISTENT7 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000003CU) )
#define LPD_SLCR_PERSISTENT7_REG_SHIFT 0
#define LPD_SLCR_PERSISTENT7_REG_WIDTH 32
#define LPD_SLCR_PERSISTENT7_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_SAFETY_CHK0
*/
#define LPD_SLCR_SAFETY_CHK0 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000040U) )
#define LPD_SLCR_SAFETY_CHK0_CHK_VAL_SHIFT 0
#define LPD_SLCR_SAFETY_CHK0_CHK_VAL_WIDTH 32
#define LPD_SLCR_SAFETY_CHK0_CHK_VAL_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_SAFETY_CHK1
*/
#define LPD_SLCR_SAFETY_CHK1 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000044U) )
#define LPD_SLCR_SAFETY_CHK1_CHK_VAL_SHIFT 0
#define LPD_SLCR_SAFETY_CHK1_CHK_VAL_WIDTH 32
#define LPD_SLCR_SAFETY_CHK1_CHK_VAL_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_SAFETY_CHK2
*/
#define LPD_SLCR_SAFETY_CHK2 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000048U) )
#define LPD_SLCR_SAFETY_CHK2_CHK_VAL_SHIFT 0
#define LPD_SLCR_SAFETY_CHK2_CHK_VAL_WIDTH 32
#define LPD_SLCR_SAFETY_CHK2_CHK_VAL_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_SAFETY_CHK3
*/
#define LPD_SLCR_SAFETY_CHK3 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000004CU) )
#define LPD_SLCR_SAFETY_CHK3_CHK_VAL_SHIFT 0
#define LPD_SLCR_SAFETY_CHK3_CHK_VAL_WIDTH 32
#define LPD_SLCR_SAFETY_CHK3_CHK_VAL_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_CSUPMU_WDT_CLK_SEL
*/
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000050U) )
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_WIDTH 1
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ADMA_CFG
*/
#define LPD_SLCR_ADMA_CFG ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000200CU) )
#define LPD_SLCR_ADMA_CFG_BUS_WIDTH_SHIFT 5
#define LPD_SLCR_ADMA_CFG_BUS_WIDTH_WIDTH 2
#define LPD_SLCR_ADMA_CFG_BUS_WIDTH_MASK ((u32)0X00000060U)
#define LPD_SLCR_ADMA_CFG_NUM_CH_SHIFT 0
#define LPD_SLCR_ADMA_CFG_NUM_CH_WIDTH 5
#define LPD_SLCR_ADMA_CFG_NUM_CH_MASK ((u32)0X0000001FU)
/**
* Register: LPD_SLCR_ADMA_RAM
*/
#define LPD_SLCR_ADMA_RAM ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00002010U) )
#define LPD_SLCR_ADMA_RAM_RAM1_EMAB_SHIFT 12
#define LPD_SLCR_ADMA_RAM_RAM1_EMAB_WIDTH 3
#define LPD_SLCR_ADMA_RAM_RAM1_EMAB_MASK ((u32)0X00007000U)
#define LPD_SLCR_ADMA_RAM_RAM1_EMASA_SHIFT 11
#define LPD_SLCR_ADMA_RAM_RAM1_EMASA_WIDTH 1
#define LPD_SLCR_ADMA_RAM_RAM1_EMASA_MASK ((u32)0X00000800U)
#define LPD_SLCR_ADMA_RAM_RAM1_EMAA_SHIFT 8
#define LPD_SLCR_ADMA_RAM_RAM1_EMAA_WIDTH 3
#define LPD_SLCR_ADMA_RAM_RAM1_EMAA_MASK ((u32)0X00000700U)
#define LPD_SLCR_ADMA_RAM_RAM0_EMAB_SHIFT 4
#define LPD_SLCR_ADMA_RAM_RAM0_EMAB_WIDTH 3
#define LPD_SLCR_ADMA_RAM_RAM0_EMAB_MASK ((u32)0X00000070U)
#define LPD_SLCR_ADMA_RAM_RAM0_EMASA_SHIFT 3
#define LPD_SLCR_ADMA_RAM_RAM0_EMASA_WIDTH 1
#define LPD_SLCR_ADMA_RAM_RAM0_EMASA_MASK ((u32)0X00000008U)
#define LPD_SLCR_ADMA_RAM_RAM0_EMAA_SHIFT 0
#define LPD_SLCR_ADMA_RAM_RAM0_EMAA_WIDTH 3
#define LPD_SLCR_ADMA_RAM_RAM0_EMAA_MASK ((u32)0X00000007U)
/**
* Register: LPD_SLCR_ERR_AIBAXI_ISR
*/
#define LPD_SLCR_ERR_AIBAXI_ISR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003000U) )
#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT 28
#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK ((u32)0X10000000U)
#define LPD_SLCR_ERR_AIBAXI_ISR_LPD_DDR_SHIFT 27
#define LPD_SLCR_ERR_AIBAXI_ISR_LPD_DDR_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_LPD_DDR_MASK ((u32)0X08000000U)
#define LPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT 26
#define LPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK ((u32)0X04000000U)
#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT 24
#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK ((u32)0X01000000U)
#define LPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT 23
#define LPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK ((u32)0X00800000U)
#define LPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT 22
#define LPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK ((u32)0X00400000U)
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT 19
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK ((u32)0X00080000U)
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT 18
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK ((u32)0X00040000U)
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT 17
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK ((u32)0X00020000U)
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT 16
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK ((u32)0X00010000U)
#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT 3
#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK ((u32)0X00000008U)
#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT 2
#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK ((u32)0X00000004U)
#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT 1
#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK ((u32)0X00000002U)
#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT 0
#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_AIBAXI_IMR
*/
#define LPD_SLCR_ERR_AIBAXI_IMR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003008U) )
#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT 28
#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK ((u32)0X10000000U)
#define LPD_SLCR_ERR_AIBAXI_IMR_LPD_DDR_SHIFT 27
#define LPD_SLCR_ERR_AIBAXI_IMR_LPD_DDR_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_LPD_DDR_MASK ((u32)0X08000000U)
#define LPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT 26
#define LPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK ((u32)0X04000000U)
#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT 24
#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK ((u32)0X01000000U)
#define LPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT 23
#define LPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK ((u32)0X00800000U)
#define LPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT 22
#define LPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK ((u32)0X00400000U)
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT 19
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK ((u32)0X00080000U)
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT 18
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK ((u32)0X00040000U)
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT 17
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK ((u32)0X00020000U)
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT 16
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK ((u32)0X00010000U)
#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT 3
#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK ((u32)0X00000008U)
#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT 2
#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK ((u32)0X00000004U)
#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT 1
#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK ((u32)0X00000002U)
#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT 0
#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_AIBAXI_IER
*/
#define LPD_SLCR_ERR_AIBAXI_IER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003010U) )
#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT 28
#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK ((u32)0X10000000U)
#define LPD_SLCR_ERR_AIBAXI_IER_LPD_DDR_SHIFT 27
#define LPD_SLCR_ERR_AIBAXI_IER_LPD_DDR_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_LPD_DDR_MASK ((u32)0X08000000U)
#define LPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT 26
#define LPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK ((u32)0X04000000U)
#define LPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT 24
#define LPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK ((u32)0X01000000U)
#define LPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT 23
#define LPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK ((u32)0X00800000U)
#define LPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT 22
#define LPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK ((u32)0X00400000U)
#define LPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT 19
#define LPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK ((u32)0X00080000U)
#define LPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT 18
#define LPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK ((u32)0X00040000U)
#define LPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT 17
#define LPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK ((u32)0X00020000U)
#define LPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT 16
#define LPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK ((u32)0X00010000U)
#define LPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT 3
#define LPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK ((u32)0X00000008U)
#define LPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT 2
#define LPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK ((u32)0X00000004U)
#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT 1
#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK ((u32)0X00000002U)
#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT 0
#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_AIBAXI_IDR
*/
#define LPD_SLCR_ERR_AIBAXI_IDR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003018U) )
#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT 28
#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK ((u32)0X10000000U)
#define LPD_SLCR_ERR_AIBAXI_IDR_LPD_DDR_SHIFT 27
#define LPD_SLCR_ERR_AIBAXI_IDR_LPD_DDR_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_LPD_DDR_MASK ((u32)0X08000000U)
#define LPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT 26
#define LPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK ((u32)0X04000000U)
#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT 24
#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK ((u32)0X01000000U)
#define LPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT 23
#define LPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK ((u32)0X00800000U)
#define LPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT 22
#define LPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK ((u32)0X00400000U)
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT 19
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK ((u32)0X00080000U)
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT 18
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK ((u32)0X00040000U)
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT 17
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK ((u32)0X00020000U)
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT 16
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK ((u32)0X00010000U)
#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT 3
#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK ((u32)0X00000008U)
#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT 2
#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK ((u32)0X00000004U)
#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT 1
#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK ((u32)0X00000002U)
#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT 0
#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH 1
#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_AIBAPB_ISR
*/
#define LPD_SLCR_ERR_AIBAPB_ISR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003020U) )
#define LPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT 0
#define LPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH 1
#define LPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_AIBAPB_IMR
*/
#define LPD_SLCR_ERR_AIBAPB_IMR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003024U) )
#define LPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT 0
#define LPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH 1
#define LPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_AIBAPB_IER
*/
#define LPD_SLCR_ERR_AIBAPB_IER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003028U) )
#define LPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT 0
#define LPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH 1
#define LPD_SLCR_ERR_AIBAPB_IER_GPU_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_AIBAPB_IDR
*/
#define LPD_SLCR_ERR_AIBAPB_IDR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000302CU) )
#define LPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT 0
#define LPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH 1
#define LPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ISO_AIBAXI_REQ
*/
#define LPD_SLCR_ISO_AIBAXI_REQ ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003030U) )
#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT 28
#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK ((u32)0X10000000U)
#define LPD_SLCR_ISO_AIBAXI_REQ_LPD_DDR_SHIFT 27
#define LPD_SLCR_ISO_AIBAXI_REQ_LPD_DDR_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_LPD_DDR_MASK ((u32)0X08000000U)
#define LPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT 26
#define LPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK ((u32)0X04000000U)
#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT 24
#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK ((u32)0X01000000U)
#define LPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT 23
#define LPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK ((u32)0X00800000U)
#define LPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT 22
#define LPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK ((u32)0X00400000U)
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT 19
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK ((u32)0X00080000U)
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT 18
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK ((u32)0X00040000U)
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT 17
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK ((u32)0X00020000U)
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT 16
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK ((u32)0X00010000U)
#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT 3
#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK ((u32)0X00000008U)
#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT 2
#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK ((u32)0X00000004U)
#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT 1
#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK ((u32)0X00000002U)
#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT 0
#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ISO_AIBAXI_TYPE
*/
#define LPD_SLCR_ISO_AIBAXI_TYPE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003038U) )
#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT 28
#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK ((u32)0X10000000U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_LPD_DDR_SHIFT 27
#define LPD_SLCR_ISO_AIBAXI_TYPE_LPD_DDR_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_LPD_DDR_MASK ((u32)0X08000000U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT 26
#define LPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK ((u32)0X04000000U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT 24
#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK ((u32)0X01000000U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT 23
#define LPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK ((u32)0X00800000U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT 22
#define LPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK ((u32)0X00400000U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT 19
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK ((u32)0X00080000U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT 18
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK ((u32)0X00040000U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT 17
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK ((u32)0X00020000U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT 16
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK ((u32)0X00010000U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT 3
#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK ((u32)0X00000008U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT 2
#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK ((u32)0X00000004U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK ((u32)0X00000002U)
#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT 0
#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ISO_AIBAXI_ACK
*/
#define LPD_SLCR_ISO_AIBAXI_ACK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003040U) )
#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT 28
#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK ((u32)0X10000000U)
#define LPD_SLCR_ISO_AIBAXI_ACK_LPD_DDR_SHIFT 27
#define LPD_SLCR_ISO_AIBAXI_ACK_LPD_DDR_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_LPD_DDR_MASK ((u32)0X08000000U)
#define LPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT 26
#define LPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK ((u32)0X04000000U)
#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT 24
#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK ((u32)0X01000000U)
#define LPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT 23
#define LPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK ((u32)0X00800000U)
#define LPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT 22
#define LPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK ((u32)0X00400000U)
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT 19
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK ((u32)0X00080000U)
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT 18
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK ((u32)0X00040000U)
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT 17
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK ((u32)0X00020000U)
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT 16
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK ((u32)0X00010000U)
#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT 3
#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK ((u32)0X00000008U)
#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT 2
#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK ((u32)0X00000004U)
#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT 1
#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK ((u32)0X00000002U)
#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT 0
#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH 1
#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ISO_AIBAPB_REQ
*/
#define LPD_SLCR_ISO_AIBAPB_REQ ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003048U) )
#define LPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT 0
#define LPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH 1
#define LPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ISO_AIBAPB_TYPE
*/
#define LPD_SLCR_ISO_AIBAPB_TYPE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000304CU) )
#define LPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT 0
#define LPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH 1
#define LPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ISO_AIBAPB_ACK
*/
#define LPD_SLCR_ISO_AIBAPB_ACK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003050U) )
#define LPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT 0
#define LPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH 1
#define LPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_ATB_ISR
*/
#define LPD_SLCR_ERR_ATB_ISR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006000U) )
#define LPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT 1
#define LPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH 1
#define LPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK ((u32)0X00000002U)
#define LPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT 0
#define LPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH 1
#define LPD_SLCR_ERR_ATB_ISR_LPDM_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_ATB_IMR
*/
#define LPD_SLCR_ERR_ATB_IMR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006004U) )
#define LPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT 1
#define LPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH 1
#define LPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK ((u32)0X00000002U)
#define LPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT 0
#define LPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH 1
#define LPD_SLCR_ERR_ATB_IMR_LPDM_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_ATB_IER
*/
#define LPD_SLCR_ERR_ATB_IER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006008U) )
#define LPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT 1
#define LPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH 1
#define LPD_SLCR_ERR_ATB_IER_AFIFS2_MASK ((u32)0X00000002U)
#define LPD_SLCR_ERR_ATB_IER_LPDM_SHIFT 0
#define LPD_SLCR_ERR_ATB_IER_LPDM_WIDTH 1
#define LPD_SLCR_ERR_ATB_IER_LPDM_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ERR_ATB_IDR
*/
#define LPD_SLCR_ERR_ATB_IDR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000600CU) )
#define LPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT 1
#define LPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH 1
#define LPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK ((u32)0X00000002U)
#define LPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT 0
#define LPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH 1
#define LPD_SLCR_ERR_ATB_IDR_LPDM_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ATB_CMD_STORE_EN
*/
#define LPD_SLCR_ATB_CMD_STORE_EN ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006010U) )
#define LPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT 1
#define LPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH 1
#define LPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK ((u32)0X00000002U)
#define LPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT 0
#define LPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH 1
#define LPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ATB_RESP_EN
*/
#define LPD_SLCR_ATB_RESP_EN ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006014U) )
#define LPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT 1
#define LPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH 1
#define LPD_SLCR_ATB_RESP_EN_AFIFS2_MASK ((u32)0X00000002U)
#define LPD_SLCR_ATB_RESP_EN_LPDM_SHIFT 0
#define LPD_SLCR_ATB_RESP_EN_LPDM_WIDTH 1
#define LPD_SLCR_ATB_RESP_EN_LPDM_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ATB_RESP_TYPE
*/
#define LPD_SLCR_ATB_RESP_TYPE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006018U) )
#define LPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT 1
#define LPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH 1
#define LPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK ((u32)0X00000002U)
#define LPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT 0
#define LPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH 1
#define LPD_SLCR_ATB_RESP_TYPE_LPDM_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ATB_ERR_INJECT
*/
#define LPD_SLCR_ATB_ERR_INJECT ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000601CU) )
#define LPD_SLCR_ATB_ERR_INJECT_AFIFS2_SHIFT 1
#define LPD_SLCR_ATB_ERR_INJECT_AFIFS2_WIDTH 1
#define LPD_SLCR_ATB_ERR_INJECT_AFIFS2_MASK ((u32)0X00000002U)
#define LPD_SLCR_ATB_ERR_INJECT_LPDM_SHIFT 0
#define LPD_SLCR_ATB_ERR_INJECT_LPDM_WIDTH 1
#define LPD_SLCR_ATB_ERR_INJECT_LPDM_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_ATB_PRESCALE
*/
#define LPD_SLCR_ATB_PRESCALE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006020U) )
#define LPD_SLCR_ATB_PRESCALE_ENABLE_SHIFT 16
#define LPD_SLCR_ATB_PRESCALE_ENABLE_WIDTH 1
#define LPD_SLCR_ATB_PRESCALE_ENABLE_MASK ((u32)0X00010000U)
#define LPD_SLCR_ATB_PRESCALE_VALUE_SHIFT 0
#define LPD_SLCR_ATB_PRESCALE_VALUE_WIDTH 16
#define LPD_SLCR_ATB_PRESCALE_VALUE_MASK ((u32)0X0000FFFFU)
/**
* Register: LPD_SLCR_MUTEX0
*/
#define LPD_SLCR_MUTEX0 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00007000U) )
#define LPD_SLCR_MUTEX0_ID_SHIFT 0
#define LPD_SLCR_MUTEX0_ID_WIDTH 32
#define LPD_SLCR_MUTEX0_ID_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_MUTEX1
*/
#define LPD_SLCR_MUTEX1 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00007004U) )
#define LPD_SLCR_MUTEX1_ID_SHIFT 0
#define LPD_SLCR_MUTEX1_ID_WIDTH 32
#define LPD_SLCR_MUTEX1_ID_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_MUTEX2
*/
#define LPD_SLCR_MUTEX2 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00007008U) )
#define LPD_SLCR_MUTEX2_ID_SHIFT 0
#define LPD_SLCR_MUTEX2_ID_WIDTH 32
#define LPD_SLCR_MUTEX2_ID_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_MUTEX3
*/
#define LPD_SLCR_MUTEX3 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000700CU) )
#define LPD_SLCR_MUTEX3_ID_SHIFT 0
#define LPD_SLCR_MUTEX3_ID_WIDTH 32
#define LPD_SLCR_MUTEX3_ID_MASK ((u32)0XFFFFFFFFU)
/**
* Register: LPD_SLCR_GICP0_IRQ_STATUS
*/
#define LPD_SLCR_GICP0_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008000U) )
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC31_SHIFT 31
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC31_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC30_SHIFT 30
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC30_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC29_SHIFT 29
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC29_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC28_SHIFT 28
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC28_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC27_SHIFT 27
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC27_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC26_SHIFT 26
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC26_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC25_SHIFT 25
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC25_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC24_SHIFT 24
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC24_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC23_SHIFT 23
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC23_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC22_SHIFT 22
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC22_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC21_SHIFT 21
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC21_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC20_SHIFT 20
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC20_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC19_SHIFT 19
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC19_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC18_SHIFT 18
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC18_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC17_SHIFT 17
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC17_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC16_SHIFT 16
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC16_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC15_SHIFT 15
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC15_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC14_SHIFT 14
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC14_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC13_SHIFT 13
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC13_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC12_SHIFT 12
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC12_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC11_SHIFT 11
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC11_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC10_SHIFT 10
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC10_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC9_SHIFT 9
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC9_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC8_SHIFT 8
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC8_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC7_SHIFT 7
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC7_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC6_SHIFT 6
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC6_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC5_SHIFT 5
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC5_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC4_SHIFT 4
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC4_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC3_SHIFT 3
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC3_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC2_SHIFT 2
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC2_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC1_SHIFT 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC1_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC0_SHIFT 0
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC0_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP0_IRQ_MASK
*/
#define LPD_SLCR_GICP0_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008004U) )
#define LPD_SLCR_GICP0_IRQ_MASK_SRC31_SHIFT 31
#define LPD_SLCR_GICP0_IRQ_MASK_SRC31_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC30_SHIFT 30
#define LPD_SLCR_GICP0_IRQ_MASK_SRC30_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC29_SHIFT 29
#define LPD_SLCR_GICP0_IRQ_MASK_SRC29_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC28_SHIFT 28
#define LPD_SLCR_GICP0_IRQ_MASK_SRC28_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC27_SHIFT 27
#define LPD_SLCR_GICP0_IRQ_MASK_SRC27_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC26_SHIFT 26
#define LPD_SLCR_GICP0_IRQ_MASK_SRC26_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC25_SHIFT 25
#define LPD_SLCR_GICP0_IRQ_MASK_SRC25_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC24_SHIFT 24
#define LPD_SLCR_GICP0_IRQ_MASK_SRC24_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC23_SHIFT 23
#define LPD_SLCR_GICP0_IRQ_MASK_SRC23_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC22_SHIFT 22
#define LPD_SLCR_GICP0_IRQ_MASK_SRC22_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC21_SHIFT 21
#define LPD_SLCR_GICP0_IRQ_MASK_SRC21_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC20_SHIFT 20
#define LPD_SLCR_GICP0_IRQ_MASK_SRC20_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC19_SHIFT 19
#define LPD_SLCR_GICP0_IRQ_MASK_SRC19_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC18_SHIFT 18
#define LPD_SLCR_GICP0_IRQ_MASK_SRC18_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC17_SHIFT 17
#define LPD_SLCR_GICP0_IRQ_MASK_SRC17_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC16_SHIFT 16
#define LPD_SLCR_GICP0_IRQ_MASK_SRC16_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC15_SHIFT 15
#define LPD_SLCR_GICP0_IRQ_MASK_SRC15_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC14_SHIFT 14
#define LPD_SLCR_GICP0_IRQ_MASK_SRC14_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC13_SHIFT 13
#define LPD_SLCR_GICP0_IRQ_MASK_SRC13_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC12_SHIFT 12
#define LPD_SLCR_GICP0_IRQ_MASK_SRC12_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC11_SHIFT 11
#define LPD_SLCR_GICP0_IRQ_MASK_SRC11_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC10_SHIFT 10
#define LPD_SLCR_GICP0_IRQ_MASK_SRC10_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC9_SHIFT 9
#define LPD_SLCR_GICP0_IRQ_MASK_SRC9_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC8_SHIFT 8
#define LPD_SLCR_GICP0_IRQ_MASK_SRC8_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC7_SHIFT 7
#define LPD_SLCR_GICP0_IRQ_MASK_SRC7_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC6_SHIFT 6
#define LPD_SLCR_GICP0_IRQ_MASK_SRC6_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC5_SHIFT 5
#define LPD_SLCR_GICP0_IRQ_MASK_SRC5_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC4_SHIFT 4
#define LPD_SLCR_GICP0_IRQ_MASK_SRC4_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC3_SHIFT 3
#define LPD_SLCR_GICP0_IRQ_MASK_SRC3_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC2_SHIFT 2
#define LPD_SLCR_GICP0_IRQ_MASK_SRC2_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC1_SHIFT 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC1_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP0_IRQ_MASK_SRC0_SHIFT 0
#define LPD_SLCR_GICP0_IRQ_MASK_SRC0_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_MASK_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP0_IRQ_ENABLE
*/
#define LPD_SLCR_GICP0_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008008U) )
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP0_IRQ_DISABLE
*/
#define LPD_SLCR_GICP0_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000800CU) )
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP0_IRQ_TRIGGER
*/
#define LPD_SLCR_GICP0_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008010U) )
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC31_SHIFT 31
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC31_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC30_SHIFT 30
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC30_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC29_SHIFT 29
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC29_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC28_SHIFT 28
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC28_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC27_SHIFT 27
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC27_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC26_SHIFT 26
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC26_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC25_SHIFT 25
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC25_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC24_SHIFT 24
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC24_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC23_SHIFT 23
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC23_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC22_SHIFT 22
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC22_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC21_SHIFT 21
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC21_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC20_SHIFT 20
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC20_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC19_SHIFT 19
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC19_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC18_SHIFT 18
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC18_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC17_SHIFT 17
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC17_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC16_SHIFT 16
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC16_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC15_SHIFT 15
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC15_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC14_SHIFT 14
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC14_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC13_SHIFT 13
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC13_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC12_SHIFT 12
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC12_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC11_SHIFT 11
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC11_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC10_SHIFT 10
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC10_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC9_SHIFT 9
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC9_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC8_SHIFT 8
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC8_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC7_SHIFT 7
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC7_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC6_SHIFT 6
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC6_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC5_SHIFT 5
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC5_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC4_SHIFT 4
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC4_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC3_SHIFT 3
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC3_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC2_SHIFT 2
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC2_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC1_SHIFT 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC1_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC0_SHIFT 0
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC0_WIDTH 1
#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP1_IRQ_STATUS
*/
#define LPD_SLCR_GICP1_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008014U) )
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC31_SHIFT 31
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC31_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC30_SHIFT 30
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC30_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC29_SHIFT 29
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC29_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC28_SHIFT 28
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC28_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC27_SHIFT 27
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC27_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC26_SHIFT 26
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC26_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC25_SHIFT 25
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC25_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC24_SHIFT 24
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC24_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC23_SHIFT 23
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC23_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC22_SHIFT 22
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC22_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC21_SHIFT 21
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC21_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC20_SHIFT 20
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC20_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC19_SHIFT 19
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC19_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC18_SHIFT 18
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC18_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC17_SHIFT 17
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC17_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC16_SHIFT 16
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC16_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC15_SHIFT 15
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC15_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC14_SHIFT 14
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC14_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC13_SHIFT 13
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC13_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC12_SHIFT 12
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC12_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC11_SHIFT 11
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC11_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC10_SHIFT 10
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC10_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC9_SHIFT 9
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC9_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC8_SHIFT 8
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC8_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC7_SHIFT 7
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC7_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC6_SHIFT 6
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC6_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC5_SHIFT 5
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC5_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC4_SHIFT 4
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC4_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC3_SHIFT 3
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC3_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC2_SHIFT 2
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC2_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC1_SHIFT 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC1_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC0_SHIFT 0
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC0_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP1_IRQ_MASK
*/
#define LPD_SLCR_GICP1_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008018U) )
#define LPD_SLCR_GICP1_IRQ_MASK_SRC31_SHIFT 31
#define LPD_SLCR_GICP1_IRQ_MASK_SRC31_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC30_SHIFT 30
#define LPD_SLCR_GICP1_IRQ_MASK_SRC30_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC29_SHIFT 29
#define LPD_SLCR_GICP1_IRQ_MASK_SRC29_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC28_SHIFT 28
#define LPD_SLCR_GICP1_IRQ_MASK_SRC28_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC27_SHIFT 27
#define LPD_SLCR_GICP1_IRQ_MASK_SRC27_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC26_SHIFT 26
#define LPD_SLCR_GICP1_IRQ_MASK_SRC26_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC25_SHIFT 25
#define LPD_SLCR_GICP1_IRQ_MASK_SRC25_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC24_SHIFT 24
#define LPD_SLCR_GICP1_IRQ_MASK_SRC24_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC23_SHIFT 23
#define LPD_SLCR_GICP1_IRQ_MASK_SRC23_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC22_SHIFT 22
#define LPD_SLCR_GICP1_IRQ_MASK_SRC22_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC21_SHIFT 21
#define LPD_SLCR_GICP1_IRQ_MASK_SRC21_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC20_SHIFT 20
#define LPD_SLCR_GICP1_IRQ_MASK_SRC20_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC19_SHIFT 19
#define LPD_SLCR_GICP1_IRQ_MASK_SRC19_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC18_SHIFT 18
#define LPD_SLCR_GICP1_IRQ_MASK_SRC18_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC17_SHIFT 17
#define LPD_SLCR_GICP1_IRQ_MASK_SRC17_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC16_SHIFT 16
#define LPD_SLCR_GICP1_IRQ_MASK_SRC16_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC15_SHIFT 15
#define LPD_SLCR_GICP1_IRQ_MASK_SRC15_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC14_SHIFT 14
#define LPD_SLCR_GICP1_IRQ_MASK_SRC14_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC13_SHIFT 13
#define LPD_SLCR_GICP1_IRQ_MASK_SRC13_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC12_SHIFT 12
#define LPD_SLCR_GICP1_IRQ_MASK_SRC12_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC11_SHIFT 11
#define LPD_SLCR_GICP1_IRQ_MASK_SRC11_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC10_SHIFT 10
#define LPD_SLCR_GICP1_IRQ_MASK_SRC10_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC9_SHIFT 9
#define LPD_SLCR_GICP1_IRQ_MASK_SRC9_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC8_SHIFT 8
#define LPD_SLCR_GICP1_IRQ_MASK_SRC8_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC7_SHIFT 7
#define LPD_SLCR_GICP1_IRQ_MASK_SRC7_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC6_SHIFT 6
#define LPD_SLCR_GICP1_IRQ_MASK_SRC6_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC5_SHIFT 5
#define LPD_SLCR_GICP1_IRQ_MASK_SRC5_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC4_SHIFT 4
#define LPD_SLCR_GICP1_IRQ_MASK_SRC4_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC3_SHIFT 3
#define LPD_SLCR_GICP1_IRQ_MASK_SRC3_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC2_SHIFT 2
#define LPD_SLCR_GICP1_IRQ_MASK_SRC2_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC1_SHIFT 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC1_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP1_IRQ_MASK_SRC0_SHIFT 0
#define LPD_SLCR_GICP1_IRQ_MASK_SRC0_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_MASK_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP1_IRQ_ENABLE
*/
#define LPD_SLCR_GICP1_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000801CU) )
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP1_IRQ_DISABLE
*/
#define LPD_SLCR_GICP1_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008020U) )
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP1_IRQ_TRIGGER
*/
#define LPD_SLCR_GICP1_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008024U) )
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC31_SHIFT 31
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC31_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC30_SHIFT 30
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC30_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC29_SHIFT 29
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC29_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC28_SHIFT 28
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC28_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC27_SHIFT 27
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC27_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC26_SHIFT 26
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC26_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC25_SHIFT 25
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC25_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC24_SHIFT 24
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC24_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC23_SHIFT 23
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC23_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC22_SHIFT 22
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC22_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC21_SHIFT 21
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC21_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC20_SHIFT 20
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC20_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC19_SHIFT 19
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC19_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC18_SHIFT 18
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC18_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC17_SHIFT 17
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC17_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC16_SHIFT 16
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC16_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC15_SHIFT 15
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC15_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC14_SHIFT 14
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC14_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC13_SHIFT 13
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC13_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC12_SHIFT 12
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC12_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC11_SHIFT 11
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC11_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC10_SHIFT 10
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC10_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC9_SHIFT 9
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC9_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC8_SHIFT 8
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC8_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC7_SHIFT 7
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC7_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC6_SHIFT 6
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC6_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC5_SHIFT 5
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC5_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC4_SHIFT 4
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC4_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC3_SHIFT 3
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC3_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC2_SHIFT 2
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC2_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC1_SHIFT 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC1_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC0_SHIFT 0
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC0_WIDTH 1
#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP2_IRQ_STATUS
*/
#define LPD_SLCR_GICP2_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008028U) )
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC31_SHIFT 31
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC31_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC30_SHIFT 30
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC30_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC29_SHIFT 29
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC29_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC28_SHIFT 28
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC28_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC27_SHIFT 27
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC27_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC26_SHIFT 26
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC26_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC25_SHIFT 25
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC25_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC24_SHIFT 24
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC24_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC23_SHIFT 23
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC23_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC22_SHIFT 22
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC22_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC21_SHIFT 21
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC21_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC20_SHIFT 20
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC20_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC19_SHIFT 19
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC19_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC18_SHIFT 18
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC18_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC17_SHIFT 17
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC17_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC16_SHIFT 16
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC16_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC15_SHIFT 15
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC15_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC14_SHIFT 14
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC14_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC13_SHIFT 13
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC13_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC12_SHIFT 12
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC12_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC11_SHIFT 11
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC11_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC10_SHIFT 10
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC10_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC9_SHIFT 9
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC9_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC8_SHIFT 8
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC8_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC7_SHIFT 7
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC7_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC6_SHIFT 6
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC6_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC5_SHIFT 5
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC5_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC4_SHIFT 4
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC4_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC3_SHIFT 3
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC3_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC2_SHIFT 2
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC2_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC1_SHIFT 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC1_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC0_SHIFT 0
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC0_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP2_IRQ_MASK
*/
#define LPD_SLCR_GICP2_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000802CU) )
#define LPD_SLCR_GICP2_IRQ_MASK_SRC31_SHIFT 31
#define LPD_SLCR_GICP2_IRQ_MASK_SRC31_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC30_SHIFT 30
#define LPD_SLCR_GICP2_IRQ_MASK_SRC30_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC29_SHIFT 29
#define LPD_SLCR_GICP2_IRQ_MASK_SRC29_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC28_SHIFT 28
#define LPD_SLCR_GICP2_IRQ_MASK_SRC28_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC27_SHIFT 27
#define LPD_SLCR_GICP2_IRQ_MASK_SRC27_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC26_SHIFT 26
#define LPD_SLCR_GICP2_IRQ_MASK_SRC26_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC25_SHIFT 25
#define LPD_SLCR_GICP2_IRQ_MASK_SRC25_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC24_SHIFT 24
#define LPD_SLCR_GICP2_IRQ_MASK_SRC24_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC23_SHIFT 23
#define LPD_SLCR_GICP2_IRQ_MASK_SRC23_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC22_SHIFT 22
#define LPD_SLCR_GICP2_IRQ_MASK_SRC22_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC21_SHIFT 21
#define LPD_SLCR_GICP2_IRQ_MASK_SRC21_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC20_SHIFT 20
#define LPD_SLCR_GICP2_IRQ_MASK_SRC20_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC19_SHIFT 19
#define LPD_SLCR_GICP2_IRQ_MASK_SRC19_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC18_SHIFT 18
#define LPD_SLCR_GICP2_IRQ_MASK_SRC18_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC17_SHIFT 17
#define LPD_SLCR_GICP2_IRQ_MASK_SRC17_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC16_SHIFT 16
#define LPD_SLCR_GICP2_IRQ_MASK_SRC16_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC15_SHIFT 15
#define LPD_SLCR_GICP2_IRQ_MASK_SRC15_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC14_SHIFT 14
#define LPD_SLCR_GICP2_IRQ_MASK_SRC14_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC13_SHIFT 13
#define LPD_SLCR_GICP2_IRQ_MASK_SRC13_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC12_SHIFT 12
#define LPD_SLCR_GICP2_IRQ_MASK_SRC12_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC11_SHIFT 11
#define LPD_SLCR_GICP2_IRQ_MASK_SRC11_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC10_SHIFT 10
#define LPD_SLCR_GICP2_IRQ_MASK_SRC10_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC9_SHIFT 9
#define LPD_SLCR_GICP2_IRQ_MASK_SRC9_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC8_SHIFT 8
#define LPD_SLCR_GICP2_IRQ_MASK_SRC8_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC7_SHIFT 7
#define LPD_SLCR_GICP2_IRQ_MASK_SRC7_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC6_SHIFT 6
#define LPD_SLCR_GICP2_IRQ_MASK_SRC6_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC5_SHIFT 5
#define LPD_SLCR_GICP2_IRQ_MASK_SRC5_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC4_SHIFT 4
#define LPD_SLCR_GICP2_IRQ_MASK_SRC4_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC3_SHIFT 3
#define LPD_SLCR_GICP2_IRQ_MASK_SRC3_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC2_SHIFT 2
#define LPD_SLCR_GICP2_IRQ_MASK_SRC2_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC1_SHIFT 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC1_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP2_IRQ_MASK_SRC0_SHIFT 0
#define LPD_SLCR_GICP2_IRQ_MASK_SRC0_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_MASK_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP2_IRQ_ENABLE
*/
#define LPD_SLCR_GICP2_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008030U) )
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP2_IRQ_DISABLE
*/
#define LPD_SLCR_GICP2_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008034U) )
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP2_IRQ_TRIGGER
*/
#define LPD_SLCR_GICP2_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008038U) )
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC31_SHIFT 31
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC31_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC30_SHIFT 30
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC30_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC29_SHIFT 29
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC29_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC28_SHIFT 28
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC28_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC27_SHIFT 27
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC27_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC26_SHIFT 26
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC26_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC25_SHIFT 25
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC25_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC24_SHIFT 24
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC24_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC23_SHIFT 23
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC23_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC22_SHIFT 22
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC22_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC21_SHIFT 21
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC21_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC20_SHIFT 20
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC20_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC19_SHIFT 19
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC19_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC18_SHIFT 18
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC18_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC17_SHIFT 17
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC17_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC16_SHIFT 16
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC16_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC15_SHIFT 15
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC15_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC14_SHIFT 14
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC14_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC13_SHIFT 13
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC13_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC12_SHIFT 12
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC12_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC11_SHIFT 11
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC11_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC10_SHIFT 10
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC10_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC9_SHIFT 9
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC9_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC8_SHIFT 8
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC8_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC7_SHIFT 7
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC7_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC6_SHIFT 6
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC6_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC5_SHIFT 5
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC5_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC4_SHIFT 4
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC4_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC3_SHIFT 3
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC3_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC2_SHIFT 2
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC2_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC1_SHIFT 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC1_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC0_SHIFT 0
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC0_WIDTH 1
#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP3_IRQ_STATUS
*/
#define LPD_SLCR_GICP3_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000803CU) )
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC31_SHIFT 31
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC31_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC30_SHIFT 30
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC30_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC29_SHIFT 29
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC29_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC28_SHIFT 28
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC28_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC27_SHIFT 27
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC27_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC26_SHIFT 26
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC26_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC25_SHIFT 25
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC25_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC24_SHIFT 24
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC24_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC23_SHIFT 23
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC23_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC22_SHIFT 22
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC22_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC21_SHIFT 21
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC21_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC20_SHIFT 20
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC20_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC19_SHIFT 19
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC19_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC18_SHIFT 18
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC18_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC17_SHIFT 17
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC17_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC16_SHIFT 16
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC16_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC15_SHIFT 15
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC15_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC14_SHIFT 14
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC14_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC13_SHIFT 13
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC13_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC12_SHIFT 12
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC12_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC11_SHIFT 11
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC11_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC10_SHIFT 10
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC10_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC9_SHIFT 9
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC9_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC8_SHIFT 8
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC8_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC7_SHIFT 7
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC7_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC6_SHIFT 6
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC6_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC5_SHIFT 5
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC5_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC4_SHIFT 4
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC4_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC3_SHIFT 3
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC3_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC2_SHIFT 2
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC2_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC1_SHIFT 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC1_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC0_SHIFT 0
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC0_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP3_IRQ_MASK
*/
#define LPD_SLCR_GICP3_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008040U) )
#define LPD_SLCR_GICP3_IRQ_MASK_SRC31_SHIFT 31
#define LPD_SLCR_GICP3_IRQ_MASK_SRC31_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC30_SHIFT 30
#define LPD_SLCR_GICP3_IRQ_MASK_SRC30_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC29_SHIFT 29
#define LPD_SLCR_GICP3_IRQ_MASK_SRC29_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC28_SHIFT 28
#define LPD_SLCR_GICP3_IRQ_MASK_SRC28_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC27_SHIFT 27
#define LPD_SLCR_GICP3_IRQ_MASK_SRC27_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC26_SHIFT 26
#define LPD_SLCR_GICP3_IRQ_MASK_SRC26_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC25_SHIFT 25
#define LPD_SLCR_GICP3_IRQ_MASK_SRC25_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC24_SHIFT 24
#define LPD_SLCR_GICP3_IRQ_MASK_SRC24_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC23_SHIFT 23
#define LPD_SLCR_GICP3_IRQ_MASK_SRC23_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC22_SHIFT 22
#define LPD_SLCR_GICP3_IRQ_MASK_SRC22_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC21_SHIFT 21
#define LPD_SLCR_GICP3_IRQ_MASK_SRC21_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC20_SHIFT 20
#define LPD_SLCR_GICP3_IRQ_MASK_SRC20_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC19_SHIFT 19
#define LPD_SLCR_GICP3_IRQ_MASK_SRC19_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC18_SHIFT 18
#define LPD_SLCR_GICP3_IRQ_MASK_SRC18_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC17_SHIFT 17
#define LPD_SLCR_GICP3_IRQ_MASK_SRC17_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC16_SHIFT 16
#define LPD_SLCR_GICP3_IRQ_MASK_SRC16_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC15_SHIFT 15
#define LPD_SLCR_GICP3_IRQ_MASK_SRC15_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC14_SHIFT 14
#define LPD_SLCR_GICP3_IRQ_MASK_SRC14_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC13_SHIFT 13
#define LPD_SLCR_GICP3_IRQ_MASK_SRC13_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC12_SHIFT 12
#define LPD_SLCR_GICP3_IRQ_MASK_SRC12_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC11_SHIFT 11
#define LPD_SLCR_GICP3_IRQ_MASK_SRC11_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC10_SHIFT 10
#define LPD_SLCR_GICP3_IRQ_MASK_SRC10_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC9_SHIFT 9
#define LPD_SLCR_GICP3_IRQ_MASK_SRC9_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC8_SHIFT 8
#define LPD_SLCR_GICP3_IRQ_MASK_SRC8_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC7_SHIFT 7
#define LPD_SLCR_GICP3_IRQ_MASK_SRC7_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC6_SHIFT 6
#define LPD_SLCR_GICP3_IRQ_MASK_SRC6_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC5_SHIFT 5
#define LPD_SLCR_GICP3_IRQ_MASK_SRC5_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC4_SHIFT 4
#define LPD_SLCR_GICP3_IRQ_MASK_SRC4_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC3_SHIFT 3
#define LPD_SLCR_GICP3_IRQ_MASK_SRC3_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC2_SHIFT 2
#define LPD_SLCR_GICP3_IRQ_MASK_SRC2_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC1_SHIFT 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC1_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP3_IRQ_MASK_SRC0_SHIFT 0
#define LPD_SLCR_GICP3_IRQ_MASK_SRC0_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_MASK_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP3_IRQ_ENABLE
*/
#define LPD_SLCR_GICP3_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008044U) )
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP3_IRQ_DISABLE
*/
#define LPD_SLCR_GICP3_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008048U) )
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP3_IRQ_TRIGGER
*/
#define LPD_SLCR_GICP3_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000804CU) )
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC31_SHIFT 31
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC31_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC30_SHIFT 30
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC30_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC29_SHIFT 29
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC29_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC28_SHIFT 28
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC28_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC27_SHIFT 27
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC27_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC26_SHIFT 26
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC26_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC25_SHIFT 25
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC25_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC24_SHIFT 24
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC24_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC23_SHIFT 23
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC23_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC22_SHIFT 22
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC22_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC21_SHIFT 21
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC21_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC20_SHIFT 20
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC20_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC19_SHIFT 19
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC19_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC18_SHIFT 18
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC18_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC17_SHIFT 17
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC17_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC16_SHIFT 16
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC16_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC15_SHIFT 15
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC15_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC14_SHIFT 14
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC14_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC13_SHIFT 13
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC13_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC12_SHIFT 12
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC12_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC11_SHIFT 11
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC11_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC10_SHIFT 10
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC10_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC9_SHIFT 9
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC9_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC8_SHIFT 8
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC8_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC7_SHIFT 7
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC7_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC6_SHIFT 6
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC6_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC5_SHIFT 5
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC5_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC4_SHIFT 4
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC4_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC3_SHIFT 3
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC3_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC2_SHIFT 2
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC2_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC1_SHIFT 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC1_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC0_SHIFT 0
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC0_WIDTH 1
#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP4_IRQ_STATUS
*/
#define LPD_SLCR_GICP4_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008050U) )
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC31_SHIFT 31
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC31_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC30_SHIFT 30
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC30_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC29_SHIFT 29
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC29_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC28_SHIFT 28
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC28_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC27_SHIFT 27
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC27_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC26_SHIFT 26
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC26_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC25_SHIFT 25
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC25_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC24_SHIFT 24
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC24_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC23_SHIFT 23
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC23_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC22_SHIFT 22
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC22_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC21_SHIFT 21
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC21_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC20_SHIFT 20
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC20_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC19_SHIFT 19
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC19_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC18_SHIFT 18
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC18_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC17_SHIFT 17
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC17_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC16_SHIFT 16
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC16_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC15_SHIFT 15
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC15_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC14_SHIFT 14
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC14_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC13_SHIFT 13
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC13_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC12_SHIFT 12
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC12_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC11_SHIFT 11
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC11_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC10_SHIFT 10
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC10_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC9_SHIFT 9
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC9_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC8_SHIFT 8
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC8_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC7_SHIFT 7
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC7_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC6_SHIFT 6
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC6_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC5_SHIFT 5
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC5_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC4_SHIFT 4
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC4_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC3_SHIFT 3
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC3_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC2_SHIFT 2
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC2_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC1_SHIFT 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC1_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC0_SHIFT 0
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC0_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP4_IRQ_MASK
*/
#define LPD_SLCR_GICP4_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008054U) )
#define LPD_SLCR_GICP4_IRQ_MASK_SRC31_SHIFT 31
#define LPD_SLCR_GICP4_IRQ_MASK_SRC31_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC30_SHIFT 30
#define LPD_SLCR_GICP4_IRQ_MASK_SRC30_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC29_SHIFT 29
#define LPD_SLCR_GICP4_IRQ_MASK_SRC29_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC28_SHIFT 28
#define LPD_SLCR_GICP4_IRQ_MASK_SRC28_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC27_SHIFT 27
#define LPD_SLCR_GICP4_IRQ_MASK_SRC27_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC26_SHIFT 26
#define LPD_SLCR_GICP4_IRQ_MASK_SRC26_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC25_SHIFT 25
#define LPD_SLCR_GICP4_IRQ_MASK_SRC25_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC24_SHIFT 24
#define LPD_SLCR_GICP4_IRQ_MASK_SRC24_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC23_SHIFT 23
#define LPD_SLCR_GICP4_IRQ_MASK_SRC23_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC22_SHIFT 22
#define LPD_SLCR_GICP4_IRQ_MASK_SRC22_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC21_SHIFT 21
#define LPD_SLCR_GICP4_IRQ_MASK_SRC21_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC20_SHIFT 20
#define LPD_SLCR_GICP4_IRQ_MASK_SRC20_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC19_SHIFT 19
#define LPD_SLCR_GICP4_IRQ_MASK_SRC19_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC18_SHIFT 18
#define LPD_SLCR_GICP4_IRQ_MASK_SRC18_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC17_SHIFT 17
#define LPD_SLCR_GICP4_IRQ_MASK_SRC17_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC16_SHIFT 16
#define LPD_SLCR_GICP4_IRQ_MASK_SRC16_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC15_SHIFT 15
#define LPD_SLCR_GICP4_IRQ_MASK_SRC15_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC14_SHIFT 14
#define LPD_SLCR_GICP4_IRQ_MASK_SRC14_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC13_SHIFT 13
#define LPD_SLCR_GICP4_IRQ_MASK_SRC13_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC12_SHIFT 12
#define LPD_SLCR_GICP4_IRQ_MASK_SRC12_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC11_SHIFT 11
#define LPD_SLCR_GICP4_IRQ_MASK_SRC11_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC10_SHIFT 10
#define LPD_SLCR_GICP4_IRQ_MASK_SRC10_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC9_SHIFT 9
#define LPD_SLCR_GICP4_IRQ_MASK_SRC9_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC8_SHIFT 8
#define LPD_SLCR_GICP4_IRQ_MASK_SRC8_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC7_SHIFT 7
#define LPD_SLCR_GICP4_IRQ_MASK_SRC7_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC6_SHIFT 6
#define LPD_SLCR_GICP4_IRQ_MASK_SRC6_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC5_SHIFT 5
#define LPD_SLCR_GICP4_IRQ_MASK_SRC5_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC4_SHIFT 4
#define LPD_SLCR_GICP4_IRQ_MASK_SRC4_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC3_SHIFT 3
#define LPD_SLCR_GICP4_IRQ_MASK_SRC3_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC2_SHIFT 2
#define LPD_SLCR_GICP4_IRQ_MASK_SRC2_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC1_SHIFT 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC1_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP4_IRQ_MASK_SRC0_SHIFT 0
#define LPD_SLCR_GICP4_IRQ_MASK_SRC0_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_MASK_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP4_IRQ_ENABLE
*/
#define LPD_SLCR_GICP4_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008058U) )
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP4_IRQ_DISABLE
*/
#define LPD_SLCR_GICP4_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000805CU) )
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP4_IRQ_TRIGGER
*/
#define LPD_SLCR_GICP4_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008060U) )
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC31_SHIFT 31
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC31_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC30_SHIFT 30
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC30_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC29_SHIFT 29
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC29_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC28_SHIFT 28
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC28_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC27_SHIFT 27
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC27_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC26_SHIFT 26
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC26_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC25_SHIFT 25
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC25_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC24_SHIFT 24
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC24_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC23_SHIFT 23
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC23_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC22_SHIFT 22
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC22_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC21_SHIFT 21
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC21_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC20_SHIFT 20
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC20_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC19_SHIFT 19
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC19_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC18_SHIFT 18
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC18_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC17_SHIFT 17
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC17_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC16_SHIFT 16
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC16_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC15_SHIFT 15
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC15_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC14_SHIFT 14
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC14_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC13_SHIFT 13
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC13_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC12_SHIFT 12
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC12_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC11_SHIFT 11
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC11_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC10_SHIFT 10
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC10_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC9_SHIFT 9
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC9_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC8_SHIFT 8
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC8_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC7_SHIFT 7
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC7_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC6_SHIFT 6
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC6_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC5_SHIFT 5
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC5_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC4_SHIFT 4
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC4_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC3_SHIFT 3
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC3_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC2_SHIFT 2
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC2_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC1_SHIFT 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC1_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC0_SHIFT 0
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC0_WIDTH 1
#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP5_IRQ_STATUS
*/
#define LPD_SLCR_GICP5_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008064U) )
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC31_SHIFT 31
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC31_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC30_SHIFT 30
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC30_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC29_SHIFT 29
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC29_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC28_SHIFT 28
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC28_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC27_SHIFT 27
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC27_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC26_SHIFT 26
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC26_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC25_SHIFT 25
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC25_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC24_SHIFT 24
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC24_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC23_SHIFT 23
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC23_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC22_SHIFT 22
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC22_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC21_SHIFT 21
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC21_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC20_SHIFT 20
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC20_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC19_SHIFT 19
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC19_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC18_SHIFT 18
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC18_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC17_SHIFT 17
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC17_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC16_SHIFT 16
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC16_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC15_SHIFT 15
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC15_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC14_SHIFT 14
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC14_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC13_SHIFT 13
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC13_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC12_SHIFT 12
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC12_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC11_SHIFT 11
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC11_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC10_SHIFT 10
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC10_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC9_SHIFT 9
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC9_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC8_SHIFT 8
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC8_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC7_SHIFT 7
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC7_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC6_SHIFT 6
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC6_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC5_SHIFT 5
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC5_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC4_SHIFT 4
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC4_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC3_SHIFT 3
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC3_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC2_SHIFT 2
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC2_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC1_SHIFT 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC1_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC0_SHIFT 0
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC0_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP5_IRQ_MASK
*/
#define LPD_SLCR_GICP5_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008068U) )
#define LPD_SLCR_GICP5_IRQ_MASK_SRC31_SHIFT 31
#define LPD_SLCR_GICP5_IRQ_MASK_SRC31_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC30_SHIFT 30
#define LPD_SLCR_GICP5_IRQ_MASK_SRC30_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC29_SHIFT 29
#define LPD_SLCR_GICP5_IRQ_MASK_SRC29_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC28_SHIFT 28
#define LPD_SLCR_GICP5_IRQ_MASK_SRC28_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC27_SHIFT 27
#define LPD_SLCR_GICP5_IRQ_MASK_SRC27_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC26_SHIFT 26
#define LPD_SLCR_GICP5_IRQ_MASK_SRC26_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC25_SHIFT 25
#define LPD_SLCR_GICP5_IRQ_MASK_SRC25_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC24_SHIFT 24
#define LPD_SLCR_GICP5_IRQ_MASK_SRC24_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC23_SHIFT 23
#define LPD_SLCR_GICP5_IRQ_MASK_SRC23_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC22_SHIFT 22
#define LPD_SLCR_GICP5_IRQ_MASK_SRC22_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC21_SHIFT 21
#define LPD_SLCR_GICP5_IRQ_MASK_SRC21_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC20_SHIFT 20
#define LPD_SLCR_GICP5_IRQ_MASK_SRC20_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC19_SHIFT 19
#define LPD_SLCR_GICP5_IRQ_MASK_SRC19_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC18_SHIFT 18
#define LPD_SLCR_GICP5_IRQ_MASK_SRC18_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC17_SHIFT 17
#define LPD_SLCR_GICP5_IRQ_MASK_SRC17_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC16_SHIFT 16
#define LPD_SLCR_GICP5_IRQ_MASK_SRC16_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC15_SHIFT 15
#define LPD_SLCR_GICP5_IRQ_MASK_SRC15_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC14_SHIFT 14
#define LPD_SLCR_GICP5_IRQ_MASK_SRC14_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC13_SHIFT 13
#define LPD_SLCR_GICP5_IRQ_MASK_SRC13_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC12_SHIFT 12
#define LPD_SLCR_GICP5_IRQ_MASK_SRC12_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC11_SHIFT 11
#define LPD_SLCR_GICP5_IRQ_MASK_SRC11_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC10_SHIFT 10
#define LPD_SLCR_GICP5_IRQ_MASK_SRC10_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC9_SHIFT 9
#define LPD_SLCR_GICP5_IRQ_MASK_SRC9_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC8_SHIFT 8
#define LPD_SLCR_GICP5_IRQ_MASK_SRC8_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC7_SHIFT 7
#define LPD_SLCR_GICP5_IRQ_MASK_SRC7_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC6_SHIFT 6
#define LPD_SLCR_GICP5_IRQ_MASK_SRC6_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC5_SHIFT 5
#define LPD_SLCR_GICP5_IRQ_MASK_SRC5_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC4_SHIFT 4
#define LPD_SLCR_GICP5_IRQ_MASK_SRC4_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC3_SHIFT 3
#define LPD_SLCR_GICP5_IRQ_MASK_SRC3_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC2_SHIFT 2
#define LPD_SLCR_GICP5_IRQ_MASK_SRC2_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC1_SHIFT 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC1_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP5_IRQ_MASK_SRC0_SHIFT 0
#define LPD_SLCR_GICP5_IRQ_MASK_SRC0_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_MASK_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP5_IRQ_ENABLE
*/
#define LPD_SLCR_GICP5_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000806CU) )
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP5_IRQ_DISABLE
*/
#define LPD_SLCR_GICP5_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008070U) )
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP5_IRQ_TRIGGER
*/
#define LPD_SLCR_GICP5_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008074U) )
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC31_SHIFT 31
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC31_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC30_SHIFT 30
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC30_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC29_SHIFT 29
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC29_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC28_SHIFT 28
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC28_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC27_SHIFT 27
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC27_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC26_SHIFT 26
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC26_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC25_SHIFT 25
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC25_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC24_SHIFT 24
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC24_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC23_SHIFT 23
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC23_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC22_SHIFT 22
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC22_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC21_SHIFT 21
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC21_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC20_SHIFT 20
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC20_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC19_SHIFT 19
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC19_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC18_SHIFT 18
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC18_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC17_SHIFT 17
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC17_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC16_SHIFT 16
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC16_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC15_SHIFT 15
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC15_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC14_SHIFT 14
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC14_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC13_SHIFT 13
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC13_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC12_SHIFT 12
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC12_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC11_SHIFT 11
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC11_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC10_SHIFT 10
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC10_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC9_SHIFT 9
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC9_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC8_SHIFT 8
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC8_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC7_SHIFT 7
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC7_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC6_SHIFT 6
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC6_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC5_SHIFT 5
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC5_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC4_SHIFT 4
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC4_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC3_SHIFT 3
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC3_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC2_SHIFT 2
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC2_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC1_SHIFT 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC1_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC0_SHIFT 0
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC0_WIDTH 1
#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP6_IRQ_STATUS
*/
#define LPD_SLCR_GICP6_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008078U) )
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC31_SHIFT 31
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC31_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC30_SHIFT 30
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC30_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC29_SHIFT 29
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC29_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC28_SHIFT 28
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC28_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC27_SHIFT 27
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC27_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC26_SHIFT 26
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC26_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC25_SHIFT 25
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC25_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC24_SHIFT 24
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC24_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC23_SHIFT 23
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC23_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC22_SHIFT 22
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC22_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC21_SHIFT 21
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC21_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC20_SHIFT 20
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC20_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC19_SHIFT 19
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC19_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC18_SHIFT 18
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC18_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC17_SHIFT 17
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC17_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC16_SHIFT 16
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC16_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC15_SHIFT 15
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC15_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC14_SHIFT 14
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC14_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC13_SHIFT 13
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC13_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC12_SHIFT 12
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC12_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC11_SHIFT 11
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC11_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC10_SHIFT 10
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC10_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC9_SHIFT 9
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC9_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC8_SHIFT 8
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC8_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC7_SHIFT 7
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC7_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC6_SHIFT 6
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC6_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC5_SHIFT 5
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC5_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC4_SHIFT 4
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC4_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC3_SHIFT 3
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC3_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC2_SHIFT 2
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC2_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC1_SHIFT 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC1_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC0_SHIFT 0
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC0_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP6_IRQ_MASK
*/
#define LPD_SLCR_GICP6_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000807CU) )
#define LPD_SLCR_GICP6_IRQ_MASK_SRC31_SHIFT 31
#define LPD_SLCR_GICP6_IRQ_MASK_SRC31_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC30_SHIFT 30
#define LPD_SLCR_GICP6_IRQ_MASK_SRC30_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC29_SHIFT 29
#define LPD_SLCR_GICP6_IRQ_MASK_SRC29_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC28_SHIFT 28
#define LPD_SLCR_GICP6_IRQ_MASK_SRC28_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC27_SHIFT 27
#define LPD_SLCR_GICP6_IRQ_MASK_SRC27_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC26_SHIFT 26
#define LPD_SLCR_GICP6_IRQ_MASK_SRC26_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC25_SHIFT 25
#define LPD_SLCR_GICP6_IRQ_MASK_SRC25_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC24_SHIFT 24
#define LPD_SLCR_GICP6_IRQ_MASK_SRC24_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC23_SHIFT 23
#define LPD_SLCR_GICP6_IRQ_MASK_SRC23_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC22_SHIFT 22
#define LPD_SLCR_GICP6_IRQ_MASK_SRC22_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC21_SHIFT 21
#define LPD_SLCR_GICP6_IRQ_MASK_SRC21_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC20_SHIFT 20
#define LPD_SLCR_GICP6_IRQ_MASK_SRC20_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC19_SHIFT 19
#define LPD_SLCR_GICP6_IRQ_MASK_SRC19_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC18_SHIFT 18
#define LPD_SLCR_GICP6_IRQ_MASK_SRC18_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC17_SHIFT 17
#define LPD_SLCR_GICP6_IRQ_MASK_SRC17_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC16_SHIFT 16
#define LPD_SLCR_GICP6_IRQ_MASK_SRC16_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC15_SHIFT 15
#define LPD_SLCR_GICP6_IRQ_MASK_SRC15_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC14_SHIFT 14
#define LPD_SLCR_GICP6_IRQ_MASK_SRC14_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC13_SHIFT 13
#define LPD_SLCR_GICP6_IRQ_MASK_SRC13_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC12_SHIFT 12
#define LPD_SLCR_GICP6_IRQ_MASK_SRC12_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC11_SHIFT 11
#define LPD_SLCR_GICP6_IRQ_MASK_SRC11_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC10_SHIFT 10
#define LPD_SLCR_GICP6_IRQ_MASK_SRC10_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC9_SHIFT 9
#define LPD_SLCR_GICP6_IRQ_MASK_SRC9_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC8_SHIFT 8
#define LPD_SLCR_GICP6_IRQ_MASK_SRC8_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC7_SHIFT 7
#define LPD_SLCR_GICP6_IRQ_MASK_SRC7_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC6_SHIFT 6
#define LPD_SLCR_GICP6_IRQ_MASK_SRC6_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC5_SHIFT 5
#define LPD_SLCR_GICP6_IRQ_MASK_SRC5_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC4_SHIFT 4
#define LPD_SLCR_GICP6_IRQ_MASK_SRC4_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC3_SHIFT 3
#define LPD_SLCR_GICP6_IRQ_MASK_SRC3_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC2_SHIFT 2
#define LPD_SLCR_GICP6_IRQ_MASK_SRC2_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC1_SHIFT 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC1_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP6_IRQ_MASK_SRC0_SHIFT 0
#define LPD_SLCR_GICP6_IRQ_MASK_SRC0_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_MASK_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP6_IRQ_ENABLE
*/
#define LPD_SLCR_GICP6_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008080U) )
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP6_IRQ_DISABLE
*/
#define LPD_SLCR_GICP6_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008084U) )
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP6_IRQ_TRIGGER
*/
#define LPD_SLCR_GICP6_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008088U) )
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC31_SHIFT 31
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC31_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC30_SHIFT 30
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC30_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC29_SHIFT 29
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC29_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC28_SHIFT 28
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC28_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC27_SHIFT 27
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC27_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC26_SHIFT 26
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC26_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC25_SHIFT 25
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC25_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC24_SHIFT 24
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC24_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC23_SHIFT 23
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC23_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC22_SHIFT 22
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC22_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC21_SHIFT 21
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC21_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC20_SHIFT 20
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC20_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC19_SHIFT 19
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC19_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC18_SHIFT 18
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC18_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC17_SHIFT 17
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC17_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC16_SHIFT 16
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC16_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC15_SHIFT 15
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC15_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC14_SHIFT 14
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC14_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC13_SHIFT 13
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC13_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC12_SHIFT 12
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC12_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC11_SHIFT 11
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC11_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC10_SHIFT 10
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC10_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC9_SHIFT 9
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC9_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC8_SHIFT 8
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC8_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC7_SHIFT 7
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC7_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC6_SHIFT 6
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC6_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC5_SHIFT 5
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC5_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC4_SHIFT 4
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC4_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC3_SHIFT 3
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC3_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC2_SHIFT 2
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC2_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC1_SHIFT 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC1_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC0_SHIFT 0
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC0_WIDTH 1
#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP7_IRQ_STATUS
*/
#define LPD_SLCR_GICP7_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000808CU) )
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC31_SHIFT 31
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC31_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC30_SHIFT 30
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC30_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC29_SHIFT 29
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC29_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC28_SHIFT 28
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC28_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC27_SHIFT 27
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC27_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC26_SHIFT 26
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC26_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC25_SHIFT 25
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC25_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC24_SHIFT 24
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC24_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC23_SHIFT 23
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC23_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC22_SHIFT 22
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC22_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC21_SHIFT 21
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC21_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC20_SHIFT 20
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC20_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC19_SHIFT 19
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC19_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC18_SHIFT 18
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC18_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC17_SHIFT 17
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC17_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC16_SHIFT 16
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC16_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC15_SHIFT 15
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC15_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC14_SHIFT 14
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC14_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC13_SHIFT 13
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC13_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC12_SHIFT 12
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC12_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC11_SHIFT 11
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC11_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC10_SHIFT 10
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC10_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC9_SHIFT 9
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC9_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC8_SHIFT 8
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC8_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC7_SHIFT 7
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC7_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC6_SHIFT 6
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC6_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC5_SHIFT 5
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC5_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC4_SHIFT 4
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC4_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC3_SHIFT 3
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC3_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC2_SHIFT 2
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC2_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC1_SHIFT 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC1_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC0_SHIFT 0
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC0_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP7_IRQ_MASK
*/
#define LPD_SLCR_GICP7_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008090U) )
#define LPD_SLCR_GICP7_IRQ_MASK_SRC31_SHIFT 31
#define LPD_SLCR_GICP7_IRQ_MASK_SRC31_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC30_SHIFT 30
#define LPD_SLCR_GICP7_IRQ_MASK_SRC30_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC29_SHIFT 29
#define LPD_SLCR_GICP7_IRQ_MASK_SRC29_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC28_SHIFT 28
#define LPD_SLCR_GICP7_IRQ_MASK_SRC28_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC27_SHIFT 27
#define LPD_SLCR_GICP7_IRQ_MASK_SRC27_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC26_SHIFT 26
#define LPD_SLCR_GICP7_IRQ_MASK_SRC26_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC25_SHIFT 25
#define LPD_SLCR_GICP7_IRQ_MASK_SRC25_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC24_SHIFT 24
#define LPD_SLCR_GICP7_IRQ_MASK_SRC24_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC23_SHIFT 23
#define LPD_SLCR_GICP7_IRQ_MASK_SRC23_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC22_SHIFT 22
#define LPD_SLCR_GICP7_IRQ_MASK_SRC22_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC21_SHIFT 21
#define LPD_SLCR_GICP7_IRQ_MASK_SRC21_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC20_SHIFT 20
#define LPD_SLCR_GICP7_IRQ_MASK_SRC20_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC19_SHIFT 19
#define LPD_SLCR_GICP7_IRQ_MASK_SRC19_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC18_SHIFT 18
#define LPD_SLCR_GICP7_IRQ_MASK_SRC18_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC17_SHIFT 17
#define LPD_SLCR_GICP7_IRQ_MASK_SRC17_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC16_SHIFT 16
#define LPD_SLCR_GICP7_IRQ_MASK_SRC16_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC15_SHIFT 15
#define LPD_SLCR_GICP7_IRQ_MASK_SRC15_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC14_SHIFT 14
#define LPD_SLCR_GICP7_IRQ_MASK_SRC14_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC13_SHIFT 13
#define LPD_SLCR_GICP7_IRQ_MASK_SRC13_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC12_SHIFT 12
#define LPD_SLCR_GICP7_IRQ_MASK_SRC12_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC11_SHIFT 11
#define LPD_SLCR_GICP7_IRQ_MASK_SRC11_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC10_SHIFT 10
#define LPD_SLCR_GICP7_IRQ_MASK_SRC10_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC9_SHIFT 9
#define LPD_SLCR_GICP7_IRQ_MASK_SRC9_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC8_SHIFT 8
#define LPD_SLCR_GICP7_IRQ_MASK_SRC8_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC7_SHIFT 7
#define LPD_SLCR_GICP7_IRQ_MASK_SRC7_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC6_SHIFT 6
#define LPD_SLCR_GICP7_IRQ_MASK_SRC6_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC5_SHIFT 5
#define LPD_SLCR_GICP7_IRQ_MASK_SRC5_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC4_SHIFT 4
#define LPD_SLCR_GICP7_IRQ_MASK_SRC4_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC3_SHIFT 3
#define LPD_SLCR_GICP7_IRQ_MASK_SRC3_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC2_SHIFT 2
#define LPD_SLCR_GICP7_IRQ_MASK_SRC2_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC1_SHIFT 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC1_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP7_IRQ_MASK_SRC0_SHIFT 0
#define LPD_SLCR_GICP7_IRQ_MASK_SRC0_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_MASK_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP7_IRQ_ENABLE
*/
#define LPD_SLCR_GICP7_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008094U) )
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP7_IRQ_DISABLE
*/
#define LPD_SLCR_GICP7_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008098U) )
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC31_SHIFT 31
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC31_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC30_SHIFT 30
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC30_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC29_SHIFT 29
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC29_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC28_SHIFT 28
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC28_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC27_SHIFT 27
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC27_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC26_SHIFT 26
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC26_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC25_SHIFT 25
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC25_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC24_SHIFT 24
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC24_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC23_SHIFT 23
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC23_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC22_SHIFT 22
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC22_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC21_SHIFT 21
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC21_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC20_SHIFT 20
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC20_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC19_SHIFT 19
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC19_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC18_SHIFT 18
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC18_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC17_SHIFT 17
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC17_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC16_SHIFT 16
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC16_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC15_SHIFT 15
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC15_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC14_SHIFT 14
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC14_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC13_SHIFT 13
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC13_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC12_SHIFT 12
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC12_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC11_SHIFT 11
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC11_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC10_SHIFT 10
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC10_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC9_SHIFT 9
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC9_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC8_SHIFT 8
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC8_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP7_IRQ_TRIGGER
*/
#define LPD_SLCR_GICP7_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000809CU) )
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC31_SHIFT 31
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC31_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC30_SHIFT 30
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC30_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC29_SHIFT 29
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC29_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC28_SHIFT 28
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC28_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC27_SHIFT 27
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC27_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC26_SHIFT 26
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC26_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC25_SHIFT 25
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC25_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC24_SHIFT 24
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC24_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC23_SHIFT 23
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC23_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC22_SHIFT 22
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC22_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC21_SHIFT 21
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC21_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC20_SHIFT 20
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC20_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC19_SHIFT 19
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC19_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC18_SHIFT 18
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC18_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC17_SHIFT 17
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC17_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC16_SHIFT 16
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC16_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC15_SHIFT 15
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC15_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC14_SHIFT 14
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC14_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC13_SHIFT 13
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC13_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC12_SHIFT 12
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC12_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC11_SHIFT 11
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC11_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC10_SHIFT 10
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC10_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC9_SHIFT 9
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC9_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC8_SHIFT 8
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC8_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC7_SHIFT 7
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC7_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC6_SHIFT 6
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC6_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC5_SHIFT 5
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC5_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC4_SHIFT 4
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC4_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC3_SHIFT 3
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC3_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC2_SHIFT 2
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC2_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC1_SHIFT 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC1_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC0_SHIFT 0
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC0_WIDTH 1
#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP_PMU_IRQ_STATUS
*/
#define LPD_SLCR_GICP_PMU_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X000080A0U) )
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC7_SHIFT 7
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC7_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC6_SHIFT 6
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC6_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC5_SHIFT 5
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC5_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC4_SHIFT 4
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC4_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC3_SHIFT 3
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC3_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC2_SHIFT 2
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC2_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC1_SHIFT 1
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC1_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC0_SHIFT 0
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC0_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP_PMU_IRQ_MASK
*/
#define LPD_SLCR_GICP_PMU_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X000080A4U) )
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC7_SHIFT 7
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC7_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC6_SHIFT 6
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC6_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC5_SHIFT 5
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC5_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC4_SHIFT 4
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC4_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC3_SHIFT 3
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC3_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC2_SHIFT 2
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC2_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC1_SHIFT 1
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC1_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC0_SHIFT 0
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC0_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP_PMU_IRQ_ENABLE
*/
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X000080A8U) )
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP_PMU_IRQ_DISABLE
*/
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X000080ACU) )
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC7_SHIFT 7
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC7_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC6_SHIFT 6
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC6_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC5_SHIFT 5
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC5_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC4_SHIFT 4
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC4_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC3_SHIFT 3
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC3_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC2_SHIFT 2
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC2_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC1_SHIFT 1
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC1_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC0_SHIFT 0
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC0_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_GICP_PMU_IRQ_TRIGGER
*/
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X000080B0U) )
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC7_SHIFT 7
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC7_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U)
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC6_SHIFT 6
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC6_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U)
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC5_SHIFT 5
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC5_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U)
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC4_SHIFT 4
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC4_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U)
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC3_SHIFT 3
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC3_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U)
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC2_SHIFT 2
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC2_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U)
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC1_SHIFT 1
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC1_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U)
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC0_SHIFT 0
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC0_WIDTH 1
#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_AFI_FS
*/
#define LPD_SLCR_AFI_FS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00009000U) )
#define LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8
#define LPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH 2
#define LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK ((u32)0X00000300U)
/**
* Register: LPD_SLCR_LPD_CCI
*/
#define LPD_SLCR_LPD_CCI ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000A000U) )
#define LPD_SLCR_LPD_CCI_SPARE_SHIFT 28
#define LPD_SLCR_LPD_CCI_SPARE_WIDTH 4
#define LPD_SLCR_LPD_CCI_SPARE_MASK ((u32)0XF0000000U)
#define LPD_SLCR_LPD_CCI_QVNVNETS4_SHIFT 27
#define LPD_SLCR_LPD_CCI_QVNVNETS4_WIDTH 1
#define LPD_SLCR_LPD_CCI_QVNVNETS4_MASK ((u32)0X08000000U)
#define LPD_SLCR_LPD_CCI_QVNVNETS3_SHIFT 26
#define LPD_SLCR_LPD_CCI_QVNVNETS3_WIDTH 1
#define LPD_SLCR_LPD_CCI_QVNVNETS3_MASK ((u32)0X04000000U)
#define LPD_SLCR_LPD_CCI_QVNVNETS2_SHIFT 25
#define LPD_SLCR_LPD_CCI_QVNVNETS2_WIDTH 1
#define LPD_SLCR_LPD_CCI_QVNVNETS2_MASK ((u32)0X02000000U)
#define LPD_SLCR_LPD_CCI_QVNVNETS1_SHIFT 24
#define LPD_SLCR_LPD_CCI_QVNVNETS1_WIDTH 1
#define LPD_SLCR_LPD_CCI_QVNVNETS1_MASK ((u32)0X01000000U)
#define LPD_SLCR_LPD_CCI_QVNVNETS0_SHIFT 23
#define LPD_SLCR_LPD_CCI_QVNVNETS0_WIDTH 1
#define LPD_SLCR_LPD_CCI_QVNVNETS0_MASK ((u32)0X00800000U)
#define LPD_SLCR_LPD_CCI_QOSOVERRIDE_SHIFT 18
#define LPD_SLCR_LPD_CCI_QOSOVERRIDE_WIDTH 5
#define LPD_SLCR_LPD_CCI_QOSOVERRIDE_MASK ((u32)0X007C0000U)
#define LPD_SLCR_LPD_CCI_QVNENABLE_M2_SHIFT 17
#define LPD_SLCR_LPD_CCI_QVNENABLE_M2_WIDTH 1
#define LPD_SLCR_LPD_CCI_QVNENABLE_M2_MASK ((u32)0X00020000U)
#define LPD_SLCR_LPD_CCI_QVNENABLE_M1_SHIFT 16
#define LPD_SLCR_LPD_CCI_QVNENABLE_M1_WIDTH 1
#define LPD_SLCR_LPD_CCI_QVNENABLE_M1_MASK ((u32)0X00010000U)
#define LPD_SLCR_LPD_CCI_STRIPING_GRANULE_SHIFT 13
#define LPD_SLCR_LPD_CCI_STRIPING_GRANULE_WIDTH 3
#define LPD_SLCR_LPD_CCI_STRIPING_GRANULE_MASK ((u32)0X0000E000U)
#define LPD_SLCR_LPD_CCI_ACCHANNELEN4_SHIFT 12
#define LPD_SLCR_LPD_CCI_ACCHANNELEN4_WIDTH 1
#define LPD_SLCR_LPD_CCI_ACCHANNELEN4_MASK ((u32)0X00001000U)
#define LPD_SLCR_LPD_CCI_ACCHANNELEN3_SHIFT 11
#define LPD_SLCR_LPD_CCI_ACCHANNELEN3_WIDTH 1
#define LPD_SLCR_LPD_CCI_ACCHANNELEN3_MASK ((u32)0X00000800U)
#define LPD_SLCR_LPD_CCI_ACCHANNELEN0_SHIFT 10
#define LPD_SLCR_LPD_CCI_ACCHANNELEN0_WIDTH 1
#define LPD_SLCR_LPD_CCI_ACCHANNELEN0_MASK ((u32)0X00000400U)
#define LPD_SLCR_LPD_CCI_ECOREVNUM_SHIFT 6
#define LPD_SLCR_LPD_CCI_ECOREVNUM_WIDTH 4
#define LPD_SLCR_LPD_CCI_ECOREVNUM_MASK ((u32)0X000003C0U)
#define LPD_SLCR_LPD_CCI_ASA2_SHIFT 5
#define LPD_SLCR_LPD_CCI_ASA2_WIDTH 1
#define LPD_SLCR_LPD_CCI_ASA2_MASK ((u32)0X00000020U)
#define LPD_SLCR_LPD_CCI_ASA1_SHIFT 4
#define LPD_SLCR_LPD_CCI_ASA1_WIDTH 1
#define LPD_SLCR_LPD_CCI_ASA1_MASK ((u32)0X00000010U)
#define LPD_SLCR_LPD_CCI_ASA0_SHIFT 3
#define LPD_SLCR_LPD_CCI_ASA0_WIDTH 1
#define LPD_SLCR_LPD_CCI_ASA0_MASK ((u32)0X00000008U)
#define LPD_SLCR_LPD_CCI_OWO2_SHIFT 2
#define LPD_SLCR_LPD_CCI_OWO2_WIDTH 1
#define LPD_SLCR_LPD_CCI_OWO2_MASK ((u32)0X00000004U)
#define LPD_SLCR_LPD_CCI_OWO1_SHIFT 1
#define LPD_SLCR_LPD_CCI_OWO1_WIDTH 1
#define LPD_SLCR_LPD_CCI_OWO1_MASK ((u32)0X00000002U)
#define LPD_SLCR_LPD_CCI_OWO0_SHIFT 0
#define LPD_SLCR_LPD_CCI_OWO0_WIDTH 1
#define LPD_SLCR_LPD_CCI_OWO0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_LPD_CCI_ADDRMAP
*/
#define LPD_SLCR_LPD_CCI_ADDRMAP ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000A004U) )
#define LPD_SLCR_LPD_CCI_ADDRMAP_15_SHIFT 30
#define LPD_SLCR_LPD_CCI_ADDRMAP_15_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_15_MASK ((u32)0XC0000000U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_14_SHIFT 28
#define LPD_SLCR_LPD_CCI_ADDRMAP_14_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_14_MASK ((u32)0X30000000U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_13_SHIFT 26
#define LPD_SLCR_LPD_CCI_ADDRMAP_13_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_13_MASK ((u32)0X0C000000U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_12_SHIFT 24
#define LPD_SLCR_LPD_CCI_ADDRMAP_12_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_12_MASK ((u32)0X03000000U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_11_SHIFT 22
#define LPD_SLCR_LPD_CCI_ADDRMAP_11_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_11_MASK ((u32)0X00C00000U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_10_SHIFT 20
#define LPD_SLCR_LPD_CCI_ADDRMAP_10_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_10_MASK ((u32)0X00300000U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_9_SHIFT 18
#define LPD_SLCR_LPD_CCI_ADDRMAP_9_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_9_MASK ((u32)0X000C0000U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_8_SHIFT 16
#define LPD_SLCR_LPD_CCI_ADDRMAP_8_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_8_MASK ((u32)0X00030000U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_7_SHIFT 14
#define LPD_SLCR_LPD_CCI_ADDRMAP_7_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_7_MASK ((u32)0X0000C000U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_6_SHIFT 12
#define LPD_SLCR_LPD_CCI_ADDRMAP_6_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_6_MASK ((u32)0X00003000U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_5_SHIFT 10
#define LPD_SLCR_LPD_CCI_ADDRMAP_5_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_5_MASK ((u32)0X00000C00U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_4_SHIFT 8
#define LPD_SLCR_LPD_CCI_ADDRMAP_4_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_4_MASK ((u32)0X00000300U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_3_SHIFT 6
#define LPD_SLCR_LPD_CCI_ADDRMAP_3_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_3_MASK ((u32)0X000000C0U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_2_SHIFT 4
#define LPD_SLCR_LPD_CCI_ADDRMAP_2_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_2_MASK ((u32)0X00000030U)
#define LPD_SLCR_LPD_CCI_ADDRMAP_1_SHIFT 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_1_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_1_MASK ((u32)0X0000000CU)
#define LPD_SLCR_LPD_CCI_ADDRMAP_0_SHIFT 0
#define LPD_SLCR_LPD_CCI_ADDRMAP_0_WIDTH 2
#define LPD_SLCR_LPD_CCI_ADDRMAP_0_MASK ((u32)0X00000003U)
/**
* Register: LPD_SLCR_LPD_CCI_QVNPREALLOC
*/
#define LPD_SLCR_LPD_CCI_QVNPREALLOC ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000A008U) )
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM2_SHIFT 20
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM2_WIDTH 4
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM2_MASK ((u32)0X00F00000U)
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM1_SHIFT 16
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM1_WIDTH 4
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM1_MASK ((u32)0X000F0000U)
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM2_SHIFT 8
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM2_WIDTH 4
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM2_MASK ((u32)0X00000F00U)
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM1_SHIFT 4
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM1_WIDTH 4
#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM1_MASK ((u32)0X000000F0U)
/**
* Register: LPD_SLCR_LPD_SMMU
*/
#define LPD_SLCR_LPD_SMMU ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000A020U) )
#define LPD_SLCR_LPD_SMMU_INTEG_SEC_OVERRIDE_SHIFT 7
#define LPD_SLCR_LPD_SMMU_INTEG_SEC_OVERRIDE_WIDTH 1
#define LPD_SLCR_LPD_SMMU_INTEG_SEC_OVERRIDE_MASK ((u32)0X00000080U)
#define LPD_SLCR_LPD_SMMU_CTTW_SHIFT 6
#define LPD_SLCR_LPD_SMMU_CTTW_WIDTH 1
#define LPD_SLCR_LPD_SMMU_CTTW_MASK ((u32)0X00000040U)
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU5_SHIFT 5
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU5_WIDTH 1
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU5_MASK ((u32)0X00000020U)
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU4_SHIFT 4
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU4_WIDTH 1
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU4_MASK ((u32)0X00000010U)
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU3_SHIFT 3
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU3_WIDTH 1
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU3_MASK ((u32)0X00000008U)
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU2_SHIFT 2
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU2_WIDTH 1
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU2_MASK ((u32)0X00000004U)
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU1_SHIFT 1
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU1_WIDTH 1
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU1_MASK ((u32)0X00000002U)
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU0_SHIFT 0
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU0_WIDTH 1
#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU0_MASK ((u32)0X00000001U)
/**
* Register: LPD_SLCR_LPD_APU
*/
#define LPD_SLCR_LPD_APU ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000A040U) )
#define LPD_SLCR_LPD_APU_BRDC_BARRIER_SHIFT 3
#define LPD_SLCR_LPD_APU_BRDC_BARRIER_WIDTH 1
#define LPD_SLCR_LPD_APU_BRDC_BARRIER_MASK ((u32)0X00000008U)
#define LPD_SLCR_LPD_APU_BRDC_CMNT_SHIFT 2
#define LPD_SLCR_LPD_APU_BRDC_CMNT_WIDTH 1
#define LPD_SLCR_LPD_APU_BRDC_CMNT_MASK ((u32)0X00000004U)
#define LPD_SLCR_LPD_APU_BRDC_INNER_SHIFT 1U
#define LPD_SLCR_LPD_APU_BRDC_INNER_WIDTH 1
#define LPD_SLCR_LPD_APU_BRDC_INNER_MASK ((u32)0X00000002U)
#define LPD_SLCR_LPD_APU_BRDC_OUTER_SHIFT 0
#define LPD_SLCR_LPD_APU_BRDC_OUTER_WIDTH 1
#define LPD_SLCR_LPD_APU_BRDC_OUTER_MASK ((u32)0X00000001U)
#ifdef __cplusplus
}
#endif
#endif /* _LPD_SLCR_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_reset.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_reset.h"
#include "xpm_device.h"
#include "xpm_domain_iso.h"
#include "xpm_powerdomain.h"
#include "xpm_regs.h"
#include "xpm_aie.h"
#include "xpm_common.h"
static XStatus Reset_AssertCommon(XPm_ResetNode *Rst, const u32 Action);
static XStatus Reset_AssertCustom(XPm_ResetNode *Rst, const u32 Action);
static u32 Reset_GetStatusCommon(XPm_ResetNode *Rst);
static XStatus SetResetNode(u32 Id, XPm_ResetNode *Rst);
static XPm_ResetNode *RstNodeList[(u32)XPM_NODEIDX_RST_MAX];
static const u32 MaxRstNodes = (u32)XPM_NODEIDX_RST_MAX;
static u32 PmNumResets;
static XPm_ResetOps ResetOps[XPM_RSTOPS_MAX] = {
[XPM_RSTOPS_GENRERIC] = {
.SetState = Reset_AssertCommon,
.GetState = Reset_GetStatusCommon,
},
[XPM_RSTOPS_CUSTOM] = {
.SetState = Reset_AssertCustom,
.GetState = Reset_GetStatusCommon,
},
};
static XStatus SetResetNode(u32 Id, XPm_ResetNode *Rst)
{
XStatus Status = XST_INVALID_PARAM;
u32 NodeIndex = NODEINDEX(Id);
/*
* We assume that the Node ID class, subclass and type has _already_
* been validated before, so only check bounds here against index
*/
if ((NULL != Rst) && ((u32)XPM_NODEIDX_RST_MAX > NodeIndex)) {
RstNodeList[NodeIndex] = Rst;
PmNumResets++;
Status = XST_SUCCESS;
}
return Status;
}
static void XPmReset_Init(XPm_ResetNode *Rst, u32 Id, u32 ControlReg, u8 Shift, u8 Width, u8 ResetType, u8 NumParents, u32* Parents)
{
u32 i = 0;
XPmNode_Init(&Rst->Node, Id, (u8)XPM_RST_STATE_ASSERTED, 0);
Rst->Node.BaseAddress = ControlReg;
Rst->Shift = Shift;
Rst->Width = Width;
Rst->Ops = &ResetOps[ResetType];
for (i=0; i<NumParents; i++) {
Rst->Parents[i] = (u16)(NODEINDEX(Parents[i]));
}
}
XStatus XPmReset_AddNode(u32 Id, u32 ControlReg, u8 Shift, u8 Width, u8 ResetType, u8 NumParents, u32* Parents)
{
XStatus Status = XST_FAILURE;
u32 SubClass = NODESUBCLASS(Id);
XPm_ResetNode *Rst = NULL;
if (NULL != XPmReset_GetById(Id) || NumParents > MAX_RESET_PARENTS) {
Status = XST_INVALID_PARAM;
goto done;
}
switch (SubClass) {
case (u32)XPM_NODETYPE_RESET_PERIPHERAL:
case (u32)XPM_NODETYPE_RESET_POR:
case (u32)XPM_NODETYPE_RESET_DBG:
case (u32)XPM_NODETYPE_RESET_SRST:
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
if (XST_SUCCESS != Status) {
goto done;
}
Rst = XPm_AllocBytes(sizeof(XPm_ResetNode));
if (Rst == NULL) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
XPmReset_Init(Rst, Id, ControlReg, Shift, Width, ResetType, NumParents, Parents);
Status = SetResetNode(Id, Rst);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
XPm_ResetNode* XPmReset_GetById(u32 ResetId)
{
u32 ResetIndex = NODEINDEX(ResetId);
XPm_ResetNode *Rst = NULL;
if ((NODECLASS(ResetId) != (u32)XPM_NODECLASS_RESET) ||
(ResetIndex >= MaxRstNodes)) {
return NULL;
}
Rst = RstNodeList[ResetIndex];
/* Check that Reset Node's ID is same as given ID or not. */
if ((NULL != Rst) && (ResetId != Rst->Node.Id)) {
Rst = NULL;
}
return Rst;
}
static XStatus PsOnlyResetAssert(XPm_ResetNode *Rst)
{
XStatus Status = XST_FAILURE;
u32 i;
const u32 PsDomainIds[] = { PM_POWER_LPD, PM_POWER_FPD };
u32 Mask = BITNMASK(Rst->Shift, Rst->Width);
/*
* Prevent LPD access
*/
XPlmi_ResetLpdInitialized();
/* Block LPD-PL interfaces */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_PL, TRUE_PENDING_REMOVE);
if (Status != XST_SUCCESS) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_PL_TEST, TRUE_PENDING_REMOVE);
if (Status != XST_SUCCESS) {
goto done;
}
/* Block LPD-NoC interfaces */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_SOC, TRUE_VALUE);
if (Status != XST_SUCCESS) {
goto done;
}
/* Block LPD-PMC interfaces */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_LPD, TRUE_VALUE);
if (Status != XST_SUCCESS) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_LPD_DFX, TRUE_VALUE);
if (Status != XST_SUCCESS) {
goto done;
}
/* Block FPD-PL interfaces */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_FPD_PL, TRUE_PENDING_REMOVE);
if (Status != XST_SUCCESS) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_FPD_PL_TEST, TRUE_PENDING_REMOVE);
if (Status != XST_SUCCESS) {
goto done;
}
/* Block FPD-NoC interfaces */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_FPD_SOC, TRUE_VALUE);
if (Status != XST_SUCCESS) {
goto done;
}
/*
* TODO: Use XPm_ForcePowerdown() API here to force LPD and FPD
* power and device nodes to power down, this will handle the
* use count and release of device requirements, gracefully.
*
* At present, Debugging is in progress for the issue where
* JTAG link is lost between XSDB and target device if this API is used.
*
* Therefore, following workaround is needed until debugging is done.
*/
for (i = 0; i < ARRAY_SIZE(PsDomainIds); i++) {
XPm_Power *Power = NULL, *Child = NULL;
Power = XPmPower_GetById(PsDomainIds[i]);
if (NULL == Power) {
Status = XST_FAILURE;
goto done;
}
Child = ((XPm_PowerDomain *)Power)->Children;
while (Child != NULL) {
Child->Node.State = (u8)XPM_POWER_STATE_OFF;
Child = Child->NextPeer;
}
Power->Node.State = (u8)XPM_POWER_STATE_OFF;
}
/* Assert PS System Reset */
XPm_RMW32(Rst->Node.BaseAddress, Mask, Mask);
done:
return Status;
}
static XStatus PsOnlyResetRelease(XPm_ResetNode *Rst)
{
u32 Mask = BITNMASK(Rst->Shift, Rst->Width);
/* Release PS System Reset */
XPm_RMW32(Rst->Node.BaseAddress, Mask, 0);
return XST_SUCCESS;
}
static XStatus PsOnlyResetPulse(XPm_ResetNode *Rst)
{
XStatus Status = XST_FAILURE;
/* Assert PS System Reset */
Status = PsOnlyResetAssert(Rst);
if (XST_SUCCESS != Status) {
goto done;
}
/* Release PS System Reset */
Status = PsOnlyResetRelease(Rst);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
static XStatus ResetPulseLpd(XPm_ResetNode *Rst)
{
XStatus Status = XST_FAILURE;
//u32 Mask = BITNMASK(Rst->Shift, Rst->Width);
/* This parameter is required as per the prototype */
(void)(Rst);
/* TODO: TBD */
Status = XST_SUCCESS;
return Status;
}
static XStatus AieResetAssert(XPm_ResetNode *Rst)
{
XStatus Status = XST_FAILURE;
XPm_Device *AieDev = XPmDevice_GetById(PM_DEV_AIE);
if (NULL == AieDev) {
goto done;
}
u32 Mask = BITNMASK(Rst->Shift, Rst->Width);
/* Unlock the AIE PCSR register to allow register writes */
XPmAieDomain_UnlockPcsr(AieDev->Node.BaseAddress);
/* Set array or shim reset bit in mask register */
XPm_RMW32((AieDev->Node.BaseAddress) + NPI_PCSR_MASK_OFFSET, Mask, Mask);
/* Write to control register to assert reset */
XPm_RMW32(Rst->Node.BaseAddress, Mask, Mask);
/* Re-lock the AIE PCSR registers for protection */
XPmAieDomain_LockPcsr(AieDev->Node.BaseAddress);
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus AieResetRelease(XPm_ResetNode *Rst)
{
XStatus Status = XST_FAILURE;
XPm_Device *AieDev = XPmDevice_GetById(PM_DEV_AIE);
if (NULL == AieDev) {
goto done;
}
u32 Mask = BITNMASK(Rst->Shift, Rst->Width);
/* Unlock the AIE PCSR register to allow register writes */
XPmAieDomain_UnlockPcsr(AieDev->Node.BaseAddress);
/* Set array or shim reset bit in mask register */
XPm_RMW32((AieDev->Node.BaseAddress) + NPI_PCSR_MASK_OFFSET, Mask, Mask);
/* Write to control register to release reset */
XPm_RMW32(Rst->Node.BaseAddress, Mask, 0U);
/* Re-lock the AIE PCSR registers for protection */
XPmAieDomain_LockPcsr(AieDev->Node.BaseAddress);
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus AieResetPulse(XPm_ResetNode *Rst)
{
XStatus Status = XST_FAILURE;
/* Assert AIE reset */
Status = AieResetAssert(Rst);
if (XST_SUCCESS != Status) {
goto done;
}
/* Release AIE reset */
Status = AieResetRelease(Rst);
done:
return Status;
}
static const struct ResetCustomOps {
u32 ResetIdx;
XStatus (*const ActionAssert)(XPm_ResetNode *Rst);
XStatus (*const ActionRelease)(XPm_ResetNode *Rst);
XStatus (*const ActionPulse)(XPm_ResetNode *Rst);
} Reset_Custom[] = {
{
.ResetIdx = (u32)XPM_NODEIDX_RST_PS_SRST,
.ActionAssert = &PsOnlyResetAssert,
.ActionRelease = &PsOnlyResetRelease,
.ActionPulse = &PsOnlyResetPulse,
},
{
.ResetIdx = (u32)XPM_NODEIDX_RST_LPD,
.ActionPulse = &ResetPulseLpd,
},
{
.ResetIdx = (u32)XPM_NODEIDX_RST_AIE_ARRAY,
.ActionAssert = &AieResetAssert,
.ActionRelease = &AieResetRelease,
.ActionPulse = &AieResetPulse,
},
{
.ResetIdx = (u32)XPM_NODEIDX_RST_AIE_SHIM,
.ActionAssert = &AieResetAssert,
.ActionRelease = &AieResetRelease,
.ActionPulse = &AieResetPulse,
},
};
static const struct ResetCustomOps *GetResetCustomOps(u32 ResetId)
{
u16 i;
for (i = 0; i < ARRAY_SIZE(Reset_Custom); i++) {
if (Reset_Custom[i].ResetIdx == NODEINDEX(ResetId)) {
return &Reset_Custom[i];
}
}
return NULL;
}
static XStatus Reset_AssertCustom(XPm_ResetNode *Rst, const u32 Action)
{
XStatus Status = XST_FAILURE;
u32 Mask = BITNMASK(Rst->Shift, Rst->Width);
u32 ControlReg = Rst->Node.BaseAddress;
const struct ResetCustomOps *Ops = GetResetCustomOps(Rst->Node.Id);
switch (Action) {
case (u32)PM_RESET_ACTION_RELEASE:
if ((NULL != Ops) && (NULL != Ops->ActionRelease)) {
Status = Ops->ActionRelease(Rst);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
XPm_RMW32(ControlReg, Mask, 0);
}
Rst->Node.State = XPM_RST_STATE_DEASSERTED;
Status = XST_SUCCESS;
break;
case (u32)PM_RESET_ACTION_ASSERT:
if ((NULL != Ops) && (NULL != Ops->ActionAssert)) {
Status = Ops->ActionAssert(Rst);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
XPm_RMW32(ControlReg, Mask, Mask);
}
Rst->Node.State = XPM_RST_STATE_ASSERTED;
Status = XST_SUCCESS;
break;
case (u32)PM_RESET_ACTION_PULSE:
if ((NULL != Ops) && (NULL != Ops->ActionPulse)) {
Status = Ops->ActionPulse(Rst);
if (XST_SUCCESS != Status) {
goto done;
}
Rst->Node.State = XPM_RST_STATE_DEASSERTED;
}
break;
default:
Status = XST_INVALID_PARAM;
break;
};
done:
return Status;
}
static XStatus Reset_AssertCommon(XPm_ResetNode *Rst, const u32 Action)
{
XStatus Status = XST_FAILURE;
u32 Mask = BITNMASK(Rst->Shift, Rst->Width);
u32 ControlReg = Rst->Node.BaseAddress;
switch (Action) {
case (u32)PM_RESET_ACTION_RELEASE:
XPm_RMW32(ControlReg, Mask, 0);
Rst->Node.State = XPM_RST_STATE_DEASSERTED;
Status = XST_SUCCESS;
break;
case (u32)PM_RESET_ACTION_ASSERT:
XPm_RMW32(ControlReg, Mask, Mask);
Rst->Node.State = XPM_RST_STATE_ASSERTED;
Status = XST_SUCCESS;
break;
case (u32)PM_RESET_ACTION_PULSE:
XPm_RMW32(ControlReg, Mask, Mask);
//Wait for xms ??
XPm_RMW32(ControlReg, Mask, 0);
Rst->Node.State = XPM_RST_STATE_DEASSERTED;
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
};
return Status;
}
XStatus XPmReset_AssertbyId(u32 ResetId, const u32 Action)
{
XStatus Status = XST_FAILURE;
XPm_ResetNode *Rst = XPmReset_GetById(ResetId);
if (NULL != Rst) {
Status = Rst->Ops->SetState(Rst, Action);
} else {
Status = XST_FAILURE;
}
return Status;
}
static u32 Reset_GetStatusCommon(XPm_ResetNode *Rst)
{
u32 ResetStatus = 0U;
u32 Mask = BITNMASK(Rst->Shift, Rst->Width);
if ((XPm_Read32(Rst->Node.BaseAddress) & Mask) == Mask) {
ResetStatus = 1U;
}
return ResetStatus;
}
int XPmReset_CheckPermissions(XPm_Subsystem *Subsystem, u32 ResetId)
{
int Status = XST_FAILURE;
u32 DevId;
XPm_ResetHandle *DevHandle;
XPm_ResetNode *Rst = XPmReset_GetById(ResetId);
if (NULL == Rst) {
Status = XST_INVALID_PARAM;
goto done;
}
DevHandle = Rst->RstHandles;
while (NULL != DevHandle) {
DevId = DevHandle->Device->Node.Id;
if ((u32)XPM_DEVSTATE_RUNNING == DevHandle->Device->Node.State) {
Status = XPmDevice_CheckPermissions(Subsystem, DevId);
if (XST_SUCCESS == Status) {
goto done;
}
}
DevHandle = DevHandle->NextDevice;
}
done:
return Status;
}
int XPmReset_SystemReset(void)
{
int Status = XST_FAILURE;
/* TODO: Confirm if idling is required here or not */
/*
* For, ES1, When NPI_REF clock is used a source for SYSMON, SRST hangs
* at ROM stage (EDT-994792). So, switch to IRO CLK as source of
* SYSMON_REF_CLK before issuing SRST.
*
* There is no need to set original parent of SYSMON_REF_CLK explicitly,
* as after SRST, CDO will set it to default value.
*/
if ((PLATFORM_VERSION_SILICON == Platform) &&
(PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
u16 i;
XPm_OutClockNode *Clk;
Clk = (XPm_OutClockNode *)XPmClock_GetById(PM_CLK_SYSMON_REF);
if (NULL == Clk) {
PmWarn("SYSMON_REF_CLK not found\r\n");
goto assert_reset;
}
/* Find parent index of IRO_DIV2 for SYSMON_REF_CLK */
for (i = 0; i < Clk->ClkNode.NumParents; i++) {
if (NODEINDEX(PM_CLK_MUXED_IRO_DIV2)
== Clk->Topology.MuxSources[i]) {
break;
}
}
if (i == Clk->ClkNode.NumParents) {
PmWarn("IRO_DIV2 not found as source of SYSMON_REF_CLK\r\n");
goto assert_reset;
}
/* Disable clock before changing parent */
(void)XPmClock_SetGate(Clk, 0);
Status = XPmClock_SetParent(Clk, i);
if (XST_SUCCESS == Status) {
PmWarn("Failed to change parent of SYSMON_REF_CLK\r\n");
}
(void)XPmClock_SetGate(Clk, 1);
}
assert_reset:
Status = XPmReset_AssertbyId(PM_RST_PMC, (u32)PM_RESET_ACTION_ASSERT);
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/rfdc_v8_0/src/xrfdc_hw.h
/******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrfdc_hw.h
* @addtogroup rfdc_v8_0
* @{
*
* This header file contains the identifiers and basic HW access driver
* functions (or macros) that can be used to access the device. Other driver
* functions are defined in xrfdc.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.0 sk 05/16/17 Initial release
* 2.1 sk 09/15/17 Remove Libmetal library dependency for MB.
* sk 09/21/17 Add support for Over voltage and Over
* Range interrupts.
* 2.3 sk 11/10/17 Corrected FIFO and DATA Interrupt masks.
* 2.4 sk 12/11/17 Added DDC and DUC support.
* 3.0 sg 13/01/18 Added PLL and external clock switch support
* 3.1 jm 01/24/18 Add Multi-tile sync support.
* sk 02/27/18 Add API's to configure Multiband.
* 4.0 sk 04/09/18 Removed redundant inclusion of xparameters.h file.
* 5.0 sk 08/03/18 Fixed MISRAC warnings.
* sk 08/24/18 Reorganize the code to improve readability and
* optimization.
* 5.1 cog 01/29/19 Added XRFdc_SetDither() and XRFdc_GetDither() APIs.
* 6.0 cog 02/17/19 New Interp/Decimation Mask.
* cog 02/17/19 Added new Inverse-Sinc mask.
* cog 02/17/19 Added new clock Distribution Defs.
* cog 02/17/19 Added new intratile clock Defs.
* cog 02/17/19 New Masks and offsets for XRFdc_GetPLLConfig() API.
* cog 02/17/19 New Masks and offsets for XRFdc_SetIMRPassMode() and
* XRFdc_SetIMRPassMode() APIs
* cog 02/17/19 New Masks and offsets for XRFdc_SetDACMode() and
* XRFdc_GetDACMode() APIs
* cog 02/17/19 New Masks and offsets for XRFdc_SetSignalDetector() and
* XRFdc_GetSignalDetector() APIs.
* cog 02/17/19 New Masks and offsets for XRFdc_DisableCoefficientsOverride(),
* XRFdc_SetCalCoefficients and XRFdc_GetCalCoefficients APIs.
* cog 02/19/19 New Masks and offsets for clock detection register.
* cog 02/20/19 New Masks for ADC common mode over/under voltage interrupts.
* cog 02/21/19 New Masks and offsets for XRFdc_SetCalFreeze() and
* XRFdc_GetCalFreeze() APIs.
* cog 03/25/19 The new common mode over/under voltage interrupts mask
* bits were clashing with other interrupt bits.
* cog 03/25/19 Added more calibration bypass masks.
* 7.0 cog 05/13/19 Formatting changes.
* cog 05/13/19 Added common power up interrupt masks/shifts.
* cog 07/16/19 Added XRFdc_SetDACOpCurr() API masks/shifts.
* cog 07/18/19 Added XRFdc_S/GetDigitalStepAttenuator() API masks/shifts.
* cog 07/26/19 Added XRFdc_S/GetLegacyCompatibilityMode() API shift.
* cog 08/02/19 Formatting changes.
* cog 09/01/19 Added offset for VOP control register.
* cog 09/01/19 Added masks/shifts for DSA.
* cog 09/18/19 Wider mask now needed for DAC Fabric Rate.
* cog 09/18/19 Added mask for bypassing PLL output divider.
* cog 10/02/19 Added mask for clock divider.
* cog 10/02/19 Added mask for PLL output clock divider.
* 7.1 cog 11/15/19 Added offsets & masks for calibration mode support for
* Gen 3 devices.
* cog 11/28/19 Added offset & shift for datapath modes.
* cog 01/03/19 Change shift and mask for alternate bondout devices.
* cog 01/23/20 Fixed shift and mask for GCB calibration override operations
* in Gen 3 Devices.
* 8.0 cog 02/10/20 Updated addtogroup.
* cog 02/17/20 Added masks and shifts for tile/path enables.
* cog 02/20/20 Added offsets, masks and shifts for FIFO delays.
* cog 03/20/20 Added masks and shifts for power state mask.
* cog 03/20/20 Added masks and shifts for datapath clock enables.
*
*</pre>
*
******************************************************************************/
#ifndef RFDC_HW_H_
#define RFDC_HW_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#ifdef __BAREMETAL__
#include "xil_io.h"
#endif
#include "metal/io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets from the base address of an RFDC ADC and DAC device.
* @{
*/
#define XRFDC_CLK_EN_OFFSET 0x000U /**< ADC Clock Enable Register */
#define XRFDC_ADC_DEBUG_RST_OFFSET 0x004U /**< ADC Debug Reset Register */
#define XRFDC_ADC_FABRIC_RATE_OFFSET 0x008U /**< ADC Fabric Rate Register */
#define XRFDC_DAC_FABRIC_RATE_OFFSET 0x008U /**< DAC Fabric Rate Register */
#define XRFDC_ADC_FABRIC_OFFSET 0x00CU /**< ADC Fabric Register */
#define XRFDC_ADC_FABRIC_ISR_OFFSET 0x010U /**< ADC Fabric ISR Register */
#define XRFDC_DAC_FIFO_START_OFFSET 0x010U /**< DAC FIFO Start Register */
#define XRFDC_DAC_FABRIC_ISR_OFFSET 0x014U /**< DAC Fabric ISR Register */
#define XRFDC_ADC_FABRIC_IMR_OFFSET 0x014U /**< ADC Fabric IMR Register */
#define XRFDC_DAC_FABRIC_IMR_OFFSET 0x018U /**< DAC Fabric IMR Register */
#define XRFDC_ADC_FABRIC_DBG_OFFSET 0x018U /**< ADC Fabric Debug Register */
#define XRFDC_ADC_UPDATE_DYN_OFFSET 0x01CU /**< ADC Update Dynamic Register */
#define XRFDC_DAC_UPDATE_DYN_OFFSET 0x020U /**< DAC Update Dynamic Register */
#define XRFDC_ADC_FIFO_LTNC_CRL_OFFSET 0x020U /**< ADC FIFO Latency Control Register */
#define XRFDC_ADC_DEC_ISR_OFFSET 0x030U /**< ADC Decoder interface ISR Register */
#define XRFDC_DAC_DATAPATH_OFFSET 0x034U /**< ADC Decoder interface IMR Register */
#define XRFDC_ADC_DEC_IMR_OFFSET 0x034U /**< ADC Decoder interface IMR Register */
#define XRFDC_DATPATH_ISR_OFFSET 0x038U /**< ADC Data Path ISR Register */
#define XRFDC_DATPATH_IMR_OFFSET 0x03CU /**< ADC Data Path IMR Register */
#define XRFDC_ADC_DECI_CONFIG_OFFSET 0x040U /**< ADC Decimation Config Register */
#define XRFDC_DAC_INTERP_CTRL_OFFSET 0x040U /**< DAC Interpolation Control Register */
#define XRFDC_ADC_DECI_MODE_OFFSET 0x044U /**< ADC Decimation mode Register */
#define XRFDC_DAC_ITERP_DATA_OFFSET 0x044U /**< DAC interpolation data */
#define XRFDC_ADC_MXR_CFG0_OFFSET 0x080U /**< ADC I channel mixer config Register */
#define XRFDC_ADC_MXR_CFG1_OFFSET 0x084U /**< ADC Q channel mixer config Register */
#define XRFDC_MXR_MODE_OFFSET 0x088U /**< ADC/DAC mixer mode Register */
#define XRFDC_NCO_UPDT_OFFSET 0x08CU /**< ADC/DAC NCO Update mode Register */
#define XRFDC_NCO_RST_OFFSET 0x090U /**< ADC/DAC NCO Phase Reset Register */
#define XRFDC_ADC_NCO_FQWD_UPP_OFFSET 0x094U /**< ADC NCO Frequency Word[47:32] Register */
#define XRFDC_ADC_NCO_FQWD_MID_OFFSET 0x098U /**< ADC NCO Frequency Word[31:16] Register */
#define XRFDC_ADC_NCO_FQWD_LOW_OFFSET 0x09CU /**< ADC NCO Frequency Word[15:0] Register */
#define XRFDC_NCO_PHASE_UPP_OFFSET 0x0A0U /**< ADC/DAC NCO Phase[17:16] Register */
#define XRFDC_NCO_PHASE_LOW_OFFSET 0x0A4U /**< ADC/DAC NCO Phase[15:0] Register */
#define XRFDC_ADC_NCO_PHASE_MOD_OFFSET 0x0A8U /**< ADC NCO Phase Mode Register */
#define XRFDC_QMC_UPDT_OFFSET 0x0C8U /**< ADC/DAC QMC Update Mode Register */
#define XRFDC_QMC_CFG_OFFSET 0x0CCU /**< ADC/DAC QMC Config Register */
#define XRFDC_QMC_OFF_OFFSET 0x0D0U /**< ADC/DAC QMC Offset Correction Register */
#define XRFDC_QMC_GAIN_OFFSET 0x0D4U /**< ADC/DAC QMC Gain Correction Register */
#define XRFDC_QMC_PHASE_OFFSET 0x0D8U /**< ADC/DAC QMC Phase Correction Register */
#define XRFDC_ADC_CRSE_DLY_UPDT_OFFSET 0x0DCU /**< ADC Coarse Delay Update Register */
#define XRFDC_DAC_CRSE_DLY_UPDT_OFFSET 0x0E0U /**< DAC Coarse Delay Update Register */
#define XRFDC_ADC_CRSE_DLY_CFG_OFFSET 0x0E0U /**< ADC Coarse delay Config Register */
#define XRFDC_DAC_CRSE_DLY_CFG_OFFSET 0x0DCU /**< DAC Coarse delay Config Register */
#define XRFDC_ADC_DAT_SCAL_CFG_OFFSET 0x0E4U /**< ADC Data Scaling Config Register */
#define XRFDC_ADC_SWITCH_MATRX_OFFSET 0x0E8U /**< ADC Switch Matrix Config Register */
#define XRFDC_ADC_TRSHD0_CFG_OFFSET 0x0ECU /**< ADC Threshold0 Config Register */
#define XRFDC_ADC_TRSHD0_AVG_UP_OFFSET 0x0F0U /**< ADC Threshold0 Average[31:16] Register */
#define XRFDC_ADC_TRSHD0_AVG_LO_OFFSET 0x0F4U /**< ADC Threshold0 Average[15:0] Register */
#define XRFDC_ADC_TRSHD0_UNDER_OFFSET 0x0F8U /**< ADC Threshold0 Under Threshold Register */
#define XRFDC_ADC_TRSHD0_OVER_OFFSET 0x0FCU /**< ADC Threshold0 Over Threshold Register */
#define XRFDC_ADC_TRSHD1_CFG_OFFSET 0x100U /**< ADC Threshold1 Config Register */
#define XRFDC_ADC_TRSHD1_AVG_UP_OFFSET 0x104U /**< ADC Threshold1 Average[31:16] Register */
#define XRFDC_ADC_TRSHD1_AVG_LO_OFFSET 0x108U /**< ADC Threshold1 Average[15:0] Register */
#define XRFDC_ADC_TRSHD1_UNDER_OFFSET 0x10CU /**< ADC Threshold1 Under Threshold Register */
#define XRFDC_ADC_TRSHD1_OVER_OFFSET 0x110U /**< ADC Threshold1 Over Threshold Register */
#define XRFDC_ADC_FEND_DAT_CRL_OFFSET 0x140U /**< ADC Front end Data Control Register */
#define XRFDC_ADC_TI_DCB_CRL0_OFFSET 0x144U /**< ADC Time Interleaved digital correction block gain control0 Register */
#define XRFDC_ADC_TI_DCB_CRL1_OFFSET 0x148U /**< ADC Time Interleaved digital correction block gain control1 Register */
#define XRFDC_ADC_TI_DCB_CRL2_OFFSET 0x14CU /**< ADC Time Interleaved digital correction block gain control2 Register */
#define XRFDC_ADC_TI_DCB_CRL3_OFFSET 0x150U /**< ADC Time Interleaved digital correction block gain control3 Register */
#define XRFDC_ADC_TI_TISK_CRL0_OFFSET 0x154U /**< ADC Time skew correction control bits0 Register */
#define XRFDC_DAC_MC_CFG0_OFFSET 0x1C4U /**< Static Configuration data for DAC Analog */
#define XRFDC_ADC_TI_TISK_CRL1_OFFSET 0x158U /**< ADC Time skew correction control bits1 Register */
#define XRFDC_ADC_TI_TISK_CRL2_OFFSET 0x15CU /**< ADC Time skew correction control bits2 Register */
#define XRFDC_ADC_TI_TISK_CRL3_OFFSET 0x160U /**< ADC Time skew correction control bits3 Register */
#define XRFDC_ADC_TI_TISK_CRL4_OFFSET 0x164U /**< ADC Time skew correction control bits4 Register */
#define XRFDC_ADC_TI_TISK_CRL5_OFFSET 0x168U /**< ADC Time skew correction control bits5 Register (Gen 3 only) */
#define XRFDC_ADC_TI_TISK_DAC0_OFFSET 0x168U /**< ADC Time skew DAC cal code of subadc ch0 Register(Below Gen 3) */
#define XRFDC_ADC_TI_TISK_DAC1_OFFSET 0x16CU /**< ADC Time skew DAC cal code of subadc ch1 Register */
#define XRFDC_ADC_TI_TISK_DAC2_OFFSET 0x170U /**< ADC Time skew DAC cal code of subadc ch2 Register */
#define XRFDC_ADC_TI_TISK_DAC3_OFFSET 0x174U /**< ADC Time skew DAC cal code of subadc ch3 Register */
#define XRFDC_ADC_TI_TISK_DACP0_OFFSET 0x178U /**< ADC Time skew DAC cal code of subadc ch0 Register */
#define XRFDC_ADC_TI_TISK_DACP1_OFFSET 0x17CU /**< ADC Time skew DAC cal code of subadc ch1 Register */
#define XRFDC_ADC_TI_TISK_DACP2_OFFSET 0x180U /**< ADC Time skew DAC cal code of subadc ch2 Register */
#define XRFDC_ADC_TI_TISK_DACP3_OFFSET 0x184U /**< ADC Time skew DAC cal code of subadc ch3 Register */
#define XRFDC_DAC_VOP_CTRL_OFFSET 0x198U /**< DAC variable output power control Register */
#define XRFDC_ADC0_SUBDRP_ADDR_OFFSET 0x198U /**< subadc0, sub-drp address of target Register */
#define XRFDC_ADC0_SUBDRP_DAT_OFFSET 0x19CU /**< subadc0, sub-drp data of target Register */
#define XRFDC_ADC1_SUBDRP_ADDR_OFFSET 0x1A0U /**< subadc1, sub-drp address of target Register */
#define XRFDC_ADC1_SUBDRP_DAT_OFFSET 0x1A4U /**< subadc1, sub-drp data of target Register */
#define XRFDC_ADC2_SUBDRP_ADDR_OFFSET 0x1A8U /**< subadc2, sub-drp address of target Register */
#define XRFDC_ADC2_SUBDRP_DAT_OFFSET 0x1ACU /**< subadc2, sub-drp data of target Register */
#define XRFDC_ADC3_SUBDRP_ADDR_OFFSET 0x1B0U /**< subadc3, sub-drp address of target Register */
#define XRFDC_ADC3_SUBDRP_DAT_OFFSET 0x1B4U /**< subadc3, sub-drp data of target Register */
#define XRFDC_ADC_RX_MC_PWRDWN_OFFSET 0x1C0U /**< ADC Static configuration bits for ADC(RX) analog Register */
#define XRFDC_ADC_DAC_MC_CFG0_OFFSET 0x1C4U /**< ADC/DAC Static configuration bits for ADC/DAC analog Register */
#define XRFDC_ADC_DAC_MC_CFG1_OFFSET 0x1C8U /**< ADC/DAC Static configuration bits for ADC/DAC analog Register */
#define XRFDC_ADC_DAC_MC_CFG2_OFFSET 0x1CCU /**< ADC/DAC Static configuration bits for ADC/DAC analog Register */
#define XRFDC_DAC_MC_CFG3_OFFSET 0x1D0U /**< DAC Static configuration bits for DAC analog Register */
#define XRFDC_ADC_RXPR_MC_CFG0_OFFSET 0x1D0U /**< ADC RX Pair static Configuration Register */
#define XRFDC_ADC_RXPR_MC_CFG1_OFFSET 0x1D4U /**< ADC RX Pair static Configuration Register */
#define XRFDC_ADC_TI_DCBSTS0_BG_OFFSET 0x200U /**< ADC DCB Status0 BG Register */
#define XRFDC_ADC_TI_DCBSTS0_FG_OFFSET 0x204U /**< ADC DCB Status0 FG Register */
#define XRFDC_ADC_TI_DCBSTS1_BG_OFFSET 0x208U /**< ADC DCB Status1 BG Register */
#define XRFDC_ADC_TI_DCBSTS1_FG_OFFSET 0x20CU /**< ADC DCB Status1 FG Register */
#define XRFDC_ADC_TI_DCBSTS2_BG_OFFSET 0x210U /**< ADC DCB Status2 BG Register */
#define XRFDC_ADC_TI_DCBSTS2_FG_OFFSET 0x214U /**< ADC DCB Status2 FG Register */
#define XRFDC_ADC_TI_DCBSTS3_BG_OFFSET 0x218U /**< ADC DCB Status3 BG Register */
#define XRFDC_ADC_TI_DCBSTS3_FG_OFFSET 0x21CU /**< ADC DCB Status3 FG Register */
#define XRFDC_ADC_TI_DCBSTS4_MB_OFFSET 0x220U /**< ADC DCB Status4 MSB Register */
#define XRFDC_ADC_TI_DCBSTS4_LB_OFFSET 0x224U /**< ADC DCB Status4 LSB Register */
#define XRFDC_ADC_TI_DCBSTS5_MB_OFFSET 0x228U /**< ADC DCB Status5 MSB Register */
#define XRFDC_ADC_TI_DCBSTS5_LB_OFFSET 0x22CU /**< ADC DCB Status5 LSB Register */
#define XRFDC_ADC_TI_DCBSTS6_MB_OFFSET 0x230U /**< ADC DCB Status6 MSB Register */
#define XRFDC_ADC_TI_DCBSTS6_LB_OFFSET 0x234U /**< ADC DCB Status6 LSB Register */
#define XRFDC_ADC_TI_DCBSTS7_MB_OFFSET 0x238U /**< ADC DCB Status7 MSB Register */
#define XRFDC_ADC_TI_DCBSTS7_LB_OFFSET 0x23CU /**< ADC DCB Status7 LSB Register */
#define XRFDC_DSA_UPDT_OFFSET 0x254U /**< ADC DSA Update Trigger REgister */
#define XRFDC_ADC_FIFO_LTNCY_LB_OFFSET 0x280U /**< ADC FIFO Latency measurement LSB Register */
#define XRFDC_ADC_FIFO_LTNCY_MB_OFFSET 0x284U /**< ADC FIFO Latency measurement MSB Register */
#define XRFDC_DAC_DECODER_CTRL_OFFSET 0x180U /**< DAC Unary Decoder/ Randomizer settings */
#define XRFDC_DAC_DECODER_CLK_OFFSET 0x184U /**< Decoder Clock enable */
#define XRFDC_ADC_SIG_DETECT_CTRL_OFFSET 0x114 /**< ADC Signal Detector Control */
#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET 0x118 /**< ADC Signal Detector Threshold 0 */
#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_ON_OFFSET 0x11C /**< ADC Signal Detector Threshold 0 on Counter */
#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_OFF_OFFSET 0x120 /**< ADC Signal Detector Threshold 0 off Counter */
#define XRFDC_ADC_SIG_DETECT_THRESHOLD1_LEVEL_OFFSET 0x124 /**< ADC Signal Detector Threshold 1 */
#define XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_ON_OFFSET 0x128 /**< ADC Signal Detector Threshold 1 on Counter */
#define XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_OFF_OFFSET 0x12C /**< ADC Signal Detector Threshold 1 off Counter */
#define XRFDC_ADC_SIG_DETECT_MAGN_OFFSET 0x130 /**< ADC Signal Detector Magintude */
#define XRFDC_HSCOM_CLK_DSTR_OFFSET 0x088U /**< Clock Distribution Register*/
#define XRFDC_HSCOM_CLK_DSTR_MASK 0xC788U /**< Clock Distribution Register*/
#define XRFDC_HSCOM_CLK_DSTR_MASK_ALT 0x1870U /**< Clock Distribution Register for Intratile*/
#define XRFDC_HSCOM_PWR_OFFSET 0x094 /**< Control register during power-up sequence */
#define XRFDC_HSCOM_CLK_DIV_OFFSET 0xB0 /**< Fabric clk out divider */
#define XRFDC_HSCOM_PWR_STATE_OFFSET 0xB4 /**< Check powerup state */
#define XRFDC_HSCOM_UPDT_DYN_OFFSET 0x0B8 /**< Trigger the update dynamic event */
#define XRFDC_HSCOM_EFUSE_2_OFFSET 0x144
#define XRFDC_DAC_INVSINC_OFFSET 0x0C0U /**< Invsinc control */
#define XRFDC_DAC_MB_CFG_OFFSET 0x0C4U /**< Multiband config */
#define XRFDC_MTS_SRDIST 0x1CA0U
#define XRFDC_MTS_SRCAP_T1 (0x24U << 2U)
#define XRFDC_MTS_SRCAP_PLL (0x0CU << 2U)
#define XRFDC_MTS_SRCAP_DIG (0x2CU << 2U)
#define XRFDC_MTS_SRDTC_T1 (0x27U << 2U)
#define XRFDC_MTS_SRDTC_PLL (0x26U << 2U)
#define XRFDC_MTS_SRFLAG (0x49U << 2U)
#define XRFDC_MTS_CLKSTAT (0x24U << 2U)
#define XRFDC_MTS_SRCOUNT_CTRL 0x004CU
#define XRFDC_MTS_SRCOUNT_VAL 0x0050U
#define XRFDC_MTS_SRFREQ_VAL 0x0054U
#define XRFDC_MTS_FIFO_CTRL_ADC 0x0010U
#define XRFDC_MTS_FIFO_CTRL_DAC 0x0014U
#define XRFDC_MTS_DELAY_CTRL 0x0028U
#define XRFDC_MTS_ADC_MARKER 0x0018U
#define XRFDC_MTS_ADC_MARKER_CNT 0x0010U
#define XRFDC_MTS_DAC_MARKER_CTRL 0x0048U
#define XRFDC_MTS_DAC_MARKER_CNT (0x92U << 2U)
#define XRFDC_MTS_DAC_MARKER_LOC (0x93U << 2U)
#define XRFDC_MTS_DAC_FIFO_MARKER_CTRL (0x94U << 2U)
#define XRFDC_MTS_DAC_FABRIC_OFFSET 0x0C
#define XRFDC_RESET_OFFSET 0x00U /**< Tile reset register */
#define XRFDC_RESTART_OFFSET 0x04U /**< Tile restart register */
#define XRFDC_RESTART_STATE_OFFSET 0x08U /**< Tile restart state register */
#define XRFDC_CURRENT_STATE_OFFSET 0x0CU /**< Current state register */
#define XRFDC_CLOCK_DETECT_OFFSET 0x80U /**< Clock detect register */
#define XRFDC_STATUS_OFFSET 0x228U /**< Common status register */
#define XRFDC_COMMON_INTR_STS 0x100U /**< Common Intr Status register */
#define XRFDC_COMMON_INTR_ENABLE 0x104U /**< Common Intr enable register */
#define XRFDC_INTR_STS 0x200U /**< Intr status register */
#define XRFDC_INTR_ENABLE 0x204U /**< Intr enable register */
#define XRFDC_CONV_INTR_STS(X) (0x208U + (X * 0x08U))
#define XRFDC_CONV_INTR_EN(X) (0x20CU + (X * 0x08U))
#define XRFDC_CONV_CAL_STGS(X) (0x234U + (X * 0x04U))
#define XRFDC_CONV_DSA_STGS(X) (0x244U + (X * 0x04U))
#define XRFDC_CAL_GCB_COEFF0_FAB(X) (0x280U + (X * 0x10U))
#define XRFDC_CAL_GCB_COEFF1_FAB(X) (0x284U + (X * 0x10U))
#define XRFDC_CAL_GCB_COEFF2_FAB(X) (0x288U + (X * 0x10U))
#define XRFDC_CAL_GCB_COEFF3_FAB(X) (0x28CU + (X * 0x10U))
#define XRFDC_PLL_FREQ 0x300U /**< PLL output frequency (before divider) register */
#define XRFDC_PLL_FS 0x304U /**< Sampling rate register */
#define XRFDC_FIFO_ENABLE 0x230U /**< FIFO Enable and Disable */
#define XRFDC_PLL_SDM_CFG0 0x00U /**< PLL Configuration bits for sdm */
#define XRFDC_PLL_SDM_SEED0 0x18U /**< PLL Bits for sdm LSB */
#define XRFDC_PLL_SDM_SEED1 0x1CU /**< PLL Bits for sdm MSB */
#define XRFDC_PLL_VREG 0x44U /**< PLL bits for voltage regulator */
#define XRFDC_PLL_VCO0 0x54U /**< PLL bits for coltage controlled oscillator LSB */
#define XRFDC_PLL_VCO1 0x58U /**< PLL bits for coltage controlled oscillator MSB */
#define XRFDC_PLL_CRS1 0x28U /**< PLL bits for coarse frequency control LSB */
#define XRFDC_PLL_CRS2 0x2CU /**< PLL bits for coarse frequency control MSB */
#define XRFDC_PLL_DIVIDER0 0x30U /**< PLL Output Divider LSB register */
#define XRFDC_PLL_DIVIDER1 0x34U /**< PLL Output Divider MSB register */
#define XRFDC_PLL_SPARE0 0x38U /**< PLL spare inputs LSB */
#define XRFDC_PLL_SPARE1 0x3CU /**< PLL spare inputs MSB */
#define XRFDC_PLL_REFDIV 0x40U /**< PLL Reference Divider register */
#define XRFDC_PLL_VREG 0x44U /**< PLL voltage regulator */
#define XRFDC_PLL_CHARGEPUMP 0x48U /**< PLL bits for charge pumps */
#define XRFDC_PLL_LPF0 0x4CU /**< PLL bits for loop filters LSB */
#define XRFDC_PLL_LPF1 0x50U /**< PLL bits for loop filters MSB */
#define XRFDC_PLL_FPDIV 0x5CU /**< PLL Feedback Divider register */
#define XRFDC_CLK_NETWORK_CTRL0 0x8CU /**< Clock network control and trim register */
#define XRFDC_CLK_NETWORK_CTRL1 0x90U /**< Multi-tile sync and clock source control register */
#define XRFDC_HSCOM_NETWORK_CTRL1_MASK 0x02FU /**< Clock Network Register Mask for IntraTile*/
#define XRFDC_PLL_REFDIV_MASK 0x0E0U /**< PLL Reference Divider Register Mask for IntraTile */
#define XRFDC_PLL_DIVIDER0_ALT_MASK 0xC00U /**< PLL Output Divider Register Mask for IntraTile */
#define XRFDC_PLL_DIVIDER0_BYPPLL_MASK 0x800U /**< PLL Output Divider Register Mask for IntraTile */
#define XRFDC_PLL_DIVIDER0_BYPDIV_MASK 0x400U /**< PLL Output Divider Register Mask for IntraTile */
#define XRFDC_CAL_OCB1_OFFSET_COEFF0 0x200 /**< Foreground offset correction block */
#define XRFDC_CAL_OCB1_OFFSET_COEFF1 0x208 /**< Foreground offset correction block */
#define XRFDC_CAL_OCB1_OFFSET_COEFF2 0x210 /**< Foreground offset correction block */
#define XRFDC_CAL_OCB1_OFFSET_COEFF3 0x218 /**< Foreground offset correction block */
#define XRFDC_CAL_OCB2_OFFSET_COEFF0 0x204 /**< Background offset correction block */
#define XRFDC_CAL_OCB2_OFFSET_COEFF1 0x20C /**< Background offset correction block */
#define XRFDC_CAL_OCB2_OFFSET_COEFF2 0x214 /**< Background offset correction block */
#define XRFDC_CAL_OCB2_OFFSET_COEFF3 0x21C /**< Background offset correction block */
#define XRFDC_CAL_GCB_OFFSET_COEFF0 0x220 /**< Background gain correction block */
#define XRFDC_CAL_GCB_OFFSET_COEFF1 0x224 /**< Background gain correction block */
#define XRFDC_CAL_GCB_OFFSET_COEFF2 0x228 /**< Background gain correction block */
#define XRFDC_CAL_GCB_OFFSET_COEFF3 0x22C /**< Background gain correction block */
#define XRFDC_CAL_GCB_OFFSET_COEFF0_ALT 0x220 /**< Background gain correction block (below Gen 3) */
#define XRFDC_CAL_GCB_OFFSET_COEFF1_ALT 0x228 /**< Background gain correction block (below Gen 3) */
#define XRFDC_CAL_GCB_OFFSET_COEFF2_ALT 0x230 /**< Background gain correction block (below Gen 3) */
#define XRFDC_CAL_GCB_OFFSET_COEFF3_ALT 0x238 /**< Background gain correction block (below Gen 3) */
#define XRFDC_CAL_TSCB_OFFSET_COEFF0 0x170 /**< Background time skew correction block */
#define XRFDC_CAL_TSCB_OFFSET_COEFF1 0x174 /**< Background time skew correction block */
#define XRFDC_CAL_TSCB_OFFSET_COEFF2 0x178 /**< Background time skew correction block */
#define XRFDC_CAL_TSCB_OFFSET_COEFF3 0x17C /**< Background time skew correction block */
#define XRFDC_CAL_TSCB_OFFSET_COEFF4 0x180 /**< Background time skew correction block */
#define XRFDC_CAL_TSCB_OFFSET_COEFF5 0x184 /**< Background time skew correction block */
#define XRFDC_CAL_TSCB_OFFSET_COEFF6 0x188 /**< Background time skew correction block */
#define XRFDC_CAL_TSCB_OFFSET_COEFF7 0x18C /**< Background time skew correction block */
#define XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT 0x168 /**< Background time skew correction block (below Gen 3) */
#define XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT 0x16C /**< Background time skew correction block (below Gen 3) */
#define XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT 0x170 /**< Background time skew correction block (below Gen 3) */
#define XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT 0x174 /**< Background time skew correction block (below Gen 3) */
#define XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT 0x178 /**< Background time skew correction block (below Gen 3) */
#define XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT 0x17C /**< Background time skew correction block (below Gen 3) */
#define XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT 0x180 /**< Background time skew correction block (below Gen 3) */
#define XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT 0x184 /**< Background time skew correction block (below Gen 3) */
#define XRFDC_HSCOM_FIFO_START_OFFSET 0x0C0U /**< FIFO Start register tommon along tile */
/* @} */
/** @name IP Register Map
*
* Register offsets from the base address of the IP.
* @{
*/
#define XRFDC_TILES_ENABLED_OFFSET 0x00A0U /**< The tiles enabled in the design */
#define XRFDC_ADC_PATHS_ENABLED_OFFSET 0x00A4U /**< The ADC analogue/digital paths enabled in the design */
#define XRFDC_DAC_PATHS_ENABLED_OFFSET 0x00A8U /**< The DAC analogue/digital paths enabled in the design */
#define XRFDC_PATH_ENABLED_TILE_SHIFT 4U /**< A shift to get to the correct tile for the path */
/* @} */
/** @name Calibration Mode - Calibration mode registers
*
* This register contains bits for calibration modes
* for ADC.
* @{
*/
#define XRFDC_CAL_MODES_MASK 0x0003 /**< Calibration modes for Gen 3 mask*/
/* @} */
/** @name Calibration Coefficients - Calibration coefficients and disable registers
*
* This register contains bits for calibration coefficients
* for ADC.
* @{
*/
#define XRFDC_CAL_OCB_MASK 0xFFFFU /**< offsets coeff mask*/
#define XRFDC_CAL_GCB_MASK 0x0FFFU /**< gain coeff mask*/
#define XRFDC_CAL_GCB_FAB_MASK 0xFFF0U /**< gain coeff mask for IP Gen 2 or below*/
#define XRFDC_CAL_TSCB_MASK 0x01FFU /**< time skew coeff mask*/
#define XRFDC_CAL_GCB_FLSH_MASK 0x1000U /**< GCB accumulator flush mask*/
#define XRFDC_CAL_GCB_ACEN_MASK 0x0800U /**< GCB accumulator enable mask*/
#define XRFDC_CAL_GCB_ENFL_MASK 0x1800U /**< GCB accumulator enable mask*/
#define XRFDC_CAL_OCB_EN_MASK 0x0001U /**< offsets coeff override enable mask*/
#define XRFDC_CAL_GCB_EN_MASK 0x2000U /**< gain coeff override enable mask*/
#define XRFDC_CAL_TSCB_EN_MASK 0x8000U /**< time skew coeff override enable mask*/
#define XRFDC_CAL_OCB_EN_SHIFT 0U /**< offsets coeff shift*/
#define XRFDC_CAL_GCB_EN_SHIFT 13U /**< gain coeff shift*/
#define XRFDC_CAL_TSCB_EN_SHIFT 15U /**< time skew coeff shift*/
#define XRFDC_CAL_GCB_FLSH_SHIFT 12U /**< GCB accumulator flush shift*/
#define XRFDC_CAL_GCB_ACEN_SHIFT 11U /**< GCB accumulator enable shift*/
#define XRFDC_CAL_SLICE_SHIFT 16U /**<Coefficient shift for HSADCs*/
/* @} */
/** @name Calibration Coefficients - Calibration coefficients and disable registers
*
* This register contains bits for calibration coefficients
* for ADC.
* @{
*/
#define XRFDC_CAL_FREEZE_CAL_MASK 0x1U /**< Calibration freeze enable mask*/
#define XRFDC_CAL_FREEZE_STS_MASK 0x2U /**< Calibration freeze status mask*/
#define XRFDC_CAL_FREEZE_PIN_MASK 0x4U /**< Calibration freeze pin disable mask*/
#define XRFDC_CAL_FREEZE_CAL_SHIFT 0U /**< Calibration freeze enable shift*/
#define XRFDC_CAL_FREEZE_STS_SHIFT 1U /**< Calibration freeze status shift*/
#define XRFDC_CAL_FREEZE_PIN_SHIFT 2U /**< Calibration freeze pin disable shift*/
/* @} */
/** @name FIFO Enable - FIFO enable and disable register
*
* This register contains bits for FIFO enable and disable
* for ADC and DAC.
* @{
*/
#define XRFDC_FIFO_EN_MASK 0x00000001U /**< FIFO enable/disable */
#define XRFDC_RESTART_MASK 0x00000001U /**< Restart bit mask */
/* @} */
/** @name Clock Enable - FIFO Latency, fabric, DataPath,
* full-rate, output register
*
* This register contains bits for various clock enable options of
* the ADC. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_CLK_EN_CAL_MASK 0x00000001U /**< Enable Output Register clock */
#define XRFDC_CLK_EN_DIG_MASK 0x00000002U /**< Enable full-rate clock */
#define XRFDC_CLK_EN_DP_MASK 0x00000004U /**< Enable Data Path clock */
#define XRFDC_CLK_EN_FAB_MASK 0x00000008U /**< Enable fabric clock */
#define XRFDC_DAT_CLK_EN_MASK 0x0000000FU /**< Data Path Clk enable */
#define XRFDC_CLK_EN_LM_MASK 0x00000010U /**< Enable for FIFO Latency measurement clock */
/* @} */
/** @name Debug reset - FIFO Latency, fabric, DataPath,
* full-rate, output register
*
* This register contains bits for various Debug reset options of
* the ADC. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_DBG_RST_CAL_MASK 0x00000001U /**< Reset clk_cal clock domain */
#define XRFDC_DBG_RST_DP_MASK 0x00000002U /**< Reset data path clock domain */
#define XRFDC_DBG_RST_FAB_MASK 0x00000004U /**< Reset clock fabric clock domain */
#define XRFDC_DBG_RST_DIG_MASK 0x00000008U /**< Reset clk_dig clock domain */
#define XRFDC_DBG_RST_DRP_CAL_MASK 0x00000010U /**< Reset subadc-drp register on clock cal */
#define XRFDC_DBG_RST_LM_MASK 0x00000020U /**< Reset FIFO Latency measurement clock domain */
/* @} */
/** @name Fabric rate - Fabric data rate for read and write
*
* This register contains bits for read and write fabric data
* rate for ADC. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_ADC_FAB_RATE_WR_MASK 0x0000000FU /**< ADC FIFO Write Number of Words per clock */
#define XRFDC_DAC_FAB_RATE_WR_MASK 0x0000001FU /**< DAC FIFO Write Number of Words per clock */
#define XRFDC_ADC_FAB_RATE_RD_MASK 0x00000F00U /**< ADC FIFO Read Number of Words per clock */
#define XRFDC_DAC_FAB_RATE_RD_MASK 0x00001F00U /**< DAC FIFO Read Number of Words per clock */
#define XRFDC_FAB_RATE_RD_SHIFT 8U /**< Fabric Read shift */
/* @} */
/** @name Fabric Offset - FIFO de-skew
*
* This register contains bits of Fabric Offset.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_FAB_RD_PTR_OFFST_MASK 0x0000003FU /**< FIFO read pointer offset for interface de-skew */
/* @} */
/** @name Fabric ISR - Interrupt status register for FIFO interface
*
* This register contains bits of margin-indicator and user-data overlap
* (overflow/underflow). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_FAB_ISR_USRDAT_OVR_MASK 0x00000001U /**< User-data overlap- data written faster than read (overflow) */
#define XRFDC_FAB_ISR_USRDAT_UND_MASK 0x00000002U /**< User-data overlap- data read faster than written (underflow) */
#define XRFDC_FAB_ISR_USRDAT_MASK 0x00000003U /**< User-data overlap Mask */
#define XRFDC_FAB_ISR_MARGIND_OVR_MASK 0x00000004U /**< Marginal-indicator overlap (overflow) */
#define XRFDC_FAB_ISR_MARGIND_UND_MASK 0x00000008U /**< Marginal-indicator overlap (underflow) */
/* @} */
/** @name Fabric IMR - Interrupt mask register for FIFO interface
*
* This register contains bits of margin-indicator and user-data overlap
* (overflow/underflow). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_FAB_IMR_USRDAT_OVR_MASK 0x00000001U /**< User-data overlap- data written faster than read (overflow) */
#define XRFDC_FAB_IMR_USRDAT_UND_MASK 0x00000002U /**< User-data overlap- data read faster than written (underflow) */
#define XRFDC_FAB_IMR_USRDAT_MASK 0x00000003U /**< User-data overlap Mask */
#define XRFDC_FAB_IMR_MARGIND_OVR_MASK 0x00000004U /**< Marginal-indicator overlap (overflow) */
#define XRFDC_FAB_IMR_MARGIND_UND_MASK 0x00000008U /**< Marginal-indicator overlap (underflow) */
/* @} */
/** @name Update Dynamic - Trigger a dynamic update event
*
* This register contains bits of update event for slice, nco, qmc
* and coarse delay. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_UPDT_EVNT_MASK 0x0000000FU /**< Update event mask */
#define XRFDC_UPDT_EVNT_SLICE_MASK 0x00000001U /**< Trigger a slice update event apply to _DCONFIG reg */
#define XRFDC_UPDT_EVNT_NCO_MASK 0x00000002U /**< Trigger a update event apply to NCO_DCONFIG reg */
#define XRFDC_UPDT_EVNT_QMC_MASK 0x00000004U /**< Trigger a update event apply to QMC_DCONFIG reg */
#define XRFDC_ADC_UPDT_CRSE_DLY_MASK 0x00000008U /**< ADC Trigger a update event apply to Coarse delay_DCONFIG reg */
#define XRFDC_DAC_UPDT_CRSE_DLY_MASK 0x00000020U /**< DAC Trigger a update event apply to Coarse delay_DCONFIG reg */
/* @} */
/** @name FIFO Latency control - Config registers for FIFO Latency measurement
*
* This register contains bits of FIFO Latency ctrl for disable, restart and
* set fifo latency measurement. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_FIFO_LTNCY_PRD_MASK 0x00000007U /**< Set FIFO Latency measurement period */
#define XRFDC_FIFO_LTNCY_RESTRT_MASK 0x00000008U /**< Restart FIFO Latency measurement */
#define XRFDC_FIFO_LTNCY_DIS_MASK 0x000000010U /**< Disable FIFO Latency measurement */
/* @} */
/** @name Decode ISR - ISR for Decoder Interface
*
* This register contains bits of subadc 0,1,2 and 3 decoder overflow
* and underflow range. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_DEC_ISR_SUBADC_MASK 0x000000FFU /**< subadc decoder Mask */
#define XRFDC_DEC_ISR_SUBADC0_UND_MASK 0x00000001U /**< subadc0 decoder underflow range */
#define XRFDC_DEC_ISR_SUBADC0_OVR_MASK 0x00000002U /**< subadc0 decoder overflow range */
#define XRFDC_DEC_ISR_SUBADC1_UND_MASK 0x00000004U /**< subadc1 decoder underflow range */
#define XRFDC_DEC_ISR_SUBADC1_OVR_MASK 0x00000008U /**< subadc1 decoder overflow range */
#define XRFDC_DEC_ISR_SUBADC2_UND_MASK 0x00000010U /**< subadc2 decoder underflow range */
#define XRFDC_DEC_ISR_SUBADC2_OVR_MASK 0x00000020U /**< subadc2 decoder overflow range */
#define XRFDC_DEC_ISR_SUBADC3_UND_MASK 0x00000040U /**< subadc3 decoder underflow range */
#define XRFDC_DEC_ISR_SUBADC3_OVR_MASK 0x00000080U /**< subadc3 decoder overflow range */
/* @} */
/** @name Decode IMR - IMR for Decoder Interface
*
* This register contains bits of subadc 0,1,2 and 3 decoder overflow
* and underflow range. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_DEC_IMR_SUBADC0_UND_MASK 0x00000001U /**< subadc0 decoder underflow range */
#define XRFDC_DEC_IMR_SUBADC0_OVR_MASK 0x00000002U /**< subadc0 decoder overflow range */
#define XRFDC_DEC_IMR_SUBADC1_UND_MASK 0x00000004U /**< subadc1 decoder underflow range */
#define XRFDC_DEC_IMR_SUBADC1_OVR_MASK 0x00000008U /**< subadc1 decoder overflow range */
#define XRFDC_DEC_IMR_SUBADC2_UND_MASK 0x00000010U /**< subadc2 decoder underflow range */
#define XRFDC_DEC_IMR_SUBADC2_OVR_MASK 0x00000020U /**< subadc2 decoder overflow range */
#define XRFDC_DEC_IMR_SUBADC3_UND_MASK 0x00000040U /**< subadc3 decoder underflow range */
#define XRFDC_DEC_IMR_SUBADC3_OVR_MASK 0x00000080U /**< subadc3 decoder overflow range */
#define XRFDC_DEC_IMR_MASK 0x000000FFU
/* @} */
/** @name DataPath (DAC)- FIFO Latency, Image Reject Filter, Mode,
*
* This register contains bits for DataPath latency, Image Reject Filter
* and the Mode for the DAC. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_DATAPATH_MODE_MASK 0x00000003U /**< DataPath Mode */
#define XRFDC_DATAPATH_IMR_MASK 0x00000004U /**< IMR Mode */
#define XRFDC_DATAPATH_LATENCY_MASK 0x00000008U /**< DataPath Latency */
#define XRFDC_DATAPATH_IMR_SHIFT 2U /**< IMR Mode shift */
/* @} */
/** @name DataPath ISR - ISR for Data Path interface
*
* This register contains bits of QMC Gain/Phase overflow, offset overflow,
* Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_ADC_DAT_PATH_ISR_MASK 0x000000FFU /**< ADC Data Path Overflow */
#define XRFDC_DAC_DAT_PATH_ISR_MASK 0x000001FFU /**< DAC Data Path Overflow */
#define XRFDC_DAT_ISR_DECI_IPATH_MASK 0x00000007U /**< Decimation I-Path overflow for stages 0,1,2 */
#define XRFDC_DAT_ISR_INTR_QPATH_MASK 0x00000038U /**< Interpolation Q-Path overflow for stages 0,1,2 */
#define XRFDC_DAT_ISR_QMC_GAIN_MASK 0x00000040U /**< QMC Gain/Phase overflow */
#define XRFDC_DAT_ISR_QMC_OFFST_MASK 0x00000080U /**< QMC offset overflow */
#define XRFDC_DAC_DAT_ISR_INVSINC_MASK 0x00000100U /**< Inverse-Sinc offset overflow */
/* @} */
/** @name DataPath IMR - IMR for Data Path interface
*
* This register contains bits of QMC Gain/Phase overflow, offset overflow,
* Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_DAT_IMR_DECI_IPATH_MASK 0x00000007U /**< Decimation I-Path overflow for stages 0,1,2 */
#define XRFDC_DAT_IMR_INTR_QPATH_MASK 0x00000038U /**< Interpolation Q-Path overflow for stages 0,1,2 */
#define XRFDC_DAT_IMR_QMC_GAIN_MASK 0x00000040U /**< QMC Gain/Phase overflow */
#define XRFDC_DAT_IMR_QMC_OFFST_MASK 0x00000080U /**< QMC offset overflow */
#define XRFDC_ADC_DAT_IMR_MASK 0x000000FFU /**< ADC DataPath mask */
#define XRFDC_DAC_DAT_IMR_MASK 0x00000FFFU /**< DAC DataPath mask */
/* @} */
/** @name Decimation Config - Decimation control
*
* This register contains bits to configure the decimation in terms of
* the type of data. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_DEC_CFG_MASK 0x00000003U /**< ChannelA (2GSPS real data from Mixer I output) */
#define XRFDC_DEC_CFG_CHA_MASK 0x00000000U /**< ChannelA(I) */
#define XRFDC_DEC_CFG_CHB_MASK 0x00000001U /**< ChannelB (2GSPS real data from Mixer Q output) */
#define XRFDC_DEC_CFG_IQ_MASK 0x00000002U /**< IQ-2GSPS */
#define XRFDC_DEC_CFG_4GSPS_MASK 0x00000003U /**< 4GSPS may be I or Q or Real depending on high level block config */
/* @} */
/** @name Decimation Mode - Decimation Rate
*
* This register contains bits to configures the decimation rate.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_DEC_MOD_MASK 0x00000007U /**< Decimation mode Mask */
#define XRFDC_DEC_MOD_MASK_EXT 0x0000003FU /**< Decimation mode Mask */
/* @} */
/** @name Mixer config0 - Configure I channel coarse mixer mode of operation
*
* This register contains bits to set the output data sequence of
* I channel. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_MIX_CFG0_MASK 0x00000FFFU /**< Mixer Config0 Mask */
#define XRFDC_MIX_I_DAT_WRD0_MASK 0x00000007U /**< Output data word[0] of I channel */
#define XRFDC_MIX_I_DAT_WRD1_MASK 0x00000038U /**< Output data word[1] of I channel */
#define XRFDC_MIX_I_DAT_WRD2_MASK 0x000001C0U /**< Output data word[2] of I channel */
#define XRFDC_MIX_I_DAT_WRD3_MASK 0x00000E00U /**< Output data word[3] of I channel */
/* @} */
/** @name Mixer config1 - Configure Q channel coarse mixer mode of operation
*
* This register contains bits to set the output data sequence of
* Q channel. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_MIX_CFG1_MASK 0x00000FFFU /**< Mixer Config0 Mask */
#define XRFDC_MIX_Q_DAT_WRD0_MASK 0x00000007U /**< Output data word[0] of Q channel */
#define XRFDC_MIX_Q_DAT_WRD1_MASK 0x00000038U /**< Output data word[1] of Q channel */
#define XRFDC_MIX_Q_DAT_WRD2_MASK 0x000001C0U /**< Output data word[2] of Q channel */
#define XRFDC_MIX_Q_DAT_WRD3_MASK 0x00000E00U /**< Output data word[3] of Q channel */
/* @} */
/** @name Mixer mode - Configure mixer mode of operation
*
* This register contains bits to set NCO phases, NCO output scale
* and fine mixer multipliers. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_EN_I_IQ_MASK 0x00000003U /**< Enable fine mixer multipliers on IQ i/p for I output */
#define XRFDC_EN_Q_IQ_MASK 0x0000000CU /**< Enable fine mixer multipliers on IQ i/p for Q output */
#define XRFDC_FINE_MIX_SCALE_MASK 0x00000010U /**< NCO output scale */
#define XRFDC_SEL_I_IQ_MASK 0x00000F00U /**< Select NCO phases for I output */
#define XRFDC_SEL_Q_IQ_MASK 0x0000F000U /**< Select NCO phases for Q output */
#define XRFDC_I_IQ_COS_MINSIN 0x00000C00U /**< Select NCO phases for I output */
#define XRFDC_Q_IQ_SIN_COS 0x00001000U /**< Select NCO phases for Q output */
#define XRFDC_MIXER_MODE_C2C_MASK 0x0000000FU /**< Mixer mode C2C Mask */
#define XRFDC_MIXER_MODE_R2C_MASK 0x00000005U /**< Mixer mode R2C Mask */
#define XRFDC_MIXER_MODE_C2R_MASK 0x00000003U /**< Mixer mode C2R Mask */
#define XRFDC_MIXER_MODE_OFF_MASK 0x00000000U /**< Mixer mode OFF Mask */
/* @} */
/** @name NCO update - NCO update mode
*
* This register contains bits to Select event source, delay and reset delay.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_NCO_UPDT_MODE_MASK 0x00000007U /**< NCO event source selection mask */
#define XRFDC_NCO_UPDT_MODE_GRP 0x00000000U /**< NCO event source selection is Group */
#define XRFDC_NCO_UPDT_MODE_SLICE 0x00000001U /**< NCO event source selection is slice */
#define XRFDC_NCO_UPDT_MODE_TILE 0x00000002U /**< NCO event source selection is tile */
#define XRFDC_NCO_UPDT_MODE_SYSREF 0x00000003U /**< NCO event source selection is Sysref */
#define XRFDC_NCO_UPDT_MODE_MARKER 0x00000004U /**< NCO event source selection is Marker */
#define XRFDC_NCO_UPDT_MODE_FABRIC 0x00000005U /**< NCO event source selection is fabric */
#define XRFDC_NCO_UPDT_DLY_MASK 0x00001FF8U /**< delay in clk_dp cycles in application of event after arrival */
#define XRFDC_NCO_UPDT_RST_DLY_MASK 0x0000D000U /**< optional delay on the NCO phase reset delay */
/* @} */
/** @name NCO Phase Reset - NCO Slice Phase Reset
*
* This register contains bits to reset the nco phase of the current
* slice phase accumulator. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_NCO_PHASE_RST_MASK 0x00000001U /**< Reset NCO Phase of current slice */
/* @} */
/** @name DAC interpolation data
*
* This register contains bits for DAC interpolation data type
* @{
*/
#define XRFDC_DAC_INTERP_DATA_MASK 0x00000001U /**< Data type mask */
/* @} */
/** @name NCO Freq Word[47:32] - NCO Phase increment(nco freq 48-bit)
*
* This register contains bits for frequency control word of the
* NCO. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_NCO_FQWD_UPP_MASK 0x0000FFFFU /**< NCO Phase increment[47:32] */
#define XRFDC_NCO_FQWD_UPP_SHIFT 32U /**< Freq Word upper shift */
/* @} */
/** @name NCO Freq Word[31:16] - NCO Phase increment(nco freq 48-bit)
*
* This register contains bits for frequency control word of the
* NCO. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_NCO_FQWD_MID_MASK 0x0000FFFFU /**< NCO Phase increment[31:16] */
#define XRFDC_NCO_FQWD_MID_SHIFT 16U /**< Freq Word Mid shift */
/* @} */
/** @name NCO Freq Word[15:0] - NCO Phase increment(nco freq 48-bit)
*
* This register contains bits for frequency control word of the
* NCO. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_NCO_FQWD_LOW_MASK 0x0000FFFFU /**< NCO Phase increment[15:0] */
#define XRFDC_NCO_FQWD_MASK 0x0000FFFFFFFFFFFFU /**< NCO Freq offset[48:0] */
/* @} */
/** @name NCO Phase Offset[17:16] - NCO Phase offset
*
* This register contains bits to set NCO Phase offset(18-bit offset
* added to the phase accumulator). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_NCO_PHASE_UPP_MASK 0x00000003U /**< NCO Phase offset[17:16] */
#define XRFDC_NCO_PHASE_UPP_SHIFT 16U /**< NCO phase upper shift */
/* @} */
/** @name NCO Phase Offset[15:0] - NCO Phase offset
*
* This register contains bits to set NCO Phase offset(18-bit offset
* added to the phase accumulator). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_NCO_PHASE_LOW_MASK 0x0000FFFFU /**< NCO Phase offset[15:0] */
#define XRFDC_NCO_PHASE_MASK 0x0003FFFFU /**< NCO Phase offset[17:0] */
/* @} */
/** @name NCO Phase mode - NCO Control setting mode
*
* This register contains bits to set NCO mode of operation.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_NCO_PHASE_MOD_MASK 0x00000003U /**< NCO mode of operation mask */
#define XRFDC_NCO_PHASE_MOD_4PHASE 0x00000003U /**< NCO output 4 successive phase */
#define XRFDC_NCO_PHASE_MOD_EVEN 0x00000001U /**< NCO output even phase */
#define XRFDC_NCO_PHASE_MODE_ODD 0x00000002U /**< NCO output odd phase */
/* @} */
/** @name QMC update - QMC update mode
*
* This register contains bits to Select event source and delay.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_QMC_UPDT_MODE_MASK 0x00000007U /**< QMC event source selection mask */
#define XRFDC_QMC_UPDT_MODE_GRP 0x00000000U /**< QMC event source selection is group */
#define XRFDC_QMC_UPDT_MODE_SLICE 0x00000001U /**< QMC event source selection is slice */
#define XRFDC_QMC_UPDT_MODE_TILE 0x00000002U /**< QMC event source selection is tile */
#define XRFDC_QMC_UPDT_MODE_SYSREF 0x00000003U /**< QMC event source selection is Sysref */
#define XRFDC_QMC_UPDT_MODE_MARKER 0x00000004U /**< QMC event source selection is Marker */
#define XRFDC_QMC_UPDT_MODE_FABRIC 0x00000005U /**< QMC event source selection is fabric */
#define XRFDC_QMC_UPDT_DLY_MASK 0x00001FF8U /**< delay in clk_dp cycles in application of event after arrival */
/* @} */
/** @name QMC Config - QMC Config register
*
* This register contains bits to enable QMC gain and QMC
* Phase correction. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_QMC_CFG_EN_GAIN_MASK 0x00000001U /**< enable QMC gain correction mask */
#define XRFDC_QMC_CFG_EN_PHASE_MASK 0x00000002U /**< enable QMC Phase correction mask */
#define XRFDC_QMC_CFG_PHASE_SHIFT 1U /**< QMC config phase shift */
/* @} */
/** @name QMC Offset - QMC offset correction
*
* This register contains bits to set QMC offset correction
* factor. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_QMC_OFFST_CRCTN_MASK 0x00000FFFU /**< QMC offset correction factor */
/* @} */
/** @name QMC Gain - QMC Gain correction
*
* This register contains bits to set QMC gain correction
* factor. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_QMC_GAIN_CRCTN_MASK 0x00003FFFU /**< QMC gain correction factor */
/* @} */
/** @name QMC Phase - QMC Phase correction
*
* This register contains bits to set QMC phase correction
* factor. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_QMC_PHASE_CRCTN_MASK 0x00000FFFU /**< QMC phase correction factor */
/* @} */
/** @name Coarse Delay Update - Coarse delay update mode.
*
* This register contains bits to Select event source and delay.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_CRSEDLY_UPDT_MODE_MASK 0x00000007U /**< Coarse delay event source selection mask */
#define XRFDC_CRSEDLY_UPDT_MODE_GRP 0x00000000U /**< Coarse delay event source selection is group */
#define XRFDC_CRSEDLY_UPDT_MODE_SLICE 0x00000001U /**< Coarse delay event source selection is slice */
#define XRFDC_CRSEDLY_UPDT_MODE_TILE 0x00000002U /**< Coarse delay event source selection is tile */
#define XRFDC_CRSEDLY_UPDT_MODE_SYSREF 0x00000003U /**< Coarse delay event source selection is sysref */
#define XRFDC_CRSEDLY_UPDT_MODE_MARKER 0x00000004U /**< Coarse delay event source selection is Marker */
#define XRFDC_CRSEDLY_UPDT_MODE_FABRIC 0x00000005U /**< Coarse delay event source selection is fabric */
#define XRFDC_CRSEDLY_UPDT_DLY_MASK 0x00001FF8U /**< delay in clk_dp cycles in application of event after arrival */
/* @} */
/** @name Coarse delay Config - Coarse delay select
*
* This register contains bits to select coarse delay.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_CRSE_DLY_CFG_MASK 0x00000007U /**< Coarse delay select */
#define XRFDC_CRSE_DLY_CFG_MASK_EXT 0x0000003FU /**< Extended coarse delay select*/
/* @} */
/** @name Data Scaling Config - Data Scaling enable
*
* This register contains bits to enable data scaling.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_DAT_SCALE_CFG_MASK 0x00000001U /**< Enable data scaling */
/* @} */
/** @name Data Scaling Config - Data Scaling enable
*
* This register contains bits to enable data scaling.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_DAT_SCALE_CFG_MASK 0x00000001U /**< Enable data scaling */
/* @} */
/** @name Switch Matrix Config
*
* This register contains bits to control crossbar switch that select
* data to mixer block. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_SWITCH_MTRX_MASK 0x0000003FU /**< Switch matrix mask */
#define XRFDC_SEL_CB_TO_MIX1_MASK 0x00000003U /**< Control crossbar switch that select the data to mixer block mux1 */
#define XRFDC_SEL_CB_TO_MIX0_MASK 0x0000000CU /**< Control crossbar switch that select the data to mixer block mux0 */
#define XRFDC_SEL_CB_TO_QMC_MASK 0x00000010U /**< Control crossbar switch that select the data to QMC */
#define XRFDC_SEL_CB_TO_DECI_MASK 0x00000020U /**< Control crossbar switch that select the data to decimation filter */
#define XRFDC_SEL_CB_TO_MIX0_SHIFT 2U /**< Crossbar Mixer0 shift */
/* @} */
/** @name Threshold0 Config
*
* This register contains bits to select mode, clear mode and to
* clear sticky bit. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TRSHD0_EN_MOD_MASK 0x00000003U /**< Enable Threshold0 block */
#define XRFDC_TRSHD0_CLR_MOD_MASK 0x00000004U /**< Clear mode */
#define XRFDC_TRSHD0_STIKY_CLR_MASK 0x00000008U /**< Clear sticky bit */
/* @} */
/** @name Threshold0 Average[31:16]
*
* This register contains bits to select Threshold0 under averaging.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TRSHD0_AVG_UPP_MASK 0x0000FFFFU /**< Threshold0 under Averaging[31:16] */
#define XRFDC_TRSHD0_AVG_UPP_SHIFT 16U /**< Threshold0 Avg upper shift */
/* @} */
/** @name Threshold0 Average[15:0]
*
* This register contains bits to select Threshold0 under averaging.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TRSHD0_AVG_LOW_MASK 0x0000FFFFU /**< Threshold0 under Averaging[15:0] */
/* @} */
/** @name Threshold0 Under threshold
*
* This register contains bits to select Threshold0 under threshold.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TRSHD0_UNDER_MASK 0x00007FFFU /**< Threshold0 under Threshold[14:0] */
/* @} */
/** @name Threshold0 Over threshold
*
* This register contains bits to select Threshold0 over threshold.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TRSHD0_OVER_MASK 0x00007FFFU /**< Threshold0 under Threshold[14:0] */
/* @} */
/** @name Threshold1 Config
*
* This register contains bits to select mode, clear mode and to
* clear sticky bit. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TRSHD1_EN_MOD_MASK 0x00000003U /**< Enable Threshold1 block */
#define XRFDC_TRSHD1_CLR_MOD_MASK 0x00000004U /**< Clear mode */
#define XRFDC_TRSHD1_STIKY_CLR_MASK 0x00000008U /**< Clear sticky bit */
/* @} */
/** @name Threshold1 Average[31:16]
*
* This register contains bits to select Threshold1 under averaging.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TRSHD1_AVG_UPP_MASK 0x0000FFFFU /**< Threshold1 under Averaging[31:16] */
#define XRFDC_TRSHD1_AVG_UPP_SHIFT 16U /**< Threshold1 Avg upper shift */
/* @} */
/** @name Threshold1 Average[15:0]
*
* This register contains bits to select Threshold1 under averaging.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TRSHD1_AVG_LOW_MASK 0x0000FFFFU /**< Threshold1 under Averaging[15:0] */
/* @} */
/** @name Threshold1 Under threshold
*
* This register contains bits to select Threshold1 under threshold.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TRSHD1_UNDER_MASK 0x00007FFFU /**< Threshold1 under Threshold[14:0] */
/* @} */
/** @name Threshold1 Over threshold
*
* This register contains bits to select Threshold1 over threshold.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TRSHD1_OVER_MASK 0x00007FFFU /**< Threshold1 under Threshold[14:0] */
/* @} */
/** @name FrontEnd Data Control
*
* This register contains bits to select raw data and cal coefficient to
* be streamed to memory. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_FEND_DAT_CTRL_MASK 0x000000FFU /**< raw data and cal coefficient to be streamed to memory */
/* @} */
/** @name TI Digital Correction Block control0
*
* This register contains bits for Time Interleaved digital correction
* block gain and offset correction. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_CTRL0_MASK 0x0000FFFFU /**< TI DCB gain and offset correction */
#define XRFDC_TI_DCB_MODE_MASK 0x00007800U /**< TI DCB Mode mask */
/* @} */
/** @name TI Digital Correction Block control1
*
* This register contains bits for Time Interleaved digital correction
* block gain and offset correction. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_CTRL1_MASK 0x00001FFFU /**< TI DCB gain and offset correction */
/* @} */
/** @name TI Digital Correction Block control2
*
* This register contains bits for Time Interleaved digital correction
* block gain and offset correction. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_CTRL2_MASK 0x00001FFFU /**< TI DCB gain and offset correction */
/* @} */
/** @name TI Time Skew control0
*
* This register contains bits for Time skew correction control bits0(enables,
* mode, multiplier factors, debug). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_TISK_EN_MASK 0x00000001U /**< Block Enable */
#define XRFDC_TI_TISK_MODE_MASK 0x00000002U /**< Mode (2G/4G) */
#define XRFDC_TI_TISK_ZONE_MASK 0x00000004U /**< Specifies Nyquist zone */
#define XRFDC_TI_TISK_CHOP_EN_MASK 0x00000008U /**< enable chopping mode */
#define XRFDC_TI_TISK_MU_CM_MASK 0x000000F0U /**< Constant mu_cm multiplying common mode path */
#define XRFDC_TI_TISK_MU_DF_MASK 0x00000F00U /**< Constant mu_df multiplying differential path */
#define XRFDC_TI_TISK_DBG_CTRL_MASK 0x0000F000U /**< Debug control */
#define XRFDC_TI_TISK_DBG_UPDT_RT_MASK 0x00001000U /**< Debug update rate */
#define XRFDC_TI_TISK_DITH_DLY_MASK 0x0000E000U /**< Programmable delay on dither path to match data path */
#define XRFDC_TISK_ZONE_SHIFT 2U /**< Nyquist zone shift */
/* @} */
/** @name DAC MC Config0
*
* This register contains bits for enable/disable shadow logic , Nyquist zone
* selection, enable full speed clock, Programmable delay.
* @{
*/
#define XRFDC_MC_CFG0_MIX_MODE_MASK 0x00000002U /**< Enable Mixing mode */
#define XRFDC_MC_CFG0_MIX_MODE_SHIFT 1U /**< Mix mode shift */
/* @} */
/** @name TI Time Skew control0
*
* This register contains bits for Time skew correction control bits0(enables,
* mode, multiplier factors, debug). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_EN_MASK 0x00000001U /**< Block Enable */
#define XRFDC_TISK_MODE_MASK 0x00000002U /**< Mode (2G/4G) */
#define XRFDC_TISK_ZONE_MASK 0x00000004U /**< Specifies Nyquist zone */
#define XRFDC_TISK_CHOP_EN_MASK 0x00000008U /**< enable chopping mode */
#define XRFDC_TISK_MU_CM_MASK 0x000000F0U /**< Constant mu_cm multiplying common mode path */
#define XRFDC_TISK_MU_DF_MASK 0x00000F00U /**< Constant mu_df multiplying differential path */
#define XRFDC_TISK_DBG_CTRL_MASK 0x0000F000U /**< Debug control */
#define XRFDC_TISK_DBG_UPDT_RT_MASK 0x00001000U /**< Debug update rate */
#define XRFDC_TISK_DITH_DLY_MASK 0x0000E000U /**< Programmable delay on dither path to match data path */
/* @} */
/** @name TI Time Skew control1
*
* This register contains bits for Time skew correction control bits1
* (Deadzone Parameters). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_DZ_MIN_VAL_MASK 0x000000FFU /**< Deadzone min */
#define XRFDC_TISK_DZ_MAX_VAL_MASK 0x0000FF00U /**< Deadzone max */
/* @} */
/** @name TI Time Skew control2
*
* This register contains bits for Time skew correction control bits2
* (Filter parameters). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_MU0_MASK 0x0000000FU /**< Filter0 multiplying factor */
#define XRFDC_TISK_BYPASS0_MASK 0x00000080U /**< ByPass filter0 */
#define XRFDC_TISK_MU1_MASK 0x00000F00U /**< Filter1 multiplying factor */
#define XRFDC_TISK_BYPASS1_MASK 0x00008000U /**< Filter1 multiplying factor */
/* @} */
/** @name TI Time Skew control3
*
* This register contains bits for Time skew control settling time
* following code update. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_SETTLE_MASK 0x000000FFU /**< Settling time following code update */
/* @} */
/** @name TI Time Skew control4
*
* This register contains bits for Time skew control setting time
* following code update. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_CAL_PRI_MASK 0x00000001U /**< */
#define XRFDC_TISK_DITH_INV_MASK 0x00000FF0U /**< */
/* @} */
/** @name TI Time Skew DAC0
*
* This register contains bits for Time skew DAC cal code of
* subadc ch0. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_DAC0_CODE_MASK 0x000000FFU /**< Code to correction DAC of subadc ch0 front end switch0 */
#define XRFDC_TISK_DAC0_OVRID_EN_MASK 0x00008000U /**< override enable */
/* @} */
/** @name TI Time Skew DAC1
*
* This register contains bits for Time skew DAC cal code of
* subadc ch1. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_DAC1_CODE_MASK 0x000000FFU /**< Code to correction DAC of subadc ch1 front end switch0 */
#define XRFDC_TISK_DAC1_OVRID_EN_MASK 0x00008000U /**< override enable */
/* @} */
/** @name TI Time Skew DAC2
*
* This register contains bits for Time skew DAC cal code of
* subadc ch2. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_DAC2_CODE_MASK 0x000000FFU /**< Code to correction DAC of subadc ch2 front end switch0 */
#define XRFDC_TISK_DAC2_OVRID_EN_MASK 0x00008000U /**< override enable */
/* @} */
/** @name TI Time Skew DAC3
*
* This register contains bits for Time skew DAC cal code of
* subadc ch3. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_DAC3_CODE_MASK 0x000000FFU /**< Code to correction DAC of subadc ch3 front end switch0 */
#define XRFDC_TISK_DAC3_OVRID_EN_MASK 0x00008000U /**< override enable */
/* @} */
/** @name TI Time Skew DACP0
*
* This register contains bits for Time skew DAC cal code of
* subadc ch0. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_DACP0_CODE_MASK 0x000000FFU /**< Code to correction DAC of subadc ch0 front end switch1 */
#define XRFDC_TISK_DACP0_OVRID_EN_MASK 0x00008000U /**< override enable */
/* @} */
/** @name TI Time Skew DACP1
*
* This register contains bits for Time skew DAC cal code of
* subadc ch1. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_DACP1_CODE_MASK 0x000000FFU /**< Code to correction DAC of subadc ch1 front end switch1 */
#define XRFDC_TISK_DACP1_OVRID_EN_MASK 0x00008000U /**< override enable */
/* @} */
/** @name TI Time Skew DACP2
*
* This register contains bits for Time skew DAC cal code of
* subadc ch2. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_DACP2_CODE_MASK 0x000000FFU /**< Code to correction DAC of subadc ch2 front end switch1 */
#define XRFDC_TISK_DACP2_OVRID_EN_MASK 0x00008000U /**< override enable */
/* @} */
/** @name TI Time Skew DACP3
*
* This register contains bits for Time skew DAC cal code of
* subadc ch3. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TISK_DACP3_CODE_MASK 0x000000FFU /**< Code to correction DAC of subadc ch3 front end switch1 */
#define XRFDC_TISK_DACP3_OVRID_EN_MASK 0x00008000U /**< override enable */
/* @} */
/** @name SubDRP ADC0 address
*
* This register contains the sub-drp address of the target register.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_SUBDRP_ADC0_ADDR_MASK 0x000000FFU /**< sub-drp0 address */
/* @} */
/** @name SubDRP ADC0 Data
*
* This register contains the sub-drp data of the target register.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_SUBDRP_ADC0_DAT_MASK 0x0000FFFFU /**< sub-drp0 data for read or write transaction */
/* @} */
/** @name SubDRP ADC1 address
*
* This register contains the sub-drp address of the target register.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_SUBDRP_ADC1_ADDR_MASK 0x000000FFU /**< sub-drp1 address */
/* @} */
/** @name SubDRP ADC1 Data
*
* This register contains the sub-drp data of the target register.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_SUBDRP_ADC1_DAT_MASK 0x0000FFFFU /**< sub-drp1 data for read or write transaction */
/* @} */
/** @name SubDRP ADC2 address
*
* This register contains the sub-drp address of the target register.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_SUBDRP_ADC2_ADDR_MASK 0x000000FFU /**< sub-drp2 address */
/* @} */
/** @name SubDRP ADC2 Data
*
* This register contains the sub-drp data of the target register.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_SUBDRP_ADC2_DAT_MASK 0x0000FFFFU /**< sub-drp2 data for read or write transaction */
/* @} */
/** @name SubDRP ADC3 address
*
* This register contains the sub-drp address of the target register.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_SUBDRP_ADC3_ADDR_MASK 0x000000FFU /**< sub-drp3 address */
/* @} */
/** @name SubDRP ADC3 Data
*
* This register contains the sub-drp data of the target register.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_SUBDRP_ADC3_DAT_MASK 0x0000FFFFU /**< sub-drp3 data for read or write transaction */
/* @} */
/** @name RX MC PWRDWN
*
* This register contains the static configuration bits of ADC(RX) analog.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_RX_MC_PWRDWN_MASK 0x0000FFFFU /**< RX MC power down */
/* @} */
/** @name RX MC Config0
*
* This register contains the static configuration bits of ADC(RX) analog.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_RX_MC_CFG0_MASK 0x0000FFFFU /**< RX MC config0 */
#define XRFDC_RX_MC_CFG0_CM_MASK 0x00000040U /**< Coupling mode mask */
#define XRFDC_RX_MC_CFG0_IM3_DITH_MASK 0x00000020U /**< IM3 Dither Enable mode mask */
#define XRFDC_RX_MC_CFG0_IM3_DITH_SHIFT 5U /**< IM3 Dither Enable mode shift */
/* @} */
/** @name RX MC Config1
*
* This register contains the static configuration bits of ADC(RX) analog.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_RX_MC_CFG1_MASK 0x0000FFFFU /**< RX MC Config1 */
/* @} */
/** @name RX MC Config2
*
* This register contains the static configuration bits of ADC(RX) analog.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_RX_MC_CFG2_MASK 0x0000FFFFU /**< RX MC Config2 */
/* @} */
/** @name RX Pair MC Config0
*
* This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static
* configuration bits of ADC(RX) analog. Read/Write apart from the
* reserved bits.
* @{
*/
#define XRFDC_RX_PR_MC_CFG0_MASK 0x0000FFFFU /**< RX Pair MC Config0 */
/* @} */
/** @name RX Pair MC Config1
*
* This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static
* configuration bits of ADC(RX) analog. Read/Write apart from the
* reserved bits.
* @{
*/
#define XRFDC_RX_PR_MC_CFG1_MASK 0x0000FFFFU /**< RX Pair MC Config1 */
/* @} */
/** @name TI DCB Status0 BG
*
* This register contains the subadc ch0 ocb1 BG offset correction factor
* value. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS0_BG_MASK 0x0000FFFFU /**< DCB Status0 BG */
/* @} */
/** @name TI DCB Status0 FG
*
* This register contains the subadc ch0 ocb2 FG offset correction factor
* value(read and write). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS0_FG_MASK 0x0000FFFFU /**< DCB Status0 FG */
/* @} */
/** @name TI DCB Status1 BG
*
* This register contains the subadc ch1 ocb1 BG offset correction factor
* value. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS1_BG_MASK 0x0000FFFFU /**< DCB Status1 BG */
/* @} */
/** @name TI DCB Status1 FG
*
* This register contains the subadc ch1 ocb2 FG offset correction factor
* value(read and write). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS1_FG_MASK 0x0000FFFFU /**< DCB Status1 FG */
/* @} */
/** @name TI DCB Status2 BG
*
* This register contains the subadc ch2 ocb1 BG offset correction factor
* value. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS2_BG_MASK 0x0000FFFFU /**< DCB Status2 BG */
/* @} */
/** @name TI DCB Status2 FG
*
* This register contains the subadc ch2 ocb2 FG offset correction factor
* value(read and write). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS2_FG_MASK 0x0000FFFFU /**< DCB Status2 FG */
/* @} */
/** @name TI DCB Status3 BG
*
* This register contains the subadc ch3 ocb1 BG offset correction factor
* value. Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS3_BG_MASK 0x0000FFFFU /**< DCB Status3 BG */
/* @} */
/** @name TI DCB Status3 FG
*
* This register contains the subadc ch3 ocb2 FG offset correction factor
* value(read and write). Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS3_FG_MASK 0x0000FFFFU /**< DCB Status3 FG */
/* @} */
/** @name TI DCB Status4 MSB
*
* This register contains the DCB status. Read/Write apart from the
* reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS4_MSB_MASK 0x0000FFFFU /**< read the status of gcb acc0 msb bits(subadc chan0) */
/* @} */
/** @name TI DCB Status4 LSB
*
* This register contains the DCB Status. Read/Write apart from the
* reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS4_LSB_MASK 0x0000FFFFU /**< read the status of gcb acc0 lsb bits(subadc chan0) */
/* @} */
/** @name TI DCB Status5 MSB
*
* This register contains the DCB status. Read/Write apart from the
* reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS5_MSB_MASK 0x0000FFFFU /**< read the status of gcb acc1 msb bits(subadc chan1) */
/* @} */
/** @name TI DCB Status5 LSB
*
* This register contains the DCB Status. Read/Write apart from the
* reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS5_LSB_MASK 0x0000FFFFU /**< read the status of gcb acc1 lsb bits(subadc chan1) */
/* @} */
/** @name TI DCB Status6 MSB
*
* This register contains the DCB status. Read/Write apart from the
* reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS6_MSB_MASK 0x0000FFFFU /**< read the status of gcb acc2 msb bits(subadc chan2) */
/* @} */
/** @name TI DCB Status6 LSB
*
* This register contains the DCB Status. Read/Write apart from the
* reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS6_LSB_MASK 0x0000FFFFU /**< read the status of gcb acc2 lsb bits(subadc chan2) */
/* @} */
/** @name TI DCB Status7 MSB
*
* This register contains the DCB status. Read/Write apart from the
* reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS7_MSB_MASK 0x0000FFFFU /**< read the status of gcb acc3 msb bits(subadc chan3) */
/* @} */
/** @name TI DCB Status7 LSB
*
* This register contains the DCB Status. Read/Write apart from the
* reserved bits.
* @{
*/
#define XRFDC_TI_DCB_STS7_LSB_MASK 0x0000FFFFU /**< read the status of gcb acc3 lsb bits(subadc chan3) */
/* @} */
/** @name PLL_REFDIV
*
* This register contains the bits for Reference Clock Divider
* @{
*/
#define XRFDC_REFCLK_DIV_MASK 0x1FU
#define XRFDC_REFCLK_DIV_1_MASK 0x10U /**< Mask for Div1 */
#define XRFDC_REFCLK_DIV_2_MASK 0x0U /**< Mask for Div2 */
#define XRFDC_REFCLK_DIV_3_MASK 0x1U /**< Mask for Div3 */
#define XRFDC_REFCLK_DIV_4_MASK 0x2U /**< Mask for Div4 */
/* @} */
/** @name FIFO Latency
*
* This register contains bits for result, key and done flag.
* Read/Write apart from the reserved bits.
* @{
*/
#define XRFDC_FIFO_LTNCY_RES_MASK 0x00000FFFU /**< Latency measurement result */
#define XRFDC_FIFO_LTNCY_KEY_MASK 0x00004000U /**< Latency measurement result identification key */
#define XRFDC_FIFO_LTNCY_DONE_MASK 0x00008000U /**< Latency measurement done flag */
/* @} */
/** @name Decoder Control
*
* This register contains Unary Decoder/Randomizer settings to use.
* @{
*/
#define XRFDC_DEC_CTRL_MODE_MASK 0x00000007U /**< Decoder mode */
/* @} */
/** @name HSCOM Power state mask
*
* This register contains HSCOM_PWR to check powerup_state.
* @{
*/
#define XRFDC_HSCOM_PWR_STATE_MASK 0x0000FFFFU /**< powerup state mask */
/* @} */
/** @name Interpolation Control
*
* This register contains Interpolation filter modes.
* @{
*/
#define XRFDC_INTERP_MODE_MASK 0x00000077U /**< Interp filter mask */
#define XRFDC_INTERP_MODE_I_MASK 0x00000007U /**< Interp filter I */
#define XRFDC_INTERP_MODE_Q_SHIFT 4U /**< Interp mode Q shift */
#define XRFDC_INTERP_MODE_MASK_EXT 0x00003F3FU /**< Interp filter mask */
#define XRFDC_INTERP_MODE_I_MASK_EXT 0x0000003FU /**< Interp filter I */
#define XRFDC_INTERP_MODE_Q_SHIFT_EXT 8U /**< Interp mode Q shift */
/* @} */
/** @name Tile enables register
*
* This register contains the bits that indicate
* whether or not a tile is enabled (Read Only).
* @{
*/
#define XRFDC_DAC_TILES_ENABLED_SHIFT 4U /**< Shift to the DAC tile bits */
/* @} */
/** @name Path enables register
*
* This register contains the bits that indicate
* whether or not an analogue/digital is enabled (Read Only).
* @{
*/
#define XRFDC_DIGITAL_PATH_ENABLED_SHIFT 16U /**< Shift to the digital path bits */
/* @} */
/** @name Tile Reset
*
* This register contains Tile reset bit.
* @{
*/
#define XRFDC_TILE_RESET_MASK 0x00000001U /**< Tile reset mask */
/* @} */
/** @name Status register
*
* This register contains common status bits.
* @{
*/
#define XRFDC_PWR_UP_STAT_MASK 0x00000004U /**< Power Up state mask */
#define XRFDC_PWR_UP_STAT_SHIFT 2U /**< PowerUp status shift */
#define XRFDC_PLL_LOCKED_MASK 0x00000008U /**< PLL Locked mask */
#define XRFDC_PLL_LOCKED_SHIFT 3U /**< PLL locked shift */
/* @} */
/** @name Restart State register
*
* This register contains Start and End state bits.
* @{
*/
#define XRFDC_PWR_STATE_MASK 0x0000FFFFU /**< State mask */
#define XRFDC_RSR_START_SHIFT 8U /**< Start state shift */
/* @} */
/** @name Clock Detect register
*
* This register contains Start and End state bits.
* @{
*/
#define XRFDC_CLOCK_DETECT_MASK 0x0000FFFFU /**< Clock detect mask */
/* @} */
/** @name Common interrupt enable register
*
* This register contains bits to enable interrupt for
* ADC and DAC tiles.
* @{
*/
#define XRFDC_EN_INTR_DAC_TILE0_MASK 0x00000001U /**< DAC Tile0 interrupt enable mask */
#define XRFDC_EN_INTR_DAC_TILE1_MASK 0x00000002U /**< DAC Tile1 interrupt enable mask */
#define XRFDC_EN_INTR_DAC_TILE2_MASK 0x00000004U /**< DAC Tile2 interrupt enable mask */
#define XRFDC_EN_INTR_DAC_TILE3_MASK 0x00000008U /**< DAC Tile3 interrupt enable mask */
#define XRFDC_EN_INTR_ADC_TILE0_MASK 0x00000010U /**< ADC Tile0 interrupt enable mask */
#define XRFDC_EN_INTR_ADC_TILE1_MASK 0x00000020U /**< ADC Tile1 interrupt enable mask */
#define XRFDC_EN_INTR_ADC_TILE2_MASK 0x00000040U /**< ADC Tile2 interrupt enable mask */
#define XRFDC_EN_INTR_ADC_TILE3_MASK 0x00000080U /**< ADC Tile3 interrupt enable mask */
/* @} */
/** @name interrupt enable register
*
* This register contains bits to enable interrupt for blocks.
* @{
*/
#define XRFDC_EN_INTR_SLICE_MASK 0x0000000FU /**< Slice intr mask */
#define XRFDC_EN_INTR_SLICE0_MASK 0x00000001U /**< slice0 interrupt enable mask */
#define XRFDC_EN_INTR_SLICE1_MASK 0x00000002U /**< slice1 interrupt enable mask */
#define XRFDC_EN_INTR_SLICE2_MASK 0x00000004U /**< slice2 interrupt enable mask */
#define XRFDC_EN_INTR_SLICE3_MASK 0x00000008U /**< slice3 interrupt enable mask */
#define XRFDC_INTR_COMMON_MASK 0x00000010U /**< Common interrupt enable mask */
/* @} */
/** @name Converter(X) interrupt register
*
* This register contains bits to enable different interrupts for block X.
* @{
*/
#define XRFDC_INTR_OVR_RANGE_MASK 0x00000008U /**< Over Range interrupt mask */
#define XRFDC_INTR_OVR_VOLTAGE_MASK 0x00000004U /**< Over Voltage interrupt mask */
#define XRFDC_INTR_FIFO_OVR_MASK 0x00008000U /**< FIFO OF mask */
#define XRFDC_INTR_DAT_OVR_MASK 0x00004000U /**< Data OF mask */
#define XRFDC_INTR_CMODE_OVR_MASK 0x00040000U /**< Common mode OV mask */
#define XRFDC_INTR_CMODE_UNDR_MASK 0x00080000U /**< Common mode UV mask */
/* @} */
/** @name Multiband config register
*
* This register contains bits to configure multiband.
* @{
*/
#define XRFDC_EN_MB_MASK 0x00000008U /**< multi-band adder mask */
#define XRFDC_EN_MB_SHIFT 3U /** <Enable Multiband shift */
#define XRFDC_ALT_BOND_MASK 0x0200 /** <Alt bondout mask */
#define XRFDC_ALT_BOND_SHIFT 9U /** <Alt bondout shift */
#define XRFDC_ALT_BOND_CLKDP_MASK 0x4U /** <Alt bondout shift */
#define XRFDC_ALT_BOND_CLKDP_SHIFT 2U /** <Alt bondout shift */
/* @} */
/** @name Invsinc control register
*
* This register contains bits to configure Invsinc.
* @{
*/
#define XRFDC_EN_INVSINC_MASK 0x00000001U /**< invsinc enable mask */
#define XRFDC_MODE_INVSINC_MASK 0x00000003U /**< invsinc mode mask */
/* @} */
/* @} */
/** @name Signal Detector control register
*
* This register contains bits to configure Signal Detector.
* @{
*/
#define XRFDC_ADC_SIG_DETECT_MASK 0xFF /**< signal detector mask */
#define XRFDC_ADC_SIG_DETECT_THRESH_MASK 0xFFFF /**< signal detector thresholds mask */
#define XRFDC_ADC_SIG_DETECT_THRESH_CNT_MASK 0xFFFF /**< signal detector thresholds counter mask */
#define XRFDC_ADC_SIG_DETECT_INTG_MASK 0x01 /**< leaky integrator enable mask */
#define XRFDC_ADC_SIG_DETECT_FLUSH_MASK 0x02 /**< leaky integrator flush mask */
#define XRFDC_ADC_SIG_DETECT_TCONST_MASK 0x1C /**< time constant mask */
#define XRFDC_ADC_SIG_DETECT_MODE_MASK 0x60 /**< mode mask */
#define XRFDC_ADC_SIG_DETECT_HYST_MASK 0x80 /**< hysteresis enable mask */
#define XRFDC_ADC_SIG_DETECT_INTG_SHIFT 0 /**< leaky integrator enable shift */
#define XRFDC_ADC_SIG_DETECT_FLUSH_SHIFT 1 /**< leaky integrator flush shift */
#define XRFDC_ADC_SIG_DETECT_TCONST_SHIFT 2 /**< time constant shift */
#define XRFDC_ADC_SIG_DETECT_MODE_WRITE_SHIFT 5 /**< mode shift fror writing */
#define XRFDC_ADC_SIG_DETECT_MODE_READ_SHIFT 6 /**< mode shift fror reading */
#define XRFDC_ADC_SIG_DETECT_HYST_SHIFT 7 /**< hysteresis enable shift */
/* @} */
/** @name CLK_DIV register
*
* This register contains the bits to control the clock
* divider providing the clock fabric out.
* @{
*/
#define XRFDC_FAB_CLK_DIV_MASK 0x0000000FU /**< clk div mask */
#define XRFDC_FAB_CLK_DIV_CAL_MASK 0x000000F0U /**< clk div cal mask */
/* @} */
/** @name Multiband Config
*
* This register contains bits to configure multiband for DAC.
* @{
*/
#define XRFDC_MB_CFG_MASK 0x000001FFU /**< MB config mask */
#define XRFDC_MB_EN_4X_MASK 0x00000100U /**< Enable 4X MB mask */
/* @} */
/** @name Multi Tile Sync
*
* Multi-Tile Sync bit masks.
* @{
*/
#define XRFDC_MTS_SRCAP_PLL_M 0x0100U
#define XRFDC_MTS_SRCAP_DIG_M 0x0100U
#define XRFDC_MTS_SRCAP_EN_TRX_M 0x0400U
#define XRFDC_MTS_SRCAP_INIT_M 0x8200U
#define XRFDC_MTS_SRCLR_T1_M 0x2000U
#define XRFDC_MTS_SRCLR_PLL_M 0x0200U
#define XRFDC_MTS_PLLEN_M 0x0001U
#define XRFDC_MTS_SRCOUNT_M 0x00FFU
#define XRFDC_MTS_DELAY_VAL_M 0x041FU
#define XRFDC_MTS_AMARK_CNT_M 0x00FFU
#define XRFDC_MTS_AMARK_LOC_M 0x0F0000U
#define XRFDC_MTS_AMARK_DONE_M 0x100000U
/* @} */
/** @name Output divider LSB register
*
* This register contains bits to configure output divisor
* @{
*/
#define XRFDC_PLL_DIVIDER0_MASK 0x00FFU
#define XRFDC_PLL_DIVIDER0_MODE_MASK 0x00C0U
#define XRFDC_PLL_DIVIDER0_BYP_OPDIV_MASK 0x0400U
#define XRFDC_PLL_DIVIDER0_BYP_PLL_MASK 0x0800U
#define XRFDC_PLL_DIVIDER0_VALUE_MASK 0x003FU
#define XRFDC_PLL_DIVIDER0_SHIFT 6U
/* @} */
/** @name Multi-tile sync and clock source control register
*
* This register contains bits to Multi-tile sync and clock source control
* @{
*/
#define XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK 0x1U /**< PLL clock mask */
#define XRFDC_CLK_NETWORK_CTRL1_USE_RX_MASK 0x2U /**< PLL clock mask */
#define XRFDC_CLK_NETWORK_CTRL1_REGS_MASK 0x3U /**< PLL clock mask */
/* @} */
/** @name PLL_CRS1 - PLL CRS1 register
*
* This register contains bits for VCO sel_auto, VCO band selection etc.,
* @{
*/
#define XRFDC_PLL_CRS1_VCO_SEL_MASK 0x00008001U /**< VCO SEL Mask */
#define XRFDC_PLL_VCO_SEL_AUTO_MASK 0x00008000U /**< VCO Auto SEL Mask */
/* @} */
/** Register bits Shift, Width Masks
*
* @{
*/
#define XRFDC_DIGI_ANALOG_SHIFT4 4U
#define XRFDC_DIGI_ANALOG_SHIFT8 8U
#define XRFDC_DIGI_ANALOG_SHIFT12 12U
/* @} */
/** @name FIFO Delays
*
* This register contains bits for delaying the FIFOs.,
* @{
*/
#define XRFDC_DAC_FIFO_DELAY_MASK 0x000000FFFU /**< DAC FIFO ReadPtr Delay */
#define XRFDC_ADC_FIFO_DELAY_MASK 0x0000001C0U /**< ADC FIFO ReadPtr Delay */
#define XRFDC_ADC_FIFO_DELAY_SHIFT 6U /**< ADC FIFO ReadPtr Shift */
/* @} */
#define XRFDC_IXR_FIFOUSRDAT_MASK 0x0000000FU
#define XRFDC_IXR_FIFOUSRDAT_OF_MASK 0x00000001U
#define XRFDC_IXR_FIFOUSRDAT_UF_MASK 0x00000002U
#define XRFDC_IXR_FIFOMRGNIND_OF_MASK 0x00000004U
#define XRFDC_IXR_FIFOMRGNIND_UF_MASK 0x00000008U
#define XRFDC_ADC_IXR_DATAPATH_MASK 0x00000FF0U
#define XRFDC_ADC_IXR_DMON_STG_MASK 0x000003F0U
#define XRFDC_DAC_IXR_DATAPATH_MASK 0x00001FF0U
#define XRFDC_DAC_IXR_INTP_STG_MASK 0x000003F0U
#define XRFDC_DAC_IXR_INTP_I_STG0_MASK 0x00000010U
#define XRFDC_DAC_IXR_INTP_I_STG1_MASK 0x00000020U
#define XRFDC_DAC_IXR_INTP_I_STG2_MASK 0x00000040U
#define XRFDC_DAC_IXR_INTP_Q_STG0_MASK 0x00000080U
#define XRFDC_DAC_IXR_INTP_Q_STG1_MASK 0x00000100U
#define XRFDC_DAC_IXR_INTP_Q_STG2_MASK 0x00000200U
#define XRFDC_ADC_IXR_DMON_I_STG0_MASK 0x00000010U
#define XRFDC_ADC_IXR_DMON_I_STG1_MASK 0x00000020U
#define XRFDC_ADC_IXR_DMON_I_STG2_MASK 0x00000040U
#define XRFDC_ADC_IXR_DMON_Q_STG0_MASK 0x00000080U
#define XRFDC_ADC_IXR_DMON_Q_STG1_MASK 0x00000100U
#define XRFDC_ADC_IXR_DMON_Q_STG2_MASK 0x00000200U
#define XRFDC_IXR_QMC_GAIN_PHASE_MASK 0x00000400U
#define XRFDC_IXR_QMC_OFFST_MASK 0x00000800U
#define XRFDC_DAC_IXR_INVSNC_OF_MASK 0x00001000U
#define XRFDC_SUBADC_IXR_DCDR_MASK 0x00FF0000U
#define XRFDC_SUBADC0_IXR_DCDR_OF_MASK 0x00010000U
#define XRFDC_SUBADC0_IXR_DCDR_UF_MASK 0x00020000U
#define XRFDC_SUBADC1_IXR_DCDR_OF_MASK 0x00040000U
#define XRFDC_SUBADC1_IXR_DCDR_UF_MASK 0x00080000U
#define XRFDC_SUBADC2_IXR_DCDR_OF_MASK 0x00100000U
#define XRFDC_SUBADC2_IXR_DCDR_UF_MASK 0x00200000U
#define XRFDC_SUBADC3_IXR_DCDR_OF_MASK 0x00400000U
#define XRFDC_SUBADC3_IXR_DCDR_UF_MASK 0x00800000U
#define XRFDC_ADC_OVR_VOLTAGE_MASK 0x04000000U
#define XRFDC_COMMON_MASK 0x01000000U
#define XRFDC_ADC_OVR_RANGE_MASK 0x08000000U
#define XRFDC_ADC_CMODE_OVR_MASK 0x10000000U
#define XRFDC_ADC_CMODE_UNDR_MASK 0x20000000U
#define XRFDC_ADC_DAT_OVR_MASK 0x40000000U
#define XRFDC_ADC_FIFO_OVR_MASK 0x80000000U
#define XRFDC_DAC_MC_CFG2_OPCSCAS_MASK 0x0000F8F8U
#define XRFDC_DAC_MC_CFG3_CSGAIN_MASK 0x0000FFC0U
#define XRFDC_DAC_MC_CFG2_OPCSCAS_20MA 0x00004858U
#define XRFDC_DAC_MC_CFG3_CSGAIN_20MA 0x000087C0U
#define XRFDC_DAC_MC_CFG2_OPCSCAS_32MA 0x0000A0D8U
#define XRFDC_DAC_MC_CFG3_CSGAIN_32MA 0x0000FFC0U
#define XRFDC_DAC_MC_CFG2_GEN1_COMP_MASK 0x0020U
#define XRFDC_DAC_MC_CFG3_OPT_LUT_MASK 0x03E0U
#define XRFDC_DAC_MC_CFG3_OPT_MASK 0x001FU
#define XRFDC_DAC_MC_CFG3_UPDATE_MASK 0x0020U
#define XRFDC_DAC_MC_CFG0_CAS_BLDR_MASK 0xE000U
#define XRFDC_DAC_MC_CFG2_CAS_BIAS_MASK 0x001FU
#define XRFDC_ADC_DSA_RTS_PIN_MASK 0x0020U
#define XRFDC_ADC_DSA_CODE_MASK 0x001FU
#define XRFDC_ADC_DSA_UPDT_MASK 0x0001U
#define XRFDC_DAC_MC_CFG3_CSGAIN_SHIFT 6U
#define XRFDC_DAC_MC_CFG3_OPT_LUT_SHIFT 5U
#define XRFDC_ADC_OVR_VOL_RANGE_SHIFT 24U
#define XRFDC_ADC_DAT_FIFO_OVR_SHIFT 16U
#define XRFDC_ADC_SUBADC_DCDR_SHIFT 16U
#define XRFDC_DATA_PATH_SHIFT 4U
#define XRFDC_ADC_CMODE_SHIFT 10U
#define XRFDC_COMMON_SHIFT 20U
#define XRFDC_DAC_MC_CFG2_GEN1_COMP_SHIFT 5U
#define XRFDC_ADC_DSA_RTS_PIN_SHIFT 5U
#define XRFDC_DAC_TILE_DRP_ADDR(X) (0x6000U + (X * 0x4000U))
#define XRFDC_DAC_TILE_CTRL_STATS_ADDR(X) (0x4000U + (X * 0x4000U))
#define XRFDC_ADC_TILE_DRP_ADDR(X) (0x16000U + (X * 0x4000U))
#define XRFDC_ADC_TILE_CTRL_STATS_ADDR(X) (0x14000U + (X * 0x4000U))
#define XRFDC_CTRL_STATS_OFFSET 0x0U
#define XRFDC_HSCOM_ADDR 0x1C00U
#define XRFDC_BLOCK_ADDR_OFFSET(X) (X * 0x400U)
#define XRFDC_TILE_DRP_OFFSET 0x2000U
/***************** Macros (Inline Functions) Definitions *********************/
#define XRFdc_In64 metal_io_read64
#define XRFdc_Out64 metal_io_write64
#define XRFdc_In32 metal_io_read32
#define XRFdc_Out32 metal_io_write32
#define XRFdc_In16 metal_io_read16
#define XRFdc_Out16 metal_io_write16
#define XRFdc_In8 metal_io_read8
#define XRFdc_Out8 metal_io_write8
/****************************************************************************/
/**
* Read a register.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XRFdc_ReadReg64(XRFdc *InstancePtr. u32 BaseAddress, s32 RegOffset)
*
******************************************************************************/
#define XRFdc_ReadReg64(InstancePtr, BaseAddress, RegOffset) \
XRFdc_In64(InstancePtr->io, ((u32)RegOffset + (u32)BaseAddress))
/***************************************************************************/
/**
* Write to a register.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @note None.
*
* @note C-Style signature:
* void XRFdc_WriteReg64(XRFdc *InstancePtr, u32 BaseAddress, s32 RegOffset,
* u64 RegisterValue)
*
******************************************************************************/
#define XRFdc_WriteReg64(InstancePtr, BaseAddress, RegOffset, RegisterValue) \
XRFdc_Out64((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))
/****************************************************************************/
/**
* Read a register.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XRFdc_ReadReg(XRFdc *InstancePtr, u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XRFdc_ReadReg(InstancePtr, BaseAddress, RegOffset) \
XRFdc_In32((InstancePtr->io), ((u32)BaseAddress + (u32)RegOffset))
/***************************************************************************/
/**
* Write to a register.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @note None.
*
* @note C-Style signature:
* void XRFdc_WriteReg(XRFdc *InstancePtr, u32 BaseAddress, int RegOffset,
* u32 RegisterValue)
*
******************************************************************************/
#define XRFdc_WriteReg(InstancePtr, BaseAddress, RegOffset, RegisterValue) \
XRFdc_Out32((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))
/****************************************************************************/
/**
* Read a register.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u16 XRFdc_ReadReg16(XRFdc *InstancePtr, u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XRFdc_ReadReg16(InstancePtr, BaseAddress, RegOffset) \
XRFdc_In16((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress))
/***************************************************************************/
/**
* Write to a register.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @note None.
*
* @note C-Style signature:
* void XRFdc_WriteReg16(XRFdc *InstancePtr, u32 BaseAddress, int RegOffset,
* u16 RegisterValue)
*
******************************************************************************/
#define XRFdc_WriteReg16(InstancePtr, BaseAddress, RegOffset, RegisterValue) \
XRFdc_Out16((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))
/****************************************************************************/
/**
* Read a register.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u8 XRFdc_ReadReg8(XRFdc *InstancePtr, u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XRFdc_ReadReg8(InstancePtr, BaseAddress, RegOffset) \
XRFdc_In8((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress))
/***************************************************************************/
/**
* Write to a register.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @note None.
*
* @note C-Style signature:
* void XRFdc_WriteReg8(XRFdc *InstancePtr, u32 BaseAddress, int RegOffset,
* u8 RegisterValue)
*
******************************************************************************/
#define XRFdc_WriteReg8(InstancePtr, BaseAddress, RegOffset, RegisterValue) \
XRFdc_Out8((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))
#ifdef __cplusplus
}
#endif
#endif /* RFDC_HW_H_ */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_rpucore.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_RPUCORE_H_
#define XPM_RPUCORE_H_
#include "xpm_core.h"
#ifdef __cplusplus
extern "C" {
#endif
#define XPM_PROC_RPU_HIVEC_ADDR 0xFFFC0000U
#define XPM_RPU_NCPUHALT_MASK BIT(0)
#define XPM_RPU_VINITHI_MASK BIT(2)
#define XPM_RPU_SLSPLIT_MASK BIT(3)
#define XPM_RPU_TCM_COMB_MASK BIT(6)
#define XPM_RPU_SLCLAMP_MASK BIT(4)
#define XPM_RPU0_0_PWR_CTRL_MASK BIT(4)
#define XPM_RPU0_1_PWR_CTRL_MASK BIT(5)
#define XPM_RPU_0_CPUPWRDWNREQ_MASK BIT(0)
#define XPM_RPU_1_CPUPWRDWNREQ_MASK BIT(0)
typedef struct XPm_RpuCore XPm_RpuCore;
/**
* The RPU core class.
*/
struct XPm_RpuCore {
XPm_Core Core; /**< Processor core devices */
u32 ResumeCfg;
u32 RpuBaseAddr; /**< Base address of RPU module */
};
/************************** Function Prototypes ******************************/
XStatus XPmRpuCore_Init(XPm_RpuCore *RpuCore, u32 Id, u32 Ipi, u32 *BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock,
XPm_ResetNode *Reset);
void XPm_RpuGetOperMode(const u32 DeviceId, u32 *Mode);
void XPm_RpuSetOperMode(const u32 DeviceId, const u32 Mode);
XStatus XPm_RpuBootAddrConfig(const u32 DeviceId, const u32 BootAddr);
XStatus XPm_RpuTcmCombConfig(const u32 DeviceId, const u32 Config);
XStatus XPmRpuCore_Halt(XPm_Device *Device);
XStatus XPm_RpuRstComparators(const u32 DeviceId);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_RPUCORE_H_ */
<file_sep>/python_drivers/tdc_wrapper.py
# -*- coding: utf-8 -*-
"""
Created on Wed Jul 1 15:59:25 2020
@author: tianlab01
"""
import time
import socket
import QuTAG
# import thread module
from _thread import *
import threading
import james_utils
tdc_err_logfile = "tdc_error_log.txt"
TIMEOUT_LONG = 15#For waiting on TDC to finish
#Use secore mode?
SECURE_MODE = 0
#Print each pulse received?
PRINT_PULSES = 0
#Socket timeout in seconds
SERVER_TIMEOUT = 2
SERVER_ACK = b'\x66'
BYTES_PER_TIMESTAMP = 20
#Mode for this instance
MODE_NORMAL = 0
MODE_CLIENT = 1
MODE_SERVER = 2
#Commands the server will process
COMMAND_PING = 0 #Chekcs server connection
COMMAND_GET_AND_CLEAR = 1 #Gets the latest timestamp for this channel and clears it from the list
COMMAND_SHUTDOWN = 2 #Stops server
COMMAND_CLOSE_CONNECTION = 3 #Closes connection between server and client
COMMAND_CLEAR_ALL = 4 #Clears all recorded timestamps
COMMAND_GET_BUSY = 5 #Checks if the server is busy offloading timestamps from TDC
COMMAND_DUMP_ALL = 6 #Returns all timestamps from a given channel
COMMAND_RECORD_PULSES = 7 #Starts recording pulses received by the TDC
COMMAND_STOP_RECORD = 8 #Stops recording pulses received by the TDC
COMMAND_GET_NUM_PULSES = 9 #Gets the number of pulses the TDC server has recorded
#channel number for the 1ms pulse
DUMMY_CHANNEL_NUM = 104
#Socket error codes
SOCKET_TIMEOUT = -1
SOCKET_DEAD = -2
SOCKET_WAIT_TIME = 0.000000000001 #Should be super sort just to give socket enough time to start working
#Record object for getting pulses out of the TDC
class pulse_record:
channel_num = 0
timestamp = 0
def __init__(self, cn, ts):
self.channel_num = cn
self.timestamp = ts
class tdc_wrapper:
timeout = 5 #in seconds
device = 0
dummy_mode = 0#If true, timestamp returned will be unix time * 1e7
mode = 0
server_ip = ""
timestamp_list = [] # list of timestamps recorded by this instance in server mode
shutdown_flag = 0
record_offset = 0
#used to effectively "reset" internal TDC counter
offset_timestamp = 0
#List of currently running threads
threads = []
port = 25567
busy = 0#1 if tdc is offloading pulses
record_pulses = 0
def __init__(self, tt, dm, m = MODE_NORMAL, s_ip = ""):
self.timeout = tt
self.dummy_mode = dm
self.mode = m
self.server_ip = s_ip
self.record_offset = 1#Record the offset first
if((not self.dummy_mode) and (self.mode == MODE_NORMAL or self.mode == MODE_SERVER)):
if(self.check_tdc_clock()):
print("External TDC clock detected!")
else:
print("Warning, TDC did not detect an external clock, results will not be accurate!")
if(self.mode == MODE_SERVER):
print("Starting TDC wrapper in SERVER mode")
self.server_init()
elif(self.mode == MODE_NORMAL):
#Start a new thread for the TDC service routine so we act like the server
t = threading.Thread(target=self.service_tdc, args=(1,))
t.start()
self.threads.append(t)
time.sleep(2)#Give the thread a moment to start
return
def __del__(self):
self.shutdown()
#Shuts down the TDC worker threads
def shutdown(self):
#Shutdown the worker thread if we're in normal mode
if(self.mode == MODE_NORMAL):
self.shutdown_flag = 1
if(len(self.threads)):
while(self.threads[0].is_alive()):
print("Waiting for TDC thread to shutdown")
time.sleep(1)
else:
print("Warning, could not shut down TDC worker thread")
print("TDC shutdown complete")
############################################################################
#############The following functions may only be called by a client or in normal mode
#Checks if an external clock is connected to the TDC
#Returns 1 if locked
def check_tdc_clock(self):
self.device = QuTAG.QuTAG()
ret_val = self.device.getClockState()
self.device.deInitialize()
self.device = 0
return ret_val
#Initializes the TDC device and sets the channel thresholds
def init_device(self):
#Open the TDC and start receiveing pulses
self.device = QuTAG.QuTAG()
self.device.enableChannels(james_utils.TDC_CHANNEL_LIST)
thresh = james_utils.TDC_THRESHOLD
self.device.setSignalConditioning(1, 3, 1, thresh)
self.device.setSignalConditioning(2, 3, 1, thresh)
self.device.setSignalConditioning(3, 3, 1, thresh)
self.device.setSignalConditioning(4, 3, 1, thresh)
return
#Used by TDC clients to check if the TDC is busy offloading pulses
def is_busy(self):
if(self.mode == MODE_NORMAL):
return self.busy
sck = socket.socket()
sck.settimeout(TIMEOUT_LONG)
sck.connect((self.server_ip, self.port))
time.sleep(SOCKET_WAIT_TIME)
#Send the GET_AND_CLEAR command
sck.send(bytearray([COMMAND_GET_BUSY]))
res = james_utils.receive_timestamp(sck)
#gracefully close the connection
sck.send(bytearray([COMMAND_CLOSE_CONNECTION]))
sck.close()
return res
#Returns the timestamp of the first pulse seen on channel_num
#Returns 0 on timeout
def wait_pulse(self, channel_num):
if(self.dummy_mode):
return int(time.time() * 10000000)
if(self.mode != MODE_NORMAL):
#If we're the client
if(self.mode == MODE_CLIENT):
return self.wait_pulse_client(channel_num)
else:
print("Error, cannot call wait_pulse in server mode!")
return -1
#if(self.device):
# print("Error, cannot call wait_pulse while recording, exiting")
# return -1
#Open the TDC and start receiveing pulses
#self.init_device()
time_now = time.time()
#ret_val = 0
#While we're not out of time
while((time.time() - time_now) < self.timeout):
for r in self.timestamp_list:
if(r.channel_num == channel_num):
return r.timestamp
#Check the data loss
#d_loss = self.device.getDataLost()
#if(d_loss != 0):
# print("Warning, data loss was " + str(d_loss) + ", some timestamps have been missed")
#Readback timestamps from the device
#t_s = self.device.ttTimestamps(True)
#If we didnt get any timestamps
#if(t_s[2] == 0):
# continue#keep going
#for i in range(0, t_s[2]):
#If we find a timestamp of this channel
# if(t_s[1][i] == channel_num):
# ret_val = t_s[0][i]
# break
#Close the TDC
#self.device.deInitialize()
#self.device = 0
#Fail if we didn't find it
return 0
#depreciated, do not use
def start_record(self):
#if(self.mode != MODE_NORMAL):
# return 0
#if(self.dummy_mode):
# return 0
#if(self.device):
# print("Error, cannot call this function while TDC is active!")
# return -1
##Don't do anything, device is being handled in its own thread
#Open the TDC and start receiveing pulses
#self.init_device()
return 0
#Returns timestamp from that channel\
#0 on fail for get all = 0, [] on fail for get_all = 1
def end_record(self, channel_num, get_all = 0):
#Testing
#return [1,2,3,4,5,6,7,8,9,10]
if(self.dummy_mode):
return int(time.time() * 10000000)
if(self.mode != MODE_NORMAL):
if(self.mode == MODE_CLIENT):
return self.end_record_client(channel_num, get_all)
else:
print("Error, end_record must be called in NORMAL mode")
return -1
ret_val = 0
#Check the data loss
#d_loss = self.device.getDataLost()
#if(d_loss != 0):
# print("Warning, data loss was " + str(d_loss) + ", some timestamps have been missed")
#Readback timestamps from the device
#t_s = self.device.getLastTimestamps(True)
#If we didnt get any timestamps
if(len(self.timestamp_list) == 0):
print("No timestamp recieved after record!")
if(get_all):
ret_val = []
else:
ret_val = 0
else:
if(get_all):
ret_val = []
done = 0
while(not done and len(self.timestamp_list) != 0):
#If we find a timestamp of this channel
for i in range(0, len(self.timestamp_list)):#Loop throught all timestamps
if(self.timestamp_list[i].channel_num == channel_num):#If we find one
ret_val.append(self.timestamp_list[i].timestamp)#Append it to our list
self.timestamp_list.remove(self.timestamp_list[i])#Remove it from the master list
break#Go around again and find more timestamps
if(i >= len(self.timestamp_list) - 1):
done = 1
else:
for i in range(0, len(self.timestamp_list)):#Look throigh all of the stuff
if(self.timestamp_list[i].channel_num == channel_num):
ret_val = self.timestamp_list[i].timestamp
self.timestamp_list.remove(self.timestamp_list[i])
#Close the TDC
#self.device.deInitialize()
#self.device = 0
return ret_val
################################################################################
#Polls the TDC until a pulse is received for a given channel number
def wait_pulse_client(self, channel_num):
sck = socket.socket()
sck.settimeout(TIMEOUT_LONG)
sck.connect((self.server_ip, self.port))
time.sleep(SOCKET_WAIT_TIME)
time_now = time.time()
ret_val = 0
while(time.time() - time_now < self.timeout):
#Keep trying to get that timestamp
channel_byte = channel_num & 0xff
#Send the GET_AND_CLEAR command
sck.send(bytearray([COMMAND_GET_AND_CLEAR, channel_byte]))
ret_val = james_utils.receive_timestamp(sck)
if(ret_val):
break
#gracefully close the connection
sck.send(bytearray([COMMAND_CLOSE_CONNECTION]))
sck.close()
return ret_val
#Gets last or all timestamps for a given channel number
def end_record_client(self, channel_num, get_all):
if(get_all):
return self.dump_all(channel_num)
sck = socket.socket()
sck.settimeout(TIMEOUT_LONG)
sck.connect((self.server_ip, self.port))
time.sleep(SOCKET_WAIT_TIME)
channel_byte = channel_num & 0xff
#Send the GET_AND_CLEAR command
#If we want to get all timestamps for this channel
#if(get_all):
# val_last = 1
# ret_val = []
# #Loop until we receive a timestamp of 0
# while(val_last > 0):
# sck.send(bytearray([COMMAND_GET_AND_CLEAR, channel_byte]))
# val_last = james_utils.receive_timestamp(sck)
# if(val_last > 0):
# ret_val.append(val_last)
#
#else:
#Otherwise just get the first timestamp and leave
sck.send(bytearray([COMMAND_GET_AND_CLEAR, channel_byte]))
ret_val = james_utils.receive_timestamp(sck)
#gracefully close the connection
sck.send(bytearray([COMMAND_CLOSE_CONNECTION]))
sck.close()
return ret_val
#Starts or stops timestamp recording
#choice = 0 will stop recording
def set_record(self, choice):
if(self.mode == MODE_NORMAL):
self.record_pulses = choice
return
sck = socket.socket()
sck.settimeout(TIMEOUT_LONG)
sck.connect((self.server_ip, self.port))
time.sleep(SOCKET_WAIT_TIME)
if(choice):
sck.send(bytearray([COMMAND_RECORD_PULSES]))
else:
sck.send(bytearray([COMMAND_STOP_RECORD]))
ret_val = james_utils.receive_timestamp(sck)
#gracefully close the connection
sck.send(bytearray([COMMAND_CLOSE_CONNECTION]))
sck.close()
return ret_val
def get_num_pulses(self):
sck = socket.socket()
sck.settimeout(TIMEOUT_LONG)
sck.connect((self.server_ip, self.port))
time.sleep(SOCKET_WAIT_TIME)
sck.send(bytearray([COMMAND_GET_NUM_PULSES]))
ret_val = james_utils.receive_timestamp(sck)
#gracefully close the connection
sck.send(bytearray([COMMAND_CLOSE_CONNECTION]))
sck.close()
return ret_val
#Clears all timestamps recorded by the TDC
def clear_all(self):
print("Clearing tdc")
if(self.mode == MODE_NORMAL):
self.timestamp_list = []
else:
sck = socket.socket()
sck.settimeout(TIMEOUT_LONG)
sck.connect((self.server_ip, self.port))
time.sleep(SOCKET_WAIT_TIME)
#Send the GET_AND_CLEAR command
sck.send(bytearray([COMMAND_CLEAR_ALL]))
res = james_utils.receive_bytes(sck,1)
if(isinstance(res, int)):
print("Error waiting for confirmation of clear from server:"+str(res))
elif(res[0] != 0x66):
print("Bad timeout received from server while clearing tdc")
#gracefully close the connection
sck.send(bytearray([COMMAND_CLOSE_CONNECTION]))
#sck.flush()
sck.close()
return 0
#Gets all recorded timestamps for a particular channel from the TDC
def dump_all(self, channel_num):
if(self.mode != MODE_CLIENT):
print("Error, must be in CLIENT mode to call dump all")
return []
sck = socket.socket()
sck.settimeout(TIMEOUT_LONG)
sck.connect((self.server_ip, self.port))
time.sleep(SOCKET_WAIT_TIME)
channel_byte = channel_num & 0xFF
#Send the GET_AND_CLEAR command
sck.send(bytearray([COMMAND_DUMP_ALL, channel_byte]))
#Receive the size
stream_size = james_utils.receive_timestamp(sck)
print("Stream size was " + str(stream_size))
byte_result = james_utils.receive_bytes(sck, stream_size)
timestamp_list = james_utils.bytes_to_timestamps(byte_result)
#gracefully close the connection
sck.send(bytearray([COMMAND_CLOSE_CONNECTION]))
#sck.flush()
sck.close()
return timestamp_list
#Initializes the server and dispatches client and TDC service threads
def server_init(self):
print("Initializing TDC in SERVER mode")
#Start a new thread for the TDC service routine
t = threading.Thread(target=self.service_tdc, args=(1,))
t.start()
self.threads.append(t)
#Start the user shutdown handlong thread
t = threading.Thread(target=self.user_quit, args=(1,))
t.start()
self.threads.append(t)
sck = socket.socket()
sck.settimeout(SERVER_TIMEOUT)
#Bind the socket and listen for a connection
host = socket.gethostname() # Get local machine name
sck.bind((host, self.port))
sck.listen(5)
#Start listening for and dispatching client connections
while(not self.shutdown_flag):
#Check for dead threads
for t in self.threads:
if(not t.is_alive()):
print("Dropping dead thread #" + str(t.ident))
self.threads.remove(t)
try:
#Once a client connects we'll be here
c, addr = sck.accept() # Establish connection with client.
name_str = str(addr[0]) + ":" + str(addr[1])
print("Got a connection from " + name_str)
#if(SECURE_MODE):
#c_s = ssl.wrap_socket(c,
# server_side=True,
# certfile=pem_path,
# keyfile=key_path,
# ssl_version=ssl.PROTOCOL_TLS)
#else:
c_s = c
c_s.settimeout(SERVER_TIMEOUT)
#Start a new thread to handle the client
#Also append the thread handle to our list of threads
#self.threads.append(start_new_thread(self.handle_client, (c_s,addr[0] + ":" + addr[1],)))
t = threading.Thread(target=self.handle_client, args=(c_s,name_str,))
t.start()
print("Starting client thread #" + str(t.ident))
self.threads.append(t)
except socket.timeout:
#print("Waiting for client connection...")
aaaa = 1
except:
print("Unknown error while waiting for client connection")
raise
print("Waiting for threads to terminate before shutting down server")
while(len(self.threads) > 0):
for t in self.threads:
t.join(0.1)
#If the thread has shut down
if(not t.is_alive()):
print("Stopped thread #" + str(t.ident))
self.threads.remove(t)
print("Shutting down server")
sck.close()
return
#Allows the TDC server to be stopped gracefully from console
def user_quit(self, arg1):
res = input()
print("[USER] Local user has stopped server")
self.shutdown_flag = 1
return
#This function is called in its own thread to constantly offload data from the tdc
def service_tdc(self, arg1):
print("[TDC SERVICE] Thread has started")
#Start the TDC
self.init_device()
while(not self.shutdown_flag):
#Check the data loss
d_loss = self.device.getDataLost()
if(d_loss != 0):
print("[TDC SERVICE] Warning, data loss was " + str(d_loss) + ", some timestamps have been missed")
file = open(tdc_err_logfile,'a')
new_line = "TDC experienced data loss"
file.write(new_line + "\n")
file.close()
#Readback timestamps from the device
t_s = self.device.getLastTimestamps(True)
#If we didnt get any timestamps
if(t_s[2] == 0):
self.busy = 0
continue#keep going
for i in range(0, t_s[2]):
#If we need to record an offset timestamp
if(self.record_offset and t_s[1][i] == DUMMY_CHANNEL_NUM):
self.record_offset = 0
self.offset_timestamp = t_s[0][i]
print("[TDC SERVICE] Recorded TDC offset as " + str(self.offset_timestamp))
#self.offset_timestamp = 0
#If we find a timestamp that isn't the dummy channel
elif(t_s[1][i] != DUMMY_CHANNEL_NUM and self.record_pulses == 1):
#elif(t_s[1][i] != DUMMY_CHANNEL_NUM):
self.busy = 1
self.timestamp_list.append(pulse_record(t_s[1][i], t_s[0][i] - self.offset_timestamp))
if(PRINT_PULSES):
print("[TDC SERVICE] Got pulse on channel #" + str(t_s[1][i]) + ", absolute = " + str(t_s[0][i]) + ", relative = " + str(t_s[0][i] - self.offset_timestamp))
#If we're here then the server shutdown command has been sent
self.device.deInitialize()
self.device = 0
return
#This function handles a client connected at socket C
def handle_client(self, c, ip_str):
time.sleep(SOCKET_WAIT_TIME)
while(not self.shutdown_flag):
#Receive one command byte from the client
client_cmd = james_utils.receive_bytes(c, 1)
if(client_cmd == SOCKET_TIMEOUT):
print("[CLIENT HANDLER] Timed out waiting for client command from " + ip_str)
elif(client_cmd == SOCKET_DEAD or client_cmd == -3):
print("[CLIENT HANDLER] Dead socket, dropping client at " + ip_str)
break
elif(client_cmd[0] == COMMAND_PING):
print("[CLIENT HANDLER] Client at " + ip_str + ": COMMAND_PING")
c.send(SERVER_ACK)
elif(client_cmd[0] == COMMAND_CLOSE_CONNECTION):
print("[CLIENT HANDLER] Client at " + ip_str + ": COMMAND_CLOSE_CONNECTION")
break
elif(client_cmd[0] == COMMAND_CLEAR_ALL):
print("[CLIENT HANDLER] Client at " + ip_str + ": COMMAND_CLEAR_ALL")
self.timestamp_list = []
c.send(SERVER_ACK)
elif(client_cmd[0] == COMMAND_GET_BUSY):
print("[CLIENT HANDLER] Client at " + ip_str + ": COMMAND_GET_BUSY")
james_utils.send_timestamp(c, self.busy)
elif(client_cmd[0] == COMMAND_GET_AND_CLEAR):
#print("[CLIENT HANDLER] Client at " + ip_str + ": COMMAND_GET_AND_CLEAR")
res = james_utils.receive_bytes(c, 1)
if(res == -1 or res == -2 or res == -3):
print("[CLIENT HANDLER] Unable to get channel from client at " + ip_str)
#break
else:
channel_num = res[0]
ts = 0
for t in self.timestamp_list:
if(t.channel_num == channel_num and t.timestamp == 0):
self.timestamp_list.remove(t)
continue
if(t.channel_num == channel_num):
ts = t.timestamp
self.timestamp_list.remove(t)
break
#If we're in dummy mode then just give the system time
if(self.dummy_mode):
ts = int(time.time() * 10000000)
james_utils.send_timestamp(c, ts)
#if(ts >= 0):
#print("[CLIENT HANDLER] Timestamp sent to client for channel " + str(channel_num) + " was " + str(ts))
elif(client_cmd[0] == COMMAND_DUMP_ALL):
res = james_utils.receive_bytes(c, 1)
if(res == -1 or res == -2 or res == -3):
print("[CLIENT HANDLER] Unable to get channel from client at " + ip_str)
#break
else:
cn = res[0]
timestamp_lc = []
for e in self.timestamp_list:#Get all timestamps for this channel
if(e.channel_num == cn):
timestamp_lc.append(e.timestamp)
#self.timestamp_list.remove(e)
self.timestamp_list = []
if(len(timestamp_lc) == 0):
print("Error, length of timestamp list was 0")
timestamp_lc.append(0)
#Serialize and send them
array_to_send = james_utils.timestamps_to_bytes(timestamp_lc)
#print("Len was " + str(len(array_to_send)))
#print(str(array_to_send))
james_utils.send_timestamp(c, len(array_to_send))
to_send = bytearray(array_to_send)
c.send(to_send)
elif(client_cmd[0] == COMMAND_RECORD_PULSES):
print("[CLIENT HANDLER] Client at " + ip_str + ": COMMAND_RECORD")
self.record_pulses = 1
#c.send(SERVER_ACK)
james_utils.send_timestamp(c, 0)
elif(client_cmd[0] == COMMAND_STOP_RECORD):
print("[CLIENT HANDLER] Client at " + ip_str + ": COMMAND_STOP_RECORD")
self.record_pulses = 0
#c.send(SERVER_ACK)
james_utils.send_timestamp(c, 0)
elif(client_cmd[0] == COMMAND_GET_NUM_PULSES):
print("[CLIENT HANDLER] Client at " + ip_str + ": COMMAND_GET_NUM_PULSES, num was " + str(len(self.timestamp_list)))
james_utils.send_timestamp(c, len(self.timestamp_list))
else:
print("[CLIENT HANDLER] Unknown command received from client: " + hex(client_cmd[0]))
c.close()
return
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_mod_dap.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_default.h"
#include "xpfw_rom_interface.h"
#include "xpfw_config.h"
#include "xpfw_core.h"
#include "xpfw_events.h"
#include "xpfw_module.h"
#include "pm_binding.h"
#include "xpfw_mod_dap.h"
/* CfgInit Handler */
static void DapCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
{
/* Used for DAP Wakes */
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_DAP_RPU_WAKE) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: DapCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_DAP_RPU_WAKE)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_DAP_FPD_WAKE) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: DapCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_DAP_FPD_WAKE)
}
XPfw_Printf(DEBUG_DETAILED,"DAP_WAKE (MOD-%d): Initialized.\r\n",
ModPtr->ModId);
}
/* Event Handler */
static void DapEventHandler(const XPfw_Module_t *ModPtr, u32 EventId)
{
if (XPFW_EV_DAP_RPU_WAKE == EventId) {
/* Call ROM Handler for RPU Wake */
XpbrServHndlrTbl[XPBR_SERV_EXT_DAPRPUWAKE]();
XPfw_Printf(DEBUG_DETAILED,"XPFW: DAP RPU WAKE.. Done\r\n");
#ifdef ENABLE_PM
XPfw_DapRpuWakeEvent();
#endif
}
if (XPFW_EV_DAP_FPD_WAKE == EventId) {
/* Call ROM Handler for FPD Wake */
XpbrServHndlrTbl[XPBR_SERV_EXT_DAPFPDWAKE]();
XPfw_Printf(DEBUG_DETAILED,"XPFW: DAP FPD WAKE.. Done\r\n");
#ifdef ENABLE_PM
XPfw_DapFpdWakeEvent();
#endif
}
}
/*
* Create a Mod and assign the Handlers. We will call this function
* from XPfw_UserStartup()
*/
void ModDapInit(void)
{
const XPfw_Module_t *DapModPtr = XPfw_CoreCreateMod();
if (XST_SUCCESS != XPfw_CoreSetCfgHandler(DapModPtr, DapCfgInit)) {
XPfw_Printf(DEBUG_DETAILED,"DAP: Set Cfg handler failed\r\n");
} else if (XST_SUCCESS !=
XPfw_CoreSetEventHandler(DapModPtr, DapEventHandler)) {
XPfw_Printf(DEBUG_DETAILED,"DAP: Set Event handler failed\r\n");
}
}
<file_sep>/python_drivers/qutag_examples/qutag-GetTimestamps-starter_example.py
# Example for using the Coincidence Counters with python + quTAG
#
# Author: qutools GmbH
# Last edited: Oct 2019
#
# Tested with python 3.7.3 (32bit), numpy-1.13.3 and Windows 7 (64bit)
#
# This is demo code. Use at your own risk. No warranties.
#
# It may be used and modified with no restriction; raw copies as well as
# modified versions may be distributed without limitation.
# for sleep
import time
# This code shows how to get timestamps from a quTAG connected via USB.
# Import the python wrapper which wraps the DLL functions.
# The wrapper should be in the same directory like this code in the folder '..\QUTAG-V1.x.x\userlib\src'.
try:
import QuTAG
except:
print("Time Tagger wrapper QuTAG.py is not in the search path.")
# Initialize the quTAG device
qutag = QuTAG.QuTAG()
# Let's check if the device lost some data.
# Timestamps of events detected by the device can get lost if their rate is too high for the USB interface or if the PC is unable to receive the data in time.
# The quTAG recognizes this situation and signals it to the PC (with high priority).
# The function checks if a data loss situation is currently detected or if it has been latched since the last call.
# If you are only interested in the current situation, call the function twice; the first call will delete the latch.
dataloss = qutag.getDataLost()
print("dataloss: " + str(dataloss))
time.sleep(1)
# The next function retrieves the timestamp values of the last n detected events on all channels.
# All timestamps are from a ring buffer with a variable buffer size.
# The default of the buffer size at the initialization of the python wrapper is 1000000.
# In any other usage of the DLL, use the DLL function TDC_setTimestampBufferSize (default 0 -> 0 data will be returned).
# The bool variable describes if the buffer should be cleared after retrieving the data (True).
for i in range(0, 10):
timestamps = qutag.getLastTimestamps(True)
print("Timestamps in an array:")
print(timestamps)
if(timestamps[0][1] != 0):
print("Got something valid!")
# The variable timestamps show our data in an array of:
# an array with all timestamps of the last events in base units 1 ps
# an array with the corresponding channels, range is 0...7 for the channels 1...8
# a variable which shows the number of the valid entries in the above arrays.
# This may be less than the buffer size if the buffer has been cleared.
# !!! If it is the same as the buffer size, the ring buffer is full.
# !!! Probably, the ring buffer was overwritten by new data which was not retrieved yet.
# Disconnects a connected device and stops the internal event loop.
qutag.deInitialize()
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_ipi.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xplmi_ipi.h"
#include "xpm_ipi.h"
#ifdef XPAR_XIPIPSU_0_DEVICE_ID
/****************************************************************************/
/**
* @brief Sends IPI request to the target module
*
* @param IpiMask IPI interrupt mask of target
* @param Payload API id and call arguments to be written in IPI
* buffer
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_IpiSend(u32 IpiMask, u32 *Payload)
{
XStatus Status = XST_FAILURE;
Status = XPlmi_IpiPollForAck(IpiMask, PM_IPI_TIMEOUT);
if (XST_SUCCESS != Status) {
PmDbg("%s: ERROR: Timeout expired\n", __func__);
goto done;
}
Status = XPlmi_IpiWrite(IpiMask, Payload,
PAYLOAD_ARG_CNT, XIPIPSU_BUF_TYPE_MSG);
if (XST_SUCCESS != Status) {
PmDbg("%s: ERROR writing to IPI request buffer\n", __func__);
goto done;
}
Status = XPlmi_IpiTrigger(IpiMask);
done:
return Status;
}
/****************************************************************************/
/**
* @brief Reads IPI Response after target module has handled interrupt
*
* @param IpiMask IPI interrupt mask of target
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
*
* @note None
*
****************************************************************************/
XStatus XPm_IpiReadStatus(u32 IpiMask)
{
u32 Response[RESPONSE_ARG_CNT] = {0};
XStatus Status = XST_FAILURE;
/* Wait until current IPI interrupt is handled by target module */
Status = XPlmi_IpiPollForAck(IpiMask, PM_IPI_TIMEOUT);
if (XST_SUCCESS != Status) {
PmDbg("%s: ERROR: Timeout expired\r\n", __func__);
goto done;
}
Status = XPlmi_IpiRead(IpiMask, Response,
RESPONSE_ARG_CNT, XIPIPSU_BUF_TYPE_RESP);
if (XST_SUCCESS != Status) {
PmDbg("%s: ERROR: Reading from IPI Response buffer\r\n", __func__);
goto done;
}
Status = (XStatus)Response[0];
done:
return Status;
}
#else
XStatus XPm_IpiSend(u32 IpiMask, u32 *Payload)
{
(void)IpiMask;
(void)Payload;
return XST_FAILURE;
}
XStatus XPm_IpiReadStatus(u32 IpiMask)
{
(void)IpiMask;
return XST_FAILURE;
}
#endif /* XPAR_XIPIPSU_0_DEVICE_ID */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilfpga_v5_2/src/xilfpga.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilfpga.c
*
* This file contains the definitions of Bitstream loading functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.2 Nava 08/06/16 Refactor the xilfpga library to support
* different PL programming Interfaces.
* 4.2 adk 11/07/18 Added support for readback of PL configuration data.
* 4.2 Nava 16/08/18 Modified the PL data handling Logic to support
* different PL programming interfaces.
* 4.2 Nava 15/09/18 Fixed global function call-backs issue.
* 5.0 Nava 11/05/18 Added full bitstream loading support for versal Platform.
* 5.0 Div 21/01/19 Fixed misra-c required standard violation for zynqmp.
* 5.0 Nava 06/02/19 Remove redundant API's from the interface agnostic layer
* and make the existing API's generic to support both
* ZynqMP and versal platforms.
* 5.0 Nava 26/02/19 Update the data handling logic to avoid the code
* duplication
* 5.0 sne 27/03/19 Fixed misra-c violations.
* 5.0 Nava 29/03/19 Removed vesal platform related changes.As per the new
* design, the Bitstream loading for versal platform is
* done by PLM based on the CDO's data exists in the PDI
* images. So there is no need of xilfpga API's for versal
* platform to configure the PL.
* 5.1 Nava 27/06/19 Updated documentation for readback API's.
* 5.1 Nava 16/07/19 Initialize empty status (or) status success to status failure
* to avoid security violations.
* 5.2 Nava 05/12/19 Added Versal platform support.
* 5.2 Nava 14/02/20 Added Bitstream loading support by using IPI services
* for ZynqMP platform.
*
*</pre>
*
*@note
*****************************************************************************/
/***************************** Include Files *********************************/
#include "xilfpga.h"
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**The API is used to load the bitstream file into the PL region.
* It supports vivado generated Bitstream(*.bit, *.bin) and bootgen
* generated Bitstream(*.bin) loading, Passing valid Bitstream size
* (AddrPtr_Size) info is mandatory for vivado * generated Bitstream,
* For bootgen generated Bitstreams it will take Bitstream size from
* the Bitstream Header.
*
*@param InstancePtr Pointer to the XFgpa structure.
*
*@param BitstreamImageAddr Linear memory Bitstream image base address
*
*@param AddrPtr_Size Aes key address which is used for Decryption (or)
* In none Secure Bitstream used it is used to store size
* of Bitstream Image.
*
*@param Flags Flags are used to specify the type of Bitstream file.
* * BIT(0) - Bitstream type
* * 0 - Full Bitstream
* * 1 - Partial Bitstream
* * BIT(1) - Authentication using DDR
* * 1 - Enable
* * 0 - Disable
* * BIT(2) - Authentication using OCM
* * 1 - Enable
* * 0 - Disable
* * BIT(3) - User-key Encryption
* * 1 - Enable
* * 0 - Disable
* * BIT(4) - Device-key Encryption
* * 1 - Enable
* * 0 - Disable
*
*@return
* - XFPGA_SUCCESS on success
* - Error code on failure.
* - XFPGA_VALIDATE_ERROR.
* - XFPGA_PRE_CONFIG_ERROR.
* - XFPGA_WRITE_BITSTREAM_ERROR.
* - XFPGA_POST_CONFIG_ERROR.
*
*****************************************************************************/
u32 XFpga_PL_BitStream_Load(XFpga *InstancePtr,
UINTPTR BitstreamImageAddr,
UINTPTR AddrPtr_Size, u32 Flags)
{
u32 Status = XFPGA_FAILURE;
/* Validate Bitstream Image */
Status = XFpga_PL_ValidateImage(InstancePtr, BitstreamImageAddr,
AddrPtr_Size, Flags);
if ((Status != XFPGA_OPS_NOT_IMPLEMENTED) &&
(Status != XFPGA_SUCCESS)) {
goto END;
}
/* Prepare the FPGA to receive configuration Data */
Status = XFpga_PL_Preconfig(InstancePtr);
if (Status != XFPGA_SUCCESS &&
Status != XFPGA_OPS_NOT_IMPLEMENTED) {
goto END;
}
/* write count bytes of configuration data into the PL */
Status = XFpga_PL_Write(InstancePtr,
InstancePtr->WriteInfo.BitstreamAddr,
InstancePtr->WriteInfo.AddrPtr_Size,
InstancePtr->WriteInfo.Flags);
if (Status != XFPGA_SUCCESS) {
goto END;
}
/* set FPGA to operating state after writing */
Status = XFpga_PL_PostConfig(InstancePtr);
if (Status == XFPGA_OPS_NOT_IMPLEMENTED) {
Status = XFPGA_SUCCESS;
}
END:
return Status;
}
/*****************************************************************************/
/**
* This function is used to validate the Bitstream Image
*
* @param InstancePtr Pointer to the XFgpa structure
*
* @param BitstreamImageAddr Linear memory Bitstream image base address
*
* @param AddrPtr_Size Aes key address which is used for Decryption (or)
* In none Secure Bitstream used it is used to store size
* of Bitstream Image.
*
* @param Flags Flags are used to specify the type of Bitstream file.
* * BIT(0) - Bitstream type
* * 0 - Full Bitstream
* * 1 - Partial Bitstream
* * BIT(1) - Authentication using DDR
* * 1 - Enable
* * 0 - Disable
* * BIT(2) - Authentication using OCM
* * 1 - Enable
* * 0 - Disable
* * BIT(3) - User-key Encryption
* * 1 - Enable
* * 0 - Disable
* * BIT(4) - Device-key Encryption
* * 1 - Enable
* * 0 - Disable
*
* @return Codes as mentioned in xilfpga.h
*****************************************************************************/
u32 XFpga_PL_ValidateImage(XFpga *InstancePtr,
UINTPTR BitstreamImageAddr,
UINTPTR AddrPtr_Size, u32 Flags)
{
u32 Status = XFPGA_VALIDATE_ERROR;
Xil_AssertNonvoid(InstancePtr != NULL);
InstancePtr->WriteInfo.BitstreamAddr = BitstreamImageAddr;
InstancePtr->WriteInfo.AddrPtr_Size = AddrPtr_Size;
InstancePtr->WriteInfo.Flags = Flags;
if (InstancePtr->XFpga_ValidateBitstream == NULL) {
Status = XFPGA_OPS_NOT_IMPLEMENTED;
Xfpga_Printf(XFPGA_DEBUG,
"%s Implementation not exists..\r\n", __FUNCTION__);
} else {
Status = InstancePtr->XFpga_ValidateBitstream(InstancePtr);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_UPDATE_ERR(XFPGA_VALIDATE_ERROR, Status);
}
}
return Status;
}
/*****************************************************************************/
/* This function prepare the FPGA to receive configuration data.
*
* @param InstancePtr is the pointer to the XFgpa.
*
* @return Codes as mentioned in xilfpga.h
*****************************************************************************/
u32 XFpga_PL_Preconfig(XFpga *InstancePtr)
{
u32 Status = XFPGA_PRE_CONFIG_ERROR;
Xil_AssertNonvoid(InstancePtr != NULL);
if (InstancePtr->XFpga_PreConfig == NULL) {
Status = XFPGA_OPS_NOT_IMPLEMENTED;
Xfpga_Printf(XFPGA_DEBUG,
"%s Implementation not exists..\r\n", __FUNCTION__);
} else {
Status = InstancePtr->XFpga_PreConfig(InstancePtr);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_UPDATE_ERR(XFPGA_PRE_CONFIG_ERROR,
Status);
}
}
return Status;
}
/*****************************************************************************/
/* This function write count bytes of configuration data into the PL.
*
* @param InstancePtr Pointer to the XFgpa structure
*
* @param BitstreamImageAddr Linear memory Bitstream image base address
*
* @param AddrPtr_Size Aes key address which is used for Decryption (or)
* In none Secure Bitstream used it is used to store size
* of Bitstream Image.
*
* @param Flags Flags are used to specify the type of Bitstream file.
* * BIT(0) - Bitstream type
* * 0 - Full Bitstream
* * 1 - Partial Bitstream
* * BIT(1) - Authentication using DDR
* * 1 - Enable
* * 0 - Disable
* * BIT(2) - Authentication using OCM
* * 1 - Enable
* * 0 - Disable
* * BIT(3) - User-key Encryption
* * 1 - Enable
* * 0 - Disable
* * BIT(4) - Device-key Encryption
* * 1 - Enable
* * 0 - Disable
*
* @return Codes as mentioned in xilfpga.h
*****************************************************************************/
u32 XFpga_PL_Write(XFpga *InstancePtr,UINTPTR BitstreamImageAddr,
UINTPTR AddrPtr_Size, u32 Flags)
{
u32 Status = XFPGA_WRITE_BITSTREAM_ERROR;
Xil_AssertNonvoid(InstancePtr != NULL);
InstancePtr->WriteInfo.BitstreamAddr = BitstreamImageAddr;
InstancePtr->WriteInfo.AddrPtr_Size = AddrPtr_Size;
InstancePtr->WriteInfo.Flags = Flags;
if (InstancePtr->XFpga_WriteToPl == NULL) {
Status = XFPGA_OPS_NOT_IMPLEMENTED;
Xfpga_Printf(XFPGA_DEBUG,
"%s Implementation not exists..\r\n", __FUNCTION__);
} else {
Status = InstancePtr->XFpga_WriteToPl(InstancePtr);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_UPDATE_ERR(XFPGA_WRITE_BITSTREAM_ERROR,
Status);
}
}
return Status;
}
/*****************************************************************************/
/** This function set FPGA to operating state after writing.
*
* @param InstancePtr Pointer to the XFgpa structure
*
* @return Codes as mentioned in xilfpga.h
*****************************************************************************/
u32 XFpga_PL_PostConfig(XFpga *InstancePtr)
{
u32 Status = XFPGA_POST_CONFIG_ERROR;
Xil_AssertNonvoid(InstancePtr != NULL);
if (InstancePtr->XFpga_PostConfig == NULL) {
Status = XFPGA_OPS_NOT_IMPLEMENTED;
Xfpga_Printf(XFPGA_DEBUG,
"%s Implementation not exists..\r\n", __FUNCTION__);
} else {
Status = InstancePtr->XFpga_PostConfig(InstancePtr);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_UPDATE_ERR(XFPGA_POST_CONFIG_ERROR,
Status);
}
}
return Status;
}
#ifndef versal
/*****************************************************************************/
/**
* This function provides functionality to read back the PL configuration data
*
* @param InstancePtr Pointer to the XFgpa structure
*
* @param ReadbackAddr Address which is used to store the PL readback data.
*
* @param NumFrames The number of Fpga configuration frames to read.
*
* @return
* - XFPGA_SUCCESS if successful
* - XFPGA_FAILURE if unsuccessful
* - XFPGA_OPS_NOT_IMPLEMENTED if implementation not exists.
*
****************************************************************************/
u32 XFpga_GetPlConfigData(XFpga *InstancePtr, UINTPTR ReadbackAddr,
u32 NumFrames)
{
u32 Status = XFPGA_FAILURE;
Xil_AssertNonvoid(InstancePtr != NULL);
InstancePtr->ReadInfo.ReadbackAddr = ReadbackAddr;
InstancePtr->ReadInfo.ConfigReg_NumFrames = NumFrames;
if (InstancePtr->XFpga_GetConfigData == NULL) {
Status = XFPGA_OPS_NOT_IMPLEMENTED;
Xfpga_Printf(XFPGA_DEBUG,
"%s Implementation not exists..\r\n", __FUNCTION__);
} else {
Status = InstancePtr->XFpga_GetConfigData(InstancePtr);
}
return Status;
}
/*****************************************************************************/
/**
* This function provides PL specific configuration register values
*
* @param InstancePtr Pointer to the XFgpa structure
*
* @param ReadbackAddr Address which is used to store the PL Configuration
* register data.
*
* @param ConfigRegAddr Configuration register address as mentioned in the
* ug570.
*
* @return
* - XFPGA_SUCCESS if successful
* - XFPGA_FAILURE if unsuccessful
* - XFPGA_OPS_NOT_IMPLEMENTED if implementation not exists.
*
****************************************************************************/
u32 XFpga_GetPlConfigReg(XFpga *InstancePtr, UINTPTR ReadbackAddr,
u32 ConfigRegAddr)
{
u32 Status = XFPGA_FAILURE;
Xil_AssertNonvoid(InstancePtr != NULL);
InstancePtr->ReadInfo.ReadbackAddr = ReadbackAddr;
InstancePtr->ReadInfo.ConfigReg_NumFrames = ConfigRegAddr;
if (InstancePtr->XFpga_GetConfigReg == NULL) {
Status = XFPGA_OPS_NOT_IMPLEMENTED;
Xfpga_Printf(XFPGA_DEBUG,
"%s Implementation not exists..\r\n", __FUNCTION__);
} else {
Status = InstancePtr->XFpga_GetConfigReg(InstancePtr);
}
return Status;
}
/*****************************************************************************/
/** This function provides the STATUS of PL programming interface
*
* @param InstancePtr Pointer to the XFgpa structure
*
* @return Status of the PL programming interface
*
*****************************************************************************/
u32 XFpga_InterfaceStatus(XFpga *InstancePtr)
{
u32 RegVal = XFPGA_INVALID_INTERFACE_STATUS;
Xil_AssertNonvoid(InstancePtr != NULL);
if (InstancePtr->XFpga_GetInterfaceStatus == NULL) {
Xfpga_Printf(XFPGA_DEBUG,
"%s Implementation not exists..\r\n", __FUNCTION__);
} else {
RegVal = InstancePtr->XFpga_GetInterfaceStatus();
}
return RegVal;
}
#endif
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/wdtps_v3_3/src/xwdtps_selftest.c
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xwdtps_selftest.c
* @addtogroup wdtps_v3_3
* @{
*
* Contains diagnostic self-test functions for the XWdtPs driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------------
* 1.00a ecm/jz 01/15/10 First release
* 1.02a sg 08/01/12 Modified it use the Reset Length mask for the self
* test for CR 658287
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xwdtps.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
*
* Run a self-test on the timebase. This test verifies that the register access
* locking functions. This is tested by trying to alter a register without
* setting the key value and verifying that the register contents did not
* change.
*
* @param InstancePtr is a pointer to the XWdtPs instance.
*
* @return
* - XST_SUCCESS if self-test was successful.
* - XST_FAILURE if self-test was not successful.
*
* @note None.
*
******************************************************************************/
s32 XWdtPs_SelfTest(XWdtPs *InstancePtr)
{
u32 ZmrOrig;
u32 ZmrValue1;
u32 ZmrValue2;
s32 Status;
/*
* Assert to ensure the inputs are valid and the instance has been
* initialized.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Read the ZMR register at start the test.
*/
ZmrOrig = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
XWDTPS_ZMR_OFFSET);
/*
* EX-OR in the length of the interrupt pulse,
* do not set the key value.
*/
ZmrValue1 = ZmrOrig ^ (u32)XWDTPS_ZMR_RSTLN_MASK;
/*
* Try to write to register w/o key value then read back.
*/
XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
ZmrValue1);
ZmrValue2 = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
XWDTPS_ZMR_OFFSET);
if (ZmrValue1 == ZmrValue2) {
/*
* If the values match, the hw failed the test,
* return orig register value.
*/
XWdtPs_WriteReg(InstancePtr->Config.BaseAddress,
XWDTPS_ZMR_OFFSET,
(ZmrOrig | (u32)XWDTPS_ZMR_ZKEY_VAL));
Status = XST_FAILURE;
} else {
/*
* Try to write to register with key value then read back.
*/
XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
(ZmrValue1 | XWDTPS_ZMR_ZKEY_VAL));
ZmrValue2 = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
XWDTPS_ZMR_OFFSET);
if (ZmrValue1 != ZmrValue2) {
/*
* If the values do not match, the hw failed the test,
* return orig register value.
*/
XWdtPs_WriteReg(InstancePtr->Config.BaseAddress,
XWDTPS_ZMR_OFFSET,
ZmrOrig | XWDTPS_ZMR_ZKEY_VAL);
Status = XST_FAILURE;
} else {
/*
* The hardware locking feature is functional, return the original value
* and return success.
*/
XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
ZmrOrig | XWDTPS_ZMR_ZKEY_VAL);
Status = XST_SUCCESS;
}
}
return Status;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/csudma_v1_6/src/xcsudma_selftest.c
/******************************************************************************
* Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcsudma_selftest.c
* @addtogroup csudma_v1_6
* @{
*
* This file contains a diagnostic self-test function for the CSU_DMA driver.
* Refer to the header file xcsudma.h for more detailed information.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------------
* 1.0 vnsld 22/10/14 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xcsudma.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function runs a self-test on the driver and hardware device. Performs
* reset of both source and destination channels and checks if reset is working
* properly or not.
*
* @param InstancePtr is a pointer to the XCsuDma instance.
*
* @return
* - XST_SUCCESS if the self-test passed.
* - XST_FAILURE otherwise.
*
* @note None.
*
******************************************************************************/
s32 XCsuDma_SelfTest(XCsuDma *InstancePtr)
{
u32 Data;
s32 Status;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
(u32)(XCSUDMA_CTRL_OFFSET));
/* Changing Endianess of Source channel */
XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
(u32)(XCSUDMA_CTRL_OFFSET),
((Data) | (u32)(XCSUDMA_CTRL_ENDIAN_MASK)));
if ((XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
(u32)(XCSUDMA_CTRL_OFFSET)) &
(u32)(XCSUDMA_CTRL_ENDIAN_MASK)) ==
(XCSUDMA_CTRL_ENDIAN_MASK)) {
Status = (s32)(XST_SUCCESS);
}
else {
Status = (s32)(XST_FAILURE);
}
/* Changes made are being reverted back */
XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
(u32)(XCSUDMA_CTRL_OFFSET), Data);
return Status;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/xfsbl_csu_dma.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xfsbl_csu_dma.c
*
* Contains code for the CSU DMA initialization
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 kc 07/22/14 Initial release
* 2.0 bv 12/05/16 Made compliance to MISRAC 2012 guidelines
*
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xcsudma.h"
#include "xfsbl_csu_dma.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
XCsuDma CsuDma = {0U};
/*****************************************************************************/
/**
* This function is used to initialize the DMA driver
*
* @param None
*
* @return returns the error codes described in xfsbl_error.h on any error
* returns XFSBL_SUCCESS on success
*
*****************************************************************************/
u32 XFsbl_CsuDmaInit(void)
{
u32 Status;
s32 SStatus;
XCsuDma_Config * CsuDmaConfig;
(void)memset(&CsuDma, 0, sizeof(CsuDma));
CsuDmaConfig = XCsuDma_LookupConfig(0);
if (NULL == CsuDmaConfig) {
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_CSUDMA_INIT_FAIL \n\r");
Status = XFSBL_ERROR_CSUDMA_INIT_FAIL;
goto END;
}
SStatus = XCsuDma_CfgInitialize(&CsuDma, CsuDmaConfig,
CsuDmaConfig->BaseAddress);
if (SStatus != XFSBL_SUCCESS) {
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_CSUDMA_INIT_FAIL \n\r");
Status = XFSBL_ERROR_CSUDMA_INIT_FAIL;
goto END;
}
Status = XFSBL_SUCCESS;
END:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/iicps_v3_11/src/xiicps_intr.c
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_intr.c
* @addtogroup iicps_v3_11
* @{
*
* Contains functions of the XIicPs driver for interrupt-driven transfers.
* See xiicps.h for a detailed description of the device and driver.
*
* <pre> MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/30/10 First release
* 3.00 sk 01/31/15 Modified the code according to MISRAC 2012 Compliant.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xiicps.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************* Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* @brief
* This function sets the status callback function, the status handler, which the
* driver calls when it encounters conditions that should be reported to the
* higher layer software. The handler executes in an interrupt context, so
* the amount of processing should be minimized
*
* Refer to the xiicps.h file for a list of the Callback events. The events are
* defined to start with XIICPS_EVENT_*.
*
* @param InstancePtr is a pointer to the XIicPs instance.
* @param CallBackRef is the upper layer callback reference passed back
* when the callback function is invoked.
* @param FunctionPtr is the pointer to the callback function.
*
* @return None.
*
* @note
*
* The handler is called within interrupt context, so it should finish its
* work quickly.
*
******************************************************************************/
void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
XIicPs_IntrHandler FunctionPtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FunctionPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
InstancePtr->StatusHandler = FunctionPtr;
InstancePtr->CallBackRef = CallBackRef;
}
/** @} */
<file_sep>/python_drivers/alice_time_sync_data_collector.py
# -*- coding: utf-8 -*-
"""
Created on Wed Jul 22 15:56:33 2020
@author: tianlab01
"""
import time
import time_sync
import james_utils
import tdc_wrapper
server_ip = "192.168.56.1"
tdc = tdc_wrapper.tdc_wrapper(15,0,tdc_wrapper.MODE_CLIENT,"192.168.56.1")
ts = time_sync.time_sync(james_utils.ALICE_PORT, server_ip, time_sync.CLIENT, tdc)
logfile = "time_sync_stats.csv"
count = 0
while(1):
try:
file = open(logfile,'a')
ts.start_client_sync()
new_line = str(count) + ", " + str(ts.time_diff) + ", " + str(ts.path_len) + "\n"
file.write(new_line)
file.close()
count += 1
print("Waiting 5 seconds...")
time.sleep(5)
except KeyboardInterrupt:
print("Exiting")
break<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_prot.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PROT_H_
#define XPM_PROT_H_
#include "xpm_requirement.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Protection node states */
typedef enum {
XPM_PROT_DISABLED,
XPM_PROT_ENABLED,
} XPm_ProtState;
typedef struct XPm_Prot XPm_Prot;
typedef struct XPm_ProtMpu XPm_ProtMpu;
typedef struct XPm_ProtPpu XPm_ProtPpu;
/**
* The processor core class. This is the base class for all processor cores.
*/
struct XPm_Prot {
XPm_Node Node; /**< Node: Base class */
};
typedef struct Aperture {
u32 NumSupported; /**< Number of Supported Apertures */
u32 StartAddress; /**< Aperture Base Address */
u32 EndAddress; /**< Aperture End Address */
}Aperture;
struct XPm_ProtPpu {
XPm_Prot ProtNode; /**< Node: Base Class */
Aperture Aperture_64k; /**< Aperture 64k */
Aperture Aperture_1m; /**< Aperture 1m */
Aperture Aperture_512m; /**< Aperture 512m */
u8 MIDParityEn; /**< Parity error checking status for Master IDs */
u8 AperParityEn; /**< Parity error checking status for Aperture entries */
};
struct XPm_ProtMpu {
XPm_Prot ProtNode;
};
/************************** Function Prototypes ******************************/
XStatus XPmProtPpu_Init(XPm_ProtPpu *PpuNode, u32 Id, u32 BaseAddr);
XStatus XPmProtMpu_Init(XPm_ProtMpu *MpuNode, u32 Id, u32 BaseAddr);
XStatus XPmProt_Configure(XPm_Requirement *Reqm, u32 Enable);
XStatus XPmProt_XppuEnable(u32 NodeId, u32 ApertureInitVal);
XStatus XPmProt_XppuDisable(u32 NodeId);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_PROT_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/pm_clock.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/**
* @file pm_clock.c
*
* PM Definitions implementation
* @addtogroup xpm_apis XilPM APIs
* @{
*****************************************************************************/
#include "pm_clock.h"
#include "pm_common.h"
#define PM_CLOCK_TYPE_DIV0 (1U << PM_CLOCK_DIV0_ID) /* bits 13:8 */
#define PM_CLOCK_TYPE_DIV1 (1U << PM_CLOCK_DIV1_ID) /* bits 21:16 */
#define PM_DIV_WIDTH 0x3FU
#define PM_2xDIV_WIDTH (PM_DIV_WIDTH * PM_DIV_WIDTH)
#define PM_CLOCK_HAS_DIV0(clk) (0U != ((clk)->type & PM_CLOCK_TYPE_DIV0))
#define PM_CLOCK_HAS_DIV1(clk) (0U != ((clk)->type & PM_CLOCK_TYPE_DIV1))
/**
* Pair of multiplexer select value and selected clock input
*/
typedef struct {
/**
ID of the clock that is selected with the 'select' value
*/
const enum XPmClock clkIn;
/**
Select value of the clock multiplexer
*/
const u8 select;
} XPmClockSel2ClkIn;
/**
* MUX select values to clock input mapping
*/
typedef struct {
/** Mux select to pll mapping at the input of the multiplexer */
const XPmClockSel2ClkIn* const inputs;
/** Size of the inputs array*/
const u8 size;
/** Number of bits of mux select*/
const u8 bits;
/** Number of bits to shift 'bits' in order to get mux select mask*/
const u8 shift;
} XPmClockMux;
/**
* Clock model
*/
typedef struct XPmClkModel {
/** Clock ID*/
const enum XPmClock id;
/** Pointer to the mux model*/
const XPmClockMux* const mux;
/** Type specifying the available divisors*/
const u8 type;
/** Next clock in the list*/
const struct XPmClkModel* const next;
} XPmClockModel;
/******************************************************************************/
/* Clock multiplexer models */
static const XPmClockSel2ClkIn advSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_APLL,
.select = 0U,
}, {
.clkIn = PM_CLOCK_DPLL,
.select = 2U,
}, {
.clkIn = PM_CLOCK_VPLL,
.select = 3U,
},
};
static XPmClockMux advMux = {
.inputs = advSel2ClkIn,
.size = PM_ARRAY_SIZE(advSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn avdSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_APLL,
.select = 0U,
}, {
.clkIn = PM_CLOCK_VPLL,
.select = 2U,
}, {
.clkIn = PM_CLOCK_DPLL,
.select = 3U,
},
};
static XPmClockMux avdMux = {
.inputs = avdSel2ClkIn,
.size = PM_ARRAY_SIZE(avdSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn aiodSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_APLL,
.select = 0U,
}, {
.clkIn = PM_CLOCK_IOPLL_TO_FPD,
.select = 2U,
}, {
.clkIn = PM_CLOCK_DPLL,
.select = 3U,
},
};
static XPmClockMux aiodMux = {
.inputs = aiodSel2ClkIn,
.size = PM_ARRAY_SIZE(aiodSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn vdrSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_VPLL,
.select = 0U,
}, {
.clkIn = PM_CLOCK_DPLL,
.select = 2U,
}, {
.clkIn = PM_CLOCK_RPLL_TO_FPD,
.select = 3U,
},
};
static XPmClockMux vdrMux = {
.inputs = vdrSel2ClkIn,
.size = PM_ARRAY_SIZE(vdrSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn dvSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_DPLL,
.select = 0U,
}, {
.clkIn = PM_CLOCK_VPLL,
.select = 1U,
},
};
static XPmClockMux dvMux = {
.inputs = dvSel2ClkIn,
.size = PM_ARRAY_SIZE(dvSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn iovdSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_IOPLL_TO_FPD,
.select = 0U,
}, {
.clkIn = PM_CLOCK_VPLL,
.select = 2U,
}, {
.clkIn = PM_CLOCK_DPLL,
.select = 3U,
},
};
static XPmClockMux iovdMux = {
.inputs = iovdSel2ClkIn,
.size = PM_ARRAY_SIZE(iovdSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn ioadSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_IOPLL_TO_FPD,
.select = 0U,
}, {
.clkIn = PM_CLOCK_APLL,
.select = 2U,
}, {
.clkIn = PM_CLOCK_DPLL,
.select = 3U,
},
};
static XPmClockMux ioadMux = {
.inputs = ioadSel2ClkIn,
.size = PM_ARRAY_SIZE(ioadSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn iodaSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_IOPLL_TO_FPD,
.select = 0U,
}, {
.clkIn = PM_CLOCK_DPLL,
.select = 2U,
}, {
.clkIn = PM_CLOCK_APLL,
.select = 3U,
},
};
static XPmClockMux iodaMux = {
.inputs = iodaSel2ClkIn,
.size = PM_ARRAY_SIZE(iodaSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn iorSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_IOPLL,
.select = 0U,
}, {
.clkIn = PM_CLOCK_RPLL,
.select = 2U,
},
};
static XPmClockMux iorMux = {
.inputs = iorSel2ClkIn,
.size = PM_ARRAY_SIZE(iorSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn iordFpdSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_IOPLL_TO_FPD,
.select = 0U,
}, {
.clkIn = PM_CLOCK_RPLL_TO_FPD,
.select = 2U,
}, {
.clkIn = PM_CLOCK_DPLL,
.select = 3U,
},
};
static XPmClockMux iordFpdMux = {
.inputs = iordFpdSel2ClkIn,
.size = PM_ARRAY_SIZE(iordFpdSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn iordSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_IOPLL,
.select = 0U,
}, {
.clkIn = PM_CLOCK_RPLL,
.select = 2U,
}, {
.clkIn = PM_CLOCK_DPLL_TO_LPD,
.select = 3U,
},
};
static XPmClockMux iordMux = {
.inputs = iordSel2ClkIn,
.size = PM_ARRAY_SIZE(iordSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn iorvSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_IOPLL,
.select = 0U,
}, {
.clkIn = PM_CLOCK_RPLL,
.select = 2U,
}, {
.clkIn = PM_CLOCK_VPLL_TO_LPD,
.select = 3U,
},
};
static XPmClockMux iorvMux = {
.inputs = iorvSel2ClkIn,
.size = PM_ARRAY_SIZE(iorvSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn riodSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_RPLL,
.select = 0U,
}, {
.clkIn = PM_CLOCK_IOPLL,
.select = 2U,
}, {
.clkIn = PM_CLOCK_DPLL_TO_LPD,
.select = 3U,
},
};
static XPmClockMux riodMux = {
.inputs = riodSel2ClkIn,
.size = PM_ARRAY_SIZE(riodSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const XPmClockSel2ClkIn iordPsRefSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_IOPLL,
.select = 0U,
}, {
.clkIn = PM_CLOCK_RPLL,
.select = 2U,
}, {
.clkIn = PM_CLOCK_DPLL_TO_LPD,
.select = 3U,
}, {
.clkIn = PM_CLOCK_EXT_PSS_REF,
.select = 4U,
}, {
.clkIn = PM_CLOCK_EXT_PSS_REF,
.select = 5U,
}, {
.clkIn = PM_CLOCK_EXT_PSS_REF,
.select = 6U,
}, {
.clkIn = PM_CLOCK_EXT_PSS_REF,
.select = 7U,
},
};
static XPmClockMux iordPsRefMux = {
.inputs = iordPsRefSel2ClkIn,
.size = PM_ARRAY_SIZE(iordPsRefSel2ClkIn),
.bits = 3U,
.shift = 0U,
};
static XPmClockMux can0MioMux = {
.inputs = NULL, /* NULL is reserved for MIO inputs */
.size = 0U,
.bits = 7U,
.shift = 0U,
};
static XPmClockMux can1MioMux = {
.inputs = NULL, /* NULL is reserved for MIO inputs */
.size = 0U,
.bits = 7U,
.shift = 15U,
};
static const XPmClockSel2ClkIn can0Sel2ClkIn[] = {
{
.clkIn = PM_CLOCK_CAN0_REF,
.select = 0U,
}, {
.clkIn = PM_CLOCK_CAN0_MIO,
.select = 1U,
},
};
static XPmClockMux can0Mux = {
.inputs = can0Sel2ClkIn,
.size = PM_ARRAY_SIZE(can0Sel2ClkIn),
.bits = 1U,
.shift = 7U,
};
static const XPmClockSel2ClkIn can1Sel2ClkIn[] = {
{
.clkIn = PM_CLOCK_CAN1_REF,
.select = 0U,
}, {
.clkIn = PM_CLOCK_CAN1_MIO,
.select = 1U,
},
};
static XPmClockMux can1Mux = {
.inputs = can1Sel2ClkIn,
.size = PM_ARRAY_SIZE(can1Sel2ClkIn),
.bits = 1U,
.shift = 22U,
};
static const XPmClockSel2ClkIn gemTsuSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_GEM_TSU_REF,
.select = 0U,
}, {
.clkIn = PM_CLOCK_EXT_MIO26,
.select = 1U,
}, {
.clkIn = PM_CLOCK_GEM_TSU_REF,
.select = 2U,
}, {
.clkIn = PM_CLOCK_EXT_MIO50_OR_MIO51,
.select = 3U,
},
};
static XPmClockMux gemTsuMux = {
.inputs = gemTsuSel2ClkIn,
.size = PM_ARRAY_SIZE(gemTsuSel2ClkIn),
.bits = 2U,
.shift = 20U,
};
static const XPmClockSel2ClkIn gem0RefSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_GEM0_REF_UNGATED,
.select = 0U,
}, {
.clkIn = PM_CLOCK_EXT_GEM0_TX_EMIO,
.select = 1U,
},
};
static XPmClockMux gem0RefMux = {
.inputs = gem0RefSel2ClkIn,
.size = PM_ARRAY_SIZE(gem0RefSel2ClkIn),
.bits = 1U,
.shift = 1U,
};
static const XPmClockSel2ClkIn gem1RefSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_GEM1_REF_UNGATED,
.select = 0U,
}, {
.clkIn = PM_CLOCK_EXT_GEM1_TX_EMIO,
.select = 1U,
},
};
static XPmClockMux gem1RefMux = {
.inputs = gem1RefSel2ClkIn,
.size = PM_ARRAY_SIZE(gem1RefSel2ClkIn),
.bits = 1U,
.shift = 6U,
};
static const XPmClockSel2ClkIn gem2RefSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_GEM2_REF_UNGATED,
.select = 0U,
}, {
.clkIn = PM_CLOCK_EXT_GEM2_TX_EMIO,
.select = 1U,
},
};
static XPmClockMux gem2RefMux = {
.inputs = gem2RefSel2ClkIn,
.size = PM_ARRAY_SIZE(gem2RefSel2ClkIn),
.bits = 1U,
.shift = 11U,
};
static const XPmClockSel2ClkIn gem3RefSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_GEM3_REF_UNGATED,
.select = 0U,
}, {
.clkIn = PM_CLOCK_EXT_GEM3_TX_EMIO,
.select = 1U,
},
};
static XPmClockMux gem3RefMux = {
.inputs = gem3RefSel2ClkIn,
.size = PM_ARRAY_SIZE(gem3RefSel2ClkIn),
.bits = 1U,
.shift = 16U,
};
static const XPmClockSel2ClkIn fpdWdtSel2ClkIn[] = {
{
.clkIn = PM_CLOCK_TOPSW_LSBUS,
.select = 0U,
}, {
.clkIn = PM_CLOCK_EXT_SWDT1,
.select = 1U,
},
};
static XPmClockMux fpdWdtMux = {
.inputs = fpdWdtSel2ClkIn,
.size = PM_ARRAY_SIZE(fpdWdtSel2ClkIn),
.bits = 1U,
.shift = 0U,
};
/******************************************************************************/
/* Clock models (only clocks with mux and divisor need to be modeled) */
static XPmClockModel pmClockAcpu = {
.id = PM_CLOCK_ACPU,
.mux = &advMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = NULL,
};
static XPmClockModel pmClockDbgTrace = {
.id = PM_CLOCK_DBG_TRACE,
.mux = &iodaMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockAcpu,
};
static XPmClockModel pmClockDbgFpd = {
.id = PM_CLOCK_DBG_FPD,
.mux = &iodaMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockDbgTrace,
};
static XPmClockModel pmClockDpVideo = {
.id = PM_CLOCK_DP_VIDEO_REF,
.mux = &vdrMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockDbgFpd,
};
static XPmClockModel pmClockDpAudio = {
.id = PM_CLOCK_DP_AUDIO_REF,
.mux = &vdrMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockDpVideo,
};
static XPmClockModel pmClockDpStc = {
.id = PM_CLOCK_DP_STC_REF,
.mux = &vdrMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockDpAudio,
};
static XPmClockModel pmClockDdr = {
.id = PM_CLOCK_DDR_REF,
.mux = &dvMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockDpStc,
};
static XPmClockModel pmClockGpu = {
.id = PM_CLOCK_GPU_REF,
.mux = &iovdMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockDdr,
};
static XPmClockModel pmClockSata = {
.id = PM_CLOCK_SATA_REF,
.mux = &ioadMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockGpu,
};
static XPmClockModel pmClockPcie = {
.id = PM_CLOCK_PCIE_REF,
.mux = &iordFpdMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockSata,
};
static XPmClockModel pmClockGdma = {
.id = PM_CLOCK_GDMA_REF,
.mux = &avdMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockPcie,
};
static XPmClockModel pmClockDpDma = {
.id = PM_CLOCK_DPDMA_REF,
.mux = &avdMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockGdma,
};
static XPmClockModel pmClockTopSwMain = {
.id = PM_CLOCK_TOPSW_MAIN,
.mux = &avdMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockDpDma,
};
static XPmClockModel pmClockTopSwLsBus = {
.id = PM_CLOCK_TOPSW_LSBUS,
.mux = &aiodMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockTopSwMain,
};
static XPmClockModel pmClockDbgTstmp = {
.id = PM_CLOCK_DBG_TSTMP,
.mux = &iodaMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockTopSwLsBus,
};
static XPmClockModel pmClockUsb3Dual = {
.id = PM_CLOCK_USB3_DUAL_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockDbgTstmp,
};
static XPmClockModel pmClockGem0RefUngated = {
.id = PM_CLOCK_GEM0_REF_UNGATED,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockUsb3Dual,
};
static XPmClockModel pmClockGem1RefUngated = {
.id = PM_CLOCK_GEM1_REF_UNGATED,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockGem0RefUngated,
};
static XPmClockModel pmClockGem2RefUngated = {
.id = PM_CLOCK_GEM2_REF_UNGATED,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockGem1RefUngated,
};
static XPmClockModel pmClockGem3RefUngated = {
.id = PM_CLOCK_GEM3_REF_UNGATED,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockGem2RefUngated,
};
static XPmClockModel pmClockUsb0Bus = {
.id = PM_CLOCK_USB0_BUS_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockGem3RefUngated,
};
static XPmClockModel pmClockUsb1Bus = {
.id = PM_CLOCK_USB1_BUS_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockUsb0Bus,
};
static XPmClockModel pmClockQSpi = {
.id = PM_CLOCK_QSPI_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockUsb1Bus,
};
static XPmClockModel pmClockSdio0 = {
.id = PM_CLOCK_SDIO0_REF,
.mux = &iorvMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockQSpi,
};
static XPmClockModel pmClockSdio1 = {
.id = PM_CLOCK_SDIO1_REF,
.mux = &iorvMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockSdio0,
};
static XPmClockModel pmClockUart0 = {
.id = PM_CLOCK_UART0_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockSdio1,
};
static XPmClockModel pmClockUart1 = {
.id = PM_CLOCK_UART1_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockUart0,
};
static XPmClockModel pmClockSpi0 = {
.id = PM_CLOCK_SPI0_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockUart1,
};
static XPmClockModel pmClockSpi1 = {
.id = PM_CLOCK_SPI1_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockSpi0,
};
static XPmClockModel pmClockCan0Ref = {
.id = PM_CLOCK_CAN0_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockSpi1,
};
static XPmClockModel pmClockCan1Ref = {
.id = PM_CLOCK_CAN1_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockCan0Ref,
};
static XPmClockModel pmClockCpuR5 = {
.id = PM_CLOCK_CPU_R5,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockCan1Ref,
};
static XPmClockModel pmClockIouSwitch = {
.id = PM_CLOCK_IOU_SWITCH,
.mux = &riodMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockCpuR5,
};
static XPmClockModel pmClockCsuPll = {
.id = PM_CLOCK_CSU_PLL,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockIouSwitch,
};
static XPmClockModel pmClockPcap = {
.id = PM_CLOCK_PCAP,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockCsuPll,
};
static XPmClockModel pmClockLpdSwitch = {
.id = PM_CLOCK_LPD_SWITCH,
.mux = &riodMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockPcap,
};
static XPmClockModel pmClockLpdLsBus = {
.id = PM_CLOCK_LPD_LSBUS,
.mux = &riodMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockLpdSwitch,
};
static XPmClockModel pmClockDbgLpd = {
.id = PM_CLOCK_DBG_LPD,
.mux = &riodMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockLpdLsBus,
};
static XPmClockModel pmClockNand = {
.id = PM_CLOCK_NAND_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockDbgLpd,
};
static XPmClockModel pmClockAdma = {
.id = PM_CLOCK_ADMA_REF,
.mux = &riodMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockNand,
};
static XPmClockModel pmClockPl0 = {
.id = PM_CLOCK_PL0_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockAdma,
};
static XPmClockModel pmClockPl1 = {
.id = PM_CLOCK_PL1_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockPl0,
};
static XPmClockModel pmClockPl2 = {
.id = PM_CLOCK_PL2_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockPl1,
};
static XPmClockModel pmClockPl3 = {
.id = PM_CLOCK_PL3_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockPl2,
};
static XPmClockModel pmClockGemTsuRef = {
.id = PM_CLOCK_GEM_TSU_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockPl3,
};
static XPmClockModel pmClockDll = {
.id = PM_CLOCK_DLL_REF,
.mux = &iorMux,
.type = 0U,
.next = &pmClockGemTsuRef,
};
static XPmClockModel pmClockAms = {
.id = PM_CLOCK_AMS_REF,
.mux = &riodMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockDll,
};
static XPmClockModel pmClockI2C0 = {
.id = PM_CLOCK_I2C0_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockAms,
};
static XPmClockModel pmClockI2C1 = {
.id = PM_CLOCK_I2C1_REF,
.mux = &iordMux,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.next = &pmClockI2C0,
};
static XPmClockModel pmClockTimeStamp = {
.id = PM_CLOCK_TIMESTAMP_REF,
.mux = &iordPsRefMux,
.type = PM_CLOCK_TYPE_DIV0,
.next = &pmClockI2C1,
};
static XPmClockModel pmClockCan0Mio = {
.id = PM_CLOCK_CAN0_MIO,
.mux = &can0MioMux,
.type = 0U,
.next = &pmClockTimeStamp,
};
static XPmClockModel pmClockCan0 = {
.id = PM_CLOCK_CAN0,
.mux = &can0Mux,
.type = 0U,
.next = &pmClockCan0Mio,
};
static XPmClockModel pmClockCan1Mio = {
.id = PM_CLOCK_CAN1_MIO,
.mux = &can1MioMux,
.type = 0U,
.next = &pmClockCan0,
};
static XPmClockModel pmClockCan1 = {
.id = PM_CLOCK_CAN1,
.mux = &can1Mux,
.type = 0U,
.next = &pmClockCan1Mio,
};
static XPmClockModel pmClockGemTsu = {
.id = PM_CLOCK_GEM_TSU,
.mux = &gemTsuMux,
.type = 0U,
.next = &pmClockCan1,
};
static XPmClockModel pmClockGem0Ref = {
.id = PM_CLOCK_GEM0_REF,
.mux = &gem0RefMux,
.type = 0U,
.next = &pmClockGemTsu,
};
static XPmClockModel pmClockGem1Ref = {
.id = PM_CLOCK_GEM1_REF,
.mux = &gem1RefMux,
.type = 0U,
.next = &pmClockGem0Ref,
};
static XPmClockModel pmClockGem2Ref = {
.id = PM_CLOCK_GEM2_REF,
.mux = &gem2RefMux,
.type = 0U,
.next = &pmClockGem1Ref,
};
static XPmClockModel pmClockGem3Ref = {
.id = PM_CLOCK_GEM3_REF,
.mux = &gem3RefMux,
.type = 0U,
.next = &pmClockGem2Ref,
};
static XPmClockModel pmClockFpdWdt = {
.id = PM_CLOCK_WDT,
.mux = &fpdWdtMux,
.type = 0U,
.next = &pmClockGem3Ref,
};
static const XPmClockModel* const head = &pmClockFpdWdt;
/****************************************************************************/
/**
* @brief Get clock structure by clock ID
*
* @param id ID of the target clock
*
* @return Returns pointer to the found clock or NULL
*
* @note None
*
****************************************************************************/
static const XPmClockModel* XPm_GetClockById(const enum XPmClock id)
{
const XPmClockModel* clk = head;
while (clk != NULL) {
if (clk->id == id) {
break;
}
clk = clk->next;
}
return clk;
}
/****************************************************************************/
/**
* @brief Get parent clock ID for a given clock ID and mux select value
*
* @param clockId ID of the target clock
* @param select Mux select value
* @param parentId Location to store parent clock ID
*
* @return Returns XST_SUCCESS if parent clock ID is found, XST_INVALID_PARAM
* otherwise.
*
* @note None
*
****************************************************************************/
XStatus XPm_GetClockParentBySelect(const enum XPmClock clockId,
const u32 select,
enum XPmClock* const parentId)
{
const XPmClockModel* const clk = XPm_GetClockById(clockId);
XStatus status = XST_INVALID_PARAM;
u32 i;
if ((NULL == clk) || (NULL == clk->mux)) {
goto done;
}
if (NULL == clk->mux->inputs) {
/* MIO mux */
if (select <= 0x4DU) {
*parentId = PM_CLOCK_EXT_MIO0;
*parentId += select;
status = XST_SUCCESS;
}
/* else select parameter is invalid (out of scope) */
goto done;
}
for (i = 0U; i < clk->mux->size; i++) {
if (clk->mux->inputs[i].select == select) {
*parentId = clk->mux->inputs[i].clkIn;
status = XST_SUCCESS;
break;
}
}
done:
return status;
}
/****************************************************************************/
/**
* @brief Get mux select value for given clock and clock parent IDs
*
* @param clockId ID of the target clock
* @param parentId ID of the parent clock
* @param select Location to store mux select value
*
* @return Returns XST_SUCCESS if select value is found, XST_INVALID_PARAM
* otherwise.
*
* @note None
*
****************************************************************************/
XStatus XPm_GetSelectByClockParent(const enum XPmClock clockId,
const enum XPmClock parentId,
u32* const select)
{
const XPmClockModel* const clk = XPm_GetClockById(clockId);
XStatus status = XST_INVALID_PARAM;
u32 i;
if ((NULL == clk) || (NULL == clk->mux)) {
goto done;
}
if (NULL == clk->mux->inputs) {
/* MIO mux */
u32 mioSel = parentId - PM_CLOCK_EXT_MIO0;
if (mioSel <= 0x4DU) {
*select = mioSel;
status = XST_SUCCESS;
}
/* else parentId parameter is invalid (out of scope) */
goto done;
}
for (i = 0U; i < clk->mux->size; i++) {
if (clk->mux->inputs[i].clkIn == parentId) {
*select = clk->mux->inputs[i].select;
status = XST_SUCCESS;
break;
}
}
done:
return status;
}
/****************************************************************************/
/**
* @brief Get number of divider that a given clock has
*
* @param clock ID of the target clock
*
* @return Encoded clock divider types. If the clock ID is invalid zero is
* returned.
*
* @note None
*
****************************************************************************/
u8 XPm_GetClockDivType(const enum XPmClock clock)
{
const XPmClockModel* const clk = XPm_GetClockById(clock);
u8 divs = 0U;
if (NULL == clk) {
goto done;
}
divs = clk->type;
done:
return divs;
}
/****************************************************************************/
/**
* @brief Map effective divider value for given clock on DIV0 and DIV1 dividers
*
* @param clock ID of the target clock
* @param div Effective divider value
* @param div0 Location to store mapped DIV0 value
* @param div1 Location to store mapped DIV1 value
*
* @return Encoded mask of mapped dividers
*
* @note The effective divider value may not be mappable on 2x 6-bit wide
* dividers. This is the case if a given divider value is higher than 6-bit
* divider (requires 2xdividers), but its a prime number (cannot be divided
* to get 2x divider values).
*
****************************************************************************/
u8 XPm_MapDivider(const enum XPmClock clock,
const u32 div,
u32* const div0,
u32* const div1)
{
const XPmClockModel* const clk = XPm_GetClockById(clock);
u32 d0, d1 = 0U;
u8 mapped = 0U;
if ((NULL == clk) || (NULL == div0) || (NULL == div1)) {
goto done;
}
/* Check if clock has no divider */
if (!PM_CLOCK_HAS_DIV0(clk) && !PM_CLOCK_HAS_DIV1(clk)) {
goto done;
}
/* Check if given div value is out of range */
if (((!PM_CLOCK_HAS_DIV1(clk)) && (div > PM_DIV_WIDTH)) ||
(div > PM_2xDIV_WIDTH)) {
goto done;
}
/* Check if divider fits in Div0 only */
if (div <= PM_DIV_WIDTH) {
*div0 = div;
mapped = PM_CLOCK_TYPE_DIV0;
if (PM_CLOCK_HAS_DIV1(clk)) {
*div1 = 1U;
mapped |= PM_CLOCK_TYPE_DIV1;
}
goto done;
}
/* Divider has to be configured using both DIV0 and DIV1 */
for (d0 = 2U; d0 <= ((PM_DIV_WIDTH/2U) + 1U); d0++) {
if (0U == (div % d0)) {
d1 = div / d0;
break;
}
}
/* Check if div is prime number > width (d1 would not be assigned) */
if (0U == d1) {
goto done;
}
*div0 = d0;
*div1 = d1;
mapped = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1;
done:
return mapped;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/xfsbl_csu_dma.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcbr_csu_dma.h
*
* Contains declarations for CSU DMA initialization
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 kc 07/22/14 Initial release
* 2.0 bv 01/29/17 XFSBL_CSU_SSS_SRC_DEST_DMA and
* XFSBL_CSU_SSS_DMA_MASK masks
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XFSBL_CSU_DMA_H
#define XFSBL_CSU_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xfsbl_hw.h"
/**************************** Macros Definitions *****************************/
/**************************** Type Definitions *******************************/
/**************************** Macros Definitions *****************************/
#define XFSBL_CSU_SSS_SRC_SRC_DMA 0x5U
#define XFSBL_CSU_SSS_SRC_DEST_DMA 0x50U
#define XFSBL_CSU_SSS_DMA_MASK 0XF000U
/************************** Function Prototypes ******************************/
u32 XFsbl_CsuDmaInit(void);
#ifdef __cplusplus
}
#endif
#endif /* XFSBL_CSU_DMA_H*/
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pll.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_pll.h"
#include "xpm_psm.h"
#include "xpm_regs.h"
#define CLK_PARENTS_PAYLOAD_LEN 12U
/* Period of time needed to lock the PLL (TODO: measure actual latency) */
#define PM_PLL_LOCKING_TIME 1U
static struct XPm_PllTopology PllTopologies[] =
{
{ TOPOLOGY_GENERIC_PLL, PLLPARAMS, RESET_SHIFT, BYPASS_SHIFT,
GEN_LOCK_SHIFT, GEN_STABLE_SHIFT, GEN_REG3_OFFSET },
{ TOPOLOGY_NOC_PLL, PLLPARAMS, RESET_SHIFT, BYPASS_SHIFT,
NPLL_LOCK_SHIFT, NPLL_STABLE_SHIFT, NPLL_REG3_OFFSET },
};
XStatus XPmClockPll_AddNode(u32 Id, u32 ControlReg, u8 TopologyType,
u16 *Offsets, u32 PowerDomainId, u8 ClkFlags)
{
XStatus Status = XST_FAILURE;
XPm_PllClockNode *PllClkPtr;
if (NULL != XPmClock_GetById(Id)) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
if (TopologyType!=TOPOLOGY_GENERIC_PLL && TopologyType!=TOPOLOGY_NOC_PLL) {
Status = XST_INVALID_PARAM;
goto done;
}
PllClkPtr = XPm_AllocBytes(sizeof(XPm_PllClockNode));
if (PllClkPtr == NULL) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
XPmNode_Init(&PllClkPtr->ClkNode.Node, Id, (u8)PM_PLL_STATE_SUSPENDED, 0);
PllClkPtr->ClkNode.Node.BaseAddress = ControlReg;
PllClkPtr->ClkNode.ClkHandles = NULL;
PllClkPtr->ClkNode.UseCount = 0;
PllClkPtr->ClkNode.NumParents = 1;
PllClkPtr->ClkNode.Flags = ClkFlags;
PllClkPtr->Topology = &PllTopologies[TopologyType-TOPOLOGY_GENERIC_PLL];
PllClkPtr->StatusReg = ControlReg + Offsets[0];
PllClkPtr->ConfigReg = ControlReg + Offsets[1];
PllClkPtr->FracConfigReg = ControlReg + Offsets[2];
Status = XPmClock_SetById(Id, (XPm_ClockNode *)PllClkPtr);
if (XST_SUCCESS != Status) {
goto done;
}
if (((u32)XPM_NODECLASS_POWER != NODECLASS(PowerDomainId)) ||
((u32)XPM_NODESUBCL_POWER_DOMAIN != NODESUBCLASS(PowerDomainId))) {
PllClkPtr->ClkNode.PwrDomain = NULL;
goto done;
}
PllClkPtr->ClkNode.PwrDomain = XPmPower_GetById(PowerDomainId);
if (NULL == PllClkPtr->ClkNode.PwrDomain) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
done:
return Status;
}
XStatus XPmClockPll_AddParent(u32 Id, u32 *Parents, u8 NumParents)
{
XStatus Status = XST_FAILURE;
XPm_PllClockNode *PllPtr = (XPm_PllClockNode *)XPmClock_GetById(Id);
if (PllPtr == NULL) {
Status = XST_INVALID_PARAM;
goto done;
}
if (PllPtr->ClkNode.NumParents == 1U && NumParents != 1U) {
Status = XST_INVALID_PARAM;
goto done;
} else {
PllPtr->ClkNode.ParentIdx = (u16)(NODEINDEX(Parents[0]));
Status = XST_SUCCESS;
}
done:
return Status;
}
XStatus XPmClockPll_SetMode(XPm_PllClockNode *Pll, u32 Mode)
{
XStatus Status = XST_FAILURE;
u32 Val = 0;
if ((u32)PM_PLL_MODE_FRACTIONAL == Mode) {
/* Check if fractional value has been set */
Status = XPmClockPll_GetParam(Pll, (u32)PM_PLL_PARAM_ID_DATA, &Val);
if ((XST_SUCCESS != Status) || (0U == Val)) {
Status = XST_FAILURE;
goto done;
}
}
Status = XPmClockPll_Reset(Pll, PLL_RESET_ASSERT);
if (XST_SUCCESS != Status) {
goto done;
}
if ((u32)PM_PLL_MODE_RESET == Mode) {
Status = XST_SUCCESS;
goto done;
} else if ((u32)PM_PLL_MODE_FRACTIONAL == Mode) {
/* Enable fractional mode */
XPm_RMW32(Pll->FracConfigReg, PLL_FRAC_CFG_ENABLED_MASK,
PLL_FRAC_CFG_ENABLED_MASK);
} else if ((u32)PM_PLL_MODE_INTEGER == Mode) {
/* Disable fractional mode */
XPm_RMW32(Pll->FracConfigReg, PLL_FRAC_CFG_ENABLED_MASK, 0);
} else {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmClockPll_Reset(Pll, PLL_RESET_RELEASE);
done:
if (XST_SUCCESS == Status) {
Pll->PllMode = (u8)Mode;
}
return Status;
}
XStatus XPmClockPll_GetMode(XPm_PllClockNode *Pll, u32 *Mode)
{
u32 Val;
XStatus Status = XST_FAILURE;
XPm_Power *PowerDomain = Pll->ClkNode.PwrDomain;
if ((u8)XPM_POWER_STATE_ON != PowerDomain->Node.State) {
Status = XST_NO_ACCESS;
goto done;
}
Val = XPm_Read32(Pll->ClkNode.Node.BaseAddress);
if (0U != (Val & BIT32(Pll->Topology->ResetShift))) {
*Mode = (u32)PM_PLL_MODE_RESET;
} else {
Val = XPm_Read32(Pll->FracConfigReg);
if (0U != (Val & PLL_FRAC_CFG_ENABLED_MASK)) {
*Mode = (u32)PM_PLL_MODE_FRACTIONAL;
} else {
*Mode = (u32)PM_PLL_MODE_INTEGER;
}
}
Pll->PllMode = (u8)(*Mode);
Status = XST_SUCCESS;
done:
return Status;
}
static void XPm_PllSaveContext(XPm_PllClockNode* Pll)
{
/* Save register setting */
Pll->Context.Ctrl = XPm_Read32(Pll->ClkNode.Node.BaseAddress);
Pll->Context.Cfg = XPm_Read32(Pll->ConfigReg);
Pll->Context.Frac = XPm_Read32(Pll->FracConfigReg);
Pll->Context.Flag |= PM_PLL_CONTEXT_SAVED;
}
static void XPm_PllRestoreContext(XPm_PllClockNode* Pll)
{
XPm_Write32(Pll->ClkNode.Node.BaseAddress, Pll->Context.Ctrl);
XPm_Write32(Pll->ConfigReg, Pll->Context.Cfg);
XPm_Write32(Pll->FracConfigReg, Pll->Context.Frac);
Pll->Context.Flag &= (u8)(~PM_PLL_CONTEXT_SAVED);
}
static void XPm_PllClearLockError(XPm_PllClockNode* Pll)
{
XPm_Psm *Psm = (XPm_Psm *)XPmDevice_GetById(PM_DEV_PSM_PROC);
if (NULL != Psm) {
if (PM_CLK_APU_PLL == Pll->ClkNode.Node.Id) {
XPm_Write32(Psm->PsmGlobalBaseAddr + PSM_ERR1_STATUS_OFFSET,
PSM_ERR1_STATUS_APLL_LOCK_MASK);
} else if (PM_CLK_RPU_PLL == Pll->ClkNode.Node.Id) {
XPm_Write32(Psm->PsmGlobalBaseAddr + PSM_ERR1_STATUS_OFFSET,
PSM_ERR1_STATUS_RPLL_LOCK_MASK);
} else {
/* Required due to MISRA */
}
}
}
XStatus XPmClockPll_Suspend(XPm_PllClockNode *Pll)
{
XStatus Status = XST_FAILURE;
XPm_PllSaveContext(Pll);
/* If PLL is not already in reset, bypass it and put in reset/pwrdn */
if (PM_PLL_STATE_RESET != Pll->ClkNode.Node.State) {
Status = XPmClockPll_Reset(Pll, PLL_RESET_ASSERT);
if (XST_SUCCESS != Status) {
goto done;
}
}
Pll->ClkNode.Node.State = PM_PLL_STATE_SUSPENDED;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClockPll_Resume(XPm_PllClockNode *Pll)
{
XStatus Status = XST_FAILURE;
if (0U != (Pll->Context.Flag & PM_PLL_CONTEXT_SAVED)) {
XPm_PllRestoreContext(Pll);
}
/* By saved configuration PLL is in reset, leave it as is */
if (0U != (Pll->Context.Ctrl & BIT32(Pll->Topology->ResetShift))) {
Pll->ClkNode.Node.State = PM_PLL_STATE_RESET;
Status = XST_SUCCESS;
} else {
Status = XPmClockPll_Reset(Pll, PLL_RESET_RELEASE);
}
return Status;
}
XStatus XPmClockPll_Request(u32 PllId)
{
XStatus Status = XST_FAILURE;
XPm_PllClockNode *Pll = (XPm_PllClockNode *)XPmClock_GetById(PllId);
if (Pll == NULL) {
Status = XST_INVALID_PARAM;
goto done;
}
XPm_Power *PowerDomain = Pll->ClkNode.PwrDomain;
if ((0U == Pll->ClkNode.UseCount) && (NULL != PowerDomain)) {
Status = PowerDomain->HandleEvent(&PowerDomain->Node,
XPM_POWER_EVENT_PWR_UP);
if (XST_SUCCESS != Status) {
goto done;
}
}
Pll->ClkNode.UseCount++;
/* If the PLL is suspended it needs to be resumed first */
if (Pll->ClkNode.Node.State == PM_PLL_STATE_SUSPENDED) {
Status = XPmClockPll_Resume(Pll);
}
else if (Pll->ClkNode.Node.State == PM_PLL_STATE_RESET) {
Status = XPmClockPll_Reset(Pll, PLL_RESET_RELEASE);
} else {
Status = XST_SUCCESS;
}
done:
return Status;
}
XStatus XPmClockPll_Release(u32 PllId)
{
XStatus Status = XST_FAILURE;
XPm_PllClockNode *Pll = (XPm_PllClockNode *)XPmClock_GetById(PllId);
if (Pll == NULL) {
Status = XST_INVALID_PARAM;
goto done;
}
Pll->ClkNode.UseCount--;
/**
* Do not suspend the PLL if its use count goes to 0 because it may
* possible that IOU_SWITCH of other domain is using this PLL.
* Just decrement its parent use count and PLL will be suspended
* when its power domain goes off.
*/
XPm_Power *PowerDomain = Pll->ClkNode.PwrDomain;
if ((0U == Pll->ClkNode.UseCount) && (NULL != PowerDomain)) {
Status = PowerDomain->HandleEvent(&PowerDomain->Node,
XPM_POWER_EVENT_PWR_DOWN);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClockPll_Reset(XPm_PllClockNode *Pll, uint8_t Flags)
{
XStatus Status = XST_FAILURE;
u32 ControlReg = Pll->ClkNode.Node.BaseAddress;
if (0U != (Flags & PLL_RESET_ASSERT)) {
/* Bypass PLL before putting it into the reset */
XPm_RMW32(ControlReg, BIT32(Pll->Topology->BypassShift),
BIT32(Pll->Topology->BypassShift));
/* Power down PLL (= reset PLL) */
XPm_RMW32(ControlReg, BIT32(Pll->Topology->ResetShift),
BIT32(Pll->Topology->ResetShift));
Pll->ClkNode.Node.State = PM_PLL_STATE_RESET;
if ((PLATFORM_VERSION_SILICON == Platform) &&
(PLATFORM_VERSION_SILICON_ES1 != PlatformVersion)) {
/*
* The value of the CRX.XPLL_REG3.CP_RES_H must be set
* to 0x1 while the PLL is in reset for ES2 and forward
*/
u32 Reg;
if ((u32)XPM_NODEIDX_CLK_PMC_PLL ==
NODEINDEX(Pll->ClkNode.Node.Id)) {
Reg = ((ControlReg & (0xFFFFFF00U)) +
PPLL_REG3_OFFSET);
} else {
Reg = ((ControlReg & (0xFFFFFF00U)) +
(Pll->Topology->PllReg3Offset));
}
XPm_RMW32(Reg, BITNMASK(PLL_REG3_CP_RES_H_SHIFT,
PLL_REG3_CP_RES_H_WIDTH),
0x1UL << PLL_REG3_CP_RES_H_SHIFT);
}
}
if (0U != (Flags & PLL_RESET_RELEASE)) {
/* Deassert the reset */
XPm_RMW32(ControlReg, BIT32(Pll->Topology->ResetShift),
~BIT32(Pll->Topology->ResetShift));
/* Poll status register for the lock */
Status = XPm_PollForMask(Pll->StatusReg, BIT32(Pll->Topology->LockShift),
PLL_LOCK_TIMEOUT);
/* Deassert bypass if the PLL locked */
if (XST_SUCCESS == Status) {
XPm_RMW32(ControlReg, BIT32(Pll->Topology->BypassShift),
~BIT32(Pll->Topology->BypassShift));
Pll->ClkNode.Node.State = PM_PLL_STATE_LOCKED;
/**
* PLL lock error source needs to be disabled before PLL suspend
* and re-enable after PLL lock which can be done by disabling
* interrupt from PMC global module but it is also disabling
* another error interrupts. So another way is to clear the PLL
* error lock status once PLL is locked after resume.
*/
XPm_PllClearLockError(Pll);
} else {
goto done;
}
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClockPll_SetParam(XPm_PllClockNode *Pll, u32 Param, u32 Value)
{
XStatus Status = XST_FAILURE;
XPm_PllParam *PtrParam;
u32 Mask, ParamValue, Reg = 0;
if (Param >= (u32)PM_PLL_PARAM_MAX) {
Status = XST_INVALID_PARAM;
goto done;
}
PtrParam = &Pll->Topology->ConfigParams[Param];
if (Value > BITMASK(PtrParam->Width)) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Allow config change only if PLL is in reset mode */
if (Pll->ClkNode.Node.State != PM_PLL_STATE_RESET) {
/*
* TODO - revisit it to allow subsystem CDO
* re-parsing which re-sets PLL parameters.
*/
PmInfo("Warning: Setting PLL parameter while not in reset state.\r\n");
Status = XST_SUCCESS;
goto done;
}
Mask = BITNMASK(PtrParam->Shift,PtrParam->Width);
ParamValue = Value << PtrParam->Shift;
switch (Param) {
case (u32)PM_PLL_PARAM_ID_DIV2:
case (u32)PM_PLL_PARAM_ID_FBDIV:
Reg = Pll->ClkNode.Node.BaseAddress;
Status = XST_SUCCESS;
break;
case (u32)PM_PLL_PARAM_ID_DATA:
Reg = Pll->FracConfigReg;
Status = XST_SUCCESS;
break;
case (u32)PM_PLL_PARAM_ID_PRE_SRC:
case (u32)PM_PLL_PARAM_ID_POST_SRC:
case (u32)PM_PLL_PARAM_ID_LOCK_DLY:
case (u32)PM_PLL_PARAM_ID_LOCK_CNT:
case (u32)PM_PLL_PARAM_ID_LFHF:
case (u32)PM_PLL_PARAM_ID_CP:
case (u32)PM_PLL_PARAM_ID_RES:
Reg = Pll->ConfigReg;
Status = XST_SUCCESS;
break;
default:
Status = XST_FAILURE;
break;
}
if (XST_SUCCESS == Status) {
XPm_RMW32(Reg, Mask, ParamValue);
}
done:
return Status;
}
XStatus XPmClockPll_GetParam(XPm_PllClockNode *Pll, u32 Param, u32 *Val)
{
XStatus Status = XST_FAILURE;
XPm_PllParam *PtrParam;
u32 Shift, Mask, Reg = 0;
XPm_Power *PowerDomain = Pll->ClkNode.PwrDomain;
if ((u32)XPM_POWER_STATE_ON != PowerDomain->Node.State) {
Status = XST_NO_ACCESS;
goto done;
}
if (Param >= (u32)PM_PLL_PARAM_MAX) {
Status = XST_INVALID_PARAM;
goto done;
}
PtrParam = &Pll->Topology->ConfigParams[Param];
Mask = BITNMASK(PtrParam->Shift, PtrParam->Width);
Shift = PtrParam->Shift;
switch (Param) {
case (u32)PM_PLL_PARAM_ID_DIV2:
case (u32)PM_PLL_PARAM_ID_FBDIV:
Reg = Pll->ClkNode.Node.BaseAddress;
Status = XST_SUCCESS;
break;
case (u32)PM_PLL_PARAM_ID_DATA:
Reg = Pll->FracConfigReg;
Status = XST_SUCCESS;
break;
case (u32)PM_PLL_PARAM_ID_PRE_SRC:
case (u32)PM_PLL_PARAM_ID_POST_SRC:
case (u32)PM_PLL_PARAM_ID_LOCK_DLY:
case (u32)PM_PLL_PARAM_ID_LOCK_CNT:
case (u32)PM_PLL_PARAM_ID_LFHF:
case (u32)PM_PLL_PARAM_ID_CP:
case (u32)PM_PLL_PARAM_ID_RES:
Reg = Pll->ConfigReg;
Status = XST_SUCCESS;
break;
default:
Status = XST_FAILURE;
break;
}
if (XST_SUCCESS == Status) {
*Val = (XPm_Read32(Reg) & Mask) >> Shift;
}
done:
return Status;
}
int XPmClockPll_QueryMuxSources(u32 Id, u32 Index, u32 *Resp)
{
int Status = XST_FAILURE;
XPm_PllClockNode *PllPtr = (XPm_PllClockNode *)XPmClock_GetById(Id);
if (PllPtr == NULL) {
Status = XST_INVALID_PARAM;
goto done;
}
(void)memset(Resp, 0, CLK_PARENTS_PAYLOAD_LEN);
if (Index != 0U) {
Status = XST_INVALID_PARAM;
goto done;
}
Resp[0] = PllPtr->ClkNode.ParentIdx;
Resp[1] = 0xFFFFFFFFU;
Status = XST_SUCCESS;
done:
return Status;
}
int XPmClockPll_GetWakeupLatency(const u32 Id, u32 *Latency)
{
int Status = XST_SUCCESS;
XPm_PllClockNode *Pll = (XPm_PllClockNode *)XPmClock_GetById(Id);
u32 Lat = 0;
*Latency = 0;
if (NULL == Pll) {
Status = XST_INVALID_PARAM;
goto done;
}
if (PM_PLL_STATE_LOCKED == Pll->ClkNode.Node.State) {
goto done;
}
*Latency += PM_PLL_LOCKING_TIME;
Status = XPmPower_GetWakeupLatency(Pll->ClkNode.PwrDomain->Node.Id,
&Lat);
if (XST_SUCCESS == Status) {
*Latency += Lat;
}
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_device.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xplmi_dma.h"
#include "xpm_device.h"
#include "xpm_core.h"
#include "xpm_regs.h"
#include "xpm_prot.h"
#include "xpm_rpucore.h"
#include "xpm_notifier.h"
#include "xpm_api.h"
#include "xpm_pmc.h"
#include "xpm_pslpdomain.h"
#include "xpm_requirement.h"
/** PSM RAM Base address */
#define XPM_PSM_RAM_BASE_ADDR (0xFFC00000U)
#define XPM_PSM_RAM_SIZE (0x40000U)
#define SD_DLL_DIV_MAP_RESET_VAL (0x50505050U)
static const char *PmDevStates[] = {
"UNUSED",
"RUNNING",
"PWR_ON",
"CLK_ON",
"RST_OFF",
"RST_ON",
"CLK_OFF",
"PWR_OFF",
"SUSPENDING",
"RUNTIME_SUSPEND",
};
static const char *PmDevEvents[] = {
"BRINGUP_ALL",
"BRINGUP_CLKRST",
"SHUTDOWN",
"TIMER",
};
static u32 IpiMasks[][2] = {
{ PM_DEV_IPI_0, IPI_0_MASK },
{ PM_DEV_IPI_1, IPI_1_MASK },
{ PM_DEV_IPI_2, IPI_2_MASK },
{ PM_DEV_IPI_3, IPI_3_MASK },
{ PM_DEV_IPI_4, IPI_4_MASK },
{ PM_DEV_IPI_5, IPI_5_MASK },
{ PM_DEV_IPI_6, IPI_6_MASK },
};
static XPm_DeviceOps PmDeviceOps;
static XPm_Device *PmDevices[(u32)XPM_NODEIDX_DEV_MAX];
static XPm_Device *PmPlDevices[(u32)XPM_NODEIDX_DEV_PLD_MAX];
static u32 PmNumDevices;
static u32 PmNumPlDevices;
static const XPm_StateCap XPmGenericDeviceStates[] = {
{
.State = (u8)XPM_DEVSTATE_UNUSED,
.Cap = XPM_MIN_CAPABILITY,
}, {
.State = (u8)XPM_DEVSTATE_RUNTIME_SUSPEND,
.Cap = (u32)PM_CAP_UNUSABLE,
}, {
.State = (u8)XPM_DEVSTATE_RUNNING,
.Cap = XPM_MAX_CAPABILITY | (u32)PM_CAP_UNUSABLE,
},
};
static const XPm_StateTran XPmGenericDevTransitions[] = {
{
.FromState = (u32)XPM_DEVSTATE_RUNNING,
.ToState = (u32)XPM_DEVSTATE_UNUSED,
.Latency = XPM_DEF_LATENCY,
}, {
.FromState = (u32)XPM_DEVSTATE_UNUSED,
.ToState = (u32)XPM_DEVSTATE_RUNNING,
.Latency = XPM_DEF_LATENCY,
}, {
.FromState = (u32)XPM_DEVSTATE_RUNTIME_SUSPEND,
.ToState = (u32)XPM_DEVSTATE_UNUSED,
.Latency = XPM_DEF_LATENCY,
}, {
.FromState = (u32)XPM_DEVSTATE_RUNTIME_SUSPEND,
.ToState = (u32)XPM_DEVSTATE_RUNNING,
.Latency = XPM_DEF_LATENCY,
}, {
.FromState = (u32)XPM_DEVSTATE_UNUSED,
.ToState = (u32)XPM_DEVSTATE_RUNTIME_SUSPEND,
.Latency = XPM_DEF_LATENCY,
}, {
.FromState = (u32)XPM_DEVSTATE_RUNNING,
.ToState = (u32)XPM_DEVSTATE_RUNTIME_SUSPEND,
.Latency = XPM_DEF_LATENCY,
},
};
static XPm_Requirement *FindReqm(XPm_Device *Device, XPm_Subsystem *Subsystem)
{
XPm_Requirement *Reqm = NULL;
Reqm = Device->Requirements;
while (NULL != Reqm) {
if (Reqm->Subsystem == Subsystem) {
break;
}
Reqm = Reqm->NextSubsystem;
}
return Reqm;
}
struct XPm_Reqm *XPmDevice_FindRequirement(const u32 DeviceId, const u32 SubsystemId)
{
XPm_Device *Device = XPmDevice_GetById(DeviceId);
XPm_Subsystem *Subsystem = XPmSubsystem_GetById(SubsystemId);
XPm_Requirement *Reqm = NULL;
if (NULL == Device || NULL == Subsystem) {
goto done;
}
Reqm = FindReqm(Device, Subsystem);
done:
return Reqm;
}
static XStatus SetDeviceNode(u32 Id, XPm_Device *Device)
{
XStatus Status = XST_INVALID_PARAM;
u32 NodeIndex = NODEINDEX(Id);
/*
* We assume that the Node ID class, subclass and type has _already_
* been validated before, so only check bounds here against index
*/
if ((NULL != Device) && ((u32)XPM_NODEIDX_DEV_MAX > NodeIndex)) {
PmDevices[NodeIndex] = Device;
PmNumDevices++;
Status = XST_SUCCESS;
}
return Status;
}
static int SetPlDeviceNode(u32 Id, XPm_Device *Device)
{
int Status = XST_INVALID_PARAM;
u32 NodeIndex = NODEINDEX(Id);
/*
* Node ID class, subclass and type should _already_ been validated
* before, so only check bounds here against index.
*/
if ((NULL != Device) && ((u32)XPM_NODEIDX_DEV_PLD_MAX > NodeIndex)) {
PmPlDevices[NodeIndex] = Device;
PmNumPlDevices++;
Status = XST_SUCCESS;
}
return Status;
}
/****************************************************************************/
/**
* @brief Get subsystem ID of processor
*
* @param Device Processor whose subsystem needs to found
*
* @return Subsystem ID of that processor
*
* @note Core must be requested from single subsystem. If it is
* requested from multiple subsystems then it returns only one
* subsystem ID and if it is not requested from any subsystem
* then this function returns maximum subsystem ID which is
* invalid.
*
****************************************************************************/
u32 XPmDevice_GetSubsystemIdOfCore(XPm_Device *Device)
{
XPm_Requirement *Reqm;
XPm_Subsystem *Subsystem = NULL;
u32 Idx, SubSystemId;
u32 MaxSubsysIdx = XPmSubsystem_GetMaxSubsysIdx();
for (Idx = 0; Idx <= MaxSubsysIdx; Idx++) {
Subsystem = XPmSubsystem_GetByIndex(Idx);
if (NULL != Subsystem) {
Reqm = FindReqm(Device, Subsystem);
if ((NULL != Reqm) && (1U == Reqm->Allocated)) {
break;
}
}
}
if (MaxSubsysIdx < Idx) {
SubSystemId = INVALID_SUBSYSID;
} else {
SubSystemId = Subsystem->Id;
}
return SubSystemId;
}
/****************************************************************************/
/**
* @brief Get maximum of all requested capabilities of device
* @param Device Device whose maximum required capabilities should be
* determined
*
* @return 32bit value encoding the capabilities
*
* @note None
*
****************************************************************************/
static u32 GetMaxCapabilities(const XPm_Device* const Device)
{
XPm_Requirement* Reqm = Device->Requirements;
u32 MaxCaps = 0U;
while (NULL != Reqm) {
MaxCaps |= Reqm->Curr.Capabilities;
Reqm = Reqm->NextSubsystem;
}
return MaxCaps;
}
/****************************************************************************/
/**
* @brief This function checks device capability
*
* @param Device Device for capability check
* @param Caps Capability
*
* @return XST_SUCCESS if desired Caps is available in Device
*
* @note None
*
****************************************************************************/
XStatus XPm_CheckCapabilities(XPm_Device *Device, u32 Caps)
{
u32 Idx;
XStatus Status = XST_FAILURE;
if (NULL == Device->DeviceFsm) {
goto done;
}
for (Idx = 0U; Idx < Device->DeviceFsm->StatesCnt; Idx++) {
/* Find the first state that contains all capabilities */
if ((Caps & Device->DeviceFsm->States[Idx].Cap) == Caps) {
Status = XST_SUCCESS;
break;
}
}
done:
if (Status != XST_SUCCESS) {
Status = XST_NO_FEATURE;
}
return Status;
}
static u32 IsRunning(XPm_Device *Device)
{
u32 Running = 0;
XPm_Requirement *Reqm = Device->Requirements;
while (NULL != Reqm) {
if (Reqm->Allocated > 0U) {
if (Reqm->Curr.Capabilities > 0U) {
Running = 1;
break;
}
}
Reqm = Reqm->NextSubsystem;
}
return Running;
}
XStatus XPmDevice_BringUp(XPm_Device *Device)
{
XStatus Status = XPM_ERR_DEVICE_BRINGUP;
if (NULL == Device->Power) {
goto done;
}
/* Check if device is already up and running */
if (Device->Node.State == (u8)XPM_DEVSTATE_RUNNING) {
Status = XST_SUCCESS;
goto done;
}
Device->WfPwrUseCnt = Device->Power->UseCount + 1U;
Status = Device->Power->HandleEvent(&Device->Power->Node,
XPM_POWER_EVENT_PWR_UP);
if (XST_SUCCESS == Status) {
Device->Node.State = (u8)XPM_DEVSTATE_PWR_ON;
/* Todo: Start timer to poll the power node */
/* Hack */
Status = Device->HandleEvent(&Device->Node, XPM_DEVEVENT_TIMER);
}
done:
return Status;
}
static XStatus SetClocks(XPm_Device *Device, u32 Enable)
{
XStatus Status = XST_FAILURE;
XPm_ClockHandle *ClkHandle = Device->ClkHandles;
/* Enable all the clock gates, skip over others */
if (1U == Enable) {
Status = XPmClock_Request(ClkHandle);
} else {
Status = XPmClock_Release(ClkHandle);
}
return Status;
}
static XStatus ResetSdDllRegs(XPm_Device *Device)
{
XStatus Status = XST_FAILURE;
u32 Value;
u32 BaseAddress;
XPm_Pmc *Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
if (NULL == Pmc) {
Status = XPM_INVALID_DEVICEID;
goto done;
}
BaseAddress = Pmc->PmcIouSlcrBaseAddr;
if (PM_DEV_SDIO_0 == Device->Node.Id) {
PmIn32(BaseAddress + PMC_IOU_SLCR_SD0_DLL_DIV_MAP0_OFFSET,
Value);
PmOut32(BaseAddress + PMC_IOU_SLCR_SD0_DLL_DIV_MAP0_OFFSET,
SD_DLL_DIV_MAP_RESET_VAL);
PmOut32(BaseAddress + PMC_IOU_SLCR_SD0_DLL_DIV_MAP0_OFFSET,
Value);
PmIn32(BaseAddress + PMC_IOU_SLCR_SD0_DLL_DIV_MAP1_OFFSET,
Value);
PmOut32(BaseAddress + PMC_IOU_SLCR_SD0_DLL_DIV_MAP1_OFFSET,
SD_DLL_DIV_MAP_RESET_VAL);
PmOut32(BaseAddress + PMC_IOU_SLCR_SD0_DLL_DIV_MAP1_OFFSET,
Value);
} else if (PM_DEV_SDIO_1 == Device->Node.Id) {
PmIn32(BaseAddress + PMC_IOU_SLCR_SD1_DLL_DIV_MAP0_OFFSET,
Value);
PmOut32(BaseAddress + PMC_IOU_SLCR_SD1_DLL_DIV_MAP0_OFFSET,
SD_DLL_DIV_MAP_RESET_VAL);
PmOut32(BaseAddress + PMC_IOU_SLCR_SD1_DLL_DIV_MAP0_OFFSET,
Value);
PmIn32(BaseAddress + PMC_IOU_SLCR_SD1_DLL_DIV_MAP1_OFFSET,
Value);
PmOut32(BaseAddress + PMC_IOU_SLCR_SD1_DLL_DIV_MAP1_OFFSET,
SD_DLL_DIV_MAP_RESET_VAL);
PmOut32(BaseAddress + PMC_IOU_SLCR_SD1_DLL_DIV_MAP1_OFFSET,
Value);
} else {
/* Required by MISRA */
}
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus HandleDeviceEvent(XPm_Node *Node, u32 Event)
{
XStatus Status = XST_FAILURE;
XPm_Device *Device = (XPm_Device *)Node;
XPm_Core *Core;
PmDbg("State=%s, Event=%s\n\r", PmDevStates[Node->State], PmDevEvents[Event]);
switch(Node->State)
{
case (u8)XPM_DEVSTATE_UNUSED:
if ((u32)XPM_DEVEVENT_BRINGUP_ALL == Event) {
Status = Device->DeviceFsm->EnterState(Device, XPM_DEVSTATE_RUNNING);
} else if ((u32)XPM_DEVEVENT_SHUTDOWN == Event) {
Status = XST_SUCCESS;
} else {
/* Required due to MISRA */
PmDbg("Invalid event type %d\r\n", Event);
}
break;
case (u8)XPM_DEVSTATE_PWR_ON:
if ((u32)XPM_DEVEVENT_TIMER == Event) {
Status = XST_SUCCESS;
if (Device->WfPwrUseCnt == Device->Power->UseCount) {
Node->State = (u8)XPM_DEVSTATE_CLK_ON;
/* Enable clock */
Status = SetClocks(Device, 1U);
if (XST_SUCCESS != Status) {
break;
}
/* Todo: Start timer to poll the clock node */
/* Hack */
Status = Device->HandleEvent(Node, (u32)XPM_DEVEVENT_TIMER);
} else {
/* Todo: Start timer to poll the power node */
}
} else {
Status = XST_DEVICE_BUSY;
}
break;
case (u8)XPM_DEVSTATE_CLK_ON:
if ((u32)XPM_DEVEVENT_TIMER == Event) {
Status = XST_SUCCESS;
/* Todo: Check if clock is enabled */
if (TRUE /* Hack: Clock enabled */) {
Node->State = (u8)XPM_DEVSTATE_RST_OFF;
XPm_PsLpDomain *PsLpd;
PsLpd = (XPm_PsLpDomain *)XPmPower_GetById(PM_POWER_LPD);
if (NULL == PsLpd) {
Status = XST_FAILURE;
break;
}
/*
* Configure ADMA as non-secure so Linux
* can use it.
* TODO: Remove this when security config
* support is added through CDO
*/
if (Device->Node.Id >= PM_DEV_ADMA_0 &&
Device->Node.Id <= PM_DEV_ADMA_7) {
XPm_Out32(PsLpd->LpdSlcrSecureBaseAddr +
LPD_SLCR_SECURE_WPROT0_OFFSET, 0x0);
XPm_Out32(PsLpd->LpdSlcrSecureBaseAddr +
LPD_SLCR_SECURE_ADMA_0_OFFSET +
(Device->Node.Id - PM_DEV_ADMA_0) * 4U, 0x1);
XPm_Out32(PsLpd->LpdSlcrSecureBaseAddr +
LPD_SLCR_SECURE_WPROT0_OFFSET, 0x1);
}
/* De-assert reset for peripheral devices */
if ((u32)XPM_NODESUBCL_DEV_PERIPH ==
NODESUBCLASS(Device->Node.Id)) {
Status = XPmDevice_Reset(Device,
PM_RESET_ACTION_RELEASE);
if (XST_SUCCESS != Status) {
break;
}
/*
* As per EDT-997700 SD/eMMC DLL modes are failing after
* SD controller reset. Reset SD_DLL_MAP registers after
* reset release as a workaround.
*/
if ((PM_DEV_SDIO_0 == Device->Node.Id) ||
(PM_DEV_SDIO_1 == Device->Node.Id)) {
Status = ResetSdDllRegs(Device);
if (XST_SUCCESS != Status) {
break;
}
}
} else if(Node->Id == PM_DEV_RPU0_0 || Node->Id == PM_DEV_RPU0_1) {
/*RPU has a special handling */
Status = XPmRpuCore_Halt(Device);
if (XST_SUCCESS != Status) {
break;
}
} else if(Node->Id == PM_DEV_PSM_PROC) {
/* Ecc initialize PSM RAM*/
Status = XPlmi_EccInit(XPM_PSM_RAM_BASE_ADDR, XPM_PSM_RAM_SIZE);
if (XST_SUCCESS != Status) {
break;
}
} else {
/* Required due to MISRA */
PmDbg("Invalid node id 0x%x\r\n", Node->Id);
}
/* Todo: Start timer to poll the reset node */
/* Hack */
Status = Device->HandleEvent(Node, (u32)XPM_DEVEVENT_TIMER);
} else {
/* Todo: Start timer to poll the clock node */
}
} else {
Status = XST_DEVICE_BUSY;
}
break;
case (u8)XPM_DEVSTATE_RST_OFF:
if ((u32)XPM_DEVEVENT_TIMER == Event) {
Status = XST_SUCCESS;
/* Todo: Check if reset is de-asserted */
if (TRUE /* Hack: Reset de-asserted */) {
XPm_RequiremntUpdate(Device->PendingReqm);
Node->State = (u8)XPM_DEVSTATE_RUNNING;
Device->PendingReqm = NULL;
} else {
/* Todo: Start timer to poll the reset node */
}
} else {
Status = XST_DEVICE_BUSY;
}
break;
case (u8)XPM_DEVSTATE_RUNNING:
if ((u32)XPM_DEVEVENT_BRINGUP_ALL == Event) {
Status = XPmDevice_BringUp(Device);
} else if ((u32)XPM_DEVEVENT_BRINGUP_CLKRST == Event) {
Node->State = (u8)XPM_DEVSTATE_CLK_ON;
/* Enable all clocks */
Status = SetClocks(Device, 1U);
if (XST_SUCCESS != Status) {
break;
}
/* Todo: Start timer to poll the clock node */
/* Hack */
Status = Device->HandleEvent(Node, (u32)XPM_DEVEVENT_TIMER);
} else if ((u32)XPM_DEVEVENT_SHUTDOWN == Event) {
if ((u32)XPM_NODECLASS_DEVICE == (NODECLASS(Device->Node.Id)) &&
((u32)XPM_NODESUBCL_DEV_CORE == NODESUBCLASS(Device->Node.Id))) {
Core = (XPm_Core *)XPmDevice_GetById(Device->Node.Id);
if ((NULL != Core) && (NULL != Core->CoreOps)
&& (NULL != Core->CoreOps->PowerDown)) {
Status = Core->CoreOps->PowerDown(Core);
break;
}
}
Node->State = (u8)XPM_DEVSTATE_RST_ON;
/* Assert reset for peripheral devices */
if ((u32)XPM_NODESUBCL_DEV_PERIPH ==
NODESUBCLASS(Device->Node.Id)) {
Status = XPmDevice_Reset(Device,
PM_RESET_ACTION_ASSERT);
if (XST_SUCCESS != Status) {
break;
}
}
/* Todo: Start timer to poll reset node */
/* Hack */
Status = Device->HandleEvent(Node, (u32)XPM_DEVEVENT_TIMER);
} else if ((u32)XPM_DEVEVENT_RUNTIME_SUSPEND == Event) {
Node->State = (u8)XPM_DEVSTATE_RUNTIME_SUSPEND;
/* Disable all clocks */
Status = SetClocks(Device, 0U);
if (XST_SUCCESS != Status) {
break;
}
} else {
/* Required by MISRA */
}
break;
case (u8)XPM_DEVSTATE_RST_ON:
if ((u32)XPM_DEVEVENT_TIMER == Event) {
Status = XST_SUCCESS;
/* Todo: Check if reset is asserted */
if (TRUE /* Hack: asserted */) {
Node->State = (u8)XPM_DEVSTATE_CLK_OFF;
/* Disable all clocks */
Status = SetClocks(Device, 0U);
if (XST_SUCCESS != Status) {
break;
}
/* Todo: Start timer to poll clock node */
/* Hack */
Status = Device->HandleEvent(Node, (u32)XPM_DEVEVENT_TIMER);
} else {
/* Todo: Start timer to poll reset node */
}
}
break;
case (u8)XPM_DEVSTATE_CLK_OFF:
if ((u32)XPM_DEVEVENT_TIMER == Event) {
Status = XST_SUCCESS;
/* Todo: Check if clock is disabled */
if (TRUE /* Hack: Clock disabled */) {
Node->State = (u8)XPM_DEVSTATE_PWR_OFF;
Device->WfPwrUseCnt = Device->Power->UseCount - 1U;
Status = Device->Power->HandleEvent(
&Device->Power->Node, (u32)XPM_POWER_EVENT_PWR_DOWN);
/* Todo: Start timer to poll power node use count */
/* Hack */
Status = Device->HandleEvent(Node, (u32)XPM_DEVEVENT_TIMER);
} else {
/* Todo: Start timer to poll clock node */
}
}
break;
case (u8)XPM_DEVSTATE_PWR_OFF:
if ((u32)XPM_DEVEVENT_TIMER == Event) {
Status = XST_SUCCESS;
Device->Node.Flags &= (u8)(~NODE_IDLE_DONE);
if (Device->WfPwrUseCnt == Device->Power->UseCount) {
if (1U == Device->WfDealloc) {
Device->PendingReqm->Allocated = 0;
Device->WfDealloc = 0;
}
if(Device->PendingReqm != NULL) {
XPm_RequiremntUpdate(Device->PendingReqm);
Device->PendingReqm = NULL;
}
if (0U == IsRunning(Device)) {
Node->State = (u8)XPM_DEVSTATE_UNUSED;
} else {
Node->State = (u8)XPM_DEVSTATE_RUNNING;
}
} else {
/* Todo: Start timer to poll power node use count */
}
} else if ((u32)XPM_DEVEVENT_SHUTDOWN == Event) {
/* Device is already in power off state */
Status = XST_SUCCESS;
} else {
/* Required due to MISRA */
PmDbg("Invalid event type %d\r\n", Event);
}
break;
case (u8)XPM_DEVSTATE_RUNTIME_SUSPEND:
if ((u32)XPM_DEVEVENT_SHUTDOWN == Event) {
/* Assert reset for peripheral devices */
if ((u32)XPM_NODESUBCL_DEV_PERIPH ==
NODESUBCLASS(Device->Node.Id)) {
Status = XPmDevice_Reset(Device,
PM_RESET_ACTION_ASSERT);
if (XST_SUCCESS != Status) {
break;
}
}
/*
* Change device's state to clock off since all
* clocks are disabled during runtime suspend.
*/
Node->State = (u8)XPM_DEVSTATE_CLK_OFF;
Status = Device->HandleEvent(Node, (u32)XPM_DEVEVENT_TIMER);
} else if ((u32)XPM_DEVEVENT_BRINGUP_ALL == Event) {
/* Enable all clocks */
Status = SetClocks(Device, 1U);
if (XST_SUCCESS != Status) {
break;
}
Node->State = (u8)XPM_DEVSTATE_RUNNING;
} else {
/* Required by MISRA */
}
break;
default:
Status = XPM_INVALID_STATE;
break;
}
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
static XStatus HandleDeviceState(XPm_Device* const Device, const u32 NextState)
{
XStatus Status = XST_FAILURE;
switch (Device->Node.State) {
case (u8)XPM_DEVSTATE_UNUSED:
if ((u32)XPM_DEVSTATE_RUNNING == NextState) {
Status = XPmDevice_BringUp(Device);
} else {
Status = XST_SUCCESS;
}
break;
case (u8)XPM_DEVSTATE_RUNNING:
if ((u32)XPM_DEVSTATE_UNUSED == NextState) {
Status = Device->HandleEvent(&Device->Node,
(u32)XPM_DEVEVENT_SHUTDOWN);
} else if ((u32)XPM_DEVSTATE_RUNTIME_SUSPEND == NextState) {
Status = Device->HandleEvent(&Device->Node,
(u32)XPM_DEVEVENT_RUNTIME_SUSPEND);
} else {
Status = XST_SUCCESS;
}
break;
case (u8)XPM_DEVSTATE_RUNTIME_SUSPEND:
if ((u32)XPM_DEVSTATE_RUNNING == NextState) {
Status = Device->HandleEvent(&Device->Node,
(u32)XPM_DEVEVENT_BRINGUP_ALL);
} else if ((u32)XPM_DEVSTATE_UNUSED == NextState) {
Status = Device->HandleEvent(&Device->Node,
(u32)XPM_DEVEVENT_SHUTDOWN);
} else {
Status = XST_SUCCESS;
}
break;
default:
Status = XPM_INVALID_STATE;
break;
}
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
static const XPm_DeviceFsm XPmGenericDeviceFsm = {
DEFINE_DEV_STATES(XPmGenericDeviceStates),
DEFINE_DEV_TRANS(XPmGenericDevTransitions),
.EnterState = HandleDeviceState,
};
static XStatus Request(XPm_Device *Device, XPm_Subsystem *Subsystem,
u32 Capabilities, const u32 QoS)
{
XStatus Status = XPM_ERR_DEVICE_REQ;
XPm_Requirement *Reqm;
u8 UsagePolicy = 0;
if (((u8)XPM_DEVSTATE_UNUSED != Device->Node.State) &&
((u8)XPM_DEVSTATE_RUNNING != Device->Node.State) &&
((u8)XPM_DEVSTATE_RUNTIME_SUSPEND != Device->Node.State)) {
Status = XST_DEVICE_BUSY;
goto done;
}
/* Check whether this device assigned to the subsystem */
Reqm = FindReqm(Device, Subsystem);
if (NULL == Reqm) {
goto done;
}
if (1U == Reqm->Allocated) {
Status = XST_SUCCESS;
goto done;
}
/* Check whether this device is shareable */
UsagePolicy = Reqm->Flags & REG_FLAGS_USAGE_MASK;
if ((UsagePolicy == (u8)REQ_TIME_SHARED) || (UsagePolicy == (u8)REQ_NONSHARED)) {
//Check if it already requested by other subsystem. If yes, return
XPm_Requirement *NextReqm = Reqm->NextSubsystem;
while (NULL != NextReqm) {
if (1U == NextReqm->Allocated) {
Status = XPM_PM_NODE_USED;
goto done;
}
NextReqm = NextReqm->NextSubsystem;
}
}
/* Allocated device for the subsystem */
Reqm->Allocated = 1U;
Status = Device->DeviceOps->SetRequirement(Device, Subsystem,
Capabilities, QoS);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmProt_Configure(Reqm, 1U);
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
static XStatus SetRequirement(XPm_Device *Device, XPm_Subsystem *Subsystem,
u32 Capabilities, const u32 QoS)
{
XStatus Status = XPM_ERR_SET_REQ;;
XPm_ReqmInfo TempReqm;
if (((u8)XPM_DEVSTATE_UNUSED != Device->Node.State) &&
((u8)XPM_DEVSTATE_RUNNING != Device->Node.State) &&
((u8)XPM_DEVSTATE_RUNTIME_SUSPEND != Device->Node.State)) {
Status = XST_DEVICE_BUSY;
goto done;
}
Device->PendingReqm = FindReqm(Device, Subsystem);
if (NULL == Device->PendingReqm) {
goto done;
}
/*
* If subsystem state is suspending then do not change device's state
* according to capabilities, only schedule requirements by setting
* device's next requirements.
*/
if ((u8)SUSPENDING == Subsystem->State) {
Device->PendingReqm->Next.Capabilities = Capabilities;
Device->PendingReqm->Next.QoS = QoS;
Status = XST_SUCCESS;
goto done;
} else {
/*
* Store current requirements as a backup in case something
* fails.
*/
TempReqm.Capabilities = Device->PendingReqm->Curr.Capabilities;
TempReqm.QoS = Device->PendingReqm->Curr.QoS;
Device->PendingReqm->Curr.Capabilities = Capabilities;
Device->PendingReqm->Curr.QoS = QoS;
}
Status = XPmDevice_UpdateStatus(Device);
if (XST_SUCCESS != Status) {
Device->PendingReqm->Curr.Capabilities = TempReqm.Capabilities;
Device->PendingReqm->Curr.QoS = TempReqm.QoS;
} else if ((u32)PM_CAP_UNUSABLE == Capabilities) {
/* Schedule next requirement to 0 */
Device->PendingReqm->Next.Capabilities = 0U;
Device->PendingReqm->Next.QoS = QoS;
} else {
XPm_RequiremntUpdate(Device->PendingReqm);
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
static XStatus Release(XPm_Device *Device,
XPm_Subsystem *Subsystem)
{
XStatus Status = XPM_ERR_DEVICE_RELEASE;
XPm_Requirement *Reqm;
if (((u8)XPM_DEVSTATE_UNUSED != Device->Node.State) &&
((u8)XPM_DEVSTATE_RUNNING != Device->Node.State) &&
((u8)XPM_DEVSTATE_RUNTIME_SUSPEND != Device->Node.State)) {
Status = XST_DEVICE_BUSY;
goto done;
}
Device->PendingReqm = FindReqm(Device, Subsystem);
if (NULL == Device->PendingReqm) {
goto done;
}
Reqm = Device->PendingReqm;
if (0U == Device->PendingReqm->Allocated) {
Status = XST_SUCCESS;
goto done;
}
Device->WfDealloc = 1U;
Status = Device->DeviceOps->SetRequirement(Device, Subsystem, 0,
XPM_DEF_QOS);
if (XST_SUCCESS != Status) {
Status = XPM_ERR_DEVICE_RELEASE;
goto done;
}
XPmRequirement_Clear(Reqm);
Device->WfDealloc = 0;
Status = XPmProt_Configure(Reqm, 0U);
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
XStatus XPmDevice_Init(XPm_Device *Device,
u32 Id,
u32 BaseAddress,
XPm_Power *Power, XPm_ClockNode * Clock, XPm_ResetNode *Reset)
{
XStatus Status = XPM_ERR_DEVICE_INIT;
if (NULL != XPmDevice_GetById(Id)) {
Status = XST_DEVICE_BUSY;
goto done;
}
XPmNode_Init(&Device->Node, Id, (u8)XPM_DEVSTATE_UNUSED, BaseAddress);
/* Add requirement by default for PMC subsystem */
Status = XPmRequirement_Add(XPmSubsystem_GetByIndex((u32)XPM_NODEIDX_SUBSYS_PMC), Device, (((u32)REQ_ACCESS_SECURE_NONSECURE << REG_FLAGS_SECURITY_OFFSET) | (u32)REQ_NO_RESTRICTION), NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Device->Power = Power;
Device->PendingReqm = NULL;
Device->WfDealloc = 0;
Device->WfPwrUseCnt = 0;
Status = XPmDevice_AddClock(Device, Clock);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDevice_AddReset(Device, Reset);
if (XST_SUCCESS != Status) {
goto done;
}
Device->HandleEvent = HandleDeviceEvent;
PmDeviceOps.Request = Request;
PmDeviceOps.SetRequirement = SetRequirement;
PmDeviceOps.Release = Release;
Device->DeviceOps = &PmDeviceOps;
if (NULL == Device->DeviceFsm) {
Device->DeviceFsm = &XPmGenericDeviceFsm;
}
if ((u32)XPM_NODESUBCL_DEV_PL == NODESUBCLASS(Id)) {
Status = SetPlDeviceNode(Id, Device);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
Status = SetDeviceNode(Id, Device);
if (XST_SUCCESS != Status) {
goto done;
}
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
XStatus XPmDevice_AddClock(XPm_Device *Device, XPm_ClockNode *Clock)
{
XStatus Status = XST_FAILURE;
XPm_ClockHandle *ClkHandle;
if (NULL == Device) {
Status = XPM_ERR_DEVICE;
goto done;
}
if (NULL == Clock) {
Status = XST_SUCCESS;
goto done;
}
ClkHandle = (XPm_ClockHandle *)XPm_AllocBytes(sizeof(XPm_ClockHandle));
if (NULL == ClkHandle) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
ClkHandle->Clock = Clock;
ClkHandle->Device = Device;
/* Prepend the new handle to the device's clock handle list */
ClkHandle->NextClock = Device->ClkHandles;
Device->ClkHandles = ClkHandle;
/* Prepend the new handle to the clock's device handle list */
ClkHandle->NextDevice = Clock->ClkHandles;
Clock->ClkHandles = ClkHandle;
Status = XST_SUCCESS;
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
XStatus XPmDevice_AddReset(XPm_Device *Device, XPm_ResetNode *Reset)
{
XStatus Status = XST_FAILURE;
XPm_ResetHandle *RstHandle;
if (NULL == Device) {
Status = XPM_ERR_DEVICE;
goto done;
}
if (NULL == Reset) {
Status = XST_SUCCESS;
goto done;
}
RstHandle = (XPm_ResetHandle *)XPm_AllocBytes(sizeof(XPm_ResetHandle));
if (NULL == RstHandle) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
RstHandle->Reset = Reset;
RstHandle->Device = Device;
/* Prepend the new handle to the device's reset handle list */
RstHandle->NextReset = Device->RstHandles;
Device->RstHandles = RstHandle;
/* Prepend the new handle to the reset's device handle list */
RstHandle->NextDevice = Reset->RstHandles;
Reset->RstHandles = RstHandle;
Status = XST_SUCCESS;
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
XStatus XPmDevice_Reset(XPm_Device *Device, const XPm_ResetActions Action)
{
XStatus Status = XST_FAILURE;
XPm_ResetHandle *RstHandle, *DeviceHandle;
XPm_ResetNode *Reset;
if (NULL == Device) {
Status = XPM_ERR_DEVICE;
goto done;
}
RstHandle = Device->RstHandles;
if (PM_RESET_ACTION_RELEASE != Action) {
while (NULL != RstHandle) {
Reset = RstHandle->Reset;
DeviceHandle = Reset->RstHandles;
while (NULL != DeviceHandle) {
if ((Device->Node.Id !=
DeviceHandle->Device->Node.Id) &&
((u32)XPM_DEVSTATE_RUNNING ==
DeviceHandle->Device->Node.State)) {
break;
}
DeviceHandle = DeviceHandle->NextDevice;
}
if (NULL == DeviceHandle) {
Status = Reset->Ops->SetState(Reset, Action);
if (XST_SUCCESS != Status) {
goto done;
}
}
RstHandle = RstHandle->NextReset;
}
} else {
while (NULL != RstHandle) {
Status = RstHandle->Reset->Ops->SetState(RstHandle->Reset, Action);
if (XST_SUCCESS != Status) {
goto done;
}
RstHandle = RstHandle->NextReset;
}
}
Status = XST_SUCCESS;
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
int XPmDevice_CheckPermissions(XPm_Subsystem *Subsystem, u32 DeviceId)
{
int Status = XPM_PM_NO_ACCESS;
XPm_Requirement *Reqm;
XPm_Device *Device = XPmDevice_GetById(DeviceId);
if (NULL == Device) {
Status = XST_INVALID_PARAM;
goto done;
}
Reqm = FindReqm(Device, Subsystem);
if (NULL == Reqm) {
goto done;
}
if (1U == Reqm->Allocated) {
Status = XST_SUCCESS;
goto done;
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief Get handle to requested device node by "complete" Node ID
*
* @param DeviceId Device Node ID
*
* @return Pointer to requested XPm_Device
* NULL otherwise
*
* @note Requires Complete Node ID
*
****************************************************************************/
XPm_Device *XPmDevice_GetById(const u32 DeviceId)
{
XPm_Device *Device = NULL;
if ((u32)XPM_NODECLASS_DEVICE != NODECLASS(DeviceId)) {
goto done;
}
if ((u32)XPM_NODESUBCL_DEV_PL == NODESUBCLASS(DeviceId)) {
if ((u32)XPM_NODEIDX_DEV_PLD_MAX <= NODEINDEX(DeviceId)) {
goto done;
}
Device = PmPlDevices[NODEINDEX(DeviceId)];
/* Check that Device's ID is same as given ID or not. */
if ((NULL != Device) && (DeviceId != Device->Node.Id)) {
Device = NULL;
}
} else {
if ((u32)XPM_NODEIDX_DEV_MAX <= NODEINDEX(DeviceId)) {
goto done;
}
Device = PmDevices[NODEINDEX(DeviceId)];
/* Check that Device's ID is same as given ID or not. */
if ((NULL != Device) && (DeviceId != Device->Node.Id)) {
Device = NULL;
}
}
done:
return Device;
}
/****************************************************************************/
/**
* @brief Get handle to requested device node by "only" Node INDEX
*
* @param DeviceIndex Device Node Index
*
* @return Pointer to requested XPm_Device, NULL otherwise
*
* @note Requires ONLY Node Index
*
* Caller should be _careful_ while using this function as it skips the checks
* for validating the class, subclass and type of the device before and after
* retrieving the node from the database. Use this only where it is absolutely
* necessary, otherwise use XPmDevice_GetById() which is more strict
* and requires 'complete' Node ID for retrieving the handle.
*
****************************************************************************/
XPm_Device *XPmDevice_GetByIndex(const u32 DeviceIndex)
{
XPm_Device *Device = NULL;
/* Make sure we are working with only Index. */
u32 Index = (DeviceIndex & NODE_INDEX_MASK);
if ((u32)XPM_NODEIDX_DEV_MAX <= Index) {
goto done;
}
Device = PmDevices[Index];
/* Check that Device's Index is same as given Index or not. */
if ((NULL != Device) && (Index != NODEINDEX(Device->Node.Id))) {
Device = NULL;
}
done:
return Device;
}
/****************************************************************************/
/**
* @brief Get PLD device node by node INDEX
*
* @param DeviceIndex Device Node Index
*
* @return Pointer to requested XPm_Device, NULL otherwise
*
* @note Requires Node Index
*
* Caller should be _careful_ while using this function as it skips the checks
* for validating the class, subclass and type of the device before and after
* retrieving the node from the database. Use this only where it is absolutely
* necessary, otherwise use XPmDevice_GetById() which is more strict and
* requires 'complete' Node ID for retrieving the handle.
*
****************************************************************************/
XPm_Device *XPmDevice_GetPlDeviceByIndex(const u32 DeviceIndex)
{
XPm_Device *Device = NULL;
/* Make sure we are working with only Index. */
u32 Index = (DeviceIndex & NODE_INDEX_MASK);
if ((u32)XPM_NODEIDX_DEV_PLD_MAX <= Index) {
goto done;
}
Device = PmPlDevices[Index];
/* Check that Device's Index is same as given Index or not. */
if ((NULL != Device) && (Index != NODEINDEX(Device->Node.Id))) {
Device = NULL;
}
done:
return Device;
}
XStatus XPmDevice_Request(const u32 SubsystemId,
const u32 DeviceId,
const u32 Capabilities,
const u32 QoS)
{
XStatus Status = XPM_ERR_DEVICE_REQ;
XPm_Device *Device;
XPm_Subsystem *Subsystem;
u32 Idx;
/* Todo: Check if policy allows this request */
/* If not allowed XPM_PM_NO_ACCESS error should be returned */
if ((u32)XPM_NODECLASS_DEVICE != NODECLASS(DeviceId)) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
Device = XPmDevice_GetById(DeviceId);
if (NULL == Device) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
if (Device->Node.Id != DeviceId) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (Subsystem == NULL || Subsystem->State != (u8)ONLINE) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
Status = Device->DeviceOps->Request(Device, Subsystem, Capabilities,
QoS);
if (XST_SUCCESS == Status) {
/* Assign IPI mask to subsystem if IPI devices are requested. */
for (Idx = 0; Idx < ARRAY_SIZE(IpiMasks); Idx++) {
if (IpiMasks[Idx][0] == Device->Node.Id) {
Subsystem->IpiMask = IpiMasks[Idx][1];
break;
}
}
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
XStatus XPmDevice_Release(const u32 SubsystemId, const u32 DeviceId)
{
XStatus Status = XPM_ERR_DEVICE_RELEASE;
XPm_Device *Device;
XPm_Subsystem *Subsystem;
/* Todo: Check if subsystem has permission */
if ((u32)XPM_NODECLASS_DEVICE != NODECLASS(DeviceId)) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
Device = XPmDevice_GetById(DeviceId);
if (NULL == Device) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
if (Device->Node.Id != DeviceId) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (Subsystem == NULL || Subsystem->State == (u8)OFFLINE) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
Status = Device->DeviceOps->Release(Device, Subsystem);
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
XStatus XPmDevice_SetRequirement(const u32 SubsystemId, const u32 DeviceId,
const u32 Capabilities, const u32 QoS)
{
XStatus Status = XPM_ERR_SET_REQ;
XPm_Device *Device;
XPm_Subsystem *Subsystem;
/* Todo: Check if subsystem has permission */
if ((u32)XPM_NODECLASS_DEVICE != NODECLASS(DeviceId)) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
Device = XPmDevice_GetById(DeviceId);
if (NULL == Device) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
if (Device->Node.Id != DeviceId) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (Subsystem == NULL || Subsystem->State == (u8)OFFLINE) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
Status = Device->DeviceOps->SetRequirement(Device, Subsystem,
Capabilities, QoS);
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
XStatus XPmDevice_GetStatus(const u32 SubsystemId,
const u32 DeviceId,
XPm_DeviceStatus *const DeviceStatus)
{
XStatus Status = XPM_ERR_DEVICE_STATUS;
XPm_Subsystem *Subsystem;
XPm_Device *Device;
XPm_Requirement *Reqm;
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (Subsystem == NULL || Subsystem->State != (u8)ONLINE) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
Device = XPmDevice_GetById(DeviceId);
if (NULL == Device) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
DeviceStatus->Status = Device->Node.State;
Reqm = FindReqm(Device, Subsystem);
if (NULL != Reqm) {
DeviceStatus->Requirement = Reqm->Curr.Capabilities;
}
DeviceStatus->Usage = XPmDevice_GetUsageStatus(Subsystem, Device);
Status = XST_SUCCESS;
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
XStatus XPmDevice_AddParent(u32 Id, u32 *Parents, u32 NumParents)
{
XStatus Status = XST_FAILURE;
u32 i = 0;
XPm_Device *DevPtr = XPmDevice_GetById(Id);
if (DevPtr == NULL || NumParents == 0U) {
Status = XST_INVALID_PARAM;
goto done;
}
for(i=0;i<NumParents;i++)
{
if ((u32)XPM_NODECLASS_CLOCK == NODECLASS(Parents[i])) {
XPm_ClockNode *Clk = XPmClock_GetById(Parents[i]);
if (NULL == Clk) {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmDevice_AddClock(DevPtr, Clk);
if (XST_SUCCESS != Status) {
goto done;
}
} else if ((u32)XPM_NODECLASS_RESET == NODECLASS(Parents[i])) {
XPm_ResetNode *Rst = XPmReset_GetById(Parents[i]);
if (NULL == Rst) {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmDevice_AddReset(DevPtr, Rst);
if (XST_SUCCESS != Status) {
goto done;
}
} else if ((u32)XPM_NODECLASS_POWER == NODECLASS(Parents[i])) {
if (DevPtr->Power != NULL) {
Status = XST_INVALID_PARAM;
goto done;
} else {
DevPtr->Power = XPmPower_GetById(Parents[i]);
if (NULL == DevPtr->Power) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
Status = XST_SUCCESS;
}
} else {
Status = XST_INVALID_PARAM;
goto done;
}
}
done:
return Status;
}
XStatus XPmDevice_GetPermissions(XPm_Device *Device, u32 *PermissionMask)
{
XStatus Status = XST_FAILURE;
XPm_Requirement *Reqm;
u32 Idx;
u32 MaxSubsysIdx = XPmSubsystem_GetMaxSubsysIdx();
if ((NULL == Device) || (NULL == PermissionMask)) {
Status = XST_INVALID_PARAM;
goto done;
}
Reqm = Device->Requirements;
while (NULL != Reqm) {
if (1U == Reqm->Allocated) {
for (Idx = 0; Idx <= MaxSubsysIdx; Idx++) {
if (Reqm->Subsystem == XPmSubsystem_GetByIndex(Idx)) {
*PermissionMask |= ((u32)1U << Idx);
}
}
}
Reqm = Reqm->NextSubsystem;
}
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief Set maximum allowed latency for the device
*
* @param SubsystemId Initiator of the request who must previously requested
* the device
* @param DeviceId Device whose latency is specified
* @param Latency Maximum allowed latency in microseconds
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
****************************************************************************/
int XPmDevice_SetMaxLatency(const u32 SubsystemId, const u32 DeviceId,
const u32 Latency)
{
int Status = XST_FAILURE;
XPm_Requirement *Reqm;
XPm_Subsystem *Subsystem = XPmSubsystem_GetById(SubsystemId);
XPm_Device *Device = XPmDevice_GetById(DeviceId);
if ((NULL == Subsystem) || (NULL == Device)) {
Status = XST_INVALID_PARAM;
goto done;
}
Reqm = FindReqm(Device, Subsystem);
if (NULL == Reqm) {
Status = XPM_ERR_DEVICE_REQ;
goto done;
}
Reqm->Next.Latency = Latency;
Reqm->SetLatReq = 1;
Status = XPmDevice_UpdateStatus(Device);
if (XST_SUCCESS != Status) {
Reqm->SetLatReq = 0;
goto done;
}
Reqm->Curr.Latency = Latency;
done:
return Status;
}
/****************************************************************************/
/**
* @brief Change state of a device
*
* @param Device Device pointer whose state should be changed
* @param NextState New state
*
* @return XST_SUCCESS if transition was performed successfully.
* Error otherwise.
*
* @note None
*
****************************************************************************/
XStatus XPmDevice_ChangeState(XPm_Device *Device, const u32 NextState)
{
XStatus Status = XPM_ERR_SETSTATE;
const XPm_DeviceFsm* Fsm = Device->DeviceFsm;
u32 OldState = Device->Node.State;
u32 Trans;
if (0U == Fsm->TransCnt) {
/* Device's FSM has no transitions when it has only one state */
Status = XST_SUCCESS;
goto done;
}
for (Trans = 0U; Trans < Fsm->TransCnt; Trans++) {
/* Find transition from current state to next state */
if ((Fsm->Trans[Trans].FromState != Device->Node.State) ||
(Fsm->Trans[Trans].ToState != NextState)) {
continue;
}
if (NULL != Device->DeviceFsm->EnterState) {
/* Execute transition action of device's FSM */
Status = Device->DeviceFsm->EnterState(Device, NextState);
} else {
Status = XST_SUCCESS;
}
break;
}
if ((OldState != NextState) && (XST_SUCCESS == Status)) {
Device->Node.State = (u8)NextState;
/* Send notification about device state change */
XPmNotifier_Event(Device->Node.Id, (u32)EVENT_STATE_CHANGE);
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief Get state with provided capabilities
*
* @param Device Device whose states are searched
* @param Caps Capabilities the state must have
* @param State Pointer to a u32 variable where the result is put if
* state is found
*
* @return Status of the operation
* - XST_SUCCESS if state is found
*
* @note None
*
****************************************************************************/
static XStatus GetStateWithCaps(const XPm_Device* const Device, const u32 Caps,
u32* const State)
{
u32 Idx;
XStatus Status = XPM_PM_CONFLICT;
for (Idx = 0U; Idx < Device->DeviceFsm->StatesCnt; Idx++) {
/* Find the first state that contains all capabilities */
if ((Caps & Device->DeviceFsm->States[Idx].Cap) == Caps) {
Status = XST_SUCCESS;
if (NULL != State) {
*State = Device->DeviceFsm->States[Idx].State;
}
break;
}
}
return Status;
}
/****************************************************************************/
/**
* @brief Find minimum of all latency requirements
*
* @Param Device Device whose min required latency is requested
*
* @return Latency in microseconds
*
****************************************************************************/
static u32 GetMinRequestedLatency(const XPm_Device *const Device)
{
XPm_Requirement *Reqm = Device->Requirements;
u32 MinLatency = XPM_MAX_LATENCY;
while (NULL != Reqm) {
if ((1U == Reqm->SetLatReq) &&
(MinLatency > Reqm->Next.Latency)) {
MinLatency = Reqm->Next.Latency;
}
Reqm = Reqm->NextSubsystem;
}
return MinLatency;
}
/****************************************************************************/
/**
* @brief Get latency from given state to the highest state
*
* @param Device Pointer to the device whose states are in question
* @param State State from which the latency is calculated
*
* @return Return value for the found latency
*
****************************************************************************/
static u32 GetLatencyFromState(const XPm_Device *const Device, const u32 State)
{
u32 Idx;
u32 Latency = 0U;
u32 HighestState = Device->DeviceFsm->StatesCnt - (u32)1U;
for (Idx = 0U; Idx < Device->DeviceFsm->TransCnt; Idx++) {
if ((State == Device->DeviceFsm->Trans[Idx].FromState) &&
(HighestState == Device->DeviceFsm->Trans[Idx].ToState)) {
Latency = Device->DeviceFsm->Trans[Idx].Latency;
break;
}
}
return Latency;
}
/****************************************************************************/
/**
* @brief Find a higher power state which satisfies latency requirements
*
* @param Device Device whose state may be constrained
* @param State Chosen state which does not satisfy latency requirements
* @param CapsToSet Capabilities that the state must have
* @param MinLatency Latency requirements to be satisfied
*
* @return Status showing whether the higher power state is found or not.
* State may not be found if multiple subsystem have contradicting requirements,
* then XST_FAILURE is returned. Otherwise, function returns success.
*
****************************************************************************/
static int ConstrainStateByLatency(const XPm_Device *const Device,
u32 *const State, const u32 CapsToSet,
const u32 MinLatency)
{
int Status = XST_FAILURE;
u32 WkupLat;
u32 Idx = 0;
/*
* Need to find higher power state, so ignore lower power states
* and find index for chosen state
*/
while (Device->DeviceFsm->States[Idx].State != *State)
{
Idx++;
}
for (; Idx < Device->DeviceFsm->StatesCnt; Idx++) {
if ((CapsToSet & Device->DeviceFsm->States[Idx].Cap) != CapsToSet) {
/* State candidate has no required capabilities */
continue;
}
WkupLat = GetLatencyFromState(Device, Device->DeviceFsm->States[Idx].State);
if (WkupLat > MinLatency) {
/* State does not satisfy latency requirement */
continue;
}
Status = XST_SUCCESS;
*State = Device->DeviceFsm->States[Idx].State;
break;
}
return Status;
}
/****************************************************************************/
/**
* @brief Device updates its power parent about latency req
*
* @param Device Device whose latency requirement have changed
*
* @return If the change of the latency requirement caused the power up of the
* power parent, the status of performing power up operation is returned,
* otherwise XST_SUCCESS is returned.
*
****************************************************************************/
static int UpdatePwrLatencyReq(const XPm_Device *const Device)
{
int Status = XST_FAILURE;
XPm_Power* Power = Device->Power;
if ((u8)XPM_POWER_STATE_ON == Power->Node.State) {
Status = XST_SUCCESS;
goto done;
}
/* Power is down, check if latency requirements trigger the power up */
if (Device->Node.LatencyMarg <
(Power->PwrDnLatency + Power->PwrUpLatency)) {
Power->Node.LatencyMarg = 0U;
Status = Power->HandleEvent(&Power->Node, XPM_POWER_EVENT_PWR_UP);
} else {
Status = XST_SUCCESS;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief Update the device's state according to the current requirements
* from all subsystems
* @param Device Device whose state is about to be updated
*
* @return Status of operation of updating device's state.
*
* @note None
*
****************************************************************************/
XStatus XPmDevice_UpdateStatus(XPm_Device *Device)
{
XStatus Status = XPM_ERR_DEVICE_STATUS;
u32 Caps = GetMaxCapabilities(Device);
u32 WkupLat, MinLat;
u32 State = 0;
if (((u8)XPM_DEVSTATE_UNUSED != Device->Node.State) &&
((u8)XPM_DEVSTATE_RUNNING != Device->Node.State) &&
((u8)XPM_DEVSTATE_RUNTIME_SUSPEND != Device->Node.State)) {
Status = XST_DEVICE_BUSY;
goto done;
}
Status = GetStateWithCaps(Device, Caps, &State);
if (XST_SUCCESS != Status) {
goto done;
}
MinLat = GetMinRequestedLatency(Device);
WkupLat = GetLatencyFromState(Device, State);
if (WkupLat > MinLat) {
/* State does not satisfy latency requirement, find another */
Status = ConstrainStateByLatency(Device, &State, Caps, MinLat);
if (XST_SUCCESS != Status) {
goto done;
}
WkupLat = GetLatencyFromState(Device, State);
}
Device->Node.LatencyMarg = (u16)(MinLat - WkupLat);
if (State != Device->Node.State) {
Status = XPmDevice_ChangeState(Device, State);
} else {
if (((u8)XPM_DEVSTATE_UNUSED == Device->Node.State) &&
(NULL != Device->Power)) {
/* Notify power parent (changed latency requirement) */
Status = UpdatePwrLatencyReq(Device);
}
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief Get the current usage status for a given device.
* @param Subsystem Subsystem for which usage status is in query
* @slave Device Device for which usage status need to be calculated
*
* @return Usage status:
* - 0: No subsystem is currently using the device
* - 1: Only requesting subsystem is currently using the device
* - 2: Only other subsystems are currently using the device
* - 3: Both the current and at least one other subsystem is currently
* using the device
*
****************************************************************************/
u32 XPmDevice_GetUsageStatus(XPm_Subsystem *Subsystem, XPm_Device *Device)
{
u32 UsageStatus = 0;
XPm_Requirement *Reqm = Device->Requirements;
while (NULL != Reqm) {
if (1U == Reqm->Allocated) {
/* This subsystem is currently using this device */
if (Subsystem == Reqm->Subsystem) {
UsageStatus |= (u32)PM_USAGE_CURRENT_SUBSYSTEM;
} else {
UsageStatus |= (u32)PM_USAGE_OTHER_SUBSYSTEM;
}
}
Reqm = Reqm->NextSubsystem;
}
return UsageStatus;
}
/****************************************************************************/
/**
* @brief Check if any clock for a given device is active
* @param Device Device whose clocks need to be checked
*
* @return XST_SUCCESS if any one clock for given device is active
* XST_FAILURE if all clocks for given device are inactive
*
****************************************************************************/
int XPmDevice_IsClockActive(XPm_Device *Device)
{
int Status = XST_FAILURE;
XPm_ClockHandle *ClkHandle = Device->ClkHandles;
XPm_OutClockNode *Clk;
u32 Enable;
while (NULL != ClkHandle) {
if ((NULL != ClkHandle->Clock) &&
(ISOUTCLK(ClkHandle->Clock->Node.Id))) {
Clk = (XPm_OutClockNode *)ClkHandle->Clock;
Status = XPmClock_GetClockData(Clk, (u32)TYPE_GATE, &Enable);
if (XST_SUCCESS == Status) {
if (1U == Enable) {
Status = XST_SUCCESS;
goto done;
}
} else if (XPM_INVALID_CLK_SUBNODETYPE == Status) {
PmDbg("Clock 0x%x does not have Clock Gate\n\r",
ClkHandle->Clock->Node.Id);
Status = XST_SUCCESS;
} else {
PmErr("XPmClock_GetClockData failed with Status 0x%x"
" for clock id: 0x%x\r\n",
Status,
ClkHandle->Clock->Node.Id);
}
}
ClkHandle = ClkHandle->NextClock;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief Check if any subsystem requested perticular device or not.
*
* @param DeviceId Device ID
* @param SubsystemId Subsystem ID
*
* @return XST_SUCCESS if device is requested from subsystem
* XST_FAILURE if device is not requested or error code
*
****************************************************************************/
int XPmDevice_IsRequested(const u32 DeviceId, const u32 SubsystemId)
{
int Status = XST_FAILURE;
XPm_Device *Device = XPmDevice_GetById(DeviceId);
XPm_Subsystem *Subsystem = XPmSubsystem_GetById(SubsystemId);
XPm_Requirement *Reqm;
if ((NULL == Device) || (NULL == Subsystem)) {
Status = XST_INVALID_PARAM;
goto done;
}
Reqm = FindReqm(Device, Subsystem);
if ((NULL != Reqm) && (1U == Reqm->Allocated)) {
Status = XST_SUCCESS;
}
done:
return Status;
}
int XPmDevice_GetWakeupLatency(const u32 DeviceId, u32 *Latency)
{
int Status = XST_SUCCESS;
XPm_Device *Device = XPmDevice_GetById(DeviceId);
u32 Lat = 0;
*Latency = 0;
if (NULL == Device) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((u8)XPM_DEVSTATE_RUNNING == Device->Node.State) {
goto done;
}
*Latency = GetLatencyFromState(Device, Device->Node.State);
if (NULL != Device->Power) {
Status = XPmPower_GetWakeupLatency(Device->Power->Node.Id, &Lat);
if (XST_SUCCESS != Status) {
*Latency += Lat;
}
}
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/xfsbl_plpartition_valid.h
/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xfsbl_plpartition_valid.h
*
* Contains constant definitions for bitstream authentication.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------------
* 1.0 vns 01/28/17 First release
* 2.0 vns 11/09/17 In structure XFsblPs_PlPartition added member
* (SecureHdr) to store partial secure header when
* single secure header is in two chunks, also added
* another member(Hdr) to store size of data stored.
* 3.0 vns 03/12/19 Added instance to XSecure_Sss structure in
* XFsblPs_PlPartition structure.
* </pre>
*
******************************************************************************/
#ifndef XFSBL_PLPARTITION_VALID_H_
#define XFSBL_PLPARTITION_VALID_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xfsbl_authentication.h"
#include "xfsbl_main.h"
/************************** Constant Definitions *****************************/
#define XFSBL_CSU_SSS_SRC_SRC_DMA 0x5U
/**************************** Type Definitions *******************************/
#if defined(XFSBL_SECURE) && defined(XFSBL_BS)
/** @name XFsblPs_PlAuthentication
* @{
*/
typedef struct {
u8 AuthType; /**< Type of Authentication used SHA2/SHA3 */
u8 *AuthCertBuf;/**< Buffer to store authentication certificate */
u32 AcOfset; /**< Offset of first authentication certificate
* of bitstream */
u8 *HashsOfChunks;/** To store hashes of all chunks of block */
u32 NoOfHashs; /**< HashsOfChunks buffer size provided */
u32 BlockSize; /**< Block size of bitstream */
} XFsblPs_PlAuthentication;
/*@}*/
/** @name XFsblPs_PlEncryption
* @{
*/
typedef struct {
XSecure_Aes *SecureAes; /**< AES initialized structure */
u32 NextBlkLen; /**< Not required for user, used for storing
* next block size */
} XFsblPs_PlEncryption;
/*@}*/
/** @name XFsblPs_PlPartition
* @{
*/
typedef struct {
u8 IsAuthenticated; /**< Authentication flag */
u8 IsEncrypted; /**< Encryption flag */
u64 StartAddress; /** Start address of the partition */
u32 UnEncryptLen; /**< un encrypted length of bitstream */
u32 TotalLen; /**< Total partition length */
u32 ChunkSize; /**< Chunk size */
u8 *ChunkBuffer; /**< Buffer for storing chunk of data */
XCsuDma *CsuDmaPtr; /**< Initialized CSUDMA driver's instance */
u32 (*DeviceCopy) (u32 SrcAddress, UINTPTR DestAddress, u32 Length);
/**< Device copy for DDR less system */
XFsblPs_PlEncryption PlEncrypt; /**< Encryption parameters */
XFsblPs_PlAuthentication PlAuth;/**< Authentication parameters */
u8 SecureHdr[XSECURE_SECURE_HDR_SIZE + XSECURE_SECURE_GCM_TAG_SIZE];
u8 Hdr;
XSecure_Sss SssInstance;
} XFsblPs_PlPartition;
/*@}*/
/***************************** Function Prototypes ***************************/
u32 XFsbl_SecPlPartition(XFsblPs * FsblInstancePtr,
XFsblPs_PlPartition *PartitionParams);
#endif
/******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_sram.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* Definitions of PM slave SRAM structures and state transitions.
*********************************************************************/
#include "pm_sram.h"
#include "pm_common.h"
#include "pm_master.h"
#include "xpfw_rom_interface.h"
#include "crf_apb.h"
#include "rpu.h"
/* TCM banks IDs (one hot encoded) */
#define PM_TCM_0A_BANK_ID 0x1U
#define PM_TCM_0B_BANK_ID 0x2U
#define PM_TCM_1A_BANK_ID 0x4U
#define PM_TCM_1B_BANK_ID 0x8U
/* Power states of SRAM */
#define PM_SRAM_STATE_OFF 0U
#define PM_SRAM_STATE_RET 1U
#define PM_SRAM_STATE_ON 2U
#define PM_SRAM_STATE_MAX 3U
/* Power consumptions for SRAM defined by its states */
#define DEFAULT_SRAM_POWER_ON 100U
#define DEFAULT_SRAM_POWER_RETENTION 50U
#define DEFAULT_SRAM_POWER_OFF 0U
/* SRAM state transition latency values */
#define PM_SRAM_ON_TO_RET_LATENCY 3U
#define PM_SRAM_RET_TO_ON_LATENCY 130U
#define PM_SRAM_ON_TO_OFF_LATENCY 3U
#define PM_SRAM_OFF_TO_ON_LATENCY 3100U
/* Sram states */
static const u8 pmSramStates[PM_SRAM_STATE_MAX] = {
[PM_SRAM_STATE_OFF] = 0U,
[PM_SRAM_STATE_RET] = PM_CAP_CONTEXT | PM_CAP_POWER,
[PM_SRAM_STATE_ON] = PM_CAP_ACCESS | PM_CAP_CONTEXT | PM_CAP_POWER,
};
/* Sram transition table (from which to which state sram can transit) */
static const PmStateTran pmSramTransitions[] = {
{
.latency = PM_SRAM_ON_TO_RET_LATENCY,
.fromState = PM_SRAM_STATE_ON,
.toState = PM_SRAM_STATE_RET,
}, {
.latency = PM_SRAM_RET_TO_ON_LATENCY,
.fromState = PM_SRAM_STATE_RET,
.toState = PM_SRAM_STATE_ON,
}, {
.latency = PM_SRAM_ON_TO_OFF_LATENCY,
.fromState = PM_SRAM_STATE_ON,
.toState = PM_SRAM_STATE_OFF,
}, {
.latency = PM_SRAM_OFF_TO_ON_LATENCY,
.fromState = PM_SRAM_STATE_OFF,
.toState = PM_SRAM_STATE_ON,
},
};
/**
* PmSramFsmHandler() - Sram FSM handler, performs transition actions
* @slave Slave whose state should be changed
* @nextState State the slave should enter
*
* @return Status of performing transition action
*/
static s32 PmSramFsmHandler(PmSlave* const slave, const PmStateId nextState)
{
s32 status = XST_PM_INTERNAL;
PmSlaveSram* sram = (PmSlaveSram*)slave->node.derived;
switch (slave->node.currState) {
case PM_SRAM_STATE_ON:
if (PM_SRAM_STATE_RET == nextState) {
/* ON -> RET */
XPfw_RMW32(sram->retCtrlAddr, sram->retCtrlMask,
sram->retCtrlMask);
status = sram->PwrDn();
} else if (PM_SRAM_STATE_OFF == nextState) {
/* ON -> OFF*/
XPfw_RMW32(sram->retCtrlAddr, sram->retCtrlMask,
~sram->retCtrlMask);
status = sram->PwrDn();
} else {
status = XST_NO_FEATURE;
}
break;
case PM_SRAM_STATE_RET:
if (PM_SRAM_STATE_ON == nextState) {
/* RET -> ON */
status = sram->PwrUp();
} else if (PM_SRAM_STATE_OFF == nextState) {
/* RET -> OFF */
XPfw_RMW32(sram->retCtrlAddr, sram->retCtrlMask,
~sram->retCtrlMask);
status = sram->PwrDn();
} else {
status = XST_NO_FEATURE;
}
break;
case PM_SRAM_STATE_OFF:
if (PM_SRAM_STATE_ON == nextState) {
/* OFF -> ON */
status = sram->PwrUp();
} else {
status = XST_NO_FEATURE;
}
break;
default:
status = XST_PM_INTERNAL;
PmNodeLogUnknownState(&slave->node, slave->node.currState);
break;
}
return status;
}
/**
* PmTcmFsmHandler() - TCM FSM handler, performs transition actions
* @slave TCM slave whose state should be changed
* @nextState State the TCM slave should enter
*
* @return Status of performing transition action
*/
static s32 PmTcmFsmHandler(PmSlave* const slave, const PmStateId nextState)
{
s32 status;
PmSlaveTcm* tcm = (PmSlaveTcm*)slave->node.derived;
if (PM_SRAM_STATE_ON == nextState) {
status = PmPowerRequestRpu(tcm);
if (XST_SUCCESS != status) {
goto done;
}
}
status = PmSramFsmHandler(slave, nextState);
if (XST_SUCCESS != status) {
goto done;
}
if ((PM_SRAM_STATE_OFF == slave->node.currState) &&
(PM_SRAM_STATE_ON == nextState)) {
tcm->eccInit(tcm);
}
if (PM_SRAM_STATE_ON != nextState) {
PmPowerReleaseRpu(tcm);
}
done:
return status;
}
/**
* PmTcm0EccInit() - ECC initialization for TCM bank 0
* @tcm TCM slave node to initialize
*/
static void PmTcm0EccInit(const PmSlaveTcm* const tcm)
{
(void)memset((u32 *)tcm->base, 0U, tcm->size);
}
/**
* PmTcm1EccInit() - ECC initialization for TCM bank 1
* @tcm TCM slave node to initialize
*/
static void PmTcm1EccInit(const PmSlaveTcm* const tcm)
{
u32 base = tcm->base;
u32 ctrl = XPfw_Read32(RPU_RPU_GLBL_CNTL);
if (0U != (ctrl & RPU_RPU_GLBL_CNTL_TCM_COMB_MASK)) {
base -= 0x80000U;
}
(void)memset((u32 *)base, 0U, tcm->size);
}
/**
* PmSlaveTcmInit() - Initialize the TCM slave
* @slave TCM slave node
*/
static s32 PmSlaveTcmInit(PmSlave* const slave)
{
s32 status = XST_SUCCESS;
PmSlaveTcm* tcm = (PmSlaveTcm*)slave->node.derived;
if (PM_SRAM_STATE_ON == slave->node.currState) {
status = PmPowerRequestRpu(tcm);
}
return status;
}
/**
* PmSlaveTcmForceDown() - Force down the TCM slave
* @slave TCM slave node
*/
static s32 PmSlaveTcmForceDown(PmSlave* const slave)
{
PmSlaveTcm* tcm = (PmSlaveTcm*)slave->node.derived;
if (PM_SRAM_STATE_ON == slave->node.currState) {
PmPowerReleaseRpu(tcm);
}
return XST_SUCCESS;
}
static PmSlaveClass pmSlaveClassTcm = {
.init = PmSlaveTcmInit,
.forceDown = PmSlaveTcmForceDown,
};
/* Sram FSM */
static const PmSlaveFsm slaveSramFsm = {
.states = pmSramStates,
.statesCnt = PM_SRAM_STATE_MAX,
.trans = pmSramTransitions,
.transCnt = ARRAY_SIZE(pmSramTransitions),
.enterState = PmSramFsmHandler,
};
/* TCM FSM */
static const PmSlaveFsm pmSlaveTcmFsm = {
DEFINE_SLAVE_STATES(pmSramStates),
DEFINE_SLAVE_TRANS(pmSramTransitions),
.enterState = PmTcmFsmHandler,
};
static u8 PmSramPowers[] = {
DEFAULT_SRAM_POWER_OFF,
DEFAULT_SRAM_POWER_RETENTION,
DEFAULT_SRAM_POWER_ON,
};
/**
* PmL2PwrDn() - Handler for powering down L2$
*
* @return Status returned by PMU-ROM handler for powering down L2$
*/
static u32 PmL2PwrDn(void)
{
s32 status;
/* Now call PMU-ROM function to power down L2 RAM */
status = XpbrPwrDnL2Bank0Handler();
/*
* Assert L2 reset after the power down. Reset will be released by the
* PMU-ROM when the first APU core is woken-up.
*/
XPfw_RMW32(CRF_APB_RST_FPD_APU,
CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK,
CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK);
return status;
}
PmSlaveSram pmSlaveL2_g = {
.slv = {
.node = {
.derived = &pmSlaveL2_g,
.nodeId = NODE_L2,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_SRAM_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmSramPowers),
DEFINE_NODE_NAME("l2$"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &slaveSramFsm,
.flags = 0U,
},
.PwrDn = PmL2PwrDn,
.PwrUp = XpbrPwrUpL2Bank0Handler,
.retCtrlAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.retCtrlMask = PMU_GLOBAL_RAM_RET_CNTRL_L2_BANK0_MASK,
};
PmSlaveSram pmSlaveOcm0_g = {
.slv = {
.node = {
.derived = &pmSlaveOcm0_g,
.nodeId = NODE_OCM_BANK_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_SRAM_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmSramPowers),
DEFINE_NODE_NAME("ocm0"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &slaveSramFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnOcmBank0Handler,
.PwrUp = XpbrPwrUpOcmBank0Handler,
.retCtrlAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.retCtrlMask = PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK0_MASK,
};
PmSlaveSram pmSlaveOcm1_g = {
.slv = {
.node = {
.derived = &pmSlaveOcm1_g,
.nodeId = NODE_OCM_BANK_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_SRAM_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmSramPowers),
DEFINE_NODE_NAME("ocm1"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &slaveSramFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnOcmBank1Handler,
.PwrUp = XpbrPwrUpOcmBank1Handler,
.retCtrlAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.retCtrlMask = PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK1_MASK,
};
PmSlaveSram pmSlaveOcm2_g = {
.slv = {
.node = {
.derived = &pmSlaveOcm2_g,
.nodeId = NODE_OCM_BANK_2,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_SRAM_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmSramPowers),
DEFINE_NODE_NAME("ocm2"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &slaveSramFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnOcmBank2Handler,
.PwrUp = XpbrPwrUpOcmBank2Handler,
.retCtrlAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.retCtrlMask = PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK2_MASK,
};
PmSlaveSram pmSlaveOcm3_g = {
.slv = {
.node = {
.derived = &pmSlaveOcm3_g,
.nodeId = NODE_OCM_BANK_3,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_SRAM_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmSramPowers),
DEFINE_NODE_NAME("ocm3"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &slaveSramFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnOcmBank3Handler,
.PwrUp = XpbrPwrUpOcmBank3Handler,
.retCtrlAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.retCtrlMask = PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK3_MASK,
};
PmSlaveTcm pmSlaveTcm0A_g = {
.sram = {
.slv = {
.node = {
.derived = &pmSlaveTcm0A_g,
.nodeId = NODE_TCM_0_A,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_SRAM_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmSramPowers),
DEFINE_NODE_NAME("tcm0a"),
},
.class = &pmSlaveClassTcm,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmSlaveTcmFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnTcm0AHandler,
.PwrUp = XpbrPwrUpTcm0AHandler,
.retCtrlAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.retCtrlMask = PMU_GLOBAL_RAM_RET_CNTRL_TCM0A_MASK,
},
.size = 0x10000U,
.base = 0xffe00000U,
.eccInit = PmTcm0EccInit,
.id = PM_TCM_0A_BANK_ID,
};
PmSlaveTcm pmSlaveTcm0B_g = {
.sram = {
.slv = {
.node = {
.derived = &pmSlaveTcm0B_g,
.nodeId = NODE_TCM_0_B,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_SRAM_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmSramPowers),
DEFINE_NODE_NAME("tcm0b"),
},
.class = &pmSlaveClassTcm,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmSlaveTcmFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnTcm0BHandler,
.PwrUp = XpbrPwrUpTcm0BHandler,
.retCtrlAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.retCtrlMask = PMU_GLOBAL_RAM_RET_CNTRL_TCM0B_MASK,
},
.size = 0x10000U,
.base = 0xffe20000U,
.eccInit = PmTcm0EccInit,
.id = PM_TCM_0B_BANK_ID,
};
PmSlaveTcm pmSlaveTcm1A_g = {
.sram = {
.slv = {
.node = {
.derived = &pmSlaveTcm1A_g,
.nodeId = NODE_TCM_1_A,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_SRAM_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmSramPowers),
DEFINE_NODE_NAME("tcm1a"),
},
.class = &pmSlaveClassTcm,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmSlaveTcmFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnTcm1AHandler,
.PwrUp = XpbrPwrUpTcm1AHandler,
.retCtrlAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.retCtrlMask = PMU_GLOBAL_RAM_RET_CNTRL_TCM1A_MASK,
},
.size = 0x10000U,
.base = 0xffe90000U,
.eccInit = PmTcm1EccInit,
.id = PM_TCM_1A_BANK_ID,
};
PmSlaveTcm pmSlaveTcm1B_g = {
.sram = {
.slv = {
.node = {
.derived = &pmSlaveTcm1B_g,
.nodeId = NODE_TCM_1_B,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_SRAM_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmSramPowers),
DEFINE_NODE_NAME("tcm1b"),
},
.class = &pmSlaveClassTcm,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmSlaveTcmFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnTcm1BHandler,
.PwrUp = XpbrPwrUpTcm1BHandler,
.retCtrlAddr = PMU_GLOBAL_RAM_RET_CNTRL,
.retCtrlMask = PMU_GLOBAL_RAM_RET_CNTRL_TCM1B_MASK,
},
.eccInit = PmTcm1EccInit,
.size = 0x10000U,
.base = 0xffeb0000U,
.id = PM_TCM_1B_BANK_ID,
};
#endif
<file_sep>/python_drivers/james_qutag_test.py
# -*- coding: utf-8 -*-
"""
Created on Tue Jun 30 16:00:14 2020
@author: tianlab01
"""
# for sleep
import time
# This code shows how to get timestamps from a quTAG connected via USB and write them into a text file.
# Import the python wrapper which wraps the DLL functions.
# The wrapper should be in the same directory like this code in the folder '..\QUTAG-V1.x.x\userlib\src'.
import QuTAG
# Initialize the quTAG device
qutag = QuTAG.QuTAG()
filename = r'quTAG_timestamps.txt'
#disable all markers
#qutag.enableMarkers((1,2))
qutag.enableChannels((0, 1, 2, 3))
#check for lost timestamps
rc = qutag.getDataLost()
print("Data loss", rc)
# start writing Timestamps from the quTAG
qutag.writeTimestamps(filename,qutag.FILEFORMAT_ASCII)
# Give some time to accumulate data
time.sleep(1) # 1 second sleep time
# stop writing Timestamps
qutag.writeTimestamps('',qutag.FILEFORMAT_NONE)
print("Let's have a look into the file " + filename)
qutag.deInitialize()
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_node_reset.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/**
* Implementation for the reset of individual node.
*/
#ifdef ENABLE_NODE_IDLING
#include <sleep.h>
#include "pm_defs.h"
#include "pm_common.h"
#include "pm_core.h"
#include "pm_reset.h"
#include "pm_node_reset.h"
#include "pm_node_idle.h"
#define MAX_RST_ACTION 5
typedef struct PmNodeResetInfo {
/*
* NodeId for the this data
*/
u32 NodeId;
/*
* List of Reset lines and corresponding action.
* The list also ends early if next element's
* ResetId is 0
*/
struct {
u32 ResetId; /* Reset Line */
u32 ResetAction; /* Action Pulse / Assert */
u32 ResetPulseWait; /* wait time (in microseconds) between Assert and de-assert*/
} RstActionList[MAX_RST_ACTION];
/*
* Individual IP soft reset function.
*/
void (*SoftRst)(u32);
u32 SoftRstArgs;
/*
* hook function for custom idling before soft reset.
*/
void (*IdleHook)(u32);
u32 IdleHookArgs;
} PmNodeResetInfo;
/* Static resource allocation for Reset Info Data for all
* possible nodes
*/
static const PmNodeResetInfo NodeRstData[] = {
{
.NodeId = NODE_USB_0,
.RstActionList= {
{ .ResetId = PM_RESET_USB0_CORERESET,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{ .ResetId = PM_RESET_USB0_APB,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{ .ResetId = PM_RESET_USB0_HIBERRESET,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_USB_XHCI_0_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeUsbIdle,
.IdleHookArgs = XPAR_PSU_USB_XHCI_0_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_USB_1,
.RstActionList= {
{ .ResetId = PM_RESET_USB1_CORERESET,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{ .ResetId = PM_RESET_USB1_APB,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{ .ResetId = PM_RESET_USB1_HIBERRESET,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_USB_XHCI_1_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeUsbIdle,
.IdleHookArgs = XPAR_PSU_USB_XHCI_1_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_TTC_0,
.RstActionList= {
{ .ResetId = PM_RESET_TTC0,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_TTC_0_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeTtcIdle,
.IdleHookArgs = XPAR_PSU_TTC_0_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_TTC_1,
.RstActionList= {
{ .ResetId = PM_RESET_TTC1,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_TTC_3_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeTtcIdle,
.IdleHookArgs = XPAR_PSU_TTC_3_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_TTC_2,
.RstActionList= {
{ .ResetId = PM_RESET_TTC2,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_TTC_6_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeTtcIdle,
.IdleHookArgs = XPAR_PSU_TTC_6_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
#ifndef ENABLE_RECOVERY
{
.NodeId = NODE_TTC_3,
.RstActionList= {
{ .ResetId = PM_RESET_TTC3,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_TTC_9_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeTtcIdle,
.IdleHookArgs = XPAR_PSU_TTC_9_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
#endif
{
.NodeId = NODE_SATA,
.RstActionList= {
{ .ResetId = PM_RESET_SATA,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_SATA_S_AXI_BASEADDR
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeSataIdle,
.IdleHookArgs = XPAR_PSU_SATA_S_AXI_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_ETH_0,
.RstActionList= {
{ .ResetId = PM_RESET_GEM0,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_ETHERNET_0_DEVICE_ID
.SoftRst = XEmacPs_ResetHw,
.SoftRstArgs = XPAR_PSU_ETHERNET_0_BASEADDR,
.IdleHook = NodeGemIdle,
.IdleHookArgs = XPAR_PSU_ETHERNET_0_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_ETH_1,
.RstActionList= {
{ .ResetId = PM_RESET_GEM1,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_ETHERNET_1_DEVICE_ID
.SoftRst = XEmacPs_ResetHw,
.SoftRstArgs = XPAR_PSU_ETHERNET_1_BASEADDR,
.IdleHook = NodeGemIdle,
.IdleHookArgs = XPAR_PSU_ETHERNET_1_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_ETH_2,
.RstActionList= {
{ .ResetId = PM_RESET_GEM2,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_ETHERNET_2_DEVICE_ID
.SoftRst = XEmacPs_ResetHw,
.SoftRstArgs = XPAR_PSU_ETHERNET_2_BASEADDR,
.IdleHook = NodeGemIdle,
.IdleHookArgs = XPAR_PSU_ETHERNET_2_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_ETH_3,
.RstActionList= {
{ .ResetId = PM_RESET_GEM3,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_ETHERNET_3_DEVICE_ID
.SoftRst = XEmacPs_ResetHw,
.SoftRstArgs = XPAR_PSU_ETHERNET_3_BASEADDR,
.IdleHook = NodeGemIdle,
.IdleHookArgs = XPAR_PSU_ETHERNET_3_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
#if !((STDOUT_BASEADDRESS == XPAR_PSU_UART_0_BASEADDR) && defined(DEBUG_MODE))
{
.NodeId = NODE_UART_0,
.RstActionList= {
{ .ResetId = PM_RESET_UART0,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_UART_0_DEVICE_ID
.SoftRst = XUartPs_ResetHw,
.SoftRstArgs = XPAR_PSU_UART_0_BASEADDR,
.IdleHook = NULL,
.IdleHookArgs = 0U
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
#endif
#if !((STDOUT_BASEADDRESS == XPAR_PSU_UART_1_BASEADDR) && defined(DEBUG_MODE))
{
.NodeId = NODE_UART_1,
.RstActionList= {
{ .ResetId = PM_RESET_UART1,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_UART_1_DEVICE_ID
.SoftRst = XUartPs_ResetHw,
.SoftRstArgs = XPAR_PSU_UART_1_BASEADDR,
.IdleHook = NULL,
.IdleHookArgs = 0U
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
#endif
{
.NodeId = NODE_SPI_0,
.RstActionList= {
{ .ResetId = PM_RESET_SPI0,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_SPI_0_DEVICE_ID
.SoftRst = XSpiPs_ResetHw,
.SoftRstArgs = XPAR_PSU_SPI_0_BASEADDR,
.IdleHook = NULL,
.IdleHookArgs = 0U
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_SPI_1,
.RstActionList= {
{ .ResetId = PM_RESET_SPI1,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_SPI_1_DEVICE_ID
.SoftRst = XSpiPs_ResetHw,
.SoftRstArgs = XPAR_PSU_SPI_1_BASEADDR,
.IdleHook = NULL,
.IdleHookArgs = 0U
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_I2C_0,
.RstActionList= {
{ .ResetId = PM_RESET_I2C0,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_I2C_0_DEVICE_ID
.SoftRst = XIicPs_ResetHw,
.SoftRstArgs = XPAR_PSU_I2C_0_BASEADDR,
.IdleHook = NodeI2cIdle,
.IdleHookArgs = XPAR_PSU_I2C_0_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_I2C_1,
.RstActionList= {
{ .ResetId = PM_RESET_I2C1,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_I2C_1_DEVICE_ID
.SoftRst = XIicPs_ResetHw,
.SoftRstArgs = XPAR_PSU_I2C_1_BASEADDR,
.IdleHook = NodeI2cIdle,
.IdleHookArgs = XPAR_PSU_I2C_1_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_SD_0,
.RstActionList= {
{ .ResetId = PM_RESET_SDIO0,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_SD_0_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeSdioIdle,
.IdleHookArgs = XPAR_PSU_SD_0_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_SD_1,
.RstActionList= {
{ .ResetId = PM_RESET_SDIO1,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_SD_1_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeSdioIdle,
.IdleHookArgs = XPAR_PSU_SD_1_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_QSPI,
.RstActionList= {
{ .ResetId = PM_RESET_QSPI,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_QSPI_0_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeQspiIdle,
.IdleHookArgs = XQSPIPSU_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
#ifndef REMOVE_GPIO_FROM_NODE_RESET_INFO
{
.NodeId = NODE_GPIO,
.RstActionList= {
{ .ResetId = PM_RESET_GPIO,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_GPIO_0_DEVICE_ID
.SoftRst = XGpioPs_ResetHw,
.SoftRstArgs = XPAR_PSU_GPIO_0_BASEADDR,
.IdleHook = NULL,
.IdleHookArgs = 0U
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
#endif
{
.NodeId = NODE_PCIE,
.RstActionList= {
{ .ResetId = PM_RESET_PCIE_CTRL,
.ResetAction = PM_RESET_ACTION_PULSE,
.ResetPulseWait = 0U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
},
{
.NodeId = NODE_DP,
.RstActionList= {
{ .ResetId = PM_RESET_DP,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_XDPPSU_0_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeDpIdle,
.IdleHookArgs = XPAR_XDPPSU_0_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_GDMA,
.RstActionList= {
{ .ResetId = PM_RESET_GDMA,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10,
},
{0,0,0}
},
#ifdef XPAR_PSU_GDMA_0_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeZdmaIdle,
.IdleHookArgs = XPAR_PSU_GDMA_0_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_ADMA,
.RstActionList= {
{ .ResetId = PM_RESET_ADMA,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10,
},
{0,0,0}
},
#ifdef XPAR_PSU_ADMA_0_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeZdmaIdle,
.IdleHookArgs = XPAR_PSU_ADMA_0_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_CAN_0,
.RstActionList= {
{ .ResetId = PM_RESET_CAN0,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_CAN_0_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeCanIdle,
.IdleHookArgs = XPAR_PSU_CAN_0_BASEADDR
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_CAN_1,
.RstActionList= {
{ .ResetId = PM_RESET_CAN1,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_CAN_1_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeCanIdle,
.IdleHookArgs = XPAR_PSU_CAN_1_BASEADDR,
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_NAND,
.RstActionList= {
{ .ResetId = PM_RESET_NAND,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U},
{0U,0U,0U}
},
#ifdef XPAR_PSU_NAND_0_DEVICE_ID
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NodeNandIdle,
.IdleHookArgs = XPAR_PSU_NAND_0_BASEADDR,
#else
.SoftRst = NULL,
.SoftRstArgs = 0U,
.IdleHook = NULL,
.IdleHookArgs = 0U
#endif
},
{
.NodeId = NODE_GPU,
.RstActionList = {
{
.ResetId = PM_RESET_GPU,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
},
.SoftRst = NULL,
.SoftRstArgs = 0U,
#ifdef XPAR_PSU_GPU_S_AXI_BASEADDR
.IdleHook = NodeGpuIdle,
.IdleHookArgs = XPAR_PSU_GPU_S_AXI_BASEADDR,
#else
.IdleHook = NULL,
.IdleHookArgs = 0U,
#endif
},
{
.NodeId = NODE_GPU_PP_0,
.RstActionList = {
{
.ResetId = PM_RESET_GPU_PP0,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
},
.SoftRst = NULL,
.SoftRstArgs = 0U,
#ifdef XPAR_PSU_GPU_S_AXI_BASEADDR
.IdleHook = NodeGpuPPIdle,
.IdleHookArgs = XPAR_PSU_GPU_S_AXI_BASEADDR +
GPU_PP_0_OFFSET,
#else
.IdleHook = NULL,
.IdleHookArgs = 0U,
#endif
},
{
.NodeId = NODE_GPU_PP_1,
.RstActionList = {
{
.ResetId = PM_RESET_GPU_PP1,
.ResetAction = PM_RESET_ACTION_ASSERT,
.ResetPulseWait = 10U,
},
},
.SoftRst = NULL,
.SoftRstArgs = 0U,
#ifdef XPAR_PSU_GPU_S_AXI_BASEADDR
.IdleHook = NodeGpuPPIdle,
.IdleHookArgs = XPAR_PSU_GPU_S_AXI_BASEADDR +
GPU_PP_1_OFFSET,
#else
.IdleHook = NULL,
.IdleHookArgs = 0U,
#endif
},
};
/**
* PmNodeResetInfo() - Get the reset info data for the given node
* @NodeId ID of Node
*
* @return Pointer to PmNodeResetInfo structure for the given
* node (or NULL if not found)
*/
static const PmNodeResetInfo *GetNodeResetInfo(const u32 NodeId)
{
u32 Index;
const PmNodeResetInfo *RstInfo = NULL;
for (Index = 0U; Index < ARRAY_SIZE(NodeRstData); Index++) {
if (NodeId == NodeRstData[Index].NodeId) {
RstInfo = &NodeRstData[Index];
break;
}
}
return RstInfo;
}
/**
* PmNodeReset() - Resets the given node after idling
* @Master Initiator of the request
* @NodeId ID of Node to be reset
* @IdleReq flag to indicate whether node should be idle and soft reset
*/
void PmNodeReset(const PmMaster *const Master, const u32 NodeId, const u32 IdleReq)
{
u32 Index;
const PmNodeResetInfo *RstInfo = GetNodeResetInfo(NodeId);
if (NULL == RstInfo) {
/*
* No reset node data available for this node.
*/
return;
}
/*
* If idling is requested, call the idling
* function along with the soft reset function
*/
if (NODE_IDLE_REQ == IdleReq) {
if (RstInfo->IdleHook != NULL) {
RstInfo->IdleHook(RstInfo->IdleHookArgs);
}
if (RstInfo->SoftRst != NULL) {
RstInfo->SoftRst(RstInfo->SoftRstArgs);
}
}
/*
* Perform the Node reset using Reset Line for the
* node and its corresponding actions
*/
for (Index = 0U; Index < MAX_RST_ACTION; Index++) {
if (RstInfo->RstActionList[Index].ResetId == 0U) {
/*
* No more reset action required.
*/
break;
}
PmResetAssert(Master, RstInfo->RstActionList[Index].ResetId,
RstInfo->RstActionList[Index].ResetAction);
if (RstInfo->RstActionList[Index].ResetAction != PM_RESET_ACTION_PULSE) {
/*
* Release the reset after given interval
*/
usleep(RstInfo->RstActionList[Index].ResetPulseWait);
PmResetAssert(Master, RstInfo->RstActionList[Index].ResetId,
PM_RESET_ACTION_RELEASE);
}
}
}
#endif
#endif /* ENABLE_NODE_IDLING */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/crl_apb.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _CRL_APB_H_
#define _CRL_APB_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* CRL_APB Base Address
*/
#define CRL_APB_BASEADDR ((u32)0XFF5E0000U)
/**
* Register: CRL_APB_ERR_CTRL
*/
#define CRL_APB_ERR_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000000U) )
#define CRL_APB_ERR_CTRL_SLVERR_ENABLE_SHIFT 0
#define CRL_APB_ERR_CTRL_SLVERR_ENABLE_WIDTH 1
#define CRL_APB_ERR_CTRL_SLVERR_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_IR_STATUS
*/
#define CRL_APB_IR_STATUS ( ( CRL_APB_BASEADDR ) + ((u32)0X00000004U) )
#define CRL_APB_IR_STATUS_ADDR_DECODE_ERR_SHIFT 0
#define CRL_APB_IR_STATUS_ADDR_DECODE_ERR_WIDTH 1
#define CRL_APB_IR_STATUS_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_IR_MASK
*/
#define CRL_APB_IR_MASK ( ( CRL_APB_BASEADDR ) + ((u32)0X00000008U) )
#define CRL_APB_IR_MASK_ADDR_DECODE_ERR_SHIFT 0
#define CRL_APB_IR_MASK_ADDR_DECODE_ERR_WIDTH 1
#define CRL_APB_IR_MASK_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_IR_ENABLE
*/
#define CRL_APB_IR_ENABLE ( ( CRL_APB_BASEADDR ) + ((u32)0X0000000CU) )
#define CRL_APB_IR_ENABLE_ADDR_DECODE_ERR_SHIFT 0
#define CRL_APB_IR_ENABLE_ADDR_DECODE_ERR_WIDTH 1
#define CRL_APB_IR_ENABLE_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_IR_DISABLE
*/
#define CRL_APB_IR_DISABLE ( ( CRL_APB_BASEADDR ) + ((u32)0X00000010U) )
#define CRL_APB_IR_DISABLE_ADDR_DECODE_ERR_SHIFT 0
#define CRL_APB_IR_DISABLE_ADDR_DECODE_ERR_WIDTH 1
#define CRL_APB_IR_DISABLE_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CRL_ECO
*/
#define CRL_APB_CRL_ECO ( ( CRL_APB_BASEADDR ) + ((u32)0X00000018U) )
#define CRL_APB_CRL_ECO_REG_SHIFT 0
#define CRL_APB_CRL_ECO_REG_WIDTH 32
#define CRL_APB_CRL_ECO_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CRL_WPROT
*/
#define CRL_APB_CRL_WPROT ( ( CRL_APB_BASEADDR ) + ((u32)0X0000001CU) )
#define CRL_APB_CRL_WPROT_ACTIVE_SHIFT 0
#define CRL_APB_CRL_WPROT_ACTIVE_WIDTH 1
#define CRL_APB_CRL_WPROT_ACTIVE_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_IOPLL_CTRL
*/
#define CRL_APB_IOPLL_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000020U) )
#define CRL_APB_IOPLL_CTRL_POST_SRC_SHIFT 24
#define CRL_APB_IOPLL_CTRL_POST_SRC_WIDTH 3
#define CRL_APB_IOPLL_CTRL_POST_SRC_MASK ((u32)0X07000000U)
#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20
#define CRL_APB_IOPLL_CTRL_PRE_SRC_WIDTH 3
#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK ((u32)0X00700000U)
#define CRL_APB_IOPLL_CTRL_CLKOUTDIV_SHIFT 17
#define CRL_APB_IOPLL_CTRL_CLKOUTDIV_WIDTH 1
#define CRL_APB_IOPLL_CTRL_CLKOUTDIV_MASK ((u32)0X00020000U)
#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16
#define CRL_APB_IOPLL_CTRL_DIV2_WIDTH 1
#define CRL_APB_IOPLL_CTRL_DIV2_MASK ((u32)0X00010000U)
#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8
#define CRL_APB_IOPLL_CTRL_FBDIV_WIDTH 7
#define CRL_APB_IOPLL_CTRL_FBDIV_MASK ((u32)0X00007F00U)
#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3
#define CRL_APB_IOPLL_CTRL_BYPASS_WIDTH 1
#define CRL_APB_IOPLL_CTRL_BYPASS_MASK ((u32)0X00000008U)
#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0
#define CRL_APB_IOPLL_CTRL_RESET_WIDTH 1
#define CRL_APB_IOPLL_CTRL_RESET_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_IOPLL_CFG
*/
#define CRL_APB_IOPLL_CFG ( ( CRL_APB_BASEADDR ) + ((u32)0X00000024U) )
#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25
#define CRL_APB_IOPLL_CFG_LOCK_DLY_WIDTH 7
#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK ((u32)0XFE000000U)
#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13
#define CRL_APB_IOPLL_CFG_LOCK_CNT_WIDTH 10
#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK ((u32)0X007FE000U)
#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10
#define CRL_APB_IOPLL_CFG_LFHF_WIDTH 2
#define CRL_APB_IOPLL_CFG_LFHF_MASK ((u32)0X00000C00U)
#define CRL_APB_IOPLL_CFG_CP_SHIFT 5
#define CRL_APB_IOPLL_CFG_CP_WIDTH 4
#define CRL_APB_IOPLL_CFG_CP_MASK ((u32)0X000001E0U)
#define CRL_APB_IOPLL_CFG_RES_SHIFT 0
#define CRL_APB_IOPLL_CFG_RES_WIDTH 4
#define CRL_APB_IOPLL_CFG_RES_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_IOPLL_FRAC_CFG
*/
#define CRL_APB_IOPLL_FRAC_CFG ( ( CRL_APB_BASEADDR ) + ((u32)0X00000028U) )
#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 31
#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_WIDTH 1
#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK ((u32)0X80000000U)
#define CRL_APB_IOPLL_FRAC_CFG_SEED_SHIFT 22
#define CRL_APB_IOPLL_FRAC_CFG_SEED_WIDTH 3
#define CRL_APB_IOPLL_FRAC_CFG_SEED_MASK ((u32)0X01C00000U)
#define CRL_APB_IOPLL_FRAC_CFG_ALGRTHM_SHIFT 19
#define CRL_APB_IOPLL_FRAC_CFG_ALGRTHM_WIDTH 1
#define CRL_APB_IOPLL_FRAC_CFG_ALGRTHM_MASK ((u32)0X00080000U)
#define CRL_APB_IOPLL_FRAC_CFG_ORDER_SHIFT 18
#define CRL_APB_IOPLL_FRAC_CFG_ORDER_WIDTH 1
#define CRL_APB_IOPLL_FRAC_CFG_ORDER_MASK ((u32)0X00040000U)
#define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 0
#define CRL_APB_IOPLL_FRAC_CFG_DATA_WIDTH 16
#define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK ((u32)0X0000FFFFU)
/**
* Register: CRL_APB_RPLL_CTRL
*/
#define CRL_APB_RPLL_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000030U) )
#define CRL_APB_RPLL_CTRL_POST_SRC_SHIFT 24
#define CRL_APB_RPLL_CTRL_POST_SRC_WIDTH 3
#define CRL_APB_RPLL_CTRL_POST_SRC_MASK ((u32)0X07000000U)
#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20
#define CRL_APB_RPLL_CTRL_PRE_SRC_WIDTH 3
#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK ((u32)0X00700000U)
#define CRL_APB_RPLL_CTRL_CLKOUTDIV_SHIFT 17
#define CRL_APB_RPLL_CTRL_CLKOUTDIV_WIDTH 1
#define CRL_APB_RPLL_CTRL_CLKOUTDIV_MASK ((u32)0X00020000U)
#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16
#define CRL_APB_RPLL_CTRL_DIV2_WIDTH 1
#define CRL_APB_RPLL_CTRL_DIV2_MASK ((u32)0X00010000U)
#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8
#define CRL_APB_RPLL_CTRL_FBDIV_WIDTH 7
#define CRL_APB_RPLL_CTRL_FBDIV_MASK ((u32)0X00007F00U)
#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3
#define CRL_APB_RPLL_CTRL_BYPASS_WIDTH 1
#define CRL_APB_RPLL_CTRL_BYPASS_MASK ((u32)0X00000008U)
#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0
#define CRL_APB_RPLL_CTRL_RESET_WIDTH 1
#define CRL_APB_RPLL_CTRL_RESET_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_RPLL_CFG
*/
#define CRL_APB_RPLL_CFG ( ( CRL_APB_BASEADDR ) + ((u32)0X00000034U) )
#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25
#define CRL_APB_RPLL_CFG_LOCK_DLY_WIDTH 7
#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK ((u32)0XFE000000U)
#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13
#define CRL_APB_RPLL_CFG_LOCK_CNT_WIDTH 10
#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK ((u32)0X007FE000U)
#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10
#define CRL_APB_RPLL_CFG_LFHF_WIDTH 2
#define CRL_APB_RPLL_CFG_LFHF_MASK ((u32)0X00000C00U)
#define CRL_APB_RPLL_CFG_CP_SHIFT 5
#define CRL_APB_RPLL_CFG_CP_WIDTH 4
#define CRL_APB_RPLL_CFG_CP_MASK ((u32)0X000001E0U)
#define CRL_APB_RPLL_CFG_RES_SHIFT 0
#define CRL_APB_RPLL_CFG_RES_WIDTH 4
#define CRL_APB_RPLL_CFG_RES_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_RPLL_FRAC_CFG
*/
#define CRL_APB_RPLL_FRAC_CFG ( ( CRL_APB_BASEADDR ) + ((u32)0X00000038U) )
#define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 31
#define CRL_APB_RPLL_FRAC_CFG_ENABLED_WIDTH 1
#define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK ((u32)0X80000000U)
#define CRL_APB_RPLL_FRAC_CFG_SEED_SHIFT 22
#define CRL_APB_RPLL_FRAC_CFG_SEED_WIDTH 3
#define CRL_APB_RPLL_FRAC_CFG_SEED_MASK ((u32)0X01C00000U)
#define CRL_APB_RPLL_FRAC_CFG_ALGRTHM_SHIFT 19
#define CRL_APB_RPLL_FRAC_CFG_ALGRTHM_WIDTH 1
#define CRL_APB_RPLL_FRAC_CFG_ALGRTHM_MASK ((u32)0X00080000U)
#define CRL_APB_RPLL_FRAC_CFG_ORDER_SHIFT 18
#define CRL_APB_RPLL_FRAC_CFG_ORDER_WIDTH 1
#define CRL_APB_RPLL_FRAC_CFG_ORDER_MASK ((u32)0X00040000U)
#define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 0
#define CRL_APB_RPLL_FRAC_CFG_DATA_WIDTH 16
#define CRL_APB_RPLL_FRAC_CFG_DATA_MASK ((u32)0X0000FFFFU)
/**
* Register: CRL_APB_PLL_STATUS
*/
#define CRL_APB_PLL_STATUS ( ( CRL_APB_BASEADDR ) + ((u32)0X00000040U) )
#define CRL_APB_PLL_STATUS_RPLL_STABLE_SHIFT 4
#define CRL_APB_PLL_STATUS_RPLL_STABLE_WIDTH 1
#define CRL_APB_PLL_STATUS_RPLL_STABLE_MASK ((u32)0X00000010U)
#define CRL_APB_PLL_STATUS_IOPLL_STABLE_SHIFT 3
#define CRL_APB_PLL_STATUS_IOPLL_STABLE_WIDTH 1
#define CRL_APB_PLL_STATUS_IOPLL_STABLE_MASK ((u32)0X00000008U)
#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1
#define CRL_APB_PLL_STATUS_RPLL_LOCK_WIDTH 1
#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK ((u32)0X00000002U)
#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0
#define CRL_APB_PLL_STATUS_IOPLL_LOCK_WIDTH 1
#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_IOPLL_TO_FPD_CTRL
*/
#define CRL_APB_IOPLL_TO_FPD_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000044U) )
#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
/**
* Register: CRL_APB_RPLL_TO_FPD_CTRL
*/
#define CRL_APB_RPLL_TO_FPD_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000048U) )
#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
/**
* Register: CRL_APB_USB3_DUAL_REF_CTRL
*/
#define CRL_APB_USB3_DUAL_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000004CU) )
#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25
#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK ((u32)0X02000000U)
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_GEM0_REF_CTRL
*/
#define CRL_APB_GEM0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000050U) )
#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 26
#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_WIDTH 1
#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK ((u32)0X04000000U)
#define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 25
#define CRL_APB_GEM0_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK ((u32)0X02000000U)
#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_GEM0_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_GEM1_REF_CTRL
*/
#define CRL_APB_GEM1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000054U) )
#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 26
#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_WIDTH 1
#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK ((u32)0X04000000U)
#define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 25
#define CRL_APB_GEM1_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK ((u32)0X02000000U)
#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_GEM1_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_GEM2_REF_CTRL
*/
#define CRL_APB_GEM2_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000058U) )
#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 26
#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_WIDTH 1
#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK ((u32)0X04000000U)
#define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 25
#define CRL_APB_GEM2_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK ((u32)0X02000000U)
#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_GEM2_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_GEM3_REF_CTRL
*/
#define CRL_APB_GEM3_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000005CU) )
#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26
#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_WIDTH 1
#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK ((u32)0X04000000U)
#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25
#define CRL_APB_GEM3_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK ((u32)0X02000000U)
#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_USB0_BUS_REF_CTRL
*/
#define CRL_APB_USB0_BUS_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000060U) )
#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25
#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK ((u32)0X02000000U)
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_USB1_BUS_REF_CTRL
*/
#define CRL_APB_USB1_BUS_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000064U) )
#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT 25
#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK ((u32)0X02000000U)
#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_QSPI_REF_CTRL
*/
#define CRL_APB_QSPI_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000068U) )
#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_QSPI_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_SDIO0_REF_CTRL
*/
#define CRL_APB_SDIO0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000006CU) )
#define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_SDIO0_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_SDIO1_REF_CTRL
*/
#define CRL_APB_SDIO1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000070U) )
#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_SDIO1_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_UART0_REF_CTRL
*/
#define CRL_APB_UART0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000074U) )
#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_UART0_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_UART0_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_UART0_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_UART0_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_UART1_REF_CTRL
*/
#define CRL_APB_UART1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000078U) )
#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_UART1_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_UART1_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_UART1_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_UART1_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_SPI0_REF_CTRL
*/
#define CRL_APB_SPI0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000007CU) )
#define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_SPI0_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_SPI0_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_SPI1_REF_CTRL
*/
#define CRL_APB_SPI1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000080U) )
#define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_SPI1_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_SPI1_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_CAN0_REF_CTRL
*/
#define CRL_APB_CAN0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000084U) )
#define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_CAN0_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_CAN0_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_CAN1_REF_CTRL
*/
#define CRL_APB_CAN1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000088U) )
#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_CAN1_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_CAN1_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_CPU_R5_CTRL
*/
#define CRL_APB_CPU_R5_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000090U) )
#define CRL_APB_CPU_R5_CTRL_CLKACT_CORE_SHIFT 25
#define CRL_APB_CPU_R5_CTRL_CLKACT_CORE_WIDTH 1
#define CRL_APB_CPU_R5_CTRL_CLKACT_CORE_MASK ((u32)0X02000000U)
#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24
#define CRL_APB_CPU_R5_CTRL_CLKACT_WIDTH 1
#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_CPU_R5_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_CPU_R5_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_IOU_SWITCH_CTRL
*/
#define CRL_APB_IOU_SWITCH_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000009CU) )
#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24
#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_WIDTH 1
#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_CSU_PLL_CTRL
*/
#define CRL_APB_CSU_PLL_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000A0U) )
#define CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT 24
#define CRL_APB_CSU_PLL_CTRL_CLKACT_WIDTH 1
#define CRL_APB_CSU_PLL_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_CSU_PLL_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_PCAP_CTRL
*/
#define CRL_APB_PCAP_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000A4U) )
#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24
#define CRL_APB_PCAP_CTRL_CLKACT_WIDTH 1
#define CRL_APB_PCAP_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_PCAP_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_PCAP_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_PCAP_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_LPD_SWITCH_CTRL
*/
#define CRL_APB_LPD_SWITCH_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000A8U) )
#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24
#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_WIDTH 1
#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_LPD_LSBUS_CTRL
*/
#define CRL_APB_LPD_LSBUS_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000ACU) )
#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24
#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_WIDTH 1
#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_DBG_LPD_CTRL
*/
#define CRL_APB_DBG_LPD_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000B0U) )
#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24
#define CRL_APB_DBG_LPD_CTRL_CLKACT_WIDTH 1
#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_NAND_REF_CTRL
*/
#define CRL_APB_NAND_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000B4U) )
#define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_NAND_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_NAND_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_NAND_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_NAND_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_NAND_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_ADMA_REF_CTRL
*/
#define CRL_APB_ADMA_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000B8U) )
#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_ADMA_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_ADMA_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_PL0_REF_CTRL
*/
#define CRL_APB_PL0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000C0U) )
#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_PL0_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_PL0_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_PL0_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_PL0_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_PL1_REF_CTRL
*/
#define CRL_APB_PL1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000C4U) )
#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_PL1_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_PL1_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_PL1_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_PL1_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_PL2_REF_CTRL
*/
#define CRL_APB_PL2_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000C8U) )
#define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_PL2_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_PL2_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_PL2_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_PL2_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_PL2_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_PL3_REF_CTRL
*/
#define CRL_APB_PL3_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000CCU) )
#define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_PL3_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_PL3_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_PL3_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_PL3_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_PL3_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_PL0_THR_CTRL
*/
#define CRL_APB_PL0_THR_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000D0U) )
#define CRL_APB_PL0_THR_CTRL_CURR_VAL_SHIFT 16
#define CRL_APB_PL0_THR_CTRL_CURR_VAL_WIDTH 16
#define CRL_APB_PL0_THR_CTRL_CURR_VAL_MASK ((u32)0XFFFF0000U)
#define CRL_APB_PL0_THR_CTRL_RUNNING_SHIFT 15
#define CRL_APB_PL0_THR_CTRL_RUNNING_WIDTH 1
#define CRL_APB_PL0_THR_CTRL_RUNNING_MASK ((u32)0X00008000U)
#define CRL_APB_PL0_THR_CTRL_CPU_START_SHIFT 1
#define CRL_APB_PL0_THR_CTRL_CPU_START_WIDTH 1
#define CRL_APB_PL0_THR_CTRL_CPU_START_MASK ((u32)0X00000002U)
#define CRL_APB_PL0_THR_CTRL_CNT_RST_SHIFT 0
#define CRL_APB_PL0_THR_CTRL_CNT_RST_WIDTH 1
#define CRL_APB_PL0_THR_CTRL_CNT_RST_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_PL0_THR_CNT
*/
#define CRL_APB_PL0_THR_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000000D4U) )
#define CRL_APB_PL0_THR_CNT_LAST_CNT_SHIFT 0
#define CRL_APB_PL0_THR_CNT_LAST_CNT_WIDTH 16
#define CRL_APB_PL0_THR_CNT_LAST_CNT_MASK ((u32)0X0000FFFFU)
/**
* Register: CRL_APB_PL1_THR_CTRL
*/
#define CRL_APB_PL1_THR_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000D8U) )
#define CRL_APB_PL1_THR_CTRL_CURR_VAL_SHIFT 16
#define CRL_APB_PL1_THR_CTRL_CURR_VAL_WIDTH 16
#define CRL_APB_PL1_THR_CTRL_CURR_VAL_MASK ((u32)0XFFFF0000U)
#define CRL_APB_PL1_THR_CTRL_RUNNING_SHIFT 15
#define CRL_APB_PL1_THR_CTRL_RUNNING_WIDTH 1
#define CRL_APB_PL1_THR_CTRL_RUNNING_MASK ((u32)0X00008000U)
#define CRL_APB_PL1_THR_CTRL_CPU_START_SHIFT 1
#define CRL_APB_PL1_THR_CTRL_CPU_START_WIDTH 1
#define CRL_APB_PL1_THR_CTRL_CPU_START_MASK ((u32)0X00000002U)
#define CRL_APB_PL1_THR_CTRL_CNT_RST_SHIFT 0
#define CRL_APB_PL1_THR_CTRL_CNT_RST_WIDTH 1
#define CRL_APB_PL1_THR_CTRL_CNT_RST_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_PL1_THR_CNT
*/
#define CRL_APB_PL1_THR_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000000DCU) )
#define CRL_APB_PL1_THR_CNT_LAST_CNT_SHIFT 0
#define CRL_APB_PL1_THR_CNT_LAST_CNT_WIDTH 16
#define CRL_APB_PL1_THR_CNT_LAST_CNT_MASK ((u32)0X0000FFFFU)
/**
* Register: CRL_APB_PL2_THR_CTRL
*/
#define CRL_APB_PL2_THR_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000E0U) )
#define CRL_APB_PL2_THR_CTRL_CURR_VAL_SHIFT 16
#define CRL_APB_PL2_THR_CTRL_CURR_VAL_WIDTH 16
#define CRL_APB_PL2_THR_CTRL_CURR_VAL_MASK ((u32)0XFFFF0000U)
#define CRL_APB_PL2_THR_CTRL_RUNNING_SHIFT 15
#define CRL_APB_PL2_THR_CTRL_RUNNING_WIDTH 1
#define CRL_APB_PL2_THR_CTRL_RUNNING_MASK ((u32)0X00008000U)
#define CRL_APB_PL2_THR_CTRL_CPU_START_SHIFT 1
#define CRL_APB_PL2_THR_CTRL_CPU_START_WIDTH 1
#define CRL_APB_PL2_THR_CTRL_CPU_START_MASK ((u32)0X00000002U)
#define CRL_APB_PL2_THR_CTRL_CNT_RST_SHIFT 0
#define CRL_APB_PL2_THR_CTRL_CNT_RST_WIDTH 1
#define CRL_APB_PL2_THR_CTRL_CNT_RST_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_PL2_THR_CNT
*/
#define CRL_APB_PL2_THR_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000000E4U) )
#define CRL_APB_PL2_THR_CNT_LAST_CNT_SHIFT 0
#define CRL_APB_PL2_THR_CNT_LAST_CNT_WIDTH 16
#define CRL_APB_PL2_THR_CNT_LAST_CNT_MASK ((u32)0X0000FFFFU)
/**
* Register: CRL_APB_PL3_THR_CTRL
*/
#define CRL_APB_PL3_THR_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000E8U) )
#define CRL_APB_PL3_THR_CTRL_CURR_VAL_SHIFT 16
#define CRL_APB_PL3_THR_CTRL_CURR_VAL_WIDTH 16
#define CRL_APB_PL3_THR_CTRL_CURR_VAL_MASK ((u32)0XFFFF0000U)
#define CRL_APB_PL3_THR_CTRL_RUNNING_SHIFT 15
#define CRL_APB_PL3_THR_CTRL_RUNNING_WIDTH 1
#define CRL_APB_PL3_THR_CTRL_RUNNING_MASK ((u32)0X00008000U)
#define CRL_APB_PL3_THR_CTRL_CPU_START_SHIFT 1
#define CRL_APB_PL3_THR_CTRL_CPU_START_WIDTH 1
#define CRL_APB_PL3_THR_CTRL_CPU_START_MASK ((u32)0X00000002U)
#define CRL_APB_PL3_THR_CTRL_CNT_RST_SHIFT 0
#define CRL_APB_PL3_THR_CTRL_CNT_RST_WIDTH 1
#define CRL_APB_PL3_THR_CTRL_CNT_RST_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_PL3_THR_CNT
*/
#define CRL_APB_PL3_THR_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000000FCU) )
#define CRL_APB_PL3_THR_CNT_LAST_CNT_SHIFT 0
#define CRL_APB_PL3_THR_CNT_LAST_CNT_WIDTH 16
#define CRL_APB_PL3_THR_CNT_LAST_CNT_MASK ((u32)0X0000FFFFU)
/**
* Register: CRL_APB_GEM_TSU_REF_CTRL
*/
#define CRL_APB_GEM_TSU_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000100U) )
#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_DLL_REF_CTRL
*/
#define CRL_APB_DLL_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000104U) )
#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_DLL_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_AMS_REF_CTRL
*/
#define CRL_APB_AMS_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000108U) )
#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_AMS_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_AMS_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_AMS_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_AMS_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_I2C0_REF_CTRL
*/
#define CRL_APB_I2C0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000120U) )
#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_I2C0_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_I2C0_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_I2C1_REF_CTRL
*/
#define CRL_APB_I2C1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000124U) )
#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_I2C1_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_TIMESTAMP_REF_CTRL
*/
#define CRL_APB_TIMESTAMP_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000128U) )
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_SAFTEY_CHK
*/
#define CRL_APB_SAFTEY_CHK ( ( CRL_APB_BASEADDR ) + ((u32)0X00000130U) )
#define CRL_APB_SAFTEY_CHK_CHK_VAL_SHIFT 0
#define CRL_APB_SAFTEY_CHK_CHK_VAL_WIDTH 32
#define CRL_APB_SAFTEY_CHK_CHK_VAL_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CLKMON_STATUS
*/
#define CRL_APB_CLKMON_STATUS ( ( CRL_APB_BASEADDR ) + ((u32)0X00000140U) )
#define CRL_APB_CLKMON_STATUS_CNTA7_OVER_ERR_SHIFT 15
#define CRL_APB_CLKMON_STATUS_CNTA7_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_CNTA7_OVER_ERR_MASK ((u32)0X00008000U)
#define CRL_APB_CLKMON_STATUS_MON7_ERR_SHIFT 14
#define CRL_APB_CLKMON_STATUS_MON7_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_MON7_ERR_MASK ((u32)0X00004000U)
#define CRL_APB_CLKMON_STATUS_CNTA6_OVER_ERR_SHIFT 13
#define CRL_APB_CLKMON_STATUS_CNTA6_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_CNTA6_OVER_ERR_MASK ((u32)0X00002000U)
#define CRL_APB_CLKMON_STATUS_MON6_ERR_SHIFT 12
#define CRL_APB_CLKMON_STATUS_MON6_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_MON6_ERR_MASK ((u32)0X00001000U)
#define CRL_APB_CLKMON_STATUS_CNTA5_OVER_ERR_SHIFT 11
#define CRL_APB_CLKMON_STATUS_CNTA5_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_CNTA5_OVER_ERR_MASK ((u32)0X00000800U)
#define CRL_APB_CLKMON_STATUS_MON5_ERR_SHIFT 10
#define CRL_APB_CLKMON_STATUS_MON5_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_MON5_ERR_MASK ((u32)0X00000400U)
#define CRL_APB_CLKMON_STATUS_CNTA4_OVER_ERR_SHIFT 9
#define CRL_APB_CLKMON_STATUS_CNTA4_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_CNTA4_OVER_ERR_MASK ((u32)0X00000200U)
#define CRL_APB_CLKMON_STATUS_MON4_ERR_SHIFT 8
#define CRL_APB_CLKMON_STATUS_MON4_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_MON4_ERR_MASK ((u32)0X00000100U)
#define CRL_APB_CLKMON_STATUS_CNTA3_OVER_ERR_SHIFT 7
#define CRL_APB_CLKMON_STATUS_CNTA3_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_CNTA3_OVER_ERR_MASK ((u32)0X00000080U)
#define CRL_APB_CLKMON_STATUS_MON3_ERR_SHIFT 6
#define CRL_APB_CLKMON_STATUS_MON3_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_MON3_ERR_MASK ((u32)0X00000040U)
#define CRL_APB_CLKMON_STATUS_CNTA2_OVER_ERR_SHIFT 5
#define CRL_APB_CLKMON_STATUS_CNTA2_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_CNTA2_OVER_ERR_MASK ((u32)0X00000020U)
#define CRL_APB_CLKMON_STATUS_MON2_ERR_SHIFT 4
#define CRL_APB_CLKMON_STATUS_MON2_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_MON2_ERR_MASK ((u32)0X00000010U)
#define CRL_APB_CLKMON_STATUS_CNTA1_OVER_ERR_SHIFT 3
#define CRL_APB_CLKMON_STATUS_CNTA1_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_CNTA1_OVER_ERR_MASK ((u32)0X00000008U)
#define CRL_APB_CLKMON_STATUS_MON1_ERR_SHIFT 2
#define CRL_APB_CLKMON_STATUS_MON1_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_MON1_ERR_MASK ((u32)0X00000004U)
#define CRL_APB_CLKMON_STATUS_CNTA0_OVER_ERR_SHIFT 1
#define CRL_APB_CLKMON_STATUS_CNTA0_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_CNTA0_OVER_ERR_MASK ((u32)0X00000002U)
#define CRL_APB_CLKMON_STATUS_MON0_ERR_SHIFT 0
#define CRL_APB_CLKMON_STATUS_MON0_ERR_WIDTH 1
#define CRL_APB_CLKMON_STATUS_MON0_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CLKMON_MASK
*/
#define CRL_APB_CLKMON_MASK ( ( CRL_APB_BASEADDR ) + ((u32)0X00000144U) )
#define CRL_APB_CLKMON_MASK_CNTA7_OVER_ERR_SHIFT 15
#define CRL_APB_CLKMON_MASK_CNTA7_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_CNTA7_OVER_ERR_MASK ((u32)0X00008000U)
#define CRL_APB_CLKMON_MASK_MON7_ERR_SHIFT 14
#define CRL_APB_CLKMON_MASK_MON7_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_MON7_ERR_MASK ((u32)0X00004000U)
#define CRL_APB_CLKMON_MASK_CNTA6_OVER_ERR_SHIFT 13
#define CRL_APB_CLKMON_MASK_CNTA6_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_CNTA6_OVER_ERR_MASK ((u32)0X00002000U)
#define CRL_APB_CLKMON_MASK_MON6_ERR_SHIFT 12
#define CRL_APB_CLKMON_MASK_MON6_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_MON6_ERR_MASK ((u32)0X00001000U)
#define CRL_APB_CLKMON_MASK_CNTA5_OVER_ERR_SHIFT 11
#define CRL_APB_CLKMON_MASK_CNTA5_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_CNTA5_OVER_ERR_MASK ((u32)0X00000800U)
#define CRL_APB_CLKMON_MASK_MON5_ERR_SHIFT 10
#define CRL_APB_CLKMON_MASK_MON5_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_MON5_ERR_MASK ((u32)0X00000400U)
#define CRL_APB_CLKMON_MASK_CNTA4_OVER_ERR_SHIFT 9
#define CRL_APB_CLKMON_MASK_CNTA4_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_CNTA4_OVER_ERR_MASK ((u32)0X00000200U)
#define CRL_APB_CLKMON_MASK_MON4_ERR_SHIFT 8
#define CRL_APB_CLKMON_MASK_MON4_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_MON4_ERR_MASK ((u32)0X00000100U)
#define CRL_APB_CLKMON_MASK_CNTA3_OVER_ERR_SHIFT 7
#define CRL_APB_CLKMON_MASK_CNTA3_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_CNTA3_OVER_ERR_MASK ((u32)0X00000080U)
#define CRL_APB_CLKMON_MASK_MON3_ERR_SHIFT 6
#define CRL_APB_CLKMON_MASK_MON3_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_MON3_ERR_MASK ((u32)0X00000040U)
#define CRL_APB_CLKMON_MASK_CNTA2_OVER_ERR_SHIFT 5
#define CRL_APB_CLKMON_MASK_CNTA2_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_CNTA2_OVER_ERR_MASK ((u32)0X00000020U)
#define CRL_APB_CLKMON_MASK_MON2_ERR_SHIFT 4
#define CRL_APB_CLKMON_MASK_MON2_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_MON2_ERR_MASK ((u32)0X00000010U)
#define CRL_APB_CLKMON_MASK_CNTA1_OVER_ERR_SHIFT 3
#define CRL_APB_CLKMON_MASK_CNTA1_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_CNTA1_OVER_ERR_MASK ((u32)0X00000008U)
#define CRL_APB_CLKMON_MASK_MON1_ERR_SHIFT 2
#define CRL_APB_CLKMON_MASK_MON1_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_MON1_ERR_MASK ((u32)0X00000004U)
#define CRL_APB_CLKMON_MASK_CNTA0_OVER_ERR_SHIFT 1
#define CRL_APB_CLKMON_MASK_CNTA0_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_CNTA0_OVER_ERR_MASK ((u32)0X00000002U)
#define CRL_APB_CLKMON_MASK_MON0_ERR_SHIFT 0
#define CRL_APB_CLKMON_MASK_MON0_ERR_WIDTH 1
#define CRL_APB_CLKMON_MASK_MON0_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CLKMON_ENABLE
*/
#define CRL_APB_CLKMON_ENABLE ( ( CRL_APB_BASEADDR ) + ((u32)0X00000148U) )
#define CRL_APB_CLKMON_ENABLE_CNTA7_OVER_ERR_SHIFT 15
#define CRL_APB_CLKMON_ENABLE_CNTA7_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_CNTA7_OVER_ERR_MASK ((u32)0X00008000U)
#define CRL_APB_CLKMON_ENABLE_MON7_ERR_SHIFT 14
#define CRL_APB_CLKMON_ENABLE_MON7_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_MON7_ERR_MASK ((u32)0X00004000U)
#define CRL_APB_CLKMON_ENABLE_CNTA6_OVER_ERR_SHIFT 13
#define CRL_APB_CLKMON_ENABLE_CNTA6_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_CNTA6_OVER_ERR_MASK ((u32)0X00002000U)
#define CRL_APB_CLKMON_ENABLE_MON6_ERR_SHIFT 12
#define CRL_APB_CLKMON_ENABLE_MON6_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_MON6_ERR_MASK ((u32)0X00001000U)
#define CRL_APB_CLKMON_ENABLE_CNTA5_OVER_ERR_SHIFT 11
#define CRL_APB_CLKMON_ENABLE_CNTA5_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_CNTA5_OVER_ERR_MASK ((u32)0X00000800U)
#define CRL_APB_CLKMON_ENABLE_MON5_ERR_SHIFT 10
#define CRL_APB_CLKMON_ENABLE_MON5_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_MON5_ERR_MASK ((u32)0X00000400U)
#define CRL_APB_CLKMON_ENABLE_CNTA4_OVER_ERR_SHIFT 9
#define CRL_APB_CLKMON_ENABLE_CNTA4_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_CNTA4_OVER_ERR_MASK ((u32)0X00000200U)
#define CRL_APB_CLKMON_ENABLE_MON4_ERR_SHIFT 8
#define CRL_APB_CLKMON_ENABLE_MON4_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_MON4_ERR_MASK ((u32)0X00000100U)
#define CRL_APB_CLKMON_ENABLE_CNTA3_OVER_ERR_SHIFT 7
#define CRL_APB_CLKMON_ENABLE_CNTA3_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_CNTA3_OVER_ERR_MASK ((u32)0X00000080U)
#define CRL_APB_CLKMON_ENABLE_MON3_ERR_SHIFT 6
#define CRL_APB_CLKMON_ENABLE_MON3_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_MON3_ERR_MASK ((u32)0X00000040U)
#define CRL_APB_CLKMON_ENABLE_CNTA2_OVER_ERR_SHIFT 5
#define CRL_APB_CLKMON_ENABLE_CNTA2_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_CNTA2_OVER_ERR_MASK ((u32)0X00000020U)
#define CRL_APB_CLKMON_ENABLE_MON2_ERR_SHIFT 4
#define CRL_APB_CLKMON_ENABLE_MON2_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_MON2_ERR_MASK ((u32)0X00000010U)
#define CRL_APB_CLKMON_ENABLE_CNTA1_OVER_ERR_SHIFT 3
#define CRL_APB_CLKMON_ENABLE_CNTA1_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_CNTA1_OVER_ERR_MASK ((u32)0X00000008U)
#define CRL_APB_CLKMON_ENABLE_MON1_ERR_SHIFT 2
#define CRL_APB_CLKMON_ENABLE_MON1_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_MON1_ERR_MASK ((u32)0X00000004U)
#define CRL_APB_CLKMON_ENABLE_CNTA0_OVER_ERR_SHIFT 1
#define CRL_APB_CLKMON_ENABLE_CNTA0_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_CNTA0_OVER_ERR_MASK ((u32)0X00000002U)
#define CRL_APB_CLKMON_ENABLE_MON0_ERR_SHIFT 0
#define CRL_APB_CLKMON_ENABLE_MON0_ERR_WIDTH 1
#define CRL_APB_CLKMON_ENABLE_MON0_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CLKMON_DISABLE
*/
#define CRL_APB_CLKMON_DISABLE ( ( CRL_APB_BASEADDR ) + ((u32)0X0000014CU) )
#define CRL_APB_CLKMON_DISABLE_CNTA7_OVER_ERR_SHIFT 15
#define CRL_APB_CLKMON_DISABLE_CNTA7_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_CNTA7_OVER_ERR_MASK ((u32)0X00008000U)
#define CRL_APB_CLKMON_DISABLE_MON7_ERR_SHIFT 14
#define CRL_APB_CLKMON_DISABLE_MON7_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_MON7_ERR_MASK ((u32)0X00004000U)
#define CRL_APB_CLKMON_DISABLE_CNTA6_OVER_ERR_SHIFT 13
#define CRL_APB_CLKMON_DISABLE_CNTA6_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_CNTA6_OVER_ERR_MASK ((u32)0X00002000U)
#define CRL_APB_CLKMON_DISABLE_MON6_ERR_SHIFT 12
#define CRL_APB_CLKMON_DISABLE_MON6_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_MON6_ERR_MASK ((u32)0X00001000U)
#define CRL_APB_CLKMON_DISABLE_CNTA5_OVER_ERR_SHIFT 11
#define CRL_APB_CLKMON_DISABLE_CNTA5_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_CNTA5_OVER_ERR_MASK ((u32)0X00000800U)
#define CRL_APB_CLKMON_DISABLE_MON5_ERR_SHIFT 10
#define CRL_APB_CLKMON_DISABLE_MON5_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_MON5_ERR_MASK ((u32)0X00000400U)
#define CRL_APB_CLKMON_DISABLE_CNTA4_OVER_ERR_SHIFT 9
#define CRL_APB_CLKMON_DISABLE_CNTA4_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_CNTA4_OVER_ERR_MASK ((u32)0X00000200U)
#define CRL_APB_CLKMON_DISABLE_MON4_ERR_SHIFT 8
#define CRL_APB_CLKMON_DISABLE_MON4_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_MON4_ERR_MASK ((u32)0X00000100U)
#define CRL_APB_CLKMON_DISABLE_CNTA3_OVER_ERR_SHIFT 7
#define CRL_APB_CLKMON_DISABLE_CNTA3_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_CNTA3_OVER_ERR_MASK ((u32)0X00000080U)
#define CRL_APB_CLKMON_DISABLE_MON3_ERR_SHIFT 6
#define CRL_APB_CLKMON_DISABLE_MON3_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_MON3_ERR_MASK ((u32)0X00000040U)
#define CRL_APB_CLKMON_DISABLE_CNTA2_OVER_ERR_SHIFT 5
#define CRL_APB_CLKMON_DISABLE_CNTA2_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_CNTA2_OVER_ERR_MASK ((u32)0X00000020U)
#define CRL_APB_CLKMON_DISABLE_MON2_ERR_SHIFT 4
#define CRL_APB_CLKMON_DISABLE_MON2_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_MON2_ERR_MASK ((u32)0X00000010U)
#define CRL_APB_CLKMON_DISABLE_CNTA1_OVER_ERR_SHIFT 3
#define CRL_APB_CLKMON_DISABLE_CNTA1_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_CNTA1_OVER_ERR_MASK ((u32)0X00000008U)
#define CRL_APB_CLKMON_DISABLE_MON1_ERR_SHIFT 2
#define CRL_APB_CLKMON_DISABLE_MON1_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_MON1_ERR_MASK ((u32)0X00000004U)
#define CRL_APB_CLKMON_DISABLE_CNTA0_OVER_ERR_SHIFT 1
#define CRL_APB_CLKMON_DISABLE_CNTA0_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_CNTA0_OVER_ERR_MASK ((u32)0X00000002U)
#define CRL_APB_CLKMON_DISABLE_MON0_ERR_SHIFT 0
#define CRL_APB_CLKMON_DISABLE_MON0_ERR_WIDTH 1
#define CRL_APB_CLKMON_DISABLE_MON0_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CLKMON_TRIGGER
*/
#define CRL_APB_CLKMON_TRIGGER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000150U) )
#define CRL_APB_CLKMON_TRIGGER_CNTA7_OVER_ERR_SHIFT 15
#define CRL_APB_CLKMON_TRIGGER_CNTA7_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_CNTA7_OVER_ERR_MASK ((u32)0X00008000U)
#define CRL_APB_CLKMON_TRIGGER_MON7_ERR_SHIFT 14
#define CRL_APB_CLKMON_TRIGGER_MON7_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_MON7_ERR_MASK ((u32)0X00004000U)
#define CRL_APB_CLKMON_TRIGGER_CNTA6_OVER_ERR_SHIFT 13
#define CRL_APB_CLKMON_TRIGGER_CNTA6_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_CNTA6_OVER_ERR_MASK ((u32)0X00002000U)
#define CRL_APB_CLKMON_TRIGGER_MON6_ERR_SHIFT 12
#define CRL_APB_CLKMON_TRIGGER_MON6_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_MON6_ERR_MASK ((u32)0X00001000U)
#define CRL_APB_CLKMON_TRIGGER_CNTA5_OVER_ERR_SHIFT 11
#define CRL_APB_CLKMON_TRIGGER_CNTA5_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_CNTA5_OVER_ERR_MASK ((u32)0X00000800U)
#define CRL_APB_CLKMON_TRIGGER_MON5_ERR_SHIFT 10
#define CRL_APB_CLKMON_TRIGGER_MON5_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_MON5_ERR_MASK ((u32)0X00000400U)
#define CRL_APB_CLKMON_TRIGGER_CNTA4_OVER_ERR_SHIFT 9
#define CRL_APB_CLKMON_TRIGGER_CNTA4_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_CNTA4_OVER_ERR_MASK ((u32)0X00000200U)
#define CRL_APB_CLKMON_TRIGGER_MON4_ERR_SHIFT 8
#define CRL_APB_CLKMON_TRIGGER_MON4_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_MON4_ERR_MASK ((u32)0X00000100U)
#define CRL_APB_CLKMON_TRIGGER_CNTA3_OVER_ERR_SHIFT 7
#define CRL_APB_CLKMON_TRIGGER_CNTA3_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_CNTA3_OVER_ERR_MASK ((u32)0X00000080U)
#define CRL_APB_CLKMON_TRIGGER_MON3_ERR_SHIFT 6
#define CRL_APB_CLKMON_TRIGGER_MON3_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_MON3_ERR_MASK ((u32)0X00000040U)
#define CRL_APB_CLKMON_TRIGGER_CNTA2_OVER_ERR_SHIFT 5
#define CRL_APB_CLKMON_TRIGGER_CNTA2_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_CNTA2_OVER_ERR_MASK ((u32)0X00000020U)
#define CRL_APB_CLKMON_TRIGGER_MON2_ERR_SHIFT 4
#define CRL_APB_CLKMON_TRIGGER_MON2_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_MON2_ERR_MASK ((u32)0X00000010U)
#define CRL_APB_CLKMON_TRIGGER_CNTA1_OVER_ERR_SHIFT 3
#define CRL_APB_CLKMON_TRIGGER_CNTA1_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_CNTA1_OVER_ERR_MASK ((u32)0X00000008U)
#define CRL_APB_CLKMON_TRIGGER_MON1_ERR_SHIFT 2
#define CRL_APB_CLKMON_TRIGGER_MON1_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_MON1_ERR_MASK ((u32)0X00000004U)
#define CRL_APB_CLKMON_TRIGGER_CNTA0_OVER_ERR_SHIFT 1
#define CRL_APB_CLKMON_TRIGGER_CNTA0_OVER_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_CNTA0_OVER_ERR_MASK ((u32)0X00000002U)
#define CRL_APB_CLKMON_TRIGGER_MON0_ERR_SHIFT 0
#define CRL_APB_CLKMON_TRIGGER_MON0_ERR_WIDTH 1
#define CRL_APB_CLKMON_TRIGGER_MON0_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CHKR0_CLKA_UPPER
*/
#define CRL_APB_CHKR0_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000160U) )
#define CRL_APB_CHKR0_CLKA_UPPER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR0_CLKA_UPPER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR0_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR0_CLKA_LOWER
*/
#define CRL_APB_CHKR0_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000164U) )
#define CRL_APB_CHKR0_CLKA_LOWER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR0_CLKA_LOWER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR0_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR0_CLKB_CNT
*/
#define CRL_APB_CHKR0_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X00000168U) )
#define CRL_APB_CHKR0_CLKB_CNT_VALUE_SHIFT 0
#define CRL_APB_CHKR0_CLKB_CNT_VALUE_WIDTH 32
#define CRL_APB_CHKR0_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR0_CTRL
*/
#define CRL_APB_CHKR0_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000016CU) )
#define CRL_APB_CHKR0_CTRL_START_SINGLE_SHIFT 8
#define CRL_APB_CHKR0_CTRL_START_SINGLE_WIDTH 1
#define CRL_APB_CHKR0_CTRL_START_SINGLE_MASK ((u32)0X00000100U)
#define CRL_APB_CHKR0_CTRL_START_CONTINUOUS_SHIFT 7
#define CRL_APB_CHKR0_CTRL_START_CONTINUOUS_WIDTH 1
#define CRL_APB_CHKR0_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U)
#define CRL_APB_CHKR0_CTRL_CLKB_MUX_CTRL_SHIFT 5
#define CRL_APB_CHKR0_CTRL_CLKB_MUX_CTRL_WIDTH 1
#define CRL_APB_CHKR0_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U)
#define CRL_APB_CHKR0_CTRL_CLKA_MUX_CTRL_SHIFT 1
#define CRL_APB_CHKR0_CTRL_CLKA_MUX_CTRL_WIDTH 3
#define CRL_APB_CHKR0_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU)
#define CRL_APB_CHKR0_CTRL_ENABLE_SHIFT 0
#define CRL_APB_CHKR0_CTRL_ENABLE_WIDTH 1
#define CRL_APB_CHKR0_CTRL_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CHKR1_CLKA_UPPER
*/
#define CRL_APB_CHKR1_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000170U) )
#define CRL_APB_CHKR1_CLKA_UPPER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR1_CLKA_UPPER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR1_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR1_CLKA_LOWER
*/
#define CRL_APB_CHKR1_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000174U) )
#define CRL_APB_CHKR1_CLKA_LOWER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR1_CLKA_LOWER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR1_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR1_CLKB_CNT
*/
#define CRL_APB_CHKR1_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X00000178U) )
#define CRL_APB_CHKR1_CLKB_CNT_VALUE_SHIFT 0
#define CRL_APB_CHKR1_CLKB_CNT_VALUE_WIDTH 32
#define CRL_APB_CHKR1_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR1_CTRL
*/
#define CRL_APB_CHKR1_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000017CU) )
#define CRL_APB_CHKR1_CTRL_START_SINGLE_SHIFT 8
#define CRL_APB_CHKR1_CTRL_START_SINGLE_WIDTH 1
#define CRL_APB_CHKR1_CTRL_START_SINGLE_MASK ((u32)0X00000100U)
#define CRL_APB_CHKR1_CTRL_START_CONTINUOUS_SHIFT 7
#define CRL_APB_CHKR1_CTRL_START_CONTINUOUS_WIDTH 1
#define CRL_APB_CHKR1_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U)
#define CRL_APB_CHKR1_CTRL_CLKB_MUX_CTRL_SHIFT 5
#define CRL_APB_CHKR1_CTRL_CLKB_MUX_CTRL_WIDTH 1
#define CRL_APB_CHKR1_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U)
#define CRL_APB_CHKR1_CTRL_CLKA_MUX_CTRL_SHIFT 1
#define CRL_APB_CHKR1_CTRL_CLKA_MUX_CTRL_WIDTH 3
#define CRL_APB_CHKR1_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU)
#define CRL_APB_CHKR1_CTRL_ENABLE_SHIFT 0
#define CRL_APB_CHKR1_CTRL_ENABLE_WIDTH 1
#define CRL_APB_CHKR1_CTRL_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CHKR2_CLKA_UPPER
*/
#define CRL_APB_CHKR2_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000180U) )
#define CRL_APB_CHKR2_CLKA_UPPER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR2_CLKA_UPPER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR2_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR2_CLKA_LOWER
*/
#define CRL_APB_CHKR2_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000184U) )
#define CRL_APB_CHKR2_CLKA_LOWER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR2_CLKA_LOWER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR2_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR2_CLKB_CNT
*/
#define CRL_APB_CHKR2_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X00000188U) )
#define CRL_APB_CHKR2_CLKB_CNT_VALUE_SHIFT 0
#define CRL_APB_CHKR2_CLKB_CNT_VALUE_WIDTH 32
#define CRL_APB_CHKR2_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR2_CTRL
*/
#define CRL_APB_CHKR2_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000018CU) )
#define CRL_APB_CHKR2_CTRL_START_SINGLE_SHIFT 8
#define CRL_APB_CHKR2_CTRL_START_SINGLE_WIDTH 1
#define CRL_APB_CHKR2_CTRL_START_SINGLE_MASK ((u32)0X00000100U)
#define CRL_APB_CHKR2_CTRL_START_CONTINUOUS_SHIFT 7
#define CRL_APB_CHKR2_CTRL_START_CONTINUOUS_WIDTH 1
#define CRL_APB_CHKR2_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U)
#define CRL_APB_CHKR2_CTRL_CLKB_MUX_CTRL_SHIFT 5
#define CRL_APB_CHKR2_CTRL_CLKB_MUX_CTRL_WIDTH 1
#define CRL_APB_CHKR2_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U)
#define CRL_APB_CHKR2_CTRL_CLKA_MUX_CTRL_SHIFT 1
#define CRL_APB_CHKR2_CTRL_CLKA_MUX_CTRL_WIDTH 3
#define CRL_APB_CHKR2_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU)
#define CRL_APB_CHKR2_CTRL_ENABLE_SHIFT 0
#define CRL_APB_CHKR2_CTRL_ENABLE_WIDTH 1
#define CRL_APB_CHKR2_CTRL_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CHKR3_CLKA_UPPER
*/
#define CRL_APB_CHKR3_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000190U) )
#define CRL_APB_CHKR3_CLKA_UPPER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR3_CLKA_UPPER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR3_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR3_CLKA_LOWER
*/
#define CRL_APB_CHKR3_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000194U) )
#define CRL_APB_CHKR3_CLKA_LOWER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR3_CLKA_LOWER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR3_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR3_CLKB_CNT
*/
#define CRL_APB_CHKR3_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X00000198U) )
#define CRL_APB_CHKR3_CLKB_CNT_VALUE_SHIFT 0
#define CRL_APB_CHKR3_CLKB_CNT_VALUE_WIDTH 32
#define CRL_APB_CHKR3_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR3_CTRL
*/
#define CRL_APB_CHKR3_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000019CU) )
#define CRL_APB_CHKR3_CTRL_START_SINGLE_SHIFT 8
#define CRL_APB_CHKR3_CTRL_START_SINGLE_WIDTH 1
#define CRL_APB_CHKR3_CTRL_START_SINGLE_MASK ((u32)0X00000100U)
#define CRL_APB_CHKR3_CTRL_START_CONTINUOUS_SHIFT 7
#define CRL_APB_CHKR3_CTRL_START_CONTINUOUS_WIDTH 1
#define CRL_APB_CHKR3_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U)
#define CRL_APB_CHKR3_CTRL_CLKB_MUX_CTRL_SHIFT 5
#define CRL_APB_CHKR3_CTRL_CLKB_MUX_CTRL_WIDTH 1
#define CRL_APB_CHKR3_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U)
#define CRL_APB_CHKR3_CTRL_CLKA_MUX_CTRL_SHIFT 1
#define CRL_APB_CHKR3_CTRL_CLKA_MUX_CTRL_WIDTH 3
#define CRL_APB_CHKR3_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU)
#define CRL_APB_CHKR3_CTRL_ENABLE_SHIFT 0
#define CRL_APB_CHKR3_CTRL_ENABLE_WIDTH 1
#define CRL_APB_CHKR3_CTRL_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CHKR4_CLKA_UPPER
*/
#define CRL_APB_CHKR4_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001A0U) )
#define CRL_APB_CHKR4_CLKA_UPPER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR4_CLKA_UPPER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR4_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR4_CLKA_LOWER
*/
#define CRL_APB_CHKR4_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001A4U) )
#define CRL_APB_CHKR4_CLKA_LOWER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR4_CLKA_LOWER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR4_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR4_CLKB_CNT
*/
#define CRL_APB_CHKR4_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001A8U) )
#define CRL_APB_CHKR4_CLKB_CNT_VALUE_SHIFT 0
#define CRL_APB_CHKR4_CLKB_CNT_VALUE_WIDTH 32
#define CRL_APB_CHKR4_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR4_CTRL
*/
#define CRL_APB_CHKR4_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001ACU) )
#define CRL_APB_CHKR4_CTRL_START_SINGLE_SHIFT 8
#define CRL_APB_CHKR4_CTRL_START_SINGLE_WIDTH 1
#define CRL_APB_CHKR4_CTRL_START_SINGLE_MASK ((u32)0X00000100U)
#define CRL_APB_CHKR4_CTRL_START_CONTINUOUS_SHIFT 7
#define CRL_APB_CHKR4_CTRL_START_CONTINUOUS_WIDTH 1
#define CRL_APB_CHKR4_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U)
#define CRL_APB_CHKR4_CTRL_CLKB_MUX_CTRL_SHIFT 5
#define CRL_APB_CHKR4_CTRL_CLKB_MUX_CTRL_WIDTH 1
#define CRL_APB_CHKR4_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U)
#define CRL_APB_CHKR4_CTRL_CLKA_MUX_CTRL_SHIFT 1
#define CRL_APB_CHKR4_CTRL_CLKA_MUX_CTRL_WIDTH 3
#define CRL_APB_CHKR4_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU)
#define CRL_APB_CHKR4_CTRL_ENABLE_SHIFT 0
#define CRL_APB_CHKR4_CTRL_ENABLE_WIDTH 1
#define CRL_APB_CHKR4_CTRL_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CHKR5_CLKA_UPPER
*/
#define CRL_APB_CHKR5_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001B0U) )
#define CRL_APB_CHKR5_CLKA_UPPER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR5_CLKA_UPPER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR5_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR5_CLKA_LOWER
*/
#define CRL_APB_CHKR5_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001B4U) )
#define CRL_APB_CHKR5_CLKA_LOWER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR5_CLKA_LOWER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR5_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR5_CLKB_CNT
*/
#define CRL_APB_CHKR5_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001B8U) )
#define CRL_APB_CHKR5_CLKB_CNT_VALUE_SHIFT 0
#define CRL_APB_CHKR5_CLKB_CNT_VALUE_WIDTH 32
#define CRL_APB_CHKR5_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR5_CTRL
*/
#define CRL_APB_CHKR5_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001BCU) )
#define CRL_APB_CHKR5_CTRL_START_SINGLE_SHIFT 8
#define CRL_APB_CHKR5_CTRL_START_SINGLE_WIDTH 1
#define CRL_APB_CHKR5_CTRL_START_SINGLE_MASK ((u32)0X00000100U)
#define CRL_APB_CHKR5_CTRL_START_CONTINUOUS_SHIFT 7
#define CRL_APB_CHKR5_CTRL_START_CONTINUOUS_WIDTH 1
#define CRL_APB_CHKR5_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U)
#define CRL_APB_CHKR5_CTRL_CLKB_MUX_CTRL_SHIFT 5
#define CRL_APB_CHKR5_CTRL_CLKB_MUX_CTRL_WIDTH 1
#define CRL_APB_CHKR5_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U)
#define CRL_APB_CHKR5_CTRL_CLKA_MUX_CTRL_SHIFT 1
#define CRL_APB_CHKR5_CTRL_CLKA_MUX_CTRL_WIDTH 3
#define CRL_APB_CHKR5_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU)
#define CRL_APB_CHKR5_CTRL_ENABLE_SHIFT 0
#define CRL_APB_CHKR5_CTRL_ENABLE_WIDTH 1
#define CRL_APB_CHKR5_CTRL_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CHKR6_CLKA_UPPER
*/
#define CRL_APB_CHKR6_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001C0U) )
#define CRL_APB_CHKR6_CLKA_UPPER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR6_CLKA_UPPER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR6_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR6_CLKA_LOWER
*/
#define CRL_APB_CHKR6_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001C4U) )
#define CRL_APB_CHKR6_CLKA_LOWER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR6_CLKA_LOWER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR6_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR6_CLKB_CNT
*/
#define CRL_APB_CHKR6_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001C8U) )
#define CRL_APB_CHKR6_CLKB_CNT_VALUE_SHIFT 0
#define CRL_APB_CHKR6_CLKB_CNT_VALUE_WIDTH 32
#define CRL_APB_CHKR6_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR6_CTRL
*/
#define CRL_APB_CHKR6_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001CCU) )
#define CRL_APB_CHKR6_CTRL_START_SINGLE_SHIFT 8
#define CRL_APB_CHKR6_CTRL_START_SINGLE_WIDTH 1
#define CRL_APB_CHKR6_CTRL_START_SINGLE_MASK ((u32)0X00000100U)
#define CRL_APB_CHKR6_CTRL_START_CONTINUOUS_SHIFT 7
#define CRL_APB_CHKR6_CTRL_START_CONTINUOUS_WIDTH 1
#define CRL_APB_CHKR6_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U)
#define CRL_APB_CHKR6_CTRL_CLKB_MUX_CTRL_SHIFT 5
#define CRL_APB_CHKR6_CTRL_CLKB_MUX_CTRL_WIDTH 1
#define CRL_APB_CHKR6_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U)
#define CRL_APB_CHKR6_CTRL_CLKA_MUX_CTRL_SHIFT 1
#define CRL_APB_CHKR6_CTRL_CLKA_MUX_CTRL_WIDTH 3
#define CRL_APB_CHKR6_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU)
#define CRL_APB_CHKR6_CTRL_ENABLE_SHIFT 0
#define CRL_APB_CHKR6_CTRL_ENABLE_WIDTH 1
#define CRL_APB_CHKR6_CTRL_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_CHKR7_CLKA_UPPER
*/
#define CRL_APB_CHKR7_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001D0U) )
#define CRL_APB_CHKR7_CLKA_UPPER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR7_CLKA_UPPER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR7_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR7_CLKA_LOWER
*/
#define CRL_APB_CHKR7_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001D4U) )
#define CRL_APB_CHKR7_CLKA_LOWER_THRSHLD_SHIFT 0
#define CRL_APB_CHKR7_CLKA_LOWER_THRSHLD_WIDTH 32
#define CRL_APB_CHKR7_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR7_CLKB_CNT
*/
#define CRL_APB_CHKR7_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001D8U) )
#define CRL_APB_CHKR7_CLKB_CNT_VALUE_SHIFT 0
#define CRL_APB_CHKR7_CLKB_CNT_VALUE_WIDTH 32
#define CRL_APB_CHKR7_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_CHKR7_CTRL
*/
#define CRL_APB_CHKR7_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001DCU) )
#define CRL_APB_CHKR7_CTRL_START_SINGLE_SHIFT 8
#define CRL_APB_CHKR7_CTRL_START_SINGLE_WIDTH 1
#define CRL_APB_CHKR7_CTRL_START_SINGLE_MASK ((u32)0X00000100U)
#define CRL_APB_CHKR7_CTRL_START_CONTINUOUS_SHIFT 7
#define CRL_APB_CHKR7_CTRL_START_CONTINUOUS_WIDTH 1
#define CRL_APB_CHKR7_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U)
#define CRL_APB_CHKR7_CTRL_CLKB_MUX_CTRL_SHIFT 5
#define CRL_APB_CHKR7_CTRL_CLKB_MUX_CTRL_WIDTH 1
#define CRL_APB_CHKR7_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U)
#define CRL_APB_CHKR7_CTRL_CLKA_MUX_CTRL_SHIFT 1
#define CRL_APB_CHKR7_CTRL_CLKA_MUX_CTRL_WIDTH 3
#define CRL_APB_CHKR7_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU)
#define CRL_APB_CHKR7_CTRL_ENABLE_SHIFT 0
#define CRL_APB_CHKR7_CTRL_ENABLE_WIDTH 1
#define CRL_APB_CHKR7_CTRL_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_PICDEBUG_TEMP_CTRL
*/
#define CRL_APB_PICDEBUG_TEMP_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001E0U) )
#define CRL_APB_PICDEBUG_TEMP_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_PICDEBUG_TEMP_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_PICDEBUG_TEMP_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_PICDEBUG_REF_CTRL
*/
#define CRL_APB_PICDEBUG_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001E4U) )
#define CRL_APB_PICDEBUG_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_PICDEBUG_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_PICDEBUG_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR1_SHIFT 16
#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR1_WIDTH 6
#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_PICDEBUG_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_PICDEBUG_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_PICDEBUG_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_PICDEBUG_CTRL
*/
#define CRL_APB_PICDEBUG_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001E8U) )
#define CRL_APB_PICDEBUG_CTRL_START_SHIFT 4
#define CRL_APB_PICDEBUG_CTRL_START_WIDTH 1
#define CRL_APB_PICDEBUG_CTRL_START_MASK ((u32)0X00000010U)
#define CRL_APB_PICDEBUG_CTRL_TRIGGER_SEL_SHIFT 2
#define CRL_APB_PICDEBUG_CTRL_TRIGGER_SEL_WIDTH 2
#define CRL_APB_PICDEBUG_CTRL_TRIGGER_SEL_MASK ((u32)0X0000000CU)
#define CRL_APB_PICDEBUG_CTRL_CNT_LOAD_SHIFT 1
#define CRL_APB_PICDEBUG_CTRL_CNT_LOAD_WIDTH 1
#define CRL_APB_PICDEBUG_CTRL_CNT_LOAD_MASK ((u32)0X00000002U)
#define CRL_APB_PICDEBUG_CTRL_TRIGGER_EN_SHIFT 0
#define CRL_APB_PICDEBUG_CTRL_TRIGGER_EN_WIDTH 1
#define CRL_APB_PICDEBUG_CTRL_TRIGGER_EN_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_PICDEBUG_LCNT
*/
#define CRL_APB_PICDEBUG_LCNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001ECU) )
#define CRL_APB_PICDEBUG_LCNT_VALUE_SHIFT 0
#define CRL_APB_PICDEBUG_LCNT_VALUE_WIDTH 32
#define CRL_APB_PICDEBUG_LCNT_VALUE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRL_APB_PICDEBUG_UCNT
*/
#define CRL_APB_PICDEBUG_UCNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001F0U) )
#define CRL_APB_PICDEBUG_UCNT_VALUE_SHIFT 0
#define CRL_APB_PICDEBUG_UCNT_VALUE_WIDTH 16
#define CRL_APB_PICDEBUG_UCNT_VALUE_MASK ((u32)0X0000FFFFU)
/**
* Register: CRL_APB_USB3_DUAL_SCAN_CTRL
*/
#define CRL_APB_USB3_DUAL_SCAN_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001F4U) )
#define CRL_APB_USB3_DUAL_SCAN_CTRL_CLKACT_SHIFT 24
#define CRL_APB_USB3_DUAL_SCAN_CTRL_CLKACT_WIDTH 1
#define CRL_APB_USB3_DUAL_SCAN_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_USB3_DUAL_SCAN_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_USB3_DUAL_SCAN_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_USB3_DUAL_SCAN_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_USB3_DUAL_SCAN_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_USB3_DUAL_SCAN_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_USB3_DUAL_SCAN_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_DFT_OSC_REF_CTRL
*/
#define CRL_APB_DFT_OSC_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001F8U) )
#define CRL_APB_DFT_OSC_REF_CTRL_CLKACT_SHIFT 24
#define CRL_APB_DFT_OSC_REF_CTRL_CLKACT_WIDTH 1
#define CRL_APB_DFT_OSC_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRL_APB_DFT_OSC_REF_CTRL_DIVISOR0_SHIFT 8
#define CRL_APB_DFT_OSC_REF_CTRL_DIVISOR0_WIDTH 6
#define CRL_APB_DFT_OSC_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRL_APB_DFT_OSC_REF_CTRL_SRCSEL_SHIFT 0
#define CRL_APB_DFT_OSC_REF_CTRL_SRCSEL_WIDTH 3
#define CRL_APB_DFT_OSC_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRL_APB_BOOT_MODE_USER
*/
#define CRL_APB_BOOT_MODE_USER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000200U) )
#define CRL_APB_BOOT_MODE_USER_ALT_BOOT_MODE_SHIFT 12
#define CRL_APB_BOOT_MODE_USER_ALT_BOOT_MODE_WIDTH 4
#define CRL_APB_BOOT_MODE_USER_ALT_BOOT_MODE_MASK ((u32)0X0000F000U)
#define CRL_APB_BOOT_MODE_USER_USE_ALT_SHIFT 8
#define CRL_APB_BOOT_MODE_USER_USE_ALT_WIDTH 1
#define CRL_APB_BOOT_MODE_USER_USE_ALT_MASK ((u32)0X00000100U)
#define CRL_APB_BOOT_MODE_USER_BOOT_MODE_SHIFT 0
#define CRL_APB_BOOT_MODE_USER_BOOT_MODE_WIDTH 4
#define CRL_APB_BOOT_MODE_USER_BOOT_MODE_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_BOOT_MODE_POR
*/
#define CRL_APB_BOOT_MODE_POR ( ( CRL_APB_BASEADDR ) + ((u32)0X00000204U) )
#define CRL_APB_BOOT_MODE_POR_BOOT_MODE2_SHIFT 8
#define CRL_APB_BOOT_MODE_POR_BOOT_MODE2_WIDTH 4
#define CRL_APB_BOOT_MODE_POR_BOOT_MODE2_MASK ((u32)0X00000F00U)
#define CRL_APB_BOOT_MODE_POR_BOOT_MODE1_SHIFT 4
#define CRL_APB_BOOT_MODE_POR_BOOT_MODE1_WIDTH 4
#define CRL_APB_BOOT_MODE_POR_BOOT_MODE1_MASK ((u32)0X000000F0U)
#define CRL_APB_BOOT_MODE_POR_BOOT_MODE0_SHIFT 0
#define CRL_APB_BOOT_MODE_POR_BOOT_MODE0_WIDTH 4
#define CRL_APB_BOOT_MODE_POR_BOOT_MODE0_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_MIMIC_RST
*/
#define CRL_APB_MIMIC_RST ( ( CRL_APB_BASEADDR ) + ((u32)0X00000214U) )
#define CRL_APB_MIMIC_RST_PSONLY_SHIFT 5
#define CRL_APB_MIMIC_RST_PSONLY_WIDTH 1
#define CRL_APB_MIMIC_RST_PSONLY_MASK ((u32)0X00000020U)
#define CRL_APB_MIMIC_RST_DEBUG_ONLY_SHIFT 4
#define CRL_APB_MIMIC_RST_DEBUG_ONLY_WIDTH 1
#define CRL_APB_MIMIC_RST_DEBUG_ONLY_MASK ((u32)0X00000010U)
#define CRL_APB_MIMIC_RST_DEBUG_SYS_SHIFT 3
#define CRL_APB_MIMIC_RST_DEBUG_SYS_WIDTH 1
#define CRL_APB_MIMIC_RST_DEBUG_SYS_MASK ((u32)0X00000008U)
#define CRL_APB_MIMIC_RST_SOFT_SHIFT 2
#define CRL_APB_MIMIC_RST_SOFT_WIDTH 1
#define CRL_APB_MIMIC_RST_SOFT_MASK ((u32)0X00000004U)
#define CRL_APB_MIMIC_RST_SRST_SHIFT 1
#define CRL_APB_MIMIC_RST_SRST_WIDTH 1
#define CRL_APB_MIMIC_RST_SRST_MASK ((u32)0X00000002U)
#define CRL_APB_MIMIC_RST_PMU_SYS_SHIFT 0
#define CRL_APB_MIMIC_RST_PMU_SYS_WIDTH 1
#define CRL_APB_MIMIC_RST_PMU_SYS_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_RESET_CTRL
*/
#define CRL_APB_RESET_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000218U) )
#define CRL_APB_RESET_CTRL_SOFT_RESET_SHIFT 4
#define CRL_APB_RESET_CTRL_SOFT_RESET_WIDTH 1
#define CRL_APB_RESET_CTRL_SOFT_RESET_MASK ((u32)0X00000010U)
#define CRL_APB_RESET_CTRL_SRST_DIS_SHIFT 0
#define CRL_APB_RESET_CTRL_SRST_DIS_WIDTH 1
#define CRL_APB_RESET_CTRL_SRST_DIS_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_BLOCKONLY_RST
*/
#define CRL_APB_BLOCKONLY_RST ( ( CRL_APB_BASEADDR ) + ((u32)0X0000021CU) )
#define CRL_APB_BLOCKONLY_RST_MIMIC_SHIFT 3
#define CRL_APB_BLOCKONLY_RST_MIMIC_WIDTH 1
#define CRL_APB_BLOCKONLY_RST_MIMIC_MASK ((u32)0X00000008U)
#define CRL_APB_BLOCKONLY_RST_DEBUG_ONLY_SHIFT 0
#define CRL_APB_BLOCKONLY_RST_DEBUG_ONLY_WIDTH 1
#define CRL_APB_BLOCKONLY_RST_DEBUG_ONLY_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_RESET_REASON
*/
#define CRL_APB_RESET_REASON ( ( CRL_APB_BASEADDR ) + ((u32)0X00000220U) )
#define CRL_APB_RESET_REASON_MIMIC_SHIFT 15
#define CRL_APB_RESET_REASON_MIMIC_WIDTH 1
#define CRL_APB_RESET_REASON_MIMIC_MASK ((u32)0X00008000U)
#define CRL_APB_RESET_REASON_DEBUG_SYS_SHIFT 6
#define CRL_APB_RESET_REASON_DEBUG_SYS_WIDTH 1
#define CRL_APB_RESET_REASON_DEBUG_SYS_MASK ((u32)0X00000040U)
#define CRL_APB_RESET_REASON_SOFT_SHIFT 5
#define CRL_APB_RESET_REASON_SOFT_WIDTH 1
#define CRL_APB_RESET_REASON_SOFT_MASK ((u32)0X00000020U)
#define CRL_APB_RESET_REASON_SRST_SHIFT 4
#define CRL_APB_RESET_REASON_SRST_WIDTH 1
#define CRL_APB_RESET_REASON_SRST_MASK ((u32)0X00000010U)
#define CRL_APB_RESET_REASON_PSONLY_RESET_REQ_SHIFT 3
#define CRL_APB_RESET_REASON_PSONLY_RESET_REQ_WIDTH 1
#define CRL_APB_RESET_REASON_PSONLY_RESET_REQ_MASK ((u32)0X00000008U)
#define CRL_APB_RESET_REASON_PMU_SYS_RESET_SHIFT 2
#define CRL_APB_RESET_REASON_PMU_SYS_RESET_WIDTH 1
#define CRL_APB_RESET_REASON_PMU_SYS_RESET_MASK ((u32)0X00000004U)
#define CRL_APB_RESET_REASON_INTERNAL_POR_SHIFT 1
#define CRL_APB_RESET_REASON_INTERNAL_POR_WIDTH 1
#define CRL_APB_RESET_REASON_INTERNAL_POR_MASK ((u32)0X00000002U)
#define CRL_APB_RESET_REASON_EXTERNAL_POR_SHIFT 0
#define CRL_APB_RESET_REASON_EXTERNAL_POR_WIDTH 1
#define CRL_APB_RESET_REASON_EXTERNAL_POR_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_RST_LPD_IOU0
*/
#define CRL_APB_RST_LPD_IOU0 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000230U) )
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK ((u32)0X00000008U)
#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 2
#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK ((u32)0X00000004U)
#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT 1
#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK ((u32)0X00000002U)
#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT 0
#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_RST_LPD_IOU1
*/
#define CRL_APB_RST_LPD_IOU1 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000234U) )
/**
* Register: CRL_APB_RST_LPD_IOU2
*/
#define CRL_APB_RST_LPD_IOU2 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000238U) )
#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20
#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK ((u32)0X00100000U)
#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 19
#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK ((u32)0X00080000U)
#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 18
#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK ((u32)0X00040000U)
#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 17
#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK ((u32)0X00020000U)
#define CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT 16
#define CRL_APB_RST_LPD_IOU2_NAND_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK ((u32)0X00010000U)
#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15
#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK ((u32)0X00008000U)
#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14
#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK ((u32)0X00004000U)
#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13
#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK ((u32)0X00002000U)
#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12
#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK ((u32)0X00001000U)
#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11
#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK ((u32)0X00000800U)
#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10
#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK ((u32)0X00000400U)
#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9
#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK ((u32)0X00000200U)
#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8
#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK ((u32)0X00000100U)
#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT 7
#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK ((u32)0X00000080U)
#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6
#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK ((u32)0X00000040U)
#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT 5
#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK ((u32)0X00000020U)
#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT 4
#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK ((u32)0X00000010U)
#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT 3
#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK ((u32)0X00000008U)
#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2
#define CRL_APB_RST_LPD_IOU2_UART1_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK ((u32)0X00000004U)
#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1
#define CRL_APB_RST_LPD_IOU2_UART0_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK ((u32)0X00000002U)
#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0
#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_WIDTH 1
#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_RST_LPD_TOP
*/
#define CRL_APB_RST_LPD_TOP ( ( CRL_APB_BASEADDR ) + ((u32)0X0000023CU) )
#define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 23
#define CRL_APB_RST_LPD_TOP_FPD_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK ((u32)0X00800000U)
#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 20
#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK ((u32)0X00100000U)
#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 19
#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK ((u32)0X00080000U)
#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 17
#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK ((u32)0X00020000U)
#define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 16
#define CRL_APB_RST_LPD_TOP_RTC_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK ((u32)0X00010000U)
#define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 15
#define CRL_APB_RST_LPD_TOP_APM_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_APM_RESET_MASK ((u32)0X00008000U)
#define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 14
#define CRL_APB_RST_LPD_TOP_IPI_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK ((u32)0X00004000U)
#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_SHIFT 11
#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK ((u32)0X00000800U)
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK ((u32)0X00000400U)
#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_SHIFT 9
#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK ((u32)0X00000200U)
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK ((u32)0X00000100U)
#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_SHIFT 7
#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK ((u32)0X00000080U)
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK ((u32)0X00000040U)
#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 4
#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK ((u32)0X00000010U)
#define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 3
#define CRL_APB_RST_LPD_TOP_OCM_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK ((u32)0X00000008U)
#define CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_SHIFT 2
#define CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK ((u32)0X00000004U)
#define CRL_APB_RST_LPD_TOP_RPU_R51_RESET_SHIFT 1
#define CRL_APB_RST_LPD_TOP_RPU_R51_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK ((u32)0X00000002U)
#define CRL_APB_RST_LPD_TOP_RPU_R50_RESET_SHIFT 0
#define CRL_APB_RST_LPD_TOP_RPU_R50_RESET_WIDTH 1
#define CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_RST_LPD_DBG
*/
#define CRL_APB_RST_LPD_DBG ( ( CRL_APB_BASEADDR ) + ((u32)0X00000240U) )
#define CRL_APB_RST_LPD_DBG_DBG_ACK_SHIFT 15
#define CRL_APB_RST_LPD_DBG_DBG_ACK_WIDTH 1
#define CRL_APB_RST_LPD_DBG_DBG_ACK_MASK ((u32)0X00008000U)
#define CRL_APB_RST_LPD_DBG_RPU_DBG1_RESET_SHIFT 5
#define CRL_APB_RST_LPD_DBG_RPU_DBG1_RESET_WIDTH 1
#define CRL_APB_RST_LPD_DBG_RPU_DBG1_RESET_MASK ((u32)0X00000020U)
#define CRL_APB_RST_LPD_DBG_RPU_DBG0_RESET_SHIFT 4
#define CRL_APB_RST_LPD_DBG_RPU_DBG0_RESET_WIDTH 1
#define CRL_APB_RST_LPD_DBG_RPU_DBG0_RESET_MASK ((u32)0X00000010U)
#define CRL_APB_RST_LPD_DBG_DBG_LPD_RESET_SHIFT 1
#define CRL_APB_RST_LPD_DBG_DBG_LPD_RESET_WIDTH 1
#define CRL_APB_RST_LPD_DBG_DBG_LPD_RESET_MASK ((u32)0X00000002U)
#define CRL_APB_RST_LPD_DBG_DBG_FPD_RESET_SHIFT 0
#define CRL_APB_RST_LPD_DBG_DBG_FPD_RESET_WIDTH 1
#define CRL_APB_RST_LPD_DBG_DBG_FPD_RESET_MASK ((u32)0X00000001U)
/**
* Register: CRL_APB_BOOT_PIN_CTRL
*/
#define CRL_APB_BOOT_PIN_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000250U) )
#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8
#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_WIDTH 4
#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK ((u32)0X00000F00U)
#define CRL_APB_BOOT_PIN_CTRL_IN_VAL_SHIFT 4
#define CRL_APB_BOOT_PIN_CTRL_IN_VAL_WIDTH 4
#define CRL_APB_BOOT_PIN_CTRL_IN_VAL_MASK ((u32)0X000000F0U)
#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_WIDTH 4
#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_DED_IOB_CTRL0
*/
#define CRL_APB_DED_IOB_CTRL0 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000254U) )
#define CRL_APB_DED_IOB_CTRL0_DRIVE0_SHIFT 0
#define CRL_APB_DED_IOB_CTRL0_DRIVE0_WIDTH 4
#define CRL_APB_DED_IOB_CTRL0_DRIVE0_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_DED_IOB_CTRL1
*/
#define CRL_APB_DED_IOB_CTRL1 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000258U) )
#define CRL_APB_DED_IOB_CTRL1_DRIVE1_SHIFT 0
#define CRL_APB_DED_IOB_CTRL1_DRIVE1_WIDTH 4
#define CRL_APB_DED_IOB_CTRL1_DRIVE1_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_DED_IOB_CTRL2
*/
#define CRL_APB_DED_IOB_CTRL2 ( ( CRL_APB_BASEADDR ) + ((u32)0X0000025CU) )
#define CRL_APB_DED_IOB_CTRL2_SCHMITT_CMOS_N_SHIFT 0
#define CRL_APB_DED_IOB_CTRL2_SCHMITT_CMOS_N_WIDTH 4
#define CRL_APB_DED_IOB_CTRL2_SCHMITT_CMOS_N_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_DED_IOB_CTRL3
*/
#define CRL_APB_DED_IOB_CTRL3 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000260U) )
#define CRL_APB_DED_IOB_CTRL3_PULL_HIGH_LOW_N_SHIFT 0
#define CRL_APB_DED_IOB_CTRL3_PULL_HIGH_LOW_N_WIDTH 4
#define CRL_APB_DED_IOB_CTRL3_PULL_HIGH_LOW_N_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_DED_IOB_CTRL4
*/
#define CRL_APB_DED_IOB_CTRL4 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000264U) )
#define CRL_APB_DED_IOB_CTRL4_PULL_ENABLE_SHIFT 0
#define CRL_APB_DED_IOB_CTRL4_PULL_ENABLE_WIDTH 4
#define CRL_APB_DED_IOB_CTRL4_PULL_ENABLE_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_DED_IOB_CTRL5
*/
#define CRL_APB_DED_IOB_CTRL5 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000268U) )
#define CRL_APB_DED_IOB_CTRL5_SLOW_FAST_SLEW_N_SHIFT 0
#define CRL_APB_DED_IOB_CTRL5_SLOW_FAST_SLEW_N_WIDTH 4
#define CRL_APB_DED_IOB_CTRL5_SLOW_FAST_SLEW_N_MASK ((u32)0X0000000FU)
/**
* Register: CRL_APB_BANK3_CTRL0
*/
#define CRL_APB_BANK3_CTRL0 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000270U) )
#define CRL_APB_BANK3_CTRL0_DRIVE0_SHIFT 0
#define CRL_APB_BANK3_CTRL0_DRIVE0_WIDTH 10
#define CRL_APB_BANK3_CTRL0_DRIVE0_MASK ((u32)0X000003FFU)
/**
* Register: CRL_APB_BANK3_CTRL1
*/
#define CRL_APB_BANK3_CTRL1 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000274U) )
#define CRL_APB_BANK3_CTRL1_DRIVE1_SHIFT 0
#define CRL_APB_BANK3_CTRL1_DRIVE1_WIDTH 10
#define CRL_APB_BANK3_CTRL1_DRIVE1_MASK ((u32)0X000003FFU)
/**
* Register: CRL_APB_BANK3_CTRL2
*/
#define CRL_APB_BANK3_CTRL2 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000278U) )
#define CRL_APB_BANK3_CTRL2_SCHMITT_CMOS_N_SHIFT 0
#define CRL_APB_BANK3_CTRL2_SCHMITT_CMOS_N_WIDTH 10
#define CRL_APB_BANK3_CTRL2_SCHMITT_CMOS_N_MASK ((u32)0X000003FFU)
/**
* Register: CRL_APB_BANK3_CTRL3
*/
#define CRL_APB_BANK3_CTRL3 ( ( CRL_APB_BASEADDR ) + ((u32)0X0000027CU) )
#define CRL_APB_BANK3_CTRL3_PULL_HIGH_LOW_N_SHIFT 0
#define CRL_APB_BANK3_CTRL3_PULL_HIGH_LOW_N_WIDTH 10
#define CRL_APB_BANK3_CTRL3_PULL_HIGH_LOW_N_MASK ((u32)0X000003FFU)
/**
* Register: CRL_APB_BANK3_CTRL4
*/
#define CRL_APB_BANK3_CTRL4 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000280U) )
#define CRL_APB_BANK3_CTRL4_PULL_ENABLE_SHIFT 0
#define CRL_APB_BANK3_CTRL4_PULL_ENABLE_WIDTH 10
#define CRL_APB_BANK3_CTRL4_PULL_ENABLE_MASK ((u32)0X000003FFU)
/**
* Register: CRL_APB_BANK3_CTRL5
*/
#define CRL_APB_BANK3_CTRL5 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000284U) )
#define CRL_APB_BANK3_CTRL5_SLOW_FAST_SLEW_N_SHIFT 0
#define CRL_APB_BANK3_CTRL5_SLOW_FAST_SLEW_N_WIDTH 10
#define CRL_APB_BANK3_CTRL5_SLOW_FAST_SLEW_N_MASK ((u32)0X000003FFU)
/**
* Register: CRL_APB_BANK3_STATUS
*/
#define CRL_APB_BANK3_STATUS ( ( CRL_APB_BASEADDR ) + ((u32)0X00000288U) )
#define CRL_APB_BANK3_STATUS_VMODE_1P8_3P3_N_SHIFT 0
#define CRL_APB_BANK3_STATUS_VMODE_1P8_3P3_N_WIDTH 1
#define CRL_APB_BANK3_STATUS_VMODE_1P8_3P3_N_MASK ((u32)0X00000001U)
#ifdef __cplusplus
}
#endif
#endif /* _CRL_APB_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/idle_hooks.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/**
* Implementation for the custom idling of of individual peripheral node.
*/
#include <sleep.h>
#include "pm_node_idle.h"
#include "pm_common.h"
#ifdef ENABLE_NODE_IDLING
#define MAX_TIMEOUT 10000 // Max Retry count
#if defined(XPAR_PSU_TTC_0_DEVICE_ID) || \
defined(XPAR_PSU_TTC_3_DEVICE_ID) || \
defined(XPAR_PSU_TTC_6_DEVICE_ID) || \
defined(XPAR_PSU_TTC_9_DEVICE_ID)
/**
* NodeTtcIdle() - Custom code to idle the TTC
*
* @BaseAddress: TTC base address
*/
void NodeTtcIdle(u32 FirstBaseAddress)
{
u32 BaseAddress;
for (BaseAddress = FirstBaseAddress; BaseAddress < FirstBaseAddress +
0xC; BaseAddress += 4) {
u32 Val;
/*Stop the TTC timer */
Val = Xil_In32(BaseAddress + XTTCPS_CNT_CNTRL_OFFSET);
Xil_Out32(BaseAddress + XTTCPS_CNT_CNTRL_OFFSET, (Val |
~XTTCPS_CNT_CNTRL_DIS_MASK));
/*
* Reset the counter control register
*/
XTtcPs_WriteReg(BaseAddress, XTTCPS_CNT_CNTRL_OFFSET,
XTTCPS_CNT_CNTRL_RESET_VALUE);
/*
* Clear counters interval values
*/
XTtcPs_WriteReg(BaseAddress, XTTCPS_INTERVAL_VAL_OFFSET, 0x0);
/*
* Clear counters Match values
*/
XTtcPs_WriteReg(BaseAddress, XTTCPS_MATCH_0_OFFSET, 0x0);
XTtcPs_WriteReg(BaseAddress, XTTCPS_MATCH_1_OFFSET, 0x0);
XTtcPs_WriteReg(BaseAddress, XTTCPS_MATCH_2_OFFSET, 0x0);
/*
* Disable counter's interrupts
*/
XTtcPs_WriteReg(BaseAddress, XTTCPS_IER_OFFSET, 0x0);
/*
* Clear interrupts (status) for all the counters [clronrd]
*/
XTtcPs_ReadReg(BaseAddress, XTTCPS_ISR_OFFSET);
}
}
#endif
#if defined(XPAR_PSU_SD_0_DEVICE_ID) || \
defined(XPAR_PSU_SD_1_DEVICE_ID)
#define IOU_SD_CTRL_OFFSET 0x00000310
#define SD_SLEEP_TIME 1000 /* in ms */
#define EMMC_RESET_TIME 1 /* in ms */
#define SD0_EMMC_SEL_MASK (0x1 << 0)
#define SD1_EMMC_SEL_MASK (0x1 << 15)
/**
* NodeSdioIdle() - Custom code to idle the SDIO
*
* @BaseAddress: SDIO base address
*/
void NodeSdioIdle(u32 BaseAddress)
{
u16 EmmcStatus;
u8 Val;
u32 StatusReg;
u32 PresentStateReg;
u32 Timeout = MAX_TIMEOUT;
u32 SdpsActive = (XSDPS_PSR_INHIBIT_CMD_MASK | XSDPS_PSR_INHIBIT_DAT_MASK
| XSDPS_PSR_DAT_ACTIVE_MASK);
PresentStateReg = XSdPs_ReadReg8(BaseAddress, XSDPS_PRES_STATE_OFFSET);
/* Check for Card Present */
if (PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) {
/* Check for SD idle */
do {
StatusReg = XSdPs_ReadReg8(BaseAddress, XSDPS_PRES_STATE_OFFSET);
} while ((StatusReg & SdpsActive) && --Timeout);
}
if (Timeout == 0) {
PmWarn("sd not idle\r\n");
}
/* Reset the eMMC card */
EmmcStatus = Xil_In32(IOU_SLCR_BASE + IOU_SD_CTRL_OFFSET);
#ifdef XPAR_PSU_SD_0_DEVICE_ID
if ((BaseAddress == XPAR_PSU_SD_0_BASEADDR)
&& (EmmcStatus & SD0_EMMC_SEL_MASK)) {
Val = XSdPs_ReadReg8(BaseAddress, XSDPS_POWER_CTRL_OFFSET);
XSdPs_WriteReg8(BaseAddress, XSDPS_POWER_CTRL_OFFSET,
Val | XSDPS_PC_EMMC_HW_RST_MASK);
usleep(1000 * EMMC_RESET_TIME);
Val = XSdPs_ReadReg8(BaseAddress, XSDPS_POWER_CTRL_OFFSET);
XSdPs_WriteReg8(BaseAddress, XSDPS_POWER_CTRL_OFFSET,
Val & ~XSDPS_PC_EMMC_HW_RST_MASK);
}
#endif
#ifdef XPAR_PSU_SD_1_DEVICE_ID
if ((BaseAddress == XPAR_PSU_SD_1_BASEADDR)
&& (EmmcStatus & SD1_EMMC_SEL_MASK)) {
Val = XSdPs_ReadReg8(BaseAddress, XSDPS_POWER_CTRL_OFFSET);
XSdPs_WriteReg8(BaseAddress, XSDPS_POWER_CTRL_OFFSET,
Val | XSDPS_PC_EMMC_HW_RST_MASK);
usleep(1000 * EMMC_RESET_TIME);
Val = XSdPs_ReadReg8(BaseAddress, XSDPS_POWER_CTRL_OFFSET);
XSdPs_WriteReg8(BaseAddress, XSDPS_POWER_CTRL_OFFSET,
Val & ~XSDPS_PC_EMMC_HW_RST_MASK);
}
#endif
/* Disable bus power */
XSdPs_WriteReg8(BaseAddress, XSDPS_POWER_CTRL_OFFSET, 0);
usleep(1000 * SD_SLEEP_TIME);
/* "Software reset for all" is initiated */
XSdPs_WriteReg8(BaseAddress, XSDPS_SW_RST_OFFSET, XSDPS_SWRST_ALL_MASK);
Timeout = MAX_TIMEOUT;
/* Proceed with initialization only after reset is complete */
Val = XSdPs_ReadReg8(BaseAddress, XSDPS_SW_RST_OFFSET);
while (((Val & XSDPS_SWRST_ALL_MASK) != 0U) && --Timeout) {
Val = XSdPs_ReadReg8(BaseAddress, XSDPS_SW_RST_OFFSET);
}
if (Timeout == 0) {
PmWarn("sd not reset\r\n");
}
}
#endif
#if defined(XPAR_PSU_I2C_0_DEVICE_ID) || \
defined(XPAR_PSU_I2C_1_DEVICE_ID)
/**
* NodeI2cIdle() - Custom code to idle the I2c
*
* @BaseAddress: I2c base address
*/
void NodeI2cIdle(u32 BaseAddress)
{
u32 StatusReg;
u32 Timeout = MAX_TIMEOUT;
/* Check whether the I2C bus is busy */
do {
StatusReg = XIicPs_ReadReg(BaseAddress,
XIICPS_SR_OFFSET);
} while (((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) && --Timeout);
if (Timeout == 0) {
PmWarn("i2c not idle\r\n");
}
}
#endif
#if defined(XPAR_PSU_ETHERNET_0_DEVICE_ID) || \
defined(XPAR_PSU_ETHERNET_1_DEVICE_ID) || \
defined(XPAR_PSU_ETHERNET_2_DEVICE_ID) || \
defined(XPAR_PSU_ETHERNET_3_DEVICE_ID)
#define DMA_STOP_TIMEOUT (500)
#define REG_POLL_STATUS_DELAY (3000) /* in us */
/**
* NodeGemIdle() - Custom code to idle the GEM
*
* @BaseAddress: GEM base address
*/
void NodeGemIdle(u32 BaseAddress)
{
u32 Reg;
u32 Timeout = MAX_TIMEOUT;
/* Make sure MDIO is in IDLE state */
do {
Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWSR_OFFSET);
} while ((!(Reg & XEMACPS_NWSR_MDIOIDLE_MASK)) && --Timeout);
if (Timeout == 0) {
PmWarn("gem not idle\r\n");
}
/* Disable all interrupts */
XEmacPs_WriteReg(BaseAddress, XEMACPS_IDR_OFFSET, XEMACPS_IXR_ALL_MASK);
/* Halt the TX traffic */
Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWCTRL_OFFSET);
Reg |= XEMACPS_NWCTRL_HALTTX_MASK;
XEmacPs_WriteReg(BaseAddress, XEMACPS_NWCTRL_OFFSET, Reg);
/* Do not accept RX frames addressed to broadcast address */
Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWCFG_OFFSET);
Reg |= XEMACPS_NWCFG_BCASTDI_MASK; /* No Broadcast bit */
XEmacPs_WriteReg(BaseAddress, XEMACPS_NWCFG_OFFSET, Reg);
/* Disable specific address filtering and thereby stop accept other RX frames */
XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR1L_OFFSET, 0x0);
XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR2L_OFFSET, 0x0);
XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR3L_OFFSET, 0x0);
XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR4L_OFFSET, 0x0);
/*
* Check for the DMA stop. Poll on the current bd ptr and make sure it
* doesn't move for considerable time.
*/
/* Wait for TX DMA to stop */
Timeout = DMA_STOP_TIMEOUT; /* Worst case timeout */
do {
Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_TXQBASE_OFFSET);
usleep(REG_POLL_STATUS_DELAY);
} while ((Reg != XEmacPs_ReadReg(BaseAddress, XEMACPS_TXQBASE_OFFSET)) && --Timeout);
if (0 == Timeout) {
PmWarn("GEM TX Not Idled\r\n");
}
/* Wait for RX DMA to stop */
Timeout = DMA_STOP_TIMEOUT; /* Worst case timeout */
do {
Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_RXQBASE_OFFSET);
usleep(REG_POLL_STATUS_DELAY);
} while ((Reg != XEmacPs_ReadReg(BaseAddress, XEMACPS_RXQBASE_OFFSET)) && --Timeout);
if (0 == Timeout) {
PmWarn("GEM RX Not Idled\r\n");
}
/* Disable the receiver & transmitter */
Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWCTRL_OFFSET);
Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
XEmacPs_WriteReg(BaseAddress, XEMACPS_NWCTRL_OFFSET, Reg);
}
#endif
#ifdef XPAR_PSU_QSPI_0_DEVICE_ID
/**
* NodeQspiIdle() - Custom code to idle the QSPI
*
* @BaseAddress: QSPI base address
*/
void NodeQspiIdle(u32 BaseAddress)
{
volatile u32 StatusReg;
/*
* If QSPI is enabled, pause Tx and Rx DMA.
*/
StatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_EN_OFFSET);
if (StatusReg & XQSPIPSU_EN_MASK) {
StatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET);
StatusReg |= (XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK |
XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK);
XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET, StatusReg);
}
}
#endif
#if defined(XPAR_XUSBPSU_0_DEVICE_ID) || defined(XPAR_XUSBPSU_1_DEVICE_ID)
#define XUSBPSU_EP_PARAM_INDEX 3
#define XUSBPSU_GSTS_OP_MODE 0x3
/**
* NodeUsbIdle() - Code to idle the Usb
*
* @BaseAddress: USB base address
*/
void NodeUsbIdle(u32 BaseAddress)
{
u32 regVal;
u32 LocalTimeout = MAX_TIMEOUT;
u8 PhyEpNum, EpNums;
u32 Cmd, RscIdx;
regVal = Xil_In32(BaseAddress + XUSBPSU_GSTS);
/* Check if USB is in device mode */
if ((regVal & XUSBPSU_GSTS_OP_MODE) == 0) {
/* Read number of endpoints */
regVal = Xil_In32(BaseAddress + ((u32)XUSBPSU_GHWPARAMS0_OFFSET
+ ((u32)XUSBPSU_EP_PARAM_INDEX * 4)));
EpNums = XUSBPSU_NUM_EPS(regVal);
/* Stop transfers */
for (PhyEpNum = 0; PhyEpNum <= EpNums; PhyEpNum++) {
LocalTimeout = MAX_TIMEOUT;
/* Issue EndTransfer command */
RscIdx = XUSBPSU_DEPCMD_GET_RSC_IDX(Xil_In32(BaseAddress
+ XUSBPSU_DEPCMD(PhyEpNum)));
if (RscIdx == 0) {
continue;
}
Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
Cmd |= XUSBPSU_DEPCMD_CMDIOC;
Cmd |= XUSBPSU_DEPCMD_PARAM(RscIdx);
Xil_Out32(BaseAddress + XUSBPSU_DEPCMDPAR0(PhyEpNum),
0x00);
Xil_Out32(BaseAddress + XUSBPSU_DEPCMDPAR1(PhyEpNum),
0x00);
Xil_Out32(BaseAddress + XUSBPSU_DEPCMDPAR2(PhyEpNum),
0x00);
Xil_Out32(BaseAddress + XUSBPSU_DEPCMD(PhyEpNum),
Cmd | XUSBPSU_DEPCMD_CMDACT);
/* Check end of transfer */
do {
regVal = Xil_In32(BaseAddress +
XUSBPSU_DEPCMD(PhyEpNum));
} while ((regVal & XUSBPSU_DEPCMD_CMDACT) &&
--LocalTimeout);
if (LocalTimeout == 0U)
PmWarn("Endpoint transfer not completed\r\n");
}
/* Disable endpoints */
for (PhyEpNum = 0; PhyEpNum <= EpNums; PhyEpNum++) {
regVal = Xil_In32(BaseAddress + XUSBPSU_DALEPENA);
regVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum);
Xil_Out32(BaseAddress + XUSBPSU_DALEPENA, regVal);
}
/* Stop USB device controller */
regVal = Xil_In32(BaseAddress + XUSBPSU_DCTL);
regVal &= ~XUSBPSU_DCTL_RUN_STOP;
Xil_Out32(BaseAddress + XUSBPSU_DCTL, regVal);
/* Check for USB */
LocalTimeout = MAX_TIMEOUT;
do {
regVal = Xil_In32(BaseAddress + XUSBPSU_DSTS);
} while (!(regVal & XUSBPSU_DSTS_DEVCTRLHLT) && --LocalTimeout);
if (LocalTimeout == 0U)
PmWarn("USB device controller not stopped\r\n");
}
/* Clear event buffer */
Xil_Out32(BaseAddress + XUSBPSU_GEVNTADRLO(0U), 0U);
Xil_Out32(BaseAddress + XUSBPSU_GEVNTADRHI(0U), 0U);
Xil_Out32(BaseAddress + XUSBPSU_GEVNTSIZ(0U),
(u32)XUSBPSU_GEVNTSIZ_INTMASK | XUSBPSU_GEVNTSIZ_SIZE(0U));
Xil_Out32(BaseAddress + XUSBPSU_GEVNTCOUNT(0U), 0U);
}
#endif
#ifdef XPAR_XDPPSU_0_DEVICE_ID
#ifdef XPAR_XDPDMA_0_DEVICE_ID
#define XDPDMA_CH_OFFSET 0X100
#define XDPDMA_NUM_CHANNEL 6U /* Number of channels */
#define XDPDMA_CH_CNTL_ENABLE BIT(0)
#define XDPDMA_CH_CNTL_PAUSE BIT(1)
#define XDPDMA_EINTR_ALL 0xffffffff
/**
* XDpDmaStopChannels - Stop DPDMA channels
*
* Stop the channel with the following sequence: 1. Pause, 2. Wait until the
* number of outstanding transactions to go to 0, 3. Disable the channel.
*/
static void XDpDmaStopChannels(void)
{
u8 channel = 0;
u32 regVal = 0, LocalTimeout;
for (channel = 0; channel < XDPDMA_NUM_CHANNEL; channel++) {
/* Pause the channel */
XDpDma_ReadModifyWrite(XPAR_XDPDMA_0_BASEADDR, XDPDMA_CH0_CNTL
+ XDPDMA_CH_OFFSET * channel,
XDPDMA_CH_CNTL_PAUSE,
XDPDMA_CH_CNTL_PAUSE_MASK);
LocalTimeout = MAX_TIMEOUT;
/* Wait until the outstanding transactions number to go to 0 */
do {
regVal = XDpDma_ReadReg(XPAR_XDPDMA_0_BASEADDR,
XDPDMA_CH0_STATUS +
XDPDMA_CH_OFFSET * channel);
} while ((regVal & XDPDMA_CH_STATUS_OTRAN_CNT_MASK) &&
--LocalTimeout);
if (!LocalTimeout) {
PmWarn("DP DMA not ready to stop\r\n");
continue;
}
/* Disable channels */
XDpDma_ReadModifyWrite(XPAR_XDPDMA_0_BASEADDR, XDPDMA_CH0_CNTL
+ XDPDMA_CH_OFFSET * channel,
~XDPDMA_CH_CNTL_ENABLE,
XDPDMA_CH_CNTL_EN_MASK);
}
/* Disable all DPDMA interrupts */
XDpDma_WriteReg(XPAR_XDPDMA_0_BASEADDR, XDPDMA_IDS, ~0);
}
#endif
/**
* NodeDpIdle() - Custom code to idle the DP
*
* @BaseAddress: DP base address
*/
void NodeDpIdle(u32 BaseAddress)
{
#ifdef XPAR_XDPDMA_0_DEVICE_ID
/* Stop all dpdma channels */
XDpDmaStopChannels();
#endif
/* Disable main stream attributes */
Xil_Out32(BaseAddress + XDPPSU_ENABLE, 0x0);
}
#endif
#ifdef XPAR_PSU_SATA_S_AXI_BASEADDR
#define SATA_HOST_CTL 0x04
#define SATA_HOST_IRQ_EN (1 << 1)
#define SATA_HOST_AHCI_EN (1U << 31U)
#define SATA_AHCI_PORT0_CTRL_OFFSET 0x100
#define SATA_AHCI_PORT1_CTRL_OFFSET 0x180
#define SATA_AHCI_PORT_PXCMD 0x18
#define SATA_AHCI_PORT_PXCMD_ST 1
#define SATA_AHCI_PORT_PXCMD_CR (1 << 15)
/**
* NodeSataIdle() - Custom code to idle the SATA
*
* @BaseAddress: SATA base address
*/
void NodeSataIdle(u32 BaseAddress)
{
u32 regVal, timeOut = MAX_TIMEOUT;
/* Disable Interrupt */
regVal = Xil_In32(BaseAddress + SATA_HOST_CTL);
regVal &= ~SATA_HOST_IRQ_EN;
Xil_Out32(BaseAddress + SATA_HOST_CTL, regVal);
/* Stop HBA engine for PORT0 and PORT1 */
regVal = Xil_In32(BaseAddress + SATA_AHCI_PORT0_CTRL_OFFSET +
SATA_AHCI_PORT_PXCMD);
regVal &= ~SATA_AHCI_PORT_PXCMD_ST;
Xil_Out32(BaseAddress + SATA_AHCI_PORT0_CTRL_OFFSET +
SATA_AHCI_PORT_PXCMD, regVal);
regVal = Xil_In32(BaseAddress + SATA_AHCI_PORT1_CTRL_OFFSET +
SATA_AHCI_PORT_PXCMD);
regVal &= ~SATA_AHCI_PORT_PXCMD_ST;
Xil_Out32(BaseAddress + SATA_AHCI_PORT1_CTRL_OFFSET +
SATA_AHCI_PORT_PXCMD, regVal);
/* Wait for command list DMA engine to stop running */
do {
regVal = Xil_In32(BaseAddress + SATA_AHCI_PORT0_CTRL_OFFSET +
SATA_AHCI_PORT_PXCMD);
} while ((regVal & SATA_AHCI_PORT_PXCMD_CR) && --timeOut);
if (!timeOut) {
PmWarn("Command list DMA engine not stopped for PORT0\r\n");
}
timeOut = MAX_TIMEOUT;
do {
regVal = Xil_In32(BaseAddress + SATA_AHCI_PORT1_CTRL_OFFSET +
SATA_AHCI_PORT_PXCMD);
} while ((regVal & SATA_AHCI_PORT_PXCMD_CR) && --timeOut);
if (!timeOut) {
PmWarn("Command list DMA engine not stopped for PORT1\r\n");
}
/* Disable AHCI */
regVal = Xil_In32(BaseAddress + SATA_HOST_CTL);
regVal &= ~SATA_HOST_AHCI_EN;
Xil_Out32(BaseAddress + SATA_HOST_CTL, regVal);
Xil_In32(BaseAddress + SATA_HOST_CTL); /* flush */
}
#endif
#if defined(XPAR_PSU_GDMA_0_DEVICE_ID) || \
defined(XPAR_PSU_ADMA_0_DEVICE_ID)
/**
* NodeZdmaIdle() - Custom code to idle the ZDMA (GDMA and ADMA)
*
* @BaseAddress: ZDMA base address of the first channel
*/
void NodeZdmaIdle(u32 BaseAddress)
{
u8 channel = 0;
volatile u32 regVal = 0;
u32 LocalTimeout;
for (channel = 0; channel < XZDMA_NUM_CHANNEL; channel++) {
/*
* Idle each of the 8 channels
*/
/* Disable / stop the channel the channel */
XZDma_WriteReg(BaseAddress, (XZDMA_CH_CTRL2_OFFSET),
(XZDMA_CH_CTRL2_DIS_MASK));
/*
* wait till transfers are not completed or halted
*/
LocalTimeout = MAX_TIMEOUT; /* todo: not right to use max timeout. do calibrate*/
do {
regVal = XZDma_ReadReg(BaseAddress, XZDMA_CH_STS_OFFSET) & XZDMA_STS_BUSY_MASK;
}while (regVal && LocalTimeout --);
/* Disables and clear all interrupts */
XZDma_WriteReg(BaseAddress, XZDMA_CH_IDS_OFFSET, XZDMA_IXR_ALL_INTR_MASK);
XZDma_WriteReg( BaseAddress, XZDMA_CH_ISR_OFFSET,
(XZDma_ReadReg(BaseAddress, XZDMA_CH_ISR_OFFSET) & XZDMA_IXR_ALL_INTR_MASK));
/* Reset all the configurations */
XZDma_WriteReg(BaseAddress, XZDMA_CH_CTRL0_OFFSET, XZDMA_CTRL0_RESET_VALUE);
XZDma_WriteReg(BaseAddress, XZDMA_CH_CTRL1_OFFSET, XZDMA_CTRL1_RESET_VALUE);
XZDma_WriteReg(BaseAddress, XZDMA_CH_DATA_ATTR_OFFSET, XZDMA_DATA_ATTR_RESET_VALUE);
XZDma_WriteReg(BaseAddress, XZDMA_CH_DSCR_ATTR_OFFSET, XZDMA_DSCR_ATTR_RESET_VALUE);
/* Clears total byte transferred */
XZDma_WriteReg(BaseAddress, XZDMA_CH_TOTAL_BYTE_OFFSET,
XZDma_ReadReg(BaseAddress, XZDMA_CH_TOTAL_BYTE_OFFSET));
/* Read interrupt counts to clear it on both source and destination channels*/
XZDma_ReadReg(BaseAddress, XZDMA_CH_IRQ_SRC_ACCT_OFFSET);
XZDma_ReadReg(BaseAddress, XZDMA_CH_IRQ_DST_ACCT_OFFSET);
/*
* Reset the channel's coherent attributes.
*/
XZDma_WriteReg(BaseAddress, XZDMA_CH_DSCR_ATTR_OFFSET, 0x0);
XZDma_WriteReg(BaseAddress, XZDMA_CH_SRC_DSCR_WORD3_OFFSET, 0x0);
XZDma_WriteReg(BaseAddress, XZDMA_CH_DST_DSCR_WORD3_OFFSET, 0x0);
BaseAddress += XZDMA_CH_OFFSET;
}
}
#endif /* ZDMA */
#if defined(XPAR_PSU_CAN_0_DEVICE_ID) || \
defined(XPAR_PSU_CAN_1_DEVICE_ID)
void NodeCanIdle(u32 BaseAddress)
{
volatile u32 StatusReg;
u32 LocalTimeout = MAX_TIMEOUT;
/*Disable CAN */
XCanPs_WriteReg(BaseAddress, XCANPS_SRR_OFFSET, 0U);
do {
StatusReg = XCanPs_ReadReg(BaseAddress, XCANPS_SR_OFFSET);
} while (!(StatusReg & XCANPS_SR_CONFIG_MASK) && LocalTimeout--);
}
#endif /* CAN */
#if defined(XPAR_PSU_NAND_0_DEVICE_ID)
void NodeNandIdle(u32 BaseAddress)
{
volatile u32 StatusReg;
u32 LocalTimeout = MAX_TIMEOUT;
/* Wait for transfer to complete if any */
do {
StatusReg = XNandPsu_ReadReg(BaseAddress,
XNANDPSU_INTR_STS_OFFSET);
} while ((StatusReg & XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK) && LocalTimeout--);
/* Disable the Interrupts */
XNandPsu_WriteReg(BaseAddress,
XNANDPSU_INTR_STS_EN_OFFSET, 0U);
}
#endif /* NAND */
#ifdef XPAR_PSU_GPU_S_AXI_BASEADDR
#define XGPU_PP_CTRL_MGMT_REG_OFFSET 0x100C
#define XGPU_PP_SOFT_RESET_MASK (1U << 7)
#define XGPU_PP_INT_RAWSTAT_REG_OFFSET 0x1020
#define XGPU_PP_RESET_COMPLETED_MASK (1U << 12)
void NodeGpuPPIdle(u32 BaseAddress)
{
volatile u32 StatusReg;
u32 LocalTimeout = MAX_TIMEOUT;
XPfw_RMW32(BaseAddress + XGPU_PP_CTRL_MGMT_REG_OFFSET,
XGPU_PP_SOFT_RESET_MASK,
XGPU_PP_SOFT_RESET_MASK);
do {
StatusReg = Xil_In32(BaseAddress +
XGPU_PP_INT_RAWSTAT_REG_OFFSET);
} while (!(StatusReg & XGPU_PP_RESET_COMPLETED_MASK) &&
LocalTimeout--);
}
void NodeGpuIdle(u32 BaseAddress)
{
NodeGpuPPIdle(BaseAddress + GPU_PP_0_OFFSET);
NodeGpuPPIdle(BaseAddress + GPU_PP_1_OFFSET);
}
#endif /* GPU */
#endif /* ENABLE_NODE_IDLING */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/clockps_v1_2/src/xclockps_fixedfactor.c
/******************************************************************************
* Copyright (C) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xclockps_fixedfactor.c
* @addtogroup xclockps_v1_2
* @{
*
* This file handles fixed factor related definition and operations.
*
* <pre>
* MODIFICATION HISTORY:
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------
* 1.00 cjp 02/09/18 First release
* 1.2 sd 02/13/20 Rename ARRAY_SIZE
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xclockps.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/* Assign structure elements for fixed factors */
#define XCLOCK_ASSIGN_FIXEDFACTORS(ParentTypeVal, FixFactIndexVal) \
{ \
.Multiplier = 1, \
.Divisor = 2, \
.IsInit = FALSE, \
.EnableCount = 0, \
.Parent = XCLOCK_GENERATE_PARENT_ID(ParentTypeVal, FixFactIndexVal), \
.Rate = XCLOCK_INVALID_RATE, \
}
/**************************** Type Definitions *******************************/
/* This typedef holds information for fixed factors */
typedef struct {
u8 Multiplier;
u8 Divisor;
u8 IsInit;
u8 EnableCount;
u16 Parent;
XClockRate Rate;
} XClock_TypeFixedFactor;
/************************** Variable Definitions *****************************/
/* Fixed factor database */
static XClock_TypeFixedFactor FixedFactors[] = {
XCLOCK_ASSIGN_FIXEDFACTORS(XCLOCK_TYPE_PLL, IOPLL_INT_PLL),
XCLOCK_ASSIGN_FIXEDFACTORS(XCLOCK_TYPE_PLL, RPLL_INT_PLL),
XCLOCK_ASSIGN_FIXEDFACTORS(XCLOCK_TYPE_PLL, APLL_INT_PLL),
XCLOCK_ASSIGN_FIXEDFACTORS(XCLOCK_TYPE_PLL, DPLL_INT_PLL),
XCLOCK_ASSIGN_FIXEDFACTORS(XCLOCK_TYPE_PLL, VPLL_INT_PLL),
XCLOCK_ASSIGN_FIXEDFACTORS(XCLOCK_TYPE_DIVIDER, ACPU_DIV0),
};
/*****************************************************************************/
/*
*
* Recalculate fixed factor rate.
*
* @param FixFactIndex is the database index of fixed factor to
* recalculate rate for.
* @param ParentRate is the rate of fixed factor parent.
* @param Rate is the pointer to variable holding recalculated rate.
*
* @return XST_SUCCESS if successful.
* XST_INVALID_PARAM if invalid argument.
*
* @note None.
*
******************************************************************************/
static XStatus XClock_FixedFactorRecalcRate(u8 FixFactIndex,
XClockRate ParentRate, XClockRate *Rate)
{
/* Validate Index */
XCLOCK_VALIDATE_INDEX(FIXEDFACTOR, FixFactIndex);
XCLOCK_VALIDATE_PTR(Rate);
*Rate = ParentRate * FixedFactors[FixFactIndex].Multiplier;
*Rate = *Rate / FixedFactors[FixFactIndex].Divisor;
return XST_SUCCESS;
}
/*****************************************************************************/
/*
*
* Initialize fixed factor node.
*
* @param FixFactIndex is the database index of fixed factor to
* initialize.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void XClock_FixedFactorInit(u8 FixFactIndex)
{
u8 ParentType;
u8 ParentIdx;
XClockRate ParentRate;
XClockRate Rate;
XCLOCK_VALIDATE_INDEX_WARN(FIXEDFACTOR, FixFactIndex);
if (!FixedFactors[FixFactIndex].IsInit) {
/* Init parent */
ParentType = XCLOCK_FETCH_PARENT_TYPE
(FixedFactors[FixFactIndex].Parent);
ParentIdx = XCLOCK_FETCH_PARENT_INDEX
(FixedFactors[FixFactIndex].Parent);
XClock_InitClk((XClock_Types)ParentType, ParentIdx);
/* Set rate */
ParentRate = XClock_FetchRate((XClock_Types)ParentType, ParentIdx);
if (XST_SUCCESS !=
XClock_FixedFactorRecalcRate(FixFactIndex, ParentRate, &Rate)) {
xil_printf("Warning: Failed to Recalculate rate for "
"Fixedfactor at index %d", FixFactIndex);
return;
}
FixedFactors[FixFactIndex].Rate = Rate;
FixedFactors[FixFactIndex].IsInit = TRUE;
}
}
/*****************************************************************************/
/*
*
* Enable function for fixed factors.
*
* @param FixFactIndex is the database index of fixed factor to enable.
*
* @return XST_SUCCESS if successful.
* XST_INVALID_PARAM if arguments are invalid.
* XST_FAILURE otherwise.
*
* @note None.
*
******************************************************************************/
static XStatus XClock_FixedFactorEnable(u8 FixFactIndex)
{
u8 ParentType;
u8 ParentIdx;
/* Validate arguments */
XCLOCK_VALIDATE_INDEX(FIXEDFACTOR, FixFactIndex);
/* Fetch parent information */
ParentType = XCLOCK_FETCH_PARENT_TYPE
(FixedFactors[FixFactIndex].Parent);
ParentIdx = XCLOCK_FETCH_PARENT_INDEX
(FixedFactors[FixFactIndex].Parent);
/* Enable parent node */
if (XST_SUCCESS != XClock_EnableClkNode((XClock_Types)ParentType, ParentIdx)) {
return XST_FAILURE;
}
FixedFactors[FixFactIndex].EnableCount++;
return XST_SUCCESS;
}
/*****************************************************************************/
/*
*
* Disable function for fixed factors.
*
* @param FixFactIndex is the database index of fixed factor to disable.
*
* @return XST_SUCCESS if successful.
* XST_INVALID_PARAM if arguments are invalid.
* XST_FAILURE otherwise.
*
* @note None.
*
******************************************************************************/
static XStatus XClock_FixedFactorDisable(u8 FixFactIndex)
{
u8 ParentType;
u8 ParentIdx;
/* Validate arguments */
XCLOCK_VALIDATE_INDEX(FIXEDFACTOR, FixFactIndex);
/* Check enable status */
if (!FixedFactors[FixFactIndex].EnableCount) {
return XST_SUCCESS;
}
/* Fetch parent information */
ParentType = XCLOCK_FETCH_PARENT_TYPE
(FixedFactors[FixFactIndex].Parent);
ParentIdx = XCLOCK_FETCH_PARENT_INDEX
(FixedFactors[FixFactIndex].Parent);
/* Disable parent node */
if (XST_SUCCESS != XClock_DisableClkNode((XClock_Types)ParentType, ParentIdx)) {
return XST_FAILURE;
}
FixedFactors[FixFactIndex].EnableCount--;
return XST_SUCCESS;
}
/*****************************************************************************/
/*
*
* This function fetchs the parent based on index in database.
*
* @param ClockId is the identifier for output clock.
* @param NodeType is the pointer holding type of the node.
* @param FixFactIndex is the pointer holding index of parent in database.
*
* @return XST_SUCCESS if successful.
* XST_INVALID_PARAM if output clock mapping not found.
*
* @note None.
*
******************************************************************************/
static XStatus XClock_FixedFactorFetchParent(XClock_Types *NodeType,
u8 *FixFactIndex)
{
/* Validate Args */
XCLOCK_VALIDATE_PTR(NodeType);
XCLOCK_VALIDATE_PTR(FixFactIndex);
XCLOCK_VALIDATE_INDEX(FIXEDFACTOR, *FixFactIndex);
*NodeType = (XClock_Types)XCLOCK_FETCH_PARENT_TYPE
(FixedFactors[*FixFactIndex].Parent);
*FixFactIndex = XCLOCK_FETCH_PARENT_INDEX
(FixedFactors[*FixFactIndex].Parent);
return XST_SUCCESS;
}
/*****************************************************************************/
/*
*
* Get Fixed factor rate.
*
* @param FixFactIndex is the database index of fixed factor to fetch
* rate for.
* @param GetRate is pointer to variable holding fixed factor rate.
*
* @return XST_SUCCESS if successful.
* XST_INVALID_PARAM for invalid function arguments.
*
* @note None.
*
******************************************************************************/
static XStatus XClock_FixedFactorGetRate(u8 FixFactIndex, XClockRate *GetRate)
{
/* Validate args */
XCLOCK_VALIDATE_INDEX(FIXEDFACTOR, FixFactIndex);
XCLOCK_VALIDATE_PTR(GetRate);
*GetRate = FixedFactors[FixFactIndex].Rate;
return XST_SUCCESS;
}
/*****************************************************************************/
/*
*
* The function updates the rate of fixed factor node.
*
* @param FixFactIndex is the database index of fixed factor to
* update rate for.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void XClock_FixedFactorUpdateRate(u8 FixFactIndex)
{
u8 ParentType;
u8 ParentIdx;
XClockRate ParentRate;
XClockRate Rate;
XCLOCK_VALIDATE_INDEX_WARN(FIXEDFACTOR, FixFactIndex);
/* Fetch parent */
ParentType = XCLOCK_FETCH_PARENT_TYPE
(FixedFactors[FixFactIndex].Parent);
ParentIdx = XCLOCK_FETCH_PARENT_INDEX
(FixedFactors[FixFactIndex].Parent);
XClock_UpdateRate((XClock_Types)ParentType, ParentIdx);
/* Set rate */
ParentRate = XClock_FetchRate((XClock_Types)ParentType, ParentIdx);
if (XST_SUCCESS !=
XClock_FixedFactorRecalcRate(FixFactIndex, ParentRate, &Rate)) {
xil_printf("Warning: Failed to Recalculate rate for "
"Fixedfactor at index %d", FixFactIndex);
return;
}
FixedFactors[FixFactIndex].Rate = Rate;
}
/*****************************************************************************/
/*
*
* Register functions for fixed factor node.
*
* @param None.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XClock_FixedFactorRegisterFuncs(void)
{
/* Register functions */
XClock_NodeInit[XCLOCK_TYPE_FIXEDFACTOR] =
&XClock_FixedFactorInit;
XClock_NodeEnable[XCLOCK_TYPE_FIXEDFACTOR] =
&XClock_FixedFactorEnable;
XClock_NodeDisable[XCLOCK_TYPE_FIXEDFACTOR] =
&XClock_FixedFactorDisable;
XClock_NodeFetchParent[XCLOCK_TYPE_FIXEDFACTOR] =
&XClock_FixedFactorFetchParent;
XClock_NodeGetRate[XCLOCK_TYPE_FIXEDFACTOR] =
&XClock_FixedFactorGetRate;
XClock_NodeUpdateRate[XCLOCK_TYPE_FIXEDFACTOR] =
&XClock_FixedFactorUpdateRate;
}
/*****************************************************************************/
/*
*
* Begin Initialization of all fixed factor node.
*
* @param None.
*
* @return None.
*
* @note This function loops over all the fixed factor nodes and
* initializes them.
*
******************************************************************************/
void XClock_FixedFactorBeginInit(void)
{
u8 Idx;
for (Idx = 0; Idx < CLK_ARRAY_SIZE(FixedFactors); Idx++) {
XClock_FixedFactorInit(Idx);
}
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_mod_pm.c
/******************************************************************************
* Copyright (c) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_config.h"
#include "xpfw_core.h"
#include "xpfw_events.h"
#include "xpfw_module.h"
#include "pm_binding.h"
#include "pm_defs.h"
#include "xpfw_ipi_manager.h"
#include "xpfw_mod_pm.h"
#ifdef ENABLE_PM
#define PM_MAX_MSG_LEN XPFW_IPI_MAX_MSG_LEN
const XPfw_Module_t *PmModPtr;
static void PmIpiHandler(const XPfw_Module_t *ModPtr, u32 IpiNum, u32 SrcMask, const u32* Payload, u8 Len)
{
XPfw_PmIpiStatus ipiStatus;
u32 isrVal;
switch (IpiNum) {
case 0U:
ipiStatus = XPfw_PmCheckIpiRequest(SrcMask, &Payload[0]);
if (XPFW_PM_IPI_IS_PM_CALL == ipiStatus) {
/* Power management API processing */
if (XST_SUCCESS != XPfw_PmIpiHandler(SrcMask, &Payload[0], Len)) {
XPfw_Printf(DEBUG_DETAILED,"MOD-%d: Error in processing IPI"
"\r\n", ModPtr->ModId);
}
} else {
XPfw_Printf(DEBUG_DETAILED,"MOD-%d: Non-PM IPI-%lu call received"
"\r\n", ModPtr->ModId, IpiNum);
}
break;
case 1U:
isrVal = XPfw_Read32(IPI_PMU_1_ISR);
XPfw_Write32(IPI_PMU_1_ISR, isrVal);
break;
case 2U:
isrVal = XPfw_Read32(IPI_PMU_2_ISR);
XPfw_Write32(IPI_PMU_2_ISR, isrVal);
break;
case 3U:
isrVal = XPfw_Read32(IPI_PMU_3_ISR);
XPfw_Write32(IPI_PMU_3_ISR, isrVal);
break;
default:
XPfw_Printf(DEBUG_ERROR,"ERROR: Invalid IPI Number: %lu\r\n", IpiNum);
break;
}
}
static void PmEventHandler(const XPfw_Module_t *ModPtr, u32 EventId)
{
u32 EvType, RegValue;
EvType = XPfw_EventGetType(EventId);
switch (EvType) {
case XPFW_EV_TYPE_GPI1:
RegValue = XPfw_EventGetRegMask(EventId);
if (XPfw_PmWakeHandler(RegValue) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED, "ERROR: Unknown processor %lu\r\n",
RegValue);
}
break;
case XPFW_EV_TYPE_GPI2:
RegValue = XPfw_EventGetRegMask(EventId);
if (XST_SUCCESS != XPfw_PmWfiHandler(RegValue)) {
XPfw_Printf(DEBUG_DETAILED, "Error in WFI event\r\n");
}
break;
default:
XPfw_Printf(DEBUG_ERROR,"Unhandled PM Event: %lu\r\n", EventId);
break;
}
}
static void PmCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
{
/* Add Event Handlers for PM */
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_0_WAKE) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_ACPU_0_WAKE)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_1_WAKE) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_ACPU_1_WAKE)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_2_WAKE) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_ACPU_2_WAKE)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_3_WAKE) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_ACPU_3_WAKE)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_R5_0_WAKE) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_R5_0_WAKE)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_R5_1_WAKE) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_R5_1_WAKE)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_0) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_MIO_WAKE_0)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_1) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_MIO_WAKE_1)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_2) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_MIO_WAKE_2)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_3) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_MIO_WAKE_3)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_4) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_MIO_WAKE_4)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_5) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_MIO_WAKE_5)
}
if (XPfw_CoreRegisterEvent(ModPtr,
XPFW_EV_FPD_WAKE_GIC_PROXY) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_FPD_WAKE_GIC_PROXY)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_USB_0_WAKE) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_USB_0_WAKE)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_USB_1_WAKE) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_USB_1_WAKE)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_0_SLEEP) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_ACPU_0_SLEEP)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_1_SLEEP) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_ACPU_1_SLEEP)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_2_SLEEP) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_ACPU_2_SLEEP)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_3_SLEEP) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_ACPU_3_SLEEP)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_R5_0_SLEEP) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_R5_0_SLEEP)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_R5_1_SLEEP) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,
"Warning: PmCfgInit: Failed to register event ID:"
" %d\r\n", XPFW_EV_R5_1_SLEEP)
}
XPfw_PmInit();
}
void ModPmInit(void)
{
PmModPtr = XPfw_CoreCreateMod();
if (XST_SUCCESS != XPfw_CoreSetCfgHandler(PmModPtr, PmCfgInit)) {
XPfw_Printf(DEBUG_DETAILED,"PM: Set Cfg handler failed\r\n");
} else if (XST_SUCCESS !=
XPfw_CoreSetEventHandler(PmModPtr, PmEventHandler)) {
XPfw_Printf(DEBUG_DETAILED,"PM: Set Event handler failed\r\n");
} else if (XST_SUCCESS !=
XPfw_CoreSetIpiHandler(PmModPtr, PmIpiHandler, 0U)) {
XPfw_Printf(DEBUG_DETAILED,"PM: Set IPI handler failed\r\n");
}
}
#else /* ENABLE_PM */
void ModPmInit(void) { }
#endif /* ENABLE_PM */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_mem.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_MEM_H_
#define XPM_MEM_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef struct XPm_MemDevice {
XPm_Device Device; /**< Device: Base class */
u32 StartAddress;
u32 EndAddress;
} XPm_MemDevice;
/************************** Function Prototypes ******************************/
XStatus XPmMemDevice_Init(XPm_MemDevice *MemDevice,
u32 Id,
u32 BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock, XPm_ResetNode *Reset, u32 MemStartAddress,
u32 MemEndAddress);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_MEM_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_prot.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_common.h"
#include "xpm_node.h"
#include "xpm_regs.h"
#include "xpm_subsystem.h"
#include "xpm_device.h"
#include "xpm_prot.h"
static XPm_Prot *PmProtNodes[XPM_NODEIDX_PROT_MAX];
#define SIZE_64K (0x10000U)
#define SIZE_1M (0x100000U)
#define SIZE_512M (0x20000000U)
/**
* Following macros represent staring and ending aperture offsets
* as defined in the XPPU HW Spec.
* 64k Apertures: 0-255
* 1m Apertures: 384-399
* 512m Aperture: 400
*/
#define APER_64K_START (0U)
#define APER_64K_END (255U)
#define APER_1M_START (384U)
#define APER_1M_END (399U)
#define APER_512M_START (400U)
#define APER_512M_END (400U)
#define MAX_PERM_REGS (13U)
#define MAX_APER_PARITY_FIELDS (4U)
#define APER_PARITY_FIELD_WIDTH (5U)
#define APER_PARITY_FIELD_MASK (0x1FU)
/** Refer: Section "XPPU protection for IPI" from XPPU Spec */
#define APER_IPI_MIN (49U)
#define APER_IPI_MAX (63U)
static XStatus XPmProt_Init(XPm_Prot *ProtNode, u32 Id, u32 BaseAddr)
{
XStatus Status = XST_FAILURE;
u32 NodeIndex = NODEINDEX(Id);
if ((u32)XPM_NODEIDX_PROT_MAX <= NodeIndex) {
goto done;
}
XPmNode_Init(&ProtNode->Node, Id, (u8)XPM_PROT_DISABLED, BaseAddr);
PmProtNodes[NodeIndex] = ProtNode;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmProtPpu_Init(XPm_ProtPpu *PpuNode, u32 Id, u32 BaseAddr)
{
XStatus Status = XST_FAILURE;
Status = XPmProt_Init((XPm_Prot *)PpuNode, Id, BaseAddr);
if (XST_SUCCESS != Status) {
goto done;
}
/* Parity status bits */
PpuNode->MIDParityEn = 0;
PpuNode->AperParityEn = 0;
/* Init addresses - 64k */
PpuNode->Aperture_64k.NumSupported = 0;
PpuNode->Aperture_64k.StartAddress = 0;
PpuNode->Aperture_64k.EndAddress = 0;
/* Init addresses - 1m */
PpuNode->Aperture_1m.NumSupported = 0;
PpuNode->Aperture_1m.StartAddress = 0;
PpuNode->Aperture_1m.EndAddress = 0;
/* Init addresses - 512mb */
PpuNode->Aperture_512m.NumSupported = 0;
PpuNode->Aperture_512m.StartAddress = 0;
PpuNode->Aperture_512m.EndAddress = 0;
done:
return Status;
}
XStatus XPmProtMpu_Init(XPm_ProtMpu *MpuNode, u32 Id, u32 BaseAddr)
{
XStatus Status = XST_FAILURE;
Status = XPmProt_Init((XPm_Prot *)MpuNode, Id, BaseAddr);
if (XST_SUCCESS != Status) {
goto done;
}
/* TODO: XMPU Init addresses */
done:
return Status;
}
static XPm_Prot *XPmProt_GetById(const u32 Id)
{
XPm_Prot *ProtNode = NULL;
if (((u32)XPM_NODECLASS_PROTECTION != NODECLASS(Id)) ||
((u32)XPM_NODEIDX_PROT_MAX <= NODEINDEX(Id))) {
goto done;
}
ProtNode = PmProtNodes[NODEINDEX(Id)];
/* Check that internal ID is same as given ID or not. */
if ((NULL != ProtNode) && (Id != ProtNode->Node.Id)) {
ProtNode = NULL;
}
done:
return ProtNode;
}
static void XPmProt_XppuSetAperture(const XPm_ProtPpu *PpuNode, u32 AperAddr, u32 AperVal)
{
u32 i, RegVal, Field, FieldParity, Tz;
u32 Parity = 0;
/* Clear parity bits */
RegVal = AperVal & ~XPPU_APERTURE_PARITY_MASK;
if (0x0U == PpuNode->AperParityEn) {
goto done;
}
/* Extract TrustZone bit */
Tz = (RegVal >> XPPU_APERTURE_TRUSTZONE_OFFSET) & 0x1U;
/**
* Enabling aperture parity provides a benefit that in terms of
* security of the XPPU module itself. Anytime an aperture entry
* is fetched from the local RAM, HW and SW computed parities are
* compared; if they mismatch then transaction fails and parity error
* is flagged.
*
* Parity for bits in this register.
* bit 28: [4:0].
* bit 29: [9:5].
* bit 30: [14:10].
* bit 31: [27],[19:15].
*/
for (i = 0; i < MAX_APER_PARITY_FIELDS; i++)
{
Field = (RegVal >> (i * APER_PARITY_FIELD_WIDTH));
FieldParity = XPm_ComputeParity(Field & APER_PARITY_FIELD_MASK);
if (i == MAX_APER_PARITY_FIELDS - 1U) {
FieldParity ^= Tz;
}
Parity |= (FieldParity << i);
}
/* Set parity bits */
RegVal |= (Parity << XPPU_APERTURE_PARITY_SHIFT);
done:
PmOut32(AperAddr, RegVal);
}
XStatus XPmProt_XppuEnable(u32 NodeId, u32 ApertureInitVal)
{
XStatus Status = XST_FAILURE;
u32 i = 0;
XPm_ProtPpu *PpuNode = (XPm_ProtPpu *)XPmProt_GetById(NodeId);
u32 Address, BaseAddr, RegVal;
if (PpuNode == NULL) {
goto done;
}
/* XPPU Base Address */
BaseAddr = PpuNode->ProtNode.Node.BaseAddress;
if ((PLATFORM_VERSION_SILICON == Platform) && (PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
/* Disable permission checks for all apertures */
Address = BaseAddr + XPPU_ENABLE_PERM_CHECK_REG00_OFFSET;
for (i = 0; i < MAX_PERM_REGS; i++)
{
PmOut32(Address, 0x0U);
Address = Address + 0x4U;
}
}
/* Get Number of Apertures supported */
PmIn32(BaseAddr + XPPU_M_APERTURE_64KB_OFFSET, RegVal);
PpuNode->Aperture_64k.NumSupported = RegVal;
Xil_AssertNonvoid((APER_64K_END - APER_64K_START + 1U) == PpuNode->Aperture_64k.NumSupported);
PmIn32(BaseAddr + XPPU_M_APERTURE_1MB_OFFSET, RegVal);
PpuNode->Aperture_1m.NumSupported = RegVal;
Xil_AssertNonvoid((APER_1M_END - APER_1M_START + 1U) == PpuNode->Aperture_1m.NumSupported);
PmIn32(BaseAddr + XPPU_M_APERTURE_512MB_OFFSET, RegVal);
PpuNode->Aperture_512m.NumSupported = RegVal;
Xil_AssertNonvoid((APER_512M_END - APER_512M_START + 1U) == PpuNode->Aperture_512m.NumSupported);
/* Store parity bits settings */
PmIn32(BaseAddr + XPPU_CTRL_OFFSET, RegVal);
PpuNode->MIDParityEn = (u8)((RegVal >> XPPU_CTRL_MID_PARITY_EN_SHIFT) & 0x1U);
PpuNode->AperParityEn = (u8)((RegVal >> XPPU_CTRL_APER_PARITY_EN_SHIFT) & 0x1U);
/* Initialize all apertures for default value */
Address = BaseAddr + XPPU_APERTURE_0_OFFSET;
for (i = APER_64K_START; i <= APER_64K_END; i++) {
/**
* In Versal, message buffer protection is moved out of XPPU, to IPI.
* Therefore, XPPU permissions for IPI specific apertures (aperture 49 to aperture 63)
* should be configured to allow all. This is applicable to LPD XPPU only.
*
* Refer "XPPU protection for IPI" from XPPU Spec
*/
if (((u32)XPM_NODEIDX_PROT_XPPU_LPD == NODEINDEX(NodeId))
&& ((i >= APER_IPI_MIN) && (i <= APER_IPI_MAX))) {
XPmProt_XppuSetAperture(PpuNode, Address, (ApertureInitVal | XPPU_APERTURE_PERMISSION_MASK));
} else {
XPmProt_XppuSetAperture(PpuNode, Address, ApertureInitVal);
}
Address = Address + 0x4U;
}
Address = BaseAddr + XPPU_APERTURE_384_OFFSET;
for (i = APER_1M_START; i <= APER_1M_END; i++) {
XPmProt_XppuSetAperture(PpuNode, Address, ApertureInitVal);
Address = Address + 0x4U;
}
Address = BaseAddr + XPPU_APERTURE_400_OFFSET;
for (i = APER_512M_START; i <= APER_512M_END; i++) {
XPmProt_XppuSetAperture(PpuNode, Address, ApertureInitVal);
Address = Address + 0x4U;
}
if ((PLATFORM_VERSION_SILICON == Platform) && (PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
/* Enable permission checks for all apertures */
Address = BaseAddr + XPPU_ENABLE_PERM_CHECK_REG00_OFFSET;
for (i = 0; i < MAX_PERM_REGS; i++)
{
PmOut32(Address, 0xFFFFFFFFU);
Address = Address + 0x4U;
}
}
/* Get Aperture start and end addresses */
PmIn32(BaseAddr + XPPU_BASE_64KB_OFFSET, RegVal);
PpuNode->Aperture_64k.StartAddress = RegVal;
PpuNode->Aperture_64k.EndAddress =
(PpuNode->Aperture_64k.StartAddress + (PpuNode->Aperture_64k.NumSupported * SIZE_64K) - 1U);
PmIn32(BaseAddr + XPPU_BASE_1MB_OFFSET, RegVal);
PpuNode->Aperture_1m.StartAddress = RegVal;
PpuNode->Aperture_1m.EndAddress =
(PpuNode->Aperture_1m.StartAddress + (PpuNode->Aperture_1m.NumSupported * SIZE_1M) - 1U);
PmIn32(BaseAddr + XPPU_BASE_512MB_OFFSET, RegVal);
PpuNode->Aperture_512m.StartAddress = RegVal;
PpuNode->Aperture_512m.EndAddress =
(PpuNode->Aperture_512m.StartAddress + (PpuNode->Aperture_512m.NumSupported * SIZE_512M) - 1U);
/* Enable Xppu */
PmRmw32(BaseAddr + XPPU_CTRL_OFFSET, XPPU_CTRL_ENABLE_MASK, XPPU_CTRL_ENABLE_MASK);
PpuNode->ProtNode.Node.State = (u8)XPM_PROT_ENABLED;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmProt_XppuDisable(u32 NodeId)
{
XStatus Status = XST_FAILURE;
XPm_ProtPpu *PpuNode = (XPm_ProtPpu *)XPmProt_GetById(NodeId);
u32 Address, idx;
if (PpuNode == NULL) {
Status = XST_FAILURE;
goto done;
}
if ((PLATFORM_VERSION_SILICON == Platform) && (PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
/* Disable permission checks for all apertures */
Address = PpuNode->ProtNode.Node.BaseAddress + XPPU_ENABLE_PERM_CHECK_REG00_OFFSET;
for (idx = 0; idx < MAX_PERM_REGS; idx++)
{
PmOut32(Address, 0x0);
Address = Address + 0x4U;
}
}
/* Disable Xppu */
PmRmw32(PpuNode->ProtNode.Node.BaseAddress + XPPU_CTRL_OFFSET,
XPPU_CTRL_ENABLE_MASK, ~XPPU_CTRL_ENABLE_MASK);
PpuNode->ProtNode.Node.State = (u8)XPM_PROT_DISABLED;
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus XPmProt_ConfigureXppu(XPm_Requirement *Reqm, u32 Enable)
{
XStatus Status = XST_FAILURE;
u32 DeviceBaseAddr = Reqm->Device->Node.BaseAddress;
XPm_ProtPpu *PpuNode = NULL;
u32 ApertureOffset = 0, ApertureAddress = 0;
u32 Permissions = 0, i;
u32 DynamicReconfigAddrOffset = 0;
u32 PermissionRegAddress = 0;
u32 PermissionRegMask = 0;
PmDbg("Xppu configure %x\r\n", Enable);
PmDbg("Device base %x\r\n", DeviceBaseAddr);
/* Find XPPU */
for (i = 0; i < (u32)XPM_NODEIDX_PROT_MAX; i++)
{
if ((PmProtNodes[i] != NULL)
&& ((u32)XPM_NODESUBCL_PROT_XPPU == NODESUBCLASS(PmProtNodes[i]->Node.Id))) {
PpuNode = (XPm_ProtPpu *)PmProtNodes[i];
if ((DeviceBaseAddr >= PpuNode->Aperture_64k.StartAddress) && (DeviceBaseAddr <= PpuNode->Aperture_64k.EndAddress)) {
ApertureOffset = (DeviceBaseAddr - PpuNode->Aperture_64k.StartAddress) / SIZE_64K;
ApertureAddress = (PpuNode->ProtNode.Node.BaseAddress + XPPU_APERTURE_0_OFFSET) + (ApertureOffset * 4U);
DynamicReconfigAddrOffset = ApertureOffset;
PermissionRegAddress = PpuNode->ProtNode.Node.BaseAddress + XPPU_ENABLE_PERM_CHECK_REG00_OFFSET + (((APER_64K_START + ApertureOffset) / 32U) * 4U);
PermissionRegMask = (u32)1U << ((APER_64K_START + ApertureOffset) % 32U);
} else if ((DeviceBaseAddr >= PpuNode->Aperture_1m.StartAddress) && (DeviceBaseAddr <= PpuNode->Aperture_1m.EndAddress)) {
ApertureOffset = (DeviceBaseAddr - PpuNode->Aperture_1m.StartAddress) / SIZE_1M;
ApertureAddress = (PpuNode->ProtNode.Node.BaseAddress + XPPU_APERTURE_384_OFFSET) + (ApertureOffset * 4U);
DynamicReconfigAddrOffset = ApertureOffset;
PermissionRegAddress = PpuNode->ProtNode.Node.BaseAddress + XPPU_ENABLE_PERM_CHECK_REG00_OFFSET + (((APER_1M_START + ApertureOffset) / 32U) * 4U);
PermissionRegMask = (u32)1U << ((APER_1M_START + ApertureOffset) % 32U);
/*TODO: 512M start and end address need to be validated */
/*} else if ((DeviceBaseAddr >= PpuNode->Aperture_512m.StartAddress) && (DeviceBaseAddr <= PpuNode->Aperture_512m.EndAddress)) {
ApertureOffset = (DeviceBaseAddr - PpuNode->Aperture_512m.StartAddress) / SIZE_512M;
ApertureAddress = (PpuNode->ProtNode.Node.BaseAddress + XPPU_APERTURE_400_OFFSET) + (ApertureOffset * 4);
DynamicReconfigAddrOffset = APER_512M_START;
PermissionRegAddress = PpuNode->ProtNode.Node.BaseAddress + XPPU_ENABLE_PERM_CHECK_REG00_OFFSET + (((APER_512M_START + ApertureOffset) / 32) * 4);
PermissionRegMask = 1 << ((APER_512M_START + ApertureOffset) % 32); */
} else {
continue;
}
break;
}
}
if ((i == (u32)XPM_NODEIDX_PROT_MAX) || (NULL == PpuNode) || (0U == ApertureAddress)) {
Status = XST_SUCCESS;
goto done;
}
/* See if XPPU is enabled or not, if not, return */
if ((u8)XPM_PROT_DISABLED == PpuNode->ProtNode.Node.State) {
Status = XST_SUCCESS;
goto done;
}
PmDbg("Aperoffset %x AperAddress %x DynamicReconfigAddrOffset %x\r\n",ApertureOffset, ApertureAddress, DynamicReconfigAddrOffset);
if (0U != Enable) {
u8 UsagePolicy = Reqm->Flags & REG_FLAGS_USAGE_MASK;
u32 Security = (Reqm->Flags & (u32)REG_FLAGS_SECURITY_MASK) >> REG_FLAGS_SECURITY_OFFSET;
PmIn32(ApertureAddress, Permissions);
/* Configure XPPU Aperture */
if ((UsagePolicy == (u8)REQ_NONSHARED) || (UsagePolicy == (u8)REQ_TIME_SHARED)) {
Permissions = ((Security << XPPU_APERTURE_TRUSTZONE_OFFSET) | (Reqm->Params[0] & XPPU_APERTURE_PERMISSION_MASK));
} else if (UsagePolicy == (u8)REQ_SHARED) {
/* if device is shared, permissions need to be ored with existing */
Permissions |= ((Security << XPPU_APERTURE_TRUSTZONE_OFFSET) | (Reqm->Params[0] & XPPU_APERTURE_PERMISSION_MASK));
} else if (UsagePolicy == (u8)REQ_NO_RESTRICTION) {
Permissions = (XPPU_APERTURE_PERMISSION_MASK | XPPU_APERTURE_TRUSTZONE_MASK);
} else {
/* Required due to MISRA */
PmDbg("Invalid UsagePolicy %d\r\n", UsagePolicy);
}
} else {
/* Configure XPPU to disable masters belonging to this subsystem */
Permissions = (Permissions | XPPU_APERTURE_TRUSTZONE_MASK);
Permissions = (Permissions & (~(Reqm->Params[0] & XPPU_APERTURE_PERMISSION_MASK)));
}
PmDbg("PermissionRegAddress %x Permissions %x RegMask %x \r\n",PermissionRegAddress, Permissions, PermissionRegMask);
if ((PLATFORM_VERSION_SILICON == Platform) && (PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
/* Set XPPU control to 0 */
PmRmw32(PpuNode->ProtNode.Node.BaseAddress + XPPU_CTRL_OFFSET,
XPPU_CTRL_ENABLE_MASK, ~XPPU_CTRL_ENABLE_MASK);
/* Set Enable Permission check of the required apertures to 0 */
PmRmw32(PermissionRegAddress, PermissionRegMask, 0);
/* Program permissions of the apertures that need to be �reconfigured� */
XPmProt_XppuSetAperture(PpuNode, ApertureAddress, Permissions);
/* Enable back permission check of the apertures */
PmRmw32(PermissionRegAddress, PermissionRegMask, PermissionRegMask);
/* Set XPPU control to 1 */
PmRmw32(PpuNode->ProtNode.Node.BaseAddress + XPPU_CTRL_OFFSET,
XPPU_CTRL_ENABLE_MASK, XPPU_CTRL_ENABLE_MASK);
} else {
/* Configure Dynamic reconfig enable registers before changing XPPU config */
PmOut32(PpuNode->ProtNode.Node.BaseAddress + XPPU_DYNAMIC_RECONFIG_APER_ADDR_OFFSET, DynamicReconfigAddrOffset);
PmOut32(PpuNode->ProtNode.Node.BaseAddress + XPPU_DYNAMIC_RECONFIG_APER_PERM_OFFSET, Permissions);
PmOut32(PpuNode->ProtNode.Node.BaseAddress + XPPU_DYNAMIC_RECONFIG_EN_OFFSET, 1);
/* Write values to Aperture */
XPmProt_XppuSetAperture(PpuNode, ApertureAddress, Permissions);
/* Disable dynamic reconfig enable once done */
PmOut32(PpuNode->ProtNode.Node.BaseAddress + XPPU_DYNAMIC_RECONFIG_EN_OFFSET, 0);
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmProt_Configure(XPm_Requirement *Reqm, u32 Enable)
{
XStatus Status = XST_FAILURE;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
if ((u32)XPM_NODESUBCL_DEV_PERIPH == NODESUBCLASS(Reqm->Device->Node.Id)) {
/* TODO: Some of the FPD peripherals are protected by XMPU. so based on device's baseaddress,
we need to find whether to configure XMPu/XPPU */
/* TODO: Need to know which addresse range particular XMPU protects */
Status = XPmProt_ConfigureXppu(Reqm, Enable);
} else {
Status = XST_SUCCESS;
goto done;
}
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_ddr.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* DDR slave definition
*
* Note: In ON state DDR depends on FPD (cannot be accessed if FPD is
* not on). Therefore, power parent of DDR is FPD.
*********************************************************************/
#include "crf_apb.h"
#include "pm_ddr.h"
#include "pm_csudma.h"
#include "pm_common.h"
#include "pm_defs.h"
#include "pm_master.h"
#include "xpfw_util.h"
#include "xpfw_aib.h"
#include "pm_system.h"
#include "pm_node.h"
#include "pm_clock.h"
#include "pm_hooks.h"
#define DDRC_BASE 0xFD070000U
#define DDRC_MSTR (DDRC_BASE + 0U)
#define DDRC_STAT (DDRC_BASE + 4U)
#define DDRC_MRCTRL0 (DDRC_BASE + 0X10U)
#define DDRC_DERATEEN (DDRC_BASE + 0X20U)
#define DDRC_DERATEINT (DDRC_BASE + 0X24U)
#define DDRC_PWRCTL (DDRC_BASE + 0x30U)
#define DDRC_PWRTMG (DDRC_BASE + 0X34U)
#define DDRC_RFSHCTL0 (DDRC_BASE + 0X50U)
#define DDRC_RFSHCTL1 (DDRC_BASE + 0X54U)
#define DDRC_RFSHCTL3 (DDRC_BASE + 0x60U)
#define DDRC_RFSHTMG (DDRC_BASE + 0x64U)
#define DDRC_ECCCFG0 (DDRC_BASE + 0X70U)
#define DDRC_ECCCFG1 (DDRC_BASE + 0X74U)
#define DDRC_ERRCLR (DDRC_BASE + 0x7CU)
#define DDRC_ERRCNT (DDRC_BASE + 0x80U)
#define DDRC_CRCPARCTL1 (DDRC_BASE + 0XC4U)
#define DDRC_CRCPARCTL2 (DDRC_BASE + 0XC8U)
#define DDRC_INIT(n) (DDRC_BASE + 0xD0U + (4U * (n)))
#define DDRC_DIMMCTL (DDRC_BASE + 0XF0U)
#define DDRC_RANKCTL (DDRC_BASE + 0XF4U)
#define DDRC_DRAMTMG(n) (DDRC_BASE + 0x100U + (4U * (n)))
#define DDRC_ZQCTL(n) (DDRC_BASE + 0x180U + (4U * (n)))
#define DDRC_DFITMG0 (DDRC_BASE + 0X190U)
#define DDRC_DFITMG1 (DDRC_BASE + 0X194U)
#define DDRC_DFILPCFG(n) (DDRC_BASE + 0X198U + (4U * (n)))
#define DDRC_DFIUPD0 (DDRC_BASE + 0X1A0U)
#define DDRC_DFIUPD1 (DDRC_BASE + 0X1A4U)
#define DDRC_DFIMISC (DDRC_BASE + 0x1b0U)
#define DDRC_DFITMG2 (DDRC_BASE + 0X1B4U)
#define DDRC_DBICTL (DDRC_BASE + 0X1C0U)
#define DDRC_ADDRMAP(n) (DDRC_BASE + 0X200U + (4U * (n)))
#define DDRC_ODTCFG (DDRC_BASE + 0X240U)
#define DDRC_ODTMAP (DDRC_BASE + 0X244U)
#define DDRC_SCHED (DDRC_BASE + 0X250U)
#define DDRC_PERFLPR1 (DDRC_BASE + 0X264U)
#define DDRC_PERFWR1 (DDRC_BASE + 0X26CU)
#define DDRC_DQMAP5 (DDRC_BASE + 0X294U)
#define DDRC_DBG0 (DDRC_BASE + 0X300U)
#define DDRC_DBGCMD (DDRC_BASE + 0X30CU)
#define DDRC_SWCTL (DDRC_BASE + 0x320U)
#define DDRC_SWSTAT (DDRC_BASE + 0x324U)
#define DDRC_PSTAT (DDRC_BASE + 0x3fcU)
#define DDRC_PCCFG (DDRC_BASE + 0X400U)
#define DDRC_PCFGR(n) (DDRC_BASE + 0X404U + (0xb0U * (n)))
#define DDRC_PCFGW(n) (DDRC_BASE + 0X408U + (0xb0U * (n)))
#define DDRC_PCTRL(n) (DDRC_BASE + 0x490U + (0xb0U * (n)))
#define DDRC_PCFGQOS(n, m) (DDRC_BASE + 0X494U + (4U * (n)) + (0xb0U * (m)))
#define DDRC_PCFGWQOS(n, m) (DDRC_BASE + 0x49cU + (4U * (n)) + (0xb0U * (m)))
#define DDRC_SARBASE(n) (DDRC_BASE + 0XF04U + (8U * (n)))
#define DDRC_SARSIZE(n) (DDRC_BASE + 0XF08U + (8U * (n)))
#define DDRC_DFITMG0_SHADOW (DDRC_BASE + 0X2190U)
#define DDRC_PWRCTL_SR_SW BIT(5U)
#define DDRC_MSTR_DDR3 BIT(0U)
#define DDRC_MSTR_LPDDR3 BIT(3U)
#define DDRC_MSTR_DDR4 BIT(4U)
#define DDRC_MSTR_LPDDR4 BIT(5U)
#define DDRC_MSTR_DDR_TYPE (DDRC_MSTR_DDR3 | \
DDRC_MSTR_LPDDR3 | \
DDRC_MSTR_DDR4 | \
DDRC_MSTR_LPDDR4)
#define DDRC_MSTR_BUS_WIDTH_MASK 3U
#define DDRC_MSTR_BUS_WIDTH_SHIFT 12U
#define DDRC_MSTR_BUS_WIDTH_FULL_DQ (0U << DDRC_MSTR_BUS_WIDTH_SHIFT)
#define DDRC_MSTR_BUS_WIDTH_HALF_DQ (1U << DDRC_MSTR_BUS_WIDTH_SHIFT)
#define DDRC_MSTR_BUS_WIDTH_QUART_DQ (2U << DDRC_MSTR_BUS_WIDTH_SHIFT)
#define DDRC_STAT_OPMODE_MASK 7U
#define DDRC_STAT_OPMODE_SHIFT 0U
#define DDRC_STAT_OPMODE_INIT 0U
#define DDRC_STAT_OPMODE_NORMAL 1U
#define DDRC_STAT_OPMODE_SR 3U
#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 ((u32)0x0000001FU)
#define DDRC_ADDRMAP2_ADDRMAP_COL_B4 ((u32)0x000F0000U)
#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16U
#define DDRC_ADDRMAP8_ADDRMAP_BG_B0 ((u32)0x0000001FU)
#define DDRC_SWSTAT_SWDONE BIT(0U)
#define DDRC_PSTAT_PORT_BUSY(n) ((BIT(0U) | BIT(16U)) << (n))
#define DDRC_PCTRL_PORT_EN BIT(0U)
#define DDRC_ZQCTL0_ZQ_DIS BIT(31U)
#define DDRC_RFSHCTL3_AUTORF_DIS BIT(0U)
#define DDRC_DFIMISC_DFI_INIT_COMP_EN BIT(0U)
#define DDRC_SWCTL_SW_DONE BIT(0U)
#define DDRC_DUAL_RANK_MASK (BIT(25U) | BIT(24U))
#define DDRPHY_BASE 0xFD080000U
#define DDRPHY_PIR (DDRPHY_BASE + 4U)
#define DDRPHY_PGCR(n) (DDRPHY_BASE + 0x10U + (4U * (n)))
#define DDRPHY_PGSR(n) (DDRPHY_BASE + 0x30U + (4U * (n)))
#define DDRPHY_PTR(n) (DDRPHY_BASE + 0X40U + (4U * (n)))
#define DDRPHY_PLLCR(n) (DDRPHY_BASE + 0X68U + (4U * (n)))
#define DDRPHY_DSGCR (DDRPHY_BASE + 0X90U)
#define DDRPHY_ODTCR (DDRPHY_BASE + 0X98U)
#define DDRPHY_GPR(n) (DDRPHY_BASE + 0XC0U + (4U * (n)))
#define DDRPHY_DCR (DDRPHY_BASE + 0X100U)
#define DDRPHY_DTPR(n) (DDRPHY_BASE + 0X110U + (4U * (n)))
#define DDRPHY_RDIMMGCR(n) (DDRPHY_BASE + 0x140U + (4U * (n)))
#define DDRPHY_RDIMMCR(n) (DDRPHY_BASE + 0x150U + (4U * (n)))
#define DDRPHY_MR(n) (DDRPHY_BASE + 0X180U + (4U * (n)))
#define DDRPHY_DTCR(n) (DDRPHY_BASE + 0X200U + (4U * (n)))
#define DDRPHY_CATR(n) (DDRPHY_BASE + 0X240U + (4U * (n)))
#define DDRPHY_RANKIDR (DDRPHY_BASE + 0X4DCU)
#define DDRPHY_RIOCR(n) (DDRPHY_BASE + 0X4E0U + (4U * (n)))
#define DDRPHY_ACIOCR(n) (DDRPHY_BASE + 0X500U + (4U * (n)))
#define DDRPHY_IOVCR(n) (DDRPHY_BASE + 0X520U + (4U * (n)))
#define DDRPHY_VTCR(n) (DDRPHY_BASE + 0X528U + (4U * (n)))
#define DDRPHY_DQSDR(n) (DDRPHY_BASE + 0x250U + (4U * (n)))
#define DDRPHY_ACBDLR(n) (DDRPHY_BASE + 0x540U + (4U * (n)))
#define DDRPHY_ZQCR (DDRPHY_BASE + 0x680U)
#define DDRPHY_ZQPR(n, m) (DDRPHY_BASE + 0x684U + (0x20U * (n)) + (4U * (m)))
#define DDRPHY_ZQDR0(n) (DDRPHY_BASE + 0x68cU + (0x20U * (n)))
#define DDRPHY_ZQDR1(n) (DDRPHY_BASE + 0x690U + (0x20U * (n)))
#define DDRPHY_DXGCR(n, m) (DDRPHY_BASE + 0X700U + (0x100U * (n)) + (4U * (m)))
#define DDRPHY_DXGSR0(n) (DDRPHY_BASE + 0X7e0U + (0x100U * (n)))
#define DDRPHY_DX8SLNOSC(n) (DDRPHY_BASE + 0x1400U + (0x40U * (n)))
#define DDRPHY_DX8SLPLLCR(n, m) (DDRPHY_BASE + 0X1404U + (0x40U * (n)) + (4U * (m)))
#define DDRPHY_DX8SLDQSCTL(n) (DDRPHY_BASE + 0x141cU + (0x40U * (n)))
#define DDRPHY_DX8SLDXCTL2(n) (DDRPHY_BASE + 0x142cU + (0x40U * (n)))
#define DDRPHY_DX8SLIOCR(n) (DDRPHY_BASE + 0x1430U + (0x40U * (n)))
#define DDRPHY_DX8SLBOSC (DDRPHY_BASE + 0x17c0U)
#define DDRPHY_PIR_INIT BIT(0U)
#define DDRPHY_PIR_ZCAL BIT(1U)
#define DDRPHY_PIR_CA BIT(2U)
#define DDRPHY_PIR_PLLINIT BIT(4U)
#define DDRPHY_PIR_DCAL BIT(5U)
#define DDRPHY_PIR_PHYRST BIT(6U)
#define DDRPHY_PIR_WL BIT(9U)
#define DDRPHY_PIR_QSGATE BIT(10U)
#define DDRPHY_PIR_WLADJ BIT(11U)
#define DDRPHY_PIR_RDDSKW BIT(12U)
#define DDRPHY_PIR_WRDSKW BIT(13U)
#define DDRPHY_PIR_RDEYE BIT(14U)
#define DDRPHY_PIR_WREYE BIT(15U)
#define DDRPHY_PIR_VREF BIT(17U)
#define DDRPHY_PIR_CTLDINIT BIT(18U)
#define DDRPHY_PIR_RDIMMINIT BIT(19U)
#define DDRPHY_PIR_DQS2DQ BIT(20U)
#define DDRPHY_PIR_ZCALBYP BIT(30U)
#define DDRPHY_PGCR0_PHYFRST BIT(26U)
#define DDRPHY_DXGSR0_DPLOCK BIT(16U)
#define DDRPHY_PGSR0_APLOCK BIT(31U)
#define DDRPHY_PGSR0_SRDERR BIT(30U)
#define DDRPHY_PGSR0_CAWRN BIT(29U)
#define DDRPHY_PGSR0_CAERR BIT(28U)
#define DDRPHY_PGSR0_WEERR BIT(27U)
#define DDRPHY_PGSR0_REERR BIT(26U)
#define DDRPHY_PGSR0_WDERR BIT(25U)
#define DDRPHY_PGSR0_RDERR BIT(24U)
#define DDRPHY_PGSR0_WLAERR BIT(23U)
#define DDRPHY_PGSR0_QSGERR BIT(22U)
#define DDRPHY_PGSR0_WLERR BIT(21U)
#define DDRPHY_PGSR0_ZCERR BIT(20U)
#define DDRPHY_PGSR0_VERR BIT(19U)
#define DDRPHY_PGSR0_DQS2DQERR BIT(18U)
#define DDRPHY_PGSR0_IDONE BIT(0U)
#define DDRPHY_PGSR0_TRAIN_ERRS (DDRPHY_PGSR0_DQS2DQERR | \
DDRPHY_PGSR0_VERR | \
DDRPHY_PGSR0_ZCERR | \
DDRPHY_PGSR0_WLERR | \
DDRPHY_PGSR0_QSGERR | \
DDRPHY_PGSR0_WLAERR | \
DDRPHY_PGSR0_RDERR | \
DDRPHY_PGSR0_WDERR | \
DDRPHY_PGSR0_REERR | \
DDRPHY_PGSR0_WEERR | \
DDRPHY_PGSR0_CAERR | \
DDRPHY_PGSR0_CAWRN | \
DDRPHY_PGSR0_SRDERR)
#define DDRPHY_RDIMMGCR0_RDIMM BIT(0U)
#define DDRPHY_DQSDR0_DFTDTEN BIT(0U)
#define DDRPHY_DQSDR0_DFTDTMODE BIT(1U)
#define DDRPHY_DQSDR0_DFTUPMODE (BIT(2U) | BIT(3U))
#define DDRPHY_DQSDR0_DFTUPMODE_SHIFT 2U
#define DDRPHY_DQSDR0_DFTGPULSE (BIT(4U) | BIT(5U) | BIT(6U) | BIT(7U))
#define DDRPHY_DQSDR0_DFTRDSPC (BIT(20U) | BIT(21U))
#define DDRPHY_DQSDR0_DFTRDSPC_SHIFT 20U
#define DDRPHY_DQSDR0_DFTDLY (BIT(28U) | BIT(29U) | BIT(30U) | BIT(31U))
#define DDRPHY_DQSDR0_DFTDLY_SHIFT 28U
#define DDRPHY_DQSDR1_DFTRDIDLC 0x000000FFU
#define DDRPHY_DQSDR1_DFTRDIDLC_SHIFT 0U
#define DDRPHY_DQSDR1_DFTRDIDLF 0x000F0000U
#define DDRPHY_DQSDR1_DFTRDIDLF_SHIFT 16U
#define DDRPHY_RIOCR2_COEMODE_SHIFT 24U
#define DDRPHY_RIOCR2_COEMODE_MASK (BIT(25) | BIT(24))
#define DDRPHY_RIOCR2_CSOEMODE_MASK (BIT(3) | BIT(2) | BIT(1) | BIT(0))
#define DDRPHY_RIOCR5_ODTOEMODE_MASK (BIT(3) | BIT(2) | BIT(1) | BIT(0))
#define DDRPHY_ACIOCR0_RSTPDR BIT(28)
#define DDRPHY_ACIOCR0_RSTODT BIT(26)
#define DDRPHY_ACIOCR0_ACPDRMDOE_SHIFT 4U
#define DDRPHY_ACIOCR0_ACPDRMDOE_MASK (BIT(5) | BIT(4))
#define DDRPHY_ACIOCR0_ACODTMODE_SHIFT 2U
#define DDRPHY_ACIOCR0_ACODTMODE_MASK (BIT(3) | BIT(2))
#define DDRPHY_ACIOCR1_AOEMODE_MASK ((u32)0xFFFFFFFF)
#define DDRPHY_ACIOCR3_PAROEMODE_SHIFT 30U
#define DDRPHY_ACIOCR3_PAROEMODE_MASK (BIT(31) | BIT(30))
#define DDRPHY_ACIOCR3_BGOEMODE_SHIFT 26U
#define DDRPHY_ACIOCR3_BGOEMODE_MASK (BIT(29) | BIT(28) | BIT(27) | BIT(26))
#define DDRPHY_ACIOCR3_BAOEMODE_SHITT 22U
#define DDRPHY_ACIOCR3_BAOEMODE_MASK (BIT(25) | BIT(24) | BIT(23) | BIT(22))
#define DDRPHY_ACIOCR3_A17OEMODE_SHIFT 20U
#define DDRPHY_ACIOCR3_A17OEMODE_MASK (BIT(21) | BIT(20))
#define DDRPHY_ACIOCR3_A16OEMODE_SHIFT 18U
#define DDRPHY_ACIOCR3_A16OEMODE_MASK (BIT(19) | BIT(18))
#define DDRPHY_ACIOCR3_ACTOEMODE_SHIFT 16U
#define DDRPHY_ACIOCR3_ACTOEMODE_MASK (BIT(17) | BIT(16))
#define DDRPHY_ACIOCR3_CKOEMODE (BIT(3) | BIT(2) | BIT(1) | BIT(0))
#define DDRPHY_IOVCR0_ACREFSEN BIT(25)
#define DDRPHY_IOVCR0_ACREFIEN BIT(24)
#define DDRPHY_ZQCR_ZQREFIEN BIT(11)
#define DDRPHY_ZQCR_ZQPD BIT(0)
#define DDRPHY_ZQnPR0_ZDEN_SHIFT 28U
#define DDRPHY_ZQnPR0_ZDEN_MASK ((u32)0xF0000000U)
#define DDRPHY_ZQnPR0_ZSEGBYP BIT(27U)
#define DDRPHY_ZQnOR_OFFSET 8U
#define DDRPHY_DX8SLBOSC_PHYFRST BIT(15U)
#define DDRPHY_DTCR0_INCWEYE BIT(4U)
#define DDRPHY_DTCR0_RFSHDT_SHIFT 28U
#define DDRPHY_DTCR0_RFSHDT_MASK ((u32)0xF0000000U)
#define DDRPHY_DTCR0_RFSHEN_SHIFT 8U
#define DDRPHY_DTCR0_RFSHEN_MASK ((u32)0x00000F00U)
#define DDRPHY_DSGCR_CTLZUEN BIT(2U)
#define DDRPHY_DSGCR_DTOPDR BIT(14U)
#define DDRPHY_DSGCR_DTOODT BIT(12U)
#define DDRPHY_DXGCR3_WDLVT BIT(25U)
#define DDRPHY_DXGCR3_RGLVT BIT(27U)
#define DDRPHY_RANKWID_MASK (BIT(3U)| BIT(2U) | BIT(1U) | BIT(0U))
#define DDRPHY_RANKRID_MASK (BIT(19U) | BIT(18U) | BIT(17U) | BIT(16U))
#define DDRPHY_RANK0_WRITE BIT(0U)
#define DDRPHY_RANK1_WRITE BIT(1U)
#define DDRPHY_RANK0_READ BIT(16U)
#define DDRPHY_RANK1_READ BIT(17U)
#define DDRQOS_BASE 0xFD090000U
#define DDRQOS_DDR_CLK_CTRL (DDRQOS_BASE + 0x700U)
#define DDRQOS_DDR_CLK_CTRL_CLKACT BIT(0U)
#define PM_DDR_POLL_PERIOD 32000U /* ~1ms @220MHz */
#ifdef ENABLE_DDR_SR_WR
/* Timeout period of around 1 second to poll for DDR flags */
#define DDR_FLAG_POLL_PERIOD XPAR_MICROBLAZE_FREQ
#endif
#define REPORT_IF_ERROR(status) \
if (XST_SUCCESS != status) { \
PmErr("@line %d\r\n", __LINE__); \
}
/* Power states of DDR */
#define PM_DDR_STATE_OFF 0U
#define PM_DDR_STATE_SR 1U
#define PM_DDR_STATE_ON 2U
#define PM_DDR_STATE_MAX 3U
/* Power consumptions for DDR defined by its states */
#define DEFAULT_DDR_POWER_ON 100U
#define DEFAULT_DDR_POWER_SR 50U
#define DEFAULT_DDR_POWER_OFF 0U
/* Number of memory locations used for ddr data training */
#define DDR3_SIZE 0X100U >> 2U
#define DDR4_SIZE 0x200U >> 2U
#define DDR4_SIZE_OLD 0x100U >> 2U
#define LPDDR3_SIZE 0x100U >> 2U
#define LPDDR4_SIZE 0x100U >> 2U
/* DDR4 old mapping ddr data training location offset */
#define OLD_MAP_OFFSET 0x2000U
#define LPDDR4_OLD_MAP_OFFSET 0x4000U
/* DDR reserved address to store training data */
#define RESERVED_ADDRESS XPAR_MICROBLAZE_DDR_RESERVE_SA
/* DIMM address mirroring */
#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN (0x00000002U)
#define IS_ADDR_MIRR() (Xil_In32(DDRC_DIMMCTL) & DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN)
/* ADDRMAP_BG_B1 */
#define DDRC_ADDRMAP8_BG_B1_MASK (0x00001F00U)
#define DDRC_ADDRMAP8_BG_B1_SHIFT (8U)
#define DDRC_ADDRMAP8_BG_B1_BASE (3U)
/* Low DDR address size: 2 GB */
#define DDR_LO_ADDR (0x0000000000000000ULL)
#define DDR_LO_SIZE (0x0000000080000000ULL)
/* High DDR address size: 32 */
#define DDR_HI_ADDR (0x0000000800000000ULL)
#define DDR_HI_SIZE (0x0000000800000000ULL)
#define ADDR_HI(ADDR) ((u32)((u64)(ADDR) >> 32U))
#define ADDR_LO(ADDR) ((u32)((u64)(ADDR) & 0x00000000FFFFFFFFULL))
/* DDR states */
static const u8 pmDdrStates[PM_DDR_STATE_MAX] = {
[PM_DDR_STATE_OFF] = 0U,
[PM_DDR_STATE_SR] = PM_CAP_CONTEXT,
[PM_DDR_STATE_ON] = PM_CAP_ACCESS | PM_CAP_CONTEXT | PM_CAP_POWER |
PM_CAP_CLOCK,
};
/* DDR transition table (from which to which state DDR can transit) */
static const PmStateTran pmDdrTransitions[] = {
{
.fromState = PM_DDR_STATE_ON,
.toState = PM_DDR_STATE_SR,
.latency = PM_DEFAULT_LATENCY,
}, {
.fromState = PM_DDR_STATE_SR,
.toState = PM_DDR_STATE_ON,
.latency = PM_DEFAULT_LATENCY,
}, {
.fromState = PM_DDR_STATE_ON,
.toState = PM_DDR_STATE_OFF,
.latency = PM_DEFAULT_LATENCY,
}, {
.fromState = PM_DDR_STATE_OFF,
.toState = PM_DDR_STATE_ON,
.latency = PM_DEFAULT_LATENCY,
},
};
#ifdef XPAR_PSU_DDRC_0_DEVICE_ID
/* If it is required to enable drift */
static u8 drift_enable_req __attribute__((__section__(".srdata")));
static PmRegisterContext ctx_ddrc[] __attribute__((__section__(".srdata"))) = {
{ .addr = DDRC_MSTR, },
{ .addr = DDRC_MRCTRL0, },
{ .addr = DDRC_DERATEEN, },
{ .addr = DDRC_DERATEINT, },
{ .addr = DDRC_PWRCTL, },
{ .addr = DDRC_PWRTMG, },
{ .addr = DDRC_RFSHCTL0, },
{ .addr = DDRC_RFSHCTL1, },
{ .addr = DDRC_RFSHCTL3, },
{ .addr = DDRC_RFSHTMG, },
{ .addr = DDRC_ECCCFG0, },
{ .addr = DDRC_ECCCFG1, },
{ .addr = DDRC_CRCPARCTL1, },
{ .addr = DDRC_CRCPARCTL2, },
{ .addr = DDRC_INIT(0U), },
{ .addr = DDRC_INIT(1U), },
{ .addr = DDRC_INIT(2U), },
{ .addr = DDRC_INIT(3U), },
{ .addr = DDRC_INIT(4U), },
{ .addr = DDRC_INIT(5U), },
{ .addr = DDRC_INIT(6U), },
{ .addr = DDRC_INIT(7U), },
{ .addr = DDRC_DIMMCTL, },
{ .addr = DDRC_RANKCTL, },
{ .addr = DDRC_DRAMTMG(0U), },
{ .addr = DDRC_DRAMTMG(1U), },
{ .addr = DDRC_DRAMTMG(2U), },
{ .addr = DDRC_DRAMTMG(3U), },
{ .addr = DDRC_DRAMTMG(4U), },
{ .addr = DDRC_DRAMTMG(5U), },
{ .addr = DDRC_DRAMTMG(6U), },
{ .addr = DDRC_DRAMTMG(7U), },
{ .addr = DDRC_DRAMTMG(8U), },
{ .addr = DDRC_DRAMTMG(9U), },
{ .addr = DDRC_DRAMTMG(11U), },
{ .addr = DDRC_DRAMTMG(12U), },
{ .addr = DDRC_DRAMTMG(13U), },
{ .addr = DDRC_DRAMTMG(14U), },
{ .addr = DDRC_ZQCTL(0U), },
{ .addr = DDRC_ZQCTL(1U), },
{ .addr = DDRC_DFITMG0, },
{ .addr = DDRC_DFITMG1, },
{ .addr = DDRC_DFILPCFG(0U), },
{ .addr = DDRC_DFILPCFG(1U), },
{ .addr = DDRC_DFIUPD0, },
{ .addr = DDRC_DFIUPD1, },
{ .addr = DDRC_DFIMISC, },
{ .addr = DDRC_DFITMG2, },
{ .addr = DDRC_DBICTL, },
{ .addr = DDRC_ADDRMAP(0U), },
{ .addr = DDRC_ADDRMAP(1U), },
{ .addr = DDRC_ADDRMAP(2U), },
{ .addr = DDRC_ADDRMAP(3U), },
{ .addr = DDRC_ADDRMAP(4U), },
{ .addr = DDRC_ADDRMAP(5U), },
{ .addr = DDRC_ADDRMAP(6U), },
{ .addr = DDRC_ADDRMAP(7U), },
{ .addr = DDRC_ADDRMAP(8U), },
{ .addr = DDRC_ADDRMAP(9U), },
{ .addr = DDRC_ADDRMAP(10U), },
{ .addr = DDRC_ADDRMAP(11U), },
{ .addr = DDRC_ODTCFG, },
{ .addr = DDRC_ODTMAP, },
{ .addr = DDRC_SCHED, },
{ .addr = DDRC_PERFLPR1, },
{ .addr = DDRC_PERFWR1, },
{ .addr = DDRC_DQMAP5, },
{ .addr = DDRC_DBG0, },
{ .addr = DDRC_DBGCMD, },
{ .addr = DDRC_PCCFG, },
{ .addr = DDRC_PCFGR(0U), },
{ .addr = DDRC_PCFGW(0U), },
{ .addr = DDRC_PCTRL(0U), },
{ .addr = DDRC_PCFGQOS(0U, 0U), },
{ .addr = DDRC_PCFGQOS(1U, 0U), },
{ .addr = DDRC_PCFGR(1U), },
{ .addr = DDRC_PCFGW(1U), },
{ .addr = DDRC_PCTRL(1U), },
{ .addr = DDRC_PCFGQOS(0U, 1U), },
{ .addr = DDRC_PCFGQOS(1U, 1U), },
{ .addr = DDRC_PCFGR(2U), },
{ .addr = DDRC_PCFGW(2U), },
{ .addr = DDRC_PCTRL(2U), },
{ .addr = DDRC_PCFGQOS(0U, 2U), },
{ .addr = DDRC_PCFGQOS(1U, 2U), },
{ .addr = DDRC_PCFGR(3U), },
{ .addr = DDRC_PCFGW(3U), },
{ .addr = DDRC_PCTRL(3U), },
{ .addr = DDRC_PCFGQOS(0U, 3U), },
{ .addr = DDRC_PCFGQOS(1U, 3U), },
{ .addr = DDRC_PCFGWQOS(0U, 3U), },
{ .addr = DDRC_PCFGWQOS(1U, 3U), },
{ .addr = DDRC_PCFGR(4U), },
{ .addr = DDRC_PCFGW(4U), },
{ .addr = DDRC_PCTRL(4U), },
{ .addr = DDRC_PCFGQOS(0U, 4U), },
{ .addr = DDRC_PCFGQOS(1U, 4U), },
{ .addr = DDRC_PCFGWQOS(0U, 4U), },
{ .addr = DDRC_PCFGWQOS(1U, 4U), },
{ .addr = DDRC_PCFGR(5U), },
{ .addr = DDRC_PCFGW(5U), },
{ .addr = DDRC_PCTRL(5U), },
{ .addr = DDRC_PCFGQOS(0U, 5U), },
{ .addr = DDRC_PCFGQOS(1U, 5U), },
{ .addr = DDRC_PCFGWQOS(0U, 5U), },
{ .addr = DDRC_PCFGWQOS(1U, 5U), },
{ .addr = DDRC_SARBASE(0U), },
{ .addr = DDRC_SARSIZE(0U), },
{ .addr = DDRC_SARBASE(1U), },
{ .addr = DDRC_SARSIZE(1U), },
{ },
};
static PmRegisterContext ctx_ddrphy[] __attribute__((__section__(".srdata"))) = {
{ .addr = DDRPHY_PGCR(0U), },
{ .addr = DDRPHY_PGCR(2U), },
{ .addr = DDRPHY_PGCR(3U), },
{ .addr = DDRPHY_PGCR(5U), },
{ .addr = DDRPHY_PTR(0U), },
{ .addr = DDRPHY_PTR(1U), },
{ .addr = DDRPHY_PLLCR(0U), },
{ .addr = DDRPHY_DSGCR, },
{ .addr = DDRPHY_GPR(0U), },
{ .addr = DDRPHY_DCR, },
{ .addr = DDRPHY_DTPR(0U), },
{ .addr = DDRPHY_DTPR(1U), },
{ .addr = DDRPHY_DTPR(2U), },
{ .addr = DDRPHY_DTPR(3U), },
{ .addr = DDRPHY_DTPR(4U), },
{ .addr = DDRPHY_DTPR(5U), },
{ .addr = DDRPHY_DTPR(6U), },
{ .addr = DDRPHY_RDIMMGCR(0U), },
{ .addr = DDRPHY_RDIMMGCR(1U), },
{ .addr = DDRPHY_RDIMMCR(0U), },
{ .addr = DDRPHY_RDIMMCR(1U), },
{ .addr = DDRPHY_MR(0U), },
{ .addr = DDRPHY_MR(1U), },
{ .addr = DDRPHY_MR(2U), },
{ .addr = DDRPHY_MR(3U), },
{ .addr = DDRPHY_MR(4U), },
{ .addr = DDRPHY_MR(5U), },
{ .addr = DDRPHY_MR(6U), },
{ .addr = DDRPHY_MR(11U), },
{ .addr = DDRPHY_MR(12U), },
{ .addr = DDRPHY_MR(13U), },
{ .addr = DDRPHY_MR(14U), },
{ .addr = DDRPHY_MR(22U), },
{ .addr = DDRPHY_DTCR(0U), },
{ .addr = DDRPHY_DTCR(1U), },
{ .addr = DDRPHY_CATR(0U), },
{ .addr = DDRPHY_RIOCR(5U), },
{ .addr = DDRPHY_ACIOCR(0U), },
{ .addr = DDRPHY_ACIOCR(2U), },
{ .addr = DDRPHY_ACIOCR(3U), },
{ .addr = DDRPHY_ACIOCR(4U), },
{ .addr = DDRPHY_ACIOCR(5U), },
{ .addr = DDRPHY_IOVCR(0U), },
{ .addr = DDRPHY_VTCR(0U), },
{ .addr = DDRPHY_VTCR(1U), },
{ .addr = DDRPHY_DQSDR(0U), },
{ .addr = DDRPHY_DQSDR(1U), },
{ .addr = DDRPHY_ACBDLR(1U), },
{ .addr = DDRPHY_ACBDLR(2U), },
{ .addr = DDRPHY_ACBDLR(6U), },
{ .addr = DDRPHY_ACBDLR(7U), },
{ .addr = DDRPHY_ACBDLR(8U), },
{ .addr = DDRPHY_ACBDLR(9U), },
{ .addr = DDRPHY_ZQCR, },
{ .addr = DDRPHY_ZQPR(0U, 0U), },
{ .addr = DDRPHY_ZQPR(1U, 0U), },
{ .addr = DDRPHY_DXGCR(0U, 0U), },
{ .addr = DDRPHY_DXGCR(0U, 1U), },
{ .addr = DDRPHY_DXGCR(0U, 2U), },
{ .addr = DDRPHY_DXGCR(0U, 3U), },
{ .addr = DDRPHY_DXGCR(0U, 4U), },
{ .addr = DDRPHY_DXGCR(0U, 5U), },
{ .addr = DDRPHY_DXGCR(0U, 6U), },
{ .addr = DDRPHY_DXGCR(1U, 0U), },
{ .addr = DDRPHY_DXGCR(1U, 1U), },
{ .addr = DDRPHY_DXGCR(1U, 2U), },
{ .addr = DDRPHY_DXGCR(1U, 3U), },
{ .addr = DDRPHY_DXGCR(1U, 4U), },
{ .addr = DDRPHY_DXGCR(1U, 5U), },
{ .addr = DDRPHY_DXGCR(1U, 6U), },
{ .addr = DDRPHY_DXGCR(2U, 0U), },
{ .addr = DDRPHY_DXGCR(2U, 1U), },
{ .addr = DDRPHY_DXGCR(2U, 2U), },
{ .addr = DDRPHY_DXGCR(2U, 3U), },
{ .addr = DDRPHY_DXGCR(2U, 4U), },
{ .addr = DDRPHY_DXGCR(2U, 5U), },
{ .addr = DDRPHY_DXGCR(2U, 6U), },
{ .addr = DDRPHY_DXGCR(3U, 0U), },
{ .addr = DDRPHY_DXGCR(3U, 1U), },
{ .addr = DDRPHY_DXGCR(3U, 2U), },
{ .addr = DDRPHY_DXGCR(3U, 3U), },
{ .addr = DDRPHY_DXGCR(3U, 4U), },
{ .addr = DDRPHY_DXGCR(3U, 5U), },
{ .addr = DDRPHY_DXGCR(3U, 6U), },
{ .addr = DDRPHY_DXGCR(4U, 0U), },
{ .addr = DDRPHY_DXGCR(4U, 1U), },
{ .addr = DDRPHY_DXGCR(4U, 2U), },
{ .addr = DDRPHY_DXGCR(4U, 3U), },
{ .addr = DDRPHY_DXGCR(4U, 4U), },
{ .addr = DDRPHY_DXGCR(4U, 5U), },
{ .addr = DDRPHY_DXGCR(4U, 6U), },
{ .addr = DDRPHY_DXGCR(5U, 0U), },
{ .addr = DDRPHY_DXGCR(5U, 1U), },
{ .addr = DDRPHY_DXGCR(5U, 2U), },
{ .addr = DDRPHY_DXGCR(5U, 3U), },
{ .addr = DDRPHY_DXGCR(5U, 4U), },
{ .addr = DDRPHY_DXGCR(5U, 5U), },
{ .addr = DDRPHY_DXGCR(5U, 6U), },
{ .addr = DDRPHY_DXGCR(6U, 0U), },
{ .addr = DDRPHY_DXGCR(6U, 1U), },
{ .addr = DDRPHY_DXGCR(6U, 2U), },
{ .addr = DDRPHY_DXGCR(6U, 3U), },
{ .addr = DDRPHY_DXGCR(6U, 4U), },
{ .addr = DDRPHY_DXGCR(6U, 5U), },
{ .addr = DDRPHY_DXGCR(6U, 6U), },
{ .addr = DDRPHY_DXGCR(7U, 0U), },
{ .addr = DDRPHY_DXGCR(7U, 1U), },
{ .addr = DDRPHY_DXGCR(7U, 2U), },
{ .addr = DDRPHY_DXGCR(7U, 3U), },
{ .addr = DDRPHY_DXGCR(7U, 4U), },
{ .addr = DDRPHY_DXGCR(7U, 5U), },
{ .addr = DDRPHY_DXGCR(7U, 6U), },
{ .addr = DDRPHY_DXGCR(8U, 0U), },
{ .addr = DDRPHY_DXGCR(8U, 1U), },
{ .addr = DDRPHY_DXGCR(8U, 2U), },
{ .addr = DDRPHY_DXGCR(8U, 3U), },
{ .addr = DDRPHY_DXGCR(8U, 4U), },
{ .addr = DDRPHY_DXGCR(8U, 5U), },
{ .addr = DDRPHY_DXGCR(8U, 6U), },
{ .addr = DDRPHY_DX8SLNOSC(0U), },
{ .addr = DDRPHY_DX8SLPLLCR(0U, 0U), },
{ .addr = DDRPHY_DX8SLDQSCTL(0U), },
{ .addr = DDRPHY_DX8SLDXCTL2(0U), },
{ .addr = DDRPHY_DX8SLIOCR(0U), },
{ .addr = DDRPHY_DX8SLNOSC(1U), },
{ .addr = DDRPHY_DX8SLPLLCR(1U, 0U), },
{ .addr = DDRPHY_DX8SLDQSCTL(1U), },
{ .addr = DDRPHY_DX8SLDXCTL2(1U), },
{ .addr = DDRPHY_DX8SLIOCR(1U), },
{ .addr = DDRPHY_DX8SLNOSC(2U), },
{ .addr = DDRPHY_DX8SLPLLCR(2U, 0U), },
{ .addr = DDRPHY_DX8SLDQSCTL(2U), },
{ .addr = DDRPHY_DX8SLDXCTL2(2U), },
{ .addr = DDRPHY_DX8SLIOCR(2U), },
{ .addr = DDRPHY_DX8SLNOSC(3U), },
{ .addr = DDRPHY_DX8SLPLLCR(3U, 0U), },
{ .addr = DDRPHY_DX8SLDQSCTL(3U), },
{ .addr = DDRPHY_DX8SLDXCTL2(3U), },
{ .addr = DDRPHY_DX8SLIOCR(3U), },
{ .addr = DDRPHY_DX8SLNOSC(4U), },
{ .addr = DDRPHY_DX8SLPLLCR(4U, 0U), },
{ .addr = DDRPHY_DX8SLDQSCTL(4U), },
{ .addr = DDRPHY_DX8SLDXCTL2(4U), },
{ .addr = DDRPHY_DX8SLIOCR(4U), },
{ },
};
static PmRegisterContext ctx_ddrphy_odtcr[] __attribute__((__section__(".srdata"))) = {
{ .addr = DDRPHY_ODTCR, },
{ .addr = DDRPHY_ODTCR, },
};
static PmRegisterContext ctx_ddrphy_zqdata[] __attribute__((__section__(".srdata"))) = {
{ .addr = DDRPHY_ZQDR0(0U), },
{ .addr = DDRPHY_ZQDR1(0U), },
{ .addr = DDRPHY_ZQDR0(1U), },
{ .addr = DDRPHY_ZQDR1(1U), },
{ },
};
static void ddr_disable_wr_drift(void)
{
u32 r;
r = Xil_In32(DDRPHY_DTCR(0U));
r &= ~DDRPHY_DTCR0_INCWEYE;
Xil_Out32(DDRPHY_DTCR(0U), r);
r = Xil_In32(DDRPHY_DSGCR);
r &= ~DDRPHY_DSGCR_CTLZUEN;
Xil_Out32(DDRPHY_DSGCR, r);
r = Xil_In32(DDRPHY_DXGCR(0U, 3U));
r |= DDRPHY_DXGCR3_WDLVT;
Xil_Out32(DDRPHY_DXGCR(0U, 3U), r);
r = Xil_In32(DDRPHY_DXGCR(1U, 3U));
r |= DDRPHY_DXGCR3_WDLVT;
Xil_Out32(DDRPHY_DXGCR(1U, 3U), r);
r = Xil_In32(DDRPHY_DXGCR(2U, 3U));
r |= DDRPHY_DXGCR3_WDLVT;
Xil_Out32(DDRPHY_DXGCR(2U, 3U), r);
r = Xil_In32(DDRPHY_DXGCR(3U, 3U));
r |= DDRPHY_DXGCR3_WDLVT;
Xil_Out32(DDRPHY_DXGCR(3U, 3U), r);
r = Xil_In32(DDRPHY_DXGCR(8U, 3U));
r |= DDRPHY_DXGCR3_WDLVT;
Xil_Out32(DDRPHY_DXGCR(8U, 3U), r);
}
static void ddr_disable_rd_drift(void)
{
u32 r;
u32 i;
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTDTEN;
Xil_Out32(DDRPHY_DQSDR(0U), r);
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTDTMODE;
Xil_Out32(DDRPHY_DQSDR(0U), r);
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTUPMODE;
Xil_Out32(DDRPHY_DQSDR(0U), r);
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTGPULSE;
Xil_Out32(DDRPHY_DQSDR(0U), r);
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTRDSPC;
Xil_Out32(DDRPHY_DQSDR(0U), r);
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTDLY;
Xil_Out32(DDRPHY_DQSDR(0U), r);
for (i = 0U; i < 9U; i++) {
r = Xil_In32(DDRPHY_DXGCR(i, 3U));
r |= DDRPHY_DXGCR3_RGLVT;
Xil_Out32(DDRPHY_DXGCR(i, 3U), r);
}
r = Xil_In32(DDRPHY_DQSDR(1U));
r &= ~DDRPHY_DQSDR1_DFTRDIDLC;
r |= (1U << DDRPHY_DQSDR1_DFTRDIDLC_SHIFT);
Xil_Out32(DDRPHY_DQSDR(1U), r);
r = Xil_In32(DDRPHY_DQSDR(1U));
r &= ~DDRPHY_DQSDR1_DFTRDIDLF;
r |= (10U << DDRPHY_DQSDR1_DFTRDIDLF_SHIFT);
Xil_Out32(DDRPHY_DQSDR(1U), r);
}
static void ddr_enable_wr_drift(void)
{
u32 r;
r = Xil_In32(DDRPHY_DSGCR);
r |= DDRPHY_DSGCR_CTLZUEN;
Xil_Out32(DDRPHY_DSGCR, r);
r = Xil_In32(DDRPHY_DXGCR(0U, 3U));
r &= ~DDRPHY_DXGCR3_WDLVT;
Xil_Out32(DDRPHY_DXGCR(0U, 3U), r);
r = Xil_In32(DDRPHY_DXGCR(1U, 3U));
r &= ~DDRPHY_DXGCR3_WDLVT;
Xil_Out32(DDRPHY_DXGCR(1U, 3U), r);
r = Xil_In32(DDRPHY_DXGCR(2U, 3U));
r &= ~DDRPHY_DXGCR3_WDLVT;
Xil_Out32(DDRPHY_DXGCR(2U, 3U), r);
r = Xil_In32(DDRPHY_DXGCR(3U, 3U));
r &= ~DDRPHY_DXGCR3_WDLVT;
Xil_Out32(DDRPHY_DXGCR(3U, 3U), r);
r = Xil_In32(DDRPHY_DXGCR(8U, 3U));
r &= ~DDRPHY_DXGCR3_WDLVT;
Xil_Out32(DDRPHY_DXGCR(8U, 3U), r);
r = Xil_In32(DDRPHY_DTCR(0U));
r |= DDRPHY_DTCR0_INCWEYE;
Xil_Out32(DDRPHY_DTCR(0U), r);
}
static void ddr_enable_rd_drift(void)
{
u32 r;
u32 i;
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTDTMODE;
Xil_Out32(DDRPHY_DQSDR(0U), r);
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTUPMODE;
r |= (1U << DDRPHY_DQSDR0_DFTUPMODE_SHIFT);
Xil_Out32(DDRPHY_DQSDR(0U), r);
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTGPULSE;
Xil_Out32(DDRPHY_DQSDR(0U), r);
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTRDSPC;
r |= (1U << DDRPHY_DQSDR0_DFTRDSPC_SHIFT);
Xil_Out32(DDRPHY_DQSDR(0U), r);
r = Xil_In32(DDRPHY_DQSDR(0U));
r &= ~DDRPHY_DQSDR0_DFTDLY;
r |= (2U << DDRPHY_DQSDR0_DFTDLY_SHIFT);
Xil_Out32(DDRPHY_DQSDR(0U), r);
for (i = 0U; i < 9U; i++) {
r = Xil_In32(DDRPHY_DXGCR(i, 3U));
r &= ~DDRPHY_DXGCR3_RGLVT;
Xil_Out32(DDRPHY_DXGCR(i, 3U), r);
}
r = Xil_In32(DDRPHY_DQSDR(1U));
r &= ~DDRPHY_DQSDR1_DFTRDIDLC;
Xil_Out32(DDRPHY_DQSDR(1U), r);
r = Xil_In32(DDRPHY_DQSDR(1U));
r &= ~DDRPHY_DQSDR1_DFTRDIDLF;
Xil_Out32(DDRPHY_DQSDR(1U), r);
r = Xil_In32(DDRPHY_DQSDR(0U));
r |= DDRPHY_DQSDR0_DFTDTEN;
Xil_Out32(DDRPHY_DQSDR(0U), r);
}
static void ddr_enable_drift(void)
{
u32 readVal;
/* Enable drift only if it is previously enabled */
if (0U == drift_enable_req) {
return;
}
readVal = Xil_In32(DDRC_MSTR);
if (0U != (readVal & DDRC_MSTR_LPDDR3)) {
/* enable read drift only for LPDDR3 */
ddr_enable_rd_drift();
} else if (0U != (readVal & DDRC_MSTR_LPDDR4)) {
/* enable read and write drift for LPDDR4 */
ddr_enable_rd_drift();
ddr_enable_wr_drift();
}
drift_enable_req = 0U;
/* do not enable drift for DDR3/4, and LPDDR2 is not supported */
}
static bool ddrc_opmode_is(u32 m)
{
u32 r = Xil_In32(DDRC_STAT);
r &= DDRC_STAT_OPMODE_MASK;
r >>= DDRC_STAT_OPMODE_SHIFT;
return r == m;
}
static bool ddrc_opmode_is_sr(void)
{
return ddrc_opmode_is(DDRC_STAT_OPMODE_SR);
}
static s32 ddrc_enable_sr(void)
{
u32 r;
size_t i;
/* disable AXI ports */
for (i = 0U; i < 6U; i++) {
while ((Xil_In32(DDRC_PSTAT) & DDRC_PSTAT_PORT_BUSY(i)) != 0U) {
;
}
r = Xil_In32(DDRC_PCTRL(i));
r &= ~DDRC_PCTRL_PORT_EN;
Xil_Out32(DDRC_PCTRL(i), r);
}
/* enable self refresh */
r = Xil_In32(DDRC_PWRCTL);
r |= DDRC_PWRCTL_SR_SW;
Xil_Out32(DDRC_PWRCTL, r);
while (true != ddrc_opmode_is_sr()) {
;
}
while ((Xil_In32(DDRC_STAT) & (3U << 4U)) != (2U << 4U)) {
;
}
return XST_SUCCESS;
}
static void ddr_clock_enable(void)
{
u32 r = Xil_In32(DDRQOS_DDR_CLK_CTRL);
r |= DDRQOS_DDR_CLK_CTRL_CLKACT;
Xil_Out32(DDRQOS_DDR_CLK_CTRL, r);
}
static void store_state(PmRegisterContext *context)
{
while (context->addr != 0U) {
context->value = Xil_In32(context->addr);
if (context->addr == DDRC_RFSHCTL3) {
/* disable auto-refresh */
context->value |= DDRC_RFSHCTL3_AUTORF_DIS;
} else if (context->addr == DDRC_ZQCTL(0U)) {
/* disable auto-sq */
context->value |= DDRC_ZQCTL0_ZQ_DIS;
} else if (context->addr == DDRC_PWRCTL) {
/* self-refresh mode */
context->value = 0x00000020U;
} else if (context->addr == DDRC_INIT(0U)) {
/* skip DRAM init and start in self-refresh */
context->value |= 0xc0000000U;
} else if (context->addr == DDRC_DFIMISC) {
context->value &= ~1U;
} else if (context->addr == DDRPHY_PGCR(0U)) {
/* assert FIFO reset */
context->value &= ~DDRPHY_PGCR0_PHYFRST;
} else if (context->addr == DDRPHY_DX8SLNOSC(0U) ||
context->addr == DDRPHY_DX8SLNOSC(1U) ||
context->addr == DDRPHY_DX8SLNOSC(2U) ||
context->addr == DDRPHY_DX8SLNOSC(3U) ||
context->addr == DDRPHY_DX8SLNOSC(4U)) {
/* assert FIFO reset */
context->value &= ~DDRPHY_DX8SLBOSC_PHYFRST;
}
#ifdef DDRSR_DEBUG_STATE
ddr_print_dbg("%s: addr:%lx, value:%lx\r\n",
__func__, context->addr, context->value);
#endif
context++;
}
}
static void restore_state(PmRegisterContext *context)
{
while (context->addr != 0U) {
#ifdef DDRSR_DEBUG_STATE
ddr_print_dbg("%s: addr:0x%lx, value:0x%lx\r\n",
__func__, context->addr, context->value);
#endif
Xil_Out32(context->addr, context->value);
context++;
}
}
static void restore_ddrphy_zqdata(PmRegisterContext *context)
{
while (context->addr != 0U) {
#ifdef DDRSR_DEBUG_STATE
ddr_print_dbg("%s: addr:%lx, value:%lx\r\n",
__func__, context->addr + 8U, context->value);
#endif
/* write result data back to override register */
Xil_Out32(context->addr + DDRPHY_ZQnOR_OFFSET, context->value);
context++;
}
}
static void store_ddrphy_odtcr(PmRegisterContext *context)
{
u32 rank = Xil_In32(DDRC_MSTR) & DDRC_DUAL_RANK_MASK;
u32 readVal = Xil_In32(DDRC_MSTR) & DDRC_MSTR_DDR_TYPE;
if (DDRC_MSTR_LPDDR3 == readVal) {
if (DDRC_DUAL_RANK_MASK == rank) {
XPfw_RMW32(DDRPHY_RANKIDR, DDRPHY_RANKRID_MASK,
DDRPHY_RANK1_READ);
context->value = Xil_In32(context->addr);
}
context++;
XPfw_RMW32(DDRPHY_RANKIDR, DDRPHY_RANKRID_MASK,
DDRPHY_RANK0_READ);
context->value = Xil_In32(context->addr);
}
}
static void restore_ddrphy_odtcr(PmRegisterContext *context)
{
u32 rank = Xil_In32(DDRC_MSTR) & DDRC_DUAL_RANK_MASK;
u32 readVal = Xil_In32(DDRC_MSTR) & DDRC_MSTR_DDR_TYPE;
if (DDRC_MSTR_LPDDR3 == readVal) {
if (DDRC_DUAL_RANK_MASK == rank) {
XPfw_RMW32(DDRPHY_RANKIDR, DDRPHY_RANKWID_MASK,
DDRPHY_RANK1_WRITE);
Xil_Out32(context->addr, context->value);
}
context++;
XPfw_RMW32(DDRPHY_RANKIDR, DDRPHY_RANKWID_MASK,
DDRPHY_RANK0_WRITE);
Xil_Out32(context->addr, context->value);
}
}
static void ddr_io_retention_set(bool en)
{
u32 r = Xil_In32(PMU_GLOBAL_DDR_CNTRL);
if (0U != en) {
r |= PMU_GLOBAL_DDR_CNTRL_RET_MASK;
} else {
r &= ~PMU_GLOBAL_DDR_CNTRL_RET_MASK;
}
Xil_Out32(PMU_GLOBAL_DDR_CNTRL, r);
}
static void ddr_power_down_io(void)
{
u32 i;
/* prepare for SR, minimizing power consumption */
/* DSGCR.DTOPDR[14] = 1 */
XPfw_UtilRMW(DDRPHY_DSGCR, DDRPHY_DSGCR_DTOPDR, DDRPHY_DSGCR_DTOPDR);
/* DSGCR.DTOODT[12] = 0 */
XPfw_UtilRMW(DDRPHY_DSGCR, DDRPHY_DSGCR_DTOODT, ~DDRPHY_DSGCR_DTOODT);
/* RIOCR2.COEMODE[25:24] = 10 */
XPfw_UtilRMW(DDRPHY_RIOCR(2U), DDRPHY_RIOCR2_COEMODE_MASK,
0x2U << DDRPHY_RIOCR2_COEMODE_SHIFT);
/* RIOCR2.CSOEMODE[3:0] = 1010 */
XPfw_UtilRMW(DDRPHY_RIOCR(2U), DDRPHY_RIOCR2_CSOEMODE_MASK , 0xAU);
/* RIOCR5.ODTOEMODE[3:0] = 1010 */
XPfw_UtilRMW(DDRPHY_RIOCR(5U), DDRPHY_RIOCR5_ODTOEMODE_MASK, 0xAU);
/* ACIOCR0.RSTPDR[28] = 1 */
XPfw_UtilRMW(DDRPHY_ACIOCR(0U), DDRPHY_ACIOCR0_RSTPDR,
DDRPHY_ACIOCR0_RSTPDR);
/* ACIOCR0.RSTODT[26] = 0 */
XPfw_UtilRMW(DDRPHY_ACIOCR(0U), DDRPHY_ACIOCR0_RSTODT,
~DDRPHY_ACIOCR0_RSTODT);
/* ACIOCR0.ACPDRMODE[5:4] = 01 */
XPfw_UtilRMW(DDRPHY_ACIOCR(0U), DDRPHY_ACIOCR0_ACPDRMDOE_MASK,
0x1U << DDRPHY_ACIOCR0_ACPDRMDOE_SHIFT);
/* ACIOCR0.ACODTMODE[3:2] = 10 */
XPfw_UtilRMW(DDRPHY_ACIOCR(0U), DDRPHY_ACIOCR0_ACODTMODE_MASK,
0x2U << DDRPHY_ACIOCR0_ACODTMODE_SHIFT);
/* ACIOCR1.AOEMODE[31:0] = 0xAAAAAAAA */
XPfw_UtilRMW(DDRPHY_ACIOCR(1U), DDRPHY_ACIOCR1_AOEMODE_MASK,
0xAAAAAAAAU);
/* ACIOCR3.PAROEMODE[31:30] = 10 */
XPfw_UtilRMW(DDRPHY_ACIOCR(3U), DDRPHY_ACIOCR3_PAROEMODE_MASK,
0x2U << DDRPHY_ACIOCR3_PAROEMODE_SHIFT);
/* ACIOCR3.BGOEMODE[29:26] = 1010 */
XPfw_UtilRMW(DDRPHY_ACIOCR(3U), DDRPHY_ACIOCR3_BGOEMODE_MASK,
0xAU << DDRPHY_ACIOCR3_BGOEMODE_SHIFT);
/* ACIOCR3.BAOEMODE[25:22] = 1010 */
XPfw_UtilRMW(DDRPHY_ACIOCR(3U), DDRPHY_ACIOCR3_BAOEMODE_MASK,
0xAU << DDRPHY_ACIOCR3_BAOEMODE_SHITT);
/* ACIOCR3.A17OEMODE[21:20] = 10 */
XPfw_UtilRMW(DDRPHY_ACIOCR(3U), DDRPHY_ACIOCR3_A17OEMODE_MASK,
0x2U << DDRPHY_ACIOCR3_A17OEMODE_SHIFT);
/* ACIOCR3.A16OEMODE[19:18] = 10 */
XPfw_UtilRMW(DDRPHY_ACIOCR(3U), DDRPHY_ACIOCR3_A16OEMODE_MASK,
0x2U << DDRPHY_ACIOCR3_A16OEMODE_SHIFT);
/* ACIOCR3.ACTOEMODE[17:16] = 10 */
XPfw_UtilRMW(DDRPHY_ACIOCR(3U), DDRPHY_ACIOCR3_ACTOEMODE_MASK,
0x2U << DDRPHY_ACIOCR3_ACTOEMODE_SHIFT);
/* ACIOCR3.CKOEMODE[3:0] = 1010 */
XPfw_UtilRMW(DDRPHY_ACIOCR(3U), DDRPHY_ACIOCR3_CKOEMODE, 0xAU);
/* IOVCR0.ACREFSEN[25] = 0 */
/* IOVCR0.ACREFIEN[24] = 0 */
XPfw_UtilRMW(DDRPHY_IOVCR(0U), (DDRPHY_IOVCR0_ACREFSEN |
DDRPHY_IOVCR0_ACREFIEN),
~(DDRPHY_IOVCR0_ACREFSEN |
DDRPHY_IOVCR0_ACREFIEN));
/* ZQCR.ZQREFIEN[11] = 0 */
XPfw_UtilRMW(DDRPHY_ZQCR, DDRPHY_ZQCR_ZQREFIEN, ~DDRPHY_ZQCR_ZQREFIEN);
/* ZQCR.ZQPD[0] = 1 */
XPfw_UtilRMW(DDRPHY_ZQCR, DDRPHY_ZQCR_ZQPD, DDRPHY_ZQCR_ZQPD);
/* DX[8:0]GCR0.DQSNSEPDR[13] = 1 */
/* DX[8:0]GCR0.DQSSEPDR[12] = 1 */
/* DX[8:0]GCR0.DQSRPD[6] = 1 */
/* DX[8:0]GCR0.DQSGPDR[5] = 1 */
/* DX[8:0]GCR0.DQSGODT[3] = 0 */
/* DX[8:0]GCR0.DQSGOE[2] = 0 */
for (i = 0U; i < 9U; i++) {
XPfw_UtilRMW(DDRPHY_DXGCR(i, 0U), 0x306CU, 0x3060U);
}
/* DX[8:0]GCR1.DXPDRMODE[31:16] = 0x5555 */
for (i = 0U; i < 9U; i++) {
XPfw_UtilRMW(DDRPHY_DXGCR(i, 1U), 0xFFFF0000U, 0x5555U << 16U);
}
/* DX[8:0]GCR2.DXOEMODE[31:16] = 0xAAAA */
/* DX[8:0]GCR2.DXTEMODE[15:0] = 0xAAAA */
for (i = 0U; i < 9U; i++) {
XPfw_UtilRMW(DDRPHY_DXGCR(i, 2U), 0xFFFFFFFFU, 0xAAAAAAAAU);
}
/* DX[8:0]GCR3.DSNOEMODE[21:20] = 10 */
/* DX[8:0]GCR3.DSNTEMODE[19:18] = 10 */
/* DX[8:0]GCR3.DSNPDRMODE[17:16] = 01 */
/* DX[8:0]GCR3.DMOEMODE[15:14] = 10 */
/* DX[8:0]GCR3.DMTEMODE[13:12] = 10 */
/* DX[8:0]GCR3.DMPDRMODE[11:10] = 01 */
/* DX[8:0]GCR3.DSOEMODE[7:6] = 10 */
/* DX[8:0]GCR3.DSTEMODE[5:4] = 10 */
/* DX[8:0]GCR3.DSPDRMODE[3:2] = 01 */
for (i = 0U; i < 9U; i++) {
XPfw_UtilRMW(DDRPHY_DXGCR(i, 3U), 0x3FFCFCU, 0x29A4A4U);
}
/* DX[8:0]GCR4.DXREFSEN[25] = 0 */
/* DX[8:0]GCR4.DXREFIEN[5:2] = 0000 */
for (i = 0U; i < 9U; i++) {
XPfw_UtilRMW(DDRPHY_DXGCR(i, 4U), 0x200003CU, 0x0U);
}
}
static void DDR_reinit(bool ddrss_is_reset)
{
size_t i;
u32 readVal, busWidth;
XStatus status = XST_FAILURE;
if (true == ddrss_is_reset) {
/* Data Bus Width */
readVal = Xil_In32(DDRC_MSTR);
busWidth = (readVal & (DDRC_MSTR_BUS_WIDTH_MASK <<
DDRC_MSTR_BUS_WIDTH_SHIFT));
/* PHY init */
do {
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_ZCALBYP |
DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_PLLINIT);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_ZCALBYP |
DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_PLLINIT |
DDRPHY_PIR_INIT);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE |
DDRPHY_PGSR0_APLOCK,
PM_DDR_POLL_PERIOD);
if (XST_SUCCESS != status) {
continue;
}
status = XPfw_UtilPollForMask(DDRPHY_DXGSR0(0U),
DDRPHY_DXGSR0_DPLOCK,
PM_DDR_POLL_PERIOD);
if (XST_SUCCESS != status) {
continue;
}
if ((DDRC_MSTR_BUS_WIDTH_FULL_DQ == busWidth) ||
(DDRC_MSTR_BUS_WIDTH_HALF_DQ == busWidth)) {
status = XPfw_UtilPollForMask(DDRPHY_DXGSR0(2U),
DDRPHY_DXGSR0_DPLOCK,
PM_DDR_POLL_PERIOD);
if (XST_SUCCESS != status) {
continue;
}
}
if (DDRC_MSTR_BUS_WIDTH_FULL_DQ == busWidth) {
status = XPfw_UtilPollForMask(DDRPHY_DXGSR0(4U),
DDRPHY_DXGSR0_DPLOCK,
PM_DDR_POLL_PERIOD);
if (XST_SUCCESS != status) {
continue;
}
status = XPfw_UtilPollForMask(DDRPHY_DXGSR0(6U),
DDRPHY_DXGSR0_DPLOCK,
PM_DDR_POLL_PERIOD);
if (XST_SUCCESS != status) {
continue;
}
}
#if XPAR_PSU_DDRC_0_HAS_ECC
status = XPfw_UtilPollForMask(DDRPHY_DXGSR0(8U),
DDRPHY_DXGSR0_DPLOCK,
PM_DDR_POLL_PERIOD);
if (XST_SUCCESS != status) {
continue;
}
#endif
} while (XST_SUCCESS != status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_ZCALBYP |
DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_PHYRST |
DDRPHY_PIR_DCAL);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_ZCALBYP |
DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_PHYRST |
DDRPHY_PIR_DCAL |
DDRPHY_PIR_INIT);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
for (i = 0U; i < 2U; i++) {
readVal = Xil_In32(DDRPHY_ZQPR(i, 0U));
readVal |= (DDRPHY_ZQnPR0_ZSEGBYP |
DDRPHY_ZQnPR0_ZDEN_MASK);
Xil_Out32(DDRPHY_ZQPR(i, 0U), readVal);
}
restore_ddrphy_odtcr(ctx_ddrphy_odtcr);
restore_ddrphy_zqdata(ctx_ddrphy_zqdata);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_INIT);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
ddr_io_retention_set(false);
#ifdef ENABLE_POS
PmHookPowerOffSuspendDdrReady();
#endif
/* remove ZQ override */
for (i = 0U; i < 2U; i++) {
readVal = Xil_In32(DDRPHY_ZQPR(i, 0U));
readVal &= ~(DDRPHY_ZQnPR0_ZSEGBYP |
DDRPHY_ZQnPR0_ZDEN_MASK);
Xil_Out32(DDRPHY_ZQPR(i, 0U), readVal);
}
/* zcal */
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_ZCAL);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_ZCAL |
DDRPHY_PIR_INIT);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
ddr_enable_drift();
/* FIFO reset */
readVal = Xil_In32(DDRPHY_PGCR(0U));
readVal |= DDRPHY_PGCR0_PHYFRST;
Xil_Out32(DDRPHY_PGCR(0U), readVal);
for (i = 0U; i < 5U; i++) {
readVal = Xil_In32(DDRPHY_DX8SLNOSC(i));
readVal |= DDRPHY_DX8SLBOSC_PHYFRST;
Xil_Out32(DDRPHY_DX8SLNOSC(i), readVal);
}
Xil_Out32(DDRC_DFIMISC, DDRC_DFIMISC_DFI_INIT_COMP_EN);
Xil_Out32(DDRC_SWCTL, DDRC_SWCTL_SW_DONE);
} else {
ddr_enable_drift();
}
Xil_Out32(DDRC_PWRCTL, 0U);
do {
readVal = Xil_In32(DDRC_STAT);
readVal &= 3U << 4U;
} while (readVal != 0U);
do {
readVal = Xil_In32(DDRC_STAT);
readVal &= DDRC_STAT_OPMODE_MASK;
readVal >>= DDRC_STAT_OPMODE_SHIFT;
} while (readVal != DDRC_STAT_OPMODE_NORMAL);
if (true == ddrss_is_reset) {
readVal = Xil_In32(DDRC_MSTR) & DDRC_MSTR_DDR_TYPE;
if (readVal == DDRC_MSTR_LPDDR3 ) {
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_WREYE |
DDRPHY_PIR_RDEYE |
DDRPHY_PIR_WRDSKW |
DDRPHY_PIR_RDDSKW |
DDRPHY_PIR_WLADJ |
DDRPHY_PIR_QSGATE |
DDRPHY_PIR_WL |
DDRPHY_PIR_CA);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_WREYE |
DDRPHY_PIR_RDEYE |
DDRPHY_PIR_WRDSKW |
DDRPHY_PIR_RDDSKW |
DDRPHY_PIR_WLADJ |
DDRPHY_PIR_QSGATE |
DDRPHY_PIR_WL |
DDRPHY_PIR_CA |
DDRPHY_PIR_INIT);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
} else if (readVal == DDRC_MSTR_LPDDR4) {
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_QSGATE |
DDRPHY_PIR_WL);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_QSGATE |
DDRPHY_PIR_WL |
DDRPHY_PIR_INIT);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
readVal = Xil_In32(DDRPHY_DTCR(0U));
readVal &= ~(DDRPHY_DTCR0_RFSHEN_MASK |
DDRPHY_DTCR0_RFSHDT_MASK);
Xil_Out32(DDRPHY_DTCR(0U), readVal);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_DQS2DQ);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_DQS2DQ |
DDRPHY_PIR_INIT);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
readVal = Xil_In32(DDRPHY_DTCR(0U));
readVal &= ~(DDRPHY_DTCR0_RFSHEN_MASK |
DDRPHY_DTCR0_RFSHDT_MASK);
readVal |= ((0x8U << DDRPHY_DTCR0_RFSHDT_SHIFT) |
(0x1U << DDRPHY_DTCR0_RFSHEN_SHIFT));
Xil_Out32(DDRPHY_DTCR(0U), readVal);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_WREYE |
DDRPHY_PIR_RDEYE |
DDRPHY_PIR_WRDSKW |
DDRPHY_PIR_RDDSKW |
DDRPHY_PIR_WLADJ);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_WREYE |
DDRPHY_PIR_RDEYE |
DDRPHY_PIR_WRDSKW |
DDRPHY_PIR_RDDSKW |
DDRPHY_PIR_WLADJ |
DDRPHY_PIR_INIT);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
} else {
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_WREYE |
DDRPHY_PIR_RDEYE |
DDRPHY_PIR_WRDSKW |
DDRPHY_PIR_RDDSKW |
DDRPHY_PIR_WLADJ |
DDRPHY_PIR_QSGATE |
DDRPHY_PIR_WL);
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_CTLDINIT |
DDRPHY_PIR_WREYE |
DDRPHY_PIR_RDEYE |
DDRPHY_PIR_WRDSKW |
DDRPHY_PIR_RDDSKW |
DDRPHY_PIR_WLADJ |
DDRPHY_PIR_QSGATE |
DDRPHY_PIR_WL |
DDRPHY_PIR_INIT);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
}
readVal = DDRPHY_PIR_CTLDINIT;
if (0U != (Xil_In32(DDRPHY_RDIMMGCR(0U)) & DDRPHY_RDIMMGCR0_RDIMM)) {
readVal |= DDRPHY_PIR_RDIMMINIT;
}
Xil_Out32(DDRPHY_PIR, readVal);
Xil_Out32(DDRPHY_PIR, readVal | DDRPHY_PIR_INIT);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
readVal = Xil_In32(DDRC_RFSHCTL3);
readVal &= ~DDRC_RFSHCTL3_AUTORF_DIS;
Xil_Out32(DDRC_RFSHCTL3, readVal);
readVal = Xil_In32(DDRC_ZQCTL(0U));
readVal &= ~DDRC_ZQCTL0_ZQ_DIS;
Xil_Out32(DDRC_ZQCTL(0U), readVal);
} else {
Xil_Out32(DDRPHY_PIR, DDRPHY_PIR_WREYE |
DDRPHY_PIR_RDEYE |
DDRPHY_PIR_WRDSKW |
DDRPHY_PIR_RDDSKW);
status = XPfw_UtilPollForMask(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_IDONE,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
status = XPfw_UtilPollForZero(DDRPHY_PGSR(0U),
DDRPHY_PGSR0_TRAIN_ERRS,
PM_DDR_POLL_PERIOD);
REPORT_IF_ERROR(status);
/* enable AXI ports */
for (i = 0U; i < 6U; i++) {
while ((Xil_In32(DDRC_PSTAT) & DDRC_PSTAT_PORT_BUSY(i)) != 0U) {
;
}
readVal = Xil_In32(DDRC_PCTRL(i));
readVal |= DDRC_PCTRL_PORT_EN;
Xil_Out32(DDRC_PCTRL(i), readVal);
}
}
}
static inline u32 get_old_map_offset(void)
{
if (DDRC_MSTR_LPDDR4 ==
(Xil_In32(DDRC_MSTR) & DDRC_MSTR_DDR_TYPE)) {
return LPDDR4_OLD_MAP_OFFSET;
} else {
return OLD_MAP_OFFSET;
}
}
static bool ddr4_is_old_mapping(void)
{
u32 bg_b0, col_b4;
bool old_mapping = false;
bg_b0 = Xil_In32(DDRC_ADDRMAP(8U)) & DDRC_ADDRMAP8_ADDRMAP_BG_B0;
col_b4 = (Xil_In32(DDRC_ADDRMAP(2U)) & DDRC_ADDRMAP2_ADDRMAP_COL_B4) >>
DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT;
if (((bg_b0 + 2U) > (col_b4 + 4U)) ||
(DDRC_MSTR_DDR4 != (Xil_In32(DDRC_MSTR) &
DDRC_MSTR_DDR_TYPE))) {
old_mapping = true;
}
return old_mapping;
}
static void ddr_rank1_addr(u32 *haddr, u32 *laddr)
{
u32 reg;
reg = Xil_In32(DDRC_ADDRMAP(0U)) & DDRC_ADDRMAP0_ADDRMAP_CS_BIT0;
if (31U != reg) {
if (reg <= 21U) {
*haddr = 0U;
*laddr = (1U << (reg + 9U));
} else if (22U == reg) {
/* Upper 32 bits for address at 32 GB. */
*haddr = 0x00000008U;
/* Lower 32 bits for address at 32 GB. */
*laddr = 0x00000000U;
} else if (23U == reg) {
/* Upper 32 bits for address at 34 GB. */
*haddr = 0x00000008U;
/* Lower 32 bits for address at 34 GB. */
*laddr = 0x80000000U;
} else if (24U == reg) {
/* Upper 32 bits for address at 38 GB. */
*haddr = 0x00000009U;
/* Lower 32 bits for address at 38 GB. */
*laddr = 0x80000000U;
} else if (25U == reg) {
/* Upper 32 bits for address at 46 GB. */
*haddr = 0x0000000BU;
/* Lower 32 bits for address at 46 GB. */
*laddr = 0x80000000U;
} else {
/*
* We don't support these sizes, configuration is
* incorrect.
*/
*haddr = 0U;
*laddr = 0U;
}
} else {
*haddr = 0U;
*laddr = 0U;
}
}
static u32 ddr_training_size(void)
{
u32 reg, size;
reg = Xil_In32(DDRC_MSTR) & DDRC_MSTR_DDR_TYPE;
switch (reg) {
case DDRC_MSTR_LPDDR4:
size = LPDDR4_SIZE;
break;
case DDRC_MSTR_DDR4:
if (0U != ddr4_is_old_mapping()) {
size = DDR4_SIZE_OLD;
} else {
size = DDR4_SIZE;
}
break;
case DDRC_MSTR_LPDDR3:
size = LPDDR3_SIZE;
break;
case DDRC_MSTR_DDR3:
size = DDR3_SIZE;
break;
default:
size = 0U;
break;
}
return size;
}
static u64 hif_to_axi_addr(u64 hif_addr)
{
u64 axi_addr = 0xFFFFFFFFFFFFFFFFULL;
if (hif_addr < DDR_LO_SIZE) {
/* HIF address in low DDR address range */
axi_addr = hif_addr;
} else if (hif_addr < (DDR_LO_SIZE + DDR_HI_SIZE)) {
/* HIF address in high DDR address range */
axi_addr = hif_addr + (DDR_HI_ADDR - DDR_LO_SIZE);
}
return axi_addr;
}
static u64 mirrored_r1_addr(void)
{
u32 bg_b1_pos;
u64 r1_hif_addr;
u64 r1_axi_addr;
/* Read register field */
bg_b1_pos = Xil_In32(DDRC_ADDRMAP(8U));
bg_b1_pos &= DDRC_ADDRMAP8_BG_B1_MASK;
bg_b1_pos >>= DDRC_ADDRMAP8_BG_B1_SHIFT;
/* Add register base */
bg_b1_pos += DDRC_ADDRMAP8_BG_B1_BASE;
/* Add burst line size: 8 bytes, or 3 bit shifts */
bg_b1_pos += 3U;
r1_hif_addr = (1ULL << bg_b1_pos);
r1_axi_addr = hif_to_axi_addr(r1_hif_addr);
return r1_axi_addr;
}
static s32 store_training_data(void)
{
u32 size, old_map_offset;
bool old_mapping;
u32 haddr, laddr;
u64 mirr_offset;
s32 status;
ddr_rank1_addr(&haddr, &laddr);
size = ddr_training_size();
old_mapping = ddr4_is_old_mapping();
old_map_offset = get_old_map_offset();
status = PmDmaInit();
if (XST_SUCCESS != status) {
goto done;
}
PmSetCsuDmaLoopbackMode();
PmDma64BitTransfer(RESERVED_ADDRESS, 0U, 0U, 0U, size);
if (((0U != haddr) || (0U != laddr)) && old_mapping) {
PmDma64BitTransfer(RESERVED_ADDRESS + size, 0U,
old_map_offset, 0U, size);
PmDma64BitTransfer(RESERVED_ADDRESS + (2U * size), 0U, laddr,
haddr, size);
if (0U != IS_ADDR_MIRR()) {
mirr_offset = mirrored_r1_addr();
mirr_offset += (((u64)haddr) << 32U);
mirr_offset += (u64)laddr;
PmDma64BitTransfer(RESERVED_ADDRESS + (3U * size), 0U,
ADDR_LO(mirr_offset),
ADDR_HI(mirr_offset),
size);
} else {
PmDma64BitTransfer(RESERVED_ADDRESS + (3U * size), 0U,
laddr + old_map_offset, haddr,
size);
}
} else if (old_mapping) {
PmDma64BitTransfer(RESERVED_ADDRESS + size, 0U, old_map_offset,
0U, size);
} else {
PmDma64BitTransfer(RESERVED_ADDRESS + size, 0U, laddr,
haddr, size);
}
done:
return status;
}
static void restore_training_data(void)
{
u32 size, old_map_offset;
bool old_mapping;
u32 haddr, laddr;
u64 mirr_offset;
s32 status;
ddr_rank1_addr(&haddr, &laddr);
size = ddr_training_size();
old_mapping = ddr4_is_old_mapping();
old_map_offset = get_old_map_offset();
status = PmDmaInit();
if (XST_SUCCESS != status) {
#ifdef DDRSR_DEBUG_STATE
ddr_print_dbg("DMA initialization failed, error = %x\r\n",
status);
#endif
}
PmSetCsuDmaLoopbackMode();
PmDma64BitTransfer(0U, 0U, RESERVED_ADDRESS, 0U, size);
if (((0U != haddr) || (0U != laddr)) && old_mapping) {
PmDma64BitTransfer(old_map_offset, 0U,
RESERVED_ADDRESS + size, 0U, size);
PmDma64BitTransfer(laddr, haddr,
RESERVED_ADDRESS + (2U * size), 0U, size);
if (0U != IS_ADDR_MIRR()) {
mirr_offset = mirrored_r1_addr();
mirr_offset += (((u64)haddr) << 32U);
mirr_offset += (u64)laddr;
PmDma64BitTransfer(ADDR_LO(mirr_offset),
ADDR_HI(mirr_offset),
RESERVED_ADDRESS + (3U * size), 0U,
size);
} else {
PmDma64BitTransfer(laddr + old_map_offset, haddr,
RESERVED_ADDRESS + (3U * size), 0U,
size);
}
} else if (old_mapping) {
PmDma64BitTransfer(old_map_offset, 0U, RESERVED_ADDRESS + size,
0U, size);
} else {
PmDma64BitTransfer(laddr, haddr, RESERVED_ADDRESS + size, 0U,
size);
}
#ifdef ENABLE_DDR_SR_WR
/*
* Clear ECC error counts.
* If ECC is enabled, the act of restoring the corrupted memory locations
* will cause ECC errors. That is because the Xil_Out32() function first
* reads 8 bytes, then modifies the 4 bytes to be updated, before writing
* out all 8 bytes. Since the memory has already been corrupted by
* calibration, the initial read will cause ECC errors.
*/
if (0U != Xil_In32(DDRC_ERRCNT)) {
Xil_Out32(DDRC_ERRCLR, 0xfU);
}
#endif
}
static s32 pm_ddr_sr_enter(void)
{
s32 ret;
ret = store_training_data();
if (XST_SUCCESS != ret) {
goto err;
}
/* Identify if drift is enabled */
if ((Xil_In32(DDRPHY_DQSDR(0U)) & DDRPHY_DQSDR0_DFTDTEN) != 0U) {
drift_enable_req = 1U;
}
/* disable read and write drift */
ddr_disable_rd_drift();
ddr_disable_wr_drift();
store_state(ctx_ddrc);
store_state(ctx_ddrphy);
store_state(ctx_ddrphy_zqdata);
store_ddrphy_odtcr(ctx_ddrphy_odtcr);
ret = ddrc_enable_sr();
if (XST_SUCCESS != ret) {
goto err;
}
#ifdef ENABLE_DDR_SR_WR
/* Set self refresh mode indication flag */
XPfw_RMW32(XPFW_DDR_STATUS_REGISTER_OFFSET, DDR_STATUS_FLAG_MASK,
DDR_STATUS_FLAG_MASK);
/* Clear DDR controller initialization flag */
XPfw_RMW32(XPFW_DDR_STATUS_REGISTER_OFFSET, DDRC_INIT_FLAG_MASK,
~DDRC_INIT_FLAG_MASK);
#endif
err:
return ret;
}
static void pm_ddr_sr_exit(bool ddrss_is_reset)
{
if (true == ddrss_is_reset) {
u32 readVal;
/* re-enable clock only if FPD was off */
ddr_clock_enable();
Xil_Out32(DDRC_SWCTL, 0U);
restore_state(ctx_ddrc);
readVal = Xil_In32(CRF_APB_RST_DDR_SS);
readVal &= ~CRF_APB_RST_DDR_SS_DDR_RESET_MASK;
Xil_Out32(CRF_APB_RST_DDR_SS, readVal);
restore_state(ctx_ddrphy);
}
DDR_reinit(ddrss_is_reset);
restore_training_data();
}
#ifdef ENABLE_DDR_SR_WR
s32 PmDdrEnterSr(void)
{
s32 status = XST_FAILURE;
if (pmSlaveDdr_g.node.currState == PM_DDR_STATE_OFF) {
/* DDR is OFF, do not enter into self refresh mode */
goto err;
} else if (pmSlaveDdr_g.node.currState == PM_DDR_STATE_SR) {
/* DDR is already in self refresh mode */
status = XST_SUCCESS;
goto err;
}
XPfw_AibEnable(XPFW_AIB_LPD_TO_DDR);
status = pm_ddr_sr_enter();
if (XST_SUCCESS != status) {
goto err;
}
ddr_io_retention_set(true);
err:
return status;
}
s32 PmDdrExitSr(void)
{
s32 Status;
/* Wait until FSBL initialize DDR controller */
Status = XPfw_UtilPollForMask(XPFW_DDR_STATUS_REGISTER_OFFSET,
DDRC_INIT_FLAG_MASK,
DDR_FLAG_POLL_PERIOD);
if (XST_SUCCESS != Status) {
goto done;
}
/* Read DDRC & DDR PHY register values and modify some bitfields */
store_state(ctx_ddrc);
store_state(ctx_ddrphy);
XPfw_RMW32(CRF_APB_RST_DDR_SS, CRF_APB_RST_DDR_SS_DDR_RESET_MASK,
CRF_APB_RST_DDR_SS_DDR_RESET_MASK);
/* Write modified values to DDRC registers */
restore_state(ctx_ddrc);
XPfw_RMW32(CRF_APB_RST_DDR_SS, CRF_APB_RST_DDR_SS_DDR_RESET_MASK,
~CRF_APB_RST_DDR_SS_DDR_RESET_MASK);
/* Write modified values to DDR PHY registers */
restore_state(ctx_ddrphy);
DDR_reinit(true);
restore_training_data();
/* Indication to FSBL that DDR is out of self refresh mode */
XPfw_RMW32(XPFW_DDR_STATUS_REGISTER_OFFSET, DDR_STATUS_FLAG_MASK,
~DDR_STATUS_FLAG_MASK);
done:
return Status;
}
#endif
/**
* PmDdrFsmHandler() - DDR FSM handler, performs transition actions
* @slave Slave whose state should be changed (pointer to DDR object)
* @nextState State the slave should enter
*
* @return Status of performing transition action
*/
static s32 PmDdrFsmHandler(PmSlave* const slave, const PmStateId nextState)
{
s32 status = XST_SUCCESS;
/* Handle transition to OFF state here */
if ((PM_DDR_STATE_OFF != slave->node.currState) &&
(PM_DDR_STATE_OFF == nextState)) {
/* Here, user can put the DDR controller in reset */
XPfw_AibEnable(XPFW_AIB_LPD_TO_DDR);
goto done;
}
switch (slave->node.currState) {
case PM_DDR_STATE_ON:
if (PM_DDR_STATE_SR == nextState) {
XPfw_AibEnable(XPFW_AIB_LPD_TO_DDR);
status = pm_ddr_sr_enter();
} else {
status = XST_NO_FEATURE;
}
break;
case PM_DDR_STATE_SR:
if (PM_DDR_STATE_ON == nextState) {
bool ddrss_is_reset = !Xil_In32(DDRC_STAT);
pm_ddr_sr_exit(ddrss_is_reset);
XPfw_AibDisable(XPFW_AIB_LPD_TO_DDR);
} else {
status = XST_NO_FEATURE;
}
break;
case PM_DDR_STATE_OFF:
if (PM_DDR_STATE_ON == nextState) {
/*
* Bring DDR controller out of reset if it was in reset
* during DDR OFF state
* */
XPfw_AibDisable(XPFW_AIB_LPD_TO_DDR);
} else {
status = XST_NO_FEATURE;
}
break;
default:
status = XST_PM_INTERNAL;
PmNodeLogUnknownState(&slave->node, slave->node.currState);
break;
}
done:
return status;
}
#ifdef ENABLE_POS
/**
* PmDdrPowerOffSuspendResume() - Take DDR out of self refresh after resume from
* Power Off Suspend
*
* @return XST_SUCCESS if DDR is resumed, failure code otherwise
*/
s32 PmDdrPowerOffSuspendResume(void)
{
s32 status;
PmClockRestoreDdr();
status = PmDdrFsmHandler(&pmSlaveDdr_g, PM_DDR_STATE_ON);
if (XST_SUCCESS != status) {
goto done;
}
pmSlaveDdr_g.node.flags = NODE_LOCKED_CLOCK_FLAG |
NODE_LOCKED_POWER_FLAG;
done:
return status;
}
#endif
#endif
void ddr_io_prepare(void)
{
#ifdef XPAR_PSU_DDRC_0_DEVICE_ID
ddr_power_down_io();
ddr_io_retention_set(true);
#endif
}
/* DDR FSM */
static const PmSlaveFsm pmSlaveDdrFsm = {
.states = pmDdrStates,
.statesCnt = PM_DDR_STATE_MAX,
.trans = pmDdrTransitions,
.transCnt = ARRAY_SIZE(pmDdrTransitions),
#ifdef XPAR_PSU_DDRC_0_DEVICE_ID
.enterState = PmDdrFsmHandler,
#else
.enterState = NULL,
#endif
};
static u8 PmDdrPowerConsumptions[] = {
DEFAULT_DDR_POWER_OFF,
DEFAULT_DDR_POWER_SR,
DEFAULT_DDR_POWER_ON,
};
PmSlave pmSlaveDdr_g __attribute__((__section__(".srdata"))) = {
.node = {
.derived = &pmSlaveDdr_g,
.nodeId = NODE_DDR,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_DDR_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmDdrPowerConsumptions),
DEFINE_NODE_NAME("ddr"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmSlaveDdrFsm,
.flags = 0U,
};
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_api.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_API_H_
#define XPM_API_H_
#include "xil_types.h"
#include "xstatus.h"
#include "xpm_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MAX_BASEADDR_LEN 3
/* Global general storage register base address */
#define GGS_BASEADDR (0xF1110030U)
#define GGS_NUM_REGS (4U)
#define GGS_4_OFFSET (0x10U)
/* Persistent global general storage register base address */
#define PGGS_BASEADDR (0xF1110050U)
#define PGGS_NUM_REGS (4U)
/* Tap delay bypass */
#define TAPDLY_BYPASS_OFFSET (0x0000003CU)
#define XPM_TAP_DELAY_MASK (0x4U)
/* SD DLL control */
#define SD0_CTRL_OFFSET (0x00000404U)
#define SD1_CTRL_OFFSET (0x00000484U)
#define XPM_SD_DLL_RST_MASK (0x4U)
/* SD ITAPDLY */
#define ITAPDLY_OFFSET (0x0000F0F8U)
#define XPM_SD_ITAPCHGWIN_MASK (0x200U)
#define XPM_SD_ITAPDLYENA_MASK (0x100U)
#define XPM_SD_ITAPDLYSEL_MASK (0xFFU)
/* SD OTAPDLY */
#define OTAPDLY_OFFSET (0x0000F0FCU)
#define XPM_SD_OTAPDLYENA_MASK (0x40U)
#define XPM_SD_OTAPDLYSEL_MASK (0x3FU)
/* Probe Counter Register related macros */
#define PROBE_COUNTER_REQ_TYPE_SHIFT (16U)
#define PROBE_COUNTER_REQ_TYPE_MASK (0xFFU)
#define PROBE_COUNTER_TYPE_SHIFT (8U)
#define PROBE_COUNTER_TYPE_MASK (0xFFU)
#define PROBE_COUNTER_IDX_SHIFT (0U)
#define PROBE_COUNTER_IDX_MASK (0xFFU)
#define PROBE_COUNTER_CPU_R5_MAX_IDX (9U)
#define PROBE_COUNTER_LPD_MAX_IDX (5U)
#define PROBE_COUNTER_FPD_MAX_IDX (15U)
#define PROBE_COUNTER_CPU_R5_MAX_REQ_TYPE (3U)
#define PROBE_COUNTER_LPD_MAX_REQ_TYPE (7U)
#define PROBE_COUNTER_FPD_MAX_REQ_TYPE (3U)
/* Extern Variable and Function */
extern int XLoader_RestartImage(u32 SubsystemId);
XStatus XPm_Init(void (* const RequestCb)(u32 SubsystemId, const u32 EventId, u32 *Payload));
int XPm_GetChipID(u32* IDCode, u32 *Version);
XStatus XPm_GetApiVersion(u32 *Version);
XStatus XPm_AddSubsystem(u32 SubsystemId);
XStatus XPm_DestroySubsystem(u32 SubsystemId);
XStatus XPm_RequestWakeUp(u32 SubsystemId, const u32 DeviceId,
const u32 SetAddress,
const u64 Address,
const u32 Ack);
XStatus XPm_ForcePowerdown(u32 SubsystemId,
const u32 NodeId,
const u32 Ack);
XStatus XPm_SystemShutdown(u32 SubsystemId, const u32 Type,
const u32 SubType);
XStatus XPm_SetWakeUpSource(const u32 SubsystemId,
const u32 TargetNodeId,
const u32 SourceNodeId,
const u32 Enable);
XStatus XPm_RequestDevice(const u32 SubsystemId, const u32 DeviceId,
const u32 Capabilities, const u32 QoS, const u32 Ack);
XStatus XPm_ReleaseDevice(const u32 SubsystemId, const u32 DeviceId);
XStatus XPm_SetRequirement(const u32 SubsystemId, const u32 DeviceId,
const u32 Capabilities, const u32 QoS,
const u32 Ack);
int XPm_SetMaxLatency(const u32 SubsystemId, const u32 DeviceId,
const u32 Latency);
XStatus XPm_GetDeviceStatus(const u32 SubsystemId,
const u32 DeviceId,
XPm_DeviceStatus *const DeviceStatus);
XStatus XPm_Query(const u32 Qid, const u32 Arg1, const u32 Arg2,
const u32 Arg3, u32 *const Output);
XStatus XPm_SetClockState(const u32 SubsystemId, const u32 ClockId, const u32 Enable);
XStatus XPm_GetClockState(const u32 ClockId, u32 *const State);
XStatus XPm_SetClockDivider(const u32 SubsystemId, const u32 ClockId, const u32 Divider);
XStatus XPm_GetClockDivider(const u32 ClockId, u32 *const Divider);
XStatus XPm_SetClockParent(const u32 SubsystemId, const u32 ClockId, const u32 ParentIdx);
XStatus XPm_GetClockParent(const u32 ClockId, u32 *const ParentIdx);
XStatus XPm_SetPllParameter(const u32 SubsystemId, const u32 ClockId, const u32 ParamId, const u32 Value);
XStatus XPm_GetPllParameter(const u32 ClockId, const u32 ParamId, u32 *const Value);
XStatus XPm_SetPllMode(const u32 SubsystemId, const u32 ClockId, const u32 Value);
XStatus XPm_GetPllMode(const u32 ClockId, u32 *const Value);
XStatus XPm_SetResetState(const u32 SubsystemId, const u32 IpiMask,
const u32 ResetId, const u32 Action);
XStatus XPm_GetResetState(const u32 ResetId, u32 *const State);
XStatus XPm_SetPinFunction(const u32 SubsystemId, const u32 PinId, const u32 FunctionId);
XStatus XPm_GetPinFunction(const u32 PinId, u32 *const FunctionId);
XStatus XPm_SetPinParameter(const u32 SubsystemId, const u32 PinId,
const u32 ParamId,
const u32 ParamVal);
XStatus XPm_GetPinParameter(const u32 PinId,
const u32 ParamId,
u32 *const ParamVal);
XStatus XPm_PinCtrlRequest(const u32 SubsystemId, const u32 PinId);
XStatus XPm_PinCtrlRelease(const u32 SubsystemId, const u32 PinId);
XStatus XPm_DevIoctl(const u32 SubsystemId, const u32 DeviceId,
const u32 IoctlId,
const u32 Arg1,
const u32 Arg2,u32 *const Response);
int XPm_InitFinalize(const u32 SubsystemId);
XStatus XPm_DescribeNodes(u32 NumArgs);
XStatus XPm_AddNodeParent(u32 *Args, u32 NumArgs);
XStatus XPm_AddNodeName(u32 *Args, u32 NumArgs);
XStatus XPm_AddNode(u32 *Args, u32 NumArgs);
XStatus XPm_SelfSuspend(const u32 SubsystemId, const u32 DeviceId,
const u32 Latency, const u8 State,
u32 AddrLow, u32 AddrHigh);
XStatus XPm_AbortSuspend(const u32 SubsystemId, const u32 Reason,
const u32 DeviceId);
XStatus XPm_RequestSuspend(const u32 SubsystemId, const u32 TargetSubsystemId,
const u32 Ack, const u32 Latency, const u32 State);
XStatus XPm_AddRequirement(const u32 SubsystemId, const u32 DeviceId, u32 Flags, u32 *Params, u32 NumParams);
XStatus XPm_SetCurrentSubsystem(u32 SubsystemId);
XStatus XPm_InitNode(u32 NodeId, u32 Function, u32 *Args, u32 NumArgs);
int XPm_FeatureCheck(const u32 ApiId, u32 *const Version);
XStatus XPm_IsoControl(u32 NodeId, u32 Enable);
XStatus XPm_GetOpCharacteristic(const u32 DeviceId, const u32 Type,
u32 *Result);
int XPm_RegisterNotifier(const u32 SubsystemId, const u32 NodeId,
const u32 Event, const u32 Wake, const u32 Enable,
const u32 IpiMask);
int XPm_GicProxyWakeUp(const u32 PeriphIdx);
int XPm_DispatchWakeHandler(void *DeviceIdx);
XStatus XPm_HookAfterPlmCdo(void);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_API_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/versal/xsecure_error.h
/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_error.h
*
* This file contains xilsecure error codes
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -------------------------------------------------------
* 1.0 rpo 03/19/2020 Initial release
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XSECURE_ERROR_H_
#define XSECURE_ERROR_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* @addtogroup xilsecure_versal_error_codes List of Error Codes
* @{
*/
typedef enum {
XSECURE_SHA3_INIT_ERROR = 0x02U, /**< 0x02 - Error when SHA3
init fails. */
XSECURE_SHA3_LAST_UPDATE_ERROR, /**< 0x03 - Error when SHA3
last update fails. */
XSECURE_SHA3_PMC_DMA_UPDATE_ERROR, /**< 0x04 - Error when DMA driver
fails to update the data to SHA3 */
XSECURE_SHA3_TIMEOUT_ERROR, /**< 0x05 - Error when timeout */
XSECURE_SHA3_KAT_FAILED_ERROR, /**< 0x06 - Error when SHA3 hash
not matched with expected hash */
XSECURE_AES_GCM_TAG_MISMATCH = 0x40U,
/**< 0x40 - user provided GCM tag does
not match calculated tag */
XSECURE_AES_KEY_CLEAR_ERROR,
/**< 0x41 - AES key clear error */
XSECURE_AES_DPA_CM_NOT_SUPPORTED,
/**< 0x42 - AES DPA CM is not supported on device */
XSECURE_AES_KAT_WRITE_KEY_FAILED_ERROR, /**< 0x43 - Error when AES key write
fails. */
XSECURE_AES_KAT_DECRYPT_INIT_FAILED_ERROR, /**< 0x44 - Error when AES
decrypt init fails. */
XSECURE_AES_KAT_GCM_TAG_MISMATCH_ERROR, /**< 0x45 - Error when GCM tag
not matched with
user provided tag */
XSECURE_AES_KAT_DATA_MISMATCH_ERROR, /**< 0x46 - Error when AES data
not matched with
expected data */
XSECURE_AES_KAT_FAILED_ERROR, /**< 0x47 - AES KAT Failes */
XSECURE_AESDPACM_KAT_WRITE_KEY_FAILED_ERROR, /**< 0x48 - Error when AESDPACM
key write fails. */
XSECURE_AESDPACM_KAT_KEYLOAD_FAILED_ERROR, /**< 0x49 - Error when AESDPACM
key load fails. */
XSECURE_AESDPACM_SSS_CFG_FAILED_ERROR, /**< 0x4A - Eroor ehen AESDPACM
sss config fails */
XSECURE_AESDPACM_KAT_FAILED_ERROR, /**< 0x4B - AESDPACM KAT Failes*/
XSECURE_AESDPACM_KAT_CHECK1_FAILED_ERROR, /**< 0x4C - Error when AESDPACM
data not matched with
expected data */
XSECURE_AESDPACM_KAT_CHECK2_FAILED_ERROR, /**< 0x4D - Error when AESDPACM
data not matched with
expected data */
XSECURE_AESDPACM_KAT_CHECK3_FAILED_ERROR, /**< 0x4E - Error when AESDPACM
data not matched with
expected data */
XSECURE_AESDPACM_KAT_CHECK4_FAILED_ERROR, /**< 0x4F - Error when AESDPACM
data not matched with
expected data */
XSECURE_AESDPACM_KAT_CHECK5_FAILED_ERROR, /**< 0x50 - Error when AESDPACM
data not matched with
expected data */
XSECURE_RSA_KAT_ENCRYPT_FAILED_ERROR = 0x80U, /**< 0x80 - RSA KAT Failes */
XSECURE_RSA_KAT_ENCRYPT_DATA_MISMATCH_ERROR, /**< 0x81 - Error when RSA data
not matched with
expected data */
XSECURE_ECC_KAT_KEY_NOTVALID_ERROR = 0xC0U, /**< 0xC0 -ECC key is not valid */
XSECURE_ECC_KAT_FAILED_ERROR, /**< 0xC1 - ECC KAT Failes */
} XSecure_ErrorCodes;
/**
* @}
*/
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_ERROR_H_ */
<file_sep>/python_drivers/alice_num_sync_pulse_test.py
# -*- coding: utf-8 -*-
"""
Created on Tue Sep 22 17:00:47 2020
@author: tianlab01
"""
# -*- coding: utf-8 -*-
"""
Created on Fri Jul 24 11:14:53 2020
@author: tianlab01
"""
import time
import time_sync
import james_utils
import tdc_wrapper
import random
import datetime
import james_utils
logfile = "stream_test_results_9_23_num_sync_variation.txt"
def log_to_file(test_num, test_series_num, stream_len, succ, num_errors, num_no_photon, num_bad_range, num_neg_offset, sent_stream, received_stream, nsp):
file = open(logfile,'a')
new_line = str(test_num) + ", " + str(test_series_num) + ", " + str(stream_len) + ", success:, " + str(succ) + ", num errors:," + str(num_errors)
new_line += ", num_no_photon," + str(num_no_photon) + ", num_bad_range," + str(num_bad_range) + ", num_neg_offset," + str(num_neg_offset) + ", num_sync_pulse," + str(nsp)
#new_line += ", Sent:, "
#for s in sent_stream:
# new_line += str(s) + ", "
#new_line += "Received:, "
#for s in received_stream:
# new_line += str(s) + ", "
file.write(new_line + "\n")
file.close()
return
bob_ip = "192.168.56.1"
tdc_ip = "192.168.56.1"
tdc = tdc_wrapper.tdc_wrapper(3,0,tdc_wrapper.MODE_CLIENT,bob_ip)
ts = time_sync.time_sync(james_utils.ALICE_PORT, bob_ip, time_sync.CLIENT, tdc)
#log file format is num, val sent, val received, error (1 if yes), successfully deccoded (1 if yess)
count = 0
#is working and tested
#bin_size = 16000 #in ps
#bin_number = 4#can encode values between 0 and 15
#period = 64000 #in ps
#Working with 16 bins#
#bin_size = 8000 #in ps
#bin_number = 16#can encode values between 0 and 15
#period = 140000 #in ps
#Faster with 32 bins, working
bin_size = 8000 #in ps
bin_number = 16#can encode values between 0 and 15
period = 280000 #in ps
#num_sync_pulse = 200
num_dead_pulse = 100
pulse_len = 16
pulse_amp = 0x7FFF
file = open(logfile,'a')
file.write(datetime.datetime.now().strftime("\n================\n%I:%M%p on %B %d, %Y\n"))
file.write("bin_size = " + str(bin_size) + ", bin_number = " + str(bin_number) + ", period = " + str(period) +"\n")
file.write("test num, test num for this # of photons, number of photons\n")
file.close()
stream_len = 10000
res = 0
res += ts.set_bin_size(bin_size)
res += ts.set_bin_number(bin_number)
res += ts.set_period(period)
exit_test = 0
if(res):
print("Failed to set encoding parameters, aborting..")
else:
#2600
#16300
for num_sync_pulse in range(100, 2000, 100):
if(exit_test):
break
for test_num in range(0, 200):
if(exit_test):
break
try:
print("================================================================")
print("Test num: " + str(count) + ", series num: " + str(test_num) + ", num values: " + str(stream_len))
test_stream = []
for i in range(0, stream_len):
test_stream.append(random.randint(0,bin_number - 1))
#test_stream.append(i%16)
sent_str = "Sending: "
for i in test_stream:
sent_str += str(i) + ", "
#print(sent_str)
res = ts.send_stream(test_stream, num_sync_pulse, num_dead_pulse, pulse_len, pulse_amp)
if(res == -1):
print("Stream transmission failed, exiting")
print(sent_str)
exit_test = 1
break
else:
print("Stream transmission success")
sent_str = "Sent: "
for i in test_stream:
sent_str += str(i) + ", "
res_str = "Got: "
for i in res:
if(i < 100):
res_str += str(i) + ", "
else:
res_str += ".,"
print(sent_str)
print(res_str)
errs = len(test_stream) - james_utils.check_results(test_stream, res)
print("Errors: " + str(errs))
log_to_file(count, test_num, stream_len, 0, errs, 0, 0, 0, [], [], num_sync_pulse)
count += 1
print("Waiting 3 seconds...")
time.sleep(3)
#exit_test = 1
except KeyboardInterrupt:
print("Exiting")
exit_test = 1
break
ts.board.close_board()
print("Done testing") <file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/zynqmp/xsecure_rsa_core.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_rsa_core.c
*
* This file contains the implementation of the ZynqMP specific RSA driver.
* Refer to the header file xsecure_rsa_core.h for more detailed information.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.0 vns 03/12/19 Initial Release.
* arc 03/20/19 modified default status value to XST_FAILURE
* for XSecure_RsaSignVerification()
* mmd 03/15/19 Refactored the code
* psl 03/26/19 Fixed MISRA-C violation
* 4.1 psl 08/05/19 Fixed MISRA-C violation
* 4.2 kpt 01/07/20 Resolved CR-1049134 and Added Macros for all
* the Magic Numbers
* kpt 03/24/20 Added XSecure_RsaZeroizeVerify for
* RSA Zeroize Verification
*
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsecure_rsa_core.h"
#include "xsecure_rsa_hw.h"
#include "xplatform_info.h"
/************************** Constant Definitions *****************************/
/* PKCS padding for SHA-3 in 1.0 Silicon */
static const u8 XSecure_Silicon1_TPadSha3[] = {0x30U, 0x41U, 0x30U, 0x0DU,
0x06U, 0x09U, 0x60U, 0x86U, 0x48U, 0x01U, 0x65U, 0x03U, 0x04U,
0x02U, 0x02U, 0x05U, 0x00U, 0x04U, 0x30U };
/* PKCS padding for SHA-3 in 2.0 Silicon and onwards */
static const u8 XSecure_Silicon2_TPadSha3[] = {0x30U, 0x41U, 0x30U, 0x0DU,
0x06U, 0x09U, 0x60U, 0x86U, 0x48U, 0x01U, 0x65U, 0x03U, 0x04U,
0x02U, 0x09U, 0x05U, 0x00U, 0x04U, 0x30U };
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static void XSecure_RsaPutData(XSecure_Rsa *InstancePtr);
static void XSecure_RsaGetData(XSecure_Rsa *InstancePtr, u32 *RdData);
static u32 XSecure_RsaZeroize(XSecure_Rsa *InstancePtr);
static u32 XSecure_RsaZeroizeVerify(XSecure_Rsa *InstancePtr);
static void XSecure_RsaWriteMem(XSecure_Rsa *InstancePtr, u32* WrData,
u8 RamOffset);
static void XSecure_RsaMod32Inverse(XSecure_Rsa *InstancePtr);
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* @brief
* This function stores the base address of RSA core registers.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
*
* @return XST_SUCCESS on success.
*
******************************************************************************/
u32 XSecure_RsaCfgInitialize(XSecure_Rsa *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
InstancePtr->BaseAddress = XSECURE_CSU_RSA_BASE;
Status = (u32)XST_SUCCESS;
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function handles the all RSA operations with provided inputs.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
* @param Input Pointer to the buffer which contains the input
* data to be decrypted.
* @param Result Pointer to the buffer where resultant decrypted
* data to be stored .
*
* @return XST_SUCCESS on success.
*
******************************************************************************/
u32 XSecure_RsaOperation(XSecure_Rsa *InstancePtr, u8 *Input,
u8 *Result, u8 EncDecFlag, u32 Size)
{
u32 Status = (u32)XST_FAILURE;
u32 ErrorCode = XST_FAILURE;
u32 RsaType = XSECURE_CSU_RSA_CONTROL_4096;
u32 TimeOut = 0U;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Input != NULL);
Xil_AssertNonvoid(Result != NULL);
Xil_AssertNonvoid((EncDecFlag == XSECURE_RSA_SIGN_ENC) ||
(EncDecFlag == XSECURE_RSA_SIGN_DEC));
Xil_AssertNonvoid((Size == XSECURE_RSA_512_KEY_SIZE) ||
(Size == XSECURE_RSA_576_KEY_SIZE) ||
(Size == XSECURE_RSA_704_KEY_SIZE) ||
(Size == XSECURE_RSA_768_KEY_SIZE) ||
(Size == XSECURE_RSA_992_KEY_SIZE) ||
(Size == XSECURE_RSA_1024_KEY_SIZE) ||
(Size == XSECURE_RSA_1152_KEY_SIZE) ||
(Size == XSECURE_RSA_1408_KEY_SIZE) ||
(Size == XSECURE_RSA_1536_KEY_SIZE) ||
(Size == XSECURE_RSA_1984_KEY_SIZE) ||
(Size == XSECURE_RSA_2048_KEY_SIZE) ||
(Size == XSECURE_RSA_3072_KEY_SIZE) ||
(Size == XSECURE_RSA_4096_KEY_SIZE));
InstancePtr->EncDec = EncDecFlag;
InstancePtr->SizeInWords = Size/XSECURE_WORD_SIZE;
/* Put Modulus, exponent, Mod extension in RSA RAM */
XSecure_RsaPutData(InstancePtr);
/* Initialize Digest */
XSecure_RsaWriteMem(InstancePtr, (u32 *)Input,
XSECURE_CSU_RSA_RAM_DIGEST);
/* Initialize MINV values from Mod. */
XSecure_RsaMod32Inverse(InstancePtr);
switch(InstancePtr->SizeInWords) {
case XSECURE_RSA_512_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_512;
break;
case XSECURE_RSA_576_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_576;
break;
case XSECURE_RSA_704_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_704;
break;
case XSECURE_RSA_768_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_768;
break;
case XSECURE_RSA_992_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_992;
break;
case XSECURE_RSA_1024_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_1024;
break;
case XSECURE_RSA_1152_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_1152;
break;
case XSECURE_RSA_1408_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_1408;
break;
case XSECURE_RSA_1536_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_1536;
break;
case XSECURE_RSA_1984_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_1984;
break;
case XSECURE_RSA_2048_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_2048;
break;
case XSECURE_RSA_3072_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_3072;
break;
case XSECURE_RSA_4096_SIZE_WORDS:
RsaType = XSECURE_CSU_RSA_CONTROL_4096;
break;
default:
ErrorCode = (u32)XST_INVALID_PARAM;
break;
}
if(ErrorCode == XST_INVALID_PARAM) {
goto END;
}
/* Start the RSA operation. */
if (InstancePtr->ModExt != NULL) {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_RSA_CONTROL_OFFSET,
RsaType + XSECURE_CSU_RSA_CONTROL_EXP_PRE);
}
else {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_RSA_CONTROL_OFFSET,
RsaType + XSECURE_CSU_RSA_CONTROL_EXP);
}
/* Check and wait for status */
do {
Status = XSecure_ReadReg(InstancePtr->BaseAddress,
XSECURE_CSU_RSA_STATUS_OFFSET);
if(XSECURE_CSU_RSA_STATUS_ERROR ==
((u32)Status & XSECURE_CSU_RSA_STATUS_ERROR))
{
ErrorCode = (u32)XST_FAILURE;
goto END;
}
if(XSECURE_CSU_RSA_STATUS_DONE ==
((u32)Status & XSECURE_CSU_RSA_STATUS_DONE)){
ErrorCode = (u32)XST_SUCCESS;
break;
}
TimeOut = TimeOut + 1U;
} while(TimeOut < XSECURE_TIMEOUT_MAX);
if(TimeOut == XSECURE_TIMEOUT_MAX) {
ErrorCode = (u32)XST_FAILURE;
goto END;
}
/* Copy the result */
XSecure_RsaGetData(InstancePtr, (u32 *)Result);
END:
/* Zeroize and Verify RSA memory space */
if (InstancePtr->EncDec == XSECURE_RSA_SIGN_DEC) {
Status = XSecure_RsaZeroize(InstancePtr);
ErrorCode |= Status;
}
return ErrorCode;
}
/*****************************************************************************/
/**
* @brief
* This function writes all the RSA data used for decryption (Modulus, Exponent)
* at the corresponding offsets in RSA RAM.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
*
* @return None.
*
*
******************************************************************************/
static void XSecure_RsaPutData(XSecure_Rsa *InstancePtr)
{
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
/* Initialize Modular exponentiation */
XSecure_RsaWriteMem(InstancePtr, (u32 *)InstancePtr->ModExpo,
XSECURE_CSU_RSA_RAM_EXPO);
/* Initialize Modular. */
XSecure_RsaWriteMem(InstancePtr, (u32 *)InstancePtr->Mod,
XSECURE_CSU_RSA_RAM_MOD);
if (InstancePtr->ModExt != NULL) {
/* Initialize Modular extension (R*R Mod M) */
XSecure_RsaWriteMem(InstancePtr, (u32 *)InstancePtr->ModExt,
XSECURE_CSU_RSA_RAM_RES_Y);
}
}
/*****************************************************************************/
/**
* @brief
* This function reads back the resulting data from RSA RAM.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
* @param RdData Pointer to location where the decrypted data
* will be written
*
* @return None
*
*
******************************************************************************/
static void XSecure_RsaGetData(XSecure_Rsa *InstancePtr, u32 *RdData)
{
u32 Index;
u32 DataOffset;
s32 TmpIndex;
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
/** Total bits to be read 4096
* Each iteration of this loop reads 32 * 6 = 192 bits
* Therefore, for 4096, total iterations required = 4096/192 = 21.33 = 22
*/
TmpIndex = InstancePtr->SizeInWords - 1;
for (DataOffset = 0U; DataOffset < XSECURE_RSA_MAX_RD_WR_CNT; DataOffset++)
{
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_RSA_RD_ADDR_OFFSET,
(XSECURE_CSU_RSA_RAM_RES_Y * XSECURE_RSA_MAX_RD_WR_CNT)
+ DataOffset);
Index = (DataOffset == 0U) ? 2U: 0U;
for (; Index < XSECURE_RSA_MAX_BUFF; Index++)
{
if(TmpIndex < 0)
{
goto END;
}
/*
* The Signature digest is compared in Big endian.
* So because RSA h/w results in Little endian,
* reverse it after reading it from RSA memory,
*/
RdData[TmpIndex] = Xil_Htonl(XSecure_ReadReg(
InstancePtr->BaseAddress,
(XSECURE_CSU_RSA_RD_DATA_0_OFFSET+
(Index * XSECURE_WORD_SIZE))));
TmpIndex--;
}
}
END: ;
}
/*****************************************************************************/
/**
* @brief
* This function calculates the MINV value and put it into RSA core registers.
*
* @param InstancePtr Pointer to XSeure_Rsa instance
*
* @return None
*
* @note MINV is the 32-bit value of `-M mod 2**32`,
* where M is LSB 32 bits of the original modulus.
*
******************************************************************************/
static void XSecure_RsaMod32Inverse(XSecure_Rsa *InstancePtr)
{
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
/* Calculate the MINV */
u8 Count;
u32 *ModPtr = (u32 *)(InstancePtr->Mod);
u32 ModVal = Xil_Htonl(ModPtr[InstancePtr->SizeInWords - 1]);
u32 Inv = (u32)2U - ModVal;
for (Count = 0U; Count < XSECURE_WORD_SIZE; ++Count)
{
Inv = (Inv * (2U - ( ModVal * Inv ) ) );
}
Inv = ~Inv + 1U;
/* Put the value in MINV registers */
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_CSU_RSA_MINV0_OFFSET,
(Inv & XSECURE_RSA_BYTE_MASK ));
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_CSU_RSA_MINV1_OFFSET,
((Inv >> XSECURE_RSA_BYTE_SHIFT)
& XSECURE_RSA_BYTE_MASK ));
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_CSU_RSA_MINV2_OFFSET,
((Inv >> XSECURE_RSA_HWORD_SHIFT)
& XSECURE_RSA_BYTE_MASK ));
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_CSU_RSA_MINV3_OFFSET,
((Inv >> XSECURE_RSA_SWORD_SHIFT)
& XSECURE_RSA_BYTE_MASK ));
}
/*****************************************************************************/
/**
* @brief
* This function writes data to RSA RAM at a given offset.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param WrData Pointer to the data to be written to RSA RAM
* @param RamOffset Offset for the data to be written in RSA RAM
*
* @return None
*
*
******************************************************************************/
static void XSecure_RsaWriteMem(XSecure_Rsa *InstancePtr, u32* WrData,
u8 RamOffset)
{
u32 Index;
u32 DataOffset;
u32 TmpIndex;
u32 Data;
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(WrData != NULL);
/** Total bits to be written 4096 (RSA Key size)
* Each iteration of this loop writes 32 * 6 = 192 bits
* Therefore, for 4096, total iteration required = 4096/192 = 21.33 = 22
*/
for (DataOffset = 0U; DataOffset < XSECURE_RSA_MAX_RD_WR_CNT; DataOffset++)
{
for (Index = 0U; Index < XSECURE_RSA_MAX_BUFF; Index++)
{
TmpIndex = (DataOffset * XSECURE_RSA_MAX_BUFF) + Index;
/**
* Exponent size is only 4 bytes
* and rest of the data needs to be 0
*/
Data = 0U;
if((XSECURE_CSU_RSA_RAM_EXPO == RamOffset) &&
(InstancePtr->EncDec == XSECURE_RSA_SIGN_ENC))
{
if(0U == TmpIndex)
{
Data = Xil_Htonl(*WrData);
}
}
else
{
if(TmpIndex < InstancePtr->SizeInWords)
{
/**
* The RSA data in Image is in Big Endian.
* So reverse it before putting in RSA memory,
* because RSA h/w expects it in Little endian.
*/
Data = Xil_Htonl(
WrData[(InstancePtr->SizeInWords - 1) - TmpIndex]);
}
}
XSecure_WriteReg(InstancePtr->BaseAddress,
(XSECURE_CSU_RSA_WR_DATA_0_OFFSET + (Index * XSECURE_WORD_SIZE)),
Data);
}
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_RSA_WR_ADDR_OFFSET,
((RamOffset * XSECURE_RSA_MAX_RD_WR_CNT) + DataOffset));
}
}
/*****************************************************************************/
/**
* @brief
* This function clears whole RSA memory space. This function clears stored
* exponent, modulus and exponentiation key components along with digest.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
*
* @return XST_SUCCESS On Zeroization Success
* XSECURE_RSA_ZEROIZE_ERROR On Zeroization Failure.
*
*****************************************************************************/
static u32 XSecure_RsaZeroize(XSecure_Rsa *InstancePtr)
{
u32 RamOffset = (u32)XSECURE_CSU_RSA_RAM_EXPO;
u32 DataOffset;
u32 Index;
u32 Status = (u32)XST_FAILURE;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->RsaState == XSECURE_RSA_INITIALIZED);
/**
* Each iteration of this loop writes Zero
* in to one of the six RSA Write Buffers
*/
for (Index = 0; Index < XSECURE_RSA_MAX_BUFF; Index++) {
XSecure_WriteReg(InstancePtr->BaseAddress,
(XSECURE_CSU_RSA_WR_DATA_0_OFFSET + (Index * XSECURE_WORD_SIZE)),
0U);
}
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_RSA_ZERO_OFFSET, XSECURE_RSA_CTRL_CLR_DATA_BUF_MASK);
do {
for (DataOffset = 0U; DataOffset < XSECURE_RSA_MAX_RD_WR_CNT;
DataOffset++) {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_RSA_WR_ADDR_OFFSET,
((RamOffset * XSECURE_RSA_MAX_RD_WR_CNT) + DataOffset));
}
RamOffset++;
} while (RamOffset <= XSECURE_CSU_RSA_RAM_RES_Q);
Status = XSecure_RsaZeroizeVerify(InstancePtr);
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_CSU_RSA_MINV0_OFFSET,
0U);
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_CSU_RSA_MINV1_OFFSET,
0U);
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_CSU_RSA_MINV2_OFFSET,
0U);
XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_CSU_RSA_MINV3_OFFSET,
0U);
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function verifies the Zeroization of RSA memory space.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
*
* @return XST_SUCCESS On Success
* XSECURE_RSA_ZEROIZE_ERROR On Zeroize Verify Failure
*
*****************************************************************************/
static u32 XSecure_RsaZeroizeVerify(XSecure_Rsa *InstancePtr)
{
u32 RamOffset = (u32)XSECURE_CSU_RSA_RAM_EXPO;
u32 DataOffset;
u32 Index;
u32 Data = 0U;
u32 Status = (u32)XST_FAILURE;
Xil_AssertNonvoid(InstancePtr != NULL);
do {
for (DataOffset = 0U; DataOffset < XSECURE_RSA_MAX_RD_WR_CNT;
DataOffset++) {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_RSA_RD_ADDR_OFFSET,
((RamOffset * (u8)XSECURE_RSA_MAX_RD_WR_CNT) +
DataOffset));
for (Index = 0U; Index < XSECURE_RSA_MAX_BUFF; Index++) {
Data |= XSecure_ReadReg(InstancePtr->BaseAddress,
(XSECURE_CSU_RSA_RD_DATA_0_OFFSET +
(Index * XSECURE_WORD_SIZE)));
}
if (Data != 0U) {
Status = (u32)XSECURE_RSA_ZEROIZE_ERROR;
goto END;
}
}
RamOffset++;
} while (RamOffset <= XSECURE_CSU_RSA_RAM_RES_Q);
if (((RamOffset - 1U) == XSECURE_CSU_RSA_RAM_RES_Q) &&
(DataOffset == XSECURE_RSA_MAX_RD_WR_CNT)) {
Status = (u32)XST_SUCCESS;
}
END:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function returns PKCS padding as per the silicon version
*
* @param None
*
* @return XSecure_Silicon2_TPadSha3 if Silicon version is not 1.0
* XSecure_Silicon1_TPadSha3 if Silicon version is 1.0
*
*****************************************************************************/
u8* XSecure_RsaGetTPadding()
{
u8* Tpadding = (u8 *)XNULL ;
/* If Silicon version is not 1.0 then use the latest NIST approved SHA-3
* id for padding
*/
if(XGetPSVersion_Info() != (u32)XPS_VERSION_1) {
Tpadding = (u8*)XSecure_Silicon2_TPadSha3;
}
else {
Tpadding = (u8*)XSecure_Silicon1_TPadSha3;
}
return Tpadding;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/include/xipipsu_hw.h
/******************************************************************************
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/**
*
* @file xipipsu_hw.h
* @addtogroup ipipsu_v2_6
* @{
*
* This file contains macro definitions for low level HW related params
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------.
* 1.0 mjr 03/15/15 First release
* 2.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance
* 2.5 sdd 12/17/18 Add the cpp extern macro.
*
* </pre>
*
******************************************************************************/
#ifndef XIPIPSU_HW_H_ /* prevent circular inclusions */
#define XIPIPSU_HW_H_ /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/* Message RAM related params */
#if defined (versal)
#define XIPIPSU_MSG_RAM_BASE 0xFF3F0000U
#else
#define XIPIPSU_MSG_RAM_BASE 0xFF990000U
#endif
#define XIPIPSU_MSG_BUF_SIZE 8U /* Size in Words */
#define XIPIPSU_MAX_BUFF_INDEX 7U
/* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */
#define XIPIPSU_BUFFER_OFFSET_GROUP (8U * 2U * 32U)
#define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U)
#define XIPIPSU_BUFFER_OFFSET_RESPONSE (32U)
/* Number of IPI slots enabled on the device */
#define XIPIPSU_MAX_TARGETS XPAR_XIPIPSU_NUM_TARGETS
/* Register Offsets for each member of IPI Register Set */
#define XIPIPSU_TRIG_OFFSET 0x00U
#define XIPIPSU_OBS_OFFSET 0x04U
#define XIPIPSU_ISR_OFFSET 0x10U
#define XIPIPSU_IMR_OFFSET 0x14U
#define XIPIPSU_IER_OFFSET 0x18U
#define XIPIPSU_IDR_OFFSET 0x1CU
/* MASK of all valid IPI bits in above registers */
#if defined (versal)
#define XIPIPSU_ALL_MASK 0x000003FFU
#else
#define XIPIPSU_ALL_MASK 0x0F0F0301U
#endif
#ifdef __cplusplus
}
#endif
#endif /* XIPIPSU_HW_H_ */
/** @} */
<file_sep>/python_drivers/pulse_gen.py
# -*- coding: utf-8 -*-
"""
Created on Thu Jun 25 17:58:22 2020
@author: tianlab01
"""
import serial
#Command definitions
CMD_PREAMBLE = 0xAA
CMD_RST_CLK = 0x00
CMD_SEND_PULSE = 0x01
CMD_SET_PERIOD = 0x02
CMD_PHASE_MEAS_ON = 0x03
CMD_PHASE_MEAS_OFF = 0x04
CMD_PING_BOARD = 0xFE
CMD_TOGGLE_PHASE_MEAS = 0x05
CMD_QUEUE_PULSE = 0xFD
CMD_SYNC_AND_STREAM = 0x06
CMD_CLEAR_QUEUE = 0x07
CMD_SET_AMPLITUDE = 0x08
CMD_SET_PULSE_LEN = 0x09
CMD_GET_BUSY = 0x0A
ACK_RESPONSE = 0x00
ACK_FAIL = 0xFF
DEFAULT_BAUD = 115200
UART_TIMEOUT = 1
class pulse_gen:
port = None
def __init__(self, portname):
self.port = serial.Serial()
self.port.baudrate = DEFAULT_BAUD
self.port.port = portname
self.port.timeout = UART_TIMEOUT
self.port.open()
def __del__(self):
print("Closing port")
self.port.close()
#def open_board(self):
#self.port.open()
def close_board(self):
self.port.close()
#Returns 0 if connection to board is up
def ping_board(self):
self.port.reset_input_buffer()
#self.port.open()
#send the command
self.port.write([CMD_PREAMBLE, CMD_PING_BOARD])
#Wait for the ack
result = self.wait_ack()
#self.port.close()
if result == ACK_RESPONSE:
return 0
elif result == ACK_FAIL:
print("No running clock detected on the FPGA, is the RF clock input plugged in and running?")
return -1
else:
return -1
#returns ACK_RESPONSE if ack successfully recieved
def wait_ack(self):
#try:
rv = self.port.read(1)
if(len(rv) < 1):
print("Error, no ACK received from FPGA")
return -1
#self.port.reset_input_buffer()
return rv[0]
#except:
# print("Error waiting for ACK from board")
# raise
def phase_meas_on(self):
self.port.reset_input_buffer()
#Send the phase meas on command
self.port.write([CMD_PREAMBLE, CMD_PHASE_MEAS_ON])
#Wait for the ack
result = self.wait_ack()
#self.port.close()
if result == ACK_RESPONSE:
return 0
elif result == ACK_FAIL:
print("No running clock detected on the FPGA, is the RF clock input plugged in and running?")
return -1
else:
print("[PHASE_MEAS_ON]Bad ACK while turning phase measurement on, is the FPGA programmed with the C firmware?")
return -1
def phase_meas_off(self):
self.port.reset_input_buffer()
#self.port.open()
#Send the phase meas on command
self.port.write([CMD_PREAMBLE, CMD_PHASE_MEAS_OFF])
#Wait for the ack
result = self.wait_ack()
#self.port.close()
if result == ACK_RESPONSE:
return 0
elif result == ACK_FAIL:
print("No running clock detected on the FPGA, is the RF clock input plugged in and running?")
return -1
else:
print("[PHASE_MEAS_OFF]Bad ACK while turning phase measurement off, is the FPGA programmed with the C firmware?")
return -1
def toggle_phase_meas(self, num_pulses):
pb1 = (round(num_pulses) >> 8) & 0xFF
pb0 = round(num_pulses) & 0xFF
self.port.reset_input_buffer()
#self.port.open()
#Send the phase meas on command
self.port.write([CMD_PREAMBLE, CMD_TOGGLE_PHASE_MEAS, 0, pb1, pb0])
#Wait for the ack
result = self.wait_ack()
#self.port.close()
if result == ACK_RESPONSE:
return 0
elif result == ACK_FAIL:
print("No running clock detected on the FPGA, is the RF clock input plugged in and running?")
return -1
else:
print("[TOGGLE_PHASE_MEAS]Bad ACK while toggling phase measurement mode, is the FPGA programmed with the C firmware?")
return -1
#Period is in clock cycles 1 clock cycle = 4ns
#Returns 0 on success
def set_period(self, period):
#self.port.open()
self.port.reset_input_buffer()
period_r = round(period)
b0 = (period_r >> 16) & 0xFF
b1 = (period_r >> 8 ) & 0xFF
b2 = period_r & 0xFF
self.port.write([CMD_PREAMBLE, CMD_SET_PERIOD, b0, b1, b2])
#Wait for the ack
result = self.wait_ack()
#self.port.close()
if result == ACK_RESPONSE:
return 0
elif result == ACK_FAIL:
print("No running clock detected on the FPGA, is the RF clock input plugged in and running?")
return -1
else:
print("[SET_PERIOD]Bad ACK while setting period, is the FPGA programmed with the C firmware?")
return -1
#returns 0 on success
#coarse delay is in clock cycles (1 = 4ns)
#fine delay is in DAC samples (1 = 250ps)
def send_pulse(self, coarse_delay, fine_delay):
#self.port.open()
self.port.reset_input_buffer()
b0 = (round(coarse_delay) >> 8) & 0xFF
b1 = round(coarse_delay) & 0xFF
b2 = round(fine_delay) & 0xFF
self.port.write([CMD_PREAMBLE, CMD_SEND_PULSE, b0, b1, b2])
#Wait for the ack
result = self.wait_ack()
#self.port.close()
if result == ACK_RESPONSE:
return 0
elif result == ACK_FAIL:
print("No running clock detected on the FPGA, is the RF clock input plugged in and running?")
return -1
else:
print("[Send Pulse]Bad ACK while sending pulse, is the FPGA programmed with the C firmware?")
return -1
def load_pulse(self, coarse_delay, fine_delay):
#self.port.open()
self.port.reset_input_buffer()
b0 = (round(coarse_delay) >> 8) & 0xFF
b1 = round(coarse_delay) & 0xFF
b2 = round(fine_delay) & 0xFF
self.port.write([CMD_PREAMBLE, CMD_QUEUE_PULSE, b0, b1, b2])
#Wait for the ack
#result = self.wait_ack()
#self.port.close()
#if result == ACK_RESPONSE:
# return 0
#elif result == ACK_FAIL:
# print("[Load pulse]No running clock detected on the FPGA, is the RF clock input plugged in and running?")
# return -1
#else:
# print("[Load Pulse]Bad ACK while sending pulse, is the FPGA programmed with the C firmware?")
# return -1
return 0
def clear_queue(self):
self.port.reset_input_buffer()
self.port.write([CMD_PREAMBLE, CMD_CLEAR_QUEUE])
result = self.wait_ack()
#self.port.close()
if result == ACK_RESPONSE:
return 0
elif result == ACK_FAIL:
print("No running clock detected on the FPGA, is the RF clock input plugged in and running?")
return -1
else:
print("[Clear queue] Bad ACK while sending pulse, is the FPGA programmed with the C firmware?")
return -1
#Num sync pulses is the number of pulses used to synchronize with server before data is sent(max 65535)
#num dead_pulses is number of clock cycles between synchronization and data (max 256)
def sync_and_stream(self, num_sync_pulses, num_dead_pulses):
self.port.reset_input_buffer()
#self.port.open()
self.port.flush
b0 = num_dead_pulses & 0xFF
b1 = (num_sync_pulses >> 8) & 0xFF
b2 = num_sync_pulses & 0xFF
self.port.write([CMD_PREAMBLE,CMD_SYNC_AND_STREAM, b0, b1, b2])
#Wait for the ack
result = self.wait_ack()
#self.port.close()
if result == ACK_RESPONSE:
return 0
elif result == ACK_FAIL:
print("No running clock detected on the FPGA, is the RF clock input plugged in and running?")
return -1
else:
print("[sync and stream]Bad ACK while sending pulse, is the FPGA programmed with the C firmware?")
return -1
def set_amplitude(self, amp):
#if(amp < 0 or amp > 0x7fff):
# print("Error, board amplitude must be between 0 and 0x7FFF")
# return
self.port.reset_input_buffer()
#self.port.open()
self.port.flush
b0 = 0
b1 = (amp >> 8) & 0xFF
b2 = amp & 0xFF
self.port.write([CMD_PREAMBLE,CMD_SET_AMPLITUDE, b0, b1, b2])
#Wait for the ack
result = self.wait_ack()
#self.port.close()
if result == ACK_RESPONSE:
return 0
elif result == ACK_FAIL:
print("No running clock detected on the FPGA, is the RF clock input plugged in and running?")
return -1
else:
print("[set amplitude]Bad ACK while sending pulse, is the FPGA programmed with the C firmware?")
return -1
def set_pulse_len(self, num_samples):
if(num_samples < 1 or num_samples > 65535):
print("Error, number of pulse samples must be between 1 and 2^16")
return
self.port.reset_input_buffer()
#self.port.open()
self.port.flush
b0 = 0
b1 = (num_samples >> 8) & 0xFF
b2 = num_samples & 0xFF
self.port.write([CMD_PREAMBLE,CMD_SET_PULSE_LEN, b0, b1, b2])
#Wait for the ack
result = self.wait_ack()
#self.port.close()
if result == ACK_RESPONSE:
return 0
elif result == ACK_FAIL:
print("No running clock detected on the FPGA, is the RF clock input plugged in and running?")
return -1
else:
print("[set pulse len]Bad ACK while sending pulse, is the FPGA programmed with the C firmware?")
return -1
#Returns 1 if board is busy sending something
def get_busy(self):
self.port.reset_input_buffer()
self.port.write([CMD_PREAMBLE,CMD_GET_BUSY])
return self.wait_ack()
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/rtcpsu_v1_9/src/xrtcpsu_selftest.c
/******************************************************************************
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xrtcpsu_selftest.c
* @addtogroup rtcpsu_v1_9
* @{
*
* This file contains the self-test functions for the XRtcPsu driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00 kvn 04/21/15 First release.
* 1.7 sne 03/01/19 Added Versal support.
* 1.7 sne 03/01/19 Fixed violations according to MISRAC-2012 standards
* modified the code such as
* No brackets to loop body,Declared the poiner param
* as Pointer to const,No brackets to then/else,
* Literal value requires a U suffix,Casting operation to a pointer
* Array has no bounds specified,Logical conjunctions need brackets.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xrtcpsu.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/****************************************************************************/
/**
*
* This function runs a self-test on the driver and hardware device. This self
* test writes reset value into safety check register and read backs the same.
* If mismatch offers, returns the failure.
*
* @param InstancePtr is a pointer to the XRtcPsu instance
*
* @return
* - XST_SUCCESS if the test was successful
*
* @note
*
* This function can hang if the hardware is not functioning properly.
*
******************************************************************************/
s32 XRtcPsu_SelfTest(const XRtcPsu *InstancePtr)
{
s32 Status = XST_SUCCESS;
u32 SafetyCheck;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Write the reset value in safety check register and
* try reading back. If mismatch happens, return failure.
*/
XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_SFTY_CHK_OFFSET,
XRTC_SFTY_CHK_RSTVAL);
SafetyCheck = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
XRTC_SFTY_CHK_OFFSET);
if (SafetyCheck != XRTC_SFTY_CHK_RSTVAL) {
Status = XST_FAILURE;
}
return Status;
}
/** @} */
<file_sep>/vitis_workspace/.metadata/.plugins/org.eclipse.tcf.debug/peers.ini
SDKUseSymbolServer=false
TransportName=TCP
UserName=tianlab01
Port=3121
Host=127.0.0.1
OSName=Windows 10
MANUAL_CONFIG=false
Name=Local
MANUAL_DEVICES=
ServiceManagerID=7fbaa9e2-c0de-4615-a355-2ce97344fba4
PeerTypeId=HARDWARE_SERVER
Frequency=
ID=Local
AgentID=7fbaa9e2-c0de-4615-a355-2ce97344fba4
ServiceManagerID=7fbaa9e2-c0de-4615-a355-2ce97344fba4
TransportName=TCP
PeerTypeId=LINUX_TCF_AGENT
UserName=tianlab01
Port=1534
Host=192.168.0.1
OSName=Windows 10
ID=Linux Agent
AgentID=7fbaa9e2-c0de-4615-a355-2ce97344fba4
Name=Linux Agent
ServiceManagerID=7fbaa9e2-c0de-4615-a355-2ce97344fba4
TransportName=TCP
PeerTypeId=QEMU_TCF_GDB_CLIENT
UserName=tianlab01
Port=1138
Host=127.0.0.1
OSName=Windows 10
ID=QEMU
AgentID=7fbaa9e2-c0de-4615-a355-2ce97344fba4
Name=QEMU
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/xsecure_aes_hw.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_aes_hw.h
*
* This is the header file which contains ZynqMP AES core hardware definitions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.0 vns 03/11/19 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XSECURE_AES_HW_H
#define XSECURE_AES_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
#define XSECURE_CSU_AES_BASE (0xFFCA1000 )
/**< CSU AES base address */
#define XSECURE_CSU_PCAP_STATUS (0xFFCA3010U)
/**< CSU PCAP Status reg. */
#define XSECURE_CSU_PCAP_STATUS_PCAP_WR_IDLE_MASK (0X00000001U)
/**< PCAP Write Idle */
/** @name Register Map
*
* Register offsets for the AES module.
* @{
*/
#define XSECURE_CSU_AES_STS_OFFSET (0x00U) /**< AES Status */
#define XSECURE_CSU_AES_KEY_SRC_OFFSET (0x04U) /**< AES Key Source */
#define XSECURE_CSU_AES_KEY_LOAD_OFFSET (0x08U) /**< AES Key Load Reg */
#define XSECURE_CSU_AES_START_MSG_OFFSET (0x0CU) /**< AES Start Message */
#define XSECURE_CSU_AES_RESET_OFFSET (0x10U) /**< AES Reset Register */
#define XSECURE_CSU_AES_KEY_CLR_OFFSET (0x14U) /**< AES Key Clear */
#define XSECURE_CSU_AES_CFG_OFFSET (0x18U)/**< AES Operational Mode */
#define XSECURE_CSU_AES_KUP_WR_OFFSET (0x1CU)/**< AES KUP Write Control */
#define XSECURE_CSU_AES_KUP_0_OFFSET (0x20U)
/**< AES Key Update 0 */
#define XSECURE_CSU_AES_KUP_1_OFFSET (0x24U) /**< AES Key Update 1 */
#define XSECURE_CSU_AES_KUP_2_OFFSET (0x28U) /**< AES Key Update 2 */
#define XSECURE_CSU_AES_KUP_3_OFFSET (0x2CU) /**< AES Key Update 3 */
#define XSECURE_CSU_AES_KUP_4_OFFSET (0x30U) /**< AES Key Update 4 */
#define XSECURE_CSU_AES_KUP_5_OFFSET (0x34U) /**< AES Key Update 5 */
#define XSECURE_CSU_AES_KUP_6_OFFSET (0x38U) /**< AES Key Update 6 */
#define XSECURE_CSU_AES_KUP_7_OFFSET (0x3CU) /**< AES Key Update 7 */
#define XSECURE_CSU_AES_IV_0_OFFSET (0x40U) /**< AES IV 0 */
#define XSECURE_CSU_AES_IV_1_OFFSET (0x44U) /**< AES IV 1 */
#define XSECURE_CSU_AES_IV_2_OFFSET (0x48U) /**< AES IV 2 */
#define XSECURE_CSU_AES_IV_3_OFFSET (0x4CU) /**< AES IV 3 */
/* @} */
/**************************** Type Definitions *******************************/
/*****************************************************************************/
/**
* Wait for writes to PL and hence PCAP write cycle to complete
*
* @param None.
*
* @return None.
*
* @note C-Style signature:
* void XSecure_PcapWaitForDone(void)
*
******************************************************************************/
static inline void XSecure_PcapWaitForDone()
{
while ((Xil_In32(XSECURE_CSU_PCAP_STATUS) &
XSECURE_CSU_PCAP_STATUS_PCAP_WR_IDLE_MASK) !=
XSECURE_CSU_PCAP_STATUS_PCAP_WR_IDLE_MASK);
}
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_AES_HW_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_apucore.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xil_io.h"
#include "xpm_apucore.h"
#include "xpm_regs.h"
static int XPmApuCore_RestoreResumeAddr(XPm_Core *Core)
{
int Status = XST_FAILURE;
u32 AddrLow = (u32) (Core->ResumeAddr & 0xfffffffeULL);
u32 AddrHigh = (u32) (Core->ResumeAddr >> 32ULL);
XPm_ApuCore *ApuCore = (XPm_ApuCore *)Core;
/* Check for valid resume address */
if (0U == (Core->ResumeAddr & 1ULL)) {
PmErr("Invalid resume address\r\n");
goto done;
}
if ((u32)XPM_NODEIDX_DEV_ACPU_0 == NODEINDEX(Core->Device.Node.Id)) {
PmOut32(ApuCore->FpdApuBaseAddr + APU_DUAL_RVBARADDR0L_OFFSET, AddrLow);
PmOut32(ApuCore->FpdApuBaseAddr + APU_DUAL_RVBARADDR0H_OFFSET, AddrHigh);
Status = XST_SUCCESS;
} else if ((u32)XPM_NODEIDX_DEV_ACPU_1 == NODEINDEX(Core->Device.Node.Id)) {
PmOut32(ApuCore->FpdApuBaseAddr + APU_DUAL_RVBARADDR1L_OFFSET, AddrLow);
PmOut32(ApuCore->FpdApuBaseAddr + APU_DUAL_RVBARADDR1H_OFFSET, AddrHigh);
Status = XST_SUCCESS;
} else {
Status = XST_INVALID_PARAM;
}
Core->ResumeAddr = 0ULL;
done:
return Status;
}
static int XPmApuCore_HasResumeAddr(XPm_Core *Core)
{
XStatus Status = XST_FAILURE;
if (0U != (Core->ResumeAddr & 1ULL)) {
Status = XST_SUCCESS;
}
return Status;
}
static XStatus XPmApuCore_WakeUp(XPm_Core *Core, u32 SetAddress, u64 Address)
{
XStatus Status = XST_FAILURE;
/* Set reset address */
if (1U == SetAddress) {
Core->ResumeAddr = Address | 1U;
}
Status = XPmCore_WakeUp(Core);
if (XST_SUCCESS != Status) {
PmErr("Core Wake Up failed, Status = %x\r\n", Status);
goto done;
}
/* Release reset for all resets attached to this core */
Status = XPmDevice_Reset(&Core->Device, PM_RESET_ACTION_RELEASE);
if (XST_SUCCESS != Status) {
goto done;
}
Core->Device.Node.State = (u8)XPM_DEVSTATE_RUNNING;
done:
return Status;
}
static XStatus XPmApuCore_PwrDwn(XPm_Core *Core)
{
XStatus Status = XST_FAILURE;
Status = XPmCore_PwrDwn(Core);
return Status;
}
static struct XPm_CoreOps ApuOps = {
.RestoreResumeAddr = XPmApuCore_RestoreResumeAddr,
.HasResumeAddr = XPmApuCore_HasResumeAddr,
.RequestWakeup = XPmApuCore_WakeUp,
.PowerDown = XPmApuCore_PwrDwn,
};
XStatus XPmApuCore_Init(XPm_ApuCore *ApuCore,
u32 Id,
u32 Ipi,
u32 *BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock, XPm_ResetNode *Reset)
{
XStatus Status = XST_FAILURE;
Status = XPmCore_Init(&ApuCore->Core, Id, Power, Clock, Reset, (u8)Ipi,
&ApuOps);
ApuCore->FpdApuBaseAddr = BaseAddress[0];
if (NODEINDEX(Id) == (u32)XPM_NODEIDX_DEV_ACPU_0) {
ApuCore->Core.SleepMask = XPM_ACPU_0_PWR_CTRL_MASK;
ApuCore->Core.PwrDwnMask = XPM_ACPU_0_CPUPWRDWNREQ_MASK;
} else if (NODEINDEX(Id) == (u32)XPM_NODEIDX_DEV_ACPU_1) {
ApuCore->Core.SleepMask = XPM_ACPU_1_PWR_CTRL_MASK;
ApuCore->Core.PwrDwnMask = XPM_ACPU_1_CPUPWRDWNREQ_MASK;
} else {
Status = XST_INVALID_PARAM;
}
return Status;
}
<file_sep>/python_drivers/qutag_examples/qutag-GetHistogram-starter_example.py
# Example for using the Coincidence Counters with python + quTAG
#
# Author: qutools GmbH
# Last edited: Sep 2019
#
# Tested with python 3.7 (32bit), numpy-1.13.3 and Windows 7 (64bit)
#
# This is demo code. Use at your own risk. No warranties.
#
# It may be used and modified with no restriction; raw copies as well as
# modified versions may be distributed without limitation.
# for plotting
import matplotlib.pyplot as plt
import matplotlib.animation as animation
from matplotlib import style
# for sleep
import time
# This code shows how to get histograms from a quTAG connected via USB.
# Additionally we are plotting the data with matplotlib.
# Import the python wrapper which wraps the DLL functions.
# The wrapper should be in the same directory like this code in the folder '..\QUTAG-V1.5.0\userlib\src'.
try:
import QuTAG
except:
print("Time Tagger wrapper QuTAG.py is not in the search path.")
# initialize device
qutag = QuTAG.QuTAG()
# Choose our start and stop channel
ch_start = 2
ch_stop = 3
### Let's add/remove (True/False) a histogram with specified start and stop channels.
# All time differences beween a start and the first following stop event will contribute to the histogram.
### This function also enables the calculation of start stop histograms ( qutag.enableStartStop(True) ). When enabled, all incoming events contribute to the histograms.
# When disabled ( qutag.enableStartStop(False) ), all corresponding functions are unavailable. The function implicitly clears the histograms.
qutag.addHistogram(ch_start,ch_stop,True)
# Wait a second for accumulating new data
time.sleep(1)
### Get the histogram of channel ch_start & ch_stop and clear the data with True
rc = qutag.getHistogram(ch_start,ch_stop,True)
# Returns an array with:
# data array with at least binCount elements
# Total number of time differences in the histogram
# Number of time diffs that were smaller than the smallest histogram bin
# Number of time diffs that were bigger than the biggest histogram bin.
# Number of events on the start channel contributing to the histogram.
# Number of events on the stop channel contributing to the histogram.
# Total exposure time for the histogram: the time difference between the first and the last event that contribute to the histogram. In timebase units.
print("Counts inside the histogram: ", rc[1], "| Counts too Small: ", rc[2], "| Counts too Large: ", rc[3], "| starts: ", rc[4], "| stops: ", rc[5], "| max exposure time: ", rc[6]/1000, "ns")
# Plotting with mathplotlib
style.use('fivethirtyeight')
fig = plt.figure()
fig.set_size_inches(10,7)
ax1 = fig.add_subplot(1,1,1)
plt.cla() # clear old plotting data
# plot the datapoints
plt.plot(rc[0])
ax1.set_title('quTAG Histogram')
plt.pause(0.05)
# Disconnects a connected device and stops the internal event loop.
qutag.deInitialize()
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_util.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPFW_UTIL_H_
#define XPFW_UTIL_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
#include "xstatus.h"
#define BIT(n) (1U << (n))
/**
* Read Modify Write a register
*/
void XPfw_UtilRMW(u32 RegAddress, u32 Mask, u32 Value);
/**
* Poll for a set of bits to be set (represented by Mask)
* or until we TimeOut
* @param RegAddress is the Address of the Register to be polled
* @param Mask is the bit mask to poll for in the register value
* @param TimeOutCount is the value to count down before return failure
*/
XStatus XPfw_UtilPollForMask(u32 RegAddress, u32 Mask, u32 TimeOutCount);
/**
* Poll for a set of bits to be cleared (represented by Mask)
* or until we TimeOut
*
* @param RegAddress is the Address of the Register to be polled
* @param Mask is the bit mask to poll for in the register value
* @param TimeOutCount is the value to count down before return failure
*/
XStatus XPfw_UtilPollForZero(u32 RegAddress, u32 Mask, u32 TimeOutCount);
/**
* Wait for a period represented by TimeOut
*
* @param Timeout is the value to count before we return this function
*/
void XPfw_UtilWait(u32 TimeOutCount);
#ifdef __cplusplus
}
#endif
#endif /* XPFW_UTIL_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/client/pm_callbacks.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef PM_CALLBACKS_H_
#define PM_CALLBACKS_H_
#include "pm_api_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
XStatus XPm_NotifierAdd(XPm_Notifier* const Notifier);
XStatus XPm_NotifierRemove(XPm_Notifier* const Notifier);
void XPm_NotifierProcessEvent(const u32 Node, const enum XPmNotifyEvent Event,
const u32 Oppoint);
#ifdef __cplusplus
}
#endif
#endif /* PM_CALLBACKS_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilsecure_v4_2/src/versal/xsecure_sss.h
/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_sss.h
*
* This file contains macros and functions required for SSS configuration for
* Versal
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 4.2 har 03/26/20 Initial Release
*
* </pre>
* @endcond
******************************************************************************/
#ifndef XSECURE_SSS_H
#define XSECURE_SSS_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions ****************************/
/** @cond xsecure_internal */
#define XSECURE_SSS_CFG_LEN_IN_BITS (4U) /**< Length is bits */
#define XSECURE_SSS_ADDRESS (0xF1110500U) /**< SSS base address */
#define XSECURE_SSS_MAX_SRCS (8U) /**< Maximum resources */
/***************************** Type Definitions******************************/
/**
* Instance structure of secure stream switch
*/
typedef struct {
u32 Address; /**< Address of SSS CFG register */
}XSecure_Sss;
/*
* Sources to be selected to configure secure stream switch.
* XSECURE_SSS__IGNORE is added to make enum type int
* irrespective of compiler used.
*/
typedef enum {
XSECURE_SSS_IGNORE = -1,
XSECURE_SSS_DMA0 = 0,
XSECURE_SSS_DMA1,
XSECURE_SSS_PTPI,
XSECURE_SSS_AES,
XSECURE_SSS_SHA,
XSECURE_SSS_SBI,
XSECURE_SSS_PZI,
XSECURE_SSS_INVALID
}XSecure_SssSrc;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void XSecure_SssInitialize(XSecure_Sss *InstancePtr);
u32 XSecure_SssAes(XSecure_Sss *InstancePtr, XSecure_SssSrc InputSrc,
XSecure_SssSrc OutputSrc);
u32 XSecure_SssSha(XSecure_Sss *InstancePtr, u16 DmaId);
u32 XSecure_SssDmaLoopBack(XSecure_Sss *InstancePtr, u16 DmaId);
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_SSS_H_ */
/**@}*/
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_proc.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* Contains all functions, datas and definitions needed for
* managing processor's states.
*********************************************************************/
#ifndef PM_PROC_H_
#define PM_PROC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_common.h"
#include "pm_node.h"
typedef u8 PmProcEvent;
/*********************************************************************
* Macros
********************************************************************/
#define DISABLE_WFI(mask) XPfw_RMW32(PMU_LOCAL_GPI2_ENABLE, (mask), ~(mask));
/*
* Processor is powered down as requested by a master which is privileged
* to request so. Processor has not saved its context.
*/
#define PM_PROC_STATE_FORCEDOFF 0U
/*
* Processor sleep state (specific for the processor implementation,
* if processor has its own power domain it is powered down)
*/
#define PM_PROC_STATE_SLEEP 2U
/*
* Processor active state. If it executes WFI without previously requesting
* suspend through PM API it is considered active.
*/
#define PM_PROC_STATE_ACTIVE 1U
/*
* Processor suspending state. It has called pm_self_suspend but WFI
* interrupt from this processor is not yet received.
*/
#define PM_PROC_STATE_SUSPENDING 3U
/* Triggered when pm_self_suspend call is received for a processor */
#define PM_PROC_EVENT_SELF_SUSPEND 1U
/*
* Triggered by pm_abort_suspend call made by a processor to cancel its
* own suspend.
*/
#define PM_PROC_EVENT_ABORT_SUSPEND 2U
/* Triggered when processor has executed wfi instruction */
#define PM_PROC_EVENT_SLEEP 3U
/* Triggered when a master requested force powerdown for this processor */
#define PM_PROC_EVENT_FORCE_PWRDN 4U
/* Triggered when PMU receives wake interrupt targeted to the processor */
#define PM_PROC_EVENT_WAKE 5U
#define RPU0_STATUS_MASK BIT(1U)
#define RPU1_STATUS_MASK BIT(2U)
#define PM_PROC_RPU_LOVEC_ADDR 0x00000000U
#define PM_PROC_RPU_HIVEC_ADDR 0xFFFF0000U
/*********************************************************************
* Structure definitions
********************************************************************/
typedef struct PmMaster PmMaster;
typedef struct PmProc PmProc;
/**
* PmProc - Processor node's structure
* @node Processor's node structure
* @resumeAddress Address from which processor should resume
* resumeAddress BIT0=1 indicates valid address
* @master Master channel used by this processor
* @saveResumeAddr Pointer to function for saving the resume address
* @restoreResumeAddr Pointer to function for restoring resume address
* @init Init handler specific to the processor
* @sleep Pointer to the processor's sleep handler
* @wake Pointer to the processor's wake handler
* @resumeCfg Address of register configuring processor's resume address
* @pwrDnReqAddr Address of the power down request register
* @pwrDnReqMask Mask in the power down request register
* @latencyReq Latenct requirement as passed in by self_suspend argument
* @pwrDnLatency Latency (in us) for transition to OFF state
* @pwrUpLatency Latency (in us) for transition to ON state
* @mask Unique mask of the processor in PM_IOMODULE_GPI2,
* PM_IOMODULE_GPI1, PM_LOCAL_GPI2_ENABLE, and
* PM_LOCAL_GPI1_ENABLE registers
*/
typedef struct PmProc {
PmNode node;
u64 resumeAddress;
PmMaster* master;
s32 (*const saveResumeAddr)(PmProc* const, u64);
void (*const restoreResumeAddr)(PmProc* const);
void (*const init)(PmProc* const proc);
s32 (*const sleep)(void);
s32 (*const wake)(void);
const u32 mask;
const u32 resumeCfg;
const u32 pwrDnReqAddr;
const u32 pwrDnReqMask;
u32 latencyReq;
const u32 pwrDnLatency;
const u32 pwrUpLatency;
} PmProc;
/*********************************************************************
* Global data declarations
********************************************************************/
extern PmProc pmProcApu0_g;
extern PmProc pmProcApu1_g;
extern PmProc pmProcApu2_g;
extern PmProc pmProcApu3_g;
extern PmProc pmProcRpu0_g;
extern PmProc pmProcRpu1_g;
extern PmNodeClass pmNodeClassProc_g;
/*********************************************************************
* Function declarations
********************************************************************/
s32 PmProcFsm(PmProc* const proc, const PmProcEvent event);
bool PmProcHasResumeAddr(const PmProc* const proc);
PmProc* PmProcGetByWakeMask(const u32 wake);
/**
* PmProcIsForcedOff() - Check whether given processor is in forced off state
*/
static inline bool PmProcIsForcedOff(const PmProc* const procPtr)
{
return PM_PROC_STATE_FORCEDOFF == procPtr->node.currState;
}
/**
* PmProcIsAsleep() - Check whether given processor is in sleep state
*/
static inline bool PmProcIsAsleep(const PmProc* const procPtr)
{
return PM_PROC_STATE_SLEEP == procPtr->node.currState;
}
/**
* PmProcIsSuspending() - Check whether given processor is in suspending state
*/
static inline bool PmProcIsSuspending(const PmProc* const procPtr)
{
return PM_PROC_STATE_SUSPENDING == procPtr->node.currState;
}
s32 PmProcSleep(PmProc* const proc);
#ifdef ENABLE_UNUSED_RPU_PWR_DWN
void PmForceDownUnusableRpuCores(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* PM_PROC_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_slave.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* All functions, data and definitions needed for
* managing PM slaves' states.
*********************************************************************/
#ifndef PM_SLAVE_H_
#define PM_SLAVE_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_defs.h"
#include "pm_common.h"
#include "pm_node.h"
/* Forward declarations */
typedef struct PmMaster PmMaster;
typedef struct PmRequirement PmRequirement;
typedef struct PmSlave PmSlave;
typedef struct PmSlaveClass PmSlaveClass;
typedef struct PmWakeEvent PmWakeEvent;
/*********************************************************************
* Macros
********************************************************************/
/* Mask definitions for slave's flags */
#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U
#define DEFINE_SLAVE_STATES(s) .states = (s), \
.statesCnt = ARRAY_SIZE(s)
#define DEFINE_SLAVE_TRANS(t) .trans = (t), \
.transCnt = ARRAY_SIZE(t)
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmWakeEventClass - Class of the wake event
* @set Set event as the wake source (must be defined by each class)
* @config Configure the propagation of wake event (master requested)
*/
typedef struct PmWakeEventClass {
void (*const set)(PmWakeEvent* const wake, const u32 ipi, const u32 en);
void (*const config)(PmWakeEvent* const wake, const u32 ipi, const u32 en);
} PmWakeEventClass;
/**
* PmWakeEvent - Structure to model wake event that can be triggered by slave
* @derived Pointer to the derived structure
* @class Pointer to the class specific to the derived structure
*/
typedef struct PmWakeEvent {
void* const derived;
PmWakeEventClass* const class;
} PmWakeEvent;
/**
* PmStateTran - Transition for a state in finite state machine
* @latency Transition latency in microseconds
* @fromState From which state the transition is taken
* @toState To which state the transition is taken
*/
typedef struct {
const u32 latency;
PmStateId fromState;
PmStateId toState;
} PmStateTran;
/**
* PmSlaveFsm - Finite state machine data for slaves
* @states Pointer to states array. Index in array is a state id.
* @enterState Pointer to a function that executes FSM actions to enter a state
* @trans Pointer to array of transitions of the FSM
* @transCnt Number of elements in transition array
* @statesCnt Number of states in state array
*/
typedef struct {
const u8* const states;
s32 (*const enterState)(PmSlave* const slave, const PmStateId nextState);
const PmStateTran* const trans;
const u8 statesCnt;
const u8 transCnt;
} PmSlaveFsm;
/**
* PmSlave - Slave structure used for managing slave's states
* @node Pointer to the node structure of this slave
* @class Slave class (NULL if derived slave has no specific methods to be
* called in addition to methods of PmNodeClass)
* @reqs Pointer to the list of masters' requirements for the slave
* @wake Wake event this slave can generate
* @slvFsm Slave finite state machine
* @flags Slave's flags (bit 0: whether the slave is shareable (1) or
* exclusive (0) resource)
*/
typedef struct PmSlave {
PmNode node;
PmSlaveClass* const class;
PmRequirement* reqs;
PmWakeEvent* const wake;
const PmSlaveFsm* slvFsm;
u8 flags;
} PmSlave;
/**
* PmSlaveClass - Slave class to model properties of PmSlave derived objects
* @init Initialize the slave
* @forceDown Force down specific to the slave
*/
typedef struct PmSlaveClass {
s32 (*const init)(PmSlave* const slave);
s32 (*const forceDown)(PmSlave* const slave);
} PmSlaveClass;
/*********************************************************************
* Global data declarations
********************************************************************/
extern PmNodeClass pmNodeClassSlave_g;
/*********************************************************************
* Function declarations
********************************************************************/
s32 PmUpdateSlave(PmSlave* const slave);
s32 PmCheckCapabilities(const PmSlave* const slave, const u32 capabilities);
s32 PmSlaveHasWakeUpCap(const PmSlave* const slv);
s32 PmSlaveSetConfig(PmSlave* const slave, const u32 policy, const u32 perms);
s32 PmSlaveVerifyRequest(const PmSlave* const slave);
u32 PmSlaveGetUsersMask(const PmSlave* const slave);
u32 PmSlaveGetUsageStatus(const PmSlave* const slave,
const PmMaster* const master);
u32 PmSlaveGetRequirements(const PmSlave* const slave,
const PmMaster* const master);
void PmResetSlaveStates(void);
#ifdef __cplusplus
}
#endif
#endif /* PM_SLAVE_H_ */
<file_sep>/python_drivers/qutag_examples/qutag-GetHistogramLoop-channelDelay-example.py
# Example for using the Coincidence Counters with python + quTAG
#
# Author: qutools GmbH
# Last edited: Sep 2019
#
# Tested with python 3.7 (32bit), numpy-1.13.3 and Windows 7 (64bit)
#
# This is demo code. Use at your own risk. No warranties.
#
# It may be used and modified with no restriction; raw copies as well as
# modified versions may be distributed without limitation.
# for plotting
import matplotlib.pyplot as plt
import matplotlib.animation as animation
from matplotlib import style
# for numpy arrays
import numpy as np
# for sleep
import time
# This code shows how to get histograms from a quTAG connected via USB.
# Additionally we are using channel delays to shift the histogram in the plot.
# Import the python wrapper which wraps the DLL functions.
# The wrapper should be in the same directory like this code in the folder '..\QUTAG-V1.5.0\userlib\src'.
try:
import QuTAG
except:
print("Time Tagger wrapper QuTAG.py is not in the search path.")
# initialize device
qutag = QuTAG.QuTAG()
# Choose our start and stop channel
ch_start = 2
ch_stop = 1
# Let's add/remove (True/False) a histogram with specified start and stop channels.
# All time differences beween a start and the first following stop event will contribute to the histogram.
# This function also enables the calculation of start stop histograms. When enabled, all incoming events contribute to the histograms.
# When disabled, all corresponding functions are unavailable. The function implicitly clears the histograms.
qutag.addHistogram(ch_start,ch_stop,True)
# Sets parameters for the internally generated start stop histograms: bin width in ps & bin count (range = 2 ... 1000000, default = 10000)
# If the function is not called, default values are in place. When the function is called, all collected histogram data are cleared.
qutag.setHistogramParams(1,3000)
# plotting with mathplotlib
style.use('fivethirtyeight')
fig = plt.figure()
fig.set_size_inches(10,7)
ax1 = fig.add_subplot(1,1,1)
# Array for the channel delays with zero ps. We are going to shift the delay on channel ch_start in the coming loop.
channelDelays = np.zeros(int(8), dtype=np.int32)
# Change the array for channel ch_start 1670ps, later we will set the delays via function. Array looks like: [0,0,1670,0,0,0,0,0]
# Optimized for periodical 1MHz input at channel ch_start & ch_stop
channelDelays[ch_stop] = 0
# Let's get histograms of the device in a loop with increasing channel delay.
while True:
# Shift the delay on channel 'ch_start' +20ps each loop by changing the created array
channelDelays[ch_stop] += 10
# Set the new channel delay with the created and changed array
qutag.setChannelDelays(channelDelays)
if (channelDelays[ch_stop] > 1200):
# Reset the channel delay for plotting range
channelDelays[ch_stop] = 0
time.sleep(0.2)
# Clear histogram data with True to avoid old data at another channel delay
qutag.getHistogram(ch_start,ch_stop,True)
# wait a second for accumulating data
time.sleep(0.1)
# get the histogram of channel ch_start & ch_stop and clear the data
rc = qutag.getHistogram(ch_start,ch_stop,True)
print("Counts inside the histogram: ", rc[1], "| Counts too Small: ", rc[2], "| Counts too Large: ", rc[3], "| max Exposure time: ", rc[6]/1000, "ns")
# Plotting...
plt.cla() # clear old plotting data
# plot the first 1000 datapoints to 'zoom in'
#plt.plot(rc[0])
plt.plot(rc[0][0:1000])
ax1.set_title('quTAG Histogram - channel delay ' + str(channelDelays[ch_stop]) + ' ps')
plt.pause(0.05)
# Disconnects a connected device and stops the internal event loop.
qutag.deInitialize()
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/libmetal_v2_1/src/libmetal/cmake/platforms/toolchain.cmake
set (CMAKE_SYSTEM_PROCESSOR "arm" CACHE STRING "")
set (MACHINE "zynqmp_a53")
set (CROSS_PREFIX "aarch64-none-elf-" CACHE STRING "")
set (CMAKE_C_FLAGS "-O2 -c -g -Wall -Wextra -IC:/James/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/include" CACHE STRING "")
set (CMAKE_SYSTEM_NAME "Generic" CACHE STRING "")
include (CMakeForceCompiler)
CMAKE_FORCE_C_COMPILER ("${CROSS_PREFIX}gcc" GNU)
CMAKE_FORCE_CXX_COMPILER ("${CROSS_PREFIX}g++" GNU)
set (CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER CACHE STRING "")
set (CMAKE_FIND_ROOT_PATH_MODE_LIBRARY NEVER CACHE STRING "")
set (CMAKE_FIND_ROOT_PATH_MODE_INCLUDE NEVER CACHE STRING "")
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/zynqmp/xsecure_sha.c
/******************************************************************************
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_sha.c
*
* This file contains the implementation of the interface functions for SHA
* driver. Refer to the header file xsecure_sha.h for more detailed information.
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 ba 08/10/14 Initial release
* 2.0 vns 01/28/17 Added API to read SHA3 hash.
* 2.2 vns 07/06/17 Added doxygen tags
* 3.0 vns 01/23/18 Added NIST SHA3 support.
* Added SSS configuration before every CSU DMA transfer
* 3.2 ka 04/30/18 Modified SHa3 hash calculation fuctionality to
* support the following features:
* - To support byte aligned data,
* - To support non-word aligned address
* - And also fixed limitation of input data,
* now size of input can be of any size.
* not limitted to 512MB.
* 4.0 arc 12/18/18 Fixed MISRA-C violations.
* arc 03/06/19 Added asserts to validate input params.
* vns 03/12/19 Modified as part of XilSecure code re-arch.
* arc 03/20/19 Added time outs and status info for API's.
* mmd 03/15/19 Refactored the code.
* psl 03/26/19 Fixed MISRA-C violation
* vns 03/30/19 Added error condition in XSecure_Sha3Finish for
* for wrong pad selection
* 4.1 kal 05/20/19 Updated doxygen tags
* psl 07/02/19 Fixed Coverity warnings.
* mmd 07/05/19 Optimized the code
* psl 07/31/19 Fixed MISRA-C violation
* 4.2 har 01/06/20 Removed asserts to validate zero size of data as per
* CR-1049217 since hashing of zero size data is valid
* mmd 02/03/20 optimized XSecure_Sha3DataUpdate function
* kpt 02/03/20 Enhanced the Code for non-aligned data and
* aligned address i.e CR-1052152
* har 03/23/20 Moved to zynqmp directory and removed versal related code
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsecure_sha_hw.h"
#include "xsecure_sha.h"
#include "xil_util.h"
#include "xil_assert.h"
#include "xsecure_utils.h"
/************************** Constant Definitions *****************************/
#define XSECURE_CSU_SHA3_HASH_LENGTH_IN_BITS (384U)
#define XSECURE_CSU_SHA3_HASH_LENGTH_IN_WORDS \
(XSECURE_CSU_SHA3_HASH_LENGTH_IN_BITS / 32U)
/* Keccak and Nist padding masks */
#define XSECURE_CSU_SHA3_START_KECCAK_PADDING_MASK (0x01U)
#define XSECURE_CSU_SHA3_END_KECCAK_PADDING_MASK (0x80U)
#define XSECURE_CSU_SHA3_START_NIST_PADDING_MASK (0x06U)
#define XSECURE_CSU_SHA3_END_NIST_PADDING_MASK (0x80U)
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* @brief
* This inline function waits till SHA3 completes its operation.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
*
* @return XST_SUCCESS if the SHA3 completes its operation.
* XST_FAILURE if a timeout has occurred.
*
******************************************************************************/
inline u32 XSecure_Sha3WaitForDone(XSecure_Sha3 *InstancePtr)
{
return Xil_WaitForEvent((InstancePtr)->BaseAddress + XSECURE_CSU_SHA3_DONE_OFFSET,
XSECURE_CSU_SHA3_DONE_DONE,
XSECURE_CSU_SHA3_DONE_DONE,
XSECURE_SHA_TIMEOUT_MAX);
}
/************************** Function Prototypes ******************************/
static u32 XSecure_Sha3DmaTransfer(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size, u8 IsLast);
static u32 XSecure_Sha3DataUpdate(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size, u8 IsLastUpdate);
static void XSecure_Sha3KeccakPadd(XSecure_Sha3 *InstancePtr, u8 *Dst,
u32 MsgLen);
static void XSecure_Sha3NistPadd(XSecure_Sha3 *InstancePtr, u8 *Dst,
u32 MsgLen);
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/****************************************************************************/
/**
* @brief
* This function initializes a XSecure_Sha3 structure with the default values
* required for operating the SHA3 cryptographic engine.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param CsuDmaPtr Pointer to the XCsuDma instance.
*
* @return XST_SUCCESS if initialization was successful
*
* @note The base address is initialized directly with value from
* xsecure_hw.h
* The default is NIST SHA3 padding, to change to KECCAK
* padding call XSecure_Sha3PadSelection() after
* XSecure_Sha3Initialize().
*
*****************************************************************************/
s32 XSecure_Sha3Initialize(XSecure_Sha3 *InstancePtr, XCsuDma* CsuDmaPtr)
{
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CsuDmaPtr != NULL);
InstancePtr->BaseAddress = XSECURE_CSU_SHA3_BASE;
InstancePtr->Sha3Len = 0U;
InstancePtr->CsuDmaPtr = CsuDmaPtr;
InstancePtr->Sha3PadType = XSECURE_CSU_NIST_SHA3;
InstancePtr->IsLastUpdate = FALSE;
XSecure_SssInitialize(&(InstancePtr->SssInstance));
InstancePtr->Sha3State = XSECURE_SHA3_INITIALIZED;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* @brief
* This function provides an option to select the SHA-3 padding type to be used
* while calculating the hash.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Sha3Type Type of SHA3 padding to be used.
* - For NIST SHA-3 padding - XSECURE_CSU_NIST_SHA3
* - For KECCAK SHA-3 padding - XSECURE_CSU_KECCAK_SHA3
*
* @return XST_SUCCESS if pad selection is successful.
* XST_FAILURE if pad selecction is failed.
*
* @note The default provides support for NIST SHA-3. If a user wants
* to change the padding to Keccak SHA-3, this function
* should be called after XSecure_Sha3Initialize()
*
******************************************************************************/
s32 XSecure_Sha3PadSelection(XSecure_Sha3 *InstancePtr,
XSecure_Sha3PadType Sha3PadType)
{
s32 Status;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((Sha3PadType == XSECURE_CSU_NIST_SHA3)
|| (Sha3PadType == XSECURE_CSU_KECCAK_SHA3));
Xil_AssertNonvoid((InstancePtr->Sha3State == XSECURE_SHA3_INITIALIZED) ||
(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED));
/* If operation is in between can't be modified */
if (InstancePtr->Sha3Len != 0x00U) {
Status = (s32)XST_FAILURE;
goto END;
}
InstancePtr->Sha3PadType = Sha3PadType;
Status = XST_SUCCESS;
END:
return Status;
}
/****************************************************************************/
/**
* @brief
* This function is to notify this is the last update of data where sha padding
* is also been included along with the data in the next update call.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
*
* @return XST_SUCCESS if last update can be accepted
*
*
*****************************************************************************/
s32 XSecure_Sha3LastUpdate(XSecure_Sha3 *InstancePtr)
{
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED);
InstancePtr->IsLastUpdate = TRUE;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* @brief
* This function generates padding for the SHA-3 engine.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Dst Pointer to location where padding is to be applied.
* @param MsgLen Length of padding in bytes.
*
* @return None
*
******************************************************************************/
static void XSecure_Sha3KeccakPadd(XSecure_Sha3 *InstancePtr, u8 *Dst,
u32 MsgLen)
{
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsgLen != 0U);
(void)memset(Dst, 0, MsgLen);
Dst[0] = XSECURE_CSU_SHA3_START_KECCAK_PADDING_MASK;
Dst[MsgLen -1U] |= XSECURE_CSU_SHA3_END_KECCAK_PADDING_MASK;
}
/*****************************************************************************/
/**
* Generate padding for the NIST SHA-3
*
* @param InstancePtr is a pointer to the XSecure_Sha3 instance.
* @param Dst is the pointer to location where padding is to be applied
* @param MsgLen is the length of padding in bytes
*
* @return None
*
* @note None
*
******************************************************************************/
static void XSecure_Sha3NistPadd(XSecure_Sha3 *InstancePtr, u8 *Dst, u32 MsgLen)
{
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsgLen != 0U);
(void)memset(Dst, 0, MsgLen);
Dst[0] = XSECURE_CSU_SHA3_START_NIST_PADDING_MASK;
Dst[MsgLen -1U] |= XSECURE_CSU_SHA3_END_NIST_PADDING_MASK;
}
/*****************************************************************************/
/**
* @brief
* This function configures Secure Stream Switch and starts the SHA-3 engine.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
*
* @return None
*
*
******************************************************************************/
void XSecure_Sha3Start(XSecure_Sha3 *InstancePtr)
{
/* Asserts validate the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->Sha3State == XSECURE_SHA3_INITIALIZED);
InstancePtr->Sha3Len = 0U;
InstancePtr->IsLastUpdate = FALSE;
InstancePtr->PartialLen = 0U;
(void)memset(InstancePtr->PartialData, 0, XSECURE_SHA3_BLOCK_LEN);
/* Reset SHA3 engine. */
XSecure_ReleaseReset(InstancePtr->BaseAddress,
XSECURE_CSU_SHA3_RESET_OFFSET);
/* Start SHA3 engine. */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_SHA3_START_OFFSET,
XSECURE_CSU_SHA3_START_START);
InstancePtr->Sha3State = XSECURE_SHA3_ENGINE_STARTED;
}
/*****************************************************************************/
/**
* @brief
* This function updates the SHA3 engine with the input data.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Data Pointer to the input data for hashing.
* @param Size Size of the input data in bytes.
*
* @return XST_SUCCESS if the update is successful
* XST_FAILURE if there is a failure in SSS config
*
******************************************************************************/
u32 XSecure_Sha3Update(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size)
{
u32 DataSize;
u32 TransferredBytes;
u32 Status = (u32)XST_FAILURE;
/* Asserts validate the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED);
InstancePtr->Sha3Len += Size;
DataSize = Size;
TransferredBytes = 0U;
/*
* CSU DMA can transfer Max 0x7FFFFFF no of words(0x1FFFFFFC bytes)
* at a time .So if the data sent more than that will be handled
* in the next update internally
*/
while (DataSize > XSECURE_CSU_DMA_MAX_TRANSFER) {
Status = XSecure_Sha3DataUpdate(InstancePtr,
(Data + TransferredBytes),
XSECURE_CSU_DMA_MAX_TRANSFER, 0);
if (Status != (u32)XST_SUCCESS){
goto END;
}
DataSize = DataSize - XSECURE_CSU_DMA_MAX_TRANSFER;
TransferredBytes = TransferredBytes +
XSECURE_CSU_DMA_MAX_TRANSFER;
}
Status = XSecure_Sha3DataUpdate(InstancePtr, (Data + TransferredBytes),
DataSize, (u8)InstancePtr->IsLastUpdate);
END:
if (Status != XST_SUCCESS) {
/* Set SHA under reset on failure condition */
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_CSU_SHA3_RESET_OFFSET);
InstancePtr->Sha3State = XSECURE_SHA3_INITIALIZED;
}
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function updates SHA3 engine with final data which includes SHA3
* padding and reads final hash on complete data.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Hash Pointer to location where resulting hash will
* be written
*
* @return XST_SUCCESS if finished without any errors
* XST_FAILURE if Sha3PadType is other than KECCAK or NIST
*
*****************************************************************************/
u32 XSecure_Sha3Finish(XSecure_Sha3 *InstancePtr, u8 *Hash)
{
u32 PadLen;
u32 Status = (u32)XST_FAILURE;
u32 Size;
/* Asserts validate the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Hash != NULL);
Xil_AssertNonvoid(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED);
PadLen = InstancePtr->Sha3Len % XSECURE_SHA3_BLOCK_LEN;
if (InstancePtr->IsLastUpdate != TRUE) {
PadLen = (PadLen == 0U)?(XSECURE_SHA3_BLOCK_LEN) :
(XSECURE_SHA3_BLOCK_LEN - PadLen);
if (InstancePtr->Sha3PadType == XSECURE_CSU_NIST_SHA3) {
XSecure_Sha3NistPadd(InstancePtr,
&InstancePtr->PartialData[InstancePtr->PartialLen],
PadLen);
}
else {
XSecure_Sha3KeccakPadd(InstancePtr,
&InstancePtr->PartialData[InstancePtr->PartialLen],
PadLen);
}
Size = PadLen + InstancePtr->PartialLen;
Status = XSecure_Sha3DmaTransfer(InstancePtr,
(u8*)InstancePtr->PartialData,
Size, 1U);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
}
else {
Size = InstancePtr->PartialLen;
if (Size != 0x0U) {
Status = XST_FAILURE;
goto END;
}
}
/* Check the SHA3 DONE bit. */
Status = XSecure_Sha3WaitForDone(InstancePtr);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* If requested, read out the Hash in reverse order. */
if (Hash != NULL)
{
XSecure_Sha3_ReadHash(InstancePtr, Hash);
}
END:
if (Size > 0X0U) {
(void)memset((void*)InstancePtr->PartialData, 0, Size);
}
/* Set SHA under reset */
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_CSU_SHA3_RESET_OFFSET);
InstancePtr->Sha3State = XSECURE_SHA3_INITIALIZED;
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function calculates the SHA-3 digest on the given input data.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param In Pointer to the input data for hashing
* @param Size Size of the input data
* @param Out Pointer to location where resulting hash will
* be written.
*
* @return XST_SUCCESS if digest calculation done successfully
* XST_FAILURE if any error from Sha3Update or Sha3Finish.
*
******************************************************************************/
u32 XSecure_Sha3Digest(XSecure_Sha3 *InstancePtr, const u8 *In, const u32 Size,
u8 *Out)
{
u32 Status = (u32)XST_FAILURE;
/* Asserts validate the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Out != NULL);
XSecure_Sha3Start(InstancePtr);
Status = XSecure_Sha3Update(InstancePtr, In, Size);
if (Status != (u32)XST_SUCCESS){
goto END;
}
Status = XSecure_Sha3Finish(InstancePtr, Out);
if (Status != (u32)XST_SUCCESS){
goto END;
}
END:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function reads the SHA3 hash of the data and it can be called
* between calls to XSecure_Sha3Update.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Hash Pointer to a buffer in which read hash will be
* stored.
*
* @return None
*
******************************************************************************/
void XSecure_Sha3_ReadHash(XSecure_Sha3 *InstancePtr, u8 *Hash)
{
u32 Index;
u32 RegVal;
u32 *HashPtr = (u32 *)Hash;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Hash != NULL);
Xil_AssertVoid(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED);
for (Index = 0U; Index < XSECURE_CSU_SHA3_HASH_LENGTH_IN_WORDS; Index++)
{
RegVal = XSecure_ReadReg(InstancePtr->BaseAddress,
XSECURE_CSU_SHA3_DIGEST_0_OFFSET + (Index * 4U));
HashPtr[XSECURE_CSU_SHA3_HASH_LENGTH_IN_WORDS - Index - 1] = RegVal;
}
}
/*****************************************************************************/
/**
* @brief
* This function Transfers Data through Dma
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Data Pointer to the input data need to be transferred.
* @param Size Size of the input data in bytes.
*
* @return None
*
*
******************************************************************************/
static u32 XSecure_Sha3DmaTransfer(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size, u8 IsLast)
{
u32 Status = (u32)XST_FAILURE;
/* Asserts validate the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Configure the SSS for SHA3 hashing. */
Status = XSecure_SssSha(&(InstancePtr->SssInstance),
InstancePtr->CsuDmaPtr->Config.DeviceId);
if (Status != (u32)XST_SUCCESS){
goto ENDF;
}
XCsuDma_Transfer(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL,
(UINTPTR)Data, (u32)Size/4U, IsLast);
/* Checking the CSU DMA done bit should be enough. */
Status = XCsuDma_WaitForDoneTimeout(InstancePtr->CsuDmaPtr,
XCSUDMA_SRC_CHANNEL);
if (Status != (u32)XST_SUCCESS) {
goto ENDF;
}
/* Acknowledge the transfer has completed */
XCsuDma_IntrClear(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL,
XCSUDMA_IXR_DONE_MASK);
ENDF:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function updates hash for data block of size <= 512MB.
*
* @param InstancePtr Pointer to the XSecure_Sha3 instance.
* @param Data Pointer to the input data for hashing.
* @param Size Size of the input data in bytes.
*
* @return None
*
*
******************************************************************************/
static u32 XSecure_Sha3DataUpdate(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size, u8 IsLastUpdate)
{
u32 RemainingDataLen;
u32 DmableDataLen;
const u8 *DmableData;
u8 IsLast;
u32 Status = (u32)XST_FAILURE;
u32 PrevPartialLen;
u8 *PartialData;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->Sha3State == XSECURE_SHA3_ENGINE_STARTED);
PrevPartialLen = InstancePtr->PartialLen;
PartialData = InstancePtr->PartialData;
RemainingDataLen = Size + PrevPartialLen;
IsLast = FALSE;
while(RemainingDataLen >= XSECURE_SHA3_BLOCK_LEN)
{
/* Handle Partial data and non dword aligned data address */
if ((PrevPartialLen != 0U) ||
(((UINTPTR)Data & XCSUDMA_ADDR_LSB_MASK) != 0U)) {
XSecure_MemCpy((void *)&PartialData[PrevPartialLen],
(void *)Data,
XSECURE_SHA3_BLOCK_LEN - PrevPartialLen);
DmableData = PartialData;
DmableDataLen = XSECURE_SHA3_BLOCK_LEN;
Data += XSECURE_SHA3_BLOCK_LEN - PrevPartialLen;
RemainingDataLen = RemainingDataLen - DmableDataLen;
}
else {
/* Process data of size in multiple of dwords */
DmableData = Data;
DmableDataLen = RemainingDataLen -
(RemainingDataLen % XSECURE_SHA3_BLOCK_LEN);
Data += DmableDataLen;
RemainingDataLen -= DmableDataLen;
}
if ((RemainingDataLen == 0U) && (IsLastUpdate == TRUE)) {
IsLast = TRUE;
}
Status = XSecure_Sha3DmaTransfer(InstancePtr, DmableData,
DmableDataLen, IsLast);
if (Status != (u32)XST_SUCCESS){
(void)memset(&InstancePtr->PartialData, 0,
sizeof(InstancePtr->PartialData));
goto END;
}
PrevPartialLen = 0U;
}
/* Handle remaining data during processing of next data chunk or during
data padding */
if(RemainingDataLen > 0U) {
XSecure_MemCpy((void *)(PartialData + PrevPartialLen), (void *)Data,
(RemainingDataLen - PrevPartialLen));
}
InstancePtr->PartialLen = RemainingDataLen;
(void)memset(&InstancePtr->PartialData[RemainingDataLen], 0,
sizeof(InstancePtr->PartialData) - RemainingDataLen);
Status = (u32) XST_SUCCESS;
END:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/ipipsu_v2_6/src/xipipsu_buf.c
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xipipsu_buf.c
* @addtogroup ipipsu_v2_6
* @{
*
* This file contains the implementation of the buffer access functions for XIpiPsu
* driver. Refer to the header file xipipsu_buf.h for more detailed information.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ----------------------------------------------
* 2.6 sd 04/02/20 Restructured the code for more readability and modularity
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xipipsu.h"
#include "xipipsu_hw.h"
#include "xipipsu_buf.h"
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
* @brief Get the Buffer Index for a CPU specified by Mask
*
* @param InstancePtr is the pointer to current IPI instance
* @param CpuMask is the Mask of the CPU form which Index is required
*
* @return Buffer Index value if CPU Mask is valid
* XIPIPSU_MAX_BUFF_INDEX+1 if not valid
*
*/
u32 XIpiPsu_GetBufferIndex(const XIpiPsu *InstancePtr, u32 CpuMask)
{
u32 BufferIndex;
u32 Index;
/* Init Index with an invalid value */
BufferIndex = XIPIPSU_MAX_BUFF_INDEX + 1U;
/*Search for CPU in the List */
for (Index = 0U; Index < InstancePtr->Config.TargetCount; Index++) {
/*If we find the CPU , then set the Index and break the loop*/
if (InstancePtr->Config.TargetList[Index].Mask == CpuMask) {
BufferIndex = InstancePtr->Config.TargetList[Index].BufferIndex;
break;
}
}
/* Return the Index */
return BufferIndex;
}
/**
* @brief Get the Buffer Address for a given pair of CPUs
*
* @param InstancePtr is the pointer to current IPI instance
* @param SrcCpuMask is the Mask for Source CPU
* @param DestCpuMask is the Mask for Destination CPU
* @param BufferType is either XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP
*
* @return Valid Buffer Address if no error
* NULL if an error occurred in calculating Address
*
*/
u32* XIpiPsu_GetBufferAddress(XIpiPsu *InstancePtr, u32 SrcCpuMask,
u32 DestCpuMask, u32 BufferType)
{
#ifdef __aarch64__
u64 BufferAddr;
#else
u32 BufferAddr;
#endif
u32 SrcIndex;
u32 DestIndex;
/* Get the buffer indices */
SrcIndex = XIpiPsu_GetBufferIndex(InstancePtr, SrcCpuMask);
DestIndex = XIpiPsu_GetBufferIndex(InstancePtr, DestCpuMask);
/* If we got an invalid buffer index, then return NULL pointer, else valid address */
if ((SrcIndex > XIPIPSU_MAX_BUFF_INDEX)
|| (DestIndex > XIPIPSU_MAX_BUFF_INDEX)) {
BufferAddr = 0U;
} else {
if (XIPIPSU_BUF_TYPE_MSG == BufferType) {
BufferAddr = XIPIPSU_MSG_RAM_BASE
+ (SrcIndex * XIPIPSU_BUFFER_OFFSET_GROUP)
+ (DestIndex * XIPIPSU_BUFFER_OFFSET_TARGET);
} else if (XIPIPSU_BUF_TYPE_RESP == BufferType) {
BufferAddr = XIPIPSU_MSG_RAM_BASE
+ (DestIndex * XIPIPSU_BUFFER_OFFSET_GROUP)
+ (SrcIndex * XIPIPSU_BUFFER_OFFSET_TARGET)
+ (XIPIPSU_BUFFER_OFFSET_RESPONSE);
} else {
BufferAddr = 0U;
}
}
return (u32 *) BufferAddr;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/qspipsu_v1_11/src/xqspipsu_control.c
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu_control.c
* @addtogroup qspipsu_v1_11
* @{
*
* This file contains intermediate control functions used by functions
* in xqspipsu.c and xqspipsu_options.c files.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.11 akm 03/09/20 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xqspipsu_control.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/*****************************************************************************/
/**
*
* This function writes the GENFIFO entries to transmit the messages requested.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
* @param Index of the current message to be handled.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if transfer fails.
* - XST_DEVICE_BUSY if a transfer is already in progress.
*
* @note None.
*
******************************************************************************/
void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg)
{
u32 GenFifoEntry;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_GenFifoEntryData\r\n");
#endif
GenFifoEntry = 0x0U;
/* Bus width */
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
GenFifoEntry |= XQspiPsu_SelectSpiMode((u8)Msg->BusWidth);
GenFifoEntry |= InstancePtr->GenFifoCS;
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
GenFifoEntry |= InstancePtr->GenFifoBus;
/* Data */
if (((Msg->Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != FALSE)
GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
else
GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
/* If Byte Count is less than 8 bytes do the transfer in IO mode */
if ((Msg->ByteCount < 8U) &&
(InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA)) {
InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
(XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) &
~XQSPIPSU_CFG_MODE_EN_MASK));
InstancePtr->IsUnaligned = 1;
}
XQspiPsu_TXRXSetup(InstancePtr, Msg, &GenFifoEntry);
XQspiPsu_GenFifoEntryDataLen(InstancePtr, Msg, &GenFifoEntry);
/* One dummy GenFifo entry in case of IO mode */
if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_IO) &&
((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
GenFifoEntry = 0x0U;
#ifdef DEBUG
xil_printf("\nDummy FifoEntry=%08x\r\n", GenFifoEntry);
#endif
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
}
}
/*****************************************************************************/
/**
*
* This function enables the polling functionality of controller
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
*
* @param Statuscommand is the status command which send by controller.
*
* @param FlashMsg is a pointer to the structure containing transfer data
*
* @return None
*
* @note None.
*
******************************************************************************/
void XQspiPsu_PollDataConfig(XQspiPsu *InstancePtr, XQspiPsu_Msg *FlashMsg)
{
u32 GenFifoEntry;
u32 Value;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FlashMsg != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_PollDataConfig\r\n");
#endif
Value = XQspiPsu_CreatePollDataConfig(InstancePtr, FlashMsg);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_POLL_CFG_OFFSET, Value);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_P_TO_OFFSET, FlashMsg->PollTimeout);
XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
GenFifoEntry = (u32)0;
GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_TX;
GenFifoEntry |= InstancePtr->GenFifoBus;
GenFifoEntry |= InstancePtr->GenFifoCS;
GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_MODE_SPI;
GenFifoEntry |= (u32)FlashMsg->PollStatusCmd;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
GenFifoEntry = (u32)0;
GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_POLL;
GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_RX;
GenFifoEntry |= InstancePtr->GenFifoBus;
GenFifoEntry |= InstancePtr->GenFifoCS;
GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_MODE_SPI;
if (((FlashMsg->Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != FALSE)
GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
else
GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
GenFifoEntry);
/* One Dummy entry required for IO mode */
GenFifoEntry = 0x0U;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
GenFifoEntry);
InstancePtr->Msg = FlashMsg;
InstancePtr->NumMsg = (s32)1;
InstancePtr->MsgCnt = 0;
Value = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
Value &= ~XQSPIPSU_CFG_MODE_EN_MASK;
Value |= (XQSPIPSU_CFG_START_GEN_FIFO_MASK |
XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK |
XQSPIPSU_CFG_EN_POLL_TO_MASK);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
Value);
/* Enable interrupts */
Value = ((u32)XQSPIPSU_IER_RXNEMPTY_MASK |
(u32)XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_IER_OFFSET,
Value);
}
#if defined (ARMR5) || (__aarch64__)
/*****************************************************************************/
/**
*
* Configures the clock according to the prescaler passed.
*
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Prescaler - clock prescaler.
*
* @return
* - XST_SUCCESS if successful.
* - XST_DEVICE_BUSY if the device is currently transferring data.
* The transfer must complete or be aborted before setting Tapdelay.
*
* @note None.
*
******************************************************************************/
s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler)
{
u32 FreqDiv, Divider;
u32 Tapdelay = 0;
u32 LBkModeReg = 0;
u32 delayReg = 0;
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Prescaler <= XQSPIPSU_CR_PRESC_MAXIMUM);
/*
* Do not allow the slave select to change while a transfer is in
* progress. Not thread-safe.
*/
if (InstancePtr->IsBusy == TRUE) {
Status = (s32)XST_DEVICE_BUSY;
goto END;
} else {
Divider = (1U << (Prescaler+1U));
FreqDiv = (InstancePtr->Config.InputClockHz)/Divider;
#if defined (versal)
if (FreqDiv <= XQSPIPSU_FREQ_37_5MHZ) {
#else
if (FreqDiv <= XQSPIPSU_FREQ_40MHZ) {
#endif
Tapdelay |= (TAPDLY_BYPASS_VALVE_40MHZ <<
IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
} else if (FreqDiv <= XQSPIPSU_FREQ_100MHZ) {
Tapdelay |= (TAPDLY_BYPASS_VALVE_100MHZ <<
IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
LBkModeReg |= (USE_DLY_LPBK << XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT);
#if defined (versal)
delayReg |= USE_DATA_DLY_ADJ <<
XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT;
#else
delayReg |= (USE_DATA_DLY_ADJ <<
XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT) |
(DATA_DLY_ADJ_DLY << XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT);
#endif
} else if (FreqDiv <= XQSPIPSU_FREQ_150MHZ) {
#if defined (versal)
LBkModeReg |= (USE_DLY_LPBK << XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT) |
(LPBK_DLY_ADJ_DLY1 << XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT);
#else
LBkModeReg |= USE_DLY_LPBK << XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT;
#endif
} else {
Status = XST_FAILURE;
goto END;
}
Status = XQspipsu_Set_TapDelay(InstancePtr, Tapdelay, LBkModeReg, delayReg);
END:
return Status;
}
}
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_core.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* This file contains implementation of the PM API functions, which
* should be used directly only by power management itself.
*********************************************************************/
#include "csu.h"
#include "pm_core.h"
#include "pm_node.h"
#include "pm_proc.h"
#include "pm_defs.h"
#include "pm_common.h"
#include "pm_callbacks.h"
#include "pm_reset.h"
#include "pm_notifier.h"
#include "pm_mmio_access.h"
#include "pm_system.h"
#include "pm_pinctrl.h"
#ifdef ENABLE_FPGA_LOAD
#include "xilfpga.h"
#endif
#include "pm_clock.h"
#include "pm_requirement.h"
#include "pm_config.h"
#include "xpfw_platform.h"
#include "xpfw_resets.h"
#include "rpu.h"
#ifdef ENABLE_SECURE
#include "xsecure.h"
#include "xilskey_eps_zynqmp_puf.h"
#endif
#ifdef EFUSE_ACCESS
#include "xilskey_eps_zynqmp.h"
#endif
#include "pmu_iomodule.h"
#include "xpfw_ipi_manager.h"
#include "xpfw_restart.h"
#ifdef ENABLE_WDT
#include "xpfw_mod_wdt.h"
#endif
#define AES_PUF_KEY_SEL_MASK 0x2U
#define INVALID_ACK_ARG(a) ((a < REQUEST_ACK_MIN) || (a > REQUEST_ACK_MAX))
/*
* PM error numbers, mostly used to identify erroneous usage of EEMI. Note:
* these errors are errors from the perspective of using EEMI API. PMU-FW
* is robust and deals properly with those errors (do not affect its internal
* operations). Standard XStatus is not used for this purpose because these
* error codes are more detailed and used for logging/optimizing prints
*/
#define PM_ERRNO_INVALID_NODE 1U
#define PM_ERRNO_INVALID_ACK 2U
#define PM_ERRNO_NO_PERMISSION 3U
#define PM_ERRNO_NO_WR_PERMISSION 4U
#define PM_ERRNO_NO_RD_PERMISSION 5U
#define PM_ERRNO_NO_RESET_PERMISSION 6U
#define PM_ERRNO_NO_ADDRESS 7U
#define PM_ERRNO_NO_REQUEST 8U
#define PM_ERRNO_DOUBLE_REQUEST 9U
#define PM_ERRNO_INVALID_LATENCY 10U
#define PM_ERRNO_INVALID_TYPE 11U
#define PM_ERRNO_INVALID_SUBTYPE 12U
#define PM_ERRNO_INVALID_RESET 13U
#define PM_ERRNO_NO_TEMP_SUPPORT 14U
#if defined(PM_LOG_LEVEL) && (PM_LOG_LEVEL >= PM_WARNING)
#define PmLog(errno, value, mst) \
PmLogInt(__LINE__, errno, value, mst)
/**
* PmLogInt() - Log an error related to EEMI usage
* @line Line in this file where the error is logged
* @errno Error code
* @value Additional information about the error (an integer)
* @mst Name of the master who issued the EEMI API
*/
static void PmLogInt(const u32 line, const u32 errno, const u32 value,
const char* const mst)
{
pm_printf("pm_core.c@%lu %s> ", line, mst);
switch (errno) {
case PM_ERRNO_INVALID_NODE:
PmWarn("Invalid node %lu\r\n", value);
break;
case PM_ERRNO_INVALID_ACK:
PmWarn("Invalid ack %lu\r\n", value);
break;
case PM_ERRNO_NO_PERMISSION:
PmWarn("No permission\r\n");
break;
case PM_ERRNO_NO_WR_PERMISSION:
PmWarn("No write permission to 0x%lx\r\n", value);
break;
case PM_ERRNO_NO_RD_PERMISSION:
PmWarn("No read permission to 0x%lx\r\n", value);
break;
case PM_ERRNO_NO_RESET_PERMISSION:
PmWarn("No reset %lu permission\r\n", value);
break;
case PM_ERRNO_NO_ADDRESS:
PmWarn("Address not provided\r\n");
break;
case PM_ERRNO_NO_REQUEST:
PmWarn("Node %d not requested\r\n", value);
break;
case PM_ERRNO_DOUBLE_REQUEST:
PmWarn("Node %d already requested\r\n", value);
break;
case PM_ERRNO_INVALID_LATENCY:
PmWarn("Invalid latency! Try > %lu\r\n", value);
break;
case PM_ERRNO_INVALID_SUBTYPE:
PmWarn("Invalid subtype %lu\r\n", value);
break;
case PM_ERRNO_INVALID_TYPE:
PmWarn("Invalid type %lu\r\n", value);
break;
case PM_ERRNO_INVALID_RESET:
PmWarn("Invalid reset %lu\r\n", value);
break;
case PM_ERRNO_NO_TEMP_SUPPORT:
PmWarn("Temperature not supported\r\n");
break;
default:
break;
}
}
#else
#define PmLog(errno, value, mst) {}
#endif
/**
* PmKillBoardPower() - Power-off board by sending KILL signal to power chip
*/
#if defined(BOARD_SHUTDOWN_PIN) && defined(BOARD_SHUTDOWN_PIN_STATE)
static void PmKillBoardPower(void)
{
u32 reg = XPfw_Read32(PMU_LOCAL_GPO1_READ);
u32 mask = PMU_IOMODULE_GPO1_MIO_0_MASK << BOARD_SHUTDOWN_PIN;
u32 value = BOARD_SHUTDOWN_PIN_STATE << BOARD_SHUTDOWN_PIN;
u32 mioPinOffset;
mioPinOffset = IOU_SLCR_MIO_PIN_34_OFFSET + (BOARD_SHUTDOWN_PIN - 2U)*4U;
reg = (reg & (~mask)) | (mask & value);
XPfw_Write32(PMU_IOMODULE_GPO1, reg);
/* Configure board shutdown pin to be controlled by the PMU */
XPfw_RMW32((IOU_SLCR_BASE + mioPinOffset),
0x000000FEU, 0x00000008U);
}
#endif
/**
* PmProcessAckRequest() -Returns appropriate acknowledge if required
* @ack Ack argument as requested by the master
* @master IPI channel to use
* @nodeId Node ID of requesting PU
* @status Status of PM's operation
* @oppoint Operating point of node in question
*/
static void PmProcessAckRequest(const u32 ack,
const PmMaster* const master,
const PmNodeId nodeId,
const u32 status,
const u32 oppoint)
{
if (REQUEST_ACK_BLOCKING == ack) {
/* Return status immediately */
IPI_RESPONSE1(master->ipiMask, status);
} else if (REQUEST_ACK_NON_BLOCKING == ack) {
/* Return acknowledge through callback */
PmAcknowledgeCb(master, nodeId, status, oppoint);
} else {
/* No returning of the acknowledge */
}
}
/**
* PmSelfSuspend() - Requested self suspend for a processor
* @master Master who initiated the request
* @node Processor or subsystem node to be suspended
* @latency Maximum latency for processor to go back to active state
* @state Encoded state that is specific for each master
*
* @note Used to announce starting of self suspend procedure. Node will be
* put to sleep when server handles corresponding processor's WFI
* interrupt.
*/
static void PmSelfSuspend(const PmMaster *const master,
const u32 node,
const u32 latency,
const u32 state,
const u64 address)
{
s32 status;
u32 worstCaseLatency = 0U;
/* the node ID must refer to a processor belonging to this master */
PmProc* proc = PmGetProcOfThisMaster(master, node);
PmInfo("%s> SelfSuspend(%lu, %lu, %lu, 0x%llx)\r\n", master->name, node,
latency, state, address);
if (NULL == proc) {
PmLog(PM_ERRNO_INVALID_NODE, node, master->name);
status = XST_INVALID_PARAM;
goto done;
}
worstCaseLatency = proc->pwrDnLatency + proc->pwrUpLatency;
if (latency < worstCaseLatency) {
PmLog(PM_ERRNO_INVALID_LATENCY, worstCaseLatency, master->name);
status = XST_INVALID_PARAM;
goto done;
}
/* Remember latency requirement */
proc->latencyReq = latency;
status = proc->saveResumeAddr(proc, address);
if (XST_SUCCESS != status) {
goto done;
}
status = PmProcFsm(proc, PM_PROC_EVENT_SELF_SUSPEND);
if (XST_SUCCESS != status) {
goto done;
}
if (NULL != master->evalState) {
status = master->evalState(state);
}
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmRequestSuspend() - Requested suspend by a PU for another PU
* @master PU from which the request is initiated
* @node PU node to be suspended
* @ack Acknowledge request
* @latency Desired wakeup latency
* @state Desired power state
*
* If suspend has been successfully requested, the requested PU needs to
* initiate its own self suspend. Remember to acknowledge to the requestor
* after:
* 1. PU's last awake processor goes to sleep (self suspend completed),
* 2. PU/processor aborts suspend,
* 3. PU/processor does not respond to the request (timeout) - not supported
*/
static void PmRequestSuspend(const PmMaster *const master,
const u32 node,
const u32 ack,
const u32 latency,
const u32 state)
{
s32 status = XST_SUCCESS;
PmMaster* target = NULL;
PmInfo("%s> RequestSuspend(%lu, %lu, %lu, %lu)\r\n", master->name, node,
ack, latency, state);
/* Only these two acknowledges are allowed for request suspend */
if (REQUEST_ACK_NO != ack && REQUEST_ACK_NON_BLOCKING != ack) {
PmLog(PM_ERRNO_INVALID_ACK, ack, master->name);
status = XST_INVALID_PARAM;
goto done;
}
/* Check whether the target is placeholder in PU */
target = PmMasterGetPlaceholder(node);
if (NULL == target) {
PmLog(PM_ERRNO_INVALID_NODE, node, master->name);
status = XST_INVALID_PARAM;
goto done;
}
if (false == PmCanRequestSuspend(master, target)) {
PmLog(PM_ERRNO_NO_PERMISSION, 0U, master->name);
status = XST_PM_NO_ACCESS;
goto done;
}
if (true == PmIsRequestedToSuspend(target)) {
status = XST_PM_DOUBLE_REQ;
goto done;
}
/* If target master cannot receive callback return failure */
if (false == PmMasterCanReceiveCb(target)) {
status = XST_FAILURE;
goto done;
}
/* Remember request info and init suspend */
target->suspendRequest.initiator = master;
target->suspendRequest.acknowledge = ack;
PmInitSuspendCb(target, SUSPEND_REASON_PU_REQ, latency, state, 0U);
done:
if (XST_SUCCESS != status) {
/* Something went wrong, acknowledge immediately */
PmProcessAckRequest(ack, master, node, status, 0U);
}
}
/**
* PmForcePowerdown() - Powerdown a PU or domain forcefully
* @master Master who initiated the request
* @node Processor, subsystem or domain node to be powered down
* @ack Acknowledge request
*
* @note The affected PUs are not notified about the upcoming powerdown,
* and PMU does not wait for their WFI interrupt.
* Admissible nodes are :
* 1. Processor nodes (RPU0..1, APU0..3, and in future: PL Procs)
* 2. Parent nodes (APU, RPU, FPD, and in future PL)
*/
static void PmForcePowerdown(const PmMaster *const master,
const u32 node,
const u32 ack)
{
u32 oppoint = 0U;
s32 status;
PmNode* nodePtr = PmGetNodeById(node);
PmPower *power;
if (NULL == nodePtr || INVALID_ACK_ARG(ack)) {
status = XST_INVALID_PARAM;
goto done;
}
if (NODE_IS_POWER(nodePtr)) {
power = (PmPower*)nodePtr->derived;
} else if (NODE_IS_PROC(nodePtr)) {
PmProc* proc = (PmProc*)nodePtr->derived;
power = (PmPower*)proc->node.parent;
/* Master can't force off its proc. */
if (proc->master->nid == master->nid) {
status = XST_PM_NO_ACCESS;
goto done;
}
} else {
/* Slaves and PLLs can not be force power down */
status = XST_INVALID_PARAM;
goto done;
}
if (false == PmMasterCanForceDown(master, power)) {
status = XST_PM_NO_ACCESS;
goto done;
}
status = PmNodeForceDown(nodePtr);
oppoint = nodePtr->currState;
done:
PmProcessAckRequest(ack, master, node, status, oppoint);
}
/**
* PmAbortSuspend() - Abort previously requested suspend
* @master Master who initiated the request
* @reason Reason of aborting suspend
* @node Node ID of processor node to abort suspend for
*
* @note Only processor within the master can initiate its own abortion of
* suspend.
*/
static void PmAbortSuspend(const PmMaster *const master,
const u32 reason,
const u32 node)
{
s32 status;
PmProc* proc = PmGetProcOfThisMaster(master, node);
PmInfo("%s> AbortSuspend(%lu, %lu)\r\n", master->name, node, reason);
if (NULL == proc) {
PmLog(PM_ERRNO_INVALID_NODE, node, master->name);
status = XST_PM_INVALID_NODE;
goto done;
}
if ((reason < ABORT_REASON_MIN) || (reason > ABORT_REASON_MAX)) {
status = XST_INVALID_PARAM;
goto done;
}
status = PmProcFsm(proc, PM_PROC_EVENT_ABORT_SUSPEND);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmRequestWakeup() - Power-up processor or subsystem
* @master Master who initiated the request
* @node Processor or subsystem node to be powered up
* @ack Acknowledge request
*/
static void PmRequestWakeup(const PmMaster *const master, const u32 node,
const u32 setAddress, const u64 address,
const u32 ack)
{
s32 status;
u32 oppoint = 0U;
PmProc* proc = (PmProc*)PmNodeGetProc(node);
PmInfo("%s> RequestWakeup(%lu, %lu, %llu, %lu)\r\n", master->name, node,
setAddress, address, ack);
if ((NULL == proc) || (NULL == proc->master)) {
PmLog(PM_ERRNO_INVALID_NODE, node, master->name);
status = XST_PM_INVALID_NODE;
goto done;
}
if (INVALID_ACK_ARG(ack)) {
status = XST_INVALID_PARAM;
goto done;
}
if ((false == PmMasterCanRequestWake(master, proc->master)) &&
(master != proc->master)) {
PmLog(PM_ERRNO_NO_PERMISSION, 0U, master->name);
status = XST_PM_NO_ACCESS;
goto done;
}
if (1U == setAddress) {
proc->saveResumeAddr(proc, address);
} else {
if (false == PmProcHasResumeAddr(proc)) {
PmLog(PM_ERRNO_NO_ADDRESS, 0U, master->name);
status = XST_INVALID_PARAM;
goto done;
}
}
status = PmMasterWakeProc(proc);
oppoint = proc->node.currState;
done:
PmProcessAckRequest(ack, master, node, status, oppoint);
}
/**
* PmReleaseNode() - Release a slave node
* @master Master who initiated the request
* @node Node to be released
*
* @note Node to be released must have been requested before
*/
static void PmReleaseNode(const PmMaster *master,
const u32 node)
{
s32 status;
u32 usage;
PmRequirement* masterReq;
PmSlave* slave;
/* Check if node is slave. If it is, handle request via requirements */
slave = (PmSlave*)PmNodeGetSlave(node);
if (NULL == slave) {
status = XST_INVALID_PARAM;
goto done;
}
/* Get static requirements structure for this master/slave pair */
masterReq = PmRequirementGet(master, slave);
if (NULL == masterReq) {
PmLog(PM_ERRNO_NO_PERMISSION, 0U, master->name);
status = XST_PM_NO_ACCESS;
goto done;
}
if (!MASTER_REQUESTED_SLAVE(masterReq)) {
PmLog(PM_ERRNO_NO_REQUEST, node, master->name);
status = XST_FAILURE;
goto done;
}
/* Release requirements */
status = PmRequirementRelease(masterReq, RELEASE_ONE);
usage = PmSlaveGetUsersMask(masterReq->slave);
if (0U == usage) {
PmNotifierEvent(&masterReq->slave->node, EVENT_ZERO_USERS);
}
done:
PmInfo("%s> ReleaseNode(%lu)\r\n", master->name, node);
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmRequestNode() - Request to use a slave node
* @master Master who initiated the request
* @node Node requested
* @capabilities Requested capabilities
* @qos Requested quality of service - Not supported
* @ack Acknowledge request
*/
static void PmRequestNode(const PmMaster *master,
const u32 node,
const u32 capabilities,
const u32 qos,
const u32 ack)
{
s32 status;
u32 oppoint = 0U;
PmRequirement* masterReq;
PmSlave* slave;
PmInfo("%s> RequestNode(%lu, %lu, %lu, %lu)\r\n", master->name, node,
capabilities, qos, ack);
/* Check if node is slave. If it is, handle request via requirements */
slave = (PmSlave*)PmNodeGetSlave(node);
if (NULL == slave || INVALID_ACK_ARG(ack)) {
status = XST_INVALID_PARAM;
goto done;
}
/*
* Each legal master/slave pair will have one static PmRequirement data
* structure. Retrieve the pointer to the structure in order to set the
* requested capabilities and mark slave as used by this master.
*/
masterReq = PmRequirementGet(master, slave);
if (NULL == masterReq) {
/* Master is not allowed to use the slave with given node */
PmLog(PM_ERRNO_NO_PERMISSION, 0U, master->name);
status = XST_PM_NO_ACCESS;
goto done;
}
if (MASTER_REQUESTED_SLAVE(masterReq)) {
PmLog(PM_ERRNO_DOUBLE_REQUEST, node, master->name);
status = XST_PM_DOUBLE_REQ;
goto done;
}
status = PmSlaveVerifyRequest(masterReq->slave);
if (XST_SUCCESS != status) {
goto done;
}
/* Set requested capabilities if they are valid */
status = PmRequirementRequest(masterReq, capabilities);
done:
PmProcessAckRequest(ack, master, node, status, oppoint);
}
/**
* PmSetRequirement() - Setting requement for a slave
* @master Master who initiated the request
* @node Node whose requirements setting is requested
* @capabilities Requested capabilities
* @qos Requested quality of service - Not supported
* @ack Acknowledge request
*
* @note If processor which initiated request is in suspending state,
* requirement will be set once PMU handles processor's WFI
* interrupt. If processor is active, setting is done
* immediately (if possible).
*/
static void PmSetRequirement(const PmMaster *master,
const u32 node,
const u32 capabilities,
const u32 qos,
const u32 ack)
{
s32 status;
u32 oppoint = 0U;
u32 caps = capabilities;
PmRequirement* masterReq;
PmSlave* slave = (PmSlave*)PmNodeGetSlave(node);
PmInfo("%s> SetRequirement(%lu, %lu, %lu, %lu)\r\n", master->name, node,
capabilities, qos, ack);
/* Set requirement call applies only to slaves */
if (NULL == slave || INVALID_ACK_ARG(ack)) {
status = XST_INVALID_PARAM;
goto done;
}
/* Is there a provision for the master to use the given slave node */
masterReq = PmRequirementGet(master, slave);
if (NULL == masterReq) {
status = XST_PM_NO_ACCESS;
goto done;
}
/* Check if master has previously requested the node */
if (!MASTER_REQUESTED_SLAVE(masterReq)) {
status = XST_PM_NO_ACCESS;
goto done;
}
/* If slave is set as wake source add the PM_CAP_WAKEUP flag */
if (0U != (PM_MASTER_WAKEUP_REQ_MASK & masterReq->info)) {
caps |= PM_CAP_WAKEUP;
}
/* Master is using slave (previously has requested node) */
if (true == PmMasterIsSuspending(master)) {
/* Schedule setting the requirement */
status = PmRequirementSchedule(masterReq, caps);
} else {
/* Set capabilities now - if they are valid */
status = PmRequirementUpdate(masterReq, caps);
}
oppoint = masterReq->slave->node.currState;
done:
PmProcessAckRequest(ack, master, node, status, oppoint);
}
/**
* PmGetApiVersion() - Provides API version number to the caller
* @master Master who initiated the request
*/
static void PmGetApiVersion(const PmMaster *const master)
{
u32 version = (PM_VERSION_MAJOR << 16U) | PM_VERSION_MINOR;
PmInfo("%s> GetApiVersion %d.%d\r\n", master->name, PM_VERSION_MAJOR,
PM_VERSION_MINOR);
IPI_RESPONSE2(master->ipiMask, XST_SUCCESS, version);
}
/**
* PmResetAssert() - Configure reset line
* @master Initiator of the request
* @reset ID of reset to be configured
* @action Specifies the action (assert, release, pulse)
*/
void PmResetAssert(const PmMaster *const master, const u32 reset,
const u32 action)
{
s32 status;
const PmReset *resetPtr = PmGetResetById(reset);
PmInfo("%s> ResetAssert(%lu, %lu)\r\n", master->name, reset, action);
if (NULL == resetPtr) {
PmLog(PM_ERRNO_INVALID_RESET, reset, master->name);
status = XST_INVALID_PARAM;
goto done;
}
/* Check whether the master has access to this reset line */
if (false == PmResetMasterHasAccess(master, resetPtr)) {
PmLog(PM_ERRNO_NO_RESET_PERMISSION, reset, master->name);
status = XST_PM_NO_ACCESS;
goto done;
}
status = PmResetDoAssert(resetPtr, action);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmResetGetStatus() - Get status of the reset
* @master Initiator of the request
* @reset Reset whose status should be returned
*/
static void PmResetGetStatus(const PmMaster *const master, const u32 reset)
{
u32 resetStatus = 0U;
s32 status = XST_SUCCESS;
const PmReset *resetPtr = PmGetResetById(reset);
PmInfo("%s> ResetGetStatus(%lu)\r\n", master->name, reset);
if (NULL == resetPtr) {
PmLog(PM_ERRNO_INVALID_RESET, reset, master->name);
status = XST_INVALID_PARAM;
goto done;
}
status = PmResetGetStatusInt(resetPtr, &resetStatus);
done:
IPI_RESPONSE2(master->ipiMask, status, resetStatus);
}
/**
* PmMmioWrite() - Perform write to protected mmio
* @master Master who initiated the request
* @address Address to write to
* @mask Mask to apply
* @value Value to write
*
* @note This function provides access to PM-related control registers
* that may not be directly accessible by a particular PU.
*/
static void PmMmioWrite(const PmMaster *const master, const u32 address,
const u32 mask, u32 value)
{
s32 status = XST_SUCCESS;
/* no bits to be updated */
if (0U == mask) {
goto done;
}
/* Check access permissions */
if (false == PmGetMmioAccessWrite(master, address)) {
PmLog(PM_ERRNO_NO_WR_PERMISSION, address, master->name);
status = XST_PM_NO_ACCESS;
goto done;
}
XPfw_RMW32(address, mask, value);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmMmioRead() - Read value from protected mmio
* @master Master who initiated the request
* @address Address to write to
*
* @note This function provides access to PM-related control registers
* that may not be directly accessible by a particular PU.
*/
static void PmMmioRead(const PmMaster *const master, const u32 address)
{
s32 status;
u32 value = 0;
/* Check access permissions */
if (false == PmGetMmioAccessRead(master, address)) {
PmLog(PM_ERRNO_NO_RD_PERMISSION, address, master->name);
status = XST_PM_NO_ACCESS;
goto done;
}
value = XPfw_Read32(address);
status = XST_SUCCESS;
done:
IPI_RESPONSE2(master->ipiMask, status, value);
}
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_FPGA_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT || \
XPFW_CFG_PMU_SHA3_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT || \
XPFW_CFG_PMU_RSA_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT || \
XPFW_CFG_PMU_AES_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT || \
XPFW_CFG_PMU_SECURE_IMG_LOAD_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
/* Notification IDs used to inform R5 about STL status
*
* STL will not run between notifications PM_NOTIFY_STL_NO_OP_ENTER &
* PM_NOTIFY_STL_NO_OP_EXIT
*
* PM_NOTIFY_STL_NO_OP_EXIT : STL is restored
* PM_NOTIFY_STL_NO_OP_ENTER : STL is stopped
*/
typedef enum {
PM_NOTIFY_STL_NO_OP_EXIT,
PM_NOTIFY_STL_NO_OP_ENTER
} PmR5StlNoOpNotification;
/**
* PmNotifyR5AndModifyWdtTimeout() - Notify R5 and modify watchdog timeout.
*
* Timeout: Watchdog Timeout value in ms
* Notification : Notification parameter
*
* @return None
*/
static void PmNotifyR5AndModifyWdtTimeout(u32 Timeout,
PmR5StlNoOpNotification Notification)
{
IPI_REQUEST2(IPI_PMU_0_IER_RPU_0_MASK, PM_NOTIFY_STL_NO_OP, Notification);
if (XST_SUCCESS != XPfw_IpiTrigger(IPI_PMU_0_IER_RPU_0_MASK)) {
PmWarn("Error in IPI trigger\r\n");
}
XPfw_WdtSetVal(Timeout);
}
#endif
#ifdef ENABLE_FPGA_LOAD
/**
* Pmfpgaload() - Load the bitstream into the PL.
* This function does the calls the necessary PCAP interfaces based on flags.
*
* AddrHigh: Higher 32-bit Linear memory space from where CSUDMA
* will read the data to be written to PCAP interface
*
* AddrLow: Lower 32-bit Linear memory space from where CSUDMA
* will read the data to be written to PCAP interface
*
* WrSize: Number of 32bit words that the DMA should write to
* the PCAP interface
*
* @return error status based on implemented functionality (SUCCESS by default)
*/
static void PmFpgaLoad(const PmMaster *const master,
const u32 AddrHigh, const u32 AddrLow,
const u32 KeyAddr, const u32 Flags)
{
u32 Status;
XFpga XFpgaInstance = {0U};
UINTPTR BitStreamAddr = ((u64)AddrHigh << 32)|AddrLow;
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_FPGA_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_FPGA_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_ENTER);
#endif
Status = XFpga_Initialize(&XFpgaInstance);
if (Status != XST_SUCCESS) {
goto done;
}
Status = XFpga_PL_BitStream_Load(&XFpgaInstance, BitStreamAddr,
KeyAddr, Flags);
if ((XST_SUCCESS == Status) && ((Flags & XFPGA_AUTHENTICATION_OCM_EN) ==
XFPGA_AUTHENTICATION_OCM_EN)) {
FSBL_Store_Restore_Info.IsOCM_Used = TRUE;
}
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_FPGA_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_EXIT);
#endif
done:
IPI_RESPONSE1(master->ipiMask, Status);
}
/**
* PmFpgaGetStatus() - Get status of the PL-block
* @master Initiator of the request
*/
static void PmFpgaGetStatus(const PmMaster *const master)
{
u32 Status;
u32 Value = 0;
XFpga XFpgaInstance = {0U};
Status = XFpga_Initialize(&XFpgaInstance);
if (Status != XST_SUCCESS) {
goto done;
}
Value = XFpga_InterfaceStatus(&XFpgaInstance);
if (Value == XFPGA_INVALID_INTERFACE_STATUS) {
Status = XST_FAILURE;
}
done:
IPI_RESPONSE2(master->ipiMask, Status, Value);
}
#if defined(ENABLE_FPGA_READ_CONFIG_DATA) || defined(ENABLE_FPGA_READ_CONFIG_REG)
/**
* PmFpgaRead() - Perform the FPGA configuration Read back
*
* Reg_Numframes: Configuration register offset (or) Number of frames to read
* AddrHigh: Higher 32-bit Linear memory space from where CSUDMA
* will read/write the data to the PCAP interface
* AddrLow: Lower 32-bit Linear memory space from where CSUDMA
* will read/write the data to the PCAP interface
* Readback_Type: Type of FPGA Read back operation
* 0 - Configuration Register Read back
* 1 - Configuration Data Read back
*
* @return error status based on implemented functionality(SUCCESS by default)
*/
static void PmFpgaRead(const PmMaster *const master,
const u32 Reg_Numframes, const u32 AddrLow,
const u32 AddrHigh, u32 Readback_Type)
{
u32 Status;
u32 Value = 0U;
XFpga XFpgaInstance = {0U};
UINTPTR Address = ((u64)AddrHigh << 32U)|AddrLow;
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_FPGA_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_FPGA_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_ENTER);
#endif
Status = XFpga_Initialize(&XFpgaInstance);
if (Status != XST_SUCCESS) {
goto done;
}
if (Readback_Type != 0U) {
#if defined(ENABLE_FPGA_READ_CONFIG_DATA)
Status = XFpga_GetPlConfigData(&XFpgaInstance, Address, Reg_Numframes);
#else
PmWarn("Unsupported EEMI API\r\n");
Status = XST_NO_ACCESS;
#endif
} else {
#if defined(ENABLE_FPGA_READ_CONFIG_REG)
Status = XFpga_GetPlConfigReg(&XFpgaInstance, Address, Reg_Numframes);
Value = *(UINTPTR *)Address;
#else
PmWarn("Unsupported EEMI API\r\n");
Status = XST_NO_ACCESS;
#endif
}
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_FPGA_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_EXIT);
#endif
done:
IPI_RESPONSE2(master->ipiMask, Status, Value);
}
#endif
#endif
#ifdef ENABLE_SECURE
/**
* PmSecureSha() - To calculate the SHA3 hash on the provided data.
*
* @SrcAddrHigh: Higher 32-bit Linear memory space from where data
* will be read.
*
* @SrcAddrLow: Lower 32-bit Linear memory space from where data
* will be read.
*
* @SrcSize: Number of bytes of data on which hash should be calculated
*
* @Flags: provides inputs for operation to be performed
*
* @return error status based on implemented functionality(SUCCESS by default)
*/
static void PmSecureSha(const PmMaster *const master,
const u32 SrcAddrHigh, const u32 SrcAddrLow,
const u32 SrcSize, const u32 Flags)
{
u32 Status;
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_SHA3_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_SHA3_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_ENTER);
#endif
Status = XSecure_Sha3Hash(SrcAddrHigh, SrcAddrLow,
SrcSize, Flags);
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_SHA3_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_EXIT);
#endif
IPI_RESPONSE1(master->ipiMask, Status);
}
/**
* PmSecureRsa() - To encrypt or decrypt the data with provided public or
* private kley components by using RSA core.
*
* @SrcAddrHigh: Higher 32-bit Linear memory space from where data
* will be read.
*
* @SrcAddrLow: Lower 32-bit Linear memory space from where data
* will be read.
*
* @SrcSize: Number of bytes of data.
*
* @Flags: provides inputs for operation to be performed
*
* @return error status based on implemented functionality(SUCCESS by default)
*/
static void PmSecureRsa(const PmMaster *const master,
const u32 SrcAddrHigh, const u32 SrcAddrLow,
const u32 SrcSize, const u32 Flags)
{
u32 Status;
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_RSA_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_RSA_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_ENTER);
#endif
Status = XSecure_RsaCore(SrcAddrHigh, SrcAddrLow,
SrcSize, Flags);
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_RSA_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_EXIT);
#endif
IPI_RESPONSE1(master->ipiMask, Status);
}
/**
* PmSecureAes() - To encrypt or decrypt the data with the provided
* key (Device/KUP/PUF keys).
*
* @SrcAddrHigh: Higher 32-bit address of the XSecure_AesParams structure
* from where data addresses will be read.
*
* @SrcAddrLow: Lower 32-bit address of the XSecure_AesParams structure
* from where data addresses will be read.
*
* @return error status based on implemented functionality(SUCCESS by default)
*/
static void PmSecureAes(const PmMaster *const master,
const u32 SrcAddrHigh, const u32 SrcAddrLow)
{
u32 Status = XST_SUCCESS;
XilSKey_Puf InstancePtr;
u64 WrAddr = ((u64)SrcAddrHigh << 32U) | SrcAddrLow;
XSecure_AesParams *Aes = (XSecure_AesParams *)(UINTPTR)WrAddr;
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_AES_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_AES_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_ENTER);
#endif
if (Aes->KeySrc == AES_PUF_KEY_SEL_MASK) {
Status = XilSKey_Puf_Regeneration(&InstancePtr);
if (Status != 0U) {
goto END;
}
}
Status = XSecure_AesOperation(SrcAddrHigh, SrcAddrLow);
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_AES_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_EXIT);
#endif
END:
IPI_RESPONSE2(master->ipiMask, XST_SUCCESS, Status);
}
/**
* PmSecureImage() - To process secure image
*
* @SrcAddrHigh: Higher 32-bit Linear memory space from where data
* will be read.
*
* @SrcAddrLow: Lower 32-bit Linear memory space from where data
* will be read.
*
* @KupAddrHigh: Higher 32-bit Linear memory space from where data
* will be read.
*
* @KupAddrLow: Lower 32-bit Linear memory space from where data
* will be read.
*
*
* @return error status based on implemented functionality(SUCCESS by default)
*/
static void PmSecureImage(const PmMaster *const master,
const u32 SrcAddrHigh, const u32 SrcAddrLow, const u32 KupAddrHigh, const u32 KupAddrLow)
{
u32 Status;
XSecure_DataAddr Addr = {0U};
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_SECURE_IMG_LOAD_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_SECURE_IMG_LOAD_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_ENTER);
#endif
Status = XSecure_SecureImage(SrcAddrHigh, SrcAddrLow, KupAddrHigh, KupAddrLow, &Addr);
#if defined (ENABLE_WDT) && \
(XPFW_CFG_PMU_SECURE_IMG_LOAD_WDT_TIMEOUT > XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT)
PmNotifyR5AndModifyWdtTimeout(XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT,
PM_NOTIFY_STL_NO_OP_EXIT);
#endif
if (Status != 0x0U) {
PmErr("Failed image loading with error : %x\r\n", Status);
}
IPI_RESPONSE3(master->ipiMask, Status, Addr.AddrHigh, Addr.AddrLow);
}
#endif
/**
* This function provides access to efuse memory
*
* @AddrHigh: Higher 32-bit address of the XilSKey_Efuse structure.
* @AddrLow: Lower 32-bit address of the XilSKey_Efuse structure.
*
* @return error status based on implemented functionality(SUCCESS by default)
*/
static void PmEfuseAccess(const PmMaster *const master,
const u32 AddrHigh, const u32 AddrLow)
{
u32 Status;
#ifdef EFUSE_ACCESS
Status = XilSkey_ZynqMpEfuseAccess(AddrHigh, AddrLow);
#else
Status = XST_NOT_ENABLED;
#endif
IPI_RESPONSE2(master->ipiMask, XST_SUCCESS, Status);
}
/**
* PmGetChipid() - Get silicon version register
*/
static void PmGetChipid(const PmMaster *const master)
{
u32 idcode = XPfw_Read32(CSU_IDCODE);
u32 version = XPfw_Read32(CSU_VERSION);
u32 pl_init = XPfw_Read32(CSU_PCAP_STATUS_REG);
u32 efuse_ipdisable = XPfw_Read32(EFUSE_IPDISABLE);
efuse_ipdisable &= EFUSE_IPDISABLE_VERSION;
pl_init &= CSU_PCAP_STATUS_PL_INIT_MASK_VAL;
version |= efuse_ipdisable << CSU_VERSION_EMPTY_SHIFT;
version |= pl_init <<
(CSU_VERSION_PL_STATE_SHIFT - CSU_PCAP_STATUS_PL_INIT_SHIFT_VAL);
IPI_RESPONSE3(master->ipiMask, XST_SUCCESS, idcode, version);
}
/**
* PmSetWakeupSource() - Master requests to be woken-up by the slaves interrupt
* @master Initiator of the request
* @targetNode Master node to be woken-up (currently must be same as initiator)
* @sourceNode Source of the wake-up (slave that generates interrupt)
* @enable Flag stating should event be enabled or disabled
*
* @note GIC wake interrupt is automatically enabled when a processor
* goes to sleep.
*/
static void PmSetWakeupSource(const PmMaster *const master,
const u32 targetNode,
const u32 sourceNode,
const u32 enable)
{
s32 status = XST_SUCCESS;
PmRequirement* req;
PmSlave* slave = (PmSlave*)PmNodeGetSlave(sourceNode);
/* Check if given target node is valid */
if ((targetNode != master->nid) &&
(NULL == PmGetProcOfThisMaster(master, targetNode))) {
status = XST_INVALID_PARAM;
goto done;
}
/* The call applies only to slave nodes */
if (NULL == slave) {
status = XST_INVALID_PARAM;
goto done;
}
req = PmRequirementGet(master, slave);
/* Is master allowed to use resource (slave)? */
if (NULL == req) {
status = XST_PM_NO_ACCESS;
goto done;
}
/* Check whether the slave has wake-up capability */
status = PmSlaveHasWakeUpCap(req->slave);
if (XST_SUCCESS != status) {
goto done;
}
/* Set/clear request info according to the enable flag */
if (0U == enable) {
req->info &= ~PM_MASTER_WAKEUP_REQ_MASK;
} else if (1U == enable) {
req->info |= PM_MASTER_WAKEUP_REQ_MASK;
} else {
status = XST_INVALID_PARAM;
goto done;
}
if (NULL != slave->wake) {
slave->wake->class->set(slave->wake, master->ipiMask, enable);
}
done:
PmInfo("%s> SetWakeupSource(%lu, %lu, %lu)\r\n", master->name,
targetNode, sourceNode, enable);
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmSystemShutdown() - Request system shutdown or restart
* @master Master requesting system shutdown
* @type Shutdown type
* @subtype Shutdown subtype
*/
static void PmSystemShutdown(PmMaster* const master, const u32 type,
const u32 subtype)
{
s32 status = XST_SUCCESS;
PmInfo("%s> SystemShutdown(%lu, %lu)\r\n", master->name, type, subtype);
/* For shutdown type the subtype is irrelevant: shut the caller down */
if (PMF_SHUTDOWN_TYPE_SHUTDOWN == type) {
status = PmMasterFsm(master, PM_MASTER_EVENT_FORCE_DOWN);
#if defined(BOARD_SHUTDOWN_PIN) && defined(BOARD_SHUTDOWN_PIN_STATE)
if (PMF_SHUTDOWN_SUBTYPE_SYSTEM == subtype) {
PmKillBoardPower();
}
#endif
goto done;
}
if (PMF_SHUTDOWN_TYPE_RESET != type) {
status = XST_INVALID_PARAM;
goto done;
}
/* Now distinguish the restart scope depending on the subtype */
switch (subtype) {
case PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM:
status = PmMasterRestart(master);
break;
case PMF_SHUTDOWN_SUBTYPE_PS_ONLY:
XPfw_ResetPsOnly();
break;
case PMF_SHUTDOWN_SUBTYPE_SYSTEM:
XPfw_ResetSystem();
break;
default:
PmLog(PM_ERRNO_INVALID_SUBTYPE, subtype, master->name);
status = XST_INVALID_PARAM;
break;
}
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmSetMaxLatency() - set maximum allowed latency for the node
* @master Initiator of the request who must previously requested the node
* @node Node whose latency, and consequently deepest possible state, is
* specified
* @latency Maximum allowed latency
*/
static void PmSetMaxLatency(const PmMaster *const master, const u32 node,
const u32 latency)
{
s32 status = XST_SUCCESS;
PmRequirement* masterReq;
PmSlave* slave = (PmSlave*)PmNodeGetSlave(node);
PmInfo("%s> SetMaxLatency(%lu, %lu)\r\n", master->name, node, latency);
if (NULL == slave) {
status = XST_INVALID_PARAM;
goto done;
}
masterReq = PmRequirementGet(master, slave);
/* Check if the master can use given slave node */
if (NULL == masterReq) {
status = XST_PM_NO_ACCESS;
goto done;
}
/* Check if master has previously requested the node */
if (!MASTER_REQUESTED_SLAVE(masterReq)) {
status = XST_PM_NO_ACCESS;
goto done;
}
masterReq->latencyReq = latency;
masterReq->info |= PM_MASTER_SET_LATENCY_REQ;
status = PmUpdateSlave(masterReq->slave);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmSetConfiguration() - Load the configuration
* @master Master who initiated the loading of configuration
* @address Address at which the configuration object is placed
*/
static void PmSetConfiguration(const PmMaster *const master, const u32 address)
{
s32 status;
u32 configAddr = address;
u32 callerIpiMask = master->ipiMask;
PmInfo("%s> SetConfig(0x%lx)\r\n", master->name, address);
if (NULL != master->remapAddr) {
configAddr = master->remapAddr(address);
}
status = PmConfigLoadObject(configAddr, callerIpiMask);
/*
* Respond using the saved IPI mask of the caller (master's IPI mask
* may change after setting the configuration)
*/
IPI_RESPONSE1(callerIpiMask, status);
}
/**
* PmProcRpuForceDownFix() - Fix the state of RPU processor to be forced down
* @proc RPU processor
*/
static void PmProcRpuForceDownFix(PmProc* const proc)
{
if (NULL != proc->node.parent) {
if (0U != (NODE_LOCKED_POWER_FLAG & proc->node.flags)) {
PmPowerReleaseParent(&proc->node);
}
}
if (NULL != proc->node.clocks) {
if (0U != (NODE_LOCKED_CLOCK_FLAG & proc->node.flags)) {
PmClockRelease(&proc->node);
}
}
proc->node.currState = PM_PROC_STATE_FORCEDOFF;
proc->master->state = PM_MASTER_STATE_KILLED;
}
/**
* PmProbeRpuState() - Probe and update the state of RPU
*
* @note The probe is performed only once
*/
static void PmProbeRpuState(void)
{
static bool probed = false;
u32 halt0 = XPfw_Read32(RPU_RPU_0_CFG);
u32 reset = XPfw_Read32(CRL_APB_RST_LPD_TOP);
u32 mode = XPfw_Read32(RPU_RPU_GLBL_CNTL);
if (true == probed) {
goto done;
}
/* If reset is asserted or (deasserted and RPU_0 is halted) */
if ((0U != (reset & CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK)) ||
((0U == (reset & CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK)) &&
(0U == (halt0 & RPU_RPU_0_CFG_NCPUHALT_MASK)))) {
PmProcRpuForceDownFix(&pmProcRpu0_g);
}
/* If RPU lockstep mode is configured in hardware */
if (0U == (mode & RPU_RPU_GLBL_CNTL_SLSPLIT_MASK)) {
if (NULL != pmProcRpu1_g.master) {
PmErr("expected split mode, found lockstep\r\n");
goto done;
}
pmProcRpu1_g.node.currState = PM_PROC_STATE_FORCEDOFF;
} else {
u32 halt1 = XPfw_Read32(RPU_RPU_1_CFG);
/* If reset is asserted or (deasserted and RPU_1 is halted) */
if ((0U != (reset & CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK)) ||
((0U == (reset & CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK)) &&
(0U == (halt1 & RPU_RPU_1_CFG_NCPUHALT_MASK)))) {
if (NULL == pmProcRpu1_g.master) {
PmErr("expected lockstep, found split mode\r\n");
goto done;
}
PmProcRpuForceDownFix(&pmProcRpu1_g);
}
}
probed = true;
done:
return;
}
/**
* PmGetNodeStatus() - Get the status of the node
* @master Initiator of the request
* @node Node whose status should be returned
*/
static void PmGetNodeStatus(const PmMaster *const master, const u32 node)
{
u32 oppoint = 0U;
u32 currReq = 0U;
u32 usage = 0U;
s32 status = XST_SUCCESS;
PmNode* nodePtr = PmGetNodeById(node);
PmInfo("%s> GetNodeStatus(%lu)\r\n", master->name, node);
if (NULL == nodePtr) {
status = XST_INVALID_PARAM;
goto done;
}
if ((NODE_RPU == node) || (NODE_RPU_0 == node) || (NODE_RPU_1 == node)) {
PmProbeRpuState();
}
oppoint = nodePtr->currState;
if (NODE_IS_SLAVE(nodePtr)) {
PmSlave* const slave = (PmSlave*)nodePtr->derived;
currReq = PmSlaveGetRequirements(slave, master);
usage = PmSlaveGetUsageStatus(slave, master);
}
done:
IPI_RESPONSE4(master->ipiMask, status, oppoint, currReq, usage);
}
/**
* PmGetOpCharacteristics() - Get operating characteristics of a node
* @master Initiator of the request
* @node Node in question
* @type Type of the operating characteristics
* power, temperature and latency
*/
static void PmGetOpCharacteristics(const PmMaster *const master, const u32 node,
const u32 type)
{
u32 result = 0U;
s32 status = XST_SUCCESS;
PmNode* nodePtr = PmGetNodeById(node);
if (NULL == nodePtr) {
status = XST_INVALID_PARAM;
goto done;
}
switch(type) {
case PM_OPCHAR_TYPE_POWER:
if (NULL == nodePtr->class->getPowerData) {
status = XST_NO_FEATURE;
goto done;
}
status = nodePtr->class->getPowerData(nodePtr, &result);
break;
case PM_OPCHAR_TYPE_TEMP:
PmLog(PM_ERRNO_NO_TEMP_SUPPORT, node, master->name);
status = XST_NO_FEATURE;
break;
case PM_OPCHAR_TYPE_LATENCY:
if (NULL == nodePtr->class->getWakeUpLatency) {
status = XST_NO_FEATURE;
goto done;
}
status = nodePtr->class->getWakeUpLatency(nodePtr, &result);
break;
default:
PmLog(PM_ERRNO_INVALID_TYPE, type, master->name);
status = XST_INVALID_PARAM;
goto done;
}
done:
PmInfo("%s> PmGetOpChar(%lu, %lu, %lu)\r\n", master->name, node, type,
result);
IPI_RESPONSE2(master->ipiMask, status, result);
}
/**
* PmRegisterNotifier() - Register a master to be notified about the event
* @master Master to be notified
* @node Node to which the event is related
* @event Event in question
* @wake Wake master upon capturing the event if value 1, do not wake if 0
* @enable Enable the registration for value 1, disable for value 0
*/
static void PmRegisterNotifier(const PmMaster *const master, const u32 node,
const u32 event, const u32 wake,
const u32 enable)
{
s32 status;
PmNode* nodePtr = PmGetNodeById(node);
PmInfo("%s> RegisterNotifier(%lu, %lu, %lu, %lu)\r\n", master->name,
node, event, wake, enable);
if (NULL == nodePtr) {
status = XST_INVALID_PARAM;
goto done;
}
if ((0U != wake && 1U != wake) || (0U != enable && 1U != enable) ||
(EVENT_STATE_CHANGE != event && EVENT_ZERO_USERS != event)) {
status = XST_INVALID_PARAM;
goto done;
}
if (0U == enable) {
PmNotifierUnregister(master, nodePtr, event);
status = XST_SUCCESS;
} else {
status = PmNotifierRegister(master, nodePtr, event, wake);
}
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmInitFinalize() - Notification from a master that it has initialized PM
* @master Initiator of the request
*/
void PmInitFinalize(PmMaster* const master)
{
s32 status;
PmInfo("%s> InitFinalize\r\n", master->name);
status = PmMasterInitFinalize(master);
#ifdef ENABLE_UNUSED_RPU_PWR_DWN
PmForceDownUnusableRpuCores();
#endif
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmClockSetParent() - Set the clock parent (configure clock's mux)
* @master The caller
* @clockId ID of the target clock
* @select Mux select value
*/
static void PmClockSetParent(PmMaster* const master, const u32 clockId,
const u32 select)
{
PmClock* clock;
s32 status = XST_SUCCESS;
PmInfo("%s> ClockSetParent(%lu, %lu)\r\n", master->name, clockId,
select);
clock = PmClockGetById(clockId);
if (NULL == clock) {
status = XST_INVALID_PARAM;
goto done;
}
#ifndef DISABLE_CLK_PERMS
status = PmClockCheckPermission(clock, master->ipiMask);
if (XST_SUCCESS != status) {
goto done;
}
#endif
status = PmClockMuxSetParent(clock, select);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmClockGetParent() - Get the mux select value of the current clock parent
* @master The caller
* @clockId ID of the target clock
*/
static void PmClockGetParent(PmMaster* const master, const u32 clockId)
{
PmClock* clock;
u32 select = 0U;
s32 status = XST_SUCCESS;
PmInfo("%s> ClockGetParent(%lu)\r\n", master->name, clockId);
clock = PmClockGetById(clockId);
if (NULL == clock) {
status = XST_INVALID_PARAM;
goto done;
}
status = PmClockMuxGetParent(clock, &select);
done:
IPI_RESPONSE2(master->ipiMask, status, select);
}
/**
* PmClockGateConfig() - Configure clock gate if master has privileges to do so
* @master The caller
* @clkId ID of the target clock
* @enable 1=enable the clock, 0=disable the clock
*/
static void PmClockGateConfig(PmMaster* const master, const u32 clkId, const u8 enable)
{
PmClock* clock;
s32 status = XST_SUCCESS;
PmInfo("%s> ClockGate(%lu, %lu)\r\n", master->name, clkId, enable);
clock = PmClockGetById(clkId);
if (NULL == clock) {
status = XST_INVALID_PARAM;
goto done;
}
#ifndef DISABLE_CLK_PERMS
status = PmClockCheckPermission(clock, master->ipiMask);
if (XST_SUCCESS != status) {
goto done;
}
#endif
status = PmClockGateSetState(clock, enable);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmClockGetStatus() - Get clock gate status
* @master Master that initiated the call
* @clockId ID of the clock in question
*/
static void PmClockGetStatus(PmMaster* const master, const u32 clockId)
{
PmClock* clock;
s32 status = XST_SUCCESS;
u8 enable = 0x0U;
PmInfo("%s> ClockGetStatus(%lu)\r\n", master->name, clockId);
clock = PmClockGetById(clockId);
if (NULL == clock) {
status = XST_INVALID_PARAM;
goto done;
}
status = PmClockGateGetState(clock, &enable);
done:
IPI_RESPONSE2(master->ipiMask, status, enable);
}
/**
* PmClockSetDivider() - Set divider of the clock
* @master Master that initiated the call
* @clockId ID of the clock in question
* @divId Identifier of the divider value to be set
* @val Divider value to be set
*/
static void PmClockSetDivider(PmMaster* const master, const u32 clockId,
const u32 divId, const u32 val)
{
PmClock* clock;
s32 status = XST_SUCCESS;
PmInfo("%s> ClockSetDivider(%lu, %lu, %lu)\r\n", master->name, clockId,
divId, val);
clock = PmClockGetById(clockId);
if (NULL == clock || 0U == val || INVALID_DIV_ID(divId)) {
status = XST_INVALID_PARAM;
goto done;
}
#ifndef DISABLE_CLK_PERMS
status = PmClockCheckPermission(clock, master->ipiMask);
if (XST_SUCCESS != status) {
goto done;
}
#endif
status = PmClockDividerSetVal(clock, divId, val);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmClockGetDivider() - Get currently configured divider value of the clock
* @master Master that initiated the call
* @clockId ID of the clock in question
* @divId ID of the divider
*/
static void PmClockGetDivider(PmMaster* const master, const u32 clockId,
const u32 divId)
{
PmClock* clock;
s32 status = XST_SUCCESS;
u32 div = 0U;
PmInfo("%s> ClockGetDivider(%lu)\r\n", master->name, clockId);
clock = PmClockGetById(clockId);
if (NULL == clock) {
status = XST_INVALID_PARAM;
goto done;
}
status = PmClockDividerGetVal(clock, divId, &div);
done:
IPI_RESPONSE2(master->ipiMask, status, div);
}
/**
* PmPllSetParam() - Set PLL parameter
* @master Master that initiated the call
* @pllId PLL node ID
* @paramId PLL parameter ID
* @value PLL parameter value to set
*/
static void PmPllSetParam(PmMaster* const master, const u32 pllId, const u32 paramId,
const u32 value)
{
s32 status = XST_SUCCESS;
PmPll* pll = PmNodeGetPll(pllId);
PmInfo("%s> PllSetParam(%lu, %lu, %lu)\r\n", master->name, pllId,
paramId, value);
if (NULL == pll) {
status = XST_INVALID_PARAM;
goto done;
}
#ifndef DISABLE_CLK_PERMS
if (0U == (master->ipiMask & PmPllGetPermissions(pll))) {
status = XST_PM_NO_ACCESS;
goto done;
}
#endif
status = PmPllSetParameterInt(pll, paramId, value);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmPllGetParam() - Get PLL parameter
* @master Master that initiated the call
* @pllId PLL node ID
* @paramId PLL parameter ID
*/
static void PmPllGetParam(PmMaster* const master, const u32 pllId, const u32 paramId)
{
s32 status = XST_SUCCESS;
PmPll* pll = PmNodeGetPll(pllId);
u32 value = 0U;
PmInfo("%s> PllGetParam(%lu, %lu)\r\n", master->name, pllId, paramId);
if (NULL == pll) {
status = XST_INVALID_PARAM;
goto done;
}
status = PmPllGetParameterInt(pll, paramId, &value);
done:
IPI_RESPONSE2(master->ipiMask, status, value);
}
/**
* PmPllSetMode() - Set PLL mode
* @master Master that initiated the call
* @pllId PLL node ID
* @mode PLL mode to set
*/
static void PmPllSetMode(PmMaster* const master, const u32 pllId, const u32 mode)
{
s32 status = XST_SUCCESS;
PmPll* pll = PmNodeGetPll(pllId);
PmInfo("%s> PllSetMode(%lu, %lu, %lu)\r\n", master->name, pllId, mode);
if (NULL == pll) {
status = XST_INVALID_PARAM;
goto done;
}
#ifndef DISABLE_CLK_PERMS
if (0U == (master->ipiMask & PmPllGetPermissions(pll))) {
status = XST_PM_NO_ACCESS;
goto done;
}
#endif
status = PmPllSetModeInt(pll, mode);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmPllGetMode() - Get PLL mode
* @master Master that initiated the call
* @pllId PLL node ID
* @mode PLL mode
*/
static void PmPllGetMode(PmMaster* const master, const u32 pllId)
{
s32 status = XST_SUCCESS;
PmPll* pll = PmNodeGetPll(pllId);
u32 mode = 0U;
PmInfo("%s> PllGetMode(%lu)\r\n", master->name, pllId);
if (NULL == pll) {
status = XST_INVALID_PARAM;
goto done;
}
mode = PmPllGetModeInt(pll);
done:
IPI_RESPONSE2(master->ipiMask, status, mode);
}
/**
* PmPinCtrlRequest() - Request PIN control
* @master Master that initiated the call
* @pinId ID of the pin
*/
static void PmPinCtrlRequest(PmMaster* const master, const u32 pinId)
{
s32 status = XST_SUCCESS;
PmInfo("%s> PmPinCtrlRequest(%lu)\r\n", master->name, pinId);
status = PmPinCtrlRequestInt(master->ipiMask, pinId);
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmPinCtrlRelease() - Release PIN control
* @master Master that initiated the call
* @pinId ID of the pin
*/
static void PmPinCtrlRelease(PmMaster* const master, const u32 pinId)
{
s32 status = XST_SUCCESS;
PmInfo("%s> PmPinCtrlRelease(%lu)\r\n", master->name, pinId);
status = PmPinCtrlReleaseInt(master->ipiMask, pinId);
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmPinCtrlGetFunction() - Get configured PIN function
* @master Master that initiated the call
* @pinId ID of the pin
*/
static void PmPinCtrlGetFunction(PmMaster* const master, const u32 pinId)
{
s32 status;
u32 fnId = 0U;
PmInfo("%s> PmPinCtrlGetFunc(%lu)\r\n", master->name, pinId);
status = PmPinCtrlGetFunctionInt(pinId, &fnId);
IPI_RESPONSE2(master->ipiMask, status, fnId);
}
/**
* PmPinCtrlSetFunction() - Set the PIN function
* @master Master that initiated the call
* @pinId ID of the pin
* @fnId Pin function ID
*/
static void PmPinCtrlSetFunction(PmMaster* const master, const u32 pinId,
const u32 fnId)
{
s32 status = XST_SUCCESS;
PmInfo("%s> PmPinCtrlSetFunc(%lu, %lu)\r\n", master->name, pinId, fnId);
status = PmPinCtrlCheckPerms(master->ipiMask, pinId);
if (XST_SUCCESS != status) {
goto done;
}
status = PmPinCtrlSetFunctionInt(master, pinId, fnId);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmPinCtrlConfigParamGet() - Get the PIN configuration parameter value
* @master Master that initiated the call
* @pinId ID of the pin
* @paramId Parameter ID
*/
static void PmPinCtrlConfigParamGet(PmMaster* const master, const u32 pinId,
const u32 paramId)
{
s32 status;
u32 value = 0U;
PmInfo("%s> PmPinCtrlParamGet(%lu, %lu)\r\n", master->name, pinId,
paramId);
status = PmPinCtrlGetParam(pinId, paramId, &value);
IPI_RESPONSE2(master->ipiMask, status, value);
}
/**
* PmPinCtrlConfigParamSet() - Set the PIN configuration parameter value
* @master Master that initiated the call
* @pinId ID of the pin
* @paramId Parameter ID
* @val Parameter value to be set
*/
static void PmPinCtrlConfigParamSet(PmMaster* const master, const u32 pinId,
const u32 paramId, const u32 val)
{
s32 status;
PmInfo("%s> PmPinCtrlParamSet(%lu, %lu, %lu)\r\n", master->name, pinId,
paramId, val);
status = PmPinCtrlCheckPerms(master->ipiMask, pinId);
if (XST_SUCCESS != status) {
goto done;
}
status = PmPinCtrlSetParam(pinId, paramId, val);
done:
IPI_RESPONSE1(master->ipiMask, status);
}
/**
* PmApiApprovalCheck() - Check if the API ID can be processed at the moment
* @apiId PM API ID
*
* @return True if API can be processed, false otherwise
*/
static bool PmApiApprovalCheck(const u32 apiId)
{
bool approved = PmConfigObjectIsLoaded();
if (true == approved) {
goto done;
}
/* If the object is not loaded only APIs below can be processed */
switch (apiId) {
case PM_GET_API_VERSION:
case PM_GET_CHIPID:
case PM_SET_CONFIGURATION:
approved = true;
break;
default:
approved = false;
break;
}
done:
return approved;
}
/**
* PmProcessApiCall() - Called to process PM API call
* @master Pointer to a requesting master structure
* @pload Pointer to array of integers with the information about the pm call
* (api id + arguments of the api)
*
* @note Called to process PM API call. If specific PM API receives less
* than 4 arguments, extra arguments are ignored.
*/
void PmProcessRequest(PmMaster *const master, const u32 *pload)
{
u32 setAddress;
u64 address;
bool approved = PmApiApprovalCheck(pload[0]);
if (false == approved) {
IPI_RESPONSE1(master->ipiMask, XST_PM_NO_ACCESS);
goto done;
}
switch (pload[0]) {
case PM_SELF_SUSPEND:
address = ((u64) pload[5]) << 32ULL;
address += pload[4];
PmSelfSuspend(master, pload[1], pload[2], pload[3], address);
break;
case PM_REQUEST_SUSPEND:
PmRequestSuspend(master, pload[1], pload[2], pload[3], pload[4]);
break;
case PM_FORCE_POWERDOWN:
PmForcePowerdown(master, pload[1], pload[2]);
break;
case PM_ABORT_SUSPEND:
PmAbortSuspend(master, pload[1], pload[2]);
break;
case PM_REQUEST_WAKEUP:
/* setAddress is encoded in the 1st bit of the low-word address */
setAddress = pload[2] & 0x1U;
/* addresses are word-aligned, ignore bit 0 */
address = ((u64) pload[3]) << 32ULL;
address += pload[2] & ~0x1U;
PmRequestWakeup(master, pload[1], setAddress, address, pload[4]);
break;
case PM_SET_WAKEUP_SOURCE:
PmSetWakeupSource(master, pload[1], pload[2], pload[3]);
break;
case PM_SYSTEM_SHUTDOWN:
PmSystemShutdown(master, pload[1], pload[2]);
break;
case PM_REQUEST_NODE:
PmRequestNode(master, pload[1], pload[2], pload[3], pload[4]);
break;
case PM_RELEASE_NODE:
PmReleaseNode(master, pload[1]);
break;
case PM_SET_REQUIREMENT:
PmSetRequirement(master, pload[1], pload[2], pload[3], pload[4]);
break;
case PM_SET_MAX_LATENCY:
PmSetMaxLatency(master, pload[1], pload[2]);
break;
case PM_GET_API_VERSION:
PmGetApiVersion(master);
break;
case PM_SET_CONFIGURATION:
PmSetConfiguration(master, pload[1]);
break;
case PM_GET_NODE_STATUS:
PmGetNodeStatus(master, pload[1]);
break;
case PM_GET_OP_CHARACTERISTIC:
PmGetOpCharacteristics(master, pload[1], pload[2]);
break;
case PM_REGISTER_NOTIFIER:
PmRegisterNotifier(master, pload[1], pload[2], pload[3], pload[4]);
break;
case PM_RESET_ASSERT:
PmResetAssert(master, pload[1], pload[2]);
break;
case PM_RESET_GET_STATUS:
PmResetGetStatus(master, pload[1]);
break;
case PM_MMIO_WRITE:
PmMmioWrite(master, pload[1], pload[2], pload[3]);
break;
case PM_MMIO_READ:
PmMmioRead(master, pload[1]);
break;
case PM_INIT_FINALIZE:
PmInitFinalize(master);
break;
#ifdef ENABLE_FPGA_LOAD
case PM_FPGA_LOAD:
PmFpgaLoad(master, pload[1], pload[2], pload[3], pload[4]);
break;
case PM_FPGA_GET_STATUS:
PmFpgaGetStatus(master);
break;
#if defined(ENABLE_FPGA_READ_CONFIG_DATA) || defined(ENABLE_FPGA_READ_CONFIG_REG)
case PM_FPGA_READ:
PmFpgaRead(master, pload[1], pload[2], pload[3], pload[4]);
break;
#endif
#endif
case PM_GET_CHIPID:
PmGetChipid(master);
break;
#ifdef ENABLE_SECURE
case PM_SECURE_SHA:
PmSecureSha(master, pload[1], pload[2], pload[3], pload[4]);
break;
case PM_SECURE_RSA:
PmSecureRsa(master, pload[1], pload[2], pload[3], pload[4]);
break;
case PM_SECURE_IMAGE:
PmSecureImage(master, pload[1], pload[2], pload[3], pload[4]);
break;
case PM_SECURE_AES:
PmSecureAes(master, pload[1], pload[2]);
break;
#endif
case PM_CLOCK_SETPARENT:
PmClockSetParent(master, pload[1], pload[2]);
break;
case PM_CLOCK_GETPARENT:
PmClockGetParent(master, pload[1]);
break;
case PM_CLOCK_ENABLE:
PmClockGateConfig(master, pload[1], 1U);
break;
case PM_CLOCK_DISABLE:
PmClockGateConfig(master, pload[1], 0U);
break;
case PM_CLOCK_GETSTATE:
PmClockGetStatus(master, pload[1]);
break;
case PM_CLOCK_SETDIVIDER:
PmClockSetDivider(master, pload[1], pload[2], pload[3]);
break;
case PM_CLOCK_GETDIVIDER:
PmClockGetDivider(master, pload[1], pload[2]);
break;
case PM_PLL_SET_PARAM:
PmPllSetParam(master, pload[1], pload[2], pload[3]);
break;
case PM_PLL_GET_PARAM:
PmPllGetParam(master, pload[1], pload[2]);
break;
case PM_PLL_SET_MODE:
PmPllSetMode(master, pload[1], pload[2]);
break;
case PM_PLL_GET_MODE:
PmPllGetMode(master, pload[1]);
break;
case PM_EFUSE_ACCESS:
PmEfuseAccess(master, pload[1], pload[2]);
break;
case PM_PINCTRL_REQUEST:
PmPinCtrlRequest(master, pload[1]);
break;
case PM_PINCTRL_RELEASE:
PmPinCtrlRelease(master, pload[1]);
break;
case PM_PINCTRL_GET_FUNCTION:
PmPinCtrlGetFunction(master, pload[1]);
break;
case PM_PINCTRL_SET_FUNCTION:
PmPinCtrlSetFunction(master, pload[1], pload[2]);
break;
case PM_PINCTRL_CONFIG_PARAM_GET:
PmPinCtrlConfigParamGet(master, pload[1], pload[2]);
break;
case PM_PINCTRL_CONFIG_PARAM_SET:
PmPinCtrlConfigParamSet(master, pload[1], pload[2], pload[3]);
break;
default:
PmWarn("Unsupported EEMI API #%lu\r\n", pload[0]);
IPI_RESPONSE1(master->ipiMask, XST_INVALID_VERSION);
break;
}
done:
return;
}
/**
* PmShutdownInterruptHandler() - Send suspend request to all active masters
*/
void PmShutdownInterruptHandler(void)
{
#if defined(PMU_MIO_INPUT_PIN) && (PMU_MIO_INPUT_PIN >= 0U) \
&& (PMU_MIO_INPUT_PIN <= 5U)
/*
* Default status of MIO26 pin is 1. So MIO wake event bit in GPI1
* register is always 1, which is used to identify shutdown event.
*
* GPI event occurs only when any bit of GPI register changes from
* 0 to 1. When any GPI1 event occurs Gpi1InterruptHandler() checks
* GPI1 register and process interrupts for the bits which are 1.
* Because of MIO wake bit is 1 in GPI1 register, shutdown handler
* will be called every time when any of GPI1 event occurs.
*
* There is no way to identify which bit cause GPI1 interrupt.
* So every time Gpi1InterruptHandler() is checking bit which are 1
* And calls respective handlers.
*
* To handle such case avoid power off when any other (other than MIO
* wake)bit in GPI1 register is 1. If no other bit is 1 in GPI1 register
* and still PMU gets GPI1 interrupt means that MIO26 pin state is
* changed from (1 to 0 and 0 to 1). In this case it is confirmed that
* it is event for shutdown only and not because of other events.
* There are chances that some shutdown events are missed (1 out of 50)
* but it should not harm.
*/
if (XPfw_Read32(PMU_IOMODULE_GPI1) !=
(PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK << PMU_MIO_INPUT_PIN)) {
return;
}
#endif
u32 rpu_mode = XPfw_Read32(RPU_RPU_GLBL_CNTL);
if (PM_MASTER_STATE_ACTIVE == PmMasterIsActive(&pmMasterApu_g)) {
PmInitSuspendCb(&pmMasterApu_g,
SUSPEND_REASON_SYS_SHUTDOWN, 1U, 0U, 0U);
}
if (0U == (rpu_mode & RPU_RPU_GLBL_CNTL_SLSPLIT_MASK)) {
if (PM_MASTER_STATE_ACTIVE == PmMasterIsActive(&pmMasterRpu0_g)) {
PmInitSuspendCb(&pmMasterRpu0_g,
SUSPEND_REASON_SYS_SHUTDOWN, 1U, 0U, 0U);
}
if (PM_MASTER_STATE_ACTIVE == PmMasterIsActive(&pmMasterRpu1_g)) {
PmInitSuspendCb(&pmMasterRpu1_g,
SUSPEND_REASON_SYS_SHUTDOWN, 1U, 0U, 0U);
}
} else {
if (PM_MASTER_STATE_ACTIVE == PmMasterIsActive(&pmMasterRpu_g)) {
PmInitSuspendCb(&pmMasterRpu_g,
SUSPEND_REASON_SYS_SHUTDOWN, 1U, 0U, 0U);
}
}
}
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_notifier.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_api.h"
#include "xpm_ipi.h"
#include "xpm_notifier.h"
#include "xplmi_err.h"
#define XPM_NOTIFIERS_COUNT 10U
typedef struct {
const XPm_Subsystem* Subsystem;
u32 NodeId;
u32 EventMask;
u32 WakeMask;
u32 IpiMask; /* TODO: Remove this when IPI mask support in CDO is available*/
} XPmNotifier;
static XPmNotifier PmNotifiers[XPM_NOTIFIERS_COUNT];
/****************************************************************************/
/**
* @brief Register the notifier for given subsystem, NodeId and event
*
* @param Subsystem Subsystem to be notified
* @param NodeId NodeId related to event
* @param Event Event to be notified about
* @param Wake Flag specifying whether the subsystem should be woken
* upon event notification
*
* @return None
*
****************************************************************************/
int XPmNotifier_Register(const XPm_Subsystem* const Subsystem,
const u32 NodeId,
const u32 Event, const u32 Wake, const u32 IpiMask)
{
int Status = XST_FAILURE;
u32 Idx, EmptyIdx = ARRAY_SIZE(PmNotifiers);
for (Idx = 0U; Idx < ARRAY_SIZE(PmNotifiers); Idx++) {
if (NULL == PmNotifiers[Idx].Subsystem) {
/* Empty entry found in PmNotifiers array */
if (EmptyIdx > Idx) {
/* Remember only first found empty entry */
EmptyIdx = Idx;
}
continue;
}
if ((Subsystem == PmNotifiers[Idx].Subsystem) &&
(NodeId == PmNotifiers[Idx].NodeId)) {
/* Drop empty index - existing entry found */
EmptyIdx = ARRAY_SIZE(PmNotifiers);
break;
}
}
if (EmptyIdx != ARRAY_SIZE(PmNotifiers)) {
/* Add new entry in empty place if no notifier found for given pair */
PmNotifiers[EmptyIdx].Subsystem = Subsystem;
PmNotifiers[EmptyIdx].NodeId = NodeId;
PmNotifiers[EmptyIdx].IpiMask = IpiMask;
Idx = EmptyIdx;
} else if (Idx >= ARRAY_SIZE(PmNotifiers)) {
/* There is no free entry in PmNotifiers array, report error */
Status = XST_FAILURE;
goto done;
} else {
/* Required due to MISRA */
PmDbg("[%d] Unknown else case\r\n", __LINE__);
}
/* Update event and wake mask for given entry */
PmNotifiers[Idx].EventMask |= Event;
if (0U != Wake) {
/* Wake subsystem for this event */
PmNotifiers[Idx].WakeMask |= Event;
}
/*
* Check if Node Class is EVENT and enable error action.
*/
if (XPM_NODECLASS_EVENT == NODECLASS(NodeId)) {
Status = XPlmi_EmSetAction(NodeId, Event, XPLMI_EM_ACTION_CUSTOM,
XPmNotifier_Event);
}
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief Unregister the notifier for given subsystem, NodeId and event
*
* @param Subsystem Subsystem which was registered for notification
* @param NodeId NodeId related to event
* @param Event Notification event
*
* @return None
*
****************************************************************************/
void XPmNotifier_Unregister(const XPm_Subsystem* const Subsystem,
const u32 NodeId,
const u32 Event)
{
u32 Idx;
for (Idx = 0U; Idx < ARRAY_SIZE(PmNotifiers); Idx++) {
if ((Subsystem == PmNotifiers[Idx].Subsystem) &&
(NodeId == PmNotifiers[Idx].NodeId)) {
/* Entry for subsystem/NodeId pair found */
PmNotifiers[Idx].EventMask &= ~Event;
PmNotifiers[Idx].WakeMask &= ~Event;
if (0U == PmNotifiers[Idx].EventMask) {
(void)memset(&PmNotifiers[Idx], 0,
sizeof(XPmNotifier));
}
/*
* Check if Node Class is EVENT and disable error action.
*/
if (XPM_NODECLASS_EVENT == NODECLASS(NodeId)) {
(void)XPlmi_EmDisable(NodeId, Event);
}
break;
}
}
}
/****************************************************************************/
/**
* @brief This function unregisters all notifiers of the given subsystem
*
* @param Subsystem Subsystem for which notifiers to be unregistered
*
* @return None
*
****************************************************************************/
void XPmNotifier_UnregisterAll(const XPm_Subsystem* const Subsystem)
{
u32 Idx;
for (Idx = 0U; Idx < ARRAY_SIZE(PmNotifiers); Idx++) {
if (Subsystem == PmNotifiers[Idx].Subsystem) {
(void)memset(&PmNotifiers[Idx], 0, sizeof(XPmNotifier));
}
}
}
/****************************************************************************/
/**
* @brief This function triggers the notification if enabled for current
* NodeId and current event.
*
* @param NodeId NodeId for which event is occurred
* @param Event Event type
*
* @return None
*
****************************************************************************/
void XPmNotifier_Event(const u32 NodeId, const u32 Event)
{
u32 Idx;
XPmNotifier* Notifier = NULL;
u32 Payload[PAYLOAD_ARG_CNT] = {0};
XPm_Device* Device;
int Status = XST_FAILURE;
for (Idx = 0U; Idx < ARRAY_SIZE(PmNotifiers); Idx++) {
/* Search for the given NodeId */
if (NodeId != PmNotifiers[Idx].NodeId) {
continue;
}
/*
* NodeId is matching, check for event
* Event 0 is valid for Node Class EVENT.
*/
if ((XPM_NODECLASS_EVENT != NODECLASS(NodeId)) &&
(0U == (Event & PmNotifiers[Idx].EventMask))) {
continue;
}
Notifier = &PmNotifiers[Idx];
break;
}
if ((NULL == Notifier) || (NULL == PmRequestCb)) {
goto done;
}
/* Populate the PayLoad */
Payload[0] = (u32)PM_NOTIFY_CB;
Payload[1] = Notifier->NodeId;
Payload[2] = Event;
switch (NODECLASS(NodeId)) {
case (u32)XPM_NODECLASS_EVENT:
/* Disable the error event. Agent will re-register for
* notification if needed */
(void)XPlmi_EmDisable(NodeId, Event);
Payload[3] = 0U;
Status = XST_SUCCESS;
break;
case (u32)XPM_NODECLASS_DEVICE:
Device = XPmDevice_GetById(NodeId);
if (NULL == Device) {
goto done;
}
Payload[3] = Device->Node.State;
Status = XST_SUCCESS;
break;
default:
PmErr("Unsupported Node Class: %d\r\n", NODECLASS(NodeId));
break;
}
if (XST_SUCCESS != Status) {
goto done;
}
/*
* If subsystem is OFFLINE then it should be notified about
* the event only if it requested to be woken up.
*/
if (((u8)OFFLINE != Notifier->Subsystem->State) ||
(0U != (Event & Notifier->WakeMask))) {
(*PmRequestCb)(Notifier->IpiMask, PM_NOTIFY_CB, Payload);
}
done:
return;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_proc.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* Definitions of processors and finite state machine
* used for managing processor's power states.
* Every processor must have:
* 1. Entry in GPI1 register for wfi interrupt (wfi enable and status
* masks)
* 2. Entry in GPI2 register for GIC wake interrupt (wake enable and
* status masks)
* 3. Operations structure in node definition with:
* - wake function pointer, that is always releasing reset and
* might include some more actions regarding the processor's
* state setting.
* - sleep function might exist but doesn't have to. For example,
* APU processors have sleep that powers down processor island,
* but RPU processors have no private objects whose state can
* be changed at this point. In future, every processor should
* have sleep function in which its clock will be gated.
*********************************************************************/
#include "pm_defs.h"
#include "pm_proc.h"
#include "pm_master.h"
#include "crl_apb.h"
#include "crf_apb.h"
#include "xpfw_rom_interface.h"
#include "apu.h"
#include "rpu.h"
#include "pm_system.h"
#include "pm_clock.h"
#include "xpfw_aib.h"
/* Enable/disable macros for processor's wfi event in GPI2 register */
#define ENABLE_WFI(mask) XPfw_RMW32(PMU_LOCAL_GPI2_ENABLE, (mask), (mask));
/* Power consumptions for the APU for specific states */
#define DEFAULT_APU_POWER_ACTIVE 200U
#define DEFAULT_APU_POWER_SUSPENDING 100U
#define DEFAULT_APU_POWER_SLEEP 0U
#define DEFAULT_APU_POWER_OFF 0U
/* Power consumptions for the RPU for specific states */
#define DEFAULT_RPU_POWER_ACTIVE 200U
#define DEFAULT_RPU_POWER_SUSPENDING 100U
#define DEFAULT_RPU_POWER_SLEEP 0U
#define DEFAULT_RPU_POWER_OFF 0U
/**
* PmProcHasResumeAddr() - Check whether the processor has the resume address
* @proc Processor to check
*/
bool PmProcHasResumeAddr(const PmProc* const proc)
{
return (0ULL != (proc->resumeAddress & 1ULL));
}
/**
* RPUSaveResumeAddr() - Saved address from which RPU core should resume
* @proc Processor to which the address should be restored upon wake-up
* @address Resume address (64-bit)
*
* @return XStatus of performing save operation
* - XST_SUCCESS is address is successfully saved
* - XST_INVALID_PARAM if address is invalid
*/
static s32 RPUSaveResumeAddr(PmProc* const proc, const u64 address)
{
s32 status = XST_SUCCESS;
u32 addrLow = (u32) (address & 0xffffffffULL);
/*
* For RPU processors lower 32-bits matter - only 2 values are
* possible to configure, report an error is addrLow is none of
* these.
*/
if ((PM_PROC_RPU_LOVEC_ADDR != addrLow) &&
(PM_PROC_RPU_HIVEC_ADDR != addrLow)) {
status = XST_INVALID_PARAM;
goto done;
}
/* Set bit0 to mark address as valid */
proc->resumeAddress = address | (u64)1ULL;
done:
return status;
}
/**
* APUSaveResumeAddr() - Saved address from which APU core should resume
* @proc Processor to which the address should be restored upon wake-up
* @address Resume address (64-bit)
*
* @return XST_SUCCESS
*/
static s32 APUSaveResumeAddr(PmProc* const proc, const u64 address)
{
/* Set bit0 to mark address as valid */
proc->resumeAddress = address | (u64)1ULL;
return XST_SUCCESS;
}
/**
* RPURestoreResumeAddr() - Restore resume address for RPU core
* @proc Processor whose address should be restored
*
* Note: RPU processors get restored resume address by configuring VINITHI bit
* in configuration register (RPUs can resume only from 2 addresses).
*/
static void RPURestoreResumeAddr(PmProc* const proc)
{
/* mask out resumeAddress BIT0, which indicates address validity */
u32 addrLow = (u32) (proc->resumeAddress & 0xfffffffeULL);
if (0ULL == (proc->resumeAddress & 1ULL)) {
goto done;
}
/* CFG_VINITHI_MASK mask is common for both processors */
if (PM_PROC_RPU_LOVEC_ADDR == addrLow) {
XPfw_RMW32(proc->resumeCfg, RPU_RPU_0_CFG_VINITHI_MASK,
~RPU_RPU_0_CFG_VINITHI_MASK);
} else {
XPfw_RMW32(proc->resumeCfg, RPU_RPU_0_CFG_VINITHI_MASK,
RPU_RPU_0_CFG_VINITHI_MASK);
}
/* Mark resume address as invalid by setting it to 0 */
proc->resumeAddress = 0ULL;
done:
return;
}
/**
* APURestoreResumeAddr() - Restore resume address for APU core
* @proc Processor whose address should be restored
*/
static void APURestoreResumeAddr(PmProc* const proc)
{
/* mask out resumeAddress BIT0, which indicates address validity */
u32 addrLow = (u32) (proc->resumeAddress & 0xfffffffeULL);
u32 addrHigh = (u32) (proc->resumeAddress >> 32ULL);
if (0ULL == (proc->resumeAddress & 1ULL)) {
goto done;
}
XPfw_Write32(proc->resumeCfg, addrLow);
XPfw_Write32(proc->resumeCfg + 4U, addrHigh);
/* Mark resume address as invalid by setting it to 0 */
proc->resumeAddress = 0ULL;
done:
return;
}
/**
* PmProcApu0Sleep() - Put APU_0 into sleep
* @return The status returned by PMU-ROM
*/
static s32 PmProcApu0Sleep(void)
{
return XpbrACPU0SleepHandler();
}
/**
* PmProcApu1Sleep() - Put APU_1 into sleep
* @return The status returned by PMU-ROM
*/
static s32 PmProcApu1Sleep(void)
{
return XpbrACPU1SleepHandler();
}
/**
* PmProcApu2Sleep() - Put APU_2 into sleep
* @return The status returned by PMU-ROM
*/
static s32 PmProcApu2Sleep(void)
{
return XpbrACPU2SleepHandler();
}
/**
* PmProcApu3Sleep() - Put APU_3 into sleep
* @return The status returned by PMU-ROM
*/
static s32 PmProcApu3Sleep(void)
{
return XpbrACPU3SleepHandler();
}
/**
* PmProcRpu0Sleep() - Put RPU_0 into sleep (reset only)
* @return Always success, reset cannot fail
*/
static s32 PmProcRpu0Sleep(void)
{
XPfw_AibEnable(XPFW_AIB_RPU0_TO_LPD);
XPfw_AibEnable(XPFW_AIB_LPD_TO_RPU0);
XPfw_RMW32(CRL_APB_RST_LPD_TOP,
CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
XPfw_RMW32(RPU_RPU_0_CFG,
RPU_RPU_0_CFG_NCPUHALT_MASK,
~RPU_RPU_0_CFG_NCPUHALT_MASK);
XPfw_RMW32(CRL_APB_RST_LPD_TOP,
CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
~CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
XPfw_AibDisable(XPFW_AIB_RPU0_TO_LPD);
XPfw_AibDisable(XPFW_AIB_LPD_TO_RPU0);
return XST_SUCCESS;
}
/**
* PmProcRpu1Sleep() - Put RPU_1 into sleep (reset only)
* @return Always success, reset cannot fail
*/
static s32 PmProcRpu1Sleep(void)
{
XPfw_AibEnable(XPFW_AIB_RPU1_TO_LPD);
XPfw_AibEnable(XPFW_AIB_LPD_TO_RPU1);
XPfw_RMW32(CRL_APB_RST_LPD_TOP,
CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
XPfw_RMW32(RPU_RPU_1_CFG,
RPU_RPU_1_CFG_NCPUHALT_MASK,
~RPU_RPU_1_CFG_NCPUHALT_MASK);
XPfw_RMW32(CRL_APB_RST_LPD_TOP,
CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
~CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
XPfw_AibDisable(XPFW_AIB_RPU1_TO_LPD);
XPfw_AibDisable(XPFW_AIB_LPD_TO_RPU1);
return XST_SUCCESS;
}
/**
* PmProcApu0Wake() - Wake up APU_0
* @return The status returned by PMU-ROM
*/
static s32 PmProcApu0Wake(void)
{
return XpbrACPU0WakeHandler();
}
/**
* PmProcApu1Wake() - Wake up APU_1
* @return The status returned by PMU-ROM
*/
static s32 PmProcApu1Wake(void)
{
return XpbrACPU1WakeHandler();
}
/**
* PmProcApu2Wake() - Wake up APU_2
* @return The status returned by PMU-ROM
*/
static s32 PmProcApu2Wake(void)
{
return XpbrACPU2WakeHandler();
}
/**
* PmProcApu3Wake() - Wake up APU_3
* @return The status returned by PMU-ROM
*/
static s32 PmProcApu3Wake(void)
{
return XpbrACPU3WakeHandler();
}
/**
* PmProcRpu0Wake() - Wake up RPU_0
* @return The status returned by PMU-ROM
*/
static s32 PmProcRpu0Wake(void)
{
s32 status;
status = XpbrRstR50Handler();
if (XST_SUCCESS != status) {
goto done;
}
XPfw_RMW32(RPU_RPU_0_CFG,
RPU_RPU_0_CFG_NCPUHALT_MASK,
RPU_RPU_0_CFG_NCPUHALT_MASK);
done:
return status;
}
/**
* PmProcRpu1Wake() - Wake up RPU_1
* @return The status returned by PMU-ROM
*/
static s32 PmProcRpu1Wake(void)
{
s32 status;
status = XpbrRstR51Handler();
if (XST_SUCCESS != status) {
goto done;
}
XPfw_RMW32(RPU_RPU_1_CFG,
RPU_RPU_1_CFG_NCPUHALT_MASK,
RPU_RPU_1_CFG_NCPUHALT_MASK);
done:
return status;
}
/**
* PmProcRpu1Init() - Initialize RPU_1
* @proc RPU_1 processor
*/
static void PmProcRpu1Init(PmProc* const proc)
{
u32 mode = XPfw_Read32(RPU_RPU_GLBL_CNTL);
/* For RPU lockstep mode RPU_1 is assumed to be always down */
if (0U == (mode & RPU_RPU_GLBL_CNTL_SLSPLIT_MASK)) {
proc->node.currState = PM_PROC_STATE_FORCEDOFF;
}
}
/**
* PmProcDisableEvents() - Disable wake and sleep events for the processor
* @proc Processor node
*/
static void PmProcDisableEvents(const PmProc* const proc)
{
/* Disable wake event in GPI1 */
DISABLE_WAKE(proc->mask);
/* Disable wfi event in GPI2 */
DISABLE_WFI(proc->mask);
}
/**
* PmProcWake() - Wake up a processor node
* @proc Processor to be woken-up
*
* @return Return status of processor specific wake handler
*/
static s32 PmProcWake(PmProc* const proc)
{
s32 status;
if (NULL != proc->node.parent) {
status = PmPowerRequestParent(&proc->node);
if (XST_SUCCESS != status) {
goto done;
}
}
if (NULL != proc->node.clocks) {
status = PmClockRequest(&proc->node);
if (XST_SUCCESS != status) {
goto done;
}
}
proc->restoreResumeAddr(proc);
status = proc->wake();
if (XST_SUCCESS == status) {
PmNodeUpdateCurrState(&proc->node, PM_PROC_STATE_ACTIVE);
}
done:
return status;
}
/**
* PmProcSleep() - Put processor node to sleep
* @proc Processor to sleep
*
* @return Return status of processor specific sleep handler
*/
s32 PmProcSleep(PmProc* const proc)
{
s32 status;
status = proc->sleep();
if (XST_SUCCESS != status) {
goto done;
}
if (NULL != proc->node.parent) {
PmPowerReleaseParent(&proc->node);
}
if (NULL != proc->node.clocks) {
PmClockRelease(&proc->node);
}
done:
return status;
}
/**
* PmProcTrActiveToSuspend() - FSM transition from active to suspend state
* @proc Pointer to processor whose FSM is changing state
*
* @return Operation status
* - XST_SUCCESS is always returned as this transition cannot fail
*
* @note Executes when processor's request for self suspend gets processed.
*/
static s32 PmProcTrActiveToSuspend(PmProc* const proc)
{
s32 status;
PmInfo("%s active->susp\r\n", proc->node.name);
ENABLE_WFI(proc->mask);
PmNodeUpdateCurrState(&proc->node, PM_PROC_STATE_SUSPENDING);
status = PmMasterFsm(proc->master, PM_MASTER_EVENT_SELF_SUSPEND);
return status;
}
/**
* PmProcTrToForcedOff() - FSM transition from active to force powerdown
* state
* @proc Pointer to processor whose FSM is changing state
*
* @return Operation status
*
* @note Executes when some other processor authorized to do so requests
* through PM API the PMU to powered down this processor. This
* processor is not informed about the following power down and
* therefore PMU does not wait for it to execute wfi. If processor has
* no implemented sleep function it will continue executing
* instructions.
* If the power down request bit is set when the processor is forced
* off, the bit must be cleared to ensure that
* 1. Processor correctly concludes on the future boot that it is not
* resuming
* 2. No wfi propagates to the PMU on the future boot (before processor
* clears the bit on its own)
*/
static s32 PmProcTrToForcedOff(PmProc* const proc)
{
s32 status;
bool killed;
u32 pwrReq;
PmInfo("%s active->forced off\r\n", proc->node.name);
proc->node.latencyMarg = MAX_LATENCY;
proc->resumeAddress = 0ULL;
status = PmProcSleep(proc);
PmNodeUpdateCurrState(&proc->node, PM_PROC_STATE_FORCEDOFF);
PmProcDisableEvents(proc);
pwrReq = XPfw_Read32(proc->pwrDnReqAddr);
if (0U != (proc->pwrDnReqMask & pwrReq)) {
pwrReq &= ~proc->pwrDnReqMask;
XPfw_Write32(proc->pwrDnReqAddr, pwrReq);
}
if ((XST_SUCCESS != status) || (NULL == proc->master)) {
goto done;
}
/* If master is also forced down we do not need to notify it */
killed = PmMasterIsKilled(proc->master);
if (false == killed) {
status = PmMasterFsm(proc->master, PM_MASTER_EVENT_FORCED_PROC);
}
done:
return status;
}
/**
* PmProcTrSuspendToActive() - FSM transition from suspend to active state
* @proc Pointer to processor whose FSM is changing state
*
* @return Operation status (should be always success)
*
* @note Executes when processor requests abort suspend through PM API.
*/
static s32 PmProcTrSuspendToActive(PmProc* const proc)
{
s32 status;
PmInfo("%s susp->active\r\n", proc->node.name);
DISABLE_WFI(proc->mask);
/* Notify master to cancel scheduled requests */
status = PmMasterFsm(proc->master, PM_MASTER_EVENT_ABORT_SUSPEND);
PmNodeUpdateCurrState(&proc->node, PM_PROC_STATE_ACTIVE);
return status;
}
/**
* PmProcTrSuspendToSleep() - FSM transition from suspend to sleep state
* @proc Pointer to processor whose FSM is changing state
*
* @return Operation status
*
* @note Processor had previously called self suspend and now PMU has
* received processor's wfi interrupt.
*/
static s32 PmProcTrSuspendToSleep(PmProc* const proc)
{
s32 status;
u32 worstCaseLatency = proc->pwrDnLatency + proc->pwrUpLatency;
PmInfo("%s susp->sleep\r\n", proc->node.name);
proc->node.latencyMarg = proc->latencyReq - worstCaseLatency;
status = PmProcSleep(proc);
if (XST_SUCCESS == status) {
PmNodeUpdateCurrState(&proc->node, PM_PROC_STATE_SLEEP);
/* Notify the master that the processor completed suspend */
status = PmMasterFsm(proc->master, PM_MASTER_EVENT_SLEEP);
/* If suspended, remember which processor to wake-up first */
if (true == (u8)PmMasterIsSuspended(proc->master)) {
proc->master->wakeProc = proc;
}
}
DISABLE_WFI(proc->mask);
ENABLE_WAKE(proc->mask);
return status;
}
/**
* PmProcTrSleepToActive() - FSM transition from sleep to active state
* @proc Pointer to processor whose FSM is changing state
*
* @return Operation status
*
* @note Processor had previously called self suspend and before it had
* executed wfi PMU has received PM API request to force power down
* of this processor. Therefore, PMU does not wait for wfi interrupt
* from this processor to come, but puts it to sleep.
*/
static s32 PmProcTrSleepToActive(PmProc* const proc)
{
s32 status;
PmInfo("%s sleep->active\r\n", proc->node.name);
status = PmProcWake(proc);
DISABLE_WAKE(proc->mask);
return status;
}
/**
* PmProcTrForcePwrdnToActive() - FSM transition from forced powerdown to active
* state
* @proc Pointer to processor whose FSM is changing state
*
* @return Operation status
*
* @note Processor had previously called self suspend and before it had
* executed wfi PMU has received PM API request to force power down
* of this processor. Therefore, PMU does not wait for wfi interrupt
* from this processor to come, but puts it to sleep.
*/
static s32 PmProcTrForcePwrdnToActive(PmProc* const proc)
{
s32 status;
PmInfo("%s forced off->active\r\n", proc->node.name);
status = PmProcWake(proc);
return status;
}
/**
* PmProcFsm() - Implements finite state machine (FSM) for a processor
* @proc Pointer to the processor the event is for
* @event Processor-specific event to act upon
*
* @return Status of the processor state change operation
*
* @note This FSM coordinates the state transitions for an individual
* processor.
*/
s32 PmProcFsm(PmProc* const proc, const PmProcEvent event)
{
s32 status = XST_PM_INTERNAL;
PmStateId currState = proc->node.currState;
switch (event) {
case PM_PROC_EVENT_SELF_SUSPEND:
if (PM_PROC_STATE_ACTIVE == currState) {
status = PmProcTrActiveToSuspend(proc);
}
break;
case PM_PROC_EVENT_FORCE_PWRDN:
if (PM_PROC_STATE_SUSPENDING == currState) {
DISABLE_WFI(proc->mask);
}
status = PmProcTrToForcedOff(proc);
/* Reset latency requirement */
proc->latencyReq = MAX_LATENCY;
break;
case PM_PROC_EVENT_ABORT_SUSPEND:
if (PM_PROC_STATE_SUSPENDING == currState) {
status = PmProcTrSuspendToActive(proc);
} else {
status = XST_SUCCESS;
}
if (true == (u8)PmIsRequestedToSuspend(proc->master)) {
status = PmMasterSuspendAck(proc->master,
XST_PM_ABORT_SUSPEND);
}
/* Reset latency requirement */
proc->latencyReq = MAX_LATENCY;
break;
case PM_PROC_EVENT_SLEEP:
if (PM_PROC_STATE_SUSPENDING == currState) {
status = PmProcTrSuspendToSleep(proc);
}
break;
case PM_PROC_EVENT_WAKE:
if (PM_PROC_STATE_SLEEP == currState) {
status = PmProcTrSleepToActive(proc);
} else if (PM_PROC_STATE_FORCEDOFF == currState) {
status = PmProcTrForcePwrdnToActive(proc);
} else if (PM_PROC_STATE_ACTIVE == currState) {
status = XST_SUCCESS;
} else if (PM_PROC_STATE_SUSPENDING == currState) {
status = XST_PM_CONFLICT;
} else {
}
/* Reset latency requirement */
proc->latencyReq = MAX_LATENCY;
break;
default:
PmErr("Unknown event %d\r\n", event);
break;
}
if (status == XST_PM_INTERNAL) {
PmErr("state #%d event #%d\r\n", currState, event);
}
return status;
}
/**
* PmProcGetByWakeMask() - Get processor struct by wake interrupt status mask
* @wake GIC wake mask read from GPI1 register
*
* @return Processor whose wake mask is provided as the argument
*/
PmProc* PmProcGetByWakeMask(const u32 wake)
{
PmProc* found = NULL;
u32 i;
for (i = 0U; i < pmNodeClassProc_g.bucketSize; i++) {
PmProc* proc = (PmProc*)pmNodeClassProc_g.bucket[i]->derived;
if (0U != (proc->mask & wake)) {
found = proc;
break;
}
}
return found;
}
/**
* PmProcClearConfig() - Clear configuration of the processor node
* @procNode Processor node
*/
static void PmProcClearConfig(PmNode* const procNode)
{
PmProc* const proc = (PmProc*)procNode->derived;
proc->latencyReq = MAX_LATENCY;
proc->resumeAddress = 0ULL;
proc->master = NULL;
PmProcDisableEvents(proc);
}
/**
* PmProcConstruct() - Constructor for the processor node
* @node Processor node
*/
static void PmProcConstruct(PmNode* const node)
{
PmProc* const proc = (PmProc*)node->derived;
PmProcDisableEvents(proc);
}
/**
* PmProcGetWakeUpLatency() - Get wake-up latency of the processor node
* @node Processor node whose wake-up latency should be get
* @lat Pointer to the location where the latency value should be stored
*
* @return XST_SUCCESS if latency value is stored in *lat, XST_NO_FEATURE
* if the latency depends on power parent which has no method
* (getWakeUpLatency) to provide latency information
*/
static s32 PmProcGetWakeUpLatency(const PmNode* const node, u32* const lat)
{
PmProc* const proc = (PmProc*)node->derived;
PmNode* const powerNode = &node->parent->node;
s32 status = XST_SUCCESS;
u32 latency = 0U;
*lat = 0U;
if (PM_PROC_STATE_ACTIVE == node->currState) {
goto done;
}
*lat = proc->pwrUpLatency;
if (PM_PROC_STATE_SUSPENDING == proc->node.currState) {
*lat += proc->pwrDnLatency;
goto done;
}
if (NULL == powerNode->class->getWakeUpLatency) {
status = XST_NO_FEATURE;
goto done;
}
status = powerNode->class->getWakeUpLatency(powerNode, &latency);
if (XST_SUCCESS == status) {
*lat += latency;
}
done:
return status;
}
/**
* PmProcForceDown() - Force down the processor node
* @node Processor node to force down
*
* @return Status of performing the force down operation
*/
static s32 PmProcForceDown(PmNode* const node)
{
PmProc* const proc = (PmProc*)node->derived;
s32 status = XST_SUCCESS;
if (PM_PROC_STATE_FORCEDOFF != node->currState) {
status = PmProcFsm(proc, PM_PROC_EVENT_FORCE_PWRDN);
}
return status;
}
#ifdef ENABLE_UNUSED_RPU_PWR_DWN
void PmForceDownUnusableRpuCores(void)
{
u32 value = Xil_In32(PMU_GLOBAL_GLOBAL_GEN_STORAGE4);
u32 mode;
/*
* If RPU core is not used then bit of PMU_GLOBAL_GLOBAL_GEN_STORAGE4
* for that core is cleared. So check that bit and force down that core.
*/
if (0U == (value & RPU0_STATUS_MASK)) {
PmProcForceDown(&pmProcRpu0_g.node);
}
if (0U == (value & RPU1_STATUS_MASK)) {
mode = XPfw_Read32(RPU_RPU_GLBL_CNTL);
/* For RPU lockstep mode RPU_1 is assumed to be always down */
if (0U == (mode & RPU_RPU_GLBL_CNTL_SLSPLIT_MASK)) {
PmProc *proc = &pmProcRpu1_g;
if (NULL != proc->node.parent) {
PmPowerReleaseParent(&proc->node);
}
if (NULL != proc->node.clocks) {
PmClockRelease(&proc->node);
}
if (NULL != proc->master) {
PmMasterFsm(proc->master,
PM_MASTER_EVENT_FORCED_PROC);
}
} else {
PmProcFsm(&pmProcRpu1_g, PM_PROC_EVENT_FORCE_PWRDN);
}
}
/* Mark RPU0 and RPU1 status as power down in RPU usage status bits */
XPfw_RMW32(PMU_GLOBAL_GLOBAL_GEN_STORAGE4,
RPU0_STATUS_MASK | RPU1_STATUS_MASK,
RPU0_STATUS_MASK | RPU1_STATUS_MASK);
}
#endif
/**
* PmProcInit() - Startup initialization of the processor node
* @node Node to initialize
*
* @return Status of initializing the node
*/
static s32 PmProcInit(PmNode* const node)
{
PmProc* const proc = (PmProc*)node->derived;
s32 status = XST_SUCCESS;
PmProcDisableEvents(proc);
if (NULL != proc->init) {
proc->init(proc);
}
if (PM_PROC_STATE_ACTIVE != node->currState) {
goto done;
}
if (NULL != node->parent) {
status = PmPowerRequestParent(node);
if (XST_SUCCESS != status) {
goto done;
}
}
if (NULL != node->clocks) {
status = PmClockRequest(node);
}
done:
return status;
}
/**
* PmProcIsUsable() - Check if processor is usable by the currently set config
* @node Processor node
*
* @return True if processor is usable, false otherwise
*/
static bool PmProcIsUsable(PmNode* const node)
{
bool usable = false;
PmProc* const proc = (PmProc*)node->derived;
/* Processor is usable if it has an associated master */
if (NULL != proc->master) {
usable = true;
}
return usable;
}
/**
* PmProcGetPerms() - Get permissions of masters to control processor clocks
* @node Target processor node
*
* @return IPI masks of the processor's master
*/
static u32 PmProcGetPerms(const PmNode* const node)
{
const PmProc* proc = (PmProc*)node->derived;
u32 perms = 0U;
if (NULL != proc->master) {
perms = proc->master->ipiMask;
}
return perms;
}
/* Power consumptions for the APU for specific states */
static u8 PmProcPowerAPU_X[] = {
DEFAULT_APU_POWER_OFF,
DEFAULT_APU_POWER_ACTIVE,
DEFAULT_APU_POWER_SLEEP,
DEFAULT_APU_POWER_SUSPENDING,
};
/* Power consumptions for the RPU for specific states */
static u8 PmProcPowerRPU_X[] = {
DEFAULT_RPU_POWER_OFF,
DEFAULT_RPU_POWER_ACTIVE,
DEFAULT_RPU_POWER_SLEEP,
DEFAULT_RPU_POWER_SUSPENDING,
};
/* Apu processors */
PmProc pmProcApu0_g = {
.node = {
.derived = &pmProcApu0_g,
.nodeId = NODE_APU_0,
.class = &pmNodeClassProc_g,
.parent = &pmPowerIslandApu_g,
.clocks = NULL,
.currState = PM_PROC_STATE_ACTIVE,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmProcPowerAPU_X),
DEFINE_NODE_NAME("apu0"),
},
.resumeAddress = 0ULL,
.master = NULL,
.saveResumeAddr = APUSaveResumeAddr,
.restoreResumeAddr = APURestoreResumeAddr,
.init = NULL,
.sleep = PmProcApu0Sleep,
.wake = PmProcApu0Wake,
.resumeCfg = APU_RVBARADDR0L,
.pwrDnReqAddr = APU_PWRCTL,
.pwrDnReqMask = 0x1U,
.latencyReq = MAX_LATENCY,
.pwrDnLatency = PM_POWER_ISLAND_LATENCY,
.pwrUpLatency = PM_POWER_ISLAND_LATENCY,
.mask = PMU_IOMODULE_GPI2_ACPU_0_SLEEP_MASK,
};
PmProc pmProcApu1_g = {
.node = {
.derived = &pmProcApu1_g,
.nodeId = NODE_APU_1,
.class = &pmNodeClassProc_g,
.parent = &pmPowerIslandApu_g,
.clocks = NULL,
.currState = PM_PROC_STATE_FORCEDOFF,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmProcPowerAPU_X),
DEFINE_NODE_NAME("apu1"),
},
.resumeAddress = 0ULL,
.master = NULL,
.saveResumeAddr = APUSaveResumeAddr,
.restoreResumeAddr = APURestoreResumeAddr,
.init = NULL,
.sleep = PmProcApu1Sleep,
.wake = PmProcApu1Wake,
.resumeCfg = APU_RVBARADDR1L,
.pwrDnReqAddr = APU_PWRCTL,
.pwrDnReqMask = 0x2U,
.latencyReq = MAX_LATENCY,
.pwrDnLatency = PM_POWER_ISLAND_LATENCY,
.pwrUpLatency = PM_POWER_ISLAND_LATENCY,
.mask = PMU_IOMODULE_GPI2_ACPU_1_SLEEP_MASK,
};
PmProc pmProcApu2_g = {
.node = {
.derived = &pmProcApu2_g,
.nodeId = NODE_APU_2,
.class = &pmNodeClassProc_g,
.parent = &pmPowerIslandApu_g,
.clocks = NULL,
.currState = PM_PROC_STATE_FORCEDOFF,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmProcPowerAPU_X),
DEFINE_NODE_NAME("apu2"),
},
.resumeAddress = 0ULL,
.master = NULL,
.saveResumeAddr = APUSaveResumeAddr,
.restoreResumeAddr = APURestoreResumeAddr,
.init = NULL,
.sleep = PmProcApu2Sleep,
.wake = PmProcApu2Wake,
.resumeCfg = APU_RVBARADDR2L,
.pwrDnReqAddr = APU_PWRCTL,
.pwrDnReqMask = 0x4U,
.latencyReq = MAX_LATENCY,
.pwrDnLatency = PM_POWER_ISLAND_LATENCY,
.pwrUpLatency = PM_POWER_ISLAND_LATENCY,
.mask = PMU_IOMODULE_GPI2_ACPU_2_SLEEP_MASK,
};
PmProc pmProcApu3_g = {
.node = {
.derived = &pmProcApu3_g,
.nodeId = NODE_APU_3,
.class = &pmNodeClassProc_g,
.parent = &pmPowerIslandApu_g,
.clocks = NULL,
.currState = PM_PROC_STATE_FORCEDOFF,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmProcPowerAPU_X),
DEFINE_NODE_NAME("apu3"),
},
.resumeAddress = 0ULL,
.master = NULL,
.saveResumeAddr = APUSaveResumeAddr,
.restoreResumeAddr = APURestoreResumeAddr,
.init = NULL,
.sleep = PmProcApu3Sleep,
.wake = PmProcApu3Wake,
.resumeCfg = APU_RVBARADDR3L,
.pwrDnReqAddr = APU_PWRCTL,
.pwrDnReqMask = 0x8U,
.latencyReq = MAX_LATENCY,
.pwrDnLatency = PM_POWER_ISLAND_LATENCY,
.pwrUpLatency = PM_POWER_ISLAND_LATENCY,
.mask = PMU_IOMODULE_GPI2_ACPU_3_SLEEP_MASK,
};
/* Rpu processors */
PmProc pmProcRpu0_g = {
.node = {
.derived = &pmProcRpu0_g,
.nodeId = NODE_RPU_0,
.class = &pmNodeClassProc_g,
.parent = &pmPowerIslandRpu_g.power,
.clocks = NULL,
.currState = PM_PROC_STATE_ACTIVE,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmProcPowerRPU_X),
DEFINE_NODE_NAME("rpu0"),
},
.resumeAddress = 0ULL,
.master = NULL,
.saveResumeAddr = RPUSaveResumeAddr,
.restoreResumeAddr = RPURestoreResumeAddr,
.init = NULL,
.sleep = PmProcRpu0Sleep,
.wake = PmProcRpu0Wake,
.resumeCfg = RPU_RPU_0_CFG,
.pwrDnReqAddr = RPU_RPU_0_PWRDWN,
.pwrDnReqMask = RPU_RPU_0_PWRDWN_EN_MASK,
.latencyReq = MAX_LATENCY,
.pwrDnLatency = 0U,
.pwrUpLatency = 0U,
.mask = PMU_IOMODULE_GPI2_R5_0_SLEEP_MASK,
};
PmProc pmProcRpu1_g = {
.node = {
.derived = &pmProcRpu1_g,
.nodeId = NODE_RPU_1,
.class = &pmNodeClassProc_g,
.parent = &pmPowerIslandRpu_g.power,
.clocks = NULL,
.currState = PM_PROC_STATE_ACTIVE,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmProcPowerRPU_X),
DEFINE_NODE_NAME("rpu1"),
},
.resumeAddress = 0ULL,
.master = NULL,
.saveResumeAddr = RPUSaveResumeAddr,
.restoreResumeAddr = RPURestoreResumeAddr,
.init = PmProcRpu1Init,
.sleep = PmProcRpu1Sleep,
.wake = PmProcRpu1Wake,
.resumeCfg = RPU_RPU_1_CFG,
.pwrDnReqAddr = RPU_RPU_1_PWRDWN,
.pwrDnReqMask = RPU_RPU_1_PWRDWN_EN_MASK,
.latencyReq = MAX_LATENCY,
.pwrDnLatency = 0U,
.pwrUpLatency = 0U,
.mask = PMU_IOMODULE_GPI2_R5_1_SLEEP_MASK,
};
/* Collection of processor nodes */
static PmNode* pmNodeProcBucket[] = {
&pmProcApu0_g.node,
&pmProcApu1_g.node,
&pmProcApu2_g.node,
&pmProcApu3_g.node,
&pmProcRpu0_g.node,
&pmProcRpu1_g.node,
};
PmNodeClass pmNodeClassProc_g = {
.clearConfig = PmProcClearConfig,
.construct = PmProcConstruct,
.getWakeUpLatency = PmProcGetWakeUpLatency,
.getPowerData = PmNodeGetPowerInfo,
.forceDown = PmProcForceDown,
.init = PmProcInit,
.isUsable = PmProcIsUsable,
.getPerms = PmProcGetPerms,
DEFINE_NODE_BUCKET(pmNodeProcBucket),
.id = NODE_CLASS_PROC,
};
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_node.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* Global array of all nodes, and GetbyId function
*********************************************************************/
#include "pm_node.h"
#include "pm_power.h"
#include "pm_proc.h"
#include "pm_slave.h"
#include "pm_notifier.h"
#include "pm_clock.h"
static PmNodeClass* pmNodeClasses[] = {
&pmNodeClassProc_g,
&pmNodeClassPower_g,
&pmNodeClassSlave_g,
&pmNodeClassPll_g,
};
/**
* PmGetNodeById() - Find node that matches a given node ID
* @nodeId ID of the node to find
*
* @returns Pointer to PmNode structure (or NULL if not found)
*/
PmNode* PmGetNodeById(const u32 nodeId)
{
u32 i, n;
PmNode* node = NULL;
for (i = 0U; i < ARRAY_SIZE(pmNodeClasses); i++) {
for (n = 0U; n < pmNodeClasses[i]->bucketSize; n++) {
if (nodeId == pmNodeClasses[i]->bucket[n]->nodeId) {
node = pmNodeClasses[i]->bucket[n];
goto done;
}
}
}
done:
return node;
}
/**
* PmNodeUpdateCurrState() - Call to update currState variable of the node
* @node Pointer to the node whose state has to be updated
* @newState New state value to be written in currState variable of the node
*/
void PmNodeUpdateCurrState(PmNode* const node, const PmStateId newState)
{
if (newState == node->currState) {
goto done;
}
/*
* Clear NODE_IDLE_DONE flag, if current state of node is OFF and
* new state is other than OFF.
*/
if (NODE_IS_OFF(node)) {
node->flags &= ~NODE_IDLE_DONE;
}
node->currState = newState;
PmNotifierEvent(node, EVENT_STATE_CHANGE);
done:
return;
}
/**
* PmNodeGetPowerInfo() - Get power consumption information for a node
* @node Pointer to the node
* @data Pointer to the location where the power info should be stored
*
* @returns Status about returning power info
* XST_SUCCESS if power info is stored in *data
* XST_NO_FEATURE if no power info can be provided for the node
*/
s32 PmNodeGetPowerInfo(const PmNode* const node, u32* const data)
{
s32 status = XST_SUCCESS;
if (NULL == node->powerInfo) {
status = XST_NO_FEATURE;
goto done;
}
*data = node->powerInfo[node->currState];
done:
return status;
}
/**
* PmNodeGetClassById() - Get node class by class ID
* @id ID of the class to get
*
* @return Pointer to class if found, NULL otherwise.
*/
static PmNodeClass* PmNodeGetClassById(const u8 id)
{
u32 i;
PmNodeClass* class = NULL;
for (i = 0U; i < ARRAY_SIZE(pmNodeClasses); i++) {
if (id == pmNodeClasses[i]->id) {
class = pmNodeClasses[i];
break;
}
}
return class;
}
/**
* PmNodeGetFromClass() - Get node with given ID from class
* @class Node class to search through
* @nid ID of the node to get
*
* @return Pointer to node if found, NULL otherwise.
*/
static PmNode* PmNodeGetFromClass(const PmNodeClass* const class, const u8 nid)
{
u32 i;
PmNode* node = NULL;
for (i = 0U; i < class->bucketSize; i++) {
if (nid == class->bucket[i]->nodeId) {
node = class->bucket[i];
break;
}
}
return node;
}
/**
* PmNodeGetDerived() - Get pointer to the derived structure of the node
* @nodeClass Node class
* @nodeId ID of the node
*
* @return Pointer to the derived node object if found, NULL otherwise
*/
void* PmNodeGetDerived(const u8 nodeClass, const u32 nodeId)
{
void* ptr = NULL;
PmNode* node = NULL;
PmNodeClass* class = PmNodeGetClassById(nodeClass);
if (NULL != class) {
node = PmNodeGetFromClass(class, nodeId);
}
if (NULL != node) {
ptr = node->derived;
}
return ptr;
}
/**
* PmNodeClearConfig() - Clear configuration for all nodes
*/
void PmNodeClearConfig(void)
{
u32 i, n;
for (i = 0U; i < ARRAY_SIZE(pmNodeClasses); i++) {
for (n = 0U; n < pmNodeClasses[i]->bucketSize; n++) {
PmNode* node = pmNodeClasses[i]->bucket[n];
node->latencyMarg = MAX_LATENCY;
node->flags = 0U;
if (NULL != pmNodeClasses[i]->clearConfig) {
pmNodeClasses[i]->clearConfig(node);
}
}
}
}
/**
* PmNodeConstruct() - Call constructors for all nodes
*/
void PmNodeConstruct(void)
{
u32 i, n;
PmClockConstructList();
for (i = 0U; i < ARRAY_SIZE(pmNodeClasses); i++) {
for (n = 0U; n < pmNodeClasses[i]->bucketSize; n++) {
PmNode* node = pmNodeClasses[i]->bucket[n];
if (NULL != pmNodeClasses[i]->construct) {
pmNodeClasses[i]->construct(node);
}
}
}
}
/**
* PmNodeInit() - Initialize all nodes
* @return XST_SUCCESS or error code if failed to initialize a node
*/
s32 PmNodeInit(void)
{
u32 i, n;
s32 status;
s32 ret = XST_SUCCESS;
PmClockInit();
for (i = 0U; i < ARRAY_SIZE(pmNodeClasses); i++) {
for (n = 0U; n < pmNodeClasses[i]->bucketSize; n++) {
PmNode* node = pmNodeClasses[i]->bucket[n];
if (NULL == pmNodeClasses[i]->init) {
continue;
}
status = pmNodeClasses[i]->init(node);
if (XST_SUCCESS != status) {
ret = XST_FAILURE;
PmErr("init %s failed\r\n", node->name);
}
}
}
return ret;
}
/**
* PmNodeForceDown() - Force down the node
* @node Node to force down
*
* @return XST_FAILURE if no force operation to execute for the node,
* otherwise status of performing force down operation
*/
s32 PmNodeForceDown(PmNode* const node)
{
s32 status = XST_FAILURE;
if (NULL != node->class->forceDown) {
status = node->class->forceDown(node);
}
return status;
}
/**
* PmNodeForceDownUnusable() - Force down nodes that are unusable
*
* @note Function puts in the lowest power states the nodes which have no
* provision to be used by currently set configuration.
*/
void PmNodeForceDownUnusable(void)
{
u32 i, n;
for (i = 0U; i < ARRAY_SIZE(pmNodeClasses); i++) {
for (n = 0U; n < pmNodeClasses[i]->bucketSize; n++) {
PmNode* node = pmNodeClasses[i]->bucket[n];
bool usable = true;
if (NULL != pmNodeClasses[i]->isUsable) {
usable = pmNodeClasses[i]->isUsable(node);
}
if (true == usable) {
continue;
}
if (NULL != pmNodeClasses[i]->forceDown) {
pmNodeClasses[i]->forceDown(node);
}
}
}
}
/**
* PmNodeLogUnknownState() - Log an unknown state error for a given node
* @node Node pointer
*/
void PmNodeLogUnknownState(const PmNode* const node, const PmStateId state)
{
PmErr("Unknown %s state #%u\r\n", node->name, state);
}
/**
* PmNodeGetPermissions() - Get permissions of masters to control node's clocks
* @node Target node
*
* @return Zero if no master has permission or node class does not
* implement get permissions method. ORed ipi masks of masters
* that have permissions otherwise.
*/
u32 PmNodeGetPermissions(PmNode* const node)
{
u32 perms = 0U;
if (NULL != node->class->getPerms) {
perms = node->class->getPerms(node);
}
return perms;
}
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_mod_ultra96.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_default.h"
#include "xpfw_config.h"
#include "xpfw_core.h"
#include "xpfw_module.h"
#include "xpfw_mod_ultra96.h"
#ifdef ENABLE_MOD_ULTRA96
#ifndef ENABLE_SCHEDULER
#error "ERROR: Ultra96 module requires scheduler to be enabled! Define ENABLE_SCHEDULER"
#endif
#ifndef ENABLE_PM
#error "ERROR: Ultra96 module requires PM module to be enabled! Define ENABLE_PM"
#endif
#ifdef ULTRA96_VERSION
#if ULTRA96_VERSION == 1
#define PWR_BTN_POLL_MASK 0U
#elif ULTRA96_VERSION == 2
#define PWR_BTN_POLL_MASK PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK
#else
#error "Unsupported ULTRA96_VERSION specified"
#endif
#else
#define PWR_BTN_POLL_MASK 0U
#endif
#include "pm_core.h"
#include "pm_master.h"
#include "pm_callbacks.h"
#include "pm_config.h"
#include "rpu.h"
/*
* Define the interval at which the power button input is polled
* This period should be a minimum of 10ms and multiples thereof, as per the scheduler configuration
*/
#define ULTRA96_PWR_BTN_POLL_PERIOD_MS 10U
const XPfw_Module_t *Ultra96ModPtr;
static void Ultra96PowerButtonHandler(void)
{
/*
* Don't check for the pin state if PM config is not yet loaded
* This also means that FSBL is not yet running, MIO is not configured and we don't have the IPI info
*/
if(!PmConfigObjectIsLoaded()) {
return;
}
/* Check if Power Button pin is Active*/
if((XPfw_Read32(PMU_IOMODULE_GPI1) & PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK) == PWR_BTN_POLL_MASK) {
/* Do a second check on the pin to mitigate sub-microsecond glitches, if any */
if ((XPfw_Read32(PMU_IOMODULE_GPI1) & PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK) != PWR_BTN_POLL_MASK) {
/* If the pin is still not active, don't initiate a power down. Just return. */
return;
}
/* Start Board Power Down Sequence. First Remove the pin polling task from scheduler
* to prevent re-triggering when shutdown is in progress
*/
XPfw_CoreRemoveTask(Ultra96ModPtr, ULTRA96_PWR_BTN_POLL_PERIOD_MS, Ultra96PowerButtonHandler);
/* Initiate Shutdown for all masters in the system */
/* TODO: All the PM related calls below should be wrapped into a single API
* like PmIntiateSystemShutdown in PM Module and this module needs to call it.
*/
u32 rpu_mode = XPfw_Read32(RPU_RPU_GLBL_CNTL);
/* APU */
if (PM_MASTER_STATE_ACTIVE == PmMasterIsActive(&pmMasterApu_g)) {
PmInitSuspendCb(&pmMasterApu_g,
SUSPEND_REASON_SYS_SHUTDOWN, 1, 0, 0);
}
/* RPU Split Mode */
if (0U == (rpu_mode & RPU_RPU_GLBL_CNTL_SLSPLIT_MASK)) {
if (PM_MASTER_STATE_ACTIVE == PmMasterIsActive(&pmMasterRpu0_g)) {
PmInitSuspendCb(&pmMasterRpu0_g,
SUSPEND_REASON_SYS_SHUTDOWN, 1, 0, 0);
}
if (PM_MASTER_STATE_ACTIVE == PmMasterIsActive(&pmMasterRpu1_g)) {
PmInitSuspendCb(&pmMasterRpu1_g,
SUSPEND_REASON_SYS_SHUTDOWN, 1, 0, 0);
}
} else {
/* RPU Lockstep Mode */
if (PM_MASTER_STATE_ACTIVE == PmMasterIsActive(&pmMasterRpu_g)) {
PmInitSuspendCb(&pmMasterRpu_g,
SUSPEND_REASON_SYS_SHUTDOWN, 1, 0, 0);
}
}
}
}
static void Ultra96CfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
{
s32 Status;
Status = XPfw_CoreScheduleTask(ModPtr, ULTRA96_PWR_BTN_POLL_PERIOD_MS, Ultra96PowerButtonHandler);
if (XST_FAILURE == Status) {
XPfw_Printf(DEBUG_ERROR,"Ultra96 (MOD-%d):Scheduling MIO Poll task failed.",
ModPtr->ModId);
}
}
void ModUltra96Init(void)
{
Ultra96ModPtr = XPfw_CoreCreateMod();
if (XST_SUCCESS != XPfw_CoreSetCfgHandler(Ultra96ModPtr,Ultra96CfgInit)) {
XPfw_Printf(DEBUG_DETAILED,"Ultra96: Set Cfg handler failed\r\n");
}
}
#else /* ENABLE_MOD_ULTRA96 */
void ModUltra96Init(void) { }
#endif /* ENABLE_MOD_ULTRA96 */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/zynqmp/client/common/pm_callbacks.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file pm_callbacks.h
*
* Callbacks implementation - for xilpm internal purposes only
*****************************************************************************/
#ifndef XILPM_CALLBACKS_H_
#define XILPM_CALLBACKS_H_
#include <xil_types.h>
#include <xstatus.h>
#include "pm_defs.h"
#include "pm_api_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
XStatus XPm_NotifierAdd(XPm_Notifier* const notifier);
XStatus XPm_NotifierRemove(XPm_Notifier* const notifier);
void XPm_NotifierProcessEvent(const enum XPmNodeId node,
const enum XPmNotifyEvent event,
const u32 oppoint);
#ifdef __cplusplus
}
#endif
#endif /* XILPM_CALLBACKS_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_core.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* Contains the function to call for processing a PM API call.
* The function (PmProcessRequest) is called from interrupt handler
* stubs, implemented in pm_binding files. The request is further
* processed according to the master that initiated request and
* API call's payload read from master's IPI buffer.
********************************************************************/
#ifndef PM_CORE_H_
#define PM_CORE_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_master.h"
#include "xil_types.h"
/*********************************************************************
* Function declarations
********************************************************************/
void PmProcessRequest(PmMaster *const master, const u32 *pload);
void PmResetAssert(const PmMaster *const master, const u32 reset,
const u32 action);
void PmShutdownInterruptHandler(void);
#ifdef __cplusplus
}
#endif
#endif /* PM_CORE_H_ */
<file_sep>/c_drivers/drivers_old_pre_gpio_debug/gpio.c
#include "gpio.h"
#define PULSE_GEN_CHANNEL 1
#define GPIO_BITWIDTH 16 /* This is the width of the GPIO */
#define GPIO_OUTPUT_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID
XGpioPs GpioInst; /* The driver instance for GPIO Device configured as O/P */
#define RST_BIT 3
#define WRITE_BIT 2
#define SCLK_BIT 0
#define SDATA_BIT 1
uint8_t gpio_init()
{
int Status;
XGpioPs_Config *ConfigPtr;
/* Initialize the GPIO driver. */
ConfigPtr = XGpioPs_LookupConfig(GPIO_OUTPUT_DEVICE_ID);
if(!ConfigPtr)
{
return XST_FAILURE;
}
Status = XGpioPs_CfgInitialize(&GpioInst, ConfigPtr,
ConfigPtr->BaseAddr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
//Set all pins to be outputs
for(int i = 0; i < 32; i++){
XGpioPs_SetDirectionPin(&GpioInst, i, 1);
XGpioPs_SetOutputEnablePin(&GpioInst, i, 1);
}
//Reset the fabric
gpio_reset_pulse_gen();
return XST_SUCCESS;
}
void gpio_set_pin(u8 pin_num, u8 value)
{
if(value){
XGpioPs_WritePin(&GpioInst, pin_num, 0x1);
}
else
{
XGpioPs_WritePin(&GpioInst, pin_num, 0x0);
}
}
//Resets the fabric in the 250MHz clock domain
void gpio_reset_pulse_gen(u32 value)
{
//Mask out the reset bit (active low)
gpio_set_pin(RST_BIT, 0);
gpio_set_pin(RST_BIT, 1);
}
//Sends a command to the pulse generator RTL via FIFO
void gpio_send_commnd(uint32_t value)
{
//First shift the command into the register
for(int i = 0; i < 32; i++)
{
//Set the output to the correct bit
u8 current_bit = (value & (1 << i)) == 0 ? 0 : 1;
gpio_set_pin(SDATA_BIT, current_bit);
//cycle the cycles sclk
gpio_set_pin(SCLK_BIT, 0x01);
gpio_set_pin(SCLK_BIT, 0x00);
}
//Then write the command into the fifo
gpio_set_pin(WRITE_BIT, 0x01);
gpio_set_pin(WRITE_BIT, 0x00);
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilfpga_v5_2/src/interface/versal/xilfpga_versal.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilfpga_versal.c
*
* This file contains the definitions of bitstream loading functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- ----- -------- -------------------------------------------------------
* 5.2 Nava 05/12/19 Added Versal platform support.
* 5.2 Nava 27/02/20 Updated the write path to read the pdi/bin image ipi
* load response to handle the pdi/bin image load
* errors properly.
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xilfpga.h"
#include "xilmailbox.h"
/************************** Constant Definitions *****************************/
#define PDI_LOAD 0x30701U
#define DELAYED_PDI_LOAD 0x30702U
#define LOAD_PDI_MSG_LEN 0x4U
#define FPGA_IPI_RESP1 0x1U
#define XMAILBOX_DEVICE_ID 0x0U
#define FPGA_PDI_SRC_DDR 0xFU
#define FPGA_IPI_TYPE_BLOCKING 0x1U
#define PDI_LOAD_TYPE_MASK BIT(0)
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static u32 XFpga_WriteToPl(XFpga *InstancePtr);
/************************** Variable Definitions *****************************/
XMailbox XMboxInstance;
static u32 ReqBuffer[LOAD_PDI_MSG_LEN];
/*****************************************************************************/
/* This API when called initializes the XFPGA interface with default settings.
* It Sets function pointers for the instance.
*
* @param InstancePtr Pointer to the XFgpa structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
******************************************************************************/
u32 XFpga_Initialize(XFpga *InstancePtr) {
(void)memset(InstancePtr, 0U, sizeof(*InstancePtr));
InstancePtr->XFpga_WriteToPl = XFpga_WriteToPl;
return XFPGA_SUCCESS;
}
/*****************************************************************************/
/* This function writes bitstream data into the PL.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_WriteToPl(XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
UINTPTR BitstreamAddr = InstancePtr->WriteInfo.BitstreamAddr;
Status = XMailbox_Initialize(&XMboxInstance, XMAILBOX_DEVICE_ID);
if (Status != XST_SUCCESS) {
goto END;
}
if (InstancePtr->WriteInfo.Flags & PDI_LOAD_TYPE_MASK) {
ReqBuffer[0U] = DELAYED_PDI_LOAD;
ReqBuffer[1U] = (u32)BitstreamAddr; /* Image ID */
} else {
ReqBuffer[0U] = PDI_LOAD;
ReqBuffer[1U] = FPGA_PDI_SRC_DDR;
ReqBuffer[2U] = UPPER_32_BITS(BitstreamAddr);
ReqBuffer[3U] = LOWER_32_BITS(BitstreamAddr);
}
/* Send an IPI Req Message */
Status = XMailbox_SendData(&XMboxInstance, XMAILBOX_IPIPMC, ReqBuffer,
LOAD_PDI_MSG_LEN, XILMBOX_MSG_TYPE_REQ,
FPGA_IPI_TYPE_BLOCKING);
if (Status != XST_SUCCESS) {
xil_printf("Sending Req Message Failed\n\r");
goto END;
}
Status = XMailbox_Recv(&XMboxInstance, XMAILBOX_IPIPMC, ReqBuffer,
FPGA_IPI_RESP1, XILMBOX_MSG_TYPE_RESP);
if (Status == XST_SUCCESS) {
Status = ReqBuffer[0U];
}
END:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/rsa_core.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _RSA_CORE_H_
#define _RSA_CORE_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* RSA_CORE Base Address
*/
#define RSA_CORE_BASEADDR 0XFFCE0000
/**
* Register: RSA_CORE_RSA_WR_DATA
*/
#define RSA_CORE_RSA_WR_DATA ( ( RSA_CORE_BASEADDR ) + 0X00000000 )
#define RSA_CORE_RSA_WR_DATA_WR_DATA_SHIFT 0
#define RSA_CORE_RSA_WR_DATA_WR_DATA_WIDTH 8
#define RSA_CORE_RSA_WR_DATA_WR_DATA_MASK 0X000000FF
/**
* Register: RSA_CORE_RSA_WR_ADDR
*/
#define RSA_CORE_RSA_WR_ADDR ( ( RSA_CORE_BASEADDR ) + 0X00000004 )
#define RSA_CORE_RSA_WR_ADDR_WR_ADDR_SHIFT 0
#define RSA_CORE_RSA_WR_ADDR_WR_ADDR_WIDTH 7
#define RSA_CORE_RSA_WR_ADDR_WR_ADDR_MASK 0X0000007F
/**
* Register: RSA_CORE_RSA_RD_DATA
*/
#define RSA_CORE_RSA_RD_DATA ( ( RSA_CORE_BASEADDR ) + 0X00000008 )
#define RSA_CORE_RSA_RD_DATA_RD_DATA_SHIFT 0
#define RSA_CORE_RSA_RD_DATA_RD_DATA_WIDTH 8
#define RSA_CORE_RSA_RD_DATA_RD_DATA_MASK 0X000000FF
/**
* Register: RSA_CORE_RSA_RD_ADDR
*/
#define RSA_CORE_RSA_RD_ADDR ( ( RSA_CORE_BASEADDR ) + 0X0000000C )
#define RSA_CORE_RSA_RD_ADDR_RD_ADDR_SHIFT 0
#define RSA_CORE_RSA_RD_ADDR_RD_ADDR_WIDTH 7
#define RSA_CORE_RSA_RD_ADDR_RD_ADDR_MASK 0X0000007F
/**
* Register: RSA_CORE_CTRL
*/
#define RSA_CORE_CTRL ( ( RSA_CORE_BASEADDR ) + 0X00000010 )
#define RSA_CORE_CTRL_LEN_CODE_SHIFT 4
#define RSA_CORE_CTRL_LEN_CODE_WIDTH 4
#define RSA_CORE_CTRL_LEN_CODE_MASK 0X000000F0
#define RSA_CORE_CTRL_DONE_CLR_ABORT_SHIFT 3
#define RSA_CORE_CTRL_DONE_CLR_ABORT_WIDTH 1
#define RSA_CORE_CTRL_DONE_CLR_ABORT_MASK 0X00000008
#define RSA_CORE_CTRL_OPCODE_SHIFT 0
#define RSA_CORE_CTRL_OPCODE_WIDTH 3
#define RSA_CORE_CTRL_OPCODE_MASK 0X00000007
/**
* Register: RSA_CORE_STATUS
*/
#define RSA_CORE_STATUS ( ( RSA_CORE_BASEADDR ) + 0X00000014 )
#define RSA_CORE_STATUS_PROG_CNT_SHIFT 3
#define RSA_CORE_STATUS_PROG_CNT_WIDTH 5
#define RSA_CORE_STATUS_PROG_CNT_MASK 0X000000F8
#define RSA_CORE_STATUS_ERROR_SHIFT 2
#define RSA_CORE_STATUS_ERROR_WIDTH 1
#define RSA_CORE_STATUS_ERROR_MASK 0X00000004
#define RSA_CORE_STATUS_BUSY_SHIFT 1
#define RSA_CORE_STATUS_BUSY_WIDTH 1
#define RSA_CORE_STATUS_BUSY_MASK 0X00000002
#define RSA_CORE_STATUS_DONE_SHIFT 0
#define RSA_CORE_STATUS_DONE_WIDTH 1
#define RSA_CORE_STATUS_DONE_MASK 0X00000001
/**
* Register: RSA_CORE_MINV0
*/
#define RSA_CORE_MINV0 ( ( RSA_CORE_BASEADDR ) + 0X00000018 )
#define RSA_CORE_MINV0_MINV0_SHIFT 0
#define RSA_CORE_MINV0_MINV0_WIDTH 8
#define RSA_CORE_MINV0_MINV0_MASK 0X000000FF
/**
* Register: RSA_CORE_MINV1
*/
#define RSA_CORE_MINV1 ( ( RSA_CORE_BASEADDR ) + 0X0000001C )
#define RSA_CORE_MINV1_MINV1_SHIFT 0
#define RSA_CORE_MINV1_MINV1_WIDTH 8
#define RSA_CORE_MINV1_MINV1_MASK 0X000000FF
/**
* Register: RSA_CORE_MINV2
*/
#define RSA_CORE_MINV2 ( ( RSA_CORE_BASEADDR ) + 0X00000020 )
#define RSA_CORE_MINV2_MINV2_SHIFT 0
#define RSA_CORE_MINV2_MINV2_WIDTH 8
#define RSA_CORE_MINV2_MINV2_MASK 0X000000FF
/**
* Register: RSA_CORE_MINV3
*/
#define RSA_CORE_MINV3 ( ( RSA_CORE_BASEADDR ) + 0X00000024 )
#define RSA_CORE_MINV3_MINV2_SHIFT 0
#define RSA_CORE_MINV3_MINV2_WIDTH 8
#define RSA_CORE_MINV3_MINV2_MASK 0X000000FF
#ifdef __cplusplus
}
#endif
#endif /* _RSA_CORE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_pinctrl.h
/*
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#ifndef PM_PINCTRL_H_
#define PM_PINCTRL_H_
#ifdef __cplusplus
extern "C" {
#endif
s32 PmPinCtrlRequestInt(const u32 ipiMask, const u32 pinId);
s32 PmPinCtrlReleaseInt(const u32 ipiMask, const u32 pinId);
s32 PmPinCtrlGetFunctionInt(const u32 pinId, u32* const fnId);
s32 PmPinCtrlSetFunctionInt(const PmMaster* const master, const u32 pinId,
const u32 fnId);
s32 PmPinCtrlCheckPerms(const u32 ipiMask, const u32 pinId);
s32 PmPinCtrlGetParam(const u32 pinId, const u32 paramId, u32* const value);
s32 PmPinCtrlSetParam(const u32 pinId, const u32 paramId, const u32 value);
#ifdef __cplusplus
}
#endif
#endif /* PM_PINCTRL_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_device_idle.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_device_idle.h"
#include "xpm_common.h"
#define XPM_MAX_TIMEOUT (0x1FFFFFFF)
static XPmDevice_SoftResetInfo DeviceRstData[] = {
#ifdef XPAR_XUSBPSU_0_DEVICE_ID
{
.DeviceId = PM_DEV_USB_0,
.SoftRst = NULL,
.IdleHook = NodeUsbIdle,
.IdleHookArgs = XPAR_XUSBPSU_0_DEVICE_ID,
},
#endif
#ifdef XPAR_PSV_ETHERNET_0_DEVICE_ID
{
.DeviceId = PM_DEV_GEM_0,
.SoftRst = NULL,
.IdleHook = NodeGemIdle,
.IdleHookArgs = XPAR_PSV_ETHERNET_0_DEVICE_ID,
},
#endif
#ifdef XPAR_PSV_ETHERNET_1_DEVICE_ID
{
.DeviceId = PM_DEV_GEM_1,
.SoftRst = NULL,
.IdleHook = NodeGemIdle,
.IdleHookArgs = XPAR_PSV_ETHERNET_1_DEVICE_ID,
},
#endif
#ifdef XPAR_PSV_OSPI_0_DEVICE_ID
{
.DeviceId = PM_DEV_OSPI,
.SoftRst = NULL,
.IdleHook = NodeOspiIdle,
.IdleHookArgs = XPAR_PSV_OSPI_0_DEVICE_ID,
},
#endif
#ifdef XPAR_PSV_QSPI_0_DEVICE_ID
{
.DeviceId = PM_DEV_QSPI,
.SoftRst = NULL,
.IdleHook = NodeQspiIdle,
.IdleHookArgs = XPAR_PSV_QSPI_0_DEVICE_ID,
},
#endif
#ifdef XPAR_PSV_SD_0_DEVICE_ID
{
.DeviceId = PM_DEV_SDIO_0,
.SoftRst = NULL,
.IdleHook = NodeSdioIdle,
.IdleHookArgs = XPAR_PSV_SD_0_DEVICE_ID,
},
#endif
#ifdef XPAR_PSV_SD_1_DEVICE_ID
{
.DeviceId = PM_DEV_SDIO_1,
.SoftRst = NULL,
.IdleHook = NodeSdioIdle,
.IdleHookArgs = XPAR_PSV_SD_1_DEVICE_ID,
},
#endif
};
#if defined(XPAR_PSV_QSPI_0_DEVICE_ID)
/**
* NodeQspiIdle() - Idle the QSPI node
*
* @DeviceId: Device ID of QSPI node
* @BaseAddress: QSPI base address
*/
void NodeQspiIdle(u16 DeviceId, u32 BaseAddress)
{
int Status = XST_FAILURE;
XQspiPsu_Config *ConfigPtr;
XQspiPsu QspiInst = {0};
ConfigPtr = XQspiPsu_LookupConfig(DeviceId);
if (NULL == ConfigPtr) {
goto done;
}
Status = XQspiPsu_CfgInitialize(&QspiInst, ConfigPtr, BaseAddress);
if (XST_SUCCESS != Status) {
goto done;
}
XQspiPsu_Idle(&QspiInst);
done:
return;
}
#endif
#if defined(XPAR_PSV_OSPI_0_DEVICE_ID)
/**
* NodeQspiIdle() - Idle the OSPI node
*
* @DeviceId: Device ID of OSPI node
* @BaseAddress: OSPI base address
*/
void NodeOspiIdle(u16 DeviceId, u32 BaseAddress)
{
int Status = XST_FAILURE;
XOspiPsv_Config *ConfigPtr;
XOspiPsv OspiInst = {0};
/* Warning Fix */
(void)(BaseAddress);
ConfigPtr = XOspiPsv_LookupConfig(DeviceId);
if (NULL == ConfigPtr) {
goto done;
}
Status = XOspiPsv_CfgInitialize(&OspiInst, ConfigPtr);
if (XST_SUCCESS != Status) {
goto done;
}
XOspiPsv_Idle(&OspiInst);
done:
return;
}
#endif
#if defined(XPAR_PSV_SD_0_DEVICE_ID) || defined(XPAR_PSV_SD_1_DEVICE_ID)
/**
* NodeSdioIdle() - Idle the SDIO node
*
* @DeviceId: Device ID of SDIO node
* @BaseAddress: SDIO base address
*/
void NodeSdioIdle(u16 DeviceId, u32 BaseAddress)
{
int Status = XST_FAILURE;
XSdPs_Config *ConfigPtr;
XSdPs SdioInst = {0};
ConfigPtr = XSdPs_LookupConfig(DeviceId);
if (NULL == ConfigPtr) {
goto done;
}
Status = XSdPs_CfgInitialize(&SdioInst, ConfigPtr, BaseAddress);
if (XST_SUCCESS != Status) {
goto done;
}
XSdPs_Idle(&SdioInst);
done:
return;
}
#endif
#if defined(XPAR_XUSBPSU_0_DEVICE_ID)
/**
* NodeUsbIdle() - Idle the USB node
*
* @DeviceId: Device ID of USB node
* @BaseAddress: USB base address
*/
void NodeUsbIdle(u16 DeviceId, u32 BaseAddress)
{
int Status = XST_FAILURE;
XUsbPsu_Config *ConfigPtr;
static struct XUsbPsu UsbInst;
ConfigPtr = XUsbPsu_LookupConfig(DeviceId);
if (NULL == ConfigPtr) {
goto done;
}
Status = XUsbPsu_CfgInitialize(&UsbInst, ConfigPtr, BaseAddress);
if (XST_SUCCESS != Status) {
goto done;
}
XUsbPsu_Idle(&UsbInst);
done:
return;
}
#endif
#if defined(XPAR_PSV_ETHERNET_0_DEVICE_ID) || defined(XPAR_PSV_ETHERNET_1_DEVICE_ID)
/**
* NodeGemIdle() - Custom code to idle the GEM
*
* @DeviceId: Device ID of GEM node
* @BaseAddress: GEM base address
*/
void NodeGemIdle(u16 DeviceId, u32 BaseAddress)
{
u32 Reg;
u32 Timeout = XPM_MAX_TIMEOUT;
/* Warning Fix */
(void)(DeviceId);
/* Make sure MDIO is in IDLE state */
do {
Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWSR_OFFSET);
Timeout--;
} while ((0U == (Reg & XEMACPS_NWSR_MDIOIDLE_MASK)) && (Timeout > 0U));
if (0U == Timeout) {
PmWarn("gem not idle\r\n");
}
/* Stop all transactions of the Ethernet and disable all interrupts */
XEmacPs_WriteReg(BaseAddress, XEMACPS_IDR_OFFSET, XEMACPS_IXR_ALL_MASK);
/* Disable the receiver & transmitter */
Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWCTRL_OFFSET);
Reg &= ~((u32)XEMACPS_NWCTRL_RXEN_MASK);
Reg &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK);
XEmacPs_WriteReg(BaseAddress, XEMACPS_NWCTRL_OFFSET, Reg);
}
#endif
#if defined(XPAR_PSV_GDMA_0_DEVICE_ID) || defined(XPAR_PSV_ADMA_0_DEVICE_ID)
#define XZDMA_CH_OFFSET (0x10000U) /* Channel offset per DMA */
#define XZDMA_NUM_CHANNEL (8U) /* Number of Channels */
/**
* NodeZdmaIdle() - Custom code to idle the ZDMA (GDMA and ADMA)
*
* @DeviceId: Device ID of ZDMA node
* @BaseAddress: ZDMA base address of the first channel
*/
void NodeZdmaIdle(u16 DeviceId, u32 BaseAddress)
{
u8 Channel = 0U;
u32 RegVal = 0U, LocalTimeout;
/* Warning Fix */
(void)(DeviceId);
/* Idle each of the 8 Channels */
for (Channel = 0; Channel < XZDMA_NUM_CHANNEL; Channel++) {
/* Disable/stop the Channel */
XZDma_WriteReg(BaseAddress, (XZDMA_CH_CTRL2_OFFSET),
(XZDMA_CH_CTRL2_DIS_MASK));
/* Wait till transfers are not completed or halted */
/* TODO: not right to use max timeout. do calibrate*/
LocalTimeout = XPM_MAX_TIMEOUT;
do {
RegVal = XZDma_ReadReg(BaseAddress, XZDMA_CH_STS_OFFSET) & XZDMA_STS_BUSY_MASK;
LocalTimeout--;
} while ((0U != RegVal) && (LocalTimeout > 0U));
/* Disable and clear all interrupts */
XZDma_WriteReg(BaseAddress, XZDMA_CH_IDS_OFFSET, XZDMA_IXR_ALL_INTR_MASK);
RegVal = XZDma_ReadReg(BaseAddress, XZDMA_CH_ISR_OFFSET);
XZDma_WriteReg(BaseAddress, XZDMA_CH_ISR_OFFSET,
(RegVal & XZDMA_IXR_ALL_INTR_MASK));
/* Reset all the configurations */
XZDma_WriteReg(BaseAddress, XZDMA_CH_CTRL0_OFFSET, XZDMA_CTRL0_RESET_VALUE);
XZDma_WriteReg(BaseAddress, XZDMA_CH_CTRL1_OFFSET, XZDMA_CTRL1_RESET_VALUE);
XZDma_WriteReg(BaseAddress, XZDMA_CH_DATA_ATTR_OFFSET, XZDMA_DATA_ATTR_RESET_VALUE);
XZDma_WriteReg(BaseAddress, XZDMA_CH_DSCR_ATTR_OFFSET, XZDMA_DSCR_ATTR_RESET_VALUE);
/* Clears total byte transferred */
RegVal = XZDma_ReadReg(BaseAddress, XZDMA_CH_TOTAL_BYTE_OFFSET);
XZDma_WriteReg(BaseAddress, XZDMA_CH_TOTAL_BYTE_OFFSET, RegVal);
/* Read interrupt counts to clear it on both source and destination Channels*/
(void)XZDma_ReadReg(BaseAddress, XZDMA_CH_IRQ_SRC_ACCT_OFFSET);
(void)XZDma_ReadReg(BaseAddress, XZDMA_CH_IRQ_DST_ACCT_OFFSET);
/* Reset the channel's coherent attributes. */
XZDma_WriteReg(BaseAddress, XZDMA_CH_DSCR_ATTR_OFFSET, 0x0);
XZDma_WriteReg(BaseAddress, XZDMA_CH_SRC_DSCR_WORD3_OFFSET, 0x0);
XZDma_WriteReg(BaseAddress, XZDMA_CH_DST_DSCR_WORD3_OFFSET, 0x0);
BaseAddress += XZDMA_CH_OFFSET;
}
}
#endif
void XPmDevice_SoftResetIdle(XPm_Device *Device, const u32 IdleReq)
{
u32 Idx;
u32 DevRstDataSize = ARRAY_SIZE(DeviceRstData);
XPmDevice_SoftResetInfo *RstInfo = NULL;
if (0U != DevRstDataSize) {
for (Idx = 0; Idx < DevRstDataSize; Idx++) {
if (Device->Node.Id == DeviceRstData[Idx].DeviceId) {
RstInfo = &DeviceRstData[Idx];
break;
}
}
}
if (NULL == RstInfo) {
return;
}
if (DEVICE_IDLE_REQ == IdleReq) {
if (NULL != RstInfo->IdleHook) {
RstInfo->IdleHook(RstInfo->IdleHookArgs,
Device->Node.BaseAddress);
}
if (NULL != RstInfo->SoftRst) {
RstInfo->SoftRst(Device->Node.BaseAddress);
}
}
/* Perform the device reset using its reset lines and its reset actions */
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/crf_apb.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _CRF_APB_H_
#define _CRF_APB_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* CRF_APB Base Address
*/
#define CRF_APB_BASEADDR ((u32)0XFD1A0000U)
/**
* Register: CRF_APB_ERR_CTRL
*/
#define CRF_APB_ERR_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000000U) )
#define CRF_APB_ERR_CTRL_SLVERR_ENABLE_SHIFT 0
#define CRF_APB_ERR_CTRL_SLVERR_ENABLE_WIDTH 1
#define CRF_APB_ERR_CTRL_SLVERR_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_IR_STATUS
*/
#define CRF_APB_IR_STATUS ( ( CRF_APB_BASEADDR ) + ((u32)0X00000004U) )
#define CRF_APB_IR_STATUS_ADDR_DECODE_ERR_SHIFT 0
#define CRF_APB_IR_STATUS_ADDR_DECODE_ERR_WIDTH 1
#define CRF_APB_IR_STATUS_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_IR_MASK
*/
#define CRF_APB_IR_MASK ( ( CRF_APB_BASEADDR ) + ((u32)0X00000008U) )
#define CRF_APB_IR_MASK_ADDR_DECODE_ERR_SHIFT 0
#define CRF_APB_IR_MASK_ADDR_DECODE_ERR_WIDTH 1
#define CRF_APB_IR_MASK_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_IR_ENABLE
*/
#define CRF_APB_IR_ENABLE ( ( CRF_APB_BASEADDR ) + ((u32)0X0000000CU) )
#define CRF_APB_IR_ENABLE_ADDR_DECODE_ERR_SHIFT 0
#define CRF_APB_IR_ENABLE_ADDR_DECODE_ERR_WIDTH 1
#define CRF_APB_IR_ENABLE_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_IR_DISABLE
*/
#define CRF_APB_IR_DISABLE ( ( CRF_APB_BASEADDR ) + ((u32)0X00000010U) )
#define CRF_APB_IR_DISABLE_ADDR_DECODE_ERR_SHIFT 0
#define CRF_APB_IR_DISABLE_ADDR_DECODE_ERR_WIDTH 1
#define CRF_APB_IR_DISABLE_ADDR_DECODE_ERR_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_CRF_ECO
*/
#define CRF_APB_CRF_ECO ( ( CRF_APB_BASEADDR ) + ((u32)0X00000018U) )
#define CRF_APB_CRF_ECO_REG_SHIFT 0
#define CRF_APB_CRF_ECO_REG_WIDTH 32
#define CRF_APB_CRF_ECO_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: CRF_APB_CRF_WPROT
*/
#define CRF_APB_CRF_WPROT ( ( CRF_APB_BASEADDR ) + ((u32)0X0000001CU) )
#define CRF_APB_CRF_WPROT_ACTIVE_SHIFT 0
#define CRF_APB_CRF_WPROT_ACTIVE_WIDTH 1
#define CRF_APB_CRF_WPROT_ACTIVE_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_APLL_CTRL
*/
#define CRF_APB_APLL_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000020U) )
#define CRF_APB_APLL_CTRL_POST_SRC_SHIFT 24
#define CRF_APB_APLL_CTRL_POST_SRC_WIDTH 3
#define CRF_APB_APLL_CTRL_POST_SRC_MASK ((u32)0X07000000U)
#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20
#define CRF_APB_APLL_CTRL_PRE_SRC_WIDTH 3
#define CRF_APB_APLL_CTRL_PRE_SRC_MASK ((u32)0X00700000U)
#define CRF_APB_APLL_CTRL_CLKOUTDIV_SHIFT 17
#define CRF_APB_APLL_CTRL_CLKOUTDIV_WIDTH 1
#define CRF_APB_APLL_CTRL_CLKOUTDIV_MASK ((u32)0X00020000U)
#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16
#define CRF_APB_APLL_CTRL_DIV2_WIDTH 1
#define CRF_APB_APLL_CTRL_DIV2_MASK ((u32)0X00010000U)
#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8
#define CRF_APB_APLL_CTRL_FBDIV_WIDTH 7
#define CRF_APB_APLL_CTRL_FBDIV_MASK ((u32)0X00007F00U)
#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3
#define CRF_APB_APLL_CTRL_BYPASS_WIDTH 1
#define CRF_APB_APLL_CTRL_BYPASS_MASK ((u32)0X00000008U)
#define CRF_APB_APLL_CTRL_RESET_SHIFT 0
#define CRF_APB_APLL_CTRL_RESET_WIDTH 1
#define CRF_APB_APLL_CTRL_RESET_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_APLL_CFG
*/
#define CRF_APB_APLL_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X00000024U) )
#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25
#define CRF_APB_APLL_CFG_LOCK_DLY_WIDTH 7
#define CRF_APB_APLL_CFG_LOCK_DLY_MASK ((u32)0XFE000000U)
#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13
#define CRF_APB_APLL_CFG_LOCK_CNT_WIDTH 10
#define CRF_APB_APLL_CFG_LOCK_CNT_MASK ((u32)0X007FE000U)
#define CRF_APB_APLL_CFG_LFHF_SHIFT 10
#define CRF_APB_APLL_CFG_LFHF_WIDTH 2
#define CRF_APB_APLL_CFG_LFHF_MASK ((u32)0X00000C00U)
#define CRF_APB_APLL_CFG_CP_SHIFT 5
#define CRF_APB_APLL_CFG_CP_WIDTH 4
#define CRF_APB_APLL_CFG_CP_MASK ((u32)0X000001E0U)
#define CRF_APB_APLL_CFG_RES_SHIFT 0
#define CRF_APB_APLL_CFG_RES_WIDTH 4
#define CRF_APB_APLL_CFG_RES_MASK ((u32)0X0000000FU)
/**
* Register: CRF_APB_APLL_FRAC_CFG
*/
#define CRF_APB_APLL_FRAC_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X00000028U) )
#define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 31
#define CRF_APB_APLL_FRAC_CFG_ENABLED_WIDTH 1
#define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK ((u32)0X80000000U)
#define CRF_APB_APLL_FRAC_CFG_SEED_SHIFT 22
#define CRF_APB_APLL_FRAC_CFG_SEED_WIDTH 3
#define CRF_APB_APLL_FRAC_CFG_SEED_MASK ((u32)0X01C00000U)
#define CRF_APB_APLL_FRAC_CFG_ALGRTHM_SHIFT 19
#define CRF_APB_APLL_FRAC_CFG_ALGRTHM_WIDTH 1
#define CRF_APB_APLL_FRAC_CFG_ALGRTHM_MASK ((u32)0X00080000U)
#define CRF_APB_APLL_FRAC_CFG_ORDER_SHIFT 18
#define CRF_APB_APLL_FRAC_CFG_ORDER_WIDTH 1
#define CRF_APB_APLL_FRAC_CFG_ORDER_MASK ((u32)0X00040000U)
#define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 0
#define CRF_APB_APLL_FRAC_CFG_DATA_WIDTH 16
#define CRF_APB_APLL_FRAC_CFG_DATA_MASK ((u32)0X0000FFFFU)
/**
* Register: CRF_APB_DPLL_CTRL
*/
#define CRF_APB_DPLL_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X0000002CU) )
#define CRF_APB_DPLL_CTRL_POST_SRC_SHIFT 24
#define CRF_APB_DPLL_CTRL_POST_SRC_WIDTH 3
#define CRF_APB_DPLL_CTRL_POST_SRC_MASK ((u32)0X07000000U)
#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20
#define CRF_APB_DPLL_CTRL_PRE_SRC_WIDTH 3
#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK ((u32)0X00700000U)
#define CRF_APB_DPLL_CTRL_CLKOUTDIV_SHIFT 17
#define CRF_APB_DPLL_CTRL_CLKOUTDIV_WIDTH 1
#define CRF_APB_DPLL_CTRL_CLKOUTDIV_MASK ((u32)0X00020000U)
#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16
#define CRF_APB_DPLL_CTRL_DIV2_WIDTH 1
#define CRF_APB_DPLL_CTRL_DIV2_MASK ((u32)0X00010000U)
#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8
#define CRF_APB_DPLL_CTRL_FBDIV_WIDTH 7
#define CRF_APB_DPLL_CTRL_FBDIV_MASK ((u32)0X00007F00U)
#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
#define CRF_APB_DPLL_CTRL_BYPASS_WIDTH 1
#define CRF_APB_DPLL_CTRL_BYPASS_MASK ((u32)0X00000008U)
#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
#define CRF_APB_DPLL_CTRL_RESET_WIDTH 1
#define CRF_APB_DPLL_CTRL_RESET_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_DPLL_CFG
*/
#define CRF_APB_DPLL_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X00000030U) )
#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25
#define CRF_APB_DPLL_CFG_LOCK_DLY_WIDTH 7
#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK ((u32)0XFE000000U)
#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13
#define CRF_APB_DPLL_CFG_LOCK_CNT_WIDTH 10
#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK ((u32)0X007FE000U)
#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10
#define CRF_APB_DPLL_CFG_LFHF_WIDTH 2
#define CRF_APB_DPLL_CFG_LFHF_MASK ((u32)0X00000C00U)
#define CRF_APB_DPLL_CFG_CP_SHIFT 5
#define CRF_APB_DPLL_CFG_CP_WIDTH 4
#define CRF_APB_DPLL_CFG_CP_MASK ((u32)0X000001E0U)
#define CRF_APB_DPLL_CFG_RES_SHIFT 0
#define CRF_APB_DPLL_CFG_RES_WIDTH 4
#define CRF_APB_DPLL_CFG_RES_MASK ((u32)0X0000000FU)
/**
* Register: CRF_APB_DPLL_FRAC_CFG
*/
#define CRF_APB_DPLL_FRAC_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X00000034U) )
#define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 31
#define CRF_APB_DPLL_FRAC_CFG_ENABLED_WIDTH 1
#define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK ((u32)0X80000000U)
#define CRF_APB_DPLL_FRAC_CFG_SEED_SHIFT 22
#define CRF_APB_DPLL_FRAC_CFG_SEED_WIDTH 3
#define CRF_APB_DPLL_FRAC_CFG_SEED_MASK ((u32)0X01C00000U)
#define CRF_APB_DPLL_FRAC_CFG_ALGRTHM_SHIFT 19
#define CRF_APB_DPLL_FRAC_CFG_ALGRTHM_WIDTH 1
#define CRF_APB_DPLL_FRAC_CFG_ALGRTHM_MASK ((u32)0X00080000U)
#define CRF_APB_DPLL_FRAC_CFG_ORDER_SHIFT 18
#define CRF_APB_DPLL_FRAC_CFG_ORDER_WIDTH 1
#define CRF_APB_DPLL_FRAC_CFG_ORDER_MASK ((u32)0X00040000U)
#define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 0
#define CRF_APB_DPLL_FRAC_CFG_DATA_WIDTH 16
#define CRF_APB_DPLL_FRAC_CFG_DATA_MASK ((u32)0X0000FFFFU)
/**
* Register: CRF_APB_VPLL_CTRL
*/
#define CRF_APB_VPLL_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000038U) )
#define CRF_APB_VPLL_CTRL_POST_SRC_SHIFT 24
#define CRF_APB_VPLL_CTRL_POST_SRC_WIDTH 3
#define CRF_APB_VPLL_CTRL_POST_SRC_MASK ((u32)0X07000000U)
#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20
#define CRF_APB_VPLL_CTRL_PRE_SRC_WIDTH 3
#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK ((u32)0X00700000U)
#define CRF_APB_VPLL_CTRL_CLKOUTDIV_SHIFT 17
#define CRF_APB_VPLL_CTRL_CLKOUTDIV_WIDTH 1
#define CRF_APB_VPLL_CTRL_CLKOUTDIV_MASK ((u32)0X00020000U)
#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16
#define CRF_APB_VPLL_CTRL_DIV2_WIDTH 1
#define CRF_APB_VPLL_CTRL_DIV2_MASK ((u32)0X00010000U)
#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8
#define CRF_APB_VPLL_CTRL_FBDIV_WIDTH 7
#define CRF_APB_VPLL_CTRL_FBDIV_MASK ((u32)0X00007F00U)
#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3
#define CRF_APB_VPLL_CTRL_BYPASS_WIDTH 1
#define CRF_APB_VPLL_CTRL_BYPASS_MASK ((u32)0X00000008U)
#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0
#define CRF_APB_VPLL_CTRL_RESET_WIDTH 1
#define CRF_APB_VPLL_CTRL_RESET_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_VPLL_CFG
*/
#define CRF_APB_VPLL_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X0000003CU) )
#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25
#define CRF_APB_VPLL_CFG_LOCK_DLY_WIDTH 7
#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK ((u32)0XFE000000U)
#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13
#define CRF_APB_VPLL_CFG_LOCK_CNT_WIDTH 10
#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK ((u32)0X007FE000U)
#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10
#define CRF_APB_VPLL_CFG_LFHF_WIDTH 2
#define CRF_APB_VPLL_CFG_LFHF_MASK ((u32)0X00000C00U)
#define CRF_APB_VPLL_CFG_CP_SHIFT 5
#define CRF_APB_VPLL_CFG_CP_WIDTH 4
#define CRF_APB_VPLL_CFG_CP_MASK ((u32)0X000001E0U)
#define CRF_APB_VPLL_CFG_RES_SHIFT 0
#define CRF_APB_VPLL_CFG_RES_WIDTH 4
#define CRF_APB_VPLL_CFG_RES_MASK ((u32)0X0000000FU)
/**
* Register: CRF_APB_VPLL_FRAC_CFG
*/
#define CRF_APB_VPLL_FRAC_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X00000040U) )
#define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 31
#define CRF_APB_VPLL_FRAC_CFG_ENABLED_WIDTH 1
#define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK ((u32)0X80000000U)
#define CRF_APB_VPLL_FRAC_CFG_SEED_SHIFT 22
#define CRF_APB_VPLL_FRAC_CFG_SEED_WIDTH 3
#define CRF_APB_VPLL_FRAC_CFG_SEED_MASK ((u32)0X01C00000U)
#define CRF_APB_VPLL_FRAC_CFG_ALGRTHM_SHIFT 19
#define CRF_APB_VPLL_FRAC_CFG_ALGRTHM_WIDTH 1
#define CRF_APB_VPLL_FRAC_CFG_ALGRTHM_MASK ((u32)0X00080000U)
#define CRF_APB_VPLL_FRAC_CFG_ORDER_SHIFT 18
#define CRF_APB_VPLL_FRAC_CFG_ORDER_WIDTH 1
#define CRF_APB_VPLL_FRAC_CFG_ORDER_MASK ((u32)0X00040000U)
#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 0
#define CRF_APB_VPLL_FRAC_CFG_DATA_WIDTH 16
#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK ((u32)0X0000FFFFU)
/**
* Register: CRF_APB_PLL_STATUS
*/
#define CRF_APB_PLL_STATUS ( ( CRF_APB_BASEADDR ) + ((u32)0X00000044U) )
#define CRF_APB_PLL_STATUS_VPLL_STABLE_SHIFT 5
#define CRF_APB_PLL_STATUS_VPLL_STABLE_WIDTH 1
#define CRF_APB_PLL_STATUS_VPLL_STABLE_MASK ((u32)0X00000020U)
#define CRF_APB_PLL_STATUS_DPLL_STABLE_SHIFT 4
#define CRF_APB_PLL_STATUS_DPLL_STABLE_WIDTH 1
#define CRF_APB_PLL_STATUS_DPLL_STABLE_MASK ((u32)0X00000010U)
#define CRF_APB_PLL_STATUS_APLL_STABLE_SHIFT 3
#define CRF_APB_PLL_STATUS_APLL_STABLE_WIDTH 1
#define CRF_APB_PLL_STATUS_APLL_STABLE_MASK ((u32)0X00000008U)
#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2
#define CRF_APB_PLL_STATUS_VPLL_LOCK_WIDTH 1
#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK ((u32)0X00000004U)
#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1
#define CRF_APB_PLL_STATUS_DPLL_LOCK_WIDTH 1
#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK ((u32)0X00000002U)
#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0
#define CRF_APB_PLL_STATUS_APLL_LOCK_WIDTH 1
#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_APLL_TO_LPD_CTRL
*/
#define CRF_APB_APLL_TO_LPD_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000048U) )
#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
/**
* Register: CRF_APB_DPLL_TO_LPD_CTRL
*/
#define CRF_APB_DPLL_TO_LPD_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X0000004CU) )
#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
/**
* Register: CRF_APB_VPLL_TO_LPD_CTRL
*/
#define CRF_APB_VPLL_TO_LPD_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000050U) )
#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
/**
* Register: CRF_APB_ACPU_CTRL
*/
#define CRF_APB_ACPU_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000060U) )
#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25
#define CRF_APB_ACPU_CTRL_CLKACT_HALF_WIDTH 1
#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK ((u32)0X02000000U)
#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24
#define CRF_APB_ACPU_CTRL_CLKACT_FULL_WIDTH 1
#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK ((u32)0X01000000U)
#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_ACPU_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_ACPU_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_ACPU_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DBG_TRACE_CTRL
*/
#define CRF_APB_DBG_TRACE_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000064U) )
#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DBG_TRACE_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DBG_FPD_CTRL
*/
#define CRF_APB_DBG_FPD_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000068U) )
#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DBG_FPD_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DBG_FPD_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DP_VIDEO_REF_CTRL
*/
#define CRF_APB_DP_VIDEO_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000070U) )
#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_WIDTH 6
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DP_AUDIO_REF_CTRL
*/
#define CRF_APB_DP_AUDIO_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000074U) )
#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_WIDTH 6
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DP_STC_REF_CTRL
*/
#define CRF_APB_DP_STC_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X0000007CU) )
#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DP_STC_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_WIDTH 6
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U)
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DDR_CTRL
*/
#define CRF_APB_DDR_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000080U) )
#define CRF_APB_DDR_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DDR_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DDR_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DDR_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DDR_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DDR_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DDR_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_GPU_REF_CTRL
*/
#define CRF_APB_GPU_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000084U) )
#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26
#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_WIDTH 1
#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK ((u32)0X04000000U)
#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25
#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_WIDTH 1
#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK ((u32)0X02000000U)
#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_GPU_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_GPU_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_GPU_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_SATA_REF_CTRL
*/
#define CRF_APB_SATA_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000A0U) )
#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_SATA_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_SATA_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_PCIE_REF_CTRL
*/
#define CRF_APB_PCIE_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000B4U) )
#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_PCIE_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_PCIE_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_GDMA_REF_CTRL
*/
#define CRF_APB_GDMA_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000B8U) )
#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_GDMA_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_GDMA_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DPDMA_REF_CTRL
*/
#define CRF_APB_DPDMA_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000BCU) )
#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DPDMA_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_TOPSW_MAIN_CTRL
*/
#define CRF_APB_TOPSW_MAIN_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000C0U) )
#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24
#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_WIDTH 1
#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_TOPSW_LSBUS_CTRL
*/
#define CRF_APB_TOPSW_LSBUS_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000C4U) )
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_WIDTH 1
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_GTGREF0_REF_CTRL
*/
#define CRF_APB_GTGREF0_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000C8U) )
#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DFT300_REF_CTRL
*/
#define CRF_APB_DFT300_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000D0U) )
#define CRF_APB_DFT300_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DFT300_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DFT300_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DFT300_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DFT300_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DFT300_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DFT300_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DFT300_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DFT300_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DFT270_REF_CTRL
*/
#define CRF_APB_DFT270_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000D4U) )
#define CRF_APB_DFT270_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DFT270_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DFT270_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DFT270_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DFT270_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DFT270_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DFT270_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DFT270_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DFT270_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DFT250_REF_CTRL
*/
#define CRF_APB_DFT250_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000D8U) )
#define CRF_APB_DFT250_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DFT250_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DFT250_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DFT250_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DFT250_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DFT250_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DFT250_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DFT250_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DFT250_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DFT125_REF_CTRL
*/
#define CRF_APB_DFT125_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000DCU) )
#define CRF_APB_DFT125_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DFT125_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DFT125_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DFT125_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DFT125_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DFT125_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DFT125_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DFT125_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DFT125_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DFT150_REF_CTRL
*/
#define CRF_APB_DFT150_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000F0U) )
#define CRF_APB_DFT150_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DFT150_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DFT150_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DFT150_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DFT150_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DFT150_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DFT150_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DFT150_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DFT150_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DFT333_REF_CTRL
*/
#define CRF_APB_DFT333_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000F4U) )
#define CRF_APB_DFT333_REF_CTRL_CLKACT_SHIFT 24
#define CRF_APB_DFT333_REF_CTRL_CLKACT_WIDTH 1
#define CRF_APB_DFT333_REF_CTRL_CLKACT_MASK ((u32)0X01000000U)
#define CRF_APB_DFT333_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DFT333_REF_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DFT333_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DFT333_REF_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DFT333_REF_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DFT333_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_DBG_TSTMP_CTRL
*/
#define CRF_APB_DBG_TSTMP_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000F8U) )
#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_WIDTH 6
#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK ((u32)0X00003F00U)
#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0
#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_WIDTH 3
#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK ((u32)0X00000007U)
/**
* Register: CRF_APB_RST_FPD_TOP
*/
#define CRF_APB_RST_FPD_TOP ( ( CRF_APB_BASEADDR ) + ((u32)0X00000100U) )
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK ((u32)0X00080000U)
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK ((u32)0X00040000U)
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK ((u32)0X00020000U)
#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16
#define CRF_APB_RST_FPD_TOP_DP_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK ((u32)0X00010000U)
#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15
#define CRF_APB_RST_FPD_TOP_SWDT_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK ((u32)0X00008000U)
#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 12
#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK ((u32)0X00001000U)
#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 11
#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK ((u32)0X00000800U)
#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 10
#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK ((u32)0X00000400U)
#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 9
#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK ((u32)0X00000200U)
#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 8
#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK ((u32)0X00000100U)
#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 7
#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK ((u32)0X00000080U)
#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6
#define CRF_APB_RST_FPD_TOP_GDMA_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK ((u32)0X00000040U)
#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5
#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK ((u32)0X00000020U)
#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4
#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK ((u32)0X00000010U)
#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3
#define CRF_APB_RST_FPD_TOP_GPU_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK ((u32)0X00000008U)
#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2
#define CRF_APB_RST_FPD_TOP_GT_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK ((u32)0X00000004U)
#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1
#define CRF_APB_RST_FPD_TOP_SATA_RESET_WIDTH 1
#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK ((u32)0X00000002U)
/**
* Register: CRF_APB_RST_FPD_APU
*/
#define CRF_APB_RST_FPD_APU ( ( CRF_APB_BASEADDR ) + ((u32)0X00000104U) )
#define CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_SHIFT 13
#define CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_WIDTH 1
#define CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_MASK ((u32)0X00002000U)
#define CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_SHIFT 12
#define CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_WIDTH 1
#define CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_MASK ((u32)0X00001000U)
#define CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_SHIFT 11
#define CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_WIDTH 1
#define CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_MASK ((u32)0X00000800U)
#define CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_SHIFT 10
#define CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_WIDTH 1
#define CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_MASK ((u32)0X00000400U)
#define CRF_APB_RST_FPD_APU_APU_L2_RESET_SHIFT 8
#define CRF_APB_RST_FPD_APU_APU_L2_RESET_WIDTH 1
#define CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK ((u32)0X00000100U)
#define CRF_APB_RST_FPD_APU_ACPU3_RESET_SHIFT 3
#define CRF_APB_RST_FPD_APU_ACPU3_RESET_WIDTH 1
#define CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK ((u32)0X00000008U)
#define CRF_APB_RST_FPD_APU_ACPU2_RESET_SHIFT 2
#define CRF_APB_RST_FPD_APU_ACPU2_RESET_WIDTH 1
#define CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK ((u32)0X00000004U)
#define CRF_APB_RST_FPD_APU_ACPU1_RESET_SHIFT 1
#define CRF_APB_RST_FPD_APU_ACPU1_RESET_WIDTH 1
#define CRF_APB_RST_FPD_APU_ACPU1_RESET_MASK ((u32)0X00000002U)
#define CRF_APB_RST_FPD_APU_ACPU0_RESET_SHIFT 0
#define CRF_APB_RST_FPD_APU_ACPU0_RESET_WIDTH 1
#define CRF_APB_RST_FPD_APU_ACPU0_RESET_MASK ((u32)0X00000001U)
/**
* Register: CRF_APB_RST_DDR_SS
*/
#define CRF_APB_RST_DDR_SS ( ( CRF_APB_BASEADDR ) + ((u32)0X00000108U) )
#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3
#define CRF_APB_RST_DDR_SS_DDR_RESET_WIDTH 1
#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK ((u32)0X00000008U)
#define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 2
#define CRF_APB_RST_DDR_SS_APM_RESET_WIDTH 1
#define CRF_APB_RST_DDR_SS_APM_RESET_MASK ((u32)0X00000004U)
#ifdef __cplusplus
}
#endif
#endif /* _CRF_APB_H_ */
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/qspipsu_v1_11/src/xqspipsu_hw.c
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu_hw.c
* @addtogroup qspipsu_v1_11
* @{
*
* This file contains functions to reads RXFifo, writes TXFifo and setup
* RX DMA operation, used by xqspipsu_control.c and xqspipsu_lowlevel.c files.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.11 akm 03/09/20 First release
* mn 03/30/20 Add xil_smc.h include for Xil_Smc calls
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xqspipsu.h"
#if defined (__aarch64__)
#include "xil_smc.h"
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/*****************************************************************************/
/**
*
* Fills the TX FIFO as long as there is room in the FIFO or the bytes required
* to be transmitted.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
* @param Size is the number of bytes to be transmitted.
*
* @return None
*
* @note None.
*
******************************************************************************/
void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 Size)
{
u32 Count = 0;
u32 Data = 0U;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
Xil_AssertVoid(Size != 0);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_FillTxFifo\r\n");
#endif
while ((InstancePtr->TxBytes > 0) && (Count < Size)) {
if (InstancePtr->TxBytes >= 4) {
(void)Xil_MemCpy((u8 *)&Data, Msg->TxBfrPtr, 4);
Msg->TxBfrPtr += 4;
InstancePtr->TxBytes -= 4;
Count += 4;
} else {
(void)Xil_MemCpy((u8 *)&Data, Msg->TxBfrPtr,
(u32)InstancePtr->TxBytes);
Msg->TxBfrPtr += InstancePtr->TxBytes;
Count += InstancePtr->TxBytes;
InstancePtr->TxBytes = 0;
}
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_TXD_OFFSET, Data);
#ifdef DEBUG
xil_printf("\nData is %08x\r\n", Data);
#endif
}
if (InstancePtr->TxBytes < 0)
InstancePtr->TxBytes = 0;
}
/*****************************************************************************/
/**
*
* This function checks the TX buffer in the message and setup the
* TX FIFO as required.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
*
* @return None
*
* @note None.
*
******************************************************************************/
void XQspiPsu_TXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_TXSetup\r\n");
#endif
InstancePtr->TxBytes = (s32)Msg->ByteCount;
InstancePtr->SendBufferPtr = Msg->TxBfrPtr;
XQspiPsu_FillTxFifo(InstancePtr, Msg, (u32)XQSPIPSU_TXD_DEPTH);
}
/*****************************************************************************/
/**
*
* This function sets up the RX DMA operation.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
*
* @return None
*
* @note None.
*
******************************************************************************/
void XQspiPsu_SetupRxDma(const XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg)
{
s32 Remainder;
s32 DmaRxBytes;
UINTPTR AddrTemp;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_SetupRxDma\r\n");
#endif
AddrTemp = ((UINTPTR)(Msg->RxBfrPtr) & XQSPIPSU_QSPIDMA_DST_ADDR_MASK);
/* Check for RXBfrPtr to be word aligned */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, (u32)AddrTemp);
#if defined(__aarch64__) || defined(__arch64__)
AddrTemp = ((UINTPTR)(Msg->RxBfrPtr) >> 32U);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, (u32)AddrTemp &
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
#else
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, 0U);
#endif
Remainder = InstancePtr->RxBytes % 4;
DmaRxBytes = InstancePtr->RxBytes;
if (Remainder != 0) {
/* This is done to make Dma bytes aligned */
DmaRxBytes = InstancePtr->RxBytes - Remainder;
Msg->ByteCount = (u32)DmaRxBytes;
}
if (InstancePtr->Config.IsCacheCoherent == 0U)
Xil_DCacheInvalidateRange((INTPTR)Msg->RxBfrPtr, Msg->ByteCount);
/* Write no. of words to DMA DST SIZE */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, (u32)DmaRxBytes);
}
/*****************************************************************************/
/**
*
* This function sets up the RX DMA operation on a 32bit Machine
* For 64bit Dma transfers..
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
*
* @return None
*
* @note None.
*
******************************************************************************/
void XQspiPsu_Setup64BRxDma(const XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg)
{
s32 Remainder;
s32 DmaRxBytes;
u64 AddrTemp;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_Setup64BRxDma\r\n");
#endif
AddrTemp = Msg->RxAddr64bit & XQSPIPSU_QSPIDMA_DST_ADDR_MASK;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, (u32)AddrTemp);
AddrTemp = (Msg->RxAddr64bit >> 32);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, (u32)AddrTemp &
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
Remainder = InstancePtr->RxBytes % 4;
DmaRxBytes = InstancePtr->RxBytes;
if (Remainder != 0) {
/* This is done to make Dma bytes aligned */
DmaRxBytes = InstancePtr->RxBytes - Remainder;
Msg->ByteCount = (u32)DmaRxBytes;
}
/* Write no. of words to DMA DST SIZE */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, (u32)DmaRxBytes);
}
/*****************************************************************************/
/**
*
* This function reads remaining bytes, after the completion of a DMA transfer,
* using IO mode
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if transfer fails.
* - XST_DEVICE_BUSY if a transfer is already in progress.
*
* @note None.
*
******************************************************************************/
u32 XQspiPsu_SetIOMode(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Msg != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_DMARXComplete\r\n");
#endif
/* Read remaining bytes using IO mode */
if ((InstancePtr->RxBytes % 4) != 0) {
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
(XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) &
~XQSPIPSU_CFG_MODE_EN_MASK));
InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
Msg->ByteCount = (InstancePtr->RxBytes % 4);
Msg->RxBfrPtr += (InstancePtr->RxBytes - (InstancePtr->RxBytes % 4));
InstancePtr->IsUnaligned = 1;
return (u32) TRUE;
}
return (u32) FALSE;
}
/*****************************************************************************/
/**
*
* This function checks the RX buffers in the message and setup the
* RX DMA as required.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
*
* @return None
*
* @note None.
*
******************************************************************************/
void XQspiPsu_RXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_RXSetup\r\n");
#endif
InstancePtr->RxBytes = (s32)Msg->ByteCount;
if (((Msg->RxAddr64bit >= XQSPIPSU_RXADDR_OVER_32BIT) ||
(Msg->Xfer64bit != (u8)0U)) &&
(InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA))
XQspiPsu_Setup64BRxDma(InstancePtr, Msg);
else if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA)
XQspiPsu_SetupRxDma(InstancePtr, Msg);
}
/*****************************************************************************/
/**
*
* This function checks the TX/RX buffers in the message and setups up the
* GENFIFO entries, TX FIFO or RX DMA as required.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
* @param GenFifoEntry is pointer to the variable in which GENFIFO mask
* is returned to calling function
*
* @return None
*
* @note None.
*
******************************************************************************/
void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 *GenFifoEntry)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
Xil_AssertVoid(GenFifoEntry != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_TXRXSetup\r\n");
#endif
/* Transmit */
if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) == FALSE)) {
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
*GenFifoEntry |= XQSPIPSU_GENFIFO_TX;
/* Discard RX data */
*GenFifoEntry &= ~XQSPIPSU_GENFIFO_RX;
/* Setup data to be TXed */
XQspiPsu_TXSetup(InstancePtr, Msg);
InstancePtr->RecvBufferPtr = NULL;
InstancePtr->RxBytes = 0;
}
/*Receive*/
if (((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE) &&
((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) == FALSE)) {
/* TX auto fill */
*GenFifoEntry &= ~XQSPIPSU_GENFIFO_TX;
/* Setup RX */
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
*GenFifoEntry |= XQSPIPSU_GENFIFO_RX;
/* Setup DMA for data to be RXed */
XQspiPsu_RXSetup(InstancePtr, Msg);
InstancePtr->SendBufferPtr = NULL;
InstancePtr->TxBytes = 0;
}
/* If only dummy is requested as a separate entry */
if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) == FALSE) &&
((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) == FALSE)) {
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
*GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
InstancePtr->TxBytes = 0;
InstancePtr->RxBytes = 0;
InstancePtr->SendBufferPtr = NULL;
InstancePtr->RecvBufferPtr = NULL;
}
/* Dummy and cmd sent by upper layer to received data */
if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
*GenFifoEntry |= (XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
/* Setup data to be TXed */
XQspiPsu_TXSetup(InstancePtr, Msg);
/* Setup DMA for data to be RXed */
XQspiPsu_RXSetup(InstancePtr, Msg);
}
}
/*****************************************************************************/
/**
*
* This function writes the Data length to GENFIFO entries that need to be
* transmitted or received.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
* @param Index of the current message to be handled.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if transfer fails.
* - XST_DEVICE_BUSY if a transfer is already in progress.
*
* @note None.
*
******************************************************************************/
void XQspiPsu_GenFifoEntryDataLen(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 *GenFifoEntry)
{
u32 TempCount;
u32 ImmData;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
Xil_AssertVoid(GenFifoEntry != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_GenFifoEntryDataLen\r\n");
#endif
if (Msg->ByteCount <= XQSPIPSU_GENFIFO_IMM_DATA_MASK) {
*GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
*GenFifoEntry |= Msg->ByteCount;
#ifdef DEBUG
xil_printf("\nFifoEntry=%08x\r\n", GenFifoEntry);
#endif
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
*GenFifoEntry);
} else {
TempCount = Msg->ByteCount;
u32 Exponent = 8; /* 2^8 = 256 */
ImmData = TempCount & 0xFFU;
/* Exponent entries */
*GenFifoEntry |= XQSPIPSU_GENFIFO_EXP;
while (TempCount != 0U) {
if ((TempCount & XQSPIPSU_GENFIFO_EXP_START) != FALSE) {
*GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
*GenFifoEntry |= Exponent;
#ifdef DEBUG
xil_printf("\nFifoEntry=%08x\r\n",
*GenFifoEntry);
#endif
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
*GenFifoEntry);
}
TempCount = TempCount >> 1;
Exponent++;
}
/* Immediate entry */
*GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_EXP);
if ((ImmData & 0xFFU) != FALSE) {
*GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
*GenFifoEntry |= ImmData & 0xFFU;
#ifdef DEBUG
xil_printf("\nFifoEntry=%08x\r\n", GenFifoEntry);
#endif
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
*GenFifoEntry);
}
}
}
/*****************************************************************************/
/**
*
* This function creates Poll config register data to write
*
* @param BusMask is mask to enable/disable upper/lower data bus masks.
*
* @param DataBusMask is Data bus mask value during poll operation.
*
* @param Data is the poll data value to write into config register.
*
* @return None
*
* @note None.
*
******************************************************************************/
u32 XQspiPsu_CreatePollDataConfig(const XQspiPsu *InstancePtr,
const XQspiPsu_Msg *FlashMsg)
{
u32 ConfigData = 0;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(FlashMsg != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_CreatePollDataConfig\r\n");
#endif
if ((InstancePtr->GenFifoBus & XQSPIPSU_GENFIFO_BUS_UPPER) != FALSE)
ConfigData = XQSPIPSU_SELECT_FLASH_BUS_LOWER <<
XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT;
if ((InstancePtr->GenFifoBus & XQSPIPSU_GENFIFO_BUS_LOWER) != FALSE)
ConfigData |= XQSPIPSU_SELECT_FLASH_BUS_LOWER <<
XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT;
ConfigData |= (u32)(((u32)FlashMsg->PollBusMask <<
XQSPIPSU_POLL_CFG_MASK_EN_SHIFT) & XQSPIPSU_POLL_CFG_MASK_EN_MASK);
ConfigData |= (u32)(((u32)FlashMsg->PollData <<
XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT)
& XQSPIPSU_POLL_CFG_DATA_VALUE_MASK);
return ConfigData;
}
/*****************************************************************************/
/**
*
* Selects SPI mode - x1 or x2 or x4.
*
* @param SpiMode - spi or dual or quad.
* @return Mask to set desired SPI mode in GENFIFO entry.
*
* @note None.
*
******************************************************************************/
u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
{
u32 Mask;
Xil_AssertNonvoid(SpiMode > 0);
#ifdef DEBUG
xil_printf("\nXQspiPsu_SelectSpiMode\r\n");
#endif
switch (SpiMode) {
case XQSPIPSU_SELECT_MODE_DUALSPI:
Mask = XQSPIPSU_GENFIFO_MODE_DUALSPI;
break;
case XQSPIPSU_SELECT_MODE_QUADSPI:
Mask = XQSPIPSU_GENFIFO_MODE_QUADSPI;
break;
case XQSPIPSU_SELECT_MODE_SPI:
Mask = XQSPIPSU_GENFIFO_MODE_SPI;
break;
default:
Mask = XQSPIPSU_GENFIFO_MODE_SPI;
break;
}
#ifdef DEBUG
xil_printf("\nSPIMode is %08x\r\n", SpiMode);
#endif
return Mask;
}
/*****************************************************************************/
/**
*
* Enable and initialize DMA Mode, set little endain, disable poll timeout,
* clear prescalar bits and reset thresholds
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XQspiPsu_SetDefaultConfig(XQspiPsu *InstancePtr)
{
u32 ConfigReg;
Xil_AssertVoid(InstancePtr != NULL);
#ifdef DEBUG
xil_printf("\nXQspiPsu_SetDefaultConfig\r\n");
#endif
/* Default value to config register */
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
/* DMA mode */
ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
/* Manual start */
ConfigReg |= XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK;
/* Little endain by default */
ConfigReg &= ~XQSPIPSU_CFG_ENDIAN_MASK;
/* Disable poll timeout */
ConfigReg &= ~XQSPIPSU_CFG_EN_POLL_TO_MASK;
/* Set hold bit */
ConfigReg |= XQSPIPSU_CFG_WP_HOLD_MASK;
/* Clear prescalar by default */
ConfigReg &= (u32)(~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK);
/* CPOL CPHA 00 */
ConfigReg &= (u32)(~XQSPIPSU_CFG_CLK_PHA_MASK);
ConfigReg &= (u32)(~XQSPIPSU_CFG_CLK_POL_MASK);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET, ConfigReg);
/* Set by default to allow for high frequencies */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_LPBK_DLY_ADJ_OFFSET,
XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_LPBK_DLY_ADJ_OFFSET) |
XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK);
/* Reset thresholds */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_TX_THRESHOLD_OFFSET, XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_RX_THRESHOLD_OFFSET, XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_GF_THRESHOLD_OFFSET, XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL);
/* DMA init */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET,
XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL);
}
/*****************************************************************************/
/**
*
* Read the specified number of bytes from RX FIFO
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
* @param Size is the number of bytes to be read.
*
* @return None
*
* @note None.
*
******************************************************************************/
void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, s32 Size)
{
s32 Count = 0;
u32 Data;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
Xil_AssertVoid(Size > 0);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_ReadRxFifo\r\n");
#endif
while ((InstancePtr->RxBytes != 0) && (Count < Size)) {
Data = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_RXD_OFFSET);
#ifdef DEBUG
xil_printf("\nData is %08x\r\n", Data);
#endif
if (InstancePtr->RxBytes >= 4) {
(void)Xil_MemCpy(Msg->RxBfrPtr, (u8 *)&Data, 4);
InstancePtr->RxBytes -= 4;
Msg->RxBfrPtr += 4;
Count += 4;
} else {
/* Read unaligned bytes (< 4 bytes) */
(void)Xil_MemCpy(Msg->RxBfrPtr, (u8 *)&Data,
(u32)InstancePtr->RxBytes);
Msg->RxBfrPtr += InstancePtr->RxBytes;
Count += InstancePtr->RxBytes;
InstancePtr->RxBytes = 0;
}
}
}
/*****************************************************************************/
/**
*
* This function reads data from RXFifo in IO mode.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
* @param StatusReg is the Interrupt status Register value.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XQspiPsu_IORead(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 StatusReg)
{
s32 RxThr;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_IORXComplete\r\n");
#endif
if ((StatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK) != 0U) {
/*
* Check if PIO RX is complete and
* update RxBytes
*/
RxThr = (s32)XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_RX_THRESHOLD_OFFSET);
RxThr = RxThr*4;
XQspiPsu_ReadRxFifo(InstancePtr, Msg, RxThr);
} else if ((StatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != 0U)
XQspiPsu_ReadRxFifo(InstancePtr, Msg, InstancePtr->RxBytes);
}
#if defined (ARMR5) || (__aarch64__)
/*****************************************************************************/
/**
*
* This function sets the Tapdelay values for the QSPIPSU device driver.The device
* must be idle rather than busy transferring data before setting Tapdelay.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param TapdelayBypss contains the IOU_TAPDLY_BYPASS register value.
* @param LPBKDelay contains the GQSPI_LPBK_DLY_ADJ register value.
* @param Datadelay contains the QSPI_DATA_DLY_ADJ register value.
*
* @return
* - XST_SUCCESS if options are successfully set.
* - XST_DEVICE_BUSY if the device is currently transferring data.
* The transfer must complete or be aborted before setting TapDelay.
*
* @note
* This function is not thread-safe.
*
******************************************************************************/
s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr, u32 TapdelayBypass,
u32 LPBKDelay, u32 Datadelay)
{
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Do not allow to modify the Control Register while a transfer is in
* progress. Not thread-safe.
*/
if (InstancePtr->IsBusy == TRUE) {
Status = XST_DEVICE_BUSY;
} else {
#if EL1_NONSECURE && defined (__aarch64__) && !defined (versal)
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
IOU_TAPDLY_BYPASS_OFFSET) | ((u64)(0x4) << 32),
(u64)TapdelayBypass, 0, 0, 0, 0, 0);
#elif defined (versal)
XQspiPsu_WriteReg(XQSPIPS_BASEADDR, IOU_TAPDLY_BYPASS_OFFSET,
TapdelayBypass);
#else
XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR, IOU_TAPDLY_BYPASS_OFFSET,
TapdelayBypass);
#endif
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_LPBK_DLY_ADJ_OFFSET, LPBKDelay);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_DATA_DLY_ADJ_OFFSET, Datadelay);
Status = XST_SUCCESS;
}
return Status;
}
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/versal/xsecure_rsa_core.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_rsa_core.c
*
* This file contains the implementation of the versal specific RSA driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.0 vns 03/18/19 Initial Release.
* 4.1 vns 08/23/19 Updated Status variables with XST_FAILURE and added
* to while loops.
* 4.2 kpt 01/07/20 Resolved CR-1049134 and added Macro's for all the
* Magic Numbers
* 03/24/20 Added XSecure_RsaZeroizeVerify for
* RSA Zeroization Verification and modified Code for
* Zeroization
*
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsecure_ecdsa_rsa_hw.h"
#include "xsecure_rsa.h"
#include "xil_util.h"
#include "xsecure_error.h"
/************************** Constant Definitions ****************************/
/* PKCS padding for SHA-3 in Versal */
static const u8 XSecure_Silicon2_TPadSha3[] = {0x30U, 0x41U, 0x30U, 0x0DU,
0x06U, 0x09U, 0x60U, 0x86U, 0x48U, 0x01U, 0x65U, 0x03U, 0x04U,
0x02U, 0x09U, 0x05U, 0x00U, 0x04U, 0x30U };
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static void XSecure_RsaPutData(XSecure_Rsa *InstancePtr);
static u32 XSecure_RsaZeroize(XSecure_Rsa *InstancePtr);
static u32 XSecure_RsaZeroizeVerify(XSecure_Rsa *InstancePtr);
static void XSecure_RsaWriteMem(XSecure_Rsa *InstancePtr, u32* WrData,
u8 RamOffset);
static void XSecure_RsaMod32Inverse(XSecure_Rsa *InstancePtr);
static void XSecure_RsaGetData(XSecure_Rsa *InstancePtr, u32 *RdData);
static void XSecure_RsaDataLenCfg(XSecure_Rsa *InstancePtr, u32 Cfg0, u32 Cfg1,
u32 Cfg2, u32 Cfg5);
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* @brief
* This function stores the base address of RSA core registers.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
*
* @return XST_SUCCESS on success.
*
******************************************************************************/
u32 XSecure_RsaCfgInitialize(XSecure_Rsa *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
InstancePtr->BaseAddress = XSECURE_ECDSA_RSA_BASEADDR;
Status = (u32)XST_SUCCESS;
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function handles the all RSA operations with provided inputs.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
* @param Input Pointer to the buffer which contains the input
* data to be encrypted/decrypted.
* @param Result Pointer to buffer where resultant encrypted/decrypted
* data to be stored.
* @param RsaOp Flag to inform the operation to be performed
* is either encryption/decryption
* @param KeySize Size of the key in bytes.
*
* @return XST_SUCCESS on success.
*
******************************************************************************/
u32 XSecure_RsaOperation(XSecure_Rsa *InstancePtr, u8 *Input,
u8 *Result, u8 RsaOp, u32 KeySize)
{
u32 Status = (u32)XST_FAILURE;
u32 ErrorCode = (u32)XST_FAILURE;
u32 Events;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Input != NULL);
Xil_AssertNonvoid(Result != NULL);
Xil_AssertNonvoid((RsaOp == XSECURE_RSA_SIGN_ENC) ||
(RsaOp == XSECURE_RSA_SIGN_DEC));
Xil_AssertNonvoid((KeySize == XSECURE_RSA_4096_KEY_SIZE) ||
(KeySize == XSECURE_RSA_3072_KEY_SIZE) ||
(KeySize == XSECURE_RSA_2048_KEY_SIZE));
InstancePtr->EncDec = RsaOp;
InstancePtr->SizeInWords = KeySize/XSECURE_WORD_SIZE;
/* Reset core */
XSecure_ReleaseReset(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_RESET_OFFSET);
/* Setting Key length */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_KEY_LEN_OFFSET,
(InstancePtr->SizeInWords * XSECURE_WORD_IN_BITS) &
XSECURE_ECDSA_RSA_KEY_LEN_MASK);
/* configuring endianness for data */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_CFG_OFFSET,
XSECURE_ECDSA_RSA_RSA_CFG_WR_ENDIANNESS_MASK |
XSECURE_ECDSA_RSA_CFG_RD_ENDIANNESS_MASK);
/* Put Modulus, exponent, Mod extension in RSA RAM */
XSecure_RsaPutData(InstancePtr);
/* Initialize Digest */
XSecure_RsaWriteMem(InstancePtr, (u32 *)Input,
XSECURE_RSA_RAM_DIGEST);
/* Initialize MINV values from Mod. */
XSecure_RsaMod32Inverse(InstancePtr);
/* Configurations */
switch (InstancePtr->SizeInWords) {
/* For 2048 key */
case XSECURE_RSA_2048_SIZE_WORDS:
XSecure_RsaDataLenCfg(InstancePtr,
XSECURE_ECDSA_RSA_CFG0_2048_VALUE,
XSECURE_ECDSA_RSA_CFG1_2048_VALUE,
XSECURE_ECDSA_RSA_CFG2_2048_VALUE,
XSECURE_ECDSA_RSA_CFG5_2048_VALUE);
ErrorCode = XST_SUCCESS;
break;
/* For 3072 key */
case XSECURE_RSA_3072_SIZE_WORDS:
XSecure_RsaDataLenCfg(InstancePtr,
XSECURE_ECDSA_RSA_CFG0_3072_VALUE,
XSECURE_ECDSA_RSA_CFG1_3072_VALUE,
XSECURE_ECDSA_RSA_CFG2_3072_VALUE,
XSECURE_ECDSA_RSA_CFG5_3072_VALUE);
ErrorCode = XST_SUCCESS;
break;
/* For 4096 key */
case XSECURE_RSA_4096_SIZE_WORDS:
XSecure_RsaDataLenCfg(InstancePtr,
XSECURE_ECDSA_RSA_CFG0_4096_VALUE,
XSECURE_ECDSA_RSA_CFG1_4096_VALUE,
XSECURE_ECDSA_RSA_CFG2_4096_VALUE,
XSECURE_ECDSA_RSA_CFG5_4096_VALUE);
ErrorCode = XST_SUCCESS;
break;
default:
ErrorCode = XST_FAILURE;
break;
}
if (ErrorCode == XST_FAILURE) {
goto END;
}
/* Start the RSA operation. */
if (InstancePtr->ModExt != NULL) {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_CTRL_OFFSET,
XSECURE_RSA_CONTROL_EXP_PRE);
}
else {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_CTRL_OFFSET,
XSECURE_RSA_CONTROL_EXP);
}
/* Check and wait for status */
Status = Xil_WaitForEvents((InstancePtr->BaseAddress +
XSECURE_ECDSA_RSA_STATUS_OFFSET),
(XSECURE_RSA_STATUS_DONE |
XSECURE_RSA_STATUS_ERROR),
(XSECURE_RSA_STATUS_DONE |
XSECURE_RSA_STATUS_ERROR),
XSECURE_TIMEOUT_MAX,
&Events);
/* Time out occurred or RSA error observed*/
if (Status != XST_SUCCESS) {
ErrorCode = Status;
goto END;
}
if((Events & XSECURE_RSA_STATUS_ERROR) == XSECURE_RSA_STATUS_ERROR)
{
ErrorCode = XST_FAILURE;
goto END;
}
/* Copy the result */
XSecure_RsaGetData(InstancePtr, (u32 *)Result);
END:
/* Revert configuring endianness for data */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_CFG_OFFSET,
XSECURE_ECDSA_RSA_CFG_REVERT_ENDIANNESS_MASK);
/* Zeroize and Verify RSA memory space */
if (InstancePtr->EncDec == XSECURE_RSA_SIGN_DEC) {
Status = XSecure_RsaZeroize(InstancePtr);
ErrorCode |= Status;
}
/* Reset core */
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_RESET_OFFSET);
return ErrorCode;
}
/*****************************************************************************/
/**
* @brief
* This function writes all the RSA data used for decryption (Modulus, Exponent)
* at the corresponding offsets in RSA RAM.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
*
* @return None.
*
*
******************************************************************************/
static void XSecure_RsaPutData(XSecure_Rsa *InstancePtr)
{
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
/* Initialize Modular exponentiation */
XSecure_RsaWriteMem(InstancePtr, (u32 *)InstancePtr->ModExpo,
XSECURE_RSA_RAM_EXPO);
/* Initialize Modular. */
XSecure_RsaWriteMem(InstancePtr, (u32 *)InstancePtr->Mod,
XSECURE_RSA_RAM_MOD);
if (InstancePtr->ModExt != NULL) {
/* Initialize Modular extension (R*R Mod M) */
XSecure_RsaWriteMem(InstancePtr, (u32 *)InstancePtr->ModExt,
XSECURE_RSA_RAM_RES_Y);
}
}
/*****************************************************************************/
/**
* @brief
* This function reads back the resulting data from RSA RAM.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
* @param RdData Pointer to location where the RSA output data
* will be written
*
* @return None
*
*
******************************************************************************/
static void XSecure_RsaGetData(XSecure_Rsa *InstancePtr, u32 *RdData)
{
u32 Index;
u32 DataOffset;
s32 TmpIndex;
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
TmpIndex = InstancePtr->SizeInWords - 1;
/* Each of this loop will write 192 bits of data */
for (DataOffset = 0U; DataOffset < XSECURE_RSA_MAX_RD_WR_CNT;
DataOffset++) {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_RAM_ADDR_OFFSET,
(XSECURE_RSA_RAM_RES_Y * XSECURE_RSA_MAX_RD_WR_CNT)
+ DataOffset);
for (Index = 0U; Index < XSECURE_RSA_MAX_BUFF; Index++) {
if(TmpIndex < 0) {
goto END;
}
RdData[TmpIndex] =
XSecure_ReadReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_RAM_DATA_OFFSET);
TmpIndex --;
}
}
END: ;
}
/*****************************************************************************/
/**
* @brief
* This function calculates the MINV value and put it into RSA core registers.
*
* @param InstancePtr Pointer to XSeure_Rsa instance
*
* @return None
*
* @note MINV is the 32-bit value of `-M mod 2**32`,
* where M is LSB 32 bits of the original modulus.
*
******************************************************************************/
static void XSecure_RsaMod32Inverse(XSecure_Rsa *InstancePtr)
{
/* Calculate the MINV */
u8 Count;
u32 *ModPtr;
u32 ModVal;
u32 Inv;
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
ModPtr = (u32 *)(InstancePtr->Mod);
ModVal = Xil_Htonl(ModPtr[InstancePtr->SizeInWords - 1]);
Inv = (u32)2U - ModVal;
for (Count = 0U; Count < XSECURE_WORD_SIZE; ++Count) {
Inv = (Inv * (2U - ( ModVal * Inv ) ) );
}
Inv = ~Inv + 1U;
/* Put the value in MINV registers */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_MINV_OFFSET, (Inv));
}
/*****************************************************************************/
/**
* @brief
* This function writes data to RSA RAM at a given offset.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param WrData Pointer to the data to be written to RSA RAM
* @param RamOffset Offset for the data to be written in RSA RAM
*
* @return None
*
*
******************************************************************************/
static void XSecure_RsaWriteMem(XSecure_Rsa *InstancePtr, u32* WrData,
u8 RamOffset)
{
u32 Index;
u32 DataOffset;
u32 TmpIndex;
u32 Data;
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(WrData != NULL);
/** Each of this loop will write 192 bits of data*/
for (DataOffset = 0U; DataOffset < XSECURE_RSA_MAX_RD_WR_CNT;
DataOffset++) {
for (Index = 0U; Index < XSECURE_RSA_MAX_BUFF; Index++) {
TmpIndex = (DataOffset * XSECURE_RSA_MAX_BUFF) + Index;
/**
* Exponent size is only 4 bytes
* and rest of the data needs to be 0
*/
if((XSECURE_RSA_RAM_EXPO == RamOffset) &&
(InstancePtr->EncDec == XSECURE_RSA_SIGN_ENC)) {
if(0U == TmpIndex ) {
Data = *WrData;
}
else
{
Data = 0x0U;
}
}
else
{
if(TmpIndex >= InstancePtr->SizeInWords)
{
Data = 0x0U;
}
else
{
Data = WrData[(InstancePtr->SizeInWords - 1) - TmpIndex];
}
}
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_RAM_DATA_OFFSET,
Data);
}
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_RAM_ADDR_OFFSET,
((RamOffset * (u8)XSECURE_RSA_MAX_RD_WR_CNT) + DataOffset) |
XSECURE_ECDSA_RSA_RAM_ADDR_WRRD_B_MASK);
}
}
/*****************************************************************************/
/**
* @brief
* This function clears whole RSA memory space. This function clears stored
* exponent, modulus and exponentiation key components along with digest.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
*
* @return XST_SUCCESS On Success
* XSECURE_RSA_ZEROIZE_ERROR On Zeroization Failure
*
*****************************************************************************/
static u32 XSecure_RsaZeroize(XSecure_Rsa *InstancePtr)
{
u32 RamOffset = (u32)XSECURE_RSA_RAM_EXPO;
u32 DataOffset;
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_CTRL_OFFSET,
XSECURE_ECDSA_RSA_CTRL_CLR_DATA_BUF_MASK);
do {
for (DataOffset = 0U; DataOffset < XSECURE_RSA_MAX_RD_WR_CNT;
DataOffset++) {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_CTRL_OFFSET,
XSECURE_ECDSA_RSA_CTRL_CLR_DATA_BUF_MASK);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_RAM_ADDR_OFFSET,
((RamOffset * (u8)XSECURE_RSA_MAX_RD_WR_CNT) +
DataOffset) | XSECURE_ECDSA_RSA_RAM_ADDR_WRRD_B_MASK);
}
RamOffset++;
} while (RamOffset <= XSECURE_RSA_RAM_RES_Q);
Status = XSecure_RsaZeroizeVerify(InstancePtr);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_MINV_OFFSET, 0U);
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function verifies the Zeroization of RSA memory space.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
*
* @return XST_SUCCESS On Success
* XSECURE_RSA_ZEROIZE_ERROR On Zeroize Verify Failure
*
*****************************************************************************/
static u32 XSecure_RsaZeroizeVerify(XSecure_Rsa *InstancePtr)
{
u32 RamOffset = (u32)XSECURE_RSA_RAM_EXPO;
u32 DataOffset;
u32 Status = (u32)XST_FAILURE;
u32 Index;
u32 Data = 0U;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
do {
for (DataOffset = 0U; DataOffset < XSECURE_RSA_MAX_RD_WR_CNT;
DataOffset++) {
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_RAM_ADDR_OFFSET,
((RamOffset * (u8)XSECURE_RSA_MAX_RD_WR_CNT) +
DataOffset));
for (Index = 0U; Index < XSECURE_RSA_MAX_BUFF; Index++) {
Data |= XSecure_ReadReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_RAM_DATA_OFFSET);
}
if (Data != 0U) {
Status = (u32)XSECURE_RSA_ZEROIZE_ERROR;
goto END;
}
}
RamOffset++;
} while (RamOffset <= XSECURE_RSA_RAM_RES_Q);
if(((RamOffset - 1U) == XSECURE_RSA_RAM_RES_Q) &&
(DataOffset == XSECURE_RSA_MAX_RD_WR_CNT)) {
Status = (u32)XST_SUCCESS;
}
END:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function updates data length configuration
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
* @param Cfg0 QSEL, Multiplication passes
* @param Cfg1 Number of Montgomery digits
* @param Cfg2 Memory location size
* @param Cfg5 Number of groups
*
* @return None
*
******************************************************************************/
static void XSecure_RsaDataLenCfg(XSecure_Rsa *InstancePtr, u32 Cfg0, u32 Cfg1,
u32 Cfg2, u32 Cfg5)
{
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_CFG0_OFFSET,
Cfg0);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_CFG1_OFFSET,
Cfg1);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_CFG2_OFFSET,
Cfg2);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_ECDSA_RSA_CFG5_OFFSET,
Cfg5);
}
/*****************************************************************************/
/**
* @brief This function performs KAT on RSA core.
*
* @param None
*
* @return returns the error codes based on failure
* returns XST_SUCCESS on success
*
*****************************************************************************/
u32 XSecure_RsaPublicEncryptKat(void)
{
u32 Status = (u32) XST_FAILURE;
u32 Index;
XSecure_Rsa XSecureRsaInstance = {0U};
u32 RsaOutput[XSECURE_RSA_4096_SIZE_WORDS] = {0U};
u32 PubExponent = 0x1000100U;
u32 PubMod[XSECURE_RSA_4096_SIZE_WORDS] = {
0xDEEA35BFU, 0xA9390A70U, 0xD3A133F4U, 0x96C82012U,
0xF1B4A9FCU, 0xCBB2D621U, 0xDE17B607U, 0x889C5116U,
0xD583EAB7U, 0xA8A4DA84U, 0xDDF81C1EU, 0x7D92D62FU,
0x5825CDB4U, 0x83373CE3U, 0xCD8183D2U, 0x5824F2B4U,
0x1CE408AU, 0x6364B98DU, 0x249ACE72U, 0x86936129U,
0x48E12F23U, 0xEF812AA6U, 0x20F4C35CU, 0x5EC224BEU,
0xA4AC6E6CU, 0x3BE6F6B8U, 0x4DFE086CU, 0x20D42B7EU,
0xFB55E806U, 0xC75D424BU, 0xF911B49FU, 0x4DBD3243U,
0xA82BD76EU, 0x8A3D268DU, 0x4F4F021CU, 0xB422C6BDU,
0x141474D4U, 0x9447741DU, 0x3C34ED28U, 0x35C40477U,
0x8640D091U, 0xAFFCA575U, 0x2A5256B5U, 0xC87C910FU,
0xCEAFB060U, 0x168532E5U, 0x5E9CB92BU, 0xB2BDC427U,
0x775093AEU, 0x769CF306U, 0xE46C7EA1U, 0xB662A4DAU,
0xC6A2BD41U, 0xFEEE5DB1U, 0xB5C92F3U, 0x33DAB72CU,
0xF025A81BU, 0xE78EB2E3U, 0x445E9B6DU, 0x51150CEFU,
0xFDEA5E6EU, 0x91353083U, 0x71858335U, 0x5842847FU,
0xC9064172U, 0xCB4A69B4U, 0x941DC4CAU, 0x4AEC29C6U,
0xDF933D68U, 0xB09D064BU, 0xD0589906U, 0xAAFFB51CU,
0x59ED9D9FU, 0x58FC1833U, 0xA38C1F7AU, 0xB0F2882AU,
0x832003FAU, 0xB094B30DU, 0xA46F48F0U, 0x770BDF55U,
0x7CDB4FE4U, 0x47C38C2FU, 0x486E269FU, 0xCC9ECFB0U,
0xFA8EA989U, 0xDAFD71D9U, 0x7B827503U, 0x99B8E790U,
0xBF6B248AU, 0xB0708D66U, 0xFAAD86AU, 0x465286E7U,
0xCBC7A51BU, 0xC99CA789U, 0x4AD9B817U, 0xBC3DACD5U,
0x8F9AFEBAU, 0xE8A3E044U, 0x191F1FF6U, 0xB30A8A91U,
0x9D097F38U, 0xC256CA9U, 0x1487DA9AU, 0x5A621A8AU,
0x5AF64A31U, 0x2026EA4EU, 0xC742CF28U, 0xD7293B92U,
0x62FF06F7U, 0x11737E35U, 0xEA290617U, 0x6760A416U,
0x351E085AU, 0x881545D4U, 0x93F5B0FAU, 0xCDFE27EDU,
0x5722C835U, 0x992BA00DU, 0x8E92807FU, 0x40640AA2U,
0x1EC33449U, 0xCBC544D5U, 0x4B82607CU, 0xB7AED391U,
0xE4A9D04U, 0xD5EC03EFU, 0xEE2DC541U, 0x4734EF2CU
};
u32 PubModExt[XSECURE_RSA_4096_SIZE_WORDS] = {
0x1072128U, 0xA9D91E4FU, 0x8BD4A745U, 0x9058EFB4U,
0xBC9F68A4U, 0x4DE184BAU, 0x939DB10BU, 0xC42F56CAU,
0xD662CF06U, 0xFB14F40BU, 0xD07964E4U, 0xBF086090U,
0xFB0B13E3U, 0xFFC8F286U, 0xB936910FU, 0x4E4575EFU,
0x9DD97CB9U, 0x9CCC2992U, 0xCBD9D687U, 0x712E6B3CU,
0x1DEF1509U, 0x78F1CA37U, 0x13638D18U, 0xF993FB7EU,
0x1D83AA06U, 0xD0D46992U, 0x36F6530BU, 0xD92265F5U,
0x62E5928U, 0x88F895EAU, 0x80906CDDU, 0x2EB685F0U,
0xB9E8655BU, 0x76569FFBU, 0xB6A43E4AU, 0xFA0288E8U,
0xB175E83EU, 0x1D035495U, 0x95B58660U, 0x9513632BU,
0xD88E019CU, 0x17D1AAD9U, 0xDAC5F5FDU, 0x9E2162D4U,
0xDA958D42U, 0x52951DCU, 0x2C9C10A3U, 0x68764F11U,
0xCB8074ADU, 0xAADDDD83U, 0xAE5D6DCU, 0x6CB51D1EU,
0xC19F0CCFU, 0x3FDACC8EU, 0x7C1CE3A5U, 0x40ED8284U,
0x5A68AC97U, 0xD2CF1EFBU, 0x194EEE08U, 0x6BB881BAU,
0xEFF6A285U, 0x2EE71166U, 0x5F371394U, 0xED1C739CU,
0x1F74775EU, 0xCD8E355CU, 0xC655494EU, 0x51F9096AU,
0xAD38C482U, 0x609468EEU, 0x9AF0DE7FU, 0x5148BFB8U,
0x6C1A6002U, 0x82A31402U, 0x794DF7C2U, 0x4DDDF77BU,
0x4AC8A8B1U, 0x2AD0F70U, 0xAC59C156U, 0xA0201449U,
0xD846AA2U, 0xB0580AA4U, 0x5ADF6019U, 0x84EA2F7FU,
0x8A786136U, 0xB8F40500U, 0x5A30B93EU, 0x1C06EE92U,
0x47C88351U, 0x381A85A2U, 0xC97B3D53U, 0xF03DE4BFU,
0x23C7093CU, 0xF3D25331U, 0x41DE3C40U, 0x2851B11CU,
0xEE9CE871U, 0xF6E1DF36U, 0x997CABF5U, 0xE0418D6AU,
0xCEA8CE62U, 0x76C90330U, 0xD4FB71CEU, 0xE730CE08U,
0xCE8281B9U, 0xB3F086E6U, 0x28C781D5U, 0xF3010C68U,
0x1F2C9E0CU, 0xC8FDC2E4U, 0x56FB2AB6U, 0xC936782CU,
0x6807C093U, 0x4D7B0196U, 0x27D7484U, 0xA45FEA96U,
0xDA420C2U, 0xD59F961BU, 0x3B9520FBU, 0x986D84CCU,
0x18877364U, 0x74ED23F8U, 0x8655C5E0U, 0xB0375246U,
0xDEEC5B9AU, 0x68927AEAU, 0x2A53F7DBU, 0x185177EU
};
u32 RsaData[XSECURE_RSA_4096_SIZE_WORDS] = {
0xFB5746B3U, 0xE1249012U, 0x3E761408U, 0x1A20EA70U,
0xFEC2F788U, 0xB9D26394U, 0x28EDACFAU, 0xF315279AU,
0x14EDEFE9U, 0x615DDC05U, 0x7CC541E2U, 0xBEDFCBD5U,
0x10340132U, 0x12D0B62BU, 0xDA0DF681U, 0x1483D434U,
0x1EC8B752U, 0x84BE665EU, 0xA36B6D8EU, 0x3206E9C3U,
0x674E9334U, 0x8A9C9A1EU, 0xC00A671U, 0xC99232C4U,
0x4EDADD32U, 0x772A1723U, 0x2D6AC26CU, 0x483A595CU,
0x52396F81U, 0x11ADC94EU, 0x1D51959FU, 0x8F031B0U,
0x252F738BU, 0x228A0761U, 0x7943828U, 0x6B4FC9F4U,
0x95C40061U, 0xD12E3B31U, 0xC4AE32F7U, 0x29F5440DU,
0x62196195U, 0x1251FB63U, 0xF7C9CCF5U, 0x389CC3A0U,
0x5FDB5FD8U, 0xEC92259AU, 0x15CD9DBBU, 0x5CEB61F9U,
0xC809EFE5U, 0x164D9BC2U, 0x8015E50EU, 0x2C4CCB5BU,
0x51974B9DU, 0xC593D13BU, 0x12D1A12EU, 0xA12DF15EU,
0xB9502495U, 0xA7606F27U, 0xCA39CCA3U, 0xD1E1C5E0U,
0xF59010DDU, 0xABD85F14U, 0x383D1336U, 0x3CB96AU,
0xB44E2673U, 0xE5010A85U, 0xEB30A62BU, 0x5EC874C3U,
0x92D071A2U, 0x2A77897FU, 0x33D175C5U, 0x7E8262EEU,
0xDB7A4C30U, 0xB905302FU, 0x11B211B0U, 0xBE7686BFU,
0xB4A310ECU, 0x9860381FU, 0x3FFDB62FU, 0xA9363083U,
0xC204F6CAU, 0x524D78CDU, 0xED9DEF22U, 0xB6E423ADU,
0xE2D72240U, 0xC54F6C4AU, 0xBC7534AAU, 0xB5C983ACU,
0x34905EE3U, 0x1C091B10U, 0xB5BA27E5U, 0x1246388FU,
0x638DF44FU, 0x4228AA9EU, 0xB26EC356U, 0xAF51C1D4U,
0x3FE93343U, 0x55416B38U, 0x7CDCDC6EU, 0x4514C6E6U,
0xF4525F26U, 0x71D1875BU, 0xB51DDE41U, 0x5B29350CU,
0xFC4324B6U, 0x83794F3U, 0xE17F4C94U, 0xCFAAD44FU,
0xC7785A1CU, 0xD6C2B762U, 0x484F880EU, 0x3EA80383U,
0x1EA7DEE1U, 0x6E80A231U, 0x50AE13E4U, 0x4920CD14U,
0x564316BCU, 0x6787A7B0U, 0x31D0AA8BU, 0x5B2E3027U,
0xB162BD0CU, 0xEF4D0B8DU, 0x3F202FA6U, 0xF700AA63U,
0x9846789EU, 0x64187374U, 0xCE81837EU, 0xA1274EC4U,
};
u32 ExpectedOuptut[XSECURE_RSA_4096_SIZE_WORDS] = {
0xF01E7F12U, 0x16907AD3U, 0x97393EB1U, 0x2FF94AD4U,
0x7F284B09U, 0x9B8B4088U, 0xEBA032D9U, 0x5A39E014U,
0x84AEC0E8U, 0xC6534852U, 0xA7133235U, 0xD1A2A186U,
0x857A0A0FU, 0xF9BD6D42U, 0xA2C6AE0AU, 0xB84C78F1U,
0x365D3687U, 0xF16007FEU, 0xAEBACE68U, 0x702F47CAU,
0x77588CC3U, 0x64AA18A7U, 0x41F5903CU, 0xE9A66042U,
0xFCAD8CF5U, 0x9BCFDD6AU, 0x48CFE701U, 0xAB8A9A60U,
0xC44FF869U, 0x33CCDD6FU, 0xD9D6CB8U, 0xE4E80947U,
0xFA5FD5E5U, 0x6659F3B4U, 0xDA1EAE6CU, 0x9B2BC74CU,
0x3C185413U, 0x4E60C8A5U, 0x5DBBB9CBU, 0xDB798EFAU,
0xEEC6499BU, 0xA9B8482EU, 0xC3EBC620U, 0xF4FC186BU,
0x17AB77C3U, 0x59F8A652U, 0x20255B10U, 0x3B58F9FDU,
0x236D230CU, 0xB6C74CA0U, 0xEC7C713AU, 0x4F973A11U,
0x4FF0A23CU, 0xF6AF9908U, 0x98954827U, 0x5E4E84B4U,
0x9ECA7101U, 0x4A6FE9F4U, 0x9D005600U, 0xF957C2CAU,
0x24070AB0U, 0x4782E349U, 0x75E3B7F9U, 0xB35A5284U,
0x5EE62748U, 0xF386DBB2U, 0xDF8A1F53U, 0x1180E79U,
0x8BE3CCF0U, 0xC68E5DFAU, 0xA2EB3BE1U, 0x948AF00DU,
0x163974B9U, 0x8DF93CEU, 0xB1D999BU, 0x6F218229U,
0xDC837457U, 0x4E6B780AU, 0xD5F958BBU, 0x39B22A45U,
0xE0BBD9DDU, 0x30733DCBU, 0xE50AB62EU, 0xE53CDD36U,
0xF8FAE46BU, 0x99A11B85U, 0x78BC2A4EU, 0x9AE231A7U,
0xDB09602AU, 0x457D8FF1U, 0xEA0DC9C0U, 0x1A902E93U,
0xC6400F62U, 0xB6422450U, 0x49B6C9D2U, 0xD0C17339U,
0xB5A14341U, 0xDC9B068EU, 0x53254732U, 0xBC81D323U,
0x36EF95B4U, 0x4DC72014U, 0xE4B2C5D9U, 0xFE373BB6U,
0x9B615CCBU, 0xD353DE7CU, 0xA1BBE0AEU, 0x6A48AEE0U,
0x443A08CCU, 0xED9A4F0FU, 0x646E0527U, 0x7D97CE4BU,
0x20D0043EU, 0x7CEE630CU, 0x7421D73U, 0xD91834B3U,
0xFE9D263FU, 0x1F7EA716U, 0x436CD24U, 0xF7E84A7FU,
0x224829B5U, 0x46DF012U, 0x5C6325E2U, 0x3C39F1FDU,
0xC0418AB2U, 0x4EF12694U, 0x1CF20CC0U, 0xAFC64ADAU};
XSecure_RsaInitialize(&XSecureRsaInstance, (u8 *)PubMod,
(u8 *)PubModExt, (u8 *)&PubExponent);
Status = XSecure_RsaPublicEncrypt(&XSecureRsaInstance, (u8 *)RsaData, 512U,
(u8 *)RsaOutput);
if (Status != (u32)XST_SUCCESS) {
Status = XSECURE_RSA_KAT_ENCRYPT_FAILED_ERROR;
goto END;
}
/* Initialized to error */
Status = XSECURE_RSA_KAT_ENCRYPT_DATA_MISMATCH_ERROR;
for (Index = 0U; Index < XSECURE_RSA_4096_SIZE_WORDS; Index++) {
if (RsaOutput[Index] != ExpectedOuptut[Index]) {
goto END;
}
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function returns PKCS padding as per the silicon version
*
* @param None
* @return XSecure_Silicon2_TPadSha3
*
*****************************************************************************/
u8* XSecure_RsaGetTPadding()
{
return (u8 *)XSecure_Silicon2_TPadSha3;
}
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/csudma_v1_6/src/xpmcdma.h
/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* The file is a wrapper that calls APIs declared in xscudma.h This wrapper is
* added for Versal as there is no CSU DMA in Versal and hence the Versal
* libraries should have no reference to CSU DMA. This is a security requirement.
*
* The PMC_DMA is present inside PMC (Platform Management Controller) module.
* PMC_DMA allows the PMC to move data efficiently between the memory (128 bit
* AXI interface) and the PMC stream peripherals (SHA, AES and SBI) via Secure
* Stream Switch (SSS).
*
* The PMC_DMA is a 2 channel simple DMA, allowing separate control of the SRC
* (read) channel and DST (write) channel. The DMA is effectively able to
* transfer data:
* - From PMC to the SSS-side (SRC DMA only)
* - From SSS-side to the PMC (DST DMA only)
* - Simultaneous PMC to SSS_side and SSS-side to PMC
*
* Initialization & Configuration
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the PMC_DMA core. The device driver internally calls CSU DMA
* APIs.
*
* XPmcDma_CfgInitialize() API is used to initialize the PMC_DMA core.
* The user needs to first call the XPmcDma_LookupConfig() API which returns
* the Configuration structure pointer which is passed as a parameter to the
* XPmcDma_CfgInitialize() API.
*
* Reset
* This driver will not support handling of CRP PDMA Reset in case of PMC_DMA
* inorder to support multiple level of handoff's. User needs to call
* the XPmcDma_Reset() API before performing any driver operation to make
* sure PMC_DMA is in proper state.
*
* Interrupts
* This driver will not support handling of interrupts user should write handler
* to handle the interrupts.
*
* Virtual Memory
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
* Threads
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* Asserts
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* Building the driver
*
* The XPmcDma driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* This header file contains identifiers and register-level driver functions (or
* macros), range macros, structure typedefs that can be used to access the
* Xilinx PMC_DMA core instance.
*
* The functionality wise ZU+ CSU_DMA and Versal PMC_DMA are similar, so all ZU+
* code is reused by wrapping in this file
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------------
* 1.0 mmd 01/04/20 First release
*
******************************************************************************/
#ifndef XPMCDMA_H_
#define XPMCDMA_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xcsudma.h"
#if defined (versal)
/************************** Constant Definitions *****************************/
/** Ranges of Size */
#define PMCDMA_0_DEVICE_ID XPAR_XCSUDMA_0_DEVICE_ID /* PMCDMA device Id */
#define PMCDMA_1_DEVICE_ID XPAR_XCSUDMA_1_DEVICE_ID /* PMCDMA device Id */
#define PMCDMA_LOOPBACK_CFG (0x0000000FU) /* LOOP BACK configuration */
#define XPMCDMA_SIZE_MAX XCSUDMA_SIZE_MAX /* Maximum allowed no of words */
#define XPMCDMA_ADDR_LSB_MASK XCSUDMA_ADDR_LSB_MASK
#define XPMCDMA_DMATYPEIS_DMA0 XCSUDMA_DMATYPEIS_PMCDMA0
#define XPMCDMA_DMATYPEIS_DMA1 XCSUDMA_DMATYPEIS_PMCDMA1
#define XPMCDMA_SRC_CHANNEL XCSUDMA_SRC_CHANNEL
#define XPMCDMA_DST_CHANNEL XCSUDMA_DST_CHANNEL
#define XPMCDMA_PAUSE_MEMORY XCSUDMA_PAUSE_MEMORY
#define XPMCDMA_PAUSE_STREAM XCSUDMA_PAUSE_STREAM
/** Interrupt Enable/Disable/Mask/Status registers bit masks */
#define XPMCDMA_IXR_FIFO_OVERFLOW_MASK XCSUDMA_IXR_FIFO_OVERFLOW_MASK
/**< FIFO overflow mask, it is valid only to Destination Channel */
#define XPMCDMA_IXR_INVALID_APB_MASK XCSUDMA_IXR_INVALID_APB_MASK
/**< Invalid APB access mask */
#define XPMCDMA_IXR_FIFO_THRESHHIT_MASK XCSUDMA_IXR_FIFO_THRESHHIT_MASK
/**< FIFO threshold hit indicator mask */
#define XPMCDMA_IXR_TIMEOUT_MEM_MASK XCSUDMA_IXR_TIMEOUT_MEM_MASK
/**< Time out counter expired to access memory mask */
#define XPMCDMA_IXR_TIMEOUT_STRM_MASK XCSUDMA_IXR_TIMEOUT_STRM_MASK
/**< Time out counter expired to access stream mask */
#define XPMCDMA_IXR_AXI_WRERR_MASK XCSUDMA_IXR_AXI_WRERR_MASK
/**< AXI Read/Write error mask */
#define XPMCDMA_IXR_DONE_MASK XCSUDMA_IXR_DONE_MASK
/**< Done mask */
#define XPMCDMA_IXR_MEM_DONE_MASK XCSUDMA_IXR_MEM_DONE_MASK
/**< Memory done mask, it is valid only for source channel*/
#define XPMCDMA_IXR_SRC_MASK XCSUDMA_IXR_SRC_MASK
/**< All interrupt mask for source */
#define XPMCDMA_IXR_DST_MASK XCSUDMA_IXR_DST_MASK
/**< All interrupt mask for destination */
/**************************** Type Definitions *******************************/
/**
* This typedef contains PMC_DMA Channel Types.
* Note that the enum values are mapped with #define above as
* XPMCDMA_SRC_CHANNEL = XCSUDMA_SRC_CHANNEL
* XPMCDMA_DST_CHANNEL = XCSUDMA_DST_CHANNEL
*/
typedef XCsuDma_Channel XPmcDma_Channel;
/**
* This typedef contains PMC_DMA Pause Types.
* Note that the enum values are mapped with #define above as
* XPMCDMA_PAUSE_MEMORY = XCSUDMA_PAUSE_MEMORY
* XPMCDMA_PAUSE_STREAM = XCSUDMA_PAUSE_STREAM
*/
typedef XCsuDma_PauseType XPmcDma_PauseType;
/**
* This typedef contains configuration information for a PMC_DMA core.
* Each PMC_DMA core should have a configuration structure associated.
*/
typedef XCsuDma_Config XPmcDma_Config;
/******************************************************************************/
/**
*
* The XPmcDma driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef XCsuDma XPmcDma;
/******************************************************************************/
/**
* This typedef contains all the configuration fields which needs to be set
* before the start of the data transfer. All these feilds of PMC_DMA can be
* configured by using XPmcDma_SetConfig API.
*/
typedef XCsuDma_Configure XPmcDma_Configure;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* This function resets the PMC_DMA core.
*
* @param DmaType is the type of DMA
* XPMCDMA_DMATYPEIS_DMA0 or XPMCDMA_DMATYPEIS_DMA1).
*
* @return None.
*
******************************************************************************/
static INLINE void XPmcDma_Reset(u32 DmaType)
{
XCsuDma_PmcReset(DmaType);
}
/*****************************************************************************/
/**
* This function will wait for DMA operation to complete
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return None.
*
* @note This function should be called after XPmcDma_Transfer in polled
* mode to wait until the data gets transfered completely.
*
******************************************************************************/
static INLINE int XPmcDma_WaitForDone(XPmcDma *InstancePtr, XPmcDma_Channel Channel)
{
XCsuDma_WaitForDone(InstancePtr, Channel);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function returns the number of completed SRC/DST DMA transfers that
* have not been acknowledged by software based on the channel selection.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return Count is number of completed DMA transfers but not acknowledged
* (Range is 0 to 7).
* - 000 - All finished transfers have been acknowledged.
* - Count - Count number of finished transfers are still
* outstanding.
*
******************************************************************************/
static INLINE u32 XPmcDma_GetDoneCount(XPmcDma *InstancePtr, XPmcDma_Channel Channel)
{
return XCsuDma_GetDoneCount(InstancePtr, Channel);
}
/*****************************************************************************/
/**
*
* This function returns the current SRC/DST FIFO level in 32 bit words of the
* selected channel
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return FIFO level. (Range is 0 to 128)
* - 0 Indicates empty
* - Any number 1 to 128 indicates the number of entries in FIFO.
*
******************************************************************************/
static INLINE u32 XPmcDma_GetFIFOLevel(XPmcDma *InstancePtr, XPmcDma_Channel Channel)
{
return XCsuDma_GetFIFOLevel(InstancePtr, Channel);
}
/*****************************************************************************/
/**
*
* This function returns the current number of read(src)/write(dst) outstanding
* commands based on the type of channel selected.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return Count of outstanding commands. (Range is 0 to 9).
*
******************************************************************************/
static INLINE u32 XPmcDma_GetWROutstandCount(XPmcDma *InstancePtr,
XPmcDma_Channel Channel)
{
return XCsuDma_GetWROutstandCount(InstancePtr, Channel);
}
/*****************************************************************************/
/**
*
* This function returns the status of Channel either it is busy or not.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return Returns the current status of the core.
* - TRUE represents core is currently busy.
* - FALSE represents core is not involved in any transfers.
*
******************************************************************************/
static INLINE u32 XPmcDma_IsBusy(XPmcDma *InstancePtr, XPmcDma_Channel Channel)
{
return XCsuDma_IsBusy(InstancePtr, Channel);
}
/*****************************************************************************/
/**
*
* XPmcDma_LookupConfig returns a reference to an XPmcDma_Config structure
* based on the unique device id, <i>DeviceId</i>. The return value will refer
* to an entry in the device configuration table defined in the xcsudma_g.c
* file.
*
* @param DeviceId is the unique device ID of the device for the lookup
* operation.
*
* @return CfgPtr is a reference to a config record in the configuration
* table (in xcsudma_g.c) corresponding to <i>DeviceId</i>, or
* NULL if no match is found.
*
******************************************************************************/
static INLINE XPmcDma_Config * XPmcDma_LookupConfig(u16 DeviceId)
{
return XCsuDma_LookupConfig(DeviceId);
}
/*****************************************************************************/
/**
*
* This function initializes an PMC_DMA core. This function must be called
* prior to using an PMC_DMA core. Initialization of an PMC_DMA includes setting
* up the instance data and ensuring the hardware is in a quiescent state.
*
* @param InstancePtr is a pointer to the XPmcDma instance.
* @param CfgPtr is a reference to a structure containing information
* about a specific XPmcDma instance.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. The caller is responsible for keeping the
* address mapping from EffectiveAddr to the device physical
* base address unchanged once this function is invoked.
* Unexpected errors may occur if the address mapping changes
* after this function is called. If address translation is not
* used, pass in the physical address instead.
*
* @return
* - XST_SUCCESS if initialization was successful.
*
******************************************************************************/
static INLINE s32 XPmcDma_CfgInitialize(XPmcDma *InstancePtr, XPmcDma_Config *CfgPtr,
u32 EffectiveAddr)
{
return XCsuDma_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr);
}
/*****************************************************************************/
/**
*
* This function sets the starting address and amount(size) of the data to be
* transfered from/to the memory through the AXI interface.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
* @param Addr is a 64 bit variable which holds the starting address of
* data which needs to write into the memory(DST) (or read from
* the memory(SRC)).
* @param Size is a 32 bit variable which represents the number of 4 byte
* words needs to be transfered from starting address.
* @param EnDataLast is to trigger an end of message. It will enable or
* disable data_inp_last signal to stream interface when current
* command is completed. It is applicable only to source channel
* and neglected for destination channel.
* - 1 - Asserts data_inp_last signal.
* - 0 - data_inp_last will not be asserted.
*
* @return None.
*
* @note Data_inp_last signal is asserted simultaneously with the
* data_inp_valid signal associated with the final 32-bit word
* transfer.
*
******************************************************************************/
static INLINE void XPmcDma_Transfer(XPmcDma *InstancePtr, XPmcDma_Channel Channel,
UINTPTR Addr, u32 Size, u8 EnDataLast)
{
XCsuDma_Transfer(InstancePtr, Channel, Addr, Size, EnDataLast);
}
/*****************************************************************************/
/**
*
* This function sets the starting address and amount(size) of the data to be
* transfered from/to the memory through the AXI interface.
* This function is useful for pmu processor when it wishes to do
* a 64-bit DMA transfer.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
* @param AddrLow is a 32 bit variable which holds the starting lower
* address of data which needs to write into the memory(DST)
* (or read from the memory(SRC)).
* @param AddrHigh is a 32 bit variable which holds the higher address of data
* which needs to write into the memory(DST) (or read from
* the memroy(SRC)).
* @param Size is a 32 bit variable which represents the number of 4 byte
* words needs to be transfered from starting address.
* @param EnDataLast is to trigger an end of message. It will enable or
* disable data_inp_last signal to stream interface when current
* command is completed. It is applicable only to source channel
* and neglected for destination channel.
* - 1 - Asserts data_inp_last signal.
* - 0 - data_inp_last will not be asserted.
*
* @return None.
*
* @note Data_inp_last signal is asserted simultaneously with the
* data_inp_valid signal associated with the final 32-bit word
* transfer
* This API won't do flush/invalidation for the DMA buffer.
* It is recommened to call this API only through PMU processor.
*
******************************************************************************/
static INLINE void XPmcDma_64BitTransfer(XPmcDma *InstancePtr, XPmcDma_Channel Channel,
u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast)
{
XCsuDma_64BitTransfer(InstancePtr, Channel, AddrLow, AddrHigh,
Size, EnDataLast);
}
/*****************************************************************************/
/**
*
* This function returns the current address location of the memory, from where
* it has to read the data(SRC) or the location where it has to write the data
* (DST) based on the channel selection.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return Address is a 64 bit variable which holds the current address.
* - From this location data has to be read(SRC)
* - At this location data has to be written(DST)
*
******************************************************************************/
static INLINE u64 XPmcDma_GetAddr(XPmcDma *InstancePtr, XPmcDma_Channel Channel)
{
return XCsuDma_GetAddr(InstancePtr, Channel);
}
/*****************************************************************************/
/**
*
* This function returns the size of the data yet to be transfered from memory
* to PMC_DMA or PMC_DMA to memory based on the channel selection.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return Size is amount of data yet to be transfered.
*
******************************************************************************/
static INLINE u32 XPmcDma_GetSize(XPmcDma *InstancePtr, XPmcDma_Channel Channel)
{
return XCsuDma_GetSize(InstancePtr, Channel);
}
/*****************************************************************************/
/**
*
* This function pause the Channel data tranfer to/from memory or to/from stream
* based on pause type.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
* @param Type is type of the pause to be enabled.
* - XPMCDMA_PAUSE_MEMORY(0) - Pause memory
* - SRC Stops issuing of new read commands to memory.
* - DST Stops issuing of new write commands to memory.
* - XPMCDMA_PAUSE_STREAM(1) - Pause stream
* - SRC Stops transfer of data from FIFO to Stream.
* - DST Stops transfer of data from stream to FIFO.
*
* @return None.
*
******************************************************************************/
static INLINE void XPmcDma_Pause(XPmcDma *InstancePtr, XPmcDma_Channel Channel,
XPmcDma_PauseType Type)
{
XCsuDma_Pause(InstancePtr, Channel,Type);
}
/*****************************************************************************/
/**
*
* This functions checks whether Channel's memory or stream is paused or not
* based on the given pause type.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
* @param Type is type of the pause which needs to be checked.
* - XPMCDMA_PAUSE_MEMORY(0) - Pause memory
* - SRC Stops issuing of new read commands to memory.
* - DST Stops issuing of new write commands to memory.
* - XPMCDMA_PAUSE_STREAM(1) - Pause stream
* - SRC Stops transfer of data from FIFO to Stream.
* - DST Stops transfer of data from stream to FIFO.
*
* @return Returns the pause status.
* - TRUE if it is in paused state.
* - FALSE if it is not in pause state.
*
******************************************************************************/
static INLINE s32 XPmcDma_IsPaused(XPmcDma *InstancePtr, XPmcDma_Channel Channel,
XPmcDma_PauseType Type)
{
return XCsuDma_IsPaused(InstancePtr, Channel, Type);
}
/*****************************************************************************/
/**
*
* This function resumes the channel if it is in paused state and continues
* where it has left or no effect if it is not in paused state, based on the
* type of pause.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
* @param Type is type of the pause to be Resume if it is in pause
* state.
* - XPMCDMA_PAUSE_MEMORY(0) - Resume memory
* - SRC Resumes issuing of new read commands to memory.
* - DST Resumes issuing of new write commands to memory.
* - XPMCDMA_PAUSE_STREAM(1) - Resules stream
* - SRC Resumes transfer of data from FIFO to Stream.
* - DST Resumes transfer of data from stream to FIFO.
*
* @return None.
*
******************************************************************************/
static INLINE void XPmcDma_Resume(XPmcDma *InstancePtr, XPmcDma_Channel Channel,
XPmcDma_PauseType Type)
{
XCsuDma_Resume(InstancePtr, Channel, Type);
}
/*****************************************************************************/
/**
*
* This function returns the sum of all the data read from AXI memory. It is
* valid only one we use PMC_DMA source channel.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
*
* @return Returns the sum of all the data read from memory.
*
* @note Before start of the transfer need to clear this register to get
* correct sum otherwise it adds to previous value which results
* to wrong output.
* Valid only for source channel
*
******************************************************************************/
static INLINE u32 XPmcDma_GetCheckSum(XPmcDma *InstancePtr)
{
return XCsuDma_GetCheckSum(InstancePtr);
}
/*****************************************************************************/
/**
*
* This function clears the check sum of the data read from AXI memory. It is
* valid only for PMC_DMA source channel.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
*
* @return Returns the sum of all the data read from memory.
*
* @note Before start of the transfer need to clear this register to get
* correct sum otherwise it adds to previous value which results
* to wrong output.
*
******************************************************************************/
static INLINE void XPmcDma_ClearCheckSum(XPmcDma *InstancePtr)
{
XCsuDma_ClearCheckSum(InstancePtr);
}
/*****************************************************************************/
/**
* This function cofigures all the values of PMC_DMA's Channels with the values
* of updated XPmcDma_Configure structure.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
* @param ConfigurValues is a pointer to the structure XPmcDma_Configure
* whose values are used to configure PMC_DMA core.
* - SssFifoThesh When the DST FIFO level >= this value,
* the SSS interface signal, "data_out_fifo_level_hit" will be
* asserted. This mechanism can be used by the SSS to flow
* control data that is being looped back from the SRC DMA.
* - Range is (0x10 to 0x7A) threshold is 17 to 123
* entries.
* - It is valid only for DST PMC_DMA IP.
* - ApbErr When accessed to invalid APB the resulting
* pslerr will be
* - 0 - 1'b0
* - 1 - 1'b1
* - EndianType Type of endianness
* - 0 doesn't change order
* - 1 will flip the order.
* - AxiBurstType....Type of the burst
* - 0 will issue INCR type burst
* - 1 will issue FIXED type burst
* - TimeoutValue Time out value for timers
* - 0x000 to 0xFFE are valid inputs
* - 0xFFF clears both timers
* - FifoThresh......Programmed watermark value
* - Range is 0x00 to 0x80 (0 to 128 entries).
* - Acache Sets the AXI CACHE bits on the AXI Write/Read
* channel.
* - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
* for DST channel are always 1, we need to configure
* remaining 3 signal support
* (Bufferable, Read allocate and Write allocate).
* Valid inputs are:
* - 0x000 - Cacheable, but do not allocate
* - 0x001 - Cacheable and bufferable, but do not allocate
* - 0x010 - Cacheable write-through, allocate on reads
* only
* - 0x011 - Cacheable write-back, allocate on reads only
* - 0x100 - Cacheable write-through, allocate on writes
* only
* - 0x101 - Cacheable write-back, allocate on writes only
* - 0x110 - Cacheable write-through, allocate on both
* reads and writes
* - 0x111 - Cacheable write-back, allocate on both reads
* and writes
* - RouteBit To select route
* - 0 : Command will be routed normally
* - 1 : Command will be routed to APU's cache controller
* - TimeoutEn To enable or disable time out counters
* - 0 : The 2 Timeout counters are disabled
* - 1 : The 2 Timeout counters are enabled
* - TimeoutPre Set the prescaler value for the timeout in
* clk (~1.6 ns) cycles
* - Range is 0x000(Prescaler enables timer every cycles)
* to 0xFFF(Prescaler enables timer every 4096 cycles)
* - MaxOutCmds Controls the maximumum number of outstanding
* AXI read commands issued.
* - Range is 0x0(Up to 1 Outstanding Read command
* allowed) to 0x8 (Up to 9 Outstanding Read
* command allowed)
*
* @return None.
*
* @note To use timers timeout value Timeout enable field should be
* enabled.
*
******************************************************************************/
static INLINE void XPmcDma_SetConfig(XPmcDma *InstancePtr, XPmcDma_Channel Channel,
XPmcDma_Configure *ConfigurValues)
{
XCsuDma_SetConfig(InstancePtr, Channel, ConfigurValues);
}
/*****************************************************************************/
/**
*
* This function updates XPmcDma_Configure structure members with the cofigured
* values of PMC_DMA's Channel.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
* @param ConfigurValues is a pointer to the structure XPmcDma_Configure
* whose members are updated with configurations of PMC_DMA core.
* - SssFifoThesh When the DST FIFO level >= this value,
* the SSS interface signal, "data_out_fifo_level_hit" will be
* asserted. This mechanism can be used by the SSS to flow
* control data that is being looped back from the SRC DMA.
* - Range is (0x10 to 0x7A) threshold is 17 to 123
* entries.
* - It is valid only for DST PMC_DMA IP.
* - ApbErr When accessed to invalid APB the resulting
* pslerr will be
* - 0 - 1'b0
* - 1 - 1'b1
* - EndianType Type of endianness
* - 0 doesn't change order
* - 1 will flip the order.
* - AxiBurstType....Type of the burst
* - 0 will issue INCR type burst
* - 1 will issue FIXED type burst
* - TimeoutValue Time out value for timers
* - 0x000 to 0xFFE are valid inputs
* - 0xFFF clears both timers
* - FifoThresh......Programmed watermark value
* - Range is 0x00 to 0x80 (0 to 128 entries).
* - Acache Sets the AXI CACHE bits on the AXI Write/Read
* channel.
* - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
* for DST channel are always 1, we need to configure
* remaining 3 signal support
* (Bufferable, Read allocate and Write allocate).
* Valid inputs are:
* - 0x000 - Cacheable, but do not allocate
* - 0x001 - Cacheable and bufferable, but do not allocate
* - 0x010 - Cacheable write-through, allocate on reads
* only
* - 0x011 - Cacheable write-back, allocate on reads only
* - 0x100 - Cacheable write-through, allocate on writes
* only
* - 0x101 - Cacheable write-back, allocate on writes only
* - 0x110 - Cacheable write-through, allocate on both
* reads and writes
* - 0x111 - Cacheable write-back, allocate on both reads
* and writes
* - RouteBit To select route
* - 0 : Command will be routed based normally
* - 1 : Command will be routed to APU's cache controller
* - TimeoutEn To enable or disable time out counters
* - 0 : The 2 Timeout counters are disabled
* - 1 : The 2 Timeout counters are enabled
* - TimeoutPre Set the prescaler value for the timeout in
* clk (~1.6 ns) cycles
* - Range is 0x000(Prescaler enables timer every cycles)
* to 0xFFF(Prescaler enables timer every 4096 cycles)
* - MaxOutCmds Controls the maximumum number of outstanding
* AXI read commands issued.
* - Range is 0x0(Up to 1 Outstanding Read command
* allowed) to 0x8 (Up to 9 Outstanding Read command
* allowed)
*
* @return None.
*
******************************************************************************/
static INLINE void XPmcDma_GetConfig(XPmcDma *InstancePtr, XPmcDma_Channel Channel,
XPmcDma_Configure *ConfigurValues)
{
XCsuDma_GetConfig(InstancePtr, Channel,ConfigurValues);
}
/*****************************************************************************/
/**
* This function will poll for completion of data transfer periodically until
* DMA done bit set or till the timeout occurs.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return XST_SUCCESS - Incase of Success
* XST_FAILURE - Incase of Timeout.
*
******************************************************************************/
static INLINE u32 XPmcDma_WaitForDoneTimeout(XPmcDma *InstancePtr,
XPmcDma_Channel Channel)
{
return XCsuDma_WaitForDoneTimeout(InstancePtr, Channel);
}
/* Interrupt related APIs */
/*****************************************************************************/
/**
*
* This function returns interrupt status read from Interrupt Status Register.
* Use the XPMCDMA_IXR_*_MASK constants defined in xpmcdma.h to interpret the
* returned value.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return The pending interrupts of the PMC_DMA. Use th following masks
* to interpret the returned value.
* XPMCDMA_IXR_SRC_MASK - For Source channel
* XPMCDMA_IXR_DST_MASK - For Destination channel
*
******************************************************************************/
static INLINE u32 XPmcDma_IntrGetStatus(XPmcDma *InstancePtr, XPmcDma_Channel Channel)
{
return XCsuDma_IntrGetStatus(InstancePtr, Channel);
}
/*****************************************************************************/
/**
*
* This function returns interrupt status read from Interrupt Status Register.
* Use the XPMCDMA_IXR_*_MASK constants defined in xpmcdma.h to interpret the
* returned value.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return The pending interrupts of the PMC_DMA. Use th following masks
* to interpret the returned value.
* XPMCDMA_IXR_SRC_MASK - For Source channel
* XPMCDMA_IXR_DST_MASK - For Destination channel
*
******************************************************************************/
static INLINE void XPmcDma_IntrClear(XPmcDma *InstancePtr, XPmcDma_Channel Channel,
u32 Mask)
{
XCsuDma_IntrClear(InstancePtr, Channel, Mask);
}
/*****************************************************************************/
/**
*
* This function enables the interrupt(s). Use the XPMCDMA_IXR_*_MASK constants
* defined in xpmcdma.h to create the bit-mask to enable interrupts.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
* @param Mask contains interrupts to be enabled.
* - Bit positions of 1 will be enabled.
* This mask is formed by OR'ing XPMCDMA_IXR_*_MASK bits defined
* in xpmcdma.h.
*
* @return None.
*
******************************************************************************/
static INLINE void XPmcDma_EnableIntr(XPmcDma *InstancePtr, XPmcDma_Channel Channel,
u32 Mask)
{
XCsuDma_EnableIntr(InstancePtr, Channel, Mask);
}
/*****************************************************************************/
/**
*
* This function disables the interrupt(s). Use the XPMCDMA_IXR_*_MASK constants
* defined in xpmcdma.h to create the bit-mask to disable interrupts.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
* @param Mask contains interrupts to be disabled.
* - Bit positions of 1 will be disabled.
* This mask is formed by OR'ing XPMCDMA_IXR_*_MASK bits defined
* in xpmcdma.h.
*
* @return None.
*
******************************************************************************/
static INLINE void XPmcDma_DisableIntr(XPmcDma *InstancePtr, XPmcDma_Channel Channel,
u32 Mask)
{
XCsuDma_DisableIntr(InstancePtr, Channel, Mask);
}
/*****************************************************************************/
/**
*
* This function returns the interrupt mask to know which interrupts are
* enabled and which of them were disaled.
*
* @param InstancePtr is a pointer to XPmcDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XPMCDMA_SRC_CHANNEL
* Destination Channel - XPMCDMA_DST_CHANNEL
*
* @return The current interrupt mask. The mask indicates which interrupts
* are enabled/disabled.
* 0 bit represents .....corresponding interrupt is enabled.
* 1 bit represents .....Corresponding interrupt is disabled.
* To interpret returned mask use
* XPMCDMA_IXR_SRC_MASK........For source channel
* XPMCDMA_IXR_DST_MASK........For destination channel
*
******************************************************************************/
static INLINE u32 XPmcDma_GetIntrMask(XPmcDma *InstancePtr, XPmcDma_Channel Channel)
{
return XCsuDma_GetIntrMask(InstancePtr, Channel);
}
/*****************************************************************************/
/**
*
* This function runs a self-test on the driver and hardware device. Performs
* reset of both source and destination channels and checks if reset is working
* properly or not.
*
* @param InstancePtr is a pointer to the XPmcDma instance.
*
* @return
* - XST_SUCCESS if the self-test passed.
* - XST_FAILURE otherwise.
*
******************************************************************************/
static INLINE s32 XPmcDma_SelfTest(XPmcDma *InstancePtr)
{
return XCsuDma_SelfTest(InstancePtr);
}
/******************************************************************************/
#endif
#ifdef __cplusplus
}
#endif
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_requirement.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_REQUIREMENT_H_
#define XPM_REQUIREMENT_H_
#include "xpm_device.h"
#include "xpm_subsystem.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct XPm_ReqmInfo XPm_ReqmInfo;
typedef struct XPm_Reqm XPm_Requirement;
/**
* Specific requirement information.
*/
struct XPm_ReqmInfo {
u32 Capabilities:4; /**< Device capabilities (1-hot) */
u32 Latency:21; /**< Maximum device latency */
u32 QoS:7; /**< QoS requirement */
};
typedef enum {
RELEASE_ONE,
RELEASE_ALL,
RELEASE_UNREQUESTED,
RELEASE_DEVICE,
} XPm_ReleaseScope;
enum XPm_ReqUsageFlags{
REQ_NO_RESTRICTION,
REQ_SHARED,
REQ_NONSHARED,
REQ_TIME_SHARED,
};
enum XPm_ReqSecurityFlags{
REQ_ACCESS_SECURE,
REQ_ACCESS_SECURE_NONSECURE,
};
#define MAX_REQ_PARAMS 1U
#define REG_FLAGS_USAGE_MASK 0x3U
#define REG_FLAGS_SECURITY_MASK 0x4U
#define REG_FLAGS_SECURITY_OFFSET 0x2U
/**
* The requirement class.
*/
struct XPm_Reqm {
struct XPm_Subsystem *Subsystem; /**< Subsystem imposing this requirement on the device */
XPm_Device *Device; /**< Device used by the subsystem */
XPm_Requirement *NextDevice; /**< Requirement on the next device from this subsystem */
XPm_Requirement *NextSubsystem; /**< Requirement from the next subsystem on this device */
u8 Allocated; /**< Device has been allocated to the subsystem */
u8 SetLatReq; /**< Latency has been set from the subsystem */
u8 Flags; /** Flags */
u8 NumParams; /**< Params count */
u32 Params[MAX_REQ_PARAMS]; /**< Params */
XPm_ReqmInfo Curr; /**< Current requirements */
XPm_ReqmInfo Next; /**< Pending requirements */
};
/************************** Function Prototypes ******************************/
XStatus XPmRequirement_Add(XPm_Subsystem *Subsystem, XPm_Device *Device, u32 Flags, u32 *Params, u32 NumParams);
void XPm_RequiremntUpdate(XPm_Requirement *Reqm);
XStatus XPmRequirement_Release(XPm_Requirement *Reqm, XPm_ReleaseScope Scope);
void XPmRequirement_Clear(XPm_Requirement* Reqm);
XStatus XPmRequirement_UpdateScheduled(XPm_Subsystem *Subsystem, u32 Swap);
XStatus XPmRequirement_IsExclusive(XPm_Requirement *Reqm);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_REQUIREMENT_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_clock.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#ifndef PM_CLOCK_H_
#define PM_CLOCK_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_pll.h"
typedef struct PmClockClass PmClockClass;
typedef struct PmNode PmNode;
/*********************************************************************
* Macros
********************************************************************/
#define INVALID_DIV_ID(divId) \
((divId != PM_CLOCK_DIV0_ID) && (divId != PM_CLOCK_DIV1_ID))
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmClock - Basic clock structure
* @derived Pointer to the derived clock structure
* @class Pointer to the clock class
* @id Clock identifier
*/
typedef struct PmClock {
void* const derived;
const PmClockClass* const class;
const u8 id;
} PmClock;
/*********************************************************************
* Function declarations
********************************************************************/
s32 PmClockRequest(PmNode* const node);
s32 PmClockIsActive(PmNode* const node);
s32 PmClockMuxSetParent(PmClock* const clock, const u32 select);
s32 PmClockMuxGetParent(PmClock* const clock, u32 *const select);
s32 PmClockGateSetState(PmClock* const clock, const u8 enable);
s32 PmClockGateGetState(PmClock* const clock, u8* const enable);
s32 PmClockDividerSetVal(PmClock* const clock, const u32 divId, const u32 val);
s32 PmClockDividerGetVal(PmClock* const clock, const u32 divId, u32* const val);
s32 PmClockCheckPermission(const PmClock* const clock, const u32 ipiMask);
void PmClockInit(void);
void PmClockRelease(PmNode* const node);
void PmClockConstructList(void);
void PmClockRestore(PmNode* const node);
void PmClockSave(PmNode* const node);
PmClock* PmClockGetById(const u32 clockId);
void PmClockRestoreDdr(void);
#ifdef __cplusplus
}
#endif
#endif /* PM_CLOCK_H_ */
<file_sep>/python_drivers/qutag_examples/qutag-DeviceSettings.py
# Example for using the Coincidence Counters with python + quTAG
#
# Author: qutools GmbH
# Last edited: Sep 2019
#
# Tested with python 3.7.3 (32bit), Windows 7 (64bit)
#
# This is demo code. Use at your own risk. No warranties.
#
# It may be used and modified with no restriction; raw copies as well as
# modified versions may be distributed without limitation.
# This code shows different device settings and their usage. For additional information see the documentation of TDCBase.
try:
import QuTAG
except:
print("Time Tagger wrapper QuTAG.py is not in the search path / same folder.")
import numpy as np
# Initialize device
qutag = QuTAG.QuTAG()
# Get the timebase (the resolution) from the quTAG. It is used as time unit by many other functions.
timebase = qutag.getTimebase()
print("Device timebase:", timebase, "s")
# Read back device parameters: coincidence window in bins (bin width is timebase) and exposuretime in ms
na, coincWin, expTime = qutag.getDeviceParams()
print("Coincidence window",coincWin, "bins, exposure time",expTime, "ms")
# Define the coincidence window in bins of the timebase
qutag.setCoincidenceWindow(20000) # with the timebase 1e-12s -> coincidence window is set to 20ns
# Set the exposure or integration time in milliseconds, range = 0..65535
qutag.setExposureTime(500) # 500ms Counting
# Enable channels, disable the rest
# Selects the channels that contribute to the timestamp output stream.
# 0 enables the start input that doesn't trigger timestamps but may affect timestamps from other channels.
qutag.enableChannels((0,1,2,3,4)) # Enables channel 0,2,3
# Let's configure a channel with threshold voltage and rising or faling edge.
# Configure the channel: 2
# Type of signal conditioning
# LVTTL signals (Trigger at 2V rising edge, termination optional.): SCOND_LVTTL
# NIM signals (Trigger at -0.6V falling edge, termination fixed on.): SCOND_NIM
# Misc signals (Conditioning on, everything optional.): SCOND_MISC
# Rising/falling edge: True/False (rising is default)
# Voltage threshold from -2...3V when signal conditioning is SIGNALCOND_MISC: 1.2V
# For additional information see the documentation of TDCBase.
qutag.setSignalConditioning(2,qutag.SCOND_MISC,False,1.2)
print("Signal Cond.", qutag.getSignalConditioning(2))
# Enable Markers.
# The markers 0-3 are low resolution timestamps triggered over the GPIO port. Marker 4 is a 1ms timer tick.
# If enabled, the markers are included in timestamp protocol files with channel numbers 100-104.
# By default, all markers are activated. The function allows to enable or disable the single marker channels.
qutag.enableMarkers((1,2))
# Get the dead time for input channel 1
# After detecting an event, all subsequent events on the same channel are ignored for this time.
rc = qutag.getDeadTime(1)
print("Dead time channel 1:", rc, "ps")
# Set dead time for a specified input channel
# Channel 1, dead time 200 ps
rc = qutag.setDeadTime(1,200)
# Set Channel Delay Times.
# Different signal runtimes cause relative delay times of the signals at different channels.
# The function allows to configure a delay per channel that will be compensated including the changed sorting of events. If not set, all delays are 0. The compensation is carried out in hardware.
# Here we create an numpy array with channel delays [ps], Range=-100ns ... 100ns.
# The array must have at least 5 elements. Enter 0 for unused channels.
delays = np.zeros(int(8), dtype=np.int32)
delays[1] = 2001
rc = qutag.setChannelDelays(delays)
# Read back Channel Delay Times in an array.
rc = qutag.getChannelDelays()
print("Channel delay", rc)
# Check for data loss.
# Timestamps of events detected by the device can get lost if their rate is too high for the USB interface or if the PC is unable to receive the data in time.
# The TDC recognizes this situation and signals it to the PC (with high priority).
# The function checks if a data loss situation is currently detected or if it has been latched since the last call.
# If you are only interested in the current situation, call the function twice; the first call will delete the latch.
rc = qutag.getDataLost()
print("Data loss", rc)
qutag.deInitialize()
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_7/src/xcpu_cortexa53.h
/******************************************************************************
* Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcpu_cortexa53.h
* @addtogroup cpu_cortexa53_v1_7
* @{
* @details
*
* dummy file
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.4 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
* parameter of cpu_cortexa53 in xparameters.h
******************************************************************************/
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_defs.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* Definitions of commonly used enums that have to match definitions
* that all software layer in the system use.
*********************************************************************/
#ifndef PM_DEFS_H_
#define PM_DEFS_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pmu_global.h"
/*********************************************************************
* Macro definitions
********************************************************************/
/*
* Version number is a 32bit value, like:
* (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
*/
#define PM_VERSION_MAJOR 1U
#define PM_VERSION_MINOR 1U
#define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR)
/*
* Capabilities common for all slave nodes (common capabilities should take
* lower 16 bits, specific capabilities of each slave take higher 16 bits)
*/
#define PM_CAP_ACCESS 0x1U
#define PM_CAP_CONTEXT 0x2U
#define PM_CAP_WAKEUP 0x4U
/* Usage status, returned by PmGetNodeStatus */
#define PM_USAGE_CURRENT_MASTER 0x1U
#define PM_USAGE_OTHER_MASTER 0x2U
#define MAX_LATENCY (~0U)
#define MAX_QOS 100U
/* System shutdown macros */
#define PMF_SHUTDOWN_TYPE_SHUTDOWN 0U
#define PMF_SHUTDOWN_TYPE_RESET 1U
#define PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM 0U
#define PMF_SHUTDOWN_SUBTYPE_PS_ONLY 1U
#define PMF_SHUTDOWN_SUBTYPE_SYSTEM 2U
/* PM API ids */
#define PM_GET_API_VERSION 1U
#define PM_SET_CONFIGURATION 2U
#define PM_GET_NODE_STATUS 3U
#define PM_GET_OP_CHARACTERISTIC 4U
#define PM_REGISTER_NOTIFIER 5U
#define PM_REQUEST_SUSPEND 6U
#define PM_SELF_SUSPEND 7U
#define PM_FORCE_POWERDOWN 8U
#define PM_ABORT_SUSPEND 9U
#define PM_REQUEST_WAKEUP 10U
#define PM_SET_WAKEUP_SOURCE 11U
#define PM_SYSTEM_SHUTDOWN 12U
#define PM_REQUEST_NODE 13U
#define PM_RELEASE_NODE 14U
#define PM_SET_REQUIREMENT 15U
#define PM_SET_MAX_LATENCY 16U
#define PM_RESET_ASSERT 17U
#define PM_RESET_GET_STATUS 18U
#define PM_MMIO_WRITE 19U
#define PM_MMIO_READ 20U
#define PM_INIT_FINALIZE 21U
#define PM_FPGA_LOAD 22U
#define PM_FPGA_GET_STATUS 23U
#define PM_GET_CHIPID 24U
#define PM_SECURE_SHA 26U
#define PM_SECURE_RSA 27U
#define PM_PINCTRL_REQUEST 28U
#define PM_PINCTRL_RELEASE 29U
#define PM_PINCTRL_GET_FUNCTION 30U
#define PM_PINCTRL_SET_FUNCTION 31U
#define PM_PINCTRL_CONFIG_PARAM_GET 32U
#define PM_PINCTRL_CONFIG_PARAM_SET 33U
#define PM_IOCTL 34U
#define PM_QUERY_DATA 35U
#define PM_CLOCK_ENABLE 36U
#define PM_CLOCK_DISABLE 37U
#define PM_CLOCK_GETSTATE 38U
#define PM_CLOCK_SETDIVIDER 39U
#define PM_CLOCK_GETDIVIDER 40U
#define PM_CLOCK_SETRATE 41U
#define PM_CLOCK_GETRATE 42U
#define PM_CLOCK_SETPARENT 43U
#define PM_CLOCK_GETPARENT 44U
#define PM_SECURE_IMAGE 45U
#define PM_FPGA_READ 46U
#define PM_SECURE_AES 47U
#define PM_PLL_SET_PARAM 48U
#define PM_PLL_GET_PARAM 49U
#define PM_PLL_SET_MODE 50U
#define PM_PLL_GET_MODE 51U
#define PM_REGISTER_ACCESS 52U
#define PM_EFUSE_ACCESS 53U
#define PM_API_MIN PM_GET_API_VERSION
#define PM_API_MAX PM_EFUSE_ACCESS
/* PM API callback ids */
#define PM_INIT_SUSPEND_CB 30U
#define PM_ACKNOWLEDGE_CB 31U
#define PM_NOTIFY_CB 32U
#define PM_NOTIFY_STL_NO_OP 33U
/* Nodes */
#define NODE_UNKNOWN 0U
#define NODE_APU 1U
#define NODE_APU_0 2U
#define NODE_APU_1 3U
#define NODE_APU_2 4U
#define NODE_APU_3 5U
#define NODE_RPU 6U
#define NODE_RPU_0 7U
#define NODE_RPU_1 8U
#define NODE_PLD 9U
#define NODE_FPD 10U
#define NODE_OCM_BANK_0 11U
#define NODE_OCM_BANK_1 12U
#define NODE_OCM_BANK_2 13U
#define NODE_OCM_BANK_3 14U
#define NODE_TCM_0_A 15U
#define NODE_TCM_0_B 16U
#define NODE_TCM_1_A 17U
#define NODE_TCM_1_B 18U
#define NODE_L2 19U
#define NODE_GPU_PP_0 20U
#define NODE_GPU_PP_1 21U
#define NODE_USB_0 22U
#define NODE_USB_1 23U
#define NODE_TTC_0 24U
#define NODE_TTC_1 25U
#define NODE_TTC_2 26U
#define NODE_TTC_3 27U
#define NODE_SATA 28U
#define NODE_ETH_0 29U
#define NODE_ETH_1 30U
#define NODE_ETH_2 31U
#define NODE_ETH_3 32U
#define NODE_UART_0 33U
#define NODE_UART_1 34U
#define NODE_SPI_0 35U
#define NODE_SPI_1 36U
#define NODE_I2C_0 37U
#define NODE_I2C_1 38U
#define NODE_SD_0 39U
#define NODE_SD_1 40U
#define NODE_DP 41U
#define NODE_GDMA 42U
#define NODE_ADMA 43U
#define NODE_NAND 44U
#define NODE_QSPI 45U
#define NODE_GPIO 46U
#define NODE_CAN_0 47U
#define NODE_CAN_1 48U
#define NODE_EXTERN 49U
#define NODE_APLL 50U
#define NODE_VPLL 51U
#define NODE_DPLL 52U
#define NODE_RPLL 53U
#define NODE_IOPLL 54U
#define NODE_DDR 55U
#define NODE_IPI_APU 56U
#define NODE_IPI_RPU_0 57U
#define NODE_GPU 58U
#define NODE_PCIE 59U
#define NODE_PCAP 60U
#define NODE_RTC 61U
#define NODE_LPD 62U
#define NODE_VCU 63U
#define NODE_IPI_RPU_1 64U
#define NODE_IPI_PL_0 65U
#define NODE_IPI_PL_1 66U
#define NODE_IPI_PL_2 67U
#define NODE_IPI_PL_3 68U
#define NODE_PL 69U
#define NODE_SWDT_1 72U
#define NODE_MIN NODE_APU
#define NODE_MAX NODE_SWDT_1
/* Request acknowledge argument values */
#define REQUEST_ACK_NO 1U
#define REQUEST_ACK_BLOCKING 2U
#define REQUEST_ACK_NON_BLOCKING 3U
#define REQUEST_ACK_MIN REQUEST_ACK_NO
#define REQUEST_ACK_MAX REQUEST_ACK_NON_BLOCKING
/* Abort reason argument */
#define ABORT_REASON_WKUP_EVENT 100U
#define ABORT_REASON_PU_BUSY 101U
#define ABORT_REASON_NO_PWRDN 102U
#define ABORT_REASON_UNKNOWN 103U
#define ABORT_REASON_MIN ABORT_REASON_WKUP_EVENT
#define ABORT_REASON_MAX ABORT_REASON_UNKNOWN
/* Suspend reason argument */
#define SUSPEND_REASON_PU_REQ 201U
#define SUSPEND_REASON_ALERT 202U
#define SUSPEND_REASON_SYS_SHUTDOWN 203U
#define SUSPEND_REASON_MIN SUSPEND_REASON_PU_REQ
#define SUSPEND_REASON_MAX SUSPEND_REASON_SYS_SHUTDOWN
/* State arguments of the self suspend (master specific) */
#define PM_APU_STATE_CPU_IDLE 0x0U
#define PM_APU_STATE_SUSPEND_TO_RAM 0xFU
/* Operating characteristics type */
#define PM_OPCHAR_TYPE_POWER 1U
#define PM_OPCHAR_TYPE_TEMP 2U
#define PM_OPCHAR_TYPE_LATENCY 3U
/* PM events */
#define EVENT_NONE 0U
#define EVENT_STATE_CHANGE 0x1U
#define EVENT_ZERO_USERS 0x2U
/* Power management specific return error statuses */
#define XST_PM_INTERNAL 2000L
#define XST_PM_CONFLICT 2001L
#define XST_PM_NO_ACCESS 2002L
#define XST_PM_INVALID_NODE 2003L
#define XST_PM_DOUBLE_REQ 2004L
#define XST_PM_ABORT_SUSPEND 2005L
#define XST_PM_TIMEOUT 2006L
#define XST_PM_NODE_USED 2007L
#define XST_PM_MULT_USER 2008L
/* Reset configuration argument */
#define PM_RESET_ACTION_RELEASE 0U
#define PM_RESET_ACTION_ASSERT 1U
#define PM_RESET_ACTION_PULSE 2U
/* Reset lines */
#define PM_RESET_BASE 1000U
#define PM_RESET_PCIE_CFG (PM_RESET_BASE + 0U)
#define PM_RESET_PCIE_BRIDGE (PM_RESET_BASE + 1U)
#define PM_RESET_PCIE_CTRL (PM_RESET_BASE + 2U)
#define PM_RESET_DP (PM_RESET_BASE + 3U)
#define PM_RESET_SWDT_CRF (PM_RESET_BASE + 4U)
#define PM_RESET_AFI_FM5 (PM_RESET_BASE + 5U)
#define PM_RESET_AFI_FM4 (PM_RESET_BASE + 6U)
#define PM_RESET_AFI_FM3 (PM_RESET_BASE + 7U)
#define PM_RESET_AFI_FM2 (PM_RESET_BASE + 8U)
#define PM_RESET_AFI_FM1 (PM_RESET_BASE + 9U)
#define PM_RESET_AFI_FM0 (PM_RESET_BASE + 10U)
#define PM_RESET_GDMA (PM_RESET_BASE + 11U)
#define PM_RESET_GPU_PP1 (PM_RESET_BASE + 12U)
#define PM_RESET_GPU_PP0 (PM_RESET_BASE + 13U)
#define PM_RESET_GPU (PM_RESET_BASE + 14U)
#define PM_RESET_GT (PM_RESET_BASE + 15U)
#define PM_RESET_SATA (PM_RESET_BASE + 16U)
#define PM_RESET_ACPU3_PWRON (PM_RESET_BASE + 17U)
#define PM_RESET_ACPU2_PWRON (PM_RESET_BASE + 18U)
#define PM_RESET_ACPU1_PWRON (PM_RESET_BASE + 19U)
#define PM_RESET_ACPU0_PWRON (PM_RESET_BASE + 20U)
#define PM_RESET_APU_L2 (PM_RESET_BASE + 21U)
#define PM_RESET_ACPU3 (PM_RESET_BASE + 22U)
#define PM_RESET_ACPU2 (PM_RESET_BASE + 23U)
#define PM_RESET_ACPU1 (PM_RESET_BASE + 24U)
#define PM_RESET_ACPU0 (PM_RESET_BASE + 25U)
#define PM_RESET_DDR (PM_RESET_BASE + 26U)
#define PM_RESET_APM_FPD (PM_RESET_BASE + 27U)
#define PM_RESET_SOFT (PM_RESET_BASE + 28U)
#define PM_RESET_GEM0 (PM_RESET_BASE + 29U)
#define PM_RESET_GEM1 (PM_RESET_BASE + 30U)
#define PM_RESET_GEM2 (PM_RESET_BASE + 31U)
#define PM_RESET_GEM3 (PM_RESET_BASE + 32U)
#define PM_RESET_QSPI (PM_RESET_BASE + 33U)
#define PM_RESET_UART0 (PM_RESET_BASE + 34U)
#define PM_RESET_UART1 (PM_RESET_BASE + 35U)
#define PM_RESET_SPI0 (PM_RESET_BASE + 36U)
#define PM_RESET_SPI1 (PM_RESET_BASE + 37U)
#define PM_RESET_SDIO0 (PM_RESET_BASE + 38U)
#define PM_RESET_SDIO1 (PM_RESET_BASE + 39U)
#define PM_RESET_CAN0 (PM_RESET_BASE + 40U)
#define PM_RESET_CAN1 (PM_RESET_BASE + 41U)
#define PM_RESET_I2C0 (PM_RESET_BASE + 42U)
#define PM_RESET_I2C1 (PM_RESET_BASE + 43U)
#define PM_RESET_TTC0 (PM_RESET_BASE + 44U)
#define PM_RESET_TTC1 (PM_RESET_BASE + 45U)
#define PM_RESET_TTC2 (PM_RESET_BASE + 46U)
#define PM_RESET_TTC3 (PM_RESET_BASE + 47U)
#define PM_RESET_SWDT_CRL (PM_RESET_BASE + 48U)
#define PM_RESET_NAND (PM_RESET_BASE + 49U)
#define PM_RESET_ADMA (PM_RESET_BASE + 50U)
#define PM_RESET_GPIO (PM_RESET_BASE + 51U)
#define PM_RESET_IOU_CC (PM_RESET_BASE + 52U)
#define PM_RESET_TIMESTAMP (PM_RESET_BASE + 53U)
#define PM_RESET_RPU_R50 (PM_RESET_BASE + 54U)
#define PM_RESET_RPU_R51 (PM_RESET_BASE + 55U)
#define PM_RESET_RPU_AMBA (PM_RESET_BASE + 56U)
#define PM_RESET_OCM (PM_RESET_BASE + 57U)
#define PM_RESET_RPU_PGE (PM_RESET_BASE + 58U)
#define PM_RESET_USB0_CORERESET (PM_RESET_BASE + 59U)
#define PM_RESET_USB1_CORERESET (PM_RESET_BASE + 60U)
#define PM_RESET_USB0_HIBERRESET (PM_RESET_BASE + 61U)
#define PM_RESET_USB1_HIBERRESET (PM_RESET_BASE + 62U)
#define PM_RESET_USB0_APB (PM_RESET_BASE + 63U)
#define PM_RESET_USB1_APB (PM_RESET_BASE + 64U)
#define PM_RESET_IPI (PM_RESET_BASE + 65U)
#define PM_RESET_APM_LPD (PM_RESET_BASE + 66U)
#define PM_RESET_RTC (PM_RESET_BASE + 67U)
#define PM_RESET_SYSMON (PM_RESET_BASE + 68U)
#define PM_RESET_AFI_FM6 (PM_RESET_BASE + 69U)
#define PM_RESET_LPD_SWDT (PM_RESET_BASE + 70U)
#define PM_RESET_FPD (PM_RESET_BASE + 71U)
#define PM_RESET_RPU_DBG1 (PM_RESET_BASE + 72U)
#define PM_RESET_RPU_DBG0 (PM_RESET_BASE + 73U)
#define PM_RESET_DBG_LPD (PM_RESET_BASE + 74U)
#define PM_RESET_DBG_FPD (PM_RESET_BASE + 75U)
#define PM_RESET_APLL (PM_RESET_BASE + 76U)
#define PM_RESET_DPLL (PM_RESET_BASE + 77U)
#define PM_RESET_VPLL (PM_RESET_BASE + 78U)
#define PM_RESET_IOPLL (PM_RESET_BASE + 79U)
#define PM_RESET_RPLL (PM_RESET_BASE + 80U)
#define PM_RESET_GPO3_PL_0 (PM_RESET_BASE + 81U)
#define PM_RESET_GPO3_PL_1 (PM_RESET_BASE + 82U)
#define PM_RESET_GPO3_PL_2 (PM_RESET_BASE + 83U)
#define PM_RESET_GPO3_PL_3 (PM_RESET_BASE + 84U)
#define PM_RESET_GPO3_PL_4 (PM_RESET_BASE + 85U)
#define PM_RESET_GPO3_PL_5 (PM_RESET_BASE + 86U)
#define PM_RESET_GPO3_PL_6 (PM_RESET_BASE + 87U)
#define PM_RESET_GPO3_PL_7 (PM_RESET_BASE + 88U)
#define PM_RESET_GPO3_PL_8 (PM_RESET_BASE + 89U)
#define PM_RESET_GPO3_PL_9 (PM_RESET_BASE + 90U)
#define PM_RESET_GPO3_PL_10 (PM_RESET_BASE + 91U)
#define PM_RESET_GPO3_PL_11 (PM_RESET_BASE + 92U)
#define PM_RESET_GPO3_PL_12 (PM_RESET_BASE + 93U)
#define PM_RESET_GPO3_PL_13 (PM_RESET_BASE + 94U)
#define PM_RESET_GPO3_PL_14 (PM_RESET_BASE + 95U)
#define PM_RESET_GPO3_PL_15 (PM_RESET_BASE + 96U)
#define PM_RESET_GPO3_PL_16 (PM_RESET_BASE + 97U)
#define PM_RESET_GPO3_PL_17 (PM_RESET_BASE + 98U)
#define PM_RESET_GPO3_PL_18 (PM_RESET_BASE + 99U)
#define PM_RESET_GPO3_PL_19 (PM_RESET_BASE + 100U)
#define PM_RESET_GPO3_PL_20 (PM_RESET_BASE + 101U)
#define PM_RESET_GPO3_PL_21 (PM_RESET_BASE + 102U)
#define PM_RESET_GPO3_PL_22 (PM_RESET_BASE + 103U)
#define PM_RESET_GPO3_PL_23 (PM_RESET_BASE + 104U)
#define PM_RESET_GPO3_PL_24 (PM_RESET_BASE + 105U)
#define PM_RESET_GPO3_PL_25 (PM_RESET_BASE + 106U)
#define PM_RESET_GPO3_PL_26 (PM_RESET_BASE + 107U)
#define PM_RESET_GPO3_PL_27 (PM_RESET_BASE + 108U)
#define PM_RESET_GPO3_PL_28 (PM_RESET_BASE + 109U)
#define PM_RESET_GPO3_PL_29 (PM_RESET_BASE + 110U)
#define PM_RESET_GPO3_PL_30 (PM_RESET_BASE + 111U)
#define PM_RESET_GPO3_PL_31 (PM_RESET_BASE + 112U)
#define PM_RESET_RPU_LS (PM_RESET_BASE + 113U)
#define PM_RESET_PS_ONLY (PM_RESET_BASE + 114U)
#define PM_RESET_PL (PM_RESET_BASE + 115U)
#define PM_RESET_GPIO5_EMIO_92 (PM_RESET_BASE + 116U)
#define PM_RESET_GPIO5_EMIO_93 (PM_RESET_BASE + 117U)
#define PM_RESET_GPIO5_EMIO_94 (PM_RESET_BASE + 118U)
#define PM_RESET_GPIO5_EMIO_95 (PM_RESET_BASE + 119U)
/* Clock IDs */
#define PM_CLOCK_IOPLL 0U
#define PM_CLOCK_RPLL 1U
#define PM_CLOCK_APLL 2U
#define PM_CLOCK_DPLL 3U
#define PM_CLOCK_VPLL 4U
#define PM_CLOCK_IOPLL_TO_FPD 5U
#define PM_CLOCK_RPLL_TO_FPD 6U
#define PM_CLOCK_APLL_TO_LPD 7U
#define PM_CLOCK_DPLL_TO_LPD 8U
#define PM_CLOCK_VPLL_TO_LPD 9U
#define PM_CLOCK_ACPU 10U
#define PM_CLOCK_ACPU_HALF 11U
#define PM_CLOCK_DBG_FPD 12U
#define PM_CLOCK_DBG_LPD 13U
#define PM_CLOCK_DBG_TRACE 14U
#define PM_CLOCK_DBG_TSTMP 15U
#define PM_CLOCK_DP_VIDEO_REF 16U
#define PM_CLOCK_DP_AUDIO_REF 17U
#define PM_CLOCK_DP_STC_REF 18U
#define PM_CLOCK_GDMA_REF 19U
#define PM_CLOCK_DPDMA_REF 20U
#define PM_CLOCK_DDR_REF 21U
#define PM_CLOCK_SATA_REF 22U
#define PM_CLOCK_PCIE_REF 23U
#define PM_CLOCK_GPU_REF 24U
#define PM_CLOCK_GPU_PP0_REF 25U
#define PM_CLOCK_GPU_PP1_REF 26U
#define PM_CLOCK_TOPSW_MAIN 27U
#define PM_CLOCK_TOPSW_LSBUS 28U
#define PM_CLOCK_GTGREF0_REF 29U
#define PM_CLOCK_LPD_SWITCH 30U
#define PM_CLOCK_LPD_LSBUS 31U
#define PM_CLOCK_USB0_BUS_REF 32U
#define PM_CLOCK_USB1_BUS_REF 33U
#define PM_CLOCK_USB3_DUAL_REF 34U
#define PM_CLOCK_USB0 35U
#define PM_CLOCK_USB1 36U
#define PM_CLOCK_CPU_R5 37U
#define PM_CLOCK_CPU_R5_CORE 38U
#define PM_CLOCK_CSU_SPB 39U
#define PM_CLOCK_CSU_PLL 40U
#define PM_CLOCK_PCAP 41U
#define PM_CLOCK_IOU_SWITCH 42U
#define PM_CLOCK_GEM_TSU_REF 43U
#define PM_CLOCK_GEM_TSU 44U
#define PM_CLOCK_GEM0_TX 45U
#define PM_CLOCK_GEM1_TX 46U
#define PM_CLOCK_GEM2_TX 47U
#define PM_CLOCK_GEM3_TX 48U
#define PM_CLOCK_GEM0_RX 49U
#define PM_CLOCK_GEM1_RX 50U
#define PM_CLOCK_GEM2_RX 51U
#define PM_CLOCK_GEM3_RX 52U
#define PM_CLOCK_QSPI_REF 53U
#define PM_CLOCK_SDIO0_REF 54U
#define PM_CLOCK_SDIO1_REF 55U
#define PM_CLOCK_UART0_REF 56U
#define PM_CLOCK_UART1_REF 57U
#define PM_CLOCK_SPI0_REF 58U
#define PM_CLOCK_SPI1_REF 59U
#define PM_CLOCK_NAND_REF 60U
#define PM_CLOCK_I2C0_REF 61U
#define PM_CLOCK_I2C1_REF 62U
#define PM_CLOCK_CAN0_REF 63U
#define PM_CLOCK_CAN1_REF 64U
#define PM_CLOCK_CAN0 65U
#define PM_CLOCK_CAN1 66U
#define PM_CLOCK_DLL_REF 67U
#define PM_CLOCK_ADMA_REF 68U
#define PM_CLOCK_TIMESTAMP_REF 69U
#define PM_CLOCK_AMS_REF 70U
#define PM_CLOCK_PL0_REF 71U
#define PM_CLOCK_PL1_REF 72U
#define PM_CLOCK_PL2_REF 73U
#define PM_CLOCK_PL3_REF 74U
#define PM_CLOCK_WDT 75U
#define PM_CLOCK_IOPLL_INT 76U
#define PM_CLOCK_IOPLL_PRE_SRC 77U
#define PM_CLOCK_IOPLL_HALF 78U
#define PM_CLOCK_IOPLL_INT_MUX 79U
#define PM_CLOCK_IOPLL_POST_SRC 80U
#define PM_CLOCK_RPLL_INT 81U
#define PM_CLOCK_RPLL_PRE_SRC 82U
#define PM_CLOCK_RPLL_HALF 83U
#define PM_CLOCK_RPLL_INT_MUX 84U
#define PM_CLOCK_RPLL_POST_SRC 85U
#define PM_CLOCK_APLL_INT 86U
#define PM_CLOCK_APLL_PRE_SRC 87U
#define PM_CLOCK_APLL_HALF 88U
#define PM_CLOCK_APLL_INT_MUX 89U
#define PM_CLOCK_APLL_POST_SRC 90U
#define PM_CLOCK_DPLL_INT 91U
#define PM_CLOCK_DPLL_PRE_SRC 92U
#define PM_CLOCK_DPLL_HALF 93U
#define PM_CLOCK_DPLL_INT_MUX 94U
#define PM_CLOCK_DPLL_POST_SRC 95U
#define PM_CLOCK_VPLL_INT 96U
#define PM_CLOCK_VPLL_PRE_SRC 97U
#define PM_CLOCK_VPLL_HALF 98U
#define PM_CLOCK_VPLL_INT_MUX 99U
#define PM_CLOCK_VPLL_POST_SRC 100U
#define PM_CLOCK_CAN0_MIO 101U
#define PM_CLOCK_CAN1_MIO 102U
#define PM_CLOCK_ACPU_FULL 103U
#define PM_CLOCK_GEM0_REF 104U
#define PM_CLOCK_GEM1_REF 105U
#define PM_CLOCK_GEM2_REF 106U
#define PM_CLOCK_GEM3_REF 107U
#define PM_CLOCK_GEM0_REF_UNGATED 108U
#define PM_CLOCK_GEM1_REF_UNGATED 109U
#define PM_CLOCK_GEM2_REF_UNGATED 110U
#define PM_CLOCK_GEM3_REF_UNGATED 111U
#define PM_CLOCK_LPD_WDT 112U
#define PM_CLOCK_EXT_BASE 113U
#define PM_CLOCK_EXT_PSS_REF (PM_CLOCK_EXT_BASE + 0U)
#define PM_CLOCK_EXT_VIDEO (PM_CLOCK_EXT_BASE + 1U)
#define PM_CLOCK_EXT_PSS_ALT_REF (PM_CLOCK_EXT_BASE + 2U)
#define PM_CLOCK_EXT_AUX_REF (PM_CLOCK_EXT_BASE + 3U)
#define PM_CLOCK_EXT_GT_CRX_REF (PM_CLOCK_EXT_BASE + 4U)
#define PM_CLOCK_EXT_SWDT0 (PM_CLOCK_EXT_BASE + 5U)
#define PM_CLOCK_EXT_SWDT1 (PM_CLOCK_EXT_BASE + 6U)
#define PM_CLOCK_EXT_GEM0_TX_EMIO (PM_CLOCK_EXT_BASE + 7U)
#define PM_CLOCK_EXT_GEM1_TX_EMIO (PM_CLOCK_EXT_BASE + 8U)
#define PM_CLOCK_EXT_GEM2_TX_EMIO (PM_CLOCK_EXT_BASE + 9U)
#define PM_CLOCK_EXT_GEM3_TX_EMIO (PM_CLOCK_EXT_BASE + 10U)
#define PM_CLOCK_EXT_GEM0_RX_EMIO (PM_CLOCK_EXT_BASE + 11U)
#define PM_CLOCK_EXT_GEM1_RX_EMIO (PM_CLOCK_EXT_BASE + 12U)
#define PM_CLOCK_EXT_GEM2_RX_EMIO (PM_CLOCK_EXT_BASE + 13U)
#define PM_CLOCK_EXT_GEM3_RX_EMIO (PM_CLOCK_EXT_BASE + 14U)
#define PM_CLOCK_EXT_MIO50_OR_MIO51 (PM_CLOCK_EXT_BASE + 15U)
#define PM_CLOCK_EXT_MIO0 (PM_CLOCK_EXT_BASE + 16U)
#define PM_CLOCK_EXT_MIO1 (PM_CLOCK_EXT_BASE + 17U)
#define PM_CLOCK_EXT_MIO2 (PM_CLOCK_EXT_BASE + 18U)
#define PM_CLOCK_EXT_MIO3 (PM_CLOCK_EXT_BASE + 19U)
#define PM_CLOCK_EXT_MIO4 (PM_CLOCK_EXT_BASE + 20U)
#define PM_CLOCK_EXT_MIO5 (PM_CLOCK_EXT_BASE + 21U)
#define PM_CLOCK_EXT_MIO6 (PM_CLOCK_EXT_BASE + 22U)
#define PM_CLOCK_EXT_MIO7 (PM_CLOCK_EXT_BASE + 23U)
#define PM_CLOCK_EXT_MIO8 (PM_CLOCK_EXT_BASE + 24U)
#define PM_CLOCK_EXT_MIO9 (PM_CLOCK_EXT_BASE + 25U)
#define PM_CLOCK_EXT_MIO10 (PM_CLOCK_EXT_BASE + 26U)
#define PM_CLOCK_EXT_MIO11 (PM_CLOCK_EXT_BASE + 27U)
#define PM_CLOCK_EXT_MIO12 (PM_CLOCK_EXT_BASE + 28U)
#define PM_CLOCK_EXT_MIO13 (PM_CLOCK_EXT_BASE + 29U)
#define PM_CLOCK_EXT_MIO14 (PM_CLOCK_EXT_BASE + 30U)
#define PM_CLOCK_EXT_MIO15 (PM_CLOCK_EXT_BASE + 31U)
#define PM_CLOCK_EXT_MIO16 (PM_CLOCK_EXT_BASE + 32U)
#define PM_CLOCK_EXT_MIO17 (PM_CLOCK_EXT_BASE + 33U)
#define PM_CLOCK_EXT_MIO18 (PM_CLOCK_EXT_BASE + 34U)
#define PM_CLOCK_EXT_MIO19 (PM_CLOCK_EXT_BASE + 35U)
#define PM_CLOCK_EXT_MIO20 (PM_CLOCK_EXT_BASE + 36U)
#define PM_CLOCK_EXT_MIO21 (PM_CLOCK_EXT_BASE + 37U)
#define PM_CLOCK_EXT_MIO22 (PM_CLOCK_EXT_BASE + 38U)
#define PM_CLOCK_EXT_MIO23 (PM_CLOCK_EXT_BASE + 39U)
#define PM_CLOCK_EXT_MIO24 (PM_CLOCK_EXT_BASE + 40U)
#define PM_CLOCK_EXT_MIO25 (PM_CLOCK_EXT_BASE + 41U)
#define PM_CLOCK_EXT_MIO26 (PM_CLOCK_EXT_BASE + 42U)
#define PM_CLOCK_EXT_MIO27 (PM_CLOCK_EXT_BASE + 43U)
#define PM_CLOCK_EXT_MIO28 (PM_CLOCK_EXT_BASE + 44U)
#define PM_CLOCK_EXT_MIO29 (PM_CLOCK_EXT_BASE + 45U)
#define PM_CLOCK_EXT_MIO30 (PM_CLOCK_EXT_BASE + 46U)
#define PM_CLOCK_EXT_MIO31 (PM_CLOCK_EXT_BASE + 47U)
#define PM_CLOCK_EXT_MIO32 (PM_CLOCK_EXT_BASE + 48U)
#define PM_CLOCK_EXT_MIO33 (PM_CLOCK_EXT_BASE + 49U)
#define PM_CLOCK_EXT_MIO34 (PM_CLOCK_EXT_BASE + 50U)
#define PM_CLOCK_EXT_MIO35 (PM_CLOCK_EXT_BASE + 51U)
#define PM_CLOCK_EXT_MIO36 (PM_CLOCK_EXT_BASE + 52U)
#define PM_CLOCK_EXT_MIO37 (PM_CLOCK_EXT_BASE + 53U)
#define PM_CLOCK_EXT_MIO38 (PM_CLOCK_EXT_BASE + 54U)
#define PM_CLOCK_EXT_MIO39 (PM_CLOCK_EXT_BASE + 55U)
#define PM_CLOCK_EXT_MIO40 (PM_CLOCK_EXT_BASE + 56U)
#define PM_CLOCK_EXT_MIO41 (PM_CLOCK_EXT_BASE + 57U)
#define PM_CLOCK_EXT_MIO42 (PM_CLOCK_EXT_BASE + 58U)
#define PM_CLOCK_EXT_MIO43 (PM_CLOCK_EXT_BASE + 59U)
#define PM_CLOCK_EXT_MIO44 (PM_CLOCK_EXT_BASE + 60U)
#define PM_CLOCK_EXT_MIO45 (PM_CLOCK_EXT_BASE + 61U)
#define PM_CLOCK_EXT_MIO46 (PM_CLOCK_EXT_BASE + 62U)
#define PM_CLOCK_EXT_MIO47 (PM_CLOCK_EXT_BASE + 63U)
#define PM_CLOCK_EXT_MIO48 (PM_CLOCK_EXT_BASE + 64U)
#define PM_CLOCK_EXT_MIO49 (PM_CLOCK_EXT_BASE + 65U)
#define PM_CLOCK_EXT_MIO50 (PM_CLOCK_EXT_BASE + 66U)
#define PM_CLOCK_EXT_MIO51 (PM_CLOCK_EXT_BASE + 67U)
#define PM_CLOCK_EXT_MIO52 (PM_CLOCK_EXT_BASE + 68U)
#define PM_CLOCK_EXT_MIO53 (PM_CLOCK_EXT_BASE + 69U)
#define PM_CLOCK_EXT_MIO54 (PM_CLOCK_EXT_BASE + 70U)
#define PM_CLOCK_EXT_MIO55 (PM_CLOCK_EXT_BASE + 71U)
#define PM_CLOCK_EXT_MIO56 (PM_CLOCK_EXT_BASE + 72U)
#define PM_CLOCK_EXT_MIO57 (PM_CLOCK_EXT_BASE + 73U)
#define PM_CLOCK_EXT_MIO58 (PM_CLOCK_EXT_BASE + 74U)
#define PM_CLOCK_EXT_MIO59 (PM_CLOCK_EXT_BASE + 75U)
#define PM_CLOCK_EXT_MIO60 (PM_CLOCK_EXT_BASE + 76U)
#define PM_CLOCK_EXT_MIO61 (PM_CLOCK_EXT_BASE + 77U)
#define PM_CLOCK_EXT_MIO62 (PM_CLOCK_EXT_BASE + 78U)
#define PM_CLOCK_EXT_MIO63 (PM_CLOCK_EXT_BASE + 79U)
#define PM_CLOCK_EXT_MIO64 (PM_CLOCK_EXT_BASE + 80U)
#define PM_CLOCK_EXT_MIO65 (PM_CLOCK_EXT_BASE + 81U)
#define PM_CLOCK_EXT_MIO66 (PM_CLOCK_EXT_BASE + 82U)
#define PM_CLOCK_EXT_MIO67 (PM_CLOCK_EXT_BASE + 83U)
#define PM_CLOCK_EXT_MIO68 (PM_CLOCK_EXT_BASE + 84U)
#define PM_CLOCK_EXT_MIO69 (PM_CLOCK_EXT_BASE + 85U)
#define PM_CLOCK_EXT_MIO70 (PM_CLOCK_EXT_BASE + 86U)
#define PM_CLOCK_EXT_MIO71 (PM_CLOCK_EXT_BASE + 87U)
#define PM_CLOCK_EXT_MIO72 (PM_CLOCK_EXT_BASE + 88U)
#define PM_CLOCK_EXT_MIO73 (PM_CLOCK_EXT_BASE + 89U)
#define PM_CLOCK_EXT_MIO74 (PM_CLOCK_EXT_BASE + 90U)
#define PM_CLOCK_EXT_MIO75 (PM_CLOCK_EXT_BASE + 91U)
#define PM_CLOCK_EXT_MIO76 (PM_CLOCK_EXT_BASE + 92U)
#define PM_CLOCK_EXT_MIO77 (PM_CLOCK_EXT_BASE + 93U)
#define PM_CLOCK_DIV0_ID 0U
#define PM_CLOCK_DIV1_ID 1U
/* PLL parameters */
#define PM_PLL_PARAM_DIV2 0U
#define PM_PLL_PARAM_FBDIV 1U
#define PM_PLL_PARAM_DATA 2U
#define PM_PLL_PARAM_PRE_SRC 3U
#define PM_PLL_PARAM_POST_SRC 4U
#define PM_PLL_PARAM_LOCK_DLY 5U
#define PM_PLL_PARAM_LOCK_CNT 6U
#define PM_PLL_PARAM_LFHF 7U
#define PM_PLL_PARAM_CP 8U
#define PM_PLL_PARAM_RES 9U
/* PLL modes */
#define PM_PLL_MODE_RESET 0U
#define PM_PLL_MODE_INTEGER 1U
#define PM_PLL_MODE_FRACTIONAL 2U
/* PIN control function IDs */
#define PINCTRL_FUNC_CAN0 0U
#define PINCTRL_FUNC_CAN1 1U
#define PINCTRL_FUNC_ETHERNET0 2U
#define PINCTRL_FUNC_ETHERNET1 3U
#define PINCTRL_FUNC_ETHERNET2 4U
#define PINCTRL_FUNC_ETHERNET3 5U
#define PINCTRL_FUNC_GEMTSU0 6U
#define PINCTRL_FUNC_GPIO0 7U
#define PINCTRL_FUNC_I2C0 8U
#define PINCTRL_FUNC_I2C1 9U
#define PINCTRL_FUNC_MDIO0 10U
#define PINCTRL_FUNC_MDIO1 11U
#define PINCTRL_FUNC_MDIO2 12U
#define PINCTRL_FUNC_MDIO3 13U
#define PINCTRL_FUNC_QSPI0 14U
#define PINCTRL_FUNC_QSPI_FBCLK 15U
#define PINCTRL_FUNC_QSPI_SS 16U
#define PINCTRL_FUNC_SPI0 17U
#define PINCTRL_FUNC_SPI1 18U
#define PINCTRL_FUNC_SPI0_SS 19U
#define PINCTRL_FUNC_SPI1_SS 20U
#define PINCTRL_FUNC_SDIO0 21U
#define PINCTRL_FUNC_SDIO0_PC 22U
#define PINCTRL_FUNC_SDIO0_CD 23U
#define PINCTRL_FUNC_SDIO0_WP 24U
#define PINCTRL_FUNC_SDIO1 25U
#define PINCTRL_FUNC_SDIO1_PC 26U
#define PINCTRL_FUNC_SDIO1_CD 27U
#define PINCTRL_FUNC_SDIO1_WP 28U
#define PINCTRL_FUNC_NAND0 29U
#define PINCTRL_FUNC_NAND0_CE 30U
#define PINCTRL_FUNC_NAND0_RB 31U
#define PINCTRL_FUNC_NAND0_DQS 32U
#define PINCTRL_FUNC_TTC0_CLK 33U
#define PINCTRL_FUNC_TTC0_WAV 34U
#define PINCTRL_FUNC_TTC1_CLK 35U
#define PINCTRL_FUNC_TTC1_WAV 36U
#define PINCTRL_FUNC_TTC2_CLK 37U
#define PINCTRL_FUNC_TTC2_WAV 38U
#define PINCTRL_FUNC_TTC3_CLK 39U
#define PINCTRL_FUNC_TTC3_WAV 40U
#define PINCTRL_FUNC_UART0 41U
#define PINCTRL_FUNC_UART1 42U
#define PINCTRL_FUNC_USB0 43U
#define PINCTRL_FUNC_USB1 44U
#define PINCTRL_FUNC_SWDT0_CLK 45U
#define PINCTRL_FUNC_SWDT0_RST 46U
#define PINCTRL_FUNC_SWDT1_CLK 47U
#define PINCTRL_FUNC_SWDT1_RST 48U
#define PINCTRL_FUNC_PMU0 49U
#define PINCTRL_FUNC_PCIE0 50U
#define PINCTRL_FUNC_CSU0 51U
#define PINCTRL_FUNC_DPAUX0 52U
#define PINCTRL_FUNC_PJTAG0 53U
#define PINCTRL_FUNC_TRACE0 54U
#define PINCTRL_FUNC_TRACE0_CLK 55U
#define PINCTRL_FUNC_TESTSCAN0 56U
#define MAX_FUNCTION 57U
#define PINCTRL_CONFIG_SLEW_RATE 0U
#define PINCTRL_CONFIG_BIAS_STATUS 1U
#define PINCTRL_CONFIG_PULL_CTRL 2U
#define PINCTRL_CONFIG_SCHMITT_CMOS 3U
#define PINCTRL_CONFIG_DRIVE_STRENGTH 4U
#define PINCTRL_CONFIG_VOLTAGE_STATUS 5U
#ifdef __cplusplus
}
#endif
#endif /* PM_DEFS_H_ */
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/iicps_v3_11/src/xiicps_master.c
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_master.c
* @addtogroup iicps_v3_11
* @{
*
* Handles master mode transfers.
*
* <pre> MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a jz 01/30/10 First release
* 1.00a sdm 09/21/11 Updated the XIicPs_SetupMaster to not check for
* Bus Busy condition when the Hold Bit is set.
* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
* check for transfer completion is added, which indicates
* the completion of current transfer.
* 2.0 hk 03/07/14 Added check for error status in the while loop that
* checks for completion. CR# 762244, 764875.
* 2.1 hk 04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
* Fix for CR# 761060 - provision for repeated start.
* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
* read mode and clear transfer size register.
* Disable NACK to avoid interrupts on each retry.
* 2.3 sk 10/06/14 Fill transmit fifo before address register when sending.
* Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH.
* Repeated start feature removed.
* 3.0 sk 12/06/14 Implemented Repeated start feature.
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
* 02/18/15 Implemented larger data transfer using repeated start
* in Zynq UltraScale MP.
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
* 3.6 ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register
* before slave address. Fix for CR996440.
* 3.8 sd 09/06/18 Enable the Timeout interrupt
* 3.9 sg 03/09/19 Added arbitration lost support in polled transfer
* 3.11 rna 12/20/19 Clear the ISR before enabling interrupts in Send/Receive.
* 12/23/19 Add 10 bit address support for Master/Slave
* 12/24/19 Disable slave monitor with XIICPS_CR_NEA_MASK for 10 bit
* addresses according to the IP spec.
* 3.11 sd 02/06/20 Added clocking support.
* 3.11 rna 02/12/20 Moved static data transfer functions to xiicps_xfer.c file
* 02/18/20 Modified latest code for MISRA-C:2012 Compliance.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xiicps.h"
#include "xiicps_xfer.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************* Variable Definitions *****************************/
/*****************************************************************************/
/**
* @brief
* This function initiates an interrupt-driven send in master mode.
*
* It tries to send the first FIFO-full of data, then lets the interrupt
* handler to handle the rest of the data if there is any.
*
* @param InstancePtr is a pointer to the XIicPs instance.
* @param MsgPtr is the pointer to the send buffer.
* @param ByteCount is the number of bytes to be sent.
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return None.
*
* @note This send routine is for interrupt-driven transfer only.
*
****************************************************************************/
void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr)
{
u32 BaseAddr;
u32 Platform = XGetPlatform_Info();
/*
* Assert validates the input arguments.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsgPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertVoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
BaseAddr = InstancePtr->Config.BaseAddress;
InstancePtr->SendBufferPtr = MsgPtr;
InstancePtr->SendByteCount = ByteCount;
InstancePtr->RecvBufferPtr = NULL;
InstancePtr->IsSend = 1;
#if defined (XCLOCKING)
if (InstancePtr->IsClkEnabled == 0) {
Xil_ClockEnable(InstancePtr->Config.RefClk);
InstancePtr->IsClkEnabled = 1;
}
#endif
/*
* Set repeated start if sending more than FIFO of data.
*/
if (((InstancePtr->IsRepeatedStart) != 0)||
(ByteCount > XIICPS_FIFO_DEPTH)) {
XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
(u32)XIICPS_CR_HOLD_MASK);
}
/*
* Setup as a master sending role.
*/
(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
(void)TransmitFifoFill(InstancePtr);
/*
* Clear the interrupt status register before use it to monitor.
*/
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
XIicPs_EnableInterrupts(BaseAddr,
(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_COMP_MASK |
(u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TO_MASK);
/*
* Do the address transfer to notify the slave.
*/
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
/* Clear the Hold bit in ZYNQ if receive byte count is less than
* the FIFO depth to get the completion interrupt properly.
*/
if ((ByteCount < XIICPS_FIFO_DEPTH) && (Platform == (u32)XPLAT_ZYNQ))
{
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) &
(u32)(~XIICPS_CR_HOLD_MASK));
}
}
/*****************************************************************************/
/**
* @brief
* This function initiates an interrupt-driven receive in master mode.
*
* It sets the transfer size register so the slave can send data to us.
* The rest of the work is managed by interrupt handler.
*
* @param InstancePtr is a pointer to the XIicPs instance.
* @param MsgPtr is the pointer to the receive buffer.
* @param ByteCount is the number of bytes to be received.
* @param SlaveAddr is the address of the slave we are receiving from.
*
* @return None.
*
* @note This receive routine is for interrupt-driven transfer only.
*
****************************************************************************/
void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr)
{
u32 BaseAddr;
/*
* Assert validates the input arguments.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsgPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertVoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
BaseAddr = InstancePtr->Config.BaseAddress;
InstancePtr->RecvBufferPtr = MsgPtr;
InstancePtr->RecvByteCount = ByteCount;
InstancePtr->SendBufferPtr = NULL;
InstancePtr->IsSend = 0;
#if defined (XCLOCKING)
if (InstancePtr->IsClkEnabled == 0) {
Xil_ClockEnable(InstancePtr->Config.RefClk);
InstancePtr->IsClkEnabled = 1;
}
#endif
if ((ByteCount > XIICPS_FIFO_DEPTH) ||
((InstancePtr->IsRepeatedStart) !=0))
{
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
(u32)XIICPS_CR_HOLD_MASK);
}
/*
* Initialize for a master receiving role.
*/
(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
/*
* Setup the transfer size register so the slave knows how much
* to send to us.
*/
if (ByteCount > (s32)XIICPS_MAX_TRANSFER_SIZE) {
XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
XIICPS_MAX_TRANSFER_SIZE);
InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
InstancePtr->UpdateTxSize = 1;
}else {
InstancePtr->CurrByteCount = ByteCount;
XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
(u32)ByteCount);
InstancePtr->UpdateTxSize = 0;
}
/*
* Clear the interrupt status register before use it to monitor.
*/
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
XIicPs_EnableInterrupts(BaseAddr,
(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
(u32)XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_TO_MASK);
/*
* Do the address transfer to signal the slave.
*/
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
}
/*****************************************************************************/
/**
* @brief
* This function initiates a polled mode send in master mode.
*
* It sends data to the FIFO and waits for the slave to pick them up.
* If master fails to send data due arbitration lost, will stop transfer
* and with arbitration lost status
* If slave fails to remove data from FIFO, the send fails with
* time out.
*
* @param InstancePtr is a pointer to the XIicPs instance.
* @param MsgPtr is the pointer to the send buffer.
* @param ByteCount is the number of bytes to be sent.
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return
* - XST_SUCCESS if everything went well.
* - XST_FAILURE if timed out.
* - XST_IIC_ARB_LOST if arbitration lost
*
* @note This send routine is for polled mode transfer only.
*
****************************************************************************/
s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
s32 ByteCount, u16 SlaveAddr)
{
u32 IntrStatusReg;
u32 StatusReg;
u32 BaseAddr;
u32 Intrs;
s32 Status;
_Bool Value;
/*
* Assert validates the input arguments.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(MsgPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
#if defined (XCLOCKING)
if (InstancePtr->IsClkEnabled == 0) {
Xil_ClockEnable(InstancePtr->Config.RefClk);
InstancePtr->IsClkEnabled = 1;
}
#endif
BaseAddr = InstancePtr->Config.BaseAddress;
InstancePtr->SendBufferPtr = MsgPtr;
InstancePtr->SendByteCount = ByteCount;
if (((InstancePtr->IsRepeatedStart) != 0) ||
(ByteCount > XIICPS_FIFO_DEPTH)) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
(u32)XIICPS_CR_HOLD_MASK);
}
(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
/*
* Intrs keeps all the error-related interrupts.
*/
Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TX_OVR_MASK |
(u32)XIICPS_IXR_NACK_MASK;
/*
* Clear the interrupt status register before use it to monitor.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
/*
* Transmit first FIFO full of data.
*/
(void)TransmitFifoFill(InstancePtr);
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
/*
* Continue sending as long as there is more data and
* there are no errors.
*/
Value = ((InstancePtr->SendByteCount > (s32)0) &&
((IntrStatusReg & Intrs) == (u32)0U));
while (Value != FALSE) {
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
/*
* Wait until transmit FIFO is empty.
*/
if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0U) {
IntrStatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_ISR_OFFSET);
Value = ((InstancePtr->SendByteCount > (s32)0) &&
((IntrStatusReg & Intrs) == (u32)0U));
continue;
}
/*
* Send more data out through transmit FIFO.
*/
(void)TransmitFifoFill(InstancePtr);
Value = ((InstancePtr->SendByteCount > (s32)0) &&
((IntrStatusReg & Intrs) == (u32)0U));
}
/*
* Check for completion of transfer.
*/
while ((IntrStatusReg & XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK){
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
/*
* If there is an error, tell the caller.
*/
if ((IntrStatusReg & Intrs) != 0U) {
break;
}
}
if (InstancePtr->IsRepeatedStart == 0) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
(~XIICPS_CR_HOLD_MASK));
}
if ((IntrStatusReg & Intrs) != 0U) {
if ((IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK) != 0U) {
Status = (s32) XST_IIC_ARB_LOST;
} else {
Status = (s32)XST_FAILURE;
}
} else {
Status = (s32)XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function initiates a polled mode receive in master mode.
*
* It repeatedly sets the transfer size register so the slave can
* send data to us. It polls the data register for data to come in.
* If master fails to read data due arbitration lost, will return
* with arbitration lost status.
* If slave fails to send us data, it fails with time out.
*
* @param InstancePtr is a pointer to the XIicPs instance.
* @param MsgPtr is the pointer to the receive buffer.
* @param ByteCount is the number of bytes to be received.
* @param SlaveAddr is the address of the slave we are receiving from.
*
* @return
* - XST_SUCCESS if everything went well.
* - XST_FAILURE if timed out.
* - XST_IIC_ARB_LOST if arbitration lost
*
* @note This receive routine is for polled mode transfer only.
*
****************************************************************************/
s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
s32 ByteCount, u16 SlaveAddr)
{
u32 IntrStatusReg;
u32 Intrs;
u32 BaseAddr;
s32 Result;
s32 IsHold;
s32 UpdateTxSize = 0;
s32 ByteCountVar = ByteCount;
u32 Platform;
/*
* Assert validates the input arguments.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(MsgPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
BaseAddr = InstancePtr->Config.BaseAddress;
InstancePtr->RecvBufferPtr = MsgPtr;
InstancePtr->RecvByteCount = ByteCountVar;
#if defined (XCLOCKING)
if (InstancePtr->IsClkEnabled == 0) {
Xil_ClockEnable(InstancePtr->Config.RefClk);
InstancePtr->IsClkEnabled = 1;
}
#endif
Platform = XGetPlatform_Info();
if((ByteCountVar > XIICPS_FIFO_DEPTH) ||
((InstancePtr->IsRepeatedStart) !=0))
{
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
(u32)XIICPS_CR_HOLD_MASK);
IsHold = 1;
} else {
IsHold = 0;
}
(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
/*
* Clear the interrupt status register before use it to monitor.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
/*
* Set up the transfer size register so the slave knows how much
* to send to us.
*/
if (ByteCountVar > (s32)XIICPS_MAX_TRANSFER_SIZE) {
XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
XIICPS_MAX_TRANSFER_SIZE);
ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
UpdateTxSize = 1;
}else {
XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
ByteCountVar);
}
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
/*
* Intrs keeps all the error-related interrupts.
*/
Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_RX_OVR_MASK |
(u32)XIICPS_IXR_RX_UNF_MASK | (u32)XIICPS_IXR_NACK_MASK;
/*
* Poll the interrupt status register to find the errors.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
while ((InstancePtr->RecvByteCount > 0) &&
((IntrStatusReg & Intrs) == 0U)) {
while ((XIicPs_RxDataValid(InstancePtr)) != 0U) {
if ((InstancePtr->RecvByteCount <
XIICPS_DATA_INTR_DEPTH) && (IsHold != 0) &&
(InstancePtr->IsRepeatedStart == 0) &&
(UpdateTxSize == 0)) {
IsHold = 0;
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr,
XIICPS_CR_OFFSET) &
(~XIICPS_CR_HOLD_MASK));
}
XIicPs_RecvByte(InstancePtr);
ByteCountVar --;
if (Platform == (u32)XPLAT_ZYNQ) {
if ((UpdateTxSize != 0) &&
(ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
break;
}
}
}
if (Platform == (u32)XPLAT_ZYNQ) {
if ((UpdateTxSize != 0) &&
(ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
/* wait while fifo is full */
while (XIicPs_RxFIFOFull(InstancePtr, ByteCountVar) != 0U) { ;
}
if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
(s32)XIICPS_MAX_TRANSFER_SIZE) {
XIicPs_WriteReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET,
XIICPS_MAX_TRANSFER_SIZE);
ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE +
XIICPS_FIFO_DEPTH;
} else {
XIicPs_WriteReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET,
InstancePtr->RecvByteCount -
XIICPS_FIFO_DEPTH);
UpdateTxSize = 0;
ByteCountVar = InstancePtr->RecvByteCount;
}
}
} else {
if ((InstancePtr->RecvByteCount > 0) && (ByteCountVar == 0)) {
/*
* Clear the interrupt status register before use it to
* monitor.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
if ((InstancePtr->RecvByteCount) >
(s32)XIICPS_MAX_TRANSFER_SIZE) {
XIicPs_WriteReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET,
XIICPS_MAX_TRANSFER_SIZE);
ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
} else {
XIicPs_WriteReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET,
InstancePtr->RecvByteCount);
UpdateTxSize = 0;
ByteCountVar = InstancePtr->RecvByteCount;
}
}
}
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
}
if (InstancePtr->IsRepeatedStart == 0) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
(~XIICPS_CR_HOLD_MASK));
}
if ((IntrStatusReg & Intrs) != 0U) {
if ((IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK) != 0U) {
Result = (s32) XST_IIC_ARB_LOST;
} else {
Result = (s32)XST_FAILURE;
}
} else {
Result = (s32)XST_SUCCESS;
}
return Result;
}
/*****************************************************************************/
/**
* @brief
* This function enables the slave monitor mode.
*
* It enables slave monitor in the control register and enables
* slave ready interrupt. It then does an address transfer to slave.
* Interrupt handler will signal the caller if slave responds to
* the address transfer.
*
* @param InstancePtr is a pointer to the XIicPs instance.
* @param SlaveAddr is the address of the slave we want to contact.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
{
u32 BaseAddr;
u32 ConfigReg;
Xil_AssertVoid(InstancePtr != NULL);
BaseAddr = InstancePtr->Config.BaseAddress;
#if defined (XCLOCKING)
if (InstancePtr->IsClkEnabled == 0) {
Xil_ClockEnable(InstancePtr->Config.RefClk);
InstancePtr->IsClkEnabled = 1;
}
#endif
/* Clear transfer size register */
XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
/*
* Enable slave monitor mode in control register.
*/
ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
(u32)XIICPS_CR_SLVMON_MASK;
ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
/*
* Check if 10 bit address option is set.
*/
if (InstancePtr->Is10BitAddr == 1) {
ConfigReg &= (u32)(~XIICPS_CR_NEA_MASK);
} else {
ConfigReg |= (u32)(XIICPS_CR_NEA_MASK);
}
XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
/*
* Set up interrupt flag for slave monitor interrupt.
* Don't enable NACK.
*/
XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
/*
* Initialize the slave monitor register.
*/
XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
/*
* Set the slave address to start the slave address transmission.
*/
XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
return;
}
/*****************************************************************************/
/**
* @brief
* This function disables slave monitor mode.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
{
u32 BaseAddr;
u32 ControlReg;
Xil_AssertVoid(InstancePtr != NULL);
BaseAddr = InstancePtr->Config.BaseAddress;
/*
* Read the control register, check the NEA bit.
* If 10 bit address mode is enabled, it has to be
* cleared to make the controller go from slave monitor
* mode into normal mode according to the IP document.
*/
ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
if (((ControlReg) & (XIICPS_CR_NEA_MASK)) == 0U) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
ControlReg | (XIICPS_CR_NEA_MASK));
}
/*
* Clear slave monitor control bit.
*/
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
& (~XIICPS_CR_SLVMON_MASK));
/*
* wait for slv monitor control bit to be clear
*/
while ((XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
& XIICPS_CR_SLVMON_MASK) != 0U) {
;
}
/*
* Write back the previous value of NEA bit in control register,
* in case it is modified above.
*/
if (((ControlReg) & (XIICPS_CR_NEA_MASK)) == 0U) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
& (~XIICPS_CR_NEA_MASK));
}
/*
* Clear interrupt flag for slave monitor interrupt.
*/
XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
#if defined (XCLOCKING)
if (InstancePtr->IsClkEnabled == 1) {
Xil_ClockDisable(InstancePtr->Config.RefClk);
InstancePtr->IsClkEnabled = 0;
}
#endif
return;
}
/*****************************************************************************/
/**
* The interrupt handler for the master mode. It does the protocol handling for
* the interrupt-driven transfers.
*
* Completion events and errors are signaled to upper layer for proper handling.
*
* <pre>
* The interrupts that are handled are:
* - DATA
* This case is handled only for master receive data.
* The master has to request for more data (if there is more data to
* receive) and read the data from the FIFO .
*
* - COMP
* If the Master is transmitting data and there is more data to be
* sent then the data is written to the FIFO. If there is no more data to
* be transmitted then a completion event is signalled to the upper layer
* by calling the callback handler.
*
* If the Master is receiving data then the data is read from the FIFO and
* the Master has to request for more data (if there is more data to
* receive). If all the data has been received then a completion event
* is signalled to the upper layer by calling the callback handler.
* It is an error if the amount of received data is more than expected.
*
* - NAK and SLAVE_RDY
* This is signalled to the upper layer by calling the callback handler.
*
* - All Other interrupts
* These interrupts are marked as error. This is signalled to the upper
* layer by calling the callback handler.
*
* </pre>
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
{
u32 IntrStatusReg;
u32 StatusEvent = 0U;
u32 BaseAddr;
u16 SlaveAddr;
s32 ByteCnt;
s32 IsHold;
u32 Platform;
/*
* Assert validates the input arguments.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
BaseAddr = InstancePtr->Config.BaseAddress;
Platform = XGetPlatform_Info();
/*
* Read the Interrupt status register.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr,
(u32)XIICPS_ISR_OFFSET);
/*
* Write the status back to clear the interrupts so no events are
* missed while processing this interrupt.
*/
XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg);
/*
* Use the Mask register AND with the Interrupt Status register so
* disabled interrupts are not processed.
*/
IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET));
ByteCnt = InstancePtr->CurrByteCount;
IsHold = 0;
if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) {
IsHold = 1;
}
/*
* Send
*/
if (((InstancePtr->IsSend) != 0) &&
((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) {
if (InstancePtr->SendByteCount > 0) {
MasterSendData(InstancePtr);
} else {
StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
}
}
/*
* Receive
*/
if ((InstancePtr->IsSend == 0) &&
((0U != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) ||
(0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){
while ((XIicPs_RxDataValid(InstancePtr)) != 0U) {
if ((InstancePtr->RecvByteCount <
XIICPS_DATA_INTR_DEPTH) && (IsHold != 0) &&
(InstancePtr->IsRepeatedStart == 0) &&
(InstancePtr->UpdateTxSize == 0)) {
IsHold = 0;
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr,
XIICPS_CR_OFFSET) &
(~XIICPS_CR_HOLD_MASK));
}
XIicPs_RecvByte(InstancePtr);
ByteCnt--;
if (Platform == (u32)XPLAT_ZYNQ) {
if ((InstancePtr->UpdateTxSize != 0) &&
(ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
break;
}
}
}
if (Platform == (u32)XPLAT_ZYNQ) {
if ((InstancePtr->UpdateTxSize != 0) &&
(ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
/* wait while fifo is full */
while (XIicPs_RxFIFOFull(InstancePtr, ByteCnt) != 0U) { ;
}
if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
(s32)XIICPS_MAX_TRANSFER_SIZE) {
XIicPs_WriteReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET,
XIICPS_MAX_TRANSFER_SIZE);
ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE +
XIICPS_FIFO_DEPTH;
} else {
XIicPs_WriteReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET,
InstancePtr->RecvByteCount -
XIICPS_FIFO_DEPTH);
InstancePtr->UpdateTxSize = 0;
ByteCnt = InstancePtr->RecvByteCount;
}
}
} else {
if ((InstancePtr->RecvByteCount > 0) && (ByteCnt == 0)) {
/*
* Clear the interrupt status register before use it to
* monitor.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
if ((InstancePtr->RecvByteCount) >
(s32)XIICPS_MAX_TRANSFER_SIZE) {
XIicPs_WriteReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET,
XIICPS_MAX_TRANSFER_SIZE);
ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE;
} else {
XIicPs_WriteReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET,
InstancePtr->RecvByteCount);
InstancePtr->UpdateTxSize = 0;
ByteCnt = InstancePtr->RecvByteCount;
}
XIicPs_EnableInterrupts(BaseAddr,
(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
(u32)XIICPS_IXR_ARB_LOST_MASK);
}
}
InstancePtr->CurrByteCount = ByteCnt;
}
if ((InstancePtr->IsSend == 0) &&
(0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
/*
* If all done, tell the application.
*/
if (InstancePtr->RecvByteCount == 0){
if (InstancePtr->IsRepeatedStart == 0) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr,
XIICPS_CR_OFFSET) &
(~XIICPS_CR_HOLD_MASK));
}
StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
}
}
/*
* Slave ready interrupt, it is only meaningful for master mode.
*/
if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
}
if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
if (InstancePtr->IsRepeatedStart == 0) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr,
XIICPS_CR_OFFSET) &
(~XIICPS_CR_HOLD_MASK));
}
StatusEvent |= XIICPS_EVENT_NACK;
}
/*
* Arbitration lost interrupt
*/
if (0U != (IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK)) {
StatusEvent |= XIICPS_EVENT_ARB_LOST;
}
if (0U != (IntrStatusReg & XIICPS_IXR_TO_MASK)) {
XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_TO_MASK);
StatusEvent |= XIICPS_EVENT_TIME_OUT;
}
/*
* All other interrupts are treated as error.
*/
if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK |
XIICPS_IXR_RX_OVR_MASK))) {
if (InstancePtr->IsRepeatedStart == 0) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr,
XIICPS_CR_OFFSET) &
(~XIICPS_CR_HOLD_MASK));
}
StatusEvent |= XIICPS_EVENT_ERROR;
}
/*
* Signal application if there are any events.
*/
if (StatusEvent != 0U) {
InstancePtr->StatusHandler(InstancePtr->CallBackRef,
StatusEvent);
}
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_gic_proxy.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
#include "pm_gic_proxy.h"
#include "pm_slave.h"
#include "lpd_slcr.h"
#include "pm_periph.h"
#include "pm_master.h"
/* GIC Proxy base address */
#define GIC_PROXY_BASE_ADDR LPD_SLCR_GICP0_IRQ_STATUS
#define GIC_PROXY_GROUP_OFFSET(g) (0x14U * (g))
/* GIC Proxy register offsets */
#define GIC_PROXY_IRQ_STATUS_OFFSET 0x0U
#define GIC_PROXY_IRQ_ENABLE_OFFSET 0x8U
#define GIC_PROXY_IRQ_DISABLE_OFFSET 0xCU
#define PM_GIC_PROXY_IS_ENABLED 0x1U
/**
* PmWakeEventGicProxySet() - Set GIC Proxy wake event as the wake source
* @wake Wake event
* @ipiMask IPI mask of the master which sets the wake source
* @enable Flag: for enable non-zero value, for disable value zero
*/
static void PmWakeEventGicProxySet(PmWakeEvent* const wake, const u32 ipiMask,
const u32 enable)
{
PmWakeEventGicProxy* gicWake = (PmWakeEventGicProxy*)wake->derived;
/* Only APU's interrupts are routed through GIC Proxy */
if (ipiMask != pmMasterApu_g.ipiMask) {
goto done;
}
if (0U == enable) {
pmGicProxy.groups[gicWake->group].setMask &= ~gicWake->mask;
} else {
u32 addr = GIC_PROXY_BASE_ADDR +
GIC_PROXY_GROUP_OFFSET(gicWake->group) +
GIC_PROXY_IRQ_STATUS_OFFSET;
/* Write 1 into status register to clear interrupt */
XPfw_Write32(addr, gicWake->mask);
/* Remember which interrupt in the group needs to be enabled */
pmGicProxy.groups[gicWake->group].setMask |= gicWake->mask;
}
done:
return;
}
/**
* PmGicProxyEnable() - Enable all interrupts that are requested
*/
static void PmGicProxyEnable(void)
{
u32 g;
/* Always enable APU's IPI as the wake-up source (callback wake-up) */
PmWakeEventGicProxySet(pmSlaveIpiApu_g.wake, pmMasterApu_g.ipiMask, 1U);
for (g = 0U; g < pmGicProxy.groupsCnt; g++) {
u32 addr = GIC_PROXY_BASE_ADDR +
GIC_PROXY_GROUP_OFFSET(g) +
GIC_PROXY_IRQ_ENABLE_OFFSET;
/* Clear GIC Proxy group interrupt */
XPfw_Write32(LPD_SLCR_GICP_PMU_IRQ_STATUS, 1U << g);
/* Enable GIC Proxy group interrupt */
XPfw_Write32(LPD_SLCR_GICP_PMU_IRQ_ENABLE, 1U << g);
/* Enable interrupts in the group that are set as wake */
XPfw_Write32(addr, pmGicProxy.groups[g].setMask);
}
/* Enable GPI1 FPD GIC Proxy wake event */
ENABLE_WAKE(PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_MASK);
pmGicProxy.flags |= PM_GIC_PROXY_IS_ENABLED;
}
/**
* PmGicProxyDisable() - Disable all interrupts in the GIC Proxy
*/
static void PmGicProxyDisable(void)
{
u32 g;
for (g = 0U; g < pmGicProxy.groupsCnt; g++) {
u32 disableAddr = GIC_PROXY_BASE_ADDR +
GIC_PROXY_GROUP_OFFSET(g) +
GIC_PROXY_IRQ_DISABLE_OFFSET;
u32 statusAddr = GIC_PROXY_BASE_ADDR +
GIC_PROXY_GROUP_OFFSET(g) +
GIC_PROXY_IRQ_STATUS_OFFSET;
/* Clear all interrupts in the GIC Proxy group */
XPfw_Write32(statusAddr, ~0U);
/* Disable all interrupts in the GIC Proxy group */
XPfw_Write32(disableAddr, ~0U);
/* Disable GIC Proxy group interrupt */
XPfw_Write32(LPD_SLCR_GICP_PMU_IRQ_DISABLE, 1U << g);
}
/* Disable FPD GPI1 wake event */
DISABLE_WAKE(PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_MASK);
pmGicProxy.flags &= ~PM_GIC_PROXY_IS_ENABLED;
}
/**
* PmGicProxyClear() - Clear wake-up sources
*/
static void PmGicProxyClear(void)
{
u32 g;
for (g = 0U; g < pmGicProxy.groupsCnt; g++) {
pmGicProxy.groups[g].setMask = 0U;
}
if (0U != (pmGicProxy.flags & PM_GIC_PROXY_IS_ENABLED)) {
PmGicProxyDisable();
}
}
/* FPD GIC Proxy has interrupts organized in 5 groups */
static PmGicProxyGroup pmGicProxyGroups[5];
PmGicProxy pmGicProxy = {
.groups = pmGicProxyGroups,
.groupsCnt = ARRAY_SIZE(pmGicProxyGroups),
.clear = PmGicProxyClear,
.enable = PmGicProxyEnable,
.flags = 0U,
};
/*
* This event class doesn't have config method because the wake events are not
* individually controlled. Instead, all GIC Proxy events are enabled when FPD
* gets powered down and disabled when APU wakes, using the PmGicProxy methods.
*/
PmWakeEventClass pmWakeEventClassGicProxy_g = {
.set = PmWakeEventGicProxySet,
.config = NULL,
};
#endif
<file_sep>/c_drivers/drivers_old_pre_gpio_debug/gpio.h
#ifndef _GPIO_H_
#define _GPIO_H_
#include "xgpiops.h"
uint8_t gpio_init();
void gpio_set_pin(u8 pin_num, u8 value);
void gpio_reset_pulse_gen();
void gpio_send_commnd(uint32_t command);
#endif
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/usbpsu_v1_7/src/xusbpsu_endpoint.c
/******************************************************************************
* Copyright (C) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_endpoint.c
* @addtogroup usbpsu_v1_7
* @{
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 sg 06/06/16 First release
* 1.3 vak 04/03/17 Added CCI support for USB
* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code
* for all USB IPs
* myk 12/01/18 Added hibernation support for device mode
* 1.4 vak 30/05/18 Removed xusb_wrapper files
* 1.6 pm 22/07/19 Removed coverity warnings
* pm 28/08/19 Removed 80-character warnings
* 1.7 pm 23/03/20 Restructured the code for more readability and modularity
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files *********************************/
#include "xusbpsu_endpoint.h"
#include "xusbpsu_local.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
* Returns Transfer Index assigned by Core for an Endpoint transfer.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEpNum is USB endpoint number.
* @param Dir is direction of endpoint
* - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT
*
* @return Transfer Resource Index.
*
* @note None.
*
*****************************************************************************/
u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
u8 Dir)
{
u8 PhyEpNum;
u32 ResourceIndex;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
(Dir == XUSBPSU_EP_DIR_OUT));
PhyEpNum = (u8)XUSBPSU_PhysicalEp(UsbEpNum, Dir);
ResourceIndex = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum));
return (u32)XUSBPSU_DEPCMD_GET_RSC_IDX(ResourceIndex);
}
/****************************************************************************/
/**
* Sends Start New Configuration command to Endpoint.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEpNum is USB endpoint number.
* @param Dir is direction of endpoint
* - XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
*
* @return XST_SUCCESS else XST_FAILURE.
*
* @note
* As per data book this command should be issued by software
* under these conditions:
* 1. After power-on-reset with XferRscIdx=0 before starting
* to configure Physical Endpoints 0 and 1.
* 2. With XferRscIdx=2 before starting to configure
* Physical Endpoints > 1
* 3. This command should always be issued to
* Endpoint 0 (DEPCMD0).
*
*****************************************************************************/
s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir)
{
struct XUsbPsu_EpParams *Params;
u32 Cmd;
u8 PhyEpNum;
PhyEpNum = (u8)XUSBPSU_PhysicalEp(UsbEpNum, (u32)Dir);
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertNonvoid(Params != NULL);
if (PhyEpNum != 1U) {
Cmd = XUSBPSU_DEPCMD_DEPSTARTCFG;
/* XferRscIdx == 0 for EP0 and 2 for the remaining */
if (PhyEpNum > 1U) {
if (InstancePtr->IsConfigDone != 0U) {
return XST_SUCCESS;
}
InstancePtr->IsConfigDone = 1U;
Cmd |= XUSBPSU_DEPCMD_PARAM(2U);
}
return XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
Cmd, Params);
}
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* Sends Set Endpoint Configuration command to Endpoint.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEpNum is USB endpoint number.
* @param Dir is direction of endpoint
* -XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
* @param Size is size of Endpoint size.
* @param Type is Endpoint type Control/Bulk/Interrupt/Isoc.
* @param Restore should be true if saved state should be restored;
* typically this would be false
*
* @return XST_SUCCESS else XST_FAILURE.
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
u16 Size, u8 Type, u8 Restore)
{
struct XUsbPsu_Ep *Ept;
struct XUsbPsu_EpParams *Params;
u8 PhyEpNum;
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertNonvoid(Params != NULL);
PhyEpNum = XUSBPSU_PhysicalEp(UsbEpNum, Dir);
Ept = &InstancePtr->eps[PhyEpNum];
Params->Param0 = XUSBPSU_DEPCFG_EP_TYPE(Type)
| XUSBPSU_DEPCFG_MAX_PACKET_SIZE(Size);
/*
* Set burst size to 1 as recommended
*/
if (InstancePtr->AppData->Speed == XUSBPSU_SPEED_SUPER) {
Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1U);
}
Params->Param1 = XUSBPSU_DEPCFG_XFER_COMPLETE_EN
| XUSBPSU_DEPCFG_XFER_NOT_READY_EN;
if (Restore == TRUE) {
Params->Param0 |= XUSBPSU_DEPCFG_ACTION_RESTORE;
Params->Param2 = Ept->EpSavedState;
}
/*
* We are doing 1:1 mapping for endpoints, meaning
* Physical Endpoints 2 maps to Logical Endpoint 2 and
* so on. We consider the direction bit as part of the physical
* endpoint number. So USB endpoint 0x81 is 0x03.
*/
Params->Param1 |= XUSBPSU_DEPCFG_EP_NUMBER(PhyEpNum);
if (Dir != XUSBPSU_EP_DIR_OUT) {
Params->Param0 |= XUSBPSU_DEPCFG_FIFO_NUMBER((u32)PhyEpNum >>
1U);
}
if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) {
Params->Param1 |= XUSBPSU_DEPCFG_BINTERVAL_M1(Ept->Interval -
1U);
Params->Param1 |= XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN;
}
return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
XUSBPSU_DEPCMD_SETEPCONFIG,
Params);
}
/****************************************************************************/
/**
* Sends Set Transfer Resource command to Endpoint.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEpNum is USB endpoint number.
* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT
*
*
* @return XST_SUCCESS else XST_FAILURE.
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
{
struct XUsbPsu_EpParams *Params;
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertNonvoid(Params != NULL);
Params->Param0 = XUSBPSU_DEPXFERCFG_NUM_XFER_RES(1U);
return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
XUSBPSU_DEPCMD_SETTRANSFRESOURCE,
Params);
}
/****************************************************************************/
/**
* Stops any active transfer.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_StopActiveTransfers(struct XUsbPsu *InstancePtr)
{
u32 Epnum;
for (Epnum = 2U; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) {
struct XUsbPsu_Ep *Ept;
Ept = &InstancePtr->eps[Epnum];
if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
continue;
}
XUsbPsu_StopTransfer(InstancePtr, Ept->UsbEpNum,
Ept->Direction, TRUE);
}
}
/****************************************************************************/
/**
* Clears stall on all stalled Eps.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_ClearStallAllEp(struct XUsbPsu *InstancePtr)
{
u32 Epnum;
for (Epnum = 1U; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) {
struct XUsbPsu_Ep *Ept;
Ept = &InstancePtr->eps[Epnum];
if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
continue;
}
if ((Ept->EpStatus & XUSBPSU_EP_STALL) == (u32)0U) {
continue;
}
XUsbPsu_EpClearStall(InstancePtr, Ept->UsbEpNum,
Ept->Direction);
}
}
#ifdef XUSBPSU_HIBERNATION_ENABLE
/*****************************************************************************/
/**
* Restarts non EP0 endpoints
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
*
* @return XST_SUCCESS on success or else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
s32 XUsbPsu_RestoreEps(struct XUsbPsu *InstancePtr)
{
struct XUsbPsu_Ep *Ept;
s32 Ret;
u8 EpNum;
for (EpNum = 2U; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) {
Ept = &InstancePtr->eps[EpNum];
if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
continue;
}
Ret = XUsbPsu_EpEnable(InstancePtr, Ept->UsbEpNum,
Ept->Direction, Ept->MaxSize, Ept->Type, TRUE);
if (Ret == XST_FAILURE) {
xil_printf("Failed to enable EP %d on wakeup: %d\r\n",
EpNum, Ret);
return (s32)XST_FAILURE;
}
}
for (EpNum = 2U; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) {
Ept = &InstancePtr->eps[EpNum];
if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
continue;
}
if ((Ept->EpStatus & XUSBPSU_EP_STALL) != (u32)0U) {
XUsbPsu_EpSetStall(InstancePtr, Ept->UsbEpNum,
Ept->Direction);
} else {
Ret = XUsbPsu_RestartEp(InstancePtr, Ept->PhyEpNum);
if (Ret == XST_FAILURE) {
xil_printf("Failed to restart EP %d on wakeup: %d\r\n",
EpNum, Ret);
return (s32)XST_FAILURE;
}
}
}
return (s32)XST_SUCCESS;
}
#endif /* XUSBPSU_HIBERNATION_ENABLE */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pmbus.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_pmbus.h"
#include "xpm_common.h"
#include "sleep.h"
#ifdef XPAR_XIICPS_1_DEVICE_ID
/*************************** Variable Definitions ****************************/
#define PMBUS_BUFFER_SIZE 3 /**< I2C Buffer size */
static u8 SendBuffer[PMBUS_BUFFER_SIZE]; /**< Data Transmitting Buffer */
/*****************************************************************************/
/**
* This function waits for the I2C Bus to be idle and times out after 1 sec
*
* @param Iic I2C instance
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*****************************************************************************/
static XStatus XPmBus_IdleBusWait(XIicPs *Iic)
{
XStatus Status = XST_FAILURE;
u32 Timeout;
Timeout = 100000;
while (0 != XIicPs_BusIsBusy(Iic)) {
usleep(10);
Timeout--;
if (0U == Timeout) {
PmErr("ERROR: I2C bus idle wait timeout\r\n");
goto done;
}
}
Status = XST_SUCCESS;
done:
return Status;
}
/*****************************************************************************/
/**
* This function is used to call the Master send from IICPS driver
*
* @param Iic I2C instance
* @param SlaveAddr Address of slave device to write to
* @param Buffer Data buffer for commands
* @param ByteCount Number of bytes in the buffer
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*****************************************************************************/
static XStatus XPmBus_Write(XIicPs *Iic, u16 SlaveAddr,
u8 *Buffer, s32 ByteCount)
{
XStatus Status = XST_FAILURE;
/* Continuously try to send in case of arbitration */
do {
if (0 != Iic->IsRepeatedStart) {
Status = XPmBus_IdleBusWait(Iic);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XIicPs_MasterSendPolled(Iic, Buffer, ByteCount, SlaveAddr);
} while (XST_IIC_ARB_LOST == Status);
if (XST_SUCCESS != Status) {
PmErr("I2C write failure\r\n");
}
done:
return Status;
}
/*****************************************************************************/
/**
* This function is used to call the Master receive from IICPS driver
*
* @param Iic I2C instance
* @param SlaveAddr Address of slave device to read from
* @param Buffer Data buffer for commands
* @param ByteCount Number of bytes in the buffer
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*****************************************************************************/
static XStatus XPmBus_Read(XIicPs *Iic, u16 SlaveAddr,
u8 *Buffer, s32 ByteCount)
{
XStatus Status = XST_FAILURE;
/* Continuously try to read in case of arbitration */
do {
Status = XPmBus_IdleBusWait(Iic);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XIicPs_MasterRecvPolled(Iic, Buffer, ByteCount, SlaveAddr);
} while (XST_IIC_ARB_LOST == Status);
if (XST_SUCCESS != Status) {
PmErr("I2C read failure\r\n");
}
done:
return Status;
}
/*****************************************************************************/
/**
* This function is used to write a single byte to a slave device
*
* @param Iic I2C instance
* @param SlaveAddr Address of slave device to write to
* @param Command PmBus command to send to slave
* @param Byte Single byte of data to write
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*****************************************************************************/
XStatus XPmBus_WriteByte(XIicPs *Iic, u16 SlaveAddr, u8 Command, u8 Byte)
{
XStatus Status = XST_FAILURE;
SendBuffer[0] = Command;
SendBuffer[1] = Byte;
Status = XPmBus_Write(Iic, SlaveAddr, SendBuffer, 2);
if (XST_SUCCESS != Status) {
PmErr("I2C write byte failure\r\n");
}
return Status;
}
/*****************************************************************************/
/**
* This function is used to write a word to a slave device
*
* @param Iic I2C instance
* @param SlaveAddr Address of slave device to write to
* @param Command PmBus command to send to slave
* @param Word Word of data to write
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*****************************************************************************/
XStatus XPmBus_WriteWord(XIicPs *Iic, u16 SlaveAddr, u8 Command, u16 Word)
{
XStatus Status = XST_FAILURE;
SendBuffer[0] = Command;
SendBuffer[1] = (u8) (Word >> 8);
SendBuffer[2] = (u8) (Word);
Status = XPmBus_Write(Iic, SlaveAddr, SendBuffer, 3);
if (XST_SUCCESS != Status) {
PmErr("I2C write word failure\r\n");
}
return Status;
}
/*****************************************************************************/
/**
* This function is used to read from a slave device
*
* @param Iic I2C instance
* @param Buffer Buffer to store data read from device
* @param SlaveAddr Address of slave device to read from
* @param Command PmBus command to send to slave
* @param ByteCount Number of bytes to receive from slave device
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*****************************************************************************/
XStatus XPmBus_ReadData(XIicPs *Iic, u8 *Buffer, u16 SlaveAddr,
u8 Command, s32 ByteCount)
{
XStatus Status = XST_FAILURE;
SendBuffer[0] = Command;
Status = XPmBus_Write(Iic, SlaveAddr, SendBuffer, 1);
if (XST_SUCCESS != Status) {
PmErr("Iic write command for read failure\r\n");
goto done;
}
/* Clear repeated start condition to reset hold bit */
if (0 != Iic->IsRepeatedStart) {
Status = XIicPs_ClearOptions(Iic, XIICPS_REP_START_OPTION);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XPmBus_Read(Iic, SlaveAddr, Buffer, ByteCount);
if (XST_SUCCESS != Status) {
PmErr("I2C read data failure\r\n");
}
done:
return Status;
}
#endif /* XPAR_XIICPS_1_DEVICE_ID */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/rfdc_v8_0/src/xrfdc_mts.h
/******************************************************************************
* Copyright (C) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrfdc_mts.c
* @addtogroup rfdc_v8_0
* @{
*
* Contains the multi tile sync related structures, Macros of the XRFdc driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 3.1 jm 01/24/18 Initial release
* 3.2 jm 03/12/18 Fixed DAC latency calculation.
* jm 03/12/18 Added support for reloading DTC scans.
* jm 03/12/18 Add option to configure sysref capture after MTS.
* 4.0 sk 04/09/18 Added API to enable/disable the sysref.
* rk 04/17/18 Adjust calculated latency by sysref period, where doing
* so results in closer alignment to the target latency.
* 5.0 sk 08/03/18 Fixed MISRAC warnings.
* sk 08/03/18 Check for Block0 enable for tiles participating in MTS.
* sk 08/24/18 Reorganize the code to improve readability and
* optimization.
* 6.0 cog 02/17/19 Added XRFdc_GetMTSEnable API.
* 7.0 cog 05/13/19 Formatting changes.
* 7.1 cog 01/20/20 Changes for MTS Gen 1/2 compatibility mode.
* 8.0 cog 02/10/20 Updated addtogroup.
*
* </pre>
*
******************************************************************************/
#ifndef RFDC_MTS_H_
#define RFDC_MTS_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xrfdc.h"
/************************** Constant Definitions *****************************/
#define XRFDC_MTS_RMW(read, mask, data) (((read) & ~(mask)) | ((data) & (mask)))
#define XRFDC_MTS_FIELD(data, mask, shift) (((data) & (mask)) >> (shift))
/**************************** Type Definitions *******************************/
typedef struct {
u32 RefTile;
u32 IsPLL;
int Target[4];
int Scan_Mode;
int DTC_Code[4];
int Num_Windows[4];
int Max_Gap[4];
int Min_Gap[4];
int Max_Overlap[4];
} XRFdc_MTS_DTC_Settings;
typedef struct {
u32 RefTile;
u32 Tiles;
int Target_Latency;
int Offset[4];
int Latency[4];
int Marker_Delay;
int SysRef_Enable;
XRFdc_MTS_DTC_Settings DTC_Set_PLL;
XRFdc_MTS_DTC_Settings DTC_Set_T1;
} XRFdc_MultiConverter_Sync_Config;
typedef struct {
u32 Count[4];
u32 Loc[4];
} XRFdc_MTS_Marker;
/***************** Macros (Inline Functions) Definitions *********************/
#define XRFDC_MTS_SYSREF_DISABLE 0U
#define XRFDC_MTS_SYSREF_ENABLE 1U
#define XRFDC_MTS_NUM_DTC 128U
#define XRFDC_MTS_REF_TARGET 64U
#define XRFDC_MTS_MAX_CODE 16U
#define XRFDC_MTS_MIN_GAP_T1 10U
#define XRFDC_MTS_MIN_GAP_PLL 5U
#define XRFDC_MTS_SR_TIMEOUT 4096U
#define XRFDC_MTS_DTC_COUNT 10U
#define XRFDC_MTS_MARKER_COUNT 4U
#define XRFDC_MTS_SCAN_INIT 0U
#define XRFDC_MTS_SCAN_RELOAD 1U
#define XRFDC_MTS_SRCOUNT_TIMEOUT 1000U
#define XRFDC_MTS_DELAY_MAX 31U
#define XRFDC_MTS_CHECK_ALL_FIFOS 0U
#define XRFDC_MTS_SRCAP_T1_EN 0x4000U
#define XRFDC_MTS_SRCAP_T1_RST 0x0800U
#define XRFDC_MTS_SRFLAG_T1 0x4U
#define XRFDC_MTS_SRFLAG_PLL 0x2U
#define XRFDC_MTS_FIFO_DEFAULT 0x0000U
#define XRFDC_MTS_FIFO_ENABLE 0x0003U
#define XRFDC_MTS_FIFO_DISABLE 0x0002U
#define XRFDC_MTS_AMARK_LOC_S 0x10U
#define XRFDC_MTS_AMARK_DONE_S 0x14U
#define XRFDC_MTS_DLY_ALIGNER0 0x28U
#define XRFDC_MTS_DLY_ALIGNER1 0x2CU
#define XRFDC_MTS_DLY_ALIGNER2 0x30U
#define XRFDC_MTS_DLY_ALIGNER3 0x34U
#define XRFDC_MTS_DIR_FIFO_PTR 0x40U
#define XRFDC_MTS_DAC_MARKER_LOC_MASK(X) ((X < XRFDC_GEN3) ? 0x7U : 0xFU)
/* Error Codes */
#define XRFDC_MTS_OK 0U
#define XRFDC_MTS_NOT_SUPPORTED 1U
#define XRFDC_MTS_TIMEOUT 2U
#define XRFDC_MTS_MARKER_RUN 4U
#define XRFDC_MTS_MARKER_MISM 8U
#define XRFDC_MTS_DELAY_OVER 16U
#define XRFDC_MTS_TARGET_LOW 32U
#define XRFDC_MTS_IP_NOT_READY 64U
#define XRFDC_MTS_DTC_INVALID 128U
#define XRFDC_MTS_NOT_ENABLED 512U
#define XRFDC_MTS_SYSREF_GATE_ERROR 2048U
#define XRFDC_MTS_SYSREF_FREQ_NDONE 4096U
/************************** Function Prototypes ******************************/
u32 XRFdc_MultiConverter_Sync(XRFdc *InstancePtr, u32 Type, XRFdc_MultiConverter_Sync_Config *ConfigPtr);
void XRFdc_MultiConverter_Init(XRFdc_MultiConverter_Sync_Config *ConfigPtr, int *PLL_CodesPtr, int *T1_CodesPtr);
u32 XRFdc_MTS_Sysref_Config(XRFdc *InstancePtr, XRFdc_MultiConverter_Sync_Config *DACSyncConfigPtr,
XRFdc_MultiConverter_Sync_Config *ADCSyncConfigPtr, u32 SysRefEnable);
u32 XRFdc_GetMTSEnable(XRFdc *InstancePtr, u32 Type, u32 Tile, u32 *EnablePtr);
#ifdef __cplusplus
}
#endif
#endif /* RFDC_MTS_H_ */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_node_idle.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* Implementation of individual node idle function and inclusion of
* driver header depending on the availability of the IP in the design
*********************************************************************/
#ifndef PM_NODE_IDLE_H_
#define PM_NODE_IDLE_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xparameters.h"
#if defined(XPAR_PSU_TTC_0_DEVICE_ID) || \
defined(XPAR_PSU_TTC_3_DEVICE_ID) || \
defined(XPAR_PSU_TTC_6_DEVICE_ID) || \
defined(XPAR_PSU_TTC_9_DEVICE_ID)
#include <xttcps_hw.h>
void NodeTtcIdle(u32 BaseAddress);
#endif
#if defined(XPAR_PSU_ETHERNET_0_DEVICE_ID) || \
defined(XPAR_PSU_ETHERNET_1_DEVICE_ID) || \
defined(XPAR_PSU_ETHERNET_2_DEVICE_ID) || \
defined(XPAR_PSU_ETHERNET_3_DEVICE_ID)
#include <xemacps_hw.h>
void NodeGemIdle(u32 BaseAddress);
#endif
#if defined(XPAR_PSU_UART_0_DEVICE_ID) || \
defined(XPAR_PSU_UART_1_DEVICE_ID)
#include <xuartps_hw.h>
#endif
#if defined(XPAR_PSU_SPI_0_DEVICE_ID) || \
defined(XPAR_PSU_SPI_1_DEVICE_ID)
#include <xspips_hw.h>
#endif
#if defined(XPAR_PSU_I2C_0_DEVICE_ID) || \
defined(XPAR_PSU_I2C_1_DEVICE_ID)
#include <xiicps_hw.h>
void NodeI2cIdle(u32 BaseAddress);
#endif
#if defined(XPAR_PSU_SD_0_DEVICE_ID) || \
defined(XPAR_PSU_SD_1_DEVICE_ID)
#include <xsdps_hw.h>
void NodeSdioIdle(u32 BaseAddress);
#endif
#ifdef XPAR_PSU_QSPI_0_DEVICE_ID
#include <xqspipsu_hw.h>
void NodeQspiIdle(u32 BaseAddress);
#endif
#ifdef XPAR_PSU_GPIO_0_DEVICE_ID
#include <xgpiops_hw.h>
#endif
#if defined(XPAR_XUSBPSU_0_DEVICE_ID) || \
defined(XPAR_XUSBPSU_1_DEVICE_ID)
#include "xusbpsu.h"
#include "xusbpsu_endpoint.h"
void NodeUsbIdle(u32 BaseAddress);
#endif
#ifdef XPAR_XDPPSU_0_DEVICE_ID
#ifdef XPAR_PSU_DPDMA_DEVICE_ID
#include "xdpdma_hw.h"
#endif
#include "xdppsu_hw.h"
void NodeDpIdle(u32 BaseAddress);
#endif
#ifdef XPAR_PSU_SATA_S_AXI_BASEADDR
void NodeSataIdle(u32 BaseAddress);
#endif
#if defined(XPAR_PSU_ZDMA_0_DEVICE_ID) || \
defined(XPAR_PSU_ADMA_0_DEVICE_ID)
#include "xzdma_hw.h"
void NodeZdmaIdle(u32 BaseAddress);
/* Total number of channels and offset per DMA */
#define XZDMA_CH_OFFSET 0X10000
#define XZDMA_NUM_CHANNEL 8U /* Number of channels */
#endif
#if defined(XPAR_PSU_CAN_0_DEVICE_ID) || \
defined(XPAR_PSU_CAN_1_DEVICE_ID)
#include "xcanps_hw.h"
void NodeCanIdle(u32 BaseAddress);
#endif
#if defined(XPAR_PSU_NAND_0_DEVICE_ID)
#include "xnandpsu.h"
void NodeNandIdle(u32 BaseAddress);
#endif
#ifdef XPAR_PSU_GPU_S_AXI_BASEADDR
#define GPU_PP_0_OFFSET 0x8000
#define GPU_PP_1_OFFSET 0xA000
void NodeGpuIdle(u32 BaseAddress);
void NodeGpuPPIdle(u32 BaseAddress);
#endif
#ifdef __cplusplus
}
#endif
#endif /* PM_NODE_IDLE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/sysmonpsu_v2_6/src/xsysmonpsu_selftest.c
/******************************************************************************
* Copyright (C) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsysmonpsu_selftest.c
* @addtogroup sysmonpsu_v2_6
*
* This file contains a diagnostic self test function for the XSysMon driver.
* The self test function does a simple read/write test of the Alarm Threshold
* Register.
*
* See xsysmonpsu.h for more information.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.0 kvn 12/15/15 First release
* 2.5 mn 07/06/18 Fixed Doxygen warnings
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xsysmonpsu.h"
/************************** Constant Definitions ****************************/
/*
* The following constant defines the test value to be written
* to the Alarm Threshold Register
*/
#define XSM_ATR_TEST_VALUE 0x55U
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/*****************************************************************************/
/**
*
* Run a self-test on the driver/device. The test
* - Resets the device,
* - Writes a value into the Alarm Threshold register and reads it back
* for comparison.
* - Resets the device again.
*
*
* @param InstancePtr is a pointer to the XSysMonPsu instance.
*
* @return
* - XST_SUCCESS if the value read from the Alarm Threshold
* register is the same as the value written.
* - XST_FAILURE Otherwise
*
* @note This is a destructive test in that resets of the device are
* performed. Refer to the device specification for the
* device status after the reset operation.
*
******************************************************************************/
s32 XSysMonPsu_SelfTest(XSysMonPsu *InstancePtr)
{
s32 Status;
u32 RegValue;
/* Assert the argument */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Reset the device to get it back to its default state */
XSysMonPsu_Reset(InstancePtr);
/*
* Write a value into the Alarm Threshold registers, read it back, and
* do the comparison
*/
XSysMonPsu_SetAlarmThreshold(InstancePtr, XSM_ATR_SUP1_UPPER,
XSM_ATR_TEST_VALUE, XSYSMON_PS);
RegValue = (u32)XSysMonPsu_GetAlarmThreshold(InstancePtr,
XSM_ATR_SUP1_UPPER, XSYSMON_PS);
if (RegValue == XSM_ATR_TEST_VALUE) {
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
/* Reset the device again to its default state. */
XSysMonPsu_Reset(InstancePtr);
/* Return the test result. */
return Status;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/include/xilskey_eps_zynqmp_hw.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilskey_eps_zynqmp_hw.h
* This header file contains identifiers and register-level driver functions (or
* macros) that can be used to access the Xilinx ZynqMp eFuse controller.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 4.0 vns 10/01/15 First release
* 6.0 vns 07/18/16 Modified RSA enable bit mask
* 6.2 vns 03/10/17 Added support for LBIST, LPD and FPD sc enable,
* PBR_BOOT_ERROR.
* 6.7 arc 01/05/19 Fixed MISRA-C violations.
* </pre>
*
******************************************************************************/
#ifndef __XSK_EPS_ZYNQMP_HW_H__
#define __XSK_EPS_ZYNQMP_HW_H__
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name eFuse PS Base Address
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_BASEADDR 0xFFCC0000U/**< Efuse PS base address */
/*@}*/
/** @name Write lock register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_OFFSET 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_RSTVAL 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_WIDTH 16U
#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_MASK 0x0000ffffU
#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_DEFVAL 0x1U
#define XSK_ZYNQMO_EFUSEP_WR_UNLOCK_VALUE 0xDF0D
/*@}*/
/** @name Cfg register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_CFG_OFFSET 0x00000004U
#define XSK_ZYNQMP_EFUSEPS_CFG_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_CFG_SLVERR_EN_SHIFT 5U
#define XSK_ZYNQMP_EFUSEPS_CFG_SLVERR_EN_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_CFG_SLVERR_EN_MASK 0x00000020U
#define XSK_ZYNQMP_EFUSEPS_CFG_SLVERR_EN_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_SHIFT 2U
#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_WIDTH 2U
#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_MASK 0x0000000cU
#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_1_RD 0x01
#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_2_RD 0x02U
#define XSK_ZYNQMP_EFUSEPS_CFG_NORMAL_RD 0x00U
#define XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_SHIFT 1U
#define XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_MASK 0x00000002U
#define XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_MASK 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_DEFVAL 0x0U
/*@}*/
/** @name Status register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_STS_OFFSET 0x00000008U
#define XSK_ZYNQMP_EFUSEPS_STS_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_PASS_SHIFT 7U
#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_PASS_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_PASS_MASK 0x00000080U
#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_PASS_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_SHIFT 6U
#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_MASK 0x00000040U
#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_SHIFT 5U
#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_MASK 0x00000020U
#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_SHIFT 4U
#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_MASK 0x00000010U
#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_SHIFT 2U
#define XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_MASK 0x00000004U
#define XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_SHIFT 1U
#define XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_MASK 0x00000002U
#define XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_MASK 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_DEFVAL 0x0U
/*@}*/
/** @name program address register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_OFFSET 0x0000000CU
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_SHIFT 11U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_WIDTH 2U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_MASK 0x00001800U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_SHIFT 5U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_WIDTH 6U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_MASK 0x000007e0U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_COL_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_COL_WIDTH 5U
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_COL_MASK 0x0000001fU
#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_COL_DEFVAL 0x0U
/*@}*/
/** @name read address register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_OFFSET 0x00000010U
#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_SHIFT 11U
#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_WIDTH 2U
#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_MASK 0x00001800U
#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_SHIFT 5U
#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_WIDTH 6U
#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_MASK 0x000007e0U
#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_DEFVAL 0x0U
/*@}*/
/** @name read data register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_RD_DATA_OFFSET 0x00000014U
#define XSK_ZYNQMP_EFUSEPS_RD_DATA_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_RD_DATA_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_RD_DATA_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_RD_DATA_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_RD_DATA_DEFVAL 0x0U
/*@}*/
/** @name TPGM register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_TPGM_OFFSET 0x00000018U
#define XSK_ZYNQMP_EFUSEPS_TPGM_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_TPGM_VAL_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_TPGM_VAL_WIDTH 16U
#define XSK_ZYNQMP_EFUSEPS_TPGM_VAL_MASK 0x0000ffffU
#define XSK_ZYNQMP_EFUSEPS_TPGM_VAL_DEFVAL 0x0U
/*@}*/
/** @name TRD register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_TRD_OFFSET 0x0000001CU
#define XSK_ZYNQMP_EFUSEPS_TRD_RSTVAL 0x00000022U
#define XSK_ZYNQMP_EFUSEPS_TRD_VAL_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_TRD_VAL_WIDTH 8U
#define XSK_ZYNQMP_EFUSEPS_TRD_VAL_MASK 0x000000ffU
#define XSK_ZYNQMP_EFUSEPS_TRD_VAL_DEFVAL 0x22U
/*@}*/
/** @name TSU_H_PS register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_OFFSET 0x00000020U
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_RSTVAL 0x000000ffU
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_VAL_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_VAL_WIDTH 8U
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_VAL_MASK 0x000000ffU
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_VAL_DEFVAL 0xffU
/*@}*/
/** @name TSU H PS register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_OFFSET 0x00000024U
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_RSTVAL 0x0000000bU
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_WIDTH 8U
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_MASK 0x000000ffU
#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_DEFVAL 0xbU
/*@}*/
/** @name TSU H CS register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_OFFSET 0x0000002CU
#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_RSTVAL 0x00000007U
#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_VAL_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_VAL_WIDTH 4U
#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_VAL_MASK 0x0000000fU
#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_VAL_DEFVAL 0x7U
/*@}*/
/** @name ISR register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_ISR_OFFSET 0x00000030U
#define XSK_ZYNQMP_EFUSEPS_ISR_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_ISR_APB_SLVERR_SHIFT 31U
#define XSK_ZYNQMP_EFUSEPS_ISR_APB_SLVERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_ISR_APB_SLVERR_MASK 0x80000000U
#define XSK_ZYNQMP_EFUSEPS_ISR_APB_SLVERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_SHIFT 4U
#define XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_MASK 0x00000010U
#define XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_SHIFT 3U
#define XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_MASK 0x00000008U
#define XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_SHIFT 2U
#define XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_MASK 0x00000004U
#define XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_SHIFT 1U
#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_MASK 0x00000002U
#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_MASK 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_DEFVAL 0U
/*@}*/
/** @name IMR register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_IMR_OFFSET 0x00000034U
#define XSK_ZYNQMP_EFUSEPS_IMR_RSTVAL 0x8000001fU
#define XSK_ZYNQMP_EFUSEPS_IMR_APB_SLVERR_SHIFT 31U
#define XSK_ZYNQMP_EFUSEPS_IMR_APB_SLVERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IMR_APB_SLVERR_MASK 0x80000000U
#define XSK_ZYNQMP_EFUSEPS_IMR_APB_SLVERR_DEFVAL 0x1U
#define XSK_ZYNQMP_EFUSEPS_IMR_CACHE_ERR_SHIFT 4U
#define XSK_ZYNQMP_EFUSEPS_IMR_CACHE_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IMR_CACHE_ERR_MASK 0x00000010U
#define XSK_ZYNQMP_EFUSEPS_IMR_CACHE_ERR_DEFVAL 0x1U
#define XSK_ZYNQMP_EFUSEPS_IMR_RD_ERR_SHIFT 3U
#define XSK_ZYNQMP_EFUSEPS_IMR_RD_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IMR_RD_ERR_MASK 0x00000008U
#define XSK_ZYNQMP_EFUSEPS_IMR_RD_ERR_DEFVAL 0x1U
#define XSK_ZYNQMP_EFUSEPS_IMR_RD_DONE_SHIFT 2U
#define XSK_ZYNQMP_EFUSEPS_IMR_RD_DONE_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IMR_RD_DONE_MASK 0x00000004U
#define XSK_ZYNQMP_EFUSEPS_IMR_RD_DONE_DEFVAL 0x1U
#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_ERR_SHIFT 1U
#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_ERR_MASK 0x00000002U
#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_ERR_DEFVAL 0x1U
#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_DONE_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_DONE_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_DONE_MASK 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_DONE_DEFVAL 0x1U
/*@}*/
/** @name IER register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_IER_OFFSET 0x00000038U
#define XSK_ZYNQMP_EFUSEPS_IER_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_IER_APB_SLVERR_SHIFT 31U
#define XSK_ZYNQMP_EFUSEPS_IER_APB_SLVERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IER_APB_SLVERR_MASK 0x80000000U
#define XSK_ZYNQMP_EFUSEPS_IER_APB_SLVERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_IER_CACHE_ERR_SHIFT 4U
#define XSK_ZYNQMP_EFUSEPS_IER_CACHE_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IER_CACHE_ERR_MASK 0x00000010U
#define XSK_ZYNQMP_EFUSEPS_IER_CACHE_ERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_IER_RD_ERR_SHIFT 3U
#define XSK_ZYNQMP_EFUSEPS_IER_RD_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IER_RD_ERR_MASK 0x00000008U
#define XSK_ZYNQMP_EFUSEPS_IER_RD_ERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_IER_RD_DONE_SHIFT 2U
#define XSK_ZYNQMP_EFUSEPS_IER_RD_DONE_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IER_RD_DONE_MASK 0x00000004U
#define XSK_ZYNQMP_EFUSEPS_IER_RD_DONE_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_IER_PGM_ERR_SHIFT 1U
#define XSK_ZYNQMP_EFUSEPS_IER_PGM_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IER_PGM_ERR_MASK 0x00000002U
#define XSK_ZYNQMP_EFUSEPS_IER_PGM_ERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_IER_PGM_DONE_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_IER_PGM_DONE_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IER_PGM_DONE_MASK 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_IER_PGM_DONE_DEFVAL 0x0U
/*@}*/
/** @name IDR register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_IDR_OFFSET 0x0000003CU
#define XSK_ZYNQMP_EFUSEPS_IDR_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_IDR_APB_SLVERR_SHIFT 31U
#define XSK_ZYNQMP_EFUSEPS_IDR_APB_SLVERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IDR_APB_SLVERR_MASK 0x80000000U
#define XSK_ZYNQMP_EFUSEPS_IDR_APB_SLVERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_IDR_CACHE_ERR_SHIFT 4U
#define XSK_ZYNQMP_EFUSEPS_IDR_CACHE_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IDR_CACHE_ERR_MASK 0x00000010U
#define XSK_ZYNQMP_EFUSEPS_IDR_CACHE_ERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_IDR_RD_ERR_SHIFT 3U
#define XSK_ZYNQMP_EFUSEPS_IDR_RD_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IDR_RD_ERR_MASK 0x00000008U
#define XSK_ZYNQMP_EFUSEPS_IDR_RD_ERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_IDR_RD_DONE_SHIFT 2U
#define XSK_ZYNQMP_EFUSEPS_IDR_RD_DONE_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IDR_RD_DONE_MASK 0x00000004U
#define XSK_ZYNQMP_EFUSEPS_IDR_RD_DONE_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_ERR_SHIFT 1U
#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_ERR_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_ERR_MASK 0x00000002U
#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_ERR_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_DONE_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_DONE_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_DONE_MASK 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_DONE_DEFVAL 0x0U
/*@}*/
/** @name Cache load register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_OFFSET 0x00000040U
#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_MASK 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_DEFVAL 0x0U
/*@}*/
/** @name Program lock register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_OFFSET 0x00000044U
#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_SPK_ID_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_SPK_ID_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_SPK_ID_MASK 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_SPK_ID_DEFVAL 0x0U
/*@}*/
/** @name AES CRC register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_AES_CRC_OFFSET 0x00000048U
#define XSK_ZYNQMP_EFUSEPS_AES_CRC_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_AES_CRC_VAL_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_AES_CRC_VAL_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_AES_CRC_VAL_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_AES_CRC_VAL_DEFVAL 0x0U
/*@}*/
/** @name Tbits programming enable register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_TBITS_PRGRMG_EN_OFFSET 0x00000100U
#define XSK_ZYNQMP_EFUSEPS_TBITS_PRGRMG_EN_MASK 0x00000008U
/*@}*/
/** @name DNA 0 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_DNA_0_OFFSET 0x0000100CU
#define XSK_ZYNQMP_EFUSEPS_DNA_0_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_DNA_0_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_DNA_0_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_DNA_0_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_DNA_0_DEFVAL 0x0U
/*@}*/
/** @name DNA 1 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_DNA_1_OFFSET 0x00001010U
#define XSK_ZYNQMP_EFUSEPS_DNA_1_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_DNA_1_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_DNA_1_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_DNA_1_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_DNA_1_DEFVAL 0x0U
/*@}*/
/** @name DNA 2 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_DNA_2_OFFSET 0x00001014U
#define XSK_ZYNQMP_EFUSEPS_DNA_2_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_DNA_2_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_DNA_2_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_DNA_2_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_DNA_2_DEFVAL 0x0U
/*@}*/
/** @name User_0 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_USER_0_OFFSET 0x00001020U
#define XSK_ZYNQMP_EFUSEPS_USER_0_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_USER_0_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_USER_0_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_USER_0_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_USER_0_DEFVAL 0x0U
/*@}*/
/** @name User_1 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_USER_1_OFFSET 0x00001024U
#define XSK_ZYNQMP_EFUSEPS_USER_1_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_USER_1_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_USER_1_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_USER_1_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_USER_1_DEFVAL 0x0U
/*@}*/
/** @name User_2 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_USER_2_OFFSET 0x00001028U
#define XSK_ZYNQMP_EFUSEPS_USER_2_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_USER_2_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_USER_2_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_USER_2_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_USER_2_DEFVAL 0x0U
/*@}*/
/** @name User_3 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_USER_3_OFFSET 0x0000102CU
#define XSK_ZYNQMP_EFUSEPS_USER_3_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_USER_3_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_USER_3_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_USER_3_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_USER_3_DEFVAL 0x0U
/*@}*/
/** @name User_4 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_USER_4_OFFSET 0x00001030U
#define XSK_ZYNQMP_EFUSEPS_USER_4_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_USER_4_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_USER_4_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_USER_4_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_USER_4_DEFVAL 0x0U
/*@}*/
/** @name User_5 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_USER_5_OFFSET 0x00001034U
#define XSK_ZYNQMP_EFUSEPS_USER_5_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_USER_5_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_USER_5_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_USER_5_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_USER_5_DEFVAL 0x0U
/*@}*/
/** @name User_6 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_USER_6_OFFSET 0x00001038U
#define XSK_ZYNQMP_EFUSEPS_USER_6_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_USER_6_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_USER_6_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_USER_6_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_USER_6_DEFVAL 0x0U
/*@}*/
/** @name User_7 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_USER_7_OFFSET 0x0000103CU
#define XSK_ZYNQMP_EFUSEPS_USER_7_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_USER_7_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_USER_7_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_USER_7_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_USER_7_DEFVAL 0x0U
/*@}*/
/** @name Misc user control register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_OFFSET 0x00001040U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_RESERVED_MASK 0xFFFE0300U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_LPD_SC_EN_MASK 0x00003800U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_LPD_SC_EN_SHIFT 11U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_FPD_SC_EN_MASK 0x00001C000U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_FPD_SC_EN_SHIFT 14U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_LBIST_EN_SHIFT 10U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_LBIST_EN_MASK 0x00000400U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_SHIFT 7U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_MASK 0x00000080U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_SHIFT 6U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_MASK 0x00000040U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_SHIFT 5U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_MASK 0x00000020U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_SHIFT 4U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_MASK 0x00000010U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_SHIFT 3U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_MASK 0x00000008U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_SHIFT 2U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_MASK 0x00000004U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_SHIFT 1U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_MASK 0x00000002U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_MASK 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_DEFVAL 0x0U
/*@}*/
/** @name PBR Boot error register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_OFFSET 0x00001044U
#define XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_MASK 0x00000007U
#define XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_SHIFT 0U
/*@}*/
/** @name Xilinx specific register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_RESERVED_OFFSET 0x0000104CU
#define XSK_ZYNQMP_EFUSEPS_RESERVED1_MASK 0x0000FFFFU
#define XSK_ZYNQMP_EFUSEPS_RESERVED2_MASK 0xFFFF0000U
#define XSK_ZYNQMP_EFUSEPS_RESERVED_SHIFT 16U
/*@}*/
/** @name Puf CHASH register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PUF_CHASH_OFFSET 0x00001050U
#define XSK_ZYNQMP_EFUSEPS_PUF_CHASH_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PUF_CHASH_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PUF_CHASH_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PUF_CHASH_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PUF_CHASH_DEFVAL 0x0U
/*@}*/
/** @name Puf MISC register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_OFFSET 0x00001054U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_REG_DIS_SHIFT 31U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_REG_DIS_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_REG_DIS_MASK 0x80000000U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_REG_DIS_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_WRLK_SHIFT 30U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_WRLK_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_WRLK_MASK 0x40000000U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_WRLK_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_INVLD_SHIFT 29U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_INVLD_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_INVLD_MASK 0x20000000U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_INVLD_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_RESERVED_SHIFT 28U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_RESERVED_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_RESERVED_MASK 0x10000000U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_RESERVED_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_AUX_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_AUX_WIDTH 24U
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_AUX_MASK 0x00ffffffU
#define XSK_ZYNQMP_EFUSEPS_PUF_MISC_AUX_DEFVAL 0x0U
/*@}*/
/** @name Secure control register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_OFFSET 0x00001058U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_SHIFT 30U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_WIDTH 2U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_MASK 0xc0000000U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_SHIFT 29U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_MASK 0x20000000U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_SHIFT 27U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_WIDTH 2U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_MASK 0x18000000U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_SHIFT 26U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_MASK 0x04000000U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_SHIFT 11U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_WIDTH 15U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_MASK 0x03FFF800U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_SHIFT 10U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_MASK 0x00000400U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_SHIFT 9U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_MASK 0x00000200U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_SHIFT 8U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_MASK 0x00000100U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_SHIFT 7U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_MASK 0x00000080U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_MASK ( \
(u32)XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_MASK | \
(u32)XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_MASK | \
(u32)XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_MASK)
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_SHIFT 6U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_MASK 0x00000040U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_SHIFT 5U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_MASK 0x00000020U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_SHIFT 4U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_MASK 0x00000010U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_SHIFT 3U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_MASK 0x00000008U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_SHIFT 2U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_MASK 0x00000004U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_SHIFT 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_MASK 0x00000002U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_DEFVAL 0x0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_WIDTH 1U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_MASK 0x00000001U
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_DEFVAL 0x0U
/*@}*/
/** @name SPK ID register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_SPK_ID_OFFSET 0x0000105CU
#define XSK_ZYNQMP_EFUSEPS_SPK_ID_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_SPK_ID_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_SPK_ID_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_SPK_ID_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_SPK_ID_DEFVAL 0x0U
/*@}*/
/** @name PPK0_0 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_0_OFFSET 0x000010A0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_0_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_0_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_0_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_0_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_0_DEFVAL 0x0U
/*@}*/
/** @name PPK0_1 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_1_OFFSET 0x000010A4U
#define XSK_ZYNQMP_EFUSEPS_PPK0_1_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_1_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_1_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_1_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_1_DEFVAL 0x0U
/*@}*/
/** @name PPK0_2 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_2_OFFSET 0x000010A8U
#define XSK_ZYNQMP_EFUSEPS_PPK0_2_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_2_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_2_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_2_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_2_DEFVAL 0x0U
/*@}*/
/** @name PPK0_3 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_3_OFFSET 0x000010ACU
#define XSK_ZYNQMP_EFUSEPS_PPK0_3_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_3_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_3_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_3_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_3_DEFVAL 0x0U
/*@}*/
/** @name PPK0_4 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_4_OFFSET 0x000010B0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_4_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_4_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_4_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_4_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_4_DEFVAL 0x0U
/*@}*/
/** @name PPK0_5 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_5_OFFSET 0x000010B4U
#define XSK_ZYNQMP_EFUSEPS_PPK0_5_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_5_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_5_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_5_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_5_DEFVAL 0x0U
/*@}*/
/** @name PPK0_6 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_6_OFFSET 0x000010B8U
#define XSK_ZYNQMP_EFUSEPS_PPK0_6_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_6_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_6_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_6_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_6_DEFVAL 0x0U
/*@}*/
/** @name PPK0_7 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_7_OFFSET 0x000010BCU
#define XSK_ZYNQMP_EFUSEPS_PPK0_7_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_7_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_7_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_7_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_7_DEFVAL 0x0U
/*@}*/
/** @name PPK0_8 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_8_OFFSET 0x000010C0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_8_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_8_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_8_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_8_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_8_DEFVAL 0x0U
/*@}*/
/** @name PPK0_9 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_9_OFFSET 0x000010C4U
#define XSK_ZYNQMP_EFUSEPS_PPK0_9_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_9_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_9_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_9_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_9_DEFVAL 0x0U
/*@}*/
/** @name PPK0_10 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_10_OFFSET 0x000010C8U
#define XSK_ZYNQMP_EFUSEPS_PPK0_10_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_10_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_10_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_10_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_10_DEFVAL 0x0U
/*@}*/
/** @name PPK0_11 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK0_11_OFFSET 0x000010CCU
#define XSK_ZYNQMP_EFUSEPS_PPK0_11_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK0_11_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK0_11_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK0_11_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK0_11_DEFVAL 0x0U
/*@}*/
/** @name PPK1_0 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_0_OFFSET 0x000010D0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_0_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_0_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_0_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_0_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_0_DEFVAL 0x0U
/*@}*/
/** @name PPK1_1 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_1_OFFSET 0x000010D4U
#define XSK_ZYNQMP_EFUSEPS_PPK1_1_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_1_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_1_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_1_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_1_DEFVAL 0x0U
/*@}*/
/** @name PPK1_2 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_2_OFFSET 0x000010D8U
#define XSK_ZYNQMP_EFUSEPS_PPK1_2_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_2_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_2_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_2_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_2_DEFVAL 0x0U
/*@}*/
/** @name PPK1_3 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_3_OFFSET 0x000010DCU
#define XSK_ZYNQMP_EFUSEPS_PPK1_3_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_3_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_3_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_3_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_3_DEFVAL 0x0U
/*@}*/
/** @name PPK1_4 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_4_OFFSET 0x000010E0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_4_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_4_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_4_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_4_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_4_DEFVAL 0x0U
/*@}*/
/** @name PPK1_5 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_5_OFFSET 0x000010E4U
#define XSK_ZYNQMP_EFUSEPS_PPK1_5_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_5_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_5_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_5_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_5_DEFVAL 0x0U
/*@}*/
/** @name PPK1_6 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_6_OFFSET 0x000010E8U
#define XSK_ZYNQMP_EFUSEPS_PPK1_6_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_6_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_6_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_6_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_6_DEFVAL 0x0U
/*@}*/
/** @name PPK1_7 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_7_OFFSET 0x000010ECU
#define XSK_ZYNQMP_EFUSEPS_PPK1_7_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_7_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_7_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_7_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_7_DEFVAL 0x0U
/*@}*/
/** @name PPK1_8 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_8_OFFSET 0x000010F0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_8_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_8_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_8_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_8_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_8_DEFVAL 0x0U
/*@}*/
/** @name PPK1_8 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_9_OFFSET 0x000010F4U
#define XSK_ZYNQMP_EFUSEPS_PPK1_9_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_9_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_9_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_9_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_9_DEFVAL 0x0U
/*@}*/
/** @name PPK1_10 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_10_OFFSET 0x000010F8U
#define XSK_ZYNQMP_EFUSEPS_PPK1_10_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_10_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_10_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_10_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_10_DEFVAL 0x0U
/*@}*/
/** @name PPK1_11 register
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PPK1_11_OFFSET 0x000010FCU
#define XSK_ZYNQMP_EFUSEPS_PPK1_11_RSTVAL 0x00000000U
#define XSK_ZYNQMP_EFUSEPS_PPK1_11_SHIFT 0U
#define XSK_ZYNQMP_EFUSEPS_PPK1_11_WIDTH 32U
#define XSK_ZYNQMP_EFUSEPS_PPK1_11_MASK 0xffffffffU
#define XSK_ZYNQMP_EFUSEPS_PPK1_11_DEFVAL 0x0U
/*@}*/
/** @name PUF masks and shifts
* @{
*/
#define XSK_ZYNQMP_EFUSEPS_PUF_ROW_UPPER_MASK 0xFFFF0000U
#define XSK_ZYNQMP_EFUSEPS_PUF_ROW_LOWER_MASK 0x0000FFFFU
#define XSK_ZYNQMP_EFUSEPS_PUF_ROW_HALF_WORD_SHIFT 16U
/*@}*/
/** @name CSU module register offset and base address
* @{
*/
#define XSK_ZYNQMP_CSU_BASEADDR (0XFFCA0000U)
#define XSK_ZYNQMP_CSU_PUF_CMD (0X4000U)
#define XSK_ZYNQMP_CSU_PUF_CFG0 (0X4004U)
#define XSK_ZYNQMP_CSU_PUF_CFG1 (0X4008U)
#define XSK_ZYNQMP_CSU_PUF_SHUT (0X400CU)
#define XSK_ZYNQMP_CSU_PUF_STATUS (0X4010U)
#define XSK_ZYNQMP_CSU_ISR (0x0020U)
#define XSK_ZYNQMP_CSU_ISR_PUF_ACC_ERROR_MASK (0x00001000U)
#define XSK_ZYNQMP_CSU_PUF_STATUS_OVERFLOW_MASK (0X30000000U)
#define XSK_ZYNQMP_CSU_PUF_STATUS_AUX_MASK (0X0FFFFFF0U)
#define XSK_ZYNQMP_CSU_PUF_STATUS_KEY_RDY_MASK (0X00000008U)
#define XSK_ZYNQMP_CSU_PUF_STATUS_SYN_WRD_RDY_MASK (0X00000001U)
#define XSK_ZYNQMP_CSU_PUF_WORD (0X4018U)
/**
* Register: CSU_PUF_TM_STATUS
*/
#define XSK_ZYNQMP_CSU_PUF_TM_STATUS (0X4804U)
#define XSK_ZYNQMP_CSU_PUF_TM_STATUS_DN_MASK (0X00000001U)
/**
* Register: CSU_PUF_TM_UL
*/
#define XSK_ZYNQMP_CSU_PUF_TM_UL (0X00004808U)
/**
* Register: CSU_PUF_TM_LL
*/
#define XSK_ZYNQMP_CSU_PUF_TM_LL (0X0000480CU)
/**
* Register: CSU_PUF_TM_SW
*/
#define XSK_ZYNQMP_CSU_PUF_TM_SW (0X00004810U)
/**
* Register: CSU_PUF_TM_TR
*/
#define XSK_ZYNQMP_CSU_PUF_TM_TR (0X00004814U)
#define XSK_ZYNQMP_CSU_PUF_TM_TR_US_MASK (0X03000000U)
#define XSK_ZYNQMP_CSU_PUF_TM_TR_ER_MASK (0X00FF0000U)
#define XSK_ZYNQMP_CSU_PUF_TM_TR_FRR_MASK (0X00000001U)
#ifdef __cplusplus
}
#endif
#endif /* __XSK_EPS_ZYNQMP_HW_H__ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_system.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* Contains system-level PM functions and state
********************************************************************/
#include "pm_system.h"
#include "pm_common.h"
#include "crl_apb.h"
#include "pm_callbacks.h"
#include "xpfw_resets.h"
#include "pm_requirement.h"
#include "pm_sram.h"
#include "pm_ddr.h"
#include "pm_periph.h"
#include "pm_hooks.h"
#include "pm_extern.h"
#include "pm_qspi.h"
#include "pm_clock.h"
#include "pm_pll.h"
#include "pm_power.h"
#include "rpu.h"
#define OCM_START_ADDR 0xFFFC0000U
#define OCM_END_ADDR 0xFFFFFFFFU
#define DDR_STORE_BASE 0x07000000U
#define TCM_0A_START_ADDR 0xFFE00000U
#define TCM_0A_END_ADDR 0xFFE0FFFFU
#define TCM_0B_START_ADDR 0xFFE20000U
#define TCM_0B_END_ADDR 0xFFE2FFFFU
#define TCM_1A_START_ADDR 0xFFE90000U
#define TCM_1A_END_ADDR 0xFFE9FFFFU
#define TCM_1B_START_ADDR 0xFFEB0000U
#define TCM_1B_END_ADDR 0xFFEBFFFFU
#define TCM_SKIP_MEMORY 0x0U
#define TCM_SAVE_MEMORY 0x1U
#define TCM_BANK_OFFSET 0x80000U
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmSystem - System level information
* @psRestartPerms ORed IPI masks of masters allowed to restart PS
* @systemRestartPerms ORed IPI masks of masters allowed to restart system
* @suspendType Type of system suspend: Regular/Power Off Suspend
*/
typedef struct {
u32 psRestartPerms;
u32 systemRestartPerms;
u32 suspendType;
} PmSystem;
/**
* PmSystemRequirement - System level requirements (not assigned to any master)
* @slave Slave for which the requirements are set
* @caps Capabilities of the slave that are required by the system
* @posCaps Capabilities of the slave that are required for entering Power
* Off Suspend state
*/
typedef struct PmSystemRequirement {
PmSlave* const slave;
u32 caps;
u32 posCaps;
} PmSystemRequirement;
#ifdef ENABLE_POS
/**
* PmTcmMemorySection - TCM memory that may be saved/restored
* @section Memory region start and end address
* @save Flag to mark that region needs to be saved/restored
*/
typedef struct PmTcmMemorySection {
PmMemorySection section;
u32 save;
} PmTcmMemorySection;
#endif
/*********************************************************************
* Data initialization
********************************************************************/
PmSystem pmSystem = {
.psRestartPerms = 0U,
.systemRestartPerms = 0U,
.suspendType = PM_SUSPEND_TYPE_REGULAR,
};
/*
* These requirements are needed for the system to operate:
* - OCM bank(s) store FSBL which is needed to restart APU, and should never be
* powered down unless the whole system goes down.
*/
PmSystemRequirement pmSystemReqs[] = {
{
.slave = &pmSlaveOcm0_g.slv,
.caps = PM_CAP_CONTEXT,
.posCaps = PM_CAP_ACCESS,
}, {
.slave = &pmSlaveOcm1_g.slv,
.caps = PM_CAP_CONTEXT,
.posCaps = PM_CAP_ACCESS,
}, {
.slave = &pmSlaveOcm2_g.slv,
.caps = PM_CAP_CONTEXT,
.posCaps = PM_CAP_ACCESS,
},{
.slave = &pmSlaveOcm3_g.slv,
.caps = PM_CAP_CONTEXT,
.posCaps = PM_CAP_ACCESS,
},{
.slave = &pmSlaveDdr_g,
.caps = PM_CAP_CONTEXT,
.posCaps = PM_CAP_ACCESS,
},{
.slave = &pmSlavePl_g,
.caps = 0U,
.posCaps = 0U,
},
#ifdef DEBUG_MODE
#if (STDOUT_BASEADDRESS == XPAR_PSU_UART_0_BASEADDR)
{
.slave = &pmSlaveUart0_g,
.caps = PM_CAP_ACCESS,
.posCaps = PM_CAP_ACCESS,
},
#endif
#if (STDOUT_BASEADDRESS == XPAR_PSU_UART_1_BASEADDR)
{
.slave = &pmSlaveUart1_g,
.caps = PM_CAP_ACCESS,
.posCaps = PM_CAP_ACCESS,
},
#endif
#endif
#ifdef ENABLE_POS
/* TCM requirements used when TCM context should be saved/restored */
{
.slave = &pmSlaveTcm0A_g.sram.slv,
.caps = 0U,
.posCaps = 0U,
}, {
.slave = &pmSlaveTcm0B_g.sram.slv,
.caps = 0U,
.posCaps = 0U,
},{
.slave = &pmSlaveTcm1A_g.sram.slv,
.caps = 0U,
.posCaps = 0U,
},{
.slave = &pmSlaveTcm1B_g.sram.slv,
.caps = 0U,
.posCaps = 0U,
},
#endif
};
#ifdef ENABLE_POS
extern u8 __data_start;
extern u8 __data_end;
extern u8 __bss_start;
extern u8 __bss_end;
/* Memory sections that needs to be saved/restored during Power Off Suspend */
PmMemorySection pmSystemMemory[] = {
/* PMU data and bss section */
{
.startAddr = (u32)&__data_start,
.endAddr = (u32)&__data_end - 1U,
}, {
.startAddr = (u32)&__bss_start,
.endAddr = (u32)&__bss_end - 1U,
},
/* OCM data */
{
.startAddr = OCM_START_ADDR,
.endAddr = OCM_END_ADDR,
},
};
/* TCM memory sections that may be saved/restored during Power Off Suspend */
PmTcmMemorySection pmSystemTcmMemory[] = {
{
{
.startAddr = TCM_0A_START_ADDR,
.endAddr = TCM_0A_END_ADDR,
},
.save = TCM_SKIP_MEMORY,
}, {
{
.startAddr = TCM_0B_START_ADDR,
.endAddr = TCM_0B_END_ADDR,
},
.save = TCM_SKIP_MEMORY,
}, {
{
.startAddr = TCM_1A_START_ADDR,
.endAddr = TCM_1A_END_ADDR,
},
.save = TCM_SKIP_MEMORY,
}, {
{
.startAddr = TCM_1B_START_ADDR,
.endAddr = TCM_1B_END_ADDR,
},
.save = TCM_SKIP_MEMORY,
},
};
/* TCM slaves that may need context save/restore during Power Off Suspend */
PmSlaveTcm* pmSystemTcmSlaves [] = {
&pmSlaveTcm0A_g,
&pmSlaveTcm0B_g,
&pmSlaveTcm1A_g,
&pmSlaveTcm1B_g,
};
/* System registers that needs to be saved/restored during Power Off Suspend */
static PmRegisterContext pmSystemRegs[] = {
/* IOU_SLCR */
{ .addr = 0XFF180000U, },
{ .addr = 0XFF180004U, },
{ .addr = 0XFF180008U, },
{ .addr = 0XFF18000CU, },
{ .addr = 0XFF180010U, },
{ .addr = 0XFF180014U, },
{ .addr = 0XFF180018U, },
{ .addr = 0XFF18001CU, },
{ .addr = 0XFF180020U, },
{ .addr = 0XFF180024U, },
{ .addr = 0XFF180028U, },
{ .addr = 0XFF18002CU, },
{ .addr = 0XFF180030U, },
{ .addr = 0XFF180034U, },
{ .addr = 0XFF180038U, },
{ .addr = 0XFF18003CU, },
{ .addr = 0XFF180040U, },
{ .addr = 0XFF180044U, },
{ .addr = 0XFF180048U, },
{ .addr = 0XFF18004CU, },
{ .addr = 0XFF180050U, },
{ .addr = 0XFF180054U, },
{ .addr = 0XFF180058U, },
{ .addr = 0XFF18005CU, },
{ .addr = 0XFF180060U, },
{ .addr = 0XFF180064U, },
{ .addr = 0XFF180068U, },
{ .addr = 0XFF18006CU, },
{ .addr = 0XFF180070U, },
{ .addr = 0XFF180074U, },
{ .addr = 0XFF180078U, },
{ .addr = 0XFF18007CU, },
{ .addr = 0XFF180080U, },
{ .addr = 0XFF180084U, },
{ .addr = 0XFF180088U, },
{ .addr = 0XFF18008CU, },
{ .addr = 0XFF180090U, },
{ .addr = 0XFF180094U, },
{ .addr = 0XFF180098U, },
{ .addr = 0XFF18009CU, },
{ .addr = 0XFF1800A0U, },
{ .addr = 0XFF1800A4U, },
{ .addr = 0XFF1800A8U, },
{ .addr = 0XFF1800ACU, },
{ .addr = 0XFF1800B0U, },
{ .addr = 0XFF1800B4U, },
{ .addr = 0XFF1800B8U, },
{ .addr = 0XFF1800BCU, },
{ .addr = 0XFF1800C0U, },
{ .addr = 0XFF1800C4U, },
{ .addr = 0XFF1800C8U, },
{ .addr = 0XFF1800CCU, },
{ .addr = 0XFF1800D0U, },
{ .addr = 0XFF1800D4U, },
{ .addr = 0XFF1800D8U, },
{ .addr = 0XFF1800DCU, },
{ .addr = 0XFF1800E0U, },
{ .addr = 0XFF1800E4U, },
{ .addr = 0XFF1800E8U, },
{ .addr = 0XFF1800ECU, },
{ .addr = 0XFF1800F0U, },
{ .addr = 0XFF1800F4U, },
{ .addr = 0XFF1800F8U, },
{ .addr = 0XFF1800FCU, },
{ .addr = 0XFF180100U, },
{ .addr = 0XFF180104U, },
{ .addr = 0XFF180108U, },
{ .addr = 0XFF18010CU, },
{ .addr = 0XFF180110U, },
{ .addr = 0XFF180114U, },
{ .addr = 0XFF180118U, },
{ .addr = 0XFF18011CU, },
{ .addr = 0XFF180120U, },
{ .addr = 0XFF180124U, },
{ .addr = 0XFF180128U, },
{ .addr = 0XFF18012CU, },
{ .addr = 0XFF180130U, },
{ .addr = 0XFF180134U, },
{ .addr = 0XFF180138U, },
{ .addr = 0XFF18013CU, },
{ .addr = 0XFF180140U, },
{ .addr = 0XFF180144U, },
{ .addr = 0XFF180148U, },
{ .addr = 0XFF18014CU, },
{ .addr = 0XFF180154U, },
{ .addr = 0XFF180158U, },
{ .addr = 0XFF18015CU, },
{ .addr = 0XFF180160U, },
{ .addr = 0XFF180164U, },
{ .addr = 0XFF180168U, },
{ .addr = 0XFF180170U, },
{ .addr = 0XFF180174U, },
{ .addr = 0XFF180178U, },
{ .addr = 0XFF18017CU, },
{ .addr = 0XFF180180U, },
{ .addr = 0XFF180184U, },
{ .addr = 0XFF180200U, },
{ .addr = 0XFF180204U, },
{ .addr = 0XFF180208U, },
{ .addr = 0XFF18020CU, },
{ .addr = 0XFF180300U, },
{ .addr = 0XFF180304U, },
{ .addr = 0XFF180308U, },
{ .addr = 0XFF18030CU, },
{ .addr = 0XFF180310U, },
{ .addr = 0XFF180314U, },
{ .addr = 0XFF180318U, },
{ .addr = 0XFF18031CU, },
{ .addr = 0XFF180320U, },
{ .addr = 0XFF180324U, },
{ .addr = 0XFF180328U, },
{ .addr = 0XFF18032CU, },
{ .addr = 0XFF180330U, },
{ .addr = 0XFF180334U, },
{ .addr = 0XFF180338U, },
{ .addr = 0XFF18033CU, },
{ .addr = 0XFF180340U, },
{ .addr = 0XFF180344U, },
{ .addr = 0XFF18034CU, },
{ .addr = 0XFF180350U, },
{ .addr = 0XFF180354U, },
{ .addr = 0XFF180358U, },
{ .addr = 0XFF18035CU, },
{ .addr = 0XFF180360U, },
{ .addr = 0XFF180380U, },
{ .addr = 0XFF180390U, },
{ .addr = 0XFF180400U, },
{ .addr = 0XFF180404U, },
{ .addr = 0XFF180408U, },
{ .addr = 0XFF180500U, },
{ .addr = 0XFF180504U, },
{ .addr = 0XFF180508U, },
{ .addr = 0XFF18050CU, },
{ .addr = 0XFF180510U, },
{ .addr = 0XFF180514U, },
{ .addr = 0XFF180518U, },
{ .addr = 0XFF18051CU, },
{ .addr = 0XFF180520U, },
{ .addr = 0XFF180524U, },
/* LPD_SLCR_SECURE */
{ .addr = 0xFF4B0024U, },
{ .addr = 0xFF4B0034U, },
/* CRL_APB */
{ .addr = 0XFF5E0000U, },
{ .addr = 0XFF5E001CU, },
{ .addr = 0XFF5E004CU, },
{ .addr = 0XFF5E0050U, },
{ .addr = 0XFF5E0054U, },
{ .addr = 0XFF5E0058U, },
{ .addr = 0XFF5E005CU, },
{ .addr = 0XFF5E0060U, },
{ .addr = 0XFF5E0064U, },
{ .addr = 0XFF5E0068U, },
{ .addr = 0XFF5E006CU, },
{ .addr = 0XFF5E0070U, },
{ .addr = 0XFF5E0074U, },
{ .addr = 0XFF5E0078U, },
{ .addr = 0XFF5E007CU, },
{ .addr = 0XFF5E0080U, },
{ .addr = 0XFF5E0084U, },
{ .addr = 0XFF5E0088U, },
{ .addr = 0XFF5E0090U, },
{ .addr = 0XFF5E009CU, },
{ .addr = 0XFF5E00A0U, },
{ .addr = 0XFF5E00A4U, },
{ .addr = 0XFF5E00A8U, },
{ .addr = 0XFF5E00ACU, },
{ .addr = 0XFF5E00B0U, },
{ .addr = 0XFF5E00B4U, },
{ .addr = 0XFF5E00B8U, },
{ .addr = 0XFF5E00C0U, },
{ .addr = 0XFF5E00C4U, },
{ .addr = 0XFF5E00C8U, },
{ .addr = 0XFF5E00CCU, },
{ .addr = 0XFF5E00D0U, },
{ .addr = 0XFF5E00D4U, },
{ .addr = 0XFF5E00D8U, },
{ .addr = 0XFF5E00DCU, },
{ .addr = 0XFF5E00E0U, },
{ .addr = 0XFF5E00E4U, },
{ .addr = 0XFF5E00E8U, },
{ .addr = 0XFF5E00FCU, },
{ .addr = 0XFF5E0100U, },
{ .addr = 0XFF5E0104U, },
{ .addr = 0XFF5E0108U, },
{ .addr = 0XFF5E0120U, },
{ .addr = 0XFF5E0124U, },
{ .addr = 0XFF5E0128U, },
{ .addr = 0XFF5E0230U, },
{ .addr = 0XFF5E0234U, },
{ .addr = 0XFF5E0238U, },
{ .addr = 0XFF5E023CU, },
{ .addr = 0XFF5E0240U, },
/* IOU_SCNTRS */
{ .addr = 0XFF260020U, },
{ .addr = 0XFF260008U, },
{ .addr = 0XFF26000CU, },
{ .addr = 0XFF260000U, },
/* RPU */
{ .addr = 0XFF9A0000U, },
{ .addr = 0XFF9A0108U, },
{ .addr = 0XFF9A0208U, },
#ifdef DEBUG_MODE
#if (STDOUT_BASEADDRESS == XPAR_PSU_UART_0_BASEADDR)
{ .addr = 0XFF000034U, },
{ .addr = 0XFF000018U, },
{ .addr = 0XFF000000U, },
{ .addr = 0XFF000004U, }
#endif
#if (STDOUT_BASEADDRESS == XPAR_PSU_UART_1_BASEADDR)
{ .addr = 0XFF010034U, },
{ .addr = 0XFF010018U, },
{ .addr = 0XFF010000U, },
{ .addr = 0XFF010004U, }
#endif
#endif
};
#endif
/*********************************************************************
* Function definitions
********************************************************************/
#ifdef ENABLE_POS
/**
* PmSystemPosDdrRequirementAdd() - Add DDR context saving requirements
* @return XST_SUCCESS if requirements are added, XST_FAILURE otherwise
*/
static s32 PmSystemPosDdrRequirementAdd(void)
{
s32 status = XST_SUCCESS;
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmPosDdrReqs_g); i++) {
PmRequirement* req;
req = PmRequirementGetNoMaster(pmPosDdrReqs_g[i].slave);
if (req == NULL) {
req = PmRequirementAdd(NULL, pmPosDdrReqs_g[i].slave);
if (NULL == req) {
status = XST_FAILURE;
goto done;
}
status = PmCheckCapabilities(req->slave,
pmPosDdrReqs_g[i].caps);
if (XST_SUCCESS != status) {
status = XST_FAILURE;
goto done;
}
req->info |= PM_SYSTEM_USING_SLAVE_MASK;
req->preReq = 0U;
req->currReq = 0U;
req->nextReq = 0U;
req->defaultReq = 0U;
req->latencyReq = 0U;
}
}
done:
return status;
}
#endif
/**
* PmSystemRequirementAdd() - Add requirements of the system
* @return XST_SUCCESS if requirements are added, XST_FAILURE otherwise
*/
s32 PmSystemRequirementAdd(void)
{
s32 status = XST_FAILURE;
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmSystemReqs); i++) {
PmRequirement* req;
req = PmRequirementAdd(NULL, pmSystemReqs[i].slave);
if (NULL == req) {
status = XST_FAILURE;
goto done;
}
status = PmCheckCapabilities(req->slave, pmSystemReqs[i].caps);
if (XST_SUCCESS != status) {
status = XST_FAILURE;
goto done;
}
req->info |= PM_SYSTEM_USING_SLAVE_MASK;
req->preReq = pmSystemReqs[i].caps;
req->currReq = pmSystemReqs[i].caps;
req->nextReq = pmSystemReqs[i].caps;
req->defaultReq = pmSystemReqs[i].caps;
req->latencyReq = MAX_LATENCY;
}
#ifdef ENABLE_POS
/* Add DDR context saving requirements */
status = PmSystemPosDdrRequirementAdd();
#endif
done:
return status;
}
/**
* PmSystemGetRequirement() - Get system-level requirement for given slave
* @slave Slave in question
*
* @return Capabilities of the slave the are required for the system
*/
static u32 PmSystemGetRequirement(const PmSlave* const slave)
{
u32 i;
u32 caps = 0U;
for (i = 0U; i < ARRAY_SIZE(pmSystemReqs); i++) {
if (slave == pmSystemReqs[i].slave) {
caps = pmSystemReqs[i].caps;
break;
}
}
return caps;
}
/**
* PmSystemPrepareForRestart() - Prepare for restarting the master
* @master Master to be restarted
*/
void PmSystemPrepareForRestart(const PmMaster* const master)
{
PmRequirement* req;
/* Change system requirement for DDR to hold it ON while restarting */
req = PmRequirementGetNoMaster(&pmSlaveDdr_g);
if ((NULL != req) && (0U == (PM_CAP_ACCESS & req->currReq))) {
req->currReq |= PM_CAP_ACCESS;
}
/* Change system requirement for PL to hold it ON while restarting */
req = PmRequirementGetNoMaster(&pmSlavePl_g);
if ((NULL != req) && (0U == (PM_CAP_ACCESS & req->currReq))) {
req->currReq |= PM_CAP_ACCESS;
}
return;
}
/**
* PmSystemRestartDone() - Done restarting the master
* @master Master which is restarted
*/
void PmSystemRestartDone(const PmMaster* const master)
{
PmRequirement* req;
u32 caps;
/* Change system requirement for DDR to hold it ON while restarting */
req = PmRequirementGetNoMaster(&pmSlaveDdr_g);
caps = PmSystemGetRequirement(&pmSlaveDdr_g);
if ((NULL != req) && (0U == (PM_CAP_ACCESS & caps))) {
req->currReq &= ~PM_CAP_ACCESS;
}
/* Clear system requirement for PL once restart is done*/
req = PmRequirementGetNoMaster(&pmSlavePl_g);
caps = PmSystemGetRequirement(&pmSlavePl_g);
if ((NULL != req) && (0U == (PM_CAP_ACCESS & caps))) {
req->currReq &= ~PM_CAP_ACCESS;
}
return;
}
#ifdef ENABLE_POS
/**
* PmSystemSaveContext() - Save system context before entering Power Off Suspend
*/
static void PmSystemSaveContext(void)
{
u32 i, start, size;
u32 address = DDR_STORE_BASE;
/* Save FPD context */
PmFpdSaveContext();
/* Save system registers */
for (i = 0U; i < ARRAY_SIZE(pmSystemRegs); i++) {
pmSystemRegs[i].value = XPfw_Read32(pmSystemRegs[i].addr);
}
/* Save system data regions */
for (i = 0U; i < ARRAY_SIZE(pmSystemMemory); i++) {
start = pmSystemMemory[i].startAddr;
size = pmSystemMemory[i].endAddr - start + 1U;
(void)memcpy((void*)address, (void*)start, size);
address += size;
if ((address % 4U) != 0U) {
address += 4U - (address % 4U);
}
}
/* Save TCM data regions */
for (i = 0U; i < ARRAY_SIZE(pmSystemTcmMemory); i++) {
if (TCM_SAVE_MEMORY == pmSystemTcmMemory[i].save) {
u32 reg;
start = pmSystemTcmMemory[i].section.startAddr;
size = pmSystemTcmMemory[i].section.endAddr - start + 1U;
/* Check TCM configuration */
reg = XPfw_Read32(RPU_RPU_GLBL_CNTL);
reg &= RPU_RPU_GLBL_CNTL_TCM_COMB_MASK;
if ((reg != 0U) && (start >= TCM_1A_START_ADDR)) {
start -= TCM_BANK_OFFSET;
}
(void)memcpy((void*)address, (void*)start, size);
address += size;
}
}
}
/**
* PmSystemPosHaltRpu() - Halt RPU0 and RPU1 cores in order to access TCMs
*/
static void PmSystemPosHaltRpu(void)
{
/* Halt RPU0 */
XPfw_RMW32(CRL_APB_RST_LPD_TOP,CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
XPfw_RMW32(RPU_RPU_0_CFG, RPU_RPU_0_CFG_NCPUHALT_MASK,
~RPU_RPU_0_CFG_NCPUHALT_MASK);
XPfw_RMW32(CRL_APB_RST_LPD_TOP, CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
~CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
/* Halt RPU1 */
XPfw_RMW32(CRL_APB_RST_LPD_TOP, CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
XPfw_RMW32(RPU_RPU_1_CFG, RPU_RPU_1_CFG_NCPUHALT_MASK,
~RPU_RPU_1_CFG_NCPUHALT_MASK);
XPfw_RMW32(CRL_APB_RST_LPD_TOP, CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
~CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
}
/**
* PmSystemRestoreContext() - Restore system context after resume from Power Off
* Suspend
*/
static void PmSystemRestoreContext(void)
{
u32 i, start, size;
u32 address = DDR_STORE_BASE;
bool haltRpu = false;
/* Restore system data regions */
for (i = 0U; i < ARRAY_SIZE(pmSystemMemory); i++) {
start = pmSystemMemory[i].startAddr;
size = pmSystemMemory[i].endAddr - start + 1U;
(void)memcpy((void*)start, (void*)address, size);
address += size;
if ((address % 4U) != 0U) {
address += 4U - (address % 4U);
}
}
/* Restore system registers */
for (i = 0U; i < ARRAY_SIZE(pmSystemRegs); i++) {
XPfw_Write32(pmSystemRegs[i].addr, pmSystemRegs[i].value);
}
/* Restore FPD context */
PmFpdRestoreContext();
/* Restore TCM data regions */
for (i = 0U; i < ARRAY_SIZE(pmSystemTcmMemory); i++) {
if (TCM_SAVE_MEMORY == pmSystemTcmMemory[i].save) {
u32 reg;
/* Halt RPU cores if TCM restoring is required */
if (!haltRpu) {
PmSystemPosHaltRpu();
haltRpu = true;
}
start = pmSystemTcmMemory[i].section.startAddr;
size = pmSystemTcmMemory[i].section.endAddr - start + 1U;
/* Check TCM configuration */
reg = XPfw_Read32(RPU_RPU_GLBL_CNTL);
reg &= RPU_RPU_GLBL_CNTL_TCM_COMB_MASK;
if (reg != 0U && start >= TCM_1A_START_ADDR) {
start -= TCM_BANK_OFFSET;
}
memcpy((void*)start, (void*)address, size);
address += size;
}
}
}
/**
* PmSystemSetPosRequirement() - Set Power Off Susped slave requirement
* @slave Slave for which requirement is set
* @caps Capability to be set
*
* @return XST_SUCCESS if slave capability is set, XST_FAILURE otherwise
*/
static s32 PmSystemSetPosRequirement(const PmSlave* const slave, u32 caps)
{
u32 i;
s32 status = XST_FAILURE;
for (i = 0U; i < ARRAY_SIZE(pmSystemReqs); i++) {
if (slave == pmSystemReqs[i].slave) {
pmSystemReqs[i].posCaps = caps;
status = XST_SUCCESS;
break;
}
}
return status;
}
/**
* PmSystemTcmSetSave() - Set save flag for TCM memory region
* @baseAddress Base address of TCM memory region
* @save Save flag
*/
static void PmSystemTcmSetSave(u32 baseAddress, u32 save)
{
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmSystemTcmMemory); i++) {
if (baseAddress == pmSystemTcmMemory[i].section.startAddr) {
pmSystemTcmMemory[i].save = save;
break;
}
}
}
/**
* PmSystemCheckTcm() - Mark TCM memory regions that needs to be saved/restored
* during Power Off Suspend
*/
static void PmSystemCheckTcm(void)
{
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmSystemTcmSlaves); i++) {
PmSlave* slave = &pmSystemTcmSlaves[i]->sram.slv;
PmRequirement* req = slave->reqs;
bool save = false;
/* Check if TCM slave has requirement different from 0 */
while (NULL != req) {
PmMaster* master = req->master;
if (NULL != master) {
if (PmMasterIsSuspended(master)) {
if (0U != req->currReq) {
save = true;
break;
}
} else if (PmMasterIsSuspending(master)) {
if (0U != req->nextReq) {
save = true;
break;
}
} else {
}
}
req = req->nextMaster;
}
if (true == save) {
PmSystemSetPosRequirement(slave, PM_CAP_ACCESS);
PmSystemTcmSetSave(pmSystemTcmSlaves[i]->base,
TCM_SAVE_MEMORY);
} else {
PmSystemSetPosRequirement(slave, 0U);
PmSystemTcmSetSave(pmSystemTcmSlaves[i]->base,
TCM_SKIP_MEMORY);
}
}
}
/**
* PmSystemDetectPowerOffSuspend() - Detecet whether Power Off Suspend state may
* be entered
* @master Suspending master
*
* @return True if master is last suspending in the system and Extern
* device is unique wakeup source in the system, false otherwise
*/
bool PmSystemDetectPowerOffSuspend(const PmMaster* const master)
{
bool cond = false;
cond = PmMasterIsLastSuspending(master);
if (false == cond) {
goto done;
}
cond = PmMasterIsUniqueWakeup(&pmSlaveExternDevice_g);
done:
return cond;
}
/**
* PmSystemPosPrepareDdrCaps() - Set slave capabilities required for DDR
* context saving
*
* @return XST_SUCCESS if capabilities are set, failure code otherwise
*/
static s32 PmSystemPosPrepareDdrCaps(void)
{
s32 status = XST_SUCCESS;
u32 i;
/* Set capabilities required for saving DDR context */
for (i = 0U; i < ARRAY_SIZE(pmPosDdrReqs_g); i++) {
PmRequirement* req;
u32 caps = pmPosDdrReqs_g[i].caps;
req = PmRequirementGetNoMaster(pmPosDdrReqs_g[i].slave);
if (NULL != req) {
if (0U == (caps & req->currReq)) {
status = PmRequirementUpdate(req,
caps | req->currReq);
if (XST_SUCCESS != status) {
goto done;
}
}
} else {
status = XST_FAILURE;
goto done;
}
}
done:
return status;
}
/**
* PmSystemPreparePowerOffSuspend() - Prepare system for entering Power Off
* Suspend state
*
* @return XST_SUCCESS if all Power Off Suspend system slave capabilities
* are set, failure code otherwise
*/
s32 PmSystemPreparePowerOffSuspend(void)
{
s32 status = XST_SUCCESS;
u32 i;
pmSystem.suspendType = PM_SUSPEND_TYPE_POWER_OFF;
/* Mark used TCM memory regions */
PmSystemCheckTcm();
/* Set Power Off Suspend capability for every system slave */
for (i = 0U; i < ARRAY_SIZE(pmSystemReqs); i++) {
PmRequirement* req;
u32 caps = pmSystemReqs[i].posCaps;
req = PmRequirementGetNoMaster(pmSystemReqs[i].slave);
if (NULL != req) {
if (caps != req->currReq) {
status = PmRequirementUpdate(req, caps);
if (XST_SUCCESS != status) {
goto done;
}
}
} else {
status = XST_FAILURE;
goto done;
}
}
/* Set DDR context saving slave capabilities */
status = PmSystemPosPrepareDdrCaps();
done:
return status;
}
/**
* PmSystemPosFinalizeDdrCaps() - Release slave capabilities required for DDR
* context saving
*
* @return XST_SUCCESS if capabilities are released, failure code otherwise
*/
static s32 PmSystemPosFinalizeDdrCaps(void)
{
s32 status = XST_SUCCESS;
u32 i;
/* Set capabilities required for DDR context saving to 0 */
for (i = 0U; i < ARRAY_SIZE(pmPosDdrReqs_g); i++) {
PmRequirement* req;
req = PmRequirementGetNoMaster(pmPosDdrReqs_g[i].slave);
if (NULL != req) {
if (0U != req->currReq) {
status = PmRequirementUpdate(req, 0U);
if (XST_SUCCESS != status) {
goto done;
}
}
} else {
status = XST_FAILURE;
goto done;
}
}
done:
return status;
}
/**
* PmSystemFinalizePowerOffSuspend() - Finalize entering Power Off Suspend state
*
* @return This function will not return in case of entering Power Off
* Suspend, failure code otherwise
*/
s32 PmSystemFinalizePowerOffSuspend(void)
{
u32 i;
s32 status;
PmRequirement* req;
/* Save system context */
PmSystemSaveContext();
/* Release all requirements for all masters in system */
status = PmMasterReleaseAll();
if (XST_SUCCESS != status) {
goto done;
}
/* Prepare system requirements for entering Power Off Suspend */
for (i = 0U; i < ARRAY_SIZE(pmSystemReqs); i++) {
u32 caps = 0U;
/* Put DDR in retention state during Power Off Suspend */
if (pmSystemReqs[i].slave == &pmSlaveDdr_g) {
caps |= PM_CAP_CONTEXT;
/* Save DDR clocks settings */
PmClockSave(&pmSlaveDdr_g.node);
}
req = PmRequirementGetNoMaster(pmSystemReqs[i].slave);
if (NULL != req) {
if (caps != req->currReq) {
status = PmRequirementUpdate(req, caps);
if (XST_SUCCESS != status) {
goto done;
}
}
} else {
status = XST_FAILURE;
goto done;
}
}
/* Save DDR context */
status = PmHookPosSaveDdrContext();
if (XST_SUCCESS != status) {
goto done;
}
/* Release DDR context saving slave capabilities */
status = PmSystemPosFinalizeDdrCaps();
done:
return status;
}
/**
* PmSystemResumePowerOffSuspend() - Resume from Power Off Suspend state
*
* @return XST_SUCCESS if system is resumed properly, error code otherwise
*/
s32 PmSystemResumePowerOffSuspend(void)
{
s32 status;
u32 i;
PmRequirement* req;
/* Wait for FSBL to start and get boot type */
do {
i = XPfw_Read32(PMU_GLOBAL_GLOBAL_GEN_STORAGE2);
} while (0U == i);
/* Clear Gen Storage register so it can be used later in system */
XPfw_Write32(PMU_GLOBAL_GLOBAL_GEN_STORAGE2, 0U);
/* DDR context restore */
status = PmHookRestoreDdrContext();
if (status != XST_SUCCESS) {
goto done;
}
/* Resume DDR operation */
status = PmDdrPowerOffSuspendResume();
if (status != XST_SUCCESS) {
goto done;
}
/* System context restore */
PmSystemRestoreContext();
pmSystem.suspendType = PM_SUSPEND_TYPE_REGULAR;
/* Update state of slave nodes */
for (i = 0U; i < pmNodeClassSlave_g.bucketSize; i++) {
PmSlave* slave = pmNodeClassSlave_g.bucket[i]->derived;
slave->node.currState = slave->slvFsm->statesCnt - 1U;
status = PmUpdateSlave(slave);
if (status != XST_SUCCESS) {
goto done;
}
}
/* Update state of proc nodes */
for (i = 0U; i < pmNodeClassProc_g.bucketSize; i++) {
PmProc* proc = pmNodeClassProc_g.bucket[i]->derived;
status = PmProcSleep(proc);
if (status != XST_SUCCESS) {
goto done;
}
}
/* Update state of power nodes */
for (i = 0U; i < pmNodeClassPower_g.bucketSize; i++) {
PmPower* power = pmNodeClassPower_g.bucket[i]->derived;
power->node.currState = PM_PWR_STATE_ON;
if (power->useCount == 0U) {
status = PmPowerDown(power);
if (status != XST_SUCCESS) {
goto done;
}
}
}
/* Wake masters that have external node as wake source */
status = PmExternWakeMasters();
if (status != XST_SUCCESS) {
goto done;
}
/* Set default value for system requirements */
for (i = 0U; i < ARRAY_SIZE(pmSystemReqs); i++) {
u32 caps = pmSystemReqs[i].caps;
req = PmRequirementGetNoMaster(pmSystemReqs[i].slave);
if (NULL != req) {
if (req->currReq != caps) {
status = PmRequirementUpdate(req, caps);
if (XST_SUCCESS != status) {
goto done;
}
}
} else {
status = XST_FAILURE;
goto done;
}
}
/* Release DDR context saving slave capabilities */
status = PmSystemPosFinalizeDdrCaps();
done:
return status;
}
#endif
u32 PmSystemSuspendType(void)
{
return pmSystem.suspendType;
}
void PmSystemSetSuspendType(u32 type)
{
pmSystem.suspendType = type;
}
#endif
<file_sep>/python_drivers/qutag_examples/qutag-GetHistogram-multiple_example.py
# Example for using the Coincidence Counters with python + quTAG
#
# Author: qutools GmbH
# Last edited: Mai 2020
#
# Tested with python 3.7 (32bit), numpy-1.13.3 and Windows 7 (64bit)
#
# This is demo code. Use at your own risk. No warranties.
#
# It may be used and modified with no restriction; raw copies as well as
# modified versions may be distributed without limitation.
# for plotting
import matplotlib.pyplot as plt
import matplotlib.animation as animation
from matplotlib import style
# for sleep
import time
# This code shows how to get histograms from a quTAG connected via USB.
# Additionally we are plotting the data with matplotlib.
# Import the python wrapper which wraps the DLL functions.
# The wrapper should be in the same directory like this code in the folder '..\QUTAG-V1.5.0\userlib\src'.
try:
import QuTAG
except:
print("Time Tagger wrapper QuTAG.py is not in the search path.")
# initialize device
qutag = QuTAG.QuTAG()
# Choose our start and stop channels for both histograms
ch_start_1 = 3
ch_stop_1 = 2
ch_start_2 = 3
ch_stop_2 = 1
ch_start_3 = 2
ch_stop_3 = 1
ch_start_4 = 4
ch_stop_4 = 1
### Let's add/remove (True/False) a histogram with specified start and stop channels.
# All time differences beween a start and the first following stop event will contribute to the histogram.
### This function also enables the calculation of start stop histograms ( qutag.enableStartStop(True) ). When enabled, all incoming events contribute to the histograms.
# When disabled ( qutag.enableStartStop(False) ), all corresponding functions are unavailable. The function implicitly clears the histograms.
qutag.addHistogram(ch_start_1,ch_stop_1,True)
# Now add the other histograms
qutag.addHistogram(ch_start_2,ch_stop_2,True)
qutag.addHistogram(ch_start_3,ch_stop_3,True)
qutag.addHistogram(ch_start_4,ch_stop_4,True)
# Let's set parameters for the internally generated start stop histograms: bin width in ps & bin count (range = 2 ... 1000000, default = 10000)
# If the function is not called, default values are in place. When the function is called, all collected histogram data are cleared.
qutag.setHistogramParams(1,4000)
### Let's freeze the buffers, empty both histograms and start both histograms recording by defreezing the buffers at the same time.
# Freeze buffers:
qutag.freezeBuffers(True)
### The function freezeBuffers(bool) can be used to freeze the internal buffers, allowing to retrieve multiple histograms with the same integration time.
# When frozen, no more events are added to the built-in histograms and timestamp buffer. The coincidence counters are not affected.
# Initially, the buffers are not frozen. All types of histograms calculated by software are affected.
# Empty histograms:
# Clear the data after retrieving the histograms with True, the next two lines simply clear the histograms successively
qutag.getHistogram(ch_start_1,ch_stop_1,True)
qutag.getHistogram(ch_start_2,ch_stop_2,True)
qutag.getHistogram(ch_start_3,ch_stop_3,True)
qutag.getHistogram(ch_start_4,ch_stop_4,True)
# Now the histograms are empty, let's start recording by defreezing the buffers
qutag.freezeBuffers(False)
# Wait a second for accumulating the data
time.sleep(1)
# Freeze the buffers to stop recording and retrieve the histograms successively
qutag.freezeBuffers(True)
### Get the histograms
rc_1 = qutag.getHistogram(ch_start_1,ch_stop_1,True)
rc_2 = qutag.getHistogram(ch_start_2,ch_stop_2,True)
rc_3 = qutag.getHistogram(ch_start_3,ch_stop_3,True)
rc_4 = qutag.getHistogram(ch_start_4,ch_stop_4,True)
# Returns an array with:
# data array with at least binCount elements, see plotting
# Total number of time differences in the histogram
# Number of time diffs that were smaller than the smallest histogram bin.
# Number of time diffs that were bigger than the biggest histogram bin.
# Number of events on the start channel contributing to the histogram.
# Number of events on the stop channel contributing to the histogram.
# Total exposure time for the histogram: the time difference between the first and the last event that contribute to the histogram. In timebase units.
print("Counts inside the histogram: ", rc_1[1], "| Counts too Small: ", rc_1[2], "| Counts too Large: ", rc_1[3], "| starts: ", rc_1[4], "| stops: ", rc_1[5], "| max exposure time: ", rc_1[6]/1000, "ns")
print("Counts inside the histogram: ", rc_2[1], "| Counts too Small: ", rc_2[2], "| Counts too Large: ", rc_2[3], "| starts: ", rc_2[4], "| stops: ", rc_2[5], "| max exposure time: ", rc_2[6]/1000, "ns")
print("Counts inside the histogram: ", rc_3[1], "| Counts too Small: ", rc_3[2], "| Counts too Large: ", rc_3[3], "| starts: ", rc_3[4], "| stops: ", rc_3[5], "| max exposure time: ", rc_3[6]/1000, "ns")
print("Counts inside the histogram: ", rc_4[1], "| Counts too Small: ", rc_4[2], "| Counts too Large: ", rc_4[3], "| starts: ", rc_4[4], "| stops: ", rc_4[5], "| max exposure time: ", rc_4[6]/1000, "ns")
# If the counts are too small or too large, individual channels can be delayed by the following function. Put it of course above the code for recording.
'''
# Create an array for the channel delays with zero ps for all channels.
import numpy as np
channelDelays = np.zeros(int(8), dtype=np.int32)
# Change the array for one channel in ps, e.g.: [0,0,1670,0,0,0,0,0]
# The range for the delay is -100ns ... 100ns
channelDelays[2] = 1670
# Then we set all the channel delays via the created array:
qutag.setChannelDelays(channelDelays)
'''
# Plotting with mathplotlib
style.use('fivethirtyeight')
fig = plt.figure()
fig.set_size_inches(10,7)
ax1 = fig.add_subplot(1,1,1)
plt.cla() # clear old plotting data
# plot the datapoints
plt.plot(rc_1[0], label='Histogram Ch: %i-%i' %(ch_start_1, ch_stop_1))
plt.plot(rc_2[0], label='Histogram Ch: %i-%i' %(ch_start_2, ch_stop_2))
plt.plot(rc_3[0], label='Histogram Ch: %i-%i' %(ch_start_3, ch_stop_3))
plt.plot(rc_4[0], label='Histogram Ch: %i-%i' %(ch_start_4, ch_stop_4))
ax1.set_title('quTAG Histograms')
plt.xlabel('Time delta [ps]')
plt.ylabel('Events [ ]')
handles, labels = ax1.get_legend_handles_labels()
ax1.legend(handles, labels)
plt.pause(0.05)
# Disconnect the device and free the USB connection.
qutag.deInitialize()
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_crc.h
/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPFW_CRC_H_
#define XPFW_CRC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xpfw_default.h"
#ifdef ENABLE_IPI_CRC
u32 XPfw_CalculateCRC(u32 BufAddr, u32 BufSize);
#endif /* ENABLE_IPI_CRC */
#ifdef __cplusplus
}
#endif
#endif /* XPFW_CRC_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_domain_iso.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_DOMAIN_ISO_H
#define XPM_DOMAIN_ISO_H
#include "xpm_node.h"
#include "xpm_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define FALSE_VALUE (0U)
#define TRUE_VALUE (1U)
#define FALSE_IMMEDIATE (2U) /* Remove isolation immediately */
#define TRUE_PENDING_REMOVE (3U) /* Set isolation, but pending removal */
typedef struct XPm_Iso {
XPm_Node Node; /**< Node: Node base class */
u32 Mask;
u8 Polarity;
u32 DependencyNodeHandles[2];
}XPm_Iso;
/* Polarity */
typedef enum {
PM_ACTIVE_LOW,
PM_ACTIVE_HIGH,
}XPm_IsoPolarity;
/* Isolation states */
typedef enum {
PM_ISOLATION_ON,
PM_ISOLATION_OFF,
PM_ISOLATION_REMOVE_PENDING,
}XPm_IsoStates;
#define ISOID(x) \
NODEID(XPM_NODECLASS_ISOLATION, XPM_NODESUBCL_ISOLATION, XPM_NODETYPE_ISOLATION, x)
XStatus XPmDomainIso_Control(u32 IsoIdx, u32 Enable);
XStatus XPmDomainIso_ProcessPending(u32 PowerDomainId);
#ifdef __cplusplus
}
#endif
#endif /* XPM_DOMAIN_ISO_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/resetps_v1_3/src/xresetps_g.c
/******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xresetps_g.c
* @addtogroup xresetps_v1_3
* @{
*
* This file contains a table that specifies the configuration of the reset
* controller devices in the system. Each device should have an entry in the
* table.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------
* 1.00 cjp 09/05/17 First release
* 1.2 cjp 04/27/18 Updated for clockps interdependency
* 1.2 sd 07/20/18 Fixed Doxygen warnings
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xresetps.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Prototypes ******************************/
/**
* This table contains configuration information for each reset controller
* device in the system.
*
* Note:
* This is a dummy instance since reset system doesnot have a dedicated
* controller
*/
XResetPs_Config XResetPs_ConfigTable[XPAR_XRESETPS_NUM_INSTANCES] = {
{
(u16)XPAR_XRESETPS_DEVICE_ID,
}
};
/** @} */
<file_sep>/python_drivers/tdc_detect_pulse_test.py
# -*- coding: utf-8 -*-
"""
Created on Tue Jul 21 11:38:33 2020
@author: tianlab01
"""
import QuTAG
threshold_voltage = 0.0 #100mV
device = QuTAG.QuTAG()
#device.enableChannels((1,2,3,4))
device.enableChannels((2,3,4))
#Set threshold voltage on all channels
device.setSignalConditioning(1, 3, 1, threshold_voltage)
device.setSignalConditioning(2, 3, 1, threshold_voltage)
device.setSignalConditioning(3, 3, 1, threshold_voltage)
device.setSignalConditioning(4, 3, 1, threshold_voltage)
print("Searching for timestamp on all channels")
timestamp_list = []
while(1):
#Check the data loss
try:
d_loss = device.getDataLost()
if(d_loss != 0):
print("Warning, data loss was " + str(d_loss) + ", some timestamps have been missed")
#Readback timestamps from the device
t_s = device.getLastTimestamps(True)
#If we didnt get any timestamps
if(t_s[2] == 0):
#print("Empty")
continue#keep going
for i in range(0, t_s[2]):
#If we find a timestamp of this channel
if(t_s[1][i] != 104):
ret_val = t_s[0][i]
timestamp_list.append(ret_val)
print("Timestamp found for channel #" + str(t_s[1][i]) + ", timestamp was: " + str(ret_val))
except KeyboardInterrupt:
print("TDC interrupted by user, exiting...")
break
device.deInitialize()
print("Timestamp list was: " + str(timestamp_list))
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_default.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPFW_DEFAULT_H_
#define XPFW_DEFAULT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xpfw_config.h"
#include "xpfw_util.h"
#include "xpfw_debug.h"
/* BSP Headers */
#include "xil_io.h"
#include "xil_types.h"
#include "mb_interface.h"
#include "xstatus.h"
/* REGDB Headers */
#include "pmu_local.h"
#include "pmu_iomodule.h"
#include "pmu_global.h"
#include "ipi.h"
#include "uart0.h"
#include "uart1.h"
#include "crl_apb.h"
#include "lpd_slcr.h"
#include "rtc.h"
/* Base address of the IOU_SLCR module */
#define IOU_SLCR_BASE 0xFF180000U
#define IOU_SLCR_MIO_PIN_34_OFFSET 0x00000088U
#define IOU_SLCR_MIO_PIN_35_OFFSET 0x0000008CU
#define IOU_SLCR_MIO_PIN_36_OFFSET 0x00000090U
#define IOU_SLCR_MIO_PIN_37_OFFSET 0x00000094U
#define IOU_SLCR_CTRL ( IOU_SLCR_BASE + (u32)(0x600U) )
#define SLVERR_MASK (u32)(0x1U)
/* XPPU SINK Registers */
#define XPPU_SINK_BASE_ADDR 0xFF9CFF00U
#define XPPU_SINK_ERR_CTRL (XPPU_SINK_BASE_ADDR + 0xECU)
/* BBRAM registers */
#define BBRAM_BASE_ADDR 0xFFCD0000U
#define BBRAM_SLVERR_REG (BBRAM_BASE_ADDR + 0x34U)
/* RAM address used for scrubbing */
#define PARAM_RAM_LOW_ADDRESS 0Xffdc0000U
#define PARAM_RAM_HIGH_ADDRESS 0Xffdcff00U
/* RAM base address for general usage */
#define PMU_RAM_BASE_ADDR 0Xffdc0000U
/* Register Access Macros */
#define XPfw_Write32(Addr, Value) Xil_Out32((Addr), (Value))
#define XPfw_Read32(Addr) Xil_In32((Addr))
#define XPfw_RMW32 XPfw_UtilRMW
#define ARRAYSIZE(x) (u32)(sizeof(x)/sizeof(x[0]))
/* Custom Flags */
#define MASK_ALL 0XffffffffU
#define ENABLE_ALL 0XffffffffU
#define ALL_HIGH 0XffffffffU
#define FLAG_ALL 0XffffffffU
#define MASK32_ALL_HIGH ((u32)0xFFFFFFFFU)
#define MASK32_ALL_LOW ((u32)0x0U)
#define YES 0x01U
#define NO 0x00U
#define XPFW_ACCESS_ALLOWED 0x01U
#define XPFW_ACCESS_DENIED 0x00U
/*
* time in ms for checking psu init completion by FSBL
*/
#define CHECK_FSBL_COMPLETION 100U
#define FSBL_COMPLETION 1U
#define IPI_CRC_ERROR_OCCURRED 0x1U
#define HW_EXCEPTION_RECEIVED 0x2U
/* Error code to be written for RPU_run mode error */
#define RPU_RUN_MODE_ERROR 0x04U
/* Handler Table Structure */
typedef void (*VoidFunction_t)(void);
struct HandlerTable{
u32 Mask;
VoidFunction_t Handler;
};
#ifdef __cplusplus
}
#endif
#endif /* XPFW_DEFAULT_H_ */
<file_sep>/c_drivers/drivers/uart.c
//System drivers
#include "xuartps.h"
#include "xparameters.h"
#include "xplatform_info.h"
#include "xuartps.h"
#include "xil_exception.h"
#ifdef XPAR_INTC_0_DEVICE_ID
#include "xintc.h"
#else
#include "xscugic.h"
#endif
//Header file for this driver
#include "uart.h"
/************************** Constant Definitions **************************/
/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
#ifdef XPAR_INTC_0_DEVICE_ID
#define INTC XIntc
#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
#define UART_INT_IRQ_ID XPAR_INTC_0_UARTPS_0_VEC_ID
#else
#define INTC XScuGic
#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#define UART_INT_IRQ_ID XPAR_XUARTPS_0_INTR
#endif
XUartPs Uart_PS; /* Instance of the UART Device */
INTC InterruptController; /* Instance of the Interrupt Controller */
//Function prototypes
int uart_SetupInterruptSystem(INTC *IntcInstancePtr,
XUartPs *UartInstancePtr,
u16 UartIntrId);
void uart_handler(void *CallBackRef, u32 Event, unsigned int EventData);
/////////////////Buffer Definitions/////////////////////
#define REC_BUFF_SIZE 1000
u8 uart_rec_buff[REC_BUFF_SIZE];
volatile uint32_t buff_write_index;//Location where next received byte will go
volatile uint32_t buff_read_index;//Location of next byte to be read out of buffer
volatile uint32_t buff_cnt;//Number of bytes in the buffer
u8 rec_buff[10];//Buffer for the interrupt handler to use
////////////////////////////////////////////////////////
void uart_clear_buffer()
{
buff_write_index = 0;
buff_read_index = 0;
buff_cnt = 0;
}
//Used to initialize in interrupt mode
int uart_UartPsIntrExample(INTC *IntcInstPtr, XUartPs *UartInstPtr,
u16 DeviceId, u16 UartIntrId)
{
int Status;
XUartPs_Config *Config;
u32 IntrMask;
#ifndef TESTAPP_GEN
if (XGetPlatform_Info() == XPLAT_ZYNQ_ULTRA_MP) {
#ifdef XPAR_XUARTPS_1_DEVICE_ID
DeviceId = XPAR_XUARTPS_1_DEVICE_ID;
#endif
}
#endif
/*
* Initialize the UART driver so that it's ready to use
* Look up the configuration in the config table, then initialize it.
*/
Config = XUartPs_LookupConfig(DeviceId);
if (NULL == Config) {
return XST_FAILURE;
}
Status = XUartPs_CfgInitialize(UartInstPtr, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Check hardware build */
Status = XUartPs_SelfTest(UartInstPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the UART to the interrupt subsystem such that interrupts
* can occur. This function is application specific.
*/
Status = uart_SetupInterruptSystem(IntcInstPtr, UartInstPtr, UartIntrId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Setup the handlers for the UART that will be called from the
* interrupt context when data has been sent and received, specify
* a pointer to the UART driver instance as the callback reference
* so the handlers are able to access the instance data
*/
XUartPs_SetHandler(UartInstPtr, (XUartPs_Handler)uart_handler, UartInstPtr);
/*
* Enable the interrupt of the UART so interrupts will occur, setup
* a local loopback so data that is sent will be received.
*/
IntrMask =
XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY | XUARTPS_IXR_FRAMING |
XUARTPS_IXR_OVER | XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXFULL |
XUARTPS_IXR_RXOVR;
if (UartInstPtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
IntrMask |= XUARTPS_IXR_RBRK;
}
XUartPs_SetInterruptMask(UartInstPtr, IntrMask);
XUartPs_SetRecvTimeout(UartInstPtr, 8);
XUartPs_SetOperMode(UartInstPtr, XUARTPS_OPER_MODE_NORMAL);
/*
* Disable RX timeout
*/
XUartPs_SetRecvTimeout(UartInstPtr, 0);
/*
* Set RX FIFO threshold to 1
*/
XUartPs_SetFifoThreshold(UartInstPtr, 1);
//Reset the receive callback
//XUartPs_Recv(&Uart_PS, rec_buff, 0);
XUartPs_Recv(&Uart_PS, rec_buff, 1);
return XST_SUCCESS;
}
uint8_t uart_get_buffer_byte()
{
//Don't do anything if the buffer is empty
if(buff_cnt == 0)
{
return 0;
}
buff_cnt--;//Removing a byte from buffer
uint8_t ret_val = uart_rec_buff[buff_read_index];
buff_read_index++;
if(buff_read_index >= REC_BUFF_SIZE)
{
buff_read_index = 0;
}
return ret_val;
}
uint32_t uart_get_buffer_size()
{
return buff_cnt;
}
//returns 0 on success
uint8_t uart_init_polled()
{
int Status;
XUartPs_Config *Config;
/*
* Initialize the UART driver so that it's ready to use.
* Look up the configuration in the config table, then initialize it.
*/
Config = XUartPs_LookupConfig(UART_DEVICE_ID);
if (NULL == Config) {
return XST_FAILURE;
}
Status = XUartPs_CfgInitialize(&Uart_PS, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Check hardware build. */
Status = XUartPs_SelfTest(&Uart_PS);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
uint8_t uart_init_interrupt()
{
buff_write_index = 0;
buff_read_index = 0;
buff_cnt = 0;
return uart_UartPsIntrExample(&InterruptController, &Uart_PS,
UART_DEVICE_ID, UART_INT_IRQ_ID);
}
//Sends a single byte
//Returns 0 on success
uint8_t uart_send_byte(uint8_t data_byte)
{
//Wait until we're done sending
while (XUartPs_IsSending(&Uart_PS));
//Send one byte
if(XUartPs_Send(&Uart_PS, &data_byte, 1) != 1)
{
return XST_FAILURE;
}
return XST_SUCCESS;
}
//Receives num_bytes into a buffer (blocking)
//Returns number of bytes written into buffer
uint32_t uart_receive_bytes(uint32_t num_bytes, uint8_t * buff)
{
uint32_t bytes_got = 0;
while (bytes_got < num_bytes) {
bytes_got +=
XUartPs_Recv(&Uart_PS, buff + bytes_got,
(num_bytes - bytes_got));
}
return bytes_got;
}
//Interrupt handler
void uart_handler(void *CallBackRef, u32 Event, unsigned int EventData)
{
//Disable interrupts
//XScuGic_Disable(&InterruptController, UART_INT_IRQ_ID);
/* All of the data has been sent */
if (Event == XUARTPS_EVENT_SENT_DATA) {
//TotalSentCount = EventData;
}
/* All of the data has been received */
if (Event == XUARTPS_EVENT_RECV_DATA) {
//TotalReceivedCount = EventData;
//Move received data into buffer here
uart_rec_buff[buff_write_index] = rec_buff[0];
buff_write_index++;
buff_cnt++;//Increase number of bytes in buffer
//If we just went over the end of the buffer then loop around
if(buff_write_index >= REC_BUFF_SIZE)
{
buff_write_index = 0;
}
//Reset the receive callback
//XUartPs_Recv(&Uart_PS, rec_buff, 0);
//Flush the receive buffer
XUartPs_Recv(&Uart_PS, rec_buff, 1);
}
/*
* Data was received, but not the expected number of bytes, a
* timeout just indicates the data stopped for 8 character times
*/
if (Event == XUARTPS_EVENT_RECV_TOUT) {
//TotalReceivedCount = EventData;
print("Error, receive timeout!");
}
/*
* Data was received with an error, keep the data but determine
* what kind of errors occurred
*/
if (Event == XUARTPS_EVENT_RECV_ERROR) {
//TotalReceivedCount = EventData;
//TotalErrorCount++;
print("Error, receive error!");
}
/*
* Data was received with an parity or frame or break error, keep the data
* but determine what kind of errors occurred. Specific to Zynq Ultrascale+
* MP.
*/
if (Event == XUARTPS_EVENT_PARE_FRAME_BRKE) {
//TotalReceivedCount = EventData;
//TotalErrorCount++;
}
/*
* Data was received with an overrun error, keep the data but determine
* what kind of errors occurred. Specific to Zynq Ultrascale+ MP.
*/
if (Event == XUARTPS_EVENT_RECV_ORERR) {
//TotalReceivedCount = EventData;
//TotalErrorCount++;
}
//XScuGic_Enable(&InterruptController, UART_INT_IRQ_ID);
}
int uart_SetupInterruptSystem(INTC *IntcInstancePtr,
XUartPs *UartInstancePtr,
u16 UartIntrId)
{
int Status;
#ifdef XPAR_INTC_0_DEVICE_ID
#ifndef TESTAPP_GEN
/*
* Initialize the interrupt controller driver so that it's ready to
* use.
*/
Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
/*
* Connect the handler that will be called when an interrupt
* for the device occurs, the handler defined above performs the
* specific interrupt processing for the device.
*/
Status = XIntc_Connect(IntcInstancePtr, UartIntrId,
(XInterruptHandler) XUartPs_InterruptHandler, UartInstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#ifndef TESTAPP_GEN
/*
* Start the interrupt controller so interrupts are enabled for all
* devices that cause interrupts.
*/
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
/*
* Enable the interrupt for uart
*/
XIntc_Enable(IntcInstancePtr, UartIntrId);
#ifndef TESTAPP_GEN
/*
* Initialize the exception table.
*/
Xil_ExceptionInit();
/*
* Register the interrupt controller handler with the exception table.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XIntc_InterruptHandler,
IntcInstancePtr);
#endif
#else
#ifndef TESTAPP_GEN
XScuGic_Config *IntcConfig; /* Config for interrupt controller */
/* Initialize the interrupt controller driver */
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the interrupt controller interrupt handler to the
* hardware interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler,
IntcInstancePtr);
#endif
/*
* Connect a device driver handler that will be called when an
* interrupt for the device occurs, the device driver handler
* performs the specific interrupt processing for the device
*/
Status = XScuGic_Connect(IntcInstancePtr, UartIntrId,
(Xil_ExceptionHandler) XUartPs_InterruptHandler,
(void *) UartInstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Enable the interrupt for the device */
XScuGic_Enable(IntcInstancePtr, UartIntrId);
#endif
#ifndef TESTAPP_GEN
/* Enable interrupts */
Xil_ExceptionEnable();
#endif
return XST_SUCCESS;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/standalone_v7_2/src/arm/ARMv8/64bit/armclang/Makefile
###############################################################################
# Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
###############################################################################
include config.make
AS=$(ASSEMBLER)
COMPILER=$(COMPILER)
ARCHIVER=$(ARCHIVER)
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
COBJS = $(addsuffix .o, $(basename $(wildcard *.c)))
AOBJS1 = asm_vectors.o
AOBJS2 = translation_table.o
AOBJS3 = boot.o
OBJS = $(COBJS) $(AOBJS1) $(AOBJS2) $(AOBJS3)
ASOURCES1 = asm_vectors.S
ASOURCES2 = translation_table.S
ASOURCES3 = boot.S
OBJECTS = $(OBJS)
libs: banner standalone_libs clean
$(AOBJS1): $(ASOURCES1)
ifeq ($(findstring asm_vectors.S,$(wildcard *.S)),asm_vectors.S)
${COMPILER} $(INCLUDES) --target=aarch64-arm-none-eabi -E -o asm_vectors_post.s asm_vectors.S
endif
${AS} --cpu=8-A.64 --fpu=fp-armv8 -o asm_vectors.o asm_vectors_post.s
$(AOBJS2): $(ASOURCES2)
ifeq ($(findstring translation_table.S,$(wildcard *.S)),translation_table.S)
${COMPILER} $(INCLUDES) --target=aarch64-arm-none-eabi -E -o translation_table_post.s translation_table.S
endif
${AS} --cpu=8-A.64 --fpu=fp-armv8 -o translation_table.o translation_table_post.s
$(AOBJS3): $(ASOURCES3)
ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S)
${COMPILER} $(INCLUDES) --target=aarch64-arm-none-eabi -E -o boot_post.s boot.S
endif
${AS} --cpu=8-A.64 --fpu=fp-armv8 -o boot.o boot_post.s
%.o: %.c
${COMPILER} -c $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling standalone"
standalone_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: standalone_includes
standalone_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_cpmdomain.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_CPMDOMAIN_H_
#define XPM_CPMDOMAIN_H_
#include "xpm_powerdomain.h"
#include "xpm_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* CPM domain node class.
*/
typedef struct XPm_CpmDomain {
XPm_PowerDomain Domain; /**< Power domain node base class */
u32 CpmSlcrBaseAddr; /**< CPM SLCR Base Address */
u32 CpmSlcrSecureBaseAddr; /**< CPM SLCR Secure base address */
u32 CpmPcsrBaseAddr; /**< CPM PCSR Base address */
u32 CpmCrCpmBaseAddr; /**< CPM CRCPM Base address */
} XPm_CpmDomain;
/************************** Function Prototypes ******************************/
XStatus XPmCpmDomain_Init(XPm_CpmDomain *CpmDomain, u32 Id, u32 BaseAddress,
XPm_Power *Parent, u32 *OtherBaseAddresses,
u32 OtherBaseAddressesCnt);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_CPMDOMAIN_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pslpdomain.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_common.h"
#include "xpm_pslpdomain.h"
#include "xpm_domain_iso.h"
#include "xpm_reset.h"
#include "xpm_bisr.h"
#include "xpm_board.h"
#include "xpm_prot.h"
#include "xpm_regs.h"
#include "xpm_device.h"
static XStatus LpdInitStart(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
(void)Args;
(void)NumOfArgs;
/* Check vccint_pslp first to make sure power is on */
if (XST_SUCCESS != XPmPower_CheckPower(PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_LPD_MASK)) {
Status = XPmBoard_ControlRail(RAIL_POWER_UP, POWER_RAIL_LPD);
if (XST_SUCCESS != Status) {
PmErr("Control power rail for LPD failure during power up\r\n");
goto done;
}
}
/* Remove PS_PMC domains isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_LPD_DFX, FALSE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/*
* Release POR for PS-LPD
*/
Status = XPmReset_AssertbyId(PM_RST_PS_POR, (u32)PM_RESET_ACTION_RELEASE);
done:
return Status;
}
static XStatus LpdPreBisrReqs(void)
{
XStatus Status = XST_FAILURE;
XPm_Device *XramDevice = NULL;
XPm_ResetNode *XramRst = NULL;
/* Remove PMC LPD isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_LPD, FALSE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Release reset for PS SRST */
Status = XPmReset_AssertbyId(PM_RST_PS_SRST, (u32)PM_RESET_ACTION_RELEASE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Release OCM2 (XRAM) SRST if XRAM exists */
XramDevice = XPmDevice_GetById(PM_DEV_XRAM_0);
if (NULL == XramDevice) {
goto done;
}
/* Make sure SRST source is PS SRST */
/* If PM_RST_XRAM_RST val is 0x0, XRAM_SRST = PS_SRST */
/* else XRAM_SRST = PL_SRST */
XramRst = XPmReset_GetById(PM_RST_XRAM);
if (NULL == XramRst) {
Status = XST_FAILURE;
goto done;
}
if (XramRst->Ops->GetState(XramRst) == 0x0U) {
Status = XPmReset_AssertbyId(PM_RST_OCM2_RST, (u32)PM_RESET_ACTION_RELEASE);
} else {
/* We shouldn't reach here. PL SRST is source for XRAM SRST */
Status = XPM_ERR_RESET;
}
done:
return Status;
}
static XStatus LpdInitFinish(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
(void)Args;
(void)NumOfArgs;
Status = XST_SUCCESS;
return Status;
}
static XStatus LpdHcComplete(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
(void)Args;
(void)NumOfArgs;
/* In case bisr and mbist are skipped */
Status = LpdPreBisrReqs();
if (XST_SUCCESS != Status) {
goto done;
}
/* Remove LPD SoC isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_SOC, FALSE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Copy sysmon data */
Status = XPmPowerDomain_ApplyAmsTrim(SysmonAddresses[XPM_NODEIDX_MONITOR_SYSMON_PS_LPD], PM_POWER_LPD, 0);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function executes scan clear sequence for LPD
*
* @return XST_SUCCESS if successful else XST_FAILURE
*
****************************************************************************/
static XStatus LpdScanClear(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
(void)Args;
(void)NumOfArgs;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
/* Trigger Scan clear on LPD/LPD_IOU */
PmRmw32(PMC_ANALOG_SCAN_CLEAR_TRIGGER,
(PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_MASK |
PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_IOU_MASK |
PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_RPU_MASK),
(PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_MASK |
PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_IOU_MASK |
PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_RPU_MASK));
Status = XPm_PollForMask(PMC_ANALOG_SCAN_CLEAR_DONE,
(PMC_ANALOG_SCAN_CLEAR_DONE_LPD_IOU_MASK |
PMC_ANALOG_SCAN_CLEAR_DONE_LPD_MASK |
PMC_ANALOG_SCAN_CLEAR_DONE_LPD_RPU_MASK),
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_PollForMask(PMC_ANALOG_SCAN_CLEAR_PASS,
(PMC_ANALOG_SCAN_CLEAR_PASS_LPD_IOU_MASK |
PMC_ANALOG_SCAN_CLEAR_PASS_LPD_MASK |
PMC_ANALOG_SCAN_CLEAR_PASS_LPD_RPU_MASK),
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* unwrite trigger bits */
PmRmw32(PMC_ANALOG_SCAN_CLEAR_TRIGGER,
(PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_MASK |
PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_IOU_MASK |
PMC_ANALOG_SCAN_CLEAR_TRIGGER_LPD_RPU_MASK), 0);
/*
* Pulse PS POR
*/
Status = XPmReset_AssertbyId(PM_RST_PS_POR, (u32)PM_RESET_ACTION_PULSE);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function executes LBIST sequence for LPD
*
* @return XST_SUCCESS if successful else XST_FAILURE
*
****************************************************************************/
static XStatus LpdLbist(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
XPm_Device *EfuseCache = XPmDevice_GetById(PM_DEV_EFUSE_CACHE);
u32 RegVal;
(void)Args;
(void)NumOfArgs;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
if (NULL == EfuseCache) {
Status = XST_FAILURE;
goto done;
}
/* Check if Lbist is enabled*/
PmIn32(EfuseCache->Node.BaseAddress + EFUSE_CACHE_MISC_CTRL_OFFSET, RegVal);
if ((RegVal & EFUSE_CACHE_MISC_CTRL_LBIST_EN_MASK) != EFUSE_CACHE_MISC_CTRL_LBIST_EN_MASK) {
Status = XST_SUCCESS;
goto done;
}
/* Enable LBIST isolation */
PmRmw32(PMC_ANALOG_LBIST_ISOLATION_EN,
(PMC_ANALOG_LBIST_ISOLATION_EN_LPD_MASK |
PMC_ANALOG_LBIST_ISOLATION_EN_LPD_RPU_MASK),
(PMC_ANALOG_LBIST_ISOLATION_EN_LPD_MASK |
PMC_ANALOG_LBIST_ISOLATION_EN_LPD_RPU_MASK));
/* Trigger LBIST on LPD */
PmRmw32(PMC_ANALOG_LBIST_ENABLE,
(PMC_ANALOG_LBIST_ENABLE_LPD_MASK |
PMC_ANALOG_LBIST_ENABLE_LPD_RPU_MASK),
(PMC_ANALOG_LBIST_ENABLE_LPD_MASK |
PMC_ANALOG_LBIST_ENABLE_LPD_RPU_MASK));
/* Release LBIST reset */
PmRmw32(PMC_ANALOG_LBIST_RST_N,
(PMC_ANALOG_LBIST_RST_N_LPD_MASK |
PMC_ANALOG_LBIST_RST_N_LPD_RPU_MASK),
(PMC_ANALOG_LBIST_RST_N_LPD_MASK |
PMC_ANALOG_LBIST_RST_N_LPD_RPU_MASK));
Status = XPm_PollForMask(PMC_ANALOG_LBIST_DONE,
(PMC_ANALOG_LBIST_DONE_LPD_MASK |
PMC_ANALOG_LBIST_DONE_LPD_RPU_MASK),
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Unwrite trigger bits */
PmRmw32(PMC_ANALOG_LBIST_ENABLE,
(PMC_ANALOG_LBIST_ENABLE_LPD_MASK |
PMC_ANALOG_LBIST_ENABLE_LPD_RPU_MASK), 0);
/*
* Pulse PS POR
*/
Status = XPmReset_AssertbyId(PM_RST_PS_POR, (u32)PM_RESET_ACTION_PULSE);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function executes BISR sequence for LPD
*
* @return XST_SUCCESS if successful else XST_FAILURE
*
****************************************************************************/
static XStatus LpdBisr(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
XPm_Device *XramDevice = XPmDevice_GetById(PM_DEV_XRAM_0);
XPm_PsLpDomain *LpDomain = (XPm_PsLpDomain *)XPmPower_GetById(PM_POWER_LPD);
if (NULL == LpDomain) {
goto done;
}
(void)Args;
(void)NumOfArgs;
/* Pre bisr requirements */
Status = LpdPreBisrReqs();
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmBisr_Repair(LPD_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
if (NULL == XramDevice) {
goto done;
}
Status = XPmBisr_Repair(XRAM_TAG_ID);
done:
if (XST_SUCCESS == Status) {
LpDomain->LpdBisrFlags |= LPD_BISR_DONE;
}
return Status;
}
/****************************************************************************/
/**
* @brief This function executes MBIST sequence for XRAM
*
* @return XST_SUCCESS if successful else XPM_ERR_MBIST_CLR
*
****************************************************************************/
static XStatus XramMbist(void)
{
/* XRAM MBIST Sequence */
/* There are 2 modes of memclear: (1) Unison Mode (2) Per Island Mode */
/* Using Unison Mode */
XStatus Status = XPM_ERR_MBIST_CLR;
XPm_Device *Device = NULL;
u32 BaseAddr, RegValue;
Device = XPmDevice_GetById(PM_DEV_XRAM_0);
if (NULL == Device) {
/* device might not have XRAM IP, hence return success*/
Status = XST_SUCCESS;
goto done;
}
BaseAddr = Device->Node.BaseAddress;
/* Unlock PCSR */
PmOut32(BaseAddr + XRAM_SLCR_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
/* Write to Memclear Trigger */
PmOut32(BaseAddr + XRAM_SLCR_PCSR_MASK_OFFSET, XRAM_MEM_CLEAR_TRIGGER_0_MASK);
PmOut32(BaseAddr + XRAM_SLCR_PCSR_PCR_OFFSET, XRAM_MEM_CLEAR_TRIGGER_0_MASK);
/* Poll for Memclear done */
Status = XPm_PollForMask(BaseAddr + XRAM_SLCR_PCSR_PSR_OFFSET,
XRAM_SLCR_PCSR_PSR_MEM_CLEAR_DONE_0_MASK |
XRAM_SLCR_PCSR_PSR_MEM_CLEAR_DONE_3_TO_1_MASK, XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Check Memclear pass/fail status */
PmIn32(BaseAddr + XRAM_SLCR_PCSR_PSR_OFFSET, RegValue);
if ((RegValue &
(XRAM_SLCR_PCSR_PSR_MEM_CLEAR_PASS_0_MASK |
XRAM_SLCR_PCSR_PSR_MEM_CLEAR_PASS_3_TO_1_MASK)) !=
((XRAM_SLCR_PCSR_PSR_MEM_CLEAR_PASS_0_MASK |
XRAM_SLCR_PCSR_PSR_MEM_CLEAR_PASS_3_TO_1_MASK))) {
Status = XST_FAILURE;
goto done;
}
/* Unwrite the trigger bits */
PmOut32(BaseAddr + XRAM_SLCR_PCSR_PCR_OFFSET, 0x0);
PmOut32(BaseAddr + XRAM_SLCR_PCSR_MASK_OFFSET, 0x0);
/* Lock PCSR */
PmOut32(BaseAddr + XRAM_SLCR_PCSR_LOCK_OFFSET, 0x0);
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function executes MBIST sequence for LPD
*
* @return XST_SUCCESS if successful else XST_FAILURE
*
****************************************************************************/
static XStatus LpdMbist(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
(void)Args;
(void)NumOfArgs;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
u32 RegValue;
/* Pre bisr requirements - In case if Bisr is skipped */
Status = LpdPreBisrReqs();
if (XST_SUCCESS != Status) {
goto done;
}
/* Release USB reset for LPD IOU Mbist to work*/
Status = XPmReset_AssertbyId(PM_RST_USB_0, (u32)PM_RESET_ACTION_RELEASE);
PmRmw32(PMC_ANALOG_OD_MBIST_RST,
(PMC_ANALOG_OD_MBIST_RST_LPD_IOU_MASK |
PMC_ANALOG_OD_MBIST_RST_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_RST_LPD_MASK),
(PMC_ANALOG_OD_MBIST_RST_LPD_IOU_MASK |
PMC_ANALOG_OD_MBIST_RST_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_RST_LPD_MASK));
PmRmw32(PMC_ANALOG_OD_MBIST_SETUP,
(PMC_ANALOG_OD_MBIST_SETUP_LPD_IOU_MASK |
PMC_ANALOG_OD_MBIST_SETUP_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_SETUP_LPD_MASK),
(PMC_ANALOG_OD_MBIST_SETUP_LPD_IOU_MASK |
PMC_ANALOG_OD_MBIST_SETUP_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_SETUP_LPD_MASK));
PmRmw32(PMC_ANALOG_OD_MBIST_PG_EN,
(PMC_ANALOG_OD_MBIST_PG_EN_LPD_IOU_MASK |
PMC_ANALOG_OD_MBIST_PG_EN_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_PG_EN_LPD_MASK),
(PMC_ANALOG_OD_MBIST_PG_EN_LPD_IOU_MASK |
PMC_ANALOG_OD_MBIST_PG_EN_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_PG_EN_LPD_MASK));
Status = XPm_PollForMask(PMC_ANALOG_OD_MBIST_DONE,
(PMC_ANALOG_OD_MBIST_DONE_LPD_IOU_MASK|
PMC_ANALOG_OD_MBIST_DONE_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_DONE_LPD_MASK),
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
PmIn32(PMC_ANALOG_OD_MBIST_GOOD, RegValue);
if ((PMC_ANALOG_OD_MBIST_GOOD_LPD_IOU_MASK |
PMC_ANALOG_OD_MBIST_GOOD_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_GOOD_LPD_MASK) != RegValue) {
Status = XST_FAILURE;
goto done;
}
/* Unwrite bits after mem clear has finished */
PmRmw32(PMC_ANALOG_OD_MBIST_RST,
(PMC_ANALOG_OD_MBIST_RST_LPD_IOU_MASK |
PMC_ANALOG_OD_MBIST_RST_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_RST_LPD_MASK), 0);
PmRmw32(PMC_ANALOG_OD_MBIST_SETUP,
(PMC_ANALOG_OD_MBIST_SETUP_LPD_IOU_MASK |
PMC_ANALOG_OD_MBIST_SETUP_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_SETUP_LPD_MASK),0);
PmRmw32(PMC_ANALOG_OD_MBIST_PG_EN,
(PMC_ANALOG_OD_MBIST_PG_EN_LPD_IOU_MASK |
PMC_ANALOG_OD_MBIST_PG_EN_LPD_RPU_MASK |
PMC_ANALOG_OD_MBIST_PG_EN_LPD_MASK),0);
Status = XramMbist();
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function configures xppu for LPD
*
* @return XST_SUCCESS if successful else XST_FAILURE
*
****************************************************************************/
static XStatus LpdXppuCtrl(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 XppuNodeId, Enable;
if (NumOfArgs < 2U) {
Status = XST_INVALID_PARAM;
goto done;
}
XppuNodeId = Args[0];
Enable = Args[1];
if ((u32)XPM_NODECLASS_PROTECTION != NODECLASS(XppuNodeId)) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((u32)XPM_NODESUBCL_PROT_XPPU != NODESUBCLASS(XppuNodeId)) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((0U != Enable) && (3U == NumOfArgs)) {
Status = XPmProt_XppuEnable(XppuNodeId, Args[2]);
} else {
Status = XPmProt_XppuDisable(XppuNodeId);
}
done:
return Status;
}
static struct XPm_PowerDomainOps LpdOps = {
.InitStart = LpdInitStart,
.InitFinish = LpdInitFinish,
.ScanClear = LpdScanClear,
.Mbist = LpdMbist,
.Lbist = LpdLbist,
.Bisr = LpdBisr,
.HcComplete = LpdHcComplete,
.XppuCtrl = LpdXppuCtrl,
};
XStatus XPmPsLpDomain_Init(XPm_PsLpDomain *PsLpd, u32 Id, u32 BaseAddress,
XPm_Power *Parent, u32 *OtherBaseAddresses,
u32 OtherBaseAddressesCnt)
{
XStatus Status = XST_FAILURE;
Status = XPmPowerDomain_Init(&PsLpd->Domain, Id, BaseAddress, Parent, &LpdOps);
if (XST_SUCCESS != Status) {
goto done;
}
PsLpd->LpdBisrFlags = 0;
/* Make sure enough base addresses are being passed */
if (3U <= OtherBaseAddressesCnt) {
PsLpd->LpdIouSlcrBaseAddr = OtherBaseAddresses[0];
PsLpd->LpdSlcrBaseAddr = OtherBaseAddresses[1];
PsLpd->LpdSlcrSecureBaseAddr = OtherBaseAddresses[2];
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pmcdomain.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_common.h"
#include "xpm_pmcdomain.h"
#include "xpm_domain_iso.h"
#include "xpm_prot.h"
static XStatus (*HandlePowerEvent)(XPm_Node *Node, u32 Event);
static XStatus HandlePmcDomainEvent(XPm_Node *Node, u32 Event)
{
XStatus Status = XST_FAILURE;
XPm_Power *Power = (XPm_Power *)Node;
PmDbg("State=%d, Event=%d\n\r", Node->State, Event);
switch (Node->State)
{
case (u8)XPM_POWER_STATE_ON:
if ((u32)XPM_POWER_EVENT_PWR_UP == Event) {
Status = XST_SUCCESS;
Power->UseCount++;
} else if ((u32)XPM_POWER_EVENT_PWR_DOWN == Event) {
Status = XST_SUCCESS;
Power->UseCount--;
} else {
/* Required by MISRA */
}
break;
default:
Status = XST_FAILURE;
break;
}
return Status;
}
/****************************************************************************/
/**
* @brief This function configures xppu for PMC or PMC_NPI
*
* @return XST_SUCCESS if successful else XST_FAILURE
*
****************************************************************************/
static XStatus PmcXppuCtrl(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 XppuNodeId, Enable;
if(NumOfArgs < 2U) {
Status = XST_INVALID_PARAM;
goto done;
}
XppuNodeId = Args[0];
Enable = Args[1];
if ((u32)XPM_NODECLASS_PROTECTION != NODECLASS(XppuNodeId)) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((u32)XPM_NODESUBCL_PROT_XPPU != NODESUBCLASS(XppuNodeId)) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((1U == Enable) && (3U == NumOfArgs)) {
Status = XPmProt_XppuEnable(XppuNodeId, Args[2]);
} else {
Status = XPmProt_XppuDisable(XppuNodeId);
}
done:
return Status;
}
static struct XPm_PowerDomainOps PmcOps = {
.XppuCtrl = PmcXppuCtrl,
};
XStatus XPmPmcDomain_Init(XPm_PmcDomain *PmcDomain, u32 Id)
{
XStatus Status = XST_FAILURE;
Status = XPmPowerDomain_Init(&PmcDomain->Domain, Id, 0x00000000, NULL, &PmcOps);
if (XST_SUCCESS != Status) {
goto done;
}
PmcDomain->Domain.Power.Node.State = (u8)XPM_POWER_STATE_ON;
PmcDomain->Domain.Power.UseCount = 1;
HandlePowerEvent = PmcDomain->Domain.Power.HandleEvent;
PmcDomain->Domain.Power.HandleEvent = HandlePmcDomainEvent;
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_node.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_defs.h"
#include "xpm_common.h"
#include "xpm_node.h"
void XPmNode_Init(XPm_Node *Node, u32 Id, u8 State, u32 BaseAddress)
{
PmDbg("Node Init: Type=%d, Id=%d, State=%d, BaseAddress=0x%08X\n\r",
NODETYPE(Id), Id, State, BaseAddress);
Node->Id = Id;
Node->State = State;
Node->BaseAddress = BaseAddress;
Node->Flags = 0;
Node->LatencyMarg = XPM_MAX_LATENCY;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilskey_v6_9/src/include/xilskey_eps_zynqmp_puf.h
/******************************************************************************
* Copyright (c) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xilskey_eps_zynqmp_puf.h
* @addtogroup xilskey_zynqmp_efuse ZynqMP EFUSE PS
* @{
* @cond xilskey_internal
* @{
* Contains the function prototypes, defines and macros for ZynqMP efusePs puf
* functionality.
*
* @note None.
*
* </pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- --------------------------------------------------------
* 6.1 vns 17/10/16 First release.
* 6.6 vns 06/06/18 Added doxygen tags
* 6.7 arc 01/05/19 Fixed MISRA-C violations.
* mmd 03/17/19 Added PUF syndrome data length in bytes for 4K mode
* 6.9 kpt 02/27/20 Removed prototype XilSKey_Puf_Debug2
* </pre>
*
*****************************************************************************/
#ifndef XSK_EPS_ZYNQMP_PUF_H
#define XSK_EPS_ZYNQMP_PUF_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xilskey_eps_zynqmp.h"
#include "xilskey_utils.h"
/************************** Constant Definitions *****************************/
#if defined XSK_PUF_DEBUG
#define XSK_PUF_DEBUG_GENERAL (1U)
#else
#define XSK_PUF_DEBUG_GENERAL (0U)
#endif
#define xPuf_printf(type,...) if ((type) == (1U)) \
{xil_printf (__VA_ARGS__);}
#define XSK_ZYNQMP_PUF_MODE4K (0U)
#define XSK_ZYNQMP_PUF_SYN_LEN (386)
#define XSK_ZYNQMP_MAX_RAW_4K_PUF_SYN_LEN (140U)
/* In bytes */
#define XSK_ZYNQMP_PUF_REGISTRATION (1U)
#define XSK_ZYNQMP_PUF_REGENERATION (4U)
#define XSK_ZYNQMP_PUF_CFG0_INIT_VAL (2U)
#define XSK_ZYNQMP_PUF_CFG1_INIT_VAL_4K (0x0c230090U)
#define XSK_ZYNQMP_EFUSEPS_PUF_TOTAL_ROWS (128U)
#define XSK_ZYNQMP_PUF_SYN_DATA_LEN_IN_BYTES (386U)
#define XSK_ZYNQMP_PUF_FORMATTED_SYN_DATA_LEN_IN_BYTES (140U)
#define XSK_ZYNQMP_PUF_DBG2_DATA_LEN_IN_BYTES (36U)
#define XSK_ZYNQMP_PUF_KEY_IV_LEN_IN_BYTES (12U)
#define XSK_ZYNQMP_PUF_AUX_LEN_IN_BITS (24U)
#define XSK_ZYNQMP_PUF_SHUTTER_VALUE (0x0100005eU)
/************************** Type Definitions ********************************/
/** @name xilinx eFUSE PUF secure bits
* @{
*/
typedef enum {
XSK_ZYNQMP_EFUSEPS_PUF_RESERVED = 28,
XSK_ZYNQMP_EFUSEPS_PUF_SYN_INVALID,
XSK_ZYNQMP_EFUSEPS_PUF_SYN_LOCK,
XSK_ZYNQMP_EFUSEPS_PUF_REG_DIS
}XskEfusePS_Puf_SecureBits;
/*@}*/
/** @name contains secure bits of efuse PUF
* @{
*/
typedef struct {
u8 SynInvalid;
u8 SynWrLk;
u8 RegisterDis;
u8 Reserved;
}XilSKey_Puf_Secure;
/*@}*/
/** @name PUF instance
* @{
*/
typedef struct {
u8 RegistrationMode; /**< PUF Registration Mode: Always 4K Mode */
u32 ShutterValue; /**< PUF Shutter value */
u32 SyndromeData[XSK_ZYNQMP_PUF_SYN_DATA_LEN_IN_BYTES];
/**< Helper data */
u32 EfuseSynData[XSK_ZYNQMP_PUF_FORMATTED_SYN_DATA_LEN_IN_BYTES];
/**< Formatted Syndrome data */
u32 Debug2Data[XSK_ZYNQMP_PUF_DBG2_DATA_LEN_IN_BYTES];
/**< Debug 2 Data */
u32 Chash; /**< CHASH Value */
u32 Aux; /**< AUX Value */
u8 RedKey[XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BYTES];
/**< Red Key */
u8 BlackKeyIV[XSK_ZYNQMP_PUF_KEY_IV_LEN_IN_BYTES];
/**< Black key IV (IV used to encrypt the
* red key using PUF key) */
u8 BlackKey[XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BYTES];
/**< Black Key generated */
} XilSKey_Puf;
/** @}
@endcond */
/****************************Prototypes***************************************/
u32 XilSKey_ZynqMp_EfusePs_WritePufHelprData(XilSKey_Puf *InstancePtr);
u32 XilSKey_ZynqMp_EfusePs_ReadPufHelprData(u32 *Address);
u32 XilSKey_ZynqMp_EfusePs_WritePufChash(XilSKey_Puf *InstancePtr);
u32 XilSKey_ZynqMp_EfusePs_ReadPufChash(u32 *Address, u8 ReadOption);
u32 XilSKey_ZynqMp_EfusePs_WritePufAux(XilSKey_Puf *InstancePtr);
u32 XilSKey_ZynqMp_EfusePs_ReadPufAux(u32 *Address, u8 ReadOption);
u32 XilSKey_Write_Puf_EfusePs_SecureBits(XilSKey_Puf_Secure *WriteSecureBits);
u32 XilSKey_Read_Puf_EfusePs_SecureBits(
XilSKey_Puf_Secure *SecureBitsRead, u8 ReadOption);
u32 XilSKey_Puf_Registration(XilSKey_Puf *InstancePtr);
u32 XilSKey_Puf_Regeneration(XilSKey_Puf *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* XSK_EPS_ZYNQMP_PUF_H */
/*@}*/
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_power.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_bisr.h"
#include "xpm_power.h"
#include "xpm_regs.h"
#include "xpm_powerdomain.h"
#include "xpm_pslpdomain.h"
#include "xpm_psm.h"
#include "sleep.h"
#include "xpm_rpucore.h"
#include "xpm_pll.h"
static XPm_Power *PmPowers[XPM_NODEIDX_POWER_MAX];
static u32 PmNumPowers;
XPm_Power *XPmPower_GetById(u32 Id)
{
XPm_Power *Power = NULL;
u32 NodeClass = NODECLASS(Id);
u32 NodeIndex = NODEINDEX(Id);
if (((u32)XPM_NODECLASS_POWER == NodeClass) &&
((u32)XPM_NODEIDX_POWER_MAX > NodeIndex)) {
Power = PmPowers[NodeIndex];
/* Validate power node ID is same as given ID. */
if ((NULL != Power) && (Id != Power->Node.Id)) {
Power = NULL;
}
}
return Power;
}
static XStatus SetPowerNode(u32 Id, XPm_Power *PwrNode)
{
XStatus Status = XST_INVALID_PARAM;
u32 NodeIndex = NODEINDEX(Id);
/*
* We assume that the Node ID class, subclass and type has _already_
* been validated before, so only check bounds here against index
*/
if ((NULL != PwrNode) && ((u32)XPM_NODEIDX_POWER_MAX > NodeIndex)) {
PmPowers[NodeIndex] = PwrNode;
PmNumPowers++;
Status = XST_SUCCESS;
}
return Status;
}
static XStatus PowerUpXram(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
XPm_Device *Device;
u32 XramSlcrAddress, PwrCtlAddress, PwrStatusAddress, RegVal;
u32 BitMask;
Device = XPmDevice_GetByIndex((u32)XPM_NODEIDX_DEV_XRAM_0);
if (NULL == Device) {
goto done;
}
XramSlcrAddress = Device->Node.BaseAddress;
BitMask = Node->BaseAddress;
switch (NODEINDEX(Node->Id)) {
case (u32)XPM_NODEIDX_POWER_XRAM_0:
case (u32)XPM_NODEIDX_POWER_XRAM_1:
case (u32)XPM_NODEIDX_POWER_XRAM_2:
case (u32)XPM_NODEIDX_POWER_XRAM_3:
PwrCtlAddress = XramSlcrAddress + XRAM_SLCR_PWR_UP_BANK0_OFFSET;
PwrStatusAddress = XramSlcrAddress + XRAM_SLCR_PWR_STATUS_BANK0_OFFSET;
Status = XST_SUCCESS;
break;
case (u32)XPM_NODEIDX_POWER_XRAM_4:
case (u32)XPM_NODEIDX_POWER_XRAM_5:
case (u32)XPM_NODEIDX_POWER_XRAM_6:
case (u32)XPM_NODEIDX_POWER_XRAM_7:
PwrCtlAddress = XramSlcrAddress + XRAM_SLCR_PWR_UP_BANK1_OFFSET;
PwrStatusAddress = XramSlcrAddress + XRAM_SLCR_PWR_STATUS_BANK1_OFFSET;
Status = XST_SUCCESS;
break;
case (u32)XPM_NODEIDX_POWER_XRAM_8:
case (u32)XPM_NODEIDX_POWER_XRAM_9:
case (u32)XPM_NODEIDX_POWER_XRAM_10:
case (u32)XPM_NODEIDX_POWER_XRAM_11:
PwrCtlAddress = XramSlcrAddress + XRAM_SLCR_PWR_UP_BANK2_OFFSET;
PwrStatusAddress = XramSlcrAddress + XRAM_SLCR_PWR_STATUS_BANK2_OFFSET;
Status = XST_SUCCESS;
break;
case (u32)XPM_NODEIDX_POWER_XRAM_12:
case (u32)XPM_NODEIDX_POWER_XRAM_13:
case (u32)XPM_NODEIDX_POWER_XRAM_14:
case (u32)XPM_NODEIDX_POWER_XRAM_15:
PwrCtlAddress = XramSlcrAddress + XRAM_SLCR_PWR_UP_BANK3_OFFSET;
PwrStatusAddress = XramSlcrAddress + XRAM_SLCR_PWR_STATUS_BANK3_OFFSET;
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
if (XST_SUCCESS != Status) {
goto done;
}
/* Check if already power up */
RegVal = XPm_In32(PwrStatusAddress);
if ((RegVal & BitMask) == BitMask) {
goto done;
}
/* Enable power state for selected bank */
PmRmw32(PwrCtlAddress, BitMask, BitMask);
/* Poll for power status to set */
Status = XPm_PollForMask(PwrStatusAddress, BitMask, XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* TODO: Wait for power to ramp up */
usleep(1);
/* TODO: Set chip enable bit */
done:
return Status;
}
static XStatus PowerDwnXram(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
XPm_Device *Device;
u32 XramSlcrAddress, PwrCtlAddress, PwrStatusAddress, RegVal;
u32 BitMask;
Device = XPmDevice_GetByIndex((u32)XPM_NODEIDX_DEV_XRAM_0);
if (NULL == Device) {
goto done;
}
XramSlcrAddress = Device->Node.BaseAddress;
BitMask = Node->BaseAddress;
switch (NODEINDEX(Node->Id)) {
case (u32)XPM_NODEIDX_POWER_XRAM_0:
case (u32)XPM_NODEIDX_POWER_XRAM_1:
case (u32)XPM_NODEIDX_POWER_XRAM_2:
case (u32)XPM_NODEIDX_POWER_XRAM_3:
PwrCtlAddress = XramSlcrAddress + XRAM_SLCR_PWR_DWN_BANK0_OFFSET;
PwrStatusAddress = XramSlcrAddress + XRAM_SLCR_PWR_STATUS_BANK0_OFFSET;
Status = XST_SUCCESS;
break;
case (u32)XPM_NODEIDX_POWER_XRAM_4:
case (u32)XPM_NODEIDX_POWER_XRAM_5:
case (u32)XPM_NODEIDX_POWER_XRAM_6:
case (u32)XPM_NODEIDX_POWER_XRAM_7:
PwrCtlAddress = XramSlcrAddress + XRAM_SLCR_PWR_DWN_BANK1_OFFSET;
PwrStatusAddress = XramSlcrAddress + XRAM_SLCR_PWR_STATUS_BANK1_OFFSET;
Status = XST_SUCCESS;
break;
case (u32)XPM_NODEIDX_POWER_XRAM_8:
case (u32)XPM_NODEIDX_POWER_XRAM_9:
case (u32)XPM_NODEIDX_POWER_XRAM_10:
case (u32)XPM_NODEIDX_POWER_XRAM_11:
PwrCtlAddress = XramSlcrAddress + XRAM_SLCR_PWR_DWN_BANK2_OFFSET;
PwrStatusAddress = XramSlcrAddress + XRAM_SLCR_PWR_STATUS_BANK2_OFFSET;
Status = XST_SUCCESS;
break;
case (u32)XPM_NODEIDX_POWER_XRAM_12:
case (u32)XPM_NODEIDX_POWER_XRAM_13:
case (u32)XPM_NODEIDX_POWER_XRAM_14:
case (u32)XPM_NODEIDX_POWER_XRAM_15:
PwrCtlAddress = XramSlcrAddress + XRAM_SLCR_PWR_DWN_BANK3_OFFSET;
PwrStatusAddress = XramSlcrAddress + XRAM_SLCR_PWR_STATUS_BANK3_OFFSET;
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
if (XST_SUCCESS != Status) {
goto done;
}
/* Check if already power up */
RegVal = XPm_In32(PwrStatusAddress);
if ((RegVal & BitMask) == 0U) {
goto done;
}
/* TODO: Clear chip enable bit */
/* Disable power state for selected bank */
PmRmw32(PwrCtlAddress, BitMask, ~BitMask);
/* Poll for power status to clear */
Status = XPm_PollForZero(PwrStatusAddress, BitMask, XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
static XStatus SendPowerUpReq(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
XPm_PsLpDomain *LpDomain = (XPm_PsLpDomain *)XPmPower_GetById(PM_POWER_LPD);
if (NULL == LpDomain) {
Status = XST_FAILURE;
goto done;
}
if ((u8)XPM_POWER_STATE_ON == Node->State) {
Status = XST_SUCCESS;
goto done;
}
if ((u32)XPM_NODESUBCL_POWER_ISLAND == NODESUBCLASS(Node->Id)) {
if ((u32)XPM_NODETYPE_POWER_ISLAND_XRAM == NODETYPE(Node->Id)) {
Status = PowerUpXram(Node);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
Status = XPmPsm_SendPowerUpReq(Node->BaseAddress);
if (XST_SUCCESS != Status) {
goto done;
}
}
/*
* For S80 ES1, there is a bug in LPD which requires the
* LPD_INT and RPU power domain signals needs to be
* asserted, to prevent repair vector corruption(EDT-993543).
* To fix this bug rerun LPD BISR whenever the RPU power
* island is powered down and brought up again.
*/
if ((PLATFORM_VERSION_SILICON_ES1 == PlatformVersion) &&
(PLATFORM_VERSION_SILICON == Platform) &&
((u32)XPM_NODEIDX_POWER_RPU0_0 == NODEINDEX(Node->Id)) &&
(0U == (LPD_BISR_DONE & LpDomain->LpdBisrFlags))) {
if (0U != (LPD_BISR_DATA_COPIED & LpDomain->LpdBisrFlags)) {
Status = XPmBisr_TriggerLpd();
} else {
Status = XPmBisr_Repair(LPD_TAG_ID);
}
}
} else {
PmDbg("Request to power up domain %x\r\n",Node->Id);
switch (NODEINDEX(Node->Id)) {
case (u32)XPM_NODEIDX_POWER_LPD:
Status = XPm_PowerUpLPD(Node);
break;
case (u32)XPM_NODEIDX_POWER_FPD:
Status = XPm_PowerUpFPD(Node);
break;
case (u32)XPM_NODEIDX_POWER_NOC:
Status = XPm_PowerUpNoC(Node);
break;
case (u32)XPM_NODEIDX_POWER_ME:
Status = XPm_PowerUpME(Node);
break;
case (u32)XPM_NODEIDX_POWER_PLD:
Status = XPm_PowerUpPLD(Node);
break;
case (u32)XPM_NODEIDX_POWER_CPM:
Status = XPm_PowerUpCPM(Node);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
}
done:
return Status;
}
static XStatus SendPowerDownReq(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk;
u32 Idx;
XPm_PsLpDomain *LpDomain = (XPm_PsLpDomain *)XPmPower_GetById(PM_POWER_LPD);
if (NULL == LpDomain) {
Status = XST_FAILURE;
goto done;
}
if ((u32)XPM_NODESUBCL_POWER_ISLAND == NODESUBCLASS(Node->Id)) {
if ((u32)XPM_NODETYPE_POWER_ISLAND_XRAM == NODETYPE(Node->Id)) {
Status = PowerDwnXram(Node);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
Status = XPmPsm_SendPowerDownReq(Node->BaseAddress);
if (XST_SUCCESS != Status) {
goto done;
}
}
if ((u32)XPM_NODEIDX_POWER_RPU0_0 == NODEINDEX(Node->Id)) {
LpDomain->LpdBisrFlags &= (u8)(~(LPD_BISR_DONE));
/*
* Clear and Disable RPU internal reg comparators to prevent
* PSM_GLOBAL_REG.PSM_ERR1_STATUS.rpu_ls from erroring out
*/
Status = XPm_RpuRstComparators(PM_DEV_RPU0_0);
if (Status != XST_SUCCESS) {
PmErr("Unable to reset RPU Comparators\n\r");
goto done;
}
}
} else {
/* Put the PLL in suspended mode */
for (Idx = (u32)XPM_NODEIDX_CLK_MIN; Idx < (u32)XPM_NODEIDX_CLK_MAX; Idx++) {
Clk = XPmClock_GetByIdx(Idx);
if ((NULL != Clk) && (ISPLL(Clk->Node.Id)) &&
(Node->Id == Clk->PwrDomain->Node.Id)) {
Status = XPmClockPll_Suspend((XPm_PllClockNode *)Clk);
if (XST_SUCCESS != Status) {
goto done;
}
}
}
PmDbg("Request to power down domain %x\r\n",Node->Id);
switch (NODEINDEX(Node->Id)) {
case (u32)XPM_NODEIDX_POWER_LPD:
Status = XPm_PowerDwnLPD();
break;
case (u32)XPM_NODEIDX_POWER_FPD:
Status = XPm_PowerDwnFPD(Node);
break;
case (u32)XPM_NODEIDX_POWER_NOC:
Status = XPm_PowerDwnNoC();
break;
case (u32)XPM_NODEIDX_POWER_ME:
Status = XPm_PowerDwnME();
break;
case (u32)XPM_NODEIDX_POWER_PLD:
Status = XPm_PowerDwnPLD();
break;
case (u32)XPM_NODEIDX_POWER_CPM:
Status = XPm_PowerDwnCPM();
break;
default:
Status = XST_INVALID_PARAM;
break;
}
}
done:
return Status;
}
static XStatus HandlePowerEvent(XPm_Node *Node, u32 Event)
{
XStatus Status = XST_FAILURE;
XPm_Power *Power = (XPm_Power *)Node;
PmDbg("Id:0x%x, UseCount:%d, State=%x, Event=%x\n\r",
Node->Id, Power->UseCount, Node->State, Event);
switch (Node->State)
{
case (u8)XPM_POWER_STATE_STANDBY:
case (u8)XPM_POWER_STATE_OFF:
if ((u32)XPM_POWER_EVENT_PWR_UP == Event) {
Status = XST_SUCCESS;
if (NULL != Power->Parent) {
Node->State = (u8)XPM_POWER_STATE_PWR_UP_PARENT;
Power->WfParentUseCnt = Power->Parent->UseCount + 1U;
Status = Power->Parent->HandleEvent(
&Power->Parent->Node, XPM_POWER_EVENT_PWR_UP);
/* Todo: Start timer to poll parent node */
/* Hack */
Status = Power->HandleEvent(Node, XPM_POWER_EVENT_TIMER);
} else {
/* Write to PSM power up request register */
Status = SendPowerUpReq(Node);
if (XST_SUCCESS != Status) {
break;
}
Node->State = (u8)XPM_POWER_STATE_PWR_UP_SELF;
/* Todo: Start timer to poll PSM status register */
/* Hack */
Status = Power->HandleEvent(Node, XPM_POWER_EVENT_TIMER);
}
}
break;
case (u8)XPM_POWER_STATE_PWR_UP_PARENT:
if ((u32)XPM_POWER_EVENT_TIMER == Event) {
Status = XST_SUCCESS;
if (Power->WfParentUseCnt == Power->Parent->UseCount) {
Power->WfParentUseCnt = 0;
/* Write to PSM power up request register */
Status = SendPowerUpReq(Node);
if (XST_SUCCESS != Status) {
break;
}
Node->State = (u8)XPM_POWER_STATE_PWR_UP_SELF;
/* Todo: Start timer to poll PSM status register */
/* Hack */
Status = Power->HandleEvent(Node, XPM_POWER_EVENT_TIMER);
} else {
/* Todo: Restart timer to poll parent state */
}
}
break;
case (u8)XPM_POWER_STATE_PWR_UP_SELF:
if ((u32)XPM_POWER_EVENT_TIMER == Event) {
Status = XST_SUCCESS;
/* Todo: Read PSM status register */
if (TRUE /* Hack: Power node is up */) {
Node->State = (u8)XPM_POWER_STATE_ON;
Power->UseCount++;
} else {
/* Todo: Restart timer to poll PSM */
}
}
break;
case (u8)XPM_POWER_STATE_ON:
if ((u32)XPM_POWER_EVENT_PWR_UP == Event) {
Status = XST_SUCCESS;
if (NULL != Power->Parent) {
Status = Power->Parent->HandleEvent(
&Power->Parent->Node, XPM_POWER_EVENT_PWR_UP);
}
Power->UseCount++;
} else if ((u32)XPM_POWER_EVENT_PWR_DOWN == Event) {
Status = XST_SUCCESS;
if (1U == Power->UseCount) {
/* Write to PSM power down request register */
Status = SendPowerDownReq(Node);
if (XST_SUCCESS != Status) {
break;
}
Node->State = (u8)XPM_POWER_STATE_PWR_DOWN_SELF;
/* Todo: Start timer to poll PSM status register */
/* Hack */
Status = Power->HandleEvent(Node, XPM_POWER_EVENT_TIMER);
} else {
Power->UseCount--;
if (NULL != Power->Parent) {
Status = Power->Parent->HandleEvent(
&Power->Parent->Node, XPM_POWER_EVENT_PWR_DOWN);
}
}
} else {
/* Required by MISRA */
}
break;
case (u8)XPM_POWER_STATE_PWR_DOWN_SELF:
if ((u32)XPM_POWER_EVENT_TIMER == Event) {
Status = XST_SUCCESS;
/* Todo: Read PSM status register */
if (TRUE /* Hack: Power node is down */) {
Power->UseCount--;
if (NULL != Power->Parent) {
Node->State = (u8)XPM_POWER_STATE_PWR_DOWN_PARENT;
Power->WfParentUseCnt = Power->Parent->UseCount - 1U;
Status = Power->Parent->HandleEvent(
&Power->Parent->Node, XPM_POWER_EVENT_PWR_DOWN);
/* Todo: Start timer to poll the parent node */
/* Hack */
Status = Power->HandleEvent(Node, XPM_POWER_EVENT_TIMER);
} else {
Node->State = (u8)XPM_POWER_STATE_OFF;
}
} else {
/* Todo: Restart timer to poll PSM */
}
}
break;
case (u8)XPM_POWER_STATE_PWR_DOWN_PARENT:
if ((u32)XPM_POWER_EVENT_TIMER == Event) {
Status = XST_SUCCESS;
if (Power->WfParentUseCnt == Power->Parent->UseCount) {
Node->State = (u8)XPM_POWER_STATE_OFF;
Power->WfParentUseCnt = 0;
} else {
/* Todo: Restart timer to poll parent state */
}
}
break;
default:
Status = XST_FAILURE;
break;
}
return Status;
}
XStatus XPmPower_GetStatus(const u32 SubsystemId, const u32 DeviceId, XPm_DeviceStatus *const DeviceStatus)
{
XStatus Status = XST_FAILURE;
XPm_Power *Power;
/* Warning Fix */
(void)SubsystemId;
Power = XPmPower_GetById(DeviceId);
if (NULL == Power) {
goto done;
}
DeviceStatus->Status = Power->Node.State;
DeviceStatus->Usage = 0;
DeviceStatus->Requirement = 0;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmPower_Init(XPm_Power *Power,
u32 Id, u32 BaseAddress, XPm_Power *Parent)
{
XStatus Status = XST_FAILURE;
XPm_PowerDomain *PowerDomain;
/* Todo: Uncomment this after integrating with CDO handler */
if (NULL != XPmPower_GetById(Id)) {
Status = XST_DEVICE_BUSY;
goto done;
}
XPmNode_Init(&Power->Node, Id, (u8)XPM_POWER_STATE_OFF, BaseAddress);
Power->Parent = Parent;
Power->NextPeer = NULL;
Power->HandleEvent = HandlePowerEvent;
Power->UseCount = 0;
Power->WfParentUseCnt = 0;
Power->PwrDnLatency = 0;
Power->PwrUpLatency = 0;
if ((NULL != Parent) && ((u32)XPM_NODESUBCL_POWER_DOMAIN ==
NODESUBCLASS(Parent->Node.Id))) {
PowerDomain = (XPm_PowerDomain *)Parent;
Power->NextPeer = PowerDomain->Children;
PowerDomain->Children = Power;
}
Status = SetPowerNode(Id, Power);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmPower_AddParent(u32 Id, u32 *Parents, u32 NumParents)
{
XStatus Status = XST_FAILURE;
XPm_Power *Power;
XPm_Power *PowerParent;
u32 i;
Power = XPmPower_GetById(Id);
if (NULL == Power) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
for (i = 0; i < NumParents; i++) {
PowerParent = XPmPower_GetById(Parents[i]);
if (NULL == PowerParent) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Todo: Handle more than one parent */
Power->Parent = PowerParent;
}
Status = XST_SUCCESS;
done:
return Status;
}
int XPmPower_GetWakeupLatency(const u32 DeviceId, u32 *Latency)
{
int Status = XST_SUCCESS;
XPm_Power *Power = XPmPower_GetById(DeviceId);
XPm_Power *Parent;
*Latency = 0;
if (NULL == Power) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((u8)XPM_POWER_STATE_ON == Power->Node.State) {
goto done;
}
*Latency += Power->PwrUpLatency;
Parent = Power->Parent;
/* Account latencies of parents if a parent is down */
while (NULL != Parent) {
if ((u8)XPM_POWER_STATE_ON == Parent->Node.State) {
break;
}
*Latency += Parent->PwrUpLatency;
Parent = Parent->Parent;
}
done:
return Status;
}
<file_sep>/python_drivers/decode_alg_test.py
# -*- coding: utf-8 -*-
"""
Created on Thu Aug 20 15:19:05 2020
@author: tianlab01
"""
import datetime
import james_utils as ju
import random
import time
logfile = "decode_test_results_2_10.txt"
def log_to_file(test_num, stream_len, loss_rate, num_dark_counts, errs):
file = open(logfile,'a')
new_line = str(test_num) + "," + str(stream_len) + "," + str(loss_rate) + "," + str(num_dark_counts) + "," + str(errs)
file.write(new_line + "\n")
file.close()
return
num_sync = 100
num_dead = 20
#loss_rate = 20
#num_dark_counts = 0
bin_size = 100000 #in ps
bin_number = 4#can encode values between 0 and 15
period = 500000 #in ps
file = open(logfile,'a')
file.write(datetime.datetime.now().strftime("\n================\n%I:%M%p on %B %d, %Y\n"))
file.write("test number, stream length, loss rate (%), number of dark counts, errors\n")
file.close()
for loss_rate in range(0, 90, 5):
for num_dark_counts in range(0, 1000, 20):
for stream_len in range(5, 1000, 25):
for test_num in range(0, 100):
#Generate the test stream
test_stream = []
for i in range(0, stream_len):
test_stream.append(random.randint(0,bin_number - 1))
#Encode the test stream
pulse_list = ju.generate_pulse_list(period, num_sync, num_dead, bin_number, bin_size, test_stream, loss_rate, num_dark_counts)
#decode the test stream
decoded_stream,a,b,c,d = ju.decode_pulse_list(pulse_list, period, bin_number, bin_size, num_sync)
sent_str = "Sent: "
for i in test_stream:
sent_str += str(i) + ", "
res_str = "Got: "
for i in decoded_stream:
res_str += str(i) + ", "
#print(sent_str)
#print(res_str)
errs = len(test_stream) - ju.check_results(test_stream, decoded_stream)
print("Stream_len: " + str(stream_len) + ", num_dark_counts: " + str(num_dark_counts) + ", loss_rate:, " + str(loss_rate))
print("Errors: " + str(errs))
log_to_file(test_num, stream_len, loss_rate, num_dark_counts, errs)
#time.sleep(3)
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_node.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* Pm Node related structures and definitions
*********************************************************************/
#ifndef PM_NODE_H_
#define PM_NODE_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_defs.h"
#include "pm_common.h"
#include "xil_types.h"
#include "xstatus.h"
typedef u8 PmNodeId;
typedef u8 PmStateId;
/* Forward declaration */
typedef struct PmPower PmPower;
typedef struct PmClockHandle PmClockHandle;
typedef struct PmNode PmNode;
typedef struct PmSlave PmSlave;
typedef struct PmProc PmProc;
typedef struct PmNodeClass PmNodeClass;
/* Function pointer for wake/sleep transition functions */
typedef int (*const PmNodeTranHandler)(PmNode* const nodePtr);
/*********************************************************************
* Macros
********************************************************************/
#define NODE_CLASS_PROC 1U
#define NODE_CLASS_POWER 2U
#define NODE_CLASS_SLAVE 3U
#define NODE_CLASS_PLL 4U
#define NODE_IS_PROC(nodePtr) (NODE_CLASS_PROC == (nodePtr)->class->id)
#define NODE_IS_POWER(nodePtr) (NODE_CLASS_POWER == (nodePtr)->class->id)
#define NODE_IS_SLAVE(nodePtr) (NODE_CLASS_SLAVE == (nodePtr)->class->id)
#define NODE_IS_PLL(nodePtr) (NODE_CLASS_PLL == (nodePtr)->class->id)
#define NODE_IS_OFF(nodePtr) (0U == ((nodePtr)->currState & 1U))
#define NODE_LOCKED_POWER_FLAG 0x1U
#define NODE_LOCKED_CLOCK_FLAG 0x2U
#define NODE_IDLE_DONE 0x4U
#define DEFINE_NODE_BUCKET(b) .bucket = (b), \
.bucketSize = ARRAY_SIZE(b)
#define DEFINE_PM_POWER_INFO(i) .powerInfo = (i), \
.powerInfoCnt = ARRAY_SIZE(i)
#if defined(PM_LOG_LEVEL) && (PM_LOG_LEVEL > 0)
#define DEFINE_NODE_NAME(n) .name = n
#else
#define DEFINE_NODE_NAME(n) .name = ""
#endif
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmNode - Structure common for all entities that have node id
* @derived Pointer to a derived node structure
* @class Pointer to the node class of the node
* @parent Pointer to power parent node
* @clocks Pointer to the list of clocks that the node uses
* @latencyMarg Latency margin: lowest latency requirement - powerup latency
* @nodeId Node id defined in pm_defs.h
* @typeId Type id, used to distinguish the nodes
* @currState Id of the node's current state. Interpretation depends on type
* of the node, bit 0 value is reserved for off states
* @powerInfo Pointer to the array of power consumptions arranged by
* stateId
* @powerInfoCnt Number of power consumptions in powerInfo array based on
* number of states
* @flags Node flags
* @name Node name
*/
typedef struct PmNode {
void* const derived;
PmNodeClass* const class;
PmPower* const parent;
PmClockHandle* clocks;
u32 latencyMarg;
const char* const name;
const u8 *const powerInfo;
const u8 powerInfoCnt;
const PmNodeId nodeId;
PmStateId currState;
u8 flags;
} PmNode;
/**
* PmNodeClass - Node class models common behavior for a collection of nodes
* @clearConfig Clear current configuration of the node
* @construct Constructor for the node, call only once on startup
* @getWakeUpLatency Get wake-up latency of the node
* @getPowerData Get power consumption of the node
* @forceDown Put node in the lowest power state
* @init Initialize the node
* @isUsable Check if the node is usable by current configuration
* @getPerms Get permissions (ORed masks of masters allowed to
* control node's clocks)
* @bucket Pointer to the array of nodes from the class
* @bucketSize Number of nodes in the bucket
* @id Nodes' class/type ID
*/
typedef struct PmNodeClass {
void (*const clearConfig)(PmNode* const node);
void (*const construct)(PmNode* const node);
s32 (*const getWakeUpLatency)(const PmNode* const node, u32* const lat);
s32 (*const getPowerData)(const PmNode* const node, u32* const data);
s32 (*const forceDown)(PmNode* const node);
s32 (*const init)(PmNode* const node);
bool (*const isUsable)(PmNode* const node);
u32 (*const getPerms)(const PmNode* const node);
PmNode** const bucket;
const u32 bucketSize;
const u8 id;
} PmNodeClass;
/*********************************************************************
* Function declarations
********************************************************************/
PmNode* PmGetNodeById(const u32 nodeId);
void* PmNodeGetDerived(const u8 nodeClass, const u32 nodeId);
static inline void* PmNodeGetSlave(const u32 nodeId) {
return PmNodeGetDerived(NODE_CLASS_SLAVE, nodeId);
}
static inline void* PmNodeGetPower(const u32 nodeId) {
return PmNodeGetDerived(NODE_CLASS_POWER, nodeId);
}
static inline void* PmNodeGetProc(const u32 nodeId) {
return PmNodeGetDerived(NODE_CLASS_PROC, nodeId);
}
static inline void* PmNodeGetPll(const u32 nodeId) {
return PmNodeGetDerived(NODE_CLASS_PLL, nodeId);
}
void PmNodeUpdateCurrState(PmNode* const node, const PmStateId newState);
void PmNodeClearConfig(void);
void PmNodeConstruct(void);
void PmNodeForceDownUnusable(void);
void PmNodeLogUnknownState(const PmNode* const node, const PmStateId state);
s32 PmNodeGetPowerInfo(const PmNode* const node, u32* const data);
s32 PmNodeForceDown(PmNode* const node);
s32 PmNodeInit(void);
u32 PmNodeGetPermissions(PmNode* const node);
#ifdef __cplusplus
}
#endif
#endif /* PM_NODE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/include/pm_apu.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef PM_APU_H
#define PM_APU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* APU Base Address
*/
#define APU_BASEADDR 0XFD5C0000U
/**
* Register: APU_ERR_CTRL
*/
#define APU_ERR_CTRL ( ( APU_BASEADDR ) + 0X00000000U )
#define APU_ERR_CTRL_PSLVERR_SHIFT 0U
#define APU_ERR_CTRL_PSLVERR_WIDTH 1U
#define APU_ERR_CTRL_PSLVERR_MASK 0X00000001U
/**
* Register: APU_ISR
*/
#define APU_ISR ( ( APU_BASEADDR ) + 0X00000010U )
#define APU_ISR_INV_APB_SHIFT 0U
#define APU_ISR_INV_APB_WIDTH 1U
#define APU_ISR_INV_APB_MASK 0X00000001U
/**
* Register: APU_IMR
*/
#define APU_IMR ( ( APU_BASEADDR ) + 0X00000014U )
#define APU_IMR_INV_APB_SHIFT 0U
#define APU_IMR_INV_APB_WIDTH 1U
#define APU_IMR_INV_APB_MASK 0X00000001U
/**
* Register: APU_IEN
*/
#define APU_IEN ( ( APU_BASEADDR ) + 0X00000018U )
#define APU_IEN_INV_APB_SHIFT 0U
#define APU_IEN_INV_APB_WIDTH 1U
#define APU_IEN_INV_APB_MASK 0X00000001U
/**
* Register: APU_IDS
*/
#define APU_IDS ( ( APU_BASEADDR ) + 0X0000001CU )
#define APU_IDS_INV_APB_SHIFT 0U
#define APU_IDS_INV_APB_WIDTH 1U
#define APU_IDS_INV_APB_MASK 0X00000001U
/**
* Register: APU_CONFIG_0
*/
#define APU_CONFIG_0 ( ( APU_BASEADDR ) + 0X00000020U )
#define APU_CONFIG_0_CFGTE_SHIFT 24U
#define APU_CONFIG_0_CFGTE_WIDTH 4U
#define APU_CONFIG_0_CFGTE_MASK 0X0F000000U
#define APU_CONFIG_0_CFGEND_SHIFT 16U
#define APU_CONFIG_0_CFGEND_WIDTH 4U
#define APU_CONFIG_0_CFGEND_MASK 0X000F0000U
#define APU_CONFIG_0_VINITHI_SHIFT 8U
#define APU_CONFIG_0_VINITHI_WIDTH 4U
#define APU_CONFIG_0_VINITHI_MASK 0X00000F00U
#define APU_CONFIG_0_AA64NAA32_SHIFT 0U
#define APU_CONFIG_0_AA64NAA32_WIDTH 4U
#define APU_CONFIG_0_AA64NAA32_MASK 0X0000000FU
/**
* Register: APU_CONFIG_1
*/
#define APU_CONFIG_1 ( ( APU_BASEADDR ) + 0X00000024U )
#define APU_CONFIG_1_L2RSTDISABLE_SHIFT 29U
#define APU_CONFIG_1_L2RSTDISABLE_WIDTH 1U
#define APU_CONFIG_1_L2RSTDISABLE_MASK 0X20000000U
#define APU_CONFIG_1_L1RSTDISABLE_SHIFT 28U
#define APU_CONFIG_1_L1RSTDISABLE_WIDTH 1U
#define APU_CONFIG_1_L1RSTDISABLE_MASK 0X10000000U
#define APU_CONFIG_1_CP15DISABLE_SHIFT 0U
#define APU_CONFIG_1_CP15DISABLE_WIDTH 4U
#define APU_CONFIG_1_CP15DISABLE_MASK 0X0000000FU
/**
* Register: APU_RVBARADDR0L
*/
#define APU_RVBARADDR0L ( ( APU_BASEADDR ) + 0X00000040U )
#define APU_RVBARADDR0L_ADDR_SHIFT 2U
#define APU_RVBARADDR0L_ADDR_WIDTH 30U
#define APU_RVBARADDR0L_ADDR_MASK 0XFFFFFFFCU
/**
* Register: APU_RVBARADDR0H
*/
#define APU_RVBARADDR0H ( ( APU_BASEADDR ) + 0X00000044U )
#define APU_RVBARADDR0H_ADDR_SHIFT 0U
#define APU_RVBARADDR0H_ADDR_WIDTH 8U
#define APU_RVBARADDR0H_ADDR_MASK 0X000000FFU
/**
* Register: APU_RVBARADDR1L
*/
#define APU_RVBARADDR1L ( ( APU_BASEADDR ) + 0X00000048U )
#define APU_RVBARADDR1L_ADDR_SHIFT 2U
#define APU_RVBARADDR1L_ADDR_WIDTH 30U
#define APU_RVBARADDR1L_ADDR_MASK 0XFFFFFFFCU
/**
* Register: APU_RVBARADDR1H
*/
#define APU_RVBARADDR1H ( ( APU_BASEADDR ) + 0X0000004CU )
#define APU_RVBARADDR1H_ADDR_SHIFT 0U
#define APU_RVBARADDR1H_ADDR_WIDTH 8U
#define APU_RVBARADDR1H_ADDR_MASK 0X000000FFU
/**
* Register: APU_RVBARADDR2L
*/
#define APU_RVBARADDR2L ( ( APU_BASEADDR ) + 0X00000050U )
#define APU_RVBARADDR2L_ADDR_SHIFT 2U
#define APU_RVBARADDR2L_ADDR_WIDTH 30U
#define APU_RVBARADDR2L_ADDR_MASK 0XFFFFFFFCU
/**
* Register: APU_RVBARADDR2H
*/
#define APU_RVBARADDR2H ( ( APU_BASEADDR ) + 0X00000054U )
#define APU_RVBARADDR2H_ADDR_SHIFT 0U
#define APU_RVBARADDR2H_ADDR_WIDTH 8U
#define APU_RVBARADDR2H_ADDR_MASK 0X000000FFU
/**
* Register: APU_RVBARADDR3L
*/
#define APU_RVBARADDR3L ( ( APU_BASEADDR ) + 0X00000058U )
#define APU_RVBARADDR3L_ADDR_SHIFT 2U
#define APU_RVBARADDR3L_ADDR_WIDTH 30U
#define APU_RVBARADDR3L_ADDR_MASK 0XFFFFFFFCU
/**
* Register: APU_RVBARADDR3H
*/
#define APU_RVBARADDR3H ( ( APU_BASEADDR ) + 0X0000005CU )
#define APU_RVBARADDR3H_ADDR_SHIFT 0U
#define APU_RVBARADDR3H_ADDR_WIDTH 8U
#define APU_RVBARADDR3H_ADDR_MASK 0X000000FFU
/**
* Register: APU_ACE_CTRL
*/
#define APU_ACE_CTRL ( ( APU_BASEADDR ) + 0X00000060U )
#define APU_ACE_CTRL_AWQOS_SHIFT 16U
#define APU_ACE_CTRL_AWQOS_WIDTH 4U
#define APU_ACE_CTRL_AWQOS_MASK 0X000F0000U
#define APU_ACE_CTRL_ARQOS_SHIFT 0U
#define APU_ACE_CTRL_ARQOS_WIDTH 4U
#define APU_ACE_CTRL_ARQOS_MASK 0X0000000FU
/**
* Register: APU_SNOOP_CTRL
*/
#define APU_SNOOP_CTRL ( ( APU_BASEADDR ) + 0X00000080U )
#define APU_SNOOP_CTRL_ACE_INACT_SHIFT 4U
#define APU_SNOOP_CTRL_ACE_INACT_WIDTH 1U
#define APU_SNOOP_CTRL_ACE_INACT_MASK 0X00000010U
#define APU_SNOOP_CTRL_ACP_INACT_SHIFT 0U
#define APU_SNOOP_CTRL_ACP_INACT_WIDTH 1U
#define APU_SNOOP_CTRL_ACP_INACT_MASK 0X00000001U
/**
* Register: APU_PWRCTL
*/
#define APU_PWRCTL ( ( APU_BASEADDR ) + 0X00000090U )
#define APU_PWRCTL_CLREXMONREQ_SHIFT 17U
#define APU_PWRCTL_CLREXMONREQ_WIDTH 1U
#define APU_PWRCTL_CLREXMONREQ_MASK 0X00020000U
#define APU_PWRCTL_L2FLUSHREQ_SHIFT 16U
#define APU_PWRCTL_L2FLUSHREQ_WIDTH 1U
#define APU_PWRCTL_L2FLUSHREQ_MASK 0X00010000U
#define APU_PWRCTL_CPUPWRDWNREQ_SHIFT 0U
#define APU_PWRCTL_CPUPWRDWNREQ_WIDTH 4U
#define APU_PWRCTL_CPUPWRDWNREQ_MASK 0X0000000FU
/**
* Register: APU_PWRSTAT
*/
#define APU_PWRSTAT ( ( APU_BASEADDR ) + 0X00000094U )
#define APU_PWRSTAT_CLREXMONACK_SHIFT 17U
#define APU_PWRSTAT_CLREXMONACK_WIDTH 1U
#define APU_PWRSTAT_CLREXMONACK_MASK 0X00020000U
#define APU_PWRSTAT_L2FLUSHDONE_SHIFT 16U
#define APU_PWRSTAT_L2FLUSHDONE_WIDTH 1U
#define APU_PWRSTAT_L2FLUSHDONE_MASK 0X00010000U
#define APU_PWRSTAT_DBGNOPWRDWN_SHIFT 0U
#define APU_PWRSTAT_DBGNOPWRDWN_WIDTH 4U
#define APU_PWRSTAT_DBGNOPWRDWN_MASK 0X0000000FU
/**
* Register: APU_ECO
*/
#define APU_ECO ( ( APU_BASEADDR ) + 0X000000ECU )
#define APU_ECO_SPARE_SHIFT 0U
#define APU_ECO_SPARE_WIDTH 32U
#define APU_ECO_SPARE_MASK 0XFFFFFFFFU
/**
* Register: APU_RAM_ADJ_0
*/
#define APU_RAM_ADJ_0 ( ( APU_BASEADDR ) + 0X000000F0U )
#define APU_RAM_ADJ_0_L1_ITAG_EMAS_SHIFT 29U
#define APU_RAM_ADJ_0_L1_ITAG_EMAS_WIDTH 1U
#define APU_RAM_ADJ_0_L1_ITAG_EMAS_MASK 0X20000000U
#define APU_RAM_ADJ_0_L1_ITAG_EMAW_SHIFT 27U
#define APU_RAM_ADJ_0_L1_ITAG_EMAW_WIDTH 2U
#define APU_RAM_ADJ_0_L1_ITAG_EMAW_MASK 0X18000000U
#define APU_RAM_ADJ_0_L1_ITAG_EMA_SHIFT 24U
#define APU_RAM_ADJ_0_L1_ITAG_EMA_WIDTH 3U
#define APU_RAM_ADJ_0_L1_ITAG_EMA_MASK 0X07000000U
#define APU_RAM_ADJ_0_L1_IDATA_EMAS_SHIFT 21U
#define APU_RAM_ADJ_0_L1_IDATA_EMAS_WIDTH 1U
#define APU_RAM_ADJ_0_L1_IDATA_EMAS_MASK 0X00200000U
#define APU_RAM_ADJ_0_L1_IDATA_EMAW_SHIFT 19U
#define APU_RAM_ADJ_0_L1_IDATA_EMAW_WIDTH 2U
#define APU_RAM_ADJ_0_L1_IDATA_EMAW_MASK 0X00180000U
#define APU_RAM_ADJ_0_L1_IDATA_EMA_SHIFT 16U
#define APU_RAM_ADJ_0_L1_IDATA_EMA_WIDTH 3U
#define APU_RAM_ADJ_0_L1_IDATA_EMA_MASK 0X00070000U
#define APU_RAM_ADJ_0_L1_DTAG_EMAS_SHIFT 13U
#define APU_RAM_ADJ_0_L1_DTAG_EMAS_WIDTH 1U
#define APU_RAM_ADJ_0_L1_DTAG_EMAS_MASK 0X00002000U
#define APU_RAM_ADJ_0_L1_DTAG_EMAW_SHIFT 11U
#define APU_RAM_ADJ_0_L1_DTAG_EMAW_WIDTH 2U
#define APU_RAM_ADJ_0_L1_DTAG_EMAW_MASK 0X00001800U
#define APU_RAM_ADJ_0_L1_DTAG_EMA_SHIFT 8U
#define APU_RAM_ADJ_0_L1_DTAG_EMA_WIDTH 3U
#define APU_RAM_ADJ_0_L1_DTAG_EMA_MASK 0X00000700U
#define APU_RAM_ADJ_0_L1_DDATA_EMAS_SHIFT 5U
#define APU_RAM_ADJ_0_L1_DDATA_EMAS_WIDTH 1U
#define APU_RAM_ADJ_0_L1_DDATA_EMAS_MASK 0X00000020U
#define APU_RAM_ADJ_0_L1_DDATA_EMAW_SHIFT 3U
#define APU_RAM_ADJ_0_L1_DDATA_EMAW_WIDTH 2U
#define APU_RAM_ADJ_0_L1_DDATA_EMAW_MASK 0X00000018U
#define APU_RAM_ADJ_0_L1_DDATA_EMA_SHIFT 0U
#define APU_RAM_ADJ_0_L1_DDATA_EMA_WIDTH 3U
#define APU_RAM_ADJ_0_L1_DDATA_EMA_MASK 0X00000007U
/**
* Register: APU_RAM_ADJ_1
*/
#define APU_RAM_ADJ_1 ( ( APU_BASEADDR ) + 0X000000F4U )
#define APU_RAM_ADJ_1_TLB_EMAS_SHIFT 29U
#define APU_RAM_ADJ_1_TLB_EMAS_WIDTH 1U
#define APU_RAM_ADJ_1_TLB_EMAS_MASK 0X20000000U
#define APU_RAM_ADJ_1_TLB_EMAW_SHIFT 27U
#define APU_RAM_ADJ_1_TLB_EMAW_WIDTH 2U
#define APU_RAM_ADJ_1_TLB_EMAW_MASK 0X18000000U
#define APU_RAM_ADJ_1_TLB_EMA_SHIFT 24U
#define APU_RAM_ADJ_1_TLB_EMA_WIDTH 3U
#define APU_RAM_ADJ_1_TLB_EMA_MASK 0X07000000U
#define APU_RAM_ADJ_1_DIRTY_EMAS_SHIFT 21U
#define APU_RAM_ADJ_1_DIRTY_EMAS_WIDTH 1U
#define APU_RAM_ADJ_1_DIRTY_EMAS_MASK 0X00200000U
#define APU_RAM_ADJ_1_DIRTY_EMAW_SHIFT 19U
#define APU_RAM_ADJ_1_DIRTY_EMAW_WIDTH 2U
#define APU_RAM_ADJ_1_DIRTY_EMAW_MASK 0X00180000U
#define APU_RAM_ADJ_1_DIRTY_EMA_SHIFT 16U
#define APU_RAM_ADJ_1_DIRTY_EMA_WIDTH 3U
#define APU_RAM_ADJ_1_DIRTY_EMA_MASK 0X00070000U
#define APU_RAM_ADJ_1_BTAC1_EMAS_SHIFT 13U
#define APU_RAM_ADJ_1_BTAC1_EMAS_WIDTH 1U
#define APU_RAM_ADJ_1_BTAC1_EMAS_MASK 0X00002000U
#define APU_RAM_ADJ_1_BTAC1_EMAW_SHIFT 11U
#define APU_RAM_ADJ_1_BTAC1_EMAW_WIDTH 2U
#define APU_RAM_ADJ_1_BTAC1_EMAW_MASK 0X00001800U
#define APU_RAM_ADJ_1_BTAC1_EMA_SHIFT 8U
#define APU_RAM_ADJ_1_BTAC1_EMA_WIDTH 3U
#define APU_RAM_ADJ_1_BTAC1_EMA_MASK 0X00000700U
#define APU_RAM_ADJ_1_BTAC0_EMAS_SHIFT 5U
#define APU_RAM_ADJ_1_BTAC0_EMAS_WIDTH 1U
#define APU_RAM_ADJ_1_BTAC0_EMAS_MASK 0X00000020U
#define APU_RAM_ADJ_1_BTAC0_EMAW_SHIFT 3U
#define APU_RAM_ADJ_1_BTAC0_EMAW_WIDTH 2U
#define APU_RAM_ADJ_1_BTAC0_EMAW_MASK 0X00000018U
#define APU_RAM_ADJ_1_BTAC0_EMA_SHIFT 0U
#define APU_RAM_ADJ_1_BTAC0_EMA_WIDTH 3U
#define APU_RAM_ADJ_1_BTAC0_EMA_MASK 0X00000007U
/**
* Register: APU_RAM_ADJ_2
*/
#define APU_RAM_ADJ_2 ( ( APU_BASEADDR ) + 0X000000F8U )
#define APU_RAM_ADJ_2_ETF_EMAS_SHIFT 29U
#define APU_RAM_ADJ_2_ETF_EMAS_WIDTH 1U
#define APU_RAM_ADJ_2_ETF_EMAS_MASK 0X20000000U
#define APU_RAM_ADJ_2_ETF_EMAW_SHIFT 27U
#define APU_RAM_ADJ_2_ETF_EMAW_WIDTH 2U
#define APU_RAM_ADJ_2_ETF_EMAW_MASK 0X18000000U
#define APU_RAM_ADJ_2_ETF_EMA_SHIFT 24U
#define APU_RAM_ADJ_2_ETF_EMA_WIDTH 3U
#define APU_RAM_ADJ_2_ETF_EMA_MASK 0X07000000U
#define APU_RAM_ADJ_2_SCU_TAG_EMAS_SHIFT 13U
#define APU_RAM_ADJ_2_SCU_TAG_EMAS_WIDTH 1U
#define APU_RAM_ADJ_2_SCU_TAG_EMAS_MASK 0X00002000U
#define APU_RAM_ADJ_2_SCU_TAG_EMAW_SHIFT 11U
#define APU_RAM_ADJ_2_SCU_TAG_EMAW_WIDTH 2U
#define APU_RAM_ADJ_2_SCU_TAG_EMAW_MASK 0X00001800U
#define APU_RAM_ADJ_2_SCU_TAG_EMA_SHIFT 8U
#define APU_RAM_ADJ_2_SCU_TAG_EMA_WIDTH 3U
#define APU_RAM_ADJ_2_SCU_TAG_EMA_MASK 0X00000700U
#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_SHIFT 5U
#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_WIDTH 1U
#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_MASK 0X00000020U
#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_SHIFT 3U
#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_WIDTH 2U
#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_MASK 0X00000018U
#define APU_RAM_ADJ_2_L2_VICTIM_EMA_SHIFT 0U
#define APU_RAM_ADJ_2_L2_VICTIM_EMA_WIDTH 3U
#define APU_RAM_ADJ_2_L2_VICTIM_EMA_MASK 0X00000007U
/**
* Register: APU_RAM_ADJ_3
*/
#define APU_RAM_ADJ_3 ( ( APU_BASEADDR ) + 0X000000FCU )
#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_SHIFT 29U
#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_WIDTH 1U
#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_MASK 0X20000000U
#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_SHIFT 27U
#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_WIDTH 2U
#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_MASK 0X18000000U
#define APU_RAM_ADJ_3_L2_TAGECC_EMA_SHIFT 24U
#define APU_RAM_ADJ_3_L2_TAGECC_EMA_WIDTH 3U
#define APU_RAM_ADJ_3_L2_TAGECC_EMA_MASK 0X07000000U
#define APU_RAM_ADJ_3_L2_TAG_EMAS_SHIFT 21U
#define APU_RAM_ADJ_3_L2_TAG_EMAS_WIDTH 1U
#define APU_RAM_ADJ_3_L2_TAG_EMAS_MASK 0X00200000U
#define APU_RAM_ADJ_3_L2_TAG_EMAW_SHIFT 19U
#define APU_RAM_ADJ_3_L2_TAG_EMAW_WIDTH 2U
#define APU_RAM_ADJ_3_L2_TAG_EMAW_MASK 0X00180000U
#define APU_RAM_ADJ_3_L2_TAG_EMA_SHIFT 16U
#define APU_RAM_ADJ_3_L2_TAG_EMA_WIDTH 3U
#define APU_RAM_ADJ_3_L2_TAG_EMA_MASK 0X00070000U
#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_SHIFT 13U
#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_WIDTH 1U
#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_MASK 0X00002000U
#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_SHIFT 11U
#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_WIDTH 2U
#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_MASK 0X00001800U
#define APU_RAM_ADJ_3_L2_DATAECC_EMA_SHIFT 8U
#define APU_RAM_ADJ_3_L2_DATAECC_EMA_WIDTH 3U
#define APU_RAM_ADJ_3_L2_DATAECC_EMA_MASK 0X00000700U
#define APU_RAM_ADJ_3_L2_DATA_EMAS_SHIFT 5U
#define APU_RAM_ADJ_3_L2_DATA_EMAS_WIDTH 1U
#define APU_RAM_ADJ_3_L2_DATA_EMAS_MASK 0X00000020U
#define APU_RAM_ADJ_3_L2_DATA_EMAW_SHIFT 3U
#define APU_RAM_ADJ_3_L2_DATA_EMAW_WIDTH 2U
#define APU_RAM_ADJ_3_L2_DATA_EMAW_MASK 0X00000018U
#define APU_RAM_ADJ_3_L2_DATA_EMA_SHIFT 0U
#define APU_RAM_ADJ_3_L2_DATA_EMA_WIDTH 3U
#define APU_RAM_ADJ_3_L2_DATA_EMA_MASK 0X00000007U
/**
* Register: APU_XPD_REG0
*/
#define APU_XPD_REG0 ( ( APU_BASEADDR ) + 0X00000600U )
#define APU_XPD_REG0_PRE_LOAD_SHIFT 0U
#define APU_XPD_REG0_PRE_LOAD_WIDTH 32U
#define APU_XPD_REG0_PRE_LOAD_MASK 0XFFFFFFFFU
/**
* Register: APU_XPD_REG1
*/
#define APU_XPD_REG1 ( ( APU_BASEADDR ) + 0X00000604U )
#define APU_XPD_REG1_EXPECTED_SHIFT 0U
#define APU_XPD_REG1_EXPECTED_WIDTH 32U
#define APU_XPD_REG1_EXPECTED_MASK 0XFFFFFFFFU
/**
* Register: APU_XPD_CTRL0
*/
#define APU_XPD_CTRL0 ( ( APU_BASEADDR ) + 0X00000608U )
#define APU_XPD_CTRL0_DELAY_SPARE_SHIFT 25U
#define APU_XPD_CTRL0_DELAY_SPARE_WIDTH 5U
#define APU_XPD_CTRL0_DELAY_SPARE_MASK 0X3E000000U
#define APU_XPD_CTRL0_CMP_SEL_SHIFT 24U
#define APU_XPD_CTRL0_CMP_SEL_WIDTH 1U
#define APU_XPD_CTRL0_CMP_SEL_MASK 0X01000000U
#define APU_XPD_CTRL0_DELAY_CELL_TYPE_SHIFT 19U
#define APU_XPD_CTRL0_DELAY_CELL_TYPE_WIDTH 5U
#define APU_XPD_CTRL0_DELAY_CELL_TYPE_MASK 0X00F80000U
#define APU_XPD_CTRL0_DELAY_VT_TYPE_SHIFT 17U
#define APU_XPD_CTRL0_DELAY_VT_TYPE_WIDTH 2U
#define APU_XPD_CTRL0_DELAY_VT_TYPE_MASK 0X00060000U
#define APU_XPD_CTRL0_DELAY_VALUE_SHIFT 6U
#define APU_XPD_CTRL0_DELAY_VALUE_WIDTH 11U
#define APU_XPD_CTRL0_DELAY_VALUE_MASK 0X0001FFC0U
#define APU_XPD_CTRL0_PATH_SEL_SHIFT 0U
#define APU_XPD_CTRL0_PATH_SEL_WIDTH 6U
#define APU_XPD_CTRL0_PATH_SEL_MASK 0X0000003FU
/**
* Register: APU_XPD_CTRL1
*/
#define APU_XPD_CTRL1 ( ( APU_BASEADDR ) + 0X0000060CU )
#define APU_XPD_CTRL1_CLK_SPARE_SHIFT 12U
#define APU_XPD_CTRL1_CLK_SPARE_WIDTH 4U
#define APU_XPD_CTRL1_CLK_SPARE_MASK 0X0000F000U
#define APU_XPD_CTRL1_CLK_PHASE_SEL_SHIFT 10U
#define APU_XPD_CTRL1_CLK_PHASE_SEL_WIDTH 2U
#define APU_XPD_CTRL1_CLK_PHASE_SEL_MASK 0X00000C00U
#define APU_XPD_CTRL1_CLK_VT_TYPE_SHIFT 8U
#define APU_XPD_CTRL1_CLK_VT_TYPE_WIDTH 2U
#define APU_XPD_CTRL1_CLK_VT_TYPE_MASK 0X00000300U
#define APU_XPD_CTRL1_CLK_CELL_TYPE_SHIFT 6U
#define APU_XPD_CTRL1_CLK_CELL_TYPE_WIDTH 2U
#define APU_XPD_CTRL1_CLK_CELL_TYPE_MASK 0X000000C0U
#define APU_XPD_CTRL1_CLK_INSERT_DLY_SHIFT 2U
#define APU_XPD_CTRL1_CLK_INSERT_DLY_WIDTH 4U
#define APU_XPD_CTRL1_CLK_INSERT_DLY_MASK 0X0000003CU
#define APU_XPD_CTRL1_CLK_SEL_SHIFT 0U
#define APU_XPD_CTRL1_CLK_SEL_WIDTH 2U
#define APU_XPD_CTRL1_CLK_SEL_MASK 0X00000003U
/**
* Register: APU_XPD_CTRL2
*/
#define APU_XPD_CTRL2 ( ( APU_BASEADDR ) + 0X00000614U )
#define APU_XPD_CTRL2_CTRL_SPARE_SHIFT 1U
#define APU_XPD_CTRL2_CTRL_SPARE_WIDTH 2U
#define APU_XPD_CTRL2_CTRL_SPARE_MASK 0X00000006U
#define APU_XPD_CTRL2_ENABLE_SHIFT 0U
#define APU_XPD_CTRL2_ENABLE_WIDTH 1U
#define APU_XPD_CTRL2_ENABLE_MASK 0X00000001U
/**
* Register: APU_XPD_CTRL3
*/
#define APU_XPD_CTRL3 ( ( APU_BASEADDR ) + 0X00000618U )
#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_SHIFT 3U
#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_WIDTH 12U
#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_MASK 0X00007FF8U
#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_SHIFT 2U
#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_WIDTH 1U
#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_MASK 0X00000004U
#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_SHIFT 1U
#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_WIDTH 1U
#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_MASK 0X00000002U
#define APU_XPD_CTRL3_DCYCLE_START_SHIFT 0U
#define APU_XPD_CTRL3_DCYCLE_START_WIDTH 1U
#define APU_XPD_CTRL3_DCYCLE_START_MASK 0X00000001U
/**
* Register: APU_XPD_SOFT_RST
*/
#define APU_XPD_SOFT_RST ( ( APU_BASEADDR ) + 0X0000061CU )
#define APU_XPD_SOFT_RST_CLK2_SHIFT 2U
#define APU_XPD_SOFT_RST_CLK2_WIDTH 1U
#define APU_XPD_SOFT_RST_CLK2_MASK 0X00000004U
#define APU_XPD_SOFT_RST_CLK1_SHIFT 1U
#define APU_XPD_SOFT_RST_CLK1_WIDTH 1U
#define APU_XPD_SOFT_RST_CLK1_MASK 0X00000002U
#define APU_XPD_SOFT_RST_CLK0_SHIFT 0U
#define APU_XPD_SOFT_RST_CLK0_WIDTH 1U
#define APU_XPD_SOFT_RST_CLK0_MASK 0X00000001U
/**
* Register: APU_XPD_STAT
*/
#define APU_XPD_STAT ( ( APU_BASEADDR ) + 0X00000620U )
#define APU_XPD_STAT_CMP_RESULT_SHIFT 1U
#define APU_XPD_STAT_CMP_RESULT_WIDTH 1U
#define APU_XPD_STAT_CMP_RESULT_MASK 0X00000002U
#define APU_XPD_STAT_CMP_DONE_SHIFT 0U
#define APU_XPD_STAT_CMP_DONE_WIDTH 1U
#define APU_XPD_STAT_CMP_DONE_MASK 0X00000001U
#ifdef __cplusplus
}
#endif
#endif /* PM_APU_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_system.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* Contains system-level PM functions
********************************************************************/
#ifndef PM_SYSTEM_H_
#define PM_SYSTEM_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
#include "pm_master.h"
#include "pm_slave.h"
#define PM_SUSPEND_TYPE_REGULAR 0U
#define PM_SUSPEND_TYPE_POWER_OFF 1U
/*********************************************************************
* Function declarations
********************************************************************/
s32 PmSystemRequirementAdd(void);
void PmSystemPrepareForRestart(const PmMaster* const master);
void PmSystemRestartDone(const PmMaster* const master);
bool PmSystemDetectPowerOffSuspend(const PmMaster* const master);
s32 PmSystemPreparePowerOffSuspend(void);
s32 PmSystemFinalizePowerOffSuspend(void);
s32 PmSystemResumePowerOffSuspend(void);
u32 PmSystemSuspendType(void);
void PmSystemSetSuspendType(u32 type);
#ifdef __cplusplus
}
#endif
#endif /* PM_SYSTEM_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/versal/xsecure_rsa_core.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_rsa_core.h
* This file contains Versal specific RSA core APIs.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.0 vns 03/09/19 Initial release
* 4.1 kpt 01/07/20 Added Macro's for Magic Numbers in
* xsecure_rsa_core.c
* 4.2 kpt 03/26/20 Added Error code XSECURE_RSA_ZEROIZE_ERROR
*
* </pre>
*
******************************************************************************/
#ifndef XSECURE_RSA_CORE_H
#define XSECURE_RSA_CORE_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xsecure_utils.h"
/************************** Constant Definitions ****************************/
#define XSECURE_RSA_FAILED 0x1U /**< RSA Failed Error Code */
#define XSECURE_RSA_DATA_VALUE_ERROR 0x2U /**< for RSA private decryption
* data should be lesser than
* modulus */
#define XSECURE_RSA_ZEROIZE_ERROR 0x80U /**< for RSA zeroization Error*/
#define XSECURE_HASH_TYPE_SHA3 (48U) /**< SHA-3 hash size */
#define XSECURE_HASH_TYPE_SHA2 (32U) /**< SHA-2 hash size */
#define XSECURE_FSBL_SIG_SIZE (512U)/**< FSBL signature size */
#define XSECURE_RSA_MAX_BUFF (6U) /**< RSA RAM Write Buffers */
#define XSECURE_RSA_MAX_RD_WR_CNT (22U) /**< No of writes or reads to RSA RAM buffers */
/* Key size in bytes */
#define XSECURE_RSA_2048_KEY_SIZE (2048U/8U) /**< RSA 2048 key size */
#define XSECURE_RSA_3072_KEY_SIZE (3072U/8U) /**< RSA 3072 key size */
#define XSECURE_RSA_4096_KEY_SIZE (4096U/8U) /**< RSA 4096 key size */
/* Key size in words */
#define XSECURE_RSA_2048_SIZE_WORDS (64) /**< RSA 2048 Size in words */
#define XSECURE_RSA_3072_SIZE_WORDS (96) /**< RSA 3072 Size in words */
#define XSECURE_RSA_4096_SIZE_WORDS (128U) /**< RSA 4096 Size in words */
#define XSECURE_RSA_RAM_EXPO (0U) /**< bit for RSA RAM Exponent */
#define XSECURE_RSA_RAM_MOD (1U) /**< bit for RSA RAM modulus */
#define XSECURE_RSA_RAM_DIGEST (2U) /**< bit for RSA RAM Digest */
#define XSECURE_RSA_RAM_SPAD (3U) /**< bit for RSA RAM SPAD */
#define XSECURE_RSA_RAM_RES_Y (4U) /**< bit for RSA RAM Result(Y) */
#define XSECURE_RSA_RAM_RES_Q (5U) /**< bit for RSA RAM Result(Q) */
/** @name Control Register
*
* Control Register opcode definitions
*/
#define XSECURE_RSA_CONTROL_DCA (0x08U) /**< Abort Operation */
#define XSECURE_RSA_CONTROL_NOP (0x00U) /**< No Operation */
#define XSECURE_RSA_CONTROL_EXP (0x01U) /**< Exponentiation Opcode */
#define XSECURE_RSA_CONTROL_EXP_PRE (0x05U) /**< Expo. using R*R mod M */
/**
* Config registers values
* CFG0 is for Qsel and multiplication passes
* CFG1 is for Mont digits
* CFG2 is for location size
* CFG5 is for No.of groups
*/
#define XSECURE_ECDSA_RSA_CFG0_4096_VALUE (0x0000006BU)
#define XSECURE_ECDSA_RSA_CFG1_4096_VALUE (0x00000081U)
#define XSECURE_ECDSA_RSA_CFG2_4096_VALUE (0x00000016U)
#define XSECURE_ECDSA_RSA_CFG5_4096_VALUE (0x00000015U)
#define XSECURE_ECDSA_RSA_CFG0_3072_VALUE (0x000000A0U)
#define XSECURE_ECDSA_RSA_CFG1_3072_VALUE (0x00000061U)
#define XSECURE_ECDSA_RSA_CFG2_3072_VALUE (0x00000016U)
#define XSECURE_ECDSA_RSA_CFG5_3072_VALUE (0x00000010U)
#define XSECURE_ECDSA_RSA_CFG0_2048_VALUE (0x00000016U)
#define XSECURE_ECDSA_RSA_CFG1_2048_VALUE (0x00000041U)
#define XSECURE_ECDSA_RSA_CFG2_2048_VALUE (0x00000016U)
#define XSECURE_ECDSA_RSA_CFG5_2048_VALUE (0x0000000AU)
/** @name RSA status Register
*
* The Status Register(SR) indicates the current state of RSA device.
*
* Status Register Bit Definition
*/
#define XSECURE_RSA_STATUS_DONE (0x1U) /**< Operation Done */
#define XSECURE_RSA_STATUS_BUSY (0x2U) /**< RSA busy */
#define XSECURE_RSA_STATUS_ERROR (0x4U) /**< Error */
#define XSECURE_RSA_STATUS_PROG_CNT (0xF8U) /**< Progress Counter */
/* @}*/
typedef enum {
XSECURE_RSA_UNINITIALIZED = 0,
XSECURE_RSA_INITIALIZED /**< 0x1 */
} XSecure_RsaState;
typedef enum {
XSECURE_RSA_SIGN_ENC = 0x0U,
XSECURE_RSA_SIGN_DEC /**< 0x1 */
}XSecure_RsaOps;
/***************************** Type Definitions ******************************/
/**
* The RSA driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
u32 BaseAddress; /**< Device Base Address */
u8* Mod; /**< Modulus */
u8* ModExt; /**< Precalc. R sq. mod N */
u8* ModExpo; /**< Exponent */
u8 EncDec; /**< 0 for signature verification and 1 for generation */
u32 SizeInWords;/** RSA key size in words */
XSecure_RsaState RsaState;
} XSecure_Rsa;
/***************************** Function Prototypes ***************************/
/* Versal specific RSA core initialization function */
u32 XSecure_RsaCfgInitialize(XSecure_Rsa *InstancePtr);
/* Versal specific RSA core encryption/decryption function */
u32 XSecure_RsaOperation(XSecure_Rsa *InstancePtr, u8 *Input,
u8 *Result, u8 RsaOp, u32 Size);
u32 XSecure_RsaPublicEncryptKat(void);
/* Versal specific function for selection of PKCS padding */
u8* XSecure_RsaGetTPadding();
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_RSA_CORE_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilffs_v4_3/src/Makefile
###############################################################################
# Copyright (c) 2013 - 2020 Xilinx, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
###############################################################################
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS =
LIB=libxilffs.a
ifeq ($(notdir $(COMPILER)) , iccarm)
EXTRA_ARCHIVE_FLAGS=--create
else
ifeq ($(notdir $(COMPILER)) , armcc)
EXTRA_ARCHIVE_FLAGS=--create
else
ifeq ($(notdir $(COMPILER)) , armclang)
EXTRA_ARCHIVE_FLAGS=-rc
else
EXTRA_ARCHIVE_FLAGS=rc
endif
endif
endif
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
FATFS_DIR = .
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
FATFS_SRCS := $(wildcard *.c)
FATFS_OBJS = $(addprefix $(FATFS_DIR)/, $(FATFS_SRCS:%.c=%.o))
INCLUDEFILES=$(FATFS_DIR)/include/ff.h \
$(FATFS_DIR)/include/ffconf.h \
$(FATFS_DIR)/include/diskio.h \
$(FATFS_DIR)/include/integer.h
libs: libxilffs.a
libxilffs.a: print_msg_fatfs $(FATFS_OBJS)
$(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} ${FATFS_OBJS}
print_msg_fatfs:
@echo "Compiling XilFFs Library"
.PHONY: include
include: libxilffs_includes
libxilffs_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf $(FATFS_DIR)/${OBJECTS}
rm -rf ${RELEASEDIR}/${LIB}
$(FATFS_DIR)/%.o: $(FATFS_DIR)/%.c $(INCLUDEFILES)
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -c $< -o $@
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_7/src/xusbpsu_hibernation.c
/******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_hibernation.c
*
* This patch adds hibernation support to usbpsu driver when dwc3 is operating
* as a gadget
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.0 Mayank 12/01/18 First release
* 1.5 VAK 14/03/19 Enable hibernation related functions only when
* XUSBPSU_HIBERNATION_ENABLE is defined
* 1.7 pm 23/03/20 Restructured the code for more readability and modularity
* pm 25/03/20 Add clocking support
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xusbpsu_hw.h"
#include "xusbpsu_endpoint.h"
#include "xusbpsu_local.h"
#ifdef XUSBPSU_HIBERNATION_ENABLE
/************************** Constant Definitions *****************************/
#define NUM_OF_NONSTICKY_REGS 27U
#define XUSBPSU_HIBER_SCRATCHBUF_SIZE 4096U
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
static u8 ScratchBuf[XUSBPSU_HIBER_SCRATCHBUF_SIZE];
/* Registers saved during hibernation and restored at wakeup */
static u32 SaveRegsAddr[] = {
XUSBPSU_DCTL,
XUSBPSU_DCFG,
XUSBPSU_DEVTEN,
XUSBPSU_GSBUSCFG0,
XUSBPSU_GSBUSCFG1,
XUSBPSU_GCTL,
XUSBPSU_GTXTHRCFG,
XUSBPSU_GRXTHRCFG,
XUSBPSU_GTXFIFOSIZ(0U),
XUSBPSU_GTXFIFOSIZ(1U),
XUSBPSU_GTXFIFOSIZ(2U),
XUSBPSU_GTXFIFOSIZ(3U),
XUSBPSU_GTXFIFOSIZ(4U),
XUSBPSU_GTXFIFOSIZ(5U),
XUSBPSU_GTXFIFOSIZ(6U),
XUSBPSU_GTXFIFOSIZ(7U),
XUSBPSU_GTXFIFOSIZ(8U),
XUSBPSU_GTXFIFOSIZ(9U),
XUSBPSU_GTXFIFOSIZ(10U),
XUSBPSU_GTXFIFOSIZ(11U),
XUSBPSU_GTXFIFOSIZ(12U),
XUSBPSU_GTXFIFOSIZ(13U),
XUSBPSU_GTXFIFOSIZ(14U),
XUSBPSU_GTXFIFOSIZ(15U),
XUSBPSU_GRXFIFOSIZ(0U),
XUSBPSU_GUSB3PIPECTL(0U),
XUSBPSU_GUSB2PHYCFG(0U),
};
static u32 SavedRegs[NUM_OF_NONSTICKY_REGS];
/*****************************************************************************/
/**
* Save non sticky registers
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void XUsbPsu_SaveRegs(struct XUsbPsu *InstancePtr)
{
u32 i;
for (i = 0U; i < NUM_OF_NONSTICKY_REGS; i++) {
SavedRegs[i] = XUsbPsu_ReadReg(InstancePtr, SaveRegsAddr[i]);
}
}
/*****************************************************************************/
/**
* Restore non sticky registers
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void XUsbPsu_RestoreRegs(struct XUsbPsu *InstancePtr)
{
u32 i;
for (i = 0U; i < NUM_OF_NONSTICKY_REGS; i++) {
XUsbPsu_WriteReg(InstancePtr, SaveRegsAddr[i], SavedRegs[i]);
}
}
/*****************************************************************************/
/**
* Initialize to handle hibernation event when it comes
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
*
* @return none
*
* @note None.
*
******************************************************************************/
void XUsbPsu_InitHibernation(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
InstancePtr->IsHibernated = 0U;
memset(ScratchBuf, 0U, sizeof(ScratchBuf));
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)ScratchBuf,
XUSBPSU_HIBER_SCRATCHBUF_SIZE);
}
XUsbPsu_SetupScratchpad(InstancePtr, ScratchBuf);
/* enable PHY suspend */
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0U));
RegVal |= XUSBPSU_GUSB2PHYCFG_SUSPHY;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0U), RegVal);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0U));
RegVal |= XUSBPSU_GUSB3PIPECTL_SUSPHY;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0U), RegVal);
}
/*****************************************************************************/
/**
* Handle hibernation event
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
*
* @return none
*
* @note None.
*
******************************************************************************/
void XUsbPsu_HibernationIntr(struct XUsbPsu *InstancePtr)
{
u8 EpNum;
u32 RegVal;
u32 retries;
XusbPsuLinkState LinkState;
/* sanity check */
switch(XUsbPsu_GetLinkState(InstancePtr)) {
case XUSBPSU_LINK_STATE_SS_DIS:
case XUSBPSU_LINK_STATE_U3:
break;
default:
/* fake hiber interrupt */
xil_printf("got fake interrupt\r\n");
return;
};
if (InstancePtr->Ep0State == XUSBPSU_EP0_SETUP_PHASE) {
XUsbPsu_StopTransfer(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, TRUE);
XUsbPsu_RecvSetup(InstancePtr);
}
/* stop active transfers for all endpoints including control
* endpoints force rm bit should be 0 when we do this */
for (EpNum = 0U; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) {
struct XUsbPsu_Ep *Ept;
Ept = &InstancePtr->eps[EpNum];
if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
continue;
}
/* save srsource index for later use */
XUsbPsu_StopTransfer(InstancePtr, Ept->UsbEpNum,
Ept->Direction, FALSE);
XUsbPsu_SaveEndpointState(InstancePtr, Ept);
}
/*
* ack events, don't process them; h/w decrements the count by the value
* written
*/
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U));
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U), RegVal);
InstancePtr->Evt.Count = 0U;
InstancePtr->Evt.Flags &= ~XUSBPSU_EVENT_PENDING;
if (XUsbPsu_Stop(InstancePtr) == XST_FAILURE) {
xil_printf("Failed to stop USB core\r\n");
return;
}
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
/* Check the link state and if it is disconnected, set
* KEEP_CONNECT to 0
*/
LinkState = XUsbPsu_GetLinkState(InstancePtr);
if (LinkState == XUSBPSU_LINK_STATE_SS_DIS) {
RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
/* update LinkState to be used while wakeup */
InstancePtr->LinkState = XUSBPSU_LINK_STATE_SS_DIS;
}
XUsbPsu_SaveRegs(InstancePtr);
/* ask core to save state */
RegVal |= XUSBPSU_DCTL_CSS;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
/* wait till core saves */
if (XUsbPsu_WaitClearTimeout(InstancePtr, XUSBPSU_DSTS,
XUSBPSU_DSTS_SSS, XUSBPSU_NON_STICKY_SAVE_RETRIES) ==
XST_FAILURE) {
xil_printf("Failed to save core state\r\n");
return;
}
/* Enable PME to wakeup from hibernation */
XUsbPsu_WriteVendorReg(XIL_PME_ENABLE, XIL_PME_ENABLE_SIG_GEN);
/* change power state to D3 */
XUsbPsu_WriteVendorReg(XIL_REQ_PWR_STATE, XIL_REQ_PWR_STATE_D3);
/* wait till current state is changed to D3 */
retries = (u32)XUSBPSU_PWR_STATE_RETRIES;
while (retries > 0U) {
RegVal = XUsbPsu_ReadVendorReg(XIL_CUR_PWR_STATE);
if ((RegVal & XIL_CUR_PWR_STATE_BITMASK) ==
XIL_CUR_PWR_STATE_D3) {
break;
}
XUsbPsu_Sleep(XUSBPSU_TIMEOUT);
retries = retries - 1U;
}
if (retries == 0U) {
xil_printf("Failed to change power state to D3\r\n");
return;
}
XUsbPsu_Sleep(XUSBPSU_TIMEOUT);
RegVal = XUsbPsu_ReadLpdReg(RST_LPD_TOP);
if (InstancePtr->ConfigPtr->DeviceId == (u16)XPAR_XUSBPSU_0_DEVICE_ID) {
XUsbPsu_WriteLpdReg(RST_LPD_TOP, RegVal | (u32)USB0_CORE_RST);
}
#if defined (XCLOCKING)
/* disable ref clocks */
if (InstancePtr->IsHibernated == 0) {
Xil_ClockDisable(InstancePtr->ConfigPtr->RefClk);
}
#endif
InstancePtr->IsHibernated = 1U;
xil_printf("Hibernated!\r\n");
}
/*****************************************************************************/
/**
* Core to restore non-sticky registers
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
*
* @return none
*
* @note None.
*
******************************************************************************/
s32 XUsbPsu_CoreRegRestore(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
XUsbPsu_SetupScratchpad(InstancePtr, ScratchBuf);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal |= XUSBPSU_DCTL_CRS;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
/* wait till non-sticky registers are restored */
if (XUsbPsu_WaitClearTimeout(InstancePtr, XUSBPSU_DSTS,
XUSBPSU_DSTS_RSS, XUSBPSU_NON_STICKY_SAVE_RETRIES) ==
XST_FAILURE) {
xil_printf("Failed to restore USB core\r\n");
return XST_FAILURE;
}
XUsbPsu_RestoreRegs(InstancePtr);
/* setup event buffers */
XUsbPsu_EventBuffersSetup(InstancePtr);
/* nothing to do when in OTG host mode */
if ((XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GSTS) &
XUSBPSU_GSTS_CUR_MODE) != (u32)0U) {
return XST_FAILURE;
}
if (XUsbPsu_RestoreEp0(InstancePtr) == XST_FAILURE) {
xil_printf("Failed to restore EP0\r\n");
return XST_FAILURE;
}
return XST_SUCCESS;
}
#endif /* XUSBPSU_HIBERNATION_ENABLE */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/usbpsu_v1_7/src/xusbpsu_ep0handler.c
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_ep0handler.c
* @addtogroup usbpsu_v1_7
* @{
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 pm 03/03/20 First release
* </pre>
*
*****************************************************************************/
/***************************** Include Files *********************************/
#include "xusbpsu_endpoint.h"
#include "xusbpsu_local.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
* Initiates DMA on Control Endpoint 0 to receive Setup packet.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return XST_SUCCESS else XST_FAILURE.
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr)
{
struct XUsbPsu_EpParams *Params;
struct XUsbPsu_Trb *TrbPtr;
struct XUsbPsu_Ep *Ept;
s32 Ret;
Xil_AssertNonvoid(InstancePtr != NULL);
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertNonvoid(Params != NULL);
/* Setup packet always on EP0 */
Ept = &InstancePtr->eps[0U];
if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
return (s32)XST_FAILURE;
}
TrbPtr = &InstancePtr->Ep0_Trb;
TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16U)
>> 16U;
TrbPtr->Size = 8U;
TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_SETUP;
TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
| XUSBPSU_TRB_CTRL_LST
| XUSBPSU_TRB_CTRL_IOC
| XUSBPSU_TRB_CTRL_ISP_IMI);
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)TrbPtr,
sizeof(struct XUsbPsu_Trb));
Xil_DCacheFlushRange((UINTPTR)&InstancePtr->SetupData,
sizeof(SetupPacket));
}
Params->Param0 = 0U;
Params->Param1 = (UINTPTR)TrbPtr;
InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
XUSBPSU_DEPCMD_STARTTRANSFER, Params);
if (Ret != XST_SUCCESS) {
return (s32)XST_FAILURE;
}
Ept->EpStatus |= XUSBPSU_EP_BUSY;
Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
Ept->UsbEpNum,
Ept->Direction);
return XST_SUCCESS;
}
/****************************************************************************/
/**
* Handles Transfer complete event of Control Endpoints EP0 OUT and EP0 IN.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is a pointer to the Endpoint event occurred in core.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event)
{
struct XUsbPsu_Ep *Ept;
SetupPacket *Ctrl;
u16 Length;
Ept = &InstancePtr->eps[Event->Epnumber];
Ctrl = &InstancePtr->SetupData;
Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
Ept->ResourceIndex = 0U;
switch (InstancePtr->Ep0State) {
case XUSBPSU_EP0_SETUP_PHASE:
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheInvalidateRange(
(INTPTR)&InstancePtr->SetupData,
sizeof(InstancePtr->SetupData));
}
Length = Ctrl->wLength;
if (Length == 0U) {
InstancePtr->IsThreeStage = 0U;
InstancePtr->ControlDir = XUSBPSU_EP_DIR_OUT;
} else {
InstancePtr->IsThreeStage = 1U;
InstancePtr->ControlDir = !!(Ctrl->bRequestType &
XUSBPSU_USB_DIR_IN);
}
Xil_AssertVoid(InstancePtr->Chapter9 != NULL);
InstancePtr->Chapter9(InstancePtr->AppData,
&InstancePtr->SetupData);
break;
case XUSBPSU_EP0_DATA_PHASE:
XUsbPsu_Ep0DataDone(InstancePtr, Event);
break;
case XUSBPSU_EP0_STATUS_PHASE:
XUsbPsu_Ep0StatusDone(InstancePtr);
break;
default:
/* Default case is a required MISRA-C guideline. */
break;
}
}
/****************************************************************************/
/**
* Handles Transfer Not Ready event of Control Endpoints EP0 OUT and EP0 IN.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is a pointer to the Endpoint event occurred in core.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event)
{
struct XUsbPsu_Ep *Ept;
Ept = &InstancePtr->eps[Event->Epnumber];
switch (Event->Status) {
case DEPEVT_STATUS_CONTROL_DATA:
/*
* We already have a DATA transfer in the controller's cache,
* if we receive a XferNotReady(DATA) we will ignore it, unless
* it's for the wrong direction.
*
* In that case, we must issue END_TRANSFER command to the Data
* Phase we already have started and issue SetStall on the
* control endpoint.
*/
if (Event->Epnumber != InstancePtr->ControlDir) {
XUsbPsu_Ep0_EndControlData(InstancePtr, Ept);
XUsbPsu_Ep0StallRestart(InstancePtr);
}
break;
case DEPEVT_STATUS_CONTROL_STATUS:
(void)XUsbPsu_Ep0StartStatus(InstancePtr, Event);
break;
default:
/* Default case is a required MIRSA-C guideline. */
break;
}
}
/****************************************************************************/
/**
* Initiates DMA to send data on Control Endpoint EP0 IN to Host.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param BufferPtr is pointer to data.
* @param BufferLen is Length of data buffer.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 BufferLen)
{
/* Control IN - EP1 */
struct XUsbPsu_EpParams *Params;
struct XUsbPsu_Ep *Ept;
struct XUsbPsu_Trb *TrbPtr;
s32 Ret;
Ept = &InstancePtr->eps[1U];
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertNonvoid(Params != NULL);
if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
return (s32)XST_FAILURE;
}
Ept->RequestedBytes = BufferLen;
Ept->BytesTxed = 0U;
Ept->BufferPtr = BufferPtr;
TrbPtr = &InstancePtr->Ep0_Trb;
TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16U) >> 16U;
TrbPtr->Size = BufferLen;
TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
| XUSBPSU_TRB_CTRL_LST
| XUSBPSU_TRB_CTRL_IOC
| XUSBPSU_TRB_CTRL_ISP_IMI);
Params->Param0 = 0U;
Params->Param1 = (UINTPTR)TrbPtr;
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)TrbPtr,
sizeof(struct XUsbPsu_Trb));
Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen);
}
InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_IN,
XUSBPSU_DEPCMD_STARTTRANSFER, Params);
if (Ret != XST_SUCCESS) {
return (s32)XST_FAILURE;
}
Ept->EpStatus |= XUSBPSU_EP_BUSY;
Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
Ept->UsbEpNum,
Ept->Direction);
return XST_SUCCESS;
}
/****************************************************************************/
/**
* Initiates DMA to receive data on Control Endpoint EP0 OUT from Host.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param BufferPtr is pointer to data.
* @param Length is Length of data to be received.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length)
{
struct XUsbPsu_EpParams *Params;
struct XUsbPsu_Ep *Ept;
struct XUsbPsu_Trb *TrbPtr;
u32 Size;
s32 Ret;
Ept = &InstancePtr->eps[0U];
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertNonvoid(Params != NULL);
if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
return (s32)XST_FAILURE;
}
Ept->RequestedBytes = Length;
Size = Length;
Ept->BytesTxed = 0U;
Ept->BufferPtr = BufferPtr;
/*
* 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
* must be a multiple of MaxPacketSize even if software is expecting a
* fixed non-multiple of MaxPacketSize transfer from the Host.
*/
if (!IS_ALIGNED(Length, Ept->MaxSize)) {
u16 TmpSize = Ept->MaxSize;
Size = (u32)roundup(Length, TmpSize);
Ept->UnalignedTx = 1U;
}
TrbPtr = &InstancePtr->Ep0_Trb;
TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16U) >> 16U;
TrbPtr->Size = Size;
TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
| XUSBPSU_TRB_CTRL_LST
| XUSBPSU_TRB_CTRL_IOC
| XUSBPSU_TRB_CTRL_ISP_IMI);
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)TrbPtr,
sizeof(struct XUsbPsu_Trb));
Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length);
}
Params->Param0 = 0U;
Params->Param1 = (UINTPTR)TrbPtr;
InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
XUSBPSU_DEPCMD_STARTTRANSFER, Params);
if (Ret != XST_SUCCESS) {
return (s32)XST_FAILURE;
}
Ept->EpStatus |= XUSBPSU_EP_BUSY;
Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
Ept->UsbEpNum, Ept->Direction);
return XST_SUCCESS;
}
#ifdef XUSBPSU_HIBERNATION_ENABLE
/*****************************************************************************/
/**
* Restarts EP0 endpoint
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
*
* @return XST_SUCCESS on success or else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
s32 XUsbPsu_RestoreEp0(struct XUsbPsu *InstancePtr)
{
struct XUsbPsu_Ep *Ept;
s32 Ret;
u8 EpNum;
for (EpNum = 0U; EpNum < 2U; EpNum++) {
Ept = &InstancePtr->eps[EpNum];
if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
continue;
}
Ret = XUsbPsu_EpEnable(InstancePtr, Ept->UsbEpNum,
Ept->Direction, Ept->MaxSize, Ept->Type, TRUE);
if (Ret == XST_FAILURE) {
return (s32)XST_FAILURE;
}
if ((Ept->EpStatus & XUSBPSU_EP_STALL) != (u32)0U) {
XUsbPsu_Ep0StallRestart(InstancePtr);
} else {
Ret = XUsbPsu_RestartEp(InstancePtr, Ept->PhyEpNum);
if (Ret == XST_FAILURE) {
return (s32)XST_FAILURE;
}
}
}
return (s32)XST_SUCCESS;
}
#endif /* #ifdef XUSBPSU_HIBERNATION_ENABLE */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_reset.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* Reset lines definitions: information needed to configure reset
* (configuration register address and mask, pointer to a function that performs
* a pulse on the reset line. If the function pointer points to NULL,
* PmResetPulse() function is called.
* Every reset line must have its entry in pmAllResets table.
*********************************************************************/
#include "xpfw_util.h"
#include "xpfw_default.h"
#include "xpfw_rom_interface.h"
#include "xpfw_resets.h"
#include "pm_reset.h"
#include "pm_defs.h"
#include "pm_common.h"
#include "pm_master.h"
#include "crl_apb.h"
#include "crf_apb.h"
#include "pmu_iomodule.h"
#include "sleep.h"
/**
* PmResetOps - Reset operations
* @assert Assert or release reset line
* @getStatus Get current status of reset line
* @pulse Function performing reset pulse operation
*/
typedef struct PmResetOps {
void (*const assert)(const PmReset* const rst, const u32 action);
u32 (*const getStatus)(const PmReset* const s);
u32 (*const pulse)(const PmReset* const rst);
} PmResetOps;
/**
* PmReset - Base structure containing information common to all reset lines
* @ops Pointer to the reset operations structure
* @access Access control bitmask (1 bit per master, see 'pmAllMasters')
* @derived Pointer to derived reset structure
*/
typedef struct PmReset {
const PmResetOps* const ops;
void* const derived;
u32 access;
} PmReset;
/**
* PmResetGeneric - Generic reset structure
* @rst Base reset structure
* @ctrlAddr Address of the reset control register
* @mask Bitmask of the control register
*/
typedef struct PmResetGeneric {
PmReset rst;
const u32 ctrlAddr;
const u32 mask;
} PmResetGeneric;
/**
* PmResetGpo - Reset structure used for PMU's GPO3 going to PL
* @rst Base reset structure
* @ctrlAddr Address of the reset control register
* @mask Bitmask of the control and status register
* @statusAddr Address of the reset status register
*/
typedef struct PmResetGpo {
PmReset rst;
const u32 ctrlAddr;
const u32 mask;
const u32 statusAddr;
} PmResetGpo;
/**
* PmResetRom - Reset which has dedicated PMU ROM function performing pulse
* @rst Base reset structure
* @ctrlAddr Address of the reset control register
* @mask Bitmask of the control register
* @pulseRom PMU ROM function performing pulse reset
*/
typedef struct PmResetRom {
PmReset rst;
u32 (*const pulseRom)(void);
const u32 ctrlAddr;
const u32 mask;
} PmResetRom;
/**
* PmResetGpioBankIOs - Reset structure used for GPIO Bank Input/Outputs
* @rst Base reset structure
* @rstLine GPIO Bank reset line number
*/
typedef struct PmResetGpioBankIOs {
PmReset rst;
const u32 rstMaskDataReg;
const u32 rstDirectionReg;
const u32 rstReadDataReg;
const bool isMaskDataLsw;
const u8 rstLine;
} PmResetGpioBankIOs;
bool PmResetMasterHasAccess(const PmMaster* const m, const PmReset* const r)
{
return !!(r->access & m->ipiMask);
}
/**
* PmResetAssertCommon() - Common assert handler
* @ctrlAddr Address of the reset control register
* @mask Bitmask of the control register
* @action States whether to assert or release reset line
*/
static void PmResetAssertCommon(const u32 ctrlAddr, const u32 mask,
const u32 action)
{
if (PM_RESET_ACTION_RELEASE == action) {
XPfw_RMW32(ctrlAddr, mask, 0U);
} else if (PM_RESET_ACTION_ASSERT == action) {
XPfw_RMW32(ctrlAddr, mask, mask);
}
}
/**
* PmResetGetStatusCommon() - Common function for getting reset status
* @addr Address of the reset status register
* @mask Bitmask of the status register
*/
static u32 PmResetGetStatusCommon(const u32 addr, const u32 mask)
{
u32 resetStatus = 0U;
if ((Xil_In32(addr) & mask) == mask) {
resetStatus = 1U;
}
return resetStatus;
}
/**
* PmResetPulseCommon() - Common function for performing reset pulse
* @ctrlAddr Address of the control register
* @mask Bitmask of the control register
*/
static u32 PmResetPulseCommon(const u32 ctrlAddr, const u32 mask)
{
XPfw_RMW32(ctrlAddr, mask, mask);
XPfw_RMW32(ctrlAddr, mask, 0U);
return XST_SUCCESS;
}
/**
* PmResetAssertGen() - Assert handler for PmResetGeneric reset class
* @rstPtr Pointer to the reset that needs to be asserted or released
* @action States whether to assert or release reset line
*/
static void PmResetAssertGen(const PmReset *const rstPtr, const u32 action)
{
const PmResetGeneric *rstGenPtr = (PmResetGeneric*)rstPtr->derived;
PmResetAssertCommon(rstGenPtr->ctrlAddr, rstGenPtr->mask, action);
}
/**
* PmResetGetStatusGen() - Get reset status handler of PmResetGeneric class
* @rstPtr Reset whose status should be returned
*
* @return Current reset status (0 - released, 1 - asserted)
*/
static u32 PmResetGetStatusGen(const PmReset *const rstPtr)
{
const PmResetGeneric *rstGenPtr = (PmResetGeneric*)rstPtr->derived;
return PmResetGetStatusCommon(rstGenPtr->ctrlAddr, rstGenPtr->mask);
}
/**
* PmResetPulseGen() - Pulse handler for PmResetGeneric class
* @rstPtr Pointer to the reset that needs to be toggled
*
* @return Operation success
*/
static u32 PmResetPulseGen(const PmReset *const rstPtr)
{
const PmResetGeneric *rstGenPtr = (PmResetGeneric*)rstPtr->derived;
return PmResetPulseCommon(rstGenPtr->ctrlAddr, rstGenPtr->mask);
}
/**
* PmResetAssertGpo() - Assert handler for PmResetGPO reset class
* @rstPtr Pointer to the reset line that needs to be asserted or released
* @action States whether to assert or release reset line
*/
static void PmResetAssertGpo(const PmReset *const rstPtr, const u32 action)
{
const PmResetGpo *rstGpoPtr = (PmResetGpo*)rstPtr->derived;
PmResetAssertCommon(rstGpoPtr->ctrlAddr, rstGpoPtr->mask, action);
}
/**
* PmResetGetStatusGpo() - Get reset status handler of PmResetGpo class
* @rstPtr Reset whose status should be returned
*
* @return Current reset status (0 - released, 1 - asserted)
*/
static u32 PmResetGetStatusGpo(const PmReset *const rstPtr)
{
const PmResetGpo *rstGpoPtr = (PmResetGpo*)rstPtr->derived;
return PmResetGetStatusCommon(rstGpoPtr->statusAddr, rstGpoPtr->mask);
}
/**
* PmResetPulseGpo() - Pulse handler for PmResetGpo class
* @rstPtr Pointer to the reset that needs to be toggled
*
* @return Operation success
*/
static u32 PmResetPulseGpo(const PmReset *const rstPtr)
{
const PmResetGpo *rstGpoPtr = (PmResetGpo*)rstPtr->derived;
return PmResetPulseCommon(rstGpoPtr->ctrlAddr, rstGpoPtr->mask);
}
/**
* PmResetAssertRom() - Assert handler for PmResetRom reset class
* @rstPtr Pointer to the reset line that needs to be asserted or released
* @action States whether to assert or release reset line
*/
static void PmResetAssertRom(const PmReset *const rstPtr, const u32 action)
{
const PmResetRom *rstRomPtr = (PmResetRom*)rstPtr->derived;
PmResetAssertCommon(rstRomPtr->ctrlAddr, rstRomPtr->mask, action);
}
/**
* PmResetGetStatusRom() - Get reset status handler of PmResetRom class
* @rstPtr Reset whose status should be returned
*
* @return Current reset status (0 - released, 1 - asserted)
*/
static u32 PmResetGetStatusRom(const PmReset *const rstPtr)
{
const PmResetRom *rstRomPtr = (PmResetRom*)rstPtr->derived;
return PmResetGetStatusCommon(rstRomPtr->ctrlAddr, rstRomPtr->mask);
}
/**
* PmResetPulseRom() - Pulse handler for PmResetRom class
* @rstPtr Pointer to the reset that needs to be toggled
*
* @return Operation success
*/
static u32 PmResetPulseRom(const PmReset *const rstPtr)
{
const PmResetRom *rstRomPtr = (PmResetRom*)rstPtr->derived;
return rstRomPtr->pulseRom();
}
/**
* PmResetGetStatusGpioBankIOs() - Get reset status handler for GPIO bank
* @rstPtr Pointer to the reset whose status should be returned
*
* @return Current reset status (0 - released, 1 - asserted)
*/
static u32 PmResetGetStatusGpioBankIOs(const PmReset* const rstPtr)
{
const PmResetGpioBankIOs *rstGpioPtr = (PmResetGpioBankIOs*)rstPtr->derived;
u32 RegShift = MAX_REG_BITS/2 + rstGpioPtr->rstLine;
u32 RegVal = 0;
/* Read the MIO/EMIO data register */
RegVal = Xil_In32(rstGpioPtr->rstReadDataReg);
return ((RegVal >> RegShift) & 1U);
}
/**
* PmResetPulseGpioBankIOs() - Pulse handler for PmResetGpioBankIOs class
* @rstPtr Pointer to the reset that needs to be toggled
*
* @return Operation success
*/
static u32 PmResetPulseGpioBankIOs(const PmReset* const rstPtr)
{
const PmResetGpioBankIOs *rstGpioPtr = (PmResetGpioBankIOs*)rstPtr->derived;
u32 GpioRstLine = rstGpioPtr->rstLine;
u32 GpioMaskDataReg = rstGpioPtr->rstMaskDataReg;
u32 GpioDirReg = rstGpioPtr->rstDirectionReg;
u32 RegVal = 0;
u32 MaskVal = 0;
u32 DirmShift = 0;
/* Set MIO/EMIO Direction */
if( rstGpioPtr->isMaskDataLsw == false ) {
DirmShift = MAX_REG_BITS/2;
}
RegVal = Xil_In32(GpioDirReg) | (1U << (DirmShift + GpioRstLine));
Xil_Out32(GpioDirReg, RegVal);
/* Assert the MIO/EMIO with the required Mask */
MaskVal = (1U << GpioRstLine) | GPIO_PIN_MASK_BITS;
RegVal = MaskVal & (~(1U << (MAX_REG_BITS/2 + GpioRstLine)));
Xil_Out32(GpioMaskDataReg, RegVal);
usleep(1000);
/* De-assert the MIO/EMIO with the required Mask */
RegVal = (~(1U << (MAX_REG_BITS/2 + GpioRstLine))) & GPIO_PIN_MASK_BITS;
Xil_Out32(GpioMaskDataReg, RegVal);
usleep(1000);
/* Assert the MIO/EMIO with the required Mask */
MaskVal = (1U << GpioRstLine) | GPIO_PIN_MASK_BITS;
RegVal = MaskVal & (~(1U << (MAX_REG_BITS/2 + GpioRstLine)));
Xil_Out32(GpioMaskDataReg, RegVal);
usleep(1000);
return XST_SUCCESS;
}
/**
* PmUserHookResetAssertPl() - Assert reset handler for PL
* @rstPtr Pointer to the PL reset structure
* @action States whether to assert or release reset
*/
#pragma weak PmUserHookResetAssertPl
void PmUserHookResetAssertPl(const PmReset *const rstPtr, const u32 action)
{
}
/**
* PmResetAssertPl() - Assert reset handler for PL
* @rstPtr Pointer to the PL reset structure
* @action States whether to assert or release reset
*/
static void PmResetAssertPl(const PmReset *const rstPtr, const u32 action)
{
PmUserHookResetAssertPl(rstPtr, action);
}
/**
* PmUserHookResetGetStatusPl() - Get PL reset status handler
* @rstPtr Pointer to PL reset structure
*
* @return Current reset status (0 - released, 1 - asserted)
*/
#pragma weak PmUserHookResetGetStatusPl
static u32 PmUserHookResetGetStatusPl(const PmReset *const rstPtr)
{
return 0;
}
/**
* PmResetGetStatusPl() - Get PL reset status handler
* @rstPtr Pointer to PL reset structure
*
* @return Current reset status (0 - released, 1 - asserted)
*/
static u32 PmResetGetStatusPl(const PmReset *const rstPtr)
{
return PmUserHookResetGetStatusPl(rstPtr);
}
/**
* PmUserHookResetPulsePl() - PL reset pulse handler
* @rstPtr Pointer to PL reset structure
*
* @return Operation status
*/
#pragma weak PmUserHookResetPulsePl
static u32 PmUserHookResetPulsePl(const PmReset* const rst)
{
return XST_SUCCESS;
}
/**
* PmResetPulsePl() - PL reset pulse handler
* @rstPtr Pointer to PL reset structure
*
* @return Operation status
*/
static u32 PmResetPulsePl(const PmReset* const rst)
{
return PmUserHookResetPulsePl(rst);
}
static const PmResetOps pmResetOpsGeneric = {
.assert = PmResetAssertGen,
.getStatus = PmResetGetStatusGen,
.pulse = PmResetPulseGen,
};
static const PmResetOps pmResetOpsGpo = {
.assert = PmResetAssertGpo,
.getStatus = PmResetGetStatusGpo,
.pulse = PmResetPulseGpo,
};
static const PmResetOps pmResetOpsRom = {
.assert = PmResetAssertRom,
.getStatus = PmResetGetStatusRom,
.pulse = PmResetPulseRom,
};
static const PmResetOps pmResetOpsNoAssert = {
.assert = NULL,
.getStatus = PmResetGetStatusRom,
.pulse = PmResetPulseRom,
};
static const PmResetOps pmResetOpsPl = {
.assert = PmResetAssertPl,
.getStatus = PmResetGetStatusPl,
.pulse = PmResetPulsePl,
};
static const PmResetOps pmResetOpsGpioBankIO = {
.assert = NULL,
.getStatus = PmResetGetStatusGpioBankIOs,
.pulse = PmResetPulseGpioBankIOs,
};
static PmResetGeneric pmResetPcieCfg = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetPcieCfg,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK,
};
static PmResetGeneric pmResetPcieBridge = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetPcieBridge,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK,
};
static PmResetRom pmResetPcieCtrl = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetPcieCtrl,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK,
.pulseRom = XpbrRstPCIeHandler,
};
static PmResetRom pmResetDp = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetDp,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_DP_RESET_MASK,
.pulseRom = XpbrRstDisplayPortHandler,
};
static PmResetGeneric pmResetSwdtCrf = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetSwdtCrf,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK,
};
static PmResetGeneric pmResetAfiFm5 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAfiFm5,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK,
};
static PmResetGeneric pmResetAfiFm4 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAfiFm4,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK,
};
static PmResetGeneric pmResetAfiFm3 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAfiFm3,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK,
};
static PmResetGeneric pmResetAfiFm2 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAfiFm2,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK,
};
static PmResetGeneric pmResetAfiFm1 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAfiFm1,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK,
};
static PmResetGeneric pmResetAfiFm0 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAfiFm0,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK,
};
static PmResetGeneric pmResetGdma = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetGdma,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK,
};
static PmResetRom pmResetGpuPp1 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetGpuPp1,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK,
.pulseRom = XpbrRstPp1Handler,
};
static PmResetRom pmResetGpuPp0 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetGpuPp0,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK,
.pulseRom = XpbrRstPp0Handler,
};
static PmResetRom pmResetGpu = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetGpu,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_GPU_RESET_MASK,
.pulseRom = XpbrRstGpuHandler,
};
static PmResetGeneric pmResetGt = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetGt,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_GT_RESET_MASK,
};
static PmResetRom pmResetSata = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetSata,
},
.ctrlAddr = CRF_APB_RST_FPD_TOP,
.mask = CRF_APB_RST_FPD_TOP_SATA_RESET_MASK,
.pulseRom = XpbrRstSataHandler,
};
static PmResetGeneric pmResetAcpu3Pwron = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAcpu3Pwron,
},
.ctrlAddr = CRF_APB_RST_FPD_APU,
.mask = CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_MASK,
};
static PmResetGeneric pmResetAcpu2Pwron = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAcpu2Pwron,
},
.ctrlAddr = CRF_APB_RST_FPD_APU,
.mask = CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_MASK,
};
static PmResetGeneric pmResetAcpu1Pwron = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAcpu1Pwron,
},
.ctrlAddr = CRF_APB_RST_FPD_APU,
.mask = CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_MASK,
};
static PmResetGeneric pmResetAcpu0Pwron = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAcpu0Pwron,
},
.ctrlAddr = CRF_APB_RST_FPD_APU,
.mask = CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_MASK,
};
static PmResetGeneric pmResetApuL2 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetApuL2,
},
.ctrlAddr = CRF_APB_RST_FPD_APU,
.mask = CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK,
};
static PmResetRom pmResetAcpu3 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetAcpu3,
},
.ctrlAddr = CRF_APB_RST_FPD_APU,
.mask = CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK,
.pulseRom = XpbrRstACPU3CPHandler,
};
static PmResetRom pmResetAcpu2 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetAcpu2,
},
.ctrlAddr = CRF_APB_RST_FPD_APU,
.mask = CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK,
.pulseRom = XpbrRstACPU2CPHandler,
};
static PmResetRom pmResetAcpu1 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetAcpu1,
},
.ctrlAddr = CRF_APB_RST_FPD_APU,
.mask = CRF_APB_RST_FPD_APU_ACPU1_RESET_MASK,
.pulseRom = XpbrRstACPU1CPHandler,
};
static PmResetRom pmResetAcpu0 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetAcpu0,
},
.ctrlAddr = CRF_APB_RST_FPD_APU,
.mask = CRF_APB_RST_FPD_APU_ACPU0_RESET_MASK,
.pulseRom = XpbrRstACPU0CPHandler,
};
static PmResetGeneric pmResetDDR = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetDDR,
},
.ctrlAddr = CRF_APB_RST_DDR_SS,
.mask = CRF_APB_RST_DDR_SS_DDR_RESET_MASK,
};
static PmResetGeneric pmResetApmFpd = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetApmFpd,
},
.ctrlAddr = CRF_APB_RST_DDR_SS,
.mask = CRF_APB_RST_DDR_SS_APM_RESET_MASK,
};
static PmResetGeneric pmResetSoft = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetSoft,
},
.ctrlAddr = CRL_APB_RESET_CTRL,
.mask = CRL_APB_RESET_CTRL_SOFT_RESET_MASK,
};
static PmResetRom pmResetGem0 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetGem0,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU0,
.mask = CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK,
.pulseRom = XpbrRstGem0Handler,
};
static PmResetRom pmResetGem1 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetGem1,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU0,
.mask = CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK,
.pulseRom = XpbrRstGem1Handler,
};
static PmResetRom pmResetGem2 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetGem2,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU0,
.mask = CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK,
.pulseRom = XpbrRstGem2Handler,
};
static PmResetRom pmResetGem3 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetGem3,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU0,
.mask = CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK,
.pulseRom = XpbrRstGem3Handler,
};
static PmResetGeneric pmResetQspi = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetQspi,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK,
};
static PmResetGeneric pmResetUart0 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetUart0,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK,
};
static PmResetGeneric pmResetUart1 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetUart1,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK,
};
static PmResetGeneric pmResetSpi0 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetSpi0,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK,
};
static PmResetGeneric pmResetSpi1 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetSpi1,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK,
};
static PmResetGeneric pmResetSdio0 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetSdio0,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK,
};
static PmResetGeneric pmResetSdio1 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetSdio1,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK,
};
static PmResetGeneric pmResetCan0 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetCan0,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK,
};
static PmResetGeneric pmResetCan1 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetCan1,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK,
};
static PmResetGeneric pmResetI2C0 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetI2C0,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK,
};
static PmResetGeneric pmResetI2C1 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetI2C1,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK,
};
static PmResetGeneric pmResetTtc0 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetTtc0,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK,
};
static PmResetGeneric pmResetTtc1 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetTtc1,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK,
};
static PmResetGeneric pmResetTtc2 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetTtc2,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK,
};
static PmResetGeneric pmResetTtc3 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetTtc3,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK,
};
static PmResetGeneric pmResetSwdtCrl = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetSwdtCrl,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK,
};
static PmResetGeneric pmResetNand = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetNand,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK,
};
static PmResetGeneric pmResetAdma = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAdma,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK,
};
static PmResetGeneric pmResetGpio = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetGpio,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK,
};
static PmResetGeneric pmResetIouCc = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetIouCc,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK,
};
static PmResetGeneric pmResetTimestamp = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetTimestamp,
},
.ctrlAddr = CRL_APB_RST_LPD_IOU2,
.mask = CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK,
};
static PmResetRom pmResetRpuR50 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetRpuR50,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
.pulseRom = XpbrRstR50Handler,
};
static PmResetRom pmResetRpuR51 = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetRpuR51,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
.pulseRom = XpbrRstR51Handler,
};
static PmResetGeneric pmResetRpuAmba = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetRpuAmba,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK,
};
static PmResetGeneric pmResetOcm = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetOcm,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_OCM_RESET_MASK,
};
static PmResetGeneric pmResetRpuPge = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetRpuPge,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK,
};
static PmResetRom pmResetUsb0Core = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetUsb0Core,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK,
.pulseRom = XpbrRstUsb0Handler,
};
static PmResetRom pmResetUsb1Core = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetUsb1Core,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK,
.pulseRom = XpbrRstUsb1Handler,
};
static PmResetGeneric pmResetUsb0Hiber = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetUsb0Hiber,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK,
};
static PmResetGeneric pmResetUsb1Hiber = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetUsb1Hiber,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK,
};
static PmResetGeneric pmResetUsb0Apb = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetUsb0Apb,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK,
};
static PmResetGeneric pmResetUsb1Apb = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetUsb1Apb,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK,
};
static PmResetGeneric pmResetIpi = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetIpi,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_IPI_RESET_MASK,
};
static PmResetGeneric pmResetApmLpd = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetApmLpd,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_APM_RESET_MASK,
};
static PmResetGeneric pmResetRtc = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetRtc,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_RTC_RESET_MASK,
};
static PmResetGeneric pmResetSysmon = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetSysmon,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK,
};
static PmResetGeneric pmResetAfiFm6 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetAfiFm6,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK,
};
static PmResetGeneric pmResetLpdSwdt = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetLpdSwdt,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK,
};
/**
* PmResetPulseFpd() - Gracefully cycle FPD reset
*
* @return Operation status
*/
static u32 PmResetPulseFpd(void)
{
return XPfw_ResetFpd();
}
static PmResetRom pmResetFpd = {
.rst = {
.ops = &pmResetOpsRom,
.access = 0U,
.derived = &pmResetFpd,
},
.ctrlAddr = CRL_APB_RST_LPD_TOP,
.mask = CRL_APB_RST_LPD_TOP_FPD_RESET_MASK,
.pulseRom = PmResetPulseFpd,
};
static PmResetGeneric pmResetRpuDbg1 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetRpuDbg1,
},
.ctrlAddr = CRL_APB_RST_LPD_DBG,
.mask = CRL_APB_RST_LPD_DBG_RPU_DBG1_RESET_MASK,
};
static PmResetGeneric pmResetRpuDbg0 = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetRpuDbg0,
},
.ctrlAddr = CRL_APB_RST_LPD_DBG,
.mask = CRL_APB_RST_LPD_DBG_RPU_DBG0_RESET_MASK,
};
static PmResetGeneric pmResetDbgLpd = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetDbgLpd,
},
.ctrlAddr = CRL_APB_RST_LPD_DBG,
.mask = CRL_APB_RST_LPD_DBG_DBG_LPD_RESET_MASK,
};
static PmResetGeneric pmResetDbgFpd = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetDbgFpd,
},
.ctrlAddr = CRL_APB_RST_LPD_DBG,
.mask = CRL_APB_RST_LPD_DBG_DBG_FPD_RESET_MASK,
};
static PmResetGeneric pmResetApll = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetApll,
},
.ctrlAddr = CRF_APB_APLL_CTRL,
.mask = CRF_APB_APLL_CTRL_RESET_MASK,
};
static PmResetGeneric pmResetDpll = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetDpll,
},
.ctrlAddr = CRF_APB_DPLL_CTRL,
.mask = CRF_APB_DPLL_CTRL_RESET_MASK,
};
static PmResetGeneric pmResetVpll = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetVpll,
},
.ctrlAddr = CRF_APB_VPLL_CTRL,
.mask = CRF_APB_VPLL_CTRL_RESET_MASK,
};
static PmResetGeneric pmResetIopll = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetIopll,
},
.ctrlAddr = CRL_APB_IOPLL_CTRL,
.mask = CRL_APB_IOPLL_CTRL_RESET_MASK,
};
static PmResetGeneric pmResetRpll = {
.rst = {
.ops = &pmResetOpsGeneric,
.access = 0U,
.derived = &pmResetRpll,
},
.ctrlAddr = CRL_APB_RPLL_CTRL,
.mask = CRL_APB_RPLL_CTRL_RESET_MASK,
};
static PmResetGpo pmResetGpo3Pl0 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl0,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_0_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl1 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl1,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_1_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl2 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl2,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_2_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl3 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl3,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_3_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl4 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl4,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_4_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl5 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl5,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_5_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl6 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl6,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_6_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl7 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl7,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_7_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl8 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl8,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_8_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl9 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl9,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_9_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl10 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl10,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_10_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl11 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl11,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_11_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl12 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl12,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_12_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl13 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl13,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_13_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl14 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl14,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_14_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl15 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl15,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_15_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl16 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl16,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_16_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl17 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl17,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_17_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl18 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl18,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_18_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl19 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl19,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_19_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl20 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl20,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_20_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl21 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl21,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_21_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl22 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl22,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_22_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl23 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl23,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_23_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl24 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl24,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_24_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl25 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl25,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_25_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl26 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl26,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_26_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl27 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl27,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_27_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl28 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl28,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_28_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl29 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl29,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_29_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl30 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl30,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_30_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
static PmResetGpo pmResetGpo3Pl31 = {
.rst = {
.ops = &pmResetOpsGpo,
.access = 0U,
.derived = &pmResetGpo3Pl31,
},
.ctrlAddr = PMU_IOMODULE_GPO3,
.mask = PMU_IOMODULE_GPO3_PL_GPO_31_MASK,
.statusAddr = PMU_LOCAL_GPO3_READ,
};
/*
* GPIO5 EMIO[95:92] are the reset lines going to PL
*/
static PmResetGpioBankIOs pmResetGpio5EMIO92 = {
.rst = {
.ops = &pmResetOpsGpioBankIO,
.access = 0U,
.derived = &pmResetGpio5EMIO92,
},
.rstMaskDataReg = GPIO_MASK_DATA_5_MSW_REG,
.rstDirectionReg = GPIO_DIRM_5,
.rstReadDataReg = GPIO_DATA_5_RO_REG,
.isMaskDataLsw = false,
.rstLine = GPIO5_EMIO92_MSW_DATA_BIT,
};
static PmResetGpioBankIOs pmResetGpio5EMIO93 = {
.rst = {
.ops = &pmResetOpsGpioBankIO,
.access = 0U,
.derived = &pmResetGpio5EMIO93,
},
.rstMaskDataReg = GPIO_MASK_DATA_5_MSW_REG,
.rstDirectionReg = GPIO_DIRM_5,
.rstReadDataReg = GPIO_DATA_5_RO_REG,
.isMaskDataLsw = false,
.rstLine = GPIO5_EMIO93_MSW_DATA_BIT,
};
static PmResetGpioBankIOs pmResetGpio5EMIO94 = {
.rst = {
.ops = &pmResetOpsGpioBankIO,
.access = 0U,
.derived = &pmResetGpio5EMIO94,
},
.rstMaskDataReg = GPIO_MASK_DATA_5_MSW_REG,
.rstDirectionReg = GPIO_DIRM_5,
.rstReadDataReg = GPIO_DATA_5_RO_REG,
.isMaskDataLsw = false,
.rstLine = GPIO5_EMIO94_MSW_DATA_BIT,
};
static PmResetGpioBankIOs pmResetGpio5EMIO95 = {
.rst = {
.ops = &pmResetOpsGpioBankIO,
.access = 0U,
.derived = &pmResetGpio5EMIO95,
},
.rstMaskDataReg = GPIO_MASK_DATA_5_MSW_REG,
.rstDirectionReg = GPIO_DIRM_5,
.rstReadDataReg = GPIO_DATA_5_RO_REG,
.isMaskDataLsw = false,
.rstLine = GPIO5_EMIO95_MSW_DATA_BIT,
};
/**
* PmResetPulsePsOnly() - Gracefully reset PS while PL remains active
*
* @return Operation status
*/
static u32 PmResetPulsePsOnly(void)
{
XPfw_ResetPsOnly();
return XST_SUCCESS;
}
static PmResetRom pmResetPsOnly = {
.rst = {
.ops = &pmResetOpsNoAssert,
.access = 0U,
.derived = &pmResetPsOnly,
},
.ctrlAddr = PMU_GLOBAL_GLOBAL_RESET,
.mask = PMU_GLOBAL_GLOBAL_RESET_PS_ONLY_RST_MASK,
.pulseRom = &PmResetPulsePsOnly,
};
/**
* PmResetPulseRpuLs() - Gracefully cycle the lock-step RPU reset
*
* @return Operation status
*/
static u32 PmResetPulseRpuLs(void)
{
return XPfw_ResetRpu();
}
static PmResetRom pmResetRpuLs = {
.rst = {
.ops = &pmResetOpsNoAssert,
.access = 0U,
.derived = &pmResetRpuLs,
},
.ctrlAddr = PMU_GLOBAL_GLOBAL_RESET,
.mask = PMU_GLOBAL_GLOBAL_RESET_RPU_LS_RST_MASK,
.pulseRom = PmResetPulseRpuLs,
};
static PmReset pmResetPl = {
.ops = &pmResetOpsPl,
.access = 0U,
.derived = &pmResetPl,
};
static PmReset* const pmAllResets[] = {
[PM_RESET_PCIE_CFG - PM_RESET_BASE] = &pmResetPcieCfg.rst,
[PM_RESET_PCIE_BRIDGE - PM_RESET_BASE] = &pmResetPcieBridge.rst,
[PM_RESET_PCIE_CTRL - PM_RESET_BASE] = &pmResetPcieCtrl.rst,
[PM_RESET_DP - PM_RESET_BASE] = &pmResetDp.rst,
[PM_RESET_SWDT_CRF - PM_RESET_BASE] = &pmResetSwdtCrf.rst,
[PM_RESET_AFI_FM5 - PM_RESET_BASE] = &pmResetAfiFm5.rst,
[PM_RESET_AFI_FM4 - PM_RESET_BASE] = &pmResetAfiFm4.rst,
[PM_RESET_AFI_FM3 - PM_RESET_BASE] = &pmResetAfiFm3.rst,
[PM_RESET_AFI_FM2 - PM_RESET_BASE] = &pmResetAfiFm2.rst,
[PM_RESET_AFI_FM1 - PM_RESET_BASE] = &pmResetAfiFm1.rst,
[PM_RESET_AFI_FM0 - PM_RESET_BASE] = &pmResetAfiFm0.rst,
[PM_RESET_GDMA - PM_RESET_BASE] = &pmResetGdma.rst,
[PM_RESET_GPU_PP1 - PM_RESET_BASE] = &pmResetGpuPp1.rst,
[PM_RESET_GPU_PP0 - PM_RESET_BASE] = &pmResetGpuPp0.rst,
[PM_RESET_GPU - PM_RESET_BASE] = &pmResetGpu.rst,
[PM_RESET_GT - PM_RESET_BASE] = &pmResetGt.rst,
[PM_RESET_SATA - PM_RESET_BASE] = &pmResetSata.rst,
[PM_RESET_ACPU3_PWRON - PM_RESET_BASE] = &pmResetAcpu3Pwron.rst,
[PM_RESET_ACPU2_PWRON - PM_RESET_BASE] = &pmResetAcpu2Pwron.rst,
[PM_RESET_ACPU1_PWRON - PM_RESET_BASE] = &pmResetAcpu1Pwron.rst,
[PM_RESET_ACPU0_PWRON - PM_RESET_BASE] = &pmResetAcpu0Pwron.rst,
[PM_RESET_APU_L2 - PM_RESET_BASE] = &pmResetApuL2.rst,
[PM_RESET_ACPU3 - PM_RESET_BASE] = &pmResetAcpu3.rst,
[PM_RESET_ACPU2 - PM_RESET_BASE] = &pmResetAcpu2.rst,
[PM_RESET_ACPU1 - PM_RESET_BASE] = &pmResetAcpu1.rst,
[PM_RESET_ACPU0 - PM_RESET_BASE] = &pmResetAcpu0.rst,
[PM_RESET_DDR - PM_RESET_BASE] = &pmResetDDR.rst,
[PM_RESET_APM_FPD - PM_RESET_BASE] = &pmResetApmFpd.rst,
[PM_RESET_SOFT - PM_RESET_BASE] = &pmResetSoft.rst,
[PM_RESET_GEM0 - PM_RESET_BASE] = &pmResetGem0.rst,
[PM_RESET_GEM1 - PM_RESET_BASE] = &pmResetGem1.rst,
[PM_RESET_GEM2 - PM_RESET_BASE] = &pmResetGem2.rst,
[PM_RESET_GEM3 - PM_RESET_BASE] = &pmResetGem3.rst,
[PM_RESET_QSPI - PM_RESET_BASE] = &pmResetQspi.rst,
[PM_RESET_UART0 - PM_RESET_BASE] = &pmResetUart0.rst,
[PM_RESET_UART1 - PM_RESET_BASE] = &pmResetUart1.rst,
[PM_RESET_SPI0 - PM_RESET_BASE] = &pmResetSpi0.rst,
[PM_RESET_SPI1 - PM_RESET_BASE] = &pmResetSpi1.rst,
[PM_RESET_SDIO0 - PM_RESET_BASE] = &pmResetSdio0.rst,
[PM_RESET_SDIO1 - PM_RESET_BASE] = &pmResetSdio1.rst,
[PM_RESET_CAN0 - PM_RESET_BASE] = &pmResetCan0.rst,
[PM_RESET_CAN1 - PM_RESET_BASE] = &pmResetCan1.rst,
[PM_RESET_I2C0 - PM_RESET_BASE] = &pmResetI2C0.rst,
[PM_RESET_I2C1 - PM_RESET_BASE] = &pmResetI2C1.rst,
[PM_RESET_TTC0 - PM_RESET_BASE] = &pmResetTtc0.rst,
[PM_RESET_TTC1 - PM_RESET_BASE] = &pmResetTtc1.rst,
[PM_RESET_TTC2 - PM_RESET_BASE] = &pmResetTtc2.rst,
[PM_RESET_TTC3 - PM_RESET_BASE] = &pmResetTtc3.rst,
[PM_RESET_SWDT_CRL - PM_RESET_BASE] = &pmResetSwdtCrl.rst,
[PM_RESET_NAND - PM_RESET_BASE] = &pmResetNand.rst,
[PM_RESET_ADMA - PM_RESET_BASE] = &pmResetAdma.rst,
[PM_RESET_GPIO - PM_RESET_BASE] = &pmResetGpio.rst,
[PM_RESET_IOU_CC - PM_RESET_BASE] = &pmResetIouCc.rst,
[PM_RESET_TIMESTAMP - PM_RESET_BASE] = &pmResetTimestamp.rst,
[PM_RESET_RPU_R50 - PM_RESET_BASE] = &pmResetRpuR50.rst,
[PM_RESET_RPU_R51 - PM_RESET_BASE] = &pmResetRpuR51.rst,
[PM_RESET_RPU_AMBA - PM_RESET_BASE] = &pmResetRpuAmba.rst,
[PM_RESET_OCM - PM_RESET_BASE] = &pmResetOcm.rst,
[PM_RESET_RPU_PGE - PM_RESET_BASE] = &pmResetRpuPge.rst,
[PM_RESET_USB0_CORERESET - PM_RESET_BASE] = &pmResetUsb0Core.rst,
[PM_RESET_USB1_CORERESET - PM_RESET_BASE] = &pmResetUsb1Core.rst,
[PM_RESET_USB0_HIBERRESET - PM_RESET_BASE] = &pmResetUsb0Hiber.rst,
[PM_RESET_USB1_HIBERRESET - PM_RESET_BASE] = &pmResetUsb1Hiber.rst,
[PM_RESET_USB0_APB - PM_RESET_BASE] = &pmResetUsb0Apb.rst,
[PM_RESET_USB1_APB - PM_RESET_BASE] = &pmResetUsb1Apb.rst,
[PM_RESET_IPI - PM_RESET_BASE] = &pmResetIpi.rst,
[PM_RESET_APM_LPD - PM_RESET_BASE] = &pmResetApmLpd.rst,
[PM_RESET_RTC - PM_RESET_BASE] = &pmResetRtc.rst,
[PM_RESET_SYSMON - PM_RESET_BASE] = &pmResetSysmon.rst,
[PM_RESET_AFI_FM6 - PM_RESET_BASE] = &pmResetAfiFm6.rst,
[PM_RESET_LPD_SWDT - PM_RESET_BASE] = &pmResetLpdSwdt.rst,
[PM_RESET_FPD - PM_RESET_BASE] = &pmResetFpd.rst,
[PM_RESET_RPU_DBG1 - PM_RESET_BASE] = &pmResetRpuDbg1.rst,
[PM_RESET_RPU_DBG0 - PM_RESET_BASE] = &pmResetRpuDbg0.rst,
[PM_RESET_DBG_LPD - PM_RESET_BASE] = &pmResetDbgLpd.rst,
[PM_RESET_DBG_FPD - PM_RESET_BASE] = &pmResetDbgFpd.rst,
[PM_RESET_APLL - PM_RESET_BASE] = &pmResetApll.rst,
[PM_RESET_DPLL - PM_RESET_BASE] = &pmResetDpll.rst,
[PM_RESET_VPLL - PM_RESET_BASE] = &pmResetVpll.rst,
[PM_RESET_IOPLL - PM_RESET_BASE] = &pmResetIopll.rst,
[PM_RESET_RPLL - PM_RESET_BASE] = &pmResetRpll.rst,
[PM_RESET_GPO3_PL_0 - PM_RESET_BASE] = &pmResetGpo3Pl0.rst,
[PM_RESET_GPO3_PL_1 - PM_RESET_BASE] = &pmResetGpo3Pl1.rst,
[PM_RESET_GPO3_PL_2 - PM_RESET_BASE] = &pmResetGpo3Pl2.rst,
[PM_RESET_GPO3_PL_3 - PM_RESET_BASE] = &pmResetGpo3Pl3.rst,
[PM_RESET_GPO3_PL_4 - PM_RESET_BASE] = &pmResetGpo3Pl4.rst,
[PM_RESET_GPO3_PL_5 - PM_RESET_BASE] = &pmResetGpo3Pl5.rst,
[PM_RESET_GPO3_PL_6 - PM_RESET_BASE] = &pmResetGpo3Pl6.rst,
[PM_RESET_GPO3_PL_7 - PM_RESET_BASE] = &pmResetGpo3Pl7.rst,
[PM_RESET_GPO3_PL_8 - PM_RESET_BASE] = &pmResetGpo3Pl8.rst,
[PM_RESET_GPO3_PL_9 - PM_RESET_BASE] = &pmResetGpo3Pl9.rst,
[PM_RESET_GPO3_PL_10 - PM_RESET_BASE] = &pmResetGpo3Pl10.rst,
[PM_RESET_GPO3_PL_11 - PM_RESET_BASE] = &pmResetGpo3Pl11.rst,
[PM_RESET_GPO3_PL_12 - PM_RESET_BASE] = &pmResetGpo3Pl12.rst,
[PM_RESET_GPO3_PL_13 - PM_RESET_BASE] = &pmResetGpo3Pl13.rst,
[PM_RESET_GPO3_PL_14 - PM_RESET_BASE] = &pmResetGpo3Pl14.rst,
[PM_RESET_GPO3_PL_15 - PM_RESET_BASE] = &pmResetGpo3Pl15.rst,
[PM_RESET_GPO3_PL_16 - PM_RESET_BASE] = &pmResetGpo3Pl16.rst,
[PM_RESET_GPO3_PL_17 - PM_RESET_BASE] = &pmResetGpo3Pl17.rst,
[PM_RESET_GPO3_PL_18 - PM_RESET_BASE] = &pmResetGpo3Pl18.rst,
[PM_RESET_GPO3_PL_19 - PM_RESET_BASE] = &pmResetGpo3Pl19.rst,
[PM_RESET_GPO3_PL_20 - PM_RESET_BASE] = &pmResetGpo3Pl20.rst,
[PM_RESET_GPO3_PL_21 - PM_RESET_BASE] = &pmResetGpo3Pl21.rst,
[PM_RESET_GPO3_PL_22 - PM_RESET_BASE] = &pmResetGpo3Pl22.rst,
[PM_RESET_GPO3_PL_23 - PM_RESET_BASE] = &pmResetGpo3Pl23.rst,
[PM_RESET_GPO3_PL_24 - PM_RESET_BASE] = &pmResetGpo3Pl24.rst,
[PM_RESET_GPO3_PL_25 - PM_RESET_BASE] = &pmResetGpo3Pl25.rst,
[PM_RESET_GPO3_PL_26 - PM_RESET_BASE] = &pmResetGpo3Pl26.rst,
[PM_RESET_GPO3_PL_27 - PM_RESET_BASE] = &pmResetGpo3Pl27.rst,
[PM_RESET_GPO3_PL_28 - PM_RESET_BASE] = &pmResetGpo3Pl28.rst,
[PM_RESET_GPO3_PL_29 - PM_RESET_BASE] = &pmResetGpo3Pl29.rst,
[PM_RESET_GPO3_PL_30 - PM_RESET_BASE] = &pmResetGpo3Pl30.rst,
[PM_RESET_GPO3_PL_31 - PM_RESET_BASE] = &pmResetGpo3Pl31.rst,
[PM_RESET_RPU_LS - PM_RESET_BASE] = &pmResetRpuLs.rst,
[PM_RESET_PS_ONLY - PM_RESET_BASE] = &pmResetPsOnly.rst,
[PM_RESET_PL - PM_RESET_BASE] = &pmResetPl,
[PM_RESET_GPIO5_EMIO_92 - PM_RESET_BASE] = &pmResetGpio5EMIO92.rst,
[PM_RESET_GPIO5_EMIO_93 - PM_RESET_BASE] = &pmResetGpio5EMIO93.rst,
[PM_RESET_GPIO5_EMIO_94 - PM_RESET_BASE] = &pmResetGpio5EMIO94.rst,
[PM_RESET_GPIO5_EMIO_95 - PM_RESET_BASE] = &pmResetGpio5EMIO95.rst,
};
/**
* PmGetResetById() - Find reset that matches a given reset ID
* @resetId ID of the reset to find
*
* @return Pointer to PmReset structure (or NULL if not found)
*/
PmReset* PmGetResetById(const u32 resetId)
{
PmReset* resetPtr = NULL;
if (resetId >= (ARRAY_SIZE(pmAllResets) + PM_RESET_BASE)) {
/* Reset id is higher than maximum */
goto done;
}
if (resetId < PM_RESET_BASE) {
/* Reset id is smaller than minimum */
goto done;
}
resetPtr = pmAllResets[resetId - PM_RESET_BASE];
done:
return resetPtr;
}
s32 PmResetDoAssert(const PmReset *reset, u32 action)
{
s32 status = XST_SUCCESS;
switch (action) {
case PM_RESET_ACTION_RELEASE:
case PM_RESET_ACTION_ASSERT:
if (NULL != reset->ops->assert) {
reset->ops->assert(reset, action);
} else {
status = XST_INVALID_PARAM;
}
break;
case PM_RESET_ACTION_PULSE:
reset->ops->pulse(reset);
break;
default:
PmWarn("invalid assert %lu\r\n", action);
status = XST_INVALID_PARAM;
break;
};
return status;
}
/**
* PmResetAssertInt() - Configure reset line
* @reset ID of reset to be configured
* @action Specifies the action (assert, release, pulse)
*/
s32 PmResetAssertInt(u32 reset, u32 action)
{
s32 status;
const PmReset *resetPtr = PmGetResetById(reset);
if (NULL == resetPtr) {
PmWarn("Invalid reset %lu\r\n", reset);
status = XST_INVALID_PARAM;
goto err;
}
status = PmResetDoAssert(resetPtr, action);
err:
return status;
}
inline u32 PmResetGetStatusInt(const PmReset* const resetPtr, u32 *status)
{
int ret = XST_NO_FEATURE;
if (resetPtr->ops->getStatus) {
*status = resetPtr->ops->getStatus(resetPtr);
ret = XST_SUCCESS;
}
return ret;
}
/**
* PmResetSetConfig() - Set configuration for reset control
* @resetId ID of the reset whose permissions should be set
* @permissions Permissions to set (ORed IPI masks of permissible masters)
*
* @return XST_INVALID_PARAM if reset with given ID is not found,
* XST_SUCCESS if permissions are set
*/
s32 PmResetSetConfig(const u32 resetId, const u32 permissions)
{
s32 status = XST_SUCCESS;
PmReset* rst = PmGetResetById(resetId);
if (NULL == rst) {
status = XST_INVALID_PARAM;
goto done;
}
rst->access = permissions;
done:
return status;
}
/**
* PmResetClearConfig() - Clear configuration for all resets
*/
void PmResetClearConfig(void)
{
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmAllResets); i++) {
pmAllResets[i]->access = 0U;
}
}
#endif
<file_sep>/python_drivers/james_board_eth_test.py
# -*- coding: utf-8 -*-
"""
Created on Tue Jun 30 20:50:01 2020
@author: tianlab01
"""
#!/usr/bin/python # This is client.py file
import socket # Import socket module
s = socket.socket() # Create a socket object
host = "192.168.3.11" # Get local machine name
port = 7 # Reserve a port for your service.
s.connect((host, port))
s.send(b'\xe8\x03\x03\x03\x03\x55')
res = s.recv(6)
print("Got: " + str(res) )
s.close() <file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/avbuf_v2_3/src/xavbuf_videoformats.c
/*******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xavbuf_videoformats.c
* @addtogroup xavbuf_v2_3
* @{
*
* Contains attributes of the video formats mapped to the hardware
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 aad 03/10/17 Initial release.
* 2.0 aad 02/22/18 Fixed scaling factors and bits per pixel
* </pre>
*
*******************************************************************************/
/******************************* Include Files ********************************/
#include "xavbuf.h"
#ifdef __cplusplus
extern "C" {
#endif
/**************************** Variable Definitions ****************************/
const XAVBuf_VideoAttribute XAVBuf_SupportedFormats[XAVBUF_NUM_SUPPORTED] = {
/* Non - Live Video Formats */
{ CbY0CrY1, 0, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ CrY0CbY1, 1, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ Y0CrY1Cb, 2, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ Y0CbY1Cr, 3, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ YV16, 4, Planar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ YV24, 5, Planar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, FALSE, FALSE, 24},
{ YV16Ci, 6, SemiPlanar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ MONOCHROME, 7, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 8},
{ YV16Ci2, 8, SemiPlanar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, TRUE, 16},
{ YUV444, 9, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, FALSE, FALSE, 24},
{ RGB888, 10, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 24},
{ RGBA8880, 11, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 32},
{ RGB888_10BPC, 12, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
FALSE, TRUE, FALSE, 30},
{ YUV444_10BPC, 13, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
FALSE, FALSE, FALSE, 30},
{ YV16Ci2_10BPC, 14, SemiPlanar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, TRUE, 20},
{ YV16Ci_10BPC, 15, SemiPlanar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 20},
{ YV16_10BPC, 16, Planar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 20},
{ YV24_10BPC, 17, Planar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
FALSE, FALSE, FALSE, 30},
{ MONOCHROME_10BPC, 18, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 10},
{ YV16_420, 19, Planar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ YV16Ci_420, 20, SemiPlanar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 16},
{ YV16Ci2_420, 21, SemiPlanar,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, TRUE, 16},
{ YV16_420_10BPC, 22, Planar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 20},
{ YV16Ci_420_10BPC, 23, SemiPlanar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 20},
{ YV16Ci2_420_10BPC, 24, SemiPlanar,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, TRUE, 20},
/* Non-Live Graphics formats */
{ RGBA8888, 0, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 32},
{ ABGR8888, 1, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 32},
{ RGB888_GFX, 2, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 24},
{ BGR888, 3, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 24},
{ RGBA5551, 4, Interleaved,
{XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_5BIT_SF},
FALSE, TRUE, FALSE, 16},
{ RGBA4444, 5, Interleaved,
{XAVBUF_BUF_4BIT_SF, XAVBUF_BUF_4BIT_SF, XAVBUF_BUF_4BIT_SF},
FALSE, TRUE, FALSE, 16},
{ RGB565, 6, Interleaved,
{XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_5BIT_SF},
FALSE, TRUE, FALSE, 16},
{ BPP8, 7, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 8},
{ BPP4, 8, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 4},
{ BPP2, 9, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 2},
{ BPP1, 10, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 1},
{ YUV422, 11, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, FALSE, FALSE, 24},
/* Video Formats for Live Video/Graphics input and output sources */
{ RGB_6BPC, 0, Interleaved,
{XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF},
FALSE, TRUE, FALSE, 18},
{ RGB_8BPC, 0, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, TRUE, FALSE, 24},
{ RGB_10BPC, 0, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
FALSE, TRUE, FALSE, 30},
{ RGB_12BPC, 0, Interleaved,
{XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF},
FALSE, TRUE, FALSE, 36},
{ YCbCr444_6BPC, 1, Interleaved,
{XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF},
FALSE, FALSE, FALSE, 18},
{ YCbCr444_8BPC, 1, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
FALSE, FALSE, FALSE, 24},
{ YCbCr444_10BPC, 1, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
FALSE, FALSE, FALSE, 30},
{ YCbCr444_12BPC, 1, Interleaved,
{XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF},
FALSE, FALSE, FALSE, 36},
{ YCbCr422_8BPC, 2, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 24},
{ YCbCr422_10BPC, 2, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 30},
{ YCbCr422_12BPC, 2, Interleaved,
{XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF},
TRUE, FALSE, FALSE, 36},
{ YOnly_8BPC, 3, Interleaved,
{XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF},
TRUE, FALSE, FALSE, 24},
{ YOnly_10BPC, 3, Interleaved,
{XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF},
TRUE, FALSE, FALSE, 30},
{ YOnly_12BPC, 3, Interleaved,
{XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF},
TRUE, FALSE, FALSE, 36},
};
#ifdef __cplusplus
}
#endif
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_subsystem.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_SUBSYSTEM_H_
#define XPM_SUBSYSTEM_H_
#include "xpm_defs.h"
#include "xstatus.h"
#ifdef __cplusplus
extern "C" {
#endif
#define INVALID_SUBSYSID (0xFFFFFFFFU)
/**
* Subsystem specific flags.
*/
#define SUBSYSTEM_INIT_FINALIZED (1U << 0U)
/**
* Subsystem creation states.
*/
typedef enum {
OFFLINE,
RESERVED,
ONLINE,
SUSPENDING,
SUSPENDED,
POWERED_OFF,
MAX_STATE
} XPm_SubsysState;
typedef struct XPm_Subsystem XPm_Subsystem;
/**
* The subsystem class.
*/
struct XPm_Subsystem {
u32 Id; /**< Subsystem ID */
u8 State; /**< Subsystem state */
u8 Flags; /**< Subsystem specific flags */
u32 IpiMask;
struct XPm_Reqm *Requirements;
/**< Head of the requirement list for all devices. */
void (*NotifyCb)(u32 SubsystemId, const u32 EventId);
XPm_Subsystem *NextSubsystem;
};
/************************** Function Prototypes ******************************/
u32 XPmSubsystem_GetIPIMask(u32 SubsystemId);
u32 XPmSubsystem_GetSubSysIdByIpiMask(u32 IpiMask);
XStatus XPm_IsWakeAllowed(u32 SubsystemId, u32 NodeId);
XStatus XPm_IsAccessAllowed(u32 SubsystemId, u32 NodeId);
XStatus XPmSubsystem_SetState(const u32 SubsystemId, const u32 State);
XStatus XPmSubsystem_Add(u32 SubsystemId);
XStatus XPmSubsystem_Destroy(u32 SubsystemId);
XStatus XPmSubsystem_IsAllProcDwn(u32 SubsystemId);
XStatus XPm_IsForcePowerDownAllowed(u32 SubsystemId, u32 NodeId);
XStatus XPmSubsystem_ForceDownCleanup(u32 SubsystemId);
int XPmSubsystem_InitFinalize(const u32 SubsystemId);
int XPmSubsystem_Idle(u32 SubsystemId);
XPm_Subsystem *XPmSubsystem_GetById(u32 SubsystemId);
XPm_Subsystem *XPmSubsystem_GetByIndex(u32 SubSysIdx);
XStatus XPmSubsystem_SetCurrent(u32 SubsystemId);
u32 XPmSubsystem_GetCurrent(void);
XStatus XPmSubsystem_Restart(u32 SubsystemId);
XStatus XPmSubsystem_GetStatus(const u32 SubsystemId, const u32 DeviceId,
XPm_DeviceStatus *const DeviceStatus);
u32 XPmSubsystem_GetMaxSubsysIdx(void);
#ifdef __cplusplus
}
#endif
#endif /* XPM_SUBSYSTEM_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_master.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* This file contains PM master related data structures and
* functions for accessing them.
*********************************************************************/
#include "pm_master.h"
#include "pm_proc.h"
#include "pm_defs.h"
#include "pm_callbacks.h"
#include "pm_notifier.h"
#include "pm_system.h"
#include "pm_sram.h"
#include "pm_ddr.h"
#include "pm_requirement.h"
#include "pmu_global.h"
#include "pm_node_reset.h"
#include "pm_clock.h"
#include "xpfw_restart.h"
#include "xpfw_ipi_manager.h"
#define SUBSYSTEM_RESTART_MASK BIT(16U)
#define PM_REQUESTED_SUSPEND 0x1U
#define TO_ACK_CB(ack, status) (REQUEST_ACK_NON_BLOCKING == (ack))
#define TCM_HIVEC_BKP_LOCATION 0xFFFFFFC0U
#define HIVEC_TO_RESORE_CODE_BRANCH_OPCODE 0xEA003FBEU
#define DEFINE_PM_PROCS(c) .procs = ((c)), \
.procsCnt = ARRAY_SIZE((c))
#if defined(PM_LOG_LEVEL) && (PM_LOG_LEVEL > 0)
#define DEFINE_MASTER_NAME(n) .name = n
#else
#define DEFINE_MASTER_NAME(n) .name = ""
#endif
static PmMaster* pmMasterHead = NULL;
/* Restore code structure*/
typedef struct RPURestoreCode {
unsigned int AddrLocation;
unsigned int RestoreData;
}RPURestoreCode;
static const RPURestoreCode RestoreCode[6] = {
// ldr r0,=0xFFFFFFC0
{ .AddrLocation = 0XFFFFFF00U, .RestoreData = 0XE3E0003FU },
// ldr r1, [r0]
{ .AddrLocation = 0XFFFFFF04U, .RestoreData = 0XE5901000U },
// ldr r0, [pc, #4]; ~0x14
{ .AddrLocation = 0XFFFFFF08U, .RestoreData = 0XE59F0004U },
// str r1, [r0]
{ .AddrLocation = 0XFFFFFF0CU, .RestoreData = 0XE5801000U },
// b 0xFFFC0000
{ .AddrLocation = 0XFFFFFF10U, .RestoreData = 0XEAFF003AU },
// =0xFFFF0000
{ .AddrLocation = 0XFFFFFF14U, .RestoreData = PM_PROC_RPU_HIVEC_ADDR },
};
static const PmSlave* pmApuMemories[] = {
&pmSlaveOcm0_g.slv,
&pmSlaveOcm1_g.slv,
&pmSlaveOcm2_g.slv,
&pmSlaveOcm3_g.slv,
&pmSlaveDdr_g,
NULL,
};
/**
* PmApuPrepareSuspendToRam() - Prepare the APU data structs for suspend to RAM
*/
static s32 PmApuPrepareSuspendToRam(void)
{
s32 status;
u32 i;
PmRequirement* req = PmRequirementGet(&pmMasterApu_g, &pmSlaveL2_g.slv);
if (NULL == req) {
status = XST_FAILURE;
goto done;
}
status = PmRequirementSchedule(req, 0U);
if (XST_SUCCESS != status) {
goto done;
}
if (NULL == pmMasterApu_g.memories) {
goto done;
}
i = 0U;
while (NULL != pmMasterApu_g.memories[i]) {
req = PmRequirementGet(&pmMasterApu_g,
pmMasterApu_g.memories[i]);
if (NULL == req) {
status = XST_FAILURE;
goto done;
}
status = PmRequirementSchedule(req, PM_CAP_CONTEXT);
i++;
}
done:
return status;
}
/**
* PmApuEvaluateState() - Evaluate state specified by the APU master for itself
* @state State argument to be evaluated (specified as the argument of the
* self suspend call)
*
* @return XST_SUCCESS if state is supported
* XST_NO_FEATURE if state is not supported
* Error code if requirements are not properly set for a slave
*/
static s32 PmApuEvaluateState(const u32 state)
{
s32 status;
switch (state) {
case PM_APU_STATE_CPU_IDLE:
status = XST_SUCCESS;
break;
case PM_APU_STATE_SUSPEND_TO_RAM:
status = PmApuPrepareSuspendToRam();
break;
default:
status = XST_NO_FEATURE;
break;
}
return status;
}
/**
* PmMasterRpuRemapAddr() - Remap address from RPU's (lockstep) to PMU's view
* @address Address to remap
*
* @return Remapped address or the provided address if no remapping done
*/
static u32 PmMasterRpuRemapAddr(const u32 address)
{
u32 remapAddr = address;
if (address < (4U * pmSlaveTcm0A_g.size)) {
remapAddr += pmSlaveTcm0A_g.base;
}
return remapAddr;
}
/**
* PmMasterRpu0RemapAddr() - Remap address from RPU_0's to PMU's view
* @address Address to remap
*
* @return Remapped address or the provided address if no remapping done
*/
static u32 PmMasterRpu0RemapAddr(const u32 address)
{
u32 remapAddr = address;
if (address < pmSlaveTcm0A_g.size) {
remapAddr += pmSlaveTcm0A_g.base;
} else {
if ((address >= (2U * pmSlaveTcm0A_g.size)) &&
(address < ((2U * pmSlaveTcm0A_g.size) + pmSlaveTcm0B_g.size))) {
remapAddr += pmSlaveTcm0B_g.base;
}
}
return remapAddr;
}
/**
* PmMasterRpu1RemapAddr() - Remap address from RPU_1's to PMU's view
* @address Address to remap
*
* @return Remapped address or the provided address if no remapping done
*/
static u32 PmMasterRpu1RemapAddr(const u32 address)
{
u32 remapAddr = address;
if (address < pmSlaveTcm1A_g.size) {
remapAddr += pmSlaveTcm1A_g.base;
} else {
if ((address >= (2U * pmSlaveTcm1A_g.size)) &&
(address < ((2U * pmSlaveTcm1A_g.size) + pmSlaveTcm1B_g.size))) {
remapAddr += pmSlaveTcm1B_g.base;
}
}
return remapAddr;
}
static PmProc* pmMasterApuProcs[] = {
&pmProcApu0_g,
&pmProcApu1_g,
&pmProcApu2_g,
&pmProcApu3_g,
};
PmMaster pmMasterApu_g = {
DEFINE_PM_PROCS(pmMasterApuProcs),
.wakeProc = NULL,
.nid = NODE_APU,
.ipiMask = IPI_PMU_0_IER_APU_MASK,
.reqs = NULL,
.nextMaster = NULL,
.wakePerms = 0U,
.suspendPerms = 0U,
.suspendTimeout = 0U,
.suspendRequest = {
.initiator = NULL,
.acknowledge = 0U,
},
.state = PM_MASTER_STATE_UNINITIALIZED,
.gic = &pmGicProxy,
.memories = pmApuMemories,
.evalState = PmApuEvaluateState,
.remapAddr = NULL,
DEFINE_MASTER_NAME("APU")
};
static PmProc* pmMasterRpuProcs[] = {
&pmProcRpu0_g,
};
/* RPU in lockstep mode */
PmMaster pmMasterRpu_g = {
DEFINE_PM_PROCS(pmMasterRpuProcs),
.wakeProc = NULL,
.nextMaster = NULL,
.nid = NODE_RPU,
.ipiMask = IPI_PMU_0_IER_RPU_0_MASK,
.reqs = NULL,
.wakePerms = 0U,
.suspendPerms = 0U,
.suspendTimeout = 0U,
.suspendRequest = {
.initiator = NULL,
.acknowledge = 0U,
},
.state = PM_MASTER_STATE_UNINITIALIZED,
.gic = NULL,
.memories = NULL,
.evalState = NULL,
.remapAddr = PmMasterRpuRemapAddr,
DEFINE_MASTER_NAME("RPU")
};
static PmProc* pmMasterRpu0Procs[] = {
&pmProcRpu0_g,
};
/* RPU in split mode can have 2 masters: RPU_0 and RPU_1 */
PmMaster pmMasterRpu0_g = {
DEFINE_PM_PROCS(pmMasterRpu0Procs),
.wakeProc = NULL,
.nextMaster = NULL,
.nid = NODE_RPU_0,
.ipiMask = 0U,
.reqs = NULL,
.wakePerms = 0U,
.suspendPerms = 0U,
.suspendTimeout = 0U,
.suspendRequest = {
.initiator = NULL,
.acknowledge = 0U,
},
.state = PM_MASTER_STATE_UNINITIALIZED,
.gic = NULL,
.memories = NULL,
.evalState = NULL,
.remapAddr = PmMasterRpu0RemapAddr,
DEFINE_MASTER_NAME("RPU0"),
};
static PmProc* pmMasterRpu1Procs[] = {
&pmProcRpu1_g,
};
PmMaster pmMasterRpu1_g = {
DEFINE_PM_PROCS(pmMasterRpu1Procs),
.wakeProc = NULL,
.nid = NODE_RPU_1,
.ipiMask = 0U,
.reqs = NULL,
.nextMaster = NULL,
.wakePerms = 0U,
.suspendPerms = 0U,
.suspendTimeout = 0U,
.suspendRequest = {
.initiator = NULL,
.acknowledge = 0U,
},
.state = PM_MASTER_STATE_UNINITIALIZED,
.gic = NULL,
.memories = NULL,
.evalState = NULL,
.remapAddr = PmMasterRpu1RemapAddr,
DEFINE_MASTER_NAME("RPU1"),
};
/* Array of all possible masters supported by the PFW */
static PmMaster *const pmMastersAll[] = {
&pmMasterApu_g,
&pmMasterRpu_g, /* RPU lockstep */
&pmMasterRpu0_g, /* RPU split mode, core 0 */
&pmMasterRpu1_g, /* RPU split mode, core 1 */
};
/**
* PmMasterAdd() - Add new master in the list
* @newMaster Master to be added in the list
*/
static void PmMasterAdd(PmMaster* const newMaster)
{
newMaster->nextMaster = pmMasterHead;
pmMasterHead = newMaster;
}
/**
* PmMasterDefaultConfig() - Add default masters (call only upon PM init)
*/
void PmMasterDefaultConfig(void)
{
PmMasterAdd(&pmMasterApu_g);
PmMasterAdd(&pmMasterRpu_g);
}
/**
* PmMasterSetConfig() - Set configuration for a master
* @mst Master for which the configuration is set
* @cfg Configuration data to set
*
* @note Master is automatically added in the list of available masters
*/
void PmMasterSetConfig(PmMaster* const mst, const PmMasterConfig* const cfg)
{
u32 i;
mst->ipiMask = cfg->ipiMask;
mst->suspendTimeout = cfg->suspendTimeout;
mst->suspendPerms = cfg->suspendPerms;
mst->wakePerms = cfg->wakePerms;
PmMasterAdd(mst);
/* Update pointers of processors to the master */
for (i = 0U; i < mst->procsCnt; i++) {
mst->procs[i]->master = mst;
}
}
void PmMasterClearConfig(void)
{
PmMaster* mst = pmMasterHead;
while (NULL != mst) {
PmMaster* next;
/* Clear the configuration of the master */
mst->wakeProc = 0U;
mst->ipiMask = 0U;
mst->wakePerms = 0U;
mst->suspendPerms = 0U;
mst->suspendTimeout = 0U;
mst->suspendRequest.initiator = NULL;
mst->suspendRequest.acknowledge = 0U;
/* Clear requirements of the master */
mst->reqs = NULL;
/* Clear the pointer to the next master */
next = mst->nextMaster;
mst->nextMaster = NULL;
/* Process next master */
mst = next;
}
/* Delete the list of available masters */
pmMasterHead = NULL;
/* Free allocated requirements from the heap */
PmRequirementFreeAll();
}
/**
* PmGetMasterByIpiMask() - Use to get pointer to master structure by ipi mask
* @mask IPI Mask of a master (requestor) in IPI registers
*
* @return Pointer to a PmMaster structure or NULL if master is not found
*/
PmMaster* PmGetMasterByIpiMask(const u32 mask)
{
PmMaster* mst = pmMasterHead;
while (NULL != mst) {
if (0U != (mask & mst->ipiMask)) {
break;
}
mst = mst->nextMaster;
}
return mst;
}
/**
* PmMasterGetNextFromIpiMask() - Get next master from ORed masters' IPI mask
* @mask Mask from which we need to extract a master
*
* @return Pointer to a master of NULL if mask does not encode a master
*
* @note The argument represents ORed IPI masks of multiple (or none)
* masters, where each master is encoded by a set bit. If a pointer
* to the master is found, the associated bitfield in the mask is
* cleared.
*/
PmMaster* PmMasterGetNextFromIpiMask(u32* const mask)
{
PmMaster* master = NULL;
u32 masterCnt = __builtin_popcount(*mask);
u32 ipiMask;
if (0U == masterCnt) {
goto done;
}
ipiMask = 1U << __builtin_ctz(*mask);
master = PmGetMasterByIpiMask(ipiMask);
*mask &= ~ipiMask;
done:
return master;
}
/**
* PmGetProcOfThisMaster() - Get processor pointer with given node id, if
* such processor exist within the master
* @master Master within which the search is performed
* @nodeId Node of the processor to be found
*
* @return Pointer to processor with the given node id (which is within the
* master), or NULL if such processor is not found.
*/
PmProc* PmGetProcOfThisMaster(const PmMaster* const master,
const PmNodeId nodeId)
{
u32 i;
PmProc *proc = NULL;
for (i = 0U; i < master->procsCnt; i++) {
if (nodeId == master->procs[i]->node.nodeId) {
proc = master->procs[i];
}
}
return proc;
}
/**
* PmGetProcByWfiStatus() - Get processor struct by wfi interrupt status
* @mask WFI interrupt mask read from GPI2 register
*
* @return Pointer to a processor structure whose wfi mask is provided, or
* NULL if processor is not found
*/
PmProc* PmGetProcByWfiStatus(const u32 mask)
{
PmProc *proc = NULL;
PmMaster* mst = pmMasterHead;
while (NULL != mst) {
u32 p;
for (p = 0U; p < mst->procsCnt; p++) {
if (0U != (mask & mst->procs[p]->mask)) {
proc = mst->procs[p];
goto done;
}
}
mst = mst->nextMaster;
}
done:
return proc;
}
/**
* PmMasterConfigWakeEvents() - Configure wake events for the master
* @master Master for which wake events should be configured
* @enable Flag (true to enable event propagation, false otherwise)
*
* @note Config method of the wake event class must ensure that only set
* wake gets enabled/disabled.
*/
static void PmMasterConfigWakeEvents(PmMaster* const master, const bool enable)
{
PmRequirement* req = master->reqs;
while (NULL != req) {
PmWakeEvent* we = req->slave->wake;
if ((NULL != we) && (NULL != we->class)) {
if (NULL != we->class->config) {
we->class->config(we, master->ipiMask, enable);
}
}
req = req->nextSlave;
}
}
/**
* PmWakeUpCancelScheduled() - Cancel scheduled wake-up sources of the master
* @master Pointer to a master whose scheduled wake-up sources should be
* cancelled
*/
static void PmWakeUpCancelScheduled(PmMaster* const master)
{
PmRequirement* req = master->reqs;
while (NULL != req) {
req->info &= ~PM_MASTER_WAKEUP_REQ_MASK;
req = req->nextSlave;
}
/* Clear all wake-up sources */
if (NULL != master->gic) {
master->gic->clear();
}
PmMasterConfigWakeEvents(master, 0U);
}
/**
* PmCanRequestSuspend() - Check whether master is privileged to request another
* master to suspend
* @reqMaster Master which requests another master to suspend
* @respMaster Master whose suspend is requested and which is extected to
* response to the request by initiating its own self suspend
*
* @return Check result
* - True if master has privilege to request suspend
* - False if master has no privilege
*/
bool PmCanRequestSuspend(const PmMaster* const reqMaster,
const PmMaster* const respMaster)
{
return 0U != (reqMaster->ipiMask & respMaster->suspendPerms);
}
/**
* PmIsRequestedToSuspend() - Check whether the master is requested from some
* other master to suspend
* @master Master to check for
*
* @return Check result
* - True if master is requested to suspend
* - False if no other master has requested this master to suspend
*/
bool PmIsRequestedToSuspend(const PmMaster* const master)
{
return NULL != master->suspendRequest.initiator;
}
/**
* PmMasterSuspendAck() - Acknowledge to the suspend request of another master
* @mst Master which is responding to the suspend request
* @response Status which is acknowledged as a response (whether the suspend
* operation is performed successfully)
* @return Status of the operation of sending acknowledge:
* - XST_SUCCESS if before calling this function the caller checked
* that PmIsRequestedToSuspend returns true (the acknowledge
* may need to be sent)
* - XST_FAILURE otherwise - this function didn't suppose to be
* called
*/
s32 PmMasterSuspendAck(PmMaster* const mst, const s32 response)
{
s32 status = XST_SUCCESS;
if (NULL == mst->suspendRequest.initiator) {
status = XST_FAILURE;
goto done;
}
if (REQUEST_ACK_NON_BLOCKING == mst->suspendRequest.acknowledge) {
PmAcknowledgeCb(mst->suspendRequest.initiator,
mst->procs[0]->node.nodeId, response,
mst->procs[0]->node.currState);
} else if (REQUEST_ACK_BLOCKING == mst->suspendRequest.acknowledge) {
IPI_RESPONSE1(mst->ipiMask, response);
} else {
/* No acknowledge */
}
mst->suspendRequest.initiator = NULL;
done:
return status;
}
/**
* PmMasterLastProcSuspending() - Check is the last awake processor suspending
* @master Master holding array of processors to be checked
* @return TRUE if there is exactly one processor in suspending state and
* all others are in sleep or forced power down.
* FALSE otherwise
*/
static bool PmMasterLastProcSuspending(const PmMaster* const master)
{
bool status = false;
u32 sleeping = 0U;
u32 i;
for (i = 0U; i < master->procsCnt; i++) {
if (NODE_IS_OFF(&master->procs[i]->node)) {
/* Count how many processors is down */
sleeping++;
} else {
/* Assume the one processor is suspending */
status = PmProcIsSuspending(master->procs[i]);
}
}
/* If the number of asleep/down processors mismatch return false */
if (master->procsCnt != (1U + sleeping)) {
status = false;
}
/* Return whether the last standing processor is in suspending state */
return status;
}
/**
* PmMasterAllProcsDown() - Check if all processors are in sleep or forced down
* @master Master holding array of processors to be checked
* @return TRUE if all processors are in either sleep or forced down state
* FALSE otherwise
*/
static bool PmMasterAllProcsDown(const PmMaster* const master)
{
bool status = true;
u32 i;
for (i = 0U; i < master->procsCnt; i++) {
if (false == NODE_IS_OFF(&master->procs[i]->node)) {
status = false;
}
}
return status;
}
/**
* PmWakeMasterBySlave() - Wake the master for which slave is set as
* wakeup source
* @slave Slave which set as wakeup source
*
* @return Status of performing wake
*/
s32 PmWakeMasterBySlave(const PmSlave * const slave)
{
PmMaster *mst = pmMasterHead;
s32 finalStatus = XST_SUCCESS;
s32 status;
while (mst) {
PmRequirement *masterReq = PmRequirementGet(mst, slave);
if ((masterReq->info & PM_MASTER_WAKEUP_REQ_MASK) != 0U) {
status = PmMasterWake(mst);
if (status != XST_SUCCESS) {
finalStatus = XST_FAILURE;
}
}
mst = mst->nextMaster;
}
return finalStatus;
}
/**
* PmMasterWakeProc() - Master prepares for wake and wakes the processor
* @proc Processor to wake up
*
* @return Status of performing wake
*/
s32 PmMasterWakeProc(PmProc* const proc)
{
s32 status;
bool hasResumeAddr = PmProcHasResumeAddr(proc);
if (false == hasResumeAddr) {
status = XST_FAILURE;
goto done;
}
status = PmMasterFsm(proc->master, PM_MASTER_EVENT_WAKE);
if (XST_SUCCESS != status) {
goto done;
}
status = PmProcFsm(proc, PM_PROC_EVENT_WAKE);
done:
return status;
}
/**
* PmMasterForceDownProcs() - Force down processors of this master
* @master Master whose processors need to be forced down
*
* @return Status of forcing down
*/
static s32 PmMasterForceDownProcs(const PmMaster* const master)
{
u32 i;
s32 status = XST_SUCCESS;
for (i = 0U; i < master->procsCnt; i++) {
s32 ret = PmNodeForceDown(&master->procs[i]->node);
if (XST_SUCCESS != ret) {
status = ret;
}
}
return status;
}
/**
* PmMasterForceDownCleanup() - Cleanup due to the force down
* @master Master being forced down
*
* @return Status of performing cleanup (releasing resources)
*/
static s32 PmMasterForceDownCleanup(PmMaster* const master)
{
s32 status;
status = PmRequirementRelease(master->reqs, RELEASE_ALL);
PmWakeUpCancelScheduled(master);
PmNotifierUnregisterAll(master);
master->wakeProc = NULL;
master->suspendRequest.initiator = NULL;
return status;
}
/**
* PmMasterIdleSlaves() - Idle and reset active slaves of a master
* @master Master whose slaves need to be idled and reset
*
* @note Idle and reset slaves which have an active clock and
* - Are not requested by any other master and this master is
uninitialized, or
- Are exclusively used by this master
*/
static void PmMasterIdleSlaves(PmMaster* const master)
{
#ifdef ENABLE_NODE_IDLING
PmRequirement* req = master->reqs;
PmNode* Node;
PmInfo("%s idle slaves\r\n", master->name);
while (NULL != req) {
u32 usage = PmSlaveGetUsageStatus(req->slave, master);
Node = &req->slave->node;
if (0U == (Node->flags & NODE_IDLE_DONE)) {
if (((PM_MASTER_STATE_UNINITIALIZED == master->state) &&
(0U == (usage & PM_USAGE_OTHER_MASTER))) ||
(usage == PM_USAGE_CURRENT_MASTER)) {
if (XST_SUCCESS == PmClockIsActive(Node)) {
PmNodeReset(master, Node->nodeId,
NODE_IDLE_REQ);
Node->flags |= NODE_IDLE_DONE;
}
}
}
req = req->nextSlave;
}
#endif
}
/**
* PmMasterFsm() - Implements finite state machine (FSM) for a master
* @master Master whose state machine is triggered
* @event Event to which the master's state machine need to react
*
* @return Status of changing state
*/
s32 PmMasterFsm(PmMaster* const master, const PmMasterEvent event)
{
s32 status = XST_SUCCESS;
bool condition;
u8 prevState = master->state;
switch (event) {
case PM_MASTER_EVENT_SELF_SUSPEND:
condition = PmMasterLastProcSuspending(master);
if ((PM_MASTER_STATE_ACTIVE == master->state) &&
(true == condition)) {
master->state = PM_MASTER_STATE_SUSPENDING;
}
break;
case PM_MASTER_EVENT_SLEEP:
if (PM_MASTER_STATE_SUSPENDING == master->state) {
#ifdef ENABLE_POS
bool isPoS = PmSystemDetectPowerOffSuspend(master);
if (true == isPoS) {
status = PmSystemPreparePowerOffSuspend();
}
#endif
status = PmRequirementUpdateScheduled(master, true);
master->state = PM_MASTER_STATE_SUSPENDED;
condition = PmIsRequestedToSuspend(master);
if (true == condition) {
status = PmMasterSuspendAck(master, XST_SUCCESS);
}
PmMasterConfigWakeEvents(master, 1U);
#ifdef ENABLE_POS
if (true == isPoS) {
status = PmSystemFinalizePowerOffSuspend();
}
#endif
}
break;
case PM_MASTER_EVENT_ABORT_SUSPEND:
if (PM_MASTER_STATE_SUSPENDING == master->state) {
PmRequirementCancelScheduled(master);
PmWakeUpCancelScheduled(master);
master->state = PM_MASTER_STATE_ACTIVE;
}
break;
case PM_MASTER_EVENT_WAKE:
if (PM_MASTER_STATE_SUSPENDED == master->state) {
status = PmRequirementUpdateScheduled(master, false);
if (XST_SUCCESS == status) {
PmWakeUpCancelScheduled(master);
}
} else if (PM_MASTER_STATE_KILLED == master->state) {
PmRequirementPreRequest(master);
status = PmRequirementUpdateScheduled(master, false);
if (XST_SUCCESS == status) {
PmRequirementClockRestore(master);
}
} else {
/* Must have else branch due to MISRA */
}
if (PM_MASTER_STATE_UNINITIALIZED != master->state) {
master->state = PM_MASTER_STATE_ACTIVE;
}
break;
case PM_MASTER_EVENT_FORCED_PROC:
condition = PmMasterAllProcsDown(master);
if (true == condition) {
PmMasterIdleSlaves(master);
status = PmMasterForceDownCleanup(master);
master->state = PM_MASTER_STATE_KILLED;
}
break;
case PM_MASTER_EVENT_FORCE_DOWN:
master->state = PM_MASTER_STATE_KILLED;
status = PmMasterForceDownProcs(master);
if (XST_SUCCESS == status) {
if (PM_MASTER_STATE_UNINITIALIZED == prevState) {
master->state = PM_MASTER_STATE_UNINITIALIZED;
}
PmMasterIdleSlaves(master);
if (PM_MASTER_STATE_UNINITIALIZED != prevState) {
status = PmMasterForceDownCleanup(master);
}
}
break;
default:
status = XST_PM_INTERNAL;
PmErr("Unknown event #%d\r\n", event);
break;
}
return status;
}
/**
* PmMasterWake() - Wake up the subsystem (master knows which processor to wake)
* @mst Master whose processor shall be woken up
* @return Status of the wake-up operation
*/
s32 PmMasterWake(const PmMaster* const mst)
{
s32 status;
PmProc* proc = mst->wakeProc;
if (NULL == proc) {
proc = mst->procs[0];
}
status = PmMasterWakeProc(proc);
return status;
}
/**
* PmGetStartAddress() - Get master hand off address for restart
* @master Master to restart
* @address Hand off address
*
* @return Void
*/
void PmGetStartAddress (PmMaster* const master, u64 *address)
{
if (master == &pmMasterRpu_g || master == &pmMasterRpu0_g) {
u32 i;
*address = PM_PROC_RPU_HIVEC_ADDR; /* Highvec */
/* Backup of HiVec memory */
XPfw_Write32(TCM_HIVEC_BKP_LOCATION,
XPfw_Read32(PM_PROC_RPU_HIVEC_ADDR));
/* Branch to restore location */
XPfw_Write32(PM_PROC_RPU_HIVEC_ADDR,
HIVEC_TO_RESORE_CODE_BRANCH_OPCODE);
/*
* Code to restore HiVec and branch to FSBL
*/
for (i = 0; i < ARRAYSIZE(RestoreCode); i++) {
XPfw_Write32(RestoreCode[i].AddrLocation,
RestoreCode[i].RestoreData);
}
} else {
*address = FSBL_LOAD_ADDR;
}
}
/**
* PmMasterRestart() - Restart the master
* @master Master to restart
*
* @return Status of performing the operation
*/
s32 PmMasterRestart(PmMaster* const master)
{
s32 status;
u64 address = 0xFFFC0000ULL;
u32 FsblProcInfo = XPfw_Read32(PMU_GLOBAL_GLOBAL_GEN_STORAGE5);
if ((FSBL_RUNNING_ON_A53 == (FsblProcInfo & FSBL_STATE_PROC_INFO_MASK)) &&
(master == &pmMasterApu_g)) {
#if defined(USE_DDR_FOR_APU_RESTART) && defined(ENABLE_SECURE)
if (0x0U != (FsblProcInfo & FSBL_ENCRYPTION_STS_MASK)) {
if (FSBL_Store_Restore_Info.IsOCM_Used == TRUE) {
/* If FSBL is encrypted, it is not copied to DDR */
PmWarn("OCM is used by XilFPGA. APU-restart will not work\r\n");
status = XST_FAILURE;
goto done;
} else {
/* Do nothing */
}
} else {
status = XPfw_RestoreFsblToOCM();
if (XST_SUCCESS != status) {
goto done;
}
}
#else
if (FSBL_Store_Restore_Info.IsOCM_Used == TRUE) {
/* If OCM is used by XilFPGA, APU restart will not work */
PmWarn("OCM is used by XilFPGA. APU-restart will not work\r\n");
status = XST_FAILURE;
goto done;
}
#endif
} else if (((FSBL_RUNNING_ON_R5_0 == (FsblProcInfo & FSBL_STATE_PROC_INFO_MASK)) &&
(master == &pmMasterRpu0_g)) ||
((FSBL_RUNNING_ON_R5_L == (FsblProcInfo & FSBL_STATE_PROC_INFO_MASK)) &&
(master == &pmMasterRpu_g))) {
/* Do nothing */
} else {
status = XST_NO_FEATURE;
goto done;
}
XPfw_RecoveryAck(master);
PmSystemPrepareForRestart(master);
status = PmMasterFsm(master, PM_MASTER_EVENT_FORCE_DOWN);
if (XST_SUCCESS != status) {
goto done;
}
status = PmMasterFsm(master, PM_MASTER_EVENT_WAKE);
if (XST_SUCCESS != status) {
goto done;
}
XPfw_RMW32(PMU_GLOBAL_GLOBAL_GEN_STORAGE4, SUBSYSTEM_RESTART_MASK,
SUBSYSTEM_RESTART_MASK);
PmGetStartAddress (master, &address);
#ifdef ENABLE_POS
/* Signal to FSBL */
XPfw_Write32(PMU_GLOBAL_GLOBAL_GEN_STORAGE1, 1U);
#endif
status = master->procs[0]->saveResumeAddr(master->procs[0], address);
if (XST_SUCCESS != status) {
goto done;
}
status = PmProcFsm(master->procs[0], PM_PROC_EVENT_WAKE);
PmSystemRestartDone(master);
done:
return status;
}
/**
* PmMasterGetPlaceholder() - Check whether there is a master which holds nodeId
* @nodeId Id of the node whose placeholder should be found
*
* @return Pointer to the master if such exist, otherwise NULL
*/
PmMaster* PmMasterGetPlaceholder(const PmNodeId nodeId)
{
PmMaster* holder = NULL;
u32 i;
/* Find the master with the node placeholder */
for (i = 0U; i < ARRAY_SIZE(pmMastersAll); i++) {
if (nodeId == pmMastersAll[i]->nid) {
holder = pmMastersAll[i];
break;
}
}
return holder;
}
/**
* PmMasterCanForceDown() - Check if master has permissions to force power down
* the power node
* @master Master which wants to force power down the node
* @power Target power node
*
* @return True if master has permission to force power down the node,
* false otherwise
*/
inline bool PmMasterCanForceDown(const PmMaster* const master,
const PmPower* const power)
{
return 0U != (power->forcePerms & master->ipiMask);
}
#ifdef IDLE_PERIPHERALS
void PmMasterIdleSystem(void)
{
PmMaster* mst = pmMasterHead;
while (NULL != mst) {
PmMasterIdleSlaves(mst);
mst = mst->nextMaster;
}
}
#endif
/**
* PmMasterInitFinalize() - Master has completed initialization, finalize init
* @master Master which has finalized initialization
*/
s32 PmMasterInitFinalize(PmMaster* const master)
{
s32 status;
master->state = PM_MASTER_STATE_ACTIVE;
status = PmRequirementRelease(master->reqs, RELEASE_UNREQUESTED);
return status;
}
#ifdef ENABLE_POS
/**
* PmMasterIsLastSuspending() - Check if master is in suspending state and all
* other masters in system are suspended or killed
* @master Master to be checked
*
* @return True if master is in suspending state and all other masters are
* killed or suspended, false otherwise
*/
bool PmMasterIsLastSuspending(const PmMaster* const master)
{
PmMaster* mst = pmMasterHead;
bool isLastWake = true;
while (NULL != mst) {
if (master == mst) {
if (mst->state == PM_MASTER_STATE_SUSPENDING) {
mst = mst->nextMaster;
continue;
} else {
isLastWake = false;
break;
}
}
if ((mst->state != PM_MASTER_STATE_SUSPENDED) &&
(mst->state != PM_MASTER_STATE_KILLED)) {
isLastWake = false;
break;
}
mst = mst->nextMaster;
}
return isLastWake;
}
/**
* @PmMasterIsUniqueWakeup() - Check if any device except slave is used as
* wakeup source in system
*
* @slave Slave node to be checked
*
* @return True if slave is the unique wakeup source used in system, false
* otherwise
*/
bool PmMasterIsUniqueWakeup(const PmSlave* const slave)
{
PmMaster* mst = pmMasterHead;
bool isUnique = false;
while (NULL != mst) {
PmRequirement* req = mst->reqs;
while (NULL != req) {
if ((PM_MASTER_WAKEUP_REQ_MASK & req->info) != 0U) {
if (req->slave != slave) {
isUnique = false;
goto done;
} else {
isUnique = true;
}
}
req = req->nextSlave;
}
mst = mst->nextMaster;
}
done:
return isUnique;
}
/**
* @PmMasterReleaseAll() - Release all requirements for every master in system
*
* @return Status of releasing all requirements for every master in system
*/
s32 PmMasterReleaseAll(void)
{
s32 status = 0;
PmMaster* mst = pmMasterHead;
while (NULL != mst) {
status = PmRequirementRelease(mst->reqs, RELEASE_ALL);
if (XST_SUCCESS != status) {
goto done;
}
mst = mst->nextMaster;
}
done:
return status;
}
#endif
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_periph.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
#include "pm_periph.h"
#include "pm_common.h"
#include "pm_node.h"
#include "pm_master.h"
#include "xpfw_rom_interface.h"
#include "lpd_slcr.h"
#include "pm_gic_proxy.h"
#include "pm_requirement.h"
#include "pm_sram.h"
/* Always-on slave has only one state */
#define PM_AON_SLAVE_STATE 0U
static const u8 pmAonFsmStates[] = {
[PM_AON_SLAVE_STATE] = PM_CAP_WAKEUP | PM_CAP_ACCESS | PM_CAP_CONTEXT,
};
static const PmSlaveFsm pmSlaveAonFsm = {
DEFINE_SLAVE_STATES(pmAonFsmStates),
.trans = NULL,
.transCnt = 0U,
.enterState = NULL,
};
static u8 pmSlaveAonPowers[] = {
DEFAULT_POWER_ON,
};
#define PM_GENERIC_SLAVE_STATE_UNUSED 0U
#define PM_GENERIC_SLAVE_STATE_RUNNING 1U
/* Generic slaves state transition latency values */
#define PM_GENERIC_SLAVE_UNUSED_TO_RUNNING_LATENCY 304U
#define PM_GENERIC_SLAVE_RUNNING_TO_UNUSED_LATENCY 6U
static const u8 pmGenericSlaveStates[] = {
[PM_GENERIC_SLAVE_STATE_UNUSED] = 0U,
[PM_GENERIC_SLAVE_STATE_RUNNING] = PM_CAP_CONTEXT | PM_CAP_WAKEUP |
PM_CAP_ACCESS | PM_CAP_CLOCK | PM_CAP_POWER,
};
static const PmStateTran pmGenericSlaveTransitions[] = {
{
.fromState = PM_GENERIC_SLAVE_STATE_RUNNING,
.toState = PM_GENERIC_SLAVE_STATE_UNUSED,
.latency = PM_GENERIC_SLAVE_RUNNING_TO_UNUSED_LATENCY,
}, {
.fromState = PM_GENERIC_SLAVE_STATE_UNUSED,
.toState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latency = PM_GENERIC_SLAVE_UNUSED_TO_RUNNING_LATENCY,
},
};
static u8 pmGenericSlavePowers[] = {
DEFAULT_POWER_OFF,
DEFAULT_POWER_ON,
};
static const PmSlaveFsm pmGenericSlaveFsm = {
DEFINE_SLAVE_STATES(pmGenericSlaveStates),
DEFINE_SLAVE_TRANS(pmGenericSlaveTransitions),
.enterState = NULL,
};
static PmWakeEventGicProxy pmRtcWake = {
.wake = {
.derived = &pmRtcWake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC27_MASK |
LPD_SLCR_GICP0_IRQ_MASK_SRC26_MASK,
.group = 0U,
};
PmSlave pmSlaveRtc_g = {
.node = {
.derived = &pmSlaveRtc_g,
.nodeId = NODE_RTC,
.class = &pmNodeClassSlave_g,
.parent = NULL,
.clocks = NULL,
.currState = PM_AON_SLAVE_STATE,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmSlaveAonPowers),
DEFINE_NODE_NAME("rtc"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmRtcWake.wake,
.slvFsm = &pmSlaveAonFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmTtc0Wake = {
.wake = {
.derived = &pmTtc0Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP1_IRQ_MASK_SRC6_MASK |
LPD_SLCR_GICP1_IRQ_MASK_SRC5_MASK |
LPD_SLCR_GICP1_IRQ_MASK_SRC4_MASK,
.group = 1U,
};
PmSlave pmSlaveTtc0_g = {
.node = {
.derived = &pmSlaveTtc0_g,
.nodeId = NODE_TTC_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ttc0"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmTtc0Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmTtc1Wake = {
.wake = {
.derived = &pmTtc1Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP1_IRQ_MASK_SRC9_MASK |
LPD_SLCR_GICP1_IRQ_MASK_SRC8_MASK |
LPD_SLCR_GICP1_IRQ_MASK_SRC7_MASK,
.group = 1U,
};
PmSlave pmSlaveTtc1_g = {
.node = {
.derived = &pmSlaveTtc1_g,
.nodeId = NODE_TTC_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ttc1"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmTtc1Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmTtc2Wake = {
.wake = {
.derived = &pmTtc2Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP1_IRQ_MASK_SRC12_MASK |
LPD_SLCR_GICP1_IRQ_MASK_SRC11_MASK |
LPD_SLCR_GICP1_IRQ_MASK_SRC10_MASK,
.group = 1U,
};
PmSlave pmSlaveTtc2_g = {
.node = {
.derived = &pmSlaveTtc2_g,
.nodeId = NODE_TTC_2,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ttc2"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmTtc2Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmTtc3Wake = {
.wake = {
.derived = &pmTtc3Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP1_IRQ_MASK_SRC15_MASK |
LPD_SLCR_GICP1_IRQ_MASK_SRC14_MASK |
LPD_SLCR_GICP1_IRQ_MASK_SRC13_MASK,
.group = 1U,
};
PmSlave pmSlaveTtc3_g = {
.node = {
.derived = &pmSlaveTtc3_g,
.nodeId = NODE_TTC_3,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ttc3"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmTtc3Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmUart0Wake = {
.wake = {
.derived = &pmUart0Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC21_MASK,
.group = 0U,
};
PmSlave pmSlaveUart0_g = {
.node = {
.derived = &pmSlaveUart0_g,
.nodeId = NODE_UART_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("uart0"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmUart0Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmUart1Wake = {
.wake = {
.derived = &pmUart1Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC22_MASK,
.group = 0U,
};
PmSlave pmSlaveUart1_g = {
.node = {
.derived = &pmSlaveUart1_g,
.nodeId = NODE_UART_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("uart1"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmUart1Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmSpi0Wake = {
.wake = {
.derived = &pmSpi0Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC19_MASK,
.group = 0U,
};
PmSlave pmSlaveSpi0_g = {
.node = {
.derived = &pmSlaveSpi0_g,
.nodeId = NODE_SPI_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("spi0"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmSpi0Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmSpi1Wake = {
.wake = {
.derived = &pmSpi1Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC20_MASK,
.group = 0U,
};
PmSlave pmSlaveSpi1_g = {
.node = {
.derived = &pmSlaveSpi1_g,
.nodeId = NODE_SPI_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("spi1"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmSpi1Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmI2C0Wake = {
.wake = {
.derived = &pmI2C0Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC17_MASK,
.group = 0U,
};
PmSlave pmSlaveI2C0_g = {
.node = {
.derived = &pmSlaveI2C0_g,
.nodeId = NODE_I2C_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("i2c0"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmI2C0Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmI2C1Wake = {
.wake = {
.derived = &pmI2C1Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC18_MASK,
.group = 0U,
};
PmSlave pmSlaveI2C1_g = {
.node = {
.derived = &pmSlaveI2C1_g,
.nodeId = NODE_I2C_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("i2c1"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmI2C1Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmSD0Wake = {
.wake = {
.derived = &pmSD0Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP1_IRQ_MASK_SRC18_MASK |
LPD_SLCR_GICP1_IRQ_MASK_SRC16_MASK,
.group = 1U,
};
PmSlave pmSlaveSD0_g = {
.node = {
.derived = &pmSlaveSD0_g,
.nodeId = NODE_SD_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("sd0"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmSD0Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmSD1Wake = {
.wake = {
.derived = &pmSD1Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP1_IRQ_MASK_SRC19_MASK |
LPD_SLCR_GICP1_IRQ_MASK_SRC17_MASK,
.group = 1U,
};
PmSlave pmSlaveSD1_g = {
.node = {
.derived = &pmSlaveSD1_g,
.nodeId = NODE_SD_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("sd1"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmSD1Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmCan0Wake = {
.wake = {
.derived = &pmCan0Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC23_MASK,
.group = 0U,
};
PmSlave pmSlaveCan0_g = {
.node = {
.derived = &pmSlaveCan0_g,
.nodeId = NODE_CAN_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("can0"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmCan0Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmCan1Wake = {
.wake = {
.derived = &pmCan1Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC24_MASK,
.group = 0U,
};
PmSlave pmSlaveCan1_g = {
.node = {
.derived = &pmSlaveCan1_g,
.nodeId = NODE_CAN_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("can1"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmCan1Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
/* Size required by Ethernet in word of OCM */
#define ETH_OCM_REQ_SIZE 6
/* OCM address used for receive queue pointer */
#define RECV_Q_OCM_ADDR 0xFFFFFF80U
#define ETH_RECV_ENABLE_MASK 0x4U
#define ETH_RECV_Q_PTR_OFFSET 0x018U
#define ETH_RECV_Q1_PTR_OFFSET 0x480U
#define ETH_RECV_HIGH_PTR_OFFSET 0x4D4U
static u32 ocmData[ETH_OCM_REQ_SIZE];
static bool ocmStored;
/**
* PmWakeEventEthConfig() - Configure propagation of ethernet wake event
* @wake Wake event
* @ipiMask IPI mask of the master which configures the wake
* @enable Flag: for enable non-zero value, for disable value zero
*/
static void PmWakeEventEthConfig(PmWakeEvent* const wake, const u32 ipiMask,
const u32 enable)
{
s32 i;
PmRequirement* req = PmRequirementGetNoMaster(&pmSlaveOcm3_g.slv);
PmWakeEventEth* ethWake = (PmWakeEventEth*)wake->derived;
/* Return if ethernet base address is not available */
if (0U == ethWake->baseAddr) {
return;
}
if (!enable && ethWake->wakeEnabled) {
/* Disable GEM Rx in network contorl register */
XPfw_RMW32(ethWake->baseAddr, ETH_RECV_ENABLE_MASK,
~ETH_RECV_ENABLE_MASK);
/* Restore receive queue pointer */
XPfw_Write32(ethWake->baseAddr + ETH_RECV_Q_PTR_OFFSET,
ethWake->receiveQptr);
XPfw_Write32(ethWake->baseAddr + ETH_RECV_Q1_PTR_OFFSET,
ethWake->receiveQ1ptr);
XPfw_Write32(ethWake->baseAddr + ETH_RECV_HIGH_PTR_OFFSET,
ethWake->receiveHighptr);
if (ocmStored) {
/*
* Restore OCM Bank3's memory which is used as receive
* queue pointer
*/
for (i = 0; i < ETH_OCM_REQ_SIZE; i++) {
XPfw_Write32(RECV_Q_OCM_ADDR + (i * 4),
ocmData[i]);
}
ocmStored = false;
}
/* Enable GEM Rx in network control register */
XPfw_RMW32(ethWake->baseAddr, ETH_RECV_ENABLE_MASK,
ETH_RECV_ENABLE_MASK);
/* Change OCM Bank3 requirement to default */
if (XST_SUCCESS != PmRequirementUpdate(req, req->defaultReq)) {
PmWarn("Error in update OCM Bank3 requirement to default\r\n");
}
ethWake->wakeEnabled = false;
}
}
/**
* PmWakeEventEthSet() - Set Ethernet wake event as the wake source
* @wake Wake event
* @ipiMask IPI mask of the master which sets the wake source
* @enable Flag: for enable non-zero value, for disable value zero
*/
static void PmWakeEventEthSet(PmWakeEvent* const wake, const u32 ipiMask,
const u32 enable)
{
s32 i;
PmRequirement* req = PmRequirementGetNoMaster(&pmSlaveOcm3_g.slv);
PmWakeEventEth* ethWake = (PmWakeEventEth*)wake->derived;
/* Return if ethernet base address is not available */
if (0U == ethWake->baseAddr) {
return;
}
if (enable != 0U) {
/* Keep OCM Bank3 ON while suspend */
if (XST_SUCCESS != PmRequirementUpdate(req, PM_CAP_ACCESS)) {
PmWarn("Error in requirement update for OCM Bank3\r\n");
}
if (0U == ocmStored) {
/*
* Store OCM Bank-3's memory which is going to be used
* as receive pointer
*/
for (i = 0; i < ETH_OCM_REQ_SIZE; i++) {
ocmData[i] = XPfw_Read32(RECV_Q_OCM_ADDR +
(i * 4));
}
ocmStored = true;
}
/* Store receive queue pointer */
ethWake->receiveQptr = XPfw_Read32(ethWake->baseAddr +
ETH_RECV_Q_PTR_OFFSET);
ethWake->receiveQ1ptr = XPfw_Read32(ethWake->baseAddr +
ETH_RECV_Q1_PTR_OFFSET);
ethWake->receiveHighptr = XPfw_Read32(ethWake->baseAddr +
ETH_RECV_HIGH_PTR_OFFSET);
/* Disable GEM Rx in network contorl register */
XPfw_RMW32(ethWake->baseAddr, ETH_RECV_ENABLE_MASK,
~ETH_RECV_ENABLE_MASK);
/* Prepare OCM memory to use as receive queue */
XPfw_Write32(RECV_Q_OCM_ADDR, 0x3U);
XPfw_Write32(RECV_Q_OCM_ADDR + 0x4U, 0x0U);
XPfw_Write32(RECV_Q_OCM_ADDR + 0x8U, 0x0U);
XPfw_Write32(RECV_Q_OCM_ADDR + 0xCU, 0x0U);
XPfw_Write32(RECV_Q_OCM_ADDR + 0x10U, 0x0U);
XPfw_Write32(RECV_Q_OCM_ADDR + 0x14U, 0x0U);
/* Change receive queue pointer to OCM address */
XPfw_Write32(ethWake->baseAddr + ETH_RECV_Q_PTR_OFFSET,
RECV_Q_OCM_ADDR);
XPfw_Write32(ethWake->baseAddr + ETH_RECV_Q1_PTR_OFFSET,
RECV_Q_OCM_ADDR);
XPfw_Write32(ethWake->baseAddr + ETH_RECV_HIGH_PTR_OFFSET, 0U);
/* Enable GEM Rx in network control register */
XPfw_RMW32(ethWake->baseAddr, ETH_RECV_ENABLE_MASK,
ETH_RECV_ENABLE_MASK);
ethWake->subClass->set(ethWake->subWake, ipiMask, enable);
ethWake->wakeEnabled = true;
}
}
PmWakeEventClass pmWakeEventClassEth_g = {
.set = PmWakeEventEthSet,
.config = PmWakeEventEthConfig,
};
static PmWakeEventGicProxy pmEth0GicWake = {
.wake = {
.derived = &pmEth0GicWake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP1_IRQ_MASK_SRC26_MASK,
.group = 1U,
};
static PmWakeEventEth pmEth0Wake = {
.wake = {
.derived = &pmEth0Wake,
.class = &pmWakeEventClassEth_g,
},
.subClass = &pmWakeEventClassGicProxy_g,
.subWake = &pmEth0GicWake.wake,
.wakeEnabled = false,
.receiveQptr = 0U,
.receiveQ1ptr = 0U,
#ifdef XPAR_PSU_ETHERNET_0_DEVICE_ID
.baseAddr = XPAR_PSU_ETHERNET_0_BASEADDR,
#else
.baseAddr = 0U,
#endif
};
PmSlave pmSlaveEth0_g = {
.node = {
.derived = &pmSlaveEth0_g,
.nodeId = NODE_ETH_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("eth0"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmEth0Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmEth1GicWake = {
.wake = {
.derived = &pmEth1GicWake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP1_IRQ_MASK_SRC28_MASK,
.group = 1U,
};
static PmWakeEventEth pmEth1Wake = {
.wake = {
.derived = &pmEth1Wake,
.class = &pmWakeEventClassEth_g,
},
.subClass = &pmWakeEventClassGicProxy_g,
.subWake = &pmEth1GicWake.wake,
.wakeEnabled = false,
.receiveQptr = 0U,
.receiveQ1ptr = 0U,
#ifdef XPAR_PSU_ETHERNET_1_DEVICE_ID
.baseAddr = XPAR_PSU_ETHERNET_1_BASEADDR,
#else
.baseAddr = 0U,
#endif
};
PmSlave pmSlaveEth1_g = {
.node = {
.derived = &pmSlaveEth1_g,
.nodeId = NODE_ETH_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("eth1"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmEth1Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmEth2GicWake = {
.wake = {
.derived = &pmEth2GicWake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP1_IRQ_MASK_SRC30_MASK,
.group = 1U,
};
static PmWakeEventEth pmEth2Wake = {
.wake = {
.derived = &pmEth2Wake,
.class = &pmWakeEventClassEth_g,
},
.subClass = &pmWakeEventClassGicProxy_g,
.subWake = &pmEth2GicWake.wake,
.wakeEnabled = false,
.receiveQptr = 0U,
.receiveQ1ptr = 0U,
#ifdef XPAR_PSU_ETHERNET_2_DEVICE_ID
.baseAddr = XPAR_PSU_ETHERNET_2_BASEADDR,
#else
.baseAddr = 0U,
#endif
};
PmSlave pmSlaveEth2_g = {
.node = {
.derived = &pmSlaveEth2_g,
.nodeId = NODE_ETH_2,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("eth2"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmEth2Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmEth3GicWake = {
.wake = {
.derived = &pmEth3GicWake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP2_IRQ_MASK_SRC0_MASK,
.group = 2U,
};
static PmWakeEventEth pmEth3Wake = {
.wake = {
.derived = &pmEth3Wake,
.class = &pmWakeEventClassEth_g,
},
.subClass = &pmWakeEventClassGicProxy_g,
.subWake = &pmEth3GicWake.wake,
.wakeEnabled = false,
.receiveQptr = 0U,
.receiveQ1ptr = 0U,
#ifdef XPAR_PSU_ETHERNET_3_DEVICE_ID
.baseAddr = XPAR_PSU_ETHERNET_3_BASEADDR,
#else
.baseAddr = 0U,
#endif
};
PmSlave pmSlaveEth3_g = {
.node = {
.derived = &pmSlaveEth3_g,
.nodeId = NODE_ETH_3,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("eth3"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmEth3Wake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmAdmaWake = {
.wake = {
.derived = &pmAdmaWake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP2_IRQ_MASK_SRC19_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC18_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC17_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC16_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC15_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC14_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC13_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC12_MASK,
.group = 2U,
};
PmSlave pmSlaveAdma_g = {
.node = {
.derived = &pmSlaveAdma_g,
.nodeId = NODE_ADMA,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("adma"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmAdmaWake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmNandWake = {
.wake = {
.derived = &pmNandWake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC14_MASK,
.group = 0U,
};
PmSlave pmSlaveNand_g = {
.node = {
.derived = &pmSlaveNand_g,
.nodeId = NODE_NAND,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("nand"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmNandWake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmQSpiWake = {
.wake = {
.derived = &pmQSpiWake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC15_MASK,
.group = 0U,
};
PmSlave pmSlaveQSpi_g = {
.node = {
.derived = &pmSlaveQSpi_g,
.nodeId = NODE_QSPI,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("qspi"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmQSpiWake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmGpioWake = {
.wake = {
.derived = &pmGpioWake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP0_IRQ_MASK_SRC16_MASK,
.group = 0U,
};
PmSlave pmSlaveGpio_g = {
.node = {
.derived = &pmSlaveGpio_g,
.nodeId = NODE_GPIO,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("gpio"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmGpioWake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlaveSata_g = {
.node = {
.derived = &pmSlaveSata_g,
.nodeId = NODE_SATA,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("sata"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlavePcie_g = {
.node = {
.derived = &pmSlavePcie_g,
.nodeId = NODE_PCIE,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("pcie"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlavePcap_g = {
.node = {
.derived = &pmSlavePcap_g,
.nodeId = NODE_PCAP,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("pcap"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlaveGdma_g = {
.node = {
.derived = &pmSlaveGdma_g,
.nodeId = NODE_GDMA,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("gdma"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlaveDP_g = {
.node = {
.derived = &pmSlaveDP_g,
.nodeId = NODE_DP,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("dp"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
static PmWakeEventGicProxy pmIpiApuWake = {
.wake = {
.derived = &pmIpiApuWake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP1_IRQ_MASK_SRC3_MASK,
.group = 1U,
};
PmSlave pmSlaveIpiApu_g = {
.node = {
.derived = &pmSlaveIpiApu_g,
.nodeId = NODE_IPI_APU,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ipi_apu"),
},
.class = NULL,
.reqs = NULL,
.wake = &pmIpiApuWake.wake,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlaveIpiRpu0_g = {
.node = {
.derived = &pmSlaveIpiRpu0_g,
.nodeId = NODE_IPI_RPU_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ipi_rpu0"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlaveIpiRpu1_g = {
.node = {
.derived = &pmSlaveIpiRpu1_g,
.nodeId = NODE_IPI_RPU_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ipi_rpu1"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlaveIpiPl0_g = {
.node = {
.derived = &pmSlaveIpiPl0_g,
.nodeId = NODE_IPI_PL_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ipi_pl0"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlaveIpiPl1_g = {
.node = {
.derived = &pmSlaveIpiPl1_g,
.nodeId = NODE_IPI_PL_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ipi_pl1"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlaveIpiPl2_g = {
.node = {
.derived = &pmSlaveIpiPl2_g,
.nodeId = NODE_IPI_PL_2,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ipi_pl2"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlaveIpiPl3_g = {
.node = {
.derived = &pmSlaveIpiPl3_g,
.nodeId = NODE_IPI_PL_3,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("ipi_pl3"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlavePl_g = {
.node = {
.derived = &pmSlavePl_g,
.nodeId = NODE_PL,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainPld_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
DEFINE_NODE_NAME("pl"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
PmSlave pmSlaveFpdWdt_g = {
.node = {
.derived = &pmSlaveFpdWdt_g,
.nodeId = NODE_SWDT_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_GENERIC_SLAVE_STATE_RUNNING,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGenericSlavePowers),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmGenericSlaveFsm,
.flags = 0U,
};
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_gic_proxy.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_GIC_H_
#define XPM_GIC_H_
#include "xpm_periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* GicProxyGroup - Properties of a GIC Proxy group
* @SetMask When GIC Proxy is Enabled, Enable the interrupts whose masks
* are set in this variable
*/
typedef struct {
u32 SetMask;
} XPm_GicProxyGroup;
/**
* XPm_GicProxy - Structure containing GIC Proxy properties
* @Groups Pointer to the array of GIC Proxy Groups
* @GroupsCnt Number of elements in the array of GIC Proxy Groups
* @Clear Clear all set wake-up sources (Flags for all Groups)
* @Enable Function that Enables GIC Proxy and all interrupts that are set
* as wake sources
* @Flags GIC Proxy Flags (is Enabled or not)
*/
typedef struct {
XPm_GicProxyGroup* const Groups;
void (*const Clear)(void);
void (*const Enable)(void);
const u8 GroupsCnt;
u8 Flags;
} XPm_GicProxy_t;
/*********************************************************************
* Global data declarations
********************************************************************/
extern XPm_GicProxy_t XPm_GicProxy;
void XPmGicProxy_WakeEventSet(XPm_Periph *Periph, u8 Enable);
#ifdef __cplusplus
}
#endif
#endif /*XPM_GIC_H_*/
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/common/Makefile
###############################################################################
# Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
###############################################################################
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
CUSTOM_COMPILER_FLAGS=-Werror
LIB= libxilpm.a
EXTRA_ARCHIVE_FLAGS=rc
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
LIBPM_DIR = .
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
LIBPM_SRCS := $(wildcard *.c)
LIBPM_OBJS = $(addprefix $(LIBPM_DIR)/, $(LIBPM_SRCS:%.c=%.o))
libs: libxilpm.a
libxilpm.a: print_msg_xilpm $(LIBPM_OBJS)
$(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} ${LIBPM_OBJS}
print_msg_xilpm:
@echo "Compiling XilPM Library"
.PHONY: include
include:
echo "Include files for this library have already been copied."
clean:
rm -rf $(LIBPM_DIR)/${OBJECTS}
rm -rf ${RELEASEDIR}/${LIB}
$(LIBPM_DIR)/%.o: $(LIBPM_DIR)/%.c $(INCLUDEFILES)
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(CUSTOM_COMPILER_FLAGS) $(INCLUDES) -c $< -o $@
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_11/src/xqspipsu_control.h
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu_control.h
* @addtogroup qspipsu_v1_11
* @{
* @details
*
* This is the header file for the implementation of QSPIPSU driver.
* Generic QSPI interface allows for communication to any QSPI slave device.
* GQSPI contains a GENFIFO into which the bus transfers required are to be
* pushed with appropriate configuration. The controller provides TX and RX
* FIFO's and a DMA to be used for RX transfers. The controller executes each
* GENFIFO entry noting the configuration and places data on the bus as required
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------.
* 1.11 akm 03/09/20 First release
*
* </pre>
*
******************************************************************************/
#ifndef XQSPIPSU_CONTROL_H_ /* prevent circular inclusions */
#define XQSPIPSU_CONTROL_H_ /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xqspipsu.h"
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#if defined (ARMR5) || (__aarch64__)
#define TAPDLY_BYPASS_VALVE_40MHZ 0x01U
#define TAPDLY_BYPASS_VALVE_100MHZ 0x01U
#define USE_DLY_LPBK 0x01U
#define USE_DATA_DLY_ADJ 0x01U
#define DATA_DLY_ADJ_DLY 0X02U
#define LPBK_DLY_ADJ_DLY0 0X02U
#define LPBK_DLY_ADJ_DLY1 0X02U
#endif
/************************** Function Prototypes ******************************/
void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
u32 XQspiPsu_SetIOMode(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
void XQspiPsu_IORead(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 StatusReg);
void XQspiPsu_PollDataConfig(XQspiPsu *InstancePtr, XQspiPsu_Msg *FlashMsg);
void XQspiPsu_TXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
void XQspiPsu_SetupRxDma(const XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg);
void XQspiPsu_Setup64BRxDma(const XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg);
void XQspiPsu_RXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 *GenFifoEntry);
void XQspiPsu_GenFifoEntryDataLen(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 *GenFifoEntry);
u32 XQspiPsu_CreatePollDataConfig(const XQspiPsu *InstancePtr,
const XQspiPsu_Msg *FlashMsg);
u32 XQspiPsu_SelectSpiMode(u8 SpiMode);
void XQspiPsu_SetDefaultConfig(XQspiPsu *InstancePtr);
void StubStatusHandler(const void *CallBackRef, u32 StatusEvent,
u32 ByteCount);
void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 Size);
void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, s32 Size);
#if defined (ARMR5) || (__aarch64__)
s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr, u32 TapdelayBypass,
u32 LPBKDelay, u32 Datadelay);
s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler);
#endif
#ifdef __cplusplus
}
#endif
#endif /* XQSPIPSU_CONTROL_H_ */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_7/src/xusbpsu.c
/******************************************************************************
* Copyright (C) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu.c
* @addtogroup usbpsu_v1_7
* @{
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.0 sg 06/16/16 First release
* 1.1 sg 10/24/16 Added new function XUsbPsu_IsSuperSpeed
* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code
* for all USB IPs.
* myk 12/01/18 Added hibernation support for device mode
* 1.4 vak 30/05/18 Removed xusb_wrapper files
* vak 24/09/18 Add support for connecting to host in high-speed
* 1.5 vak 02/06/19 Add API for idling usb controller
* 1.6 pm 22/07/19 Removed coverity warnings
* pm 08/08/19 Added support to set AXI-Cache bits when CCI is enable
* pm 28/08/19 Removed 80-character warnings
* 1.7 pm 02/20/20 Add support to set CCI bit in Coherency Mode Register
* when CCI is eanble
* pm 03/23/20 Restructured the code for more readability and modularity
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xusbpsu_local.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
static INLINE void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode);
static void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr);
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* Sets mode of Core to USB Device/Host/OTG.
*
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
* @param Mode is mode to set
* - XUSBPSU_GCTL_PRTCAP_OTG
* - XUSBPSU_GCTL_PRTCAP_HOST
* - XUSBPSU_GCTL_PRTCAP_DEVICE
*
* @return None
*
* @note None.
*
******************************************************************************/
static INLINE void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode)
{
u32 RegVal;
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
RegVal &= ~(XUSBPSU_GCTL_PRTCAPDIR(XUSBPSU_GCTL_PRTCAP_OTG));
RegVal |= XUSBPSU_GCTL_PRTCAPDIR(Mode);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
}
/****************************************************************************/
/**
* Initializes Endpoints. All OUT endpoints are even numbered and all IN
* endpoints are odd numbered. EP0 is for Control OUT and EP1 is for
* Control IN.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return None.
*
* @note None.
*
****************************************************************************/
static void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr)
{
u8 i;
u8 Epnum;
for (i = 0U; i < InstancePtr->NumOutEps; i++) {
Epnum = (i << 1U) | XUSBPSU_EP_DIR_OUT;
InstancePtr->eps[Epnum].PhyEpNum = Epnum;
InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_OUT;
InstancePtr->eps[Epnum].ResourceIndex = 0U;
}
for (i = 0U; i < InstancePtr->NumInEps; i++) {
Epnum = (i << 1U) | XUSBPSU_EP_DIR_IN;
InstancePtr->eps[Epnum].PhyEpNum = Epnum;
InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_IN;
InstancePtr->eps[Epnum].ResourceIndex = 0U;
}
}
/****************************************************************************/
/**
* @brief
* This function does the following:
* - initializes a specific XUsbPsu instance.
* - sets up Event Buffer for Core to write events.
* - Core Reset and PHY Reset.
* - Sets core in Device Mode.
* - Sets default speed as HIGH_SPEED.
* - Sets Device Address to 0.
* - Enables interrupts.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param ConfigPtr points to the XUsbPsu device configuration structure.
* @param BaseAddress is the device base address in the virtual memory
* address space. If the address translation is not used then the
* physical address is passed.
* Unexpected errors may occur if the address mapping is changed
* after this function is invoked.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
XUsbPsu_Config *ConfigPtr, u32 BaseAddress)
{
s32 Status;
u32 RegVal;
u32 Speed;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
Xil_AssertNonvoid(BaseAddress != 0U)
InstancePtr->ConfigPtr = ConfigPtr;
Status = XUsbPsu_CoreInit(InstancePtr);
if (Status != XST_SUCCESS) {
#ifdef XUSBPSU_DEBUG
xil_printf("Core initialization failed\r\n");
#endif
return (s32)XST_FAILURE;
}
RegVal = XUsbPsu_ReadHwParams(InstancePtr, 3U);
InstancePtr->NumInEps = (u8)XUSBPSU_NUM_IN_EPS(RegVal);
InstancePtr->NumOutEps = (u8)(XUSBPSU_NUM_EPS(RegVal) -
InstancePtr->NumInEps);
/* Map USB and Physical Endpoints */
XUsbPsu_InitializeEps(InstancePtr);
XUsbPsu_EventBuffersSetup(InstancePtr);
XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE);
/*
* Set connection speed based on EnableSuperSpeed parameter
*/
Speed = (ConfigPtr->EnableSuperSpeed == TRUE) ?
XUSBPSU_DCFG_SUPERSPEED : XUSBPSU_DCFG_HIGHSPEED;
/*
* Setting to max speed to support SS and HS
*/
XUsbPsu_SetSpeed(InstancePtr, Speed);
(void)XUsbPsu_SetDeviceAddress(InstancePtr, 0U);
return XST_SUCCESS;
}
/****************************************************************************/
/**
*
* @brief
* Starts the controller so that Host can detect this device.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal |= XUSBPSU_DCTL_RUN_STOP;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
if (XUsbPsu_WaitClearTimeout(InstancePtr, XUSBPSU_DSTS,
XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
return (s32)XST_FAILURE;
}
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
*
* @brief
* Stops the controller so that Device disconnects from Host.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal &= ~XUSBPSU_DCTL_RUN_STOP;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
if (XUsbPsu_WaitSetTimeout(InstancePtr, XUSBPSU_DSTS,
XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
return (s32)XST_FAILURE;
}
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* Gets current State of USB Link
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return Link State
*
* @note None.
*
****************************************************************************/
u8 XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
return XUSBPSU_DSTS_USBLNKST(RegVal);
}
/****************************************************************************/
/**
* Sets USB Link to a particular State
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param State is State of Link to set.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
****************************************************************************/
s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
XusbPsuLinkStateChange State)
{
u32 RegVal;
/* Wait until device controller is ready. */
if (XUsbPsu_WaitClearTimeout(InstancePtr, XUSBPSU_DSTS,
XUSBPSU_DSTS_DCNRD, 500U) == XST_FAILURE) {
return (s32)XST_FAILURE;
}
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal &= ~XUSBPSU_DCTL_ULSTCHNGREQ_MASK;
RegVal |= XUSBPSU_DCTL_ULSTCHNGREQ(State);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Set U1 sleep timeout
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Sleep is time in microseconds
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
RegVal &= ~XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK;
RegVal |= (u32)(Sleep << XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Set U2 sleep timeout
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Sleep is time in microseconds
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
RegVal &= ~XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK;
RegVal |= (u32)(Sleep << XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Enable Accept U1 and U2 sleep enable
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal |= XUSBPSU_DCTL_ACCEPTU2ENA | XUSBPSU_DCTL_ACCEPTU1ENA;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Enable U1 enable sleep
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal |= XUSBPSU_DCTL_INITU1ENA;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Enable U2 enable sleep
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal |= XUSBPSU_DCTL_INITU2ENA;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Enable U1 disable sleep
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Enable U2 disable sleep
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Checks if the current speed is Super Speed or not
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
if (InstancePtr->AppData->Speed != XUSBPSU_SPEED_SUPER) {
return (s32)XST_FAILURE;
}
return (s32)XST_SUCCESS;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_requirement.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* PM requirements are data structures allocated for each valid
* master/slave pair, used for tracking master's requests for slave's
* capabilities/states.
*********************************************************************/
#ifndef PM_REQUIREMENT_H_
#define PM_REQUIREMENT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_common.h"
#include "xil_types.h"
#include "pm_node.h"
/* Forward declarations */
typedef struct PmMaster PmMaster;
typedef struct PmSlave PmSlave;
typedef struct PmRequirement PmRequirement;
typedef enum {
RELEASE_ONE,
RELEASE_ALL,
RELEASE_UNREQUESTED,
} PmReleaseScope;
/*********************************************************************
* Macros
********************************************************************/
/*
* Max number of master/slave pairs (max number of combinations that can
* exist at the runtime). The value is used to statically initialize
* size of the pmReqData array, which is used as the heap.
*/
#define PM_REQUIREMENT_MAX 200U
/* Requirement flags */
#define PM_MASTER_WAKEUP_REQ_MASK 0x1U
#define PM_MASTER_REQUESTED_SLAVE_MASK 0x2U
#define PM_MASTER_SET_LATENCY_REQ 0x4U
#define PM_SYSTEM_USING_SLAVE_MASK 0x8U
#define MASTER_REQUESTED_SLAVE(reqPtr) \
(0U != (PM_MASTER_REQUESTED_SLAVE_MASK & (reqPtr)->info))
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmRequirement - structure for tracking requirements of a master for the slave
* setting. One structure should be statically assigned for each
* possible combination of master/slave, because dynamic memory
* allocation cannot be used.
* @slave Pointer to the slave structure
* @master Pointer to the master structure
* @nextSlave Pointer to the master's requirement for a next slave in the list
* @nextMaster Pointer to the requirement of a next master that uses the slave
* @preReq Requirements of a master that it cannot request for itself (when
* a master starts the cold boot there are some resources it will
* use before it is capable of requesting them, like memories)
* @defaultReq Default requirements of a master - requirements for slave
* capabilities without which the master cannot run
* @currReq Currently holding requirements of a master for this slave
* @nextReq Requirements of a master to be configured when it changes the
* state (after it goes to sleep or before it gets awake)
* @latencyReq Latency requirements of master for the slave's transition time
* from any to its maximum (highest id) state
* @info Contains information about master's request - a bit for
* encoding has master requested or released node, and a bit to
* encode has master requested a wake-up of this slave.
*/
typedef struct PmRequirement {
PmSlave* slave;
PmMaster* master;
PmRequirement* nextSlave;
PmRequirement* nextMaster;
u8 preReq;
u8 defaultReq;
u8 currReq;
u8 nextReq;
u32 latencyReq;
u8 info;
} PmRequirement;
/*********************************************************************
* Function declarations
********************************************************************/
void PmRequirementCancelScheduled(const PmMaster* const master);
void PmRequirementPreRequest(const PmMaster* const master);
void PmRequirementClockRestore(const PmMaster* const master);
void PmRequirementFreeAll(void);
void PmRequirementClear(PmRequirement* const req);
s32 PmRequirementSchedule(PmRequirement* const masterReq, const u32 caps);
s32 PmRequirementUpdate(PmRequirement* const masterReq, const u32 caps);
s32 PmRequirementUpdateScheduled(const PmMaster* const master, const bool swap);
s32 PmRequirementRequest(PmRequirement* const req, const u32 caps);
s32 PmRequirementRelease(PmRequirement* const first, const PmReleaseScope scope);
PmRequirement* PmRequirementAdd(PmMaster* const master, PmSlave* const slave);
PmRequirement* PmRequirementGet(const PmMaster* const master,
const PmSlave* const slave);
PmRequirement* PmRequirementGetNoMaster(const PmSlave* const slave);
s32 PmRequirementSetConfig(PmRequirement* const req, const u32 flags,
const u32 currReq, const u32 defaultReq);
#ifdef __cplusplus
}
#endif
#endif /* PM_REQUIREMENT_H_ */
<file_sep>/python_drivers/qutag_examples/qutag-GetCoincCounter-starter_example.py
# Example for using the Coincidence Counters with python + quTAG
#
# Author: qutools GmbH
# Last edited: Sep 2019
#
# Tested with python 3.7.3 (32bit), numpy-1.13.3 and Windows 7 (64bit)
#
# This is demo code. Use at your own risk. No warranties.
#
# It may be used and modified with no restriction; raw copies as well as
# modified versions may be distributed without limitation.
# for sleep
import time
# This code shows how to get event rates and coincidences from a quTAG connected via USB.
# Import the python wrapper which wraps the DLL functions.
# The wrapper should be in the same directory like this code in the folder '..\QUTAG-V1.5.0\userlib\src'.
try:
import QuTAG
except:
print("Time Tagger wrapper QuTAG.py is not in the search path.")
# Initialize the quTAG device
qutag = QuTAG.QuTAG()
# Set the exposure time (or integration time) of the internal coincidence counters in milliseconds, range = 0...65535
qutag.setExposureTime(100) # 100 ms exposure time
# Give some time to accumulate data
time.sleep(1) # 1 second sleep time with 100ms exposure time would give ~10 times data we don't get
# Now let's retrieve the most recent values of the built-in coincidence counters from quTAG.
# The array contains count rates for all 5 channels and rates for coincidences of events detected on different channels. Events are coincident if they happen within the coincidence window (qutag.setCoincidenceWindow).
# The coincidence counters are not accumulated, i.e. the counter values for the last exposure (see setExposureTime ) are returned.
data,updates = qutag.getCoincCounters()
print("Updates since last call: ", updates, "| Data: ", data)
# updates Output: Number of data updates by the device since the last call. Pointer may be NULL.
# data Output: Counter Values. The array must have at least 31 elements.
# The Counters come in the following channel order with single counts and coincidences:
# 0(5), 1, 2, 3, 4, 1/2, 1/3, 2/3, 1/4, 2/4, 3/4, 1/5, 2/5, 3/5, 4/5, 1/2/3, 1/2/4, 1/3/4, 2/3/4, 1/2/5, 1/3/5, 2/3/5, 1/4/5, 2/4/5, 3/4/5, 1/2/3/4, 1/2/3/5, 1/2/4/5, 1/3/4/5, 2/3/4/5, 1/2/3/4/5
### see 'tdcbase.h' file reference for more info: function TDC_getCoincCounters(Int32 *data, Int32 *updates)
# Disconnects a connected device and stops the internal event loop.
qutag.deInitialize()
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_gic_proxy.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_gic_proxy.h"
#include "xpm_pmc.h"
#include "xpm_device.h"
#include "xpm_common.h"
#include "xpm_regs.h"
#define XPM_GIC_PROXY_IS_ENABLED 0x1U
void XPmGicProxy_WakeEventSet(XPm_Periph *Periph, u8 Enable)
{
u32 GicProxyMask = Periph->GicProxyMask;
u32 GicProxyGroup = Periph->GicProxyGroup;
XPm_Pmc *Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
if (0U == Enable) {
XPm_GicProxy.Groups[GicProxyGroup].SetMask &= ~GicProxyMask;
} else {
/* PMC Global base address */
u32 BaseAddress = Pmc->PmcGlobalBaseAddr;
u32 RegAddress = BaseAddress +
PMC_GLOBAL_GIC_PROXY_BASE_OFFSET +
GIC_PROXY_GROUP_OFFSET(GicProxyGroup) +
GIC_PROXY_IRQ_STATUS_OFFSET;
/* Write 1 into status register to Clear interrupt */
XPm_Out32(RegAddress, GicProxyMask);
/* Remember which interrupt in the group needs to be Enabled */
XPm_GicProxy.Groups[GicProxyGroup].SetMask |= GicProxyMask;
}
}
/**
* XPmGicProxy_Enable() - Enable all interrupts that are requested
*/
static void XPmGicProxy_Enable(void)
{
u32 g;
XPm_Pmc *Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
for (g = 0U; g < XPm_GicProxy.GroupsCnt; g++) {
/* PMC Global base address */
u32 BaseAddress = Pmc->PmcGlobalBaseAddr;
u32 RegAddress = BaseAddress +
PMC_GLOBAL_GIC_PROXY_BASE_OFFSET +
GIC_PROXY_GROUP_OFFSET(g) +
GIC_PROXY_IRQ_ENABLE_OFFSET;
/* Enable interrupts in the group that are set as wake */
XPm_Out32(RegAddress, XPm_GicProxy.Groups[g].SetMask);
if (0U != XPm_GicProxy.Groups[g].SetMask) {
XPm_Out32(BaseAddress +
PMC_GLOBAL_GICP_IRQ_ENABLE_OFFSET, BIT32(g));
}
}
XPm_GicProxy.Flags |= XPM_GIC_PROXY_IS_ENABLED;
}
/**
* XPm_GicProxyDisable() - Disable all interrupts in the GIC Proxy
*/
static void XPm_GicProxyDisable(void)
{
u32 g;
XPm_Pmc *Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
for (g = 0U; g < XPm_GicProxy.GroupsCnt; g++) {
/* PMC Global base address */
u32 BaseAddress = Pmc->PmcGlobalBaseAddr;
u32 DisableAddr = BaseAddress +
PMC_GLOBAL_GIC_PROXY_BASE_OFFSET +
GIC_PROXY_GROUP_OFFSET(g) +
GIC_PROXY_IRQ_DISABLE_OFFSET;
u32 StatusAddr = BaseAddress +
PMC_GLOBAL_GIC_PROXY_BASE_OFFSET +
GIC_PROXY_GROUP_OFFSET(g) +
GIC_PROXY_IRQ_STATUS_OFFSET;
u32 MaskAddr = BaseAddress +
PMC_GLOBAL_GIC_PROXY_BASE_OFFSET +
GIC_PROXY_GROUP_OFFSET(g) +
GIC_PROXY_IRQ_MASK_OFFSET;
/* Clear interrupts in the GIC Proxy group that are set as wake */
XPm_Out32(StatusAddr, XPm_GicProxy.Groups[g].SetMask);
/* Disable interrupts in the GIC Proxy group that are set as wake */
XPm_Out32(DisableAddr, XPm_GicProxy.Groups[g].SetMask);
if (GIC_PROXY_ALL_MASK == XPm_In32(MaskAddr)) {
XPm_Out32(BaseAddress +
PMC_GLOBAL_GICP_IRQ_DISABLE_OFFSET, BIT32(g));
}
}
XPm_GicProxy.Flags &= (u8)(~XPM_GIC_PROXY_IS_ENABLED);
}
/**
* XPmGicProxy_Clear() - Clear wake-up sources
*/
static void XPmGicProxy_Clear(void)
{
u32 g;
if (0U != (XPm_GicProxy.Flags & XPM_GIC_PROXY_IS_ENABLED)) {
XPm_GicProxyDisable();
}
for (g = 0U; g < XPm_GicProxy.GroupsCnt; g++) {
XPm_GicProxy.Groups[g].SetMask = 0U;
}
}
/* FPD GIC Proxy has interrupts organized in 5 Groups */
static XPm_GicProxyGroup XPm_GicProxyGroups[5];
XPm_GicProxy_t XPm_GicProxy = {
.Groups = XPm_GicProxyGroups,
.GroupsCnt = ARRAY_SIZE(XPm_GicProxyGroups),
.Clear = XPmGicProxy_Clear,
.Enable = XPmGicProxy_Enable,
.Flags = 0U,
};
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_notifier.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* Implementation of notifications and event handling within
* power management.
*********************************************************************/
#include "pm_notifier.h"
#include <string.h>
#include "pm_callbacks.h"
/*
* Maximum number of notifier master/node pairs supported by PM -
* determines size of PmNotifiers array.
*/
#define PM_NOTIFIERS_COUNT 10U
/**
* PmNotifier - Encapsulates all info related to master/node notification
* @master Master to be notified about the event
* @node Pointer to the node which is subject of notification
* @eventMask Event mask of the event that triggers notification to be sent
* @wakeMask Mask specifyng whether the master should be woken up if it is
* sleeping at the moment when event happens. Bitfield matches
* eventMask (if a bitfield for event is 0 - no wake; otherwise,
* if event's bitfield in wakeMask is set the master is woken-up
* when the event occurs)
*/
typedef struct {
const PmMaster* master;
const PmNode* node;
u32 eventMask;
u32 wakeMask;
} PmNotifier;
static PmNotifier pmNotifiers[PM_NOTIFIERS_COUNT];
/**
* PmRegisterEvent() - Register one event in pmNotifiers array's entry
* @entry Valid index in pmNotifiers array
* @event Event to be registered for
* @wake Flag specifying whether the master should be woken up to
* handle event
*
* @note Master and node pointers for the entry are set by the function
* calling this.
*/
static void PmRegisterEvent(const u32 entry, const u32 event, const u32 wake)
{
pmNotifiers[entry].eventMask |= event;
if (0U != wake) {
/* Wake master for this event (event mask matches wake mask) */
pmNotifiers[entry].wakeMask |= event;
}
}
/**
* PmNotifierRegister() - Register notifier for given master, node and event
* @mst Master to be notified
* @nd Node related to event
* @event Event to be notified about
* @wake Flag specifying whether the master should be woken upin order
* to be notified (if it is sleeping when the event happens)
*
* @return Status of registration
* - XST_FAILURE - notifier is not registered as all entries in
* pmNotifiers array are occupied
* - XST_SUCCESS - notifier is successfully registered
*/
s32 PmNotifierRegister(const PmMaster* const mst, const PmNode* const nd,
const u32 event, const u32 wake)
{
s32 status = XST_FAILURE;
u32 i, empty = ARRAY_SIZE(pmNotifiers); /* init just to exceed max */
for (i = 0U; i < ARRAY_SIZE(pmNotifiers); i++) {
if (NULL == pmNotifiers[i].master) {
/* Empty entry found in pmNotifiers array */
if (ARRAY_SIZE(pmNotifiers) == empty) {
/* Remember only first found empty entry */
empty = i;
status = XST_SUCCESS;
}
continue;
}
if ((mst == pmNotifiers[i].master) &&
(nd == pmNotifiers[i].node)) {
/* Reuse existing entry for master/node pair */
PmRegisterEvent(i, event, wake);
/* Drop empty value - done with registration */
empty = ARRAY_SIZE(pmNotifiers);
status = XST_SUCCESS;
break;
}
}
if (XST_SUCCESS != status) {
/* There is no free entry in pmNotifiers array, report error */
goto done;
}
if (ARRAY_SIZE(pmNotifiers) != empty) {
/* Empty entry should be filled with registration info */
pmNotifiers[empty].master = mst;
pmNotifiers[empty].node = nd;
PmRegisterEvent(empty, event, wake);
}
done:
return status;
}
/**
* PmUnregisterEvent() - Unregister event in pmNotifiers' array entry
* @entry Valid index in pmNotifiers array
* @event Event to be unregistered
*
* @note This function also clears master/node pointer values if no other
* event is left registered for the entry, so the entry can be used
* for other pairs.
*/
static void PmUnregisterEvent(const u32 entry, const u32 event)
{
pmNotifiers[entry].eventMask &= ~event;
pmNotifiers[entry].wakeMask &= ~event;
if (0U == pmNotifiers[entry].eventMask) {
(void)memset(&pmNotifiers[entry], 0U, sizeof(PmNotifier));
}
}
/**
* PmNotifierUnregister() - Unregister notifier for given master, node and event
* @mst Master which was registered for notification
* @nd Node related to event
* @event Notification event
*/
void PmNotifierUnregister(const PmMaster* const mst, const PmNode* const nd,
const u32 event)
{
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmNotifiers); i++) {
if ((mst == pmNotifiers[i].master) &&
(nd == pmNotifiers[i].node)) {
/* Entry for master/node pair found */
PmUnregisterEvent(i, event);
break;
}
}
}
/**
* PmNotifierUnregisterAll() - Unregister all notifiers of the given master
* @mst Master whose notifiers should be unregistered
*/
void PmNotifierUnregisterAll(const PmMaster* const mst)
{
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmNotifiers); i++) {
if (mst == pmNotifiers[i].master) {
(void)memset(&pmNotifiers[i], 0U, sizeof(PmNotifier));
}
}
}
/**
* PmNotifierProcessEvent() - Process event for the registration
* @nt Pointer to registered notifier
* @event Event that occurred in the system
*/
static void PmNotifierProcessEvent(const PmNotifier* const nt,
const u32 event)
{
if ((false == PmMasterIsActive(nt->master)) &&
(0U == (event & nt->wakeMask))) {
/*
* If master has no active processor it should be notified about
* the event only if it requested to be woken up.
*/
goto done;
}
PmNotifyCb(nt->master, nt->node->nodeId, event, nt->node->currState);
done:
return;
}
/**
* PmNotifierEvent() - Called to trigger the notification framework to check
* whether the notification callback should be sent for given
* arguments
* @nd Node regarding which the event is generated
* @event Event that occurred in the system (check for its PU recipients)
*/
void PmNotifierEvent(const PmNode* const nd, const u32 event)
{
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmNotifiers); i++) {
/* Search for the given node */
if (nd != pmNotifiers[i].node) {
continue;
}
/* Node is matching, check for event */
if (0U == (event & pmNotifiers[i].eventMask)) {
continue;
}
PmNotifierProcessEvent(&pmNotifiers[i], event);
}
}
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/efuse.h
/*
* Copyright (c) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#ifndef _EFUSE_H_
#define _EFUSE_H_
#ifdef __cplusplus
extern "C" {
#endif
/* EFUSE Base Address */
#define EFUSE_BASEADDR 0XFFCC0000U
/* Register: EFUSE_IPDISABLE */
#define EFUSE_IPDISABLE ( ( EFUSE_BASEADDR ) + 0X00001018U )
#define EFUSE_IPDISABLE_GPU_DIS_SHIFT 5U
#define EFUSE_IPDISABLE_GPU_DIS_WIDTH 1U
#define EFUSE_IPDISABLE_GPU_DIS_MASK 0X00000020U
#define EFUSE_IPDISABLE_APU3_DIS_SHIFT 3U
#define EFUSE_IPDISABLE_APU3_DIS_WIDTH 1U
#define EFUSE_IPDISABLE_APU3_DIS_MASK 0X00000008U
#define EFUSE_IPDISABLE_APU2_DIS_SHIFT 2U
#define EFUSE_IPDISABLE_APU2_DIS_WIDTH 1U
#define EFUSE_IPDISABLE_APU2_DIS_MASK 0X00000004U
#define EFUSE_IPDISABLE_APU1_DIS_SHIFT 1U
#define EFUSE_IPDISABLE_APU1_DIS_WIDTH 1U
#define EFUSE_IPDISABLE_APU1_DIS_MASK 0X00000002U
#define EFUSE_IPDISABLE_APU0_DIS_SHIFT 0U
#define EFUSE_IPDISABLE_APU0_DIS_WIDTH 1U
#define EFUSE_IPDISABLE_APU0_DIS_MASK 0X00000001U
#define EFUSE_IPDISABLE_VERSION 0x1FFU
#ifdef __cplusplus
}
#endif
#endif /* _EFUSE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_common.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xil_io.h"
#include "xpm_common.h"
#include "xpm_regs.h"
#include "xpm_pmc.h"
#include "xpm_psfpdomain.h"
#include "xpm_pslpdomain.h"
#define MAX_BYTEBUFFER_SIZE (32U * 1024U)
static u8 ByteBuffer[MAX_BYTEBUFFER_SIZE];
static u8 *FreeBytes = ByteBuffer;
u32 Platform;
u32 PlatformVersion;
u32 SlrType;
void *XPm_AllocBytes(u32 Size)
{
void *Bytes = NULL;
u32 BytesLeft = (u32)ByteBuffer + MAX_BYTEBUFFER_SIZE - (u32)FreeBytes;
u32 i;
u32 NumWords;
u32 *Words;
/* Round size to the next multiple of 4 */
Size += 3U;
Size &= ~0x3U;
if (Size > BytesLeft) {
goto done;
}
Bytes = FreeBytes;
FreeBytes += Size;
/* Zero the bytes */
NumWords = Size / 4U;
Words = (u32 *)Bytes;
for (i = 0; i < NumWords; i++) {
Words[i] = 0U;
}
done:
return Bytes;
}
void XPm_DumpMemUsage(void)
{
xil_printf("Total buffer size = %d bytes\n\r", MAX_BYTEBUFFER_SIZE);
xil_printf("Used = %d bytes\n\r", FreeBytes - ByteBuffer);
xil_printf("Free = %d bytes\n\r", MAX_BYTEBUFFER_SIZE - (u32)FreeBytes - (u32)ByteBuffer);
xil_printf("\n\r");
}
u32 XPm_In32(u32 RegAddress)
{
return Xil_In32(RegAddress);
}
void XPm_Out32(u32 RegAddress, u32 l_Val)
{
XPm_Pmc *Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
XPm_PsLpDomain *PsLpd = (XPm_PsLpDomain *)XPmPower_GetById(PM_POWER_LPD);
XPm_PsFpDomain *PsFpd = (XPm_PsFpDomain *)XPmPower_GetById(PM_POWER_FPD);
if ((NULL != Pmc) && ((RegAddress & 0xFFFF0000U) == Pmc->PmcIouSlcrBaseAddr)) {
Xil_Out32(Pmc->PmcIouSlcrBaseAddr + PMC_IOU_SLCR_WPROT0_OFFSET,
0x0U);
Xil_Out32(RegAddress, l_Val);
Xil_Out32(Pmc->PmcIouSlcrBaseAddr + PMC_IOU_SLCR_WPROT0_OFFSET,
0x1U);
} else if ((NULL != PsLpd) && ((RegAddress & 0xFFFF0000U) ==
PsLpd->LpdIouSlcrBaseAddr)) {
Xil_Out32(PsLpd->LpdIouSlcrBaseAddr + LPD_IOU_SLCR_WPROT0_OFFSET,
0x0U);
Xil_Out32(RegAddress, l_Val);
Xil_Out32(PsLpd->LpdIouSlcrBaseAddr + LPD_IOU_SLCR_WPROT0_OFFSET,
0x1U);
} else if ((NULL != PsLpd) && ((RegAddress & 0xFFFF0000U) ==
PsLpd->LpdSlcrBaseAddr)) {
Xil_Out32(PsLpd->LpdSlcrBaseAddr + LPD_SLCR_WPROT0_OFFSET,
0x0U);
Xil_Out32(RegAddress, l_Val);
Xil_Out32(PsLpd->LpdSlcrBaseAddr + LPD_SLCR_WPROT0_OFFSET,
0x1U);
} else if ((NULL != PsFpd) && ((RegAddress & 0xFFFF0000U) ==
PsFpd->FpdSlcrBaseAddr)) {
Xil_Out32(PsFpd->FpdSlcrBaseAddr + FPD_SLCR_WPROT0_OFFSET,
0x0U);
Xil_Out32(RegAddress, l_Val);
Xil_Out32(PsFpd->FpdSlcrBaseAddr + FPD_SLCR_WPROT0_OFFSET,
0x1U);
} else {
Xil_Out32(RegAddress, l_Val);
}
}
void XPm_RMW32(u32 RegAddress, u32 Mask, u32 Value)
{
u32 l_Val;
l_Val = XPm_In32(RegAddress);
l_Val = (l_Val & (~Mask)) | (Mask & Value);
XPm_Out32(RegAddress, l_Val);
}
void XPm_Wait(u32 TimeOutCount)
{
u32 TimeOut = TimeOutCount;
while (TimeOut > 0U) {
TimeOut--;
}
}
XStatus XPm_PollForMask(u32 RegAddress, u32 Mask, u32 TimeOutCount)
{
u32 l_RegValue;
u32 TimeOut = TimeOutCount;
/* Read the Register value */
l_RegValue = XPm_In32(RegAddress);
/* Loop while the MAsk is not set or we timeout */
while(((l_RegValue & Mask) != Mask) && (TimeOut > 0U))
{
/* Latch up the Register value again */
l_RegValue = XPm_In32(RegAddress);
/* Decrement the TimeOut Count */
TimeOut--;
}
return ((TimeOut == 0U) ? XPM_PM_TIMEOUT : XST_SUCCESS);
}
XStatus XPm_PollForZero(u32 RegAddress, u32 Mask, u32 TimeOutCount)
{
u32 l_RegValue;
u32 TimeOut = TimeOutCount;
/* Read the Register value */
l_RegValue = XPm_In32(RegAddress);
/* Loop while the MAsk is not set or we timeout */
while(((l_RegValue & Mask) != 0U) && (TimeOut > 0U))
{
/* Latch up the Register value again */
l_RegValue = XPm_In32(RegAddress);
/* Decrement the TimeOut Count */
TimeOut--;
}
return ((TimeOut == 0U) ? XPM_PM_TIMEOUT : XST_SUCCESS);
}
u32 XPm_ComputeParity(u32 Value)
{
Value ^= (Value >> 16U);
Value ^= (Value >> 8U);
Value ^= (Value >> 4U);
Value ^= (Value >> 2U);
Value ^= (Value >> 1U);
return (Value & 1U);
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_api.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xplmi_util.h"
#include "xpm_api.h"
#include "xpm_defs.h"
#include "xpm_psm_api.h"
#include "xpm_pldomain.h"
#include "xpm_pll.h"
#include "xpm_powerdomain.h"
#include "xpm_pmcdomain.h"
#include "xpm_pslpdomain.h"
#include "xpm_psfpdomain.h"
#include "xpm_npdomain.h"
#include "xpm_cpmdomain.h"
#include "xpm_psm.h"
#include "xpm_pmc.h"
#include "xpm_periph.h"
#include "xpm_mem.h"
#include "xpm_apucore.h"
#include "xpm_rpucore.h"
#include "xpm_power.h"
#include "xpm_pin.h"
#include "xplmi.h"
#include "xplmi_modules.h"
#include "xpm_aie.h"
#include "xpm_prot.h"
#include "xpm_regs.h"
#include "xpm_ipi.h"
#include "xsysmonpsv.h"
#include "xpm_notifier.h"
#include "xplmi_error_node.h"
#ifdef STDOUT_BASEADDRESS
#if (STDOUT_BASEADDRESS == 0xFF000000U)
#define NODE_UART PM_DEV_UART_0 /* Assign node ID with UART0 device ID */
#elif (STDOUT_BASEADDRESS == 0xFF010000U)
#define NODE_UART PM_DEV_UART_1 /* Assign node ID with UART1 device ID */
#endif
#endif
#define XPm_RegisterWakeUpHandler(GicId, SrcId, NodeId) \
XPlmi_GicRegisterHandler(((GicId) << (8U)) | ((SrcId) << (16U)), \
XPm_DispatchWakeHandler, (void *)(NodeId))
u32 ResetReason;
u32 SysmonAddresses[XPM_NODEIDX_MONITOR_MAX];
void (* PmRequestCb)(u32 SubsystemId, const u32 EventId, u32 *Payload);
static XPlmi_ModuleCmd XPlmi_PmCmds[PM_API_MAX+1];
static XPlmi_Module XPlmi_Pm =
{
XPLMI_MODULE_XILPM_ID,
XPlmi_PmCmds,
PM_API_MAX+1,
};
/****************************************************************************/
/**
* @brief This function sets the rate of the clock.
*
* @param IpiMask IpiMask of subsystem
* @param ClockId Clock node ID
* @param ClkRate Clock rate
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static int XPm_SetClockRate(const u32 IpiMask, const u32 ClockId, const u32 ClkRate)
{
int Status = XST_FAILURE;
XPm_ClockNode *Clk = XPmClock_GetById(ClockId);
if (NULL == Clk) {
Status = XPM_INVALID_CLKID;
goto done;
}
/* Set rate is allow only for the request come from CDO,
* So by use of IpiMask check that request come from CDO or not,
* If request comes from CDO then IpiMask will 0x00U.
*/
if (0U != IpiMask) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
/* Set rate is allowed only for ref clocks */
if (!ISREFCLK(ClockId)) {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmClock_SetRate(Clk, ClkRate);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function gets the rate of the clock.
*
* @param ClockId Clock node ID
* @param ClkRate Pointer to store clock rate.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static int XPm_GetClockRate(const u32 ClockId, u32 *ClkRate)
{
int Status = XST_SUCCESS;
XPm_ClockNode *Clk = XPmClock_GetById(ClockId);
if (NULL == Clk) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Get rate is allowed only for ref clocks */
if (!ISREFCLK(ClockId)) {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmClock_GetRate(Clk, ClkRate);
done:
return Status;
}
static int XPm_ProcessCmd(XPlmi_Cmd * Cmd)
{
u32 ApiResponse[XPLMI_CMD_RESP_SIZE-1] = {0};
int Status = XST_FAILURE;
XPm_Subsystem *Subsystem = NULL;
u32 SubsystemId = INVALID_SUBSYSID;
u32 *Pload = Cmd->Payload;
u32 Len = Cmd->Len;
u32 SetAddress;
u64 Address;
PmDbg("Processing Cmd %x\r\n", Cmd->CmdId);
if((Cmd->CmdId & 0xFFU) != PM_SET_CURRENT_SUBSYSTEM) {
SubsystemId = XPmSubsystem_GetCurrent();
if(SubsystemId != INVALID_SUBSYSID) {
PmDbg("Using current subsystemId: 0x%x\n\r", SubsystemId);
} else if ((0U == Cmd->IpiMask) && (0U != Cmd->SubsystemId)) {
SubsystemId = Cmd->SubsystemId;
PmDbg("Using subsystemId passed by PLM: 0x%x\n\r", SubsystemId);
/* Use PMC subsystem ID for power domain CDOs. */
if ((u32)XPM_NODECLASS_POWER == NODECLASS(SubsystemId)) {
SubsystemId = PM_SUBSYS_PMC;
}
} else if (0U != Cmd->IpiMask) {
SubsystemId = XPmSubsystem_GetSubSysIdByIpiMask(Cmd->IpiMask);
PmDbg("Using subsystemId mapped to IPI: 0x%x\n\r", SubsystemId);
} else {
/* Required due to MISRA */
PmDbg("[%d] Unknown else case\r\n", __LINE__);
}
Subsystem = XPmSubsystem_GetById(SubsystemId);
if ((NULL == Subsystem) || (Subsystem->State == (u8)OFFLINE)) {
/* Subsystem must not be offline here */
PmErr("Invalid SubsystemId 0x%x\n\r", SubsystemId);
Status = XPM_INVALID_SUBSYSID;
goto done;
}
/* Set subsystem to online if suspended or powered off */
if ((Subsystem->State == (u8)SUSPENDED) ||
(Subsystem->State == (u8)POWERED_OFF)) {
Status = XPmSubsystem_SetState(SubsystemId, (u32)ONLINE);
if (XST_SUCCESS != Status) {
goto done;
}
}
}
switch (Cmd->CmdId & 0xFFU) {
case PM_GET_CHIPID:
Status = XPm_GetChipID(&ApiResponse[0], &ApiResponse[1]);
break;
case PM_GET_API_VERSION:
Status = XPm_GetApiVersion(ApiResponse);
break;
case PM_REQUEST_WAKEUP:
/* setAddress is encoded in the 1st bit of the low-word address */
SetAddress = Pload[1] & 0x1U;
/* addresses are word-aligned, ignore bit 0 */
Address = ((u64) Pload[2]) << 32ULL;
Address += Pload[1] & (~(u64)0x1U);
Status = XPm_RequestWakeUp(SubsystemId, Pload[0],
SetAddress, Address,
Pload[3]);
break;
case PM_FORCE_POWERDOWN:
Status = XPm_ForcePowerdown(SubsystemId, Pload[0], Pload[1]);
break;
case PM_SYSTEM_SHUTDOWN:
Status = XPm_SystemShutdown(SubsystemId, Pload[0], Pload[1]);
break;
case PM_SELF_SUSPEND:
Status = XPm_SelfSuspend(SubsystemId, Pload[0],
Pload[1], (u8)Pload[2],
Pload[3], Pload[4]);
break;
case PM_REQUEST_SUSPEND:
Status = XPm_RequestSuspend(SubsystemId, Pload[0], Pload[1], Pload[2], Pload[3]);
break;
case PM_ABORT_SUSPEND:
Status = XPm_AbortSuspend(SubsystemId, Pload[0], Pload[1]);
break;
case PM_SET_WAKEUP_SOURCE:
Status = XPm_SetWakeUpSource(SubsystemId, Pload[0], Pload[1], Pload[2]);
break;
case PM_CLOCK_SETRATE:
Status = XPm_SetClockRate(Cmd->IpiMask, Pload[0], Pload[1]);
break;
case PM_CLOCK_GETRATE:
Status = XPm_GetClockRate(Pload[0], ApiResponse);
break;
case PM_CLOCK_SETPARENT:
Status = XPm_SetClockParent(SubsystemId, Pload[0], Pload[1]);
break;
case PM_CLOCK_GETPARENT:
Status = XPm_GetClockParent(Pload[0], ApiResponse);
break;
case PM_CLOCK_ENABLE:
Status = XPm_SetClockState(SubsystemId, Pload[0], 1);
break;
case PM_CLOCK_DISABLE:
Status = XPm_SetClockState(SubsystemId, Pload[0], 0);
break;
case PM_CLOCK_GETSTATE:
Status = XPm_GetClockState(Pload[0], ApiResponse);
break;
case PM_CLOCK_SETDIVIDER:
Status = XPm_SetClockDivider(SubsystemId, Pload[0], Pload[1]);
break;
case PM_CLOCK_GETDIVIDER:
Status = XPm_GetClockDivider(Pload[0], ApiResponse);
break;
case PM_PLL_SET_PARAMETER:
Status = XPm_SetPllParameter(SubsystemId, Pload[0], Pload[1], Pload[2]);
break;
case PM_PLL_GET_PARAMETER:
Status = XPm_GetPllParameter(Pload[0], Pload[1], ApiResponse);
break;
case PM_PLL_SET_MODE:
Status = XPm_SetPllMode(SubsystemId, Pload[0], Pload[1]);
break;
case PM_PLL_GET_MODE:
Status = XPm_GetPllMode(Pload[0], ApiResponse);
break;
case PM_REQUEST_NODE:
Status = XPm_RequestDevice(SubsystemId, Pload[0],
Pload[1], Pload[2],
Pload[3]);
break;
case PM_RELEASE_NODE:
Status = XPm_ReleaseDevice(SubsystemId, Pload[0]);
break;
case PM_SET_REQUIREMENT:
Status = XPm_SetRequirement(SubsystemId, Pload[0], Pload[1], Pload[2], Pload[3]);
break;
case PM_SET_MAX_LATENCY:
Status = XPm_SetMaxLatency(SubsystemId, Pload[0],
Pload[1]);
break;
case PM_GET_NODE_STATUS:
Status = XPm_GetDeviceStatus(SubsystemId, Pload[0], (XPm_DeviceStatus *)ApiResponse);
break;
case PM_QUERY_DATA:
Status = XPm_Query(Pload[0], Pload[1], Pload[2],
Pload[3], ApiResponse);
break;
case PM_RESET_ASSERT:
Status = XPm_SetResetState(SubsystemId, Cmd->IpiMask,
Pload[0], Pload[1]);
break;
case PM_RESET_GET_STATUS:
Status = XPm_GetResetState(Pload[0], ApiResponse);
break;
case PM_ADD_SUBSYSTEM:
Status = XPm_AddSubsystem(Pload[0]);
break;
case PM_DESTROY_SUBSYSTEM:
Status = XPm_DestroySubsystem(Pload[0]);
break;
case PM_PINCTRL_REQUEST:
Status = XPm_PinCtrlRequest(SubsystemId, Pload[0]);
break;
case PM_PINCTRL_RELEASE:
Status = XPm_PinCtrlRelease(SubsystemId, Pload[0]);
break;
case PM_PINCTRL_GET_FUNCTION:
Status = XPm_GetPinFunction(Pload[0], ApiResponse);
break;
case PM_PINCTRL_SET_FUNCTION:
Status = XPm_SetPinFunction(SubsystemId, Pload[0], Pload[1]);
break;
case PM_PINCTRL_CONFIG_PARAM_GET:
Status = XPm_GetPinParameter(Pload[0], Pload[1], ApiResponse);
break;
case PM_PINCTRL_CONFIG_PARAM_SET:
Status = XPm_SetPinParameter(SubsystemId, Pload[0], Pload[1], Pload[2]);
break;
case PM_IOCTL:
Status = XPm_DevIoctl(SubsystemId, Pload[0], Pload[1],
Pload[2], Pload[3], ApiResponse);
break;
case PM_INIT_FINALIZE:
Status = XPm_InitFinalize(SubsystemId);
break;
case PM_DESCRIBE_NODES:
Status = XPm_DescribeNodes(Len);
break;
case PM_ADD_NODE:
Status = XPm_AddNode(&Pload[0], Len);
break;
case PM_ADD_NODE_PARENT:
Status = XPm_AddNodeParent(&Pload[0], Len);
break;
case PM_ADD_NODE_NAME:
Status = XPm_AddNodeName(&Pload[0], Len);
break;
case PM_ADD_REQUIREMENT:
Status = XPm_AddRequirement(Pload[0], Pload[1], Pload[2], &Pload[3], Len-3U);
break;
case PM_SET_CURRENT_SUBSYSTEM:
Status = XPm_SetCurrentSubsystem(Pload[0]);
break;
case PM_INIT_NODE:
Status = XPm_InitNode(Pload[0], Pload[1], &Pload[2], Len-2U);
break;
case PM_FEATURE_CHECK:
Status = XPm_FeatureCheck(Pload[0], ApiResponse);
break;
case PM_ISO_CONTROL:
Status = XPm_IsoControl(Pload[0], Pload[1]);
break;
case PM_GET_OP_CHARACTERISTIC:
Status = XPm_GetOpCharacteristic(Pload[0], Pload[1],
ApiResponse);
break;
case PM_REGISTER_NOTIFIER:
Status = XPm_RegisterNotifier(SubsystemId, Pload[0],
Pload[1], Pload[2],
Pload[3], Cmd->IpiMask);
break;
default:
PmErr("CMD: INVALID PARAM\n\r");
Status = XST_INVALID_PARAM;
break;
}
/* First word of the response is status */
Cmd->Response[0] = (u32)Status;
(void)XPlmi_MemCpy(&Cmd->Response[1], ApiResponse, sizeof(ApiResponse));
if (Status == XST_SUCCESS) {
Cmd->ResumeHandler = NULL;
} else {
PmErr("Error %d while processing command 0x%x\r\n", Status, Cmd->CmdId);
PmDbg("Command payload: 0x%x, 0x%x, 0x%x, 0x%x\r\n",
Pload[0], Pload[1], Pload[2], Pload[3]);
}
done:
if(Status != XST_SUCCESS) {
PmErr("Err Code: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief Register wakeup handlers with XilPlmi
* @param none
* @return none
****************************************************************************/
static void XPm_RegisterWakeUpHandlers(void)
{
/**
* Register the events for PM
*/
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC13, XPM_NODEIDX_DEV_GPIO);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC14, XPM_NODEIDX_DEV_I2C_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC15, XPM_NODEIDX_DEV_I2C_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC16, XPM_NODEIDX_DEV_SPI_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC17, XPM_NODEIDX_DEV_SPI_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC18, XPM_NODEIDX_DEV_UART_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC19, XPM_NODEIDX_DEV_UART_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC20, XPM_NODEIDX_DEV_CAN_FD_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC21, XPM_NODEIDX_DEV_CAN_FD_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC22, XPM_NODEIDX_DEV_USB_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC23, XPM_NODEIDX_DEV_USB_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC24, XPM_NODEIDX_DEV_USB_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC25, XPM_NODEIDX_DEV_USB_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP0, (u32)XPLMI_GICP0_SRC26, XPM_NODEIDX_DEV_USB_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC5, XPM_NODEIDX_DEV_TTC_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC6, XPM_NODEIDX_DEV_TTC_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC7, XPM_NODEIDX_DEV_TTC_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC8, XPM_NODEIDX_DEV_TTC_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC9, XPM_NODEIDX_DEV_TTC_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC10, XPM_NODEIDX_DEV_TTC_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC11, XPM_NODEIDX_DEV_TTC_2);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC12, XPM_NODEIDX_DEV_TTC_2);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC13, XPM_NODEIDX_DEV_TTC_2);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC14, XPM_NODEIDX_DEV_TTC_3);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC15, XPM_NODEIDX_DEV_TTC_3);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC16, XPM_NODEIDX_DEV_TTC_3);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC24, XPM_NODEIDX_DEV_GEM_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC25, XPM_NODEIDX_DEV_GEM_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC26, XPM_NODEIDX_DEV_GEM_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC27, XPM_NODEIDX_DEV_GEM_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC28, XPM_NODEIDX_DEV_ADMA_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC29, XPM_NODEIDX_DEV_ADMA_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC30, XPM_NODEIDX_DEV_ADMA_2);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP1, (u32)XPLMI_GICP1_SRC31, XPM_NODEIDX_DEV_ADMA_3);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP2, (u32)XPLMI_GICP2_SRC0, XPM_NODEIDX_DEV_ADMA_4);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP2, (u32)XPLMI_GICP2_SRC1, XPM_NODEIDX_DEV_ADMA_5);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP2, (u32)XPLMI_GICP2_SRC2, XPM_NODEIDX_DEV_ADMA_6);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP2, (u32)XPLMI_GICP2_SRC3, XPM_NODEIDX_DEV_ADMA_7);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP2, (u32)XPLMI_GICP2_SRC10, XPM_NODEIDX_DEV_USB_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP3, (u32)XPLMI_GICP3_SRC30, XPM_NODEIDX_DEV_SDIO_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP3, (u32)XPLMI_GICP3_SRC31, XPM_NODEIDX_DEV_SDIO_0);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP4, (u32)XPLMI_GICP4_SRC0, XPM_NODEIDX_DEV_SDIO_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP4, (u32)XPLMI_GICP4_SRC1, XPM_NODEIDX_DEV_SDIO_1);
XPm_RegisterWakeUpHandler((u32)XPLMI_PMC_GIC_IRQ_GICP4, (u32)XPLMI_GICP4_SRC14, XPM_NODEIDX_DEV_RTC);
}
/****************************************************************************/
/**
* @brief Initialize XilPM library
*
* @param IpiInst IPI instance
* @param RequestCb Pointer to the request calbback handler
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_Init(void (* const RequestCb)(u32 SubsystemId, const u32 EventId, u32 *Payload))
{
XStatus Status = XST_FAILURE;
unsigned int i;
u32 Version;
u32 RegValue;
u32 PmcIPORMask = (CRP_RESET_REASON_ERR_POR_MASK |
CRP_RESET_REASON_SLR_POR_MASK |
CRP_RESET_REASON_SW_POR_MASK);
u32 SysResetMask = (CRP_RESET_REASON_SLR_SYS_MASK |
CRP_RESET_REASON_SW_SYS_MASK |
CRP_RESET_REASON_ERR_SYS_MASK |
CRP_RESET_REASON_DAP_SYS_MASK);
u32 IsolationIdx[] = {
(u32)XPM_NODEIDX_ISO_VCCAUX_VCCRAM,
(u32)XPM_NODEIDX_ISO_VCCRAM_SOC,
(u32)XPM_NODEIDX_ISO_VCCAUX_SOC,
(u32)XPM_NODEIDX_ISO_PL_SOC,
(u32)XPM_NODEIDX_ISO_PMC_SOC,
(u32)XPM_NODEIDX_ISO_PMC_SOC_NPI,
(u32)XPM_NODEIDX_ISO_PMC_PL,
(u32)XPM_NODEIDX_ISO_PMC_LPD,
(u32)XPM_NODEIDX_ISO_LPD_SOC,
(u32)XPM_NODEIDX_ISO_LPD_PL,
(u32)XPM_NODEIDX_ISO_LPD_CPM,
(u32)XPM_NODEIDX_ISO_FPD_SOC,
(u32)XPM_NODEIDX_ISO_FPD_PL,
};
PmInfo("Initializing LibPM\n\r");
PmRequestCb = RequestCb;
/* Register command handlers with eFSBL */
for (i = 1; i < XPlmi_Pm.CmdCnt; i++) {
XPlmi_PmCmds[i].Handler = XPm_ProcessCmd;
}
XPlmi_ModuleRegister(&XPlmi_Pm);
XPm_PsmModuleInit();
PmIn32(PMC_TAP_VERSION, Version);
PlatformVersion = ((Version & PMC_TAP_VERSION_PLATFORM_VERSION_MASK) >>
PMC_TAP_VERSION_PLATFORM_VERSION_SHIFT);
Platform = ((Version & PMC_TAP_VERSION_PLATFORM_MASK) >>
PMC_TAP_VERSION_PLATFORM_SHIFT);
PmIn32(PMC_TAP_SLR_TYPE_OFFSET + PMC_TAP_BASEADDR, RegValue);
SlrType = (RegValue & PMC_TAP_SLR_TYPE_MASK);
/* Read and store the reset reason value */
PmIn32(CRP_RESET_REASON, ResetReason);
if (0U != (ResetReason & SysResetMask)) {
/* Clear the system reset bits of reset_reason register */
PmOut32(CRP_RESET_REASON, (ResetReason & SysResetMask));
/* Enable domain isolations after system reset */
for (i = 0; i < ARRAY_SIZE(IsolationIdx); i++) {
Status = XPmDomainIso_Control(IsolationIdx[i], TRUE_VALUE);
if (Status != XST_SUCCESS) {
goto done;
}
}
/* For some boards, vccaux workaround is implemented using gpio to control vccram supply.
During system reset, when gpio goes low, delay is required for system controller to process
vccram rail off, before pdi load is started */
if ((PLATFORM_VERSION_SILICON == Platform) && (PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
usleep(300000);
}
}
/*
* Clear DomainInitStatusReg in case of internal PMC_POR. Since PGGS0
* value is not cleared in case of internal POR.
*/
if (0U != (ResetReason & PmcIPORMask)) {
XPm_Out32(XPM_DOMAIN_INIT_STATUS_REG, 0);
}
XPm_RegisterWakeUpHandlers();
Status = XPmSubsystem_Add(PM_SUBSYS_PMC);
done:
return Status;
}
/*****************************************************************************/
/**
* @brief This is the handler for wake up interrupts
*
* @param DeviceIdx Index of peripheral device
*
* @return Status XST_SUCCESS if processor wake successfully
* XST_FAILURE or error code in case of failure
*
*****************************************************************************/
int XPm_DispatchWakeHandler(void *DeviceIdx)
{
int Status;
Status = XPm_GicProxyWakeUp((u32)DeviceIdx);
return Status;
}
static void AddPld0Device(void)
{
XPm_Device *Device = XPmDevice_GetById(PM_DEV_PLD_0);
int Status;
if (NULL == Device) {
u32 Args[3] = {PM_DEV_PLD_0, PM_POWER_PLD};
u32 Parents[] = {PM_CLK_PMC_PL0_REF, PM_CLK_PMC_PL1_REF,
PM_CLK_PMC_PL2_REF, PM_CLK_PMC_PL3_REF,
PM_RST_PL0, PM_RST_PL1, PM_RST_PL2,
PM_RST_PL3};
Status = XPm_AddNode(Args, (u32)ARRAY_SIZE(Args));
if (XST_SUCCESS != Status) {
PmWarn("Error %d in adding PLD0 device\r\n", Status);
}
Status = XPmDevice_AddParent(PM_DEV_PLD_0, Parents,
(u32)ARRAY_SIZE(Parents));
if (XST_SUCCESS != Status) {
PmWarn("Error %d in add patent for PLD0 device\r\n",
Status);
}
}
}
static void AddIPIPmcDevice(void)
{
XPm_Device *Device = XPmDevice_GetById(PM_DEV_IPI_PMC);
int Status;
if (NULL == Device) {
u32 Args[3] = {PM_DEV_IPI_PMC, PM_POWER_LPD};
u32 Parents[] = {PM_RST_IPI};
Status = XPm_AddNode(Args, (u32)ARRAY_SIZE(Args));
if (XST_SUCCESS != Status) {
PmWarn("Error %d in adding PLD0 device\r\n", Status);
}
Status = XPmDevice_AddParent(PM_DEV_IPI_PMC, Parents,
(u32)ARRAY_SIZE(Parents));
if (XST_SUCCESS != Status) {
PmWarn("Error %d in add patent for PLD0 device\r\n",
Status);
}
}
}
static void PostTopologyHook(void)
{
/**
* Currently PLD0 device is not added through CDO. This will create
* issues when dynamic subsystems are supported. So add workaround for
* adding PLD0 device from XilPM until CDO changes to add PLD0 device
* from topology are there.
* TODO: Remove this workaround when CDO changes to add PLD0 device
* will available in tools.
*/
AddPld0Device();
/**
* TODO: Remove this workaround when CDO changes to add PMC IPI device
* will available in tools.
*/
AddIPIPmcDevice();
}
XStatus XPm_HookAfterPlmCdo(void)
{
XStatus Status = XST_FAILURE;
/*
* There is a silicon problem where on 2-4% of Versal ES1 S80 devices
* you can get 12A of VCCINT_PL current before CFI housecleaning is run.
* The problem is eliminated when PL Vgg frame housecleaning is run
* so we need to do that ASAP after PLM is loaded.
* Otherwise also, PL housecleaning needs to be trigerred asap to reduce
* boot time.
*/
XPmPlDomain_InitandHouseclean();
// On Boot, Update PMC SAT0 & SAT1 sysmon trim
(void)XPmPowerDomain_ApplyAmsTrim(SysmonAddresses[XPM_NODEIDX_MONITOR_SYSMON_PMC_0], PM_POWER_PMC, 0);
(void)XPmPowerDomain_ApplyAmsTrim(SysmonAddresses[XPM_NODEIDX_MONITOR_SYSMON_PMC_1], PM_POWER_PMC, 1);
PostTopologyHook();
/**
* VCK190/VMK180 boards have VCC_AUX workaround where MIO-37 (PMC GPIO)
* is used to enable the VCC_RAM which used to power the PL.
* As a result, if PMC GPIO is disabled, VCC_RAM goes off.
* To prevent this from happening, request PMC GPIO device on behalf PMC subsystem.
* This will take care of the use cases where PMC is up.
* GPIO will get reset only when PMC goes down.
*
* The VCC_AUX workaround will be removed from MIO-37 in ES2 going ahead.
*/
if ((PLATFORM_VERSION_SILICON == Platform) &&
(PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
Status = XPmDevice_Request(PM_SUBSYS_PMC, PM_DEV_GPIO_PMC,
XPM_MAX_CAPABILITY, XPM_MAX_QOS);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to request the version and ID code of a chip
*
* @param IDCode Returns the chip ID code.
* @param Version Returns the chip version.
*
* @return XST_SUCCESS
*
* @note None
*
****************************************************************************/
int XPm_GetChipID(u32* IDCode, u32 *Version)
{
/* Read the chip ID code */
PmIn32(PMC_TAP_IDCODE, *IDCode);
/* Read the chip version */
PmIn32(PMC_TAP_VERSION, *Version);
return XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief This function is used to request the version number of the API
* running on the power management controller.
*
* @param Version Returns the API 32-bit version number.
* Returns 0 if no firmware present.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_GetApiVersion(u32 *Version)
{
*Version = PM_VERSION;
return XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief This function configures the
* platform resources for the new subsystem.
*
* @param SubSystemCdo Pointer to the subsystem CDO
* @param NotifyCb Pointer to the notify callback handler
* @param SubsystemId Address to store the new subsystem ID
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note The provided address must be in an address space which is
* accessible by the callee. There will be no change if the subsystem CDO
* is incompatible or if the required resources are not available, so no
* clean-up will be necessary
*
****************************************************************************/
XStatus XPm_AddSubsystem(u32 SubsystemId)
{
XStatus Status = XST_FAILURE;
Status = XPmSubsystem_Add(SubsystemId);
if (Status != XST_SUCCESS) {
PmErr("Failed to configure platform resources\n\r");
}
return Status;
}
/****************************************************************************/
/**
* @brief This function allows to set current subsystem id.
*
* @param SubsystemId Address to store the new subsystem ID
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note none
*
****************************************************************************/
XStatus XPm_SetCurrentSubsystem(u32 SubsystemId)
{
XStatus Status = XST_FAILURE;
Status = XPmSubsystem_SetCurrent(SubsystemId);
if (Status != XST_SUCCESS) {
PmErr("Unable to set current subsystem. Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function allows to initialize the node.
*
* @param NodeId Supported power domain nodes only
* @param Function Function id
* @param Args Arguments speicifc to function
* @param NumArgs Number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note none
*
****************************************************************************/
XStatus XPm_InitNode(u32 NodeId, u32 Function, u32 *Args, u32 NumArgs)
{
XStatus Status = XST_FAILURE;
XPm_PowerDomain *PwrDomainNode;
if (((u32)XPM_NODECLASS_POWER != NODECLASS(NodeId)) ||
((u32)XPM_NODESUBCL_POWER_DOMAIN != NODESUBCLASS(NodeId)) ||
((u32)XPM_NODEIDX_POWER_MAX <= NODEINDEX(NodeId))) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
PwrDomainNode = (XPm_PowerDomain *)XPmPower_GetById(NodeId);
if (NULL == PwrDomainNode) {
PmErr("Unable to find Power Domain for given Node Id\n\r");
Status = XPM_PM_INVALID_NODE;
goto done;
}
switch (NODEINDEX(NodeId)) {
case (u32)XPM_NODEIDX_POWER_PMC:
case (u32)XPM_NODEIDX_POWER_LPD:
case (u32)XPM_NODEIDX_POWER_FPD:
case (u32)XPM_NODEIDX_POWER_NOC:
case (u32)XPM_NODEIDX_POWER_PLD:
case (u32)XPM_NODEIDX_POWER_ME:
case (u32)XPM_NODEIDX_POWER_CPM:
case (u32)XPM_NODEIDX_POWER_CPM5:
Status = XPmPowerDomain_InitDomain(PwrDomainNode, Function,
Args, NumArgs);
break;
default:
Status = XPM_INVALID_PWRDOMAIN;
PmErr("Unrecognized Power Domain: 0x%x\n\r", NODEINDEX(NodeId));
break;
}
/*
* Call LPD init to initialize required components
*/
if ((NODEINDEX(NodeId) == (u32)XPM_NODEIDX_POWER_LPD) &&
(Function == (u32)FUNC_INIT_FINISH) &&
(XST_SUCCESS == Status)) {
#ifdef DEBUG_UART_PS
/**
* PLM needs to request UART if debug is enabled, else LibPM
* will turn it off when it is not used by other processor.
* During such scenario when PLM tries to print debug message,
* system may not work properly.
*/
Status = XPm_RequestDevice(PM_SUBSYS_PMC, NODE_UART,
(u32)PM_CAP_ACCESS, XPM_MAX_QOS, 0);
if (XST_SUCCESS != Status) {
goto done;
}
#endif
/**
* PLM needs to request PMC IPI, else LibPM will reset IPI
* when it is not used by other processor. Because of that PLM
* hangs when it tires to communicate through IPI.
*/
Status = XPm_RequestDevice(PM_SUBSYS_PMC, PM_DEV_IPI_PMC,
(u32)PM_CAP_ACCESS, XPM_MAX_QOS, 0);
if (XST_SUCCESS != Status) {
PmErr("Error %d in request IPI PMC\r\n", Status);
}
XPlmi_LpdInit();
}
done:
if (Status != XST_SUCCESS) {
PmErr("Unable to initialize node. Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function allows to control isolation nodes.
*
* @param Isoaltion NodeId Supported isoaltion nodes only
* @param Enable/Disable
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note none
*
****************************************************************************/
XStatus XPm_IsoControl(u32 NodeId, u32 Enable)
{
XStatus Status = XST_FAILURE;
if (((u32)XPM_NODECLASS_ISOLATION != NODECLASS(NodeId)) ||
((u32)XPM_NODEIDX_ISO_MAX <= NODEINDEX(NodeId))) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
Status = XPmDomainIso_Control(NODEINDEX(NodeId), Enable);
done:
if (Status != XST_SUCCESS) {
PmErr("Unable to initialize node. Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function releases all the resources of a subsystem. The
* subsystem ID will become invalid.
*
* @param SubsystemId Subsystem ID
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_DestroySubsystem(u32 SubsystemId)
{
XStatus Status = XST_FAILURE;
Status = XPmSubsystem_Destroy(SubsystemId);
if (Status != XST_SUCCESS) {
PmErr("Unable release node. Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function can be used by a subsystem to aborting suspend of a
* child subsystem.
*
* @param SubsystemId Subsystem ID
* @param Reason Abort reason
* @param DeviceId Processor device ID
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_AbortSuspend(const u32 SubsystemId, const u32 Reason,
const u32 DeviceId)
{
XStatus Status = XST_FAILURE;
XPm_Core *Core;
PmInfo("(%lu, %lu)\r\n", Reason, DeviceId);
if((NODECLASS(DeviceId) == (u32)XPM_NODECLASS_DEVICE) &&
(NODESUBCLASS(DeviceId) == (u32)XPM_NODESUBCL_DEV_CORE)) {
Core = (XPm_Core *)XPmDevice_GetById(DeviceId);
if (NULL == Core) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
Core->Device.Node.State = (u8)XPM_DEVSTATE_RUNNING;
} else {
PmErr("Invalid Device Id\n\r");
Status = XPM_PM_INVALID_NODE;
goto done;
}
DISABLE_WFI(Core->SleepMask);
Status = XPmSubsystem_SetState(SubsystemId, (u32)ONLINE);
done:
if (Status != XST_SUCCESS) {
PmErr("Unable to abort suspend child subsystem. Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function can be used by a subsystem to suspend a child
* subsystem.
*
* @param SubsystemId Subsystem ID
* @param DeviceId Processor device ID
* @param Latency Maximum wake-up latency requirement in us(microsecs)
* @param State Instead of specifying a maximum latency, a CPU can also
* explicitly request a certain power state.
* @param AddressLow Lower Address from which to resume when wake up.
* @param AddressHigh Higher Address from which to resume when wake up.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_SelfSuspend(const u32 SubsystemId, const u32 DeviceId,
const u32 Latency, const u8 State,
u32 AddrLow, u32 AddrHigh)
{
XStatus Status = XST_FAILURE;
XPm_Core *Core;
u64 Address = (u64)AddrLow + ((u64)AddrHigh << 32ULL);
XPm_Requirement *Reqm;
/* TODO: Remove this warning fix hack when functionality is implemented */
(void)Latency;
if ((NODECLASS(DeviceId) == (u32)XPM_NODECLASS_DEVICE) &&
(NODESUBCLASS(DeviceId) == (u32)XPM_NODESUBCL_DEV_CORE)) {
Core = (XPm_Core *)XPmDevice_GetById(DeviceId);
if (NULL == Core) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
Core->ResumeAddr = Address | 1U;
Core->Device.Node.State = (u8)XPM_DEVSTATE_SUSPENDING;
} else {
Status = XPM_INVALID_DEVICEID;
goto done;
}
ENABLE_WFI(Core->SleepMask);
if (PM_SUSPEND_STATE_SUSPEND_TO_RAM == State) {
Status = XPmSubsystem_SetState(SubsystemId, (u32)SUSPENDING);
if (XST_SUCCESS != Status) {
goto done;
}
}
/* If subsystem is using DDR, enable self-refresh as post suspend requirement*/
if (PM_SUSPEND_STATE_SUSPEND_TO_RAM == State) {
Reqm = XPmDevice_FindRequirement(PM_DEV_DDR_0, SubsystemId);
if (XST_SUCCESS == XPmRequirement_IsExclusive(Reqm)) {
Status = XPmDevice_SetRequirement(SubsystemId, PM_DEV_DDR_0,
(u32)PM_CAP_CONTEXT, 0);
if (XST_SUCCESS != Status) {
goto done;
}
}
}
Status = XST_SUCCESS;
done:
if (XST_SUCCESS != Status) {
PmErr("Unable to Self Suspend child subsystem. Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function can be used by a subsystem to send suspend request
* to another subsystem. If the target subsystem accepts the request, it
* needs to initiate its own self suspend.
*
* @param SubsystemId Subsystem ID
* @param TargetSubsystemId Target subsystem ID (cannot be the same subsystem)
* @param Ack Ack request
* @param Latency Desired wakeup latency
* @param State Desired power state
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note This function does not block. A successful return code means that
* the request has been sent.
*
****************************************************************************/
XStatus XPm_RequestSuspend(const u32 SubsystemId, const u32 TargetSubsystemId,
const u32 Ack, const u32 Latency, const u32 State)
{
XStatus Status = XST_FAILURE;
u32 IpiMask = 0;
u32 Payload[5] = {0};
/* Warning Fix */
(void) (Ack);
IpiMask = XPmSubsystem_GetIPIMask(TargetSubsystemId);
if (0U == IpiMask) {
PmErr("Unable to fetch IpiMask for given TargetSubsystem\r\n");
Status = XPM_INVALID_SUBSYSID;
goto done;
}
if (SubsystemId == TargetSubsystemId) {
Status = XPM_INVALID_SUBSYSID;
PmErr("Cannot Suspend yourself\n\r");
goto done;
}
/* TODO: Check if current subsystem has access to request target subsystem */
/* Failure in this case should return XPM_PM_NO_ACCESS */
/* TODO: Target subsystem must be active to get the suspend request */
/* TODO: Check if other subsystem has sent suspend request to target subsystem */
/* Failure in this case should return XPM_PM_DOUBLE_REQ */
Payload[0] = (u32)PM_INIT_SUSPEND_CB;
Payload[1] = (u32)SUSPEND_REASON_PU_REQ;
Payload[2] = Latency;
Payload[3] = State;
/* Payload[4] is for timeout which is not considered */
Payload[4] = 0U;
/* Send the suspend request via callback */
if (NULL != PmRequestCb) {
(*PmRequestCb)(IpiMask, PM_INIT_SUSPEND_CB, Payload);
}
Status = XST_SUCCESS;
done:
if (Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
int XPm_GicProxyWakeUp(const u32 PeriphIdx)
{
int Status = XST_FAILURE;
XPm_Periph *Periph = (XPm_Periph *)XPmDevice_GetByIndex(PeriphIdx);
if ((NULL == Periph) || (0U == Periph->WakeProcId)) {
goto done;
}
Status = XPm_RequestWakeUp(PM_SUBSYS_PMC, Periph->WakeProcId, 0, 0, 0);
done:
return Status;
}
int XPm_SubsystemPwrUp(const u32 SubsystemId)
{
XStatus Status = XST_FAILURE;
/* Add a workaround to power on FPD before
* subsystem wakeup if FPD is off.
* TODO: This workaround will be reverted,
* once recursive CDO loading support is available.
*/
XPm_Power *FpdPwrNode = XPmPower_GetById(PM_POWER_FPD);
if ((NULL != FpdPwrNode) &&
((u8)XPM_POWER_STATE_OFF == FpdPwrNode->Node.State)) {
Status = XPm_PowerUpFPD(&FpdPwrNode->Node);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XLoader_RestartImage(SubsystemId);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function can be used by a subsystem to start-up and wake-up
* a child subsystem. If the target subsystem has been loaded and is ready
* to run, it will start running. If the target subsystem is suspended, it
* will resume.
*
* @param SubsystemId Subsystem ID
* @param DeviceId Processor device ID
* @param SetAddress Specifies whether to set the start address.
* - 0 : do not set start address
* - 1 : set start address
* @param Address Address from which to resume when woken up.
* @param Ack Ack request
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note This function does not block. A successful return code means that
* the request has been received.
*
****************************************************************************/
XStatus XPm_RequestWakeUp(u32 SubsystemId, const u32 DeviceId,
const u32 SetAddress, const u64 Address,
const u32 Ack)
{
XStatus Status = XST_FAILURE;
XPm_Core *Core;
u32 CoreSubsystemId, CoreDeviceId;
XPm_Requirement *Reqm;
XPm_Power *Power;
/* Warning Fix */
(void) (Ack);
/*Validate access first */
Status = XPm_IsWakeAllowed(SubsystemId, DeviceId);
if (XST_SUCCESS != Status) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
switch (NODECLASS(DeviceId))
{
case (u32)XPM_NODECLASS_SUBSYSTEM:
CoreSubsystemId = DeviceId;
Status = XPm_SubsystemPwrUp(CoreSubsystemId);
break;
case (u32)XPM_NODECLASS_DEVICE:
CoreDeviceId = DeviceId;
Core = (XPm_Core *)XPmDevice_GetById(CoreDeviceId);
if ((NULL == Core) ||
(NULL == Core->CoreOps->RequestWakeup)) {
Status = XPM_ERR_WAKEUP;
break;
}
if (((u32)XPM_NODETYPE_DEV_CORE_APU == NODETYPE(CoreDeviceId)) ||
((u32)XPM_NODETYPE_DEV_CORE_RPU == NODETYPE(CoreDeviceId)) ||
((u32)XPM_NODETYPE_DEV_CORE_PSM == NODETYPE(CoreDeviceId))) {
/* Power up LPD if not powered up */
Power = XPmPower_GetById(PM_POWER_LPD);
if ((NULL != Power) && ((u8)XPM_POWER_STATE_OFF == Power->Node.State)) {
Status = XLoader_RestartImage(Power->Node.Id);
if (XST_SUCCESS != Status) {
goto done;
}
}
}
CoreSubsystemId = XPmDevice_GetSubsystemIdOfCore((XPm_Device *)Core);
if (INVALID_SUBSYSID == CoreSubsystemId) {
Status = XPM_ERR_SUBSYS_NOTFOUND;
break;
}
Status = Core->CoreOps->RequestWakeup(Core, SetAddress, Address);
if (XST_SUCCESS == Status) {
Status = XPmSubsystem_SetState(CoreSubsystemId, (u32)ONLINE);
if (XST_SUCCESS != Status) {
goto done;
}
}
break;
default:
Status = XST_INVALID_PARAM;
break;
}
if (XST_SUCCESS != Status) {
goto done;
}
/* If subsystem is using DDR, disable self-refresh */
Reqm = XPmDevice_FindRequirement(PM_DEV_DDR_0, CoreSubsystemId);
if (XST_SUCCESS == XPmRequirement_IsExclusive(Reqm)) {
Status = XPmDevice_SetRequirement(CoreSubsystemId, PM_DEV_DDR_0,
(u32)PM_CAP_ACCESS, 0);
}
done:
if (XST_SUCCESS != Status) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function can be used by a subsystem to Powerdown other
* processor or domain node forcefully. To powerdown whole
* subsystem, this function needs to be called for all processors
* of target subsystem, which in turn will power down the whole
* subsystem
*
* @param SubsystemId Subsystem ID
* @param Node Processor or domain node to be powered down
* @param Ack Ack request
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note The affected PUs are not notified about the upcoming powerdown,
* and PMU does not wait for their WFI interrupt.
*
****************************************************************************/
XStatus XPm_ForcePowerdown(u32 SubsystemId, const u32 NodeId, const u32 Ack)
{
XStatus Status = XST_FAILURE;
XPm_Core *Core;
XPm_Device *Device;
XPm_Power *Power;
XPm_Requirement *Reqm;
u32 i;
XPm_Power *Acpu0PwrNode = XPmPower_GetById(PM_POWER_ACPU_0);
XPm_Power *Acpu1PwrNode = XPmPower_GetById(PM_POWER_ACPU_1);
XPm_Power *FpdPwrNode = XPmPower_GetById(PM_POWER_FPD);
XPm_Subsystem *TargetSubsystem = NULL;
u32 DeviceId = 0U;
/* Warning Fix */
(void) (Ack);
/*Validate access first */
Status = XPm_IsForcePowerDownAllowed(SubsystemId, NodeId);
if (XST_SUCCESS != Status) {
goto done;
}
if ((NODECLASS(NodeId) == (u32)XPM_NODECLASS_DEVICE) &&
(NODESUBCLASS(NodeId) == (u32)XPM_NODESUBCL_DEV_CORE)) {
Core = (XPm_Core *)XPmDevice_GetById(NodeId);
if ((NULL != Core) && (NULL != Core->CoreOps)
&& (NULL != Core->CoreOps->PowerDown)) {
Status = Core->CoreOps->PowerDown(Core);
if (XST_SUCCESS != Status) {
goto done;
}
/* Disable the direct wake in case of force power down */
DISABLE_WAKE(Core->SleepMask);
} else {
Status = XST_FAILURE;
goto done;
}
/* Do APU GIC pulse reset if All the cores are in Power OFF
* state and FPD in Power ON state.
* Now APU has two core as ACPU0 and ACPU1.
*/
if (((PM_DEV_ACPU_0 == NodeId) || (PM_DEV_ACPU_1 == NodeId)) &&
(NULL != Acpu0PwrNode) && (NULL != Acpu1PwrNode) &&
(NULL != FpdPwrNode)) {
if (((u8)XPM_POWER_STATE_OFF != FpdPwrNode->Node.State) &&
((u8)XPM_POWER_STATE_OFF == Acpu0PwrNode->Node.State) &&
((u8)XPM_POWER_STATE_OFF == Acpu1PwrNode->Node.State)) {
Status = XPmReset_AssertbyId(PM_RST_ACPU_GIC, (u32)PM_RESET_ACTION_PULSE);
if (XST_SUCCESS != Status) {
goto done;
}
}
}
} else if ((u32)XPM_NODECLASS_POWER == NODECLASS(NodeId)) {
if ((u32)XPM_NODESUBCL_POWER_ISLAND == NODESUBCLASS(NodeId)) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
if ((u32)XPM_NODESUBCL_POWER_DOMAIN != NODESUBCLASS(NodeId)) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
/*
* PMC power domain can not be powered off.
*/
if ((u32)XPM_NODEIDX_POWER_PMC == NODEINDEX(NodeId)) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
/*
* Release devices belonging to the power domain.
*/
for (i = 1; i < (u32)XPM_NODEIDX_DEV_MAX; i++) {
/*
* Note: XPmDevice_GetByIndex() assumes that the caller
* is responsible for validating the Node ID attributes
* other than node index.
*/
Device = XPmDevice_GetByIndex(i);
if ((NULL == Device) ||
((u32)XPM_DEVSTATE_UNUSED == Device->Node.State)) {
continue;
}
/*
* Check power topology of this device to identify
* if it belongs to the power domain.
*/
Power = Device->Power;
while (NULL != Power) {
if (NodeId == Power->Node.Id) {
if ((u32)XPM_NODESUBCL_DEV_CORE == NODESUBCLASS(Device->Node.Id)) {
Core = (XPm_Core *)XPmDevice_GetById(Device->Node.Id);
if ((NULL != Core) &&
(NULL != Core->CoreOps) &&
(NULL != Core->CoreOps->PowerDown)) {
PmDbg("Powering down core 0x%x\r\n", Device->Node.Id);
Status = Core->CoreOps->PowerDown(Core);
if (XST_SUCCESS != Status) {
goto done;
}
/*
* Disable the direct
* wake in case of force
* power down
*/
DISABLE_WAKE(Core->SleepMask);
} else {
Status = XST_FAILURE;
goto done;
}
}
Status = XPmRequirement_Release(
Device->Requirements, RELEASE_DEVICE);
if (XST_SUCCESS != Status) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
}
Power = Power->Parent;
}
}
} else if ((u32)XPM_NODECLASS_SUBSYSTEM == NODECLASS(NodeId)) {
TargetSubsystem = XPmSubsystem_GetById(NodeId);
if (NULL == TargetSubsystem) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
Reqm = TargetSubsystem->Requirements;
while (NULL != Reqm) {
if ((1U == Reqm->Allocated) &&
((u32)XPM_NODESUBCL_DEV_CORE == NODESUBCLASS(Reqm->Device->Node.Id))) {
DeviceId = Reqm->Device->Node.Id;
Status = XPm_ForcePowerdown(SubsystemId, DeviceId, 0U);
if (XST_SUCCESS != Status) {
goto done;
}
}
Reqm = Reqm->NextDevice;
}
/* Idle the subsystem */
Status = XPmSubsystem_Idle(TargetSubsystem->Id);
if(XST_SUCCESS != Status) {
Status = XPM_ERR_SUBSYS_IDLE;
goto done;
}
Status = XPmSubsystem_ForceDownCleanup(TargetSubsystem->Id);
if(XST_SUCCESS != Status) {
Status = XPM_ERR_CLEANUP;
goto done;
}
Status = XPmSubsystem_SetState(TargetSubsystem->Id, (u32)POWERED_OFF);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
Status = XPM_PM_INVALID_NODE;
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function can be used by a subsystem to shutdown self or restart
* self, Ps or system
*
* @param SubsystemId Subsystem ID
* @param Type Shutdown type
* @param SubType Shutdown subtype
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note This function does not block. A successful return code means that
* the request has been received.
*
****************************************************************************/
XStatus XPm_SystemShutdown(u32 SubsystemId, const u32 Type, const u32 SubType)
{
XStatus Status = XST_FAILURE;
XPm_Subsystem *Subsystem;
if ((PM_SHUTDOWN_TYPE_SHUTDOWN != Type) &&
(PM_SHUTDOWN_TYPE_RESET != Type)) {
Status = XPM_INVALID_TYPEID;
goto done;
}
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
/* For shutdown type the subtype is irrelevant: shut the caller down */
if (PM_SHUTDOWN_TYPE_SHUTDOWN == Type) {
/* Idle the subsystem first */
Status = XPmSubsystem_Idle(SubsystemId);
if (XST_SUCCESS != Status) {
Status = XPM_ERR_SUBSYS_IDLE;
goto done;
}
/* Release devices and power down cores */
Status = XPmSubsystem_ForceDownCleanup(SubsystemId);
if (XST_SUCCESS != Status) {
Status = XPM_ERR_CLEANUP;
goto done;
}
Status = XPmSubsystem_SetState(SubsystemId, (u32)POWERED_OFF);
goto done;
}
switch (SubType) {
case PM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM:
Status = XPmSubsystem_Restart(SubsystemId);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_SubsystemPwrUp(SubsystemId);
if (XST_SUCCESS != Status) {
goto done;
}
break;
case PM_SHUTDOWN_SUBTYPE_RST_PS_ONLY:
/* TODO */
break;
case PM_SHUTDOWN_SUBTYPE_RST_SYSTEM:
Status = XPmReset_SystemReset();
break;
default:
Status = XPM_INVALID_TYPEID;
break;
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function can be used by a subsystem to to set wake up
* source
*
* @param SubsystemId Initiator of the request
* @param TargetNodeId Core to be woken-up (currently must be same as initiator)
* @param SourceNodeId Source of the wake-up (Device that generates interrupt)
* @param Enable Flag stating should event be enabled or disabled
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note This function does not block. A successful return code means that
* the request has been received.
*
****************************************************************************/
XStatus XPm_SetWakeUpSource(const u32 SubsystemId, const u32 TargetNodeId,
const u32 SourceNodeId, const u32 Enable)
{
int Status = XST_FAILURE;
XPm_Periph *Periph = NULL;
XPm_Subsystem *Subsystem;
/* Check if given target node is valid */
if(NODECLASS(TargetNodeId) != (u32)XPM_NODECLASS_DEVICE ||
NODESUBCLASS(TargetNodeId) != (u32)XPM_NODESUBCL_DEV_CORE)
{
Status = XST_INVALID_PARAM;
goto done;
}
/* The call applies only to peripheral nodes */
if (NODECLASS(SourceNodeId) != (u32)XPM_NODECLASS_DEVICE ||
NODESUBCLASS(SourceNodeId) != (u32)XPM_NODESUBCL_DEV_PERIPH) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Is subsystem allowed to use resource (slave)? */
Status = XPm_IsAccessAllowed(SubsystemId, SourceNodeId);
if (XST_SUCCESS != Status) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Periph = (XPm_Periph *)XPmDevice_GetById(SourceNodeId);
Subsystem = XPmSubsystem_GetById(SubsystemId);
if((NULL == Periph) || (NULL == Subsystem)) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Check whether the device has wake-up capability */
Status = XPm_CheckCapabilities(&Periph->Device, (u32)PM_CAP_WAKEUP);
if (XST_SUCCESS != Status) {
Status = XST_NO_FEATURE;
goto done;
}
Periph->WakeProcId = TargetNodeId;
if (NULL != Periph->PeriphOps->SetWakeupSource) {
Periph->PeriphOps->SetWakeupSource(Periph, Enable);
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief Request the usage of a device. A subsystem requests access to a
* device and asserts its requirements on that device. The platform
* management controller will enable access to the memory mapped region
* containing the control registers of that device. For devices that can only
* be used by one subsystem, any other subsystems will now be blocked from
* accessing this device until it is released.
*
* @param SubsystemId Target subsystem ID (can be the same subsystem)
* @param Device ID of the device
* @param Capabilities Capability requirements (1-hot)
* @param QoS Quality of Service (0-100) required
* @param Ack Ack request
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_RequestDevice(const u32 SubsystemId, const u32 DeviceId,
const u32 Capabilities, const u32 QoS, const u32 Ack)
{
XStatus Status = XST_FAILURE;
/* Warning Fix */
(void) (Ack);
Status = XPmDevice_Request(SubsystemId, DeviceId, Capabilities,
QoS);
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function is used by a subsystem to release the usage of a
* device. This will tell the platform management controller that the device
* is no longer needed, allowing the device to be placed into an inactive
* state.
*
* @param SubsystemId Subsystem ID
* @param DeviceId ID of the device.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_ReleaseDevice(const u32 SubsystemId, const u32 DeviceId)
{
XStatus Status = XST_FAILURE;
XPm_Subsystem* Subsystem = NULL;
XPm_Device* Device = NULL;
u32 Usage = 0U;
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
goto done;
}
Device = XPmDevice_GetById(DeviceId);
if (NULL == Device) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
Status = XPm_IsAccessAllowed(SubsystemId, DeviceId);
if (XST_SUCCESS != Status) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Status = XPmDevice_Release(SubsystemId, DeviceId);
if (XST_SUCCESS != Status) {
goto done;
}
Usage = XPmDevice_GetUsageStatus(Subsystem, Device);
if (0U == Usage) {
XPmNotifier_Event(Device->Node.Id, (u32)EVENT_ZERO_USERS);
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function is used by a subsystem to announce a change in
* requirements for a specific device which is currently in use.
*
* @param SubsystemId Subsystem ID.
* @param DeviceId ID of the device.
* @param Capabilities Capabilities required
* @param QoS Quality of Service (0-100) required.
* @param Ack Ack request
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note If this function is called after the last awake CPU within the
* subsystem calls RequestSuspend, the requirement change shall be performed
* after the CPU signals the end of suspend to the platform management
* controller, (e.g. WFI interrupt).
*
****************************************************************************/
XStatus XPm_SetRequirement(const u32 SubsystemId, const u32 DeviceId,
const u32 Capabilities, const u32 QoS, const u32 Ack)
{
XStatus Status = XST_FAILURE;
/* Warning Fix */
(void) (Ack);
Status = XPm_IsAccessAllowed(SubsystemId, DeviceId);
if (XST_SUCCESS != Status) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Status = XPmDevice_SetRequirement(SubsystemId, DeviceId,
Capabilities, QoS);
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief Set maximum allowed latency for the device
*
* @param SubsystemId Initiator of the request who must previously requested
* the device
* @param DeviceId Device whose latency is specified
* @param Latency Maximum allowed latency in micro sec
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code or
* a reason code
*
****************************************************************************/
int XPm_SetMaxLatency(const u32 SubsystemId, const u32 DeviceId,
const u32 Latency)
{
int Status = XPM_ERR_SET_LATENCY;
PmInfo("(%x, %lu)\r\n", DeviceId, Latency);
Status = XPm_IsAccessAllowed(SubsystemId, DeviceId);
if (XST_SUCCESS != Status) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Status = XPmDevice_SetMaxLatency(SubsystemId, DeviceId, Latency);
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to obtain information about the current state
* of a device. The caller must pass a pointer to an XPm_DeviceStatus
* structure, which must be pre-allocated by the caller.
*
* @param SubsystemId Subsystem ID.
* @param DeviceId Device ID
* @param DeviceStatus Pointer to the device status
*
* - Status - The current power state of the device
* - For CPU nodes:
* - 0 : if CPU is powered down,
* - 1 : if CPU is active (powered up),
* - 2 : if CPU is suspending (powered up)
* - For power islands and power domains:
* - 0 : if island is powered down,
* - 1 : if island is powered up
* - For slaves:
* - 0 : if slave is powered down,
* - 1 : if slave is powered up,
* - 2 : if slave is in retention
*
* - Requirement - Requirements placed on the device by the caller
*
* - Usage
* - 0 : node is not used by any PU,
* - 1 : node is used by caller exclusively,
* - 2 : node is used by other PU(s) only,
* - 3 : node is used by caller and by other PU(s)
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_GetDeviceStatus(const u32 SubsystemId,
const u32 DeviceId,
XPm_DeviceStatus *const DeviceStatus)
{
XStatus Status = XPM_ERR_DEVICE_STATUS;
switch(NODECLASS(DeviceId)) {
case (u32)XPM_NODECLASS_DEVICE:
Status = XPmDevice_GetStatus(SubsystemId, DeviceId, DeviceStatus);
break;
case (u32)XPM_NODECLASS_POWER:
Status = XPmPower_GetStatus(SubsystemId, DeviceId, DeviceStatus);
break;
case (u32)XPM_NODECLASS_SUBSYSTEM:
Status = XPmSubsystem_GetStatus(SubsystemId, DeviceId,
DeviceStatus);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
return Status;
}
/****************************************************************************/
/**
* @brief This function queries information about the platform resources.
*
* @param Qid The type of data to query
* @param Arg1 Query argument 1
* @param Arg2 Query argument 2
* @param Arg3 Query argument 3
* @param Output Pointer to the output data
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
****************************************************************************/
XStatus XPm_Query(const u32 Qid, const u32 Arg1, const u32 Arg2,
const u32 Arg3, u32 *const Output)
{
XStatus Status = XST_FAILURE;
/* Warning Fix */
(void) (Arg3);
switch (Qid) {
case (u32)XPM_QID_CLOCK_GET_NAME:
Status = XPmClock_QueryName(Arg1,Output);
break;
case (u32)XPM_QID_CLOCK_GET_TOPOLOGY:
Status = XPmClock_QueryTopology(Arg1,Arg2,Output);
break;
case (u32)XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS:
Status = XPmClock_QueryFFParams(Arg1,Output);
break;
case (u32)XPM_QID_CLOCK_GET_MUXSOURCES:
if (ISPLL(Arg1)) {
Status = XPmClockPll_QueryMuxSources(Arg1,Arg2,Output);
} else {
Status = XPmClock_QueryMuxSources(Arg1,Arg2,Output);
}
break;
case (u32)XPM_QID_CLOCK_GET_ATTRIBUTES:
Status = XPmClock_QueryAttributes(Arg1,Output);
break;
case (u32)XPM_QID_PINCTRL_GET_NUM_PINS:
Status = XPmPin_GetNumPins(Output);
break;
case (u32)XPM_QID_PINCTRL_GET_NUM_FUNCTIONS:
Status = XPmPinFunc_GetNumFuncs(Output);
break;
case (u32)XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS:
Status = XPmPinFunc_GetNumFuncGroups(Arg1, Output);
break;
case (u32)XPM_QID_PINCTRL_GET_FUNCTION_NAME:
Status = XPmPinFunc_GetFuncName(Arg1, (char *)Output);
break;
case (u32)XPM_QID_PINCTRL_GET_FUNCTION_GROUPS:
Status = XPmPinFunc_GetFuncGroups(Arg1, Arg2, (u16 *)Output);
break;
case (u32)XPM_QID_PINCTRL_GET_PIN_GROUPS:
Status = XPmPin_GetPinGroups(Arg1, Arg2, (u16 *)Output);
break;
case (u32)XPM_QID_CLOCK_GET_NUM_CLOCKS:
Status = XPmClock_GetNumClocks(Output);
break;
case (u32)XPM_QID_CLOCK_GET_MAX_DIVISOR:
Status = XPmClock_GetMaxDivisor(Arg1, Arg2, Output);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
return Status;
}
/****************************************************************************/
/**
* @brief This function enables or disables the clock.
*
* @param SubsystemId Subsystem ID
* @param ClockId ID of the clock node
* @param Enable Enable (1) or disable (0)
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note To enable a clock, the subsystem must be using the clock. To
* disable a clock, the subsystem must be the only user of the clock, and the
* clock must not have any downstream clock(s) that are enabled. Otherwise,
* this request will be denied.
*
****************************************************************************/
XStatus XPm_SetClockState(const u32 SubsystemId, const u32 ClockId, const u32 Enable)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk = XPmClock_GetById(ClockId);
u32 CurrState = 0U;
/* HACK: Don't disable PLL clocks for now */
if(Enable == 0U && ISPLL(ClockId))
{
Status = XST_SUCCESS;
return Status;
}
/* Check if clock's state is already desired state */
Status = XPm_GetClockState(ClockId, &CurrState);
if ((XST_SUCCESS == Status) && (CurrState == Enable)) {
goto done;
}
/* HACK: Allow enabling of PLLs for now */
if ((1U == Enable) && (ISPLL(ClockId))) {
goto bypass;
}
/* Check if subsystem is allowed to access requested clock or not */
Status = XPm_IsAccessAllowed(SubsystemId, ClockId);
if (Status != XST_SUCCESS) {
goto done;
}
bypass:
if (ISOUTCLK(ClockId)) {
Status = XPmClock_SetGate((XPm_OutClockNode *)Clk, Enable);
} else if (ISPLL(ClockId)) {
u32 Mode;
if (1U == Enable) {
Mode = ((XPm_PllClockNode *)Clk)->PllMode;
} else if (0U == Enable) {
Mode = (u32)PM_PLL_MODE_RESET;
} else {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmClockPll_SetMode((XPm_PllClockNode *)Clk, Mode);
} else {
Status = XST_INVALID_PARAM;
goto done;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function reads the clock state.
*
* @param ClockId ID of the clock node
* @param State Pointer to the clock state
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_GetClockState(const u32 ClockId, u32 *const State)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk;
Clk = XPmClock_GetById(ClockId);
if (NULL == Clk) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
if (ISOUTCLK(ClockId)) {
Status = XPmClock_GetClockData((XPm_OutClockNode *)Clk,
(u32)TYPE_GATE, State);
} else if (ISPLL(ClockId)) {
Status = XPmClockPll_GetMode((XPm_PllClockNode *)Clk, State);
if (*State == (u32)PM_PLL_MODE_RESET) {
*State = 0;
} else {
*State = 1;
}
} else {
Status = XST_INVALID_PARAM;
goto done;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function sets the divider value of the clock.
*
* @param SubsystemId Subsystem ID.
* @param ClockId Clock node ID
* @param Divider Divider value
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note To change the clock divider, the clock must be disabled. Otherwise,
* this request will be denied.
*
****************************************************************************/
XStatus XPm_SetClockDivider(const u32 SubsystemId, const u32 ClockId, const u32 Divider)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk = XPmClock_GetById(ClockId);
if (0U == Divider) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Check if subsystem is allowed to access requested clock or not */
Status = XPm_IsAccessAllowed(SubsystemId, ClockId);
if (Status != XST_SUCCESS) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
if (ISOUTCLK(ClockId)) {
Status = XPmClock_SetDivider((XPm_OutClockNode *)Clk, Divider);
} else if (ISPLL(ClockId)) {
Status = XPmClockPll_SetParam((XPm_PllClockNode *)Clk,
(u32)PM_PLL_PARAM_ID_FBDIV, Divider);
} else {
Status = XPM_INVALID_CLKID;
goto done;
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function reads the clock divider.
*
* @param ClockId ID of the clock node
* @param Divider Address to store the divider values
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_GetClockDivider(const u32 ClockId, u32 *const Divider)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk = XPmClock_GetById(ClockId);
if (ISOUTCLK(ClockId)) {
Status = XPmClock_GetClockData((XPm_OutClockNode *)Clk,
(u32)TYPE_DIV1, Divider);
} else if (ISPLL(ClockId)) {
Status = XPmClockPll_GetParam((XPm_PllClockNode *)Clk,
(u32)PM_PLL_PARAM_ID_FBDIV, Divider);
} else {
Status = XPM_INVALID_CLKID;
goto done;
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function sets the parent of the clock.
*
* @param SubsystemId Subsystem ID.
* @param ClockId Clock node ID
* @param ParentIdx Parent clock index
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note To change the clock parent, the clock must be disabled. Otherwise,
* this request will be denied.
*
****************************************************************************/
XStatus XPm_SetClockParent(const u32 SubsystemId, const u32 ClockId, const u32 ParentIdx)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk = XPmClock_GetById(ClockId);
/* Check if subsystem is allowed to access requested clock or not */
Status = XPm_IsAccessAllowed(SubsystemId, ClockId);
if (Status != XST_SUCCESS) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
/* Set parent is allowed only on output clocks */
if (!ISOUTCLK(ClockId)) {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmClock_SetParent((XPm_OutClockNode *)Clk, ParentIdx);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function reads the clock parent.
*
* @param ClockId ID of the clock node
* @param ParentIdx Address to store the parent clock index
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_GetClockParent(const u32 ClockId, u32 *const ParentIdx)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk = XPmClock_GetById(ClockId);
/* Get parent is allowed only on output clocks */
if (!ISOUTCLK(ClockId)) {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmClock_GetClockData((XPm_OutClockNode *)Clk, (u32)TYPE_MUX, ParentIdx);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function sets the parameter of PLL clock.
*
* @param SubsystemId Subsystem ID
* @param ClockId ID of the clock node
* @param ParmaId ID of the parameter
* @param Value Value of the parameter
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_SetPllParameter(const u32 SubsystemId, const u32 ClockId, const u32 ParamId, const u32 Value)
{
XStatus Status = XST_FAILURE;
XPm_PllClockNode* Clock;
if (!ISPLL(ClockId)) {
Status = XPM_INVALID_CLKID;
goto done;
}
/* Check if subsystem is allowed to access requested clock or not */
Status = XPm_IsAccessAllowed(SubsystemId, ClockId);
if (Status != XST_SUCCESS) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Clock = (XPm_PllClockNode *)XPmClock_GetById(ClockId);
if (NULL == Clock) {
Status = XPM_INVALID_CLKID;
goto done;
}
Status = XPmClockPll_SetParam(Clock, ParamId, Value);
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%xn\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function reads the parameter of PLL clock.
*
* @param ClockId ID of the clock node
* @param ParmaId ID of the parameter
* @param Value Address to store parameter value
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_GetPllParameter(const u32 ClockId, const u32 ParamId, u32 *const Value)
{
XStatus Status = XST_FAILURE;
XPm_PllClockNode* Clock;
if (!ISPLL(ClockId)) {
Status = XPM_INVALID_CLKID;
goto done;
}
Clock = (XPm_PllClockNode *)XPmClock_GetById(ClockId);
if (NULL == Clock) {
Status = XPM_INVALID_CLKID;
goto done;
}
Status = XPmClockPll_GetParam(Clock, ParamId, Value);
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function sets the mode of PLL clock.
*
* @param SubsystemId Subsystem ID
* @param ClockId ID of the clock node
* @param Value Pll mode value
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_SetPllMode(const u32 SubsystemId, const u32 ClockId, const u32 Value)
{
XStatus Status = XST_FAILURE;
XPm_PllClockNode* Clock;
if (!ISPLL(ClockId)) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Check if subsystem is allowed to access requested pll or not */
Status = XPm_IsAccessAllowed(SubsystemId, ClockId);
if (Status != XST_SUCCESS) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Clock = (XPm_PllClockNode *)XPmClock_GetById(ClockId);
if (NULL == Clock) {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmClockPll_SetMode(Clock, Value);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function reads the mode of PLL clock.
*
* @param ClockId ID of the clock node
* @param Value Address to store mode value
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_GetPllMode(const u32 ClockId, u32 *const Value)
{
XStatus Status = XST_FAILURE;
XPm_PllClockNode* Clock;
if (!ISPLL(ClockId)) {
Status = XST_INVALID_PARAM;
goto done;
}
Clock = (XPm_PllClockNode *)XPmClock_GetById(ClockId);
if (NULL == Clock) {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmClockPll_GetMode(Clock, Value);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function reset or de-reset a device.
*
* @param SubsystemId Subsystem ID
* @param ResetId Reset ID
* @param IpiMask IPI Mask currently being used
* @param Action Reset (true) or de-reset (false) the device
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note To de-reset a device, the subsystem must be using the device, and
* all the upstream reset line(s) must be de-asserted. To reset a device, the
* subsystem must be the only user of the device, and all downstream devices
* (in terms of reset dependency) must be already in reset state. Otherwise,
* this request will be denied.
*
****************************************************************************/
XStatus XPm_SetResetState(const u32 SubsystemId, const u32 IpiMask,
const u32 ResetId, const u32 Action)
{
int Status = XST_FAILURE;
XPm_ResetNode* Reset;
u32 SubClass = NODESUBCLASS(ResetId);
u32 SubType = NODETYPE(ResetId);
Reset = XPmReset_GetById(ResetId);
if (NULL == Reset) {
Status = XST_INVALID_PARAM;
goto done;
}
/*
* XSDB is a privileged master, allow unrestricted access.
*/
if (XSDB_IPI_INT_MASK != IpiMask) {
/*
* Only peripheral and debug resets
* are allowed to control externally, on other masters.
*/
if ((u32)XPM_NODESUBCL_RESET_PERIPHERAL == SubClass) {
if ((u32)XPM_NODETYPE_RESET_PERIPHERAL != SubType) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
} else if ((u32)XPM_NODESUBCL_RESET_DBG == SubClass) {
if ((u32)XPM_NODETYPE_RESET_DBG != SubType) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
} else {
Status = XPM_PM_NO_ACCESS;
goto done;
}
/* Check if subsystem is allowed to access requested reset */
Status = XPm_IsAccessAllowed(SubsystemId, ResetId);
if (XST_SUCCESS != Status) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
}
Status = Reset->Ops->SetState(Reset, Action);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function reads the device reset state.
*
* @param ResetId Reset ID
* @param State Pointer to the reset state
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_GetResetState(const u32 ResetId, u32 *const State)
{
int Status = XST_FAILURE;
XPm_ResetNode* Reset;
Reset = XPmReset_GetById(ResetId);
if (NULL == Reset) {
Status = XST_INVALID_PARAM;
goto done;
}
*State = Reset->Ops->GetState(Reset);
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function requests the pin.
*
* @param SubsystemId Subsystem ID
* @param PinId ID of the pin node
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_PinCtrlRequest(const u32 SubsystemId, const u32 PinId)
{
XStatus Status = XST_FAILURE;
Status = XPmPin_Request(SubsystemId, PinId);
return Status;
}
/****************************************************************************/
/**
* @brief This function releases the pin.
*
* @param SubsystemId Subsystem ID
* @param PinId ID of the pin node
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_PinCtrlRelease(const u32 SubsystemId, const u32 PinId)
{
XStatus Status = XST_FAILURE;
Status = XPmPin_Release(SubsystemId, PinId);
return Status;
}
/****************************************************************************/
/**
* @brief This function sets the pin function.
*
* @param SubsystemId Subsystem ID
* @param PinId Pin node ID
* @param FunctionId Function for the pin
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note If no change to the pin function setting is required (the pin is
* already set up for this function), this call will be successful.
* Otherwise, the request is denied unless the subsystem has already
* requested this pin.
*
****************************************************************************/
XStatus XPm_SetPinFunction(const u32 SubsystemId,
const u32 PinId, const u32 FunctionId)
{
XStatus Status = XST_FAILURE;
/* Check if subsystem is allowed to access or not */
Status = XPm_IsAccessAllowed(SubsystemId, PinId);
if(Status != XST_SUCCESS) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Status = XPmPin_CheckPerms(SubsystemId, PinId);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPin_SetPinFunction(PinId, FunctionId);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function reads the pin function.
*
* @param PinId ID of the pin node
* @param FunctionId Address to store the function
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_GetPinFunction(const u32 PinId, u32 *const FunctionId)
{
XStatus Status = XST_FAILURE;
Status = XPmPin_GetPinFunction(PinId, FunctionId);
return Status;
}
/****************************************************************************/
/**
* @brief This function sets the pin parameter value.
*
* @param SubsystemId Subsystem ID
* @param PinId Pin node ID
* @param ParamId Pin parameter ID
* @param ParamVal Pin parameter value
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note If no change to the pin parameter setting is required (the pin
* parameter is already set up for this value), this call will be successful.
* Otherwise, the request is denied unless the subsystem has already
* requested this pin.
*
****************************************************************************/
XStatus XPm_SetPinParameter(const u32 SubsystemId, const u32 PinId,
const u32 ParamId,
const u32 ParamVal)
{
XStatus Status = XST_FAILURE;
/* Check if subsystem is allowed to access or not */
Status = XPm_IsAccessAllowed(SubsystemId, PinId);
if(Status != XST_SUCCESS) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Status = XPmPin_CheckPerms(SubsystemId, PinId);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPin_SetPinConfig(PinId, ParamId, ParamVal);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function reads the pin parameter value.
*
* @param PinId ID of the pin node
* @param ParamId Pin parameter ID
* @param ParamVal Address to store the pin parameter value
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_GetPinParameter(const u32 PinId,
const u32 ParamId,
u32 * const ParamVal)
{
XStatus Status = XST_FAILURE;
Status = XPmPin_GetPinConfig(PinId, ParamId, ParamVal);
return Status;
}
/****************************************************************************/
/**
* @brief Enable/Disable tap delay bypass
*
* @param DeviceId ID of the device
* @param Type Type of tap delay to enable/disable (QSPI)
* @param Value Enable/Disable
*
* @return XST_SUCCESS if successful else error code or a reason code
*
****************************************************************************/
static int XPm_SetTapdelayBypass(const u32 DeviceId, const u32 Type,
const u32 Value)
{
int Status = XST_FAILURE;
XPm_Device *Device = XPmDevice_GetById(DeviceId);
u32 BaseAddress;
if (NULL == Device) {
Status = XPM_INVALID_DEVICEID;
goto done;
}
/* QSPI base address */
BaseAddress = Device->Node.BaseAddress;
if (((XPM_TAPDELAY_BYPASS_ENABLE != Value) &&
(XPM_TAPDELAY_BYPASS_DISABLE != Value)) ||
(XPM_TAPDELAY_QSPI != Type)) {
Status = XST_INVALID_PARAM;
goto done;
}
PmRmw32(BaseAddress + TAPDLY_BYPASS_OFFSET, XPM_TAP_DELAY_MASK,
Value << Type);
Status = XST_SUCCESS;
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function resets DLL logic for the SD device.
*
* @param DeviceId DeviceId of the device
* @param Type Reset type
*
* @return XST_SUCCESS if successful else error code or a reason code
*
****************************************************************************/
static int XPm_SdDllReset(const u32 DeviceId, const u32 Type)
{
int Status = XST_FAILURE;
XPm_Pmc *Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
u32 BaseAddress;
u32 Offset;
if (NULL == Pmc) {
Status = XPM_INVALID_DEVICEID;
goto done;
}
/* PMC_IOU_SLCR base address */
BaseAddress = Pmc->PmcIouSlcrBaseAddr;
if (PM_DEV_SDIO_0 == DeviceId) {
Offset = SD0_CTRL_OFFSET;
} else if (PM_DEV_SDIO_1 == DeviceId) {
Offset = SD1_CTRL_OFFSET;
} else {
Status = XPM_INVALID_DEVICEID;
goto done;
}
switch (Type) {
case XPM_DLL_RESET_ASSERT:
PmRmw32(BaseAddress + Offset, XPM_SD_DLL_RST_MASK,
XPM_SD_DLL_RST_MASK);
Status = XST_SUCCESS;
break;
case XPM_DLL_RESET_RELEASE:
PmRmw32(BaseAddress + Offset, XPM_SD_DLL_RST_MASK,
~XPM_SD_DLL_RST_MASK);
Status = XST_SUCCESS;
break;
case XPM_DLL_RESET_PULSE:
PmRmw32(BaseAddress + Offset, XPM_SD_DLL_RST_MASK,
XPM_SD_DLL_RST_MASK);
PmRmw32(BaseAddress + Offset, XPM_SD_DLL_RST_MASK,
~XPM_SD_DLL_RST_MASK);
Status = XST_SUCCESS;
break;
default:
Status = XPM_INVALID_TYPEID;
break;
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function sets input/output tap delay for the SD device.
*
* @param DeviceId DeviceId of the device
* @param Type Type of tap delay to set (input/output)
* @param Value Value to set for the tap delay
*
* @return XST_SUCCESS if successful else error code or a reason code
*
****************************************************************************/
static int XPm_SetSdTapDelay(const u32 DeviceId, const u32 Type,
const u32 Value)
{
int Status = XST_FAILURE;
XPm_Device *Device = XPmDevice_GetById(DeviceId);
u32 BaseAddress;
if (NULL == Device) {
Status = XPM_INVALID_DEVICEID;
goto done;
}
/*Check for Type */
if (XPM_TAPDELAY_INPUT != Type && XPM_TAPDELAY_OUTPUT != Type) {
Status = XPM_INVALID_TYPEID;
goto done;
}
/* SD0/1 base address */
BaseAddress = Device->Node.BaseAddress;
Status = XPm_SdDllReset(DeviceId, XPM_DLL_RESET_ASSERT);
if (XST_SUCCESS != Status) {
goto done;
}
switch (Type) {
case XPM_TAPDELAY_INPUT:
PmRmw32(BaseAddress + ITAPDLY_OFFSET, XPM_SD_ITAPCHGWIN_MASK,
XPM_SD_ITAPCHGWIN_MASK);
PmRmw32(BaseAddress + ITAPDLY_OFFSET, XPM_SD_ITAPDLYENA_MASK,
XPM_SD_ITAPDLYENA_MASK);
PmRmw32(BaseAddress + ITAPDLY_OFFSET, XPM_SD_ITAPDLYSEL_MASK,
Value);
PmRmw32(BaseAddress + ITAPDLY_OFFSET, XPM_SD_ITAPCHGWIN_MASK,
~XPM_SD_ITAPCHGWIN_MASK);
break;
case XPM_TAPDELAY_OUTPUT:
PmRmw32(BaseAddress + OTAPDLY_OFFSET, XPM_SD_OTAPDLYENA_MASK,
XPM_SD_OTAPDLYENA_MASK);
PmRmw32(BaseAddress + OTAPDLY_OFFSET, XPM_SD_OTAPDLYSEL_MASK,
Value);
break;
default:
/*No action taken because we check for type earlier in the function
* but present as part of defensive programming in case we reach here */
break;
}
Status = XPm_SdDllReset(DeviceId, XPM_DLL_RESET_RELEASE);
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function performs read/write operation on probe counter
* registers of LPD/FPD.
*
* @param DeviceId DeviceId of the LPD/FPD
* @param Arg1 - Counter Number (0 to 7 bit)
* - Register Type (8 to 15 bit)
* 0 - LAR_LSR access (Request Type is ignored and
* Counter Number is ignored)
* 1 - Main Ctl (Counter Number is ignored)
* 2 - Config Ctl (Counter Number is ignored)
* 3 - State Period (Counter Number is ignored)
* 4 - PortSel
* 5 - Src
* 6 - Val
* - Request Type (16 to 23 bit)
* 0 - Read Request
* 1 - Read Response
* 2 - Write Request
* 3 - Write Response
* 4 - lpd Read Request (For LPD only)
* 5 - lpd Read Response (For LPD only)
* 6 - lpd Write Request (For LPD only)
* 7 - lpd Write Response (For LPD only)
* @param Value Register value to write (if Write flag is 1)
* @param Response Value of register read (if Write flag is 0)
* @param Write Operation type (0 - Read, 1 - Write)
*
* @return XST_SUCCESS if successful else error code or a reason code
*
****************************************************************************/
static int XPm_ProbeCounterAccess(u32 DeviceId, u32 Arg1, u32 Value,
u32 *const Response, u8 Write)
{
int Status = XST_INVALID_PARAM;
XPm_Power *Power;
u32 Reg;
u32 CounterIdx;
u32 ReqType;
u32 ReqTypeOffset;
u32 FpdReqTypeOffset[] = {
PROBE_COUNTER_FPD_RD_REQ_OFFSET,
PROBE_COUNTER_FPD_RD_RES_OFFSET,
PROBE_COUNTER_FPD_WR_REQ_OFFSET,
PROBE_COUNTER_FPD_WR_RES_OFFSET,
};
CounterIdx = Arg1 & PROBE_COUNTER_IDX_MASK;
ReqType = ((Arg1 >> PROBE_COUNTER_REQ_TYPE_SHIFT) &
PROBE_COUNTER_REQ_TYPE_MASK);
switch (NODEINDEX(DeviceId)) {
case (u32)XPM_NODEIDX_POWER_LPD:
if (CounterIdx > PROBE_COUNTER_CPU_R5_MAX_IDX) {
goto done;
}
if (ReqType > PROBE_COUNTER_LPD_MAX_REQ_TYPE) {
goto done;
} else if ((ReqType > PROBE_COUNTER_CPU_R5_MAX_REQ_TYPE) &&
(CounterIdx > PROBE_COUNTER_LPD_MAX_IDX)) {
goto done;
} else {
/* Required due to MISRA */
PmDbg("[%d] Unknown else case\r\n", __LINE__);
}
Reg = CORESIGHT_LPD_ATM_BASE;
ReqTypeOffset = (ReqType * PROBE_COUNTER_LPD_REQ_TYPE_OFFSET);
Status = XST_SUCCESS;
break;
case (u32)XPM_NODEIDX_POWER_FPD:
if (CounterIdx > PROBE_COUNTER_FPD_MAX_IDX) {
goto done;
}
if (ReqType > PROBE_COUNTER_FPD_MAX_REQ_TYPE) {
goto done;
}
Reg = CORESIGHT_FPD_ATM_BASE;
ReqTypeOffset = FpdReqTypeOffset[ReqType];
Status = XST_SUCCESS;
break;
default:
Status = XPM_PM_INVALID_NODE;
break;
}
if (XST_SUCCESS != Status) {
goto done;
}
Power = XPmPower_GetById(DeviceId);
if ((NULL == Power) || ((u8)XPM_POWER_STATE_ON != Power->Node.State)) {
goto done;
}
switch ((Arg1 >> PROBE_COUNTER_TYPE_SHIFT) & PROBE_COUNTER_TYPE_MASK) {
case XPM_PROBE_COUNTER_TYPE_LAR_LSR:
if (1U == Write) {
Reg += PROBE_COUNTER_LAR_OFFSET;
} else {
Reg += PROBE_COUNTER_LSR_OFFSET;
}
Status = XST_SUCCESS;
break;
case XPM_PROBE_COUNTER_TYPE_MAIN_CTL:
Reg += ReqTypeOffset + PROBE_COUNTER_MAIN_CTL_OFFSET;
Status = XST_SUCCESS;
break;
case XPM_PROBE_COUNTER_TYPE_CFG_CTL:
Reg += ReqTypeOffset + PROBE_COUNTER_CFG_CTL_OFFSET;
Status = XST_SUCCESS;
break;
case XPM_PROBE_COUNTER_TYPE_STATE_PERIOD:
Reg += ReqTypeOffset + PROBE_COUNTER_STATE_PERIOD_OFFSET;
Status = XST_SUCCESS;
break;
case XPM_PROBE_COUNTER_TYPE_PORT_SEL:
Reg += (ReqTypeOffset + (CounterIdx * 20U) +
PROBE_COUNTER_PORT_SEL_OFFSET);
Status = XST_SUCCESS;
break;
case XPM_PROBE_COUNTER_TYPE_SRC:
Reg += (ReqTypeOffset + (CounterIdx * 20U) +
PROBE_COUNTER_SRC_OFFSET);
Status = XST_SUCCESS;
break;
case XPM_PROBE_COUNTER_TYPE_VAL:
if (1U == Write) {
/* This type doesn't support write operation */
goto done;
}
Reg += (ReqTypeOffset + (CounterIdx * 20U) +
PROBE_COUNTER_VAL_OFFSET);
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
if (XST_SUCCESS != Status) {
goto done;
}
if (0U == Write) {
if (NULL == Response) {
Status = XST_FAILURE;
goto done;
}
PmIn32(Reg, *Response);
} else {
PmOut32(Reg, Value);
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function sets the controller into either D3 or D0 state
*
* @param DeviceId DeviceId of the device
* @param ReqState Requested State (0 - D0, 3 - D3)
* @param TimeOut TimeOut value in micro secs to wait for D3/D0 entry
*
* @return XST_SUCCESS if successful else error code
*
****************************************************************************/
static int XPm_USBDxState(const u32 DeviceId, const u32 ReqState,
const u32 TimeOut)
{
int Status = XST_FAILURE;
XPm_Pmc *Pmc;
u32 BaseAddress;
u32 Offset;
u32 CurState;
u32 LocalTimeOut;
(void)DeviceId;
LocalTimeOut = TimeOut;
Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
if (NULL == Pmc) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
/* Only (D0 == 0U) or (D3 == 3U) states allowed */
if ((ReqState != 0U) && (ReqState != 3U)) {
Status = XST_INVALID_PARAM;
goto done;
}
/* PMC_IOU_SLCR base address */
BaseAddress = Pmc->PmcIouSlcrBaseAddr;;
/* power state request */
Offset = XPM_USB_PWR_REQ_OFFSET;
PmOut32(BaseAddress + Offset, ReqState);
/* current power state */
Offset = XPM_USB_CUR_PWR_OFFSET;
PmIn32(BaseAddress + Offset, CurState);
while((CurState != ReqState) && (LocalTimeOut > 0U)) {
LocalTimeOut--;
PmIn32(BaseAddress + Offset, CurState);
usleep(1U);
}
Status = ((LocalTimeOut == 0U) ? XST_FAILURE : XST_SUCCESS);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function selects/returns the AXI interface to OSPI device
*
* @param DeviceId DeviceId of the device
* @param Type Reset type
* @param Response Output Response (0 - DMA, 1 - LINEAR)
*
* @return XST_SUCCESS if successful else error code or a reason code
*
****************************************************************************/
static int XPm_OspiMuxSelect(const u32 DeviceId, const u32 Type, u32 *Response)
{
int Status = XST_FAILURE;
XPm_Pmc *Pmc;
u32 BaseAddress;
u32 Offset;
(void)DeviceId;
Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
if (NULL == Pmc) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
/* PMC_IOU_SLCR base address */
BaseAddress = Pmc->PmcIouSlcrBaseAddr;
Offset = XPM_OSPI_MUX_SEL_OFFSET;
switch (Type) {
case XPM_OSPI_MUX_SEL_DMA:
PmRmw32(BaseAddress + Offset, XPM_OSPI_MUX_SEL_MASK,
~XPM_OSPI_MUX_SEL_MASK);
Status = XST_SUCCESS;
break;
case XPM_OSPI_MUX_SEL_LINEAR:
PmRmw32(BaseAddress + Offset, XPM_OSPI_MUX_SEL_MASK,
XPM_OSPI_MUX_SEL_MASK);
Status = XST_SUCCESS;
break;
case XPM_OSPI_MUX_GET_MODE:
if (NULL == Response) {
Status = XST_INVALID_PARAM;
goto done;
}
PmIn32(BaseAddress + Offset, *Response);
*Response = (((*Response) & XPM_OSPI_MUX_SEL_MASK) >>
XPM_OSPI_MUX_SEL_SHIFT);
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function performs driver-like IOCTL functions on shared system
* devices.
*
* @param SubsystemId ID of the subsystem
* @param DeviceId ID of the device
* @param IoctlId IOCTL function ID
* @param Arg1 Argument 1
* @param Arg2 Argument 2
* @param Response Ioctl response
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note If no change to the pin parameter setting is required (the pin
* parameter is already set up for this value), this call will be successful.
* Otherwise, the request is denied unless the subsystem has already
* requested this pin.
*
****************************************************************************/
XStatus XPm_DevIoctl(const u32 SubsystemId, const u32 DeviceId,
const u32 IoctlId,
const u32 Arg1,
const u32 Arg2, u32 *const Response)
{
XStatus Status = XPM_ERR_IOCTL;
switch (IoctlId) {
case (u32)IOCTL_GET_RPU_OPER_MODE:
if ((DeviceId != PM_DEV_RPU0_0) &&
(DeviceId != PM_DEV_RPU0_1)) {
Status = XPM_INVALID_DEVICEID;
goto done;
}
XPm_RpuGetOperMode(DeviceId, Response);
Status = XST_SUCCESS;
break;
case (u32)IOCTL_SET_RPU_OPER_MODE:
if ((DeviceId != PM_DEV_RPU0_0) &&
(DeviceId != PM_DEV_RPU0_1)) {
Status = XPM_INVALID_DEVICEID;
goto done;
}
XPm_RpuSetOperMode(DeviceId, Arg1);
Status = XST_SUCCESS;
break;
case (u32)IOCTL_RPU_BOOT_ADDR_CONFIG:
if ((PM_DEV_RPU0_0 != DeviceId) &&
(PM_DEV_RPU0_1 != DeviceId)) {
goto done;
}
Status = XPm_RpuBootAddrConfig(DeviceId, Arg1);
break;
case (u32)IOCTL_TCM_COMB_CONFIG:
if ((PM_DEV_RPU0_0 != DeviceId) &&
(PM_DEV_RPU0_1 != DeviceId)) {
Status = XPM_INVALID_DEVICEID;
goto done;
}
Status = XPm_RpuTcmCombConfig(DeviceId, Arg1);
break;
case (u32)IOCTL_SET_TAPDELAY_BYPASS:
if (PM_DEV_QSPI != DeviceId) {
Status = XPM_INVALID_DEVICEID;
goto done;
}
Status = XPm_IsAccessAllowed(SubsystemId, DeviceId);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_SetTapdelayBypass(DeviceId, Arg1, Arg2);
break;
case (u32)IOCTL_SD_DLL_RESET:
Status = XPm_IsAccessAllowed(SubsystemId, DeviceId);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_SdDllReset(DeviceId, Arg1);
break;
case (u32)IOCTL_SET_SD_TAPDELAY:
Status = XPm_IsAccessAllowed(SubsystemId, DeviceId);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_SetSdTapDelay(DeviceId, Arg1, Arg2);
break;
case (u32)IOCTL_WRITE_GGS:
if (Arg1 >= GGS_NUM_REGS) {
goto done;
}
PmOut32((GGS_BASEADDR + (Arg1 << 2)), Arg2);
Status = XST_SUCCESS;
break;
case (u32)IOCTL_READ_GGS:
if (Arg1 >= GGS_NUM_REGS) {
goto done;
}
PmIn32((GGS_BASEADDR + (Arg1 << 2)), *Response);
Status = XST_SUCCESS;
break;
case (u32)IOCTL_WRITE_PGGS:
if (Arg1 >= PGGS_NUM_REGS) {
goto done;
}
PmOut32((PGGS_BASEADDR + (Arg1 << 2)), Arg2);
Status = XST_SUCCESS;
break;
case (u32)IOCTL_READ_PGGS:
if (Arg1 >= PGGS_NUM_REGS) {
goto done;
}
PmIn32((PGGS_BASEADDR + (Arg1 << 2)), *Response);
Status = XST_SUCCESS;
break;
case (u32)IOCTL_SET_BOOT_HEALTH_STATUS:
PmRmw32(GGS_BASEADDR + GGS_4_OFFSET,
XPM_BOOT_HEALTH_STATUS_MASK, Arg1);
Status = XST_SUCCESS;
break;
case (u32)IOCTL_PROBE_COUNTER_READ:
Status = XPm_ProbeCounterAccess(DeviceId, Arg1, Arg2,
Response, 0U);
break;
case (u32)IOCTL_PROBE_COUNTER_WRITE:
Status = XPm_ProbeCounterAccess(DeviceId, Arg1, Arg2,
Response, 1U);
break;
case (u32)IOCTL_OSPI_MUX_SELECT:
if (PM_DEV_OSPI != DeviceId) {
goto done;
}
Status = XPm_IsAccessAllowed(SubsystemId, DeviceId);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_OspiMuxSelect(DeviceId, Arg1, Response);
break;
case (u32)IOCTL_USB_SET_STATE:
if (PM_DEV_USB_0 != DeviceId) {
goto done;
}
Status = XPm_IsAccessAllowed(SubsystemId, DeviceId);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_USBDxState(DeviceId, Arg1, Arg2);
break;
default:
/* Not supported yet */
Status = XPM_ERR_IOCTL;
break;
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief This function initializes subsystem and releases unused devices
*
* @param SubsystemId ID of the subsystem
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
int XPm_InitFinalize(const u32 SubsystemId)
{
return XPmSubsystem_InitFinalize(SubsystemId);
}
/****************************************************************************/
/**
* @brief This function provides topology information
*
* @param Args topology information data
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_DescribeNodes(u32 NumArgs)
{
int Status = XST_FAILURE;
/*u32 NumPwrNodes, NumClkNodes, NumRstNodes, NumMioNodes, NumDevices;*/
if(NumArgs < 3U) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Uncomment when AllocNodes will implement */
/*NumPwrNodes = (Args[0] >> 16) & 0xFFFF;
NumClkNodes = Args[0] & 0xFFFF;
NumRstNodes = (Args[1] >> 16) & 0xFFFF;
NumMioNodes = Args[1] & 0xFFFF;
NumDevices = Args[2] & 0xFFFF;
if(NumClkNodes != 0)
Status = XPmClock_AllocNodes(NumClkNodes);
if(NumPwrNodes != 0)
Status = XPmPower_AllocNodes(NumPwrNodes);
if(NumRstNodes != 0)
Status = XPmReset_AllocNodes(NumRstNodes);
if (NumMioNodes != 0)
Status = XPmMio_AllocNodes(NumMioNodes);
if (NumDevices != 0)
Status = XPmDevice_Alloc(NumDevices);*/
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function allows adding parent to any node or device
*
* @param Args Parent ids
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_AddNodeParent(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 Id = Args[0];
u32 *Parents;
u32 NumParents;
if (NumArgs < 2U) {
Status = XST_INVALID_PARAM;
goto done;
}
NumParents = NumArgs-1U;
Parents = &Args[1];
switch (NODECLASS(Id)) {
case (u32)XPM_NODECLASS_POWER:
Status = XPmPower_AddParent(Id, Parents, NumParents);
break;
case (u32)XPM_NODECLASS_CLOCK:
if (ISPLL(Id)) {
Status = XPmClockPll_AddParent(Id, Parents, (u8)NumParents);
} else {
Status = XPmClock_AddParent(Id, Parents, (u8)NumParents);
}
break;
case (u32)XPM_NODECLASS_RESET:
Status = XST_SUCCESS;
break;
case (u32)XPM_NODECLASS_MEMIC:
Status = XST_SUCCESS;
break;
case (u32)XPM_NODECLASS_STMIC:
Status = XST_SUCCESS;
break;
case (u32)XPM_NODECLASS_DEVICE:
Status = XPmDevice_AddParent(Id, Parents, NumParents);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function adds sub nodes for clocks having custom topology
*
* @param Args topology node arguments
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static XStatus XPm_AddClockSubNode(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 ClockId, ControlReg, Type, Flags;
u8 Param1, Param2;
if (NumArgs < 5U) {
Status = XST_INVALID_PARAM;
goto done;
}
ClockId = Args[0];
if (ISOUTCLK(ClockId)) {
Type = Args[1];
ControlReg = Args[2];
Param1 = (u8)(Args[3] & 0xFFU);
Param2 = (u8)((Args[3] >> 8U) & 0xFFU);
Flags = Args[4];
Status = XPmClock_AddSubNode(ClockId, Type, ControlReg, Param1, Param2, Flags);
} else {
Status = XST_INVALID_PARAM;
goto done;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function add clock node to clock topology database
*
* @param Args clock arguments
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static XStatus XPm_AddNodeClock(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 ClockId, ControlReg;
u32 PowerDomainId;
u8 TopologyType, NumCustomNodes=0, NumParents, ClkFlags;
if (NumArgs < 4U) {
Status = XST_INVALID_PARAM;
goto done;
}
ClockId = Args[0];
if (NODETYPE(ClockId) == (u32)XPM_NODETYPE_CLOCK_SUBNODE) {
Status = XPm_AddClockSubNode(Args, NumArgs);
goto done;
}
if (ISOUTCLK(ClockId) || ISREFCLK(ClockId) || ISPLL(ClockId)) {
ControlReg = Args[1];
TopologyType = (u8)(Args[2] & 0xFFU);
NumCustomNodes = (u8)((Args[2] >> 8U) & 0xFFU);
NumParents = (u8)((Args[2] >> 16U) & 0xFFU);
ClkFlags = (u8)((Args[2] >> 24U) & 0xFFU);
PowerDomainId = Args[3];
if (ISPLL(ClockId)) {
u16 *Offsets = (u16 *)&Args[4];
Status = XPmClockPll_AddNode(ClockId, ControlReg,
TopologyType, Offsets,
PowerDomainId, ClkFlags);
} else {
Status = XPmClock_AddNode(ClockId, ControlReg,
TopologyType, NumCustomNodes,
NumParents, PowerDomainId,
ClkFlags);
}
} else {
Status = XST_INVALID_PARAM;
goto done;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function adds node name
*
* @param Args name
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_AddNodeName(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 NodeId;
char Name[MAX_NAME_BYTES] = {0};
u32 i=0, j=0;
if (NumArgs == 0U) {
Status = XST_INVALID_PARAM;
goto done;
}
NodeId = Args[0];
if (ISOUTCLK(NodeId) || ISREFCLK(NodeId) || ISPLL(NodeId)) {
for (i = 1U; i < NumArgs; i++) {
(void)memcpy(&Name[j], (char *)((UINTPTR)&Args[i]), 4U);
j += 4U;
}
Status = XPmClock_AddClkName(NodeId, Name);
} else {
Status = XST_INVALID_PARAM;
goto done;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function add power node to power topology database
*
* @param Args power arguments
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static XStatus XPm_AddNodePower(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 PowerId;
u32 PowerType;
u8 Width;
u8 Shift;
u32 BitMask;
u32 ParentId;
XPm_Power *Power;
XPm_Power *PowerParent = NULL;
XPm_PsFpDomain *PsFpDomain;
XPm_PmcDomain *PmcDomain;
XPm_PsLpDomain *PsLpDomain;
XPm_NpDomain *NpDomain;
XPm_PlDomain *PlDomain;
XPm_AieDomain *AieDomain;
XPm_CpmDomain *CpmDomain;
if (NumArgs < 3U) {
Status = XST_INVALID_PARAM;
goto done;
}
PowerId = Args[0];
PowerType = NODETYPE(PowerId);
Width = (u8)(Args[1] >> 8) & 0xFFU;
Shift = (u8)(Args[1] & 0xFFU);
ParentId = Args[2];
if (NODECLASS(PowerId) != (u32)XPM_NODECLASS_POWER) {
Status = XST_INVALID_PARAM;
goto done;
} else if (NODEINDEX(PowerId) >= (u32)XPM_NODEIDX_POWER_MAX) {
Status = XST_INVALID_PARAM;
goto done;
} else {
/* Required by MISRA */
}
BitMask = BITNMASK(Shift, Width);
if (ParentId != (u32)XPM_NODEIDX_POWER_MIN) {
if (NODECLASS(ParentId) != (u32)XPM_NODECLASS_POWER) {
Status = XST_INVALID_PARAM;
goto done;
} else if (NODEINDEX(ParentId) >= (u32)XPM_NODEIDX_POWER_MAX) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
} else {
/* Required by MISRA */
}
PowerParent = XPmPower_GetById(ParentId);
if (NULL == PowerParent) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
}
switch (PowerType) {
case (u32)XPM_NODETYPE_POWER_ISLAND:
case (u32)XPM_NODETYPE_POWER_ISLAND_XRAM:
Power = (XPm_Power *)XPm_AllocBytes(sizeof(XPm_Power));
if (NULL == Power) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmPower_Init(Power, PowerId, BitMask,
PowerParent);
break;
case (u32)XPM_NODETYPE_POWER_DOMAIN_PMC:
PmcDomain =
(XPm_PmcDomain *)XPm_AllocBytes(sizeof(XPm_PmcDomain));
if (NULL == PmcDomain) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmPmcDomain_Init((XPm_PmcDomain *)PmcDomain, PowerId);
break;
case (u32)XPM_NODETYPE_POWER_DOMAIN_PS_FULL:
PsFpDomain =
(XPm_PsFpDomain *)XPm_AllocBytes(sizeof(XPm_PsFpDomain));
if (NULL == PsFpDomain) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmPsFpDomain_Init(PsFpDomain, PowerId,
BitMask, PowerParent, &Args[3], (NumArgs - 3U));
break;
case (u32)XPM_NODETYPE_POWER_DOMAIN_PS_LOW:
PsLpDomain =
(XPm_PsLpDomain *)XPm_AllocBytes(sizeof(XPm_PsLpDomain));
if (NULL == PsLpDomain) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmPsLpDomain_Init(PsLpDomain, PowerId,
BitMask, PowerParent,
&Args[3], (NumArgs - 3U));
break;
case (u32)XPM_NODETYPE_POWER_DOMAIN_NOC:
NpDomain = (XPm_NpDomain *)XPm_AllocBytes(sizeof(XPm_NpDomain));
if (NULL == NpDomain) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmNpDomain_Init(NpDomain, PowerId, 0x00000000,
PowerParent);
break;
case (u32)XPM_NODETYPE_POWER_DOMAIN_PL:
PlDomain = (XPm_PlDomain *)XPm_AllocBytes(sizeof(XPm_PlDomain));
if (NULL == PlDomain) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmPlDomain_Init(PlDomain, PowerId, 0x00000000,
PowerParent, &Args[3], (NumArgs - 3U));
break;
case (u32)XPM_NODETYPE_POWER_DOMAIN_CPM:
CpmDomain = (XPm_CpmDomain *)XPm_AllocBytes(sizeof(XPm_CpmDomain));
if (NULL == CpmDomain) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmCpmDomain_Init(CpmDomain, PowerId, 0x00000000, PowerParent,
&Args[3], (NumArgs - 3U));
break;
case (u32)XPM_NODETYPE_POWER_DOMAIN_ME:
AieDomain = (XPm_AieDomain *)XPm_AllocBytes(sizeof(XPm_AieDomain));
if (NULL == AieDomain) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmAieDomain_Init(AieDomain, PowerId, BitMask, PowerParent);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function add reset node to reset topology database
*
* @param Args reset arguments
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static XStatus XPm_AddNodeReset(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 ResetId, ControlReg;
u8 Shift, Width, ResetType, NumParents;
u32 *Parents;
if (NumArgs < 4U) {
Status = XST_INVALID_PARAM;
goto done;
}
ResetId = Args[0];
ControlReg = Args[1];
Shift = (u8)(Args[2] & 0xFFU);
Width = (u8)((Args[2] >> 8U) & 0xFFU);
ResetType = (u8)((Args[2] >> 16U) & 0xFFU);
NumParents = (u8)((Args[2] >> 24U) & 0xFFU);
Parents = &Args[3];
Status = XPmReset_AddNode(ResetId, ControlReg, Shift, Width, ResetType, NumParents, Parents);
done:
return Status;
}
static XStatus AddProcDevice(u32 *Args, u32 PowerId)
{
XStatus Status = XST_FAILURE;
u32 DeviceId;
u32 Type;
u32 Index;
XPm_Psm *Psm;
XPm_Pmc *Pmc;
XPm_ApuCore *ApuCore;
XPm_RpuCore *RpuCore;
XPm_Power *Power;
u32 BaseAddr[MAX_BASEADDR_LEN];
u32 Ipi;
DeviceId = Args[0];
BaseAddr[0] = Args[2];
Ipi = Args[3];
BaseAddr[1] = Args[4];
BaseAddr[2] = Args[5];
Type = NODETYPE(DeviceId);
Index = NODEINDEX(DeviceId);
Power = XPmPower_GetById(PowerId);
if (NULL == Power) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
if (Index >= (u32)XPM_NODEIDX_DEV_MAX) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
if (NULL != XPmDevice_GetById(DeviceId)) {
Status = XST_DEVICE_BUSY;
goto done;
}
switch (Type) {
case (u32)XPM_NODETYPE_DEV_CORE_PSM:
Psm = (XPm_Psm *)XPm_AllocBytes(sizeof(XPm_Psm));
if (NULL == Psm) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmPsm_Init(Psm, Ipi, BaseAddr, Power, NULL, NULL);
break;
case (u32)XPM_NODETYPE_DEV_CORE_APU:
ApuCore = (XPm_ApuCore *)XPm_AllocBytes(sizeof(XPm_ApuCore));
if (NULL == ApuCore) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmApuCore_Init(ApuCore, DeviceId, Ipi, BaseAddr, Power, NULL, NULL);
break;
case (u32)XPM_NODETYPE_DEV_CORE_RPU:
RpuCore = (XPm_RpuCore *)XPm_AllocBytes(sizeof(XPm_RpuCore));
if (NULL == RpuCore) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmRpuCore_Init(RpuCore, DeviceId, Ipi, BaseAddr, Power, NULL, NULL);
break;
case (u32)XPM_NODETYPE_DEV_CORE_PMC:
Pmc = (XPm_Pmc *)XPm_AllocBytes(sizeof(XPm_Pmc));
if (NULL == Pmc) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmPmc_Init(Pmc, DeviceId, 0, BaseAddr, Power, NULL, NULL);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
static XStatus AddPeriphDevice(u32 *Args, u32 PowerId)
{
XStatus Status = XST_FAILURE;
u32 DeviceId;
u32 Index;
u32 GicProxyMask;
u32 GicProxyGroup;
XPm_Periph *Device;
XPm_Power *Power;
u32 BaseAddr;
DeviceId = Args[0];
BaseAddr = Args[2];
GicProxyMask = Args[3];
GicProxyGroup = Args[4];
Index = NODEINDEX(DeviceId);
Power = XPmPower_GetById(PowerId);
if (NULL == Power) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
if (Index >= (u32)XPM_NODEIDX_DEV_MAX) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
if (NULL != XPmDevice_GetById(DeviceId)) {
Status = XST_DEVICE_BUSY;
goto done;
}
Device = (XPm_Periph *)XPm_AllocBytes(sizeof(XPm_Periph));
if (NULL == Device) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmPeriph_Init(Device, DeviceId, BaseAddr, Power, NULL, NULL,
GicProxyMask, GicProxyGroup);
done:
return Status;
}
static XStatus AddMemDevice(u32 *Args, u32 PowerId)
{
XStatus Status = XST_FAILURE;
u32 DeviceId;
u32 Type;
u32 Index;
XPm_MemDevice *Device;
XPm_Power *Power;
u32 BaseAddr;
u32 StartAddr;
u32 EndAddr;
DeviceId = Args[0];
BaseAddr = Args[2];
StartAddr = Args[3];
EndAddr = Args[4];
Power = XPmPower_GetById(PowerId);
if (NULL == Power) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
Type = NODETYPE(DeviceId);
Index = NODEINDEX(DeviceId);
if (Index >= (u32)XPM_NODEIDX_DEV_MAX) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
if (NULL != XPmDevice_GetById(DeviceId)) {
Status = XST_DEVICE_BUSY;
goto done;
}
switch (Type) {
case (u32)XPM_NODETYPE_DEV_OCM:
case (u32)XPM_NODETYPE_DEV_XRAM:
case (u32)XPM_NODETYPE_DEV_L2CACHE:
case (u32)XPM_NODETYPE_DEV_DDR:
case (u32)XPM_NODETYPE_DEV_TCM:
case (u32)XPM_NODETYPE_DEV_EFUSE:
Device = (XPm_MemDevice *)XPm_AllocBytes(sizeof(XPm_MemDevice));
if (NULL == Device) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmMemDevice_Init(Device, DeviceId, BaseAddr, Power, NULL, NULL, StartAddr, EndAddr);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
static XStatus AddMemCtrlrDevice(u32 *Args, u32 PowerId)
{
XStatus Status = XST_FAILURE;
u32 DeviceId;
u32 Type;
XPm_Device *Device;
XPm_Power *Power;
u32 BaseAddr;
DeviceId = Args[0];
BaseAddr = Args[2];
Power = XPmPower_GetById(PowerId);
if (NULL == Power) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
Type = NODETYPE(DeviceId);
if (NULL != XPmDevice_GetById(DeviceId)) {
Status = XST_DEVICE_BUSY;
goto done;
}
switch (Type) {
case (u32)XPM_NODETYPE_DEV_DDR:
Device = (XPm_Device *)XPm_AllocBytes(sizeof(XPm_Device));
if (NULL == Device) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmDevice_Init(Device, DeviceId, BaseAddr,
Power, NULL, NULL);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
static XStatus AddPhyDevice(u32 *Args, u32 PowerId)
{
XStatus Status = XST_FAILURE;
u32 DeviceId;
u32 Type;
XPm_Device *Device;
XPm_Power *Power;
u32 BaseAddr;
DeviceId = Args[0];
BaseAddr = Args[2];
Power = XPmPower_GetById(PowerId);
if (NULL == Power) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
Type = NODETYPE(DeviceId);
if (NULL != XPmDevice_GetById(DeviceId)) {
Status = XST_DEVICE_BUSY;
goto done;
}
switch (Type) {
case (u32)XPM_NODETYPE_DEV_GT:
Device = (XPm_Device *)XPm_AllocBytes(sizeof(XPm_Device));
if (NULL == Device) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmDevice_Init(Device, DeviceId, BaseAddr,
Power, NULL, NULL);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
static int AddPlDevice(u32 *Args, u32 PowerId)
{
int Status = XST_FAILURE;
u32 DeviceId;
u32 Index;
XPm_Power *Power;
XPm_Device *Device;
u32 BaseAddr;
DeviceId = Args[0];
BaseAddr = Args[2];
Index = NODEINDEX(DeviceId);
Power = XPmPower_GetById(PowerId);
if (NULL == Power) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
if ((u32)XPM_NODEIDX_DEV_PLD_MAX <= Index) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
/* Check if Device is already added or not. */
if (NULL != XPmDevice_GetById(DeviceId)) {
PmWarn("0x%x Device is already added\r\n", DeviceId);
Status = XST_DEVICE_BUSY;
goto done;
}
Device = (XPm_Device *)XPm_AllocBytes(sizeof(XPm_Device));
if (NULL == Device) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmDevice_Init(Device, DeviceId, BaseAddr, Power, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function adds device node to device topology database
*
* @param Args device specific arguments
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static XStatus XPm_AddDevice(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 DeviceId;
u32 SubClass;
u32 PowerId;
if (NumArgs < 3U) {
Status = XST_INVALID_PARAM;
goto done;
}
DeviceId = Args[0];
SubClass = NODESUBCLASS(DeviceId);
PowerId = Args[1];
if (NULL == XPmPower_GetById(PowerId)) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
switch (SubClass) {
case (u32)XPM_NODESUBCL_DEV_CORE:
Status = AddProcDevice(Args, PowerId);
break;
case (u32)XPM_NODESUBCL_DEV_PERIPH:
Status = AddPeriphDevice(Args, PowerId);
break;
case (u32)XPM_NODESUBCL_DEV_MEM:
Status = AddMemDevice(Args, PowerId);
break;
case (u32)XPM_NODESUBCL_DEV_MEM_CTRLR:
Status = AddMemCtrlrDevice(Args, PowerId);
break;
case (u32)XPM_NODESUBCL_DEV_PHY:
Status = AddPhyDevice(Args, PowerId);
break;
case (u32)XPM_NODESUBCL_DEV_PL:
Status = AddPlDevice(Args, PowerId);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function add memic node to the topology database
*
* @param Args MEMIC arguments
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static XStatus XPm_AddNodeMemIc(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 MemIcId;
u32 BaseAddress;
if (NumArgs < 3U) {
Status = XST_INVALID_PARAM;
goto done;
}
MemIcId = Args[0];
BaseAddress = Args[2];
if ((u32)XPM_NODECLASS_MEMIC != NODECLASS(MemIcId)) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((u32)XPM_NODESUBCL_MEMIC_NOC != NODESUBCLASS(MemIcId)) {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmNpDomain_MemIcInit(MemIcId, BaseAddress);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function add monitor node to the topology database
*
* @param Args arguments
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static XStatus XPm_AddNodeMonitor(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 NodeId, BaseAddress, NodeType;
if (NumArgs < 3U) {
Status = XST_INVALID_PARAM;
goto done;
}
NodeId = Args[0];
BaseAddress = Args[2];
if ((u32)XPM_NODECLASS_MONITOR != NODECLASS(NodeId)) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((u32)XPM_NODESUBCL_MONITOR_SYSMON != NODESUBCLASS(NodeId)) {
Status = XST_INVALID_PARAM;
goto done;
}
NodeType = NODETYPE(NodeId);
if ((((u32)XPM_NODETYPE_MONITOR_SYSMON_PMC != NodeType) &&
((u32)XPM_NODETYPE_MONITOR_SYSMON_PS != NodeType)
&& ((u32)XPM_NODETYPE_MONITOR_SYSMON_NPD != NodeType)) ||
((u32)XPM_NODEIDX_MONITOR_MAX <= NODEINDEX(NodeId))) {
Status = XST_INVALID_PARAM;
goto done;
}
SysmonAddresses[NODEINDEX(NodeId)] = BaseAddress;
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function add xmpu/xppu node to the topology database
*
* @param Args Node arguments
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static XStatus XPm_AddNodeProt(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 NodeId;
u32 BaseAddress;
u32 SubClass;
XPm_ProtPpu *PpuNode;
XPm_ProtMpu *MpuNode;
if (NumArgs < 3U) {
Status = XST_INVALID_PARAM;
goto done;
}
NodeId = Args[0];
BaseAddress = Args[2];
SubClass = NODESUBCLASS(NodeId);
if ((u32)XPM_NODECLASS_PROTECTION != NODECLASS(NodeId)) {
Status = XST_INVALID_PARAM;
goto done;
}
switch (SubClass) {
case (u32)XPM_NODESUBCL_PROT_XPPU:
PpuNode = XPm_AllocBytes(sizeof(XPm_ProtPpu));
if (NULL == PpuNode) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmProtPpu_Init(PpuNode, NodeId, BaseAddress);
break;
case (u32)XPM_NODESUBCL_PROT_XMPU:
MpuNode = XPm_AllocBytes(sizeof(XPm_ProtMpu));
if (NULL == MpuNode) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmProtMpu_Init(MpuNode, NodeId, BaseAddress);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function add mio pin node to the topology database
*
* @param Args mio arguments
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
static XStatus XPm_AddNodeMio(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 MioId;
u32 BaseAddress;
XPm_PinNode *MioPin;
if (NumArgs < 3U) {
Status = XST_INVALID_PARAM;
goto done;
}
MioId = Args[0];
BaseAddress = Args[1];
if ((u32)XPM_NODECLASS_STMIC != NODECLASS(MioId)) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((u32)XPM_NODESUBCL_PIN != NODESUBCLASS(MioId)) {
Status = XST_INVALID_PARAM;
goto done;
}
if (((u32)XPM_NODETYPE_LPD_MIO != NODETYPE(MioId)) &&
((u32)XPM_NODETYPE_PMC_MIO != NODETYPE(MioId))) {
Status = XST_INVALID_PARAM;
goto done;
}
MioPin = (XPm_PinNode *)XPm_AllocBytes(sizeof(XPm_PinNode));
if (NULL == MioPin) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmPin_Init(MioPin, MioId, BaseAddress);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function allows adding node to clock, power, reset, mio
* or device topology
*
* @param Args Node specific arguments
* @param NumArgs number of arguments
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_AddNode(u32 *Args, u32 NumArgs)
{
int Status = XST_FAILURE;
u32 Id = Args[0];
switch (NODECLASS(Id)) {
case (u32)XPM_NODECLASS_POWER:
Status = XPm_AddNodePower(Args, NumArgs);
break;
case (u32)XPM_NODECLASS_CLOCK:
Status = XPm_AddNodeClock(Args, NumArgs);
break;
case (u32)XPM_NODECLASS_RESET:
Status = XPm_AddNodeReset(Args, NumArgs);
break;
case (u32)XPM_NODECLASS_MEMIC:
Status = XPm_AddNodeMemIc(Args, NumArgs);
break;
case (u32)XPM_NODECLASS_STMIC:
Status = XPm_AddNodeMio(Args, NumArgs);
break;
case (u32)XPM_NODECLASS_DEVICE:
Status = XPm_AddDevice(Args, NumArgs);
break;
case (u32)XPM_NODECLASS_PROTECTION:
Status = XPm_AddNodeProt(Args, NumArgs);
break;
case (u32)XPM_NODECLASS_MONITOR:
Status = XPm_AddNodeMonitor(Args, NumArgs);
break;
default:
Status = XST_INVALID_PARAM;
break;
}
return Status;
}
/****************************************************************************/
/**
* @brief This function links a device to a subsystem so requirement
* assignment could be made by XPm_RequestDevice() or
* XPm_SetRequirement() call.
*
* @param SubsystemId Subsystem Id
* @param DeviceId Device Id
* @param Flags Bit0-2 - No restriction/ Shared/Time Shared/Nonshared/ - 0,1,2,3
* Bit 3 -Secure(1)/Nonsecure(0) (Device mode)
* @param Params Optional: XPPU- master id mask for peripherals
* @param NumParams Number of params
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
*
****************************************************************************/
XStatus XPm_AddRequirement(const u32 SubsystemId, const u32 DeviceId, u32 Flags, u32 *Params, u32 NumParams)
{
XStatus Status = XST_INVALID_PARAM;
XPm_Device *Device = NULL;
XPm_Subsystem *Subsystem;
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (Subsystem == NULL || Subsystem->State != (u8)ONLINE) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
Device = (XPm_Device *)XPmDevice_GetById(DeviceId);
if (NULL == Device) {
Status = XPM_INVALID_DEVICEID;
goto done;
}
Status = XPmRequirement_Add(Subsystem, Device, Flags, Params, NumParams);
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
static int XPm_GetTemperature(u32 const DeviceId, u32 *Result)
{
int Status = XST_FAILURE;
static XSysMonPsv SysMonInst;
XSysMonPsv *SysMonInstPtr = &SysMonInst;
XSysMonPsv_Config *ConfigPtr;
if ((u32)XPM_NODECLASS_DEVICE != NODECLASS(DeviceId)) {
goto done;
}
/*
* TODO - need to implement getting temperature, beside the
* temperature of entire SoC.
*/
if ((u32)XPM_NODETYPE_DEV_SOC != NODETYPE(DeviceId)) {
Status = XST_NO_FEATURE;
goto done;
}
/* Initialize the SysMon driver. */
ConfigPtr = XSysMonPsv_LookupConfig();
if (ConfigPtr == NULL) {
goto done;
}
Status = XSysMonPsv_CfgInitialize(SysMonInstPtr, ConfigPtr);
if (XST_SUCCESS != Status) {
goto done;
}
*Result = XSysMonPsv_ReadDeviceTemp(SysMonInstPtr,
XSYSMONPSV_VAL_VREF_MAX);
Status = XST_SUCCESS;
done:
return Status;
}
static int XPm_GetLatency(const u32 DeviceId, u32 *Latency)
{
int Status = XST_SUCCESS;
switch (NODECLASS(DeviceId)) {
case (u32)XPM_NODECLASS_DEVICE:
if ((u32)XPM_NODESUBCL_DEV_CORE == NODESUBCLASS(DeviceId)) {
Status = XPmCore_GetWakeupLatency(DeviceId, Latency);
} else {
Status = XPmDevice_GetWakeupLatency(DeviceId, Latency);
}
break;
case (u32)XPM_NODECLASS_POWER:
Status = XPmPower_GetWakeupLatency(DeviceId, Latency);
break;
case (u32)XPM_NODECLASS_CLOCK:
if ((u32)XPM_NODESUBCL_CLOCK_PLL == NODESUBCLASS(DeviceId)) {
Status = XPmClockPll_GetWakeupLatency(DeviceId, Latency);
} else {
Status = XST_INVALID_PARAM;
}
break;
default:
Status = XST_INVALID_PARAM;
break;
}
return Status;
}
/****************************************************************************/
/**
* @brief This function gets operating characteristics of a device
*
* @param DeviceId Targeted device Id.
* @param Type Type of the operating characteristics:
* power, temperature, and latency
* @param Result Returns the value of operating characteristic type
*
* @return XST_SUCCESS if successful else either XST_NO_FEATURE or XST_FAILURE.
*
* @note Temperature reported in Celsius (signed Q8.7 format)
*
****************************************************************************/
XStatus XPm_GetOpCharacteristic(u32 const DeviceId, u32 const Type, u32 *Result)
{
XStatus Status = XST_FAILURE;
switch(Type) {
case (u32)PM_OPCHAR_TYPE_TEMP:
Status = XPm_GetTemperature(DeviceId, Result);
break;
case (u32)PM_OPCHAR_TYPE_LATENCY:
Status = XPm_GetLatency(DeviceId, Result);
break;
case (u32)PM_OPCHAR_TYPE_POWER:
Status = XST_NO_FEATURE;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
return Status;
}
/****************************************************************************/
/**
* @brief Register a subsystem to be notified about the device event
*
* @param IpiMask IPI mask of current subsystem
* @param SubsystemId Subsystem to be notified
* @param NodeId Node to which the event is related
* @param Event Event in question
* @param Wake Wake subsystem upon capturing the event if value 1
* @param Enable Enable the registration for value 1, disable for value 0
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note None
****************************************************************************/
int XPm_RegisterNotifier(const u32 SubsystemId, const u32 NodeId,
const u32 Event, const u32 Wake, const u32 Enable,
const u32 IpiMask)
{
int Status = XST_FAILURE;
XPm_Subsystem* Subsystem = NULL;
/* Validate SubsystemId */
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
goto done;
}
/* Only Event and Device Nodes are supported */
if (((u32)XPM_NODECLASS_EVENT != NODECLASS(NodeId)) &&
((u32)XPM_NODECLASS_DEVICE != NODECLASS(NodeId))) {
goto done;
}
/* Validate other parameters */
if ((((u32)XPM_NODECLASS_EVENT == NODECLASS(NodeId)) &&
(Event >= XPLMI_NODEIDX_ERROR_PSMERR2_MAX)) ||
(((u32)XPM_NODECLASS_DEVICE == NODECLASS(NodeId)) &&
(((0U != Wake) && (1U != Wake)) ||
((0U != Enable) && (1U != Enable)) ||
(((u32)EVENT_STATE_CHANGE != Event) &&
((u32)EVENT_ZERO_USERS != Event))))) {
Status = XST_INVALID_PARAM;
goto done;
}
if (0U == Enable) {
XPmNotifier_Unregister(Subsystem, NodeId, Event);
Status = XST_SUCCESS;
} else {
Status = XPmNotifier_Register(Subsystem, NodeId, Event, Wake,
IpiMask);
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function returns supported version of the given API.
*
* @param ApiId API ID to check
* @param Version Supported version number
*
* @return XST_SUCCESS if successful else XST_NO_FEATURE.
*
* @note None
*
****************************************************************************/
int XPm_FeatureCheck(const u32 ApiId, u32 *const Version)
{
int Status = XST_FAILURE;
if (NULL == Version) {
Status = XPM_ERR_VERSION;
goto done;
}
switch (ApiId) {
case PM_GET_API_VERSION:
case PM_GET_NODE_STATUS:
case PM_GET_OP_CHARACTERISTIC:
case PM_REGISTER_NOTIFIER:
case PM_REQUEST_SUSPEND:
case PM_SELF_SUSPEND:
case PM_FORCE_POWERDOWN:
case PM_ABORT_SUSPEND:
case PM_REQUEST_WAKEUP:
case PM_SET_WAKEUP_SOURCE:
case PM_SYSTEM_SHUTDOWN:
case PM_REQUEST_NODE:
case PM_RELEASE_NODE:
case PM_SET_REQUIREMENT:
case PM_SET_MAX_LATENCY:
case PM_RESET_ASSERT:
case PM_RESET_GET_STATUS:
case PM_INIT_FINALIZE:
case PM_GET_CHIPID:
case PM_PINCTRL_REQUEST:
case PM_PINCTRL_RELEASE:
case PM_PINCTRL_GET_FUNCTION:
case PM_PINCTRL_SET_FUNCTION:
case PM_PINCTRL_CONFIG_PARAM_GET:
case PM_PINCTRL_CONFIG_PARAM_SET:
case PM_IOCTL:
case PM_CLOCK_ENABLE:
case PM_CLOCK_DISABLE:
case PM_CLOCK_GETSTATE:
case PM_CLOCK_SETDIVIDER:
case PM_CLOCK_GETDIVIDER:
case PM_CLOCK_SETPARENT:
case PM_CLOCK_GETPARENT:
case PM_PLL_SET_PARAMETER:
case PM_PLL_GET_PARAMETER:
case PM_PLL_SET_MODE:
case PM_PLL_GET_MODE:
case PM_ADD_SUBSYSTEM:
case PM_DESTROY_SUBSYSTEM:
case PM_DESCRIBE_NODES:
case PM_ADD_NODE:
case PM_ADD_NODE_PARENT:
case PM_ADD_NODE_NAME:
case PM_ADD_REQUIREMENT:
case PM_SET_CURRENT_SUBSYSTEM:
case PM_INIT_NODE:
case PM_FEATURE_CHECK:
*Version = XST_API_BASE_VERSION;
Status = XST_SUCCESS;
break;
case PM_QUERY_DATA:
*Version = XST_API_QUERY_DATA_VERSION;
Status = XST_SUCCESS;
break;
default:
*Version = 0U;
Status = XPM_NO_FEATURE;
break;
}
done:
if(Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilsecure_v4_2/src/versal/xsecure_sha.h
/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_sha.h
* @addtogroup xsecure_sha3_apis SHA-3
* @{
* @cond xsecure_internal
* This file Contains the function prototypes, defines and macros for
* the SHA-384 hardware module.
*
* This driver supports the following features:
*
* - SHA-3 hash calculation
*
* <b>Initialization & Configuration</b>
*
* The SHA-3 driver instance can be initialized
* in the following way:
*
* - XSecure_Sha3Initialize(XSecure_Sha3 *InstancePtr, XPmcDma *DmaPtr)
*
* A pointer to XPmcDma instance has to be passed in initialization as PMC
* DMA will be used for data transfers to SHA module.
*
*
* @note
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.2 har 03/20/20 Initial release
*
* </pre>
*
* @note
* @endcond
*
******************************************************************************/
#ifndef XSECURE_SHA_H
#define XSECURE_SHA_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xpmcdma.h"
#include "xsecure_sss.h"
/************************** Constant Definitions ****************************/
/** @cond xsecure_internal
@{
*/
/**
* SHA3 Memory Map
*/
#define XSECURE_SHA3_START_START (1U << 0) /**< SHA Start Message */
#define XSECURE_SHA3_RESET_RESET (1U << 0) /**< SHA Reset Value */
#define XSECURE_SHA3_DONE_DONE (1U << 0) /**< SHA Done */
#define XSECURE_SHA3_BLOCK_LEN (104U) /**< SHA min block length */
#define XSECURE_SHA3_LAST_PACKET (0x1U) /**< Last Data Packet */
#define XSECURE_PMC_DMA_MAX_TRANSFER (0x1FFFFFFCU) /** < PMC DMA Max Transfer
rate in bytes*/
#define XSECURE_SHA_TIMEOUT_MAX (0x1FFFFU)
#define XSECURE_HASH_SIZE_IN_BYTES (48U)
/**
* SHA3 padding type
*/
/***************************** Type Definitions******************************/
/* Sha3 driver states */
typedef enum {
XSECURE_SHA3_UNINITIALIZED = 0,
XSECURE_SHA3_INITIALIZED,
XSECURE_SHA3_ENGINE_STARTED
} XSecure_Sha3State;
/**
* The SHA-3 driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
u32 BaseAddress; /**< Device Base Address */
XPmcDma *DmaPtr; /**< Pointer to PMC DMA Instance */
u32 Sha3Len; /**< SHA3 Input Length */
u32 PartialLen;
u32 IsLastUpdate;
u8 PartialData[XSECURE_SHA3_BLOCK_LEN];
XSecure_Sss SssInstance;
XSecure_Sha3State Sha3State;
} XSecure_Sha3;
/**
@}
@endcond */
/***************************** Function Prototypes ***************************/
/* Initialization */
u32 XSecure_Sha3Initialize(XSecure_Sha3 *InstancePtr, XPmcDma *DmaPtr);
void XSecure_Sha3Start(XSecure_Sha3 *InstancePtr);
/* Data Transfer */
u32 XSecure_Sha3Update(XSecure_Sha3 *InstancePtr, const u8 *Data,
const u32 Size);
u32 XSecure_Sha3Finish(XSecure_Sha3 *InstancePtr, u8 *Hash);
/* Complete SHA digest calculation */
u32 XSecure_Sha3Digest(XSecure_Sha3 *InstancePtr, const u8 *In,
const u32 Size, u8 *Out);
void XSecure_Sha3ReadHash(XSecure_Sha3 *InstancePtr, u8 *Hash);
u32 XSecure_Sha3LastUpdate(XSecure_Sha3 *InstancePtr);
u32 XSecure_Sha3WaitForDone(XSecure_Sha3 *InstancePtr);
u32 XSecure_Sha3Kat(XSecure_Sha3 *SecureSha3);
#ifdef __cplusplus
}
#endif
#endif /** XSECURE_SHA_H */
/* @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_power.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* Power nodes (power islands and power domains) related structures,
* transition actions, and FSM definition.
*********************************************************************/
#include "pm_power.h"
#include "pm_common.h"
#include "pm_proc.h"
#include "pm_master.h"
#include "pm_reset.h"
#include "pm_sram.h"
#include "pm_periph.h"
#include "pm_pll.h"
#include "pm_usb.h"
#include "pm_requirement.h"
#include "xpfw_rom_interface.h"
#include "crf_apb.h"
#include "pm_system.h"
#include "pm_ddr.h"
#include "apu.h"
#include "pm_clock.h"
#include "rpu.h"
#include "xpfw_util.h"
#include "pm_gpp.h"
#include "xpfw_aib.h"
#include "pm_hooks.h"
#define DEFINE_PM_POWER_CHILDREN(c) .children = ((c)), \
.childCnt = ARRAY_SIZE((c))
#define PM_FPD_POWER_SUPPLYCHECK_TIMEOUT 727273U /* Delay of 40ms */
#define PM_PLD_POWER_SUPPLYCHECK_TIMEOUT 100000U /* Delay of 5ms */
#define AMS_PSSYSMON_CONFIG_REG2 0XFFA50908U
#define A53_DBG_0_EDPRCR_REG (0xFEC10310U) /* APU_0 external debug control */
#define A53_DBG_1_EDPRCR_REG (0xFED10310U) /* APU_1 external debug control */
#define A53_DBG_2_EDPRCR_REG (0xFEE10310U) /* APU_2 external debug control */
#define A53_DBG_3_EDPRCR_REG (0xFEF10310U) /* APU_3 external debug control */
#define A53_DBG_EDPRCR_REG_MASK (0x00000009U) /* COREPURQ and CORENPDRQ bit mask */
/**
* PmPowerStack() - Used to construct stack for implementing non-recursive
* depth-first search in power graph
* @power Power node pushed/popped from stack
* @index Index of the child to be visited when the power node gets popped
*/
typedef struct PmPowerStack {
PmPower* power;
u8 index;
} PmPowerStack;
/**
* PmPowerDfs() - Captures current state of depth-first search in power graph
* @power Currently visited power node
* @it Iterator/index of the power's child that is currently visited
* @sp Power stack pointer
*/
typedef struct PmPowerDfs {
PmPower* power;
u8 it;
u8 sp;
} PmPowerDfs;
/*
* Stack size is equal to the number of levels in power hierarchy. Power
* hierarchy has only 2 levels: power islands and domains, therefore the stack
* size is 2. If this changes in future the stack size should be incremented.
*/
static PmPowerStack pmPowerStack[2];
static PmPowerDfs pmDfs;
/**
* PmPowerStackPush() - Push power/index on stack
* @power Power node pushed on stack
* @index Index of a child which should be visited upon pop
*/
void PmPowerStackPush(PmPower* const power, const u8 index)
{
/* Stack overflow should never happen */
if (ARRAY_SIZE(pmPowerStack) == pmDfs.sp) {
PmAlert("Power stack overflow\r\n");
goto done;
}
pmPowerStack[pmDfs.sp].power = power;
pmPowerStack[pmDfs.sp].index = index;
pmDfs.sp++;
done:
return;
}
/**
* PmPowerStackPop() - Pop power/index from stack
* @power Pointer to the location where to store popped power node pointer
* @index Pointer to the location where to store popped index
*/
void PmPowerStackPop(PmPower** const power, u8* const index)
{
if (0U == pmDfs.sp) {
/* This should never happen */
PmAlert("Power stack empty\r\n");
goto done;
}
pmDfs.sp--;
*power = pmPowerStack[pmDfs.sp].power;
*index = pmPowerStack[pmDfs.sp].index;
/* Clearing is not needed, but it's nice for debugging */
(void)memset(&pmPowerStack[pmDfs.sp], 0U, sizeof(PmPowerStack));
done:
return;
}
/**
* PmPowerStackIsEmpty() - Check if power stack is empty
* @return True if empty, false otherwise
*/
static inline bool PmPowerStackIsEmpty(void)
{
return (0U == pmDfs.sp);
}
/**
* PmPowerDfsBegin() - Prepare for the power graph search
* @power Power node which is the root of the searched graph
*/
static void PmPowerDfsBegin(PmPower* const power)
{
/* Clearing stack is not needed, but it's nice for debugging */
(void)memset(pmPowerStack, 0U, sizeof(pmPowerStack));
pmDfs.sp = 0U;
pmDfs.it = 0U;
pmDfs.power = NULL;
PmPowerStackPush(power, 0U);
}
/**
* PmPowerDfsGetNext() - Get next node (DFS)
* @return Pointer to the next node or NULL if all nodes are visited
*/
static PmNode* PmPowerDfsGetNext(void)
{
PmNode* node = NULL;
while ((NULL != pmDfs.power) || (false == (u8)PmPowerStackIsEmpty())) {
if (NULL == pmDfs.power) {
PmPowerStackPop(&pmDfs.power, &pmDfs.it);
}
if (pmDfs.power->childCnt == pmDfs.it) {
node = &pmDfs.power->node;
pmDfs.power = NULL;
goto done;
}
if (NODE_IS_POWER(pmDfs.power->children[pmDfs.it])) {
PmPowerStackPush(pmDfs.power, pmDfs.it + 1U);
PmPowerStackPush(pmDfs.power->children[pmDfs.it]->derived, 0U);
pmDfs.power = NULL;
} else {
node = pmDfs.power->children[pmDfs.it];
pmDfs.it++;
goto done;
}
}
done:
return node;
}
/*
* Note: PLL registers will never be saved/restored as part of CRF_APB module
* context. PLLs have separate logic, which is part of the PLL management
* (see pm_pll.h/c)
*/
static PmRegisterContext pmFpdContext[] = {
{ .addr = CRF_APB_ERR_CTRL },
{ .addr = CRF_APB_CRF_WPROT },
{ .addr = CRF_APB_ACPU_CTRL, },
{ .addr = CRF_APB_DBG_TRACE_CTRL },
{ .addr = CRF_APB_DBG_FPD_CTRL },
{ .addr = CRF_APB_DP_VIDEO_REF_CTRL },
{ .addr = CRF_APB_DP_AUDIO_REF_CTRL },
{ .addr = CRF_APB_DP_STC_REF_CTRL },
{ .addr = CRF_APB_DDR_CTRL },
{ .addr = CRF_APB_GPU_REF_CTRL },
{ .addr = CRF_APB_SATA_REF_CTRL },
{ .addr = CRF_APB_PCIE_REF_CTRL },
{ .addr = CRF_APB_GDMA_REF_CTRL },
{ .addr = CRF_APB_DPDMA_REF_CTRL },
{ .addr = CRF_APB_TOPSW_MAIN_CTRL },
{ .addr = CRF_APB_TOPSW_LSBUS_CTRL },
{ .addr = CRF_APB_GTGREF0_REF_CTRL },
{ .addr = CRF_APB_DBG_TSTMP_CTRL },
{ .addr = CRF_APB_RST_FPD_TOP },
{ .addr = CRF_APB_RST_FPD_APU },
{ .addr = APU_PWRCTL },
};
/**
* PmFpdPowerSupplyCheck() - Wrapper for PMU-ROM FPD power supply check handler
* @RomHandler Default PMU-ROM handler for FPD power supply check
*
* @return The PMU-ROM handler's return value
*
* @note The wrapper just introduces a timeout based on counting.
* This function should be replaced by either Sysmon-based check
* or custom/board specific implementation.
*/
static u32 PmFpdPowerSupplyCheck(XpbrServHndlr_t RomHandler)
{
s32 status;
u32 var = 0U;
/* Cheat compiler to not optimize timeout based on counting */
(void)XPfw_UtilPollForMask((u32)&var, ~var,
PM_FPD_POWER_SUPPLYCHECK_TIMEOUT);
status = RomHandler();
return status;
}
/**
* PmPldPowerSupplyCheck() - Wrapper for PMU-ROM PLD power supply check handler
* @RomHandler Default PMU-ROM handler for PLD power supply check
*
* @return The PMU-ROM handler's return value
*
* @note The wrapper just introduces a timeout based on counting.
* This function should be replaced by either Sysmon-based check
* or custom/board specific implementation.
*/
static u32 PmPldPowerSupplyCheck(XpbrServHndlr_t RomHandler)
{
s32 status;
u32 var = 0U;
/* Cheat compiler to not optimize timeout based on counting */
(void)XPfw_UtilPollForMask((u32)&var, ~var,
PM_PLD_POWER_SUPPLYCHECK_TIMEOUT);
status = RomHandler();
return status;
}
/*
* PmPowerDomainConstruct() - Constructor method to call for power domain node
* @power Power node of a domain
*/
static void PmPowerDomainConstruct(PmPower* const power)
{
PmPowerDomain* pd = (PmPowerDomain*)power->node.derived;
if (NULL != pd->supplyCheckHook) {
XpbrServExtTbl[pd->supplyCheckHookId] = pd->supplyCheckHook;
}
}
static PmPowerClass pmPowerClassDomain_g = {
.construct = PmPowerDomainConstruct,
.forceDown = NULL,
};
/**
* PmFpdSaveContext() - Save context of CRF_APB module due to powering down FPD
*/
void PmFpdSaveContext(void)
{
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmFpdContext); i++) {
pmFpdContext[i].value = XPfw_Read32(pmFpdContext[i].addr);
}
}
/**
* PmFpdRestoreContext() - Restore context of CRF_APB module (FPD has been
* powered up)
*/
void PmFpdRestoreContext(void)
{
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmFpdContext); i++) {
XPfw_Write32(pmFpdContext[i].addr, pmFpdContext[i].value);
}
}
/**
* PmPowerDownFpd() - Power down FPD domain
*
* @return Status of the pmu-rom operations
*/
static s32 PmPowerDownFpd(void)
{
s32 status;
if (A53_DBG_EDPRCR_REG_MASK & (XPfw_Read32(A53_DBG_0_EDPRCR_REG) |
XPfw_Read32(A53_DBG_1_EDPRCR_REG) |
XPfw_Read32(A53_DBG_2_EDPRCR_REG) |
XPfw_Read32(A53_DBG_3_EDPRCR_REG))) {
PmInfo("Skipped FPD pwrdn (debugger connected)\r\n");
return XST_SUCCESS;
}
/* Block FPD power down if any of the LPD peripherals uses CCI path which is in FPD */
#ifdef XPAR_LPD_IS_CACHE_COHERENT
PmErr("Blocked FPD pwrdn (CCI used by LPD)\r\n");
status = XST_FAILURE;
goto err;
#endif /* XPAR_LPD_IS_CACHE_COHERENT */
PmFpdSaveContext();
ddr_io_prepare();
status = PmResetAssertInt(PM_RESET_FPD, PM_RESET_ACTION_ASSERT);
if (XST_SUCCESS != status) {
goto err;
}
XPfw_AibEnable(XPFW_AIB_LPD_TO_DDR);
XPfw_AibEnable(XPFW_AIB_LPD_TO_FPD);
status = XpbrPwrDnFpdHandler();
if (XST_SUCCESS != status) {
goto err;
}
/*
* When FPD is powered off, the APU-GIC will be affected too.
* GIC Proxy has to take over for all wake-up sources for
* the APU.
*/
pmMasterApu_g.gic->enable();
err:
return status;
}
/**
* PmPowerDownLpd() - Power down LPD domain
*
* @return Function doesn't return because LPD is powered down
*/
static s32 __attribute__((noreturn)) PmPowerDownLpd(void)
{
#ifdef ENABLE_POS
/* Call user hook for finishing Power Off Suspend */
PmHookFinalizePowerOffSuspend();
#endif
/* Call user hook for powering down LPD */
PmHookPowerDownLpd();
while (1);
}
/**
* PmPowerUpRpu() - Power up RPU island and disable AIBs
*
* @return Status returned by the PMU-ROM handler
*/
static s32 PmPowerUpRpu(void)
{
s32 status;
status = XpbrPwrUpRpuHandler();
if (XST_SUCCESS != status) {
goto done;
}
XPfw_AibDisable(XPFW_AIB_RPU0_TO_LPD);
XPfw_AibDisable(XPFW_AIB_RPU1_TO_LPD);
XPfw_AibDisable(XPFW_AIB_LPD_TO_RPU0);
XPfw_AibDisable(XPFW_AIB_LPD_TO_RPU1);
done:
return status;
}
/**
* PmPowerUpFpd() - Power up FPD domain
*
* @return Status of the pmu-rom operations
*/
static s32 PmPowerUpFpd(void)
{
if (0 != (XPfw_Read32(PMU_GLOBAL_PWR_STATE) &
PMU_GLOBAL_PWR_STATE_FP_MASK)) {
PmInfo("Skipped FPD pwrup (FPD is on)\r\n");
return XST_SUCCESS;
}
s32 status = XpbrPwrUpFpdHandler();
if (XST_SUCCESS != status) {
goto err;
}
status = PmResetAssertInt(PM_RESET_FPD, PM_RESET_ACTION_RELEASE);
if (XST_SUCCESS != status) {
goto err;
}
XPfw_AibDisable(XPFW_AIB_LPD_TO_DDR);
XPfw_AibDisable(XPFW_AIB_LPD_TO_FPD);
PmFpdRestoreContext();
err:
return status;
}
/**
* PmPowerDownRpu() - Wrapper for powering down RPU (due to the return cast)
* Enables AIBs at RPU interfaces to gracefully respond to
* AXI transactions when RPU is powered down
* @return Return value of PMU-ROM handler
*/
static s32 PmPowerDownRpu(void)
{
XPfw_AibEnable(XPFW_AIB_RPU0_TO_LPD);
XPfw_AibEnable(XPFW_AIB_RPU1_TO_LPD);
XPfw_AibEnable(XPFW_AIB_LPD_TO_RPU0);
XPfw_AibEnable(XPFW_AIB_LPD_TO_RPU1);
return XpbrPwrDnRpuHandler();
}
/**
* PmPowerForceDownRpu() - Force down RPU island
* @power RPU power island
*/
static void PmPowerForceDownRpu(PmPower* const power)
{
/*
* To access TCM, RPU island needs to be on. If RPU island if getting
* turned off, TCM also needs to be turned off. Otherwise, user may not
* get correct state of TCM whether TCM can be accessed or not.
*/
PmNodeForceDown(&pmSlaveTcm0A_g.sram.slv.node);
PmNodeForceDown(&pmSlaveTcm0B_g.sram.slv.node);
PmNodeForceDown(&pmSlaveTcm1A_g.sram.slv.node);
PmNodeForceDown(&pmSlaveTcm1B_g.sram.slv.node);
/* Reset RPU AMBA */
PmResetAssertInt(PM_RESET_RPU_AMBA, PM_RESET_ACTION_ASSERT);
}
/**
* PmPowerDownPld() - Wrapper for powering down PLD (due to the return cast)
* @return Return value of PMU-ROM handler
*/
static s32 PmPowerDownPld(void)
{
XPfw_AibEnable(XPFW_AIB_LPD_TO_AFI_FS2);
XPfw_AibEnable(XPFW_AIB_FPD_TO_AFI_FS0);
XPfw_AibEnable(XPFW_AIB_FPD_TO_AFI_FS1);
return XpbrPwrDnPldHandler();
}
/**
* PmPowerUpPld() - Wrapper for powering up PLD (due to the return cast)
* @return Return value of PMU-ROM handler
*/
static s32 PmPowerUpPld(void)
{
u32 status;
status = XpbrPwrUpPldHandler();
if (XST_SUCCESS != status) {
goto done;
}
XPfw_AibDisable(XPFW_AIB_LPD_TO_AFI_FS2);
XPfw_AibDisable(XPFW_AIB_FPD_TO_AFI_FS0);
XPfw_AibDisable(XPFW_AIB_FPD_TO_AFI_FS1);
done:
return status;
}
/**
* PmPowerPowerDownSysOsc() - Wrapper to put SysOsc in sleep mode.
*/
static void PmPowerDownSysOsc(void)
{
u32 val;
/* Put Sysosc in sleep mode */
val = Xil_In32(AMS_PSSYSMON_CONFIG_REG2);
val |= 0x30U;
Xil_Out32(AMS_PSSYSMON_CONFIG_REG2, val);
}
/**
* PmPowerPowerUpSysOsc() - Wrapper to put SysOsc in normal operation mode.
*/
static void PmPowerUpSysOsc(void)
{
u32 val;
/* Wake up SysOsc */
val = Xil_In32(AMS_PSSYSMON_CONFIG_REG2);
val &= 0xFF0FU;
Xil_Out32(AMS_PSSYSMON_CONFIG_REG2, val);
}
/**
* PmPowerDown() - Power down the power node
* @power Power node in question
*
* @return Status of powering down (what powerDown handler returns or
* XST_SUCCESS)
*/
s32 PmPowerDown(PmPower* const power)
{
s32 status = XST_SUCCESS;
if (PM_PWR_STATE_OFF == power->node.currState) {
goto done;
}
if (NULL != power->powerDown) {
status = power->powerDown();
}
if (XST_SUCCESS != status) {
goto done;
}
PmNodeUpdateCurrState(&power->node, PM_PWR_STATE_OFF);
if (NULL != power->node.clocks) {
PmClockRelease(&power->node);
}
PmInfo("%s 1->0\r\n", power->node.name);
#ifdef DEBUG_MODE
if ((pmPowerIslandRpu_g.power.node.currState == PM_PWR_STATE_OFF) &&
(pmPowerDomainFpd_g.power.node.currState == PM_PWR_STATE_OFF)) {
PmRequirement* req;
#if (STDOUT_BASEADDRESS == XPAR_PSU_UART_0_BASEADDR)
req = PmRequirementGetNoMaster(&pmSlaveUart0_g);
#elif (STDOUT_BASEADDRESS == XPAR_PSU_UART_1_BASEADDR)
req = PmRequirementGetNoMaster(&pmSlaveUart1_g);
#endif
status = PmRequirementUpdate(req, 0U);
if (XST_SUCCESS != status) {
goto done;
}
}
#endif
/* Put SysOsc in sleep mode while going to deep sleep mode. */
if ((pmPowerIslandRpu_g.power.node.currState == PM_PWR_STATE_OFF) &&
(pmPowerDomainFpd_g.power.node.currState == PM_PWR_STATE_OFF) &&
(pmPowerDomainPld_g.power.node.currState == PM_PWR_STATE_OFF) &&
(pmIOpll_g.node.currState == PM_PLL_STATE_RESET) &&
(pmRpll_g.node.currState == PM_PLL_STATE_RESET)) {
PmPowerDownSysOsc();
}
done:
return status;
}
/**
* PmPowerUp() - Power up island/domain
* @power Power node to be powered up
*
* @return Operation status of power up procedure (node specific) or
* XST_SUCCESS
*/
static s32 PmPowerUp(PmPower* const power)
{
s32 status = XST_SUCCESS;
/* Enable SysOsc for normal operation if it is in sleep mode. */
if ((Xil_In32(AMS_PSSYSMON_CONFIG_REG2) & 0xF0U) == 0x30U) {
PmPowerUpSysOsc();
}
#ifdef DEBUG_MODE
PmRequirement* req;
#if (STDOUT_BASEADDRESS == XPAR_PSU_UART_0_BASEADDR)
req = PmRequirementGetNoMaster(&pmSlaveUart0_g);
#elif (STDOUT_BASEADDRESS == XPAR_PSU_UART_1_BASEADDR)
req = PmRequirementGetNoMaster(&pmSlaveUart1_g);
#endif
status = PmRequirementUpdate(req, PM_CAP_ACCESS);
if (XST_SUCCESS != status) {
goto done;
}
#endif
PmInfo("%s 0->1\r\n", power->node.name);
if (PM_PWR_STATE_ON == power->node.currState) {
goto done;
}
if (NULL != power->powerUp) {
status = power->powerUp();
}
if (XST_SUCCESS != status) {
goto done;
}
if (NULL != power->node.clocks) {
status = PmClockRequest(&power->node);
}
PmNodeUpdateCurrState(&power->node, PM_PWR_STATE_ON);
done:
return status;
}
/* Children array definitions */
static PmNode* pmApuChildren[] = {
&pmProcApu0_g.node,
&pmProcApu1_g.node,
&pmProcApu2_g.node,
&pmProcApu3_g.node,
};
static PmNode* pmRpuChildren[] = {
&pmProcRpu0_g.node,
&pmProcRpu1_g.node,
};
static PmNode* pmFpdChildren[] = {
&pmPowerIslandApu_g.node,
&pmApll_g.node,
&pmVpll_g.node,
&pmDpll_g.node,
&pmSlaveL2_g.slv.node,
&pmSlaveSata_g.node,
&pmSlaveGpu_g.node,
&pmSlaveGpuPP0_g.slv.node,
&pmSlaveGpuPP1_g.slv.node,
&pmSlaveGdma_g.node,
&pmSlaveDP_g.node,
&pmSlaveDdr_g.node,
&pmSlavePcie_g.node,
};
static PmNode* pmLpdChildren[] = {
&pmPowerIslandRpu_g.power.node,
&pmRpll_g.node,
&pmIOpll_g.node,
&pmSlaveOcm0_g.slv.node,
&pmSlaveOcm1_g.slv.node,
&pmSlaveOcm2_g.slv.node,
&pmSlaveOcm3_g.slv.node,
&pmSlaveTcm0A_g.sram.slv.node,
&pmSlaveTcm0B_g.sram.slv.node,
&pmSlaveTcm1A_g.sram.slv.node,
&pmSlaveTcm1B_g.sram.slv.node,
&pmSlaveUsb0_g.slv.node,
&pmSlaveUsb1_g.slv.node,
&pmSlaveTtc0_g.node,
&pmSlaveTtc1_g.node,
&pmSlaveTtc2_g.node,
&pmSlaveTtc3_g.node,
&pmSlaveSata_g.node,
&pmSlaveUart0_g.node,
&pmSlaveUart1_g.node,
&pmSlaveSpi0_g.node,
&pmSlaveSpi1_g.node,
&pmSlaveI2C0_g.node,
&pmSlaveI2C1_g.node,
&pmSlaveSD0_g.node,
&pmSlaveSD1_g.node,
&pmSlaveCan0_g.node,
&pmSlaveCan1_g.node,
&pmSlaveEth0_g.node,
&pmSlaveEth1_g.node,
&pmSlaveEth2_g.node,
&pmSlaveEth3_g.node,
&pmSlaveAdma_g.node,
&pmSlaveNand_g.node,
&pmSlaveQSpi_g.node,
&pmSlaveGpio_g.node,
&pmSlaveIpiApu_g.node,
&pmSlaveIpiRpu0_g.node,
&pmSlaveIpiRpu1_g.node,
&pmSlaveIpiPl0_g.node,
&pmSlaveIpiPl1_g.node,
&pmSlaveIpiPl2_g.node,
&pmSlaveIpiPl3_g.node,
&pmSlavePcap_g.node,
};
static PmNode* pmPldChildren[] = {
&pmSlaveVcu_g.slv.node,
&pmSlavePl_g.node,
};
/* Dummy consumption for the power domains/islands */
static u8 PmDomainPowers[] = {
DEFAULT_POWER_OFF,
DEFAULT_POWER_ON,
};
static u8 PmApuDomainPowers[] = {
DEFAULT_POWER_OFF,
DEFAULT_POWER_OFF,
};
static PmPowerClass pmPowerClassRpuIsland_g = {
.construct = NULL,
.forceDown = PmPowerForceDownRpu,
};
/*
* Power Island and Power Domain definitions
*
* We only define those islands and domains containing more than 1 node.
* For optimization reasons private power islands, such as APU0-island or
* USB0-island are modeled as a feature of the node itself and are therefore
* not described here.
*/
PmPowerIslandRpu pmPowerIslandRpu_g = {
.power = {
.node = {
.derived = &pmPowerIslandRpu_g,
.nodeId = NODE_RPU,
.class = &pmNodeClassPower_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_PWR_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmDomainPowers),
DEFINE_NODE_NAME("rpu"),
},
DEFINE_PM_POWER_CHILDREN(pmRpuChildren),
.class = &pmPowerClassRpuIsland_g,
.powerUp = PmPowerUpRpu,
.powerDown = PmPowerDownRpu,
.pwrDnLatency = PM_POWER_ISLAND_LATENCY,
.pwrUpLatency = PM_POWER_ISLAND_LATENCY,
.forcePerms = 0U,
},
.deps = 0U,
};
/*
* @Note: The APU power island does not physically exist, therefore it has
* no operations and no latencies. The individual APU cores have their own
* dedicated power islands, the transition latency is hence accounted for
* in PmProc
*/
PmPower pmPowerIslandApu_g = {
.node = {
.derived = &pmPowerIslandApu_g,
.nodeId = NODE_APU,
.class = &pmNodeClassPower_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_PWR_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmApuDomainPowers),
DEFINE_NODE_NAME("apu"),
},
DEFINE_PM_POWER_CHILDREN(pmApuChildren),
.class = NULL,
.powerUp = NULL,
.powerDown = NULL,
.pwrDnLatency = 0,
.pwrUpLatency = 0,
.forcePerms = 0U,
};
PmPowerDomain pmPowerDomainFpd_g = {
.power = {
.node = {
.derived = &pmPowerDomainFpd_g,
.nodeId = NODE_FPD,
.class = &pmNodeClassPower_g,
.parent = NULL,
.clocks = NULL,
.currState = PM_PWR_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmDomainPowers),
DEFINE_NODE_NAME("fpd"),
},
DEFINE_PM_POWER_CHILDREN(pmFpdChildren),
.class = &pmPowerClassDomain_g,
.powerUp = PmPowerUpFpd,
.powerDown = PmPowerDownFpd,
.pwrDnLatency = PM_POWER_DOMAIN_LATENCY,
.pwrUpLatency = PM_POWER_DOMAIN_LATENCY,
.forcePerms = 0U,
.useCount = 0U,
},
.supplyCheckHook = PmFpdPowerSupplyCheck,
.supplyCheckHookId = XPBR_SERV_EXT_FPD_SUPPLYCHECK,
};
PmPowerDomain pmPowerDomainLpd_g = {
.power = {
.node = {
.derived = &pmPowerDomainLpd_g,
.nodeId = NODE_LPD,
.class = &pmNodeClassPower_g,
.parent = NULL,
.clocks = NULL,
.currState = PM_PWR_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmDomainPowers),
DEFINE_NODE_NAME("lpd"),
},
DEFINE_PM_POWER_CHILDREN(pmLpdChildren),
.class = &pmPowerClassDomain_g,
.powerUp = NULL,
.powerDown = PmPowerDownLpd,
.pwrDnLatency = PM_POWER_DOMAIN_LATENCY,
.pwrUpLatency = PM_POWER_DOMAIN_LATENCY,
.forcePerms = 0U,
.useCount = 0U,
},
.supplyCheckHook = NULL,
.supplyCheckHookId = XPBR_SERV_EXT_TBL_BASE,
};
PmPowerDomain pmPowerDomainPld_g = {
.power = {
.node = {
.derived = &pmPowerDomainPld_g,
.nodeId = NODE_PLD,
.class = &pmNodeClassPower_g,
.parent = NULL,
.clocks = NULL,
.currState = PM_PWR_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmDomainPowers),
DEFINE_NODE_NAME("pld"),
},
DEFINE_PM_POWER_CHILDREN(pmPldChildren),
.class = &pmPowerClassDomain_g,
.powerUp = PmPowerUpPld,
.powerDown = PmPowerDownPld,
.pwrDnLatency = PM_POWER_DOMAIN_LATENCY,
.pwrUpLatency = PM_POWER_DOMAIN_LATENCY,
.forcePerms = 0U,
.useCount = 0U,
},
.supplyCheckHook = PmPldPowerSupplyCheck,
.supplyCheckHookId = XPBR_SERV_EXT_PLD_SUPPLYCHECK,
};
/**
* PmPowerUpdateLatencyMargin() - Update latency margin for the power node
* @power Power node to update
*/
static void PmPowerUpdateLatencyMargin(PmPower* const power)
{
u32 i;
/* Find minimum latency margin of all children */
power->node.latencyMarg = MAX_LATENCY;
for (i = 0U; i < power->childCnt; i++) {
if (power->children[i]->latencyMarg < power->node.latencyMarg) {
power->node.latencyMarg = power->children[i]->latencyMarg;
}
}
if ((power->pwrDnLatency + power->pwrUpLatency) < power->node.latencyMarg) {
power->node.latencyMarg -= power->pwrDnLatency + power->pwrUpLatency;
} else {
power->node.latencyMarg = 0U;
}
}
/**
* PmPowerDownCond() - Power the node down if conditions are satisfied
* @power Power node to conditionally power down
*
* @note Conditions for powering down the node
* 1) Use count is zero (power node is unused)
* 2) Latency requirements of the children allow the power down
*/
static void PmPowerDownCond(PmPower* const power)
{
if (0U == power->useCount) {
PmPowerUpdateLatencyMargin(power);
if (power->node.latencyMarg > 0U) {
if (XST_SUCCESS != PmPowerDown(power)) {
PmWarn("Error in power down for %s\r\n", power->node.name);
}
}
}
}
/**
* PmPowerUpdateLatencyReq() - Child updates its power parent about latency req
* @node Child node whose latency requirement have changed
*
* @return If the change of the latency requirement caused the power up of
* the power parent, the status of performing power up operation
* is returned. Otherwise, XST_SUCCESS.
*/
s32 PmPowerUpdateLatencyReq(const PmNode* const node)
{
s32 status = XST_SUCCESS;
PmPower* power = node->parent;
if (PM_PWR_STATE_ON == power->node.currState) {
/* Try to power down the node if all conditions are ok */
PmPowerDownCond(power);
if (PM_PWR_STATE_OFF == power->node.currState) {
if (NULL != power->node.parent) {
PmPowerReleaseParent(&power->node);
}
}
goto done;
}
/* Power is down, check if latency requirements trigger the power up */
if (node->latencyMarg < (power->pwrDnLatency + power->pwrUpLatency)) {
power->node.latencyMarg = 0U;
if (NULL != power->node.parent) {
status = PmPowerRequestParent(&power->node);
if (XST_SUCCESS != status) {
goto done;
}
}
status = PmPowerUp(power);
}
done:
return status;
}
/**
* PmPowerRequestInt() - Used internally to request a power node
* @power Requested power node
*
* @return XST_SUCCESS if power is already powered up, otherwise status
* of powering up.
*/
static s32 PmPowerRequestInt(PmPower* const power)
{
s32 status = XST_SUCCESS;
if (PM_PWR_STATE_OFF == power->node.currState) {
status = PmPowerUp(power);
}
if (XST_SUCCESS == status) {
power->useCount++;
}
return status;
}
/**
* PmPowerRequest() - Request for power to be powered up
* @power Requested power
*
* @return XST_SUCCESS if power is already powered up, otherwise status
* of powering up.
*/
static s32 PmPowerRequest(PmPower* const power)
{
s32 status = XST_SUCCESS;
if (NULL != power->node.parent) {
if (0U == (power->node.flags & NODE_LOCKED_POWER_FLAG)) {
status = PmPowerRequestInt(power->node.parent);
if (XST_SUCCESS != status) {
goto done;
}
power->node.flags |= NODE_LOCKED_POWER_FLAG;
}
}
status = PmPowerRequestInt(power);
done:
return status;
}
/**
* PmPowerReleaseInt() - Used internally to release the power node
* @power Power node
*/
static void PmPowerReleaseInt(PmPower* const power)
{
if (power->useCount > 0U) {
power->useCount--;
PmPowerDownCond(power);
}
}
/**
* PmPowerRelease() - Release the power
* @power Released power
*/
static void PmPowerRelease(PmPower* const power)
{
PmPowerReleaseInt(power);
if (NULL != power->node.parent) {
if (0U != (power->node.flags & NODE_LOCKED_POWER_FLAG)) {
PmPowerReleaseInt(power->node.parent);
power->node.flags &= ~NODE_LOCKED_POWER_FLAG;
}
}
}
/**
* PmPowerRequestParent() - Request power parent to be powered up
* @node Node which requests its power parent
*
* @return XST_SUCCESS if power parent is already up, status of powering up
* otherwise.
*/
s32 PmPowerRequestParent(PmNode* const node)
{
s32 status = XST_SUCCESS;
if (0U == (NODE_LOCKED_POWER_FLAG & node->flags)) {
status = PmPowerRequest(node->parent);
if (XST_SUCCESS == status) {
node->flags |= NODE_LOCKED_POWER_FLAG;
}
}
return status;
}
/**
* PmPowerReleaseParent() - Release power parent
* @node Node which releases its power parent
*/
void PmPowerReleaseParent(PmNode* const node)
{
if (0U != (NODE_LOCKED_POWER_FLAG & node->flags)) {
node->flags &= ~NODE_LOCKED_POWER_FLAG;
PmPowerRelease(node->parent);
}
}
/**
* PmPowerReleaseRpu() - Release RPU (TCM doesn't depend on RPU anymore)
* @tcm TCM which releases RPU
*/
void PmPowerReleaseRpu(PmSlaveTcm* const tcm)
{
pmPowerIslandRpu_g.deps &= ~tcm->id;
/* If no other TCM depends on RPU release it */
if (0U == pmPowerIslandRpu_g.deps) {
PmPowerRelease(&pmPowerIslandRpu_g.power);
}
}
/**
* PmPowerRequestRpu() - Request RPU (TCM now depends on RPU)
* @tcm TCM which requests RPU
*
* @return XST_SUCCESS or error code if powering up of RPU failed
*/
s32 PmPowerRequestRpu(PmSlaveTcm* const tcm)
{
s32 status = XST_SUCCESS;
u32 resetMask = CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK |
CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK;
u32 reset;
if (0U != pmPowerIslandRpu_g.deps) {
goto done;
}
/* Ensure that the RPU island is ON */
status = PmPowerRequest(&pmPowerIslandRpu_g.power);
if (XST_SUCCESS != status) {
goto ret;
}
/*
* Ensure the comparators are in clean state when rpu comes up
*/
XPfw_RMW32(RPU_RPU_ERR_INJ,
RPU_RPU_ERR_INJ_DCCMINP2_MASK | RPU_RPU_ERR_INJ_DCCMINP_MASK,
0x0);
reset = XPfw_Read32(CRL_APB_RST_LPD_TOP);
/* If PGE and AMBA resets are asserted, deassert them now */
if (0U != (reset & resetMask)) {
XPfw_Write32(CRL_APB_RST_LPD_TOP, reset & ~resetMask);
}
/* If RPU0 reset is asserted, halt the core and deassert its reset */
if (0U != (reset & CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK)) {
XPfw_RMW32(RPU_RPU_0_CFG,
RPU_RPU_0_CFG_NCPUHALT_MASK,
~RPU_RPU_0_CFG_NCPUHALT_MASK);
XPfw_RMW32(CRL_APB_RST_LPD_TOP,
CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
~CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
}
/* If RPU1 reset is asserted, halt the core and deassert its reset */
if (0U != (reset & CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK)) {
XPfw_RMW32(RPU_RPU_1_CFG,
RPU_RPU_1_CFG_NCPUHALT_MASK,
~RPU_RPU_1_CFG_NCPUHALT_MASK);
XPfw_RMW32(CRL_APB_RST_LPD_TOP,
CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
~CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
}
done:
pmPowerIslandRpu_g.deps |= tcm->id;
ret:
return status;
}
/**
* PmPowerClearConfig() - Clear configuration of the power node
* @powerNode Pointer to the power node
*/
static void PmPowerClearConfig(PmNode* const powerNode)
{
PmPower* const power = (PmPower*)powerNode->derived;
power->forcePerms = 0U;
power->useCount = 0U;
}
/**
* PmPowerConstruct() - Constructor method for the power node
* @powerNode Power node to construct
*/
static void PmPowerConstruct(PmNode* const powerNode)
{
PmPower* const power = (PmPower*)powerNode->derived;
if ((NULL != power->class) && (NULL != power->class->construct)) {
power->class->construct(power);
}
}
/**
* PmPowerGetWakeUpLatency() - Get wake-up latency of the power node
* @node Power node whose wake-up latency should be get
* @lat Pointer to the location where the latency value should be stored
*
* @return XST_SUCCESS always
*/
static s32 PmPowerGetWakeUpLatency(const PmNode* const node, u32* const lat)
{
PmPower* const power = (PmPower*)node->derived;
PmPower* parent = power->node.parent;
*lat = 0U;
if (PM_PWR_STATE_ON == node->currState) {
goto done;
}
*lat = power->pwrUpLatency;
/* Account latencies of powered down parents (if a parent is down) */
while (NULL != parent) {
if (PM_PWR_STATE_ON == parent->node.currState) {
break;
}
*lat += parent->pwrUpLatency;
parent = parent->node.parent;
}
done:
return XST_SUCCESS;
}
/**
* PmPowerGetPowerData() - Get power consumption of the node
* @powerNode Power node whose power consumption should be get
* @data Pointer to the location where the power data should be stored
*
* @return XST_SUCCESS if power consumption data is stored in *data
* XST_NO_FEATURE otherwise
* @note Power consumption of power node is a sum of consumptions of the
* children.
*/
static s32 PmPowerGetPowerData(const PmNode* const powerNode, u32* const data)
{
PmNode* node;
u32 val = 0U;
s32 status = XST_NO_FEATURE;
*data = 0U;
if (PM_PWR_STATE_OFF == powerNode->currState) {
status = XST_SUCCESS;
goto done;
}
PmPowerDfsBegin((PmPower*)powerNode->derived);
node = PmPowerDfsGetNext();
while (NULL != node) {
if (NODE_IS_POWER(node)) {
status = PmNodeGetPowerInfo(node, &val);
} else {
if (NULL != node->class->getPowerData) {
status = node->class->getPowerData(node, &val);
} else {
status = XST_NO_FEATURE;
}
}
if (XST_SUCCESS != status) {
goto done;
}
*data += val;
node = PmPowerDfsGetNext();
}
done:
return status;
}
/**
* PmPowerForceDown() - Force down the power node and all of its children
* @powerNode Power node to force down
*
* @return Status of performing force power down
*/
static s32 PmPowerForceDown(PmNode* const powerNode)
{
PmNode* node;
PmPower* const power = (PmPower*)powerNode->derived;
s32 status = XST_FAILURE;
PmPowerDfsBegin(power);
node = PmPowerDfsGetNext();
while (NULL != node) {
if (NODE_IS_POWER(node)) {
status = PmPowerDown((PmPower*)node->derived);
} else {
status = PmNodeForceDown(node);
}
if (XST_SUCCESS != status) {
goto done;
}
node = PmPowerDfsGetNext();
}
if ((NULL != power->class) && (NULL != power->class->forceDown)) {
power->class->forceDown(power);
}
done:
return status;
}
/**
* PmPowerInit() - Initialize power node
* @powerNode Power node to initialize
*
* @return Status of initializing the node
*/
static s32 PmPowerInit(PmNode* const powerNode)
{
s32 status = XST_SUCCESS;
if (PM_PWR_STATE_OFF == powerNode->currState) {
goto done;
}
if (NULL != powerNode->parent) {
status = PmPowerRequestParent(powerNode);
if (XST_SUCCESS != status) {
goto done;
}
}
if (NULL != powerNode->clocks) {
status = PmClockRequest(powerNode);
}
done:
return status;
}
/**
* PmPowerIsUsable() - Check if power node could be used by current config
* @powerNode Power node to check
*
* @return True if power node is usable, false otherwise
*/
static bool PmPowerIsUsable(PmNode* const powerNode)
{
PmNode* node;
bool usable = false;
PmPowerDfsBegin((PmPower*)powerNode->derived);
node = PmPowerDfsGetNext();
while (NULL != node) {
if (!NODE_IS_POWER(node)) {
if (NULL != node->class->isUsable) {
usable = node->class->isUsable(node);
if (true == usable) {
goto done;
}
}
}
node = PmPowerDfsGetNext();
}
done:
return usable;
}
/**
* PmPowerGetPerms() - Get permissions to control node's clocks
* @powerNode Power node
*
* @return ORed IPI masks of permissible masters
*
* @note Permissions are determined based on permissions to do the same
* for non-power children nodes of the target power node. If at
* least one child's clocks no one has permission to control, this
* stands for the power parent (this node) as well.
*/
static u32 PmPowerGetPerms(const PmNode* const powerNode)
{
const PmNode* node;
u32 perms = 0U;
u32 node_perms;
PmPowerDfsBegin((PmPower*)powerNode->derived);
node = PmPowerDfsGetNext();
while (NULL != node) {
if (!NODE_IS_POWER(node)) {
if (NULL == node->class->getPerms) {
perms = 0U;
goto done;
}
node_perms = node->class->getPerms(node);
if (0U == node_perms) {
perms = 0U;
goto done;
}
perms |= node_perms;
}
node = PmPowerDfsGetNext();
}
done:
return perms;
}
/* Collection of power nodes */
static PmNode* pmNodePowerBucket[] = {
&pmPowerIslandApu_g.node,
&pmPowerIslandRpu_g.power.node,
&pmPowerDomainFpd_g.power.node,
&pmPowerDomainPld_g.power.node,
&pmPowerDomainLpd_g.power.node,
};
PmNodeClass pmNodeClassPower_g = {
DEFINE_NODE_BUCKET(pmNodePowerBucket),
.id = NODE_CLASS_POWER,
.clearConfig = PmPowerClearConfig,
.construct = PmPowerConstruct,
.getWakeUpLatency = PmPowerGetWakeUpLatency,
.getPowerData = PmPowerGetPowerData,
.forceDown = PmPowerForceDown,
.init = PmPowerInit,
.isUsable = PmPowerIsUsable,
.getPerms = PmPowerGetPerms,
};
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/rfdc_v8_0/src/xrfdc_clock.c
/******************************************************************************
* Copyright (C) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrfdc_clock.c
* @addtogroup rfdc_v8_0
* @{
*
* Contains the interface functions of the Mixer Settings in XRFdc driver.
* See xrfdc.h for a detailed description of the device and driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 6.0 cog 02/17/19 Initial release.
* cog 03/12/19 Invert clock detection bits to support IP change.
* cog 03/12/19 Fix bug where incorrect FS, RefClk and were output
* divider were being returned.
* cog 04/09/19 Discriminate between Gen 3 IP and lower for checking
* if internal PLL is enabled.
* cog 04/09/19 Fixed issue where tile was not autostarting after PLL
* rate change.
* 7.0 cog 05/13/19 Formatting changes.
* cog 08/02/19 Formatting changes and added a MACRO for the IP generation.
* cog 09/18/19 XRFdc_GetClockSourceAPI must handle GEN 3 devices differently
* to previous generations.
* cog 09/18/19 Account for different PLL settings for GEN 3 devices.
* cog 09/18/19 Fixed issues with clock distribution functionallity.
* cog 10/02/19 Updated PLL VCO ranges and reset divide bits while bypassing
* PLL output divider.
* cog 10/02/19 Moved new external clock output divider functionallity from
* the clock distribution to XRFdc_DynamicPLLConfig() API.
* cog 10/02/19 Refactor of XRFdc_GetClkDistribution() API.
* 7.1 cog 12/20/19 Metal log messages are now more descriptive.
* cog 01/08/20 Changed clocking checks to allow ADC distribution to all
* ADC tiles.
* cog 01/29/20 Fixed metal log typos.
* 8.0 cog 02/10/20 Updated addtogroup.
* cog 03/20/20 Updated PowerState masks for Gen3.
* cog 04/06/20 Fix GCC warnings.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xrfdc.h"
/************************** Constant Definitions *****************************/
static u32 PllTuningMatrix[8][4][2] = {
{ { 0x7F8A, 0x3FFF }, { 0x7F9C, 0x3FFF }, { 0x7FE2, 0x3FFF } },
{ { 0x7FE9, 0xFFFF }, { 0x7F8E, 0xFFFF }, { 0x7F9C, 0xFFFF } },
{ { 0x7F95, 0xFFFF }, { 0x7F8E, 0xFFFF }, { 0x7F9A, 0xFFFF }, { 0x7F8C, 0xFFFF } },
{ { 0x7F95, 0x3FFF }, { 0x7FEE, 0x3FFF }, { 0x7F9A, 0xFFFF }, { 0x7F9C, 0xFFFF } },
{ { 0x7F95, 0x3FFF }, { 0x7FEE, 0x3FFF }, { 0x7F9A, 0xFFFF }, { 0x7F9C, 0xFFFF } },
{ { 0x7F95, 0xFFFF }, { 0x7F8E, 0xFFFF }, { 0x7FEA, 0xFFFF }, { 0x7F9C, 0xFFFF } },
{ { 0x7FE9, 0xFFFF }, { 0x7F8E, 0xFFFF }, { 0x7F9A, 0xFFFF }, { 0x7F9C, 0xFFFF } },
{ { 0x7FEC, 0xFFFF }, { 0x7FEE, 0x3FFF }, { 0x7F9C, 0xFFFF } }
};
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
static u32 XRFdc_CheckClkDistValid(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr);
static u32 XRFdc_SetPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, double RefClkFreq, double SamplingRate);
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* This function is used to set the clock settings
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type indicates ADC/DAC.
* @param Tile_Id indicates Tile number (0-3).
* @param SettingsPtr pointer to set the clock settings
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if no valid distribution found.
*
******************************************************************************/
static u32 XRFdc_SetTileClkSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, XRFdc_Tile_Clock_Settings *SettingsPtr)
{
u32 Status;
u32 BaseAddr;
u16 PLLSource;
u16 NetworkCtrlReg;
u16 DistCtrlReg;
u16 PLLRefDivReg;
u32 TileIndex;
u32 PowerStateMaskReg;
TileIndex = (Type == XRFDC_DAC_TILE) ? (XRFDC_CLK_DST_TILE_228 - Tile_Id) : (XRFDC_CLK_DST_TILE_224 - Tile_Id);
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_INFO, "\n Requested Tile (%s %u) not available - Skipping in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_SUCCESS;
goto RETURN_PATH;
}
if (SettingsPtr->DistributedClock > XRFDC_DIST_OUT_OUTDIV) {
metal_log(METAL_LOG_ERROR, "\n Invalid Parameter Value for Distribution Out (%u) for %s %u in %s\r\n",
SettingsPtr->DistributedClock, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (SettingsPtr->PLLEnable > XRFDC_ENABLED) {
metal_log(METAL_LOG_ERROR, "\n Invalid Parameter Value for PLLEnable (%u) for %s %u %s\r\n",
SettingsPtr->PLLEnable, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((SettingsPtr->SourceTile != TileIndex) && (SettingsPtr->DistributedClock != XRFDC_DIST_OUT_NONE)) {
metal_log(METAL_LOG_ERROR, "\n Cannot Redistribute Clock in (%s %u is not a source tile)%s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
/*configure PLL & divider or just divider*/
if (SettingsPtr->PLLEnable == XRFDC_ENABLED) {
PLLSource = XRFDC_INTERNAL_PLL_CLK;
Status = XRFdc_DynamicPLLConfig(InstancePtr, Type, Tile_Id, PLLSource,
SettingsPtr->PLLSettings.RefClkFreq,
SettingsPtr->PLLSettings.SampleRate);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Could not set up PLL for %s %u %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
}
} else {
PLLSource = XRFDC_EXTERNAL_CLK;
Status = XRFdc_DynamicPLLConfig(InstancePtr, Type, Tile_Id, PLLSource,
SettingsPtr->PLLSettings.RefClkFreq,
SettingsPtr->PLLSettings.SampleRate);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Could not set up external clocking for %s %u %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
}
}
(void)XRFdc_GetPLLConfig(InstancePtr, Type, Tile_Id, &(SettingsPtr->PLLSettings));
SettingsPtr->DivisionFactor = SettingsPtr->PLLSettings.OutputDivider;
DistCtrlReg = 0;
PLLRefDivReg = 0;
NetworkCtrlReg = 0;
if (SettingsPtr->SourceTile == TileIndex) {
if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_NONE) {
if (SettingsPtr->PLLEnable == XRFDC_DISABLED) {
PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
if (SettingsPtr->DivisionFactor < 2) {
/*
T1 from Self
No PLL
Do Not Use PLL Output Divider
Do Not Distribute
*/
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_LOCAL;
DistCtrlReg |= XRFDC_DIST_CTRL_CLK_T1_SRC_LOCAL;
PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_SRC;
} else {
/*
T1 from Self
No PLL
Use PLL Output Divider
Do Not Distribute
*/
PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC;
}
} else {
/*
T1 from Self
PLL
Use PLL Output Divider
Do Not Distribute
*/
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_PLL;
PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL;
}
} else {
if (SettingsPtr->PLLEnable == XRFDC_DISABLED) {
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
if (SettingsPtr->DivisionFactor < 2) {
/*
T1 From Distribution (RX back)
No PLL
Do Not Use PLL Output Divider
Send to Distribution
*/
PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1;
DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL;
PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_SRC;
} else if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_RX) {
/*
RX Back From Distribution
No PLL
Use PLL Output Divider
Send to Distribution
*/
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST;
DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL;
PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC;
} else {
/*
PLL Output Divider Back From Distribution
No PLL
Use PLL Output Divider
Send to Distribution
*/
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST;
DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL;
PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC;
}
} else {
/*
RX Back From Distribution
PLL
Use PLL Output Divider
Send to Distribution
*/
if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_RX) {
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_DIST;
DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL;
PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL;
} else {
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_PLL;
PLLRefDivReg |= XRFDC_PLLOPDIV_INPUT_DIST_LOCAL;
DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1;
DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL;
PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL;
}
}
}
} else {
if (SettingsPtr->PLLEnable == XRFDC_DISABLED) {
PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
if (SettingsPtr->DivisionFactor > 1) {
/*
Source From Distribution
No PLL
Use PLL Output Divider
Do Not Distribute
*/
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST;
DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV;
} else {
/*
Source From Distribution
No PLL
Do Not Use PLL Output Divider
Do Not Distribute
*/
NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1;
PowerStateMaskReg = ((Type == XRFDC_ADC_TILE) ? XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV :
XRFDC_HSCOM_PWR_STATS_DIST_EXT);
}
} else {
/*
Source From Distribution
PLL
Use PLL Output Divider
Do Not Distribute
*/
PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_DIST;
DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_PLL;
}
}
/*Write to Registers*/
if (Type == XRFDC_ADC_TILE) {
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id);
} else {
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id);
}
BaseAddr += XRFDC_HSCOM_ADDR;
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_HSCOM_CLK_DSTR_OFFSET, XRFDC_HSCOM_CLK_DSTR_MASK_ALT, DistCtrlReg);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CLK_NETWORK_CTRL1, XRFDC_HSCOM_NETWORK_CTRL1_MASK, NetworkCtrlReg);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_PLL_REFDIV, XRFDC_PLL_REFDIV_MASK, PLLRefDivReg);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET, PowerStateMaskReg);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to check the distribution chosen is valid
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param DistributionSettingsPtr pointer to the distribution settings struct
*
* @return
* - XRFDC_SUCCESS if valid.
* - XRFDC_FAILURE if not valid.
*
******************************************************************************/
static u32 XRFdc_CheckClkDistValid(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr)
{
u32 Status;
u8 CurrentTile;
u8 *Source;
u8 Sources[8] = { DistributionSettingsPtr->DAC[3].SourceTile, DistributionSettingsPtr->DAC[2].SourceTile,
DistributionSettingsPtr->DAC[1].SourceTile, DistributionSettingsPtr->DAC[0].SourceTile,
DistributionSettingsPtr->ADC[3].SourceTile, DistributionSettingsPtr->ADC[2].SourceTile,
DistributionSettingsPtr->ADC[1].SourceTile, DistributionSettingsPtr->ADC[0].SourceTile };
u8 LowBoundary;
u16 EFuse;
XRFdc_Distribution *DistributionPtr;
/*init for first distribution*/
DistributionPtr = DistributionSettingsPtr->DistributionStatus;
Source = Sources;
LowBoundary = DistributionSettingsPtr->DAC[3].SourceTile;
DistributionPtr->DistributionSource = DistributionSettingsPtr->DAC[3].SourceTile;
DistributionPtr->Enabled = XRFDC_ENABLED;
DistributionPtr->LowerBound = 0;
for (CurrentTile = 0; CurrentTile < XRFDC_DIST_MAX; CurrentTile++, Source++) {
if (*Source >= XRFDC_DIST_MAX) {
Status = XRFDC_FAILURE; /*out of range*/
metal_log(METAL_LOG_ERROR, "\n Invalid Source value in %s - Out of Range\r\n", __func__);
goto RETURN_PATH;
}
if (*Source < LowBoundary) {
Status = XRFDC_FAILURE; /*SW: no hopovers*/
metal_log(METAL_LOG_ERROR, "\n Hopping Over Tiles Not Allowed in %s\r\n", __func__);
goto RETURN_PATH;
}
if (Sources[*Source] != *Source) { /*SW: check source is a distributer*/
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Sourcing from Tile that is not Distributing in %s\r\n",
__func__);
goto RETURN_PATH;
}
if ((CurrentTile < XRFDC_CLK_DST_TILE_227) &&
(*Source > XRFDC_CLK_DST_TILE_228)) { /*Cut between ADC0 MUX8 && DAC3 STH*/
metal_log(METAL_LOG_ERROR, "\n DAC Cannot Source from ADC in %s\r\n", __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (CurrentTile < XRFDC_CLK_DST_TILE_227) { /*DAC*/
EFuse = XRFdc_ReadReg16(InstancePtr,
XRFDC_DRP_BASE(XRFDC_DAC_TILE, CurrentTile) + XRFDC_HSCOM_ADDR,
XRFDC_HSCOM_EFUSE_2_OFFSET);
} else { /*ADC*/
EFuse = XRFdc_ReadReg16(InstancePtr,
XRFDC_DRP_BASE(XRFDC_ADC_TILE, (CurrentTile - XRFDC_CLK_DST_TILE_227)) +
XRFDC_HSCOM_ADDR,
XRFDC_HSCOM_EFUSE_2_OFFSET);
}
if ((DistributionSettingsPtr->DAC[0].SourceTile != DistributionSettingsPtr->DAC[1].SourceTile) ||
(DistributionSettingsPtr->DAC[0].SourceTile != DistributionSettingsPtr->DAC[2].SourceTile) ||
(DistributionSettingsPtr->DAC[0].SourceTile != DistributionSettingsPtr->DAC[3].SourceTile) ||
(DistributionSettingsPtr->DAC[0].SourceTile != DistributionSettingsPtr->ADC[3].SourceTile) ||
(DistributionSettingsPtr->DAC[0].SourceTile != DistributionSettingsPtr->ADC[2].SourceTile) ||
(DistributionSettingsPtr->DAC[0].SourceTile != DistributionSettingsPtr->ADC[1].SourceTile) ||
(DistributionSettingsPtr->DAC[0].SourceTile != DistributionSettingsPtr->ADC[0].SourceTile) ||
(DistributionSettingsPtr->DAC[0].PLLEnable != XRFDC_ENABLED) ||
(DistributionSettingsPtr->DAC[1].PLLEnable != XRFDC_ENABLED) ||
(DistributionSettingsPtr->DAC[2].PLLEnable != XRFDC_ENABLED) ||
(DistributionSettingsPtr->DAC[3].PLLEnable != XRFDC_ENABLED) ||
(DistributionSettingsPtr->ADC[0].PLLEnable != XRFDC_ENABLED) ||
(DistributionSettingsPtr->ADC[1].PLLEnable != XRFDC_ENABLED) ||
(DistributionSettingsPtr->ADC[2].PLLEnable != XRFDC_ENABLED) ||
(DistributionSettingsPtr->ADC[3].PLLEnable != XRFDC_ENABLED)) { /*special case that is allowed.*/
if (EFuse & XRFDC_PREMIUMCTRL_CLKDIST) {
if ((CurrentTile > XRFDC_CLK_DST_TILE_226) &&
(*Source < XRFDC_CLK_DST_TILE_227)) { /*E: no dist past adc2*/
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid Configuration in %s\r\n", __func__);
goto RETURN_PATH;
}
}
}
if (*Source != DistributionPtr->DistributionSource) { /*i.e. if new distribution*/
DistributionPtr->UpperBound = CurrentTile - 1;
DistributionPtr++;
DistributionPtr->Enabled = XRFDC_ENABLED;
LowBoundary = *Source;
DistributionPtr->DistributionSource = *Source;
DistributionPtr->LowerBound = CurrentTile;
}
}
DistributionPtr->UpperBound = CurrentTile - 1;
Status = XRFDC_SUCCESS;
RETURN_PATH:
if (Status == XRFDC_FAILURE) {
memset(DistributionSettingsPtr, 0, sizeof(XRFdc_Distribution_Settings));
}
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to wait for a tile to reach a given state.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type represents ADC or DAC.
* @param Tile_Id Valid values are 0-3.
* @param State represents the state which the tile must reach.
*
* @return
* - XRFDC_SUCCESS if valid.
* - XRFDC_FAILURE if not valid.
*
******************************************************************************/
static u32 XRFdc_WaitForState(XRFdc *InstancePtr, u32 Type, u32 Tile, u32 State)
{
u32 DelayCount;
u32 TileState;
TileState = XRFdc_RDReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile), 0xC, 0xF);
DelayCount = 0;
while (TileState < State) {
if (DelayCount == 10000) {
metal_log(METAL_LOG_ERROR, "\n timeout error in %s[%u] going to state %u in %s\r\n",
(Type ? "DAC" : "ADC"), Tile, State, __func__);
return XRFDC_FAILURE;
} else {
/* Wait for 0.1 msec */
#ifdef __BAREMETAL__
usleep(100);
#else
metal_sleep_usec(100);
#endif
DelayCount++;
TileState = XRFdc_RDReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile), 0xC, 0xF);
}
}
return XRFDC_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function is used to start the distribution tiles
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param DistributionSettingsPtr pointer to the distribution settings struct
*
* @return
* - XRFDC_SUCCESS if valid.
* - XRFDC_FAILURE if not valid.
*
******************************************************************************/
static u32 XRFdc_StartUpDist(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr)
{
u32 Status;
u32 GlobalTile;
u32 Type;
u32 Tile;
u32 DistributionCount;
XRFdc_Distribution *Distribution;
u32 i;
u32 enables[8];
u32 BaseAddr;
Status = XRFDC_SUCCESS;
for (Distribution = DistributionSettingsPtr->DistributionStatus, DistributionCount = 0;
DistributionCount < XRFDC_DIST_MAX; Distribution++, DistributionCount++) {
if (Distribution->Enabled == XRFDC_DISABLED) {
break;
}
/*Fully Start Source Tile*/
if ((Distribution->DistributionSource) < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - Distribution->DistributionSource;
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile);
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - Distribution->DistributionSource;
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile);
}
BaseAddr += XRFDC_HSCOM_ADDR;
enables[DistributionCount] = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CLK_NETWORK_CTRL1, 0x3);
}
/*DAC0 Must reach state 4 in Startup FSM*/
for (i = 0; i < 4; i++) {
XRFdc_ClrSetReg(InstancePtr, XRFDC_CTRL_STS_BASE(XRFDC_DAC_TILE, i), 8, 0x10f, 0x10F);
XRFdc_ClrSetReg(InstancePtr, XRFDC_CTRL_STS_BASE(XRFDC_ADC_TILE, i), 8, 0x10f, 0x10F);
XRFdc_ClrSetReg(InstancePtr, XRFDC_CTRL_STS_BASE(XRFDC_DAC_TILE, i), 4, 0x1, 1);
XRFdc_ClrSetReg(InstancePtr, XRFDC_CTRL_STS_BASE(XRFDC_ADC_TILE, i), 4, 0x1, 1);
}
for (Distribution = DistributionSettingsPtr->DistributionStatus, DistributionCount = 0;
DistributionCount < XRFDC_DIST_MAX; Distribution++, DistributionCount++) {
if (Distribution->Enabled == XRFDC_DISABLED) {
break;
}
/*Fully Start Source Tile*/
if ((Distribution->DistributionSource) < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - Distribution->DistributionSource;
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile);
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - Distribution->DistributionSource;
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile);
}
BaseAddr += XRFDC_HSCOM_ADDR;
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile);
if (Status != XRFDC_SUCCESS) {
continue;
}
Status |= XRFdc_WaitForState(InstancePtr, Type, Tile, 7);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CLK_NETWORK_CTRL1, 0x3, enables[DistributionCount]);
Status = XRFdc_WaitForState(InstancePtr, Type, Tile, 0xF);
for (GlobalTile = Distribution->LowerBound; GlobalTile <= Distribution->UpperBound; GlobalTile++) {
if (GlobalTile < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - GlobalTile;
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - GlobalTile;
}
Status |= XRFdc_WaitForState(InstancePtr, Type, Tile, 0xF);
}
}
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to set the clock distribution
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param DistributionSettingsPtr pointer to the distribution settings struct
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if could not set distribution.
*
******************************************************************************/
u32 XRFdc_SetClkDistribution(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr)
{
u32 Status;
u8 DelayLeft;
u8 DelayRight;
s8 Delay;
s8 ClkDetItr;
u8 *Delays[8];
u8 DelayOutSourceLeft;
u8 DelayOutSourceRight;
XRFdc_Distribution *Distribution;
u8 DistributionCount;
u16 Reg;
u16 ClkDetectReg;
u8 FeedBackForInputRight = 0;
u8 FeedBackForInputLeft = 0;
u32 Tile;
u32 Type;
XRFdc_Tile_Clock_Settings *SettingsPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(DistributionSettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested fuctionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckClkDistValid(InstancePtr, DistributionSettingsPtr);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Invalid Distribution in %s\r\n", __func__);
goto RETURN_PATH;
}
Delays[0] = &DistributionSettingsPtr->DAC[3].Delay;
Delays[1] = &DistributionSettingsPtr->DAC[2].Delay;
Delays[2] = &DistributionSettingsPtr->DAC[1].Delay;
Delays[3] = &DistributionSettingsPtr->DAC[0].Delay;
Delays[4] = &DistributionSettingsPtr->ADC[3].Delay;
Delays[5] = &DistributionSettingsPtr->ADC[2].Delay;
Delays[6] = &DistributionSettingsPtr->ADC[1].Delay;
Delays[7] = &DistributionSettingsPtr->ADC[0].Delay;
Status = XRFdc_Shutdown(InstancePtr, XRFDC_ADC_TILE, -1);
if (Status != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
Status = XRFdc_Shutdown(InstancePtr, XRFDC_DAC_TILE, -1);
if (Status != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
for (Distribution = DistributionSettingsPtr->DistributionStatus, DistributionCount = 0;
DistributionCount < XRFDC_DIST_MAX; Distribution++, DistributionCount++) {
if (Distribution->Enabled == XRFDC_DISABLED) {
break;
}
DelayLeft = (-Distribution->LowerBound + Distribution->DistributionSource);
DelayRight = (Distribution->UpperBound - Distribution->DistributionSource);
DelayOutSourceLeft = 0;
DelayOutSourceRight = 0;
Distribution->MaxDelay = 0;
Distribution->MinDelay = 255;
Distribution->IsDelayBalanced = 0;
if ((DelayLeft == 0) && (DelayRight == 0)) { /*self contained*/
Reg = XRFDC_CLK_DISTR_OFF;
} else {
Reg = XRFDC_CLK_DISTR_MUX9_SRC_INT;
if (DelayLeft == 0) {
Reg |= XRFDC_CLK_DISTR_MUX8_SRC_NTH;
} else {
Reg |= XRFDC_CLK_DISTR_MUX8_SRC_INT;
}
if (((Distribution->DistributionSource == XRFDC_CLK_DST_TILE_228) ||
(Distribution->DistributionSource == XRFDC_CLK_DST_TILE_224)) &&
((DelayLeft > 1) || (DelayRight > 1))) /*cases for no FB from tile to right*/
{
Reg |= XRFDC_CLK_DISTR_MUX4A_SRC_INT | XRFDC_CLK_DISTR_MUX6_SRC_INT |
XRFDC_CLK_DISTR_MUX7_SRC_INT;
FeedBackForInputRight = 0;
FeedBackForInputLeft = 0;
} else {
if (DelayLeft > 1) {
Reg |= XRFDC_CLK_DISTR_MUX4A_SRC_STH | XRFDC_CLK_DISTR_MUX6_SRC_NTH |
XRFDC_CLK_DISTR_MUX7_SRC_INT;
DelayOutSourceRight = 2;
FeedBackForInputRight = 0;
FeedBackForInputLeft = 1;
} else {
Reg |= XRFDC_CLK_DISTR_MUX4A_SRC_INT;
FeedBackForInputRight = 1;
FeedBackForInputLeft = 0;
if ((DelayRight > 1) &&
(Distribution->DistributionSource != XRFDC_CLK_DST_TILE_229)) {
Reg |= XRFDC_CLK_DISTR_MUX7_SRC_STH;
DelayOutSourceLeft = 2;
} else {
Reg |= XRFDC_CLK_DISTR_MUX7_SRC_INT;
}
if (DelayRight == 0) {
Reg |= XRFDC_CLK_DISTR_MUX6_SRC_OFF;
} else {
Reg |= XRFDC_CLK_DISTR_MUX6_SRC_INT;
}
}
}
}
*Delays[Distribution->DistributionSource] =
(Reg == XRFDC_CLK_DISTR_OFF) ? 0 : DelayOutSourceLeft + DelayOutSourceRight + 2;
Distribution->MaxDelay = MAX(Distribution->MaxDelay, (*Delays[Distribution->DistributionSource]));
Distribution->MinDelay = MIN(Distribution->MinDelay, (*Delays[Distribution->DistributionSource]));
/* setup clk detect register */
ClkDetectReg =
(XRFDC_CLOCK_DETECT_CLK << ((XRFDC_CLK_DST_TILE_224 - Distribution->DistributionSource) << 1));
if ((Distribution->DistributionSource) < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - Distribution->DistributionSource;
SettingsPtr = &DistributionSettingsPtr->DAC[Tile];
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - Distribution->DistributionSource;
SettingsPtr = &DistributionSettingsPtr->ADC[Tile];
}
XRFdc_ClrSetReg(InstancePtr, (XRFDC_DRP_BASE(Type, Tile) + XRFDC_HSCOM_ADDR),
XRFDC_HSCOM_CLK_DSTR_OFFSET, XRFDC_HSCOM_CLK_DSTR_MASK, Reg);
XRFdc_ClrSetReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile), XRFDC_CLOCK_DETECT_OFFSET,
XRFDC_CLOCK_DETECT_MASK, ClkDetectReg);
XRFdc_SetTileClkSettings(InstancePtr, Type, Tile, SettingsPtr);
/*Leftmost tile*/
if (DelayLeft) {
*Delays[Distribution->LowerBound] = DelayOutSourceLeft + (DelayLeft << 1);
Distribution->MaxDelay = MAX(Distribution->MaxDelay, (*Delays[Distribution->LowerBound]));
Distribution->MinDelay = MIN(Distribution->MinDelay, (*Delays[Distribution->LowerBound]));
Reg = XRFDC_CLK_DISTR_MUX4A_SRC_STH | XRFDC_CLK_DISTR_MUX6_SRC_OFF |
XRFDC_CLK_DISTR_MUX7_SRC_OFF | XRFDC_CLK_DISTR_MUX8_SRC_NTH |
XRFDC_CLK_DISTR_MUX9_SRC_INT;
/* setup clk detect register */
ClkDetectReg = (XRFDC_CLOCK_DETECT_BOTH
<< ((XRFDC_CLK_DST_TILE_224 - Distribution->DistributionSource) << 1));
for (ClkDetItr = DelayLeft - 1; ClkDetItr > 0; ClkDetItr--) {
ClkDetectReg |=
(XRFDC_CLOCK_DETECT_DIST
<< ((XRFDC_CLK_DST_TILE_224 - (Distribution->DistributionSource - ClkDetItr))
<< 1));
}
if ((Distribution->DistributionSource - DelayLeft) < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - (Distribution->DistributionSource - DelayLeft);
SettingsPtr = &DistributionSettingsPtr->DAC[Tile];
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - (Distribution->DistributionSource - DelayLeft);
SettingsPtr = &DistributionSettingsPtr->ADC[Tile];
}
XRFdc_ClrSetReg(InstancePtr, (XRFDC_DRP_BASE(Type, Tile) + XRFDC_HSCOM_ADDR),
XRFDC_HSCOM_CLK_DSTR_OFFSET, XRFDC_HSCOM_CLK_DSTR_MASK, Reg);
XRFdc_ClrSetReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile), XRFDC_CLOCK_DETECT_OFFSET,
XRFDC_CLOCK_DETECT_MASK, ClkDetectReg);
XRFdc_SetTileClkSettings(InstancePtr, Type, Tile, SettingsPtr);
}
/*Rest of tiles left of Distribution->DistributionSource*/
for (Delay = 1; Delay < DelayLeft; Delay++) {
Reg = XRFDC_CLK_DISTR_MUX6_SRC_OFF | XRFDC_CLK_DISTR_MUX7_SRC_STH |
XRFDC_CLK_DISTR_MUX8_SRC_INT | XRFDC_CLK_DISTR_MUX9_SRC_INT;
if (FeedBackForInputLeft == 0) {
Reg |= XRFDC_CLK_DISTR_MUX4A_SRC_STH;
} else {
Reg |= XRFDC_CLK_DISTR_MUX4A_SRC_INT;
}
*Delays[Distribution->DistributionSource - Delay] =
DelayOutSourceLeft + ((Delay + FeedBackForInputLeft) << 1);
Distribution->MaxDelay =
MAX(Distribution->MaxDelay, (*Delays[Distribution->DistributionSource - Delay]));
Distribution->MinDelay =
MIN(Distribution->MinDelay, (*Delays[Distribution->DistributionSource - Delay]));
FeedBackForInputLeft = !FeedBackForInputLeft;
/* setup clk detect register */
ClkDetectReg = (XRFDC_CLOCK_DETECT_BOTH
<< ((XRFDC_CLK_DST_TILE_224 - Distribution->DistributionSource) << 1));
for (ClkDetItr = Delay - 1; ClkDetItr > 0; ClkDetItr--) {
ClkDetectReg |=
(XRFDC_CLOCK_DETECT_DIST
<< ((XRFDC_CLK_DST_TILE_224 - (Distribution->DistributionSource - ClkDetItr))
<< 1));
}
if ((Distribution->DistributionSource - Delay) < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - (Distribution->DistributionSource - Delay);
SettingsPtr = &DistributionSettingsPtr->DAC[Tile];
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - (Distribution->DistributionSource - Delay);
SettingsPtr = &DistributionSettingsPtr->ADC[Tile];
}
XRFdc_ClrSetReg(InstancePtr, (XRFDC_DRP_BASE(Type, Tile) + XRFDC_HSCOM_ADDR),
XRFDC_HSCOM_CLK_DSTR_OFFSET, XRFDC_HSCOM_CLK_DSTR_MASK, Reg);
XRFdc_ClrSetReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile), XRFDC_CLOCK_DETECT_OFFSET,
XRFDC_CLOCK_DETECT_MASK, ClkDetectReg);
XRFdc_SetTileClkSettings(InstancePtr, Type, Tile, SettingsPtr);
}
/*Rightmost tile*/
if (DelayRight) {
Reg = XRFDC_CLK_DISTR_MUX4A_SRC_INT | XRFDC_CLK_DISTR_MUX6_SRC_OFF |
XRFDC_CLK_DISTR_MUX7_SRC_OFF | XRFDC_CLK_DISTR_MUX8_SRC_NTH |
XRFDC_CLK_DISTR_MUX9_SRC_NTH;
*Delays[Distribution->UpperBound] = DelayOutSourceRight + (DelayRight << 1);
Distribution->MaxDelay = MAX(Distribution->MaxDelay, (*Delays[Distribution->UpperBound]));
Distribution->MinDelay = MIN(Distribution->MinDelay, (*Delays[Distribution->UpperBound]));
/* setup clk detect register */
ClkDetectReg = (XRFDC_CLOCK_DETECT_BOTH
<< ((XRFDC_CLK_DST_TILE_224 - Distribution->DistributionSource) << 1));
for (ClkDetItr = DelayRight - 1; ClkDetItr > 0; ClkDetItr--) {
ClkDetectReg |=
(XRFDC_CLOCK_DETECT_DIST
<< ((XRFDC_CLK_DST_TILE_224 - (Distribution->DistributionSource + ClkDetItr))
<< 1));
}
if ((Distribution->DistributionSource + DelayRight) < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - (Distribution->DistributionSource + DelayRight);
SettingsPtr = &DistributionSettingsPtr->DAC[Tile];
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - (Distribution->DistributionSource + DelayRight);
SettingsPtr = &DistributionSettingsPtr->ADC[Tile];
}
XRFdc_ClrSetReg(InstancePtr, (XRFDC_DRP_BASE(Type, Tile) + XRFDC_HSCOM_ADDR),
XRFDC_HSCOM_CLK_DSTR_OFFSET, XRFDC_HSCOM_CLK_DSTR_MASK, Reg);
XRFdc_ClrSetReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile), XRFDC_CLOCK_DETECT_OFFSET,
XRFDC_CLOCK_DETECT_MASK, ClkDetectReg);
XRFdc_SetTileClkSettings(InstancePtr, Type, Tile, SettingsPtr);
}
/*rest of tiles to right*/
for (Delay = 1; Delay < DelayRight; Delay++) {
if (((Delay + Distribution->DistributionSource) == 3) || (FeedBackForInputRight == 0)) {
FeedBackForInputRight = 0;
Reg = XRFDC_CLK_DISTR_MUX4A_SRC_INT;
*Delays[Distribution->DistributionSource + Delay] = DelayOutSourceRight + (Delay << 1);
} else {
Reg = XRFDC_CLK_DISTR_MUX4A_SRC_STH;
*Delays[Distribution->DistributionSource + Delay] =
DelayOutSourceRight + ((Delay + 1) << 1);
}
Distribution->MaxDelay =
MAX(Distribution->MaxDelay, (*Delays[Distribution->DistributionSource + Delay]));
Distribution->MinDelay =
MIN(Distribution->MinDelay, (*Delays[Distribution->DistributionSource + Delay]));
FeedBackForInputRight = !FeedBackForInputRight;
Reg |= XRFDC_CLK_DISTR_MUX6_SRC_NTH | XRFDC_CLK_DISTR_MUX7_SRC_OFF |
XRFDC_CLK_DISTR_MUX8_SRC_NTH | XRFDC_CLK_DISTR_MUX9_SRC_NTH;
/* setup clk detect register */
ClkDetectReg = (XRFDC_CLOCK_DETECT_BOTH
<< ((XRFDC_CLK_DST_TILE_224 - Distribution->DistributionSource) << 1));
for (ClkDetItr = Delay - 1; ClkDetItr > 0; ClkDetItr--) {
ClkDetectReg |=
(XRFDC_CLOCK_DETECT_DIST
<< ((XRFDC_CLK_DST_TILE_224 - (Distribution->DistributionSource + ClkDetItr))
<< 1));
}
if ((Distribution->DistributionSource + Delay) < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - (Distribution->DistributionSource + Delay);
SettingsPtr = &DistributionSettingsPtr->DAC[Tile];
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - (Distribution->DistributionSource + Delay);
SettingsPtr = &DistributionSettingsPtr->ADC[Tile];
}
XRFdc_ClrSetReg(InstancePtr, (XRFDC_DRP_BASE(Type, Tile) + XRFDC_HSCOM_ADDR),
XRFDC_HSCOM_CLK_DSTR_OFFSET, XRFDC_HSCOM_CLK_DSTR_MASK, Reg);
XRFdc_ClrSetReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile), XRFDC_CLOCK_DETECT_OFFSET,
XRFDC_CLOCK_DETECT_MASK, ClkDetectReg);
XRFdc_SetTileClkSettings(InstancePtr, Type, Tile, SettingsPtr);
}
Distribution->IsDelayBalanced = (Distribution->MaxDelay == Distribution->MinDelay) ? 1 : 0;
}
/*start tiles*/
Status = XRFdc_StartUpDist(InstancePtr, DistributionSettingsPtr);
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to get the clock distribution
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param DistributionSettingsPtr pointer to get the distribution settings
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if no valid distribution found.
*
******************************************************************************/
u32 XRFdc_GetClkDistribution(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr)
{
u32 Status;
u16 ReadReg;
s8 CurrentTile;
s8 AdjacentTile;
u8 DelayOutSourceLeft;
u8 DelayOutSourceRight;
XRFdc_Tile_Clock_Settings *ClockSettingsPtr;
u32 Type;
u32 Tile;
u8 MaxDelay[XRFDC_DIST_MAX];
u8 MinDelay[XRFDC_DIST_MAX];
u8 Distribution;
u8 i;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(DistributionSettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested fuctionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
memset(DistributionSettingsPtr, 0, sizeof(XRFdc_Distribution_Settings));
memset(MaxDelay, 0, sizeof(u8) * XRFDC_DIST_MAX);
memset(MinDelay, 0, sizeof(u8) * XRFDC_DIST_MAX);
DistributionSettingsPtr->DAC[0].SourceTile = XRFDC_CLK_DST_INVALID;
DistributionSettingsPtr->DAC[1].SourceTile = XRFDC_CLK_DST_INVALID;
DistributionSettingsPtr->DAC[2].SourceTile = XRFDC_CLK_DST_INVALID;
DistributionSettingsPtr->DAC[3].SourceTile = XRFDC_CLK_DST_INVALID;
DistributionSettingsPtr->ADC[0].SourceTile = XRFDC_CLK_DST_INVALID;
DistributionSettingsPtr->ADC[1].SourceTile = XRFDC_CLK_DST_INVALID;
DistributionSettingsPtr->ADC[2].SourceTile = XRFDC_CLK_DST_INVALID;
DistributionSettingsPtr->ADC[3].SourceTile = XRFDC_CLK_DST_INVALID;
for (CurrentTile = XRFDC_CLK_DST_TILE_224, Distribution = 0; CurrentTile >= XRFDC_CLK_DST_TILE_231;
CurrentTile--) {
DelayOutSourceLeft = 0;
DelayOutSourceRight = 0;
if (CurrentTile < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - CurrentTile;
ClockSettingsPtr = &DistributionSettingsPtr->DAC[Tile];
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - CurrentTile;
ClockSettingsPtr = &DistributionSettingsPtr->ADC[Tile];
}
(void)XRFdc_GetPLLConfig(InstancePtr, Type, Tile, &(ClockSettingsPtr->PLLSettings));
ClockSettingsPtr->PLLEnable = ClockSettingsPtr->PLLSettings.Enabled;
ClockSettingsPtr->DivisionFactor = ClockSettingsPtr->PLLSettings.OutputDivider;
if (ClockSettingsPtr->SourceTile != XRFDC_CLK_DST_INVALID) {
continue;
}
ReadReg = XRFdc_ReadReg16(InstancePtr, XRFDC_DRP_BASE(Type, Tile) + XRFDC_HSCOM_ADDR,
XRFDC_HSCOM_CLK_DSTR_OFFSET) &
(XRFDC_HSCOM_CLK_DSTR_MASK | XRFDC_HSCOM_CLK_DSTR_MASK_ALT);
if ((ReadReg == XRFDC_CLK_DISTR_OFF) || (ReadReg == XRFDC_DISABLED)) { /*it is its own source no dist*/
ClockSettingsPtr->SourceTile = CurrentTile;
ClockSettingsPtr->Delay = 0;
MaxDelay[Distribution] = 0;
MinDelay[Distribution] = 0;
Distribution++;
} else if (ReadReg & (XRFDC_CLK_DISTR_MUX6_SRC_INT |
XRFDC_CLK_DISTR_MUX7_SRC_INT)) { /*it is its own source, distributes its clk*/
MaxDelay[Distribution] = 0;
MinDelay[Distribution] = 255;
ClockSettingsPtr->SourceTile = CurrentTile;
if ((ReadReg & XRFDC_DIST_CTRL_DIST_SRC_LOCAL) == XRFDC_DIST_CTRL_DIST_SRC_LOCAL) {
ClockSettingsPtr->DistributedClock = XRFDC_DIST_OUT_RX;
} else {
ClockSettingsPtr->DistributedClock = XRFDC_DIST_OUT_OUTDIV;
}
if (ReadReg & XRFDC_CLK_DISTR_MUX7_SRC_STH) {
DelayOutSourceLeft = 2;
} else if (ReadReg & XRFDC_CLK_DISTR_MUX6_SRC_NTH) {
DelayOutSourceRight = 2;
}
ClockSettingsPtr->Delay = DelayOutSourceLeft + DelayOutSourceRight + 2;
MaxDelay[Distribution] = MAX(MaxDelay[Distribution], (ClockSettingsPtr->Delay));
MinDelay[Distribution] = MIN(MinDelay[Distribution], (ClockSettingsPtr->Delay));
/*work left*/
for (AdjacentTile = CurrentTile - 1; AdjacentTile >= XRFDC_CLK_DST_TILE_231; AdjacentTile--) {
if (AdjacentTile < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - AdjacentTile;
ClockSettingsPtr = &DistributionSettingsPtr->DAC[Tile];
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - AdjacentTile;
ClockSettingsPtr = &DistributionSettingsPtr->ADC[Tile];
}
ReadReg = XRFdc_ReadReg16(InstancePtr, XRFDC_DRP_BASE(Type, Tile) + XRFDC_HSCOM_ADDR,
XRFDC_HSCOM_CLK_DSTR_OFFSET) &
XRFDC_HSCOM_CLK_DSTR_MASK;
if (ReadReg == XRFDC_CLK_DISTR_LEFTMOST_TILE) {
ClockSettingsPtr->SourceTile = CurrentTile;
ClockSettingsPtr->Delay =
DelayOutSourceLeft + ((CurrentTile - AdjacentTile) << 1);
break;
} else if ((ReadReg & XRFDC_CLK_DISTR_CONT_LEFT_EVEN) ==
XRFDC_CLK_DISTR_CONT_LEFT_EVEN) {
ClockSettingsPtr->SourceTile = CurrentTile;
ClockSettingsPtr->Delay =
DelayOutSourceLeft + ((CurrentTile - AdjacentTile) << 1) + 2;
} else if ((ReadReg & XRFDC_CLK_DISTR_CONT_LEFT_ODD) == XRFDC_CLK_DISTR_CONT_LEFT_ODD) {
ClockSettingsPtr->Delay =
DelayOutSourceLeft + ((CurrentTile - AdjacentTile) << 1);
ClockSettingsPtr->SourceTile = CurrentTile;
} else {
break;
}
MaxDelay[Distribution] = MAX(MaxDelay[Distribution], (ClockSettingsPtr->Delay));
MinDelay[Distribution] = MIN(MinDelay[Distribution], (ClockSettingsPtr->Delay));
}
/*work right*/
for (AdjacentTile = CurrentTile + 1; AdjacentTile <= XRFDC_CLK_DST_TILE_224; AdjacentTile++) {
if (AdjacentTile < XRFDC_CLK_DST_TILE_227) { /*DAC*/
Type = XRFDC_DAC_TILE;
Tile = XRFDC_CLK_DST_TILE_228 - AdjacentTile;
ClockSettingsPtr = &DistributionSettingsPtr->DAC[Tile];
} else { /*ADC*/
Type = XRFDC_ADC_TILE;
Tile = XRFDC_CLK_DST_TILE_224 - AdjacentTile;
ClockSettingsPtr = &DistributionSettingsPtr->ADC[Tile];
}
ReadReg = XRFdc_ReadReg16(InstancePtr, XRFDC_DRP_BASE(Type, Tile) + XRFDC_HSCOM_ADDR,
XRFDC_HSCOM_CLK_DSTR_OFFSET) &
XRFDC_HSCOM_CLK_DSTR_MASK;
if ((ReadReg & XRFDC_CLK_DISTR_CONT_RIGHT_HWL_ODD) ==
XRFDC_CLK_DISTR_CONT_RIGHT_HWL_ODD) {
ClockSettingsPtr->SourceTile = CurrentTile;
ClockSettingsPtr->Delay =
DelayOutSourceRight + ((AdjacentTile - CurrentTile) << 1);
MaxDelay[Distribution] = MAX(MaxDelay[Distribution], (ClockSettingsPtr->Delay));
MinDelay[Distribution] = MIN(MinDelay[Distribution], (ClockSettingsPtr->Delay));
} else if (((ReadReg & XRFDC_CLK_DISTR_CONT_RIGHT_EVEN) ==
XRFDC_CLK_DISTR_CONT_RIGHT_EVEN) &&
(AdjacentTile != XRFDC_CLK_DST_TILE_228)) {
ClockSettingsPtr->SourceTile = CurrentTile;
ClockSettingsPtr->Delay =
DelayOutSourceRight + ((AdjacentTile - CurrentTile) << 1) + 2;
MaxDelay[Distribution] = MAX(MaxDelay[Distribution], (ClockSettingsPtr->Delay));
MinDelay[Distribution] = MIN(MinDelay[Distribution], (ClockSettingsPtr->Delay));
} else if ((ReadReg & XRFDC_CLK_DISTR_RIGHTMOST_TILE) ==
XRFDC_CLK_DISTR_RIGHTMOST_TILE) {
ClockSettingsPtr->SourceTile = CurrentTile;
ClockSettingsPtr->Delay =
DelayOutSourceRight + ((AdjacentTile - CurrentTile) << 1);
MaxDelay[Distribution] = MAX(MaxDelay[Distribution], (ClockSettingsPtr->Delay));
MinDelay[Distribution] = MIN(MinDelay[Distribution], (ClockSettingsPtr->Delay));
break;
} else {
break;
}
}
Distribution++;
}
}
Distribution--;
for (i = 0; i <= Distribution; i++) { /*flip distributions*/
DistributionSettingsPtr->DistributionStatus[i].MaxDelay = MaxDelay[Distribution - i];
DistributionSettingsPtr->DistributionStatus[i].MinDelay = MinDelay[Distribution - i];
DistributionSettingsPtr->DistributionStatus[i].IsDelayBalanced =
(MaxDelay[Distribution - i] == MinDelay[Distribution - i]) ? 1 : 0;
}
Status = XRFdc_CheckClkDistValid(InstancePtr, DistributionSettingsPtr);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Invalid Distribution in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function gets Clock source
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type indicates ADC/DAC.
* @param Tile_Id indicates Tile number (0-3).
* @param ClockSourcePtr Pointer to return the clock source
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if tile not enabled.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_GetClockSource(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *ClockSourcePtr)
{
u32 BaseAddr;
u32 Status;
u32 PLLEnReg;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ClockSourcePtr != NULL);
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Requested tile (%s %u) not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_DRP_BASE(Type, Tile_Id) + XRFDC_HSCOM_ADDR;
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
*ClockSourcePtr = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CLK_NETWORK_CTRL1,
XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK);
} else {
PLLEnReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_PLL_DIVIDER0);
if ((PLLEnReg & XRFDC_PLL_DIVIDER0_BYP_PLL_MASK) != 0) {
*ClockSourcePtr = XRFDC_EXTERNAL_CLK;
} else {
*ClockSourcePtr = XRFDC_INTERNAL_PLL_CLK;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function gets PLL lock status
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type indicates ADC/DAC.
* @param Tile_Id indicates Tile number (0-3).
* @param LockStatusPtr Pointer to return the PLL lock status
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_GetPLLLockStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *LockStatusPtr)
{
u32 BaseAddr;
u32 ReadReg;
u32 ClkSrc = 0U;
u32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(LockStatusPtr != NULL);
/*
* Get Tile clock source information
*/
if (XRFdc_GetClockSource(InstancePtr, Type, Tile_Id, &ClkSrc) != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Get clock source request %s %u failed in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (ClkSrc == XRFDC_EXTERNAL_CLK) {
metal_log(METAL_LOG_DEBUG, "\n %s %u uses external clock source in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
*LockStatusPtr = XRFDC_PLL_LOCKED;
} else {
if (Type == XRFDC_ADC_TILE) {
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
} else {
BaseAddr = XRFDC_DAC_TILE_CTRL_STATS_ADDR(Tile_Id);
}
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_STATUS_OFFSET, XRFDC_PLL_LOCKED_MASK);
if (ReadReg != 0U) {
*LockStatusPtr = XRFDC_PLL_LOCKED;
} else {
*LockStatusPtr = XRFDC_PLL_UNLOCKED;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function used for configuring the internal PLL registers
* based on reference clock and sampling rate
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type indicates ADC/DAC.
* @param Tile_Id indicates Tile number (0-3).
* @param RefClkFreq Reference Clock Frequency MHz(50MHz - 1.2GHz)
* @param SamplingRate Sampling Rate in MHz(0.5- 4 GHz)
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
static u32 XRFdc_SetPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, double RefClkFreq, double SamplingRate)
{
u32 BaseAddr;
u32 Status;
u32 FeedbackDiv;
u32 OutputDiv;
double CalcSamplingRate;
double PllFreq;
double SamplingError;
u32 Best_FeedbackDiv = 0x0U;
u32 Best_OutputDiv = 0x2U;
double Best_Error = 0xFFFFFFFFU;
u32 DivideMode = 0x0U;
u32 DivideValue = 0x0U;
u32 PllFreqIndex = 0x0U;
u32 FbDivIndex = 0x0U;
u32 RefClkDiv = 0x1;
u16 ReadReg;
u32 VCOMin;
u32 VCOMax;
if (Type == XRFDC_ADC_TILE) {
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id);
} else {
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id);
}
BaseAddr += XRFDC_HSCOM_ADDR;
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_PLL_REFDIV);
if (ReadReg & XRFDC_REFCLK_DIV_1_MASK) {
RefClkDiv = XRFDC_REF_CLK_DIV_1;
} else {
switch (ReadReg & XRFDC_REFCLK_DIV_MASK) {
case XRFDC_REFCLK_DIV_2_MASK:
RefClkDiv = XRFDC_REF_CLK_DIV_2;
break;
case XRFDC_REFCLK_DIV_3_MASK:
RefClkDiv = XRFDC_REF_CLK_DIV_3;
break;
case XRFDC_REFCLK_DIV_4_MASK:
RefClkDiv = XRFDC_REF_CLK_DIV_4;
break;
default:
/*
* IP currently supporting 1 to 4 divider values. This
* error condition might change in future based on IP update.
*/
metal_log(METAL_LOG_ERROR,
"\n Unsupported Reference clock Divider value (%u) for %s %u in %s\r\n",
(ReadReg & XRFDC_REFCLK_DIV_MASK), (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id,
__func__);
return XRFDC_FAILURE;
}
}
RefClkFreq /= RefClkDiv;
/*
* Sweep valid integer values of FeedbackDiv(N) and record a list
* of values that fall in the valid VCO range 8.5GHz - 12.8GHz
*/
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
VCOMin = VCO_RANGE_MIN;
VCOMax = VCO_RANGE_MAX;
} else {
if (Type == XRFDC_ADC_TILE) {
VCOMin = VCO_RANGE_ADC_MIN;
VCOMax = VCO_RANGE_ADC_MAX;
} else {
VCOMin = VCO_RANGE_DAC_MIN;
VCOMax = VCO_RANGE_DAC_MAX;
}
}
for (FeedbackDiv = PLL_FPDIV_MIN; FeedbackDiv <= PLL_FPDIV_MAX; FeedbackDiv++) {
PllFreq = FeedbackDiv * RefClkFreq;
if ((PllFreq >= VCOMin) && (PllFreq <= VCOMax)) {
/*
* Sweep values of OutputDiv(M) to find the output frequency
* that best matches the user requested value
*/
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
OutputDiv = PLL_DIVIDER_MIN_GEN3;
CalcSamplingRate = (PllFreq / OutputDiv);
if (SamplingRate > CalcSamplingRate) {
SamplingError = SamplingRate - CalcSamplingRate;
} else {
SamplingError = CalcSamplingRate - SamplingRate;
}
if (Best_Error > SamplingError) {
Best_FeedbackDiv = FeedbackDiv;
Best_OutputDiv = OutputDiv;
Best_Error = SamplingError;
}
}
for (OutputDiv = PLL_DIVIDER_MIN; OutputDiv <= PLL_DIVIDER_MAX; OutputDiv += 2U) {
CalcSamplingRate = (PllFreq / OutputDiv);
if (SamplingRate > CalcSamplingRate) {
SamplingError = SamplingRate - CalcSamplingRate;
} else {
SamplingError = CalcSamplingRate - SamplingRate;
}
if (Best_Error > SamplingError) {
Best_FeedbackDiv = FeedbackDiv;
Best_OutputDiv = OutputDiv;
Best_Error = SamplingError;
}
}
OutputDiv = 3U;
CalcSamplingRate = (PllFreq / OutputDiv);
if (SamplingRate > CalcSamplingRate) {
SamplingError = SamplingRate - CalcSamplingRate;
} else {
SamplingError = CalcSamplingRate - SamplingRate;
}
if (Best_Error > SamplingError) {
Best_FeedbackDiv = FeedbackDiv;
Best_OutputDiv = OutputDiv;
Best_Error = SamplingError;
}
}
/*
* PLL Static configuration
*/
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_SDM_CFG0, 0x80U);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_SDM_SEED0, 0x111U);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_SDM_SEED1, 0x11U);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_VCO1, 0x08U);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_VREG, 0x45U);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_VCO0, 0x5800U);
} else {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_VREG, 0x2DU);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_VCO0, 0x5F03U);
}
/*
* Set Feedback divisor value
*/
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_FPDIV, Best_FeedbackDiv - 2U);
/*
* Set Output divisor value
*/
if (Best_OutputDiv == 1U) {
DivideMode = 0x0U;
} else if (Best_OutputDiv == 2U) {
DivideMode = 0x1U;
} else if (Best_OutputDiv == 3U) {
DivideMode = 0x2U;
DivideValue = 0x1U;
} else if (Best_OutputDiv >= 4U) {
DivideMode = 0x3U;
DivideValue = ((Best_OutputDiv - 4U) / 2U);
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_PLL_DIVIDER0, XRFDC_PLL_DIVIDER0_MASK,
((DivideMode << XRFDC_PLL_DIVIDER0_SHIFT) | DivideValue));
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
if (Best_OutputDiv > PLL_DIVIDER_MIN_GEN3) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_PLL_DIVIDER0, XRFDC_PLL_DIVIDER0_ALT_MASK,
XRFDC_DISABLED);
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_PLL_DIVIDER0, XRFDC_PLL_DIVIDER0_ALT_MASK,
XRFDC_PLL_DIVIDER0_BYPDIV_MASK);
}
}
/*
* Enable fine sweep
*/
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_CRS2, XRFDC_PLL_CRS2_VAL);
/*
* Set default PLL spare inputs LSB
*/
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_SPARE0, 0x507U);
} else {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_SPARE0, 0x0D37U);
}
/*
* Set PLL spare inputs MSB
*/
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_SPARE1, 0x0U);
} else {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_SPARE1, 0x80U);
}
PllFreq = RefClkFreq * Best_FeedbackDiv;
if (PllFreq < 9400U) {
PllFreqIndex = 0U;
FbDivIndex = 2U;
if (Best_FeedbackDiv < 21U) {
FbDivIndex = 0U;
} else if (Best_FeedbackDiv < 30U) {
FbDivIndex = 1U;
}
} else if (PllFreq < 10070U) {
PllFreqIndex = 1U;
FbDivIndex = 2U;
if (Best_FeedbackDiv < 18U) {
FbDivIndex = 0U;
} else if (Best_FeedbackDiv < 30U) {
FbDivIndex = 1U;
}
} else if (PllFreq < 10690U) {
PllFreqIndex = 2U;
FbDivIndex = 3U;
if (Best_FeedbackDiv < 18U) {
FbDivIndex = 0U;
} else if (Best_FeedbackDiv < 25U) {
FbDivIndex = 1U;
} else if (Best_FeedbackDiv < 35U) {
FbDivIndex = 2U;
}
} else if (PllFreq < 10990U) {
PllFreqIndex = 3U;
FbDivIndex = 3U;
if (Best_FeedbackDiv < 19U) {
FbDivIndex = 0U;
} else if (Best_FeedbackDiv < 27U) {
FbDivIndex = 1U;
} else if (Best_FeedbackDiv < 38U) {
FbDivIndex = 2U;
}
} else if (PllFreq < 11430U) {
PllFreqIndex = 4U;
FbDivIndex = 3U;
if (Best_FeedbackDiv < 19U) {
FbDivIndex = 0U;
} else if (Best_FeedbackDiv < 27U) {
FbDivIndex = 1U;
} else if (Best_FeedbackDiv < 38U) {
FbDivIndex = 2U;
}
} else if (PllFreq < 12040U) {
PllFreqIndex = 5U;
FbDivIndex = 3U;
if (Best_FeedbackDiv < 20U) {
FbDivIndex = 0U;
} else if (Best_FeedbackDiv < 28U) {
FbDivIndex = 1U;
} else if (Best_FeedbackDiv < 40U) {
FbDivIndex = 2U;
}
} else if (PllFreq < 12530U) {
PllFreqIndex = 6U;
FbDivIndex = 3U;
if (Best_FeedbackDiv < 23U) {
FbDivIndex = 0U;
} else if (Best_FeedbackDiv < 30U) {
FbDivIndex = 1U;
} else if (Best_FeedbackDiv < 42U) {
FbDivIndex = 2U;
}
} else if (PllFreq < 20000U) {
PllFreqIndex = 7U;
FbDivIndex = 2U;
if (Best_FeedbackDiv < 20U) {
FbDivIndex = 0U;
/*
* Set PLL spare inputs LSB
*/
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_SPARE0, 0x577);
} else {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_SPARE0, 0x0D37U);
}
} else if (Best_FeedbackDiv < 39U) {
FbDivIndex = 1U;
}
}
/*
* Enable automatic selection of the VCO, this will work with the
* IP version 2.0.1 and above and using older version of IP is
* not likely to work.
*/
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_PLL_CRS1, XRFDC_PLL_VCO_SEL_AUTO_MASK,
XRFDC_PLL_VCO_SEL_AUTO_MASK);
/*
* PLL bits for loop filters LSB
*/
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_LPF0, PllTuningMatrix[PllFreqIndex][FbDivIndex][0]);
/*
* PLL bits for loop filters MSB
*/
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_LPF1, XRFDC_PLL_LPF1_VAL);
/*
* Set PLL bits for charge pumps
*/
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_PLL_CHARGEPUMP,
PllTuningMatrix[PllFreqIndex][FbDivIndex][1]);
}
CalcSamplingRate = (Best_FeedbackDiv * RefClkFreq) / Best_OutputDiv;
CalcSamplingRate /= XRFDC_MILLI;
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.SampleRate = CalcSamplingRate;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.RefClkDivider = RefClkDiv;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.FeedbackDivider = Best_FeedbackDiv;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.OutputDivider = Best_OutputDiv;
} else {
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.SampleRate = CalcSamplingRate;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.RefClkDivider = RefClkDiv;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.FeedbackDivider = Best_FeedbackDiv;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.OutputDivider = Best_OutputDiv;
}
Status = XRFDC_SUCCESS;
return Status;
}
/*****************************************************************************/
/**
*
* This API is used to get the PLL Configurations.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type represents ADC or DAC.
* @param Tile_Id Valid values are 0-3.
* @param PLLSettings pointer to the XRFdc_PLL_Settings structure to get
* the PLL configurations
*
* @note None.
*
******************************************************************************/
u32 XRFdc_GetPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, XRFdc_PLL_Settings *PLLSettings)
{
u32 Status;
u32 BaseAddr;
u16 ReadReg;
double RefClkFreq;
double SampleRate;
u32 FeedbackDivider;
u8 OutputDivider;
u32 RefClkDivider;
u32 Enabled;
u8 DivideMode;
u32 PLLFreq;
u32 PLLFS;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Xil_AssertNonvoid(PLLSettings != NULL);
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Requested tile (%s %u) not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_CTRL_STS_BASE(Type, Tile_Id);
PLLFreq = XRFdc_ReadReg(InstancePtr, BaseAddr, XRFDC_PLL_FREQ);
RefClkFreq = ((double)PLLFreq) / 1000;
PLLFS = XRFdc_ReadReg(InstancePtr, BaseAddr, XRFDC_PLL_FS);
SampleRate = ((double)PLLFS) / 1000000;
if (PLLFS == 0) {
/*This code is here to support the old IPs.*/
if (Type == XRFDC_ADC_TILE) {
PLLSettings->Enabled = InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.Enabled;
PLLSettings->FeedbackDivider = InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.FeedbackDivider;
PLLSettings->OutputDivider = InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.OutputDivider;
PLLSettings->RefClkDivider = InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.RefClkDivider;
PLLSettings->RefClkFreq = InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.RefClkFreq;
PLLSettings->SampleRate = InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.SampleRate;
Status = XRFDC_SUCCESS;
goto RETURN_PATH;
} else {
PLLSettings->Enabled = InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.Enabled;
PLLSettings->FeedbackDivider = InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.FeedbackDivider;
PLLSettings->OutputDivider = InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.OutputDivider;
PLLSettings->RefClkDivider = InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.RefClkDivider;
PLLSettings->RefClkFreq = InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.RefClkFreq;
PLLSettings->SampleRate = InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.SampleRate;
Status = XRFDC_SUCCESS;
goto RETURN_PATH;
}
} else {
if (Type == XRFDC_ADC_TILE) {
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id);
} else {
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id);
}
BaseAddr += XRFDC_HSCOM_ADDR;
FeedbackDivider = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_PLL_FPDIV, 0x00FF) + 2;
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_PLL_REFDIV);
if (ReadReg & XRFDC_REFCLK_DIV_1_MASK) {
RefClkDivider = XRFDC_REF_CLK_DIV_1;
} else {
switch (ReadReg & XRFDC_REFCLK_DIV_MASK) {
case XRFDC_REFCLK_DIV_2_MASK:
RefClkDivider = XRFDC_REF_CLK_DIV_2;
break;
case XRFDC_REFCLK_DIV_3_MASK:
RefClkDivider = XRFDC_REF_CLK_DIV_3;
break;
case XRFDC_REFCLK_DIV_4_MASK:
RefClkDivider = XRFDC_REF_CLK_DIV_4;
break;
default:
/*
* IP currently supporting 1 to 4 divider values. This
* error condition might change in future based on IP update.
*/
metal_log(METAL_LOG_ERROR,
"\n Unsupported Reference clock Divider value (%u) for %s %u in %s\r\n",
(ReadReg & XRFDC_REFCLK_DIV_MASK), (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC",
Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
}
if (XRFdc_GetClockSource(InstancePtr, Type, Tile_Id, &Enabled) != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_PLL_DIVIDER0);
DivideMode = (ReadReg & XRFDC_PLL_DIVIDER0_MODE_MASK) >> XRFDC_PLL_DIVIDER0_SHIFT;
switch (DivideMode) {
case XRFDC_PLL_OUTDIV_MODE_1:
OutputDivider = 1;
break;
case XRFDC_PLL_OUTDIV_MODE_2:
OutputDivider = 2;
break;
case XRFDC_PLL_OUTDIV_MODE_3:
OutputDivider = 3;
break;
case XRFDC_PLL_OUTDIV_MODE_N:
OutputDivider = ((ReadReg & XRFDC_PLL_DIVIDER0_VALUE_MASK) + 2) << 1;
break;
default:
metal_log(METAL_LOG_ERROR, "\n Unsupported Output clock Divider value (%u) for %s %u in %s\r\n",
DivideMode, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
break;
}
PLLSettings->Enabled = Enabled;
PLLSettings->FeedbackDivider = FeedbackDivider;
PLLSettings->OutputDivider = OutputDivider;
PLLSettings->RefClkDivider = RefClkDivider;
PLLSettings->RefClkFreq = RefClkFreq;
PLLSettings->SampleRate = SampleRate;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function used for dynamically switch between internal PLL and
* external clcok source and configuring the internal PLL
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type indicates ADC/DAC
* @param Tile_Id indicates Tile number (0-3)
* @param Source Clock source internal PLL or external clock source
* @param RefClkFreq Reference Clock Frequency in MHz(102.40625MHz - 1.2GHz)
* @param SamplingRate Sampling Rate in MHz(0.1- 6.554GHz for DAC and
* 0.5/1.0 - 2.058/4.116GHz for ADC based on the device package).
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note This API enables automatic selection of the VCO which will work in
* IP version 2.0.1 and above. Using older version of IP this API is
* not likely to work.
*
******************************************************************************/
u32 XRFdc_DynamicPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 Source, double RefClkFreq, double SamplingRate)
{
u32 ClkSrc = 0U;
u32 Status;
u32 BaseAddr;
u32 PLLEnable = 0x0U;
u32 InitialPowerUpState;
double MaxSampleRate;
double MinSampleRate;
u32 OpDiv;
u32 PLLFreq;
u32 PLLFS;
u32 DivideMode;
u32 DivideValue;
u32 NetCtrlReg = 0x0U;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if ((Source != XRFDC_INTERNAL_PLL_CLK) && (Source != XRFDC_EXTERNAL_CLK)) {
metal_log(METAL_LOG_ERROR, "\n Invalid Source value (%u) for %s %u in %s\r\n", Source,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Requested tile (%s %u) not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
}
/*
* Get Tile clock source information
*/
if (XRFdc_GetClockSource(InstancePtr, Type, Tile_Id, &ClkSrc) != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (XRFdc_GetMaxSampleRate(InstancePtr, Type, Tile_Id, &MaxSampleRate) != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (XRFdc_GetMinSampleRate(InstancePtr, Type, Tile_Id, &MinSampleRate) != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((SamplingRate < MinSampleRate) || (SamplingRate > MaxSampleRate)) {
metal_log(METAL_LOG_ERROR, "\n Invalid sampling rate value (%lf) for %s %u in %s\r\n", SamplingRate,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
BaseAddr = XRFDC_CTRL_STS_BASE(Type, Tile_Id);
if (Source == XRFDC_INTERNAL_PLL_CLK) {
if ((RefClkFreq < XRFDC_REFFREQ_MIN) || (RefClkFreq > XRFDC_REFFREQ_MAX)) {
metal_log(
METAL_LOG_ERROR,
"\n Input reference clock frequency (%lf MHz) does not respect the specifications for internal PLL usage. Please use a different frequency (%lf - %lf MHz) or bypass the internal PLL for %s %u in %s\r\n",
RefClkFreq, XRFDC_REFFREQ_MIN, XRFDC_REFFREQ_MAX,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
}
PLLFreq = (u32)(RefClkFreq * 1000);
PLLFS = (u32)(SamplingRate * 1000);
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_PLL_FREQ, PLLFreq);
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_PLL_FS, PLLFS);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if ((Source != XRFDC_INTERNAL_PLL_CLK) && (ClkSrc != XRFDC_INTERNAL_PLL_CLK)) {
metal_log(METAL_LOG_DEBUG, "\n Requested tile (%s %u) uses external clock source in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.SampleRate = (double)(SamplingRate / 1000);
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.RefClkFreq = RefClkFreq;
} else {
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.SampleRate = (double)(SamplingRate / 1000);
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.RefClkFreq = RefClkFreq;
}
Status = XRFDC_SUCCESS;
goto RETURN_PATH;
}
}
if (Type == XRFDC_ADC_TILE) {
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
InitialPowerUpState = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_STATUS_OFFSET, XRFDC_PWR_UP_STAT_MASK) >>
XRFDC_PWR_UP_STAT_SHIFT;
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_HSCOM_ADDR;
} else {
BaseAddr = XRFDC_DAC_TILE_CTRL_STATS_ADDR(Tile_Id);
InitialPowerUpState = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_STATUS_OFFSET, XRFDC_PWR_UP_STAT_MASK) >>
XRFDC_PWR_UP_STAT_SHIFT;
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_HSCOM_ADDR;
}
/*
* Stop the ADC or DAC tile by putting tile in reset state if not stopped already
*/
if (InitialPowerUpState != XRFDC_DISABLED) {
Status = XRFdc_Shutdown(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
}
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
NetCtrlReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_CLK_NETWORK_CTRL1);
}
if (Source == XRFDC_INTERNAL_PLL_CLK) {
PLLEnable = 0x1;
/*
* Configure the PLL
*/
if (XRFdc_SetPLLConfig(InstancePtr, Type, Tile_Id, RefClkFreq, SamplingRate) != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_PLL_DIVIDER0, XRFDC_PLL_DIVIDER0_BYP_PLL_MASK,
XRFDC_DISABLED);
if ((NetCtrlReg & XRFDC_CLK_NETWORK_CTRL1_REGS_MASK) != XRFDC_DISABLED) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET,
XRFDC_HSCOM_PWR_STATS_RX_PLL);
} else {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET,
XRFDC_HSCOM_PWR_STATS_DIST_PLL);
}
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CLK_NETWORK_CTRL1,
XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK, XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET,
XRFDC_HSCOM_PWR_STATS_PLL);
}
} else {
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
OpDiv = PLLFreq / PLLFS;
if ((OpDiv == 0) || ((OpDiv > 3) && (OpDiv % 2))) {
metal_log(METAL_LOG_ERROR, "\n No valid output divisor available for %s %u in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (OpDiv == 1) {
DivideMode = XRFDC_PLL_OUTDIV_MODE_1;
DivideValue = XRFDC_PLL_DIVIDER0_BYP_OPDIV_MASK;
} else if (OpDiv == 2U) {
DivideMode = XRFDC_PLL_OUTDIV_MODE_2;
DivideValue = XRFDC_DISABLED;
} else if (OpDiv == 3U) {
DivideMode = XRFDC_PLL_OUTDIV_MODE_3;
DivideValue = XRFDC_PLL_OUTDIV_MODE_3_VAL;
} else {
DivideMode = XRFDC_PLL_OUTDIV_MODE_N;
DivideValue = ((OpDiv - 4U) >> 1);
}
if (OpDiv == 1) {
if ((NetCtrlReg & XRFDC_CLK_NETWORK_CTRL1_REGS_MASK) != XRFDC_DISABLED) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET,
XRFDC_HSCOM_PWR_STATS_DIST_EXT_SRC);
} else {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET,
XRFDC_HSCOM_PWR_STATS_DIST_EXT);
}
} else {
if ((NetCtrlReg & XRFDC_CLK_NETWORK_CTRL1_REGS_MASK) != XRFDC_DISABLED) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET,
XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC);
} else {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET,
XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV);
}
}
XRFdc_ClrSetReg(InstancePtr, XRFDC_DRP_BASE(Type, Tile_Id) + XRFDC_HSCOM_ADDR,
XRFDC_PLL_DIVIDER0, (XRFDC_PLL_DIVIDER0_ALT_MASK | XRFDC_PLL_DIVIDER0_MASK),
((DivideMode << XRFDC_PLL_DIVIDER0_SHIFT) | DivideValue |
XRFDC_PLL_DIVIDER0_BYP_PLL_MASK));
} else {
OpDiv = 0; /*keep backwards compatibility */
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET,
XRFDC_HSCOM_PWR_STATS_EXTERNAL);
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CLK_NETWORK_CTRL1, XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK,
XRFDC_DISABLED);
SamplingRate /= XRFDC_MILLI;
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.SampleRate = SamplingRate;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.RefClkDivider = 0x0U;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.FeedbackDivider = 0x0U;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.OutputDivider = OpDiv;
} else {
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.SampleRate = SamplingRate;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.RefClkDivider = 0x0U;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.FeedbackDivider = 0x0U;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.OutputDivider = OpDiv;
}
}
/*
* Re-start the ADC or DAC tile if tile was shut down in this function
*/
if (InitialPowerUpState != XRFDC_DISABLED) {
Status = XRFdc_StartUp(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
}
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.RefClkFreq = RefClkFreq;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.Enabled = PLLEnable;
} else {
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.RefClkFreq = RefClkFreq;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.Enabled = PLLEnable;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilfpga_v5_2/src/Makefile
###############################################################################
# Copyright (c) 2007 - 2020 Xilinx, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
###############################################################################
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxilfpga.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
xilfpga_DIR = .
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
xilfpga_SRCS := $(wildcard *.c)
xilfpga_OBJS = $(addprefix $(xilfpga_DIR)/, $(xilfpga_SRCS:%.c=%.o))
INCLUDEFILES=$(xilfpga_DIR)/$(wildcard *.h)
libs: libxilfpga.a
ifeq ($(notdir $(COMPILER)) , iccarm)
EXTRA_ARCHIVE_FLAGS=--create
else
ifeq ($(notdir $(COMPILER)) , armclang)
EXTRA_ARCHIVE_FLAGS=-rc
else
EXTRA_ARCHIVE_FLAGS=rc
endif
endif
libxilfpga.a: print_msg_xilfpga $(xilfpga_OBJS)
$(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} ${xilfpga_OBJS}
print_msg_xilfpga:
@echo "Compiling xilfpga Library"
.PHONY: include
include: libxilfpga_includes
libxilfpga_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf $(xilfpga_DIR)/${OBJECTS}
rm -rf ${RELEASEDIR}/${LIB}
$(xilfpga_DIR)/%.o: $(xilfpga_DIR)/%.c $(INCLUDEFILES)
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -c $< -o $@
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/afi.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _AFI_H_
#define _AFI_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* FPD SLCR Base Address
*/
#define FPD_SLCR_BASEADDR ((u32)0xFD610000U)
/*
* FPD SLCR Ctrl
*/
#define FPD_SLCR_CTRL ( ( FPD_SLCR_BASEADDR ) + ((u32)0x4U) )
/*
* Register: AFI_FS
*/
#define FPD_SLCR_AFI_FS_REG ( ( FPD_SLCR_BASEADDR ) + ((u32)0X00005000U) )
/*
* AFI FM0 Base Address
*/
#define AFI_FM0_BASEADDR ((u32)0xFD360000U)
/*
* AFI FM1 Base Address
*/
#define AFI_FM1_BASEADDR ((u32)0xFD370000U)
/*
* AFI FM2 Base Address
*/
#define AFI_FM2_BASEADDR ((u32)0xFD380000U)
/*
* AFI FM3 Base Address
*/
#define AFI_FM3_BASEADDR ((u32)0xFD390000U)
/*
* AFI FM4 Base Address
*/
#define AFI_FM4_BASEADDR ((u32)0xFD3A0000U)
/*
* AFI FM5 Base Address
*/
#define AFI_FM5_BASEADDR ((u32)0xFD3B0000U)
/*
* AFI FM6 Base Address
*/
#define AFI_FM6_BASEADDR ((u32)0xFF9B0000U)
#ifdef __cplusplus
}
#endif
#endif /* _AFI_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_core.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_psm_api.h"
#include "xpm_core.h"
#include "xpm_psm.h"
XStatus XPmCore_Init(XPm_Core *Core, u32 Id, XPm_Power *Power,
XPm_ClockNode *Clock, XPm_ResetNode *Reset, u8 IpiCh,
struct XPm_CoreOps *Ops)
{
XStatus Status = XST_FAILURE;
Status = XPmDevice_Init(&Core->Device, Id, 0, Power, Clock, Reset);
if (XST_SUCCESS != Status) {
goto done;
}
Core->DebugMode = 0;
Core->ImageId = 0;
Core->Ipi = IpiCh;
Core->CoreOps = Ops;
Core->PwrUpLatency = 0;
Core->PwrDwnLatency = 0;
done:
return Status;
}
static XStatus XPmCore_Sleep(XPm_Core *Core)
{
XStatus Status = XST_FAILURE;
XPm_Device *Device;
XPm_Device *DevTcm0A = XPmDevice_GetById(PM_DEV_TCM_0_A);
XPm_Device *DevTcm0B = XPmDevice_GetById(PM_DEV_TCM_0_B);
XPm_Device *DevTcm1A = XPmDevice_GetById(PM_DEV_TCM_1_A);
XPm_Device *DevTcm1B = XPmDevice_GetById(PM_DEV_TCM_1_B);
/*
* If parent is on, then only send sleep request
*/
if ((Core->Device.Power->Parent->Node.State == (u8)XPM_POWER_STATE_ON) &&
((u32)XPM_NODETYPE_DEV_CORE_RPU != NODETYPE(Core->Device.Node.Id))) {
/*
* Power down the core
*/
Status = XPm_DirectPwrDwn(Core->Device.Node.Id);
if (XST_SUCCESS != Status) {
goto done;
}
}
if (NULL != Core->Device.ClkHandles) {
Status = XPmClock_Release(Core->Device.ClkHandles);
if (XST_SUCCESS != Status) {
goto done;
}
}
/* Skip reset for RPU cores if any of the TCM is ON */
if (!(((u32)XPM_NODETYPE_DEV_CORE_RPU == NODETYPE(Core->Device.Node.Id)) &&
(((u8)XPM_DEVSTATE_RUNNING == DevTcm0A->Node.State) ||
((u8)XPM_DEVSTATE_RUNNING == DevTcm0B->Node.State) ||
((u8)XPM_DEVSTATE_RUNNING == DevTcm1A->Node.State) ||
((u8)XPM_DEVSTATE_RUNNING == DevTcm1B->Node.State)))) {
Device = &Core->Device;
Status = XPmDevice_Reset(Device, PM_RESET_ACTION_ASSERT);
} else {
Status = XST_SUCCESS;
}
done:
return Status;
}
XStatus XPmCore_WakeUp(XPm_Core *Core)
{
XStatus Status = XST_FAILURE;
XPm_Power *PwrNode;
DISABLE_WAKE(Core->SleepMask);
if (((u32)XPM_DEVSTATE_RUNNING != Core->Device.Node.State) &&
(NULL != Core->Device.Power)) {
PwrNode = Core->Device.Power;
Status = PwrNode->HandleEvent(&PwrNode->Node, XPM_POWER_EVENT_PWR_UP);
if (XST_SUCCESS != Status) {
goto done;
}
}
if (NULL != Core->CoreOps && NULL != Core->CoreOps->RestoreResumeAddr) {
Status = Core->CoreOps->RestoreResumeAddr(Core);
if (XST_SUCCESS != Status) {
goto done;
}
}
if ((u32)XPM_DEVSTATE_RUNNING != Core->Device.Node.State) {
if (NULL != Core->Device.ClkHandles) {
Status = XPmClock_Request(Core->Device.ClkHandles);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XPm_DirectPwrUp(Core->Device.Node.Id);
}
done:
return Status;
}
XStatus XPmCore_PwrDwn(XPm_Core *Core)
{
XStatus Status = XST_FAILURE;
XPm_Power *PwrNode;
if ((u32)XPM_DEVSTATE_UNUSED == Core->Device.Node.State) {
Status = XST_SUCCESS;
goto done;
}
if ((u32)XPM_DEVSTATE_SUSPENDING == Core->Device.Node.State) {
DISABLE_WFI(Core->SleepMask);
}
Status = XPmCore_Sleep(Core);
if(Status != XST_SUCCESS) {
goto done;
}
if (NULL != Core->Device.Power) {
PwrNode = Core->Device.Power;
Status = PwrNode->HandleEvent(&PwrNode->Node, XPM_POWER_EVENT_PWR_DOWN);
if (XST_SUCCESS != Status) {
goto done;
}
}
/**
* Since RPU direct power down is skipped in case of power-down,
* wakeup interrupt needs to be enabled here.
*/
if (((u32)XPM_NODETYPE_DEV_CORE_RPU == NODETYPE(Core->Device.Node.Id)) &&
((u32)XPM_DEVSTATE_SUSPENDING == Core->Device.Node.State)) {
ENABLE_WAKE(Core->SleepMask);
}
Core->Device.Node.State = (u8)XPM_DEVSTATE_UNUSED;
done:
return Status;
}
int XPmCore_GetWakeupLatency(const u32 DeviceId, u32 *Latency)
{
int Status = XST_SUCCESS;
XPm_Core *Core = (XPm_Core *)XPmDevice_GetById(DeviceId);
XPm_Power *Power;
u32 Lat = 0;
*Latency = 0;
if (NULL == Core) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((u32)XPM_DEVSTATE_RUNNING == Core->Device.Node.State) {
goto done;
}
*Latency += Core->PwrUpLatency;
if ((u32)XPM_DEVSTATE_SUSPENDING == Core->Device.Node.State) {
*Latency += Core->PwrDwnLatency;
goto done;
}
Power = Core->Device.Power;
if (NULL != Power) {
Status = XPmPower_GetWakeupLatency(Power->Node.Id, &Lat);
if (XST_SUCCESS == Status) {
*Latency += Lat;
}
}
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/versal/xsecure_aes_core_hw.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_aes_hw.h
* This file contains AES core hardware definitions of versal.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.0 vns 03/21/19 Initial release
* 4.2 vns 02/10/20 Added efuse cache DPA mask register address and mask
*
* </pre>
*
* @endcond
******************************************************************************/
#ifndef XSECURE_AES_HW_H
#define XSECURE_AES_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions ****************************/
/**
* AES Base Address
*/
#define XSECURE_AES_BASEADDR (0xF11E0000U)
/**
* Register: XSECURE_AES_STATUS
*/
#define XSECURE_AES_STATUS_OFFSET (0x00000000U)
#define XSECURE_AES_STATUS_CM_ENABLED_SHIFT (12U)
#define XSECURE_AES_STATUS_CM_ENABLED_MASK (0x00001000U)
#define XSECURE_AES_STATUS_BLK_KEY_DEC_DONE_SHIFT (5U)
#define XSECURE_AES_STATUS_BLK_KEY_DEC_DONE_MASK (0x00000020U)
#define XSECURE_AES_STATUS_KEY_INIT_DONE_SHIFT (4U)
#define XSECURE_AES_STATUS_KEY_INIT_DONE_MASK (0x00000010U)
#define XSECURE_AES_STATUS_GCM_TAG_PASS_SHIFT (3U)
#define XSECURE_AES_STATUS_GCM_TAG_PASS_MASK (0x00000008U)
#define XSECURE_AES_STATUS_DONE_SHIFT (2U)
#define XSECURE_AES_STATUS_DONE_MASK (0x00000004U)
#define XSECURE_AES_STATUS_READY_SHIFT (1U)
#define XSECURE_AES_STATUS_READY_MASK (0x00000002)
#define XSECURE_AES_STATUS_BUSY_MASK (0x00000001U)
/**
* Register: XSECURE_AES_KEY_SEL
*/
#define XSECURE_AES_KEY_SEL_OFFSET (0x00000004U)
/**
* Register: XSECURE_AES_KEY_LOAD
*/
#define XSECURE_AES_KEY_LOAD_OFFSET (0x00000008U)
#define XSECURE_AES_KEY_LOAD_VAL_MASK (0x00000001U)
/**
* Register: XSECURE_AES_START_MSG
*/
#define XSECURE_AES_START_MSG_OFFSET (0x0000000CU)
#define XSECURE_AES_START_MSG_VAL_MASK (0x00000001U)
/**
* Register: XSECURE_AES_SOFT_RST
*/
#define XSECURE_AES_SOFT_RST_OFFSET (0x00000010U)
/**
* Register: XSECURE_AES_KEY_CLEAR
*/
#define XSECURE_AES_KEY_CLEAR_OFFSET (0x00000014U)
#define XSECURE_AES_KEY_CLEAR_RESERVED_2_SHIFT (22U)
#define XSECURE_AES_KEY_CLEAR_RESERVED_2_MASK (0xFFC00000U)
#define XSECURE_AES_KEY_CLEAR_PUF_KEY_SHIFT (21U)
#define XSECURE_AES_KEY_CLEAR_PUF_KEY_MASK (0x00200000U)
#define XSECURE_AES_KEY_CLEAR_BBRAM_RED_KEY_SHIFT (20U)
#define XSECURE_AES_KEY_CLEAR_BBRAM_RED_KEY_MASK (0x00100000U)
#define XSECURE_AES_KEY_CLEAR_BH_RED_KEY_SHIFT (19U)
#define XSECURE_AES_KEY_CLEAR_BH_RED_KEY_MASK (0x00080000U)
#define XSECURE_AES_KEY_CLEAR_BH_KEY_SHIFT (18U)
#define XSECURE_AES_KEY_CLEAR_BH_KEY_MASK (0x00040000U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_USER_RED_KEY_1_SHIFT (17U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_USER_RED_KEY_1_MASK (0x00020000U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_USER_RED_KEY_0_SHIFT (16U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_USER_RED_KEY_0_MASK (0x00010000U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_RED_KEY_SHIFT (15U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_RED_KEY_MASK (0x00008000U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_USER_KEY_1_SHIFT (14U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_USER_KEY_1_MASK (0x00004000U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_USER_KEY_0_SHIFT (13U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_USER_KEY_0_MASK (0x00002000U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_KEY_SHIFT (12U)
#define XSECURE_AES_KEY_CLEAR_EFUSE_KEY_MASK (0x00001000U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_7_SHIFT (11U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_7_MASK (0x00000800U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_6_SHIFT (10U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_6_MASK (0x00000400U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_5_SHIFT (9U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_5_MASK (0x00000200U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_4_SHIFT (8U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_4_MASK (0x00000100U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_3_SHIFT (7U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_3_MASK (0x00000080U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_2_SHIFT (6U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_2_MASK (0x00000040U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_1_SHIFT (5U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_1_MASK (0x00000020U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_0_SHIFT (4U)
#define XSECURE_AES_KEY_CLEAR_USER_KEY_0_MASK (0x00000010U)
#define XSECURE_AES_KEY_CLEAR_RESERVED_1_SHIFT (2U)
#define XSECURE_AES_KEY_CLEAR_RESERVED_1_MASK (0x0000000CU)
#define XSECURE_AES_KEY_CLEAR_KUP_KEY_SHIFT (1U)
#define XSECURE_AES_KEY_CLEAR_KUP_KEY_MASK (0x00000002U)
#define XSECURE_AES_KEY_CLEAR_AES_KEY_ZEROIZE_SHIFT (0U)
#define XSECURE_AES_KEY_CLEAR_AES_KEY_ZEROIZE_MASK (0x00000001U)
#define XSECURE_AES_KEY_CLEAR_ALL_AES_KEYS (0x00000000U)
/**
* Register: XSECURE_AES_MODE
*/
#define XSECURE_AES_MODE_OFFSET (0x00000018U)
#define XSECURE_AES_MODE_ENC_DEC_N_MASK (0x00000001U)
#define XSECURE_AES_MODE_ENC (0x00000001U)
/**
* Register: XSECURE_AES_KUP_WR
*/
#define XSECURE_AES_KUP_WR_OFFSET (0x0000001CU)
#define XSECURE_AES_KUP_WR_IV_SAVE_SHIFT (1U)
#define XSECURE_AES_KUP_WR_IV_SAVE_MASK (0x00000002U)
#define XSECURE_AES_KUP_WR_KEY_SAVE_SHIFT (0U)
#define XSECURE_AES_KUP_WR_KEY_SAVE_MASK (0x00000001U)
/**
* Register: XSECURE_AES_IV_0
*/
#define XSECURE_AES_IV_0_OFFSET (0x00000040U)
#define XSECURE_AES_IV_0_VAL_MASK (0xFFFFFFFFU)
/**
* Register: XSECURE_AES_IV_1
*/
#define XSECURE_AES_IV_1_OFFSET (0x00000044U)
/**
* Register: XSECURE_AES_IV_2
*/
#define XSECURE_AES_IV_2_OFFSET (0x00000048U)
/**
* Register: XSECURE_AES_IV_3
*/
#define XSECURE_AES_IV_3_OFFSET (0x0000004CU)
/**
* Register: XSECURE_AES_KEY_SIZE
*/
#define XSECURE_AES_KEY_SIZE_OFFSET (0x00000050U)
#define XSECURE_AES_KEY_SIZE_VAL_MASK (0x00000003U)
/**
* Register: XSECURE_AES_KEY_DEC
*/
#define XSECURE_AES_KEY_DEC_OFFSET (0x00000058U)
#define XSECURE_AES_KEY_DEC_MASK (0xFFFFFFFFU)
/**
* Register: XSECURE_AES_KEY_DEC_TRIG
*/
#define XSECURE_AES_KEY_DEC_TRIG_OFFSET (0x0000005CU)
#define XSECURE_AES_KEY_DEC_TRIG_VAL_MASK (0x00000001U)
/**
* Register: XSECURE_AES_KEY_DEC_SEL
*/
#define XSECURE_AES_KEY_DEC_SEL_OFFSET (0x00000060U)
#define XSECURE_AES_KEY_DEC_SEL_VAL_MASK (0x00000007U)
/**
* Register: XSECURE_AES_KEY_ZEROED_STATUS
*/
#define XSECURE_AES_KEY_ZEROED_STATUS_OFFSET (0x00000064U)
#define XSECURE_AES_KEY_ZEROED_STATUS_RESERVED_2_SHIFT (22U)
#define XSECURE_AES_KEY_ZEROED_STATUS_RESERVED_2_MASK (0xFFC00000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_PUF_KEY_SHIFT (21U)
#define XSECURE_AES_KEY_ZEROED_STATUS_PUF_KEY_MASK (0x00200000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_BBRAM_RED_KEY_SHIFT (20U)
#define XSECURE_AES_KEY_ZEROED_STATUS_BBRAM_RED_KEY_MASK (0x00100000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_BH_RED_KEY_SHIFT (19U)
#define XSECURE_AES_KEY_ZEROED_STATUS_BH_RED_KEY_MASK (0x00080000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_BH_KEY_SHIFT (18U)
#define XSECURE_AES_KEY_ZEROED_STATUS_BH_KEY_MASK (0x00040000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_USER_RED_KEY_1_SHIFT (17U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_USER_RED_KEY_1_MASK (0x00020000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_USER_RED_KEY_0_SHIFT (16U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_USER_RED_KEY_0_MASK (0x00010000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_RED_KEY_SHIFT (15U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_RED_KEY_MASK (0x00008000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_USER_KEY_1_SHIFT (14U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_USER_KEY_1_MASK (0x00004000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_USER_KEY_0_SHIFT (13U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_USER_KEY_0_MASK (0x00002000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_KEY_SHIFT (12U)
#define XSECURE_AES_KEY_ZEROED_STATUS_EFUSE_KEY_MASK (0x00001000U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_7_SHIFT (11U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_7_MASK (0x00000800U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_6_SHIFT (10U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_6_MASK (0x00000400U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_5_SHIFT (9U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_5_MASK (0x00000200U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_4_SHIFT (8U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_4_MASK (0x00000100U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_3_SHIFT (7U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_3_MASK (0x00000080U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_2_SHIFT (6U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_2_MASK (0x00000040U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_1_SHIFT (5U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_1_MASK (0x00000020U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_0_SHIFT (4U)
#define XSECURE_AES_KEY_ZEROED_STATUS_USER_KEY_0_MASK (0x00000010U)
#define XSECURE_AES_KEY_ZEROED_STATUS_RESERVED_1_SHIFT (2U)
#define XSECURE_AES_KEY_ZEROED_STATUS_RESERVED_1_MASK (0x0000000CU)
#define XSECURE_AES_KEY_ZEROED_STATUS_KUP_KEY_SHIFT (1U)
#define XSECURE_AES_KEY_ZEROED_STATUS_KUP_KEY_MASK (0x00000002U)
#define XSECURE_AES_KEY_ZEROED_STATUS_AES_KEY_ZEROED_SHIFT (0U)
#define XSECURE_AES_KEY_ZEROED_STATUS_AES_KEY_ZEROED_MASK (0x00000001U)
/**
* Register: XSECURE_AES_KEY_LOCK_STATUS
*/
#define XSECURE_AES_KEY_LOCK_STATUS_OFFSET (0x00000068U)
#define XSECURE_AES_KEY_LOCK_STATUS_BBRAM_MASK (0x00000002U)
#define XSECURE_AES_KEY_LOCK_STATUS_EFUSE_MASK (0x00000001U)
/**
* Register: XSECURE_AES_AAD
*/
#define XSECURE_AES_AAD_OFFSET (0x0000006CU)
#define XSECURE_AES_AAD_HDR_PAYLOAD_N_SHIFT (0U)
#define XSECURE_AES_AAD_HDR_PAYLOAD_N_WIDTH (1U)
#define XSECURE_AES_AAD_HDR_PAYLOAD_N_MASK (0x00000001U)
/**
* Register: XSECURE_AES_USER_SEL
*/
#define XSECURE_AES_USER_SEL_OFFSET (0x00000070U)
#define XSECURE_AES_USER_SEL_VAL_SHIFT (0U)
#define XSECURE_AES_USER_SEL_VAL_WIDTH (3U)
#define XSECURE_AES_USER_SEL_VAL_MASK (0x00000007U)
/**
* Register: XSECURE_AES_USER_KEY_CRC
*/
#define XSECURE_AES_USER_KEY_CRC (0x00000074U)
#define XSECURE_AES_USER_KEY_CRC_VAL_SHIFT (0U)
#define XSECURE_AES_USER_KEY_CRC_VAL_WIDTH (32U)
#define XSECURE_AES_USER_KEY_CRC_VAL_MASK (0xFFFFFFFFU)
/**
* Register: XSECURE_AES_USER_KEY_CRC_STATUS
*/
#define XSECURE_AES_USER_KEY_CRC_STATUS (0x00000078U)
#define XSECURE_AES_USER_KEY_CRC_STATUS_DONE_SHIFT (1U)
#define XSECURE_AES_USER_KEY_CRC_STATUS_DONE_WIDTH (1U)
#define XSECURE_AES_USER_KEY_CRC_STATUS_DONE_MASK (0x00000002U)
#define XSECURE_AES_USER_KEY_CRC_STATUS_PASS_SHIFT (0U)
#define XSECURE_AES_USER_KEY_CRC_STATUS_PASS_WIDTH (1U)
#define XSECURE_AES_USER_KEY_CRC_STATUS_PASS_MASK (0x00000001U)
/**
* Register: XSECURE_AES_CM_EN
*/
#define XSECURE_AES_CM_EN_OFFSET (0x0000007CU)
#define XSECURE_AES_CM_EN_VAL_MASK (0x00000001U)
/**
* Register: XSECURE_AES_SPLIT_CFG
*/
#define XSECURE_AES_SPLIT_CFG_OFFSET (0x00000080U)
#define XSECURE_AES_SPLIT_CFG_KEY_SPLIT_SHIFT (1U)
#define XSECURE_AES_SPLIT_CFG_KEY_SPLIT_MASK (0x00000002U)
#define XSECURE_AES_SPLIT_CFG_KEY_SPLIT (0x00000002U)
#define XSECURE_AES_SPLIT_CFG_DATA_SPLIT_SHIFT (0U)
#define XSECURE_AES_SPLIT_CFG_DATA_SPLIT_MASK (0x00000001U)
#define XSECURE_AES_SPLIT_CFG_DATA_SPLIT (0x00000001U)
#define XSECURE_AES_SPLIT_CFG_DATA_KEY_DISABLE (0U)
/**
* Register: XSECURE_AES_DATA_SWAP
*/
#define XSECURE_AES_DATA_SWAP_OFFSET (0x00000084U)
#define XSECURE_AES_DATA_SWAP_VAL_MASK 0x00000001U
#define XSECURE_AES_DATA_SWAP_VAL_DISABLE (0x00000000U)
/**
* Register: AES_BH_KEY_0
*/
#define XSECURE_AES_BH_KEY_0_OFFSET (0x000000F0U)
/**
* Register: AES_USER_KEY_0_0
*/
#define XSECURE_AES_USER_KEY_0_0_OFFSET (0x00000110U)
/**
* Register: AES_USER_KEY_1_0
*/
#define XSECURE_AES_USER_KEY_1_0_OFFSET (0x00000130U)
/**
* Register: AES_USER_KEY_2_0
*/
#define XSECURE_AES_USER_KEY_2_0_OFFSET (0x00000150U)
/**
* Register: AES_USER_KEY_3_0
*/
#define XSECURE_AES_USER_KEY_3_0_OFFSET (0x00000170U)
/**
* Register: AES_USER_KEY_4_0
*/
#define XSECURE_AES_USER_KEY_4_0_OFFSET (0x00000190U)
/**
* Register: AES_USER_KEY_5_0
*/
#define XSECURE_AES_USER_KEY_5_0_OFFSET (0x000001B0U)
/**
* Register: AES_USER_KEY_6_0
*/
#define XSECURE_AES_USER_KEY_6_0_OFFSET (0x000001D0U)
/**
* Register: XSECURE_AES_USER_KEY_7_0
*/
#define XSECURE_AES_USER_KEY_7_0_OFFSET (0x000001F0U)
/**
* Register: XSECURE_AES_ECO
*/
#define XSECURE_AES_ECO_OFFSET (0x00000230U)
/* Efuse Cache Register : SECURITY_MISC_1 */
#define XSECURE_EFUSE_SECURITY_MISC1 (0xF12500E8U)
#define XSECURE_EFUSE_DPA_CM_DIS_MASK (0xFFFF0000U)
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_AES_HW_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_7/src/xusbpsu_intr.c
/******************************************************************************
* Copyright (C) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_intr.c
* @addtogroup usbpsu_v1_7
* @{
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 sg 06/06/16 First release
* 1.3 vak 04/03/17 Added CCI support for USB
* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code
* for all USB IPs
* myk 12/01/18 Added hibernation support
* vak 22/01/18 Added changes for supporting microblaze platform
* vak 13/03/18 Moved the setup interrupt system calls from driver to
* example.
* 1.4 vak 30/05/18 Removed xusb_wrapper files
* 1.7 pm 23/03/20 Restructured the code for more readability and modularity
* pm 25/03/20 Add clocking support
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xusbpsu_local.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
* Disconnect Interrupt handler.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
InstancePtr->IsConfigDone = 0U;
InstancePtr->AppData->Speed = XUSBPSU_SPEED_UNKNOWN;
#ifdef XUSBPSU_HIBERNATION_ENABLE
/* In USB 2.0, to avoid hibernation interrupt at the time of connection
* clear KEEP_CONNECT bit.
*/
if (InstancePtr->HasHibernation == TRUE) {
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
if ((RegVal & XUSBPSU_DCTL_KEEP_CONNECT) != (u32)0U) {
RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
}
}
#endif
/* Call the handler if necessary */
if (InstancePtr->DisconnectIntrHandler != NULL) {
InstancePtr->DisconnectIntrHandler(InstancePtr->AppData);
}
}
/****************************************************************************/
/**
* Reset Interrupt handler.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
u32 Index;
InstancePtr->AppData->State = XUSBPSU_STATE_DEFAULT;
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
InstancePtr->TestMode = 0U;
XUsbPsu_StopActiveTransfers(InstancePtr);
XUsbPsu_ClearStallAllEp(InstancePtr);
for (Index = 0U; Index <
(InstancePtr->NumInEps + InstancePtr->NumOutEps);
Index++)
{
InstancePtr->eps[Index].EpStatus = 0U;
}
InstancePtr->IsConfigDone = 0U;
/* Reset device address to zero */
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
/* Call the handler if necessary */
if (InstancePtr->ResetIntrHandler != NULL) {
InstancePtr->ResetIntrHandler(InstancePtr->AppData);
}
}
/****************************************************************************/
/**
* Handles Interrupts of Control Endpoints EP0 OUT and EP0 IN.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is a pointer to the Endpoint event occurred in core.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Event != NULL);
switch (Event->Endpoint_Event) {
case XUSBPSU_DEPEVT_XFERCOMPLETE:
XUsbPsu_Ep0XferComplete(InstancePtr, Event);
break;
case XUSBPSU_DEPEVT_XFERNOTREADY:
XUsbPsu_Ep0XferNotReady(InstancePtr, Event);
break;
case XUSBPSU_DEPEVT_XFERINPROGRESS:
case XUSBPSU_DEPEVT_STREAMEVT:
case XUSBPSU_DEPEVT_EPCMDCMPLT:
break;
default:
/* Default case is a required MIRSA-C guideline. */
break;
}
}
/****************************************************************************/
/**
* Connection Done Interrupt handler.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
u16 Size;
u8 Speed;
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
Speed = (u8)(RegVal & XUSBPSU_DSTS_CONNECTSPD);
InstancePtr->AppData->Speed = Speed;
switch (Speed) {
case XUSBPSU_DCFG_SUPERSPEED:
#ifdef XUSBPSU_DEBUG
xil_printf("Super Speed\r\n");
#endif
Size = 512U;
InstancePtr->AppData->Speed = XUSBPSU_SPEED_SUPER;
break;
case XUSBPSU_DCFG_HIGHSPEED:
#ifdef XUSBPSU_DEBUG
xil_printf("High Speed\r\n");
#endif
Size = 64U;
InstancePtr->AppData->Speed = XUSBPSU_SPEED_HIGH;
break;
case XUSBPSU_DCFG_FULLSPEED2:
case XUSBPSU_DCFG_FULLSPEED1:
#ifdef XUSBPSU_DEBUG
xil_printf("Full Speed\r\n");
#endif
Size = 64U;
InstancePtr->AppData->Speed = XUSBPSU_SPEED_FULL;
break;
case XUSBPSU_DCFG_LOWSPEED:
#ifdef XUSBPSU_DEBUG
xil_printf("Low Speed\r\n");
#endif
Size = 64U;
InstancePtr->AppData->Speed = XUSBPSU_SPEED_LOW;
break;
default :
Size = 64U;
break;
}
if (InstancePtr->AppData->Speed == XUSBPSU_SPEED_SUPER) {
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal &= ~XUSBPSU_DCTL_HIRD_THRES_MASK;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
}
(void)XUsbPsu_EnableControlEp(InstancePtr, Size);
(void)XUsbPsu_RecvSetup(InstancePtr);
#ifdef XUSBPSU_HIBERNATION_ENABLE
/* In USB 2.0, to avoid hibernation interrupt at the time of connection
* clear KEEP_CONNECT bit.
*/
if (InstancePtr->HasHibernation == TRUE) {
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
if ((RegVal & XUSBPSU_DCTL_KEEP_CONNECT) == (u32)0U) {
RegVal |= XUSBPSU_DCTL_KEEP_CONNECT;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
}
}
#endif
}
/****************************************************************************/
/**
* Link Status Change Interrupt handler.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param EvtInfo is Event information.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr, u32 EvtInfo)
{
u32 State = EvtInfo & (u32)XUSBPSU_LINK_STATE_MASK;
InstancePtr->LinkState = (u8)State;
}
/****************************************************************************/
/**
* Processes an Event entry in Event Buffer.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is the Event entry.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr,
const union XUsbPsu_Event *Event)
{
if (Event->Type.Is_DevEvt == 0U) {
/* End point Specific Event */
XUsbPsu_EpEvent(InstancePtr, &Event->Epevt);
return;
}
switch (Event->Type.Type) {
case XUSBPSU_EVENT_TYPE_DEV:
/* Device Specific Event */
XUsbPsu_DeviceEvent(InstancePtr, &Event->Devt);
break;
/* Carkit and I2C events not supported now */
default:
/* Made for Misra-C Compliance. */
break;
}
}
/*****************************************************************************/
/**
* @brief
* Enables an interrupt in Event Enable RegValister.
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on
* @param Mask is the OR of any Interrupt Enable Masks:
* - XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
* - XUSBPSU_DEVTEN_EVNTOVERFLOWEN
* - XUSBPSU_DEVTEN_CMDCMPLTEN
* - XUSBPSU_DEVTEN_ERRTICERREN
* - XUSBPSU_DEVTEN_SOFEN
* - XUSBPSU_DEVTEN_EOPFEN
* - XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
* - XUSBPSU_DEVTEN_WKUPEVTEN
* - XUSBPSU_DEVTEN_ULSTCNGEN
* - XUSBPSU_DEVTEN_CONNECTDONEEN
* - XUSBPSU_DEVTEN_USBRSTEN
* - XUSBPSU_DEVTEN_DISCONNEVTEN
*
* @return None
*
* @note None.
*
******************************************************************************/
void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
{
u32 RegVal;
Xil_AssertVoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
RegVal |= Mask;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
}
/*****************************************************************************/
/**
* @brief
* Disables an interrupt in Event Enable RegValister.
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
* @param Mask is the OR of Interrupt Enable Masks
* - XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
* - XUSBPSU_DEVTEN_EVNTOVERFLOWEN
* - XUSBPSU_DEVTEN_CMDCMPLTEN
* - XUSBPSU_DEVTEN_ERRTICERREN
* - XUSBPSU_DEVTEN_SOFEN
* - XUSBPSU_DEVTEN_EOPFEN
* - XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
* - XUSBPSU_DEVTEN_WKUPEVTEN
* - XUSBPSU_DEVTEN_ULSTCNGEN
* - XUSBPSU_DEVTEN_CONNECTDONEEN
* - XUSBPSU_DEVTEN_USBRSTEN
* - XUSBPSU_DEVTEN_DISCONNEVTEN
*
* @return None
*
* @note None.
*
******************************************************************************/
void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
{
u32 RegVal;
Xil_AssertVoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
RegVal &= ~Mask;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
}
/****************************************************************************/
/**
* @brief
* Main Interrupt Handler.
*
* @param XUsbPsuInstancePtr is a void pointer to the XUsbPsu instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr)
{
struct XUsbPsu *InstancePtr;
struct XUsbPsu_EvtBuffer *Evt;
u32 Count;
u32 RegVal;
InstancePtr = (struct XUsbPsu *)XUsbPsuInstancePtr;
Xil_AssertVoid(InstancePtr != NULL);
Evt = &InstancePtr->Evt;
Count = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U));
Count &= XUSBPSU_GEVNTCOUNT_MASK;
/*
* As per data book software should only process Events if Event count
* is greater than zero.
*/
if (Count == 0U) {
return;
}
Evt->Count = Count;
Evt->Flags |= XUSBPSU_EVENT_PENDING;
/* Mask event interrupt */
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U));
RegVal |= XUSBPSU_GEVNTSIZ_INTMASK;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U), RegVal);
/* Processes events in an Event Buffer */
XUsbPsu_EventBufferHandler(InstancePtr);
}
#ifdef XUSBPSU_HIBERNATION_ENABLE
/****************************************************************************/
/**
* @brief
* Wakeup Interrupt Event Handler.
*
* @param XUsbPsuInstancePtr is a pointer of driver Instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_WakeUpIntrHandler(void *XUsbPsuInstancePtr)
{
u32 RegVal;
u32 retries;
struct XUsbPsu *InstancePtr = (struct XUsbPsu *)XUsbPsuInstancePtr;
#if defined (XCLOCKING)
/* enable ref clocks */
if (InstancePtr->IsHibernated) {
Xil_ClockEnable(InstancePtr->ConfigPtr->RefClk);
}
#endif
RegVal = XUsbPsu_ReadLpdReg(RST_LPD_TOP);
if (InstancePtr->ConfigPtr->DeviceId == (u16)XPAR_XUSBPSU_0_DEVICE_ID) {
XUsbPsu_WriteLpdReg(RST_LPD_TOP,
(u32)(RegVal & ~(u32)USB0_CORE_RST));
}
/* change power state to D0 */
XUsbPsu_WriteVendorReg(XIL_REQ_PWR_STATE, XIL_REQ_PWR_STATE_D0);
/* wait till current state is changed to D0 */
retries = (u32)XUSBPSU_PWR_STATE_RETRIES;
while (retries > 0U) {
RegVal = XUsbPsu_ReadVendorReg(XIL_CUR_PWR_STATE);
if ((RegVal & XIL_CUR_PWR_STATE_BITMASK) ==
XIL_CUR_PWR_STATE_D0) {
break;
}
XUsbPsu_Sleep(XUSBPSU_TIMEOUT);
retries = retries - 1U;
}
if (retries == 0U) {
xil_printf("Failed to change power state to D0\r\n");
return;
}
/* ask core to restore non-sticky registers */
if (XUsbPsu_CoreRegRestore(InstancePtr) == XST_FAILURE) {
return;
}
/* start controller */
if (XUsbPsu_Start(InstancePtr) == XST_FAILURE) {
xil_printf("Failed to start core on wakeup\r\n");
return;
}
/* Wait until device controller is ready */
if (XUsbPsu_WaitClearTimeout(InstancePtr, XUSBPSU_DSTS,
XUSBPSU_DSTS_DCNRD, XUSBPSU_CTRL_RDY_RETRIES) == XST_FAILURE) {
xil_printf("Failed to ready device controller\r\n");
return;
}
/*
* there can be spurious wakeup events , so wait for some time and check
* the link state
*/
XUsbPsu_Sleep(XUSBPSU_TIMEOUT * 10U);
/* Processes link state events for hibernation */
XUsbPsu_HibernationStateIntr(InstancePtr);
xil_printf("We are back from hibernation!\r\n");
}
#endif
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/zynqmp/client/common/pm_clock.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file pm_clock.h
*
* PM Definitions of clocks - for xilpm internal purposes only
*****************************************************************************/
#ifndef PM_CLOCKS_H_
#define PM_CLOCKS_H_
#include <xil_types.h>
#include <xstatus.h>
#include "pm_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
XStatus XPm_GetClockParentBySelect(const enum XPmClock clock,
const u32 select,
enum XPmClock* const parent);
XStatus XPm_GetSelectByClockParent(const enum XPmClock clock,
const enum XPmClock parent,
u32* const select);
u8 XPm_GetClockDivType(const enum XPmClock clock);
u8 XPm_MapDivider(const enum XPmClock clock,
const u32 div,
u32* const div0,
u32* const div1);
#ifdef __cplusplus
}
#endif
#endif /* PM_CLOCKS_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_core.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_CORE_H_
#define XPM_CORE_H_
#include "xpm_api.h"
#include "xpm_device.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MAX_CORE_REGS 3
typedef struct XPm_Core XPm_Core;
/* Core Operations */
struct XPm_CoreOps {
int (*RestoreResumeAddr)(XPm_Core *Core);
int (*HasResumeAddr) (XPm_Core *Core);
XStatus (*RequestWakeup)(XPm_Core *Core, u32 SetAddress, u64 Address);
XStatus (*PowerDown) (XPm_Core *Core);
};
/**
* The processor core class. This is the base class for all processor cores.
*/
struct XPm_Core {
XPm_Device Device; /**< Device: Base class */
u32 ImageId; /**< ImageId: Image ID */
u16 PwrUpLatency;
u16 PwrDwnLatency;
u64 ResumeAddr;
struct XPm_CoreOps *CoreOps; /**< Core operations */
u8 DebugMode; /**< DebugMode: Debugger is connected */
u8 Ipi; /**< IPI channel */
u8 SleepMask;
u8 PwrDwnMask;
};
/************************** Function Prototypes ******************************/
XStatus XPmCore_Init(XPm_Core *Core, u32 Id, XPm_Power *Power,
XPm_ClockNode *Clock, XPm_ResetNode *Reset, u8 IpiCh,
struct XPm_CoreOps *Ops);
XStatus XPmCore_PwrDwn(XPm_Core *Core);
XStatus XPmCore_WakeUp(XPm_Core *Core);
int XPmCore_GetWakeupLatency(const u32 DeviceId, u32 *Latency);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_CORE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/rfdc_v8_0/src/xrfdc.c
/******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrfdc.c
* @addtogroup rfdc_v8_0
* @{
*
* Contains the interface functions of the XRFdc driver.
* See xrfdc.h for a detailed description of the device and driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.0 sk 05/16/17 Initial release
* 2.0 sk 08/09/17 Fixed coarse Mixer configuration settings
* CR# 977266, 977872.
* Return error for Slice Event on 4G ADC Block.
* 08/16/17 Add support for SYSREF and PL event sources.
* 08/18/17 Add API to enable and disable FIFO.
* 08/23/17 Add API to configure Nyquist zone.
* 08/30/17 Add additional info to BlockStatus.
* 08/30/17 Add support for Coarse Mixer BYPASS mode.
* 08/31/17 Removed Tile Reset Assert and Deassert.
* 09/07/17 Add support for negative NCO freq.
* 09/15/17 Fixed NCO freq precision issue.
* 09/15/17 Fixed Immediate Event source issue and also
* updated the Immediate Macro value to 0.
* 2.1 sk 09/15/17 Remove Libmetal library dependency for MB.
* sk 09/25/17 Modified XRFdc_GetBlockStatus API to give
* correct information and also updates the
* description for Vector Param in intr handler
* Add API to get Output current and removed
* GetTermVoltage and GetOutputCurr inline functions.
* 2.2 sk 10/05/17 Fixed XRFdc_GetNoOfADCBlocks API for 4GSPS.
* Enable the decoder clock based on decoder mode.
* Add API to get the current FIFO status.
* Updated XRFdc_DumpRegs API for better readability
* of output register dump.
* Add support for 4GSPS CoarseMixer frequency.
* 10/11/17 Modify float types to double to increase precision.
* 10/12/17 Update BlockStatus API to give current status.
* In BYPASS mode, input datatype can be Real or IQ,
* hence checked both while reading the mixer mode.
* 10/17/17 Fixed Set Threshold API Issue.
* 2.3 sk 11/06/17 Fixed PhaseOffset truncation issue.
* Provide user configurability for FineMixerScale.
* 11/08/17 Return error for DAC R2C mode and ADC C2R mode.
* 11/20/17 Fixed StartUp, Shutdown and Reset API for Tile_Id -1.
* 11/20/17 Remove unwanted ADC block checks in 4GSPS mode.
* 3.0 sk 12/11/17 Added DDC and DUC support.
* 12/13/17 Add CoarseMixMode field in Mixer_Settings structure.
* 12/15/17 Add support to switch calibration modes.
* 12/15/17 Add support for mixer frequencies > Fs/2 and < -Fs/2.
* sg 13/01/18 Added PLL and external clock switch support.
* Added API to get PLL lock status.
* Added API to get clock source.
* 3.1 jm 01/24/18 Add Multi-tile sync support.
* sk 01/25/18 Updated Set and Get Interpolation/Decimation factor
* API's to consider the actual factor value.
* 3.2 sk 02/02/18 Add API's to configure inverse-sinc.
* sk 02/27/18 Add API's to configure Multiband.
* sk 03/09/18 Update PLL structure in XRFdc_DynamicPLLConfig API.
* sk 03/09/18 Update ADC and DAC datatypes in Mixer API and use
* input datatype for ADC in threshold and QMC APIs.
* sk 03/09/18 Removed FIFO disable check in DDC and DUC APIs.
* sk 03/09/18 Add support for Marker event source for DAC block.
* sk 03/22/18 Updated PLL settings based on latest IP values.
* 4.0 sk 04/17/18 Corrected Set/Get MixerSettings API description for
* FineMixerScale parameter.
* sk 04/19/18 Enable VCO Auto selection while configuring the clock.
* sk 04/24/18 Add API to get PLL Configurations.
* sk 04/24/18 Add API to get the Link Coupling mode.
* sk 04/28/18 Implement timeouts for PLL Lock, Startup and shutdown.
* sk 05/30/18 Removed CalibrationMode check for DAC.
* sk 06/05/18 Updated minimum Ref clock value to 102.40625MHz.
* 5.0 sk 06/25/18 Update DAC min sampling rate to 500MHz and also update
* VCO Range, PLL_DIVIDER and PLL_FPDIV ranges.
* sk 06/25/18 Add XRFdc_GetFabClkOutDiv() API to read fabric clk div.
* Add Inline APIs XRFdc_CheckBlockEnabled(),
* XRFdc_CheckTileEnabled().
* sk 07/06/18 Add support to dump HSCOM regs in XRFdc_DumpRegs() API
* sk 07/12/18 Fixed Multiband crossbar settings in C2C mode.
* sk 07/19/18 Add MixerType member to MixerSettings structure and
* Update Mixer Settings APIs to consider the MixerType
* variable.
* sk 07/19/18 Add XRFdc_GetMultibandConfig() API to read Multiband
* configuration.
* sk 07/20/18 Update the APIs to check the corresponding section
* (Digital/Analog)enable/disable.
* sk 07/26/18 Fixed Doxygen, coverity warnings.
* sk 08/03/18 Fixed MISRAC warnings.
* sk 08/24/18 Move mixer related APIs to xrfdc_mixer.c file.
* Define asserts for Linux, Re-arranged XRFdc_RestartIPSM,
* XRFdc_CfgInitialize() and XRFdc_MultiBand() APIs.
* Reorganize the code to improve readability and
* optimization.
* sk 09/24/18 Update powerup-state value based on PLL mode in
* XRFdc_DynamicPLLConfig() API.
* sk 10/10/18 Check for DigitalPath enable in XRFdc_GetNyquistZone()
* and XRFdc_GetCalibrationMode() APIs for Multiband.
* sk 10/13/18 Add support to read the REFCLKDIV param from design.
* Update XRFdc_SetPLLConfig() API to support range of
* REF_CLK_DIV values(1 to 4).
* 5.1 cog 01/29/19 Replace structure reference ADC checks with
* function.
* cog 01/29/19 Added XRFdc_SetDither() and XRFdc_GetDither() APIs.
* cog 01/29/19 Rename DataType for mixer input to MixerInputDataType
* for readability.
* cog 01/29/19 Refactoring of interpolation and decimation APIs and
* changed fabric rate for decimation X8 for non-high speed ADCs.
* cog 01/29/19 New inline functions to determine max & min sampling rates
* rates in PLL range checking.
* 6.0 cog 02/17/19 Added decimation & interpolation modes
* 02/17/19 Added Inverse-Sinc Second Nyquist Zone Support
* cog 02/17/19 Added new clock Distribution functionality.
* cog 02/17/19 Refactored to improve delay balancing in clock
* distribution.
* cog 02/17/19 Added delay calculation & metal log messages.
* cog 02/17/19 Added intratile clock settings.
* cog 02/17/19 Moved multiband to a new file xrfdc_mb.c
* cog 02/17/19 Moved clocking functionality to a new file xrfdc_clock.c
* cog 02/17/19 Added XRFdc_SetIMRPassMode() and XRFdc_SetIMRPassMode() APIs
* cog 02/17/19 Added XRFdc_SetDACMode() and XRFdc_GetDACMode() APIs
* cog 02/17/19 Added XRFdc_SetSignalDetector() and XRFdc_GetSignalDetector() APIs.
* cog 02/17/19 Added XRFdc_DisableCoefficientsOverride(), XRFdc_SetCalCoefficients
* and XRFdc_GetCalCoefficients APIs.
* cog 02/21/19 Added XRFdc_SetCalFreeze() and XRFdc_GetCalFreeze() APIs.
* cog 04/09/19 Changed calibration coefficient override control register for OCB1.
* cog 04/15/19 Rename XRFdc_SetDACMode() and XRFdc_GetDACMode() APIs to
* XRFdc_SetDataPathMode() and XRFdc_GetDataPathMode() respectively.
* cog 04/30/19 Made Changes to the bypass calibration functionality to support Gen2
* and below.
* 7.0 cog 05/13/19 Formatting changes.
* cog 07/16/19 Added XRFdc_SetDACOpCurr() API.
* cog 07/18/19 Added XRFdc_S/GetDigitalStepAttenuator() APIs.
* cog 07/25/19 Baremetal Region mapping now taken care of in XRFdc_RegisterMetal().
* cog 07/25/19 Moved XRFDC_PLL_LOCK_DLY_CNT macro to header file.
* cog 07/26/19 Added new XRFdc_S/GetLegacyCompatibilityMode() APIs.
* cog 08/02/19 Formatting changes and added a MACRO for the IP generation.
* cog 09/01/19 Renamed XRFdc_SetDACOpCurr() to XRFdc_SetDACVOP(). Also explicitly set
* API to use register values rather than from fabric.
* cog 09/01/19 Added support for VOP in XRFdc_GetOutputCurr().
* cog 09/01/19 Rename new XRFdc_S/GetLegacyCompatibilityMode() APIs to
* XRFdc_S/GetDACCompMode().
* cog 09/01/19 Rename XRFdc_S/GetDigitalStepAttenuator() APIs to XRFdc_S/GetDSA().
* Also, refactored DSA to use struct and absolute value for Attenuation.
* cog 09/18/19 Wider mask now needed for DAC Fabric Rate.
* cog 09/19/19 Calibration mode 1 does not need the frequency shifting workaround
* for Gen 3 devices.
* cog 10/02/19 Added explicit clock divider for datapath modes.
* cog 10/02/19 The register value for the link coupling is inverted in Gen 3 Devices.
* cog 10/18/19 DSA was checking DAC tile rather than ADC.
* cog 10/18/19 Fix GCB read indexing issue with HSADC devices & TSCB coefficients.
* 7.1 cog 11/14/19 Increased ADC fabric read rate to 12 words per cycle for Gen 3 devices.
* cog 11/15/19 Added calibration mode support for Gen 3 devices and fixed issue with going
* to calibration mode 1 when in real mode.
* cog 11/28/19 Datapath "Mode 2" is now half bandwith with low pass IMR (previously it was
* full bandwidth, no IMR, even Nyquist zone).
* cog 11/28/19 Set defalult compatibility setting when moving to Bypass Mode (Mode 4).
* cog 11/28/19 Prevent setting non compliant interpolation rates when in the bypass
* datapath mode.
* cog 12/19/19 Update FIFO widths for higher interpolation & decimation factors.
* cog 12/20/19 Metal log messages are now more descriptive.
* cog 01/08/20 Added programmable hysteresis for counters ADC signal detector.
* cog 01/23/20 Calibration modes for Gen 3 were inverted.
* cog 01/23/20 Fixed offset and bit for GCB calibration override operations in Gen 3 Devices.
* cog 01/29/20 Fixed metal log typos.
* 8.0 cog 02/10/20 Updated addtogroup.
* cog 02/20/20 Adjust FIFO delays for clock gated interpolation/decimation rates.
* cog 03/13/20 Fixed issue where over threshold flag was asserting as soon as the threshold
* settings are applied.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xrfdc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
static u32 XRFdc_RestartIPSM(XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Start, u32 End);
static void StubHandler(void *CallBackRefPtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 StatusEvent);
static void XRFdc_ADCInitialize(XRFdc *InstancePtr);
static void XRFdc_DACInitialize(XRFdc *InstancePtr);
static void XRFdc_DACMBConfigInit(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id);
static void XRFdc_ADCMBConfigInit(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id);
static void XRFdc_UpdatePLLStruct(XRFdc *InstancePtr, u32 Type, u32 Tile_Id);
static u32 XRFdc_GetADCBlockStatus(XRFdc *InstancePtr, u32 BaseAddr, u32 Tile_Id, u32 Block_Id,
XRFdc_BlockStatus *BlockStatusPtr);
static u32 XRFdc_GetDACBlockStatus(XRFdc *InstancePtr, u32 BaseAddr, u32 Tile_Id, u32 Block_Id,
XRFdc_BlockStatus *BlockStatusPtr);
static void XRFdc_DumpHSCOMRegs(XRFdc *InstancePtr, u32 Type, int Tile_Id);
static void XRFdc_DumpDACRegs(XRFdc *InstancePtr, int Tile_Id);
static void XRFdc_DumpADCRegs(XRFdc *InstancePtr, int Tile_Id);
static u32 XRFdc_WaitForRestartClr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 BaseAddr, u32 End);
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Initializes a specific XRFdc instance such that the driver is ready to use.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param ConfigPtr is a reference to a structure containing information
* about xrfdc. This function initializes an InstancePtr object
* for a specific device specified by the contents of Config.
*
* @return
* - XRFDC_SUCCESS if successful.
*
* @note The user needs to first call the XRFdc_LookupConfig() API
* which returns the Configuration structure pointer which is
* passed as a parameter to the XRFdc_CfgInitialize() API.
*
******************************************************************************/
u32 XRFdc_CfgInitialize(XRFdc *InstancePtr, XRFdc_Config *ConfigPtr)
{
u32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
#ifdef __BAREMETAL__
/*for cases where we haven't registered a custom device*/
if (InstancePtr->io == NULL) {
InstancePtr->io = (struct metal_io_region *)metal_allocate_memory(sizeof(struct metal_io_region));
metal_io_init(InstancePtr->io, (void *)(metal_phys_addr_t)ConfigPtr->BaseAddr, &ConfigPtr->BaseAddr,
XRFDC_REGION_SIZE, (unsigned)(-1), 0, NULL);
}
#endif
/*
* Set the values read from the device config and the base address.
*/
InstancePtr->BaseAddr = ConfigPtr->BaseAddr;
InstancePtr->RFdc_Config = *ConfigPtr;
InstancePtr->ADC4GSPS = ConfigPtr->ADCType;
InstancePtr->StatusHandler = StubHandler;
/* Initialize ADC */
XRFdc_ADCInitialize(InstancePtr);
/* Initialize DAC */
XRFdc_DACInitialize(InstancePtr);
/*
* Indicate the instance is now ready to use and
* initialized without error.
*/
InstancePtr->IsReady = XRFDC_COMPONENT_IS_READY;
Status = XRFDC_SUCCESS;
return Status;
}
/*****************************************************************************/
/**
*
* Initialize ADC Tiles.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
*
* @return
* - None.
*
* @note Static API used to initialize ADC Tiles
*
******************************************************************************/
static void XRFdc_ADCInitialize(XRFdc *InstancePtr)
{
u32 Tile_Id;
u32 Block_Id;
u8 MixerType;
for (Tile_Id = XRFDC_TILE_ID0; Tile_Id < XRFDC_TILE_ID4; Tile_Id++) {
InstancePtr->ADC_Tile[Tile_Id].NumOfADCBlocks = 0U;
for (Block_Id = XRFDC_BLK_ID0; Block_Id < XRFDC_BLK_ID4; Block_Id++) {
if (XRFdc_IsADCBlockEnabled(InstancePtr, Tile_Id, Block_Id) != 0U) {
InstancePtr->ADC_Tile[Tile_Id].NumOfADCBlocks += 1U;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Analog_Datapath[Block_Id].AnalogPathEnabled =
XRFDC_ANALOGPATH_ENABLE;
}
/* Initialize Data Type */
if (InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].ADCBlock_Analog_Config[Block_Id].MixMode ==
XRFDC_MIXER_MODE_BYPASS) {
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].MixerInputDataType =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id]
.ADCBlock_Digital_Config[Block_Id]
.MixerInputDataType;
} else {
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].MixerInputDataType =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id]
.ADCBlock_Analog_Config[Block_Id]
.MixMode;
}
/* Initialize MixerType */
MixerType = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id]
.ADCBlock_Digital_Config[Block_Id]
.MixerType;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].Mixer_Settings.MixerType =
MixerType;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].ConnectedIData = -1;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].ConnectedQData = -1;
InstancePtr->ADC_Tile[Tile_Id].MultibandConfig =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].MultibandConfig;
if (XRFdc_IsADCDigitalPathEnabled(InstancePtr, Tile_Id, Block_Id) != 0U) {
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].DigitalPathAvailable =
XRFDC_DIGITALPATH_ENABLE;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].DigitalPathEnabled =
XRFDC_DIGITALPATH_ENABLE;
/* Initialize ConnectedI/QData, MB Config */
XRFdc_ADCMBConfigInit(InstancePtr, Tile_Id, Block_Id);
}
}
/* Initialize PLL Structure */
XRFdc_UpdatePLLStruct(InstancePtr, XRFDC_ADC_TILE, Tile_Id);
}
}
/*****************************************************************************/
/**
*
* Initialize DAC Tiles.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
*
* @return
* - None.
*
* @note Static API used to initialize DAC Tiles
*
******************************************************************************/
static void XRFdc_DACInitialize(XRFdc *InstancePtr)
{
u32 Tile_Id;
u32 Block_Id;
u8 MixerType;
for (Tile_Id = XRFDC_TILE_ID0; Tile_Id < XRFDC_TILE_ID4; Tile_Id++) {
InstancePtr->DAC_Tile[Tile_Id].NumOfDACBlocks = 0U;
for (Block_Id = XRFDC_BLK_ID0; Block_Id < XRFDC_BLK_ID4; Block_Id++) {
if (XRFdc_IsDACBlockEnabled(InstancePtr, Tile_Id, Block_Id) != 0U) {
InstancePtr->DAC_Tile[Tile_Id].NumOfDACBlocks += 1U;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Analog_Datapath[Block_Id].AnalogPathEnabled =
XRFDC_ANALOGPATH_ENABLE;
}
/* Initialize Data Type */
if (InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].DACBlock_Analog_Config[Block_Id].MixMode ==
XRFDC_MIXER_MODE_BYPASS) {
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].MixerInputDataType =
InstancePtr->RFdc_Config.DACTile_Config[Tile_Id]
.DACBlock_Digital_Config[Block_Id]
.MixerInputDataType;
} else {
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].MixerInputDataType =
XRFDC_DATA_TYPE_IQ;
}
/* Initialize MixerType */
MixerType = InstancePtr->RFdc_Config.DACTile_Config[Tile_Id]
.DACBlock_Digital_Config[Block_Id]
.MixerType;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].Mixer_Settings.MixerType =
MixerType;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].ConnectedIData = -1;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].ConnectedQData = -1;
InstancePtr->DAC_Tile[Tile_Id].MultibandConfig =
InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].MultibandConfig;
if (XRFdc_IsDACDigitalPathEnabled(InstancePtr, Tile_Id, Block_Id) != 0U) {
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].DigitalPathAvailable =
XRFDC_DIGITALPATH_ENABLE;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].DigitalPathEnabled =
XRFDC_DIGITALPATH_ENABLE;
/* Initialize ConnectedI/QData, MB Config */
XRFdc_DACMBConfigInit(InstancePtr, Tile_Id, Block_Id);
}
}
/* Initialize PLL Structure */
XRFdc_UpdatePLLStruct(InstancePtr, XRFDC_DAC_TILE, Tile_Id);
}
}
/*****************************************************************************/
/**
*
* Initialize Multiband Configuration for DAC Tiles.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3, and -1.
* @param Block_Id is DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - None.
*
* @note Static API used to initialize DAC MB Config
*
******************************************************************************/
static void XRFdc_DACMBConfigInit(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id)
{
if (InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].DACBlock_Analog_Config[Block_Id].MixMode ==
XRFDC_MIXER_MODE_C2C) {
/* Mixer Mode is C2C */
switch (InstancePtr->DAC_Tile[Tile_Id].MultibandConfig) {
case XRFDC_MB_MODE_4X:
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID0,
XRFDC_BLK_ID1);
break;
case XRFDC_MB_MODE_2X_BLK01_BLK23:
case XRFDC_MB_MODE_2X_BLK01:
case XRFDC_MB_MODE_2X_BLK23:
if ((Block_Id == XRFDC_BLK_ID0) || (Block_Id == XRFDC_BLK_ID1)) {
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID0,
XRFDC_BLK_ID1);
} else {
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID2,
XRFDC_BLK_ID3);
}
break;
default:
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, Block_Id,
Block_Id + 1U);
break;
}
} else if (InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].DACBlock_Analog_Config[Block_Id].MixMode == 0x0) {
/* Mixer Mode is C2R */
switch (InstancePtr->DAC_Tile[Tile_Id].MultibandConfig) {
case XRFDC_MB_MODE_4X:
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID0, -1);
break;
case XRFDC_MB_MODE_2X_BLK01_BLK23:
case XRFDC_MB_MODE_2X_BLK01:
case XRFDC_MB_MODE_2X_BLK23:
if ((Block_Id == XRFDC_BLK_ID0) || (Block_Id == XRFDC_BLK_ID1)) {
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID0,
-1);
} else {
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID2,
-1);
}
break;
default:
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, Block_Id, -1);
break;
}
} else {
/* Mixer Mode is BYPASS */
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, Block_Id, -1);
}
}
/*****************************************************************************/
/**
*
* Initialize Multiband Configuration for ADC Tiles.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3, and -1.
* @param Block_Id is ADC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - None.
*
* @note Static API used to initialize ADC MB Config
*
******************************************************************************/
static void XRFdc_ADCMBConfigInit(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id)
{
if (InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].ADCBlock_Analog_Config[Block_Id].MixMode ==
XRFDC_MIXER_MODE_C2C) {
/* Mixer mode is C2C */
switch (InstancePtr->ADC_Tile[Tile_Id].MultibandConfig) {
case XRFDC_MB_MODE_4X:
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID0,
XRFDC_BLK_ID1);
break;
case XRFDC_MB_MODE_2X_BLK01_BLK23:
case XRFDC_MB_MODE_2X_BLK01:
case XRFDC_MB_MODE_2X_BLK23:
if ((Block_Id == XRFDC_BLK_ID0) || (Block_Id == XRFDC_BLK_ID1)) {
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID0,
XRFDC_BLK_ID1);
} else {
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID2,
XRFDC_BLK_ID3);
}
break;
default:
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, Block_Id,
Block_Id + 1U);
break;
}
} else if (InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].ADCBlock_Analog_Config[Block_Id].MixMode == 0x0) {
/* Mixer mode is R2C */
switch (InstancePtr->ADC_Tile[Tile_Id].MultibandConfig) {
case XRFDC_MB_MODE_4X:
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID0, -1);
break;
case XRFDC_MB_MODE_2X_BLK01_BLK23:
case XRFDC_MB_MODE_2X_BLK01:
case XRFDC_MB_MODE_2X_BLK23:
if ((Block_Id == XRFDC_BLK_ID0) || (Block_Id == XRFDC_BLK_ID1)) {
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID0,
-1);
} else {
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, XRFDC_BLK_ID2,
-1);
}
break;
default:
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, Block_Id, -1);
break;
}
} else {
/* Mixer mode is BYPASS */
XRFdc_SetConnectedIQData(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, Block_Id, -1);
}
}
/*****************************************************************************/
/**
*
* This API updates PLL Structure.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC.
* @param Tile_Id Valid values are 0-3, and -1.
*
* @return
* - None.
*
* @note Static API used to initialize PLL Settings for ADC and DAC
*
******************************************************************************/
static void XRFdc_UpdatePLLStruct(XRFdc *InstancePtr, u32 Type, u32 Tile_Id)
{
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.SampleRate =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].SamplingRate;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.RefClkFreq =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].RefClkFreq;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.Enabled =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].PLLEnable;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.FeedbackDivider =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].FeedbackDiv;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.OutputDivider =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].OutputDiv;
InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.RefClkDivider =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].RefClkDiv;
} else {
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.SampleRate =
InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].SamplingRate;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.RefClkFreq =
InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].RefClkFreq;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.Enabled =
InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].PLLEnable;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.FeedbackDivider =
InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].FeedbackDiv;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.OutputDivider =
InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].OutputDiv;
InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.RefClkDivider =
InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].RefClkDiv;
}
}
/*****************************************************************************/
/**
*
* The API Restarts the requested tile. It can restart a single tile and
* alternatively can restart all the tiles. Existing register settings are not
* lost or altered in the process. It just starts the requested tile(s).
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_StartUp(XRFdc *InstancePtr, u32 Type, int Tile_Id)
{
u32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_RestartIPSM(InstancePtr, Type, Tile_Id, XRFDC_SM_STATE1, XRFDC_SM_STATE15);
return Status;
}
/*****************************************************************************/
/**
*
* The API stops the tile as requested. It can also stop all the tiles if
* asked for. It does not clear any of the existing register settings. It just
* stops the requested tile(s).
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_Shutdown(XRFdc *InstancePtr, u32 Type, int Tile_Id)
{
u32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_RestartIPSM(InstancePtr, Type, Tile_Id, XRFDC_SM_STATE1, XRFDC_SM_STATE1);
return Status;
}
/*****************************************************************************/
/**
*
* The API resets the requested tile. It can reset all the tiles as well. In
* the process, all existing register settings are cleared and are replaced
* with the settings initially configured (through the GUI).
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
******************************************************************************/
u32 XRFdc_Reset(XRFdc *InstancePtr, u32 Type, int Tile_Id)
{
u32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_RestartIPSM(InstancePtr, Type, Tile_Id, XRFDC_SM_STATE0, XRFDC_SM_STATE15);
return Status;
}
/*****************************************************************************/
/**
*
* This Static API will be used to wait for restart bit clears and also check
* for PLL Lock if clock source is internal PLL.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param End is end state of State Machine.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if timeout occurs.
*
* @note None.
*
******************************************************************************/
static u32 XRFdc_WaitForRestartClr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 BaseAddr, u32 End)
{
u32 ClkSrc = 0U;
u32 DelayCount;
u32 LockStatus = 0U;
u32 Status;
/*
* Get Tile clock source information
*/
if (XRFdc_GetClockSource(InstancePtr, Type, Tile_Id, &ClkSrc) != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((ClkSrc == XRFDC_INTERNAL_PLL_CLK) && (End == XRFDC_SM_STATE15)) {
/*
* Wait for internal PLL to lock
*/
if (XRFdc_GetPLLLockStatus(InstancePtr, Type, Tile_Id, &LockStatus) != XRFDC_SUCCESS) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
DelayCount = 0U;
while (LockStatus != XRFDC_PLL_LOCKED) {
if (DelayCount == XRFDC_PLL_LOCK_DLY_CNT) {
metal_log(METAL_LOG_ERROR, "\n %s %u timed out at state %u in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id,
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_CURRENT_STATE_OFFSET), __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
} else {
/* Wait for 1 msec */
#ifdef __BAREMETAL__
usleep(1000);
#else
metal_sleep_usec(1000);
#endif
DelayCount++;
(void)XRFdc_GetPLLLockStatus(InstancePtr, Type, Tile_Id, &LockStatus);
}
}
}
/* Wait till restart bit clear */
DelayCount = 0U;
while (XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_RESTART_OFFSET) != 0U) {
if (DelayCount == XRFDC_PLL_LOCK_DLY_CNT) {
metal_log(METAL_LOG_ERROR, "\n %s %u timed out at state %u in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id,
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_CURRENT_STATE_OFFSET), __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
} else {
/* Wait for 1 msec */
#ifdef __BAREMETAL__
usleep(1000);
#else
metal_sleep_usec(1000);
#endif
DelayCount++;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Restarts a requested the tile and ensures that starts from a defined start
* state and reaches the requested or defined end state.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
* @param Start is start state of State Machine
* @param End is end state of State Machine.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
static u32 XRFdc_RestartIPSM(XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Start, u32 End)
{
u32 Status;
u32 BaseAddr;
u16 NoOfTiles;
u16 Index;
/* An input tile if of -1 selects all tiles */
if (Tile_Id == XRFDC_SELECT_ALL_TILES) {
NoOfTiles = XRFDC_NUM_OF_TILES4;
Index = XRFDC_TILE_ID0;
} else {
NoOfTiles = Tile_Id + 1;
Index = Tile_Id;
}
for (; Index < NoOfTiles; Index++) {
BaseAddr = XRFDC_CTRL_STS_BASE(Type, Index);
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Index);
if ((Status != XRFDC_SUCCESS) && (Tile_Id != XRFDC_SELECT_ALL_TILES)) {
metal_log(METAL_LOG_ERROR, "\n Requested tile (%s %u) not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Index, __func__);
goto RETURN_PATH;
} else if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_DEBUG, "\n %s %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Index, __func__);
continue;
} else {
/* Write Start and End states */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_RESTART_STATE_OFFSET, XRFDC_PWR_STATE_MASK,
(Start << XRFDC_RSR_START_SHIFT) | End);
/* Trigger restart */
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_RESTART_OFFSET, XRFDC_RESTART_MASK);
/* Wait for restart bit clear */
Status = XRFdc_WaitForRestartClr(InstancePtr, Type, Index, BaseAddr, End);
if (Status != XRFDC_SUCCESS) {
goto RETURN_PATH;
}
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* The API returns the IP status.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param IPStatusPtr Pointer to the XRFdc_IPStatus structure through
* which the status is returned.
*
* @return
* - XRFDC_SUCCESS if successful.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_GetIPStatus(XRFdc *InstancePtr, XRFdc_IPStatus *IPStatusPtr)
{
u32 Tile_Id;
u32 Block_Id;
u32 BaseAddr;
u16 ReadReg;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(IPStatusPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
for (Tile_Id = XRFDC_TILE_ID0; Tile_Id < XRFDC_TILE_ID4; Tile_Id++) {
IPStatusPtr->ADCTileStatus[Tile_Id].BlockStatusMask = 0x0;
IPStatusPtr->DACTileStatus[Tile_Id].BlockStatusMask = 0x0;
for (Block_Id = XRFDC_BLK_ID0; Block_Id < XRFDC_BLK_ID4; Block_Id++) {
if (XRFdc_IsADCBlockEnabled(InstancePtr, Tile_Id, Block_Id) != 0U) {
IPStatusPtr->ADCTileStatus[Tile_Id].IsEnabled = 1;
IPStatusPtr->ADCTileStatus[Tile_Id].BlockStatusMask |= (1U << Block_Id);
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_STATUS_OFFSET);
IPStatusPtr->ADCTileStatus[Tile_Id].PowerUpState =
(ReadReg & XRFDC_PWR_UP_STAT_MASK) >> XRFDC_PWR_UP_STAT_SHIFT;
IPStatusPtr->ADCTileStatus[Tile_Id].PLLState =
(ReadReg & XRFDC_PLL_LOCKED_MASK) >> XRFDC_PLL_LOCKED_SHIFT;
IPStatusPtr->ADCTileStatus[Tile_Id].TileState =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_CURRENT_STATE_OFFSET);
}
if (XRFdc_IsDACBlockEnabled(InstancePtr, Tile_Id, Block_Id) != 0U) {
IPStatusPtr->DACTileStatus[Tile_Id].IsEnabled = 1;
IPStatusPtr->DACTileStatus[Tile_Id].BlockStatusMask |= (1U << Block_Id);
BaseAddr = XRFDC_DAC_TILE_CTRL_STATS_ADDR(Tile_Id);
IPStatusPtr->DACTileStatus[Tile_Id].TileState =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_CURRENT_STATE_OFFSET);
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_STATUS_OFFSET);
IPStatusPtr->DACTileStatus[Tile_Id].PowerUpState =
(ReadReg & XRFDC_PWR_UP_STAT_MASK) >> XRFDC_PWR_UP_STAT_SHIFT;
IPStatusPtr->DACTileStatus[Tile_Id].PLLState =
(ReadReg & XRFDC_PLL_LOCKED_MASK) >> XRFDC_PLL_LOCKED_SHIFT;
}
}
}
/*TODO IP state*/
return XRFDC_SUCCESS;
}
/*****************************************************************************/
/**
*
* The API returns the requested block status.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3. XRFdc_BlockStatus.
* @param BlockStatusPtr is Pointer to the XRFdc_BlockStatus structure through
* which the ADC/DAC block status is returned.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if block not enabled.
*
* @note Common API for ADC/DAC blocks.
*
******************************************************************************/
u32 XRFdc_GetBlockStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_BlockStatus *BlockStatusPtr)
{
u32 Status;
u32 Block;
u16 ReadReg;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(BlockStatusPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Block = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1) &&
(Type == XRFDC_ADC_TILE)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Block_Id);
if (Type == XRFDC_ADC_TILE) {
Status = XRFdc_GetADCBlockStatus(InstancePtr, BaseAddr, Tile_Id, Block, BlockStatusPtr);
} else {
Status = XRFdc_GetDACBlockStatus(InstancePtr, BaseAddr, Tile_Id, Block, BlockStatusPtr);
}
if (Status != XRFDC_SUCCESS) {
goto RETURN_PATH;
}
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CLK_EN_OFFSET, XRFDC_DAT_CLK_EN_MASK);
if (ReadReg == XRFDC_DAT_CLK_EN_MASK) {
BlockStatusPtr->DataPathClocksStatus = 0x1U;
} else {
BlockStatusPtr->DataPathClocksStatus = 0x0U;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* The API returns the requested block status for ADC block
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3. XRFdc_BlockStatus.
* @param BlockStatus is Pointer to the XRFdc_BlockStatus structure through
* which the ADC/DAC block status is returned.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if block not enabled.
*
* @note Static API for ADC blocks.
*
******************************************************************************/
static u32 XRFdc_GetADCBlockStatus(XRFdc *InstancePtr, u32 BaseAddr, u32 Tile_Id, u32 Block_Id,
XRFdc_BlockStatus *BlockStatusPtr)
{
u8 FIFOEnable = 0U;
u32 DecimationFactor = 0U;
u8 MixerMode;
u16 ReadReg;
u32 Status;
BlockStatusPtr->SamplingFreq = InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.SampleRate;
/* DigitalDataPathStatus */
(void)XRFdc_GetFIFOStatus(InstancePtr, XRFDC_ADC_TILE, Tile_Id, &FIFOEnable);
BlockStatusPtr->DigitalDataPathStatus = FIFOEnable;
(void)XRFdc_GetDecimationFactor(InstancePtr, Tile_Id, Block_Id, &DecimationFactor);
BlockStatusPtr->DigitalDataPathStatus |= (DecimationFactor << XRFDC_DIGI_ANALOG_SHIFT4);
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET, (XRFDC_EN_I_IQ_MASK | XRFDC_EN_Q_IQ_MASK));
switch (ReadReg) {
case XRFDC_MIXER_MODE_C2C_MASK:
MixerMode = XRFDC_MIXER_MODE_C2C;
break;
case XRFDC_MIXER_MODE_R2C_MASK:
MixerMode = XRFDC_MIXER_MODE_R2C;
break;
case XRFDC_MIXER_MODE_OFF_MASK:
MixerMode = XRFDC_MIXER_MODE_OFF;
break;
default:
metal_log(METAL_LOG_ERROR, "\n Invalid MixerMode (%u) for ADC %u block %u in %s\r\n", ReadReg, Tile_Id,
Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
BlockStatusPtr->DigitalDataPathStatus |= (MixerMode << XRFDC_DIGI_ANALOG_SHIFT8);
/*
* Checking ADC block enable for ADC AnalogPath.
* This can be changed later,
*/
BlockStatusPtr->AnalogDataPathStatus = XRFdc_IsADCBlockEnabled(InstancePtr, Tile_Id, Block_Id);
BlockStatusPtr->IsFIFOFlagsEnabled =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_IMR_OFFSET, XRFDC_FAB_IMR_USRDAT_MASK);
BlockStatusPtr->IsFIFOFlagsAsserted =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_ISR_OFFSET, XRFDC_FAB_ISR_USRDAT_MASK);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* The API returns the requested block status for DAC block
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3. XRFdc_BlockStatus.
* @param BlockStatus is Pointer to the XRFdc_BlockStatus structure through
* which the DAC block status is returned.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if block not enabled.
*
* @note Static API for DAC blocks.
*
******************************************************************************/
static u32 XRFdc_GetDACBlockStatus(XRFdc *InstancePtr, u32 BaseAddr, u32 Tile_Id, u32 Block_Id,
XRFdc_BlockStatus *BlockStatusPtr)
{
u32 InterpolationFactor = 0U;
u32 DecoderMode = 0U;
u8 MixerMode;
u16 ReadReg;
u32 Status;
u8 FIFOEnable = 0U;
BlockStatusPtr->SamplingFreq = InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.SampleRate;
/* DigitalDataPathStatus */
(void)XRFdc_GetFIFOStatus(InstancePtr, XRFDC_DAC_TILE, Tile_Id, &FIFOEnable);
BlockStatusPtr->DigitalDataPathStatus = FIFOEnable;
(void)XRFdc_GetInterpolationFactor(InstancePtr, Tile_Id, Block_Id, &InterpolationFactor);
BlockStatusPtr->DigitalDataPathStatus |= (InterpolationFactor << XRFDC_DIGI_ANALOG_SHIFT4);
/* Adder Enable */
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_MB_CFG_OFFSET, XRFDC_EN_MB_MASK);
ReadReg = ReadReg >> XRFDC_EN_MB_SHIFT;
BlockStatusPtr->DigitalDataPathStatus |= (ReadReg << XRFDC_DIGI_ANALOG_SHIFT8);
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET, (XRFDC_EN_I_IQ_MASK | XRFDC_EN_Q_IQ_MASK));
switch (ReadReg) {
case XRFDC_MIXER_MODE_C2C_MASK:
MixerMode = XRFDC_MIXER_MODE_C2C;
break;
case XRFDC_MIXER_MODE_C2R_MASK:
MixerMode = XRFDC_MIXER_MODE_C2R;
break;
case XRFDC_MIXER_MODE_OFF_MASK:
MixerMode = XRFDC_MIXER_MODE_OFF;
break;
default:
metal_log(METAL_LOG_ERROR, "\n Invalid MixerMode (%u) for DAC %u block %u in %s\r\n", ReadReg, Tile_Id,
Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
BlockStatusPtr->DigitalDataPathStatus |= (MixerMode << XRFDC_DIGI_ANALOG_SHIFT12);
/* AnalogDataPathStatus */
BlockStatusPtr->AnalogDataPathStatus = XRFdc_RDReg(
InstancePtr, BaseAddr, XRFDC_DAC_INVSINC_OFFSET,
(InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) ? XRFDC_EN_INVSINC_MASK : XRFDC_MODE_INVSINC_MASK);
(void)XRFdc_GetDecoderMode(InstancePtr, Tile_Id, Block_Id, &DecoderMode);
BlockStatusPtr->AnalogDataPathStatus |= (DecoderMode << XRFDC_DIGI_ANALOG_SHIFT4);
/* FIFO Flags status */
BlockStatusPtr->IsFIFOFlagsEnabled =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_FABRIC_IMR_OFFSET, XRFDC_FAB_IMR_USRDAT_MASK);
BlockStatusPtr->IsFIFOFlagsAsserted =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_FABRIC_ISR_OFFSET, XRFDC_FAB_ISR_USRDAT_MASK);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
* This API is used to update various QMC settings, eg gain, phase, offset etc.
* QMC settings passed are used to update the corresponding
* block level registers. Driver structure is updated with the new values.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param QMCSettingsPtr is Pointer to the XRFdc_QMC_Settings structure
* in which the QMC settings are passed.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_SetQMCSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr)
{
u32 Status;
XRFdc_QMC_Settings *QMCConfigPtr;
u32 BaseAddr;
s32 PhaseCorrectionFactor;
u32 GainCorrectionFactor;
u32 Index;
u32 NoOfBlocks;
u32 Offset;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(QMCSettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
if (InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ) {
Index = Block_Id;
NoOfBlocks = XRFDC_NUM_OF_BLKS3;
if (Block_Id == XRFDC_BLK_ID1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks;) {
if (Type == XRFDC_ADC_TILE) {
/* ADC */
QMCConfigPtr = &InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Analog_Datapath[Index].QMC_Settings;
} else {
QMCConfigPtr = &InstancePtr->DAC_Tile[Tile_Id].DACBlock_Analog_Datapath[Index].QMC_Settings;
}
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Index);
if ((QMCSettingsPtr->EnableGain != 0U) && (QMCSettingsPtr->EnableGain != 1U)) {
metal_log(METAL_LOG_ERROR, "\n Invalid QMC gain option (%u) for %s %u block %u in %s\r\n",
QMCSettingsPtr->EnableGain, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id,
Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((QMCSettingsPtr->EnablePhase != 0U) && (QMCSettingsPtr->EnablePhase != 1U)) {
metal_log(METAL_LOG_ERROR, "\n Invalid QMC phase option (%u) for %s %u block %u in %s\r\n",
QMCSettingsPtr->EnableGain, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id,
Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((QMCSettingsPtr->PhaseCorrectionFactor <= XRFDC_MIN_PHASE_CORR_FACTOR) ||
(QMCSettingsPtr->PhaseCorrectionFactor >= XRFDC_MAX_PHASE_CORR_FACTOR)) {
metal_log(METAL_LOG_ERROR,
"\n Invalid QMC Phase Correction factor (%d) for %s %u block %u in %s\r\n",
QMCSettingsPtr->PhaseCorrectionFactor, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC",
Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((QMCSettingsPtr->GainCorrectionFactor < XRFDC_MIN_GAIN_CORR_FACTOR) ||
(QMCSettingsPtr->GainCorrectionFactor >= XRFDC_MAX_GAIN_CORR_FACTOR)) {
metal_log(METAL_LOG_ERROR,
"\n Invalid QMC Gain Correction factor (%d) for %s %u block %u in %s\r\n",
QMCSettingsPtr->GainCorrectionFactor, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC",
Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((QMCSettingsPtr->EventSource > XRFDC_EVNT_SRC_PL) ||
((QMCSettingsPtr->EventSource == XRFDC_EVNT_SRC_MARKER) && (Type == XRFDC_ADC_TILE))) {
metal_log(METAL_LOG_ERROR,
"\n Invalid event source selection (%u) for %s %u block %u in %s\r\n",
QMCSettingsPtr->EventSource, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id,
Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE) &&
((QMCSettingsPtr->EventSource == XRFDC_EVNT_SRC_SLICE) ||
(QMCSettingsPtr->EventSource == XRFDC_EVNT_SRC_IMMEDIATE))) {
metal_log(
METAL_LOG_ERROR,
"\n Invalid Event Source, event source is not supported in 4GSPS ADC (%u) for ADC %u block %u in %s\r\n",
QMCSettingsPtr->EventSource, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_QMC_CFG_OFFSET, XRFDC_QMC_CFG_EN_GAIN_MASK,
QMCSettingsPtr->EnableGain);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_QMC_CFG_OFFSET, XRFDC_QMC_CFG_EN_PHASE_MASK,
(QMCSettingsPtr->EnablePhase << XRFDC_QMC_CFG_PHASE_SHIFT));
/* Phase Correction factor is applicable to ADC/DAC IQ mode only */
if (((Type == XRFDC_ADC_TILE) &&
(InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ)) ||
((Type == XRFDC_DAC_TILE) &&
(InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ))) {
PhaseCorrectionFactor = ((QMCSettingsPtr->PhaseCorrectionFactor / XRFDC_MAX_PHASE_CORR_FACTOR) *
XRFDC_QMC_PHASE_MULT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_QMC_PHASE_OFFSET, XRFDC_QMC_PHASE_CRCTN_MASK,
PhaseCorrectionFactor);
}
/* Gain Correction factor */
GainCorrectionFactor =
((QMCSettingsPtr->GainCorrectionFactor * XRFDC_QMC_GAIN_MULT) / XRFDC_MAX_GAIN_CORR_FACTOR);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_QMC_GAIN_OFFSET, XRFDC_QMC_GAIN_CRCTN_MASK,
GainCorrectionFactor);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_QMC_OFF_OFFSET, XRFDC_QMC_OFFST_CRCTN_MASK,
QMCSettingsPtr->OffsetCorrectionFactor);
/* Event Source */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_QMC_UPDT_OFFSET, XRFDC_QMC_UPDT_MODE_MASK,
QMCSettingsPtr->EventSource);
if (QMCSettingsPtr->EventSource == XRFDC_EVNT_SRC_IMMEDIATE) {
if (Type == XRFDC_ADC_TILE) {
Offset = XRFDC_ADC_UPDATE_DYN_OFFSET;
} else {
Offset = XRFDC_DAC_UPDATE_DYN_OFFSET;
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, Offset, XRFDC_UPDT_EVNT_MASK, XRFDC_UPDT_EVNT_QMC_MASK);
}
/* Update the instance with new values */
QMCConfigPtr->EventSource = QMCSettingsPtr->EventSource;
QMCConfigPtr->PhaseCorrectionFactor = QMCSettingsPtr->PhaseCorrectionFactor;
QMCConfigPtr->GainCorrectionFactor = QMCSettingsPtr->GainCorrectionFactor;
QMCConfigPtr->OffsetCorrectionFactor = QMCSettingsPtr->OffsetCorrectionFactor;
QMCConfigPtr->EnablePhase = QMCSettingsPtr->EnablePhase;
QMCConfigPtr->EnableGain = QMCSettingsPtr->EnableGain;
if ((Type == XRFDC_ADC_TILE) &&
(InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ) &&
(XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
Index += XRFDC_BLK_ID2;
} else {
Index += XRFDC_BLK_ID1;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* QMC settings are returned back to the caller through this API.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param QMCSettingsPtr Pointer to the XRFdc_QMC_Settings structure
* in which the QMC settings are passed.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_GetQMCSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr)
{
u32 Status;
u32 BaseAddr;
s32 PhaseCorrectionFactor;
u32 GainCorrectionFactor;
s32 OffsetCorrectionFactor;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(QMCSettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1) &&
(Type == XRFDC_ADC_TILE) &&
(InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].MixerInputDataType !=
XRFDC_DATA_TYPE_IQ)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Block_Id);
QMCSettingsPtr->EnableGain =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_QMC_CFG_OFFSET, XRFDC_QMC_CFG_EN_GAIN_MASK);
QMCSettingsPtr->EnablePhase =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_QMC_CFG_OFFSET, XRFDC_QMC_CFG_EN_PHASE_MASK) >>
XRFDC_QMC_CFG_PHASE_SHIFT;
/* Phase Correction factor */
if (((Type == XRFDC_ADC_TILE) &&
(InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ)) ||
((Type == XRFDC_DAC_TILE) &&
(InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ))) {
PhaseCorrectionFactor =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_QMC_PHASE_OFFSET, XRFDC_QMC_PHASE_CRCTN_MASK);
PhaseCorrectionFactor = (PhaseCorrectionFactor >> 11) == 0 ? PhaseCorrectionFactor :
((-1 ^ 0xFFF) | PhaseCorrectionFactor);
QMCSettingsPtr->PhaseCorrectionFactor =
((PhaseCorrectionFactor * XRFDC_MAX_PHASE_CORR_FACTOR) / XRFDC_QMC_PHASE_MULT);
} else {
QMCSettingsPtr->PhaseCorrectionFactor = 0U;
}
/* Gain Correction factor */
GainCorrectionFactor = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_QMC_GAIN_OFFSET, XRFDC_QMC_GAIN_CRCTN_MASK);
QMCSettingsPtr->GainCorrectionFactor =
((GainCorrectionFactor * XRFDC_MAX_GAIN_CORR_FACTOR) / XRFDC_QMC_GAIN_MULT);
OffsetCorrectionFactor = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_QMC_OFF_OFFSET, XRFDC_QMC_OFFST_CRCTN_MASK);
QMCSettingsPtr->OffsetCorrectionFactor =
(OffsetCorrectionFactor >> 11) == 0 ? OffsetCorrectionFactor : ((-1 ^ 0xFFF) | OffsetCorrectionFactor);
/* Event Source */
QMCSettingsPtr->EventSource =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_QMC_UPDT_OFFSET, XRFDC_QMC_UPDT_MODE_MASK);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Coarse delay settings passed are used to update the corresponding
* block level registers. Driver structure is updated with the new values.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param CoarseDelaySettingsPtr is Pointer to the XRFdc_CoarseDelay_Settings
* structure in which the CoarseDelay settings are passed.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_SetCoarseDelaySettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr)
{
u32 Status;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
u16 Mask;
u16 MaxDelay;
XRFdc_CoarseDelay_Settings *CoarseDelayConfigPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CoarseDelaySettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Mask = (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) ? XRFDC_CRSE_DLY_CFG_MASK : XRFDC_CRSE_DLY_CFG_MASK_EXT;
MaxDelay = (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) ? XRFDC_CRSE_DLY_MAX : XRFDC_CRSE_DLY_MAX_EXT;
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
if (Type == XRFDC_ADC_TILE) {
CoarseDelayConfigPtr =
&InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Analog_Datapath[Index].CoarseDelay_Settings;
} else {
CoarseDelayConfigPtr =
&InstancePtr->DAC_Tile[Tile_Id].DACBlock_Analog_Datapath[Index].CoarseDelay_Settings;
}
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Index);
if (CoarseDelaySettingsPtr->CoarseDelay > MaxDelay) {
metal_log(METAL_LOG_ERROR,
"\n Requested coarse delay not valid (%u) for %s %u block %u in %s\r\n",
CoarseDelaySettingsPtr->CoarseDelay, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC",
Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((CoarseDelaySettingsPtr->EventSource > XRFDC_EVNT_SRC_PL) ||
((CoarseDelaySettingsPtr->EventSource == XRFDC_EVNT_SRC_MARKER) && (Type == XRFDC_ADC_TILE))) {
metal_log(METAL_LOG_ERROR,
"\n Invalid event source selection (%u) for %s %u block %u in %s\r\n",
CoarseDelaySettingsPtr->EventSource, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC",
Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE) &&
((CoarseDelaySettingsPtr->EventSource == XRFDC_EVNT_SRC_SLICE) ||
(CoarseDelaySettingsPtr->EventSource == XRFDC_EVNT_SRC_IMMEDIATE))) {
Status = XRFDC_FAILURE;
metal_log(
METAL_LOG_ERROR,
"\n Invalid Event Source, event source is not supported in 4GSPS ADC (%u) for ADC %u block %u in %s\r\n",
CoarseDelaySettingsPtr->EventSource, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (Type == XRFDC_ADC_TILE) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_CRSE_DLY_CFG_OFFSET, Mask,
CoarseDelaySettingsPtr->CoarseDelay);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_CRSE_DLY_UPDT_OFFSET, XRFDC_QMC_UPDT_MODE_MASK,
CoarseDelaySettingsPtr->EventSource);
if (CoarseDelaySettingsPtr->EventSource == XRFDC_EVNT_SRC_IMMEDIATE) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_UPDATE_DYN_OFFSET,
XRFDC_UPDT_EVNT_MASK, XRFDC_ADC_UPDT_CRSE_DLY_MASK);
}
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_CRSE_DLY_CFG_OFFSET, Mask,
CoarseDelaySettingsPtr->CoarseDelay);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_CRSE_DLY_UPDT_OFFSET, XRFDC_QMC_UPDT_MODE_MASK,
CoarseDelaySettingsPtr->EventSource);
if (CoarseDelaySettingsPtr->EventSource == XRFDC_EVNT_SRC_IMMEDIATE) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_UPDATE_DYN_OFFSET,
XRFDC_UPDT_EVNT_MASK, XRFDC_DAC_UPDT_CRSE_DLY_MASK);
}
}
/* Update the instance with new values */
CoarseDelayConfigPtr->CoarseDelay = CoarseDelaySettingsPtr->CoarseDelay;
CoarseDelayConfigPtr->EventSource = CoarseDelaySettingsPtr->EventSource;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Coarse delay settings are returned back to the caller.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param CoarseDelaySettingsPtr Pointer to the XRFdc_CoarseDelay_Settings
* structure in which the Coarse Delay settings are passed.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_GetCoarseDelaySettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CoarseDelaySettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1) &&
(Type == XRFDC_ADC_TILE)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Block_Id);
if (Type == XRFDC_ADC_TILE) {
CoarseDelaySettingsPtr->CoarseDelay =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_CRSE_DLY_CFG_OFFSET);
CoarseDelaySettingsPtr->EventSource =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_CRSE_DLY_UPDT_OFFSET, XRFDC_QMC_UPDT_MODE_MASK);
} else {
CoarseDelaySettingsPtr->CoarseDelay =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DAC_CRSE_DLY_CFG_OFFSET);
CoarseDelaySettingsPtr->EventSource =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_CRSE_DLY_UPDT_OFFSET, XRFDC_QMC_UPDT_MODE_MASK);
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function will trigger the update event for an event.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param Event is for which dynamic update event will trigger.
* XRFDC_EVENT_* defines the different events.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Common API for ADC/DAC blocks
*
******************************************************************************/
u32 XRFdc_UpdateEvent(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 Event)
{
u32 Status;
u32 BaseAddr;
u32 EventSource;
u32 NoOfBlocks;
u32 Index;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
if ((Event == XRFDC_EVENT_QMC) &&
(InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ)) {
Index = Block_Id;
NoOfBlocks = XRFDC_NUM_OF_BLKS3;
if (Block_Id == XRFDC_BLK_ID1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
}
} else {
NoOfBlocks = Block_Id + 1U;
}
if ((Event != XRFDC_EVENT_MIXER) && (Event != XRFDC_EVENT_QMC) && (Event != XRFDC_EVENT_CRSE_DLY)) {
metal_log(METAL_LOG_ERROR, "\n Invalid Event value (%u) for %s %u block %u in %s\r\n", Event,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
for (; Index < NoOfBlocks;) {
/* Identify the Event Source */
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Index);
if (Event == XRFDC_EVENT_MIXER) {
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, Type, Tile_Id, Block_Id);
EventSource =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_NCO_UPDT_OFFSET, XRFDC_NCO_UPDT_MODE_MASK);
} else if (Event == XRFDC_EVENT_CRSE_DLY) {
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
EventSource = XRFdc_RDReg(InstancePtr, BaseAddr,
(Type == XRFDC_ADC_TILE) ? XRFDC_ADC_CRSE_DLY_UPDT_OFFSET :
XRFDC_DAC_CRSE_DLY_UPDT_OFFSET,
XRFDC_QMC_UPDT_MODE_MASK);
} else {
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
EventSource =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_QMC_UPDT_OFFSET, XRFDC_QMC_UPDT_MODE_MASK);
}
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((EventSource == XRFDC_EVNT_SRC_SYSREF) || (EventSource == XRFDC_EVNT_SRC_PL) ||
(EventSource == XRFDC_EVNT_SRC_MARKER)) {
Status = XRFDC_FAILURE;
metal_log(
METAL_LOG_ERROR,
"\n Invalid Event Source (%u), this should be issued external to the driver for %s %u block %u in %s\r\n",
Event, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (Type == XRFDC_ADC_TILE) {
if (EventSource == XRFDC_EVNT_SRC_SLICE) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_UPDATE_DYN_OFFSET, 0x1);
} else {
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_HSCOM_ADDR;
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_UPDT_DYN_OFFSET, 0x1);
}
} else {
if (EventSource == XRFDC_EVNT_SRC_SLICE) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_DAC_UPDATE_DYN_OFFSET, 0x1);
} else {
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_HSCOM_ADDR;
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_UPDT_DYN_OFFSET, 0x1);
}
}
if ((Event == XRFDC_EVENT_QMC) &&
(InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ) &&
(XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
Index += XRFDC_BLK_ID2;
} else {
Index += XRFDC_BLK_ID1;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is to set the decimation factor and also update the FIFO write
* words w.r.t to decimation factor.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param DecimationFactor to be set for DAC block.
* XRFDC_INTERP_DECIM_* defines the valid values.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only ADC blocks
*
******************************************************************************/
u32 XRFdc_SetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecimationFactor)
{
u32 Status;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
u16 FabricRate;
u8 DataType;
u32 Factor;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u digital path %u not enabled in %s\r\n", Tile_Id, Block_Id,
__func__);
goto RETURN_PATH;
}
if ((DecimationFactor != XRFDC_INTERP_DECIM_OFF) && (DecimationFactor != XRFDC_INTERP_DECIM_1X) &&
(DecimationFactor != XRFDC_INTERP_DECIM_2X) && (DecimationFactor != XRFDC_INTERP_DECIM_4X) &&
(DecimationFactor != XRFDC_INTERP_DECIM_8X) &&
((InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) ||
((DecimationFactor != XRFDC_INTERP_DECIM_3X) && (DecimationFactor != XRFDC_INTERP_DECIM_5X) &&
(DecimationFactor != XRFDC_INTERP_DECIM_6X) && (DecimationFactor != XRFDC_INTERP_DECIM_10X) &&
(DecimationFactor != XRFDC_INTERP_DECIM_12X) && (DecimationFactor != XRFDC_INTERP_DECIM_16X) &&
(DecimationFactor != XRFDC_INTERP_DECIM_20X) && (DecimationFactor != XRFDC_INTERP_DECIM_24X) &&
(DecimationFactor != XRFDC_INTERP_DECIM_40X)))) {
metal_log(METAL_LOG_ERROR, "\n Invalid Decimation factor value (%u) for ADC %u block %u in %s\r\n",
DecimationFactor, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
DataType = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_DECI_CONFIG_OFFSET, XRFDC_DEC_CFG_MASK);
/* Decimation factor */
Factor = DecimationFactor;
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if (DecimationFactor == XRFDC_INTERP_DECIM_4X) {
Factor = 0x3;
}
if (DecimationFactor == XRFDC_INTERP_DECIM_8X) {
Factor = 0x4;
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_DECI_MODE_OFFSET, XRFDC_DEC_MOD_MASK, Factor);
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_DECI_MODE_OFFSET, XRFDC_DEC_MOD_MASK_EXT,
Factor);
}
/* Fabric rate */
FabricRate =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_ADC_FAB_RATE_WR_MASK);
if ((DataType == XRFDC_DECIM_2G_IQ_DATA_TYPE) || (DataType == XRFDC_DECIM_4G_DATA_TYPE) ||
(XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
switch (DecimationFactor) {
case XRFDC_INTERP_DECIM_1X:
FabricRate = XRFDC_FAB_RATE_8;
break;
case XRFDC_INTERP_DECIM_2X:
case XRFDC_INTERP_DECIM_3X:
FabricRate = XRFDC_FAB_RATE_4;
break;
case XRFDC_INTERP_DECIM_4X:
case XRFDC_INTERP_DECIM_5X:
case XRFDC_INTERP_DECIM_6X:
FabricRate = XRFDC_FAB_RATE_2;
break;
case XRFDC_INTERP_DECIM_8X:
case XRFDC_INTERP_DECIM_10X:
case XRFDC_INTERP_DECIM_12X:
case XRFDC_INTERP_DECIM_16X:
case XRFDC_INTERP_DECIM_20X:
case XRFDC_INTERP_DECIM_24X:
case XRFDC_INTERP_DECIM_40X:
FabricRate = XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) ? XRFDC_FAB_RATE_1 :
XRFDC_FAB_RATE_2;
break;
default:
metal_log(METAL_LOG_DEBUG, "\n Decimation block is OFF in ADC %u block %u in %s\r\n",
Tile_Id, Block_Id, __func__);
break;
}
} else {
switch (DecimationFactor) {
case XRFDC_INTERP_DECIM_1X:
FabricRate = XRFDC_FAB_RATE_4;
break;
case XRFDC_INTERP_DECIM_2X:
case XRFDC_INTERP_DECIM_3X:
FabricRate = XRFDC_FAB_RATE_2;
break;
case XRFDC_INTERP_DECIM_4X:
case XRFDC_INTERP_DECIM_8X:
case XRFDC_INTERP_DECIM_5X:
case XRFDC_INTERP_DECIM_6X:
case XRFDC_INTERP_DECIM_10X:
case XRFDC_INTERP_DECIM_12X:
case XRFDC_INTERP_DECIM_16X:
case XRFDC_INTERP_DECIM_20X:
case XRFDC_INTERP_DECIM_24X:
case XRFDC_INTERP_DECIM_40X:
FabricRate = XRFDC_FAB_RATE_1;
break;
default:
metal_log(METAL_LOG_DEBUG, "\n Decimation block is OFF in %s\r\n", __func__);
break;
}
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_ADC_FAB_RATE_WR_MASK,
FabricRate);
}
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
switch (DecimationFactor) {
case XRFDC_INTERP_DECIM_1X:
case XRFDC_INTERP_DECIM_2X:
case XRFDC_INTERP_DECIM_4X:
case XRFDC_INTERP_DECIM_8X:
XRFdc_ClrSetReg(InstancePtr, (XRFDC_DRP_BASE(XRFDC_ADC_TILE, Tile_Id) + XRFDC_HSCOM_ADDR),
XRFDC_HSCOM_FIFO_START_OFFSET, XRFDC_ADC_FIFO_DELAY_MASK, 0);
break;
case XRFDC_INTERP_DECIM_3X:
case XRFDC_INTERP_DECIM_6X:
case XRFDC_INTERP_DECIM_12X:
case XRFDC_INTERP_DECIM_5X:
case XRFDC_INTERP_DECIM_10X:
case XRFDC_INTERP_DECIM_16X:
case XRFDC_INTERP_DECIM_20X:
case XRFDC_INTERP_DECIM_24X:
case XRFDC_INTERP_DECIM_40X:
XRFdc_ClrSetReg(InstancePtr, (XRFDC_DRP_BASE(XRFDC_ADC_TILE, Tile_Id) + XRFDC_HSCOM_ADDR),
XRFDC_HSCOM_FIFO_START_OFFSET, XRFDC_ADC_FIFO_DELAY_MASK,
XRFDC_ADC_CG_WAIT_CYCLES << XRFDC_ADC_FIFO_DELAY_SHIFT);
break;
default:
metal_log(METAL_LOG_DEBUG, "\n Decimation block is OFF for DAC %u block %u in %s\r\n", Tile_Id,
Block_Id, __func__);
break;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is to set the divider for clock fabric out.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param FabClkDiv to be set for a tile.
* XRFDC_FAB_CLK_* defines the valid divider values.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note ADC and DAC Tiles
*
******************************************************************************/
u32 XRFdc_SetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 FabClkDiv)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Requested tile (%s %u) not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
}
if ((FabClkDiv != XRFDC_FAB_CLK_DIV1) && (FabClkDiv != XRFDC_FAB_CLK_DIV2) &&
(FabClkDiv != XRFDC_FAB_CLK_DIV4) && (FabClkDiv != XRFDC_FAB_CLK_DIV8) &&
(FabClkDiv != XRFDC_FAB_CLK_DIV16)) {
metal_log(METAL_LOG_ERROR, "\n Invalid Fabric clock out divider value (%u) for %s %u in %s\r\n",
FabClkDiv, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
BaseAddr = XRFDC_DRP_BASE(Type, Tile_Id) + XRFDC_HSCOM_ADDR;
if ((Type == XRFDC_ADC_TILE) && (FabClkDiv == XRFDC_FAB_CLK_DIV1)) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid clock divider (%u) for %s %u in %s\r\n", FabClkDiv,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_HSCOM_CLK_DIV_OFFSET, XRFDC_FAB_CLK_DIV_MASK, FabClkDiv);
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is to get the divider for clock fabric out.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param FabClkDivPtr is a pointer to get fabric clock for a tile.
* XRFDC_FAB_CLK_* defines the valid divider values.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note API is applicable for both ADC and DAC Tiles
*
******************************************************************************/
u32 XRFdc_GetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 *FabClkDivPtr)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(FabClkDivPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Requested tile (%s %u) not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_DRP_BASE(Type, Tile_Id) + XRFDC_HSCOM_ADDR;
*FabClkDivPtr = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_HSCOM_CLK_DIV_OFFSET, XRFDC_FAB_CLK_DIV_MASK);
if ((*FabClkDivPtr < XRFDC_FAB_CLK_DIV1) || (*FabClkDivPtr > XRFDC_FAB_CLK_DIV16)) {
*FabClkDivPtr = XRFDC_FAB_CLK_DIV16;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is to set the interpolation factor and also update the FIFO read
* words w.r.t to interpolation factor.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param InterpolationFactor to be set for DAC block.
* XRFDC_INTERP_DECIM_* defines the valid values.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only DAC blocks
*
******************************************************************************/
u32 XRFdc_SetInterpolationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 InterpolationFactor)
{
u32 Status;
u32 BaseAddr;
u16 FabricRate;
u8 DataType;
u32 Factor;
u32 DatapathMode;
u32 ReadPtrDelay;
u32 CGNumerator;
u32 CGDenominator;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u digital path %u not enabled in %s\r\n", Tile_Id, Block_Id,
__func__);
goto RETURN_PATH;
}
if ((InterpolationFactor != XRFDC_INTERP_DECIM_OFF) && (InterpolationFactor != XRFDC_INTERP_DECIM_1X) &&
(InterpolationFactor != XRFDC_INTERP_DECIM_2X) && (InterpolationFactor != XRFDC_INTERP_DECIM_4X) &&
(InterpolationFactor != XRFDC_INTERP_DECIM_8X) &&
((InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) ||
((InterpolationFactor != XRFDC_INTERP_DECIM_3X) && (InterpolationFactor != XRFDC_INTERP_DECIM_5X) &&
(InterpolationFactor != XRFDC_INTERP_DECIM_6X) && (InterpolationFactor != XRFDC_INTERP_DECIM_10X) &&
(InterpolationFactor != XRFDC_INTERP_DECIM_12X) && (InterpolationFactor != XRFDC_INTERP_DECIM_16X) &&
(InterpolationFactor != XRFDC_INTERP_DECIM_20X) && (InterpolationFactor != XRFDC_INTERP_DECIM_24X) &&
(InterpolationFactor != XRFDC_INTERP_DECIM_40X)))) {
metal_log(METAL_LOG_ERROR,
"\n Invalid Interpolation factor divider value (%u) for DAC %u block %u in %s\r\n",
InterpolationFactor, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
DatapathMode = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_DATAPATH_OFFSET, XRFDC_DATAPATH_MODE_MASK);
if (DatapathMode == XRFDC_DAC_INT_MODE_FULL_BW_BYPASS) {
Status = XRFDC_FAILURE;
metal_log(
METAL_LOG_ERROR,
"\n Can't set interpolation mode as DUC is in bypass mode for DAC %u block %u in %s\r\n",
Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
}
DataType = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DAC_ITERP_DATA_OFFSET);
if ((DataType == XRFDC_ADC_MIXER_MODE_IQ) && (InterpolationFactor == XRFDC_INTERP_DECIM_1X)) {
Status = XRFDC_FAILURE;
metal_log(
METAL_LOG_ERROR,
"\n Invalid interpolation factor (x1 interpolation factor in IQ mode) for DAC %u block %u in %s\r\n",
Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
/* Interpolation factor */
Factor = InterpolationFactor;
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if (InterpolationFactor == XRFDC_INTERP_DECIM_4X) {
Factor = 0x3;
}
if (InterpolationFactor == XRFDC_INTERP_DECIM_8X) {
Factor = 0x4;
}
}
if (DataType == XRFDC_ADC_MIXER_MODE_IQ) {
Factor |= Factor << ((InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) ? XRFDC_INTERP_MODE_Q_SHIFT :
XRFDC_INTERP_MODE_Q_SHIFT_EXT);
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_INTERP_CTRL_OFFSET,
(InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) ? XRFDC_INTERP_MODE_MASK :
XRFDC_INTERP_MODE_MASK_EXT,
Factor);
/* Fabric rate */
FabricRate = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_DAC_FAB_RATE_RD_MASK);
FabricRate = FabricRate >> XRFDC_FAB_RATE_RD_SHIFT;
if (DataType == XRFDC_ADC_MIXER_MODE_IQ) {
switch (InterpolationFactor) {
case XRFDC_INTERP_DECIM_2X:
case XRFDC_INTERP_DECIM_3X:
FabricRate = XRFDC_FAB_RATE_8;
break;
case XRFDC_INTERP_DECIM_4X:
case XRFDC_INTERP_DECIM_5X:
case XRFDC_INTERP_DECIM_6X:
FabricRate = XRFDC_FAB_RATE_4;
break;
case XRFDC_INTERP_DECIM_8X:
case XRFDC_INTERP_DECIM_10X:
case XRFDC_INTERP_DECIM_12X:
case XRFDC_INTERP_DECIM_16X:
case XRFDC_INTERP_DECIM_20X:
case XRFDC_INTERP_DECIM_24X:
case XRFDC_INTERP_DECIM_40X:
FabricRate = XRFDC_FAB_RATE_2;
break;
default:
metal_log(METAL_LOG_DEBUG, "\n Interpolation block is OFF for DAC %u block %u in %s\r\n",
Tile_Id, Block_Id, __func__);
break;
}
} else {
switch (InterpolationFactor) {
case XRFDC_INTERP_DECIM_1X:
FabricRate = XRFDC_FAB_RATE_8;
break;
case XRFDC_INTERP_DECIM_2X:
case XRFDC_INTERP_DECIM_3X:
FabricRate = XRFDC_FAB_RATE_4;
break;
case XRFDC_INTERP_DECIM_4X:
case XRFDC_INTERP_DECIM_5X:
case XRFDC_INTERP_DECIM_6X:
FabricRate = XRFDC_FAB_RATE_2;
break;
case XRFDC_INTERP_DECIM_8X:
case XRFDC_INTERP_DECIM_10X:
case XRFDC_INTERP_DECIM_12X:
case XRFDC_INTERP_DECIM_16X:
case XRFDC_INTERP_DECIM_20X:
case XRFDC_INTERP_DECIM_24X:
case XRFDC_INTERP_DECIM_40X:
FabricRate = XRFDC_FAB_RATE_1;
break;
default:
metal_log(METAL_LOG_DEBUG, "\n Interpolation block is OFF for DAC %u block %u in %s\r\n",
Tile_Id, Block_Id, __func__);
break;
}
}
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
switch (InterpolationFactor) {
case XRFDC_INTERP_DECIM_1X:
case XRFDC_INTERP_DECIM_2X:
case XRFDC_INTERP_DECIM_4X:
case XRFDC_INTERP_DECIM_8X:
CGNumerator = XRFDC_CG_CYCLES_TOTAL_X1_X2_X4_X8;
CGDenominator = XRFDC_CG_CYCLES_KEPT_X1_X2_X4_X8;
break;
case XRFDC_INTERP_DECIM_3X:
case XRFDC_INTERP_DECIM_6X:
case XRFDC_INTERP_DECIM_12X:
CGNumerator = XRFDC_CG_CYCLES_TOTAL_X3_X6_X12;
CGDenominator = XRFDC_CG_CYCLES_KEPT_X3_X6_X12;
break;
case XRFDC_INTERP_DECIM_5X:
case XRFDC_INTERP_DECIM_10X:
CGNumerator = XRFDC_CG_CYCLES_TOTAL_X5_X10;
CGDenominator = XRFDC_CG_CYCLES_KEPT_X5_X10;
break;
case XRFDC_INTERP_DECIM_16X:
CGNumerator = XRFDC_CG_CYCLES_TOTAL_X16;
CGDenominator = XRFDC_CG_CYCLES_KEPT_X16;
break;
case XRFDC_INTERP_DECIM_20X:
CGNumerator = XRFDC_CG_CYCLES_TOTAL_X20;
CGDenominator = XRFDC_CG_CYCLES_KEPT_X20;
break;
case XRFDC_INTERP_DECIM_24X:
CGNumerator = XRFDC_CG_CYCLES_TOTAL_X24;
CGDenominator = XRFDC_CG_CYCLES_KEPT_X24;
break;
case XRFDC_INTERP_DECIM_40X:
CGNumerator = XRFDC_CG_CYCLES_TOTAL_X40;
CGDenominator = XRFDC_CG_CYCLES_KEPT_X40;
break;
default:
metal_log(METAL_LOG_DEBUG, "\n Interpolation block is OFF for DAC %u block %u in %s\r\n",
Tile_Id, Block_Id, __func__);
CGNumerator = XRFDC_CG_CYCLES_TOTAL_X1_X2_X4_X8;
CGDenominator = XRFDC_CG_CYCLES_KEPT_X1_X2_X4_X8;
break;
}
ReadPtrDelay = ((XRFDC_CG_WAIT_CYCLES * CGNumerator) / CGDenominator) +
(((XRFDC_CG_WAIT_CYCLES * CGNumerator) % CGDenominator) ? 1 : 0);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_FIFO_START_OFFSET, XRFDC_DAC_FIFO_DELAY_MASK,
ReadPtrDelay);
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_DAC_FAB_RATE_RD_MASK,
(FabricRate << XRFDC_FAB_RATE_RD_SHIFT));
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Interpolation factor are returned back to the caller.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param InterpolationFactorPtr Pointer to return the interpolation factor
* for DAC blocks.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for DAC blocks
*
******************************************************************************/
u32 XRFdc_GetInterpolationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *InterpolationFactorPtr)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InterpolationFactorPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u digital path %u not enabled in %s\r\n", Tile_Id, Block_Id,
__func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
*InterpolationFactorPtr =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_INTERP_CTRL_OFFSET, XRFDC_INTERP_MODE_I_MASK);
if (*InterpolationFactorPtr == 0x3U) {
*InterpolationFactorPtr = XRFDC_INTERP_DECIM_4X;
} else if (*InterpolationFactorPtr == 0x4U) {
*InterpolationFactorPtr = XRFDC_INTERP_DECIM_8X;
}
} else {
*InterpolationFactorPtr =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_INTERP_CTRL_OFFSET, XRFDC_INTERP_MODE_I_MASK_EXT);
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Decimation factor are returned back to the caller.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param DecimationFactorPtr Pointer to return the Decimation factor
* for DAC blocks.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_GetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecimationFactorPtr)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(DecimationFactorPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u digital path %u not enabled in %s\r\n", Tile_Id, Block_Id,
__func__);
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
*DecimationFactorPtr =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_DECI_MODE_OFFSET, XRFDC_DEC_MOD_MASK);
if (*DecimationFactorPtr == 0x3U) {
*DecimationFactorPtr = XRFDC_INTERP_DECIM_4X;
} else if (*DecimationFactorPtr == 0x4U) {
*DecimationFactorPtr = XRFDC_INTERP_DECIM_8X;
}
} else {
*DecimationFactorPtr =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_DECI_MODE_OFFSET, XRFDC_DEC_MOD_MASK_EXT);
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Fabric data rate for the requested DAC block is set by writing to the
* corresponding register. The function writes the number of valid write words
* for the requested DAC block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param FabricWrVldWords is write fabric rate to be set for DAC block.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for DAC blocks
*
******************************************************************************/
u32 XRFdc_SetFabWrVldWords(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricWrVldWords)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u digital path %u not enabled in %s\r\n", Tile_Id, Block_Id,
__func__);
goto RETURN_PATH;
}
if (FabricWrVldWords > XRFDC_DAC_MAX_WR_FAB_RATE) {
metal_log(METAL_LOG_ERROR,
"\n Requested write valid words is Invalid (%u) for DAC %u block %u in %s\r\n",
FabricWrVldWords, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_DAC_FAB_RATE_WR_MASK,
FabricWrVldWords);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Fabric data rate for the requested ADC block is set by writing to the
* corresponding register. The function writes the number of valid read words
* for the requested ADC block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC block number inside the tile. Valid values
* are 0-3.
* @param FabricRdVldWords is Read fabric rate to be set for ADC block.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_SetFabRdVldWords(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricRdVldWords)
{
u32 Status;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u digital path %u not enabled in %s\r\n", Tile_Id, Block_Id,
__func__);
goto RETURN_PATH;
}
if (FabricRdVldWords > XRFDC_ADC_MAX_RD_FAB_RATE(InstancePtr->RFdc_Config.IPType)) {
metal_log(METAL_LOG_ERROR,
"\n Requested read valid words is Invalid (%u) for ADC %u block %u in %s\r\n",
FabricRdVldWords, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_ADC_FAB_RATE_RD_MASK,
(FabricRdVldWords << XRFDC_FAB_RATE_RD_SHIFT));
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API returns the the number of fabric write valid words requested
* for the block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param FabricWrVldWordsPtr Pointer to return the fabric data rate for
* DAC block
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note ADC/DAC blocks
*
******************************************************************************/
u32 XRFdc_GetFabWrVldWords(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricWrVldWordsPtr)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(FabricWrVldWordsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u digital path %u not enabled in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1) &&
(Type == XRFDC_ADC_TILE)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Block_Id);
*FabricWrVldWordsPtr = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET);
if (Type == XRFDC_ADC_TILE) {
*FabricWrVldWordsPtr &= XRFDC_ADC_FAB_RATE_WR_MASK;
} else {
*FabricWrVldWordsPtr &= XRFDC_DAC_FAB_RATE_WR_MASK;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API returns the the number of fabric read valid words requested
* for the block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param FabricRdVldWordsPtr Pointer to return the fabric data rate for
* ADC/DAC block
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note ADC/DAC blocks
*
******************************************************************************/
u32 XRFdc_GetFabRdVldWords(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricRdVldWordsPtr)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(FabricRdVldWordsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u digital path %u not enabled in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1) &&
(Type == XRFDC_ADC_TILE)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Block_Id);
*FabricRdVldWordsPtr = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET);
*FabricRdVldWordsPtr = (*FabricRdVldWordsPtr) >> XRFDC_FAB_RATE_RD_SHIFT;
if (Type == XRFDC_ADC_TILE) {
*FabricRdVldWordsPtr &= XRFDC_ADC_FAB_RATE_WR_MASK;
} else {
*FabricRdVldWordsPtr &= XRFDC_DAC_FAB_RATE_WR_MASK;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is to clear the Sticky bit in threshold config registers.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param ThresholdToUpdate Select which Threshold (Threshold0 or
* Threshold1 or both) to update.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only ADC blocks
*
******************************************************************************/
u32 XRFdc_ThresholdStickyClear(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 ThresholdToUpdate)
{
u32 Status;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((ThresholdToUpdate != XRFDC_UPDATE_THRESHOLD_0) && (ThresholdToUpdate != XRFDC_UPDATE_THRESHOLD_1) &&
(ThresholdToUpdate != XRFDC_UPDATE_THRESHOLD_BOTH)) {
metal_log(METAL_LOG_ERROR, "\n Invalid ThresholdToUpdate value (%u) for ADC %u block %u in %s\r\n",
ThresholdToUpdate, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
if (InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ) {
Index = Block_Id;
NoOfBlocks = XRFDC_NUM_OF_BLKS3;
if (Block_Id == XRFDC_BLK_ID1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks;) {
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
/* Update for Threshold0 */
if ((ThresholdToUpdate == XRFDC_UPDATE_THRESHOLD_0) ||
(ThresholdToUpdate == XRFDC_UPDATE_THRESHOLD_BOTH)) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_CFG_OFFSET, XRFDC_TRSHD0_STIKY_CLR_MASK,
XRFDC_TRSHD0_STIKY_CLR_MASK);
}
/* Update for Threshold1 */
if ((ThresholdToUpdate == XRFDC_UPDATE_THRESHOLD_1) ||
(ThresholdToUpdate == XRFDC_UPDATE_THRESHOLD_BOTH)) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_CFG_OFFSET, XRFDC_TRSHD1_STIKY_CLR_MASK,
XRFDC_TRSHD1_STIKY_CLR_MASK);
}
if ((InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ) &&
(XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
Index += XRFDC_BLK_ID2;
} else {
Index += XRFDC_BLK_ID1;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API sets the threshold clear mode. The clear mode can be through
* explicit DRP access (manual) or auto clear (QMC gain update event).
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADCC block number inside the tile. Valid values
* are 0-3.
* @param ThresholdToUpdate Select which Threshold (Threshold0 or
* Threshold1 or both) to update.
* @param ClrMode can be DRP access (manual) or auto clear (QMC gain
* update event).
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only ADC blocks
*
******************************************************************************/
u32 XRFdc_SetThresholdClrMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 ThresholdToUpdate, u32 ClrMode)
{
u32 Status;
u16 ReadReg;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((ThresholdToUpdate != XRFDC_UPDATE_THRESHOLD_0) && (ThresholdToUpdate != XRFDC_UPDATE_THRESHOLD_1) &&
(ThresholdToUpdate != XRFDC_UPDATE_THRESHOLD_BOTH)) {
metal_log(METAL_LOG_ERROR, "\n Invalid ThresholdToUpdate value (%u) for ADC %u block %u in %s\r\n",
ThresholdToUpdate, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((ClrMode != XRFDC_THRESHOLD_CLRMD_MANUAL_CLR) && (ClrMode != XRFDC_THRESHOLD_CLRMD_AUTO_CLR)) {
metal_log(METAL_LOG_ERROR, "\n Invalid Clear mode value (%u) for ADC %u block %u in %s\r\n", ClrMode,
Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
if (InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ) {
Index = Block_Id;
NoOfBlocks = XRFDC_NUM_OF_BLKS3;
if (Block_Id == XRFDC_BLK_ID1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks;) {
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
/* Update for Threshold0 */
if ((ThresholdToUpdate == XRFDC_UPDATE_THRESHOLD_0) ||
(ThresholdToUpdate == XRFDC_UPDATE_THRESHOLD_BOTH)) {
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_CFG_OFFSET);
if (ClrMode == XRFDC_THRESHOLD_CLRMD_MANUAL_CLR) {
ReadReg &= ~XRFDC_TRSHD0_CLR_MOD_MASK;
} else {
ReadReg |= XRFDC_TRSHD0_CLR_MOD_MASK;
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_CFG_OFFSET, ReadReg);
}
/* Update for Threshold1 */
if ((ThresholdToUpdate == XRFDC_UPDATE_THRESHOLD_1) ||
(ThresholdToUpdate == XRFDC_UPDATE_THRESHOLD_BOTH)) {
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_CFG_OFFSET);
if (ClrMode == XRFDC_THRESHOLD_CLRMD_MANUAL_CLR) {
ReadReg &= ~XRFDC_TRSHD1_CLR_MOD_MASK;
} else {
ReadReg |= XRFDC_TRSHD1_CLR_MOD_MASK;
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_CFG_OFFSET, ReadReg);
}
if ((InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ) &&
(XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
Index += XRFDC_BLK_ID2;
} else {
Index += XRFDC_BLK_ID1;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Threshold settings are updated into the relevant registers. Driver structure
* is updated with the new values. There can be two threshold settings:
* threshold0 and threshold1. Both of them are independent of each other.
* The function returns the requested threshold (which can be threshold0,
* threshold1, or both.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param ThresholdSettingsPtr Pointer through which the register settings for
* thresholds are passed to the API.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only ADC blocks
*
******************************************************************************/
u32 XRFdc_SetThresholdSettings(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
XRFdc_Threshold_Settings *ThresholdSettingsPtr)
{
u32 Status;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
XRFdc_Threshold_Settings *ThresholdConfigPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ThresholdSettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
if (InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ) {
Index = Block_Id;
NoOfBlocks = XRFDC_NUM_OF_BLKS3;
if (Block_Id == XRFDC_BLK_ID1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks;) {
ThresholdConfigPtr = &InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Analog_Datapath[Index].Threshold_Settings;
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
if ((ThresholdSettingsPtr->UpdateThreshold != XRFDC_UPDATE_THRESHOLD_0) &&
(ThresholdSettingsPtr->UpdateThreshold != XRFDC_UPDATE_THRESHOLD_1) &&
(ThresholdSettingsPtr->UpdateThreshold != XRFDC_UPDATE_THRESHOLD_BOTH)) {
metal_log(METAL_LOG_ERROR,
"\n Invalid UpdateThreshold value (%u) for ADC %u block %u in %s\r\n",
ThresholdSettingsPtr->UpdateThreshold, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (((ThresholdSettingsPtr->UpdateThreshold == XRFDC_UPDATE_THRESHOLD_0) ||
(ThresholdSettingsPtr->UpdateThreshold == XRFDC_UPDATE_THRESHOLD_BOTH)) &&
(ThresholdSettingsPtr->ThresholdMode[0] > XRFDC_TRSHD_HYSTERISIS)) {
metal_log(
METAL_LOG_ERROR,
"\n Requested threshold mode for threshold0 is invalid (%u) for ADC %u block %u in %s\r\n",
ThresholdSettingsPtr->ThresholdMode[0], Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (((ThresholdSettingsPtr->UpdateThreshold == XRFDC_UPDATE_THRESHOLD_1) ||
(ThresholdSettingsPtr->UpdateThreshold == XRFDC_UPDATE_THRESHOLD_BOTH)) &&
(ThresholdSettingsPtr->ThresholdMode[1] > XRFDC_TRSHD_HYSTERISIS)) {
metal_log(
METAL_LOG_ERROR,
"\n Requested threshold mode for threshold1 is invalid (%u) for ADC %u block %u in %s\r\n",
ThresholdSettingsPtr->ThresholdMode[0], Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
/* Update for Threshold0 */
if ((ThresholdSettingsPtr->UpdateThreshold == XRFDC_UPDATE_THRESHOLD_0) ||
(ThresholdSettingsPtr->UpdateThreshold == XRFDC_UPDATE_THRESHOLD_BOTH)) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_AVG_LO_OFFSET,
(u16)ThresholdSettingsPtr->ThresholdAvgVal[0]);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_AVG_UP_OFFSET,
(u16)(ThresholdSettingsPtr->ThresholdAvgVal[0] >> XRFDC_TRSHD0_AVG_UPP_SHIFT));
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_UNDER_OFFSET, XRFDC_TRSHD0_UNDER_MASK,
ThresholdSettingsPtr->ThresholdUnderVal[0]);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_OVER_OFFSET, XRFDC_TRSHD0_OVER_MASK,
ThresholdSettingsPtr->ThresholdOverVal[0]);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_CFG_OFFSET, XRFDC_TRSHD0_EN_MOD_MASK,
ThresholdSettingsPtr->ThresholdMode[0]);
ThresholdConfigPtr->ThresholdMode[0] = ThresholdSettingsPtr->ThresholdMode[0];
ThresholdConfigPtr->ThresholdAvgVal[0] = ThresholdSettingsPtr->ThresholdAvgVal[0];
ThresholdConfigPtr->ThresholdUnderVal[0] = ThresholdSettingsPtr->ThresholdUnderVal[0];
ThresholdConfigPtr->ThresholdOverVal[0] = ThresholdSettingsPtr->ThresholdOverVal[0];
}
/* Update for Threshold1 */
if ((ThresholdSettingsPtr->UpdateThreshold == XRFDC_UPDATE_THRESHOLD_1) ||
(ThresholdSettingsPtr->UpdateThreshold == XRFDC_UPDATE_THRESHOLD_BOTH)) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_AVG_LO_OFFSET,
(u16)ThresholdSettingsPtr->ThresholdAvgVal[1]);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_AVG_UP_OFFSET,
(u16)(ThresholdSettingsPtr->ThresholdAvgVal[1] >> XRFDC_TRSHD1_AVG_UPP_SHIFT));
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_UNDER_OFFSET, XRFDC_TRSHD1_UNDER_MASK,
ThresholdSettingsPtr->ThresholdUnderVal[1]);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_OVER_OFFSET, XRFDC_TRSHD1_OVER_MASK,
ThresholdSettingsPtr->ThresholdOverVal[1]);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_CFG_OFFSET, XRFDC_TRSHD1_EN_MOD_MASK,
ThresholdSettingsPtr->ThresholdMode[1]);
ThresholdConfigPtr->ThresholdMode[1] = ThresholdSettingsPtr->ThresholdMode[1];
ThresholdConfigPtr->ThresholdAvgVal[1] = ThresholdSettingsPtr->ThresholdAvgVal[1];
ThresholdConfigPtr->ThresholdUnderVal[1] = ThresholdSettingsPtr->ThresholdUnderVal[1];
ThresholdConfigPtr->ThresholdOverVal[1] = ThresholdSettingsPtr->ThresholdOverVal[1];
}
if ((InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ) &&
(XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
Index += XRFDC_BLK_ID2;
} else {
Index += XRFDC_BLK_ID1;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Threshold settings are read from the corresponding registers and are passed
* back to the caller. There can be two threshold settings:
* threshold0 and threshold1. Both of them are independent of each other.
* The function returns the requested threshold (which can be threshold0,
* threshold1, or both.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param ThresholdSettingsPtr Pointer through which the register settings
* for thresholds are passed back..
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_GetThresholdSettings(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
XRFdc_Threshold_Settings *ThresholdSettingsPtr)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ThresholdSettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1) &&
(InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].MixerInputDataType !=
XRFDC_DATA_TYPE_IQ)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Block_Id);
/* Threshold mode */
ThresholdSettingsPtr->UpdateThreshold = XRFDC_UPDATE_THRESHOLD_BOTH;
ThresholdSettingsPtr->ThresholdMode[0] =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_CFG_OFFSET, XRFDC_TRSHD0_EN_MOD_MASK);
ThresholdSettingsPtr->ThresholdMode[1] =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_CFG_OFFSET, XRFDC_TRSHD1_EN_MOD_MASK);
/* Threshold Average Value */
ThresholdSettingsPtr->ThresholdAvgVal[0] =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_AVG_LO_OFFSET);
ThresholdSettingsPtr->ThresholdAvgVal[0] |=
(XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_AVG_UP_OFFSET) << XRFDC_TRSHD0_AVG_UPP_SHIFT);
ThresholdSettingsPtr->ThresholdAvgVal[1] =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_AVG_LO_OFFSET);
ThresholdSettingsPtr->ThresholdAvgVal[1] |=
(XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_AVG_UP_OFFSET) << XRFDC_TRSHD1_AVG_UPP_SHIFT);
/* Threshold Under Value */
ThresholdSettingsPtr->ThresholdUnderVal[0] =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_UNDER_OFFSET, XRFDC_TRSHD0_UNDER_MASK);
ThresholdSettingsPtr->ThresholdUnderVal[1] =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_UNDER_OFFSET, XRFDC_TRSHD1_UNDER_MASK);
/* Threshold Over Value */
ThresholdSettingsPtr->ThresholdOverVal[0] =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD0_OVER_OFFSET, XRFDC_TRSHD0_OVER_MASK);
ThresholdSettingsPtr->ThresholdOverVal[1] =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_TRSHD1_OVER_OFFSET, XRFDC_TRSHD1_OVER_MASK);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Decoder mode is updated into the relevant registers. Driver structure is
* updated with the new values.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is DAC block number inside the tile. Valid values
* are 0-3.
* @param DecoderMode Valid values are 1 (Maximum SNR, for non-
* randomized decoder), 2 (Maximum Linearity, for randomized decoder)
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only DAC blocks
*
******************************************************************************/
u32 XRFdc_SetDecoderMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecoderMode)
{
u32 Status;
u32 *DecoderModeConfigPtr;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
DecoderModeConfigPtr = &InstancePtr->DAC_Tile[Tile_Id].DACBlock_Analog_Datapath[Block_Id].DecoderMode;
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
if ((DecoderMode != XRFDC_DECODER_MAX_SNR_MODE) && (DecoderMode != XRFDC_DECODER_MAX_LINEARITY_MODE)) {
metal_log(METAL_LOG_ERROR, "\n Invalid decoder mode (%u) for DAC %u block %u in %s\r\n", DecoderMode,
Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_DECODER_CTRL_OFFSET, XRFDC_DEC_CTRL_MODE_MASK, DecoderMode);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_DECODER_CLK_OFFSET, XRFDC_DEC_CTRL_MODE_MASK, DecoderMode);
*DecoderModeConfigPtr = DecoderMode;
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Decoder mode is read and returned back.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is DAC block number inside the tile. Valid values
* are 0-3.
* @param DecoderModePtr Valid values are 1 (Maximum SNR, for non-randomized
* decoder), 2 (Maximum Linearity, for randomized decoder)
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for DAC blocks
*
******************************************************************************/
u32 XRFdc_GetDecoderMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecoderModePtr)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(DecoderModePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
*DecoderModePtr = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_DECODER_CTRL_OFFSET, XRFDC_DEC_CTRL_MODE_MASK);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Resets the NCO phase of the current block phase accumulator.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_ResetNCOPhase(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
{
u32 Status;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u digital path %u not enabled in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Index);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_NCO_RST_OFFSET, XRFDC_NCO_PHASE_RST_MASK,
XRFDC_NCO_PHASE_RST_MASK);
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Enable and Disable the ADC/DAC FIFO.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Enable valid values are 1 (FIFO enable) and 0 (FIFO Disable)
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Common API for ADC/DAC blocks
*
******************************************************************************/
u32 XRFdc_SetupFIFO(XRFdc *InstancePtr, u32 Type, int Tile_Id, u8 Enable)
{
u32 Status;
u32 BaseAddr;
u16 NoOfTiles;
u16 Index;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if ((Enable != 0U) && (Enable != 1U)) {
metal_log(METAL_LOG_ERROR, "\n Invalid enable value (%u) for %s %d in %s\r\n", Enable,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
/* An input tile if of -1 selects all tiles */
if (Tile_Id == XRFDC_SELECT_ALL_TILES) {
NoOfTiles = XRFDC_NUM_OF_TILES4;
Index = XRFDC_TILE_ID0;
} else {
NoOfTiles = Tile_Id + 1;
Index = Tile_Id;
}
for (; Index < NoOfTiles; Index++) {
BaseAddr = XRFDC_CTRL_STS_BASE(Type, Index);
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Index);
if ((Status != XRFDC_SUCCESS) && (Tile_Id != XRFDC_SELECT_ALL_TILES)) {
metal_log(METAL_LOG_ERROR, "\n %s %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Index, __func__);
goto RETURN_PATH;
} else if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Index, __func__);
continue;
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_FIFO_ENABLE, XRFDC_FIFO_EN_MASK, (!Enable));
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Current status of ADC/DAC FIFO.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param EnablePtr valid values are 1 (FIFO enable) and 0 (FIFO Disable)
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Common API for ADC/DAC blocks
*
******************************************************************************/
u32 XRFdc_GetFIFOStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 *EnablePtr)
{
u32 Status;
u32 BaseAddr;
u32 ReadReg;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(EnablePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Requested tile (%s %u) not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_CTRL_STS_BASE(Type, Tile_Id);
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_FIFO_ENABLE, XRFDC_FIFO_EN_MASK);
*EnablePtr = (!ReadReg);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Get Output Current for DAC block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param OutputCurrPtr pointer to return the output current.
*
* @return
* - Return Output Current for DAC block
*
******************************************************************************/
u32 XRFdc_GetOutputCurr(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *OutputCurrPtr)
{
u32 Status;
u32 BaseAddr;
u16 ReadReg_Cfg2;
u16 ReadReg_Cfg3;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(OutputCurrPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
ReadReg_Cfg3 = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_MC_CFG3_OFFSET, XRFDC_DAC_MC_CFG3_CSGAIN_MASK);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
ReadReg_Cfg2 = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_DAC_MC_CFG2_OFFSET,
XRFDC_DAC_MC_CFG2_OPCSCAS_MASK);
if ((ReadReg_Cfg2 == XRFDC_DAC_MC_CFG2_OPCSCAS_32MA) &&
(ReadReg_Cfg3 == XRFDC_DAC_MC_CFG3_CSGAIN_32MA)) {
*OutputCurrPtr = XRFDC_OUTPUT_CURRENT_32MA;
} else if ((ReadReg_Cfg2 == XRFDC_DAC_MC_CFG2_OPCSCAS_20MA) &&
(ReadReg_Cfg3 == XRFDC_DAC_MC_CFG3_CSGAIN_20MA)) {
*OutputCurrPtr = XRFDC_OUTPUT_CURRENT_20MA;
} else if ((ReadReg_Cfg2 == 0x0) && (ReadReg_Cfg3 == 0x0)) {
*OutputCurrPtr = 0x0;
} else {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid output current value (%u) for DAC %u block %u in %s\r\n",
*OutputCurrPtr, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
} else {
*OutputCurrPtr = ((ReadReg_Cfg3 >> XRFDC_DAC_MC_CFG3_CSGAIN_SHIFT) * XRFDC_STEP_I_UA) + XRFDC_MIN_I_UA;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Set the Nyquist zone.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param NyquistZone valid values are 1 (Odd),2 (Even).
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Common API for ADC/DAC blocks
*
******************************************************************************/
u32 XRFdc_SetNyquistZone(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 NyquistZone)
{
u32 Status;
u16 ReadReg;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
u8 CalibrationMode = 0U;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((NyquistZone != XRFDC_ODD_NYQUIST_ZONE) && (NyquistZone != XRFDC_EVEN_NYQUIST_ZONE)) {
metal_log(METAL_LOG_ERROR, "\n Invalid NyquistZone value (%u) for %s %u block %u in %s\r\n",
NyquistZone, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Index);
if (Type == XRFDC_ADC_TILE) {
/* Identify calibration mode */
Status = XRFdc_GetCalibrationMode(InstancePtr, Tile_Id, Block_Id, &CalibrationMode);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if (CalibrationMode == XRFDC_CALIB_MODE1) {
if (NyquistZone == XRFDC_ODD_NYQUIST_ZONE) {
NyquistZone = XRFDC_EVEN_NYQUIST_ZONE;
} else {
NyquistZone = XRFDC_ODD_NYQUIST_ZONE;
}
}
}
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_TI_TISK_CRL0_OFFSET);
if ((NyquistZone % 2U) == 0U) {
ReadReg |= XRFDC_TI_TISK_ZONE_MASK;
} else {
ReadReg &= ~XRFDC_TI_TISK_ZONE_MASK;
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_TI_TISK_CRL0_OFFSET, ReadReg);
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Analog_Datapath[Index].NyquistZone = NyquistZone;
} else {
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DAC_MC_CFG0_OFFSET);
if ((NyquistZone % 2U) == 0U) {
ReadReg |= XRFDC_MC_CFG0_MIX_MODE_MASK;
} else {
ReadReg &= ~XRFDC_MC_CFG0_MIX_MODE_MASK;
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_DAC_MC_CFG0_OFFSET, ReadReg);
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Analog_Datapath[Index].NyquistZone = NyquistZone;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Get the Nyquist zone.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param NyquistZonePtr Pointer to return the Nyquist zone.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Common API for ADC/DAC blocks
*
******************************************************************************/
u32 XRFdc_GetNyquistZone(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *NyquistZonePtr)
{
u32 Status;
u16 ReadReg;
u32 BaseAddr;
u32 Block;
u8 CalibrationMode = 0U;
u8 MultibandConfig;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(NyquistZonePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (Type == XRFDC_ADC_TILE) {
MultibandConfig = InstancePtr->ADC_Tile[Tile_Id].MultibandConfig;
} else {
MultibandConfig = InstancePtr->DAC_Tile[Tile_Id].MultibandConfig;
}
if (MultibandConfig != XRFDC_MB_MODE_SB) {
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, Type, Tile_Id, Block_Id);
} else {
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
}
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Block = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1) &&
(Type == XRFDC_ADC_TILE)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Block_Id);
if (Type == XRFDC_ADC_TILE) {
/* Identify calibration mode */
Status = XRFdc_GetCalibrationMode(InstancePtr, Tile_Id, Block, &CalibrationMode);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_TISK_CRL0_OFFSET, XRFDC_TI_TISK_ZONE_MASK);
*NyquistZonePtr = (ReadReg >> XRFDC_TISK_ZONE_SHIFT);
} else {
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_MC_CFG0_OFFSET, XRFDC_MC_CFG0_MIX_MODE_MASK);
*NyquistZonePtr = (ReadReg >> XRFDC_MC_CFG0_MIX_MODE_SHIFT);
}
if (*NyquistZonePtr == 0U) {
*NyquistZonePtr = XRFDC_ODD_NYQUIST_ZONE;
} else {
*NyquistZonePtr = XRFDC_EVEN_NYQUIST_ZONE;
}
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if ((Type == XRFDC_ADC_TILE) && (CalibrationMode == XRFDC_CALIB_MODE1)) {
if (*NyquistZonePtr == XRFDC_EVEN_NYQUIST_ZONE) {
*NyquistZonePtr = XRFDC_ODD_NYQUIST_ZONE;
} else {
*NyquistZonePtr = XRFDC_EVEN_NYQUIST_ZONE;
}
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is to set the DAC Datapath mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param Mode valid values are 0-3.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if tile not enabled / out of range.
*
* @note Only for DAC blocks
*
******************************************************************************/
u32 XRFdc_SetDataPathMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode)
{
u32 Status = XRFDC_SUCCESS;
u32 BaseAddr;
u32 GetClkDiv;
u32 SetClkDiv;
u32 GetInterpolationFactor;
XRFdc_Mixer_Settings MixerSettings;
u32 FabricRate;
u32 DatapathReg;
u32 CurrentMode;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested functionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
SetClkDiv = XRFDC_CLK_DIV_DP_OTHER_MODES;
FabricRate = XRFDC_FAB_RATE_8;
switch (Mode) {
case XRFDC_DATAPATH_MODE_DUC_0_FSDIVTWO:
DatapathReg = XRFDC_DAC_INT_MODE_FULL_BW;
SetClkDiv = XRFDC_CLK_DIV_DP_FIRST_MODE;
break;
case XRFDC_DATAPATH_MODE_DUC_0_FSDIVFOUR:
DatapathReg = XRFDC_DAC_INT_MODE_HALF_BW_IMR;
break;
case XRFDC_DATAPATH_MODE_FSDIVFOUR_FSDIVTWO:
DatapathReg = XRFDC_DAC_INT_MODE_HALF_BW_IMR;
DatapathReg |= (XRFDC_DAC_IMR_MODE_HIGHPASS << XRFDC_DATAPATH_IMR_SHIFT);
break;
case XRFDC_DATAPATH_MODE_NODUC_0_FSDIVTWO:
DatapathReg = XRFDC_DAC_INT_MODE_FULL_BW_BYPASS;
FabricRate = XRFDC_FAB_RATE_16;
break;
default:
metal_log(METAL_LOG_ERROR, "\n Invalid Mode value in (%u) for DAC %u block %u in %s\r\n", Mode, Tile_Id,
Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
/*
Interpolation factor, mixer settings and fabric rate needs to be set if going to Mode 4.
Fabric rate needs to be set if going from mode 4 to another Mode.
*/
if ((Mode == XRFDC_DATAPATH_MODE_NODUC_0_FSDIVTWO)) {
Status = XRFdc_GetMixerSettings(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, &MixerSettings);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Failed to get mixer settings for DAC %u block %u in %s\r\n",
Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (MixerSettings.MixerMode != XRFDC_MIXER_MODE_R2R) {
MixerSettings.CoarseMixFreq = XRFDC_COARSE_MIX_BYPASS;
MixerSettings.MixerMode = XRFDC_MIXER_MODE_R2R;
MixerSettings.MixerType = XRFDC_MIXER_TYPE_COARSE;
metal_log(
METAL_LOG_WARNING,
"\n Setting mixer mode to remain compatible with datapath mode for DAC %u block %u (R2R) in %s\r\n",
Tile_Id, Block_Id, __func__);
Status = XRFdc_SetMixerSettings(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id, &MixerSettings);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR,
"\n Failed to set mixer settings for DAC %u block %u in %s\r\n", Tile_Id,
Block_Id, __func__);
goto RETURN_PATH;
}
}
GetInterpolationFactor =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_INTERP_CTRL_OFFSET, XRFDC_INTERP_MODE_I_MASK_EXT);
if (GetInterpolationFactor != XRFDC_INTERP_DECIM_1X) {
metal_log(
METAL_LOG_WARNING,
"\n Setting Interpolation settings mode to remain compatible with datapath mode for DAC %u block %u (x1 Real) in %s\r\n",
Tile_Id, Block_Id, __func__);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_INTERP_CTRL_OFFSET, XRFDC_INTERP_MODE_MASK_EXT,
XRFDC_INTERP_DECIM_1X);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_ITERP_DATA_OFFSET, XRFDC_DAC_INTERP_DATA_MASK,
XRFDC_DISABLED);
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_FABRIC_RATE_OFFSET, XRFDC_DAC_FAB_RATE_RD_MASK,
(FabricRate << XRFDC_FAB_RATE_RD_SHIFT));
} else { /*Modes 1-3*/
CurrentMode = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_DATAPATH_OFFSET, XRFDC_DATAPATH_MODE_MASK);
if (CurrentMode == XRFDC_DAC_INT_MODE_FULL_BW_BYPASS) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_FABRIC_RATE_OFFSET, XRFDC_DAC_FAB_RATE_RD_MASK,
(FabricRate << XRFDC_FAB_RATE_RD_SHIFT));
}
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_DATAPATH_OFFSET,
(XRFDC_DATAPATH_MODE_MASK | XRFDC_DATAPATH_IMR_MASK), DatapathReg);
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_HSCOM_ADDR;
GetClkDiv = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_HSCOM_CLK_DIV_OFFSET, XRFDC_FAB_CLK_DIV_CAL_MASK);
if (GetClkDiv != SetClkDiv) {
metal_log(METAL_LOG_WARNING,
"\n Setting mode that may not be compatible with other channels on this tile %s\r\n",
__func__);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_HSCOM_CLK_DIV_OFFSET, XRFDC_FAB_CLK_DIV_CAL_MASK,
SetClkDiv);
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is to get the DAC Datapath mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param ModePtr pointer used to return value.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for DAC blocks
*
******************************************************************************/
u32 XRFdc_GetDataPathMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr)
{
u32 Status = XRFDC_SUCCESS;
u32 BaseAddr;
u32 DatapathReg;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Xil_AssertNonvoid(ModePtr != NULL);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested functionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
DatapathReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_DATAPATH_OFFSET,
(XRFDC_DATAPATH_MODE_MASK | XRFDC_DATAPATH_IMR_MASK));
switch (DatapathReg & XRFDC_DATAPATH_MODE_MASK) {
case XRFDC_DAC_INT_MODE_FULL_BW_BYPASS:
*ModePtr = XRFDC_DATAPATH_MODE_NODUC_0_FSDIVTWO;
break;
case XRFDC_DAC_INT_MODE_HALF_BW_IMR:
if ((DatapathReg >> XRFDC_DATAPATH_IMR_SHIFT) == XRFDC_DAC_IMR_MODE_HIGHPASS) {
*ModePtr = XRFDC_DATAPATH_MODE_FSDIVFOUR_FSDIVTWO;
} else {
*ModePtr = XRFDC_DATAPATH_MODE_DUC_0_FSDIVFOUR;
}
break;
case XRFDC_DAC_INT_MODE_FULL_BW:
default:
*ModePtr = XRFDC_DATAPATH_MODE_DUC_0_FSDIVTWO;
break;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is to set the DAC Image Reject Filter Pass mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param Mode valid values are 0 (for low pass) 1 (for high pass).
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if tile not enabled / bad parameter passed
*
* @note Only for DAC blocks
*
******************************************************************************/
u32 XRFdc_SetIMRPassMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode)
{
u32 Status = XRFDC_SUCCESS;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
return Status;
}
if (Mode > XRFDC_DAC_IMR_MODE_MAX) {
metal_log(METAL_LOG_ERROR, "\n Invalid Mode value in (%u) for DAC %u block %u in %s\r\n", Mode, Tile_Id,
Block_Id, __func__);
Status = XRFDC_FAILURE;
return Status;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_DATAPATH_OFFSET, XRFDC_DATAPATH_IMR_MASK, Mode << 2);
return Status;
}
/*****************************************************************************/
/**
*
* This API is to get the DAC Image Reject Filter Pass mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param ModePtr pointer used to return value.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for DAC blocks
*
******************************************************************************/
u32 XRFdc_GetIMRPassMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr)
{
u32 Status = XRFDC_SUCCESS;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Xil_AssertNonvoid(ModePtr != NULL);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
return Status;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
*ModePtr = (XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_DATAPATH_OFFSET, XRFDC_DATAPATH_IMR_MASK)) >> 2;
return Status;
}
/*****************************************************************************/
/**
*
* This API is to set the Calibration mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param CalibrationMode valid values are 1 and 2.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_SetCalibrationMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u8 CalibrationMode)
{
u32 Status;
u16 ReadReg;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
XRFdc_Mixer_Settings Mixer_Settings = { 0 };
u32 NyquistZone = 0U;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if (InstancePtr->ADC_Tile[Tile_Id].MultibandConfig != XRFDC_MB_MODE_SB) {
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
} else {
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
}
} else {
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
}
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
return XRFDC_FAILURE;
}
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
if ((CalibrationMode != XRFDC_CALIB_MODE1) && (CalibrationMode != XRFDC_CALIB_MODE2)) {
metal_log(METAL_LOG_ERROR, "\n Invalid Calibration mode value (%u) for ADC %u block %u in %s\r\n",
CalibrationMode, Tile_Id, Block_Id, __func__);
return XRFDC_FAILURE;
}
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
/* Get Mixer Configurations */
Status = XRFdc_GetMixerSettings(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, &Mixer_Settings);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
/* Get Nyquist Zone */
Status = XRFdc_GetNyquistZone(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, &NyquistZone);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL0_OFFSET);
ReadReg &= ~XRFDC_TI_DCB_MODE_MASK;
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if (CalibrationMode == XRFDC_CALIB_MODE1) {
if (((Index % 2U) != 0U) && (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
ReadReg |= XRFDC_TI_DCB_MODE1_4GSPS;
} else if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) {
ReadReg |= XRFDC_TI_DCB_MODE1_2GSPS;
}
}
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL0_OFFSET, ReadReg);
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Analog_Datapath[Index].CalibrationMode =
CalibrationMode;
}
/* Set Nyquist Zone */
Status = XRFdc_SetNyquistZone(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, NyquistZone);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
/* Set Mixer Configurations */
Status = XRFdc_SetMixerSettings(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id, &Mixer_Settings);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
} else {
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_TISK_CRL5_OFFSET, XRFDC_CAL_MODES_MASK,
((CalibrationMode == XRFDC_CALIB_MODE1) ? XRFDC_CALIB_MODE_NEG_ABS_SUM :
XRFDC_CALIB_MODE_ABS_DIFF));
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Analog_Datapath[Index].CalibrationMode =
CalibrationMode;
}
}
Status = XRFDC_SUCCESS;
return Status;
}
/*****************************************************************************/
/**
*
* This API is to get the Calibration mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param CalibrationModePtr pointer to get the calibration mode.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_GetCalibrationMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u8 *CalibrationModePtr)
{
u32 Status;
u16 ReadReg;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CalibrationModePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if (InstancePtr->ADC_Tile[Tile_Id].MultibandConfig != XRFDC_MB_MODE_SB) {
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
} else {
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
}
} else {
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
}
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
if (Block_Id == XRFDC_BLK_ID1) {
Block_Id = XRFDC_BLK_ID3;
}
if (Block_Id == XRFDC_BLK_ID0) {
Block_Id = XRFDC_BLK_ID1;
}
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL0_OFFSET, XRFDC_TI_DCB_MODE_MASK);
*CalibrationModePtr = (ReadReg != 0U) ? XRFDC_CALIB_MODE1 : XRFDC_CALIB_MODE2;
} else {
*CalibrationModePtr =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_TISK_CRL5_OFFSET, XRFDC_CAL_MODES_MASK);
*CalibrationModePtr = (*CalibrationModePtr == XRFDC_CALIB_MODE_NEG_ABS_SUM) ?
XRFDC_CALIB_MODE1 :
XRFDC_CALIB_MODE2; /*mode 0 same as XRFDC_CALIB_MODE_MIXER*/
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is used to set the mode for the Inverse-Sinc filter.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is DAC block number inside the tile. Valid values
* are 0-3.
* @param Mode valid values are 0(disable), 1(1st Nyquist zone)
and 2(2nd Nyquist zone).
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if block not enabled/invalid mode.
*
* @note Only DAC blocks
*
******************************************************************************/
u32 XRFdc_SetInvSincFIR(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 Mode)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (Mode > ((InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) ? XRFDC_INV_SYNC_EN_MAX : XRFDC_INV_SYNC_MODE_MAX)) {
metal_log(METAL_LOG_ERROR, "\n Invalid mode value (%u) for DAC %u block %u in %s\r\n", Mode, Tile_Id,
Block_Id, __func__);
;
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
XRFdc_ClrSetReg(
InstancePtr, BaseAddr, XRFDC_DAC_INVSINC_OFFSET,
(InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) ? XRFDC_EN_INVSINC_MASK : XRFDC_MODE_INVSINC_MASK, Mode);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is used to get the Inverse-Sinc filter mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is DAC block number inside the tile. Valid values
* are 0-3.
* @param ModePtr is a pointer to get the inv-sinc status. valid values
* are 0(disable), 1(1st Nyquist zone) and 2(2nd Nyquist zone).
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only DAC blocks
*
******************************************************************************/
u32 XRFdc_GetInvSincFIR(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 *ModePtr)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Xil_AssertNonvoid(ModePtr != NULL);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
*ModePtr = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_INVSINC_OFFSET,
(InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) ? XRFDC_EN_INVSINC_MASK :
XRFDC_MODE_INVSINC_MASK);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Static API to dump ADC registers.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3, and -1.
*
* @return
* None
*
* @note None.
*
******************************************************************************/
static void XRFdc_DumpADCRegs(XRFdc *InstancePtr, int Tile_Id)
{
u32 BlockId;
u32 Block;
u32 IsBlockAvail;
u32 Offset;
u32 BaseAddr;
u32 ReadReg = 0U;
for (BlockId = XRFDC_BLK_ID0; BlockId < XRFDC_BLK_ID4; BlockId++) {
Block = BlockId;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
if (BlockId == XRFDC_BLK_ID1) {
Block = XRFDC_BLK_ID0;
}
if ((BlockId == XRFDC_BLK_ID3) || (BlockId == XRFDC_BLK_ID2)) {
Block = XRFDC_BLK_ID1;
}
}
IsBlockAvail = XRFdc_IsADCBlockEnabled(InstancePtr, Tile_Id, Block);
if (IsBlockAvail == 0U) {
IsBlockAvail = XRFdc_IsADCDigitalPathEnabled(InstancePtr, Tile_Id, Block);
if (IsBlockAvail == 0U) {
continue;
}
}
metal_log(METAL_LOG_DEBUG, "\n ADC%d%d:: \r\n", Tile_Id, BlockId);
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(BlockId);
for (Offset = 0x0U; Offset <= 0x284U; Offset += 0x4U) {
if ((Offset >= 0x24U && Offset <= 0x2CU) || (Offset >= 0x48U && Offset <= 0x7CU) ||
(Offset >= 0xACU && Offset <= 0xC4U) || (Offset >= 0x114U && Offset <= 0x13CU) ||
(Offset >= 0x188U && Offset <= 0x194U) || (Offset >= 0x1B8U && Offset <= 0x1BCU) ||
(Offset >= 0x1D8U && Offset <= 0x1FCU) || (Offset >= 0x240U && Offset <= 0x27CU)) {
continue;
}
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, Offset);
metal_log(METAL_LOG_DEBUG, "\n offset = 0x%x and Value = 0x%x \t", Offset, ReadReg);
}
}
(void)ReadReg;
}
/*****************************************************************************/
/**
*
* Static API to dump DAC registers.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3, and -1.
*
* @return
* None
*
* @note None.
*
******************************************************************************/
static void XRFdc_DumpDACRegs(XRFdc *InstancePtr, int Tile_Id)
{
u32 BlockId;
u32 IsBlockAvail;
u32 Offset;
u32 BaseAddr;
u32 ReadReg = 0U;
for (BlockId = XRFDC_BLK_ID0; BlockId < XRFDC_BLK_ID4; BlockId++) {
IsBlockAvail = XRFdc_IsDACBlockEnabled(InstancePtr, Tile_Id, BlockId);
if (IsBlockAvail == 0U) {
IsBlockAvail = XRFdc_IsDACDigitalPathEnabled(InstancePtr, Tile_Id, BlockId);
if (IsBlockAvail == 0U) {
continue;
}
}
metal_log(METAL_LOG_DEBUG, "\n DAC%d%d:: \r\n", Tile_Id, BlockId);
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(BlockId);
for (Offset = 0x0U; Offset <= 0x24CU; Offset += 0x4U) {
if ((Offset >= 0x28U && Offset <= 0x34U) || (Offset >= 0x48U && Offset <= 0x7CU) ||
(Offset >= 0xA8U && Offset <= 0xBCU) || (Offset >= 0xE4U && Offset <= 0xFCU) ||
(Offset >= 0x16CU && Offset <= 0x17CU) || (Offset >= 0x198U && Offset <= 0x1BCU) ||
(Offset >= 0x1ECU && Offset <= 0x1FCU) || (Offset >= 0x204U && Offset <= 0x23CU)) {
continue;
}
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, Offset);
metal_log(METAL_LOG_DEBUG, "\n offset = 0x%x and Value = 0x%x \t", Offset, ReadReg);
}
}
(void)ReadReg;
}
/*****************************************************************************/
/**
*
* Static API to dump HSCOM registers.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
*
* @return
* None
*
* @note None.
*
******************************************************************************/
static void XRFdc_DumpHSCOMRegs(XRFdc *InstancePtr, u32 Type, int Tile_Id)
{
u32 Offset;
u32 BaseAddr;
u32 ReadReg = 0U;
if (Type == XRFDC_ADC_TILE) {
metal_log(METAL_LOG_DEBUG, "\n ADC%d HSCOM:: \r\n", Tile_Id);
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_HSCOM_ADDR;
} else {
metal_log(METAL_LOG_DEBUG, "\n DAC%d HSCOM:: \r\n", Tile_Id);
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_HSCOM_ADDR;
}
metal_log(METAL_LOG_DEBUG, "\n Offset\tValue \r\n");
for (Offset = 0x0U; Offset <= 0x148U; Offset += 0x4U) {
if ((Offset >= 0x60U && Offset <= 0x88U) || (Offset == 0xBCU) || (Offset >= 0xC4U && Offset <= 0xFCU) ||
(Offset >= 0x110U && Offset <= 0x11CU) || (Offset >= 0x12CU && Offset <= 0x13CU)) {
continue;
}
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, Offset);
metal_log(METAL_LOG_DEBUG, "\n 0x%x \t 0x%x \t", Offset, ReadReg);
}
(void)ReadReg;
}
/*****************************************************************************/
/**
*
* This Prints the offset of the register along with the content. This API is
* meant to be used for debug purposes. It prints to the console the contents
* of registers for the passed Tile_Id. If -1 is passed, it prints the contents
* of the registers for all the tiles for the respective ADC or DAC
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
*
* @return
* None
*
* @note None.
*
******************************************************************************/
void XRFdc_DumpRegs(XRFdc *InstancePtr, u32 Type, int Tile_Id)
{
u16 NoOfTiles;
u16 Index;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (Tile_Id == XRFDC_SELECT_ALL_TILES) {
NoOfTiles = XRFDC_NUM_OF_TILES4;
} else {
NoOfTiles = XRFDC_NUM_OF_TILES1;
}
for (Index = XRFDC_TILE_ID0; Index < NoOfTiles; Index++) {
if (NoOfTiles == XRFDC_NUM_OF_TILES4) {
Tile_Id = Index;
}
if (Type == XRFDC_ADC_TILE) {
XRFdc_DumpADCRegs(InstancePtr, Tile_Id);
} else {
XRFdc_DumpDACRegs(InstancePtr, Tile_Id);
}
XRFdc_DumpHSCOMRegs(InstancePtr, Type, Tile_Id);
}
}
/*****************************************************************************/
/**
*
* This is a stub for the status callback. The stub is here in case the upper
* layers forget to set the handler.
*
* @param CallBackRefPtr is a pointer to the upper layer callback reference.
* @param Type indicates ADC/DAC.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number (0-3).
* @param StatusEvent indicates one or more interrupt occurred.
*
* @note None.
*
* @note None.
*
******************************************************************************/
static void StubHandler(void *CallBackRefPtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 StatusEvent)
{
(void)((void *)CallBackRefPtr);
(void)Type;
(void)Tile_Id;
(void)Block_Id;
(void)StatusEvent;
Xil_AssertVoidAlways();
}
/*****************************************************************************/
/**
*
* This function is used to get the Link Coupling mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number(0-3 for 2G, 0-1 for 4G).
* @param ModePtr pointer to get link coupling mode.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_GetLinkCoupling(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr)
{
u32 Status;
u16 ReadReg;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ModePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Block_Id);
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_RXPR_MC_CFG0_OFFSET, XRFDC_RX_MC_CFG0_CM_MASK);
if (ReadReg != 0U) {
*ModePtr = XRFDC_LINK_COUPLING_AC;
} else {
*ModePtr = XRFDC_LINK_COUPLING_DC;
}
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
*ModePtr = !(*ModePtr); /*logic is inverted for GEN3 devices */
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to set the IM3 Dither mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number(0-3 for LS, 0-1 for HS).
* @param Mode 0: Disable
* 1: Enable
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_SetDither(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode)
{
u32 Status;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (Mode > XRFDC_DITH_ENABLE) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid Dither Mode (%u) for ADC %u block %u in %s\r\n", Mode, Tile_Id,
Block_Id, __func__);
goto RETURN_PATH;
}
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_DAC_MC_CFG0_OFFSET, XRFDC_RX_MC_CFG0_IM3_DITH_MASK,
(Mode << XRFDC_RX_MC_CFG0_IM3_DITH_SHIFT));
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to get the IM3 Dither mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number(0-3 for LS, 0-1 for HS).
* @param ModePtr pointer to get link coupling mode.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_GetDither(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr)
{
u32 Status;
u16 ReadReg;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ModePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Block_Id);
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_DAC_MC_CFG0_OFFSET, XRFDC_RX_MC_CFG0_IM3_DITH_MASK);
if (ReadReg != 0U) {
*ModePtr = XRFDC_DITH_ENABLE;
} else {
*ModePtr = XRFDC_DITH_DISABLE;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to set the ADC Signal Detector Settings.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number(0-3 for LS, 0-1 for HS).
* @param SettingsPtr pointer to the XRFdc_Signal_Detector_Settings structure
* to set the signal detector configurations
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if tile not enabled, or invalid values.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_SetSignalDetector(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Signal_Detector_Settings *SettingsPtr)
{
u32 Status;
u32 BaseAddr;
u32 Index;
u32 NoOfBlocks;
u16 SignalDetCtrlReg = 0;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(SettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested fuctionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (SettingsPtr->Mode > XRFDC_SIGDET_MODE_RNDM) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid Signal Detector Mode (%u) for ADC %u block %u in %s\r\n",
SettingsPtr->Mode, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (SettingsPtr->EnableIntegrator > XRFDC_ENABLED) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR,
"\n Invalid Signal Detector Integrator Enable (%u) for ADC %u block %u in %s\r\n",
SettingsPtr->EnableIntegrator, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (SettingsPtr->HysteresisEnable > XRFDC_ENABLED) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR,
"\n Invalid Signal Detector Hysteresis Enable (%u) for ADC %u block %u in %s\r\n",
SettingsPtr->HysteresisEnable, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (SettingsPtr->Flush > XRFDC_ENABLED) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid Signal Detector Flush Option (%u) for ADC %u block %u in %s\r\n",
SettingsPtr->Flush, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (SettingsPtr->TimeConstant > XRFDC_SIGDET_TC_2_18) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR,
"\n Invalid Signal Detector Time Constant (%u) for ADC %u block %u in %s\r\n",
SettingsPtr->TimeConstant, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
SignalDetCtrlReg |= SettingsPtr->EnableIntegrator << XRFDC_ADC_SIG_DETECT_INTG_SHIFT;
SignalDetCtrlReg |= SettingsPtr->Flush << XRFDC_ADC_SIG_DETECT_FLUSH_SHIFT;
SignalDetCtrlReg |= SettingsPtr->TimeConstant << XRFDC_ADC_SIG_DETECT_TCONST_SHIFT;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
SignalDetCtrlReg |= ((SettingsPtr->Mode << 1) | 1) << XRFDC_ADC_SIG_DETECT_MODE_WRITE_SHIFT;
} else {
SignalDetCtrlReg |= (SettingsPtr->Mode << 1) << XRFDC_ADC_SIG_DETECT_MODE_WRITE_SHIFT;
}
SignalDetCtrlReg |= SettingsPtr->HysteresisEnable << XRFDC_ADC_SIG_DETECT_HYST_SHIFT;
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_CTRL_OFFSET, XRFDC_ADC_SIG_DETECT_MASK,
SignalDetCtrlReg);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET,
SettingsPtr->HighThreshold);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD1_LEVEL_OFFSET,
SettingsPtr->LowThreshold);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_ON_OFFSET,
SettingsPtr->HighThreshOnTriggerCnt);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_OFF_OFFSET,
SettingsPtr->HighThreshOffTriggerCnt);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_ON_OFFSET,
SettingsPtr->LowThreshOnTriggerCnt);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_OFF_OFFSET,
SettingsPtr->LowThreshOffTriggerCnt);
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to get the ADC Signal Detector Settings.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number(0-3 for LS, 0-1 for HS).
* @param SettingsPtr pointer to the XRFdc_Signal_Detector_Settings structure
* to get the signal detector configurations
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_GetSignalDetector(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Signal_Detector_Settings *SettingsPtr)
{
u32 Status;
u32 BaseAddr;
u16 SignalDetCtrlReg = 0;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(SettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested functionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Block_Id == XRFDC_BLK_ID1)) {
Block_Id = XRFDC_BLK_ID2;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Block_Id);
SignalDetCtrlReg =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_CTRL_OFFSET, XRFDC_ADC_SIG_DETECT_MASK);
SettingsPtr->EnableIntegrator =
(SignalDetCtrlReg & XRFDC_ADC_SIG_DETECT_INTG_MASK) >> XRFDC_ADC_SIG_DETECT_INTG_SHIFT;
SettingsPtr->Flush = (SignalDetCtrlReg & XRFDC_ADC_SIG_DETECT_FLUSH_MASK) >> XRFDC_ADC_SIG_DETECT_FLUSH_SHIFT;
SettingsPtr->TimeConstant =
(SignalDetCtrlReg & XRFDC_ADC_SIG_DETECT_TCONST_MASK) >> XRFDC_ADC_SIG_DETECT_TCONST_SHIFT;
SettingsPtr->Mode = (SignalDetCtrlReg & XRFDC_ADC_SIG_DETECT_MODE_MASK) >> XRFDC_ADC_SIG_DETECT_MODE_READ_SHIFT;
SettingsPtr->HysteresisEnable =
(SignalDetCtrlReg & XRFDC_ADC_SIG_DETECT_HYST_MASK) >> XRFDC_ADC_SIG_DETECT_HYST_SHIFT;
SettingsPtr->HighThreshold =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET);
SettingsPtr->LowThreshold =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD1_LEVEL_OFFSET);
SettingsPtr->HighThreshOnTriggerCnt =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_ON_OFFSET);
SettingsPtr->HighThreshOffTriggerCnt =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_OFF_OFFSET);
SettingsPtr->LowThreshOnTriggerCnt =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_ON_OFFSET);
SettingsPtr->LowThreshOffTriggerCnt =
XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_OFF_OFFSET);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to disable Calibration Coefficients override.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number(0-3 for LS, 0-1 for HS).
* @param CalibrationBlock indicates the calibration block.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_DisableCoefficientsOverride(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock)
{
u32 BaseAddr;
u32 Status;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) && (CalibrationBlock == XRFDC_CAL_BLOCK_OCB1)) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested functionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
switch (CalibrationBlock) {
case XRFDC_CAL_BLOCK_OCB1:
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL1_OFFSET, XRFDC_CAL_OCB_EN_MASK,
XRFDC_DISABLED);
break;
case XRFDC_CAL_BLOCK_OCB2:
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL3_OFFSET, XRFDC_CAL_OCB_EN_MASK,
XRFDC_DISABLED);
break;
case XRFDC_CAL_BLOCK_GCB:
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL1_OFFSET,
XRFDC_CAL_GCB_ENFL_MASK, XRFDC_CAL_GCB_ACEN_MASK);
/*Clear IP Override Coeffs*/
XRFdc_ClrSetReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF0_FAB(Index), XRFDC_CAL_GCB_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF1_FAB(Index), XRFDC_CAL_GCB_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF2_FAB(Index), XRFDC_CAL_GCB_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF3_FAB(Index), XRFDC_CAL_GCB_MASK, XRFDC_DISABLED);
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL1_OFFSET,
XRFDC_CAL_GCB_EN_MASK, XRFDC_DISABLED);
}
break;
case XRFDC_CAL_BLOCK_TSCB:
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF0,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF1,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF2,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF3,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF4,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF5,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF6,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF7,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_DISABLED);
}
break;
default:
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid Calibration Mode (%u) for ADC %u block %u in %s\r\n",
CalibrationBlock, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to set the ADC Calibration Coefficients.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number(0-3 for LS, 0-1 for HS).
* @param CalibrationBlock indicates the block to be written to.
* @param CoeffPtr is pointer to the XRFdc_Calibration_Coefficients structure
* to set the calibration coefficients.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_SetCalCoefficients(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock,
XRFdc_Calibration_Coefficients *CoeffPtr)
{
u32 BaseAddr;
u32 Status;
u32 Index;
u32 NoOfBlocks;
u32 HighSpeed;
u32 Shift;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CoeffPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if ((InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) && (CalibrationBlock == XRFDC_CAL_BLOCK_OCB1)) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested functionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
if (CalibrationBlock == XRFDC_CAL_BLOCK_GCB) {
if ((CoeffPtr->Coeff0 | CoeffPtr->Coeff1 | CoeffPtr->Coeff2 | CoeffPtr->Coeff3) &
~(XRFDC_CAL_GCB_MASK | (XRFDC_CAL_GCB_MASK << XRFDC_CAL_SLICE_SHIFT))) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR,
"\n Bad GCB Coefficient(s) {%u %u %u %u} for ADC %u block %u in %s\r\n",
CoeffPtr->Coeff0, CoeffPtr->Coeff1, CoeffPtr->Coeff2, CoeffPtr->Coeff3, Tile_Id,
Block_Id, __func__);
goto RETURN_PATH;
}
}
if (CalibrationBlock == XRFDC_CAL_BLOCK_TSCB) {
if ((CoeffPtr->Coeff0 | CoeffPtr->Coeff1 | CoeffPtr->Coeff2 | CoeffPtr->Coeff3 | CoeffPtr->Coeff4 |
CoeffPtr->Coeff5 | CoeffPtr->Coeff6 | CoeffPtr->Coeff7) &
~(XRFDC_CAL_TSCB_MASK | (XRFDC_CAL_TSCB_MASK << XRFDC_CAL_SLICE_SHIFT))) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR,
"\n Bad TSCB Coefficient(s) {%u %u %u %u %u %u %u %u} for ADC %u block %u in %s\r\n",
CoeffPtr->Coeff0, CoeffPtr->Coeff1, CoeffPtr->Coeff2, CoeffPtr->Coeff3,
CoeffPtr->Coeff4, CoeffPtr->Coeff5, CoeffPtr->Coeff6, CoeffPtr->Coeff7, Tile_Id,
Block_Id, __func__);
goto RETURN_PATH;
}
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Index = Block_Id;
HighSpeed = XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id);
if (HighSpeed == XRFDC_ENABLED) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
Shift = HighSpeed ? XRFDC_CAL_SLICE_SHIFT * (Index % 2) : 0;
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
switch (CalibrationBlock) {
case XRFDC_CAL_BLOCK_OCB1:
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL1_OFFSET, XRFDC_CAL_OCB_EN_MASK,
XRFDC_ENABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB1_OFFSET_COEFF0, XRFDC_CAL_OCB_MASK,
CoeffPtr->Coeff0 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB1_OFFSET_COEFF1, XRFDC_CAL_OCB_MASK,
CoeffPtr->Coeff1 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB1_OFFSET_COEFF2, XRFDC_CAL_OCB_MASK,
CoeffPtr->Coeff2 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB1_OFFSET_COEFF3, XRFDC_CAL_OCB_MASK,
CoeffPtr->Coeff3 >> Shift);
break;
case XRFDC_CAL_BLOCK_OCB2:
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL3_OFFSET, XRFDC_CAL_OCB_EN_MASK,
XRFDC_ENABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB2_OFFSET_COEFF0, XRFDC_CAL_OCB_MASK,
CoeffPtr->Coeff0 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB2_OFFSET_COEFF1, XRFDC_CAL_OCB_MASK,
CoeffPtr->Coeff1 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB2_OFFSET_COEFF2, XRFDC_CAL_OCB_MASK,
CoeffPtr->Coeff2 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB2_OFFSET_COEFF3, XRFDC_CAL_OCB_MASK,
CoeffPtr->Coeff3 >> Shift);
break;
case XRFDC_CAL_BLOCK_GCB:
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL1_OFFSET,
XRFDC_CAL_GCB_ACEN_MASK, XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL1_OFFSET,
XRFDC_CAL_GCB_FLSH_MASK, XRFDC_ENABLED << XRFDC_CAL_GCB_FLSH_SHIFT);
XRFdc_ClrSetReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF0_FAB(Index), XRFDC_CAL_GCB_MASK,
CoeffPtr->Coeff0 >> Shift);
XRFdc_ClrSetReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF1_FAB(Index), XRFDC_CAL_GCB_MASK,
CoeffPtr->Coeff1 >> Shift);
XRFdc_ClrSetReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF2_FAB(Index), XRFDC_CAL_GCB_MASK,
CoeffPtr->Coeff2 >> Shift);
XRFdc_ClrSetReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF3_FAB(Index), XRFDC_CAL_GCB_MASK,
CoeffPtr->Coeff3 >> Shift);
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL1_OFFSET,
XRFDC_CAL_GCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_GCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF0, XRFDC_CAL_GCB_MASK,
CoeffPtr->Coeff0 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF1, XRFDC_CAL_GCB_MASK,
CoeffPtr->Coeff1 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF2, XRFDC_CAL_GCB_MASK,
CoeffPtr->Coeff2 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF3, XRFDC_CAL_GCB_MASK,
CoeffPtr->Coeff3 >> Shift);
}
break;
case XRFDC_CAL_BLOCK_TSCB:
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff0 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff1 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff2 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff3 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff4 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff5 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff6 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff7 >> Shift);
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF0,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF1,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF2,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF3,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF4,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF5,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF6,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF7,
XRFDC_CAL_TSCB_EN_MASK, XRFDC_ENABLED << XRFDC_CAL_TSCB_EN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF0,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff0 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF1,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff1 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF2,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff2 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF3,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff3 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF4,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff4 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF5,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff5 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF6,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff6 >> Shift);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF7,
XRFDC_CAL_TSCB_MASK, CoeffPtr->Coeff7 >> Shift);
}
break;
default:
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid calibration block (%u) for ADC %u block %u in %s\r\n",
CalibrationBlock, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to get the ADC Calibration Coefficients.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number(0-3 for LS, 0-1 for HS).
* @param CalibrationBlock indicates the block to be read from
* @param CoeffPtr is pointer to the XRFdc_Calibration_Coefficients structure
* to get the calibration coefficients.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_GetCalCoefficients(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock,
XRFdc_Calibration_Coefficients *CoeffPtr)
{
u32 BaseAddr;
u32 Status;
u32 Index;
u32 HighSpeed;
u32 Shift;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CoeffPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
memset(CoeffPtr, 0, sizeof(XRFdc_Calibration_Coefficients));
Index = Block_Id;
HighSpeed = XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id);
if (HighSpeed == XRFDC_ENABLED) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_ADC_TILE, Tile_Id, Index);
Shift = HighSpeed ? XRFDC_CAL_SLICE_SHIFT * (Index % 2) : 0;
switch (CalibrationBlock) {
case XRFDC_CAL_BLOCK_OCB1:
CoeffPtr->Coeff0 |=
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB1_OFFSET_COEFF0, XRFDC_CAL_OCB_MASK)
<< Shift;
CoeffPtr->Coeff1 |=
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB1_OFFSET_COEFF1, XRFDC_CAL_OCB_MASK)
<< Shift;
CoeffPtr->Coeff2 |=
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB1_OFFSET_COEFF2, XRFDC_CAL_OCB_MASK)
<< Shift;
CoeffPtr->Coeff3 |=
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB1_OFFSET_COEFF3, XRFDC_CAL_OCB_MASK)
<< Shift;
break;
case XRFDC_CAL_BLOCK_OCB2:
CoeffPtr->Coeff0 |=
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB2_OFFSET_COEFF0, XRFDC_CAL_OCB_MASK)
<< Shift;
CoeffPtr->Coeff1 |=
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB2_OFFSET_COEFF1, XRFDC_CAL_OCB_MASK)
<< Shift;
CoeffPtr->Coeff2 |=
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB2_OFFSET_COEFF2, XRFDC_CAL_OCB_MASK)
<< Shift;
CoeffPtr->Coeff3 |=
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_OCB2_OFFSET_COEFF3, XRFDC_CAL_OCB_MASK)
<< Shift;
break;
case XRFDC_CAL_BLOCK_GCB:
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if (XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_TI_DCB_CRL1_OFFSET,
XRFDC_CAL_GCB_FLSH_MASK) == XRFDC_DISABLED) {
CoeffPtr->Coeff0 |=
(XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF0_ALT,
XRFDC_CAL_GCB_FAB_MASK) >>
4)
<< Shift;
CoeffPtr->Coeff1 |=
(XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF1_ALT,
XRFDC_CAL_GCB_FAB_MASK) >>
4)
<< Shift;
CoeffPtr->Coeff2 |=
(XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF2_ALT,
XRFDC_CAL_GCB_FAB_MASK) >>
4)
<< Shift;
CoeffPtr->Coeff3 |=
(XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF3_ALT,
XRFDC_CAL_GCB_FAB_MASK) >>
4)
<< Shift;
} else {
CoeffPtr->Coeff0 |=
XRFdc_RDReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF0_FAB(Index), XRFDC_CAL_GCB_MASK)
<< Shift;
CoeffPtr->Coeff1 |=
XRFdc_RDReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF1_FAB(Index), XRFDC_CAL_GCB_MASK)
<< Shift;
CoeffPtr->Coeff2 |=
XRFdc_RDReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF2_FAB(Index), XRFDC_CAL_GCB_MASK)
<< Shift;
CoeffPtr->Coeff3 |=
XRFdc_RDReg(InstancePtr, XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id),
XRFDC_CAL_GCB_COEFF3_FAB(Index), XRFDC_CAL_GCB_MASK)
<< Shift;
}
} else {
CoeffPtr->Coeff0 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF0,
XRFDC_CAL_GCB_MASK)
<< Shift;
CoeffPtr->Coeff1 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF1,
XRFDC_CAL_GCB_MASK)
<< Shift;
CoeffPtr->Coeff2 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF2,
XRFDC_CAL_GCB_MASK)
<< Shift;
CoeffPtr->Coeff3 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_GCB_OFFSET_COEFF3,
XRFDC_CAL_GCB_MASK)
<< Shift;
}
break;
case XRFDC_CAL_BLOCK_TSCB:
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
CoeffPtr->Coeff0 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff1 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff2 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff3 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff4 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff5 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff6 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff7 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT,
XRFDC_CAL_TSCB_MASK)
<< Shift;
} else {
CoeffPtr->Coeff0 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF0,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff1 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF1,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff2 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF2,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff3 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF3,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff4 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF4,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff5 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF5,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff6 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF6,
XRFDC_CAL_TSCB_MASK)
<< Shift;
CoeffPtr->Coeff7 |= XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CAL_TSCB_OFFSET_COEFF7,
XRFDC_CAL_TSCB_MASK)
<< Shift;
}
break;
default:
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid calibration block (%u) for ADC %u block %u in %s\r\n",
CalibrationBlock, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to set calibration freeze settings.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number(0-3 for LS, 0-1 for HS).
* @param CalFreezePtr pointer to the settings to be applied.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_SetCalFreeze(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Cal_Freeze_Settings *CalFreezePtr)
{
u32 BaseAddr;
u32 Status;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CalFreezePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (CalFreezePtr->FreezeCalibration > XRFDC_CAL_FREEZE_CALIB) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid FreezeCalibration option (%u) for ADC %u block %u in %s\r\n",
CalFreezePtr->FreezeCalibration, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (CalFreezePtr->DisableFreezePin > XRFDC_CAL_FRZ_PIN_DISABLE) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid DisableFreezePin option (%u) for ADC %u block %u in %s\r\n",
CalFreezePtr->DisableFreezePin, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CONV_CAL_STGS(Index), XRFDC_CAL_FREEZE_PIN_MASK,
CalFreezePtr->DisableFreezePin << XRFDC_CAL_FREEZE_PIN_SHIFT);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CONV_CAL_STGS(Index), XRFDC_CAL_FREEZE_CAL_MASK,
CalFreezePtr->FreezeCalibration << XRFDC_CAL_FREEZE_CAL_SHIFT);
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This function is used to get calibration freeze settings and status.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number(0-3 for LS, 0-1 for HS).
* @param CalFreezePtr pointer to be filled the settings/status.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Only for ADC blocks
*
******************************************************************************/
u32 XRFdc_GetCalFreeze(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Cal_Freeze_Settings *CalFreezePtr)
{
u32 BaseAddr;
u32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CalFreezePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
if (Block_Id == XRFDC_BLK_ID1) {
Block_Id = XRFDC_BLK_ID2;
}
}
CalFreezePtr->CalFrozen =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CONV_CAL_STGS(Block_Id), XRFDC_CAL_FREEZE_STS_MASK) >>
XRFDC_CAL_FREEZE_STS_SHIFT;
CalFreezePtr->DisableFreezePin =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CONV_CAL_STGS(Block_Id), XRFDC_CAL_FREEZE_PIN_MASK) >>
XRFDC_CAL_FREEZE_PIN_SHIFT;
CalFreezePtr->FreezeCalibration =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CONV_CAL_STGS(Block_Id), XRFDC_CAL_FREEZE_CAL_MASK) >>
XRFDC_CAL_FREEZE_CAL_SHIFT;
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Set Output Current for DAC block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param uACurrent is the current in uA.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Range 6425 - 32000 uA with 25 uA resolution.
******************************************************************************/
u32 XRFdc_SetDACVOP(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 uACurrent)
{
u32 Status;
u32 BaseAddr;
u16 EFuse;
u16 Gen1CompatibilityMode;
u32 OptIdx;
u32 uACurrentNext;
u32 Code;
/* Tuned optimization values*/
u32 OptimLU[32] = { 5, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9,
9, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20 };
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested functionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
EFuse = XRFdc_ReadReg16(InstancePtr, XRFDC_DRP_BASE(XRFDC_DAC_TILE, Tile_Id) + XRFDC_HSCOM_ADDR,
XRFDC_HSCOM_EFUSE_2_OFFSET);
if ((EFuse & XRFDC_EXPORTCTRL_VOP) == XRFDC_EXPORTCTRL_VOP) {
if ((uACurrent != XRFDC_GEN1_LOW_I) && (uACurrent != XRFDC_GEN1_HIGH_I)) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n API not available - Licensing - for DAC %u block %u in %s\r\n",
Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
}
if (uACurrent > XRFDC_MAX_I_UA) {
metal_log(METAL_LOG_ERROR, "\n Invalid current selection (too high - %u) for DAC %u block %u in %s\r\n",
uACurrent, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (uACurrent < XRFDC_MIN_I_UA) {
metal_log(METAL_LOG_ERROR, "\n Invalid current selection (too low - %u) for DAC %u block %u in %s\r\n",
uACurrent, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (uACurrent % XRFDC_STEP_I_UA) {
metal_log(
METAL_LOG_ERROR,
"\n Invalid current selection (%u - please use a multiple of 25 uA) for DAC %u block %u in %s\r\n",
uACurrent, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
Gen1CompatibilityMode =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_DAC_MC_CFG2_OFFSET, XRFDC_DAC_MC_CFG2_GEN1_COMP_MASK);
if (Gen1CompatibilityMode == XRFDC_DAC_MC_CFG2_GEN1_COMP_MASK) {
metal_log(METAL_LOG_ERROR, "\n Invalid compatibility mode is set for DAC %u block %u in %s\r\n",
Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_VOP_CTRL_OFFSET,
(XRFDC_DAC_VOP_CTRL_REG_UPDT_MASK | XRFDC_DAC_VOP_CTRL_TST_BLD_MASK), XRFDC_DISABLED);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_DAC_MC_CFG0_OFFSET, XRFDC_DAC_MC_CFG0_CAS_BLDR_MASK,
XRFDC_CSCAS_BLDR);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_DAC_MC_CFG2_OFFSET,
(XRFDC_DAC_MC_CFG3_CSGAIN_MASK | XRFDC_DAC_MC_CFG2_CAS_BIAS_MASK),
(XRFDC_BLDR_GAIN | XRFDC_CSCAS_BIAS));
uACurrentNext = ((XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_MC_CFG3_OFFSET, XRFDC_DAC_MC_CFG3_CSGAIN_MASK)) *
XRFDC_STEP_I_UA) +
XRFDC_MIN_I_UA;
while (uACurrent != uACurrentNext) {
if (uACurrentNext < uACurrent) {
uACurrentNext += uACurrentNext / 10;
if (uACurrentNext > uACurrent)
uACurrentNext = uACurrent;
} else {
uACurrentNext -= uACurrentNext / 10;
if (uACurrentNext < uACurrent)
uACurrentNext = uACurrent;
}
Code = ((uACurrentNext - XRFDC_MIN_I_UA) / XRFDC_STEP_I_UA);
OptIdx = (Code & XRFDC_DAC_MC_CFG3_OPT_LUT_MASK) >> XRFDC_DAC_MC_CFG3_OPT_LUT_SHIFT;
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_MC_CFG3_OFFSET,
(XRFDC_DAC_MC_CFG3_CSGAIN_MASK | XRFDC_DAC_MC_CFG3_OPT_MASK),
((Code << XRFDC_DAC_MC_CFG3_CSGAIN_SHIFT) | OptimLU[OptIdx]));
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_MC_CFG3_OFFSET, XRFDC_DAC_MC_CFG3_UPDATE_MASK,
XRFDC_DAC_MC_CFG3_UPDATE_MASK);
#ifdef __BAREMETAL__
usleep(1);
#else
metal_sleep_usec(1);
#endif
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Gets VOP compatibility mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param mode is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param EnabledPtr is pointer a that is filled with whether the mode is
* enabled (1) or disabled(0).
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
******************************************************************************/
u32 XRFdc_GetDACCompMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *EnabledPtr)
{
u32 Status;
u32 BaseAddr;
u16 CompatibilityMode;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Xil_AssertNonvoid(EnabledPtr != NULL);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested functionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
CompatibilityMode =
XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_DAC_MC_CFG2_OFFSET, XRFDC_DAC_MC_CFG2_GEN1_COMP_MASK);
*EnabledPtr = (CompatibilityMode == XRFDC_DAC_MC_CFG2_GEN1_COMP_MASK) ? XRFDC_ENABLED : XRFDC_DISABLED;
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Sets VOP compatibility mode.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param mode is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param Enable is whether to enable (1) or disable(0) the compatibility
* mode.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note None.
******************************************************************************/
u32 XRFdc_SetDACCompMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Enable)
{
u32 Status;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested functionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n DAC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (Enable > XRFDC_ENABLED) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Bad enable parameter (%u) for DAC %u block %u in %s\r\n", Enable,
Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_DAC_MC_CFG2_OFFSET, XRFDC_DAC_MC_CFG2_GEN1_COMP_MASK,
Enable << XRFDC_DAC_MC_CFG2_GEN1_COMP_SHIFT);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Set DSA for ADC block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param Attenuation is the attenuation in dB
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Range 0 - 11 dB with 0.5 dB resolution.
******************************************************************************/
u32 XRFdc_SetDSA(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_DSA_Settings *SettingsPtr)
{
u32 Status;
u32 BaseAddr;
u16 EFuse;
u32 Code;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Xil_AssertNonvoid(SettingsPtr != NULL);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested functionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
EFuse = XRFdc_ReadReg16(InstancePtr, XRFDC_DRP_BASE(XRFDC_ADC_TILE, Tile_Id) + XRFDC_HSCOM_ADDR,
XRFDC_HSCOM_EFUSE_2_OFFSET);
if ((EFuse & XRFDC_EXPORTCTRL_DSA) == XRFDC_EXPORTCTRL_DSA) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n API not available - Licensing - for ADC %u block %u in %s\r\n", Tile_Id,
Block_Id, __func__);
goto RETURN_PATH;
}
if (SettingsPtr->Attenuation > XRFDC_MAX_ATTEN) {
metal_log(METAL_LOG_ERROR, "\n Invalid attenuation selection (too high - %f) in ADC %u block %u %s\r\n",
SettingsPtr->Attenuation, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (SettingsPtr->Attenuation < XRFDC_MIN_ATTEN) {
metal_log(METAL_LOG_ERROR, "\n Invalid current selection (too low - %f) in ADC %u block %u %s\r\n",
SettingsPtr->Attenuation, Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
Index = Block_Id;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
Code = (u32)((XRFDC_MAX_ATTEN - SettingsPtr->Attenuation) / XRFDC_STEP_ATTEN);
for (; Index < NoOfBlocks; Index++) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CONV_DSA_STGS(Index),
(XRFDC_ADC_DSA_CODE_MASK | XRFDC_ADC_DSA_RTS_PIN_MASK),
(Code | (SettingsPtr->DisableRTS << XRFDC_ADC_DSA_RTS_PIN_SHIFT)));
}
/*trigger*/
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DSA_UPDT_OFFSET, XRFDC_ADC_DSA_UPDT_MASK, XRFDC_ADC_DSA_UPDT_MASK);
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Get DSA for ADC block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param AttenuationPtr is the attenuation in dB
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Range 0 - ll dB with 0.5 dB resolution.
******************************************************************************/
u32 XRFdc_GetDSA(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_DSA_Settings *SettingsPtr)
{
u32 Status;
u32 BaseAddr;
u16 EFuse;
u32 Code;
u32 RTSENMode;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Xil_AssertNonvoid(SettingsPtr != NULL);
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Requested functionality not available for this IP in %s\r\n", __func__);
goto RETURN_PATH;
}
Status = XRFdc_CheckBlockEnabled(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n ADC %u block %u not available in %s\r\n", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
EFuse = XRFdc_ReadReg16(InstancePtr, XRFDC_DRP_BASE(XRFDC_ADC_TILE, Tile_Id) + XRFDC_HSCOM_ADDR,
XRFDC_HSCOM_EFUSE_2_OFFSET);
if ((EFuse & XRFDC_EXPORTCTRL_DSA) == XRFDC_EXPORTCTRL_DSA) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n API not available - Licensing - for ADC %u block %u in %s\r\n", Tile_Id,
Block_Id, __func__);
goto RETURN_PATH;
}
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
if (Block_Id == XRFDC_BLK_ID1) {
Block_Id = XRFDC_BLK_ID2;
}
}
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
Code = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CONV_DSA_STGS(Block_Id), XRFDC_ADC_DSA_CODE_MASK);
RTSENMode = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_CONV_DSA_STGS(Block_Id), XRFDC_ADC_DSA_RTS_PIN_MASK);
SettingsPtr->Attenuation = XRFDC_MAX_ATTEN - (float)(Code * XRFDC_STEP_ATTEN);
SettingsPtr->DisableRTS = RTSENMode >> XRFDC_ADC_DSA_RTS_PIN_SHIFT;
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/clockps_v1_2/src/xclockps_sinit.c
/******************************************************************************
* Copyright (C) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xclockps_sinit.c
* @addtogroup xclockps_v1_2
* @{
*
* This file contains method for static initialization (compile-time) of the
* driver.
*
* <pre>
* MODIFICATION HISTORY:
* Ver Who Date Changes
* ----- ------ -------- ----------------------------------------------
* 1.00 cjp 02/09/18 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xclockps.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*************************** Variable Definitions ****************************/
/**
* configuration table defined in xclockps_g.c
*/
extern XClockPs_Config XClockPs_ConfigTable[XPAR_XCLOCKPS_NUM_INSTANCES];
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* contains the configuration info for each device in the system.
*
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
*
******************************************************************************/
XClockPs_Config *XClock_LookupConfig(u16 DeviceId)
{
XClockPs_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; Index < (u32)XPAR_XCLOCKPS_NUM_INSTANCES; Index++) {
if (XClockPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XClockPs_ConfigTable[Index];
break;
}
}
return (XClockPs_Config *)CfgPtr;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_notifier.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_NOTIFIER_H_
#define XPM_NOTIFIER_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xpm_subsystem.h"
#include "xpm_device.h"
extern void (* PmRequestCb)(u32 SubsystemId, const u32 EventId, u32 *Payload);
int XPmNotifier_Register(const XPm_Subsystem* const Subsystem,
const u32 NodeId,
const u32 Event, const u32 Wake, const u32 IpiMask);
void XPmNotifier_Unregister(const XPm_Subsystem* const Subsystem,
const u32 NodeId,
const u32 Event);
void XPmNotifier_UnregisterAll(const XPm_Subsystem* const Subsystem);
void XPmNotifier_Event(const u32 NodeId, const u32 Event);
#ifdef __cplusplus
}
#endif
#endif /* XPM_NOTIFIER_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_reset.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* Implementation of reset configuration mechanism within
* power management.
*********************************************************************/
#ifndef PM_RESET_H_
#define PM_RESET_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
#include "gpio.h"
#include "pm_common.h"
/*********************************************************************
* Structure definitions
********************************************************************/
typedef struct PmReset PmReset;
typedef struct PmMaster PmMaster;
/*********************************************************************
* Function declarations
********************************************************************/
u32 PmResetGetStatusInt(const PmReset* const resetPtr, u32 *status);
s32 PmResetDoAssert(const PmReset *reset, u32 action);
s32 PmResetAssertInt(u32 reset, u32 action);
s32 PmResetSetConfig(const u32 resetId, const u32 permissions);
void PmResetClearConfig(void);
bool PmResetMasterHasAccess(const PmMaster* const m, const PmReset* const r);
PmReset* PmGetResetById(const u32 resetId);
#ifdef __cplusplus
}
#endif
#endif /* PM_RESET_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_bisr.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_common.h"
#include "xpm_regs.h"
#include "xpm_bisr.h"
#include "xpm_npdomain.h"
#include "xpm_powerdomain.h"
#include "xpm_pslpdomain.h"
#include "xpm_core.h"
#include "xpm_pmc.h"
#include "xpm_power.h"
#include "xpm_device.h"
#include "xpm_psfpdomain.h"
#include "xpm_cpmdomain.h"
#include "xpm_pldomain.h"
/* Defines */
#define PMC_EFUSE_BISR_EXIT_CODE (0U)
#define PMC_EFUSE_BISR_SKIP_CODE (0xFFFFFFFFU)
#define PMC_EFUSE_BISR_TAG_ID_MASK (0xFF000000U)
#define PMC_EFUSE_BISR_TAG_ID_SHIFT (24U)
#define PMC_EFUSE_BISR_SIZE_MASK (0x00FF0000U)
#define PMC_EFUSE_BISR_SIZE_SHIFT (16U)
#define PMC_EFUSE_BISR_OPTIONAL_MASK (0x0000FFFFU)
#define PMC_EFUSE_BISR_OPTIONAL_SHIFT (0U)
#define TAG_ID_VALID_MASK (0x80000000U)
#define TAG_ID_VALID_SHIFT (31U)
#define TAG_ID_TYPE_MASK (0x7FFFFFFFU)
#define TAG_ID_TYPE_SHIFT (0U)
#define TAG_ID_TYPE_ME (1U)
#define TAG_ID_TYPE_CFRM_HB (2U)
#define TAG_ID_TYPE_CFRM_BR (3U)
#define TAG_ID_TYPE_CFRM_UR (4U)
#define TAG_ID_TYPE_DDRMC (5U)
#define TAG_ID_TYPE_CPM (6U)
#define TAG_ID_TYPE_GTY (7U)
#define TAG_ID_TYPE_LPD (8U)
#define TAG_ID_TYPE_FPD (9U)
#define TAG_ID_TYPE_CPM5 (10U)
#define TAG_ID_TYPE_CPM5_GTYP (11U)
#define TAG_ID_TYPE_GTYP (12U)
#define TAG_ID_TYPE_GTM (13U)
#define TAG_ID_TYPE_XRAM (14U)
#define TAG_ID_ARRAY_SIZE (256U)
#define PMC_EFUSE_BISR_UNKN_TAG_ID (0x1U)
#define PMC_EFUSE_BISR_INVLD_TAG_ID (0x2U)
#define PMC_EFUSE_BISR_BAD_TAG_TYPE (0x3U)
#define PMC_EFUSE_BISR_UNSUPPORTED_ID (0x4U)
#define PMC_EFUSE_BISR_CFRM_HB_BAD_SIZE (0x5U)
#ifndef VIVADO_ME_BASEADDR
#define VIVADO_ME_BASEADDR (0x0200000000U)
#endif
#define ME_BISR_FIXED_OFFSET (0x36010U)
#define ME_BISR_FIXED_OFFSET_MASK (0x00000FFFFFU)
#define ME_BISR_FIXED_OFFSET_SHIFT (0U)
#define ME_BISR_EFUSE_OFFSET_MASK (0x0FFFF00000U)
#define ME_BISR_EFUSE_OFFSET_SHIFT (20U)
#define ME_BISR_CACHE_CTRL_OFFSET (0x36000U)
#define ME_BISR_CACHE_CTRL_BISR_TRIGGER_MASK (0x00000001U)
#define ME_BISR_CACHE_STATUS_OFFSET (0x36008U)
#define ME_BISR_CACHE_STATUS_BISR_DONE_MASK (0x00000001U)
#define ME_BISR_CACHE_STATUS_BISR_PASS_MASK (0x00000002U)
#define NPI_FIXED_BASEADDR (0x00F6000000U)
#define NPI_FIXED_MASK (0x00FE000000U)
#define NPI_EFUSE_ENDPOINT_SHIFT (16U)
#define NPI_EFUSE_ENDPOINT_ADDR_MASK (0x0001FF0000U)
#define DDRMC_NPI_CACHE_STATUS_REGISTER_OFFSET (0x268U)
#define DDRMC_NPI_CACHE_DATA_REGISTER_OFFSET (0x258U)
#define DDRMC_NPI_PCSR_CONTROL_REGISTER_OFFSET (0x004U)
#define DDRMC_NPI_PCSR_MASK_REGISTER_OFFSET (0x000U)
#define DDRMC_NPI_PCSR_LOCK_REGISTER_OFFSET (0x00CU)
#define DDRMC_NPI_PCSR_BISR_TRIGGER_MASK (0x02000000U)
#define DDRMC_NPI_CACHE_STATUS_BISR_DONE_MASK (0x00000001U)
#define DDRMC_NPI_CACHE_STATUS_BISR_PASS_MASK (0x00000002U)
#define DDRMC_NPI_CLK_GATE_REGISTER_OFFSET (0x24CU)
#define DDRMC_NPI_CLK_GATE_BISREN_MASK (0x00000040U)
#define GTY_CACHE_DATA_REGISTER_OFFSET (0x64U)
//BRAM Repair
#define CFRM_BRAM_REPAIR_ROW_MASK (0x000f0000U)
#define CFRM_BRAM_REPAIR_ROW_SHIFT (16U)
#define CFRM_BRAM_REPAIR_COL_MASK (0x0000fc00U)
#define CFRM_BRAM_REPAIR_COL_SHIFT (10U)
#define CFRM_BRAM_REPAIR_INDEX_MASK (0x000003E0U)
#define CFRM_BRAM_REPAIR_INDEX_SHIFT (5U)
#define CFRM_BRAM_REPAIR_VAL_MASK (0x0000001FU)
#define CFRM_BRAM_REPAIR_VAL_SHIFT (0U)
#define CFRM_BRAM_EXP_REPAIR_BLK_TYPE_BRAM (0x3UL)
#define CFRM_BRAM_EXP_REPAIR_BLK_TYPE_MASK (0x00038000U)
#define CFRM_BRAM_EXP_REPAIR_BLK_TYPE_WIDTH (3U)
#define CFRM_BRAM_EXP_REPAIR_BLK_TYPE_SHIFT (15U)
#define CFRM_BRAM_EXP_REPAIR_COL_MASK (0x00007F80U)
#define CFRM_BRAM_EXP_REPAIR_COL_WIDTH (8U)
#define CFRM_BRAM_EXP_REPAIR_COL_SHIFT (7U)
#define CFRM_BRAM_EXP_REPAIR_INDEX_MASK (0x0000007FU)
#define CFRM_BRAM_EXP_REPAIR_INDEX_WIDTH (7U)
#define CFRM_BRAM_EXP_REPAIR_INDEX_SHIFT (0U)
#define CFRM_BRAM_EXP_REPAIR_VAL_MASK (0xFFFFFFFFU)
#define CFRM_BRAM_EXP_REPAIR_VAL_SHIFT (0U)
//URAM Repair
#define CFRM_URAM_REPAIR_ROW_MASK (0x000f0000U)
#define CFRM_URAM_REPAIR_ROW_SHIFT (16U)
#define CFRM_URAM_REPAIR_COL_MASK (0x0000f800U)
#define CFRM_URAM_REPAIR_COL_SHIFT (11U)
#define CFRM_URAM_REPAIR_INDEX_MASK (0x000007C0U)
#define CFRM_URAM_REPAIR_INDEX_SHIFT (6U)
#define CFRM_URAM_REPAIR_VAL_MASK (0x0000003FU)
#define CFRM_URAM_REPAIR_VAL_SHIFT (0U)
#define CFRM_URAM_EXP_REPAIR_BLK_TYPE_URAM (0x4UL)
#define CFRM_URAM_EXP_REPAIR_BLK_TYPE_MASK (0x00038000U)
#define CFRM_URAM_EXP_REPAIR_BLK_TYPE_WIDTH (3U)
#define CFRM_URAM_EXP_REPAIR_BLK_TYPE_SHIFT (15U)
#define CFRM_URAM_EXP_REPAIR_COL_MASK (0x00007F80U)
#define CFRM_URAM_EXP_REPAIR_COL_WIDTH (8U)
#define CFRM_URAM_EXP_REPAIR_COL_SHIFT (7U)
#define CFRM_URAM_EXP_REPAIR_INDEX_MASK (0x0000007FU)
#define CFRM_URAM_EXP_REPAIR_INDEX_WIDTH (7U)
#define CFRM_URAM_EXP_REPAIR_INDEX_SHIFT (0U)
#define CFRM_URAM_EXP_REPAIR_VAL_MASK (0xFFFFFFFFU)
#define CFRM_URAM_EXP_REPAIR_VAL_SHIFT (0U)
//CFRM_HB Repair
#define CFRM_HB_REPAIR_QTILE_MASK (0x03E00000U)
#define CFRM_HB_REPAIR_QTILE_SHIFT (21U)
#define CFRM_HB_REPAIR_COL_MASK (0x0C000000U)
#define CFRM_HB_REPAIR_COL_SHIFT (26U)
#define CFRM_HB_REPAIR_ROW_MASK (0xF0000000U)
#define CFRM_HB_REPAIR_ROW_SHIFT (28U)
#define CFRM_HB_REPAIR_VAL0_MASK (0x001FFFFFU) //value field in the first row
#define CFRM_HB_REPAIR_VAL0_SHIFT (0U)
#define CFRM_HB_REPAIR_VAL1_MASK (0xFFFFFFFFU) //value field in the second row
#define CFRM_HB_REPAIR_VAL1_SHIFT (0U)
#define CFRM_HB_EXP_REPAIR_BLK_TYPE (0x5UL)
#define CFRM_HB_EXP_REPAIR_BLK_TYPE_MASK (0x00038000U)
#define CFRM_HB_EXP_REPAIR_BLK_TYPE_WIDTH (3U)
#define CFRM_HB_EXP_REPAIR_BLK_TYPE_SHIFT (15U)
#define CFRM_HB_EXP_REPAIR_COL_MASK (0x00007F80U)
#define CFRM_HB_EXP_REPAIR_COL_WIDTH (8U)
#define CFRM_HB_EXP_REPAIR_COL_SHIFT (7U)
#define CFRM_HB_EXP_REPAIR_QTILE_MASK (0x0000007FU)
#define CFRM_HB_EXP_REPAIR_QTILE_WIDTH (7U)
#define CFRM_HB_EXP_REPAIR_QTILE_SHIFT (0U)
#define CFRM_HB_EXP_REPAIR_VAL_MASK (0xFFFFFFFFU)
#define CFRM_HB_EXP_REPAIR_VAL_SHIFT (0U)
#define CFRM_HB_EXP_REPAIR_VAL1_MASK (0x001FFFFFU)
#define CFRM_HB_EXP_REPAIR_VAL1_SHIFT (0U)
//CPM5_GTYP Repair
#define CPM5_GTYP_FIXED_BASEADDR (0xFC000000U)
#define CPM5_GTYP_EFUSE_ENDPOINT_SHIFT (16U)
//NIDB Lane Repair
#define MAX_NIDB_EFUSE_GROUPS (0x5U)
#define NPI_ROOT_BASEADDR (NPI_BASEADDR + NPI_NIR_0_OFFSET)
#define NIDB_OFFSET_DIFF (0x00010000U)
#define NIDB_PCSR_LOCK_OFFSET (0x0000000CU)
#define NIDB_PCSR_MASK_OFFSET (0x00000000U)
#define NIDB_PCSR_MASK_ODISABLE_MASK (0x00000004U)
#define NIDB_PCSR_CONTROL_OFFSET (0x00000004U)
#define NIDB_LANE_REPAIR_UNLOCK_OFFSET (0x00000038U)
#define NIDB_LANE_REPAIR_UNLOCK_VAL (0xE6172839U)
#define NIDB_REPAIR_OFFSET (0x00000010U)
//XRAM Repair
#define XRAM_SLCR_PCSR_BISR_TRIGGER_MASK (0x08000000U)
#define XRAM_SLCR_PCSR_BISR_CLR_MASK (0x10000000U)
#define XRAM_SLCR_PCSR_PSR_BISR_DONE_MASK (0x00004000U)
#define XRAM_SLCR_PCSR_PSR_BISR_PASS_MASK (0x00008000U)
typedef struct XPm_NidbEfuseGrpInfo {
u8 RdnCntl;
u16 NpiBase;
u8 NpiOffset;
} XPm_NidbEfuseGrpInfo;
static u32 XPmTagIdWhiteList[TAG_ID_ARRAY_SIZE] = {0};
static void XPmBisr_InitTagIdList(void)
{
XPmTagIdWhiteList[LPD_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_LPD;
XPmTagIdWhiteList[FPD_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_FPD;
XPmTagIdWhiteList[CPM_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_CPM;
XPmTagIdWhiteList[CPM5_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_CPM5;
XPmTagIdWhiteList[MEA_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_ME;
XPmTagIdWhiteList[MEB_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_ME;
XPmTagIdWhiteList[MEC_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_ME;
XPmTagIdWhiteList[DDRMC_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_DDRMC;
XPmTagIdWhiteList[GTY_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_GTY;
XPmTagIdWhiteList[DCMAC_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_CFRM_HB;
XPmTagIdWhiteList[ILKN_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_CFRM_HB;
XPmTagIdWhiteList[MRMAC_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_CFRM_HB;
XPmTagIdWhiteList[SDFEC_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_CFRM_HB;
XPmTagIdWhiteList[BRAM_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_CFRM_BR;
XPmTagIdWhiteList[URAM_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_CFRM_UR;
XPmTagIdWhiteList[CPM5_GTYP_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_CPM5_GTYP;
XPmTagIdWhiteList[GTYP_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_GTYP;
XPmTagIdWhiteList[GTM_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_GTM;
XPmTagIdWhiteList[XRAM_TAG_ID] = TAG_ID_VALID_MASK | TAG_ID_TYPE_XRAM;
return;
}
static XStatus XPmBisr_TagSupportCheck(u32 TagId)
{
if (TAG_ID_VALID_MASK == (XPmTagIdWhiteList[TagId] & TAG_ID_VALID_MASK)) {
return XST_SUCCESS;
} else {
return XST_FAILURE;
}
}
static void XPmBisr_SwError(u32 ErrorCode)
{
XPm_Pmc *Pmc;
Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
if (NULL == Pmc) {
goto done;
}
XPm_Out32(Pmc->PmcGlobalBaseAddr + PMC_GLOBAL_PMC_GSW_ERR_OFFSET,
XPm_In32(Pmc->PmcGlobalBaseAddr + PMC_GLOBAL_PMC_GSW_ERR_OFFSET) |
((u32)1U << ErrorCode) |
(1UL << PMC_GLOBAL_PMC_GSW_ERR_CR_FLAG_SHIFT));
done:
return;
}
static u32 XPmBisr_CopyStandard(u32 EfuseTagAddr, u32 TagSize, u64 BisrDataDestAddr)
{
u64 TagRow;
u32 TagData;
u32 TagDataAddr;
//EFUSE Tag Data start pos
TagDataAddr = EfuseTagAddr + 4U;
XPm_Device *EfuseCache = XPmDevice_GetById(PM_DEV_EFUSE_CACHE);
if (NULL == EfuseCache) {
/* Return max possible address so error can be identified by caller */
TagDataAddr = ~0U;
goto done;
}
//Collect Repair data from EFUSE and write to endpoint base + word offset
TagRow = 0;
while (TagRow < (u64)TagSize) {
if (TagDataAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET) ||
TagDataAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET)) {
TagDataAddr += 4U;
}
TagData = XPm_In32(TagDataAddr);
swea(BisrDataDestAddr + (TagRow << 2U), TagData);
TagRow++;
TagDataAddr += 4U;
}
done:
return TagDataAddr;
}
static XStatus XPmBisr_RepairGty(u32 EfuseTagAddr, u32 TagSize, u32 TagOptional, u32 *TagDataAddr, u32 TagType)
{
XStatus Status = XST_FAILURE;
u32 RegValue, EfuseEndpointShift;
u32 BaseAddr, BisrDataDestAddr;
/* Modify Base Address based on the Tag type */
switch(TagType) {
case TAG_ID_TYPE_GTY:
case TAG_ID_TYPE_GTYP:
case TAG_ID_TYPE_GTM:
/* GTY, GTYP and GTM lie in NPI Address space */
BaseAddr = NPI_FIXED_BASEADDR;
EfuseEndpointShift = NPI_EFUSE_ENDPOINT_SHIFT;
Status = XST_SUCCESS;
break;
case TAG_ID_TYPE_CPM5_GTYP:
/* CPM5_GTYP lies in CPM5 Address space */
BaseAddr = CPM5_GTYP_FIXED_BASEADDR;
EfuseEndpointShift = CPM5_GTYP_EFUSE_ENDPOINT_SHIFT;
Status = XST_SUCCESS;
break;
default:
XPmBisr_SwError(PMC_EFUSE_BISR_UNSUPPORTED_ID);
Status = XST_FAILURE;
break;
}
if (XST_SUCCESS != Status) {
goto done;
}
BaseAddr = BaseAddr | (TagOptional<< EfuseEndpointShift);
BisrDataDestAddr = BaseAddr | GTY_CACHE_DATA_REGISTER_OFFSET;
/* Copy repair data */
*TagDataAddr = XPmBisr_CopyStandard(EfuseTagAddr, TagSize, BisrDataDestAddr);
/* Unlock PCSR */
PmOut32(BaseAddr | GTY_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
/* Trigger Bisr */
PmOut32(BaseAddr | GTY_PCSR_MASK_OFFSET, GTY_PCSR_BISR_TRIGGER_MASK);
PmOut32(BaseAddr | GTY_PCSR_CONTROL_OFFSET, GTY_PCSR_BISR_TRIGGER_MASK);
/* Wait for Bisr to finish */
Status = XPm_PollForMask(BaseAddr | GTY_PCSR_STATUS_OFFSET, GTY_PCSR_STATUS_BISR_DONE_MASK, XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
PmIn32(BaseAddr | GTY_PCSR_STATUS_OFFSET, RegValue);
if ((RegValue & GTY_PCSR_STATUS_BISR_PASS_MASK) != GTY_PCSR_STATUS_BISR_PASS_MASK) {
Status = XST_FAILURE;
goto done;
}
/* Unwrite Trigger Bit */
PmOut32(BaseAddr | GTY_PCSR_MASK_OFFSET, GTY_PCSR_BISR_TRIGGER_MASK);
PmOut32(BaseAddr | GTY_PCSR_CONTROL_OFFSET, 0);
/* Lock PCSR */
PmOut32(BaseAddr | GTY_PCSR_LOCK_OFFSET, 1);
done:
return Status;
}
static XStatus XPmBisr_RepairLpd(u32 EfuseTagAddr, u32 TagSize, u32 *TagDataAddr)
{
XStatus Status = XST_FAILURE;
u64 BisrDataDestAddr;
XPm_PsLpDomain *LpDomain = (XPm_PsLpDomain *)XPmPower_GetById(PM_POWER_LPD);
if (NULL == LpDomain) {
goto done;
}
BisrDataDestAddr = LpDomain->LpdSlcrBaseAddr + (u64)LPD_SLCR_BISR_CACHE_DATA_0_OFFSET;
/* Copy repair data */
*TagDataAddr = XPmBisr_CopyStandard(EfuseTagAddr, TagSize, BisrDataDestAddr);
LpDomain->LpdBisrFlags |= LPD_BISR_DATA_COPIED;
Status = XPmBisr_TriggerLpd();
done:
return Status;
}
int XPmBisr_TriggerLpd(void)
{
int Status = XST_FAILURE;
XPm_PsLpDomain *PsLpd;
u32 RegValue;
PsLpd = (XPm_PsLpDomain *)XPmPower_GetById(PM_POWER_LPD);
if (NULL == PsLpd) {
goto done;
}
/* Trigger Bisr */
PmRmw32(PsLpd->LpdSlcrBaseAddr + LPD_SLCR_BISR_CACHE_CTRL_1_OFFSET,
(LPD_SLCR_CACHE_CTRL_1_PGEN0_MASK | LPD_SLCR_CACHE_CTRL_1_PGEN1_MASK),
(LPD_SLCR_CACHE_CTRL_1_PGEN0_MASK | LPD_SLCR_CACHE_CTRL_1_PGEN1_MASK));
PmRmw32(PsLpd->LpdSlcrBaseAddr + LPD_SLCR_BISR_CACHE_CTRL_0_OFFSET,
LPD_SLCR_CACHE_CTRL_0_BISR_TRIGGER_MASK,
LPD_SLCR_CACHE_CTRL_0_BISR_TRIGGER_MASK);
/* Wait for Bisr to finish */
Status = XPm_PollForMask(PsLpd->LpdSlcrBaseAddr + LPD_SLCR_BISR_CACHE_STATUS_OFFSET,
(LPD_SLCR_BISR_DONE_GLOBAL_MASK |
LPD_SLCR_BISR_DONE_1_MASK |
LPD_SLCR_BISR_DONE_0_MASK),
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Check Bisr Status */
PmIn32(PsLpd->LpdSlcrBaseAddr + LPD_SLCR_BISR_CACHE_STATUS_OFFSET, RegValue);
if ((RegValue & (LPD_SLCR_BISR_PASS_GLOBAL_MASK |
LPD_SLCR_BISR_PASS_1_MASK |
LPD_SLCR_BISR_PASS_0_MASK)) !=
(LPD_SLCR_BISR_PASS_GLOBAL_MASK |
LPD_SLCR_BISR_PASS_1_MASK |
LPD_SLCR_BISR_PASS_0_MASK)) {
Status = XST_FAILURE;
}
/* Unwrite Trigger Bits */
PmRmw32(PsLpd->LpdSlcrBaseAddr + LPD_SLCR_BISR_CACHE_CTRL_1_OFFSET,
(LPD_SLCR_CACHE_CTRL_1_PGEN0_MASK |
LPD_SLCR_CACHE_CTRL_1_PGEN1_MASK), 0);
done:
return Status;
}
static XStatus XPmBisr_RepairFpd(u32 EfuseTagAddr, u32 TagSize, u32 *TagDataAddr)
{
XStatus Status = XST_FAILURE;
XPm_PsFpDomain *PsFpd;
u32 RegValue;
u64 BisrDataDestAddr;
PsFpd = (XPm_PsFpDomain *)XPmPower_GetById(PM_POWER_FPD);
if (NULL == PsFpd) {
goto done;
}
BisrDataDestAddr = PsFpd->FpdSlcrBaseAddr + (u64)FPD_SLCR_BISR_CACHE_DATA_0_OFFSET;
/* Copy repair data */
*TagDataAddr = XPmBisr_CopyStandard(EfuseTagAddr, TagSize, BisrDataDestAddr);
/* Trigger Bisr */
PmRmw32(PsFpd->FpdSlcrBaseAddr + FPD_SLCR_BISR_CACHE_CTRL_1_OFFSET,
(FPD_SLCR_CACHE_CTRL_1_PGEN0_MASK |
FPD_SLCR_CACHE_CTRL_1_PGEN1_MASK |
FPD_SLCR_CACHE_CTRL_1_PGEN2_MASK |
FPD_SLCR_CACHE_CTRL_1_PGEN3_MASK),
(FPD_SLCR_CACHE_CTRL_1_PGEN0_MASK |
FPD_SLCR_CACHE_CTRL_1_PGEN1_MASK |
FPD_SLCR_CACHE_CTRL_1_PGEN2_MASK |
FPD_SLCR_CACHE_CTRL_1_PGEN3_MASK));
PmRmw32(PsFpd->FpdSlcrBaseAddr + FPD_SLCR_BISR_CACHE_CTRL_0_OFFSET,
FPD_SLCR_CACHE_CTRL_0_BISR_TRIGGER_MASK,
FPD_SLCR_CACHE_CTRL_0_BISR_TRIGGER_MASK);
/* Wait for Bisr to finish */
Status = XPm_PollForMask(PsFpd->FpdSlcrBaseAddr + FPD_SLCR_BISR_CACHE_STATUS_OFFSET,
(FPD_SLCR_BISR_DONE_GLOBAL_MASK |
FPD_SLCR_BISR_DONE_3_MASK |
FPD_SLCR_BISR_DONE_2_MASK |
FPD_SLCR_BISR_DONE_1_MASK |
FPD_SLCR_BISR_DONE_0_MASK),
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Check Bisr Status */
PmIn32(PsFpd->FpdSlcrBaseAddr + FPD_SLCR_BISR_CACHE_STATUS_OFFSET, RegValue);
if ((RegValue & (FPD_SLCR_BISR_PASS_GLOBAL_MASK |
FPD_SLCR_BISR_PASS_3_MASK |
FPD_SLCR_BISR_PASS_2_MASK |
FPD_SLCR_BISR_PASS_1_MASK |
FPD_SLCR_BISR_PASS_0_MASK)) !=
(FPD_SLCR_BISR_PASS_GLOBAL_MASK |
FPD_SLCR_BISR_PASS_3_MASK |
FPD_SLCR_BISR_PASS_2_MASK |
FPD_SLCR_BISR_PASS_1_MASK |
FPD_SLCR_BISR_PASS_0_MASK)) {
Status = XST_FAILURE;
goto done;
}
/* Unwrite Trigger Bits */
PmRmw32(PsFpd->FpdSlcrBaseAddr + FPD_SLCR_BISR_CACHE_CTRL_1_OFFSET,
(FPD_SLCR_CACHE_CTRL_1_PGEN0_MASK |
FPD_SLCR_CACHE_CTRL_1_PGEN1_MASK |
FPD_SLCR_CACHE_CTRL_1_PGEN2_MASK |
FPD_SLCR_CACHE_CTRL_1_PGEN3_MASK), 0);
done:
return Status;
}
static XStatus XPmBisr_RepairCpm(u32 EfuseTagAddr, u32 TagSize, u32 *TagDataAddr)
{
XStatus Status = XST_FAILURE;
XPm_CpmDomain *Cpm;
u32 RegValue;
u64 BisrDataDestAddr;
Cpm = (XPm_CpmDomain *)XPmPower_GetById(PM_POWER_CPM);
if (NULL == Cpm) {
goto done;
}
BisrDataDestAddr = Cpm->CpmSlcrBaseAddr + (u64)CPM_SLCR_BISR_CACHE_DATA_0_OFFSET;
/* Copy repair data */
*TagDataAddr = XPmBisr_CopyStandard(EfuseTagAddr, TagSize, BisrDataDestAddr);
/* Clear BISR data test registers */
PmOut32(Cpm->CpmSlcrBaseAddr + CPM_SLCR_BISR_CACHE_CTRL_OFFSET,
CPM_SLCR_BISR_CACHE_CTRL_CLR_MASK);
PmOut32(Cpm->CpmSlcrBaseAddr + CPM_SLCR_BISR_CACHE_CTRL_OFFSET, 0x0);
/* Trigger Bisr */
PmRmw32(Cpm->CpmSlcrBaseAddr + CPM_SLCR_BISR_CACHE_CTRL_OFFSET,
CPM_SLCR_BISR_CACHE_CTRL_TRIGGER_MASK,
CPM_SLCR_BISR_CACHE_CTRL_TRIGGER_MASK);
/* Wait for Bisr to finish */
Status = XPm_PollForMask(Cpm->CpmSlcrBaseAddr + CPM_SLCR_BISR_CACHE_STATUS_OFFSET,
CPM_SLCR_BISR_CACHE_STATUS_DONE_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Check Bisr status */
PmIn32(Cpm->CpmSlcrBaseAddr + CPM_SLCR_BISR_CACHE_STATUS_OFFSET, RegValue);
if ((RegValue & CPM_SLCR_BISR_CACHE_STATUS_PASS_MASK) != CPM_SLCR_BISR_CACHE_STATUS_PASS_MASK) {
Status = XST_FAILURE;
goto done;
}
PmOut32(Cpm->CpmSlcrBaseAddr + CPM_SLCR_BISR_CACHE_CTRL_OFFSET, 0x0);
done:
return Status;
}
static XStatus XPmBisr_RepairCpm5(u32 EfuseTagAddr, u32 TagSize, u32 *TagDataAddr)
{
XStatus Status = XPM_ERR_BISR;
XPm_CpmDomain *Cpm;
u32 RegValue;
u64 BisrDataDestAddr;
Cpm = (XPm_CpmDomain *)XPmPower_GetById(PM_POWER_CPM5);
if (NULL == Cpm) {
goto done;
}
BisrDataDestAddr = Cpm->CpmSlcrBaseAddr + (u64)CPM5_SLCR_BISR_CACHE_DATA_0_OFFSET;
/* Disable write protection */
PmOut32(Cpm->CpmSlcrBaseAddr + CPM5_SLCR_WPROTP_OFFSET, 0x0);
/* Copy repair data */
*TagDataAddr = XPmBisr_CopyStandard(EfuseTagAddr, TagSize, BisrDataDestAddr);
/* Clear BISR data test registers */
PmOut32(Cpm->CpmSlcrBaseAddr + CPM5_SLCR_BISR_CACHE_CTRL_OFFSET,
CPM5_SLCR_BISR_CACHE_CTRL_CLR_MASK);
PmOut32(Cpm->CpmSlcrBaseAddr + CPM5_SLCR_BISR_CACHE_CTRL_OFFSET, 0x0);
/* Trigger Bisr */
PmRmw32(Cpm->CpmSlcrBaseAddr + CPM5_SLCR_BISR_CACHE_CTRL_OFFSET,
CPM5_SLCR_BISR_CACHE_CTRL_TRIGGER_MASK,
CPM5_SLCR_BISR_CACHE_CTRL_TRIGGER_MASK);
/* Wait for Bisr to finish */
Status = XPm_PollForMask(Cpm->CpmSlcrBaseAddr + CPM5_SLCR_BISR_CACHE_STATUS_OFFSET,
CPM5_SLCR_BISR_CACHE_STATUS_DONE_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Check Bisr status */
PmIn32(Cpm->CpmSlcrBaseAddr + CPM5_SLCR_BISR_CACHE_STATUS_OFFSET, RegValue);
if ((RegValue & CPM5_SLCR_BISR_CACHE_STATUS_PASS_MASK) !=
CPM5_SLCR_BISR_CACHE_STATUS_PASS_MASK) {
Status = XST_FAILURE;
goto done;
}
/* Unwrite trigger bit */
PmOut32(Cpm->CpmSlcrBaseAddr + CPM5_SLCR_BISR_CACHE_CTRL_OFFSET, 0x0);
/* Enable write protection */
PmOut32(Cpm->CpmSlcrBaseAddr + CPM5_SLCR_WPROTP_OFFSET, 0x1);
done:
return Status;
}
static XStatus XPmBisr_RepairDdrMc(u32 EfuseTagAddr, u32 TagSize, u32 TagOptional, u32 *TagDataAddr)
{
XStatus Status = XST_FAILURE;
u32 RegValue;
u32 BaseAddr, BisrDataDestAddr;
XPm_NpDomain *NpDomain = (XPm_NpDomain *)XPmPower_GetById(PM_POWER_NOC);
if (NULL == NpDomain) {
goto done;
}
BaseAddr = NPI_FIXED_BASEADDR | (TagOptional<<NPI_EFUSE_ENDPOINT_SHIFT);
BisrDataDestAddr = BaseAddr | DDRMC_NPI_CACHE_DATA_REGISTER_OFFSET;
if (0U == NpDomain->BisrDataCopied) {
/* Copy repair data */
*TagDataAddr = XPmBisr_CopyStandard(EfuseTagAddr, TagSize,
BisrDataDestAddr);
NpDomain->BisrDataCopied = 1;
}
/* Unlock PCSR */
PmOut32(BaseAddr | DDRMC_NPI_PCSR_LOCK_REGISTER_OFFSET, PCSR_UNLOCK_VAL);
/* Enable Bisr clock */
PmRmw32(BaseAddr | DDRMC_NPI_CLK_GATE_REGISTER_OFFSET, DDRMC_NPI_CLK_GATE_BISREN_MASK, DDRMC_NPI_CLK_GATE_BISREN_MASK);
/*Trigger Bisr */
PmOut32(BaseAddr | DDRMC_NPI_PCSR_MASK_REGISTER_OFFSET, DDRMC_NPI_PCSR_BISR_TRIGGER_MASK);
PmOut32(BaseAddr | DDRMC_NPI_PCSR_CONTROL_REGISTER_OFFSET, DDRMC_NPI_PCSR_BISR_TRIGGER_MASK);
/* Wait for Bisr to be done and check status */
Status = XPm_PollForMask(BaseAddr | DDRMC_NPI_CACHE_STATUS_REGISTER_OFFSET,
DDRMC_NPI_CACHE_STATUS_BISR_DONE_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
PmIn32(BaseAddr | DDRMC_NPI_CACHE_STATUS_REGISTER_OFFSET, RegValue);
if ((RegValue & DDRMC_NPI_CACHE_STATUS_BISR_PASS_MASK) != DDRMC_NPI_CACHE_STATUS_BISR_PASS_MASK) {
Status = XST_FAILURE;
goto done;
}
/* Disable Bisr Clock */
PmRmw32(BaseAddr | DDRMC_NPI_CLK_GATE_REGISTER_OFFSET, DDRMC_NPI_CLK_GATE_BISREN_MASK, ~DDRMC_NPI_CLK_GATE_BISREN_MASK);
/* Unwrite Trigger Bit */
PmOut32(BaseAddr | DDRMC_NPI_PCSR_MASK_REGISTER_OFFSET, DDRMC_NPI_PCSR_BISR_TRIGGER_MASK);
PmOut32(BaseAddr | DDRMC_NPI_PCSR_CONTROL_REGISTER_OFFSET, 0);
/* Lock PCSR */
PmOut32(BaseAddr | DDRMC_NPI_PCSR_LOCK_REGISTER_OFFSET, 1);
done:
return Status;
}
static XStatus XPmBisr_RepairME(u32 EfuseTagAddr, u32 TagId,u32 TagSize,u32 TagOptional, u32 *TagDataAddr)
{
XStatus Status = XST_FAILURE;
u32 RegValue;
u32 BaseAddr, BisrDataDestAddr;
/* Compilation warning fix */
(void)TagId;
BaseAddr = (u32)VIVADO_ME_BASEADDR | (TagOptional << ME_BISR_EFUSE_OFFSET_SHIFT);
BisrDataDestAddr = BaseAddr | ME_BISR_FIXED_OFFSET;
/* Copy repair data */
*TagDataAddr = XPmBisr_CopyStandard(EfuseTagAddr, TagSize, BisrDataDestAddr);
/* Trigger Bisr */
PmRmw32(BaseAddr | ME_BISR_CACHE_CTRL_OFFSET, ME_BISR_CACHE_CTRL_BISR_TRIGGER_MASK, ME_BISR_CACHE_CTRL_BISR_TRIGGER_MASK);
/* Wait for Bisr to finish */
Status = XPm_PollForMask(BaseAddr | ME_BISR_CACHE_STATUS_OFFSET,
ME_BISR_CACHE_STATUS_BISR_DONE_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Check Bisr Status */
PmIn32(BaseAddr | ME_BISR_CACHE_STATUS_OFFSET, RegValue);
if ((RegValue & ME_BISR_CACHE_STATUS_BISR_PASS_MASK) !=
ME_BISR_CACHE_STATUS_BISR_PASS_MASK) {
Status = XST_FAILURE;
goto done;
}
/* Unwrite Trigger Bit */
PmRmw32(BaseAddr | ME_BISR_CACHE_CTRL_OFFSET, ME_BISR_CACHE_CTRL_BISR_TRIGGER_MASK, 0);
done:
return Status;
}
static u32 XPmBisr_RepairBram(u32 EfuseTagAddr, u32 TagSize)
{
XPm_PlDomain *Pld;
u32 TagRow = 0;
u32 TagData;
u32 TagDataAddr;
u32 CframeRowAddr;
u32 BramRepairRow;
u32 BramRepairCol;
u32 BramRepairIndex;
u32 BramRepairVal;
u32 BramExtendedRepair[4];
u32 BramRepairWord;
XPm_Device *EfuseCache = XPmDevice_GetById(PM_DEV_EFUSE_CACHE);
TagDataAddr = EfuseTagAddr + 4U;
Pld = (XPm_PlDomain *)XPmPower_GetById(PM_POWER_PLD);
if (NULL == Pld) {
/* Return negative address, caller can identify error */
TagDataAddr = ~0U;
goto done;
}
if (NULL == EfuseCache) {
/* Return negative address so error can be identified by caller */
TagDataAddr = ~0U;
goto done;
}
while (TagRow < TagSize) {
if (TagDataAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET) ||
TagDataAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET)) {
TagDataAddr += 4U;
}
TagData = XPm_In32(TagDataAddr);
TagRow++;
TagDataAddr += 4U;
//break down TAG into components:
BramRepairRow = (TagData & CFRM_BRAM_REPAIR_ROW_MASK) >> CFRM_BRAM_REPAIR_ROW_SHIFT;
BramRepairCol = (TagData & CFRM_BRAM_REPAIR_COL_MASK) >> CFRM_BRAM_REPAIR_COL_SHIFT;
BramRepairIndex = (TagData & CFRM_BRAM_REPAIR_INDEX_MASK) >> CFRM_BRAM_REPAIR_INDEX_SHIFT;
BramRepairVal = (TagData & CFRM_BRAM_REPAIR_VAL_MASK) >> CFRM_BRAM_REPAIR_VAL_SHIFT;
//Build address for cfrm registers based on the "row"
//CFRM0_REG=0xF12D0000, CFRM1_REG=0xF12D2000, ...
CframeRowAddr = Pld->Cframe0RegBaseAddr + (0x2000U * BramRepairRow);
//construct expanded vector
//[31:0] init to 0
//[4:0] set repair value
//[63:32] init to 0
//[95:64] init to 0
//[70:64] set pair index
//[78:71] set column
//[81:79] set block type to BRAM
//[127:96] init to 0
BramExtendedRepair[0] = 0;
BramExtendedRepair[0] |= (BramRepairVal<<CFRM_BRAM_EXP_REPAIR_VAL_SHIFT);
BramExtendedRepair[1] = 0;
BramExtendedRepair[2] = 0;
BramExtendedRepair[2] |= (BramRepairIndex<<CFRM_BRAM_EXP_REPAIR_INDEX_SHIFT);
BramExtendedRepair[2] |= (BramRepairCol<<CFRM_BRAM_EXP_REPAIR_COL_SHIFT) ;
BramExtendedRepair[2] |= (CFRM_BRAM_EXP_REPAIR_BLK_TYPE_BRAM<<CFRM_BRAM_EXP_REPAIR_BLK_TYPE_SHIFT);
BramExtendedRepair[3] = 0;
//write to CFRM Reg
//address to start at = CFRM_REG + word count
for (BramRepairWord = 0; BramRepairWord < 4U; BramRepairWord++) {
XPm_Out32((CframeRowAddr + 0x250U)+(BramRepairWord<<2), BramExtendedRepair[BramRepairWord]);
}
//Trigger repair command
XPm_Out32((CframeRowAddr + 0x60U), 0xD);
XPm_Out32((CframeRowAddr + 0x64U), 0x0);
XPm_Out32((CframeRowAddr + 0x68U), 0x0);
XPm_Out32((CframeRowAddr + 0x6CU), 0x0);
}
done:
return TagDataAddr;
}
static u32 XPmBisr_RepairUram(u32 EfuseTagAddr, u32 TagSize)
{
XPm_PlDomain *Pld;
u32 TagRow = 0;
u32 TagData;
u32 TagDataAddr;
u32 CframeRowAddr;
u32 UramRepairRow;
u32 UramRepairCol;
u32 UramRepairIndex;
u32 UramRepairVal;
u32 UramExtendedRepair[4];
u32 UramRepairWord;
XPm_Device *EfuseCache = XPmDevice_GetById(PM_DEV_EFUSE_CACHE);
TagDataAddr = EfuseTagAddr + 4U;
Pld = (XPm_PlDomain *)XPmPower_GetById(PM_POWER_PLD);
if (NULL == Pld) {
/* Return negative address, caller can identify error */
TagDataAddr = ~0U;
goto done;
}
if (NULL == EfuseCache) {
/* Return negative address so error can be identified by caller */
TagDataAddr = ~0U;
goto done;
}
while (TagRow < TagSize) {
if (TagDataAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET) ||
TagDataAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET)) {
TagDataAddr += 4U;
}
TagData = XPm_In32(TagDataAddr);
TagRow++;
TagDataAddr += 4U;
//break down TAG into components:
UramRepairRow = (TagData & CFRM_URAM_REPAIR_ROW_MASK) >> CFRM_URAM_REPAIR_ROW_SHIFT;
UramRepairCol = (TagData & CFRM_URAM_REPAIR_COL_MASK) >> CFRM_URAM_REPAIR_COL_SHIFT;
UramRepairIndex = (TagData & CFRM_URAM_EXP_REPAIR_INDEX_MASK) >> CFRM_URAM_REPAIR_INDEX_SHIFT;
UramRepairVal = (TagData & CFRM_URAM_REPAIR_VAL_MASK) >> CFRM_URAM_REPAIR_VAL_SHIFT;
//Build address for cfrm registers based on the "row"
//CFRM0_REG=0xF12D0000, CFRM1_REG=0xF12D2000, ...
CframeRowAddr = Pld->Cframe0RegBaseAddr + (0x2000U * UramRepairRow);
//construct expanded vector: BRAM Bottom
//[31:0] init to 0
//[5:0] set repair value
//[63:32] init to 0
//[95:64] init to 0
//[70:64] set pair index
//[76:71] set column
//[81:79] set block type to BRAM
//[127:96] init to 0
UramExtendedRepair[0] = 0;
UramExtendedRepair[0] |= (UramRepairVal<<CFRM_URAM_EXP_REPAIR_VAL_SHIFT);
UramExtendedRepair[1] = 0;
UramExtendedRepair[2] = 0;
UramExtendedRepair[2] |= (UramRepairIndex<<CFRM_URAM_EXP_REPAIR_INDEX_SHIFT);
UramExtendedRepair[2] |= (UramRepairCol<<CFRM_URAM_EXP_REPAIR_COL_SHIFT) ;
UramExtendedRepair[2] |= (CFRM_URAM_EXP_REPAIR_BLK_TYPE_URAM<<CFRM_URAM_EXP_REPAIR_BLK_TYPE_SHIFT);
UramExtendedRepair[3] = 0;
//write Bottom to CFRM
//address to start at = CFRM_REG + word count
for (UramRepairWord = 0; UramRepairWord < 4U; UramRepairWord++) {
XPm_Out32((CframeRowAddr + 0x250U)+(UramRepairWord<<2),UramExtendedRepair[UramRepairWord]);
}
//Trigger repair command
XPm_Out32((CframeRowAddr + 0x60U), 0xD);
XPm_Out32((CframeRowAddr + 0x64U), 0x0);
XPm_Out32((CframeRowAddr + 0x68U), 0x0);
XPm_Out32((CframeRowAddr + 0x6CU), 0x0);
}
done:
return TagDataAddr;
}
static u32 XPmBisr_RepairHardBlock(u32 EfuseTagAddr, u32 TagSize)
{
XPm_PlDomain *Pld;
u32 TagPairCnt;
u32 TagPair[2] = {0};
u32 NumPairs;
u32 TagDataAddr;
u32 CframeRowAddr;
u32 HbRepairQTile;
u32 HbRepairCol;
u32 HbRepairRow;
u32 HbRepairVal[2];
u32 HbExtendedRepair[4];
u32 HbRepairWord;
TagDataAddr = EfuseTagAddr + 4U;
XPm_Device *EfuseCache = XPmDevice_GetById(PM_DEV_EFUSE_CACHE);
if (NULL == EfuseCache) {
/* Return negative address so error can be identified by caller */
TagDataAddr = ~0U;
goto done;
}
//tag size must be multiple of 2
if ((TagSize % 2U) != 0U) {
XPmBisr_SwError(PMC_EFUSE_BISR_CFRM_HB_BAD_SIZE);
TagDataAddr += (TagSize << 2);
if ((EfuseTagAddr < (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET) &&
TagDataAddr > (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET)) ||
(EfuseTagAddr < (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET) &&
TagDataAddr > (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET))) {
TagDataAddr += 4U;
}
return TagDataAddr;
}
Pld = (XPm_PlDomain *)XPmPower_GetById(PM_POWER_PLD);
if (NULL == Pld) {
/* Return negative address so error can be identified by caller */
TagDataAddr = ~0U;
goto done;
}
TagPairCnt = 0;
NumPairs = TagSize/2U;
while (TagPairCnt < NumPairs) {
//get first half (row,column,qtile,value)
if (TagDataAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET) ||
TagDataAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET)) {
TagDataAddr += 4U;
}
TagPair[0] = XPm_In32(TagDataAddr);
TagDataAddr += 4U;
//get second half (value)
if (TagDataAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET) ||
TagDataAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET)) {
TagDataAddr += 4U;
}
TagPair[1] = XPm_In32(TagDataAddr);
TagDataAddr += 4U;
TagPairCnt++;
//break down the components
HbRepairRow = (TagPair[0] & CFRM_HB_REPAIR_ROW_MASK) >> CFRM_HB_REPAIR_ROW_SHIFT;
HbRepairCol = (TagPair[0] & CFRM_HB_REPAIR_COL_MASK) >> CFRM_HB_REPAIR_COL_SHIFT;
HbRepairQTile = (TagPair[0] & CFRM_HB_REPAIR_QTILE_MASK) >> CFRM_HB_REPAIR_QTILE_SHIFT;
HbRepairVal[0] = TagPair[1];
HbRepairVal[1] = TagPair[0] & CFRM_HB_REPAIR_VAL0_MASK;
//Build address for cfrm registers based on the "row"
//CFRM0_REG=0xF12D0000, CFRM1_REG=0xF12D2000, ...
CframeRowAddr = Pld->Cframe0RegBaseAddr + (0x2000U * HbRepairRow);
//construct expanded vector
// REPAIR_VALUE[31:0] = BISR Value[31:0] (align to LSB)
// REPAIR_VALUE[63:32] = BISR Value[52:32]
//[95:64] init to 0
// REPAIR_TILE[70:64] = Q-tile[4:0] (Align to LSB)
// REPAIR_COLUMN[78:71] = Column[1:0] (Align to LSB)
// REPAIR_BLK_TYPE[81:79]=3’b101 (FUSE Tag is Hard-ip, i.e. MRMAC, SDFEC etc)
//[127:96] init to 0
HbExtendedRepair[0] = HbRepairVal[0]; //[31:0 ] (from second row)
HbExtendedRepair[1] = HbRepairVal[1]; //[52:32] (from first row of efuse pair)
HbExtendedRepair[2] = 0;
HbExtendedRepair[2] |= (HbRepairQTile<<CFRM_HB_EXP_REPAIR_QTILE_SHIFT);
HbExtendedRepair[2] |= (HbRepairCol<<CFRM_HB_EXP_REPAIR_COL_SHIFT);
HbExtendedRepair[2] |= (CFRM_HB_EXP_REPAIR_BLK_TYPE<<CFRM_HB_EXP_REPAIR_BLK_TYPE_SHIFT);
HbExtendedRepair[3] = 0;
//write to CFRM Reg
//address to start at = CFRM_REG + word count
for (HbRepairWord=0; HbRepairWord < 4U; HbRepairWord++) {
XPm_Out32((CframeRowAddr + 0x250U)+(HbRepairWord<<2),HbExtendedRepair[HbRepairWord]);
}
//Trigger repair command
XPm_Out32((CframeRowAddr + 0x60U), 0xD);
XPm_Out32((CframeRowAddr + 0x64U), 0x0);
XPm_Out32((CframeRowAddr + 0x68U), 0x0);
XPm_Out32((CframeRowAddr + 0x6CU), 0x0);
}
done:
return TagDataAddr;
}
static XStatus XPmBisr_RepairXram(u32 EfuseTagAddr, u32 TagSize, u32 *TagDataAddr)
{
XStatus Status = XPM_ERR_BISR;
XPm_Device *Device = NULL;
u32 RegValue, BaseAddr;
u64 BisrDataDestAddr;
/* Not possible to reach here if Device doesn't exist hence no */
/* check for existence of Device */
Device = XPmDevice_GetByIndex((u32)XPM_NODEIDX_DEV_XRAM_0);
/* Calculate Destination address */
/* Dest. Addr = slcr_address + cache_data_offset */
BaseAddr = Device->Node.BaseAddress;
BisrDataDestAddr = BaseAddr + (u64)XRAM_SLCR_BISR_CACHE_DATA_0_OFFSET;
/* Write unlock code to PCSR_LOCK register */
PmOut32(BaseAddr + XRAM_SLCR_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
/* Clear the BISR Test Data */
PmOut32(BaseAddr + XRAM_SLCR_PCSR_MASK_OFFSET,
XRAM_SLCR_PCSR_BISR_CLR_MASK);
PmOut32(BaseAddr + XRAM_SLCR_PCSR_PCR_OFFSET,
XRAM_SLCR_PCSR_BISR_CLR_MASK);
/* Exit the BISR Test Data Clear Mode*/
PmOut32(BaseAddr + XRAM_SLCR_PCSR_PCR_OFFSET, 0x0);
PmOut32(BaseAddr + XRAM_SLCR_PCSR_MASK_OFFSET, 0x0);
/* Copy Data from EFUSE to BISR Cache of XRAM */
*TagDataAddr = XPmBisr_CopyStandard(EfuseTagAddr, TagSize, BisrDataDestAddr);
/* BISR Trigger */
PmOut32(BaseAddr + XRAM_SLCR_PCSR_MASK_OFFSET,
XRAM_SLCR_PCSR_BISR_TRIGGER_MASK);
PmOut32(BaseAddr + XRAM_SLCR_PCSR_PCR_OFFSET,
XRAM_SLCR_PCSR_BISR_TRIGGER_MASK);
/* Poll for BISR_DONE */
Status = XPm_PollForMask(BaseAddr + XRAM_SLCR_PCSR_PSR_OFFSET,
XRAM_SLCR_PCSR_PSR_BISR_DONE_MASK, XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
/* Check BISR Pass/Fail */
PmIn32(BaseAddr + XRAM_SLCR_PCSR_PSR_OFFSET, RegValue);
if (XRAM_SLCR_PCSR_PSR_BISR_PASS_MASK != (RegValue &
XRAM_SLCR_PCSR_PSR_BISR_PASS_MASK)) {
Status = XPM_ERR_BISR;
goto done;
}
/* Exit the memory repair operation */
PmOut32(BaseAddr + XRAM_SLCR_PCSR_PCR_OFFSET, 0x0);
PmOut32(BaseAddr + XRAM_SLCR_PCSR_MASK_OFFSET, 0x0);
/* Write unlock code to PCSR_LOCK register */
PmOut32(BaseAddr + XRAM_SLCR_PCSR_LOCK_OFFSET, 0x0);
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmBisr_Repair(u32 TagId)
{
XStatus Status = XST_FAILURE;
u32 EfuseRowTag;
u32 EfuseCurrAddr;
u32 EfuseNextAddr;
u32 ExitCodeSeen;
u32 EfuseBisrTagId;
u32 EfuseBisrSize;
u32 EfuseBisrOptional;
u32 TagType;
XPm_Device *EfuseCache = XPmDevice_GetById(PM_DEV_EFUSE_CACHE);
if (NULL == EfuseCache) {
goto done;
}
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
//set up the white list
XPmBisr_InitTagIdList();
//check requested ID is a valid ID
if (TagId > 255U) {
XPmBisr_SwError(PMC_EFUSE_BISR_UNKN_TAG_ID);
Status = XST_FAILURE;
goto done;
}
//Compare to the white list to check it is a supported TAG
if (TAG_ID_VALID_MASK == (XPmTagIdWhiteList[TagId] & TAG_ID_VALID_MASK)) {
TagType = XPmTagIdWhiteList[TagId] & TAG_ID_TYPE_MASK;
} else {
XPmBisr_SwError(PMC_EFUSE_BISR_INVLD_TAG_ID);
Status = XST_FAILURE;
goto done;
}
//Scan EFUSE looking for valid tags that match requested tag, exit on 0, skip row on all 1's
EfuseNextAddr = EfuseCache->Node.BaseAddress + EFUSE_CACHE_BISR_RSVD_0_OFFSET;
ExitCodeSeen = 0;
while (0U == ExitCodeSeen) {
//read efuse row
EfuseCurrAddr = EfuseNextAddr;
EfuseRowTag = XPm_In32(EfuseCurrAddr);
if (EfuseRowTag == PMC_EFUSE_BISR_EXIT_CODE) {
ExitCodeSeen = 1;
} else if(EfuseRowTag==PMC_EFUSE_BISR_SKIP_CODE) { //SKIP Code Found
EfuseNextAddr += 4U;//then increment address and try again
} else {//Within Valid range and not a skip
//grab fields from the tag
EfuseBisrTagId = (EfuseRowTag & PMC_EFUSE_BISR_TAG_ID_MASK)>>PMC_EFUSE_BISR_TAG_ID_SHIFT;
EfuseBisrSize = (EfuseRowTag & PMC_EFUSE_BISR_SIZE_MASK)>>PMC_EFUSE_BISR_SIZE_SHIFT;
EfuseBisrOptional = (EfuseRowTag & PMC_EFUSE_BISR_OPTIONAL_MASK)>>PMC_EFUSE_BISR_OPTIONAL_SHIFT;
if (XST_SUCCESS == XPmBisr_TagSupportCheck(EfuseBisrTagId)) {//check supported TAG_ID
if (EfuseBisrTagId == TagId) {//check if matched TAG_ID
switch(TagType) {
case TAG_ID_TYPE_ME:
Status = XPmBisr_RepairME(EfuseCurrAddr,EfuseBisrTagId,EfuseBisrSize,EfuseBisrOptional, &EfuseNextAddr);
break;
case TAG_ID_TYPE_LPD:
Status = XPmBisr_RepairLpd(EfuseCurrAddr, EfuseBisrSize, &EfuseNextAddr);
break;
case TAG_ID_TYPE_FPD:
Status = XPmBisr_RepairFpd(EfuseCurrAddr, EfuseBisrSize, &EfuseNextAddr);
break;
case TAG_ID_TYPE_CPM:
Status = XPmBisr_RepairCpm(EfuseCurrAddr, EfuseBisrSize, &EfuseNextAddr);
break;
case TAG_ID_TYPE_GTY:
case TAG_ID_TYPE_GTYP:
case TAG_ID_TYPE_GTM:
case TAG_ID_TYPE_CPM5_GTYP:
Status = XPmBisr_RepairGty(EfuseCurrAddr, EfuseBisrSize, EfuseBisrOptional, &EfuseNextAddr, TagType);
break;
case TAG_ID_TYPE_DDRMC:
Status = XPmBisr_RepairDdrMc(EfuseCurrAddr, EfuseBisrSize, EfuseBisrOptional, &EfuseNextAddr);
break;
case TAG_ID_TYPE_CFRM_BR: //BRAM repair function
EfuseNextAddr = XPmBisr_RepairBram(EfuseCurrAddr, EfuseBisrSize);
if (EfuseNextAddr != ~0U) {
Status = XST_SUCCESS;
}
break;
case TAG_ID_TYPE_CFRM_UR: //URAM Repair function
EfuseNextAddr = XPmBisr_RepairUram(EfuseCurrAddr, EfuseBisrSize);
if (EfuseNextAddr != ~0U) {
Status = XST_SUCCESS;
}
break;
case TAG_ID_TYPE_CFRM_HB: //HardBlock repair function
EfuseNextAddr = XPmBisr_RepairHardBlock(EfuseCurrAddr, EfuseBisrSize);
if (EfuseNextAddr != ~0U) {
Status = XST_SUCCESS;
}
break;
case TAG_ID_TYPE_CPM5:
Status = XPmBisr_RepairCpm5(EfuseCurrAddr, EfuseBisrSize, &EfuseNextAddr);
break;
case TAG_ID_TYPE_XRAM:
Status = XPmBisr_RepairXram(EfuseCurrAddr, EfuseBisrSize, &EfuseNextAddr);
break;
default: //block type not recognized, no function to handle it
XPmBisr_SwError(PMC_EFUSE_BISR_BAD_TAG_TYPE);
Status = XST_FAILURE;
break;
}
if (XST_SUCCESS != Status) {
goto done;
}
} else { //calculate the next efuse address if not matched ID
EfuseNextAddr = (EfuseCurrAddr + 4U);//move to first data address of this tag
EfuseNextAddr += (EfuseBisrSize << 2); //move down number of words from the tag size
//did we cross over tbit row in the data size space
if ((EfuseCurrAddr < (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET) &&
EfuseNextAddr > (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET)) ||
(EfuseCurrAddr < (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET) &&
EfuseNextAddr > (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET))) {
EfuseNextAddr += 4U;
}
}
} else { //Not supported
XPmBisr_SwError(PMC_EFUSE_BISR_UNSUPPORTED_ID);
Status = XST_FAILURE;
goto done;
}
}
if (EfuseNextAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET) ||
EfuseNextAddr == (EfuseCache->Node.BaseAddress + EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET)) {
EfuseNextAddr += 4U;
}
}
Status = XST_SUCCESS;
done:
return Status;
}
static void NidbEfuseGrpInit(XPm_NidbEfuseGrpInfo *EfuseGroup)
{
XPm_Device *EfuseCache = XPmDevice_GetById(PM_DEV_EFUSE_CACHE);
u32 BaseAddr = EfuseCache->Node.BaseAddress;
u32 RegVal;
/* Initialize 1st NIDB Group */
RegVal = XPm_In32(BaseAddr + EFUSE_CACHE_NIDB_0_OFFSET);
EfuseGroup[0].NpiOffset = (u8)((RegVal & EFUSE_CACHE_NIDB_0_NPI_OFFSET_0_MASK)
>> EFUSE_CACHE_NIDB_0_NPI_OFFSET_0_SHIFT);
EfuseGroup[0].NpiBase = (u16)((RegVal & EFUSE_CACHE_NIDB_0_NPI_BASE_0_MASK) >>
EFUSE_CACHE_NIDB_0_NPI_BASE_0_SHIFT);
EfuseGroup[0].RdnCntl = (u8)((RegVal & EFUSE_CACHE_NIDB_0_RDN_CNTRL_0_MASK) >>
EFUSE_CACHE_NIDB_0_RDN_CNTRL_0_SHIFT);
/* Initialize 2nd NIDB Group */
EfuseGroup[1].NpiOffset = (u8)((RegVal & EFUSE_CACHE_NIDB_0_NPI_OFFSET_1_MASK)
>> EFUSE_CACHE_NIDB_0_NPI_OFFSET_1_SHIFT);
EfuseGroup[1].NpiBase = (u16)((RegVal & EFUSE_CACHE_NIDB_0_NPI_BASE_1_MASK) >>
EFUSE_CACHE_NIDB_0_NPI_BASE_1_SHIFT);
RegVal = XPm_In32(BaseAddr + EFUSE_CACHE_NIDB_1_OFFSET);
EfuseGroup[1].RdnCntl = (u8)((RegVal & EFUSE_CACHE_NIDB_1_RDN_CNTRL_1_MASK) >>
EFUSE_CACHE_NIDB_1_RDN_CNTRL_1_SHIFT);
/* Initialize 3rd NIDB Group */
EfuseGroup[2].NpiOffset = (u8)((RegVal & EFUSE_CACHE_NIDB_1_NPI_OFFSET_2_MASK)
>> EFUSE_CACHE_NIDB_1_NPI_OFFSET_2_SHIFT);
EfuseGroup[2].NpiBase = (u16)((RegVal & EFUSE_CACHE_NIDB_1_NPI_BASE_2_MASK) >>
EFUSE_CACHE_NIDB_1_NPI_BASE_2_SHIFT);
EfuseGroup[2].RdnCntl = (u8)((RegVal & EFUSE_CACHE_NIDB_1_RDN_CNTL_2_MASK) >>
EFUSE_CACHE_NIDB_1_RDN_CNTL_2_SHIFT);
/* Initialize 4th NIDB Group */
/* Portion of NPI_BASE_3 is stored in NIDB_2 [8:3] and NIDB_1 [2:0] */
EfuseGroup[3].NpiOffset = (u8)((RegVal & EFUSE_CACHE_NIDB_1_NPI_OFFSET_3_MASK
>> EFUSE_CACHE_NIDB_1_NPI_OFFSET_3_SHIFT));
EfuseGroup[3].NpiBase = (u16)((RegVal & EFUSE_CACHE_NIDB_1_NPI_BASE_3_MASK) >>
EFUSE_CACHE_NIDB_1_NPI_BASE_3_SHIFT);
RegVal = XPm_In32(BaseAddr + EFUSE_CACHE_NIDB_2_OFFSET);
EfuseGroup[3].NpiBase |= (u16)((RegVal & EFUSE_CACHE_NIDB_2_NPI_BASE_3_MASK) <<
EFUSE_CACHE_NIDB_1_NPI_BASE_3_WIDTH);
EfuseGroup[3].RdnCntl = (u8)((RegVal & EFUSE_CACHE_NIDB_2_RDN_CNTL_3_MASK) >>
EFUSE_CACHE_NIDB_2_RDN_CNTL_3_SHIFT);
/* Initialize 5th Group*/
EfuseGroup[4].NpiOffset = (u8)((RegVal & EFUSE_CACHE_NIDB_2_NPI_OFFSET_4_MASK)
>> EFUSE_CACHE_NIDB_2_NPI_OFFSET_4_SHIFT);
EfuseGroup[4].NpiBase = (u16)((RegVal & EFUSE_CACHE_NIDB_2_NPI_BASE_4_MASK) >>
EFUSE_CACHE_NIDB_2_NPI_BASE_4_SHIFT);
EfuseGroup[4].RdnCntl = (u8)((RegVal & EFUSE_CACHE_NIDB_2_RDN_CNTRL_4_MASK) >>
EFUSE_CACHE_NIDB_2_RDN_CNTRL_4_SHIFT);
}
XStatus XPmBisr_NidbLaneRepair(void)
{
XStatus Status = XST_FAILURE;
u32 i;
u32 RepairAddr = 0x0;
u32 NocSwId = 0x0;
u32 SlvSkipAddr = 0x0;
u32 NidbAddr = 0x0;
struct XPm_NidbEfuseGrpInfo NidbEfuseGrpInfo[MAX_NIDB_EFUSE_GROUPS];
/* Check SLR TYPE */
if ( SlrType == SLR_TYPE_MONOLITHIC_DEV ||
SlrType == SLR_TYPE_INVALID) {
PmInfo("Not an SSIT Device\n\r");
Status = XST_SUCCESS;
goto done;
}
/* Calculates first NIDB Address */
NocSwId = XPm_In32(PMC_GLOBAL_BASEADDR + PMC_GLOBAL_SSIT_NOC_ID_OFFSET) &
PMC_GLOBAL_SSIT_NOC_ID_SWITCHID_MASK;
/* This is partial address of NoC */
SlvSkipAddr = ((NocSwId << 10) - NIDB_OFFSET_DIFF) >> 16U;
/* Initialize NIDB Group Info Array */
NidbEfuseGrpInit(NidbEfuseGrpInfo);
/* lane repair logic */
for(i=0; i<MAX_NIDB_EFUSE_GROUPS; ++i) {
if (0x0U == NidbEfuseGrpInfo[i].RdnCntl) {
continue;
}
/* Skip Lane Repair for left most NIDB for Slave SSIT */
if (SlrType != SLR_TYPE_SSIT_DEV_MASTER_SLR &&
NidbEfuseGrpInfo[i].NpiBase == SlvSkipAddr) {
continue;
}
/* Calculate Absolute Base Address */
NidbAddr = NidbEfuseGrpInfo[i].NpiBase;
NidbAddr = (NidbAddr << 16U) + NPI_ROOT_BASEADDR;
/* Unlock PCSR */
XPm_Out32(NidbAddr + NIDB_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
/* Unlock Lane Repair Registers */
XPm_Out32(NidbAddr + NIDB_LANE_REPAIR_UNLOCK_OFFSET,
NIDB_LANE_REPAIR_UNLOCK_VAL);
/* Calculate Repair Address */
RepairAddr = NidbAddr + NIDB_REPAIR_OFFSET +
(NidbEfuseGrpInfo[i].NpiOffset << 2);
/* Write Repair Data */
XPm_Out32(RepairAddr, NidbEfuseGrpInfo[i].RdnCntl);
}
for(i=0; i<MAX_NIDB_EFUSE_GROUPS; ++i) {
NidbAddr = NidbEfuseGrpInfo[i].NpiBase;
NidbAddr = (NidbAddr << 16U) + NPI_ROOT_BASEADDR;
/* Lock Lane Repair Registers */
XPm_Out32(NidbAddr + NIDB_LANE_REPAIR_UNLOCK_OFFSET, 0x1);
/* Lock PCSR Register */
XPm_Out32(NidbAddr + NIDB_PCSR_MASK_OFFSET,
NIDB_PCSR_MASK_ODISABLE_MASK);
XPm_Out32(NidbAddr + NIDB_PCSR_CONTROL_OFFSET, 0x0);
XPm_Out32(NidbAddr + NIDB_PCSR_LOCK_OFFSET, 0x0);
}
Status = XST_SUCCESS;
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pmu_iomodule.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _PMU_IOMODULE_H_
#define _PMU_IOMODULE_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* PMU_IOMODULE Base Address
*/
#define PMU_IOMODULE_BASEADDR ((u32)0XFFD40000U)
/**
* Register: PMU_IOMODULE_IRQ_MODE
*/
#define PMU_IOMODULE_IRQ_MODE ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X0000000CU) )
/**
* Register: PMU_IOMODULE_GPO0
*/
#define PMU_IOMODULE_GPO0 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000010U) )
#define PMU_IOMODULE_GPO0_MAGIC_WORD_1_SHIFT 24
#define PMU_IOMODULE_GPO0_MAGIC_WORD_1_WIDTH 8
#define PMU_IOMODULE_GPO0_MAGIC_WORD_1_MASK ((u32)0XFF000000U)
#define PMU_IOMODULE_GPO0_MAGIC_WORD_2_SHIFT 16
#define PMU_IOMODULE_GPO0_MAGIC_WORD_2_WIDTH 8
#define PMU_IOMODULE_GPO0_MAGIC_WORD_2_MASK ((u32)0X00FF0000U)
#define PMU_IOMODULE_GPO0_FT_INJECT_FAILURE_SHIFT 13
#define PMU_IOMODULE_GPO0_FT_INJECT_FAILURE_WIDTH 3
#define PMU_IOMODULE_GPO0_FT_INJECT_FAILURE_MASK ((u32)0X0000E000U)
#define PMU_IOMODULE_GPO0_DISABLE_RST_FTSM_SHIFT 12
#define PMU_IOMODULE_GPO0_DISABLE_RST_FTSM_WIDTH 1
#define PMU_IOMODULE_GPO0_DISABLE_RST_FTSM_MASK ((u32)0X00001000U)
#define PMU_IOMODULE_GPO0_RST_FTSM_SHIFT 11
#define PMU_IOMODULE_GPO0_RST_FTSM_WIDTH 1
#define PMU_IOMODULE_GPO0_RST_FTSM_MASK ((u32)0X00000800U)
#define PMU_IOMODULE_GPO0_CLR_FTSTS_SHIFT 10
#define PMU_IOMODULE_GPO0_CLR_FTSTS_WIDTH 1
#define PMU_IOMODULE_GPO0_CLR_FTSTS_MASK ((u32)0X00000400U)
#define PMU_IOMODULE_GPO0_RST_ON_SLEEP_SHIFT 9
#define PMU_IOMODULE_GPO0_RST_ON_SLEEP_WIDTH 1
#define PMU_IOMODULE_GPO0_RST_ON_SLEEP_MASK ((u32)0X00000200U)
#define PMU_IOMODULE_GPO0_DISABLE_TRACE_COMP_SHIFT 8
#define PMU_IOMODULE_GPO0_DISABLE_TRACE_COMP_WIDTH 1
#define PMU_IOMODULE_GPO0_DISABLE_TRACE_COMP_MASK ((u32)0X00000100U)
#define PMU_IOMODULE_GPO0_PIT3_PRESCALE_SHIFT 7
#define PMU_IOMODULE_GPO0_PIT3_PRESCALE_WIDTH 1
#define PMU_IOMODULE_GPO0_PIT3_PRESCALE_MASK ((u32)0X00000080U)
#define PMU_IOMODULE_GPO0_PIT2_PRESCALE_SHIFT 5
#define PMU_IOMODULE_GPO0_PIT2_PRESCALE_WIDTH 2
#define PMU_IOMODULE_GPO0_PIT2_PRESCALE_MASK ((u32)0X00000060U)
#define PMU_IOMODULE_GPO0_PIT1_PRESCALE_SHIFT 3
#define PMU_IOMODULE_GPO0_PIT1_PRESCALE_WIDTH 2
#define PMU_IOMODULE_GPO0_PIT1_PRESCALE_MASK ((u32)0X00000018U)
#define PMU_IOMODULE_GPO0_PIT0_PRESCALE_SHIFT 1
#define PMU_IOMODULE_GPO0_PIT0_PRESCALE_WIDTH 2
#define PMU_IOMODULE_GPO0_PIT0_PRESCALE_MASK ((u32)0X00000006U)
#define PMU_IOMODULE_GPO0_DEBUG_REMAP_SHIFT 0
#define PMU_IOMODULE_GPO0_DEBUG_REMAP_WIDTH 1
#define PMU_IOMODULE_GPO0_DEBUG_REMAP_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_GPO1
*/
#define PMU_IOMODULE_GPO1 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000014U) )
#define PMU_IOMODULE_GPO1_MIO_5_SHIFT 5
#define PMU_IOMODULE_GPO1_MIO_5_WIDTH 1
#define PMU_IOMODULE_GPO1_MIO_5_MASK ((u32)0X00000020U)
#define PMU_IOMODULE_GPO1_MIO_4_SHIFT 4
#define PMU_IOMODULE_GPO1_MIO_4_WIDTH 1
#define PMU_IOMODULE_GPO1_MIO_4_MASK ((u32)0X00000010U)
#define PMU_IOMODULE_GPO1_MIO_3_SHIFT 3
#define PMU_IOMODULE_GPO1_MIO_3_WIDTH 1
#define PMU_IOMODULE_GPO1_MIO_3_MASK ((u32)0X00000008U)
#define PMU_IOMODULE_GPO1_MIO_2_SHIFT 2
#define PMU_IOMODULE_GPO1_MIO_2_WIDTH 1
#define PMU_IOMODULE_GPO1_MIO_2_MASK ((u32)0X00000004U)
#define PMU_IOMODULE_GPO1_MIO_1_SHIFT 1
#define PMU_IOMODULE_GPO1_MIO_1_WIDTH 1
#define PMU_IOMODULE_GPO1_MIO_1_MASK ((u32)0X00000002U)
#define PMU_IOMODULE_GPO1_MIO_0_SHIFT 0
#define PMU_IOMODULE_GPO1_MIO_0_WIDTH 1
#define PMU_IOMODULE_GPO1_MIO_0_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_GPO2
*/
#define PMU_IOMODULE_GPO2 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000018U) )
#define PMU_IOMODULE_GPO2_DAP_RPU_WAKE_ACK_SHIFT 9
#define PMU_IOMODULE_GPO2_DAP_RPU_WAKE_ACK_WIDTH 1
#define PMU_IOMODULE_GPO2_DAP_RPU_WAKE_ACK_MASK ((u32)0X00000200U)
#define PMU_IOMODULE_GPO2_DAP_FP_WAKE_ACK_SHIFT 8
#define PMU_IOMODULE_GPO2_DAP_FP_WAKE_ACK_WIDTH 1
#define PMU_IOMODULE_GPO2_DAP_FP_WAKE_ACK_MASK ((u32)0X00000100U)
#define PMU_IOMODULE_GPO2_PS_STATUS_SHIFT 7
#define PMU_IOMODULE_GPO2_PS_STATUS_WIDTH 1
#define PMU_IOMODULE_GPO2_PS_STATUS_MASK ((u32)0X00000080U)
/**
* Register: PMU_IOMODULE_GPO3
*/
#define PMU_IOMODULE_GPO3 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X0000001CU) )
#define PMU_IOMODULE_GPO3_PL_GPO_31_SHIFT 31
#define PMU_IOMODULE_GPO3_PL_GPO_31_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_31_MASK ((u32)0X80000000U)
#define PMU_IOMODULE_GPO3_PL_GPO_30_SHIFT 30
#define PMU_IOMODULE_GPO3_PL_GPO_30_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_30_MASK ((u32)0X40000000U)
#define PMU_IOMODULE_GPO3_PL_GPO_29_SHIFT 29
#define PMU_IOMODULE_GPO3_PL_GPO_29_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_29_MASK ((u32)0X20000000U)
#define PMU_IOMODULE_GPO3_PL_GPO_28_SHIFT 28
#define PMU_IOMODULE_GPO3_PL_GPO_28_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_28_MASK ((u32)0X10000000U)
#define PMU_IOMODULE_GPO3_PL_GPO_27_SHIFT 27
#define PMU_IOMODULE_GPO3_PL_GPO_27_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_27_MASK ((u32)0X08000000U)
#define PMU_IOMODULE_GPO3_PL_GPO_26_SHIFT 26
#define PMU_IOMODULE_GPO3_PL_GPO_26_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_26_MASK ((u32)0X04000000U)
#define PMU_IOMODULE_GPO3_PL_GPO_25_SHIFT 25
#define PMU_IOMODULE_GPO3_PL_GPO_25_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_25_MASK ((u32)0X02000000U)
#define PMU_IOMODULE_GPO3_PL_GPO_24_SHIFT 24
#define PMU_IOMODULE_GPO3_PL_GPO_24_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_24_MASK ((u32)0X01000000U)
#define PMU_IOMODULE_GPO3_PL_GPO_23_SHIFT 23
#define PMU_IOMODULE_GPO3_PL_GPO_23_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_23_MASK ((u32)0X00800000U)
#define PMU_IOMODULE_GPO3_PL_GPO_22_SHIFT 22
#define PMU_IOMODULE_GPO3_PL_GPO_22_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_22_MASK ((u32)0X00400000U)
#define PMU_IOMODULE_GPO3_PL_GPO_21_SHIFT 21
#define PMU_IOMODULE_GPO3_PL_GPO_21_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_21_MASK ((u32)0X00200000U)
#define PMU_IOMODULE_GPO3_PL_GPO_20_SHIFT 20
#define PMU_IOMODULE_GPO3_PL_GPO_20_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_20_MASK ((u32)0X00100000U)
#define PMU_IOMODULE_GPO3_PL_GPO_19_SHIFT 19
#define PMU_IOMODULE_GPO3_PL_GPO_19_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_19_MASK ((u32)0X00080000U)
#define PMU_IOMODULE_GPO3_PL_GPO_18_SHIFT 18
#define PMU_IOMODULE_GPO3_PL_GPO_18_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_18_MASK ((u32)0X00040000U)
#define PMU_IOMODULE_GPO3_PL_GPO_17_SHIFT 17
#define PMU_IOMODULE_GPO3_PL_GPO_17_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_17_MASK ((u32)0X00020000U)
#define PMU_IOMODULE_GPO3_PL_GPO_16_SHIFT 16
#define PMU_IOMODULE_GPO3_PL_GPO_16_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_16_MASK ((u32)0X00010000U)
#define PMU_IOMODULE_GPO3_PL_GPO_15_SHIFT 15
#define PMU_IOMODULE_GPO3_PL_GPO_15_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_15_MASK ((u32)0X00008000U)
#define PMU_IOMODULE_GPO3_PL_GPO_14_SHIFT 14
#define PMU_IOMODULE_GPO3_PL_GPO_14_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_14_MASK ((u32)0X00004000U)
#define PMU_IOMODULE_GPO3_PL_GPO_13_SHIFT 13
#define PMU_IOMODULE_GPO3_PL_GPO_13_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_13_MASK ((u32)0X00002000U)
#define PMU_IOMODULE_GPO3_PL_GPO_12_SHIFT 12
#define PMU_IOMODULE_GPO3_PL_GPO_12_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_12_MASK ((u32)0X00001000U)
#define PMU_IOMODULE_GPO3_PL_GPO_11_SHIFT 11
#define PMU_IOMODULE_GPO3_PL_GPO_11_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_11_MASK ((u32)0X00000800U)
#define PMU_IOMODULE_GPO3_PL_GPO_10_SHIFT 10
#define PMU_IOMODULE_GPO3_PL_GPO_10_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_10_MASK ((u32)0X00000400U)
#define PMU_IOMODULE_GPO3_PL_GPO_9_SHIFT 9
#define PMU_IOMODULE_GPO3_PL_GPO_9_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_9_MASK ((u32)0X00000200U)
#define PMU_IOMODULE_GPO3_PL_GPO_8_SHIFT 8
#define PMU_IOMODULE_GPO3_PL_GPO_8_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_8_MASK ((u32)0X00000100U)
#define PMU_IOMODULE_GPO3_PL_GPO_7_SHIFT 7
#define PMU_IOMODULE_GPO3_PL_GPO_7_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_7_MASK ((u32)0X00000080U)
#define PMU_IOMODULE_GPO3_PL_GPO_6_SHIFT 6
#define PMU_IOMODULE_GPO3_PL_GPO_6_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_6_MASK ((u32)0X00000040U)
#define PMU_IOMODULE_GPO3_PL_GPO_5_SHIFT 5
#define PMU_IOMODULE_GPO3_PL_GPO_5_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_5_MASK ((u32)0X00000020U)
#define PMU_IOMODULE_GPO3_PL_GPO_4_SHIFT 4
#define PMU_IOMODULE_GPO3_PL_GPO_4_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_4_MASK ((u32)0X00000010U)
#define PMU_IOMODULE_GPO3_PL_GPO_3_SHIFT 3
#define PMU_IOMODULE_GPO3_PL_GPO_3_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_3_MASK ((u32)0X00000008U)
#define PMU_IOMODULE_GPO3_PL_GPO_2_SHIFT 2
#define PMU_IOMODULE_GPO3_PL_GPO_2_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_2_MASK ((u32)0X00000004U)
#define PMU_IOMODULE_GPO3_PL_GPO_1_SHIFT 1
#define PMU_IOMODULE_GPO3_PL_GPO_1_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_1_MASK ((u32)0X00000002U)
#define PMU_IOMODULE_GPO3_PL_GPO_0_SHIFT 0
#define PMU_IOMODULE_GPO3_PL_GPO_0_WIDTH 1
#define PMU_IOMODULE_GPO3_PL_GPO_0_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_GPI0
*/
#define PMU_IOMODULE_GPI0 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000020U) )
#define PMU_IOMODULE_GPI0_RFT_ECC_FATAL_ERR_SHIFT 31
#define PMU_IOMODULE_GPI0_RFT_ECC_FATAL_ERR_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_ECC_FATAL_ERR_MASK ((u32)0X80000000U)
#define PMU_IOMODULE_GPI0_RFT_VOTER_ERR_SHIFT 30
#define PMU_IOMODULE_GPI0_RFT_VOTER_ERR_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_VOTER_ERR_MASK ((u32)0X40000000U)
#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_23_SHIFT 29
#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_23_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_23_MASK ((u32)0X20000000U)
#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_13_SHIFT 28
#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_13_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_13_MASK ((u32)0X10000000U)
#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_12_SHIFT 27
#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_12_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_12_MASK ((u32)0X08000000U)
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_B_SHIFT 26
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_B_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_B_MASK ((u32)0X04000000U)
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_B_SHIFT 25
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_B_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_B_MASK ((u32)0X02000000U)
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_B_SHIFT 24
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_B_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_B_MASK ((u32)0X01000000U)
#define PMU_IOMODULE_GPI0_RFT_MISMATCH_STATE_SHIFT 23
#define PMU_IOMODULE_GPI0_RFT_MISMATCH_STATE_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_MISMATCH_STATE_MASK ((u32)0X00800000U)
#define PMU_IOMODULE_GPI0_RFT_MISMATCH_CPU_SHIFT 22
#define PMU_IOMODULE_GPI0_RFT_MISMATCH_CPU_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_MISMATCH_CPU_MASK ((u32)0X00400000U)
#define PMU_IOMODULE_GPI0_RFT_SLEEP_RESET_SHIFT 19
#define PMU_IOMODULE_GPI0_RFT_SLEEP_RESET_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_SLEEP_RESET_MASK ((u32)0X00080000U)
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_A_SHIFT 18
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_A_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_A_MASK ((u32)0X00040000U)
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_A_SHIFT 17
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_A_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_A_MASK ((u32)0X00020000U)
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_A_SHIFT 16
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_A_WIDTH 1
#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_A_MASK ((u32)0X00010000U)
#define PMU_IOMODULE_GPI0_NFT_ECC_FATAL_ERR_SHIFT 15
#define PMU_IOMODULE_GPI0_NFT_ECC_FATAL_ERR_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_ECC_FATAL_ERR_MASK ((u32)0X00008000U)
#define PMU_IOMODULE_GPI0_NFT_VOTER_ERR_SHIFT 14
#define PMU_IOMODULE_GPI0_NFT_VOTER_ERR_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_VOTER_ERR_MASK ((u32)0X00004000U)
#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_23_SHIFT 13
#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_23_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_23_MASK ((u32)0X00002000U)
#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_13_SHIFT 12
#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_13_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_13_MASK ((u32)0X00001000U)
#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_12_SHIFT 11
#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_12_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_12_MASK ((u32)0X00000800U)
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_B_SHIFT 10
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_B_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_B_MASK ((u32)0X00000400U)
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_B_SHIFT 9
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_B_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_B_MASK ((u32)0X00000200U)
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_B_SHIFT 8
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_B_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_B_MASK ((u32)0X00000100U)
#define PMU_IOMODULE_GPI0_NFT_MISMATCH_STATE_SHIFT 7
#define PMU_IOMODULE_GPI0_NFT_MISMATCH_STATE_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_MISMATCH_STATE_MASK ((u32)0X00000080U)
#define PMU_IOMODULE_GPI0_NFT_MISMATCH_CPU_SHIFT 6
#define PMU_IOMODULE_GPI0_NFT_MISMATCH_CPU_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_MISMATCH_CPU_MASK ((u32)0X00000040U)
#define PMU_IOMODULE_GPI0_NFT_SLEEP_RESET_SHIFT 3
#define PMU_IOMODULE_GPI0_NFT_SLEEP_RESET_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_SLEEP_RESET_MASK ((u32)0X00000008U)
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_A_SHIFT 2
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_A_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_A_MASK ((u32)0X00000004U)
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_A_SHIFT 1
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_A_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_A_MASK ((u32)0X00000002U)
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_A_SHIFT 0
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_A_WIDTH 1
#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_A_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_GPI1
*/
#define PMU_IOMODULE_GPI1 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000024U) )
#define PMU_IOMODULE_GPI1_APB_AIB_ERROR_SHIFT 31
#define PMU_IOMODULE_GPI1_APB_AIB_ERROR_WIDTH 1
#define PMU_IOMODULE_GPI1_APB_AIB_ERROR_MASK ((u32)0X80000000U)
#define PMU_IOMODULE_GPI1_AXI_AIB_ERROR_SHIFT 30
#define PMU_IOMODULE_GPI1_AXI_AIB_ERROR_WIDTH 1
#define PMU_IOMODULE_GPI1_AXI_AIB_ERROR_MASK ((u32)0X40000000U)
#define PMU_IOMODULE_GPI1_ERROR_2_SHIFT 29
#define PMU_IOMODULE_GPI1_ERROR_2_WIDTH 1
#define PMU_IOMODULE_GPI1_ERROR_2_MASK ((u32)0X20000000U)
#define PMU_IOMODULE_GPI1_ERROR_1_SHIFT 28
#define PMU_IOMODULE_GPI1_ERROR_1_WIDTH 1
#define PMU_IOMODULE_GPI1_ERROR_1_MASK ((u32)0X10000000U)
#define PMU_IOMODULE_GPI1_ACPU_3_DBG_PWRUP_SHIFT 23
#define PMU_IOMODULE_GPI1_ACPU_3_DBG_PWRUP_WIDTH 1
#define PMU_IOMODULE_GPI1_ACPU_3_DBG_PWRUP_MASK ((u32)0X00800000U)
#define PMU_IOMODULE_GPI1_ACPU_2_DBG_PWRUP_SHIFT 22
#define PMU_IOMODULE_GPI1_ACPU_2_DBG_PWRUP_WIDTH 1
#define PMU_IOMODULE_GPI1_ACPU_2_DBG_PWRUP_MASK ((u32)0X00400000U)
#define PMU_IOMODULE_GPI1_ACPU_1_DBG_PWRUP_SHIFT 21
#define PMU_IOMODULE_GPI1_ACPU_1_DBG_PWRUP_WIDTH 1
#define PMU_IOMODULE_GPI1_ACPU_1_DBG_PWRUP_MASK ((u32)0X00200000U)
#define PMU_IOMODULE_GPI1_ACPU_0_DBG_PWRUP_SHIFT 20
#define PMU_IOMODULE_GPI1_ACPU_0_DBG_PWRUP_WIDTH 1
#define PMU_IOMODULE_GPI1_ACPU_0_DBG_PWRUP_MASK ((u32)0X00100000U)
#define PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_SHIFT 16
#define PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_WIDTH 1
#define PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_MASK ((u32)0X00010000U)
#define PMU_IOMODULE_GPI1_MIO_WAKE_5_SHIFT 15
#define PMU_IOMODULE_GPI1_MIO_WAKE_5_WIDTH 1
#define PMU_IOMODULE_GPI1_MIO_WAKE_5_MASK ((u32)0X00008000U)
#define PMU_IOMODULE_GPI1_MIO_WAKE_4_SHIFT 14
#define PMU_IOMODULE_GPI1_MIO_WAKE_4_WIDTH 1
#define PMU_IOMODULE_GPI1_MIO_WAKE_4_MASK ((u32)0X00004000U)
#define PMU_IOMODULE_GPI1_MIO_WAKE_3_SHIFT 13
#define PMU_IOMODULE_GPI1_MIO_WAKE_3_WIDTH 1
#define PMU_IOMODULE_GPI1_MIO_WAKE_3_MASK ((u32)0X00002000U)
#define PMU_IOMODULE_GPI1_MIO_WAKE_2_SHIFT 12
#define PMU_IOMODULE_GPI1_MIO_WAKE_2_WIDTH 1
#define PMU_IOMODULE_GPI1_MIO_WAKE_2_MASK ((u32)0X00001000U)
#define PMU_IOMODULE_GPI1_MIO_WAKE_1_SHIFT 11
#define PMU_IOMODULE_GPI1_MIO_WAKE_1_WIDTH 1
#define PMU_IOMODULE_GPI1_MIO_WAKE_1_MASK ((u32)0X00000800U)
#define PMU_IOMODULE_GPI1_MIO_WAKE_0_SHIFT 10
#define PMU_IOMODULE_GPI1_MIO_WAKE_0_WIDTH 1
#define PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK ((u32)0X00000400U)
#define PMU_IOMODULE_GPI1_DAP_RPU_WAKE_SHIFT 9
#define PMU_IOMODULE_GPI1_DAP_RPU_WAKE_WIDTH 1
#define PMU_IOMODULE_GPI1_DAP_RPU_WAKE_MASK ((u32)0X00000200U)
#define PMU_IOMODULE_GPI1_DAP_FPD_WAKE_SHIFT 8
#define PMU_IOMODULE_GPI1_DAP_FPD_WAKE_WIDTH 1
#define PMU_IOMODULE_GPI1_DAP_FPD_WAKE_MASK ((u32)0X00000100U)
#define PMU_IOMODULE_GPI1_USB_1_WAKE_SHIFT 7
#define PMU_IOMODULE_GPI1_USB_1_WAKE_WIDTH 1
#define PMU_IOMODULE_GPI1_USB_1_WAKE_MASK ((u32)0X00000080U)
#define PMU_IOMODULE_GPI1_USB_0_WAKE_SHIFT 6
#define PMU_IOMODULE_GPI1_USB_0_WAKE_WIDTH 1
#define PMU_IOMODULE_GPI1_USB_0_WAKE_MASK ((u32)0X00000040U)
#define PMU_IOMODULE_GPI1_R5_1_WAKE_SHIFT 5
#define PMU_IOMODULE_GPI1_R5_1_WAKE_WIDTH 1
#define PMU_IOMODULE_GPI1_R5_1_WAKE_MASK ((u32)0X00000020U)
#define PMU_IOMODULE_GPI1_R5_0_WAKE_SHIFT 4
#define PMU_IOMODULE_GPI1_R5_0_WAKE_WIDTH 1
#define PMU_IOMODULE_GPI1_R5_0_WAKE_MASK ((u32)0X00000010U)
#define PMU_IOMODULE_GPI1_ACPU_3_WAKE_SHIFT 3
#define PMU_IOMODULE_GPI1_ACPU_3_WAKE_WIDTH 1
#define PMU_IOMODULE_GPI1_ACPU_3_WAKE_MASK ((u32)0X00000008U)
#define PMU_IOMODULE_GPI1_ACPU_2_WAKE_SHIFT 2
#define PMU_IOMODULE_GPI1_ACPU_2_WAKE_WIDTH 1
#define PMU_IOMODULE_GPI1_ACPU_2_WAKE_MASK ((u32)0X00000004U)
#define PMU_IOMODULE_GPI1_ACPU_1_WAKE_SHIFT 1
#define PMU_IOMODULE_GPI1_ACPU_1_WAKE_WIDTH 1
#define PMU_IOMODULE_GPI1_ACPU_1_WAKE_MASK ((u32)0X00000002U)
#define PMU_IOMODULE_GPI1_ACPU_0_WAKE_SHIFT 0
#define PMU_IOMODULE_GPI1_ACPU_0_WAKE_WIDTH 1
#define PMU_IOMODULE_GPI1_ACPU_0_WAKE_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_GPI2
*/
#define PMU_IOMODULE_GPI2 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000028U) )
#define PMU_IOMODULE_GPI2_VCC_INT_FP_DISCONNECT_SHIFT 31
#define PMU_IOMODULE_GPI2_VCC_INT_FP_DISCONNECT_WIDTH 1
#define PMU_IOMODULE_GPI2_VCC_INT_FP_DISCONNECT_MASK ((u32)0X80000000U)
#define PMU_IOMODULE_GPI2_VCC_INT_DISCONNECT_SHIFT 30
#define PMU_IOMODULE_GPI2_VCC_INT_DISCONNECT_WIDTH 1
#define PMU_IOMODULE_GPI2_VCC_INT_DISCONNECT_MASK ((u32)0X40000000U)
#define PMU_IOMODULE_GPI2_VCC_AUX_DISCONNECT_SHIFT 29
#define PMU_IOMODULE_GPI2_VCC_AUX_DISCONNECT_WIDTH 1
#define PMU_IOMODULE_GPI2_VCC_AUX_DISCONNECT_MASK ((u32)0X20000000U)
#define PMU_IOMODULE_GPI2_DBG_ACPU3_RST_REQ_SHIFT 23
#define PMU_IOMODULE_GPI2_DBG_ACPU3_RST_REQ_WIDTH 1
#define PMU_IOMODULE_GPI2_DBG_ACPU3_RST_REQ_MASK ((u32)0X00800000U)
#define PMU_IOMODULE_GPI2_DBG_ACPU2_RST_REQ_SHIFT 22
#define PMU_IOMODULE_GPI2_DBG_ACPU2_RST_REQ_WIDTH 1
#define PMU_IOMODULE_GPI2_DBG_ACPU2_RST_REQ_MASK ((u32)0X00400000U)
#define PMU_IOMODULE_GPI2_DBG_ACPU1_RST_REQ_SHIFT 21
#define PMU_IOMODULE_GPI2_DBG_ACPU1_RST_REQ_WIDTH 1
#define PMU_IOMODULE_GPI2_DBG_ACPU1_RST_REQ_MASK ((u32)0X00200000U)
#define PMU_IOMODULE_GPI2_DBG_ACPU0_RST_REQ_SHIFT 20
#define PMU_IOMODULE_GPI2_DBG_ACPU0_RST_REQ_WIDTH 1
#define PMU_IOMODULE_GPI2_DBG_ACPU0_RST_REQ_MASK ((u32)0X00100000U)
#define PMU_IOMODULE_GPI2_CP_ACPU3_RST_REQ_SHIFT 19
#define PMU_IOMODULE_GPI2_CP_ACPU3_RST_REQ_WIDTH 1
#define PMU_IOMODULE_GPI2_CP_ACPU3_RST_REQ_MASK ((u32)0X00080000U)
#define PMU_IOMODULE_GPI2_CP_ACPU2_RST_REQ_SHIFT 18
#define PMU_IOMODULE_GPI2_CP_ACPU2_RST_REQ_WIDTH 1
#define PMU_IOMODULE_GPI2_CP_ACPU2_RST_REQ_MASK ((u32)0X00040000U)
#define PMU_IOMODULE_GPI2_CP_ACPU1_RST_REQ_SHIFT 17
#define PMU_IOMODULE_GPI2_CP_ACPU1_RST_REQ_WIDTH 1
#define PMU_IOMODULE_GPI2_CP_ACPU1_RST_REQ_MASK ((u32)0X00020000U)
#define PMU_IOMODULE_GPI2_CP_ACPU0_RST_REQ_SHIFT 16
#define PMU_IOMODULE_GPI2_CP_ACPU0_RST_REQ_WIDTH 1
#define PMU_IOMODULE_GPI2_CP_ACPU0_RST_REQ_MASK ((u32)0X00010000U)
#define PMU_IOMODULE_GPI2_DBG_RCPU1_RST_REQ_SHIFT 9
#define PMU_IOMODULE_GPI2_DBG_RCPU1_RST_REQ_WIDTH 1
#define PMU_IOMODULE_GPI2_DBG_RCPU1_RST_REQ_MASK ((u32)0X00000200U)
#define PMU_IOMODULE_GPI2_DBG_RCPU0_RST_REQ_SHIFT 8
#define PMU_IOMODULE_GPI2_DBG_RCPU0_RST_REQ_WIDTH 1
#define PMU_IOMODULE_GPI2_DBG_RCPU0_RST_REQ_MASK ((u32)0X00000100U)
#define PMU_IOMODULE_GPI2_R5_1_SLEEP_SHIFT 5
#define PMU_IOMODULE_GPI2_R5_1_SLEEP_WIDTH 1
#define PMU_IOMODULE_GPI2_R5_1_SLEEP_MASK ((u32)0X00000020U)
#define PMU_IOMODULE_GPI2_R5_0_SLEEP_SHIFT 4
#define PMU_IOMODULE_GPI2_R5_0_SLEEP_WIDTH 1
#define PMU_IOMODULE_GPI2_R5_0_SLEEP_MASK ((u32)0X00000010U)
#define PMU_IOMODULE_GPI2_ACPU_3_SLEEP_SHIFT 3
#define PMU_IOMODULE_GPI2_ACPU_3_SLEEP_WIDTH 1
#define PMU_IOMODULE_GPI2_ACPU_3_SLEEP_MASK ((u32)0X00000008U)
#define PMU_IOMODULE_GPI2_ACPU_2_SLEEP_SHIFT 2
#define PMU_IOMODULE_GPI2_ACPU_2_SLEEP_WIDTH 1
#define PMU_IOMODULE_GPI2_ACPU_2_SLEEP_MASK ((u32)0X00000004U)
#define PMU_IOMODULE_GPI2_ACPU_1_SLEEP_SHIFT 1
#define PMU_IOMODULE_GPI2_ACPU_1_SLEEP_WIDTH 1
#define PMU_IOMODULE_GPI2_ACPU_1_SLEEP_MASK ((u32)0X00000002U)
#define PMU_IOMODULE_GPI2_ACPU_0_SLEEP_SHIFT 0
#define PMU_IOMODULE_GPI2_ACPU_0_SLEEP_WIDTH 1
#define PMU_IOMODULE_GPI2_ACPU_0_SLEEP_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_GPI3
*/
#define PMU_IOMODULE_GPI3 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X0000002CU) )
#define PMU_IOMODULE_GPI3_PL_GPI_31_SHIFT 31
#define PMU_IOMODULE_GPI3_PL_GPI_31_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_31_MASK ((u32)0X80000000U)
#define PMU_IOMODULE_GPI3_PL_GPI_30_SHIFT 30
#define PMU_IOMODULE_GPI3_PL_GPI_30_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_30_MASK ((u32)0X40000000U)
#define PMU_IOMODULE_GPI3_PL_GPI_29_SHIFT 29
#define PMU_IOMODULE_GPI3_PL_GPI_29_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_29_MASK ((u32)0X20000000U)
#define PMU_IOMODULE_GPI3_PL_GPI_28_SHIFT 28
#define PMU_IOMODULE_GPI3_PL_GPI_28_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_28_MASK ((u32)0X10000000U)
#define PMU_IOMODULE_GPI3_PL_GPI_27_SHIFT 27
#define PMU_IOMODULE_GPI3_PL_GPI_27_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_27_MASK ((u32)0X08000000U)
#define PMU_IOMODULE_GPI3_PL_GPI_26_SHIFT 26
#define PMU_IOMODULE_GPI3_PL_GPI_26_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_26_MASK ((u32)0X04000000U)
#define PMU_IOMODULE_GPI3_PL_GPI_25_SHIFT 25
#define PMU_IOMODULE_GPI3_PL_GPI_25_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_25_MASK ((u32)0X02000000U)
#define PMU_IOMODULE_GPI3_PL_GPI_24_SHIFT 24
#define PMU_IOMODULE_GPI3_PL_GPI_24_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_24_MASK ((u32)0X01000000U)
#define PMU_IOMODULE_GPI3_PL_GPI_23_SHIFT 23
#define PMU_IOMODULE_GPI3_PL_GPI_23_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_23_MASK ((u32)0X00800000U)
#define PMU_IOMODULE_GPI3_PL_GPI_22_SHIFT 22
#define PMU_IOMODULE_GPI3_PL_GPI_22_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_22_MASK ((u32)0X00400000U)
#define PMU_IOMODULE_GPI3_PL_GPI_21_SHIFT 21
#define PMU_IOMODULE_GPI3_PL_GPI_21_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_21_MASK ((u32)0X00200000U)
#define PMU_IOMODULE_GPI3_PL_GPI_20_SHIFT 20
#define PMU_IOMODULE_GPI3_PL_GPI_20_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_20_MASK ((u32)0X00100000U)
#define PMU_IOMODULE_GPI3_PL_GPI_19_SHIFT 19
#define PMU_IOMODULE_GPI3_PL_GPI_19_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_19_MASK ((u32)0X00080000U)
#define PMU_IOMODULE_GPI3_PL_GPI_18_SHIFT 18
#define PMU_IOMODULE_GPI3_PL_GPI_18_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_18_MASK ((u32)0X00040000U)
#define PMU_IOMODULE_GPI3_PL_GPI_17_SHIFT 17
#define PMU_IOMODULE_GPI3_PL_GPI_17_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_17_MASK ((u32)0X00020000U)
#define PMU_IOMODULE_GPI3_PL_GPI_16_SHIFT 16
#define PMU_IOMODULE_GPI3_PL_GPI_16_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_16_MASK ((u32)0X00010000U)
#define PMU_IOMODULE_GPI3_PL_GPI_15_SHIFT 15
#define PMU_IOMODULE_GPI3_PL_GPI_15_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_15_MASK ((u32)0X00008000U)
#define PMU_IOMODULE_GPI3_PL_GPI_14_SHIFT 14
#define PMU_IOMODULE_GPI3_PL_GPI_14_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_14_MASK ((u32)0X00004000U)
#define PMU_IOMODULE_GPI3_PL_GPI_13_SHIFT 13
#define PMU_IOMODULE_GPI3_PL_GPI_13_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_13_MASK ((u32)0X00002000U)
#define PMU_IOMODULE_GPI3_PL_GPI_12_SHIFT 12
#define PMU_IOMODULE_GPI3_PL_GPI_12_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_12_MASK ((u32)0X00001000U)
#define PMU_IOMODULE_GPI3_PL_GPI_11_SHIFT 11
#define PMU_IOMODULE_GPI3_PL_GPI_11_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_11_MASK ((u32)0X00000800U)
#define PMU_IOMODULE_GPI3_PL_GPI_10_SHIFT 10
#define PMU_IOMODULE_GPI3_PL_GPI_10_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_10_MASK ((u32)0X00000400U)
#define PMU_IOMODULE_GPI3_PL_GPI_9_SHIFT 9
#define PMU_IOMODULE_GPI3_PL_GPI_9_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_9_MASK ((u32)0X00000200U)
#define PMU_IOMODULE_GPI3_PL_GPI_8_SHIFT 8
#define PMU_IOMODULE_GPI3_PL_GPI_8_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_8_MASK ((u32)0X00000100U)
#define PMU_IOMODULE_GPI3_PL_GPI_7_SHIFT 7
#define PMU_IOMODULE_GPI3_PL_GPI_7_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_7_MASK ((u32)0X00000080U)
#define PMU_IOMODULE_GPI3_PL_GPI_6_SHIFT 6
#define PMU_IOMODULE_GPI3_PL_GPI_6_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_6_MASK ((u32)0X00000040U)
#define PMU_IOMODULE_GPI3_PL_GPI_5_SHIFT 5
#define PMU_IOMODULE_GPI3_PL_GPI_5_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_5_MASK ((u32)0X00000020U)
#define PMU_IOMODULE_GPI3_PL_GPI_4_SHIFT 4
#define PMU_IOMODULE_GPI3_PL_GPI_4_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_4_MASK ((u32)0X00000010U)
#define PMU_IOMODULE_GPI3_PL_GPI_3_SHIFT 3
#define PMU_IOMODULE_GPI3_PL_GPI_3_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_3_MASK ((u32)0X00000008U)
#define PMU_IOMODULE_GPI3_PL_GPI_2_SHIFT 2
#define PMU_IOMODULE_GPI3_PL_GPI_2_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_2_MASK ((u32)0X00000004U)
#define PMU_IOMODULE_GPI3_PL_GPI_1_SHIFT 1
#define PMU_IOMODULE_GPI3_PL_GPI_1_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_1_MASK ((u32)0X00000002U)
#define PMU_IOMODULE_GPI3_PL_GPI_0_SHIFT 0
#define PMU_IOMODULE_GPI3_PL_GPI_0_WIDTH 1
#define PMU_IOMODULE_GPI3_PL_GPI_0_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_IRQ_STATUS
*/
#define PMU_IOMODULE_IRQ_STATUS ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000030U) )
#define PMU_IOMODULE_IRQ_STATUS_CSU_PMU_SEC_LOCK_SHIFT 31
#define PMU_IOMODULE_IRQ_STATUS_CSU_PMU_SEC_LOCK_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_CSU_PMU_SEC_LOCK_MASK ((u32)0X80000000U)
#define PMU_IOMODULE_IRQ_STATUS_INV_ADDR_SHIFT 29
#define PMU_IOMODULE_IRQ_STATUS_INV_ADDR_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_INV_ADDR_MASK ((u32)0X20000000U)
#define PMU_IOMODULE_IRQ_STATUS_PWR_DN_REQ_SHIFT 28
#define PMU_IOMODULE_IRQ_STATUS_PWR_DN_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_PWR_DN_REQ_MASK ((u32)0X10000000U)
#define PMU_IOMODULE_IRQ_STATUS_PWR_UP_REQ_SHIFT 27
#define PMU_IOMODULE_IRQ_STATUS_PWR_UP_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_PWR_UP_REQ_MASK ((u32)0X08000000U)
#define PMU_IOMODULE_IRQ_STATUS_SW_RST_REQ_SHIFT 26
#define PMU_IOMODULE_IRQ_STATUS_SW_RST_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_SW_RST_REQ_MASK ((u32)0X04000000U)
#define PMU_IOMODULE_IRQ_STATUS_HW_RST_REQ_SHIFT 25
#define PMU_IOMODULE_IRQ_STATUS_HW_RST_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_HW_RST_REQ_MASK ((u32)0X02000000U)
#define PMU_IOMODULE_IRQ_STATUS_ISO_REQ_SHIFT 24
#define PMU_IOMODULE_IRQ_STATUS_ISO_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_ISO_REQ_MASK ((u32)0X01000000U)
#define PMU_IOMODULE_IRQ_STATUS_LOGCLR_REQ_SHIFT 23
#define PMU_IOMODULE_IRQ_STATUS_LOGCLR_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_LOGCLR_REQ_MASK ((u32)0X00800000U)
#define PMU_IOMODULE_IRQ_STATUS_IPI3_SHIFT 22
#define PMU_IOMODULE_IRQ_STATUS_IPI3_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_IPI3_MASK ((u32)0X00400000U)
#define PMU_IOMODULE_IRQ_STATUS_IPI2_SHIFT 21
#define PMU_IOMODULE_IRQ_STATUS_IPI2_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_IPI2_MASK ((u32)0X00200000U)
#define PMU_IOMODULE_IRQ_STATUS_IPI1_SHIFT 20
#define PMU_IOMODULE_IRQ_STATUS_IPI1_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_IPI1_MASK ((u32)0X00100000U)
#define PMU_IOMODULE_IRQ_STATUS_IPI0_SHIFT 19
#define PMU_IOMODULE_IRQ_STATUS_IPI0_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_IPI0_MASK ((u32)0X00080000U)
#define PMU_IOMODULE_IRQ_STATUS_RTC_ALARM_SHIFT 18
#define PMU_IOMODULE_IRQ_STATUS_RTC_ALARM_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_RTC_ALARM_MASK ((u32)0X00040000U)
#define PMU_IOMODULE_IRQ_STATUS_RTC_EVERY_SECOND_SHIFT 17
#define PMU_IOMODULE_IRQ_STATUS_RTC_EVERY_SECOND_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_RTC_EVERY_SECOND_MASK ((u32)0X00020000U)
#define PMU_IOMODULE_IRQ_STATUS_CORRECTABLE_ECC_SHIFT 16
#define PMU_IOMODULE_IRQ_STATUS_CORRECTABLE_ECC_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_CORRECTABLE_ECC_MASK ((u32)0X00010000U)
#define PMU_IOMODULE_IRQ_STATUS_GPI3_SHIFT 14
#define PMU_IOMODULE_IRQ_STATUS_GPI3_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_GPI3_MASK ((u32)0X00004000U)
#define PMU_IOMODULE_IRQ_STATUS_GPI2_SHIFT 13
#define PMU_IOMODULE_IRQ_STATUS_GPI2_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_GPI2_MASK ((u32)0X00002000U)
#define PMU_IOMODULE_IRQ_STATUS_GPI1_SHIFT 12
#define PMU_IOMODULE_IRQ_STATUS_GPI1_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_GPI1_MASK ((u32)0X00001000U)
#define PMU_IOMODULE_IRQ_STATUS_GPI0_SHIFT 11
#define PMU_IOMODULE_IRQ_STATUS_GPI0_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_GPI0_MASK ((u32)0X00000800U)
#define PMU_IOMODULE_IRQ_STATUS_PIT3_SHIFT 6
#define PMU_IOMODULE_IRQ_STATUS_PIT3_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_PIT3_MASK ((u32)0X00000040U)
#define PMU_IOMODULE_IRQ_STATUS_PIT2_SHIFT 5
#define PMU_IOMODULE_IRQ_STATUS_PIT2_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_PIT2_MASK ((u32)0X00000020U)
#define PMU_IOMODULE_IRQ_STATUS_PIT1_SHIFT 4
#define PMU_IOMODULE_IRQ_STATUS_PIT1_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_PIT1_MASK ((u32)0X00000010U)
#define PMU_IOMODULE_IRQ_STATUS_PIT0_SHIFT 3
#define PMU_IOMODULE_IRQ_STATUS_PIT0_WIDTH 1
#define PMU_IOMODULE_IRQ_STATUS_PIT0_MASK ((u32)0X00000008U)
/**
* Register: PMU_IOMODULE_IRQ_PENDING
*/
#define PMU_IOMODULE_IRQ_PENDING ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000034U) )
#define PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_SHIFT 31
#define PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_MASK ((u32)0X80000000U)
#define PMU_IOMODULE_IRQ_PENDING_INV_ADDR_SHIFT 29
#define PMU_IOMODULE_IRQ_PENDING_INV_ADDR_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_INV_ADDR_MASK ((u32)0X20000000U)
#define PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_SHIFT 28
#define PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_MASK ((u32)0X10000000U)
#define PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_SHIFT 27
#define PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_MASK ((u32)0X08000000U)
#define PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_SHIFT 26
#define PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_MASK ((u32)0X04000000U)
#define PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_SHIFT 25
#define PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_MASK ((u32)0X02000000U)
#define PMU_IOMODULE_IRQ_PENDING_ISO_REQ_SHIFT 24
#define PMU_IOMODULE_IRQ_PENDING_ISO_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_ISO_REQ_MASK ((u32)0X01000000U)
#define PMU_IOMODULE_IRQ_PENDING_LOGCLR_REQ_SHIFT 23
#define PMU_IOMODULE_IRQ_PENDING_LOGCLR_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_LOGCLR_REQ_MASK ((u32)0X00800000U)
#define PMU_IOMODULE_IRQ_PENDING_IPI3_SHIFT 22
#define PMU_IOMODULE_IRQ_PENDING_IPI3_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_IPI3_MASK ((u32)0X00400000U)
#define PMU_IOMODULE_IRQ_PENDING_IPI2_SHIFT 21
#define PMU_IOMODULE_IRQ_PENDING_IPI2_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_IPI2_MASK ((u32)0X00200000U)
#define PMU_IOMODULE_IRQ_PENDING_IPI1_SHIFT 20
#define PMU_IOMODULE_IRQ_PENDING_IPI1_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_IPI1_MASK ((u32)0X00100000U)
#define PMU_IOMODULE_IRQ_PENDING_IPI0_SHIFT 19
#define PMU_IOMODULE_IRQ_PENDING_IPI0_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_IPI0_MASK ((u32)0X00080000U)
#define PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_SHIFT 18
#define PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_MASK ((u32)0X00040000U)
#define PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_SHIFT 17
#define PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_MASK ((u32)0X00020000U)
#define PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_SHIFT 16
#define PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_MASK ((u32)0X00010000U)
#define PMU_IOMODULE_IRQ_PENDING_GPI3_SHIFT 14
#define PMU_IOMODULE_IRQ_PENDING_GPI3_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_GPI3_MASK ((u32)0X00004000U)
#define PMU_IOMODULE_IRQ_PENDING_GPI2_SHIFT 13
#define PMU_IOMODULE_IRQ_PENDING_GPI2_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_GPI2_MASK ((u32)0X00002000U)
#define PMU_IOMODULE_IRQ_PENDING_GPI1_SHIFT 12
#define PMU_IOMODULE_IRQ_PENDING_GPI1_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_GPI1_MASK ((u32)0X00001000U)
#define PMU_IOMODULE_IRQ_PENDING_GPI0_SHIFT 11
#define PMU_IOMODULE_IRQ_PENDING_GPI0_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_GPI0_MASK ((u32)0X00000800U)
#define PMU_IOMODULE_IRQ_PENDING_PIT3_SHIFT 6
#define PMU_IOMODULE_IRQ_PENDING_PIT3_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_PIT3_MASK ((u32)0X00000040U)
#define PMU_IOMODULE_IRQ_PENDING_PIT2_SHIFT 5
#define PMU_IOMODULE_IRQ_PENDING_PIT2_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_PIT2_MASK ((u32)0X00000020U)
#define PMU_IOMODULE_IRQ_PENDING_PIT1_SHIFT 4
#define PMU_IOMODULE_IRQ_PENDING_PIT1_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_PIT1_MASK ((u32)0X00000010U)
#define PMU_IOMODULE_IRQ_PENDING_PIT0_SHIFT 3
#define PMU_IOMODULE_IRQ_PENDING_PIT0_WIDTH 1
#define PMU_IOMODULE_IRQ_PENDING_PIT0_MASK ((u32)0X00000008U)
/**
* Register: PMU_IOMODULE_IRQ_ENABLE
*/
#define PMU_IOMODULE_IRQ_ENABLE ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000038U) )
#define PMU_IOMODULE_IRQ_ENABLE_CSU_PMU_SEC_LOCK_SHIFT 31
#define PMU_IOMODULE_IRQ_ENABLE_CSU_PMU_SEC_LOCK_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_CSU_PMU_SEC_LOCK_MASK ((u32)0X80000000U)
#define PMU_IOMODULE_IRQ_ENABLE_INV_ADDR_SHIFT 29
#define PMU_IOMODULE_IRQ_ENABLE_INV_ADDR_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_INV_ADDR_MASK ((u32)0X20000000U)
#define PMU_IOMODULE_IRQ_ENABLE_PWR_DN_REQ_SHIFT 28
#define PMU_IOMODULE_IRQ_ENABLE_PWR_DN_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_PWR_DN_REQ_MASK ((u32)0X10000000U)
#define PMU_IOMODULE_IRQ_ENABLE_PWR_UP_REQ_SHIFT 27
#define PMU_IOMODULE_IRQ_ENABLE_PWR_UP_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_PWR_UP_REQ_MASK ((u32)0X08000000U)
#define PMU_IOMODULE_IRQ_ENABLE_SW_RST_REQ_SHIFT 26
#define PMU_IOMODULE_IRQ_ENABLE_SW_RST_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_SW_RST_REQ_MASK ((u32)0X04000000U)
#define PMU_IOMODULE_IRQ_ENABLE_HW_RST_REQ_SHIFT 25
#define PMU_IOMODULE_IRQ_ENABLE_HW_RST_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_HW_RST_REQ_MASK ((u32)0X02000000U)
#define PMU_IOMODULE_IRQ_ENABLE_ISO_REQ_SHIFT 24
#define PMU_IOMODULE_IRQ_ENABLE_ISO_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_ISO_REQ_MASK ((u32)0X01000000U)
#define PMU_IOMODULE_IRQ_ENABLE_LOGCLR_REQ_SHIFT 23
#define PMU_IOMODULE_IRQ_ENABLE_LOGCLR_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_LOGCLR_REQ_MASK ((u32)0X00800000U)
#define PMU_IOMODULE_IRQ_ENABLE_IPI3_SHIFT 22
#define PMU_IOMODULE_IRQ_ENABLE_IPI3_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_IPI3_MASK ((u32)0X00400000U)
#define PMU_IOMODULE_IRQ_ENABLE_IPI2_SHIFT 21
#define PMU_IOMODULE_IRQ_ENABLE_IPI2_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_IPI2_MASK ((u32)0X00200000U)
#define PMU_IOMODULE_IRQ_ENABLE_IPI1_SHIFT 20
#define PMU_IOMODULE_IRQ_ENABLE_IPI1_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_IPI1_MASK ((u32)0X00100000U)
#define PMU_IOMODULE_IRQ_ENABLE_IPI0_SHIFT 19
#define PMU_IOMODULE_IRQ_ENABLE_IPI0_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_IPI0_MASK ((u32)0X00080000U)
#define PMU_IOMODULE_IRQ_ENABLE_RTC_ALARM_SHIFT 18
#define PMU_IOMODULE_IRQ_ENABLE_RTC_ALARM_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_RTC_ALARM_MASK ((u32)0X00040000U)
#define PMU_IOMODULE_IRQ_ENABLE_RTC_EVERY_SECOND_SHIFT 17
#define PMU_IOMODULE_IRQ_ENABLE_RTC_EVERY_SECOND_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_RTC_EVERY_SECOND_MASK ((u32)0X00020000U)
#define PMU_IOMODULE_IRQ_ENABLE_CORRECTABLE_ECC_SHIFT 16
#define PMU_IOMODULE_IRQ_ENABLE_CORRECTABLE_ECC_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_CORRECTABLE_ECC_MASK ((u32)0X00010000U)
#define PMU_IOMODULE_IRQ_ENABLE_GPI3_SHIFT 14
#define PMU_IOMODULE_IRQ_ENABLE_GPI3_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_GPI3_MASK ((u32)0X00004000U)
#define PMU_IOMODULE_IRQ_ENABLE_GPI2_SHIFT 13
#define PMU_IOMODULE_IRQ_ENABLE_GPI2_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_GPI2_MASK ((u32)0X00002000U)
#define PMU_IOMODULE_IRQ_ENABLE_GPI1_SHIFT 12
#define PMU_IOMODULE_IRQ_ENABLE_GPI1_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_GPI1_MASK ((u32)0X00001000U)
#define PMU_IOMODULE_IRQ_ENABLE_GPI0_SHIFT 11
#define PMU_IOMODULE_IRQ_ENABLE_GPI0_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_GPI0_MASK ((u32)0X00000800U)
#define PMU_IOMODULE_IRQ_ENABLE_PIT3_SHIFT 6
#define PMU_IOMODULE_IRQ_ENABLE_PIT3_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_PIT3_MASK ((u32)0X00000040U)
#define PMU_IOMODULE_IRQ_ENABLE_PIT2_SHIFT 5
#define PMU_IOMODULE_IRQ_ENABLE_PIT2_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_PIT2_MASK ((u32)0X00000020U)
#define PMU_IOMODULE_IRQ_ENABLE_PIT1_SHIFT 4
#define PMU_IOMODULE_IRQ_ENABLE_PIT1_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_PIT1_MASK ((u32)0X00000010U)
#define PMU_IOMODULE_IRQ_ENABLE_PIT0_SHIFT 3
#define PMU_IOMODULE_IRQ_ENABLE_PIT0_WIDTH 1
#define PMU_IOMODULE_IRQ_ENABLE_PIT0_MASK ((u32)0X00000008U)
/**
* Register: PMU_IOMODULE_IRQ_ACK
*/
#define PMU_IOMODULE_IRQ_ACK ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X0000003CU) )
#define PMU_IOMODULE_IRQ_ACK_CSU_PMU_SEC_LOCK_SHIFT 31
#define PMU_IOMODULE_IRQ_ACK_CSU_PMU_SEC_LOCK_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_CSU_PMU_SEC_LOCK_MASK ((u32)0X80000000U)
#define PMU_IOMODULE_IRQ_ACK_INV_ADDR_SHIFT 29
#define PMU_IOMODULE_IRQ_ACK_INV_ADDR_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_INV_ADDR_MASK ((u32)0X20000000U)
#define PMU_IOMODULE_IRQ_ACK_PWR_DN_REQ_SHIFT 28
#define PMU_IOMODULE_IRQ_ACK_PWR_DN_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_PWR_DN_REQ_MASK ((u32)0X10000000U)
#define PMU_IOMODULE_IRQ_ACK_PWR_UP_REQ_SHIFT 27
#define PMU_IOMODULE_IRQ_ACK_PWR_UP_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_PWR_UP_REQ_MASK ((u32)0X08000000U)
#define PMU_IOMODULE_IRQ_ACK_SW_RST_REQ_SHIFT 26
#define PMU_IOMODULE_IRQ_ACK_SW_RST_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_SW_RST_REQ_MASK ((u32)0X04000000U)
#define PMU_IOMODULE_IRQ_ACK_HW_RST_REQ_SHIFT 25
#define PMU_IOMODULE_IRQ_ACK_HW_RST_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_HW_RST_REQ_MASK ((u32)0X02000000U)
#define PMU_IOMODULE_IRQ_ACK_ISO_REQ_SHIFT 24
#define PMU_IOMODULE_IRQ_ACK_ISO_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_ISO_REQ_MASK ((u32)0X01000000U)
#define PMU_IOMODULE_IRQ_ACK_LOGCLR_REQ_SHIFT 23
#define PMU_IOMODULE_IRQ_ACK_LOGCLR_REQ_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_LOGCLR_REQ_MASK ((u32)0X00800000U)
#define PMU_IOMODULE_IRQ_ACK_IPI3_SHIFT 22
#define PMU_IOMODULE_IRQ_ACK_IPI3_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_IPI3_MASK ((u32)0X00400000U)
#define PMU_IOMODULE_IRQ_ACK_IPI2_SHIFT 21
#define PMU_IOMODULE_IRQ_ACK_IPI2_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_IPI2_MASK ((u32)0X00200000U)
#define PMU_IOMODULE_IRQ_ACK_IPI1_SHIFT 20
#define PMU_IOMODULE_IRQ_ACK_IPI1_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_IPI1_MASK ((u32)0X00100000U)
#define PMU_IOMODULE_IRQ_ACK_IPI0_SHIFT 19
#define PMU_IOMODULE_IRQ_ACK_IPI0_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_IPI0_MASK ((u32)0X00080000U)
#define PMU_IOMODULE_IRQ_ACK_RTC_ALARM_SHIFT 18
#define PMU_IOMODULE_IRQ_ACK_RTC_ALARM_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_RTC_ALARM_MASK ((u32)0X00040000U)
#define PMU_IOMODULE_IRQ_ACK_RTC_EVERY_SECOND_SHIFT 17
#define PMU_IOMODULE_IRQ_ACK_RTC_EVERY_SECOND_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_RTC_EVERY_SECOND_MASK ((u32)0X00020000U)
#define PMU_IOMODULE_IRQ_ACK_CORRECTABLE_ECC_SHIFT 16
#define PMU_IOMODULE_IRQ_ACK_CORRECTABLE_ECC_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_CORRECTABLE_ECC_MASK ((u32)0X00010000U)
#define PMU_IOMODULE_IRQ_ACK_GPI3_SHIFT 14
#define PMU_IOMODULE_IRQ_ACK_GPI3_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_GPI3_MASK ((u32)0X00004000U)
#define PMU_IOMODULE_IRQ_ACK_GPI2_SHIFT 13
#define PMU_IOMODULE_IRQ_ACK_GPI2_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_GPI2_MASK ((u32)0X00002000U)
#define PMU_IOMODULE_IRQ_ACK_GPI1_SHIFT 12
#define PMU_IOMODULE_IRQ_ACK_GPI1_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_GPI1_MASK ((u32)0X00001000U)
#define PMU_IOMODULE_IRQ_ACK_GPI0_SHIFT 11
#define PMU_IOMODULE_IRQ_ACK_GPI0_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_GPI0_MASK ((u32)0X00000800U)
#define PMU_IOMODULE_IRQ_ACK_PIT3_SHIFT 6
#define PMU_IOMODULE_IRQ_ACK_PIT3_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_PIT3_MASK ((u32)0X00000040U)
#define PMU_IOMODULE_IRQ_ACK_PIT2_SHIFT 5
#define PMU_IOMODULE_IRQ_ACK_PIT2_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_PIT2_MASK ((u32)0X00000020U)
#define PMU_IOMODULE_IRQ_ACK_PIT1_SHIFT 4
#define PMU_IOMODULE_IRQ_ACK_PIT1_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_PIT1_MASK ((u32)0X00000010U)
#define PMU_IOMODULE_IRQ_ACK_PIT0_SHIFT 3
#define PMU_IOMODULE_IRQ_ACK_PIT0_WIDTH 1
#define PMU_IOMODULE_IRQ_ACK_PIT0_MASK ((u32)0X00000008U)
/**
* Register: PMU_IOMODULE_PIT0_PRELOAD
*/
#define PMU_IOMODULE_PIT0_PRELOAD ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000040U) )
#define PMU_IOMODULE_PIT0_PRELOAD_PIT0_PRELOAD_SHIFT 0
#define PMU_IOMODULE_PIT0_PRELOAD_PIT0_PRELOAD_WIDTH 32
#define PMU_IOMODULE_PIT0_PRELOAD_PIT0_PRELOAD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_IOMODULE_PIT0_COUNTER
*/
#define PMU_IOMODULE_PIT0_COUNTER ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000044U) )
#define PMU_IOMODULE_PIT0_COUNTER_PIT0_COUNTER_SHIFT 0
#define PMU_IOMODULE_PIT0_COUNTER_PIT0_COUNTER_WIDTH 32
#define PMU_IOMODULE_PIT0_COUNTER_PIT0_COUNTER_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_IOMODULE_PIT0_CONTROL
*/
#define PMU_IOMODULE_PIT0_CONTROL ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000048U) )
#define PMU_IOMODULE_PIT0_CONTROL_PRELOAD_SHIFT 1
#define PMU_IOMODULE_PIT0_CONTROL_PRELOAD_WIDTH 1
#define PMU_IOMODULE_PIT0_CONTROL_PRELOAD_MASK ((u32)0X00000002U)
#define PMU_IOMODULE_PIT0_CONTROL_EN_SHIFT 0
#define PMU_IOMODULE_PIT0_CONTROL_EN_WIDTH 1
#define PMU_IOMODULE_PIT0_CONTROL_EN_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_PIT1_PRELOAD
*/
#define PMU_IOMODULE_PIT1_PRELOAD ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000050U) )
#define PMU_IOMODULE_PIT1_PRELOAD_PIT1_PRELOAD_SHIFT 0
#define PMU_IOMODULE_PIT1_PRELOAD_PIT1_PRELOAD_WIDTH 32
#define PMU_IOMODULE_PIT1_PRELOAD_PIT1_PRELOAD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_IOMODULE_PIT1_COUNTER
*/
#define PMU_IOMODULE_PIT1_COUNTER ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000054U) )
#define PMU_IOMODULE_PIT1_COUNTER_PIT1_COUNTER_SHIFT 0
#define PMU_IOMODULE_PIT1_COUNTER_PIT1_COUNTER_WIDTH 32
#define PMU_IOMODULE_PIT1_COUNTER_PIT1_COUNTER_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_IOMODULE_PIT1_CONTROL
*/
#define PMU_IOMODULE_PIT1_CONTROL ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000058U) )
#define PMU_IOMODULE_PIT1_CONTROL_PRELOAD_SHIFT 1
#define PMU_IOMODULE_PIT1_CONTROL_PRELOAD_WIDTH 1
#define PMU_IOMODULE_PIT1_CONTROL_PRELOAD_MASK ((u32)0X00000002U)
#define PMU_IOMODULE_PIT1_CONTROL_EN_SHIFT 0
#define PMU_IOMODULE_PIT1_CONTROL_EN_WIDTH 1
#define PMU_IOMODULE_PIT1_CONTROL_EN_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_PIT2_PRELOAD
*/
#define PMU_IOMODULE_PIT2_PRELOAD ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000060U) )
#define PMU_IOMODULE_PIT2_PRELOAD_PIT2_PRELOAD_SHIFT 0
#define PMU_IOMODULE_PIT2_PRELOAD_PIT2_PRELOAD_WIDTH 32
#define PMU_IOMODULE_PIT2_PRELOAD_PIT2_PRELOAD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_IOMODULE_PIT2_COUNTER
*/
#define PMU_IOMODULE_PIT2_COUNTER ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000064U) )
#define PMU_IOMODULE_PIT2_COUNTER_PIT2_COUNTER_SHIFT 0
#define PMU_IOMODULE_PIT2_COUNTER_PIT2_COUNTER_WIDTH 32
#define PMU_IOMODULE_PIT2_COUNTER_PIT2_COUNTER_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_IOMODULE_PIT2_CONTROL
*/
#define PMU_IOMODULE_PIT2_CONTROL ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000068U) )
#define PMU_IOMODULE_PIT2_CONTROL_PRELOAD_SHIFT 1
#define PMU_IOMODULE_PIT2_CONTROL_PRELOAD_WIDTH 1
#define PMU_IOMODULE_PIT2_CONTROL_PRELOAD_MASK ((u32)0X00000002U)
#define PMU_IOMODULE_PIT2_CONTROL_EN_SHIFT 0
#define PMU_IOMODULE_PIT2_CONTROL_EN_WIDTH 1
#define PMU_IOMODULE_PIT2_CONTROL_EN_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_PIT3_PRELOAD
*/
#define PMU_IOMODULE_PIT3_PRELOAD ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000070U) )
#define PMU_IOMODULE_PIT3_PRELOAD_PIT3_PRELOAD_SHIFT 0
#define PMU_IOMODULE_PIT3_PRELOAD_PIT3_PRELOAD_WIDTH 32
#define PMU_IOMODULE_PIT3_PRELOAD_PIT3_PRELOAD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_IOMODULE_PIT3_COUNTER
*/
#define PMU_IOMODULE_PIT3_COUNTER ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000074U) )
#define PMU_IOMODULE_PIT3_COUNTER_PIT3_COUNTER_SHIFT 0
#define PMU_IOMODULE_PIT3_COUNTER_PIT3_COUNTER_WIDTH 32
#define PMU_IOMODULE_PIT3_COUNTER_PIT3_COUNTER_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_IOMODULE_PIT3_CONTROL
*/
#define PMU_IOMODULE_PIT3_CONTROL ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000078U) )
#define PMU_IOMODULE_PIT3_CONTROL_PRELOAD_SHIFT 1
#define PMU_IOMODULE_PIT3_CONTROL_PRELOAD_WIDTH 1
#define PMU_IOMODULE_PIT3_CONTROL_PRELOAD_MASK ((u32)0X00000002U)
#define PMU_IOMODULE_PIT3_CONTROL_EN_SHIFT 0
#define PMU_IOMODULE_PIT3_CONTROL_EN_WIDTH 1
#define PMU_IOMODULE_PIT3_CONTROL_EN_MASK ((u32)0X00000001U)
/**
* Register: PMU_IOMODULE_INSTRUCTION_INJECT_ADDR
*/
#define PMU_IOMODULE_INSTRUCTION_INJECT_ADDR ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00001014U) )
#define PMU_IOMODULE_INSTRUCTION_INJECT_ADDR_BIT0_SHIFT 0
#define PMU_IOMODULE_INSTRUCTION_INJECT_ADDR_BIT0_WIDTH 32
#define PMU_IOMODULE_INSTRUCTION_INJECT_ADDR_BIT0_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_IOMODULE_INSTRUCTION_INJECT
*/
#define PMU_IOMODULE_INSTRUCTION_INJECT ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00001018U) )
#define PMU_IOMODULE_INSTRUCTION_INJECT_BIT0_SHIFT 0
#define PMU_IOMODULE_INSTRUCTION_INJECT_BIT0_WIDTH 32
#define PMU_IOMODULE_INSTRUCTION_INJECT_BIT0_MASK ((u32)0XFFFFFFFFU)
#ifdef __cplusplus
}
#endif
#endif /* _PMU_IOMODULE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/versal/xsecure_sha_hw.h
/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_sha_hw.h
* This file contains SHA3 core hardware definitions for Versal.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.2 har 03/20/20 Initial release
*
* </pre>
*
* @endcond
******************************************************************************/
#ifndef XSECURE_SHA_HW_H
#define XSECURE_SHA_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xsecure_utils.h"
/************************** Constant Definitions ****************************/
/**< SHA3 base address */
#define XSECURE_SHA3_BASE (0xF1210000U)
/** @name Register Map
*
* Register offsets for the SHA module.
* @{
*/
#define XSECURE_SHA3_START_OFFSET (0x00U) /**< SHA start message */
#define XSECURE_SHA3_RESET_OFFSET (0x04U) /**< Reset Register */
#define XSECURE_SHA3_DONE_OFFSET (0x08U) /**< SHA Done Register */
#define XSECURE_SHA3_DIGEST_0_OFFSET (0x10U)
/**< SHA3 Digest: Reg 0 */
#define XSECURE_SHA3_DIGEST_11_OFFSET (0x3CU)
/**< SHA3 Digest: Last Register */
/* @} */
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_SHA_HW_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/xfsbl_ddr_init.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xfsbl_ddr_init.c
*
* This is the file which contains initialization code for the DDR. This
* code is used for all the ZynqMP boards.
*
* This code will identify the DDR DIMM part by fetching SPD data from EEPROM
* of the DIMM on run time and Initialize the same.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 mn 07/06/18 Add DDR initialization support for new DDR DIMM part
* mn 07/18/18 Move iicps.h inclusion under ZCU102 and ZCU106 macro
* checks
* 2.0 mn 02/28/19 Add Dynamic DDR initialization support for all DDR DIMMs
* mn 03/12/19 Select EEPROM Lower Page for reading SPD data
* mn 09/03/19 Fix coverity warnings
* 2.1 mn 12/24/19 Enable Address Mirroring based on SPD data
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xfsbl_hw.h"
#ifdef XFSBL_PS_DDR
#ifdef XPAR_DYNAMIC_DDR_ENABLED
#include "xiicps.h"
#include "xfsbl_ddr_init.h"
/************************** Constant Definitions *****************************/
/* Default values for DDRC register fields */
#define XFSBL_DDRC_REG_DEFVAL { \
0x0U, 0x0U, 0x0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x3U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x800000U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x40U, 0x20U, 0x10U, 0x2U, 0x10U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x62U, \
0x0U, 0x8CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x10U, 0x1U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x30U, 0x5U, 0x0U, \
0x0U, 0x2U, 0x4EU, 0x0U, 0x0U, 0x0U, 0xDU, 0x5U, \
0x0U, 0x510U, 0x5102U, 0x5103U, 0x0U, 0x4U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x6U, 0x6U, 0xFU, 0xFU, 0x10U, 0x1BU, \
0xFU, 0x8U, 0x4U, 0x14U, 0x3U, 0x5U, 0x6U, 0xDU, \
0x5U, 0x4U, 0xCU, 0x5U, 0x4U, 0x4U, 0x5U, 0x5U, \
0x5U, 0x4U, 0x3U, 0x0U, 0x0U, 0x5U, 0x2U, 0x2U, \
0x3U, 0x3U, 0x44U, 0x5U, 0x0U, 0x4U, 0x4U, 0xDU, \
0x44U, 0xCU, 0x0U, 0x1CU, 0x2U, 0x6U, 0x10U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x200U, 0x40U, 0x20U, \
0x100U, 0x0U, 0x0U, 0x2U, 0x0U, 0x0U, 0x2U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x40U, 0x3U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x2U, \
0x2U, 0x0U, 0x0U, 0x1U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x4U, 0x0U, 0x4U, 0x0U, 0x0U, 0x2U, 0x0U, 0x1U, \
0x0U, 0x0U, 0x20U, 0x0U, 0x0U, 0x1U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U \
}
/* Default values for DDR-PHY register fields */
#define XFSBL_PHY_REG_DEFVAL { \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0xEU, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x5U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x4U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x1D0U, 0x0U, 0x0U, 0x200U, 0x8U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x1U, 0xDU, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x1U, 0xDU, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x2U, 0x1U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x5U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x5U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x5U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x19U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x7U, 0x7U, \
0xBU, 0xBU, 0x0U, 0x1U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x1U, \
0x0U, 0x0U, 0x0U, 0x1U, 0x1U, 0x1U, 0x1U, 0x1U, \
0xFFU, 0x1U, 0x1U, 0x1U, 0x1U, 0x1U, 0x1U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x2U, \
0x0U, 0x0U, 0x0U, 0x1U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x1U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, \
0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U \
}
/* Column offset Value used for HIF calculation */
#define XFSBL_HIF_COLUMN(XVal) (100U + (XVal))
/* Row offset Value used for HIF calculation */
#define XFSBL_HIF_ROW(XVal) (200U + (XVal))
/* Bank offset Value used for HIF calculation */
#define XFSBL_HIF_BANK(XVal) (300U + (XVal))
/* Bank Group offset Value used for HIF calculation */
#define XFSBL_HIF_BG(XVal) (400U + (XVal))
/* Rank offset Value used for HIF calculation */
#define XFSBL_HIF_RANK(XVal) (500U + (XVal))
/* IIC Serial Clock rate */
#define XFSBL_IIC_SCLK_RATE 100000U
/* IIC Mux Address */
#define XFSBL_MUX_ADDR 0x75U
/* SODIMM Slave Address */
#define XFSBL_SODIMM_SLAVE_ADDR 0x51U
/* SODIMM Control Address Low */
#define XFSBL_SODIMM_CONTROL_ADDR_LOW 0x36U
/* SODIMM Control Address High */
#define XFSBL_SODIMM_CONTROL_ADDR_HIGH 0x37U
/* IIC Bus Idle Timeout */
#define XFSBL_IIC_BUS_TIMEOUT 1000000U
#define XFSBL_DDR_TRAINING_TIMEOUT 1000000U
#define XFSBL_DDRC_BASE_ADDR 0xFD070000U
#define XFSBL_DDRPHY_BASE_ADDR 0xFD080000U
#define XFSBL_DBI_INFO XPAR_PSU_DDRC_0_DDR_DATA_MASK_AND_DBI
#define XFSBL_VIDEOBUF XPAR_PSU_DDRC_0_VIDEO_BUFFER_SIZE
#define XFSBL_BRCMAPPING XPAR_PSU_DDRC_0_BRC_MAPPING
#define XFSBL_DDR4ADDRMAPPING XPAR_PSU_DDRC_0_DDR4_ADDR_MAPPING
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/* Macro to find the maximum between two values */
#define XFSBL_MAX(Val1, Val2) (((Val1) > (Val2)) ? (Val1) : (Val2))
/* Macro to find the minimum between two values */
#define XFSBL_MIN(Val1, Val2) (((Val1) < (Val2)) ? (Val1) : (Val2))
/* Macro to set particular bits in a register */
#define XFSBL_SETBITS(a, b, c) ((a & ((1U << c) - 1U)) << b)
/* Macro to poll for register bits to be set with certain value */
#define XFSBL_POLL(a, b, c) {while ((Xil_In32(a) & (b)) != (c));}
/* Macro to poll for register bits to be set equal to given mask value */
#define XFSBL_MASK_POLL(a, b) {while ((Xil_In32(a) & (b)) != (b));}
/* Program the register with given value, shifts and mask */
#define XFSBL_PROG_REG(Addr, mask, shift, Value) { \
Xil_Out32((Addr), ((Xil_In32(Addr) & \
(~(mask))) | ((Value) << (shift)))); \
}
/* Convert the timing value from SPD to picoseconds */
#define XFSBL_SPD_TO_PS(Mtb, Ftb) \
(Mtb * PDimmPtr->MtbPs + (Ftb * (s8)PDimmPtr->Ftb10thPs) / 10)
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* This function returns log2 of the given value in argument
*
* @param XVal is the value whose log2 value is returned
*
* @return returns log2 of the given value
*
*****************************************************************************/
static u32 XFsbl_GetLog2(u32 XVal)
{
u32 RVal = 0U;
if (XVal == 0U) {
goto END;
}
while (XVal != 1U) {
RVal = RVal + 1U;
XVal = XVal >> 1U;
}
END:
return RVal;
}
/*****************************************************************************/
/**
* This function returns the particular DDR rank
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
*
* @return returns DDR Rank Size
*
*****************************************************************************/
u64 XFsbl_ComputeDdr4RankSize(struct Ddr4SpdEeprom *Ddr4SpdData)
{
u64 BSize;
u32 NbitDdramCapBsize;
u32 NbitPrimaryBusWidth;
u32 NbitSdramWidth;
u32 DieCount;
u8 Package3Ds;
if ((Ddr4SpdData->DensityBanks & 0xFU) <= 7U) {
NbitDdramCapBsize = (Ddr4SpdData->DensityBanks & 0xFU) + 28U;
} else {
NbitDdramCapBsize = 0U;
}
if ((Ddr4SpdData->BusWidth & 0x7U) < 4U) {
NbitPrimaryBusWidth = (Ddr4SpdData->BusWidth & 0x7U) + 3U;
} else {
NbitPrimaryBusWidth = 0U;
}
if ((Ddr4SpdData->Organization & 0x7U) < 4U) {
NbitSdramWidth = (Ddr4SpdData->Organization & 0x7U) + 2U;
} else {
NbitSdramWidth = 0U;
}
Package3Ds = (Ddr4SpdData->PackageType & 0x3U) == 0x2U;
if (Package3Ds) {
DieCount = (Ddr4SpdData->PackageType >> 4U) & 0x7U;
} else {
DieCount = 0U;
}
BSize = 1ULL << (NbitDdramCapBsize - 3U +
NbitPrimaryBusWidth - NbitSdramWidth +
DieCount);
return BSize;
}
/*****************************************************************************/
/**
* This function returns the particular DDR rank
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
*
* @return returns DDR Rank Size
*
*****************************************************************************/
u64 XFsbl_ComputeDdr3RankSize(struct Ddr3SpdEeprom *Ddr3SpdData)
{
u64 BSize;
u32 NbitDdramCapBsize;
u32 NbitPrimaryBusWidth;
u32 NbitSdramWidth;
if ((Ddr3SpdData->DensityBanks & 0xFU) < 7U) {
NbitDdramCapBsize = (Ddr3SpdData->DensityBanks & 0xFU) + 28U;
} else {
NbitDdramCapBsize = 0U;
}
if ((Ddr3SpdData->BusWidth & 0x7U) < 4U) {
NbitPrimaryBusWidth = (Ddr3SpdData->BusWidth & 0x7U) + 3U;
} else {
NbitPrimaryBusWidth = 0U;
}
if ((Ddr3SpdData->Organization & 0x7U) < 4U) {
NbitSdramWidth = (Ddr3SpdData->Organization & 0x7U) + 2U;
} else {
NbitSdramWidth = 0U;
}
BSize = 1ULL << (NbitDdramCapBsize - 3U
+ NbitPrimaryBusWidth - NbitSdramWidth);
return BSize;
}
/*****************************************************************************/
/**
* This function returns the particular DDR rank
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
*
* @return returns DDR Rank Size
*
*****************************************************************************/
u64 XFsbl_ComputeLpDdrRankSize(struct LpDdrSpdEeprom *LpDdrSpdData)
{
u64 BSize;
u32 NbitDdramCapBsize;
u32 NbitPrimaryBusWidth;
u32 NbitSdramWidth;
u32 DieCount;
u8 Package3Ds;
if ((LpDdrSpdData->DensityBanks & 0xFU) <= 7U) {
NbitDdramCapBsize = (LpDdrSpdData->DensityBanks & 0xFU) + 28U;
} else {
NbitDdramCapBsize = 0U;
}
if ((LpDdrSpdData->BusWidth & 0x7U) < 4U) {
NbitPrimaryBusWidth = (LpDdrSpdData->BusWidth & 0x7U) + 3U;
} else {
NbitPrimaryBusWidth = 0U;
}
if ((LpDdrSpdData->Organization & 0x7U) < 4U) {
NbitSdramWidth = (LpDdrSpdData->Organization & 0x7U) + 2U;
} else {
NbitSdramWidth = 0U;
}
Package3Ds = (LpDdrSpdData->PackageType & 0x3U) == 0x2U;
if (Package3Ds) {
DieCount = (LpDdrSpdData->PackageType >> 4U) & 0x7U;
} else {
DieCount = 0U;
}
BSize = 1ULL << (NbitDdramCapBsize - 3U +
NbitPrimaryBusWidth - NbitSdramWidth +
DieCount);
return BSize;
}
/*****************************************************************************/
/**
* This function computes DIMM parameters based upon the SPD information in
* Ddr4SpdData. Writes the results to the XFsbl_DimmParams structure pointed
* by PDimmPtr.
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param SpdData is the array containing the SPD data from DIMM EEPROM
*
* @return XFSBL_SUCCESS or XFSBL_FAILURE
*
*****************************************************************************/
u32 XFsbl_ComputeDdr4Params(u8 *SpdData, struct DdrcInitData *DdrDataPtr)
{
struct Ddr4SpdEeprom *Ddr4SpdData = (struct Ddr4SpdEeprom *)SpdData;
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
u32 Status = XFSBL_FAILURE;
memset(PDimmPtr->Mpart, 0U, sizeof(PDimmPtr->Mpart));
if ((Ddr4SpdData->InfoSizeCrc & 0xFU) > 2U)
memcpy(PDimmPtr->Mpart, Ddr4SpdData->Mpart, sizeof(PDimmPtr->Mpart) - 1U);
PDimmPtr->MemType = Ddr4SpdData->MemType;
PDimmPtr->NRanks = ((Ddr4SpdData->Organization >> 3U) & 0x7U) + 1U;
PDimmPtr->RankDensity = XFsbl_ComputeDdr4RankSize(Ddr4SpdData);
PDimmPtr->Capacity = (PDimmPtr->NRanks * PDimmPtr->RankDensity) / (1024U * 1024U);
PDimmPtr->BusWidth = 1U << (3U + (Ddr4SpdData->BusWidth & 0x7U));
if ((Ddr4SpdData->BusWidth >> 3U) & 0x3U)
PDimmPtr->EccBusWidth = 8U;
else
PDimmPtr->EccBusWidth = 0U;
PDimmPtr->DramWidth = 1U << ((Ddr4SpdData->Organization & 0x7U) + 2U);
PDimmPtr->AddrMirror = 0U;
PDimmPtr->RDimm = 0U;
switch (Ddr4SpdData->ModuleType & DDR4_SPD_MODULETYPE_MASK) {
case DDR4_SPD_MODULETYPE_RDIMM:
case DDR4_SPD_MODULETYPE_72B_SO_RDIMM:
PDimmPtr->RDimm = 1U;
break;
case DDR4_SPD_MODULETYPE_UDIMM:
case DDR4_SPD_MODULETYPE_SO_DIMM:
case DDR4_SPD_MODULETYPE_72B_SO_UDIMM:
PDimmPtr->UDimm = 1U;
if (Ddr4SpdData->ModSection.unbuffered.AddrMapping & 0x1U)
PDimmPtr->AddrMirror = 1U;
break;
default:
/* Do nothing as Status is initialized to XFSBL_FAILURE */
goto END;
}
PDimmPtr->NumRowAddr = ((Ddr4SpdData->Addressing >> 3U) & 0x7U) + 12U;
PDimmPtr->NumColAddr = (Ddr4SpdData->Addressing & 0x7U) + 9U;
PDimmPtr->NumBankAddr = ((Ddr4SpdData->DensityBanks >> 4U) & 0x3U) + 2U;
PDimmPtr->NumBgAddr = (Ddr4SpdData->DensityBanks >> 6U) & 0x3U;
PDimmPtr->NumRankAddr = XFsbl_GetLog2(PDimmPtr->NRanks);
PDimmPtr->BurstLength = 8U;
PDimmPtr->RowDensity = XFsbl_GetLog2(PDimmPtr->RankDensity);
if ((Ddr4SpdData->Timebases & 0xFU) == 0x0U) {
PDimmPtr->MtbPs = 125U;
PDimmPtr->Ftb10thPs = 10U;
}
PDimmPtr->TckminXPs = XFSBL_SPD_TO_PS(Ddr4SpdData->TckMin, Ddr4SpdData->FineTckMin);
PDimmPtr->SpeedBin = (u32)XFsbl_Ceil(2000000.0 / PDimmPtr->TckminXPs);
PDimmPtr->FreqMhz = 1000000.0 / PDimmPtr->TckminXPs;
PDimmPtr->ClockPeriod = PDimmPtr->TckminXPs / 1000.0;
PDimmPtr->TckmaxPs = XFSBL_SPD_TO_PS(Ddr4SpdData->TckMax, Ddr4SpdData->FineTckMax);
PDimmPtr->CaslatX = (Ddr4SpdData->CaslatB1 << 7U) |
(Ddr4SpdData->CaslatB2 << 15U) |
(Ddr4SpdData->CaslatB3 << 23U);
PDimmPtr->TaaPs = XFSBL_SPD_TO_PS(Ddr4SpdData->TaaMin, Ddr4SpdData->FineTaaMin);
PDimmPtr->CasLatency = (u32)XFsbl_Ceil(PDimmPtr->TaaPs / 1000.0) + 1U;
PDimmPtr->CasWriteLatency = XFsbl_Ceil(PDimmPtr->TaaPs / 1000.0);
PDimmPtr->TRcdPs = XFSBL_SPD_TO_PS(Ddr4SpdData->TrcdMin, Ddr4SpdData->FineTrcdMin);
PDimmPtr->TRpPs = XFSBL_SPD_TO_PS(Ddr4SpdData->TrpMin, Ddr4SpdData->FineTrpMin);
PDimmPtr->TRasPs = (((Ddr4SpdData->TrasTrcExt & 0xFU) << 8U) +
Ddr4SpdData->TrasMinLsb) * PDimmPtr->MtbPs;
PDimmPtr->TRcPs = XFSBL_SPD_TO_PS((((Ddr4SpdData->TrasTrcExt & 0xF0U) << 4U) +
Ddr4SpdData->TrcMinLsb), Ddr4SpdData->FineTrcMin);
PDimmPtr->TRfc1Ps = ((Ddr4SpdData->Trfc1MinMsb << 8U) | (Ddr4SpdData->Trfc1MinLsb)) *
PDimmPtr->MtbPs;
PDimmPtr->TRfc2Ps = ((Ddr4SpdData->Trfc2MinMsb << 8U) | (Ddr4SpdData->Trfc2MinLsb)) *
PDimmPtr->MtbPs;
PDimmPtr->TRfc4Ps = ((Ddr4SpdData->Trfc4MinMsb << 8U) | (Ddr4SpdData->Trfc4MinLsb)) *
PDimmPtr->MtbPs;
PDimmPtr->TFawPs = (((Ddr4SpdData->TfawMsb & 0xFU) << 8U) | Ddr4SpdData->TfawMin) *
PDimmPtr->MtbPs;
PDimmPtr->TRrdsPs = XFSBL_SPD_TO_PS(Ddr4SpdData->TrrdsMin, Ddr4SpdData->FineTrrdsMin);
PDimmPtr->TRrdlPs = XFSBL_SPD_TO_PS(Ddr4SpdData->TrrdlMin, Ddr4SpdData->FineTrrdlMin);
PDimmPtr->TCcdlPs = XFSBL_SPD_TO_PS(Ddr4SpdData->TccdlMin, Ddr4SpdData->FineTccdlMin);
PDimmPtr->TRefi = 7800000U;
Status = XFSBL_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
* This function computes DIMM parameters based upon the SPD information in
* Dd34SpdData. Writes the results to the XFsbl_DimmParams structure pointed
* by PDimmPtr.
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param SpdData is the array containing the SPD data from DIMM EEPROM
*
* @return XFSBL_SUCCESS or XFSBL_FAILURE
*
*****************************************************************************/
u32 XFsbl_ComputeDdr3Params(u8 *SpdData, struct DdrcInitData *DdrDataPtr)
{
struct Ddr3SpdEeprom *Ddr3SpdData = (struct Ddr3SpdEeprom *)SpdData;
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
u32 MtbPs;
u32 Ftb10thPs;
u32 Status = XFSBL_FAILURE;
memset(PDimmPtr->Mpart, 0U, sizeof(PDimmPtr->Mpart));
if ((Ddr3SpdData->InfoSizeCrc & 0xFU) > 1U)
memcpy(PDimmPtr->Mpart, Ddr3SpdData->Mpart, sizeof(PDimmPtr->Mpart) - 1U);
PDimmPtr->MemType = Ddr3SpdData->MemType;
PDimmPtr->NRanks = ((Ddr3SpdData->Organization >> 3U) & 0x7U) + 1U;
PDimmPtr->RankDensity = XFsbl_ComputeDdr3RankSize(Ddr3SpdData);
PDimmPtr->Capacity = PDimmPtr->NRanks * PDimmPtr->RankDensity;
PDimmPtr->BusWidth = 1U << (3U + (Ddr3SpdData->BusWidth & 0x7U));
if ((Ddr3SpdData->BusWidth >> 3U) & 0x3U)
PDimmPtr->EccBusWidth = 8U;
else
PDimmPtr->EccBusWidth = 0U;
PDimmPtr->DramWidth = 1U << ((Ddr3SpdData->Organization & 0x7U) + 2U);
PDimmPtr->AddrMirror = 0U;
PDimmPtr->RDimm = 0U;
switch (Ddr3SpdData->ModuleType & DDR3_SPD_MODULETYPE_MASK) {
case DDR3_SPD_MODULETYPE_RDIMM:
case DDR3_SPD_MODULETYPE_MINI_RDIMM:
case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
PDimmPtr->RDimm = 1U;
break;
case DDR3_SPD_MODULETYPE_UDIMM:
case DDR3_SPD_MODULETYPE_SO_DIMM:
case DDR3_SPD_MODULETYPE_MICRO_DIMM:
case DDR3_SPD_MODULETYPE_MINI_UDIMM:
case DDR3_SPD_MODULETYPE_MINI_CDIMM:
case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
case DDR3_SPD_MODULETYPE_LRDIMM:
case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
if (Ddr3SpdData->ModSection.unbuffered.AddrMapping & 0x1U)
PDimmPtr->AddrMirror = 1U;
break;
default:
/* Do nothing as Status is initialized to XFSBL_FAILURE */
goto END;
}
PDimmPtr->NBanksPerSdramDevice = 8U << ((Ddr3SpdData->DensityBanks >> 4U) & 0x7U);
PDimmPtr->NumRowAddr = ((Ddr3SpdData->Addressing >> 3U) & 0x7U) + 12U;
PDimmPtr->NumColAddr = (Ddr3SpdData->Addressing & 0x7U) + 9U;
PDimmPtr->NumBankAddr = ((Ddr3SpdData->DensityBanks >> 4U) & 0x3U) + 2U;
PDimmPtr->NumBgAddr = (Ddr3SpdData->DensityBanks >> 6U) & 0x3U;
PDimmPtr->NumRankAddr = XFsbl_GetLog2(PDimmPtr->NRanks);
PDimmPtr->BurstLength = 8U;
PDimmPtr->RowDensity = XFsbl_GetLog2(PDimmPtr->RankDensity);
MtbPs = (Ddr3SpdData->MtbDividend * 1000U) / Ddr3SpdData->MtbDivisor;
PDimmPtr->MtbPs = MtbPs;
Ftb10thPs =
((Ddr3SpdData->FtbDiv & 0xF0U) >> 4U) * 10U / (Ddr3SpdData->FtbDiv & 0x0fU);
PDimmPtr->Ftb10thPs = Ftb10thPs;
PDimmPtr->TckminXPs = Ddr3SpdData->TckMin * MtbPs +
(Ddr3SpdData->FineTckMin * Ftb10thPs) / 10U;
PDimmPtr->CaslatX = ((Ddr3SpdData->CaslatMsb << 8U) | Ddr3SpdData->CaslatLsb) << 4U;
PDimmPtr->TaaPs = Ddr3SpdData->TaaMin * MtbPs +
(Ddr3SpdData->FineTaaMin * Ftb10thPs) / 10U;
PDimmPtr->TwrPs = Ddr3SpdData->TwrMin * MtbPs;
PDimmPtr->TRcdPs = Ddr3SpdData->TrcdMin * MtbPs +
(Ddr3SpdData->FineTrcdMin * Ftb10thPs) / 10U;
PDimmPtr->TRrdPs = Ddr3SpdData->TrrdMin * MtbPs;
PDimmPtr->TRpPs = Ddr3SpdData->TrpMin * MtbPs +
(Ddr3SpdData->FineTrpMin * Ftb10thPs) / 10U;
PDimmPtr->TRasPs = (((Ddr3SpdData->TrasTrcExt & 0xFU) << 8U) | Ddr3SpdData->TrasMinLsb)
* MtbPs;
PDimmPtr->TRcPs = (((Ddr3SpdData->TrasTrcExt & 0xF0U) << 4U) | Ddr3SpdData->TrcMinLsb)
* MtbPs + (Ddr3SpdData->FineTrcMin * Ftb10thPs) / 10U;
PDimmPtr->TRfcPs = ((Ddr3SpdData->TrfcMinMsb << 8U) | Ddr3SpdData->TrfcMinLsb)
* MtbPs;
PDimmPtr->TwtrPs = Ddr3SpdData->TwtrMin * MtbPs;
PDimmPtr->TrtpPs = Ddr3SpdData->TrtpMin * MtbPs;
PDimmPtr->TRefi = 7800000U;
if ((Ddr3SpdData->ThermRefOpt & 0x1U) && !(Ddr3SpdData->ThermRefOpt & 0x2U)) {
PDimmPtr->TRefi = 3900000U;
}
PDimmPtr->TFawPs = (((Ddr3SpdData->TfawMsb & 0xFU) << 8U) | Ddr3SpdData->TfawMin)
* MtbPs;
Status = XFSBL_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
* This function computes DIMM parameters based upon the SPD information in
* LpDdrSpdData. Writes the results to the XFsbl_DimmParams structure pointed
* by PDimmPtr.
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param SpdData is the array containing the SPD data from DIMM EEPROM
*
* @return XFSBL_SUCCESS or XFSBL_FAILURE
*
*****************************************************************************/
u32 XFsbl_ComputeLpDdrParams(u8 *SpdData, struct DdrcInitData *DdrDataPtr)
{
struct LpDdrSpdEeprom *LpDdrSpdData = (struct LpDdrSpdEeprom *)SpdData;
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
memset(PDimmPtr->Mpart, 0U, sizeof(PDimmPtr->Mpart));
if ((LpDdrSpdData->InfoSizeCrc & 0xFU) > 2U)
memcpy(PDimmPtr->Mpart, LpDdrSpdData->Mpart, sizeof(PDimmPtr->Mpart) - 1U);
PDimmPtr->MemType = LpDdrSpdData->MemType;
PDimmPtr->NRanks = ((LpDdrSpdData->Organization >> 3U) & 0x7U) + 1U;
PDimmPtr->RankDensity = XFsbl_ComputeLpDdrRankSize(LpDdrSpdData);
PDimmPtr->Capacity = (PDimmPtr->NRanks * PDimmPtr->RankDensity) / (1024U * 1024U);
PDimmPtr->BusWidth = 1U << (3U + (LpDdrSpdData->BusWidth & 0x7U));
if ((LpDdrSpdData->BusWidth >> 3U) & 0x3U)
PDimmPtr->EccBusWidth = 8U;
else
PDimmPtr->EccBusWidth = 0U;
PDimmPtr->DramWidth = 1U << ((LpDdrSpdData->Organization & 0x7U) + 2U);
PDimmPtr->AddrMirror = 0U;
PDimmPtr->RDimm = 0U;
PDimmPtr->NumRowAddr = ((LpDdrSpdData->Addressing >> 3U) & 0x7U) + 12U;
PDimmPtr->NumColAddr = (LpDdrSpdData->Addressing & 0x7U) + 9U;
PDimmPtr->NumBankAddr = ((LpDdrSpdData->DensityBanks >> 4U) & 0x3U) + 2U;
PDimmPtr->NumBgAddr = (LpDdrSpdData->DensityBanks >> 6U) & 0x3U;
PDimmPtr->NumRankAddr = XFsbl_GetLog2(PDimmPtr->NRanks);
PDimmPtr->BurstLength = 8U;
PDimmPtr->RowDensity = XFsbl_GetLog2(PDimmPtr->RankDensity);
if ((LpDdrSpdData->Timebases & 0xFU) == 0x0U) {
PDimmPtr->MtbPs = 125U;
PDimmPtr->Ftb10thPs = 10U;
}
PDimmPtr->TckminXPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TckMin, LpDdrSpdData->FineTckMin);
PDimmPtr->SpeedBin = (u32)XFsbl_Ceil(2000000.0 / PDimmPtr->TckminXPs);
PDimmPtr->FreqMhz = 1000000.0 / PDimmPtr->TckminXPs;
PDimmPtr->ClockPeriod = PDimmPtr->TckminXPs / 1000.0;
PDimmPtr->TckmaxPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TckMax, LpDdrSpdData->FineTckMax);
PDimmPtr->CaslatX = (LpDdrSpdData->CaslatB1 << 7U) |
(LpDdrSpdData->CaslatB2 << 15U) |
(LpDdrSpdData->CaslatB3 << 23U);
PDimmPtr->TaaPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TaaMin, LpDdrSpdData->FineTaaMin);
PDimmPtr->CasLatency = (u32)XFsbl_Ceil(PDimmPtr->TaaPs / 1000.0) + 1U;
PDimmPtr->CasWriteLatency = XFsbl_Ceil(PDimmPtr->TaaPs / 1000.0);
PDimmPtr->TRcdPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TrcdMin, LpDdrSpdData->FineTrcdMin);
PDimmPtr->TrpabPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TrpabMin, LpDdrSpdData->FineTrpabMin);
PDimmPtr->TrppbPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TrppbMin, LpDdrSpdData->FineTrppbMin);
PDimmPtr->TRfcAbPs = ((LpDdrSpdData->TrfcabMinMsb << 8U) |
(LpDdrSpdData->TrfcabMinLsb)) *
PDimmPtr->MtbPs;
PDimmPtr->TRfcPbPs = ((LpDdrSpdData->TrfcpbMinMsb << 8U) |
(LpDdrSpdData->TrfcpbMinLsb)) *
PDimmPtr->MtbPs;
if ((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) ||
((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) &&
(PDimmPtr->Capacity != 1024U))) {
PDimmPtr->TRefi = 3900000U;
} else {
PDimmPtr->TRefi = 7800000U;
}
return XFSBL_SUCCESS;
}
#if !(defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
|| defined(XPS_BOARD_ZCU208))
/*****************************************************************************/
/**
* This function computes DIMM parameters based upon the SPD information.
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param SpdData is the array containing SPD data got from EEPROM
*
* @return XFSBL_SUCCESS or XFSBL_FAILURE
*
*****************************************************************************/
static u32 XFsbl_DdrComputeDimmParameters(u8 *SpdData,
struct DdrcInitData *DdrDataPtr)
{
u32 Status = XFSBL_FAILURE;
switch (SpdData[2U]) {
case SPD_MEMTYPE_DDR4:
Status = XFsbl_ComputeDdr4Params(SpdData, DdrDataPtr);
break;
case SPD_MEMTYPE_DDR3:
Status = XFsbl_ComputeDdr3Params(SpdData, DdrDataPtr);
break;
case SPD_MEMTYPE_LPDDR3:
case SPD_MEMTYPE_LPDDR4:
Status = XFsbl_ComputeLpDdrParams(SpdData, DdrDataPtr);
break;
default:
/* Do nothing as Status is initialized to XFSBL_FAILURE */
break;
}
return Status;
}
#endif
/*****************************************************************************/
/**
* This function calculates the HIF Addresses for Non-DDR4 mode
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param HifAddr is the pointer to the HIF Addresses Array
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrCalcDdr4HifAddr(struct DdrcInitData *DdrDataPtr, u32 *HifAddr)
{
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
u32 Position = 0U;
u32 Index;
/* Define Column positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumColAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_COLUMN(Index);
Position++;
}
/* Define Bank Group positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumBgAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_BG(Index);
Position++;
}
/* Define Bank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumBankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_BANK(Index);
Position++;
}
/* Define Row positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumRowAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_ROW(Index);
Position++;
}
/* Define Rank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumRankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_RANK(Index);
Position++;
}
}
#if (XFSBL_VIDEOBUF != 0U)
/*****************************************************************************/
/**
* This function calculates the HIF Addresses for Video mapping mode
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param HifAddr is the pointer to the HIF Addresses Array
* @param VideoBuf is size of Video Buffer used in the design
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrCalcHifAddrVideo(struct DdrcInitData *DdrDataPtr,
u32 *HifAddr, u32 VideoBuf)
{
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
u32 Position=0U;
u32 Index;
u32 BufWidth;
u32 RemainingRow;
/* Calculate Buffer Width based on Video Buffer Size */
for (Index = 0U; Index <= 6U; Index++) {
if (((u32)1U << Index) == VideoBuf) {
BufWidth = Index + 20U;
break;
} else {
BufWidth = 20U;
}
}
if (PDimmPtr->BusWidth == 16U) {
BufWidth = BufWidth + 2U;
}
if (PDimmPtr->BusWidth == 32U) {
BufWidth = BufWidth + 1U;
}
if (PDimmPtr->MemType != SPD_MEMTYPE_DDR4) {
/* Define Column positions in HIF Addresses */
for (Index = 3U; Index < PDimmPtr->NumColAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_COLUMN(Index);
Position++;
}
/* Define Row positions in HIF Addresses */
for (Index = 0U; Index < (BufWidth - PDimmPtr->NumColAddr - 3U); Index++) {
HifAddr[Position] = XFSBL_HIF_ROW(Index);
Position++;
}
/* Define Bank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumBankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_BANK(Index);
Position++;
}
/* Define Remaining Row positions in HIF Addresses */
RemainingRow = PDimmPtr->NumRowAddr - (BufWidth - PDimmPtr->NumColAddr - 3U);
for (Index = 0U; Index < RemainingRow; Index++) {
HifAddr[Position] = XFSBL_HIF_ROW(Index) + (BufWidth -
PDimmPtr->NumColAddr - 4U);
Position++;
}
/* Define Rank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumRankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_RANK(Index);
Position++;
}
} else {
/* First four HIF addresses are fixed for Video Mapping */
HifAddr[0U] = XFSBL_HIF_COLUMN(0U);
HifAddr[1U] = XFSBL_HIF_COLUMN(1U);
HifAddr[2U] = XFSBL_HIF_COLUMN(2U);
HifAddr[3U] = XFSBL_HIF_BG(0U);
Position = 4U;
/* Define Column positions in HIF Addresses */
for (Index = 3U; Index < PDimmPtr->NumColAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_COLUMN(Index);
Position++;
}
/* Define Row positions in HIF Addresses */
for (Index = 0U; Index < (BufWidth - PDimmPtr->NumColAddr - 4U); Index++) {
HifAddr[Position] = XFSBL_HIF_ROW(Index);
Position++;
}
/* Define Bank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumBankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_BANK(Index);
Position++;
}
/* Define Remaining Row positions in HIF Addresses */
RemainingRow = PDimmPtr->NumRowAddr - (BufWidth - PDimmPtr->NumColAddr - 4U);
for (Index = 0U; Index < RemainingRow; Index++) {
HifAddr[Position] = XFSBL_HIF_ROW(Index) + (BufWidth -
PDimmPtr->NumColAddr - 4U);
Position++;
}
/* Define Rank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumRankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_RANK(Index);
Position++;
}
}
}
#endif
#if (XFSBL_BRCMAPPING == 1U)
/*****************************************************************************/
/**
* This function calculates the HIF Addresses for Bank-Row-Column mapping mode
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param HifAddr is the pointer to the HIF Addresses Array
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrCalcHifAddrBrcMap(struct DdrcInitData *DdrDataPtr,
u32 *HifAddr)
{
u32 Position;
u32 Index;
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
/* First four HIF addresses are fixed for BRC Mapping */
HifAddr[0U] = XFSBL_HIF_COLUMN(0U);
HifAddr[1U] = XFSBL_HIF_COLUMN(1U);
HifAddr[2U] = XFSBL_HIF_COLUMN(2U);
HifAddr[3U] = XFSBL_HIF_BG(0U);
Position = 4U;
/* Define Column positions in HIF Addresses */
for (Index = 3U; Index < PDimmPtr->NumColAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_COLUMN(Index);
Position++;
}
/* Define Row positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumRowAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_ROW(Index);
Position++;
}
/* Define Bank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumBankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_BANK(Index);
Position++;
}
/* Define Rank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumRankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_RANK(Index);
Position++;
}
}
#endif
#if (XFSBL_DDR4ADDRMAPPING == 1U)
/*****************************************************************************/
/**
* This function calculates the HIF Addresses for Address Mapping Enabled mode
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param HifAddr is the pointer to the HIF Addresses Array
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrCalcHifAddrMemMap(struct DdrcInitData *DdrDataPtr, u32 *HifAddr)
{
u32 Position;
u32 Index;
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
/* First four HIF addresses are fixed for DDR4 Address Mapped Mode */
HifAddr[0U] = XFSBL_HIF_COLUMN(0U);
HifAddr[1U] = XFSBL_HIF_COLUMN(1U);
HifAddr[2U] = XFSBL_HIF_COLUMN(2U);
HifAddr[3U] = XFSBL_HIF_BG(0U);
Position = 4U;
/* Define Column positions in HIF Addresses */
for (Index = 3U; Index < PDimmPtr->NumColAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_COLUMN(Index);
Position++;
}
/* Define Bank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumBankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_BANK(Index);
Position++;
}
/* Define Row positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumRowAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_ROW(Index);
Position++;
}
/* Define Rank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumRankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_RANK(Index);
Position++;
}
}
#endif
/*****************************************************************************/
/**
* This function calculates the HIF Addresses for Non-DDR4 mode
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param HifAddr is the pointer to the HIF Addresses Array
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrCalcHifAddr(struct DdrcInitData *DdrDataPtr, u32 *HifAddr)
{
u32 Position = 0U;
u32 Index;
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
/* Define Column positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumColAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_COLUMN(Index);
Position++;
}
/* Define Bank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumBankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_BANK(Index);
Position++;
}
/* Define Row positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumRowAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_ROW(Index);
Position++;
}
/* Define Rank positions in HIF Addresses */
for (Index = 0U; Index < PDimmPtr->NumRankAddr; Index++) {
HifAddr[Position] = XFSBL_HIF_RANK(Index);
Position++;
}
}
/*****************************************************************************/
/**
* This function calculates the Bank Address Map based on HIF Addresses
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param HifAddr is the pointer to the HIF Addresses Array
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrCalcBankAddr(struct DdrcInitData *DdrDataPtr, u32 *HifAddr)
{
u32 Index;
u32 BankBit;
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
/* Calculate Bank Addresses */
for (BankBit = 0U; BankBit < XFSBL_MAX_BANKS; BankBit++) {
if (BankBit < PDimmPtr->NumBankAddr) {
Index = BankBit + 2U;
while (HifAddr[Index] != XFSBL_HIF_BANK(BankBit)) {
Index++;
}
DdrDataPtr->AddrMapBankBit[BankBit] = Index -
(BankBit + 2U);
} else {
DdrDataPtr->AddrMapBankBit[BankBit] = 0x1FU;
}
}
}
/*****************************************************************************/
/**
* This function calculates the Bank Group Address Map based on HIF Addresses
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param HifAddr is the pointer to the HIF Addresses Array
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrCalcBgAddr(struct DdrcInitData *DdrDataPtr, u32 *HifAddr)
{
u32 Index;
u32 BgBit;
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
/* Calculate Bank Group Addresses */
for (BgBit = 0U; BgBit < XFSBL_MAX_BANK_GROUPS; BgBit++) {
if (BgBit < PDimmPtr->NumBgAddr) {
Index = BgBit + 2U;
while (HifAddr[Index] != XFSBL_HIF_BG(BgBit)) {
Index++;
}
if (Index >= (BgBit + 2U)) {
DdrDataPtr->AddrMapBgBit[BgBit] = Index -
(BgBit + 2U);
} else {
DdrDataPtr->AddrMapBgBit[BgBit] = 0U;
}
} else {
DdrDataPtr->AddrMapBgBit[BgBit] = 0x1FU;
}
}
}
/*****************************************************************************/
/**
* This function calculates the Column Address Map based on HIF Addresses
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param HifAddr is the pointer to the HIF Addresses Array
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrCalcColAddr(struct DdrcInitData *DdrDataPtr, u32 *HifAddr)
{
u32 Index;
u32 ColBit;
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
/* Calculate Column Addresses */
for (ColBit = 2U; ColBit < XFSBL_MAX_COLUMNS; ColBit++) {
if (ColBit < PDimmPtr->NumColAddr) {
Index = ColBit;
while (HifAddr[Index] != XFSBL_HIF_COLUMN(ColBit)) {
Index++;
}
DdrDataPtr->AddrMapColBit[ColBit] = Index - ColBit;
} else {
DdrDataPtr->AddrMapColBit[ColBit] = 0xFU;
}
}
}
/*****************************************************************************/
/**
* This function calculates the Row Address Map based on HIF Addresses
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param HifAddr is the pointer to the HIF Addresses Array
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrCalcRowAddr(struct DdrcInitData *DdrDataPtr, u32 *HifAddr)
{
u32 Index;
u32 RowBit;
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
/* HIF address bits used as row address bits 2U to 10U */
DdrDataPtr->AddrMapRowBits2To10 = 15U;
/* Calculate Row Addresses */
for (RowBit = 0U; RowBit < XFSBL_MAX_ROWS; RowBit++) {
if (RowBit < PDimmPtr->NumRowAddr) {
Index = RowBit + 6U;
while (HifAddr[Index] != XFSBL_HIF_ROW(RowBit)) {
Index++;
}
DdrDataPtr->AddrMapRowBit[RowBit] = Index -
(RowBit + 6U);
} else {
DdrDataPtr->AddrMapRowBit[RowBit] = 0xFU;
}
}
}
/*****************************************************************************/
/**
* This function calculates the Address Mapping of the DDR
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrCalcAddrMap(struct DdrcInitData *DdrDataPtr)
{
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
u32 HifAddr[40U] = {0U};
u32 RegVal[12U];
u32 Index;
#if (XFSBL_VIDEOBUF != 0U)
/* Calculate the HIF Addresses when Video Buffers are Enabled */
XFsbl_DdrCalcHifAddrVideo(DdrDataPtr, HifAddr, VideoBuf);
#elif (XFSBL_BRCMAPPING == 1U)
if (PDimmPtr->MemType != SPD_MEMTYPE_DDR4) {
/*
* Calculate the HIF Addresses for Non-DDR4 Mapping
*/
XFsbl_DdrCalcHifAddr(DdrDataPtr, HifAddr);
} else {
/*
* Calculate the HIF Addresses when Bank-Row-Column Mapping is
* Enabled
*/
XFsbl_DdrCalcHifAddrBrcMap(DdrDataPtr, HifAddr);
}
#else
if (PDimmPtr->MemType != SPD_MEMTYPE_DDR4) {
/*
* Calculate the HIF Addresses for Non-DDR4 Mapping
*/
XFsbl_DdrCalcHifAddr(DdrDataPtr, HifAddr);
} else {
#if (XFSBL_DDR4ADDRMAPPING == 1U)
/*
* Calculate the HIF Addresses when DDR4 Address Mapping
* is Enabled
*/
XFsbl_DdrCalcHifAddrMemMap(DdrDataPtr, HifAddr);
#else
/*
* Calculate the HIF Addresses for default DDR4 Mapping
*/
XFsbl_DdrCalcDdr4HifAddr(DdrDataPtr, HifAddr);
#endif
}
#endif
if (PDimmPtr->BusWidth <= 32U) {
for (Index = 0U; Index < 39U; Index++) {
HifAddr[Index] = HifAddr[Index + 1U];
}
HifAddr[39U] = 0U;
}
if (PDimmPtr->BusWidth == 16U) {
for (Index = 0U; Index < 39U; Index++) {
HifAddr[Index] = HifAddr[Index + 1U];
}
HifAddr[39U] = 0U;
}
/* Calculate Bank Address Map based on HIF Addresses */
XFsbl_DdrCalcBankAddr(DdrDataPtr, HifAddr);
/* Calculate Column Address Map based on HIF Addresses */
XFsbl_DdrCalcColAddr(DdrDataPtr, HifAddr);
/* Calculate Row Address Map based on HIF Addresses */
XFsbl_DdrCalcRowAddr(DdrDataPtr, HifAddr);
/* Calculate Bank Group Address Map based on HIF Addresses */
XFsbl_DdrCalcBgAddr(DdrDataPtr, HifAddr);
/* Rank Width is 0U for the New DIMM */
DdrDataPtr->AddrMapCsBit0 = 0x1FU;
/* Address Map Register 0U */
RegVal[0U] = ((DdrDataPtr->AddrMapCsBit0 & 0x1FU) << 0U);
/* Address Map Register 1U */
RegVal[1U] = ((DdrDataPtr->AddrMapBankBit[2U] &
0x1FU) << 16U);
RegVal[1U] |= ((DdrDataPtr->AddrMapBankBit[1U] &
0x1FU) << 8U);
RegVal[1U] |= ((DdrDataPtr->AddrMapBankBit[0U] &
0x1FU) << 0U);
/* Address Map Register 2U */
RegVal[2U] = ((DdrDataPtr->AddrMapColBit[5U] &
0xFU) << 24U);
RegVal[2U] |= ((DdrDataPtr->AddrMapColBit[4U] &
0xFU) << 16U);
RegVal[2U] |= ((DdrDataPtr->AddrMapColBit[3U] &
0xFU) << 8U);
RegVal[2U] |= ((DdrDataPtr->AddrMapColBit[2U] &
0xFU) << 0U);
/* Address Map Register 3U */
RegVal[3U] = ((DdrDataPtr->AddrMapColBit[9U] &
0xFU) << 24U);
RegVal[3U] |= ((DdrDataPtr->AddrMapColBit[8U] &
0xFU) << 16U);
RegVal[3U] |= ((DdrDataPtr->AddrMapColBit[7U] &
0xFU) << 8U);
RegVal[3U] |= ((DdrDataPtr->AddrMapColBit[6U] &
0xFU) << 0U);
/* Address Map Register 4U */
RegVal[4U] = ((DdrDataPtr->AddrMapColBit[11U] &
0xFU) << 8U);
RegVal[4U] |= ((DdrDataPtr->AddrMapColBit[10U] &
0xFU) << 0U);
/* Address Map Register 5U */
RegVal[5U] = ((DdrDataPtr->AddrMapRowBit[11U] &
0xFU) << 24U);
RegVal[5U] |= ((DdrDataPtr->AddrMapRowBits2To10 &
0xFU) << 16U);
RegVal[5U] |= ((DdrDataPtr->AddrMapRowBit[1U] &
0xFU) << 8U);
RegVal[5U] |= ((DdrDataPtr->AddrMapRowBit[0U] &
0xFU) << 0U);
/* Address Map Register 6U */
RegVal[6U] = ((DdrDataPtr->AddrMapRowBit[15U] &
0xFU) << 24U);
RegVal[6U] |= ((DdrDataPtr->AddrMapRowBit[14U] &
0xFU) << 16U);
RegVal[6U] |= ((DdrDataPtr->AddrMapRowBit[13U] &
0xFU) << 8U);
RegVal[6U] |= ((DdrDataPtr->AddrMapRowBit[12U] &
0xFU) << 0U);
/* Address Map Register 7U */
RegVal[7U] = ((DdrDataPtr->AddrMapRowBit[17U] &
0xFU) << 8U);
RegVal[7U] |= ((DdrDataPtr->AddrMapRowBit[16U] &
0xFU) << 0U);
/* Address Map Register 8U */
RegVal[8U] = ((DdrDataPtr->AddrMapBgBit[1U] &
0x1FU) << 8U);
RegVal[8U] |= ((DdrDataPtr->AddrMapBgBit[0U] &
0x1FU) << 0U);
/* Address Map Register 9U */
RegVal[9U] = ((DdrDataPtr->AddrMapRowBit[5U] &
0xFU) << 24U);
RegVal[9U] |= ((DdrDataPtr->AddrMapRowBit[4U] &
0xFU) << 16U);
RegVal[9U] |= ((DdrDataPtr->AddrMapRowBit[3U] &
0xFU) << 8U);
RegVal[9U] |= ((DdrDataPtr->AddrMapRowBit[2U] &
0xFU) << 0U);
/* Address Map Register 10U */
RegVal[10U] = ((DdrDataPtr->AddrMapRowBit[9U] &
0xFU) << 24U);
RegVal[10U] |= ((DdrDataPtr->AddrMapRowBit[8U] &
0xFU) << 16U);
RegVal[10U] |= ((DdrDataPtr->AddrMapRowBit[7U] &
0xFU) << 8U);
RegVal[10U] |= ((DdrDataPtr->AddrMapRowBit[6U] &
0xFU) << 0U);
/* Address Map Register 11U */
RegVal[11U] = ((DdrDataPtr->AddrMapRowBit[10U] &
0xFU) << 0U);
for (Index = 0U; Index < 12U; Index ++) {
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x200U + (Index * 4U), RegVal[Index]);
}
}
/*****************************************************************************/
/**
* This function calculates the DDRC register values common to all DDR types
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param DdrCfg is the array to store register field values
*
* @return None
*
*****************************************************************************/
static u32 XFsbl_DdrcCalcCommonRegVal(struct DdrcInitData *DdrDataPtr,
XFsbl_DimmParams *PDimmPtr, u32 *DdrCfg)
{
DdrCfg[DDR_DEVICE_CONFIG] = (PDimmPtr->DramWidth >= 4U) ? XFsbl_GetLog2(PDimmPtr->DramWidth) - 2U : 0U;
DdrCfg[DDR_ACTIVE_RANKS] = (PDimmPtr->NumRankAddr * 2U) + 1U;
DdrCfg[DDR_BURST_RDWR] = PDimmPtr->BurstLength / 2U;
DdrCfg[DDR_DATA_BUS_WIDTH] = 6U - XFsbl_GetLog2(PDimmPtr->BusWidth);
DdrCfg[DDR_GEARDOWN_MODE] = PDimmPtr->Geardown;
if (!(PDimmPtr->Geardown == 1U)) {
DdrCfg[DDR_EN_2T_TIMING_MODE] = PDimmPtr->En2tTimingMode;
}
DdrCfg[DDR_RC_DERATE_VALUE] = (u32)XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod / 2.0);
DdrCfg[DDR_EN_DFI_DRAM_CLK_DISABLE] = PDimmPtr->ClockStopEn;
DdrCfg[DDR_POWERDOWN_EN] = PDimmPtr->PwrDnEn;
DdrCfg[DDR_T_DPD_X4096] = XFSBL_MIN(((u32)XFsbl_Ceil(500000.0 / (4096.0 * PDimmPtr->ClockPeriod)) + 1U), 255U);
DdrCfg[DDR_REFRESH_MODE] = PDimmPtr->Fgrm;
DdrCfg[DDR_T_RFC_MIN] = (u32)XFsbl_Ceil(((PDimmPtr->TRfcPs / 1000.0) / 2.0) / PDimmPtr->ClockPeriod);
DdrCfg[DDR_DIS_SCRUB] = PDimmPtr->EccScrub;
DdrCfg[DDR_ECC_MODE] = PDimmPtr->Ecc << 2U;
DdrCfg[DDR_DATA_POISON_EN] = PDimmPtr->EccPoison;
if (PDimmPtr->Parity | PDimmPtr->Crc) {
DdrCfg[DDR_ALERT_WAIT_FOR_SW] = 0U;
if (!PDimmPtr->NoRetry)
DdrCfg[DDR_CRC_PARITY_RETRY_ENABLE] = 1U;
}
if (PDimmPtr->Crc) {
DdrCfg[DDR_CRC_INC_DM] = 1U;
DdrCfg[DDR_CRC_ENABLE] = 1U;
}
DdrCfg[DDR_PARITY_ENABLE] = PDimmPtr->Parity;
DdrCfg[DDR_IDLE_AFTER_RESET_X32] = XFSBL_MIN(1U + ((u32)XFsbl_Ceil(1000.0 / (32.0 * PDimmPtr->ClockPeriod))), 255U);
DdrCfg[DDR_DIMM_ADDR_MIRR_EN] = PDimmPtr->AddrMirror;
DdrCfg[DDR_T_FAW] = (u32)XFsbl_Ceil((PDimmPtr->TFawPs / 1000.0) /
PDimmPtr->ClockPeriod / 2.0);
DdrCfg[DDR_T_XP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp / 2.0), 31U);
DdrCfg[DDR_T_RC] = (u32)XFsbl_Ceil((PDimmPtr->TRcPs / 1000.0) /
PDimmPtr->ClockPeriod / 2.0) + 1U;
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
PDimmPtr->WriteLatency = PDimmPtr->WriteLatency +
PDimmPtr->ParityLatency;
}
PDimmPtr->WriteLatency += PDimmPtr->RDimm;
DdrCfg[DDR_WRITE_LATENCY] = (u32)XFsbl_Ceil(PDimmPtr->WriteLatency / 2.0);
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
PDimmPtr->ReadLatency = PDimmPtr->ReadLatency + PDimmPtr->ParityLatency;
}
PDimmPtr->ReadLatency += PDimmPtr->RDimm;
DdrCfg[DDR_READ_LATENCY] = (u32)XFsbl_Ceil(PDimmPtr->ReadLatency / 2.0);
DdrCfg[DDR_T_RCD] = (u32)XFsbl_Ceil(((PDimmPtr->TRcdPs / 1000.0) -
PDimmPtr->AdditiveLatency) / 2.0) + 1U;
DdrCfg[DDR_T_CCD] = (u32)XFsbl_Ceil((PDimmPtr->TCcdlPs / 1000.0) / 2.0);
DdrCfg[DDR_T_XS_FAST_X32] = (u32)XFsbl_Ceil(((PDimmPtr->TRfc4Ps /
1000.0) + 10.0) / PDimmPtr->ClockPeriod / 32.0 / 2.0) + 1U;
DdrCfg[DDR_T_XS_ABORT_X32] = DdrCfg[DDR_T_XS_FAST_X32];
DdrCfg[DDR_DDR4_WR_PREAMBLE] = PDimmPtr->WrPreamble;
DdrCfg[DDR_T_MRD_PDA] = (u32)XFsbl_Ceil(XFSBL_MAX(16.0, 10.0 / PDimmPtr->ClockPeriod) / 2.0);
if (!PDimmPtr->DisDfiLpSr) {
DdrCfg[DDR_DFI_LP_EN_SR] = 0x1U;
}
if (!PDimmPtr->DisDfiLpPd) {
DdrCfg[DDR_DFI_LP_EN_PD] = 0x1U;
}
if (!PDimmPtr->DisDfiLpMpsm) {
DdrCfg[DDR_DFI_LP_EN_MPSM] = 0x1U;
}
DdrCfg[DDR_DIS_AUTO_CTRLUPD] = PDimmPtr->Slowboot;
if (PDimmPtr->WrDrift) {
DdrCfg[DDR_DFI_T_CTRLUP_MAX] = 0x3FFU;
}
DdrCfg[DDR_PHY_DBI_MODE] = !!PDimmPtr->PhyDbiMode;
/* Calculate Address Map for the DDR */
XFsbl_DdrCalcAddrMap(DdrDataPtr);
if (PDimmPtr->LprNumEntries != 0U) {
DdrCfg[DDR_LPR_NUM_ENTRIES] = PDimmPtr->LprNumEntries;
}
DdrCfg[DDR_DQ_NIBBLE_MAP_12_15] = PDimmPtr->Dqmap1215;
DdrCfg[DDR_DQ_NIBBLE_MAP_8_11] = PDimmPtr->Dqmap811;
DdrCfg[DDR_DQ_NIBBLE_MAP_4_7] = PDimmPtr->Dqmap47;
DdrCfg[DDR_DQ_NIBBLE_MAP_0_3] = PDimmPtr->Dqmap03;
DdrCfg[DDR_DQ_NIBBLE_MAP_28_31] = PDimmPtr->Dqmap2831;
DdrCfg[DDR_DQ_NIBBLE_MAP_24_27] = PDimmPtr->Dqmap2427;
DdrCfg[DDR_DQ_NIBBLE_MAP_20_23] = PDimmPtr->Dqmap2023;
DdrCfg[DDR_DQ_NIBBLE_MAP_16_19] = PDimmPtr->Dqmap1619;
DdrCfg[DDR_DQ_NIBBLE_MAP_44_47] = PDimmPtr->Dqmap4447;
DdrCfg[DDR_DQ_NIBBLE_MAP_40_43] = PDimmPtr->Dqmap4043;
DdrCfg[DDR_DQ_NIBBLE_MAP_36_39] = PDimmPtr->Dqmap3639;
DdrCfg[DDR_DQ_NIBBLE_MAP_32_35] = PDimmPtr->Dqmap3235;
DdrCfg[DDR_DQ_NIBBLE_MAP_60_63] = PDimmPtr->Dqmap6063;
DdrCfg[DDR_DQ_NIBBLE_MAP_56_59] = PDimmPtr->Dqmap5659;
DdrCfg[DDR_DQ_NIBBLE_MAP_52_55] = PDimmPtr->Dqmap5255;
DdrCfg[DDR_DQ_NIBBLE_MAP_48_51] = PDimmPtr->Dqmap4851;
DdrCfg[DDR_DQ_NIBBLE_MAP_CB_4_7] = PDimmPtr->Dqmap6871;
DdrCfg[DDR_DQ_NIBBLE_MAP_CB_0_3] = PDimmPtr->Dqmap6467;
return XFSBL_SUCCESS;
}
/*****************************************************************************/
/**
* This function calculates the DDRC register values for DDR4
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param DdrCfg is the array to store register field values
*
* @return None
*
*****************************************************************************/
static u32 XFsbl_DdrcCalcDdr4RegVal(XFsbl_DimmParams *PDimmPtr, u32 *DdrCfg)
{
u32 Val;
u32 Cal = 0U;
u32 Bit543 = 0U;
u32 CasLatency;
u32 Twr;
u32 Bit2;
u32 Bit654;
u32 POdt = 0U;
u32 POdi = 0U;
float FVal;
DdrCfg[DDR_DDR4] = 1U;
DdrCfg[DDR_MPSM_EN] = PDimmPtr->MaxPwrSavEn;
Val = (u32)(((PDimmPtr->TRefi / 1000.0) / 2.0 / PDimmPtr->ClockPeriod) / 32.0);
if ((PDimmPtr->RDimm || PDimmPtr->UDimm) && (PDimmPtr->NumRankAddr == 1U)) {
DdrCfg[DDR_REFRESH_TIMER1_START_VALUE_X32] = Val / 2U;
}
Val = (u32)(((PDimmPtr->TRefi / 1000.0) / 2.0 / PDimmPtr->ClockPeriod) / 32.0);
if (PDimmPtr->Fgrm == 1U) {
Val /= 2U;
} else if (PDimmPtr->Fgrm == 2U) {
Val /= 4U;
}
if (PDimmPtr->TRefRange) {
Val /= 2U;
}
if (PDimmPtr->Fgrm == 1U) {
DdrCfg[DDR_T_RFC_NOM_X32] = XFSBL_MIN(Val, 0x7FFU);
} else if (PDimmPtr->Fgrm == 2U) {
DdrCfg[DDR_T_RFC_NOM_X32] = XFSBL_MIN(Val, 0x3FFU);
} else {
DdrCfg[DDR_T_RFC_NOM_X32] = XFSBL_MIN(Val, 0xFFEU);
}
DdrCfg[DDR_T_PAR_ALERT_PW_MAX] = (u32)XFsbl_Ceil((PDimmPtr->SpeedBin * 3.0) / 100.0);
DdrCfg[DDR_T_CRC_ALERT_PW_MAX] = 5U;
DdrCfg[DDR_POST_CKE_X1024] = XFSBL_MAX(1U, (u32)XFsbl_Ceil(400.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2U) + 1U);
DdrCfg[DDR_PRE_CKE_X1024] = XFSBL_MAX(1U, (u32)XFsbl_Ceil(500000.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2U) + 1U);
DdrCfg[DDR_DRAM_RSTN_X1024] = XFSBL_MAX(((u32)XFsbl_Ceil(100.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2.0) + 1U), 1U);
CasLatency = PDimmPtr->CasLatency;
if (CasLatency <= 16U) {
Bit654 = (CasLatency - 9U) / 2U;
Bit2 = ((CasLatency - 1U) % 2U);
} else if ((CasLatency % 2U) == 1U) {
Bit654 = (CasLatency + 2U) / 6U;
Bit2 = (((CasLatency + 1U) / 2U) % 2U);
} else {
Bit654 = (CasLatency - 1U) / 4U;
Bit2 = (((CasLatency / 2U) + 1U) % 2U);
}
Twr = (u32)XFsbl_Ceil(15.0 / PDimmPtr->ClockPeriod);
if ((Twr >= 10U) || (Twr <= 24U)) {
if (Twr % 2U == 1U) {
Twr += 1U;
}
if (Twr < 24U) {
Twr = (Twr - 10U) / 2U;
} else {
Twr = 6U;
}
}
DdrCfg[DDR_MR] = XFSBL_SETBITS(Twr, 9U, 3U) + (1U << 8U) +
XFSBL_SETBITS(Bit654, 4U, 3U) + (Bit2 << 2U) +
XFSBL_SETBITS(((PDimmPtr->BurstLength == 4U) ? 2U : 0U), 0U, 2U);
switch (PDimmPtr->DramOdt) {
case 60U:
POdt = 1U;
break;
case 120U:
POdt = 2U;
break;
case 40U:
POdt = 3U;
break;
case 240U:
POdt = 4U;
break;
case 48U:
POdt = 5U;
break;
case 80U:
POdt = 6U;
break;
case 34U:
POdt = 7U;
break;
default:
POdt = 0x3U + (PDimmPtr->NumRankAddr * 2U);
break;
}
POdi = (PDimmPtr->DramDrv == 48U) ? 1U : 0U;
DdrCfg[DDR_EMR] = XFSBL_SETBITS(POdt, 8U, 3U) +
XFSBL_SETBITS(PDimmPtr->AdditiveLatency, 3U, 2U) +
XFSBL_SETBITS(POdi, 1U, 2U) + 1U;
if (PDimmPtr->TRefRange)
PDimmPtr->LpAsr = 0x3U;
if ((PDimmPtr->CasWriteLatency >= 9U) && (PDimmPtr->CasWriteLatency <= 12U)) {
Bit543 = PDimmPtr->CasWriteLatency - 9U;
} else if ((PDimmPtr->CasWriteLatency > 12U) && (PDimmPtr->CasWriteLatency <= 18U)) {
Bit543 = (PDimmPtr->CasWriteLatency - 14U) / 2U + 4U;
} else {
Bit543 = 0U;
}
DdrCfg[DDR_EMR2] = (PDimmPtr->Crc << 12U) + XFSBL_SETBITS(PDimmPtr->LpAsr, 6U, 2U) + XFSBL_SETBITS(Bit543, 3U, 3U);
Val = (PDimmPtr->SpeedBin - 1066U) / 800U;
DdrCfg[DDR_EMR3] = XFSBL_SETBITS(Val, 9U, 2U) + XFSBL_SETBITS(PDimmPtr->Fgrm, 6U, 3U);
DdrCfg[DDR_DEV_ZQINIT_X32] = 33U;
if (!PDimmPtr->CalModeEn) {
Cal = 0U;
Val = 0U;
} else {
Cal = ((PDimmPtr->SpeedBin - 266U) / 533U) + 1U;
Val = Cal - 2U;
}
DdrCfg[DDR_MR4] = (PDimmPtr->WrPreamble << 12U) + (PDimmPtr->RdPreamble << 11U) + (PDimmPtr->MaxPwrSavEn << 1U) + XFSBL_SETBITS(Val, 6U, 3U) + (PDimmPtr->TRefMode << 3U) + (PDimmPtr->TRefRange << 2U) + (PDimmPtr->SelfRefAbort << 9U);
Val = PDimmPtr->Parity * ((PDimmPtr->SpeedBin < 2400U) ? 1U : 2U);
DdrCfg[DDR_MR5] = (PDimmPtr->RdDbi << 12U) + (PDimmPtr->WrDbi << 11U) + (PDimmPtr->DataMask << 10U) + (1U << 9U) + ((0x3U + PDimmPtr->NumRankAddr) << 6U) + Val;
Val = XFSBL_MAX(0U, XFSBL_MIN(3U, ((PDimmPtr->FreqMhz - 667U) / 266U) + 1U));
DdrCfg[DDR_MR6] = XFSBL_SETBITS(Val, 10U, 3U) + XFSBL_SETBITS((PDimmPtr->DramOdt == 60U) ? 0x13U : 0x19U, 0U, 6U);
if (PDimmPtr->RDimm) {
if (PDimmPtr->DisOpInv)
DdrCfg[DDR_DIMM_OUTPUT_INV_EN] = 0U;
else
DdrCfg[DDR_DIMM_OUTPUT_INV_EN] = 1U;
}
if ((PDimmPtr->RDimm || PDimmPtr->UDimm) && (PDimmPtr->NumRankAddr == 1U)) {
DdrCfg[DDR_DIMM_STAGGER_CS_EN] = 1U;
}
if ((PDimmPtr->WrPreamble || PDimmPtr->Crc)) {
DdrCfg[DDR_DIFF_RANK_WR_GAP] += 1U;
}
DdrCfg[DDR_DIFF_RANK_WR_GAP] = (u32)XFsbl_Ceil(DdrCfg[DDR_DIFF_RANK_WR_GAP] / 2.0) + 3U;
DdrCfg[DDR_DIFF_RANK_RD_GAP] = (u32)XFsbl_Ceil(DdrCfg[DDR_DIFF_RANK_RD_GAP] / 2.0) + 3U;
Twr = (u32)XFsbl_Ceil(15.0 / PDimmPtr->ClockPeriod);
if (PDimmPtr->Crc) {
if ((PDimmPtr->SpeedBin >= 1866U) && (PDimmPtr->SpeedBin <= 2666U)) {
Twr += (u32)XFSBL_MAX(XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod), 5U);
} else if (PDimmPtr->SpeedBin == 1600U) {
Twr += (u32)XFSBL_MAX(XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod), 4U);
}
}
DdrCfg[DDR_WR2PRE] = (u32)(PDimmPtr->WriteLatency + PDimmPtr->BurstLength / 2.0 + Twr + PDimmPtr->WrPreamble) / 2U;
if (PDimmPtr->En2tTimingMode) {
DdrCfg[DDR_WR2PRE] += 1U;
}
DdrCfg[DDR_T_RAS_MAX] = XFSBL_MAX(1U, (u32)((((9.0 * (PDimmPtr->TRefi / 1000.0)) / PDimmPtr->ClockPeriod / 1024.0)) - 1U) / 2.0);
if (PDimmPtr->En2tTimingMode) {
DdrCfg[DDR_T_RAS_MIN] = (u32)XFsbl_Ceil(((PDimmPtr->TRasPs /
1000.0) / PDimmPtr->ClockPeriod / 2.0));
} else {
DdrCfg[DDR_T_RAS_MIN] = XFsbl_Round(((PDimmPtr->TRasPs / 1000.0) /
PDimmPtr->ClockPeriod / 2.0));
}
PDimmPtr->TXp = XFSBL_MAX(4U, 6.0 / PDimmPtr->ClockPeriod) + PDimmPtr->ParityLatency;
DdrCfg[DDR_T_XP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp / 2.0), 31U);
Val = XFSBL_MAX(PDimmPtr->AdditiveLatency +
XFSBL_MAX((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 4U),
(PDimmPtr->ReadLatency + PDimmPtr->BurstLength / 2U -
(PDimmPtr->TRpPs / 1000.0)));
if (PDimmPtr->En2tTimingMode) {
DdrCfg[DDR_RD2PRE] = (u32)XFsbl_Ceil(Val / 2.0);
} else {
DdrCfg[DDR_RD2PRE] = (u32)Val / 2U;
}
DdrCfg[DDR_RD2WR] = (u32)XFsbl_Ceil((PDimmPtr->ReadLatency +
PDimmPtr->BurstLength / 2U + 2U +
PDimmPtr->WrPreamble - PDimmPtr->WriteLatency) /
2.0) + 2U;
PDimmPtr->TWtr = (u32)XFSBL_MAX(XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 4U);
if (PDimmPtr->Crc) {
if ((PDimmPtr->SpeedBin >= 1866U) && (PDimmPtr->SpeedBin <= 2666U)) {
PDimmPtr->TWtr += (u32)XFSBL_MAX(XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod), 5U);
} else if (PDimmPtr->SpeedBin == 1600U) {
PDimmPtr->TWtr += (u32)XFSBL_MAX(XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod), 4U);
}
}
Val = PDimmPtr->WriteLatency + PDimmPtr->TWtr + PDimmPtr->BurstLength / 2U + PDimmPtr->ParityLatency;
if (PDimmPtr->WrPreamble) {
Val += 2U;
}
DdrCfg[DDR_WR2RD] = (u32)XFsbl_Ceil((float)Val / 2U);
FVal = (PDimmPtr->SpeedBin < 2666U) ? 8.0 : 9.0;
if (PDimmPtr->Parity) {
FVal = XFSBL_MAX(24U, 15U / PDimmPtr->ClockPeriod) +
PDimmPtr->ParityLatency;
}
if (PDimmPtr->CalModeEn) {
FVal = XFSBL_MAX(24U, 15U / PDimmPtr->ClockPeriod) + Cal;
}
DdrCfg[DDR_T_MRD] = (u32)XFsbl_Ceil(FVal / 2.0);
PDimmPtr->TMod = XFSBL_MAX(24U, 15U / PDimmPtr->ClockPeriod) + (PDimmPtr->Parity * PDimmPtr->ParityLatency) + (PDimmPtr->CalModeEn * Cal) + PDimmPtr->RDimm;
DdrCfg[DDR_T_MOD] = (u32)XFsbl_Ceil(PDimmPtr->TMod / 2.0);
DdrCfg[DDR_T_RRD] = (u32)XFsbl_Ceil((XFSBL_MAX(XFsbl_Ceil((PDimmPtr->TRrdlPs / 1000.0) / PDimmPtr->ClockPeriod), 4U)) / 2.0);
DdrCfg[DDR_T_RP] = (u32)(XFsbl_Ceil((PDimmPtr->TRpPs / 1000.0) / 2.0) + 1U) + 1U;
DdrCfg[DDR_T_CKSRX] = (u32)XFsbl_Ceil((XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 5.0)) / 2.0);
DdrCfg[DDR_T_CKSRE] = (u32)XFsbl_Ceil((XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 5.0) + PDimmPtr->ParityLatency) / 2.0);
DdrCfg[DDR_T_CKESR] = (u32)XFsbl_Ceil((XFSBL_MAX(XFsbl_Ceil(5.0 / PDimmPtr->ClockPeriod), 3.0) + 1.0) / 2.0);
FVal = XFSBL_MAX(XFsbl_Ceil(5.0 / PDimmPtr->ClockPeriod), 3.0);
DdrCfg[DDR_T_CKE] = (u32)XFsbl_Ceil(FVal / 2.0);
DdrCfg[DDR_T_CKCSX] = (u32)XFsbl_Ceil((FVal + 2.0) / 2.0);
DdrCfg[DDR_T_CKPDE] = DdrCfg[DDR_T_CKSRE];
DdrCfg[DDR_T_CKPDX] = DdrCfg[DDR_T_CKSRX];
DdrCfg[DDR_T_XS_DLL_X32] = (u32)XFsbl_Ceil(((PDimmPtr->SpeedBin <= 1866U) ? 597.0 : ((PDimmPtr->SpeedBin <= 2400U) ? 768.0 : 1024.0)) / 32.0 / 2.0) + 1U;
DdrCfg[DDR_T_XS_X32] = (u32)XFsbl_Ceil((((PDimmPtr->TRfcPs / 1000.0) + 10U) / PDimmPtr->ClockPeriod) / 32.0 / 2.0) + 1U;
DdrCfg[DDR_T_CCD_S] = 2U;
DdrCfg[DDR_T_RRD_S] = (u32)XFsbl_Ceil(XFSBL_MAX((PDimmPtr->TRrdsPs / 1000.0) / PDimmPtr->ClockPeriod , 4U) / 2.0);
FVal = PDimmPtr->ParityLatency + PDimmPtr->WriteLatency + PDimmPtr->BurstLength / 2U + XFSBL_MAX(XFsbl_Ceil(2.5 / PDimmPtr->ClockPeriod), 2U);
if (PDimmPtr->Crc) {
FVal += XFSBL_MAX(XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod), (PDimmPtr->SpeedBin > 1600U) ? 5.0 : 4.0);
}
DdrCfg[DDR_WR2RD_S] = (u32)XFsbl_Ceil((FVal + PDimmPtr->WrPreamble) / 2.0);
FVal = PDimmPtr->ClockPeriod * ((PDimmPtr->SpeedBin <= 1866U) ? 597.0 : ((PDimmPtr->SpeedBin <= 2400U) ? 768.0 : 1024.0));
FVal = ((PDimmPtr->TRfcPs / 1000.0) + 10.0 + FVal);
DdrCfg[DDR_POST_MPSM_GAP_X32] = (u32)XFsbl_Ceil(FVal / (2.0 * 32U * PDimmPtr->ClockPeriod));
DdrCfg[DDR_T_MPX_LH] = (u32)XFsbl_Ceil(12U / PDimmPtr->ClockPeriod / 2.0);
FVal = XFSBL_MAX(24U, 15U / PDimmPtr->ClockPeriod) + 4U;
if (PDimmPtr->SpeedBin == 2666U) {
FVal += 1U;
}
if (PDimmPtr->SpeedBin == 3200U) {
FVal += 2U;
}
DdrCfg[DDR_T_CKMPE] = (u32)XFsbl_Ceil(FVal / 2U);
DdrCfg[DDR_T_ZQ_LONG_NOP] = 256U;
DdrCfg[DDR_T_ZQ_SHORT_NOP] = 64U;
DdrCfg[DDR_T_ZQ_SHORT_INTERVAL_X1024] = (u32)((100000000.0 / PDimmPtr->ClockPeriod) / 1024.0);
DdrCfg[DDR_DFI_T_RDDATA_EN] = PDimmPtr->ReadLatency - 4U + Cal - PDimmPtr->RDimm;
DdrCfg[DDR_DFI_TPHY_WRLAT] = PDimmPtr->WriteLatency - 3U + Cal - PDimmPtr->RDimm;
DdrCfg[DDR_DFI_T_CMD_LAT] = Cal;
DdrCfg[DDR_DFI_T_WRDATA_DELAY] = 3U;
DdrCfg[DDR_DFI_DATA_CS_POLARITY] = 0U;
if (PDimmPtr->DramWidth != 4U) {
if (PDimmPtr->RdDbi) {
DdrCfg[DDR_RD_DBI_EN] = 1U;
}
if (PDimmPtr->WrDbi) {
DdrCfg[DDR_WR_DBI_EN] = 1U;
}
if (PDimmPtr->DataMask) {
DdrCfg[DDR_DM_EN] = 1U;
} else {
DdrCfg[DDR_DM_EN] = 0U;
}
} else {
DdrCfg[DDR_DM_EN] = 0U;
}
DdrCfg[DDR_WR_ODT_HOLD] = (PDimmPtr->BurstLength / 2U) + 2U;
if (PDimmPtr->Crc | PDimmPtr->WrPreamble) {
DdrCfg[DDR_WR_ODT_HOLD] += 1U;
}
DdrCfg[DDR_WR_ODT_DELAY] = Cal;
DdrCfg[DDR_RD_ODT_HOLD] = 6U;
DdrCfg[DDR_RD_ODT_DELAY] = Cal + (((PDimmPtr->CasLatency -
PDimmPtr->CasWriteLatency) < 1U) ? 0U :
(PDimmPtr->CasLatency - PDimmPtr->CasWriteLatency - 1U));
DdrCfg[DDR_RANK1_WR_ODT] = 2U * PDimmPtr->NumRankAddr;
DdrCfg[DDR_RANK0_WR_ODT] = 0x1U;
if (PDimmPtr->BusWidth == 32U) {
DdrCfg[DDR_DIS_WC] = 1U;
DdrCfg[DDR_BL_EXP_MODE] = 1U;
}
return XFSBL_SUCCESS;
}
#if !(defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
|| defined(XPS_BOARD_ZCU208))
/*****************************************************************************/
/**
* This function calculates the DDRC register values for DDR3
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param DdrCfg is the array to store register field values
*
* @return None
*
*****************************************************************************/
static u32 XFsbl_DdrcCalcDdr3RegVal(XFsbl_DimmParams *PDimmPtr, u32 *DdrCfg)
{
u32 Val;
u32 BurstLength;
u32 CasLatency;
u32 Twr;
u32 Bit654;
u32 POdt = 0U;
float FVal;
DdrCfg[DDR_DDR3] = 1U;
Val = (u32)(((PDimmPtr->TRefi / 1000.0) / 2.0 / PDimmPtr->ClockPeriod) / 32.0);
if ((PDimmPtr->RDimm || PDimmPtr->UDimm) && (PDimmPtr->NumRankAddr == 1U)) {
DdrCfg[DDR_REFRESH_TIMER1_START_VALUE_X32] = Val / 2U;
}
if (PDimmPtr->TRefRange) {
Val /= 2U;
}
DdrCfg[DDR_T_RFC_NOM_X32] = XFSBL_MAX(1U, XFSBL_MIN(Val, 0xFFEU));
DdrCfg[DDR_POST_CKE_X1024] = XFSBL_MAX(1U, (u32)XFsbl_Ceil(400.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2U) + 1U);
DdrCfg[DDR_PRE_CKE_X1024] = XFSBL_MAX(1U, (u32)XFsbl_Ceil(500000.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2U) + 1U);
DdrCfg[DDR_DRAM_RSTN_X1024] = XFSBL_MAX(((u32)XFsbl_Ceil(200000.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2.0) + 1U), 1U);
BurstLength = (PDimmPtr->BurstLength == 4U) ? 2U : 0U;
CasLatency = PDimmPtr->CasLatency;
Bit654 = (CasLatency < 12U) ? CasLatency - 4U : CasLatency - 12U;
Twr = (u32)XFsbl_Ceil(15.0 / PDimmPtr->ClockPeriod);
Twr = XFSBL_MAX(5U, XFSBL_MIN(16U, Twr));
DdrCfg[DDR_MR] = XFSBL_SETBITS(((Twr < 8U) ? (Twr - 4U) : (u32)XFsbl_Ceil(Twr / 2.0)), 9U, 3U) + (1U << 8U) +
XFSBL_SETBITS(Bit654, 4U, 3U) + (((CasLatency < 12U) ? 0U : 1U) << 2U) +
XFSBL_SETBITS(BurstLength, 0U, 2U);
if (PDimmPtr->DramOdt == 60U) {
POdt = (1U << 2U);
} else if (PDimmPtr->DramOdt == 120U) {
POdt = (1U << 6U);
} else if (PDimmPtr->DramOdt == 40U) {
POdt = (1U << 6U) + (1U << 2U);
} else if (PDimmPtr->DramOdt == 20U) {
POdt = (1U << 9U);
} else if (PDimmPtr->DramOdt == 30U) {
POdt = (1U << 9U) + (1U << 2U);
} else {
if (PDimmPtr->NumRankAddr == 0U) {
POdt = (1U << 2U);
} else {
POdt = (1U << 6U);
}
}
DdrCfg[DDR_EMR] = (PDimmPtr->AdditiveLatency << 3U) + POdt + ((PDimmPtr->DramDrv == 34U) ? 0x2U : 0U);
DdrCfg[DDR_EMR2] = (PDimmPtr->NumRankAddr << 9U) + XFSBL_SETBITS((PDimmPtr->CasWriteLatency - 5U), 3U, 3U);
DdrCfg[DDR_EMR2] += (PDimmPtr->TRefRange << 7U);
DdrCfg[DDR_EMR3] = 0U;
DdrCfg[DDR_DEV_ZQINIT_X32] = (512U / 32U) + 1U;
if ((PDimmPtr->RDimm || PDimmPtr->UDimm) && (PDimmPtr->NumRankAddr == 1U)) {
DdrCfg[DDR_DIMM_STAGGER_CS_EN] = 1U;
}
DdrCfg[DDR_DIFF_RANK_WR_GAP] = (u32)XFsbl_Ceil(DdrCfg[DDR_DIFF_RANK_WR_GAP] / 2.0) + 3U;
DdrCfg[DDR_DIFF_RANK_RD_GAP] = (u32)XFsbl_Ceil(DdrCfg[DDR_DIFF_RANK_RD_GAP] / 2.0) + 3U;
Twr = (u32)XFsbl_Ceil(15.0 / PDimmPtr->ClockPeriod);
if ((PDimmPtr->MemType == SPD_MEMTYPE_DDR4) && PDimmPtr->Crc) {
if ((PDimmPtr->SpeedBin >= 1866U) && (PDimmPtr->SpeedBin <= 2666U)) {
Twr += (u32)XFSBL_MAX(XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod), 5U);
} else if (PDimmPtr->SpeedBin == 1600U) {
Twr += (u32)XFSBL_MAX(XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod), 4U);
}
}
if (PDimmPtr->WrPreamble && (PDimmPtr->MemType == SPD_MEMTYPE_DDR4)) {
Twr += 1U;
}
DdrCfg[DDR_WR2PRE] = (u32)(PDimmPtr->WriteLatency + PDimmPtr->BurstLength / 2.0 + Twr) / 2U;
if (PDimmPtr->En2tTimingMode && (PDimmPtr->MemType == SPD_MEMTYPE_DDR4)) {
DdrCfg[DDR_WR2PRE] += 1U;
}
DdrCfg[DDR_T_RAS_MAX] = (u32)XFSBL_MAX(1U, (((9.0 * (PDimmPtr->TRefi / 1000.0)) / PDimmPtr->ClockPeriod / 1024.0) - 1U) / 2.0);
if (PDimmPtr->En2tTimingMode) {
DdrCfg[DDR_T_RAS_MIN] = (u32)XFsbl_Ceil(((PDimmPtr->TRasPs /
1000.0) / PDimmPtr->ClockPeriod / 2.0));
} else {
DdrCfg[DDR_T_RAS_MIN] = XFsbl_Round(((PDimmPtr->TRasPs / 1000.0) /
PDimmPtr->ClockPeriod / 2.0));
}
PDimmPtr->TXp = XFSBL_MAX(10U, 24.0 / PDimmPtr->ClockPeriod);
DdrCfg[DDR_T_XP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp / 2.0), 31U);
if (PDimmPtr->En2tTimingMode) {
DdrCfg[DDR_RD2PRE] = (u32)XFsbl_Ceil((PDimmPtr->AdditiveLatency + XFSBL_MAX((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 4U)) / 2.0);
} else {
DdrCfg[DDR_RD2PRE] = (u32)(PDimmPtr->AdditiveLatency + XFSBL_MAX((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 4U)) / 2U;
}
DdrCfg[DDR_RD2WR] = (u32)XFsbl_Ceil((PDimmPtr->ReadLatency + (PDimmPtr->BurstLength/2U) + 2U - PDimmPtr->WriteLatency) / 2.0) + 2U;
PDimmPtr->TWtr = (u32)XFSBL_MAX(XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 4U);
DdrCfg[DDR_WR2RD] = (u32)XFsbl_Ceil((float)(PDimmPtr->WriteLatency + PDimmPtr->TWtr + PDimmPtr->BurstLength / 2U) / 2.0);
DdrCfg[DDR_T_MRD] = 0x2U;
PDimmPtr->TMod = XFSBL_MAX(12U, 15U / PDimmPtr->ClockPeriod) + PDimmPtr->RDimm;
DdrCfg[DDR_T_MOD] = (u32)XFsbl_Ceil(PDimmPtr->TMod / 2.0);
DdrCfg[DDR_T_RRD] = (u32)XFsbl_Ceil(XFSBL_MAX(XFsbl_Ceil((PDimmPtr->TRrdPs / 1000.0) / PDimmPtr->ClockPeriod), 4U) / 2.0);
DdrCfg[DDR_T_RP] = (u32)(XFsbl_Ceil((PDimmPtr->TRpPs / 1000.0) / 2.0) + 1U) + 1U;
DdrCfg[DDR_T_CKSRX] = (u32)XFsbl_Ceil(XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 5.0) / 2.0);
DdrCfg[DDR_T_CKSRE] = (u32)XFsbl_Ceil(XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 5.0) / 2.0);
DdrCfg[DDR_T_CKESR] = (u32)XFsbl_Ceil((XFSBL_MAX(XFsbl_Ceil((XFSBL_MAX(5.0, 45.0 / ((PDimmPtr->SpeedBin / 266U) + 3U))) / PDimmPtr->ClockPeriod), 3.0) + 1.0) / 2.0);
FVal = XFSBL_MAX(XFsbl_Ceil((XFSBL_MAX(5.0, 45.0 / ((PDimmPtr->SpeedBin / 266U) + 3U))) / PDimmPtr->ClockPeriod), 3.0);
DdrCfg[DDR_T_CKE] = (u32)XFsbl_Ceil(FVal / 2.0);
DdrCfg[DDR_T_CKCSX] = (u32)XFsbl_Ceil((FVal + 2.0) / 2.0);
DdrCfg[DDR_T_CKPDE] = DdrCfg[DDR_T_CKSRE];
DdrCfg[DDR_T_CKPDX] = DdrCfg[DDR_T_CKSRX];
DdrCfg[DDR_T_XS_DLL_X32] = (u32)XFsbl_Ceil(512.0 / 32.0 / 2.0) + 1U;
DdrCfg[DDR_T_XS_X32] = (u32)XFsbl_Ceil(512.0 / 32.0 / 2.0) + 1U;
DdrCfg[DDR_T_ZQ_LONG_NOP] = (u32)XFsbl_Ceil(XFSBL_MAX(256.0, 320.0 / PDimmPtr->ClockPeriod) / 2.0);
DdrCfg[DDR_T_ZQ_SHORT_NOP] = (u32)XFsbl_Ceil(XFSBL_MAX(64.0, 80.0 / PDimmPtr->ClockPeriod) / 2.0);
DdrCfg[DDR_T_ZQ_SHORT_INTERVAL_X1024] = (u32)((100000000.0 / PDimmPtr->ClockPeriod) / 1024.0);
DdrCfg[DDR_DFI_T_RDDATA_EN] = PDimmPtr->ReadLatency - 4U - PDimmPtr->RDimm;
DdrCfg[DDR_DFI_TPHY_WRLAT] = PDimmPtr->WriteLatency - 3U - PDimmPtr->RDimm;
DdrCfg[DDR_DFI_T_WRDATA_DELAY] = 2U;
DdrCfg[DDR_DFI_DATA_CS_POLARITY] = 0U;
DdrCfg[DDR_PHY_DBI_MODE] = PDimmPtr->PhyDbiMode;
DdrCfg[DDR_DM_EN] = 0U;
DdrCfg[DDR_WR_ODT_HOLD] = (PDimmPtr->BurstLength / 2U) + 3U;
DdrCfg[DDR_WR_ODT_DELAY] = 0U;
DdrCfg[DDR_RD_ODT_HOLD] = (PDimmPtr->BurstLength / 2U) + 2U;
DdrCfg[DDR_RD_ODT_DELAY] = PDimmPtr->CasLatency - PDimmPtr->CasWriteLatency;
DdrCfg[DDR_RANK1_WR_ODT] = 2U * PDimmPtr->NumRankAddr;
DdrCfg[DDR_RANK0_WR_ODT] = 0x1U;
return XFSBL_SUCCESS;
}
/*****************************************************************************/
/**
* This function calculates the DDRC register values for LPDDR3
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param DdrCfg is the array to store register field values
*
* @return None
*
*****************************************************************************/
static u32 XFsbl_DdrcCalcLpddr3RegVal(XFsbl_DimmParams *PDimmPtr, u32 *DdrCfg)
{
u32 Val;
u32 Twr;
float FVal;
DdrCfg[DDR_EN_2T_TIMING_MODE] = PDimmPtr->En2tTimingMode;
DdrCfg[DDR_LPDDR3] = 1U;
DdrCfg[DDR_DERATE_VALUE] = ((PDimmPtr->ClockPeriod / 2U) > 1.875) ? 0U : 1U;
DdrCfg[DDR_MR4_READ_INTERVAL] = (u32)(PDimmPtr->DerateIntD * 1000U / PDimmPtr->ClockPeriod / 2.0);
DdrCfg[DDR_DEEPPOWERDOWN_EN] = PDimmPtr->DeepPwrDnEn;
DdrCfg[DDR_PER_BANK_REFRESH] = PDimmPtr->PerBankRefresh;
Val = (u32)(((PDimmPtr->TRefi / 1000.0) / 2.0 / PDimmPtr->ClockPeriod) / 32.0);
if (PDimmPtr->PerBankRefresh == 0U) {
if (PDimmPtr->Capacity != 1024U) Val /= 2U;
} else {
if (PDimmPtr->Capacity >= 2048U)
Val = (u32)((487.5 / 2U / PDimmPtr->ClockPeriod) / 32.0);
else if (PDimmPtr->Capacity == 1024U)
Val = (u32)((975.0 / 2U / PDimmPtr->ClockPeriod) / 32.0);
}
if (PDimmPtr->TRefRange) {
Val /= 4U;
}
DdrCfg[DDR_T_RFC_NOM_X32] = XFSBL_MIN(Val, 0xFFEU);
DdrCfg[DDR_T_RFC_NOM_X32] = XFSBL_MAX(1U, DdrCfg[DDR_T_RFC_NOM_X32]);
DdrCfg[DDR_POST_CKE_X1024] = XFSBL_MAX(1U, (u32)XFsbl_Ceil(200000.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2U) + 1U);
DdrCfg[DDR_PRE_CKE_X1024] = XFSBL_MAX(1U, (u32)XFsbl_Ceil(100.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2U) + 1U);
Twr = (u32)XFsbl_Ceil(XFSBL_MAX(15U, 4U * PDimmPtr->ClockPeriod) / PDimmPtr->ClockPeriod);
Twr = XFSBL_MAX(6U, XFSBL_MIN(12U, Twr));
DdrCfg[DDR_MR] = XFSBL_SETBITS(((Twr < 10U) ? (Twr - 2U) : (Twr % 10U)), 5U, 3U) + XFSBL_SETBITS(3U, 0U, 3U);
Val = XFSBL_MAX(6U, XFSBL_MIN(10U, (PDimmPtr->FreqMhz / 66U) - 2U));
Twr = (u32)XFsbl_Ceil(XFSBL_MAX(15U, 4U * PDimmPtr->ClockPeriod) /
PDimmPtr->ClockPeriod);
DdrCfg[DDR_EMR] = (1U << 6U) + (((Twr >= 10U) ? 1U : 0U) << 4U) + XFSBL_SETBITS(Val, 0U, 4U);
if (PDimmPtr->DramDrv == 40U) {
Val = 2U;
} else if (PDimmPtr->DramDrv == 48U) {
Val = 3U;
} else if (PDimmPtr->DramDrv == 60U) {
Val = 4U;
} else if (PDimmPtr->DramDrv == 80U) {
Val = 6U;
} else {
Val = 1U;
}
DdrCfg[DDR_EMR2] = Val;
DdrCfg[DDR_EMR3] = 0U;
DdrCfg[DDR_DEV_ZQINIT_X32] = XFSBL_MIN(1U + ((u32)XFsbl_Ceil(1000.0 / (32.0 * PDimmPtr->ClockPeriod))), 255U);
DdrCfg[DDR_MAX_AUTO_INIT_X1024] = XFSBL_MIN(1U + ((u32)XFsbl_Ceil(10000.0 / (1024U * PDimmPtr->ClockPeriod))), 1023U);
DdrCfg[DDR_DIFF_RANK_WR_GAP] = (u32)XFsbl_Ceil(DdrCfg[DDR_DIFF_RANK_WR_GAP] / 2.0) + 3U;
DdrCfg[DDR_DIFF_RANK_RD_GAP] = (u32)XFsbl_Ceil(DdrCfg[DDR_DIFF_RANK_RD_GAP] / 2.0) + 3U;
Twr = (u32)XFsbl_Ceil(XFSBL_MAX(15.0 /
PDimmPtr->ClockPeriod, 4.0));
DdrCfg[DDR_WR2PRE] = (u32)(PDimmPtr->WriteLatency +
PDimmPtr->BurstLength / 2.0 + Twr + 1.0) / 2U;
FVal = XFSBL_MIN(9.0 * (PDimmPtr->TRefi / 1000.0), 70200.0);
FVal = (FVal / PDimmPtr->ClockPeriod / 1024.0);
FVal = (u32)(FVal - 1U) / 2.0;
DdrCfg[DDR_T_RAS_MAX] = (u32)XFSBL_MAX(1U, FVal);
if (PDimmPtr->En2tTimingMode) {
DdrCfg[DDR_T_RAS_MIN] = (u32)XFsbl_Ceil(((PDimmPtr->TRasPs /
1000.0) / PDimmPtr->ClockPeriod / 2.0));
} else {
DdrCfg[DDR_T_RAS_MIN] = XFsbl_Round(((PDimmPtr->TRasPs / 1000.0) /
PDimmPtr->ClockPeriod / 2.0));
}
PDimmPtr->TXp = XFSBL_MAX(7.5 / PDimmPtr->ClockPeriod, 3U);
DdrCfg[DDR_T_XP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp / 2.0), 31U);
Val = PDimmPtr->BurstLength / 2U + XFSBL_MAX(((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod)), 4U) - 4U;
if (PDimmPtr->En2tTimingMode) {
DdrCfg[DDR_RD2PRE] = (u32)XFsbl_Ceil(Val / 2.0);
} else {
DdrCfg[DDR_RD2PRE] = (u32)Val / 2U;
}
FVal = XFsbl_Ceil(5.5 / PDimmPtr->ClockPeriod);
DdrCfg[DDR_RD2WR] = (u32)XFsbl_Ceil((PDimmPtr->ReadLatency + PDimmPtr->BurstLength / 2U +
FVal + 1U - PDimmPtr->WriteLatency) / 2.0) + 2U;
PDimmPtr->TWtr = (u32)XFSBL_MAX(XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 4U);
DdrCfg[DDR_WR2RD] = (u32)XFsbl_Ceil((float)(PDimmPtr->WriteLatency + PDimmPtr->TWtr + (PDimmPtr->BurstLength / 2U) + 1U) / 2.0);
DdrCfg[DDR_T_MRW] = 10U;
DdrCfg[DDR_T_MRD] = (u32)XFsbl_Ceil(XFSBL_MAX(10U, 15U / PDimmPtr->ClockPeriod) / 2.0);
DdrCfg[DDR_T_RRD] = (u32)XFsbl_Ceil((XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 2U) + (1.875 * PDimmPtr->TRefRange)) / 2.0);
DdrCfg[DDR_T_RP] = (u32)(XFsbl_Ceil((PDimmPtr->TRpPs / 1000.0) / 2.0) + 1U) + 1U;
DdrCfg[DDR_T_CKSRX] = 1U;
DdrCfg[DDR_T_CKSRE] = 1U;
DdrCfg[DDR_T_CKESR] = (u32)XFsbl_Ceil((XFSBL_MAX(XFsbl_Ceil(15.0 / PDimmPtr->ClockPeriod), 3.0)) / 2.0);
DdrCfg[DDR_T_CKE] = (u32)XFsbl_Ceil((XFSBL_MAX(XFsbl_Ceil(15.0 / PDimmPtr->ClockPeriod), 3.0)) / 2.0);
DdrCfg[DDR_T_CKCSX] = (u32)XFsbl_Ceil((XFSBL_MAX(7.5 / PDimmPtr->ClockPeriod, 3.0) + 2.0) / 2.0) + 2U;
DdrCfg[DDR_T_CKPDE] = 1U;
DdrCfg[DDR_T_CKPDX] = 1U;
DdrCfg[DDR_T_XS_DLL_X32] = (u32)XFsbl_Ceil((((PDimmPtr->TRfcPs / 1000.0) + 10U) / PDimmPtr->ClockPeriod) / 32.0 / 2.0) + 1U;
DdrCfg[DDR_T_XS_X32] = (u32)XFsbl_Ceil((((PDimmPtr->TRfcPs / 1000.0) + 10U) / PDimmPtr->ClockPeriod) / 32.0 / 2.0) + 1U;
DdrCfg[DDR_ZQ_RESISTOR_SHARED] = (PDimmPtr->Ddp == 1U);
DdrCfg[DDR_T_ZQ_LONG_NOP] = (u32)XFsbl_Ceil(((360.0 / PDimmPtr->ClockPeriod)) / 2.0);
DdrCfg[DDR_T_ZQ_SHORT_NOP] = (u32)XFsbl_Ceil((90.0 / PDimmPtr->ClockPeriod) / 2.0);
DdrCfg[DDR_T_ZQ_RESET_NOP] = (u32)XFsbl_Ceil(XFSBL_MAX(3U, 50.0 / PDimmPtr->ClockPeriod) / 2.0);
DdrCfg[DDR_T_ZQ_SHORT_INTERVAL_X1024] = (u32)((400000000.0 / PDimmPtr->ClockPeriod) / 1024.0);
DdrCfg[DDR_DFI_T_RDDATA_EN] = (PDimmPtr->ReadLatency + (u32)(1.5 / PDimmPtr->ClockPeriod)) - 4U - PDimmPtr->RDimm;
DdrCfg[DDR_DFI_TPHY_WRLAT] = (PDimmPtr->WriteLatency + 1U) - 3U - PDimmPtr->RDimm;
DdrCfg[DDR_DFI_T_WRDATA_DELAY] = 2U;
DdrCfg[DDR_DFI_DATA_CS_POLARITY] = 0U;
DdrCfg[DDR_DM_EN] = 0U;
DdrCfg[DDR_WR_ODT_HOLD] = PDimmPtr->WriteLatency + 2U + (PDimmPtr->BurstLength / 2U);
DdrCfg[DDR_WR_ODT_DELAY] = 0U;
DdrCfg[DDR_RD_ODT_HOLD] = (u32)XFsbl_Ceil(5.5 / PDimmPtr->ClockPeriod) + 5U;
DdrCfg[DDR_RD_ODT_DELAY] = PDimmPtr->ReadLatency - (u32)XFsbl_Ceil(3.5 / PDimmPtr->ClockPeriod);
if (PDimmPtr->NumRankAddr == 0U) {
DdrCfg[DDR_RANK1_WR_ODT] = 0U;
} else {
if (PDimmPtr->Ddp == 1U)
DdrCfg[DDR_RANK1_WR_ODT] = 1U;
else
DdrCfg[DDR_RANK1_WR_ODT] = 2U;
}
DdrCfg[DDR_RANK0_WR_ODT] = 0x1U;
return XFSBL_SUCCESS;
}
/*****************************************************************************/
/**
* This function calculates the DDRC register values for LPDDR4
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param DdrCfg is the array to store register field values
*
* @return None
*
*****************************************************************************/
static u32 XFsbl_DdrcCalcLpddr4RegVal(XFsbl_DimmParams *PDimmPtr, u32 *DdrCfg)
{
u32 Val;
u32 Val2 = 0U;
u32 OdtLon = 0U;
float FVal;
float XVal;
DdrCfg[DDR_EN_2T_TIMING_MODE] = PDimmPtr->En2tTimingMode;
DdrCfg[DDR_LPDDR4] = 1U;
DdrCfg[DDR_DERATE_VALUE] = ((PDimmPtr->ClockPeriod / 2U) > 1.875) ? 0U : 1U;
DdrCfg[DDR_MR4_READ_INTERVAL] = (u32)(PDimmPtr->DerateIntD * 1000U / PDimmPtr->ClockPeriod / 2.0);
DdrCfg[DDR_PER_BANK_REFRESH] = PDimmPtr->PerBankRefresh;
Val = (u32)(((3904U / ((PDimmPtr->PerBankRefresh != 0U) ? 8U : 1U)) / 2U / PDimmPtr->ClockPeriod) / 32.0);
if (PDimmPtr->TRefRange) {
Val /= 4U;
}
DdrCfg[DDR_T_RFC_NOM_X32] = XFSBL_MIN(Val, 0xFFEU);
DdrCfg[DDR_T_RFC_NOM_X32] = XFSBL_MAX(1U, DdrCfg[DDR_T_RFC_NOM_X32]);
DdrCfg[DDR_POST_CKE_X1024] = XFSBL_MAX(1U, (u32)XFsbl_Ceil(2000.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2U) + 1U);
DdrCfg[DDR_PRE_CKE_X1024] = XFSBL_MAX(1U, (u32)XFsbl_Ceil(2000000.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2U) + 1U);
DdrCfg[DDR_DRAM_RSTN_X1024] = XFSBL_MAX(((u32)XFsbl_Ceil(200000.0 / (PDimmPtr->ClockPeriod * 1024.0) / 2.0) + 1U), 1U);
DdrCfg[DDR_MR] = XFSBL_SETBITS((u32)XFSBL_MAX(0U, ((PDimmPtr->FreqMhz / 266U) - 1U)), 4U, 3U) + XFSBL_SETBITS(1U, 2U, 1U) + (PDimmPtr->RdPostamble << 7U);
Val = XFSBL_MAX(0U, ((PDimmPtr->FreqMhz / 266U) - 1U));
DdrCfg[DDR_EMR] = (((PDimmPtr->UseSetB) ? 1U : 0U) << 6U) + XFSBL_SETBITS(Val, 3U, 3U) + XFSBL_SETBITS(Val, 0U, 3U);
if (PDimmPtr->DramDrv == 240U) {
Val = 1U;
} else if (PDimmPtr->DramDrv == 120U) {
Val = 2U;
} else if (PDimmPtr->DramDrv == 80U) {
Val = 3U;
} else if (PDimmPtr->DramDrv == 60U) {
Val = 4U;
} else if (PDimmPtr->DramDrv == 48U) {
Val = 5U;
} else {
Val = 6U;
}
DdrCfg[DDR_EMR2] = (PDimmPtr->WrDbi << 7U) + (PDimmPtr->RdDbi << 6U) + XFSBL_SETBITS(Val, 3U, 3U) + (PDimmPtr->WrPostamble << 1U) + 1U;
DdrCfg[DDR_EMR3] = (((PDimmPtr->DataMask) ? 0U : 1U) << 5U) + (1U << 3U);
DdrCfg[DDR_DEV_ZQINIT_X32] = (1024U / 32U) + 1U;
DdrCfg[DDR_DIFF_RANK_WR_GAP] += (1U + PDimmPtr->WrPostamble);
DdrCfg[DDR_DIFF_RANK_WR_GAP] = (u32)XFsbl_Ceil(DdrCfg[DDR_DIFF_RANK_WR_GAP] / 2.0) + 3U;
DdrCfg[DDR_DIFF_RANK_RD_GAP] += (1U + PDimmPtr->RdPostamble);
DdrCfg[DDR_DIFF_RANK_RD_GAP] = (u32)XFsbl_Ceil(DdrCfg[DDR_DIFF_RANK_RD_GAP] / 2.0) + 3U;
DdrCfg[DDR_WR2PRE] = (u32)XFsbl_Ceil((PDimmPtr->WriteLatency + (PDimmPtr->BurstLength / 2.0) + ((u32)XFsbl_Ceil(XFSBL_MAX(18.0 / PDimmPtr->ClockPeriod, 4.0))) + 1.0) / 2U);
DdrCfg[DDR_T_RAS_MAX] = (u32)XFSBL_MAX(1U, ((u32)(((XFSBL_MIN(9.0 * (PDimmPtr->TRefi / 1000.0), 70200.0)) / PDimmPtr->ClockPeriod / 1024.0) - 1U) / 2.0));
DdrCfg[DDR_T_RAS_MIN] = (u32)XFsbl_Ceil(((PDimmPtr->TRasPs / 1000.0) / PDimmPtr->ClockPeriod / 2.0));
PDimmPtr->TXp = XFSBL_MAX(7.5 / PDimmPtr->ClockPeriod, 5U);
DdrCfg[DDR_T_XP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp / 2.0), 31U);
DdrCfg[DDR_RD2PRE] = (u32)(PDimmPtr->BurstLength / 2U + XFSBL_MAX((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 8U) - 8U) / 2U;
DdrCfg[DDR_RD2PRE] = (u32)XFsbl_Ceil(Val / 2.0);
if (PDimmPtr->FreqMhz <= 800U) {
OdtLon = PDimmPtr->UseSetB * 6U;
} else {
OdtLon = (PDimmPtr->FreqMhz / 533U) * 2U;
}
FVal = XFsbl_Ceil(3.6 / PDimmPtr->ClockPeriod);
if (PDimmPtr->Lpddr4Hynix == 1U) {
XVal = PDimmPtr->ReadLatency + PDimmPtr->BurstLength / 2U +
FVal + 2U - OdtLon - XFsbl_Ceil(1.5 /
PDimmPtr->ClockPeriod) + (6U) +
(PDimmPtr->WriteLatency - PDimmPtr->WdqsOn);
} else {
XVal = PDimmPtr->ReadLatency + PDimmPtr->BurstLength / 2U +
FVal + 2U - OdtLon - XFsbl_Ceil(1.5 /
PDimmPtr->ClockPeriod);
}
if (PDimmPtr->RdPostamble == 0U) {
XVal = XVal + 0.5;
} else if (PDimmPtr->RdPostamble == 1U) {
XVal = XVal + 1.5;
}
DdrCfg[DDR_RD2WR] = (u32)XFsbl_Ceil(XVal / 2.0) + 2U;
PDimmPtr->TWtr = (u32)XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 8U);
Val = PDimmPtr->WriteLatency + PDimmPtr->TWtr + PDimmPtr->BurstLength / 2U;
if ((PDimmPtr->Lpddr4Hynix == 1U) &&
(PDimmPtr->NumRankAddr == 1U)) {
Val2 = PDimmPtr->WdqsOff - PDimmPtr->WriteLatency -
PDimmPtr->BurstLength / 2U - (2U);
Val += Val2;
}
DdrCfg[DDR_WR2RD] = (u32)XFsbl_Ceil((float)(Val + 1U) / 2U);
DdrCfg[DDR_T_MRW] = (u32)XFSBL_MAX(XFsbl_Ceil(14.0 / PDimmPtr->ClockPeriod), 10U);
DdrCfg[DDR_T_MRD] = (u32)XFsbl_Ceil((XFSBL_MAX(14.0 / PDimmPtr->ClockPeriod, 10U)) / 2.0);
DdrCfg[DDR_T_RRD] = (u32)XFsbl_Ceil((XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 4U) + (1.875 * PDimmPtr->TRefRange)) / 2.0);
DdrCfg[DDR_T_RP] = (u32)XFsbl_Ceil((PDimmPtr->TRpPs / 1000.0) / 2.0);
DdrCfg[DDR_T_CKSRX] = 1U;
DdrCfg[DDR_T_CKSRE] = (u32)XFsbl_Ceil(XFSBL_MAX(7.5 / PDimmPtr->ClockPeriod, 3U) / 2.0);
DdrCfg[DDR_T_CKESR] = (u32)XFsbl_Ceil(XFSBL_MAX(15U / PDimmPtr->ClockPeriod, 4U) / 2.0);
DdrCfg[DDR_T_CKE] = (u32)XFsbl_Ceil(XFSBL_MAX(15U / PDimmPtr->ClockPeriod, 4U) / 2.0);
DdrCfg[DDR_T_CKCSX] = (u32)XFsbl_Ceil((XFSBL_MAX(7.5 / PDimmPtr->ClockPeriod, 5.0) + 2.0) / 2.0);
DdrCfg[DDR_T_CKPDE] = (u32)XFsbl_Ceil(XFSBL_MAX(7.5 / PDimmPtr->ClockPeriod, 3.0) / 2.0);
DdrCfg[DDR_T_CKPDX] = 1U;
DdrCfg[DDR_T_XS_DLL_X32] = (u32)XFsbl_Ceil((((PDimmPtr->TRfcPs / 1000.0) + 7.5) / PDimmPtr->ClockPeriod) / 32.0 / 2.0) + 1U;
DdrCfg[DDR_T_XS_X32] = (u32)XFsbl_Ceil((((PDimmPtr->TRfcPs / 1000.0) + 7.5) / PDimmPtr->ClockPeriod) / 32.0 / 2.0) + 1U;
if (PDimmPtr->SpeedBin >= 3200U) {
DdrCfg[DDR_T_CMDCKE] = 1U;
DdrCfg[DDR_T_CKEHCMD] = (u32)XFsbl_Ceil(XFSBL_MAX(7.5 / PDimmPtr->ClockPeriod, 3.0) / 2.0);
}
DdrCfg[DDR_T_ZQ_LONG_NOP] = (u32)XFsbl_Ceil((1000.0 / PDimmPtr->ClockPeriod) / 2.0);
DdrCfg[DDR_T_ZQ_SHORT_NOP] = (u32)XFsbl_Ceil(XFSBL_MAX(30.0 / PDimmPtr->ClockPeriod, 8U) / 2.0);
DdrCfg[DDR_T_ZQ_RESET_NOP] = (u32)XFsbl_Ceil(XFSBL_MAX(3U, 50.0 / PDimmPtr->ClockPeriod) / 2.0);
DdrCfg[DDR_T_ZQ_SHORT_INTERVAL_X1024] = (u32)((400000000.0 / PDimmPtr->ClockPeriod) / 1024.0);
Val = (PDimmPtr->SpeedBin >= 1600U) ? ((u32)(1.5 / PDimmPtr->ClockPeriod)) : 1U;
DdrCfg[DDR_DFI_T_RDDATA_EN] = (PDimmPtr->ReadLatency + Val) - 4U - PDimmPtr->RDimm;
DdrCfg[DDR_DFI_TPHY_WRLAT] = (PDimmPtr->WriteLatency + 1U) - 3U - PDimmPtr->RDimm;
DdrCfg[DDR_DFI_T_WRDATA_DELAY] = 3U;
DdrCfg[DDR_DFI_DATA_CS_POLARITY] = 1U;
DdrCfg[DDR_RD_DBI_EN] = PDimmPtr->RdDbi;
DdrCfg[DDR_WR_DBI_EN] = PDimmPtr->WrDbi;
DdrCfg[DDR_DM_EN] = PDimmPtr->DataMask;
DdrCfg[DDR_RANK1_WR_ODT] = 0U;
DdrCfg[DDR_RANK0_WR_ODT] = 0x0U;
return XFSBL_SUCCESS;
}
#endif
/*****************************************************************************/
/**
* This function writes the DDRC registers with calculated values
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param DdrCfg is the array to store register field values
*
* @return None
*
*****************************************************************************/
static void XFsbl_DdrcRegsWrite(XFsbl_DimmParams *PDimmPtr, u32 *DdrCfg)
{
u32 Val;
Val = ((DdrCfg[DDR_DEVICE_CONFIG] & 0x3U) << 30U)
+ ((DdrCfg[DDR_FREQUENCY_MODE] & 0x1U) << 29U)
+ ((DdrCfg[DDR_ACTIVE_RANKS] & 0x3U) << 24U)
+ ((DdrCfg[DDR_BURST_RDWR] & 0xFU) << 16U)
+ ((DdrCfg[DDR_DLL_OFF_MODE] & 0x1U) << 15U)
+ ((DdrCfg[DDR_DATA_BUS_WIDTH] & 0x3U) << 12U)
+ ((DdrCfg[DDR_GEARDOWN_MODE] & 0x1U) << 11U)
+ ((DdrCfg[DDR_EN_2T_TIMING_MODE] & 0x1U) << 10U)
+ ((DdrCfg[DDR_BURSTCHOP] & 0x1U) << 9U)
+ ((DdrCfg[DDR_LPDDR4] & 0x1U) << 5U)
+ ((DdrCfg[DDR_DDR4] & 0x1U) << 4U)
+ ((DdrCfg[DDR_LPDDR3] & 0x1U) << 3U)
+ ((DdrCfg[DDR_LPDDR2] & 0x1U) << 2U)
+ ((DdrCfg[DDR_DDR3] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x0U, Val);
Val = ((DdrCfg[DDR_MR_WR] & 0x1U) << 31U)
+ ((DdrCfg[DDR_MR_ADDR] & 0xFU) << 12U)
+ ((DdrCfg[DDR_MR_RANK] & 0x3U) << 4U)
+ ((DdrCfg[DDR_PDA_EN] & 0x1U) << 2U)
+ ((DdrCfg[DDR_MPR_EN] & 0x1U) << 1U)
+ ((DdrCfg[DDR_MR_TYPE] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x10U, Val);
Val = ((DdrCfg[DDR_RC_DERATE_VALUE] & 0x3U) << 8U)
+ ((DdrCfg[DDR_DERATE_BYTE] & 0xFU) << 4U)
+ ((DdrCfg[DDR_DERATE_VALUE] & 0x1U) << 1U)
+ ((DdrCfg[DDR_DERATE_ENABLE] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x20U, Val);
Val = ((DdrCfg[DDR_MR4_READ_INTERVAL] & 0xFFFFFFFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x24U, Val);
Val = ((DdrCfg[DDR_STAY_IN_SELFREF] & 0x1U) << 6U)
+ ((DdrCfg[DDR_SELFREF_SW] & 0x1U) << 5U)
+ ((DdrCfg[DDR_MPSM_EN] & 0x1U) << 4U)
+ ((DdrCfg[DDR_EN_DFI_DRAM_CLK_DISABLE] & 0x1U) << 3U)
+ ((DdrCfg[DDR_DEEPPOWERDOWN_EN] & 0x1U) << 2U)
+ ((DdrCfg[DDR_POWERDOWN_EN] & 0x1U) << 1U)
+ ((DdrCfg[DDR_SELFREF_EN] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x30U, Val);
Val = ((DdrCfg[DDR_SELFREF_TO_X32] & 0xFFU) << 16U)
+ ((DdrCfg[DDR_T_DPD_X4096] & 0xFFU) << 8U)
+ ((DdrCfg[DDR_POWERDOWN_TO_X32] & 0x1FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x34U, Val);
Val = ((DdrCfg[DDR_REFRESH_MARGIN] & 0xFU) << 20U)
+ ((DdrCfg[DDR_REFRESH_TO_X32] & 0x1FU) << 12U)
+ ((DdrCfg[DDR_REFRESH_BURST] & 0x1FU) << 4U)
+ ((DdrCfg[DDR_PER_BANK_REFRESH] & 0x1U) << 2U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x50U, Val);
Val = ((DdrCfg[DDR_REFRESH_TIMER1_START_VALUE_X32] & 0xFFFU) << 16U)
+ ((DdrCfg[DDR_REFRESH_TIMER0_START_VALUE_X32] & 0xFFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x54U, Val);
Val = ((DdrCfg[DDR_REFRESH_MODE] & 0x7U) << 4U)
+ ((DdrCfg[DDR_REFRESH_UPDATE_LEVEL] & 0x1U) << 1U)
+ ((0x1U << 0U));
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x60U, Val);
Val = ((DdrCfg[DDR_T_RFC_NOM_X32] & 0xFFFU) << 16U)
+ ((0x1U) << 15U)
+ ((DdrCfg[DDR_T_RFC_MIN] & 0x3FFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x64U, Val);
Val = ((DdrCfg[DDR_DIS_SCRUB] & 0x1U) << 4U)
+ ((DdrCfg[DDR_ECC_MODE] & 0x7U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x70U, Val);
Val = ((DdrCfg[DDR_DATA_POISON_BIT] & 0x1U) << 1U)
+ ((DdrCfg[DDR_DATA_POISON_EN] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x74U, Val);
Val = ((DdrCfg[DDR_DFI_T_PHY_RDLAT] & 0x3FU) << 24U)
+ ((DdrCfg[DDR_ALERT_WAIT_FOR_SW] & 0x1U) << 9U)
+ ((DdrCfg[DDR_CRC_PARITY_RETRY_ENABLE] & 0x1U) << 8U)
+ ((DdrCfg[DDR_CRC_INC_DM] & 0x1U) << 7U)
+ ((DdrCfg[DDR_CRC_ENABLE] & 0x1U) << 4U)
+ ((DdrCfg[DDR_PARITY_ENABLE] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xC4U, Val);
Val = ((DdrCfg[DDR_T_PAR_ALERT_PW_MAX] & 0x1FFU) << 16U)
+ ((DdrCfg[DDR_T_CRC_ALERT_PW_MAX] & 0x1FU) << 8U)
+ ((0x1FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xC8U, Val);
Val = ((DdrCfg[DDR_SKIP_DRAM_INIT] & 0x3U) << 30U)
+ ((DdrCfg[DDR_POST_CKE_X1024] & 0x3FFU) << 16U)
+ ((DdrCfg[DDR_PRE_CKE_X1024] & 0xFFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xD0U, Val);
Val = ((DdrCfg[DDR_DRAM_RSTN_X1024] & 0x1FFU) << 16U)
+ ((DdrCfg[DDR_FINAL_WAIT_X32] & 0x7FU) << 8U)
+ ((DdrCfg[DDR_PRE_OCD_X32] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xD4U, Val);
Val = ((DdrCfg[DDR_IDLE_AFTER_RESET_X32] & 0xFFU) << 8U)
+ ((DdrCfg[DDR_MIN_STABLE_CLOCK_X1] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xD8U, Val);
Val = ((DdrCfg[DDR_MR] & 0xFFFFU) << 16U)
+ ((DdrCfg[DDR_EMR] & 0xFFFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xDCU, Val);
Val = ((DdrCfg[DDR_EMR2] & 0xFFFFU) << 16U)
+ ((DdrCfg[DDR_EMR3] & 0xFFFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xE0U, Val);
Val = ((DdrCfg[DDR_DEV_ZQINIT_X32] & 0xFFU) << 16U)
+ ((DdrCfg[DDR_MAX_AUTO_INIT_X1024] & 0x3FFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xE4U, Val);
Val = ((DdrCfg[DDR_MR4] & 0xFFFFU) << 16U)
+ ((DdrCfg[DDR_MR5] & 0xFFFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xE8U, Val);
Val = ((DdrCfg[DDR_MR6] & 0xFFFFU) << 16U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xECU, Val);
Val = ((DdrCfg[DDR_DIMM_DIS_BG_MIRRORING] & 0x1U) << 5U)
+ ((0x1U) << 4U)
+ ((DdrCfg[DDR_MRS_A17_EN] & 0x1U) << 3U)
+ ((DdrCfg[DDR_DIMM_OUTPUT_INV_EN] & 0x1U) << 2U)
+ ((DdrCfg[DDR_DIMM_ADDR_MIRR_EN] & 0x1U) << 1U)
+ ((DdrCfg[DDR_DIMM_STAGGER_CS_EN] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xF0U, Val);
Val = ((DdrCfg[DDR_DIFF_RANK_WR_GAP] & 0xFU) << 8U)
+ ((DdrCfg[DDR_DIFF_RANK_RD_GAP] & 0xFU) << 4U)
+ ((DdrCfg[DDR_MAX_RANK_RD] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xF4U, Val);
Val = ((DdrCfg[DDR_WR2PRE] & 0x7FU) << 24U)
+ ((DdrCfg[DDR_T_FAW] & 0x3FU) << 16U)
+ ((DdrCfg[DDR_T_RAS_MAX] & 0x7FU) << 8U)
+ ((DdrCfg[DDR_T_RAS_MIN] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x100U, Val);
Val = ((DdrCfg[DDR_T_XP] & 0x1FU) << 16U)
+ ((DdrCfg[DDR_RD2PRE] & 0x1FU) << 8U)
+ ((DdrCfg[DDR_T_RC] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x104U, Val);
Val = ((DdrCfg[DDR_WRITE_LATENCY] & 0x3FU) << 24U)
+ ((DdrCfg[DDR_READ_LATENCY] & 0x3FU) << 16U)
+ ((DdrCfg[DDR_RD2WR] & 0x3FU) << 8U)
+ ((DdrCfg[DDR_WR2RD] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x108U, Val);
Val = ((DdrCfg[DDR_T_MRW] & 0x3FFU) << 20U)
+ ((DdrCfg[DDR_T_MRD] & 0x3FU) << 12U)
+ ((DdrCfg[DDR_T_MOD] & 0x3FFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x10CU, Val);
Val = ((DdrCfg[DDR_T_RCD] & 0x1FU) << 24U)
+ ((DdrCfg[DDR_T_CCD] & 0xFU) << 16U)
+ ((DdrCfg[DDR_T_RRD] & 0xFU) << 8U)
+ ((DdrCfg[DDR_T_RP] & 0x1FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x110U, Val);
Val = ((DdrCfg[DDR_T_CKSRX] & 0xFU) << 24U)
+ ((DdrCfg[DDR_T_CKSRE] & 0xFU) << 16U)
+ ((DdrCfg[DDR_T_CKESR] & 0x3FU) << 8U)
+ ((DdrCfg[DDR_T_CKE] & 0x1FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x114U, Val);
Val = ((0x1U & 0xfU) << 24U)
+ ((0x1U & 0xfU) << 16U)
+ ((DdrCfg[DDR_T_CKCSX] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x118U, Val);
Val = ((DdrCfg[DDR_T_CKPDE] & 0xFU) << 8U)
+ ((DdrCfg[DDR_T_CKPDX] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x11CU, Val);
Val = ((DdrCfg[DDR_T_XS_FAST_X32] & 0x7FU) << 24U)
+ ((DdrCfg[DDR_T_XS_ABORT_X32] & 0x7FU) << 16U)
+ ((DdrCfg[DDR_T_XS_DLL_X32] & 0x7FU) << 8U)
+ ((DdrCfg[DDR_T_XS_X32] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x120U, Val);
Val = ((DdrCfg[DDR_DDR4_WR_PREAMBLE] & 0x1U) << 30U)
+ ((DdrCfg[DDR_T_CCD_S] & 0x7U) << 16U)
+ ((DdrCfg[DDR_T_RRD_S] & 0xFU) << 8U)
+ ((DdrCfg[DDR_WR2RD_S] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x124U, Val);
Val = ((DdrCfg[DDR_POST_MPSM_GAP_X32] & 0x7FU) << 24U)
+ ((DdrCfg[DDR_T_MPX_LH] & 0x1FU) << 16U)
+ ((0x1U & 0x3U) << 8U)
+ ((DdrCfg[DDR_T_CKMPE] & 0x1FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x12CU, Val);
Val = ((DdrCfg[DDR_T_CMDCKE] & 0x3U) << 16U)
+ ((DdrCfg[DDR_T_CKEHCMD] & 0xFU) << 8U)
+ ((DdrCfg[DDR_T_MRD_PDA] & 0x1FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x130U, Val);
Val = ((0x1U) << 31U)
+ ((DdrCfg[DDR_DIS_SRX_ZQCL] & 0x1U) << 30U)
+ ((DdrCfg[DDR_ZQ_RESISTOR_SHARED] & 0x1U) << 29U)
+ ((DdrCfg[DDR_DIS_MPSMX_ZQCL] & 0x1U) << 28U)
+ ((DdrCfg[DDR_T_ZQ_LONG_NOP] & 0x7FFU) << 16U)
+ ((DdrCfg[DDR_T_ZQ_SHORT_NOP] & 0x3FFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x180U, Val);
Val = ((DdrCfg[DDR_T_ZQ_RESET_NOP] & 0x3FFU) << 20U)
+ ((DdrCfg[DDR_T_ZQ_SHORT_INTERVAL_X1024] & 0xFFFFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x184U, Val);
Val = ((0x4U & 0x1fU) << 24U)
+ ((0x1U) << 23U)
+ ((DdrCfg[DDR_DFI_T_RDDATA_EN] & 0x3FU) << 16U)
+ ((0x1U) << 15U)
+ ((0x2U & 0x3fU) << 8U)
+ ((DdrCfg[DDR_DFI_TPHY_WRLAT] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x190U, Val);
Val = ((DdrCfg[DDR_DFI_T_CMD_LAT] & 0xFU) << 28U)
+ ((DdrCfg[DDR_DFI_T_WRDATA_DELAY] & 0x1FU) << 16U)
+ ((0x3U & 0xfU) << 8U)
+ ((0x4U & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x194U, Val);
Val = ((0x7U & 0xfU) << 24U)
+ ((DdrCfg[DDR_DFI_LP_WAKEUP_DPD] & 0xFU) << 20U)
+ ((DdrCfg[DDR_DFI_LP_EN_DPD] & 0x1U) << 16U)
+ ((DdrCfg[DDR_DFI_LP_EN_SR] & 0x1U) << 8U)
+ ((DdrCfg[DDR_DFI_LP_EN_PD] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x198U, Val);
Val = ((0x2U & 0xfU) << 4U)
+ ((DdrCfg[DDR_DFI_LP_EN_MPSM] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x19CU, Val);
Val = ((DdrCfg[DDR_DIS_AUTO_CTRLUPD] & 0x1U) << 31U)
+ ((DdrCfg[DDR_DIS_AUTO_CTRLUPD_SRX] & 0x1U) << 30U)
+ ((DdrCfg[DDR_DFI_T_CTRLUP_MAX] & 0x3FFU) << 16U)
+ ((DdrCfg[DDR_DFI_T_CTRLUP_MIN] & 0x3FFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x1A0U, Val);
Val = ((200U & 0xFFU) << 16U)
+ ((255U & 0xFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x1A4U, Val);
Val = ((DdrCfg[DDR_DFI_DATA_CS_POLARITY] & 0x1U) << 2U)
+ ((DdrCfg[DDR_PHY_DBI_MODE] & 0x1U) << 1U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x1B0U, Val);
Val = ((DdrCfg[DDR_DFI_TPHY_RDCSLAT] & 0x3FU) << 8U)
+ ((DdrCfg[DDR_DFI_TPHY_WRCSLAT] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x1B4U, Val);
Val = ((DdrCfg[DDR_RD_DBI_EN] & 0x1U) << 2U)
+ ((DdrCfg[DDR_WR_DBI_EN] & 0x1U) << 1U)
+ ((DdrCfg[DDR_DM_EN] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x1C0U, Val);
Val = ((DdrCfg[DDR_WR_ODT_HOLD] & 0xFU) << 24U)
+ ((DdrCfg[DDR_WR_ODT_DELAY] & 0x1FU) << 16U)
+ ((DdrCfg[DDR_RD_ODT_HOLD] & 0xFU) << 8U)
+ ((DdrCfg[DDR_RD_ODT_DELAY] & 0x1FU) << 2U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x240U, Val);
Val = ((DdrCfg[DDR_RANK1_WR_ODT] & 0x3U) << 8U)
+ ((DdrCfg[DDR_RANK0_WR_ODT] & 0x3U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x244U, Val);
Val = ((0x1U & 0x7fU) << 24U)
+ ((DdrCfg[DDR_GO2CRITICAL_HYSTERESIS] & 0xFFU) << 16U)
+ ((DdrCfg[DDR_LPR_NUM_ENTRIES] & 0x3FU) << 8U)
+ ((DdrCfg[DDR_PREFER_WRITE] & 0x1U) << 1U)
+ ((DdrCfg[DDR_FORCE_LOW_PRI_N] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x250U, Val);
Val = ((0x8U & 0xffU) << 24U)
+ ((64U & 0xFFFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x264U, Val);
Val = ((0x8U & 0xffU) << 24U)
+ ((0x40U & 0xffffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x26CU, Val);
Val = ((DdrCfg[DDR_DQ_NIBBLE_MAP_12_15] & 0xFFU) << 24U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_8_11] & 0xFFU) << 16U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_4_7] & 0xFFU) << 8U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_0_3] & 0xFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x280U, Val);
Val = ((DdrCfg[DDR_DQ_NIBBLE_MAP_28_31] & 0xFFU) << 24U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_24_27] & 0xFFU) << 16U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_20_23] & 0xFFU) << 8U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_16_19] & 0xFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x284U, Val);
Val = ((DdrCfg[DDR_DQ_NIBBLE_MAP_44_47] & 0xFFU) << 24U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_40_43] & 0xFFU) << 16U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_36_39] & 0xFFU) << 8U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_32_35] & 0xFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x288U, Val);
Val = ((DdrCfg[DDR_DQ_NIBBLE_MAP_60_63] & 0xFFU) << 24U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_56_59] & 0xFFU) << 16U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_52_55] & 0xFFU) << 8U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_48_51] & 0xFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x28CU, Val);
Val = ((DdrCfg[DDR_DQ_NIBBLE_MAP_CB_4_7] & 0xFFU) << 8U)
+ ((DdrCfg[DDR_DQ_NIBBLE_MAP_CB_0_3] & 0xFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x290U, Val);
Val = ((0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x294U, Val);
Val = ((DdrCfg[DDR_DIS_COLLISION_PAGE_OPT] & 0x1U) << 4U)
+ ((DdrCfg[DDR_DIS_WC] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x300U, Val);
Val = ((DdrCfg[DDR_CTRLUPD] & 0x1U) << 5U)
+ ((DdrCfg[DDR_ZQ_CALIB_SHORT] & 0x1U) << 4U)
+ ((DdrCfg[DDR_RANK1_REFRESH] & 0x1U) << 1U)
+ ((DdrCfg[DDR_RANK0_REFRESH] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x30CU, Val);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x320U, 0x0U);
Val = ((DdrCfg[DDR_BL_EXP_MODE] & 0x1U) << 8U)
+ ((DdrCfg[DDR_PAGEMATCH_LIMIT] & 0x1U) << 4U)
+ ((0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x400U, Val);
Val = ((0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x404U, Val);
Val = ((0x1U & 0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x408U, Val);
Val = ((0x1U & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x490U, Val);
Val = ((0x2U & 0x3U) << 20U)
+ ((0xBU & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x494U, Val);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x498U, 0x0U);
Val = ((0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x4B4U, Val);
Val = ((0x1U & 0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x4B8U, Val);
Val = ((0x1U & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x540U, Val);
Val = ((0x2U & 0x3U) << 24U)
+ ((0xBU & 0xfU) << 8U)
+ ((0x3U & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x544U, Val);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x548U, 0x0U);
Val = ((0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x564U, Val);
Val = ((0x1U & 0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x568U, Val);
Val = ((0x1U & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x5F0U, Val);
Val = ((0x2U & 0x3U) << 24U)
+ ((0xBU & 0xfU) << 8U)
+ ((0x3U & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x5F4U, Val);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x5F8U, 0x0U);
Val = ((0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x614U, Val);
Val = ((0x1U & 0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x618U, Val);
Val = ((0x1U & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x6A0U, Val);
Val = ((0x1U & 0x3U) << 20U)
+ ((0x3U & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x6A4U, Val);
Val = ((0x4FU & 0x7ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x6A8U, Val);
Val = ((0x1U & 0x3U) << 20U)
+ ((0x3U & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x6ACU, Val);
Val = ((0x4FU & 0x7ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x6B0U, Val);
Val = ((0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x6C4U, Val);
Val = ((0x1U & 0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x6C8U, Val);
Val = ((0x1U & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x750U, Val);
Val = ((0x1U & 0x3U) << 20U)
+ ((0x3U & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x754U, Val);
Val = ((0x4FU & 0x7ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x758U, Val);
Val = ((0x1U & 0x3U) << 20U)
+ ((0x3U & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x75CU, Val);
Val = ((0x4FU & 0x7ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x760U, Val);
Val = ((0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x774U, Val);
Val = ((0x1U & 0x1U) << 13U)
+ ((0xFU & 0x3ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x778U, Val);
Val = ((0x1U & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x800U, Val);
Val = ((0x1U & 0x3U) << 20U)
+ ((0x3U & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x804U, Val);
Val = ((0x4FU & 0x7ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x808U, Val);
Val = ((0x1U & 0x3U) << 20U)
+ ((0x3U & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x80CU, Val);
Val = ((0x4FU & 0x7ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x810U, Val);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xF04U, 0x0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xF08U, 0x0U);
Val = ((0x10U & 0x1ffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xF0CU, Val);
Val = ((0xFU & 0xffU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0xF10U, Val);
Val = ((0x7U & 0x1fU) << 24U)
+ ((0x1U) << 23U)
+ ((0x2U & 0x3fU) << 16U)
+ ((0x1U) << 15U)
+ ((0x2U & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x2190U, Val);
}
#if !(defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
|| defined(XPS_BOARD_ZCU208))
/*****************************************************************************/
/**
* This function calculates and writes DDR controller registers
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
*
* @return None
*
*****************************************************************************/
static u32 XFsbl_DdrcRegsInit(struct DdrcInitData *DdrDataPtr)
{
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
u32 DdrCfg[300U] = XFSBL_DDRC_REG_DEFVAL;
u32 Status;
Status = XFsbl_DdrcCalcCommonRegVal(DdrDataPtr, PDimmPtr, DdrCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR3) {
Status = XFsbl_DdrcCalcDdr3RegVal(PDimmPtr, DdrCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
}
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
Status = XFsbl_DdrcCalcDdr4RegVal(PDimmPtr, DdrCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
}
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
Status = XFsbl_DdrcCalcLpddr3RegVal(PDimmPtr, DdrCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
}
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
Status = XFsbl_DdrcCalcLpddr4RegVal(PDimmPtr, DdrCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
}
DdrCfg[DDR_DFI_TPHY_RDCSLAT] = DdrCfg[DDR_DFI_T_RDDATA_EN] - 2U;
if (!PDimmPtr->RDimm) {
DdrCfg[DDR_DFI_TPHY_WRCSLAT] = DdrCfg[DDR_DFI_TPHY_WRLAT] - 2U;
}
/* Store the MR values which will be used for PHY Registers */
PDimmPtr->Mr = DdrCfg[DDR_MR];
PDimmPtr->Emr = DdrCfg[DDR_EMR];
PDimmPtr->Emr2 = DdrCfg[DDR_EMR2];
PDimmPtr->Emr3 = DdrCfg[DDR_EMR3];
PDimmPtr->Mr4 = DdrCfg[DDR_MR4];
PDimmPtr->Mr5 = DdrCfg[DDR_MR5];
PDimmPtr->Mr6 = DdrCfg[DDR_MR6];
XFsbl_DdrcRegsWrite(PDimmPtr, DdrCfg);
END:
return Status;
}
#endif
/*****************************************************************************/
/**
* This function calculates the PHY register values common to all DDR types
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param PhyCfg is the array to store register field values
*
* @return None
*
*****************************************************************************/
static u32 XFsbl_PhyCalcCommonRegVal(XFsbl_DimmParams *PDimmPtr, u32 *PhyCfg)
{
u32 MemSize = 0U;
u32 Lp4DramSize = 0U;
u32 NumRank = 0U;
PhyCfg[PHY_ADCP] = PDimmPtr->AddrMirror;
if (!PDimmPtr->PhyClkGate) {
PhyCfg[PHY_GATEACRDCLK] = 0x2U;
PhyCfg[PHY_GATEACDDRCLK] = 0x2U;
PhyCfg[PHY_GATEACCTLCLK] = 0x2U;
}
if (PDimmPtr->FreqB) {
PhyCfg[PHY_DDLPGACT] = 1U;
PhyCfg[PHY_DDLPGRW] = 1U;
}
PhyCfg[PHY_TPLLPD] = (u32)XFsbl_Ceil(1000U / (PDimmPtr->ClockPeriod * 2U));
PhyCfg[PHY_TPLLGS] = (u32)XFsbl_Ceil(4000.0 / (PDimmPtr->ClockPeriod * 2U));
PhyCfg[PHY_TPLLLOCK] = (u32)XFsbl_Ceil(100000.0 / (PDimmPtr->ClockPeriod * 2U));
PhyCfg[PHY_TPLLRST] = (u32)XFsbl_Ceil(9000.0 / (PDimmPtr->ClockPeriod * 2U));
PhyCfg[PHY_PLLBYP] = PDimmPtr->PllByp;
if (PDimmPtr->CtlClkFreq > 668U) {
PhyCfg[PHY_FRQSEL] = 8U;
PhyCfg[PHY_CPPC] = 5U;
PhyCfg[PHY_CPIC] = 0U;
} else if (PDimmPtr->CtlClkFreq > 560U) {
PhyCfg[PHY_FRQSEL] = 0U;
PhyCfg[PHY_CPPC] = 7U;
PhyCfg[PHY_CPIC] = 0U;
} else if (PDimmPtr->CtlClkFreq > 471U) {
PhyCfg[PHY_FRQSEL] = 1U;
PhyCfg[PHY_CPPC] = 8U;
PhyCfg[PHY_CPIC] = 0U;
} else if (PDimmPtr->CtlClkFreq > 396U) {
PhyCfg[PHY_FRQSEL] = 2U;
PhyCfg[PHY_CPPC] = 9U;
PhyCfg[PHY_CPIC] = 0U;
} else if (PDimmPtr->CtlClkFreq > 332U) {
PhyCfg[PHY_FRQSEL] = 3U;
PhyCfg[PHY_CPPC] = 10U;
PhyCfg[PHY_CPIC] = 0U;
} else if (PDimmPtr->CtlClkFreq > 279U) {
PhyCfg[PHY_FRQSEL] = 4U;
PhyCfg[PHY_CPPC] = 6U;
PhyCfg[PHY_CPIC] = 1U;
} else if (PDimmPtr->CtlClkFreq > 235U) {
PhyCfg[PHY_FRQSEL] = 5U;
PhyCfg[PHY_CPPC] = 8U;
} else if (PDimmPtr->CtlClkFreq > 197U) {
PhyCfg[PHY_FRQSEL] = 6U;
PhyCfg[PHY_CPPC] = 9U;
PhyCfg[PHY_CPIC] = 2U;
} else if (PDimmPtr->CtlClkFreq >= 166U) {
PhyCfg[PHY_FRQSEL] = 7U;
PhyCfg[PHY_CPPC] = 10U;
PhyCfg[PHY_CPIC] = 3U;
}
PhyCfg[PHY_PUAD] = (u32)(10U / PDimmPtr->ClockPeriod / 2.0);
if (PDimmPtr->UDimm & PDimmPtr->AddrMirror)
PhyCfg[PHY_UDIMM] = 1U;
if (PDimmPtr->En2tTimingMode) {
PhyCfg[PHY_TRAS] = (u32)XFsbl_Ceil(((PDimmPtr->TRasPs / 1000.0) /
PDimmPtr->ClockPeriod / 2.0)) * 2U;
} else {
PhyCfg[PHY_TRAS] = XFsbl_Round(((PDimmPtr->TRasPs / 1000.0) /
PDimmPtr->ClockPeriod / 2.0)) * 2U;
}
PhyCfg[PHY_TRP] = (PDimmPtr->TRpPs / 1000.0) + 2U;
PhyCfg[PHY_TFAW] = (u32)XFsbl_Ceil((PDimmPtr->TFawPs / 1000.0) / PDimmPtr->ClockPeriod);
PhyCfg[PHY_TRFC] = (u32)XFsbl_Ceil((PDimmPtr->TRfcPs / 1000.0) / PDimmPtr->ClockPeriod);
PhyCfg[PHY_TRC] = (u32)XFsbl_Ceil((PDimmPtr->TRcPs / 1000.0) / PDimmPtr->ClockPeriod) + 1U;
PhyCfg[PHY_TWTR] = PDimmPtr->TWtr;
PhyCfg[PHY_PUBWL] = PDimmPtr->WriteLatency;
PhyCfg[PHY_PUBRL] = PDimmPtr->ReadLatency;
PhyCfg[PHY_ERROUTODT] = PDimmPtr->Crc;
PhyCfg[PHY_RDIMM] = PDimmPtr->RDimm;
PhyCfg[PHY_DTDRS] = PDimmPtr->NumRankAddr;
PhyCfg[PHY_RANKEN] = (2U * PDimmPtr->NumRankAddr) + 1U;
Lp4DramSize = (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) ? 32U : PDimmPtr->DramWidth;
NumRank = (PDimmPtr->Zc1656 || PDimmPtr->HasEccComp) ? 0U : PDimmPtr->NumRankAddr;
MemSize = ((PDimmPtr->BusWidth / Lp4DramSize) * PDimmPtr->Capacity * (1U << NumRank)) / 8U;
PhyCfg[PHY_SEED] = (0x12340000U) | MemSize;
PhyCfg[PHY_DVMIN] = (PDimmPtr->Lp4NoOdt) ? 0x27U : 0U;
PhyCfg[PHY_PGWAIT_FRQA] = (u32)(40U / (PDimmPtr->ClockPeriod) / 2U);
if (PDimmPtr->HostDrv == 34U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xDU;
} else if (PDimmPtr->HostDrv == 40U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
} else if (PDimmPtr->HostDrv == 48U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x9U;
} else if (PDimmPtr->HostDrv == 60U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x7U;
} else if (PDimmPtr->HostDrv == 80U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x5U;
} else if (PDimmPtr->HostDrv == 120U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x3U;
} else {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
}
PhyCfg[PHY_ZPROG_ASYM_DRV_PU] = PhyCfg[PHY_ZPROG_ASYM_DRV_PD];
return XFSBL_SUCCESS;
}
/*****************************************************************************/
/**
* This function calculates the PHY register values for DDR4
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param PhyCfg is the array to store register field values
*
* @return XFSBL_SUCCESS or XFSBL_FAILURE
*
*****************************************************************************/
static u32 XFsbl_PhyCalcDdr4RegVal(XFsbl_DimmParams *PDimmPtr, u32 *PhyCfg)
{
u32 Val;
u32 Cal = 0U;
u32 BurstLength;
u32 CasLatency;
u32 Twr;
u32 Bit2;
u32 Bit654;
u32 POdt = 0U;
float FVal = 0.0;
Val = (u32)(((PDimmPtr->TRefi / 1000.0) / PDimmPtr->ClockPeriod));
if (PDimmPtr->Fgrm == 1U)
Val /= 2U;
else if (PDimmPtr->Fgrm == 2U)
Val /= 4U;
if (PDimmPtr->TRefRange) {
Val /= 2U;
}
PhyCfg[PHY_TREFPRD] = (8U * Val) - 1000U;
PhyCfg[PHY_NOSRA] = 0x1U;
PhyCfg[PHY_DDRMD] = 0x4U;
PhyCfg[PHY_TRRD] = (u32)XFSBL_MAX(XFsbl_Ceil((PDimmPtr->TRrdlPs / 1000.0) / PDimmPtr->ClockPeriod), 4U);
Val = PDimmPtr->AdditiveLatency + XFSBL_MAX((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 4U);
Val = XFSBL_MAX(Val, (PDimmPtr->ReadLatency + PDimmPtr->BurstLength / 2U - (PDimmPtr->TRpPs / 1000.0)));
PhyCfg[PHY_TRTP] = Val;
if ((PDimmPtr->TMod >= 24U) || (PDimmPtr->TMod <= 30U)) {
PhyCfg[PHY_TMOD] = (u32)XFsbl_Ceil(PDimmPtr->TMod - 24.0);
} else {
PhyCfg[PHY_TMOD] = 6U;
}
FVal = (PDimmPtr->SpeedBin < 2666U) ? 8.0 : 9.0;
if (PDimmPtr->Parity)
FVal = XFSBL_MAX(24U, 15U / PDimmPtr->ClockPeriod) + PDimmPtr->ParityLatency;
if (PDimmPtr->CalModeEn)
FVal = XFSBL_MAX(24U, 15U / PDimmPtr->ClockPeriod) + Cal;
PhyCfg[PHY_TMRD] = XFSBL_MIN(((u32)XFsbl_Ceil(FVal / 2.0)) * 2U, 32U);
PhyCfg[PHY_TXS] = (u32)XFsbl_Ceil((PDimmPtr->SpeedBin <= 1866U) ? 597.0 : ((PDimmPtr->SpeedBin <= 2400U) ? 768.0 : 1023.0));
PhyCfg[PHY_TDLLK] = (u32)XFsbl_Ceil((PDimmPtr->SpeedBin <= 1866U) ? 597.0 : ((PDimmPtr->SpeedBin <= 2400U) ? 768.0 : ((PDimmPtr->SpeedBin <= 2666U) ? 854U : 1023.0)));
PhyCfg[PHY_TDQSCK] = 0U;
PhyCfg[PHY_TXP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp), 31U);
PhyCfg[PHY_TRCD] = (PDimmPtr->TRcdPs / 1000.0) - PDimmPtr->AdditiveLatency + 2U;
if (PDimmPtr->Parity && PDimmPtr->RDimm)
PhyCfg[PHY_A17BID] = 1U;
if (PDimmPtr->RDimm && PDimmPtr->DisOpInv)
PhyCfg[PHY_RC0] = 0x1U;
if (PDimmPtr->AddrMirror && PDimmPtr->RDimm)
PhyCfg[PHY_RC13] = 0x8U;
PhyCfg[PHY_RC10] = (PDimmPtr->SpeedBin > 1600U) ? ((PDimmPtr->SpeedBin - 1600U) / 266U) : 0U;
if (PDimmPtr->Parity && PDimmPtr->RDimm)
PhyCfg[PHY_RC8] = 0x8U;
BurstLength = (PDimmPtr->BurstLength == 4U) ? 2U : 0U;
CasLatency = PDimmPtr->CasLatency;
if (CasLatency <= 16U) {
Bit654 = (CasLatency - 9U) / 2U;
Bit2 = ((CasLatency - 1U) % 2U);
} else if ((CasLatency % 2U) == 1U) {
Bit654 = (CasLatency + 2U) / 6U;
Bit2 = (((CasLatency + 1U) / 2U) % 2U);
} else {
Bit654 = (CasLatency - 1U) / 4U;
Bit2 = (((CasLatency / 2U) + 1U) % 2U);
}
Twr = (u32)XFsbl_Ceil(15.0 / PDimmPtr->ClockPeriod);
if ((Twr >= 10U) || (Twr <= 24U)) {
if (Twr % 2U == 1U) {
Twr += 1U;
}
if (Twr < 24U) {
Twr = (Twr - 10U) / 2U;
} else {
Twr = 6U;
}
}
PhyCfg[PHY_R060] = XFSBL_SETBITS(Twr, 9U, 3U) + (0U << 8U) +
XFSBL_SETBITS(Bit654, 4U, 3U) + (Bit2 << 2U) +
XFSBL_SETBITS(BurstLength, 0U, 2U);
if (PDimmPtr->DramOdt == 60U) {
POdt = 1U;
} else if (PDimmPtr->DramOdt == 120U) {
POdt = 2U;
} else if (PDimmPtr->DramOdt == 40U) {
POdt = 3U;
} else if (PDimmPtr->DramOdt == 240U) {
POdt = 4U;
} else if (PDimmPtr->DramOdt == 48U) {
POdt = 5U;
} else if (PDimmPtr->DramOdt == 80U) {
POdt = 6U;
} else if (PDimmPtr->DramOdt == 34U) {
POdt = 7U;
} else {
POdt = 0x3U + (2U * PDimmPtr->NumRankAddr);
}
PhyCfg[PHY_R061] = XFSBL_SETBITS(POdt, 8U, 3U) + XFSBL_SETBITS(PDimmPtr->AdditiveLatency, 3U, 2U) + XFSBL_SETBITS(((PDimmPtr->DramDrv == 48U) ? 1U : 0U), 1U, 2U) + 1U;
if (PDimmPtr->TRefRange)
PDimmPtr->LpAsr = 0x3U;
if ((PDimmPtr->CasWriteLatency >= 9U) &&
(PDimmPtr->CasWriteLatency <= 12U)) {
Val = PDimmPtr->CasWriteLatency - 9U;
} else if ((PDimmPtr->CasWriteLatency > 12U) &&
(PDimmPtr->CasWriteLatency <= 18U)) {
Val = (PDimmPtr->CasWriteLatency - 14U) / 2U + 4U;
}
PhyCfg[PHY_R062] = (PDimmPtr->Crc << 12U) + XFSBL_SETBITS(PDimmPtr->LpAsr, 6U, 2U) + XFSBL_SETBITS(Val, 3U, 3U);
PhyCfg[PHY_R063] = XFSBL_SETBITS((((PDimmPtr->SpeedBin - 266U) / 800U) - 1U), 9U, 2U) + XFSBL_SETBITS(PDimmPtr->Fgrm, 6U, 3U);
PhyCfg[PHY_R064] = PDimmPtr->Mr4;
PhyCfg[PHY_R065] = PDimmPtr->Mr5;
PhyCfg[PHY_R066] = PDimmPtr->Mr6;
if (PDimmPtr->RdDbi) {
if (!PDimmPtr->RdbiWrkAround) {
PhyCfg[PHY_DTRDBITR] = 0x3U;
} else {
PhyCfg[PHY_DTRDBITR] = 0x0U;
}
}
if (!(PDimmPtr->DataMask || PDimmPtr->WrDbi))
PhyCfg[PHY_DTWBDDM] = 0U;
if (PDimmPtr->En2ndClk) {
PhyCfg[PHY_CKOEMODE] = 0x5U;
PhyCfg[PHY_CKNCLKGATE0] = 0x0U;
PhyCfg[PHY_CKCLKGATE0] = 0x0U;
PhyCfg[PHY_CKNCLKGATE1] = 0x0U;
PhyCfg[PHY_CKCLKGATE1] = 0x0U;
} else {
PhyCfg[PHY_CKOEMODE] = ((1U - PDimmPtr->NumRankAddr) * 4U) + 5U;
PhyCfg[PHY_CKNCLKGATE0] = (1U - PDimmPtr->NumRankAddr) * 0x2U;
PhyCfg[PHY_CKCLKGATE0] = PhyCfg[PHY_CKNCLKGATE0];
PhyCfg[PHY_CKNCLKGATE1] = PhyCfg[PHY_CKNCLKGATE0];
PhyCfg[PHY_CKCLKGATE1] = PhyCfg[PHY_CKNCLKGATE0];
}
PhyCfg[PHY_ACREFSSEL] = 0x30U;
PhyCfg[PHY_ACVREFISEL] = 0x4EU;
PhyCfg[PHY_PDAEN] = 0x1U;
PhyCfg[PHY_DVINIT] = (PDimmPtr->DramOdt == 60U) ? 0x13U : 0x19U;
PhyCfg[PHY_A03BD] = 0x0U;
PhyCfg[PHY_A02BD] = 0x0U;
PhyCfg[PHY_A01BD] = 0x0U;
PhyCfg[PHY_A00BD] = 0x0U;
PhyCfg[PHY_A07BD] = 0x0U;
PhyCfg[PHY_A06BD] = 0x0U;
PhyCfg[PHY_A05BD] = 0x0U;
PhyCfg[PHY_A04BD] = 0x0U;
PhyCfg[PHY_A11BD] = 0x0U;
PhyCfg[PHY_A10BD] = 0x0U;
PhyCfg[PHY_A09BD] = 0x0U;
PhyCfg[PHY_A08BD] = 0x0U;
PhyCfg[PHY_ODT_MODE] = 0x1U;
PhyCfg[PHY_ZPROG_HOST_ODT] = 9U;
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xDU;
PhyCfg[PHY_ZPROG_ASYM_DRV_PU] = 0xDU;
if (!(PDimmPtr->DataMask || PDimmPtr->WrDbi || PDimmPtr->RdDbi)) {
PhyCfg[PHY_DMEN] = 0U;
PhyCfg[PHY_DMOEMODE] = 2U;
PhyCfg[PHY_DMTEMODE] = 2U;
PhyCfg[PHY_DMPDRMODE] = 1U;
}
PhyCfg[PHY_DXREFSSEL] = 0x30U;
PhyCfg[PHY_DXREFIEN] = 0xFU;
if ((PDimmPtr->UDimm == 1U) || (PDimmPtr->RDimm == 1U)) {
PhyCfg[PHY_DXREFISELR1] = 0x55U;
} else {
PhyCfg[PHY_DXREFISELR1] = 0x4FU;
}
if ((PDimmPtr->UDimm == 1U) || (PDimmPtr->RDimm == 1U)) {
PhyCfg[PHY_DXREFISELR0] = 0x55U;
} else {
PhyCfg[PHY_DXREFISELR0] = 0x4FU;
}
return XFSBL_SUCCESS;
}
#if !(defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
|| defined(XPS_BOARD_ZCU208))
/*****************************************************************************/
/**
* This function calculates the PHY register values for DDR3
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param PhyCfg is the array to store register field values
*
* @return XFSBL_SUCCESS or XFSBL_FAILURE
*
*****************************************************************************/
static u32 XFsbl_PhyCalcDdr3RegVal(XFsbl_DimmParams *PDimmPtr, u32 *PhyCfg)
{
u32 Val;
u32 BurstLength;
u32 CasLatency;
u32 Twr;
u32 Bit2;
u32 Bit654;
u32 POdt = 0U;
float FVal = 0.0;
Val = (u32)(((PDimmPtr->TRefi / 1000.0) / PDimmPtr->ClockPeriod));
if (PDimmPtr->TRefRange) {
Val /= 2U;
}
PhyCfg[PHY_TREFPRD] = (8U * Val) - 1000U;
PhyCfg[PHY_NOSRA] = 0x1U;
PhyCfg[PHY_DDRMD] = 0x3U;
PhyCfg[PHY_TRRD] = (u32)XFSBL_MAX(XFsbl_Ceil((PDimmPtr->TRrdPs / 1000.0) /
PDimmPtr->ClockPeriod), 4U);
PhyCfg[PHY_TRTP] = PDimmPtr->AdditiveLatency + XFSBL_MAX(((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod)), 4U);
if ((PDimmPtr->TMod >= 12U) || (PDimmPtr->TMod <= 17U)) {
PhyCfg[PHY_TMOD] = (u32)XFsbl_Ceil(PDimmPtr->TMod - 12.0);
} else {
PhyCfg[PHY_TMOD] = 5U;
}
PhyCfg[PHY_TMRD] = 4U;
FVal = ((PDimmPtr->TRfcPs / 1000.0) + 10.0) / PDimmPtr->ClockPeriod;
PhyCfg[PHY_TXS] = (u32)XFsbl_Ceil(XFSBL_MAX(512.0, FVal));
PhyCfg[PHY_TDQSCK] = 0U;
PhyCfg[PHY_TXP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp), 31U);
PhyCfg[PHY_TRCD] = (PDimmPtr->TRcdPs / 1000.0) - PDimmPtr->AdditiveLatency + 2U;
PhyCfg[PHY_RC10] = XFSBL_MAX(0U, (PDimmPtr->SpeedBin / 266U) - 3U);
BurstLength = (PDimmPtr->BurstLength == 4U) ? 2U : 0U;
CasLatency = PDimmPtr->CasLatency;
if (CasLatency < 12U) {
Bit2 = 0U;
Bit654 = CasLatency - 4U;
} else {
Bit2 = 1U;
Bit654 = CasLatency - 12U;
}
Twr = (u32)XFsbl_Ceil(15.0 / PDimmPtr->ClockPeriod);
Twr = XFSBL_MAX(5U, XFSBL_MIN(16U, Twr));
PhyCfg[PHY_R060] = XFSBL_SETBITS(((Twr < 9U) ? (Twr - 4U) : ((Twr + 1U) / 2U)), 9U, 3U) + (1U << 8U) + XFSBL_SETBITS(Bit654, 4U, 3U)
+ (Bit2 << 2U) + XFSBL_SETBITS(BurstLength, 0U, 2U);
if (PDimmPtr->DramOdt == 60U) {
POdt = (0U << 9U) + (0U << 6U) + (1U << 2U);
} else if (PDimmPtr->DramOdt == 120U) {
POdt = (0U << 9U) + (1U << 6U) + (0U << 2U);
} else if (PDimmPtr->DramOdt == 40U) {
POdt = (0U << 9U) + (1U << 6U) + (1U << 2U);
} else if (PDimmPtr->DramOdt == 20U) {
POdt = (1U << 9U) + (0U << 6U) + (0U << 2U);
} else if (PDimmPtr->DramOdt == 30U) {
POdt = (1U << 9U) + (0U << 6U) + (1U << 2U);
} else {
if (PDimmPtr->NumRankAddr == 0U) {
POdt = (1U << 2U);
} else {
POdt = (1U << 6U);
}
}
PhyCfg[PHY_R061] = (PDimmPtr->AdditiveLatency << 3U) + POdt + ((PDimmPtr->DramDrv == 34U) ? 0x2U : 0x0U);
PhyCfg[PHY_R062] = (PDimmPtr->NumRankAddr << 9U) + XFSBL_SETBITS((PDimmPtr->CasWriteLatency - 5U), 3U, 3U) + (PDimmPtr->TRefRange << 7U);
PhyCfg[PHY_R063] = 0x0U;
PhyCfg[PHY_DTWBDDM] = 0x0U;
if (PDimmPtr->En2ndClk) {
PhyCfg[PHY_CKOEMODE] = 0x5U;
PhyCfg[PHY_CKNCLKGATE0] = 0x0U;
PhyCfg[PHY_CKCLKGATE0] = 0x0U;
PhyCfg[PHY_CKNCLKGATE1] = 0x0U;
PhyCfg[PHY_CKCLKGATE1] = 0x0U;
} else {
PhyCfg[PHY_CKOEMODE] = ((1U - PDimmPtr->NumRankAddr) * 4U) + 5U;
PhyCfg[PHY_CKNCLKGATE0] = (1U - PDimmPtr->NumRankAddr) * 0x2U;
PhyCfg[PHY_CKCLKGATE0] = PhyCfg[PHY_CKNCLKGATE0];
PhyCfg[PHY_CKNCLKGATE1] = PhyCfg[PHY_CKNCLKGATE0];
PhyCfg[PHY_CKCLKGATE1] = PhyCfg[PHY_CKNCLKGATE0];
}
PhyCfg[PHY_ACREFSSEL] = 0x30U;
PhyCfg[PHY_ACVREFISEL] = 0x30U;
PhyCfg[PHY_PDAEN] = 0x0U;
if (PDimmPtr->Zc1656 || PDimmPtr->HasEccComp) {
PhyCfg[PHY_DVINIT] = 0x2EU;
} else {
if (PDimmPtr->Lp4NoOdt) {
PhyCfg[PHY_DVINIT] = 0x2FU;
} else {
PhyCfg[PHY_DVINIT] = 0x19U;
}
}
PhyCfg[PHY_A03BD] = 0x0U;
PhyCfg[PHY_A02BD] = 0x0U;
PhyCfg[PHY_A01BD] = 0x0U;
PhyCfg[PHY_A00BD] = 0x0U;
PhyCfg[PHY_A07BD] = 0x0U;
PhyCfg[PHY_A06BD] = 0x0U;
PhyCfg[PHY_A05BD] = 0x0U;
PhyCfg[PHY_A04BD] = 0x0U;
PhyCfg[PHY_A11BD] = 0x0U;
PhyCfg[PHY_A10BD] = 0x0U;
PhyCfg[PHY_A09BD] = 0x0U;
PhyCfg[PHY_A08BD] = 0x0U;
PhyCfg[PHY_ODT_MODE] = 0x0U;
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
PhyCfg[PHY_ZPROG_ASYM_DRV_PU] = 0xBU;
PhyCfg[PHY_DXREFSSEL] = 0x30U;
PhyCfg[PHY_DXREFIEN] = 0x3U;
PhyCfg[PHY_DXREFISELR1] = 0x30U;
PhyCfg[PHY_DXREFISELR0] = 0x30U;
return XFSBL_SUCCESS;
}
/*****************************************************************************/
/**
* This function calculates the PHY register values for LPDDR3
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param PhyCfg is the array to store register field values
*
* @return XFSBL_SUCCESS or XFSBL_FAILURE
*
*****************************************************************************/
static u32 XFsbl_PhyCalcLpddr3RegVal(XFsbl_DimmParams *PDimmPtr, u32 *PhyCfg)
{
u32 Val;
Val = (u32)(((PDimmPtr->TRefi / 1000.0) / PDimmPtr->ClockPeriod));
if (PDimmPtr->PerBankRefresh == 0U) {
if (PDimmPtr->Capacity != 1024U) {
Val /= 2U;
}
} else {
if (PDimmPtr->Capacity >= 2048U) {
Val = (u32)((487.5 / PDimmPtr->ClockPeriod));
} else if (PDimmPtr->Capacity == 1024U) {
Val = (u32)((975.0 / PDimmPtr->ClockPeriod));
}
}
if (PDimmPtr->TRefRange) {
Val /= 4U;
}
PhyCfg[PHY_TREFPRD] = (8U * Val) - 1000U;
PhyCfg[PHY_NOSRA] = 0x1U;
PhyCfg[PHY_DDRMD] = 0x1U;
PhyCfg[PHY_TRRD] = (u32)XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 2U) + (1.875 * PDimmPtr->TRefRange);
PhyCfg[PHY_TRTP] = PDimmPtr->BurstLength / 2U + XFSBL_MAX((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 4U) - 4U;
PhyCfg[PHY_TMRD] = XFSBL_MIN(((u32)XFsbl_Ceil((XFSBL_MAX(10U, 15U / PDimmPtr->ClockPeriod)) / 2.0)) * 2U, 32U);
PhyCfg[PHY_TXS] = (u32)XFsbl_Ceil(XFSBL_MAX(2.0, ((PDimmPtr->TRfcPs / 1000.0) + 10U) / PDimmPtr->ClockPeriod));
PhyCfg[PHY_TDQSCKMAX] = 0x5U;
PhyCfg[PHY_TDQSCK] = (u32)(1.5 / PDimmPtr->ClockPeriod);
PhyCfg[PHY_TXP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp), 31U);
PhyCfg[PHY_TRCD] = (PDimmPtr->TRcdPs / 1000.0) - PDimmPtr->AdditiveLatency + 2U;
PhyCfg[PHY_R061] = PDimmPtr->Mr;
PhyCfg[PHY_R062] = PDimmPtr->Emr;
PhyCfg[PHY_R063] = PDimmPtr->Emr2;
PhyCfg[PHY_DQODT] = (PDimmPtr->DramOdt == 240U) ? 3U : 2U;
if ((PDimmPtr->AddrMirror == 1U) && (PDimmPtr->DramWidth == 16U)) {
PhyCfg[PHY_CA1BYTE1] = 3U;
}
if ((PDimmPtr->AddrMirror == 1U) && (PDimmPtr->DramWidth == 16U)) {
PhyCfg[PHY_CA1BYTE0] = 2U;
}
if (PDimmPtr->En2ndClk) {
PhyCfg[PHY_CKOEMODE] = 0x5U;
PhyCfg[PHY_CKNCLKGATE0] = 0x0U;
PhyCfg[PHY_CKCLKGATE0] = 0x0U;
PhyCfg[PHY_CKNCLKGATE1] = 0x0U;
PhyCfg[PHY_CKCLKGATE1] = 0x0U;
} else {
PhyCfg[PHY_CKOEMODE] = ((1U - PDimmPtr->NumRankAddr) * 4U) + 5U;
PhyCfg[PHY_CKNCLKGATE0] = (1U - PDimmPtr->NumRankAddr) * 0x2U;
PhyCfg[PHY_CKCLKGATE0] = PhyCfg[PHY_CKNCLKGATE0];
PhyCfg[PHY_CKNCLKGATE1] = PhyCfg[PHY_CKNCLKGATE0];
PhyCfg[PHY_CKCLKGATE1] = PhyCfg[PHY_CKNCLKGATE0];
}
PhyCfg[PHY_ACREFSSEL] = 0x30U;
PhyCfg[PHY_ACVREFISEL] = 0x30U;
PhyCfg[PHY_PDAEN] = 0x0U;
if (PDimmPtr->Zc1656 || PDimmPtr->HasEccComp) {
PhyCfg[PHY_DVINIT] = 0x2EU;
} else {
if (PDimmPtr->Lp4NoOdt) {
PhyCfg[PHY_DVINIT] = 0x2FU;
} else {
PhyCfg[PHY_DVINIT] = 0x19U;
}
}
PhyCfg[PHY_ACTBD] = 4U;
PhyCfg[PHY_BG1BD] = 4U;
PhyCfg[PHY_BG0BD] = 4U;
PhyCfg[PHY_BA1BD] = 4U;
PhyCfg[PHY_BA0BD] = 4U;
PhyCfg[PHY_A03BD] = 4U;
PhyCfg[PHY_A02BD] = 4U;
PhyCfg[PHY_A01BD] = 4U;
PhyCfg[PHY_A00BD] = 4U;
PhyCfg[PHY_A07BD] = 4U;
PhyCfg[PHY_A06BD] = 4U;
PhyCfg[PHY_A05BD] = 4U;
PhyCfg[PHY_A04BD] = 4U;
PhyCfg[PHY_A11BD] = 4U;
PhyCfg[PHY_A10BD] = 4U;
PhyCfg[PHY_A09BD] = 4U;
PhyCfg[PHY_A08BD] = 4U;
PhyCfg[PHY_A15BD] = 4U;
PhyCfg[PHY_A14BD] = 4U;
PhyCfg[PHY_A13BD] = 4U;
PhyCfg[PHY_A12BD] = 4U;
PhyCfg[PHY_ODT_MODE] = 0x1U;
PhyCfg[PHY_ZPROG_DRAM_ODT] = 0x7U;
PhyCfg[PHY_ZPROG_HOST_ODT] = 7U;
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
PhyCfg[PHY_ZPROG_ASYM_DRV_PU] = 0xBU;
PhyCfg[PHY_DXREFSSEL] = 0x30U;
PhyCfg[PHY_DXREFIEN] = 0x3U;
PhyCfg[PHY_DXREFISELR1] = 0x3FU;
PhyCfg[PHY_DXREFISELR0] = 0x3FU;
return XFSBL_SUCCESS;
}
/*****************************************************************************/
/**
* This function calculates the PHY register values for LPDDR4
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param PhyCfg is the array to store register field values
*
* @return XFSBL_SUCCESS or XFSBL_FAILURE
*
*****************************************************************************/
static u32 XFsbl_PhyCalcLpddr4RegVal(XFsbl_DimmParams *PDimmPtr, u32 *PhyCfg)
{
u32 Val;
Val = (u32)(((3904U / ((PDimmPtr->PerBankRefresh != 0U) ? 8U : 1U)) / PDimmPtr->ClockPeriod));
if (PDimmPtr->TRefRange) {
Val /= 4U;
}
PhyCfg[PHY_TREFPRD] = (8U * Val) - 1000U;
PhyCfg[PHY_NOSRA] = 0x0U;
PhyCfg[PHY_DDRMD] = 0x5U;
PhyCfg[PHY_TRRD] = (u32)XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 4U) + (1.875 * PDimmPtr->TRefRange);
PhyCfg[PHY_TRAS] = (u32)XFsbl_Ceil(((PDimmPtr->TRasPs / 1000.0) / PDimmPtr->ClockPeriod / 2.0)) * 2U;
PhyCfg[PHY_TRTP] = (PDimmPtr->BurstLength / 2U) + XFSBL_MAX((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 8U) - 8U;
PhyCfg[PHY_TMOD] = 5U;
PhyCfg[PHY_TMRD] = XFSBL_MIN(((u32)XFsbl_Ceil((XFSBL_MAX(14.0 / PDimmPtr->ClockPeriod, 10U)) / 2.0)) * 2U, 32U);
PhyCfg[PHY_TXS] = (u32)XFsbl_Ceil(XFSBL_MAX(2.0, ((PDimmPtr->TRfcPs / 1000.0) + 7.5) / PDimmPtr->ClockPeriod));
PhyCfg[PHY_TDQSCKMAX] = 0x5U;
PhyCfg[PHY_TDQSCK] = (PDimmPtr->SpeedBin >= 1600U) ? ((u32)(1.5 / PDimmPtr->ClockPeriod)) : 1U;
PhyCfg[PHY_TXP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp) + 3U, 31U);
PhyCfg[PHY_TRCD] = XFSBL_MAX(((PDimmPtr->TRcdPs / 1000.0) - PDimmPtr->AdditiveLatency), (PhyCfg[PHY_TRAS] - 8U));
PhyCfg[PHY_R061] = PDimmPtr->Mr;
PhyCfg[PHY_R062] = PDimmPtr->Emr;
PhyCfg[PHY_R063] = PDimmPtr->Emr2;
PhyCfg[PHY_R064] = PDimmPtr->Emr3;
if (PDimmPtr->DramCaOdt == 240U) {
PhyCfg[PHY_CAODT] = 1U;
} else if (PDimmPtr->DramCaOdt == 120U) {
PhyCfg[PHY_CAODT] = 2U;
} else if (PDimmPtr->DramCaOdt == 80U) {
PhyCfg[PHY_CAODT] = 3U;
} else if (PDimmPtr->DramCaOdt == 60U) {
PhyCfg[PHY_CAODT] = 4U;
} else if (PDimmPtr->DramCaOdt == 48U) {
PhyCfg[PHY_CAODT] = 5U;
} else if (PDimmPtr->DramCaOdt == 40U) {
PhyCfg[PHY_CAODT] = 6U;
} else {
PhyCfg[PHY_CAODT] = 5U;
}
PhyCfg[PHY_DQODT] = PDimmPtr->DramOdt ? PhyCfg[PHY_CAODT] : 6U;
PhyCfg[PHY_VREFCA_RANGE] = 0U;
PhyCfg[PHY_VREFCA] = 0x21U;
PhyCfg[PHY_VREFDQ_RANGE] = PDimmPtr->Lp4NoOdt;
if (PDimmPtr->Zc1656 || PDimmPtr->HasEccComp) {
PhyCfg[PHY_VREFDQ] = 0x2EU;
} else {
if (PDimmPtr->Lp4NoOdt) {
PhyCfg[PHY_VREFDQ] = 0x2FU;
} else {
PhyCfg[PHY_VREFDQ] = 0x19U;
}
}
PhyCfg[PHY_ODTD_CA] = 0U;
PhyCfg[PHY_ODTE_CS] = 1U;
PhyCfg[PHY_ODTE_CK] = 0U;
PhyCfg[PHY_CODT] = 6U;
if (PDimmPtr->RdDbi) {
if (!PDimmPtr->RdbiWrkAround) {
PhyCfg[PHY_DTRDBITR] = 0x3U;
} else {
PhyCfg[PHY_DTRDBITR] = 0x0U;
}
}
if (!(PDimmPtr->DataMask || PDimmPtr->WrDbi)) {
PhyCfg[PHY_DTWBDDM] = 0U;
}
PhyCfg[PHY_ODTOEMODE] = 0xAU;
PhyCfg[PHY_CKNCLKGATE0] = 0x0U;
PhyCfg[PHY_CKCLKGATE0] = 0x0U;
PhyCfg[PHY_CKOEMODE] = 0x5U;
PhyCfg[PHY_CKNCLKGATE1] = 0x0U;
PhyCfg[PHY_CKCLKGATE1] = 0x0U;
PhyCfg[PHY_ACREFSSEL] = 0x3DU;
PhyCfg[PHY_ACVREFISEL] = 0x19U;
PhyCfg[PHY_PDAEN] = 0x0U;
if (PDimmPtr->Zc1656 || PDimmPtr->HasEccComp) {
PhyCfg[PHY_DVINIT] = 0x2EU;
} else {
if (PDimmPtr->Lp4NoOdt) {
PhyCfg[PHY_DVINIT] = 0x2FU;
} else {
PhyCfg[PHY_DVINIT] = 0x19U;
}
}
return XFSBL_SUCCESS;
}
#endif
/*****************************************************************************/
/**
* This function writes the PHY registers with calculated values
*
* @param PDimmPtr is pointer to DIMM parameters Data Structure
* @param PhyCfg is the array to store register field values
*
* @return None
*
*****************************************************************************/
static void XFsbl_PhyRegsWrite(XFsbl_DimmParams *PDimmPtr, u32 *PhyCfg)
{
u32 Val;
Val = ((PhyCfg[PHY_CALBYP] & 0x1U) << 31U)
+ ((0x1U) << 30U)
+ ((PhyCfg[PHY_CODTSHFT] & 0x3U) << 28U)
+ ((PhyCfg[PHY_DQSDCC] & 0x7U) << 24U)
+ ((0x8U & 0xfU) << 20U)
+ ((PhyCfg[PHY_DQSNSEPDR] & 0x1U) << 13U)
+ ((PhyCfg[PHY_DQSSEPDR] & 0x1U) << 12U)
+ ((PhyCfg[PHY_RTTOAL] & 0x1U) << 11U)
+ ((0x3U & 0x3U) << 9U)
+ ((PhyCfg[PHY_CPDRSHFT] & 0x3U) << 7U)
+ ((PhyCfg[PHY_DQSRPD] & 0x1U) << 6U)
+ ((PhyCfg[PHY_DQSGPDR] & 0x1U) << 5U)
+ ((PhyCfg[PHY_DQSGODT] & 0x1U) << 3U)
+ ((0x1U) << 2U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x700U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x800U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x900U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xA00U, Val);
Val = ((PhyCfg[PHY_DXPDRMODE] & 0xFFFFU) << 16U)
+ ((0x1U & 0x1U) << 14U)
+ ((0x1U & 0x1U) << 13U)
+ ((0x1U) << 12U)
+ ((0x1U) << 11U)
+ ((0x1U) << 10U)
+ ((0x1U) << 9U)
+ ((PhyCfg[PHY_DMEN] & 0x1U) << 8U)
+ ((0xFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x704U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x804U, Val);
Val = ((0x1U) << 29U)
+ ((0x1U) << 28U)
+ ((0x1U) << 27U)
+ ((0x1U) << 26U)
+ ((0x1U) << 25U)
+ ((0x1U) << 24U)
+ ((PhyCfg[PHY_DSNOEMODE] & 0x3U) << 20U)
+ ((PhyCfg[PHY_DSNTEMODE] & 0x3U) << 18U)
+ ((PhyCfg[PHY_DSNPDRMODE] & 0x3U) << 16U)
+ ((PhyCfg[PHY_DMOEMODE] & 0x3U) << 14U)
+ ((PhyCfg[PHY_DMTEMODE] & 0x3U) << 12U)
+ ((PhyCfg[PHY_DMPDRMODE] & 0x3U) << 10U)
+ ((PhyCfg[PHY_DSOEMODE] & 0x3U) << 6U)
+ ((PhyCfg[PHY_DSTEMODE] & 0x3U) << 4U)
+ ((0x2U & 0x3U) << 2U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x70CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x80CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x90CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xA0CU, Val);
Val = ((PhyCfg[PHY_DXREFIOM] & 0x7U) << 29U)
+ ((PhyCfg[PHY_DXREFPEN] & 0x1U) << 28U)
+ ((0x3U & 0x3U) << 26U)
+ ((0x1U) << 25U)
+ ((PhyCfg[PHY_DXREFESELRANGE] & 0x1U) << 23U)
+ ((PhyCfg[PHY_DXREFESEL] & 0x7FU) << 16U)
+ ((0x1U & 0x1U) << 15U)
+ ((PhyCfg[PHY_DXREFSSEL] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFIEN] & 0xFU) << 2U)
+ ((PhyCfg[PHY_DXREFIMON] & 0x3U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x710U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x810U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x910U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xA10U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xC10U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xE10U, Val);
if (PDimmPtr->BusWidth == 16U)
PhyCfg[PHY_DQEN] = 0x0U;
Val = ((PhyCfg[PHY_DXPDRMODE] & 0xFFFFU) << 16U)
+ ((0x1U & 0x1U) << 14U)
+ ((0x1U & 0x1U) << 13U)
+ ((0x1U) << 12U)
+ ((0x1U) << 11U)
+ ((0x1U) << 10U)
+ ((PhyCfg[PHY_DSEN] & 0x1U) << 9U)
+ ((PhyCfg[PHY_DMEN] & 0x1U) << 8U)
+ ((PhyCfg[PHY_DQEN] & 0xFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x904U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xA04U, Val);
if (PDimmPtr->BusWidth == 32U) {
PhyCfg[PHY_CALBYP] = 1U;
PhyCfg[PHY_MDLEN] = 0U;
PhyCfg[PHY_DQSNSEPDR] = 1U;
PhyCfg[PHY_DQSSEPDR] = 1U;
PhyCfg[PHY_DQSRPD] = 1U;
PhyCfg[PHY_DQSGPDR] = 1U;
PhyCfg[PHY_DQSGODT] = 0U;
PhyCfg[PHY_DQSGOE] = 0U;
PhyCfg[PHY_DXPDRMODE] = 0x5555U;
PhyCfg[PHY_OEEN] = 0x0U;
PhyCfg[PHY_PDREN] = 0x0U;
PhyCfg[PHY_TEEN] = 0x0U;
PhyCfg[PHY_DSEN] = 0x0U;
PhyCfg[PHY_DMEN] = 0x0U;
PhyCfg[PHY_DXOEMODE] = 0xAAAAU;
PhyCfg[PHY_DXTEMODE] = 0xAAAAU;
PhyCfg[PHY_RDBVT] = 0x0U;
PhyCfg[PHY_WDBVT] = 0x0U;
PhyCfg[PHY_RGLVT] = 0x0U;
PhyCfg[PHY_RDLVT] = 0x0U;
PhyCfg[PHY_WDLVT] = 0x0U;
PhyCfg[PHY_WLLVT] = 0x0U;
PhyCfg[PHY_DSNOEMODE] = 2U;
PhyCfg[PHY_DSNTEMODE] = 2U;
PhyCfg[PHY_DSNPDRMODE] = 1U;
PhyCfg[PHY_DMOEMODE] = 2U;
PhyCfg[PHY_DMTEMODE] = 2U;
PhyCfg[PHY_DMPDRMODE] = 1U;
PhyCfg[PHY_DSOEMODE] = 2U;
PhyCfg[PHY_DSTEMODE] = 2U;
PhyCfg[PHY_DSPDRMODE] = 1U;
PhyCfg[PHY_DXREFSEN] = 0U;
}
if (PDimmPtr->BusWidth != 64U) {
PhyCfg[PHY_DQEN] = 0x0U;
}
Val = ((PhyCfg[PHY_CALBYP] & 0x1U) << 31U)
+ ((PhyCfg[PHY_MDLEN] & 0x1U) << 30U)
+ ((PhyCfg[PHY_CODTSHFT] & 0x3U) << 28U)
+ ((PhyCfg[PHY_DQSDCC] & 0x7U) << 24U)
+ ((0x8U & 0xfU) << 20U)
+ ((PhyCfg[PHY_DQSNSEPDR] & 0x1U) << 13U)
+ ((PhyCfg[PHY_DQSSEPDR] & 0x1U) << 12U)
+ ((PhyCfg[PHY_RTTOAL] & 0x1U) << 11U)
+ ((0x3U & 0x3U) << 9U)
+ ((PhyCfg[PHY_CPDRSHFT] & 0x3U) << 7U)
+ ((PhyCfg[PHY_DQSRPD] & 0x1U) << 6U)
+ ((PhyCfg[PHY_DQSGPDR] & 0x1U) << 5U)
+ ((PhyCfg[PHY_DQSGODT] & 0x1U) << 3U)
+ ((PhyCfg[PHY_DQSGOE] & 0x1U) << 2U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xB00U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xC00U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xD00U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xE00U, Val);
Val = ((PhyCfg[PHY_DXPDRMODE] & 0xFFFFU) << 16U)
+ ((0x1U & 0x1U) << 14U)
+ ((0x1U & 0x1U) << 13U)
+ ((PhyCfg[PHY_OEEN] & 0x1U) << 12U)
+ ((PhyCfg[PHY_PDREN] & 0x1U) << 11U)
+ ((PhyCfg[PHY_TEEN] & 0x1U) << 10U)
+ ((PhyCfg[PHY_DSEN] & 0x1U) << 9U)
+ ((PhyCfg[PHY_DMEN] & 0x1U) << 8U)
+ ((PhyCfg[PHY_DQEN] & 0xFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xB04U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xC04U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xD04U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xE04U, Val);
Val = ((PhyCfg[PHY_RDBVT] & 0x1U) << 29U)
+ ((PhyCfg[PHY_WDBVT] & 0x1U) << 28U)
+ ((PhyCfg[PHY_RGLVT] & 0x1U) << 27U)
+ ((PhyCfg[PHY_RDLVT] & 0x1U) << 26U)
+ ((PhyCfg[PHY_WDLVT] & 0x1U) << 25U)
+ ((PhyCfg[PHY_WLLVT] & 0x1U) << 24U)
+ ((PhyCfg[PHY_DSNOEMODE] & 0x3U) << 20U)
+ ((PhyCfg[PHY_DSNTEMODE] & 0x3U) << 18U)
+ ((PhyCfg[PHY_DSNPDRMODE] & 0x3U) << 16U)
+ ((PhyCfg[PHY_DMOEMODE] & 0x3U) << 14U)
+ ((PhyCfg[PHY_DMTEMODE] & 0x3U) << 12U)
+ ((PhyCfg[PHY_DMPDRMODE] & 0x3U) << 10U)
+ ((PhyCfg[PHY_DSOEMODE] & 0x3U) << 6U)
+ ((PhyCfg[PHY_DSTEMODE] & 0x3U) << 4U)
+ ((PhyCfg[PHY_DSPDRMODE] & 0x3U) << 2U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xB0CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xC0CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xD0CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xE0CU, Val);
if (PDimmPtr->BusWidth == 32U)
PhyCfg[PHY_DXREFIEN] = 0U;
else {
if (PDimmPtr->NumRankAddr == 1U)
PhyCfg[PHY_DXREFIEN] = 3U;
else
PhyCfg[PHY_DXREFIEN] = 1U;
}
Val = ((PhyCfg[PHY_DXREFIOM] & 0x7U) << 29U)
+ ((PhyCfg[PHY_DXREFPEN] & 0x1U) << 28U)
+ ((0x3U & 0x3U) << 26U)
+ ((PhyCfg[PHY_DXREFSEN] & 0x1U) << 25U)
+ ((PhyCfg[PHY_DXREFESELRANGE] & 0x1U) << 23U)
+ ((PhyCfg[PHY_DXREFESEL] & 0x7FU) << 16U)
+ ((0x1U & 0x1U) << 15U)
+ ((PhyCfg[PHY_DXREFSSEL] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFIEN] & 0xFU) << 2U)
+ ((PhyCfg[PHY_DXREFIMON] & 0x3U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xB10U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xD10U, Val);
if (PDimmPtr->Ecc == 0U) {
PhyCfg[PHY_CALBYP] = 1U;
PhyCfg[PHY_MDLEN] = 0U;
PhyCfg[PHY_DQSNSEPDR] = 1U;
PhyCfg[PHY_DQSSEPDR] = 1U;
PhyCfg[PHY_DQSRPD] = 1U;
PhyCfg[PHY_DQSGPDR] = 1U;
PhyCfg[PHY_DQSGOE] = 0U;
PhyCfg[PHY_DXPDRMODE] = 0x5555U;
PhyCfg[PHY_OEEN] = 0U;
PhyCfg[PHY_PDREN] = 0U;
PhyCfg[PHY_TEEN] = 0U;
PhyCfg[PHY_DSEN] = 0U;
PhyCfg[PHY_DMEN] = 0U;
PhyCfg[PHY_DQEN] = 0x0U;
PhyCfg[PHY_DXOEMODE] = 0xAAAAU;
PhyCfg[PHY_DXTEMODE] = 0xAAAAU;
PhyCfg[PHY_RDBVT] = 0U;
PhyCfg[PHY_WDBVT] = 0U;
PhyCfg[PHY_RGLVT] = 0U;
PhyCfg[PHY_RDLVT] = 0U;
PhyCfg[PHY_WDLVT] = 0U;
PhyCfg[PHY_WLLVT] = 0U;
PhyCfg[PHY_DSNOEMODE] = 2U;
PhyCfg[PHY_DSNTEMODE] = 2U;
PhyCfg[PHY_DSNPDRMODE] = 1U;
PhyCfg[PHY_DMOEMODE] = 2U;
PhyCfg[PHY_DMTEMODE] = 2U;
PhyCfg[PHY_DMPDRMODE] = 1U;
PhyCfg[PHY_DSOEMODE] = 2U;
PhyCfg[PHY_DSTEMODE] = 2U;
PhyCfg[PHY_DSPDRMODE] = 1U;
PhyCfg[PHY_DXREFSEN] = 0U;
} else {
PhyCfg[PHY_DQSGPDR] = 1U;
}
Val = ((PhyCfg[PHY_CALBYP] & 0x1U) << 31U)
+ ((PhyCfg[PHY_MDLEN] & 0x1U) << 30U)
+ ((PhyCfg[PHY_CODTSHFT] & 0x3U) << 28U)
+ ((PhyCfg[PHY_DQSDCC] & 0x7U) << 24U)
+ ((0x8U & 0xfU) << 20U)
+ ((PhyCfg[PHY_DQSNSEPDR] & 0x1U) << 13U)
+ ((PhyCfg[PHY_DQSSEPDR] & 0x1U) << 12U)
+ ((PhyCfg[PHY_RTTOAL] & 0x1U) << 11U)
+ ((0x3U & 0x3U) << 9U)
+ ((PhyCfg[PHY_CPDRSHFT] & 0x3U) << 7U)
+ ((PhyCfg[PHY_DQSRPD] & 0x1U) << 6U)
+ ((PhyCfg[PHY_DQSGPDR] & 0x1U) << 5U)
+ ((PhyCfg[PHY_DQSGODT] & 0x1U) << 3U)
+ ((PhyCfg[PHY_DQSGOE] & 0x1U) << 2U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xF00U, Val);
Val = ((PhyCfg[PHY_DXPDRMODE] & 0xFFFFU) << 16U)
+ ((0x1U & 0x1U) << 14U)
+ ((0x1U & 0x1U) << 13U)
+ ((PhyCfg[PHY_OEEN] & 0x1U) << 12U)
+ ((PhyCfg[PHY_PDREN] & 0x1U) << 11U)
+ ((PhyCfg[PHY_TEEN] & 0x1U) << 10U)
+ ((PhyCfg[PHY_DSEN] & 0x1U) << 9U)
+ ((PhyCfg[PHY_DMEN] & 0x1U) << 8U)
+ ((PhyCfg[PHY_DQEN] & 0xFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xF04U, Val);
Val = ((PhyCfg[PHY_DXOEMODE] & 0xFFFFU) << 16U)
+ ((PhyCfg[PHY_DXTEMODE] & 0xFFFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xF08U, Val);
Val = ((PhyCfg[PHY_RDBVT] & 0x1U) << 29U)
+ ((PhyCfg[PHY_WDBVT] & 0x1U) << 28U)
+ ((PhyCfg[PHY_RGLVT] & 0x1U) << 27U)
+ ((PhyCfg[PHY_RDLVT] & 0x1U) << 26U)
+ ((PhyCfg[PHY_WDLVT] & 0x1U) << 25U)
+ ((PhyCfg[PHY_WLLVT] & 0x1U) << 24U)
+ ((PhyCfg[PHY_DSNOEMODE] & 0x3U) << 20U)
+ ((PhyCfg[PHY_DSNTEMODE] & 0x3U) << 18U)
+ ((PhyCfg[PHY_DSNPDRMODE] & 0x3U) << 16U)
+ ((PhyCfg[PHY_DMOEMODE] & 0x3U) << 14U)
+ ((PhyCfg[PHY_DMTEMODE] & 0x3U) << 12U)
+ ((PhyCfg[PHY_DMPDRMODE] & 0x3U) << 10U)
+ ((PhyCfg[PHY_DSOEMODE] & 0x3U) << 6U)
+ ((PhyCfg[PHY_DSTEMODE] & 0x3U) << 4U)
+ ((PhyCfg[PHY_DSPDRMODE] & 0x3U) << 2U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xF0CU, Val);
if (PDimmPtr->Ecc == 0U)
PhyCfg[PHY_DXREFIEN] = 0U;
else {
if (PDimmPtr->NumRankAddr == 1U)
PhyCfg[PHY_DXREFIEN] = 3U;
else
PhyCfg[PHY_DXREFIEN] = 1U;
}
Val = ((PhyCfg[PHY_DXREFIOM] & 0x7U) << 29U)
+ ((PhyCfg[PHY_DXREFPEN] & 0x1U) << 28U)
+ ((0x3U & 0x3U) << 26U)
+ ((PhyCfg[PHY_DXREFSEN] & 0x1U) << 25U)
+ ((PhyCfg[PHY_DXREFESELRANGE] & 0x1U) << 23U)
+ ((PhyCfg[PHY_DXREFESEL] & 0x7FU) << 16U)
+ ((0x1U & 0x1U) << 15U)
+ ((PhyCfg[PHY_DXREFSSEL] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFIEN] & 0xFU) << 2U)
+ ((PhyCfg[PHY_DXREFIMON] & 0x3U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xF10U, Val);
if (!PDimmPtr->PhyClkGate)
PhyCfg[PHY_GATEDXRDCLK] = 0x2U;
if (!PDimmPtr->PhyClkGate)
PhyCfg[PHY_GATEDXDDRCLK] = 0x2U;
if (!PDimmPtr->PhyClkGate)
PhyCfg[PHY_GATEDXCTLCLK] = 0x2U;
if (PDimmPtr->PllByp)
PhyCfg[PHY_PLLBYP] = 1U;
if (PDimmPtr->CtlClkFreq > 668U) {
PhyCfg[PHY_FRQSEL] = 8U;
PhyCfg[PHY_CPPC] = 5U;
PhyCfg[PHY_CPIC] = 0U;
} else if (PDimmPtr->CtlClkFreq > 560U) {
PhyCfg[PHY_FRQSEL] = 0U;
PhyCfg[PHY_CPPC] = 7U;
PhyCfg[PHY_CPIC] = 0U;
} else if (PDimmPtr->CtlClkFreq > 471U) {
PhyCfg[PHY_FRQSEL] = 1U;
PhyCfg[PHY_CPPC] = 8U;
PhyCfg[PHY_CPIC] = 0U;
} else if (PDimmPtr->CtlClkFreq > 396U) {
PhyCfg[PHY_FRQSEL] = 2U;
PhyCfg[PHY_CPPC] = 9U;
PhyCfg[PHY_CPIC] = 0U;
} else if (PDimmPtr->CtlClkFreq > 332U) {
PhyCfg[PHY_FRQSEL] = 3U;
PhyCfg[PHY_CPPC] = 10U;
PhyCfg[PHY_CPIC] = 0U;
} else if (PDimmPtr->CtlClkFreq > 279U) {
PhyCfg[PHY_FRQSEL] = 4U;
PhyCfg[PHY_CPPC] = 6U;
PhyCfg[PHY_CPIC] = 1U;
} else if (PDimmPtr->CtlClkFreq > 235U) {
PhyCfg[PHY_FRQSEL] = 5U;
PhyCfg[PHY_CPPC] = 8U;
} else if (PDimmPtr->CtlClkFreq > 197U) {
PhyCfg[PHY_FRQSEL] = 6U;
PhyCfg[PHY_CPPC] = 9U;
PhyCfg[PHY_CPIC] = 2U;
} else if (PDimmPtr->CtlClkFreq >= 166U) {
PhyCfg[PHY_FRQSEL] = 7U;
PhyCfg[PHY_CPPC] = 10U;
PhyCfg[PHY_CPIC] = 3U;
}
if (((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3)) &&
((PDimmPtr->GateExt == 1U))) {
if (PDimmPtr->NoGateExtNoTrain == 1U) {
PhyCfg[PHY_DQSGX] = 0x0U;
} else {
PhyCfg[PHY_DQSGX] = 0x3U;
}
} else {
PhyCfg[PHY_DQSGX] = 0x0U;
}
PhyCfg[PHY_DXSR] = 0x3U;
if ((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) ||
((PDimmPtr->MemType == SPD_MEMTYPE_DDR4) &&
PDimmPtr->WrPreamble))
PhyCfg[PHY_PREOEX] = 0x3U;
if (PDimmPtr->Preoex != 0U)
PhyCfg[PHY_PREOEX] = PDimmPtr->Preoex;
if (PDimmPtr->PhyDbiMode && PDimmPtr->RdDbi)
PhyCfg[PHY_RDBI] = 1U;
if (PDimmPtr->PhyDbiMode && PDimmPtr->WrDbi)
PhyCfg[PHY_WDBI] = 1U;
PhyCfg[PHY_DXDACRANGE] = 0x7U;
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4)
PhyCfg[PHY_DXIOM] = 0x2U;
else if (PDimmPtr->MemType == SPD_MEMTYPE_DDR3)
PhyCfg[PHY_DXIOM] = 0x0U;
else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4)
PhyCfg[PHY_DXIOM] = 0x4U;
else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3)
PhyCfg[PHY_DXIOM] = 0x2U;
Val = ((PhyCfg[PHY_GATEDXRDCLK] & 0x3U) << 28U)
+ ((PhyCfg[PHY_GATEDXDDRCLK] & 0x3U) << 26U)
+ ((PhyCfg[PHY_GATEDXCTLCLK] & 0x3U) << 24U)
+ ((PhyCfg[PHY_CLKLEVEL] & 0x3U) << 22U)
+ ((PhyCfg[PHY_LBMODE] & 0x1U) << 21U)
+ ((PhyCfg[PHY_LBGSDQS] & 0x1U) << 20U)
+ ((PhyCfg[PHY_LBDGDQS] & 0x3U) << 18U)
+ ((PhyCfg[PHY_LBDQSS] & 0x1U) << 17U)
+ ((0x1U & 0x1U) << 16U)
+ ((0x1U & 0x1U) << 15U)
+ ((PhyCfg[PHY_DLTST] & 0x1U) << 14U)
+ ((PhyCfg[PHY_DLTMODE] & 0x1U) << 13U)
+ ((0x3U & 0x3U) << 11U)
+ ((0x3U & 0x3U) << 9U)
+ ((0x3U & 0x3U) << 7U)
+ ((0x3U & 0x3U) << 5U)
+ ((0xFU & 0xfU) << 1U)
+ ((PhyCfg[PHY_OSCEN] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1400U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1440U, Val);
Val = ((PhyCfg[PHY_PLLBYP] & 0x1U) << 31U)
+ ((PhyCfg[PHY_PLLRST] & 0x1U) << 30U)
+ ((PhyCfg[PHY_PLLPD] & 0x1U) << 29U)
+ ((PhyCfg[PHY_RSTOPM] & 0x1U) << 28U)
+ ((PhyCfg[PHY_FRQSEL] & 0xFU) << 24U)
+ ((PhyCfg[PHY_RLOCKM] & 0x1U) << 23U)
+ ((PhyCfg[PHY_CPPC] & 0x3FU) << 17U)
+ ((PhyCfg[PHY_CPIC] & 0xFU) << 13U)
+ ((PhyCfg[PHY_GSHIFT] & 0x1U) << 12U)
+ ((PhyCfg[PHY_ATOEN] & 0x1U) << 8U)
+ ((PhyCfg[PHY_ATC] & 0xFU) << 4U)
+ ((PhyCfg[PHY_DTC] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1404U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1444U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x17C4U, Val);
Val = ((0x1U & 0x1U) << 24U)
+ ((0x1U) << 21U)
+ ((PhyCfg[PHY_DQSGX] & 0x3U) << 19U)
+ ((0x1U & 0x1U) << 18U)
+ ((0x1U & 0x1U) << 17U)
+ ((0x1U & 0x1U) << 14U)
+ ((PhyCfg[PHY_UDQIOM] & 0x1U) << 13U)
+ ((PhyCfg[PHY_DXSR] & 0x3U) << 8U)
+ ((PhyCfg[PHY_DQSNRES] & 0xFU) << 4U)
+ ((PhyCfg[PHY_DQSRES] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x141CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x145CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x17DCU, Val);
Val = ((PhyCfg[PHY_CRDEN] & 0x1U) << 23U)
+ ((PhyCfg[PHY_PREOEX] & 0x3U) << 18U)
+ ((PhyCfg[PHY_IOAG] & 0x1U) << 16U)
+ ((PhyCfg[PHY_IOLB] & 0x1U) << 15U)
+ ((0xCU & 0xfU) << 9U)
+ ((PhyCfg[PHY_RDBI] & 0x1U) << 8U)
+ ((PhyCfg[PHY_WDBI] & 0x1U) << 7U)
+ ((PhyCfg[PHY_PRFBYP] & 0x1U) << 6U)
+ ((PhyCfg[PHY_RDMODE] & 0x3U) << 4U)
+ ((PhyCfg[PHY_DISRST] & 0x1U) << 3U)
+ ((PhyCfg[PHY_DQSGLB] & 0x3U) << 1U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x142CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x146CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x14ACU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x14ECU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x152CU, Val);
Val = ((PhyCfg[PHY_DXDACRANGE] & 0x7U) << 28U)
+ ((PhyCfg[PHY_DXVREFIOM] & 0x7U) << 25U)
+ ((PhyCfg[PHY_DXIOM] & 0x7U) << 22U)
+ ((PhyCfg[PHY_DXTXM] & 0x7FFU) << 11U)
+ ((PhyCfg[PHY_DXRXM] & 0x7FFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1430U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1470U, Val);
if (PDimmPtr->BusWidth != 64U) {
PhyCfg[PHY_GATEDXRDCLK] = 0x1U;
}
if (PDimmPtr->BusWidth != 64U) {
PhyCfg[PHY_GATEDXDDRCLK] = 0x1U;
}
if (PDimmPtr->BusWidth != 64U) {
PhyCfg[PHY_GATEDXCTLCLK] = 0x1U;
}
if (PDimmPtr->BusWidth == 32U) {
PhyCfg[PHY_PLLPD] = 1U;
}
if (PDimmPtr->BusWidth == 32U) {
PhyCfg[PHY_UDQIOM] = 1U;
}
if (PDimmPtr->BusWidth == 32U) {
PhyCfg[PHY_DXIOM] = 0x1U;
}
Val = ((PhyCfg[PHY_GATEDXRDCLK] & 0x3U) << 28U)
+ ((PhyCfg[PHY_GATEDXDDRCLK] & 0x3U) << 26U)
+ ((PhyCfg[PHY_GATEDXCTLCLK] & 0x3U) << 24U)
+ ((PhyCfg[PHY_CLKLEVEL] & 0x3U) << 22U)
+ ((PhyCfg[PHY_LBMODE] & 0x1U) << 21U)
+ ((PhyCfg[PHY_LBGSDQS] & 0x1U) << 20U)
+ ((PhyCfg[PHY_LBDGDQS] & 0x3U) << 18U)
+ ((PhyCfg[PHY_LBDQSS] & 0x1U) << 17U)
+ ((0x1U & 0x1U) << 16U)
+ ((0x1U & 0x1U) << 15U)
+ ((PhyCfg[PHY_DLTST] & 0x1U) << 14U)
+ ((PhyCfg[PHY_DLTMODE] & 0x1U) << 13U)
+ ((0x3U & 0x3U) << 11U)
+ ((0x3U & 0x3U) << 9U)
+ ((0x3U & 0x3U) << 7U)
+ ((0x3U & 0x3U) << 5U)
+ ((0xFU & 0xfU) << 1U)
+ ((PhyCfg[PHY_OSCEN] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1480U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x14C0U, Val);
Val = ((PhyCfg[PHY_PLLBYP] & 0x1U) << 31U)
+ ((PhyCfg[PHY_PLLRST] & 0x1U) << 30U)
+ ((PhyCfg[PHY_PLLPD] & 0x1U) << 29U)
+ ((PhyCfg[PHY_RSTOPM] & 0x1U) << 28U)
+ ((PhyCfg[PHY_FRQSEL] & 0xFU) << 24U)
+ ((PhyCfg[PHY_RLOCKM] & 0x1U) << 23U)
+ ((PhyCfg[PHY_CPPC] & 0x3FU) << 17U)
+ ((PhyCfg[PHY_CPIC] & 0xFU) << 13U)
+ ((PhyCfg[PHY_GSHIFT] & 0x1U) << 12U)
+ ((PhyCfg[PHY_ATOEN] & 0x1U) << 8U)
+ ((PhyCfg[PHY_ATC] & 0xFU) << 4U)
+ ((PhyCfg[PHY_DTC] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1484U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x14C4U, Val);
Val = ((0x1U & 0x1U) << 24U)
+ ((0x1U & 0x1U) << 21U)
+ ((PhyCfg[PHY_DQSGX] & 0x3U) << 19U)
+ ((0x1U & 0x1U) << 18U)
+ ((0x1U & 0x1U) << 17U)
+ ((0x1U & 0x1U) << 14U)
+ ((PhyCfg[PHY_UDQIOM] & 0x1U) << 13U)
+ ((PhyCfg[PHY_DXSR] & 0x3U) << 8U)
+ ((PhyCfg[PHY_DQSNRES] & 0xFU) << 4U)
+ ((PhyCfg[PHY_DQSRES] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x149CU, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x14DCU, Val);
Val = ((PhyCfg[PHY_DXDACRANGE] & 0x7U) << 28U)
+ ((PhyCfg[PHY_DXVREFIOM] & 0x7U) << 25U)
+ ((PhyCfg[PHY_DXIOM] & 0x7U) << 22U)
+ ((PhyCfg[PHY_DXTXM] & 0x7FFU) << 11U)
+ ((PhyCfg[PHY_DXRXM] & 0x7FFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x14B0U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x14F0U, Val);
if (PDimmPtr->Ecc != 1U) {
PhyCfg[PHY_GATEDXRDCLK] = 0x1U;
PhyCfg[PHY_GATEDXDDRCLK] = 0x1U;
PhyCfg[PHY_GATEDXCTLCLK] = 0x1U;
PhyCfg[PHY_PLLPD] = 1U;
PhyCfg[PHY_UDQIOM] = 1U;
PhyCfg[PHY_DXIOM] = 1U;
}
Val = ((PhyCfg[PHY_GATEDXRDCLK] & 0x3U) << 28U)
+ ((PhyCfg[PHY_GATEDXDDRCLK] & 0x3U) << 26U)
+ ((PhyCfg[PHY_GATEDXCTLCLK] & 0x3U) << 24U)
+ ((PhyCfg[PHY_CLKLEVEL] & 0x3U) << 22U)
+ ((PhyCfg[PHY_LBMODE] & 0x1U) << 21U)
+ ((PhyCfg[PHY_LBGSDQS] & 0x1U) << 20U)
+ ((PhyCfg[PHY_LBDGDQS] & 0x3U) << 18U)
+ ((PhyCfg[PHY_LBDQSS] & 0x1U) << 17U)
+ ((0x1U & 0x1U) << 16U)
+ ((0x1U & 0x1U) << 15U)
+ ((PhyCfg[PHY_DLTST] & 0x1U) << 14U)
+ ((PhyCfg[PHY_DLTMODE] & 0x1U) << 13U)
+ ((0x3U & 0x3U) << 11U)
+ ((0x3U & 0x3U) << 9U)
+ ((0x3U & 0x3U) << 7U)
+ ((0x3U & 0x3U) << 5U)
+ ((0xFU & 0xfU) << 1U)
+ ((PhyCfg[PHY_OSCEN] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1500U, Val);
Val = ((PhyCfg[PHY_PLLBYP] & 0x1U) << 31U)
+ ((PhyCfg[PHY_PLLRST] & 0x1U) << 30U)
+ ((PhyCfg[PHY_PLLPD] & 0x1U) << 29U)
+ ((PhyCfg[PHY_RSTOPM] & 0x1U) << 28U)
+ ((PhyCfg[PHY_FRQSEL] & 0xFU) << 24U)
+ ((PhyCfg[PHY_RLOCKM] & 0x1U) << 23U)
+ ((PhyCfg[PHY_CPPC] & 0x3FU) << 17U)
+ ((PhyCfg[PHY_CPIC] & 0xFU) << 13U)
+ ((PhyCfg[PHY_GSHIFT] & 0x1U) << 12U)
+ ((PhyCfg[PHY_ATOEN] & 0x1U) << 8U)
+ ((PhyCfg[PHY_ATC] & 0xFU) << 4U)
+ ((PhyCfg[PHY_DTC] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1504U, Val);
Val = ((0x1U & 0x1U) << 24U)
+ ((0x1U & 0x1U) << 21U)
+ ((PhyCfg[PHY_DQSGX] & 0x3U) << 19U)
+ ((0x1U & 0x1U) << 18U)
+ ((0x1U & 0x1U) << 17U)
+ ((0x1U & 0x1U) << 14U)
+ ((PhyCfg[PHY_UDQIOM] & 0x1U) << 13U)
+ ((PhyCfg[PHY_DXSR] & 0x3U) << 8U)
+ ((PhyCfg[PHY_DQSNRES] & 0xFU) << 4U)
+ ((PhyCfg[PHY_DQSRES] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x151CU, Val);
Val = ((PhyCfg[PHY_DXDACRANGE] & 0x7U) << 28U)
+ ((PhyCfg[PHY_DXVREFIOM] & 0x7U) << 25U)
+ ((PhyCfg[PHY_DXIOM] & 0x7U) << 22U)
+ ((PhyCfg[PHY_DXTXM] & 0x7FFU) << 11U)
+ ((PhyCfg[PHY_DXRXM] & 0x7FFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1530U, Val);
Val = ((PhyCfg[PHY_ADCP] & 0x1U) << 31U)
+ ((PhyCfg[PHY_RESERVED_30_27] & 0xFU) << 27U)
+ ((0x1U & 0x1U) << 26U)
+ ((0x3U) << 24U)
+ ((PhyCfg[PHY_RESERVED_23_19] & 0x1FU) << 19U)
+ ((PhyCfg[PHY_DTOSEL] & 0x1FU) << 14U)
+ ((0xFU & 0xfU) << 9U)
+ ((PhyCfg[PHY_OSCEN] & 0x1U) << 8U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x10U, Val);
Val = ((PhyCfg[PHY_CLRTSTAT] & 0x1U) << 31U)
+ ((PhyCfg[PHY_CLRZCAL] & 0x1U) << 30U)
+ ((PhyCfg[PHY_CLRPERR] & 0x1U) << 29U)
+ ((PhyCfg[PHY_ICPC] & 0x1U) << 28U)
+ ((0xFU & 0xffU) << 20U)
+ ((PhyCfg[PHY_INITFSMBYP] & 0x1U) << 19U)
+ ((PhyCfg[PHY_PLLFSMBYP] & 0x1U) << 18U)
+ ((PhyCfg[PHY_TREFPRD] & 0x3FFFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x18U, Val);
Val = ((0x55U & 0xffU) << 24U)
+ ((0xAAU & 0xffU) << 16U)
+ ((PhyCfg[PHY_GATEACRDCLK] & 0x3U) << 13U)
+ ((PhyCfg[PHY_GATEACDDRCLK] & 0x3U) << 11U)
+ ((PhyCfg[PHY_GATEACCTLCLK] & 0x3U) << 9U)
+ ((0x2U & 0x3U) << 6U)
+ ((PhyCfg[PHY_IOLB0] & 0x1U) << 5U)
+ ((PhyCfg[PHY_RDMODE0] & 0x3U) << 3U)
+ ((PhyCfg[PHY_DISRST0] & 0x1U) << 2U)
+ ((PhyCfg[PHY_CLKLEVEL0] & 0x3U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1CU, Val);
Val = ((0x1U & 0xffU) << 24U)
+ ((0x1U & 0xffU) << 16U)
+ ((PhyCfg[PHY_DISCNPERIOD] & 0xFFU) << 8U)
+ ((0xFU) << 4U)
+ ((0x1U) << 2U)
+ ((PhyCfg[PHY_DDLPGACT] & 0x1U) << 1U)
+ ((PhyCfg[PHY_DDLPGRW] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x24U, Val);
Val = ((PhyCfg[PHY_TPLLPD] & 0x7FFU) << 21U)
+ ((PhyCfg[PHY_TPLLGS] & 0x7FFFU) << 6U)
+ ((0x10U & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x40U, Val);
Val = ((PhyCfg[PHY_TPLLLOCK] & 0xFFFFU) << 16U)
+ ((PhyCfg[PHY_TPLLRST] & 0x1FFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x44U, Val);
PhyCfg[PHY_PLLPD] = 0U;
Val = ((PhyCfg[PHY_PLLBYP] & 0x1U) << 31U)
+ ((PhyCfg[PHY_PLLRST] & 0x1U) << 30U)
+ ((PhyCfg[PHY_PLLPD] & 0x1U) << 29U)
+ ((PhyCfg[PHY_RSTOPM] & 0x1U) << 28U)
+ ((PhyCfg[PHY_FRQSEL] & 0xFU) << 24U)
+ ((PhyCfg[PHY_RLOCKM] & 0x1U) << 23U)
+ ((PhyCfg[PHY_CPPC] & 0x3FU) << 17U)
+ ((PhyCfg[PHY_CPIC] & 0xFU) << 13U)
+ ((PhyCfg[PHY_GSHIFT] & 0x1U) << 12U)
+ ((PhyCfg[PHY_ATOEN] & 0x1U) << 8U)
+ ((PhyCfg[PHY_ATC] & 0xFU) << 4U)
+ ((PhyCfg[PHY_DTC] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x68U, Val);
Val = ((PhyCfg[PHY_RDBICLSEL] & 0x1U) << 27U)
+ ((0x2U & 0x7U) << 24U)
+ ((0x1U) << 23U)
+ ((0x1U) << 21U)
+ ((PhyCfg[PHY_SDRMODE] & 0x3U) << 19U)
+ ((PhyCfg[PHY_ATOAE] & 0x1U) << 17U)
+ ((PhyCfg[PHY_DTOOE] & 0x1U) << 16U)
+ ((PhyCfg[PHY_DTOIOM] & 0x1U) << 15U)
+ ((0x1U) << 14U)
+ ((PhyCfg[PHY_DTOODT] & 0x1U) << 12U)
+ ((PhyCfg[PHY_PUAD] & 0x3FU) << 6U)
+ ((0x1U) << 5U)
+ ((PhyCfg[PHY_CTLZUEN] & 0x1U) << 2U)
+ ((PhyCfg[PHY_RESERVED_1] & 0x1U) << 1U)
+ ((0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x90U, Val);
Val = ((PhyCfg[PHY_GPR1] & 0xFFFFFFFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xC4U, Val);
Val = ((PhyCfg[PHY_GEARDN] & 0x1U) << 31U)
+ ((PhyCfg[PHY_UBG] & 0x1U) << 30U)
+ ((PhyCfg[PHY_UDIMM] & 0x1U) << 29U)
+ ((PhyCfg[PHY_DDR2T] & 0x1U) << 28U)
+ ((PhyCfg[PHY_NOSRA] & 0x1U) << 27U)
+ ((0x1U & 0xffU) << 10U)
+ ((PhyCfg[PHY_DDRTYPE] & 0x3U) << 8U)
+ ((PhyCfg[PHY_MPRDQ] & 0x1U) << 7U)
+ ((PhyCfg[PHY_PDQ] & 0x7U) << 4U)
+ ((0x1U) << 3U)
+ ((PhyCfg[PHY_DDRMD] & 0x7U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x100U, Val);
Val = ((PhyCfg[PHY_TRRD] & 0x1FU) << 24U)
+ ((PhyCfg[PHY_TRAS] & 0x7FU) << 16U)
+ ((PhyCfg[PHY_TRP] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_TRTP] & 0x1FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x110U, Val);
Val = ((0x28U & 0x7fU) << 24U)
+ ((PhyCfg[PHY_TFAW] & 0x7FU) << 16U)
+ ((PhyCfg[PHY_TMOD] & 0x7U) << 8U)
+ ((PhyCfg[PHY_TMRD] & 0x1FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x114U, Val);
Val = ((PhyCfg[PHY_TRTW] & 0x1U) << 28U)
+ ((PhyCfg[PHY_TRTODT] & 0x1U) << 24U)
+ ((0xFU) << 16U)
+ ((PhyCfg[PHY_TXS] & 0x3FFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x118U, Val);
Val = ((0x4 & 0x7U) << 29U)
+ ((PhyCfg[PHY_TDLLK] & 0x3FFU) << 16U)
+ ((PhyCfg[PHY_TDQSCKMAX] & 0xFU) << 8U)
+ ((PhyCfg[PHY_TDQSCK] & 0x7U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x11CU, Val);
Val = ((PhyCfg[PHY_TAOND_TAOFD] & 0x3U) << 28U)
+ ((PhyCfg[PHY_TRFC] & 0x3FFU) << 16U)
+ ((0x2BU & 0x3fU) << 8U)
+ ((PhyCfg[PHY_TXP] & 0x1FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x120U, Val);
Val = ((PhyCfg[PHY_TRC] & 0xFFU) << 16U)
+ ((PhyCfg[PHY_TRCD] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_TWTR] & 0x1FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x124U, Val);
Val = ((PhyCfg[PHY_PUBWL] & 0x3FU) << 8U)
+ ((PhyCfg[PHY_PUBRL] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x128U, Val);
Val = ((PhyCfg[PHY_QCSEN] & 0x1U) << 30U)
+ ((0x1U) << 27U)
+ ((PhyCfg[PHY_ERROUTOE] & 0x1U) << 23U)
+ ((0x1U) << 22U)
+ ((PhyCfg[PHY_ERROUTPDR] & 0x1U) << 21U)
+ ((PhyCfg[PHY_ERROUTODT] & 0x1U) << 19U)
+ ((PhyCfg[PHY_LRDIMM] & 0x1U) << 18U)
+ ((PhyCfg[PHY_PARINIOM] & 0x1U) << 17U)
+ ((0x2 & 0x3U) << 4U)
+ ((PhyCfg[PHY_SOPERR] & 0x1U) << 2U)
+ ((PhyCfg[PHY_ERRNOREG] & 0x1U) << 1U)
+ ((PhyCfg[PHY_RDIMM] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x140U, Val);
Val = ((PhyCfg[PHY_A17BID] & 0x1U) << 28U)
+ ((PhyCfg[PHY_TBCMRD_L2] & 0x7U) << 24U)
+ ((PhyCfg[PHY_TBCMRD_L] & 0x7U) << 20U)
+ ((PhyCfg[PHY_TBCMRD] & 0x7U) << 16U)
+ ((0xC80U & 0x3fffU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x144U, Val);
Val = ((PhyCfg[PHY_RC7] & 0xFU) << 28U)
+ ((PhyCfg[PHY_RC6] & 0xFU) << 24U)
+ ((PhyCfg[PHY_RC5] & 0xFU) << 20U)
+ ((PhyCfg[PHY_RC4] & 0xFU) << 16U)
+ ((PhyCfg[PHY_RC3] & 0xFU) << 12U)
+ ((PhyCfg[PHY_RC2] & 0xFU) << 8U)
+ ((PhyCfg[PHY_RC1] & 0xFU) << 4U)
+ ((PhyCfg[PHY_RC0] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x150U, Val);
Val = ((PhyCfg[PHY_RC15] & 0xFU) << 28U)
+ ((PhyCfg[PHY_RC14] & 0xFU) << 24U)
+ ((PhyCfg[PHY_RC13] & 0xFU) << 20U)
+ ((PhyCfg[PHY_RC12] & 0xFU) << 16U)
+ ((PhyCfg[PHY_RC11] & 0xFU) << 12U)
+ ((PhyCfg[PHY_RC10] & 0xFU) << 8U)
+ ((PhyCfg[PHY_RC9] & 0xFU) << 4U)
+ ((PhyCfg[PHY_RC8] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x154U, Val);
Val = ((0x2U & 0x3U) << 5U)
+ ((0x2U & 0x7U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x180U, PhyCfg[PHY_R060]);
Val = ((PhyCfg[PHY_RDPST] & 0x1U) << 7U)
+ ((PhyCfg[PHY_NWR] & 0x7U) << 4U)
+ ((PhyCfg[PHY_RDPRE] & 0x1U) << 3U)
+ ((0x1U) << 2U)
+ ((PhyCfg[PHY_BL] & 0x3U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x184U, PhyCfg[PHY_R061]);
Val = ((PhyCfg[PHY_WRLEV] & 0x1U) << 7U)
+ ((PhyCfg[PHY_WLS] & 0x1U) << 6U)
+ ((PhyCfg[PHY_WL0] & 0x7U) << 3U)
+ ((PhyCfg[PHY_RL] & 0x7U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x188U, PhyCfg[PHY_R062]);
Val = ((PhyCfg[PHY_DBIWR] & 0x1U) << 7U)
+ ((PhyCfg[PHY_DBIRD] & 0x1U) << 6U)
+ ((0x6U & 0x7U) << 3U)
+ ((PhyCfg[PHY_RSVD] & 0x1U) << 2U)
+ ((PhyCfg[PHY_WRPST] & 0x1U) << 1U)
+ ((0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x18CU, PhyCfg[PHY_R063]);
Val = ((PhyCfg[PHY_RSVD_15_13] & 0x7U) << 13U)
+ ((PhyCfg[PHY_WRP] & 0x1U) << 12U)
+ ((PhyCfg[PHY_RDP] & 0x1U) << 11U)
+ ((PhyCfg[PHY_RPTM] & 0x1U) << 10U)
+ ((PhyCfg[PHY_SRA] & 0x1U) << 9U)
+ ((PhyCfg[PHY_CS2CMDL] & 0x7U) << 6U)
+ ((PhyCfg[PHY_RSVD] & 0x1U) << 5U)
+ ((PhyCfg[PHY_IVM] & 0x1U) << 4U)
+ ((PhyCfg[PHY_TCRM] & 0x1U) << 3U)
+ ((PhyCfg[PHY_TCRR] & 0x1U) << 2U)
+ ((PhyCfg[PHY_MPDM] & 0x1U) << 1U)
+ ((PhyCfg[PHY_RSVD_0] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x190U, PhyCfg[PHY_R064]);
Val = ((PhyCfg[PHY_RSVD] & 0x7U) << 13U)
+ ((PhyCfg[PHY_RDBI0] & 0x1U) << 12U)
+ ((PhyCfg[PHY_WDBI0] & 0x1U) << 11U)
+ ((PhyCfg[PHY_DM] & 0x1U) << 10U)
+ ((PhyCfg[PHY_CAPPE] & 0x1U) << 9U)
+ ((PhyCfg[PHY_RTTPARK] & 0x7U) << 6U)
+ ((PhyCfg[PHY_ODTIBPD] & 0x1U) << 5U)
+ ((PhyCfg[PHY_CAPES] & 0x1U) << 4U)
+ ((PhyCfg[PHY_CRCEC] & 0x1U) << 3U)
+ ((PhyCfg[PHY_CAPM] & 0x7U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x194U, PhyCfg[PHY_R065]);
Val = ((PhyCfg[PHY_TCCDL] & 0x7U) << 10U)
+ ((PhyCfg[PHY_RSVD_9_8] & 0x3U) << 8U)
+ ((PhyCfg[PHY_VDDQTEN] & 0x1U) << 7U)
+ ((0x1U) << 6U)
+ ((0x2BU & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x198U, PhyCfg[PHY_R066]);
Val = ((PhyCfg[PHY_RSVD_7] & 0x1U) << 7U)
+ ((PhyCfg[PHY_CAODT] & 0x7U) << 4U)
+ ((PhyCfg[PHY_RSVD_3] & 0x1U) << 3U)
+ ((PhyCfg[PHY_DQODT] & 0x7U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1ACU, Val);
Val = ((PhyCfg[PHY_VREFCA_RANGE] & 0x1U) << 6U)
+ ((PhyCfg[PHY_VREFCA] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1B0U, Val);
Val = ((PhyCfg[PHY_FSPOP] & 0x1U) << 7U)
+ ((PhyCfg[PHY_FSPWR] & 0x1U) << 6U)
+ ((PhyCfg[PHY_DMD] & 0x1U) << 5U)
+ ((PhyCfg[PHY_RRO] & 0x1U) << 4U)
+ ((0x1U) << 3U)
+ ((PhyCfg[PHY_VRO] & 0x1U) << 2U)
+ ((PhyCfg[PHY_RPT] & 0x1U) << 1U)
+ ((PhyCfg[PHY_CBT] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1B4U, Val);
Val = ((PhyCfg[PHY_VREFDQ_RANGE] & 0x1U) << 6U)
+ ((PhyCfg[PHY_VREFDQ] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1B8U, Val);
Val = ((PhyCfg[PHY_ODTD_CA] & 0x1U) << 5U)
+ ((PhyCfg[PHY_ODTE_CS] & 0x1U) << 4U)
+ ((PhyCfg[PHY_ODTE_CK] & 0x1U) << 3U)
+ ((PhyCfg[PHY_CODT] & 0x7U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x1D8U, Val);
Val = ((0x8 & 0xfU) << 28U)
+ ((PhyCfg[PHY_DTDRS] & 0x3U) << 24U)
+ ((PhyCfg[PHY_DTEXG] & 0x1U) << 23U)
+ ((PhyCfg[PHY_DTEXD] & 0x1U) << 22U)
+ ((PhyCfg[PHY_DTDSTP] & 0x1U) << 21U)
+ ((PhyCfg[PHY_DTDEN] & 0x1U) << 20U)
+ ((PhyCfg[PHY_DTDBS] & 0xFU) << 16U)
+ ((PhyCfg[PHY_DTRDBITR] & 0x3U) << 14U)
+ ((PhyCfg[PHY_DTWBDDM] & 0x1U) << 12U)
+ ((0x1 & 0xfU) << 8U)
+ ((0x1U) << 7U)
+ ((0x1U) << 6U)
+ ((0x7U & 0xfU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x200U, Val);
Val = ((PhyCfg[PHY_RANKEN] & 0x3U) << 16U)
+ ((PhyCfg[PHY_DTRANK] & 0x3U) << 12U)
+ ((0x2U & 0x7U) << 8U)
+ ((0x3 & 0x7U) << 4U)
+ ((0x1U) << 2U)
+ ((0x1U) << 1U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x204U, Val);
Val = ((0x14U & 0x1fU) << 16U)
+ ((0x10U & 0x1fU) << 8U)
+ ((PhyCfg[PHY_CA1BYTE1] & 0xFU) << 4U)
+ ((PhyCfg[PHY_CA1BYTE0] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x240U, Val);
Val = ((PhyCfg[PHY_DFTDLY] & 0xFU) << 28U)
+ ((PhyCfg[PHY_DFTZQUP] & 0x1U) << 27U)
+ ((PhyCfg[PHY_DFTDDLUP] & 0x1U) << 26U)
+ ((PhyCfg[PHY_DFTRDSPC] & 0x3U) << 20U)
+ ((0x8U & 0xfU) << 16U)
+ ((0x8U & 0xfU) << 12U)
+ ((PhyCfg[PHY_RESERVED_11_8] & 0xFU) << 8U)
+ ((PhyCfg[PHY_DFTGPULSE] & 0xFU) << 4U)
+ ((PhyCfg[PHY_DFTUPMODE] & 0x3U) << 2U)
+ ((PhyCfg[PHY_DFTDTMODE] & 0x1U) << 1U)
+ ((PhyCfg[PHY_DFTDTEN] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x250U, Val);
Val = ((PhyCfg[PHY_SEED] & 0xFFFFFFFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x414U, Val);
Val = ((PhyCfg[PHY_RESERVED_31_16] & 0xFFFFU) << 16U)
+ ((PhyCfg[PHY_ODTOEMODE] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x4F4U, Val);
Val = ((0x1U) << 29U)
+ ((0x1U) << 28U)
+ ((PhyCfg[PHY_RSTODT] & 0x1U) << 26U)
+ ((PhyCfg[PHY_CKDCC] & 0xFU) << 6U)
+ ((0x2U & 0x3U) << 4U)
+ ((0x2U & 0x3U) << 2U)
+ ((PhyCfg[PHY_ACRANKCLKSEL] & 0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x500U, Val);
Val = ((PhyCfg[PHY_CLKGENCLKGATE] & 0x1U) << 31U)
+ ((PhyCfg[PHY_ACOECLKGATE0] & 0x1U) << 30U)
+ ((PhyCfg[PHY_ACPDRCLKGATE0] & 0x1U) << 29U)
+ ((PhyCfg[PHY_ACTECLKGATE0] & 0x1U) << 28U)
+ ((PhyCfg[PHY_CKNCLKGATE0] & 0x3U) << 26U)
+ ((PhyCfg[PHY_CKCLKGATE0] & 0x3U) << 24U)
+ ((PhyCfg[PHY_ACCLKGATE0] & 0xFFFFFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x508U, Val);
Val = ((PhyCfg[PHY_PAROEMODE] & 0x3U) << 30U)
+ ((PhyCfg[PHY_BGOEMODE] & 0xFU) << 26U)
+ ((PhyCfg[PHY_BAOEMODE] & 0xFU) << 22U)
+ ((PhyCfg[PHY_A17OEMODE] & 0x3U) << 20U)
+ ((PhyCfg[PHY_A16OEMODE] & 0x3U) << 18U)
+ ((PhyCfg[PHY_ACTOEMODE] & 0x3U) << 16U)
+ ((PhyCfg[PHY_CKOEMODE] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x50CU, Val);
Val = ((PhyCfg[PHY_LBCLKGATE] & 0x1U) << 31U)
+ ((PhyCfg[PHY_ACOECLKGATE1] & 0x1U) << 30U)
+ ((PhyCfg[PHY_ACPDRCLKGATE1] & 0x1U) << 29U)
+ ((PhyCfg[PHY_ACTECLKGATE1] & 0x1U) << 28U)
+ ((PhyCfg[PHY_CKNCLKGATE1] & 0x3U) << 26U)
+ ((PhyCfg[PHY_CKCLKGATE1] & 0x3U) << 24U)
+ ((PhyCfg[PHY_ACCLKGATE1] & 0xFFFFFFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x510U, Val);
Val = ((PhyCfg[PHY_ACREFIOM] & 0x7U) << 29U)
+ ((PhyCfg[PHY_ACREFPEN] & 0x1U) << 28U)
+ ((0x1U) << 25U)
+ ((0x1U) << 24U)
+ ((PhyCfg[PHY_ACREFESELRANGE] & 0x1U) << 23U)
+ ((PhyCfg[PHY_ACREFESEL] & 0x7FU) << 16U)
+ ((0x1U) << 15U)
+ ((PhyCfg[PHY_ACREFSSEL] & 0x7FU) << 8U)
+ ((0x1U) << 7U)
+ ((PhyCfg[PHY_ACVREFISEL] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x520U, Val);
Val = ((0x7U) << 29U)
+ ((0x1U) << 28U)
+ ((PhyCfg[PHY_PDAEN] & 0x1U) << 27U)
+ ((0x4U & 0xfU) << 22U)
+ ((PhyCfg[PHY_DVSS] & 0xFU) << 18U)
+ ((0x32U & 0x3fU) << 12U)
+ ((PhyCfg[PHY_DVMIN] & 0x3FU) << 6U)
+ ((PhyCfg[PHY_DVINIT] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x528U, Val);
Val = ((PhyCfg[PHY_HVSS] & 0xFU) << 28U)
+ ((0x7FU) << 20U)
+ ((PhyCfg[PHY_HVMIN] & 0x7FU) << 12U)
+ ((PhyCfg[PHY_SHRNK] & 0x3U) << 9U)
+ ((0x1U) << 8U)
+ ((0x7U) << 5U)
+ ((0x1U) << 1U)
+ ((0x1U) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x52CU, Val);
Val = ((PhyCfg[PHY_PARBD] & 0x3FU) << 24U)
+ ((PhyCfg[PHY_A16BD] & 0x3FU) << 16U)
+ ((PhyCfg[PHY_A17BD] & 0x3FU) << 8U)
+ ((PhyCfg[PHY_ACTBD] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x544U, Val);
Val = ((PhyCfg[PHY_BG1BD] & 0x3FU) << 24U)
+ ((PhyCfg[PHY_BG0BD] & 0x3FU) << 16U)
+ ((PhyCfg[PHY_BA1BD] & 0x3FU) << 8U)
+ ((PhyCfg[PHY_BA0BD] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x548U, Val);
Val = ((PhyCfg[PHY_A03BD] & 0x3FU) << 24U)
+ ((PhyCfg[PHY_A02BD] & 0x3FU) << 16U)
+ ((PhyCfg[PHY_A01BD] & 0x3FU) << 8U)
+ ((PhyCfg[PHY_A00BD] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x558U, Val);
Val = ((PhyCfg[PHY_A07BD] & 0x3FU) << 24U)
+ ((PhyCfg[PHY_A06BD] & 0x3FU) << 16U)
+ ((PhyCfg[PHY_A05BD] & 0x3FU) << 8U)
+ ((PhyCfg[PHY_A04BD] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x55CU, Val);
Val = ((PhyCfg[PHY_A11BD] & 0x3FU) << 24U)
+ ((PhyCfg[PHY_A10BD] & 0x3FU) << 16U)
+ ((PhyCfg[PHY_A09BD] & 0x3FU) << 8U)
+ ((PhyCfg[PHY_A08BD] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x560U, Val);
Val = ((PhyCfg[PHY_A15BD] & 0x3FU) << 24U)
+ ((PhyCfg[PHY_A14BD] & 0x3FU) << 16U)
+ ((PhyCfg[PHY_A13BD] & 0x3FU) << 8U)
+ ((PhyCfg[PHY_A12BD] & 0x3FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x564U, Val);
Val = ((PhyCfg[PHY_ZQREFISELRANGE] & 0x1U) << 25U)
+ ((0x11U & 0x3fU) << 19U)
+ ((PhyCfg[PHY_PGWAIT_FRQA] & 0x3FU) << 13U)
+ ((PhyCfg[PHY_ZQREFPEN] & 0x1U) << 12U)
+ ((0x1U) << 11U)
+ ((PhyCfg[PHY_ODT_MODE] & 0x3U) << 9U)
+ ((PhyCfg[PHY_FORCE_ZCAL_VT_UPDATE] & 0x1U) << 8U)
+ ((0x2U & 0x7U) << 5U)
+ ((0x1U) << 4U)
+ ((0x2U & 0x3U) << 2U)
+ ((PhyCfg[PHY_ZCALT] & 0x1U) << 1U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x680U, Val);
Val = ((PhyCfg[PHY_ZSEGBYP] & 0x1U) << 27U)
+ ((PhyCfg[PHY_ZLE_MODE] & 0x3U) << 25U)
+ ((PhyCfg[PHY_ODT_ADJUST] & 0x7U) << 22U)
+ ((PhyCfg[PHY_PD_DRV_ADJUST] & 0x7U) << 19U)
+ ((PhyCfg[PHY_PU_DRV_ADJUST] & 0x7U) << 16U)
+ ((PhyCfg[PHY_ZPROG_DRAM_ODT] & 0xFU) << 12U)
+ ((PhyCfg[PHY_ZPROG_HOST_ODT] & 0xFU) << 8U)
+ ((PhyCfg[PHY_ZPROG_ASYM_DRV_PD] & 0xFU) << 4U)
+ ((PhyCfg[PHY_ZPROG_ASYM_DRV_PU] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x684U, Val);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x694U, 0x01e10210U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x698U, 0x01e10000U);
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
PhyCfg[PHY_PD_DRV_ADJUST] = 0x1U;
} else {
PhyCfg[PHY_PD_DRV_ADJUST] = 0U;
}
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
PhyCfg[PHY_PU_DRV_ADJUST] = 0x1U;
} else {
PhyCfg[PHY_PU_DRV_ADJUST] = 0U;
}
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
PhyCfg[PHY_ZPROG_DRAM_ODT] = 0x7U;
} else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
PhyCfg[PHY_ZPROG_DRAM_ODT] = 0xBU;
}
if (PDimmPtr->HostOdt == 40U) {
PhyCfg[PHY_ZPROG_HOST_ODT] = 0xBU;
} else if (PDimmPtr->HostOdt == 48U) {
PhyCfg[PHY_ZPROG_HOST_ODT] = 0x9U;
} else if (PDimmPtr->HostOdt == 60U) {
PhyCfg[PHY_ZPROG_HOST_ODT] = 0x7U;
} else if (PDimmPtr->HostOdt == 80U) {
PhyCfg[PHY_ZPROG_HOST_ODT] = 0x5U;
} else if (PDimmPtr->HostOdt == 120U) {
PhyCfg[PHY_ZPROG_HOST_ODT] = 0x3U;
} else {
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
if (PDimmPtr->NumRankAddr == 1U) {
PhyCfg[PHY_ZPROG_HOST_ODT] = 0x9U;
} else {
PhyCfg[PHY_ZPROG_HOST_ODT] = 0xBU;
}
} else if (PDimmPtr->MemType == SPD_MEMTYPE_DDR3) {
PhyCfg[PHY_ZPROG_HOST_ODT] = 0x6U;
} else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
PhyCfg[PHY_ZPROG_HOST_ODT] = 0xBU;
} else {
PhyCfg[PHY_ZPROG_HOST_ODT] = 0x3U;
}
}
if (PDimmPtr->HostDrv == 34U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xDU;
} else if (PDimmPtr->HostDrv == 40U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
} else if (PDimmPtr->HostDrv == 48U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x9U;
} else if (PDimmPtr->HostDrv == 60U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x7U;
} else if (PDimmPtr->HostDrv == 80U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x5U;
} else if (PDimmPtr->HostDrv == 120U) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x3U;
} else {
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xDU;
} else if ((PDimmPtr->MemType == SPD_MEMTYPE_DDR3) ||
(PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3)) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
} else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x9U;
}
}
PhyCfg[PHY_ZPROG_ASYM_DRV_PU] = PhyCfg[PHY_ZPROG_ASYM_DRV_PD];
Val = ((PhyCfg[PHY_ZSEGBYP] & 0x1U) << 27U)
+ ((PhyCfg[PHY_ZLE_MODE] & 0x3U) << 25U)
+ ((PhyCfg[PHY_ODT_ADJUST] & 0x7U) << 22U)
+ ((PhyCfg[PHY_PD_DRV_ADJUST] & 0x7U) << 19U)
+ ((PhyCfg[PHY_PU_DRV_ADJUST] & 0x7U) << 16U)
+ ((PhyCfg[PHY_ZPROG_DRAM_ODT] & 0xFU) << 12U)
+ ((PhyCfg[PHY_ZPROG_HOST_ODT] & 0xFU) << 8U)
+ ((PhyCfg[PHY_ZPROG_ASYM_DRV_PD] & 0xFU) << 4U)
+ ((PhyCfg[PHY_ZPROG_ASYM_DRV_PU] & 0xFU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x6A4U, Val);
Val = ((0x9U & 0x7fU) << 24U)
+ ((0x9U & 0x7fU) << 16U)
+ ((PhyCfg[PHY_DXREFISELR1] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFISELR0] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x714U, Val);
Val = ((0x9U & 0x3fU) << 24U)
+ ((0x9U & 0x3fU) << 16U)
+ ((0x2BU & 0x3fU) << 8U)
+ ((0x2BU & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x718U, Val);
Val = ((0x9U & 0x7fU) << 24U)
+ ((0x9U & 0x7fU) << 16U)
+ ((PhyCfg[PHY_DXREFISELR1] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFISELR0] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x814U, Val);
Val = ((0x9U & 0x3fU) << 24U)
+ ((0x9U & 0x3fU) << 16U)
+ ((0x2BU & 0x3fU) << 8U)
+ ((0x2BU & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x818U, Val);
Val = ((0x9U & 0x7fU) << 24U)
+ ((0x9U & 0x7fU) << 16U)
+ ((PhyCfg[PHY_DXREFISELR1] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFISELR0] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x914U, Val);
Val = ((0x9U & 0x3fU) << 24U)
+ ((0x9U & 0x3fU) << 16U)
+ ((0x2BU & 0x3fU) << 8U)
+ ((0x2BU & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x918U, Val);
Val = ((0x9U & 0x7fU) << 24U)
+ ((0x9U & 0x7fU) << 16U)
+ ((PhyCfg[PHY_DXREFISELR1] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFISELR0] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xA14U, Val);
Val = ((0x9U & 0x3fU) << 24U)
+ ((0x9U & 0x3fU) << 16U)
+ ((0x2BU & 0x3fU) << 8U)
+ ((0x2BU & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xA18U, Val);
Val = ((0x9U & 0x7fU) << 24U)
+ ((0x9U & 0x7fU) << 16U)
+ ((PhyCfg[PHY_DXREFISELR1] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFISELR0] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xB14U, Val);
Val = ((0x9U & 0x3fU) << 24U)
+ ((0x9U & 0x3fU) << 16U)
+ ((0x2BU & 0x3fU) << 8U)
+ ((0x2BU & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xB18U, Val);
Val = ((0x9U & 0x7fU) << 24U)
+ ((0x9U & 0x7fU) << 16U)
+ ((PhyCfg[PHY_DXREFISELR1] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFISELR0] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xC14U, Val);
Val = ((0x9U & 0x3fU) << 24U)
+ ((0x9U & 0x3fU) << 16U)
+ ((0x2BU & 0x3fU) << 8U)
+ ((0x2BU & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xC18U, Val);
Val = ((0x9U & 0x7fU) << 24U)
+ ((0x9U & 0x7fU) << 16U)
+ ((PhyCfg[PHY_DXREFISELR1] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFISELR0] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xD14U, Val);
Val = ((0x9U & 0x3fU) << 24U)
+ ((0x9U & 0x3fU) << 16U)
+ ((0x2BU & 0x3fU) << 8U)
+ ((0x2BU & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xD18U, Val);
Val = ((0x9U & 0x7fU) << 24U)
+ ((0x9U & 0x7fU) << 16U)
+ ((PhyCfg[PHY_DXREFISELR1] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFISELR0] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xE14U, Val);
Val = ((0x9U & 0x3fU) << 24U)
+ ((0x9U & 0x3fU) << 16U)
+ ((0x2BU & 0x3fU) << 8U)
+ ((0x2BU & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xE18U, Val);
Val = ((0x9U & 0x7fU) << 24U)
+ ((0x9U & 0x7fU) << 16U)
+ ((PhyCfg[PHY_DXREFISELR1] & 0x7FU) << 8U)
+ ((PhyCfg[PHY_DXREFISELR0] & 0x7FU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xF14U, Val);
Val = ((0x9U & 0x3fU) << 24U)
+ ((0x9U & 0x3fU) << 16U)
+ ((0x2BU & 0x3fU) << 8U)
+ ((0x2BU & 0x3fU) << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0xF18U, Val);
}
#if !(defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
|| defined(XPS_BOARD_ZCU208))
/*****************************************************************************/
/**
* This function calculates and writes the DDR-PHY registers
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
*
* @return None
*
*****************************************************************************/
static u32 XFsbl_PhyRegsInit(struct DdrcInitData *DdrDataPtr)
{
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
u32 PhyCfg[512U] = XFSBL_PHY_REG_DEFVAL;
u32 Status;
Status = XFsbl_PhyCalcCommonRegVal(PDimmPtr, PhyCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR3) {
Status = XFsbl_PhyCalcDdr3RegVal(PDimmPtr, PhyCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
}
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
Status = XFsbl_PhyCalcDdr4RegVal(PDimmPtr, PhyCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
}
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
Status = XFsbl_PhyCalcLpddr3RegVal(PDimmPtr, PhyCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
}
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
Status = XFsbl_PhyCalcLpddr4RegVal(PDimmPtr, PhyCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
}
XFsbl_PhyRegsWrite(PDimmPtr, PhyCfg);
END:
return Status;
}
#endif
/*****************************************************************************/
/**
* This function initializes the registers affected by enabling the Read DBI.
*
* @param PDimmPtr is pointer to DDR parameters structure
*
* @return None
*
*****************************************************************************/
static void XFsbl_RdbiWrkAround(XFsbl_DimmParams *PDimmPtr)
{
u32 CalByte[9U]={0U};
u32 DqRbd[9U][8U];
u32 Index;
u32 Index1;
XFSBL_PROG_REG(DDR_PHY_PGCR1_OFFSET, DDR_PHY_PGCR1_PUBMODE_MASK,
DDR_PHY_PGCR1_PUBMODE_SHIFT, 1U);
XFSBL_PROG_REG(DDRC_SWCTL_OFFSET, DDRC_SWCTL_SW_DONE_MASK,
DDRC_SWCTL_SW_DONE_SHIFT, 0U);
XFSBL_PROG_REG(DDRC_DFIUPD0_OFFSET, DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK,
DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT, 1U);
DqRbd[0U][0U] = ((DDR_PHY_DX0BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[0U][1U] = ((DDR_PHY_DX0BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[0U][2U] = ((DDR_PHY_DX0BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[0U][3U] = ((DDR_PHY_DX0BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[0U][4U] = ((DDR_PHY_DX0BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[0U][5U] = ((DDR_PHY_DX0BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[0U][6U] = ((DDR_PHY_DX0BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[0U][7U] = ((DDR_PHY_DX0BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[1U][0U] = ((DDR_PHY_DX1BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[1U][1U] = ((DDR_PHY_DX1BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[1U][2U] = ((DDR_PHY_DX1BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[1U][3U] = ((DDR_PHY_DX1BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[1U][4U] = ((DDR_PHY_DX1BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[1U][5U] = ((DDR_PHY_DX1BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[1U][6U] = ((DDR_PHY_DX1BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[1U][7U] = ((DDR_PHY_DX1BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[2U][0U] = ((DDR_PHY_DX2BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[2U][1U] = ((DDR_PHY_DX2BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[2U][2U] = ((DDR_PHY_DX2BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[2U][3U] = ((DDR_PHY_DX2BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[2U][4U] = ((DDR_PHY_DX2BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[2U][5U] = ((DDR_PHY_DX2BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[2U][6U] = ((DDR_PHY_DX2BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[2U][7U] = ((DDR_PHY_DX2BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[3U][0U] = ((DDR_PHY_DX3BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[3U][1U] = ((DDR_PHY_DX3BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[3U][2U] = ((DDR_PHY_DX3BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[3U][3U] = ((DDR_PHY_DX3BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[3U][4U] = ((DDR_PHY_DX3BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[3U][5U] = ((DDR_PHY_DX3BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[3U][6U] = ((DDR_PHY_DX3BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[3U][7U] = ((DDR_PHY_DX3BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[4U][0U] = ((DDR_PHY_DX4BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[4U][1U] = ((DDR_PHY_DX4BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[4U][2U] = ((DDR_PHY_DX4BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[4U][3U] = ((DDR_PHY_DX4BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[4U][4U] = ((DDR_PHY_DX4BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[4U][5U] = ((DDR_PHY_DX4BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[4U][6U] = ((DDR_PHY_DX4BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[4U][7U] = ((DDR_PHY_DX4BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[5U][0U] = ((DDR_PHY_DX5BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[5U][1U] = ((DDR_PHY_DX5BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[5U][2U] = ((DDR_PHY_DX5BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[5U][3U] = ((DDR_PHY_DX5BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[5U][4U] = ((DDR_PHY_DX5BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[5U][5U] = ((DDR_PHY_DX5BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[5U][6U] = ((DDR_PHY_DX5BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[5U][7U] = ((DDR_PHY_DX5BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[6U][0U] = ((DDR_PHY_DX6BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[6U][1U] = ((DDR_PHY_DX6BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[6U][2U] = ((DDR_PHY_DX6BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[6U][3U] = ((DDR_PHY_DX6BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[6U][4U] = ((DDR_PHY_DX6BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[6U][5U] = ((DDR_PHY_DX6BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[6U][6U] = ((DDR_PHY_DX6BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[6U][7U] = ((DDR_PHY_DX6BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[7U][0U] = ((DDR_PHY_DX7BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[7U][1U] = ((DDR_PHY_DX7BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[7U][2U] = ((DDR_PHY_DX7BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[7U][3U] = ((DDR_PHY_DX7BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[7U][4U] = ((DDR_PHY_DX7BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[7U][5U] = ((DDR_PHY_DX7BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[7U][6U] = ((DDR_PHY_DX7BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[7U][7U] = ((DDR_PHY_DX7BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
if (PDimmPtr->Ecc) {
DqRbd[8U][0U] = ((DDR_PHY_DX8BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[8U][1U] = ((DDR_PHY_DX8BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[8U][2U] = ((DDR_PHY_DX8BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[8U][3U] = ((DDR_PHY_DX8BDLR3_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
DqRbd[8U][4U] = ((DDR_PHY_DX8BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ0RBD_MASK) <<
DDR_PHY_DXBDLR_DQ0RBD_SHIFT);
DqRbd[8U][5U] = ((DDR_PHY_DX8BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ1RBD_MASK) <<
DDR_PHY_DXBDLR_DQ1RBD_SHIFT);
DqRbd[8U][6U] = ((DDR_PHY_DX8BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ2RBD_MASK) <<
DDR_PHY_DXBDLR_DQ2RBD_SHIFT);
DqRbd[8U][7U] = ((DDR_PHY_DX8BDLR4_OFFSET &
DDR_PHY_DXBDLR_DQ3RBD_MASK) <<
DDR_PHY_DXBDLR_DQ3RBD_SHIFT);
}
for (Index = 0U; Index < (PDimmPtr->Ecc ? 9U : 8U); Index++) {
CalByte[Index] = 0U;
for (Index1 = 0U; Index1 < 8U; Index1++) {
CalByte[Index] = CalByte[Index] + DqRbd[Index][Index1];
}
CalByte[Index] = CalByte[Index] / 8U;
}
XFSBL_PROG_REG(DDR_PHY_DX0BDLR5_OFFSET,
DDR_PHY_DXBDLR5_DMRBD_MASK, 0U, CalByte[0U]);
XFSBL_PROG_REG(DDR_PHY_DX1BDLR5_OFFSET,
DDR_PHY_DXBDLR5_DMRBD_MASK, 0U, CalByte[1U]);
XFSBL_PROG_REG(DDR_PHY_DX2BDLR5_OFFSET,
DDR_PHY_DXBDLR5_DMRBD_MASK, 0U, CalByte[2U]);
XFSBL_PROG_REG(DDR_PHY_DX3BDLR5_OFFSET,
DDR_PHY_DXBDLR5_DMRBD_MASK, 0U, CalByte[3U]);
XFSBL_PROG_REG(DDR_PHY_DX4BDLR5_OFFSET,
DDR_PHY_DXBDLR5_DMRBD_MASK, 0U, CalByte[4U]);
XFSBL_PROG_REG(DDR_PHY_DX5BDLR5_OFFSET,
DDR_PHY_DXBDLR5_DMRBD_MASK, 0U, CalByte[5U]);
XFSBL_PROG_REG(DDR_PHY_DX6BDLR5_OFFSET,
DDR_PHY_DXBDLR5_DMRBD_MASK, 0U, CalByte[6U]);
XFSBL_PROG_REG(DDR_PHY_DX7BDLR5_OFFSET,
DDR_PHY_DXBDLR5_DMRBD_MASK, 0U, CalByte[7U]);
if (PDimmPtr->Ecc) {
XFSBL_PROG_REG(DDR_PHY_DX8BDLR5_OFFSET,
DDR_PHY_DXBDLR5_DMRBD_MASK, 0U, CalByte[8U]);
}
XFSBL_PROG_REG(DDRC_DFIUPD0_OFFSET,
DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK,
DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT, 0U);
XFSBL_PROG_REG(DDRC_SWCTL_OFFSET,
DDRC_SWCTL_SW_DONE_MASK,
DDRC_SWCTL_SW_DONE_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_PGCR1_OFFSET,
DDR_PHY_PGCR1_PUBMODE_MASK,
DDR_PHY_PGCR1_PUBMODE_SHIFT, 0U);
}
/*****************************************************************************/
/**
* This function initializes the registers affected by enabling the Read DBI.
*
* @param PDimmPtr is pointer to DDR parameters structure
*
* @return None
*
*****************************************************************************/
static u32 XFsbl_DdrPllBypass(u32 En)
{
XFSBL_PROG_REG(DDR_QOS_CTRL_DDRPHY_CTRL_OFFSET,
DDR_QOS_CTRL_DDRPHY_CTRL_BYP_MODE_MASK,
DDR_QOS_CTRL_DDRPHY_CTRL_BYP_MODE_SHIFT, En);
XFSBL_PROG_REG(DDR_PHY_PLLCR0_OFFSET, DDR_PHY_PLLCR0_PLLBYP_MASK,
DDR_PHY_PLLCR0_PLLBYP_SHIFT, En);
XFSBL_PROG_REG(DDR_PHY_DX8SL0PLLCR0_OFFSET,
DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK,
DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT, En);
XFSBL_PROG_REG(DDR_PHY_DX8SL1PLLCR0_OFFSET,
DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK,
DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT, En);
XFSBL_PROG_REG(DDR_PHY_DX8SL2PLLCR0_OFFSET,
DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK,
DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT, En);
XFSBL_PROG_REG(DDR_PHY_DX8SL3PLLCR0_OFFSET,
DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK,
DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT, En);
XFSBL_PROG_REG(DDR_PHY_DX8SL4PLLCR0_OFFSET,
DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK,
DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT, En);
XFSBL_PROG_REG(DDR_PHY_PLLCR0_OFFSET, DDR_PHY_PLLCR0_PLLRST_MASK,
DDR_PHY_PLLCR0_PLLRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX8SL0PLLCR0_OFFSET,
DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK,
DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX8SL1PLLCR0_OFFSET,
DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK,
DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX8SL2PLLCR0_OFFSET,
DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK,
DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX8SL3PLLCR0_OFFSET,
DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK,
DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX8SL4PLLCR0_OFFSET,
DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK,
DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_QOS_CTRL_DDR_CLK_CTRL_OFFSET,
DDR_QOS_CTRL_DDR_CLK_CTRL_CLKACT_MASK,
DDR_QOS_CTRL_DDR_CLK_CTRL_CLKACT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_PLLCR0_OFFSET, DDR_PHY_PLLCR0_PLLRST_MASK,
DDR_PHY_PLLCR0_PLLRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL0PLLCR0_OFFSET,
DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK,
DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL1PLLCR0_OFFSET,
DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK,
DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL2PLLCR0_OFFSET,
DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK,
DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL3PLLCR0_OFFSET,
DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK,
DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL4PLLCR0_OFFSET,
DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK,
DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_QOS_CTRL_DDR_CLK_CTRL_OFFSET,
DDR_QOS_CTRL_DDR_CLK_CTRL_CLKACT_MASK,
DDR_QOS_CTRL_DDR_CLK_CTRL_CLKACT_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_PGCR1_OFFSET,
DDR_PHY_PGCR1_PHYHRST_MASK,
DDR_PHY_PGCR1_PHYHRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL0OSC_OFFSET,
DDR_PHY_DX8SL0OSC_PHYHRST_MASK,
DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL1OSC_OFFSET,
DDR_PHY_DX8SL1OSC_PHYHRST_MASK,
DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL2OSC_OFFSET,
DDR_PHY_DX8SL2OSC_PHYHRST_MASK,
DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL3OSC_OFFSET,
DDR_PHY_DX8SL3OSC_PHYHRST_MASK,
DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL4OSC_OFFSET,
DDR_PHY_DX8SL4OSC_PHYHRST_MASK,
DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_PGCR1_OFFSET, DDR_PHY_PGCR1_PHYHRST_MASK,
DDR_PHY_PGCR1_PHYHRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX8SL0OSC_OFFSET,
DDR_PHY_DX8SL0OSC_PHYHRST_MASK,
DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX8SL1OSC_OFFSET,
DDR_PHY_DX8SL1OSC_PHYHRST_MASK,
DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX8SL2OSC_OFFSET,
DDR_PHY_DX8SL2OSC_PHYHRST_MASK,
DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX8SL3OSC_OFFSET,
DDR_PHY_DX8SL3OSC_PHYHRST_MASK,
DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX8SL4OSC_OFFSET,
DDR_PHY_DX8SL4OSC_PHYHRST_MASK,
DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT, 1U);
return 0U;
}
/*****************************************************************************/
/**
* This function enables/disables the DFI Init in DDR
*
* @param Value is the value to be set in DFI Misc Control Register
*
* @return None
*
*****************************************************************************/
static void XFsbl_CfgDfiInitComplete(u32 Value)
{
u32 RegVal;
RegVal = Xil_In32(XFSBL_DDRC_BASE_ADDR + 0x1B0U);
RegVal &= ~(0x1U << 0U);
RegVal |= (Value << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x1B0U, RegVal);
}
/*****************************************************************************/
/**
* This function enables/disables the Software Intervention in DDR
*
* @param Value is the value to be set in MR Control Register
*
* @return None
*
*****************************************************************************/
static void XFsbl_CfgSwInitInt(u32 Value)
{
u32 RegVal;
RegVal = Xil_In32(XFSBL_DDRC_BASE_ADDR + 0x10U);
RegVal &= ~(0x1U << 3U);
RegVal |= (Value << 3U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x10U, RegVal);
}
/*****************************************************************************/
/**
* This function sets the Mode Register with specific rank of DDR
*
* @param Addr is the Address of the MR Register
* @param Rank is the rank of the DDR
* @param Mr07 is the value to be set in MR Register
*
* @return None
*
*****************************************************************************/
static void XFsbl_MrsFunc(u32 Addr, u32 Rank, u32 Mr07)
{
u32 Val;
u32 RegVal;
Val = ((Addr & 0x3FFFFU) << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x14U, Val);
RegVal = Xil_In32(XFSBL_DDRC_BASE_ADDR + 0x10U);
RegVal |= (0x1U << 31U);
RegVal &= ~(0x1U << 31U);
RegVal |= (0x1U << 31U);
if (Mr07 != 0U) {
RegVal &= ~(0xFU << 12U);
RegVal |= (Mr07 << 12U);
}
RegVal &= ~(0x3U << 4U);
RegVal |= (Rank << 4U);
RegVal &= ~(0x1U << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x10U, RegVal);
RegVal = Xil_In32(DDRC_MRSTAT_OFFSET);
while ((RegVal & 0x1U) != 0x0U)
RegVal = Xil_In32(DDRC_MRSTAT_OFFSET);
for (u32 i = 0U; i < 10U; i++) {
RegVal = Xil_In32(DDRC_MRSTAT_OFFSET);
}
}
/*****************************************************************************/
/**
* This function performs the DDR/PHY training sequence to initialize the DDR
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
*
* @return Returns XFSBL_SUCCESS or XFSBL_FAILURE
*
*****************************************************************************/
static u32 XFsbl_DdrcPhyTraining(struct DdrcInitData *DdrDataPtr)
{
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
u32 ActiveRanks;
u32 PollVal = 0U;
u32 CurTRefPrd;
u32 RegVal = 0U;
u32 PllRetry = 100U;
u32 PllLocked = 0U;
u32 Puad;
u32 Status = XFSBL_FAILURE;
ActiveRanks = Xil_In32(XFSBL_DDRC_BASE_ADDR + 0x0000U);
while ((PllRetry > 0U) && (!PllLocked)) {
if ((PllRetry % 10U) == 0U) {
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x00040010U);
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x00040011U);
}
while ((Xil_In32(DDR_PHY_PGSR0_OFFSET) & 0x1U) != 1U);
PllLocked = (Xil_In32(DDR_PHY_PGSR0_OFFSET) & 0x80000000U) >> 31U;
PllLocked &= (Xil_In32(DDR_PHY_DX0GSR0_OFFSET) & 0x10000U) >> 16U;
PllLocked &= (Xil_In32(DDR_PHY_DX2GSR0_OFFSET) & 0x10000U) >> 16U;
if (PDimmPtr->BusWidth == 64U) {
PllLocked &= (Xil_In32(DDR_PHY_DX4GSR0_OFFSET) & 0x10000U) >> 16U;
PllLocked &= (Xil_In32(DDR_PHY_DX6GSR0_OFFSET) & 0x10000U) >> 16U;
}
if (PDimmPtr->Ecc) {
PllLocked &= (Xil_In32(DDR_PHY_DX8GSR0_OFFSET) & 0x10000U) >> 16U;
}
PllRetry--;
}
Xil_Out32(DDR_PHY_GPR1_OFFSET, Xil_In32(DDR_PHY_GPR1_OFFSET) | (PllRetry << 16U));
if (PllLocked == 0U) {
XFsbl_Printf(DEBUG_INFO,"DDR-PHY Training failed\n\r");
/* Do nothing as Status is initialized to XFSBL_FAILURE */
goto END;
}
RegVal = ((PDimmPtr->RDimm ? 0x1U : 0x0U) << 19U) | (0x1U << 18U) | 0x73U;
/* Now PLL lock is done, resume with other training */
RegVal = RegVal & ~DDR_PHY_PIR_PLLINIT_MASK;
/* End of pll lock retry */
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x4U, RegVal);
if (PDimmPtr->PllByp) {
XFsbl_DdrPllBypass(1U);
}
XFSBL_POLL(DDR_PHY_PGSR0_OFFSET, 0xFU, 0xFU);
XFSBL_PROG_REG(DDR_PHY_PIR_OFFSET, DDR_PHY_PIR_INIT_MASK,
DDR_PHY_PIR_INIT_SHIFT, 1U);
XFSBL_POLL(DDR_PHY_PGSR0_OFFSET, 0xFFU, 0x1FU);
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
XFsbl_CfgSwInitInt(1U);
XFsbl_CfgDfiInitComplete(1U);
XFsbl_MrsFunc(0x331U, ActiveRanks, 0U);
XFsbl_MrsFunc(0xB36U, ActiveRanks, 0U);
if ((PDimmPtr->Zc1656) || (PDimmPtr->HasEccComp)) {
XFsbl_MrsFunc(0xC4DU, ActiveRanks, 0U);
if (PDimmPtr->Lp4NoOdt) {
XFsbl_MrsFunc(0xE6EU, ActiveRanks, 0U);
} else {
XFsbl_MrsFunc(0xE1EU, ActiveRanks, 0U);
}
XFsbl_MrsFunc(0x1606U, ActiveRanks, 0U);
} else {
XFsbl_MrsFunc(0xC21U, ActiveRanks, 0U);
if (PDimmPtr->Lp4NoOdt) {
XFsbl_MrsFunc(0xE6FU, ActiveRanks, 0U);
} else {
XFsbl_MrsFunc(0xE19U, ActiveRanks, 0U);
}
XFsbl_MrsFunc(0x1616U, ActiveRanks, 0U);
}
XFsbl_CfgSwInitInt(0U);
}
if ((PDimmPtr->MemType == SPD_MEMTYPE_DDR4) && PDimmPtr->RDimm) {
XFsbl_CfgSwInitInt(1U);
XFsbl_CfgDfiInitComplete(1U);
if (PDimmPtr->Parity)
XFsbl_MrsFunc(0x88U, 1U, 7U);
if (PDimmPtr->AddrMirror)
XFsbl_MrsFunc(0xD8U, 1U, 7U);
if (PDimmPtr->DisOpInv)
XFsbl_MrsFunc(0x01U, 1U, 7U);
if (PDimmPtr->SpeedBin == 1866U)
XFsbl_MrsFunc(0xA1U, 1U, 7U);
if (PDimmPtr->SpeedBin == 2133U)
XFsbl_MrsFunc(0xA2U, 1U, 7U);
if (PDimmPtr->SpeedBin == 2400U)
XFsbl_MrsFunc(0xA3U, 1U, 7U);
if (PDimmPtr->SpeedBin == 2666U)
XFsbl_MrsFunc(0xA4U, 1U, 7U);
XFsbl_CfgSwInitInt(0U);
}
RegVal = Xil_In32(XFSBL_DDRC_BASE_ADDR + 0x1B0U);
RegVal |= (0x1U << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x1B0U, RegVal);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x320U, 0x1U);
XFSBL_POLL(DDRC_STAT_OFFSET, 0xFU, 1U);
if (PDimmPtr->Slowboot == 1U) {
XFSBL_PROG_REG(DDRC_DFIMISC_OFFSET,
DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK,
DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_PGCR1_OFFSET,
DDR_PHY_PGCR1_PUBMODE_MASK,
DDR_PHY_PGCR1_PUBMODE_SHIFT, 0x1U);
XFSBL_PROG_REG(DDR_PHY_PGCR6_OFFSET,
DDR_PHY_PGCR6_INHVT_MASK,
DDR_PHY_PGCR6_INHVT_SHIFT, 0x1U);
XFSBL_PROG_REG(DDR_PHY_PIR_OFFSET,
DDR_PHY_PIR_DCALPSE_MASK,
DDR_PHY_PIR_DCALPSE_SHIFT, 0x1U);
XFSBL_PROG_REG(DDR_PHY_SCHCR1_OFFSET,
DDR_PHY_SCHCR1_ALLRANK_MASK,
DDR_PHY_SCHCR1_ALLRANK_SHIFT, 0x1U);
XFSBL_PROG_REG(DDR_PHY_SCHCR0_OFFSET,
DDR_PHY_SCHCR0_CMD_MASK,
DDR_PHY_SCHCR0_CMD_SHIFT, 0x7U);
XFSBL_PROG_REG(DDR_PHY_SCHCR0_OFFSET,
DDR_PHY_SCHCR0_SP_CMD_MASK,
DDR_PHY_SCHCR0_SP_CMD_SHIFT, 0x2U);
XFSBL_PROG_REG(DDR_PHY_SCHCR0_OFFSET,
DDR_PHY_SCHCR0_SCHTRIG_MASK,
DDR_PHY_SCHCR0_SCHTRIG_SHIFT, 0x1U);
Xil_Out32(DDR_PHY_PLLCR0_OFFSET, Xil_In32(DDR_PHY_PLLCR0_OFFSET));
Xil_Out32(DDR_PHY_DX8SL0PLLCR0_OFFSET, Xil_In32(DDR_PHY_DX8SL0PLLCR0_OFFSET));
Xil_Out32(DDR_PHY_DX8SL1PLLCR0_OFFSET, Xil_In32(DDR_PHY_DX8SL1PLLCR0_OFFSET));
Xil_Out32(DDR_PHY_DX8SL2PLLCR0_OFFSET, Xil_In32(DDR_PHY_DX8SL2PLLCR0_OFFSET));
Xil_Out32(DDR_PHY_DX8SL3PLLCR0_OFFSET, Xil_In32(DDR_PHY_DX8SL3PLLCR0_OFFSET));
Xil_Out32(DDR_PHY_DX8SL4PLLCR0_OFFSET, Xil_In32(DDR_PHY_DX8SL4PLLCR0_OFFSET));
Xil_Out32(DDR_PHY_DX8SLBPLLCR0_OFFSET, Xil_In32(DDR_PHY_DX8SLBPLLCR0_OFFSET));
XFSBL_PROG_REG(DDR_PHY_PIR_OFFSET, DDR_PHY_PIR_DCALPSE_MASK,
DDR_PHY_PIR_DCALPSE_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_PIR_OFFSET, DDR_PHY_PIR_CTLDINIT_MASK,
DDR_PHY_PIR_CTLDINIT_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_PIR_OFFSET, DDR_PHY_PIR_PHYRST_MASK,
DDR_PHY_PIR_PHYRST_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_PIR_OFFSET, DDR_PHY_PIR_DCAL_MASK,
DDR_PHY_PIR_DCAL_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_PIR_OFFSET, DDR_PHY_PIR_PLLINIT_MASK,
DDR_PHY_PIR_PLLINIT_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_PIR_OFFSET, DDR_PHY_PIR_INIT_MASK,
DDR_PHY_PIR_INIT_SHIFT, 1U);
XFSBL_POLL(DDR_PHY_PGSR0_OFFSET, 0xFU, 0xFU);
XFSBL_PROG_REG(DDR_PHY_PIR_OFFSET, DDR_PHY_PIR_INIT_MASK,
DDR_PHY_PIR_INIT_SHIFT, 1U);
XFSBL_POLL(DDR_PHY_PGSR0_OFFSET, 0xFFU, 0x1FU);
XFSBL_PROG_REG(DDR_PHY_PGCR6_OFFSET, DDR_PHY_PGCR6_INHVT_MASK,
DDR_PHY_PGCR6_INHVT_SHIFT, 0x0U);
XFSBL_PROG_REG(DDR_PHY_SCHCR1_OFFSET,
DDR_PHY_SCHCR1_ALLRANK_MASK,
DDR_PHY_SCHCR1_ALLRANK_SHIFT, 0x1U);
XFSBL_PROG_REG(DDR_PHY_SCHCR0_OFFSET,
DDR_PHY_SCHCR0_CMD_MASK,
DDR_PHY_SCHCR0_CMD_SHIFT, 0x7U);
XFSBL_PROG_REG(DDR_PHY_SCHCR0_OFFSET,
DDR_PHY_SCHCR0_SP_CMD_MASK,
DDR_PHY_SCHCR0_SP_CMD_SHIFT, 0x3U);
XFSBL_PROG_REG(DDR_PHY_SCHCR0_OFFSET,
DDR_PHY_SCHCR0_SCHTRIG_MASK,
DDR_PHY_SCHCR0_SCHTRIG_SHIFT, 0x1U);
}
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
XFsbl_CfgSwInitInt(1U);
XFsbl_CfgDfiInitComplete(1U);
XFsbl_MrsFunc(0xB02U, ActiveRanks, 0U);
XFsbl_CfgSwInitInt(0U);
}
if ((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) && (PDimmPtr->Lp4catrain == 1U)) {
XFSBL_PROG_REG(DDRC_SWCTL_OFFSET, DDRC_SWCTL_SW_DONE_MASK,
DDRC_SWCTL_SW_DONE_SHIFT, 1U);
XFSBL_PROG_REG(DDRC_DFIUPD0_OFFSET,
DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK,
DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT, 1U);
XFSBL_PROG_REG(DDRC_RFSHCTL3_OFFSET,
DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK,
DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT, 1U);
XFSBL_PROG_REG(DDRC_ZQCTL0_OFFSET,
DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK,
DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT, 1U);
XFSBL_PROG_REG(DDRC_RFSHCTL3_OFFSET,
DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK,
DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT, 0U);
XFSBL_PROG_REG(DDRC_ZQCTL0_OFFSET,
DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK,
DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT, 0U);
}
XFSBL_PROG_REG(DDR_PHY_PGCR1_OFFSET, DDR_PHY_PGCR1_PUBMODE_MASK,
DDR_PHY_PGCR1_PUBMODE_SHIFT, 1U);
if ((PDimmPtr->MemType == SPD_MEMTYPE_DDR3) ||
(PDimmPtr->MemType == SPD_MEMTYPE_DDR4)) {
if (PDimmPtr->DeskewTrn == 0U)
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x0004CE01U);
else
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x0004FE01U);
} else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
if (PDimmPtr->Ddp == 1U) {
XFSBL_PROG_REG(DDR_PHY_RANKIDR_OFFSET,
DDR_PHY_RANKIDR_RANKWID_MASK,
DDR_PHY_RANKIDR_RANKWID_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_ODTCR_OFFSET,
DDR_PHY_ODTCR_WRODT_MASK,
DDR_PHY_ODTCR_WRODT_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_RANKIDR_OFFSET,
DDR_PHY_RANKIDR_RANKWID_MASK,
DDR_PHY_RANKIDR_RANKWID_SHIFT, 0U);
}
if (PDimmPtr->Zc1650)
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x0004FE01U);
else {
if (PDimmPtr->GateExt)
if (PDimmPtr->DeskewTrn == 0U)
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x0004CA05U);
else
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x0004FA05U);
else
if (PDimmPtr->DeskewTrn == 0U)
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x0004CE05U);
else
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x0004FE05U);
}
} else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
if (PDimmPtr->DeskewTrn == 0U)
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x0014CE01U);
else
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x0014FE01U);
}
if ((PDimmPtr->MemType == SPD_MEMTYPE_DDR3) ||
(PDimmPtr->MemType == SPD_MEMTYPE_DDR4)) {
PollVal = 0x80000CFFU;
} else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
if (PDimmPtr->Zc1650) {
PollVal = 0x80000FFFU;
} else {
if (PDimmPtr->GateExt)
PollVal = 0x80001CBFU;
else
PollVal = 0x80001CFFU;
}
} else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
PollVal = 0x80008CFFU;
}
if (PDimmPtr->DeskewTrn != 0U) {
PollVal |= 0x300U;
}
if (PDimmPtr->MemType != SPD_MEMTYPE_LPDDR4) {
RegVal = Xil_In32(DDR_PHY_PGSR0_OFFSET);
while (RegVal != PollVal) {
RegVal = Xil_In32(DDR_PHY_PGSR0_OFFSET);
}
} else {
while (RegVal != 0x8000007EU)
RegVal = Xil_In32(DDR_PHY_PGSR0_OFFSET);
RegVal = Xil_In32(XFSBL_DDRPHY_BASE_ADDR + 0x200U);
RegVal &= ~(0xFU << 28U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x200U, RegVal);
RegVal = Xil_In32(DDR_PHY_PGSR0_OFFSET);
while (RegVal != PollVal)
RegVal = Xil_In32(DDR_PHY_PGSR0_OFFSET);
RegVal &= ~(0xFU << 28U);
RegVal |= (0x8U << 28U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x200U, RegVal);
}
if (PDimmPtr->MemType != SPD_MEMTYPE_LPDDR4) {
RegVal = Xil_In32(DDR_PHY_PGSR0_OFFSET);
}
RegVal = ((Xil_In32(DDR_PHY_PGSR0_OFFSET) & 0x1FFF0000U) >> 18U);
if ((PDimmPtr->Vref == 1U) && (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4 ||
PDimmPtr->MemType == SPD_MEMTYPE_DDR4)) {
RegVal = Xil_In32(XFSBL_DDRPHY_BASE_ADDR + 0x200U);
RegVal &= ~(0xFU << 28U);
if (((Xil_In32(XFSBL_DDRPHY_BASE_ADDR + 0x528U) >> 27U) & 0x1U) == 0x1U) {
RegVal |= (0x1U << 28U);
}
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x200U, RegVal);
CurTRefPrd = (Xil_In32(DDR_PHY_PGCR2_OFFSET) &
DDR_PHY_PGCR2_TREFPRD_MASK) >>
DDR_PHY_PGCR2_TREFPRD_SHIFT;
XFSBL_PROG_REG(DDR_PHY_PGCR2_OFFSET,
DDR_PHY_PGCR2_TREFPRD_MASK,
DDR_PHY_PGCR2_TREFPRD_SHIFT, CurTRefPrd - 400U);
XFSBL_PROG_REG(DDR_PHY_PGCR3_OFFSET, DDR_PHY_PGCR3_RDMODE_MASK,
DDR_PHY_PGCR3_RDMODE_SHIFT, 3U);
XFSBL_PROG_REG(DDR_PHY_DX8SL0DXCTL2_OFFSET,
DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK,
DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT, 3U);
XFSBL_PROG_REG(DDR_PHY_DX8SL1DXCTL2_OFFSET,
DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK,
DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT, 3U);
XFSBL_PROG_REG(DDR_PHY_DX8SL2DXCTL2_OFFSET,
DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK,
DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT, 3U);
XFSBL_PROG_REG(DDR_PHY_DX8SL3DXCTL2_OFFSET,
DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK,
DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT, 3U);
XFSBL_PROG_REG(DDR_PHY_DX8SL4DXCTL2_OFFSET,
DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK,
DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT, 3U);
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x00060001U);
RegVal = Xil_In32(DDR_PHY_PGSR0_OFFSET);
while ((RegVal & 0x80004001U) != 0x80004001U)
RegVal = Xil_In32(DDR_PHY_PGSR0_OFFSET);
XFSBL_PROG_REG(DDR_PHY_PGCR3_OFFSET, DDR_PHY_PGCR3_RDMODE_MASK,
DDR_PHY_PGCR3_RDMODE_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL0DXCTL2_OFFSET,
DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK,
DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL1DXCTL2_OFFSET,
DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK,
DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL2DXCTL2_OFFSET,
DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK,
DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL3DXCTL2_OFFSET,
DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK,
DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8SL4DXCTL2_OFFSET,
DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK,
DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT, 0U);
RegVal = Xil_In32(XFSBL_DDRPHY_BASE_ADDR + 0x200U);
RegVal &= ~(0xFU << 28U);
RegVal |= (0x8U << 28U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x200U, RegVal);
XFSBL_PROG_REG(DDR_PHY_PGCR2_OFFSET,
DDR_PHY_PGCR2_TREFPRD_MASK,
DDR_PHY_PGCR2_TREFPRD_SHIFT, CurTRefPrd);
Xil_Out32(DDR_PHY_PIR_OFFSET, 0x0000C001U);
RegVal = Xil_In32(DDR_PHY_PGSR0_OFFSET);
while ((RegVal & 0x80000C01U) != 0x80000C01U)
RegVal = Xil_In32(DDR_PHY_PGSR0_OFFSET);
}
if (PDimmPtr->Slowboot == 1U) {
XFSBL_PROG_REG(DDRC_SWCTL_OFFSET, DDRC_SWCTL_SW_DONE_MASK,
DDRC_SWCTL_SW_DONE_SHIFT, 0U);
XFSBL_PROG_REG(DDRC_DFIMISC_OFFSET,
DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK,
DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT, 1U);
XFSBL_PROG_REG(DDRC_DFIUPD0_OFFSET,
DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK,
DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT, 0U);
XFSBL_PROG_REG(DDRC_SWCTL_OFFSET, DDRC_SWCTL_SW_DONE_MASK,
DDRC_SWCTL_SW_DONE_SHIFT, 1U);
}
RegVal = Xil_In32(XFSBL_DDRC_BASE_ADDR + 0x180U);
RegVal &= ~(0x1U << 31U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x180U, RegVal);
RegVal = Xil_In32(XFSBL_DDRC_BASE_ADDR + 0x60U);
RegVal &= ~(0x1U << 0U);
Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x60U, RegVal);
if ((PDimmPtr->RdDqsCenter) && (PDimmPtr->MemType != SPD_MEMTYPE_LPDDR4)) {
XFSBL_PROG_REG(DDR_PHY_PGCR1_OFFSET,
DDR_PHY_PGCR1_PUBMODE_MASK,
DDR_PHY_PGCR1_PUBMODE_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_PGCR1_OFFSET,
DDR_PHY_PGCR1_PUBMODE_MASK,
DDR_PHY_PGCR1_PUBMODE_SHIFT, 1U);
}
XFSBL_PROG_REG(DDR_PHY_PGCR1_OFFSET,
DDR_PHY_PGCR1_PUBMODE_MASK,
DDR_PHY_PGCR1_PUBMODE_SHIFT, 0U);
if ((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) && (PDimmPtr->Slowboot == 1U)) {
if ((PDimmPtr->RdDqsCenter) &&
(PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4)) {
XFSBL_PROG_REG(DDR_PHY_PGCR1_OFFSET,
DDR_PHY_PGCR1_PUBMODE_MASK,
DDR_PHY_PGCR1_PUBMODE_SHIFT, 0U);
}
}
if ((PDimmPtr->MemType == SPD_MEMTYPE_DDR4) && PDimmPtr->RDimm) {
if (PDimmPtr->DisOpInv && (PDimmPtr->EnOpInvAfterTrain)) {
XFsbl_MrsFunc(0x00U, 1U, 7U);
RegVal = Xil_In32(XFSBL_DDRPHY_BASE_ADDR + 0x150U);
RegVal &= ~(0x1U << 0U);
Xil_Out32(XFSBL_DDRPHY_BASE_ADDR + 0x150U, RegVal);
}
}
if (PDimmPtr->RdbiWrkAround == 1U) {
XFsbl_RdbiWrkAround(PDimmPtr);
}
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
XFsbl_CfgSwInitInt(1U);
XFsbl_CfgDfiInitComplete(1U);
XFsbl_MrsFunc(0xB02U, ActiveRanks, 0U);
XFsbl_CfgSwInitInt(0U);
}
if (PDimmPtr->WrDrift) {
Puad = (u32)XFSBL_MAX(30.0 / PDimmPtr->ClockPeriod / 2.0, 8U) / 2U;
XFSBL_PROG_REG(DDR_PHY_DSGCR_OFFSET,
DDR_PHY_DSGCR_PUAD_MASK,
DDR_PHY_DSGCR_PUAD_SHIFT, Puad);
XFSBL_PROG_REG(DDR_PHY_DSGCR_OFFSET,
DDR_PHY_DSGCR_CTLZUEN_MASK,
DDR_PHY_DSGCR_CTLZUEN_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DX0GCR3_OFFSET,
DDR_PHY_DX0GCR3_WDLVT_MASK,
DDR_PHY_DX0GCR3_WDLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX1GCR3_OFFSET,
DDR_PHY_DX1GCR3_WDLVT_MASK,
DDR_PHY_DX1GCR3_WDLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX2GCR3_OFFSET,
DDR_PHY_DX2GCR3_WDLVT_MASK,
DDR_PHY_DX2GCR3_WDLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX3GCR3_OFFSET,
DDR_PHY_DX3GCR3_WDLVT_MASK,
DDR_PHY_DX3GCR3_WDLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8GCR3_OFFSET,
DDR_PHY_DX8GCR3_WDLVT_MASK,
DDR_PHY_DX8GCR3_WDLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DTCR0_OFFSET,
DDR_PHY_DTCR0_INCWEYE_MASK,
DDR_PHY_DTCR0_INCWEYE_SHIFT, 1U);
}
if (PDimmPtr->RdDrift) {
XFSBL_PROG_REG(DDR_PHY_DQSDR0_OFFSET,
DDR_PHY_DQSDR0_DFTDTMODE_MASK,
DDR_PHY_DQSDR0_DFTDTMODE_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DQSDR0_OFFSET,
DDR_PHY_DQSDR0_DFTUPMODE_MASK,
DDR_PHY_DQSDR0_DFTUPMODE_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DQSDR0_OFFSET,
DDR_PHY_DQSDR0_DFTGPULSE_MASK,
DDR_PHY_DQSDR0_DFTGPULSE_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DQSDR0_OFFSET,
DDR_PHY_DQSDR0_DFTRDSPC_MASK,
DDR_PHY_DQSDR0_DFTRDSPC_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DQSDR0_OFFSET,
DDR_PHY_DQSDR0_DFTDLY_MASK,
DDR_PHY_DQSDR0_DFTDLY_SHIFT, 2U);
XFSBL_PROG_REG(DDR_PHY_DX0GCR3_OFFSET,
DDR_PHY_DX0GCR3_RGLVT_MASK,
DDR_PHY_DX0GCR3_RGLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX1GCR3_OFFSET,
DDR_PHY_DX1GCR3_RGLVT_MASK,
DDR_PHY_DX1GCR3_RGLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX2GCR3_OFFSET,
DDR_PHY_DX2GCR3_RGLVT_MASK,
DDR_PHY_DX2GCR3_RGLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX3GCR3_OFFSET,
DDR_PHY_DX3GCR3_RGLVT_MASK,
DDR_PHY_DX3GCR3_RGLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX4GCR3_OFFSET,
DDR_PHY_DX4GCR3_RGLVT_MASK,
DDR_PHY_DX4GCR3_RGLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX5GCR3_OFFSET,
DDR_PHY_DX5GCR3_RGLVT_MASK,
DDR_PHY_DX5GCR3_RGLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX6GCR3_OFFSET,
DDR_PHY_DX6GCR3_RGLVT_MASK,
DDR_PHY_DX6GCR3_RGLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX7GCR3_OFFSET,
DDR_PHY_DX7GCR3_RGLVT_MASK,
DDR_PHY_DX7GCR3_RGLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DX8GCR3_OFFSET,
DDR_PHY_DX8GCR3_RGLVT_MASK,
DDR_PHY_DX8GCR3_RGLVT_SHIFT, 0U);
XFSBL_PROG_REG(DDR_PHY_DQSDR1_OFFSET,
DDR_PHY_DQSDR1_DFTRDIDLC_MASK,
DDR_PHY_DQSDR1_DFTRDIDLC_SHIFT, 1U);
XFSBL_PROG_REG(DDR_PHY_DQSDR1_OFFSET,
DDR_PHY_DQSDR1_DFTRDIDLF_MASK,
DDR_PHY_DQSDR1_DFTRDIDLF_SHIFT, 10U);
XFSBL_PROG_REG(DDR_PHY_DQSDR0_OFFSET,
DDR_PHY_DQSDR0_DFTDTEN_MASK,
DDR_PHY_DQSDR0_DFTDTEN_SHIFT, 1U);
}
Status = XFSBL_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
* This function sets the DDR config parameters used to initialize the DDR
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
*
* @return None
*
*****************************************************************************/
static void XFsbl_InitilizeDdrParams(struct DdrcInitData *DdrDataPtr)
{
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
PDimmPtr->DataMask = (XFSBL_DBI_INFO & 0x4U) >> 2U;
#if (XFSBL_DBI_INFO == 1U) || (XFSBL_DBI_INFO == 4U)
PDimmPtr->RdDbi = 1U;
PDimmPtr->WrDbi = 1U;
#elif (XFSBL_DBI_INFO == 2U) || (XFSBL_DBI_INFO == 5U)
PDimmPtr->RdDbi = 1U;
PDimmPtr->WrDbi = 0U;
#elif (XFSBL_DBI_INFO == 3U) || (XFSBL_DBI_INFO == 6U)
PDimmPtr->RdDbi = 0U;
PDimmPtr->WrDbi = 1U;
#else
PDimmPtr->RdDbi = 0U;
PDimmPtr->WrDbi = 0U;
#endif
PDimmPtr->Ecc = XPAR_PSU_DDRC_0_HAS_ECC;
PDimmPtr->En2ndClk = XPAR_PSU_DDRC_0_DDR_2ND_CLOCK;
PDimmPtr->Parity = XPAR_PSU_DDRC_0_DDR_PARITY;
PDimmPtr->PwrDnEn = XPAR_PSU_DDRC_0_DDR_POWER_DOWN_ENABLE;
PDimmPtr->ClockStopEn = XPAR_PSU_DDRC_0_CLOCK_STOP;
PDimmPtr->LpAsr = XPAR_PSU_DDRC_0_DDR_LOW_POWER_AUTO_SELF_REFRESH;
PDimmPtr->TRefMode = XPAR_PSU_DDRC_0_DDR_TEMP_CONTROLLED_REFRESH;
PDimmPtr->TRefRange = XPAR_PSU_DDRC_0_DDR_MAX_OPERATING_TEMPARATURE;
PDimmPtr->Fgrm = XPAR_PSU_DDRC_0_DDR_FINE_GRANULARITY_REFRESH_MODE;
PDimmPtr->SelfRefAbort = XPAR_PSU_DDRC_0_DDR_SELF_REFRESH_ABORT;
if (((PDimmPtr->MemType == SPD_MEMTYPE_DDR4) ||
(PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4)) &&
(PDimmPtr->RdDbi == 1U)) {
PDimmPtr->RdbiWrkAround = 1U;
}
PDimmPtr->ClockPeriod = 1000.0 / PDimmPtr->FreqMhz;
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
if (PDimmPtr->WrDbi == 1U) {
PDimmPtr->DataMask = 0U;
}
if (PDimmPtr->RdDbi == 1U) {
if (PDimmPtr->FreqMhz <= 933U) {
PDimmPtr->CasLatency = PDimmPtr->CasLatency + 2U;
} else {
PDimmPtr->CasLatency = PDimmPtr->CasLatency + 3U;
}
}
}
if ((PDimmPtr->TRefRange == 1U) &&
((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) ||
(PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3))) {
PDimmPtr->ClockPeriod = 1000.0 / PDimmPtr->FreqMhz;
PDimmPtr->TRpPs += XFsbl_Ceil(1.875 / PDimmPtr->ClockPeriod) * 1000.0;
PDimmPtr->TRcdPs += XFsbl_Ceil(1.875 / PDimmPtr->ClockPeriod) * 1000.0;
PDimmPtr->TRasPs += XFsbl_Ceil(1.875 / PDimmPtr->ClockPeriod) * 1000.0;
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
PDimmPtr->TRcPs += XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod) * 1000.0;
} else {
PDimmPtr->TRcPs += XFsbl_Ceil(1.875 / PDimmPtr->ClockPeriod) * 1000.0;
}
}
if ((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) &&
((PDimmPtr->Lpddr4Samsung == 1U) ||
(PDimmPtr->Lpddr4Hynix == 1U))) {
if ((PDimmPtr->SpeedBin <= 1600U) &&
(PDimmPtr->SpeedBin > 1066U)) {
PDimmPtr->UseSetB = 1U;
} else if (PDimmPtr->SpeedBin <= 1066U) {
PDimmPtr->Lp4NoOdt = 1U;
}
}
PDimmPtr->Vref = 1U;
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
if (PDimmPtr->Fgrm == 0U) {
PDimmPtr->TRfcPs = PDimmPtr->TRfc1Ps;
}
else if (PDimmPtr->Fgrm == 1U) {
PDimmPtr->TRfcPs = PDimmPtr->TRfc2Ps;
}
else if (PDimmPtr->Fgrm == 2U) {
PDimmPtr->TRfcPs = PDimmPtr->TRfc4Ps;
}
}
else if ((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) || (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4)) {
if (PDimmPtr->PerBankRefresh) {
PDimmPtr->TRfcPs = PDimmPtr->TRfcPbPs;
} else {
PDimmPtr->TRfcPs = PDimmPtr->TRfcAbPs;
}
}
if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
PDimmPtr->ReadLatency = (PDimmPtr->FreqMhz <= 733U) ? (PDimmPtr->FreqMhz / 66U) : 12U;
}
else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
PDimmPtr->ReadLatency = (PDimmPtr->FreqMhz / 66U) + 4U;
if (PDimmPtr->RdDbi) {
if (PDimmPtr->FreqMhz <= 266U)
PDimmPtr->ReadLatency = 6U;
else if (PDimmPtr->FreqMhz <= 1066U)
PDimmPtr->ReadLatency = PDimmPtr->ReadLatency + 2U;
else if (PDimmPtr->FreqMhz <= 2133U)
PDimmPtr->ReadLatency = PDimmPtr->ReadLatency + 4U;
}
}
else
PDimmPtr->ReadLatency = PDimmPtr->AdditiveLatency + PDimmPtr->CasLatency;
if ((PDimmPtr->MemType == SPD_MEMTYPE_DDR3) || (PDimmPtr->MemType == SPD_MEMTYPE_DDR4))
PDimmPtr->WriteLatency = PDimmPtr->AdditiveLatency + PDimmPtr->CasWriteLatency;
else if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
if (PDimmPtr->FreqMhz <= 167U) {
PDimmPtr->WriteLatency = 4U;
}
else if (PDimmPtr->FreqMhz <= 400U) {
PDimmPtr->WriteLatency = 4U;
}
else if (PDimmPtr->FreqMhz <= 533U) {
PDimmPtr->WriteLatency = 4U;
}
else if (PDimmPtr->FreqMhz <= 600U) {
PDimmPtr->WriteLatency = 5U;
}
else if (PDimmPtr->FreqMhz <= 667U) {
PDimmPtr->WriteLatency = 8U;
}
else if (PDimmPtr->FreqMhz <= 733U) {
PDimmPtr->WriteLatency = 9U;
}
else if (PDimmPtr->FreqMhz <= 800U) {
PDimmPtr->WriteLatency = 9U;
}
else {
PDimmPtr->WriteLatency = 9U;
}
}
else {
if (PDimmPtr->FreqMhz <= 266U) {
PDimmPtr->WriteLatency = 4U;
PDimmPtr->WdqsOn = 0U;
PDimmPtr->WdqsOff = 15U;
} else if (PDimmPtr->FreqMhz <= 533U) {
PDimmPtr->WriteLatency = 6U;
PDimmPtr->WdqsOn = 0U;
PDimmPtr->WdqsOff = 18U;
} else if (PDimmPtr->FreqMhz <= 800U) {
PDimmPtr->WriteLatency = 8U;
if (PDimmPtr->UseSetB == 1U) PDimmPtr->WriteLatency = 12U;
PDimmPtr->WdqsOn = 0U;
PDimmPtr->WdqsOff = 21U;
} else if (PDimmPtr->FreqMhz <= 1066U) {
PDimmPtr->WriteLatency = 10U;
PDimmPtr->WdqsOn = 4U;
PDimmPtr->WdqsOff = 24U;
} else if (PDimmPtr->FreqMhz <= 1333U) {
PDimmPtr->WriteLatency = 12U;
PDimmPtr->WdqsOn = 4U;
PDimmPtr->WdqsOff = 27U;
} else if (PDimmPtr->FreqMhz <= 1600U) {
PDimmPtr->WriteLatency = 14U;
PDimmPtr->WdqsOn = 6U;
PDimmPtr->WdqsOff = 30U;
} else if (PDimmPtr->FreqMhz <= 1866U) {
PDimmPtr->WriteLatency = 16U;
PDimmPtr->WdqsOn = 6U;
PDimmPtr->WdqsOff = 33U;
} else if (PDimmPtr->FreqMhz <= 2133U) {
PDimmPtr->WriteLatency = 18U;
PDimmPtr->WdqsOn = 8U;
PDimmPtr->WdqsOff = 36U;
}
}
if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4)
{
if (PDimmPtr->Parity)
{
PDimmPtr->ParityLatency = (PDimmPtr->SpeedBin < 2400U) ? 4U : 5U;
}
}
PDimmPtr->CtlClkFreq = PDimmPtr->FreqMhz / 2U;
}
#if defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
|| defined(XPS_BOARD_ZCU208)
/*****************************************************************************/
/**
* This function calculates and writes DDR controller registers
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
*
* @return None
*
*****************************************************************************/
static u32 XFsbl_Ddr4Init(u8 *SpdData, struct DdrcInitData *DdrDataPtr)
{
XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
u32 DdrCfg[300U] = XFSBL_DDRC_REG_DEFVAL;
u32 PhyCfg[512U] = XFSBL_PHY_REG_DEFVAL;
u32 Status;
u32 RegVal;
XFsbl_ComputeDdr4Params(SpdData, DdrDataPtr);
/* Initialize the Parameters with their default values */
XFsbl_InitilizeDdrParams(DdrDataPtr);
/* Assert Reset for DDR controller */
RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
RegVal |= 0x00000008U;
Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);
Status = XFsbl_DdrcCalcCommonRegVal(DdrDataPtr, PDimmPtr, DdrCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
Status = XFsbl_DdrcCalcDdr4RegVal(PDimmPtr, DdrCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
DdrCfg[DDR_DFI_TPHY_RDCSLAT] = DdrCfg[DDR_DFI_T_RDDATA_EN] - 2U;
if (!PDimmPtr->RDimm) {
DdrCfg[DDR_DFI_TPHY_WRCSLAT] = DdrCfg[DDR_DFI_TPHY_WRLAT] - 2U;
}
/* Store the MR values which will be used for PHY Registers */
PDimmPtr->Mr = DdrCfg[DDR_MR];
PDimmPtr->Emr = DdrCfg[DDR_EMR];
PDimmPtr->Emr2 = DdrCfg[DDR_EMR2];
PDimmPtr->Emr3 = DdrCfg[DDR_EMR3];
PDimmPtr->Mr4 = DdrCfg[DDR_MR4];
PDimmPtr->Mr5 = DdrCfg[DDR_MR5];
PDimmPtr->Mr6 = DdrCfg[DDR_MR6];
XFsbl_DdrcRegsWrite(PDimmPtr, DdrCfg);
/* De-assert Reset for DDR controller */
RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
RegVal &= ~0x0000000CU;
Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);
Status = XFsbl_PhyCalcCommonRegVal(PDimmPtr, PhyCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
Status = XFsbl_PhyCalcDdr4RegVal(PDimmPtr, PhyCfg);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
XFsbl_PhyRegsWrite(PDimmPtr, PhyCfg);
Status = XFSBL_SUCCESS;
END:
return Status;
}
#endif
/*****************************************************************************/
/**
* This function Reads the DDR4 SPD from EEPROM via I2C
*
* @param DdrDataPtr is pointer to DDR Initialization Data Structure
*
* @return returns the error codes described in xfsbl_error.h on any error
* returns XFSBL_SUCCESS on success
*
*****************************************************************************/
static u32 XFsbl_IicReadSpdEeprom(u8 *SpdData)
{
XIicPs IicInstance; /* The instance of the IIC device. */
XIicPs_Config *ConfigIic;
u8 TxArray;
s32 Status;
u32 UStatus;
u32 Regval = 0U;
/* Lookup for I2C-1U device */
ConfigIic = XIicPs_LookupConfig(XPAR_PSU_I2C_1_DEVICE_ID);
if (!ConfigIic) {
UStatus = XFSBL_FAILURE;
goto END;
}
/* Initialize the I2C device */
Status = XIicPs_CfgInitialize(&IicInstance, ConfigIic,
ConfigIic->BaseAddress);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/* Set the Serial Clock for I2C */
Status = XIicPs_SetSClk(&IicInstance, XFSBL_IIC_SCLK_RATE);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Configure I2C Mux to select DDR4 SODIMM Slave
* 0x08U - Enable DDR4 SODIMM module
*/
TxArray = 0x08U;
XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U, XFSBL_MUX_ADDR);
/*
* Wait until bus is idle to start another transfer.
*/
Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
XIICPS_SR_OFFSET, Regval, (Regval & XIICPS_SR_BA_MASK) == 0x0U,
XFSBL_IIC_BUS_TIMEOUT);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Get Configuration to confirm the selection of the slave
* device.
*/
Status = XIicPs_MasterRecvPolled(&IicInstance, SpdData, 1U,
XFSBL_MUX_ADDR);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Wait until bus is idle to start another transfer.
*/
Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
XIICPS_SR_OFFSET, Regval, (Regval &
XIICPS_SR_BA_MASK) == 0x0U,
XFSBL_IIC_BUS_TIMEOUT);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Set SODIMM control address to enable access to lower
* EEPROM page (0U to 255U Bytes).
* 0x00U - Enable Read of Lower Page from EEPROM
*/
TxArray = 0x00U;
XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
XFSBL_SODIMM_CONTROL_ADDR_LOW);
/*
* Wait until bus is idle to start another transfer.
*/
Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
XIICPS_SR_OFFSET, Regval, (Regval &
XIICPS_SR_BA_MASK) == 0x0U,
XFSBL_IIC_BUS_TIMEOUT);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Configure SODIMM Slave address to select starting address of the
* read bytes.
* 0x00U - Set starting byte address of read Lowe Page from EEPROM
* This will result in to starting address of 0x149U (0x100U + 0x49U) in
* the EEPROM.
*/
TxArray = 0x00U;
XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
XFSBL_SODIMM_SLAVE_ADDR);
/*
* Wait until bus is idle to start another transfer.
*/
Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
XIICPS_SR_OFFSET, Regval, (Regval &
XIICPS_SR_BA_MASK) == 0x0U,
XFSBL_IIC_BUS_TIMEOUT);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Receive the Data of 256U Bytes from SPD EEPROM via I2C.
*/
Status = XIicPs_MasterRecvPolled(&IicInstance, SpdData, 256U,
XFSBL_SODIMM_SLAVE_ADDR);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Wait until bus is idle.
*/
Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
XIICPS_SR_OFFSET, Regval, (Regval &
XIICPS_SR_BA_MASK) == 0x0U,
XFSBL_IIC_BUS_TIMEOUT);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Set SODIMM control address to enable access to upper
* EEPROM page (256U to 511U Bytes).
* 0x01U - Enable Read of Upper Page from EEPROM
*/
TxArray = 0x01U;
XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
XFSBL_SODIMM_CONTROL_ADDR_HIGH);
/*
* Wait until bus is idle to start another transfer.
*/
Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
XIICPS_SR_OFFSET, Regval, (Regval &
XIICPS_SR_BA_MASK) == 0x0U,
XFSBL_IIC_BUS_TIMEOUT);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Configure SODIMM Slave address to select starting address of the
* read bytes.
* 0x00U - Set starting byte address of read Upper Page from EEPROM
* This will result in to starting address of 0x149U (0x100U + 0x49U) in
* the EEPROM.
*/
TxArray = 0x00U;
XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
XFSBL_SODIMM_SLAVE_ADDR);
/*
* Wait until bus is idle to start another transfer.
*/
Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
XIICPS_SR_OFFSET, Regval, (Regval &
XIICPS_SR_BA_MASK) == 0x0U,
XFSBL_IIC_BUS_TIMEOUT);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Receive the Data of 256U Bytes from SPD EEPROM via I2C.
*/
Status = XIicPs_MasterRecvPolled(&IicInstance, &SpdData[256U], 256U,
XFSBL_SODIMM_SLAVE_ADDR);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
/*
* Wait until bus is idle.
*/
Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
XIICPS_SR_OFFSET, Regval, (Regval &
XIICPS_SR_BA_MASK) == 0x0U,
XFSBL_IIC_BUS_TIMEOUT);
if (Status != XST_SUCCESS) {
UStatus = XFSBL_FAILURE;
goto END;
}
UStatus = XFSBL_SUCCESS;
END:
return UStatus;
}
/*****************************************************************************/
/**
* This function checks for the DDR SPD data and Initializes the same based on
* configuration parameters obtained from SPD data.
*
* @param None
*
* @return returns the error codes described in xfsbl_error.h on any error
* returns XFSBL_SUCCESS on success
*
*****************************************************************************/
u32 XFsbl_DdrInit(void)
{
u32 Status;
u8 SpdData[512U];
#if !(defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
|| defined(XPS_BOARD_ZCU208)) || defined(XFSBL_ENABLE_DDR_SR)
u32 RegVal;
#endif
/* Define and Initialize the DDR Initialization data */
struct DdrcInitData DdrData = {
.AddrMapCsBit0 = 0x0U,
.AddrMapRowBits2To10 = 0x0U,
};
/* Get the Model Part Number from the SPD stored in EEPROM */
Status = XFsbl_IicReadSpdEeprom(SpdData);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
#if defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
|| defined(XPS_BOARD_ZCU208)
/* ZCU102, ZCU106 and ZCU111, ZCU216 and ZCU208 Boards have support
* only for DDR4 DIMMs. Skip checking for DDR type for these boards.
*/
Status = XFsbl_Ddr4Init(SpdData, &DdrData);
if (XFSBL_SUCCESS != Status) {
Status = XFSBL_FAILURE;
goto END;
}
#else
/* Determine the DIMM parameters to be used for register writes */
Status = XFsbl_DdrComputeDimmParameters(SpdData, &DdrData);
if (Status != XFSBL_SUCCESS) {
goto END;
}
/* Initialize the Parameters with their default values */
XFsbl_InitilizeDdrParams(&DdrData);
/* Assert Reset for DDR controller */
RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
RegVal |= 0x00000008U;
Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);
/* Calculate and Write all the registers of DDR Controller */
Status = XFsbl_DdrcRegsInit(&DdrData);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
/* De-assert Reset for DDR controller */
RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
RegVal &= ~0x0000000CU;
Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);
/* Calculate and Write all the registers of DDR-PHY Controller */
Status = XFsbl_PhyRegsInit(&DdrData);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
#endif
#ifdef XFSBL_ENABLE_DDR_SR
/* Check if DDR is in self refresh mode */
RegVal = Xil_In32(XFSBL_DDR_STATUS_REGISTER_OFFSET) &
DDR_STATUS_FLAG_MASK;
if (!RegVal) {
/* Execute the Training Sequence */
Status = XFsbl_DdrcPhyTraining(&DdrData);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
}
#else
/* Execute the Training Sequence */
Status = XFsbl_DdrcPhyTraining(&DdrData);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_FAILURE;
goto END;
}
#endif
Status = XFSBL_SUCCESS;
END:
return Status;
}
#endif /* XPAR_DYNAMIC_DDR_ENABLED */
#endif /* XFSBL_PS_DDR */
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/zdma_v1_9/src/xzdma_selftest.c
/******************************************************************************
* Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xzdma_selftest.c
* @addtogroup zdma_v1_9
* @{
*
* This file contains the self-test function for the ZDMA core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 1.0 vns 2/27/15 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xzdma.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This file contains a diagnostic self-test function for the ZDMA driver.
* Refer to the header file xzdma.h for more detailed information.
*
* @param InstancePtr is a pointer to XZDma instance.
*
* @return
* - XST_SUCCESS if the test is successful.
* - XST_FAILURE if the test is failed.
*
* @note None.
*
******************************************************************************/
s32 XZDma_SelfTest(XZDma *InstancePtr)
{
u32 Data;
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
XZDMA_CH_CTRL0_OFFSET);
/* Changing DMA channel to over fetch */
XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
(Data | XZDMA_CTRL0_OVR_FETCH_MASK));
if (((u32)XZDma_ReadReg(InstancePtr->Config.BaseAddress,
XZDMA_CH_CTRL0_OFFSET) & XZDMA_CTRL0_OVR_FETCH_MASK) !=
XZDMA_CTRL0_OVR_FETCH_MASK) {
Status = (s32)XST_FAILURE;
}
else {
Status = (s32)XST_SUCCESS;
}
/* Retrieving the change settings */
XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
Data);
return Status;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/common/xpm_err.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpm_err.h
*
* This is the header file which contains status codes for the PLM, PLMI
* and loader.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 Amit 05/08/2019 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XPM_ERR_H
#define XPM_ERR_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
/************************** Constant Definitions *****************************/
/**
* @name PLM error codes description
*
* 0xXXXXYYYY - Error code format
* XXXX - PLM/LOADER/XPLMI error codes as defined in xplmi_status.h
* YYYY - Libraries / Drivers error code as defined in respective modules
*/
#define XPM_SUCCESS XST_SUCCESS
#define XPM_FAILURE XST_FAILURE
/****************************** PM Specific Errors ***********************/
/****************************** 0x2000 - 0x2007 ************************/
#define XPM_PM_INTERNAL 0x2000L /* Internal error
occurred */
#define XPM_PM_CONFLICT 0x2001L /* Conflicting require-
ments asserted */
#define XPM_PM_NO_ACCESS 0x2002L /* No access to reque-
sted node or operation */
#define XPM_PM_INVALID_NODE 0x2003L /* API does not apply¬
to node */
#define XPM_PM_DOUBLE_REQ 0x2004L /* Duplicate device
request */
#define XPM_PM_ABORT_SUSPEND 0x2005L /* Abort suspend not
allowed */
#define XPM_PM_TIMEOUT 0x2006L /* Timeout occurred */
#define XPM_PM_NODE_USED 0x2007L /* Node is used and
non-shareable */
/****************************** Generic API Errors ***********************/
/****************************** 0x2010 - 0x2020 ************************/
#define XPM_INVALID_TYPEID 0x2010 /* Invalid Reset/Shutd-
ownType */
#define XPM_ERR_WAKEUP 0x2011 /* Failed to wakeup core
*/
#define XPM_ERR_CLEANUP 0x2012 /* Failed subsys cleanup
*/
#define XPM_NO_FEATURE 0x2013 /* Feature check failed
because of unsupported1
feature */
#define XPM_ERR_VERSION 0x2014 /* Version not supported
*/
#define XPM_ERR_IOCTL 0x2015 /* IOCTL type not suppor
ted */
#define XPM_INVALID_NAME 0x2016 /* Generic Error for in-
valid name, eg. clock
name */
/****************************** Reset Based Errors ***********************/
/****************************** 0x2021 - 0x202F ************************/
#define XPM_ERR_RESET 0x2021 /* Generic Reset failure
*/
#define XPM_ERR_APU_RESET 0x2022 /* APU Reset Failure */
#define XPM_ERR_RPU_RESET 0x2023 /* RPU Reset Failure */
/***************************** State Errors ****************************/
/***************************** 0x2030 - 0x2035 ************************/
#define XPM_ERR_SETSTATE 0x2030 /* Failure to set state
*/
#define XPM_ERR_GETSTATE 0x2031 /* Failure to get curr-
ent state */
#define XPM_INVALID_STATE 0x2032 /* Entered Invalid state
*/
/***************************** Subsystem Errors *************************/
/***************************** 0x2036 - 0x2045 *************************/
#define XPM_INVALID_SUBSYSID 0x2036 /* Invalid subsystem id
passed to func */
#define XPM_ERR_SUBSYS_IDLE 0x2037 /* Unable to idle subs-
ystem */
#define XPM_ERR_SUBSYS_NOTFOUND 0x2038 /* Unable to Find subs-
ystem */
/******************************* Device Errors **************************/
/****************************** 0x2046 - 0x2055 *************************/
#define XPM_ERR_DEVICE 0x2046 /* Generic Device Error
*/
#define XPM_INVALID_DEVICEID 0x2047 /* Error when invalid Dev
Id is passed */
#define XPM_ERR_DEVICE_INIT 0x2048 /* Unable to initialize
device */
#define XPM_ERR_DEVICE_REQ 0x2049 /* Failure to request
device */
#define XPM_ERR_DEVICE_RELEASE 0x2050 /* Failue to release
device */
#define XPM_ERR_DEVICE_BRINGUP 0x2051 /* Unable to bringup de-
vice*/
#define XPM_ERR_DEVICE_STATUS 0x2052 /* Unable to get/set dev-
ice status */
/*************************** Requirement Errors ************************/
/***************************** 0x2056 - 0x2065 *************************/
#define XPM_ERR_REQMNT_REL 0x2056 /* Failure to release
requirement */
#define XPM_ERR_SET_REQ 0x2057 /* Failure to set requi-
rement */
/*************************** Clock Errors ******************************/
/***************************** 0x2066 - 0x2080 *************************/
#define XPM_ERR_SET_LATENCY 0x2066 /* Failure to set laten-
cy for a device*/
#define XPM_INVALID_CLKID 0x2067 /* Invalid clock id pas-
sed */
#define XPM_INVALID_CLK_SUBNODETYPE 0x2068 /* Invalid clock
subnode type */
/**************************** Power Errors ****************************/
/**************************** 0x2081 - 0x2095 *************************/
#define XPM_ERR_POWER_STATUS 0x2081 /* Failure to get/set
power*/
#define XPM_INVALID_PWRDOMAIN 0x2082 /* Power Domain does not
exist */
#define XPM_ERR_INIT_START 0x2083 /* Error while starting
power domain initiali
zation */
#define XPM_ERR_INIT_FINISH 0x2084 /*Error while finishing
power domain initiali-
zation */
#define XPM_ERR_SCAN_CLR 0x2085 /* Failure to scan clear
Power Domain */
#define XPM_ERR_BISR 0x2086 /* BISR Failure */
#define XPM_ERR_LBIST 0x2087 /* LBIST Failure */
#define XPM_ERR_MBIST_CLR 0x2088 /* MBIST Failure */
#define XPM_ERR_HC_PL 0x2089 /* Error while housecle-
aning PL */
#define XPM_ERR_MEM_INIT 0x208A /* Memory Initialization
*/
#define XPM_ERR_HC_CMPLT 0x208B /* Unable to finish
housecleaning */
/*************************** RPU ERRORS ******************************/
/************************** 0X2096 - 0X20A5 **************************/
#define XPM_INVALID_BOOTADDR 0x2096 /* Valid boot address
not passed */
#define XPM_INVALID_TCM_CONFIG 0x2097 /* Failure to configure
TCM */
/************************** DOMAIN ISO ERRORS ************************/
/************************** 0X20A6 - 0X20B0 **************************/
#define XPM_INVALID_ISO_IDX 0x20A6 /* Invalid Isolation in-
dex passed */
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* XPM_ERR_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/iicps_v3_11/src/xiicps_sinit.c
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_sinit.c
* @addtogroup iicps_v3_11
* @{
*
* The implementation of the XIicPs component's static initialization
* functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------------
* 1.00a drg/jz 01/30/10 First release
* 3.00 sk 01/31/15 Modified the code according to MISRAC 2012 Compliant.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xparameters.h"
#include "xiicps.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES];
/*****************************************************************************/
/**
*
* @brief
* Looks up the device configuration based on the unique device ID. A table
* contains the configuration info for each device in the system.
*
* @param DeviceId contains the ID of the device to look up the
* configuration for.
*
* @return A pointer to the configuration found or NULL if the specified
* device ID was not found. See xiicps.h for the definition of
* XIicPs_Config.
*
* @note None.
*
******************************************************************************/
XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
{
XIicPs_Config *CfgPtr = NULL;
s32 Index;
for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XIicPs_ConfigTable[Index];
break;
}
}
return (XIicPs_Config *)CfgPtr;
}
/** @} */
<file_sep>/python_drivers/tdc_client_test.py
# -*- coding: utf-8 -*-
"""
Created on Fri Jul 17 12:36:30 2020
@author: tianlab01
"""
import tdc_wrapper
tdc_client = tdc_wrapper.tdc_wrapper(15,0,tdc_wrapper.MODE_CLIENT,"192.168.56.1")
ts = tdc_client.wait_pulse(3)
print("Timestamp was " + str(ts))<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_requirement.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
#include "pm_requirement.h"
#include "pm_master.h"
#include "pm_slave.h"
#include "pm_sram.h"
#include "pm_usb.h"
#include "pm_pll.h"
#include "pm_periph.h"
#include "pm_ddr.h"
#include "pm_clock.h"
/*
* The array below is used as the heap, because dynamic memory allocation is
* not allowed by MISRA. When a requirement structure needs to be allocated
* we get the first empty structure from the array.
*/
static PmRequirement pmReqData[PM_REQUIREMENT_MAX];
/* Top of the heap = index of the first free entry in pmReqData array (heap) */
static u32 pmReqTop;
/**
* PmRequirementLink() - Link requirement struct into master's and slave's lists
* @req Pointer to the requirement structure to be linked in lists
*/
static void PmRequirementLink(PmRequirement* const req)
{
if (NULL != req->master) {
/* The req structure is becoming master's head of requirements list */
req->nextSlave = req->master->reqs;
req->master->reqs = req;
}
/* The req is becoming the head of slave's requirements list as well */
req->nextMaster = req->slave->reqs;
req->slave->reqs = req;
}
/**
* PmRequirementMalloc() - Allocate a PmRequirement structure
*
* @return Pointer to the allocated structure or NULL if there is no free
* memory
*/
static PmRequirement* PmRequirementMalloc(void)
{
PmRequirement* newReq = NULL;
if (pmReqTop < ARRAY_SIZE(pmReqData)) {
newReq = &pmReqData[pmReqTop];
pmReqTop++;
} else {
PmAlert("out of memory!\r\n");
}
return newReq;
}
/**
* PmRequirementFreeAll() - Clear all data on requirements heap
*/
void PmRequirementFreeAll(void)
{
/* Clear the used content of pmReqData */
(void)memset(pmReqData, 0U, pmReqTop * sizeof(PmRequirement));
/* Reset top of the heap */
pmReqTop = 0U;
}
/**
* PmRequirementAdd() - Add a requirement structure for master/slave pair
* @master Master that can use the slave
* @slave Slave that can be used by the master
*
* @return Pointer to the requirement if added, NULL if there is no
* free memory to add new requirement
*/
PmRequirement* PmRequirementAdd(PmMaster* const master, PmSlave* const slave)
{
PmRequirement* req = PmRequirementMalloc();
if (NULL == req) {
goto done;
}
req->master = master;
req->slave = slave;
PmRequirementLink(req);
done:
return req;
}
/**
* PmRequirementSchedule() - Schedule requirements of the master for slave
* @masterReq Pointer to master requirement structure (for a slave)
* @caps Required capabilities of slave
*
* @return Status of the operation
* - XST_SUCCESS if requirement is successfully scheduled
* - XST_NO_FEATURE if there is no state with requested
* capabilities
*
* @note Slave state will be updated according to the saved requirements
* after all processors/master suspends.
*/
s32 PmRequirementSchedule(PmRequirement* const masterReq, const u32 caps)
{
s32 status;
/* Check if slave has a state with requested capabilities */
status = PmCheckCapabilities(masterReq->slave, caps);
if (XST_SUCCESS != status) {
goto done;
}
/* Schedule setting of the requirement for later */
masterReq->nextReq = caps;
done:
return status;
}
/**
* PmRequirementUpdate() - Set slaves capabilities according to the master's
* requirements
* @masterReq Pointer to structure keeping information about the
* master's requirement
* @caps Capabilities of a slave requested by the master
*
* @return Status of the operation
*/
s32 PmRequirementUpdate(PmRequirement* const masterReq, const u32 caps)
{
s32 status;
u32 tmpCaps;
/* Check if slave has a state with requested capabilities */
status = PmCheckCapabilities(masterReq->slave, caps);
if (XST_SUCCESS != status) {
goto done;
}
/* Configure requested capabilities */
tmpCaps = masterReq->currReq;
masterReq->currReq = caps;
status = PmUpdateSlave(masterReq->slave);
if (XST_SUCCESS == status) {
/* All capabilities requested in active state are constant */
masterReq->nextReq = masterReq->currReq;
} else {
/* Remember the last setting, will report an error */
masterReq->currReq = tmpCaps;
}
done:
return status;
}
/**
* PmRequirementRequest() - Process request for new requirements
* @req Requirements determining master/slave pair
* @caps Requested capabilities
*
* @return Status of processing the request
*/
s32 PmRequirementRequest(PmRequirement* const req, const u32 caps)
{
s32 status;
req->info |= PM_MASTER_REQUESTED_SLAVE_MASK;
status = PmRequirementUpdate(req, caps);
return status;
}
/**
* PmRequirementRelease() - Process release of requirements
* @first Pointer to the requirement structure
* @scope Scope of the release
*
* @return Status of processing the release
*/
s32 PmRequirementRelease(PmRequirement* const first, const PmReleaseScope scope)
{
s32 status = XST_FAILURE;
PmRequirement* req = first;
if (RELEASE_ONE == scope) {
PmRequirementClear(req);
status = PmUpdateSlave(req->slave);
goto done;
}
while (NULL != req) {
if ((RELEASE_ALL == scope) ||
((RELEASE_UNREQUESTED == scope) && !MASTER_REQUESTED_SLAVE(req))) {
PmRequirementClear(req);
status = PmUpdateSlave(req->slave);
if (XST_SUCCESS != status) {
break;
}
} else if (MASTER_REQUESTED_SLAVE(req)) {
status = XST_SUCCESS;
} else {
/* Invalid Scope */
PmErr("Invalid scope #%d\r\n", scope);
status = XST_FAILURE;
break;
}
req = req->nextSlave;
}
done:
return status;
}
/**
* PmRequirementUpdateScheduled() - Triggers the setting for scheduled
* requirements
* @master Master which changed the state and whose scheduled requirements are
* triggered
* @swap Flag stating should current/default requirements be saved as next
*
* a) swap=false
* Set scheduled requirements of a master without swapping current/default and
* next requirements - means the current requirements will be dropped and
* default requirements has no effect. Upon every self suspend, master has to
* explicitly re-request slave requirements.
* b) swap=true
* Set scheduled requirements of a master with swapping current/default and
* next requirements (swapping means the current/default requirements will be
* saved as next, and will be configured once master wakes-up). If the master
* has default requirements, default requirements are saved as next instead of
* current requirements. Default requirements has priority over current
* requirements.
*/
s32 PmRequirementUpdateScheduled(const PmMaster* const master, const bool swap)
{
s32 status = XST_SUCCESS;
PmRequirement* req = master->reqs;
while (NULL != req) {
if (req->currReq != req->nextReq) {
u32 tmpReq = req->nextReq;
if (true == swap) {
if (0U != req->defaultReq) {
/* Master has default requirements for
* this slave, default has priority over
* current requirements.
*/
req->nextReq = req->defaultReq;
} else {
/* Save current requirements as next */
req->nextReq = req->currReq;
}
}
req->currReq = tmpReq;
/* Update slave setting */
status = PmUpdateSlave(req->slave);
/* if rom works correctly, status should be always ok */
if (XST_SUCCESS != status) {
PmErr("updating %s\r\n", req->slave->node.name);
break;
}
}
req = req->nextSlave;
}
return status;
}
/**
* PmRequirementCancelScheduled() - Called when master aborts suspend, to cancel
* scheduled requirements (slave capabilities requests)
* @master Master whose scheduled requests should be cancelled
*/
void PmRequirementCancelScheduled(const PmMaster* const master)
{
PmRequirement* req = master->reqs;
while (NULL != req) {
if (req->currReq != req->nextReq) {
/* Drop the scheduled request by making it constant */
req->nextReq = req->currReq;
}
req = req->nextSlave;
}
}
/**
* PmRequirementPreRequest() - Request requirements for master which it will not
* request for itself
* @master Master whose requirements are requested
*
* When waking up from forced power down, master may have some requirements to
* be configured before it enters active state (example TCM for RPU). Loop
* through all slaves, find such requirements and update next requirements data
* in master/slave requirement structure that will be configured.
*/
void PmRequirementPreRequest(const PmMaster* const master)
{
PmRequirement* req = master->reqs;
while (NULL != req) {
if (0U != req->preReq) {
/* Set flag to state that master is using slave */
req->info |= PM_MASTER_REQUESTED_SLAVE_MASK;
req->nextReq = req->preReq;
}
req = req->nextSlave;
}
}
/**
* PmRequirementClockRestore() - Restore clock configuration for the master's
* preallocated requirements
* @master Master for whom clock restoration is done
*
* When waking up from forced power down, clocks for the preallocated
* requirements must be restored. Loop through all slaves, find such
* requirements and restore their clock configuration.
*/
void PmRequirementClockRestore(const PmMaster* const master)
{
PmRequirement* req = master->reqs;
while (NULL != req) {
if (0U != req->preReq) {
PmClockRestore(&req->slave->node);
}
req = req->nextSlave;
}
}
/**
* PmRequirementClear() - Clear requirements
* @req Requirements to clear
*
* @note The function marks slave as unused
*/
void PmRequirementClear(PmRequirement* const req)
{
/* Clear flag - master is not using slave anymore */
req->info &= ~PM_MASTER_REQUESTED_SLAVE_MASK;
/* Release current and next requirements */
req->currReq = 0U;
req->nextReq = 0U;
}
/**
* PmRequirementGet() - Get requirement for master/slave pair
* @master Master whose request structure should be found
* @slave Slave in question
*
* @return Pointer to the requirement associated with the master/slave pair.
* NULL if such structure is not found.
*/
PmRequirement* PmRequirementGet(const PmMaster* const master,
const PmSlave* const slave)
{
PmRequirement* req = master->reqs;
while (NULL != req) {
if (slave == req->slave) {
break;
}
req = req->nextSlave;
}
return req;
}
/**
* PmRequirementGetNoMaster() - Get system requirement for a slave
* @slave Slave in question
*
* @return Pointer to the requirement or NULL if not found.
*/
PmRequirement* PmRequirementGetNoMaster(const PmSlave* const slave)
{
PmRequirement* req = slave->reqs;
while (NULL != req) {
if (NULL == req->master) {
break;
}
req = req->nextMaster;
}
return req;
}
/**
* PmRequirementSetConfig() - Set requirement configuration
* @req Requirement structure to configure
* @flags Flags to configure (is the slave currently used by the master)
* @currReq Current requirements of the master
* @defaultReq Default requirement of the master
*
* @return XST_SUCCESS if requirements are configured properly,
* XST_FAILURE otherwise
*/
s32 PmRequirementSetConfig(PmRequirement* const req, const u32 flags,
const u32 currReq, const u32 defaultReq)
{
s32 status;
status = PmCheckCapabilities(req->slave, currReq);
if (XST_SUCCESS != status) {
status = XST_FAILURE;
goto error;
}
status = PmCheckCapabilities(req->slave, defaultReq);
if (XST_SUCCESS != status) {
status = XST_FAILURE;
goto error;
}
if (0U != (PM_MASTER_REQUESTED_SLAVE_MASK & flags)) {
req->info |= PM_MASTER_REQUESTED_SLAVE_MASK;
req->currReq = currReq;
req->nextReq = currReq;
PmClockSave(&req->slave->node);
}
req->preReq = currReq;
req->defaultReq = defaultReq;
req->latencyReq = MAX_LATENCY;
goto done;
error:
PmErr("%s has no state with caps 0x%lx\r\n",
req->slave->node.name, currReq);
done:
return status;
}
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_common.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* Definitions of commonly used macros and enums in PMU Power
* Management (PM).
*********************************************************************/
#ifndef PM_COMMON_H_
#define PM_COMMON_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pmu_local.h"
#include "xpfw_default.h"
#include "xil_types.h"
#include "xpfw_ipi_manager.h"
#include "xpfw_mod_pm.h"
/*********************************************************************
* Typedefs (common use in PMU Power Management)
********************************************************************/
/*
* stdint.h is not available, and pmu-fw framework defined similar
* macros but as 0 and 1 (signed). PM, as in general, uses unsigned.
*/
#ifndef bool
typedef u8 bool;
#define true 1U
#define false 0U
#endif
typedef u32 (*const PmTranHandler)(void);
typedef struct PmNode PmNode;
/*********************************************************************
* Macros
********************************************************************/
#define pm_printf xil_printf
/*
* PM log levels. The configured log level should be specifid with:
* -DPM_LOG_LEVEL=X where X is one of the numbers defined below
*/
#define PM_ALERT 1U
#define PM_ERROR 2U
#define PM_WARNING 3U
#define PM_INFO 4U
#if defined(PM_LOG_LEVEL) && (PM_LOG_LEVEL >= PM_INFO)
#define PmInfo(...) pm_printf(__VA_ARGS__)
#else
#define PmInfo(...) {}
#endif
#if defined(PM_LOG_LEVEL) && (PM_LOG_LEVEL >= PM_WARNING)
#define PmWarn(...) xil_printf(__VA_ARGS__)
#else
#define PmWarn(...) {}
#endif
#if defined(PM_LOG_LEVEL) && (PM_LOG_LEVEL >= PM_ERROR)
#define PmErr(...) pm_printf("Err: "); xil_printf(__VA_ARGS__)
#else
#define PmErr(...) {}
#endif
#if defined(PM_LOG_LEVEL) && (PM_LOG_LEVEL >= PM_ALERT)
#define PmAlert(...) pm_printf("Alert: "); xil_printf(__VA_ARGS__)
#else
#define PmAlert(...) {}
#endif
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
/* Enable/disable macros for wake events in GPI1 register */
#define ENABLE_WAKE(mask) XPfw_RMW32(PMU_LOCAL_GPI1_ENABLE, (mask), (mask));
#define DISABLE_WAKE(mask) XPfw_RMW32(PMU_LOCAL_GPI1_ENABLE, (mask), ~(mask));
/* Macros for IPI responses (return values and callbacks) */
#define IPI_RESPONSE1(mask, arg0) \
{ \
u32 _ipi_resp_data[XPFW_IPI_MAX_MSG_LEN] = {(arg0), 0U, 0U, 0U, 0U, 0U, 0U, 0U}; \
if (XST_SUCCESS != XPfw_IpiWriteResponse(PmModPtr, (mask), \
&_ipi_resp_data[0], \
ARRAY_SIZE(_ipi_resp_data))) { \
PmWarn("Error in IPI write response\r\n"); \
} \
}
#define IPI_RESPONSE2(mask, arg0, arg1) \
{ \
u32 _ipi_resp_data[XPFW_IPI_MAX_MSG_LEN] = {(arg0), (arg1), 0U, 0U, 0U, 0U, 0U, 0U}; \
if (XST_SUCCESS != XPfw_IpiWriteResponse(PmModPtr, (mask), \
&_ipi_resp_data[0], \
ARRAY_SIZE(_ipi_resp_data))) { \
PmWarn("Error in IPI write response\r\n"); \
} \
}
#define IPI_RESPONSE3(mask, arg0, arg1, arg2) \
{ \
u32 _ipi_resp_data[XPFW_IPI_MAX_MSG_LEN] = {(arg0), (arg1), (arg2), 0U, 0U, 0U, 0U, 0U}; \
if (XST_SUCCESS != XPfw_IpiWriteResponse(PmModPtr, (mask), \
&_ipi_resp_data[0], \
ARRAY_SIZE(_ipi_resp_data))) { \
PmWarn("Error in IPI write response\r\n"); \
} \
}
#define IPI_RESPONSE4(mask, arg0, arg1, arg2, arg3) \
{ \
u32 _ipi_resp_data[XPFW_IPI_MAX_MSG_LEN] = {(arg0), (arg1), (arg2), (arg3),0U, 0U, 0U, 0U}; \
if (XST_SUCCESS != XPfw_IpiWriteResponse(PmModPtr, (mask), \
&_ipi_resp_data[0], \
ARRAY_SIZE(_ipi_resp_data))) { \
PmWarn("Error in IPI write response\r\n"); \
} \
}
#define IPI_RESPONSE5(mask, arg0, arg1, arg2, arg3, arg4) \
{ \
u32 ipi_resp_data[XPFW_IPI_MAX_MSG_LEN] = {(arg0), (arg1), (arg2), (arg3), (arg4), 0U, 0U, 0U}; \
if (XST_SUCCESS != XPfw_IpiWriteResponse(PmModPtr, (mask), \
&_ipi_resp_data[0], \
ARRAY_SIZE(_ipi_resp_data))) { \
PmWarn("Error in IPI write response\r\n"); \
} \
}
/* PMU internal capabilities used in definition of slaves' states */
#define PM_CAP_POWER 0x8U
#define PM_CAP_CLOCK 0x10U
/* Default transition latencies in us */
#define PM_DEFAULT_LATENCY 1000U
#define PM_POWER_ISLAND_LATENCY 2000U
#define PM_POWER_DOMAIN_LATENCY 10000U
/* Power consumptions of the slave components */
#define DEFAULT_POWER_ON 100U
#define DEFAULT_POWER_RETENTION 50U
#define DEFAULT_POWER_OFF 0U
/* Type of boot cold vs warm boot */
#define PM_COLD_BOOT 1U
#define PM_WARM_BOOT 2U
/* One (first) u32 is used for API call id coding */
#define PAYLOAD_API_ID 1U
/* Each API can have up to 5 arguments */
#define PAYLOAD_API_ARGS_CNT 5U
/* Number of payload elements (api id and api's arguments) */
#define PAYLOAD_ELEM_CNT (PAYLOAD_API_ID + PAYLOAD_API_ARGS_CNT)
#define MASK_OF_BITS(bits) ((1U << (bits)) - 1U)
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmRegisterContext - A pair of address/value used for saving/restoring context
* of a register
* @addr Address of a register
* @value Variable to store register content
*/
typedef struct PmRegisterContext {
const u32 addr;
u32 value;
} PmRegisterContext;
/**
* PmMemorySection - Memory region that will be processed by PMUFW
* @startAddr Start address of memory region
* @endAddr End address of memory region
*/
typedef struct PmMemorySection {
const u32 startAddr;
const u32 endAddr;
} PmMemorySection;
/*********************************************************************
* Function declarations
********************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* PM_COMMON_H_ */
<file_sep>/c_drivers/drivers/gpio.h
#ifndef _GPIO_H_
#define _GPIO_H_
#include "xgpio.h"
uint8_t gpio_init();
void gpio_set_pin(u8 pin_num, u8 value);
void gpio_reset_pulse_gen();
void gpio_send_command(uint32_t value);
void gpio_queue_pulse(uint32_t value);
u8 gpio_get_busy();//Returns 1 if board is busy transmitting something
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/usbpsu_v1_7/src/xusbpsu_controltransfers.c
/******************************************************************************
* Copyright (C) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_controltransfers.c
* @addtogroup usbpsu_v1_7
* @{
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 sg 06/06/16 First release
* 1.3 vak 04/03/17 Added CCI support for USB
* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code
* for all USB IPs.
* 1.4 vak 30/05/18 Removed xusb_wrapper files
* 1.6 pm 28/08/19 Removed 80-character warnings
* 1.7 pm 23/03/20 Restructured the code for more readability and modularity
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files *********************************/
#include "xusbpsu_endpoint.h"
#include "sleep.h"
#include "xusbpsu_local.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
* @brief
* Stalls Control Endpoint and restarts to receive Setup packet.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return None
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr)
{
struct XUsbPsu_Ep *Ept;
Xil_AssertVoid(InstancePtr != NULL);
/* reinitialize physical ep1 */
Ept = &InstancePtr->eps[1U];
Ept->EpStatus = XUSBPSU_EP_ENABLED;
/* stall is always issued on EP0 */
XUsbPsu_EpSetStall(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT);
Ept = &InstancePtr->eps[0U];
Ept->EpStatus = XUSBPSU_EP_ENABLED;
InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
(void)XUsbPsu_RecvSetup(InstancePtr);
}
/****************************************************************************/
/**
* Checks the Data Phase and calls user Endpoint handler.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is a pointer to the Endpoint event occurred in core.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event)
{
struct XUsbPsu_Ep *Ept;
struct XUsbPsu_Trb *TrbPtr;
u32 Status;
u32 Length;
u32 Epnum;
u8 Dir;
Epnum = Event->Epnumber;
Dir = (u8)(!!Epnum);
Ept = &InstancePtr->eps[Epnum];
TrbPtr = &InstancePtr->Ep0_Trb;
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheInvalidateRange((INTPTR)TrbPtr,
sizeof(struct XUsbPsu_Trb));
}
Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size);
if (Status == XUSBPSU_TRBSTS_SETUP_PENDING) {
return;
}
Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
if (Length == 0U) {
Ept->BytesTxed = Ept->RequestedBytes;
} else {
if (Dir == XUSBPSU_EP_DIR_IN) {
Ept->BytesTxed = Ept->RequestedBytes - Length;
} else {
if ((Dir == XUSBPSU_EP_DIR_OUT) &&
(Ept->UnalignedTx == 1U)) {
Ept->BytesTxed = Ept->RequestedBytes;
Ept->UnalignedTx = 0U;
}
}
}
if (Dir == XUSBPSU_EP_DIR_OUT) {
/* Invalidate Cache */
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr,
Ept->BytesTxed);
}
}
if (Ept->Handler) {
Ept->Handler(InstancePtr->AppData, Ept->RequestedBytes,
Ept->BytesTxed);
}
}
/****************************************************************************/
/**
* Checks the Status Phase and starts next Control transfer.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr)
{
struct XUsbPsu_Trb *TrbPtr;
TrbPtr = &InstancePtr->Ep0_Trb;
if (InstancePtr->IsInTestMode != 0U) {
s32 Ret;
Ret = XUsbPsu_SetTestMode(InstancePtr,
InstancePtr->TestMode);
if (Ret < 0) {
XUsbPsu_Ep0StallRestart(InstancePtr);
return;
}
}
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheInvalidateRange((INTPTR)TrbPtr,
sizeof(struct XUsbPsu_Trb));
}
(void)XUsbPsu_RecvSetup(InstancePtr);
}
/****************************************************************************/
/**
* Starts Status Phase of Control Transfer
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is a pointer to the Endpoint event occurred in core.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event)
{
struct XUsbPsu_Ep *Ept;
struct XUsbPsu_EpParams *Params;
struct XUsbPsu_Trb *TrbPtr;
u32 Type;
s32 Ret;
u8 Dir;
Ept = &InstancePtr->eps[Event->Epnumber];
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertNonvoid(Params != NULL);
if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
return (s32)XST_FAILURE;
}
Type = (InstancePtr->IsThreeStage != 0U) ?
XUSBPSU_TRBCTL_CONTROL_STATUS3
: XUSBPSU_TRBCTL_CONTROL_STATUS2;
TrbPtr = &InstancePtr->Ep0_Trb;
/* we use same TrbPtr for setup packet */
TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16U)
>> 16U;
TrbPtr->Size = 0U;
TrbPtr->Ctrl = Type;
TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
| XUSBPSU_TRB_CTRL_LST
| XUSBPSU_TRB_CTRL_IOC
| XUSBPSU_TRB_CTRL_ISP_IMI);
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)TrbPtr,
sizeof(struct XUsbPsu_Trb));
}
Params->Param0 = 0U;
Params->Param1 = (UINTPTR)TrbPtr;
InstancePtr->Ep0State = XUSBPSU_EP0_STATUS_PHASE;
/*
* Control OUT transfer - Status stage happens on EP0 IN - EP1
* Control IN transfer - Status stage happens on EP0 OUT - EP0
*/
Dir = !InstancePtr->ControlDir;
Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, Dir,
XUSBPSU_DEPCMD_STARTTRANSFER,
Params);
if (Ret != XST_SUCCESS) {
return (s32)XST_FAILURE;
}
Ept->EpStatus |= XUSBPSU_EP_BUSY;
Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
Ept->UsbEpNum,
Ept->Direction);
return XST_SUCCESS;
}
/****************************************************************************/
/**
* Ends Data Phase - used in case of error.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Ept is a pointer to the Endpoint structure.
*
* @return None
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
struct XUsbPsu_Ep *Ept)
{
struct XUsbPsu_EpParams *Params;
u32 Cmd;
if (Ept->ResourceIndex == 0U) {
return;
}
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertVoid(Params != NULL);
Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
Cmd, Params);
Ept->ResourceIndex = 0U;
XUsbPsu_Sleep(200U);
}
/****************************************************************************/
/**
* Enables USB Control Endpoint i.e., EP0OUT and EP0IN of Core.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Size is control endpoint size.
*
* @return XST_SUCCESS else XST_FAILURE.
*
* @note None.
*
****************************************************************************/
s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size)
{
s32 RetVal;
Xil_AssertNonvoid((Size >= 64U) && (Size <= 512U));
RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, Size,
XUSBPSU_ENDPOINT_XFER_CONTROL, FALSE);
if (RetVal == XST_FAILURE) {
return (s32)XST_FAILURE;
}
RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, Size,
XUSBPSU_ENDPOINT_XFER_CONTROL, FALSE);
if (RetVal == XST_FAILURE) {
return (s32)XST_FAILURE;
}
return (s32)XST_SUCCESS;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/zynqmp/client/rpu/pm_client.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*
* CONTENT
* Each PU client in the system have such file with definitions of
* masters in the subsystem and functions for getting information
* about the master.
*/
#include "pm_client.h"
#include "xparameters.h"
#include "xil_cache.h"
#include <xreg_cortexr5.h>
#include <xpseudo_asm.h>
#include "xreg_cortexr5.h"
#define PM_CLIENT_RPU_ERR_INJ 0xFF9A0020U
#define PM_CLIENT_RPU_FAULT_LOG_EN_MASK 0x00000101U
/* Mask to get affinity level 0 */
#define PM_CLIENT_AFL0_MASK 0xFFU
static struct XPm_Master pm_rpu_0_master = {
.node_id = NODE_RPU_0,
.pwrctl = RPU_RPU_0_PWRDWN,
.pwrdn_mask = RPU_RPU_0_PWRDWN_EN_MASK,
.ipi = NULL,
};
static struct XPm_Master pm_rpu_1_master = {
.node_id = NODE_RPU_1,
.pwrctl = RPU_RPU_1_PWRDWN,
.pwrdn_mask = RPU_RPU_1_PWRDWN_EN_MASK,
.ipi = NULL,
};
/* Order in pm_master_all array must match cpu ids */
static struct XPm_Master *const pm_masters_all[] = {
&pm_rpu_0_master,
&pm_rpu_1_master,
};
/**
* pm_get_master() - returns pointer to the master structure
* @cpuid: id of the cpu whose master struct pointer should be returned
*
* Return: pointer to a master structure if master is found, otherwise NULL
*/
struct XPm_Master *pm_get_master(const u32 cpuid)
{
struct XPm_Master *master = NULL;
if (PM_ARRAY_SIZE(pm_masters_all) != 0U) {
master = pm_masters_all[cpuid];
goto done;
}
done:
return master;
}
/**
* pm_get_master_by_node() - returns pointer to the master structure
* @nid: ndoe id of the cpu master
*
* Return: pointer to a master structure if master is found, otherwise NULL
*/
struct XPm_Master *pm_get_master_by_node(const enum XPmNodeId nid)
{
u8 i;
struct XPm_Master *master = NULL;
for (i = 0U; i < PM_ARRAY_SIZE(pm_masters_all); i++) {
if (nid == pm_masters_all[i]->node_id) {
master = pm_masters_all[i];
goto done;
}
}
done:
return master;
}
static u32 pm_get_cpuid(const enum XPmNodeId node)
{
u32 i;
u32 ret;
for (i = 0U; i < PM_ARRAY_SIZE(pm_masters_all); i++) {
if (pm_masters_all[i]->node_id == node) {
ret = i;
goto done;
}
}
ret = UNDEFINED_CPUID;
done:
return ret;
}
const enum XPmNodeId subsystem_node = NODE_RPU;
/* By default, lock-step mode is assumed */
struct XPm_Master *primary_master = &pm_rpu_0_master;
void XPm_ClientSuspend(const struct XPm_Master *const master)
{
u32 pwrdn_req;
/* Disable interrupts at processor level */
pm_disable_int();
/* Set powerdown request */
if (NULL != master) {
pwrdn_req = pm_read(master->pwrctl);
pwrdn_req |= master->pwrdn_mask;
pm_write(master->pwrctl, pwrdn_req);
}
}
void XPm_ClientAbortSuspend(void)
{
u32 pwrdn_req;
if (NULL != primary_master) {
pwrdn_req = pm_read(primary_master->pwrctl);
/* Clear powerdown request */
pwrdn_req &= ~primary_master->pwrdn_mask;
pm_write(primary_master->pwrctl, pwrdn_req);
/* Enable interrupts at processor level */
pm_enable_int();
}
}
void XPm_ClientWakeup(const struct XPm_Master *const master)
{
u32 cpuid = pm_get_cpuid(master->node_id);
if (UNDEFINED_CPUID != cpuid) {
u32 val = pm_read(master->pwrctl);
val &= ~(master->pwrdn_mask);
pm_write(master->pwrctl, val);
}
}
/**
* XPm_ClientSuspendFinalize() - Finalize suspend procedure by executing
* wfi instruction
*/
void XPm_ClientSuspendFinalize(void)
{
u32 ctrlReg;
/*
* Unconditionally disable fault log.
* BSP enables it once the processor resumes.
*/
pm_dbg("%s: Disabling RPU Lock-Step Fault Log...\n", __func__);
pm_write(PM_CLIENT_RPU_ERR_INJ,
pm_read(PM_CLIENT_RPU_ERR_INJ) & ~PM_CLIENT_RPU_FAULT_LOG_EN_MASK);
#if defined (__GNUC__)
/* Flush data cache if the cache is enabled */
ctrlReg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL, ctrlReg);
#endif
if ((XREG_CP15_CONTROL_C_BIT & ctrlReg) != 0U) {
Xil_DCacheFlush();
}
pm_dbg("%s: Going to WFI...\n", __func__);
#if defined (__GNUC__)
__asm__("wfi");
#elif defined (__ICCARM__)
__asm("wfi");
#endif
pm_dbg("%s: WFI exit...\n", __func__);
}
/**
* XPm_GetMasterName() - Get name of the master
*
* This function determines name of the master based on current configuration.
*
* @return Name of the master
*/
const char* XPm_GetMasterName(void)
{
static const char* retptr;
bool lockstep = !(pm_read(RPU_RPU_GLBL_CNTL) &
(u32)RPU_RPU_GLBL_CNTL_SLSPLIT_MASK);
if (lockstep != 0U) {
retptr = "RPU";
}
else {
switch (primary_master->node_id) {
case NODE_RPU_0:
retptr = "RPU0";
break;
case NODE_RPU_1:
retptr = "RPU1";
break;
default:
retptr = "ERROR";
break;
};
}
return retptr;
}
/**
* XPm_ClientSetPrimaryMaster() -Set primary master
*
* This function determines the RPU configuration (split or lock-step mode)
* and sets the primary master accordingly.
*
* If this function is not called, the default configuration is assumed
* (i.e. lock-step)
*/
void XPm_ClientSetPrimaryMaster(void)
{
u32 master_id;
bool lockstep;
#if defined (__GNUC__)
master_id = mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & PM_CLIENT_AFL0_MASK;
#elif defined (__ICCARM__)
mfcp(XREG_CP15_MULTI_PROC_AFFINITY, master_id);
master_id &= PM_CLIENT_AFL0_MASK;
#endif
lockstep = !(pm_read(RPU_RPU_GLBL_CNTL) &
(u32)RPU_RPU_GLBL_CNTL_SLSPLIT_MASK);
if (lockstep) {
primary_master = &pm_rpu_0_master;
} else {
primary_master = pm_masters_all[master_id];
}
pm_print("Running in %s mode\n", lockstep ? "Lock-Step" : "Split");
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_scheduler.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_scheduler.h"
/**
* PMU PIT Clock Frequency and Tick Calculation
*/
#define PMU_PIT_CLK_FREQ XPFW_CFG_PMU_CLK_FREQ
#define TICK_MILLISECONDS 10U
#define COUNT_PER_TICK ((PMU_PIT_CLK_FREQ / 1000U)* TICK_MILLISECONDS )
/**
* Microblaze IOModule PIT Register Offsets
* Used internally in this file
*/
#define PIT_PRELOAD_OFFSET 0U
#define PIT_COUNTER_OFFSET 4U
#define PIT_CONTROL_OFFSET 8U
static u32 is_task_active(XPfw_Scheduler_t *SchedPtr, u32 TaskListIndex)
{
u32 ReturnVal;
/* Periodic */
if ((0U != SchedPtr->TaskList[TaskListIndex].Interval)
&& (NULL != SchedPtr->TaskList[TaskListIndex].Callback)
&& (0U == (SchedPtr->Tick
% SchedPtr->TaskList[TaskListIndex].Interval))) {
ReturnVal = TRUE;
} else if ((0U == SchedPtr->TaskList[TaskListIndex].Interval)
&& (NULL != SchedPtr->TaskList[TaskListIndex].Callback)) {
/* Non-Periodic */
ReturnVal = TRUE;
} else {
ReturnVal = FALSE;
}
return ReturnVal;
}
static u32 is_task_non_periodic(XPfw_Scheduler_t *SchedPtr, u32 TaskListIndex)
{
u32 ReturnVal;
if ((0U == SchedPtr->TaskList[TaskListIndex].Interval)
&& (NULL != SchedPtr->TaskList[TaskListIndex].Callback)) {
ReturnVal = TRUE;
} else {
ReturnVal = FALSE;
}
return ReturnVal;
}
XStatus XPfw_SchedulerInit(XPfw_Scheduler_t *SchedPtr, u32 PitBaseAddr)
{
u32 Idx;
XStatus Status;
if (SchedPtr == NULL) {
Status = XST_FAILURE;
goto done;
}
/* Disable all the tasks */
for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) {
SchedPtr->TaskList[Idx].Interval = 0U;
SchedPtr->TaskList[Idx].Callback = NULL;
SchedPtr->TaskList[Idx].Status = XPFW_TASK_STATUS_DISABLED;
}
SchedPtr->Enabled = FALSE;
SchedPtr->PitBaseAddr = PitBaseAddr;
SchedPtr->Tick = 0U;
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_CONTROL_OFFSET, 0U);
/* Successfully completed init */
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPfw_SchedulerStart(XPfw_Scheduler_t *SchedPtr)
{
XStatus Status;
if (SchedPtr == NULL) {
Status = XST_FAILURE;
goto done;
}
SchedPtr->Enabled = TRUE;
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_PRELOAD_OFFSET,
COUNT_PER_TICK);
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_CONTROL_OFFSET, 3U);
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPfw_SchedulerStop(XPfw_Scheduler_t *SchedPtr)
{
SchedPtr->Enabled =FALSE;
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_PRELOAD_OFFSET, 0U );
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_CONTROL_OFFSET, 0U );
return XST_SUCCESS;
}
void XPfw_SchedulerTickHandler(XPfw_Scheduler_t *SchedPtr)
{
u32 Idx;
SchedPtr->Tick++;
for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) {
/* Check if it this task can be triggered */
if (TRUE == is_task_active(SchedPtr, Idx)) {
/* Mark the Task as TRIGGERED */
SchedPtr->TaskList[Idx].Status = XPFW_TASK_STATUS_TRIGGERED;
}
}
}
void XPfw_SchedulerProcess(XPfw_Scheduler_t *SchedPtr)
{
u32 Idx;
u32 CallCount = 0U;
for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) {
/* Check if the task is triggered and has a valid Callback */
if ((XPFW_TASK_STATUS_TRIGGERED == SchedPtr->TaskList[Idx].Status) &&
(NULL != SchedPtr->TaskList[Idx].Callback)) {
/* Execute the Task */
SchedPtr->TaskList[Idx].Callback();
/* Disable the executed Task */
SchedPtr->TaskList[Idx].Status = XPFW_TASK_STATUS_DISABLED;
CallCount++;
/* Remove the Non-Periodic Task */
if (TRUE == is_task_non_periodic(SchedPtr, Idx)) {
SchedPtr->TaskList[Idx].Callback = NULL;
}
}
}
}
XStatus XPfw_SchedulerAddTask(XPfw_Scheduler_t *SchedPtr, u32 OwnerId,u32 MilliSeconds, XPfw_Callback_t CallbackFn)
{
u32 Idx;
XStatus Status;
/* Get the Next Free Task Index */
for (Idx=0U;Idx < XPFW_SCHED_MAX_TASK;Idx++) {
if (NULL == SchedPtr->TaskList[Idx].Callback){
break;
}
}
/* Check if we have reached Max Task limit */
if (XPFW_SCHED_MAX_TASK == Idx) {
Status = XST_FAILURE;
goto done;
}
/* Add Interval as a factor of TICK_MILLISECONDS */
SchedPtr->TaskList[Idx].Interval = MilliSeconds/TICK_MILLISECONDS;
SchedPtr->TaskList[Idx].OwnerId = OwnerId;
SchedPtr->TaskList[Idx].Callback = CallbackFn;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPfw_SchedulerRemoveTask(XPfw_Scheduler_t *SchedPtr, u32 OwnerId, u32 MilliSeconds, XPfw_Callback_t CallbackFn)
{
u32 Idx;
u32 TaskCount = 0U;
/*Find the Task Index */
for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) {
if ((CallbackFn == SchedPtr->TaskList[Idx].Callback) &&
(SchedPtr->TaskList[Idx].OwnerId == OwnerId) &&
((SchedPtr->TaskList[Idx].Interval == (MilliSeconds/TICK_MILLISECONDS)) ||
(0U == MilliSeconds))) {
SchedPtr->TaskList[Idx].Interval = 0U;
SchedPtr->TaskList[Idx].OwnerId = 0U;
SchedPtr->TaskList[Idx].Callback = NULL;
TaskCount++;
}
}
XPfw_Printf(DEBUG_DETAILED,"%s: Removed %lu tasks\r\n",
__func__, TaskCount);
return ((TaskCount > 0U) ? XST_SUCCESS : XST_FAILURE);
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_aie.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_AIE_H_
#define XPM_AIE_H_
#include "xpm_powerdomain.h"
#include "xpm_defs.h"
#include "xpm_psm_api.h"
#include "xpm_ipi.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* AI Engine domain node class.
*/
typedef struct XPm_AieDomain {
XPm_PowerDomain Domain; /**< Power domain node base class */
} XPm_AieDomain;
/************************** Function Prototypes ******************************/
void XPmAieDomain_UnlockPcsr(u32 BaseAddress);
void XPmAieDomain_LockPcsr(u32 BaseAddress);
XStatus XPmAieDomain_Init(XPm_AieDomain *AieDomain, u32 Id, u32 BaseAddress,
XPm_Power *Parent);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_AIE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_psfpdomain.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_common.h"
#include "xpm_psfpdomain.h"
#include "xpm_bisr.h"
#include "xpm_board.h"
#include "xpm_regs.h"
#include "xpm_psm.h"
#include "xpm_device.h"
static XStatus FpdInitStart(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT] = {0};
(void)Args;
(void)NumOfArgs;
/* Check vccint_fpd first to make sure power is on */
if (XST_SUCCESS != XPmPower_CheckPower(PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_FPD_MASK)) {
Status = XPmBoard_ControlRail(RAIL_POWER_UP, POWER_RAIL_FPD);
if (XST_SUCCESS != Status) {
PmErr("Control power rail for FPD failure during power up\r\n");
goto done;
}
}
if (1U != XPmPsm_FwIsPresent()) {
Status = XST_NOT_ENABLED;
goto done;
}
Payload[0] = PSM_API_FPD_HOUSECLEAN;
Payload[1] = (u32)FUNC_INIT_START;
Status = XPm_IpiSend(PSM_IPI_INT_MASK, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_IpiReadStatus(PSM_IPI_INT_MASK);
if (XST_SUCCESS != Status) {
goto done;
}
/* Release POR for PS-FPD */
Status = XPmReset_AssertbyId(PM_RST_FPD_POR, (u32)PM_RESET_ACTION_RELEASE);
done:
return Status;
}
static XStatus FpdInitFinish(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
(void)Args;
(void)NumOfArgs;
Status = XST_SUCCESS;
return Status;
}
static XStatus FpdHcComplete(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT] = {0};
(void)Args;
(void)NumOfArgs;
/* Release SRST for PS-FPD - in case Bisr and Mbist are skipped */
Status = XPmReset_AssertbyId(PM_RST_FPD, (u32)PM_RESET_ACTION_RELEASE);
Payload[0] = PSM_API_FPD_HOUSECLEAN;
Payload[1] = (u32)FUNC_INIT_FINISH;
Status = XPm_IpiSend(PSM_IPI_INT_MASK, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_IpiReadStatus(PSM_IPI_INT_MASK);
if (XST_SUCCESS != Status) {
goto done;
}
/* Remove FPD SOC domains isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_FPD_SOC, FALSE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Copy sysmon data */
Status = XPmPowerDomain_ApplyAmsTrim(SysmonAddresses[XPM_NODEIDX_MONITOR_SYSMON_PS_FPD], PM_POWER_FPD, 0);
done:
return Status;
}
static XStatus FpdScanClear(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
XPm_Psm *Psm;
(void)Args;
(void)NumOfArgs;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
Psm = (XPm_Psm *)XPmDevice_GetById(PM_DEV_PSM_PROC);;
if (NULL == Psm) {
Status = XST_FAILURE;
goto done;
}
/* Trigger scan clear */
PmRmw32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_SCAN_CLEAR_FPD_OFFSET,
PSM_GLOBAL_SCAN_CLEAR_TRIGGER, PSM_GLOBAL_SCAN_CLEAR_TRIGGER);
Status = XPm_PollForMask(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_SCAN_CLEAR_FPD_OFFSET,
PSM_GLOBAL_SCAN_CLEAR_DONE_STATUS, 0x10000U);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_PollForMask(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_SCAN_CLEAR_FPD_OFFSET,
PSM_GLOBAL_SCAN_CLEAR_PASS_STATUS, 0x10000U);
if (XST_SUCCESS != Status) {
goto done;
}
/* Unwrite trigger bits */
PmRmw32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_SCAN_CLEAR_FPD_OFFSET,
PSM_GLOBAL_SCAN_CLEAR_TRIGGER, 0);
done:
return Status;
}
static XStatus FpdBisr(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT] = {0};
(void)Args;
(void)NumOfArgs;
/* Release SRST for PS-FPD */
Status = XPmReset_AssertbyId(PM_RST_FPD, (u32)PM_RESET_ACTION_RELEASE);
/* Call PSM to execute pre bisr requirements */
Payload[0] = PSM_API_FPD_HOUSECLEAN;
Payload[1] = (u32)FUNC_BISR;
Status = XPm_IpiSend(PSM_IPI_INT_MASK, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_IpiReadStatus(PSM_IPI_INT_MASK);
if (XST_SUCCESS != Status) {
goto done;
}
/* Trigger Bisr repair */
Status = XPmBisr_Repair(FPD_TAG_ID);
done:
return Status;
}
static XStatus FpdMbistClear(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT] = {0};
XPm_Psm *Psm;
(void)Args;
(void)NumOfArgs;
Psm = (XPm_Psm *)XPmDevice_GetById(PM_DEV_PSM_PROC);;
if (NULL == Psm) {
Status = XST_FAILURE;
goto done;
}
/* Release SRST for PS-FPD */
Status = XPmReset_AssertbyId(PM_RST_FPD, (u32)PM_RESET_ACTION_RELEASE);
Payload[0] = PSM_API_FPD_HOUSECLEAN;
Payload[1] = (u32)FUNC_MBIST_CLEAR;
Status = XPm_IpiSend(PSM_IPI_INT_MASK, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_IpiReadStatus(PSM_IPI_INT_MASK);
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
PmRmw32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_MBIST_RST_OFFSET,
PSM_GLOBAL_MBIST_RST_FPD_MASK, PSM_GLOBAL_MBIST_RST_FPD_MASK);
PmRmw32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_MBIST_SETUP_OFFSET,
PSM_GLOBAL_MBIST_SETUP_FPD_MASK, PSM_GLOBAL_MBIST_SETUP_FPD_MASK);
PmRmw32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_MBIST_PG_EN_OFFSET,
PSM_GLOBAL_MBIST_PG_EN_FPD_MASK, PSM_GLOBAL_MBIST_PG_EN_FPD_MASK);
Status = XPm_PollForMask(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_MBIST_DONE_OFFSET,
PSM_GLOBAL_MBIST_DONE_FPD_MASK, 0x10000U);
if (XST_SUCCESS != Status) {
goto done;
}
if (PSM_GLOBAL_MBIST_GO_FPD_MASK !=
(XPm_In32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_MBIST_GO_OFFSET) &
PSM_GLOBAL_MBIST_GO_FPD_MASK)) {
Status = XST_FAILURE;
}
/* Unwrite trigger bits */
PmRmw32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_MBIST_RST_OFFSET,
PSM_GLOBAL_MBIST_RST_FPD_MASK, 0);
PmRmw32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_MBIST_SETUP_OFFSET,
PSM_GLOBAL_MBIST_SETUP_FPD_MASK, 0);
PmRmw32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_MBIST_PG_EN_OFFSET,
PSM_GLOBAL_MBIST_PG_EN_FPD_MASK, 0);
if (XST_SUCCESS != Status) {
goto done;
}
/* EDT-997247: Mem clear introduces apu gic ecc error,
so pulse gic reset as a work around to fix it */
Status = XPmReset_AssertbyId(PM_RST_ACPU_GIC, (u32)PM_RESET_ACTION_ASSERT);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmReset_AssertbyId(PM_RST_ACPU_GIC, (u32)PM_RESET_ACTION_RELEASE);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
static struct XPm_PowerDomainOps FpdOps = {
.InitStart = FpdInitStart,
.InitFinish = FpdInitFinish,
.ScanClear = FpdScanClear,
.Bisr = FpdBisr,
.Mbist = FpdMbistClear,
.HcComplete = FpdHcComplete,
};
XStatus XPmPsFpDomain_Init(XPm_PsFpDomain *PsFpd, u32 Id, u32 BaseAddress,
XPm_Power *Parent, u32 *OtherBaseAddresses,
u32 OtherBaseAddressCnt)
{
XStatus Status = XST_FAILURE;
Status = XPmPowerDomain_Init(&PsFpd->Domain, Id, BaseAddress, Parent, &FpdOps);
if (XST_SUCCESS != Status) {
goto done;
}
/* Make sure enough base addresses are being passed */
if (1U <= OtherBaseAddressCnt) {
PsFpd->FpdSlcrBaseAddr = OtherBaseAddresses[0];
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pmc.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_pmc.h"
XStatus XPmPmc_Init(XPm_Pmc *Pmc, u32 DevcieId, u32 Ipi, u32 *BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock,
XPm_ResetNode *Reset)
{
XStatus Status = XST_FAILURE;
Status = XPmCore_Init(&Pmc->Core, DevcieId, Power, Clock, Reset, (u8)Ipi,
NULL);
if (XST_SUCCESS != Status) {
goto done;
}
Pmc->PmcIouSlcrBaseAddr = BaseAddress[0];
Pmc->PmcGlobalBaseAddr = BaseAddress[1];
Pmc->PmcAnalogBaseAddr = BaseAddress[2];
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/client/pm_client.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef PM_CLIENT_H_
#define PM_CLIENT_H_
#include <xil_types.h>
#include <xstatus.h>
#include <xil_exception.h>
#include <xil_io.h>
#include <xipipsu.h>
#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DEBUG_MODE
#define PAYLOAD_ARG_CNT (6U) /* 1 for API ID + 5 for API arguments */
#define RESPONSE_ARG_CNT (4U) /* 1 for status + 3 for values */
#define PM_IPI_TIMEOUT (~0U)
#define TARGET_IPI_INT_MASK XPAR_XIPIPS_TARGET_PSV_PMC_0_CH0_MASK
/**
* XPm_Proc - Processor structure
*/
struct XPm_Proc {
const u32 DevId; /**< Device ID */
const u32 PwrCtrl; /**< Power Control Register Address */
const u32 PwrDwnMask; /**< Power Down Mask */
XIpiPsu *Ipi; /**< IPI Instance */
};
extern struct XPm_Proc *PrimaryProc;
#define XPm_Read(addr) Xil_In32(addr)
#define XPm_Write(addr, value) Xil_Out32(addr, value)
#define XpmEnableInterrupts() Xil_ExceptionEnable()
#define XpmDisableInterrupts() Xil_ExceptionDisable()
#if defined (__aarch64__)
#define XPm_Print(MSG, ...) xil_printf("APU: "MSG, ##__VA_ARGS__)
#elif defined (__arm__)
extern char ProcName[5];
#define XPm_Print(MSG, ...) xil_printf("%s: "MSG, ProcName, ##__VA_ARGS__)
#endif
/* Conditional debugging prints */
#ifdef DEBUG_MODE
#define XPm_Dbg(MSG, ...) XPm_Print(MSG, ##__VA_ARGS__);
#else
#define XPm_Dbg(MSG, ...) {}
#endif
#define pm_print XPm_Dbg
#define pm_dbg XPm_Dbg
#define pm_read XPm_Read
#define pm_write XPm_Write
void XPm_SetPrimaryProc(void);
struct XPm_Proc *XPm_GetProcByDeviceId(u32 DeviceId);
void XPm_ClientSuspend(const struct XPm_Proc *const Proc);
void XPm_ClientWakeUp(const struct XPm_Proc *const Proc);
void XPm_ClientSuspendFinalize(void);
void XPm_ClientAbortSuspend(void);
#ifdef __cplusplus
}
#endif
#endif /* PM_CLIENT_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_apucore.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_APUCORE_H_
#define XPM_APUCORE_H_
#include "xpm_core.h"
#ifdef __cplusplus
extern "C" {
#endif
#define XPM_ACPU_0_CPUPWRDWNREQ_MASK BIT(0)
#define XPM_ACPU_1_CPUPWRDWNREQ_MASK BIT(1)
#define XPM_ACPU_0_PWR_CTRL_MASK BIT(0)
#define XPM_ACPU_1_PWR_CTRL_MASK BIT(1)
typedef struct XPm_ApuCore XPm_ApuCore;
/**
* The APU core class.
*/
struct XPm_ApuCore {
XPm_Core Core; /**< Processor core devices */
u32 FpdApuBaseAddr; /**< Base address of FPD_APU module */
};
/************************** Function Prototypes ******************************/
XStatus XPmApuCore_Init(XPm_ApuCore *ApuCore,
u32 Id,
u32 Ipi,
u32 *BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock, XPm_ResetNode *Reset);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_APUCORE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pinfunc.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_pinfunc.h"
#define FUNC_QUERY_NAME_LEN (FUNC_NAME_SIZE)
/* TODO: Each function can not be mapped with their corresponding
* device. Keeping those devIdx as 0.
*/
static XPm_PinFunc PmPinFuncs[MAX_FUNCTION] = {
[PIN_FUNC_SPI0] = {
.Id = (u8)PIN_FUNC_SPI0,
.Name = "spi0",
.DevIdx = (u16)XPM_NODEIDX_DEV_SPI_0,
.LmioRegMask = 0x80,
.PmioRegMask = 0x100,
.NumPins = 3,
.NumGroups = 6,
.Groups = ((u16 []) {
PIN_GRP_SPI0_0,
PIN_GRP_SPI0_1,
PIN_GRP_SPI0_2,
PIN_GRP_SPI0_3,
PIN_GRP_SPI0_4,
PIN_GRP_SPI0_5,
}),
},
[PIN_FUNC_SPI0_SS] = {
.Id = (u8)PIN_FUNC_SPI0_SS,
.Name = "spi0_ss",
.DevIdx = (u16)XPM_NODEIDX_DEV_SPI_0,
.LmioRegMask = 0x80,
.PmioRegMask = 0x100,
.NumPins = 1,
.NumGroups = 18,
.Groups = ((u16 []) {
PIN_GRP_SPI0_0_SS0,
PIN_GRP_SPI0_0_SS1,
PIN_GRP_SPI0_0_SS2,
PIN_GRP_SPI0_1_SS0,
PIN_GRP_SPI0_1_SS1,
PIN_GRP_SPI0_1_SS2,
PIN_GRP_SPI0_2_SS0,
PIN_GRP_SPI0_2_SS1,
PIN_GRP_SPI0_2_SS2,
PIN_GRP_SPI0_3_SS0,
PIN_GRP_SPI0_3_SS1,
PIN_GRP_SPI0_3_SS2,
PIN_GRP_SPI0_4_SS0,
PIN_GRP_SPI0_4_SS1,
PIN_GRP_SPI0_4_SS2,
PIN_GRP_SPI0_5_SS0,
PIN_GRP_SPI0_5_SS1,
PIN_GRP_SPI0_5_SS2,
}),
},
[PIN_FUNC_SPI1] = {
.Id = (u8)PIN_FUNC_SPI1,
.Name = "spi1",
.DevIdx = (u16)XPM_NODEIDX_DEV_SPI_1,
.LmioRegMask = 0x80,
.PmioRegMask = 0x100,
.NumPins = 3,
.NumGroups = 6,
.Groups = ((u16 []) {
PIN_GRP_SPI1_0,
PIN_GRP_SPI1_1,
PIN_GRP_SPI1_2,
PIN_GRP_SPI1_3,
PIN_GRP_SPI1_4,
PIN_GRP_SPI1_5,
}),
},
[PIN_FUNC_SPI1_SS] = {
.Id = (u8)PIN_FUNC_SPI1_SS,
.Name = "spi1_ss",
.DevIdx = (u16)XPM_NODEIDX_DEV_SPI_1,
.LmioRegMask = 0x80,
.PmioRegMask = 0x100,
.NumPins = 3,
.NumGroups = 18,
.Groups = ((u16 []) {
PIN_GRP_SPI1_0_SS0,
PIN_GRP_SPI1_0_SS1,
PIN_GRP_SPI1_0_SS2,
PIN_GRP_SPI1_1_SS0,
PIN_GRP_SPI1_1_SS1,
PIN_GRP_SPI1_1_SS2,
PIN_GRP_SPI1_2_SS0,
PIN_GRP_SPI1_2_SS1,
PIN_GRP_SPI1_2_SS2,
PIN_GRP_SPI1_3_SS0,
PIN_GRP_SPI1_3_SS1,
PIN_GRP_SPI1_3_SS2,
PIN_GRP_SPI1_4_SS0,
PIN_GRP_SPI1_4_SS1,
PIN_GRP_SPI1_4_SS2,
PIN_GRP_SPI1_5_SS0,
PIN_GRP_SPI1_5_SS1,
PIN_GRP_SPI1_5_SS2,
}),
},
[PIN_FUNC_CAN0] = {
.Id = (u8)PIN_FUNC_CAN0,
.Name = "can0",
.DevIdx = (u16)XPM_NODEIDX_DEV_CAN_FD_0,
.LmioRegMask = 0x180,
.PmioRegMask = 0x180,
.NumPins = 2,
.NumGroups = 18,
.Groups = ((u16 []) {
PIN_GRP_CAN0_0,
PIN_GRP_CAN0_1,
PIN_GRP_CAN0_2,
PIN_GRP_CAN0_3,
PIN_GRP_CAN0_4,
PIN_GRP_CAN0_5,
PIN_GRP_CAN0_6,
PIN_GRP_CAN0_7,
PIN_GRP_CAN0_8,
PIN_GRP_CAN0_9,
PIN_GRP_CAN0_10,
PIN_GRP_CAN0_11,
PIN_GRP_CAN0_12,
PIN_GRP_CAN0_13,
PIN_GRP_CAN0_14,
PIN_GRP_CAN0_15,
PIN_GRP_CAN0_16,
PIN_GRP_CAN0_17,
}),
},
[PIN_FUNC_CAN1] = {
.Id = (u8)PIN_FUNC_CAN1,
.Name = "can1",
.DevIdx = (u16)XPM_NODEIDX_DEV_CAN_FD_1,
.LmioRegMask = 0x180,
.PmioRegMask = 0x180,
.NumPins = 2,
.NumGroups = 19,
.Groups = ((u16 []) {
PIN_GRP_CAN1_0,
PIN_GRP_CAN1_1,
PIN_GRP_CAN1_2,
PIN_GRP_CAN1_3,
PIN_GRP_CAN1_4,
PIN_GRP_CAN1_5,
PIN_GRP_CAN1_6,
PIN_GRP_CAN1_7,
PIN_GRP_CAN1_8,
PIN_GRP_CAN1_9,
PIN_GRP_CAN1_10,
PIN_GRP_CAN1_11,
PIN_GRP_CAN1_12,
PIN_GRP_CAN1_13,
PIN_GRP_CAN1_14,
PIN_GRP_CAN1_15,
PIN_GRP_CAN1_16,
PIN_GRP_CAN1_17,
PIN_GRP_CAN1_18,
}),
},
[PIN_FUNC_I2C0] = {
.Id = (u8)PIN_FUNC_I2C0,
.Name = "i2c0",
.DevIdx = (u16)XPM_NODEIDX_DEV_I2C_0,
.LmioRegMask = 0x200,
.PmioRegMask = 0x80,
.NumPins = 2,
.NumGroups = 18,
.Groups = ((u16 []) {
PIN_GRP_I2C0_0,
PIN_GRP_I2C0_1,
PIN_GRP_I2C0_2,
PIN_GRP_I2C0_3,
PIN_GRP_I2C0_4,
PIN_GRP_I2C0_5,
PIN_GRP_I2C0_6,
PIN_GRP_I2C0_7,
PIN_GRP_I2C0_8,
PIN_GRP_I2C0_9,
PIN_GRP_I2C0_10,
PIN_GRP_I2C0_11,
PIN_GRP_I2C0_12,
PIN_GRP_I2C0_13,
PIN_GRP_I2C0_14,
PIN_GRP_I2C0_15,
PIN_GRP_I2C0_16,
PIN_GRP_I2C0_17,
}),
},
[PIN_FUNC_I2C1] = {
.Id = (u8)PIN_FUNC_I2C1,
.Name = "i2c1",
.DevIdx = (u16)XPM_NODEIDX_DEV_I2C_1,
.LmioRegMask = 0x200,
.PmioRegMask = 0x80,
.NumPins = 2,
.NumGroups = 19,
.Groups = ((u16 []) {
PIN_GRP_I2C1_0,
PIN_GRP_I2C1_1,
PIN_GRP_I2C1_2,
PIN_GRP_I2C1_3,
PIN_GRP_I2C1_4,
PIN_GRP_I2C1_5,
PIN_GRP_I2C1_6,
PIN_GRP_I2C1_7,
PIN_GRP_I2C1_8,
PIN_GRP_I2C1_9,
PIN_GRP_I2C1_10,
PIN_GRP_I2C1_11,
PIN_GRP_I2C1_12,
PIN_GRP_I2C1_13,
PIN_GRP_I2C1_14,
PIN_GRP_I2C1_15,
PIN_GRP_I2C1_16,
PIN_GRP_I2C1_17,
PIN_GRP_I2C1_18,
}),
},
[PIN_FUNC_I2C_PMC] = {
.Id = (u8)PIN_FUNC_I2C_PMC,
.Name = "i2c_pmc",
.DevIdx = (u16)XPM_NODEIDX_DEV_I2C_PMC,
.LmioRegMask = 0xFFF,
.PmioRegMask = 0x300,
.NumPins = 2,
.NumGroups = 13,
.Groups = ((u16 []) {
PIN_GRP_I2C_PMC_0,
PIN_GRP_I2C_PMC_1,
PIN_GRP_I2C_PMC_2,
PIN_GRP_I2C_PMC_3,
PIN_GRP_I2C_PMC_4,
PIN_GRP_I2C_PMC_5,
PIN_GRP_I2C_PMC_6,
PIN_GRP_I2C_PMC_7,
PIN_GRP_I2C_PMC_8,
PIN_GRP_I2C_PMC_9,
PIN_GRP_I2C_PMC_10,
PIN_GRP_I2C_PMC_11,
PIN_GRP_I2C_PMC_12,
}),
},
[PIN_FUNC_TTC0_CLK] = {
.Id = (u8)PIN_FUNC_TTC0_CLK,
.Name = "tt0_clk",
.DevIdx = (u16)XPM_NODEIDX_DEV_TTC_0,
.LmioRegMask = 0x280,
.PmioRegMask = 0x280,
.NumPins = 1,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_TTC0_0_CLK,
PIN_GRP_TTC0_1_CLK,
PIN_GRP_TTC0_2_CLK,
PIN_GRP_TTC0_3_CLK,
PIN_GRP_TTC0_4_CLK,
PIN_GRP_TTC0_5_CLK,
PIN_GRP_TTC0_6_CLK,
PIN_GRP_TTC0_7_CLK,
PIN_GRP_TTC0_8_CLK,
}),
},
[PIN_FUNC_TTC0_WAV] = {
.Id = (u8)PIN_FUNC_TTC0_WAV,
.Name = "ttc0_wav",
.DevIdx = (u16)XPM_NODEIDX_DEV_TTC_0,
.LmioRegMask = 0x280,
.PmioRegMask = 0x280,
.NumPins = 1,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_TTC0_0_WAV,
PIN_GRP_TTC0_1_WAV,
PIN_GRP_TTC0_2_WAV,
PIN_GRP_TTC0_3_WAV,
PIN_GRP_TTC0_4_WAV,
PIN_GRP_TTC0_5_WAV,
PIN_GRP_TTC0_6_WAV,
PIN_GRP_TTC0_7_WAV,
PIN_GRP_TTC0_8_WAV,
}),
},
[PIN_FUNC_TTC1_CLK] = {
.Id = (u8)PIN_FUNC_TTC1_CLK,
.Name = "ttc1_clk",
.DevIdx = (u16)XPM_NODEIDX_DEV_TTC_1,
.LmioRegMask = 0x280,
.PmioRegMask = 0x280,
.NumPins = 1,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_TTC1_0_CLK,
PIN_GRP_TTC1_1_CLK,
PIN_GRP_TTC1_2_CLK,
PIN_GRP_TTC1_3_CLK,
PIN_GRP_TTC1_4_CLK,
PIN_GRP_TTC1_5_CLK,
PIN_GRP_TTC1_6_CLK,
PIN_GRP_TTC1_7_CLK,
PIN_GRP_TTC1_8_CLK,
}),
},
[PIN_FUNC_TTC1_WAV] = {
.Id = (u8)PIN_FUNC_TTC1_WAV,
.Name = "ttc1_wav",
.DevIdx = (u16)XPM_NODEIDX_DEV_TTC_1,
.LmioRegMask = 0x280,
.PmioRegMask = 0x280,
.NumPins = 1,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_TTC1_0_WAV,
PIN_GRP_TTC1_1_WAV,
PIN_GRP_TTC1_2_WAV,
PIN_GRP_TTC1_3_WAV,
PIN_GRP_TTC1_4_WAV,
PIN_GRP_TTC1_5_WAV,
PIN_GRP_TTC1_6_WAV,
PIN_GRP_TTC1_7_WAV,
PIN_GRP_TTC1_8_WAV,
}),
},
[PIN_FUNC_TTC2_CLK] = {
.Id = (u8)PIN_FUNC_TTC2_CLK,
.Name = "ttc2_wav",
.DevIdx = (u16)XPM_NODEIDX_DEV_TTC_2,
.LmioRegMask = 0x280,
.PmioRegMask = 0x280,
.NumPins = 1,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_TTC2_0_CLK,
PIN_GRP_TTC2_1_CLK,
PIN_GRP_TTC2_2_CLK,
PIN_GRP_TTC2_3_CLK,
PIN_GRP_TTC2_4_CLK,
PIN_GRP_TTC2_5_CLK,
PIN_GRP_TTC2_6_CLK,
PIN_GRP_TTC2_7_CLK,
PIN_GRP_TTC2_8_CLK,
}),
},
[PIN_FUNC_TTC2_WAV] = {
.Id = (u8)PIN_FUNC_TTC2_WAV,
.Name = "ttc2_wav",
.DevIdx = (u16)XPM_NODEIDX_DEV_TTC_2,
.LmioRegMask = 0x280,
.PmioRegMask = 0x280,
.NumPins = 1,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_TTC2_0_WAV,
PIN_GRP_TTC2_1_WAV,
PIN_GRP_TTC2_2_WAV,
PIN_GRP_TTC2_3_WAV,
PIN_GRP_TTC2_4_WAV,
PIN_GRP_TTC2_5_WAV,
PIN_GRP_TTC2_6_WAV,
PIN_GRP_TTC2_7_WAV,
PIN_GRP_TTC2_8_WAV,
}),
},
[PIN_FUNC_TTC3_CLK] = {
.Id = (u8)PIN_FUNC_TTC3_CLK,
.Name = "ttc3_clk",
.DevIdx = (u16)XPM_NODEIDX_DEV_TTC_3,
.LmioRegMask = 0x280,
.PmioRegMask = 0x280,
.NumPins = 1,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_TTC3_0_CLK,
PIN_GRP_TTC3_1_CLK,
PIN_GRP_TTC3_2_CLK,
PIN_GRP_TTC3_3_CLK,
PIN_GRP_TTC3_4_CLK,
PIN_GRP_TTC3_5_CLK,
PIN_GRP_TTC3_6_CLK,
PIN_GRP_TTC3_7_CLK,
PIN_GRP_TTC3_8_CLK,
}),
},
[PIN_FUNC_TTC3_WAV] = {
.Id = (u8)PIN_FUNC_TTC3_WAV,
.Name = "ttc3_wav",
.DevIdx = (u16)XPM_NODEIDX_DEV_TTC_3,
.LmioRegMask = 0x280,
.PmioRegMask = 0x280,
.NumPins = 1,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_TTC3_0_WAV,
PIN_GRP_TTC3_1_WAV,
PIN_GRP_TTC3_2_WAV,
PIN_GRP_TTC3_3_WAV,
PIN_GRP_TTC3_4_WAV,
PIN_GRP_TTC3_5_WAV,
PIN_GRP_TTC3_6_WAV,
PIN_GRP_TTC3_7_WAV,
PIN_GRP_TTC3_8_WAV,
}),
},
[PIN_FUNC_WWDT0] = {
.Id = (u8)PIN_FUNC_WWDT0,
.Name = "wwdt0",
.DevIdx = (u16)XPM_NODEIDX_DEV_SWDT_LPD,
.LmioRegMask = 0x300,
.PmioRegMask = 0x200,
.NumPins = 6,
.NumGroups = 6,
.Groups = ((u16 []) {
PIN_GRP_WWDT0_0,
PIN_GRP_WWDT0_1,
PIN_GRP_WWDT0_2,
PIN_GRP_WWDT0_3,
PIN_GRP_WWDT0_4,
PIN_GRP_WWDT0_5,
}),
},
[PIN_FUNC_WWDT1] = {
.Id = (u8)PIN_FUNC_WWDT1,
.Name = "wwdt1",
.DevIdx = (u16)XPM_NODEIDX_DEV_SWDT_FPD,
.LmioRegMask = 0x300,
.PmioRegMask = 0x200,
.NumPins = 6,
.NumGroups = 6,
.Groups = ((u16 []) {
PIN_GRP_WWDT1_0,
PIN_GRP_WWDT1_1,
PIN_GRP_WWDT1_2,
PIN_GRP_WWDT1_3,
PIN_GRP_WWDT1_4,
PIN_GRP_WWDT1_5,
}),
},
[PIN_FUNC_SYSMON_I2C0] = {
.Id = (u8)PIN_FUNC_SYSMON_I2C0,
.Name = "sysmon_i2c0",
.DevIdx = 0,
.LmioRegMask = 0x380,
.PmioRegMask = 0x00,
.NumPins = 2,
.NumGroups = 18,
.Groups = ((u16 []) {
PIN_GRP_SYSMON_I2C0_0,
PIN_GRP_SYSMON_I2C0_1,
PIN_GRP_SYSMON_I2C0_2,
PIN_GRP_SYSMON_I2C0_3,
PIN_GRP_SYSMON_I2C0_4,
PIN_GRP_SYSMON_I2C0_5,
PIN_GRP_SYSMON_I2C0_6,
PIN_GRP_SYSMON_I2C0_7,
PIN_GRP_SYSMON_I2C0_8,
PIN_GRP_SYSMON_I2C0_9,
PIN_GRP_SYSMON_I2C0_10,
PIN_GRP_SYSMON_I2C0_11,
PIN_GRP_SYSMON_I2C0_12,
PIN_GRP_SYSMON_I2C0_13,
PIN_GRP_SYSMON_I2C0_14,
PIN_GRP_SYSMON_I2C0_15,
PIN_GRP_SYSMON_I2C0_16,
PIN_GRP_SYSMON_I2C0_17,
}),
},
[PIN_FUNC_SYSMON_I2C0_ALERT] = {
.Id = (u8)PIN_FUNC_SYSMON_I2C0_ALERT,
.Name = "sysmon_i2c0_alrt",
.DevIdx = 0,
.LmioRegMask = 0x380,
.PmioRegMask = 0x00,
.NumPins = 1,
.NumGroups = 18,
.Groups = ((u16 []) {
PIN_GRP_SYSMON_I2C0_0_ALERT,
PIN_GRP_SYSMON_I2C0_1_ALERT,
PIN_GRP_SYSMON_I2C0_2_ALERT,
PIN_GRP_SYSMON_I2C0_3_ALERT,
PIN_GRP_SYSMON_I2C0_4_ALERT,
PIN_GRP_SYSMON_I2C0_5_ALERT,
PIN_GRP_SYSMON_I2C0_6_ALERT,
PIN_GRP_SYSMON_I2C0_7_ALERT,
PIN_GRP_SYSMON_I2C0_8_ALERT,
PIN_GRP_SYSMON_I2C0_9_ALERT,
PIN_GRP_SYSMON_I2C0_10_ALERT,
PIN_GRP_SYSMON_I2C0_11_ALERT,
PIN_GRP_SYSMON_I2C0_12_ALERT,
PIN_GRP_SYSMON_I2C0_13_ALERT,
PIN_GRP_SYSMON_I2C0_14_ALERT,
PIN_GRP_SYSMON_I2C0_15_ALERT,
PIN_GRP_SYSMON_I2C0_16_ALERT,
PIN_GRP_SYSMON_I2C0_17_ALERT,
}),
},
[PIN_FUNC_UART0] = {
.Id = (u8)PIN_FUNC_UART0,
.Name = "uart0",
.DevIdx = (u16)XPM_NODEIDX_DEV_UART_0,
.LmioRegMask = 0x20,
.PmioRegMask = 0x40,
.NumPins = 2,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_UART0_0,
PIN_GRP_UART0_1,
PIN_GRP_UART0_2,
PIN_GRP_UART0_3,
PIN_GRP_UART0_4,
PIN_GRP_UART0_5,
PIN_GRP_UART0_6,
PIN_GRP_UART0_7,
PIN_GRP_UART0_8,
}),
},
[PIN_FUNC_UART0_CTRL] = {
.Id = (u8)PIN_FUNC_UART0_CTRL,
.Name = "uart0_ctrl",
.DevIdx = (u16)XPM_NODEIDX_DEV_UART_0,
.LmioRegMask = 0x20,
.PmioRegMask = 0x40,
.NumPins = 2,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_UART0_0_CTRL,
PIN_GRP_UART0_1_CTRL,
PIN_GRP_UART0_2_CTRL,
PIN_GRP_UART0_3_CTRL,
PIN_GRP_UART0_4_CTRL,
PIN_GRP_UART0_5_CTRL,
PIN_GRP_UART0_6_CTRL,
PIN_GRP_UART0_7_CTRL,
PIN_GRP_UART0_8_CTRL,
}),
},
[PIN_FUNC_UART1] = {
.Id = (u8)PIN_FUNC_UART1,
.Name = "uart1",
.DevIdx = (u16)XPM_NODEIDX_DEV_UART_1,
.LmioRegMask = 0x20,
.PmioRegMask = 0x20,
.NumPins = 2,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_UART1_0,
PIN_GRP_UART1_1,
PIN_GRP_UART1_2,
PIN_GRP_UART1_3,
PIN_GRP_UART1_4,
PIN_GRP_UART1_5,
PIN_GRP_UART1_6,
PIN_GRP_UART1_7,
PIN_GRP_UART1_8,
}),
},
[PIN_FUNC_UART1_CTRL] = {
.Id = (u8)PIN_FUNC_UART1_CTRL,
.Name = "uart1_ctrl",
.DevIdx = (u16)XPM_NODEIDX_DEV_UART_1,
.LmioRegMask = 0x20,
.PmioRegMask = 0x40,
.NumPins = 2,
.NumGroups = 9,
.Groups = ((u16 []) {
PIN_GRP_UART1_0_CTRL,
PIN_GRP_UART1_1_CTRL,
PIN_GRP_UART1_2_CTRL,
PIN_GRP_UART1_3_CTRL,
PIN_GRP_UART1_4_CTRL,
PIN_GRP_UART1_5_CTRL,
PIN_GRP_UART1_6_CTRL,
PIN_GRP_UART1_7_CTRL,
PIN_GRP_UART1_8_CTRL,
}),
},
[PIN_FUNC_GPIO0] = {
.Id = (u8)PIN_FUNC_GPIO0,
.Name = "gpio0",
.DevIdx = (u16)XPM_NODEIDX_DEV_GPIO_PMC,
.LmioRegMask = 0xFFF,
.PmioRegMask = 0x60,
.NumPins = 1,
.NumGroups = 26,
.Groups = ((u16 []) {
PIN_GRP_GPIO0_0,
PIN_GRP_GPIO0_1,
PIN_GRP_GPIO0_2,
PIN_GRP_GPIO0_3,
PIN_GRP_GPIO0_4,
PIN_GRP_GPIO0_5,
PIN_GRP_GPIO0_6,
PIN_GRP_GPIO0_7,
PIN_GRP_GPIO0_8,
PIN_GRP_GPIO0_9,
PIN_GRP_GPIO0_10,
PIN_GRP_GPIO0_11,
PIN_GRP_GPIO0_12,
PIN_GRP_GPIO0_13,
PIN_GRP_GPIO0_14,
PIN_GRP_GPIO0_15,
PIN_GRP_GPIO0_16,
PIN_GRP_GPIO0_17,
PIN_GRP_GPIO0_18,
PIN_GRP_GPIO0_19,
PIN_GRP_GPIO0_20,
PIN_GRP_GPIO0_21,
PIN_GRP_GPIO0_22,
PIN_GRP_GPIO0_23,
PIN_GRP_GPIO0_24,
PIN_GRP_GPIO0_25,
}),
},
[PIN_FUNC_GPIO1] = {
.Id = (u8)PIN_FUNC_GPIO1,
.Name = "gpio1",
.DevIdx = (u16)XPM_NODEIDX_DEV_GPIO_PMC,
.LmioRegMask = 0xFFF,
.PmioRegMask = 0x60,
.NumPins = 1,
.NumGroups = 26,
.Groups = ((u16 []) {
PIN_GRP_GPIO1_0,
PIN_GRP_GPIO1_1,
PIN_GRP_GPIO1_2,
PIN_GRP_GPIO1_3,
PIN_GRP_GPIO1_4,
PIN_GRP_GPIO1_5,
PIN_GRP_GPIO1_6,
PIN_GRP_GPIO1_7,
PIN_GRP_GPIO1_8,
PIN_GRP_GPIO1_9,
PIN_GRP_GPIO1_10,
PIN_GRP_GPIO1_11,
PIN_GRP_GPIO1_12,
PIN_GRP_GPIO1_13,
PIN_GRP_GPIO1_14,
PIN_GRP_GPIO1_15,
PIN_GRP_GPIO1_16,
PIN_GRP_GPIO1_17,
PIN_GRP_GPIO1_18,
PIN_GRP_GPIO1_19,
PIN_GRP_GPIO1_20,
PIN_GRP_GPIO1_21,
PIN_GRP_GPIO1_22,
PIN_GRP_GPIO1_23,
PIN_GRP_GPIO1_24,
PIN_GRP_GPIO1_25,
}),
},
[PIN_FUNC_GPIO2] = {
.Id = (u8)PIN_FUNC_GPIO2,
.Name = "gpio2",
.DevIdx = (u16)XPM_NODEIDX_DEV_GPIO,
.LmioRegMask = 0x40,
.PmioRegMask = 0xFFF,
.NumPins = 1,
.NumGroups = 26,
.Groups = ((u16 []) {
PIN_GRP_GPIO2_0,
PIN_GRP_GPIO2_1,
PIN_GRP_GPIO2_2,
PIN_GRP_GPIO2_3,
PIN_GRP_GPIO2_4,
PIN_GRP_GPIO2_5,
PIN_GRP_GPIO2_6,
PIN_GRP_GPIO2_7,
PIN_GRP_GPIO2_8,
PIN_GRP_GPIO2_9,
PIN_GRP_GPIO2_10,
PIN_GRP_GPIO2_11,
PIN_GRP_GPIO2_12,
PIN_GRP_GPIO2_13,
PIN_GRP_GPIO2_14,
PIN_GRP_GPIO2_15,
PIN_GRP_GPIO2_16,
PIN_GRP_GPIO2_17,
PIN_GRP_GPIO2_18,
PIN_GRP_GPIO2_19,
PIN_GRP_GPIO2_20,
PIN_GRP_GPIO2_21,
PIN_GRP_GPIO2_22,
PIN_GRP_GPIO2_23,
PIN_GRP_GPIO2_24,
PIN_GRP_GPIO2_25,
}),
},
[PIN_FUNC_EMIO0] = {
.Id = (u8)PIN_FUNC_EMIO0,
.Name = "emio0",
.DevIdx = 0,
.LmioRegMask = 0x10,
.PmioRegMask = 0x18,
.NumPins = 1,
.NumGroups = 78,
.Groups = ((u16 []) {
PIN_GRP_EMIO0_0,
PIN_GRP_EMIO0_1,
PIN_GRP_EMIO0_2,
PIN_GRP_EMIO0_3,
PIN_GRP_EMIO0_4,
PIN_GRP_EMIO0_5,
PIN_GRP_EMIO0_6,
PIN_GRP_EMIO0_7,
PIN_GRP_EMIO0_8,
PIN_GRP_EMIO0_9,
PIN_GRP_EMIO0_10,
PIN_GRP_EMIO0_11,
PIN_GRP_EMIO0_12,
PIN_GRP_EMIO0_13,
PIN_GRP_EMIO0_14,
PIN_GRP_EMIO0_15,
PIN_GRP_EMIO0_16,
PIN_GRP_EMIO0_17,
PIN_GRP_EMIO0_18,
PIN_GRP_EMIO0_19,
PIN_GRP_EMIO0_20,
PIN_GRP_EMIO0_21,
PIN_GRP_EMIO0_22,
PIN_GRP_EMIO0_23,
PIN_GRP_EMIO0_24,
PIN_GRP_EMIO0_25,
PIN_GRP_EMIO0_26,
PIN_GRP_EMIO0_27,
PIN_GRP_EMIO0_28,
PIN_GRP_EMIO0_29,
PIN_GRP_EMIO0_30,
PIN_GRP_EMIO0_31,
PIN_GRP_EMIO0_32,
PIN_GRP_EMIO0_33,
PIN_GRP_EMIO0_34,
PIN_GRP_EMIO0_35,
PIN_GRP_EMIO0_36,
PIN_GRP_EMIO0_37,
PIN_GRP_EMIO0_38,
PIN_GRP_EMIO0_39,
PIN_GRP_EMIO0_40,
PIN_GRP_EMIO0_41,
PIN_GRP_EMIO0_42,
PIN_GRP_EMIO0_43,
PIN_GRP_EMIO0_44,
PIN_GRP_EMIO0_45,
PIN_GRP_EMIO0_46,
PIN_GRP_EMIO0_47,
PIN_GRP_EMIO0_48,
PIN_GRP_EMIO0_49,
PIN_GRP_EMIO0_50,
PIN_GRP_EMIO0_51,
PIN_GRP_EMIO0_52,
PIN_GRP_EMIO0_53,
PIN_GRP_EMIO0_54,
PIN_GRP_EMIO0_55,
PIN_GRP_EMIO0_56,
PIN_GRP_EMIO0_57,
PIN_GRP_EMIO0_58,
PIN_GRP_EMIO0_59,
PIN_GRP_EMIO0_60,
PIN_GRP_EMIO0_61,
PIN_GRP_EMIO0_62,
PIN_GRP_EMIO0_63,
PIN_GRP_EMIO0_64,
PIN_GRP_EMIO0_65,
PIN_GRP_EMIO0_66,
PIN_GRP_EMIO0_67,
PIN_GRP_EMIO0_68,
PIN_GRP_EMIO0_69,
PIN_GRP_EMIO0_70,
PIN_GRP_EMIO0_71,
PIN_GRP_EMIO0_72,
PIN_GRP_EMIO0_73,
PIN_GRP_EMIO0_74,
PIN_GRP_EMIO0_75,
PIN_GRP_EMIO0_76,
PIN_GRP_EMIO0_77,
}),
},
[PIN_FUNC_GEM0] = {
.Id = (u8)PIN_FUNC_GEM0,
.Name = "gem0",
.DevIdx = (u16)XPM_NODEIDX_DEV_GEM_0,
.LmioRegMask = 0x4,
.PmioRegMask = 0x6,
.NumPins = 12,
.NumGroups = 2,
.Groups = ((u16 []) {
PIN_GRP_GEM0_0,
PIN_GRP_GEM0_1,
}),
},
[PIN_FUNC_GEM1] = {
.Id = (u8)PIN_FUNC_GEM1,
.Name = "gem1",
.DevIdx = (u16)XPM_NODEIDX_DEV_GEM_1,
.LmioRegMask = 0x4,
.PmioRegMask = 0x6,
.NumPins = 12,
.NumGroups = 2,
.Groups = ((u16 []) {
PIN_GRP_GEM1_0,
PIN_GRP_GEM1_1,
}),
},
[PIN_FUNC_TRACE0] = {
.Id = (u8)PIN_FUNC_TRACE0,
.Name = "trace0",
.DevIdx = 0,
.LmioRegMask = 0x8,
.PmioRegMask = 0x10,
.NumPins = 17,
.NumGroups = 3,
.Groups = ((u16 []) {
PIN_GRP_TRACE0_0,
PIN_GRP_TRACE0_1,
PIN_GRP_TRACE0_2,
}),
},
[PIN_FUNC_TRACE0_CLK] = {
.Id = (u8)PIN_FUNC_TRACE0_CLK,
.Name = "trace0_clk",
.DevIdx = 0,
.LmioRegMask = 0x8,
.PmioRegMask = 0x10,
.NumPins = 1,
.NumGroups = 3,
.Groups = ((u16 []) {
PIN_GRP_TRACE0_0_CLK,
PIN_GRP_TRACE0_1_CLK,
PIN_GRP_TRACE0_2_CLK,
}),
},
[PIN_FUNC_MDIO0] = {
.Id = (u8)PIN_FUNC_MDIO0,
.Name = "mdio0",
.DevIdx = 0,
.LmioRegMask = 0x280,
.PmioRegMask = 0x180,
.NumPins = 2,
.NumGroups = 2,
.Groups = ((u16 []) {
PIN_GRP_MDIO0_0,
PIN_GRP_MDIO0_1,
}),
},
[PIN_FUNC_MDIO1] = {
.Id = (u8)PIN_FUNC_MDIO1,
.Name = "mdio1",
.DevIdx = 0,
.LmioRegMask = 0x300,
.PmioRegMask = 0x200,
.NumPins = 2,
.NumGroups = 2,
.Groups = ((u16 []) {
PIN_GRP_MDIO1_0,
PIN_GRP_MDIO1_1,
}),
},
[PIN_FUNC_GEM_TSU0] = {
.Id = (u8)PIN_FUNC_GEM_TSU0,
.Name = "gem_tsu0",
.DevIdx = 0,
.LmioRegMask = 0x4,
.PmioRegMask = 0x6,
.NumPins = 1,
.NumGroups = 4,
.Groups = ((u16 []) {
PIN_GRP_GEM_TSU0_0,
PIN_GRP_GEM_TSU0_1,
PIN_GRP_GEM_TSU0_2,
PIN_GRP_GEM_TSU0_3,
}),
},
[PIN_FUNC_PCIE0] = {
.Id = (u8)PIN_FUNC_PCIE0,
.Name = "pcie0",
.DevIdx = 0,
.LmioRegMask = 0x100,
.PmioRegMask = 0x380,
.NumPins = 2,
.NumGroups = 3,
.Groups = ((u16 []) {
PIN_GRP_PCIE0_0,
PIN_GRP_PCIE0_1,
PIN_GRP_PCIE0_2,
}),
},
[PIN_FUNC_SMAP0] = {
.Id = (u8)PIN_FUNC_SMAP0,
.Name = "smap0",
.DevIdx = 0,
.LmioRegMask = 0xFFF,
.PmioRegMask = 0x4,
.NumPins = 36,
.NumGroups = 1,
.Groups = ((u16 []) {
PIN_GRP_SMAP0_0,
}),
},
[PIN_FUNC_USB0] = {
.Id = (u8)PIN_FUNC_USB0,
.Name = "usb0",
.DevIdx = (u16)XPM_NODEIDX_DEV_USB_0,
.LmioRegMask = 0xFFF,
.PmioRegMask = 0x6,
.NumPins = 13,
.NumGroups = 1,
.Groups = ((u16 []) {
PIN_GRP_USB0_0,
}),
},
[PIN_FUNC_SD0] = {
.Id = (u8)PIN_FUNC_SD0,
.Name = "sd0",
.DevIdx = (u16)XPM_NODEIDX_DEV_SDIO_0,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x2,
.NumPins = 10,
.NumGroups = 22,
.Groups = ((u16 []) {
PIN_GRP_SD0_0,
PIN_GRP_SD0_4BIT_0_0,
PIN_GRP_SD0_4BIT_0_1,
PIN_GRP_SD0_1BIT_0_0,
PIN_GRP_SD0_1BIT_0_1,
PIN_GRP_SD0_1BIT_0_2,
PIN_GRP_SD0_1BIT_0_3,
PIN_GRP_SD0_1BIT_0_4,
PIN_GRP_SD0_1BIT_0_5,
PIN_GRP_SD0_1BIT_0_6,
PIN_GRP_SD0_1BIT_0_7,
PIN_GRP_SD0_1,
PIN_GRP_SD0_4BIT_1_0,
PIN_GRP_SD0_4BIT_1_1,
PIN_GRP_SD0_1BIT_1_0,
PIN_GRP_SD0_1BIT_1_1,
PIN_GRP_SD0_1BIT_1_2,
PIN_GRP_SD0_1BIT_1_3,
PIN_GRP_SD0_1BIT_1_4,
PIN_GRP_SD0_1BIT_1_5,
PIN_GRP_SD0_1BIT_1_6,
PIN_GRP_SD0_1BIT_1_7,
}),
},
[PIN_FUNC_SD0_PC] = {
.Id = (u8)PIN_FUNC_SD0_PC,
.Name = "sd0_pc",
.DevIdx = (u16)XPM_NODEIDX_DEV_SDIO_0,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x2,
.NumPins = 1,
.NumGroups = 2,
.Groups = ((u16 []) {
PIN_GRP_SD0_0_PC,
PIN_GRP_SD0_1_PC,
}),
},
[PIN_FUNC_SD0_CD] = {
.Id = (u8)PIN_FUNC_SD0_CD,
.Name = "sd0_cd",
.DevIdx = (u16)XPM_NODEIDX_DEV_SDIO_0,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x2,
.NumPins = 1,
.NumGroups = 2,
.Groups = ((u16 []) {
PIN_GRP_SD0_0_CD,
PIN_GRP_SD0_1_CD,
}),
},
[PIN_FUNC_SD0_WP] = {
.Id = (u8)PIN_FUNC_SD0_WP,
.Name = "sd0_wp",
.DevIdx = (u16)XPM_NODEIDX_DEV_SDIO_0,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x2,
.NumPins = 1,
.NumGroups = 2,
.Groups = ((u16 []) {
PIN_GRP_SD0_0_WP,
PIN_GRP_SD0_1_WP,
}),
},
[PIN_FUNC_SD1] = {
.Id = (u8)PIN_FUNC_SD1,
.Name = "sd1",
.DevIdx = (u16)XPM_NODEIDX_DEV_SDIO_1,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x2,
.NumPins = 10,
.NumGroups = 22,
.Groups = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_SD1_4BIT_0_0,
PIN_GRP_SD1_4BIT_0_1,
PIN_GRP_SD1_1BIT_0_0,
PIN_GRP_SD1_1BIT_0_1,
PIN_GRP_SD1_1BIT_0_2,
PIN_GRP_SD1_1BIT_0_3,
PIN_GRP_SD1_1BIT_0_4,
PIN_GRP_SD1_1BIT_0_5,
PIN_GRP_SD1_1BIT_0_6,
PIN_GRP_SD1_1BIT_0_7,
PIN_GRP_SD1_1,
PIN_GRP_SD1_4BIT_1_0,
PIN_GRP_SD1_4BIT_1_1,
PIN_GRP_SD1_1BIT_1_0,
PIN_GRP_SD1_1BIT_1_1,
PIN_GRP_SD1_1BIT_1_2,
PIN_GRP_SD1_1BIT_1_3,
PIN_GRP_SD1_1BIT_1_4,
PIN_GRP_SD1_1BIT_1_5,
PIN_GRP_SD1_1BIT_1_6,
PIN_GRP_SD1_1BIT_1_7,
}),
},
[PIN_FUNC_SD1_PC] = {
.Id = (u8)PIN_FUNC_SD1_PC,
.Name = "sd1_pc",
.DevIdx = (u16)XPM_NODEIDX_DEV_SDIO_1,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x2,
.NumPins = 1,
.NumGroups = 2,
.Groups = ((u16 []) {
PIN_GRP_SD1_0_PC,
PIN_GRP_SD1_1_PC,
}),
},
[PIN_FUNC_SD1_CD] = {
.Id = (u8)PIN_FUNC_SD1_CD,
.Name = "sd1_cd",
.DevIdx = (u16)XPM_NODEIDX_DEV_SDIO_1,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x2,
.NumPins = 1,
.NumGroups = 2,
.Groups = ((u16 []) {
PIN_GRP_SD1_0_CD,
PIN_GRP_SD1_1_CD,
}),
},
[PIN_FUNC_SD1_WP] = {
.Id = (u8)PIN_FUNC_SD1_WP,
.Name = "sd1_wp",
.DevIdx = (u16)XPM_NODEIDX_DEV_SDIO_1,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x2,
.NumPins = 1,
.NumGroups = 2,
.Groups = ((u16 []) {
PIN_GRP_SD1_0_WP,
PIN_GRP_SD1_1_WP,
}),
},
[PIN_FUNC_OSPI0] = {
.Id = (u8)PIN_FUNC_OSPI0,
.Name = "ospi0",
.DevIdx = (u16)XPM_NODEIDX_DEV_OSPI,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x4,
.NumPins = 10,
.NumGroups = 1,
.Groups = ((u16 []) {
PIN_GRP_OSPI0_0,
}),
},
[PIN_FUNC_OSPI0_SS] = {
.Id = (u8)PIN_FUNC_OSPI0_SS,
.Name = "ospi0_ss",
.DevIdx = (u16)XPM_NODEIDX_DEV_OSPI,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x4,
.NumPins = 2,
.NumGroups = 1,
.Groups = ((u16 []) {
PIN_GRP_OSPI0_0_SS,
}),
},
[PIN_FUNC_QSPI0] = {
.Id = (u8)PIN_FUNC_QSPI0,
.Name = "qspi0",
.DevIdx = (u16)XPM_NODEIDX_DEV_QSPI,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x6,
.NumPins = 10,
.NumGroups = 1,
.Groups = ((u16 []) {
PIN_GRP_QSPI0_0,
}),
},
[PIN_FUNC_QSPI0_FBCLK] = {
.Id = (u8)PIN_FUNC_QSPI0_FBCLK,
.Name = "qspi0_fbclk",
.DevIdx = (u16)XPM_NODEIDX_DEV_QSPI,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x6,
.NumPins = 1,
.NumGroups = 1,
.Groups = ((u16 []) {
PIN_GRP_QSPI0_0_FBCLK,
}),
},
[PIN_FUNC_QSPI0_SS] = {
.Id = (u8)PIN_FUNC_QSPI0_SS,
.Name = "qspi0_ss",
.DevIdx = (u16)XPM_NODEIDX_DEV_QSPI,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x6,
.NumPins = 2,
.NumGroups = 1,
.Groups = ((u16 []) {
PIN_GRP_QSPI0_0_SS,
}),
},
[PIN_FUNC_TEST_CLK] = {
.Id = (u8)PIN_FUNC_TEST_CLK,
.Name = "test_clk",
.DevIdx = 0,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x8,
.NumPins = 4,
.NumGroups = 1,
.Groups = ((u16 []) {
PIN_GRP_TEST_CLK_0,
}),
},
[PIN_FUNC_TEST_SCAN] = {
.Id = (u8)PIN_FUNC_TEST_SCAN,
.Name = "test_scan",
.DevIdx = 0,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x20,
.NumPins = 38,
.NumGroups = 1,
.Groups = ((u16 []) {
PIN_GRP_TEST_SCAN_0,
}),
},
[PIN_FUNC_TAMPER_TRIGGER] = {
.Id = (u8)PIN_FUNC_TAMPER_TRIGGER,
.Name = "tamper_trigger",
.DevIdx = 0,
.LmioRegMask = 0x3FF,
.PmioRegMask = 0x380,
.NumPins = 8,
.NumGroups = 1,
.Groups = ((u16 []) {
PIN_GRP_TAMPER_TRIGGER_0,
}),
},
};
/****************************************************************************/
/**
* @brief This function returns handle to requested XPm_PinFunc struct
*
* @param FuncId Function ID.
*
* @return Pointer to XPm_PinFunc if successful, NULL otherwise
*
****************************************************************************/
XPm_PinFunc *XPmPinFunc_GetById(u32 FuncId)
{
XPm_PinFunc *PinFunc = NULL;
if ((u32)MAX_FUNCTION > FuncId) {
PinFunc = &PmPinFuncs[FuncId];
}
return PinFunc;
}
/****************************************************************************/
/**
* @brief This function returns total number of functions available.
*
* @param NumFuncs Number of functions.
*
* @return XST_SUCCESS.
*
****************************************************************************/
XStatus XPmPinFunc_GetNumFuncs(u32 *NumFuncs)
{
*NumFuncs = (u32)MAX_FUNCTION;
return XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief This function returns function name based on function ID.
*
* @param FuncId Function ID.
* @param FuncName Name of the function.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPinFunc_GetFuncName(u32 FuncId, char *FuncName)
{
XStatus Status = XST_FAILURE;
XPm_PinFunc *PinFunc = NULL;
(void)memset(FuncName, 0, FUNC_QUERY_NAME_LEN);
PinFunc = XPmPinFunc_GetById(FuncId);
if (NULL == PinFunc) {
goto done;
}
(void)memcpy(FuncName, &PinFunc->Name[0], FUNC_QUERY_NAME_LEN);
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function returns number of groups in function based on
* function ID.
*
* @param FuncId Function ID.
* @param NumGroups Number of groups.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPinFunc_GetNumFuncGroups(u32 FuncId, u32 *NumGroups)
{
XStatus Status = XST_FAILURE;
XPm_PinFunc *PinFunc = NULL;
PinFunc = XPmPinFunc_GetById(FuncId);
if (NULL != PinFunc) {
*NumGroups = PinFunc->NumGroups;
Status = XST_SUCCESS;
}
return Status;
}
/****************************************************************************/
/**
* @brief This function returns groups present in function based on
* function ID. Index 0 returns the first 6 group IDs, index 6
* returns the next 6 group IDs, and so forth.
*
* @param FuncId Function ID.
* @param Index Index of next function groups
* @param Groups Function groups.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPinFunc_GetFuncGroups(u32 FuncId, u32 Index, u16 *Groups)
{
XStatus Status = XST_FAILURE;
u32 i;
u32 num_read;
XPm_PinFunc *PinFunc = NULL;
(void)memset(Groups, (s32)END_OF_GRP, (MAX_GROUPS_PER_RES * sizeof(u16)));
PinFunc = XPmPinFunc_GetById(FuncId);
if ((NULL == PinFunc) || (Index > PinFunc->NumGroups)) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Read up to 6 group IDs from Index */
if ((PinFunc->NumGroups - Index) > MAX_GROUPS_PER_RES) {
num_read = MAX_GROUPS_PER_RES;
} else {
num_read = PinFunc->NumGroups - Index;
}
for (i = 0; i < num_read; i++) {
Groups[i] = PinFunc->Groups[i + Index];
}
Status = XST_SUCCESS;
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/versal/xsecure_ecdsa_rsa_hw.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xecdsa_rsa_hw.h
*
* This header file contains RSA ECDSA core hardware register offsets of versal.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 4.0 vns 02/14/19 First Release
* 4.1 kpt 01/07/20 Added MACRO
* XSECURE_ECDSA_RSA_CFG_REVERT_ENDIANNESS_MASK
* </pre>
*
******************************************************************************/
#ifndef XSECURE_ECDSA_RSA_H_
#define XSECURE_ECDSA_RSA_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/* ECDSA RSA core's base Address */
#define XSECURE_ECDSA_RSA_BASEADDR (0xF1200000U)
/**< Base address of ECDSA RSA core */
/* Register offsets */
/**
* Register: RAM data register
*/
#define XSECURE_ECDSA_RSA_RAM_DATA_OFFSET (0x00000000U)
/**
* Register: RAM address register
*/
#define XSECURE_ECDSA_RSA_RAM_ADDR_OFFSET (0x00000004U)
#define XSECURE_ECDSA_RSA_RAM_ADDR_WRRD_B_MASK (0x80000000U)
#define XSECURE_ECDSA_RSA_RAM_ADDR_ADDR_MASK (0x7FFFFFFFU)
/**
* Register: Control register
*/
#define XSECURE_ECDSA_RSA_CTRL_OFFSET (0x00000008U)
#define XSECURE_ECDSA_RSA_CTRL_CLR_DATA_BUF_SHIFT (7U)
#define XSECURE_ECDSA_RSA_CTRL_CLR_DATA_BUF_MASK (0x00000080U)
#define XSECURE_ECDSA_RSA_CTRL_CLR_DONE_ABORT_SHIFT (6U)
#define XSECURE_ECDSA_RSA_CTRL_CLR_DONE_ABORT_MASK (0x00000040U)
#define XSECURE_ECDSA_RSA_CTRL_OPCODE_MASK (0x00000007U)
/**
* Register: Status Register
*/
#define XSECURE_ECDSA_RSA_STATUS_OFFSET (0x0000000CU)
#define XSECURE_ECDSA_RSA_STATUS_PROG_CNT_SHIFT (3U)
#define XSECURE_ECDSA_RSA_STATUS_PROG_CNT_MASK (0x000000F8U)
#define XSECURE_ECDSA_RSA_STATUS_ERR_SHIFT (2U)
#define XSECURE_ECDSA_RSA_STATUS_ERR_MASK (0x00000004U)
#define XSECURE_ECDSA_RSA_STATUS_BUSY_SHIFT (1U)
#define XSECURE_ECDSA_RSA_STATUS_BUSY_MASK (0x00000002U)
#define XSECURE_ECDSA_RSA_STATUS_DONE_MASK (0x00000001U)
/**
* Register: MINV value register
*/
#define XSECURE_ECDSA_RSA_MINV_OFFSET (0x00000010U)
/**
* Register: Key Length register
*/
#define XSECURE_ECDSA_RSA_KEY_LEN_OFFSET (0x00000020U)
#define XSECURE_ECDSA_RSA_KEY_LEN_BIN_PRIME_SHIFT (15U)
#define XSECURE_ECDSA_RSA_KEY_LEN_BIN_PRIME_MASK (0x00008000U)
#define XSECURE_ECDSA_RSA_KEY_LEN_MASK (0x00007FFFU)
/**
* Register: CFG 0
*/
#define XSECURE_ECDSA_RSA_CFG0_OFFSET (0x00000028U)
#define XSECURE_ECDSA_RSA_CFG0_QSEL_SHIFT (6U)
#define XSECURE_ECDSA_RSA_CFG0_QSEL_MASK (0x000000C0U)
#define XSECURE_ECDSA_RSA_CFG0_MULTI_PASS_MASK (0x0000003FU)
/**
* Register: CFG 1
*/
#define XSECURE_ECDSA_RSA_CFG1_OFFSET (0x0000002CU)
#define XSECURE_ECDSA_RSA_CFG1_MONT_DIGIT_MASK (0x000000FFU)
/**
* Register: CFG 2
*/
#define XSECURE_ECDSA_RSA_CFG2_OFFSET (0x00000030U)
#define XSECURE_ECDSA_RSA_CFG2_MEM_LOC_SIZE_MASK (0x0000001FU)
/**
* Register: CFG 3
*/
#define XSECURE_ECDSA_RSA_CFG3_OFFSET (0x00000034U)
#define XSECURE_ECDSA_RSA_CFG3_MONT_MOD_SHIFT (4U)
#define XSECURE_ECDSA_RSA_CFG3_MONT_MOD_MASK (0x000000F0U)
#define XSECURE_ECDSA_RSA_CFG3_SCRATCH_MASK (0x0000000FU)
/**
* Register: XSECURE_ECDSA_RSA_CFG4
*/
#define XSECURE_ECDSA_RSA_CFG4_OFFSET (0x00000038U)
#define XSECURE_ECDSA_RSA_CFG4_START_ADDR_MASK (0x000000FFU)
/**
* Register: XSECURE_ECDSA_RSA_CFG5
*/
#define XSECURE_ECDSA_RSA_CFG5_OFFSET (0x0000003CU)
#define XSECURE_ECDSA_RSA_CFG5_NO_GROUPS_MASK (0x0000001FU)
/**
* Register: XSECURE_ECDSA_RSA_RESET
*/
#define XSECURE_ECDSA_RSA_RESET_OFFSET (0x00000040U)
/**
* Register: XSECURE_ECDSA_RSA_APB_SLAVE_ERR_CTRL
*/
#define XSECURE_ECDSA_RSA_APB__ERR_CTRL_OFFSET (0x00000044U)
/**
* Register: XSECURE_ECDSA_RSA_RSA_CFG
*/
#define XSECURE_ECDSA_RSA_CFG_OFFSET (0x00000058U)
#define XSECURE_ECDSA_RSA_CFG_RD_ENDIANNESS_MASK (0x00000002U)
#define XSECURE_ECDSA_RSA_RSA_CFG_WR_ENDIANNESS_MASK (0x00000001U)
#define XSECURE_ECDSA_RSA_CFG_REVERT_ENDIANNESS_MASK (0U)
/**
* Register: XSECURE_ECDSA_RSA_ECO
*/
#define XSECURE_ECDSA_RSA_ECO_OFFSET (0x00000060U)
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_ECDSA_RSA_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_psm.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xil_io.h"
#include "xpm_regs.h"
#include "xpm_psm.h"
#define GLOBAL_CNTRL(BASE) ((BASE) + PSM_GLOBAL_CNTRL)
#define PWR_UP_EN(BASE) ((BASE) + PSM_GLOBAL_REQ_PWRUP_EN)
#define PWR_UP_TRIG(BASE) ((BASE) + PSM_GLOBAL_REQ_PWRUP_TRIG)
#define PWR_DN_EN(BASE) ((BASE) + PSM_GLOBAL_REQ_PWRDWN_EN)
#define PWR_DN_TRIG(BASE) ((BASE) + PSM_GLOBAL_REQ_PWRDWN_TRIG)
#define PWR_DN_STAT(BASE) ((BASE) + PSM_GLOBAL_REQ_PWRDWN_STAT)
#define SLEEP_EN(BASE) ((BASE) + PSM_GLOBAL_PWR_CTRL_EN)
#define SLEEP_DIS(BASE) ((BASE) + PSM_GLOBAL_PWR_CTRL_DIS)
#define SLEEP_TRIG(BASE) ((BASE) + PSM_GLOBAL_PWR_CTRL_TRIG)
#define PWR_STAT(BASE) ((BASE) + PSM_GLOBAL_PWR_STATE)
static XStatus XPmPsm_WakeUp(XPm_Core *Core, u32 SetAddress,
u64 Address)
{
XStatus Status = XST_FAILURE;
XPm_Psm *Psm = (XPm_Psm *)Core;
u32 CRLBaseAddress = Psm->CrlBaseAddr;
/* Set reset address */
if (1U == SetAddress) {
if (0U != Address) {
PmWarn("Handoff address is not used for PSM.\r\n");
}
Status = XST_INVALID_PARAM;
goto done;
}
/* Assert wakeup bit to Wakeup PSM */
PmRmw32(CRLBaseAddress + CRL_PSM_RST_MODE_OFFSET, XPM_PSM_WAKEUP_MASK, XPM_PSM_WAKEUP_MASK);
/* Wait for PSMFW to initialize */
Status = XPm_PollForMask(GLOBAL_CNTRL(Psm->PsmGlobalBaseAddr),
PSM_GLOBAL_REG_GLOBAL_CNTRL_FW_IS_PRESENT_MASK,
XPM_MAX_POLL_TIMEOUT);
done:
return Status;
}
static struct XPm_CoreOps PsmOps = {
.RestoreResumeAddr = NULL,
.HasResumeAddr = NULL,
.RequestWakeup = XPmPsm_WakeUp,
.PowerDown = NULL,
};
XStatus XPmPsm_Init(XPm_Psm *Psm,
u32 Ipi,
u32 *BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock, XPm_ResetNode *Reset)
{
XStatus Status = XST_FAILURE;
Status = XPmCore_Init(&Psm->Core, PM_DEV_PSM_PROC, Power, Clock, Reset,
(u8)Ipi, &PsmOps);
if (XST_SUCCESS != Status) {
goto done;
}
Psm->PsmGlobalBaseAddr = BaseAddress[0];
Psm->CrlBaseAddr = BaseAddress[1];
done:
return Status;
}
XStatus XPmPsm_SendPowerUpReq(u32 BitMask)
{
XStatus Status = XST_FAILURE;
u32 Reg;
XPm_Psm *Psm;
PmDbg("BitMask=0x%08X\n\r", BitMask);
Psm = (XPm_Psm *)XPmDevice_GetById(PM_DEV_PSM_PROC);
if (NULL == Psm) {
goto done;
}
if (1U != XPmPsm_FwIsPresent()) {
Status = XST_NOT_ENABLED;
goto done;
}
/* Check if already powered up */
PmIn32(PWR_STAT(Psm->PsmGlobalBaseAddr), Reg);
if (BitMask == (Reg & BitMask)) {
Status = XST_SUCCESS;
goto done;
}
PmOut32(PWR_UP_TRIG(Psm->PsmGlobalBaseAddr), BitMask);
PmOut32(PWR_UP_EN(Psm->PsmGlobalBaseAddr), BitMask);
do {
PmIn32(PWR_STAT(Psm->PsmGlobalBaseAddr), Reg);
} while ((Reg & BitMask) != BitMask);
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmPsm_SendPowerDownReq(u32 BitMask)
{
XStatus Status = XST_FAILURE;
u32 Reg;
XPm_Psm *Psm;
XPm_Power *Ocm0 = XPmPower_GetById(PM_POWER_OCM_0);
XPm_Power *Ocm1 = XPmPower_GetById(PM_POWER_OCM_1);
XPm_Power *Ocm2 = XPmPower_GetById(PM_POWER_OCM_2);
XPm_Power *Ocm3 = XPmPower_GetById(PM_POWER_OCM_3);
/*
* As per EDT-995988, Getting the SLV error from power down
* island even when Dec error disabled
*
* OCM gives SLVERR response when a powered-down bank is
* accessed, even when Response Error is disabled. Error occurs
* only for a narrow access (< 64 bits). Skip OCM power down as
* workaround.
*/
if ((BitMask == Ocm0->Node.BaseAddress) ||
(BitMask == Ocm1->Node.BaseAddress) ||
(BitMask == Ocm2->Node.BaseAddress) ||
(BitMask == Ocm3->Node.BaseAddress)) {
Status = XST_SUCCESS;
goto done;
}
PmDbg("BitMask=0x%08X\n\r", BitMask);
Psm = (XPm_Psm *)XPmDevice_GetById(PM_DEV_PSM_PROC);
if (NULL == Psm) {
goto done;
}
if (1U != XPmPsm_FwIsPresent()) {
Status = XST_NOT_ENABLED;
goto done;
}
/* Check if already powered down */
PmIn32(PWR_STAT(Psm->PsmGlobalBaseAddr), Reg);
if (0U == (Reg & BitMask)) {
Status = XST_SUCCESS;
goto done;
}
PmOut32(PWR_DN_TRIG(Psm->PsmGlobalBaseAddr), BitMask);
PmOut32(PWR_DN_EN(Psm->PsmGlobalBaseAddr), BitMask);
do {
PmIn32(PWR_DN_STAT(Psm->PsmGlobalBaseAddr), Reg);
} while (0U != (Reg & BitMask));
Status = XST_SUCCESS;
done:
return Status;
}
u32 XPmPsm_FwIsPresent(void)
{
u32 Reg = 0U;
XPm_Psm *Psm;
Psm = (XPm_Psm *)XPmDevice_GetById(PM_DEV_PSM_PROC);
if (NULL == Psm) {
goto done;
}
PmIn32(GLOBAL_CNTRL(Psm->PsmGlobalBaseAddr), Reg)
if (PSM_GLOBAL_REG_GLOBAL_CNTRL_FW_IS_PRESENT_MASK ==
(Reg & PSM_GLOBAL_REG_GLOBAL_CNTRL_FW_IS_PRESENT_MASK)) {
Reg = 1U;
}
done:
return Reg;
}
void XPmPsm_RegWrite(const u32 Offset, const u32 Value)
{
XPm_Psm *Psm;
Psm = (XPm_Psm *)XPmDevice_GetById(PM_DEV_PSM_PROC);
if (NULL == Psm) {
goto done;
}
PmOut32(Psm->PsmGlobalBaseAddr + Offset, Value);
done:
return;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/xsecure_utils.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_utils.c
* This file contains common functionalities required for xilsecure library
* like functions to read/write hardware registers, SSS switch configurations.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 4.0 vns 03/09/19 Initial release
* psl 03/26/19 Fixed MISRA-C violation
* psl 04/05/19 Fixed IAR warnings.
* 4.1 psl 07/31/19 Fixed MISRA-C violation
* 4.2 har 01/03/20 Added blind write check for SssCfg
* vns 01/24/20 Added assert statements to input arguments
* har 03/26/20 Removed code for SSS configuration
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsecure_utils.h"
/************************** Constant Definitions *****************************/
/************************** Function Prototypes ******************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* @brief
* This function takes the hardware core out of reset.
*
* @param BaseAddress Base address of the core.
* @param BaseAddress Offset of the reset register.
*
* @return None
*
*****************************************************************************/
void XSecure_ReleaseReset(u32 BaseAddress, u32 Offset)
{
/* Assert validates the input arguments */
Xil_AssertVoid(BaseAddress != 0x00);
XSecure_WriteReg(BaseAddress, Offset, XSECURE_RESET_SET);
XSecure_WriteReg(BaseAddress, Offset, XSECURE_RESET_UNSET);
}
/*****************************************************************************/
/**
* @brief
* This function places the hardware core into the reset.
*
* @param BaseAddress Base address of the core.
* @param BaseAddress Offset of the reset register.
*
* @return None
*
*****************************************************************************/
void XSecure_SetReset(u32 BaseAddress, u32 Offset)
{
/* Assert validates the input arguments */
Xil_AssertVoid(BaseAddress != 0x00);
XSecure_WriteReg(BaseAddress, Offset, XSECURE_RESET_SET);
}
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/rfdc_v8_0/src/xrfdc_mb.c
/******************************************************************************
* Copyright (C) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrfdc_mb.c
* @addtogroup rfdc_v8_0
* @{
*
* Contains the interface functions of the Mixer Settings in XRFdc driver.
* See xrfdc.h for a detailed description of the device and driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 6.0 cog 02/17/18 Initial release/handle alternate bound out.
* 7.0 cog 05/13/19 Formatting changes.
* cog 08/02/19 Formatting changes.
* 7.1 cog 12/20/19 Metal log messages are now more descriptive.
* cog 01/29/20 Fixed metal log typos.
* 8.0 cog 02/10/20 Updated addtogroup.
* cog 03/20/20 Clock enables for new bondout.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xrfdc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
static void XRFdc_SetSignalFlow(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Mode, u32 DigitalDataPathId,
u32 MixerInOutDataType, int ConnectIData, int ConnectQData);
static void XRFdc_MB_R2C_C2R(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 NoOfDataPaths, u32 MixerInOutDataType,
u32 Mode, u32 DataPathIndex[], u32 BlockIndex[]);
static void XRFdc_MB_C2C(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 NoOfDataPaths, u32 MixerInOutDataType, u32 Mode,
u32 DataPathIndex[], u32 BlockIndex[]);
static void XRFdc_SB_R2C_C2R(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 MixerInOutDataType, u32 Mode,
u32 DataPathIndex[], u32 BlockIndex[]);
static void XRFdc_SB_C2C(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 MixerInOutDataType, u32 Mode,
u32 DataPathIndex[], u32 BlockIndex[]);
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Static API to setup Singleband configuration for C2C MixerInOutDataType
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param MixerInOutDataType is mixer data type, valid values are XRFDC_MB_DATATYPE_*
* @param Mode is connection mode SB/MB_2X/MB_4X.
* @param DataPathIndex is the array that represents the blocks enabled in
* DigitalData Path.
* @param BlockIndex is the array that represents the blocks enabled in
* Analog Path(Data Converters).
*
* @return
* - None
*
* @note Static API for ADC/DAC blocks
*
******************************************************************************/
static void XRFdc_SB_C2C(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 MixerInOutDataType, u32 Mode,
u32 DataPathIndex[], u32 BlockIndex[])
{
u32 Block_Id;
if ((Type == XRFDC_ADC_TILE) && (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
/* Update ConnectedIData and ConnectedQData for ADC 4GSPS */
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData =
BlockIndex[1U];
Block_Id = (DataPathIndex[0] == 0U ? 1U : 0U);
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].ConnectedIData = -1;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].ConnectedQData = -1;
if (DataPathIndex[0] == XRFDC_BLK_ID1) {
DataPathIndex[0] = XRFDC_BLK_ID2;
}
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType,
BlockIndex[0U], BlockIndex[0U] + 1U);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0] + 1U, MixerInOutDataType,
BlockIndex[1U] + 1U, BlockIndex[1U] + 2U);
Block_Id = (DataPathIndex[0] == XRFDC_BLK_ID2 ? XRFDC_BLK_ID0 : XRFDC_BLK_ID2);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, Block_Id, MixerInOutDataType, -1, -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, Block_Id + 1U, MixerInOutDataType, -1, -1);
} else {
DataPathIndex[1] = BlockIndex[0] + BlockIndex[1] - DataPathIndex[0];
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType,
BlockIndex[0], BlockIndex[1]);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[1], MixerInOutDataType, -1, -1);
/* Update ConnectedIData and ConnectedQData for DAC and ADC 2GSPS */
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData =
BlockIndex[1];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData = -1;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData = -1;
} else {
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData =
BlockIndex[1];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData = -1;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData = -1;
}
}
}
/*****************************************************************************/
/**
*
* Static API to setup Singleband configuration for C2R and R2C MultiBandDataTypes
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param MixerInOutDataType is mixer data type, valid values are XRFDC_MB_DATATYPE_*
* @param Mode is connection mode SB/MB_2X/MB_4X.
* @param DataPathIndex is the array that represents the blocks enabled in
* DigitalData Path.
* @param BlockIndex is the array that represents the blocks enabled in
* Analog Path(Data Converters).
*
* @return
* - None
*
* @note Static API for ADC/DAC blocks
*
******************************************************************************/
static void XRFdc_SB_R2C_C2R(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 MixerInOutDataType, u32 Mode,
u32 DataPathIndex[], u32 BlockIndex[])
{
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData = -1;
} else {
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData = -1;
}
if ((Type == XRFDC_ADC_TILE) && (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
if (DataPathIndex[0] == XRFDC_BLK_ID1) {
DataPathIndex[0] = XRFDC_BLK_ID2;
}
if (BlockIndex[0] == XRFDC_BLK_ID1) {
BlockIndex[0] = XRFDC_BLK_ID2;
}
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0] + 1U, MixerInOutDataType,
BlockIndex[0U] + 1U, -1);
}
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType, BlockIndex[0U], -1);
}
/*****************************************************************************/
/**
*
* Static API to setup Multiband configuration for C2C MixerInOutDataType
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param MixerInOutDataType is mixer data type, valid values are XRFDC_MB_DATATYPE_*
* @param Mode is connection mode SB/MB_2X/MB_4X.
* @param DataPathIndex is the array that represents the blocks enabled in
* DigitalData Path.
* @param BlockIndex is the array that represents the blocks enabled in
* Analog Path(Data Converters).
*
* @return
* - None
*
* @note Static API for ADC/DAC blocks
*
******************************************************************************/
static void XRFdc_MB_C2C(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 NoOfDataPaths, u32 MixerInOutDataType, u32 Mode,
u32 DataPathIndex[], u32 BlockIndex[])
{
if ((Type == XRFDC_ADC_TILE) && (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType,
BlockIndex[0U], BlockIndex[0U] + 1U);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0] + 1U, MixerInOutDataType,
BlockIndex[0U] + 2U, BlockIndex[0U] + 3U);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0] + 2U, MixerInOutDataType,
BlockIndex[0U], BlockIndex[0U] + 1U);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0] + 3U, MixerInOutDataType,
BlockIndex[0U] + 2U, BlockIndex[0U] + 3U);
/* Update ConnectedIData and ConnectedQData for ADC 4GSPS */
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData =
BlockIndex[1U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData =
BlockIndex[1U];
} else if (NoOfDataPaths == 2U) {
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType,
BlockIndex[0U], BlockIndex[1U]);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[1], MixerInOutDataType,
BlockIndex[0U], BlockIndex[1U]);
/* Update ConnectedIData and ConnectedQData for DAC and ADC 2GSPS */
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData =
BlockIndex[1U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData =
BlockIndex[1U];
} else {
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData =
BlockIndex[1U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData =
BlockIndex[0U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData =
BlockIndex[1U];
}
}
if (NoOfDataPaths == 4U) {
if (Type == XRFDC_ADC_TILE) {
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType,
BlockIndex[0U], BlockIndex[1U]);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[1], MixerInOutDataType,
BlockIndex[0U], BlockIndex[1U]);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[2], MixerInOutDataType,
BlockIndex[0U], BlockIndex[1U]);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[3], MixerInOutDataType,
BlockIndex[0U], BlockIndex[1U]);
/* Update ConnectedIData and ConnectedQData for ADC 4GSPS */
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData =
BlockIndex[1U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData =
BlockIndex[1U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[2]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[2]].ConnectedQData =
BlockIndex[1U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[3]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[3]].ConnectedQData =
BlockIndex[1U];
} else {
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType,
DataPathIndex[0], DataPathIndex[1U]);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[1], MixerInOutDataType,
DataPathIndex[0U], DataPathIndex[1U]);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[2], MixerInOutDataType,
DataPathIndex[2U], DataPathIndex[3U]);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[3], MixerInOutDataType,
DataPathIndex[2U], DataPathIndex[3U]);
/* Update ConnectedIData and ConnectedQData for DAC and ADC 2GSPS */
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData =
BlockIndex[1U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData =
BlockIndex[0U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData =
BlockIndex[1U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[2]].ConnectedIData =
DataPathIndex[0U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[2]].ConnectedQData =
DataPathIndex[1U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[3]].ConnectedIData =
DataPathIndex[0U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[3]].ConnectedQData =
DataPathIndex[1U];
}
}
}
/*****************************************************************************/
/**
*
* Static API to setup Multiband configuration for C2C MixerInOutDataType
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param MixerInOutDataType is mixer data type, valid values are XRFDC_MB_DATATYPE_*
* @param Mode is connection mode SB/MB_2X/MB_4X.
* @param DataPathIndex is the array that represents the blocks enabled in
* DigitalData Path.
* @param BlockIndex is the array that represents the blocks enabled in
* Analog Path(Data Converters).
*
* @return
* - None
*
* @note Static API for ADC/DAC blocks
*
******************************************************************************/
static void XRFdc_MB_R2C_C2R(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 NoOfDataPaths, u32 MixerInOutDataType,
u32 Mode, u32 DataPathIndex[], u32 BlockIndex[])
{
if ((Type == XRFDC_ADC_TILE) && (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
/* Update ConnectedIData and ConnectedQData */
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData = -1;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData = -1;
if (BlockIndex[0] == XRFDC_BLK_ID1) {
BlockIndex[0] = XRFDC_BLK_ID2;
}
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType,
BlockIndex[0U], -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[1], MixerInOutDataType,
BlockIndex[0U] + 1U, -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0] + 2U, MixerInOutDataType,
BlockIndex[0U], -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[1] + 2U, MixerInOutDataType,
BlockIndex[0U] + 1U, -1);
} else if (NoOfDataPaths == 2U) {
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType,
BlockIndex[0], -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[1], MixerInOutDataType,
BlockIndex[0], -1);
/* Update ConnectedIData and ConnectedQData */
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData = -1;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData = -1;
} else {
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData = -1;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData =
BlockIndex[0U];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData = -1;
}
}
if (NoOfDataPaths == 4U) {
if (Type == XRFDC_ADC_TILE) {
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType,
BlockIndex[0], -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[1], MixerInOutDataType,
BlockIndex[0], -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[2], MixerInOutDataType,
BlockIndex[0], -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[3], MixerInOutDataType,
BlockIndex[0], -1);
/* Update ConnectedIData and ConnectedQData */
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData = -1;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData = -1;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[2]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[2]].ConnectedQData = -1;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[3]].ConnectedIData =
BlockIndex[0U];
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[DataPathIndex[3]].ConnectedQData = -1;
} else {
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[0], MixerInOutDataType,
DataPathIndex[0], -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[1], MixerInOutDataType,
DataPathIndex[0], -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[2], MixerInOutDataType,
DataPathIndex[2], -1);
XRFdc_SetSignalFlow(InstancePtr, Type, Tile_Id, Mode, DataPathIndex[3], MixerInOutDataType,
DataPathIndex[2], -1);
/* Update ConnectedIData and ConnectedQData */
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedIData =
DataPathIndex[0];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[0]].ConnectedQData = -1;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[1]].ConnectedIData =
DataPathIndex[0];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[1]].ConnectedQData = -1;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[2]].ConnectedIData =
DataPathIndex[0];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[2]].ConnectedQData = -1;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[3]].ConnectedIData =
DataPathIndex[0];
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[DataPathIndex[3]].ConnectedQData = -1;
}
}
}
/*****************************************************************************/
/**
*
* Static API to update mode and MultibandConfig
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param NoOfDataPaths is number of DataPaths enabled.
* @param ModePtr is a pointer to connection mode SB/MB_2X/MB_4X.
* @param DataPathIndex is the array that represents the blocks enabled in
* DigitalData Path.
*
* @return
* - None
*
* @note Static API for ADC/DAC blocks
*
******************************************************************************/
static u32 XRFdc_UpdateMBConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 NoOfDataPaths, u32 *ModePtr,
u32 DataPathIndex[])
{
u8 MultibandConfig;
u32 Status;
if (Type == XRFDC_ADC_TILE) {
MultibandConfig = InstancePtr->ADC_Tile[Tile_Id].MultibandConfig;
} else {
MultibandConfig = InstancePtr->DAC_Tile[Tile_Id].MultibandConfig;
}
if (NoOfDataPaths == 1U) {
*ModePtr = XRFDC_SINGLEBAND_MODE;
if (((DataPathIndex[0] == XRFDC_BLK_ID2) || (DataPathIndex[0] == XRFDC_BLK_ID3)) &&
((MultibandConfig == XRFDC_MB_MODE_2X_BLK01_BLK23) || (MultibandConfig == XRFDC_MB_MODE_4X))) {
MultibandConfig = XRFDC_MB_MODE_2X_BLK01;
} else if (((DataPathIndex[0] == XRFDC_BLK_ID0) || (DataPathIndex[0] == XRFDC_BLK_ID1)) &&
((MultibandConfig == XRFDC_MB_MODE_2X_BLK01_BLK23) ||
(MultibandConfig == XRFDC_MB_MODE_4X))) {
MultibandConfig = XRFDC_MB_MODE_2X_BLK23;
} else if ((MultibandConfig == XRFDC_MB_MODE_2X_BLK01) &&
((DataPathIndex[0] == XRFDC_BLK_ID0) || (DataPathIndex[0] == XRFDC_BLK_ID1))) {
MultibandConfig = XRFDC_MB_MODE_SB;
} else if ((MultibandConfig == XRFDC_MB_MODE_2X_BLK23) &&
((DataPathIndex[0] == XRFDC_BLK_ID2) || (DataPathIndex[0] == XRFDC_BLK_ID3))) {
MultibandConfig = XRFDC_MB_MODE_SB;
}
} else if (NoOfDataPaths == 2U) {
*ModePtr = XRFDC_MULTIBAND_MODE_2X;
if (((MultibandConfig == XRFDC_MB_MODE_2X_BLK01) && (DataPathIndex[0] == XRFDC_BLK_ID2) &&
(DataPathIndex[1] == XRFDC_BLK_ID3)) ||
((MultibandConfig == XRFDC_MB_MODE_2X_BLK23) && (DataPathIndex[0] == XRFDC_BLK_ID0) &&
(DataPathIndex[1] == XRFDC_BLK_ID1)) ||
(MultibandConfig == XRFDC_MB_MODE_4X)) {
MultibandConfig = XRFDC_MB_MODE_2X_BLK01_BLK23;
} else if (((DataPathIndex[0] == XRFDC_BLK_ID2) && (DataPathIndex[1] == XRFDC_BLK_ID3)) &&
(MultibandConfig == XRFDC_MB_MODE_SB)) {
MultibandConfig = XRFDC_MB_MODE_2X_BLK23;
} else if (((DataPathIndex[0] == XRFDC_BLK_ID0) && (DataPathIndex[1] == XRFDC_BLK_ID1)) &&
(MultibandConfig == XRFDC_MB_MODE_SB)) {
MultibandConfig = XRFDC_MB_MODE_2X_BLK01;
}
} else if (NoOfDataPaths == 4U) {
*ModePtr = XRFDC_MULTIBAND_MODE_4X;
MultibandConfig = XRFDC_MB_MODE_4X;
} else {
metal_log(METAL_LOG_ERROR, "\n Invalid Number of Datapaths (%u) for %s %u in %s\r\n", NoOfDataPaths,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
/* Update Multiband Config member */
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].MultibandConfig = MultibandConfig;
} else {
InstancePtr->DAC_Tile[Tile_Id].MultibandConfig = MultibandConfig;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* User-level API to setup multiband configuration.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param DigitalDataPathMask is the DataPath mask. First 4 bits represent
* 4 data paths, 1 means enabled and 0 means disabled.
* @param MixerInOutDataType is mixer data type, valid values are XRFDC_MB_DATATYPE_*
* @param DataConverterMask is block enabled mask (input/output driving
* blocks). 1 means enabled and 0 means disabled.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note Common API for ADC/DAC blocks
*
******************************************************************************/
u32 XRFdc_MultiBand(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 DigitalDataPathMask, u32 MixerInOutDataType,
u32 DataConverterMask)
{
u32 Status;
u32 Block_Id;
u8 NoOfDataPaths = 0U;
u32 BlockIndex[XRFDC_NUM_OF_BLKS4] = { XRFDC_BLK_ID4 };
u32 DataPathIndex[XRFDC_NUM_OF_BLKS4] = { XRFDC_BLK_ID4 };
u32 NoOfDataConverters = 0U;
u32 Mode = 0x0;
u32 NoOfBlocks = XRFDC_BLK_ID4;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
if ((DigitalDataPathMask == 0U) || (DigitalDataPathMask > 0xFU)) {
metal_log(METAL_LOG_ERROR, "\n Invalid DigitalDataPathMask value (0x%x) for %s %u in %s\r\n",
DigitalDataPathMask, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((DataConverterMask == 0U) || (DataConverterMask > 0xFU)) {
metal_log(METAL_LOG_ERROR, "\n Invalid DataConverterMask value (0x%x) for %s %u in %s\r\n",
DataConverterMask, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((MixerInOutDataType != XRFDC_MB_DATATYPE_C2C) && (MixerInOutDataType != XRFDC_MB_DATATYPE_R2C) &&
(MixerInOutDataType != XRFDC_MB_DATATYPE_C2R)) {
metal_log(METAL_LOG_ERROR, "\n Invalid MixerInOutDataType value (%u) for %s %u in %s\r\n",
MixerInOutDataType, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_BLK_ID2;
}
/* Identify DataPathIndex and BlockIndex */
for (Block_Id = XRFDC_BLK_ID0; Block_Id < NoOfBlocks; Block_Id++) {
if ((DataConverterMask & (1U << Block_Id)) != 0U) {
BlockIndex[NoOfDataConverters] = Block_Id;
NoOfDataConverters += 1U;
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
}
if ((DigitalDataPathMask & (1U << Block_Id)) != 0U) {
DataPathIndex[NoOfDataPaths] = Block_Id;
NoOfDataPaths += 1U;
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u digital path %u not enabled in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
}
}
/* rerouting & configuration for alternative bonding. */
if ((Type == XRFDC_DAC_TILE) && (DataConverterMask & 0x05) && (MixerInOutDataType == XRFDC_MB_DATATYPE_C2C) &&
(InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].NumSlices == 2)) {
BlockIndex[XRFDC_BLK_ID1] = XRFDC_BLK_ID1;
XRFdc_ClrSetReg(InstancePtr, XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, XRFDC_BLK_ID1),
XRFDC_DAC_MB_CFG_OFFSET, XRFDC_ALT_BOND_MASK, XRFDC_ENABLED << XRFDC_ALT_BOND_SHIFT);
XRFdc_ClrSetReg(InstancePtr, XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, XRFDC_BLK_ID2),
XRFDC_DAC_MB_CFG_OFFSET, XRFDC_ALT_BOND_MASK, XRFDC_ENABLED << XRFDC_ALT_BOND_SHIFT);
XRFdc_ClrSetReg(InstancePtr, XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, XRFDC_BLK_ID1),
XRFDC_CLK_EN_OFFSET, XRFDC_ALT_BOND_CLKDP_MASK,
XRFDC_ENABLED << XRFDC_ALT_BOND_CLKDP_SHIFT);
}
if (BlockIndex[0] != DataPathIndex[0]) {
metal_log(METAL_LOG_ERROR, "\n Not a valid MB/SB combination for %s %u block %u in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
/* UPdate MultibandConfig in driver instance */
Status = XRFdc_UpdateMBConfig(InstancePtr, Type, Tile_Id, NoOfDataPaths, &Mode, DataPathIndex);
if (Status != XRFDC_SUCCESS) {
goto RETURN_PATH;
}
if ((MixerInOutDataType == XRFDC_MB_DATATYPE_C2C) && (Mode == XRFDC_SINGLEBAND_MODE)) {
/* Singleband C2C */
XRFdc_SB_C2C(InstancePtr, Type, Tile_Id, MixerInOutDataType, Mode, DataPathIndex, BlockIndex);
} else if (((MixerInOutDataType == XRFDC_MB_DATATYPE_R2C) || (MixerInOutDataType == XRFDC_MB_DATATYPE_C2R)) &&
(Mode == XRFDC_SINGLEBAND_MODE)) {
/* Singleband R2C and C2R */
XRFdc_SB_R2C_C2R(InstancePtr, Type, Tile_Id, MixerInOutDataType, Mode, DataPathIndex, BlockIndex);
}
if ((MixerInOutDataType == XRFDC_MB_DATATYPE_C2C) &&
((Mode == XRFDC_MULTIBAND_MODE_2X) || (Mode == XRFDC_MULTIBAND_MODE_4X))) {
/* Multiband C2C */
XRFdc_MB_C2C(InstancePtr, Type, Tile_Id, NoOfDataPaths, MixerInOutDataType, Mode, DataPathIndex,
BlockIndex);
} else if (((MixerInOutDataType == XRFDC_MB_DATATYPE_R2C) || (MixerInOutDataType == XRFDC_MB_DATATYPE_C2R)) &&
((Mode == XRFDC_MULTIBAND_MODE_2X) || (Mode == XRFDC_MULTIBAND_MODE_4X))) {
/* Multiband C2R and R2C */
XRFdc_MB_R2C_C2R(InstancePtr, Type, Tile_Id, NoOfDataPaths, MixerInOutDataType, Mode, DataPathIndex,
BlockIndex);
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Sets up signal flow configuration.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Mode is connection mode SB/MB_2X/MB_4X.
* @param DigitalDataPathId for the requested I or Q data.
* @param MixerInOutDataType is mixer data type, valid values are XRFDC_MB_DATATYPE_*
* @param ConnectIData is analog blocks that are connected to
* DigitalDataPath I.
* @param ConnectQData is analog blocks that are connected to
* DigitalDataPath Q.
*
* @note None.
*
* @note static API used internally.
*
******************************************************************************/
static void XRFdc_SetSignalFlow(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Mode, u32 DigitalDataPathId,
u32 MixerInOutDataType, int ConnectIData, int ConnectQData)
{
u16 ReadReg;
u32 BaseAddr;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, DigitalDataPathId);
if (Type == XRFDC_ADC_TILE) {
/* ADC */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_SWITCH_MATRX_OFFSET);
ReadReg &= ~XRFDC_SWITCH_MTRX_MASK;
if (ConnectIData != -1) {
ReadReg |= ((u16)ConnectIData) << XRFDC_SEL_CB_TO_MIX0_SHIFT;
}
if (ConnectQData != -1) {
ReadReg |= (u16)ConnectQData;
}
if ((MixerInOutDataType == XRFDC_MB_DATATYPE_C2C) &&
(XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1)) {
ReadReg |= XRFDC_SEL_CB_TO_QMC_MASK;
}
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
ReadReg |= XRFDC_SEL_CB_TO_DECI_MASK;
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_SWITCH_MATRX_OFFSET, ReadReg);
} else {
/* DAC */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DAC_MB_CFG_OFFSET);
ReadReg &= ~XRFDC_MB_CFG_MASK;
if (Mode == XRFDC_SINGLEBAND_MODE) {
if ((u32)ConnectIData == DigitalDataPathId) {
if (ConnectQData != -1) {
ReadReg |= XRFDC_SB_C2C_BLK0;
} else {
ReadReg |= XRFDC_SB_C2R;
}
}
if ((ConnectIData == -1) && (ConnectQData == -1)) {
ReadReg |= XRFDC_SB_C2C_BLK1;
}
} else {
if (Mode == XRFDC_MULTIBAND_MODE_4X) {
ReadReg |= XRFDC_MB_EN_4X_MASK;
}
if ((u32)ConnectIData == DigitalDataPathId) {
if (ConnectQData != -1) {
ReadReg |= XRFDC_MB_C2C_BLK0;
} else {
ReadReg |= XRFDC_MB_C2R_BLK0;
}
} else {
if (ConnectQData != -1) {
ReadReg |= XRFDC_MB_C2C_BLK1;
} else {
ReadReg |= XRFDC_MB_C2R_BLK1;
}
}
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_DAC_MB_CFG_OFFSET, ReadReg);
}
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/client/pm_client.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "pm_client.h"
#include <xil_cache.h>
#include "xpm_nodeid.h"
#if defined (__aarch64__)
#include <xreg_cortexa53.h>
#elif defined (__arm__)
#include <xreg_cortexr5.h>
#endif
#define XPM_ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#define PM_AFL0_MASK (0xFFU)
#define WFI __asm__ ("wfi")
#if defined (__aarch64__)
#define APU_PWRCTRL_OFFSET (0x90U)
#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK (0x00000001U)
#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK (0x00000002U)
static struct XPm_Proc Proc_APU0 = {
.DevId = PM_DEV_ACPU_0,
.PwrCtrl = XPAR_PSV_APU_0_S_AXI_BASEADDR + APU_PWRCTRL_OFFSET,
.PwrDwnMask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK,
.Ipi = NULL,
};
static struct XPm_Proc Proc_APU1 = {
.DevId = PM_DEV_ACPU_1,
.PwrCtrl = XPAR_PSV_APU_0_S_AXI_BASEADDR + APU_PWRCTRL_OFFSET,
.PwrDwnMask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK,
.Ipi = NULL,
};
static struct XPm_Proc *const ProcList[] = {
&Proc_APU0,
&Proc_APU1,
};
struct XPm_Proc *PrimaryProc = &Proc_APU0;
#elif defined (__arm__)
#define RPU_0_PWRDWN_OFFSET (0x108U)
#define RPU_1_PWRDWN_OFFSET (0x208U)
#define RPU_PWRDWN_EN_MASK (0x1U)
#define RPU_GLBL_CTRL_OFFSET (0x00U)
#define RPU_GLBL_CNTL_SLSPLIT_MASK (0x00000008U)
static struct XPm_Proc Proc_RPU0 = {
.DevId = PM_DEV_RPU0_0,
.PwrCtrl = XPAR_PSV_RPU_0_S_AXI_BASEADDR + RPU_0_PWRDWN_OFFSET,
.PwrDwnMask = RPU_PWRDWN_EN_MASK,
.Ipi = NULL,
};
static struct XPm_Proc Proc_RPU1 = {
.DevId = PM_DEV_RPU0_1,
.PwrCtrl = XPAR_PSV_RPU_0_S_AXI_BASEADDR + RPU_1_PWRDWN_OFFSET,
.PwrDwnMask = RPU_PWRDWN_EN_MASK,
.Ipi = NULL,
};
static struct XPm_Proc *const ProcList[] = {
&Proc_RPU0,
&Proc_RPU1,
};
struct XPm_Proc *PrimaryProc = &Proc_RPU0;
char ProcName[5] = "RPU";
static char RPU_LS[] = "RPU";
static char RPU0[] = "RPU0";
static char RPU1[] = "RPU1";
#endif
/**
* XPm_SetPrimaryProc() - Set primary processor based on processor ID
*/
void XPm_SetPrimaryProc(void)
{
u32 ProcId;
#if defined (__aarch64__)
ProcId = ((u32)mfcp(MPIDR_EL1) & PM_AFL0_MASK);
#elif defined (__arm__)
ProcId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & PM_AFL0_MASK);
if (0U == (XPm_Read(XPAR_PSV_RPU_0_S_AXI_BASEADDR + RPU_GLBL_CTRL_OFFSET) &
RPU_GLBL_CNTL_SLSPLIT_MASK)) {
ProcId = 0;
(void)memcpy(ProcName, RPU_LS, sizeof(RPU_LS));
XPm_Dbg("Running in lock-step mode\r\n");
} else {
if (0U == ProcId) {
(void)memcpy(ProcName, RPU0, sizeof(RPU0));
} else {
(void)memcpy(ProcName, RPU1, sizeof(RPU1));
}
XPm_Dbg("Running in split mode\r\n");
}
#endif
ProcId &= PM_AFL0_MASK;
PrimaryProc = ProcList[ProcId];
}
struct XPm_Proc *XPm_GetProcByDeviceId(u32 DeviceId)
{
struct XPm_Proc *Proc = NULL;
u8 Idx;
for (Idx = 0; Idx < XPM_ARRAY_SIZE(ProcList); Idx++) {
if (DeviceId == ProcList[Idx]->DevId) {
Proc = ProcList[Idx];
break;
}
}
return Proc;
}
void XPm_ClientSuspend(const struct XPm_Proc *const Proc)
{
u32 PwrDwnReg;
/* Disable interrupts at processor level */
XpmDisableInterrupts();
/* Set powerdown request */
PwrDwnReg = XPm_Read(Proc->PwrCtrl);
PwrDwnReg |= Proc->PwrDwnMask;
XPm_Write(Proc->PwrCtrl, PwrDwnReg);
}
void XPm_ClientWakeUp(const struct XPm_Proc *const Proc)
{
if (NULL != Proc) {
u32 Val;
Val = XPm_Read(Proc->PwrCtrl);
Val &= ~Proc->PwrDwnMask;
XPm_Write(Proc->PwrCtrl, Val);
}
}
void XPm_ClientSuspendFinalize(void)
{
u32 CtrlReg;
/* Flush the data cache only if it is enabled */
#ifdef __aarch64__
CtrlReg = (u32)mfcp(SCTLR_EL3);
if (0U != (XREG_CONTROL_DCACHE_BIT & CtrlReg)) {
Xil_DCacheFlush();
}
#else
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
if (0U != (XREG_CP15_CONTROL_C_BIT & CtrlReg)) {
Xil_DCacheFlush();
}
#endif
XPm_Dbg("Going to WFI...\n");
WFI;
XPm_Dbg("WFI exit...\n");
}
void XPm_ClientAbortSuspend(void)
{
u32 PwrDwnReg;
/* Clear powerdown request */
PwrDwnReg = XPm_Read(PrimaryProc->PwrCtrl);
PwrDwnReg &= ~PrimaryProc->PwrDwnMask;
XPm_Write(PrimaryProc->PwrCtrl, PwrDwnReg);
/* Enable interrupts at processor level */
XpmEnableInterrupts();
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pldomain.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PLDOMAIN_H_
#define XPM_PLDOMAIN_H_
#include "xpm_powerdomain.h"
#include "xcframe.h"
#include "xcfupmc.h"
#ifdef __cplusplus
extern "C" {
#endif
extern u32 HcleanDone;
/**
* The PL power domain node class.
*/
typedef struct XPm_PlDomain {
XPm_PowerDomain Domain; /**< Power domain node base class */
u32 CfuApbBaseAddr; /**< CFU APB base address */
u32 Cframe0RegBaseAddr; /**< CFRAME0 Register base address */
} XPm_PlDomain;
/* TRIM Types */
#define XPM_PL_TRIM_VGG (0x1U)
#define XPM_PL_TRIM_CRAM (0x2U)
#define XPM_PL_TRIM_BRAM (0x3U)
#define XPM_PL_TRIM_URAM (0x4U)
/************************** Function Prototypes ******************************/
XStatus XPmPlDomain_InitandHouseclean(void);
XStatus XPmPlDomain_Init(XPm_PlDomain *PlDomain, u32 Id, u32 BaseAddress,
XPm_Power *Parent, u32 *OtherBaseAddresses,
u32 OtherBaseAddressCnt);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_PLDOMAIN_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_clock.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xplmi_util.h"
#include "xpm_clock.h"
#include "xpm_pll.h"
#include "xpm_device.h"
/* Query related defines */
#define CLK_QUERY_NAME_LEN (MAX_NAME_BYTES)
#define CLK_INIT_ENABLE_SHIFT 1U
#define CLK_TYPE_SHIFT 2U
#define CLK_NODETYPE_SHIFT 14U
#define CLK_NODESUBCLASS_SHIFT 20U
#define CLK_NODECLASS_SHIFT 26U
#define CLK_PARENTS_PAYLOAD_LEN 12U
#define CLK_TOPOLOGY_PAYLOAD_LEN 12U
#define CLK_NA_PARENT -1
#define CLK_DUMMY_PARENT -2
#define CLK_CLKFLAGS_SHIFT 8U
#define CLK_TYPEFLAGS_SHIFT 24U
#define CLOCK_PARENT_INVALID 0U
/* Clock Flags */
#define CLK_FLAG_READ_ONLY (1U << 0U)
#define GENERIC_MUX \
{ \
.Type = (u8)TYPE_MUX, \
.Param1.Shift = PERIPH_MUX_SHIFT, \
.Param2.Width = PERIPH_MUX_WIDTH, \
.Clkflags = CLK_SET_RATE_NO_REPARENT | \
CLK_IS_BASIC, \
.Typeflags = NA_TYPE_FLAGS, \
}
#define GENERIC_DIV \
{ \
.Type = (u8)TYPE_DIV1, \
.Param1.Shift = PERIPH_DIV_SHIFT, \
.Param2.Width = PERIPH_DIV_WIDTH, \
.Clkflags = CLK_SET_RATE_NO_REPARENT | \
CLK_IS_BASIC, \
.Typeflags = CLK_DIVIDER_ONE_BASED | \
CLK_DIVIDER_ALLOW_ZERO, \
}
#define GENERIC_GATE(id) \
{ \
.Type = (u8)TYPE_GATE, \
.Param1.Shift = PERIPH_GATE##id##_SHIFT, \
.Param2.Width = PERIPH_GATE_WIDTH, \
.Clkflags = CLK_SET_RATE_PARENT | \
CLK_SET_RATE_GATE | \
CLK_IS_BASIC, \
.Typeflags = NA_TYPE_FLAGS, \
}
static struct XPm_ClkTopologyNode GenericMuxDivNodes[] = {
GENERIC_MUX,
GENERIC_DIV,
};
static struct XPm_ClkTopologyNode GenericMuxGate2Nodes[] = {
GENERIC_MUX,
GENERIC_GATE(2),
};
static struct XPm_ClkTopologyNode GenericDivGate2Nodes[] = {
GENERIC_DIV,
GENERIC_GATE(2),
};
static struct XPm_ClkTopologyNode GenericMuxDivGate1Nodes[] = {
GENERIC_MUX,
GENERIC_DIV,
GENERIC_GATE(1),
};
static struct XPm_ClkTopologyNode GenericMuxDivGate2Nodes[] = {
GENERIC_MUX,
GENERIC_DIV,
GENERIC_GATE(2),
};
static XPm_ClkTopology ClkTopologies[ ] = {
{&GenericMuxDivNodes, TOPOLOGY_GENERIC_MUX_DIV, ARRAY_SIZE(GenericMuxDivNodes), {0}},
{&GenericMuxGate2Nodes, TOPOLOGY_GENERIC_MUX_GATE, ARRAY_SIZE(GenericMuxGate2Nodes), {0}},
{&GenericDivGate2Nodes, TOPOLOGY_GENERIC_DIV_GATE, ARRAY_SIZE(GenericDivGate2Nodes), {0}},
{&GenericMuxDivGate1Nodes, TOPOLOGY_GENERIC_MUX_DIV_GATE_1, ARRAY_SIZE(GenericMuxDivGate1Nodes), {0}},
{&GenericMuxDivGate2Nodes, TOPOLOGY_GENERIC_MUX_DIV_GATE_2, ARRAY_SIZE(GenericMuxDivGate2Nodes), {0}},
{&GenericMuxDivGate2Nodes, TOPOLOGY_GENERIC_MUX_DIV_GATE_2, ARRAY_SIZE(GenericMuxDivGate2Nodes), {0}},
};
static XPm_ClockNode *ClkNodeList[(u32)XPM_NODEIDX_CLK_MAX];
static const u32 MaxClkNodes = (u32)XPM_NODEIDX_CLK_MAX;
static u32 PmNumClocks;
static XStatus XPmClock_Init(XPm_ClockNode *Clk, u32 Id, u32 ControlReg,
u8 TopologyType, u8 NumCustomNodes, u8 NumParents,
u32 PowerDomainId, u8 ClkFlags)
{
XStatus Status = XST_FAILURE;
u32 Subclass = NODESUBCLASS(Id);
if (Subclass == (u32)XPM_NODETYPE_CLOCK_REF) {
XPmNode_Init(&Clk->Node, Id, (u8)XPM_CLK_STATE_ON, 0);
} else if (Subclass == (u32)XPM_NODETYPE_CLOCK_OUT) {
if (NumParents > MAX_MUX_PARENTS) {
Status = XST_INVALID_PARAM;
goto done;
}
XPm_OutClockNode *OutClkPtr = (XPm_OutClockNode *)Clk;
XPmNode_Init(&OutClkPtr->ClkNode.Node, Id, (u8)XPM_CLK_STATE_OFF, 0);
OutClkPtr->ClkNode.Node.BaseAddress = ControlReg;
OutClkPtr->ClkNode.ClkHandles = NULL;
OutClkPtr->ClkNode.UseCount = 0;
OutClkPtr->ClkNode.NumParents = NumParents;
OutClkPtr->ClkNode.Flags = ClkFlags;
if (TopologyType == TOPOLOGY_CUSTOM) {
OutClkPtr->Topology.Id = TOPOLOGY_CUSTOM;
OutClkPtr->Topology.NumNodes = NumCustomNodes;
OutClkPtr->Topology.Nodes = XPm_AllocBytes((u32)NumCustomNodes * sizeof(struct XPm_ClkTopologyNode));
if (OutClkPtr->Topology.Nodes == NULL) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
} else {
OutClkPtr->Topology.Id = ClkTopologies[TopologyType-TOPOLOGY_GENERIC_MUX_DIV].Id;
OutClkPtr->Topology.NumNodes = ClkTopologies[TopologyType-TOPOLOGY_GENERIC_MUX_DIV].NumNodes;
OutClkPtr->Topology.Nodes = ClkTopologies[TopologyType-TOPOLOGY_GENERIC_MUX_DIV].Nodes;
}
} else {
Status = XST_INVALID_PARAM;
goto done;
}
if (((u32)XPM_NODECLASS_POWER != NODECLASS(PowerDomainId)) ||
((u32)XPM_NODESUBCL_POWER_DOMAIN != NODESUBCLASS(PowerDomainId))) {
Clk->PwrDomain = NULL;
Status = XST_SUCCESS;
goto done;
}
Clk->PwrDomain = XPmPower_GetById(PowerDomainId);
if (NULL == Clk->PwrDomain) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
Clk->ClkRate = 0;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_AddNode(u32 Id, u32 ControlReg, u8 TopologyType,
u8 NumCustomNodes, u8 NumParents, u32 PowerDomainId,
u8 ClkFlags)
{
XStatus Status = XST_FAILURE;
u32 Subclass = NODESUBCLASS(Id);
XPm_ClockNode *Clk;
if (NULL != XPmClock_GetById(Id)) {
Status = XST_INVALID_PARAM;
goto done;
}
if (Subclass == (u32)XPM_NODETYPE_CLOCK_REF) {
Clk = XPm_AllocBytes(sizeof(XPm_ClockNode));
if (Clk==NULL) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
} else if (Subclass == (u32)XPM_NODETYPE_CLOCK_OUT) {
if (TopologyType >= MAX_TOPOLOGY || TopologyType < TOPOLOGY_GENERIC_MUX_DIV) {
Status = XST_INVALID_PARAM;
goto done;
}
Clk = XPm_AllocBytes(sizeof(XPm_OutClockNode));
if (Clk == NULL) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
} else {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XPmClock_Init(Clk, Id, ControlReg, TopologyType,
NumCustomNodes, NumParents, PowerDomainId,
ClkFlags);
if (XST_SUCCESS == Status) {
Status = XPmClock_SetById(Id, Clk);
} else {
/* TODO: Free allocated memory */
}
done:
return Status;
}
XStatus XPmClock_AddClkName(u32 Id, char *Name)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk = XPmClock_GetById(Id);
if (NULL == Clk) {
Status = XST_INVALID_PARAM;
goto done;
}
(void)XPlmi_MemCpy(Clk->Name, Name, MAX_NAME_BYTES);
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_AddSubNode(u32 Id, u32 Type, u32 ControlReg, u8 Param1, u8 Param2, u32 Flags)
{
XStatus Status = XST_FAILURE;
u32 i = 0U;
XPm_OutClockNode *OutClkPtr = (XPm_OutClockNode *)XPmClock_GetById(Id);
struct XPm_ClkTopologyNode *SubNodes;
if (OutClkPtr == NULL || OutClkPtr->Topology.Id != TOPOLOGY_CUSTOM) {
Status = XST_INVALID_PARAM;
goto done;
}
if (Type <= (u32)TYPE_INVALID || Type >= (u32)TYPE_MAX || Type == (u32)TYPE_PLL) {
Status = XST_INVALID_PARAM;
goto done;
}
SubNodes = *OutClkPtr->Topology.Nodes;
for (i=0; i<OutClkPtr->Topology.NumNodes; i++) {
if (SubNodes[i].Type == 0U) {
SubNodes[i].Type = (u8)Type;
SubNodes[i].Reg = ControlReg;
if (Type == (u32)TYPE_FIXEDFACTOR) {
SubNodes[i].Param1.Mult = Param1;
SubNodes[i].Param2.Div = Param2;
} else {
SubNodes[i].Param1.Shift = Param1;
SubNodes[i].Param2.Width = Param2;
}
SubNodes[i].Clkflags = (u16)(Flags & 0xFFFFU);
SubNodes[i].Typeflags = (u16)((Flags >> 16) & 0xFFFFU);
SubNodes[i].Reg = ControlReg;
break;
}
}
if (i == OutClkPtr->Topology.NumNodes) {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_AddParent(u32 Id, u32 *Parents, u8 NumParents)
{
XStatus Status = XST_FAILURE;
u32 Idx = 0;
u32 LastParentIdx = 0;
u16 ParentIdx = 0;
XPm_ClockNode *ParentClk = NULL;
XPm_OutClockNode *ClkPtr = (XPm_OutClockNode *)XPmClock_GetById(Id);
if (ClkPtr == NULL || NumParents > MAX_MUX_PARENTS || NumParents == 0U) {
Status = XST_INVALID_PARAM;
goto done;
}
for (Idx = 0; Idx < NumParents; Idx++) {
u32 ParentId = Parents[Idx];
/*
* FIXME: For GEM0_RX and GEM1_RX parents are EMIO and MIO
* clocks and their IDs are 0 which is not valid clock ID.
* Consider 0 as a valid parent ID for now.
* Remove this condition once EMIO and MIO clocks are added
* as valid clocks.
*/
if (0U == ParentId) {
continue;
}
if (!ISOUTCLK(ParentId) && !ISREFCLK(ParentId) &&
!ISPLL(ParentId) && (u32)CLK_DUMMY_PARENT != ParentId) {
Status = XST_INVALID_PARAM;
goto done;
}
}
/*
* For clocks which has more than 5 parents add parent command will call
* multiple times. Because from single command only 5 parents can add.
* So find parent index for second command from there remaining parents
* should be stored.
*/
while ((0U != ClkPtr->Topology.MuxSources[LastParentIdx]) &&
(MAX_MUX_PARENTS != LastParentIdx)) {
LastParentIdx++;
}
/* Parents count should not be greater than clock's numbed of parents */
if ((LastParentIdx + NumParents > ClkPtr->ClkNode.NumParents) ||
(MAX_MUX_PARENTS == LastParentIdx)) {
Status = XST_INVALID_PARAM;
goto done;
}
/* For clocks involving mux */
for (Idx = 0; Idx < NumParents; Idx++) {
if ((u32)CLK_DUMMY_PARENT == Parents[Idx]) {
ParentIdx = (u16)CLK_DUMMY_PARENT;
} else {
ParentIdx = (u16)(NODEINDEX(Parents[Idx]));
}
ClkPtr->Topology.MuxSources[LastParentIdx++] = ParentIdx;
}
/* Assign default parent */
if (ClkPtr->ClkNode.NumParents > 1U) {
/*
* For mux clocks, parents are initialized when clock
* requested. So assign invalid clock parent by default.
*/
ClkPtr->ClkNode.ParentIdx = (u16)CLOCK_PARENT_INVALID;
} else {
ParentClk = XPmClock_GetByIdx(ClkPtr->Topology.MuxSources[0]);
if (NULL != ParentClk) {
ClkPtr->ClkNode.ParentIdx = (u16)(NODEINDEX(ParentClk->Node.Id));
}
}
Status = XST_SUCCESS;
done:
return Status;
}
XPm_ClockNode* XPmClock_GetById(u32 ClockId)
{
u32 ClockIndex = NODEINDEX(ClockId);
u32 NodeType = NODETYPE(ClockId);
XPm_ClockNode *Clk = NULL;
u32 MaskId = ((u32)XPM_NODETYPE_CLOCK_SUBNODE == NodeType) ?
(~((u32)NODE_TYPE_MASK)) : ((~(u32)0x0));
if (((u32)XPM_NODECLASS_CLOCK != NODECLASS(ClockId)) ||
(MaxClkNodes <= ClockIndex)) {
goto done;
}
Clk = ClkNodeList[ClockIndex];
if (NULL == Clk) {
goto done;
}
/* Check that Clock's ID is same as given ID or not.
* NOTE:
* For ADD_CLOCK_SUBNODE command, we add the subnodes to the existing
* clock nodes in the database. These "existing" clock nodes are stored
* with a different node type than the 'XPM_NODETYPE_CLOCK_SUBNODE'
* which is passed into this function for retrieval of such nodes.
* So, we need to mask the type for this special case while validating.
* This is what MaskId does. For all other cases, it is all ones.
*/
if ((ClockId & MaskId) != (Clk->Node.Id & MaskId)) {
Clk = NULL;
}
done:
return Clk;
}
XPm_ClockNode* XPmClock_GetByIdx(u32 ClockIdx)
{
XPm_ClockNode *Clk = NULL;
if(MaxClkNodes <= ClockIdx) {
goto done;
}
Clk = ClkNodeList[ClockIdx];
done:
return Clk;
}
XStatus XPmClock_SetById(u32 ClockId, XPm_ClockNode *Clk)
{
XStatus Status = XST_INVALID_PARAM;
u32 NodeIndex = NODEINDEX(ClockId);
/*
* We assume that the Node ID class, subclass and type has _already_
* been validated before, so only check bounds here against index
*/
if ((NULL != Clk) && (MaxClkNodes > NodeIndex)) {
ClkNodeList[NodeIndex] = Clk;
PmNumClocks++;
Status = XST_SUCCESS;
}
return Status;
}
static struct XPm_ClkTopologyNode* XPmClock_GetTopologyNode(XPm_OutClockNode *Clk, u32 Type)
{
struct XPm_ClkTopologyNode *SubNodes;
uint8_t NumNodes;
u32 i;
if (Clk == NULL) {
return NULL;
}
SubNodes = *Clk->Topology.Nodes;
NumNodes = Clk->Topology.NumNodes;
for (i = 0; i < NumNodes; i++) {
if (SubNodes[i].Type == Type) {
/* For custom topology, nodes have correct control address but
* for other topologies, there's no separate node memory to fill
* register each time */
if (Clk->Topology.Id != TOPOLOGY_CUSTOM) {
SubNodes[i].Reg = Clk->ClkNode.Node.BaseAddress;
}
return &SubNodes[i];
}
}
return NULL;
}
static void XPmClock_InitParent(XPm_OutClockNode *Clk)
{
u32 ParentIdx = 0;
struct XPm_ClkTopologyNode *Ptr;
XPm_ClockNode *ParentClk = NULL;
int Status;
Ptr = XPmClock_GetTopologyNode(Clk, (u32)TYPE_MUX);
if (NULL != Ptr) {
Status = XPmClock_GetClockData(Clk, (u32)TYPE_MUX, &ParentIdx);
if (XST_SUCCESS != Status) {
PmWarn("Error %d in GetClockData of 0x%x\r\n", Status, Clk->ClkNode.Node.Id);
}
/* Update new parent id */
ParentClk = XPmClock_GetByIdx(Clk->Topology.MuxSources[ParentIdx]);
if (NULL != ParentClk) {
Clk->ClkNode.ParentIdx = (u16)(NODEINDEX(ParentClk->Node.Id));
}
}
return;
}
static void XPmClock_RequestInt(XPm_ClockNode *Clk)
{
int Status;
if (Clk != NULL) {
if (0U == Clk->UseCount) {
/* Initialize the parent if not done before */
if (CLOCK_PARENT_INVALID == Clk->ParentIdx) {
XPmClock_InitParent((XPm_OutClockNode *)Clk);
}
/* Request the parent first */
XPm_ClockNode *ParentClk = XPmClock_GetByIdx(Clk->ParentIdx);
if (ISOUTCLK(ParentClk->Node.Id)) {
XPmClock_RequestInt(ParentClk);
} else if (ISPLL(ParentClk->Node.Id)) {
Status = XPmClockPll_Request(ParentClk->Node.Id);
if (XST_SUCCESS != Status) {
PmWarn("Error %d in request PLL of 0x%x\r\n", Status, ParentClk->Node.Id);
}
} else {
/* Required due to MISRA */
PmDbg("Invalid clock type of clock 0x%x\r\n", ParentClk->Node.Id);
}
/* Mark it as requested. If clock has a gate, state will be changed to On when enabled */
Clk->Node.State |= XPM_CLK_STATE_REQUESTED;
/* Enable clock if gated */
(void)XPmClock_SetGate((XPm_OutClockNode *)Clk, 1);
}
/* Increment the use count of clock */
Clk->UseCount++;
}
return;
}
XStatus XPmClock_Request(XPm_ClockHandle *ClkHandle)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk;
u32 ClkId;
if (NULL == ClkHandle) {
Status = XST_SUCCESS;
goto done;
}
while (NULL != ClkHandle) {
Clk = ClkHandle->Clock;
ClkId = Clk->Node.Id;
if (ISOUTCLK(ClkId)) {
XPmClock_RequestInt(Clk);
} else if (ISPLL(ClkId)) {
Status = XPmClockPll_Request(ClkId);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
/* Required due to MISRA */
PmDbg("Invalid clock type of clock 0x%x\r\n", ClkId);
}
ClkHandle = ClkHandle->NextClock;
}
Status = XST_SUCCESS;
done:
return Status;
}
static void XPmClock_ReleaseInt(XPm_ClockNode *Clk)
{
int Status;
if (Clk != NULL) {
/* Decrease the use count of clock */
Clk->UseCount--;
if (0U == Clk->UseCount) {
/* Clear the requested bit of clock */
Clk->Node.State &= (u8)(~(XPM_CLK_STATE_REQUESTED));
/* Disable clock */
(void)XPmClock_SetGate((XPm_OutClockNode *)Clk, 0);
/* Release the clock parent */
XPm_ClockNode *ParentClk = XPmClock_GetByIdx(Clk->ParentIdx);
if (ISOUTCLK(ParentClk->Node.Id)) {
XPmClock_ReleaseInt(ParentClk);
} else if (ISPLL(ParentClk->Node.Id)) {
Status = XPmClockPll_Release(ParentClk->Node.Id);
if (XST_SUCCESS != Status) {
PmWarn("Error %d in release PLL of 0x%x\r\n", Status, ParentClk->Node.Id);
}
} else {
/* Required due to MISRA */
PmDbg("Invalid clock type of clock 0x%x\r\n", ParentClk->Node.Id);
}
}
}
return;
}
XStatus XPmClock_Release(XPm_ClockHandle *ClkHandle)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk;
u32 ClkId;
if (NULL == ClkHandle) {
Status = XST_SUCCESS;
goto done;
}
while (NULL != ClkHandle) {
Clk = ClkHandle->Clock;
ClkId = Clk->Node.Id;
if (ISOUTCLK(ClkId)) {
XPmClock_ReleaseInt(Clk);
} else if (ISPLL(ClkId)) {
Status = XPmClockPll_Release(ClkId);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
/* Required due to MISRA */
}
ClkHandle = ClkHandle->NextClock;
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_SetGate(XPm_OutClockNode *Clk, u32 Enable)
{
XStatus Status = XST_FAILURE;
struct XPm_ClkTopologyNode *Ptr;
Ptr = XPmClock_GetTopologyNode(Clk, (u32)TYPE_GATE);
if (Ptr == NULL) {
Status = XST_INVALID_PARAM;
goto done;
}
if (Enable > 1U) {
Status = XST_INVALID_PARAM;
goto done;
}
XPm_RMW32(Ptr->Reg, BITNMASK(Ptr->Param1.Shift,Ptr->Param2.Width), Enable << Ptr->Param1.Shift);
if (1U == Enable) {
Clk->ClkNode.Node.State |= XPM_CLK_STATE_ON;
} else {
Clk->ClkNode.Node.State &= (u8)(~(XPM_CLK_STATE_ON));
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_SetParent(XPm_OutClockNode *Clk, u32 ParentIdx)
{
XStatus Status = XST_FAILURE;
struct XPm_ClkTopologyNode *Ptr;
XPm_ClockNode *ParentClk = NULL;
XPm_ClockNode *OldParentClk = NULL;
Ptr = XPmClock_GetTopologyNode(Clk, (u32)TYPE_MUX);
if (Ptr == NULL) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((ParentIdx > BITMASK(Ptr->Param2.Width)) ||
(ParentIdx > (((u32)Clk->ClkNode.NumParents) - 1U))) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Request new parent */
ParentClk = XPmClock_GetByIdx(Clk->Topology.MuxSources[ParentIdx]);
if (ISOUTCLK(ParentClk->Node.Id)) {
XPmClock_RequestInt(ParentClk);
} else if (ISPLL(ParentClk->Node.Id)) {
Status = XPmClockPll_Request(ParentClk->Node.Id);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
/* Required due to MISRA */
PmDbg("Invalid clock type of clock 0x%x\r\n", ParentClk->Node.Id);
}
XPm_RMW32(Ptr->Reg, BITNMASK(Ptr->Param1.Shift,Ptr->Param2.Width), ParentIdx << Ptr->Param1.Shift);
/* Release old parent */
OldParentClk = XPmClock_GetByIdx(Clk->ClkNode.ParentIdx);
if (ISOUTCLK(OldParentClk->Node.Id)) {
XPmClock_ReleaseInt(OldParentClk);
} else if (ISPLL(OldParentClk->Node.Id)) {
Status = XPmClockPll_Release(OldParentClk->Node.Id);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
/* Required due to MISRA */
PmDbg("Invalid clock type of clock 0x%x\r\n", OldParentClk->Node.Id);
}
/* Update new parent idx */
Clk->ClkNode.ParentIdx = (u16)(NODEINDEX(ParentClk->Node.Id));
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_SetDivider(XPm_OutClockNode *Clk, u32 Divider)
{
XStatus Status = XST_FAILURE;
struct XPm_ClkTopologyNode *Ptr;
u32 Divider1;
Ptr = XPmClock_GetTopologyNode(Clk, (u32)TYPE_DIV1);
if (Ptr == NULL) {
Status = XST_INVALID_PARAM;
goto done;
}
Divider1 = Divider & 0xFFFFU;
if (Divider1 > BITMASK(Ptr->Param2.Width)) {
Status = XST_INVALID_PARAM;
goto done;
}
XPm_RMW32(Ptr->Reg, BITNMASK(Ptr->Param1.Shift,Ptr->Param2.Width), Divider1 << Ptr->Param1.Shift);
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_GetClockData(XPm_OutClockNode *Clk, u32 Nodetype, u32 *Value)
{
XStatus Status = XST_FAILURE;
u32 Mask;
struct XPm_ClkTopologyNode *Ptr;
XPm_Power *PowerDomain = Clk->ClkNode.PwrDomain;
Ptr = XPmClock_GetTopologyNode(Clk, Nodetype);
if (Ptr == NULL) {
Status = XPM_INVALID_CLK_SUBNODETYPE;
goto done;
}
if ((u8)XPM_POWER_STATE_ON != PowerDomain->Node.State) {
Status = XST_NO_ACCESS;
goto done;
}
Mask = BITNMASK(Ptr->Param1.Shift, Ptr->Param2.Width);
*Value = (XPm_Read32(Ptr->Reg) & Mask) >> Ptr->Param1.Shift;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_QueryName(u32 ClockId, u32 *Resp)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk;
(void)memset(Resp, 0, CLK_QUERY_NAME_LEN);
Clk = XPmClock_GetById(ClockId);
if (NULL == Clk) {
goto done;
}
(void)memcpy((char *)Resp, &Clk->Name[0], CLK_QUERY_NAME_LEN);
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_QueryTopology(u32 ClockId, u32 Index, u32 *Resp)
{
XStatus Status = XST_FAILURE;
u32 i;
struct XPm_ClkTopologyNode *PtrNodes;
XPm_OutClockNode *Clk;
Clk = (XPm_OutClockNode *)XPmClock_GetById(ClockId);
(void)memset(Resp, 0, CLK_TOPOLOGY_PAYLOAD_LEN);
if (ISOUTCLK(ClockId)) {
PtrNodes = *Clk->Topology.Nodes;
/* Skip parent till index */
if (Index >= Clk->Topology.NumNodes) {
Status = XST_SUCCESS;
goto done;
}
for (i = 0; i < 3U; i++) {
if ((Index + i) == Clk->Topology.NumNodes) {
break;
}
Resp[i] = PtrNodes[Index + i].Type;
Resp[i] |= ((u32)(PtrNodes[Index + i].Clkflags) << CLK_CLKFLAGS_SHIFT);
Resp[i] |= ((u32)(PtrNodes[Index + i].Typeflags) << CLK_TYPEFLAGS_SHIFT);
}
} else if (ISPLL(ClockId)) {
if (Index != 0U) {
Status = XST_SUCCESS;
goto done;
}
Resp[0] = (u32)TYPE_PLL;
Resp[0] |= CLK_SET_RATE_NO_REPARENT << CLK_CLKFLAGS_SHIFT;
Resp[0] |= ((u32)NA_TYPE_FLAGS) << CLK_TYPEFLAGS_SHIFT;
} else {
Status = XST_FAILURE;
goto done;
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_QueryFFParams(u32 ClockId, u32 *Resp)
{
XStatus Status = XST_FAILURE;
struct XPm_ClkTopologyNode *Ptr;
XPm_OutClockNode *Clk;
Clk = (XPm_OutClockNode *)XPmClock_GetById(ClockId);
if (!ISOUTCLK(ClockId)) {
goto done;
}
Ptr = XPmClock_GetTopologyNode(Clk, (u32)TYPE_FIXEDFACTOR);
if (Ptr == NULL) {
Status = XST_INVALID_PARAM;
goto done;
}
Resp[0] = Ptr->Param1.Mult;
Resp[1] = Ptr->Param2.Div;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_QueryMuxSources(u32 ClockId, u32 Index, u32 *Resp)
{
XStatus Status = XST_FAILURE;
XPm_OutClockNode *Clk;
u32 i;
Clk = (XPm_OutClockNode *)XPmClock_GetById(ClockId);
if (!ISOUTCLK(ClockId)) {
goto done;
}
(void)memset(Resp, 0, CLK_PARENTS_PAYLOAD_LEN);
/* Skip parent till index */
for (i = 0; i < 3U; i++) {
if (Clk->ClkNode.NumParents == (Index + i)) {
Resp[i] = 0xFFFFFFFFU;
break;
}
Resp[i] = Clk->Topology.MuxSources[Index + i];
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_QueryAttributes(u32 ClockIndex, u32 *Resp)
{
XStatus Status = XST_FAILURE;
unsigned int Attr = 0;
u32 InitEnable = 0;
u32 ClockId = 0;
XPm_ClockNode *Clk;
if (ClockIndex >= MaxClkNodes) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Clock valid bit. All clocks present in clock database is valid. */
if (NULL != ClkNodeList[ClockIndex]) {
Attr = 1U;
Clk = ClkNodeList[ClockIndex];
ClockId = Clk->Node.Id;
} else {
Attr = 0U;
}
//if (PLATFORM_VERSION_SILICON != Platform) {
/*
* Mark CPM related clock as invalid because their registers
* are not accessible from PS DDR SPP.
* TODO: This code under platform version check needs to be
* removed when CPM registers are accessible.
*/
if (ClockIndex == (u32)XPM_NODEIDX_CLK_CPM_LSBUS_REF ||
ClockIndex == (u32)XPM_NODEIDX_CLK_CPM_PLL ||
ClockIndex == (u32)XPM_NODEIDX_CLK_CPM_PRESRC ||
ClockIndex == (u32)XPM_NODEIDX_CLK_CPM_POSTCLK ||
ClockIndex == (u32)XPM_NODEIDX_CLK_CPM_PLL_OUT ||
ClockIndex == (u32)XPM_NODEIDX_CLK_CPM_CORE_REF ||
ClockIndex == (u32)XPM_NODEIDX_CLK_CPM_DBG_REF ||
ClockIndex == (u32)XPM_NODEIDX_CLK_CPM_AUX0_REF ||
ClockIndex == (u32)XPM_NODEIDX_CLK_CPM_AUX1_REF ||
ClockIndex == (u32)XPM_NODEIDX_CLK_CPM_TOPSW_REF) {
//PmInfo("Marking Clock: %d as Invalid\r\n", ClockIndex);
Attr = 0;
}
//}
/* If clock needs to be enabled during init */
/* TBD - Decide InitEnable value */
Attr |= InitEnable << CLK_INIT_ENABLE_SHIFT;
/* Clock type (Output/External) */
if (NODESUBCLASS(ClockId) == (u32)XPM_NODESUBCL_CLOCK_REF) {
Attr |= 1U << CLK_TYPE_SHIFT;
}
/* Clock node type PLL, OUT or REF*/
Attr |= NODETYPE(ClockId) << CLK_NODETYPE_SHIFT;
/* Clock node subclass PLL, OUT or REF */
Attr |= NODESUBCLASS(ClockId) << CLK_NODESUBCLASS_SHIFT;
/* Node class, i.e Clock */
Attr |= NODECLASS(ClockId) << CLK_NODECLASS_SHIFT;
*Resp = Attr;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_GetNumClocks(u32 *Resp)
{
*Resp = (u32)XPM_NODEIDX_CLK_MAX;
return XST_SUCCESS;
}
XStatus XPmClock_CheckPermissions(u32 SubsystemIdx, u32 ClockId)
{
XStatus Status = XST_FAILURE;
XPm_ClockNode *Clk;
XPm_ClockHandle *DevHandle;
u32 PermissionMask = 0U;
Clk = XPmClock_GetById(ClockId);
if (NULL == Clk) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Check for read-only flag */
if (0U != (CLK_FLAG_READ_ONLY & Clk->Flags)) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
/* Check for power domain of clock */
if ((NULL != Clk->PwrDomain) &&
((u8)XPM_POWER_STATE_ON != Clk->PwrDomain->Node.State)) {
Status = XST_FAILURE;
goto done;
}
if (ISPLL(ClockId)) {
/* Do not allow permission by default when PLL is shared */
Status = XPM_PM_NO_ACCESS;
goto done;
}
DevHandle = Clk->ClkHandles;
while (NULL != DevHandle) {
/* Get permission mask which indicates permission for each subsystem */
Status = XPmDevice_GetPermissions(DevHandle->Device,
&PermissionMask);
if (XST_SUCCESS != Status) {
goto done;
}
DevHandle = DevHandle->NextDevice;
}
/* Check permission for given subsystem */
if (0U == (PermissionMask & ((u32)1U << SubsystemIdx))) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
/* Access is not allowed if resource is shared (multiple subsystems) */
if (__builtin_popcount(PermissionMask) > 1) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmClock_GetMaxDivisor(u32 ClockId, u32 DivType, u32 *Resp)
{
XStatus Status = XST_FAILURE;
struct XPm_ClkTopologyNode *Ptr;
XPm_OutClockNode *Clk;
Clk = (XPm_OutClockNode *)XPmClock_GetById(ClockId);
if (NULL == Clk) {
Status = XST_INVALID_PARAM;
goto done;
}
Ptr = XPmClock_GetTopologyNode(Clk, DivType);
if (NULL == Ptr) {
Status = XST_INVALID_PARAM;
goto done;
}
*Resp = BITMASK(Ptr->Param2.Width);
Status = XST_SUCCESS;
done:
return Status;
}
int XPmClock_SetRate(XPm_ClockNode *Clk, const u32 ClkRate)
{
Clk->ClkRate = ClkRate;
return XST_SUCCESS;
}
int XPmClock_GetRate(XPm_ClockNode *Clk, u32 *ClkRate)
{
*ClkRate = Clk->ClkRate;
return XST_SUCCESS;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pmu_global.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _PMU_GLOBAL_H_
#define _PMU_GLOBAL_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* PMU_GLOBAL Base Address
*/
#define PMU_GLOBAL_BASEADDR ((u32)0XFFD80000U)
/**
* Register: PMU_GLOBAL_GLOBAL_CNTRL
*/
#define PMU_GLOBAL_GLOBAL_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000000U) )
#define PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_SHIFT 16
#define PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_WIDTH 1
#define PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_GLOBAL_CNTRL_WRITE_QOS_SHIFT 12
#define PMU_GLOBAL_GLOBAL_CNTRL_WRITE_QOS_WIDTH 4
#define PMU_GLOBAL_GLOBAL_CNTRL_WRITE_QOS_MASK ((u32)0X0000F000U)
#define PMU_GLOBAL_GLOBAL_CNTRL_READ_QOS_SHIFT 8
#define PMU_GLOBAL_GLOBAL_CNTRL_READ_QOS_WIDTH 4
#define PMU_GLOBAL_GLOBAL_CNTRL_READ_QOS_MASK ((u32)0X00000F00U)
#define PMU_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_SHIFT 4
#define PMU_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_WIDTH 1
#define PMU_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_GLOBAL_CNTRL_COHERENT_SHIFT 2
#define PMU_GLOBAL_GLOBAL_CNTRL_COHERENT_WIDTH 1
#define PMU_GLOBAL_GLOBAL_CNTRL_COHERENT_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_SHIFT 1
#define PMU_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_WIDTH 1
#define PMU_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_GLOBAL_CNTRL_DONT_SLEEP_SHIFT 0
#define PMU_GLOBAL_GLOBAL_CNTRL_DONT_SLEEP_WIDTH 1
#define PMU_GLOBAL_GLOBAL_CNTRL_DONT_SLEEP_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_PS_CNTRL
*/
#define PMU_GLOBAL_PS_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000004U) )
#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_STATUS_SHIFT 16
#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_STATUS_WIDTH 1
#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_STATUS_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_PS_CNTRL_PROG_ENABLE_SHIFT 1
#define PMU_GLOBAL_PS_CNTRL_PROG_ENABLE_WIDTH 1
#define PMU_GLOBAL_PS_CNTRL_PROG_ENABLE_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_SHIFT 0
#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_WIDTH 1
#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_APU_PWR_STATUS_INIT
*/
#define PMU_GLOBAL_APU_PWR_STATUS_INIT ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000008U) )
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU3_SHIFT 3
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU3_WIDTH 1
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU2_SHIFT 2
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU2_WIDTH 1
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU1_SHIFT 1
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU1_WIDTH 1
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU0_SHIFT 0
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU0_WIDTH 1
#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_MEM_CNTRL
*/
#define PMU_GLOBAL_MEM_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000000CU) )
#define PMU_GLOBAL_MEM_CNTRL_ROM1_KEN_SHIFT 23
#define PMU_GLOBAL_MEM_CNTRL_ROM1_KEN_WIDTH 1
#define PMU_GLOBAL_MEM_CNTRL_ROM1_KEN_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_MEM_CNTRL_ROM1_EMA_SHIFT 20
#define PMU_GLOBAL_MEM_CNTRL_ROM1_EMA_WIDTH 3
#define PMU_GLOBAL_MEM_CNTRL_ROM1_EMA_MASK ((u32)0X00700000U)
#define PMU_GLOBAL_MEM_CNTRL_ROM0_KEN_SHIFT 19
#define PMU_GLOBAL_MEM_CNTRL_ROM0_KEN_WIDTH 1
#define PMU_GLOBAL_MEM_CNTRL_ROM0_KEN_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_MEM_CNTRL_ROM0_EMA_SHIFT 16
#define PMU_GLOBAL_MEM_CNTRL_ROM0_EMA_WIDTH 3
#define PMU_GLOBAL_MEM_CNTRL_ROM0_EMA_MASK ((u32)0X00070000U)
#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAS_SHIFT 11
#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAS_WIDTH 1
#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAS_MASK ((u32)0X00000800U)
#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAW_SHIFT 9
#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAW_WIDTH 2
#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAW_MASK ((u32)0X00000600U)
#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMA_SHIFT 6
#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMA_WIDTH 3
#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMA_MASK ((u32)0X000001C0U)
#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAS_SHIFT 5
#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAS_WIDTH 1
#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAS_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAW_SHIFT 3
#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAW_WIDTH 2
#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAW_MASK ((u32)0X00000018U)
#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMA_SHIFT 0
#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMA_WIDTH 3
#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMA_MASK ((u32)0X00000007U)
/**
* Register: PMU_GLOBAL_ADDR_ERROR_STATUS
*/
#define PMU_GLOBAL_ADDR_ERROR_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000010U) )
#define PMU_GLOBAL_ADDR_ERROR_STATUS_STATUS_SHIFT 0
#define PMU_GLOBAL_ADDR_ERROR_STATUS_STATUS_WIDTH 1
#define PMU_GLOBAL_ADDR_ERROR_STATUS_STATUS_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ADDR_ERROR_INT_MASK
*/
#define PMU_GLOBAL_ADDR_ERROR_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000014U) )
#define PMU_GLOBAL_ADDR_ERROR_INT_MASK_MASK_SHIFT 0
#define PMU_GLOBAL_ADDR_ERROR_INT_MASK_MASK_WIDTH 1
#define PMU_GLOBAL_ADDR_ERROR_INT_MASK_MASK_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ADDR_ERROR_INT_EN
*/
#define PMU_GLOBAL_ADDR_ERROR_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000018U) )
#define PMU_GLOBAL_ADDR_ERROR_INT_EN_ENABLE_SHIFT 0
#define PMU_GLOBAL_ADDR_ERROR_INT_EN_ENABLE_WIDTH 1
#define PMU_GLOBAL_ADDR_ERROR_INT_EN_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ADDR_ERROR_INT_DIS
*/
#define PMU_GLOBAL_ADDR_ERROR_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000001CU) )
#define PMU_GLOBAL_ADDR_ERROR_INT_DIS_DISABLE_SHIFT 0
#define PMU_GLOBAL_ADDR_ERROR_INT_DIS_DISABLE_WIDTH 1
#define PMU_GLOBAL_ADDR_ERROR_INT_DIS_DISABLE_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE0
*/
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE0 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000030U) )
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE0_REG_SHIFT 0
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE0_REG_WIDTH 32
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE0_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE1
*/
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000034U) )
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE1_REG_SHIFT 0
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE1_REG_WIDTH 32
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE1_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE2
*/
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000038U) )
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE2_REG_SHIFT 0
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE2_REG_WIDTH 32
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE2_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE3
*/
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE3 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000003CU) )
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE3_REG_SHIFT 0
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE3_REG_WIDTH 32
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE3_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE4
*/
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE4 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000040U) )
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE4_REG_SHIFT 0
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE4_REG_WIDTH 32
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE4_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE5
*/
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE5 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000044U) )
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE5_REG_SHIFT 0
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE5_REG_WIDTH 32
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE5_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE6
*/
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE6 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000048U) )
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE6_REG_SHIFT 0
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE6_REG_WIDTH 32
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE6_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE7
*/
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE7 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000004CU) )
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE7_REG_SHIFT 0
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE7_REG_WIDTH 32
#define PMU_GLOBAL_GLOBAL_GEN_STORAGE7_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE0
*/
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE0 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000050U) )
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE0_REG_SHIFT 0
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE0_REG_WIDTH 32
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE0_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE1
*/
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000054U) )
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE1_REG_SHIFT 0
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE1_REG_WIDTH 32
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE1_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE2
*/
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000058U) )
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE2_REG_SHIFT 0
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE2_REG_WIDTH 32
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE2_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE3
*/
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE3 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000005CU) )
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE3_REG_SHIFT 0
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE3_REG_WIDTH 32
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE3_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4
*/
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000060U) )
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4_REG_SHIFT 0
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4_REG_WIDTH 32
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5
*/
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000064U) )
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5_REG_SHIFT 0
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5_REG_WIDTH 32
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE6
*/
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE6 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000068U) )
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE6_REG_SHIFT 0
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE6_REG_WIDTH 32
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE6_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7
*/
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000006CU) )
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7_REG_SHIFT 0
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7_REG_WIDTH 32
#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_DDR_CNTRL
*/
#define PMU_GLOBAL_DDR_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000070U) )
#define PMU_GLOBAL_DDR_CNTRL_RET_SHIFT 0
#define PMU_GLOBAL_DDR_CNTRL_RET_WIDTH 1
#define PMU_GLOBAL_DDR_CNTRL_RET_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_PWR_STATE
*/
#define PMU_GLOBAL_PWR_STATE ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000100U) )
#define PMU_GLOBAL_PWR_STATE_PL_SHIFT 23
#define PMU_GLOBAL_PWR_STATE_PL_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_PWR_STATE_FP_SHIFT 22
#define PMU_GLOBAL_PWR_STATE_FP_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_PWR_STATE_USB1_SHIFT 21
#define PMU_GLOBAL_PWR_STATE_USB1_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_PWR_STATE_USB0_SHIFT 20
#define PMU_GLOBAL_PWR_STATE_USB0_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_PWR_STATE_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_PWR_STATE_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_PWR_STATE_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_PWR_STATE_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_PWR_STATE_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_PWR_STATE_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_PWR_STATE_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_PWR_STATE_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_PWR_STATE_TCM1B_SHIFT 15
#define PMU_GLOBAL_PWR_STATE_TCM1B_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_PWR_STATE_TCM1A_SHIFT 14
#define PMU_GLOBAL_PWR_STATE_TCM1A_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_PWR_STATE_TCM0B_SHIFT 13
#define PMU_GLOBAL_PWR_STATE_TCM0B_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_PWR_STATE_TCM0A_SHIFT 12
#define PMU_GLOBAL_PWR_STATE_TCM0A_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_PWR_STATE_R5_1_SHIFT 11
#define PMU_GLOBAL_PWR_STATE_R5_1_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_R5_1_MASK ((u32)0X00000800U)
#define PMU_GLOBAL_PWR_STATE_R5_0_SHIFT 10
#define PMU_GLOBAL_PWR_STATE_R5_0_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_R5_0_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_PWR_STATE_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_PWR_STATE_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_PWR_STATE_PP1_SHIFT 5
#define PMU_GLOBAL_PWR_STATE_PP1_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_PWR_STATE_PP0_SHIFT 4
#define PMU_GLOBAL_PWR_STATE_PP0_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_PWR_STATE_ACPU3_SHIFT 3
#define PMU_GLOBAL_PWR_STATE_ACPU3_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_PWR_STATE_ACPU2_SHIFT 2
#define PMU_GLOBAL_PWR_STATE_ACPU2_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_PWR_STATE_ACPU1_SHIFT 1
#define PMU_GLOBAL_PWR_STATE_ACPU1_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_PWR_STATE_ACPU0_SHIFT 0
#define PMU_GLOBAL_PWR_STATE_ACPU0_WIDTH 1
#define PMU_GLOBAL_PWR_STATE_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_AUX_PWR_STATE
*/
#define PMU_GLOBAL_AUX_PWR_STATE ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000104U) )
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU3_EMULATION_SHIFT 31
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU3_EMULATION_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU3_EMULATION_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU2_EMULATION_SHIFT 30
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU2_EMULATION_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU2_EMULATION_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU1_EMULATION_SHIFT 29
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU1_EMULATION_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU1_EMULATION_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU0_EMULATION_SHIFT 28
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU0_EMULATION_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_ACPU0_EMULATION_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_AUX_PWR_STATE_RPU_EMULATION_SHIFT 27
#define PMU_GLOBAL_AUX_PWR_STATE_RPU_EMULATION_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_RPU_EMULATION_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_AUX_PWR_STATE_TCM1B_SHIFT 15
#define PMU_GLOBAL_AUX_PWR_STATE_TCM1B_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_AUX_PWR_STATE_TCM1A_SHIFT 14
#define PMU_GLOBAL_AUX_PWR_STATE_TCM1A_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_AUX_PWR_STATE_TCM0B_SHIFT 13
#define PMU_GLOBAL_AUX_PWR_STATE_TCM0B_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_AUX_PWR_STATE_TCM0A_SHIFT 12
#define PMU_GLOBAL_AUX_PWR_STATE_TCM0A_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_AUX_PWR_STATE_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_AUX_PWR_STATE_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_AUX_PWR_STATE_L2_BANK0_MASK ((u32)0X00000080U)
/**
* Register: PMU_GLOBAL_RAM_RET_CNTRL
*/
#define PMU_GLOBAL_RAM_RET_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000108U) )
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1B_SHIFT 15
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1B_WIDTH 1
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1A_SHIFT 14
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1A_WIDTH 1
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0B_SHIFT 13
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0B_WIDTH 1
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0A_SHIFT 12
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0A_WIDTH 1
#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_RAM_RET_CNTRL_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_RAM_RET_CNTRL_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_RAM_RET_CNTRL_L2_BANK0_MASK ((u32)0X00000080U)
/**
* Register: PMU_GLOBAL_PWR_SUPPLY_STATUS
*/
#define PMU_GLOBAL_PWR_SUPPLY_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000010CU) )
#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSAUX_SHIFT 2
#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSAUX_WIDTH 1
#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSAUX_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_INT_SHIFT 1
#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_INT_WIDTH 1
#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_INT_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSINTFP_SHIFT 0
#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSINTFP_WIDTH 1
#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSINTFP_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_PWRUP_STATUS
*/
#define PMU_GLOBAL_REQ_PWRUP_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000110U) )
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_FP_SHIFT 22
#define PMU_GLOBAL_REQ_PWRUP_STATUS_FP_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB1_SHIFT 21
#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB0_SHIFT 20
#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1B_SHIFT 15
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1A_SHIFT 14
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0B_SHIFT 13
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0A_SHIFT 12
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_PWRUP_STATUS_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_REQ_PWRUP_STATUS_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP1_SHIFT 5
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP0_SHIFT 4
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_PWRUP_INT_MASK
*/
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000114U) )
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PL_SHIFT 23
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PL_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_FP_SHIFT 22
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_FP_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB1_SHIFT 21
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB0_SHIFT 20
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1B_SHIFT 15
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1A_SHIFT 14
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0B_SHIFT 13
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0A_SHIFT 12
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP1_SHIFT 5
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP0_SHIFT 4
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_PWRUP_INT_EN
*/
#define PMU_GLOBAL_REQ_PWRUP_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000118U) )
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_FP_SHIFT 22
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_FP_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB1_SHIFT 21
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB0_SHIFT 20
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1B_SHIFT 15
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1A_SHIFT 14
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0B_SHIFT 13
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0A_SHIFT 12
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP1_SHIFT 5
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP0_SHIFT 4
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_PWRUP_INT_DIS
*/
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000011CU) )
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PL_SHIFT 23
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PL_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_FP_SHIFT 22
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_FP_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB1_SHIFT 21
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB0_SHIFT 20
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1B_SHIFT 15
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1A_SHIFT 14
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0B_SHIFT 13
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0A_SHIFT 12
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP1_SHIFT 5
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP0_SHIFT 4
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_PWRUP_TRIG
*/
#define PMU_GLOBAL_REQ_PWRUP_TRIG ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000120U) )
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_FP_SHIFT 22
#define PMU_GLOBAL_REQ_PWRUP_TRIG_FP_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB1_SHIFT 21
#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB0_SHIFT 20
#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1B_SHIFT 15
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1A_SHIFT 14
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0B_SHIFT 13
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0A_SHIFT 12
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_PWRUP_TRIG_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_REQ_PWRUP_TRIG_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP1_SHIFT 5
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP0_SHIFT 4
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_PWRDWN_STATUS
*/
#define PMU_GLOBAL_REQ_PWRDWN_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000210U) )
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PL_SHIFT 23
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PL_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_FP_SHIFT 22
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_FP_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB1_SHIFT 21
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB0_SHIFT 20
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1B_SHIFT 15
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1A_SHIFT 14
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0B_SHIFT 13
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0A_SHIFT 12
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP1_SHIFT 5
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP0_SHIFT 4
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_PWRDWN_INT_MASK
*/
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000214U) )
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PL_SHIFT 23
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PL_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_FP_SHIFT 22
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_FP_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB1_SHIFT 21
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB0_SHIFT 20
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1B_SHIFT 15
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1A_SHIFT 14
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0B_SHIFT 13
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0A_SHIFT 12
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP1_SHIFT 5
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP0_SHIFT 4
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_PWRDWN_INT_EN
*/
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000218U) )
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PL_SHIFT 23
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PL_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_FP_SHIFT 22
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_FP_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB1_SHIFT 21
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB0_SHIFT 20
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1B_SHIFT 15
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1A_SHIFT 14
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0B_SHIFT 13
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0A_SHIFT 12
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP1_SHIFT 5
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP0_SHIFT 4
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_PWRDWN_INT_DIS
*/
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000021CU) )
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PL_SHIFT 23
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PL_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_FP_SHIFT 22
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_FP_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB1_SHIFT 21
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB0_SHIFT 20
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1B_SHIFT 15
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1A_SHIFT 14
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0B_SHIFT 13
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0A_SHIFT 12
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP1_SHIFT 5
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP0_SHIFT 4
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_PWRDWN_TRIG
*/
#define PMU_GLOBAL_REQ_PWRDWN_TRIG ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000220U) )
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PL_SHIFT 23
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PL_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PL_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_FP_SHIFT 22
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_FP_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_FP_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB1_SHIFT 21
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB0_SHIFT 20
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK3_SHIFT 19
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK3_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK2_SHIFT 18
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK2_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK1_SHIFT 17
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK0_SHIFT 16
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1B_SHIFT 15
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1B_MASK ((u32)0X00008000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1A_SHIFT 14
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1A_MASK ((u32)0X00004000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0B_SHIFT 13
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0B_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0B_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0A_SHIFT 12
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0A_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0A_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_L2_BANK0_SHIFT 7
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_L2_BANK0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_L2_BANK0_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP1_SHIFT 5
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP1_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP0_SHIFT 4
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP0_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_ISO_STATUS
*/
#define PMU_GLOBAL_REQ_ISO_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000310U) )
#define PMU_GLOBAL_REQ_ISO_STATUS_FP_LOCKED_SHIFT 4
#define PMU_GLOBAL_REQ_ISO_STATUS_FP_LOCKED_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_STATUS_FP_LOCKED_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_ISO_STATUS_PL_NONPCAP_SHIFT 2
#define PMU_GLOBAL_REQ_ISO_STATUS_PL_NONPCAP_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_STATUS_PL_NONPCAP_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_ISO_STATUS_PL_SHIFT 1
#define PMU_GLOBAL_REQ_ISO_STATUS_PL_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_STATUS_PL_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_ISO_STATUS_FP_SHIFT 0
#define PMU_GLOBAL_REQ_ISO_STATUS_FP_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_STATUS_FP_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_ISO_INT_MASK
*/
#define PMU_GLOBAL_REQ_ISO_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000314U) )
#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_LOCKED_SHIFT 4
#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_LOCKED_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_LOCKED_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_NONPCAP_SHIFT 2
#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_NONPCAP_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_NONPCAP_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_SHIFT 1
#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_SHIFT 0
#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_ISO_INT_EN
*/
#define PMU_GLOBAL_REQ_ISO_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000318U) )
#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_LOCKED_SHIFT 4
#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_LOCKED_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_LOCKED_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_NONPCAP_SHIFT 2
#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_NONPCAP_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_NONPCAP_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_SHIFT 1
#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_SHIFT 0
#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_ISO_INT_DIS
*/
#define PMU_GLOBAL_REQ_ISO_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000031CU) )
#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_LOCKED_SHIFT 4
#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_LOCKED_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_LOCKED_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_NONPCAP_SHIFT 2
#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_NONPCAP_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_NONPCAP_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_SHIFT 1
#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_SHIFT 0
#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_ISO_TRIG
*/
#define PMU_GLOBAL_REQ_ISO_TRIG ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000320U) )
#define PMU_GLOBAL_REQ_ISO_TRIG_FP_LOCKED_SHIFT 4
#define PMU_GLOBAL_REQ_ISO_TRIG_FP_LOCKED_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_TRIG_FP_LOCKED_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_ISO_TRIG_PL_NONPCAP_SHIFT 2
#define PMU_GLOBAL_REQ_ISO_TRIG_PL_NONPCAP_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_TRIG_PL_NONPCAP_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_ISO_TRIG_PL_SHIFT 1
#define PMU_GLOBAL_REQ_ISO_TRIG_PL_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_TRIG_PL_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_ISO_TRIG_FP_SHIFT 0
#define PMU_GLOBAL_REQ_ISO_TRIG_FP_WIDTH 1
#define PMU_GLOBAL_REQ_ISO_TRIG_FP_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_SWRST_STATUS
*/
#define PMU_GLOBAL_REQ_SWRST_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000410U) )
#define PMU_GLOBAL_REQ_SWRST_STATUS_PL_SHIFT 31
#define PMU_GLOBAL_REQ_SWRST_STATUS_PL_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_PL_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_FP_SHIFT 30
#define PMU_GLOBAL_REQ_SWRST_STATUS_FP_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_FP_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_LP_SHIFT 29
#define PMU_GLOBAL_REQ_SWRST_STATUS_LP_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_LP_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_PS_ONLY_SHIFT 28
#define PMU_GLOBAL_REQ_SWRST_STATUS_PS_ONLY_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_PS_ONLY_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_IOU_SHIFT 27
#define PMU_GLOBAL_REQ_SWRST_STATUS_IOU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_IOU_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_USB1_SHIFT 25
#define PMU_GLOBAL_REQ_SWRST_STATUS_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_USB1_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_USB0_SHIFT 24
#define PMU_GLOBAL_REQ_SWRST_STATUS_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_USB0_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM3_SHIFT 23
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM3_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM3_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM2_SHIFT 22
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM2_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM2_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM1_SHIFT 21
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM0_SHIFT 20
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_RPU_SHIFT 18
#define PMU_GLOBAL_REQ_SWRST_STATUS_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_RPU_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_1_SHIFT 17
#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_0_SHIFT 16
#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_DISPLAY_PORT_SHIFT 12
#define PMU_GLOBAL_REQ_SWRST_STATUS_DISPLAY_PORT_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_DISPLAY_PORT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_SATA_SHIFT 10
#define PMU_GLOBAL_REQ_SWRST_STATUS_SATA_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_SATA_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_PCIE_SHIFT 9
#define PMU_GLOBAL_REQ_SWRST_STATUS_PCIE_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_PCIE_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_GPU_SHIFT 8
#define PMU_GLOBAL_REQ_SWRST_STATUS_GPU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_GPU_MASK ((u32)0X00000100U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_PP1_SHIFT 7
#define PMU_GLOBAL_REQ_SWRST_STATUS_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_PP0_SHIFT 6
#define PMU_GLOBAL_REQ_SWRST_STATUS_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_APU_SHIFT 4
#define PMU_GLOBAL_REQ_SWRST_STATUS_APU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_APU_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_SWRST_INT_MASK
*/
#define PMU_GLOBAL_REQ_SWRST_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000414U) )
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PL_SHIFT 31
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PL_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PL_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_FP_SHIFT 30
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_FP_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_FP_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LP_SHIFT 29
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LP_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LP_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PS_ONLY_SHIFT 28
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PS_ONLY_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PS_ONLY_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_IOU_SHIFT 27
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_IOU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_IOU_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB1_SHIFT 25
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB1_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB0_SHIFT 24
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB0_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM3_SHIFT 23
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM3_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM3_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM2_SHIFT 22
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM2_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM2_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM1_SHIFT 21
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM0_SHIFT 20
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LS_R5_SHIFT 18
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LS_R5_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LS_R5_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_1_SHIFT 17
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_0_SHIFT 16
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_DISPLAY_PORT_SHIFT 12
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_DISPLAY_PORT_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_DISPLAY_PORT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_SATA_SHIFT 10
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_SATA_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_SATA_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PCIE_SHIFT 9
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PCIE_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PCIE_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GPU_SHIFT 8
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GPU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GPU_MASK ((u32)0X00000100U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP1_SHIFT 7
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP0_SHIFT 6
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_APU_SHIFT 4
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_APU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_APU_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_SWRST_INT_EN
*/
#define PMU_GLOBAL_REQ_SWRST_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000418U) )
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PL_SHIFT 31
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PL_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PL_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_FP_SHIFT 30
#define PMU_GLOBAL_REQ_SWRST_INT_EN_FP_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_FP_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_LP_SHIFT 29
#define PMU_GLOBAL_REQ_SWRST_INT_EN_LP_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_LP_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PS_ONLY_SHIFT 28
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PS_ONLY_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PS_ONLY_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_IOU_SHIFT 27
#define PMU_GLOBAL_REQ_SWRST_INT_EN_IOU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_IOU_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB1_SHIFT 25
#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB1_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB0_SHIFT 24
#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB0_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM3_SHIFT 23
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM3_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM3_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM2_SHIFT 22
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM2_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM2_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM1_SHIFT 21
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM0_SHIFT 20
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_LS_R5_SHIFT 18
#define PMU_GLOBAL_REQ_SWRST_INT_EN_LS_R5_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_LS_R5_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_1_SHIFT 17
#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_0_SHIFT 16
#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_DISPLAY_PORT_SHIFT 12
#define PMU_GLOBAL_REQ_SWRST_INT_EN_DISPLAY_PORT_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_DISPLAY_PORT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_SATA_SHIFT 10
#define PMU_GLOBAL_REQ_SWRST_INT_EN_SATA_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_SATA_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PCIE_SHIFT 9
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PCIE_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PCIE_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GPU_SHIFT 8
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GPU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_GPU_MASK ((u32)0X00000100U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP1_SHIFT 7
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP0_SHIFT 6
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_APU_SHIFT 4
#define PMU_GLOBAL_REQ_SWRST_INT_EN_APU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_APU_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_SWRST_INT_DIS
*/
#define PMU_GLOBAL_REQ_SWRST_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000041CU) )
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PL_SHIFT 31
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PL_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PL_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_FP_SHIFT 30
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_FP_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_FP_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LP_SHIFT 29
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LP_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LP_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PS_ONLY_SHIFT 28
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PS_ONLY_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PS_ONLY_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_IOU_SHIFT 27
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_IOU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_IOU_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB1_SHIFT 25
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB1_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB0_SHIFT 24
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB0_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM3_SHIFT 23
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM3_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM3_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM2_SHIFT 22
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM2_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM2_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM1_SHIFT 21
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM0_SHIFT 20
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LS_R5_SHIFT 18
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LS_R5_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LS_R5_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_1_SHIFT 17
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_0_SHIFT 16
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_DISPLAY_PORT_SHIFT 12
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_DISPLAY_PORT_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_DISPLAY_PORT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_SATA_SHIFT 10
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_SATA_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_SATA_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PCIE_SHIFT 9
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PCIE_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PCIE_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GPU_SHIFT 8
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GPU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GPU_MASK ((u32)0X00000100U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP1_SHIFT 7
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP0_SHIFT 6
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_APU_SHIFT 4
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_APU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_APU_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_SWRST_TRIG
*/
#define PMU_GLOBAL_REQ_SWRST_TRIG ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000420U) )
#define PMU_GLOBAL_REQ_SWRST_TRIG_PL_SHIFT 31
#define PMU_GLOBAL_REQ_SWRST_TRIG_PL_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_PL_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_FP_SHIFT 30
#define PMU_GLOBAL_REQ_SWRST_TRIG_FP_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_FP_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_LP_SHIFT 29
#define PMU_GLOBAL_REQ_SWRST_TRIG_LP_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_LP_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_PS_ONLY_SHIFT 28
#define PMU_GLOBAL_REQ_SWRST_TRIG_PS_ONLY_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_PS_ONLY_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_IOU_SHIFT 27
#define PMU_GLOBAL_REQ_SWRST_TRIG_IOU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_IOU_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_USB1_SHIFT 25
#define PMU_GLOBAL_REQ_SWRST_TRIG_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_USB1_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_USB0_SHIFT 24
#define PMU_GLOBAL_REQ_SWRST_TRIG_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_USB0_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM3_SHIFT 23
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM3_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM3_MASK ((u32)0X00800000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM2_SHIFT 22
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM2_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM2_MASK ((u32)0X00400000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM1_SHIFT 21
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM1_MASK ((u32)0X00200000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM0_SHIFT 20
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM0_MASK ((u32)0X00100000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_LS_R5_SHIFT 18
#define PMU_GLOBAL_REQ_SWRST_TRIG_LS_R5_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_LS_R5_MASK ((u32)0X00040000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_1_SHIFT 17
#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_1_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_0_SHIFT 16
#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_0_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_DISPLAY_PORT_SHIFT 12
#define PMU_GLOBAL_REQ_SWRST_TRIG_DISPLAY_PORT_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_DISPLAY_PORT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_SATA_SHIFT 10
#define PMU_GLOBAL_REQ_SWRST_TRIG_SATA_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_SATA_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_PCIE_SHIFT 9
#define PMU_GLOBAL_REQ_SWRST_TRIG_PCIE_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_PCIE_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_GPU_SHIFT 8
#define PMU_GLOBAL_REQ_SWRST_TRIG_GPU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_GPU_MASK ((u32)0X00000100U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_PP1_SHIFT 7
#define PMU_GLOBAL_REQ_SWRST_TRIG_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_PP0_SHIFT 6
#define PMU_GLOBAL_REQ_SWRST_TRIG_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_APU_SHIFT 4
#define PMU_GLOBAL_REQ_SWRST_TRIG_APU_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_APU_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_LOGCLR_STATUS
*/
#define PMU_GLOBAL_REQ_LOGCLR_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000510U) )
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_FP_SHIFT 17
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_FP_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_FP_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_LP_SHIFT 16
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_LP_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_LP_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB1_SHIFT 13
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB1_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB0_SHIFT 12
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB0_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP1_SHIFT 7
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP0_SHIFT 6
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_LOGCLR_INT_MASK
*/
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000514U) )
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_FP_SHIFT 17
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_FP_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_FP_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_LP_SHIFT 16
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_LP_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_LP_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB1_SHIFT 13
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB1_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB0_SHIFT 12
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB0_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP1_SHIFT 7
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP0_SHIFT 6
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_LOGCLR_INT_EN
*/
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000518U) )
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_FP_SHIFT 17
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_FP_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_FP_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_LP_SHIFT 16
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_LP_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_LP_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB1_SHIFT 13
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB1_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB0_SHIFT 12
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB0_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP1_SHIFT 7
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP0_SHIFT 6
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_LOGCLR_INT_DIS
*/
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000051CU) )
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_FP_SHIFT 17
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_FP_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_FP_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_LP_SHIFT 16
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_LP_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_LP_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB1_SHIFT 13
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB1_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB0_SHIFT 12
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB0_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP1_SHIFT 7
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP0_SHIFT 6
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_REQ_LOGCLR_TRIG
*/
#define PMU_GLOBAL_REQ_LOGCLR_TRIG ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000520U) )
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_FP_SHIFT 17
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_FP_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_FP_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_LP_SHIFT 16
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_LP_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_LP_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB1_SHIFT 13
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB1_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB0_SHIFT 12
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB0_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_RPU_SHIFT 10
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_RPU_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP1_SHIFT 7
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP0_SHIFT 6
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU3_SHIFT 3
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU3_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU2_SHIFT 2
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU2_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU1_SHIFT 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU1_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU0_SHIFT 0
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU0_WIDTH 1
#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_LOGCLR_STATUS
*/
#define PMU_GLOBAL_LOGCLR_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000524U) )
#define PMU_GLOBAL_LOGCLR_STATUS_FP_SHIFT 17
#define PMU_GLOBAL_LOGCLR_STATUS_FP_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_FP_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_LOGCLR_STATUS_LP_SHIFT 16
#define PMU_GLOBAL_LOGCLR_STATUS_LP_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_LP_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_LOGCLR_STATUS_USB1_SHIFT 13
#define PMU_GLOBAL_LOGCLR_STATUS_USB1_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_USB1_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_LOGCLR_STATUS_USB0_SHIFT 12
#define PMU_GLOBAL_LOGCLR_STATUS_USB0_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_USB0_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_LOGCLR_STATUS_RPU_SHIFT 10
#define PMU_GLOBAL_LOGCLR_STATUS_RPU_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_RPU_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_LOGCLR_STATUS_PP1_SHIFT 7
#define PMU_GLOBAL_LOGCLR_STATUS_PP1_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_PP1_MASK ((u32)0X00000080U)
#define PMU_GLOBAL_LOGCLR_STATUS_PP0_SHIFT 6
#define PMU_GLOBAL_LOGCLR_STATUS_PP0_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_PP0_MASK ((u32)0X00000040U)
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU3_SHIFT 3
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU3_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU3_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU2_SHIFT 2
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU2_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU2_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU1_SHIFT 1
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU1_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU1_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU0_SHIFT 0
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU0_WIDTH 1
#define PMU_GLOBAL_LOGCLR_STATUS_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_CSU_BR_ERROR
*/
#define PMU_GLOBAL_CSU_BR_ERROR ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000528U) )
#define PMU_GLOBAL_CSU_BR_ERROR_BR_ERROR_SHIFT 31
#define PMU_GLOBAL_CSU_BR_ERROR_BR_ERROR_WIDTH 1
#define PMU_GLOBAL_CSU_BR_ERROR_BR_ERROR_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_CSU_BR_ERROR_ERR_TYPE_SHIFT 0
#define PMU_GLOBAL_CSU_BR_ERROR_ERR_TYPE_WIDTH 16
#define PMU_GLOBAL_CSU_BR_ERROR_ERR_TYPE_MASK ((u32)0X0000FFFFU)
/**
* Register: PMU_GLOBAL_MB_FAULT_STATUS
*/
#define PMU_GLOBAL_MB_FAULT_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000052CU) )
#define PMU_GLOBAL_MB_FAULT_STATUS_R_FFAIL_SHIFT 24
#define PMU_GLOBAL_MB_FAULT_STATUS_R_FFAIL_WIDTH 8
#define PMU_GLOBAL_MB_FAULT_STATUS_R_FFAIL_MASK ((u32)0XFF000000U)
#define PMU_GLOBAL_MB_FAULT_STATUS_R_SLEEP_RST_SHIFT 19
#define PMU_GLOBAL_MB_FAULT_STATUS_R_SLEEP_RST_WIDTH 1
#define PMU_GLOBAL_MB_FAULT_STATUS_R_SLEEP_RST_MASK ((u32)0X00080000U)
#define PMU_GLOBAL_MB_FAULT_STATUS_R_LSFAIL_SHIFT 16
#define PMU_GLOBAL_MB_FAULT_STATUS_R_LSFAIL_WIDTH 3
#define PMU_GLOBAL_MB_FAULT_STATUS_R_LSFAIL_MASK ((u32)0X00070000U)
#define PMU_GLOBAL_MB_FAULT_STATUS_N_FFAIL_SHIFT 8
#define PMU_GLOBAL_MB_FAULT_STATUS_N_FFAIL_WIDTH 8
#define PMU_GLOBAL_MB_FAULT_STATUS_N_FFAIL_MASK ((u32)0X0000FF00U)
#define PMU_GLOBAL_MB_FAULT_STATUS_N_SLEEP_RST_SHIFT 3
#define PMU_GLOBAL_MB_FAULT_STATUS_N_SLEEP_RST_WIDTH 1
#define PMU_GLOBAL_MB_FAULT_STATUS_N_SLEEP_RST_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_MB_FAULT_STATUS_N_LSFAIL_SHIFT 0
#define PMU_GLOBAL_MB_FAULT_STATUS_N_LSFAIL_WIDTH 3
#define PMU_GLOBAL_MB_FAULT_STATUS_N_LSFAIL_MASK ((u32)0X00000007U)
/**
* Register: PMU_GLOBAL_ERROR_STATUS_1
*/
#define PMU_GLOBAL_ERROR_STATUS_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000530U) )
#define PMU_GLOBAL_ERROR_STATUS_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_STATUS_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_STATUS_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_STATUS_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_STATUS_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_STATUS_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_STATUS_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_STATUS_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_STATUS_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_STATUS_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_STATUS_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_STATUS_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_STATUS_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_STATUS_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_STATUS_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_STATUS_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_STATUS_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_STATUS_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_STATUS_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_STATUS_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_STATUS_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_STATUS_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_STATUS_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_STATUS_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_STATUS_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_STATUS_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_STATUS_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_STATUS_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_STATUS_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_STATUS_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_STATUS_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_STATUS_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_STATUS_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_STATUS_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_STATUS_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_STATUS_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_STATUS_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_STATUS_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_STATUS_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_INT_MASK_1
*/
#define PMU_GLOBAL_ERROR_INT_MASK_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000534U) )
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_INT_MASK_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_INT_MASK_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_INT_MASK_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_INT_MASK_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_INT_MASK_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_INT_MASK_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_INT_MASK_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_INT_MASK_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_INT_EN_1
*/
#define PMU_GLOBAL_ERROR_INT_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000538U) )
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_INT_EN_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_INT_EN_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_INT_EN_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_INT_EN_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_INT_EN_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_INT_EN_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_INT_EN_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_INT_EN_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_INT_EN_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_INT_EN_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_INT_EN_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_INT_EN_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_INT_EN_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_INT_EN_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_INT_DIS_1
*/
#define PMU_GLOBAL_ERROR_INT_DIS_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000053CU) )
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_INT_DIS_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_INT_DIS_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_INT_DIS_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_INT_DIS_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_INT_DIS_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_INT_DIS_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_INT_DIS_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_INT_DIS_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_STATUS_2
*/
#define PMU_GLOBAL_ERROR_STATUS_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000540U) )
#define PMU_GLOBAL_ERROR_STATUS_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_STATUS_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_STATUS_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_STATUS_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_STATUS_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_STATUS_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_STATUS_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_STATUS_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_STATUS_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_STATUS_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_STATUS_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_INT_MASK_2
*/
#define PMU_GLOBAL_ERROR_INT_MASK_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000544U) )
#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_INT_MASK_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_INT_MASK_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_INT_MASK_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_INT_MASK_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_INT_MASK_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_INT_MASK_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_INT_MASK_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_INT_MASK_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_INT_MASK_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_INT_EN_2
*/
#define PMU_GLOBAL_ERROR_INT_EN_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000548U) )
#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_INT_EN_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_INT_EN_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_INT_EN_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_INT_EN_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_INT_EN_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_INT_EN_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_INT_EN_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_INT_EN_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_INT_EN_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_INT_DIS_2
*/
#define PMU_GLOBAL_ERROR_INT_DIS_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000054CU) )
#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_INT_DIS_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_INT_DIS_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_INT_DIS_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_INT_DIS_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_INT_DIS_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_INT_DIS_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_INT_DIS_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_INT_DIS_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_INT_DIS_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_POR_MASK_1
*/
#define PMU_GLOBAL_ERROR_POR_MASK_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000550U) )
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_POR_MASK_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_POR_MASK_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_POR_MASK_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_POR_MASK_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_POR_MASK_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_POR_MASK_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_POR_MASK_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_POR_MASK_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_POR_EN_1
*/
#define PMU_GLOBAL_ERROR_POR_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000554U) )
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_POR_EN_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_POR_EN_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_POR_EN_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_POR_EN_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_POR_EN_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_POR_EN_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_POR_EN_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_POR_EN_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_POR_EN_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_POR_EN_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_POR_EN_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_POR_EN_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_POR_EN_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_POR_EN_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_POR_DIS_1
*/
#define PMU_GLOBAL_ERROR_POR_DIS_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000558U) )
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_POR_DIS_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_POR_DIS_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_POR_DIS_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_POR_DIS_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_POR_DIS_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_POR_DIS_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_POR_DIS_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_POR_DIS_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_POR_MASK_2
*/
#define PMU_GLOBAL_ERROR_POR_MASK_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000055CU) )
#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_POR_MASK_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_POR_MASK_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_POR_MASK_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_POR_MASK_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_POR_MASK_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_POR_MASK_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_POR_MASK_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_POR_MASK_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_POR_MASK_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_POR_EN_2
*/
#define PMU_GLOBAL_ERROR_POR_EN_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000560U) )
#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_POR_EN_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_POR_EN_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_POR_EN_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_POR_EN_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_POR_EN_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_POR_EN_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_POR_EN_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_POR_EN_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_POR_EN_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_POR_DIS_2
*/
#define PMU_GLOBAL_ERROR_POR_DIS_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000564U) )
#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_POR_DIS_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_POR_DIS_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_POR_DIS_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_POR_DIS_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_POR_DIS_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_POR_DIS_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_POR_DIS_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_POR_DIS_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_POR_DIS_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_SRST_MASK_1
*/
#define PMU_GLOBAL_ERROR_SRST_MASK_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000568U) )
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_SRST_MASK_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_SRST_MASK_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_SRST_MASK_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_SRST_MASK_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_SRST_MASK_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_SRST_MASK_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_SRST_MASK_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_SRST_MASK_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_SRST_EN_1
*/
#define PMU_GLOBAL_ERROR_SRST_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000056CU) )
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_SRST_EN_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_SRST_EN_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_SRST_EN_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_SRST_EN_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_SRST_EN_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_SRST_EN_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_SRST_EN_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_SRST_EN_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_SRST_DIS_1
*/
#define PMU_GLOBAL_ERROR_SRST_DIS_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000570U) )
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_SRST_DIS_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_SRST_DIS_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_SRST_DIS_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_SRST_DIS_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_SRST_DIS_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_SRST_DIS_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_SRST_DIS_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_SRST_DIS_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_SRST_MASK_2
*/
#define PMU_GLOBAL_ERROR_SRST_MASK_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000574U) )
#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_SRST_MASK_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_SRST_MASK_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_SRST_MASK_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_SRST_MASK_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_SRST_EN_2
*/
#define PMU_GLOBAL_ERROR_SRST_EN_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000578U) )
#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_SRST_EN_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_SRST_EN_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_SRST_EN_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_SRST_EN_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_SRST_EN_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_SRST_EN_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_SRST_EN_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_SRST_EN_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_SRST_EN_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_SRST_DIS_2
*/
#define PMU_GLOBAL_ERROR_SRST_DIS_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000057CU) )
#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_SRST_DIS_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_SRST_DIS_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_SRST_DIS_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_SRST_DIS_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_SIG_MASK_1
*/
#define PMU_GLOBAL_ERROR_SIG_MASK_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000580U) )
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_SIG_MASK_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_SIG_MASK_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_SIG_MASK_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_SIG_MASK_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_SIG_MASK_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_SIG_MASK_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_SIG_MASK_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_SIG_MASK_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_SIG_EN_1
*/
#define PMU_GLOBAL_ERROR_SIG_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000584U) )
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_SIG_EN_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_SIG_EN_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_SIG_EN_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_SIG_EN_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_SIG_EN_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_SIG_EN_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_SIG_EN_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_SIG_EN_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_SIG_DIS_1
*/
#define PMU_GLOBAL_ERROR_SIG_DIS_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000588U) )
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_SIG_DIS_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_SIG_DIS_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_SIG_DIS_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_SIG_DIS_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_SIG_DIS_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_SIG_DIS_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_SIG_DIS_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_SIG_DIS_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_SIG_MASK_2
*/
#define PMU_GLOBAL_ERROR_SIG_MASK_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000058CU) )
#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_SIG_MASK_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_SIG_MASK_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_SIG_MASK_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_SIG_MASK_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_SIG_EN_2
*/
#define PMU_GLOBAL_ERROR_SIG_EN_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000590U) )
#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_SIG_EN_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_SIG_EN_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_SIG_EN_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_SIG_EN_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_SIG_EN_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_SIG_EN_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_SIG_EN_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_SIG_EN_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_SIG_EN_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_ERROR_SIG_DIS_2
*/
#define PMU_GLOBAL_ERROR_SIG_DIS_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000594U) )
#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_SIG_DIS_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_SIG_DIS_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_SIG_DIS_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_SIG_DIS_2_TO_MASK ((u32)0X00000003U)
#define PMU_GLOBAL_ERROR_SIG_2_IOPLL_SHIFT 8
#define PMU_GLOBAL_ERROR_SIG_2_RPLL_SHIFT 9
#define PMU_GLOBAL_ERROR_SIG_2_APLL_SHIFT 10
#define PMU_GLOBAL_ERROR_SIG_2_DPLL_SHIFT 11
#define PMU_GLOBAL_ERROR_SIG_2_VPLL_SHIFT 12
/**
* Register: PMU_GLOBAL_ERROR_EN_1
*/
#define PMU_GLOBAL_ERROR_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X000005A0U) )
#define PMU_GLOBAL_ERROR_EN_1_AUX3_SHIFT 31
#define PMU_GLOBAL_ERROR_EN_1_AUX3_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_AUX3_MASK ((u32)0X80000000U)
#define PMU_GLOBAL_ERROR_EN_1_AUX2_SHIFT 30
#define PMU_GLOBAL_ERROR_EN_1_AUX2_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_AUX2_MASK ((u32)0X40000000U)
#define PMU_GLOBAL_ERROR_EN_1_AUX1_SHIFT 29
#define PMU_GLOBAL_ERROR_EN_1_AUX1_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_AUX1_MASK ((u32)0X20000000U)
#define PMU_GLOBAL_ERROR_EN_1_AUX0_SHIFT 28
#define PMU_GLOBAL_ERROR_EN_1_AUX0_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_AUX0_MASK ((u32)0X10000000U)
#define PMU_GLOBAL_ERROR_EN_1_CSU_SWDT_SHIFT 27
#define PMU_GLOBAL_ERROR_EN_1_CSU_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_CSU_SWDT_MASK ((u32)0X08000000U)
#define PMU_GLOBAL_ERROR_EN_1_CLK_MON_SHIFT 26
#define PMU_GLOBAL_ERROR_EN_1_CLK_MON_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_CLK_MON_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_EN_1_XMPU_SHIFT 24
#define PMU_GLOBAL_ERROR_EN_1_XMPU_WIDTH 2
#define PMU_GLOBAL_ERROR_EN_1_XMPU_MASK ((u32)0X03000000U)
#define PMU_GLOBAL_ERROR_EN_1_PWR_SUPPLY_SHIFT 16
#define PMU_GLOBAL_ERROR_EN_1_PWR_SUPPLY_WIDTH 8
#define PMU_GLOBAL_ERROR_EN_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U)
#define PMU_GLOBAL_ERROR_EN_1_FPD_SWDT_SHIFT 13
#define PMU_GLOBAL_ERROR_EN_1_FPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_FPD_SWDT_MASK ((u32)0X00002000U)
#define PMU_GLOBAL_ERROR_EN_1_LPD_SWDT_SHIFT 12
#define PMU_GLOBAL_ERROR_EN_1_LPD_SWDT_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_LPD_SWDT_MASK ((u32)0X00001000U)
#define PMU_GLOBAL_ERROR_EN_1_RPU_CCF_SHIFT 9
#define PMU_GLOBAL_ERROR_EN_1_RPU_CCF_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_RPU_CCF_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_ERROR_EN_1_RPU_LS_SHIFT 6
#define PMU_GLOBAL_ERROR_EN_1_RPU_LS_WIDTH 2
#define PMU_GLOBAL_ERROR_EN_1_RPU_LS_MASK ((u32)0X000000C0U)
#define PMU_GLOBAL_ERROR_EN_1_FPD_TEMP_SHIFT 5
#define PMU_GLOBAL_ERROR_EN_1_FPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_FPD_TEMP_MASK ((u32)0X00000020U)
#define PMU_GLOBAL_ERROR_EN_1_LPD_TEMP_SHIFT 4
#define PMU_GLOBAL_ERROR_EN_1_LPD_TEMP_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_LPD_TEMP_MASK ((u32)0X00000010U)
#define PMU_GLOBAL_ERROR_EN_1_RPU1_SHIFT 3
#define PMU_GLOBAL_ERROR_EN_1_RPU1_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_RPU1_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_ERROR_EN_1_RPU0_SHIFT 2
#define PMU_GLOBAL_ERROR_EN_1_RPU0_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_RPU0_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_ERROR_EN_1_OCM_ECC_SHIFT 1
#define PMU_GLOBAL_ERROR_EN_1_OCM_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_OCM_ECC_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ERROR_EN_1_DDR_ECC_SHIFT 0
#define PMU_GLOBAL_ERROR_EN_1_DDR_ECC_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_1_DDR_ECC_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ERROR_EN_2
*/
#define PMU_GLOBAL_ERROR_EN_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X000005A4U) )
#define PMU_GLOBAL_ERROR_EN_2_CSU_ROM_SHIFT 26
#define PMU_GLOBAL_ERROR_EN_2_CSU_ROM_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_2_CSU_ROM_MASK ((u32)0X04000000U)
#define PMU_GLOBAL_ERROR_EN_2_PMU_PB_SHIFT 25
#define PMU_GLOBAL_ERROR_EN_2_PMU_PB_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_2_PMU_PB_MASK ((u32)0X02000000U)
#define PMU_GLOBAL_ERROR_EN_2_PMU_SERVICE_SHIFT 24
#define PMU_GLOBAL_ERROR_EN_2_PMU_SERVICE_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_2_PMU_SERVICE_MASK ((u32)0X01000000U)
#define PMU_GLOBAL_ERROR_EN_2_PMU_FW_SHIFT 18
#define PMU_GLOBAL_ERROR_EN_2_PMU_FW_WIDTH 4
#define PMU_GLOBAL_ERROR_EN_2_PMU_FW_MASK ((u32)0X003C0000U)
#define PMU_GLOBAL_ERROR_EN_2_PMU_UC_SHIFT 17
#define PMU_GLOBAL_ERROR_EN_2_PMU_UC_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_2_PMU_UC_MASK ((u32)0X00020000U)
#define PMU_GLOBAL_ERROR_EN_2_CSU_SHIFT 16
#define PMU_GLOBAL_ERROR_EN_2_CSU_WIDTH 1
#define PMU_GLOBAL_ERROR_EN_2_CSU_MASK ((u32)0X00010000U)
#define PMU_GLOBAL_ERROR_EN_2_PLL_LOCK_SHIFT 8
#define PMU_GLOBAL_ERROR_EN_2_PLL_LOCK_WIDTH 5
#define PMU_GLOBAL_ERROR_EN_2_PLL_LOCK_MASK ((u32)0X00001F00U)
#define PMU_GLOBAL_ERROR_EN_2_PL_SHIFT 2
#define PMU_GLOBAL_ERROR_EN_2_PL_WIDTH 4
#define PMU_GLOBAL_ERROR_EN_2_PL_MASK ((u32)0X0000003CU)
#define PMU_GLOBAL_ERROR_EN_2_TO_SHIFT 0
#define PMU_GLOBAL_ERROR_EN_2_TO_WIDTH 2
#define PMU_GLOBAL_ERROR_EN_2_TO_MASK ((u32)0X00000003U)
/**
* Register: PMU_GLOBAL_AIB_CNTRL
*/
#define PMU_GLOBAL_AIB_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000600U) )
#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FS_SHIFT 3
#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FS_WIDTH 1
#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FS_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FM_SHIFT 2
#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FM_WIDTH 1
#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FM_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FS_SHIFT 1
#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FS_WIDTH 1
#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FS_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FM_SHIFT 0
#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FM_WIDTH 1
#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FM_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_AIB_STATUS
*/
#define PMU_GLOBAL_AIB_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000604U) )
#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FS_SHIFT 3
#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FS_WIDTH 1
#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FS_MASK ((u32)0X00000008U)
#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FM_SHIFT 2
#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FM_WIDTH 1
#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FM_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FS_SHIFT 1
#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FS_WIDTH 1
#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FS_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FM_SHIFT 0
#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FM_WIDTH 1
#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FM_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_GLOBAL_RESET
*/
#define PMU_GLOBAL_GLOBAL_RESET ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000608U) )
#define PMU_GLOBAL_GLOBAL_RESET_PS_ONLY_RST_SHIFT 10
#define PMU_GLOBAL_GLOBAL_RESET_PS_ONLY_RST_WIDTH 1
#define PMU_GLOBAL_GLOBAL_RESET_PS_ONLY_RST_MASK ((u32)0X00000400U)
#define PMU_GLOBAL_GLOBAL_RESET_FPD_RST_SHIFT 9
#define PMU_GLOBAL_GLOBAL_RESET_FPD_RST_WIDTH 1
#define PMU_GLOBAL_GLOBAL_RESET_FPD_RST_MASK ((u32)0X00000200U)
#define PMU_GLOBAL_GLOBAL_RESET_RPU_LS_RST_SHIFT 8
#define PMU_GLOBAL_GLOBAL_RESET_RPU_LS_RST_WIDTH 1
#define PMU_GLOBAL_GLOBAL_RESET_RPU_LS_RST_MASK ((u32)0X00000100U)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_STATUS
*/
#define PMU_GLOBAL_ROM_VALIDATION_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000610U) )
#define PMU_GLOBAL_ROM_VALIDATION_STATUS_PASS_SHIFT 1
#define PMU_GLOBAL_ROM_VALIDATION_STATUS_PASS_WIDTH 1
#define PMU_GLOBAL_ROM_VALIDATION_STATUS_PASS_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_ROM_VALIDATION_STATUS_DONE_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_STATUS_DONE_WIDTH 1
#define PMU_GLOBAL_ROM_VALIDATION_STATUS_DONE_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_0
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_0 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000614U) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_0_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_0_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_0_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_1
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000618U) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_1_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_1_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_1_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_2
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000061CU) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_2_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_2_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_2_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_3
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_3 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000620U) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_3_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_3_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_3_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_4
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_4 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000624U) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_4_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_4_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_4_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_5
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_5 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000628U) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_5_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_5_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_5_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_6
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_6 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000062CU) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_6_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_6_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_6_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_7
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_7 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000630U) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_7_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_7_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_7_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_8
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_8 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000634U) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_8_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_8_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_8_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_9
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_9 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000638U) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_9_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_9_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_9_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_10
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_10 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000063CU) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_10_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_10_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_10_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_11
*/
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_11 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000640U) )
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_11_WORD_SHIFT 0
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_11_WORD_WIDTH 32
#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_11_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_SAFETY_GATE
*/
#define PMU_GLOBAL_SAFETY_GATE ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000650U) )
#define PMU_GLOBAL_SAFETY_GATE_PMU_LOGCLR_ENABLE_SHIFT 2
#define PMU_GLOBAL_SAFETY_GATE_PMU_LOGCLR_ENABLE_WIDTH 1
#define PMU_GLOBAL_SAFETY_GATE_PMU_LOGCLR_ENABLE_MASK ((u32)0X00000004U)
#define PMU_GLOBAL_SAFETY_GATE_LBIST_ENABLE_SHIFT 1
#define PMU_GLOBAL_SAFETY_GATE_LBIST_ENABLE_WIDTH 1
#define PMU_GLOBAL_SAFETY_GATE_LBIST_ENABLE_MASK ((u32)0X00000002U)
#define PMU_GLOBAL_SAFETY_GATE_SCAN_ENABLE_SHIFT 0
#define PMU_GLOBAL_SAFETY_GATE_SCAN_ENABLE_WIDTH 1
#define PMU_GLOBAL_SAFETY_GATE_SCAN_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: PMU_GLOBAL_MBIST_RST
*/
#define PMU_GLOBAL_MBIST_RST ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000700U) )
#define PMU_GLOBAL_MBIST_RST_REG_SHIFT 0
#define PMU_GLOBAL_MBIST_RST_REG_WIDTH 32
#define PMU_GLOBAL_MBIST_RST_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_MBIST_PG_EN
*/
#define PMU_GLOBAL_MBIST_PG_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000704U) )
#define PMU_GLOBAL_MBIST_PG_EN_REG_SHIFT 0
#define PMU_GLOBAL_MBIST_PG_EN_REG_WIDTH 32
#define PMU_GLOBAL_MBIST_PG_EN_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_MBIST_SETUP
*/
#define PMU_GLOBAL_MBIST_SETUP ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000708U) )
#define PMU_GLOBAL_MBIST_SETUP_REG_SHIFT 0
#define PMU_GLOBAL_MBIST_SETUP_REG_WIDTH 32
#define PMU_GLOBAL_MBIST_SETUP_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_MBIST_DONE
*/
#define PMU_GLOBAL_MBIST_DONE ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000710U) )
#define PMU_GLOBAL_MBIST_DONE_WORD_SHIFT 0
#define PMU_GLOBAL_MBIST_DONE_WORD_WIDTH 32
#define PMU_GLOBAL_MBIST_DONE_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_MBIST_GOOD
*/
#define PMU_GLOBAL_MBIST_GOOD ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000714U) )
#define PMU_GLOBAL_MBIST_GOOD_WORD_SHIFT 0
#define PMU_GLOBAL_MBIST_GOOD_WORD_WIDTH 32
#define PMU_GLOBAL_MBIST_GOOD_WORD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_SAFETY_CHK
*/
#define PMU_GLOBAL_SAFETY_CHK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000800U) )
#define PMU_GLOBAL_SAFETY_CHK_REG_SHIFT 0
#define PMU_GLOBAL_SAFETY_CHK_REG_WIDTH 32
#define PMU_GLOBAL_SAFETY_CHK_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ECO_1
*/
#define PMU_GLOBAL_ECO_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000804U) )
#define PMU_GLOBAL_ECO_1_REG_SHIFT 0
#define PMU_GLOBAL_ECO_1_REG_WIDTH 32
#define PMU_GLOBAL_ECO_1_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_GLOBAL_ECO_2
*/
#define PMU_GLOBAL_ECO_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000808U) )
#define PMU_GLOBAL_ECO_2_REG_SHIFT 0
#define PMU_GLOBAL_ECO_2_REG_WIDTH 32
#define PMU_GLOBAL_ECO_2_REG_MASK ((u32)0XFFFFFFFFU)
#ifdef __cplusplus
}
#endif
#endif /* _PMU_GLOBAL_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pmu_local.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _PMU_LOCAL_H_
#define _PMU_LOCAL_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* PMU_LOCAL Base Address
*/
#define PMU_LOCAL_BASEADDR ((u32)0XFFD60000U)
/**
* Register: PMU_LOCAL_DOMAIN_ISO_CNTRL
*/
#define PMU_LOCAL_DOMAIN_ISO_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000F0U) )
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_LOCKED_SHIFT 31
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_LOCKED_WIDTH 1
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_LOCKED_MASK ((u32)0X80000000U)
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_FP_PL_SHIFT 5
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_FP_PL_WIDTH 1
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_FP_PL_MASK ((u32)0X00000020U)
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_PCAP_SHIFT 4
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_PCAP_WIDTH 1
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_PCAP_MASK ((u32)0X00000010U)
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_NON_PCAP_SHIFT 3
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_NON_PCAP_WIDTH 1
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_NON_PCAP_MASK ((u32)0X00000008U)
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_2_SHIFT 2
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_2_WIDTH 1
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_2_MASK ((u32)0X00000004U)
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_1_SHIFT 1
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_1_WIDTH 1
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_1_MASK ((u32)0X00000002U)
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_PMU_SHIFT 0
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_PMU_WIDTH 1
#define PMU_LOCAL_DOMAIN_ISO_CNTRL_PMU_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_GPO1_READ
*/
#define PMU_LOCAL_GPO1_READ ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000214U) )
#define PMU_LOCAL_GPO1_READ_MIO_GPO_SHIFT 0
#define PMU_LOCAL_GPO1_READ_MIO_GPO_WIDTH 6
#define PMU_LOCAL_GPO1_READ_MIO_GPO_MASK ((u32)0X0000003FU)
/**
* Register: PMU_LOCAL_GPO2_READ
*/
#define PMU_LOCAL_GPO2_READ ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000218U) )
#define PMU_LOCAL_GPO2_READ_DAP_RPU_WAKE_ACK_SHIFT 9
#define PMU_LOCAL_GPO2_READ_DAP_RPU_WAKE_ACK_WIDTH 1
#define PMU_LOCAL_GPO2_READ_DAP_RPU_WAKE_ACK_MASK ((u32)0X00000200U)
#define PMU_LOCAL_GPO2_READ_DAP_FP_WAKE_ACK_SHIFT 8
#define PMU_LOCAL_GPO2_READ_DAP_FP_WAKE_ACK_WIDTH 1
#define PMU_LOCAL_GPO2_READ_DAP_FP_WAKE_ACK_MASK ((u32)0X00000100U)
#define PMU_LOCAL_GPO2_READ_PS_STATUS_SHIFT 7
#define PMU_LOCAL_GPO2_READ_PS_STATUS_WIDTH 1
#define PMU_LOCAL_GPO2_READ_PS_STATUS_MASK ((u32)0X00000080U)
#define PMU_LOCAL_GPO2_READ_FP_LP_PWRDWN_REQ_SHIFT 6
#define PMU_LOCAL_GPO2_READ_FP_LP_PWRDWN_REQ_WIDTH 1
#define PMU_LOCAL_GPO2_READ_FP_LP_PWRDWN_REQ_MASK ((u32)0X00000040U)
/**
* Register: PMU_LOCAL_GPO3_READ
*/
#define PMU_LOCAL_GPO3_READ ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000021CU) )
#define PMU_LOCAL_GPO3_READ_PL_GPO_SHIFT 0
#define PMU_LOCAL_GPO3_READ_PL_GPO_WIDTH 32
#define PMU_LOCAL_GPO3_READ_PL_GPO_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_GPI1_ENABLE
*/
#define PMU_LOCAL_GPI1_ENABLE ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000224U) )
#define PMU_LOCAL_GPI1_ENABLE_APB_AIB_ERROR_SHIFT 31
#define PMU_LOCAL_GPI1_ENABLE_APB_AIB_ERROR_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_APB_AIB_ERROR_MASK ((u32)0X80000000U)
#define PMU_LOCAL_GPI1_ENABLE_AXI_AIB_ERROR_SHIFT 30
#define PMU_LOCAL_GPI1_ENABLE_AXI_AIB_ERROR_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_AXI_AIB_ERROR_MASK ((u32)0X40000000U)
#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG2_INT_SHIFT 29
#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG2_INT_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG2_INT_MASK ((u32)0X20000000U)
#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG1_INT_SHIFT 28
#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG1_INT_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG1_INT_MASK ((u32)0X10000000U)
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU3_PWRUP_REQ_SHIFT 23
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU3_PWRUP_REQ_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU3_PWRUP_REQ_MASK ((u32)0X00800000U)
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU2_PWRUP_REQ_SHIFT 22
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU2_PWRUP_REQ_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU2_PWRUP_REQ_MASK ((u32)0X00400000U)
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU1_PWRUP_REQ_SHIFT 21
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU1_PWRUP_REQ_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU1_PWRUP_REQ_MASK ((u32)0X00200000U)
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU0_PWRUP_REQ_SHIFT 20
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU0_PWRUP_REQ_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU0_PWRUP_REQ_MASK ((u32)0X00100000U)
#define PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_SHIFT 16
#define PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_MASK ((u32)0X00010000U)
#define PMU_LOCAL_GPI1_ENABLE_MIO_WAKE_SHIFT 10
#define PMU_LOCAL_GPI1_ENABLE_MIO_WAKE_WIDTH 6
#define PMU_LOCAL_GPI1_ENABLE_MIO_WAKE_MASK ((u32)0X0000FC00U)
#define PMU_LOCAL_GPI1_ENABLE_DAP_RPU_WAKE_SHIFT 9
#define PMU_LOCAL_GPI1_ENABLE_DAP_RPU_WAKE_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_DAP_RPU_WAKE_MASK ((u32)0X00000200U)
#define PMU_LOCAL_GPI1_ENABLE_DAP_FP_WAKE_SHIFT 8
#define PMU_LOCAL_GPI1_ENABLE_DAP_FP_WAKE_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_DAP_FP_WAKE_MASK ((u32)0X00000100U)
#define PMU_LOCAL_GPI1_ENABLE_USB1_WAKE_SHIFT 7
#define PMU_LOCAL_GPI1_ENABLE_USB1_WAKE_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_USB1_WAKE_MASK ((u32)0X00000080U)
#define PMU_LOCAL_GPI1_ENABLE_USB0_WAKE_SHIFT 6
#define PMU_LOCAL_GPI1_ENABLE_USB0_WAKE_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_USB0_WAKE_MASK ((u32)0X00000040U)
#define PMU_LOCAL_GPI1_ENABLE_R5_1_WAKE_SHIFT 5
#define PMU_LOCAL_GPI1_ENABLE_R5_1_WAKE_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_R5_1_WAKE_MASK ((u32)0X00000020U)
#define PMU_LOCAL_GPI1_ENABLE_R5_0_WAKE_SHIFT 4
#define PMU_LOCAL_GPI1_ENABLE_R5_0_WAKE_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_R5_0_WAKE_MASK ((u32)0X00000010U)
#define PMU_LOCAL_GPI1_ENABLE_ACPU3_WAKE_SHIFT 3
#define PMU_LOCAL_GPI1_ENABLE_ACPU3_WAKE_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_ACPU3_WAKE_MASK ((u32)0X00000008U)
#define PMU_LOCAL_GPI1_ENABLE_ACPU2_WAKE_SHIFT 2
#define PMU_LOCAL_GPI1_ENABLE_ACPU2_WAKE_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_ACPU2_WAKE_MASK ((u32)0X00000004U)
#define PMU_LOCAL_GPI1_ENABLE_ACPU1_WAKE_SHIFT 1
#define PMU_LOCAL_GPI1_ENABLE_ACPU1_WAKE_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_ACPU1_WAKE_MASK ((u32)0X00000002U)
#define PMU_LOCAL_GPI1_ENABLE_ACPU0_WAKE_SHIFT 0
#define PMU_LOCAL_GPI1_ENABLE_ACPU0_WAKE_WIDTH 1
#define PMU_LOCAL_GPI1_ENABLE_ACPU0_WAKE_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_GPI2_ENABLE
*/
#define PMU_LOCAL_GPI2_ENABLE ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000228U) )
#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINTFP_ALARM_SHIFT 31
#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINTFP_ALARM_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINTFP_ALARM_MASK ((u32)0X80000000U)
#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINT_ALARM_SHIFT 30
#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINT_ALARM_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINT_ALARM_MASK ((u32)0X40000000U)
#define PMU_LOCAL_GPI2_ENABLE_VCC_PSAUX_ALARM_SHIFT 29
#define PMU_LOCAL_GPI2_ENABLE_VCC_PSAUX_ALARM_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_VCC_PSAUX_ALARM_MASK ((u32)0X20000000U)
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU3_RST_REQ_SHIFT 23
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU3_RST_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU3_RST_REQ_MASK ((u32)0X00800000U)
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU2_RST_REQ_SHIFT 22
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU2_RST_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU2_RST_REQ_MASK ((u32)0X00400000U)
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU1_RST_REQ_SHIFT 21
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU1_RST_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU1_RST_REQ_MASK ((u32)0X00200000U)
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU0_RST_REQ_SHIFT 20
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU0_RST_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU0_RST_REQ_MASK ((u32)0X00100000U)
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU3_RST_REQ_SHIFT 19
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU3_RST_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU3_RST_REQ_MASK ((u32)0X00080000U)
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU2_RST_REQ_SHIFT 18
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU2_RST_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU2_RST_REQ_MASK ((u32)0X00040000U)
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU1_RST_REQ_SHIFT 17
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU1_RST_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU1_RST_REQ_MASK ((u32)0X00020000U)
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU0_RST_REQ_SHIFT 16
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU0_RST_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU0_RST_REQ_MASK ((u32)0X00010000U)
#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU1_RST_REQ_SHIFT 9
#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU1_RST_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU1_RST_REQ_MASK ((u32)0X00000200U)
#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU0_RST_REQ_SHIFT 8
#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU0_RST_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU0_RST_REQ_MASK ((u32)0X00000100U)
#define PMU_LOCAL_GPI2_ENABLE_FP_LP_PWRDWN_ACK_SHIFT 6
#define PMU_LOCAL_GPI2_ENABLE_FP_LP_PWRDWN_ACK_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_FP_LP_PWRDWN_ACK_MASK ((u32)0X00000040U)
#define PMU_LOCAL_GPI2_ENABLE_R5_1_PWRDWN_REQ_SHIFT 5
#define PMU_LOCAL_GPI2_ENABLE_R5_1_PWRDWN_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_R5_1_PWRDWN_REQ_MASK ((u32)0X00000020U)
#define PMU_LOCAL_GPI2_ENABLE_R5_0_PWRDWN_REQ_SHIFT 4
#define PMU_LOCAL_GPI2_ENABLE_R5_0_PWRDWN_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_R5_0_PWRDWN_REQ_MASK ((u32)0X00000010U)
#define PMU_LOCAL_GPI2_ENABLE_ACPU3_PWRDWN_REQ_SHIFT 3
#define PMU_LOCAL_GPI2_ENABLE_ACPU3_PWRDWN_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_ACPU3_PWRDWN_REQ_MASK ((u32)0X00000008U)
#define PMU_LOCAL_GPI2_ENABLE_ACPU2_PWRDWN_REQ_SHIFT 2
#define PMU_LOCAL_GPI2_ENABLE_ACPU2_PWRDWN_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_ACPU2_PWRDWN_REQ_MASK ((u32)0X00000004U)
#define PMU_LOCAL_GPI2_ENABLE_ACPU1_PWRDWN_REQ_SHIFT 1
#define PMU_LOCAL_GPI2_ENABLE_ACPU1_PWRDWN_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_ACPU1_PWRDWN_REQ_MASK ((u32)0X00000002U)
#define PMU_LOCAL_GPI2_ENABLE_ACPU0_PWRDWN_REQ_SHIFT 0
#define PMU_LOCAL_GPI2_ENABLE_ACPU0_PWRDWN_REQ_WIDTH 1
#define PMU_LOCAL_GPI2_ENABLE_ACPU0_PWRDWN_REQ_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_GPI3_ENABLE
*/
#define PMU_LOCAL_GPI3_ENABLE ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000022CU) )
#define PMU_LOCAL_GPI3_ENABLE_PL_GPI_SHIFT 0
#define PMU_LOCAL_GPI3_ENABLE_PL_GPI_WIDTH 32
#define PMU_LOCAL_GPI3_ENABLE_PL_GPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_PMU_SERV_ERR
*/
#define PMU_LOCAL_PMU_SERV_ERR ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000033CU) )
#define PMU_LOCAL_PMU_SERV_ERR_FWERR3_SHIFT 31
#define PMU_LOCAL_PMU_SERV_ERR_FWERR3_WIDTH 1
#define PMU_LOCAL_PMU_SERV_ERR_FWERR3_MASK ((u32)0X80000000U)
#define PMU_LOCAL_PMU_SERV_ERR_FWERR2_SHIFT 30
#define PMU_LOCAL_PMU_SERV_ERR_FWERR2_WIDTH 1
#define PMU_LOCAL_PMU_SERV_ERR_FWERR2_MASK ((u32)0X40000000U)
#define PMU_LOCAL_PMU_SERV_ERR_FWERR1_SHIFT 29
#define PMU_LOCAL_PMU_SERV_ERR_FWERR1_WIDTH 1
#define PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK ((u32)0X20000000U)
#define PMU_LOCAL_PMU_SERV_ERR_FWERR0_SHIFT 28
#define PMU_LOCAL_PMU_SERV_ERR_FWERR0_WIDTH 1
#define PMU_LOCAL_PMU_SERV_ERR_FWERR0_MASK ((u32)0X10000000U)
#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_FLAG_SHIFT 23
#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_FLAG_WIDTH 1
#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_FLAG_MASK ((u32)0X00800000U)
#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_DATA_SHIFT 0
#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_DATA_WIDTH 20
#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_DATA_MASK ((u32)0X000FFFFFU)
#ifdef __cplusplus
}
#endif
#endif /* _PMU_LOCAL_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/rfdc_v8_0/src/xrfdc_mts.c
/******************************************************************************
* Copyright (C) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrfdc_mts.c
* @addtogroup rfdc_v8_0
* @{
*
* Contains the multi tile sync functions of the XRFdc driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 3.1 jm 01/24/18 Initial release
* 3.2 jm 03/12/18 Fixed DAC latency calculation.
* jm 03/12/18 Added support for reloading DTC scans.
* jm 03/12/18 Add option to configure sysref capture after MTS.
* 4.0 sk 04/09/18 Added API to enable/disable the sysref.
* rk 04/17/18 Adjust calculated latency by sysref period, where doing
* so results in closer alignment to the target latency.
* 5.0 sk 08/03/18 Fixed MISRAC warnings.
* sk 08/03/18 Check for Block0 enable for tiles participating in MTS.
* sk 08/24/18 Reorganize the code to improve readability and
* optimization.
* 5.1 cog 01/29/19 Replace structure reference ADC checks with
* function.
* 6.0 cog 02/17/19 Added XRFdc_GetMTSEnable API.
* 7.0 cog 05/13/19 Formatting changes.
* cog 08/02/19 Formatting changes.
* 7.1 cog 12/20/19 Metal log messages are now more descriptive.
* cog 01/20/20 Changes for MTS Gen 1/2 compatibility mode.
* cog 01/29/20 Fixed metal log typos.
* 8.0 cog 02/10/20 Updated addtogroup.
* cog 02/20/20 Apply applicable clock gated offets to marker counter.
* cog 02/20/20 Double sysref frequency if in IQ mode.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xrfdc_mts.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static void XRFdc_MTS_Sysref_TRx(XRFdc *InstancePtr, u32 Enable);
static void XRFdc_MTS_Sysref_Ctrl(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Is_PLL, u32 Enable_Cap,
u32 Enable_Div_Reset);
static u32 XRFdc_MTS_Sysref_Dist(XRFdc *InstancePtr, int Num_DAC);
static u32 XRFdc_MTS_Sysref_Count(XRFdc *InstancePtr, u32 Type, u32 Count_Val);
static u32 XRFdc_MTS_Dtc_Scan(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, XRFdc_MTS_DTC_Settings *SettingsPtr);
static u32 XRFdc_MTS_Dtc_Code(XRFdc *InstancePtr, u32 Type, u32 BaseAddr, u32 SRCtrlAddr, u32 DTCAddr, u16 SRctl,
u16 SRclr_m, u32 Code);
static u32 XRFdc_MTS_Dtc_Calc(u32 Type, u32 Tile_Id, XRFdc_MTS_DTC_Settings *SettingsPtr, u8 *FlagsPtr);
static void XRFdc_MTS_Dtc_Flag_Debug(u8 *FlagsPtr, u32 Type, u32 Tile_Id, u32 Target, u32 Picked);
static void XRFdc_MTS_FIFOCtrl(XRFdc *InstancePtr, u32 Type, u32 FIFO_Mode, u32 Tiles_To_Clear);
static u32 XRFdc_MTS_GetMarker(XRFdc *InstancePtr, u32 Type, u32 Tiles, XRFdc_MTS_Marker *MarkersPtr, int Marker_Delay);
static void XRFdc_MTS_Marker_Read(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 FIFO_Id, u32 *CountPtr, u32 *LocPtr,
u32 *DonePtr);
static u32 XRFdc_MTS_Latency(XRFdc *InstancePtr, u32 Type, XRFdc_MultiConverter_Sync_Config *ConfigPtr,
XRFdc_MTS_Marker *MarkersPtr);
/*****************************************************************************/
/**
*
* This API enables the master tile sysref Tx/Rx
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Enable the master tile sysref for Tx/Rx, valid values are 0 and 1.
*
* @return
* - None.
*
* @note None.
*
******************************************************************************/
static void XRFdc_MTS_Sysref_TRx(XRFdc *InstancePtr, u32 Enable)
{
u32 BaseAddr;
u32 Data;
BaseAddr = XRFDC_DRP_BASE(XRFDC_DAC_TILE, 0) + XRFDC_HSCOM_ADDR;
Data = (Enable != 0U) ? 0xFFFFU : 0U;
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_SRCAP_T1, XRFDC_MTS_SRCAP_EN_TRX_M, Data);
}
/*****************************************************************************/
/**
*
* This API Control SysRef Capture Settings
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Is_PLL Valid values are 0 and 1.
* @param Enable_Cap Valid values are 0 and 1.
* @param Enable_Div_Reset Valid values are 0 and 1.
*
* @return
* - None.
*
* @note None.
*
******************************************************************************/
static void XRFdc_MTS_Sysref_Ctrl(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Is_PLL, u32 Enable_Cap,
u32 Enable_Div_Reset)
{
u32 BaseAddr;
u16 RegData;
RegData = 0U;
BaseAddr = XRFDC_DRP_BASE(Type, Tile_Id) + XRFDC_HSCOM_ADDR;
/* Write some bits to ensure sysref is in the right mode */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_SRCAP_T1, XRFDC_MTS_SRCAP_INIT_M, 0U);
if (Is_PLL != 0U) {
/* PLL Cap */
RegData = (Enable_Cap != 0U) ? XRFDC_MTS_SRCAP_PLL_M : 0U;
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_SRCAP_PLL, XRFDC_MTS_SRCAP_PLL_M, RegData);
} else {
/* Analog Cap disable */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_SRCAP_T1, XRFDC_MTS_SRCAP_T1_EN, 0U);
/* Analog Divider */
RegData = (Enable_Div_Reset != 0U) ? 0U : XRFDC_MTS_SRCAP_T1_RST;
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_SRCAP_T1, XRFDC_MTS_SRCAP_T1_RST, RegData);
/* Digital Divider */
RegData = (Enable_Div_Reset != 0U) ? 0U : XRFDC_MTS_SRCAP_DIG_M;
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_SRCAP_DIG, XRFDC_MTS_SRCAP_DIG_M, RegData);
/* Set SysRef Cap Clear */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_SRCAP_T1, XRFDC_MTS_SRCLR_T1_M, XRFDC_MTS_SRCLR_T1_M);
/* Analog Cap enable */
RegData = (Enable_Cap != 0U) ? XRFDC_MTS_SRCAP_T1_EN : 0U;
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_SRCAP_T1, XRFDC_MTS_SRCAP_T1_EN, RegData);
/* Unset SysRef Cap Clear */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_SRCAP_T1, XRFDC_MTS_SRCLR_T1_M, 0U);
}
}
/*****************************************************************************/
/**
*
* This API Update SysRef Distribution between tiles
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Num_DAC is number of DAC tiles
*
* @return
* - XRFDC_MTS_OK if successful.
* - XRFDC_MTS_NOT_SUPPORTED
*
* @note None.
*
******************************************************************************/
static u32 XRFdc_MTS_Sysref_Dist(XRFdc *InstancePtr, int Num_DAC)
{
if (Num_DAC < 0) {
/* Auto-detect. Only 2 types Supported - 2GSPS ADCs, 4GSPS ADCs */
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3 && XRFdc_IsHighSpeedADC(InstancePtr, 0) != 0U) {
Num_DAC = 2;
} else {
Num_DAC = 4;
}
}
if (Num_DAC == XRFDC_NUM_OF_TILES2) {
/* 2 DACs, 4ADCs */
XRFdc_WriteReg16(InstancePtr, XRFDC_DAC_TILE_DRP_ADDR(0U), XRFDC_MTS_SRDIST, 0xC980U);
XRFdc_WriteReg16(InstancePtr, XRFDC_DAC_TILE_DRP_ADDR(1U), XRFDC_MTS_SRDIST, 0x0100U);
XRFdc_WriteReg16(InstancePtr, XRFDC_ADC_TILE_DRP_ADDR(3U), XRFDC_MTS_SRDIST, 0x1700U);
} else if (Num_DAC == XRFDC_NUM_OF_TILES4) {
/* 4 DACs, 4ADCs */
XRFdc_WriteReg16(InstancePtr, XRFDC_DAC_TILE_DRP_ADDR(0U), XRFDC_MTS_SRDIST, 0xCA80U);
XRFdc_WriteReg16(InstancePtr, XRFDC_DAC_TILE_DRP_ADDR(1U), XRFDC_MTS_SRDIST, 0x2400U);
XRFdc_WriteReg16(InstancePtr, XRFDC_DAC_TILE_DRP_ADDR(2U), XRFDC_MTS_SRDIST, 0x0980U);
XRFdc_WriteReg16(InstancePtr, XRFDC_DAC_TILE_DRP_ADDR(3U), XRFDC_MTS_SRDIST, 0x0100U);
XRFdc_WriteReg16(InstancePtr, XRFDC_ADC_TILE_DRP_ADDR(3U), XRFDC_MTS_SRDIST, 0x0700U);
} else {
return XRFDC_MTS_NOT_SUPPORTED;
}
XRFdc_WriteReg16(InstancePtr, XRFDC_ADC_TILE_DRP_ADDR(0U), XRFDC_MTS_SRDIST, 0x0280U);
XRFdc_WriteReg16(InstancePtr, XRFDC_ADC_TILE_DRP_ADDR(1U), XRFDC_MTS_SRDIST, 0x0600U);
XRFdc_WriteReg16(InstancePtr, XRFDC_ADC_TILE_DRP_ADDR(2U), XRFDC_MTS_SRDIST, 0x8880U);
return XRFDC_MTS_OK;
}
/*****************************************************************************/
/**
*
* This API Wait for a number of sysref's to be captured
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Count_Val to wait for a number of sysref's to be captured.
*
* @return
* - XRFDC_MTS_OK if successful.
* - XRFDC_MTS_TIMEOUT if timeout occurs.
*
* @note None.
*
******************************************************************************/
static u32 XRFdc_MTS_Sysref_Count(XRFdc *InstancePtr, u32 Type, u32 Count_Val)
{
u32 RegData;
u32 Timeout;
u32 Shift;
RegData = (Type == XRFDC_DAC_TILE) ? 0x2U : 0x1U;
Shift = (Type == XRFDC_DAC_TILE) ? 8U : 0U;
/* Start counter */
XRFdc_WriteReg(InstancePtr, 0U, XRFDC_MTS_SRCOUNT_CTRL, RegData);
/* Check counter with timeout in case sysref is not active */
Timeout = 0U;
while (Timeout < XRFDC_MTS_SRCOUNT_TIMEOUT) {
RegData = XRFdc_ReadReg(InstancePtr, 0U, XRFDC_MTS_SRCOUNT_VAL);
RegData = ((RegData >> Shift) & XRFDC_MTS_SRCOUNT_M);
if (RegData >= Count_Val) {
break;
}
Timeout++;
}
if (Timeout >= XRFDC_MTS_SRCOUNT_TIMEOUT) {
metal_log(METAL_LOG_ERROR, "PL SysRef Timeout - PL SysRef not active: %d\n in %s\n", Timeout, __func__);
return XRFDC_MTS_TIMEOUT;
}
return XRFDC_MTS_OK;
}
/*****************************************************************************/
/**
*
* This API print the DTC scan results
*
*
* @param FlagsPtr is for internal usage.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Target is for internal usage.
* @param Picked is for internal usage.
*
* @note None.
*
* @note None.
*
******************************************************************************/
static void XRFdc_MTS_Dtc_Flag_Debug(u8 *FlagsPtr, u32 Type, u32 Tile_Id, u32 Target, u32 Picked)
{
u32 Index;
char buf[XRFDC_MTS_NUM_DTC + 1];
for (Index = 0U; Index < XRFDC_MTS_NUM_DTC; Index++) {
if (Index == Picked) {
buf[Index] = '*';
} else if (Index == Target) {
buf[Index] = '#';
} else {
buf[Index] = '0' + FlagsPtr[Index];
}
}
buf[XRFDC_MTS_NUM_DTC] = '\0';
metal_log(METAL_LOG_INFO, "%s%d: %s\n", (Type == XRFDC_DAC_TILE) ? "DAC" : "ADC", Tile_Id, buf);
(void)buf;
(void)Type;
(void)Tile_Id;
}
/*****************************************************************************/
/**
*
* This API Calculate the best DTC code to use
*
*
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param SettingsPtr dtc settings structure.
* @param FlagsPtr is for internal usage.
*
* @return
* - XRFDC_MTS_OK if successful.
* - XRFDC_MTS_NOT_SUPPORTED if MTS is not supported.
*
* @note None.
*
******************************************************************************/
static u32 XRFdc_MTS_Dtc_Calc(u32 Type, u32 Tile_Id, XRFdc_MTS_DTC_Settings *SettingsPtr, u8 *FlagsPtr)
{
u32 Index, Status, Num_Found;
int Last, Current_Gap, Max_Overlap, Overlap_Cnt;
int Min_Gap, Max_Gap, Diff, Min_Diff, Min_Range, Val, Target;
u8 Min_Gap_Allowed;
int Codes[XRFDC_MTS_MAX_CODE] = { 0 };
Min_Gap_Allowed = (SettingsPtr->IsPLL != 0U) ? XRFDC_MTS_MIN_GAP_PLL : XRFDC_MTS_MIN_GAP_T1;
Status = XRFDC_MTS_OK;
/* Scan the flags and find candidate DTC codes */
Num_Found = 0U;
Max_Gap = 0;
Min_Gap = XRFDC_MTS_NUM_DTC;
Max_Overlap = 0;
Overlap_Cnt = 0;
Last = -1;
FlagsPtr[XRFDC_MTS_NUM_DTC] = 1;
for (Index = 0U; Index <= XRFDC_MTS_NUM_DTC; Index++) {
Current_Gap = Index - Last;
if (FlagsPtr[Index] != 0) {
if (Current_Gap > Min_Gap_Allowed) {
Codes[Num_Found] = Last + (Current_Gap / 2);
Num_Found++;
/* Record max/min gaps */
Current_Gap--;
if (Current_Gap > Max_Gap) {
Max_Gap = Current_Gap;
}
if (Current_Gap < Min_Gap) {
Min_Gap = Current_Gap;
}
}
Last = Index;
}
/* check for the longest run of overlapping codes */
if (FlagsPtr[Index] == 3U) {
Overlap_Cnt++;
if (Overlap_Cnt > Max_Overlap) {
Max_Overlap = Overlap_Cnt;
}
} else {
Overlap_Cnt = 0;
}
}
/* Record some stats */
SettingsPtr->Num_Windows[Tile_Id] = Num_Found;
SettingsPtr->Max_Gap[Tile_Id] = Max_Gap;
SettingsPtr->Min_Gap[Tile_Id] = Min_Gap;
SettingsPtr->Max_Overlap[Tile_Id] = Max_Overlap;
/* Calculate the best code */
if (SettingsPtr->Scan_Mode == XRFDC_MTS_SCAN_INIT) {
/* Initial scan */
if (Tile_Id == SettingsPtr->RefTile) {
/* RefTile: Get the code closest to the target */
Target = XRFDC_MTS_REF_TARGET;
SettingsPtr->Target[Tile_Id] = XRFDC_MTS_REF_TARGET;
Min_Diff = XRFDC_MTS_NUM_DTC;
/* scan all codes to find the closest */
for (Index = 0U; Index < Num_Found; Index++) {
Diff = abs(Target - Codes[Index]);
if (Diff < Min_Diff) {
Min_Diff = Diff;
SettingsPtr->DTC_Code[Tile_Id] = Codes[Index];
}
metal_log(METAL_LOG_DEBUG, "Target %d, DTC Code %d, Diff %d, Min %d\n", Target,
Codes[Index], Diff, Min_Diff);
}
/* set the reference code as the target for the other tiles */
for (Index = 0U; Index < 4U; Index++) {
if (Index != Tile_Id) {
SettingsPtr->Target[Index] = SettingsPtr->DTC_Code[Tile_Id];
}
}
metal_log(METAL_LOG_DEBUG, "RefTile (%d): DTC Code Target %d, Picked %d\n", Tile_Id, Target,
SettingsPtr->DTC_Code[Tile_Id]);
} else {
/*
* Other Tiles: Get the code that minimises the total range of codes
* compute the range of the existing dtc codes
*/
Max_Gap = 0;
Min_Gap = XRFDC_MTS_NUM_DTC;
for (Index = XRFDC_TILE_ID0; Index < XRFDC_TILE_ID4; Index++) {
Val = SettingsPtr->DTC_Code[Index];
if ((Val != -1) && (Val > Max_Gap)) {
Max_Gap = Val;
}
if ((Val != -1) && (Val < Min_Gap)) {
Min_Gap = Val;
}
}
metal_log(METAL_LOG_DEBUG, "Tile (%d): Max/Min %d/%d, Range %d\n", Tile_Id, Max_Gap, Min_Gap,
Max_Gap - Min_Gap);
Min_Range = XRFDC_MTS_NUM_DTC;
for (Index = 0U; Index < Num_Found; Index++) {
Val = Codes[Index];
Diff = Max_Gap - Min_Gap;
if (Val < Min_Gap) {
Diff = Max_Gap - Val;
}
if (Val > Max_Gap) {
Diff = Val - Min_Gap;
}
if (Diff <= Min_Range) {
Min_Range = Diff;
SettingsPtr->DTC_Code[Tile_Id] = Val;
}
metal_log(METAL_LOG_DEBUG, "Tile (%d): Code %d, New-Range: %d, Min-Range: %d\n",
Tile_Id, Val, Diff, Min_Range);
}
metal_log(METAL_LOG_DEBUG, "Tile (%d): Code %d, Range Prev %d, New %d\n", Tile_Id,
SettingsPtr->DTC_Code[Tile_Id], Max_Gap - Min_Gap, Min_Range);
}
} else {
/* Reload the results of an initial scan to seed a new scan */
if (Tile_Id == SettingsPtr->RefTile) {
/* RefTile: Get code closest to the target */
Target = SettingsPtr->Target[Tile_Id];
} else {
Target = SettingsPtr->DTC_Code[SettingsPtr->RefTile] + SettingsPtr->Target[Tile_Id] -
SettingsPtr->Target[SettingsPtr->RefTile];
}
Min_Diff = XRFDC_MTS_NUM_DTC;
/* scan all codes to find the closest */
for (Index = 0U; Index < Num_Found; Index++) {
Diff = abs(Target - Codes[Index]);
if (Diff < Min_Diff) {
Min_Diff = Diff;
SettingsPtr->DTC_Code[Tile_Id] = Codes[Index];
}
metal_log(METAL_LOG_DEBUG, "Reload Target %d, DTC Code %d, Diff %d, Min %d\n", Target,
Codes[Index], Diff, Min_Diff);
}
}
/* Print some debug info */
XRFdc_MTS_Dtc_Flag_Debug(FlagsPtr, Type, Tile_Id, SettingsPtr->Target[Tile_Id], SettingsPtr->DTC_Code[Tile_Id]);
return Status;
}
/*****************************************************************************/
/**
*
* This API Set a DTC code and wait for it to be updated. Return early/late
* flags, if set
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param BaseAddr is for internal usage.
* @param SRCtrlAddr is for internal usage.
* @param DTCAddr is for internal usage.
* @param SRctl is for internal usage.
* @param SRclr_m is for internal usage.
* @param Code is for internal usage.
*
* @return
* - XRFDC_MTS_OK if successful.
* - XRFDC_MTS_TIMEOUT if timeout occurs.
*
* @note None.
*
******************************************************************************/
static u32 XRFdc_MTS_Dtc_Code(XRFdc *InstancePtr, u32 Type, u32 BaseAddr, u32 SRCtrlAddr, u32 DTCAddr, u16 SRctl,
u16 SRclr_m, u32 Code)
{
u32 Status;
/* set the DTC code */
XRFdc_WriteReg16(InstancePtr, BaseAddr, DTCAddr, Code);
/* set sysref cap clear */
XRFdc_WriteReg16(InstancePtr, BaseAddr, SRCtrlAddr, SRctl | SRclr_m);
/* unset sysref cap clear */
XRFdc_WriteReg16(InstancePtr, BaseAddr, SRCtrlAddr, SRctl);
Status = XRFdc_MTS_Sysref_Count(InstancePtr, Type, XRFDC_MTS_DTC_COUNT);
return Status;
}
/*****************************************************************************/
/**
*
* This API Scan the DTC codes and determine the optimal capture code for
* both PLL and T1 cases
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param SettingsPtr dtc settings structure.
*
* @return
* - XRFDC_MTS_OK if successful.
* - XRFDC_MTS_TIMEOUT if timeout occurs.
*
* @note None.
*
******************************************************************************/
static u32 XRFdc_MTS_Dtc_Scan(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, XRFdc_MTS_DTC_Settings *SettingsPtr)
{
u32 Status;
u32 BaseAddr;
u32 SRCtrlAddr;
u32 DTCAddr;
u8 Flags[XRFDC_MTS_NUM_DTC + 1];
u16 SRctl;
u16 SRclr_m;
u16 Flag_s;
u32 Index;
BaseAddr = XRFDC_DRP_BASE(Type, Tile_Id) + XRFDC_HSCOM_ADDR;
Status = XRFDC_MTS_OK;
/* Enable SysRef Capture and Disable Divide Reset */
XRFdc_MTS_Sysref_Ctrl(InstancePtr, Type, Tile_Id, SettingsPtr->IsPLL, 1, 0);
SRCtrlAddr = (SettingsPtr->IsPLL != 0U) ? XRFDC_MTS_SRCAP_PLL : XRFDC_MTS_SRCAP_T1;
DTCAddr = (SettingsPtr->IsPLL != 0U) ? XRFDC_MTS_SRDTC_PLL : XRFDC_MTS_SRDTC_T1;
SRclr_m = (SettingsPtr->IsPLL != 0U) ? XRFDC_MTS_SRCLR_PLL_M : XRFDC_MTS_SRCLR_T1_M;
Flag_s = (SettingsPtr->IsPLL != 0U) ? XRFDC_MTS_SRFLAG_PLL : XRFDC_MTS_SRFLAG_T1;
SRctl = XRFdc_ReadReg16(InstancePtr, BaseAddr, SRCtrlAddr) & ~SRclr_m;
for (Index = 0U; Index < XRFDC_MTS_NUM_DTC; Index++) {
Flags[Index] = 0U;
}
for (Index = 0U; (Index < XRFDC_MTS_NUM_DTC) && (Status == XRFDC_MTS_OK); Index++) {
Status |= XRFdc_MTS_Dtc_Code(InstancePtr, Type, BaseAddr, SRCtrlAddr, DTCAddr, SRctl, SRclr_m, Index);
Flags[Index] = (XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_MTS_SRFLAG) >> Flag_s) & 0x3U;
}
/* Calculate the best DTC code */
(void)XRFdc_MTS_Dtc_Calc(Type, Tile_Id, SettingsPtr, Flags);
/* Program the calculated code */
if (SettingsPtr->DTC_Code[Tile_Id] == -1) {
metal_log(METAL_LOG_ERROR, "Unable to capture analog SysRef safely on %s tile %d\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id);
Status |= XRFDC_MTS_DTC_INVALID;
} else {
(void)XRFdc_MTS_Dtc_Code(InstancePtr, Type, BaseAddr, SRCtrlAddr, DTCAddr, SRctl, SRclr_m,
SettingsPtr->DTC_Code[Tile_Id]);
}
if (SettingsPtr->IsPLL != 0U) {
/* PLL - Disable SysRef Capture */
XRFdc_MTS_Sysref_Ctrl(InstancePtr, Type, Tile_Id, 1, 0, 0);
} else {
/* T1 - Reset Dividers */
XRFdc_MTS_Sysref_Ctrl(InstancePtr, Type, Tile_Id, 0, 1, 1);
Status |= XRFdc_MTS_Sysref_Count(InstancePtr, Type, XRFDC_MTS_DTC_COUNT);
XRFdc_MTS_Sysref_Ctrl(InstancePtr, Type, Tile_Id, 0, 1, 0);
}
return Status;
}
/*****************************************************************************/
/**
*
* This API Control the FIFO enable for the group. If Tiles_to_clear has bits
* set, the FIFOs of those tiles will have their FIFO flags cleared.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param FIFO_Mode is fifo mode.
* @param Tiles_To_Clear bits set, FIFO flags will be cleared for those tiles.
*
* @note None.
*
* @note None.
*
******************************************************************************/
static void XRFdc_MTS_FIFOCtrl(XRFdc *InstancePtr, u32 Type, u32 FIFO_Mode, u32 Tiles_To_Clear)
{
u32 RegAddr;
u32 BaseAddr;
u32 Tile_Id;
u32 Block_Id;
/* Clear the FIFO Flags */
RegAddr = (Type == XRFDC_ADC_TILE) ? XRFDC_ADC_FABRIC_ISR_OFFSET : XRFDC_DAC_FABRIC_ISR_OFFSET;
for (Tile_Id = XRFDC_TILE_ID0; Tile_Id < XRFDC_TILE_ID4; Tile_Id++) {
if (((1U << Tile_Id) & Tiles_To_Clear) != 0U) {
for (Block_Id = XRFDC_BLK_ID0; Block_Id < XRFDC_BLK_ID4; Block_Id++) {
BaseAddr = XRFDC_DRP_BASE(Type, Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Block_Id);
XRFdc_WriteReg16(InstancePtr, BaseAddr, RegAddr, XRFDC_IXR_FIFOUSRDAT_MASK);
}
}
}
/* Enable the FIFOs */
RegAddr = (Type == XRFDC_ADC_TILE) ? XRFDC_MTS_FIFO_CTRL_ADC : XRFDC_MTS_FIFO_CTRL_DAC;
XRFdc_WriteReg(InstancePtr, 0, RegAddr, FIFO_Mode);
}
/*****************************************************************************/
/**
*
* This API Read-back the marker data for an ADC or DAC
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param FIFO_Id is FIFO number.
* @param Count is for internal usage.
* @param Loc is for internal usage.
* @param Done is for internal usage.
*
* @return
* - None.
*
* @note None.
*
******************************************************************************/
static void XRFdc_MTS_Marker_Read(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 FIFO_Id, u32 *CountPtr, u32 *LocPtr,
u32 *DonePtr)
{
u32 BaseAddr;
u32 RegData = 0x0;
u32 RateFactor;
u32 Group;
u32 GStart;
u32 GOffset = XRFDC_CG_FIXED_OFS;
if (Type == XRFDC_ADC_TILE) {
BaseAddr = XRFDC_CTRL_STS_BASE(Type, Tile_Id);
RegData = XRFdc_ReadReg(InstancePtr, BaseAddr, XRFDC_MTS_ADC_MARKER_CNT + (FIFO_Id << 2));
*CountPtr = XRFDC_MTS_FIELD(RegData, XRFDC_MTS_AMARK_CNT_M, 0);
*LocPtr = XRFDC_MTS_FIELD(RegData, XRFDC_MTS_AMARK_LOC_M, XRFDC_MTS_AMARK_LOC_S);
*DonePtr = XRFDC_MTS_FIELD(RegData, XRFDC_MTS_AMARK_DONE_M, XRFDC_MTS_AMARK_DONE_S);
} else {
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, FIFO_Id);
*CountPtr = XRFdc_ReadReg(InstancePtr, BaseAddr, XRFDC_MTS_DAC_MARKER_CNT);
*LocPtr = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_MTS_DAC_MARKER_LOC,
XRFDC_MTS_DAC_MARKER_LOC_MASK(InstancePtr->RFdc_Config.IPType));
*DonePtr = 1;
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
RateFactor = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_DAC_INTERP_CTRL_OFFSET,
XRFDC_INTERP_MODE_I_MASK_EXT);
switch (RateFactor) {
case XRFDC_INTERP_DECIM_1X:
case XRFDC_INTERP_DECIM_2X:
case XRFDC_INTERP_DECIM_4X:
case XRFDC_INTERP_DECIM_8X:
break;
case XRFDC_INTERP_DECIM_3X:
case XRFDC_INTERP_DECIM_6X:
case XRFDC_INTERP_DECIM_12X:
Group = (*CountPtr - GOffset) / XRFDC_CG_CYCLES_TOTAL_X3_X6_X12;
GStart = Group * XRFDC_CG_CYCLES_TOTAL_X3_X6_X12;
*CountPtr = (Group * XRFDC_CG_CYCLES_KEPT_X3_X6_X12) + *CountPtr - GStart;
break;
case XRFDC_INTERP_DECIM_5X:
case XRFDC_INTERP_DECIM_10X:
Group = (*CountPtr - GOffset) / XRFDC_CG_CYCLES_TOTAL_X5_X10;
GStart = Group * XRFDC_CG_CYCLES_TOTAL_X5_X10;
*CountPtr = (Group * XRFDC_CG_CYCLES_KEPT_X5_X10) + *CountPtr - GStart;
break;
case XRFDC_INTERP_DECIM_16X:
Group = (*CountPtr - GOffset) / XRFDC_CG_CYCLES_TOTAL_X16;
GStart = Group * XRFDC_CG_CYCLES_TOTAL_X16;
*CountPtr = (Group * XRFDC_CG_CYCLES_KEPT_X16) + *CountPtr - GStart;
break;
case XRFDC_INTERP_DECIM_20X:
Group = (*CountPtr - GOffset) / XRFDC_CG_CYCLES_TOTAL_X20;
GStart = Group * XRFDC_CG_CYCLES_TOTAL_X20;
*CountPtr = (Group * XRFDC_CG_CYCLES_KEPT_X20) + *CountPtr - GStart;
break;
case XRFDC_INTERP_DECIM_24X:
Group = (*CountPtr - GOffset) / XRFDC_CG_CYCLES_TOTAL_X24;
GStart = Group * XRFDC_CG_CYCLES_TOTAL_X24;
*CountPtr = (Group * XRFDC_CG_CYCLES_KEPT_X24) + *CountPtr - GStart;
break;
case XRFDC_INTERP_DECIM_40X:
Group = (*CountPtr - GOffset) / XRFDC_CG_CYCLES_TOTAL_X40;
GStart = Group * XRFDC_CG_CYCLES_TOTAL_X40;
*CountPtr = (Group * XRFDC_CG_CYCLES_KEPT_X40) + *CountPtr - GStart;
break;
default:
metal_log(METAL_LOG_DEBUG,
"\n Interpolation block is OFF for DAC %u block %u in %s\r\n", Tile_Id,
FIFO_Id, __func__);
break;
}
}
}
metal_log(METAL_LOG_DEBUG, "Marker Read Tile %d, FIFO %d - %08X = %04X: count=%d, loc=%d, done=%d\n", Tile_Id,
FIFO_Id, BaseAddr, RegData, *CountPtr, *LocPtr, *DonePtr);
}
/*****************************************************************************/
/**
*
* This API Run the marker counter and read the results
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tiles is tiles to get marker
* @param MarkersPtr mts marker structure.
* @param Marker_Delay is marker delay.
*
* @return
* - XRFDC_MTS_OK if successful.
* - XRFDC_MTS_TIMEOUT if timeout occurs.
* - XRFDC_MTS_MARKER_RUN
* - XRFDC_MTS_MARKER_MISM
* -
*
* @note None.
*
******************************************************************************/
static u32 XRFdc_MTS_GetMarker(XRFdc *InstancePtr, u32 Type, u32 Tiles, XRFdc_MTS_Marker *MarkersPtr, int Marker_Delay)
{
u32 Done;
u32 Count;
u32 Loc;
u32 Tile_Id;
u32 Block_Id;
u32 Status;
u32 BaseAddr;
Status = XRFDC_MTS_OK;
if (Type == XRFDC_ADC_TILE) {
/* Reset marker counter */
XRFdc_WriteReg(InstancePtr, 0, XRFDC_MTS_ADC_MARKER, 1);
XRFdc_WriteReg(InstancePtr, 0, XRFDC_MTS_ADC_MARKER, 0);
} else {
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
/*
* SysRef Capture should be still active from the DTC Scan
* but set it anyway to be sure
*/
for (Tile_Id = XRFDC_TILE_ID0; Tile_Id < XRFDC_TILE_ID4; Tile_Id++) {
if (((XRFDC_ENABLED << Tile_Id) & Tiles) != 0U) {
XRFdc_MTS_Sysref_Ctrl(InstancePtr, XRFDC_DAC_TILE, Tile_Id, 0, 1, 0);
}
}
/* Set marker delay */
XRFdc_WriteReg(InstancePtr, XRFDC_IP_BASE, XRFDC_MTS_DAC_MARKER_CTRL, Marker_Delay);
} else {
for (Tile_Id = XRFDC_TILE_ID0; Tile_Id < XRFDC_TILE_ID4; Tile_Id++) {
if (((XRFDC_ENABLED << Tile_Id) & Tiles) != 0U) {
for (Block_Id = XRFDC_BLK_ID0; Block_Id < XRFDC_BLK_ID4; Block_Id++) {
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Block_Id);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_DAC_FIFO_MARKER_CTRL,
0x1, 0x1);
}
}
}
}
}
/* Allow the marker counter to run */
Status |= XRFdc_MTS_Sysref_Count(InstancePtr, Type, XRFDC_MTS_MARKER_COUNT);
/* Read master FIFO (FIFO0 in each Tile) */
for (Tile_Id = XRFDC_TILE_ID0; Tile_Id < XRFDC_TILE_ID4; Tile_Id++) {
if (((1U << Tile_Id) & Tiles) != 0U) {
if (Type == XRFDC_DAC_TILE) {
/* Disable SysRef Capture before reading it */
XRFdc_MTS_Sysref_Ctrl(InstancePtr, XRFDC_DAC_TILE, Tile_Id, 0, 0, 0);
Status |= XRFdc_MTS_Sysref_Count(InstancePtr, Type, XRFDC_MTS_MARKER_COUNT);
}
XRFdc_MTS_Marker_Read(InstancePtr, Type, Tile_Id, 0, &Count, &Loc, &Done);
MarkersPtr->Count[Tile_Id] = Count;
MarkersPtr->Loc[Tile_Id] = Loc;
metal_log(METAL_LOG_INFO, "%s%d: Marker: - %d, %d\n", (Type == XRFDC_DAC_TILE) ? "DAC" : "ADC",
Tile_Id, MarkersPtr->Count[Tile_Id], MarkersPtr->Loc[Tile_Id]);
if ((!Done) != 0U) {
metal_log(METAL_LOG_ERROR, "Analog SysRef timeout, SysRef not detected on %s tile %d\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id);
Status |= XRFDC_MTS_MARKER_RUN;
}
/*
* Check all enabled FIFOs agree with the master FIFO.
* This is optional.
*/
for (Block_Id = XRFDC_BLK_ID0; Block_Id < XRFDC_BLK_ID4; Block_Id++) {
if (XRFdc_IsFifoEnabled(InstancePtr, Type, Tile_Id, Block_Id) != 0U) {
XRFdc_MTS_Marker_Read(InstancePtr, Type, Tile_Id, Block_Id, &Count, &Loc,
&Done);
if ((MarkersPtr->Count[Tile_Id] != Count) ||
(MarkersPtr->Loc[Tile_Id] != Loc)) {
metal_log(METAL_LOG_DEBUG,
"Tile %d, FIFO %d Marker != Expected: %d, %d vs %d, %d\n",
Tile_Id, Block_Id, MarkersPtr->Count[Tile_Id],
MarkersPtr->Loc[Tile_Id], Count, Loc);
metal_log(
METAL_LOG_ERROR,
"SysRef capture mismatch on %s tile %d, PL SysRef may not have been captured synchronously\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id);
Status |= XRFDC_MTS_MARKER_MISM;
}
}
}
}
}
return Status;
}
/*****************************************************************************/
/**
*
* This API Calculate the absolute/relative latencies
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param ConfigPtr is mts config structure.
* @param MarkersPtr is mts marker structure.
*
* @return
* - XRFDC_MTS_OK if successful.
* - XRFDC_MTS_DELAY_OVER
* - XRFDC_MTS_TARGET_LOW
* -
*
* @note Latency calculation will use Sysref frequency counters
* logic which will work with IP version 2.0.1 and above.
*
******************************************************************************/
static u32 XRFdc_MTS_Latency(XRFdc *InstancePtr, u32 Type, XRFdc_MultiConverter_Sync_Config *ConfigPtr,
XRFdc_MTS_Marker *MarkersPtr)
{
u32 Status, Fifo, Index, BaseAddr, RegAddr;
int Count_W, Loc_W, Latency, Offset, OffsetReg, Max_Latency, Target, Delta;
int I_Part, F_Part, SysRefT1Period, LatencyDiff, LatencyOffset;
u32 RegData, SysRefFreqCntrDone;
int Target_Latency = -1;
int LatencyOffsetDiff;
u32 Factor = 1U;
u32 Write_Words = 0U;
u32 Read_Words = 1U;
u32 Block_Id;
XRFdc_Mixer_Settings Mixer_Settings;
u32 IQFactor = 1U;
Status = XRFDC_MTS_OK;
if (Type == XRFDC_ADC_TILE) {
(void)XRFdc_GetDecimationFactor(InstancePtr, ConfigPtr->RefTile, 0, &Factor);
} else {
(void)XRFdc_GetInterpolationFactor(InstancePtr, ConfigPtr->RefTile, 0, &Factor);
(void)XRFdc_GetFabWrVldWords(InstancePtr, Type, ConfigPtr->RefTile, 0, &Write_Words);
XRFdc_GetMixerSettings(InstancePtr, Type, ConfigPtr->RefTile, 0, &Mixer_Settings);
if (Mixer_Settings.MixerMode == (XRFDC_MIXER_MODE_C2R)) {
IQFactor = 2U;
} else {
IQFactor = 1U;
}
}
(void)XRFdc_GetFabRdVldWords(InstancePtr, Type, ConfigPtr->RefTile, 0, &Read_Words);
Count_W = Read_Words * Factor;
Loc_W = Factor;
metal_log(METAL_LOG_DEBUG, "Count_W %d, loc_W %d\n", Count_W, Loc_W);
/* Find the individual latencies */
Max_Latency = 0;
/* Determine relative SysRef frequency */
RegData = XRFdc_ReadReg(InstancePtr, 0, XRFDC_MTS_SRFREQ_VAL);
if (Type == XRFDC_ADC_TILE) {
/* ADC SysRef frequency information contained in lower 16 bits */
RegData = RegData & 0XFFFFU;
} else {
/* DAC SysRef frequency information contained in upper 16 bits */
RegData = (RegData >> 16U) & 0XFFFFU;
}
/*
* Ensure SysRef frequency counter has completed.
* Sysref frequency counters logic will work with IP version
* 2.0.1 and above.
*/
SysRefFreqCntrDone = RegData & 0x1U;
if (SysRefFreqCntrDone == 0U) {
metal_log(METAL_LOG_ERROR, "Error : %s SysRef frequency counter not yet done\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC");
Status |= XRFDC_MTS_SYSREF_FREQ_NDONE;
/* Set SysRef period in terms of T1's will not be used */
SysRefT1Period = 0;
} else {
SysRefT1Period = (RegData >> 1) * Count_W;
if (Type == XRFDC_DAC_TILE) {
/*
* DAC marker counter is on the tile clock domain so need
* to update SysRef period accordingly
*/
SysRefT1Period = ((SysRefT1Period * Write_Words) / Read_Words) / IQFactor;
}
metal_log(METAL_LOG_INFO, "SysRef period in terms of %s T1s = %d\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", SysRefT1Period);
}
/* Work out the latencies */
for (Index = XRFDC_TILE_ID0; Index < XRFDC_TILE_ID4; Index++) {
if (((1U << Index) & ConfigPtr->Tiles) != 0U) {
Latency = (MarkersPtr->Count[Index] * Count_W) + (MarkersPtr->Loc[Index] * Loc_W);
/* Set marker counter target on first tile */
if (Target_Latency < 0) {
Target_Latency = ConfigPtr->Target_Latency;
if (Target_Latency < 0) {
Target_Latency = Latency;
}
metal_log(METAL_LOG_INFO, "%s target latency = %d\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Target_Latency);
}
/*
* Adjust reported counter values if offsetting by a SysRef
* period reduces distance between current and target latencies
*/
LatencyDiff = Target_Latency - Latency;
LatencyOffset = (LatencyDiff > 0) ? (Latency + SysRefT1Period) : (Latency - SysRefT1Period);
LatencyOffsetDiff = Target_Latency - LatencyOffset;
if (abs(LatencyDiff) > abs(LatencyOffsetDiff)) {
Latency = LatencyOffset;
metal_log(METAL_LOG_INFO, "%s%d latency offset by a SysRef period to %d\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Index, Latency);
}
ConfigPtr->Latency[Index] = Latency;
if (Latency > Max_Latency) {
Max_Latency = Latency;
}
metal_log(METAL_LOG_DEBUG, "Tile %d, latency %d, max %d\n", Index, Latency, Max_Latency);
}
}
/*
* Adjust the latencies to meet the target. Choose max, if it
* is not supplied by the user.
*/
Target = (ConfigPtr->Target_Latency < 0) ? Max_Latency : ConfigPtr->Target_Latency;
if (Target < Max_Latency) {
/* Cannot correct for -ve latencies, so default to aligning */
Target = Max_Latency;
metal_log(METAL_LOG_ERROR, "Error : %s alignment target latency of %d < minimum possible %d\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Target, Max_Latency);
Status |= XRFDC_MTS_TARGET_LOW;
}
for (Index = XRFDC_TILE_ID0; Index < XRFDC_TILE_ID4; Index++) {
if (((1U << Index) & ConfigPtr->Tiles) != 0U) {
Delta = Target - ConfigPtr->Latency[Index];
if (Delta < 0) {
Delta = 0;
}
I_Part = Delta / Factor;
F_Part = Delta % Factor;
Offset = I_Part;
if (F_Part > (int)(Factor / 2U)) {
Offset++;
}
metal_log(METAL_LOG_DEBUG, "Target %d, Tile %d, delta %d, i/f_part %d/%d, offset %d\n", Target,
Index, Delta, I_Part, F_Part, Offset * Factor);
/* check for excessive delay correction values */
if (Offset > (int)XRFDC_MTS_DELAY_MAX) {
Offset = (int)XRFDC_MTS_DELAY_MAX;
metal_log(
METAL_LOG_ERROR,
"Alignment correction delay %d required exceeds maximum (%u) for %s Tile %d\n",
Offset, XRFDC_MTS_DELAY_MAX, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Index);
Status |= XRFDC_MTS_DELAY_OVER;
}
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
// Adjust the latency, write the same value to each FIFO
BaseAddr = XRFDC_CTRL_STS_BASE(Type, Index);
;
for (Fifo = XRFDC_BLK_ID0; Fifo < XRFDC_BLK_ID4; Fifo++) {
RegAddr = XRFDC_MTS_DELAY_CTRL + (Fifo << 2);
RegData = XRFdc_ReadReg(InstancePtr, BaseAddr, RegAddr);
RegData = XRFDC_MTS_RMW(RegData, XRFDC_MTS_DELAY_VAL_M, Offset);
XRFdc_WriteReg(InstancePtr, BaseAddr, RegAddr, RegData);
}
} else {
for (Block_Id = XRFDC_BLK_ID0; Block_Id < XRFDC_BLK_ID4; Block_Id++) {
BaseAddr = XRFDC_BLOCK_BASE(Type, Index, Block_Id);
if (Offset > 0) {
OffsetReg = Offset | XRFDC_MTS_DIR_FIFO_PTR;
} else {
OffsetReg = Offset;
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MTS_DAC_FABRIC_OFFSET, 0x7F,
OffsetReg);
}
}
/* Report the total latency for this tile */
ConfigPtr->Latency[Index] = ConfigPtr->Latency[Index] + (Offset * Factor);
ConfigPtr->Offset[Index] = Offset;
/* Set the Final SysRef Capture Enable state */
XRFdc_MTS_Sysref_Ctrl(InstancePtr, Type, Index, 0, ConfigPtr->SysRef_Enable, 0);
}
}
return Status;
}
/*****************************************************************************/
/**
*
* This API is used to enable/disable the sysref.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param DACSyncConfigPtr is pointer to DAC Multi-Tile Sync config structure.
* @param ADCSyncConfigPtr is pointer to ADC Multi-Tile Sync config structure.
* @param SysRefEnable valid values are 0(disable) and 1(enable).
*
* @return
* - XRFDC_MTS_OK if successful.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_MTS_Sysref_Config(XRFdc *InstancePtr, XRFdc_MultiConverter_Sync_Config *DACSyncConfigPtr,
XRFdc_MultiConverter_Sync_Config *ADCSyncConfigPtr, u32 SysRefEnable)
{
u32 Tile;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(DACSyncConfigPtr != NULL);
Xil_AssertNonvoid(ADCSyncConfigPtr != NULL);
/* Enable/disable SysRef Capture on all DACs participating in MTS */
for (Tile = XRFDC_TILE_ID0; Tile < XRFDC_TILE_ID4; Tile++) {
if (((1U << Tile) & DACSyncConfigPtr->Tiles) != 0U) {
XRFdc_MTS_Sysref_Ctrl(InstancePtr, XRFDC_DAC_TILE, Tile, 0, SysRefEnable, 0);
}
}
/* Enable/Disable SysRef Capture on all ADCs participating in MTS */
for (Tile = XRFDC_TILE_ID0; Tile < XRFDC_TILE_ID4; Tile++) {
if (((1U << Tile) & ADCSyncConfigPtr->Tiles) != 0U) {
XRFdc_MTS_Sysref_Ctrl(InstancePtr, XRFDC_ADC_TILE, Tile, 0, SysRefEnable, 0);
}
}
/* Enable/Disable SysRef TRX */
XRFdc_MTS_Sysref_TRx(InstancePtr, SysRefEnable);
return XRFDC_MTS_OK;
}
/*****************************************************************************/
/**
*
* This API Initializes the multi-tile sync config structures.
* Optionally allows target codes to be provided for the Pll/T1
* analog sysref capture
*
* @param ConfigPtr pointer to Multi-tile sync config structure.
* @param PLL_CodesPtr pointer to PLL analog sysref capture.
* @param T1_CodesPtr pointer to T1 analog sysref capture.
*
* @note None.
*
* @note None.
*
******************************************************************************/
void XRFdc_MultiConverter_Init(XRFdc_MultiConverter_Sync_Config *ConfigPtr, int *PLL_CodesPtr, int *T1_CodesPtr)
{
u32 Index;
Xil_AssertVoid(ConfigPtr != NULL);
ConfigPtr->RefTile = 0U;
ConfigPtr->DTC_Set_PLL.Scan_Mode = (PLL_CodesPtr == NULL) ? XRFDC_MTS_SCAN_INIT : XRFDC_MTS_SCAN_RELOAD;
ConfigPtr->DTC_Set_T1.Scan_Mode = (T1_CodesPtr == NULL) ? XRFDC_MTS_SCAN_INIT : XRFDC_MTS_SCAN_RELOAD;
ConfigPtr->DTC_Set_PLL.IsPLL = 1U;
ConfigPtr->DTC_Set_T1.IsPLL = 0U;
ConfigPtr->Target_Latency = -1;
ConfigPtr->Marker_Delay = 15;
ConfigPtr->SysRef_Enable = 1; /* By default enable Sysref capture after MTS */
/* Initialize variables per tile */
for (Index = XRFDC_TILE_ID0; Index < XRFDC_TILE_ID4; Index++) {
if (PLL_CodesPtr != NULL) {
ConfigPtr->DTC_Set_PLL.Target[Index] = PLL_CodesPtr[Index];
} else {
ConfigPtr->DTC_Set_PLL.Target[Index] = 0;
}
if (T1_CodesPtr != NULL) {
ConfigPtr->DTC_Set_T1.Target[Index] = T1_CodesPtr[Index];
} else {
ConfigPtr->DTC_Set_T1.Target[Index] = 0;
}
ConfigPtr->DTC_Set_PLL.DTC_Code[Index] = -1;
ConfigPtr->DTC_Set_T1.DTC_Code[Index] = -1;
}
}
/*****************************************************************************/
/**
*
* This is the top level API which will be used for Multi-tile
* Synchronization.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param ConfigPtr Multi-tile sync config structure.
*
* @return
* - XRFDC_MTS_OK if successful.
* - XRFDC_MTS_TIMEOUT if timeout occurs.
* - XRFDC_MTS_MARKER_RUN
* - XRFDC_MTS_MARKER_MISM
* - XRFDC_MTS_NOT_SUPPORTED if MTS is not supported.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_MultiConverter_Sync(XRFdc *InstancePtr, u32 Type, XRFdc_MultiConverter_Sync_Config *ConfigPtr)
{
u32 Status;
u32 Index;
u32 RegData;
XRFdc_IPStatus IPStatus = { 0 };
XRFdc_MTS_Marker Markers = { 0U };
u32 BaseAddr;
u32 TileState;
u32 BlockStatus;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
Status = XRFDC_MTS_OK;
(void)XRFdc_GetIPStatus(InstancePtr, &IPStatus);
for (Index = XRFDC_TILE_ID0; Index < XRFDC_TILE_ID4; Index++) {
if ((ConfigPtr->Tiles & (1U << Index)) != 0U) {
TileState = (Type == XRFDC_DAC_TILE) ? IPStatus.DACTileStatus[Index].TileState :
IPStatus.ADCTileStatus[Index].TileState;
if (TileState != 0xFU) {
metal_log(METAL_LOG_ERROR, "%s tile %d in Multi-Tile group not started\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Index);
Status |= XRFDC_MTS_IP_NOT_READY;
}
BaseAddr = XRFDC_DRP_BASE(Type, Index) - XRFDC_TILE_DRP_OFFSET;
RegData = XRFdc_ReadReg(InstancePtr, BaseAddr, XRFDC_MTS_DLY_ALIGNER0);
if (RegData == 0U) {
metal_log(METAL_LOG_ERROR,
"%s tile %d is not enabled for MTS, check IP configuration\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Index);
Status |= XRFDC_MTS_NOT_ENABLED;
}
BlockStatus = XRFdc_CheckBlockEnabled(InstancePtr, Type, Index, 0x0U);
if (BlockStatus != 0U) {
metal_log(METAL_LOG_ERROR, "%s%d block0 is not enabled, check IP configuration\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Index);
Status |= XRFDC_MTS_NOT_SUPPORTED;
}
}
}
if (Status != XRFDC_MTS_OK) {
return Status;
}
/* Disable the FIFOs */
XRFdc_MTS_FIFOCtrl(InstancePtr, Type, XRFDC_MTS_FIFO_DISABLE, 0);
/* Enable SysRef Rx */
XRFdc_MTS_Sysref_TRx(InstancePtr, 1);
/* Update distribution */
Status |= XRFdc_MTS_Sysref_Dist(InstancePtr, -1);
/* Scan DTCs for each tile */
for (Index = XRFDC_TILE_ID0; Index < XRFDC_TILE_ID4; Index++) {
if ((ConfigPtr->Tiles & (1U << Index)) != 0U) {
/* Run DTC Scan for T1/PLL */
BaseAddr = XRFDC_DRP_BASE(Type, Index) + XRFDC_HSCOM_ADDR;
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
RegData = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_MTS_CLKSTAT);
if ((RegData & XRFDC_MTS_PLLEN_M) != XRFDC_DISABLED) {
/* DTC Scan PLL */
if (Index == XRFDC_BLK_ID0) {
metal_log(METAL_LOG_INFO, "\nDTC Scan PLL\n");
}
ConfigPtr->DTC_Set_PLL.RefTile = ConfigPtr->RefTile;
Status |= XRFdc_MTS_Dtc_Scan(InstancePtr, Type, Index, &ConfigPtr->DTC_Set_PLL);
}
} else {
RegData = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_PLL_DIVIDER0);
if ((((RegData & XRFDC_PLL_DIVIDER0_BYP_PLL_MASK) == XRFDC_DISABLED) ||
((RegData & XRFDC_PLL_DIVIDER0_BYP_OPDIV_MASK) == XRFDC_DISABLED)) &&
((RegData & XRFDC_PLL_DIVIDER0_MODE_MASK) != XRFDC_DISABLED)) {
/* DTC Scan PLL */
if (Index == XRFDC_BLK_ID0) {
metal_log(METAL_LOG_INFO, "\nDTC Scan PLL\n");
}
ConfigPtr->DTC_Set_PLL.RefTile = ConfigPtr->RefTile;
Status |= XRFdc_MTS_Dtc_Scan(InstancePtr, Type, Index, &ConfigPtr->DTC_Set_PLL);
}
}
}
}
/* Scan DTCs for each tile T1 */
metal_log(METAL_LOG_INFO, "\nDTC Scan T1\n", 0);
for (Index = XRFDC_TILE_ID0; Index < XRFDC_TILE_ID4; Index++) {
if ((ConfigPtr->Tiles & (1U << Index)) != 0U) {
ConfigPtr->DTC_Set_T1.RefTile = ConfigPtr->RefTile;
Status |= XRFdc_MTS_Dtc_Scan(InstancePtr, Type, Index, &ConfigPtr->DTC_Set_T1);
}
}
/* Enable FIFOs */
XRFdc_MTS_FIFOCtrl(InstancePtr, Type, XRFDC_MTS_FIFO_ENABLE, ConfigPtr->Tiles);
/* Measure latency */
Status |= XRFdc_MTS_GetMarker(InstancePtr, Type, ConfigPtr->Tiles, &Markers, ConfigPtr->Marker_Delay);
/* Calculate latency difference and adjust for it */
Status |= XRFdc_MTS_Latency(InstancePtr, Type, ConfigPtr, &Markers);
return Status;
}
/*****************************************************************************/
/**
*
* This is the top level API which will be used to check if Multi-tile
* is enabled.
*
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC.
* @param Tile_Id indicates Tile number (0-3).
* @param EnablePtr to be filled with the enable state.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_SUCCESS if error occurs.
*
* @note None.
*
******************************************************************************/
u32 XRFdc_GetMTSEnable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *EnablePtr)
{
u32 RegData;
u32 BaseAddr;
u32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(EnablePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Requested Tile (%s %u) not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_CTRL_STS_BASE(Type, Tile_Id);
RegData = XRFdc_ReadReg(InstancePtr, BaseAddr, XRFDC_MTS_DLY_ALIGNER0);
if (RegData == 0) {
*EnablePtr = 0;
} else {
*EnablePtr = 1;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_powerdomain.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_POWERDOMAIN_H_
#define XPM_POWERDOMAIN_H_
#include "xpm_power.h"
#include "xpm_reset.h"
#include "xpm_domain_iso.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct XPm_PowerDomain XPm_PowerDomain;
/* Extern Variable and Function */
extern u32 SysmonAddresses[];
extern u32 ResetReason;
extern int XLoader_ReloadImage(u32 ImageId);
#define XPM_POLL_TIMEOUT (0X1000000U)
#define XPM_DOMAIN_INIT_STATUS_REG PMC_GLOBAL_PERS_GLOB_GEN_STORAGE0
/**
* The power domain node class. This is the base class for all the power domain
* classes.
*/
struct XPm_PowerDomainOps {
XStatus (*InitStart)(u32 *Args, u32 NumOfArgs);
XStatus (*InitFinish)(u32 *Args, u32 NumOfArgs);
XStatus (*ScanClear)(u32 *Args, u32 NumOfArgs);
XStatus (*Mbist)(u32 *Args, u32 NumOfArgs);
XStatus (*Lbist)(u32 *Args, u32 NumOfArgs);
XStatus (*Bisr)(u32 *Args, u32 NumOfArgs);
XStatus (*PlHouseclean)(u32 *Args, u32 NumOfArgs);
XStatus (*MemInit)(u32 *Args, u32 NumOfArgs);
XStatus (*HcComplete)(u32 *Args, u32 NumOfArgs);
XStatus (*XppuCtrl)(u32 *Args, u32 NumOfArgs);
};
struct XPm_PowerDomain {
XPm_Power Power; /**< Power: Power node base class */
XPm_Power *Children; /**< List of children power nodes */
struct XPm_PowerDomainOps *DomainOps; /**< house cleaning operations */
u16 InitMask; /**< Mask to indicate house cleaning functions present */
u16 InitFlag; /**< Flag to indicate house cleaning functions performed */
};
/************************** Function Prototypes ******************************/
XStatus XPmPowerDomain_Init(XPm_PowerDomain *PowerDomain, u32 Id,
u32 BaseAddress, XPm_Power *Parent,
struct XPm_PowerDomainOps *Ops);
XStatus XPm_PowerUpLPD(XPm_Node *Node);
XStatus XPm_PowerDwnLPD(void);
XStatus XPm_PowerUpFPD(XPm_Node *Node);
XStatus XPm_PowerDwnFPD(XPm_Node *Node);
XStatus XPm_PowerUpPLD(XPm_Node *Node);
XStatus XPm_PowerDwnPLD(void);
XStatus XPm_PowerUpME(XPm_Node *Node);
XStatus XPm_PowerDwnME(void);
XStatus XPm_PowerUpCPM(XPm_Node *Node);
XStatus XPm_PowerDwnCPM(void);
XStatus XPm_PowerUpNoC(XPm_Node *Node);
XStatus XPm_PowerDwnNoC(void);
XStatus XPmPowerDomain_InitDomain(XPm_PowerDomain *PwrDomain, u32 Function,
u32 *Args, u32 NumArgs);
XStatus XPmPower_CheckPower(u32 VoltageRailMask);
XStatus XPmPowerDomain_ApplyAmsTrim(u32 DestAddress, u32 PowerDomainId, u32 SateliteIdx);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_POWERDOMAIN_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_pll.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* Contains:
* PLL management implementation based on the use count (the number of
* nodes whose clocks are driven by the PLL)
*********************************************************************/
#include "pm_pll.h"
#include "pm_power.h"
#include "crf_apb.h"
#include "crl_apb.h"
#include "xpfw_util.h"
/* Register offsets (in regard to PLL's base address of control registers) */
#define PM_PLL_CTRL_OFFSET 0x0U
#define PM_PLL_CFG_OFFSET 0x4U
#define PM_PLL_FRAC_OFFSET 0x8U
/* Masks of bitfields in PLL's control register */
#define PM_PLL_CTRL_RESET_MASK 0x1U
#define PM_PLL_CTRL_BYPASS_MASK 0x8U
#define PLL_FRAC_CFG_ENABLED_MASK CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK
/* Configurable: timeout period when waiting for PLL to lock */
#define PM_PLL_LOCK_TIMEOUT 0x10000U
/* Power consumptions for PLLs defined by its states */
#define DEFAULT_PLL_POWER_LOCKED 100U
#define DEFAULT_PLL_POWER_RESET 0U
/* Period of time needed to lock the PLL (to measure) */
#define PM_PLL_LOCKING_TIME 1U
/* PLL flags */
#define PM_PLL_REQUESTED (1U << 0U)
#define PM_PLL_CONTEXT_SAVED (1U << 1U)
typedef struct PmPllParam {
u8 regOffset;
u8 shift;
u8 bits;
} PmPllParam;
static PmPllParam pllParams[] = {
[PM_PLL_PARAM_DIV2] = {
.regOffset = PM_PLL_CTRL_OFFSET,
.shift = 16U,
.bits = 1U,
},
[PM_PLL_PARAM_FBDIV] = {
.regOffset = PM_PLL_CTRL_OFFSET,
.shift = 8U,
.bits = 7U,
},
[PM_PLL_PARAM_DATA] = {
.regOffset = PM_PLL_FRAC_OFFSET,
.shift = 0U,
.bits = 16U,
},
[PM_PLL_PARAM_PRE_SRC] = {
.regOffset = PM_PLL_CTRL_OFFSET,
.shift = 20U,
.bits = 3U,
},
[PM_PLL_PARAM_POST_SRC] = {
.regOffset = PM_PLL_CTRL_OFFSET,
.shift = 24U,
.bits = 3U,
},
[PM_PLL_PARAM_LOCK_DLY] = {
.regOffset = PM_PLL_CFG_OFFSET,
.shift = 25U,
.bits = 7U,
},
[PM_PLL_PARAM_LOCK_CNT] = {
.regOffset = PM_PLL_CFG_OFFSET,
.shift = 13U,
.bits = 10U,
},
[PM_PLL_PARAM_LFHF] = {
.regOffset = PM_PLL_CFG_OFFSET,
.shift = 10U,
.bits = 3U,
},
[PM_PLL_PARAM_CP] = {
.regOffset = PM_PLL_CFG_OFFSET,
.shift = 5U,
.bits = 4U,
},
[PM_PLL_PARAM_RES] = {
.regOffset = PM_PLL_CFG_OFFSET,
.shift = 0U,
.bits = 4U,
},
};
/**
* PmPllBypassAndReset() - Bypass and reset/power down a PLL
* @pll Pointer to a Pll to be bypassed/reset
*/
static void PmPllBypassAndReset(PmPll* const pll)
{
u32 pllCtrl = pll->addr + PM_PLL_CTRL_OFFSET;
u32 r;
#ifdef ENABLE_EM
u32 pllErrMask = 1 << pll->errShift;
pll->errValue = 0;
/*
* Store PLL lock error interrupt mask and error enable
* before disabling it
*/
pll->errValue |= (~XPfw_Read32(PMU_GLOBAL_ERROR_INT_MASK_2) &
pllErrMask) >> pll->errShift;
pll->errValue |= ((~XPfw_Read32(PMU_GLOBAL_ERROR_POR_MASK_2) &
pllErrMask) >> pll->errShift) << 1;
pll->errValue |= ((~XPfw_Read32(PMU_GLOBAL_ERROR_SRST_MASK_2) &
pllErrMask) >> pll->errShift) << 2;
pll->errValue |= ((~XPfw_Read32(PMU_GLOBAL_ERROR_SIG_MASK_2) &
pllErrMask) >> pll->errShift) << 3;
pll->errValue |= ((~XPfw_Read32(PMU_GLOBAL_ERROR_EN_2) &
pllErrMask) >> pll->errShift) << 4;
/* Disable PLL lock error interrupts before powering down PLL */
XPfw_Write32(PMU_GLOBAL_ERROR_INT_DIS_2, pllErrMask);
XPfw_Write32(PMU_GLOBAL_ERROR_POR_DIS_2, pllErrMask);
XPfw_Write32(PMU_GLOBAL_ERROR_SRST_DIS_2, pllErrMask);
XPfw_Write32(PMU_GLOBAL_ERROR_SIG_DIS_2, pllErrMask);
XPfw_RMW32(PMU_GLOBAL_ERROR_EN_2, pllErrMask, 0x0U);
#endif
/* Bypass PLL before putting it into the reset */
r = Xil_In32(pllCtrl);
r |= PM_PLL_CTRL_BYPASS_MASK;
Xil_Out32(pllCtrl, r);
/* Power down PLL (= reset PLL) */
r = Xil_In32(pllCtrl);
r |= PM_PLL_CTRL_RESET_MASK;
Xil_Out32(pllCtrl, r);
}
/**
* PmPllLock() - Trigger locking of the PLL and wait for it to lock
* @pll Target PLL
*
* @status Status of polling for the lock status as returned by
* XPfw_UtilPollForMask
*/
static s32 PmPllLock(const PmPll* const pll)
{
s32 status;
/* Deassert reset to trigger the PLL locking */
XPfw_RMW32(pll->addr + PM_PLL_CTRL_OFFSET, PM_PLL_CTRL_RESET_MASK,
~PM_PLL_CTRL_RESET_MASK);
/* Poll status register for the lock */
status = XPfw_UtilPollForMask(pll->statusAddr, 1U << pll->lockShift,
PM_PLL_LOCK_TIMEOUT);
#ifdef ENABLE_EM
/*
* Restore PLL lock error interrupts and error enable
* once PLL is locked
*/
XPfw_Write32(PMU_GLOBAL_ERROR_INT_EN_2,
((pll->errValue & 1U) << pll->errShift));
XPfw_Write32(PMU_GLOBAL_ERROR_POR_EN_2,
(((pll->errValue >> 1) & 1U) << pll->errShift));
XPfw_Write32(PMU_GLOBAL_ERROR_SRST_EN_2,
(((pll->errValue >> 2) & 1U) << pll->errShift));
XPfw_Write32(PMU_GLOBAL_ERROR_SIG_EN_2,
(((pll->errValue >> 3) & 1U) << pll->errShift));
XPfw_RMW32(PMU_GLOBAL_ERROR_EN_2, (1U << pll->errShift),
(((pll->errValue >> 4) & 1U) << pll->errShift));
#endif
return status;
}
/**
* PmPllSaveContext() - Save the context of the PLL
* @pll PLL whose context should be saved
*/
static void PmPllSaveContext(PmPll* const pll)
{
/* Save register setting */
pll->context.ctrl = XPfw_Read32(pll->addr + PM_PLL_CTRL_OFFSET);
pll->context.cfg = XPfw_Read32(pll->addr + PM_PLL_CFG_OFFSET);
pll->context.frac = XPfw_Read32(pll->addr + PM_PLL_FRAC_OFFSET);
pll->flags |= PM_PLL_CONTEXT_SAVED;
}
/**
* PmPllRestoreContext() - Restore the context of the PLL
* @pll PLL whose context should be restored
*/
static void PmPllRestoreContext(PmPll* const pll)
{
/* Bypass and reset PLL */
PmPllBypassAndReset(pll);
/* Restore register values with reset and bypass asserted */
XPfw_Write32(pll->addr + PM_PLL_CTRL_OFFSET, pll->context.ctrl |
PM_PLL_CTRL_RESET_MASK | PM_PLL_CTRL_BYPASS_MASK);
XPfw_Write32(pll->addr + PM_PLL_CFG_OFFSET, pll->context.cfg);
XPfw_Write32(pll->addr + PM_PLL_FRAC_OFFSET, pll->context.frac);
pll->flags &= ~PM_PLL_CONTEXT_SAVED;
}
/**
* PmPllSuspend() - Save context of PLL and power it down (reset)
* @pll Pointer to a Pll to be suspended
*/
static void PmPllSuspend(PmPll* const pll)
{
PmInfo("%s 1->0\r\n", pll->node.name);
PmPllSaveContext(pll);
/* If PLL is not already in reset, bypass it and put in reset/pwrdn */
if (0U == (pll->context.ctrl & PM_PLL_CTRL_RESET_MASK)) {
PmPllBypassAndReset(pll);
}
PmNodeUpdateCurrState(&pll->node, PM_PLL_STATE_RESET);
if (NULL != pll->node.parent) {
PmPowerReleaseParent(&pll->node);
}
}
/**
* PmPllResume() - Restore PLL context
* @pll Pll whose context should be restored
*
* @return Status of resume:
* - XST_SUCCESS if resumed correctly
* - XST_FAILURE if resume failed (if PLL failed to lock)
*/
static s32 PmPllResume(PmPll* const pll)
{
s32 status = XST_SUCCESS;
PmInfo("%s 0->1\r\n", pll->node.name);
if (0U != (pll->flags & PM_PLL_CONTEXT_SAVED)) {
PmPllRestoreContext(pll);
}
if (0U != (PM_PLL_CTRL_RESET_MASK & pll->context.ctrl)) {
/* By saved/init configuration PLL is in reset, leave it as is */
goto done;
}
if (NULL != pll->node.parent) {
status = PmPowerRequestParent(&pll->node);
if (XST_SUCCESS != status) {
goto done;
}
}
status = PmPllLock(pll);
if (XST_SUCCESS != status) {
/* Failed to lock PLL - assert reset and return */
XPfw_RMW32(pll->addr + PM_PLL_CTRL_OFFSET,
PM_PLL_CTRL_RESET_MASK, PM_PLL_CTRL_RESET_MASK);
goto done;
}
/* PLL is bypassed here (done by the reset) */
if (0U == (PM_PLL_CTRL_BYPASS_MASK & pll->context.ctrl)) {
/* According to saved context PLL should not be bypassed */
XPfw_RMW32(pll->addr + PM_PLL_CTRL_OFFSET,
PM_PLL_CTRL_BYPASS_MASK,
~PM_PLL_CTRL_BYPASS_MASK);
}
PmNodeUpdateCurrState(&pll->node, PM_PLL_STATE_LOCKED);
done:
return status;
}
/**
* PmPllClearConfig() - Clear configuration of the PLL
* @node PLL node
*/
static void PmPllClearConfig(PmNode* const node)
{
PmPll* pll = (PmPll*)node->derived;
pll->flags = 0U;
}
/**
* PmPllGetWakeUpLatency() - Get wake-up latency of a PLL
* @node PLL node
* @lat Pointer to the location where the latency value should be stored
*
* @return XST_SUCCESS if latency value is stored in *lat, XST_NO_FEATURE
* if the latency depends on power parent which has no method
* (getWakeUpLatency) to provide latency information.
*/
static s32 PmPllGetWakeUpLatency(const PmNode* const node, u32* const lat)
{
s32 status = XST_SUCCESS;
PmPll* pll = (PmPll*)node->derived;
PmNode* const powerNode = &node->parent->node;
u32 latency = 0U;
*lat = 0U;
if (PM_PLL_STATE_LOCKED == pll->node.currState) {
goto done;
}
*lat += PM_PLL_LOCKING_TIME;
if (NULL == powerNode->class->getWakeUpLatency) {
status = XST_NO_FEATURE;
goto done;
}
status = powerNode->class->getWakeUpLatency(powerNode, &latency);
if (XST_SUCCESS == status) {
*lat += latency;
}
done:
return status;
}
/**
* PmPllForceDown() - Force down a PLL node
* @node PLL node
*
* @return XST_SUCCESS always (operation cannot fail)
*/
static s32 PmPllForceDown(PmNode* const node)
{
PmPll* pll = (PmPll*)node->derived;
if (PM_PLL_STATE_LOCKED == node->currState) {
pll->flags = 0U;
PmPllSuspend(pll);
}
return XST_SUCCESS;
}
/**
* PmPllInit() - Initialize the PLL
* @node PLL node
*
* @note This function does not affect the PLL configuration in hardware.
*/
static s32 PmPllInit(PmNode* const node)
{
PmPll* pll = (PmPll*)node->derived;
u32 ctrl = XPfw_Read32(pll->addr + PM_PLL_CTRL_OFFSET);
s32 status = XST_SUCCESS;
if (0U == (ctrl & PM_PLL_CTRL_RESET_MASK)) {
node->currState = PM_PLL_STATE_LOCKED;
if (NULL != node->parent) {
status = PmPowerRequestParent(node);
}
} else {
node->currState = PM_PLL_STATE_RESET;
}
return status;
}
/**
* PmPllGetPerms() - Get permissions of masters to control clocks of PLLs
* @node Target PLL node
*
* @return ORed IPI masks of masters allowed to directly control the PLL
*
* @note Permissions to control clocks of PLLs is equivalent to
* permissions to directly configure the PLL.
*/
static u32 PmPllGetPerms(const PmNode* const node)
{
const PmPll* pll = (PmPll*)node->derived;
return pll->perms;
}
/**
* PmPllIsUsable() - Check if the PLL is used according to the set configuration
* @node PLL node
*
* @return True if PLL is used, false otherwise
*/
static bool PmPllIsUsable(PmNode* const node)
{
PmPll* pll = (PmPll*)node->derived;
return 0U != (PM_PLL_REQUESTED & pll->flags);
}
/* Collection of PLL nodes */
static PmNode* pmNodePllBucket[] = {
&pmApll_g.node,
&pmVpll_g.node,
&pmDpll_g.node,
&pmRpll_g.node,
&pmIOpll_g.node,
};
PmNodeClass pmNodeClassPll_g = {
DEFINE_NODE_BUCKET(pmNodePllBucket),
.id = NODE_CLASS_PLL,
.clearConfig = PmPllClearConfig,
.construct = NULL,
.getWakeUpLatency = PmPllGetWakeUpLatency,
.getPowerData = PmNodeGetPowerInfo,
.forceDown = PmPllForceDown,
.init = PmPllInit,
.isUsable = PmPllIsUsable,
.getPerms = PmPllGetPerms,
};
static u8 PmStdPllPowers[] = {
DEFAULT_PLL_POWER_RESET,
DEFAULT_PLL_POWER_LOCKED,
};
PmPll pmApll_g = {
.node = {
.derived = &pmApll_g,
.nodeId = NODE_APLL,
.class = &pmNodeClassPll_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_PLL_STATE_RESET,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmStdPllPowers),
DEFINE_NODE_NAME("apll"),
},
.context = { 0U },
.addr = CRF_APB_APLL_CTRL,
.statusAddr = CRF_APB_PLL_STATUS,
.perms = 0U,
.lockShift = CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT,
.flags = 0U,
.childCount = 0U,
#ifdef ENABLE_EM
.errShift = PMU_GLOBAL_ERROR_SIG_2_APLL_SHIFT,
.errValue = 0,
#endif
};
PmPll pmVpll_g = {
.node = {
.derived = &pmVpll_g,
.nodeId = NODE_VPLL,
.class = &pmNodeClassPll_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_PLL_STATE_RESET,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmStdPllPowers),
DEFINE_NODE_NAME("vpll"),
},
.context = { 0U },
.addr = CRF_APB_VPLL_CTRL,
.statusAddr = CRF_APB_PLL_STATUS,
.perms = 0U,
.lockShift = CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT,
.flags = 0U,
.childCount = 0U,
#ifdef ENABLE_EM
.errShift = PMU_GLOBAL_ERROR_SIG_2_VPLL_SHIFT,
.errValue = 0,
#endif
};
PmPll pmDpll_g __attribute__((__section__(".srdata"))) = {
.node = {
.derived = &pmDpll_g,
.nodeId = NODE_DPLL,
.class = &pmNodeClassPll_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_PLL_STATE_RESET,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmStdPllPowers),
DEFINE_NODE_NAME("dpll"),
},
.context = { 0U },
.addr = CRF_APB_DPLL_CTRL,
.statusAddr = CRF_APB_PLL_STATUS,
.perms = 0U,
.lockShift = CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT,
.flags = 0U,
.childCount = 0U,
#ifdef ENABLE_EM
.errShift = PMU_GLOBAL_ERROR_SIG_2_DPLL_SHIFT,
.errValue = 0,
#endif
};
PmPll pmRpll_g = {
.node = {
.derived = &pmRpll_g,
.nodeId = NODE_RPLL,
.class = &pmNodeClassPll_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_PLL_STATE_RESET,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmStdPllPowers),
DEFINE_NODE_NAME("rpll"),
},
.context = { 0U },
.addr = CRL_APB_RPLL_CTRL,
.statusAddr = CRL_APB_PLL_STATUS,
.perms = 0U,
.lockShift = CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT,
.flags = 0U,
.childCount = 0U,
#ifdef ENABLE_EM
.errShift = PMU_GLOBAL_ERROR_SIG_2_RPLL_SHIFT,
.errValue = 0,
#endif
};
PmPll pmIOpll_g = {
.node = {
.derived = &pmIOpll_g,
.nodeId = NODE_IOPLL,
.class = &pmNodeClassPll_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
.currState = PM_PLL_STATE_RESET,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(PmStdPllPowers),
DEFINE_NODE_NAME("iopll"),
},
.context = { 0U },
.addr = CRL_APB_IOPLL_CTRL,
.statusAddr = CRL_APB_PLL_STATUS,
.perms = 0U,
.lockShift = CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT,
.flags = 0U,
.childCount = 0U,
#ifdef ENABLE_EM
.errShift = PMU_GLOBAL_ERROR_SIG_2_IOPLL_SHIFT,
.errValue = 0,
#endif
};
/**
* PmPllRequest() - Request the PLL
* @pll The requested PLL
* @note If the requested PLL is not locked and if it was never locked
* before, the PM framework will not lock it because the frequency
* related aspects are not handled by the PM framework. The PM
* framework only saves/restores the context of PLLs.
*/
void PmPllRequest(PmPll* const pll)
{
/* If the PLL is suspended it needs to be resumed first */
if (0U != (PM_PLL_CONTEXT_SAVED & pll->flags)) {
s32 status = PmPllResume(pll);
if (XST_SUCCESS != status) {
PmErr("Failed to lock %s", pll->node.name);
}
}
pll->flags |= PM_PLL_REQUESTED;
}
/**
* PmPllRelease() - Release the PLL (PLL will be suspended)
* @pll The released PLL
*/
void PmPllRelease(PmPll* const pll)
{
pll->flags &= ~PM_PLL_REQUESTED;
PmPllSuspend(pll);
}
/**
* PmPllSetParameterInt() - Set PLL parameter
* @pll PLL whose parameter should be set
* @paramId Parameter ID
* @val Parameter value to be set
*
* @return Status of setting the parameter:
* XST_INVALID_PARAM if one of the given arguments is invalid
* XST_SUCCESS if parameter is set
*/
s32 PmPllSetParameterInt(PmPll* const pll, const u32 paramId, const u32 val)
{
s32 status = XST_INVALID_PARAM;
PmPllParam* p;
if (paramId >= ARRAY_SIZE(pllParams)) {
goto done;
}
p = &pllParams[paramId];
if (val > MASK_OF_BITS(p->bits)) {
goto done;
}
/*
* We're running on a ZynqMP compatible machine, make sure the
* VPLL only has one child. Check only while changing PLL rate.
* This helps to remove the warn in cases where the expected clock
* is not using vpll and vpll is used for other stuff.
*/
if (NODE_VPLL == pll->node.nodeId && PM_PLL_PARAM_FBDIV == paramId) {
if (pll->childCount > 1) {
PmErr("More than 1 devices are using VPLL which is forbidden\r\n");
status = XST_PM_MULT_USER;
goto done;
}
}
XPfw_RMW32(pll->addr + p->regOffset, MASK_OF_BITS(p->bits) << p->shift,
val << p->shift);
status = XST_SUCCESS;
done:
return status;
}
/**
* PmPllGetParameterInt() - Get the PLL parameter value
* @pll PLL whose parameter should be get
* @paramId Parameter ID
* @val Location to store parameter value
*
* @return Status of setting the parameter:
* XST_INVALID_PARAM if one of the given arguments is invalid
* XST_SUCCESS if parameter is set
*/
s32 PmPllGetParameterInt(PmPll* const pll, const u32 paramId, u32* const val)
{
s32 status = XST_SUCCESS;
PmPllParam* p;
if (paramId >= ARRAY_SIZE(pllParams)) {
status = XST_INVALID_PARAM;
goto done;
}
p = &pllParams[paramId];
*val = XPfw_Read32(pll->addr + p->regOffset) >> p->shift;
*val &= MASK_OF_BITS(p->bits);
done:
return status;
}
/**
* PmPllSetModeInt() - Set the mode for PLL
* @pll Target PLL
* @mode Identifier of the mode to be set
*
* @return XST_SUCCESS if the mode is set
* XST_NO_DATA if the fractional mode is requested and configured
* fractional divider is zero
*/
s32 PmPllSetModeInt(PmPll* const pll, const u32 mode)
{
s32 status = XST_SUCCESS;
u32 val;
/* Check whether all config parameters are known for frac/int mode */
if (PM_PLL_MODE_FRACTIONAL == mode) {
PmPllParam* p = &pllParams[PM_PLL_PARAM_DATA];
val = XPfw_Read32(pll->addr + p->regOffset);
val = (val >> p->shift) & MASK_OF_BITS(p->bits);
/* Check if fractional divider has been set (data parameter) */
if (0U == val) {
status = XST_NO_DATA;
goto done;
}
}
PmPllBypassAndReset(pll);
if (PM_PLL_MODE_RESET == mode) {
goto done;
}
if (PM_PLL_MODE_FRACTIONAL == mode) {
val = PLL_FRAC_CFG_ENABLED_MASK;
} else {
val = ~PLL_FRAC_CFG_ENABLED_MASK;
}
/* Enable/disable fractional mode */
XPfw_RMW32(pll->addr + PM_PLL_FRAC_OFFSET, PLL_FRAC_CFG_ENABLED_MASK,
val);
status = PmPllLock(pll);
if (XST_SUCCESS != status) {
goto done;
}
/* Deassert bypass if the PLL has locked */
if (XST_SUCCESS == status) {
XPfw_RMW32(pll->addr + PM_PLL_CTRL_OFFSET,
PM_PLL_CTRL_BYPASS_MASK, ~PM_PLL_CTRL_BYPASS_MASK);
}
done:
return status;
}
/**
* PmPllGetModeInt() - Get current PLL mode
* @pll Target PLL
*
* @return Current mode of the PLL, i.e. one of the following:
* PM_PLL_MODE_FRACTIONAL
* PM_PLL_MODE_INTEGER
* PM_PLL_MODE_RESET
*/
u32 PmPllGetModeInt(PmPll* const pll)
{
u32 val, mode;
val = XPfw_Read32(pll->addr + PM_PLL_CTRL_OFFSET);
if (0U != (val & PM_PLL_CTRL_RESET_MASK)) {
mode = PM_PLL_MODE_RESET;
} else {
val = XPfw_Read32(pll->addr + PM_PLL_FRAC_OFFSET);
if (0U != (val & PLL_FRAC_CFG_ENABLED_MASK)) {
mode = PM_PLL_MODE_FRACTIONAL;
} else {
mode = PM_PLL_MODE_INTEGER;
}
}
return mode;
}
/**
* PmPllOpenAccess() - Allow direct access to the master with given IPI mask
* @pll Target PLL
* @ipiMask IPI mask of the master that will be allowed to directly control
* the target PLL
*/
void PmPllOpenAccess(PmPll* const pll, u32 ipiMask) {
pll->perms = ipiMask;
};
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_slave.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*************************************************************************
* PM slave structures definitions and code for handling states of slaves.
************************************************************************/
#include "pm_slave.h"
#include "pm_requirement.h"
#include "pm_defs.h"
#include "pm_common.h"
#include "pm_node.h"
#include "pm_sram.h"
#include "pm_usb.h"
#include "pm_periph.h"
#include "pm_pll.h"
#include "pm_power.h"
#include "lpd_slcr.h"
#include "pm_ddr.h"
#include "pm_clock.h"
#include <unistd.h>
#include "pm_gpp.h"
#include "pm_extern.h"
#include "pm_system.h"
#define HAS_CAPABILITIES(slavePtr, state, caps) \
((caps) == ((caps) & (slavePtr)->slvFsm->states[state]))
/**
* PmGetMaxCapabilities()- Get maximum of all requested capabilities of slave
* @slave Slave whose maximum required capabilities should be determined
*
* @return 32bit value encoding the capabilities
*/
static u32 PmGetMaxCapabilities(const PmSlave* const slave)
{
PmRequirement* req = slave->reqs;
u32 maxCaps = 0U;
while (NULL != req) {
maxCaps |= req->currReq;
req = req->nextMaster;
}
return maxCaps;
}
/**
* PmCheckCapabilities() - Check whether the slave has state with specified
* capabilities
* @slave Slave pointer whose capabilities/states should be checked
* @cap Check for these capabilities
*
* @return Status whether slave has a state with given capabilities
* - XST_SUCCESS if slave has state with given capabilities
* - XST_NO_FEATURE if slave does not have such state
*/
s32 PmCheckCapabilities(const PmSlave* const slave, const u32 capabilities)
{
PmStateId i;
s32 status = XST_NO_FEATURE;
for (i = 0U; i < slave->slvFsm->statesCnt; i++) {
/* Find the first state that contains all capabilities */
if ((capabilities & slave->slvFsm->states[i]) == capabilities) {
status = XST_SUCCESS;
break;
}
}
return status;
}
/**
* PmSlaveHasWakeUpCap() - Check if the slave has a wake-up capability
* @slv Slave to be checked
*
* @return XST_SUCCESS if the slave has the wake-up capability
* XST_NO_FEATURE if the slave doesn't have the wake-up capability
*/
s32 PmSlaveHasWakeUpCap(const PmSlave* const slv)
{
s32 status;
/* Check is the slave's pointer to the GIC Proxy wake initialized */
if (NULL == slv->wake) {
status = XST_NO_FEATURE;
goto done;
}
/* Check whether the slave has a state with wake-up capability */
status = PmCheckCapabilities(slv, PM_CAP_WAKEUP);
done:
return status;
}
/**
* PmSlavePrepareState() - Prepare for entering a state
* @slv Slave that would enter next state
* @next Next state the slave would enter
*
* @return Status fo preparing for the transition (XST_SUCCESS or an error
* code)
*/
static s32 PmSlavePrepareState(PmSlave* const slv, const PmStateId next)
{
s32 status = XST_SUCCESS;
const PmStateId curr = slv->node.currState;
/* If slave has power parent make sure the parent is in proper state */
if (NULL != slv->node.parent) {
if ((0U == (slv->slvFsm->states[curr] & PM_CAP_POWER)) &&
(0U != (slv->slvFsm->states[next] & PM_CAP_POWER))) {
status = PmPowerRequestParent(&slv->node);
if (XST_SUCCESS != status) {
goto done;
}
}
}
/* Check if slave requires clocks in the next state */
if (NULL != slv->node.clocks) {
if ((0U == (slv->slvFsm->states[curr] & PM_CAP_CLOCK)) &&
(0U != (slv->slvFsm->states[next] & PM_CAP_CLOCK))) {
status = PmClockRequest(&slv->node);
}
}
done:
return status;
}
/**
* PmSlaveClearAfterState() - Clean after exiting a state
* @slv Slave that exited the prev state
* @prev Previous state the slave was in
*/
static void PmSlaveClearAfterState(PmSlave* const slv, const PmStateId prev)
{
const PmStateId curr = slv->node.currState;
/* Check if slave doesn't use clocks in the new state */
if (NULL != slv->node.clocks) {
if ((0U != (slv->slvFsm->states[prev] & PM_CAP_CLOCK)) &&
(0U == (slv->slvFsm->states[curr] & PM_CAP_CLOCK))) {
PmClockRelease(&slv->node);
}
}
/* Check if slave doesn't need power in the new state */
if (NULL != slv->node.parent) {
if ((0U != (slv->slvFsm->states[prev] & PM_CAP_POWER)) &&
(0U == (slv->slvFsm->states[curr] & PM_CAP_POWER))) {
PmPowerReleaseParent(&slv->node);
}
}
}
/**
* PmSlaveChangeState() - Change state of a slave
* @slave Slave pointer whose state should be changed
* @state New state
*
* @return XST_SUCCESS if transition was performed successfully.
* Error otherwise.
*/
static s32 PmSlaveChangeState(PmSlave* const slave, const PmStateId state)
{
u32 t;
s32 status;
const PmSlaveFsm* fsm = slave->slvFsm;
PmStateId oldState = slave->node.currState;
/* Check what needs to be done prior to performing the transition */
status = PmSlavePrepareState(slave, state);
if (XST_SUCCESS != status) {
goto done;
}
if (0U == fsm->transCnt) {
/* Slave's FSM has no transitions when it has only one state */
status = XST_SUCCESS;
} else {
/*
* Slave has transitions to change the state. Assume the failure
* and change status if state is changed correctly.
*/
status = XST_FAILURE;
}
for (t = 0U; t < fsm->transCnt; t++) {
/* Find transition from current state to state to be set */
if ((fsm->trans[t].fromState != slave->node.currState) ||
(fsm->trans[t].toState != state)) {
continue;
}
if (NULL != slave->slvFsm->enterState) {
/* Execute transition action of slave's FSM */
status = slave->slvFsm->enterState(slave, state);
} else {
status = XST_SUCCESS;
}
break;
}
done:
if ((oldState != state) && (XST_SUCCESS == status)) {
PmNodeUpdateCurrState(&slave->node, state);
PmSlaveClearAfterState(slave, oldState);
}
if (XST_SUCCESS == status) {
PmInfo("%s %d->%d\r\n", slave->node.name, oldState,
slave->node.currState);
} else {
PmErr("#%d %s state#%u\r\n", status, slave->node.name,
oldState);
}
return status;
}
/**
* PmGetStateWithCaps() - Get id of the state with provided capabilities
* @slave Slave whose states are searched
* @caps Capabilities the state must have
* @state Pointer to a PmStateId variable where the result is put if
* state is found
*
* @return Status of the operation
* - XST_SUCCESS if state is found
* - XST_NO_FEATURE if state with required capabilities does not
* exist
*
* This function is to be called when state of a slave should be updated,
* to find the slave's state with required capabilities.
* Argument caps has included capabilities requested by all masters which
* currently use the slave. Although these separate capabilities are validated
* at the moment request is made, it could happen that there is no state that
* has capabilities requested by all masters. This conflict has to be resolved
* between the masters, so PM returns an error.
*/
static s32 PmGetStateWithCaps(const PmSlave* const slave, const u32 caps,
PmStateId* const state)
{
PmStateId i;
s32 status = XST_PM_CONFLICT;
for (i = 0U; i < slave->slvFsm->statesCnt; i++) {
/* Find the first state that contains all capabilities */
if ((caps & slave->slvFsm->states[i]) == caps) {
status = XST_SUCCESS;
if (NULL != state) {
*state = i;
}
break;
}
}
return status;
}
/**
* PmGetMinRequestedLatency() - Find minimum of all latency requirements
* @slave Slave whose min required latency should be found
*
* @return Latency in microseconds
*/
static u32 PmGetMinRequestedLatency(const PmSlave* const slave)
{
PmRequirement* req = slave->reqs;
u32 minLatency = MAX_LATENCY;
while (NULL != req) {
if (0U != (PM_MASTER_SET_LATENCY_REQ & req->info)) {
if (minLatency > req->latencyReq) {
minLatency = req->latencyReq;
}
}
req = req->nextMaster;
}
return minLatency;
}
/**
* PmGetLatencyFromToState() - Get latency from given state to the highest state
* @slave Pointer to the slave whose states are in question
* @state State from which the latency is calculated
*
* @return Return value for the found latency
*/
static u32 PmGetLatencyFromState(const PmSlave* const slave,
const PmStateId state)
{
u32 i, latency = 0U;
PmStateId highestState = slave->slvFsm->statesCnt - 1;
for (i = 0U; i < slave->slvFsm->transCnt; i++) {
if ((state == slave->slvFsm->trans[i].fromState) &&
(highestState == slave->slvFsm->trans[i].toState)) {
latency = slave->slvFsm->trans[i].latency;
break;
}
}
return latency;
}
/**
* PmConstrainStateByLatency() - Find a higher power state which satisfies
* latency requirements
* @slave Slave whose state may be constrained
* @state Chosen state which does not satisfy latency requirements
* @capsToSet Capabilities that the state must have
* @minLatency Latency requirements to be satisfied
*
* @return Status showing whether the higher power state is found or not.
* State may not be found if multiple masters have contradicting
* requirements, then XST_PM_CONFLICT is returned. Otherwise,
* function returns success.
*/
static s32 PmConstrainStateByLatency(const PmSlave* const slave,
PmStateId* const state,
const u32 capsToSet,
const u32 minLatency)
{
s32 status = XST_PM_CONFLICT;
PmStateId startState = *state;
u32 wkupLat, i;
for (i = startState; i < slave->slvFsm->statesCnt; i++) {
if ((capsToSet & slave->slvFsm->states[i]) != capsToSet) {
/* State candidate has no required capabilities */
continue;
}
wkupLat = PmGetLatencyFromState(slave, i);
if (wkupLat > minLatency) {
/* State does not satisfy latency requirement */
continue;
}
status = XST_SUCCESS;
*state = i;
break;
}
return status;
}
/**
* PmUpdateSlave() - Update the slave's state according to the current
* requirements from all masters
* @slave Slave whose state is about to be updated
*
* @return Status of operation of updating slave's state.
*
* @note A slave may not have state with zero capabilities. If that is
* the case and no capabilities are requested, it is put in lowest power state
* (state ID 0).
* When non-zero capabilities are requested and a selected state which has the
* requested capabilities doesn't satisfy the wake-up latency requirements, the
* first higher power state which satisfies latency requirement and has the
* requested capabilities is configured (in the worst case it's the highest
* power state).
*/
s32 PmUpdateSlave(PmSlave* const slave)
{
PmStateId state = 0U;
s32 status = XST_SUCCESS;
u32 wkupLat, minLat;
u32 caps = PmGetMaxCapabilities(slave);
if (0U != caps) {
/* Find which state has the requested capabilities */
status = PmGetStateWithCaps(slave, caps, &state);
if (XST_SUCCESS != status) {
goto done;
}
}
minLat = PmGetMinRequestedLatency(slave);
wkupLat = PmGetLatencyFromState(slave, state);
if (wkupLat > minLat) {
/* State does not satisfy latency requirement, find another */
status = PmConstrainStateByLatency(slave, &state, caps, minLat);
if (XST_SUCCESS != status) {
goto done;
}
wkupLat = PmGetLatencyFromState(slave, state);
}
slave->node.latencyMarg = minLat - wkupLat;
if (state != slave->node.currState) {
status = PmSlaveChangeState(slave, state);
if (XST_SUCCESS != status) {
goto done;
}
} else {
if (!HAS_CAPABILITIES(slave, state, PM_CAP_POWER) &&
(NULL != slave->node.parent)) {
/* Notify power parent (changed latency requirement) */
status = PmPowerUpdateLatencyReq(&slave->node);
}
}
done:
return status;
}
/**
* PmSlaveGetUsersMask() - Gets all masters' mask currently using the slave
* @slave Slave in question
*
* @return Each master has unique ipiMask which identifies it (one hot
* encoding). Return value represents ORed masks of all masters
* which are currently using the slave.
*/
u32 PmSlaveGetUsersMask(const PmSlave* const slave)
{
PmRequirement* req = slave->reqs;
u32 usage = 0U;
while (NULL != req) {
if (MASTER_REQUESTED_SLAVE(req)) {
/* Found master which is using slave */
usage |= req->master->ipiMask;
}
req = req->nextMaster;
}
return usage;
}
/**
* PmSlaveGetUsageStatus() - get current usage status for a slave node
* @slave Slave node for which the usage status is requested
* @master Master that's requesting the current usage status
*
* @return Usage status:
* - 0: No master is currently using the node
* - 1: Only requesting master is currently using the node
* - 2: Only other masters (1 or more) are currently using the node
* - 3: Both the current and at least one other master is currently
* using the node
*/
u32 PmSlaveGetUsageStatus(const PmSlave* const slave,
const PmMaster* const master)
{
u32 usageStatus = 0U;
const PmRequirement* req = slave->reqs;
while (NULL != req) {
if (MASTER_REQUESTED_SLAVE(req)) {
/* This master is currently using this slave */
if (master == req->master) {
usageStatus |= PM_USAGE_CURRENT_MASTER;
} else {
usageStatus |= PM_USAGE_OTHER_MASTER;
}
}
req = req->nextMaster;
}
return usageStatus;
}
/**
* PmSlaveGetRequirements() - get current requirements for a slave node
* @slave Slave node for which the current requirements are requested
* @master Master that's making the request
*
* @return Current requirements of the requesting master on the node
*/
u32 PmSlaveGetRequirements(const PmSlave* const slave,
const PmMaster* const master)
{
u32 currReq = 0U;
PmRequirement* masterReq = PmRequirementGet(master, slave);
if (NULL == masterReq) {
/* This master has no access to this slave */
goto done;
}
if (!MASTER_REQUESTED_SLAVE(masterReq)) {
/* This master is currently not using this slave */
goto done;
}
/* This master is currently using this slave */
currReq = masterReq->currReq;
done:
return currReq;
}
/**
* PmSlaveVerifyRequest() - Check whether PM framework can grant the request
* @slave Slave node that is requested
*
* @return XST_SUCCESS if the following condition is satisfied : (slave
* is shareable) OR (it is exclusively used AND no other master
* currently uses the slave)
* XST_PM_NODE_USED otherwise
*/
s32 PmSlaveVerifyRequest(const PmSlave* const slave)
{
s32 status = XST_SUCCESS;
u32 usage;
/* If slave is shareable the request is ok */
if (0U != (PM_SLAVE_FLAG_IS_SHAREABLE & slave->flags)) {
goto done;
}
usage = PmSlaveGetUsersMask(slave);
/* Slave is not shareable, if it is unused the request is ok */
if (0U == usage) {
goto done;
}
/* Slave request cannot be granted, node is non-shareable and used */
status = XST_PM_NODE_USED;
done:
return status;
}
/**
* PmSlaveSetConfig() - Set the configuration for the slave
* @slave Slave to configure
* @policy Usage policy for the slave to configure
* @perms Permissions to use the slave (ORed IPI masks of permissible
* masters)
* @return XST_SUCCESS if configuration is set, XST_FAILURE otherwise
*
* @note For each master whose IPI is encoded in the 'perms', the
* requirements structure is automatically allocated and added in
* master's/slave's lists of requirements.
*/
s32 PmSlaveSetConfig(PmSlave* const slave, const u32 policy, const u32 perms)
{
s32 status = XST_SUCCESS;
u32 masterIpiMasks = perms;
u32 caps = slave->slvFsm->states[slave->slvFsm->statesCnt - 1U];
if (0U != (policy & PM_SLAVE_FLAG_IS_SHAREABLE)) {
slave->flags |= PM_SLAVE_FLAG_IS_SHAREABLE;
}
/* Extract and process one by one master from the encoded perms */
while (0U != masterIpiMasks) {
PmMaster* master = PmMasterGetNextFromIpiMask(&masterIpiMasks);
PmRequirement* req;
if (NULL == master) {
status = XST_FAILURE;
goto done;
}
req = PmRequirementAdd(master, slave);
if (NULL == req) {
status = XST_FAILURE;
goto done;
}
req->currReq = caps;
}
done:
return status;
}
/**
* PmSlaveClearConfig() - Clear configuration of the slave node
* @slaveNode Slave node to clear
*/
static void PmSlaveClearConfig(PmNode* const slaveNode)
{
PmSlave* const slave = (PmSlave*)slaveNode->derived;
slave->reqs = NULL;
slave->flags = 0U;
}
/**
* PmSlaveGetWakeUpLatency() - Get wake-up latency of the slave node
* @node Slave node
* @lat Pointer to the location where the latency value should be stored
*
* @return XST_SUCCESS if latency value is stored in *lat, XST_NO_FEATURE
* if the latency depends on power parent which has no method
* (getWakeUpLatency) to provide latency information
*/
static s32 PmSlaveGetWakeUpLatency(const PmNode* const node, u32* const lat)
{
PmSlave* const slave = (PmSlave*)node->derived;
PmNode* powerNode;
s32 status = XST_SUCCESS;
u32 latency = 0U;
*lat = PmGetLatencyFromState(slave, slave->node.currState);
if (NULL == node->parent) {
status = XST_NO_FEATURE;
goto done;
}
powerNode = &node->parent->node;
if (NULL == powerNode->class->getWakeUpLatency) {
status = XST_NO_FEATURE;
goto done;
}
status = powerNode->class->getWakeUpLatency(powerNode, &latency);
if (XST_SUCCESS == status) {
*lat += latency;
}
done:
return status;
}
/**
* PmSlaveForceDown() - Force down the slave node
* @node Slave node to force down
*
* @return Status of performing force down operation
*/
static s32 PmSlaveForceDown(PmNode* const node)
{
s32 status = XST_SUCCESS;
PmSlave* const slave = (PmSlave*)node->derived;
PmRequirement* req = slave->reqs;
while (NULL != req) {
if (MASTER_REQUESTED_SLAVE(req)) {
PmRequirementClear(req);
}
req = req->nextMaster;
}
status = PmUpdateSlave(slave);
if ((NULL != slave->class) && (NULL != slave->class->forceDown)) {
slave->class->forceDown(slave);
}
return status;
}
/**
* PmSlaveInit() - Initialize the slave node
* @node Node to initialize
*
* @return Status of initializing the node
*/
static s32 PmSlaveInit(PmNode* const node)
{
PmSlave* const slave = (PmSlave*)node->derived;
s32 status = XST_SUCCESS;
if (NULL != node->parent) {
if (HAS_CAPABILITIES(slave, node->currState, PM_CAP_POWER)) {
status = PmPowerRequestParent(node);
if (XST_SUCCESS != status) {
goto done;
}
}
}
if (NULL != node->clocks) {
if (HAS_CAPABILITIES(slave, node->currState, PM_CAP_CLOCK)) {
status = PmClockRequest(node);
}
}
if ((NULL != slave->class) && (NULL != slave->class->init)) {
slave->class->init(slave);
}
done:
return status;
}
/**
* PmSlaveIsUsable() - Check if slave is usable according to the configuration
* @node Slave node to check
*
* @return True if slave can be used, false otherwise
*/
static bool PmSlaveIsUsable(PmNode* const node)
{
bool usable = true;
PmSlave* const slave = (PmSlave*)node->derived;
/* Slave is not usable if it has no allocated requirements */
if (NULL == slave->reqs) {
usable = false;
}
return usable;
}
/**
* PmSlaveGetPerms() - Get permissions of masters to control slave's clocks
* @node Slave node
*
* @return ORed masks of permissible masters' IPI masks
*
* @note Only masters that have requested the slave are accounted to have
* permissions
*/
static u32 PmSlaveGetPerms(const PmNode* const node)
{
PmSlave* slave = (PmSlave*)node->derived;
PmRequirement* req = slave->reqs;
u32 perms = 0U;
while (NULL != req) {
/* Check if system requirement (used by PMU) */
if (NULL == req->master) {
perms |= IPI_PMU_0_IER_PMU_0_MASK;
} else {
if (MASTER_REQUESTED_SLAVE(req)) {
perms |= req->master->ipiMask;
}
}
req = req->nextMaster;
}
return perms;
}
/* Collection of slave nodes */
static PmNode* pmNodeSlaveBucket[] = {
&pmSlaveL2_g.slv.node,
&pmSlaveOcm0_g.slv.node,
&pmSlaveOcm1_g.slv.node,
&pmSlaveOcm2_g.slv.node,
&pmSlaveOcm3_g.slv.node,
&pmSlaveTcm0A_g.sram.slv.node,
&pmSlaveTcm0B_g.sram.slv.node,
&pmSlaveTcm1A_g.sram.slv.node,
&pmSlaveTcm1B_g.sram.slv.node,
&pmSlaveUsb0_g.slv.node,
&pmSlaveUsb1_g.slv.node,
&pmSlaveTtc0_g.node,
&pmSlaveTtc1_g.node,
&pmSlaveTtc2_g.node,
&pmSlaveTtc3_g.node,
&pmSlaveSata_g.node,
&pmSlaveGpuPP0_g.slv.node,
&pmSlaveGpuPP1_g.slv.node,
&pmSlaveUart0_g.node,
&pmSlaveUart1_g.node,
&pmSlaveSpi0_g.node,
&pmSlaveSpi1_g.node,
&pmSlaveI2C0_g.node,
&pmSlaveI2C1_g.node,
&pmSlaveSD0_g.node,
&pmSlaveSD1_g.node,
&pmSlaveCan0_g.node,
&pmSlaveCan1_g.node,
&pmSlaveEth0_g.node,
&pmSlaveEth1_g.node,
&pmSlaveEth2_g.node,
&pmSlaveEth3_g.node,
&pmSlaveAdma_g.node,
&pmSlaveGdma_g.node,
&pmSlaveDP_g.node,
&pmSlaveNand_g.node,
&pmSlaveQSpi_g.node,
&pmSlaveGpio_g.node,
&pmSlaveDdr_g.node,
&pmSlaveIpiApu_g.node,
&pmSlaveIpiRpu0_g.node,
&pmSlaveIpiRpu1_g.node,
&pmSlaveIpiPl0_g.node,
&pmSlaveIpiPl1_g.node,
&pmSlaveIpiPl2_g.node,
&pmSlaveIpiPl3_g.node,
&pmSlaveGpu_g.node,
&pmSlavePcie_g.node,
&pmSlavePcap_g.node,
&pmSlaveRtc_g.node,
&pmSlaveVcu_g.slv.node,
&pmSlaveExternDevice_g.node,
&pmSlavePl_g.node,
&pmSlaveFpdWdt_g.node,
};
PmNodeClass pmNodeClassSlave_g = {
DEFINE_NODE_BUCKET(pmNodeSlaveBucket),
.id = NODE_CLASS_SLAVE,
.clearConfig = PmSlaveClearConfig,
.construct = NULL,
.getWakeUpLatency = PmSlaveGetWakeUpLatency,
.getPowerData = PmNodeGetPowerInfo,
.forceDown = PmSlaveForceDown,
.init = PmSlaveInit,
.isUsable = PmSlaveIsUsable,
.getPerms = PmSlaveGetPerms,
};
void PmResetSlaveStates(void)
{
PmSlave* slave;
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmNodeSlaveBucket); i++) {
slave = (PmSlave*)pmNodeSlaveBucket[i]->derived;
if (XST_SUCCESS != PmSlaveChangeState(slave,
slave->slvFsm->statesCnt - 1U)) {
PmWarn("Error in change state for %s\r\n", slave->node.name);
}
}
}
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/pm_callbacks.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/**
* @file pm_callbacks.c
*
* @addtogroup xpm_apis XilPM APIs
* @{
*****************************************************************************/
#include <stdlib.h>
#include "pm_callbacks.h"
#include "pm_client.h"
static XPm_Notifier* notifierList = NULL;
/****************************************************************************/
/**
* @brief Add notifier into the list
*
* @param notifier Pointer to notifier object which needs to be added
* in the list
*
* @return Returns XST_SUCCESS if notifier is added /
* XST_INVALID_PARAM if given notifier argument is NULL
*
* @note None
*
****************************************************************************/
XStatus XPm_NotifierAdd(XPm_Notifier* const notifier)
{
XStatus status = XST_FAILURE;
if (NULL == notifier) {
status = XST_INVALID_PARAM;
goto done;
}
notifier->received = 0U;
/* New notifiers are added at the front of list */
notifier->next = notifierList;
notifierList = notifier;
status = XST_SUCCESS;
done:
return status;
}
/****************************************************************************/
/**
* @brief Remove notifier from the list
*
* @param notifier Pointer to notifier object to be removed from list
*
* @return Returns XST_SUCCESS if notifier is removed /
* XST_INVALID_PARAM if given notifier pointer is NULL /
* XST_FAILURE if notifier is not found
*
* @note None
*
****************************************************************************/
XStatus XPm_NotifierRemove(XPm_Notifier* const notifier)
{
XStatus status = XST_FAILURE;
XPm_Notifier* curr;
XPm_Notifier* prev = NULL;
if (NULL == notifier) {
status = XST_INVALID_PARAM;
goto done;
}
curr = notifierList;
while (curr != NULL) {
if (notifier == curr) {
if (prev != NULL) {
prev->next = curr->next;
}
else {
notifierList = curr->next;
}
status = XST_SUCCESS;
break;
}
prev = curr;
curr = curr->next;
}
done:
return status;
}
/****************************************************************************/
/**
* @brief Call to process notification event
*
* @param node Node which is the subject of notification
* @param event Event which is the subject of notification
* @param oppoint Operating point of the node in question
*
* @return None
*
* @note None
*
****************************************************************************/
void XPm_NotifierProcessEvent(const enum XPmNodeId node,
const enum XPmNotifyEvent event,
const u32 oppoint)
{
XPm_Notifier* notifier;
/* Validate the notifier list */
if (NULL != notifierList) {
notifier = notifierList;
}
else {
notifier = NULL;
}
while (notifier != NULL) {
if ((node == notifier->node) &&
(event == notifier->event)) {
notifier->oppoint = oppoint;
notifier->received++;
if (notifier->callback != NULL) {
notifier->callback(notifier);
}
/*
* Don't break here, there could be multiple pairs of
* (node, event) with different notifiers
*/
}
notifier = notifier->next;
}
}
/** @} */
<file_sep>/python_drivers/qutag_examples/qutag-WriteTimestamps-starter_example.py
# Example for using the Coincidence Counters with python + quTAG
#
# Author: qutools GmbH
# Last edited: Oct 2019
#
# Tested with python 3.7.3 (32bit), numpy-1.13.3 and Windows 7 (64bit)
#
# This is demo code. Use at your own risk. No warranties.
#
# It may be used and modified with no restriction; raw copies as well as
# modified versions may be distributed without limitation.
# for sleep
import time
# This code shows how to get timestamps from a quTAG connected via USB and write them into a text file.
# Import the python wrapper which wraps the DLL functions.
# The wrapper should be in the same directory like this code in the folder '..\QUTAG-V1.x.x\userlib\src'.
try:
import QuTAG
except:
print("Time Tagger wrapper QuTAG.py is not in the search path.")
# Initialize the quTAG device
qutag = QuTAG.QuTAG()
qutag.enableChannels((1,2,3,4))
qutag.setSignalConditioning(1, 3, 1, 0.25)
qutag.setSignalConditioning(2, 3, 1, 0.25)
qutag.setSignalConditioning(3, 3, 1, 0.25)
qutag.setSignalConditioning(4, 3, 1, 0.25)
filename = r'quTAG_timestamps.txt'
# The next function starts or stops writing the timestamp values to a file continuously.
# The timestamps written are already corrected by the detector delays, see example 'qutag-GetHistogramLoop-channelDelay-example.py'.
# Timestamps come in base units of 1 ps. The channel numbers start with 0 in binary formats, with 1 in ASCII.
# A channel number of (100 + Marker Number) is associated with marker input events.
# The 104 is a millisecond tick.
# The following file formats are available:
# ASCII: FILEFORMAT_ASCII - Timestamp values (int base units) and channel numbers as decimal values in two comma separated columns. Channel numbers range from 1 to 8 in this format.
# binary: FILEFORMAT_BINARY - A binary header of 40 bytes, records of 10 bytes, 8 bytes for the timestamp, 2 for the channel number, stored in little endian (Intel) byte order.
# compressed: FILEFORMAT_COMPRESSED - A binary header of 40 bytes, records of 40 bits (5 bytes), 37 bits for the timestamp, 3 for the channel number, stored in little endian (Intel) byte order. No marker events and timer ticks are stored.
# raw: FILEFORMAT_RAW - Like binary, but without header. Provided for backward compatiblity.
print("Recording")
# start writing Timestamps from the quTAG
qutag.writeTimestamps(filename,qutag.FILEFORMAT_ASCII)
# Give some time to accumulate data
time.sleep(5) # 1 second sleep time
# stop writing Timestamps
qutag.writeTimestamps('',qutag.FILEFORMAT_NONE)
print("Let's have a look into the file " + filename)
# Disconnects a connected device and stops the internal event loop.
qutag.deInitialize()
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilskey_v6_9/src/include/xilskey_utils.h
/******************************************************************************
* Copyright (c) 2013 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xilskey_utils.h
* @cond xilskey_internal
* @{
*
* @note
*
* For Ultrascale
* ------------------------------------------------------------------------
* If user wants to Debug and avoid writing Fuses, then user needs to
* define "DEBUG_FUSE_WRITE_DISABLE" that will disable writing to Fuses.
*
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- --------------------------------------------------------
* 1.00a rpoolla 04/26/13 First release
* 2.00 hk 23/01/14 Corrected PL voltage checks to VCCINT and VCCAUX.
* CR#768077.
* Changed PS efuse error codes for voltage out of range
* 3.00 vns 31/07/15 Added Xilskey_Timer_Intialise API and modified
* prototype of XilSKey_Efuse_StartTimer
* Modified efuse PS macro
* XSK_EFUSEPS_RSA_KEY_HASH_STRING_SIZE to
* XSK_EFUSEPL_RSA_KEY_HASH_STRING_SIZE
* Added efuse functionality for Ultrascale.
* 4.0 vns 10/01/15 Added efuse functionality for ZynqMp platform.
* Added XilSKey_Ceil API. Added error code for efuse and
* bbram PS for Zynq MP.
* Modified Xilskey_CrcCalculation API name to
* XilSKey_CrcCalculation. and Xilskey_Timer_Intialise API
* to XilSKey_Timer_Intialise
* vns 10/20/15 Added cplusplus boundary blocks.
* 6.0 vns 07/07/16 Added hardware module time out error code
* 07/18/16 Added error codes for eFUSE PS User FUSEs programming
* Added sysmonpsu driver for temperature and voltage
* checks.
* 6.2 vns 03/10/17 Added error codes for LBist, LPD/FPD SC enable bits
* programming.
* 6.4 vns 02/27/18 Added support for virtex and virtex ultrascale plus
* 6.6 vns 06/06/18 Added doxygen tags
* vns 09/18/18 Added error code for zynqmp efuseps
* vns 10/11/18 Added new error code for SPKID bit revert request
* XSK_EFUSEPS_ERROR_SPKID_BIT_CANT_REVERT
* 6.7 arc 01/05/19 Fixed MISRA-C violations.
* arc 25/02/19 Added Timeout Macro and new error code for
* bbram zeroisation and error in write CRC
* XSK_ZYNQMP_BBRAMPS_ERROR_IN_ZEROISE
* XSK_ZYNQMP_BBRAMPS_ERROR_IN_WRITE_CRC
* mmd 03/17/19 Added timeout and PUF underflow error
* psl 03/19/19 FIxed MISRA-C violation
* psl 03/29/19 Removed GPIO ID macro.
* 6.8 psl 06/07/19 Added doxygen tags
* psl 08/12/19 Fixed MISRA-C violation
* psl 08/23/19 Added Debug define to avoid writing of eFuse.
* 6.9 kpt 02/27/20 Added Error code XSK_EFUSEPS_ERROR_PGM_NOT_DONE.
* 02/27/20 Replaced XSYSMON_DEVICE_ID with
* XSYSMON_PSU_DEVICE_ID.
* kpt 03/31/20 Added Error Codes
* XSK_EFUSEPS_RD_FROM_EFUSE_NOT_ALLOWED
* XSK_EFUSEPS_ERROR_PUF_AUX_ALREADY_PROGRAMMED
* XSK_EFUSEPS_ERROR_PUF_CHASH_ALREADY_PROGRAMMED
*
*****************************************************************************/
#ifndef XILSKEY_UTILS_H
#define XILSKEY_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xparameters.h"
#ifdef XPAR_XSK_MICROBLAZE_PLATFORM
#include "xsysmon.h"
#include "xtmrctr.h"
#else
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU)
#include "xsysmonpsu.h"
#include "xplatform_info.h"
#else
#include "xadcps.h"
#endif
#endif
#include "xstatus.h"
#include "xil_util.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
#ifdef XPAR_XSK_MICROBLAZE_PLATFORM
#define XSK_MICROBLAZE_PLATFORM
#else
#define XSK_ARM_PLATFORM
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU)
#define XSK_ZYNQ_ULTRA_MP_PLATFORM
#else
#define XSK_ZYNQ_PLATFORM
#endif
#endif
/* Definitions for Ultrascale and Ultrascale plus */
#ifdef XSK_MICROBLAZE_PLATFORM
#ifdef XPAR_XSK_MICROBLAZE_ULTRA_PLUS
#define XSK_MICROBLAZE_ULTRA_PLUS
#endif
#ifdef XPAR_XSK_MICROBLAZE_ULTRA
#define XSK_MICROBLAZE_ULTRA
#endif
#endif
#ifdef DEBUG_FUSE_WRITE_DISABLE
#define XilsKey_DbgPrint xil_printf
#endif
/**
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
#ifdef XSK_ZYNQ_PLATFORM
#define XADC_DEVICE_ID XPAR_XADCPS_0_DEVICE_ID
#endif
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
#define XSYSMON_PSU_DEVICE_ID XPAR_XSYSMONPSU_0_DEVICE_ID
/* ZynqMp efusePs ps Ref Clk frequency */
#define XSK_ZYNQMP_EFUSEPS_PS_REF_CLK_FREQ XPAR_PSU_PSS_REF_CLK_FREQ_HZ
#endif
#ifdef XSK_MICROBLAZE_PLATFORM
#define XTMRCTR_DEVICE_ID (XPAR_TMRCTR_0_DEVICE_ID)
#define XSK_EFUSEPL_CLCK_FREQ_ULTRA (XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ)
#define XSK_TMRCTR_NUM (0U)
#endif
#define REVERSE_POLYNOMIAL (0x82F63B78U)
/**< Polynomial for calculating CRC */
/** @name CSU_DMA pause types
* @{
*/
typedef enum {
XSK_FPGA_SERIES_ULTRA, /**< Ultrascale series */
XSK_FPGA_SERIES_ZYNQ, /**< Zynq series */
XSK_FPGA_SERIES_ULTRA_PLUS /**< Ultrascale plus series */
}XSKEfusePl_Fpga;
/*@}*/
/**
* Row numbers of Sysmon
*/
#define XSK_SYSMON_TEMP_ROW (0) /**< Row for Temperature */
#define XSK_SYSMON_VOL_ROW (2) /**< Row for Voltage */
/**
* Temperature and voltage range for PS eFUSE reading and programming
* Temperature in Celsius('C) and Voltage(V) is in volts
*/
#define XSK_EFUSEPS_TEMP_MIN (-40.0f)
#define XSK_EFUSEPS_TEMP_MAX (125.0f)
#define XSK_EFUSEPS_READ_VPAUX_MIN (1.71)
#define XSK_EFUSEPS_READ_VPAUX_MAX (1.98)
#define XSK_EFUSEPS_WRITE_VPAUX_MIN (1.71)
#define XSK_EFUSEPS_WRITE_VPAUX_MAX (1.98)
/* ZynqMP eFUSE voltage ranges */
#define XSK_ZYNQMP_EFUSEPS_VCC_PSINTLP_MIN (0.675)
#define XSK_ZYNQMP_EFUSEPS_VCC_PSINTLP_MAX (0.935)
/* VCC AUX should be 1.8 +/-10% */
#define XSK_ZYNQMP_EFUSEPS_VCC_AUX_MIN (1.62f)
#define XSK_ZYNQMP_EFUSEPS_VCC_AUX_MAX (1.98f)
#ifdef XSK_ZYNQ_PLATFORM
/**
* Converting the celsius temperature to equivalent Binary data for xAdc
*/
#define XSK_EFUSEPS_TEMP_MIN_RAW (XAdcPs_TemperatureToRaw(XSK_EFUSEPS_TEMP_MIN))
#define XSK_EFUSEPS_TEMP_MAX_RAW (XAdcPs_TemperatureToRaw(XSK_EFUSEPS_TEMP_MAX))
/**
* Converting the voltage to equivalent Binary data for xAdc
*/
#define XSK_EFUSEPS_READ_VPAUX_MIN_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPS_READ_VPAUX_MIN))
#define XSK_EFUSEPS_READ_VPAUX_MAX_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPS_READ_VPAUX_MAX))
#define XSK_EFUSEPS_WRITE_VPAUX_MIN_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPS_WRITE_VPAUX_MIN))
#define XSK_EFUSEPS_WRITE_VPAUX_MAX_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPS_WRITE_VPAUX_MAX))
#endif
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
/**
* Converting the celsius temperature to equivalent Binary data for xAdc
*/
#define XSK_EFUSEPS_TEMP_MIN_RAW \
(XSysMonPsu_TemperatureToRaw_OnChip(XSK_EFUSEPS_TEMP_MIN))
#define XSK_EFUSEPS_TEMP_MAX_RAW \
(XSysMonPsu_TemperatureToRaw_OnChip(XSK_EFUSEPS_TEMP_MAX))
#define XSK_EFUSEPS_VPAUX_MIN_RAW \
(XSysMonPsu_VoltageToRaw(XSK_ZYNQMP_EFUSEPS_VCC_AUX_MIN))
#define XSK_EFUSEPS_VPAUX_MAX_RAW \
(XSysMonPsu_VoltageToRaw(XSK_ZYNQMP_EFUSEPS_VCC_AUX_MAX))
#define XSK_EFUSEPS_VCC_PSINTLP_MIN_RAW \
(XSysMonPsu_VoltageToRaw(XSK_ZYNQMP_EFUSEPS_VCC_PSINTLP_MIN))
#define XSK_EFUSEPS_VCC_PSINTLP_MAX_RAW \
(XSysMonPsu_VoltageToRaw(XSK_ZYNQMP_EFUSEPS_VCC_PSINTLP_MAX))
#endif
/**
* Temperature and voltage range for PL eFUSE reading and programming
* Temperature in Celsius('C) and Voltage(V) is in volts
*/
/**
* PL eFUSE write Min and Max Temperature and Voltages
*/
#define XSK_EFUSEPL_WRITE_TEMP_MIN (15U)
#define XSK_EFUSEPL_WRITE_TEMP_MAX (125U)
#define XSK_EFUSEPL_WRITE_VOLTAGE_VCCAUX_MIN (1.71)
#define XSK_EFUSEPL_WRITE_VOLTAGE_VCCAUX_MAX (1.98)
#define XSK_EFUSEPL_WRITE_VOLTAGE_VCCINT_MIN (.87)
#define XSK_EFUSEPL_WRITE_VOLTAGE_VCCINT_MAX (1.1)
/**
* PL eFUSE read Min and Max Temperature and Voltages
*/
#define XSK_EFUSEPL_READ_TEMP_MIN (-55)
#define XSK_EFUSEPL_READ_TEMP_MAX (125)
#define XSK_EFUSEPL_READ_VOLTAGE_VCCAUX_MIN (1.62)
#define XSK_EFUSEPL_READ_VOLTAGE_VCCAUX_MAX (1.98)
#define XSK_EFUSEPL_READ_VOLTAGE_VCCINT_MIN (.795)
#define XSK_EFUSEPL_READ_VOLTAGE_VCCINT_MAX (1.1)
/* Ultrascale Microblaze Voltage range */
#define XSK_EFUSEPL_VOL_VCCAUX_MIN_ULTRA (1.746)
#define XSK_EFUSEPL_VOL_VCCAUX_MAX_ULTRA (1.854)
#define XSK_EFUSEPL_TEMP_MIN_ULTRA (-40)
#define XSK_EFUSEPL_TEMP_MAX_ULTRA (125)
/**
* PL eFUSE write Min and Max Temperature and Voltages
*/
#ifdef XSK_ARM_PLATFORM
/**
* Converting the celsius temperature to equivalent Binary data for xAdc
*/
#define XSK_EFUSEPL_WRITE_TEMP_MIN_RAW (XAdcPs_TemperatureToRaw(XSK_EFUSEPL_WRITE_TEMP_MIN))
#define XSK_EFUSEPL_WRITE_TEMP_MAX_RAW (XAdcPs_TemperatureToRaw(XSK_EFUSEPL_WRITE_TEMP_MAX))
/**
* Converting the voltage to equivalent Binary data for xAdc
*/
#define XSK_EFUSEPL_WRITE_VOLTAGE_VCCAUX_MIN_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPL_WRITE_VOLTAGE_VCCAUX_MIN))
#define XSK_EFUSEPL_WRITE_VOLTAGE_VCCAUX_MAX_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPL_WRITE_VOLTAGE_VCCAUX_MAX))
/**
* Converting the voltage to equivalent Binary data for xAdc
*/
#define XSK_EFUSEPL_WRITE_VOLTAGE_VCCINT_MIN_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPL_WRITE_VOLTAGE_VCCINT_MIN))
#define XSK_EFUSEPL_WRITE_VOLTAGE_VCCINT_MAX_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPL_WRITE_VOLTAGE_VCCINT_MAX))
/**
* PL eFUSE read Min and Max Temperature and Voltages
*/
/**
* Converting the celsius temperature to equivalent Binary data for xAdc
*/
#define XSK_EFUSEPL_READ_TEMP_MIN_RAW (XAdcPs_TemperatureToRaw(XSK_EFUSEPL_READ_TEMP_MIN))
#define XSK_EFUSEPL_READ_TEMP_MAX_RAW (XAdcPs_TemperatureToRaw(XSK_EFUSEPL_READ_TEMP_MAX))
/**
* Converting the voltage to equivalent Binary data for xAdc
*/
#define XSK_EFUSEPL_READ_VOLTAGE_VCCAUX_MIN_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPL_READ_VOLTAGE_VCCAUX_MIN))
#define XSK_EFUSEPL_READ_VOLTAGE_VCCAUX_MAX_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPL_READ_VOLTAGE_VCCAUX_MAX))
/**
* Converting the voltage to equivalent Binary data for xAdc
*/
#define XSK_EFUSEPL_READ_VOLTAGE_VCCINT_MIN_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPL_READ_VOLTAGE_VCCINT_MIN))
#define XSK_EFUSEPL_READ_VOLTAGE_VCCINT_MAX_RAW (XAdcPs_VoltageToRaw(XSK_EFUSEPL_READ_VOLTAGE_VCCINT_MAX))
#else
/**
* Converting the voltage to equivalent Binary data for xAdc
*/
#define XSK_EFUSEPL_VOL_VCCAUX_MIN_RAW_ULTRA (XSysMon_VoltageToRaw(XSK_EFUSEPL_VOL_VCCAUX_MIN_ULTRA))
#define XSK_EFUSEPL_VOL_VCCAUX_MAX_RAW_ULTRA (XSysMon_VoltageToRaw(XSK_EFUSEPL_VOL_VCCAUX_MAX_ULTRA))
#define XSK_EFUSEPL_TEMP_MIN_RAW_ULTRA (XSysMon_TemperatureToRaw(XSK_EFUSEPL_TEMP_MIN_ULTRA))
#define XSK_EFUSEPL_TEMP_MAX_RAW_ULTRA (XSysMon_TemperatureToRaw(XSK_EFUSEPL_TEMP_MAX_ULTRA))
#endif
/**
* Different voltage types that can be read from xAdc
*/
#define XSK_EFUSEPS_VPINT (1)
#define XSK_EFUSEPS_VPAUX (2)
#define XSK_EFUSEPS_VPDRO (3)
#define XSK_EFUSEPS_VINT (4)
#define XSK_EFUSEPS_VAUX (5)
#define XSK_EFUSE_DEBUG_GENERAL 0x00000001U /* general debug messages */
#if defined (XSK_EFUSE_DEBUG)
#define xeFUSE_dbg_current_types (XSK_EFUSE_DEBUG_GENERAL)
#else
#define xeFUSE_dbg_current_types 0U
#endif
#ifdef STDOUT_BASEADDRESS
#define xeFUSE_printf(type,...) \
if (((type) & xeFUSE_dbg_current_types) != 0U) {xil_printf (__VA_ARGS__); }
#else
#define xeFUSE_printf(type, ...)
#endif
#define XSK_GLOBAL_TIMER_BASE_ADDRESS (0xF8F00000U)
/**
* Global_Timer_Counter _Register0 (0xf8f00200)
*/
#define XSK_GLOBAL_TIMER_COUNT_REG_LOW (XSK_GLOBAL_TIMER_BASE_ADDRESS + 0x200U)
/**
* Global_Timer_Counter _Register1 (0xf8f00204)
*/
#define XSK_GLOBAL_TIMER_COUNT_REG_HIGH (XSK_GLOBAL_TIMER_BASE_ADDRESS + 0x204U)
/**
* Global_Timer_Control_Register (0xf8f00208)
*/
#define XSK_GLOBAL_TIMER_CTRL_REG (XSK_GLOBAL_TIMER_BASE_ADDRESS + 0x208U)
/**
* System Level Control Registers Start Addr
*/
#define XSK_SLCR_START_ADDRESS (0xF8000000U)
/**
* ARM PLL Control Register
*/
#define XSK_ARM_PLL_CTRL_REG (XSK_SLCR_START_ADDRESS + 0x100U)
/**
* ARM Clock Control Register
*/
#define XSK_ARM_CLK_CTRL_REG (XSK_SLCR_START_ADDRESS + 0x120U)
/**
* PL eFUSE aes key size in characters
*/
#define XSK_EFUSEPL_AES_KEY_STRING_SIZE (64U)
/**
* PL eFUSE user low key size in characters
*/
#define XSK_EFUSEPL_USER_LOW_KEY_STRING_SIZE (2U)
/**
* PL eFUSE user high key size in characters
*/
#define XSK_EFUSEPL_USER_HIGH_KEY_STRING_SIZE (6U)
/**
* AES Key size in Bytes
*/
#define XSK_EFUSEPL_AES_KEY_SIZE_IN_BYTES (32U)
/**
* 32 bit User Key size in Bytes
*/
#define XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES (4U)
/* 128 bit User key size in bytes */
#define XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES (16U)
/**
* AES Key size in Bits
*/
#define XSK_EFUSEPL_AES_KEY_SIZE_IN_BITS (256U)
/**
* User Low Key size in Bytes
*/
#define XSK_EFUSEPL_USER_LOW_KEY_SIZE_IN_BITS (8U)
/**
* User High Key size in Bytes
*/
#define XSK_EFUSEPL_USER_HIGH_KEY_SIZE_IN_BITS (24U)
/**
* Key length definition for RSA KEY Hash
*/
#define XSK_EFUSEPS_RSA_KEY_HASH_LEN_IN_BYTES (32U)
/**
* PS eFUSE RSA key Hash size in characters
*/
#define XSK_EFUSEPS_RSA_KEY_HASH_STRING_SIZE (64U)
/**
* Ultrascale Efuse PL RSA Key size in Bytes
*/
#define XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES (48U)
#define XSK_POLL_TIMEOUT 0xFFFFFFFFU
#define XSK_STRING_SIZE_2 (2U)
#define XSK_STRING_SIZE_6 (6U)
#define XSK_STRING_SIZE_8 (8U)
#define XSK_STRING_SIZE_64 (64U)
#define XSK_STRING_SIZE_96 (96U)
/************************** Variable Definitions ****************************/
typedef enum {
XSK_SLR_NUM_0,
XSK_SLR_NUM_1,
XSK_SLR_NUM_2,
XSK_SLR_NUM_3
}XSK_SlrNum;
typedef enum {
XSK_SLR_CONFIG_ORDER_0,
XSK_SLR_CONFIG_ORDER_1,
XSK_SLR_CONFIG_ORDER_2,
XSK_SLR_CONFIG_ORDER_3
}XSK_SlrCfgOrder;
typedef enum {
XSK_TARGET_MAX_1_SLRS = 1,
XSK_TARGET_MAX_2_SLRS,
XSK_TARGET_MAX_3_SLRS,
XSK_TARGET_MAX_4_SLRS
}XSK_MaxSlrs;
/**
* XADC Structure
*/
typedef struct
{
/**
* Current temperature
*/
u32 Temp;
/**
* Minimum temperature
*/
u32 TempMin;
/**
* Maximum temperature
*/
u32 TempMax;
/**
* Voltage type to read to select from VCCPINT, VCCPAUX, VCCPDRO
*/
u32 VType;
/**
* Current voltage of Vtype
*/
u32 V;
/**
* Minimum voltage of Vtype
*/
u32 VMin;
/**
* Maximum voltage of Vtype
*/
u32 VMax;
} XSKEfusePs_XAdc;
/**
@}
@endcond */
/**
* @addtogroup xilskey_plefuse_error_codes PL EFUSE error codes
* @{
*/
typedef enum {
XSK_EFUSEPL_ERROR_NONE = 0, /**< 0 <br>No error. */
/**
* @name EFUSE Read error codes
*/
XSK_EFUSEPL_ERROR_ROW_NOT_ZERO = 0x10,/**< 0x10 <br>Row is not zero. */
XSK_EFUSEPL_ERROR_READ_ROW_OUT_OF_RANGE,/**< 0x11 <br>Read Row is out
* of range. */
XSK_EFUSEPL_ERROR_READ_MARGIN_OUT_OF_RANGE,/**< 0x12 <br>Read Margin
* is out of range. */
XSK_EFUSEPL_ERROR_READ_BUFFER_NULL, /**< 0x13 <br>No buffer
* for read. */
XSK_EFUSEPL_ERROR_READ_BIT_VALUE_NOT_SET,/**< 0x14 <br>Read bit
* not set. */
XSK_EFUSEPL_ERROR_READ_BIT_OUT_OF_RANGE,/**< 0x15 <br>Read bit is out
* of range. */
XSK_EFUSEPL_ERROR_READ_TMEPERATURE_OUT_OF_RANGE,/**< 0x16 <br>Temperature
* obtained
* from XADC is out
* of range to read.*/
XSK_EFUSEPL_ERROR_READ_VCCAUX_VOLTAGE_OUT_OF_RANGE,/**< 0x17 <br>VCCAUX
* obtained
* from XADC is
* out of range to
* read. */
XSK_EFUSEPL_ERROR_READ_VCCINT_VOLTAGE_OUT_OF_RANGE,/**< 0x18 <br>VCCINT
* obtained
* from XADC is
* out of range to
* read. */
/**
* @name EFUSE Write error codes
*/
XSK_EFUSEPL_ERROR_WRITE_ROW_OUT_OF_RANGE,/**< 0x19 <br>To write row
* is out of range. */
XSK_EFUSEPL_ERROR_WRITE_BIT_OUT_OF_RANGE,/**< 0x1A <br>To read bit is
* out of range. */
XSK_EFUSEPL_ERROR_WRITE_TMEPERATURE_OUT_OF_RANGE,/**< 0x1B <br>To eFUSE
* write Temperature
* obtained from XADC
* is outof range. */
XSK_EFUSEPL_ERROR_WRITE_VCCAUX_VOLTAGE_OUT_OF_RANGE,
/**< 0x1C <br>To
* write eFUSE
* VCCAUX obtained
* from XADC is
* out of range.*/
XSK_EFUSEPL_ERROR_WRITE_VCCINT_VOLTAGE_OUT_OF_RANGE, /**< 0x1D <br>To
* write into
* eFUSE VCCINT
* obtained from
* XADC is out
* of range. */
/**
* @name EFUSE CNTRL error codes
*/
XSK_EFUSEPL_ERROR_FUSE_CNTRL_WRITE_DISABLED,/**< 0x1E <br>Fuse
* control write
* is disabled. */
XSK_EFUSEPL_ERROR_CNTRL_WRITE_BUFFER_NULL,/**< 0x1F <br>Buffer
* pointer that is
* supposed to
* contain control data
* is null.*/
/**
* @name EFUSE KEY error codes
*/
XSK_EFUSEPL_ERROR_NOT_VALID_KEY_LENGTH, /**< 0x20 <br>Key length
* invalid. */
XSK_EFUSEPL_ERROR_ZERO_KEY_LENGTH, /**< 0x21 <br>Key length zero. */
XSK_EFUSEPL_ERROR_NOT_VALID_KEY_CHAR, /**< 0x22 <br>Invalid key
* characters. */
XSK_EFUSEPL_ERROR_NULL_KEY, /**< 0x23 <br>Null key. */
/**
* @name SECURE KEY error codes
*/
XSK_EFUSEPL_ERROR_FUSE_SEC_WRITE_DISABLED, /**< 0x24 <br>Secure bits
* write is disabled. */
XSK_EFUSEPL_ERROR_FUSE_SEC_READ_DISABLED, /**< 0x25 <br>Secure bits
* reading is disabled.*/
XSK_EFUSEPL_ERROR_SEC_WRITE_BUFFER_NULL, /**< 0x26 <br>Buffer to write
* into secure block
* is NULL. */
XSK_EFUSEPL_ERROR_READ_PAGE_OUT_OF_RANGE, /**< 0x27 <br>Page is
* out of range. */
XSK_EFUSEPL_ERROR_FUSE_ROW_RANGE, /**< 0x28 <br>Row is out of range. */
XSK_EFUSEPL_ERROR_IN_PROGRAMMING_ROW, /**< 0x29 <br>Error programming
* fuse row.*/
XSK_EFUSEPL_ERROR_PRGRMG_ROWS_NOT_EMPTY, /**< 0x2A <br>Error when
* tried to program non Zero
* rows of eFUSE.*/
/* Error in Hw module */
XSK_EFUSEPL_ERROR_HWM_TIMEOUT = 0x80, /**< 0x80 <br>Error when hardware
* module is exceeded the time
* for programming eFUSE.*/
XSK_EFUSEPL_ERROR_USER_FUSE_REVERT = 0x90, /**< 0x90 <br>Error occurs
* when user
* requests to revert
* already programmed
* user eFUSE bit.*/
/**
* @name XSKEfusepl_Program_Efuse() error codes
*/
XSK_EFUSEPL_ERROR_KEY_VALIDATION = 0xF000, /**< 0xF000<br>Invalid
* key. */
XSK_EFUSEPL_ERROR_PL_STRUCT_NULL = 0x1000, /**< 0x1000<br>Null PL
* structure. */
XSK_EFUSEPL_ERROR_JTAG_SERVER_INIT = 0x1100, /**< 0x1100<br>JTAG server
* initialization
* error. */
XSK_EFUSEPL_ERROR_READING_FUSE_CNTRL = 0x1200, /**< 0x1200<br>Error
* reading fuse control. */
XSK_EFUSEPL_ERROR_DATA_PROGRAMMING_NOT_ALLOWED = 0x1300,
/**< 0x1300<br>Data programming not allowed. */
XSK_EFUSEPL_ERROR_FUSE_CTRL_WRITE_NOT_ALLOWED = 0x1400,
/**< 0x1400<br>Fuse control write is disabled.*/
XSK_EFUSEPL_ERROR_READING_FUSE_AES_ROW = 0x1500, /**< 0x1500<br>Error
* reading fuse
* AES row. */
XSK_EFUSEPL_ERROR_AES_ROW_NOT_EMPTY = 0x1600, /**< 0x1600<br>AES row
* is not empty. */
XSK_EFUSEPL_ERROR_PROGRAMMING_FUSE_AES_ROW = 0x1700, /**< 0x1700<br>
* Error programming fuse
* AES row. */
XSK_EFUSEPL_ERROR_READING_FUSE_USER_DATA_ROW = 0x1800,
/**< 0x1800<br>
* Error reading fuse
* user row. */
XSK_EFUSEPL_ERROR_USER_DATA_ROW_NOT_EMPTY = 0x1900,
/**< 0x1900<br>User row is not empty. */
XSK_EFUSEPL_ERROR_PROGRAMMING_FUSE_DATA_ROW = 0x1A00,
/**< 0x1A00<br>Error
* programming fuse
* user row. */
XSK_EFUSEPL_ERROR_PROGRAMMING_FUSE_CNTRL_ROW = 0x1B00,/**< 0x1B00<br>
* Error programming
* fuse control row. */
XSK_EFUSEPL_ERROR_XADC = 0x1C00, /**< 0x1C00<br>XADC error. */
XSK_EFUSEPL_ERROR_INVALID_REF_CLK= 0x3000U,/**< 0x3000<br>Invalid
* reference clock. */
XSK_EFUSEPL_ERROR_FUSE_SEC_WRITE_NOT_ALLOWED = 0x1D00,
/**< 0x1D00<br>Error in programming secure block. */
XSK_EFUSEPL_ERROR_READING_FUSE_STATUS = 0x1E00,/**< 0x1E00<br>Error in
* reading FUSE
* status. */
XSK_EFUSEPL_ERROR_FUSE_BUSY = 0x1F00, /**< 0x1F00<br>Fuse busy. */
XSK_EFUSEPL_ERROR_READING_FUSE_RSA_ROW = 0x2000, /**< 0x2000<br>Error
* in reading
* FUSE RSA block. */
XSK_EFUSEPL_ERROR_TIMER_INTIALISE_ULTRA = 0x2200, /**< 0x2200<br>Error
* in initiating
* Timer. */
XSK_EFUSEPL_ERROR_READING_FUSE_SEC = 0x2300, /**< 0x2300<br>Error in
* reading
* FUSE secure bits. */
XSK_EFUSEPL_ERROR_PRGRMG_FUSE_SEC_ROW = 0x2500, /**< 0x2500<br>Error
* in programming
* Secure bits of
* efuse. */
XSK_EFUSEPL_ERROR_PRGRMG_USER_KEY = 0x4000, /**< 0x4000<br>Error in
* programming 32
* bit user key. */
XSK_EFUSEPL_ERROR_PRGRMG_128BIT_USER_KEY = 0x5000,
/**< 0x5000<br>Error in
* programming 128 bit
* User key.*/
XSK_EFUSEPL_ERROR_PRGRMG_RSA_HASH = 0x8000 /**< 0x8000<br>Error in
* programming RSA hash. */
}XSKEfusePl_ErrorCodes;
/**
* @}
*/
/**
* @addtogroup xilskey_psefuse_error_codes PS EFUSE error codes
* @{
*/
typedef enum {
XSK_EFUSEPS_ERROR_NONE = 0, /**< 0<br>No error. */
/**
* @name EFUSE Read error codes
*/
XSK_EFUSEPS_ERROR_ADDRESS_XIL_RESTRICTED = 0x01, /**< 0x01<br>Address
* is restricted. */
XSK_EFUSEPS_ERROR_READ_TMEPERATURE_OUT_OF_RANGE, /**< 0x02<br>Temperature
* obtained from XADC
* is out of
* range. */
XSK_EFUSEPS_ERROR_READ_VCCPAUX_VOLTAGE_OUT_OF_RANGE,/**< 0x03<br>VCCAUX
* obtained from
* XADC is out of
* range. */
XSK_EFUSEPS_ERROR_READ_VCCPINT_VOLTAGE_OUT_OF_RANGE,/**< 0x04<br>VCCINT
* obtained from
* XADC is out of
* range. */
/**
* @name EFUSE Write error codes
*/
XSK_EFUSEPS_ERROR_WRITE_TEMPERATURE_OUT_OF_RANGE,/**< 0x05<br>
* Temperature
* obtained from
* XADC is out
* of range. */
XSK_EFUSEPS_ERROR_WRITE_VCCPAUX_VOLTAGE_OUT_OF_RANGE,/**< 0x06<br>VCCAUX
* obtained from
* XADC is out of
* range. */
XSK_EFUSEPS_ERROR_WRITE_VCCPINT_VOLTAGE_OUT_OF_RANGE,/**< 0x07<br>VCCINT
* obtained from
* XADC is out of
* range. */
XSK_EFUSEPS_ERROR_VERIFICATION, /**< 0x08<br>Verification
* error. */
XSK_EFUSEPS_ERROR_RSA_HASH_ALREADY_PROGRAMMED,/**< 0x09<br>RSA hash was
* already programmed. */
/**
* @name FUSE CNTRL error codes
*/
XSK_EFUSEPS_ERROR_CONTROLLER_MODE,/**< 0x0A<br>Controller mode error */
XSK_EFUSEPS_ERROR_REF_CLOCK,/**< 0x0B<br>Reference clock not between
* 20 to 60MHz */
XSK_EFUSEPS_ERROR_READ_MODE,/**< 0x0C<br>Not supported read mode */
/**
* @name XADC Error Codes
*/
XSK_EFUSEPS_ERROR_XADC_CONFIG,/**< 0x0D<br>XADC configuration error. */
XSK_EFUSEPS_ERROR_XADC_INITIALIZE,/**< 0x0E<br>XADC initialization
* error. */
XSK_EFUSEPS_ERROR_XADC_SELF_TEST,/**< 0x0F<br>XADC self-test failed. */
/**
* @name Utils Error Codes
*/
XSK_EFUSEPS_ERROR_PARAMETER_NULL,/**< 0x10<br>Passed parameter null. */
XSK_EFUSEPS_ERROR_STRING_INVALID,/**< 0x20<br>Passed string
* is invalid. */
XSK_EFUSEPS_ERROR_AES_ALREADY_PROGRAMMED,/**< 0x12<br>AES key is
* already programmed.*/
XSK_EFUSEPS_ERROR_SPKID_ALREADY_PROGRAMMED,/**< 0x13<br>SPK ID is
* already programmed. */
XSK_EFUSEPS_ERROR_PPK0_HASH_ALREADY_PROGRAMMED,/**< 0x14<br>PPK0 hash
* is already
* programmed. */
XSK_EFUSEPS_ERROR_PPK1_HASH_ALREADY_PROGRAMMED,/**< 0x15<br>PPK1 hash
* is already
* programmed. */
XSK_EFUSEPS_ERROR_IN_TBIT_PATTERN,/**< 0x16<br>Error in
* TBITS pattern . */
XSK_EFUSEPS_ERROR_PROGRAMMING = 0x00A0U,/**< 0x00A0<br>Error in
* programming eFUSE.*/
XSK_EFUSEPS_ERROR_PGM_NOT_DONE = 0X00A1,/**< 0x00A1<br>Program not done */
XSK_EFUSEPS_ERROR_READ = 0x00B0U,/**< 0x00B0<br>Error in reading. */
XSK_EFUSEPS_ERROR_BYTES_REQUEST = 0x00C0U, /**< 0x00C0<br>Error in
* requested byte count. */
XSK_EFUSEPS_ERROR_RESRVD_BITS_PRGRMG = 0x00D0U, /**< 0x00D0<br>Error in
* programming reserved bits. */
XSK_EFUSEPS_ERROR_ADDR_ACCESS = 0x00E0U, /**< 0x00E0<br>Error in
* accessing requested address. */
XSK_EFUSEPS_ERROR_READ_NOT_DONE = 0x00F0U,/**< 0x00F0<br>Read not done */
/**
* @name XSKEfuse_Write/Read()common error codes
*/
XSK_EFUSEPS_ERROR_PS_STRUCT_NULL=0x8100U,/**< 0x8100<br>PS structure
* pointer is null. */
XSK_EFUSEPS_ERROR_XADC_INIT=0x8200U,/**< 0x8200<br>XADC initialization
* error. */
XSK_EFUSEPS_ERROR_CONTROLLER_LOCK=0x8300U,/**< 0x8300<br>PS eFUSE
* controller is locked. */
XSK_EFUSEPS_ERROR_EFUSE_WRITE_PROTECTED=0x8400U,/**< 0x8400<br>PS eFUSE
* is write protected.*/
XSK_EFUSEPS_ERROR_CONTROLLER_CONFIG=0x8500U,/**< 0x8500<br>Controller
* configuration error. */
XSK_EFUSEPS_ERROR_PS_PARAMETER_WRONG=0x8600U,/**< 0x8600<br>PS eFUSE
* parameter is not
* TRUE/FALSE. */
/**
* @name XSKEfusePs_Write() error codes
*/
XSK_EFUSEPS_ERROR_WRITE_128K_CRC_BIT=0x9100U,/**< 0x9100<br>Error in
* enabling 128K CRC. */
XSK_EFUSEPS_ERROR_WRITE_NONSECURE_INITB_BIT=0x9200U,/**< 0x9200<br>Error
* in programming
* NON secure bit.
*/
XSK_EFUSEPS_ERROR_WRITE_UART_STATUS_BIT=0x9300U,/**< 0x9300<br>Error in
* writing UART
* status bit. */
XSK_EFUSEPS_ERROR_WRITE_RSA_HASH=0x9400U,/**< 0x9400<br>Error in
* writing RSA key. */
XSK_EFUSEPS_ERROR_WRITE_RSA_AUTH_BIT=0x9500U, /**< 0x9500<br>Error in
* enabling RSA
* authentication bit. */
XSK_EFUSEPS_ERROR_WRITE_WRITE_PROTECT_BIT=0x9600U,/**< 0x9600<br>Error in
* writing
* write-protect bit. */
XSK_EFUSEPS_ERROR_READ_HASH_BEFORE_PROGRAMMING=0x9700U, /**< 0x9700<br>
* Check RSA key before trying
* to program. */
XSK_EFUSEPS_ERROR_WRTIE_DFT_JTAG_DIS_BIT = 0x9800U,/**< 0x9800<br>Error
* in programming
* DFT JTAG disable
* bit. */
XSK_EFUSEPS_ERROR_WRTIE_DFT_MODE_DIS_BIT = 0x9900U,/**< 0x9900<br>Error
* in programming
* DFT MODE
* disable bit. */
XSK_EFUSEPS_ERROR_WRTIE_AES_CRC_LK_BIT = 0x9A00U,/**< 0x9A00<br>Error in
* enabling AES's CRC
* check lock. */
XSK_EFUSEPS_ERROR_WRTIE_AES_WR_LK_BIT = 0x9B00U,/**< 0x9B00<br>Error in
* programming AES
* write lock bit. */
XSK_EFUSEPS_ERROR_WRTIE_USE_AESONLY_EN_BIT = 0x9C00U,/**< 0x9C00<br>Error
* in programming
* use AES only
* bit. */
XSK_EFUSEPS_ERROR_WRTIE_BBRAM_DIS_BIT = 0x9D00U,/**< 0x9D00<br>Error in
* programming BBRAM
* disable bit. */
XSK_EFUSEPS_ERROR_WRTIE_PMU_ERR_DIS_BIT = 0x9E00U,/**< 0x9E00<br>Error
* in programming
* PMU error disable
* bit. */
XSK_EFUSEPS_ERROR_WRTIE_JTAG_DIS_BIT = 0x9F00U,/**< 0x9F00<br>Error in
* programming JTAG
* disable bit. */
/**
* @name XSKEfusePs_Read() error codes
*/
XSK_EFUSEPS_ERROR_READ_RSA_HASH=0xA100U,/**< 0xA100<br>Error in reading
* RSA key. */
XSK_EFUSEPS_ERROR_WRONG_TBIT_PATTERN = 0xA200U,/**< 0xA200<br>Error in
* programming TBIT
* pattern. */
XSK_EFUSEPS_ERROR_WRITE_AES_KEY = 0xA300U,/**< 0xA300<br>Error in
* programming AES key. */
XSK_EFUSEPS_ERROR_WRITE_SPK_ID = 0xA400U,/**< 0xA400<br>Error in
* programming SPK ID. */
XSK_EFUSEPS_ERROR_WRITE_USER_KEY = 0xA500U,/**< 0xA500<br>Error in
* programming USER key.*/
XSK_EFUSEPS_ERROR_WRITE_PPK0_HASH = 0xA600U,/**< 0xA600<br>Error in
* programming PPK0 hash. */
XSK_EFUSEPS_ERROR_WRITE_PPK1_HASH = 0xA700U,/**< 0xA700<br>Error in
* programming PPK1 hash.*/
/* Error in programmin user fuses */
XSK_EFUSEPS_ERROR_WRITE_USER0_FUSE = 0xC000U,/**< 0xC000<br>Error in
* programming USER 0 Fuses. */
XSK_EFUSEPS_ERROR_WRITE_USER1_FUSE = 0xC100U,/**< 0xC100<br>Error in
* programming USER 1 Fuses. */
XSK_EFUSEPS_ERROR_WRITE_USER2_FUSE = 0xC200U,/**< 0xC200<br>Error in
* programming USER 2 Fuses. */
XSK_EFUSEPS_ERROR_WRITE_USER3_FUSE = 0xC300U,/**< 0xC300<br>Error in
* programming USER 3 Fuses. */
XSK_EFUSEPS_ERROR_WRITE_USER4_FUSE = 0xC400U,/**< 0xC400<br>Error in
* programming USER 4 Fuses. */
XSK_EFUSEPS_ERROR_WRITE_USER5_FUSE = 0xC500U,/**< 0xC500<br>Error in
* programming USER 5 Fuses. */
XSK_EFUSEPS_ERROR_WRITE_USER6_FUSE = 0xC600U,/**< 0xC600<br>Error in
* programming USER 6 Fuses. */
XSK_EFUSEPS_ERROR_WRITE_USER7_FUSE = 0xC700U,/**< 0xC700<br>Error in
* programming USER 7 Fuses. */
XSK_EFUSEPS_ERROR_WRTIE_USER0_LK_BIT = 0xC800U,/**< 0xC800<br>Error in
* programming USER 0 fuses lock bit. */
XSK_EFUSEPS_ERROR_WRTIE_USER1_LK_BIT = 0xC900U,/**< 0xC900<br>Error in
* programming USER 1 fuses lock bit.*/
XSK_EFUSEPS_ERROR_WRTIE_USER2_LK_BIT = 0xCA00U,/**< 0xCA00<br>Error in
* programming USER 2 fuses lock bit.*/
XSK_EFUSEPS_ERROR_WRTIE_USER3_LK_BIT = 0xCB00U,/**< 0xCB00<br>Error in
* programming USER 3 fuses lock bit.*/
XSK_EFUSEPS_ERROR_WRTIE_USER4_LK_BIT = 0xCC00U,/**< 0xCC00<br>Error in
* programming USER 4 fuses lock bit.*/
XSK_EFUSEPS_ERROR_WRTIE_USER5_LK_BIT = 0xCD00U,/**< 0xCD00<br>Error in
* programming USER 5 fuses lock bit.*/
XSK_EFUSEPS_ERROR_WRTIE_USER6_LK_BIT = 0xCE00U,/**< 0xCE00<br>Error in
* programming USER 6 fuses lock bit.*/
XSK_EFUSEPS_ERROR_WRTIE_USER7_LK_BIT = 0xCF00U,/**< 0xCF00<br>Error in
* programming USER 7 fuses lock bit.*/
XSK_EFUSEPS_ERROR_WRTIE_PROG_GATE0_DIS_BIT = 0xD000U,/**< 0xD000<br>
* Error in programming PROG_GATE0
* disabling bit. */
XSK_EFUSEPS_ERROR_WRTIE_PROG_GATE1_DIS_BIT = 0xD100U,/**< 0xD100<br>
* Error in programming PROG_GATE1
* disabling bit. */
XSK_EFUSEPS_ERROR_WRTIE_PROG_GATE2_DIS_BIT = 0xD200U,/**< 0xD200<br>Error
* in programming PROG_GATE2
* disabling bit. */
XSK_EFUSEPS_ERROR_WRTIE_SEC_LOCK_BIT = 0xD300U,/**< 0xD300<br>Error in
* programming SEC_LOCK bit. */
XSK_EFUSEPS_ERROR_WRTIE_PPK0_WR_LK_BIT = 0xD400U,/**< 0xD400<br>Error in
* programming PPK0 write lock bit. */
XSK_EFUSEPS_ERROR_WRTIE_PPK0_RVK_BIT = 0xD500U,/**< 0xD500<br>Error in
* programming PPK0 revoke bit. */
XSK_EFUSEPS_ERROR_WRTIE_PPK1_WR_LK_BIT = 0xD600U,/**< 0xD600<br>Error in
* programming PPK1 write lock bit.*/
XSK_EFUSEPS_ERROR_WRTIE_PPK1_RVK_BIT = 0xD700U,/**< 0xD700<br>Error in
* programming PPK0 revoke bit.*/
XSK_EFUSEPS_ERROR_WRITE_PUF_SYN_INVLD = 0xD800U,/**< 0xD800<br>Error
* while programming the
* PUF syndrome invalidate bit.*/
XSK_EFUSEPS_ERROR_WRITE_PUF_SYN_WRLK = 0xD900U,/**< 0xD900<br>Error while
* programming Syndrome write
* lock bit. */
XSK_EFUSEPS_ERROR_WRITE_PUF_SYN_REG_DIS = 0xDA00U,/**< 0xDA00<br>Error
* while programming PUF syndrome
* register disable bit. */
XSK_EFUSEPS_ERROR_WRITE_PUF_RESERVED_BIT = 0xDB00U,/**< 0xDB00<br>Error
* while programming PUF reserved bit. */
XSK_EFUSEPS_ERROR_WRITE_LBIST_EN_BIT = 0xDC00U,/**< 0xDC00<br>Error
* while programming LBIST enable bit. */
XSK_EFUSEPS_ERROR_WRITE_LPD_SC_EN_BIT = 0xDD00U,/**< 0xDD00<br>Error while
* programming LPD SC enable bit. */
XSK_EFUSEPS_ERROR_WRITE_FPD_SC_EN_BIT = 0xDE00U,/**< 0xDE00<br>Error while
* programming FPD SC enable bit. */
XSK_EFUSEPS_ERROR_WRITE_PBR_BOOT_ERR_BIT = 0xDF00U,/**< 0xDF00<br>Error
* while programming PBR boot error bit. */
/* Error codes related to PUF */
XSK_EFUSEPS_ERROR_PUF_INVALID_REG_MODE = 0xE000U,/**< 0xE000<br>Error when
* PUF registration is requested
* with invalid registration mode. */
XSK_EFUSEPS_ERROR_PUF_REG_WO_AUTH = 0xE100U,/**< 0xE100<br>Error when
* write not allowed without
* authentication enabled. */
XSK_EFUSEPS_ERROR_PUF_REG_DISABLED = 0xE200U,/**< 0xE200<br>Error when
* trying to do PUF registration
* and when PUF registration is
* disabled. */
XSK_EFUSEPS_ERROR_PUF_INVALID_REQUEST = 0xE300U,/**< 0xE300<br>Error
* when an invalid mode is requested. */
XSK_EFUSEPS_ERROR_PUF_DATA_ALREADY_PROGRAMMED = 0xE400U,/**< 0xE400<br>
* Error when PUF is already programmed
* in eFUSE. */
XSK_EFUSEPS_ERROR_PUF_DATA_OVERFLOW = 0xE500U,/**< 0xE500<br>Error
* when an over flow occurs. */
XSK_EFUSEPS_ERROR_SPKID_BIT_CANT_REVERT = 0xE600U,/**< 0xE600<br>
* Already programmed SPKID bit
* cannot be reverted */
XSK_EFUSEPS_ERROR_PUF_DATA_UNDERFLOW = 0xE700U,/**< 0xE700<br>Error
* when an under flow occurs. */
XSK_EFUSEPS_ERROR_PUF_TIMEOUT = 0xE800U,/**< 0xE800<br>Error
* when an PUF generation timedout. */
XSK_EFUSEPS_ERROR_PUF_ACCESS = 0xE900,/**< 0xE900<br>Error
* when an PUF Access violation. */
XSK_EFUSEPS_ERROR_PUF_CHASH_ALREADY_PROGRAMMED = 0XEA00,/** 0xEA00<br>Error
* When PUF Chash already programmed
* in eFuse. */
XSK_EFUSEPS_ERROR_PUF_AUX_ALREADY_PROGRAMMED = 0XEB00,/** 0xEB00<br>Error
* When PUF AUX already programmed
* in eFuse. */
XSK_EFUSEPS_ERROR_CMPLTD_EFUSE_PRGRM_WITH_ERR = 0x10000U,/**< 0x10000<br>
* eFUSE programming is completed with
* temp and vol read errors. */
XSK_EFUSEPS_ERROR_CACHE_LOAD = 0x20000U,/**< 0x20000U<br>Error in
* re-loading CACHE. */
XSK_EFUSEPS_RD_FROM_EFUSE_NOT_ALLOWED = 0x30000U,/**< 0x30000U<br>Read
* from eFuse is
* not allowed. */
/* If requested FUSE is write protected */
XSK_EFUSEPS_ERROR_FUSE_PROTECTED = 0x00080000U,/**< 0x00080000
* <br>Requested eFUSE is write
* protected. */
/* If User requested to program USER FUSE to make Non-zero to 1 */
XSK_EFUSEPS_ERROR_USER_BIT_CANT_REVERT = 0x00800000U,/**< 0x00800000<br>
* Already programmed user FUSE bit
* cannot be reverted.*/
XSK_EFUSEPS_ERROR_BEFORE_PROGRAMMING = 0x08000000U,/**< 0x08000000U<br>Error
* occurred before
* programming. */
}XSKEfusePs_ErrorCodes;
/** @} */
/**
* @addtogroup xilskey_zmpsoc_ps_error_codes Zynq UltraScale+ MPSoC error codes
* @{
*/
typedef enum {
XSK_ZYNQMP_BBRAMPS_ERROR_NONE = 0U, /**< 0<br>No error. */
XSK_ZYNQMP_BBRAMPS_ERROR_IN_PRGRMG_ENABLE = 0x010U, /**< 0x010<br>If this
* error is occurred
* programming is not
* possible. */
XSK_ZYNQMP_BBRAMPS_ERROR_IN_ZEROISE = 0x20U, /**< 0x20<br>
* zeroize bbram is
* failed. */
XSK_ZYNQMP_BBRAMPS_ERROR_IN_CRC_CHECK = 0xB000U, /**< 0xB000<br>If this
* error is occurred
* programming is done
* but CRC
* check is failed. */
XSK_ZYNQMP_BBRAMPS_ERROR_IN_PRGRMG = 0xC000U, /**< 0xC000<br>
* programming of key
* is failed. */
XSK_ZYNQMP_BBRAMPS_ERROR_IN_WRITE_CRC = 0xE800U /**< 0xE800<br>
* error write CRC
* value. */
}XskZynqMp_Ps_Bbram_ErrorCodes;
/** @} */
/** @cond xilskey_internal
* @{
*/
/*
* For backward compatibility with old error codes
*/
#define XSK_EFUSEPS_ERROR_READ_VCCAUX_VOLTAGE_OUT_OF_RANGE XSK_EFUSEPS_ERROR_READ_VCCPAUX_VOLTAGE_OUT_OF_RANGE
#define XSK_EFUSEPS_ERROR_READ_VCCINT_VOLTAGE_OUT_OF_RANGE XSK_EFUSEPS_ERROR_READ_VCCPINT_VOLTAGE_OUT_OF_RANGE
#define XSK_EFUSEPS_ERROR_WRITE_VCCAUX_VOLTAGE_OUT_OF_RANGE XSK_EFUSEPS_ERROR_WRITE_VCCPAUX_VOLTAGE_OUT_OF_RANGE
#define XSK_EFUSEPS_ERROR_WRITE_VCCINT_VOLTAGE_OUT_OF_RANGE XSK_EFUSEPS_ERROR_WRITE_VCCPINT_VOLTAGE_OUT_OF_RANGE
#define Xilskey_CrcCalculation XilSKey_CrcCalculation
#define Xilskey_Timer_Intialise XilSKey_Timer_Intialise
#define XilSKey_Ceil Xil_Ceil
/*****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddress is the Xilinx base address of the eFuse or Bbram
* controller.
* @param RegOffset is the register offset of the register.
*
* @return The 32-bit value of the register.
*
* @note C-style signature:
* u32 XilSKey_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define XilSKey_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (u32)(RegOffset))
/*****************************************************************************/
/**
*
* This macro writes the value into the given register.
*
* @param BaseAddress is the Xilinx base address of the eFuse or Bbram
* controller.
* @param RegOffset is the register offset of the register.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note C-style signature:
* void XilSKey_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XilSKey_WriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32(((BaseAddress) + (u32)(RegOffset)), (u32)(Data))
/************************** Function Prototypes *****************************/
u32 XilSKey_EfusePs_XAdcInit (void );
#if defined (XSK_ZYNQ_ULTRA_MP_PLATFORM) && !defined (XSK_OVERRIDE_SYSMON_CFG)
u32 XilSKey_EfusePs_XAdcCfgValidate (void);
#endif
void XilSKey_EfusePs_XAdcReadTemperatureAndVoltage(XSKEfusePs_XAdc *XAdcInstancePtr);
u32 XilSKey_ZynqMp_EfusePs_Temp_Vol_Checks(void);
void XilSKey_Efuse_StartTimer(void);
u64 XilSKey_Efuse_GetTime(void);
void XilSKey_Efuse_SetTimeOut(volatile u64* t, u64 us);
u8 XilSKey_Efuse_IsTimerExpired(u64 t);
void XilSKey_Efuse_ConvertBitsToBytes(const u8 * Bits, u8 * Bytes, u32 Len);
void XilSKey_EfusePs_ConvertBytesToBits(const u8 * Bytes, u8 * Bits, u32 Len);
void XilSKey_EfusePs_ConvertBytesBeToLe(const u8 *Be, u8 *Le, u32 Len);
u32 XilSKey_Efuse_ValidateKey(const char *key, u32 len);
u32 XilSKey_Efuse_IsValidChar(const char *c);
/**
* Common functions
*/
u32 XilSKey_Efuse_ConvertStringToHexLE(const char * Str, u8 * Buf, u32 Len);
u32 XilSKey_Efuse_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len);
u32 XilSKey_Efuse_ValidateKey(const char *Key, u32 Len);
u32 XilSKey_Timer_Intialise(void);
u32 XilSKey_Efuse_ReverseHex(u32 Input);
void XilSKey_StrCpyRange(u8 *Src, u8 *Dst, u32 From, u32 To);
void XilSKey_GetSlrNum(u32 MasterSlr, u32 ConfigOrderIndex, u32 *SlrNum);
/** @}
@endcond */
/**
* @addtogroup xilskey_cmn_crc xilskey common file
* @{
*/
u32 XilSKey_CrcCalculation(u8 *Key);
u32 XilSkey_CrcCalculation_AesKey(u8 *Key);
/***************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* XILSKEY_UTILS_H */
/**@}*/
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/include/xilskey_eps_zynqmp.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xilskey_eps_zynqmp.h
* @addtogroup xilskey_zynqmp_efuse ZynqMP EFUSE PS
* @{
* @cond xilskey_internal
* @{
*
* Contains the function prototypes, defines and macros for ZynqMP efusePs
* functionality.
*
* @note None.
*
* </pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- --------------------------------------------------------
* 4.0 vns 10/01/15 First release
* vns 10/20/15 Modified secure control bits readback bits.
* 6.0 vns 07/18/16 Added separate User FUSEs programming feasibility
* Modified XilSKey_ZynqMp_EfusePs_ReadUserFuse
* prototype. Removed JTAG user code programming
* feature.Added XSK_ZYNQMP_SEC_PPK_INVLD_BITS_SET
* to check both PPK invalid bits are set or not,
* To check RSA authentication enable, defined
* XSK_ZYNQMP_SEC_RSA_15BITS_SET and
* XSK_ZYNQMP_SEC_RSA_2BITS_SET macros. Added all RSA
* enable bits to enum. Modified RSAenable variable type
* to u16.
* 6.2 vns 03/10/17 Added support for LBIST, LPD and FPD sc enable,
* PBR_BOOT_ERROR. Modified names of secure control
* bits UseAESOnly -> EncOnly, PMUError->ErrorDisable,
* PPK0Revoke->PPK0InVld and PPK1Revoke->PPK1InVld
* 6.6 vns 06/06/18 Added doxygen tags
* vns 09/18/18 Added APIs to support eFUSE programming from linux
* 6.7 arc 01/05/19 Fixed MISRA-C violations.
* 6.8 psl 07/30/19 Fixed MISRA-C violations.
* </pre>
*
*****************************************************************************/
#ifndef XILSKEY_EPS_ZYNQMP_H
#define XILSKEY_EPS_ZYNQMP_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xilskey_utils.h"
/************************** Constant Definitions *****************************/
/* Efuse read selection */
#define XSK_EFUSEPS_READ_FROM_CACHE 0U
#define XSK_EFUSEPS_READ_FROM_EFUSE 1U
/* Key length definitions for ZynqMP eFuse */
#define XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BYTES (32U)
#define XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES (4U)
#define XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES (48U)
#define XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BYTES (4U)
#define XSK_ZYNQMP_EFUSEPS_DNA_LEN_IN_BYTES (12U)
/* ZynqMP eFuse PS keys lengths in bits */
#define XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BITS (256U)
#define XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BITS (32U)
#define XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS (384U)
#define XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BITS (32U)
/* ZynqMP eFuse maximum bits in a row */
#define XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW (32U)
/* No of Registers allocated for PPK sha3 hash */
#define XSK_ZYNQMP_EFUSEPS_PPK_HASH_REG_NUM (12U)
#define XSK_ZYNQMP_EFUSEPS_USR_FUSE_REG_NUM (8U)
/* Row numbers of Efuse PS of Zynq MP */
#define XSK_ZYNQMP_EFUSEPS_USR_KEY_END_ROW (15U)
#define XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW (16U)
#define XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW (17U)
#define XSK_ZYNQMP_EFUSEPS_RESERVED_ROW (19U)
#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW (22U)
#define XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW (23U)
#define XSK_ZYNQMP_EFUSEPS_AES_KEY_START_ROW (24U)
#define XSK_ZYNQMP_EFUSEPS_AES_KEY_END_ROW (31U)
#define XSK_ZYNQMP_EFUSEPS_PUF_ROW_START (0U)
#define XSK_ZYNQMP_EFUSEPS_PUF_ROW_END (63U)
#define XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW (20U)
#define XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW (21U)
/* User Fuses Row numbers */
#define XSK_ZYNQMP_EFUSEPS_USR0_FUSE_ROW (8U)
#define XSK_ZYNQMP_EFUSEPS_USR1_FUSE_ROW (9U)
#define XSK_ZYNQMP_EFUSEPS_USR2_FUSE_ROW (10U)
#define XSK_ZYNQMP_EFUSEPS_USR3_FUSE_ROW (11U)
#define XSK_ZYNQMP_EFUSEPS_USR4_FUSE_ROW (12U)
#define XSK_ZYNQMP_EFUSEPS_USR5_FUSE_ROW (13U)
#define XSK_ZYNQMP_EFUSEPS_USR6_FUSE_ROW (14U)
#define XSK_ZYNQMP_EFUSEPS_USR7_FUSE_ROW (15U)
#define XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW (40U)
#define XSK_ZYNQMP_EFUSEPS_PPK0_SHA3_HASH_END_ROW (51U)
#define XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW (52U)
#define XSK_ZYNQMP_EFUSEPS_PPK1_SHA3_HASH_END_ROW (63U)
#define XSK_ZYNQMP_EFUSEPS_TBITS_ROW (0U)
#define XSK_ZYNQMP_EFUSEPS_TBITS_MASK (0xFU)
#define XSK_ZYNQMP_EFUSEPS_TBITS_SHIFT (28U)
#define XSK_ZYNQMP_EFUSEPS_CRC_AES_ZEROS (0x6858A3D5U)
/* eFuse Offset = efuse row number * 4(that is sizeof(row))
*/
#define XSK_ZYNQMP_EFUSEPS_AES_KEY_OFFSET \
(XSK_ZYNQMP_EFUSEPS_AES_KEY_START_ROW << 2U)
/* User fuses*/
#define XSK_ZYNQMP_EFUSEPS_USR0_FUSE (0U)
#define XSK_ZYNQMP_EFUSEPS_USR1_FUSE (1U)
#define XSK_ZYNQMP_EFUSEPS_USR2_FUSE (2U)
#define XSK_ZYNQMP_EFUSEPS_USR3_FUSE (3U)
#define XSK_ZYNQMP_EFUSEPS_USR4_FUSE (4U)
#define XSK_ZYNQMP_EFUSEPS_USR5_FUSE (5U)
#define XSK_ZYNQMP_EFUSEPS_USR6_FUSE (6U)
#define XSK_ZYNQMP_EFUSEPS_USR7_FUSE (7U)
#define XSK_EFUSEPS_TPRGM_VALUE \
(((5.0f) * (XSK_ZYNQMP_EFUSEPS_PS_REF_CLK_FREQ)) / (1000000.0f))
#define XSK_EFUSEPS_TRD_VALUE \
(((15.0f) * (XSK_ZYNQMP_EFUSEPS_PS_REF_CLK_FREQ)) / (100000000.0f))
#define XSK_EFUSEPS_TSUHPS_VALUE \
(((67.0f) * (XSK_ZYNQMP_EFUSEPS_PS_REF_CLK_FREQ)) / (1000000000.0f))
#define XSK_EFUSEPS_TSUHPSCS_VALUE \
(((46.0f) * (XSK_ZYNQMP_EFUSEPS_PS_REF_CLK_FREQ)) / (1000000000.0f))
#define XSK_EFUSEPS_TSUHCS_VALUE \
(((30.0f) * (XSK_ZYNQMP_EFUSEPS_PS_REF_CLK_FREQ)) / (1000000000.0f))
/* Timer related macros */
#define XilSKey_ZynqMp_EfusePs_Tprgrm() \
Xil_Ceil(XSK_EFUSEPS_TPRGM_VALUE)
#define XilSKey_ZynqMp_EfusePs_Trd() \
Xil_Ceil(XSK_EFUSEPS_TRD_VALUE)
#define XilSKey_ZynqMp_EfusePs_TsuHPs() \
Xil_Ceil(XSK_EFUSEPS_TSUHPS_VALUE)
#define XilSKey_ZynqMp_EfusePs_TsuHPsCs() \
Xil_Ceil(XSK_EFUSEPS_TSUHPSCS_VALUE)
#define XilSKey_ZynqMp_EfusePs_TsuHCs() \
Xil_Ceil(XSK_EFUSEPS_TSUHCS_VALUE)
#define XSK_ZYNQMP_SEC_PPK_INVLD_BITS_SET (0x3U)
/**< If PPK invalid bits are set */
/* For Silicon from 3.0 version */
#define XSK_ZYNQMP_SEC_RSA_15BITS_SET (0x7FFF)
/**< If RSA authentication bits are set */
/* For Silicon before 3.0 version */
#define XSK_ZYNQMP_SEC_RSA_2BITS_SET (0x3U)
/* For any of secure control bits which has 3 bits */
#define XSK_ZYNQMP_SEC_ALL_3BITS_SET (0x7U)
/* For any of secure control bits which has 3 bits */
#define XSK_ZYNQMP_SEC_ALL_16BITS_SET (0xFFFFU)
#define XSK_ZYNQMP_EFUSEPS_SECTRL_BIT_SHIFT 0x1U
/**< Shift macro for SEC_CTRL
* if it has 2 bits */
#define XSK_EFUSEPS_OFFSET_MASK (0xFFU)
#define XSK_EFUSEPS_ONE_WORD (1U)
#define XSK_EFUSEPS_BYTES_IN_WORD (4U)
/** @name efuse types
* @{
*/
typedef enum {
XSK_ZYNQMP_EFUSEPS_EFUSE_0,
XSK_ZYNQMP_EFUSEPS_EFUSE_2 = 2U,
XSK_ZYNQMP_EFUSEPS_EFUSE_3 = 3U
}XskEfusePs_Type;
/*@}*/
/** @name efuse secure control bits
* @{
*/
typedef enum {
XSK_ZYNQMP_EFUSEPS_SEC_AES_RDLK,
XSK_ZYNQMP_EFUSEPS_SEC_AES_WRLK,
XSK_ZYNQMP_EFUSEPS_SEC_ENC_ONLY,
XSK_ZYNQMP_EFUSEPS_SEC_BRAM_DIS,
XSK_ZYNQMP_EFUSEPS_SEC_ERR_DIS,
XSK_ZYNQMP_EFUSEPS_SEC_JTAG_DIS,
XSK_ZYNQMP_EFUSEPS_SEC_DFT_DIS,
XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE0,
XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE1,
XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE2,
XSK_ZYNQMP_EFUSEPS_SEC_LOCK,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT1,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT2,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT3,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT4,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT5,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT6,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT7,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT8,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT9,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT10,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT11,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT12,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT13,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT14,
XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT15,
XSK_ZYNQMP_EFUSEPS_SEC_PPK0_WRLK,
XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT1,
XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT2,
XSK_ZYNQMP_EFUSEPS_SEC_PPK1_WRLK,
XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT1,
XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT2
}XskEfusePS_SecCtrlBits;
/*@}*/
/** @name efuse misc user control bits
* @{
*/
typedef enum {
XSK_ZYNQMP_EFUSEPS_USR_WRLK_0,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_1,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_2,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_3,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_4,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_5,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_6,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_7,
XSK_ZYNQMP_EFUSEPS_LBIST_EN = 10,
XSK_ZYNQMP_EFUSEPS_LPD_SC_EN_0,
XSK_ZYNQMP_EFUSEPS_LPD_SC_EN_1,
XSK_ZYNQMP_EFUSEPS_LPD_SC_EN_2,
XSK_ZYNQMP_EFUSEPS_FPD_SC_EN_0,
XSK_ZYNQMP_EFUSEPS_FPD_SC_EN_1,
XSK_ZYNQMP_EFUSEPS_FPD_SC_EN_2,
}XskEfusePS_MiscUserBits;
/*@}*/
/** @name efuse PBR boot error bits
* @{
*/
typedef enum {
XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_0,
XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_1,
XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_2
}XskEfusePS_PbrBootErrBits;
/*@}*/
/**
*
* This typedef contains secure control features of efusePs
*/
typedef struct {
/* Secure and control bits */
u8 AesKeyRead;
u8 AesKeyWrite;
u8 EncOnly;
u8 BbramDisable;
u8 ErrorDisable;
u8 JtagDisable;
u8 DFTDisable;
u8 ProgGate;
u8 SecureLock;
u16 RSAEnable;
u8 PPK0WrLock;
u8 PPK0InVld;
u8 PPK1WrLock;
u8 PPK1InVld;
u8 PbrBootErr;
/* User control bits */
u8 UserWrLk0;
u8 UserWrLk1;
u8 UserWrLk2;
u8 UserWrLk3;
u8 UserWrLk4;
u8 UserWrLk5;
u8 UserWrLk6;
u8 UserWrLk7;
u8 LBistEn;
u8 FpdScEn;
u8 LpdScEn;
/* Reserved for Xilinx internal use */
u16 Reserved1;
u16 Reserved2;
} XilSKey_SecCtrlBits;
/*@}*/
/**
* XilSKey_ZynqMpEPs is the PS eFUSE driver instance. Using this
* structure, user can define the eFUSE bits of Zynq MP ultrascale to be
* blown.
*/
typedef struct {
XilSKey_SecCtrlBits PrgrmgSecCtrlBits;
/* For writing into eFuse */
u8 PrgrmAesKey;
u8 PrgrmPpk0Hash;
u8 PrgrmPpk1Hash;
u8 PrgrmSpkID;
u8 PrgrmUser0Fuse;
u8 PrgrmUser1Fuse;
u8 PrgrmUser2Fuse;
u8 PrgrmUser3Fuse;
u8 PrgrmUser4Fuse;
u8 PrgrmUser5Fuse;
u8 PrgrmUser6Fuse;
u8 PrgrmUser7Fuse;
u8 AESKey[XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BYTES];
u8 User0Fuses[XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES];
u8 User1Fuses[XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES];
u8 User2Fuses[XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES];
u8 User3Fuses[XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES];
u8 User4Fuses[XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES];
u8 User5Fuses[XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES];
u8 User6Fuses[XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES];
u8 User7Fuses[XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES];
u8 Ppk0Hash[XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES];
u8 Ppk1Hash[XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES];
u8 SpkId[XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BYTES];
XilSKey_SecCtrlBits ReadBackSecCtrlBits;
u8 IntialisedTimer;
}XilSKey_ZynqMpEPs;
/**
* XilSKey_Efuse is the eFUSE access structure. Using this
* structure, user can request the eFUSE access.
*/
typedef struct {
u64 Src; /**< Address of Data buffer */
u32 Size; /**< Size in words */
u32 Offset; /**< offset */
u32 Flag; /**< Flag - 0 : to read efuse and Flag - 1 : to write efuse */
}XilSKey_Efuse;
/***************** Macros (Inline Functions) Definitions *******************/
/***************************************************************************/
/**
* This macro is used to Unlock the eFuse controller.
*
* @return None
*
* @note None
*
****************************************************************************/
#define XilSKey_ZynqMp_EfusePs_CtrlrUnLock() \
(XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \
XSK_ZYNQMP_EFUSEPS_WR_LOCK_OFFSET, \
XSK_ZYNQMO_EFUSEP_WR_UNLOCK_VALUE))
/***************************************************************************/
/**
* This macro is used to Lock the eFuse controller.
*
* @return None
*
* @note None
*
****************************************************************************/
#define XilSKey_ZynqMp_EfusePs_CtrlrLock() \
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \
XSK_ZYNQMP_EFUSEPS_WR_LOCK_OFFSET, \
XSK_ZYNQMP_EFUSEPS_WR_LOCK_RSTVAL)
/***************************************************************************/
/**
* This macro is used to tell the lock status of eFuse controller.
*
* @return
* - TRUE if controller is locked
* - FALSE if controller is Unlocked
*
* @note None
*
****************************************************************************/
#define XilSKey_ZynqMp_EfusePs_CtrlrLockStatus() \
(((XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \
XSK_ZYNQMP_EFUSEPS_WR_LOCK_OFFSET)) != 0U) ? 1U : 0U)
/***************************************************************************/
/**
* This macro is used to tells the status of eFuse controller.
*
* @return
* - TRUE if controller is locked
* - FALSE if controller is Unlocked
*
* @note None
*
****************************************************************************/
#define XilSKey_ZynqMp_EfusePs_Status() \
(XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \
XSK_ZYNQMP_EFUSEPS_STS_OFFSET))
/***************************************************************************/
/**
* This macro enables the programming of efuse
*
* @return None
*
* @note None
*
****************************************************************************/
#define XilSKey_ZynqMp_EfusePS_PrgrmEn() \
(XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \
XSK_ZYNQMP_EFUSEPS_CFG_OFFSET, \
(XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \
XSK_ZYNQMP_EFUSEPS_CFG_OFFSET) | (u32)XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_MASK)))
/***************************************************************************/
/**
* This macro disables programming of efuse
*
* @return None.
*
* @note None
*
****************************************************************************/
#define XilSKey_ZynqMp_EfusePS_PrgrmDisable() \
(XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \
XSK_ZYNQMP_EFUSEPS_CFG_OFFSET, \
(XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \
XSK_ZYNQMP_EFUSEPS_CFG_OFFSET) & \
(~XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_MASK))))
/** @}
@endcond */
/****************************Prototypes***************************************/
/* Ps eFuse interface functions of Zynq MP */
u32 XilSKey_ZynqMp_EfusePs_CheckAesKeyCrc(u32 CrcValue);
u32 XilSKey_ZynqMp_EfusePs_ReadUserFuse(u32 *UseFusePtr, u8 UserFuse_Num,
u8 ReadOption);
u32 XilSKey_ZynqMp_EfusePs_ReadPpk0Hash(u32 *Ppk0Hash, u8 ReadOption);
u32 XilSKey_ZynqMp_EfusePs_ReadPpk1Hash(u32 *Ppk1Hash, u8 ReadOption);
u32 XilSKey_ZynqMp_EfusePs_ReadSpkId(u32 *SpkId, u8 ReadOption);
void XilSKey_ZynqMp_EfusePs_ReadDna(u32 *DnaRead);
u32 XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits(
XilSKey_SecCtrlBits *ReadBackSecCtrlBits, u8 ReadOption);
u32 XilSKey_ZynqMp_EfusePs_CacheLoad(void);
u32 XilSKey_ZynqMp_EfusePs_Write(XilSKey_ZynqMpEPs *InstancePtr);
u32 XilSkey_ZynqMpEfuseAccess(const u32 AddrHigh, const u32 AddrLow);
#ifdef __cplusplus
}
#endif
#endif /* XILSKEY_EPS_ZYNQMP_H */
/**@}*/
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_ipi_manager.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_ipi_manager.h"
/**
* This file provides a framework for modules to send and receive IPI messages
* PMU IPI-0 is used for communication initiated by other master.
* PMU IPI-1 is used for communication initiated by PMU.
*
* Currently this framework supports for checking/embedding IPI ID of a module.
* IPI ID is the MSB 16-bits of the first word in pay load.
* Depending on the application requirements, more features like CheckSum,
* Message Sequencing etc can be added.
*/
/* Instance of IPI Driver */
static XIpiPsu Ipi0Inst, Ipi1Inst;
static XIpiPsu *Ipi0InstPtr = &Ipi0Inst;
static XIpiPsu *Ipi1InstPtr = &Ipi1Inst;
u32 IpiMaskList[XPFW_IPI_MASK_COUNT] = {0U};
#ifdef ENABLE_IPI_CRC
#define XPFW_IPI_W0_TO_W6_SIZE 28U
#endif
s32 XPfw_IpiManagerInit(void)
{
s32 Status;
XIpiPsu_Config *Ipi0CfgPtr, *Ipi1CfgPtr;
u32 i;
/* Load Config for PMU IPI-0 */
Ipi0CfgPtr = XIpiPsu_LookupConfig(XPAR_XIPIPSU_0_DEVICE_ID);
if (Ipi0CfgPtr == NULL) {
Status = XST_FAILURE;
goto Done;
}
/* Load Config for PMU IPI-1 */
Ipi1CfgPtr = XIpiPsu_LookupConfig(XPAR_XIPIPSU_1_DEVICE_ID);
if (Ipi1CfgPtr == NULL) {
Status = XST_FAILURE;
goto Done;
}
/* Init Mask Lists */
for (i = 0U; i < XPFW_IPI_MASK_COUNT; i++) {
IpiMaskList[i] = Ipi0CfgPtr->TargetList[i].Mask;
}
/* Initialize the Instance pointer of IPI-0 channel */
Status = XIpiPsu_CfgInitialize(Ipi0InstPtr, Ipi0CfgPtr,
Ipi0CfgPtr->BaseAddress);
if (XST_SUCCESS != Status) {
return Status;
}
/* Initialize the Instance pointer of IPI-1 channel */
Status = XIpiPsu_CfgInitialize(Ipi1InstPtr, Ipi1CfgPtr,
Ipi1CfgPtr->BaseAddress);
if (XST_SUCCESS != Status) {
return Status;
}
/* Enable IPI-0 and IPI-1 from all Masters */
for (i = 0U; i < XPFW_IPI_MASK_COUNT; i++) {
XIpiPsu_InterruptEnable(Ipi0InstPtr,
Ipi0CfgPtr->TargetList[i].Mask);
XIpiPsu_InterruptEnable(Ipi1InstPtr,
Ipi1CfgPtr->TargetList[i].Mask);
}
Done:
return Status;
}
s32 XPfw_IpiWriteMessage(const XPfw_Module_t *ModPtr, u32 DestCpuMask, u32 *MsgPtr, u32 MsgLen)
{
s32 Status;
if ((ModPtr == NULL) || (MsgPtr == NULL)) {
Status = XST_FAILURE;
goto Done;
}
MsgPtr[0] = (MsgPtr[0] & 0x0000FFFFU) | ((u32)ModPtr->IpiId << 16U);
#ifdef ENABLE_IPI_CRC
/* For CRC, IPI message should have max allowed length i.e.,8 words */
MsgLen = XPFW_IPI_MAX_MSG_LEN;
/*
* Note : The last word MsgPtr[7] in IPI Msg is reserved for CRC.
* This is only for safety applications.
*/
MsgPtr[7] = XPfw_CalculateCRC((u32)MsgPtr, XPFW_IPI_W0_TO_W6_SIZE);
#endif
Status = XIpiPsu_WriteMessage(Ipi1InstPtr, DestCpuMask, MsgPtr, MsgLen,
XIPIPSU_BUF_TYPE_MSG);
Done:
return Status;
}
s32 XPfw_IpiWriteResponse(const XPfw_Module_t *ModPtr, u32 DestCpuMask, u32 *MsgPtr, u32 MsgLen)
{
s32 Status;
if ((ModPtr == NULL) || (MsgPtr == NULL)) {
Status = XST_FAILURE;
goto Done;
}
MsgPtr[0] = (MsgPtr[0] & 0x0000FFFFU) | ((u32)ModPtr->IpiId << 16U);
#ifdef ENABLE_IPI_CRC
/* For CRC, IPI message should have max allowed length i.e.,8 words */
MsgLen = XPFW_IPI_MAX_MSG_LEN;
/*
* Note : The last word MsgPtr[7] in IPI Msg is reserved for CRC.
* This is only for safety applications.
*/
MsgPtr[7] = XPfw_CalculateCRC((u32)MsgPtr, XPFW_IPI_W0_TO_W6_SIZE);
#endif
Status = XIpiPsu_WriteMessage(Ipi0InstPtr, DestCpuMask, MsgPtr, MsgLen,
XIPIPSU_BUF_TYPE_RESP);
Done:
return Status;
}
s32 XPfw_IpiReadMessage(u32 SrcCpuMask, u32 *MsgPtr, u32 MsgLen)
{
s32 Status = XST_FAILURE;
u32 RespBuf[XPFW_IPI_MAX_MSG_LEN] = {0};
if (MsgPtr == NULL) {
Status = XST_FAILURE;
goto Done;
}
/* Read Entire Message to Buffer */
Status = XIpiPsu_ReadMessage(Ipi0InstPtr, SrcCpuMask, MsgPtr, MsgLen,
XIPIPSU_BUF_TYPE_MSG);
#ifdef ENABLE_IPI_CRC
if (XST_SUCCESS != Status) {
goto Done;
}
/* For CRC, IPI message should have max allowed length i.e.,8 words */
if (XPFW_IPI_MAX_MSG_LEN != MsgLen) {
Status = XST_FAILURE;
goto Done;
}
/*
* Note : The last word MsgPtr[7] in IPI Msg is reserved for CRC.
* Compute the CRC and compare.
* This is only for safety applications.
*/
if (MsgPtr[7] != XPfw_CalculateCRC((u32)MsgPtr, XPFW_IPI_W0_TO_W6_SIZE)) {
/* Write error occurrence to PERS register and trigger FW Error1 */
XPfw_RMW32(PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5, IPI_CRC_ERROR_OCCURRED,
IPI_CRC_ERROR_OCCURRED);
XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK);
XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
0x0U);
XPfw_Printf(DEBUG_ERROR, "ERROR: IPI buffer CRC mismatch\r\n");
Status = XST_FAILURE;
goto Done;
}
#endif
Done:
/* Send response for failure status */
if (XST_SUCCESS != Status) {
RespBuf[0] = Status;
#ifdef ENABLE_IPI_CRC
RespBuf[7] = XPfw_CalculateCRC((u32)RespBuf, XPFW_IPI_W0_TO_W6_SIZE);
#endif
Status = XIpiPsu_WriteMessage(Ipi0InstPtr, SrcCpuMask, RespBuf,
XPFW_IPI_MAX_MSG_LEN, XIPIPSU_BUF_TYPE_RESP);
}
return Status;
}
s32 XPfw_IpiReadResponse(const XPfw_Module_t *ModPtr, u32 SrcCpuMask, u32 *MsgPtr, u32 MsgLen)
{
s32 Status = XST_FAILURE;
u32 MsgHeader = 0U;
if ((ModPtr == NULL) || (MsgPtr == NULL)) {
Status = XST_FAILURE;
goto Done;
}
/* Read the first word */
Status = XIpiPsu_ReadMessage(Ipi1InstPtr, SrcCpuMask, &MsgHeader, 1U,
XIPIPSU_BUF_TYPE_RESP);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto Done;
}
/* Check if IPI Id matches the upper 16 bits of first word*/
if ((MsgHeader >> 16) != ModPtr->IpiId) {
Status = XST_FAILURE;
goto Done;
}
/* Read Entire Message to Buffer */
Status = XIpiPsu_ReadMessage(Ipi1InstPtr, SrcCpuMask, MsgPtr, MsgLen,
XIPIPSU_BUF_TYPE_RESP);
#ifdef ENABLE_IPI_CRC
/* For CRC, IPI message should have max allowed length i.e.,8 words */
if (XPFW_IPI_MAX_MSG_LEN != MsgLen) {
Status = XST_FAILURE;
goto Done;
}
/*
* Note : The last word MsgPtr[7] in IPI Msg is reserved for CRC.
* Compute the CRC and compare.
* This is only for safety applications.
*/
if (MsgPtr[7] != XPfw_CalculateCRC((u32)MsgPtr, XPFW_IPI_W0_TO_W6_SIZE)) {
/* Write error occurrence to PERS register and trigger FW Error1 */
XPfw_RMW32(PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5, IPI_CRC_ERROR_OCCURRED,
IPI_CRC_ERROR_OCCURRED);
XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK);
XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
0x0U);
XPfw_Printf(DEBUG_ERROR, "ERROR: IPI buffer CRC mismatch\r\n");
Status = XST_FAILURE;
goto Done;
}
#endif
Done:
return Status;
}
inline s32 XPfw_IpiTrigger(u32 DestCpuMask)
{
return XIpiPsu_TriggerIpi(Ipi1InstPtr, DestCpuMask);
}
inline s32 XPfw_IpiPollForAck(u32 DestCpuMask, u32 TimeOutCount)
{
return XIpiPsu_PollForAck(Ipi1InstPtr, DestCpuMask, TimeOutCount);
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_binding.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* Implementations of the functions to be used for integrating power
* management (PM) within PMU firmware.
*********************************************************************/
#include "pm_binding.h"
#include "pm_defs.h"
#include "pm_common.h"
#include "pm_proc.h"
#include "pm_core.h"
#include "pm_notifier.h"
#include "pm_power.h"
#include "pm_gic_proxy.h"
#include "pm_requirement.h"
#include "pm_extern.h"
#include "pm_usb.h"
#include "pm_hooks.h"
/* All GIC wakes in GPI1 */
#define PMU_IOMODULE_GPI1_GIC_WAKES_ALL_MASK \
(PMU_IOMODULE_GPI1_ACPU_0_WAKE_MASK | \
PMU_IOMODULE_GPI1_ACPU_1_WAKE_MASK | \
PMU_IOMODULE_GPI1_ACPU_2_WAKE_MASK | \
PMU_IOMODULE_GPI1_ACPU_3_WAKE_MASK | \
PMU_IOMODULE_GPI1_R5_0_WAKE_MASK | \
PMU_IOMODULE_GPI1_R5_1_WAKE_MASK)
#define PMU_IOMODULE_GPI1_MIO_WAKE_ALL_MASK \
(PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK | \
PMU_IOMODULE_GPI1_MIO_WAKE_1_MASK | \
PMU_IOMODULE_GPI1_MIO_WAKE_2_MASK | \
PMU_IOMODULE_GPI1_MIO_WAKE_3_MASK | \
PMU_IOMODULE_GPI1_MIO_WAKE_4_MASK | \
PMU_IOMODULE_GPI1_MIO_WAKE_5_MASK)
/**
* XPfw_PmInit() - initializes PM firmware
*
* @note Call on startup to initialize PM firmware.
*/
void XPfw_PmInit(void)
{
#ifdef ENABLE_POS
u32 bootType = PmHookGetBootType();
/* Call user hook for Power Off Suspend initialization */
PmHookInitPowerOffSuspend();
#else
u32 bootType = PM_COLD_BOOT;
#endif
PmInfo("Power Management Init\r\n");
if (bootType == PM_COLD_BOOT) {
PmMasterDefaultConfig();
PmNodeConstruct();
}
}
/**
* XPfw_PmIpiHandler() - Call from IPI interrupt handler to process PM API call
* @IsrMask IPI's ISR register value. Needed to determine the source master
*
* @Payload Pointer to IPI Payload
*
* @Len Size of the payload in words
*
* @return Status of the processing IPI
* - XST_INVALID_PARAM if input parameters have invalid value
* - XST_SUCCESS otherwise
* - Note that if request is processed, firmware is not receiving any
* status of processing information. Processing status is returned to
* the master which initiated communication through IPI.
*
*/
s32 XPfw_PmIpiHandler(const u32 IsrMask, const u32* Payload, u8 Len)
{
s32 status = XST_SUCCESS;
PmMaster* master = PmGetMasterByIpiMask(IsrMask);
if ((NULL == Payload) || (NULL == master) || (Len < PAYLOAD_ELEM_CNT)) {
/* Never happens if IPI irq handler is implemented correctly */
PmErr("Unknown IPI %lu\r\n", IsrMask);
status = XST_INVALID_PARAM;
goto done;
}
PmProcessRequest(master, Payload);
done:
return status;
}
/**
* XPfw_PmWfiHandler() - Call from GPI2 interrupt handler to process sleep req
* @srcMask Value read from GPI2 register which determines master requestor
*
* @return Status of triggering sleep for a processor (XST_INVALID_PARAM if
* processor cannot be determined by srcMask, status of performing
* sleep operation otherwise)
*
* @note Call from GPI2 interrupt routine to process sleep request. Must not
* clear GPI2 interrupt before this function returns.
*/
s32 XPfw_PmWfiHandler(const u32 srcMask)
{
s32 status;
PmProc *proc = PmGetProcByWfiStatus(srcMask);
if (NULL == proc) {
PmErr("Unknown processor 0x%lx\r\n", srcMask);
status = XST_INVALID_PARAM;
goto done;
}
status = PmProcFsm(proc, PM_PROC_EVENT_SLEEP);
done:
return status;
}
/**
* XPfw_PmWakeHandler() - Call from GPI1 interrupt to process wake request
* @srcMask Value read from GPI1 register which determines interrupt source
*
* @return Status of performing wake-up (XST_INVALID_PARAM if wake is a
* processor wake event but processor is not found, status of
* performing wake otherwise)
*
* @note Call from GPI1 interrupt routine to process wake request. Must not
* clear GPI1 interrupt before this function returns.
* If the wake source is one of GIC wakes, source of the interrupt
* (peripheral that actually generated interrupt to GIC) cannot be
* determined, and target should be immediately woken-up (target is
* processor whose GIC wake bit is set in srcMask). If the wake is the
* FPD GIC Proxy interrupt, the APU needs to be woken up.
*/
s32 XPfw_PmWakeHandler(const u32 srcMask)
{
s32 status = XST_INVALID_PARAM;
#if defined(PMU_MIO_INPUT_PIN) && (PMU_MIO_INPUT_PIN >= 0U) \
&& (PMU_MIO_INPUT_PIN <= 5U)
if ((PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK << PMU_MIO_INPUT_PIN) == srcMask) {
PmShutdownInterruptHandler();
return XST_SUCCESS;
}
#endif
if (0U != (PMU_IOMODULE_GPI1_GIC_WAKES_ALL_MASK & srcMask)) {
/* Processor GIC wake */
PmProc* proc = PmProcGetByWakeMask(srcMask);
if ((NULL != proc) && (NULL != proc->master)) {
status = PmMasterWakeProc(proc);
} else {
status = XST_INVALID_PARAM;
}
} else if (0U != (PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_MASK & srcMask)) {
status = PmMasterWake(&pmMasterApu_g);
} else if (0U != (PMU_IOMODULE_GPI1_MIO_WAKE_ALL_MASK & srcMask)) {
status = PmExternWakeMasters();
} else if (0U != (PMU_IOMODULE_GPI1_USB_0_WAKE_MASK & srcMask)) {
status = PmWakeMasterBySlave(&pmSlaveUsb0_g.slv);
} else if (0U != (PMU_IOMODULE_GPI1_USB_1_WAKE_MASK & srcMask)) {
status = PmWakeMasterBySlave(&pmSlaveUsb1_g.slv);
} else {
}
return status;
}
/**
* XPfw_PmCheckIpiRequest() - Check whether the IPI interrupt is a PM call
* @isrVal IPI's ISR register value
* @apiId Pointer to a variable holding the api id (first word of message)
*
* @return Check result
*
* @note Call from IPI interrupt routine to check is interrupt a PM call.
* Function reads first argument of payload in IPI buffer of
* requestor master to determine whether first argument is within
* PM API regular ids.
*/
XPfw_PmIpiStatus XPfw_PmCheckIpiRequest(const u32 isrVal,
const u32* apiId)
{
XPfw_PmIpiStatus status;
const PmMaster *master = PmGetMasterByIpiMask(isrVal);
if (NULL == master) {
/* IPI is not generated by one of the PM supported PUs */
status = XPFW_PM_IPI_SRC_UNKNOWN;
goto done;
}
/* Api id is first argument in payload */
if ((*apiId >= PM_API_MIN) && (*apiId <= PM_API_MAX)) {
/* Api id is within valid range */
status = XPFW_PM_IPI_IS_PM_CALL;
} else {
/* This IPI was not a PM call */
status = XPFW_PM_IPI_NOT_PM_CALL;
}
done:
return status;
}
/**
* XPfw_DapFpdWakeEvent() - Inform PM about the FPD DAP wake event
*/
void XPfw_DapFpdWakeEvent(void)
{
if (0 != (XPfw_Read32(PMU_GLOBAL_PWR_STATE) &
PMU_GLOBAL_PWR_STATE_FP_MASK)) {
pmPowerDomainFpd_g.power.node.currState = PM_PWR_STATE_ON;
}
}
/**
* XPfw_DapRpuWakeEvent() - Inform PM about the RPU DAP wake event
*/
void XPfw_DapRpuWakeEvent(void)
{
if (0 != (XPfw_Read32(PMU_GLOBAL_PWR_STATE) &
PMU_GLOBAL_PWR_STATE_R5_0_MASK)) {
pmPowerIslandRpu_g.power.node.currState = PM_PWR_STATE_ON;
}
}
#endif
<file_sep>/c_drivers/drivers/rf.h
#ifndef SRC_DRIVERS_RF_H_
#define SRC_DRIVERS_RF_H_
#include "xparameters.h"
#include "xgpio.h"
uint8_t rf_init();
int rf_self_test();
u8 get_rf_clock_status();//Returns 0 if clock is active
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_power.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_POWER_H_
#define XPM_POWER_H_
#include "xpm_defs.h"
#include "xpm_node.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
/* Default FSM states */
XPM_POWER_STATE_OFF = 0,
XPM_POWER_STATE_INITIALIZING,
XPM_POWER_STATE_ON,
XPM_POWER_STATE_STANDBY,
XPM_POWER_STATE_PWR_UP_PARENT,
XPM_POWER_STATE_PWR_DOWN_PARENT,
XPM_POWER_STATE_PWR_UP_SELF,
XPM_POWER_STATE_PWR_DOWN_SELF,
} XPm_PowerState;
typedef enum {
XPM_POWER_EVENT_PWR_UP,
XPM_POWER_EVENT_PARENT_UP_DONE,
XPM_POWER_EVENT_SELF_UP_DONE,
XPM_POWER_EVENT_PWR_DOWN,
XPM_POWER_EVENT_SELF_DOWN_DONE,
XPM_POWER_EVENT_PARENT_DOWN_DONE,
XPM_POWER_EVENT_TIMER,
} XPm_PowerEvent;
typedef struct XPm_Power XPm_Power;
/**
* The power node class. This is the base class for all the power island and
* power domain classes.
*/
struct XPm_Power {
XPm_Node Node; /**< Node: Node base class */
XPm_Power *Parent; /**< Parent: Parent node in the power topology */
XPm_Power *NextPeer; /**< NextPeer: Next power node of the same parent */
u8 UseCount; /**< No. of devices currently using this power node */
u8 WfParentUseCnt; /**< Pending use count of the parent */
u16 PwrDnLatency; /**< Latency (in us) for transition to OFF state */
u16 PwrUpLatency; /**< Latency (in us) for transition to ON state */
XStatus (* HandleEvent)(XPm_Node *Node, u32 Event);
/**< HandleEvent: Pointer to event handler */
};
/************************** Function Prototypes ******************************/
XPm_Power *XPmPower_GetById(u32 Id);
XStatus XPmPower_Init(XPm_Power *Power,
u32 Id, u32 BaseAddress, XPm_Power *Parent);
XStatus XPmPower_AddParent(u32 Id, u32 *Parents, u32 NumParents);
XStatus XPmPower_GetStatus(const u32 SubsystemId, const u32 DeviceId, XPm_DeviceStatus *const DeviceStatus);
int XPmPower_GetWakeupLatency(const u32 DeviceId, u32 *Latency);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_POWER_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_psfpdomain.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PSFPDOMAIN_H_
#define XPM_PSFPDOMAIN_H_
#include "xpm_powerdomain.h"
#include "xpm_defs.h"
#include "xpm_psm_api.h"
#include "xpm_ipi.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* The PS Full power domain node class.
*/
typedef struct XPm_PsFpDomain {
XPm_PowerDomain Domain; /**< Power domain node base class */
u32 FpdSlcrBaseAddr; /**< FPD SLCR base address */
} XPm_PsFpDomain;
/************************** Function Prototypes ******************************/
XStatus XPmPsFpDomain_Init(XPm_PsFpDomain *PsFpd, u32 Id, u32 BaseAddress,
XPm_Power *Parent, u32 *OtherBaseAddresses,
u32 OtherBaseAddressCnt);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_PSFPDOMAIN_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/gpio.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _GPIO_H_
#define _GPIO_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* APU Base Address
*/
#define GPIO_BASEADDR (0XFF0A0000U)
/**
* Register: GPIO_MASK_DATA_5_MSW_REG
*/
#define GPIO_MASK_DATA_5_MSW_REG ( GPIO_BASEADDR + 0X0000002CU )
/**
* Register: GPIO_DATA_5_RO_REG
*/
#define GPIO_DATA_5_RO_REG ( GPIO_BASEADDR + 0X00000074U )
/**
* Register: GPIO_DIRM_5
*/
#define GPIO_DIRM_5 ( GPIO_BASEADDR + 0X00000344U )
#define MAX_REG_BITS 32
/*
* GPIO5 EMIO[95:92] are the PS-PL reset lines
*/
#define GPIO5_EMIO92_MSW_DATA_BIT 12
#define GPIO5_EMIO93_MSW_DATA_BIT 13
#define GPIO5_EMIO94_MSW_DATA_BIT 14
#define GPIO5_EMIO95_MSW_DATA_BIT 15
#define GPIO_PIN_MASK_BITS 0xFFFF0000
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_npdomain.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "sleep.h"
#include "xpm_common.h"
#include "xpm_pmc.h"
#include "xpm_domain_iso.h"
#include "xpm_npdomain.h"
#include "xpm_pslpdomain.h"
#include "xpm_regs.h"
#include "xpm_clock.h"
#include "xpm_reset.h"
#include "xpm_bisr.h"
#define XPM_NODEIDX_DEV_DDRMC_MIN XPM_NODEIDX_DEV_DDRMC_0
#define XPM_NODEIDX_DEV_DDRMC_MAX XPM_NODEIDX_DEV_DDRMC_3
static u32 NpdMemIcAddresses[XPM_NODEIDX_MEMIC_MAX];
static XStatus NpdInitStart(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 NpdPowerUpTime = 0;
(void)Args;
(void)NumOfArgs;
/* Check vccint_soc first to make sure power is on */
while (XST_SUCCESS != XPmPower_CheckPower(PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_SOC_MASK)) {
/* Wait for VCCINT_SOC power up */
usleep(10);
NpdPowerUpTime++;
if (NpdPowerUpTime > XPM_POLL_TIMEOUT) {
/* TODO: Request PMC to power up VCCINT_SOC rail and wait for the acknowledgement.*/
Status = XST_FAILURE;
goto done;
}
}
if (PLATFORM_VERSION_SILICON == Platform) {
/* TODO: This is a temporary fix for MGT boards;
* Remove the delay once AMS solution to read rail voltages is finalized.
*/
usleep(1000);
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_SOC_NPI, FALSE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Release POR for NoC */
Status = XPmReset_AssertbyId(PM_RST_NOC_POR, (u32)PM_RESET_ACTION_RELEASE);
done:
return Status;
}
static void NpdPreBisrReqs(void)
{
/* Release NPI Reset */
(void)XPmReset_AssertbyId(PM_RST_NPI, (u32)PM_RESET_ACTION_RELEASE);
/* Release NoC Reset */
(void)XPmReset_AssertbyId(PM_RST_NOC, (u32)PM_RESET_ACTION_RELEASE);
/* Release Sys Resets */
(void)XPmReset_AssertbyId(PM_RST_SYS_RST_1, (u32)PM_RESET_ACTION_RELEASE);
(void)XPmReset_AssertbyId(PM_RST_SYS_RST_2, (u32)PM_RESET_ACTION_RELEASE);
(void)XPmReset_AssertbyId(PM_RST_SYS_RST_3, (u32)PM_RESET_ACTION_RELEASE);
return;
}
static XStatus NpdInitFinish(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 i=0;
XPm_Device *Device;
u32 BaseAddress;
(void)Args;
(void)NumOfArgs;
/* NPD pre bisr requirements - in case if bisr and mbist was skipped */
NpdPreBisrReqs();
if (XST_SUCCESS == XPmPower_CheckPower( PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_MASK |
PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_SOC_MASK)) {
/* Remove vccaux-soc domain isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_VCCAUX_SOC, FALSE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
}
/* Remove PMC-NoC domain isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_SOC, FALSE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Assert ODISABLE NPP for all NMU and NSU
* This step is omitted for SSIT Device Slave SLR for NSU_1 as config is
* done by BOOT ROM
*/
for (i = 0; i < ARRAY_SIZE(NpdMemIcAddresses) && (0U != NpdMemIcAddresses[i]); i++) {
if (i == (u32)XPM_NODEIDX_MEMIC_NSU_1 &&
SlrType < SLR_TYPE_SSIT_DEV_MASTER_SLR) {
continue;
}
PmOut32(NpdMemIcAddresses[i] + NPI_PCSR_LOCK_OFFSET,
PCSR_UNLOCK_VAL);
PmOut32(NpdMemIcAddresses[i] + NPI_PCSR_MASK_OFFSET,
NPI_PCSR_CONTROL_ODISABLE_NPP_MASK);
PmOut32(NpdMemIcAddresses[i] + NPI_PCSR_CONTROL_OFFSET,
NPI_PCSR_CONTROL_ODISABLE_NPP_MASK);
PmOut32(NpdMemIcAddresses[i] + NPI_PCSR_LOCK_OFFSET, 1);
}
/* Deassert UB_INITSTATE for DDR blocks */
for (i = (u32)XPM_NODEIDX_DEV_DDRMC_MIN; i <= (u32)XPM_NODEIDX_DEV_DDRMC_MAX; i++) {
Device = XPmDevice_GetById(DDRMC_DEVID(i));
if (NULL != Device) {
BaseAddress = Device->Node.BaseAddress;
PmOut32(BaseAddress + NPI_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
PmOut32(BaseAddress + NPI_PCSR_MASK_OFFSET,
NPI_DDRMC_PSCR_CONTROL_UB_INITSTATE_MASK);
PmOut32(BaseAddress + NPI_PCSR_CONTROL_OFFSET, 0);
PmOut32(BaseAddress + NPI_PCSR_LOCK_OFFSET, 1);
/* Only UB0 for non sillicon platforms */
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
break;
}
}
}
/* When NPD is powered, copy sysmon data */
for (i = (u32)XPM_NODEIDX_MONITOR_SYSMON_NPD_MIN; i < (u32)XPM_NODEIDX_MONITOR_SYSMON_NPD_MAX; i++) {
/* Copy_trim< AMS_SAT_N> */
if (0U != SysmonAddresses[i]) {
Status = XPmPowerDomain_ApplyAmsTrim(SysmonAddresses[i], PM_POWER_NOC, i-(u32)XPM_NODEIDX_MONITOR_SYSMON_NPD_MIN);
if (XST_SUCCESS != Status) {
goto done;
}
}
}
/* Assert pcomplete to indicate HC is done and NoC is ready to use */
/* Unlock PCSR Register*/
PmOut32(NPI_BASEADDR + NPI_NIR_0_OFFSET + NPI_PCSR_LOCK_OFFSET,
PCSR_UNLOCK_VAL);
/* Unmask the pcomplete bit */
PmOut32(NPI_BASEADDR + NPI_NIR_0_OFFSET + NPI_PCSR_MASK_OFFSET,
NPI_PCSR_CONTROL_PCOMPLETE_MASK);
/*Assert control on pcomplete bit*/
PmOut32(NPI_BASEADDR + NPI_NIR_0_OFFSET + NPI_PCSR_CONTROL_OFFSET,
NPI_PCSR_CONTROL_PCOMPLETE_MASK);
/*Lock PCSR Register */
PmOut32(NPI_BASEADDR + NPI_NIR_0_OFFSET + NPI_PCSR_LOCK_OFFSET,
0x1);
done:
return Status;
}
static XStatus NpdScanClear(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
XPm_Pmc *Pmc;
u32 RegValue;
XPm_OutClockNode *Clk;
(void)Args;
(void)NumOfArgs;
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
if (SlrType != SLR_TYPE_MONOLITHIC_DEV &&
SlrType != SLR_TYPE_SSIT_DEV_MASTER_SLR) {
PmDbg("Skipping Scan-Clear of NPD for Slave SLR\n\r");
Status = XST_SUCCESS;
goto done;
}
Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
if (NULL == Pmc) {
Status = XST_FAILURE;
goto done;
}
PmOut32((Pmc->PmcGlobalBaseAddr + PMC_GLOBAL_ERR1_STATUS_OFFSET),
(PMC_GLOBAL_ERR1_STATUS_NOC_TYPE_1_NCR_MASK |
PMC_GLOBAL_ERR1_STATUS_DDRMC_MC_NCR_MASK));
PmRmw32(PMC_ANALOG_SCAN_CLEAR_TRIGGER,
PMC_ANALOG_SCAN_CLEAR_TRIGGER_NOC_MASK,
PMC_ANALOG_SCAN_CLEAR_TRIGGER_NOC_MASK);
/* 200 us is not enough and scan clear pass status is updated
after so increasing delay for scan clear to finish */
usleep(400);
/* Enable NPI Clock */
Clk = (XPm_OutClockNode *)XPmClock_GetByIdx((u32)XPM_NODEIDX_CLK_NPI_REF);
Status = XPmClock_SetGate((XPm_OutClockNode *)Clk, 1);
if (XST_SUCCESS != Status) {
goto done;
}
/* Release NPI Reset */
Status = XPmReset_AssertbyId(PM_RST_NPI, (u32)PM_RESET_ACTION_RELEASE);
if (XST_SUCCESS != Status) {
goto done;
}
PmIn32((Pmc->PmcGlobalBaseAddr + PMC_GLOBAL_ERR1_STATUS_OFFSET),
RegValue);
if (0U != (RegValue & (PMC_GLOBAL_ERR1_STATUS_NOC_TYPE_1_NCR_MASK |
PMC_GLOBAL_ERR1_STATUS_DDRMC_MC_NCR_MASK))) {
Status = XST_FAILURE;
goto done;
}
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus NpdMbist(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 RegValue;
u32 i;
XPm_Device *Device;
u32 DdrMcAddresses[XPM_NODEIDX_DEV_DDRMC_MAX - XPM_NODEIDX_DEV_DDRMC_MIN + 1] = {0};
(void)Args;
(void)NumOfArgs;
for (i = 0; i < ARRAY_SIZE(DdrMcAddresses); i++) {
Device = XPmDevice_GetById(DDRMC_DEVID((u32)XPM_NODEIDX_DEV_DDRMC_MIN + i));
if (NULL != Device) {
DdrMcAddresses[i] = Device->Node.BaseAddress;
}
}
/* NPD pre bisr requirements - in case if bisr was skipped */
NpdPreBisrReqs();
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
/* Deassert PCSR Lock*/
for (i = 0; i < ARRAY_SIZE(NpdMemIcAddresses) && (0U != NpdMemIcAddresses[i]); i++) {
PmOut32(NpdMemIcAddresses[i] + NPI_PCSR_LOCK_OFFSET,
PCSR_UNLOCK_VAL);
}
/* Enable ILA clock for DDR blocks*/
for (i = 0; i < ARRAY_SIZE(DdrMcAddresses) && (0U != DdrMcAddresses[i]); i++) {
PmOut32(DdrMcAddresses[i] + NPI_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
PmRmw32(DdrMcAddresses[i] + NOC_DDRMC_UB_CLK_GATE_OFFSET,
NOC_DDRMC_UB_CLK_GATE_ILA_EN_MASK,
NOC_DDRMC_UB_CLK_GATE_ILA_EN_MASK);
}
/* Trigger Mem clear */
for (i = 0; i < ARRAY_SIZE(NpdMemIcAddresses) && (0U != NpdMemIcAddresses[i]); i++) {
PmOut32(NpdMemIcAddresses[i] + NPI_PCSR_MASK_OFFSET,
NPI_PCSR_CONTROL_MEM_CLEAR_TRIGGER_MASK);
PmOut32(NpdMemIcAddresses[i] + NPI_PCSR_CONTROL_OFFSET,
NPI_PCSR_CONTROL_MEM_CLEAR_TRIGGER_MASK);
}
for (i = 0; i < ARRAY_SIZE(DdrMcAddresses) && (0U != DdrMcAddresses[i]); i++) {
PmOut32(DdrMcAddresses[i] + NPI_PCSR_MASK_OFFSET,
NPI_PCSR_CONTROL_MEM_CLEAR_TRIGGER_MASK);
PmOut32(DdrMcAddresses[i] + NPI_PCSR_CONTROL_OFFSET,
NPI_PCSR_CONTROL_MEM_CLEAR_TRIGGER_MASK);
}
/* Check for Mem clear done */
for (i = 0; i < ARRAY_SIZE(NpdMemIcAddresses) && (0U != NpdMemIcAddresses[i]); i++) {
Status = XPm_PollForMask(NpdMemIcAddresses[i] +
NPI_PCSR_STATUS_OFFSET,
NPI_PCSR_STATUS_MEM_CLEAR_DONE_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
}
for (i = 0; i < ARRAY_SIZE(DdrMcAddresses) && (0U != DdrMcAddresses[i]); i++) {
Status = XPm_PollForMask(DdrMcAddresses[i] + NPI_PCSR_STATUS_OFFSET,
NPI_PCSR_STATUS_MEM_CLEAR_DONE_MASK,
XPM_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
goto done;
}
}
/* Check for Mem clear Pass/Fail */
for (i = 0; i < ARRAY_SIZE(NpdMemIcAddresses) && (0U != NpdMemIcAddresses[i]); i++) {
PmIn32(NpdMemIcAddresses[i] + NPI_PCSR_STATUS_OFFSET, RegValue);
if (NPI_PCSR_STATUS_MEM_CLEAR_PASS_MASK !=
(RegValue & NPI_PCSR_STATUS_MEM_CLEAR_PASS_MASK)) {
Status = XST_FAILURE;
goto done;
}
}
for (i = 0; i < ARRAY_SIZE(DdrMcAddresses) && (0U != DdrMcAddresses[i]); i++) {
PmIn32(DdrMcAddresses[i] + NPI_PCSR_STATUS_OFFSET, RegValue);
if (NPI_PCSR_STATUS_MEM_CLEAR_PASS_MASK !=
(RegValue & NPI_PCSR_STATUS_MEM_CLEAR_PASS_MASK)) {
Status = XST_FAILURE;
goto done;
}
}
/* Disable ILA clock for DDR blocks*/
for (i = 0; i < ARRAY_SIZE(DdrMcAddresses) && (0U != DdrMcAddresses[i]); i++) {
PmRmw32(DdrMcAddresses[i] + NOC_DDRMC_UB_CLK_GATE_OFFSET,
NOC_DDRMC_UB_CLK_GATE_ILA_EN_MASK, 0);
PmOut32(DdrMcAddresses[i] + NPI_PCSR_LOCK_OFFSET, 1);
}
/* Unwrite trigger bits */
for (i = 0; i < ARRAY_SIZE(NpdMemIcAddresses) && (0U != NpdMemIcAddresses[i]); i++) {
PmOut32(NpdMemIcAddresses[i] + NPI_PCSR_MASK_OFFSET,
NPI_PCSR_CONTROL_MEM_CLEAR_TRIGGER_MASK)
PmOut32(NpdMemIcAddresses[i] + NPI_PCSR_CONTROL_OFFSET, 0);
}
for (i = 0; i < ARRAY_SIZE(DdrMcAddresses) && (0U != DdrMcAddresses[i]); i++) {
PmOut32(DdrMcAddresses[i] + NPI_PCSR_MASK_OFFSET,
NPI_PCSR_CONTROL_MEM_CLEAR_TRIGGER_MASK);
PmOut32(DdrMcAddresses[i] + NPI_PCSR_CONTROL_OFFSET, 0);
}
/* Assert PCSR Lock*/
for (i = 0; i < ARRAY_SIZE(NpdMemIcAddresses) && (0U != NpdMemIcAddresses[i]); i++) {
PmOut32(NpdMemIcAddresses[i] + NPI_PCSR_LOCK_OFFSET, 1);
}
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus NpdBisr(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 i = 0;
XPm_Device *Device;
u32 DdrMcAddresses[XPM_NODEIDX_DEV_DDRMC_MAX - XPM_NODEIDX_DEV_DDRMC_MIN + 1] = {0};
(void)Args;
(void)NumOfArgs;
for (i = 0; i < ARRAY_SIZE(DdrMcAddresses); i++) {
Device = XPmDevice_GetById(DDRMC_DEVID((u32)XPM_NODEIDX_DEV_DDRMC_MIN + i));
if (NULL != Device) {
DdrMcAddresses[i] = Device->Node.BaseAddress;
}
}
/* NPD pre bisr requirements */
NpdPreBisrReqs();
if (PLATFORM_VERSION_SILICON != Platform) {
Status = XST_SUCCESS;
goto done;
}
/* Enable Bisr clock */
for (i = 0; i < ARRAY_SIZE(DdrMcAddresses) && (0U != DdrMcAddresses[i]); i++) {
/* Unlock writes */
PmOut32(DdrMcAddresses[i] + NPI_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
PmRmw32(DdrMcAddresses[i] + NOC_DDRMC_UB_CLK_GATE_OFFSET,
NOC_DDRMC_UB_CLK_GATE_BISR_EN_MASK,
NOC_DDRMC_UB_CLK_GATE_BISR_EN_MASK);
}
/* Run BISR */
Status = XPmBisr_Repair(DDRMC_TAG_ID);
if (Status != XST_SUCCESS) {
goto done;
}
/* Disable Bisr clock */
for (i = 0; i < ARRAY_SIZE(DdrMcAddresses) && (0U != DdrMcAddresses[i]); i++) {
PmRmw32(DdrMcAddresses[i] + NOC_DDRMC_UB_CLK_GATE_OFFSET,
NOC_DDRMC_UB_CLK_GATE_BISR_EN_MASK, 0);
/* Lock writes */
PmOut32(DdrMcAddresses[i] + NPI_PCSR_LOCK_OFFSET, 1);
}
/* NIDB Lane Repair */
Status = XPmBisr_NidbLaneRepair();
done:
return Status;
}
static struct XPm_PowerDomainOps NpdOps = {
.InitStart = NpdInitStart,
.InitFinish = NpdInitFinish,
.ScanClear = NpdScanClear,
.Mbist = NpdMbist,
.Bisr = NpdBisr,
};
XStatus XPmNpDomain_Init(XPm_NpDomain *Npd, u32 Id, u32 BaseAddress,
XPm_Power *Parent)
{
XStatus Status = XST_FAILURE;
Status = XPmPowerDomain_Init(&Npd->Domain, Id, BaseAddress, Parent, &NpdOps);
if (XST_SUCCESS == Status) {
Npd->BisrDataCopied = 0;
}
return Status;
}
XStatus XPmNpDomain_MemIcInit(u32 DeviceId, u32 BaseAddr)
{
XStatus Status = XST_FAILURE;
u32 Idx = NODEINDEX(DeviceId);
u32 Type = NODETYPE(DeviceId);
if ((((u32)XPM_NODETYPE_MEMIC_SLAVE != Type) &&
((u32)XPM_NODETYPE_MEMIC_MASTER != Type)) ||
((u32)XPM_NODEIDX_MEMIC_MAX <= Idx)) {
Status = XST_INVALID_PARAM;
goto done;
}
NpdMemIcAddresses[Idx] = BaseAddr;
Status = XST_SUCCESS;
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_7/src/xusbpsu_ephandler.c
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_ephandler.c
* @addtogroup usbpsu_v1_7
* @{
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 pm 03/23/20 First release
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files *********************************/
#include "xusbpsu_endpoint.h"
#include "xusbpsu_local.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
* @brief
* Stops transfer on Endpoint.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEpNum is USB endpoint number.
* @param Dir is direction of endpoint
* - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
* @param Force flag to stop/pause transfer.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
u8 Dir, u8 Force)
{
struct XUsbPsu_Ep *Ept;
struct XUsbPsu_EpParams *Params;
u8 PhyEpNum;
u32 Cmd;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(UsbEpNum <= (u8)16U);
Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) ||
(Dir == XUSBPSU_EP_DIR_OUT));
PhyEpNum = XUSBPSU_PhysicalEp(UsbEpNum, Dir);
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertVoid(Params != NULL);
Ept = &InstancePtr->eps[PhyEpNum];
if (Ept->ResourceIndex == 0U) {
return;
}
/*
* - Issue EndTransfer WITH CMDIOC bit set
* - Wait 100us
*/
Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
Cmd |= (Force == TRUE) ? XUSBPSU_DEPCMD_HIPRI_FORCERM : 0U;
Cmd |= XUSBPSU_DEPCMD_CMDIOC;
Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
Cmd, Params);
if (Force == TRUE) {
Ept->ResourceIndex = 0U;
}
Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
XUsbPsu_Sleep(100U);
}
/****************************************************************************/
/**
* Reset and Deactivate transfer Endpoint.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEpNum is USB endpoint number.
* @param Dir is direction of endpoint
* - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XUsbPsu_EpTransferDeactive(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
u8 Dir)
{
struct XUsbPsu_Ep *Ept;
u8 PhyEpNum;
u32 RegVal;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(UsbEpNum <= (u8)16U);
Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) ||
(Dir == XUSBPSU_EP_DIR_OUT));
PhyEpNum = XUSBPSU_PhysicalEp(UsbEpNum, Dir);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
RegVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
Ept = &InstancePtr->eps[PhyEpNum];
if (Ept != NULL) {
Ept->Type = 0U;
Ept->EpStatus = 0U;
Ept->MaxSize = 0U;
Ept->TrbEnqueue = 0U;
Ept->TrbDequeue = 0U;
}
}
/****************************************************************************/
/**
* Query endpoint state and save it in EpSavedState
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Ept is a pointer to the XUsbPsu pointer structure.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XUsbPsu_SaveEndpointState(struct XUsbPsu *InstancePtr,
struct XUsbPsu_Ep *Ept)
{
Xil_AssertVoid(InstancePtr != NULL);
struct XUsbPsu_EpParams *Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertVoid(Params != NULL);
XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
XUSBPSU_DEPCMD_GETEPSTATE, Params);
Ept->EpSavedState = XUsbPsu_ReadReg(InstancePtr,
XUSBPSU_DEPCMDPAR2(Ept->PhyEpNum));
}
/****************************************************************************/
/**
* Clears Stall on all endpoints.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr)
{
struct XUsbPsu_EpParams *Params;
u32 Epnum;
struct XUsbPsu_Ep *Ept;
Xil_AssertVoid(InstancePtr != NULL);
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertVoid(Params != NULL);
for (Epnum = 1U; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) {
Ept = &InstancePtr->eps[Epnum];
if ((Ept->EpStatus & XUSBPSU_EP_STALL) == 0U) {
continue;
}
Ept->EpStatus &= ~XUSBPSU_EP_STALL;
(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum,
Ept->Direction,
XUSBPSU_DEPCMD_CLEARSTALL,
Params);
}
}
/****************************************************************************/
/**
* @brief
* Initiates DMA to send data on endpoint to Host.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEp is USB endpoint number.
* @param BufferPtr is pointer to data.
* @param BufferLen is length of data buffer.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp,
u8 *BufferPtr, u32 BufferLen)
{
u8 PhyEpNum;
u32 cmd;
s32 RetVal;
struct XUsbPsu_Trb *TrbPtr;
struct XUsbPsu_Ep *Ept;
struct XUsbPsu_EpParams *Params;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(UsbEp <= (u8)16U);
Xil_AssertNonvoid(BufferPtr != NULL);
PhyEpNum = XUSBPSU_PhysicalEp(UsbEp, XUSBPSU_EP_DIR_IN);
if (PhyEpNum == 1U) {
RetVal = XUsbPsu_Ep0Send(InstancePtr, BufferPtr, BufferLen);
return RetVal;
}
Ept = &InstancePtr->eps[PhyEpNum];
if (Ept->Direction != XUSBPSU_EP_DIR_IN) {
return (s32)XST_FAILURE;
}
Ept->RequestedBytes = BufferLen;
Ept->BytesTxed = 0U;
Ept->BufferPtr = BufferPtr;
TrbPtr = &Ept->EpTrb[Ept->TrbEnqueue];
Ept->TrbEnqueue++;
if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) {
Ept->TrbEnqueue = 0U;
}
TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16U) >> 16U;
TrbPtr->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK;
switch (Ept->Type) {
case XUSBPSU_ENDPOINT_XFER_ISOC:
/*
* According to DWC3 datasheet, XUSBPSU_TRBCTL_ISOCHRONOUS and
* XUSBPSU_TRBCTL_CHN fields are only set when request has
* scattered list so these fields are not set over here.
*/
TrbPtr->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST
| XUSBPSU_TRB_CTRL_CSP);
break;
case XUSBPSU_ENDPOINT_XFER_INT:
case XUSBPSU_ENDPOINT_XFER_BULK:
TrbPtr->Ctrl = (XUSBPSU_TRBCTL_NORMAL
| XUSBPSU_TRB_CTRL_LST);
break;
default:
/* Do Nothing. Added for making MISRA-C complaint */
break;
}
TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
| XUSBPSU_TRB_CTRL_IOC
| XUSBPSU_TRB_CTRL_ISP_IMI);
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)TrbPtr,
sizeof(struct XUsbPsu_Trb));
Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen);
}
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertNonvoid(Params != NULL);
Params->Param0 = 0U;
Params->Param1 = (UINTPTR)TrbPtr;
if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != (u32)0U) {
cmd = XUSBPSU_DEPCMD_UPDATETRANSFER;
cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
} else {
if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) {
BufferPtr += BufferLen;
struct XUsbPsu_Trb *TrbTempNext;
TrbTempNext = &Ept->EpTrb[Ept->TrbEnqueue];
Ept->TrbEnqueue++;
if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) {
Ept->TrbEnqueue = 0U;
}
TrbTempNext->BufferPtrLow = (UINTPTR)BufferPtr;
TrbTempNext->BufferPtrHigh = ((UINTPTR)BufferPtr >>
16U) >> 16U;
TrbTempNext->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK;
TrbTempNext->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST
| XUSBPSU_TRB_CTRL_CSP
| XUSBPSU_TRB_CTRL_HWO
| XUSBPSU_TRB_CTRL_IOC
| XUSBPSU_TRB_CTRL_ISP_IMI);
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)TrbTempNext,
sizeof(struct XUsbPsu_Trb));
Xil_DCacheFlushRange((INTPTR)BufferPtr,
BufferLen);
}
}
cmd = XUSBPSU_DEPCMD_STARTTRANSFER;
cmd |= XUSBPSU_DEPCMD_PARAM(Ept->CurUf);
}
RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
cmd, Params);
if (RetVal & (s32)XST_FAILURE) {
return (s32)XST_FAILURE;
}
if ((Ept->EpStatus & XUSBPSU_EP_BUSY) == (u32)0U) {
Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
Ept->UsbEpNum,
Ept->Direction);
Ept->EpStatus |= XUSBPSU_EP_BUSY;
}
return XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Initiates DMA to receive data on Endpoint from Host.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param UsbEp is USB endpoint number.
* @param BufferPtr is pointer to data.
* @param Length is length of data to be received.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp,
u8 *BufferPtr, u32 Length)
{
u8 PhyEpNum;
u32 cmd;
u32 Size;
s32 RetVal;
struct XUsbPsu_Trb *TrbPtr;
struct XUsbPsu_Ep *Ept;
struct XUsbPsu_EpParams *Params;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(UsbEp <= (u8)16U);
Xil_AssertNonvoid(BufferPtr != NULL);
PhyEpNum = XUSBPSU_PhysicalEp(UsbEp, XUSBPSU_EP_DIR_OUT);
if (PhyEpNum == 0U) {
RetVal = XUsbPsu_Ep0Recv(InstancePtr, BufferPtr, Length);
return RetVal;
}
Ept = &InstancePtr->eps[PhyEpNum];
if (Ept->Direction != XUSBPSU_EP_DIR_OUT) {
return (s32)XST_FAILURE;
}
Ept->RequestedBytes = Length;
Size = Length;
Ept->BytesTxed = 0U;
Ept->BufferPtr = BufferPtr;
/*
* 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
* must be a multiple of MaxPacketSize even if software is expecting a
* fixed non-multiple of MaxPacketSize transfer from the Host.
*/
if (!IS_ALIGNED(Length, Ept->MaxSize)) {
Size = (u32)roundup(Length, (u16)Ept->MaxSize);
Ept->UnalignedTx = 1U;
}
TrbPtr = &Ept->EpTrb[Ept->TrbEnqueue];
Ept->TrbEnqueue += 1U;
if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) {
Ept->TrbEnqueue = 0U;
}
TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16U) >> 16U;
TrbPtr->Size = Size;
switch (Ept->Type) {
case XUSBPSU_ENDPOINT_XFER_ISOC:
/*
* According to Linux driver, XUSBPSU_TRBCTL_ISOCHRONOUS and
* XUSBPSU_TRBCTL_CHN fields are only set when request has
* scattered list so these fields are not set over here.
*/
TrbPtr->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST
| XUSBPSU_TRB_CTRL_CSP);
break;
case XUSBPSU_ENDPOINT_XFER_INT:
case XUSBPSU_ENDPOINT_XFER_BULK:
TrbPtr->Ctrl = (XUSBPSU_TRBCTL_NORMAL
| XUSBPSU_TRB_CTRL_LST);
break;
default:
/* Do Nothing. Added for making MISRA-C complaint */
break;
}
TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
| XUSBPSU_TRB_CTRL_IOC
| XUSBPSU_TRB_CTRL_ISP_IMI);
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)TrbPtr,
sizeof(struct XUsbPsu_Trb));
Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length);
}
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertNonvoid(Params != NULL);
Params->Param0 = 0U;
Params->Param1 = (UINTPTR)TrbPtr;
if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != (u32)0U) {
cmd = XUSBPSU_DEPCMD_UPDATETRANSFER;
cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
} else {
if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) {
BufferPtr += Length;
struct XUsbPsu_Trb *TrbTempNext;
TrbTempNext = &Ept->EpTrb[Ept->TrbEnqueue];
Ept->TrbEnqueue++;
if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) {
Ept->TrbEnqueue = 0U;
}
TrbTempNext->BufferPtrLow = (UINTPTR)BufferPtr;
TrbTempNext->BufferPtrHigh = ((UINTPTR)BufferPtr >>
16U) >> 16U;
TrbTempNext->Size = Length & XUSBPSU_TRB_SIZE_MASK;
TrbTempNext->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST
| XUSBPSU_TRB_CTRL_CSP
| XUSBPSU_TRB_CTRL_HWO
| XUSBPSU_TRB_CTRL_IOC
| XUSBPSU_TRB_CTRL_ISP_IMI);
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)TrbTempNext,
sizeof(struct XUsbPsu_Trb));
Xil_DCacheFlushRange((INTPTR)BufferPtr, Length);
}
}
cmd = XUSBPSU_DEPCMD_STARTTRANSFER;
cmd |= XUSBPSU_DEPCMD_PARAM(Ept->CurUf);
}
RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
cmd, Params);
if (RetVal != XST_SUCCESS) {
return (s32)XST_FAILURE;
}
if ((Ept->EpStatus & XUSBPSU_EP_BUSY) == (u32)0U) {
Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
Ept->UsbEpNum,
Ept->Direction);
Ept->EpStatus |= XUSBPSU_EP_BUSY;
}
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief
* Stalls an Endpoint.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Epnum is USB endpoint number.
* @param Dir is direction.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
{
u8 PhyEpNum;
struct XUsbPsu_Ep *Ept = NULL;
struct XUsbPsu_EpParams *Params;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Epnum <= (u8)16U);
Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) ||
(Dir == XUSBPSU_EP_DIR_OUT));
PhyEpNum = XUSBPSU_PhysicalEp(Epnum, Dir);
Ept = &InstancePtr->eps[PhyEpNum];
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertVoid(Params != NULL);
(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
XUSBPSU_DEPCMD_SETSTALL, Params);
Ept->EpStatus |= XUSBPSU_EP_STALL;
}
/****************************************************************************/
/**
* @brief
* Clears Stall on an Endpoint.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Epnum is USB endpoint number.
* @param Dir is direction.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
{
u8 PhyEpNum;
struct XUsbPsu_Ep *Ept = NULL;
struct XUsbPsu_EpParams *Params;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Epnum <= (u8)16U);
Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) ||
(Dir == XUSBPSU_EP_DIR_OUT));
PhyEpNum = XUSBPSU_PhysicalEp(Epnum, Dir);
Ept = &InstancePtr->eps[PhyEpNum];
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertVoid(Params != NULL);
(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
XUSBPSU_DEPCMD_CLEARSTALL, Params);
Ept->EpStatus &= ~XUSBPSU_EP_STALL;
}
/****************************************************************************/
/**
* @brief
* Sets an user handler to be called after data is sent/received by an Endpoint
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Epnum is USB endpoint number.
* @param Dir is direction of endpoint
* - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
* @param Handler is user handler to be called.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum,
u8 Dir, void (*Handler)(void *, u32, u32))
{
u8 PhyEpNum;
struct XUsbPsu_Ep *Ept;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Epnum <= (u8)16U);
Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) ||
(Dir == XUSBPSU_EP_DIR_OUT));
PhyEpNum = XUSBPSU_PhysicalEp(Epnum, Dir);
Ept = &InstancePtr->eps[PhyEpNum];
Ept->Handler = (void (*)(void *, u32, u32))Handler;
}
/****************************************************************************/
/**
* @brief
* Returns status of endpoint - Stalled or not
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Epnum is USB endpoint number.
* @param Dir is direction of endpoint
* - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
*
* @return
* 1 - if stalled
* 0 - if not stalled
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
{
u8 PhyEpNum;
struct XUsbPsu_Ep *Ept;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Epnum <= (u8)16U);
Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
(Dir == XUSBPSU_EP_DIR_OUT));
PhyEpNum = XUSBPSU_PhysicalEp(Epnum, Dir);
Ept = &InstancePtr->eps[PhyEpNum];
return (s32)(!!(Ept->EpStatus & XUSBPSU_EP_STALL));
}
/****************************************************************************/
/**
* Checks the Data Phase and calls user Endpoint handler.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is a pointer to the Endpoint event occurred in core.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event)
{
struct XUsbPsu_Ep *Ept;
struct XUsbPsu_Trb *TrbPtr;
u32 Length;
u32 Epnum;
u8 Dir;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Event != NULL);
Epnum = Event->Epnumber;
Ept = &InstancePtr->eps[Epnum];
Dir = Ept->Direction;
TrbPtr = &Ept->EpTrb[Ept->TrbDequeue];
Ept->TrbDequeue++;
if (Ept->TrbDequeue == NO_OF_TRB_PER_EP) {
Ept->TrbDequeue = 0U;
}
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheInvalidateRange((INTPTR)TrbPtr,
sizeof(struct XUsbPsu_Trb));
}
if (Event->Endpoint_Event == XUSBPSU_DEPEVT_XFERCOMPLETE) {
Ept->EpStatus &= ~(XUSBPSU_EP_BUSY);
Ept->ResourceIndex = 0U;
}
Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
if (Length == 0U) {
Ept->BytesTxed = Ept->RequestedBytes;
} else {
if (Dir == XUSBPSU_EP_DIR_IN) {
Ept->BytesTxed = Ept->RequestedBytes - Length;
} else {
if (Ept->UnalignedTx == 1U) {
Ept->BytesTxed = (u32)roundup(
Ept->RequestedBytes,
(u16)Ept->MaxSize);
Ept->BytesTxed -= Length;
Ept->UnalignedTx = 0U;
} else {
/*
* Get the actual number of bytes transmitted
* by host
*/
Ept->BytesTxed = Ept->RequestedBytes - Length;
}
}
}
if (Dir == XUSBPSU_EP_DIR_OUT) {
/* Invalidate Cache */
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr,
Ept->BytesTxed);
}
}
if (Ept->Handler) {
Ept->Handler(InstancePtr->AppData, Ept->RequestedBytes,
Ept->BytesTxed);
}
}
/****************************************************************************/
/**
* For Isochronous transfer, get the microframe time and calls respective
* Endpoint handler.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is a pointer to the Endpoint event occurred in core.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_EpXferNotReady(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *Event)
{
struct XUsbPsu_Ep *Ept;
u32 Epnum;
u32 CurUf;
u32 Mask;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Event != NULL);
Epnum = Event->Epnumber;
Ept = &InstancePtr->eps[Epnum];
if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) {
Mask = ~(u32)((u32)1U << (Ept->Interval - 1U));
CurUf = Event->Parameters & Mask;
Ept->CurUf = (u16)(CurUf + (Ept->Interval * 4U));
if (Ept->Handler) {
Ept->Handler(InstancePtr->AppData, 0U, 0U);
}
}
}
#ifdef XUSBPSU_HIBERNATION_ENABLE
/*****************************************************************************/
/**
* Restarts transfer for active endpoint
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
* @param EpNum is an endpoint number.
*
* @return XST_SUCCESS on success or else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
s32 XUsbPsu_RestartEp(struct XUsbPsu *InstancePtr, u8 EpNum)
{
struct XUsbPsu_EpParams *Params;
struct XUsbPsu_Trb *TrbPtr;
struct XUsbPsu_Ep *Ept;
u32 Cmd;
s32 Ret;
Xil_AssertNonvoid(InstancePtr != NULL);
Params = XUsbPsu_GetEpParams(InstancePtr);
Xil_AssertNonvoid(Params != NULL);
Ept = &InstancePtr->eps[EpNum];
/* check if we need to restart transfer */
if ((Ept->ResourceIndex == (u32)0U) && (Ept->PhyEpNum != (u32)0U)) {
return XST_SUCCESS;
}
if (Ept->UsbEpNum != (u32)0U) {
TrbPtr = &Ept->EpTrb[Ept->TrbDequeue];
} else {
TrbPtr = &InstancePtr->Ep0_Trb;
}
TrbPtr->Ctrl |= XUSBPSU_TRB_CTRL_HWO;
if (InstancePtr->ConfigPtr->IsCacheCoherent == (u8)0U) {
Xil_DCacheFlushRange((INTPTR)TrbPtr,
sizeof(struct XUsbPsu_Trb));
Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr,
Ept->RequestedBytes);
}
Params->Param0 = 0U;
Params->Param1 = (UINTPTR)TrbPtr;
Cmd = XUSBPSU_DEPCMD_STARTTRANSFER;
Ret = XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
Cmd, Params);
if (Ret == XST_FAILURE) {
return (s32)XST_FAILURE;
}
Ept->EpStatus |= XUSBPSU_EP_BUSY;
Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
Ept->UsbEpNum, Ept->Direction);
return (s32)XST_SUCCESS;
}
#endif /*#ifdef XUSBPSU_HIBERNATION_ENABLE*/
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/apu.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _APU_H_
#define _APU_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* APU Base Address
*/
#define APU_BASEADDR ((u32)0XFD5C0000U)
/**
* Register: APU_ERR_CTRL
*/
#define APU_ERR_CTRL ( ( APU_BASEADDR ) + ((u32)0X00000000U) )
#define APU_ERR_CTRL_PSLVERR_SHIFT 0
#define APU_ERR_CTRL_PSLVERR_WIDTH 1
#define APU_ERR_CTRL_PSLVERR_MASK ((u32)0X00000001U)
/**
* Register: APU_ISR
*/
#define APU_ISR ( ( APU_BASEADDR ) + ((u32)0X00000010U) )
#define APU_ISR_INV_APB_SHIFT 0
#define APU_ISR_INV_APB_WIDTH 1
#define APU_ISR_INV_APB_MASK ((u32)0X00000001U)
/**
* Register: APU_IMR
*/
#define APU_IMR ( ( APU_BASEADDR ) + ((u32)0X00000014U) )
#define APU_IMR_INV_APB_SHIFT 0
#define APU_IMR_INV_APB_WIDTH 1
#define APU_IMR_INV_APB_MASK ((u32)0X00000001U)
/**
* Register: APU_IEN
*/
#define APU_IEN ( ( APU_BASEADDR ) + ((u32)0X00000018U) )
#define APU_IEN_INV_APB_SHIFT 0
#define APU_IEN_INV_APB_WIDTH 1
#define APU_IEN_INV_APB_MASK ((u32)0X00000001U)
/**
* Register: APU_IDS
*/
#define APU_IDS ( ( APU_BASEADDR ) + ((u32)0X0000001CU) )
#define APU_IDS_INV_APB_SHIFT 0
#define APU_IDS_INV_APB_WIDTH 1
#define APU_IDS_INV_APB_MASK ((u32)0X00000001U)
/**
* Register: APU_CONFIG_0
*/
#define APU_CONFIG_0 ( ( APU_BASEADDR ) + ((u32)0X00000020U) )
#define APU_CONFIG_0_CFGTE_SHIFT 24
#define APU_CONFIG_0_CFGTE_WIDTH 4
#define APU_CONFIG_0_CFGTE_MASK ((u32)0X0F000000U)
#define APU_CONFIG_0_CFGEND_SHIFT 16
#define APU_CONFIG_0_CFGEND_WIDTH 4
#define APU_CONFIG_0_CFGEND_MASK ((u32)0X000F0000U)
#define APU_CONFIG_0_VINITHI_SHIFT 8
#define APU_CONFIG_0_VINITHI_WIDTH 4
#define APU_CONFIG_0_VINITHI_MASK ((u32)0X00000F00U)
#define APU_CONFIG_0_AA64NAA32_SHIFT 0
#define APU_CONFIG_0_AA64NAA32_WIDTH 4
#define APU_CONFIG_0_AA64NAA32_MASK ((u32)0X0000000FU)
/**
* Register: APU_CONFIG_1
*/
#define APU_CONFIG_1 ( ( APU_BASEADDR ) + ((u32)0X00000024U) )
#define APU_CONFIG_1_L2RSTDISABLE_SHIFT 29
#define APU_CONFIG_1_L2RSTDISABLE_WIDTH 1
#define APU_CONFIG_1_L2RSTDISABLE_MASK ((u32)0X20000000U)
#define APU_CONFIG_1_L1RSTDISABLE_SHIFT 28
#define APU_CONFIG_1_L1RSTDISABLE_WIDTH 1
#define APU_CONFIG_1_L1RSTDISABLE_MASK ((u32)0X10000000U)
#define APU_CONFIG_1_CP15DISABLE_SHIFT 0
#define APU_CONFIG_1_CP15DISABLE_WIDTH 4
#define APU_CONFIG_1_CP15DISABLE_MASK ((u32)0X0000000FU)
/**
* Register: APU_RVBARADDR0L
*/
#define APU_RVBARADDR0L ( ( APU_BASEADDR ) + ((u32)0X00000040U) )
#define APU_RVBARADDR0L_ADDR_SHIFT 2
#define APU_RVBARADDR0L_ADDR_WIDTH 30
#define APU_RVBARADDR0L_ADDR_MASK ((u32)0XFFFFFFFCU)
/**
* Register: APU_RVBARADDR0H
*/
#define APU_RVBARADDR0H ( ( APU_BASEADDR ) + ((u32)0X00000044U) )
#define APU_RVBARADDR0H_ADDR_SHIFT 0
#define APU_RVBARADDR0H_ADDR_WIDTH 8
#define APU_RVBARADDR0H_ADDR_MASK ((u32)0X000000FFU)
/**
* Register: APU_RVBARADDR1L
*/
#define APU_RVBARADDR1L ( ( APU_BASEADDR ) + ((u32)0X00000048U) )
#define APU_RVBARADDR1L_ADDR_SHIFT 2
#define APU_RVBARADDR1L_ADDR_WIDTH 30
#define APU_RVBARADDR1L_ADDR_MASK ((u32)0XFFFFFFFCU)
/**
* Register: APU_RVBARADDR1H
*/
#define APU_RVBARADDR1H ( ( APU_BASEADDR ) + ((u32)0X0000004CU) )
#define APU_RVBARADDR1H_ADDR_SHIFT 0
#define APU_RVBARADDR1H_ADDR_WIDTH 8
#define APU_RVBARADDR1H_ADDR_MASK ((u32)0X000000FFU)
/**
* Register: APU_RVBARADDR2L
*/
#define APU_RVBARADDR2L ( ( APU_BASEADDR ) + ((u32)0X00000050U) )
#define APU_RVBARADDR2L_ADDR_SHIFT 2
#define APU_RVBARADDR2L_ADDR_WIDTH 30
#define APU_RVBARADDR2L_ADDR_MASK ((u32)0XFFFFFFFCU)
/**
* Register: APU_RVBARADDR2H
*/
#define APU_RVBARADDR2H ( ( APU_BASEADDR ) + ((u32)0X00000054U) )
#define APU_RVBARADDR2H_ADDR_SHIFT 0
#define APU_RVBARADDR2H_ADDR_WIDTH 8
#define APU_RVBARADDR2H_ADDR_MASK ((u32)0X000000FFU)
/**
* Register: APU_RVBARADDR3L
*/
#define APU_RVBARADDR3L ( ( APU_BASEADDR ) + ((u32)0X00000058U) )
#define APU_RVBARADDR3L_ADDR_SHIFT 2
#define APU_RVBARADDR3L_ADDR_WIDTH 30
#define APU_RVBARADDR3L_ADDR_MASK ((u32)0XFFFFFFFCU)
/**
* Register: APU_RVBARADDR3H
*/
#define APU_RVBARADDR3H ( ( APU_BASEADDR ) + ((u32)0X0000005CU) )
#define APU_RVBARADDR3H_ADDR_SHIFT 0
#define APU_RVBARADDR3H_ADDR_WIDTH 8
#define APU_RVBARADDR3H_ADDR_MASK ((u32)0X000000FFU)
/**
* Register: APU_ACE_CTRL
*/
#define APU_ACE_CTRL ( ( APU_BASEADDR ) + ((u32)0X00000060U) )
#define APU_ACE_CTRL_AWQOS_SHIFT 16
#define APU_ACE_CTRL_AWQOS_WIDTH 4
#define APU_ACE_CTRL_AWQOS_MASK ((u32)0X000F0000U)
#define APU_ACE_CTRL_ARQOS_SHIFT 0
#define APU_ACE_CTRL_ARQOS_WIDTH 4
#define APU_ACE_CTRL_ARQOS_MASK ((u32)0X0000000FU)
/**
* Register: APU_SNOOP_CTRL
*/
#define APU_SNOOP_CTRL ( ( APU_BASEADDR ) + ((u32)0X00000080U) )
#define APU_SNOOP_CTRL_ACE_INACT_SHIFT 4
#define APU_SNOOP_CTRL_ACE_INACT_WIDTH 1
#define APU_SNOOP_CTRL_ACE_INACT_MASK ((u32)0X00000010U)
#define APU_SNOOP_CTRL_ACP_INACT_SHIFT 0
#define APU_SNOOP_CTRL_ACP_INACT_WIDTH 1
#define APU_SNOOP_CTRL_ACP_INACT_MASK ((u32)0X00000001U)
/**
* Register: APU_PWRCTL
*/
#define APU_PWRCTL ( ( APU_BASEADDR ) + ((u32)0X00000090U) )
#define APU_PWRCTL_CLREXMONREQ_SHIFT 17
#define APU_PWRCTL_CLREXMONREQ_WIDTH 1
#define APU_PWRCTL_CLREXMONREQ_MASK ((u32)0X00020000U)
#define APU_PWRCTL_L2FLUSHREQ_SHIFT 16
#define APU_PWRCTL_L2FLUSHREQ_WIDTH 1
#define APU_PWRCTL_L2FLUSHREQ_MASK ((u32)0X00010000U)
#define APU_PWRCTL_CPUPWRDWNREQ_SHIFT 0
#define APU_PWRCTL_CPUPWRDWNREQ_WIDTH 4
#define APU_PWRCTL_CPUPWRDWNREQ_MASK ((u32)0X0000000FU)
/**
* Register: APU_PWRSTAT
*/
#define APU_PWRSTAT ( ( APU_BASEADDR ) + ((u32)0X00000094U) )
#define APU_PWRSTAT_CLREXMONACK_SHIFT 17
#define APU_PWRSTAT_CLREXMONACK_WIDTH 1
#define APU_PWRSTAT_CLREXMONACK_MASK ((u32)0X00020000U)
#define APU_PWRSTAT_L2FLUSHDONE_SHIFT 16
#define APU_PWRSTAT_L2FLUSHDONE_WIDTH 1
#define APU_PWRSTAT_L2FLUSHDONE_MASK ((u32)0X00010000U)
#define APU_PWRSTAT_DBGNOPWRDWN_SHIFT 0
#define APU_PWRSTAT_DBGNOPWRDWN_WIDTH 4
#define APU_PWRSTAT_DBGNOPWRDWN_MASK ((u32)0X0000000FU)
/**
* Register: APU_ECO
*/
#define APU_ECO ( ( APU_BASEADDR ) + ((u32)0X000000ECU) )
#define APU_ECO_SPARE_SHIFT 0
#define APU_ECO_SPARE_WIDTH 32
#define APU_ECO_SPARE_MASK ((u32)0XFFFFFFFFU)
/**
* Register: APU_RAM_ADJ_0
*/
#define APU_RAM_ADJ_0 ( ( APU_BASEADDR ) + ((u32)0X000000F0U) )
#define APU_RAM_ADJ_0_L1_ITAG_EMAS_SHIFT 29
#define APU_RAM_ADJ_0_L1_ITAG_EMAS_WIDTH 1
#define APU_RAM_ADJ_0_L1_ITAG_EMAS_MASK ((u32)0X20000000U)
#define APU_RAM_ADJ_0_L1_ITAG_EMAW_SHIFT 27
#define APU_RAM_ADJ_0_L1_ITAG_EMAW_WIDTH 2
#define APU_RAM_ADJ_0_L1_ITAG_EMAW_MASK ((u32)0X18000000U)
#define APU_RAM_ADJ_0_L1_ITAG_EMA_SHIFT 24
#define APU_RAM_ADJ_0_L1_ITAG_EMA_WIDTH 3
#define APU_RAM_ADJ_0_L1_ITAG_EMA_MASK ((u32)0X07000000U)
#define APU_RAM_ADJ_0_L1_IDATA_EMAS_SHIFT 21
#define APU_RAM_ADJ_0_L1_IDATA_EMAS_WIDTH 1
#define APU_RAM_ADJ_0_L1_IDATA_EMAS_MASK ((u32)0X00200000U)
#define APU_RAM_ADJ_0_L1_IDATA_EMAW_SHIFT 19
#define APU_RAM_ADJ_0_L1_IDATA_EMAW_WIDTH 2
#define APU_RAM_ADJ_0_L1_IDATA_EMAW_MASK ((u32)0X00180000U)
#define APU_RAM_ADJ_0_L1_IDATA_EMA_SHIFT 16
#define APU_RAM_ADJ_0_L1_IDATA_EMA_WIDTH 3
#define APU_RAM_ADJ_0_L1_IDATA_EMA_MASK ((u32)0X00070000U)
#define APU_RAM_ADJ_0_L1_DTAG_EMAS_SHIFT 13
#define APU_RAM_ADJ_0_L1_DTAG_EMAS_WIDTH 1
#define APU_RAM_ADJ_0_L1_DTAG_EMAS_MASK ((u32)0X00002000U)
#define APU_RAM_ADJ_0_L1_DTAG_EMAW_SHIFT 11
#define APU_RAM_ADJ_0_L1_DTAG_EMAW_WIDTH 2
#define APU_RAM_ADJ_0_L1_DTAG_EMAW_MASK ((u32)0X00001800U)
#define APU_RAM_ADJ_0_L1_DTAG_EMA_SHIFT 8
#define APU_RAM_ADJ_0_L1_DTAG_EMA_WIDTH 3
#define APU_RAM_ADJ_0_L1_DTAG_EMA_MASK ((u32)0X00000700U)
#define APU_RAM_ADJ_0_L1_DDATA_EMAS_SHIFT 5
#define APU_RAM_ADJ_0_L1_DDATA_EMAS_WIDTH 1
#define APU_RAM_ADJ_0_L1_DDATA_EMAS_MASK ((u32)0X00000020U)
#define APU_RAM_ADJ_0_L1_DDATA_EMAW_SHIFT 3
#define APU_RAM_ADJ_0_L1_DDATA_EMAW_WIDTH 2
#define APU_RAM_ADJ_0_L1_DDATA_EMAW_MASK ((u32)0X00000018U)
#define APU_RAM_ADJ_0_L1_DDATA_EMA_SHIFT 0
#define APU_RAM_ADJ_0_L1_DDATA_EMA_WIDTH 3
#define APU_RAM_ADJ_0_L1_DDATA_EMA_MASK ((u32)0X00000007U)
/**
* Register: APU_RAM_ADJ_1
*/
#define APU_RAM_ADJ_1 ( ( APU_BASEADDR ) + ((u32)0X000000F4U) )
#define APU_RAM_ADJ_1_TLB_EMAS_SHIFT 29
#define APU_RAM_ADJ_1_TLB_EMAS_WIDTH 1
#define APU_RAM_ADJ_1_TLB_EMAS_MASK ((u32)0X20000000U)
#define APU_RAM_ADJ_1_TLB_EMAW_SHIFT 27
#define APU_RAM_ADJ_1_TLB_EMAW_WIDTH 2
#define APU_RAM_ADJ_1_TLB_EMAW_MASK ((u32)0X18000000U)
#define APU_RAM_ADJ_1_TLB_EMA_SHIFT 24
#define APU_RAM_ADJ_1_TLB_EMA_WIDTH 3
#define APU_RAM_ADJ_1_TLB_EMA_MASK ((u32)0X07000000U)
#define APU_RAM_ADJ_1_DIRTY_EMAS_SHIFT 21
#define APU_RAM_ADJ_1_DIRTY_EMAS_WIDTH 1
#define APU_RAM_ADJ_1_DIRTY_EMAS_MASK ((u32)0X00200000U)
#define APU_RAM_ADJ_1_DIRTY_EMAW_SHIFT 19
#define APU_RAM_ADJ_1_DIRTY_EMAW_WIDTH 2
#define APU_RAM_ADJ_1_DIRTY_EMAW_MASK ((u32)0X00180000U)
#define APU_RAM_ADJ_1_DIRTY_EMA_SHIFT 16
#define APU_RAM_ADJ_1_DIRTY_EMA_WIDTH 3
#define APU_RAM_ADJ_1_DIRTY_EMA_MASK ((u32)0X00070000U)
#define APU_RAM_ADJ_1_BTAC1_EMAS_SHIFT 13
#define APU_RAM_ADJ_1_BTAC1_EMAS_WIDTH 1
#define APU_RAM_ADJ_1_BTAC1_EMAS_MASK ((u32)0X00002000U)
#define APU_RAM_ADJ_1_BTAC1_EMAW_SHIFT 11
#define APU_RAM_ADJ_1_BTAC1_EMAW_WIDTH 2
#define APU_RAM_ADJ_1_BTAC1_EMAW_MASK ((u32)0X00001800U)
#define APU_RAM_ADJ_1_BTAC1_EMA_SHIFT 8
#define APU_RAM_ADJ_1_BTAC1_EMA_WIDTH 3
#define APU_RAM_ADJ_1_BTAC1_EMA_MASK ((u32)0X00000700U)
#define APU_RAM_ADJ_1_BTAC0_EMAS_SHIFT 5
#define APU_RAM_ADJ_1_BTAC0_EMAS_WIDTH 1
#define APU_RAM_ADJ_1_BTAC0_EMAS_MASK ((u32)0X00000020U)
#define APU_RAM_ADJ_1_BTAC0_EMAW_SHIFT 3
#define APU_RAM_ADJ_1_BTAC0_EMAW_WIDTH 2
#define APU_RAM_ADJ_1_BTAC0_EMAW_MASK ((u32)0X00000018U)
#define APU_RAM_ADJ_1_BTAC0_EMA_SHIFT 0
#define APU_RAM_ADJ_1_BTAC0_EMA_WIDTH 3
#define APU_RAM_ADJ_1_BTAC0_EMA_MASK ((u32)0X00000007U)
/**
* Register: APU_RAM_ADJ_2
*/
#define APU_RAM_ADJ_2 ( ( APU_BASEADDR ) + ((u32)0X000000F8U) )
#define APU_RAM_ADJ_2_ETF_EMAS_SHIFT 29
#define APU_RAM_ADJ_2_ETF_EMAS_WIDTH 1
#define APU_RAM_ADJ_2_ETF_EMAS_MASK ((u32)0X20000000U)
#define APU_RAM_ADJ_2_ETF_EMAW_SHIFT 27
#define APU_RAM_ADJ_2_ETF_EMAW_WIDTH 2
#define APU_RAM_ADJ_2_ETF_EMAW_MASK ((u32)0X18000000U)
#define APU_RAM_ADJ_2_ETF_EMA_SHIFT 24
#define APU_RAM_ADJ_2_ETF_EMA_WIDTH 3
#define APU_RAM_ADJ_2_ETF_EMA_MASK ((u32)0X07000000U)
#define APU_RAM_ADJ_2_SCU_TAG_EMAS_SHIFT 13
#define APU_RAM_ADJ_2_SCU_TAG_EMAS_WIDTH 1
#define APU_RAM_ADJ_2_SCU_TAG_EMAS_MASK ((u32)0X00002000U)
#define APU_RAM_ADJ_2_SCU_TAG_EMAW_SHIFT 11
#define APU_RAM_ADJ_2_SCU_TAG_EMAW_WIDTH 2
#define APU_RAM_ADJ_2_SCU_TAG_EMAW_MASK ((u32)0X00001800U)
#define APU_RAM_ADJ_2_SCU_TAG_EMA_SHIFT 8
#define APU_RAM_ADJ_2_SCU_TAG_EMA_WIDTH 3
#define APU_RAM_ADJ_2_SCU_TAG_EMA_MASK ((u32)0X00000700U)
#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_SHIFT 5
#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_WIDTH 1
#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_MASK ((u32)0X00000020U)
#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_SHIFT 3
#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_WIDTH 2
#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_MASK ((u32)0X00000018U)
#define APU_RAM_ADJ_2_L2_VICTIM_EMA_SHIFT 0
#define APU_RAM_ADJ_2_L2_VICTIM_EMA_WIDTH 3
#define APU_RAM_ADJ_2_L2_VICTIM_EMA_MASK ((u32)0X00000007U)
/**
* Register: APU_RAM_ADJ_3
*/
#define APU_RAM_ADJ_3 ( ( APU_BASEADDR ) + ((u32)0X000000FCU) )
#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_SHIFT 29
#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_WIDTH 1
#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_MASK ((u32)0X20000000U)
#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_SHIFT 27
#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_WIDTH 2
#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_MASK ((u32)0X18000000U)
#define APU_RAM_ADJ_3_L2_TAGECC_EMA_SHIFT 24
#define APU_RAM_ADJ_3_L2_TAGECC_EMA_WIDTH 3
#define APU_RAM_ADJ_3_L2_TAGECC_EMA_MASK ((u32)0X07000000U)
#define APU_RAM_ADJ_3_L2_TAG_EMAS_SHIFT 21
#define APU_RAM_ADJ_3_L2_TAG_EMAS_WIDTH 1
#define APU_RAM_ADJ_3_L2_TAG_EMAS_MASK ((u32)0X00200000U)
#define APU_RAM_ADJ_3_L2_TAG_EMAW_SHIFT 19
#define APU_RAM_ADJ_3_L2_TAG_EMAW_WIDTH 2
#define APU_RAM_ADJ_3_L2_TAG_EMAW_MASK ((u32)0X00180000U)
#define APU_RAM_ADJ_3_L2_TAG_EMA_SHIFT 16
#define APU_RAM_ADJ_3_L2_TAG_EMA_WIDTH 3
#define APU_RAM_ADJ_3_L2_TAG_EMA_MASK ((u32)0X00070000U)
#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_SHIFT 13
#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_WIDTH 1
#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_MASK ((u32)0X00002000U)
#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_SHIFT 11
#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_WIDTH 2
#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_MASK ((u32)0X00001800U)
#define APU_RAM_ADJ_3_L2_DATAECC_EMA_SHIFT 8
#define APU_RAM_ADJ_3_L2_DATAECC_EMA_WIDTH 3
#define APU_RAM_ADJ_3_L2_DATAECC_EMA_MASK ((u32)0X00000700U)
#define APU_RAM_ADJ_3_L2_DATA_EMAS_SHIFT 5
#define APU_RAM_ADJ_3_L2_DATA_EMAS_WIDTH 1
#define APU_RAM_ADJ_3_L2_DATA_EMAS_MASK ((u32)0X00000020U)
#define APU_RAM_ADJ_3_L2_DATA_EMAW_SHIFT 3
#define APU_RAM_ADJ_3_L2_DATA_EMAW_WIDTH 2
#define APU_RAM_ADJ_3_L2_DATA_EMAW_MASK ((u32)0X00000018U)
#define APU_RAM_ADJ_3_L2_DATA_EMA_SHIFT 0
#define APU_RAM_ADJ_3_L2_DATA_EMA_WIDTH 3
#define APU_RAM_ADJ_3_L2_DATA_EMA_MASK ((u32)0X00000007U)
/**
* Register: APU_XPD_REG0
*/
#define APU_XPD_REG0 ( ( APU_BASEADDR ) + ((u32)0X00000600U) )
#define APU_XPD_REG0_PRE_LOAD_SHIFT 0
#define APU_XPD_REG0_PRE_LOAD_WIDTH 32
#define APU_XPD_REG0_PRE_LOAD_MASK ((u32)0XFFFFFFFFU)
/**
* Register: APU_XPD_REG1
*/
#define APU_XPD_REG1 ( ( APU_BASEADDR ) + ((u32)0X00000604U) )
#define APU_XPD_REG1_EXPECTED_SHIFT 0
#define APU_XPD_REG1_EXPECTED_WIDTH 32
#define APU_XPD_REG1_EXPECTED_MASK ((u32)0XFFFFFFFFU)
/**
* Register: APU_XPD_CTRL0
*/
#define APU_XPD_CTRL0 ( ( APU_BASEADDR ) + ((u32)0X00000608U) )
#define APU_XPD_CTRL0_DELAY_SPARE_SHIFT 25
#define APU_XPD_CTRL0_DELAY_SPARE_WIDTH 5
#define APU_XPD_CTRL0_DELAY_SPARE_MASK ((u32)0X3E000000U)
#define APU_XPD_CTRL0_CMP_SEL_SHIFT 24
#define APU_XPD_CTRL0_CMP_SEL_WIDTH 1
#define APU_XPD_CTRL0_CMP_SEL_MASK ((u32)0X01000000U)
#define APU_XPD_CTRL0_DELAY_CELL_TYPE_SHIFT 19
#define APU_XPD_CTRL0_DELAY_CELL_TYPE_WIDTH 5
#define APU_XPD_CTRL0_DELAY_CELL_TYPE_MASK ((u32)0X00F80000U)
#define APU_XPD_CTRL0_DELAY_VT_TYPE_SHIFT 17
#define APU_XPD_CTRL0_DELAY_VT_TYPE_WIDTH 2
#define APU_XPD_CTRL0_DELAY_VT_TYPE_MASK ((u32)0X00060000U)
#define APU_XPD_CTRL0_DELAY_VALUE_SHIFT 6
#define APU_XPD_CTRL0_DELAY_VALUE_WIDTH 11
#define APU_XPD_CTRL0_DELAY_VALUE_MASK ((u32)0X0001FFC0U)
#define APU_XPD_CTRL0_PATH_SEL_SHIFT 0
#define APU_XPD_CTRL0_PATH_SEL_WIDTH 6
#define APU_XPD_CTRL0_PATH_SEL_MASK ((u32)0X0000003FU)
/**
* Register: APU_XPD_CTRL1
*/
#define APU_XPD_CTRL1 ( ( APU_BASEADDR ) + ((u32)0X0000060CU) )
#define APU_XPD_CTRL1_CLK_SPARE_SHIFT 12
#define APU_XPD_CTRL1_CLK_SPARE_WIDTH 4
#define APU_XPD_CTRL1_CLK_SPARE_MASK ((u32)0X0000F000U)
#define APU_XPD_CTRL1_CLK_PHASE_SEL_SHIFT 10
#define APU_XPD_CTRL1_CLK_PHASE_SEL_WIDTH 2
#define APU_XPD_CTRL1_CLK_PHASE_SEL_MASK ((u32)0X00000C00U)
#define APU_XPD_CTRL1_CLK_VT_TYPE_SHIFT 8
#define APU_XPD_CTRL1_CLK_VT_TYPE_WIDTH 2
#define APU_XPD_CTRL1_CLK_VT_TYPE_MASK ((u32)0X00000300U)
#define APU_XPD_CTRL1_CLK_CELL_TYPE_SHIFT 6
#define APU_XPD_CTRL1_CLK_CELL_TYPE_WIDTH 2
#define APU_XPD_CTRL1_CLK_CELL_TYPE_MASK ((u32)0X000000C0U)
#define APU_XPD_CTRL1_CLK_INSERT_DLY_SHIFT 2
#define APU_XPD_CTRL1_CLK_INSERT_DLY_WIDTH 4
#define APU_XPD_CTRL1_CLK_INSERT_DLY_MASK ((u32)0X0000003CU)
#define APU_XPD_CTRL1_CLK_SEL_SHIFT 0
#define APU_XPD_CTRL1_CLK_SEL_WIDTH 2
#define APU_XPD_CTRL1_CLK_SEL_MASK ((u32)0X00000003U)
/**
* Register: APU_XPD_CTRL2
*/
#define APU_XPD_CTRL2 ( ( APU_BASEADDR ) + ((u32)0X00000614U) )
#define APU_XPD_CTRL2_CTRL_SPARE_SHIFT 1
#define APU_XPD_CTRL2_CTRL_SPARE_WIDTH 2
#define APU_XPD_CTRL2_CTRL_SPARE_MASK ((u32)0X00000006U)
#define APU_XPD_CTRL2_ENABLE_SHIFT 0
#define APU_XPD_CTRL2_ENABLE_WIDTH 1
#define APU_XPD_CTRL2_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: APU_XPD_CTRL3
*/
#define APU_XPD_CTRL3 ( ( APU_BASEADDR ) + ((u32)0X00000618U) )
#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_SHIFT 3
#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_WIDTH 12
#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_MASK ((u32)0X00007FF8U)
#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_SHIFT 2
#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_WIDTH 1
#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_MASK ((u32)0X00000004U)
#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_SHIFT 1
#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_WIDTH 1
#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_MASK ((u32)0X00000002U)
#define APU_XPD_CTRL3_DCYCLE_START_SHIFT 0
#define APU_XPD_CTRL3_DCYCLE_START_WIDTH 1
#define APU_XPD_CTRL3_DCYCLE_START_MASK ((u32)0X00000001U)
/**
* Register: APU_XPD_SOFT_RST
*/
#define APU_XPD_SOFT_RST ( ( APU_BASEADDR ) + ((u32)0X0000061CU) )
#define APU_XPD_SOFT_RST_CLK2_SHIFT 2
#define APU_XPD_SOFT_RST_CLK2_WIDTH 1
#define APU_XPD_SOFT_RST_CLK2_MASK ((u32)0X00000004U)
#define APU_XPD_SOFT_RST_CLK1_SHIFT 1
#define APU_XPD_SOFT_RST_CLK1_WIDTH 1
#define APU_XPD_SOFT_RST_CLK1_MASK ((u32)0X00000002U)
#define APU_XPD_SOFT_RST_CLK0_SHIFT 0
#define APU_XPD_SOFT_RST_CLK0_WIDTH 1
#define APU_XPD_SOFT_RST_CLK0_MASK ((u32)0X00000001U)
/**
* Register: APU_XPD_STAT
*/
#define APU_XPD_STAT ( ( APU_BASEADDR ) + ((u32)0X00000620U) )
#define APU_XPD_STAT_CMP_RESULT_SHIFT 1
#define APU_XPD_STAT_CMP_RESULT_WIDTH 1
#define APU_XPD_STAT_CMP_RESULT_MASK ((u32)0X00000002U)
#define APU_XPD_STAT_CMP_DONE_SHIFT 0
#define APU_XPD_STAT_CMP_DONE_WIDTH 1
#define APU_XPD_STAT_CMP_DONE_MASK ((u32)0X00000001U)
#ifdef __cplusplus
}
#endif
#endif /* _APU_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_board.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_board.h"
#include "xpm_common.h"
#include "xpm_pmc.h"
#include "xplmi_util.h"
#include "xpm_regs.h"
#include "xpm_pmbus.h"
#ifdef XPAR_XIICPS_1_DEVICE_ID
/**
* I2C master instance
*/
static XIicPs IicInstance;
/*****************************************************************************/
/**
* This function waits for the power rail to be fully powered on to prevent
* usage before complete. Timeout after max timeout.
*
* @param VoltageRailMask Mask to read power rail register value
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*
* @note This function is not PmBus dependent and can be used for any power
* rail connection
*****************************************************************************/
static XStatus XPmBoard_WaitForPowerRailUp(u32 VoltageRailMask)
{
XStatus Status = XST_FAILURE;
XPm_Pmc *Pmc;
Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
if (NULL == Pmc) {
goto done;
}
Status = XPlmi_UtilPollForMask((Pmc->PmcGlobalBaseAddr +
PWR_SUPPLY_STATUS_OFFSET),
VoltageRailMask,
XPLMI_TIME_OUT_DEFAULT);
if (XST_SUCCESS != Status) {
PmInfo("ERROR: Poll for power rail up timeout \r\n");
}
done:
return Status;
}
/**
* Forward declarations of private functions
*/
static XStatus XPmBoard_MuxConfigure(XIicPs * Iic, u16 MuxAddr, u8 Channel)
maybe_unused;
static XStatus XPmBoard_PowerUpRail(u8 RegulatorAddress, u32 PmcPowerSupplyMask)
maybe_unused;
static XStatus XPmBoard_PowerDownRail(u8 RegulatorAddress)
maybe_unused;
/*****************************************************************************/
/**
* This function initializes the I2C Bus
*
* @param Iic I2C instance
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*
* @note IIC_BASE_ADDR is currently hardcoded to be set to PMC I2C
*****************************************************************************/
static XStatus XPmBoard_IicInit(XIicPs *Iic)
{
XStatus Status = XST_FAILURE;
XIicPs_Config *Config;
/* Request the PMC_I2C device */
Status = XPm_RequestDevice(PM_SUBSYS_PMC, PM_DEV_I2C_PMC,
(u32)PM_CAP_ACCESS, XPM_MAX_QOS, 0);
if (XST_SUCCESS != Status) {
PmErr("Fail to request PMC_I2C device\n\r");
goto done;
}
Config = XIicPs_LookupConfig(IIC_DEVICE_ID);
if (NULL == Config) {
PmInfo("Could not find I2C\n\r");
goto done;
}
/* Initialize I2C base address and clock frequency */
Config->BaseAddress = IIC_BASE_ADDR;
Config->InputClockHz = IIC_CLK_FREQ_HZ;
Status = XIicPs_CfgInitialize(Iic, Config, Config->BaseAddress);
if (XST_SUCCESS != Status) {
PmErr("I2C initialization failure\n\r");
goto done;
}
/* Set the I2C serial clock rate */
Status = XIicPs_SetSClk(Iic, IIC_SCLK_RATE);
if (XST_SUCCESS != Status) {
PmErr("Failure setting I2C clock rate\n\r");
}
done:
return Status;
}
/***********************************************************************/
/* This function initializes the I2C Mux to select the required channel
*
* @param Iic I2C instance
* @param MuxAddr The address of the MUX
* @param channel The channel select value
*
* @return XST_SUCCESS or XST_FAILURE
***********************************************************************/
static XStatus XPmBoard_MuxConfigure(XIicPs *Iic, u16 MuxAddr, u8 Channel)
{
XStatus Status = XST_FAILURE;
u8 WriteBuffer[1]; /* mux channel select value */
/* Initialize the I2C instance if it has not been done already */
if ((u32)XIL_COMPONENT_IS_READY != Iic->IsReady) {
Status = XPmBoard_IicInit(Iic);
if (XST_SUCCESS != Status) {
PmErr("I2C initialization failure\n\r");
goto done;
}
}
WriteBuffer[0] = Channel;
/*
* Send configuration to Mux
* Wait for idle bus and check for arbitration
*/
do {
while (0 != XIicPs_BusIsBusy(Iic)) {};
Status = XIicPs_MasterSendPolled(Iic, WriteBuffer, 1, MuxAddr);
} while (XST_IIC_ARB_LOST == Status);
if (XST_SUCCESS != Status) {
PmErr("Failure to initialize Mux\n\r");
}
done:
return Status;
}
/*****************************************************************************/
/**
* This function sends PmBus commands to power up power rail
*
* @param RegulatorAddress Regulator address on Pmbus to be powered up
* @param PmcPowerSupplyMask Register mask for given regulator
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*****************************************************************************/
static XStatus XPmBoard_PowerUpRail(u8 RegulatorAddress,
u32 PmcPowerSupplyMask)
{
XStatus Status = XST_FAILURE;
Status = XPmBus_WriteByte(&IicInstance, RegulatorAddress,
ON_OFF_CONFIG, OP_POW_CTRL_CONFIG);
if (XST_SUCCESS != Status) {
PmErr("Failed to configure power regulator\r\n");
goto done;
}
Status = XPmBus_WriteByte(&IicInstance, RegulatorAddress,
OPERATION, PM_OP_POWER_UP);
if (XST_SUCCESS != Status) {
PmErr("Failed to power up power rail\r\n");
goto done;
}
Status = XPmBoard_WaitForPowerRailUp(PmcPowerSupplyMask);
done:
return Status;
}
/*****************************************************************************/
/**
* This function sends PmBus commands to power down power rail
*
* @param RegulatorAddress Regulator address on Pmbus to be powered down
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*****************************************************************************/
static XStatus XPmBoard_PowerDownRail(u8 RegulatorAddress)
{
XStatus Status = XST_FAILURE;
Status = XPmBus_WriteByte(&IicInstance, RegulatorAddress,
ON_OFF_CONFIG, OP_POW_CTRL_CONFIG);
if (XST_SUCCESS != Status) {
PmErr("Failed to configure power regulator\r\n");
goto done;
}
Status = XPmBus_WriteByte(&IicInstance, RegulatorAddress,
OPERATION, PM_OP_POWER_DOWN);
if (XST_SUCCESS != Status) {
PmErr("Failed to power down power rail\n");
}
done:
return Status;
}
#endif /* XPAR_XIICPS_1_DEVICE_ID */
/*****************************************************************************/
/**
* This function is used to control the power rails
*
* @param Function Action to be performed on power rail
* @param PowerRegulatorId Id given to a particular power rail
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*****************************************************************************/
XStatus XPmBoard_ControlRail(const enum power_rail_function Function,
const enum power_rail_id PowerRegulatorId)
{
XStatus Status = XST_FAILURE;
(void)Function;
(void)PowerRegulatorId;
#ifdef CUSTOM_PMBUS
u8 MuxChannel;
u8 RegulatorAddress;
u32 PmcPowerSupplyMask;
switch (PowerRegulatorId) {
case POWER_RAIL_FPD:
RegulatorAddress = PSFP_REGULATOR_ADDR;
MuxChannel = MUX_SEL_CHANNEL_0;
PmcPowerSupplyMask = PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_FPD_MASK;
break;
case POWER_RAIL_LPD:
RegulatorAddress = PSLP_REGULATOR_ADDR;
MuxChannel = MUX_SEL_CHANNEL_0;
PmcPowerSupplyMask = PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_LPD_MASK;
break;
/*TODO: Add cases for other power rails */
default:
PmErr("Invalid Regulator Id\n\r");
goto done;
}
#ifdef XPAR_XIICPS_1_DEVICE_ID
/* Configure Mux */
Status = XPmBoard_MuxConfigure(&IicInstance, I2C0_MUX_ADDR, MuxChannel);
if (XST_SUCCESS != Status) {
PmErr("Failure initializing I2C Mux\r\n");
goto done;
}
switch (Function) {
case RAIL_POWER_UP:
/* Send PMBus commands to Power up rail */
Status = XPmBoard_PowerUpRail(RegulatorAddress, PmcPowerSupplyMask);
if (XST_SUCCESS != Status) {
PmErr("Failure powering up power rail\n\r");
goto done;
}
break;
case RAIL_POWER_DOWN:
/* Send PMC_I2C command to turn off power rail */
Status = XPmBoard_PowerDownRail(RegulatorAddress);
if (XST_SUCCESS != Status) {
PmErr("Failure turning off power rail\n\r");
goto done;
}
break;
/* TODO: Add cases for other power rail actions */
default:
PmErr("Invalid Function Id\n\r");
goto done;
}
#endif /* XPAR_XIICPS_1_DEVICE_ID */
#endif /* CUSTOM_PMBUS */
Status = XST_SUCCESS;
#ifdef CUSTOM_PMBUS
done:
#endif
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/qspipsu_v1_11/src/xqspipsu.c
/******************************************************************************
* Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu.c
* @addtogroup qspipsu_v1_11
* @{
*
* This file implements the functions required to use the QSPIPSU hardware to
* perform a transfer. These are accessible to the user via xqspipsu.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.0 hk 08/21/14 First release
* sk 03/13/15 Added IO mode support.
* hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
* Clear and disable DMA interrupts/status in abort.
* Use DMA DONE bit instead of BUSY as recommended.
* sk 04/24/15 Modified the code according to MISRAC-2012.
* sk 06/17/15 Removed NULL checks for Rx/Tx buffers. As
* writing/reading from 0x0 location is permitted.
* 1.1 sk 04/12/16 Added debug message prints.
* 1.2 nsk 07/01/16 Changed XQspiPsu_Select to support GQSPI and LQSPI
* selection.
* rk 07/15/16 Added support for TapDelays at different frequencies.
* nsk 08/05/16 Added example support PollData and PollTimeout
* 1.3 nsk 09/16/16 Update PollData and PollTimeout support for dual
* parallel configurations, modified XQspiPsu_PollData()
* and XQspiPsu_Create_PollConfigData()
* 1,5 nsk 08/14/17 Added CCI support
* 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560)
* 1.7 tjs 01/17/18 Added a support to toggle WP pin of the flash.
* 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882)
* 1.8 tjs 06/26/18 Added an example for accessing 64bit dma within
* 32 bit application. CR#1004701
* 1.8 tjs 06/26/18 Removed checkpatch warnings.
* 1.8 tjs 07/09/18 Fixed cppcheck and doxygen warnings. (CR#1006336)
* 1.8 tjs 07/18/18 Setup64BRxDma() should be called only if the RxAddress is
* greater than 32 bit address space. (CR#1006862)
* 1.8 tjs 09/06/18 Fixed the code in XQspiPsu_GenFifoEntryData() for data
* transfer length up to 255 for reducing the extra loop.
* 1.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
* 1.9 tjs 11/22/17 Added the check for A72 and R5 processors (CR-987075)
* 1.9 tjs 04/17/18 Updated register addresses as per the latest revision
* of versal (CR#999610)
* 1.9 aru 01/17/19 Fixes violations according to MISRAC-2012
* in safety mode and modified the code such as
* Added UNITPTR inplace of INTPTR,Declared the pointer param
* as Pointer to const .
* 1.9 nsk 02/01/19 Clear DMA_DST_ADDR_MSB register on 32bit machine, if the
* address is of only 32bit (CR#1020031)
* 1.9 nsk 02/01/19 Added QSPI idling support.
* 1.9 rama 03/13/19 Fixed MISRA violations related to UR data anamoly,
* expression is not a boolean
* 1.9 nsk 03/27/19 Update 64bit dma support
* 1.10 sk 08/20/19 Fixed issues in poll timeout feature.
* 1.11 akm 02/19/20 Added XQspiPsu_StartDmaTransfer() and XQspiPsu_CheckDmaDone()
* APIs for non-blocking transfer.
* 1.11 sd 01/02/20 Added clocking support
* 1.11 akm 03/09/20 Reorganize the source code, enable qspi controller and
* interrupts in XQspiPsu_CfgInitialize() API.
* 1.11 akm 03/26/20 Fixed issue by updating XQspiPsu_CfgInitialize to return
* XST_DEVICE_IS_STARTED instead of asserting, when the
* instance is already configured.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xqspipsu.h"
#include "xqspipsu_control.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Initializes a specific XQspiPsu instance as such the driver is ready to use.
*
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param ConfigPtr is a reference to a structure containing information
* about a specific QSPIPSU device. This function initializes an
* InstancePtr object for a specific device specified by the
* contents of Config.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. The caller is responsible for keeping the address
* mapping from EffectiveAddr to the device physical base address
* unchanged once this function is invoked. Unexpected errors may
* occur if the address mapping changes after this function is
* called. If address translation is not used, use
* ConfigPtr->Config.BaseAddress for this device.
*
* @return
* - XST_SUCCESS if successful.
* - XST_DEVICE_IS_STARTED if the device is already started.
* It must be stopped to re-initialize.
*
* @note None.
*
******************************************************************************/
s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr,
const XQspiPsu_Config *ConfigPtr, u32 EffectiveAddr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
s32 Status;
/*
* If the device is busy, disallow the initialize and return a status
* indicating it is already started. This allows the user to stop the
* device and re-initialize, but prevents a user from inadvertently
* initializing. This assumes the busy flag is cleared at startup.
*/
if (InstancePtr->IsBusy == TRUE ||
InstancePtr->IsReady == XIL_COMPONENT_IS_READY) {
Status = (s32)XST_DEVICE_IS_STARTED;
} else {
/* Set some default values. */
InstancePtr->IsBusy = FALSE;
InstancePtr->Config.BaseAddress =
EffectiveAddr + XQSPIPSU_OFFSET;
InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
InstancePtr->StatusHandler = StubStatusHandler;
InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
#if defined (XCLOCKING)
InstancePtr->Config.RefClk = ConfigPtr->RefClk;
#endif
InstancePtr->Config.IsCacheCoherent =
ConfigPtr->IsCacheCoherent;
/* Other instance variable initializations */
InstancePtr->SendBufferPtr = NULL;
InstancePtr->RecvBufferPtr = NULL;
InstancePtr->GenFifoBufferPtr = NULL;
InstancePtr->TxBytes = 0;
InstancePtr->RxBytes = 0;
InstancePtr->GenFifoEntries = 0;
InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
InstancePtr->IsUnaligned = 0;
InstancePtr->IsManualstart = TRUE;
/* Select QSPIPSU */
XQspiPsu_Select(InstancePtr, XQSPIPSU_SEL_GQSPI_MASK);
/*
* Reset the QSPIPSU device to get it into its initial state.
* It is expected that device configuration will take place
* after this initialization is done, but before the device
* is started.
*/
XQspiPsu_Reset(InstancePtr);
/* Enable */
XQspiPsu_Enable(InstancePtr);
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
Status = XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/**
*
* Stops the transfer of data to internal DST FIFO from stream interface and
* also stops the issuing of new write commands to memory.
*
* By calling this API, any ongoing Dma transfers will be paused and DMA will
* not issue AXI write commands to memory
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XQspiPsu_Idle(const XQspiPsu *InstancePtr)
{
u32 RegEn;
u32 DmaStatus;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Check for QSPI enable */
RegEn = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_EN_OFFSET);
if ((RegEn & XQSPIPSU_EN_MASK) != 0U) {
DmaStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET);
DmaStatus |= XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK;
DmaStatus |= XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET, DmaStatus);
}
#if defined (XCLOCKING)
Xil_ClockDisable(InstancePtr->Config.RefClk);
#endif
}
/*****************************************************************************/
/**
*
* Resets the QSPIPSU device. Reset must only be called after the driver has
* been initialized. Any data transfer that is in progress is aborted.
*
* The upper layer software is responsible for re-configuring (if necessary)
* and restarting the QSPIPSU device after the reset.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XQspiPsu_Reset(XQspiPsu *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
#ifdef DEBUG
xil_printf("\nXQspiPsu_Reset\r\n");
#endif
/* Abort any transfer that is in progress */
XQspiPsu_Abort(InstancePtr);
/* Default value to config register */
XQspiPsu_SetDefaultConfig(InstancePtr);
}
/*****************************************************************************/
/**
*
* Aborts a transfer in progress.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
*
* @return None.
*
* @note
*
******************************************************************************/
void XQspiPsu_Abort(XQspiPsu *InstancePtr)
{
u32 IntrStatus, ConfigReg;
Xil_AssertVoid(InstancePtr != NULL);
#ifdef DEBUG
xil_printf("\nXQspiPsu_Abort\r\n");
#endif
IntrStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_ISR_OFFSET);
/* Clear and disable interrupts */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_ISR_OFFSET, IntrStatus | XQSPIPSU_ISR_WR_TO_CLR_MASK);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET));
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_STS_OFFSET,
XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_STS_OFFSET) |
XQSPIPSU_QSPIDMA_DST_STS_WTC);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_IDR_OFFSET, XQSPIPSU_IDR_ALL_MASK);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK);
/* Clear FIFO */
if ((XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_ISR_OFFSET) & XQSPIPSU_ISR_RXEMPTY_MASK) != FALSE)
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_FIFO_CTRL_OFFSET, XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK |
XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK);
/*
* Switch to IO mode to Clear RX FIFO. This is because of DMA behaviour
* where it waits on RX empty and goes busy assuming there is data
* to be transferred even if there is no request.
*/
if ((IntrStatus & XQSPIPSU_ISR_RXEMPTY_MASK) != 0U) {
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET, ConfigReg);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_FIFO_CTRL_OFFSET,
XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK);
if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET, ConfigReg);
}
}
InstancePtr->TxBytes = 0;
InstancePtr->RxBytes = 0;
InstancePtr->GenFifoEntries = 0;
InstancePtr->IsBusy = FALSE;
}
/*****************************************************************************/
/**
* This is the handler for polling functionality of controller. It reads data
* from RXFIFO, since when data from the flash device (status data) matched
* with configured value in poll_cfg, then controller writes the matched data
* into RXFIFO.
*
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.l
* @param Index is the message number to be transferred.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XQspiPsu_PollDataHandler(XQspiPsu *InstancePtr, u32 StatusReg)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
xil_printf("\nXQspiPsu_PollDataHandler\r\n");
#endif
if ((StatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK) != FALSE) {
/*
* Read data from RXFIFO, since when data from the
* flash device (status data) matched with configured
* value in poll_cfg, then controller writes the
* matched data into RXFIFO.
*/
(void)XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_RXD_OFFSET);
InstancePtr->StatusHandler(InstancePtr->StatusRef,
XST_SPI_POLL_DONE, 0);
}
if ((StatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK) != FALSE)
InstancePtr->StatusHandler(InstancePtr->StatusRef,
XST_FLASH_TIMEOUT_ERROR, 0);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_IDR_OFFSET,
(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
(u32)XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK);
InstancePtr->IsBusy = FALSE;
if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA)
XQspiPsu_SetReadMode(InstancePtr, XQSPIPSU_READMODE_DMA);
/* De-select slave */
XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
XQspiPsu_ManualStartEnable(InstancePtr);
}
/*****************************************************************************/
/**
*
* This function performs a transfer on the bus in polled mode. The messages
* passed are all transferred on the bus between one CS assert and de-assert.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
* @param NumMsg is the number of messages to be transferred.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if transfer fails.
* - XST_DEVICE_BUSY if a transfer is already in progress.
*
* @note None.
*
******************************************************************************/
s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 NumMsg)
{
s32 Index;
u32 QspiPsuStatusReg;
u32 IOPending = (u32)FALSE;
u32 DmaIntrSts;
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Msg != NULL);
Xil_AssertNonvoid(NumMsg > 0);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
for (Index = 0; Index < (s32)NumMsg; Index++)
Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
/*
* Check whether there is another transfer in progress.
* Not thread-safe
*/
if (InstancePtr->IsBusy == TRUE) {
Status = (s32)XST_DEVICE_BUSY;
goto END;
}
/* Check for ByteCount upper limit - 2^28 for DMA */
for (Index = 0; Index < (s32)NumMsg; Index++) {
if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
Status = XST_FAILURE;
goto END;
}
}
/*
* Set the busy flag, which will be cleared when the transfer is
* entirely done.
*/
InstancePtr->IsBusy = TRUE;
#if defined (XCLOCKING)
Xil_ClockEnable(InstancePtr->Config.RefClk);
#endif
/* Select slave */
XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
/* list */
Index = 0;
while (Index < (s32)NumMsg) {
XQspiPsu_GenFifoEntryData(InstancePtr, &Msg[Index]);
XQspiPsu_ManualStartEnable(InstancePtr);
/* Use thresholds here */
/* If there is more data to be transmitted */
do {
QspiPsuStatusReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_ISR_OFFSET);
/* Transmit more data if left */
if (((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) != FALSE) &&
((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
(InstancePtr->TxBytes > 0))
XQspiPsu_FillTxFifo(InstancePtr, &Msg[Index],
(u32)XQSPIPSU_TXD_DEPTH);
/* Check if DMA RX is complete and update RxBytes */
if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
DmaIntrSts = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
if ((DmaIntrSts &
XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET, DmaIntrSts);
IOPending = XQspiPsu_SetIOMode(InstancePtr, &Msg[Index]);
InstancePtr->RxBytes = 0;
if (IOPending == (u32)TRUE)
break;
}
} else if ((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)
XQspiPsu_IORead(InstancePtr, &Msg[Index], QspiPsuStatusReg);
} while (((QspiPsuStatusReg &
XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE) ||
(InstancePtr->TxBytes != 0) ||
((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) == FALSE) ||
(InstancePtr->RxBytes != 0));
if ((InstancePtr->IsUnaligned != 0) && (IOPending == (u32)FALSE)) {
InstancePtr->IsUnaligned = 0;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
(XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) |
XQSPIPSU_CFG_MODE_EN_DMA_MASK));
InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
}
if (IOPending == (u32)TRUE)
IOPending = (u32)FALSE;
else
Index++;
}
/* De-select slave */
XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
XQspiPsu_ManualStartEnable(InstancePtr);
do
QspiPsuStatusReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_ISR_OFFSET);
while ((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE);
/* Clear the busy flag. */
InstancePtr->IsBusy = FALSE;
Status = XST_SUCCESS;
#if defined (XCLOCKING)
Xil_ClockDisable(InstancePtr->Config.RefClk);
#endif
END:
return Status;
}
/*****************************************************************************/
/**
*
* This function initiates a transfer on the bus and enables interrupts.
* The transfer is completed by the interrupt handler. The messages passed are
* all transferred on the bus between one CS assert and de-assert.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
* @param NumMsg is the number of messages to be transferred.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if transfer fails.
* - XST_DEVICE_BUSY if a transfer is already in progress.
*
* @note None.
*
******************************************************************************/
s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 NumMsg)
{
s32 Index;
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
for (Index = 0; Index < (s32)NumMsg; Index++)
Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
/*
* Check whether there is another transfer in progress.
* Not thread-safe
*/
if (InstancePtr->IsBusy == TRUE) {
Status = (s32)XST_DEVICE_BUSY;
goto END;
}
#if defined (XCLOCKING)
Xil_ClockEnable(InstancePtr->Config.RefClk);
#endif
if ((Msg[0].Flags & XQSPIPSU_MSG_FLAG_POLL) != FALSE) {
InstancePtr->IsBusy = TRUE;
XQspiPsu_PollDataConfig(InstancePtr, Msg);
} else {
/* Check for ByteCount upper limit - 2^28 for DMA */
for (Index = 0; Index < (s32)NumMsg; Index++) {
if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
Status = XST_FAILURE;
goto END;
}
}
/*
* Set the busy flag, which will be cleared when the transfer is
* entirely done.
*/
InstancePtr->IsBusy = TRUE;
InstancePtr->Msg = Msg;
InstancePtr->NumMsg = (s32)NumMsg;
InstancePtr->MsgCnt = 0;
/* Select slave */
XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
/* This might not work if not manual start */
/* Put first message in FIFO along with the above slave select */
XQspiPsu_GenFifoEntryData(InstancePtr, &Msg[0]);
XQspiPsu_ManualStartEnable(InstancePtr);
/* Enable interrupts */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_IER_OFFSET,
(u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
(u32)XQSPIPSU_IER_TXEMPTY_MASK |
(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
(u32)XQSPIPSU_IER_RXEMPTY_MASK);
if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA)
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET,
XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
}
Status = XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
*
* Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if transfer fails.
*
* @note None.
*
******************************************************************************/
s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
{
u32 QspiPsuStatusReg, DmaIntrStatusReg = 0;
XQspiPsu_Msg *Msg;
s32 NumMsg;
s32 MsgCnt;
u8 DeltaMsgCnt = 0;
u32 TxRxFlag;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->NumMsg > 0);
Xil_AssertNonvoid(InstancePtr->Msg != NULL);
Msg = InstancePtr->Msg;
NumMsg = InstancePtr->NumMsg;
MsgCnt = InstancePtr->MsgCnt;
TxRxFlag = Msg[MsgCnt].Flags;
/* QSPIPSU Intr cleared on read */
QspiPsuStatusReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_ISR_OFFSET);
if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
/* DMA Intr write to clear */
DmaIntrStatusReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
DmaIntrStatusReg);
}
if (((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK) != FALSE))
/* Call status handler to indicate error */
InstancePtr->StatusHandler(InstancePtr->StatusRef,
XST_SPI_COMMAND_ERROR, 0);
/* Fill more data to be txed if required */
if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) != FALSE) &&
(InstancePtr->TxBytes > 0))
XQspiPsu_FillTxFifo(InstancePtr, &Msg[MsgCnt], (u32)XQSPIPSU_TXD_DEPTH);
/*
* Check if the entry is ONLY TX and increase MsgCnt.
* This is to allow TX and RX together in one entry - corner case.
*/
if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) != FALSE) &&
((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
(InstancePtr->TxBytes == 0) &&
((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) == FALSE)) {
MsgCnt += 1;
DeltaMsgCnt = 1U;
}
if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
(MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
if ((DmaIntrStatusReg &
XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
if (XQspiPsu_SetIOMode(InstancePtr, &Msg[MsgCnt])) {
XQspiPsu_GenFifoEntryData(InstancePtr, &Msg[MsgCnt]);
XQspiPsu_ManualStartEnable(InstancePtr);
} else {
InstancePtr->RxBytes = 0;
MsgCnt += 1;
DeltaMsgCnt = 1U;
}
}
} else if ((MsgCnt < NumMsg) &&
((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
if (InstancePtr->RxBytes != 0) {
XQspiPsu_IORead(InstancePtr, &Msg[MsgCnt], QspiPsuStatusReg);
if (InstancePtr->RxBytes == 0) {
MsgCnt += 1;
DeltaMsgCnt = 1U;
}
}
}
/*
* Dummy byte transfer
* MsgCnt < NumMsg check is to ensure is it a valid dummy cycle message
* If one of the above conditions increased MsgCnt, then
* the new message is yet to be placed in the FIFO; hence !DeltaMsgCnt.
*/
if ((MsgCnt < NumMsg) && (DeltaMsgCnt == FALSE) &&
((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) == FALSE) &&
((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) == FALSE) &&
((TxRxFlag & XQSPIPSU_MSG_FLAG_POLL) == FALSE) &&
((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE)) {
MsgCnt += 1;
DeltaMsgCnt = 1U;
}
InstancePtr->MsgCnt = MsgCnt;
/*
* DeltaMsgCnt is to handle conditions where genfifo empty can be set
* while tx is still not empty or rx dma is not yet done.
* MsgCnt > NumMsg indicates CS de-assert entry was also executed.
*/
if (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
((DeltaMsgCnt != FALSE) || (MsgCnt > NumMsg))) {
if (MsgCnt < NumMsg) {
if (InstancePtr->IsUnaligned != 0) {
InstancePtr->IsUnaligned = 0;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) |
XQSPIPSU_CFG_MODE_EN_DMA_MASK));
InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
}
/* This might not work if not manual start */
XQspiPsu_GenFifoEntryData(InstancePtr, &Msg[MsgCnt]);
XQspiPsu_ManualStartEnable(InstancePtr);
} else if (MsgCnt == NumMsg) {
/* This is just to keep track of the de-assert entry */
MsgCnt += 1;
InstancePtr->MsgCnt = MsgCnt;
/* De-select slave */
XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
XQspiPsu_ManualStartEnable(InstancePtr);
} else {
/* Disable interrupts */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_IDR_OFFSET,
(u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
(u32)XQSPIPSU_IER_TXEMPTY_MASK |
(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
(u32)XQSPIPSU_IER_RXEMPTY_MASK);
if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA)
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
/* Clear the busy flag. */
InstancePtr->IsBusy = FALSE;
#if defined (XCLOCKING)
Xil_ClockDisable(InstancePtr->Config.RefClk);
#endif
/* Call status handler to indicate completion */
InstancePtr->StatusHandler(InstancePtr->StatusRef,
XST_SPI_TRANSFER_DONE, 0);
}
}
if ((TxRxFlag & XQSPIPSU_MSG_FLAG_POLL) != FALSE)
XQspiPsu_PollDataHandler(InstancePtr, QspiPsuStatusReg);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Sets the status callback function, the status handler, which the driver
* calls when it encounters conditions that should be reported to upper
* layer software. The handler executes in an interrupt context, so it must
* minimize the amount of processing performed. One of the following status
* events is passed to the status handler.
*
* <pre>
*
* XST_SPI_TRANSFER_DONE The requested data transfer is done
*
* XST_SPI_TRANSMIT_UNDERRUN As a slave device, the master clocked data
* but there were none available in the transmit
* register/FIFO. This typically means the slave
* application did not issue a transfer request
* fast enough, or the processor/driver could not
* fill the transmit register/FIFO fast enough.
*
* XST_SPI_RECEIVE_OVERRUN The QSPIPSU device lost data. Data was received
* but the receive data register/FIFO was full.
*
* </pre>
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param CallBackRef is the upper layer callback reference passed back
* when the callback function is invoked.
* @param FuncPointer is the pointer to the callback function.
*
* @return None.
*
* @note
*
* The handler is called within interrupt context, so it should do its work
* quickly and queue potentially time-consuming work to a task-level thread.
*
******************************************************************************/
void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
XQspiPsu_StatusHandler FuncPointer)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FuncPointer != NULL);
Xil_AssertVoid(CallBackRef != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
InstancePtr->StatusHandler = FuncPointer;
InstancePtr->StatusRef = CallBackRef;
}
/*****************************************************************************/
/**
* @brief
* This API enables/ disables Write Protect pin on the flash parts.
*
* @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use.
*
* @param Toggle is a value of the GPIO pin
*
* @return None
*
* @note By default WP pin as per the QSPI controller is driven High
* which means no write protection. Calling this function once
* will enable the protection.
*
******************************************************************************/
void XQspiPsu_WriteProtectToggle(const XQspiPsu *InstancePtr, u32 Toggle)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* For Single and Stacked flash configuration with x1 or x2 mode*/
if (InstancePtr->Config.ConnectionMode ==
XQSPIPSU_CONNECTION_MODE_SINGLE) {
/* Select slave */
XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_GPIO_OFFSET, Toggle);
} else {
#ifdef DEBUG
xil_printf("Dual Parallel/Stacked configuration ");
xil_printf("is not supported by this API\r\n");
#endif
}
}
/*****************************************************************************/
/**
*
* This function start a DMA transfer.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
* @param NumMsg is the number of messages to be transferred.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if ByteCount is greater than
* XQSPIPSU_DMA_BYTES_MAX.
* - XST_DEVICE_BUSY if a transfer is already in progress.
*
* @note None.
*
*
******************************************************************************/
s32 XQspiPsu_StartDmaTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 NumMsg)
{
s32 Index;
u32 QspiPsuStatusReg = 0;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Msg != NULL);
Xil_AssertNonvoid(NumMsg > 0);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
for (Index = 0; Index < (s32)NumMsg; Index++) {
Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
}
/*
* Check whether there is another transfer in progress.
* Not thread-safe
*/
if (InstancePtr->IsBusy == TRUE) {
return (s32)XST_DEVICE_BUSY;
}
/* Check for ByteCount upper limit - 2^28 for DMA */
for (Index = 0; Index < (s32)NumMsg; Index++) {
if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE))
return (s32)XST_FAILURE;
}
/*
* Set the busy flag, which will be cleared when the transfer is
* entirely done.
*/
InstancePtr->IsBusy = TRUE;
/* Select slave */
XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
/* list */
Index = 0;
while (Index < (s32)NumMsg) {
XQspiPsu_GenFifoEntryData(InstancePtr, &Msg[Index]);
if (InstancePtr->IsManualstart == TRUE) {
#ifdef DEBUG
xil_printf("\nManual Start\r\n");
#endif
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET) |
XQSPIPSU_CFG_START_GEN_FIFO_MASK);
}
do {
if((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE))
break;
QspiPsuStatusReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_ISR_OFFSET);
}while (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE) ||
(InstancePtr->TxBytes != 0) ||
((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) == FALSE));
if(InstancePtr->ReadMode == XQSPIPSU_READMODE_IO) {
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) |
XQSPIPSU_CFG_MODE_EN_DMA_MASK));
InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
}
Index++;
}
return (s32)XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function check for DMA transfer complete.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
*
* @return
* - XST_SUCCESS if DMA transfer complete.
* - XST_FAILURE if DMA transfer is not completed.
*
* @note None.
*
******************************************************************************/
s32 XQspiPsu_CheckDmaDone(XQspiPsu *InstancePtr)
{
u32 QspiPsuStatusReg;
u32 DmaIntrSts;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
DmaIntrSts = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
if ((DmaIntrSts & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET, DmaIntrSts);
/* De-select slave */
XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
if (InstancePtr->IsManualstart == TRUE) {
#ifdef DEBUG
xil_printf("\nManual Start\r\n");
#endif
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) |
XQSPIPSU_CFG_START_GEN_FIFO_MASK);
}
do
QspiPsuStatusReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_ISR_OFFSET);
while ((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE);
/* Clear the busy flag. */
InstancePtr->IsBusy = FALSE;
return (s32)XST_SUCCESS;
}
else {
return (s32)XST_FAILURE;
}
}
/** @} */
<file_sep>/python_drivers/tdc_server_run.py
# -*- coding: utf-8 -*-
"""
Created on Thu Jul 16 20:00:58 2020
@author: tianlab01
"""
import tdc_wrapper
tdc_server = tdc_wrapper.tdc_wrapper(15,0,tdc_wrapper.MODE_SERVER,"")
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilfpga_v5_2/src/interface/zynqmp/xilfpga_pcap.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilfpga_pcap.h
*
* The XILFPGA library provides the interface to the application to configure
* the programmable logic (PL) though the PS.
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 Nava 08/06/16 Initial release
* 1.1 Nava 16/11/16 Added PL power-up sequence.
* 2.0 Nava 10/1/17 Added Encrypted bitstream loading support.
* 2.0 Nava 16/02/17 Added Authenticated bitstream loading support.
* 2.1 Nava 06/05/17 Correct the check logic issues in
* XFpga_PL_BitStream_Load()
* to avoid the unwanted blocking conditions.
* 3.0 Nava 12/05/17 Added PL configuration registers readback support.
* 4.0 Nava 08/02/18 Added Authenticated and Encypted Bitstream
loading support.
* 4.0 Nava 02/03/18 Added the legacy bit file loading feature support
* from U-boot.and improve the error handling support
* by returning the proper ERROR value upon error
* conditions.
* 4.1 Nava 27/03/18 For Secure Bitstream loading to avoid the Security
* violations Need to Re-validate the User Crypto flags
* with the Image Crypto operation by using the internal
* memory.To Fix this added a new API
* XFpga_ReValidateCryptoFlags().
* 4.1 Nava 16/04/18 Added partial bitstream loading support.
* 4.2 Nava 08/06/16 Refactor the xilfpga library to support
* different PL programming Interfaces.
* 4.2 adk 11/07/18 Added support for readback of PL configuration data.
* 4.2 Nava 22/07/18 Added XFpga_SelectEndianess() new API to Support
* programming the vivado generated .bit and .bin files
* 4.2 adk 03/08/18 Added example for partial reconfiguration.
* 4.2 Nava 16/08/18 Modified the PL data handling Logic to support
* different PL programming interfaces.
* 4.2 Nava 15/09/18 Fixed global function call-backs issue.
* 5.0 Div 21/01/19 Fixed misra-c required standard violations.
* 5.0 Nava 06/02/19 Remove redundant API's from the interface agnostic layer
* and make the existing API's generic to support both
* ZynqMP and versal platforms.
* 5.0 Nava 26/02/19 Fix for power-up PL issue with pmufw.
* 5.0 Nava 26/02/19 Update the data handling logic to avoid the code
* duplication
* 5.0 Nava 28/02/19 Handling all the 4 PS-PL resets irrespective of the
* design configuration.
* 5.0 Nava 21/03/19 Added Address alignment check. As CSUDMA expects word
* aligned address. In case user passes an unaligned
* address return error.
* 5.0 sne 27/03/19 Fixed misra-c violations.
* 5.0 Nava 23/04/19 Optimize the API's logic to avoid code duplication.
* 5.2 Nava 18/12/19 Fix for security violation in the readback path.
* 5.2 Nava 14/02/20 Added Bitstream loading support by using IPI services.
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XILFPGA_PCAP_H
#define XILFPGA_PCAP_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xcsudma.h"
#include "xsecure.h"
#include "xil_util.h"
/************************** Constant Definitions *****************************/
#define PL_DONE_POLL_COUNT 300000U
#define PL_RESET_PERIOD_IN_US 1U
/* Dummy address to indicate that destination is PCAP */
#define XFPGA_CSU_SSS_SRC_SRC_DMA (0x5U)
#define XFPGA_CSU_SSS_SRC_DST_DMA (0x30U)
#define XFPGA_CSU_SSS_DMA_TO_DMA (0x50U)
/* Boot Header Image Offsets */
#define PARTATION_HEADER_OFFSET (0x9cU)
#define PARTATION_ATTRIBUTES_OFFSET (0x24U)
#define BITSTREAM_PARTATION_OFFSET (0x20U)
#define BITSTREAM_IV_OFFSET (0xA0U)
/**
* CSU Base Address
*/
#define XILFPGA_CSU_BASEADDR 0XFFCA0000U
/**
* Register: CSU_CSU_SSS_CFG
*/
#define CSU_CSU_SSS_CFG ((XILFPGA_CSU_BASEADDR) + 0X00000008U)
#define CSU_CSU_SSS_CFG_PCAP_SSS_MASK 0X0000000FU
#define CSU_CSU_SSS_CFG_PCAP_SSS_SHIFT 0U
/**
* Register: CSU_PCAP_STATUS
*/
#define CSU_PCAP_STATUS ((XILFPGA_CSU_BASEADDR) + 0X00003010U)
#define CSU_PCAP_STATUS_PL_INIT_SHIFT 2U
#define CSU_PCAP_STATUS_PL_INIT_MASK 0X00000004U
#define PCAP_STATUS_PCAP_WR_IDLE_MASK 0X00000001U
#define PCAP_STATUS_PCAP_RD_IDLE_MASK 0X00000002U
#define CSU_PCAP_STATUS_PCAP_RD_SHIFT 1U
#define CSU_PCAP_STATUS_PL_DONE_MASK 0X00000008U
/* Register: CSU_PCAP_RESET */
#define CSU_PCAP_RESET ((XILFPGA_CSU_BASEADDR) + 0X0000300CU)
#define CSU_PCAP_RESET_RESET_MASK 0X00000001U
/* Register: CSU_PCAP_CTRL */
#define CSU_PCAP_CTRL ((XILFPGA_CSU_BASEADDR) + 0X00003008U)
#define CSU_PCAP_CTRL_PCAP_PR_MASK 0X00000001U
/**
* Register: CSU_PCAP_RDWR
*/
#define CSU_PCAP_RDWR ((XILFPGA_CSU_BASEADDR) + 0X00003004U)
#define CSU_PCAP_RDWR_PCAP_RDWR_B_SHIFT 0U
/* Register: CSU_PCAP_PROG */
#define CSU_PCAP_PROG ((XILFPGA_CSU_BASEADDR) + 0X00003000U)
#define CSU_PCAP_PROG_PCFG_PROG_B_MASK 0X00000001U
#define CSU_PCAP_PROG_PCFG_PROG_B_SHIFT 0U
/* Register: PMU_GLOBAL for PL power-up */
#define PMU_GLOBAL_BASE 0xFFD80000U
#define PMU_GLOBAL_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110U)
#define PMU_GLOBAL_PWRUP_EN (PMU_GLOBAL_BASE + 0x118U)
#define PMU_GLOBAL_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120U)
#define PMU_GLOBAL_PWR_PL_MASK 0x800000U
#define PMU_GLOBAL_GEN_STORAGE5 (PMU_GLOBAL_BASE + 0x44U)
#define PMU_GLOBAL_ISO_INT_EN (PMU_GLOBAL_BASE + 0X318U)
#define PMU_GLOBAL_ISO_TRIG (PMU_GLOBAL_BASE + 0X320U)
#define PMU_GLOBAL_ISO_STATUS (PMU_GLOBAL_BASE + 0X310U)
#define PMU_GLOBAL_ISO_NONPCAP_MASK 0X00000004U
#define GPIO_DIRM_5_EMIO 0xFF0A0344U
#define GPIO_MASK_DATA_5_MSW 0xFF0A002CU
#define GPIO_PS_PL_DIRM_MASK 0xF0000000U
#define GPIO_LOW_DATA_MSW_VAL 0x0FFF0000U
#define GPIO_HIGH_DATA_MSW_VAL 0x0FFFF000U
/* Register: PCAP_CLK_CTRL Address */
#define PCAP_CLK_CTRL 0xFF5E00A4U
#define PCAP_CLK_EN_MASK 0x01000000U
/* AES KEY SRC Info */
#define XFPGA_KEY_SRC_EFUSE_RED 0xA5C3C5A3U
#define XFPGA_KEY_SRC_BBRAM_RED 0x3A5C3C5AU
#define XFPGA_KEY_SRC_EFUSE_BLK 0xA5C3C5A5U
#define XFPGA_KEY_SRC_BH_BLACK 0xA35C7C53U
#define XFPGA_KEY_SRC_EFUSE_GRY 0xA5C3C5A7U
#define XFPGA_KEY_SRC_BH_GRY 0xA35C7CA5U
#define XFPGA_KEY_SRC_KUP 0xA3A5C3C5U
/* Error Codes */
#define XFPGA_ERROR_CSUDMA_INIT_FAIL (0x2U)
#define XFPGA_ERROR_PL_POWER_UP (0x3U)
#define XFPGA_ERROR_PL_ISOLATION (0x4U)
#define XPFGA_ERROR_PCAP_INIT (0x5U)
#define XFPGA_ERROR_BITSTREAM_LOAD_FAIL (0x6U)
#define XFPGA_ERROR_CRYPTO_FLAGS (0x7U)
#define XFPGA_ERROR_HDR_AUTH (0X8U)
#define XFPGA_ENC_ISCOMPULSORY (0x9U)
#define XFPGA_PARTITION_AUTH_FAILURE (0xAU)
#define XFPGA_STRING_INVALID_ERROR (0xBU)
#define XFPGA_ERROR_SECURE_CRYPTO_FLAGS (0xCU)
#define XFPGA_ERROR_SECURE_MODE_EN (0xDU)
#define XFPGA_HDR_NOAUTH_PART_AUTH (0xEU)
#define XFPGA_DEC_WRONG_KEY_SOURCE (0xFU)
#define XFPGA_ERROR_DDR_AUTH_VERIFY_SPK (0x10U)
#define XFPGA_ERROR_DDR_AUTH_PARTITION (0x11U)
#define XFPGA_ERROR_DDR_AUTH_WRITE_PL (0x12U)
#define XFPGA_ERROR_OCM_AUTH_VERIFY_SPK (0x13U)
#define XFPGA_ERROR_OCM_AUTH_PARTITION (0x14U)
#define XFPGA_ERROR_OCM_REAUTH_WRITE_PL (0x15U)
#define XFPGA_ERROR_PCAP_PL_DONE (0x16U)
#define XFPGA_ERROR_AES_DECRYPT_PL (0x17U)
#define XFPGA_ERROR_CSU_PCAP_TRANSFER (0x18U)
#define XFPGA_ERROR_PLSTATE_UNKNOWN (0x19U)
#define XFPGA_ERROR_BITSTREAM_FORMAT (0x1AU)
#define XFPGA_ERROR_UNALIGN_ADDR (0x1BU)
#define XFPGA_ERROR_AES_INIT (0x1CU)
#define XFPGA_ERROR_EFUSE_CHECK (0x1DU)
/* PCAP Error Update Macro */
#define XFPGA_PCAP_ERR_MASK (0xFF00U)
#define XFPGA_ERR_MODULE_MASK (0xFFFF0000U)
#define XFPGA_PCAP_UPDATE_ERR(XfpgaPcapErr, ModuleErr) \
(((ModuleErr) << (u32)16U) & XFPGA_ERR_MODULE_MASK) + \
(((XfpgaPcapErr) << (u32)8U) & XFPGA_PCAP_ERR_MASK)
#define XFPGA_STATE_MASK 0x00FF0000U
#define XFPGA_STATE_SHIFT 16U
/**************************** Type Definitions *******************************/
typedef struct {
XSecure_Aes *SecureAes; /* AES initialized structure */
u32 NextBlkLen; /* Not required for user, used
* for storing next block size
*/
} XFpgaPs_PlEncryption;
typedef struct {
XFpgaPs_PlEncryption PlEncrypt; /* Encryption parameters */
u8 SecureHdr[XSECURE_SECURE_HDR_SIZE + XSECURE_SECURE_GCM_TAG_SIZE];
u8 Hdr;
XSecure_Sss SssInstance;
} XFpgaPs_PlPartition;
/**
* Structure to store the PL Image details.
*
* @XSecure_ImageInfo Used to store the secure image data.
* @PlAesInfo used to store the encrypted image data.
* @Secure_Aes The AES-GCM driver instance data structure
* @TotalBitPartCount Used to store the number of Authenticated partitions info.
* @SecureOcmState Used to Preserve the initialization states for the OCM
* use cases.
* @RemaningBytes used to preserve the remaining byte to process Authenticated
* bitstream Images.
* @AcPtr Used to Access the authenticate certificate buffer address
* @BitAddr Used to Access the Bitstream buffer Address.
*/
typedef struct {
XSecure_ImageInfo SecureImageInfo;
XFpgaPs_PlPartition PlAesInfo;
XSecure_Aes Secure_Aes;
u32 TotalBitPartCount;
u32 SecureOcmState;
u32 RemaningBytes;
UINTPTR AcPtr;
UINTPTR BitAddr;
} XFpga_Info;
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* XILFPGA_PCAP_H */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/zynqmp/client/rpu/pm_rpu.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef PM_RPU_H
#define PM_RPU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* RPU Base Address
*/
#define RPU_BASEADDR 0XFF9A0000U
/**
* Register: RPU_RPU_GLBL_CNTL
*/
#define RPU_RPU_GLBL_CNTL ( ( RPU_BASEADDR ) + 0X00000000U )
#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_SHIFT 10U
#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_WIDTH 1U
#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_MASK 0X00000400U
#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_SHIFT 8U
#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_WIDTH 1U
#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_MASK 0X00000100U
#define RPU_RPU_GLBL_CNTL_TCM_WAIT_SHIFT 7U
#define RPU_RPU_GLBL_CNTL_TCM_WAIT_WIDTH 1U
#define RPU_RPU_GLBL_CNTL_TCM_WAIT_MASK 0X00000080U
#define RPU_RPU_GLBL_CNTL_TCM_COMB_SHIFT 6U
#define RPU_RPU_GLBL_CNTL_TCM_COMB_WIDTH 1U
#define RPU_RPU_GLBL_CNTL_TCM_COMB_MASK 0X00000040U
#define RPU_RPU_GLBL_CNTL_TEINIT_SHIFT 5U
#define RPU_RPU_GLBL_CNTL_TEINIT_WIDTH 1U
#define RPU_RPU_GLBL_CNTL_TEINIT_MASK 0X00000020U
#define RPU_RPU_GLBL_CNTL_SLCLAMP_SHIFT 4U
#define RPU_RPU_GLBL_CNTL_SLCLAMP_WIDTH 1U
#define RPU_RPU_GLBL_CNTL_SLCLAMP_MASK 0X00000010U
#define RPU_RPU_GLBL_CNTL_SLSPLIT_SHIFT 3U
#define RPU_RPU_GLBL_CNTL_SLSPLIT_WIDTH 1U
#define RPU_RPU_GLBL_CNTL_SLSPLIT_MASK 0X00000008U
#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_SHIFT 2U
#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_WIDTH 1U
#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_MASK 0X00000004U
#define RPU_RPU_GLBL_CNTL_CFGIE_SHIFT 1U
#define RPU_RPU_GLBL_CNTL_CFGIE_WIDTH 1U
#define RPU_RPU_GLBL_CNTL_CFGIE_MASK 0X00000002U
#define RPU_RPU_GLBL_CNTL_CFGEE_SHIFT 0U
#define RPU_RPU_GLBL_CNTL_CFGEE_WIDTH 1U
#define RPU_RPU_GLBL_CNTL_CFGEE_MASK 0X00000001U
/**
* Register: RPU_RPU_GLBL_STATUS
*/
#define RPU_RPU_GLBL_STATUS ( ( RPU_BASEADDR ) + 0X00000004U )
#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_SHIFT 0U
#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_WIDTH 1U
#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_MASK 0X00000001U
/**
* Register: RPU_RPU_ERR_CNTL
*/
#define RPU_RPU_ERR_CNTL ( ( RPU_BASEADDR ) + 0X00000008U )
#define RPU_RPU_ERR_CNTL_APB_ERR_RES_SHIFT 0U
#define RPU_RPU_ERR_CNTL_APB_ERR_RES_WIDTH 1U
#define RPU_RPU_ERR_CNTL_APB_ERR_RES_MASK 0X00000001U
/**
* Register: RPU_RPU_RAM
*/
#define RPU_RPU_RAM ( ( RPU_BASEADDR ) + 0X0000000CU )
#define RPU_RPU_RAM_RAMCONTROL1_SHIFT 8U
#define RPU_RPU_RAM_RAMCONTROL1_WIDTH 8U
#define RPU_RPU_RAM_RAMCONTROL1_MASK 0X0000FF00U
#define RPU_RPU_RAM_RAMCONTROL0_SHIFT 0U
#define RPU_RPU_RAM_RAMCONTROL0_WIDTH 8U
#define RPU_RPU_RAM_RAMCONTROL0_MASK 0X000000FFU
/**
* Register: RPU_RPU_CACHE_DATA
*/
#define RPU_RPU_CACHE_DATA ( ( RPU_BASEADDR ) + 0X00000010U )
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_SHIFT 29U
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_WIDTH 1U
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_MASK 0X20000000U
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_SHIFT 27U
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_WIDTH 2U
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_MASK 0X18000000U
#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_SHIFT 24U
#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_WIDTH 3U
#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_MASK 0X07000000U
#define RPU_RPU_CACHE_DATA_DTAG_EMAS_SHIFT 23U
#define RPU_RPU_CACHE_DATA_DTAG_EMAS_WIDTH 1U
#define RPU_RPU_CACHE_DATA_DTAG_EMAS_MASK 0X00800000U
#define RPU_RPU_CACHE_DATA_DTAG_EMAW_SHIFT 21U
#define RPU_RPU_CACHE_DATA_DTAG_EMAW_WIDTH 2U
#define RPU_RPU_CACHE_DATA_DTAG_EMAW_MASK 0X00600000U
#define RPU_RPU_CACHE_DATA_DTAG_EMA_SHIFT 18U
#define RPU_RPU_CACHE_DATA_DTAG_EMA_WIDTH 3U
#define RPU_RPU_CACHE_DATA_DTAG_EMA_MASK 0X001C0000U
#define RPU_RPU_CACHE_DATA_DDATA_EMAS_SHIFT 17U
#define RPU_RPU_CACHE_DATA_DDATA_EMAS_WIDTH 1U
#define RPU_RPU_CACHE_DATA_DDATA_EMAS_MASK 0X00020000U
#define RPU_RPU_CACHE_DATA_DDATA_EMAW_SHIFT 15U
#define RPU_RPU_CACHE_DATA_DDATA_EMAW_WIDTH 2U
#define RPU_RPU_CACHE_DATA_DDATA_EMAW_MASK 0X00018000U
#define RPU_RPU_CACHE_DATA_DDATA_EMA_SHIFT 12U
#define RPU_RPU_CACHE_DATA_DDATA_EMA_WIDTH 3U
#define RPU_RPU_CACHE_DATA_DDATA_EMA_MASK 0X00007000U
#define RPU_RPU_CACHE_DATA_ITAG_EMAS_SHIFT 11U
#define RPU_RPU_CACHE_DATA_ITAG_EMAS_WIDTH 1U
#define RPU_RPU_CACHE_DATA_ITAG_EMAS_MASK 0X00000800U
#define RPU_RPU_CACHE_DATA_ITAG_EMAW_SHIFT 9U
#define RPU_RPU_CACHE_DATA_ITAG_EMAW_WIDTH 2U
#define RPU_RPU_CACHE_DATA_ITAG_EMAW_MASK 0X00000600U
#define RPU_RPU_CACHE_DATA_ITAG_EMA_SHIFT 6U
#define RPU_RPU_CACHE_DATA_ITAG_EMA_WIDTH 3U
#define RPU_RPU_CACHE_DATA_ITAG_EMA_MASK 0X000001C0U
#define RPU_RPU_CACHE_DATA_IDATA_EMAS_SHIFT 5U
#define RPU_RPU_CACHE_DATA_IDATA_EMAS_WIDTH 1U
#define RPU_RPU_CACHE_DATA_IDATA_EMAS_MASK 0X00000020U
#define RPU_RPU_CACHE_DATA_IDATA_EMAW_SHIFT 3U
#define RPU_RPU_CACHE_DATA_IDATA_EMAW_WIDTH 2U
#define RPU_RPU_CACHE_DATA_IDATA_EMAW_MASK 0X00000018U
#define RPU_RPU_CACHE_DATA_IDATA_EMA_SHIFT 0U
#define RPU_RPU_CACHE_DATA_IDATA_EMA_WIDTH 3U
#define RPU_RPU_CACHE_DATA_IDATA_EMA_MASK 0X00000007U
/**
* Register: RPU_RPU_CACHE_SYN
*/
#define RPU_RPU_CACHE_SYN ( ( RPU_BASEADDR ) + 0X00000014U )
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_SHIFT 29U
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_WIDTH 1U
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_MASK 0X20000000U
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_SHIFT 27U
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_WIDTH 2U
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_MASK 0X18000000U
#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_SHIFT 24U
#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_WIDTH 3U
#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_MASK 0X07000000U
#define RPU_RPU_CACHE_SYN_DTAG_EMAS_SHIFT 23U
#define RPU_RPU_CACHE_SYN_DTAG_EMAS_WIDTH 1U
#define RPU_RPU_CACHE_SYN_DTAG_EMAS_MASK 0X00800000U
#define RPU_RPU_CACHE_SYN_DTAG_EMAW_SHIFT 21U
#define RPU_RPU_CACHE_SYN_DTAG_EMAW_WIDTH 2U
#define RPU_RPU_CACHE_SYN_DTAG_EMAW_MASK 0X00600000U
#define RPU_RPU_CACHE_SYN_DTAG_EMA_SHIFT 18U
#define RPU_RPU_CACHE_SYN_DTAG_EMA_WIDTH 3U
#define RPU_RPU_CACHE_SYN_DTAG_EMA_MASK 0X001C0000U
#define RPU_RPU_CACHE_SYN_DDATA_EMAS_SHIFT 17U
#define RPU_RPU_CACHE_SYN_DDATA_EMAS_WIDTH 1U
#define RPU_RPU_CACHE_SYN_DDATA_EMAS_MASK 0X00020000U
#define RPU_RPU_CACHE_SYN_DDATA_EMAW_SHIFT 15U
#define RPU_RPU_CACHE_SYN_DDATA_EMAW_WIDTH 2U
#define RPU_RPU_CACHE_SYN_DDATA_EMAW_MASK 0X00018000U
#define RPU_RPU_CACHE_SYN_DDATA_EMA_SHIFT 12U
#define RPU_RPU_CACHE_SYN_DDATA_EMA_WIDTH 3U
#define RPU_RPU_CACHE_SYN_DDATA_EMA_MASK 0X00007000U
#define RPU_RPU_CACHE_SYN_ITAG_EMAS_SHIFT 11U
#define RPU_RPU_CACHE_SYN_ITAG_EMAS_WIDTH 1U
#define RPU_RPU_CACHE_SYN_ITAG_EMAS_MASK 0X00000800U
#define RPU_RPU_CACHE_SYN_ITAG_EMAW_SHIFT 9U
#define RPU_RPU_CACHE_SYN_ITAG_EMAW_WIDTH 2U
#define RPU_RPU_CACHE_SYN_ITAG_EMAW_MASK 0X00000600U
#define RPU_RPU_CACHE_SYN_ITAG_EMA_SHIFT 6U
#define RPU_RPU_CACHE_SYN_ITAG_EMA_WIDTH 3U
#define RPU_RPU_CACHE_SYN_ITAG_EMA_MASK 0X000001C0U
#define RPU_RPU_CACHE_SYN_IDATA_EMAS_SHIFT 5U
#define RPU_RPU_CACHE_SYN_IDATA_EMAS_WIDTH 1U
#define RPU_RPU_CACHE_SYN_IDATA_EMAS_MASK 0X00000020U
#define RPU_RPU_CACHE_SYN_IDATA_EMAW_SHIFT 3U
#define RPU_RPU_CACHE_SYN_IDATA_EMAW_WIDTH 2U
#define RPU_RPU_CACHE_SYN_IDATA_EMAW_MASK 0X00000018U
#define RPU_RPU_CACHE_SYN_IDATA_EMA_SHIFT 0U
#define RPU_RPU_CACHE_SYN_IDATA_EMA_WIDTH 3U
#define RPU_RPU_CACHE_SYN_IDATA_EMA_MASK 0X00000007U
/**
* Register: RPU_RPU_TCM_DATA
*/
#define RPU_RPU_TCM_DATA ( ( RPU_BASEADDR ) + 0X00000018U )
#define RPU_RPU_TCM_DATA_B_EMAS_SHIFT 17U
#define RPU_RPU_TCM_DATA_B_EMAS_WIDTH 1U
#define RPU_RPU_TCM_DATA_B_EMAS_MASK 0X00020000U
#define RPU_RPU_TCM_DATA_B_EMAW_SHIFT 15U
#define RPU_RPU_TCM_DATA_B_EMAW_WIDTH 2U
#define RPU_RPU_TCM_DATA_B_EMAW_MASK 0X00018000U
#define RPU_RPU_TCM_DATA_B_EMA_SHIFT 12U
#define RPU_RPU_TCM_DATA_B_EMA_WIDTH 3U
#define RPU_RPU_TCM_DATA_B_EMA_MASK 0X00007000U
#define RPU_RPU_TCM_DATA_A_EMAS_SHIFT 5U
#define RPU_RPU_TCM_DATA_A_EMAS_WIDTH 1U
#define RPU_RPU_TCM_DATA_A_EMAS_MASK 0X00000020U
#define RPU_RPU_TCM_DATA_A_EMAW_SHIFT 3U
#define RPU_RPU_TCM_DATA_A_EMAW_WIDTH 2U
#define RPU_RPU_TCM_DATA_A_EMAW_MASK 0X00000018U
#define RPU_RPU_TCM_DATA_A_EMA_SHIFT 0U
#define RPU_RPU_TCM_DATA_A_EMA_WIDTH 3U
#define RPU_RPU_TCM_DATA_A_EMA_MASK 0X00000007U
/**
* Register: RPU_RPU_TCM_SYN
*/
#define RPU_RPU_TCM_SYN ( ( RPU_BASEADDR ) + 0X0000001CU )
#define RPU_RPU_TCM_SYN_B_EMAS_SHIFT 23U
#define RPU_RPU_TCM_SYN_B_EMAS_WIDTH 1U
#define RPU_RPU_TCM_SYN_B_EMAS_MASK 0X00800000U
#define RPU_RPU_TCM_SYN_B_EMAW_SHIFT 21U
#define RPU_RPU_TCM_SYN_B_EMAW_WIDTH 2U
#define RPU_RPU_TCM_SYN_B_EMAW_MASK 0X00600000U
#define RPU_RPU_TCM_SYN_B_EMA_SHIFT 18U
#define RPU_RPU_TCM_SYN_B_EMA_WIDTH 3U
#define RPU_RPU_TCM_SYN_B_EMA_MASK 0X001C0000U
#define RPU_RPU_TCM_SYN_A_EMAS_SHIFT 11U
#define RPU_RPU_TCM_SYN_A_EMAS_WIDTH 1U
#define RPU_RPU_TCM_SYN_A_EMAS_MASK 0X00000800U
#define RPU_RPU_TCM_SYN_A_EMAW_SHIFT 9U
#define RPU_RPU_TCM_SYN_A_EMAW_WIDTH 2U
#define RPU_RPU_TCM_SYN_A_EMAW_MASK 0X00000600U
#define RPU_RPU_TCM_SYN_A_EMA_SHIFT 6U
#define RPU_RPU_TCM_SYN_A_EMA_WIDTH 3U
#define RPU_RPU_TCM_SYN_A_EMA_MASK 0X000001C0U
/**
* Register: RPU_RPU_ERR_INJ
*/
#define RPU_RPU_ERR_INJ ( ( RPU_BASEADDR ) + 0X00000020U )
#define RPU_RPU_ERR_INJ_DCCMINP2_SHIFT 8U
#define RPU_RPU_ERR_INJ_DCCMINP2_WIDTH 8U
#define RPU_RPU_ERR_INJ_DCCMINP2_MASK 0X0000FF00U
#define RPU_RPU_ERR_INJ_DCCMINP_SHIFT 0U
#define RPU_RPU_ERR_INJ_DCCMINP_WIDTH 8U
#define RPU_RPU_ERR_INJ_DCCMINP_MASK 0X000000FFU
/**
* Register: RPU_RPU_CCF_MASK
*/
#define RPU_RPU_CCF_MASK ( ( RPU_BASEADDR ) + 0X00000024U )
#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_SHIFT 7U
#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_WIDTH 1U
#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_MASK 0X00000080U
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_SHIFT 6U
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_WIDTH 1U
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_MASK 0X00000040U
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_SHIFT 5U
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_WIDTH 1U
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_MASK 0X00000020U
#define RPU_RPU_CCF_MASK_ISO_SHIFT 4U
#define RPU_RPU_CCF_MASK_ISO_WIDTH 1U
#define RPU_RPU_CCF_MASK_ISO_MASK 0X00000010U
#define RPU_RPU_CCF_MASK_PGE_SHIFT 3U
#define RPU_RPU_CCF_MASK_PGE_WIDTH 1U
#define RPU_RPU_CCF_MASK_PGE_MASK 0X00000008U
#define RPU_RPU_CCF_MASK_R50_DBG_RST_SHIFT 2U
#define RPU_RPU_CCF_MASK_R50_DBG_RST_WIDTH 1U
#define RPU_RPU_CCF_MASK_R50_DBG_RST_MASK 0X00000004U
#define RPU_RPU_CCF_MASK_R50_RST_SHIFT 1U
#define RPU_RPU_CCF_MASK_R50_RST_WIDTH 1U
#define RPU_RPU_CCF_MASK_R50_RST_MASK 0X00000002U
#define RPU_RPU_CCF_MASK_PGE_RST_SHIFT 0U
#define RPU_RPU_CCF_MASK_PGE_RST_WIDTH 1U
#define RPU_RPU_CCF_MASK_PGE_RST_MASK 0X00000001U
/**
* Register: RPU_RPU_INTR_0
*/
#define RPU_RPU_INTR_0 ( ( RPU_BASEADDR ) + 0X00000028U )
#define RPU_RPU_INTR_0_SPI_SHIFT 0U
#define RPU_RPU_INTR_0_SPI_WIDTH 32U
#define RPU_RPU_INTR_0_SPI_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_INTR_1
*/
#define RPU_RPU_INTR_1 ( ( RPU_BASEADDR ) + 0X0000002CU )
#define RPU_RPU_INTR_1_SPI_SHIFT 0U
#define RPU_RPU_INTR_1_SPI_WIDTH 32U
#define RPU_RPU_INTR_1_SPI_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_INTR_2
*/
#define RPU_RPU_INTR_2 ( ( RPU_BASEADDR ) + 0X00000030U )
#define RPU_RPU_INTR_2_SPI_SHIFT 0U
#define RPU_RPU_INTR_2_SPI_WIDTH 32U
#define RPU_RPU_INTR_2_SPI_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_INTR_3
*/
#define RPU_RPU_INTR_3 ( ( RPU_BASEADDR ) + 0X00000034U )
#define RPU_RPU_INTR_3_SPI_SHIFT 0U
#define RPU_RPU_INTR_3_SPI_WIDTH 32U
#define RPU_RPU_INTR_3_SPI_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_INTR_4
*/
#define RPU_RPU_INTR_4 ( ( RPU_BASEADDR ) + 0X00000038U )
#define RPU_RPU_INTR_4_SPI_SHIFT 0U
#define RPU_RPU_INTR_4_SPI_WIDTH 32U
#define RPU_RPU_INTR_4_SPI_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_INTR_MASK_0
*/
#define RPU_RPU_INTR_MASK_0 ( ( RPU_BASEADDR ) + 0X00000040U )
#define RPU_RPU_INTR_MASK_0_SPI_SHIFT 0U
#define RPU_RPU_INTR_MASK_0_SPI_WIDTH 32U
#define RPU_RPU_INTR_MASK_0_SPI_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_INTR_MASK_1
*/
#define RPU_RPU_INTR_MASK_1 ( ( RPU_BASEADDR ) + 0X00000044U )
#define RPU_RPU_INTR_MASK_1_SPI_SHIFT 0U
#define RPU_RPU_INTR_MASK_1_SPI_WIDTH 32U
#define RPU_RPU_INTR_MASK_1_SPI_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_INTR_MASK_2
*/
#define RPU_RPU_INTR_MASK_2 ( ( RPU_BASEADDR ) + 0X00000048U )
#define RPU_RPU_INTR_MASK_2_SPI_SHIFT 0U
#define RPU_RPU_INTR_MASK_2_SPI_WIDTH 32U
#define RPU_RPU_INTR_MASK_2_SPI_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_INTR_MASK_3
*/
#define RPU_RPU_INTR_MASK_3 ( ( RPU_BASEADDR ) + 0X0000004CU )
#define RPU_RPU_INTR_MASK_3_SPI_SHIFT 0U
#define RPU_RPU_INTR_MASK_3_SPI_WIDTH 32U
#define RPU_RPU_INTR_MASK_3_SPI_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_INTR_MASK_4
*/
#define RPU_RPU_INTR_MASK_4 ( ( RPU_BASEADDR ) + 0X00000050U )
#define RPU_RPU_INTR_MASK_4_SPI_SHIFT 0U
#define RPU_RPU_INTR_MASK_4_SPI_WIDTH 32U
#define RPU_RPU_INTR_MASK_4_SPI_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_CCF_VAL
*/
#define RPU_RPU_CCF_VAL ( ( RPU_BASEADDR ) + 0X00000054U )
#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_SHIFT 7U
#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_WIDTH 1U
#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_MASK 0X00000080U
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_SHIFT 6U
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_WIDTH 1U
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_MASK 0X00000040U
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_SHIFT 5U
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_WIDTH 1U
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_MASK 0X00000020U
#define RPU_RPU_CCF_VAL_ISO_SHIFT 4U
#define RPU_RPU_CCF_VAL_ISO_WIDTH 1U
#define RPU_RPU_CCF_VAL_ISO_MASK 0X00000010U
#define RPU_RPU_CCF_VAL_PGE_SHIFT 3U
#define RPU_RPU_CCF_VAL_PGE_WIDTH 1U
#define RPU_RPU_CCF_VAL_PGE_MASK 0X00000008U
#define RPU_RPU_CCF_VAL_R50_DBG_RST_SHIFT 2U
#define RPU_RPU_CCF_VAL_R50_DBG_RST_WIDTH 1U
#define RPU_RPU_CCF_VAL_R50_DBG_RST_MASK 0X00000004U
#define RPU_RPU_CCF_VAL_R50_RST_SHIFT 1U
#define RPU_RPU_CCF_VAL_R50_RST_WIDTH 1U
#define RPU_RPU_CCF_VAL_R50_RST_MASK 0X00000002U
#define RPU_RPU_CCF_VAL_PGE_RST_SHIFT 0U
#define RPU_RPU_CCF_VAL_PGE_RST_WIDTH 1U
#define RPU_RPU_CCF_VAL_PGE_RST_MASK 0X00000001U
/**
* Register: RPU_RPU_SAFETY_CHK
*/
#define RPU_RPU_SAFETY_CHK ( ( RPU_BASEADDR ) + 0X000000F0U )
#define RPU_RPU_SAFETY_CHK_VAL_SHIFT 0U
#define RPU_RPU_SAFETY_CHK_VAL_WIDTH 32U
#define RPU_RPU_SAFETY_CHK_VAL_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU
*/
#define RPU_RPU ( ( RPU_BASEADDR ) + 0X000000F4U )
#define RPU_RPU_ECO_SHIFT 0U
#define RPU_RPU_ECO_WIDTH 32U
#define RPU_RPU_ECO_MASK 0XFFFFFFFFU
/**
* Register: RPU_RPU_0_CFG
*/
#define RPU_RPU_0_CFG ( ( RPU_BASEADDR ) + 0X00000100U )
#define RPU_RPU_0_CFG_CFGNMFI0_SHIFT 3U
#define RPU_RPU_0_CFG_CFGNMFI0_WIDTH 1U
#define RPU_RPU_0_CFG_CFGNMFI0_MASK 0X00000008U
#define RPU_RPU_0_CFG_VINITHI_SHIFT 2U
#define RPU_RPU_0_CFG_VINITHI_WIDTH 1U
#define RPU_RPU_0_CFG_VINITHI_MASK 0X00000004U
#define RPU_RPU_0_CFG_COHERENT_SHIFT 1U
#define RPU_RPU_0_CFG_COHERENT_WIDTH 1U
#define RPU_RPU_0_CFG_COHERENT_MASK 0X00000002U
#define RPU_RPU_0_CFG_NCPUHALT_SHIFT 0U
#define RPU_RPU_0_CFG_NCPUHALT_WIDTH 1U
#define RPU_RPU_0_CFG_NCPUHALT_MASK 0X00000001U
/**
* Register: RPU_RPU_0_STATUS
*/
#define RPU_RPU_0_STATUS ( ( RPU_BASEADDR ) + 0X00000104U )
#define RPU_RPU_0_STATUS_NVALRESET_SHIFT 5U
#define RPU_RPU_0_STATUS_NVALRESET_WIDTH 1U
#define RPU_RPU_0_STATUS_NVALRESET_MASK 0X00000020U
#define RPU_RPU_0_STATUS_NVALIRQ_SHIFT 4U
#define RPU_RPU_0_STATUS_NVALIRQ_WIDTH 1U
#define RPU_RPU_0_STATUS_NVALIRQ_MASK 0X00000010U
#define RPU_RPU_0_STATUS_NVALFIQ_SHIFT 3U
#define RPU_RPU_0_STATUS_NVALFIQ_WIDTH 1U
#define RPU_RPU_0_STATUS_NVALFIQ_MASK 0X00000008U
#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_SHIFT 2U
#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_WIDTH 1U
#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_MASK 0X00000004U
#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_SHIFT 1U
#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_WIDTH 1U
#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_MASK 0X00000002U
#define RPU_RPU_0_STATUS_NCLKSTOPPED_SHIFT 0U
#define RPU_RPU_0_STATUS_NCLKSTOPPED_WIDTH 1U
#define RPU_RPU_0_STATUS_NCLKSTOPPED_MASK 0X00000001U
/**
* Register: RPU_RPU_0_PWRDWN
*/
#define RPU_RPU_0_PWRDWN ( ( RPU_BASEADDR ) + 0X00000108U )
#define RPU_RPU_0_PWRDWN_EN_SHIFT 0U
#define RPU_RPU_0_PWRDWN_EN_WIDTH 1U
#define RPU_RPU_0_PWRDWN_EN_MASK 0X00000001U
/**
* Register: RPU_RPU_0_ISR
*/
#define RPU_RPU_0_ISR ( ( RPU_BASEADDR ) + 0X00000114U )
#define RPU_RPU_0_ISR_FPUFC_SHIFT 24U
#define RPU_RPU_0_ISR_FPUFC_WIDTH 1U
#define RPU_RPU_0_ISR_FPUFC_MASK 0X01000000U
#define RPU_RPU_0_ISR_FPOFC_SHIFT 23U
#define RPU_RPU_0_ISR_FPOFC_WIDTH 1U
#define RPU_RPU_0_ISR_FPOFC_MASK 0X00800000U
#define RPU_RPU_0_ISR_FPIXC_SHIFT 22U
#define RPU_RPU_0_ISR_FPIXC_WIDTH 1U
#define RPU_RPU_0_ISR_FPIXC_MASK 0X00400000U
#define RPU_RPU_0_ISR_FPIOC_SHIFT 21U
#define RPU_RPU_0_ISR_FPIOC_WIDTH 1U
#define RPU_RPU_0_ISR_FPIOC_MASK 0X00200000U
#define RPU_RPU_0_ISR_FPIDC_SHIFT 20U
#define RPU_RPU_0_ISR_FPIDC_WIDTH 1U
#define RPU_RPU_0_ISR_FPIDC_MASK 0X00100000U
#define RPU_RPU_0_ISR_FPDZC_SHIFT 19U
#define RPU_RPU_0_ISR_FPDZC_WIDTH 1U
#define RPU_RPU_0_ISR_FPDZC_MASK 0X00080000U
#define RPU_RPU_0_ISR_TCM_ASLV_CE_SHIFT 18U
#define RPU_RPU_0_ISR_TCM_ASLV_CE_WIDTH 1U
#define RPU_RPU_0_ISR_TCM_ASLV_CE_MASK 0X00040000U
#define RPU_RPU_0_ISR_TCM_ASLV_FAT_SHIFT 17U
#define RPU_RPU_0_ISR_TCM_ASLV_FAT_WIDTH 1U
#define RPU_RPU_0_ISR_TCM_ASLV_FAT_MASK 0X00020000U
#define RPU_RPU_0_ISR_TCM_LST_CE_SHIFT 16U
#define RPU_RPU_0_ISR_TCM_LST_CE_WIDTH 1U
#define RPU_RPU_0_ISR_TCM_LST_CE_MASK 0X00010000U
#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_SHIFT 15U
#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_WIDTH 1U
#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_MASK 0X00008000U
#define RPU_RPU_0_ISR_B1TCM_CE_SHIFT 14U
#define RPU_RPU_0_ISR_B1TCM_CE_WIDTH 1U
#define RPU_RPU_0_ISR_B1TCM_CE_MASK 0X00004000U
#define RPU_RPU_0_ISR_B0TCM_CE_SHIFT 13U
#define RPU_RPU_0_ISR_B0TCM_CE_WIDTH 1U
#define RPU_RPU_0_ISR_B0TCM_CE_MASK 0X00002000U
#define RPU_RPU_0_ISR_ATCM_CE_SHIFT 12U
#define RPU_RPU_0_ISR_ATCM_CE_WIDTH 1U
#define RPU_RPU_0_ISR_ATCM_CE_MASK 0X00001000U
#define RPU_RPU_0_ISR_B1TCM_UE_SHIFT 11U
#define RPU_RPU_0_ISR_B1TCM_UE_WIDTH 1U
#define RPU_RPU_0_ISR_B1TCM_UE_MASK 0X00000800U
#define RPU_RPU_0_ISR_B0TCM_UE_SHIFT 10U
#define RPU_RPU_0_ISR_B0TCM_UE_WIDTH 1U
#define RPU_RPU_0_ISR_B0TCM_UE_MASK 0X00000400U
#define RPU_RPU_0_ISR_ATCM_UE_SHIFT 9U
#define RPU_RPU_0_ISR_ATCM_UE_WIDTH 1U
#define RPU_RPU_0_ISR_ATCM_UE_MASK 0X00000200U
#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_SHIFT 8U
#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_WIDTH 1U
#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_MASK 0X00000100U
#define RPU_RPU_0_ISR_DDATA_FAT_SHIFT 7U
#define RPU_RPU_0_ISR_DDATA_FAT_WIDTH 1U
#define RPU_RPU_0_ISR_DDATA_FAT_MASK 0X00000080U
#define RPU_RPU_0_ISR_TCM_LST_FAT_SHIFT 6U
#define RPU_RPU_0_ISR_TCM_LST_FAT_WIDTH 1U
#define RPU_RPU_0_ISR_TCM_LST_FAT_MASK 0X00000040U
#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_SHIFT 5U
#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_WIDTH 1U
#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_MASK 0X00000020U
#define RPU_RPU_0_ISR_DDATA_CE_SHIFT 4U
#define RPU_RPU_0_ISR_DDATA_CE_WIDTH 1U
#define RPU_RPU_0_ISR_DDATA_CE_MASK 0X00000010U
#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_SHIFT 3U
#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_WIDTH 1U
#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_MASK 0X00000008U
#define RPU_RPU_0_ISR_IDATA_CE_SHIFT 2U
#define RPU_RPU_0_ISR_IDATA_CE_WIDTH 1U
#define RPU_RPU_0_ISR_IDATA_CE_MASK 0X00000004U
#define RPU_RPU_0_ISR_ITAG_CE_SHIFT 1U
#define RPU_RPU_0_ISR_ITAG_CE_WIDTH 1U
#define RPU_RPU_0_ISR_ITAG_CE_MASK 0X00000002U
#define RPU_RPU_0_ISR_APB_ERR_SHIFT 0U
#define RPU_RPU_0_ISR_APB_ERR_WIDTH 1U
#define RPU_RPU_0_ISR_APB_ERR_MASK 0X00000001U
/**
* Register: RPU_RPU_0_IMR
*/
#define RPU_RPU_0_IMR ( ( RPU_BASEADDR ) + 0X00000118U)
#define RPU_RPU_0_IMR_FPUFC_SHIFT 24U
#define RPU_RPU_0_IMR_FPUFC_WIDTH 1U
#define RPU_RPU_0_IMR_FPUFC_MASK 0X01000000U
#define RPU_RPU_0_IMR_FPOFC_SHIFT 23U
#define RPU_RPU_0_IMR_FPOFC_WIDTH 1U
#define RPU_RPU_0_IMR_FPOFC_MASK 0X00800000U
#define RPU_RPU_0_IMR_FPIXC_SHIFT 22U
#define RPU_RPU_0_IMR_FPIXC_WIDTH 1U
#define RPU_RPU_0_IMR_FPIXC_MASK 0X00400000U
#define RPU_RPU_0_IMR_FPIOC_SHIFT 21U
#define RPU_RPU_0_IMR_FPIOC_WIDTH 1U
#define RPU_RPU_0_IMR_FPIOC_MASK 0X00200000U
#define RPU_RPU_0_IMR_FPIDC_SHIFT 20U
#define RPU_RPU_0_IMR_FPIDC_WIDTH 1U
#define RPU_RPU_0_IMR_FPIDC_MASK 0X00100000U
#define RPU_RPU_0_IMR_FPDZC_SHIFT 19U
#define RPU_RPU_0_IMR_FPDZC_WIDTH 1U
#define RPU_RPU_0_IMR_FPDZC_MASK 0X00080000U
#define RPU_RPU_0_IMR_TCM_ASLV_CE_SHIFT 18U
#define RPU_RPU_0_IMR_TCM_ASLV_CE_WIDTH 1U
#define RPU_RPU_0_IMR_TCM_ASLV_CE_MASK 0X00040000U
#define RPU_RPU_0_IMR_TCM_ASLV_FAT_SHIFT 17U
#define RPU_RPU_0_IMR_TCM_ASLV_FAT_WIDTH 1U
#define RPU_RPU_0_IMR_TCM_ASLV_FAT_MASK 0X00020000U
#define RPU_RPU_0_IMR_TCM_LST_CE_SHIFT 16U
#define RPU_RPU_0_IMR_TCM_LST_CE_WIDTH 1U
#define RPU_RPU_0_IMR_TCM_LST_CE_MASK 0X00010000U
#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_SHIFT 15U
#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_WIDTH 1U
#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_MASK 0X00008000U
#define RPU_RPU_0_IMR_B1TCM_CE_SHIFT 14U
#define RPU_RPU_0_IMR_B1TCM_CE_WIDTH 1U
#define RPU_RPU_0_IMR_B1TCM_CE_MASK 0X00004000U
#define RPU_RPU_0_IMR_B0TCM_CE_SHIFT 13U
#define RPU_RPU_0_IMR_B0TCM_CE_WIDTH 1U
#define RPU_RPU_0_IMR_B0TCM_CE_MASK 0X00002000U
#define RPU_RPU_0_IMR_ATCM_CE_SHIFT 12U
#define RPU_RPU_0_IMR_ATCM_CE_WIDTH 1U
#define RPU_RPU_0_IMR_ATCM_CE_MASK 0X00001000U
#define RPU_RPU_0_IMR_B1TCM_UE_SHIFT 11U
#define RPU_RPU_0_IMR_B1TCM_UE_WIDTH 1U
#define RPU_RPU_0_IMR_B1TCM_UE_MASK 0X00000800U
#define RPU_RPU_0_IMR_B0TCM_UE_SHIFT 10U
#define RPU_RPU_0_IMR_B0TCM_UE_WIDTH 1U
#define RPU_RPU_0_IMR_B0TCM_UE_MASK 0X00000400U
#define RPU_RPU_0_IMR_ATCM_UE_SHIFT 9U
#define RPU_RPU_0_IMR_ATCM_UE_WIDTH 1U
#define RPU_RPU_0_IMR_ATCM_UE_MASK 0X00000200U
#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_SHIFT 8U
#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_WIDTH 1U
#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_MASK 0X00000100U
#define RPU_RPU_0_IMR_DDATA_FAT_SHIFT 7U
#define RPU_RPU_0_IMR_DDATA_FAT_WIDTH 1U
#define RPU_RPU_0_IMR_DDATA_FAT_MASK 0X00000080U
#define RPU_RPU_0_IMR_TCM_LST_FAT_SHIFT 6U
#define RPU_RPU_0_IMR_TCM_LST_FAT_WIDTH 1U
#define RPU_RPU_0_IMR_TCM_LST_FAT_MASK 0X00000040U
#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_SHIFT 5U
#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_WIDTH 1U
#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_MASK 0X00000020U
#define RPU_RPU_0_IMR_DDATA_CE_SHIFT 4U
#define RPU_RPU_0_IMR_DDATA_CE_WIDTH 1U
#define RPU_RPU_0_IMR_DDATA_CE_MASK 0X00000010U
#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_SHIFT 3U
#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_WIDTH 1U
#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_MASK 0X00000008U
#define RPU_RPU_0_IMR_IDATA_CE_SHIFT 2U
#define RPU_RPU_0_IMR_IDATA_CE_WIDTH 1U
#define RPU_RPU_0_IMR_IDATA_CE_MASK 0X00000004U
#define RPU_RPU_0_IMR_ITAG_CE_SHIFT 1U
#define RPU_RPU_0_IMR_ITAG_CE_WIDTH 1U
#define RPU_RPU_0_IMR_ITAG_CE_MASK 0X00000002U
#define RPU_RPU_0_IMR_APB_ERR_SHIFT 0U
#define RPU_RPU_0_IMR_APB_ERR_WIDTH 1U
#define RPU_RPU_0_IMR_APB_ERR_MASK 0X00000001U
/**
* Register: RPU_RPU_0_IEN
*/
#define RPU_RPU_0_IEN ( ( RPU_BASEADDR ) + 0X0000011CU )
#define RPU_RPU_0_IEN_FPUFC_SHIFT 24U
#define RPU_RPU_0_IEN_FPUFC_WIDTH 1U
#define RPU_RPU_0_IEN_FPUFC_MASK 0X01000000U
#define RPU_RPU_0_IEN_FPOFC_SHIFT 23U
#define RPU_RPU_0_IEN_FPOFC_WIDTH 1U
#define RPU_RPU_0_IEN_FPOFC_MASK 0X00800000U
#define RPU_RPU_0_IEN_FPIXC_SHIFT 22U
#define RPU_RPU_0_IEN_FPIXC_WIDTH 1U
#define RPU_RPU_0_IEN_FPIXC_MASK 0X00400000U
#define RPU_RPU_0_IEN_FPIOC_SHIFT 21U
#define RPU_RPU_0_IEN_FPIOC_WIDTH 1U
#define RPU_RPU_0_IEN_FPIOC_MASK 0X00200000U
#define RPU_RPU_0_IEN_FPIDC_SHIFT 20U
#define RPU_RPU_0_IEN_FPIDC_WIDTH 1U
#define RPU_RPU_0_IEN_FPIDC_MASK 0X00100000U
#define RPU_RPU_0_IEN_FPDZC_SHIFT 19U
#define RPU_RPU_0_IEN_FPDZC_WIDTH 1U
#define RPU_RPU_0_IEN_FPDZC_MASK 0X00080000U
#define RPU_RPU_0_IEN_TCM_ASLV_CE_SHIFT 18U
#define RPU_RPU_0_IEN_TCM_ASLV_CE_WIDTH 1U
#define RPU_RPU_0_IEN_TCM_ASLV_CE_MASK 0X00040000U
#define RPU_RPU_0_IEN_TCM_ASLV_FAT_SHIFT 17U
#define RPU_RPU_0_IEN_TCM_ASLV_FAT_WIDTH 1U
#define RPU_RPU_0_IEN_TCM_ASLV_FAT_MASK 0X00020000U
#define RPU_RPU_0_IEN_TCM_LST_CE_SHIFT 16U
#define RPU_RPU_0_IEN_TCM_LST_CE_WIDTH 1U
#define RPU_RPU_0_IEN_TCM_LST_CE_MASK 0X00010000U
#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_SHIFT 15U
#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_WIDTH 1U
#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_MASK 0X00008000U
#define RPU_RPU_0_IEN_B1TCM_CE_SHIFT 14U
#define RPU_RPU_0_IEN_B1TCM_CE_WIDTH 1U
#define RPU_RPU_0_IEN_B1TCM_CE_MASK 0X00004000U
#define RPU_RPU_0_IEN_B0TCM_CE_SHIFT 13U
#define RPU_RPU_0_IEN_B0TCM_CE_WIDTH 1U
#define RPU_RPU_0_IEN_B0TCM_CE_MASK 0X00002000U
#define RPU_RPU_0_IEN_ATCM_CE_SHIFT 12U
#define RPU_RPU_0_IEN_ATCM_CE_WIDTH 1U
#define RPU_RPU_0_IEN_ATCM_CE_MASK 0X00001000U
#define RPU_RPU_0_IEN_B1TCM_UE_SHIFT 11U
#define RPU_RPU_0_IEN_B1TCM_UE_WIDTH 1U
#define RPU_RPU_0_IEN_B1TCM_UE_MASK 0X00000800U
#define RPU_RPU_0_IEN_B0TCM_UE_SHIFT 10U
#define RPU_RPU_0_IEN_B0TCM_UE_WIDTH 1U
#define RPU_RPU_0_IEN_B0TCM_UE_MASK 0X00000400U
#define RPU_RPU_0_IEN_ATCM_UE_SHIFT 9U
#define RPU_RPU_0_IEN_ATCM_UE_WIDTH 1U
#define RPU_RPU_0_IEN_ATCM_UE_MASK 0X00000200U
#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_SHIFT 8U
#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_WIDTH 1U
#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_MASK 0X00000100U
#define RPU_RPU_0_IEN_DDATA_FAT_SHIFT 7U
#define RPU_RPU_0_IEN_DDATA_FAT_WIDTH 1U
#define RPU_RPU_0_IEN_DDATA_FAT_MASK 0X00000080U
#define RPU_RPU_0_IEN_TCM_LST_FAT_SHIFT 6U
#define RPU_RPU_0_IEN_TCM_LST_FAT_WIDTH 1U
#define RPU_RPU_0_IEN_TCM_LST_FAT_MASK 0X00000040U
#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_SHIFT 5U
#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_WIDTH 1U
#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_MASK 0X00000020U
#define RPU_RPU_0_IEN_DDATA_CE_SHIFT 4U
#define RPU_RPU_0_IEN_DDATA_CE_WIDTH 1U
#define RPU_RPU_0_IEN_DDATA_CE_MASK 0X00000010U
#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_SHIFT 3U
#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_WIDTH 1U
#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_MASK 0X00000008U
#define RPU_RPU_0_IEN_IDATA_CE_SHIFT 2U
#define RPU_RPU_0_IEN_IDATA_CE_WIDTH 1U
#define RPU_RPU_0_IEN_IDATA_CE_MASK 0X00000004U
#define RPU_RPU_0_IEN_ITAG_CE_SHIFT 1U
#define RPU_RPU_0_IEN_ITAG_CE_WIDTH 1U
#define RPU_RPU_0_IEN_ITAG_CE_MASK 0X00000002U
#define RPU_RPU_0_IEN_APB_ERR_SHIFT 0U
#define RPU_RPU_0_IEN_APB_ERR_WIDTH 1U
#define RPU_RPU_0_IEN_APB_ERR_MASK 0X00000001U
/**
* Register: RPU_RPU_0_IDS
*/
#define RPU_RPU_0_IDS ( ( RPU_BASEADDR ) + 0X00000120U )
#define RPU_RPU_0_IDS_FPUFC_SHIFT 24U
#define RPU_RPU_0_IDS_FPUFC_WIDTH 1U
#define RPU_RPU_0_IDS_FPUFC_MASK 0X01000000U
#define RPU_RPU_0_IDS_FPOFC_SHIFT 23U
#define RPU_RPU_0_IDS_FPOFC_WIDTH 1U
#define RPU_RPU_0_IDS_FPOFC_MASK 0X00800000U
#define RPU_RPU_0_IDS_FPIXC_SHIFT 22U
#define RPU_RPU_0_IDS_FPIXC_WIDTH 1U
#define RPU_RPU_0_IDS_FPIXC_MASK 0X00400000U
#define RPU_RPU_0_IDS_FPIOC_SHIFT 21U
#define RPU_RPU_0_IDS_FPIOC_WIDTH 1U
#define RPU_RPU_0_IDS_FPIOC_MASK 0X00200000U
#define RPU_RPU_0_IDS_FPIDC_SHIFT 20U
#define RPU_RPU_0_IDS_FPIDC_WIDTH 1U
#define RPU_RPU_0_IDS_FPIDC_MASK 0X00100000U
#define RPU_RPU_0_IDS_FPDZC_SHIFT 19U
#define RPU_RPU_0_IDS_FPDZC_WIDTH 1U
#define RPU_RPU_0_IDS_FPDZC_MASK 0X00080000U
#define RPU_RPU_0_IDS_TCM_ASLV_CE_SHIFT 18U
#define RPU_RPU_0_IDS_TCM_ASLV_CE_WIDTH 1U
#define RPU_RPU_0_IDS_TCM_ASLV_CE_MASK 0X00040000U
#define RPU_RPU_0_IDS_TCM_ASLV_FAT_SHIFT 17U
#define RPU_RPU_0_IDS_TCM_ASLV_FAT_WIDTH 1U
#define RPU_RPU_0_IDS_TCM_ASLV_FAT_MASK 0X00020000U
#define RPU_RPU_0_IDS_TCM_LST_CE_SHIFT 16U
#define RPU_RPU_0_IDS_TCM_LST_CE_WIDTH 1U
#define RPU_RPU_0_IDS_TCM_LST_CE_MASK 0X00010000U
#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_SHIFT 15U
#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_WIDTH 1U
#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_MASK 0X00008000U
#define RPU_RPU_0_IDS_B1TCM_CE_SHIFT 14U
#define RPU_RPU_0_IDS_B1TCM_CE_WIDTH 1U
#define RPU_RPU_0_IDS_B1TCM_CE_MASK 0X00004000U
#define RPU_RPU_0_IDS_B0TCM_CE_SHIFT 13U
#define RPU_RPU_0_IDS_B0TCM_CE_WIDTH 1U
#define RPU_RPU_0_IDS_B0TCM_CE_MASK 0X00002000U
#define RPU_RPU_0_IDS_ATCM_CE_SHIFT 12U
#define RPU_RPU_0_IDS_ATCM_CE_WIDTH 1U
#define RPU_RPU_0_IDS_ATCM_CE_MASK 0X00001000U
#define RPU_RPU_0_IDS_B1TCM_UE_SHIFT 11U
#define RPU_RPU_0_IDS_B1TCM_UE_WIDTH 1U
#define RPU_RPU_0_IDS_B1TCM_UE_MASK 0X00000800U
#define RPU_RPU_0_IDS_B0TCM_UE_SHIFT 10U
#define RPU_RPU_0_IDS_B0TCM_UE_WIDTH 1U
#define RPU_RPU_0_IDS_B0TCM_UE_MASK 0X00000400U
#define RPU_RPU_0_IDS_ATCM_UE_SHIFT 9U
#define RPU_RPU_0_IDS_ATCM_UE_WIDTH 1U
#define RPU_RPU_0_IDS_ATCM_UE_MASK 0X00000200U
#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_SHIFT 8U
#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_WIDTH 1U
#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_MASK 0X00000100U
#define RPU_RPU_0_IDS_DDATA_FAT_SHIFT 7U
#define RPU_RPU_0_IDS_DDATA_FAT_WIDTH 1U
#define RPU_RPU_0_IDS_DDATA_FAT_MASK 0X00000080U
#define RPU_RPU_0_IDS_TCM_LST_FAT_SHIFT 6U
#define RPU_RPU_0_IDS_TCM_LST_FAT_WIDTH 1U
#define RPU_RPU_0_IDS_TCM_LST_FAT_MASK 0X00000040U
#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_SHIFT 5U
#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_WIDTH 1U
#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_MASK 0X00000020U
#define RPU_RPU_0_IDS_DDATA_CE_SHIFT 4U
#define RPU_RPU_0_IDS_DDATA_CE_WIDTH 1U
#define RPU_RPU_0_IDS_DDATA_CE_MASK 0X00000010U
#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_SHIFT 3U
#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_WIDTH 1U
#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_MASK 0X00000008U
#define RPU_RPU_0_IDS_IDATA_CE_SHIFT 2U
#define RPU_RPU_0_IDS_IDATA_CE_WIDTH 1U
#define RPU_RPU_0_IDS_IDATA_CE_MASK 0X00000004U
#define RPU_RPU_0_IDS_ITAG_CE_SHIFT 1U
#define RPU_RPU_0_IDS_ITAG_CE_WIDTH 1U
#define RPU_RPU_0_IDS_ITAG_CE_MASK 0X00000002U
#define RPU_RPU_0_IDS_APB_ERR_SHIFT 0U
#define RPU_RPU_0_IDS_APB_ERR_WIDTH 1U
#define RPU_RPU_0_IDS_APB_ERR_MASK 0X00000001U
/**
* Register: RPU_RPU_0_SLV_BASE
*/
#define RPU_RPU_0_SLV_BASE ( ( RPU_BASEADDR ) + 0X00000124U )
#define RPU_RPU_0_SLV_BASE_ADDR_SHIFT 0U
#define RPU_RPU_0_SLV_BASE_ADDR_WIDTH 8U
#define RPU_RPU_0_SLV_BASE_ADDR_MASK 0X000000FFU
/**
* Register: RPU_RPU_0_AXI_OVER
*/
#define RPU_RPU_0_AXI_OVER ( ( RPU_BASEADDR ) + 0X00000128U )
#define RPU_RPU_0_AXI_OVER_AWCACHE_SHIFT 6U
#define RPU_RPU_0_AXI_OVER_AWCACHE_WIDTH 4U
#define RPU_RPU_0_AXI_OVER_AWCACHE_MASK 0X000003C0U
#define RPU_RPU_0_AXI_OVER_ARCACHE_SHIFT 2U
#define RPU_RPU_0_AXI_OVER_ARCACHE_WIDTH 4U
#define RPU_RPU_0_AXI_OVER_ARCACHE_MASK 0X0000003CU
#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_SHIFT 1U
#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_WIDTH 1U
#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_MASK 0X00000002U
#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_SHIFT 0U
#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_WIDTH 1U
#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_MASK 0X00000001U
/**
* Register: RPU_RPU_1_CFG
*/
#define RPU_RPU_1_CFG ( ( RPU_BASEADDR ) + 0X00000200U )
#define RPU_RPU_1_CFG_CFGNMFI1_SHIFT 3U
#define RPU_RPU_1_CFG_CFGNMFI1_WIDTH 1U
#define RPU_RPU_1_CFG_CFGNMFI1_MASK 0X00000008U
#define RPU_RPU_1_CFG_VINITHI_SHIFT 2U
#define RPU_RPU_1_CFG_VINITHI_WIDTH 1U
#define RPU_RPU_1_CFG_VINITHI_MASK 0X00000004U
#define RPU_RPU_1_CFG_COHERENT_SHIFT 1U
#define RPU_RPU_1_CFG_COHERENT_WIDTH 1U
#define RPU_RPU_1_CFG_COHERENT_MASK 0X00000002U
#define RPU_RPU_1_CFG_NCPUHALT_SHIFT 0U
#define RPU_RPU_1_CFG_NCPUHALT_WIDTH 1U
#define RPU_RPU_1_CFG_NCPUHALT_MASK 0X00000001U
/**
* Register: RPU_RPU_1_STATUS
*/
#define RPU_RPU_1_STATUS ( ( RPU_BASEADDR ) + 0X00000204U )
#define RPU_RPU_1_STATUS_NVALRESET_SHIFT 5U
#define RPU_RPU_1_STATUS_NVALRESET_WIDTH 1U
#define RPU_RPU_1_STATUS_NVALRESET_MASK 0X00000020U
#define RPU_RPU_1_STATUS_NVALIRQ_SHIFT 4U
#define RPU_RPU_1_STATUS_NVALIRQ_WIDTH 1U
#define RPU_RPU_1_STATUS_NVALIRQ_MASK 0X00000010U
#define RPU_RPU_1_STATUS_NVALFIQ_SHIFT 3U
#define RPU_RPU_1_STATUS_NVALFIQ_WIDTH 1U
#define RPU_RPU_1_STATUS_NVALFIQ_MASK 0X00000008U
#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_SHIFT 2U
#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_WIDTH 1U
#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_MASK 0X00000004U
#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_SHIFT 1U
#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_WIDTH 1U
#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_MASK 0X00000002U
#define RPU_RPU_1_STATUS_NCLKSTOPPED_SHIFT 0U
#define RPU_RPU_1_STATUS_NCLKSTOPPED_WIDTH 1U
#define RPU_RPU_1_STATUS_NCLKSTOPPED_MASK 0X00000001U
/**
* Register: RPU_RPU_1_PWRDWN
*/
#define RPU_RPU_1_PWRDWN ( ( RPU_BASEADDR ) + 0X00000208U )
#define RPU_RPU_1_PWRDWN_EN_SHIFT 0U
#define RPU_RPU_1_PWRDWN_EN_WIDTH 1U
#define RPU_RPU_1_PWRDWN_EN_MASK 0X00000001U
/**
* Register: RPU_RPU_1_ISR
*/
#define RPU_RPU_1_ISR ( ( RPU_BASEADDR ) + 0X00000214U )
#define RPU_RPU_1_ISR_FPUFC_SHIFT 24U
#define RPU_RPU_1_ISR_FPUFC_WIDTH 1U
#define RPU_RPU_1_ISR_FPUFC_MASK 0X01000000U
#define RPU_RPU_1_ISR_FPOFC_SHIFT 23U
#define RPU_RPU_1_ISR_FPOFC_WIDTH 1U
#define RPU_RPU_1_ISR_FPOFC_MASK 0X00800000U
#define RPU_RPU_1_ISR_FPIXC_SHIFT 22U
#define RPU_RPU_1_ISR_FPIXC_WIDTH 1U
#define RPU_RPU_1_ISR_FPIXC_MASK 0X00400000U
#define RPU_RPU_1_ISR_FPIOC_SHIFT 21U
#define RPU_RPU_1_ISR_FPIOC_WIDTH 1U
#define RPU_RPU_1_ISR_FPIOC_MASK 0X00200000U
#define RPU_RPU_1_ISR_FPIDC_SHIFT 20U
#define RPU_RPU_1_ISR_FPIDC_WIDTH 1U
#define RPU_RPU_1_ISR_FPIDC_MASK 0X00100000U
#define RPU_RPU_1_ISR_FPDZC_SHIFT 19U
#define RPU_RPU_1_ISR_FPDZC_WIDTH 1U
#define RPU_RPU_1_ISR_FPDZC_MASK 0X00080000U
#define RPU_RPU_1_ISR_TCM_ASLV_CE_SHIFT 18U
#define RPU_RPU_1_ISR_TCM_ASLV_CE_WIDTH 1U
#define RPU_RPU_1_ISR_TCM_ASLV_CE_MASK 0X00040000U
#define RPU_RPU_1_ISR_TCM_ASLV_FAT_SHIFT 17U
#define RPU_RPU_1_ISR_TCM_ASLV_FAT_WIDTH 1U
#define RPU_RPU_1_ISR_TCM_ASLV_FAT_MASK 0X00020000U
#define RPU_RPU_1_ISR_TCM_LST_CE_SHIFT 16U
#define RPU_RPU_1_ISR_TCM_LST_CE_WIDTH 1U
#define RPU_RPU_1_ISR_TCM_LST_CE_MASK 0X00010000U
#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_SHIFT 15U
#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_WIDTH 1U
#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_MASK 0X00008000U
#define RPU_RPU_1_ISR_B1TCM_CE_SHIFT 14U
#define RPU_RPU_1_ISR_B1TCM_CE_WIDTH 1U
#define RPU_RPU_1_ISR_B1TCM_CE_MASK 0X00004000U
#define RPU_RPU_1_ISR_B0TCM_CE_SHIFT 13U
#define RPU_RPU_1_ISR_B0TCM_CE_WIDTH 1U
#define RPU_RPU_1_ISR_B0TCM_CE_MASK 0X00002000U
#define RPU_RPU_1_ISR_ATCM_CE_SHIFT 12U
#define RPU_RPU_1_ISR_ATCM_CE_WIDTH 1U
#define RPU_RPU_1_ISR_ATCM_CE_MASK 0X00001000U
#define RPU_RPU_1_ISR_B1TCM_UE_SHIFT 11U
#define RPU_RPU_1_ISR_B1TCM_UE_WIDTH 1U
#define RPU_RPU_1_ISR_B1TCM_UE_MASK 0X00000800U
#define RPU_RPU_1_ISR_B0TCM_UE_SHIFT 10U
#define RPU_RPU_1_ISR_B0TCM_UE_WIDTH 1U
#define RPU_RPU_1_ISR_B0TCM_UE_MASK 0X00000400U
#define RPU_RPU_1_ISR_ATCM_UE_SHIFT 9U
#define RPU_RPU_1_ISR_ATCM_UE_WIDTH 1U
#define RPU_RPU_1_ISR_ATCM_UE_MASK 0X00000200U
#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_SHIFT 8U
#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_WIDTH 1U
#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_MASK 0X00000100U
#define RPU_RPU_1_ISR_DDATA_FAT_SHIFT 7U
#define RPU_RPU_1_ISR_DDATA_FAT_WIDTH 1U
#define RPU_RPU_1_ISR_DDATA_FAT_MASK 0X00000080U
#define RPU_RPU_1_ISR_TCM_LST_FAT_SHIFT 6U
#define RPU_RPU_1_ISR_TCM_LST_FAT_WIDTH 1U
#define RPU_RPU_1_ISR_TCM_LST_FAT_MASK 0X00000040U
#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_SHIFT 5U
#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_WIDTH 1U
#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_MASK 0X00000020U
#define RPU_RPU_1_ISR_DDATA_CE_SHIFT 4U
#define RPU_RPU_1_ISR_DDATA_CE_WIDTH 1U
#define RPU_RPU_1_ISR_DDATA_CE_MASK 0X00000010U
#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_SHIFT 3U
#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_WIDTH 1U
#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_MASK 0X00000008U
#define RPU_RPU_1_ISR_IDATA_CE_SHIFT 2U
#define RPU_RPU_1_ISR_IDATA_CE_WIDTH 1U
#define RPU_RPU_1_ISR_IDATA_CE_MASK 0X00000004U
#define RPU_RPU_1_ISR_ITAG_CE_SHIFT 1U
#define RPU_RPU_1_ISR_ITAG_CE_WIDTH 1U
#define RPU_RPU_1_ISR_ITAG_CE_MASK 0X00000002U
#define RPU_RPU_1_ISR_APB_ERR_SHIFT 0U
#define RPU_RPU_1_ISR_APB_ERR_WIDTH 1U
#define RPU_RPU_1_ISR_APB_ERR_MASK 0X00000001U
/**
* Register: RPU_RPU_1_IMR
*/
#define RPU_RPU_1_IMR ( ( RPU_BASEADDR ) + 0X00000218U )
#define RPU_RPU_1_IMR_FPUFC_SHIFT 24U
#define RPU_RPU_1_IMR_FPUFC_WIDTH 1U
#define RPU_RPU_1_IMR_FPUFC_MASK 0X01000000U
#define RPU_RPU_1_IMR_FPOFC_SHIFT 23U
#define RPU_RPU_1_IMR_FPOFC_WIDTH 1U
#define RPU_RPU_1_IMR_FPOFC_MASK 0X00800000U
#define RPU_RPU_1_IMR_FPIXC_SHIFT 22U
#define RPU_RPU_1_IMR_FPIXC_WIDTH 1U
#define RPU_RPU_1_IMR_FPIXC_MASK 0X00400000U
#define RPU_RPU_1_IMR_FPIOC_SHIFT 21U
#define RPU_RPU_1_IMR_FPIOC_WIDTH 1U
#define RPU_RPU_1_IMR_FPIOC_MASK 0X00200000U
#define RPU_RPU_1_IMR_FPIDC_SHIFT 20U
#define RPU_RPU_1_IMR_FPIDC_WIDTH 1U
#define RPU_RPU_1_IMR_FPIDC_MASK 0X00100000U
#define RPU_RPU_1_IMR_FPDZC_SHIFT 19U
#define RPU_RPU_1_IMR_FPDZC_WIDTH 1U
#define RPU_RPU_1_IMR_FPDZC_MASK 0X00080000U
#define RPU_RPU_1_IMR_TCM_ASLV_CE_SHIFT 18U
#define RPU_RPU_1_IMR_TCM_ASLV_CE_WIDTH 1U
#define RPU_RPU_1_IMR_TCM_ASLV_CE_MASK 0X00040000U
#define RPU_RPU_1_IMR_TCM_ASLV_FAT_SHIFT 17U
#define RPU_RPU_1_IMR_TCM_ASLV_FAT_WIDTH 1U
#define RPU_RPU_1_IMR_TCM_ASLV_FAT_MASK 0X00020000U
#define RPU_RPU_1_IMR_TCM_LST_CE_SHIFT 16U
#define RPU_RPU_1_IMR_TCM_LST_CE_WIDTH 1U
#define RPU_RPU_1_IMR_TCM_LST_CE_MASK 0X00010000U
#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_SHIFT 15U
#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_WIDTH 1U
#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_MASK 0X00008000U
#define RPU_RPU_1_IMR_B1TCM_CE_SHIFT 14U
#define RPU_RPU_1_IMR_B1TCM_CE_WIDTH 1U
#define RPU_RPU_1_IMR_B1TCM_CE_MASK 0X00004000U
#define RPU_RPU_1_IMR_B0TCM_CE_SHIFT 13U
#define RPU_RPU_1_IMR_B0TCM_CE_WIDTH 1U
#define RPU_RPU_1_IMR_B0TCM_CE_MASK 0X00002000U
#define RPU_RPU_1_IMR_ATCM_CE_SHIFT 12U
#define RPU_RPU_1_IMR_ATCM_CE_WIDTH 1U
#define RPU_RPU_1_IMR_ATCM_CE_MASK 0X00001000U
#define RPU_RPU_1_IMR_B1TCM_UE_SHIFT 11U
#define RPU_RPU_1_IMR_B1TCM_UE_WIDTH 1U
#define RPU_RPU_1_IMR_B1TCM_UE_MASK 0X00000800U
#define RPU_RPU_1_IMR_B0TCM_UE_SHIFT 10U
#define RPU_RPU_1_IMR_B0TCM_UE_WIDTH 1U
#define RPU_RPU_1_IMR_B0TCM_UE_MASK 0X00000400U
#define RPU_RPU_1_IMR_ATCM_UE_SHIFT 9U
#define RPU_RPU_1_IMR_ATCM_UE_WIDTH 1U
#define RPU_RPU_1_IMR_ATCM_UE_MASK 0X00000200U
#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_SHIFT 8U
#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_WIDTH 1U
#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_MASK 0X00000100U
#define RPU_RPU_1_IMR_DDATA_FAT_SHIFT 7U
#define RPU_RPU_1_IMR_DDATA_FAT_WIDTH 1U
#define RPU_RPU_1_IMR_DDATA_FAT_MASK 0X00000080U
#define RPU_RPU_1_IMR_TCM_LST_FAT_SHIFT 6U
#define RPU_RPU_1_IMR_TCM_LST_FAT_WIDTH 1U
#define RPU_RPU_1_IMR_TCM_LST_FAT_MASK 0X00000040U
#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_SHIFT 5U
#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_WIDTH 1U
#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_MASK 0X00000020U
#define RPU_RPU_1_IMR_DDATA_CE_SHIFT 4U
#define RPU_RPU_1_IMR_DDATA_CE_WIDTH 1U
#define RPU_RPU_1_IMR_DDATA_CE_MASK 0X00000010U
#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_SHIFT 3U
#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_WIDTH 1U
#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_MASK 0X00000008U
#define RPU_RPU_1_IMR_IDATA_CE_SHIFT 2U
#define RPU_RPU_1_IMR_IDATA_CE_WIDTH 1U
#define RPU_RPU_1_IMR_IDATA_CE_MASK 0X00000004U
#define RPU_RPU_1_IMR_ITAG_CE_SHIFT 1U
#define RPU_RPU_1_IMR_ITAG_CE_WIDTH 1U
#define RPU_RPU_1_IMR_ITAG_CE_MASK 0X00000002U
#define RPU_RPU_1_IMR_APB_ERR_SHIFT 0U
#define RPU_RPU_1_IMR_APB_ERR_WIDTH 1U
#define RPU_RPU_1_IMR_APB_ERR_MASK 0X00000001U
/**
* Register: RPU_RPU_1_IEN
*/
#define RPU_RPU_1_IEN ( ( RPU_BASEADDR ) + 0X0000021CU )
#define RPU_RPU_1_IEN_FPUFC_SHIFT 24U
#define RPU_RPU_1_IEN_FPUFC_WIDTH 1U
#define RPU_RPU_1_IEN_FPUFC_MASK 0X01000000U
#define RPU_RPU_1_IEN_FPOFC_SHIFT 23U
#define RPU_RPU_1_IEN_FPOFC_WIDTH 1U
#define RPU_RPU_1_IEN_FPOFC_MASK 0X00800000U
#define RPU_RPU_1_IEN_FPIXC_SHIFT 22U
#define RPU_RPU_1_IEN_FPIXC_WIDTH 1U
#define RPU_RPU_1_IEN_FPIXC_MASK 0X00400000U
#define RPU_RPU_1_IEN_FPIOC_SHIFT 21U
#define RPU_RPU_1_IEN_FPIOC_WIDTH 1U
#define RPU_RPU_1_IEN_FPIOC_MASK 0X00200000U
#define RPU_RPU_1_IEN_FPIDC_SHIFT 20U
#define RPU_RPU_1_IEN_FPIDC_WIDTH 1U
#define RPU_RPU_1_IEN_FPIDC_MASK 0X00100000U
#define RPU_RPU_1_IEN_FPDZC_SHIFT 19U
#define RPU_RPU_1_IEN_FPDZC_WIDTH 1U
#define RPU_RPU_1_IEN_FPDZC_MASK 0X00080000U
#define RPU_RPU_1_IEN_TCM_ASLV_CE_SHIFT 18U
#define RPU_RPU_1_IEN_TCM_ASLV_CE_WIDTH 1U
#define RPU_RPU_1_IEN_TCM_ASLV_CE_MASK 0X00040000U
#define RPU_RPU_1_IEN_TCM_ASLV_FAT_SHIFT 17U
#define RPU_RPU_1_IEN_TCM_ASLV_FAT_WIDTH 1U
#define RPU_RPU_1_IEN_TCM_ASLV_FAT_MASK 0X00020000U
#define RPU_RPU_1_IEN_TCM_LST_CE_SHIFT 16U
#define RPU_RPU_1_IEN_TCM_LST_CE_WIDTH 1U
#define RPU_RPU_1_IEN_TCM_LST_CE_MASK 0X00010000U
#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_SHIFT 15U
#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_WIDTH 1U
#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_MASK 0X00008000U
#define RPU_RPU_1_IEN_B1TCM_CE_SHIFT 14U
#define RPU_RPU_1_IEN_B1TCM_CE_WIDTH 1U
#define RPU_RPU_1_IEN_B1TCM_CE_MASK 0X00004000U
#define RPU_RPU_1_IEN_B0TCM_CE_SHIFT 13U
#define RPU_RPU_1_IEN_B0TCM_CE_WIDTH 1U
#define RPU_RPU_1_IEN_B0TCM_CE_MASK 0X00002000U
#define RPU_RPU_1_IEN_ATCM_CE_SHIFT 12U
#define RPU_RPU_1_IEN_ATCM_CE_WIDTH 1U
#define RPU_RPU_1_IEN_ATCM_CE_MASK 0X00001000U
#define RPU_RPU_1_IEN_B1TCM_UE_SHIFT 11U
#define RPU_RPU_1_IEN_B1TCM_UE_WIDTH 1U
#define RPU_RPU_1_IEN_B1TCM_UE_MASK 0X00000800U
#define RPU_RPU_1_IEN_B0TCM_UE_SHIFT 10U
#define RPU_RPU_1_IEN_B0TCM_UE_WIDTH 1U
#define RPU_RPU_1_IEN_B0TCM_UE_MASK 0X00000400U
#define RPU_RPU_1_IEN_ATCM_UE_SHIFT 9U
#define RPU_RPU_1_IEN_ATCM_UE_WIDTH 1U
#define RPU_RPU_1_IEN_ATCM_UE_MASK 0X00000200U
#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_SHIFT 8U
#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_WIDTH 1U
#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_MASK 0X00000100U
#define RPU_RPU_1_IEN_DDATA_FAT_SHIFT 7U
#define RPU_RPU_1_IEN_DDATA_FAT_WIDTH 1U
#define RPU_RPU_1_IEN_DDATA_FAT_MASK 0X00000080U
#define RPU_RPU_1_IEN_TCM_LST_FAT_SHIFT 6U
#define RPU_RPU_1_IEN_TCM_LST_FAT_WIDTH 1U
#define RPU_RPU_1_IEN_TCM_LST_FAT_MASK 0X00000040U
#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_SHIFT 5U
#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_WIDTH 1U
#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_MASK 0X00000020U
#define RPU_RPU_1_IEN_DDATA_CE_SHIFT 4U
#define RPU_RPU_1_IEN_DDATA_CE_WIDTH 1U
#define RPU_RPU_1_IEN_DDATA_CE_MASK 0X00000010U
#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_SHIFT 3U
#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_WIDTH 1U
#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_MASK 0X00000008U
#define RPU_RPU_1_IEN_IDATA_CE_SHIFT 2U
#define RPU_RPU_1_IEN_IDATA_CE_WIDTH 1U
#define RPU_RPU_1_IEN_IDATA_CE_MASK 0X00000004U
#define RPU_RPU_1_IEN_ITAG_CE_SHIFT 1U
#define RPU_RPU_1_IEN_ITAG_CE_WIDTH 1U
#define RPU_RPU_1_IEN_ITAG_CE_MASK 0X00000002U
#define RPU_RPU_1_IEN_APB_ERR_SHIFT 0U
#define RPU_RPU_1_IEN_APB_ERR_WIDTH 1U
#define RPU_RPU_1_IEN_APB_ERR_MASK 0X00000001U
/**
* Register: RPU_RPU_1_IDS
*/
#define RPU_RPU_1_IDS ( ( RPU_BASEADDR ) + 0X00000220U )
#define RPU_RPU_1_IDS_FPUFC_SHIFT 24U
#define RPU_RPU_1_IDS_FPUFC_WIDTH 1U
#define RPU_RPU_1_IDS_FPUFC_MASK 0X01000000U
#define RPU_RPU_1_IDS_FPOFC_SHIFT 23U
#define RPU_RPU_1_IDS_FPOFC_WIDTH 1U
#define RPU_RPU_1_IDS_FPOFC_MASK 0X00800000U
#define RPU_RPU_1_IDS_FPIXC_SHIFT 22U
#define RPU_RPU_1_IDS_FPIXC_WIDTH 1U
#define RPU_RPU_1_IDS_FPIXC_MASK 0X00400000U
#define RPU_RPU_1_IDS_FPIOC_SHIFT 21U
#define RPU_RPU_1_IDS_FPIOC_WIDTH 1U
#define RPU_RPU_1_IDS_FPIOC_MASK 0X00200000U
#define RPU_RPU_1_IDS_FPIDC_SHIFT 20U
#define RPU_RPU_1_IDS_FPIDC_WIDTH 1U
#define RPU_RPU_1_IDS_FPIDC_MASK 0X00100000U
#define RPU_RPU_1_IDS_FPDZC_SHIFT 19U
#define RPU_RPU_1_IDS_FPDZC_WIDTH 1U
#define RPU_RPU_1_IDS_FPDZC_MASK 0X00080000U
#define RPU_RPU_1_IDS_TCM_ASLV_CE_SHIFT 18U
#define RPU_RPU_1_IDS_TCM_ASLV_CE_WIDTH 1U
#define RPU_RPU_1_IDS_TCM_ASLV_CE_MASK 0X00040000U
#define RPU_RPU_1_IDS_TCM_ASLV_FAT_SHIFT 17U
#define RPU_RPU_1_IDS_TCM_ASLV_FAT_WIDTH 1U
#define RPU_RPU_1_IDS_TCM_ASLV_FAT_MASK 0X00020000U
#define RPU_RPU_1_IDS_TCM_LST_CE_SHIFT 16U
#define RPU_RPU_1_IDS_TCM_LST_CE_WIDTH 1U
#define RPU_RPU_1_IDS_TCM_LST_CE_MASK 0X00010000U
#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_SHIFT 15U
#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_WIDTH 1U
#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_MASK 0X00008000U
#define RPU_RPU_1_IDS_B1TCM_CE_SHIFT 14U
#define RPU_RPU_1_IDS_B1TCM_CE_WIDTH 1U
#define RPU_RPU_1_IDS_B1TCM_CE_MASK 0X00004000U
#define RPU_RPU_1_IDS_B0TCM_CE_SHIFT 13U
#define RPU_RPU_1_IDS_B0TCM_CE_WIDTH 1U
#define RPU_RPU_1_IDS_B0TCM_CE_MASK 0X00002000U
#define RPU_RPU_1_IDS_ATCM_CE_SHIFT 12U
#define RPU_RPU_1_IDS_ATCM_CE_WIDTH 1U
#define RPU_RPU_1_IDS_ATCM_CE_MASK 0X00001000U
#define RPU_RPU_1_IDS_B1TCM_UE_SHIFT 11U
#define RPU_RPU_1_IDS_B1TCM_UE_WIDTH 1U
#define RPU_RPU_1_IDS_B1TCM_UE_MASK 0X00000800U
#define RPU_RPU_1_IDS_B0TCM_UE_SHIFT 10U
#define RPU_RPU_1_IDS_B0TCM_UE_WIDTH 1U
#define RPU_RPU_1_IDS_B0TCM_UE_MASK 0X00000400U
#define RPU_RPU_1_IDS_ATCM_UE_SHIFT 9U
#define RPU_RPU_1_IDS_ATCM_UE_WIDTH 1U
#define RPU_RPU_1_IDS_ATCM_UE_MASK 0X00000200U
#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_SHIFT 8U
#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_WIDTH 1U
#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_MASK 0X00000100U
#define RPU_RPU_1_IDS_DDATA_FAT_SHIFT 7U
#define RPU_RPU_1_IDS_DDATA_FAT_WIDTH 1U
#define RPU_RPU_1_IDS_DDATA_FAT_MASK 0X00000080U
#define RPU_RPU_1_IDS_TCM_LST_FAT_SHIFT 6U
#define RPU_RPU_1_IDS_TCM_LST_FAT_WIDTH 1U
#define RPU_RPU_1_IDS_TCM_LST_FAT_MASK 0X00000040U
#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_SHIFT 5U
#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_WIDTH 1U
#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_MASK 0X00000020U
#define RPU_RPU_1_IDS_DDATA_CE_SHIFT 4U
#define RPU_RPU_1_IDS_DDATA_CE_WIDTH 1U
#define RPU_RPU_1_IDS_DDATA_CE_MASK 0X00000010U
#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_SHIFT 3U
#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_WIDTH 1U
#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_MASK 0X00000008U
#define RPU_RPU_1_IDS_IDATA_CE_SHIFT 2U
#define RPU_RPU_1_IDS_IDATA_CE_WIDTH 1U
#define RPU_RPU_1_IDS_IDATA_CE_MASK 0X00000004U
#define RPU_RPU_1_IDS_ITAG_CE_SHIFT 1U
#define RPU_RPU_1_IDS_ITAG_CE_WIDTH 1U
#define RPU_RPU_1_IDS_ITAG_CE_MASK 0X00000002U
#define RPU_RPU_1_IDS_APB_ERR_SHIFT 0U
#define RPU_RPU_1_IDS_APB_ERR_WIDTH 1U
#define RPU_RPU_1_IDS_APB_ERR_MASK 0X00000001U
/**
* Register: RPU_RPU_1_SLV_BASE
*/
#define RPU_RPU_1_SLV_BASE ( ( RPU_BASEADDR ) + 0X00000224U )
#define RPU_RPU_1_SLV_BASE_ADDR_SHIFT 0U
#define RPU_RPU_1_SLV_BASE_ADDR_WIDTH 8U
#define RPU_RPU_1_SLV_BASE_ADDR_MASK 0X000000FFU
/**
* Register: RPU_RPU_1_AXI_OVER
*/
#define RPU_RPU_1_AXI_OVER ( ( RPU_BASEADDR ) + 0X00000228U )
#define RPU_RPU_1_AXI_OVER_AWCACHE_SHIFT 6U
#define RPU_RPU_1_AXI_OVER_AWCACHE_WIDTH 4U
#define RPU_RPU_1_AXI_OVER_AWCACHE_MASK 0X000003C0U
#define RPU_RPU_1_AXI_OVER_ARCACHE_SHIFT 2U
#define RPU_RPU_1_AXI_OVER_ARCACHE_WIDTH 4U
#define RPU_RPU_1_AXI_OVER_ARCACHE_MASK 0X0000003CU
#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_SHIFT 1U
#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_WIDTH 1U
#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_MASK 0X00000002U
#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_SHIFT 0U
#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_WIDTH 1U
#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_MASK 0X00000001U
#ifdef __cplusplus
}
#endif
#endif /* PM_RPU_H */
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/standalone_v7_2/src/arm/cortexr5/iccarm/Makefile
###############################################################################
# Copyright (c) 2011 - 2020 Xilinx, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
###############################################################################
include config.make
AS=$(ASSEMBLER)
COMPILER=$(COMPILER)
ARCHIVER=$(ARCHIVER)
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
OBJECTS += $(addsuffix .o, $(basename $(wildcard *.s)))
#OBJECTS += boot.o
libs: banner $(LIBS) clean
#boot.s: boot.S
# ${COMPILER} $(INCLUDES) -E -o $@ $<
# rm -f boot.S
%.o: %.s
${AS} --cpu Cortex-R5 --fpu VFPv3_D16 $(INCLUDES) -o $@ $<
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling standalone"
echo "${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<"
standalone_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: standalone_includes
standalone_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pmu_lmb_bram.h
/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _PMU_LMB_BRAM_H_
#define _PMU_LMB_BRAM_H_
#ifdef __cplusplus
extern "C" {
#endif
#define PMU_LMB_BRAM_ECC_STATUS_REG 0xFFD50000U
#define PMU_LMB_BRAM_ECC_IRQ_EN_REG 0xFFD50004U
#define PMU_LMB_BRAM_CE_CNT_REG 0xFFD5000CU
#define PMU_LMB_BRAM_CE_MASK 0x2U
#ifdef __cplusplus
}
#endif
#endif /* _PMU_LMB_BRAM_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_sram.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* SRAM memories slaves definitions and data structures
*********************************************************************/
#ifndef PM_SRAM_H_
#define PM_SRAM_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_slave.h"
typedef struct PmSlaveTcm PmSlaveTcm;
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmSlaveSram - Structure of a sram object, derived from slave
* @slv Base slave structure
* @PwrDn Pointer to a power down pmu-rom handler
* @PwrUp Pointer to a power up pmu-rom handler
* @retCtrlAddr Address of the retention control register
* @retCtrlMask Mask of the retention bits in control register
*/
typedef struct PmSlaveSram {
PmSlave slv;
PmTranHandler PwrDn;
PmTranHandler PwrUp;
const u32 retCtrlAddr;
const u32 retCtrlMask;
} PmSlaveSram;
/**
* PmSlaveTcm - TCM structure derived from SRAM slave
* @sram Base SRAM slave structure
* @eccInit ECC initialization handler (to call on OFF->ON transition)
* @base Base address of the memory bank
* @size Size of the memory bank
* @id ID of the TCM bank
*/
typedef struct PmSlaveTcm {
PmSlaveSram sram;
void (*const eccInit)(const PmSlaveTcm* const tcm);
u32 base;
u32 size;
u8 id;
} PmSlaveTcm;
/*********************************************************************
* Global data declarations
********************************************************************/
extern PmSlaveSram pmSlaveOcm0_g;
extern PmSlaveSram pmSlaveOcm1_g;
extern PmSlaveSram pmSlaveOcm2_g;
extern PmSlaveSram pmSlaveOcm3_g;
extern PmSlaveSram pmSlaveL2_g;
extern PmSlaveTcm pmSlaveTcm0A_g;
extern PmSlaveTcm pmSlaveTcm0B_g;
extern PmSlaveTcm pmSlaveTcm1A_g;
extern PmSlaveTcm pmSlaveTcm1B_g;
#ifdef __cplusplus
}
#endif
#endif /* PM_SRAM_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/iicps_v3_11/src/xiicps_hw.c
/******************************************************************************
* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_hw.c
* @addtogroup iicps_v3_11
* @{
*
* Contains implementation of required functions for providing the reset sequence
* to the i2c interface
*
* <pre> MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------------
* 1.04a kpc 11/07/13 First release
* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
* 3.11 rna 02/11/20 Moved XIicPs_Reset function from xiicps.c
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xiicps.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* @brief
* This function perform the reset sequence to the given I2c interface by
* configuring the appropriate control bits in the I2c specific registers
* the i2cps reset sequence involves the following steps
* Disable all the interuupts
* Clear the status
* Clear FIFO's and disable hold bit
* Clear the line status
* Update relevant config registers with reset values
*
* @param BaseAddress of the interface
*
* @return N/A
*
* @note
* This function will not modify the slcr registers that are relevant for
* I2c controller
******************************************************************************/
void XIicPs_ResetHw(u32 BaseAddress)
{
u32 RegVal;
/* Disable all the interrupts */
XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
/* Clear the interrupt status */
RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
/* Clear the hold bit,master enable bit and ack bit */
RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
/* Clear the fifos */
RegVal |= XIICPS_CR_CLR_FIFO_MASK;
XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
/* Clear the timeout register */
XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
/* Clear the transfer size register */
XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0U);
/* Clear the status register */
RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
/* Update the configuraqtion register with reset value */
XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0U);
}
/*****************************************************************************/
/**
*
* @brief
* Resets the IIC device. Reset must only be called after the driver has been
* initialized. The configuration of the device after reset is the same as its
* configuration after initialization. Any data transfer that is in progress is
* aborted.
*
* The upper layer software is responsible for re-configuring (if necessary)
* and reenabling interrupts for the IIC device after the reset.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIicPs_Reset(XIicPs *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/*
* Abort any transfer that is in progress.
*/
XIicPs_Abort(InstancePtr);
/*
* Reset any values so the software state matches the hardware device.
*/
XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
XIICPS_CR_RESET_VALUE);
XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
XIICPS_IXR_ALL_INTR_MASK);
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_usb.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* Definitions of PM slave USB structures and state transitions.
*********************************************************************/
#include "pm_usb.h"
#include "pm_common.h"
#include "pm_master.h"
#include "pm_reset.h"
#include "xpfw_rom_interface.h"
#include "lpd_slcr.h"
/* Power states of USB */
#define PM_USB_STATE_UNUSED 0U
#define PM_USB_STATE_OFF 1U
#define PM_USB_STATE_ON 2U
/* Power consumptions for USB defined by its states */
#define DEFAULT_USB_POWER_ON 100U
#define DEFAULT_USB_POWER_OFF 0U
/* USB state transition latency values */
#define PM_USB_UNUSED_TO_ON_LATENCY 152U
#define PM_USB_ON_TO_UNUSED_LATENCY 3U
#define PM_USB_ON_TO_OFF_LATENCY 3U
#define PM_USB_OFF_TO_ON_LATENCY 152U
/* USB states */
static const u8 pmUsbStates[] = {
[PM_USB_STATE_UNUSED] = 0U,
[PM_USB_STATE_OFF] = PM_CAP_WAKEUP | PM_CAP_POWER,
[PM_USB_STATE_ON] = PM_CAP_WAKEUP | PM_CAP_ACCESS | PM_CAP_CONTEXT |
PM_CAP_CLOCK | PM_CAP_POWER,
};
/* USB transition table (from which to which state USB can transit) */
static const PmStateTran pmUsbTransitions[] = {
{
.fromState = PM_USB_STATE_OFF,
.toState = PM_USB_STATE_ON,
.latency = PM_USB_OFF_TO_ON_LATENCY,
}, {
.fromState = PM_USB_STATE_UNUSED,
.toState = PM_USB_STATE_ON,
.latency = PM_USB_UNUSED_TO_ON_LATENCY,
}, {
.fromState = PM_USB_STATE_ON,
.toState = PM_USB_STATE_OFF,
.latency = PM_USB_ON_TO_OFF_LATENCY,
}, {
.fromState = PM_USB_STATE_UNUSED,
.toState = PM_USB_STATE_OFF,
.latency = 0U,
}, {
.fromState = PM_USB_STATE_ON,
.toState = PM_USB_STATE_UNUSED,
.latency = PM_USB_ON_TO_UNUSED_LATENCY,
}, {
.fromState = PM_USB_STATE_OFF,
.toState = PM_USB_STATE_UNUSED,
.latency = 0U,
},
};
/**
* PmUsbFsmHandler() - Usb FSM handler, performs transition actions
* @slave Slave whose state should be changed
* @nextState State the slave should enter
*
* @return Status of performing transition action
*/
static s32 PmUsbFsmHandler(PmSlave* const slave, const PmStateId nextState)
{
s32 status;
PmSlaveUsb* usb = (PmSlaveUsb*)slave->node.derived;
switch (slave->node.currState) {
case PM_USB_STATE_ON:
if ((PM_USB_STATE_OFF == nextState) ||
(PM_USB_STATE_UNUSED == nextState)) {
/* ON -> OFF*/
XPfw_AibEnable(usb->aibId);
status = usb->PwrDn();
} else {
status = XST_NO_FEATURE;
}
break;
case PM_USB_STATE_OFF:
case PM_USB_STATE_UNUSED:
if (PM_USB_STATE_ON == nextState) {
/* OFF -> ON */
status = usb->PwrUp();
XPfw_AibDisable(usb->aibId);
if (XST_SUCCESS == status) {
status = PmResetAssertInt(usb->rstId,
PM_RESET_ACTION_PULSE);
}
} else {
status = XST_NO_FEATURE;
}
break;
default:
status = XST_PM_INTERNAL;
PmNodeLogUnknownState(&slave->node, slave->node.currState);
break;
}
return status;
}
/* USB FSM */
static const PmSlaveFsm slaveUsbFsm = {
.states = pmUsbStates,
.enterState = PmUsbFsmHandler,
.trans = pmUsbTransitions,
.statesCnt = ARRAY_SIZE(pmUsbStates),
.transCnt = ARRAY_SIZE(pmUsbTransitions),
};
static PmWakeEventGicProxy pmUsb0Wake = {
.wake = {
.derived = &pmUsb0Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP2_IRQ_MASK_SRC11_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC5_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC4_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC3_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC2_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC1_MASK,
.group = 2U,
};
static u8 PmUsbPowers[] = {
[PM_USB_STATE_UNUSED] = DEFAULT_USB_POWER_OFF,
[PM_USB_STATE_OFF] = DEFAULT_USB_POWER_OFF,
[PM_USB_STATE_ON] = DEFAULT_USB_POWER_ON,
};
PmSlaveUsb pmSlaveUsb0_g = {
.slv = {
.node = {
.derived = &pmSlaveUsb0_g,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
DEFINE_PM_POWER_INFO(PmUsbPowers),
.latencyMarg = MAX_LATENCY,
DEFINE_NODE_NAME("usb0"),
.nodeId = NODE_USB_0,
.currState = PM_USB_STATE_ON,
.flags = 0U,
},
.class = NULL,
.reqs = NULL,
.wake = &pmUsb0Wake.wake,
.slvFsm = &slaveUsbFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnUsb0Handler,
.PwrUp = XpbrPwrUpUsb0Handler,
.rstId = PM_RESET_USB0_CORERESET,
.aibId = XPFW_AIB_LPD_TO_USB0,
};
static PmWakeEventGicProxy pmUsb1Wake = {
.wake = {
.derived = &pmUsb1Wake,
.class = &pmWakeEventClassGicProxy_g,
},
.mask = LPD_SLCR_GICP2_IRQ_MASK_SRC12_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC10_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC9_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC8_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC7_MASK |
LPD_SLCR_GICP2_IRQ_MASK_SRC6_MASK,
.group = 2U,
};
PmSlaveUsb pmSlaveUsb1_g = {
.slv = {
.node = {
.derived = &pmSlaveUsb1_g,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainLpd_g.power,
.clocks = NULL,
DEFINE_PM_POWER_INFO(PmUsbPowers),
.latencyMarg = MAX_LATENCY,
DEFINE_NODE_NAME("usb1"),
.nodeId = NODE_USB_1,
.currState = PM_USB_STATE_ON,
.flags = 0U,
},
.class = NULL,
.reqs = NULL,
.wake = &pmUsb1Wake.wake,
.slvFsm = &slaveUsbFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnUsb1Handler,
.PwrUp = XpbrPwrUpUsb1Handler,
.rstId = PM_RESET_USB1_CORERESET,
.aibId = XPFW_AIB_LPD_TO_USB1,
};
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/xfsbl_ddr_init.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xfsbl_ddr_init.h
*
* This is the file which contains definition for initialization function
* for the DDR.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 mn 07/06/18 Add DDR initialization support for new DDR DIMM part
* mn 07/30/18 Define some DDR registers addresses if not defined
* 2.0 mn 02/28/19 Add Dynamic DDR initialization support for all DDR DIMMs
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XFSBL_DDR_INIT_H
#define XFSBL_DDR_INIT_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef XFSBL_PS_DDR
#ifdef XPAR_DYNAMIC_DDR_ENABLED
/***************************** Include Files *********************************/
#include "psu_init.h"
/************************** Constant Definitions *****************************/
/* Maximum number of Rows in DDR */
#define XFSBL_MAX_ROWS 18U
/* Maximum number of Columns in DDR */
#define XFSBL_MAX_COLUMNS 12U
/* Maximum number of Banks in DDR */
#define XFSBL_MAX_BANKS 3U
/* Maximum number of Bank Groups in DDR */
#define XFSBL_MAX_BANK_GROUPS 2U
/* Total number of DDR controller registers */
#define XFSBL_DDRC_REG_COUNT 115U
/* Total number of DDR PHY registers */
#define XFSBL_DDR_PHY_REG_COUNT 127U
/* In some older designs, this register is not used in psu_init flow */
#ifndef DDR_PHY_GPR0_OFFSET
#define DDR_PHY_GPR0_OFFSET 0xFD0800C0U
#endif
#ifndef DDRC_STAT_OFFSET
#define DDRC_STAT_OFFSET 0xFD070004U
#endif
#ifndef DDRC_MRSTAT_OFFSET
#define DDRC_MRSTAT_OFFSET 0xFD070018U
#endif
#ifndef DDRC_RFSHCTL1_OFFSET
#define DDRC_RFSHCTL1_OFFSET 0xFD070054U
#endif
#ifndef DDRC_DFIUPD0_OFFSET
#define DDRC_DFIUPD0_OFFSET 0xFD0701A0U
#endif
#ifndef DDRC_DQMAP0_OFFSET
#define DDRC_DQMAP0_OFFSET 0xFD070280U
#endif
#ifndef DDRC_DQMAP1_OFFSET
#define DDRC_DQMAP1_OFFSET 0xFD070284U
#endif
#ifndef DDRC_DQMAP2_OFFSET
#define DDRC_DQMAP2_OFFSET 0xFD070288U
#endif
#ifndef DDRC_DQMAP3_OFFSET
#define DDRC_DQMAP3_OFFSET 0xFD07028CU
#endif
#ifndef DDRC_DQMAP4_OFFSET
#define DDRC_DQMAP4_OFFSET 0xFD070290U
#endif
#ifndef DDR_PHY_PIR_OFFSET
#define DDR_PHY_PIR_OFFSET 0xFD080004U
#endif
#ifndef DDR_PHY_PGCR1_OFFSET
#define DDR_PHY_PGCR1_OFFSET 0xFD080014U
#endif
#ifndef DDR_PHY_PGCR6_OFFSET
#define DDR_PHY_PGCR6_OFFSET 0xFD080028U
#endif
#ifndef DDR_PHY_PGSR0_OFFSET
#define DDR_PHY_PGSR0_OFFSET 0xFD080030U
#endif
#ifndef DDR_PHY_PLLCR0_OFFSET
#define DDR_PHY_PLLCR0_OFFSET 0xFD080068U
#endif
#ifndef DDR_PHY_ODTCR_OFFSET
#define DDR_PHY_ODTCR_OFFSET 0xFD080098U
#endif
#ifndef DDR_PHY_GPR1_OFFSET
#define DDR_PHY_GPR1_OFFSET 0xFD0800C4U
#endif
#ifndef DDR_PHY_SCHCR0_OFFSET
#define DDR_PHY_SCHCR0_OFFSET 0xFD080168U
#endif
#ifndef DDR_PHY_SCHCR1_OFFSET
#define DDR_PHY_SCHCR1_OFFSET 0xFD08016CU
#endif
#ifndef DDR_PHY_DQSDR0_OFFSET
#define DDR_PHY_DQSDR0_OFFSET 0xFD080250U
#endif
#ifndef DDR_PHY_DQSDR1_OFFSET
#define DDR_PHY_DQSDR1_OFFSET 0xFD080254U
#endif
#ifndef DDR_PHY_RANKIDR_OFFSET
#define DDR_PHY_RANKIDR_OFFSET 0xFD0804DCU
#endif
#ifndef DDR_PHY_DX0BDLR3_OFFSET
#define DDR_PHY_DX0BDLR3_OFFSET 0xFD080750U
#endif
#ifndef DDR_PHY_DX0BDLR4_OFFSET
#define DDR_PHY_DX0BDLR4_OFFSET 0xFD080754U
#endif
#ifndef DDR_PHY_DX0BDLR5_OFFSET
#define DDR_PHY_DX0BDLR5_OFFSET 0xFD080758U
#endif
#ifndef DDR_PHY_DX0LCDLR1_OFFSET
#define DDR_PHY_DX0LCDLR1_OFFSET 0xFD080784U
#endif
#ifndef DDR_PHY_DX0MDLR0_OFFSET
#define DDR_PHY_DX0MDLR0_OFFSET 0xFD0807A0U
#endif
#ifndef DDR_PHY_DX0GTR0_OFFSET
#define DDR_PHY_DX0GTR0_OFFSET 0xFD0807C0U
#endif
#ifndef DDR_PHY_DX0GSR0_OFFSET
#define DDR_PHY_DX0GSR0_OFFSET 0xFD0807E0U
#endif
#ifndef DDR_PHY_DX2GSR0_OFFSET
#define DDR_PHY_DX2GSR0_OFFSET 0xFD0809E0U
#endif
#ifndef DDR_PHY_DX4GSR0_OFFSET
#define DDR_PHY_DX4GSR0_OFFSET 0xFD080BE0U
#endif
#ifndef DDR_PHY_DX6GSR0_OFFSET
#define DDR_PHY_DX6GSR0_OFFSET 0xFD080DE0U
#endif
#ifndef DDR_PHY_DX8GSR0_OFFSET
#define DDR_PHY_DX8GSR0_OFFSET 0xFD080FE0U
#endif
#ifndef DDR_PHY_DX1BDLR3_OFFSET
#define DDR_PHY_DX1BDLR3_OFFSET 0xFD080850U
#endif
#ifndef DDR_PHY_DX1BDLR4_OFFSET
#define DDR_PHY_DX1BDLR4_OFFSET 0xFD080854U
#endif
#ifndef DDR_PHY_DX1BDLR5_OFFSET
#define DDR_PHY_DX1BDLR5_OFFSET 0xFD080858U
#endif
#ifndef DDR_PHY_DX2BDLR3_OFFSET
#define DDR_PHY_DX2BDLR3_OFFSET 0xFD080950U
#endif
#ifndef DDR_PHY_DX2BDLR4_OFFSET
#define DDR_PHY_DX2BDLR4_OFFSET 0xFD080954U
#endif
#ifndef DDR_PHY_DX2BDLR5_OFFSET
#define DDR_PHY_DX2BDLR5_OFFSET 0xFD080958U
#endif
#ifndef DDR_PHY_DX3BDLR3_OFFSET
#define DDR_PHY_DX3BDLR3_OFFSET 0xFD080A50U
#endif
#ifndef DDR_PHY_DX3BDLR4_OFFSET
#define DDR_PHY_DX3BDLR4_OFFSET 0xFD080A54U
#endif
#ifndef DDR_PHY_DX3BDLR5_OFFSET
#define DDR_PHY_DX3BDLR5_OFFSET 0xFD080A58U
#endif
#ifndef DDR_PHY_DX4BDLR3_OFFSET
#define DDR_PHY_DX4BDLR3_OFFSET 0xFD080B50U
#endif
#ifndef DDR_PHY_DX4BDLR4_OFFSET
#define DDR_PHY_DX4BDLR4_OFFSET 0xFD080B54U
#endif
#ifndef DDR_PHY_DX4BDLR5_OFFSET
#define DDR_PHY_DX4BDLR5_OFFSET 0xFD080B58U
#endif
#ifndef DDR_PHY_DX5BDLR3_OFFSET
#define DDR_PHY_DX5BDLR3_OFFSET 0xFD080C50U
#endif
#ifndef DDR_PHY_DX5BDLR4_OFFSET
#define DDR_PHY_DX5BDLR4_OFFSET 0xFD080C54U
#endif
#ifndef DDR_PHY_DX5BDLR5_OFFSET
#define DDR_PHY_DX5BDLR5_OFFSET 0xFD080C58U
#endif
#ifndef DDR_PHY_DX6BDLR3_OFFSET
#define DDR_PHY_DX6BDLR3_OFFSET 0xFD080D50U
#endif
#ifndef DDR_PHY_DX6BDLR4_OFFSET
#define DDR_PHY_DX6BDLR4_OFFSET 0xFD080D54U
#endif
#ifndef DDR_PHY_DX6BDLR5_OFFSET
#define DDR_PHY_DX6BDLR5_OFFSET 0xFD080D58U
#endif
#ifndef DDR_PHY_DX7BDLR3_OFFSET
#define DDR_PHY_DX7BDLR3_OFFSET 0xFD080E50U
#endif
#ifndef DDR_PHY_DX7BDLR4_OFFSET
#define DDR_PHY_DX7BDLR4_OFFSET 0xFD080E54U
#endif
#ifndef DDR_PHY_DX7BDLR5_OFFSET
#define DDR_PHY_DX7BDLR5_OFFSET 0xFD080E58U
#endif
#ifndef DDR_PHY_DX8BDLR3_OFFSET
#define DDR_PHY_DX8BDLR3_OFFSET 0xFD080F50U
#endif
#ifndef DDR_PHY_DX8BDLR4_OFFSET
#define DDR_PHY_DX8BDLR4_OFFSET 0xFD080F54U
#endif
#ifndef DDR_PHY_DX8BDLR5_OFFSET
#define DDR_PHY_DX8BDLR5_OFFSET 0xFD080F58U
#endif
#ifndef DDR_PHY_DX8SL0PLLCR0_OFFSET
#define DDR_PHY_DX8SL0PLLCR0_OFFSET 0xFD081404U
#endif
#ifndef DDR_PHY_DX8SL1PLLCR0_OFFSET
#define DDR_PHY_DX8SL1PLLCR0_OFFSET 0xFD081444U
#endif
#ifndef DDR_PHY_DX8SL2PLLCR0_OFFSET
#define DDR_PHY_DX8SL2PLLCR0_OFFSET 0xFD081484U
#endif
#ifndef DDR_PHY_DX8SL3PLLCR0_OFFSET
#define DDR_PHY_DX8SL3PLLCR0_OFFSET 0xFD0814C4U
#endif
#ifndef DDR_PHY_DX8SL4PLLCR0_OFFSET
#define DDR_PHY_DX8SL4PLLCR0_OFFSET 0xFD081504U
#endif
#ifndef DDR_PHY_DX8SLBPLLCR0_OFFSET
#define DDR_PHY_DX8SLBPLLCR0_OFFSET 0xFD0817C4U
#endif
#ifndef DDR_QOS_CTRL_DDRPHY_CTRL_OFFSET
#define DDR_QOS_CTRL_DDRPHY_CTRL_OFFSET 0xFD090708U
#endif
#ifndef DDR_QOS_CTRL_DDR_CLK_CTRL_OFFSET
#define DDR_QOS_CTRL_DDR_CLK_CTRL_OFFSET 0xFD090700U
#endif
#define DDR_PHY_PIR_INIT_SHIFT 0U
#define DDR_PHY_PIR_INIT_WIDTH 1U
#define DDR_PHY_PIR_INIT_MASK 0x00000001U
#define DDR_PHY_PIR_INIT_DEFVAL 0x0U
#define DDR_PHY_PIR_DCALPSE_SHIFT 29U
#define DDR_PHY_PIR_DCALPSE_WIDTH 1U
#define DDR_PHY_PIR_DCALPSE_MASK 0x20000000U
#define DDR_PHY_PIR_DCALPSE_DEFVAL 0x0U
#define DDR_PHY_PIR_CTLDINIT_SHIFT 18U
#define DDR_PHY_PIR_CTLDINIT_WIDTH 1U
#define DDR_PHY_PIR_CTLDINIT_MASK 0x00040000U
#define DDR_PHY_PIR_CTLDINIT_DEFVAL 0x0U
#define DDR_PHY_PIR_PHYRST_SHIFT 6U
#define DDR_PHY_PIR_PHYRST_WIDTH 1U
#define DDR_PHY_PIR_PHYRST_MASK 0x00000040U
#define DDR_PHY_PIR_PHYRST_DEFVAL 0x0U
#define DDR_PHY_PIR_DCAL_SHIFT 5U
#define DDR_PHY_PIR_DCAL_WIDTH 1U
#define DDR_PHY_PIR_DCAL_MASK 0x00000020U
#define DDR_PHY_PIR_DCAL_DEFVAL 0x0U
#define DDR_PHY_PIR_PLLINIT_SHIFT 4U
#define DDR_PHY_PIR_PLLINIT_MASK 0x00000010U
#define DDR_PHY_PIR_QSGATE_SHIFT 10U
#define DDR_PHY_PIR_QSGATE_MASK 0x00000400U
#define DDR_PHY_PIR_WL_SHIFT 9U
#define DDR_PHY_PIR_WL_MASK 0x00000200U
#define DDR_PHY_PGSR0_IDONE_SHIFT 0U
#define DDR_PHY_PGSR0_IDONE_MASK 0x00000001U
#define DDR_PHY_PGCR1_PUBMODE_SHIFT 6U
#define DDR_PHY_PGCR1_PUBMODE_WIDTH 1U
#define DDR_PHY_PGCR1_PUBMODE_MASK 0x00000040U
#define DDR_PHY_PGCR1_PUBMODE_DEFVAL 0x0U
#define DDR_PHY_PGCR1_PHYHRST_SHIFT 25U
#define DDR_PHY_PGCR1_PHYHRST_WIDTH 1U
#define DDR_PHY_PGCR1_PHYHRST_MASK 0x02000000U
#define DDR_PHY_PGCR1_PHYHRST_DEFVAL 0x1U
#define DDR_PHY_SCHCR0_SP_CMD_SHIFT 8U
#define DDR_PHY_SCHCR0_SP_CMD_WIDTH 4U
#define DDR_PHY_SCHCR0_SP_CMD_MASK 0x00000F00U
#define DDR_PHY_SCHCR0_SP_CMD_DEFVAL 0x0U
#define DDR_PHY_SCHCR0_CMD_SHIFT 4U
#define DDR_PHY_SCHCR0_CMD_WIDTH 4U
#define DDR_PHY_SCHCR0_CMD_MASK 0x000000F0U
#define DDR_PHY_SCHCR0_CMD_DEFVAL 0x0U
#define DDR_PHY_SCHCR0_SCHTRIG_SHIFT 0U
#define DDR_PHY_SCHCR0_SCHTRIG_WIDTH 4U
#define DDR_PHY_SCHCR0_SCHTRIG_MASK 0x0000000FU
#define DDR_PHY_SCHCR0_SCHTRIG_DEFVAL 0x0U
#define DDR_PHY_SCHCR1_ALLRANK_SHIFT 2U
#define DDR_PHY_SCHCR1_ALLRANK_WIDTH 1U
#define DDR_PHY_SCHCR1_ALLRANK_MASK 0x00000004U
#define DDR_PHY_SCHCR1_ALLRANK_DEFVAL 0x0U
#define DDR_PHY_RANKIDR_RANKWID_SHIFT 0U
#define DDR_PHY_RANKIDR_RANKWID_WIDTH 4U
#define DDR_PHY_RANKIDR_RANKWID_MASK 0x0000000FU
#define DDR_PHY_RANKIDR_RANKWID_DEFVAL 0x0U
#define DDR_PHY_PGCR6_INHVT_SHIFT 0U
#define DDR_PHY_PGCR6_INHVT_MASK 0x00000001U
#define DDR_PHY_ODTCR_WRODT_SHIFT 16U
#define DDR_PHY_ODTCR_WRODT_WIDTH 2U
#define DDR_PHY_ODTCR_WRODT_MASK 0x00030000U
#define DDR_PHY_ODTCR_WRODT_DEFVAL 0x1U
#define DDR_PHY_DTCR0_INCWEYE_SHIFT 4U
#define DDR_PHY_DTCR0_INCWEYE_WIDTH 1U
#define DDR_PHY_DTCR0_INCWEYE_MASK 0x00000010U
#define DDR_PHY_DTCR0_INCWEYE_DEFVAL 0x0U
#define DDR_PHY_DQSDR1_DFTRDIDLC_SHIFT 0U
#define DDR_PHY_DQSDR1_DFTRDIDLC_WIDTH 8U
#define DDR_PHY_DQSDR1_DFTRDIDLC_MASK 0x000000FFU
#define DDR_PHY_DQSDR1_DFTRDIDLC_DEFVAL 0x0U
#define DDR_PHY_DQSDR1_DFTRDIDLF_SHIFT 16U
#define DDR_PHY_DQSDR1_DFTRDIDLF_WIDTH 4U
#define DDR_PHY_DQSDR1_DFTRDIDLF_MASK 0x000F0000U
#define DDR_PHY_DQSDR1_DFTRDIDLF_DEFVAL 0x0U
#define DDR_PHY_DXBDLR_DQ0RBD_SHIFT 0U
#define DDR_PHY_DXBDLR_DQ0RBD_MASK 0x0000003FU
#define DDR_PHY_DXBDLR_DQ1RBD_SHIFT 8U
#define DDR_PHY_DXBDLR_DQ1RBD_MASK 0x00003F00U
#define DDR_PHY_DXBDLR_DQ2RBD_SHIFT 16U
#define DDR_PHY_DXBDLR_DQ2RBD_MASK 0x003F0000U
#define DDR_PHY_DXBDLR_DQ3RBD_SHIFT 24U
#define DDR_PHY_DXBDLR_DQ3RBD_MASK 0x3F000000U
#define DDR_PHY_DX0BDLR5_DMRBD_SHIFT 0U
#define DDR_PHY_DXBDLR5_DMRBD_MASK 0x0000003FU
#define DDR_PHY_DXGTR0_WDQSL_SHIFT 24U
#define DDR_PHY_DXGTR0_WDQSL_MASK 0x07000000U
#define DDR_PHY_DXLCDLR1_WDQD_SHIFT 0U
#define DDR_PHY_DXLCDLR1_WDQD_MASK 0x000001FFU
#define DDR_PHY_DXMDLR0_IPRD_SHIFT 0U
#define DDR_PHY_DXMDLR0_IPRD_MASK 0x000001FFU
#define DDR_PHY_PIR_DQS2DQ_SHIFT 20U
#define DDR_PHY_PIR_DQS2DQ_MASK 0x00100000U
#define DDR_PHY_PGSR0_DQS2DQDONE_SHIFT 15U
#define DDR_PHY_PGSR0_DQS2DQDONE_MASK 0x00008000U
#define DDR_PHY_PIR_DQS2DQ_SHIFT 20U
#define DDR_PHY_PIR_DQS2DQ_MASK 0x00100000U
#define DDR_PHY_PGSR0_DQS2DQDONE_SHIFT 15U
#define DDR_PHY_PGSR0_DQS2DQDONE_MASK 0x00008000U
#define DDR_PHY_PIR_VREF_SHIFT 17U
#define DDR_PHY_PIR_VREF_MASK 0x00020000U
#define DDR_PHY_PIR_WREYE_SHIFT 15U
#define DDR_PHY_PIR_WREYE_MASK 0x00008000U
#define DDR_PHY_PIR_RDEYE_SHIFT 14U
#define DDR_PHY_PIR_RDEYE_MASK 0x00004000U
#define DDR_PHY_PGSR0_REDONE_SHIFT 10U
#define DDR_PHY_PGSR0_REDONE_MASK 0x00000400U
#define DDR_PHY_PIR_WLADJ_SHIFT 11U
#define DDR_PHY_PIR_WLADJ_MASK 0x00000800U
#define DDR_PHY_PIR_WRDSKW_SHIFT 13U
#define DDR_PHY_PIR_WRDSKW_MASK 0x00002000U
#define DDR_PHY_PIR_RDDSKW_SHIFT 12U
#define DDR_PHY_PIR_RDDSKW_MASK 0x00001000U
#define DDR_PHY_RANKIDR_RANKRID_SHIFT 16U
#define DDR_PHY_RANKIDR_RANKRID_MASK 0x000F0000U
#define DDR_QOS_CTRL_DDRPHY_CTRL_BYP_MODE_SHIFT 0U
#define DDR_QOS_CTRL_DDRPHY_CTRL_BYP_MODE_WIDTH 1U
#define DDR_QOS_CTRL_DDRPHY_CTRL_BYP_MODE_MASK 0x00000001U
#define DDR_QOS_CTRL_DDRPHY_CTRL_BYP_MODE_DEFVAL 0x0U
#define DDR_QOS_CTRL_DDR_CLK_CTRL_CLKACT_SHIFT 0U
#define DDR_QOS_CTRL_DDR_CLK_CTRL_CLKACT_WIDTH 1U
#define DDR_QOS_CTRL_DDR_CLK_CTRL_CLKACT_MASK 0x00000001U
#define DDR_QOS_CTRL_DDR_CLK_CTRL_CLKACT_DEFVAL 0x1U
/*
* Byte 2U Fundamental Memory Types.
*/
#define SPD_MEMTYPE_FPM (0x01U)
#define SPD_MEMTYPE_EDO (0x02U)
#define SPD_MEMTYPE_PIPE_NIBBLE (0x03U)
#define SPD_MEMTYPE_SDRAM (0x04U)
#define SPD_MEMTYPE_ROM (0x05U)
#define SPD_MEMTYPE_SGRAM (0x06U)
#define SPD_MEMTYPE_DDR (0x07U)
#define SPD_MEMTYPE_DDR2 (0x08U)
#define SPD_MEMTYPE_DDR2_FBDIMM (0x09U)
#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0AU)
#define SPD_MEMTYPE_DDR3 (0x0BU)
#define SPD_MEMTYPE_DDR4 (0x0CU)
#define SPD_MEMTYPE_LPDDR3 (0x0FU)
#define SPD_MEMTYPE_LPDDR4 (0x10U)
/* Byte 3U Key Byte / Module Type for DDR3 SPD */
#define DDR3_SPD_MODULETYPE_MASK (0x0FU)
#define DDR3_SPD_MODULETYPE_RDIMM (0x01U)
#define DDR3_SPD_MODULETYPE_UDIMM (0x02U)
#define DDR3_SPD_MODULETYPE_SO_DIMM (0x03U)
#define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04U)
#define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05U)
#define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06U)
#define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07U)
#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08U)
#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09U)
#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0AU)
#define DDR3_SPD_MODULETYPE_LRDIMM (0x0BU)
#define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0CU)
#define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0DU)
/* DIMM Type for DDR4 SPD */
#define DDR4_SPD_MODULETYPE_MASK (0x0FU)
#define DDR4_SPD_MODULETYPE_EXT (0x00U)
#define DDR4_SPD_MODULETYPE_RDIMM (0x01U)
#define DDR4_SPD_MODULETYPE_UDIMM (0x02U)
#define DDR4_SPD_MODULETYPE_SO_DIMM (0x03U)
#define DDR4_SPD_MODULETYPE_LRDIMM (0x04U)
#define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05U)
#define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06U)
#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x08U)
#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x09U)
#define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0CU)
#define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0DU)
/* DIMM Type for LPDDR SPD */
#define LPDDR_SPD_MODULETYPE_MASK (0x0FU)
#define LPDDR_SPD_MODULETYPE_EXT (0x00U)
#define LPDDR_SPD_MODULETYPE_LPDIMM (0x07U)
#define LPDDR_SPD_MODULETYPE_NON_DIMM (0xEU)
/* DDRC Register fields */
enum {
DDR_DEVICE_CONFIG,
DDR_FREQUENCY_MODE,
DDR_ACTIVE_RANKS,
DDR_BURST_RDWR,
DDR_DLL_OFF_MODE,
DDR_DATA_BUS_WIDTH,
DDR_GEARDOWN_MODE,
DDR_EN_2T_TIMING_MODE,
DDR_BURSTCHOP,
DDR_LPDDR4,
DDR_DDR4,
DDR_LPDDR3,
DDR_LPDDR2,
DDR_DDR3,
DDR_MR_WR,
DDR_MR_ADDR,
DDR_MR_RANK,
DDR_SW_INIT_INT,
DDR_PDA_EN,
DDR_MPR_EN,
DDR_MR_TYPE,
DDR_RC_DERATE_VALUE,
DDR_DERATE_BYTE,
DDR_DERATE_VALUE,
DDR_DERATE_ENABLE,
DDR_MR4_READ_INTERVAL,
DDR_STAY_IN_SELFREF,
DDR_SELFREF_SW,
DDR_MPSM_EN,
DDR_EN_DFI_DRAM_CLK_DISABLE,
DDR_DEEPPOWERDOWN_EN,
DDR_POWERDOWN_EN,
DDR_SELFREF_EN,
DDR_SELFREF_TO_X32,
DDR_T_DPD_X4096,
DDR_POWERDOWN_TO_X32,
DDR_REFRESH_MARGIN,
DDR_REFRESH_TO_X32,
DDR_REFRESH_BURST,
DDR_PER_BANK_REFRESH,
DDR_REFRESH_TIMER1_START_VALUE_X32,
DDR_REFRESH_TIMER0_START_VALUE_X32,
DDR_REFRESH_MODE,
DDR_REFRESH_UPDATE_LEVEL,
DDR_DIS_AUTO_REFRESH,
DDR_T_RFC_NOM_X32,
DDR_LPDDR3_TREFBW_EN,
DDR_T_RFC_MIN,
DDR_DIS_SCRUB,
DDR_ECC_MODE,
DDR_DATA_POISON_BIT,
DDR_DATA_POISON_EN,
DDR_DFI_T_PHY_RDLAT,
DDR_ALERT_WAIT_FOR_SW,
DDR_CRC_PARITY_RETRY_ENABLE,
DDR_CRC_INC_DM,
DDR_CRC_ENABLE,
DDR_PARITY_ENABLE,
DDR_T_PAR_ALERT_PW_MAX,
DDR_T_CRC_ALERT_PW_MAX,
DDR_RETRY_FIFO_MAX_HOLD_TIMER_X4,
DDR_SKIP_DRAM_INIT,
DDR_POST_CKE_X1024,
DDR_PRE_CKE_X1024,
DDR_DRAM_RSTN_X1024,
DDR_FINAL_WAIT_X32,
DDR_PRE_OCD_X32,
DDR_IDLE_AFTER_RESET_X32,
DDR_MIN_STABLE_CLOCK_X1,
DDR_MR,
DDR_EMR,
DDR_EMR2,
DDR_EMR3,
DDR_DEV_ZQINIT_X32,
DDR_MAX_AUTO_INIT_X1024,
DDR_MR4,
DDR_MR5,
DDR_MR6,
DDR_DIMM_DIS_BG_MIRRORING,
DDR_MRS_BG1_EN,
DDR_MRS_A17_EN,
DDR_DIMM_OUTPUT_INV_EN,
DDR_DIMM_ADDR_MIRR_EN,
DDR_DIMM_STAGGER_CS_EN,
DDR_DIFF_RANK_WR_GAP,
DDR_DIFF_RANK_RD_GAP,
DDR_MAX_RANK_RD,
DDR_WR2PRE,
DDR_T_FAW,
DDR_T_RAS_MAX,
DDR_T_RAS_MIN,
DDR_T_XP,
DDR_RD2PRE,
DDR_T_RC,
DDR_WRITE_LATENCY,
DDR_READ_LATENCY,
DDR_RD2WR,
DDR_WR2RD,
DDR_T_MRW,
DDR_T_MRD,
DDR_T_MOD,
DDR_T_RCD,
DDR_T_CCD,
DDR_T_RRD,
DDR_T_RP,
DDR_T_CKSRX,
DDR_T_CKSRE,
DDR_T_CKESR,
DDR_T_CKE,
DDR_T_CKDPDE,
DDR_T_CKDPDX,
DDR_T_CKCSX,
DDR_T_CKPDE,
DDR_T_CKPDX,
DDR_T_XS_FAST_X32,
DDR_T_XS_ABORT_X32,
DDR_T_XS_DLL_X32,
DDR_T_XS_X32,
DDR_DDR4_WR_PREAMBLE,
DDR_T_CCD_S,
DDR_T_RRD_S,
DDR_WR2RD_S,
DDR_POST_MPSM_GAP_X32,
DDR_T_MPX_LH,
DDR_T_MPX_S,
DDR_T_CKMPE,
DDR_T_CMDCKE,
DDR_T_CKEHCMD,
DDR_T_MRD_PDA,
DDR_DIS_AUTO_ZQ,
DDR_DIS_SRX_ZQCL,
DDR_ZQ_RESISTOR_SHARED,
DDR_DIS_MPSMX_ZQCL,
DDR_T_ZQ_LONG_NOP,
DDR_T_ZQ_SHORT_NOP,
DDR_T_ZQ_RESET_NOP,
DDR_T_ZQ_SHORT_INTERVAL_X1024,
DDR_DFI_T_CTRL_DELAY,
DDR_DFI_RDDATA_USE_SDR,
DDR_DFI_T_RDDATA_EN,
DDR_DFI_WRDATA_USE_SDR,
DDR_DFI_TPHY_WRDATA,
DDR_DFI_TPHY_WRLAT,
DDR_DFI_T_CMD_LAT,
DDR_DFI_T_PARIN_LAT,
DDR_DFI_T_WRDATA_DELAY,
DDR_DFI_T_DRAM_CLK_DISABLE,
DDR_DFI_T_DRAM_CLK_ENABLE,
DDR_DFI_TLP_RESP,
DDR_DFI_LP_WAKEUP_DPD,
DDR_DFI_LP_EN_DPD,
DDR_DFI_LP_WAKEUP_SR,
DDR_DFI_LP_EN_SR,
DDR_DFI_LP_WAKEUP_PD,
DDR_DFI_LP_EN_PD,
DDR_DFI_LP_WAKEUP_MPSM,
DDR_DFI_LP_EN_MPSM,
DDR_DIS_AUTO_CTRLUPD,
DDR_DIS_AUTO_CTRLUPD_SRX,
DDR_DFI_T_CTRLUP_MAX,
DDR_DFI_T_CTRLUP_MIN,
DDR_DFI_T_CTRLUPD_INTERVAL_MIN_X1024,
DDR_DFI_T_CTRLUPD_INTERVAL_MAX_X1024,
DDR_DFI_DATA_CS_POLARITY,
DDR_PHY_DBI_MODE,
DDR_DFI_INIT_COMPLETE_EN,
DDR_DFI_TPHY_RDCSLAT,
DDR_DFI_TPHY_WRCSLAT,
DDR_RD_DBI_EN,
DDR_WR_DBI_EN,
DDR_DM_EN,
DDR_ADDRMAP_CS_BIT0,
DDR_ADDRMAP_BANK_B2,
DDR_ADDRMAP_BANK_B1,
DDR_ADDRMAP_BANK_B0,
DDR_ADDRMAP_COL_B5,
DDR_ADDRMAP_COL_B4,
DDR_ADDRMAP_COL_B3,
DDR_ADDRMAP_COL_B2,
DDR_ADDRMAP_COL_B9,
DDR_ADDRMAP_COL_B8,
DDR_ADDRMAP_COL_B7,
DDR_ADDRMAP_COL_B6,
DDR_ADDRMAP_COL_B11,
DDR_ADDRMAP_COL_B10,
DDR_ADDRMAP_ROW_B11,
DDR_ADDRMAP_ROW_B2_10,
DDR_ADDRMAP_ROW_B1,
DDR_ADDRMAP_ROW_B0,
DDR_LPDDR3_6GB_12GB,
DDR_ADDRMAP_ROW_B15,
DDR_ADDRMAP_ROW_B14,
DDR_ADDRMAP_ROW_B13,
DDR_ADDRMAP_ROW_B12,
DDR_ADDRMAP_ROW_B17,
DDR_ADDRMAP_ROW_B16,
DDR_ADDRMAP_BG_B1,
DDR_ADDRMAP_BG_B0,
DDR_ADDRMAP_ROW_B5,
DDR_ADDRMAP_ROW_B4,
DDR_ADDRMAP_ROW_B3,
DDR_ADDRMAP_ROW_B2,
DDR_ADDRMAP_ROW_B9,
DDR_ADDRMAP_ROW_B8,
DDR_ADDRMAP_ROW_B7,
DDR_ADDRMAP_ROW_B6,
DDR_ADDRMAP_ROW_B10,
DDR_WR_ODT_HOLD,
DDR_WR_ODT_DELAY,
DDR_RD_ODT_HOLD,
DDR_RD_ODT_DELAY,
DDR_RANK1_RD_ODT,
DDR_RANK1_WR_ODT,
DDR_RANK0_RD_ODT,
DDR_RANK0_WR_ODT,
DDR_RDWR_IDLE_GAP,
DDR_GO2CRITICAL_HYSTERESIS,
DDR_LPR_NUM_ENTRIES,
DDR_PAGECLOSE,
DDR_PREFER_WRITE,
DDR_FORCE_LOW_PRI_N,
DDR_LPR_XACT_RUN_LENGTH,
DDR_LPR_MAX_STARVE,
DDR_W_XACT_RUN_LENGTH,
DDR_W_MAX_STARVE,
DDR_DQ_NIBBLE_MAP_12_15,
DDR_DQ_NIBBLE_MAP_8_11,
DDR_DQ_NIBBLE_MAP_4_7,
DDR_DQ_NIBBLE_MAP_0_3,
DDR_DQ_NIBBLE_MAP_28_31,
DDR_DQ_NIBBLE_MAP_24_27,
DDR_DQ_NIBBLE_MAP_20_23,
DDR_DQ_NIBBLE_MAP_16_19,
DDR_DQ_NIBBLE_MAP_44_47,
DDR_DQ_NIBBLE_MAP_40_43,
DDR_DQ_NIBBLE_MAP_36_39,
DDR_DQ_NIBBLE_MAP_32_35,
DDR_DQ_NIBBLE_MAP_60_63,
DDR_DQ_NIBBLE_MAP_56_59,
DDR_DQ_NIBBLE_MAP_52_55,
DDR_DQ_NIBBLE_MAP_48_51,
DDR_DQ_NIBBLE_MAP_CB_4_7,
DDR_DQ_NIBBLE_MAP_CB_0_3,
DDR_DIS_DQ_RANK_SWAP,
DDR_DIS_COLLISION_PAGE_OPT,
DDR_DIS_WC,
DDR_HW_REF_ZQ_EN,
DDR_CTRLUPD,
DDR_ZQ_CALIB_SHORT,
DDR_RANK1_REFRESH,
DDR_RANK0_REFRESH,
DDR_SW_DONE,
DDR_BL_EXP_MODE,
DDR_PAGEMATCH_LIMIT,
DDR_GO2CRITICAL_EN,
DDR_RD_PORT_PAGEMATCH_EN,
DDR_RD_PORT_URGENT_EN,
DDR_RD_PORT_AGING_EN,
DDR_RD_PORT_PRIORITY,
DDR_WR_PORT_PAGEMATCH_EN,
DDR_WR_PORT_URGENT_EN,
DDR_WR_PORT_AGING_EN,
DDR_WR_PORT_PRIORITY,
DDR_PORT_EN,
DDR_RQOS_MAP_TIMEOUTR,
DDR_RQOS_MAP_TIMEOUTB,
DDR_RQOS_MAP_REGION2,
DDR_RQOS_MAP_REGION1,
DDR_RQOS_MAP_REGION0,
DDR_RQOS_MAP_LEVEL2,
DDR_RQOS_MAP_LEVEL1,
DDR_RQOS_MAP_LEVEL11,
DDR_WQOS_MAP_REGION1,
DDR_WQOS_MAP_REGION0,
DDR_WQOS_MAP_LEVEL,
DDR_WQOS_MAP_TIMEOUT,
DDR_BASE_ADDR,
DDR_NBLOCKS
};
/* PHY Register fields */
enum {
PHY_ADCP,
PHY_RESERVED_30_27,
PHY_PHYFRST1,
PHY_OSCACDL,
PHY_RESERVED_23_19,
PHY_DTOSEL,
PHY_OSCDIV1,
PHY_OSCEN1,
PHY_CLRTSTAT,
PHY_CLRZCAL,
PHY_CLRPERR,
PHY_ICPC,
PHY_DTPMXTMR,
PHY_INITFSMBYP,
PHY_PLLFSMBYP,
PHY_TREFPRD,
PHY_CKNEN,
PHY_CKEN,
PHY_GATEACRDCLK,
PHY_GATEACDDRCLK,
PHY_GATEACCTLCLK,
PHY_DDLBYPMODE,
PHY_IOLB0,
PHY_RDMODE0,
PHY_DISRST0,
PHY_CLKLEVEL0,
PHY_FRQBT,
PHY_FRQAT,
PHY_DISCNPERIOD,
PHY_VREF_RBCTRL,
PHY_DXREFISELRANGE,
PHY_DDLPGACT,
PHY_DDLPGRW,
PHY_TPLLPD,
PHY_TPLLGS,
PHY_TPHYRST,
PHY_TPLLLOCK,
PHY_TPLLRST,
PHY_PLLBYP,
PHY_PLLRST,
PHY_PLLPD,
PHY_RSTOPM,
PHY_FRQSEL,
PHY_RLOCKM,
PHY_CPPC,
PHY_CPIC,
PHY_GSHIFT,
PHY_ATOEN,
PHY_ATC,
PHY_DTC,
PHY_RDBICLSEL,
PHY_RDBICL,
PHY_PHYZUEN,
PHY_RSTOE,
PHY_SDRMODE,
PHY_ATOAE,
PHY_DTOOE,
PHY_DTOIOM,
PHY_DTOPDR,
PHY_DTOODT,
PHY_PUAD,
PHY_CUAEN,
PHY_CTLZUEN,
PHY_RESERVED_1,
PHY_PUREN,
PHY_0_GPR0,
PHY_GPR1,
PHY_GEARDN,
PHY_UBG,
PHY_UDIMM,
PHY_DDR2T,
PHY_NOSRA,
PHY_BYTEMASK,
PHY_DDRTYPE,
PHY_MPRDQ,
PHY_PDQ,
PHY_DDR8BNK,
PHY_DDRMD,
PHY_TRRD,
PHY_TRAS,
PHY_TRP,
PHY_TRTP,
PHY_TWLMRD,
PHY_TFAW,
PHY_TMOD,
PHY_TMRD,
PHY_TRTW,
PHY_TRTODT,
PHY_TCKE,
PHY_TXS,
PHY_TOFDX,
PHY_TCCD,
PHY_TDLLK,
PHY_TDQSCKMAX,
PHY_TDQSCK,
PHY_TAOND_TAOFD,
PHY_TRFC,
PHY_TWLO,
PHY_TXP,
PHY_TRC,
PHY_TRCD,
PHY_TWTR,
PHY_PUBWLEN,
PHY_PUBRLEN,
PHY_PUBWL,
PHY_PUBRL,
PHY_QCSEN,
PHY_RDIMMIOM,
PHY_ERROUTOE,
PHY_ERROUTIOM,
PHY_ERROUTPDR,
PHY_ERROUTODT,
PHY_LRDIMM,
PHY_PARINIOM,
PHY_RNKMRREN,
PHY_SOPERR,
PHY_ERRNOREG,
PHY_RDIMM,
PHY_A17BID,
PHY_TBCMRD_L2,
PHY_TBCMRD_L,
PHY_TBCMRD,
PHY_TBCSTAB,
PHY_RC7,
PHY_RC6,
PHY_RC5,
PHY_RC4,
PHY_RC3,
PHY_RC2,
PHY_RC1,
PHY_RC0,
PHY_RC15,
PHY_RC14,
PHY_RC13,
PHY_RC12,
PHY_RC11,
PHY_RC10,
PHY_RC9,
PHY_RC8,
PHY_RSVD_6_5,
PHY_RSVD_2_0,
PHY_RDPST,
PHY_NWR,
PHY_RDPRE,
PHY_WRPRE,
PHY_BL,
PHY_WRLEV,
PHY_WLS,
PHY_WL0,
PHY_RL,
PHY_DBIWR,
PHY_DBIRD,
PHY_PDDS,
PHY_RSVD,
PHY_WRPST,
PHY_PUCAL,
PHY_RSVD_15_13,
PHY_WRP,
PHY_RDP,
PHY_RPTM,
PHY_SRA,
PHY_CS2CMDL,
PHY_IVM,
PHY_TCRM,
PHY_TCRR,
PHY_MPDM,
PHY_RSVD_0,
PHY_RDBI0,
PHY_WDBI0,
PHY_DM,
PHY_CAPPE,
PHY_RTTPARK,
PHY_ODTIBPD,
PHY_CAPES,
PHY_CRCEC,
PHY_CAPM,
PHY_TCCDL,
PHY_RSVD_9_8,
PHY_VDDQTEN,
PHY_VDQTRG,
PHY_VDQTVAL,
PHY_RSVD_7,
PHY_CAODT,
PHY_RSVD_3,
PHY_DQODT,
PHY_VREFCA_RANGE,
PHY_VREFCA,
PHY_FSPOP,
PHY_FSPWR,
PHY_DMD,
PHY_RRO,
PHY_VRCG,
PHY_VRO,
PHY_RPT,
PHY_CBT,
PHY_VREFDQ_RANGE,
PHY_VREFDQ,
PHY_ODTD_CA,
PHY_ODTE_CS,
PHY_ODTE_CK,
PHY_CODT,
PHY_RFSHDT,
PHY_DTDRS,
PHY_DTEXG,
PHY_DTEXD,
PHY_DTDSTP,
PHY_DTDEN,
PHY_DTDBS,
PHY_DTRDBITR,
PHY_DTWBDDM,
PHY_RFSHENT,
PHY_DTCMPD,
PHY_DTMPR,
PHY_DTRPTN,
PHY_RANKEN,
PHY_DTRANK,
PHY_RDLVLGDIFF,
PHY_RDLVLGS,
PHY_RDPRMVL_TRN,
PHY_RDLVLEN,
PHY_BSTEN,
PHY_CACD,
PHY_CAADR,
PHY_CA1BYTE1,
PHY_CA1BYTE0,
PHY_DFTDLY,
PHY_DFTZQUP,
PHY_DFTDDLUP,
PHY_DFTRDSPC,
PHY_DFTB2BRD,
PHY_DFTIDLRD,
PHY_RESERVED_11_8,
PHY_DFTGPULSE,
PHY_DFTUPMODE,
PHY_DFTDTMODE,
PHY_DFTDTEN,
PHY_SEED,
PHY_RESERVED_31_16,
PHY_ODTOEMODE,
PHY_ACSR,
PHY_RSTIOM,
PHY_RSTPDR,
PHY_RSTODT,
PHY_CKDCC,
PHY_ACPDRMODE,
PHY_ACODTMODE,
PHY_ACRANKCLKSEL,
PHY_CLKGENCLKGATE,
PHY_ACOECLKGATE0,
PHY_ACPDRCLKGATE0,
PHY_ACTECLKGATE0,
PHY_CKNCLKGATE0,
PHY_CKCLKGATE0,
PHY_ACCLKGATE0,
PHY_PAROEMODE,
PHY_BGOEMODE,
PHY_BAOEMODE,
PHY_A17OEMODE,
PHY_A16OEMODE,
PHY_ACTOEMODE,
PHY_CKOEMODE,
PHY_LBCLKGATE,
PHY_ACOECLKGATE1,
PHY_ACPDRCLKGATE1,
PHY_ACTECLKGATE1,
PHY_CKNCLKGATE1,
PHY_CKCLKGATE1,
PHY_ACCLKGATE1,
PHY_ACREFIOM,
PHY_ACREFPEN,
PHY_ACREFEEN,
PHY_ACREFSEN,
PHY_ACREFIEN,
PHY_ACREFESELRANGE,
PHY_ACREFESEL,
PHY_ACREFSSELRANGE,
PHY_ACREFSSEL,
PHY_ACVREFISELRANGE,
PHY_ACVREFISEL,
PHY_TVREF,
PHY_DVEN,
PHY_PDAEN,
PHY_VWCR,
PHY_DVSS,
PHY_DVMAX,
PHY_DVMIN,
PHY_DVINIT,
PHY_HVSS,
PHY_HVMAX,
PHY_HVMIN,
PHY_SHRNK,
PHY_SHREN,
PHY_TVREFIO,
PHY_EOFF,
PHY_ENUM,
PHY_HVEN,
PHY_HVIO,
PHY_PARBD,
PHY_A16BD,
PHY_A17BD,
PHY_ACTBD,
PHY_BG1BD,
PHY_BG0BD,
PHY_BA1BD,
PHY_BA0BD,
PHY_A03BD,
PHY_A02BD,
PHY_A01BD,
PHY_A00BD,
PHY_A07BD,
PHY_A06BD,
PHY_A05BD,
PHY_A04BD,
PHY_A11BD,
PHY_A10BD,
PHY_A09BD,
PHY_A08BD,
PHY_A15BD,
PHY_A14BD,
PHY_A13BD,
PHY_A12BD,
PHY_ZQREFISELRANGE,
PHY_PGWAIT_FRQB,
PHY_PGWAIT_FRQA,
PHY_ZQREFPEN,
PHY_ZQREFIEN,
PHY_ODT_MODE,
PHY_FORCE_ZCAL_VT_UPDATE,
PHY_IODLMT,
PHY_AVGEN,
PHY_AVGMAX,
PHY_ZCALT,
PHY_PD_DRV_ZDEN,
PHY_PU_DRV_ZDEN,
PHY_PD_ODT_ZDEN,
PHY_PU_ODT_ZDEN,
PHY_ZSEGBYP,
PHY_ZLE_MODE,
PHY_ODT_ADJUST,
PHY_PD_DRV_ADJUST,
PHY_PU_DRV_ADJUST,
PHY_ZPROG_DRAM_ODT,
PHY_ZPROG_HOST_ODT,
PHY_ZPROG_ASYM_DRV_PD,
PHY_ZPROG_ASYM_DRV_PU,
PHY_CALBYP,
PHY_MDLEN,
PHY_CODTSHFT,
PHY_DQSDCC,
PHY_RDDLY,
PHY_DQSNSEPDR,
PHY_DQSSEPDR,
PHY_RTTOAL,
PHY_RTTOH,
PHY_CPDRSHFT,
PHY_DQSRPD,
PHY_DQSGPDR,
PHY_DQSGODT,
PHY_DQSGOE,
PHY_DXPDRMODE,
PHY_QSNSEL,
PHY_QSSEL,
PHY_OEEN,
PHY_PDREN,
PHY_TEEN,
PHY_DSEN,
PHY_DMEN,
PHY_DQEN,
PHY_RDBVT,
PHY_WDBVT,
PHY_RGLVT,
PHY_RDLVT,
PHY_WDLVT,
PHY_WLLVT,
PHY_DSNOEMODE,
PHY_DSNTEMODE,
PHY_DSNPDRMODE,
PHY_DMOEMODE,
PHY_DMTEMODE,
PHY_DMPDRMODE,
PHY_DSOEMODE,
PHY_DSTEMODE,
PHY_DSPDRMODE,
PHY_DXREFIOM,
PHY_DXREFPEN,
PHY_DXREFEEN,
PHY_DXREFSEN,
PHY_DXREFESELRANGE,
PHY_DXREFESEL,
PHY_DXREFSSELRANGE,
PHY_DXREFSSEL,
PHY_DXREFIEN,
PHY_DXREFIMON,
PHY_DXREFISELR3,
PHY_DXREFISELR2,
PHY_DXREFISELR1,
PHY_DXREFISELR0,
PHY_DXDQVREFR3,
PHY_DXDQVREFR2,
PHY_DXDQVREFR1,
PHY_DXDQVREFR0,
PHY_DXOEMODE,
PHY_DXTEMODE,
PHY_GATEDXRDCLK,
PHY_GATEDXDDRCLK,
PHY_GATEDXCTLCLK,
PHY_CLKLEVEL,
PHY_LBMODE,
PHY_LBGSDQS,
PHY_LBDGDQS,
PHY_LBDQSS,
PHY_PHYHRST,
PHY_PHYFRST,
PHY_DLTST,
PHY_DLTMODE,
PHY_RESERVED_12_11,
PHY_OSCWDDL,
PHY_RESERVED_8_7,
PHY_OSCWDL,
PHY_OSCDIV,
PHY_OSCEN,
PHY_RRRMODE,
PHY_WRRMODE,
PHY_DQSGX,
PHY_LPPLLPD,
PHY_LPIOPD,
PHY_QSCNTEN,
PHY_UDQIOM,
PHY_DXSR,
PHY_DQSNRES,
PHY_DQSRES,
PHY_CRDEN,
PHY_POSOEX,
PHY_PREOEX,
PHY_IOAG,
PHY_IOLB,
PHY_LPWAKEUP_THRSH,
PHY_RDBI,
PHY_WDBI,
PHY_PRFBYP,
PHY_RDMODE,
PHY_DISRST,
PHY_DQSGLB,
PHY_DXDACRANGE,
PHY_DXVREFIOM,
PHY_DXIOM,
PHY_DXTXM,
PHY_DXRXM,
PHY_ZCALBYP,
PHY_DCALPSE,
PHY_DQS2DQ,
PHY_RDIMMINIT,
PHY_CTLDINIT,
PHY_VREF,
PHY_SRD,
PHY_WREYE,
PHY_RDEYE,
PHY_WRDSKW,
PHY_RDDSKW,
PHY_WLADJ,
PHY_QSGATE,
PHY_WL,
PHY_DRAMINIT,
PHY_DRAMRST,
PHY_PHYRST,
PHY_DCAL,
PHY_PLLINIT,
PHY_CA,
PHY_ZCAL,
PHY_INIT,
PHY_R060,
PHY_R061,
PHY_R062,
PHY_R063,
PHY_R064,
PHY_R065,
PHY_R066
};
/************************** Variable Definitions *****************************/
struct Ddr3SpdEeprom {
/* General Section: Bytes 0U-59U */
u8 InfoSizeCrc; /* 0U # bytes written into serial memory,
CRC coverage */
u8 SpdRev; /* 1U Total # bytes of SPD mem device */
u8 MemType; /* 2U Key Byte / Fundamental mem type */
u8 ModuleType; /* 3U Key Byte / Module Type */
u8 DensityBanks; /* 4U SDRAM Density and Banks */
u8 Addressing; /* 5U SDRAM Addressing */
u8 ModuleVdd; /* 6U Module nominal voltage, VDD */
u8 Organization; /* 7U Module Organization */
u8 BusWidth; /* 8U Module Memory Bus Width */
u8 FtbDiv; /* 9U Fine Timebase (FTB)
Dividend / Divisor */
u8 MtbDividend; /* 10U Medium Timebase (MTB) Dividend */
u8 MtbDivisor; /* 11U Medium Timebase (MTB) Divisor */
u8 TckMin; /* 12U SDRAM Minimum Cycle Time */
u8 Res13; /* 13U Reserved */
u8 CaslatLsb; /* 14U CAS Latencies Supported,
Least Significant Byte */
u8 CaslatMsb; /* 15U CAS Latencies Supported,
Most Significant Byte */
u8 TaaMin; /* 16U Min CAS Latency Time */
u8 TwrMin; /* 17U Min Write REcovery Time */
u8 TrcdMin; /* 18U Min RAS# to CAS# Delay Time */
u8 TrrdMin; /* 19U Min Row Active to
Row Active Delay Time */
u8 TrpMin; /* 20U Min Row Precharge Delay Time */
u8 TrasTrcExt; /* 21U Upper Nibbles for tRAS and tRC */
u8 TrasMinLsb; /* 22U Min Active to Precharge
Delay Time */
u8 TrcMinLsb; /* 23U Min Active to Active/Refresh
Delay Time, LSB */
u8 TrfcMinLsb; /* 24U Min Refresh Recovery Delay Time */
u8 TrfcMinMsb; /* 25U Min Refresh Recovery Delay Time */
u8 TwtrMin; /* 26U Min Internal Write to
Read Command Delay Time */
u8 TrtpMin; /* 27U Min Internal Read to Precharge
Command Delay Time */
u8 TfawMsb; /* 28U Upper Nibble for tFAW */
u8 TfawMin; /* 29U Min Four Activate Window
Delay Time*/
u8 OptFeatures; /* 30U SDRAM Optional Features */
u8 ThermRefOpt; /* 31U SDRAM Thermal and Refresh Opts */
u8 ThermSensor; /* 32U Module Thermal Sensor */
u8 DeviceType; /* 33U SDRAM device type */
s8 FineTckMin; /* 34U Fine offset for tCKmin */
s8 FineTaaMin; /* 35U Fine offset for tAAmin */
s8 FineTrcdMin; /* 36U Fine offset for tRCDmin */
s8 FineTrpMin; /* 37U Fine offset for tRPmin */
s8 FineTrcMin; /* 38U Fine offset for tRCmin */
u8 Res3959[21U]; /* 39U-59U Reserved, General Section */
/* Module-Specific Section: Bytes 60U-116U */
union {
struct {
/* 60U (Unbuffered) Module Nominal Height */
u8 ModHeight;
/* 61U (Unbuffered) Module Maximum Thickness */
u8 ModThickness;
/* 62U (Unbuffered) Reference Raw Card Used */
u8 RefRawCard;
/* 63U (Unbuffered) Address Mapping from
Edge Connector to DRAM */
u8 AddrMapping;
/* 64U-116U (Unbuffered) Reserved */
u8 Res64116[53U];
} unbuffered;
struct {
/* 60U (Registered) Module Nominal Height */
u8 ModHeight;
/* 61U (Registered) Module Maximum Thickness */
u8 ModThickness;
/* 62U (Registered) Reference Raw Card Used */
u8 RefRawCard;
/* 63U DIMM Module Attributes */
u8 ModuAttr;
/* 64U RDIMM Thermal Heat Spreader Solution */
u8 Thermal;
/* 65U Register Manufacturer ID Code, Least Significant Byte */
u8 RegIdLo;
/* 66U Register Manufacturer ID Code, Most Significant Byte */
u8 RegIdHi;
/* 67U Register Revision Number */
u8 RegRev;
/* 68U Register Type */
u8 RegType;
/* 69U-76U RC1,3U,5...15 (MS Nibble) / RC0,2U,4...14 (LS Nibble) */
u8 Rcw[8U];
} registered;
u8 Uc[57U]; /* 60U-116U Module-Specific Section */
} ModSection;
/* Unique Module ID: Bytes 117U-125U */
u8 MmidLsb; /* 117U Module MfgID Code LSB - JEP-106U */
u8 MmidMsb; /* 118U Module MfgID Code MSB - JEP-106U */
u8 Mloc; /* 119U Mfg Location */
u8 Mdate[2U]; /* 120U-121U Mfg Date */
u8 Sernum[4U]; /* 122U-125U Module Serial Number */
/* CRC: Bytes 126U-127U */
u8 Crc[2U]; /* 126U-127U SPD CRC */
/* Other Manufacturer Fields and User Space: Bytes 128U-255U */
u8 Mpart[18U]; /* 128U-145U Mfg's Module Part Number */
u8 Mrev[2U]; /* 146U-147U Module Revision Code */
u8 DmidLsb; /* 148U DRAM MfgID Code LSB - JEP-106U */
u8 DmidMsb; /* 149U DRAM MfgID Code MSB - JEP-106U */
u8 Msd[26U]; /* 150U-175U Mfg's Specific Data */
u8 Cust[80U]; /* 176U-255U Open for Customer Use */
};
/* From JEEC Standard No. 21U-C release 23A */
struct Ddr4SpdEeprom {
/* General Section: Bytes 0U-127U */
u8 InfoSizeCrc; /* 0U # bytes */
u8 SpdRev; /* 1U Total # bytes of SPD */
u8 MemType; /* 2U Key Byte / mem type */
u8 ModuleType; /* 3U Key Byte / Module Type */
u8 DensityBanks; /* 4U Density and Banks */
u8 Addressing; /* 5U Addressing */
u8 PackageType; /* 6U Package type */
u8 OptFeature; /* 7U Optional features */
u8 ThermalRef; /* 8U Thermal and refresh */
u8 OthOptFeatures; /* 9U Other optional features */
u8 Res10; /* 10U Reserved */
u8 ModuleVdd; /* 11U Module nominal voltage */
u8 Organization; /* 12U Module Organization */
u8 BusWidth; /* 13U Module Memory Bus Width */
u8 ThermSensor; /* 14U Module Thermal Sensor */
u8 ExtType; /* 15U Extended module type */
u8 Res16;
u8 Timebases; /* 17U MTb and FTB */
u8 TckMin; /* 18U tCKAVGmin */
u8 TckMax; /* 19U TCKAVGmax */
u8 CaslatB1; /* 20U CAS latencies, 1st byte */
u8 CaslatB2; /* 21U CAS latencies, 2nd byte */
u8 CaslatB3; /* 22U CAS latencies, 3rd byte */
u8 CaslatB4; /* 23U CAS latencies, 4th byte */
u8 TaaMin; /* 24U Min CAS Latency Time */
u8 TrcdMin; /* 25U Min RAS# to CAS# Delay Time */
u8 TrpMin; /* 26U Min Row Precharge Delay Time */
u8 TrasTrcExt; /* 27U Upper Nibbles for tRAS and tRC */
u8 TrasMinLsb; /* 28U tRASmin, lsb */
u8 TrcMinLsb; /* 29U tRCmin, lsb */
u8 Trfc1MinLsb; /* 30U Min Refresh Recovery Delay Time */
u8 Trfc1MinMsb; /* 31U Min Refresh Recovery Delay Time */
u8 Trfc2MinLsb; /* 32U Min Refresh Recovery Delay Time */
u8 Trfc2MinMsb; /* 33U Min Refresh Recovery Delay Time */
u8 Trfc4MinLsb; /* 34U Min Refresh Recovery Delay Time */
u8 Trfc4MinMsb; /* 35U Min Refresh Recovery Delay Time */
u8 TfawMsb; /* 36U Upper Nibble for tFAW */
u8 TfawMin; /* 37U tFAW, lsb */
u8 TrrdsMin; /* 38U tRRD_Smin, MTB */
u8 TrrdlMin; /* 39U tRRD_Lmin, MTB */
u8 TccdlMin; /* 40U tCCS_Lmin, MTB */
u8 Res41[60U-41U]; /* 41U Rserved */
u8 Mapping[78U-60U]; /* 60U~77U Connector to SDRAM bit map */
u8 Res78[117U-78U]; /* 78U~116U, Reserved */
s8 FineTccdlMin; /* 117U Fine offset for tCCD_Lmin */
s8 FineTrrdlMin; /* 118U Fine offset for tRRD_Lmin */
s8 FineTrrdsMin; /* 119U Fine offset for tRRD_Smin */
s8 FineTrcMin; /* 120U Fine offset for tRCmin */
s8 FineTrpMin; /* 121U Fine offset for tRPmin */
s8 FineTrcdMin; /* 122U Fine offset for tRCDmin */
s8 FineTaaMin; /* 123U Fine offset for tAAmin */
s8 FineTckMax; /* 124U Fine offset for tCKAVGmax */
s8 FineTckMin; /* 125U Fine offset for tCKAVGmin */
/* CRC: Bytes 126U-127U */
u8 Crc[2U]; /* 126U-127U SPD CRC */
/* Module-Specific Section: Bytes 128U-255U */
union {
struct {
/* 128U (Unbuffered) Module Nominal Height */
u8 ModHeight;
/* 129U (Unbuffered) Module Maximum Thickness */
u8 ModThickness;
/* 130U (Unbuffered) Reference Raw Card Used */
u8 RefRawCard;
/* 131U (Unbuffered) Address Mapping from
Edge Connector to DRAM */
u8 AddrMapping;
/* 132U~253U (Unbuffered) Reserved */
u8 Res132[254U-132U];
/* 254U~255U CRC */
u8 Crc[2U];
} unbuffered;
struct {
/* 128U (Registered) Module Nominal Height */
u8 ModHeight;
/* 129U (Registered) Module Maximum Thickness */
u8 ModThickness;
/* 130U (Registered) Reference Raw Card Used */
u8 RefRawCard;
/* 131U DIMM Module Attributes */
u8 ModuAttr;
/* 132U RDIMM Thermal Heat Spreader Solution */
u8 Thermal;
/* 133U Register Manufacturer ID Code, LSB */
u8 RegIdLo;
/* 134U Register Manufacturer ID Code, MSB */
u8 RegIdHi;
/* 135U Register Revision Number */
u8 RegRev;
/* 136U Address mapping from register to DRAM */
u8 RegMap;
/* 137U~253U Reserved */
u8 Res137[254U-137U];
/* 254U~255U CRC */
u8 Crc[2U];
} registered;
struct {
/* 128U (Loadreduced) Module Nominal Height */
u8 ModHeight;
/* 129U (Loadreduced) Module Maximum Thickness */
u8 ModThickness;
/* 130U (Loadreduced) Reference Raw Card Used */
u8 RefRawCard;
/* 131U DIMM Module Attributes */
u8 ModuAttr;
/* 132U RDIMM Thermal Heat Spreader Solution */
u8 Thermal;
/* 133U Register Manufacturer ID Code, LSB */
u8 RegIdLo;
/* 134U Register Manufacturer ID Code, MSB */
u8 RegIdHi;
/* 135U Register Revision Number */
u8 RegRev;
/* 136U Address mapping from register to DRAM */
u8 RegMap;
/* 137U Register Output Drive Strength for CMD/Add*/
u8 RegDrv;
/* 138U Register Output Drive Strength for CK */
u8 RegDrvCk;
/* 139U Data Buffer Revision Number */
u8 DataBufRev;
/* 140U DRAM VrefDQ for Package Rank 0U */
u8 VrefqeR0;
/* 141U DRAM VrefDQ for Package Rank 1U */
u8 VrefqeR1;
/* 142U DRAM VrefDQ for Package Rank 2U */
u8 VrefqeR2;
/* 143U DRAM VrefDQ for Package Rank 3U */
u8 VrefqeR3;
/* 144U Data Buffer VrefDQ for DRAM Interface */
u8 DataIntf;
/*
* 145U Data Buffer MDQ Drive Strength and RTT
* for data rate <= 1866U
*/
u8 DataDrv1866;
/*
* 146U Data Buffer MDQ Drive Strength and RTT
* for 1866U < data rate <= 2400U
*/
u8 DataDrv2400;
/*
* 147U Data Buffer MDQ Drive Strength and RTT
* for 2400U < data rate <= 3200U
*/
u8 DataDrv3200;
/* 148U DRAM Drive Strength */
u8 DramDrv;
/*
* 149U DRAM ODT (RTT_WR, RTT_NOM)
* for data rate <= 1866U
*/
u8 DramOdt1866;
/*
* 150U DRAM ODT (RTT_WR, RTT_NOM)
* for 1866U < data rate <= 2400U
*/
u8 DramOdt2400;
/*
* 151U DRAM ODT (RTT_WR, RTT_NOM)
* for 2400U < data rate <= 3200U
*/
u8 DramOdt3200;
/*
* 152U DRAM ODT (RTT_PARK)
* for data rate <= 1866U
*/
u8 DramOdtPark1866;
/*
* 153U DRAM ODT (RTT_PARK)
* for 1866U < data rate <= 2400U
*/
u8 DramOdtPark2400;
/*
* 154U DRAM ODT (RTT_PARK)
* for 2400U < data rate <= 3200U
*/
u8 DramOdtPark3200;
u8 Res155[254U-155U]; /* Reserved */
/* 254U~255U CRC */
u8 Crc[2U];
} LoadReduced;
u8 Uc[128U]; /* 128U-255U Module-Specific Section */
} ModSection;
u8 Res256[320U-256U]; /* 256U~319U Reserved */
/* Module supplier's data: Byte 320U~383U */
u8 MmidLsb; /* 320U Module MfgID Code LSB */
u8 MmidMsb; /* 321U Module MfgID Code MSB */
u8 Mloc; /* 322U Mfg Location */
u8 Mdate[2U]; /* 323U~324U Mfg Date */
u8 Sernum[4U]; /* 325U~328U Module Serial Number */
u8 Mpart[20U]; /* 329U~348U Mfg's Module Part Number */
u8 Mrev; /* 349U Module Revision Code */
u8 DmidLsb; /* 350U DRAM MfgID Code LSB */
u8 DmidMsb; /* 351U DRAM MfgID Code MSB */
u8 Stepping; /* 352U DRAM stepping */
u8 Msd[29U]; /* 353U~381U Mfg's Specific Data */
u8 Res382[2U]; /* 382U~383U Reserved */
u8 User[512U-384U]; /* 384U~511U End User Programmable */
};
/* From JEEC Standard No. 21U-C release 23A */
struct LpDdrSpdEeprom {
/* General Section: Bytes 0U-127U */
u8 InfoSizeCrc; /* 0U # bytes */
u8 SpdRev; /* 1U Total # bytes of SPD */
u8 MemType; /* 2U Key Byte / mem type */
u8 ModuleType; /* 3U Key Byte / Module Type */
u8 DensityBanks; /* 4U Density and Banks */
u8 Addressing; /* 5U Addressing */
u8 PackageType; /* 6U Package type */
u8 OptFeature; /* 7U Optional features */
u8 ThermalRef; /* 8U Thermal and refresh */
u8 OthOptFeatures; /* 9U Other optional features */
u8 Res10; /* 10U Reserved */
u8 ModuleVdd; /* 11U Module nominal voltage */
u8 Organization; /* 12U Module Organization */
u8 BusWidth; /* 13U Module Memory Bus Width */
u8 ThermSensor; /* 14U Module Thermal Sensor */
u8 ExtType; /* 15U Extended module type */
u8 SignalLoading; /* 16U Signal Loading */
u8 Timebases; /* 17U MTb and FTB */
u8 TckMin; /* 18U tCKAVGmin */
u8 TckMax; /* 19U TCKAVGmax */
u8 CaslatB1; /* 20U CAS latencies, 1st byte */
u8 CaslatB2; /* 21U CAS latencies, 2nd byte */
u8 CaslatB3; /* 22U CAS latencies, 3rd byte */
u8 CaslatB4; /* 23U CAS latencies, 4th byte */
u8 TaaMin; /* 24U Min CAS Latency Time */
u8 RdWrLatSet; /* 25U Read & Write Latency Set Options */
u8 TrcdMin; /* 26U Min RAS# to CAS# Delay Time */
u8 TrpabMin; /* 27U All banks Min Row Precharge Delay Time */
u8 TrppbMin; /* 28U Per bank Min Row Precharge Delay Time */
u8 TrfcabMinLsb; /* 29U All banks Min Refresh Recovery Delay Time */
u8 TrfcabMinMsb; /* 30U All banks Min Refresh Recovery Delay Time */
u8 TrfcpbMinLsb; /* 31U Per bank Min Refresh Recovery Delay Time */
u8 TrfcpbMinMsb; /* 32U Per bank Min Refresh Recovery Delay Time */
u8 Res33[60U-33U]; /* 33U Rserved */
u8 Mapping[78U-60U]; /* 60U~77U Connector to SDRAM bit map */
u8 Res78[120U-78U]; /* 78U~119U, Reserved */
s8 FineTrppbMin; /* 120U Fine offset for tRPpbmin */
s8 FineTrpabMin; /* 121U Fine offset for tRPabmin */
s8 FineTrcdMin; /* 122U Fine offset for tRCDmin */
s8 FineTaaMin; /* 123U Fine offset for tAAmin */
s8 FineTckMax; /* 124U Fine offset for tCKAVGmax */
s8 FineTckMin; /* 125U Fine offset for tCKAVGmin */
/* CRC: Bytes 126U-127U */
u8 Crc[2U]; /* 126U-127U SPD CRC */
/* Module-Specific Section: Bytes 128U-255U */
union {
struct {
/* 128U (Unbuffered) Module Nominal Height */
u8 ModHeight;
/* 129U (Unbuffered) Module Maximum Thickness */
u8 ModThickness;
/* 130U (Unbuffered) Reference Raw Card Used */
u8 RefRawCard;
/* 131U~253U (Unbuffered) Reserved */
u8 Res132[254U-131U];
/* 254U~255U CRC */
u8 Crc[2U];
} lpdimm;
u8 Uc[128U]; /* 128U-255U Module-Specific Section */
} ModSection;
u8 Res256[320U-256U]; /* 256U~319U Reserved */
/* Module supplier's data: Byte 320U~383U */
u8 MmidLsb; /* 320U Module MfgID Code LSB */
u8 MmidMsb; /* 321U Module MfgID Code MSB */
u8 Mloc; /* 322U Mfg Location */
u8 Mdate[2U]; /* 323U~324U Mfg Date */
u8 Sernum[4U]; /* 325U~328U Module Serial Number */
u8 Mpart[20U]; /* 329U~348U Mfg's Module Part Number */
u8 Mrev; /* 349U Module Revision Code */
u8 DmidLsb; /* 350U DRAM MfgID Code LSB */
u8 DmidMsb; /* 351U DRAM MfgID Code MSB */
u8 Stepping; /* 352U DRAM stepping */
u8 Msd[29U]; /* 353U~381U Mfg's Specific Data */
u8 Res382[2U]; /* 382U~383U Reserved */
u8 User[512U-384U]; /* 384U~511U End User Programmable */
};
/* Parameters for a DDR dimm computed from the SPD */
typedef struct {
/* DIMM organization parameters */
s8 Mpart[19U]; /* guaranteed null terminated */
u32 MemType;
u32 NRanks;
u64 RankDensity;
u64 Capacity;
u32 BusWidth;
u32 PrimaryBusWidth;
u32 EccBusWidth;
u32 UDimm;
u32 RDimm;
u32 SpeedBin;
u32 DramWidth; /* x4, x8, x16 components */
/* SDRAM device parameters */
u32 NumRankAddr;
u32 NumRowAddr;
u32 NumColAddr;
u32 EdcConfig; /* 0U = none, 1U = parity, 2U = ECC */
u32 NumBankAddr;
u32 NumBgAddr;
u32 NBanksPerSdramDevice;
u32 BurstLength; /* BL=4U bit 2U, BL=8U = bit 3U */
u32 RowDensity;
/* used in computing base address of DIMMs */
u64 BaseAddress;
/* mirrored DIMMs */
u32 AddrMirror; /* only for ddr3 */
/* DIMM timing parameters */
u32 MtbPs; /* medium timebase ps */
u32 Ftb10thPs; /* fine timebase, in 1U/10U ps */
u32 TaaPs; /* minimum CAS latency time */
u32 TFawPs; /* four active window delay */
/*
* SDRAM clock periods
* The range for these are 1000U-10000U so a short should be sufficient
*/
u32 TckminXPs;
u32 TckminXMinus1Ps;
u32 TckminXMinus2Ps;
u32 TckmaxPs;
float ClockPeriod;
float FreqMhz;
/* SPD-defined CAS latencies */
u32 CaslatX;
u32 CaslatXMinus1;
u32 CaslatXMinus2;
u32 CaslatLowestDerated; /* Derated CAS latency */
u32 CasLatency;
u32 CasWriteLatency;
u32 AdditiveLatency;
u32 WriteLatency;
u32 ReadLatency;
/* basic timing parameters */
u32 TRcdPs;
u32 TRpPs;
u32 TrpabPs;
u32 TrppbPs;
u32 TRasPs;
u32 TRfc1Ps;
u32 TRfc2Ps;
u32 TRfc4Ps;
u32 TRfcAbPs;
u32 TRfcPbPs;
u32 TRrdsPs;
u32 TRrdlPs;
u32 TCcdlPs;
u32 TwrPs; /* maximum = 63750U ps */
u32 TRfcPs; /* max = 255U ns + 256U ns + .75 ns
= 511750U ps */
u32 TRrdPs; /* maximum = 63750U ps */
u32 TwtrPs; /* maximum = 63750U ps */
u32 TrtpPs; /* byte 38U, spd->trtp */
u32 TRcPs; /* maximum = 254U ns + .75 ns = 254750U ps */
u32 TRefi;
float TXp;
float TMod;
u32 TWtr;
u32 Vref;
u32 Ecc;
u32 TRefMode;
u32 TRefRange;
u32 RdDbi;
u32 WrDbi;
u32 PhyDbiMode;
u32 DataMask;
u32 EccScrub;
u32 EccPoison;
u32 Parity;
u32 ParityLatency;
u32 En2tTimingMode;
u32 Geardown;
u32 MaxPwrSavEn;
u32 CalModeEn;
u32 DeepPwrDnEn;
u32 PwrDnEn;
u32 Crc;
u32 WrPreamble;
u32 RdPreamble;
u32 RdPostamble;
u32 WrPostamble;
u32 Lpddr4Hynix;
u32 Lpddr4Samsung;
u32 Video;
u32 Decoder;
u32 TileWidth;
u32 TileHeight;
u32 PerBankRefresh;
u32 Fgrm;
u32 LpAsr;
u32 DisDfiLpSr;
u32 DisDfiLpPd;
u32 DisDfiLpMpsm;
u32 Ddr4AddrMapping;
u32 BrcMapping;
u32 PllByp;
u32 FreqB;
u32 StaticRdMode;
u32 SelfRefAbort;
u32 Gls;
u32 Slowboot;
u32 En2ndClk;
u32 Dp;
u32 HasEccComp;
u32 ClockStopEn;
u32 Zcu100;
u32 DdriobCtrl;
u32 WrDrift;
u32 RdDrift;
u32 GateExt;
u32 NoGateExtNoTrain;
u32 Preoex;
u32 DerateIntD;
u32 Zc1650;
u32 Zc1656;
u32 RdbiWrkAround;
u32 Lp4catrain;
u32 RdDqsCenter;
u32 NoDerate;
u32 HostOdt;
u32 HostDrv;
u32 DramOdt;
u32 DramDrv;
u32 DramCaOdt;
u32 DeskewTrn;
u32 DisOpInv;
u32 PhyClkGate;
u32 NoRetry;
u32 Lp4FmaxWrkAround;
u32 EnOpInvAfterTrain;
u32 Dqmap03;
u32 Dqmap47;
u32 Dqmap811;
u32 Dqmap1215;
u32 Dqmap1619;
u32 Dqmap2023;
u32 Dqmap2427;
u32 Dqmap2831;
u32 Dqmap3235;
u32 Dqmap3639;
u32 Dqmap4043;
u32 Dqmap4447;
u32 Dqmap4851;
u32 Dqmap5255;
u32 Dqmap5659;
u32 Dqmap6063;
u32 Dqmap6467;
u32 Dqmap6871;
u32 Ddp;
u32 LprNumEntries;
u32 PllRetry;
u32 UseSetB;
u32 Lp4NoOdt;
u32 Mr;
u32 Emr;
u32 Emr2;
u32 Emr3;
u32 Mr4;
u32 Mr5;
u32 Mr6;
u32 WdqsOn;
u32 WdqsOff;
u32 CtlClkFreq;
} XFsbl_DimmParams;
/* DDR Initialization Data Structure */
struct DdrcInitData {
u32 AddrMapRowBit[XFSBL_MAX_ROWS]; /* Row Bits in Address Map */
u32 AddrMapColBit[XFSBL_MAX_COLUMNS]; /* Column Bits in Address Map */
u32 AddrMapBankBit[XFSBL_MAX_BANKS]; /* Bank Bits in Address Map */
u32 AddrMapBgBit[XFSBL_MAX_BANK_GROUPS]; /* BG Bits in Address Map */
u32 AddrMapCsBit0; /* Rank Bits in Address Map */
u32 AddrMapRowBits2To10; /* Row Bits (2U-10U) in Address Map */
XFsbl_DimmParams PDimm;
};
u32 XFsbl_DdrInit(void);
#endif /* XPAR_DYNAMIC_DDR_ENABLED */
#ifdef __cplusplus
}
#endif
#endif /* XFSBL_DDR_INIT_H */
#endif /* XFSBL_PS_DDR */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_platform.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPFW_PLATFORM_H_
#define XPFW_PLATFORM_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
#define XPFW_PLATFORM_PS_V1 0x0U
#define PBR_VERSION_REG 0xFFD07FCC
u8 XPfw_PlatformGetPsVersion(void);
void XPfw_PrintPBRVersion(u32 xpbr_version);
#ifdef __cplusplus
}
#endif
#endif /* XPFW_PLATFORM_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilsecure_v4_2/src/versal/xsecure_aes.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_aes.h
* @addtogroup xsecure_aes_versal_apis XilSecure AES VERSAL APIs
* @{
* @cond xsecure_internal
*
* This file contains AES hardware interface APIs
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -------------------------------------------------------
* 4.0 vns 04/24/2019 Initial release
* 4.1 vns 08/06/2019 Added AES encryption APIs
* 4.2 kpt 01/07/2020 Removed Macro XSECURE_WORD_SIZE
* and added in xsecure_utils.h
* vns 02/10/2020 Added DPA CM enable/disable function
* </pre>
*
* @note
* @endcond
*
******************************************************************************/
#ifndef XSECURE_AES_H_
#define XSECURE_AES_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xpmcdma.h"
#include "xsecure_sss.h"
/************************** Constant Definitions *****************************/
/** @cond xsecure_internal
@{
*/
#define XSECURE_AES_BUFFER_SIZE (4U)
#define XSECURE_AES_KEY_DEC_SEL_BBRAM_RED (0x0U)
#define XSECURE_AES_KEY_DEC_SEL_BH_RED (0x1U)
#define XSECURE_AES_KEY_DEC_SEL_EFUSE_RED (0x2U)
#define XSECURE_AES_KEY_DEC_SEL_EFUSE_USR0_RED (0x3U)
#define XSECURE_AES_KEY_DEC_SEL_EFUSE_USR1_RED (0x4U)
#define XSECURE_SECURE_GCM_TAG_SIZE (16U)
/**< GCM Tag Size in Bytes */
#define XSECURE_AES_KEY_SIZE_128BIT_WORDS (4U)
#define XSECURE_AES_KEY_SIZE_256BIT_WORDS (8U)
#define XSECURE_AES_TIMEOUT_MAX (0x1FFFFU)
#define XSECURE_AES_INVALID_CFG (0xFFFFFFFFU)
#define XSECURE_AES_NO_CFG_DST_DMA (0xFFFFFFFFU)
#define XSECURE_AES_KEY_MASK_INDEX (0xA0U)
#define XSECURE_AES_DMA_SIZE (16U)
#define XSECURE_AES_DMA_LAST_WORD_ENABLE (0x1U)
#define XSECURE_AES_DMA_LAST_WORD_DISABLE (0x0U)
/* Key select values */
#define XSECURE_AES_KEY_SEL_BBRAM_KEY (<KEY>)
#define XSECURE_AES_KEY_SEL_BBRAM_RD_KEY (<KEY>)
#define XSECURE_AES_KEY_SEL_BH_KEY (<KEY>)
#define XSECURE_AES_KEY_SEL_BH_RD_KEY (0<KEY>)
#define XSECURE_AES_KEY_SEL_EFUSE_KEY (0xEFDE6600)
#define XSECURE_AES_KEY_SEL_EFUSE_RED_KEY (0xEFDE8200)
#define XSECURE_AES_KEY_SEL_EFUSE_USR_KEY0 (0xEF856601)
#define XSECURE_AES_KEY_SEL_EFUSE_USR_KEY1 (0xEF856602)
#define XSECURE_AES_KEY_SEL_EFUSE_USR_RD_KEY0 (0xEF858201)
#define XSECURE_AES_KEY_SEL_EFUSE_USR_RD_KEY1 (0xEF858202)
#define XSECURE_AES_KEY_SEL_KUP_KEY (<KEY>)
#define XSECURE_AES_KEY_SEL_FAMILY_KEY (0xFEDE8200)
#define XSECURE_AES_KEY_SEL_PUF_KEY (<KEY>)
#define XSECURE_AES_KEY_SEL_USR_KEY_0 (<KEY>)
#define XSECURE_AES_KEY_SEL_USR_KEY_1 (<KEY>)
#define XSECURE_AES_KEY_SEL_USR_KEY_2 (<KEY>)
#define XSECURE_AES_KEY_SEL_USR_KEY_3 (<KEY>)
#define XSECURE_AES_KEY_SEL_USR_KEY_4 (<KEY>)
#define XSECURE_AES_KEY_SEL_USR_KEY_5 (<KEY>)
#define XSECURE_AES_KEY_SEL_USR_KEY_6 (<KEY>)
#define XSECURE_AES_KEY_SEL_USR_KEY_7 (<KEY>)
/** @}
@endcond */
/**************************** Type Definitions *******************************/
typedef enum {
XSECURE_BLACK_KEY,
XSECURE_OBFUSCATED_KEY
}XSecure_AesKekType;
typedef enum {
XSECURE_AES_BBRAM_KEY = 0,
XSECURE_AES_BBRAM_RED_KEY,
XSECURE_AES_BH_KEY,
XSECURE_AES_BH_RED_KEY,
XSECURE_AES_EFUSE_KEY,
XSECURE_AES_EFUSE_RED_KEY,
XSECURE_AES_EFUSE_USER_KEY_0,
XSECURE_AES_EFUSE_USER_KEY_1,
XSECURE_AES_EFUSE_USER_RED_KEY_0,
XSECURE_AES_EFUSE_USER_RED_KEY_1,
XSECURE_AES_KUP_KEY,
XSECURE_AES_FAMILY_KEY,
XSECURE_AES_PUF_KEY,
XSECURE_AES_USER_KEY_0,
XSECURE_AES_USER_KEY_1,
XSECURE_AES_USER_KEY_2,
XSECURE_AES_USER_KEY_3,
XSECURE_AES_USER_KEY_4,
XSECURE_AES_USER_KEY_5,
XSECURE_AES_USER_KEY_6,
XSECURE_AES_USER_KEY_7,
XSECURE_AES_EXPANDED_KEYS
} XSecure_AesKeySrc;
typedef enum {
XSECURE_AES_KEY_SIZE_128 = 0,
XSECURE_AES_KEY_SIZE_256 = 2,
}XSecure_AesKeySize;
/** @cond xsecure_internal
@{
*/
typedef enum {
XSECURE_AES_UNINITIALIZED,
XSECURE_AES_INITIALIZED,
XSECURE_AES_ENCRYPT_INITIALIZED,
XSECURE_AES_DECRYPT_INITIALIZED
} XSecure_AesState;
typedef struct {
u32 BaseAddress;
XPmcDma *PmcDmaPtr; /**< PMCDMA Instance Pointer */
XSecure_Sss SssInstance;
XSecure_AesState AesState; /**< Current Aes State */
XSecure_AesKeySrc KeySrc;
} XSecure_Aes;
/** @}
@endcond */
/************************** Function Prototypes ******************************/
u32 XSecure_AesInitialize(XSecure_Aes *InstancePtr, XPmcDma *PmcDmaPtr);
u32 XSecure_AesSetDpaCm(XSecure_Aes *InstancePtr, u32 Configuration);
u32 XSecure_AesKeyZero(XSecure_Aes *InstancePtr, XSecure_AesKeySrc KeySrc);
u32 XSecure_AesWriteKey(XSecure_Aes *InstancePtr, XSecure_AesKeySrc KeySrc,
XSecure_AesKeySize KeySize, u64 KeyAddr);
u32 XSecure_AesKekDecrypt(XSecure_Aes *InstancePtr, XSecure_AesKekType KeyType,
XSecure_AesKeySrc DecKeySrc, XSecure_AesKeySrc DstKeySrc,
u64 IvAddr, u32 KeySize);
u32 XSecure_AesCfgKupIv(XSecure_Aes *InstancePtr, u32 Config);
u32 XSecure_AesGetNxtBlkLen(XSecure_Aes *InstancePtr, u32 *Size);
u32 XSecure_AesDecryptInit(XSecure_Aes *InstancePtr, XSecure_AesKeySrc KeySrc,
XSecure_AesKeySize KeySize, u64 IvAddr);
u32 XSecure_AesDecryptUpdate(XSecure_Aes *InstancePtr, u64 InDataAddr,
u64 OutDataAddr, u32 Size, u8 IsLastChunk);
u32 XSecure_AesDecryptFinal(XSecure_Aes *InstancePtr, u64 GcmTagAddr);
u32 XSecure_AesDecryptData(XSecure_Aes *InstancePtr, u64 InDataAddr,
u64 OutDataAddr, u32 Size, u64 GcmTagAddr);
u32 XSecure_AesEncryptInit(XSecure_Aes *InstancePtr, XSecure_AesKeySrc KeySrc,
XSecure_AesKeySize KeySize, u64 IvAddr);
u32 XSecure_AesEncryptUpdate(XSecure_Aes *InstancePtr, u64 InDataAddr,
u64 OutDataAddr, u32 Size, u8 IsLastChunk);
u32 XSecure_AesEncryptFinal(XSecure_Aes *InstancePtr, u64 GcmTagAddr);
u32 XSecure_AesEncryptData(XSecure_Aes *InstancePtr, u64 InDataAddr,
u64 OutDataAddr, u32 Size, u64 GcmTagAddr);
u32 XSecure_AesDecryptKat(XSecure_Aes *InstancePtr);
u32 XSecure_AesDecryptCmKat(XSecure_Aes *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_AES_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/client/pm_api_sys.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/**
* @file pm_api_sys.c
*
* PM Definitions implementation
* @addtogroup xpm_versal_apis XilPM Versal APIs
* @{
*****************************************************************************/
#include "pm_api_sys.h"
#include "pm_callbacks.h"
#include "pm_client.h"
/* Payload Packets */
#define PACK_PAYLOAD(Payload, Arg0, Arg1, Arg2, Arg3, Arg4, Arg5) \
Payload[0] = (u32)Arg0; \
Payload[1] = (u32)Arg1; \
Payload[2] = (u32)Arg2; \
Payload[3] = (u32)Arg3; \
Payload[4] = (u32)Arg4; \
Payload[5] = (u32)Arg5; \
XPm_Dbg("%s(%x, %x, %x, %x, %x)\r\n", __func__, Arg1, Arg2, Arg3, Arg4, Arg5);
#define LIBPM_MODULE_ID (0x02UL)
#define HEADER(len, ApiId) ((len << 16U) | (LIBPM_MODULE_ID << 8U) | ((u32)ApiId))
#define PACK_PAYLOAD0(Payload, ApiId) \
PACK_PAYLOAD(Payload, HEADER(0UL, ApiId), 0, 0, 0, 0, 0)
#define PACK_PAYLOAD1(Payload, ApiId, Arg1) \
PACK_PAYLOAD(Payload, HEADER(1UL, ApiId), Arg1, 0, 0, 0, 0)
#define PACK_PAYLOAD2(Payload, ApiId, Arg1, Arg2) \
PACK_PAYLOAD(Payload, HEADER(2UL, ApiId), Arg1, Arg2, 0, 0, 0)
#define PACK_PAYLOAD3(Payload, ApiId, Arg1, Arg2, Arg3) \
PACK_PAYLOAD(Payload, HEADER(3UL, ApiId), Arg1, Arg2, Arg3, 0, 0)
#define PACK_PAYLOAD4(Payload, ApiId, Arg1, Arg2, Arg3, Arg4) \
PACK_PAYLOAD(Payload, HEADER(4UL, ApiId), Arg1, Arg2, Arg3, Arg4, 0)
#define PACK_PAYLOAD5(Payload, ApiId, Arg1, Arg2, Arg3, Arg4, Arg5) \
PACK_PAYLOAD(Payload, HEADER(5UL, ApiId), Arg1, Arg2, Arg3, Arg4, Arg5)
/****************************************************************************/
/**
* @brief Sends IPI request to the target module
*
* @param Proc Pointer to the processor who is initiating request
* @param Payload API id and call arguments to be written in IPI buffer
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
static XStatus XPm_IpiSend(struct XPm_Proc *const Proc, u32 *Payload)
{
XStatus Status = (s32)XST_FAILURE;
Status = XIpiPsu_PollForAck(Proc->Ipi, TARGET_IPI_INT_MASK,
PM_IPI_TIMEOUT);
if (Status != XST_SUCCESS) {
XPm_Dbg("%s: ERROR: Timeout expired\n", __func__);
goto done;
}
Status = XIpiPsu_WriteMessage(Proc->Ipi, TARGET_IPI_INT_MASK, Payload,
PAYLOAD_ARG_CNT, XIPIPSU_BUF_TYPE_MSG);
if (Status != XST_SUCCESS) {
XPm_Dbg("xilpm: ERROR writing to IPI request buffer\n");
goto done;
}
Status = XIpiPsu_TriggerIpi(Proc->Ipi, TARGET_IPI_INT_MASK);
done:
return Status;
}
/****************************************************************************/
/**
* @brief Reads IPI Response after target module has handled interrupt
*
* @param Proc Pointer to the processor who is waiting and reading Response
* @param Val1 Used to return value from 2nd IPI buffer element (optional)
* @param Val2 Used to return value from 3rd IPI buffer element (optional)
* @param Val3 Used to return value from 4th IPI buffer element (optional)
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
static XStatus Xpm_IpiReadBuff32(struct XPm_Proc *const Proc, u32 *Val1,
u32 *Val2, u32 *Val3)
{
u32 Response[RESPONSE_ARG_CNT];
XStatus Status = (s32)XST_FAILURE;
/* Wait until current IPI interrupt is handled by target module */
Status = XIpiPsu_PollForAck(Proc->Ipi, TARGET_IPI_INT_MASK,
PM_IPI_TIMEOUT);
if (XST_SUCCESS != Status) {
XPm_Dbg("%s: ERROR: Timeout expired\r\n", __func__);
goto done;
}
Status = XIpiPsu_ReadMessage(Proc->Ipi, TARGET_IPI_INT_MASK, Response,
RESPONSE_ARG_CNT, XIPIPSU_BUF_TYPE_RESP);
if (XST_SUCCESS != Status) {
XPm_Dbg("%s: ERROR: Reading from IPI Response buffer\r\n", __func__);
goto done;
}
/*
* Read Response from IPI buffer
* buf-0: success or error+reason
* buf-1: Val1
* buf-2: Val2
* buf-3: Val3
*/
if (NULL != Val1) {
*Val1 = Response[1];
}
if (NULL != Val2) {
*Val2 = Response[2];
}
if (NULL != Val3) {
*Val3 = Response[3];
}
Status = (s32)Response[0];
done:
return Status;
}
/****************************************************************************/
/**
* @brief Initialize xilpm library
*
* @param IpiInst Pointer to IPI driver instance
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
****************************************************************************/
XStatus XPm_InitXilpm(XIpiPsu *IpiInst)
{
XStatus Status = (s32)XST_FAILURE;
if (NULL == IpiInst) {
XPm_Dbg("ERROR passing NULL pointer to %s\r\n", __func__);
Status = (s32)XST_INVALID_PARAM;
goto done;
}
XPm_SetPrimaryProc();
PrimaryProc->Ipi = IpiInst;
Status = (s32)XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This Function returns information about the boot reason.
* If the boot is not a system startup but a resume,
* power down request bitfield for this processor will be cleared.
*
* @return Returns processor boot status
* - PM_RESUME : If the boot reason is because of system resume.
* - PM_INITIAL_BOOT : If this boot is the initial system startup.
*
*
*
****************************************************************************/
enum XPmBootStatus XPm_GetBootStatus(void)
{
u32 PwrDwnReq;
enum XPmBootStatus Ret;
XPm_SetPrimaryProc();
/* Error out if primary proc is not defined */
if (NULL == PrimaryProc) {
Ret = PM_BOOT_ERROR;
goto done;
}
PwrDwnReq = XPm_Read(PrimaryProc->PwrCtrl);
if (0U != (PwrDwnReq & PrimaryProc->PwrDwnMask)) {
PwrDwnReq &= ~PrimaryProc->PwrDwnMask;
XPm_Write(PrimaryProc->PwrCtrl, PwrDwnReq);
Ret = PM_RESUME;
goto done;
} else {
Ret = PM_INITIAL_BOOT;
goto done;
}
done:
return Ret;
}
/****************************************************************************/
/**
* @brief This function is used to request the version and ID code of a chip
*
* @param IDCode Returns the chip ID code.
* @param Version Returns the chip version.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_GetChipID(u32* IDCode, u32 *Version)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD0(Payload, PM_GET_CHIPID);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, IDCode, Version, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to request the version number of the API
* running on the platform management controller.
*
* @param version Returns the API 32-bit version number.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_GetApiVersion(u32 *Version)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD0(Payload, PM_GET_API_VERSION);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, Version, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to request the device
*
* @param DeviceId Device which needs to be requested
* @param Capabilities Device Capabilities, can be combined
* - PM_CAP_ACCESS : full access / functionality
* - PM_CAP_CONTEXT : preserve context
* - PM_CAP_WAKEUP : emit wake interrupts
* @param QoS Quality of Service (0-100) required
* @param Ack Requested acknowledge type
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_RequestNode(const u32 DeviceId, const u32 Capabilities,
const u32 QoS, const u32 Ack)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD4(Payload, PM_REQUEST_NODE, DeviceId, Capabilities,
QoS, Ack);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to release the requested device
*
* @param DeviceId Device which needs to be released
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_ReleaseNode(const u32 DeviceId)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD1(Payload, PM_RELEASE_NODE, DeviceId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to set the requirement for specified device
*
* @param DeviceId Device for which requirement needs to be set
* @param Capabilities Device Capabilities, can be combined
* - PM_CAP_ACCESS : full access / functionality
* - PM_CAP_CONTEXT : preserve context
* - PM_CAP_WAKEUP : emit wake interrupts
* @param QoS Quality of Service (0-100) required
* @param Ack Requested acknowledge type
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_SetRequirement(const u32 DeviceId, const u32 Capabilities,
const u32 QoS, const u32 Ack)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD4(Payload, PM_SET_REQUIREMENT, DeviceId, Capabilities, QoS, Ack);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to get the device status
*
* @param DeviceId Device for which status is requested
* @param NodeStatus Structure pointer to store device status
* - Status - The current power state of the device
* - For CPU nodes:
* - 0 : if CPU is powered down,
* - 1 : if CPU is active (powered up),
* - 2 : if CPU is suspending (powered up)
* - For power islands and power domains:
* - 0 : if island is powered down,
* - 1 : if island is powered up
* - For slaves:
* - 0 : if slave is powered down,
* - 1 : if slave is powered up,
* - 2 : if slave is in retention
*
* - Requirement - Requirements placed on the device by the caller
*
* - Usage
* - 0 : node is not used by any PU,
* - 1 : node is used by caller exclusively,
* - 2 : node is used by other PU(s) only,
* - 3 : node is used by caller and by other PU(s)
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_GetNodeStatus(const u32 DeviceId, XPm_NodeStatus *const NodeStatus)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == NodeStatus) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD1(Payload, PM_GET_NODE_STATUS, DeviceId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, &NodeStatus->status,
&NodeStatus->requirements,
&NodeStatus->usage);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to assert or release reset for a particular
* reset line. Alternatively a reset pulse can be requested as well.
*
* @param ResetId Reset ID
* @param Action Reset action to be taken
* - PM_RESET_ACTION_RELEASE for Release Reset
* - PM_RESET_ACTION_ASSERT for Assert Reset
* - PM_RESET_ACTION_PULSE for Pulse Reset
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_ResetAssert(const u32 ResetId, const u32 Action)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD2(Payload, PM_RESET_ASSERT, ResetId, Action);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to get the status of reset
*
* @param ResetId Reset ID
* @param State Pointer to store the status of specified reset
* - 1 for reset asserted
* - 2 for reset released
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_ResetGetStatus(const u32 ResetId, u32 *const State)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == State) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD1(Payload, PM_RESET_GET_STATUS, ResetId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, State, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to request the pin
*
* @param PinId Pin ID
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_PinCtrlRequest(const u32 PinId)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD1(Payload, PM_PINCTRL_REQUEST, PinId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to release the pin
*
* @param PinId Pin ID
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_PinCtrlRelease(const u32 PinId)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD1(Payload, PM_PINCTRL_RELEASE, PinId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to set the function on specified pin
*
* @param PinId Pin ID
* @param FunctionId Function ID which needs to be set
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_PinCtrlSetFunction(const u32 PinId, const u32 FunctionId)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD2(Payload, PM_PINCTRL_SET_FUNCTION, PinId, FunctionId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to get the function on specified pin
*
* @param PinId Pin ID
* @param FunctionId Pointer to Function ID
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_PinCtrlGetFunction(const u32 PinId, u32 *const FunctionId)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == FunctionId) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD1(Payload, PM_PINCTRL_GET_FUNCTION, PinId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, FunctionId, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to set the pin parameter of specified pin
*
* @param PinId Pin ID
* @param ParamId Parameter ID
* @param ParamVal Value of the parameter
*
* @details The following table lists the parameter ID and their respective values:
*
* ----------------------------------------------------------------------------
* ParamId | ParamVal
* ---------------------|------------------------------------------------------
* PINCTRL_CONFIG_SLEW_RATE | PINCTRL_SLEW_RATE_SLOW, PINCTRL_SLEW_RATE_FAST
* PINCTRL_CONFIG_BIAS_STATUS | PINCTRL_BIAS_DISABLE, PINCTRL_BIAS_ENABLE
* PINCTRL_CONFIG_PULL_CTRL | PINCTRL_BIAS_PULL_DOWN, PINCTRL_BIAS_PULL_UP
* PINCTRL_CONFIG_SCHMITT_CMOS | PINCTRL_INPUT_TYPE_CMOS, PINCTRL_INPUT_TYPE_SCHMITT
* PINCTRL_CONFIG_DRIVE_STRENGTH | PINCTRL_DRIVE_STRENGTH_TRISTATE, PINCTRL_DRIVE_STRENGTH_4MA, PINCTRL_DRIVE_STRENGTH_8MA, PINCTRL_DRIVE_STRENGTH_12MA
* PINCTRL_CONFIG_TRI_STATE | PINCTRL_TRI_STATE_DISABLE, PINCTRL_TRI_STATE_ENABLE
* ----------------------------------------------------------------------------
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_PinCtrlSetParameter(const u32 PinId, const u32 ParamId, const u32 ParamVal)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD3(Payload, PM_PINCTRL_CONFIG_PARAM_SET, PinId, ParamId, ParamVal);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to get the pin parameter of specified pin
*
* @param PinId Pin ID
* @param ParamId Parameter ID
* @param ParamVal Pointer to the value of the parameter
*
* @details The following table lists the parameter ID and their respective values:
*
* ----------------------------------------------------------------------------
* ParamId | ParamVal
* ---------------------|------------------------------------------------------
* PINCTRL_CONFIG_SLEW_RATE | PINCTRL_SLEW_RATE_SLOW, PINCTRL_SLEW_RATE_FAST
* PINCTRL_CONFIG_BIAS_STATUS | PINCTRL_BIAS_DISABLE, PINCTRL_BIAS_ENABLE
* PINCTRL_CONFIG_PULL_CTRL | PINCTRL_BIAS_PULL_DOWN, PINCTRL_BIAS_PULL_UP
* PINCTRL_CONFIG_SCHMITT_CMOS | PINCTRL_INPUT_TYPE_CMOS, PINCTRL_INPUT_TYPE_SCHMITT
* PINCTRL_CONFIG_DRIVE_STRENGTH | PINCTRL_DRIVE_STRENGTH_TRISTATE, PINCTRL_DRIVE_STRENGTH_4MA, PINCTRL_DRIVE_STRENGTH_8MA, PINCTRL_DRIVE_STRENGTH_12MA
* PINCTRL_CONFIG_VOLTAGE_STATUS | 1 for 1.8v mode, 0 for 3.3v mode
* PINCTRL_CONFIG_TRI_STATE | PINCTRL_TRI_STATE_DISABLE, PINCTRL_TRI_STATE_ENABLE
* ----------------------------------------------------------------------------
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_PinCtrlGetParameter(const u32 PinId, const u32 ParamId, u32 *const ParamVal)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == ParamVal) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD2(Payload, PM_PINCTRL_CONFIG_PARAM_GET, PinId, ParamId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, ParamVal, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function performs driver-like IOCTL functions on shared system
* devices.
*
* @param DeviceId ID of the device
* @param IoctlId IOCTL function ID
* @param Arg1 Argument 1
* @param Arg2 Argument 2
* @param Response Ioctl response
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_DevIoctl(const u32 DeviceId, const u32 IoctlId, const u32 Arg1,
const u32 Arg2, u32 *const Response)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == Response) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD4(Payload, PM_IOCTL, DeviceId, IoctlId, Arg1, Arg2);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, Response, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to enable the specified clock
*
* @param ClockId Clock ID
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_ClockEnable(const u32 ClockId)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD1(Payload, PM_CLOCK_ENABLE, ClockId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to disable the specified clock
*
* @param ClockId Clock ID
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_ClockDisable(const u32 ClockId)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD1(Payload, PM_CLOCK_DISABLE, ClockId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to get the state of specified clock
*
* @param ClockId Clock ID
* @param State Pointer to store the clock state
* - 1 for enable and 0 for disable
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_ClockGetStatus(const u32 ClockId, u32 *const State)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == State) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD1(Payload, PM_CLOCK_GETSTATE, ClockId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, State, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to set the divider value for specified clock
*
* @param ClockId Clock ID
* @param Divider Value of the divider
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_ClockSetDivider(const u32 ClockId, const u32 Divider)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD2(Payload, PM_CLOCK_SETDIVIDER, ClockId, Divider);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to get divider value for specified clock
*
* @param ClockId Clock ID
* @param Divider Pointer to store divider value
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_ClockGetDivider(const u32 ClockId, u32 *const Divider)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == Divider) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD1(Payload, PM_CLOCK_GETDIVIDER, ClockId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, Divider, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to set the parent for specified clock
*
* @param ClockId Clock ID
* @param ParentIdx Parent clock index
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_ClockSetParent(const u32 ClockId, const u32 ParentIdx)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD2(Payload, PM_CLOCK_SETPARENT, ClockId, ParentIdx);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to get the parent of specified clock
*
* @param ClockId Clock ID
* @param ParentIdx Pointer to store the parent clock index
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_ClockGetParent(const u32 ClockId, u32 *const ParentIdx)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == ParentIdx) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD1(Payload, PM_CLOCK_GETPARENT, ClockId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, ParentIdx, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to get rate of specified clock
*
* @param ClockId Clock ID
* @param Rate Pointer to store the rate clock
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
****************************************************************************/
int XPm_ClockGetRate(const u32 ClockId, u32 *const Rate)
{
int Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD1(Payload, PM_CLOCK_GETRATE, ClockId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, Rate, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to set the rate of specified clock
*
* @param ClockId Clock ID
* @param Rate Clock rate
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
****************************************************************************/
int XPm_ClockSetRate(const u32 ClockId, const u32 Rate)
{
int Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD2(Payload, PM_CLOCK_SETRATE, ClockId, Rate);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to set the parameters for specified PLL clock
*
* @param ClockId Clock ID
* @param ParamId Parameter ID
* - PM_PLL_PARAM_ID_DIV2
* - PM_PLL_PARAM_ID_FBDIV
* - PM_PLL_PARAM_ID_DATA
* - PM_PLL_PARAM_ID_PRE_SRC
* - PM_PLL_PARAM_ID_POST_SRC
* - PM_PLL_PARAM_ID_LOCK_DLY
* - PM_PLL_PARAM_ID_LOCK_CNT
* - PM_PLL_PARAM_ID_LFHF
* - PM_PLL_PARAM_ID_CP
* - PM_PLL_PARAM_ID_RES
* @param Value Value of parameter
* (See register description for possible values)
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_PllSetParameter(const u32 ClockId,
const enum XPm_PllConfigParams ParamId,
const u32 Value)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD3(Payload, PM_PLL_SET_PARAMETER, ClockId, ParamId, Value);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to get the parameter of specified PLL clock
*
* @param ClockId Clock ID
* @param ParamId Parameter ID
* - PM_PLL_PARAM_ID_DIV2
* - PM_PLL_PARAM_ID_FBDIV
* - PM_PLL_PARAM_ID_DATA
* - PM_PLL_PARAM_ID_PRE_SRC
* - PM_PLL_PARAM_ID_POST_SRC
* - PM_PLL_PARAM_ID_LOCK_DLY
* - PM_PLL_PARAM_ID_LOCK_CNT
* - PM_PLL_PARAM_ID_LFHF
* - PM_PLL_PARAM_ID_CP
* - PM_PLL_PARAM_ID_RES
* @param Value Pointer to store parameter value
* (See register description for possible values)
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_PllGetParameter(const u32 ClockId,
const enum XPm_PllConfigParams ParamId,
u32 *const Value)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == Value) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD2(Payload, PM_PLL_GET_PARAMETER, ClockId, ParamId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, Value, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to set the mode of specified PLL clock
*
* @param ClockId Clock ID
* @param Value Mode which need to be set
* - 0 for Reset mode
* - 1 for Integer mode
* - 2 for Fractional mode
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_PllSetMode(const u32 ClockId, const u32 Value)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD2(Payload, PM_PLL_SET_MODE, ClockId, Value);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used to get the mode of specified PLL clock
*
* @param ClockId Clock ID
* @param Value Pointer to store the value of mode
* - 0 for Reset mode
* - 1 for Integer mode
* - 2 for Fractional mode
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_PllGetMode(const u32 ClockId, u32 *const Value)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == Value) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD1(Payload, PM_PLL_GET_MODE, ClockId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, Value, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used by a CPU to declare that it is about to
* suspend itself.
*
* @param DeviceId Device ID of the CPU
* @param Latency Maximum wake-up latency requirement in us(microsecs)
* @param State Instead of specifying a maximum latency, a CPU can also
* explicitly request a certain power state.
* @param Address Address from which to resume when woken up.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_SelfSuspend(const u32 DeviceId, const u32 Latency,
const u8 State, const u64 Address)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
struct XPm_Proc *Proc;
Proc = XPm_GetProcByDeviceId(DeviceId);
if (NULL == Proc) {
XPm_Dbg("ERROR: Invalid Device ID\r\n");
Status = (s32)XST_INVALID_PARAM;
goto done;
}
XPm_ClientSuspend(Proc);
PACK_PAYLOAD5(Payload, PM_SELF_SUSPEND, DeviceId, Latency, State,
(u32)Address, (u32)(Address >> 32));
/* Send request to the target module */
Status = XPm_IpiSend(Proc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(Proc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function can be used to request power up of a CPU node
* within the same PU, or to power up another PU.
*
* @param TargetDevId Device ID of the CPU or PU to be powered/woken up.
* @param SetAddress Specifies whether the start address argument is being passed.
* - 0 : do not set start address
* - 1 : set start address
* @param Address Address from which to resume when woken up.
* Will only be used if set_address is 1.
* @param Ack Requested acknowledge type
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_RequestWakeUp(const u32 TargetDevId, const u8 SetAddress,
const u64 Address, const u32 Ack)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
u64 EncodedAddr;
struct XPm_Proc *Proc;
Proc = XPm_GetProcByDeviceId(TargetDevId);
XPm_ClientWakeUp(Proc);
/* encode set Address into 1st bit of address */
EncodedAddr = Address | ((1U == SetAddress) ? 1U : 0U);
PACK_PAYLOAD4(Payload, PM_REQUEST_WAKEUP, TargetDevId, (u32)EncodedAddr,
(u32)(EncodedAddr >> 32), Ack);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This Function waits for firmware to finish all previous API requests
* sent by the PU and performs client specific actions to finish suspend
* procedure (e.g. execution of wfi instruction on A53 and R5 processors).
*
* @note This function should not return if the suspend procedure is
* successful.
*
****************************************************************************/
void XPm_SuspendFinalize(void)
{
XStatus Status = (s32)XST_FAILURE;
/*
* Wait until previous IPI request is handled by the PMU.
* If PMU is busy, keep trying until PMU becomes responsive
*/
do {
Status = XIpiPsu_PollForAck(PrimaryProc->Ipi,
TARGET_IPI_INT_MASK,
PM_IPI_TIMEOUT);
if (Status != XST_SUCCESS) {
XPm_Dbg("ERROR timed out while waiting for PMU to"
" finish processing previous PM-API call\n");
}
} while (XST_SUCCESS != Status);
XPm_ClientSuspendFinalize();
}
/****************************************************************************/
/**
* @brief This function is used by a CPU to request suspend to another CPU.
*
* @param TargetSubsystemId Subsystem ID of the target
* @param Ack Requested acknowledge type
* @param Latency Maximum wake-up latency requirement in us(microsecs)
* @param State Power State
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_RequestSuspend(const u32 TargetSubsystemId, const u32 Ack,
const u32 Latency, const u32 State)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD4(Payload, PM_REQUEST_SUSPEND, TargetSubsystemId, Ack, Latency, State);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is called by a CPU after a SelfSuspend call to
* notify the platform management controller that CPU has aborted suspend
* or in response to an init suspend request when the PU refuses to suspend.
*
* @param reason Reason code why the suspend can not be performed or completed
* - ABORT_REASON_WKUP_EVENT : local wakeup-event received
* - ABORT_REASON_PU_BUSY : PU is busy
* - ABORT_REASON_NO_PWRDN : no external powerdown supported
* - ABORT_REASON_UNKNOWN : unknown error during suspend procedure
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_AbortSuspend(const enum XPmAbortReason Reason)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD2(Payload, PM_ABORT_SUSPEND, Reason, PrimaryProc->DevId);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
if (XST_SUCCESS != Status) {
goto done;
}
/*
* Do client specific abort suspend operations
* (e.g. enable interrupts and clear powerdown request bit)
*/
XPm_ClientAbortSuspend();
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used by PU to request a forced poweroff of another
* PU or its power island or power domain. This can be used for killing an
* unresponsive PU, in which case all resources of that PU will be
* automatically released.
*
* @param TargetDevId Device ID of the PU node to be forced powered down.
* @param Ack Requested acknowledge type
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note Force power down may not be requested by a PU for itself.
*
****************************************************************************/
XStatus XPm_ForcePowerDown(const u32 TargetDevId, const u32 Ack)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD2(Payload, PM_FORCE_POWERDOWN, TargetDevId, Ack);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function can be used by a privileged PU to shut down
* or restart the complete device.
*
* @param Type Shutdown type (shutdown/restart)
* @param SubType Shutdown subtype (subsystem-only/PU-only/system)
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_SystemShutdown(const u32 Type, const u32 SubType)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD2(Payload, PM_SYSTEM_SHUTDOWN, Type, SubType);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used by a CPU to set wakeup source
*
* @param TargetDeviceId Device ID of the target
* @param DeviceId Device ID used as wakeup source
* @param Enable 1 - Enable, 0 - Disable
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_SetWakeUpSource(const u32 TargetDeviceId, const u32 DeviceId,
const u32 Enable)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD3(Payload, PM_SET_WAKEUP_SOURCE, TargetDeviceId, DeviceId, Enable);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function queries information about the platform resources.
*
* @param Qid The type of data to query
* @param Arg1 Query argument 1
* @param Arg2 Query argument 2
* @param Arg3 Query argument 3
* @param Data Pointer to the output data
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
****************************************************************************/
XStatus XPm_Query(const u32 QueryId, const u32 Arg1, const u32 Arg2,
const u32 Arg3, u32 *const Data)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == Data) {
XPm_Dbg("ERROR: Passing NULL pointer to %s\r\n", __func__);
goto done;
}
PACK_PAYLOAD4(Payload, PM_QUERY_DATA, QueryId, Arg1, Arg2, Arg3);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
switch (QueryId) {
case (u32)XPM_QID_CLOCK_GET_NAME:
case (u32)XPM_QID_PINCTRL_GET_FUNCTION_NAME:
/*
* XPM_QID_CLOCK_GET_NAME and XPM_QID_PINCTRL_GET_FUNCTION_NAME store
* part of their clock names in Status variable which is stored
* in response. So this value should not be treated as error code.
* Consider error only if clock name is not found.
*/
Status = Xpm_IpiReadBuff32(PrimaryProc, &Data[1], &Data[2], &Data[3]);
if (XST_SUCCESS != Status) {
Data[0] = (u32)('\0');
Status = (s32)XST_FAILURE;
} else {
Data[0] = (u32)Status;
}
break;
case (u32)XPM_QID_CLOCK_GET_TOPOLOGY:
case (u32)XPM_QID_CLOCK_GET_MUXSOURCES:
case (u32)XPM_QID_PINCTRL_GET_FUNCTION_GROUPS:
case (u32)XPM_QID_PINCTRL_GET_PIN_GROUPS:
Status = Xpm_IpiReadBuff32(PrimaryProc, &Data[0], &Data[1], &Data[2]);
break;
case (u32)XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS:
Status = Xpm_IpiReadBuff32(PrimaryProc, &Data[0], &Data[1], NULL);
break;
case (u32)XPM_QID_CLOCK_GET_ATTRIBUTES:
case (u32)XPM_QID_PINCTRL_GET_NUM_PINS:
case (u32)XPM_QID_PINCTRL_GET_NUM_FUNCTIONS:
case (u32)XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS:
case (u32)XPM_QID_CLOCK_GET_NUM_CLOCKS:
case (u32)XPM_QID_CLOCK_GET_MAX_DIVISOR:
Status = Xpm_IpiReadBuff32(PrimaryProc, &Data[0], NULL, NULL);
break;
default:
Status = (s32)XST_INVALID_PARAM;
break;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is used by a CPU to announce a change in the
* maximum wake-up latency requirements for a specific device
* currently used by that CPU.
*
* @param DeviceId Device ID.
* @param Latency Maximum wake-up latency required.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note Setting maximum wake-up latency can constrain the set of
* possible power states a resource can be put into.
*
****************************************************************************/
int XPm_SetMaxLatency(const u32 DeviceId, const u32 Latency)
{
int Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD2(Payload, PM_SET_MAX_LATENCY, DeviceId, Latency);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Read the result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief Call this function to request the power management controller to
* return information about an operating characteristic of a component.
*
* @param DeviceId Device ID.
* @param Type Type of operating characteristic requested:
* - power (current power consumption),
* - latency (current latency in us to return to active
* state),
* - temperature (current temperature),
* @param Result Used to return the requested operating characteristic.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
XStatus XPm_GetOpCharacteristic(const u32 DeviceId,
const enum XPmOpCharType Type,
u32 *const Result)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
/* Send request to the target module */
PACK_PAYLOAD2(Payload, PM_GET_OP_CHARACTERISTIC, DeviceId, Type);
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, Result, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function is called to notify the power management controller
* about the completed power management initialization.
*
* @return XST_SUCCESS if successful, otherwise an error code
*
****************************************************************************/
int XPm_InitFinalize(void)
{
XStatus Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
PACK_PAYLOAD0(Payload, PM_INIT_FINALIZE);
/* Send request to the target module */
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
done:
return Status;
}
/****************************************************************************/
/**
* @brief A PU can call this function to request that the power management
* controller call its notify callback whenever a qualifying event occurs.
* One can request to be notified for a specific or any event related to
* a specific node.
*
* @param Notifier Pointer to the notifier object to be associated with
* the requested notification.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
* @note The caller shall initialize the notifier object before invoking
* the XPm_RegisteredNotifier function. While notifier is registered,
* the notifier object shall not be modified by the caller.
*
****************************************************************************/
int XPm_RegisterNotifier(XPm_Notifier* const Notifier)
{
int Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == Notifier) {
XPm_Dbg("%s ERROR: NULL notifier pointer\n", __func__);
Status = (s32)XST_INVALID_PARAM;
goto done;
}
/* Send request to the target module */
PACK_PAYLOAD4(Payload, PM_REGISTER_NOTIFIER, Notifier->node,
Notifier->event, Notifier->flags, 1);
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
if (XST_SUCCESS != Status) {
goto done;
}
/* Add notifier in the list only if target module has it registered */
Status = XPm_NotifierAdd(Notifier);
done:
return Status;
}
/****************************************************************************/
/**
* @brief A PU calls this function to unregister for the previously
* requested notifications.
*
* @param Notifier Pointer to the notifier object associated with the
* previously requested notification
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code
* or a reason code
*
*
*
****************************************************************************/
int XPm_UnregisterNotifier(XPm_Notifier* const Notifier)
{
int Status = (s32)XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
if (NULL == Notifier) {
XPm_Dbg("%s ERROR: NULL notifier pointer\n", __func__);
Status = (s32)XST_INVALID_PARAM;
goto done;
}
/*
* Remove first the notifier from the list. If it's not in the list
* report an error, and don't trigger target module since it don't have
* it registered either.
*/
Status = XPm_NotifierRemove(Notifier);
if (XST_SUCCESS != Status) {
goto done;
}
/* Send request to the target module */
PACK_PAYLOAD4(Payload, PM_REGISTER_NOTIFIER, Notifier->node,
Notifier->event, 0, 0);
Status = XPm_IpiSend(PrimaryProc, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
/* Return result from IPI return buffer */
Status = Xpm_IpiReadBuff32(PrimaryProc, NULL, NULL, NULL);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
/* Callback API functions */
struct pm_init_suspend pm_susp = {
.received = 0U,
/* initialization of other fields is irrelevant while 'received' is false */
};
struct pm_acknowledge pm_ack = {
.received = 0U,
/* initialization of other fields is irrelevant while 'received' is false */
};
/****************************************************************************/
/**
* @brief Callback function to be implemented in each PU, allowing the power
* management controller to request that the PU suspend itself.
*
* @param Reason Suspend reason:
* - SUSPEND_REASON_PU_REQ : Request by another PU
* - SUSPEND_REASON_ALERT : Unrecoverable SysMon alert
* - SUSPEND_REASON_SHUTDOWN : System shutdown
* - SUSPEND_REASON_RESTART : System restart
* @param Latency Maximum wake-up latency in us(micro secs). This information
* can be used by the PU to decide what level of context saving may be
* required.
* @param State Targeted sleep/suspend state.
* @param Timeout Timeout in ms, specifying how much time a PU has to initiate
* its suspend procedure before it's being considered unresponsive.
*
* @return None
*
* @note If the PU fails to act on this request the power management
* controller or the requesting PU may choose to employ the forceful
* power down option.
*
****************************************************************************/
void XPm_InitSuspendCb(const enum XPmSuspendReason Reason,
const u32 Latency, const u32 State, const u32 Timeout)
{
if (1U == pm_susp.received) {
XPm_Dbg("%s: WARNING: dropping unhandled init suspend request!\n", __func__);
XPm_Dbg("Dropped %s (%d, %d, %d, %d)\n", __func__, pm_susp.reason,
pm_susp.latency, pm_susp.state, pm_susp.timeout);
}
XPm_Dbg("%s (%d, %d, %d, %d)\n", __func__, Reason, Latency, State, Timeout);
pm_susp.reason = Reason;
pm_susp.latency = Latency;
pm_susp.state = State;
pm_susp.timeout = Timeout;
pm_susp.received = 1U;
}
/****************************************************************************/
/**
* @brief This function is called by the power management controller in
* response to any request where an acknowledge callback was requested,
* i.e. where the 'ack' argument passed by the PU was REQUEST_ACK_NON_BLOCKING.
*
* @param Node ID of the component or sub-system in question.
* @param Status Status of the operation:
* - OK: the operation completed successfully
* - ERR: the requested operation failed
* @param Oppoint Operating point of the node in question
*
* @return None
*
*
*
****************************************************************************/
void XPm_AcknowledgeCb(const u32 Node, const XStatus Status, const u32 Oppoint)
{
if (1U == pm_ack.received) {
XPm_Dbg("%s: WARNING: dropping unhandled acknowledge!\n", __func__);
XPm_Dbg("Dropped %s (%d, %d, %d)\n", __func__, pm_ack.node,
pm_ack.status, pm_ack.opp);
}
XPm_Dbg("%s (%d, %d, %d)\n", __func__, Node, Status, Oppoint);
pm_ack.node = Node;
pm_ack.status = Status;
pm_ack.opp = Oppoint;
pm_ack.received = 1U;
}
/****************************************************************************/
/**
* @brief This function is called by the power management controller if an
* event the PU was registered for has occurred. It will populate the notifier
* data structure passed when calling XPm_RegisterNotifier.
*
* @param Node ID of the device the event notification is related to.
* @param Event ID of the event
* @param Oppoint Current operating state of the device.
*
* @return None
*
*
*
****************************************************************************/
void XPm_NotifyCb(const u32 Node, const enum XPmNotifyEvent Event,
const u32 Oppoint)
{
XPm_Dbg("%s (%d, %d, %d)\n", __func__, Node, Event, Oppoint);
XPm_NotifierProcessEvent(Node, Event, Oppoint);
}
int XPm_SetConfiguration(const u32 Address)
{
/* Suppress compilation warning */
(void)Address;
XPm_Dbg("WARNING: %s() API is not supported\r\n", __func__);
return (s32)XST_SUCCESS;
}
int XPm_MmioWrite(const u32 Address, const u32 Mask, const u32 Value)
{
/* Suppress compilation warning */
(void)Address, (void)Mask, (void)Value;
XPm_Dbg("ERROR: %s() API is not supported\r\n", __func__);
return (s32)XST_FAILURE;
}
int XPm_MmioRead(const u32 Address, u32 *const Value)
{
/* Suppress compilation warning */
(void)Address, (void)Value;
XPm_Dbg("ERROR: %s() API is not supported\r\n", __func__);
return (s32)XST_FAILURE;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/usbpsu_v1_7/src/xusbpsu_device.c
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_device.c
* @addtogroup usbpsu_v1_7
* @{
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.0 pm 03/03/20 First release
* 1.7 pm 25/03/20 Add clocking support
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xusbpsu_local.h"
#include "sleep.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
static INLINE void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr);
void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr);
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* Waits until a bit in a register is cleared or timeout occurs
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on
* @param Offset is register offset.
* @param BitMask is bit mask of required bit to be checked.
* @param Timeout is the time to wait specified in micro seconds.
*
* @return
* - XST_SUCCESS when bit is cleared.
* - XST_FAILURE when timed out.
*
******************************************************************************/
s32 XUsbPsu_WaitClearTimeout(struct XUsbPsu *InstancePtr, u32 Offset,
u32 BitMask, u32 Timeout)
{
u32 RegVal;
u32 LocalTimeout = Timeout;
while (LocalTimeout > 0U) {
RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
if ((RegVal & BitMask) == 0U) {
break;
}
LocalTimeout = LocalTimeout - 1U;
XUsbPsu_Sleep(1U);
}
if (LocalTimeout == 0U) {
return (s32)XST_FAILURE;
}
return (s32)XST_SUCCESS;
}
/*****************************************************************************/
/**
* Waits until a bit in a register is set or timeout occurs
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on
* @param Offset is register offset.
* @param BitMask is bit mask of required bit to be checked.
* @param Timeout is the time to wait specified in micro seconds.
*
* @return
* - XST_SUCCESS when bit is set.
* - XST_FAILURE when timed out.
*
******************************************************************************/
s32 XUsbPsu_WaitSetTimeout(struct XUsbPsu *InstancePtr, u32 Offset,
u32 BitMask, u32 Timeout)
{
u32 RegVal;
u32 LocalTimeout = Timeout;
while (LocalTimeout > 0U) {
RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
if ((RegVal & BitMask) != 0U) {
break;
}
LocalTimeout = LocalTimeout - 1U;
XUsbPsu_Sleep(1U);
}
if (LocalTimeout == 0U) {
return (s32)XST_FAILURE;
}
return (s32)XST_SUCCESS;
}
/*****************************************************************************/
/**
* Resets Event buffer Registers to zero so that events are not written by Core.
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
*
* @return None
*
****************************************************************************/
static INLINE void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr)
{
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0U), 0U);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0U), 0U);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U),
(u32)XUSBPSU_GEVNTSIZ_INTMASK |
XUSBPSU_GEVNTSIZ_SIZE(0U));
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U), 0U);
}
/*****************************************************************************/
/**
* Reads data from Hardware Params Registers of Core.
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on
* @param RegIndex is Register number to read
* - XUSBPSU_GHWPARAMS0
* - XUSBPSU_GHWPARAMS1
* - XUSBPSU_GHWPARAMS2
* - XUSBPSU_GHWPARAMS3
* - XUSBPSU_GHWPARAMS4
* - XUSBPSU_GHWPARAMS5
* - XUSBPSU_GHWPARAMS6
* - XUSBPSU_GHWPARAMS7
*
* @return One of the GHWPARAMS RegValister contents.
*
******************************************************************************/
u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex)
{
u32 RegVal;
Xil_AssertNonvoid(RegIndex <= (u8)XUSBPSU_GHWPARAMS7);
RegVal = XUsbPsu_ReadReg(InstancePtr, ((u32)XUSBPSU_GHWPARAMS0_OFFSET +
((u32)RegIndex * (u32)4U)));
return RegVal;
}
/*****************************************************************************/
/**
* * Issues core PHY reset.
* *
* * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
* *
* * @return None
* *
* ****************************************************************************/
void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
/* Before Resetting PHY, put Core in Reset */
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
RegVal |= XUSBPSU_GCTL_CORESOFTRESET;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
/* Assert USB3 PHY reset */
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0U));
RegVal |= XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0U), RegVal);
/* Assert USB2 PHY reset */
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0U));
RegVal |= XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0U), RegVal);
XUsbPsu_Sleep(XUSBPSU_PHY_TIMEOUT);
/* Clear USB3 PHY reset */
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0U));
RegVal &= ~XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0U), RegVal);
/* Clear USB2 PHY reset */
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0U));
RegVal &= ~XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0U), RegVal);
XUsbPsu_Sleep(XUSBPSU_PHY_TIMEOUT);
/* Take Core out of reset state after PHYS are stable*/
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
RegVal &= ~XUSBPSU_GCTL_CORESOFTRESET;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
}
/****************************************************************************/
/**
* @brief
* Sets speed of the Core for connecting to Host
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Speed is required speed
* - XUSBPSU_DCFG_HIGHSPEED
* - XUSBPSU_DCFG_FULLSPEED2
* - XUSBPSU_DCFG_LOWSPEED
* - XUSBPSU_DCFG_FULLSPEED1
*
* @return None
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed)
{
u32 RegVal;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Speed <= (u32)XUSBPSU_DCFG_SUPERSPEED);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
RegVal &= ~(XUSBPSU_DCFG_SPEED_MASK);
RegVal |= Speed;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
}
/****************************************************************************/
/**
* @brief
* Sets Device Address of the Core
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Addr is address to set.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
*****************************************************************************/
s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr)
{
u32 RegVal;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Addr <= 127U);
if (InstancePtr->AppData->State == XUSBPSU_STATE_CONFIGURED) {
return (s32)XST_FAILURE;
}
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
RegVal |= XUSBPSU_DCFG_DEVADDR(Addr);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
if (Addr > 0U) {
InstancePtr->AppData->State = XUSBPSU_STATE_ADDRESS;
} else {
InstancePtr->AppData->State = XUSBPSU_STATE_DEFAULT;
}
return (s32)XST_SUCCESS;
}
/****************************************************************************/
/**
* Enables USB2 Test Modes
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Mode is Test mode to set.
*
* @return XST_SUCCESS else XST_FAILURE
*
* @note None.
*
****************************************************************************/
s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode)
{
u32 RegVal;
s32 Status = XST_SUCCESS;
Xil_AssertNonvoid(InstancePtr != NULL);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
switch (Mode) {
case XUSBPSU_TEST_J:
case XUSBPSU_TEST_K:
case XUSBPSU_TEST_SE0_NAK:
case XUSBPSU_TEST_PACKET:
case XUSBPSU_TEST_FORCE_ENABLE:
RegVal |= (u32)Mode << 1;
break;
default:
Status = (s32)XST_FAILURE;
break;
}
if (Status != (s32)XST_FAILURE) {
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
Status = XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function puts the controller into idle state by stopping the transfers
* for all endpoints, stopping the usb core and clearing the event buffers.
* buffers.
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on
*
* @return None
*
******************************************************************************/
void XUsbPsu_Idle(struct XUsbPsu *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
/* Stop the transfers when in peripheral mode */
if ((XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GSTS) &
XUSBPSU_GSTS_CUR_MODE) == 0U) {
u32 RegVal;
u32 EpNums, CurEpNum, InEpNums, OutEpNums, PhyEpNum;
/* Read HwParams 3 for fetching the max number of eps */
RegVal = XUsbPsu_ReadHwParams(InstancePtr, 3U);
EpNums = XUSBPSU_NUM_EPS(RegVal);
InEpNums = XUSBPSU_NUM_IN_EPS(RegVal);
OutEpNums = EpNums - InEpNums;
/* Stop transfers for Out Endpoints */
for (CurEpNum = 0U; CurEpNum < OutEpNums; CurEpNum++) {
PhyEpNum = XUSBPSU_PhysicalEp(CurEpNum,
XUSBPSU_EP_DIR_OUT);
XUsbPsu_StopTransfer(InstancePtr, CurEpNum,
XUSBPSU_EP_DIR_OUT, FALSE);
/* Wait until CMD ACT bit is cleared */
if (XUsbPsu_WaitClearTimeout(InstancePtr,
XUSBPSU_DEPCMD(PhyEpNum),
XUSBPSU_DEPCMD_CMDACT, 500U) ==
XST_FAILURE) {
#ifdef XUSBPSU_DEBUG
xil_printf(
"End Transfer on Endpoint %dOUT failed\n\r",
CurEpNum);
#endif
}
}
/* Stop transfers for In Endpoints */
for (CurEpNum = 0U; CurEpNum < InEpNums; CurEpNum++) {
PhyEpNum = XUSBPSU_PhysicalEp(CurEpNum,
XUSBPSU_EP_DIR_IN);
XUsbPsu_StopTransfer(InstancePtr, CurEpNum,
XUSBPSU_EP_DIR_IN, FALSE);
/* Wait until CMD ACT bit is cleared */
if (XUsbPsu_WaitClearTimeout(InstancePtr,
XUSBPSU_DEPCMD(PhyEpNum),
XUSBPSU_DEPCMD_CMDACT, 500U) ==
XST_FAILURE) {
#ifdef XUSBPSU_DEBUG
xil_printf(
"End Transfer on Endpoint %dIN failed\n\r",
CurEpNum);
#endif
}
}
/* Stop transfers for Out Endpoints */
for (CurEpNum = 0U; CurEpNum < OutEpNums; CurEpNum++) {
XUsbPsu_EpTransferDeactive(InstancePtr, CurEpNum,
XUSBPSU_EP_DIR_OUT);
}
/* Stop transfers for In Endpoints */
for (CurEpNum = 0U; CurEpNum < InEpNums; CurEpNum++) {
XUsbPsu_EpTransferDeactive(InstancePtr, CurEpNum,
XUSBPSU_EP_DIR_IN);
}
/* Stop the USB core */
if (XUsbPsu_Stop(InstancePtr) == XST_FAILURE) {
#ifdef XUSBPSU_DEBUG
xil_printf("Failed to stop USB core\r\n");
#endif
}
/* Reset the Event buffers to 0 */
XUsbPsu_EventBuffersReset(InstancePtr);
}
}
/*****************************************************************************/
/**
* Initializes Core.
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
*
* @return
* - XST_SUCCESS if initialization was successful
* - XST_FAILURE if initialization was not successful
*
*******************************************************************************/
s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr)
{
u32 RegVal;
u32 Hwparams1;
/* issue device SoftReset too */
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, XUSBPSU_DCTL_CSFTRST);
if (XUsbPsu_WaitClearTimeout(InstancePtr, XUSBPSU_DCTL,
XUSBPSU_DCTL_CSFTRST, 500U) == XST_FAILURE) {
/* timed out return failure */
return (s32)XST_FAILURE;
}
XUsbPsu_PhyReset(InstancePtr);
RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK;
RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE;
RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS;
Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1U);
switch (XUSBPSU_GHWPARAMS1_EN_PWROPT(Hwparams1)) {
case XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK:
RegVal &= ~XUSBPSU_GCTL_DSBLCLKGTNG;
break;
case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB:
/* enable ref clocks */
#if defined (XCLOCKING)
Xil_ClockEnable(InstancePtr->ConfigPtr->RefClk);
#endif
/* enable hibernation here */
#ifdef XUSBPSU_HIBERNATION_ENABLE
RegVal |= XUSBPSU_GCTL_GBLHIBERNATIONEN;
InstancePtr->HasHibernation = 1U;
#endif
break;
default:
/* Made for Misra-C Compliance. */
break;
}
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
#ifdef XUSBPSU_HIBERNATION_ENABLE
if (InstancePtr->HasHibernation == TRUE) {
XUsbPsu_InitHibernation(InstancePtr);
}
#endif
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* Sets up Event buffers so that events are written by Core.
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
*
* @return None
*
****************************************************************************/
void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr)
{
struct XUsbPsu_EvtBuffer *Evt;
Evt = &InstancePtr->Evt;
Evt->BuffAddr = (void *)InstancePtr->EventBuffer;
Evt->Offset = 0U;
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0U),
(UINTPTR)InstancePtr->EventBuffer);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0U),
((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U);
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U),
XUSBPSU_GEVNTSIZ_SIZE(
sizeof(InstancePtr->EventBuffer)));
XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U), 0U);
}
/*****************************************************************************/
/**
* @brief
* API for Sleep routine.
*
* @param USeconds is time in MicroSeconds.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XUsbPsu_Sleep(u32 USeconds)
{
(void)usleep(USeconds);
}
#ifdef XUSBPSU_HIBERNATION_ENABLE
/*****************************************************************************/
/**
* Sets scratchpad buffers
*
* @param InstancePtr is a pointer to the XUsbPsu instance to be worked
* on.
*
* @return XST_SUCCESS on success or else error code
*
* @note None.
*
******************************************************************************/
s32 XUsbPsu_SetupScratchpad(struct XUsbPsu *InstancePtr, u8 *ScratchBuf)
{
s32 Ret;
Ret = XUsbPsu_SendGadgetGenericCmd(InstancePtr,
XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO,
(UINTPTR)ScratchBuf & 0xFFFFFFFFU);
if (Ret == XST_FAILURE) {
xil_printf("Failed to set scratchpad low addr: %d\n", Ret);
return Ret;
}
Ret = XUsbPsu_SendGadgetGenericCmd(InstancePtr,
XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI,
((UINTPTR)ScratchBuf >> 16U) >> 16U);
if (Ret == XST_FAILURE) {
xil_printf("Failed to set scratchpad high addr: %d\n", Ret);
return Ret;
}
return XST_SUCCESS;
}
#endif
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/common/xpm_defs.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/**
* @file xpm_defs.h
*
* @addtogroup xpm_versal_apis XilPM Versal APIs
* @{
*****************************************************************************/
#ifndef XPM_DEFS_H_
#define XPM_DEFS_H_
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Version number is a 32bit value, like:
* (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
*/
#define PM_VERSION_MAJOR 1UL
#define PM_VERSION_MINOR 0UL
#define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR)
/**
* PM abort reasons enumeration.
*/
enum XPmAbortReason {
ABORT_REASON_WKUP_EVENT = 100,
ABORT_REASON_PU_BUSY,
ABORT_REASON_NO_PWRDN,
ABORT_REASON_UNKNOWN,
};
/**
* Boot status enumeration.
*/
enum XPmBootStatus {
PM_INITIAL_BOOT, /**< boot is a fresh system startup */
PM_RESUME, /**< boot is a resume */
PM_BOOT_ERROR, /**< error, boot cause cannot be identified */
};
/**
* Device capability requirements enumeration.
*/
enum XPmCapability {
PM_CAP_ACCESS = 0x1U, /**< Full access */
PM_CAP_CONTEXT = 0x2U, /**< Configuration and contents retained */
PM_CAP_WAKEUP = 0x4U, /**< Enabled as a wake-up source */
PM_CAP_UNUSABLE = 0x8U, /**< Not usable */
};
/* Usage status, returned by PmGetNodeStatus */
enum XPmDeviceUsage {
PM_USAGE_CURRENT_SUBSYSTEM = 0x1U,
PM_USAGE_OTHER_SUBSYSTEM = 0x2U,
};
/* Reset configuration argument */
enum XPmResetActions {
PM_RESET_ACTION_RELEASE,
PM_RESET_ACTION_ASSERT,
PM_RESET_ACTION_PULSE,
};
/* Suspend reasons */
enum XPmSuspendReason {
SUSPEND_REASON_PU_REQ = (201U),
SUSPEND_REASON_ALERT = (202U),
SUSPEND_REASON_SYS_SHUTDOWN = (203U),
};
/* PM API callback ids */
enum XPmApiCbId {
PM_INIT_SUSPEND_CB = (30U),
PM_ACKNOWLEDGE_CB = (31U),
PM_NOTIFY_CB = (32U),
};
/**
* Contains the device status information.
*/
typedef struct XPm_DeviceStatus {
u32 Status; /**< Device power state */
u32 Requirement; /**< Requirements placed on the device by the caller */
u32 Usage; /**< Usage info (which subsystem is using the device) */
} XPm_DeviceStatus;
/* Requirement limits */
#define XPM_MAX_CAPABILITY ((u32)PM_CAP_ACCESS | (u32)PM_CAP_CONTEXT | (u32)PM_CAP_WAKEUP)
#define XPM_MAX_LATENCY (0xFFFFU)
#define XPM_MAX_QOS (100)
#define XPM_MIN_CAPABILITY (0)
#define XPM_MIN_LATENCY (0)
#define XPM_MIN_QOS (0)
#define XPM_DEF_CAPABILITY XPM_MAX_CAPABILITY
#define XPM_DEF_LATENCY XPM_MAX_LATENCY
#define XPM_DEF_QOS XPM_MAX_QOS
/* Device node status */
#define NODE_STATE_OFF (0U)
#define NODE_STATE_ON (1U)
/* Processor node status */
#define PROC_STATE_SLEEP NODE_STATE_OFF
#define PROC_STATE_ACTIVE NODE_STATE_ON
#define PROC_STATE_FORCEDOFF (7U)
#define PROC_STATE_SUSPENDING (8U)
enum pm_query_id {
XPM_QID_INVALID,
XPM_QID_CLOCK_GET_NAME,
XPM_QID_CLOCK_GET_TOPOLOGY,
XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
XPM_QID_CLOCK_GET_MUXSOURCES,
XPM_QID_CLOCK_GET_ATTRIBUTES,
XPM_QID_PINCTRL_GET_NUM_PINS,
XPM_QID_PINCTRL_GET_NUM_FUNCTIONS,
XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
XPM_QID_PINCTRL_GET_FUNCTION_NAME,
XPM_QID_PINCTRL_GET_FUNCTION_GROUPS,
XPM_QID_PINCTRL_GET_PIN_GROUPS,
XPM_QID_CLOCK_GET_NUM_CLOCKS,
XPM_QID_CLOCK_GET_MAX_DIVISOR,
};
enum PmPinFunIds {
PIN_FUNC_SPI0,
PIN_FUNC_SPI0_SS,
PIN_FUNC_SPI1,
PIN_FUNC_SPI1_SS,
PIN_FUNC_CAN0,
PIN_FUNC_CAN1,
PIN_FUNC_I2C0,
PIN_FUNC_I2C1,
PIN_FUNC_I2C_PMC,
PIN_FUNC_TTC0_CLK,
PIN_FUNC_TTC0_WAV,
PIN_FUNC_TTC1_CLK,
PIN_FUNC_TTC1_WAV,
PIN_FUNC_TTC2_CLK,
PIN_FUNC_TTC2_WAV,
PIN_FUNC_TTC3_CLK,
PIN_FUNC_TTC3_WAV,
PIN_FUNC_WWDT0,
PIN_FUNC_WWDT1,
PIN_FUNC_SYSMON_I2C0,
PIN_FUNC_SYSMON_I2C0_ALERT,
PIN_FUNC_UART0,
PIN_FUNC_UART0_CTRL,
PIN_FUNC_UART1,
PIN_FUNC_UART1_CTRL,
PIN_FUNC_GPIO0,
PIN_FUNC_GPIO1,
PIN_FUNC_GPIO2,
PIN_FUNC_EMIO0,
PIN_FUNC_GEM0,
PIN_FUNC_GEM1,
PIN_FUNC_TRACE0,
PIN_FUNC_TRACE0_CLK,
PIN_FUNC_MDIO0,
PIN_FUNC_MDIO1,
PIN_FUNC_GEM_TSU0,
PIN_FUNC_PCIE0,
PIN_FUNC_SMAP0,
PIN_FUNC_USB0,
PIN_FUNC_SD0,
PIN_FUNC_SD0_PC,
PIN_FUNC_SD0_CD,
PIN_FUNC_SD0_WP,
PIN_FUNC_SD1,
PIN_FUNC_SD1_PC,
PIN_FUNC_SD1_CD,
PIN_FUNC_SD1_WP,
PIN_FUNC_OSPI0,
PIN_FUNC_OSPI0_SS,
PIN_FUNC_QSPI0,
PIN_FUNC_QSPI0_FBCLK,
PIN_FUNC_QSPI0_SS,
PIN_FUNC_TEST_CLK,
PIN_FUNC_TEST_SCAN,
PIN_FUNC_TAMPER_TRIGGER,
MAX_FUNCTION,
};
enum pm_pinctrl_config_param {
PINCTRL_CONFIG_SLEW_RATE,
PINCTRL_CONFIG_BIAS_STATUS,
PINCTRL_CONFIG_PULL_CTRL,
PINCTRL_CONFIG_SCHMITT_CMOS,
PINCTRL_CONFIG_DRIVE_STRENGTH,
PINCTRL_CONFIG_VOLTAGE_STATUS,
PINCTRL_CONFIG_TRI_STATE,
PINCTRL_CONFIG_MAX,
};
enum pm_pinctrl_slew_rate {
PINCTRL_SLEW_RATE_FAST,
PINCTRL_SLEW_RATE_SLOW,
};
enum pm_pinctrl_bias_status {
PINCTRL_BIAS_DISABLE,
PINCTRL_BIAS_ENABLE,
};
enum pm_pinctrl_pull_ctrl {
PINCTRL_BIAS_PULL_DOWN,
PINCTRL_BIAS_PULL_UP,
};
enum pm_pinctrl_schmitt_cmos {
PINCTRL_INPUT_TYPE_CMOS,
PINCTRL_INPUT_TYPE_SCHMITT,
};
enum pm_pinctrl_drive_strength {
PINCTRL_DRIVE_STRENGTH_TRISTATE,
PINCTRL_DRIVE_STRENGTH_4MA,
PINCTRL_DRIVE_STRENGTH_8MA,
PINCTRL_DRIVE_STRENGTH_12MA,
PINCTRL_DRIVE_STRENGTH_MAX,
};
enum pm_pinctrl_tri_state {
PINCTRL_TRI_STATE_DISABLE,
PINCTRL_TRI_STATE_ENABLE,
};
enum pm_ioctl_id {
IOCTL_GET_RPU_OPER_MODE,
IOCTL_SET_RPU_OPER_MODE,
IOCTL_RPU_BOOT_ADDR_CONFIG,
IOCTL_TCM_COMB_CONFIG,
IOCTL_SET_TAPDELAY_BYPASS,
IOCTL_SET_SGMII_MODE,
IOCTL_SD_DLL_RESET,
IOCTL_SET_SD_TAPDELAY,
/* Ioctl for clock driver */
IOCTL_SET_PLL_FRAC_MODE,
IOCTL_GET_PLL_FRAC_MODE,
IOCTL_SET_PLL_FRAC_DATA,
IOCTL_GET_PLL_FRAC_DATA,
IOCTL_WRITE_GGS,
IOCTL_READ_GGS,
IOCTL_WRITE_PGGS,
IOCTL_READ_PGGS,
/* IOCTL for ULPI reset */
IOCTL_ULPI_RESET,
/* Set healthy bit value */
IOCTL_SET_BOOT_HEALTH_STATUS,
IOCTL_AFI,
/* Probe counter read/write */
IOCTL_PROBE_COUNTER_READ,
IOCTL_PROBE_COUNTER_WRITE,
/* Ospi mux select */
IOCTL_OSPI_MUX_SELECT,
/* USB PMU state req */
IOCTL_USB_SET_STATE,
};
/* PLL parameters */
enum XPm_PllConfigParams {
PM_PLL_PARAM_ID_DIV2,
PM_PLL_PARAM_ID_FBDIV,
PM_PLL_PARAM_ID_DATA,
PM_PLL_PARAM_ID_PRE_SRC,
PM_PLL_PARAM_ID_POST_SRC,
PM_PLL_PARAM_ID_LOCK_DLY,
PM_PLL_PARAM_ID_LOCK_CNT,
PM_PLL_PARAM_ID_LFHF,
PM_PLL_PARAM_ID_CP,
PM_PLL_PARAM_ID_RES,
PM_PLL_PARAM_MAX,
};
/* PLL modes */
enum XPmPllMode {
PM_PLL_MODE_INTEGER = (0U),
PM_PLL_MODE_FRACTIONAL = (1U),
PM_PLL_MODE_RESET = (2U),
};
/**
* PM init node functions
*/
enum XPmInitFunctions {
FUNC_INIT_START,
FUNC_INIT_FINISH,
FUNC_SCAN_CLEAR,
FUNC_BISR,
FUNC_LBIST,
FUNC_MEM_INIT,
FUNC_MBIST_CLEAR,
FUNC_HOUSECLEAN_PL,
FUNC_HOUSECLEAN_COMPLETE,
FUNC_XPPU_CTRL,
};
/**
* PM operating characteristic types enumeration.
*/
enum XPmOpCharType {
PM_OPCHAR_TYPE_POWER = 1,
PM_OPCHAR_TYPE_TEMP,
PM_OPCHAR_TYPE_LATENCY,
};
/**
* PM notify events enumeration.
*/
enum XPmNotifyEvent {
EVENT_STATE_CHANGE = 1,
EVENT_ZERO_USERS = 2,
};
/* System shutdown macros */
#define PM_SHUTDOWN_TYPE_SHUTDOWN (0U)
#define PM_SHUTDOWN_TYPE_RESET (1U)
#define PM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM (0U)
#define PM_SHUTDOWN_SUBTYPE_RST_PS_ONLY (1U)
#define PM_SHUTDOWN_SUBTYPE_RST_SYSTEM (2U)
/* State arguments of the self suspend */
#define PM_SUSPEND_STATE_CPU_IDLE 0x0U
#define PM_SUSPEND_STATE_SUSPEND_TO_RAM 0xFU
/* RPU operation mode */
#define XPM_RPU_MODE_LOCKSTEP 0U
#define XPM_RPU_MODE_SPLIT 1U
/* RPU Boot memory */
#define XPM_RPU_BOOTMEM_LOVEC (0U)
#define XPM_RPU_BOOTMEM_HIVEC (1U)
/* RPU TCM mode */
#define XPM_RPU_TCM_SPLIT 0U
#define XPM_RPU_TCM_COMB 1U
/* Boot health status mask */
#define XPM_BOOT_HEALTH_STATUS_MASK (0x1U)
/* Tap delay signal type */
#define XPM_TAPDELAY_QSPI (2U)
/* Tap delay bypass */
#define XPM_TAPDELAY_BYPASS_DISABLE (0U)
#define XPM_TAPDELAY_BYPASS_ENABLE (1U)
/* Ospi AXI Mux select */
#define XPM_OSPI_MUX_SEL_DMA (0U)
#define XPM_OSPI_MUX_SEL_LINEAR (1U)
#define XPM_OSPI_MUX_GET_MODE (2U)
/* Tap delay type */
#define XPM_TAPDELAY_INPUT (0U)
#define XPM_TAPDELAY_OUTPUT (1U)
/* Dll reset type */
#define XPM_DLL_RESET_ASSERT (0U)
#define XPM_DLL_RESET_RELEASE (1U)
#define XPM_DLL_RESET_PULSE (2U)
/* Probe Counter Type */
#define XPM_PROBE_COUNTER_TYPE_LAR_LSR (0U)
#define XPM_PROBE_COUNTER_TYPE_MAIN_CTL (1U)
#define XPM_PROBE_COUNTER_TYPE_CFG_CTL (2U)
#define XPM_PROBE_COUNTER_TYPE_STATE_PERIOD (3U)
#define XPM_PROBE_COUNTER_TYPE_PORT_SEL (4U)
#define XPM_PROBE_COUNTER_TYPE_SRC (5U)
#define XPM_PROBE_COUNTER_TYPE_VAL (6U)
/* PM API versions */
#define XST_API_BASE_VERSION (1U)
#define XST_API_QUERY_DATA_VERSION (2U)
/* PM API ids */
#define PM_GET_API_VERSION 1U
#define PM_SET_CONFIGURATION 2U
#define PM_GET_NODE_STATUS 3U
#define PM_GET_OP_CHARACTERISTIC 4U
#define PM_REGISTER_NOTIFIER 5U
#define PM_REQUEST_SUSPEND 6U
#define PM_SELF_SUSPEND 7U
#define PM_FORCE_POWERDOWN 8U
#define PM_ABORT_SUSPEND 9U
#define PM_REQUEST_WAKEUP 10U
#define PM_SET_WAKEUP_SOURCE 11U
#define PM_SYSTEM_SHUTDOWN 12U
#define PM_REQUEST_NODE 13U
#define PM_RELEASE_NODE 14U
#define PM_SET_REQUIREMENT 15U
#define PM_SET_MAX_LATENCY 16U
#define PM_RESET_ASSERT 17U
#define PM_RESET_GET_STATUS 18U
#define PM_MMIO_WRITE 19U
#define PM_MMIO_READ 20U
#define PM_INIT_FINALIZE 21U
#define PM_FPGA_LOAD 22U
#define PM_FPGA_GET_STATUS 23U
#define PM_GET_CHIPID 24U
#define PM_SECURE_RSA_AES 25U
#define PM_SECURE_SHA 26U
#define PM_SECURE_RSA 27U
#define PM_PINCTRL_REQUEST 28U
#define PM_PINCTRL_RELEASE 29U
#define PM_PINCTRL_GET_FUNCTION 30U
#define PM_PINCTRL_SET_FUNCTION 31U
#define PM_PINCTRL_CONFIG_PARAM_GET 32U
#define PM_PINCTRL_CONFIG_PARAM_SET 33U
#define PM_IOCTL 34U
#define PM_QUERY_DATA 35U
#define PM_CLOCK_ENABLE 36U
#define PM_CLOCK_DISABLE 37U
#define PM_CLOCK_GETSTATE 38U
#define PM_CLOCK_SETDIVIDER 39U
#define PM_CLOCK_GETDIVIDER 40U
#define PM_CLOCK_SETRATE 41U
#define PM_CLOCK_GETRATE 42U
#define PM_CLOCK_SETPARENT 43U
#define PM_CLOCK_GETPARENT 44U
#define PM_SECURE_IMAGE 45U
#define PM_FPGA_READ 46U
#define PM_PLL_SET_PARAMETER 48U
#define PM_PLL_GET_PARAMETER 49U
#define PM_PLL_SET_MODE 50U
#define PM_PLL_GET_MODE 51U
#define PM_REGISTER_ACCESS 52U
#define PM_EFUSE_ACCESS 53U
#define PM_ADD_SUBSYSTEM 54U
#define PM_DESTROY_SUBSYSTEM 55U
#define PM_DESCRIBE_NODES 56U
#define PM_ADD_NODE 57U
#define PM_ADD_NODE_PARENT 58U
#define PM_ADD_NODE_NAME 59U
#define PM_ADD_REQUIREMENT 60U
#define PM_SET_CURRENT_SUBSYSTEM 61U
#define PM_INIT_NODE 62U
#define PM_FEATURE_CHECK 63U
#define PM_ISO_CONTROL 64U
#define PM_API_MIN PM_GET_API_VERSION
#define PM_API_MAX PM_ISO_CONTROL
#ifdef __cplusplus
}
#endif
#endif /* XPM_DEFS_H_ */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/rfdc_v8_0/src/xrfdc_intr.c
/******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrfdc_intr.c
* @addtogroup rfdc_v8_0
* @{
*
* This file contains functions related to RFdc interrupt handling.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.0 sk 05/16/17 First release
* 2.1 sk 09/15/17 Remove Libmetal library dependency for MB.
* 09/18/17 Add API to clear the interrupts.
* sk 09/21/17 Add support for Over voltage and Over
* Range interrupts.
* 2.2 sk 10/18/17 Add support for FIFO and DATA overflow interrupt
* 5.0 sk 08/24/18 Reorganize the code to improve readability and
* optimization.
* 5.1 cog 01/29/19 Replace structure reference ADC checks with
* function.
* 6.0 cog 02/20/19 Added handling for new ADC common mode over/under
* voltage interrupts.
* cog 02/20/19 XRFdc_GetIntrStatus now populates a pointer with the
* status and returns an error code.
* cog 02/20/19 XRFdc_IntrClr, XRFdc_IntrDisable and XRFdc_IntrEnable
* now return error codes.
* cog 03/25/19 The new common mode over/under voltage interrupts mask
* bits were clashing with other interrupt bits.
* 7.0 cog 05/13/19 Formatting changes.
* cog 05/13/19 Re-factor of interrupt clear/status handling.
* cog 05/13/19 Added handling for common power up interrupt.
* cog 07/29/19 Added XRFdc_GetEnabledInterrupts() API.
* cog 08/02/19 Formatting changes.
* 7.1 aad 12/01/19 Fixed static analysis errors.
* 12/20/19 Metal log messages are now more descriptive.
* cog 01/29/20 Fixed metal log typos.
* 8.0 cog 02/10/20 Updated addtogroup.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xrfdc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions ****************************/
/****************************************************************************/
/**
*
* This function sets the interrupt mask.
*
* @param InstancePtr is a pointer to the XRFdc instance
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param IntrMask contains the interrupts to be enabled.
* '1' enables an interrupt, and '0' disables.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if block not available.
*
* @note None.
*
*****************************************************************************/
u32 XRFdc_IntrEnable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask)
{
u32 BaseAddr;
u32 ReadReg;
u32 Index;
u32 NoOfBlocks;
u32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
ReadReg = XRFdc_ReadReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile_Id), XRFDC_INTR_ENABLE);
if ((IntrMask & XRFDC_COMMON_MASK) != 0U) {
ReadReg |= (XRFDC_COMMON_MASK >> XRFDC_COMMON_SHIFT);
XRFdc_WriteReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile_Id), XRFDC_INTR_ENABLE, ReadReg);
if ((IntrMask & ~XRFDC_COMMON_MASK) == XRFDC_DISABLED) {
Status = XRFDC_SUCCESS;
goto RETURN_PATH;
}
}
for (; Index < NoOfBlocks; Index++) {
ReadReg = XRFdc_ReadReg16(InstancePtr, 0x0, XRFDC_COMMON_INTR_ENABLE);
if (Type == XRFDC_ADC_TILE) {
ReadReg |= (1U << (Tile_Id + 4));
XRFdc_WriteReg16(InstancePtr, 0x0, XRFDC_COMMON_INTR_ENABLE, ReadReg);
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_INTR_ENABLE, (1U << Index), (1U << Index));
/* Enable Converter interrupts */
ReadReg = XRFdc_ReadReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_EN(Index));
if ((IntrMask & XRFDC_ADC_OVR_VOLTAGE_MASK) != 0U) {
ReadReg |= (XRFDC_ADC_OVR_VOLTAGE_MASK >> XRFDC_ADC_OVR_VOL_RANGE_SHIFT);
}
if ((IntrMask & XRFDC_ADC_OVR_RANGE_MASK) != 0U) {
ReadReg |= (XRFDC_ADC_OVR_RANGE_MASK >> XRFDC_ADC_OVR_VOL_RANGE_SHIFT);
}
if ((IntrMask & XRFDC_ADC_FIFO_OVR_MASK) != 0U) {
ReadReg |= (XRFDC_ADC_FIFO_OVR_MASK >> XRFDC_ADC_DAT_FIFO_OVR_SHIFT);
}
if ((IntrMask & XRFDC_ADC_DAT_OVR_MASK) != 0U) {
ReadReg |= (XRFDC_ADC_DAT_OVR_MASK >> XRFDC_ADC_DAT_FIFO_OVR_SHIFT);
}
if ((IntrMask & XRFDC_ADC_CMODE_OVR_MASK) != 0U) {
ReadReg |= (XRFDC_ADC_CMODE_OVR_MASK >> XRFDC_ADC_CMODE_SHIFT);
}
if ((IntrMask & XRFDC_ADC_CMODE_UNDR_MASK) != 0U) {
ReadReg |= (XRFDC_ADC_CMODE_UNDR_MASK >> XRFDC_ADC_CMODE_SHIFT);
}
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_EN(Index), ReadReg);
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
/* Check for FIFO interface interrupts */
if ((IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK) != 0U) {
ReadReg = (IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_IMR_OFFSET,
XRFDC_IXR_FIFOUSRDAT_MASK, ReadReg);
}
/* Check for SUBADC interrupts */
if ((IntrMask & XRFDC_SUBADC_IXR_DCDR_MASK) != 0U) {
ReadReg = (IntrMask & XRFDC_SUBADC_IXR_DCDR_MASK) >> XRFDC_ADC_SUBADC_DCDR_SHIFT;
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_DEC_IMR_OFFSET, XRFDC_DEC_IMR_MASK,
ReadReg);
}
/* Check for DataPath interrupts */
if ((IntrMask & XRFDC_ADC_IXR_DATAPATH_MASK) != 0U) {
ReadReg = (IntrMask & XRFDC_ADC_IXR_DATAPATH_MASK) >> XRFDC_DATA_PATH_SHIFT;
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DATPATH_IMR_OFFSET, XRFDC_ADC_DAT_IMR_MASK,
ReadReg);
}
} else {
ReadReg |= (1U << Tile_Id);
XRFdc_WriteReg16(InstancePtr, 0x0, XRFDC_COMMON_INTR_ENABLE, ReadReg);
BaseAddr = XRFDC_DAC_TILE_CTRL_STATS_ADDR(Tile_Id);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_INTR_ENABLE, (1U << Index), (1U << Index));
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
/* Check for FIFO interface interrupts */
if ((IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK) != 0U) {
ReadReg = (IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DAC_FABRIC_IMR_OFFSET,
XRFDC_IXR_FIFOUSRDAT_MASK, ReadReg);
}
if ((IntrMask & XRFDC_DAC_IXR_DATAPATH_MASK) != 0U) {
ReadReg = (IntrMask & XRFDC_DAC_IXR_DATAPATH_MASK) >> XRFDC_DATA_PATH_SHIFT;
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_DATPATH_IMR_OFFSET, XRFDC_DAC_DAT_IMR_MASK,
ReadReg);
}
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/****************************************************************************/
/**
*
* This function clears the interrupt mask.
*
* @param InstancePtr is a pointer to the XRFdc instance
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param IntrMask contains the interrupts to be disabled.
* '1' disables an interrupt, and '0' remains no change.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if block not available.
*
* @note None.
*
*****************************************************************************/
u32 XRFdc_IntrDisable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask)
{
u32 BaseAddr;
u32 ReadReg;
u32 Status;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
ReadReg = XRFdc_ReadReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile_Id), XRFDC_INTR_ENABLE);
if ((IntrMask & XRFDC_COMMON_MASK) != 0U) {
ReadReg &= ~(XRFDC_COMMON_MASK >> XRFDC_COMMON_SHIFT);
XRFdc_WriteReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile_Id), XRFDC_INTR_ENABLE, ReadReg);
}
for (; Index < NoOfBlocks; Index++) {
if (Type == XRFDC_ADC_TILE) {
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
/* Check for Over Voltage and Over Range */
ReadReg = XRFdc_ReadReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_EN(Index));
if ((IntrMask & XRFDC_ADC_OVR_VOLTAGE_MASK) != 0U) {
ReadReg &= ~(XRFDC_ADC_OVR_VOLTAGE_MASK >> XRFDC_ADC_OVR_VOL_RANGE_SHIFT);
}
if ((IntrMask & XRFDC_ADC_OVR_RANGE_MASK) != 0U) {
ReadReg &= ~(XRFDC_ADC_OVR_RANGE_MASK >> XRFDC_ADC_OVR_VOL_RANGE_SHIFT);
}
/* Disable Converter interrupts */
if ((IntrMask & XRFDC_ADC_FIFO_OVR_MASK) != 0U) {
ReadReg &= ~(XRFDC_ADC_FIFO_OVR_MASK >> XRFDC_ADC_DAT_FIFO_OVR_SHIFT);
}
if ((IntrMask & XRFDC_ADC_DAT_OVR_MASK) != 0U) {
ReadReg &= ~(XRFDC_ADC_DAT_OVR_MASK >> XRFDC_ADC_DAT_FIFO_OVR_SHIFT);
}
if ((IntrMask & XRFDC_ADC_CMODE_OVR_MASK) != 0U) {
ReadReg &= ~(XRFDC_ADC_CMODE_OVR_MASK >> XRFDC_ADC_CMODE_SHIFT);
}
if ((IntrMask & XRFDC_ADC_CMODE_UNDR_MASK) != 0U) {
ReadReg &= ~(XRFDC_ADC_CMODE_UNDR_MASK >> XRFDC_ADC_CMODE_SHIFT);
}
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_EN(Index), ReadReg);
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
/* Check for FIFO interface interrupts */
if ((IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK) != 0U) {
ReadReg = IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK;
XRFdc_ClrReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_IMR_OFFSET, ReadReg);
}
/* Check for SUBADC interrupts */
if ((IntrMask & XRFDC_SUBADC_IXR_DCDR_MASK) != 0U) {
ReadReg = ((IntrMask & XRFDC_SUBADC_IXR_DCDR_MASK) >> XRFDC_ADC_SUBADC_DCDR_SHIFT);
XRFdc_ClrReg(InstancePtr, BaseAddr, XRFDC_ADC_DEC_IMR_OFFSET, ReadReg);
}
/* Check for DataPath interrupts */
if ((IntrMask & XRFDC_ADC_IXR_DATAPATH_MASK) != 0U) {
ReadReg = ((IntrMask & XRFDC_ADC_IXR_DATAPATH_MASK) >> XRFDC_DATA_PATH_SHIFT);
XRFdc_ClrReg(InstancePtr, BaseAddr, XRFDC_DATPATH_IMR_OFFSET, ReadReg);
}
} else {
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
/* Check for FIFO interface interrupts */
if ((IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK) != 0U) {
ReadReg = (IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK);
XRFdc_ClrReg(InstancePtr, BaseAddr, XRFDC_DAC_FABRIC_IMR_OFFSET, ReadReg);
}
/* Check for FIFO DataPath interrupts */
if ((IntrMask & XRFDC_DAC_IXR_DATAPATH_MASK) != 0U) {
ReadReg = ((IntrMask & XRFDC_DAC_IXR_DATAPATH_MASK) >> XRFDC_DATA_PATH_SHIFT);
XRFdc_ClrReg(InstancePtr, BaseAddr, XRFDC_DATPATH_IMR_OFFSET, ReadReg);
}
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/****************************************************************************/
/**
*
* This function gets a mask of enabled interrupts.
*
* @param InstancePtr is a pointer to the XRFdc instance
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param IntrMask is a pointer to the mask of enabled interrupts.
* '1' denotes an enabled interrupt, and '0' denotes a disabled
* interrupt.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if block not available.
*
* @note None.
*
*****************************************************************************/
u32 XRFdc_GetEnabledInterrupts(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *IntrMask)
{
u32 BaseAddr;
u32 ReadReg;
u32 Index;
u32 NoOfBlocks;
u32 Status;
u32 TileIdMask;
u32 BlockIntrEn;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Xil_AssertNonvoid(IntrMask != NULL);
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
*IntrMask = 0;
ReadReg = XRFdc_ReadReg16(InstancePtr, XRFDC_IP_BASE, XRFDC_COMMON_INTR_ENABLE);
TileIdMask = XRFDC_ENABLED << XRFDC_TILE_GLBL_ADDR(Type, Tile_Id);
if ((ReadReg & TileIdMask) == XRFDC_DISABLED) {
metal_log(METAL_LOG_DEBUG, "\n Tile interrupt bit not set for %s %u in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
Status = XRFDC_SUCCESS;
goto RETURN_PATH;
}
BlockIntrEn = XRFdc_ReadReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile_Id), XRFDC_INTR_ENABLE);
if (BlockIntrEn & (XRFDC_COMMON_MASK >> XRFDC_COMMON_SHIFT)) {
*IntrMask |= XRFDC_COMMON_MASK;
}
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == XRFDC_ENABLED) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
if ((BlockIntrEn & (XRFDC_ENABLED << Index)) == XRFDC_DISABLED) {
continue;
}
if (Type == XRFDC_ADC_TILE) {
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
/* Get Converter interrupts */
ReadReg = XRFdc_ReadReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_EN(Index));
if (ReadReg & (XRFDC_ADC_OVR_VOLTAGE_MASK >> XRFDC_ADC_OVR_VOL_RANGE_SHIFT)) {
*IntrMask |= XRFDC_ADC_OVR_VOLTAGE_MASK;
}
if (ReadReg & (XRFDC_ADC_OVR_RANGE_MASK >> XRFDC_ADC_OVR_VOL_RANGE_SHIFT)) {
*IntrMask |= XRFDC_ADC_OVR_RANGE_MASK;
}
if (ReadReg & (XRFDC_ADC_FIFO_OVR_MASK >> XRFDC_ADC_DAT_FIFO_OVR_SHIFT)) {
*IntrMask |= XRFDC_ADC_FIFO_OVR_MASK;
}
if (ReadReg & (XRFDC_ADC_DAT_OVR_MASK >> XRFDC_ADC_DAT_FIFO_OVR_SHIFT)) {
*IntrMask |= XRFDC_ADC_DAT_OVR_MASK;
}
if (ReadReg & (XRFDC_ADC_CMODE_OVR_MASK >> XRFDC_ADC_CMODE_SHIFT)) {
*IntrMask |= XRFDC_ADC_CMODE_OVR_MASK;
}
if (ReadReg & (XRFDC_ADC_CMODE_UNDR_MASK >> XRFDC_ADC_CMODE_SHIFT)) {
*IntrMask |= XRFDC_ADC_CMODE_UNDR_MASK;
}
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
/* Check for FIFO interface interrupts */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_IMR_OFFSET);
if (ReadReg & XRFDC_IXR_FIFOUSRDAT_MASK) {
*IntrMask |= XRFDC_IXR_FIFOUSRDAT_MASK;
}
/* Check for SUBADC interrupts */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_DEC_IMR_OFFSET);
if (ReadReg & XRFDC_DEC_IMR_MASK) {
*IntrMask |= XRFDC_SUBADC_IXR_DCDR_MASK;
}
/* Check for DataPath interrupts */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DATPATH_IMR_OFFSET);
if (ReadReg & XRFDC_ADC_DAT_IMR_MASK) {
*IntrMask |= XRFDC_ADC_IXR_DATAPATH_MASK;
}
} else {
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
/* Check for FIFO interface interrupts */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DAC_FABRIC_IMR_OFFSET);
if (ReadReg & XRFDC_IXR_FIFOUSRDAT_MASK) {
*IntrMask |= XRFDC_IXR_FIFOUSRDAT_MASK;
}
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DATPATH_IMR_OFFSET);
if (ReadReg & XRFDC_DAC_DAT_IMR_MASK) {
*IntrMask |= XRFDC_DAC_IXR_DATAPATH_MASK;
}
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/****************************************************************************/
/**
*
* This function returns the interrupt status read from Interrupt Status
* Register(ISR).
*
* @param InstancePtr is a pointer to the XRFdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param IntrStsPtr is pointer to a32-bit value representing the contents of
* the Interrupt Status Registers (FIFO interface, Decoder interface,
* Data Path Interface).
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if block not available.
*
* @note None.
*
*****************************************************************************/
u32 XRFdc_GetIntrStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *IntrStsPtr)
{
u32 BaseAddr;
u32 ReadReg;
u32 Status;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(IntrStsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
*IntrStsPtr = 0;
ReadReg = XRFdc_ReadReg16(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile_Id), XRFDC_INTR_STS);
*IntrStsPtr |= ((ReadReg & XRFDC_INTR_COMMON_MASK) << XRFDC_COMMON_SHIFT);
for (; Index < NoOfBlocks; Index++) {
if (Type == XRFDC_ADC_TILE) {
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
/* Check for Over Voltage and Over Range */
ReadReg = XRFdc_ReadReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_STS(Index));
*IntrStsPtr |= ((ReadReg & XRFDC_INTR_OVR_VOLTAGE_MASK) << XRFDC_ADC_OVR_VOL_RANGE_SHIFT);
*IntrStsPtr |= ((ReadReg & XRFDC_INTR_OVR_RANGE_MASK) << XRFDC_ADC_OVR_VOL_RANGE_SHIFT);
*IntrStsPtr |= ((ReadReg & XRFDC_INTR_FIFO_OVR_MASK) << XRFDC_ADC_DAT_FIFO_OVR_SHIFT);
*IntrStsPtr |= ((ReadReg & XRFDC_INTR_DAT_OVR_MASK) << XRFDC_ADC_DAT_FIFO_OVR_SHIFT);
/* Check for Common Mode Over/Under Voltage */
*IntrStsPtr |= ((ReadReg & XRFDC_INTR_CMODE_OVR_MASK) << XRFDC_ADC_CMODE_SHIFT);
*IntrStsPtr |= ((ReadReg & XRFDC_INTR_CMODE_UNDR_MASK) << XRFDC_ADC_CMODE_SHIFT);
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
/* Check for FIFO interface interrupts */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_ISR_OFFSET);
*IntrStsPtr |= (ReadReg & XRFDC_IXR_FIFOUSRDAT_MASK);
/* Check for SUBADC interrupts */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_DEC_ISR_OFFSET);
*IntrStsPtr |= ((ReadReg & XRFDC_DEC_ISR_SUBADC_MASK) << XRFDC_ADC_SUBADC_DCDR_SHIFT);
/* Check for DataPath interrupts */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DATPATH_ISR_OFFSET);
*IntrStsPtr |= ((ReadReg & XRFDC_ADC_DAT_PATH_ISR_MASK) << XRFDC_DATA_PATH_SHIFT);
} else {
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
/* Check for FIFO interface interrupts */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DAC_FABRIC_ISR_OFFSET);
*IntrStsPtr |= (ReadReg & XRFDC_IXR_FIFOUSRDAT_MASK);
/* Check for DataPath interrupts */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DATPATH_ISR_OFFSET);
*IntrStsPtr |= ((ReadReg & XRFDC_DAC_DAT_PATH_ISR_MASK) << XRFDC_DATA_PATH_SHIFT);
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/****************************************************************************/
/**
*
* This function clear the interrupts.
*
* @param InstancePtr is a pointer to the XRFdc instance
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3, and -1.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param IntrMask contains the interrupts to be cleared.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if block not available.
*
* @note None.
*
*****************************************************************************/
u32 XRFdc_IntrClr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask)
{
u32 BaseAddr;
u32 Status;
u32 Index;
u32 NoOfBlocks;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckBlockEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n %s %u block %u not available in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
if (Type == XRFDC_ADC_TILE) {
/* ADC */
BaseAddr = XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile_Id);
/* Check for Converter interrupts */
if ((IntrMask & XRFDC_ADC_OVR_VOLTAGE_MASK) != 0U) {
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_STS(Index),
(IntrMask & XRFDC_ADC_OVR_VOLTAGE_MASK) >>
XRFDC_ADC_OVR_VOL_RANGE_SHIFT);
}
if ((IntrMask & XRFDC_ADC_OVR_RANGE_MASK) != 0U) {
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_STS(Index),
(IntrMask & XRFDC_ADC_OVR_RANGE_MASK) >> XRFDC_ADC_OVR_VOL_RANGE_SHIFT);
}
if ((IntrMask & XRFDC_ADC_FIFO_OVR_MASK) != 0U) {
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_STS(Index),
(IntrMask & XRFDC_ADC_FIFO_OVR_MASK) >> XRFDC_ADC_DAT_FIFO_OVR_SHIFT);
}
if ((IntrMask & XRFDC_ADC_DAT_OVR_MASK) != 0U) {
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_STS(Index),
(IntrMask & XRFDC_ADC_DAT_OVR_MASK) >> XRFDC_ADC_DAT_FIFO_OVR_SHIFT);
}
if ((IntrMask & XRFDC_ADC_CMODE_OVR_MASK) != 0U) {
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_STS(Index),
(IntrMask & XRFDC_ADC_CMODE_OVR_MASK) >> XRFDC_ADC_CMODE_SHIFT);
}
if ((IntrMask & XRFDC_ADC_CMODE_UNDR_MASK) != 0U) {
XRFdc_WriteReg(InstancePtr, BaseAddr, XRFDC_CONV_INTR_STS(Index),
(IntrMask & XRFDC_ADC_CMODE_UNDR_MASK) >> XRFDC_ADC_CMODE_SHIFT);
}
BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
/* Check for FIFO interface interrupts */
if ((IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK) != 0U) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_ISR_OFFSET,
(IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK));
}
/* Check for SUBADC interrupts */
if ((IntrMask & XRFDC_SUBADC_IXR_DCDR_MASK) != 0U) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_DEC_ISR_OFFSET,
(u16)((IntrMask & XRFDC_SUBADC_IXR_DCDR_MASK) >>
XRFDC_ADC_SUBADC_DCDR_SHIFT));
}
/* Check for DataPath interrupts */
if ((IntrMask & XRFDC_ADC_IXR_DATAPATH_MASK) != 0U) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_DATPATH_ISR_OFFSET,
(u16)(IntrMask & XRFDC_ADC_IXR_DATAPATH_MASK) >>
XRFDC_DATA_PATH_SHIFT);
}
} else {
/* DAC */
BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Index);
/* Check for FIFO interface interrupts */
if ((IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK) != 0U) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_DAC_FABRIC_ISR_OFFSET,
(u16)(IntrMask & XRFDC_IXR_FIFOUSRDAT_MASK));
}
/* Check for DataPath interrupts */
if ((IntrMask & XRFDC_DAC_IXR_DATAPATH_MASK) != 0U) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_DATPATH_ISR_OFFSET,
(u16)(IntrMask & XRFDC_DAC_IXR_DATAPATH_MASK) >>
XRFDC_DATA_PATH_SHIFT);
}
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/****************************************************************************/
/**
*
* This function is the interrupt handler for the driver.
* It must be connected to an interrupt system by the application such that it
* can be called when an interrupt occurs.
*
* @param Vector is interrupt vector number. Libmetal status handler
* expects two parameters in the handler prototype, hence
* kept this parameter. This is not used inside
* the interrupt handler API.
* @param XRFdcPtr contains a pointer to the driver instance
*
* @note None.
*
* @note Vector param is not useful inside the interrupt handler, hence
* typecast with void to remove compilation warning.
*
******************************************************************************/
u32 XRFdc_IntrHandler(u32 Vector, void *XRFdcPtr)
{
XRFdc *InstancePtr = (XRFdc *)XRFdcPtr;
u32 Intrsts = 0x0U;
u32 Tile_Id = XRFDC_TILE_ID_INV;
s32 Block_Id;
u32 ReadReg;
u16 Type = 0U;
u32 BaseAddr;
u32 IntrMask = 0x0U;
u32 Block = XRFDC_BLK_ID_INV;
Xil_AssertNonvoid(InstancePtr != NULL);
(void)Vector;
/*
* Read the interrupt ID register to determine which
* interrupt is active
*/
ReadReg = XRFdc_ReadReg16(InstancePtr, 0x0, XRFDC_COMMON_INTR_STS);
if ((ReadReg & XRFDC_EN_INTR_DAC_TILE0_MASK) != 0U) {
Type = XRFDC_DAC_TILE;
Tile_Id = XRFDC_TILE_ID0;
} else if ((ReadReg & XRFDC_EN_INTR_DAC_TILE1_MASK) != 0U) {
Type = XRFDC_DAC_TILE;
Tile_Id = XRFDC_TILE_ID1;
} else if ((ReadReg & XRFDC_EN_INTR_DAC_TILE2_MASK) != 0U) {
Type = XRFDC_DAC_TILE;
Tile_Id = XRFDC_TILE_ID2;
} else if ((ReadReg & XRFDC_EN_INTR_DAC_TILE3_MASK) != 0U) {
Type = XRFDC_DAC_TILE;
Tile_Id = XRFDC_TILE_ID3;
} else if ((ReadReg & XRFDC_EN_INTR_ADC_TILE0_MASK) != 0U) {
Type = XRFDC_ADC_TILE;
Tile_Id = XRFDC_TILE_ID0;
} else if ((ReadReg & XRFDC_EN_INTR_ADC_TILE1_MASK) != 0U) {
Type = XRFDC_ADC_TILE;
Tile_Id = XRFDC_TILE_ID1;
} else if ((ReadReg & XRFDC_EN_INTR_ADC_TILE2_MASK) != 0U) {
Type = XRFDC_ADC_TILE;
Tile_Id = XRFDC_TILE_ID2;
} else if ((ReadReg & XRFDC_EN_INTR_ADC_TILE3_MASK) != 0U) {
Type = XRFDC_ADC_TILE;
Tile_Id = XRFDC_TILE_ID3;
} else {
metal_log(METAL_LOG_DEBUG, "\n Invalid Tile_Id \r\n");
goto END_OF_BLOCK_LEVEL;
}
BaseAddr = XRFDC_CTRL_STS_BASE(Type, Tile_Id);
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_INTR_STS);
if ((ReadReg & XRFDC_EN_INTR_SLICE0_MASK) != 0U) {
Block_Id = XRFDC_BLK_ID0;
} else if ((ReadReg & XRFDC_EN_INTR_SLICE1_MASK) != 0U) {
Block_Id = XRFDC_BLK_ID1;
} else if ((ReadReg & XRFDC_EN_INTR_SLICE2_MASK) != 0U) {
Block_Id = XRFDC_BLK_ID2;
} else if ((ReadReg & XRFDC_EN_INTR_SLICE3_MASK) != 0U) {
Block_Id = XRFDC_BLK_ID3;
} else if ((ReadReg & XRFDC_INTR_COMMON_MASK) != 0U) {
Block = XRFDC_BLK_ID_NONE;
IntrMask |= XRFDC_COMMON_MASK;
goto END_OF_BLOCK_LEVEL;
} else {
metal_log(METAL_LOG_DEBUG, "\n Invalid ADC Block_Id \r\n");
goto END_OF_BLOCK_LEVEL;
}
IntrMask |= (ReadReg & XRFDC_INTR_COMMON_MASK) << XRFDC_COMMON_SHIFT;
Block = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
if ((Block_Id == XRFDC_BLK_ID0) || (Block_Id == XRFDC_BLK_ID1)) {
Block = XRFDC_BLK_ID0;
} else {
Block = XRFDC_BLK_ID1;
}
}
(void)XRFdc_GetIntrStatus(InstancePtr, Type, Tile_Id, Block, &Intrsts);
if (Type == XRFDC_ADC_TILE) {
/* ADC */
if ((Intrsts & XRFDC_ADC_OVR_VOLTAGE_MASK) != 0U) {
IntrMask |= Intrsts & XRFDC_ADC_OVR_VOLTAGE_MASK;
metal_log(METAL_LOG_DEBUG, "\n ADC Over Voltage interrupt \r\n");
}
if ((Intrsts & XRFDC_ADC_OVR_RANGE_MASK) != 0U) {
IntrMask |= Intrsts & XRFDC_ADC_OVR_RANGE_MASK;
metal_log(METAL_LOG_DEBUG, "\n ADC Over Range interrupt \r\n");
}
if ((Intrsts & XRFDC_ADC_FIFO_OVR_MASK) != 0U) {
IntrMask |= Intrsts & XRFDC_ADC_FIFO_OVR_MASK;
metal_log(METAL_LOG_DEBUG, "\n ADC FIFO OF interrupt \r\n");
}
if ((Intrsts & XRFDC_ADC_DAT_OVR_MASK) != 0U) {
IntrMask |= Intrsts & XRFDC_ADC_DAT_OVR_MASK;
metal_log(METAL_LOG_DEBUG, "\n ADC DATA OF interrupt \r\n");
}
if ((Intrsts & XRFDC_ADC_CMODE_OVR_MASK) != 0U) {
IntrMask |= XRFDC_ADC_CMODE_OVR_MASK;
metal_log(METAL_LOG_DEBUG, "\n ADC CMODE OV interrupt \r\n");
}
if ((Intrsts & XRFDC_ADC_CMODE_UNDR_MASK) != 0U) {
IntrMask |= XRFDC_ADC_CMODE_UNDR_MASK;
metal_log(METAL_LOG_DEBUG, "\n ADC CMODE UV interrupt \r\n");
}
if ((Intrsts & XRFDC_IXR_FIFOUSRDAT_MASK) != 0U) {
IntrMask |= Intrsts & XRFDC_IXR_FIFOUSRDAT_MASK;
metal_log(METAL_LOG_DEBUG, "\n ADC FIFO interface interrupt \r\n");
}
if ((Intrsts & XRFDC_SUBADC_IXR_DCDR_MASK) != 0U) {
IntrMask |= Intrsts & XRFDC_SUBADC_IXR_DCDR_MASK;
metal_log(METAL_LOG_DEBUG, "\n ADC Decoder interface interrupt \r\n");
}
if ((Intrsts & XRFDC_ADC_IXR_DATAPATH_MASK) != 0U) {
IntrMask |= Intrsts & XRFDC_ADC_IXR_DATAPATH_MASK;
metal_log(METAL_LOG_DEBUG, "\n ADC Data Path interface interrupt \r\n");
}
} else {
/* DAC */
if ((Intrsts & XRFDC_IXR_FIFOUSRDAT_MASK) != 0U) {
IntrMask |= Intrsts & XRFDC_IXR_FIFOUSRDAT_MASK;
metal_log(METAL_LOG_DEBUG, "\n DAC FIFO interface interrupt \r\n");
}
if ((Intrsts & XRFDC_DAC_IXR_DATAPATH_MASK) != 0U) {
IntrMask |= Intrsts & XRFDC_DAC_IXR_DATAPATH_MASK;
metal_log(METAL_LOG_DEBUG, "\n DAC Data Path interface interrupt \r\n");
}
}
/* Clear the interrupt */
if (Type == XRFDC_ADC_TILE) {
/* ADC */
XRFdc_IntrClr(InstancePtr, XRFDC_ADC_TILE, Tile_Id, Block, Intrsts);
} else {
/* DAC */
XRFdc_IntrClr(InstancePtr, XRFDC_DAC_TILE, Tile_Id, Block, Intrsts);
}
END_OF_BLOCK_LEVEL:
InstancePtr->StatusHandler(InstancePtr->CallBackRef, Type, Tile_Id, Block, IntrMask);
return (u32)METAL_IRQ_HANDLED;
}
/*****************************************************************************/
/**
*
* This function sets the status callback function, the status handler, which the
* driver calls when it encounters conditions that should be reported to the
* higher layer software. The handler executes in an interrupt context, so
* the amount of processing should be minimized
*
*
* @param InstancePtr is a pointer to the XRFdc instance.
* @param CallBackRef is the upper layer callback reference passed back
* when the callback function is invoked.
* @param FunctionPtr is the pointer to the callback function.
*
* @note None.
*
* @note The handler is called within interrupt context, so it should finish
* its work quickly.
*
******************************************************************************/
void XRFdc_SetStatusHandler(XRFdc *InstancePtr, void *CallBackRef, XRFdc_StatusHandler FunctionPtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FunctionPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XRFDC_COMPONENT_IS_READY);
InstancePtr->StatusHandler = FunctionPtr;
InstancePtr->CallBackRef = CallBackRef;
}
/** @} */
<file_sep>/python_drivers/alice_single_stream_test.py
# -*- coding: utf-8 -*-
"""
Created on Fri Jul 24 13:33:35 2020
@author: tianlab01
"""
import time
import time_sync
import james_utils
import tdc_wrapper
import random
server_ip = "192.168.56.1"
tdc = tdc_wrapper.tdc_wrapper(3,0,tdc_wrapper.MODE_CLIENT,"192.168.56.1")
ts = time_sync.time_sync(james_utils.ALICE_PORT, server_ip, time_sync.CLIENT, tdc)
#is working and tested
#bin_size = 16000 #in ps
#bin_number = 4#can encode values between 0 and 15
#period = 64000 #in ps
#Faster with 16 bins
bin_size = 80000 #in ps
bin_number = 16#can encode values between 0 and 15
period = 1400000 #in ps
num_sync_pulse = 200
num_dead_pulse = 200
test_stream = [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
#test_stream = [0,1,2,3,0,1,2,3,0,1,2,3]
res = 0
res += ts.set_bin_size(bin_size)
res += ts.set_bin_number(bin_number)
res += ts.set_period(period)
if(res):
print("Failed to set encoding parameters, aborting..")
else:
res = ts.send_stream(test_stream, num_sync_pulse, num_dead_pulse)
if(res == -1):
print("Stream transmission failed, exiting")
else:
print("Stream transmission success")
sent_str = "Sent: "
for i in test_stream:
sent_str += str(i) + ", "
res_str = "Got: "
for i in res:
res_str += str(i) + ", "
print(sent_str)
print(res_str)
succ = 1
if(len(test_stream) == len(res)):
for i in range(0, len(test_stream)):
if(test_stream[i] != res[i]):
succ = 0
break
else:
succ = 0
if(succ):
print("Stream decoded successfully by Bob!")
else:
print("Bob did not correctly decode stream")
#file = open(logfile,'a')
#new_line = str(count) + ", " + str(rand_val) + ", " + str(ret_val) + ", " + str(error) + ", " + str(succ) + "\n"
#file.write(new_line)
#file.close()
print("Done.")
ts.board.close_board()
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/clockps_v1_2/src/xclockps_g.c
/******************************************************************************
* Copyright (C) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xclockps_g.c
* @addtogroup xclockps_v1_2
* @{
*
* This file contains a table that specifies the configuration of the clocking
* in the system. Each device should have an entry in the table.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------
* 1.00 cjp 02/09/18 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xclockps.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Prototypes ******************************/
/**
* This table contains configuration information for clocking device in
* the system.
*/
XClockPs_Config XClockPs_ConfigTable[XPAR_XCLOCKPS_NUM_INSTANCES] = {
{
(u16)XPAR_XCLOCKPS_DEVICE_ID,
}
};
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_periph.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_periph.h"
#include "xpm_gic_proxy.h"
static struct XPm_PeriphOps GenericOps = {
.SetWakeupSource = XPmGicProxy_WakeEventSet,
};
XStatus XPmPeriph_Init(XPm_Periph *Periph, u32 Id, u32 BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock,
XPm_ResetNode *Reset, u32 GicProxyMask,
u32 GicProxyGroup)
{
XStatus Status = XST_FAILURE;
Status = XPmDevice_Init(&Periph->Device, Id, BaseAddress, Power, Clock,
Reset);
if (XST_SUCCESS != Status) {
goto done;
}
Periph->PeriphOps = &GenericOps;
Periph->GicProxyMask = GicProxyMask;
Periph->GicProxyGroup = GicProxyGroup;
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/dpdma_v1_2/src/xdpdma_sinit.c
/*******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xdpdma_sinit.c
* @addtogroup dpdma_v1_2
* @{
*
* This file contains static initialization methods for the XDpDma driver.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 aad 01/20/15 Initial release.
* </pre>
*
*******************************************************************************/
/******************************* Include Files ********************************/
#include "xdpdma.h"
#include "xparameters.h"
/*************************** Variable Declarations ****************************/
/**
* A table of configuration structures containing the configuration information
* for each DisplayPort TX core in the system.
*/
extern XDpDma_Config XDpDma_ConfigTable[XPAR_XDPDMA_NUM_INSTANCES];
/**************************** Function Definitions ****************************/
/******************************************************************************/
/**
* This function looks for the device configuration based on the unique device
* ID. The table XDpDma_ConfigTable[] contains the configuration information for
* each device in the system.
*
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
*
*******************************************************************************/
XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId)
{
XDpDma_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0; Index < XPAR_XDPDMA_NUM_INSTANCES; Index++) {
if (XDpDma_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XDpDma_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/rpu.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _RPU_H_
#define _RPU_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* RPU Base Address
*/
#define RPU_BASEADDR ((u32)0XFF9A0000U)
/**
* Register: RPU_RPU_GLBL_CNTL
*/
#define RPU_RPU_GLBL_CNTL ( ( RPU_BASEADDR ) + ((u32)0X00000000U) )
#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_SHIFT 10
#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_WIDTH 1
#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_MASK ((u32)0X00000400U)
#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_SHIFT 8
#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_WIDTH 1
#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_MASK ((u32)0X00000100U)
#define RPU_RPU_GLBL_CNTL_TCM_WAIT_SHIFT 7
#define RPU_RPU_GLBL_CNTL_TCM_WAIT_WIDTH 1
#define RPU_RPU_GLBL_CNTL_TCM_WAIT_MASK ((u32)0X00000080U)
#define RPU_RPU_GLBL_CNTL_TCM_COMB_SHIFT 6
#define RPU_RPU_GLBL_CNTL_TCM_COMB_WIDTH 1
#define RPU_RPU_GLBL_CNTL_TCM_COMB_MASK ((u32)0X00000040U)
#define RPU_RPU_GLBL_CNTL_TEINIT_SHIFT 5
#define RPU_RPU_GLBL_CNTL_TEINIT_WIDTH 1
#define RPU_RPU_GLBL_CNTL_TEINIT_MASK ((u32)0X00000020U)
#define RPU_RPU_GLBL_CNTL_SLCLAMP_SHIFT 4
#define RPU_RPU_GLBL_CNTL_SLCLAMP_WIDTH 1
#define RPU_RPU_GLBL_CNTL_SLCLAMP_MASK ((u32)0X00000010U)
#define RPU_RPU_GLBL_CNTL_SLSPLIT_SHIFT 3
#define RPU_RPU_GLBL_CNTL_SLSPLIT_WIDTH 1
#define RPU_RPU_GLBL_CNTL_SLSPLIT_MASK ((u32)0X00000008U)
#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_SHIFT 2
#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_WIDTH 1
#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_MASK ((u32)0X00000004U)
#define RPU_RPU_GLBL_CNTL_CFGIE_SHIFT 1
#define RPU_RPU_GLBL_CNTL_CFGIE_WIDTH 1
#define RPU_RPU_GLBL_CNTL_CFGIE_MASK ((u32)0X00000002U)
#define RPU_RPU_GLBL_CNTL_CFGEE_SHIFT 0
#define RPU_RPU_GLBL_CNTL_CFGEE_WIDTH 1
#define RPU_RPU_GLBL_CNTL_CFGEE_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_GLBL_STATUS
*/
#define RPU_RPU_GLBL_STATUS ( ( RPU_BASEADDR ) + ((u32)0X00000004U) )
#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_SHIFT 0
#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_WIDTH 1
#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_ERR_CNTL
*/
#define RPU_RPU_ERR_CNTL ( ( RPU_BASEADDR ) + ((u32)0X00000008U) )
#define RPU_RPU_ERR_CNTL_APB_ERR_RES_SHIFT 0
#define RPU_RPU_ERR_CNTL_APB_ERR_RES_WIDTH 1
#define RPU_RPU_ERR_CNTL_APB_ERR_RES_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_RAM
*/
#define RPU_RPU_RAM ( ( RPU_BASEADDR ) + ((u32)0X0000000CU) )
#define RPU_RPU_RAM_RAMCONTROL1_SHIFT 8
#define RPU_RPU_RAM_RAMCONTROL1_WIDTH 8
#define RPU_RPU_RAM_RAMCONTROL1_MASK ((u32)0X0000FF00U)
#define RPU_RPU_RAM_RAMCONTROL0_SHIFT 0
#define RPU_RPU_RAM_RAMCONTROL0_WIDTH 8
#define RPU_RPU_RAM_RAMCONTROL0_MASK ((u32)0X000000FFU)
/**
* Register: RPU_RPU_CACHE_DATA
*/
#define RPU_RPU_CACHE_DATA ( ( RPU_BASEADDR ) + ((u32)0X00000010U) )
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_SHIFT 29
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_WIDTH 1
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_MASK ((u32)0X20000000U)
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_SHIFT 27
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_WIDTH 2
#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_MASK ((u32)0X18000000U)
#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_SHIFT 24
#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_WIDTH 3
#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_MASK ((u32)0X07000000U)
#define RPU_RPU_CACHE_DATA_DTAG_EMAS_SHIFT 23
#define RPU_RPU_CACHE_DATA_DTAG_EMAS_WIDTH 1
#define RPU_RPU_CACHE_DATA_DTAG_EMAS_MASK ((u32)0X00800000U)
#define RPU_RPU_CACHE_DATA_DTAG_EMAW_SHIFT 21
#define RPU_RPU_CACHE_DATA_DTAG_EMAW_WIDTH 2
#define RPU_RPU_CACHE_DATA_DTAG_EMAW_MASK ((u32)0X00600000U)
#define RPU_RPU_CACHE_DATA_DTAG_EMA_SHIFT 18
#define RPU_RPU_CACHE_DATA_DTAG_EMA_WIDTH 3
#define RPU_RPU_CACHE_DATA_DTAG_EMA_MASK ((u32)0X001C0000U)
#define RPU_RPU_CACHE_DATA_DDATA_EMAS_SHIFT 17
#define RPU_RPU_CACHE_DATA_DDATA_EMAS_WIDTH 1
#define RPU_RPU_CACHE_DATA_DDATA_EMAS_MASK ((u32)0X00020000U)
#define RPU_RPU_CACHE_DATA_DDATA_EMAW_SHIFT 15
#define RPU_RPU_CACHE_DATA_DDATA_EMAW_WIDTH 2
#define RPU_RPU_CACHE_DATA_DDATA_EMAW_MASK ((u32)0X00018000U)
#define RPU_RPU_CACHE_DATA_DDATA_EMA_SHIFT 12
#define RPU_RPU_CACHE_DATA_DDATA_EMA_WIDTH 3
#define RPU_RPU_CACHE_DATA_DDATA_EMA_MASK ((u32)0X00007000U)
#define RPU_RPU_CACHE_DATA_ITAG_EMAS_SHIFT 11
#define RPU_RPU_CACHE_DATA_ITAG_EMAS_WIDTH 1
#define RPU_RPU_CACHE_DATA_ITAG_EMAS_MASK ((u32)0X00000800U)
#define RPU_RPU_CACHE_DATA_ITAG_EMAW_SHIFT 9
#define RPU_RPU_CACHE_DATA_ITAG_EMAW_WIDTH 2
#define RPU_RPU_CACHE_DATA_ITAG_EMAW_MASK ((u32)0X00000600U)
#define RPU_RPU_CACHE_DATA_ITAG_EMA_SHIFT 6
#define RPU_RPU_CACHE_DATA_ITAG_EMA_WIDTH 3
#define RPU_RPU_CACHE_DATA_ITAG_EMA_MASK ((u32)0X000001C0U)
#define RPU_RPU_CACHE_DATA_IDATA_EMAS_SHIFT 5
#define RPU_RPU_CACHE_DATA_IDATA_EMAS_WIDTH 1
#define RPU_RPU_CACHE_DATA_IDATA_EMAS_MASK ((u32)0X00000020U)
#define RPU_RPU_CACHE_DATA_IDATA_EMAW_SHIFT 3
#define RPU_RPU_CACHE_DATA_IDATA_EMAW_WIDTH 2
#define RPU_RPU_CACHE_DATA_IDATA_EMAW_MASK ((u32)0X00000018U)
#define RPU_RPU_CACHE_DATA_IDATA_EMA_SHIFT 0
#define RPU_RPU_CACHE_DATA_IDATA_EMA_WIDTH 3
#define RPU_RPU_CACHE_DATA_IDATA_EMA_MASK ((u32)0X00000007U)
/**
* Register: RPU_RPU_CACHE_SYN
*/
#define RPU_RPU_CACHE_SYN ( ( RPU_BASEADDR ) + ((u32)0X00000014U) )
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_SHIFT 29
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_WIDTH 1
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_MASK ((u32)0X20000000U)
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_SHIFT 27
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_WIDTH 2
#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_MASK ((u32)0X18000000U)
#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_SHIFT 24
#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_WIDTH 3
#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_MASK ((u32)0X07000000U)
#define RPU_RPU_CACHE_SYN_DTAG_EMAS_SHIFT 23
#define RPU_RPU_CACHE_SYN_DTAG_EMAS_WIDTH 1
#define RPU_RPU_CACHE_SYN_DTAG_EMAS_MASK ((u32)0X00800000U)
#define RPU_RPU_CACHE_SYN_DTAG_EMAW_SHIFT 21
#define RPU_RPU_CACHE_SYN_DTAG_EMAW_WIDTH 2
#define RPU_RPU_CACHE_SYN_DTAG_EMAW_MASK ((u32)0X00600000U)
#define RPU_RPU_CACHE_SYN_DTAG_EMA_SHIFT 18
#define RPU_RPU_CACHE_SYN_DTAG_EMA_WIDTH 3
#define RPU_RPU_CACHE_SYN_DTAG_EMA_MASK ((u32)0X001C0000U)
#define RPU_RPU_CACHE_SYN_DDATA_EMAS_SHIFT 17
#define RPU_RPU_CACHE_SYN_DDATA_EMAS_WIDTH 1
#define RPU_RPU_CACHE_SYN_DDATA_EMAS_MASK ((u32)0X00020000U)
#define RPU_RPU_CACHE_SYN_DDATA_EMAW_SHIFT 15
#define RPU_RPU_CACHE_SYN_DDATA_EMAW_WIDTH 2
#define RPU_RPU_CACHE_SYN_DDATA_EMAW_MASK ((u32)0X00018000U)
#define RPU_RPU_CACHE_SYN_DDATA_EMA_SHIFT 12
#define RPU_RPU_CACHE_SYN_DDATA_EMA_WIDTH 3
#define RPU_RPU_CACHE_SYN_DDATA_EMA_MASK ((u32)0X00007000U)
#define RPU_RPU_CACHE_SYN_ITAG_EMAS_SHIFT 11
#define RPU_RPU_CACHE_SYN_ITAG_EMAS_WIDTH 1
#define RPU_RPU_CACHE_SYN_ITAG_EMAS_MASK ((u32)0X00000800U)
#define RPU_RPU_CACHE_SYN_ITAG_EMAW_SHIFT 9
#define RPU_RPU_CACHE_SYN_ITAG_EMAW_WIDTH 2
#define RPU_RPU_CACHE_SYN_ITAG_EMAW_MASK ((u32)0X00000600U)
#define RPU_RPU_CACHE_SYN_ITAG_EMA_SHIFT 6
#define RPU_RPU_CACHE_SYN_ITAG_EMA_WIDTH 3
#define RPU_RPU_CACHE_SYN_ITAG_EMA_MASK ((u32)0X000001C0U)
#define RPU_RPU_CACHE_SYN_IDATA_EMAS_SHIFT 5
#define RPU_RPU_CACHE_SYN_IDATA_EMAS_WIDTH 1
#define RPU_RPU_CACHE_SYN_IDATA_EMAS_MASK ((u32)0X00000020U)
#define RPU_RPU_CACHE_SYN_IDATA_EMAW_SHIFT 3
#define RPU_RPU_CACHE_SYN_IDATA_EMAW_WIDTH 2
#define RPU_RPU_CACHE_SYN_IDATA_EMAW_MASK ((u32)0X00000018U)
#define RPU_RPU_CACHE_SYN_IDATA_EMA_SHIFT 0
#define RPU_RPU_CACHE_SYN_IDATA_EMA_WIDTH 3
#define RPU_RPU_CACHE_SYN_IDATA_EMA_MASK ((u32)0X00000007U)
/**
* Register: RPU_RPU_TCM_DATA
*/
#define RPU_RPU_TCM_DATA ( ( RPU_BASEADDR ) + ((u32)0X00000018U) )
#define RPU_RPU_TCM_DATA_B_EMAS_SHIFT 17
#define RPU_RPU_TCM_DATA_B_EMAS_WIDTH 1
#define RPU_RPU_TCM_DATA_B_EMAS_MASK ((u32)0X00020000U)
#define RPU_RPU_TCM_DATA_B_EMAW_SHIFT 15
#define RPU_RPU_TCM_DATA_B_EMAW_WIDTH 2
#define RPU_RPU_TCM_DATA_B_EMAW_MASK ((u32)0X00018000U)
#define RPU_RPU_TCM_DATA_B_EMA_SHIFT 12
#define RPU_RPU_TCM_DATA_B_EMA_WIDTH 3
#define RPU_RPU_TCM_DATA_B_EMA_MASK ((u32)0X00007000U)
#define RPU_RPU_TCM_DATA_A_EMAS_SHIFT 5
#define RPU_RPU_TCM_DATA_A_EMAS_WIDTH 1
#define RPU_RPU_TCM_DATA_A_EMAS_MASK ((u32)0X00000020U)
#define RPU_RPU_TCM_DATA_A_EMAW_SHIFT 3
#define RPU_RPU_TCM_DATA_A_EMAW_WIDTH 2
#define RPU_RPU_TCM_DATA_A_EMAW_MASK ((u32)0X00000018U)
#define RPU_RPU_TCM_DATA_A_EMA_SHIFT 0
#define RPU_RPU_TCM_DATA_A_EMA_WIDTH 3
#define RPU_RPU_TCM_DATA_A_EMA_MASK ((u32)0X00000007U)
/**
* Register: RPU_RPU_TCM_SYN
*/
#define RPU_RPU_TCM_SYN ( ( RPU_BASEADDR ) + ((u32)0X0000001CU) )
#define RPU_RPU_TCM_SYN_B_EMAS_SHIFT 23
#define RPU_RPU_TCM_SYN_B_EMAS_WIDTH 1
#define RPU_RPU_TCM_SYN_B_EMAS_MASK ((u32)0X00800000U)
#define RPU_RPU_TCM_SYN_B_EMAW_SHIFT 21
#define RPU_RPU_TCM_SYN_B_EMAW_WIDTH 2
#define RPU_RPU_TCM_SYN_B_EMAW_MASK ((u32)0X00600000U)
#define RPU_RPU_TCM_SYN_B_EMA_SHIFT 18
#define RPU_RPU_TCM_SYN_B_EMA_WIDTH 3
#define RPU_RPU_TCM_SYN_B_EMA_MASK ((u32)0X001C0000U)
#define RPU_RPU_TCM_SYN_A_EMAS_SHIFT 11
#define RPU_RPU_TCM_SYN_A_EMAS_WIDTH 1
#define RPU_RPU_TCM_SYN_A_EMAS_MASK ((u32)0X00000800U)
#define RPU_RPU_TCM_SYN_A_EMAW_SHIFT 9
#define RPU_RPU_TCM_SYN_A_EMAW_WIDTH 2
#define RPU_RPU_TCM_SYN_A_EMAW_MASK ((u32)0X00000600U)
#define RPU_RPU_TCM_SYN_A_EMA_SHIFT 6
#define RPU_RPU_TCM_SYN_A_EMA_WIDTH 3
#define RPU_RPU_TCM_SYN_A_EMA_MASK ((u32)0X000001C0U)
/**
* Register: RPU_RPU_ERR_INJ
*/
#define RPU_RPU_ERR_INJ ( ( RPU_BASEADDR ) + ((u32)0X00000020U) )
#define RPU_RPU_ERR_INJ_DCCMINP2_SHIFT 8
#define RPU_RPU_ERR_INJ_DCCMINP2_WIDTH 8
#define RPU_RPU_ERR_INJ_DCCMINP2_MASK ((u32)0X0000FF00U)
#define RPU_RPU_ERR_INJ_DCCMINP_SHIFT 0
#define RPU_RPU_ERR_INJ_DCCMINP_WIDTH 8
#define RPU_RPU_ERR_INJ_DCCMINP_MASK ((u32)0X000000FFU)
/**
* Register: RPU_RPU_CCF_MASK
*/
#define RPU_RPU_CCF_MASK ( ( RPU_BASEADDR ) + ((u32)0X00000024U) )
#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_SHIFT 7
#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_WIDTH 1
#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_MASK ((u32)0X00000080U)
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_SHIFT 6
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_WIDTH 1
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_MASK ((u32)0X00000040U)
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_SHIFT 5
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_WIDTH 1
#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_MASK ((u32)0X00000020U)
#define RPU_RPU_CCF_MASK_ISO_SHIFT 4
#define RPU_RPU_CCF_MASK_ISO_WIDTH 1
#define RPU_RPU_CCF_MASK_ISO_MASK ((u32)0X00000010U)
#define RPU_RPU_CCF_MASK_PGE_SHIFT 3
#define RPU_RPU_CCF_MASK_PGE_WIDTH 1
#define RPU_RPU_CCF_MASK_PGE_MASK ((u32)0X00000008U)
#define RPU_RPU_CCF_MASK_R50_DBG_RST_SHIFT 2
#define RPU_RPU_CCF_MASK_R50_DBG_RST_WIDTH 1
#define RPU_RPU_CCF_MASK_R50_DBG_RST_MASK ((u32)0X00000004U)
#define RPU_RPU_CCF_MASK_R50_RST_SHIFT 1
#define RPU_RPU_CCF_MASK_R50_RST_WIDTH 1
#define RPU_RPU_CCF_MASK_R50_RST_MASK ((u32)0X00000002U)
#define RPU_RPU_CCF_MASK_PGE_RST_SHIFT 0
#define RPU_RPU_CCF_MASK_PGE_RST_WIDTH 1
#define RPU_RPU_CCF_MASK_PGE_RST_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_INTR_0
*/
#define RPU_RPU_INTR_0 ( ( RPU_BASEADDR ) + ((u32)0X00000028U) )
#define RPU_RPU_INTR_0_SPI_SHIFT 0
#define RPU_RPU_INTR_0_SPI_WIDTH 32
#define RPU_RPU_INTR_0_SPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_INTR_1
*/
#define RPU_RPU_INTR_1 ( ( RPU_BASEADDR ) + ((u32)0X0000002CU) )
#define RPU_RPU_INTR_1_SPI_SHIFT 0
#define RPU_RPU_INTR_1_SPI_WIDTH 32
#define RPU_RPU_INTR_1_SPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_INTR_2
*/
#define RPU_RPU_INTR_2 ( ( RPU_BASEADDR ) + ((u32)0X00000030U) )
#define RPU_RPU_INTR_2_SPI_SHIFT 0
#define RPU_RPU_INTR_2_SPI_WIDTH 32
#define RPU_RPU_INTR_2_SPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_INTR_3
*/
#define RPU_RPU_INTR_3 ( ( RPU_BASEADDR ) + ((u32)0X00000034U) )
#define RPU_RPU_INTR_3_SPI_SHIFT 0
#define RPU_RPU_INTR_3_SPI_WIDTH 32
#define RPU_RPU_INTR_3_SPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_INTR_4
*/
#define RPU_RPU_INTR_4 ( ( RPU_BASEADDR ) + ((u32)0X00000038U) )
#define RPU_RPU_INTR_4_SPI_SHIFT 0
#define RPU_RPU_INTR_4_SPI_WIDTH 32
#define RPU_RPU_INTR_4_SPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_INTR_MASK_0
*/
#define RPU_RPU_INTR_MASK_0 ( ( RPU_BASEADDR ) + ((u32)0X00000040U) )
#define RPU_RPU_INTR_MASK_0_SPI_SHIFT 0
#define RPU_RPU_INTR_MASK_0_SPI_WIDTH 32
#define RPU_RPU_INTR_MASK_0_SPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_INTR_MASK_1
*/
#define RPU_RPU_INTR_MASK_1 ( ( RPU_BASEADDR ) + ((u32)0X00000044U) )
#define RPU_RPU_INTR_MASK_1_SPI_SHIFT 0
#define RPU_RPU_INTR_MASK_1_SPI_WIDTH 32
#define RPU_RPU_INTR_MASK_1_SPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_INTR_MASK_2
*/
#define RPU_RPU_INTR_MASK_2 ( ( RPU_BASEADDR ) + ((u32)0X00000048U) )
#define RPU_RPU_INTR_MASK_2_SPI_SHIFT 0
#define RPU_RPU_INTR_MASK_2_SPI_WIDTH 32
#define RPU_RPU_INTR_MASK_2_SPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_INTR_MASK_3
*/
#define RPU_RPU_INTR_MASK_3 ( ( RPU_BASEADDR ) + ((u32)0X0000004CU) )
#define RPU_RPU_INTR_MASK_3_SPI_SHIFT 0
#define RPU_RPU_INTR_MASK_3_SPI_WIDTH 32
#define RPU_RPU_INTR_MASK_3_SPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_INTR_MASK_4
*/
#define RPU_RPU_INTR_MASK_4 ( ( RPU_BASEADDR ) + ((u32)0X00000050U) )
#define RPU_RPU_INTR_MASK_4_SPI_SHIFT 0
#define RPU_RPU_INTR_MASK_4_SPI_WIDTH 32
#define RPU_RPU_INTR_MASK_4_SPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_CCF_VAL
*/
#define RPU_RPU_CCF_VAL ( ( RPU_BASEADDR ) + ((u32)0X00000054U) )
#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_SHIFT 7
#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_WIDTH 1
#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_MASK ((u32)0X00000080U)
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_SHIFT 6
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_WIDTH 1
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_MASK ((u32)0X00000040U)
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_SHIFT 5
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_WIDTH 1
#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_MASK ((u32)0X00000020U)
#define RPU_RPU_CCF_VAL_ISO_SHIFT 4
#define RPU_RPU_CCF_VAL_ISO_WIDTH 1
#define RPU_RPU_CCF_VAL_ISO_MASK ((u32)0X00000010U)
#define RPU_RPU_CCF_VAL_PGE_SHIFT 3
#define RPU_RPU_CCF_VAL_PGE_WIDTH 1
#define RPU_RPU_CCF_VAL_PGE_MASK ((u32)0X00000008U)
#define RPU_RPU_CCF_VAL_R50_DBG_RST_SHIFT 2
#define RPU_RPU_CCF_VAL_R50_DBG_RST_WIDTH 1
#define RPU_RPU_CCF_VAL_R50_DBG_RST_MASK ((u32)0X00000004U)
#define RPU_RPU_CCF_VAL_R50_RST_SHIFT 1
#define RPU_RPU_CCF_VAL_R50_RST_WIDTH 1
#define RPU_RPU_CCF_VAL_R50_RST_MASK ((u32)0X00000002U)
#define RPU_RPU_CCF_VAL_PGE_RST_SHIFT 0
#define RPU_RPU_CCF_VAL_PGE_RST_WIDTH 1
#define RPU_RPU_CCF_VAL_PGE_RST_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_SAFETY_CHK
*/
#define RPU_RPU_SAFETY_CHK ( ( RPU_BASEADDR ) + ((u32)0X000000F0U) )
#define RPU_RPU_SAFETY_CHK_VAL_SHIFT 0
#define RPU_RPU_SAFETY_CHK_VAL_WIDTH 32
#define RPU_RPU_SAFETY_CHK_VAL_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU
*/
#define RPU_RPU ( ( RPU_BASEADDR ) + ((u32)0X000000F4U) )
#define RPU_RPU_ECO_SHIFT 0
#define RPU_RPU_ECO_WIDTH 32
#define RPU_RPU_ECO_MASK ((u32)0XFFFFFFFFU)
/**
* Register: RPU_RPU_0_CFG
*/
#define RPU_RPU_0_CFG ( ( RPU_BASEADDR ) + ((u32)0X00000100U) )
#define RPU_RPU_0_CFG_CFGNMFI0_SHIFT 3
#define RPU_RPU_0_CFG_CFGNMFI0_WIDTH 1
#define RPU_RPU_0_CFG_CFGNMFI0_MASK ((u32)0X00000008U)
#define RPU_RPU_0_CFG_VINITHI_SHIFT 2
#define RPU_RPU_0_CFG_VINITHI_WIDTH 1
#define RPU_RPU_0_CFG_VINITHI_MASK ((u32)0X00000004U)
#define RPU_RPU_0_CFG_COHERENT_SHIFT 1
#define RPU_RPU_0_CFG_COHERENT_WIDTH 1
#define RPU_RPU_0_CFG_COHERENT_MASK ((u32)0X00000002U)
#define RPU_RPU_0_CFG_NCPUHALT_SHIFT 0
#define RPU_RPU_0_CFG_NCPUHALT_WIDTH 1
#define RPU_RPU_0_CFG_NCPUHALT_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_0_STATUS
*/
#define RPU_RPU_0_STATUS ( ( RPU_BASEADDR ) + ((u32)0X00000104U) )
#define RPU_RPU_0_STATUS_NVALRESET_SHIFT 5
#define RPU_RPU_0_STATUS_NVALRESET_WIDTH 1
#define RPU_RPU_0_STATUS_NVALRESET_MASK ((u32)0X00000020U)
#define RPU_RPU_0_STATUS_NVALIRQ_SHIFT 4
#define RPU_RPU_0_STATUS_NVALIRQ_WIDTH 1
#define RPU_RPU_0_STATUS_NVALIRQ_MASK ((u32)0X00000010U)
#define RPU_RPU_0_STATUS_NVALFIQ_SHIFT 3
#define RPU_RPU_0_STATUS_NVALFIQ_WIDTH 1
#define RPU_RPU_0_STATUS_NVALFIQ_MASK ((u32)0X00000008U)
#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_SHIFT 2
#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_WIDTH 1
#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_MASK ((u32)0X00000004U)
#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_SHIFT 1
#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_WIDTH 1
#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_MASK ((u32)0X00000002U)
#define RPU_RPU_0_STATUS_NCLKSTOPPED_SHIFT 0
#define RPU_RPU_0_STATUS_NCLKSTOPPED_WIDTH 1
#define RPU_RPU_0_STATUS_NCLKSTOPPED_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_0_PWRDWN
*/
#define RPU_RPU_0_PWRDWN ( ( RPU_BASEADDR ) + ((u32)0X00000108U) )
#define RPU_RPU_0_PWRDWN_EN_SHIFT 0
#define RPU_RPU_0_PWRDWN_EN_WIDTH 1
#define RPU_RPU_0_PWRDWN_EN_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_0_ISR
*/
#define RPU_RPU_0_ISR ( ( RPU_BASEADDR ) + ((u32)0X00000114U) )
#define RPU_RPU_0_ISR_FPUFC_SHIFT 24
#define RPU_RPU_0_ISR_FPUFC_WIDTH 1
#define RPU_RPU_0_ISR_FPUFC_MASK ((u32)0X01000000U)
#define RPU_RPU_0_ISR_FPOFC_SHIFT 23
#define RPU_RPU_0_ISR_FPOFC_WIDTH 1
#define RPU_RPU_0_ISR_FPOFC_MASK ((u32)0X00800000U)
#define RPU_RPU_0_ISR_FPIXC_SHIFT 22
#define RPU_RPU_0_ISR_FPIXC_WIDTH 1
#define RPU_RPU_0_ISR_FPIXC_MASK ((u32)0X00400000U)
#define RPU_RPU_0_ISR_FPIOC_SHIFT 21
#define RPU_RPU_0_ISR_FPIOC_WIDTH 1
#define RPU_RPU_0_ISR_FPIOC_MASK ((u32)0X00200000U)
#define RPU_RPU_0_ISR_FPIDC_SHIFT 20
#define RPU_RPU_0_ISR_FPIDC_WIDTH 1
#define RPU_RPU_0_ISR_FPIDC_MASK ((u32)0X00100000U)
#define RPU_RPU_0_ISR_FPDZC_SHIFT 19
#define RPU_RPU_0_ISR_FPDZC_WIDTH 1
#define RPU_RPU_0_ISR_FPDZC_MASK ((u32)0X00080000U)
#define RPU_RPU_0_ISR_TCM_ASLV_CE_SHIFT 18
#define RPU_RPU_0_ISR_TCM_ASLV_CE_WIDTH 1
#define RPU_RPU_0_ISR_TCM_ASLV_CE_MASK ((u32)0X00040000U)
#define RPU_RPU_0_ISR_TCM_ASLV_FAT_SHIFT 17
#define RPU_RPU_0_ISR_TCM_ASLV_FAT_WIDTH 1
#define RPU_RPU_0_ISR_TCM_ASLV_FAT_MASK ((u32)0X00020000U)
#define RPU_RPU_0_ISR_TCM_LST_CE_SHIFT 16
#define RPU_RPU_0_ISR_TCM_LST_CE_WIDTH 1
#define RPU_RPU_0_ISR_TCM_LST_CE_MASK ((u32)0X00010000U)
#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_SHIFT 15
#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_WIDTH 1
#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_MASK ((u32)0X00008000U)
#define RPU_RPU_0_ISR_B1TCM_CE_SHIFT 14
#define RPU_RPU_0_ISR_B1TCM_CE_WIDTH 1
#define RPU_RPU_0_ISR_B1TCM_CE_MASK ((u32)0X00004000U)
#define RPU_RPU_0_ISR_B0TCM_CE_SHIFT 13
#define RPU_RPU_0_ISR_B0TCM_CE_WIDTH 1
#define RPU_RPU_0_ISR_B0TCM_CE_MASK ((u32)0X00002000U)
#define RPU_RPU_0_ISR_ATCM_CE_SHIFT 12
#define RPU_RPU_0_ISR_ATCM_CE_WIDTH 1
#define RPU_RPU_0_ISR_ATCM_CE_MASK ((u32)0X00001000U)
#define RPU_RPU_0_ISR_B1TCM_UE_SHIFT 11
#define RPU_RPU_0_ISR_B1TCM_UE_WIDTH 1
#define RPU_RPU_0_ISR_B1TCM_UE_MASK ((u32)0X00000800U)
#define RPU_RPU_0_ISR_B0TCM_UE_SHIFT 10
#define RPU_RPU_0_ISR_B0TCM_UE_WIDTH 1
#define RPU_RPU_0_ISR_B0TCM_UE_MASK ((u32)0X00000400U)
#define RPU_RPU_0_ISR_ATCM_UE_SHIFT 9
#define RPU_RPU_0_ISR_ATCM_UE_WIDTH 1
#define RPU_RPU_0_ISR_ATCM_UE_MASK ((u32)0X00000200U)
#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_SHIFT 8
#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_WIDTH 1
#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U)
#define RPU_RPU_0_ISR_DDATA_FAT_SHIFT 7
#define RPU_RPU_0_ISR_DDATA_FAT_WIDTH 1
#define RPU_RPU_0_ISR_DDATA_FAT_MASK ((u32)0X00000080U)
#define RPU_RPU_0_ISR_TCM_LST_FAT_SHIFT 6
#define RPU_RPU_0_ISR_TCM_LST_FAT_WIDTH 1
#define RPU_RPU_0_ISR_TCM_LST_FAT_MASK ((u32)0X00000040U)
#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_SHIFT 5
#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_WIDTH 1
#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U)
#define RPU_RPU_0_ISR_DDATA_CE_SHIFT 4
#define RPU_RPU_0_ISR_DDATA_CE_WIDTH 1
#define RPU_RPU_0_ISR_DDATA_CE_MASK ((u32)0X00000010U)
#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_SHIFT 3
#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_WIDTH 1
#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_MASK ((u32)0X00000008U)
#define RPU_RPU_0_ISR_IDATA_CE_SHIFT 2
#define RPU_RPU_0_ISR_IDATA_CE_WIDTH 1
#define RPU_RPU_0_ISR_IDATA_CE_MASK ((u32)0X00000004U)
#define RPU_RPU_0_ISR_ITAG_CE_SHIFT 1
#define RPU_RPU_0_ISR_ITAG_CE_WIDTH 1
#define RPU_RPU_0_ISR_ITAG_CE_MASK ((u32)0X00000002U)
#define RPU_RPU_0_ISR_APB_ERR_SHIFT 0
#define RPU_RPU_0_ISR_APB_ERR_WIDTH 1
#define RPU_RPU_0_ISR_APB_ERR_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_0_IMR
*/
#define RPU_RPU_0_IMR ( ( RPU_BASEADDR ) + ((u32)0X00000118U) )
#define RPU_RPU_0_IMR_FPUFC_SHIFT 24
#define RPU_RPU_0_IMR_FPUFC_WIDTH 1
#define RPU_RPU_0_IMR_FPUFC_MASK ((u32)0X01000000U)
#define RPU_RPU_0_IMR_FPOFC_SHIFT 23
#define RPU_RPU_0_IMR_FPOFC_WIDTH 1
#define RPU_RPU_0_IMR_FPOFC_MASK ((u32)0X00800000U)
#define RPU_RPU_0_IMR_FPIXC_SHIFT 22
#define RPU_RPU_0_IMR_FPIXC_WIDTH 1
#define RPU_RPU_0_IMR_FPIXC_MASK ((u32)0X00400000U)
#define RPU_RPU_0_IMR_FPIOC_SHIFT 21
#define RPU_RPU_0_IMR_FPIOC_WIDTH 1
#define RPU_RPU_0_IMR_FPIOC_MASK ((u32)0X00200000U)
#define RPU_RPU_0_IMR_FPIDC_SHIFT 20
#define RPU_RPU_0_IMR_FPIDC_WIDTH 1
#define RPU_RPU_0_IMR_FPIDC_MASK ((u32)0X00100000U)
#define RPU_RPU_0_IMR_FPDZC_SHIFT 19
#define RPU_RPU_0_IMR_FPDZC_WIDTH 1
#define RPU_RPU_0_IMR_FPDZC_MASK ((u32)0X00080000U)
#define RPU_RPU_0_IMR_TCM_ASLV_CE_SHIFT 18
#define RPU_RPU_0_IMR_TCM_ASLV_CE_WIDTH 1
#define RPU_RPU_0_IMR_TCM_ASLV_CE_MASK ((u32)0X00040000U)
#define RPU_RPU_0_IMR_TCM_ASLV_FAT_SHIFT 17
#define RPU_RPU_0_IMR_TCM_ASLV_FAT_WIDTH 1
#define RPU_RPU_0_IMR_TCM_ASLV_FAT_MASK ((u32)0X00020000U)
#define RPU_RPU_0_IMR_TCM_LST_CE_SHIFT 16
#define RPU_RPU_0_IMR_TCM_LST_CE_WIDTH 1
#define RPU_RPU_0_IMR_TCM_LST_CE_MASK ((u32)0X00010000U)
#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_SHIFT 15
#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_WIDTH 1
#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_MASK ((u32)0X00008000U)
#define RPU_RPU_0_IMR_B1TCM_CE_SHIFT 14
#define RPU_RPU_0_IMR_B1TCM_CE_WIDTH 1
#define RPU_RPU_0_IMR_B1TCM_CE_MASK ((u32)0X00004000U)
#define RPU_RPU_0_IMR_B0TCM_CE_SHIFT 13
#define RPU_RPU_0_IMR_B0TCM_CE_WIDTH 1
#define RPU_RPU_0_IMR_B0TCM_CE_MASK ((u32)0X00002000U)
#define RPU_RPU_0_IMR_ATCM_CE_SHIFT 12
#define RPU_RPU_0_IMR_ATCM_CE_WIDTH 1
#define RPU_RPU_0_IMR_ATCM_CE_MASK ((u32)0X00001000U)
#define RPU_RPU_0_IMR_B1TCM_UE_SHIFT 11
#define RPU_RPU_0_IMR_B1TCM_UE_WIDTH 1
#define RPU_RPU_0_IMR_B1TCM_UE_MASK ((u32)0X00000800U)
#define RPU_RPU_0_IMR_B0TCM_UE_SHIFT 10
#define RPU_RPU_0_IMR_B0TCM_UE_WIDTH 1
#define RPU_RPU_0_IMR_B0TCM_UE_MASK ((u32)0X00000400U)
#define RPU_RPU_0_IMR_ATCM_UE_SHIFT 9
#define RPU_RPU_0_IMR_ATCM_UE_WIDTH 1
#define RPU_RPU_0_IMR_ATCM_UE_MASK ((u32)0X00000200U)
#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_SHIFT 8
#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_WIDTH 1
#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U)
#define RPU_RPU_0_IMR_DDATA_FAT_SHIFT 7
#define RPU_RPU_0_IMR_DDATA_FAT_WIDTH 1
#define RPU_RPU_0_IMR_DDATA_FAT_MASK ((u32)0X00000080U)
#define RPU_RPU_0_IMR_TCM_LST_FAT_SHIFT 6
#define RPU_RPU_0_IMR_TCM_LST_FAT_WIDTH 1
#define RPU_RPU_0_IMR_TCM_LST_FAT_MASK ((u32)0X00000040U)
#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_SHIFT 5
#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_WIDTH 1
#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U)
#define RPU_RPU_0_IMR_DDATA_CE_SHIFT 4
#define RPU_RPU_0_IMR_DDATA_CE_WIDTH 1
#define RPU_RPU_0_IMR_DDATA_CE_MASK ((u32)0X00000010U)
#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_SHIFT 3
#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_WIDTH 1
#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_MASK ((u32)0X00000008U)
#define RPU_RPU_0_IMR_IDATA_CE_SHIFT 2
#define RPU_RPU_0_IMR_IDATA_CE_WIDTH 1
#define RPU_RPU_0_IMR_IDATA_CE_MASK ((u32)0X00000004U)
#define RPU_RPU_0_IMR_ITAG_CE_SHIFT 1
#define RPU_RPU_0_IMR_ITAG_CE_WIDTH 1
#define RPU_RPU_0_IMR_ITAG_CE_MASK ((u32)0X00000002U)
#define RPU_RPU_0_IMR_APB_ERR_SHIFT 0
#define RPU_RPU_0_IMR_APB_ERR_WIDTH 1
#define RPU_RPU_0_IMR_APB_ERR_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_0_IEN
*/
#define RPU_RPU_0_IEN ( ( RPU_BASEADDR ) + ((u32)0X0000011CU) )
#define RPU_RPU_0_IEN_FPUFC_SHIFT 24
#define RPU_RPU_0_IEN_FPUFC_WIDTH 1
#define RPU_RPU_0_IEN_FPUFC_MASK ((u32)0X01000000U)
#define RPU_RPU_0_IEN_FPOFC_SHIFT 23
#define RPU_RPU_0_IEN_FPOFC_WIDTH 1
#define RPU_RPU_0_IEN_FPOFC_MASK ((u32)0X00800000U)
#define RPU_RPU_0_IEN_FPIXC_SHIFT 22
#define RPU_RPU_0_IEN_FPIXC_WIDTH 1
#define RPU_RPU_0_IEN_FPIXC_MASK ((u32)0X00400000U)
#define RPU_RPU_0_IEN_FPIOC_SHIFT 21
#define RPU_RPU_0_IEN_FPIOC_WIDTH 1
#define RPU_RPU_0_IEN_FPIOC_MASK ((u32)0X00200000U)
#define RPU_RPU_0_IEN_FPIDC_SHIFT 20
#define RPU_RPU_0_IEN_FPIDC_WIDTH 1
#define RPU_RPU_0_IEN_FPIDC_MASK ((u32)0X00100000U)
#define RPU_RPU_0_IEN_FPDZC_SHIFT 19
#define RPU_RPU_0_IEN_FPDZC_WIDTH 1
#define RPU_RPU_0_IEN_FPDZC_MASK ((u32)0X00080000U)
#define RPU_RPU_0_IEN_TCM_ASLV_CE_SHIFT 18
#define RPU_RPU_0_IEN_TCM_ASLV_CE_WIDTH 1
#define RPU_RPU_0_IEN_TCM_ASLV_CE_MASK ((u32)0X00040000U)
#define RPU_RPU_0_IEN_TCM_ASLV_FAT_SHIFT 17
#define RPU_RPU_0_IEN_TCM_ASLV_FAT_WIDTH 1
#define RPU_RPU_0_IEN_TCM_ASLV_FAT_MASK ((u32)0X00020000U)
#define RPU_RPU_0_IEN_TCM_LST_CE_SHIFT 16
#define RPU_RPU_0_IEN_TCM_LST_CE_WIDTH 1
#define RPU_RPU_0_IEN_TCM_LST_CE_MASK ((u32)0X00010000U)
#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_SHIFT 15
#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_WIDTH 1
#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_MASK ((u32)0X00008000U)
#define RPU_RPU_0_IEN_B1TCM_CE_SHIFT 14
#define RPU_RPU_0_IEN_B1TCM_CE_WIDTH 1
#define RPU_RPU_0_IEN_B1TCM_CE_MASK ((u32)0X00004000U)
#define RPU_RPU_0_IEN_B0TCM_CE_SHIFT 13
#define RPU_RPU_0_IEN_B0TCM_CE_WIDTH 1
#define RPU_RPU_0_IEN_B0TCM_CE_MASK ((u32)0X00002000U)
#define RPU_RPU_0_IEN_ATCM_CE_SHIFT 12
#define RPU_RPU_0_IEN_ATCM_CE_WIDTH 1
#define RPU_RPU_0_IEN_ATCM_CE_MASK ((u32)0X00001000U)
#define RPU_RPU_0_IEN_B1TCM_UE_SHIFT 11
#define RPU_RPU_0_IEN_B1TCM_UE_WIDTH 1
#define RPU_RPU_0_IEN_B1TCM_UE_MASK ((u32)0X00000800U)
#define RPU_RPU_0_IEN_B0TCM_UE_SHIFT 10
#define RPU_RPU_0_IEN_B0TCM_UE_WIDTH 1
#define RPU_RPU_0_IEN_B0TCM_UE_MASK ((u32)0X00000400U)
#define RPU_RPU_0_IEN_ATCM_UE_SHIFT 9
#define RPU_RPU_0_IEN_ATCM_UE_WIDTH 1
#define RPU_RPU_0_IEN_ATCM_UE_MASK ((u32)0X00000200U)
#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_SHIFT 8
#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_WIDTH 1
#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U)
#define RPU_RPU_0_IEN_DDATA_FAT_SHIFT 7
#define RPU_RPU_0_IEN_DDATA_FAT_WIDTH 1
#define RPU_RPU_0_IEN_DDATA_FAT_MASK ((u32)0X00000080U)
#define RPU_RPU_0_IEN_TCM_LST_FAT_SHIFT 6
#define RPU_RPU_0_IEN_TCM_LST_FAT_WIDTH 1
#define RPU_RPU_0_IEN_TCM_LST_FAT_MASK ((u32)0X00000040U)
#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_SHIFT 5
#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_WIDTH 1
#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U)
#define RPU_RPU_0_IEN_DDATA_CE_SHIFT 4
#define RPU_RPU_0_IEN_DDATA_CE_WIDTH 1
#define RPU_RPU_0_IEN_DDATA_CE_MASK ((u32)0X00000010U)
#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_SHIFT 3
#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_WIDTH 1
#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_MASK ((u32)0X00000008U)
#define RPU_RPU_0_IEN_IDATA_CE_SHIFT 2
#define RPU_RPU_0_IEN_IDATA_CE_WIDTH 1
#define RPU_RPU_0_IEN_IDATA_CE_MASK ((u32)0X00000004U)
#define RPU_RPU_0_IEN_ITAG_CE_SHIFT 1
#define RPU_RPU_0_IEN_ITAG_CE_WIDTH 1
#define RPU_RPU_0_IEN_ITAG_CE_MASK ((u32)0X00000002U)
#define RPU_RPU_0_IEN_APB_ERR_SHIFT 0
#define RPU_RPU_0_IEN_APB_ERR_WIDTH 1
#define RPU_RPU_0_IEN_APB_ERR_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_0_IDS
*/
#define RPU_RPU_0_IDS ( ( RPU_BASEADDR ) + ((u32)0X00000120U) )
#define RPU_RPU_0_IDS_FPUFC_SHIFT 24
#define RPU_RPU_0_IDS_FPUFC_WIDTH 1
#define RPU_RPU_0_IDS_FPUFC_MASK ((u32)0X01000000U)
#define RPU_RPU_0_IDS_FPOFC_SHIFT 23
#define RPU_RPU_0_IDS_FPOFC_WIDTH 1
#define RPU_RPU_0_IDS_FPOFC_MASK ((u32)0X00800000U)
#define RPU_RPU_0_IDS_FPIXC_SHIFT 22
#define RPU_RPU_0_IDS_FPIXC_WIDTH 1
#define RPU_RPU_0_IDS_FPIXC_MASK ((u32)0X00400000U)
#define RPU_RPU_0_IDS_FPIOC_SHIFT 21
#define RPU_RPU_0_IDS_FPIOC_WIDTH 1
#define RPU_RPU_0_IDS_FPIOC_MASK ((u32)0X00200000U)
#define RPU_RPU_0_IDS_FPIDC_SHIFT 20
#define RPU_RPU_0_IDS_FPIDC_WIDTH 1
#define RPU_RPU_0_IDS_FPIDC_MASK ((u32)0X00100000U)
#define RPU_RPU_0_IDS_FPDZC_SHIFT 19
#define RPU_RPU_0_IDS_FPDZC_WIDTH 1
#define RPU_RPU_0_IDS_FPDZC_MASK ((u32)0X00080000U)
#define RPU_RPU_0_IDS_TCM_ASLV_CE_SHIFT 18
#define RPU_RPU_0_IDS_TCM_ASLV_CE_WIDTH 1
#define RPU_RPU_0_IDS_TCM_ASLV_CE_MASK ((u32)0X00040000U)
#define RPU_RPU_0_IDS_TCM_ASLV_FAT_SHIFT 17
#define RPU_RPU_0_IDS_TCM_ASLV_FAT_WIDTH 1
#define RPU_RPU_0_IDS_TCM_ASLV_FAT_MASK ((u32)0X00020000U)
#define RPU_RPU_0_IDS_TCM_LST_CE_SHIFT 16
#define RPU_RPU_0_IDS_TCM_LST_CE_WIDTH 1
#define RPU_RPU_0_IDS_TCM_LST_CE_MASK ((u32)0X00010000U)
#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_SHIFT 15
#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_WIDTH 1
#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_MASK ((u32)0X00008000U)
#define RPU_RPU_0_IDS_B1TCM_CE_SHIFT 14
#define RPU_RPU_0_IDS_B1TCM_CE_WIDTH 1
#define RPU_RPU_0_IDS_B1TCM_CE_MASK ((u32)0X00004000U)
#define RPU_RPU_0_IDS_B0TCM_CE_SHIFT 13
#define RPU_RPU_0_IDS_B0TCM_CE_WIDTH 1
#define RPU_RPU_0_IDS_B0TCM_CE_MASK ((u32)0X00002000U)
#define RPU_RPU_0_IDS_ATCM_CE_SHIFT 12
#define RPU_RPU_0_IDS_ATCM_CE_WIDTH 1
#define RPU_RPU_0_IDS_ATCM_CE_MASK ((u32)0X00001000U)
#define RPU_RPU_0_IDS_B1TCM_UE_SHIFT 11
#define RPU_RPU_0_IDS_B1TCM_UE_WIDTH 1
#define RPU_RPU_0_IDS_B1TCM_UE_MASK ((u32)0X00000800U)
#define RPU_RPU_0_IDS_B0TCM_UE_SHIFT 10
#define RPU_RPU_0_IDS_B0TCM_UE_WIDTH 1
#define RPU_RPU_0_IDS_B0TCM_UE_MASK ((u32)0X00000400U)
#define RPU_RPU_0_IDS_ATCM_UE_SHIFT 9
#define RPU_RPU_0_IDS_ATCM_UE_WIDTH 1
#define RPU_RPU_0_IDS_ATCM_UE_MASK ((u32)0X00000200U)
#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_SHIFT 8
#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_WIDTH 1
#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U)
#define RPU_RPU_0_IDS_DDATA_FAT_SHIFT 7
#define RPU_RPU_0_IDS_DDATA_FAT_WIDTH 1
#define RPU_RPU_0_IDS_DDATA_FAT_MASK ((u32)0X00000080U)
#define RPU_RPU_0_IDS_TCM_LST_FAT_SHIFT 6
#define RPU_RPU_0_IDS_TCM_LST_FAT_WIDTH 1
#define RPU_RPU_0_IDS_TCM_LST_FAT_MASK ((u32)0X00000040U)
#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_SHIFT 5
#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_WIDTH 1
#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U)
#define RPU_RPU_0_IDS_DDATA_CE_SHIFT 4
#define RPU_RPU_0_IDS_DDATA_CE_WIDTH 1
#define RPU_RPU_0_IDS_DDATA_CE_MASK ((u32)0X00000010U)
#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_SHIFT 3
#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_WIDTH 1
#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_MASK ((u32)0X00000008U)
#define RPU_RPU_0_IDS_IDATA_CE_SHIFT 2
#define RPU_RPU_0_IDS_IDATA_CE_WIDTH 1
#define RPU_RPU_0_IDS_IDATA_CE_MASK ((u32)0X00000004U)
#define RPU_RPU_0_IDS_ITAG_CE_SHIFT 1
#define RPU_RPU_0_IDS_ITAG_CE_WIDTH 1
#define RPU_RPU_0_IDS_ITAG_CE_MASK ((u32)0X00000002U)
#define RPU_RPU_0_IDS_APB_ERR_SHIFT 0
#define RPU_RPU_0_IDS_APB_ERR_WIDTH 1
#define RPU_RPU_0_IDS_APB_ERR_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_0_SLV_BASE
*/
#define RPU_RPU_0_SLV_BASE ( ( RPU_BASEADDR ) + ((u32)0X00000124U) )
#define RPU_RPU_0_SLV_BASE_ADDR_SHIFT 0
#define RPU_RPU_0_SLV_BASE_ADDR_WIDTH 8
#define RPU_RPU_0_SLV_BASE_ADDR_MASK ((u32)0X000000FFU)
/**
* Register: RPU_RPU_0_AXI_OVER
*/
#define RPU_RPU_0_AXI_OVER ( ( RPU_BASEADDR ) + ((u32)0X00000128U) )
#define RPU_RPU_0_AXI_OVER_AWCACHE_SHIFT 6
#define RPU_RPU_0_AXI_OVER_AWCACHE_WIDTH 4
#define RPU_RPU_0_AXI_OVER_AWCACHE_MASK ((u32)0X000003C0U)
#define RPU_RPU_0_AXI_OVER_ARCACHE_SHIFT 2
#define RPU_RPU_0_AXI_OVER_ARCACHE_WIDTH 4
#define RPU_RPU_0_AXI_OVER_ARCACHE_MASK ((u32)0X0000003CU)
#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_SHIFT 1
#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_WIDTH 1
#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_MASK ((u32)0X00000002U)
#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_SHIFT 0
#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_WIDTH 1
#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_1_CFG
*/
#define RPU_RPU_1_CFG ( ( RPU_BASEADDR ) + ((u32)0X00000200U) )
#define RPU_RPU_1_CFG_CFGNMFI1_SHIFT 3
#define RPU_RPU_1_CFG_CFGNMFI1_WIDTH 1
#define RPU_RPU_1_CFG_CFGNMFI1_MASK ((u32)0X00000008U)
#define RPU_RPU_1_CFG_VINITHI_SHIFT 2
#define RPU_RPU_1_CFG_VINITHI_WIDTH 1
#define RPU_RPU_1_CFG_VINITHI_MASK ((u32)0X00000004U)
#define RPU_RPU_1_CFG_COHERENT_SHIFT 1
#define RPU_RPU_1_CFG_COHERENT_WIDTH 1
#define RPU_RPU_1_CFG_COHERENT_MASK ((u32)0X00000002U)
#define RPU_RPU_1_CFG_NCPUHALT_SHIFT 0
#define RPU_RPU_1_CFG_NCPUHALT_WIDTH 1
#define RPU_RPU_1_CFG_NCPUHALT_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_1_STATUS
*/
#define RPU_RPU_1_STATUS ( ( RPU_BASEADDR ) + ((u32)0X00000204U) )
#define RPU_RPU_1_STATUS_NVALRESET_SHIFT 5
#define RPU_RPU_1_STATUS_NVALRESET_WIDTH 1
#define RPU_RPU_1_STATUS_NVALRESET_MASK ((u32)0X00000020U)
#define RPU_RPU_1_STATUS_NVALIRQ_SHIFT 4
#define RPU_RPU_1_STATUS_NVALIRQ_WIDTH 1
#define RPU_RPU_1_STATUS_NVALIRQ_MASK ((u32)0X00000010U)
#define RPU_RPU_1_STATUS_NVALFIQ_SHIFT 3
#define RPU_RPU_1_STATUS_NVALFIQ_WIDTH 1
#define RPU_RPU_1_STATUS_NVALFIQ_MASK ((u32)0X00000008U)
#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_SHIFT 2
#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_WIDTH 1
#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_MASK ((u32)0X00000004U)
#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_SHIFT 1
#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_WIDTH 1
#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_MASK ((u32)0X00000002U)
#define RPU_RPU_1_STATUS_NCLKSTOPPED_SHIFT 0
#define RPU_RPU_1_STATUS_NCLKSTOPPED_WIDTH 1
#define RPU_RPU_1_STATUS_NCLKSTOPPED_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_1_PWRDWN
*/
#define RPU_RPU_1_PWRDWN ( ( RPU_BASEADDR ) + ((u32)0X00000208U) )
#define RPU_RPU_1_PWRDWN_EN_SHIFT 0
#define RPU_RPU_1_PWRDWN_EN_WIDTH 1
#define RPU_RPU_1_PWRDWN_EN_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_1_ISR
*/
#define RPU_RPU_1_ISR ( ( RPU_BASEADDR ) + ((u32)0X00000214U) )
#define RPU_RPU_1_ISR_FPUFC_SHIFT 24
#define RPU_RPU_1_ISR_FPUFC_WIDTH 1
#define RPU_RPU_1_ISR_FPUFC_MASK ((u32)0X01000000U)
#define RPU_RPU_1_ISR_FPOFC_SHIFT 23
#define RPU_RPU_1_ISR_FPOFC_WIDTH 1
#define RPU_RPU_1_ISR_FPOFC_MASK ((u32)0X00800000U)
#define RPU_RPU_1_ISR_FPIXC_SHIFT 22
#define RPU_RPU_1_ISR_FPIXC_WIDTH 1
#define RPU_RPU_1_ISR_FPIXC_MASK ((u32)0X00400000U)
#define RPU_RPU_1_ISR_FPIOC_SHIFT 21
#define RPU_RPU_1_ISR_FPIOC_WIDTH 1
#define RPU_RPU_1_ISR_FPIOC_MASK ((u32)0X00200000U)
#define RPU_RPU_1_ISR_FPIDC_SHIFT 20
#define RPU_RPU_1_ISR_FPIDC_WIDTH 1
#define RPU_RPU_1_ISR_FPIDC_MASK ((u32)0X00100000U)
#define RPU_RPU_1_ISR_FPDZC_SHIFT 19
#define RPU_RPU_1_ISR_FPDZC_WIDTH 1
#define RPU_RPU_1_ISR_FPDZC_MASK ((u32)0X00080000U)
#define RPU_RPU_1_ISR_TCM_ASLV_CE_SHIFT 18
#define RPU_RPU_1_ISR_TCM_ASLV_CE_WIDTH 1
#define RPU_RPU_1_ISR_TCM_ASLV_CE_MASK ((u32)0X00040000U)
#define RPU_RPU_1_ISR_TCM_ASLV_FAT_SHIFT 17
#define RPU_RPU_1_ISR_TCM_ASLV_FAT_WIDTH 1
#define RPU_RPU_1_ISR_TCM_ASLV_FAT_MASK ((u32)0X00020000U)
#define RPU_RPU_1_ISR_TCM_LST_CE_SHIFT 16
#define RPU_RPU_1_ISR_TCM_LST_CE_WIDTH 1
#define RPU_RPU_1_ISR_TCM_LST_CE_MASK ((u32)0X00010000U)
#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_SHIFT 15
#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_WIDTH 1
#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_MASK ((u32)0X00008000U)
#define RPU_RPU_1_ISR_B1TCM_CE_SHIFT 14
#define RPU_RPU_1_ISR_B1TCM_CE_WIDTH 1
#define RPU_RPU_1_ISR_B1TCM_CE_MASK ((u32)0X00004000U)
#define RPU_RPU_1_ISR_B0TCM_CE_SHIFT 13
#define RPU_RPU_1_ISR_B0TCM_CE_WIDTH 1
#define RPU_RPU_1_ISR_B0TCM_CE_MASK ((u32)0X00002000U)
#define RPU_RPU_1_ISR_ATCM_CE_SHIFT 12
#define RPU_RPU_1_ISR_ATCM_CE_WIDTH 1
#define RPU_RPU_1_ISR_ATCM_CE_MASK ((u32)0X00001000U)
#define RPU_RPU_1_ISR_B1TCM_UE_SHIFT 11
#define RPU_RPU_1_ISR_B1TCM_UE_WIDTH 1
#define RPU_RPU_1_ISR_B1TCM_UE_MASK ((u32)0X00000800U)
#define RPU_RPU_1_ISR_B0TCM_UE_SHIFT 10
#define RPU_RPU_1_ISR_B0TCM_UE_WIDTH 1
#define RPU_RPU_1_ISR_B0TCM_UE_MASK ((u32)0X00000400U)
#define RPU_RPU_1_ISR_ATCM_UE_SHIFT 9
#define RPU_RPU_1_ISR_ATCM_UE_WIDTH 1
#define RPU_RPU_1_ISR_ATCM_UE_MASK ((u32)0X00000200U)
#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_SHIFT 8
#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_WIDTH 1
#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U)
#define RPU_RPU_1_ISR_DDATA_FAT_SHIFT 7
#define RPU_RPU_1_ISR_DDATA_FAT_WIDTH 1
#define RPU_RPU_1_ISR_DDATA_FAT_MASK ((u32)0X00000080U)
#define RPU_RPU_1_ISR_TCM_LST_FAT_SHIFT 6
#define RPU_RPU_1_ISR_TCM_LST_FAT_WIDTH 1
#define RPU_RPU_1_ISR_TCM_LST_FAT_MASK ((u32)0X00000040U)
#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_SHIFT 5
#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_WIDTH 1
#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U)
#define RPU_RPU_1_ISR_DDATA_CE_SHIFT 4
#define RPU_RPU_1_ISR_DDATA_CE_WIDTH 1
#define RPU_RPU_1_ISR_DDATA_CE_MASK ((u32)0X00000010U)
#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_SHIFT 3
#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_WIDTH 1
#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_MASK ((u32)0X00000008U)
#define RPU_RPU_1_ISR_IDATA_CE_SHIFT 2
#define RPU_RPU_1_ISR_IDATA_CE_WIDTH 1
#define RPU_RPU_1_ISR_IDATA_CE_MASK ((u32)0X00000004U)
#define RPU_RPU_1_ISR_ITAG_CE_SHIFT 1
#define RPU_RPU_1_ISR_ITAG_CE_WIDTH 1
#define RPU_RPU_1_ISR_ITAG_CE_MASK ((u32)0X00000002U)
#define RPU_RPU_1_ISR_APB_ERR_SHIFT 0
#define RPU_RPU_1_ISR_APB_ERR_WIDTH 1
#define RPU_RPU_1_ISR_APB_ERR_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_1_IMR
*/
#define RPU_RPU_1_IMR ( ( RPU_BASEADDR ) + ((u32)0X00000218U) )
#define RPU_RPU_1_IMR_FPUFC_SHIFT 24
#define RPU_RPU_1_IMR_FPUFC_WIDTH 1
#define RPU_RPU_1_IMR_FPUFC_MASK ((u32)0X01000000U)
#define RPU_RPU_1_IMR_FPOFC_SHIFT 23
#define RPU_RPU_1_IMR_FPOFC_WIDTH 1
#define RPU_RPU_1_IMR_FPOFC_MASK ((u32)0X00800000U)
#define RPU_RPU_1_IMR_FPIXC_SHIFT 22
#define RPU_RPU_1_IMR_FPIXC_WIDTH 1
#define RPU_RPU_1_IMR_FPIXC_MASK ((u32)0X00400000U)
#define RPU_RPU_1_IMR_FPIOC_SHIFT 21
#define RPU_RPU_1_IMR_FPIOC_WIDTH 1
#define RPU_RPU_1_IMR_FPIOC_MASK ((u32)0X00200000U)
#define RPU_RPU_1_IMR_FPIDC_SHIFT 20
#define RPU_RPU_1_IMR_FPIDC_WIDTH 1
#define RPU_RPU_1_IMR_FPIDC_MASK ((u32)0X00100000U)
#define RPU_RPU_1_IMR_FPDZC_SHIFT 19
#define RPU_RPU_1_IMR_FPDZC_WIDTH 1
#define RPU_RPU_1_IMR_FPDZC_MASK ((u32)0X00080000U)
#define RPU_RPU_1_IMR_TCM_ASLV_CE_SHIFT 18
#define RPU_RPU_1_IMR_TCM_ASLV_CE_WIDTH 1
#define RPU_RPU_1_IMR_TCM_ASLV_CE_MASK ((u32)0X00040000U)
#define RPU_RPU_1_IMR_TCM_ASLV_FAT_SHIFT 17
#define RPU_RPU_1_IMR_TCM_ASLV_FAT_WIDTH 1
#define RPU_RPU_1_IMR_TCM_ASLV_FAT_MASK ((u32)0X00020000U)
#define RPU_RPU_1_IMR_TCM_LST_CE_SHIFT 16
#define RPU_RPU_1_IMR_TCM_LST_CE_WIDTH 1
#define RPU_RPU_1_IMR_TCM_LST_CE_MASK ((u32)0X00010000U)
#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_SHIFT 15
#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_WIDTH 1
#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_MASK ((u32)0X00008000U)
#define RPU_RPU_1_IMR_B1TCM_CE_SHIFT 14
#define RPU_RPU_1_IMR_B1TCM_CE_WIDTH 1
#define RPU_RPU_1_IMR_B1TCM_CE_MASK ((u32)0X00004000U)
#define RPU_RPU_1_IMR_B0TCM_CE_SHIFT 13
#define RPU_RPU_1_IMR_B0TCM_CE_WIDTH 1
#define RPU_RPU_1_IMR_B0TCM_CE_MASK ((u32)0X00002000U)
#define RPU_RPU_1_IMR_ATCM_CE_SHIFT 12
#define RPU_RPU_1_IMR_ATCM_CE_WIDTH 1
#define RPU_RPU_1_IMR_ATCM_CE_MASK ((u32)0X00001000U)
#define RPU_RPU_1_IMR_B1TCM_UE_SHIFT 11
#define RPU_RPU_1_IMR_B1TCM_UE_WIDTH 1
#define RPU_RPU_1_IMR_B1TCM_UE_MASK ((u32)0X00000800U)
#define RPU_RPU_1_IMR_B0TCM_UE_SHIFT 10
#define RPU_RPU_1_IMR_B0TCM_UE_WIDTH 1
#define RPU_RPU_1_IMR_B0TCM_UE_MASK ((u32)0X00000400U)
#define RPU_RPU_1_IMR_ATCM_UE_SHIFT 9
#define RPU_RPU_1_IMR_ATCM_UE_WIDTH 1
#define RPU_RPU_1_IMR_ATCM_UE_MASK ((u32)0X00000200U)
#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_SHIFT 8
#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_WIDTH 1
#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U)
#define RPU_RPU_1_IMR_DDATA_FAT_SHIFT 7
#define RPU_RPU_1_IMR_DDATA_FAT_WIDTH 1
#define RPU_RPU_1_IMR_DDATA_FAT_MASK ((u32)0X00000080U)
#define RPU_RPU_1_IMR_TCM_LST_FAT_SHIFT 6
#define RPU_RPU_1_IMR_TCM_LST_FAT_WIDTH 1
#define RPU_RPU_1_IMR_TCM_LST_FAT_MASK ((u32)0X00000040U)
#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_SHIFT 5
#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_WIDTH 1
#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U)
#define RPU_RPU_1_IMR_DDATA_CE_SHIFT 4
#define RPU_RPU_1_IMR_DDATA_CE_WIDTH 1
#define RPU_RPU_1_IMR_DDATA_CE_MASK ((u32)0X00000010U)
#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_SHIFT 3
#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_WIDTH 1
#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_MASK ((u32)0X00000008U)
#define RPU_RPU_1_IMR_IDATA_CE_SHIFT 2
#define RPU_RPU_1_IMR_IDATA_CE_WIDTH 1
#define RPU_RPU_1_IMR_IDATA_CE_MASK ((u32)0X00000004U)
#define RPU_RPU_1_IMR_ITAG_CE_SHIFT 1
#define RPU_RPU_1_IMR_ITAG_CE_WIDTH 1
#define RPU_RPU_1_IMR_ITAG_CE_MASK ((u32)0X00000002U)
#define RPU_RPU_1_IMR_APB_ERR_SHIFT 0
#define RPU_RPU_1_IMR_APB_ERR_WIDTH 1
#define RPU_RPU_1_IMR_APB_ERR_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_1_IEN
*/
#define RPU_RPU_1_IEN ( ( RPU_BASEADDR ) + ((u32)0X0000021CU) )
#define RPU_RPU_1_IEN_FPUFC_SHIFT 24
#define RPU_RPU_1_IEN_FPUFC_WIDTH 1
#define RPU_RPU_1_IEN_FPUFC_MASK ((u32)0X01000000U)
#define RPU_RPU_1_IEN_FPOFC_SHIFT 23
#define RPU_RPU_1_IEN_FPOFC_WIDTH 1
#define RPU_RPU_1_IEN_FPOFC_MASK ((u32)0X00800000U)
#define RPU_RPU_1_IEN_FPIXC_SHIFT 22
#define RPU_RPU_1_IEN_FPIXC_WIDTH 1
#define RPU_RPU_1_IEN_FPIXC_MASK ((u32)0X00400000U)
#define RPU_RPU_1_IEN_FPIOC_SHIFT 21
#define RPU_RPU_1_IEN_FPIOC_WIDTH 1
#define RPU_RPU_1_IEN_FPIOC_MASK ((u32)0X00200000U)
#define RPU_RPU_1_IEN_FPIDC_SHIFT 20
#define RPU_RPU_1_IEN_FPIDC_WIDTH 1
#define RPU_RPU_1_IEN_FPIDC_MASK ((u32)0X00100000U)
#define RPU_RPU_1_IEN_FPDZC_SHIFT 19
#define RPU_RPU_1_IEN_FPDZC_WIDTH 1
#define RPU_RPU_1_IEN_FPDZC_MASK ((u32)0X00080000U)
#define RPU_RPU_1_IEN_TCM_ASLV_CE_SHIFT 18
#define RPU_RPU_1_IEN_TCM_ASLV_CE_WIDTH 1
#define RPU_RPU_1_IEN_TCM_ASLV_CE_MASK ((u32)0X00040000U)
#define RPU_RPU_1_IEN_TCM_ASLV_FAT_SHIFT 17
#define RPU_RPU_1_IEN_TCM_ASLV_FAT_WIDTH 1
#define RPU_RPU_1_IEN_TCM_ASLV_FAT_MASK ((u32)0X00020000U)
#define RPU_RPU_1_IEN_TCM_LST_CE_SHIFT 16
#define RPU_RPU_1_IEN_TCM_LST_CE_WIDTH 1
#define RPU_RPU_1_IEN_TCM_LST_CE_MASK ((u32)0X00010000U)
#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_SHIFT 15
#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_WIDTH 1
#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_MASK ((u32)0X00008000U)
#define RPU_RPU_1_IEN_B1TCM_CE_SHIFT 14
#define RPU_RPU_1_IEN_B1TCM_CE_WIDTH 1
#define RPU_RPU_1_IEN_B1TCM_CE_MASK ((u32)0X00004000U)
#define RPU_RPU_1_IEN_B0TCM_CE_SHIFT 13
#define RPU_RPU_1_IEN_B0TCM_CE_WIDTH 1
#define RPU_RPU_1_IEN_B0TCM_CE_MASK ((u32)0X00002000U)
#define RPU_RPU_1_IEN_ATCM_CE_SHIFT 12
#define RPU_RPU_1_IEN_ATCM_CE_WIDTH 1
#define RPU_RPU_1_IEN_ATCM_CE_MASK ((u32)0X00001000U)
#define RPU_RPU_1_IEN_B1TCM_UE_SHIFT 11
#define RPU_RPU_1_IEN_B1TCM_UE_WIDTH 1
#define RPU_RPU_1_IEN_B1TCM_UE_MASK ((u32)0X00000800U)
#define RPU_RPU_1_IEN_B0TCM_UE_SHIFT 10
#define RPU_RPU_1_IEN_B0TCM_UE_WIDTH 1
#define RPU_RPU_1_IEN_B0TCM_UE_MASK ((u32)0X00000400U)
#define RPU_RPU_1_IEN_ATCM_UE_SHIFT 9
#define RPU_RPU_1_IEN_ATCM_UE_WIDTH 1
#define RPU_RPU_1_IEN_ATCM_UE_MASK ((u32)0X00000200U)
#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_SHIFT 8
#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_WIDTH 1
#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U)
#define RPU_RPU_1_IEN_DDATA_FAT_SHIFT 7
#define RPU_RPU_1_IEN_DDATA_FAT_WIDTH 1
#define RPU_RPU_1_IEN_DDATA_FAT_MASK ((u32)0X00000080U)
#define RPU_RPU_1_IEN_TCM_LST_FAT_SHIFT 6
#define RPU_RPU_1_IEN_TCM_LST_FAT_WIDTH 1
#define RPU_RPU_1_IEN_TCM_LST_FAT_MASK ((u32)0X00000040U)
#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_SHIFT 5
#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_WIDTH 1
#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U)
#define RPU_RPU_1_IEN_DDATA_CE_SHIFT 4
#define RPU_RPU_1_IEN_DDATA_CE_WIDTH 1
#define RPU_RPU_1_IEN_DDATA_CE_MASK ((u32)0X00000010U)
#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_SHIFT 3
#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_WIDTH 1
#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_MASK ((u32)0X00000008U)
#define RPU_RPU_1_IEN_IDATA_CE_SHIFT 2
#define RPU_RPU_1_IEN_IDATA_CE_WIDTH 1
#define RPU_RPU_1_IEN_IDATA_CE_MASK ((u32)0X00000004U)
#define RPU_RPU_1_IEN_ITAG_CE_SHIFT 1
#define RPU_RPU_1_IEN_ITAG_CE_WIDTH 1
#define RPU_RPU_1_IEN_ITAG_CE_MASK ((u32)0X00000002U)
#define RPU_RPU_1_IEN_APB_ERR_SHIFT 0
#define RPU_RPU_1_IEN_APB_ERR_WIDTH 1
#define RPU_RPU_1_IEN_APB_ERR_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_1_IDS
*/
#define RPU_RPU_1_IDS ( ( RPU_BASEADDR ) + ((u32)0X00000220U) )
#define RPU_RPU_1_IDS_FPUFC_SHIFT 24
#define RPU_RPU_1_IDS_FPUFC_WIDTH 1
#define RPU_RPU_1_IDS_FPUFC_MASK ((u32)0X01000000U)
#define RPU_RPU_1_IDS_FPOFC_SHIFT 23
#define RPU_RPU_1_IDS_FPOFC_WIDTH 1
#define RPU_RPU_1_IDS_FPOFC_MASK ((u32)0X00800000U)
#define RPU_RPU_1_IDS_FPIXC_SHIFT 22
#define RPU_RPU_1_IDS_FPIXC_WIDTH 1
#define RPU_RPU_1_IDS_FPIXC_MASK ((u32)0X00400000U)
#define RPU_RPU_1_IDS_FPIOC_SHIFT 21
#define RPU_RPU_1_IDS_FPIOC_WIDTH 1
#define RPU_RPU_1_IDS_FPIOC_MASK ((u32)0X00200000U)
#define RPU_RPU_1_IDS_FPIDC_SHIFT 20
#define RPU_RPU_1_IDS_FPIDC_WIDTH 1
#define RPU_RPU_1_IDS_FPIDC_MASK ((u32)0X00100000U)
#define RPU_RPU_1_IDS_FPDZC_SHIFT 19
#define RPU_RPU_1_IDS_FPDZC_WIDTH 1
#define RPU_RPU_1_IDS_FPDZC_MASK ((u32)0X00080000U)
#define RPU_RPU_1_IDS_TCM_ASLV_CE_SHIFT 18
#define RPU_RPU_1_IDS_TCM_ASLV_CE_WIDTH 1
#define RPU_RPU_1_IDS_TCM_ASLV_CE_MASK ((u32)0X00040000U)
#define RPU_RPU_1_IDS_TCM_ASLV_FAT_SHIFT 17
#define RPU_RPU_1_IDS_TCM_ASLV_FAT_WIDTH 1
#define RPU_RPU_1_IDS_TCM_ASLV_FAT_MASK ((u32)0X00020000U)
#define RPU_RPU_1_IDS_TCM_LST_CE_SHIFT 16
#define RPU_RPU_1_IDS_TCM_LST_CE_WIDTH 1
#define RPU_RPU_1_IDS_TCM_LST_CE_MASK ((u32)0X00010000U)
#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_SHIFT 15
#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_WIDTH 1
#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_MASK ((u32)0X00008000U)
#define RPU_RPU_1_IDS_B1TCM_CE_SHIFT 14
#define RPU_RPU_1_IDS_B1TCM_CE_WIDTH 1
#define RPU_RPU_1_IDS_B1TCM_CE_MASK ((u32)0X00004000U)
#define RPU_RPU_1_IDS_B0TCM_CE_SHIFT 13
#define RPU_RPU_1_IDS_B0TCM_CE_WIDTH 1
#define RPU_RPU_1_IDS_B0TCM_CE_MASK ((u32)0X00002000U)
#define RPU_RPU_1_IDS_ATCM_CE_SHIFT 12
#define RPU_RPU_1_IDS_ATCM_CE_WIDTH 1
#define RPU_RPU_1_IDS_ATCM_CE_MASK ((u32)0X00001000U)
#define RPU_RPU_1_IDS_B1TCM_UE_SHIFT 11
#define RPU_RPU_1_IDS_B1TCM_UE_WIDTH 1
#define RPU_RPU_1_IDS_B1TCM_UE_MASK ((u32)0X00000800U)
#define RPU_RPU_1_IDS_B0TCM_UE_SHIFT 10
#define RPU_RPU_1_IDS_B0TCM_UE_WIDTH 1
#define RPU_RPU_1_IDS_B0TCM_UE_MASK ((u32)0X00000400U)
#define RPU_RPU_1_IDS_ATCM_UE_SHIFT 9
#define RPU_RPU_1_IDS_ATCM_UE_WIDTH 1
#define RPU_RPU_1_IDS_ATCM_UE_MASK ((u32)0X00000200U)
#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_SHIFT 8
#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_WIDTH 1
#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U)
#define RPU_RPU_1_IDS_DDATA_FAT_SHIFT 7
#define RPU_RPU_1_IDS_DDATA_FAT_WIDTH 1
#define RPU_RPU_1_IDS_DDATA_FAT_MASK ((u32)0X00000080U)
#define RPU_RPU_1_IDS_TCM_LST_FAT_SHIFT 6
#define RPU_RPU_1_IDS_TCM_LST_FAT_WIDTH 1
#define RPU_RPU_1_IDS_TCM_LST_FAT_MASK ((u32)0X00000040U)
#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_SHIFT 5
#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_WIDTH 1
#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U)
#define RPU_RPU_1_IDS_DDATA_CE_SHIFT 4
#define RPU_RPU_1_IDS_DDATA_CE_WIDTH 1
#define RPU_RPU_1_IDS_DDATA_CE_MASK ((u32)0X00000010U)
#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_SHIFT 3
#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_WIDTH 1
#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_MASK ((u32)0X00000008U)
#define RPU_RPU_1_IDS_IDATA_CE_SHIFT 2
#define RPU_RPU_1_IDS_IDATA_CE_WIDTH 1
#define RPU_RPU_1_IDS_IDATA_CE_MASK ((u32)0X00000004U)
#define RPU_RPU_1_IDS_ITAG_CE_SHIFT 1
#define RPU_RPU_1_IDS_ITAG_CE_WIDTH 1
#define RPU_RPU_1_IDS_ITAG_CE_MASK ((u32)0X00000002U)
#define RPU_RPU_1_IDS_APB_ERR_SHIFT 0
#define RPU_RPU_1_IDS_APB_ERR_WIDTH 1
#define RPU_RPU_1_IDS_APB_ERR_MASK ((u32)0X00000001U)
/**
* Register: RPU_RPU_1_SLV_BASE
*/
#define RPU_RPU_1_SLV_BASE ( ( RPU_BASEADDR ) + ((u32)0X00000224U) )
#define RPU_RPU_1_SLV_BASE_ADDR_SHIFT 0
#define RPU_RPU_1_SLV_BASE_ADDR_WIDTH 8
#define RPU_RPU_1_SLV_BASE_ADDR_MASK ((u32)0X000000FFU)
/**
* Register: RPU_RPU_1_AXI_OVER
*/
#define RPU_RPU_1_AXI_OVER ( ( RPU_BASEADDR ) + ((u32)0X00000228U) )
#define RPU_RPU_1_AXI_OVER_AWCACHE_SHIFT 6
#define RPU_RPU_1_AXI_OVER_AWCACHE_WIDTH 4
#define RPU_RPU_1_AXI_OVER_AWCACHE_MASK ((u32)0X000003C0U)
#define RPU_RPU_1_AXI_OVER_ARCACHE_SHIFT 2
#define RPU_RPU_1_AXI_OVER_ARCACHE_WIDTH 4
#define RPU_RPU_1_AXI_OVER_ARCACHE_MASK ((u32)0X0000003CU)
#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_SHIFT 1
#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_WIDTH 1
#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_MASK ((u32)0X00000002U)
#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_SHIFT 0
#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_WIDTH 1
#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_MASK ((u32)0X00000001U)
#ifdef __cplusplus
}
#endif
#endif /* _RPU_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_common.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_COMMON_H_
#define XPM_COMMON_H_
#include "xstatus.h"
#include "xil_io.h"
#include "xpm_err.h"
#include "xplmi_debug.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Hack: These will increase code size. Define them as needed. */
#define xSELF_TEST
#define xSELF_TEST_DEVICE_REQUEST
#define xSELF_TEST_PIN_API
#define xSELF_TEST_RESET_API
#define xSELF_TEST_CLOCK_API
#define xDEBUG_REG_IO
#define TRUE 1U
#define FALSE 0U
/**
* GCC Specific attribute to suppress unused variable/function warning
*/
#ifndef maybe_unused
#define maybe_unused __attribute__((unused))
#endif
/* Debug logs */
#define PmAlert(...) \
XPlmi_Printf(DEBUG_GENERAL, "[ALERT] %s: ", __func__); \
XPlmi_Printf(DEBUG_GENERAL, __VA_ARGS__)
#define PmErr(...) \
XPlmi_Printf(DEBUG_GENERAL, "[ERROR] %s: ", __func__); \
XPlmi_Printf(DEBUG_GENERAL, __VA_ARGS__)
#define PmWarn(...) \
XPlmi_Printf(DEBUG_GENERAL, "[WARN] %s: ", __func__); \
XPlmi_Printf(DEBUG_GENERAL, __VA_ARGS__)
#define PmInfo(...) \
XPlmi_Printf(DEBUG_INFO, "[INFO] %s: ", __func__); \
XPlmi_Printf(DEBUG_INFO, __VA_ARGS__)
#define PmDbg(...) \
XPlmi_Printf(DEBUG_DETAILED, "[DEBUG] %s: ", __func__); \
XPlmi_Printf(DEBUG_DETAILED, __VA_ARGS__)
#ifdef DEBUG_REG_IO
#define PmIn32(ADDR, VAL) \
(VAL) = XPm_In32(ADDR); \
PmInfo("Read from 0x%08X: 0x%08X\n\r", ADDR, VAL); \
#define PmOut32(ADDR, VAL) \
PmInfo("Write to 0x%08X: 0x%08X\n\r", ADDR, VAL); \
XPm_Out32(ADDR, VAL);
#define PmRmw32(ADDR, MASK, VAL) \
XPm_RMW32(ADDR, MASK, VAL); \
PmInfo("RMW: Addr=0x%08X, Mask=0x%08X, Val=0x%08X, Reg=0x%08X\n\r", \
ADDR, MASK, VAL, XPm_In32(ADDR));
#else
#define PmIn32(ADDR, VAL) \
(VAL) = XPm_In32(ADDR);
#define PmOut32(ADDR, VAL) \
XPm_Out32(ADDR, VAL);
#define PmRmw32(ADDR, MASK, VAL) \
XPm_RMW32(ADDR, MASK, VAL);
#endif
#define BIT(n) (1U << (n))
#define BIT8(n) ((u8)1U << (n))
#define BIT16(n) ((u16)1U << (n))
#define BIT32(n) ((u32)1U << (n))
// set the first n bits to 1, rest to 0
#define BITMASK(n) (u32)((1ULL << (n)) - 1ULL)
// set width specified bits at offset to 1, rest to 0
#define BITNMASK(offset, width) (BITMASK(width) << (offset))
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define XPm_Read32 XPm_In32
#define XPm_Write32 XPm_Out32
#define PLATFORM_VERSION_SILICON (0x0U)
#define PLATFORM_VERSION_SPP (0x1U)
#define PLATFORM_VERSION_EMU (0x2U)
#define PLATFORM_VERSION_QEMU (0x3U)
#define PLATFORM_VERSION_FCV (0x4U)
#define PLATFORM_VERSION_SILICON_ES1 (0x0U)
#define SLR_TYPE_MONOLITHIC_DEV (0x7U)
#define SLR_TYPE_SSIT_DEV_MASTER_SLR (0x6U)
#define SLR_TYPE_SSIT_DEV_SLAVE_1_SLR_TOP (0x5U)
#define SLR_TYPE_SSIT_DEV_SLAVE_1_SLR_NTOP (0x4U)
#define SLR_TYPE_SSIT_DEV_SLAVE_2_SLR_TOP (0x3U)
#define SLR_TYPE_SSIT_DEV_SLAVE_2_SLR_NTOP (0x2U)
#define SLR_TYPE_SSIT_DEV_SLAVE_3_SLR_TOP (0x1U)
#define SLR_TYPE_INVALID (0x0U)
extern u32 Platform;
extern u32 PlatformVersion;
extern u32 SlrType;
void *XPm_AllocBytes(u32 Size);
void XPm_Out32(u32 RegAddress, u32 l_Val);
u32 XPm_In32(u32 RegAddress);
/**
* Read Modify Write a register
*/
void XPm_RMW32(u32 RegAddress, u32 Mask, u32 Value);
/**
* Wait for a period represented by TimeOut
*
*/
void XPm_Wait(u32 TimeOutCount);
/**
* Poll for mask for a period represented by TimeOut
*/
XStatus XPm_PollForMask(u32 RegAddress, u32 Mask, u32 TimeOutCount);
XStatus XPm_PollForZero(u32 RegAddress, u32 Mask, u32 TimeOutCount);
/**
* Compute parity of a 32-bit word
*/
u32 XPm_ComputeParity(u32 Value);
/* Dump Memory Related Data like Total Mem, Usaged Mem, Free Mem */
void XPm_DumpMemUsage(void);
#ifdef __cplusplus
}
#endif
#endif /* XPM_COMMON_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_mod_wdt.c
/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_default.h"
#include "xpfw_config.h"
#include "xpfw_core.h"
#include "xpfw_module.h"
#include "xpfw_mod_wdt.h"
#ifdef ENABLE_WDT
#include "xwdtps.h"
/* Check if PMU has access to CSU WDT (psu_csu_wdt) */
#ifdef XPAR_PSU_CSU_WDT_DEVICE_ID
#include "xwdtps.h"
#else /* XPAR_PSU_CSU_WDT_DEVICE_ID */
#error "ENABLE_WDT is defined but psu_csu_wdt is not defined in the design"
#endif
/* Instance of WDT Driver */
static XWdtPs WdtInst;
static XWdtPs *WdtInstPtr = &WdtInst;
/*
* WDT expire time in milliseconds.
*/
#define XPFW_WDT_EXPIRE_TIME XPFW_CFG_PMU_DEFAULT_WDT_TIMEOUT
/*
* WDT restart time in milliseconds.
*/
#define XPFW_WDT_RESTART_TIME 50U
#define XPFW_WDT_CRV_SHIFT 12U
#define XPFW_WDT_PRESCALER 8U
#define XPFW_WDT_CLK_PER_MSEC ((XPAR_PSU_CSU_WDT_WDT_CLK_FREQ_HZ) / (XPFW_WDT_PRESCALER * 1000U))
#define XPFW_WDT_COUNTER_VAL ((XPFW_WDT_EXPIRE_TIME) * (XPFW_WDT_CLK_PER_MSEC))
const XPfw_Module_t *WdtModPtr;
/****************************************************************************/
/**
* @brief This scheduler task restarts CSU PMU WDT.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
static void XPfw_WdtRestart(void)
{
if (WdtInstPtr != NULL) {
XWdtPs_RestartWdt(WdtInstPtr);
}
}
/****************************************************************************/
/**
* @brief This scheduler sets the watchdog timer.
*
* @param TimeOutVal - Watchdog timeout in ms.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XPfw_WdtSetVal(u32 TimeOutVal)
{
u32 CounterValue;
if (TimeOutVal > 0U) {
/* Stop the Watchdog timer */
XWdtPs_Stop(WdtInstPtr);
/* Watchdog counter reset value for Expire time of 100Sec,
* i.e., XPFW_WDT_EXPIRE_TIME
*/
CounterValue = ((TimeOutVal) * (XPFW_WDT_CLK_PER_MSEC)) >> XPFW_WDT_CRV_SHIFT;
/* Set the Watchdog counter reset value */
XWdtPs_SetControlValue(WdtInstPtr, XWDTPS_COUNTER_RESET,
CounterValue);
/* Enable reset output */
XWdtPs_EnableOutput(WdtInstPtr, XWDTPS_RESET_SIGNAL);
/* Start the Watchdog timer */
XWdtPs_Start(WdtInstPtr);
XWdtPs_RestartWdt(WdtInstPtr);
}
}
/****************************************************************************/
/**
* @brief This function initializes the CSU PMU Watchdog timer.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void InitCsuPmuWdt(void)
{
s32 Status;
XWdtPs_Config *WdtConfigPtr;
u32 CounterValue;
XPfw_Printf(DEBUG_DETAILED, "In InitCsuPmuWdt\r\n");
/* Load Config for WDT */
WdtConfigPtr = XWdtPs_LookupConfig(XPAR_PSU_CSU_WDT_DEVICE_ID);
if (NULL == WdtConfigPtr) {
Status = XST_FAILURE;
XPfw_Printf(DEBUG_ERROR,"WDT (MOD-%d): WDT LookupConfig failed.\r\n",
WdtModPtr->ModId);
goto Done;
}
/* Initialize the WDT driver */
Status = XWdtPs_CfgInitialize(WdtInstPtr, WdtConfigPtr,
WdtConfigPtr->BaseAddress);
if (XST_FAILURE == Status) {
XPfw_Printf(DEBUG_ERROR,"WDT (MOD-%d): Initialization failed.\r\n",
WdtModPtr->ModId);
goto Done;
}
/* Setting the divider value */
XWdtPs_SetControlValue(WdtInstPtr, XWDTPS_CLK_PRESCALE,
XWDTPS_CCR_PSCALE_0008);
/* Watchdog counter reset value for Expire time of 100Sec,
* i.e., XPFW_WDT_EXPIRE_TIME
*/
CounterValue = XPFW_WDT_COUNTER_VAL >> XPFW_WDT_CRV_SHIFT;
/* Set the Watchdog counter reset value */
XWdtPs_SetControlValue(WdtInstPtr, XWDTPS_COUNTER_RESET,
CounterValue);
/* Enable reset output */
XWdtPs_EnableOutput(WdtInstPtr, XWDTPS_RESET_SIGNAL);
/* Start the Watchdog timer */
XWdtPs_Start(WdtInstPtr);
XWdtPs_RestartWdt(WdtInstPtr);
Status = XPfw_CoreScheduleTask(WdtModPtr, XPFW_WDT_RESTART_TIME, XPfw_WdtRestart);
if (XST_FAILURE == Status) {
XPfw_Printf(DEBUG_ERROR,"WDT (MOD-%d):Scheduling WDT restart failed.",
WdtModPtr->ModId);
}
XPfw_Printf(DEBUG_DETAILED,"WDT (MOD-%d): Initialized.\r\n", WdtModPtr->ModId);
Done:
return;
}
/****************************************************************************/
/**
* @brief WDT module init
*
* @param ModPtr Module pointer
* CfgData Module config data
* Len Length of config data
*
* @return None.
*
* @note None.
*
****************************************************************************/
static void WdtCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
{
}
void ModWdtInit(void)
{
WdtModPtr = XPfw_CoreCreateMod();
if (XST_SUCCESS != XPfw_CoreSetCfgHandler(WdtModPtr, WdtCfgInit)) {
XPfw_Printf(DEBUG_DETAILED,"WDT: Set Cfg handler failed\r\n");
}
}
#else /* ENABLE_WDT */
void ModWdtInit(void) { }
#endif /* ENABLE_WDT */
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/zdma_v1_9/src/xzdma_sinit.c
/******************************************************************************
* Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xzdma_sinit.c
* @addtogroup zdma_v1_9
* @{
*
* This file contains static initialization methods for Xilinx ZDMA core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 1.0 vns 2/27/15 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xzdma.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* XZDma_LookupConfig returns a reference to an XZDma_Config structure
* based on the unique device id, <i>DeviceId</i>. The return value will refer
* to an entry in the device configuration table defined in the xzdma_g.c
* file.
*
* @param DeviceId is the unique device ID of the device for the lookup
* operation.
*
* @return CfgPtr is a reference to a config record in the configuration
* table (in xzdma_g.c) corresponding to <i>DeviceId</i>, or
* NULL if no match is found.
*
* @note None.
******************************************************************************/
XZDma_Config *XZDma_LookupConfig(u16 DeviceId)
{
extern XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES];
XZDma_Config *CfgPtr = NULL;
u32 Index;
/* Checks all the instances */
for (Index = (u32)0x0; Index < (u32)(XPAR_XZDMA_NUM_INSTANCES);
Index++) {
if (XZDma_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XZDma_ConfigTable[Index];
break;
}
}
return (XZDma_Config *)CfgPtr;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pmcdomain.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PMCDOMAIN_H_
#define XPM_PMCDOMAIN_H_
#include "xpm_powerdomain.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct XPm_PmcDomain XPm_PmcDomain;
/**
* The PMC power domain node class.
*/
struct XPm_PmcDomain {
XPm_PowerDomain Domain; /**< Power: Power domain base class */
};
/************************** Function Prototypes ******************************/
XStatus XPmPmcDomain_Init(XPm_PmcDomain *PmcDomain, u32 Id);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_PMCDOMAIN_H_ */
<file_sep>/python_drivers/alice_pulse_stream_test.py
# -*- coding: utf-8 -*-
"""
Created on Fri Jul 24 11:14:53 2020
@author: tianlab01
"""
import time
import time_sync
import james_utils
import tdc_wrapper
import random
import datetime
import james_utils
logfile = "stream_test_results_2_10_200k.txt"
def log_to_file(test_num, test_series_num, stream_len, succ, num_errors, num_no_photon, num_bad_range, num_neg_offset, sent_stream, received_stream):
file = open(logfile,'a')
new_line = str(test_num) + ", " + str(test_series_num) + ", " + str(stream_len) + ", success:, " + str(succ) + ", num errors:," + str(num_errors)
new_line += ", num_no_photon," + str(num_no_photon) + ", num_bad_range," + str(num_bad_range) + ", num_neg_offset," + str(num_neg_offset)
#new_line += ", Sent:, "
#for s in sent_stream:
# new_line += str(s) + ", "
#new_line += "Received:, "
#for s in received_stream:
# new_line += str(s) + ", "
file.write(new_line + "\n")
file.close()
return
bob_ip = "192.168.56.1"
tdc_ip = "192.168.56.1"
tdc = tdc_wrapper.tdc_wrapper(3,0,tdc_wrapper.MODE_CLIENT,bob_ip)
ts = time_sync.time_sync(james_utils.ALICE_PORT, bob_ip, time_sync.CLIENT, tdc)
#log file format is num, val sent, val received, error (1 if yes), successfully deccoded (1 if yess)
count = 0
#is working and tested
#bin_size = 16000 #in ps
bin_size = 100000 #in ps
bin_number = 4#can encode values between 0 and 15
period = 500000 #in ps
#period = 100000 #in ps
#Working with 16 bins#
#bin_size = 8000 #in ps
#bin_number = 16#can encode values between 0 and 15
#period = 140000 #in ps
#Faster with 32 bins, working
#bin_size = 8000 #in ps
#bin_number = 16#can encode values between 0 and 15
#period = 280000 #in ps
num_sync_pulse = 100
num_dead_pulse = 20
pulse_len = 16
pulse_amp = 0x7FFF
num_leading_0s = 0
num_runs_per_len = 200
#Lists for doing analysis
len_list = []
perc_errs_list = [] #Percentage of errors in pulse decoding
#External experimental factors to be recorded
attenuation = 21.6 # in dB
laser_power = 0.7 # in mW
light_counts = 216 # in thousands per second
dark_counts = 1.1 # in thousands per second
file = open(logfile,'a')
file.write(datetime.datetime.now().strftime("\n================\n%I:%M%p on %B %d, %Y\n"))
file.write("bin_size = " + str(bin_size) + ", bin_number = " + str(bin_number) + ", period = " + str(period) + ", num sync pulses = " + str(num_sync_pulse) + ", pulse len (samples) = " + str(pulse_len) + ", pulse amp = " + hex(pulse_amp) + ", leading 0s = " + str(num_leading_0s) + ", laser power: " + str(laser_power) + "mW, attenuation: " + str(attenuation) + "dB, light counts per s: " + str(light_counts) + "k, dark counts per s: " + str(dark_counts) + "k\n")
file.write("test num, test num for this # of photons, number of photons\n")
file.close()
res = 0
res += ts.set_bin_size(bin_size)
res += ts.set_bin_number(bin_number)
res += ts.set_period(period)
exit_test = 0
if(res):
print("Failed to set encoding parameters, aborting..")
else:
#2600
#16300
for stream_len in range(100, 400, 10):
if(exit_test):
break
errs_total = 0
for test_num in range(0, num_runs_per_len):
if(exit_test):
break
try:
print("================================================================")
print("Test num: " + str(count) + ", series num: " + str(test_num) + ", num values: " + str(stream_len))
test_stream = []
for i in range(0, stream_len):
test_stream.append(random.randint(0,bin_number - 1))
#if(i >= num_leading_0s):
# test_stream.append(i%bin_number)
#else:
#pad with leading 0s
# test_stream.append(0)
sent_str = "Sending: "
for i in test_stream:
sent_str += str(i) + ", "
#print(sent_str)
res, a, b = ts.send_stream(test_stream, num_sync_pulse, num_dead_pulse, pulse_len, pulse_amp)
if(res == -1):
print("Stream transmission failed, exiting")
print(sent_str)
exit_test = 1
break
else:
print("Stream transmission success")
sent_str = "Sent: "
for i in test_stream:
sent_str += str(i) + ", "
num_no_photon = 0
num_neg_offset = 0
num_bad_range = 0
res_str = "Got: "
for i in res:
if(i == james_utils.FAIL_TIMESTAMP_NEG_OFFSET):
num_neg_offset += 1
if(i == james_utils.FAIL_TIMESTAMP_NO_PHOTON):
num_no_photon += 1
if(i == james_utils.FAIL_TIMESTAMP_BAD_RANGE):
num_bad_range += 1
if(i < 100):
res_str += str(i) + ", "
elif (i == james_utils.FAIL_TIMESTAMP_BAD_RANGE):
res_str += "br,"
elif (i == james_utils.FAIL_TIMESTAMP_NO_PHOTON):
res_str += "np,"
else:
res_str += ".,"
print(sent_str)
print(res_str)
errs = len(test_stream) - james_utils.check_results(test_stream, res)
print("Errors: " + str(errs))
errs_total += errs
log_to_file(count, test_num, stream_len, 0, errs, num_no_photon, num_bad_range, num_neg_offset, test_stream, res)
count += 1
print("Waiting 3 seconds...")
time.sleep(1)
#exit_test = 1
except KeyboardInterrupt:
print("Exiting")
exit_test = 1
break
len_list.append(stream_len)
perc_errs_list.append(100*errs_total/(stream_len*num_runs_per_len))
#Append the final results
new_line = "\n\n=================================================\nFinal results: \n num_encoded_pulses:"
for l in len_list:
new_line += ","+str(l)
new_line += "\n percent_error:"
for p in perc_errs_list:
new_line += ","+str(p)
new_line += "\n=============================================\n\n\n\n"
print(new_line)
file = open(logfile,'a')
file.write(new_line + "\n")
file.close()
ts.board.close_board()
print("Done testing") <file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_npdomain.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_NPDOMAIN_H_
#define XPM_NPDOMAIN_H_
#include "xpm_powerdomain.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* The NOC power domain node class.
*/
typedef struct XPm_NpDomain {
XPm_PowerDomain Domain; /**< Power domain node base class */
u8 BisrDataCopied;
} XPm_NpDomain;
/************************** Function Prototypes ******************************/
XStatus XPmNpDomain_Init(XPm_NpDomain *Npd, u32 Id, u32 BaseAddress,
XPm_Power *Parent);
XStatus XPmNpDomain_MemIcInit(u32 DeviceId, u32 BaseAddr);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_NPDOMAIN_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_restart.c
/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_default.h"
#include "pm_master.h"
#include "xpfw_ipi_manager.h"
#include "xpfw_platform.h"
#include "crl_apb.h"
#include "xpfw_error_manager.h"
#include "ipi.h"
#include "csu.h"
#include "pm_reset.h"
#include "xpfw_resets.h"
#include "xpfw_restart.h"
#include "pm_csudma.h"
#include "xpfw_aib.h"
#if defined(USE_DDR_FOR_APU_RESTART) && defined(ENABLE_SECURE)
#include "xsecure_sha.h"
static XSecure_Sha3 Sha3Instance;
#endif
FSBL_Store_Restore_Info_Struct FSBL_Store_Restore_Info = {0U};
#ifdef ENABLE_RECOVERY
#define XPFW_RESTART_SCOPE_REG PMU_GLOBAL_GLOBAL_GEN_STORAGE4
#define XPFW_RESTART_SCOPE_SHIFT (3U)
#define XPFW_RESTART_SCOPE_MASK (0x3U << XPFW_RESTART_SCOPE_SHIFT)
#ifdef CHECK_HEALTHY_BOOT
#define XPFW_BOOT_HEALTH_STS PMU_GLOBAL_GLOBAL_GEN_STORAGE4
#define XPFW_BOOT_HEALTH_GOOD (0x1U)
#endif
/* Macros used to track the phases in restart */
#define XPFW_RESTART_STATE_BOOT 0U
#define XPFW_RESTART_STATE_INPROGRESS 1U
#define XPFW_RESTART_STATE_DONE 2U
/* Check if PMU has access to FPD WDT (psu_wdt_1) and LPD WDT (psu_wdt_0)*/
#if defined(XPAR_PSU_WDT_1_DEVICE_ID) && defined(XPAR_PSU_WDT_0_DEVICE_ID)
#include "xwdtps.h"
#define WDT_INSTANCE_COUNT XPAR_XWDTPS_NUM_INSTANCES
#else /* XPAR_PSU_WDT_1_DEVICE_ID */
#error "ENABLE_RECOVERY is defined but psu_wdt_0 & psu_wdt_1 is not assigned to PMU"
#endif
/* Check if PMU has access to TTC_9 */
#ifdef XPAR_PSU_TTC_9_DEVICE_ID
#include "xttcps.h"
#else /* XPAR_PSU_TTC_9_DEVICE_ID */
#error "ENABLE_RECOVERY is defined but psu_tcc_9 is not assigned to PMU, APU recovery will not work"
#endif
/* Check if a timeout value was provided in build flags else default to 120 secs */
#if (RECOVERY_TIMEOUT > 0U)
#define WDT_DEFAULT_TIMEOUT_SEC RECOVERY_TIMEOUT
#else
#define WDT_DEFAULT_TIMEOUT_SEC 60U
#endif
/* Assign default values for WDT params assuming default config */
#define WDT_CRV_SHIFT 12U
#define WDT_PRESCALER 4096U
#define WDT_CLK_PER_SEC ((XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ) / (WDT_PRESCALER))
#define TTC_PRESCALER 15U
#define TTC_COUNT_PER_SEC (XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ / 65535U)
#define TTC_DEFAULT_NOTIFY_TIMEOUT_SEC 0U
/* FPD WDT driver instance used within this file */
static XWdtPs WdtInstance;
/* TTC driver instance used within this file */
static XTtcPs FpdTtcInstance;
/* Data strcuture to track restart phases for a Master */
typedef struct XPfwRestartTracker {
PmMaster *Master; /* Master whose restart cycle is being tracked */
u8 RestartState; /* Track different phases in restart cycle */
u8 RestartScope; /* Restart scope upon WDT */
u32 WdtBaseAddress; /* Base address for WDT assigend to this master */
u8 WdtTimeout; /* Timeout value for WDT */
u8 ErrorId; /* Error Id corresponding to the WDT */
XWdtPs* WdtPtr; /* Pointer to WDT for this master */
u32 WdtResetId; /* WDT reset ID */
u16 TtcDeviceId; /* TTC timer device ID */
XTtcPs *TtcPtr; /* Pointer to TTC for this master */
u8 TtcTimeout; /* Timeout to notify master for event */
u32 TtcResetId; /* Reset line ID for TTC */
} XPfwRestartTracker;
static XPfwRestartTracker RstTrackerList[] ={
{
.Master = &pmMasterApu_g,
.RestartState = XPFW_RESTART_STATE_BOOT,
.WdtBaseAddress = XPAR_PSU_WDT_1_BASEADDR,
.WdtTimeout= WDT_DEFAULT_TIMEOUT_SEC,
.WdtPtr = &WdtInstance,
.WdtResetId = PM_RESET_SWDT_CRF,
.TtcDeviceId = XPAR_PSU_TTC_9_DEVICE_ID,
.TtcTimeout = TTC_DEFAULT_NOTIFY_TIMEOUT_SEC,
.TtcPtr = &FpdTtcInstance,
.TtcResetId = PM_RESET_TTC3,
#ifdef ENABLE_RECOVERY_RESET_SYSTEM
.RestartScope = PMF_SHUTDOWN_SUBTYPE_SYSTEM,
#elif defined(ENABLE_RECOVERY_RESET_PS_ONLY)
.RestartScope = PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
#else
.RestartScope = PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
#endif
},
{
.Master = &pmMasterRpu0_g,
.RestartState = XPFW_RESTART_STATE_BOOT,
.WdtBaseAddress = XPAR_PSU_WDT_0_BASEADDR,
.WdtTimeout= WDT_DEFAULT_TIMEOUT_SEC,
.WdtPtr = &WdtInstance,
.WdtResetId = PM_RESET_SWDT_CRL,
.TtcDeviceId = 0,
.TtcTimeout = 0,
.TtcPtr = NULL,
.TtcResetId = 0,
#ifdef ENABLE_RECOVERY_RESET_SYSTEM
.RestartScope = PMF_SHUTDOWN_SUBTYPE_SYSTEM,
#elif defined(ENABLE_RECOVERY_RESET_PS_ONLY)
.RestartScope = PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
#else
.RestartScope = PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
#endif
},
{
.Master = &pmMasterRpu_g,
.RestartState = XPFW_RESTART_STATE_BOOT,
.WdtBaseAddress = XPAR_PSU_WDT_0_BASEADDR,
.WdtTimeout= WDT_DEFAULT_TIMEOUT_SEC,
.WdtPtr = &WdtInstance,
.WdtResetId = PM_RESET_SWDT_CRL,
.TtcDeviceId = 0,
.TtcTimeout = 0,
.TtcPtr = NULL,
.TtcResetId = 0,
#ifdef ENABLE_RECOVERY_RESET_SYSTEM
.RestartScope = PMF_SHUTDOWN_SUBTYPE_SYSTEM,
#elif defined(ENABLE_RECOVERY_RESET_PS_ONLY)
.RestartScope = PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
#else
.RestartScope = PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
#endif
},
};
static XWdtPs_Config* GetWdtCfgPtr(u32 BaseAddress)
{
u32 WdtIdx;
XWdtPs_Config* WdtConfigPtr = NULL;
/* Search and return Config pointer with given base address */
for(WdtIdx = 0U; WdtIdx < WDT_INSTANCE_COUNT; WdtIdx++) {
WdtConfigPtr = XWdtPs_LookupConfig(WdtIdx);
if (WdtConfigPtr == NULL) {
goto Done;
}
if (BaseAddress == WdtConfigPtr->BaseAddress) {
break;
}
}
Done:
return WdtConfigPtr;
}
static void WdtRestart(XWdtPs* WdtInstptr, u32 Timeout)
{
XWdtPs_DisableOutput(WdtInstptr, XWDTPS_RESET_SIGNAL);
XWdtPs_Stop(WdtInstptr);
/* Setting the divider value */
XWdtPs_SetControlValue(WdtInstptr, XWDTPS_CLK_PRESCALE,
XWDTPS_CCR_PSCALE_4096);
/* Set the Watchdog counter reset value */
XWdtPs_SetControlValue(WdtInstptr, XWDTPS_COUNTER_RESET,
(Timeout*WDT_CLK_PER_SEC) >> WDT_CRV_SHIFT);
/* Start the Watchdog timer */
XWdtPs_Start(WdtInstptr);
XWdtPs_RestartWdt(WdtInstptr);
/* Enable reset output */
XWdtPs_EnableOutput(WdtInstptr, XWDTPS_RESET_SIGNAL);
}
/**
* XPfw_TimerSetIntervalMode - Set interval mode of TTC
* @TtcInstancePtr: Timer instance pointer
* @PeriodInSec: Timer interval in seconds
*
* Set timer mode to interval mode and set interval to specified
* value.
*/
static void XPfw_TimerSetIntervalMode(XTtcPs *TtcInstancePtr, u32 PeriodInSec)
{
if (!TtcInstancePtr) {
goto END;
}
/* Stop the timer */
XTtcPs_Stop(TtcInstancePtr);
/* Set Interval mode */
XTtcPs_SetOptions(TtcInstancePtr, XTTCPS_OPTION_INTERVAL_MODE);
XTtcPs_SetInterval(TtcInstancePtr, (PeriodInSec * TTC_COUNT_PER_SEC));
XTtcPs_ResetCounterValue(TtcInstancePtr);
XTtcPs_SetPrescaler(TtcInstancePtr, TTC_PRESCALER);
END:
return;
}
/**
* XPfw_TTCStart - Start TTC timer
* @TtcInstancePtr: Timer instance pointer
* @Timeout: Timeout in seconds
*
* Start TTC timer and enable TTC interrupts. TTC configurations should
* be done before this.
*/
static void XPfw_TTCStart(XTtcPs *TtcInstancePtr, u32 Timeout)
{
if (!TtcInstancePtr) {
goto END;
}
/* Enable interrupt */
XTtcPs_EnableInterrupts(TtcInstancePtr, XTTCPS_IXR_INTERVAL_MASK);
/* Start the timer */
XTtcPs_Start(TtcInstancePtr);
END:
return;
}
/**
* XPfw_TTCStop - Stop TTC timer
* @TtcInstancePtr: Timer instance pointer
*
* Stop TTC timer and disable TTC interrupts.
*/
static void XPfw_TTCStop(XTtcPs *TtcInstancePtr)
{
if (!TtcInstancePtr) {
goto END;
}
/* Stop the timer */
XTtcPs_Stop(TtcInstancePtr);
/* Disable interrupt */
XTtcPs_DisableInterrupts(TtcInstancePtr, XTTCPS_IXR_INTERVAL_MASK);
END:
return;
}
#ifdef CHECK_HEALTHY_BOOT
/**
* Get the healthy bit state.
*/
u32 XPfw_GetBootHealthStatus(void)
{
return !(!(XPfw_Read32(XPFW_BOOT_HEALTH_STS) & XPFW_BOOT_HEALTH_GOOD));
}
/**
* Clear APU healthy bit
*/
void XPfw_ClearBootHealthStatus(void)
{
XPfw_RMW32(XPFW_BOOT_HEALTH_STS, XPFW_BOOT_HEALTH_GOOD, 0U);
}
#endif
/* Set up the restart scope */
static void SetRestartScope(XPfwRestartTracker *RestartTracker)
{
/* Set up for master to read and send back the proper restart command */
XPfw_RMW32(XPFW_RESTART_SCOPE_REG, XPFW_RESTART_SCOPE_MASK,
((u32)RestartTracker->RestartScope << XPFW_RESTART_SCOPE_SHIFT));
}
/**
* MasterIdle - Notify master to execute idle sequence
* @TtcInstancePtr: Timer instance pointer
* @Timeout: Timeout in seconds
*
* On receiving WDT event, PMU calls this function to start TTC timer
* to notify master about WDT event.
*/
static void MasterIdle(XTtcPs *TtcInstancePtr, u32 Timeout)
{
/* This is the first restart, send a TTC event */
XPfw_TTCStart(TtcInstancePtr, Timeout);
}
#ifdef ENABLE_ESCALATION
/**
* XPfw_RestartIsPlDone - check the status of PL DONE bit
*
* @return TRUE if its done else FALSE
*/
static bool XPfw_RestartIsPlDone(void)
{
return ((XPfw_Read32(CSU_PCAP_STATUS_REG) &
CSU_PCAP_STATUS_PL_DONE_MASK_VAL) == CSU_PCAP_STATUS_PL_DONE_MASK_VAL);
}
static void XPfw_RestartSystemLevel(void)
{
bool IsPlUp = XPfw_RestartIsPlDone();
if(IsPlUp) {
XPfw_Printf(DEBUG_DETAILED,"Ps Only Reset\r\n");
XPfw_ResetPsOnly();
}
else {
XPfw_Printf(DEBUG_DETAILED,"SRST\r\n");
XPfw_ResetSystem();
}
}
#endif /* ENABLE_ESCALATION */
/**
* Xpfw_TTCInit - Initialize TTC timer
* @TtcDeviceId: TTC timer device ID
* @TtcInstancePtr: Timer instance pointer
*
* Lookup TTC configurations based on TTC device ID and initialize
* TTC based on configurations.
*
* @return XST_SUCCESS in case of success else proper error code
*/
static s32 Xpfw_TTCInit(u16 TtcDeviceId, XTtcPs *TtcInstancePtr)
{
XTtcPs_Config *timerConfig;
s32 Status = XST_FAILURE;
if (!TtcInstancePtr) {
Status = XST_INVALID_PARAM;
goto END;
}
/* Look up the configuration based on the device identifier */
timerConfig = XTtcPs_LookupConfig(TtcDeviceId);
if (NULL == timerConfig) {
Status = XST_FAILURE;
goto END;
}
/* Initialize the device */
Status = XTtcPs_CfgInitialize(TtcInstancePtr, timerConfig, timerConfig->BaseAddress);
END:
return Status;
}
/**
* Xpfw_GetRstTracker - Get WDT reset tracker
*
* @return XPfwRestartTracker in case of success else NULL
*/
static XPfwRestartTracker *Xpfw_GetRstTracker(void)
{
XPfwRestartTracker *Handle = NULL;
u32 RstIdx;
u32 FsblProcInfo = XPfw_Read32(PMU_GLOBAL_GLOBAL_GEN_STORAGE5) & FSBL_STATE_PROC_INFO_MASK;
for (RstIdx = 0; RstIdx < ARRAY_SIZE(RstTrackerList); RstIdx++) {
if ((FSBL_RUNNING_ON_A53 == FsblProcInfo) &&
(NODE_APU == RstTrackerList[RstIdx].Master->nid)) {
XPfw_Printf(DEBUG_DETAILED,"APU\r\n");
break;
}
if ((FSBL_RUNNING_ON_R5_0 == FsblProcInfo) &&
(NODE_RPU_0 == RstTrackerList[RstIdx].Master->nid)) {
XPfw_Printf(DEBUG_DETAILED,"RPU0\r\n");
break;
}
if ((FSBL_RUNNING_ON_R5_L == FsblProcInfo) &&
(NODE_RPU == RstTrackerList[RstIdx].Master->nid)) {
XPfw_Printf(DEBUG_DETAILED,"RPU LS\r\n");
break;
}
}
if (ARRAY_SIZE(RstTrackerList) > RstIdx) {
Handle = &RstTrackerList[RstIdx];
}
return Handle;
}
/**
* @XPfw_RecoveryInit - Initialize WDTs and setup recovery
*
* @return XST_SUCCESS if all Restart Trackers were initialized
* successfully
*/
s32 XPfw_RecoveryInit(void)
{
s32 Status = XST_FAILURE;
XWdtPs_Config *WdtConfigPtr;
XPfwRestartTracker *RstTracker = Xpfw_GetRstTracker();
if (NULL == RstTracker) {
XPfw_Printf(DEBUG_DETAILED,"ASSERT: No Valid Rst Tracker\r\n");
goto END;
}
/*
* Reset TTC lines. TTC lines can be same for different TTC ID so
* reset them in advance to avoid reset after initialization.
*/
if (NULL != RstTracker->TtcPtr) {
Status = PmResetAssertInt(RstTracker->TtcResetId,
PM_RESET_ACTION_PULSE);
if (XST_SUCCESS != Status) {
goto END;
}
}
WdtConfigPtr = GetWdtCfgPtr(RstTracker->WdtBaseAddress);
if (NULL == WdtConfigPtr) {
goto END;
}
/* Initialize and capture the status */
Status = XWdtPs_CfgInitialize(RstTracker->WdtPtr,
WdtConfigPtr, WdtConfigPtr->BaseAddress);
if (XST_SUCCESS != Status) {
goto END;
}
/* Reset the WDT */
Status = PmResetAssertInt(RstTracker->WdtResetId, PM_RESET_ACTION_PULSE);
if (XST_SUCCESS != Status) {
goto END;
}
WdtRestart(RstTracker->WdtPtr, RstTracker->WdtTimeout);
if (NULL != RstTracker->TtcPtr) {
Status = Xpfw_TTCInit(RstTracker->TtcDeviceId, RstTracker->TtcPtr);
if (XST_SUCCESS != Status) {
goto END;
}
XPfw_TimerSetIntervalMode(RstTracker->TtcPtr, RstTracker->TtcTimeout);
}
END:
return Status;
}
/**
* XPfw_RecoveryHandler() - Handle WDT expiry
*
* @ErrorId is the ID corresponding to WDT that has expired
*/
void XPfw_RecoveryHandler(u8 ErrorId)
{
XPfwRestartTracker *RstTracker = Xpfw_GetRstTracker();
if (NULL == RstTracker) {
XPfw_Printf(DEBUG_DETAILED,"ASSERT: No Valid Rst Tracker\r\n");
goto END;
}
#ifdef CHECK_HEALTHY_BOOT
u32 DoSubSystemRestart = 0U;
if (XPfw_GetBootHealthStatus()) {
/*
* Do subsystem restart only if last boot was healthy
*/
DoSubSystemRestart=1;
}
#endif
if ((EM_ERR_ID_FPD_SWDT == ErrorId) &&
(NODE_APU != RstTracker->Master->nid)) {
XPfw_Printf(DEBUG_DETAILED,"ASSERT: Nothing to be done for FPD swdt\r\n");
goto END;
}
if ((EM_ERR_ID_LPD_SWDT == ErrorId) &&
((NODE_RPU_0 != RstTracker->Master->nid) &&
(NODE_RPU != RstTracker->Master->nid))) {
XPfw_Printf(DEBUG_DETAILED,"ASSERT: Nothing to be done for LPD swdt\r\n");
goto END;
}
#ifdef CHECK_HEALTHY_BOOT
if ((XPFW_RESTART_STATE_INPROGRESS != RstTracker->RestartState) &&
DoSubSystemRestart) {
#else
if (XPFW_RESTART_STATE_INPROGRESS != RstTracker->RestartState) {
#endif
XPfw_Printf(DEBUG_DETAILED,"Request Master to idle its cores\r\n");
RstTracker->RestartState = XPFW_RESTART_STATE_INPROGRESS;
WdtRestart(RstTracker->WdtPtr, RstTracker->WdtTimeout);
switch (ErrorId) {
case EM_ERR_ID_FPD_SWDT:
/*
* Inform ATF to idle APU and issue the PmSystemShutdown for restart scope.
*/
SetRestartScope(RstTracker);
MasterIdle(RstTracker->TtcPtr, RstTracker->TtcTimeout);
break;
case EM_ERR_ID_LPD_SWDT:
/*
* Apply Isolation for RPU(M), Slave interface
* will be taken care while releasing tcm.
* todo: Store the AIB enum in the RstTraker's structure.
*/
XPfw_AibEnable(XPFW_AIB_RPU0_TO_LPD);
/* Note: Need not to enable AIB over rpu1 even in case of
* lock-step, as R5-0 will go to sleep.
*/
RstTracker->Master->procs[0]->sleep();
/*
* Remove the isolation
*/
XPfw_AibDisable(XPFW_AIB_RPU0_TO_LPD);
if (PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM ==
RstTracker->RestartScope) {
XPfw_Printf(DEBUG_DETAILED, "Restarting RPU from WDT\n\r");
if (XST_SUCCESS != PmMasterRestart(RstTracker->Master)) {
XPfw_Printf(DEBUG_DETAILED, "Master restart failed");
}
} else if (PMF_SHUTDOWN_SUBTYPE_PS_ONLY ==
RstTracker->RestartScope) {
XPfw_ResetPsOnly();
} else if (PMF_SHUTDOWN_SUBTYPE_SYSTEM ==
RstTracker->RestartScope) {
XPfw_ResetSystem();
}
break;
default:
// Fatal: Never Happen
break;
}
} else {
XPfw_Printf(DEBUG_DETAILED,"Escalating to system level reset\r\n");
#ifdef ENABLE_ESCALATION
XPfw_RestartSystemLevel();
#else
/*
* Fixme: reset as per the restartScope, don't assume subsystem only.
*/
if (XST_SUCCESS != PmMasterRestart(RstTracker->Master)) {
XPfw_Printf(DEBUG_DETAILED, "Master restart failed\r\n");
}
#endif /* ENABLE_ESCALATION */
}
END:
XPfw_Printf(DEBUG_DETAILED,"Exit restart handler\r\n");
}
/**
* XPfw_RecoveryAck - Acknowledge the reception of restart call from a master
* @Master is the PM master from which restart call has been received
*
* @note: The restart state corresponding to this master is set to DONE when
* this function is called.
*/
void XPfw_RecoveryAck(PmMaster *Master)
{
u32 RstIdx;
for (RstIdx = 0U; RstIdx < ARRAY_SIZE(RstTrackerList); RstIdx++) {
/* Currently we support only APU restart */
if(RstTrackerList[RstIdx].Master == Master) {
RstTrackerList[RstIdx].RestartState = XPFW_RESTART_STATE_DONE;
XPfw_TTCStop(RstTrackerList[RstIdx].TtcPtr);
WdtRestart(RstTrackerList[RstIdx].WdtPtr, RstTrackerList[RstIdx].WdtTimeout);
#ifdef CHECK_HEALTHY_BOOT
/*
* clear the healthy status of the boot.
* This has to be set by the targeted application on boot.
*/
XPfw_ClearBootHealthStatus();
#endif
}
}
}
#else /* ENABLE_RECOVERY */
void XPfw_RecoveryAck(PmMaster *Master) { }
void XPfw_RecoveryHandler(u8 ErrorId) { }
s32 XPfw_RecoveryInit(void)
{
/* Recovery is not enabled. So return a failure code */
return XST_FAILURE;
}
void XPfw_RecoveryStop(PmMaster *Master) { }
void XPfw_RecoveryRestart(PmMaster *Master) { }
#endif /* ENABLE_RECOVERY */
#if defined(USE_DDR_FOR_APU_RESTART) && defined(ENABLE_SECURE)
/**
*
* This function is used to store the FSBL image from OCM to
* reserved location of DDR.
*
* @param None
*
* @return Returns the status
*
*/
s32 XPfw_StoreFsblToDDR(void)
{
u32 FsblStatus;
s32 Status;
Status = PmDmaInit();
if (XST_SUCCESS != Status) {
goto END;
}
Status = XSecure_Sha3Initialize(&Sha3Instance, &CsuDma);
if (XST_SUCCESS != Status) {
goto END;
}
FsblStatus = XPfw_Read32(PMU_GLOBAL_GLOBAL_GEN_STORAGE5);
/* Check if FSBL is running on A53 and not encrypted, store it to DDR */
if (FSBL_RUNNING_ON_A53 == (FsblStatus & FSBL_STATE_PROC_INFO_MASK)) {
if (0x0U == (FsblStatus & FSBL_ENCRYPTION_STS_MASK)) {
(void)memcpy((u32 *)FSBL_STORE_ADDR, (u32 *)FSBL_LOAD_ADDR,
FSBL_IMAGE_SIZE);
XSecure_Sha3Digest(&Sha3Instance, (u8 *)FSBL_STORE_ADDR,
FSBL_IMAGE_SIZE, (u8 *)FSBL_Store_Restore_Info.FSBLImageHash);
XPfw_Printf(DEBUG_DETAILED, "Copied FSBL image to DDR\r\n");
} else {
XPfw_Printf(DEBUG_DETAILED, "FSBL copy to DDR is skipped.\r\n"
"Note: APU-only restart will not work if XilFPGA uses OCM "
"for secure bit-stream loading.\r\n");
}
} else {
XPfw_Printf(DEBUG_PRINT_ALWAYS, "FSBL is running on RPU. \r\n"
"Warning: APU-only restart is not supported "
"if FSBL boots on RPU.\r\n");
}
END:
return Status;
}
/**
*
* This function is used to load the FSBL image from reserved location of DDR
* to OCM.
*
* @param None
*
* @return Returns the status
*
*/
s32 XPfw_RestoreFsblToOCM(void)
{
u32 Index;
u32 HashCalculated[SHA3_HASH_LENGTH_IN_WORDS] = {0U};
u32 Status = XST_SUCCESS;
XSecure_Sha3Digest(&Sha3Instance, (u8 *)FSBL_STORE_ADDR,
FSBL_IMAGE_SIZE, (u8 *)HashCalculated);
for (Index = 0U; Index < SHA3_HASH_LENGTH_IN_WORDS; Index++) {
if (FSBL_Store_Restore_Info.FSBLImageHash[Index] !=
HashCalculated[Index]) {
Status = XST_FAILURE;
break;
} else {
Status = XST_SUCCESS;
}
}
if (XST_SUCCESS == Status) {
(void)memcpy((u32 *)FSBL_LOAD_ADDR, (u32 *)FSBL_STORE_ADDR,
FSBL_IMAGE_SIZE);
XPfw_Printf(DEBUG_DETAILED, "FSBL image hash checksum matched\r\n");
} else {
XPfw_Printf(DEBUG_DETAILED, "FSBL image hash checksum is not matching."
" This could be due to FSBL image being corrupted. "
"Unable to do APU-only restart\r\n");
}
return Status;
}
#endif
<file_sep>/python_drivers/tdc_entangled_pair_detect_test.py
# -*- coding: utf-8 -*-
"""
Created on Wed Aug 5 11:20:24 2020
@author: tianlab01
"""
import tdc_wrapper
import pulse_gen
import matplotlib.pyplot as plt
import time
pulses_to_send = 10000
amplitude = 0x8000
period = 100 #in clock cycles
channel_num = 2 #TDC channel connected to SNSPD
#Create a new TDC object
tdc = tdc_wrapper.tdc_wrapper(15, 0, tdc_wrapper.MODE_NORMAL, "")
#Create a new FPGA object
board = pulse_gen.pulse_gen("COM4")
if(board.ping_board()):
print("Connection to board is down, aborting...")
else:
print("Connection to board is up!")
print("Sending " + str(pulses_to_send) + " pulses")
#Set the board amplitude and period
board.set_amplitude(amplitude)
board.set_period(period)
board.set_pulse_len(16)
#Clear the TDC
tdc.clear_all()
tdc.set_record(1)
#Send the pulses
board.toggle_phase_meas(pulses_to_send)
#while(tdc.is_busy()):
# a = 1
time.sleep(0.01)
tdc.set_record(0)
tdc.shutdown()
board.close_board()
#time.sleep()
#Get the pulses from the TDC
pulses = tdc.end_record(channel_num, 1)
pulses.sort()
print("Got " + str(len(pulses)) + " counts")
# diffs = []
# for i in range(0, len(pulses)-1):
# for j in range(0, len(pulses)-1):
# if(i != j):
# diffs.append(pulses[i+1] - pulses[i])
# avg_diff = sum(diffs)/len(diffs)
# print("Average difference was " + str(avg_diff/1000) +"ns")
# plt.hist(diffs, bins = 10000000)
# plt.title('Histogram of time differences between adjacent pulses')
# plt.show()
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_aie.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xplmi_util.h"
#include "xplmi_dma.h"
#include "xpm_common.h"
#include "xpm_aie.h"
#include "xpm_regs.h"
#include "xpm_bisr.h"
#include "xpm_device.h"
#define AIE_POLL_TIMEOUT 0X1000000U
#define COL_SHIFT 23U
#define ROW_SHIFT 18U
#define TILE_BASEADDRESS(col, row) ((u64)0x20000000000U +\
((u64)(col) << COL_SHIFT)+\
((u64)(row) << ROW_SHIFT))
#define AIE_CORE_CONTROL_ENABLE_MASK (1U<<0U)
#define AIE_CORE_CONTROL_RESET_MASK (1U<<1U)
#define AIE_CORE_STATUS_DONE_MASK (1UL<<20U)
#define AieWrite64(addr, val) swea(addr, val)
/* Buffer to hold AIE data memory zeroization elf*/
static u32 ProgramMem[] __attribute__ ((aligned(16))) = {
0x0600703fU,
0x0a000804U,
0x000018c0U,
0x603803f7U,
0x00000203U,
0x400c9803U,
0x13201803U,
0x31009803U,
0x200003f7U,
0x00000277U,
0x800003f7U,
0x00000257U,
0x00000000U,
0x39200000U,
0x0000003dU,
0x00000000U,
0x00000000U,
0x00000000U,
0x40000000U,
0x00001888U,
0x00000000U,
0x00000000U,
0x00000000U,
0x0000079aU,
0x00000000U,
0x00000000U,
0x00000000U,
0x00002614U,
0x00000000U,
0x00000000U,
0x07428800U,
0x00000000U,
0x00010001U,
0x00010001U,
0x00030001U,
0x00011000U,
0x00010001U,
0x00010001U,
0x00010001U,
0x00010001U,
};
struct AieArray {
u32 NpiAddress;
u64 NocAddress;
u32 NumCols;
u32 NumRows;
u32 StartCol;
u32 StartRow;
u8 IsSecure;
};
static struct AieArray AieInst = {
.NpiAddress = 0xF70A0000U,
.NocAddress = 0x20000000000U,
.NumCols = 50U,
.NumRows = 8U,
.StartCol = 0U,
.StartRow = 1U,
.IsSecure = 0U,
};
/*****************************************************************************/
/**
* This function is used to set/clear bits in AIE PCSR
*
* @param Mask Mask to be written into PCSR_MASK register
* @param Value Value to be written into PCSR_CONTROL register
* @return
*****************************************************************************/
static XStatus AiePcsrWrite(u32 Mask, u32 Value)
{
XStatus Status = XST_FAILURE;
u32 BaseAddress;
const XPm_Device * const AieDev = XPmDevice_GetById(PM_DEV_AIE);
if (NULL == AieDev) {
goto done;
}
BaseAddress = AieDev->Node.BaseAddress;
PmOut32((BaseAddress + NPI_PCSR_MASK_OFFSET), Mask);
PmOut32((BaseAddress + NPI_PCSR_CONTROL_OFFSET), Value);
Status = XST_SUCCESS;
done:
return Status;
}
/*****************************************************************************/
/**
* This function provides a delay for specified duration
*
* @param MicroSeconds Duration in micro seconds
* @return
*****************************************************************************/
static inline void AieWait(u32 MicroSeconds)
{
usleep(MicroSeconds);
}
/*****************************************************************************/
/**
* This function is used to enable AIE Core
*
* @param Col Column index of the Core
* @param Row Row index of the Core
* @return
*****************************************************************************/
static void AieCoreEnable(u32 Col, u32 Row)
{
/* Release reset to the Core */
AieWrite64(TILE_BASEADDRESS(Col, Row) + AIE_CORE_CONTROL_OFFSET, 0U);
/* Enable the Core */
AieWrite64(TILE_BASEADDRESS(Col, Row) + AIE_CORE_CONTROL_OFFSET, 1U);
}
/*****************************************************************************/
/**
* This function waits for a Core's DONE bit to be set
*
* @param Col Column index of the Core
* @param Row Row index of the Core
* @return Status Code
*****************************************************************************/
static XStatus AieWaitForCoreDone(u32 Col, u32 Row)
{
u64 StatusRegAddr = TILE_BASEADDRESS(Col, Row) + AIE_CORE_STATUS_OFFSET;
XStatus Status = XST_FAILURE;
Status = XPlmi_UtilPollForMask64((u32)(StatusRegAddr>>32),
(u32)(StatusRegAddr), AIE_CORE_STATUS_DONE_MASK, 10U);
if (Status != XST_SUCCESS) {
PmInfo("ERROR: Poll for Done timeout \r\n");
}
return Status;
}
/*****************************************************************************/
/**
* This function loads a core's program memory with zeroization elf
*
* @param Col Column index of the Core
* @param Row Row index of the Core
* @return Status Code
*****************************************************************************/
static XStatus ProgramCore(u32 Col, u32 Row, u32 *PrgData, u32 NumOfWords)
{
u64 PrgAddr = TILE_BASEADDRESS(Col, Row) + AIE_PROGRAM_MEM_OFFSET;
return XPlmi_DmaXfr((u64)(0U)|(u32)PrgData, PrgAddr, NumOfWords, XPLMI_PMCDMA_0);
}
/*****************************************************************************/
/**
* This function is used to cycle reset to the entire AIE array
*
* @return
*****************************************************************************/
static XStatus ArrayReset(void)
{
XStatus Status = XST_FAILURE;
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_ME_ARRAY_RESET_MASK,
ME_NPI_REG_PCSR_MASK_ME_ARRAY_RESET_MASK);
if (XST_SUCCESS != Status) {
goto done;
}
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_ME_ARRAY_RESET_MASK, 0U);
done:
return Status;
}
/*****************************************************************************/
/**
* This function is used to scrub ECC enabled memories in the entire AIE array
*
* @return
*****************************************************************************/
static void TriggerEccScrub(void)
{
u32 row, col;
for (col = AieInst.StartCol; col < (AieInst.StartCol + AieInst.NumCols); col++) {
for (row = AieInst.StartRow; row < (AieInst.StartRow + AieInst.NumRows); row++) {
AieWrite64(TILE_BASEADDRESS(col, row) + AIE_CORE_ECC_SCRUB_EVENT_OFFSET, 1U);
}
}
}
static XStatus MemInit(void)
{
u32 row = AieInst.StartRow;
u32 col = AieInst.StartCol;
int Status;
for (col = AieInst.StartCol; col < (AieInst.StartCol + AieInst.NumCols); col++) {
for (row = AieInst.StartRow; row < (AieInst.StartRow + AieInst.NumRows); row++) {
PmDbg("---------- (%d, %d)----------\r\n", col, row);
Status = ProgramCore(col, row, &ProgramMem[0], ARRAY_SIZE(ProgramMem));
if (XST_SUCCESS != Status) {
goto done;
}
AieCoreEnable(col, row);
}
}
Status = AieWaitForCoreDone(col-1U, row-1U);
done:
return Status;
}
static XStatus AieInitStart(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 BaseAddress;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
const XPm_Device * const AieDev = XPmDevice_GetById(PM_DEV_AIE);
if (NULL == AieDev) {
goto done;
}
BaseAddress = AieDev->Node.BaseAddress;
/* Check for ME Power Status */
if( (XPm_In32(BaseAddress + NPI_PCSR_STATUS_OFFSET) &
ME_NPI_REG_PCSR_STATUS_ME_PWR_SUPPLY_MASK) !=
ME_NPI_REG_PCSR_STATUS_ME_PWR_SUPPLY_MASK) {
goto done;
}
/* Unlock ME PCSR */
PmOut32((BaseAddress + NPI_PCSR_LOCK_OFFSET), NPI_PCSR_UNLOCK_VAL);
/* Relelase IPOR */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_ME_IPOR_MASK, 0U);
if (XST_SUCCESS != Status) {
goto done;
}
/* TODO: Configure TOP_ROW and ROW_OFFSET by reading from EFUSE */
/* Hardcode ME_TOP_ROW value for S80 device */
PmOut32((BaseAddress + ME_NPI_ME_TOP_ROW_OFFSET), 0x00000008U);
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus AieInitFinish(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
/* Set PCOMPLETE bit */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_PCOMPLETE_MASK,
ME_NPI_REG_PCSR_MASK_PCOMPLETE_MASK);
if (XST_SUCCESS != Status) {
goto done;
}
/* TODO: Check if we can lock PCSR registers here */
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus AieScanClear(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 BaseAddress;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
const XPm_Device * const AieDev = XPmDevice_GetById(PM_DEV_AIE);
if (NULL == AieDev) {
goto done;
}
BaseAddress = AieDev->Node.BaseAddress;
/* De-assert ODISABLE[1] */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_ODISABLE_1_MASK, 0U);
if (XST_SUCCESS != Status) {
goto done;
}
if (PLATFORM_VERSION_SILICON == Platform) {
/* Trigger Scan Clear */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_SCAN_CLEAR_TRIGGER_MASK,
ME_NPI_REG_PCSR_MASK_SCAN_CLEAR_TRIGGER_MASK);
if (XST_SUCCESS != Status) {
goto done;
}
XPlmi_Printf(DEBUG_INFO, "INFO: %s : Wait for AIE Scan Clear complete...", __func__);
/* Wait for Scan Clear DONE */
Status = XPm_PollForMask(BaseAddress + NPI_PCSR_STATUS_OFFSET,
ME_NPI_REG_PCSR_STATUS_SCAN_CLEAR_DONE_MASK,
AIE_POLL_TIMEOUT);
if (XST_SUCCESS != Status) {
XPlmi_Printf(DEBUG_INFO, "ERROR\r\n");
goto done;
}
else {
XPlmi_Printf(DEBUG_INFO, "DONE\r\n");
}
/* Check Scan Clear PASS */
if( (XPm_In32(BaseAddress + NPI_PCSR_STATUS_OFFSET) &
ME_NPI_REG_PCSR_STATUS_SCAN_CLEAR_PASS_MASK) !=
ME_NPI_REG_PCSR_STATUS_SCAN_CLEAR_PASS_MASK) {
XPlmi_Printf(DEBUG_GENERAL, "ERROR: %s: AIE Scan Clear FAILED\r\n", __func__);
Status = XST_FAILURE;
goto done;
}
/* Unwrite trigger bits */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_SCAN_CLEAR_TRIGGER_MASK, 0);
if (XST_SUCCESS != Status) {
goto done;
}
}
/* De-assert ODISABLE[0] */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_ODISABLE_0_MASK, 0U);
if (XST_SUCCESS != Status) {
goto done;
}
/* De-assert GATEREG */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_GATEREG_MASK, 0U);
done:
return Status;
}
static XStatus AieBisr(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
/* Remove PMC-NoC domain isolation */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_SOC, FALSE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmBisr_Repair(MEA_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmBisr_Repair(MEB_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmBisr_Repair(MEC_TAG_ID);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
static XStatus AieMbistClear(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
u32 BaseAddress;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
const XPm_Device * const AieDev = XPmDevice_GetById(PM_DEV_AIE);
if (NULL == AieDev) {
goto done;
}
BaseAddress = AieDev->Node.BaseAddress;
if (Platform == PLATFORM_VERSION_SILICON) {
/* Assert MEM_CLEAR_EN_ALL */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_MEM_CLEAR_EN_ALL_MASK,
ME_NPI_REG_PCSR_MASK_MEM_CLEAR_EN_ALL_MASK);
if (XST_SUCCESS != Status) {
goto done;
}
/* De-assert OD_MBIST_ASYNC_RESET_N */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_OD_MBIST_ASYNC_RESET_N_MASK,
ME_NPI_REG_PCSR_MASK_OD_MBIST_ASYNC_RESET_N_MASK);
if (XST_SUCCESS != Status) {
goto done;
}
/* Assert OD_BIST_SETUP_1 */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_OD_BIST_SETUP_1_MASK,
ME_NPI_REG_PCSR_MASK_OD_BIST_SETUP_1_MASK);
if (XST_SUCCESS != Status) {
goto done;
}
/* Assert MEM_CLEAR_TRIGGER */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_MEM_CLEAR_TRIGGER_MASK,
ME_NPI_REG_PCSR_MASK_MEM_CLEAR_TRIGGER_MASK);
if (XST_SUCCESS != Status) {
goto done;
}
XPlmi_Printf(DEBUG_INFO, "INFO: %s : Wait for AIE Mem Clear complete...", __func__);
/* Wait for Mem Clear DONE */
Status = XPm_PollForMask(BaseAddress + NPI_PCSR_STATUS_OFFSET,
ME_NPI_REG_PCSR_STATUS_MEM_CLEAR_DONE_MASK,
AIE_POLL_TIMEOUT);
if (Status != XST_SUCCESS) {
XPlmi_Printf(DEBUG_INFO, "ERROR\r\n");
goto done;
}
else {
XPlmi_Printf(DEBUG_INFO, "DONE\r\n");
}
/* Check Mem Clear PASS */
if ((XPm_In32(BaseAddress + NPI_PCSR_STATUS_OFFSET) &
ME_NPI_REG_PCSR_STATUS_MEM_CLEAR_PASS_MASK) !=
ME_NPI_REG_PCSR_STATUS_MEM_CLEAR_PASS_MASK) {
XPlmi_Printf(DEBUG_GENERAL, "ERROR: %s: AIE Mem Clear FAILED\r\n", __func__);
Status = XST_FAILURE;
goto done;
}
/* Assert OD_MBIST_ASYNC_RESET_N */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_OD_MBIST_ASYNC_RESET_N_MASK, 0U);
if (XST_SUCCESS != Status) {
goto done;
}
/* De-assert OD_BIST_SETUP_1 */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_OD_BIST_SETUP_1_MASK, 0U);
if (XST_SUCCESS != Status) {
goto done;
}
/* De-assert MEM_CLEAR_TRIGGER */
Status = AiePcsrWrite(ME_NPI_REG_PCSR_MASK_MEM_CLEAR_TRIGGER_MASK, 0U);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XST_SUCCESS;
done:
return Status;
}
static XStatus AieMemInit(u32 *Args, u32 NumOfArgs)
{
XStatus Status = XST_FAILURE;
/* This function does not use the args */
(void)Args;
(void)NumOfArgs;
PmDbg("---------- START ----------\r\n");
/* Scrub ECC protected memories */
TriggerEccScrub();
/* Wait for scrubbing to finish (1ms)*/
AieWait(1000U);
/* Reset Array */
Status = ArrayReset();
if (XST_SUCCESS != Status) {
PmErr("ERROR: Array reset failed\r\n");
}
/* Zeroize Data Memory */
Status = MemInit();
if (Status != XST_SUCCESS) {
PmInfo("ERROR: MemInit failed\r\n");
}
/* Reset Array */
Status = ArrayReset();
if (XST_SUCCESS != Status) {
PmErr("ERROR: Array reset failed\r\n");
}
PmDbg("---------- END ----------\r\n");
return Status;
}
static struct XPm_PowerDomainOps AieOps = {
.InitStart = AieInitStart,
.InitFinish = AieInitFinish,
.ScanClear = AieScanClear,
.Bisr = AieBisr,
.Mbist = AieMbistClear,
.MemInit = AieMemInit,
};
/*****************************************************************************/
/**
* @brief This funcction unlocks the AIE PCSR registers.
*
*****************************************************************************/
void XPmAieDomain_UnlockPcsr(u32 BaseAddress)
{
u32 NpiPcsrLockReg = BaseAddress + NPI_PCSR_LOCK_OFFSET;
PmOut32(NpiPcsrLockReg, NPI_PCSR_UNLOCK_VAL);
}
/*****************************************************************************/
/**
* @brief This funcction locks the AIE PCSR registers.
*
*****************************************************************************/
void XPmAieDomain_LockPcsr(u32 BaseAddress)
{
u32 NpiPcsrLockReg = BaseAddress + NPI_PCSR_LOCK_OFFSET;
PmOut32(NpiPcsrLockReg, 0x00000000U);
}
XStatus XPmAieDomain_Init(XPm_AieDomain *AieDomain, u32 Id, u32 BaseAddress,
XPm_Power *Parent)
{
XStatus Status = XST_FAILURE;
/* Skip AIE Init for base QEMU without COSIM */
if (Platform == PLATFORM_VERSION_QEMU) {
AieOps.InitStart = NULL;
AieOps.InitFinish = NULL;
AieOps.ScanClear = NULL;
AieOps.Bisr = NULL;
AieOps.Mbist = NULL;
AieOps.MemInit = NULL;
}
/* For SPP and EMU, setup the array size */
if (Platform != PLATFORM_VERSION_SILICON) {
AieInst.NumCols = 7U;
AieInst.NumRows = 5U;
AieInst.StartCol = 6U;
AieInst.StartRow = 1U;
}
Status = XPmPowerDomain_Init(&AieDomain->Domain, Id, BaseAddress, Parent, &AieOps);
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/iicps_v3_11/src/xiicps_xfer.c
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_xfer.c
* @addtogroup iicps_v3_11
* @{
*
* Contains implementation of required helper functions for the XIicPs driver.
* See xiicps.h for detailed description of the device and driver.
*
* <pre> MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------------
* 3.11 rna 12/10/19 First release
* 02/18/20 Modified latest code for MISRA-C:2012 Compliance.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xiicps.h"
#include "xiicps_xfer.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/*****************************************************************************/
/*
* This function prepares a device to transfers as a master.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @param Role specifies whether the device is sending or receiving.
*
* @return
* - XST_SUCCESS if everything went well.
* - XST_FAILURE if bus is busy.
*
* @note Interrupts are always disabled, device which needs to use
* interrupts needs to setup interrupts after this call.
*
****************************************************************************/
s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
{
u32 ControlReg;
u32 BaseAddr;
BaseAddr = InstancePtr->Config.BaseAddress;
ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
/*
* Only check if bus is busy when repeated start option is not set.
*/
if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
return (s32)XST_FAILURE;
}
}
/*
* Set up master, AckEn, nea and also clear fifo.
*/
ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
(u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
if (Role == RECVING_ROLE) {
ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
}else {
ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
}
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
XIicPs_DisableAllInterrupts(BaseAddr);
return (s32)XST_SUCCESS;
}
/*****************************************************************************/
/*
* This function handles continuation of sending data. It is invoked
* from interrupt handler.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void MasterSendData(XIicPs *InstancePtr)
{
(void)TransmitFifoFill(InstancePtr);
/*
* Clear hold bit if done, so stop can be sent out.
*/
if (InstancePtr->SendByteCount == 0) {
/*
* If user has enabled repeated start as an option,
* do not disable it.
*/
if (InstancePtr->IsRepeatedStart == 0) {
XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
(u32)XIICPS_CR_OFFSET,
XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
(u32)XIICPS_CR_OFFSET) & (u32)(~ XIICPS_CR_HOLD_MASK));
}
}
return;
}
/*****************************************************************************/
/*
*
* This function handles continuation of receiving data. It is invoked
* from interrupt handler.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @return Number of bytes still expected by the instance.
*
* @note None.
*
****************************************************************************/
s32 SlaveRecvData(XIicPs *InstancePtr)
{
u32 StatusReg;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
BaseAddr = InstancePtr->Config.BaseAddress;
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
(InstancePtr->RecvByteCount > 0)) {
XIicPs_RecvByte(InstancePtr);
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
}
return InstancePtr->RecvByteCount;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilfpga_v5_2/src/xilfpga_pcap_common.h
/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilfpga_pcap_common.h
* @addtogroup xfpga_apis XilFPGA APIs
* @{
*
*
* The XILFPGA library provides the interface to the application to configure
* the programmable logic (PL) though the PS.
*
* - Supported Features:
* - Full Bitstream loading.
* - Partial Bitstream loading.
* - Encrypted Bitstream loading.
* - Authenticated Bitstream loading.
* - Authenticated and Encrypted Bitstream loading.
* - Partial Bitstream loading.
*
* # Xilfpga_PL library Interface modules {#xilfpgapllib}
* Xilfpga_PL library uses the below major components to configure the PL
* through PS.
* - CSU DMA driver is used to transfer the actual Bit stream file for the
* PS to PL after PCAP initialization
*
* - Xilsecure_library provides APIs to access secure hardware on the Zynq®
* UltraScale+&tm MPSoC devices. This library includes:
* - SHA-3 engine hash functions
* - AES for symmetric key encryption
* - RSA for authentication
*
* These algorithms are needed to support to load the Encrypted and
* Authenticated Bitstreams into PL.
*
* ## Initialization & Writing Bitstream {#xilinit}
*
* Use the u32 XFpga_PL_BitSream_Load(); function to initialize the driver
* and load the Bitstream.
*
* @{
* @cond xilfpga_internal
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- ---- -------- --------------------------------------------------------
* 5.2 Nava 14/02/20 Added Bitstream loading support by using IPI services.
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XILFPGA_PCAP_COMMON_H
#define XILFPGA_PCAP_COMMON_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/**
* Structure to store the PL Write Image details.
*
* @BitstreamAddr Bitstream image base address.
* @AddrPtr_Size Aes key address which is used for Decryption (or)
* In none Secure Bitstream used it is used store size
* of Bitstream Image.
* @Flags Flags are used to specify the type of Bitstream file.
* * BIT(0) - Bitstream type
* * 0 - Full Bitstream
* * 1 - Partial Bitstream
* * BIT(1) - Authentication using DDR
* * 1 - Enable
* * 0 - Disable
* * BIT(2) - Authentication using OCM
* * 1 - Enable
* * 0 - Disable
* * BIT(3) - User-key Encryption
* * 1 - Enable
* * 0 - Disable
* * BIT(4) - Device-key Encryption
* * 1 - Enable
* * 0 - Disable
*
*/
typedef struct {
UINTPTR BitstreamAddr;
UINTPTR AddrPtr_Size;
u32 Flags;
}XFpga_Write;
/**
* Structure to store the PL Image details.
*
* @ReadbackAddr Address which is used to store the PL readback data.
* @ConfigReg Configuration register value to be returned (or)
* The number of Fpga configuration frames to read
*/
typedef struct {
UINTPTR ReadbackAddr;
u32 ConfigReg_NumFrames;
}XFpga_Read;
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/* FPGA Configuration Registers Offsets */
#define CRC 0U /* Status Register */
#define FAR1 1U /* Frame Address Register */
#define FDRI 2U /* FDRI Register */
#define FDRO 3U /* FDRO Register */
#define CMD 4U /* Command Register */
#define CTL0 5U /* Control Register 0 */
#define MASK 6U /* MASK Register */
#define STAT 7U /* Status Register */
#define LOUT 8U /* LOUT Register */
#define COR0 9U /* Configuration Options Register 0 */
#define MFWR 10U /* MFWR Register */
#define CBC 11U /* CBC Register */
#define IDCODE 12U /* IDCODE Register */
#define AXSS 13U /* AXSS Register */
#define COR1 14U /* Configuration Options Register 1 */
#define WBSTAR 16U /* Warm Boot Start Address Register */
#define TIMER 17U /* Watchdog Timer Register */
#define BOOTSTS 22U /* Boot History Status Register */
#define CTL1 24U /* Control Register 1 */
/************************** Function Prototypes ******************************/
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* XILFPGA_PCAP_COMMON_H */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/include/xrfdc.h
/******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrfdc.h
* @addtogroup rfdc_v8_0
* @{
* @details
*
* The Xilinx� LogiCORE IP Zynq UltraScale+ RFSoC RF Data Converter IP core
* provides a configurable wrapper to allow the RF DAC and RF ADC blocks to be
* used in IP Integrator designs. Multiple tiles are available on each RFSoC
* and each tile can have a number of data converters (analog-to-digital (ADC)
* and digital-to-analog (DAC)). The RF ADCs can sample input frequencies up
* to 4 GHz at 4 GSPS with excellent noise spectral density. The RF DACs
* generate output carrier frequencies up to 4 GHz using the 2nd Nyquist zone
* with excellent noise spectral density at an update rate of 6.4 GSPS.
* The RF data converters also include power efficient digital down-converters
* (DDCs) and digital up-converters (DUCs) that include programmable interpolation
* and decimation, NCO and complex mixer. The DDCs and DUCs can also support
* dual-band operation.
* A maximum of 4 tiles are available on for DAC and ADC operations each. Each
* tile can have a maximum of 4 blocks/slices.
* This driver provides APIs to configure various functionalities. Similarly
* the driver provides APIs to read back configurations.
* Some of the features that the driver supports are:
* 1) Setting up and reading back fine mixer settings
* 2) Setting up and reading back coarse mixer settings
* 3) Reading back interpolation or decimation factors
* 4) Setting up and reading back QMC settings which include gain, phase etc
* 5) Setting up and reading back decoder mode settings
* 6) Setting up and reading back coarse delay settings
* All the APIs implemented in the driver provide appropriate range checks.
* An API has been provided for debug purpose which will dump all registers
* for a requested tile.
* Inline functions have also been provided to read back the parameters
* initially configured through the GUI.
*
* There are plans to add more features, e.g. Support for multi band, PLL
* configurations etc.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.0 sk 05/16/17 Initial release
* 2.0 sk 08/09/17 Fixed coarse Mixer configuration settings
* CR# 977266, 977872.
* Return error for Slice Event on 4G ADC Block.
* Corrected Interrupt Macro names and values.
* 08/16/17 Add support for SYSREF and PL event sources.
* 08/18/17 Add API to enable and disable FIFO.
* 08/23/17 Add API to configure Nyquist zone.
* 08/30/17 Add additional info to BlockStatus.
* 08/30/17 Add support for Coarse Mixer BYPASS mode.
* 08/31/17 Removed Tile Reset Assert and Deassert.
* 09/07/17 Add support for negative NCO freq.
* 09/15/17 Fixed NCO freq precision issue.
* 09/15/17 Fixed Immediate Event source issue and also
* updated the Immediate Macro value to 0.
* 2.1 sk 09/15/17 Remove Libmetal library dependency for MB.
* 09/18/17 Add API to clear the interrupts.
* sk 09/21/17 Add __BAREMETAL__ compiler flag option
* for Baremetal.
* sk 09/21/17 Add support for Over voltage and Over
* Range interrupts.
* sk 09/22/17 Add s64 typedef for Linux.
* sk 09/24/17 Fixed Get_Tile/BlockBaseAddr always
* giving ADC related address.
* sk 09/25/17 Modified XRFdc_GetBlockStatus API to give
* correct information and also updates the
* description for Vector Param in intr handler
* Add API to get Output current and removed
* GetTermVoltage and GetOutputCurr inline functions.
* 2.2 sk 10/05/17 Fixed XRFdc_GetNoOfADCBlocks API for 4GSPS.
* Enable the decoder clock based on decoder mode.
* Add API to get the current FIFO status.
* Updated XRFdc_DumpRegs API for better readability
* of output register dump.
* Add support for 4GSPS CoarseMixer frequency.
* 10/11/17 Modify float types to double to increase precision.
* 10/12/17 Update BlockStatus API to give current status.
* In BYPASS mode, input datatype can be Real or IQ
* hence checked both while reading the mixer mode.
* 10/17/17 Fixed Set Threshold API Issue.
* 2.2 sk 10/18/17 Add support for FIFO and DATA overflow interrupt
* 2.3 sk 11/06/17 Fixed PhaseOffset truncation issue.
* Provide user configurability for FineMixerScale.
* 11/08/17 Return error for DAC R2C mode and ADC C2R mode.
* 11/10/17 Corrected FIFO and DATA Interrupt masks.
* 11/20/17 Fixed StartUp, Shutdown and Reset API for Tile_Id -1.
* 11/20/17 Remove unwanted ADC block checks in 4GSPS mode.
* 3.0 sk 12/11/17 Added DDC and DUC support.
* 12/13/17 Add CoarseMixMode field in Mixer_Settings structure.
* 12/15/17 Add support to switch calibration modes.
* 12/15/17 Add support for mixer frequencies > Fs/2 and < -Fs/2.
* sg 13/01/18 Added PLL and external clock switch support
* Added API to get PLL lock status.
* Added API to get clock source.
* sk 01/18/18 Add API to get driver version.
* 3.1 jm 01/24/18 Add Multi-tile sync support.
* sk 01/25/18 Updated Set and Get Interpolation/Decimation factor
* API's to consider the actual factor value.
* 3.2 sk 02/02/18 Add API's to configure inverse-sinc.
* sk 02/27/18 Add API's to configure Multiband.
* sk 03/09/18 Update PLL structure in XRFdc_DynamicPLLConfig API.
* sk 03/09/18 Update ADC and DAC datatypes in Mixer API and use
* input datatype for ADC in threshold and QMC APIs.
* sk 03/09/18 Removed FIFO disable check in DDC and DUC APIs.
* sk 03/09/18 Add support for Marker event source for DAC block.
* jm 03/12/18 Fixed DAC latency calculation in MTS.
* jm 03/12/18 Added support for reloading DTC scans.
* jm 03/12/18 Add option to configure sysref capture after MTS.
* sk 03/22/18 Updated PLL settings based on latest IP values.
* 4.0 sk 04/09/18 Added API to enable/disable the sysref.
* sk 04/09/18 Updated max VCO to 13108MHz to support max DAC
* sample rate of 6.554MHz.
* rk 04/17/18 Adjust calculated latency by sysref period, where doing
* so results in closer alignment to the target latency.
* sk 04/17/18 Corrected Set/Get MixerSettings API description for
* FineMixerScale parameter.
* sk 04/19/18 Enable VCO Auto selection while configuring the clock.
* sk 04/24/18 Add API to get PLL Configurations.
* sk 04/24/18 Add API to get the Link Coupling mode.
* sk 04/28/18 Implement timeouts for PLL Lock, Startup and shutdown.
* sk 05/30/18 Removed CalibrationMode check for DAC.
* sk 06/05/18 Updated minimum Ref clock value to 102.40625MHz.
* 5.0 sk 06/25/18 Update DAC min sampling rate to 500MHz and also update
* VCO Range, PLL_DIVIDER and PLL_FPDIV ranges.
* Update PLL structure with calculated sampling rate.
* sk 06/25/18 Add XRFdc_GetFabClkOutDiv() API to read fabric clk div.
* Add Inline APIs XRFdc_CheckBlockEnabled(),
* XRFdc_CheckTileEnabled().
* sk 07/06/18 Add support to dump HSCOM regs in XRFdc_DumpRegs() API
* sk 07/12/18 Fixed Multiband crossbar settings in C2C mode.
* sk 07/19/18 Add MixerType member to MixerSettings structure and
* Update Mixer Settings APIs to consider the MixerType
* variable.
* sk 07/19/18 Add XRFdc_GetMultibandConfig() API to read Multiband
* configuration.
* sk 07/20/18 Update the APIs to check the corresponding section
* (Digital/Analog)enable/disable.
* sk 07/26/18 Fixed Doxygen, coverity warnings.
* sk 08/03/18 Fixed MISRAC warnings.
* sk 08/24/18 Move mixer related APIs to xrfdc_mixer.c file.
* Define asserts for Linux, Re-arranged XRFdc_RestartIPSM,
* XRFdc_CfgInitialize() and XRFdc_MultiBand() APIs.
* Reorganize the code to improve readability and
* optimization.
* mus 08/17/18 Removed structure paddings from XRFdc_Config structure.
* It has been done to have 1:1 mapping between
* XRFdc_Config structure and device tree property
* "param-list", over linux platform.
* sk 09/24/18 Update powerup-state value based on PLL mode in
* XRFdc_DynamicPLLConfig() API.
* sk 10/10/18 Check for DigitalPath enable in XRFdc_GetNyquistZone()
* and XRFdc_GetCalibrationMode() APIs for Multiband.
* sk 10/13/18 Add support to read the REFCLKDIV param from design.
* Update XRFdc_SetPLLConfig() API to support range of
* REF_CLK_DIV values(1 to 4).
* Add XRFDC_MIXER_MODE_R2R option to support BYPASS mode
* for Real input.
* 5.1 cog 01/29/19 Replace structure reference ADC checks with
* function.
* cog 01/29/19 Added XRFdc_SetDither() and XRFdc_GetDither() APIs.
* cog 01/29/19 Rename DataType for mixer input to MixerInputDataType
* for readability.
* cog 01/29/19 Refactoring of interpolation and decimation APIs and
* changed fabric rate for decimation X8 for non-high speed ADCs.
* cog 01/29/19 New inline functions to determine max & min sampling rates.
* 6.0 cog 02/17/19 Added Inverse-Sinc Second Nyquist Zone Support
* cog 02/17/19 Added new clock Distribution functionality.
* cog 02/17/19 Refactored to improve delay balancing in clock
* distribution.
* cog 02/17/19 Added delay calculation & metal log messages.
* cog 02/17/19 Added Intratile clock settings.
* cog 02/17/19 XRFdc_GetPLLConfig() now uses register values to get the
* PLL configuration for new IPs and is no longer static.
* cog 02/17/19 Refactoring of interpolation and decimation APIs and
* changed fabric rate for decimation X8 for non-high speed ADCs.
* cog 02/17/19 Added XRFdc_SetIMRPassMode() and XRFdc_SetIMRPassMode() APIs
* cog 02/17/19 Added XRFdc_SetDACMode() and XRFdc_GetDACMode() APIs
* cog 02/17/19 Added XRFdc_SetSignalDetector() and XRFdc_GetSignalDetector() APIs
* cog 02/17/19 Added XRFdc_DisableCoefficientsOverride(), XRFdc_SetCalCoefficients
* and XRFdc_GetCalCoefficients APIs.
* cog 02/19/19 New definitions for clock detection.
* 6.0 cog 02/20/19 Added handling for new ADC common mode over/under
* voltage interrupts.
* cog 02/20/19 XRFdc_GetIntrStatus now populates a pointer with the
* status and returns an error code.
* cog 02/20/19 XRFdc_IntrClr, XRFdc_IntrDisable and XRFdc_IntrEnable
* now return error codes.
* cog 02/21/19 Added XRFdc_SetCalFreeze() and XRFdc_GetCalFreeze() APIs
* cog 04/15/19 Rename XRFdc_SetDACMode() and XRFdc_GetDACMode() APIs to
* XRFdc_SetDataPathMode() and XRFdc_GetDataPathMode() respectively.
* 7.0 cog 05/13/19 Formatting changes.
* cog 05/13/19 Added new bock MACROs.
* cog 05/13/19 XRFdc_CheckTileEnabled(), XRFdc_IsDACBlockEnabled(),
* XRFdc_IsADCBlockEnabled(), XRFdc_IsDACDigitalPathEnabled() &
* XRFdc_IsADCDigitalPathEnabled() APIs now derive answer from
* DRP rather than context structure.
* cog 06/12/19 Fixed issue where positive NCO frequencies were not being
* set correctly.
* cog 07/14/19 Added new off mode for mixers (both mixers off).
* cog 07/16/19 The powerup state is not necessary to be checked for the
* tile/block/digital path enabled functions and had potential
* to cause lockout.
* cog 07/16/19 Added XRFdc_SetDACOpCurr() API.
* cog 07/18/19 Added XRFdc_S/GetDigitalStepAttenuator() APIs.
* cog 07/25/19 Added new XRFdc_RegisterMetal() API to register RFDC with Libmetal.
* cog 07/25/19 Moved XRFDC_PLL_LOCK_DLY_CNT macro from source file.
* cog 07/26/19 Added new XRFdc_S/GetLegacyCompatibilityMode() APIs.
* cog 07/29/19 Added XRFdc_GetEnabledInterrupts() API.
* cog 08/02/19 Formatting changes and added a MACRO for the IP generation.
* cog 09/01/19 Changed the MACRO for turning off the mixer.
* cog 09/01/19 XRFdc_CheckTileEnabled(), XRFdc_IsDACBlockEnabled(),
* XRFdc_IsADCBlockEnabled(), XRFdc_IsDACDigitalPathEnabled() &
* XRFdc_IsADCDigitalPathEnabled() APIs now get answer from
* context structure.
* cog 09/01/19 Rename new XRFdc_S/GetLegacyCompatibilityMode() APIs to
* XRFdc_S/GetDACCompMode().
* cog 09/01/19 Rename XRFdc_S/GetDigitalStepAttenuator() APIs to XRFdc_S/GetDSA().
* Also, add new XRFdc_DSA_Settings structure.
* cog 09/12/19 Swapped MIXER_TYPE_OFF and MIXER_TYPE_DISABLED macros.
* cog 09/18/19 Minumum output divider is now 1 for Gen 3 devices.
* cog 09/18/19 Changed clock distribution macros, also removed prototype for a function
* that is now static.
* cog 10/02/19 Added macros for the clock divider.
* cog 10/02/19 Added macro for fabric rate of 16.
* cog 10/02/19 Added macros for new VCO ranges.
* 7.1 cog 11/14/19 Increased ADC fabric read rate to 12 words per cycle for Gen 3 devices.
* cog 11/15/19 Added macros for calibration mode support for Gen 3 devices.
* cog 11/28/19 Datapath mode macros have been changed to reflect the new functionality.
* cog 01/08/20 Added programmable hysteresis counters for ADC signal detector.
* cog 01/23/20 Calibration modes for Gen 3 were inverted.
* 8.0 cog 02/10/20 Updated addtogroup and added s16 typedef.
* cog 02/10/20 Added Silicon revison to dirver structures to allow discrimation
* between engineering sample & production silicon.
* cog 02/17/20 Driver now gets tile/path enables from the bitfile.
* cog 02/20/20 Added macros for Clock Gater handling.
* cog 03/05/20 IMR datapath modes require the frequency word to be doubled.
* cog 03/20/20 Updated PowerState masks for Gen 3 Devices.
*
* </pre>
*
******************************************************************************/
#ifndef RFDC_H_
#define RFDC_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include <stdlib.h>
#include <stdint.h>
#ifdef __BAREMETAL__
#include "xil_assert.h"
#include "xdebug.h"
#include "sleep.h"
#endif
#include <metal/sys.h>
#include <metal/device.h>
#include <metal/irq.h>
#include <metal/atomic.h>
#include <metal/io.h>
#include <metal/sleep.h>
#include "metal/alloc.h"
#include "xrfdc_hw.h"
/**************************** Type Definitions *******************************/
#define XRFdc_IsADC4GSPS(InstPtr) XRFdc_IsHighSpeedADC(InstPtr, 0)
#ifndef __BAREMETAL__
typedef __u32 u32;
typedef __u16 u16;
typedef __u8 u8;
typedef __s32 s32;
typedef __s16 s16;
typedef __u64 u64;
typedef __s64 s64;
typedef __s8 s8;
#endif
/**
* The handler data type allows the user to define a callback function to
* respond to interrupt events in the system. This function is executed
* in interrupt context, so amount of processing should be minimized.
*
* @param CallBackRef is the callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* not important to the driver, so it is a void pointer.
* @param Type indicates ADC/DAC.
* @param Tile_Id indicates Tile number (0-3).
* @param Block_Id indicates Block number (0-3).
* @param StatusEvent indicates one or more interrupt occurred.
*/
typedef void (*XRFdc_StatusHandler)(void *CallBackRef, u32 Type, u32 Tile_Id, u32 Block_Id, u32 StatusEvent);
#ifndef __BAREMETAL__
#pragma pack(1)
#endif
/**
* PLL settings.
*/
typedef struct {
u32 Enabled; /* PLL Enables status (not a setter) */
double RefClkFreq;
double SampleRate;
u32 RefClkDivider;
u32 FeedbackDivider;
u32 OutputDivider;
u32 FractionalMode; /* Fractional mode is currently not supported */
u64 FractionalData; /* Fractional data is currently not supported */
u32 FractWidth; /* Fractional width is currently not supported */
} XRFdc_PLL_Settings;
/**
* ClkIntraTile Settings.
*/
typedef struct {
u8 SourceTile;
u8 PLLEnable;
XRFdc_PLL_Settings PLLSettings;
u8 DivisionFactor;
u8 Delay;
u8 DistributedClock;
} XRFdc_Tile_Clock_Settings;
/**
* Clk Distribution.
*/
typedef struct {
u8 Enabled;
u8 DistributionSource;
u8 UpperBound;
u8 LowerBound;
u8 MaxDelay;
u8 MinDelay;
u8 IsDelayBalanced;
} XRFdc_Distribution;
/**
* Clk Distribution Settings.
*/
typedef struct {
XRFdc_Tile_Clock_Settings DAC[4];
XRFdc_Tile_Clock_Settings ADC[4];
XRFdc_Distribution DistributionStatus[8];
} XRFdc_Distribution_Settings;
#ifndef __BAREMETAL__
#pragma pack()
#endif
/**
* ADC Signal Detect Settings.
*/
typedef struct {
u8 Mode;
u8 TimeConstant;
u8 Flush;
u8 EnableIntegrator;
u16 HighThreshold;
u16 LowThreshold;
u16 HighThreshOnTriggerCnt; /* the number of times value must exceed HighThreshold before turning on*/
u16 HighThreshOffTriggerCnt; /* the number of times value must be less than HighThreshold before turning off*/
u16 LowThreshOnTriggerCnt; /* the number of times value must exceed LowThreshold before turning on*/
u16 LowThreshOffTriggerCnt; /* the number of times value must be less than LowThreshold before turning off*/
u8 HysteresisEnable;
} XRFdc_Signal_Detector_Settings;
/**
* QMC settings.
*/
typedef struct {
u32 EnablePhase;
u32 EnableGain;
double GainCorrectionFactor;
double PhaseCorrectionFactor;
s32 OffsetCorrectionFactor;
u32 EventSource;
} XRFdc_QMC_Settings;
/**
* Coarse delay settings.
*/
typedef struct {
u32 CoarseDelay;
u32 EventSource;
} XRFdc_CoarseDelay_Settings;
/**
* Mixer settings.
*/
typedef struct {
double Freq;
double PhaseOffset;
u32 EventSource;
u32 CoarseMixFreq;
u32 MixerMode;
u8 FineMixerScale; /* NCO output scale, valid values 0,1 and 2 */
u8 MixerType;
} XRFdc_Mixer_Settings;
/**
* ADC block Threshold settings.
*/
typedef struct {
u32 UpdateThreshold; /* Selects which threshold to update */
u32 ThresholdMode[2]; /* Entry 0 for Threshold0 and 1 for Threshold1 */
u32 ThresholdAvgVal[2]; /* Entry 0 for Threshold0 and 1 for Threshold1 */
u32 ThresholdUnderVal[2]; /* Entry 0 for Threshold0 and 1 for Threshold1 */
u32 ThresholdOverVal[2]; /* Entry 0 is for Threshold0 and 1 for Threshold1 */
} XRFdc_Threshold_Settings;
/**
* RFSoC Calibration coefficients generic struct
*/
typedef struct {
u32 Coeff0;
u32 Coeff1;
u32 Coeff2;
u32 Coeff3;
u32 Coeff4;
u32 Coeff5;
u32 Coeff6;
u32 Coeff7;
} XRFdc_Calibration_Coefficients;
/**
* RFSoC DSA settings
*/
typedef struct {
u32 DisableRTS; /*Disables RTS control of DSA attenuation*/
float Attenuation; /*Attenuation*/
} XRFdc_DSA_Settings;
/**
* RFSoC Calibration freeze settings struct
*/
typedef struct {
u32 CalFrozen; /*Status indicates calibration freeze state*/
u32 DisableFreezePin; /*Disable the calibration freeze pin*/
u32 FreezeCalibration; /*Setter for freezing*/
} XRFdc_Cal_Freeze_Settings;
/**
* RFSoC Tile status.
*/
typedef struct {
u32 IsEnabled; /* 1, if tile is enabled, 0 otherwise */
u32 TileState; /* Indicates Tile Current State */
u8 BlockStatusMask; /* Bit mask for block status, 1 indicates block enable */
u32 PowerUpState;
u32 PLLState;
} XRFdc_TileStatus;
/**
* RFSoC Data converter IP status.
*/
typedef struct {
XRFdc_TileStatus DACTileStatus[4];
XRFdc_TileStatus ADCTileStatus[4];
u32 State;
} XRFdc_IPStatus;
/**
* status of DAC or ADC blocks in the RFSoC Data converter.
*/
typedef struct {
double SamplingFreq;
u32 AnalogDataPathStatus;
u32 DigitalDataPathStatus;
u8 DataPathClocksStatus; /* Indicates all required datapath
clocks are enabled or not, 1 if all clocks enabled, 0 otherwise */
u8 IsFIFOFlagsEnabled; /* Indicates FIFO flags enabled or not,
1 if all flags enabled, 0 otherwise */
u8 IsFIFOFlagsAsserted; /* Indicates FIFO flags asserted or not,
1 if all flags asserted, 0 otherwise */
} XRFdc_BlockStatus;
#ifndef __BAREMETAL__
#pragma pack(1)
#endif
/**
* DAC block Analog DataPath Config settings.
*/
typedef struct {
u32 BlockAvailable;
u32 InvSyncEnable;
u32 MixMode;
u32 DecoderMode;
} XRFdc_DACBlock_AnalogDataPath_Config;
/**
* DAC block Digital DataPath Config settings.
*/
typedef struct {
u32 MixerInputDataType;
u32 DataWidth;
u32 InterpolationMode;
u32 FifoEnable;
u32 AdderEnable;
u32 MixerType;
} XRFdc_DACBlock_DigitalDataPath_Config;
/**
* ADC block Analog DataPath Config settings.
*/
typedef struct {
u32 BlockAvailable;
u32 MixMode;
} XRFdc_ADCBlock_AnalogDataPath_Config;
/**
* DAC block Digital DataPath Config settings.
*/
typedef struct {
u32 MixerInputDataType;
u32 DataWidth;
u32 DecimationMode;
u32 FifoEnable;
u32 MixerType;
} XRFdc_ADCBlock_DigitalDataPath_Config;
/**
* DAC Tile Config structure.
*/
typedef struct {
u32 Enable;
u32 PLLEnable;
double SamplingRate;
double RefClkFreq;
double FabClkFreq;
u32 FeedbackDiv;
u32 OutputDiv;
u32 RefClkDiv;
u32 MultibandConfig;
double MaxSampleRate;
u32 NumSlices;
XRFdc_DACBlock_AnalogDataPath_Config DACBlock_Analog_Config[4];
XRFdc_DACBlock_DigitalDataPath_Config DACBlock_Digital_Config[4];
} XRFdc_DACTile_Config;
/**
* ADC Tile Config Structure.
*/
typedef struct {
u32 Enable; /* Tile Enable status */
u32 PLLEnable; /* PLL enable Status */
double SamplingRate;
double RefClkFreq;
double FabClkFreq;
u32 FeedbackDiv;
u32 OutputDiv;
u32 RefClkDiv;
u32 MultibandConfig;
double MaxSampleRate;
u32 NumSlices;
XRFdc_ADCBlock_AnalogDataPath_Config ADCBlock_Analog_Config[4];
XRFdc_ADCBlock_DigitalDataPath_Config ADCBlock_Digital_Config[4];
} XRFdc_ADCTile_Config;
/**
* RFdc Config Structure.
*/
typedef struct {
u32 DeviceId;
metal_phys_addr_t BaseAddr;
u32 ADCType; /* ADC Type 4GSPS or 2GSPS*/
u32 MasterADCTile; /* ADC master Tile */
u32 MasterDACTile; /* DAC Master Tile */
u32 ADCSysRefSource;
u32 DACSysRefSource;
u32 IPType;
u32 SiRevision;
XRFdc_DACTile_Config DACTile_Config[4];
XRFdc_ADCTile_Config ADCTile_Config[4];
} XRFdc_Config;
#ifndef __BAREMETAL__
#pragma pack()
#endif
/**
* DAC Block Analog DataPath Structure.
*/
typedef struct {
u32 Enabled; /* DAC Analog Data Path Enable */
u32 MixedMode;
double TerminationVoltage;
double OutputCurrent;
u32 InverseSincFilterEnable;
u32 DecoderMode;
void *FuncHandler;
u32 NyquistZone;
u8 AnalogPathEnabled;
u8 AnalogPathAvailable;
XRFdc_QMC_Settings QMC_Settings;
XRFdc_CoarseDelay_Settings CoarseDelay_Settings;
} XRFdc_DACBlock_AnalogDataPath;
/**
* DAC Block Digital DataPath Structure.
*/
typedef struct {
u32 MixerInputDataType;
u32 DataWidth;
int ConnectedIData;
int ConnectedQData;
u32 InterpolationFactor;
u8 DigitalPathEnabled;
u8 DigitalPathAvailable;
XRFdc_Mixer_Settings Mixer_Settings;
} XRFdc_DACBlock_DigitalDataPath;
/**
* ADC Block Analog DataPath Structure.
*/
typedef struct {
u32 Enabled; /* ADC Analog Data Path Enable */
XRFdc_QMC_Settings QMC_Settings;
XRFdc_CoarseDelay_Settings CoarseDelay_Settings;
XRFdc_Threshold_Settings Threshold_Settings;
u32 NyquistZone;
u8 CalibrationMode;
u8 AnalogPathEnabled;
u8 AnalogPathAvailable;
} XRFdc_ADCBlock_AnalogDataPath;
/**
* ADC Block Digital DataPath Structure.
*/
typedef struct {
u32 MixerInputDataType;
u32 DataWidth;
u32 DecimationFactor;
int ConnectedIData;
int ConnectedQData;
u8 DigitalPathEnabled;
u8 DigitalPathAvailable;
XRFdc_Mixer_Settings Mixer_Settings;
} XRFdc_ADCBlock_DigitalDataPath;
/**
* DAC Tile Structure.
*/
typedef struct {
u32 TileBaseAddr; /* Tile BaseAddress*/
u32 NumOfDACBlocks; /* Number of DAC block enabled */
XRFdc_PLL_Settings PLL_Settings;
u8 MultibandConfig;
XRFdc_DACBlock_AnalogDataPath DACBlock_Analog_Datapath[4];
XRFdc_DACBlock_DigitalDataPath DACBlock_Digital_Datapath[4];
} XRFdc_DAC_Tile;
/**
* ADC Tile Structure.
*/
typedef struct {
u32 TileBaseAddr;
u32 NumOfADCBlocks; /* Number of ADC block enabled */
XRFdc_PLL_Settings PLL_Settings;
u8 MultibandConfig;
XRFdc_ADCBlock_AnalogDataPath ADCBlock_Analog_Datapath[4];
XRFdc_ADCBlock_DigitalDataPath ADCBlock_Digital_Datapath[4];
} XRFdc_ADC_Tile;
/**
* RFdc Structure.
*/
typedef struct {
XRFdc_Config RFdc_Config; /* Config Structure */
u32 IsReady;
u32 ADC4GSPS;
metal_phys_addr_t BaseAddr; /* BaseAddress */
struct metal_io_region *io; /* Libmetal IO structure */
struct metal_device *device; /* Libmetal device structure */
XRFdc_DAC_Tile DAC_Tile[4];
XRFdc_ADC_Tile ADC_Tile[4];
XRFdc_StatusHandler StatusHandler; /* Event handler function */
void *CallBackRef; /* Callback reference for event handler */
u8 UpdateMixerScale; /* Set to 1, if user overwrite mixer scale */
} XRFdc;
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef __BAREMETAL__
#define Xil_AssertNonvoid(Expression) \
{ \
if (!(Expression)) { \
while (1) \
; \
} \
}
#define Xil_AssertVoid(Expression) \
{ \
if (!(Expression)) { \
while (1) \
; \
} \
}
#define Xil_AssertVoidAlways() \
{ \
while (1) \
; \
}
#endif
#define MAX(x, y) (x > y) ? x : y
#define MIN(x, y) (x < y) ? x : y
#define XRFDC_SUCCESS 0U
#define XRFDC_FAILURE 1U
#define XRFDC_GEN3 2
#define XRFDC_COMPONENT_IS_READY 0x11111111U
#define XRFDC_NUM_SLICES_HSADC 2
#define XRFDC_NUM_SLICES_LSADC 4
#ifndef __BAREMETAL__
#define XRFDC_PLATFORM_DEVICE_DIR "/sys/bus/platform/devices/"
#define XRFDC_BUS_NAME "platform"
#define XRFDC_SIGNATURE "usp_rf_data_converter" /* String in RFDC node name */
#define XRFDC_CONFIG_DATA_PROPERTY "param-list" /* device tree property */
#define XRFDC_COMPATIBLE_PROPERTY "compatible" /* device tree property */
#define XRFDC_NUM_INSTANCES_PROPERTY "num-insts" /* device tree property */
#define XRFDC_COMPATIBLE_STRING "xlnx,usp-rf-data-converter-"
#define XRFDC_DEVICE_ID_SIZE 4U
#define XRFDC_NUM_INST_SIZE 4U
#define XRFDC_CONFIG_DATA_SIZE sizeof(XRFdc_Config)
#else
#define XRFDC_BUS_NAME "generic"
#define XRFDC_DEV_NAME XPAR_XRFDC_0_DEV_NAME
#endif
#define XRFDC_REGION_SIZE 0x40000U
#define XRFDC_IP_BASE 0x0U
#define XRFDC_DRP_BASE(type, tile) \
((type) == XRFDC_ADC_TILE ? XRFDC_ADC_TILE_DRP_ADDR(tile) : XRFDC_DAC_TILE_DRP_ADDR(tile))
#define XRFDC_CTRL_STS_BASE(Type, Tile) \
((Type) == XRFDC_ADC_TILE ? XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile) : XRFDC_DAC_TILE_CTRL_STATS_ADDR(Tile))
#define XRFDC_BLOCK_BASE(Type, Tile, Block) \
((Type) == XRFDC_ADC_TILE ? (XRFDC_ADC_TILE_DRP_ADDR(Tile) + XRFDC_BLOCK_ADDR_OFFSET(Block)) : \
(XRFDC_DAC_TILE_DRP_ADDR(Tile) + XRFDC_BLOCK_ADDR_OFFSET(Block)))
#define XRFDC_ADC_TILE 0U
#define XRFDC_DAC_TILE 1U
#define XRFDC_TILE_ID_MAX 0x3U
#define XRFDC_BLOCK_ID_MAX 0x3U
#define XRFDC_EVNT_SRC_IMMEDIATE 0x00000000U
#define XRFDC_EVNT_SRC_SLICE 0x00000001U
#define XRFDC_EVNT_SRC_TILE 0x00000002U
#define XRFDC_EVNT_SRC_SYSREF 0x00000003U
#define XRFDC_EVNT_SRC_MARKER 0x00000004U
#define XRFDC_EVNT_SRC_PL 0x00000005U
#define XRFDC_EVENT_MIXER 0x00000001U
#define XRFDC_EVENT_CRSE_DLY 0x00000002U
#define XRFDC_EVENT_QMC 0x00000004U
#define XRFDC_SELECT_ALL_TILES -1
#define XRFDC_ADC_4GSPS 1U
#define XRFDC_CRSE_DLY_MAX 0x7U
#define XRFDC_CRSE_DLY_MAX_EXT 0x28U
#define XRFDC_NCO_FREQ_MULTIPLIER (0x1LLU << 48U) /* 2^48 */
#define XRFDC_NCO_PHASE_MULTIPLIER (1U << 17U) /* 2^17 */
#define XRFDC_QMC_PHASE_MULT (1U << 11U) /* 2^11 */
#define XRFDC_QMC_GAIN_MULT (1U << 14U) /* 2^14 */
#define XRFDC_DATA_TYPE_IQ 0x00000001U
#define XRFDC_DATA_TYPE_REAL 0x00000000U
#define XRFDC_TRSHD_OFF 0x0U
#define XRFDC_TRSHD_STICKY_OVER 0x00000001U
#define XRFDC_TRSHD_STICKY_UNDER 0x00000002U
#define XRFDC_TRSHD_HYSTERISIS 0x00000003U
/* Mixer modes */
#define XRFDC_MIXER_MODE_OFF 0x0U
#define XRFDC_MIXER_MODE_C2C 0x1U
#define XRFDC_MIXER_MODE_C2R 0x2U
#define XRFDC_MIXER_MODE_R2C 0x3U
#define XRFDC_MIXER_MODE_R2R 0x4U
#define XRFDC_I_IQ_COS_MINSIN 0x00000C00U
#define XRFDC_Q_IQ_SIN_COS 0x00001000U
#define XRFDC_EN_I_IQ 0x00000001U
#define XRFDC_EN_Q_IQ 0x00000004U
#define XRFDC_MIXER_TYPE_COARSE 0x1U
#define XRFDC_MIXER_TYPE_FINE 0x2U
#define XRFDC_MIXER_TYPE_OFF 0x0U
#define XRFDC_MIXER_TYPE_DISABLED 0x3U
#define XRFDC_COARSE_MIX_OFF 0x0U
#define XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO 0x2U
#define XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR 0x4U
#define XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR 0x8U
#define XRFDC_COARSE_MIX_BYPASS 0x10U
#define XRFDC_COARSE_MIX_MODE_C2C_C2R 0x1U
#define XRFDC_COARSE_MIX_MODE_R2C 0x2U
#define XRFDC_CRSE_MIX_OFF 0x924U
#define XRFDC_CRSE_MIX_BYPASS 0x0U
#define XRFDC_CRSE_4GSPS_ODD_FSBYTWO 0x492U
#define XRFDC_CRSE_MIX_I_ODD_FSBYFOUR 0x2CBU
#define XRFDC_CRSE_MIX_Q_ODD_FSBYFOUR 0x659U
#define XRFDC_CRSE_MIX_I_Q_FSBYTWO 0x410U
#define XRFDC_CRSE_MIX_I_FSBYFOUR 0x298U
#define XRFDC_CRSE_MIX_Q_FSBYFOUR 0x688U
#define XRFDC_CRSE_MIX_I_MINFSBYFOUR 0x688U
#define XRFDC_CRSE_MIX_Q_MINFSBYFOUR 0x298U
#define XRFDC_CRSE_MIX_R_I_FSBYFOUR 0x8A0U
#define XRFDC_CRSE_MIX_R_Q_FSBYFOUR 0x70CU
#define XRFDC_CRSE_MIX_R_I_MINFSBYFOUR 0x8A0U
#define XRFDC_CRSE_MIX_R_Q_MINFSBYFOUR 0x31CU
#define XRFDC_MIXER_SCALE_AUTO 0x0U
#define XRFDC_MIXER_SCALE_1P0 0x1U
#define XRFDC_MIXER_SCALE_0P7 0x2U
#define XRFDC_MIXER_PHASE_OFFSET_UP_LIMIT 180
#define XRFDC_MIXER_PHASE_OFFSET_LOW_LIMIT (-180)
#define XRFDC_UPDATE_THRESHOLD_0 0x1U
#define XRFDC_UPDATE_THRESHOLD_1 0x2U
#define XRFDC_UPDATE_THRESHOLD_BOTH 0x4U
#define XRFDC_THRESHOLD_CLRMD_MANUAL_CLR 0x1U
#define XRFDC_THRESHOLD_CLRMD_AUTO_CLR 0x2U
#define XRFDC_DECODER_MAX_SNR_MODE 0x1U
#define XRFDC_DECODER_MAX_LINEARITY_MODE 0x2U
#define XRFDC_OUTPUT_CURRENT_32MA 32U
#define XRFDC_OUTPUT_CURRENT_20MA 20U
#define XRFDC_ADC_MIXER_MODE_IQ 0x1U
#define XRFDC_DAC_MIXER_MODE_REAL 0x2U
#define XRFDC_ODD_NYQUIST_ZONE 0x1U
#define XRFDC_EVEN_NYQUIST_ZONE 0x2U
#define XRFDC_INTERP_DECIM_OFF 0x0U
#define XRFDC_INTERP_DECIM_1X 0x1U
#define XRFDC_INTERP_DECIM_2X 0x2U
#define XRFDC_INTERP_DECIM_3X 0x3U
#define XRFDC_INTERP_DECIM_4X 0x4U
#define XRFDC_INTERP_DECIM_5X 0x5U
#define XRFDC_INTERP_DECIM_6X 0x6U
#define XRFDC_INTERP_DECIM_8X 0x8U
#define XRFDC_INTERP_DECIM_10X 0xAU
#define XRFDC_INTERP_DECIM_12X 0xCU
#define XRFDC_INTERP_DECIM_16X 0x10U
#define XRFDC_INTERP_DECIM_20X 0x14U
#define XRFDC_INTERP_DECIM_24X 0x18U
#define XRFDC_INTERP_DECIM_40X 0x28U
#define XRFDC_FAB_CLK_DIV1 0x1U
#define XRFDC_FAB_CLK_DIV2 0x2U
#define XRFDC_FAB_CLK_DIV4 0x3U
#define XRFDC_FAB_CLK_DIV8 0x4U
#define XRFDC_FAB_CLK_DIV16 0x5U
#define XRFDC_CALIB_MODE1 0x1U
#define XRFDC_CALIB_MODE2 0x2U
#define XRFDC_CALIB_MODE_ABS_DIFF 0x1U
#define XRFDC_CALIB_MODE_NEG_ABS_SUM 0x2U
#define XRFDC_TI_DCB_MODE1_4GSPS 0x00007800U
#define XRFDC_TI_DCB_MODE1_2GSPS 0x00005000U
/* PLL Configuration */
#define XRFDC_PLL_UNLOCKED 0x1U
#define XRFDC_PLL_LOCKED 0x2U
#define XRFDC_EXTERNAL_CLK 0x0U
#define XRFDC_INTERNAL_PLL_CLK 0x1U
#define PLL_FPDIV_MIN 13U
#define PLL_FPDIV_MAX 128U
#define PLL_DIVIDER_MIN 2U
#define PLL_DIVIDER_MIN_GEN3 1U
#define PLL_DIVIDER_MAX 28U
#define VCO_RANGE_MIN 8500U
#define VCO_RANGE_MAX 13200U
#define VCO_RANGE_ADC_MIN 8500U
#define VCO_RANGE_ADC_MAX 12800U
#define VCO_RANGE_DAC_MIN 7800U
#define VCO_RANGE_DAC_MAX 13800U
#define XRFDC_PLL_LPF1_VAL 0x6U
#define XRFDC_PLL_CRS2_VAL 0x7008U
#define XRFDC_VCO_UPPER_BAND 0x0U
#define XRFDC_VCO_LOWER_BAND 0x1U
#define XRFDC_REF_CLK_DIV_1 0x1U
#define XRFDC_REF_CLK_DIV_2 0x2U
#define XRFDC_REF_CLK_DIV_3 0x3U
#define XRFDC_REF_CLK_DIV_4 0x4U
#define XRFDC_SINGLEBAND_MODE 0x1U
#define XRFDC_MULTIBAND_MODE_2X 0x2U
#define XRFDC_MULTIBAND_MODE_4X 0x4U
#define XRFDC_MB_DATATYPE_C2C 0x1U
#define XRFDC_MB_DATATYPE_R2C 0x2U
#define XRFDC_MB_DATATYPE_C2R 0x4U
#define XRFDC_SB_C2C_BLK0 0x82U
#define XRFDC_SB_C2C_BLK1 0x64U
#define XRFDC_SB_C2R 0x40U
#define XRFDC_MB_C2C_BLK0 0x5EU
#define XRFDC_MB_C2C_BLK1 0x5DU
#define XRFDC_MB_C2R_BLK0 0x5CU
#define XRFDC_MB_C2R_BLK1 0x0U
#define XRFDC_MIXER_MODE_BYPASS 0x2U
#define XRFDC_LINK_COUPLING_DC 0x0U
#define XRFDC_LINK_COUPLING_AC 0x1U
#define XRFDC_MB_MODE_SB 0x0U
#define XRFDC_MB_MODE_2X_BLK01 0x1U
#define XRFDC_MB_MODE_2X_BLK23 0x2U
#define XRFDC_MB_MODE_2X_BLK01_BLK23 0x3U
#define XRFDC_MB_MODE_4X 0x4U
#define XRFDC_MILLI 1000U
#define XRFDC_DAC_SAMPLING_MIN 500
#define XRFDC_DAC_SAMPLING_MAX 6554
#define XRFDC_ADC_4G_SAMPLING_MIN 1000
#define XRFDC_ADC_4G_SAMPLING_MAX 4116
#define XRFDC_ADC_2G_SAMPLING_MIN 500
#define XRFDC_ADC_2G_SAMPLING_MAX 2058
#define XRFDC_REFFREQ_MIN 102.40625
#define XRFDC_REFFREQ_MAX 614.0
#define XRFDC_DIGITALPATH_ENABLE 0x1U
#define XRFDC_ANALOGPATH_ENABLE 0x1U
#define XRFDC_BLK_ID0 0x0U
#define XRFDC_BLK_ID1 0x1U
#define XRFDC_BLK_ID2 0x2U
#define XRFDC_BLK_ID3 0x3U
#define XRFDC_BLK_ID4 0x4U
#define XRFDC_BLK_ID_NONE -1
#define XRFDC_BLK_ID_ALL -1
#define XRFDC_BLK_ID_INV 0x4
#define XRFDC_TILE_ID0 0x0U
#define XRFDC_TILE_ID1 0x1U
#define XRFDC_TILE_ID2 0x2U
#define XRFDC_TILE_ID3 0x3U
#define XRFDC_TILE_ID4 0x4U
#define XRFDC_TILE_ID_INV 0x4U
#define XRFDC_NUM_OF_BLKS1 0x1U
#define XRFDC_NUM_OF_BLKS2 0x2U
#define XRFDC_NUM_OF_BLKS3 0x3U
#define XRFDC_NUM_OF_BLKS4 0x4U
#define XRFDC_NUM_OF_TILES1 0x1U
#define XRFDC_NUM_OF_TILES2 0x2U
#define XRFDC_NUM_OF_TILES3 0x3U
#define XRFDC_NUM_OF_TILES4 0x4U
#define XRFDC_SM_STATE0 0x0U
#define XRFDC_SM_STATE1 0x1U
#define XRFDC_SM_STATE15 0xFU
#define XRFDC_DECIM_4G_DATA_TYPE 0x3U
#define XRFDC_DECIM_2G_IQ_DATA_TYPE 0x2U
#define XRFDC_DAC_MAX_WR_FAB_RATE 16U
#define XRFDC_ADC_MAX_RD_FAB_RATE(X) ((X < XRFDC_GEN3) ? 8U : 12U)
#define XRFDC_MIN_PHASE_CORR_FACTOR -26.5
#define XRFDC_MAX_PHASE_CORR_FACTOR 26.5
#define XRFDC_MAX_GAIN_CORR_FACTOR 2.0
#define XRFDC_MIN_GAIN_CORR_FACTOR 0.0
#define XRFDC_FAB_RATE_16 16
#define XRFDC_FAB_RATE_8 8
#define XRFDC_FAB_RATE_4 4
#define XRFDC_FAB_RATE_2 2
#define XRFDC_FAB_RATE_1 1
#define XRFDC_HSCOM_PWR_STATS_PLL 0xFFC0U
#define XRFDC_HSCOM_PWR_STATS_EXTERNAL 0xF240U
#define XRFDC_HSCOM_PWR_STATS_RX_EXT 0xF2FCU
#define XRFDC_HSCOM_PWR_STATS_DIST_EXT 0xF0FEU
#define XRFDC_HSCOM_PWR_STATS_RX_PLL 0xFFFCU
#define XRFDC_HSCOM_PWR_STATS_DIST_PLL 0xFDFEU
#define XRFDC_HSCOM_PWR_STATS_RX_EXT_DIV 0xF2FCU
#define XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV 0xF0FE
#define XRFDC_HSCOM_PWR_STATS_DIST_EXT_SRC 0xF2FCU
#define XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC 0xF2FCU
#define XRFDC_CLK_DST_TILE_231 0
#define XRFDC_CLK_DST_TILE_230 1
#define XRFDC_CLK_DST_TILE_229 2
#define XRFDC_CLK_DST_TILE_228 3
#define XRFDC_CLK_DST_TILE_227 4
#define XRFDC_CLK_DST_TILE_226 5
#define XRFDC_CLK_DST_TILE_225 6
#define XRFDC_CLK_DST_TILE_224 7
#define XRFDC_CLK_DST_INVALID 0xFFU
#define XRFDC_GLBL_OFST_DAC 0U
#define XRFDC_GLBL_OFST_ADC 4U
#define XRFDC_TILE_GLBL_ADDR(X, Y) (Y + ((X == XRFDC_ADC_TILE) ? XRFDC_GLBL_OFST_ADC : XRFDC_GLBL_OFST_DAC))
#define XRFDC_CLK_DISTR_MUX4A_SRC_INT 0x0008U
#define XRFDC_CLK_DISTR_MUX4A_SRC_STH 0x0000U
#define XRFDC_CLK_DISTR_MUX6_SRC_OFF 0x0000U
#define XRFDC_CLK_DISTR_MUX6_SRC_INT 0x0100U
#define XRFDC_CLK_DISTR_MUX6_SRC_NTH 0x0080U
#define XRFDC_CLK_DISTR_MUX7_SRC_OFF 0x0000U
#define XRFDC_CLK_DISTR_MUX7_SRC_STH 0x0200U
#define XRFDC_CLK_DISTR_MUX7_SRC_INT 0x0400U
#define XRFDC_CLK_DISTR_MUX8_SRC_NTH 0x0000U
#define XRFDC_CLK_DISTR_MUX8_SRC_INT 0x8000U
#define XRFDC_CLK_DISTR_MUX9_SRC_NTH 0x4000U
#define XRFDC_CLK_DISTR_MUX9_SRC_INT 0x0000U
#define XRFDC_CLK_DISTR_MUX5A_SRC_PLL 0x0800U
#define XRFDC_CLK_DISTR_MUX5A_SRC_RX 0x0040U
#define XRFDC_CLK_DISTR_OFF \
(XRFDC_CLK_DISTR_MUX4A_SRC_INT | XRFDC_CLK_DISTR_MUX6_SRC_OFF | XRFDC_CLK_DISTR_MUX7_SRC_OFF | \
XRFDC_CLK_DISTR_MUX8_SRC_NTH | XRFDC_CLK_DISTR_MUX9_SRC_INT)
#define XRFDC_CLK_DISTR_LEFTMOST_TILE 0x0000U
#define XRFDC_CLK_DISTR_CONT_LEFT_EVEN 0x8208U
#define XRFDC_CLK_DISTR_CONT_LEFT_ODD 0x8200U
#define XRFDC_CLK_DISTR_RIGHTMOST_TILE 0x4008
#define XRFDC_CLK_DISTR_CONT_RIGHT_EVEN 0x4080
#define XRFDC_CLK_DISTR_CONT_RIGHT_HWL_ODD 0x4088
#define XRFDC_CLK_DISTR_MUX4A_SRC_CLR 0x0008U
#define XRFDC_CLK_DISTR_MUX6_SRC_CLR 0x0180U
#define XRFDC_CLK_DISTR_MUX7_SRC_CLR 0x0600U
#define XRFDC_CLK_DISTR_MUX8_SRC_CLR 0x8000U
#define XRFDC_CLK_DISTR_MUX9_SRC_CLR 0x4000U
#define XRFDC_DIST_MAX 8
#define XRFDC_NET_CTRL_CLK_REC_PLL 0x1U
#define XRFDC_NET_CTRL_CLK_REC_DIST_T1 0x2U
#define XRFDC_NET_CTRL_CLK_T1_SRC_LOCAL 0x4U
#define XRFDC_NET_CTRL_CLK_T1_SRC_DIST 0x8U
#define XRFDC_NET_CTRL_CLK_INPUT_DIST 0x20U
#define XRFDC_DIST_CTRL_TO_PLL_DIV 0x10U
#define XRFDC_DIST_CTRL_TO_T1 0x20U
#define XRFDC_DIST_CTRL_DIST_SRC_LOCAL 0x40U
#define XRFDC_DIST_CTRL_DIST_SRC_PLL 0x800U
#define XRFDC_DIST_CTRL_CLK_T1_SRC_LOCAL 0x1000U
#define XRFDC_PLLREFDIV_INPUT_OFF 0x20U
#define XRFDC_PLLREFDIV_INPUT_DIST 0x40U
#define XRFDC_PLLREFDIV_INPUT_FABRIC 0x60U
#define XRFDC_PLLOPDIV_INPUT_DIST_LOCAL 0x800U
#define XRFDC_TILE_SOURCE_RX 0U
#define XRFDC_TILE_SOURCE_DIST 1U
#define XRFDC_TILE_SOURCE_FABRIC 2U
#define XRFDC_DIST_OUT_NONE 0U
#define XRFDC_DIST_OUT_RX 1U
#define XRFDC_DIST_OUT_OUTDIV 2U
#define XRFDC_PLL_SOURCE_NONE 0U
#define XRFDC_PLL_SOURCE_RX 1U
#define XRFDC_PLL_SOURCE_OUTDIV 2U
#define XRFDC_PLL_OUTDIV_MODE_1 0x0U
#define XRFDC_PLL_OUTDIV_MODE_2 0x1U
#define XRFDC_PLL_OUTDIV_MODE_3 0x2U
#define XRFDC_PLL_OUTDIV_MODE_N 0x3U
#define XRFDC_PLL_OUTDIV_MODE_3_VAL 0x1U
#define XRFDC_DIVISION_FACTOR_MIN 1
#define XRFDC_DITH_ENABLE 1
#define XRFDC_DITH_DISABLE 0
#define XRFDC_SIGDET_MODE_AVG 0
#define XRFDC_SIGDET_MODE_RNDM 1
#define XRFDC_SIGDET_TC_2_0 0
#define XRFDC_SIGDET_TC_2_2 1
#define XRFDC_SIGDET_TC_2_4 2
#define XRFDC_SIGDET_TC_2_8 3
#define XRFDC_SIGDET_TC_2_12 4
#define XRFDC_SIGDET_TC_2_14 5
#define XRFDC_SIGDET_TC_2_16 6
#define XRFDC_SIGDET_TC_2_18 7
#define XRFDC_DISABLED 0
#define XRFDC_ENABLED 1
#define XRFDC_CAL_BLOCK_OCB1 0
#define XRFDC_CAL_BLOCK_OCB2 1
#define XRFDC_CAL_BLOCK_GCB 2
#define XRFDC_CAL_BLOCK_TSCB 3
#define XRFDC_INV_SYNC_MODE_MAX 2
#define XRFDC_INV_SYNC_EN_MAX 1
#define XRFDC_CTRL_MASK 0x0440
#define XRFDC_EXPORTCTRL_CLKDIST 0x0400
#define XRFDC_PREMIUMCTRL_CLKDIST 0x0040
#define XRFDC_EXPORTCTRL_VOP 0x2000
#define XRFDC_EXPORTCTRL_DSA 0x0400
#define XRFDC_DATAPATH_MODE_DUC_0_FSDIVTWO 1U
#define XRFDC_DATAPATH_MODE_DUC_0_FSDIVFOUR 2U
#define XRFDC_DATAPATH_MODE_FSDIVFOUR_FSDIVTWO 3U
#define XRFDC_DATAPATH_MODE_NODUC_0_FSDIVTWO 4U
#define XRFDC_DAC_INT_MODE_FULL_BW 0U
#define XRFDC_DAC_INT_MODE_HALF_BW_IMR 2U
#define XRFDC_DAC_INT_MODE_FULL_BW_BYPASS 3U
#define XRFDC_DAC_MODE_MAX XRFDC_DATAPATH_MODE_NODUC_0_FSDIVTWO
#define XRFDC_FULL_BW_DIVISOR 1U
#define XRFDC_HALF_BW_DIVISOR 2U
#define XRFDC_DAC_IMR_MODE_LOWPASS 0U
#define XRFDC_DAC_IMR_MODE_HIGHPASS 1U
#define XRFDC_DAC_IMR_MODE_MAX XRFDC_DAC_IMR_MODE_HIGHPASS
#define XRFDC_CLOCK_DETECT_CLK 0x1U
#define XRFDC_CLOCK_DETECT_DIST 0x2U
#define XRFDC_CLOCK_DETECT_BOTH 0x3U
#define XRFDC_CAL_UNFREEZE_CALIB 0U
#define XRFDC_CAL_FREEZE_CALIB 1U
#define XRFDC_CAL_FRZ_PIN_ENABLE 0U
#define XRFDC_CAL_FRZ_PIN_DISABLE 1U
#define XRFDC_CLK_REG_EN_MASK 0x2000U
#define XRFDC_GEN1_LOW_I 20000U
#define XRFDC_GEN1_HIGH_I 32000U
#define XRFDC_MIN_I_UA 6425U
#define XRFDC_MAX_I_UA 32000U
#define XRFDC_STEP_I_UA 25U
#define XRFDC_BLDR_GAIN 0x0000U
#define XRFDC_CSCAS_BLDR 0xE000U
#define XRFDC_CSCAS_BIAS 0x001BU
#define XRFDC_MAX_ATTEN 11
#define XRFDC_MIN_ATTEN 0
#define XRFDC_STEP_ATTEN 0.5
#define XRFDC_DAC_VOP_CTRL_REG_UPDT_MASK 0x2U
#define XRFDC_DAC_VOP_CTRL_TST_BLD_MASK 0x1U
#define XRFDC_PLL_LOCK_DLY_CNT 1000U
#define XRFDC_CLK_DIV_DP_FIRST_MODE 0x10U
#define XRFDC_CLK_DIV_DP_OTHER_MODES 0x20U
#define XRFDC_TILE_STARTED XRFDC_SM_STATE15
#define XRFDC_SI_REV_ES 0U
#define XRFDC_SI_REV_PROD 1U
#define XRFDC_CG_WAIT_CYCLES 3U
#define XRFDC_ADC_CG_WAIT_CYCLES 1U
#define XRFDC_CG_CYCLES_TOTAL_X1_X2_X4_X8 0U
#define XRFDC_CG_CYCLES_KEPT_X1_X2_X4_X8 1U
#define XRFDC_CG_CYCLES_TOTAL_X3_X6_X12 3U
#define XRFDC_CG_CYCLES_KEPT_X3_X6_X12 2U
#define XRFDC_CG_CYCLES_TOTAL_X5_X10 5U
#define XRFDC_CG_CYCLES_KEPT_X5_X10 4U
#define XRFDC_CG_CYCLES_TOTAL_X16 2U
#define XRFDC_CG_CYCLES_KEPT_X16 1U
#define XRFDC_CG_CYCLES_TOTAL_X20 5U
#define XRFDC_CG_CYCLES_KEPT_X20 2U
#define XRFDC_CG_CYCLES_TOTAL_X24 3U
#define XRFDC_CG_CYCLES_KEPT_X24 1U
#define XRFDC_CG_CYCLES_TOTAL_X40 5U
#define XRFDC_CG_CYCLES_KEPT_X40 1U
#define XRFDC_CG_FIXED_OFS 2U
/*****************************************************************************/
/**
*
* Execute Read modify Write
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddr is address of a block.
* @param RegAddr is register offset value.
* @param Mask contains bit mask value.
* @param Data contains value to be written to register.
*
* @return
* - None
*
******************************************************************************/
static inline void XRFdc_ClrSetReg(XRFdc *InstancePtr, u32 BaseAddr, u32 RegAddr, u16 Mask, u16 Data)
{
u16 ReadReg;
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, RegAddr);
ReadReg = (ReadReg & ~Mask) | (Data & Mask);
XRFdc_WriteReg16(InstancePtr, BaseAddr, RegAddr, ReadReg);
}
/*****************************************************************************/
/**
*
* Execute Read and clear
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddr is address of a block.
* @param RegAddr is register offset value.
* @param Mask contains bit mask value.
*
* @return
* - None
*
******************************************************************************/
static inline void XRFdc_ClrReg(XRFdc *InstancePtr, u32 BaseAddr, u32 RegAddr, u16 Mask)
{
u16 ReadReg;
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, RegAddr);
ReadReg &= ~Mask;
XRFdc_WriteReg16(InstancePtr, BaseAddr, RegAddr, ReadReg);
}
/*****************************************************************************/
/**
*
* Execute Read and mask with the value
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddr is address of a block.
* @param RegAddr is register offset value.
* @param Mask contains bit mask value.
*
* @return
* - None
*
******************************************************************************/
static inline u16 XRFdc_RDReg(XRFdc *InstancePtr, u32 BaseAddr, u32 RegAddr, u16 Mask)
{
u16 ReadReg;
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, RegAddr);
ReadReg &= Mask;
return ReadReg;
}
/*****************************************************************************/
/**
*
* Get ADC type is High Speed or Medium Speed.
*
* @param InstancePtr is a pointer to the XRfdc instance.
*
* @return
* - Return 1 if ADC type is 4GSPS, otherwise 0.
*
******************************************************************************/
static inline u32 XRFdc_IsHighSpeedADC(XRFdc *InstancePtr, int Tile)
{
if (InstancePtr->RFdc_Config.ADCTile_Config[Tile].NumSlices == 0) {
return InstancePtr->ADC4GSPS;
} else {
return (InstancePtr->RFdc_Config.ADCTile_Config[Tile].NumSlices == XRFDC_NUM_SLICES_HSADC);
}
}
/*****************************************************************************/
/**
*
* Checks whether DAC block is available or not.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - Return 1 if DAC block is available, otherwise 0.
*
******************************************************************************/
static inline u32 XRFdc_IsDACBlockEnabled(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id)
{
u32 IsBlockAvail;
u32 BlockShift;
u32 BlockEnableReg;
BlockShift = Block_Id + (XRFDC_PATH_ENABLED_TILE_SHIFT * Tile_Id);
BlockEnableReg = XRFdc_ReadReg(InstancePtr, XRFDC_IP_BASE, XRFDC_DAC_PATHS_ENABLED_OFFSET);
BlockEnableReg &= (XRFDC_ENABLED << BlockShift);
IsBlockAvail = BlockEnableReg >> BlockShift;
return IsBlockAvail;
}
/*****************************************************************************/
/**
*
* Checks whether ADC block is available or not.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3 in DAC/ADC-2GSPS and 0-1 in ADC-4GSPS.
*
* @return
* - Return 1 if ADC block is available, otherwise 0.
*
******************************************************************************/
static inline u32 XRFdc_IsADCBlockEnabled(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id)
{
u32 IsBlockAvail;
u32 BlockShift;
u32 BlockEnableReg;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == XRFDC_ENABLED) {
if ((Block_Id == 2U) || (Block_Id == 3U)) {
IsBlockAvail = 0;
goto RETURN_PATH;
}
if (Block_Id == 1U) {
Block_Id = 2U;
}
}
BlockShift = Block_Id + (XRFDC_PATH_ENABLED_TILE_SHIFT * Tile_Id);
BlockEnableReg = XRFdc_ReadReg(InstancePtr, XRFDC_IP_BASE, XRFDC_ADC_PATHS_ENABLED_OFFSET);
BlockEnableReg &= (XRFDC_ENABLED << BlockShift);
IsBlockAvail = BlockEnableReg >> BlockShift;
RETURN_PATH:
return IsBlockAvail;
}
/*****************************************************************************/
/**
*
* Checks whether DAC Digital path is enabled or not.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - Return 1 if DAC digital path is enabled, otherwise 0.
*
******************************************************************************/
static inline u32 XRFdc_IsDACDigitalPathEnabled(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id)
{
u32 IsDigitalPathAvail;
u32 DigitalPathShift;
u32 DigitalPathEnableReg;
DigitalPathShift = Block_Id + XRFDC_DIGITAL_PATH_ENABLED_SHIFT + (XRFDC_PATH_ENABLED_TILE_SHIFT * Tile_Id);
DigitalPathEnableReg = XRFdc_ReadReg(InstancePtr, XRFDC_IP_BASE, XRFDC_DAC_PATHS_ENABLED_OFFSET);
DigitalPathEnableReg &= (XRFDC_ENABLED << DigitalPathShift);
IsDigitalPathAvail = DigitalPathEnableReg >> DigitalPathShift;
return IsDigitalPathAvail;
}
/*****************************************************************************/
/**
*
* Checks whether ADC digital path is enabled or not.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3 in DAC/ADC-2GSPS and 0-1 in ADC-4GSPS.
*
* @return
* - Return 1 if ADC digital path is enabled, otherwise 0.
*
******************************************************************************/
static inline u32 XRFdc_IsADCDigitalPathEnabled(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id)
{
u32 IsDigitalPathAvail;
u32 DigitalPathShift;
u32 DigitalPathEnableReg;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == XRFDC_ENABLED) {
if ((Block_Id == 2U) || (Block_Id == 3U)) {
IsDigitalPathAvail = 0;
goto RETURN_PATH;
}
if (Block_Id == 1U) {
Block_Id = 2U;
}
}
DigitalPathShift = Block_Id + XRFDC_DIGITAL_PATH_ENABLED_SHIFT + (XRFDC_PATH_ENABLED_TILE_SHIFT * Tile_Id);
DigitalPathEnableReg = XRFdc_ReadReg(InstancePtr, XRFDC_IP_BASE, XRFDC_ADC_PATHS_ENABLED_OFFSET);
DigitalPathEnableReg &= (XRFDC_ENABLED << DigitalPathShift);
IsDigitalPathAvail = DigitalPathEnableReg >> DigitalPathShift;
RETURN_PATH:
return IsDigitalPathAvail;
}
/*****************************************************************************/
/**
*
* Checks whether ADC/DAC Digital path is enabled or not.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - XRFDC_SUCCESS if Digital path is enabled.
* - XRFDC_FAILURE if Digital path is not enabled.
*
******************************************************************************/
static inline u32 XRFdc_CheckDigitalPathEnabled(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
{
u32 IsBlockAvail;
u32 Status;
if ((Type != XRFDC_ADC_TILE) && (Type != XRFDC_DAC_TILE)) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((Tile_Id > XRFDC_TILE_ID_MAX) || (Block_Id > XRFDC_BLOCK_ID_MAX)) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (Type == XRFDC_ADC_TILE) {
IsBlockAvail = XRFdc_IsADCDigitalPathEnabled(InstancePtr, Tile_Id, Block_Id);
} else {
IsBlockAvail = XRFdc_IsDACDigitalPathEnabled(InstancePtr, Tile_Id, Block_Id);
}
if (IsBlockAvail == 0U) {
Status = XRFDC_FAILURE;
} else {
Status = XRFDC_SUCCESS;
}
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Get IP BaseAddress.
*
* @param InstancePtr is a pointer to the XRfdc instance.
*
* @return
* - Return IP BaseAddress.
*
******************************************************************************/
static inline u32 XRFdc_Get_IPBaseAddr(XRFdc *InstancePtr)
{
return (u32)InstancePtr->BaseAddr;
}
/*****************************************************************************/
/**
*
* Get Tile BaseAddress
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
*
* @return
* - Return Tile BaseAddress.
*
******************************************************************************/
static inline u32 XRFdc_Get_TileBaseAddr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id)
{
u32 BaseAddr;
if (Type == XRFDC_ADC_TILE) {
BaseAddr = InstancePtr->BaseAddr + XRFDC_ADC_TILE_DRP_ADDR(Tile_Id);
} else {
BaseAddr = InstancePtr->BaseAddr + XRFDC_DAC_TILE_DRP_ADDR(Tile_Id);
}
return BaseAddr;
}
/*****************************************************************************/
/**
*
* Get Block BaseAddress
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3 in DAC/ADC-2GSPS and 0-1 in ADC-4GSPS.
*
* @return
* - Return Block BaseAddress.
*
******************************************************************************/
static inline u32 XRFdc_Get_BlockBaseAddr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
{
u32 BaseAddr;
if (Type == XRFDC_ADC_TILE) {
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == XRFDC_ENABLED) {
if (Block_Id == 1U) {
Block_Id = 2U;
}
}
BaseAddr = InstancePtr->BaseAddr + XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Block_Id);
} else {
BaseAddr = InstancePtr->BaseAddr + XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) + XRFDC_BLOCK_ADDR_OFFSET(Block_Id);
}
return BaseAddr;
}
/*****************************************************************************/
/**
*
* Get Number of DAC Blocks enabled.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
*
* @return
* - Return number of DAC blocks enabled.
*
******************************************************************************/
static inline u32 XRFdc_GetNoOfDACBlock(XRFdc *InstancePtr, u32 Tile_Id)
{
return InstancePtr->DAC_Tile[Tile_Id].NumOfDACBlocks;
}
/*****************************************************************************/
/**
*
* Get Number of ADC Blocks enabled.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
*
* @return
* - Return number of ADC blocks enabled.
*
******************************************************************************/
static inline u32 XRFdc_GetNoOfADCBlocks(XRFdc *InstancePtr, u32 Tile_Id)
{
return InstancePtr->ADC_Tile[Tile_Id].NumOfADCBlocks;
}
/*****************************************************************************/
/**
*
* Get Mixer Input Data Type for ADC/DAC block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - Return MixerInputDataType of ADC/DAC block.
*
******************************************************************************/
static inline u32 XRFdc_GetDataType(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
{
u32 MixerInputDataType;
if (Type == XRFDC_ADC_TILE) {
MixerInputDataType = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id]
.ADCBlock_Digital_Config[Block_Id]
.MixerInputDataType;
} else {
MixerInputDataType = InstancePtr->RFdc_Config.DACTile_Config[Tile_Id]
.DACBlock_Digital_Config[Block_Id]
.MixerInputDataType;
}
return MixerInputDataType;
}
/*****************************************************************************/
/**
*
* Get Data Width for ADC/DAC block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - Return DataWidth of ADC/DAC block.
*
******************************************************************************/
static inline u32 XRFdc_GetDataWidth(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
{
u32 DataWidth;
if (Type == XRFDC_ADC_TILE) {
DataWidth =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].ADCBlock_Digital_Config[Block_Id].DataWidth;
} else {
DataWidth =
InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].DACBlock_Digital_Config[Block_Id].DataWidth;
}
return DataWidth;
}
/*****************************************************************************/
/**
*
* Get Inversesync filter for DAC block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - Return Inversesync filter for DAC block
*
******************************************************************************/
static inline u32 XRFdc_GetInverseSincFilter(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id)
{
return InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].DACBlock_Analog_Config[Block_Id].InvSyncEnable;
}
/*****************************************************************************/
/**
*
* Get Mixed mode for DAC block.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - Return mixed mode for DAC block
*
******************************************************************************/
static inline u32 XRFdc_GetMixedMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id)
{
return InstancePtr->DAC_Tile[Tile_Id].DACBlock_Analog_Datapath[Block_Id].MixedMode;
}
/*****************************************************************************/
/**
*
* Get Master Tile for ADC/DAC tiles.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
*
* @return
* - Return Master Tile for ADC/DAC tiles
*
******************************************************************************/
static inline u32 XRFdc_GetMasterTile(XRFdc *InstancePtr, u32 Type)
{
u32 MasterTile;
if (Type == XRFDC_ADC_TILE) {
MasterTile = InstancePtr->RFdc_Config.MasterADCTile;
} else {
MasterTile = InstancePtr->RFdc_Config.MasterDACTile;
}
return MasterTile;
}
/*****************************************************************************/
/**
*
* Get Sysref source for ADC/DAC tile.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
*
* @return
* - Return Sysref source for ADC/DAC tile
*
******************************************************************************/
static inline u32 XRFdc_GetSysRefSource(XRFdc *InstancePtr, u32 Type)
{
u32 SysRefSource;
if (Type == XRFDC_ADC_TILE) {
SysRefSource = InstancePtr->RFdc_Config.ADCSysRefSource;
} else {
SysRefSource = InstancePtr->RFdc_Config.DACSysRefSource;
}
return SysRefSource;
}
/*****************************************************************************/
/**
*
* Get Fabric Clock frequency.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
*
* @return
* - Return Fabric Clock frequency for ADC/DAC tile
*
******************************************************************************/
static inline double XRFdc_GetFabClkFreq(XRFdc *InstancePtr, u32 Type, u32 Tile_Id)
{
double FabClkFreq;
if (Type == XRFDC_ADC_TILE) {
FabClkFreq = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].FabClkFreq;
} else {
FabClkFreq = InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].FabClkFreq;
}
return FabClkFreq;
}
/*****************************************************************************/
/**
*
* Get whether FIFO is enabled or not.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - Return 1 if FIFO is enabled, otherwise 0.
*
******************************************************************************/
static inline u32 XRFdc_IsFifoEnabled(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
{
u32 FifoEnable;
if (Type == XRFDC_ADC_TILE) {
FifoEnable =
InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].ADCBlock_Digital_Config[Block_Id].FifoEnable;
} else {
FifoEnable =
InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].DACBlock_Digital_Config[Block_Id].FifoEnable;
}
return FifoEnable;
}
/*****************************************************************************/
/**
*
* Get Data Converter connected for digital data path I
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is Digital Data Path number.
*
* @return
* - Return Data converter Id.
*
******************************************************************************/
static inline int XRFdc_GetConnectedIData(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
{
int ConnectedIData;
if (Type == XRFDC_ADC_TILE) {
ConnectedIData = InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].ConnectedIData;
} else {
ConnectedIData = InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].ConnectedIData;
}
return ConnectedIData;
}
/*****************************************************************************/
/**
*
* Get Data Converter connected for digital data path Q
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is Digital Data Path number.
*
* @return
* - Return Data converter Id.
*
******************************************************************************/
static inline int XRFdc_GetConnectedQData(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
{
int ConnectedQData;
if (Type == XRFDC_ADC_TILE) {
ConnectedQData = InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].ConnectedQData;
} else {
ConnectedQData = InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].ConnectedQData;
}
return ConnectedQData;
}
/*****************************************************************************/
/**
*
* Set Data Converter connected for digital data path I and Q
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is Digital Data Path number.
* @param ConnectedIData is Converter Id to which DigitalPathI connected.
* @param ConnectedQData is Converter Id to which DigitalPathQ connected.
*
* @return
* - None.
*
******************************************************************************/
static inline void XRFdc_SetConnectedIQData(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, int ConnectedIData,
int ConnectedQData)
{
if (Type == XRFDC_ADC_TILE) {
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].ConnectedIData = ConnectedIData;
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].ConnectedQData = ConnectedQData;
} else {
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].ConnectedIData = ConnectedIData;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].ConnectedQData = ConnectedQData;
}
}
/*****************************************************************************/
/**
*
* Get Multiband Config data
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
*
* @return
* - Return Multiband Configuration.
*
******************************************************************************/
static inline u32 XRFdc_GetMultibandConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id)
{
u32 MultibandConfig;
if (Type == XRFDC_ADC_TILE) {
MultibandConfig = InstancePtr->ADC_Tile[Tile_Id].MultibandConfig;
} else {
MultibandConfig = InstancePtr->DAC_Tile[Tile_Id].MultibandConfig;
}
return MultibandConfig;
}
/*****************************************************************************/
/**
*
* Checks whether ADC/DAC block is enabled or not.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC.
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
*
* @return
* - XRFDC_SUCCESS if block enabled.
* - XRFDC_FAILURE if block not enabled.
*
******************************************************************************/
static inline u32 XRFdc_CheckBlockEnabled(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
{
u32 IsBlockAvail;
u32 Status;
if ((Type != XRFDC_ADC_TILE) && (Type != XRFDC_DAC_TILE)) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((Tile_Id > XRFDC_TILE_ID_MAX) || (Block_Id > XRFDC_BLOCK_ID_MAX)) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (Type == XRFDC_ADC_TILE) {
IsBlockAvail = XRFdc_IsADCBlockEnabled(InstancePtr, Tile_Id, Block_Id);
} else {
IsBlockAvail = XRFdc_IsDACBlockEnabled(InstancePtr, Tile_Id, Block_Id);
}
if (IsBlockAvail == 0U) {
Status = XRFDC_FAILURE;
} else {
Status = XRFDC_SUCCESS;
}
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Checks whether ADC/DAC tile is enabled or not.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC.
* @param Tile_Id Valid values are 0-3.
*
* @return
* - XRFDC_SUCCESS if tile enabled.
* - XRFDC_FAILURE if tile not enabled.
*
******************************************************************************/
static inline u32 XRFdc_CheckTileEnabled(XRFdc *InstancePtr, u32 Type, u32 Tile_Id)
{
u32 Status;
u32 TileMask;
u32 TileEnableReg;
if ((Type != XRFDC_ADC_TILE) && (Type != XRFDC_DAC_TILE)) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (Tile_Id > XRFDC_TILE_ID_MAX) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
TileEnableReg = XRFdc_ReadReg(InstancePtr, XRFDC_IP_BASE, XRFDC_TILES_ENABLED_OFFSET);
TileMask = XRFDC_ENABLED << Tile_Id;
if (Type == XRFDC_DAC_TILE) {
TileMask <<= XRFDC_DAC_TILES_ENABLED_SHIFT;
}
if ((TileEnableReg & TileMask) == 0U) {
Status = XRFDC_FAILURE;
} else {
Status = XRFDC_SUCCESS;
}
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Gets ADC/DAC tile maximum sampling rate.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC.
* @param Tile_Id Valid values are 0-3.
* @param MaxSampleRatePtr pointer for maximum sample rate.
*
* @return
* - XRFDC_SUCCESS if found sampling rate.
* - XRFDC_FAILURE if could not find sampling rate.
*
******************************************************************************/
static inline u32 XRFdc_GetMaxSampleRate(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, double *MaxSampleRatePtr)
{
u32 Status;
if ((Type != XRFDC_ADC_TILE) && (Type != XRFDC_DAC_TILE)) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (Tile_Id > XRFDC_TILE_ID_MAX) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (Type == XRFDC_ADC_TILE) {
*MaxSampleRatePtr = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].MaxSampleRate * 1000;
if (*MaxSampleRatePtr == 0) {
*MaxSampleRatePtr = XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) ? XRFDC_ADC_4G_SAMPLING_MAX :
XRFDC_ADC_2G_SAMPLING_MAX;
}
} else {
*MaxSampleRatePtr = InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].MaxSampleRate * 1000;
if (*MaxSampleRatePtr == 0) {
*MaxSampleRatePtr = XRFDC_DAC_SAMPLING_MAX;
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* Gets ADC/DAC tile minimum sampling rate.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC.
* @param Tile_Id Valid values are 0-3.
* @param MinSampleRatePtr pointer for minimum sample rate.
*
* @return
* - XRFDC_SUCCESS if found sampling rate.
* - XRFDC_FAILURE if could not find sampling rate.
*
******************************************************************************/
static inline u32 XRFdc_GetMinSampleRate(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, double *MinSampleRatePtr)
{
u32 Status;
if ((Type != XRFDC_ADC_TILE) && (Type != XRFDC_DAC_TILE)) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (Tile_Id > XRFDC_TILE_ID_MAX) {
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (Type == XRFDC_ADC_TILE) {
*MinSampleRatePtr = XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) ? XRFDC_ADC_4G_SAMPLING_MIN :
XRFDC_ADC_2G_SAMPLING_MIN;
} else {
*MinSampleRatePtr = XRFDC_DAC_SAMPLING_MIN;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
*
* This API is used to get the driver version.
*
* @param None
*
* @return
* Driver version number
*
* @note None.
*
******************************************************************************/
static inline double XRFdc_GetDriverVersion(void)
{
return 8.0;
}
/************************** Function Prototypes ******************************/
XRFdc_Config *XRFdc_LookupConfig(u16 DeviceId);
u32 XRFdc_RegisterMetal(XRFdc *InstancePtr, u16 DeviceId, struct metal_device **DevicePtr);
u32 XRFdc_CfgInitialize(XRFdc *InstancePtr, XRFdc_Config *ConfigPtr);
u32 XRFdc_StartUp(XRFdc *InstancePtr, u32 Type, int Tile_Id);
u32 XRFdc_Shutdown(XRFdc *InstancePtr, u32 Type, int Tile_Id);
u32 XRFdc_Reset(XRFdc *InstancePtr, u32 Type, int Tile_Id);
u32 XRFdc_GetIPStatus(XRFdc *InstancePtr, XRFdc_IPStatus *IPStatusPtr);
u32 XRFdc_GetBlockStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_BlockStatus *BlockStatusPtr);
u32 XRFdc_SetMixerSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
XRFdc_Mixer_Settings *MixerSettingsPtr);
u32 XRFdc_GetMixerSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
XRFdc_Mixer_Settings *MixerSettingsPtr);
u32 XRFdc_SetQMCSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr);
u32 XRFdc_GetQMCSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr);
u32 XRFdc_GetCoarseDelaySettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr);
u32 XRFdc_SetCoarseDelaySettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr);
u32 XRFdc_GetInterpolationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *InterpolationFactorPtr);
u32 XRFdc_GetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecimationFactorPtr);
u32 XRFdc_GetFabWrVldWords(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricDataRatePtr);
u32 XRFdc_GetFabRdVldWords(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricDataRatePtr);
u32 XRFdc_SetFabRdVldWords(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricRdVldWords);
u32 XRFdc_SetFabWrVldWords(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricWrVldWords);
u32 XRFdc_GetThresholdSettings(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
XRFdc_Threshold_Settings *ThresholdSettingsPtr);
u32 XRFdc_SetThresholdSettings(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
XRFdc_Threshold_Settings *ThresholdSettingsPtr);
u32 XRFdc_SetDecoderMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecoderMode);
u32 XRFdc_UpdateEvent(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 Event);
u32 XRFdc_GetDecoderMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecoderModePtr);
u32 XRFdc_ResetNCOPhase(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id);
void XRFdc_DumpRegs(XRFdc *InstancePtr, u32 Type, int Tile_Id);
u32 XRFdc_MultiBand(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 DigitalDataPathMask, u32 MixerInOutDataType,
u32 DataConverterMask);
u32 XRFdc_IntrHandler(u32 Vector, void *XRFdcPtr);
u32 XRFdc_IntrClr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask);
u32 XRFdc_GetIntrStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *IntrStsPtr);
u32 XRFdc_IntrDisable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask);
u32 XRFdc_IntrEnable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask);
u32 XRFdc_GetEnabledInterrupts(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *IntrMask);
u32 XRFdc_SetThresholdClrMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 ThresholdToUpdate, u32 ClrMode);
u32 XRFdc_ThresholdStickyClear(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 ThresholdToUpdate);
void XRFdc_SetStatusHandler(XRFdc *InstancePtr, void *CallBackRef, XRFdc_StatusHandler FunctionPtr);
u32 XRFdc_SetupFIFO(XRFdc *InstancePtr, u32 Type, int Tile_Id, u8 Enable);
u32 XRFdc_GetFIFOStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 *EnablePtr);
u32 XRFdc_SetNyquistZone(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 NyquistZone);
u32 XRFdc_GetNyquistZone(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *NyquistZonePtr);
u32 XRFdc_GetOutputCurr(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *OutputCurrPtr);
u32 XRFdc_SetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecimationFactor);
u32 XRFdc_SetInterpolationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 InterpolationFactor);
u32 XRFdc_SetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 FabClkDiv);
u32 XRFdc_SetCalibrationMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u8 CalibrationMode);
u32 XRFdc_GetCalibrationMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u8 *CalibrationModePtr);
u32 XRFdc_GetClockSource(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *ClockSourcePtr);
u32 XRFdc_GetPLLLockStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *LockStatusPtr);
u32 XRFdc_GetPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, XRFdc_PLL_Settings *PLLSettings);
u32 XRFdc_DynamicPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 Source, double RefClkFreq,
double SamplingRate);
u32 XRFdc_SetInvSincFIR(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 Mode);
u32 XRFdc_GetInvSincFIR(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 *ModePtr);
u32 XRFdc_GetLinkCoupling(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr);
u32 XRFdc_GetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 *FabClkDivPtr);
u32 XRFdc_SetDither(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode);
u32 XRFdc_GetDither(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr);
u32 XRFdc_SetClkDistribution(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr);
u32 XRFdc_GetClkDistribution(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr);
u32 XRFdc_SetDataPathMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode);
u32 XRFdc_GetDataPathMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr);
u32 XRFdc_SetIMRPassMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode);
u32 XRFdc_GetIMRPassMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr);
u32 XRFdc_SetSignalDetector(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Signal_Detector_Settings *SettingsPtr);
u32 XRFdc_GetSignalDetector(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Signal_Detector_Settings *SettingsPtr);
u32 XRFdc_DisableCoefficientsOverride(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock);
u32 XRFdc_SetCalCoefficients(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock,
XRFdc_Calibration_Coefficients *CoeffPtr);
u32 XRFdc_GetCalCoefficients(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock,
XRFdc_Calibration_Coefficients *CoeffPtr);
u32 XRFdc_SetCalFreeze(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Cal_Freeze_Settings *CalFreezePtr);
u32 XRFdc_GetCalFreeze(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Cal_Freeze_Settings *CalFreezePtr);
u32 XRFdc_SetDACVOP(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 uACurrent);
u32 XRFdc_SetDACCompMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Enable);
u32 XRFdc_GetDACCompMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *EnabledPtr);
u32 XRFdc_SetDSA(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_DSA_Settings *SettingsPtr);
u32 XRFdc_GetDSA(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_DSA_Settings *SettingsPtr);
#ifndef __BAREMETAL__
s32 XRFdc_GetDeviceNameByDeviceId(char *DevNamePtr, u16 DevId);
#endif
#ifdef __cplusplus
}
#endif
#endif /* RFDC_H_ */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_qspi.c
/*
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
#ifdef ENABLE_POS_QSPI
#include "pm_qspi.h"
#include "pm_common.h"
#include "xpfw_config.h"
#include "xparameters.h"
#ifdef XPAR_PSU_QSPI_0_DEVICE_ID
#include <xqspipsu.h>
#else
#error "ENABLE_POS_QSPI is defined but qspi device is not available"
#endif
#define IOU_SCLR_MIO_PIN_0 ( ( IOU_SLCR_BASE ) + 0X00000000U )
#define IOU_SCLR_MIO_PIN_1 ( ( IOU_SLCR_BASE ) + 0X00000004U )
#define IOU_SCLR_MIO_PIN_2 ( ( IOU_SLCR_BASE ) + 0X00000008U )
#define IOU_SCLR_MIO_PIN_3 ( ( IOU_SLCR_BASE ) + 0X0000000CU )
#define IOU_SCLR_MIO_PIN_4 ( ( IOU_SLCR_BASE ) + 0X00000010U )
#define IOU_SCLR_MIO_PIN_5 ( ( IOU_SLCR_BASE ) + 0X00000014U )
#define IOU_SCLR_MIO_PIN_6 ( ( IOU_SLCR_BASE ) + 0X00000018U )
#define IOU_SCLR_MIO_PIN_7 ( ( IOU_SLCR_BASE ) + 0X0000001CU )
#define IOU_SCLR_MIO_PIN_8 ( ( IOU_SLCR_BASE ) + 0X00000020U )
#define IOU_SCLR_MIO_PIN_9 ( ( IOU_SLCR_BASE ) + 0X00000024U )
#define IOU_SCLR_MIO_PIN_10 ( ( IOU_SLCR_BASE ) + 0X00000028U )
#define IOU_SCLR_MIO_PIN_11 ( ( IOU_SLCR_BASE ) + 0X0000002CU )
#define IOU_SCLR_MIO_PIN_12 ( ( IOU_SLCR_BASE ) + 0X00000030U )
#define IOU_SCLR_MIO_MST_TRI0 ( ( IOU_SLCR_BASE ) + 0X00000204U )
#define IOU_SCLR_TAPDLY_BYPASS ( ( IOU_SLCR_BASE ) + 0X00000390U )
/*
* The following constants define the commands which may be sent to the Flash
* device.
*/
#define WRITE_STATUS_CMD 0x01U
#define WRITE_CMD 0x02U
#define READ_CMD 0x03U
#define WRITE_DISABLE_CMD 0x04U
#define READ_STATUS_CMD 0x05U
#define WRITE_ENABLE_CMD 0x06U
#define FAST_READ_CMD 0x0BU
#define DUAL_READ_CMD 0x3BU
#define QUAD_READ_CMD 0x6BU
#define BULK_ERASE_CMD 0xC7U
#define SEC_ERASE_CMD 0xD8U
#define READ_ID 0x9FU
#define READ_CONFIG_CMD 0x35U
#define WRITE_CONFIG_CMD 0x01U
#define WRITE_CMD_4B 0x12U
#define READ_CMD_4B 0x13U
#define FAST_READ_CMD_4B 0x0CU
#define DUAL_READ_CMD_4B 0x3CU
#define QUAD_READ_CMD_4B 0x6CU
#define SEC_ERASE_CMD_4B 0xDCU
#define BANK_REG_RD 0x16U
#define BANK_REG_WR 0x17U
/* Bank register is called Extended Address Register in Micron */
#define EXTADD_REG_RD 0xC8U
#define EXTADD_REG_WR 0xC5U
#define DIE_ERASE_CMD 0xC4U
#define READ_FLAG_STATUS_CMD 0x70U
/*
* The following constants define the offsets within a FlashBuffer data
* type for each kind of data. Note that the read data offset is not the
* same as the write data because the QSPIPSU driver is designed to allow full
* duplex transfers such that the number of bytes received is the number
* sent and received.
*/
#define COMMAND_OFFSET 0 /* Flash instruction */
#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
#define ADDRESS_4_OFFSET 4 /* LSB byte of address to read or write when
4 byte address */
#define DUMMY_CLOCKS 8U /* Number of dummy bytes for fast, dual and
quad reads */
/*
* Max page size to initialize write and read buffer
*/
#define MAX_PAGE_SIZE 512U
#define SECT_SIZE 0x10000U
#define SECT_MASK 0xFFFF0000U
#define FLASH_SIZE 0x4000000U
/*
* Flash address to which data is to be written.
*/
#define TEST_ADDRESS 0x000000U
#define WRITE_ADDR TEST_ADDRESS
#define READ_ADDR TEST_ADDRESS
static u8 CmdBfr[8];
static u32 QspiMioPinArr[] = {
IOU_SCLR_MIO_PIN_0,
IOU_SCLR_MIO_PIN_1,
IOU_SCLR_MIO_PIN_2,
IOU_SCLR_MIO_PIN_3,
IOU_SCLR_MIO_PIN_4,
IOU_SCLR_MIO_PIN_5,
IOU_SCLR_MIO_PIN_6,
IOU_SCLR_MIO_PIN_7,
IOU_SCLR_MIO_PIN_8,
IOU_SCLR_MIO_PIN_9,
IOU_SCLR_MIO_PIN_10,
IOU_SCLR_MIO_PIN_11,
IOU_SCLR_MIO_PIN_12,
};
/*
* The instances to support the device drivers are global such that they
* are initialized to zero each time the program runs. They could be local
* but should at least be static so they are zeroed.
*/
static XQspiPsu QspiPsuInstance;
static XQspiPsu_Msg FlashMsg[5];
s32 FlashWrite(XQspiPsu *QspiPsuPtr, u32 Address, u32 ByteCount, u8 Command,
u8 *WriteBfrPtr);
s32 FlashRead(XQspiPsu *QspiPsuPtr, u32 Address, u32 ByteCount, u8 Command,
u8 *WriteBfrPtr, u8 *ReadBfrPtr);
s32 FlashErase(XQspiPsu *QspiPsuPtr, u32 Address, u32 ByteCount,
u8 *WriteBfrPtr);
u32 GetRealAddr(XQspiPsu *QspiPsuPtr, u32 Address);
/*****************************************************************************/
/**
* This is wrapper function used to write data to the Flash. If number of bytes
* to be transmitted exceeds page size spilt transfer into smaller packets sized
* up to the page size.
*
* @param Pointer to the write buffer (which is to be transmitted)
* @param ByteCount contains the number of bytes to write.
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
s32 PmQspiWrite(u8 *WriteBufrPtr, u32 ByteCount)
{
s32 Status;
u32 length = ByteCount;
u32 page = 0U;
Status = FlashErase(&QspiPsuInstance, WRITE_ADDR, ByteCount, CmdBfr);
if(Status != XST_FAILURE) {
while (length > 0U) {
if (length < MAX_PAGE_SIZE) {
Status = FlashWrite(&QspiPsuInstance,
(page * MAX_PAGE_SIZE) + WRITE_ADDR,
length,
WRITE_CMD_4B,
WriteBufrPtr + (page * MAX_PAGE_SIZE));
length = 0U;
} else {
Status = FlashWrite(&QspiPsuInstance,
(page * MAX_PAGE_SIZE) + WRITE_ADDR,
MAX_PAGE_SIZE,
WRITE_CMD_4B,
WriteBufrPtr + (page * MAX_PAGE_SIZE));
length -= MAX_PAGE_SIZE;
}
page++;
}
}
return Status;
}
/*****************************************************************************/
/**
*
* This is wrapper function used to read data from the Flash. Use READ_ADDR as
* as address to read from in the Flash. Use quad 4b read command.
*
* @param ByteCount contains the number of bytes to read.
* @param Pointer to the read buffer to which valid received data should be
* written
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
s32 PmQspiRead(u32 ByteCount, u8 *ReadBfrPtr)
{
s32 Status;
Status = FlashRead(&QspiPsuInstance, READ_ADDR, ByteCount,
QUAD_READ_CMD_4B, CmdBfr, ReadBfrPtr);
return Status;
}
/*****************************************************************************/
/**
*
* This is function used to initialize QSPI Flash driver for communication with
* serial Flash memory device.
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
s32 PmQspiInit(void)
{
s32 Status;
XQspiPsu_Config *QspiPsuConfig;
/* Initialize QSPIPSU driver so that it's ready to use */
QspiPsuConfig = XQspiPsu_LookupConfig(QSPIPSU_DEVICE_ID);
if (NULL == QspiPsuConfig) {
return XST_FAILURE;
}
Status = XQspiPsu_CfgInitialize(&QspiPsuInstance, QspiPsuConfig,
QspiPsuConfig->BaseAddress);
if (XST_SUCCESS != Status) {
return XST_FAILURE;
}
/* Set manual start option */
XQspiPsu_SetOptions(&QspiPsuInstance, XQSPIPSU_MANUAL_START_OPTION);
/* Set prescaler for QSPIPSU clock */
XQspiPsu_SetClkPrescaler(&QspiPsuInstance, XQSPIPSU_CLK_PRESCALE_8);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function writes to the serial Flash connected to the QSPIPSU interface.
* All the data put into the buffer must be in the same page of the device with
* page boundaries being on 256 byte boundaries per memory chip.
*
* @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use.
* @param Address contains the address to write data to in the Flash.
* @param ByteCount contains the number of bytes to write.
* @param Command is the command used to write data to the flash. QSPIPSU
* device supports only Page Program command to write data to the
* flash.
* @param Pointer to the write buffer (which is to be transmitted)
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
s32 FlashWrite(XQspiPsu *QspiPsuPtr, u32 Address, u32 ByteCount, u8 Command,
u8 *WriteBfrPtr)
{
u8 WriteEnableCmd;
u8 ReadStatusCmd;
u8 FlashStatus[2] = {0U};
u8 WriteCmd[5];
u32 RealAddr;
s32 Status;
WriteEnableCmd = WRITE_ENABLE_CMD;
/*
* Translate address based on type of connection
* If stacked assert the slave select based on address
*/
RealAddr = GetRealAddr(QspiPsuPtr, Address);
/*
* Send the write enable command to the Flash so that it can be
* written to, this needs to be sent as a separate transfer before
* the write
*/
FlashMsg[0].TxBfrPtr = &WriteEnableCmd;
FlashMsg[0].RxBfrPtr = NULL;
FlashMsg[0].ByteCount = 1;
FlashMsg[0].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[0].Flags = XQSPIPSU_MSG_FLAG_TX;
Status = XQspiPsu_PolledTransfer(QspiPsuPtr, FlashMsg, 1U);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
WriteCmd[COMMAND_OFFSET] = Command;
WriteCmd[ADDRESS_1_OFFSET] = (u8)((RealAddr & 0xFF000000U) >> 24U);
WriteCmd[ADDRESS_2_OFFSET] = (u8)((RealAddr & 0xFF0000U) >> 16U);
WriteCmd[ADDRESS_3_OFFSET] = (u8)((RealAddr & 0xFF00U) >> 8U);
WriteCmd[ADDRESS_4_OFFSET] = (u8)(RealAddr & 0xFFU);
FlashMsg[0].TxBfrPtr = WriteCmd;
FlashMsg[0].RxBfrPtr = NULL;
FlashMsg[0].ByteCount = 5;
FlashMsg[0].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[0].Flags = XQSPIPSU_MSG_FLAG_TX;
FlashMsg[1].TxBfrPtr = WriteBfrPtr;
FlashMsg[1].RxBfrPtr = NULL;
FlashMsg[1].ByteCount = ByteCount;
FlashMsg[1].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[1].Flags = XQSPIPSU_MSG_FLAG_TX;
if (QspiPsuPtr->Config.ConnectionMode ==
XQSPIPSU_CONNECTION_MODE_PARALLEL) {
FlashMsg[1].Flags |= XQSPIPSU_MSG_FLAG_STRIPE;
}
Status = XQspiPsu_PolledTransfer(QspiPsuPtr, FlashMsg, 2U);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait for the write command to the Flash to be completed, it takes
* some time for the data to be written
*/
while (1) {
ReadStatusCmd = READ_FLAG_STATUS_CMD;
FlashMsg[0].TxBfrPtr = &ReadStatusCmd;
FlashMsg[0].RxBfrPtr = NULL;
FlashMsg[0].ByteCount = 1U;
FlashMsg[0].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[0].Flags = XQSPIPSU_MSG_FLAG_TX;
FlashMsg[1].TxBfrPtr = NULL;
FlashMsg[1].RxBfrPtr = FlashStatus;
FlashMsg[1].ByteCount = 2U;
FlashMsg[1].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[1].Flags = XQSPIPSU_MSG_FLAG_RX;
if (QspiPsuPtr->Config.ConnectionMode ==
XQSPIPSU_CONNECTION_MODE_PARALLEL) {
FlashMsg[1].Flags |= XQSPIPSU_MSG_FLAG_STRIPE;
}
Status = XQspiPsu_PolledTransfer(QspiPsuPtr, FlashMsg, 2U);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
if (QspiPsuPtr->Config.ConnectionMode ==
XQSPIPSU_CONNECTION_MODE_PARALLEL) {
FlashStatus[1] &= FlashStatus[0];
}
if ((FlashStatus[1] & 0x80U) == 0x80U) {
break;
}
}
return 0;
}
/*****************************************************************************/
/**
*
* This function performs read. DMA is the default setting.
*
* @param QspiPtr is a pointer to the QSPIPSU driver component to use.
* @param Address contains the address in the Flash to read data from.
* @param ByteCount contains the number of bytes to read.
* @param Command is the command used to read data from the flash. Supports
* normal, fast, dual and quad read commands.
* @param Pointer to the write buffer which contains data to be transmitted
* @param Pointer to the read buffer to which valid received data should be
* written
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
s32 FlashRead(XQspiPsu *QspiPsuPtr, u32 Address, u32 ByteCount, u8 Command,
u8 *WriteBfrPtr, u8 *ReadBfrPtr)
{
u32 RealAddr;
s32 Status;
/*
* Translate address based on type of connection
* If stacked assert the slave select based on address
*/
RealAddr = GetRealAddr(QspiPsuPtr, Address);
WriteBfrPtr[COMMAND_OFFSET] = Command;
WriteBfrPtr[ADDRESS_1_OFFSET] = (u8)((RealAddr & 0xFF000000U) >> 24U);
WriteBfrPtr[ADDRESS_2_OFFSET] = (u8)((RealAddr & 0xFF0000U) >> 16U);
WriteBfrPtr[ADDRESS_3_OFFSET] = (u8)((RealAddr & 0xFF00U) >> 8U);
WriteBfrPtr[ADDRESS_4_OFFSET] = (u8)(RealAddr & 0xFFU);
FlashMsg[0].TxBfrPtr = WriteBfrPtr;
FlashMsg[0].RxBfrPtr = NULL;
FlashMsg[0].ByteCount = 5U;
FlashMsg[0].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[0].Flags = XQSPIPSU_MSG_FLAG_TX;
/*
* It is recommended to have a separate entry for dummy
* It is recommended that Bus width value during dummy
* phase should be same as data phase
*/
FlashMsg[1].BusWidth = XQSPIPSU_SELECT_MODE_QUADSPI;
FlashMsg[1].TxBfrPtr = NULL;
FlashMsg[1].RxBfrPtr = NULL;
FlashMsg[1].ByteCount = DUMMY_CLOCKS;
FlashMsg[1].Flags = 0U;
FlashMsg[2].BusWidth = XQSPIPSU_SELECT_MODE_QUADSPI;
FlashMsg[2].TxBfrPtr = NULL;
FlashMsg[2].RxBfrPtr = ReadBfrPtr;
FlashMsg[2].ByteCount = ByteCount;
FlashMsg[2].Flags = XQSPIPSU_MSG_FLAG_RX;
if (QspiPsuPtr->Config.ConnectionMode ==
XQSPIPSU_CONNECTION_MODE_PARALLEL) {
FlashMsg[2].Flags |= XQSPIPSU_MSG_FLAG_STRIPE;
}
Status = XQspiPsu_PolledTransfer(QspiPsuPtr, FlashMsg, 3U);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return 0;
}
/*****************************************************************************/
/**
*
* This function erases the sectors in the serial Flash connected to the
* QSPIPSU interface.
*
* @param QspiPtr is a pointer to the QSPIPSU driver component to use.
* @param Address contains the address of the first sector which needs to
* be erased.
* @param ByteCount contains the total size to be erased.
* @param Pointer to the write buffer (which is to be transmitted)
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
s32 FlashErase(XQspiPsu *QspiPsuPtr, u32 Address, u32 ByteCount,
u8 *WriteBfrPtr)
{
u8 WriteEnableCmd;
u8 ReadStatusCmd;
u8 FlashStatus[2];
u32 Sector;
u32 RealAddr;
u32 NumSect;
s32 Status;
WriteEnableCmd = WRITE_ENABLE_CMD;
/*
* Calculate no. of sectors to erase based on byte count
*/
NumSect = (ByteCount/(SECT_SIZE)) + 1U;
/*
* If ByteCount to k sectors, but the address range spans from
* N to N+k+1 sectors, then increment no. of sectors to be erased
*/
if (((Address + ByteCount) & SECT_MASK) ==
((Address + (NumSect * SECT_SIZE)) & SECT_MASK) ) {
NumSect++;
}
for (Sector = 0U; Sector < NumSect; Sector++) {
/*
* Translate address based on type of connection
* If stacked assert the slave select based on address
*/
RealAddr = GetRealAddr(QspiPsuPtr, Address);
/*
* Send the write enable command to the Flash so that it can be
* written to, this needs to be sent as a separate transfer
* before the write
*/
FlashMsg[0].TxBfrPtr = &WriteEnableCmd;
FlashMsg[0].RxBfrPtr = NULL;
FlashMsg[0].ByteCount = 1U;
FlashMsg[0].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[0].Flags = XQSPIPSU_MSG_FLAG_TX;
Status = XQspiPsu_PolledTransfer(QspiPsuPtr, FlashMsg, 1U);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
WriteBfrPtr[COMMAND_OFFSET] = SEC_ERASE_CMD_4B;
WriteBfrPtr[ADDRESS_1_OFFSET] = (u8)((RealAddr & 0xFF000000U)
>> 24U);
WriteBfrPtr[ADDRESS_2_OFFSET] = (u8)((RealAddr & 0xFF0000U)
>> 16U);
WriteBfrPtr[ADDRESS_3_OFFSET] = (u8)((RealAddr & 0xFF00U) >> 8U);
WriteBfrPtr[ADDRESS_4_OFFSET] = (u8)(RealAddr & 0xFFU);
FlashMsg[0].ByteCount = 5U;
FlashMsg[0].TxBfrPtr = WriteBfrPtr;
FlashMsg[0].RxBfrPtr = NULL;
FlashMsg[0].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[0].Flags = XQSPIPSU_MSG_FLAG_TX;
Status = XQspiPsu_PolledTransfer(QspiPsuPtr, FlashMsg, 1U);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait for the erase command to be completed
*/
while (1) {
ReadStatusCmd = READ_FLAG_STATUS_CMD;
FlashMsg[0].TxBfrPtr = &ReadStatusCmd;
FlashMsg[0].RxBfrPtr = NULL;
FlashMsg[0].ByteCount = 1U;
FlashMsg[0].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[0].Flags = XQSPIPSU_MSG_FLAG_TX;
FlashMsg[1].TxBfrPtr = NULL;
FlashMsg[1].RxBfrPtr = FlashStatus;
FlashMsg[1].ByteCount = 2U;
FlashMsg[1].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[1].Flags = XQSPIPSU_MSG_FLAG_RX;
if (QspiPsuPtr->Config.ConnectionMode ==
XQSPIPSU_CONNECTION_MODE_PARALLEL) {
FlashMsg[1].Flags |= XQSPIPSU_MSG_FLAG_STRIPE;
}
Status = XQspiPsu_PolledTransfer(QspiPsuPtr,
FlashMsg, 2U);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
if (QspiPsuPtr->Config.ConnectionMode ==
XQSPIPSU_CONNECTION_MODE_PARALLEL) {
FlashStatus[1] &= FlashStatus[0];
}
if ((FlashStatus[1] & 0x80U) != 0U) {
break;
}
}
Address += SECT_SIZE;
}
return 0;
}
/*****************************************************************************/
/**
*
* This functions translates the address based on the type of interconnection.
* In case of stacked, this function asserts the corresponding slave select.
*
* @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use.
* @param Address which is to be accessed (for erase, write or read)
*
* @return RealAddr is the translated address - for single it is unchanged.
* for stacked, the lower flash size is subtracted.
* for parallel the address is divided by 2.
*
* @note None.
*
******************************************************************************/
u32 GetRealAddr(XQspiPsu *QspiPsuPtr, u32 Address)
{
u32 RealAddr;
switch(QspiPsuPtr->Config.ConnectionMode) {
case XQSPIPSU_CONNECTION_MODE_SINGLE:
XQspiPsu_SelectFlash(QspiPsuPtr, XQSPIPSU_SELECT_FLASH_CS_LOWER,
XQSPIPSU_SELECT_FLASH_BUS_LOWER);
RealAddr = Address;
break;
case XQSPIPSU_CONNECTION_MODE_STACKED:
/* Select lower or upper Flash based on sector address */
if ((Address & FLASH_SIZE) != 0U) {
XQspiPsu_SelectFlash(QspiPsuPtr,
XQSPIPSU_SELECT_FLASH_CS_UPPER,
XQSPIPSU_SELECT_FLASH_BUS_LOWER);
RealAddr = Address & (~FLASH_SIZE);
} else {
XQspiPsu_SelectFlash(QspiPsuPtr,
XQSPIPSU_SELECT_FLASH_CS_LOWER,
XQSPIPSU_SELECT_FLASH_BUS_LOWER);
RealAddr = Address;
}
break;
case XQSPIPSU_CONNECTION_MODE_PARALLEL:
/*
* The effective address in each flash is the actual address / 2
*/
XQspiPsu_SelectFlash(QspiPsuPtr,
XQSPIPSU_SELECT_FLASH_CS_BOTH,
XQSPIPSU_SELECT_FLASH_BUS_BOTH);
RealAddr = Address / 2U;
break;
default:
RealAddr = 0x0U; /* Assign default value */
break;
}
return(RealAddr);
}
/*****************************************************************************/
/**
*
* This function initialize hardware required for normal QSPI operation.
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note By default this initialization is performed by FSBL, in case of
* resume from Power Off Suspend because FSBL initialization is
* skipped PMUFW must initialize hardware required for QSPI before
* using it.
*
******************************************************************************/
s32 PmQspiHWInit(void)
{
s32 Status;
u32 i;
/* Configure QSPI in MIOs */
for (i = 0U; i < ARRAY_SIZE(QspiMioPinArr); i++) {
XPfw_RMW32(QspiMioPinArr[i], 0x000000FEU ,0x00000002U);
}
/* Initialize MIO tri-state enables */
XPfw_RMW32(IOU_SCLR_MIO_MST_TRI0, 0x00001FFFU ,0x00000000U);
/* Initialize IOPLL used by QSPI clock */
/* Configure IOPLL */
XPfw_RMW32(CRL_APB_IOPLL_CFG, 0xFE7FEDEFU, 0x7E672C6CU);
XPfw_RMW32(CRL_APB_IOPLL_CTRL, 0x00717F00U, 0x00002D00U);
/* Bypass PLL */
XPfw_RMW32(CRL_APB_IOPLL_CTRL, 0x00000008U, 0x00000008U);
/* Assert PLL reset */
XPfw_RMW32(CRL_APB_IOPLL_CTRL, 0x00000001U, 0x00000001U);
/* Release PLL reset */
XPfw_RMW32(CRL_APB_IOPLL_CTRL, 0x00000001U, 0x00000000U);
/* Wait for PLL lock */
Status = XPfw_UtilPollForMask(CRL_APB_PLL_STATUS, 0x00000001U, 32000U);
if (XST_SUCCESS != Status) {
goto done;
}
/* Remove PLL bypass */
XPfw_RMW32(CRL_APB_IOPLL_CTRL, 0x00000008U, 0x00000000U);
/* Configure IOPLL */
XPfw_RMW32(CRL_APB_IOPLL_TO_FPD_CTRL, 0x00003F00U, 0x00000300U);
XPfw_RMW32(CRL_APB_IOPLL_FRAC_CFG, 0x8000FFFFU, 0x00000000U);
/* Configure QSPI clock */
XPfw_RMW32(CRL_APB_QSPI_REF_CTRL, 0x013F3F07U ,0x01010C00U);
/* Release QSPI reset */
XPfw_RMW32(CRL_APB_RST_LPD_IOU2, 0x00000001U ,0x00000000U);
/* Configure QSPI tap delay */
XPfw_RMW32(IOU_SCLR_TAPDLY_BYPASS, 0x00000004U ,0x00000004U);
done:
return Status;
}
#endif
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/wdtps_v3_3/src/xwdtps_sinit.c
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xwdtps_sinit.c
* @addtogroup wdtps_v3_3
* @{
*
* This file contains method for static initialization (compile-time) of the
* driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ----------------------------------------------
* 1.00a ecm/jz 01/15/10 First release
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xwdtps.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*************************** Variable Definitions ****************************/
extern XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES];
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* contains the configuration info for each device in the system.
*
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
*
******************************************************************************/
XWdtPs_Config *XWdtPs_LookupConfig(u16 DeviceId)
{
XWdtPs_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; Index < (u32)XPAR_XWDTPS_NUM_INSTANCES; Index++) {
if (XWdtPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XWdtPs_ConfigTable[Index];
break;
}
}
return (XWdtPs_Config *)CfgPtr;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pmc.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PMC_H_
#define XPM_PMC_H_
#include "xpm_core.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct XPm_Pmc XPm_Pmc;
/**
* The PMC processor class.
*/
struct XPm_Pmc {
XPm_Core Core; /**< Processor core device */
u32 PmcIouSlcrBaseAddr; /**< PMC IOU SLCR register base address */
u32 PmcGlobalBaseAddr; /**< PMC GLOBAL register base address */
u32 PmcAnalogBaseAddr; /**< PMC Analog register base address */
};
/************************** Function Prototypes ******************************/
XStatus XPmPmc_Init(XPm_Pmc *Pmc, u32 DevcieId, u32 Ipi, u32 *BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock,
XPm_ResetNode *Reset);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_PMC_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_requirement.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xplmi_util.h"
#include "xpm_requirement.h"
#include "xpm_power.h"
#include "xpm_api.h"
static XStatus XPmRequirement_Init(XPm_Requirement *Reqm,
XPm_Subsystem *Subsystem, XPm_Device *Device, u32 Flags, u32 *Params, u32 NumParams)
{
/* Prepend to subsystem's device reqm list */
Reqm->NextDevice = Subsystem->Requirements;
Subsystem->Requirements = Reqm;
Reqm->Subsystem = Subsystem;
/* Prepend to device's subsystem reqm list */
Reqm->NextSubsystem = Device->Requirements;
Device->Requirements = Reqm;
Reqm->Device = Device;
Reqm->Allocated = 0;
Reqm->SetLatReq = 0;
Reqm->Flags = (u8)(Flags & 0xFU);
if ((NULL != Params) && (0U != NumParams) && (NumParams <= MAX_REQ_PARAMS)) {
(void)XPlmi_MemCpy(Reqm->Params, Params, NumParams * sizeof(*Params));
Reqm->NumParams = NumParams;
} else {
(void)memset(Reqm->Params, 0, sizeof(Reqm->Params));
Reqm->NumParams = 0;
}
Reqm->Curr.Capabilities = XPM_MIN_CAPABILITY;
Reqm->Curr.Latency = XPM_MAX_LATENCY;
Reqm->Curr.QoS = XPM_MAX_QOS;
Reqm->Next.Capabilities = XPM_MIN_CAPABILITY;
Reqm->Next.Latency = XPM_MAX_LATENCY;
Reqm->Next.QoS = XPM_MAX_QOS;
return XST_SUCCESS;
}
XStatus XPmRequirement_Add(XPm_Subsystem *Subsystem, XPm_Device *Device, u32 Flags, u32 *Params, u32 NumParams)
{
XStatus Status = XST_FAILURE;
XPm_Requirement *Reqm;
Reqm = (XPm_Requirement *)XPm_AllocBytes(sizeof(XPm_Requirement));
if (NULL == Reqm) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Status = XPmRequirement_Init(Reqm, Subsystem, Device, Flags, Params, NumParams);
done:
return Status;
}
void XPm_RequiremntUpdate(XPm_Requirement *Reqm)
{
if(NULL != Reqm)
{
Reqm->Next.Capabilities = Reqm->Curr.Capabilities;
Reqm->Next.Latency = Reqm->Curr.Latency;
Reqm->Next.QoS = Reqm->Curr.QoS;
}
}
void XPmRequirement_Clear(XPm_Requirement* Reqm)
{
if(NULL != Reqm) {
/* Clear flag - master is not using slave anymore */
Reqm->Allocated = 0;
/* Release current and next requirements */
Reqm->Curr.Capabilities = XPM_MIN_CAPABILITY;
Reqm->Curr.Latency = XPM_MAX_LATENCY;
Reqm->Curr.QoS = XPM_MAX_QOS;
Reqm->Next.Capabilities = XPM_MIN_CAPABILITY;
Reqm->Next.Latency = XPM_MAX_LATENCY;
Reqm->Next.QoS = XPM_MAX_QOS;
}
}
XStatus XPmRequirement_Release(XPm_Requirement *Reqm, XPm_ReleaseScope Scope)
{
XStatus Status = XST_FAILURE;
XPm_Requirement *NextReqm = NULL;
if (RELEASE_ONE == Scope) {
Status = XPmDevice_Release(Reqm->Subsystem->Id, Reqm->Device->Node.Id);
goto done;
}
/*
* Release requirements of a device from all subsystems that are
* sharing the device.
*/
if (RELEASE_DEVICE == Scope) {
NextReqm = Reqm;
while (NULL != NextReqm) {
Status = XPmRequirement_Release(NextReqm, RELEASE_ONE);
if (XST_SUCCESS != Status) {
goto done;
}
NextReqm = NextReqm->NextSubsystem;
}
goto done;
}
while (NULL != Reqm) {
if ((((RELEASE_ALL == Scope) && (1U == Reqm->Allocated)) ||
((RELEASE_UNREQUESTED == Scope) && (0U == Reqm->Allocated))) &&
((u32)XPM_NODETYPE_DEV_DDR != NODETYPE(Reqm->Device->Node.Id))) {
Status = XPmDevice_Release(Reqm->Subsystem->Id, Reqm->Device->Node.Id);
if (XST_SUCCESS != Status) {
goto done;
}
}
Reqm = Reqm->NextDevice;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief Triggers the setting for scheduled requirements
*
* @param Subsystem Subsystem which changed the state and whose scheduled
requirements are triggered
* @param Swap Flag stating should current requirements be saved as next
*
* @note a) swap=false
* Set scheduled requirements of a subsystem without swapping
* current and next requirements - means the current requirements
* will be dropped. Upon every self suspend, subsystem has to
* explicitly re-request device requirements.
* b) swap=true
* Set scheduled requirements of a subsystem with swapping current
* and next requirements (swapping means the current requirements
* will be saved as next, and will be configured once subsystem
* wakes-up).
*
****************************************************************************/
XStatus XPmRequirement_UpdateScheduled(XPm_Subsystem *Subsystem, u32 Swap)
{
XStatus Status = XST_FAILURE;
XPm_Requirement *Reqm = Subsystem->Requirements;
XPm_ReqmInfo TempReq;
if (NULL == Reqm) {
Status = XST_SUCCESS;
goto done;
}
while (NULL != Reqm) {
if (Reqm->Curr.Capabilities != Reqm->Next.Capabilities) {
TempReq.Capabilities = Reqm->Next.Capabilities;
TempReq.Latency = Reqm->Next.Latency;
TempReq.QoS = Reqm->Next.QoS;
if (1U == Swap) {
Reqm->Next.Capabilities = Reqm->Curr.Capabilities;
Reqm->Next.Latency = Reqm->Curr.Latency;
Reqm->Next.QoS = Reqm->Curr.QoS;
}
Reqm->Curr.Capabilities = TempReq.Capabilities;
Reqm->Curr.Latency = TempReq.Latency;
Reqm->Curr.QoS = TempReq.QoS;
Status = XPmDevice_UpdateStatus(Reqm->Device);
if (XST_SUCCESS != Status) {
PmErr("Updating %x\r\n", Reqm->Device->Node.Id);
break;
}
}
Reqm = Reqm->NextDevice;
}
done:
return Status;
}
XStatus XPmRequirement_IsExclusive(XPm_Requirement *Reqm)
{
XStatus Status = XST_FAILURE;
XPm_Requirement *Next_Reqm;
if (NULL == Reqm) {
goto done;
}
if (1U != Reqm->Allocated) {
goto done;
}
Next_Reqm = Reqm->NextSubsystem;
while (NULL != Next_Reqm) {
if (1U == Next_Reqm->Allocated) {
goto done;
}
Next_Reqm = Next_Reqm->NextSubsystem;
}
Status = XST_SUCCESS;
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_subsystem.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_subsystem.h"
#include "xpm_clock.h"
#include "xpm_pll.h"
#include "xpm_reset.h"
#include "xpm_device.h"
#include "xpm_device_idle.h"
#include "xpm_pin.h"
#include "xpm_regs.h"
#include "xpm_rpucore.h"
#include "xpm_notifier.h"
#include "xpm_requirement.h"
static XPm_Subsystem *PmSubsystems;
static u32 MaxSubsysIdx;
/*
* Global SubsystemId which is set and is valid during XPm_CreateSubsystem()
*/
static u32 CurrentSubsystemId = INVALID_SUBSYSID;
u32 XPmSubsystem_GetIPIMask(u32 SubsystemId)
{
XPm_Subsystem *Subsystem;
u32 IpiMaskVal = 0;
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
goto done;
}
IpiMaskVal = Subsystem->IpiMask;
done:
return IpiMaskVal;
}
u32 XPmSubsystem_GetSubSysIdByIpiMask(u32 IpiMask)
{
u32 SubsystemId = INVALID_SUBSYSID;
XPm_Subsystem *Subsystem;
/* If default subsystem is active, return default subsystem id
as it does not have ipi channel mapped to it.*/
Subsystem = XPmSubsystem_GetById(PM_SUBSYS_DEFAULT);
if ((NULL != Subsystem) && ((u8)OFFLINE != Subsystem->State)) {
SubsystemId = Subsystem->Id;
goto done;
}
Subsystem = PmSubsystems;
while (NULL != Subsystem) {
if ((Subsystem->IpiMask == IpiMask) &&
((u8)OFFLINE != Subsystem->State)) {
SubsystemId = Subsystem->Id;
break;
}
Subsystem = Subsystem->NextSubsystem;
}
done:
return SubsystemId;
}
XStatus XPmSubsystem_ForceDownCleanup(u32 SubsystemId)
{
XStatus Status = XST_FAILURE;
XPm_Subsystem *Subsystem;
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
Status = XPmRequirement_Release(Subsystem->Requirements, RELEASE_ALL);
/* Todo: Cancel wakeup if scheduled
* Should be included with wakeup support
XPm_WakeUpCancelScheduled(SubSysIdx);*/
/* Unregister all notifiers for this subsystem */
XPmNotifier_UnregisterAll(Subsystem);
done:
return Status;
}
int XPmSubsystem_InitFinalize(const u32 SubsystemId)
{
int Status = XST_FAILURE;
XPm_Subsystem *Subsystem;
XPm_Device *Device;
XPm_Requirement *Reqm;
int DeviceInUse = 0;
u32 Idx, Idx2;
/* TODO: Remove this device list when CDO change is available */
u32 ExcludeDevList[] = {
PM_DEV_L2_BANK_0,
PM_DEV_IPI_0,
PM_DEV_IPI_1,
PM_DEV_IPI_2,
PM_DEV_IPI_3,
PM_DEV_IPI_4,
PM_DEV_IPI_5,
PM_DEV_IPI_6,
};
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
Status = XST_INVALID_PARAM;
goto done;
}
Subsystem->Flags |= SUBSYSTEM_INIT_FINALIZED;
for (Idx = 1; Idx < (u32)XPM_NODEIDX_DEV_MAX; Idx++) {
DeviceInUse = 0;
Device = XPmDevice_GetByIndex(Idx);
/* Exclude devices which are expected not to be requested by anyone
but should be kept on for basic functionalities to work
Soc, PMC, Efuse are required for basic boot
Ams root is root device for all sysmons and required for
any sysmon activities
Usage of GTs is board dependednt and used by multiple devices
so should be kept on*/
if ((NULL == Device) ||
((u32)XPM_NODETYPE_DEV_SOC == NODETYPE(Device->Node.Id)) ||
((u32)XPM_NODETYPE_DEV_GT == NODETYPE(Device->Node.Id)) ||
((u32)XPM_NODETYPE_DEV_CORE_PMC == NODETYPE(Device->Node.Id)) ||
((u32)XPM_NODETYPE_DEV_EFUSE == NODETYPE(Device->Node.Id)) ||
((u32)XPM_NODEIDX_DEV_AMS_ROOT == NODEINDEX(Device->Node.Id))) {
continue;
}
/* Skip if device falls in ExcludeDevList */
for (Idx2 = 0; Idx2 < ARRAY_SIZE(ExcludeDevList); Idx2++) {
if (Device->Node.Id == ExcludeDevList[Idx2]) {
break;
}
}
if (Idx2 < ARRAY_SIZE(ExcludeDevList)) {
continue;
}
if (((u32)PM_DEV_GPIO == Device->Node.Id) &&
(PLATFORM_VERSION_SILICON == Platform) &&
(PLATFORM_VERSION_SILICON_ES1 == PlatformVersion)) {
continue;
}
/* Iterate over all subsystems for particular device */
Reqm = Device->Requirements;
while (NULL != Reqm) {
if ((u8)OFFLINE == Reqm->Subsystem->State) {
Reqm = Reqm->NextSubsystem;
continue;
}
if ((1U == Reqm->Allocated) ||
(((u8)ONLINE == Reqm->Subsystem->State) &&
(0U == (Reqm->Subsystem->Flags & SUBSYSTEM_INIT_FINALIZED)))) {
DeviceInUse = 1;
break;
}
Reqm = Reqm->NextSubsystem;
}
/* Power down the device if device is unused */
if (0 == DeviceInUse) {
/*
* Here device needs to be requested and released to handle
* the use count of its clock and power. This makes unused
* clock and power to be powered down.
*/
Status = XPmDevice_Request(PM_SUBSYS_PMC, Device->Node.Id,
(u32)PM_CAP_ACCESS, XPM_MAX_QOS);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDevice_Release(PM_SUBSYS_PMC, Device->Node.Id);
if (XST_SUCCESS != Status) {
goto done;
}
} else {
Status = XST_SUCCESS;
}
}
done:
return Status;
}
int XPmSubsystem_Idle(u32 SubsystemId)
{
int Status = XST_FAILURE;
XPm_Subsystem *Subsystem;
XPm_Requirement *Reqm;
XPm_Device *Device;
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
Status = XST_FAILURE;
goto done;
}
Reqm = Subsystem->Requirements;
while (NULL != Reqm) {
Device = Reqm->Device;
u32 Usage = XPmDevice_GetUsageStatus(Subsystem, Device);
s32 IsClkActive = XPmDevice_IsClockActive(Device);
/* Check if device is requested and its clock is active */
if ((1U == Reqm->Allocated) &&
(0U == (Device->Node.Flags & NODE_IDLE_DONE)) &&
(XST_SUCCESS == IsClkActive) &&
((u32)PM_USAGE_CURRENT_SUBSYSTEM == Usage)) {
XPmDevice_SoftResetIdle(Device, DEVICE_IDLE_REQ);
Device->Node.Flags |= NODE_IDLE_DONE;
}
Reqm = Reqm->NextDevice;
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPm_IsForcePowerDownAllowed(u32 SubsystemId, u32 NodeId)
{
XStatus Status = XST_FAILURE;
if (NULL == XPmSubsystem_GetById(SubsystemId)) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
if ((u32)XPM_NODECLASS_SUBSYSTEM == NODECLASS(NodeId)) {
if (NULL == XPmSubsystem_GetById(NodeId)) {
Status = XST_INVALID_PARAM;
goto done;
}
/* Check that force powerdown is not for self or PMC subsystem */
if ((SubsystemId == NodeId) || (PM_SUBSYS_PMC == NodeId)) {
goto done;
}
}
/*TODO: Add validation based on permissions defined by user*/
/* No permission should return XPM_PM_NO_ACCESS */
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function gives Subsystem from SubsystemId.
*
* @param SubsystemId Subsystem ID
*
* @return XPm_Subsystem if successful else NULL
*
* @note None
*
****************************************************************************/
XPm_Subsystem * XPmSubsystem_GetById(u32 SubsystemId)
{
XPm_Subsystem *SubSystem = NULL;
if (SubsystemId == INVALID_SUBSYSID) {
goto done;
}
SubSystem = PmSubsystems;
while (NULL != SubSystem) {
if (SubSystem->Id == SubsystemId) {
break;
}
SubSystem = SubSystem->NextSubsystem;
}
done:
return SubSystem;
}
/****************************************************************************/
/**
* @brief This function gives Subsystem from Subsystem "INDEX".
*
* @param SubSysIdx Subsystem Index
*
* @return Pointer to XPm_Subsystem if successful else NULL
*
* @note
* This is a less strict version of XPmSubsystem_GetByIndex(),
* and mainly is implemented due to other modules such as xpm_device
* needs to access the subsystem database and iterate over it using
* indexes only, without the need to use the complete subsystem ID.
* Use this function where it is absolutely necessary.
*
****************************************************************************/
XPm_Subsystem *XPmSubsystem_GetByIndex(u32 SubSysIdx)
{
XPm_Subsystem *Subsystem = PmSubsystems;
/*
* We assume that Subsystem class, subclass and type have been
* validated before, so just validate index against bounds here
*/
while (NULL != Subsystem) {
if (SubSysIdx == NODEINDEX(Subsystem->Id)) {
break;
}
Subsystem = Subsystem->NextSubsystem;
}
return Subsystem;
}
XStatus XPm_IsWakeAllowed(u32 SubsystemId, u32 NodeId)
{
XStatus Status = XST_FAILURE;
if (NULL == XPmSubsystem_GetById(SubsystemId)) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
switch (NODECLASS(NodeId))
{
case (u32)XPM_NODECLASS_SUBSYSTEM:
/* Check that request wakeup is not for self */
if (SubsystemId == NodeId) {
Status = XST_INVALID_PARAM;
break;
}
if (NULL == XPmSubsystem_GetById(NodeId)) {
Status = XPM_INVALID_SUBSYSID;
break;
}
Status = XST_SUCCESS;
break;
case (u32)XPM_NODECLASS_DEVICE:
if ((u32)XPM_NODESUBCL_DEV_CORE != NODESUBCLASS(NodeId))
{
Status = XST_INVALID_PARAM;
break;
}
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
/*TODO: Add validation based on permissions defined by user*/
done:
return Status;
}
XStatus XPm_IsAccessAllowed(u32 SubsystemId, u32 NodeId)
{
XStatus Status = XST_FAILURE;
XPm_Subsystem *Subsystem;
XPm_PinNode *Pin;
XPm_Device *Device = NULL;
u32 DevId;
if (SubsystemId == PM_SUBSYS_PMC) {
Status = XST_SUCCESS;
goto done;
}
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
switch (NODECLASS(NodeId)) {
case (u32)XPM_NODECLASS_POWER:
/*
Node = (XPm_Node *)XPmPower_GetById(NodeId);
if (NULL == Node) {
goto done;
}
*/
break;
case (u32)XPM_NODECLASS_CLOCK:
Status = XPmClock_CheckPermissions(NODEINDEX(Subsystem->Id), NodeId);
if (XST_SUCCESS != Status) {
goto done;
}
break;
case (u32)XPM_NODECLASS_RESET:
Status = XPmReset_CheckPermissions(Subsystem, NodeId);
if (XST_SUCCESS != Status) {
goto done;
}
break;
case (u32)XPM_NODECLASS_DEVICE:
Status = XPmDevice_CheckPermissions(Subsystem, NodeId);
if (XST_SUCCESS != Status) {
goto done;
}
break;
case (u32)XPM_NODECLASS_STMIC:
Pin = XPmPin_GetById(NodeId);
if (NULL == Pin) {
goto done;
}
if ((u8)XPM_PINSTATE_UNUSED == Pin->Node.State) {
Status = XST_SUCCESS;
goto done;
}
/*
* Note: XPmDevice_GetByIndex() assumes that the caller
* is responsible for validating the Node ID attributes
* other than node index.
*/
Device = XPmDevice_GetByIndex(Pin->PinFunc->DevIdx);
if (NULL == Device) {
Status = XST_DEVICE_NOT_FOUND;
goto done;
}
DevId = Device->Node.Id;
if (((u8)XPM_PINSTATE_UNUSED == Pin->Node.State) || (0U == DevId)) {
Status = XST_SUCCESS;
goto done;
}
Status = XPmDevice_CheckPermissions(Subsystem, DevId);
if (XST_SUCCESS != Status) {
goto done;
}
break;
default:
/* XXX - Not implemented yet. */
break;
}
done:
return Status;
}
XStatus XPmSubsystem_SetState(const u32 SubsystemId, const u32 State)
{
XStatus Status = XST_FAILURE;
XPm_Subsystem *Subsystem = XPmSubsystem_GetById(SubsystemId);
if (((u32)MAX_STATE <= State) || (NULL == Subsystem)) {
Status = XST_INVALID_PARAM;
goto done;
}
Subsystem->State = (u8)State;
Status = XST_SUCCESS;
done:
return Status;
}
u32 XPmSubsystem_GetCurrent(void)
{
return CurrentSubsystemId;
}
XStatus XPmSubsystem_SetCurrent(u32 SubsystemId)
{
XStatus Status = XST_FAILURE;
if ((INVALID_SUBSYSID != SubsystemId) &&
(NULL == XPmSubsystem_GetById(SubsystemId))) {
Status = XST_INVALID_PARAM;
goto done;
}
CurrentSubsystemId = SubsystemId;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmSubsystem_Add(u32 SubsystemId)
{
XStatus Status = XST_FAILURE;
XPm_Subsystem *Subsystem;
u32 i = 0;
if (((u32)XPM_NODECLASS_SUBSYSTEM != NODECLASS(SubsystemId)) ||
((u32)XPM_NODESUBCL_SUBSYSTEM != NODESUBCLASS(SubsystemId)) ||
((u32)XPM_NODETYPE_SUBSYSTEM != NODETYPE(SubsystemId))) {
Status = XST_INVALID_PARAM;
goto done;
}
/* If default subsystem is online, no other subsystem is allowed to be created */
Subsystem = XPmSubsystem_GetById(PM_SUBSYS_DEFAULT);
if ((NULL != Subsystem) && ((u8)OFFLINE != Subsystem->State)) {
Status = XST_INVALID_PARAM;
goto done;
}
Subsystem = XPmSubsystem_GetById(SubsystemId);
if ((NULL != Subsystem) && ((u8)OFFLINE != Subsystem->State)) {
Status = XST_FAILURE;
goto done;
}
Subsystem = (XPm_Subsystem *)XPm_AllocBytes(sizeof(XPm_Subsystem));
if (NULL == Subsystem) {
Status = XST_BUFFER_TOO_SMALL;
goto done;
}
Subsystem->NextSubsystem = PmSubsystems;
Subsystem->Id = SubsystemId;
if (PM_SUBSYS_PMC == SubsystemId) {
Subsystem->Flags = SUBSYSTEM_INIT_FINALIZED;
Subsystem->IpiMask = PMC_IPI_MASK;
} else {
Subsystem->Flags = 0U;
Subsystem->IpiMask = 0U;
}
PmSubsystems = Subsystem;
if (NODEINDEX(SubsystemId) > MaxSubsysIdx) {
MaxSubsysIdx = NODEINDEX(SubsystemId);
}
/* Add all requirements for default subsystem */
if(SubsystemId == PM_SUBSYS_DEFAULT)
{
for (i = 0; i < (u32)XPM_NODEIDX_DEV_MAX; i++) {
/*
* Note: XPmDevice_GetByIndex() assumes that the caller
* is responsible for validating the Node ID attributes
* other than node index.
*/
XPm_Device *Device = XPmDevice_GetByIndex(i);
if (NULL != Device) {
Status = XPmRequirement_Add(Subsystem, Device, (((u32)REQ_ACCESS_SECURE_NONSECURE << REG_FLAGS_SECURITY_OFFSET) | (u32)REQ_NO_RESTRICTION), NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
}
}
for (i = 0; i < (u32)XPM_NODEIDX_DEV_PLD_MAX; i++) {
XPm_Device *Device = XPmDevice_GetPlDeviceByIndex(i);
if (NULL != Device) {
Status = XPmRequirement_Add(Subsystem, Device,
(((u32)REQ_ACCESS_SECURE_NONSECURE <<
REG_FLAGS_SECURITY_OFFSET) |
(u32)REQ_NO_RESTRICTION),
NULL, 0U);
if (XST_SUCCESS != Status) {
goto done;
}
}
}
}
Status = XPmSubsystem_SetState(SubsystemId, (u32)ONLINE);
if (XST_SUCCESS != Status) {
goto done;
}
done:
return Status;
}
XStatus XPmSubsystem_IsAllProcDwn(u32 SubsystemId)
{
XStatus Status = XST_FAILURE;
XPm_Subsystem *Subsystem;
XPm_Requirement *Reqm;
XPm_Device *Device;
u32 SubClass;
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
Reqm = Subsystem->Requirements;
while (NULL != Reqm) {
if (1U == Reqm->Allocated) {
Device = Reqm->Device;
SubClass = NODESUBCLASS(Device->Node.Id);
if (((u32)XPM_NODESUBCL_DEV_CORE == SubClass) &&
((u8)XPM_DEVSTATE_RUNNING == Device->Node.State)) {
goto done;
}
}
Reqm = Reqm->NextDevice;
}
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPmSubsystem_Destroy(u32 SubsystemId)
{
XStatus Status = XST_FAILURE;
XPm_Subsystem *Subsystem;
XPm_Requirement *Reqm;
XPm_Device *Device;
if (((u32)XPM_NODECLASS_SUBSYSTEM != NODECLASS(SubsystemId)) ||
((u32)XPM_NODESUBCL_SUBSYSTEM != NODESUBCLASS(SubsystemId)) ||
((u32)XPM_NODETYPE_SUBSYSTEM != NODETYPE(SubsystemId))) {
Status = XST_INVALID_PARAM;
goto done;
}
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (Subsystem == NULL || Subsystem->State != (u8)ONLINE) {
Status = XST_FAILURE;
goto done;
}
Reqm = Subsystem->Requirements;
while (NULL != Reqm) {
if (1U == Reqm->Allocated) {
Device = Reqm->Device;
Status = Device->DeviceOps->Release(Device, Subsystem);
if (XST_FAILURE == Status) {
goto done;
}
}
Reqm = Reqm->NextDevice;
}
Status = XPmSubsystem_SetState(SubsystemId, (u32)OFFLINE);
done:
return Status;
}
XStatus XPmSubsystem_Restart(u32 SubsystemId)
{
XStatus Status = XST_FAILURE;
XPm_Subsystem *Subsystem;
XPm_Requirement *Reqm;
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
Status = XPM_INVALID_SUBSYSID;
goto done;
}
/* Idle the subsystem */
Status = XPmSubsystem_Idle(SubsystemId);
if (XST_SUCCESS != Status) {
goto done;
}
/*
* In case the application has not released its
* devices prior to restart request, it is
* released here.
* Also all the cores from subsystem are gets released.
* Don't release DDR as there is no DDR CDO
* to bring it up back again.
*/
Reqm = Subsystem->Requirements;
while (NULL != Reqm) {
if ((1U == Reqm->Allocated) &&
((u32)XPM_NODETYPE_DEV_DDR != NODETYPE(Reqm->Device->Node.Id))) {
Status = XPmRequirement_Release(Reqm, RELEASE_ONE);
if (XST_SUCCESS != Status) {
goto done;
}
}
Reqm = Reqm->NextDevice;
}
done:
return Status;
}
XStatus XPmSubsystem_GetStatus(const u32 SubsystemId, const u32 DeviceId,
XPm_DeviceStatus *const DeviceStatus)
{
XStatus Status = XPM_ERR_DEVICE_STATUS;
XPm_Subsystem *Subsystem, *Target_Subsystem;
Subsystem = XPmSubsystem_GetById(SubsystemId);
Target_Subsystem = XPmSubsystem_GetById(DeviceId);
if (NULL == Subsystem || NULL == Target_Subsystem ||
NULL == DeviceStatus) {
Status = XPM_PM_INVALID_NODE;
goto done;
}
DeviceStatus->Status = Target_Subsystem->State;
Status = XST_SUCCESS;
done:
if (Status != XST_SUCCESS) {
PmErr("Returned: 0x%x\n\r", Status);
}
return Status;
}
u32 XPmSubsystem_GetMaxSubsysIdx(void)
{
return MaxSubsysIdx;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_main.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xil_io.h"
#include "xstatus.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xpfw_version.h"
#include "xpfw_default.h"
#include "xpfw_core.h"
#include "xpfw_user_startup.h"
#include "xpfw_platform.h"
#ifdef PMU_RAM_EINJ_ADDR
#include "xstl_defs.h"
#include "xstl_pmuerrinj.h"
#include "xstl_topmb.h"
#endif
#include "xpfw_restart.h"
#include "pm_system.h"
#ifdef ENABLE_DDR_SR_WR
#include "pm_hooks.h"
#endif
#ifdef PMU_RAM_EINJ_ADDR
XStl_ErrReport PMUEccErrInfo;
#endif
void Assert_CallBack(const char8 *File, s32 Line)
{
XPfw_Printf(DEBUG_PRINT_ALWAYS, "Assert occurred from file %s "
"at line %d\r\n", File, Line);
/* Trigger FW Error0 */
XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR0_MASK,
PMU_LOCAL_PMU_SERV_ERR_FWERR0_MASK);
}
XStatus XPfw_Main(void)
{
XStatus Status;
u32 xpbr_version;
#ifdef PMU_RAM_EINJ_ADDR
u32 Addr;
u32 ErrType;
u32 ControlWord;
u32 RegVal;
#endif
/* Start the Init Routine */
XPfw_Printf(DEBUG_PRINT_ALWAYS,"PMU Firmware %s\t%s %s\r\n",
ZYNQMP_XPFW_VERSION, __DATE__, __TIME__);
/* Print ROM version */
xpbr_version = XPfw_Read32(PBR_VERSION_REG);
XPfw_PrintPBRVersion(xpbr_version);
/*
* Clear previous FW error and register callback handler
* for assert conditions
*/
Xil_Out32(PMU_LOCAL_PMU_SERV_ERR, MASK32_ALL_LOW);
Xil_AssertSetCallback(Assert_CallBack);
/* Initialize the FW Core Object */
Status = XPfw_CoreInit(0U);
if (Status != XST_SUCCESS) {
XPfw_Printf(DEBUG_ERROR,"%s: Error! Core Init failed\r\n", __func__);
goto Done;
}
/* Call the User Start Up Code to add Mods, Handlers and Tasks */
XPfw_UserStartUp();
#ifdef PMU_RAM_EINJ_ADDR
/* Invoke PMU RAM ECC Error Injection STL */
Addr = PMU_RAM_EINJ_ADDR;
ErrType = XSTL_PMU_ECC_SNGLEBIT | XSTL_PMU_ECC_ERRINJ_DAT;
ControlWord = ((ErrType << 20U) | (Addr & 0xFFFFFU));
Status = XStl_PMUECCErrInj(ControlWord, 0x1U, &PMUEccErrInfo);
if(XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_ERROR,"%s: Error! PMU RAM ECC Error Injection \r\n", __func__);
/* Enable STL error bit (ERROR_SIG_2) */
RegVal = Xil_In32(XSTL_PMU_ERR_SIG_MASK_2);
RegVal |= XSTL_PMU_HW_ERR_BITMASK;
Xil_Out32(XSTL_PMU_ERR_SIG_EN_2, RegVal);
/* Trigger Error */
RegVal = Xil_In32(XSTL_PMU_SERV_ERR_REG);
/* Set bit 31 in the PMU SERV ERR Register */
RegVal |= XSTL_PMU_SERV_ERR_BITMASK;
Xil_Out32(XSTL_PMU_SERV_ERR_REG, RegVal);
goto Done;
}
#endif
/* Configure the Modules. Calls CfgInit Handlers of all modules */
Status = XPfw_CoreConfigure();
if (Status != XST_SUCCESS) {
XPfw_Printf(DEBUG_ERROR,"%s: Error! Core Cfg failed\r\n", __func__);
goto Done;
}
#ifdef ENABLE_DDR_SR_WR
if (PM_SUSPEND_TYPE_POWER_OFF != PmSystemSuspendType()) {
Status = PmHookSystemStart();
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_ERROR, "%s: Error! System start failed\r\n", __func__);
goto Done;
}
}
#endif
/* Restore system state in case of resume from Power Off Suspend */
#ifdef ENABLE_POS
if (PM_SUSPEND_TYPE_POWER_OFF == PmSystemSuspendType()) {
Status = PmSystemResumePowerOffSuspend();
if (Status != XST_SUCCESS) {
XPfw_Printf(DEBUG_ERROR,"%s: Error! Power Off Suspend resume failed\r\n", __func__);
goto Done;
}
}
#endif
/* Wait to Service the Requests */
Status = XPfw_CoreLoop();
if (Status != XST_SUCCESS) {
XPfw_Printf(DEBUG_ERROR,"%s: Error! Unexpected exit from CoreLoop\r\n",
__func__);
goto Done;
}
Done:
/* Control never comes here */
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_regs.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_REGS_H
#define XPM_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* Base Addresses
*/
#define PMC_GLOBAL_BASEADDR (0xF1110000U)
#define CPM_CRCPM_BASEADDR (0xFCA00000U)
#define PCIEA_ATTRIB_0_BASEADDR (0xFCA50000U)
#define PCIEA_ATTRIB_1_BASEADDR (0xFCA60000U)
#define CRL_BASEADDR (0xFF5E0000U)
#define PMC_TAP_BASEADDR (0xF11A0000U)
#define NPI_BASEADDR (0xF6000000U)
#define XRAM_SLCR_BASEADDR (0xFF950000U)
/**
* PMC Global module
*/
#define DOMAIN_ISO_CTRL_OFFSET (0x10000U)
#define PMC_GLOBAL_DOMAIN_ISO_CONTROL ( ( PMC_GLOBAL_BASEADDR ) + DOMAIN_ISO_CTRL_OFFSET )
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_VCCRAM_SHIFT (18U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_VCCRAM_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_VCCRAM_MASK (0x00040000U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCRAM_SOC_SHIFT (17U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCRAM_SOC_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCRAM_SOC_MASK (0x00020000U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_SOC_SHIFT (16U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_SOC_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_SOC_MASK (0x00010000U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PL_SOC_SHIFT (15U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PL_SOC_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PL_SOC_MASK (0x00008000U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_SHIFT (14U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_MASK (0x00004000U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_NPI_SHIFT (13U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_NPI_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_NPI_MASK (0x00002000U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_SHIFT (12U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_MASK (0x00001000U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_SHIFT (11U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_MASK (0x00000800U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_SHIFT (10U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_MASK (0x00000400U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_SHIFT (9U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_MASK (0x00000200U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_DFX_SHIFT (8U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_DFX_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_DFX_MASK (0x00000100U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_SOC_SHIFT (7U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_SOC_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_SOC_MASK (0x00000080U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_SHIFT (6U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_MASK (0x00000040U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_TEST_SHIFT (5U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_TEST_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_TEST_MASK (0x00000020U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_SHIFT (4U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_MASK (0x00000010U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_DFX_SHIFT (3U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_DFX_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_DFX_MASK (0x00000008U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_SOC_SHIFT (2U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_SOC_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_SOC_MASK (0x00000004U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_SHIFT (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_MASK (0x00000002U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_TEST_SHIFT (0U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_TEST_WIDTH (1U)
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_TEST_MASK (0x00000001U)
#define PWR_SUPPLY_STATUS_OFFSET (0x10CU)
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_RAM_MASK (0x00000080U)
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_PL_MASK (0x00000040U)
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_MASK (0x00000020U)
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_SOC_MASK (0x00000010U)
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_LPD_MASK (0x00000008U)
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_FPD_MASK (0x00000004U)
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_PMC_MASK (0x00000002U)
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_PMC_MASK (0x00000001U)
#define PMC_GLOBAL_SSIT_NOC_ID_OFFSET (0x00000950U)
#define PMC_GLOBAL_SSIT_NOC_ID_SWITCHID_WIDTH (13U)
#define PMC_GLOBAL_SSIT_NOC_ID_SWITCHID_MASK (0x00003FFFU)
#define CPM_PCSR_HOLDSTATE_MASK (0x00000080U)
#define CPM_PCSR_INITSTATE_MASK (0x00000040U)
#define EFUSE_CACHE_MISC_CTRL_OFFSET (0x000000A0U)
#define EFUSE_CACHE_MISC_CTRL_LBIST_EN_MASK (0x00004000U)
#define EFUSE_CACHE_TRIM_CFRM_VGG_0_OFFSET (0x000001B4U)
#define EFUSE_CACHE_TRIM_CFRM_VGG_1_OFFSET (0x000001B8U)
#define EFUSE_CACHE_TRIM_CFRM_VGG_2_OFFSET (0x000001BCU)
#define EFUSE_CACHE_TRIM_CRAM_OFFSET (0x000001C0U)
#define EFUSE_CACHE_TRIM_BRAM_OFFSET (0x00000098U)
#define EFUSE_CACHE_TRIM_URAM_OFFSET (0x0000009CU)
#define EFUSE_CACHE_BISR_RSVD_0_OFFSET (0x00000300U)
#define EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET (0x00000400U)
#define EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET (0x00000800U)
#define EFUSE_CACHE_TRIM_AMS_3_OFFSET (0X00000200U)
#define EFUSE_CACHE_TRIM_AMS_3_TSENS_SLOPE_5_0_SHIFT (9U)
#define EFUSE_CACHE_TRIM_AMS_3_TSENS_SLOPE_5_0_MASK (0X00007E00U)
#define EFUSE_CACHE_TRIM_AMS_3_TSENS_INT_OFFSET_5_0_SHIFT (3U)
#define EFUSE_CACHE_TRIM_AMS_3_TSENS_INT_OFFSET_5_0_MASK (0X000001F8U)
#define EFUSE_CACHE_TRIM_AMS_3_TSENS_DELTA_16_0_SHIFT (15U)
#define EFUSE_CACHE_TRIM_AMS_3_TSENS_DELTA_16_0_MASK (0Xffff8000U)
#define EFUSE_CACHE_TRIM_AMS_4_OFFSET (0x00000190U)
#define EFUSE_CACHE_TRIM_AMS_11_OFFSET (0X000001ACU)
#define EFUSE_CACHE_TRIM_AMS_11_IXPCM_PROCESS_15_0_SHIFT (15U)
#define EFUSE_CACHE_TRIM_AMS_11_IXPCM_PROCESS_15_0_MASK (0X7FFF8000U)
#define EFUSE_CACHE_TRIM_AMS_11_RES_PROCESS_0_SHIFT (31U)
#define EFUSE_CACHE_TRIM_AMS_11_RES_PROCESS_0_MASK (0X80000000U)
#define EFUSE_CACHE_TRIM_AMS_12_OFFSET (0X000001B0U)
#define EFUSE_CACHE_TRIM_AMS_12_BJT_PROCESS_3_0_SHIFT (6U)
#define EFUSE_CACHE_TRIM_AMS_12_BJT_PROCESS_3_0_MASK (0X000003C0U)
#define EFUSE_CACHE_TRIM_AMS_12_RES_PROCESS_6_1_SHIFT (0U)
#define EFUSE_CACHE_TRIM_AMS_12_RES_PROCESS_6_1_MASK (0X0000003FU)
#define EFUSE_CACHE_TRIM_AMS_12_TSENS_EXT_OFFSET_5_0_SHIFT (10U)
#define EFUSE_CACHE_TRIM_AMS_12_TSENS_EXT_OFFSET_5_0_MASK (0X0000FC00U)
#define EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_1_0_SHIFT (16U)
#define EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_1_0_MASK (0X00030000U)
#define EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_14_2_SHIFT (18U)
#define EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_14_2_MASK (0X7ffc0000U)
#define EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_2_SHIFT (18U)
#define EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_2_MASK (0X00040000U)
#define EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_6_SHIFT (22U)
#define EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_6_MASK (0X00400000U)
#define EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_4_3_SHIFT (19U)
#define EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_4_3_MASK (0X00180000U)
#define EFUSE_CACHE_NIDB_0_OFFSET (0x000001C4U)
#define EFUSE_CACHE_NIDB_0_NPI_BASE_1_SHIFT (23U)
#define EFUSE_CACHE_NIDB_0_NPI_BASE_1_WIDTH (9U)
#define EFUSE_CACHE_NIDB_0_NPI_BASE_1_MASK (0xFF800000U)
#define EFUSE_CACHE_NIDB_0_NPI_OFFSET_1_SHIFT (19U)
#define EFUSE_CACHE_NIDB_0_NPI_OFFSET_1_WIDTH (4U)
#define EFUSE_CACHE_NIDB_0_NPI_OFFSET_1_MASK (0x00780000U)
#define EFUSE_CACHE_NIDB_0_RDN_CNTRL_0_SHIFT (13U)
#define EFUSE_CACHE_NIDB_0_RDN_CNTRL_0_WIDTH (6U)
#define EFUSE_CACHE_NIDB_0_RDN_CNTRL_0_MASK (0x0007E000U)
#define EFUSE_CACHE_NIDB_0_NPI_BASE_0_SHIFT (4U)
#define EFUSE_CACHE_NIDB_0_NPI_BASE_0_WIDTH (9U)
#define EFUSE_CACHE_NIDB_0_NPI_BASE_0_MASK (0x00001FF0U)
#define EFUSE_CACHE_NIDB_0_NPI_OFFSET_0_SHIFT (0U)
#define EFUSE_CACHE_NIDB_0_NPI_OFFSET_0_WIDTH (4U)
#define EFUSE_CACHE_NIDB_0_NPI_OFFSET_0_MASK (0x0000000FU)
#define EFUSE_CACHE_NIDB_1_OFFSET (0x000001C8U)
#define EFUSE_CACHE_NIDB_1_NPI_BASE_3_SHIFT (29U)
#define EFUSE_CACHE_NIDB_1_NPI_BASE_3_WIDTH (3U)
#define EFUSE_CACHE_NIDB_1_NPI_BASE_3_MASK (0xE0000000U)
#define EFUSE_CACHE_NIDB_1_NPI_OFFSET_3_SHIFT (25U)
#define EFUSE_CACHE_NIDB_1_NPI_OFFSET_3_WIDTH (4U)
#define EFUSE_CACHE_NIDB_1_NPI_OFFSET_3_MASK (0x1E000000U)
#define EFUSE_CACHE_NIDB_1_RDN_CNTL_2_SHIFT (19U)
#define EFUSE_CACHE_NIDB_1_RDN_CNTL_2_WIDTH (6U)
#define EFUSE_CACHE_NIDB_1_RDN_CNTL_2_MASK (0x01F80000U)
#define EFUSE_CACHE_NIDB_1_NPI_BASE_2_SHIFT (10U)
#define EFUSE_CACHE_NIDB_1_NPI_BASE_2_WIDTH (9U)
#define EFUSE_CACHE_NIDB_1_NPI_BASE_2_MASK (0x0007FC00U)
#define EFUSE_CACHE_NIDB_1_NPI_OFFSET_2_SHIFT (6U)
#define EFUSE_CACHE_NIDB_1_NPI_OFFSET_2_WIDTH (4U)
#define EFUSE_CACHE_NIDB_1_NPI_OFFSET_2_MASK (0x000003C0U)
#define EFUSE_CACHE_NIDB_1_RDN_CNTRL_1_SHIFT (0U)
#define EFUSE_CACHE_NIDB_1_RDN_CNTRL_1_WIDTH (6U)
#define EFUSE_CACHE_NIDB_1_RDN_CNTRL_1_MASK (0x0000003FU)
#define EFUSE_CACHE_NIDB_2_OFFSET (0x000001CCU)
#define EFUSE_CACHE_NIDB_2_RDN_CNTRL_4_SHIFT (25U)
#define EFUSE_CACHE_NIDB_2_RDN_CNTRL_4_WIDTH (6U)
#define EFUSE_CACHE_NIDB_2_RDN_CNTRL_4_MASK (0x7E000000U)
#define EFUSE_CACHE_NIDB_2_NPI_BASE_4_SHIFT (16U)
#define EFUSE_CACHE_NIDB_2_NPI_BASE_4_WIDTH (9U)
#define EFUSE_CACHE_NIDB_2_NPI_BASE_4_MASK (0x01FF0000U)
#define EFUSE_CACHE_NIDB_2_NPI_OFFSET_4_SHIFT (12U)
#define EFUSE_CACHE_NIDB_2_NPI_OFFSET_4_WIDTH (4U)
#define EFUSE_CACHE_NIDB_2_NPI_OFFSET_4_MASK (0x0000F000U)
#define EFUSE_CACHE_NIDB_2_RDN_CNTL_3_SHIFT (6U)
#define EFUSE_CACHE_NIDB_2_RDN_CNTL_3_WIDTH (6U)
#define EFUSE_CACHE_NIDB_2_RDN_CNTL_3_MASK (0x00000FC0U)
#define EFUSE_CACHE_NIDB_2_NPI_BASE_3_SHIFT (0U)
#define EFUSE_CACHE_NIDB_2_NPI_BASE_3_WIDTH (6U)
#define EFUSE_CACHE_NIDB_2_NPI_BASE_3_MASK (0x0000003FU)
#define EFUSE_CONFIG0_OFFSET (0x180U)
#define EFUSE_CONFIG0_OFFSET_MASK (0x3fU)
#define EFUSE_CONFIG0_OFFSET_SHIFT (0U)
#define EFUSE_CONFIG0_SLOPE_MASK (0xfc0U)
#define EFUSE_CONFIG0_SLOPE_SHIFT (6U)
#define EFUSE_CONFIG0_PROCESS_MASK (0xffff0000U)
#define EFUSE_CONFIG0_DELTA_SHIFT (12U)
#define EFUSE_CONFIG0_DELTA_MASK (0x0000f000U)
#define EFUSE_CONFIG0_PROCESS_SHIFT (16U)
#define EFUSE_CONFIG1_OFFSET (0x184U)
#define EFUSE_CONFIG1_RESISTOR_MASK (0x7fU)
#define EFUSE_CONFIG1_RESISTOR_SHIFT (0U)
#define EFUSE_CONFIG1_BJT_OFFSET_MASK (0x780U)
#define EFUSE_CONFIG1_BJT_OFFSET_SHIFT (7U)
#define EFUSE_CONFIG1_EXT_OFFSET_MASK (0x1f800U)
#define EFUSE_CONFIG1_EXT_OFFSET_SHIFT (11U)
#define EFUSE_CONFIG1_ANA_SPARE_MASK (0x00060000U)
#define EFUSE_CONFIG1_ANA_SPARE_SHIFT (17U)
#define EFUSE_CONFIG1_DIG_SPARE_MASK (0xfff80000U)
#define EFUSE_CONFIG1_DIG_SPARE_SHIFT (19U)
#define CAL_SM_BIP_TSENS_OFFSET (0x144U)
#define CAL_SM_BIP_TSENS_BIP_MASK (0x00000001U)
#define CAL_SM_BIP_TSENS_BIP_SHIFT (0U)
#define CAL_SM_BIP_TSENS_TSENS_MASK (0x00000002U)
#define CAL_SM_BIP_TSENS_TSENS_SHIFT (1U)
#define TSENS_BIAS_CTRL_OFFSET (0x17CU)
#define TSENS_BIAS_VAL_MASK (0x00000003U)
#define TSENS_BIAS_VAL_SHIFT (0U)
#define DOMAIN_ISO_CTRL_OFFSET (0x10000U)
#define PMC_GLOBAL_DOMAIN_ISO_CONTROL ( ( PMC_GLOBAL_BASEADDR ) + DOMAIN_ISO_CTRL_OFFSET )
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE0 ( ( PMC_GLOBAL_BASEADDR ) + 0x00000050U )
#define PMC_GLOBAL_PL_STATUS_OFFSET (0x00000880U)
#define PMC_GLOBAL_PL_STATUS_POR_PL_B_MASK (0x00000001U)
#define PMC_GLOBAL_PMC_GSW_ERR_OFFSET (0x00000064U)
#define PMC_GLOBAL_PMC_GSW_ERR_CR_FLAG_SHIFT (30U)
#define PMC_GLOBAL_ERR1_STATUS_OFFSET (0x00020000U)
#define PMC_GLOBAL_ERR1_STATUS_CFU_MASK (0x00000040U)
#define PMC_GLOBAL_ERR1_STATUS_CFRAME_MASK (0x00000080U)
#define PMC_GLOBAL_ERR1_STATUS_DDRMC_MC_NCR_MASK (0x00080000U)
#define PMC_GLOBAL_ERR1_STATUS_NOC_TYPE_1_NCR_MASK (0x00002000U)
#define PMC_GLOBAL_ERR2_STATUS_OFFSET (0x00020004U)
#define PMC_GLOBAL_ERR2_STATUS_CFI_MASK (0x00020000U)
#define PMC_GLOBAL_ERR2_STATUS_CFRAME_SEU_CRC_MASK (0x00040000U)
#define PMC_GLOBAL_ERR2_STATUS_CFRAME_SEU_ECC_MASK (0x00080000U)
/**
* PMC Global GIC Proxy Module
*/
#define PMC_GLOBAL_GIC_PROXY_BASE_OFFSET (0x30000U)
#define GIC_PROXY_GROUP_OFFSET(g) (0x14U * (g))
#define PMC_GLOBAL_GICP_IRQ_ENABLE_OFFSET (0x300A8U)
#define PMC_GLOBAL_GICP_IRQ_DISABLE_OFFSET (0x300ACU)
/**
* GIC Proxy register offsets
*/
#define GIC_PROXY_IRQ_STATUS_OFFSET (0x0U)
#define GIC_PROXY_IRQ_MASK_OFFSET (0x4U)
#define GIC_PROXY_IRQ_ENABLE_OFFSET (0x8U)
#define GIC_PROXY_IRQ_DISABLE_OFFSET (0xCU)
#define GIC_PROXY_ALL_MASK (0xFFFFFFFFU)
#define GICP3_CFU_MASK (0x01000000U)
#define GICP3_CFRAME_SEU_MASK (0x02000000U)
/**
* PMC IOU SLCR Module
*/
#define PMC_IOU_SLCR_SD0_DLL_DIV_MAP0_OFFSET (0x00000458U)
#define PMC_IOU_SLCR_SD0_DLL_DIV_MAP1_OFFSET (0x0000045CU)
#define PMC_IOU_SLCR_SD1_DLL_DIV_MAP0_OFFSET (0x000004D8U)
#define PMC_IOU_SLCR_SD1_DLL_DIV_MAP1_OFFSET (0x000004DCU)
#define PMC_IOU_SLCR_WPROT0_OFFSET (0x00000828U)
/**
* PSM Global Module
*/
#define PSM_GLOBAL_APU_POWER_STATUS_INIT_OFFSET (0x00000008U)
#define PSM_GLOBAL_SCAN_CLEAR_FPD_OFFSET (0x0000092CU)
#define PSM_GLOBAL_SCAN_CLEAR_TRIGGER (0x1U)
#define PSM_GLOBAL_SCAN_CLEAR_DONE_STATUS (0x2U)
#define PSM_GLOBAL_SCAN_CLEAR_PASS_STATUS (0x4U)
#define PSM_GLOBAL_MBIST_RST_OFFSET (0x00000900U)
#define PSM_GLOBAL_MBIST_PG_EN_OFFSET (0x00000904U)
#define PSM_GLOBAL_MBIST_SETUP_OFFSET (0x00000908U)
#define PSM_GLOBAL_MBIST_DONE_OFFSET (0x00000910U)
#define PSM_GLOBAL_MBIST_GO_OFFSET (0x00000914U)
#define PSM_GLOBAL_MBIST_RST_FPD_MASK (0x0000001FU)
#define PSM_GLOBAL_MBIST_PG_EN_FPD_MASK (0x0000001FU)
#define PSM_GLOBAL_MBIST_SETUP_FPD_MASK (0x0000001FU)
#define PSM_GLOBAL_MBIST_DONE_FPD_MASK (0x0000001FU)
#define PSM_GLOBAL_MBIST_GO_FPD_MASK (0x0000001FU)
#define PSM_ERR1_STATUS_OFFSET (0x1000U)
#define PSM_ERR1_STATUS_APLL_LOCK_MASK (0x00004000U)
#define PSM_ERR1_STATUS_RPLL_LOCK_MASK (0x00008000U)
/**
* LPD IOU SLCR Module
*/
#define LPD_IOU_SLCR_WPROT0_OFFSET (0x00000728U)
/**
* LPD SLCR Module
*/
#define LPD_SLCR_WPROT0_OFFSET (0x00000000U)
#define LPD_SLCR_BISR_CACHE_DATA_0_OFFSET (0x0000010CU)
#define LPD_SLCR_BISR_CACHE_CTRL_0_OFFSET (0x00000100U)
#define LPD_SLCR_CACHE_CTRL_0_BISR_TRIGGER_MASK (0x00000001U)
#define LPD_SLCR_BISR_CACHE_CTRL_1_OFFSET (0x00000104U)
#define LPD_SLCR_CACHE_CTRL_1_PGEN0_MASK (0x00000001U)
#define LPD_SLCR_CACHE_CTRL_1_PGEN1_MASK (0x00000002U)
#define LPD_SLCR_BISR_CACHE_STATUS_OFFSET (0x00000108U)
#define LPD_SLCR_BISR_PASS_GLOBAL_MASK (0x8000000U)
#define LPD_SLCR_BISR_DONE_GLOBAL_MASK (0x4000000U)
#define LPD_SLCR_BISR_PASS_1_MASK (0x0000008U)
#define LPD_SLCR_BISR_DONE_1_MASK (0x0000004U)
#define LPD_SLCR_BISR_PASS_0_MASK (0x0000002U)
#define LPD_SLCR_BISR_DONE_0_MASK (0x0000001U)
/**
* Register: LPD_SLCR_SECURE
*/
#define LPD_SLCR_SECURE_WPROT0_OFFSET (0x00000000U)
#define LPD_SLCR_SECURE_ADMA_0_OFFSET (0x00000060U)
/**
* FPD_SLCR Module
*/
#define FPD_SLCR_WPROT0_OFFSET (0x00000000U)
#define FPD_SLCR_BISR_CACHE_DATA_0_OFFSET (0x0000040CU)
#define FPD_SLCR_BISR_CACHE_CTRL_0_OFFSET (0x00000400U)
#define FPD_SLCR_CACHE_CTRL_0_BISR_TRIGGER_MASK (0x00000001U)
#define FPD_SLCR_BISR_CACHE_CTRL_1_OFFSET (0x00000404U)
#define FPD_SLCR_CACHE_CTRL_1_PGEN0_MASK (0x00000001U)
#define FPD_SLCR_CACHE_CTRL_1_PGEN1_MASK (0x00000002U)
#define FPD_SLCR_CACHE_CTRL_1_PGEN2_MASK (0x00000004U)
#define FPD_SLCR_CACHE_CTRL_1_PGEN3_MASK (0x00000008U)
#define FPD_SLCR_BISR_CACHE_STATUS_OFFSET (0x00000408U)
#define FPD_SLCR_BISR_PASS_3_MASK (0x0000200U)
#define FPD_SLCR_BISR_DONE_3_MASK (0x0000100U)
#define FPD_SLCR_BISR_PASS_2_MASK (0x0000080U)
#define FPD_SLCR_BISR_DONE_2_MASK (0x0000040U)
#define FPD_SLCR_BISR_PASS_1_MASK (0x0000020U)
#define FPD_SLCR_BISR_DONE_1_MASK (0x0000010U)
#define FPD_SLCR_BISR_PASS_0_MASK (0x0000008U)
#define FPD_SLCR_BISR_DONE_0_MASK (0x0000004U)
#define FPD_SLCR_BISR_PASS_GLOBAL_MASK (0x0000002U)
#define FPD_SLCR_BISR_DONE_GLOBAL_MASK (0x0000001U)
#define APU_DUAL_RVBARADDR0L_OFFSET (0x40U)
#define APU_DUAL_RVBARADDR0H_OFFSET (0x44U)
#define APU_DUAL_RVBARADDR1L_OFFSET (0x48U)
#define APU_DUAL_RVBARADDR1H_OFFSET (0x4CU)
#define RPU_0_CFG_OFFSET (0x00000100U)
#define RPU_1_CFG_OFFSET (0x00000200U)
#define RPU_GLBL_CNTL_OFFSET (0x00000000U)
#define CRL_RCLK_CTRL (CRL_BASEADDR + 0x000001A0)
#define CRL_RCLK_CTRL_CLKACT_GEM_TSU_MASK (0x1000)
#define CRL_RCLK_CTRL_CLKACT_GEM0_TXRX_MASK (0x300)
#define CRL_RCLK_CTRL_CLKACT_GEM1_TXRX_MASK (0xC00)
#define CRL_PSM_RST_MODE_OFFSET (0x00000370U)
#define FPD_APU_PWRCTL_OFFSET (0x00000090U)
#define RPU_0_PWRDWN_OFFSET (0x00000108U)
#define RPU_1_PWRDWN_OFFSET (0x00000208U)
#define RPU_ERR_INJ_OFFSET (0x00000020U)
/**
* AMS_ROOT Module
*/
#define AMS_ROOT_REG_PCSR_LOCK_OFFSET (0x0000000CU)
#define AMS_ROOT_TOKEN_MNGR_OFFSET (0x00000104U)
#define AMS_ROOT_TOKEN_MNGR_BYPASS_FPD_MASK (0x00040000U)
#define AMS_ROOT_TOKEN_MNGR_BYPASS_LPD_MASK (0x00080000U)
#define AMS_ROOT_TOKEN_MNGR_BYPASS_PL_MASK (0x00100000U)
/**
* CFU APB Module
*/
#define CFU_APB_CFU_FGCR_OFFSET (0x00000018U)
#define CFU_APB_CFU_MASK_OFFSET (0x00000028U)
#define CFU_APB_CFU_MASK_INIT_COMPLETE_ENABLE_MASK (0x00000001U)
#define CFU_APB_CFU_STATUS_OFFSET (0x00000100U)
#define CFU_APB_CFU_PROTECT_OFFSET (0x00000014U)
/**
* CPM PCSR Module
*/
#define CPM_PCSR_MASK_OFFSET (0x00000000U)
#define CPM_PCSR_MASK_SCAN_CLEAR_TRIGGER_WEN_MASK (0x00000800U)
#define CPM_PCSR_PCR_OFFSET (0x00000004U)
#define CPM_PCSR_PCR_SCAN_CLEAR_TRIGGER_MASK (0x00000800U)
#define CPM_PCSR_PSR_OFFSET (0x00000008U)
#define CPM_PCSR_PSR_SCAN_CLEAR_DONE_MASK (0x00000002U)
#define CPM_PCSR_PSR_SCAN_CLEAR_PASS_MASK (0x00000004U)
#define CPM_PCSR_LOCK_OFFSET (0x0000000CU)
#define CPM_PCSR_ECO_OFFSET (0x00000020U)
/**
* CPM CRCPM Module
*/
#define CPM_CRCPM_RST_CPI0 (CPM_CRCPM_BASEADDR + 0x00000324)
#define CPM_CRCPM_RST_CPI0_RESET_SHIFT (0U)
#define CPM_CRCPM_RST_CPI1 (CPM_CRCPM_BASEADDR + 0x00000328)
#define CPM_CRCPM_RST_CPI1_RESET_SHIFT (0U)
/**
* CPM_SLCR Module
*/
#define CPM_SLCR_BISR_CACHE_DATA_0_OFFSET (0x000003F4U)
#define CPM_SLCR_BISR_CACHE_CTRL_OFFSET (0x000003F0U)
#define CPM_SLCR_BISR_CACHE_STATUS_OFFSET (0x000003ECU)
#define CPM_SLCR_BISR_CACHE_CTRL_CLR_MASK (0x00000010U)
#define CPM_SLCR_BISR_CACHE_CTRL_TRIGGER_MASK (0x00000001U)
#define CPM_SLCR_BISR_CACHE_STATUS_DONE_MASK (0x00000001U)
#define CPM_SLCR_BISR_CACHE_STATUS_PASS_MASK (0x00000002U)
/**
* CPM5_SLCR Module
*/
#define CPM5_SLCR_WPROTS_OFFSET (0x00000000U)
#define CPM5_SLCR_WPROTP_OFFSET (0x00000004U)
#define CPM5_SLCR_BISR_CACHE_STATUS_OFFSET (0x00000500U)
#define CPM5_SLCR_BISR_CACHE_STATUS_DONE_MASK (0x00000001U)
#define CPM5_SLCR_BISR_CACHE_STATUS_PASS_MASK (0x00000002U)
#define CPM5_SLCR_BISR_CACHE_CTRL_OFFSET (0x00000504U)
#define CPM5_SLCR_BISR_CACHE_CTRL_TRIGGER_MASK (0x00000001U)
#define CPM5_SLCR_BISR_CACHE_CTRL_CLR_MASK (0x00000010U)
#define CPM5_SLCR_BISR_CACHE_DATA_0_OFFSET (0x00000508U)
/**
* CPM_SLCR_SECURE Module
*/
#define CPM_SLCR_SECURE_WPROT0_OFFSET (0x00000000U)
#define CPM_SLCR_SECURE_OD_MBIST_RESET_N_OFFSET (0x00000420U)
#define CPM_SLCR_SECURE_OD_MBIST_PG_EN_OFFSET (0x00000424U)
#define CPM_SLCR_SECURE_OD_MBIST_SETUP_OFFSET (0x00000428U)
#define CPM_SLCR_SECURE_OD_MBIST_DONE_OFFSET (0x0000042CU)
#define CPM_SLCR_SECURE_OD_MBIST_GO_OFFSET (0x00000430U)
/**
* CPM5_SLCR_SECURE Module
*/
#define CPM5_SLCR_SECURE_WPROTS_OFFSET (0x00000000U)
#define CPM5_SLCR_SECURE_WPROTP_OFFSET (0x00000004U)
#define CPM5_SLCR_SECURE_OD_MBIST_TRIGGER_OFFSET (0x00000420U)
#define CPM5_SLCR_SECURE_OD_MBIST_TRIGGER_MASK (0x0007FFFFU)
#define CPM5_SLCR_SECURE_OD_MBIST_DONE_OFFSET (0x0000042CU)
#define CPM5_SLCR_SECURE_OD_MBIST_DONE_MASK (0x0007FFFFU)
#define CPM5_SLCR_SECURE_OD_MBIST_PASSOUT_OFFSET (0x00000430U)
#define CPM5_SLCR_SECURE_OD_MBIST_PASSOUT_MASK (0x0007FFFFU)
/**
* GTY PCSR Module
*/
#define GTY_PCSR_LOCK_OFFSET (0x0000000CU)
#define GTY_PCSR_MASK_OFFSET (0x00000000U)
#define GTY_PCSR_CONTROL_OFFSET (0x00000004U)
#define GTY_PCSR_STATUS_OFFSET (0x00000008U)
#define GTY_PCSR_INITCTRL_MASK (0x01000000U)
#define GTY_PCSR_MEM_CLEAR_TRIGGER_MASK (0x00040000U)
#define GTY_PCSR_BISR_TRIGGER_MASK (0x20000000U)
#define GTY_PCSR_STATUS_MEM_CLEAR_DONE_MASK (0x00000040U)
#define GTY_PCSR_STATUS_MEM_CLEAR_PASS_MASK (0x00000080U)
#define GTY_PCSR_STATUS_BISR_DONE_MASK (0x00080000U)
#define GTY_PCSR_STATUS_BISR_PASS_MASK (0x00100000U)
/**
* EFUSE CACHE Module
*/
#define EFUSE_CACHE_MISC_CTRL_OFFSET (0x000000A0U)
#define EFUSE_CACHE_MISC_CTRL_LBIST_EN_MASK (0x00004000U)
#define EFUSE_CACHE_TRIM_CFRM_VGG_0_OFFSET (0x000001B4U)
#define EFUSE_CACHE_TRIM_CFRM_VGG_1_OFFSET (0x000001B8U)
#define EFUSE_CACHE_TRIM_CFRM_VGG_2_OFFSET (0x000001BCU)
#define EFUSE_CACHE_TRIM_CRAM_OFFSET (0x000001C0U)
#define EFUSE_CACHE_TRIM_BRAM_OFFSET (0x00000098U)
#define EFUSE_CACHE_TRIM_URAM_OFFSET (0x0000009CU)
#define EFUSE_CACHE_BISR_RSVD_0_OFFSET (0x00000300U)
#define EFUSE_CACHE_TBITS1_BISR_RSVD_OFFSET (0x00000400U)
#define EFUSE_CACHE_TBITS2_BISR_RSVD_OFFSET (0x00000800U)
/**
* PCIe controller module
*/
#define PCIEA_ATTRIB_0_FABRICEN ( PCIEA_ATTRIB_0_BASEADDR + 0x00000E84 )
#define PCIEA_ATTRIB_0_FABRICEN_ATTR_SHIFT (0U)
#define PCIEA_ATTRIB_1_FABRICEN ( PCIEA_ATTRIB_1_BASEADDR + 0x00000E84 )
#define PCIEA_ATTRIB_1_FABRICEN_ATTR_SHIFT (0U)
/**
* Register: PCSR_CONTROL
*/
#define NPI_PCSR_UNLOCK_VAL (0xF9E8D7C6U)
#define NPI_PCSR_LOCK_OFFSET (0x0000000CU)
#define NPI_PCSR_MASK_OFFSET (0x00000000U)
#define NPI_PCSR_CONTROL_OFFSET (0x00000004U)
#define NPI_PCSR_CONTROL_MEM_CLEAR_TRIGGER_MASK (0x00040000U)
#define NPI_PCSR_CONTROL_ODISABLE_NPP_MASK (0x00000008U)
#define NPI_PCSR_STATUS_OFFSET (0x00000008U)
#define NPI_PCSR_STATUS_MEM_CLEAR_DONE_MASK (0x00000040U)
#define NPI_PCSR_STATUS_MEM_CLEAR_PASS_MASK (0x00000080U)
#define NPI_PCSR_CONTROL_PCOMPLETE_MASK (0x00000001U)
#define NOC_DDRMC_UB_CLK_GATE_OFFSET (0x0000024CU)
#define NOC_DDRMC_UB_CLK_GATE_BISR_EN_MASK (0x00000040U)
#define NOC_DDRMC_UB_CLK_GATE_ILA_EN_MASK (0x00000020U)
#define NPI_DDRMC_PSCR_CONTROL_UB_INITSTATE_MASK (0x01000000U)
/**
* DDRMC_UB Registers
*/
#define DDRMC_UB_PMC2UB_INTERRUPT_OFFSET (0x228U)
#define DDRMC_UB_UB2PMC_ACK_OFFSET (0x22CU)
#define DDRMC_UB_UB2PMC_DONE_OFFSET (0x230U)
#define DDRMC_UB_PMC2UB_INTERRUPT_SPARE_0_MASK BIT(2U)
#define DDRMC_UB_UB2PMC_ACK_SPARE_0_MASK BIT(2U)
#define DDRMC_UB_UB2PMC_DONE_SPARE_0_MASK BIT(2U)
#define DDRMC_UB_PMC2UB_INTERRUPT_SR_EXIT_MASK BIT(1U)
#define DDRMC_UB_UB2PMC_ACK_SR_EXIT_MASK BIT(1U)
#define DDRMC_UB_UB2PMC_DONE_SR_EXIT_MASK BIT(1U)
#define DDRMC_UB_PCSR_CONTROL_PCOMPLETE_MASK (0x1U)
/* Probe Counter Register related macros */
#define CORESIGHT_LPD_ATM_BASE (0xF0980000U)
#define CORESIGHT_FPD_ATM_BASE (0xF0B80000U)
#define PROBE_COUNTER_LAR_OFFSET (0x0FB0U)
#define PROBE_COUNTER_LSR_OFFSET (0x0FB4U)
#define PROBE_COUNTER_MAIN_CTL_OFFSET (0x1008U)
#define PROBE_COUNTER_CFG_CTL_OFFSET (0x100CU)
#define PROBE_COUNTER_STATE_PERIOD_OFFSET (0x1024U)
#define PROBE_COUNTER_PORT_SEL_OFFSET (0x1134U)
#define PROBE_COUNTER_SRC_OFFSET (0x1138U)
#define PROBE_COUNTER_VAL_OFFSET (0x113CU)
#define PROBE_COUNTER_FPD_RD_REQ_OFFSET (0x800U)
#define PROBE_COUNTER_FPD_RD_RES_OFFSET (0x000U)
#define PROBE_COUNTER_FPD_WR_REQ_OFFSET (0xC00U)
#define PROBE_COUNTER_FPD_WR_RES_OFFSET (0x400U)
#define PROBE_COUNTER_LPD_REQ_TYPE_OFFSET (0x1000U)
/**
* CRP_RESET_REASON
*/
#define CRP_RESET_REASON (0xF1260220U)
#define CRP_RESET_REASON_SLR_SYS_MASK (0x00000400U)
#define CRP_RESET_REASON_SW_SYS_MASK (0x00000200U)
#define CRP_RESET_REASON_ERR_SYS_MASK (0x00000100U)
#define CRP_RESET_REASON_DAP_SYS_MASK (0x00000080U)
#define CRP_RESET_REASON_ERR_POR_MASK (0x00000008U)
#define CRP_RESET_REASON_SLR_POR_MASK (0x00000004U)
#define CRP_RESET_REASON_SW_POR_MASK (0x00000002U)
#define CRP_RESET_REASON_EXTERNAL_POR_MASK (0x00000001U)
/**
* Definitions required from pmc_tap.h
*/
#define PMC_TAP_IDCODE ( ( PMC_TAP_BASEADDR ) + 0x00000000U )
#define PMC_TAP_VERSION ( ( PMC_TAP_BASEADDR ) + 0x00000004U )
#define PMC_TAP_VERSION_PLATFORM_SHIFT (24U)
#define PMC_TAP_VERSION_PLATFORM_MASK (0x0F000000U)
#define PMC_TAP_VERSION_PLATFORM_VERSION_SHIFT (28U)
#define PMC_TAP_VERSION_PLATFORM_VERSION_MASK (0xF0000000U)
/**
* SLR TYPES
*/
#define PMC_TAP_SLR_TYPE_OFFSET (0x00000024U)
#define PMC_TAP_SLR_TYPE_WIDTH (0x00000002U)
#define PMC_TAP_SLR_TYPE_MASK (0x00000007U)
#define XPPU_CTRL_OFFSET (0x0U)
#define XPPU_CTRL_ENABLE_SHIFT (0U)
#define XPPU_CTRL_ENABLE_MASK (0x1U)
#define XPPU_CTRL_MID_PARITY_EN_SHIFT (1U)
#define XPPU_CTRL_MID_PARITY_EN_MASK (0x2U)
#define XPPU_CTRL_APER_PARITY_EN_SHIFT (2U)
#define XPPU_CTRL_APER_PARITY_EN_MASK (0x4U)
#define XPPU_M_APERTURE_64KB_OFFSET (0x44U)
#define XPPU_M_APERTURE_1MB_OFFSET (0x48U)
#define XPPU_M_APERTURE_512MB_OFFSET (0x4CU)
#define XPPU_BASE_64KB_OFFSET (0x54U)
#define XPPU_BASE_1MB_OFFSET (0x58U)
#define XPPU_BASE_512MB_OFFSET (0x5CU)
#define XPPU_APERTURE_0_OFFSET (0x1000U)
#define XPPU_APERTURE_384_OFFSET (0x1600U)
#define XPPU_APERTURE_400_OFFSET (0x1640U)
#define XPPU_APERTURE_PERMISSION_MASK (0xFFFFFU)
#define XPPU_APERTURE_TRUSTZONE_OFFSET (27U)
#define XPPU_APERTURE_TRUSTZONE_MASK (0x8000000U)
#define XPPU_APERTURE_PARITY_SHIFT (28U)
#define XPPU_APERTURE_PARITY_MASK (0xF0000000U)
//for ES2
#define XPPU_DYNAMIC_RECONFIG_APER_ADDR_OFFSET (0x150U)
#define XPPU_DYNAMIC_RECONFIG_APER_PERM_OFFSET (0x154U)
#define XPPU_DYNAMIC_RECONFIG_EN_OFFSET (0xFCU)
//for ES1
#define XPPU_ENABLE_PERM_CHECK_REG00_OFFSET (0x150U)
/**
* OSPI Mux select related macros
*/
#define XPM_OSPI_MUX_SEL_OFFSET (0x00000504U)
#define XPM_OSPI_MUX_SEL_MASK (0x2U)
#define XPM_OSPI_MUX_SEL_SHIFT (0x1U)
/**
* USB PMU registers
*/
#define XPM_USB_CUR_PWR_OFFSET (0x00000600U)
#define XPM_USB_PWR_REQ_OFFSET (0x00000608U)
#define XPM_USB_PWR_MASK (0x3U)
/**
* IPI register masks
*/
#define IPI_PMC_ISR_ADDR (0xFF320010U)
#define PSM_IPI_BIT (0x1U)
#define PMC_IPI_MASK (0x00000002U)
#define IPI_0_MASK (0x00000004U)
#define IPI_1_MASK (0x00000008U)
#define IPI_2_MASK (0x00000010U)
#define IPI_3_MASK (0x00000020U)
#define IPI_4_MASK (0x00000040U)
#define IPI_5_MASK (0x00000080U)
#define IPI_6_MASK (0x00000200U)
/**
* XRAM registers
*/
#define XRAM_SLCR_PCSR_MASK_OFFSET (0x0000U)
#define XRAM_SLCR_PCSR_PCR_OFFSET (0x0004U)
#define XRAM_SLCR_PCSR_ODISABLE_PL_AXI0_MASK (0x00000004U)
#define XRAM_SLCR_PCSR_ODISABLE_PL_AXI1_MASK (0x00000008U)
#define XRAM_SLCR_PCSR_ODISABLE_PL_AXI2_MASK (0x00000010U)
#define XRAM_SLCR_PCSR_ODISABLE_PL_AXILITE_MASK (0x00000020U)
#define XRAM_SLCR_PCSR_FABRICEN_MASK (0x00000200U)
#define XRAM_MEM_CLEAR_TRIGGER_0_MASK (0x00040000U)
#define XRAM_SLCR_PCSR_PSR_OFFSET (0x0008U)
#define XRAM_SLCR_PCSR_PSR_MEM_CLEAR_DONE_0_MASK (0x00000040U)
#define XRAM_SLCR_PCSR_PSR_MEM_CLEAR_DONE_3_TO_1_MASK (0x000E0000U)
#define XRAM_SLCR_PCSR_PSR_MEM_CLEAR_PASS_0_MASK (0x00000080U)
#define XRAM_SLCR_PCSR_PSR_MEM_CLEAR_PASS_3_TO_1_MASK (0x00700000U)
#define XRAM_SLCR_PCSR_LOCK_OFFSET (0x000CU)
#define XRAM_SLCR_BISR_CACHE_DATA_0_OFFSET (0xE010U)
#define XRAM_SLCR_PWR_UP_BANK0_OFFSET (0x1100U)
#define XRAM_SLCR_PWR_UP_BANK1_OFFSET (0x1110U)
#define XRAM_SLCR_PWR_UP_BANK2_OFFSET (0x1120U)
#define XRAM_SLCR_PWR_UP_BANK3_OFFSET (0x1130U)
#define XRAM_SLCR_PWR_DWN_BANK0_OFFSET (0x1104U)
#define XRAM_SLCR_PWR_DWN_BANK1_OFFSET (0x1114U)
#define XRAM_SLCR_PWR_DWN_BANK2_OFFSET (0x1124U)
#define XRAM_SLCR_PWR_DWN_BANK3_OFFSET (0x1134U)
#define XRAM_SLCR_PWR_STATUS_BANK0_OFFSET (0x1108U)
#define XRAM_SLCR_PWR_STATUS_BANK1_OFFSET (0x1118U)
#define XRAM_SLCR_PWR_STATUS_BANK2_OFFSET (0x1128U)
#define XRAM_SLCR_PWR_STATUS_BANK3_OFFSET (0x1138U)
/**
* NPI Module for SSIT device
*/
#define NPI_NIR_0_OFFSET (0x00000000U)
/**
* AIE registers
*/
#define ME_NPI_REG_PCSR_STATUS_ME_PWR_SUPPLY_MASK 0x00008000U
#define ME_NPI_REG_PCSR_STATUS_SCAN_CLEAR_DONE_MASK 0x00000002U
#define ME_NPI_REG_PCSR_STATUS_SCAN_CLEAR_PASS_MASK 0x00000004U
#define ME_NPI_REG_PCSR_MASK_ME_ARRAY_RESET_MASK 0x04000000U
#define ME_NPI_REG_PCSR_MASK_INITSTATE_MASK 0x00000040U
#define ME_NPI_REG_PCSR_MASK_ME_IPOR_MASK 0x01000000U
#define ME_NPI_REG_PCSR_MASK_SCAN_CLEAR_TRIGGER_MASK 0x00000800U
#define ME_NPI_REG_PCSR_MASK_GATEREG_MASK 0x00000002U
#define ME_NPI_REG_PCSR_MASK_PCOMPLETE_MASK 0x00000001U
#define ME_NPI_REG_PCSR_MASK_MEM_CLEAR_EN_ALL_MASK 0x00800000U
#define ME_NPI_REG_PCSR_MASK_OD_BIST_SETUP_1_MASK 0x00400000U
#define ME_NPI_REG_PCSR_MASK_OD_MBIST_ASYNC_RESET_N_MASK 0x00200000U
#define ME_NPI_REG_PCSR_MASK_MEM_CLEAR_TRIGGER_MASK 0x00040000U
#define ME_NPI_REG_PCSR_STATUS_MEM_CLEAR_PASS_MASK 0x00000080U
#define ME_NPI_REG_PCSR_STATUS_MEM_CLEAR_DONE_MASK 0x00000040U
#define ME_NPI_ME_TOP_ROW_OFFSET 0x00000148U
#define ME_NPI_REG_PCSR_MASK_ODISABLE_SHIFT 2U
#define ME_NPI_REG_PCSR_MASK_ODISABLE_0_MASK \
(1U << (ME_NPI_REG_PCSR_MASK_ODISABLE_SHIFT + 0U))
#define ME_NPI_REG_PCSR_MASK_ODISABLE_1_MASK \
(1U << (ME_NPI_REG_PCSR_MASK_ODISABLE_SHIFT + 1U))
#define AIE_CORE_CONTROL_OFFSET 0x00032000U
#define AIE_CORE_STATUS_OFFSET 0x00032004U
#define AIE_CORE_ECC_SCRUB_EVENT_OFFSET 0x00032110U
#define AIE_PROGRAM_MEM_OFFSET 0x00020000U
#ifdef __cplusplus
}
#endif
#endif /* XPM_REGS_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_clock.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_CLOCK_H_
#define XPM_CLOCK_H_
#include "xpm_common.h"
#include "xpm_node.h"
#include "xpm_power.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ISOUTCLK(id) ((NODECLASS(id) == (u32)XPM_NODECLASS_CLOCK) && \
(NODESUBCLASS(id) == (u32)XPM_NODESUBCL_CLOCK_OUT) && \
(NODEINDEX(id) < (u32)XPM_NODEIDX_CLK_MAX))
#define ISREFCLK(id) ((NODECLASS(id) == (u32)XPM_NODECLASS_CLOCK) && \
(NODESUBCLASS(id) == (u32)XPM_NODESUBCL_CLOCK_REF) && \
(NODEINDEX(id) < (u32)XPM_NODEIDX_CLK_MAX))
/* Topology types */
#define TOPOLOGY_GENERIC_PLL 1U
#define TOPOLOGY_NOC_PLL 2U
#define TOPOLOGY_GENERIC_MUX_DIV 3U
#define TOPOLOGY_GENERIC_MUX_GATE 4U
#define TOPOLOGY_GENERIC_DIV_GATE 5U
#define TOPOLOGY_GENERIC_MUX_DIV_GATE_1 6U
#define TOPOLOGY_GENERIC_MUX_DIV_GATE_2 7U
#define TOPOLOGY_CUSTOM 8U
#define MAX_TOPOLOGY 9U
#define MAX_MUX_PARENTS 8U
#define MAX_NAME_BYTES 16U
/**
* The topology node class. This is the class to represent each node
* in clock topology. It can be mux/div/gate/fixed factor.
*/
struct XPm_ClkTopologyNode {
u32 Reg;
uint16_t Clkflags;
uint16_t Typeflags;
union {uint8_t Shift; uint8_t Mult;}Param1;
union {uint8_t Width; uint8_t Div;}Param2;
uint8_t Type;
};
typedef struct XPm_ClkTopology {
struct XPm_ClkTopologyNode(*Nodes)[];
uint8_t Id;
uint8_t NumNodes;
u16 MuxSources[MAX_MUX_PARENTS]; /**< Clock index of mux sources */
}XPm_ClkTopology;
typedef struct XPm_ClockNode XPm_ClockNode;
typedef struct XPm_ClockHandle XPm_ClockHandle;
/**
* The clock class. This is the base class for all the clocks.
*/
struct XPm_ClockNode {
XPm_Node Node;
char Name[MAX_NAME_BYTES];
u16 ParentIdx;
u8 NumParents;
u8 Flags;
u8 UseCount;
XPm_ClockHandle *ClkHandles; /**< Pointer to the clock/device pairs */
XPm_Power *PwrDomain;
u32 ClkRate;
};
/**
* XPm_ClockHandle - This models clock/device pair.
*/
struct XPm_ClockHandle {
XPm_ClockNode *Clock; /**< Clock used by device */
struct XPm_DeviceNode *Device; /**< Device which uses the clock */
XPm_ClockHandle *NextClock; /**< Next handle of same device */
XPm_ClockHandle *NextDevice; /**< Next handle of same clock */
};
typedef struct XPm_OutClockNode {
XPm_ClockNode ClkNode;
XPm_ClkTopology Topology;
}XPm_OutClockNode;
/* Common topology definitions */
enum XPm_ClockSubnodeType {
TYPE_INVALID,
TYPE_MUX,
TYPE_PLL,
TYPE_FIXEDFACTOR,
TYPE_DIV1,
TYPE_DIV2,
TYPE_GATE,
TYPE_MAX,
};
/* Clock states: */
#define XPM_CLK_STATE_OFF 0U
#define XPM_CLK_STATE_REQUESTED 1U //For all clocks with/without gate
#define XPM_CLK_STATE_ON 2U //For clocks with gate
/* Peripheral Clocks */
#define PERIPH_MUX_SHIFT 0
#define PERIPH_MUX_WIDTH 3
#define PERIPH_DIV_SHIFT 8
#define PERIPH_DIV_WIDTH 10
#define PERIPH_GATE1_SHIFT 25
#define PERIPH_GATE2_SHIFT 24
#define PERIPH_GATE_WIDTH 1
/* Common Flags */
#define NA_TYPE_FLAGS 0U
#define CLK_SET_RATE_GATE BIT16(0) /* must be gated across rate change */
#define CLK_SET_PARENT_GATE BIT16(1) /* must be gated across re-parent */
#define CLK_SET_RATE_PARENT BIT16(2) /* propagate rate change up one level */
#define CLK_IGNORE_UNUSED BIT16(3) /* do not gate even if unused */
#define CLK_IS_BASIC BIT16(5) /* Basic clk, can't do a to_clk_foo() */
#define CLK_GET_RATE_NOCACHE BIT16(6) /* do not use the cached clk rate */
#define CLK_SET_RATE_NO_REPARENT BIT16(7) /* don't re-parent on rate change */
#define CLK_GET_ACCURACY_NOCACHE BIT16(8) /* do not use the cached clk accuracy */
#define CLK_RECALC_NEW_RATES BIT16(9) /* recalc rates after notifications */
#define CLK_SET_RATE_UNGATE BIT16(10) /* clock needs to run to set rate */
#define CLK_IS_CRITICAL BIT16(11) /* do not gate, ever */
/* Type Flags */
#define CLK_DIVIDER_ONE_BASED BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
#define CLK_DIVIDER_HIWORD_MASK BIT(3)
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
/************************** Function Prototypes ******************************/
XStatus XPmClock_AddNode(u32 Id, u32 ControlReg, u8 TopologyType,
u8 NumCustomNodes, u8 NumParents, u32 PowerDomainId,
u8 ClkFlags);
XStatus XPmClock_AddClkName(u32 Id, char *Name);
XStatus XPmClock_AddSubNode(u32 Id, u32 Type, u32 ControlReg, u8 Param1, u8 Param2, u32 Flags);
XStatus XPmClock_AddParent(u32 Id, u32 *Parents, u8 NumParents);
XPm_ClockNode* XPmClock_GetById(u32 ClockId);
XPm_ClockNode* XPmClock_GetByIdx(u32 ClockIdx);
XStatus XPmClock_SetById(u32 ClockId, XPm_ClockNode *Clk);
XStatus XPmClock_Request(XPm_ClockHandle *ClkHandle);
XStatus XPmClock_Release(XPm_ClockHandle *ClkHandle);
XStatus XPmClock_SetGate(XPm_OutClockNode *Clk, u32 Enable);
XStatus XPmClock_SetParent(XPm_OutClockNode *Clk, u32 ParentIdx);
XStatus XPmClock_SetDivider(XPm_OutClockNode *Clk, u32 Divider);
XStatus XPmClock_GetClockData(XPm_OutClockNode *Clk, u32 Nodetype, u32 *Value);
XStatus XPmClock_QueryName(u32 ClockId, u32 *Resp);
XStatus XPmClock_QueryTopology(u32 ClockId, u32 Index, u32 *Resp);
XStatus XPmClock_QueryFFParams(u32 ClockId, u32 *Resp);
XStatus XPmClock_QueryMuxSources(u32 ClockId, u32 Index, u32 *Resp);
XStatus XPmClock_QueryAttributes(u32 ClockIndex, u32 *Resp);
XStatus XPmClock_GetNumClocks(u32 *Resp);
XStatus XPmClock_CheckPermissions(u32 SubsystemIdx, u32 ClockId);
XStatus XPmClock_GetMaxDivisor(u32 ClockId, u32 DivType, u32 *Resp);
int XPmClock_SetRate(XPm_ClockNode *Clk, const u32 ClkRate);
int XPmClock_GetRate(XPm_ClockNode *Clk, u32 *ClkRate);
#ifdef __cplusplus
}
#endif
#endif /* XPM_CLOCK_H_ */
<file_sep>/python_drivers/socket_client_test.py
# -*- coding: utf-8 -*-
"""
Created on Mon Jul 6 17:16:40 2020
@author: tianlab01
"""
import socket
server_ip = "192.168.3.11"
s = socket.socket()
s.connect((server_ip, 25565))
s.close()
print("done")<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pin.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_pin.h"
static XPm_PinNode *PmMioPins[XPM_NODEIDX_STMIC_MAX];
static u16 PmNumPins;
struct PmPinGroup {
u16 GroupCount;
u16 *GroupList;
};
static struct PmPinGroup PmPinGroups[XPM_NODEIDX_STMIC_MAX] = {
[XPM_NODEIDX_STMIC_LMIO_0] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_0,
RESERVED_GRP,
PIN_GRP_UART0_0,
PIN_GRP_GPIO2_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_0,
RESERVED_GRP,
PIN_GRP_CAN1_0,
PIN_GRP_I2C1_0,
PIN_GRP_TTC3_0_CLK,
PIN_GRP_WWDT0_0,
PIN_GRP_SYSMON_I2C0_0,
}),
},
[XPM_NODEIDX_STMIC_LMIO_1] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_1,
RESERVED_GRP,
PIN_GRP_UART0_0,
PIN_GRP_GPIO2_1,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_0_SS1,
RESERVED_GRP,
PIN_GRP_CAN1_0,
PIN_GRP_I2C1_0,
PIN_GRP_TTC3_0_WAV,
PIN_GRP_WWDT0_0,
PIN_GRP_SYSMON_I2C0_0,
}),
},
[XPM_NODEIDX_STMIC_LMIO_2] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_2,
RESERVED_GRP,
PIN_GRP_UART0_0_CTRL,
PIN_GRP_GPIO2_2,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_0_SS2,
RESERVED_GRP,
PIN_GRP_CAN0_0,
PIN_GRP_I2C0_0,
PIN_GRP_TTC2_0_CLK,
PIN_GRP_WWDT0_0,
PIN_GRP_SYSMON_I2C0_0_ALERT,
}),
},
[XPM_NODEIDX_STMIC_LMIO_3] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_3,
RESERVED_GRP,
PIN_GRP_UART0_0_CTRL,
PIN_GRP_GPIO2_3,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_0_SS0,
RESERVED_GRP,
PIN_GRP_CAN0_0,
PIN_GRP_I2C0_0,
PIN_GRP_TTC2_0_WAV,
PIN_GRP_WWDT0_0,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_LMIO_4] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_4,
RESERVED_GRP,
PIN_GRP_UART1_0,
PIN_GRP_GPIO2_4,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_0,
RESERVED_GRP,
PIN_GRP_CAN1_1,
PIN_GRP_I2C1_1,
PIN_GRP_TTC1_0_CLK,
PIN_GRP_WWDT0_0,
PIN_GRP_SYSMON_I2C0_1,
}),
},
[XPM_NODEIDX_STMIC_LMIO_5] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_5,
RESERVED_GRP,
PIN_GRP_UART1_0,
PIN_GRP_GPIO2_5,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_0,
RESERVED_GRP,
PIN_GRP_CAN1_1,
PIN_GRP_I2C1_1,
PIN_GRP_TTC1_0_WAV,
PIN_GRP_WWDT0_0,
PIN_GRP_SYSMON_I2C0_1,
}),
},
[XPM_NODEIDX_STMIC_LMIO_6] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0_CLK,
PIN_GRP_EMIO0_6,
RESERVED_GRP,
PIN_GRP_UART1_0_CTRL,
PIN_GRP_GPIO2_6,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_0,
RESERVED_GRP,
PIN_GRP_CAN0_1,
PIN_GRP_I2C0_1,
PIN_GRP_TTC0_0_CLK,
PIN_GRP_WWDT1_0,
PIN_GRP_SYSMON_I2C0_1_ALERT,
}),
},
[XPM_NODEIDX_STMIC_LMIO_7] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_7,
RESERVED_GRP,
PIN_GRP_UART1_0_CTRL,
PIN_GRP_GPIO2_7,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_0_SS0,
RESERVED_GRP,
PIN_GRP_CAN0_1,
PIN_GRP_I2C0_1,
PIN_GRP_TTC0_0_WAV,
PIN_GRP_WWDT1_0,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_LMIO_8] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_8,
RESERVED_GRP,
PIN_GRP_UART0_1,
PIN_GRP_GPIO2_8,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_0_SS1,
RESERVED_GRP,
PIN_GRP_CAN1_2,
PIN_GRP_I2C1_2,
PIN_GRP_TTC3_1_CLK,
PIN_GRP_WWDT1_0,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_LMIO_9] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_9,
RESERVED_GRP,
PIN_GRP_UART0_1,
PIN_GRP_GPIO2_9,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_0_SS2,
RESERVED_GRP,
PIN_GRP_CAN1_2,
PIN_GRP_I2C1_2,
PIN_GRP_TTC3_1_WAV,
PIN_GRP_WWDT1_0,
PIN_GRP_SYSMON_I2C0_2,
}),
},
[XPM_NODEIDX_STMIC_LMIO_10] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_10,
RESERVED_GRP,
PIN_GRP_UART0_1_CTRL,
PIN_GRP_GPIO2_10,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_0,
RESERVED_GRP,
PIN_GRP_CAN0_2,
PIN_GRP_I2C0_2,
PIN_GRP_TTC2_1_CLK,
PIN_GRP_WWDT1_0,
PIN_GRP_SYSMON_I2C0_2,
}),
},
[XPM_NODEIDX_STMIC_LMIO_11] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_11,
RESERVED_GRP,
PIN_GRP_UART0_1_CTRL,
PIN_GRP_GPIO2_11,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_0,
RESERVED_GRP,
PIN_GRP_CAN0_2,
PIN_GRP_I2C0_2,
PIN_GRP_TTC2_1_WAV,
PIN_GRP_WWDT1_0,
PIN_GRP_SYSMON_I2C0_2_ALERT,
}),
},
[XPM_NODEIDX_STMIC_LMIO_12] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_12,
RESERVED_GRP,
PIN_GRP_UART1_1,
PIN_GRP_GPIO2_12,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_1,
RESERVED_GRP,
PIN_GRP_CAN1_3,
PIN_GRP_I2C1_3,
PIN_GRP_TTC1_1_CLK,
PIN_GRP_WWDT0_1,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_LMIO_13] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_13,
RESERVED_GRP,
PIN_GRP_UART1_1,
PIN_GRP_GPIO2_13,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_1_SS0,
RESERVED_GRP,
PIN_GRP_CAN1_3,
PIN_GRP_I2C1_3,
PIN_GRP_TTC1_1_WAV,
PIN_GRP_WWDT0_1,
PIN_GRP_SYSMON_I2C0_3,
}),
},
[XPM_NODEIDX_STMIC_LMIO_14] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_14,
RESERVED_GRP,
PIN_GRP_UART1_1_CTRL,
PIN_GRP_GPIO2_14,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_1_SS1,
RESERVED_GRP,
PIN_GRP_CAN0_3,
PIN_GRP_I2C0_3,
PIN_GRP_TTC0_1_CLK,
PIN_GRP_WWDT0_1,
PIN_GRP_SYSMON_I2C0_3,
}),
},
[XPM_NODEIDX_STMIC_LMIO_15] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_15,
RESERVED_GRP,
PIN_GRP_UART1_1_CTRL,
PIN_GRP_GPIO2_15,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_1_SS2,
RESERVED_GRP,
PIN_GRP_CAN0_3,
PIN_GRP_I2C0_3,
PIN_GRP_TTC0_1_WAV,
PIN_GRP_WWDT0_1,
PIN_GRP_SYSMON_I2C0_3_ALERT,
}),
},
[XPM_NODEIDX_STMIC_LMIO_16] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_16,
RESERVED_GRP,
PIN_GRP_UART0_2,
PIN_GRP_GPIO2_16,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_1,
RESERVED_GRP,
PIN_GRP_CAN1_4,
PIN_GRP_I2C1_4,
PIN_GRP_TTC3_2_CLK,
PIN_GRP_WWDT0_1,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_LMIO_17] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_17,
RESERVED_GRP,
PIN_GRP_UART0_2,
PIN_GRP_GPIO2_17,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI0_1,
RESERVED_GRP,
PIN_GRP_CAN1_4,
PIN_GRP_I2C1_4,
PIN_GRP_TTC3_2_WAV,
PIN_GRP_WWDT0_1,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_LMIO_18] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_18,
RESERVED_GRP,
PIN_GRP_UART0_2_CTRL,
PIN_GRP_GPIO2_18,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_1,
PIN_GRP_PCIE0_0,
PIN_GRP_CAN0_4,
PIN_GRP_I2C0_4,
PIN_GRP_TTC2_2_CLK,
PIN_GRP_WWDT1_1,
PIN_GRP_SYSMON_I2C0_4,
}),
},
[XPM_NODEIDX_STMIC_LMIO_19] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_19,
RESERVED_GRP,
PIN_GRP_UART0_2_CTRL,
PIN_GRP_GPIO2_19,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_1_SS0,
PIN_GRP_PCIE0_0,
PIN_GRP_CAN0_4,
PIN_GRP_I2C0_4,
PIN_GRP_TTC2_2_WAV,
PIN_GRP_WWDT1_1,
PIN_GRP_SYSMON_I2C0_4,
}),
},
[XPM_NODEIDX_STMIC_LMIO_20] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_20,
RESERVED_GRP,
PIN_GRP_UART1_2,
PIN_GRP_GPIO2_20,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_1_SS1,
RESERVED_GRP,
PIN_GRP_CAN1_5,
PIN_GRP_I2C1_5,
PIN_GRP_TTC1_2_CLK,
PIN_GRP_WWDT1_1,
PIN_GRP_SYSMON_I2C0_4_ALERT,
}),
},
[XPM_NODEIDX_STMIC_LMIO_21] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_21,
RESERVED_GRP,
PIN_GRP_UART1_2,
PIN_GRP_GPIO2_21,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_1_SS2,
RESERVED_GRP,
PIN_GRP_CAN1_5,
PIN_GRP_I2C1_5,
PIN_GRP_TTC1_2_WAV,
PIN_GRP_WWDT1_1,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_LMIO_22] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_22,
RESERVED_GRP,
PIN_GRP_UART1_2_CTRL,
PIN_GRP_GPIO2_22,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_1,
RESERVED_GRP,
PIN_GRP_CAN0_5,
PIN_GRP_I2C0_5,
PIN_GRP_TTC0_2_CLK,
PIN_GRP_WWDT1_1,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_LMIO_23] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM1_0,
RESERVED_GRP,
PIN_GRP_TRACE0_0,
PIN_GRP_EMIO0_23,
RESERVED_GRP,
PIN_GRP_UART1_2_CTRL,
PIN_GRP_GPIO2_23,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SPI1_1,
RESERVED_GRP,
PIN_GRP_CAN0_5,
PIN_GRP_I2C0_5,
PIN_GRP_TTC0_2_WAV,
PIN_GRP_WWDT1_1,
PIN_GRP_SYSMON_I2C0_5,
}),
},
[XPM_NODEIDX_STMIC_LMIO_24] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM_TSU0_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_24,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_GPIO2_24,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_CAN1_6,
PIN_GRP_I2C1_6,
PIN_GRP_MDIO0_0,
PIN_GRP_MDIO1_0,
PIN_GRP_SYSMON_I2C0_5,
}),
},
[XPM_NODEIDX_STMIC_LMIO_25] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
RESERVED_GRP,
PIN_GRP_GEM_TSU0_1,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_25,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_GPIO2_25,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_CAN1_6,
PIN_GRP_I2C1_6,
PIN_GRP_MDIO0_0,
PIN_GRP_MDIO1_0,
PIN_GRP_SYSMON_I2C0_5_ALERT,
}),
},
[XPM_NODEIDX_STMIC_PMIO_0] = {
.GroupCount = 27,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_OSPI0_0,
PIN_GRP_QSPI0_0,
PIN_GRP_TEST_CLK_0,
RESERVED_GRP,
PIN_GRP_EMIO0_26,
RESERVED_GRP,
PIN_GRP_UART0_3,
PIN_GRP_GPIO0_0,
PIN_GRP_SYSMON_I2C0_6,
PIN_GRP_I2C1_7,
PIN_GRP_SPI0_2,
PIN_GRP_CAN0_6,
PIN_GRP_WWDT0_2,
PIN_GRP_TTC3_3_CLK,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_0_0,
PIN_GRP_SD1_4BIT_0_1,
PIN_GRP_SD1_1BIT_0_0,
PIN_GRP_SD1_1BIT_0_1,
PIN_GRP_SD1_1BIT_0_2,
PIN_GRP_SD1_1BIT_0_3,
PIN_GRP_SD1_1BIT_0_4,
PIN_GRP_SD1_1BIT_0_5,
PIN_GRP_SD1_1BIT_0_6,
PIN_GRP_SD1_1BIT_0_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_1] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0_WP,
PIN_GRP_OSPI0_0,
PIN_GRP_QSPI0_0,
PIN_GRP_TEST_CLK_0,
RESERVED_GRP,
PIN_GRP_EMIO0_27,
RESERVED_GRP,
PIN_GRP_UART0_3,
PIN_GRP_GPIO0_1,
PIN_GRP_SYSMON_I2C0_6,
PIN_GRP_I2C1_7,
PIN_GRP_SPI0_2_SS0,
PIN_GRP_CAN0_6,
PIN_GRP_WWDT0_2,
PIN_GRP_TTC3_3_WAV,
RESERVED_GRP,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_PMIO_2] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0_CD,
PIN_GRP_OSPI0_0,
PIN_GRP_QSPI0_0,
PIN_GRP_TEST_CLK_0,
RESERVED_GRP,
PIN_GRP_EMIO0_28,
RESERVED_GRP,
PIN_GRP_UART0_3_CTRL,
PIN_GRP_GPIO0_2,
PIN_GRP_SYSMON_I2C0_6_ALERT,
PIN_GRP_I2C0_6,
PIN_GRP_SPI0_2_SS1,
PIN_GRP_CAN1_7,
PIN_GRP_WWDT0_2,
PIN_GRP_TTC2_3_CLK,
PIN_GRP_I2C_PMC_0,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_PMIO_3] = {
.GroupCount = 27,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_OSPI0_0,
PIN_GRP_QSPI0_0,
PIN_GRP_TEST_CLK_0,
RESERVED_GRP,
PIN_GRP_EMIO0_29,
RESERVED_GRP,
PIN_GRP_UART0_3_CTRL,
PIN_GRP_GPIO0_3,
RESERVED_GRP,
PIN_GRP_I2C0_6,
PIN_GRP_SPI0_2_SS2,
PIN_GRP_CAN1_7,
PIN_GRP_WWDT0_2,
PIN_GRP_TTC2_3_WAV,
PIN_GRP_I2C_PMC_0,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_0_0,
PIN_GRP_SD1_4BIT_0_1,
PIN_GRP_SD1_1BIT_0_0,
PIN_GRP_SD1_1BIT_0_1,
PIN_GRP_SD1_1BIT_0_2,
PIN_GRP_SD1_1BIT_0_3,
PIN_GRP_SD1_1BIT_0_4,
PIN_GRP_SD1_1BIT_0_5,
PIN_GRP_SD1_1BIT_0_6,
PIN_GRP_SD1_1BIT_0_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_4] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_OSPI0_0,
PIN_GRP_QSPI0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_30,
RESERVED_GRP,
PIN_GRP_UART1_3,
PIN_GRP_GPIO0_4,
PIN_GRP_SYSMON_I2C0_7,
PIN_GRP_I2C1_8,
PIN_GRP_SPI0_2,
PIN_GRP_CAN0_7,
PIN_GRP_WWDT0_2,
PIN_GRP_TTC1_3_CLK,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_0_0,
PIN_GRP_SD1_1BIT_0_0,
}),
},
[XPM_NODEIDX_STMIC_PMIO_5] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_OSPI0_0,
PIN_GRP_QSPI0_0_SS,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_31,
RESERVED_GRP,
PIN_GRP_UART1_3,
PIN_GRP_GPIO0_5,
PIN_GRP_SYSMON_I2C0_7,
PIN_GRP_I2C1_8,
PIN_GRP_SPI0_2,
PIN_GRP_CAN0_7,
PIN_GRP_WWDT0_2,
PIN_GRP_TTC1_3_WAV,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_0_0,
PIN_GRP_SD1_1BIT_0_1,
}),
},
[XPM_NODEIDX_STMIC_PMIO_6] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_OSPI0_0,
PIN_GRP_QSPI0_0_FBCLK,
RESERVED_GRP,
PIN_GRP_TRACE0_1_CLK,
PIN_GRP_EMIO0_32,
RESERVED_GRP,
PIN_GRP_UART1_3_CTRL,
PIN_GRP_GPIO0_6,
PIN_GRP_SYSMON_I2C0_7_ALERT,
PIN_GRP_I2C0_7,
PIN_GRP_SPI1_2,
PIN_GRP_CAN1_8,
PIN_GRP_WWDT1_2,
PIN_GRP_TTC0_3_CLK,
PIN_GRP_I2C_PMC_1,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_0_0,
PIN_GRP_SD1_1BIT_0_2,
}),
},
[XPM_NODEIDX_STMIC_PMIO_7] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_OSPI0_0,
PIN_GRP_QSPI0_0_SS,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_33,
RESERVED_GRP,
PIN_GRP_UART1_3_CTRL,
PIN_GRP_GPIO0_7,
RESERVED_GRP,
PIN_GRP_I2C0_7,
PIN_GRP_SPI1_2_SS0,
PIN_GRP_CAN1_8,
PIN_GRP_WWDT1_2,
PIN_GRP_TTC0_3_WAV,
PIN_GRP_I2C_PMC_1,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_0_0,
PIN_GRP_SD1_1BIT_0_3,
}),
},
[XPM_NODEIDX_STMIC_PMIO_8] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_OSPI0_0,
PIN_GRP_QSPI0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_34,
RESERVED_GRP,
PIN_GRP_UART0_4,
PIN_GRP_GPIO0_8,
RESERVED_GRP,
PIN_GRP_I2C1_9,
PIN_GRP_SPI1_2_SS1,
PIN_GRP_CAN0_8,
PIN_GRP_WWDT1_2,
PIN_GRP_TTC3_4_CLK,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_0_1,
PIN_GRP_SD1_1BIT_0_4,
}),
},
[XPM_NODEIDX_STMIC_PMIO_9] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_OSPI0_0,
PIN_GRP_QSPI0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_35,
RESERVED_GRP,
PIN_GRP_UART0_4,
PIN_GRP_GPIO0_9,
PIN_GRP_SYSMON_I2C0_8,
PIN_GRP_I2C1_9,
PIN_GRP_SPI1_2_SS2,
PIN_GRP_CAN0_8,
PIN_GRP_WWDT1_2,
PIN_GRP_TTC3_4_WAV,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_0_1,
PIN_GRP_SD1_1BIT_0_5,
}),
},
[XPM_NODEIDX_STMIC_PMIO_10] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_OSPI0_0_SS,
PIN_GRP_QSPI0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_36,
RESERVED_GRP,
PIN_GRP_UART0_4_CTRL,
PIN_GRP_GPIO0_10,
PIN_GRP_SYSMON_I2C0_8,
PIN_GRP_I2C0_8,
PIN_GRP_SPI1_2,
PIN_GRP_CAN1_9,
PIN_GRP_WWDT1_2,
PIN_GRP_TTC2_4_CLK,
PIN_GRP_I2C_PMC_2,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_0_1,
PIN_GRP_SD1_1BIT_0_6,
}),
},
[XPM_NODEIDX_STMIC_PMIO_11] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0,
PIN_GRP_OSPI0_0_SS,
PIN_GRP_QSPI0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_37,
RESERVED_GRP,
PIN_GRP_UART0_4_CTRL,
PIN_GRP_GPIO0_11,
PIN_GRP_SYSMON_I2C0_8_ALERT,
PIN_GRP_I2C0_8,
PIN_GRP_SPI1_2,
PIN_GRP_CAN1_9,
PIN_GRP_WWDT1_2,
PIN_GRP_TTC2_4_WAV,
PIN_GRP_I2C_PMC_2,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_0_1,
PIN_GRP_SD1_1BIT_0_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_12] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD1_0_PC,
RESERVED_GRP,
PIN_GRP_QSPI0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_38,
RESERVED_GRP,
PIN_GRP_UART1_4,
PIN_GRP_GPIO0_12,
RESERVED_GRP,
PIN_GRP_I2C1_10,
PIN_GRP_SPI0_3,
PIN_GRP_CAN0_9,
PIN_GRP_WWDT0_3,
PIN_GRP_TTC1_4_CLK,
RESERVED_GRP,
PIN_GRP_TAMPER_TRIGGER_0,
}),
},
[XPM_NODEIDX_STMIC_PMIO_13] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0,
RESERVED_GRP,
PIN_GRP_USB0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_39,
RESERVED_GRP,
PIN_GRP_UART1_4,
PIN_GRP_GPIO0_13,
PIN_GRP_SYSMON_I2C0_9,
PIN_GRP_I2C1_10,
PIN_GRP_SPI0_3_SS0,
PIN_GRP_CAN0_9,
PIN_GRP_WWDT0_3,
PIN_GRP_TTC1_4_WAV,
RESERVED_GRP,
PIN_GRP_TAMPER_TRIGGER_0,
PIN_GRP_SD0_4BIT_0_0,
PIN_GRP_SD0_1BIT_0_0,
}),
},
[XPM_NODEIDX_STMIC_PMIO_14] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_40,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_4_CTRL,
PIN_GRP_GPIO0_14,
PIN_GRP_SYSMON_I2C0_9,
PIN_GRP_I2C0_9,
PIN_GRP_SPI0_3_SS1,
PIN_GRP_CAN1_10,
PIN_GRP_WWDT0_3,
PIN_GRP_TTC0_4_CLK,
PIN_GRP_I2C_PMC_3,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_0_0,
PIN_GRP_SD0_1BIT_0_1,
}),
},
[XPM_NODEIDX_STMIC_PMIO_15] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_41,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_4_CTRL,
PIN_GRP_GPIO0_15,
PIN_GRP_SYSMON_I2C0_9_ALERT,
PIN_GRP_I2C0_9,
PIN_GRP_SPI0_3_SS2,
PIN_GRP_CAN1_10,
PIN_GRP_WWDT0_3,
PIN_GRP_TTC0_4_WAV,
PIN_GRP_I2C_PMC_3,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_0_0,
PIN_GRP_SD0_1BIT_0_2,
}),
},
[XPM_NODEIDX_STMIC_PMIO_16] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_42,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_5,
PIN_GRP_GPIO0_16,
RESERVED_GRP,
PIN_GRP_I2C1_11,
PIN_GRP_SPI0_3,
PIN_GRP_CAN0_10,
PIN_GRP_WWDT0_3,
PIN_GRP_TTC3_5_CLK,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_0_0,
PIN_GRP_SD0_1BIT_0_3,
}),
},
[XPM_NODEIDX_STMIC_PMIO_17] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0_PC,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_43,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_5,
PIN_GRP_GPIO0_17,
RESERVED_GRP,
PIN_GRP_I2C1_11,
PIN_GRP_SPI0_3,
PIN_GRP_CAN0_10,
PIN_GRP_WWDT0_3,
PIN_GRP_TTC3_5_WAV,
RESERVED_GRP,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_PMIO_18] = {
.GroupCount = 27,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_44,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_5_CTRL,
PIN_GRP_GPIO0_18,
PIN_GRP_SYSMON_I2C0_10,
PIN_GRP_I2C0_10,
PIN_GRP_SPI1_3,
PIN_GRP_CAN1_11,
PIN_GRP_WWDT1_3,
PIN_GRP_TTC2_5_CLK,
PIN_GRP_I2C_PMC_4,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_0_0,
PIN_GRP_SD0_4BIT_0_1,
PIN_GRP_SD0_1BIT_0_0,
PIN_GRP_SD0_1BIT_0_1,
PIN_GRP_SD0_1BIT_0_2,
PIN_GRP_SD0_1BIT_0_3,
PIN_GRP_SD0_1BIT_0_4,
PIN_GRP_SD0_1BIT_0_5,
PIN_GRP_SD0_1BIT_0_6,
PIN_GRP_SD0_1BIT_0_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_19] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_45,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_5_CTRL,
PIN_GRP_GPIO0_19,
PIN_GRP_SYSMON_I2C0_10,
PIN_GRP_I2C0_10,
PIN_GRP_SPI1_3_SS0,
PIN_GRP_CAN1_11,
PIN_GRP_WWDT1_3,
PIN_GRP_TTC2_5_WAV,
PIN_GRP_I2C_PMC_4,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_0_1,
PIN_GRP_SD0_1BIT_0_4,
}),
},
[XPM_NODEIDX_STMIC_PMIO_20] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_46,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_5,
PIN_GRP_GPIO0_20,
PIN_GRP_SYSMON_I2C0_10_ALERT,
PIN_GRP_I2C1_12,
PIN_GRP_SPI1_3_SS1,
PIN_GRP_CAN0_11,
PIN_GRP_WWDT1_3,
PIN_GRP_TTC1_5_CLK,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_0_1,
PIN_GRP_SD0_1BIT_0_5,
}),
},
[XPM_NODEIDX_STMIC_PMIO_21] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
PIN_GRP_TRACE0_1,
PIN_GRP_EMIO0_47,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_5,
PIN_GRP_GPIO0_21,
RESERVED_GRP,
PIN_GRP_I2C1_12,
PIN_GRP_SPI1_3_SS2,
PIN_GRP_CAN0_11,
PIN_GRP_WWDT1_3,
PIN_GRP_TTC1_5_WAV,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_0_1,
PIN_GRP_SD0_1BIT_0_6,
}),
},
[XPM_NODEIDX_STMIC_PMIO_22] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_48,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_5_CTRL,
PIN_GRP_GPIO0_22,
RESERVED_GRP,
PIN_GRP_I2C0_11,
PIN_GRP_SPI1_3,
PIN_GRP_CAN1_12,
PIN_GRP_WWDT1_3,
PIN_GRP_TTC0_5_CLK,
PIN_GRP_I2C_PMC_5,
PIN_GRP_TAMPER_TRIGGER_0,
PIN_GRP_SD0_4BIT_0_1,
PIN_GRP_SD0_1BIT_0_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_23] = {
.GroupCount = 27,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_49,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_5_CTRL,
PIN_GRP_GPIO0_23,
PIN_GRP_SYSMON_I2C0_11,
PIN_GRP_I2C0_11,
PIN_GRP_SPI1_3,
PIN_GRP_CAN1_12,
PIN_GRP_WWDT1_3,
PIN_GRP_TTC0_5_WAV,
PIN_GRP_I2C_PMC_5,
PIN_GRP_TAMPER_TRIGGER_0,
PIN_GRP_SD0_4BIT_0_0,
PIN_GRP_SD0_4BIT_0_1,
PIN_GRP_SD0_1BIT_0_0,
PIN_GRP_SD0_1BIT_0_1,
PIN_GRP_SD0_1BIT_0_2,
PIN_GRP_SD0_1BIT_0_3,
PIN_GRP_SD0_1BIT_0_4,
PIN_GRP_SD0_1BIT_0_5,
PIN_GRP_SD0_1BIT_0_6,
PIN_GRP_SD0_1BIT_0_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_24] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0_CD,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_50,
PIN_GRP_TEST_SCAN_0,
RESERVED_GRP,
PIN_GRP_GPIO0_24,
PIN_GRP_SYSMON_I2C0_11,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_PCIE0_1,
}),
},
[XPM_NODEIDX_STMIC_PMIO_25] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD0_0_WP,
PIN_GRP_SMAP0_0,
PIN_GRP_USB0_0,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_51,
PIN_GRP_TEST_SCAN_0,
RESERVED_GRP,
PIN_GRP_GPIO0_25,
PIN_GRP_SYSMON_I2C0_11_ALERT,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_PCIE0_1,
}),
},
[XPM_NODEIDX_STMIC_PMIO_26] = {
.GroupCount = 27,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1,
RESERVED_GRP,
PIN_GRP_GEM0_1,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_52,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_6,
PIN_GRP_GPIO1_0,
PIN_GRP_SYSMON_I2C0_12,
PIN_GRP_I2C0_12,
PIN_GRP_SPI0_4,
PIN_GRP_CAN0_12,
PIN_GRP_WWDT0_4,
PIN_GRP_TTC3_6_CLK,
PIN_GRP_I2C_PMC_6,
PIN_GRP_TAMPER_TRIGGER_0,
PIN_GRP_SD1_4BIT_1_0,
PIN_GRP_SD1_4BIT_1_1,
PIN_GRP_SD1_1BIT_1_0,
PIN_GRP_SD1_1BIT_1_1,
PIN_GRP_SD1_1BIT_1_2,
PIN_GRP_SD1_1BIT_1_3,
PIN_GRP_SD1_1BIT_1_4,
PIN_GRP_SD1_1BIT_1_5,
PIN_GRP_SD1_1BIT_1_6,
PIN_GRP_SD1_1BIT_1_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_27] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1,
RESERVED_GRP,
PIN_GRP_GEM0_1,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_53,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_6,
PIN_GRP_GPIO1_1,
PIN_GRP_SYSMON_I2C0_12,
PIN_GRP_I2C0_12,
PIN_GRP_SPI0_4_SS0,
PIN_GRP_CAN0_12,
PIN_GRP_WWDT0_4,
PIN_GRP_TTC3_6_WAV,
PIN_GRP_I2C_PMC_6,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_1_1,
PIN_GRP_SD1_1BIT_1_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_28] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1_CD,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM0_1,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_54,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_6_CTRL,
PIN_GRP_GPIO1_2,
PIN_GRP_SYSMON_I2C0_12_ALERT,
PIN_GRP_I2C1_13,
PIN_GRP_SPI0_4_SS1,
PIN_GRP_CAN1_13,
PIN_GRP_WWDT0_4,
PIN_GRP_TTC2_6_CLK,
RESERVED_GRP,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_PMIO_29] = {
.GroupCount = 27,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM0_1,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_55,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_6_CTRL,
PIN_GRP_GPIO1_3,
RESERVED_GRP,
PIN_GRP_I2C1_13,
PIN_GRP_SPI0_4_SS2,
PIN_GRP_CAN1_13,
PIN_GRP_WWDT0_4,
PIN_GRP_TTC2_6_WAV,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_1_0,
PIN_GRP_SD1_4BIT_1_1,
PIN_GRP_SD1_1BIT_1_0,
PIN_GRP_SD1_1BIT_1_1,
PIN_GRP_SD1_1BIT_1_2,
PIN_GRP_SD1_1BIT_1_3,
PIN_GRP_SD1_1BIT_1_4,
PIN_GRP_SD1_1BIT_1_5,
PIN_GRP_SD1_1BIT_1_6,
PIN_GRP_SD1_1BIT_1_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_30] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM0_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_56,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_6,
PIN_GRP_GPIO1_4,
PIN_GRP_SYSMON_I2C0_13,
PIN_GRP_I2C0_13,
PIN_GRP_SPI0_4,
PIN_GRP_CAN0_13,
PIN_GRP_WWDT0_4,
PIN_GRP_TTC1_6_CLK,
PIN_GRP_I2C_PMC_7,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_1_0,
PIN_GRP_SD1_1BIT_1_0,
}),
},
[XPM_NODEIDX_STMIC_PMIO_31] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM0_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_57,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_6,
PIN_GRP_GPIO1_5,
PIN_GRP_SYSMON_I2C0_13,
PIN_GRP_I2C0_13,
PIN_GRP_SPI0_4,
PIN_GRP_CAN0_13,
PIN_GRP_WWDT0_4,
PIN_GRP_TTC1_6_WAV,
PIN_GRP_I2C_PMC_7,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_1_0,
PIN_GRP_SD1_1BIT_1_1,
}),
},
[XPM_NODEIDX_STMIC_PMIO_32] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM0_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2_CLK,
PIN_GRP_EMIO0_58,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_6_CTRL,
PIN_GRP_GPIO1_6,
PIN_GRP_SYSMON_I2C0_13_ALERT,
PIN_GRP_I2C1_14,
PIN_GRP_SPI1_4,
PIN_GRP_CAN1_14,
PIN_GRP_WWDT1_4,
PIN_GRP_TTC0_6_CLK,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_1_0,
PIN_GRP_SD1_1BIT_1_2,
}),
},
[XPM_NODEIDX_STMIC_PMIO_33] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM0_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_59,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_6_CTRL,
PIN_GRP_GPIO1_7,
RESERVED_GRP,
PIN_GRP_I2C1_14,
PIN_GRP_SPI1_4_SS0,
PIN_GRP_CAN1_14,
PIN_GRP_WWDT1_4,
PIN_GRP_TTC0_6_WAV,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_1_0,
PIN_GRP_SD1_1BIT_1_3,
}),
},
[XPM_NODEIDX_STMIC_PMIO_34] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM0_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_60,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_7,
PIN_GRP_GPIO1_8,
RESERVED_GRP,
PIN_GRP_I2C0_14,
PIN_GRP_SPI1_4_SS1,
PIN_GRP_CAN0_14,
PIN_GRP_WWDT1_4,
PIN_GRP_TTC3_7_CLK,
PIN_GRP_I2C_PMC_8,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_1_1,
PIN_GRP_SD1_1BIT_1_4,
}),
},
[XPM_NODEIDX_STMIC_PMIO_35] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM0_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_61,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_7,
PIN_GRP_GPIO1_9,
PIN_GRP_SYSMON_I2C0_14,
PIN_GRP_I2C0_14,
PIN_GRP_SPI1_4_SS2,
PIN_GRP_CAN0_14,
PIN_GRP_WWDT1_4,
PIN_GRP_TTC3_7_WAV,
PIN_GRP_I2C_PMC_8,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_1_1,
PIN_GRP_SD1_1BIT_1_5,
}),
},
[XPM_NODEIDX_STMIC_PMIO_36] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM0_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_62,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_7_CTRL,
PIN_GRP_GPIO1_10,
PIN_GRP_SYSMON_I2C0_14,
PIN_GRP_I2C1_15,
PIN_GRP_SPI1_4,
PIN_GRP_CAN1_15,
PIN_GRP_WWDT1_4,
PIN_GRP_TTC2_7_CLK,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD1_4BIT_1_1,
PIN_GRP_SD1_1BIT_1_6,
}),
},
[XPM_NODEIDX_STMIC_PMIO_37] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1_WP,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM0_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_63,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_7_CTRL,
PIN_GRP_GPIO1_11,
PIN_GRP_SYSMON_I2C0_14_ALERT,
PIN_GRP_I2C1_15,
PIN_GRP_SPI1_4,
PIN_GRP_CAN1_15,
PIN_GRP_WWDT1_4,
PIN_GRP_TTC2_7_WAV,
RESERVED_GRP,
PIN_GRP_TAMPER_TRIGGER_0,
}),
},
[XPM_NODEIDX_STMIC_PMIO_38] = {
.GroupCount = 27,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_64,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_7,
PIN_GRP_GPIO1_12,
RESERVED_GRP,
PIN_GRP_I2C0_15,
PIN_GRP_SPI0_5,
PIN_GRP_CAN0_15,
PIN_GRP_WWDT0_5,
PIN_GRP_TTC1_7_CLK,
PIN_GRP_I2C_PMC_9,
PIN_GRP_PCIE0_2,
PIN_GRP_SD0_4BIT_1_0,
PIN_GRP_SD0_4BIT_1_1,
PIN_GRP_SD0_1BIT_1_0,
PIN_GRP_SD0_1BIT_1_1,
PIN_GRP_SD0_1BIT_1_2,
PIN_GRP_SD0_1BIT_1_3,
PIN_GRP_SD0_1BIT_1_4,
PIN_GRP_SD0_1BIT_1_5,
PIN_GRP_SD0_1BIT_1_6,
PIN_GRP_SD0_1BIT_1_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_39] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1_CD,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_65,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_7,
PIN_GRP_GPIO1_13,
PIN_GRP_SYSMON_I2C0_15,
PIN_GRP_I2C0_15,
PIN_GRP_SPI0_5_SS0,
PIN_GRP_CAN0_15,
PIN_GRP_WWDT0_5,
PIN_GRP_TTC1_7_WAV,
PIN_GRP_I2C_PMC_9,
PIN_GRP_PCIE0_2,
}),
},
[XPM_NODEIDX_STMIC_PMIO_40] = {
.GroupCount = 27,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_66,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_7_CTRL,
PIN_GRP_GPIO1_14,
PIN_GRP_SYSMON_I2C0_15,
PIN_GRP_I2C1_16,
PIN_GRP_SPI0_5_SS1,
PIN_GRP_CAN1_16,
PIN_GRP_WWDT0_5,
PIN_GRP_TTC0_7_CLK,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_1_0,
PIN_GRP_SD0_4BIT_1_1,
PIN_GRP_SD0_1BIT_1_0,
PIN_GRP_SD0_1BIT_1_1,
PIN_GRP_SD0_1BIT_1_2,
PIN_GRP_SD0_1BIT_1_3,
PIN_GRP_SD0_1BIT_1_4,
PIN_GRP_SD0_1BIT_1_5,
PIN_GRP_SD0_1BIT_1_6,
PIN_GRP_SD0_1BIT_1_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_41] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_67,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_7_CTRL,
PIN_GRP_GPIO1_15,
PIN_GRP_SYSMON_I2C0_15_ALERT,
PIN_GRP_I2C1_16,
PIN_GRP_SPI0_5_SS2,
PIN_GRP_CAN1_16,
PIN_GRP_WWDT0_5,
PIN_GRP_TTC0_7_WAV,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_1_0,
PIN_GRP_SD0_1BIT_1_0,
}),
},
[XPM_NODEIDX_STMIC_PMIO_42] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_68,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_8,
PIN_GRP_GPIO1_16,
RESERVED_GRP,
PIN_GRP_I2C0_16,
PIN_GRP_SPI0_5,
PIN_GRP_CAN0_16,
PIN_GRP_WWDT0_5,
PIN_GRP_TTC3_8_CLK,
PIN_GRP_I2C_PMC_10,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_1_0,
PIN_GRP_SD0_1BIT_1_1,
}),
},
[XPM_NODEIDX_STMIC_PMIO_43] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_69,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_8,
PIN_GRP_GPIO1_17,
RESERVED_GRP,
PIN_GRP_I2C0_16,
PIN_GRP_SPI0_5,
PIN_GRP_CAN0_16,
PIN_GRP_WWDT0_5,
PIN_GRP_TTC3_8_WAV,
PIN_GRP_I2C_PMC_10,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_1_0,
PIN_GRP_SD0_1BIT_1_2,
}),
},
[XPM_NODEIDX_STMIC_PMIO_44] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_70,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_8_CTRL,
PIN_GRP_GPIO1_18,
PIN_GRP_SYSMON_I2C0_16,
PIN_GRP_I2C1_17,
PIN_GRP_SPI1_5,
PIN_GRP_CAN1_17,
PIN_GRP_WWDT1_5,
PIN_GRP_TTC2_8_CLK,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_1_0,
PIN_GRP_SD0_1BIT_1_3,
}),
},
[XPM_NODEIDX_STMIC_PMIO_45] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_71,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART0_8_CTRL,
PIN_GRP_GPIO1_19,
PIN_GRP_SYSMON_I2C0_16,
PIN_GRP_I2C1_17,
PIN_GRP_SPI1_5_SS0,
PIN_GRP_CAN1_17,
PIN_GRP_WWDT1_5,
PIN_GRP_TTC2_8_WAV,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_1_1,
PIN_GRP_SD0_1BIT_1_4,
}),
},
[XPM_NODEIDX_STMIC_PMIO_46] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_72,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_8,
PIN_GRP_GPIO1_20,
PIN_GRP_SYSMON_I2C0_16_ALERT,
PIN_GRP_I2C0_17,
PIN_GRP_SPI1_5_SS1,
PIN_GRP_CAN0_17,
PIN_GRP_WWDT1_5,
PIN_GRP_TTC1_8_CLK,
PIN_GRP_I2C_PMC_11,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_1_1,
PIN_GRP_SD0_1BIT_1_5,
}),
},
[XPM_NODEIDX_STMIC_PMIO_47] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
PIN_GRP_TRACE0_2,
PIN_GRP_EMIO0_73,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_8,
PIN_GRP_GPIO1_21,
RESERVED_GRP,
PIN_GRP_I2C0_17,
PIN_GRP_SPI1_5_SS2,
PIN_GRP_CAN0_17,
PIN_GRP_WWDT1_5,
PIN_GRP_TTC1_8_WAV,
PIN_GRP_I2C_PMC_11,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_1_1,
PIN_GRP_SD0_1BIT_1_6,
}),
},
[XPM_NODEIDX_STMIC_PMIO_48] = {
.GroupCount = 19,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_74,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_8_CTRL,
PIN_GRP_GPIO1_22,
RESERVED_GRP,
PIN_GRP_I2C1_18,
PIN_GRP_SPI1_5,
PIN_GRP_CAN1_18,
PIN_GRP_WWDT1_5,
PIN_GRP_TTC0_8_CLK,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_SD0_4BIT_1_1,
PIN_GRP_SD0_1BIT_1_7,
}),
},
[XPM_NODEIDX_STMIC_PMIO_49] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD0_1_PC,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM1_1,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_75,
PIN_GRP_TEST_SCAN_0,
PIN_GRP_UART1_8_CTRL,
PIN_GRP_GPIO1_23,
PIN_GRP_SYSMON_I2C0_17,
PIN_GRP_I2C1_18,
PIN_GRP_SPI1_5,
PIN_GRP_CAN1_18,
PIN_GRP_WWDT1_5,
PIN_GRP_TTC0_8_WAV,
RESERVED_GRP,
RESERVED_GRP,
}),
},
[XPM_NODEIDX_STMIC_PMIO_50] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1_WP,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM_TSU0_2,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_76,
PIN_GRP_TEST_SCAN_0,
RESERVED_GRP,
PIN_GRP_GPIO1_24,
PIN_GRP_SYSMON_I2C0_17,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_MDIO0_1,
PIN_GRP_MDIO1_1,
RESERVED_GRP,
PIN_GRP_I2C_PMC_12,
PIN_GRP_TAMPER_TRIGGER_0,
}),
},
[XPM_NODEIDX_STMIC_PMIO_51] = {
.GroupCount = 17,
.GroupList = ((u16 []) {
PIN_GRP_SD1_1_PC,
PIN_GRP_SMAP0_0,
PIN_GRP_GEM_TSU0_3,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_EMIO0_77,
PIN_GRP_TEST_SCAN_0,
RESERVED_GRP,
PIN_GRP_GPIO1_25,
PIN_GRP_SYSMON_I2C0_17_ALERT,
RESERVED_GRP,
RESERVED_GRP,
PIN_GRP_MDIO0_1,
PIN_GRP_MDIO1_1,
RESERVED_GRP,
PIN_GRP_I2C_PMC_12,
PIN_GRP_TAMPER_TRIGGER_0,
}),
},
};
/****************************************************************************/
/**
* @brief This function validates PinFunction availability in given Pin.
*
* @param Pin Pin Node.
* @param PinFunc Pin Function.
*
* @return 1 if function is available on given pin else 0.
*
****************************************************************************/
static u8 ValidatePinFunc(XPm_PinNode *Pin, XPm_PinFunc *PinFunc)
{
u16 FGrpIdx, PGrpIdx;
u16 *FunGrps, *PinGrps;
u8 IsValid = 0;
FunGrps = PinFunc->Groups;
PinGrps = Pin->Groups;
for (PGrpIdx = 0; PGrpIdx < Pin->NumGroups; PGrpIdx++) {
for (FGrpIdx = 0; FGrpIdx < PinFunc->NumGroups; FGrpIdx++) {
if (FunGrps[FGrpIdx] == PinGrps[PGrpIdx]) {
IsValid = 1;
break;
}
}
if (1U == IsValid) {
break;
}
}
return IsValid;
}
/****************************************************************************/
/**
* @brief This function initializes the XPm_PinNode data staructure.
*
* @param Pin XPm_PinNode data staructure.
* @param PinId PinNode ID.
* @param BaseAddress BaseAddress of the pin.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPin_Init(XPm_PinNode *Pin, u32 PinId, u32 BaseAddress)
{
XStatus Status = XST_FAILURE;
u32 PinIdx;
PinIdx = NODEINDEX(PinId);
if (PinIdx >= (u32)XPM_NODEIDX_STMIC_MAX) {
goto done;
}
XPmNode_Init(&Pin->Node, PinId, (u8)XPM_PINSTATE_UNUSED, BaseAddress);
Pin->Groups = PmPinGroups[PinIdx].GroupList;
Pin->NumGroups = (u8)(PmPinGroups[PinIdx].GroupCount);
Pin->PinFunc = NULL;
Pin->SubsysIdx = (u16)NODEINDEX(INVALID_SUBSYSID);
if (PinIdx <= PINS_PER_BANK) {
Pin->Bank = 0;
} else {
Pin->Bank = (u8)((PinIdx - PINS_PER_BANK - 1U) / PINS_PER_BANK);
}
Pin->BiasStatus = (u8)PINCTRL_BIAS_ENABLE;
Pin->PullCtrl = (u8)PINCTRL_BIAS_PULL_UP;
Pin->TriState = (u8)PINCTRL_TRI_STATE_ENABLE;
PmMioPins[PinIdx] = Pin;
PmNumPins++;
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function returns instance to XPm_PinNode based on PinId.
*
* @param PinId PinNode ID.
*
* @return Instance of XPm_PinNode if successful else NULL.
*
****************************************************************************/
XPm_PinNode *XPmPin_GetById(u32 PinId)
{
XPm_PinNode *PinNode = NULL;
u32 PinIndex = NODEINDEX(PinId);
if ((u32)XPM_NODECLASS_STMIC != NODECLASS(PinId)) {
goto done;
} else if ((u32)XPM_NODESUBCL_PIN != NODESUBCLASS(PinId)) {
goto done;
} else if (((u32)XPM_NODETYPE_LPD_MIO != NODETYPE(PinId)) &&
((u32)XPM_NODETYPE_PMC_MIO != NODETYPE(PinId))) {
goto done;
} else if (PinIndex >= (u32)XPM_NODEIDX_STMIC_MAX) {
goto done;
} else {
/* Required by MISRA */
}
PinNode = PmMioPins[PinIndex];
done:
return PinNode;
}
/****************************************************************************/
/**
* @brief This function sets pin function on given pin.
*
* @param PinId Pin ID.
* @param FuncId Function ID.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPin_SetPinFunction(u32 PinId, u32 FuncId)
{
XStatus Status = XST_FAILURE;
XPm_PinNode *Pin;
XPm_PinFunc *PinFunc;
Pin = XPmPin_GetById(PinId);
if (NULL == Pin) {
Status = XST_INVALID_PARAM;
goto done;
}
PinFunc = XPmPinFunc_GetById(FuncId);
if ((NULL == PinFunc) || (0U == ValidatePinFunc(Pin, PinFunc))) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((u32)XPM_NODETYPE_LPD_MIO == NODETYPE(PinId)) {
PmOut32(Pin->Node.BaseAddress + PINNUM(Pin->Node.Id) * 4U, PinFunc->LmioRegMask);
} else if ((u32)XPM_NODETYPE_PMC_MIO == NODETYPE(PinId)) {
PmOut32(Pin->Node.BaseAddress + PINNUM(Pin->Node.Id) * 4U, PinFunc->PmioRegMask);
} else {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Pin->PinFunc = PinFunc;
Pin->Node.State = (u8)XPM_PINSTATE_ASSIGNED;
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function returns pin function on given pin.
*
* @param PinId Pin ID.
* @param FuncId Function ID.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPin_GetPinFunction(u32 PinId, u32 *FuncId)
{
XStatus Status = XST_FAILURE;
XPm_PinNode *Pin;
Pin = XPmPin_GetById(PinId);
if (NULL == Pin) {
Status = XST_INVALID_PARAM;
goto done;
} else if (NULL == Pin->PinFunc) {
*FuncId = INVALID_FUNC_ID;
Status = XST_SUCCESS;
} else {
*FuncId = Pin->PinFunc->Id;
Status = XST_SUCCESS;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function sets pin configuration on given pin.
*
* @param PinId Pin ID.
* @param Param Configuration parameter type.
* @param Value Configuration parameter value.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPin_SetPinConfig(u32 PinId, u32 Param, u32 Value)
{
XStatus Status = XST_FAILURE;
XPm_PinNode *Pin;
u32 BitMask, BaseAddr;
u32 RegPuAddr, RegPdAddr;
Pin = XPmPin_GetById(PinId);
if (NULL == Pin) {
Status = XST_INVALID_PARAM;
goto done;
} else {
/* Required by MISRA */
}
BitMask = (u32)1U << (PINNUM(Pin->Node.Id) % PINS_PER_BANK);
BaseAddr = Pin->Node.BaseAddress + ((Pin->Bank) * ((u32)BNK_OFFSET));
switch (Param) {
case (u32)PINCTRL_CONFIG_SLEW_RATE:
if ((u32)PINCTRL_SLEW_RATE_SLOW == Value) {
XPm_RMW32((BaseAddr + SEL_SLEW), BitMask, 0);
} else if ((u32)PINCTRL_SLEW_RATE_FAST == Value) {
XPm_RMW32((BaseAddr + SEL_SLEW), BitMask, BitMask);
} else {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_BIAS_STATUS:
RegPuAddr = BaseAddr + EN_WK_PU;
RegPdAddr = BaseAddr + EN_WK_PD;
if (((u32)PINCTRL_BIAS_ENABLE != Value) &&
((u32)PINCTRL_BIAS_DISABLE != Value)) {
Status = XST_INVALID_PARAM;
goto done;
}
if (((u32)PINCTRL_BIAS_ENABLE == Value) &&
((u32)PINCTRL_BIAS_DISABLE == Pin->BiasStatus)) {
if ((u32)PINCTRL_BIAS_PULL_UP == Pin->PullCtrl) {
PmRmw32(RegPuAddr, BitMask, BitMask);
} else {
PmRmw32(RegPdAddr, BitMask, BitMask);
}
} else if (((u32)PINCTRL_BIAS_DISABLE == Value) &&
((u32)PINCTRL_BIAS_ENABLE == Pin->BiasStatus)) {
PmRmw32(RegPdAddr, BitMask, 0);
PmRmw32(RegPuAddr, BitMask, 0);
} else {
/* Required by MISRA */
}
Pin->BiasStatus = (u8)Value;
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_PULL_CTRL:
RegPuAddr = BaseAddr + EN_WK_PU;
RegPdAddr = BaseAddr + EN_WK_PD;
if ((u32)PINCTRL_BIAS_ENABLE == Pin->BiasStatus) {
if ((u32)PINCTRL_BIAS_PULL_UP == Value) {
/* Disable weak pull-down */
PmRmw32(RegPdAddr, BitMask, 0);
/* Enable weak pull-up */
PmRmw32(RegPuAddr, BitMask, BitMask);
} else if ((u32)PINCTRL_BIAS_PULL_DOWN == Value) {
/* Disable weak pull-up */
PmRmw32(RegPuAddr, BitMask, 0);
/* Enable weak pull-down */
PmRmw32(RegPdAddr, BitMask, BitMask);
} else {
Status = XST_INVALID_PARAM;
goto done;
}
}
Pin->PullCtrl = (u8)Value;
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_SCHMITT_CMOS:
if ((u32)PINCTRL_INPUT_TYPE_CMOS == Value) {
PmRmw32((BaseAddr + EN_RX_SCHMITT_HYST), BitMask, 0);
} else if ((u32)PINCTRL_INPUT_TYPE_SCHMITT == Value) {
PmRmw32((BaseAddr + EN_RX_SCHMITT_HYST), BitMask, BitMask);
} else {
Status = XST_INVALID_PARAM;
goto done;
}
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_DRIVE_STRENGTH:
if (Value >= (u32)PINCTRL_DRIVE_STRENGTH_MAX) {
Status = XST_INVALID_PARAM;
goto done;
}
if ((PINNUM(Pin->Node.Id) * SEL_DRV_WIDTH) < BITS_IN_REG) {
Value <<= PINNUM(Pin->Node.Id);
BitMask = SEL_DRV0_MASK(Pin->Node.Id);
PmRmw32((BaseAddr + SEL_DRV0), BitMask, Value);
} else {
Value <<= (PINNUM(Pin->Node.Id) - (BITS_IN_REG / SEL_DRV_WIDTH));
BitMask = SEL_DRV1_MASK(Pin->Node.Id);
PmRmw32((BaseAddr + SEL_DRV1), BitMask, Value);
}
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_TRI_STATE:
if ((u32)XPM_NODETYPE_LPD_MIO == NODETYPE(Pin->Node.Id)) {
BaseAddr = Pin->Node.BaseAddress + TRI_STATE + 4U;
} else {
BaseAddr = Pin->Node.BaseAddress + TRI_STATE + ((Pin->Bank) * 4U);
}
if (Value == (u32)PINCTRL_TRI_STATE_ENABLE) {
PmRmw32(BaseAddr, BitMask, BitMask);
} else if (Value == (u32)PINCTRL_TRI_STATE_DISABLE) {
/* Add check to make sure that domain is powered on */
PmRmw32(BaseAddr, BitMask, 0);
} else {
Status = XST_INVALID_PARAM;
goto done;
}
Pin->TriState = (u8)Value;
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function returns pin configuration of given pin.
*
* @param PinId Pin ID.
* @param Param Configuration parameter type.
* @param Value Configuration parameter value.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPin_GetPinConfig(u32 PinId, u32 Param, u32 *Value)
{
XStatus Status = XST_FAILURE;
XPm_PinNode *Pin;
u32 BitMask;
u32 Reg;
u32 BaseAddr;
Pin = XPmPin_GetById(PinId);
if (NULL == Pin) {
Status = XST_INVALID_PARAM;
goto done;
} else {
/* Required by MISRA */
}
BitMask = (u32)1U << (PINNUM(Pin->Node.Id) % PINS_PER_BANK);
BaseAddr = Pin->Node.BaseAddress + ((Pin->Bank) * ((u32)BNK_OFFSET));
switch (Param) {
case (u32)PINCTRL_CONFIG_SLEW_RATE:
PmIn32((BaseAddr + SEL_SLEW), Reg);
if (BitMask == (Reg & BitMask)) {
*Value = (u32)PINCTRL_SLEW_RATE_FAST;
} else {
*Value = (u32)PINCTRL_SLEW_RATE_SLOW;
}
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_BIAS_STATUS:
*Value = Pin->BiasStatus;
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_PULL_CTRL:
*Value = Pin->PullCtrl;
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_SCHMITT_CMOS:
PmIn32((BaseAddr + EN_RX_SCHMITT_HYST), Reg);
if (0U == (Reg & BitMask)) {
*Value = (u32)PINCTRL_INPUT_TYPE_CMOS;
} else {
*Value = (u32)PINCTRL_INPUT_TYPE_SCHMITT;
}
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_DRIVE_STRENGTH:
if ((PINNUM(Pin->Node.Id) * SEL_DRV_WIDTH) < BITS_IN_REG) {
BitMask = SEL_DRV0_MASK(Pin->Node.Id);
PmIn32((BaseAddr + SEL_DRV0), *Value);
*Value &= BitMask;
*Value >>= PINNUM(Pin->Node.Id);
} else {
BitMask = SEL_DRV1_MASK(Pin->Node.Id);
PmIn32((BaseAddr + SEL_DRV1), *Value);
*Value &= BitMask;
*Value >>= (PINNUM(Pin->Node.Id) - (BITS_IN_REG / SEL_DRV_WIDTH));
}
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_VOLTAGE_STATUS:
PmIn32((BaseAddr + VMODE), *Value);
*Value &= VMODE_MASK;
Status = XST_SUCCESS;
break;
case (u32)PINCTRL_CONFIG_TRI_STATE:
*Value = Pin->TriState;
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function returns total number of pins added.
*
* @param NumPins Number of pins.
*
* @return XST_SUCCESS.
*
****************************************************************************/
XStatus XPmPin_GetNumPins(u32 *NumPins)
{
*NumPins = PmNumPins;
return XST_SUCCESS;
}
/****************************************************************************/
/**
* @brief This function returns groups present in pin based on
* pin ID. Index 0 returns the first 6 group IDs, index 6
* returns the next 6 group IDs, and so forth.
*
* @param PinId Pin ID.
* @param Index Index of next function groups
* @param Groups Function groups.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPin_GetPinGroups(u32 PinId, u32 Index, u16 *Groups)
{
XStatus Status = XST_FAILURE;
u32 i;
u32 NumRead;
XPm_PinNode *Pin;
Pin = XPmPin_GetById(PinId);
(void)memset(Groups, (s32)END_OF_GRP, (MAX_GROUPS_PER_RES * sizeof(u16)));
if (NULL == Pin) {
Status = XST_INVALID_PARAM;
goto done;
} else {
/* Required by MISRA */
}
/* Read up to 6 group IDs from Index */
if ((Pin->NumGroups - Index) > MAX_GROUPS_PER_RES) {
NumRead = MAX_GROUPS_PER_RES;
} else {
NumRead = Pin->NumGroups - Index;
}
for (i = 0; i < NumRead; i++) {
Groups[i] = Pin->Groups[i + Index];
}
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function requests pin.
*
* @param SubsystemId Subsystem ID.
* @param PinId Pin ID.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPin_Request(const u32 SubsystemId, const u32 PinId)
{
XStatus Status = XST_FAILURE;
XPm_PinNode *Pin;
Pin = XPmPin_GetById(PinId);
if (NULL == Pin) {
Status = XST_INVALID_PARAM;
goto done;
}
if (Pin->SubsysIdx != (u16)NODEINDEX(INVALID_SUBSYSID)) {
if (Pin->SubsysIdx == NODEINDEX(SubsystemId)) {
goto done;
}
Status = XPM_PM_NO_ACCESS;
goto done;
}
Pin->SubsysIdx = (u16)(NODEINDEX(SubsystemId));
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function releases pin.
*
* @param SubsystemId Subsystem ID.
* @param PinId Pin ID.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPin_Release(const u32 SubsystemId, const u32 PinId)
{
XStatus Status = XST_FAILURE;
XPm_PinNode *Pin;
Pin = XPmPin_GetById(PinId);
if (NULL == Pin) {
Status = XST_INVALID_PARAM;
goto done;
}
if (Pin->SubsysIdx != NODEINDEX(SubsystemId)) {
Status = XST_FAILURE;
goto done;
}
Pin->SubsysIdx = (u16)NODEINDEX(INVALID_SUBSYSID);
Status = XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief This function checks permission for given pin. If subsystem
* requested this pin it returns success else error code.
*
* @param SubsystemId Subsystem ID.
* @param PinId Pin ID.
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
****************************************************************************/
XStatus XPmPin_CheckPerms(const u32 SubsystemId, const u32 PinId)
{
XStatus Status = XST_FAILURE;
XPm_PinNode *Pin;
Pin = XPmPin_GetById(PinId);
if (NULL == Pin) {
Status = XST_INVALID_PARAM;
goto done;
}
if (Pin->SubsysIdx != NODEINDEX(SubsystemId)) {
Status = XPM_PM_NO_ACCESS;
goto done;
}
Status = XST_SUCCESS;
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_6/src/xsysmonpsu_sinit.c
/******************************************************************************
* Copyright (C) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsysmonpsu_sinit.c
* @addtogroup sysmonpsu_v2_6
*
* This file contains the implementation of the XSysMonPsu driver's static
* initialization functionality.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.0 kvn 12/15/15 First release.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsysmonpsu.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern XSysMonPsu_Config XSysMonPsu_ConfigTable[XPAR_XSYSMONPSU_NUM_INSTANCES];
/*****************************************************************************/
/**
*
* This function looks for the device configuration based on the unique device
* ID. The table XSysmonPsu_ConfigTable[] contains the configuration information
* for each device in the system.
*
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
*
******************************************************************************/
XSysMonPsu_Config *XSysMonPsu_LookupConfig(u16 DeviceId)
{
XSysMonPsu_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; Index < (u32)XPAR_XSYSMONPSU_NUM_INSTANCES; Index++) {
if (XSysMonPsu_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XSysMonPsu_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
<file_sep>/c_drivers/drivers/cmd_handler.c
#include "cmd_handler.h"
#include "uart.h"
#include "gpio.h"
#include "rf.h"
//#define DEBUG_PRINT
//localparam [7:0] command_reset_clock = 0,
/// command_send_pulse = 1,
// command_set_period = 2,
// command_set_phase_meas_mode = 3,
// command_reset_phase_meas_mode = 4;
//Command definitions for this code and the RTL module
#define CMD_PREAMBLE 0xAA
#define CMD_RST_CLK 0x00
#define CMD_SEND_PULSE 0x01
#define CMD_SET_PERIOD 0x02
#define CMD_PHASE_MEAS_ON 0x03
#define CMD_PHASE_MEAS_OFF 0x04
#define CMD_PING_BOARD 0xFE
#define CMD_TOGGLE_PHASE_MEAS 0x05
#define CMD_QUEUE_PULSE 0xFD
#define CMD_SYNC_AND_STREAM 0x06
#define CMD_CLEAR_QUEUE 0x07
#define CMD_SET_AMPLITUDE 0x08
#define CMD_SET_PULSE_LEN 0x09
#define CMD_GET_BUSY 0x0A
//Handler function states
#define STATE_WAIT_PREAMBLE 0
#define STATE_WAIT_CMD 1
#define STATE_WAIT_PAYLOAD 2
u8 cmd_state;
u8 curr_cmd;
u8 ack_byte;
//Initializes UART, GPIO and RFSOC
//Returns 0 on success
u8 cmd_init()
{
cmd_state = 0;
print("Initializing peripherals...\r\n");
if(gpio_init())
{
print("Failed to initialize GPIO!\r\n");
return 1;
}
else
{
print("Successfully initialized GPIO!\r\n");
}
if(uart_init_interrupt() != 0)
{
print("Failed to initialize UART!\r\n");
return 1;
}
else
{
print("Successfully initialized UART!\r\n");
}
if(rf_init())
{
print("Failed to initialize RF components!\r\n");
}
else
{
print("Successfully initialized RF components!\r\n");
}
print("Finished initializing peripherals\r\n");
//Clear the buffer once
uart_clear_buffer();
if(get_rf_clock_status())
{
print("No running clock detected in RF section\r\n");
}
else
{
print("Clock for RF section is running\r\n");
}
return 0;
}
void debug_print(char* str);
//Main command handler function
void cmd_update_state()
{
ack_byte = get_rf_clock_status();
switch(cmd_state)
{
case STATE_WAIT_PREAMBLE:
//Check to see if there is a preamble byte waiting
if(uart_get_buffer_size())
{
//Check to see if the byte is correct
u8 p_b = uart_get_buffer_byte();
if(p_b == CMD_PREAMBLE)
{
//Preamble byte is correct, we can move on to the next state
cmd_state = STATE_WAIT_CMD;
}
else
{
xil_printf("Got bad preamble byte: 0x%x\r\n", p_b);
}
}
break;
case STATE_WAIT_CMD:
//Check to see if there is a command byte waiting
if(uart_get_buffer_size())
{
//Decode the command
curr_cmd = uart_get_buffer_byte();
switch(curr_cmd)
{
case CMD_RST_CLK:
//Send the clock reset command
gpio_send_command( ((u32)CMD_RST_CLK) << 24);
uart_send_byte(ack_byte);//Send an ACK
cmd_state = STATE_WAIT_PREAMBLE;
debug_print("Resetting the clock");
break;
//These are handled in the same manner
case CMD_SEND_PULSE:
case CMD_SET_PERIOD:
case CMD_TOGGLE_PHASE_MEAS:
case CMD_SYNC_AND_STREAM:
case CMD_QUEUE_PULSE:
case CMD_SET_AMPLITUDE:
case CMD_SET_PULSE_LEN:
//Handle these in their own FMS state
cmd_state = STATE_WAIT_PAYLOAD;
break;
case CMD_PHASE_MEAS_ON:
//Send the set phase meas command
gpio_send_command( ((u32)CMD_PHASE_MEAS_ON) << 24);
uart_send_byte(ack_byte);//Send an ACK
cmd_state = STATE_WAIT_PREAMBLE;
debug_print("Turning on phase measurement mode");
break;
case CMD_PHASE_MEAS_OFF:
//Send the set phase meas command
gpio_send_command( ((u32)CMD_PHASE_MEAS_OFF) << 24);
uart_send_byte(ack_byte);//Send an ACK
cmd_state = STATE_WAIT_PREAMBLE;
debug_print("Turning off phase measurement mode");
break;
case CMD_PING_BOARD:
uart_send_byte(ack_byte);//Send an ACK
debug_print("Responding to ping");
cmd_state = STATE_WAIT_PREAMBLE;
break;
case CMD_CLEAR_QUEUE:
//Send the set phase meas command
gpio_send_command( ((u32)CMD_CLEAR_QUEUE) << 24);
cmd_state = STATE_WAIT_PREAMBLE;
uart_send_byte(ack_byte);//Send an ACK
debug_print("Clearing pulse queue");
break;
case CMD_GET_BUSY:
uart_send_byte(gpio_get_busy());
cmd_state = STATE_WAIT_PREAMBLE;//Go back to waiting for next command
debug_print("Sending busy state");
break;
default:
xil_printf("Invalid command byte: 0x%x\r\n", curr_cmd);
cmd_state = STATE_WAIT_PREAMBLE;
break;
}
}
break;
case STATE_WAIT_PAYLOAD:
//Check if we have 3 payload bytes yet
if(uart_get_buffer_size() >= 3)
{
u32 b0, b1, b2;
b0 = uart_get_buffer_byte();
b1 = uart_get_buffer_byte();
b2 = uart_get_buffer_byte();
u32 cmd_f = (((u32)curr_cmd) << 24) | (b0 << 16) | (b1 << 8) | b2;
if(curr_cmd == CMD_QUEUE_PULSE)
{
gpio_queue_pulse(cmd_f);
}
else{
gpio_send_command(cmd_f);//Send the command to the fifo
}
uart_send_byte(ack_byte);//Send an ACK
cmd_state = STATE_WAIT_PREAMBLE;
#ifdef DEBUG_PRINT
xil_printf("Executing: 0x%x, with args 0x%x, 0x%x, 0x%x\r\n", curr_cmd, b0, b1, b2);
#endif
}
break;
}
}
void debug_print(char* str)
{
#ifdef DEBUG_PRINT
print(str);
print("\r\n");
#endif
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/pm_defs.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file pm_defs.h
*
* PM Definitions implementation
* @addtogroup xpm_apis XilPM APIs
* @{
*****************************************************************************/
#ifndef PM_DEFS_H_
#define PM_DEFS_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @name PM Version Number macros
*
* @{
*/
#define PM_VERSION_MAJOR 1
#define PM_VERSION_MINOR 1
#define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR)
/**@}*/
/** @name Capabilities for RAM
*
* @{
*/
#define PM_CAP_ACCESS 0x1U
#define PM_CAP_CONTEXT 0x2U
#define PM_CAP_WAKEUP 0x4U
/**@}*/
/** @name Node default states macros
*
* @{
*/
#define NODE_STATE_OFF 0
#define NODE_STATE_ON 1
/**@}*/
/** @name Processor's states macros
*
* @{
*/
#define PROC_STATE_FORCEDOFF 0
#define PROC_STATE_ACTIVE 1
#define PROC_STATE_SLEEP 2
#define PROC_STATE_SUSPENDING 3
/**@}*/
/** @name Maximum Latency/QOS macros
*
* @{
*/
#define MAX_LATENCY (~0U)
#define MAX_QOS 100U
/**@}*/
/** @name System shutdown/Restart macros
*
* @{
*/
#define PMF_SHUTDOWN_TYPE_SHUTDOWN 0U
#define PMF_SHUTDOWN_TYPE_RESET 1U
#define PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM 0U
#define PMF_SHUTDOWN_SUBTYPE_PS_ONLY 1U
#define PMF_SHUTDOWN_SUBTYPE_SYSTEM 2U
/**@}*/
#define PM_CLOCK_DIV0_ID 0U
#define PM_CLOCK_DIV1_ID 1U
/**
* APIs for Miscellaneous functions, suspending of PUs, managing PM slaves and Direct control.
*/
enum XPmApiId {
/* Miscellaneous API functions: */
PM_GET_API_VERSION = 1, /* Do not change or move */
PM_SET_CONFIGURATION,
PM_GET_NODE_STATUS,
PM_GET_OP_CHARACTERISTIC,
PM_REGISTER_NOTIFIER,
/* API for suspending of PUs: */
PM_REQUEST_SUSPEND,
PM_SELF_SUSPEND,
PM_FORCE_POWERDOWN,
PM_ABORT_SUSPEND,
PM_REQUEST_WAKEUP,
PM_SET_WAKEUP_SOURCE,
PM_SYSTEM_SHUTDOWN,
/*API for managing PM slaves: */
PM_REQUEST_NODE,
PM_RELEASE_NODE,
PM_SET_REQUIREMENT,
PM_SET_MAX_LATENCY,
/* Direct control API functions: */
PM_RESET_ASSERT,
PM_RESET_GET_STATUS,
PM_MMIO_WRITE,
PM_MMIO_READ,
PM_INIT_FINALIZE,
PM_FPGA_LOAD,
PM_FPGA_GET_STATUS,
PM_GET_CHIPID,
/* Secure library generic API functions */
PM_SECURE_SHA = 26U,
PM_SECURE_RSA,
PM_PINCTRL_REQUEST,
PM_PINCTRL_RELEASE,
PM_PINCTRL_GET_FUNCTION,
PM_PINCTRL_SET_FUNCTION,
PM_PINCTRL_CONFIG_PARAM_GET,
PM_PINCTRL_CONFIG_PARAM_SET,
/* PM IOCTL API */
PM_IOCTL,
/* API to query information from firmware */
PM_QUERY_DATA,
/* Clock control API functions */
PM_CLOCK_ENABLE,
PM_CLOCK_DISABLE,
PM_CLOCK_GETSTATE,
PM_CLOCK_SETDIVIDER,
PM_CLOCK_GETDIVIDER,
PM_CLOCK_SETRATE,
PM_CLOCK_GETRATE,
PM_CLOCK_SETPARENT,
PM_CLOCK_GETPARENT,
/* Secure image */
PM_SECURE_IMAGE,
PM_FPGA_READ,
PM_SECURE_AES,
/* PLL direct control API functions */
PM_PLL_SET_PARAMETER,
PM_PLL_GET_PARAMETER,
PM_PLL_SET_MODE,
PM_PLL_GET_MODE,
PM_REGISTER_ACCESS,
PM_EFUSE_ACCESS,
PM_API_MAX
};
/** @name PM API Min and Max macros
*
* @{
*/
#define PM_API_MIN PM_GET_API_VERSION
/**@}*/
/**
* PM API Callback Id Enum
*/
enum XPmApiCbId {
PM_INIT_SUSPEND_CB = 30,
PM_ACKNOWLEDGE_CB,
PM_NOTIFY_CB,
PM_NOTIFY_STL_NO_OP
};
/**
* PM Node ID Enum
*/
enum XPmNodeId {
NODE_UNKNOWN,
NODE_APU,
NODE_APU_0,
NODE_APU_1,
NODE_APU_2,
NODE_APU_3,
NODE_RPU,
NODE_RPU_0,
NODE_RPU_1,
NODE_PLD,
NODE_FPD,
NODE_OCM_BANK_0,
NODE_OCM_BANK_1,
NODE_OCM_BANK_2,
NODE_OCM_BANK_3,
NODE_TCM_0_A,
NODE_TCM_0_B,
NODE_TCM_1_A,
NODE_TCM_1_B,
NODE_L2,
NODE_GPU_PP_0,
NODE_GPU_PP_1,
NODE_USB_0,
NODE_USB_1,
NODE_TTC_0,
NODE_TTC_1,
NODE_TTC_2,
NODE_TTC_3,
NODE_SATA,
NODE_ETH_0,
NODE_ETH_1,
NODE_ETH_2,
NODE_ETH_3,
NODE_UART_0,
NODE_UART_1,
NODE_SPI_0,
NODE_SPI_1,
NODE_I2C_0,
NODE_I2C_1,
NODE_SD_0,
NODE_SD_1,
NODE_DP,
NODE_GDMA,
NODE_ADMA,
NODE_NAND,
NODE_QSPI,
NODE_GPIO,
NODE_CAN_0,
NODE_CAN_1,
NODE_EXTERN,
NODE_APLL,
NODE_VPLL,
NODE_DPLL,
NODE_RPLL,
NODE_IOPLL,
NODE_DDR,
NODE_IPI_APU,
NODE_IPI_RPU_0,
NODE_GPU,
NODE_PCIE,
NODE_PCAP,
NODE_RTC,
NODE_LPD,
NODE_VCU,
NODE_IPI_RPU_1,
NODE_IPI_PL_0,
NODE_IPI_PL_1,
NODE_IPI_PL_2,
NODE_IPI_PL_3,
NODE_PL,
NODE_ID_MAX
};
/**
* PM Acknowledge Request Types
*/
enum XPmRequestAck {
REQUEST_ACK_NO = 1,
REQUEST_ACK_BLOCKING,
REQUEST_ACK_NON_BLOCKING,
REQUEST_ACK_CB_CERROR,
};
/**
* PM Abort Reasons Enum
*/
enum XPmAbortReason {
ABORT_REASON_WKUP_EVENT = 100,
ABORT_REASON_PU_BUSY,
ABORT_REASON_NO_PWRDN,
ABORT_REASON_UNKNOWN,
};
/**
* PM Suspend Reasons Enum
*/
enum XPmSuspendReason {
SUSPEND_REASON_PU_REQ = 201,
SUSPEND_REASON_ALERT,
SUSPEND_REASON_SYS_SHUTDOWN,
};
/**
* PM RAM States Enum
*/
enum XPmRamState {
PM_RAM_STATE_OFF = 0,
PM_RAM_STATE_RETENTION,
PM_RAM_STATE_ON,
};
/**
* PM Operating Characteristic types Enum
*/
enum XPmOpCharType {
PM_OPCHAR_TYPE_POWER = 1,
PM_OPCHAR_TYPE_TEMP,
PM_OPCHAR_TYPE_LATENCY,
};
/* Power management specific return error statuses */
/** @defgroup pmstatmacro
* @{
*/
/** An internal error occurred while performing the requested operation */
#define XST_PM_INTERNAL 2000L
/** Conflicting requirements have been asserted when more than one processing
* cluster is using the same PM slave */
#define XST_PM_CONFLICT 2001L
/** The processing cluster does not have access to the requested node or
* operation */
#define XST_PM_NO_ACCESS 2002L
/** The API function does not apply to the node passed as argument */
#define XST_PM_INVALID_NODE 2003L
/** A processing cluster has already been assigned access to a PM slave and
* has issued a duplicate request for that PM slave */
#define XST_PM_DOUBLE_REQ 2004L
/** The target processing cluster has aborted suspend */
#define XST_PM_ABORT_SUSPEND 2005L
/** A timeout occurred while performing the requested operation*/
#define XST_PM_TIMEOUT 2006L
/** Slave request cannot be granted since node is non-shareable and used */
#define XST_PM_NODE_USED 2007L
/**@}*/
/**
* Boot Status Enum
*/
enum XPmBootStatus {
PM_INITIAL_BOOT, /* boot is a fresh system startup */
PM_RESUME, /* boot is a resume */
PM_BOOT_ERROR, /* error, boot cause cannot be identified */
};
/**
* PM Reset Action types
*/
enum XPmResetAction {
XILPM_RESET_ACTION_RELEASE,
XILPM_RESET_ACTION_ASSERT,
XILPM_RESET_ACTION_PULSE,
};
/**
* PM Reset Line IDs
*/
enum XPmReset {
XILPM_RESET_PCIE_CFG = 1000,
XILPM_RESET_PCIE_BRIDGE,
XILPM_RESET_PCIE_CTRL,
XILPM_RESET_DP,
XILPM_RESET_SWDT_CRF,
XILPM_RESET_AFI_FM5,
XILPM_RESET_AFI_FM4,
XILPM_RESET_AFI_FM3,
XILPM_RESET_AFI_FM2,
XILPM_RESET_AFI_FM1,
XILPM_RESET_AFI_FM0,
XILPM_RESET_GDMA,
XILPM_RESET_GPU_PP1,
XILPM_RESET_GPU_PP0,
XILPM_RESET_GPU,
XILPM_RESET_GT,
XILPM_RESET_SATA,
XILPM_RESET_ACPU3_PWRON,
XILPM_RESET_ACPU2_PWRON,
XILPM_RESET_ACPU1_PWRON,
XILPM_RESET_ACPU0_PWRON,
XILPM_RESET_APU_L2,
XILPM_RESET_ACPU3,
XILPM_RESET_ACPU2,
XILPM_RESET_ACPU1,
XILPM_RESET_ACPU0,
XILPM_RESET_DDR,
XILPM_RESET_APM_FPD,
XILPM_RESET_SOFT,
XILPM_RESET_GEM0,
XILPM_RESET_GEM1,
XILPM_RESET_GEM2,
XILPM_RESET_GEM3,
XILPM_RESET_QSPI,
XILPM_RESET_UART0,
XILPM_RESET_UART1,
XILPM_RESET_SPI0,
XILPM_RESET_SPI1,
XILPM_RESET_SDIO0,
XILPM_RESET_SDIO1,
XILPM_RESET_CAN0,
XILPM_RESET_CAN1,
XILPM_RESET_I2C0,
XILPM_RESET_I2C1,
XILPM_RESET_TTC0,
XILPM_RESET_TTC1,
XILPM_RESET_TTC2,
XILPM_RESET_TTC3,
XILPM_RESET_SWDT_CRL,
XILPM_RESET_NAND,
XILPM_RESET_ADMA,
XILPM_RESET_GPIO,
XILPM_RESET_IOU_CC,
XILPM_RESET_TIMESTAMP,
XILPM_RESET_RPU_R50,
XILPM_RESET_RPU_R51,
XILPM_RESET_RPU_AMBA,
XILPM_RESET_OCM,
XILPM_RESET_RPU_PGE,
XILPM_RESET_USB0_CORERESET,
XILPM_RESET_USB1_CORERESET,
XILPM_RESET_USB0_HIBERRESET,
XILPM_RESET_USB1_HIBERRESET,
XILPM_RESET_USB0_APB,
XILPM_RESET_USB1_APB,
XILPM_RESET_IPI,
XILPM_RESET_APM_LPD,
XILPM_RESET_RTC,
XILPM_RESET_SYSMON,
XILPM_RESET_AFI_FM6,
XILPM_RESET_LPD_SWDT,
XILPM_RESET_FPD,
XILPM_RESET_RPU_DBG1,
XILPM_RESET_RPU_DBG0,
XILPM_RESET_DBG_LPD,
XILPM_RESET_DBG_FPD,
XILPM_RESET_APLL,
XILPM_RESET_DPLL,
XILPM_RESET_VPLL,
XILPM_RESET_IOPLL,
XILPM_RESET_RPLL,
XILPM_RESET_GPO3_PL_0,
XILPM_RESET_GPO3_PL_1,
XILPM_RESET_GPO3_PL_2,
XILPM_RESET_GPO3_PL_3,
XILPM_RESET_GPO3_PL_4,
XILPM_RESET_GPO3_PL_5,
XILPM_RESET_GPO3_PL_6,
XILPM_RESET_GPO3_PL_7,
XILPM_RESET_GPO3_PL_8,
XILPM_RESET_GPO3_PL_9,
XILPM_RESET_GPO3_PL_10,
XILPM_RESET_GPO3_PL_11,
XILPM_RESET_GPO3_PL_12,
XILPM_RESET_GPO3_PL_13,
XILPM_RESET_GPO3_PL_14,
XILPM_RESET_GPO3_PL_15,
XILPM_RESET_GPO3_PL_16,
XILPM_RESET_GPO3_PL_17,
XILPM_RESET_GPO3_PL_18,
XILPM_RESET_GPO3_PL_19,
XILPM_RESET_GPO3_PL_20,
XILPM_RESET_GPO3_PL_21,
XILPM_RESET_GPO3_PL_22,
XILPM_RESET_GPO3_PL_23,
XILPM_RESET_GPO3_PL_24,
XILPM_RESET_GPO3_PL_25,
XILPM_RESET_GPO3_PL_26,
XILPM_RESET_GPO3_PL_27,
XILPM_RESET_GPO3_PL_28,
XILPM_RESET_GPO3_PL_29,
XILPM_RESET_GPO3_PL_30,
XILPM_RESET_GPO3_PL_31,
XILPM_RESET_RPU_LS,
XILPM_RESET_PS_ONLY,
XILPM_RESET_PL,
XILPM_RESET_GPIO5_EMIO_92,
XILPM_RESET_GPIO5_EMIO_93,
XILPM_RESET_GPIO5_EMIO_94,
XILPM_RESET_GPIO5_EMIO_95,
};
/**
* PM Notify Events Enum
*/
enum XPmNotifyEvent {
EVENT_STATE_CHANGE = 1,
EVENT_ZERO_USERS = 2,
};
/**
* PM Clock IDs
*/
enum XPmClock {
PM_CLOCK_IOPLL,
PM_CLOCK_RPLL,
PM_CLOCK_APLL,
PM_CLOCK_DPLL,
PM_CLOCK_VPLL,
PM_CLOCK_IOPLL_TO_FPD,
PM_CLOCK_RPLL_TO_FPD,
PM_CLOCK_APLL_TO_LPD,
PM_CLOCK_DPLL_TO_LPD,
PM_CLOCK_VPLL_TO_LPD,
PM_CLOCK_ACPU,
PM_CLOCK_ACPU_HALF,
PM_CLOCK_DBG_FPD,
PM_CLOCK_DBG_LPD,
PM_CLOCK_DBG_TRACE,
PM_CLOCK_DBG_TSTMP,
PM_CLOCK_DP_VIDEO_REF,
PM_CLOCK_DP_AUDIO_REF,
PM_CLOCK_DP_STC_REF,
PM_CLOCK_GDMA_REF,
PM_CLOCK_DPDMA_REF,
PM_CLOCK_DDR_REF,
PM_CLOCK_SATA_REF,
PM_CLOCK_PCIE_REF,
PM_CLOCK_GPU_REF,
PM_CLOCK_GPU_PP0_REF,
PM_CLOCK_GPU_PP1_REF,
PM_CLOCK_TOPSW_MAIN,
PM_CLOCK_TOPSW_LSBUS,
PM_CLOCK_GTGREF0_REF,
PM_CLOCK_LPD_SWITCH,
PM_CLOCK_LPD_LSBUS,
PM_CLOCK_USB0_BUS_REF,
PM_CLOCK_USB1_BUS_REF,
PM_CLOCK_USB3_DUAL_REF,
PM_CLOCK_USB0,
PM_CLOCK_USB1,
PM_CLOCK_CPU_R5,
PM_CLOCK_CPU_R5_CORE,
PM_CLOCK_CSU_SPB,
PM_CLOCK_CSU_PLL,
PM_CLOCK_PCAP,
PM_CLOCK_IOU_SWITCH,
PM_CLOCK_GEM_TSU_REF,
PM_CLOCK_GEM_TSU,
PM_CLOCK_GEM0_TX,
PM_CLOCK_GEM1_TX,
PM_CLOCK_GEM2_TX,
PM_CLOCK_GEM3_TX,
PM_CLOCK_GEM0_RX,
PM_CLOCK_GEM1_RX,
PM_CLOCK_GEM2_RX,
PM_CLOCK_GEM3_RX,
PM_CLOCK_QSPI_REF,
PM_CLOCK_SDIO0_REF,
PM_CLOCK_SDIO1_REF,
PM_CLOCK_UART0_REF,
PM_CLOCK_UART1_REF,
PM_CLOCK_SPI0_REF,
PM_CLOCK_SPI1_REF,
PM_CLOCK_NAND_REF,
PM_CLOCK_I2C0_REF,
PM_CLOCK_I2C1_REF,
PM_CLOCK_CAN0_REF,
PM_CLOCK_CAN1_REF,
PM_CLOCK_CAN0,
PM_CLOCK_CAN1,
PM_CLOCK_DLL_REF,
PM_CLOCK_ADMA_REF,
PM_CLOCK_TIMESTAMP_REF,
PM_CLOCK_AMS_REF,
PM_CLOCK_PL0_REF,
PM_CLOCK_PL1_REF,
PM_CLOCK_PL2_REF,
PM_CLOCK_PL3_REF,
PM_CLOCK_WDT,
PM_CLOCK_IOPLL_INT,
PM_CLOCK_IOPLL_PRE_SRC,
PM_CLOCK_IOPLL_HALF,
PM_CLOCK_IOPLL_INT_MUX,
PM_CLOCK_IOPLL_POST_SRC,
PM_CLOCK_RPLL_INT,
PM_CLOCK_RPLL_PRE_SRC,
PM_CLOCK_RPLL_HALF,
PM_CLOCK_RPLL_INT_MUX,
PM_CLOCK_RPLL_POST_SRC,
PM_CLOCK_APLL_INT,
PM_CLOCK_APLL_PRE_SRC,
PM_CLOCK_APLL_HALF,
PM_CLOCK_APLL_INT_MUX,
PM_CLOCK_APLL_POST_SRC,
PM_CLOCK_DPLL_INT,
PM_CLOCK_DPLL_PRE_SRC,
PM_CLOCK_DPLL_HALF,
PM_CLOCK_DPLL_INT_MUX,
PM_CLOCK_DPLL_POST_SRC,
PM_CLOCK_VPLL_INT,
PM_CLOCK_VPLL_PRE_SRC,
PM_CLOCK_VPLL_HALF,
PM_CLOCK_VPLL_INT_MUX,
PM_CLOCK_VPLL_POST_SRC,
PM_CLOCK_CAN0_MIO,
PM_CLOCK_CAN1_MIO,
PM_CLOCK_ACPU_FULL,
PM_CLOCK_GEM0_REF,
PM_CLOCK_GEM1_REF,
PM_CLOCK_GEM2_REF,
PM_CLOCK_GEM3_REF,
PM_CLOCK_GEM0_REF_UNGATED,
PM_CLOCK_GEM1_REF_UNGATED,
PM_CLOCK_GEM2_REF_UNGATED,
PM_CLOCK_GEM3_REF_UNGATED,
PM_CLOCK_EXT_PSS_REF,
PM_CLOCK_EXT_VIDEO,
PM_CLOCK_EXT_PSS_ALT_REF,
PM_CLOCK_EXT_AUX_REF,
PM_CLOCK_EXT_GT_CRX_REF,
PM_CLOCK_EXT_SWDT0,
PM_CLOCK_EXT_SWDT1,
PM_CLOCK_EXT_GEM0_TX_EMIO,
PM_CLOCK_EXT_GEM1_TX_EMIO,
PM_CLOCK_EXT_GEM2_TX_EMIO,
PM_CLOCK_EXT_GEM3_TX_EMIO,
PM_CLOCK_EXT_GEM0_RX_EMIO,
PM_CLOCK_EXT_GEM1_RX_EMIO,
PM_CLOCK_EXT_GEM2_RX_EMIO,
PM_CLOCK_EXT_GEM3_RX_EMIO,
PM_CLOCK_EXT_MIO50_OR_MIO51,
PM_CLOCK_EXT_MIO0,
PM_CLOCK_EXT_MIO1,
PM_CLOCK_EXT_MIO2,
PM_CLOCK_EXT_MIO3,
PM_CLOCK_EXT_MIO4,
PM_CLOCK_EXT_MIO5,
PM_CLOCK_EXT_MIO6,
PM_CLOCK_EXT_MIO7,
PM_CLOCK_EXT_MIO8,
PM_CLOCK_EXT_MIO9,
PM_CLOCK_EXT_MIO10,
PM_CLOCK_EXT_MIO11,
PM_CLOCK_EXT_MIO12,
PM_CLOCK_EXT_MIO13,
PM_CLOCK_EXT_MIO14,
PM_CLOCK_EXT_MIO15,
PM_CLOCK_EXT_MIO16,
PM_CLOCK_EXT_MIO17,
PM_CLOCK_EXT_MIO18,
PM_CLOCK_EXT_MIO19,
PM_CLOCK_EXT_MIO20,
PM_CLOCK_EXT_MIO21,
PM_CLOCK_EXT_MIO22,
PM_CLOCK_EXT_MIO23,
PM_CLOCK_EXT_MIO24,
PM_CLOCK_EXT_MIO25,
PM_CLOCK_EXT_MIO26,
PM_CLOCK_EXT_MIO27,
PM_CLOCK_EXT_MIO28,
PM_CLOCK_EXT_MIO29,
PM_CLOCK_EXT_MIO30,
PM_CLOCK_EXT_MIO31,
PM_CLOCK_EXT_MIO32,
PM_CLOCK_EXT_MIO33,
PM_CLOCK_EXT_MIO34,
PM_CLOCK_EXT_MIO35,
PM_CLOCK_EXT_MIO36,
PM_CLOCK_EXT_MIO37,
PM_CLOCK_EXT_MIO38,
PM_CLOCK_EXT_MIO39,
PM_CLOCK_EXT_MIO40,
PM_CLOCK_EXT_MIO41,
PM_CLOCK_EXT_MIO42,
PM_CLOCK_EXT_MIO43,
PM_CLOCK_EXT_MIO44,
PM_CLOCK_EXT_MIO45,
PM_CLOCK_EXT_MIO46,
PM_CLOCK_EXT_MIO47,
PM_CLOCK_EXT_MIO48,
PM_CLOCK_EXT_MIO49,
PM_CLOCK_EXT_MIO50,
PM_CLOCK_EXT_MIO51,
PM_CLOCK_EXT_MIO52,
PM_CLOCK_EXT_MIO53,
PM_CLOCK_EXT_MIO54,
PM_CLOCK_EXT_MIO55,
PM_CLOCK_EXT_MIO56,
PM_CLOCK_EXT_MIO57,
PM_CLOCK_EXT_MIO58,
PM_CLOCK_EXT_MIO59,
PM_CLOCK_EXT_MIO60,
PM_CLOCK_EXT_MIO61,
PM_CLOCK_EXT_MIO62,
PM_CLOCK_EXT_MIO63,
PM_CLOCK_EXT_MIO64,
PM_CLOCK_EXT_MIO65,
PM_CLOCK_EXT_MIO66,
PM_CLOCK_EXT_MIO67,
PM_CLOCK_EXT_MIO68,
PM_CLOCK_EXT_MIO69,
PM_CLOCK_EXT_MIO70,
PM_CLOCK_EXT_MIO71,
PM_CLOCK_EXT_MIO72,
PM_CLOCK_EXT_MIO73,
PM_CLOCK_EXT_MIO74,
PM_CLOCK_EXT_MIO75,
PM_CLOCK_EXT_MIO76,
PM_CLOCK_EXT_MIO77,
};
enum XPmPllParam {
PM_PLL_PARAM_ID_DIV2,
PM_PLL_PARAM_ID_FBDIV,
PM_PLL_PARAM_ID_DATA,
PM_PLL_PARAM_ID_PRE_SRC,
PM_PLL_PARAM_ID_POST_SRC,
PM_PLL_PARAM_ID_LOCK_DLY,
PM_PLL_PARAM_ID_LOCK_CNT,
PM_PLL_PARAM_ID_LFHF,
PM_PLL_PARAM_ID_CP,
PM_PLL_PARAM_ID_RES,
};
enum XPmPllMode {
PM_PLL_MODE_RESET,
PM_PLL_MODE_INTEGER,
PM_PLL_MODE_FRACTIONAL,
};
enum XPmPinFn {
PINCTRL_FUNC_CAN0,
PINCTRL_FUNC_CAN1,
PINCTRL_FUNC_ETHERNET0,
PINCTRL_FUNC_ETHERNET1,
PINCTRL_FUNC_ETHERNET2,
PINCTRL_FUNC_ETHERNET3,
PINCTRL_FUNC_GEMTSU0,
PINCTRL_FUNC_GPIO0,
PINCTRL_FUNC_I2C0,
PINCTRL_FUNC_I2C1,
PINCTRL_FUNC_MDIO0,
PINCTRL_FUNC_MDIO1,
PINCTRL_FUNC_MDIO2,
PINCTRL_FUNC_MDIO3,
PINCTRL_FUNC_QSPI0,
PINCTRL_FUNC_QSPI_FBCLK,
PINCTRL_FUNC_QSPI_SS,
PINCTRL_FUNC_SPI0,
PINCTRL_FUNC_SPI1,
PINCTRL_FUNC_SPI0_SS,
PINCTRL_FUNC_SPI1_SS,
PINCTRL_FUNC_SDIO0,
PINCTRL_FUNC_SDIO0_PC,
PINCTRL_FUNC_SDIO0_CD,
PINCTRL_FUNC_SDIO0_WP,
PINCTRL_FUNC_SDIO1,
PINCTRL_FUNC_SDIO1_PC,
PINCTRL_FUNC_SDIO1_CD,
PINCTRL_FUNC_SDIO1_WP,
PINCTRL_FUNC_NAND0,
PINCTRL_FUNC_NAND0_CE,
PINCTRL_FUNC_NAND0_RB,
PINCTRL_FUNC_NAND0_DQS,
PINCTRL_FUNC_TTC0_CLK,
PINCTRL_FUNC_TTC0_WAV,
PINCTRL_FUNC_TTC1_CLK,
PINCTRL_FUNC_TTC1_WAV,
PINCTRL_FUNC_TTC2_CLK,
PINCTRL_FUNC_TTC2_WAV,
PINCTRL_FUNC_TTC3_CLK,
PINCTRL_FUNC_TTC3_WAV,
PINCTRL_FUNC_UART0,
PINCTRL_FUNC_UART1,
PINCTRL_FUNC_USB0,
PINCTRL_FUNC_USB1,
PINCTRL_FUNC_SWDT0_CLK,
PINCTRL_FUNC_SWDT0_RST,
PINCTRL_FUNC_SWDT1_CLK,
PINCTRL_FUNC_SWDT1_RST,
PINCTRL_FUNC_PMU0,
PINCTRL_FUNC_PCIE0,
PINCTRL_FUNC_CSU0,
PINCTRL_FUNC_DPAUX0,
PINCTRL_FUNC_PJTAG0,
PINCTRL_FUNC_TRACE0,
PINCTRL_FUNC_TRACE0_CLK,
PINCTRL_FUNC_TESTSCAN0,
};
enum XPmPinParam {
PINCTRL_CONFIG_SLEW_RATE,
PINCTRL_CONFIG_BIAS_STATUS,
PINCTRL_CONFIG_PULL_CTRL,
PINCTRL_CONFIG_SCHMITT_CMOS,
PINCTRL_CONFIG_DRIVE_STRENGTH,
PINCTRL_CONFIG_VOLTAGE_STATUS,
};
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* PM_DEFS_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_rpucore.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xil_io.h"
#include "xpm_rpucore.h"
#include "xpm_regs.h"
#include "xpm_api.h"
#include "xpm_subsystem.h"
#include "xpm_psm.h"
XStatus XPmRpuCore_Halt(XPm_Device *Device)
{
XStatus Status = XST_FAILURE;
XPm_RpuCore *RpuCore = (XPm_RpuCore *)Device;
/* RPU should be in reset state before putting it into halt state */
Status = XPmDevice_Reset(&RpuCore->Core.Device, PM_RESET_ACTION_ASSERT);
/* Put RPU in halt state */
PmRmw32(RpuCore->ResumeCfg, XPM_RPU_NCPUHALT_MASK,
~XPM_RPU_NCPUHALT_MASK);
/* Release reset for all resets attached to this core */
Status = XPmDevice_Reset(&RpuCore->Core.Device, PM_RESET_ACTION_RELEASE);
return Status;
}
static int XPmRpuCore_RestoreResumeAddr(XPm_Core *Core)
{
int Status = XST_FAILURE;
XPm_RpuCore *RpuCore = (XPm_RpuCore *)Core;
u32 AddrLow = (u32) (Core->ResumeAddr & 0xffff0000ULL);
/* Check for valid resume address */
if (0U == (Core->ResumeAddr & 1ULL)) {
PmErr("Invalid resume address\r\n");
Status = XST_FAILURE;
goto done;
}
/* CFG_VINITHI_MASK mask is common for both processors */
if (XPM_PROC_RPU_HIVEC_ADDR == AddrLow) {
PmRmw32(RpuCore->ResumeCfg, XPM_RPU_VINITHI_MASK,
XPM_RPU_VINITHI_MASK);
} else {
PmRmw32(RpuCore->ResumeCfg, XPM_RPU_VINITHI_MASK,
~XPM_RPU_VINITHI_MASK);
}
Core->ResumeAddr = 0ULL;
Status = XST_SUCCESS;
done:
return Status;
}
static int XPmRpuCore_HasResumeAddr(XPm_Core *Core)
{
XStatus Status = XST_FAILURE;
if (0U != (Core->ResumeAddr & 1ULL)) {
Status = XST_SUCCESS;
}
return Status;
}
static XStatus XPmRpuCore_WakeUp(XPm_Core *Core, u32 SetAddress, u64 Address)
{
XStatus Status = XST_FAILURE;
XPm_RpuCore *RpuCore = (XPm_RpuCore *)Core;
/* Set reset address */
if (1U == SetAddress) {
Core->ResumeAddr = Address | 1U;
}
Status = XPmCore_WakeUp(Core);
if (XST_SUCCESS != Status) {
PmErr("Core Wake Up failed, Status = %x\r\n", Status);
goto done;
}
/* Release reset for all resets attached to this core */
Status = XPmDevice_Reset(&Core->Device, PM_RESET_ACTION_RELEASE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Put RPU in running state from halt state */
PmRmw32(RpuCore->ResumeCfg, XPM_RPU_NCPUHALT_MASK,
XPM_RPU_NCPUHALT_MASK);
Core->Device.Node.State = (u8)XPM_DEVSTATE_RUNNING;
done:
return Status;
}
static XStatus XPmRpuCore_PwrDwn(XPm_Core *Core)
{
XStatus Status = XST_FAILURE;
Status = XPmRpuCore_Halt((XPm_Device *)Core);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmCore_PwrDwn(Core);
done:
return Status;
}
static struct XPm_CoreOps RpuOps = {
.RestoreResumeAddr = XPmRpuCore_RestoreResumeAddr,
.HasResumeAddr = XPmRpuCore_HasResumeAddr,
.RequestWakeup = XPmRpuCore_WakeUp,
.PowerDown = XPmRpuCore_PwrDwn,
};
XStatus XPmRpuCore_Init(XPm_RpuCore *RpuCore, u32 Id, u32 Ipi, u32 *BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock,
XPm_ResetNode *Reset)
{
XStatus Status = XST_FAILURE;
Status = XPmCore_Init(&RpuCore->Core, Id, Power, Clock, Reset, (u8)Ipi,
&RpuOps);
if (XST_SUCCESS != Status) {
goto done;
}
RpuCore->RpuBaseAddr = BaseAddress[0];
if (PM_DEV_RPU0_0 == Id) {
RpuCore->ResumeCfg = RpuCore->RpuBaseAddr + RPU_0_CFG_OFFSET;
RpuCore->Core.SleepMask = XPM_RPU0_0_PWR_CTRL_MASK;
RpuCore->Core.PwrDwnMask = XPM_RPU_0_CPUPWRDWNREQ_MASK;
} else {
RpuCore->ResumeCfg = RpuCore->RpuBaseAddr + RPU_1_CFG_OFFSET;
RpuCore->Core.SleepMask = XPM_RPU0_1_PWR_CTRL_MASK;
RpuCore->Core.PwrDwnMask = XPM_RPU_1_CPUPWRDWNREQ_MASK;
}
done:
return Status;
}
void XPm_RpuGetOperMode(const u32 DeviceId, u32 *Mode)
{
u32 Val;
XPm_RpuCore *RpuCore = (XPm_RpuCore *)XPmDevice_GetById(DeviceId);
PmIn32(RpuCore->RpuBaseAddr + RPU_GLBL_CNTL_OFFSET, Val);
Val &= XPM_RPU_SLSPLIT_MASK;
if (0U == Val) {
*Mode = XPM_RPU_MODE_LOCKSTEP;
} else {
*Mode = XPM_RPU_MODE_SPLIT;
}
}
void XPm_RpuSetOperMode(const u32 DeviceId, const u32 Mode)
{
u32 Val;
int Status;
XPm_Subsystem *DefSubsystem = XPmSubsystem_GetById(PM_SUBSYS_DEFAULT);
XPm_RpuCore *RpuCore = (XPm_RpuCore *)XPmDevice_GetById(DeviceId);
if (NULL == RpuCore) {
PmErr("Unable to get RPU Core for Id: 0x%x\n\r", DeviceId);
return;
}
PmIn32(RpuCore->RpuBaseAddr + RPU_GLBL_CNTL_OFFSET, Val);
if (Mode == XPM_RPU_MODE_SPLIT) {
Val |= XPM_RPU_SLSPLIT_MASK;
Val &= ~XPM_RPU_TCM_COMB_MASK;
Val &= ~XPM_RPU_SLCLAMP_MASK;
} else if (Mode == XPM_RPU_MODE_LOCKSTEP) {
Val &= ~XPM_RPU_SLSPLIT_MASK;
Val |= XPM_RPU_TCM_COMB_MASK;
Val |= XPM_RPU_SLCLAMP_MASK;
} else {
/* Required by MISRA */
}
PmOut32(RpuCore->RpuBaseAddr + RPU_GLBL_CNTL_OFFSET, Val);
/* Add or remove R50_1 core in default subsystem according to its mode */
if (NULL != DefSubsystem) {
Status = XPmDevice_IsRequested(PM_DEV_RPU0_0,
PM_SUBSYS_DEFAULT);
if ((XST_SUCCESS == Status) &&
((u8)ONLINE == DefSubsystem->State)) {
if (Mode == XPM_RPU_MODE_SPLIT) {
Status = XPmDevice_Request(PM_SUBSYS_DEFAULT,
PM_DEV_RPU0_1,
(u32)PM_CAP_ACCESS,
XPM_MAX_QOS);
if (XST_SUCCESS != Status) {
PmErr("Unable to request RPU 1 Core\n\r");
}
} else if (Mode == XPM_RPU_MODE_LOCKSTEP) {
Status = XPmDevice_IsRequested(PM_DEV_RPU0_1,
PM_SUBSYS_DEFAULT);
if (XST_SUCCESS == Status) {
Status = XPmDevice_Release(PM_SUBSYS_DEFAULT,
PM_DEV_RPU0_1);
if (XST_SUCCESS != Status) {
PmErr("Unable to release RPU 1 Core\n\r");
}
}
} else {
/* Required due to MISRA */
PmDbg("Invalid RPU mode %d\r\n", Mode);
}
}
}
}
XStatus XPm_RpuBootAddrConfig(const u32 DeviceId, const u32 BootAddr)
{
XStatus Status = XST_FAILURE;
XPm_RpuCore *RpuCore = (XPm_RpuCore *)XPmDevice_GetById(DeviceId);
/* CFG_VINITHI_MASK mask is common for both processors */
if (XPM_RPU_BOOTMEM_LOVEC == BootAddr) {
PmRmw32(RpuCore->ResumeCfg, XPM_RPU_VINITHI_MASK,
~XPM_RPU_VINITHI_MASK);
Status = XST_SUCCESS;
} else if (XPM_RPU_BOOTMEM_HIVEC == BootAddr) {
PmRmw32(RpuCore->ResumeCfg, XPM_RPU_VINITHI_MASK,
XPM_RPU_VINITHI_MASK);
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
return Status;
}
XStatus XPm_RpuTcmCombConfig(const u32 DeviceId, const u32 Config)
{
XStatus Status = XST_FAILURE;
u32 Address;
XPm_RpuCore *RpuCore = (XPm_RpuCore *)XPmDevice_GetById(DeviceId);
Address = RpuCore->RpuBaseAddr + RPU_GLBL_CNTL_OFFSET;
if (Config == XPM_RPU_TCM_SPLIT) {
PmRmw32(Address, XPM_RPU_TCM_COMB_MASK,
~XPM_RPU_TCM_COMB_MASK);
Status = XST_SUCCESS;
} else if (Config == XPM_RPU_TCM_COMB) {
PmRmw32(Address, XPM_RPU_TCM_COMB_MASK,
XPM_RPU_TCM_COMB_MASK);
Status = XST_SUCCESS;
} else {
Status = XST_INVALID_PARAM;
}
return Status;
}
XStatus XPm_RpuRstComparators(const u32 DeviceId)
{
XStatus Status = XST_FAILURE;
XPm_RpuCore *RpuCore = NULL;
RpuCore = (XPm_RpuCore *)XPmDevice_GetById(DeviceId);
if(RpuCore == NULL) {
PmInfo("Device Id does not correspond to any RPU Core\n\r");
PmInfo("Invalid Device Id: 0x%x\n\r", DeviceId);
goto done;
}
PmOut32(RpuCore->RpuBaseAddr + RPU_ERR_INJ_OFFSET, 0x0);
Status = XST_SUCCESS;
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilsecure_v4_2/src/versal/xsecure_ecdsa.c
/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_ecdsa.c
*
* This file contains the implementation of the interface functions for ECDSA
* driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 rpo 03/31/2020 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsecure_error.h"
#include "xsecure_ecdsa.h"
#include "xsecure_ecdsa_rsa_hw.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* @brief This function performs known answer test(KAT) on ECDSA core.
*
* @return
* - Returns XST_SUCCESS on success.
* - Returns error code on failure
*
*****************************************************************************/
u32 XSecure_EcdsaKat(void)
{
u32 Status = XSECURE_ECC_KAT_FAILED_ERROR;
u32 QxCord[XSECURE_ECC_DATA_SIZE_WORDS] = {
0x88371BE6U, 0xFD2D8761U, 0x30DA0A10U, 0xEA9DBD2EU,
0x30FB204AU, 0x1361EFBAU, 0xF9FDF2CEU, 0x48405353U,
0xDE06D343U, 0x335DFF33U, 0xCBF43FDFU, 0x6C037A0U
};
u32 QyCord[XSECURE_ECC_DATA_SIZE_WORDS] = {
0xEA662A43U, 0xD380E26EU, 0x57AA933CU, 0x4DD77035U,
0x5891AD86U, 0x7AB634EDU, 0x3E46D080U, 0xD97F2544U,
0xBF70B8A4U, 0x9204B98FU, 0x940E3467U, 0x360D38F3U
};
u32 SignR[XSECURE_ECC_DATA_SIZE_WORDS] = {
0x52D853B5U, 0x41531533U, 0x2D1B4AA6U, 0x6EAF0088U,
0x4E88153DU, 0x9F0AB1AAU, 0x12A416D8U, 0x7A50E599U,
0xB7CA0FA0U, 0x330C7507U, 0x3495767EU, 0x5886078DU
};
u32 SignS[XSECURE_ECC_DATA_SIZE_WORDS] = {
0x7A36E1AAU, 0x329682AEU, 0xE17F691BU, 0xF3869DA0U,
0xE32BDE69U, 0x6F78CDC4U, 0x89C8FF9FU, 0x449A3523U,
0x82CC2114U, 0xFD14B06BU, 0xBF1BF8CCU, 0x2CC10023U
};
u32 HashVal[XSECURE_ECC_DATA_SIZE_WORDS] = {
0x925FA874U, 0x331B36FBU, 0x13173C62U, 0x57633F17U,
0x110BA0CDU, 0x9E3B9A7DU, 0x46DE70D2U, 0xB30870DBU,
0xF3CA965DU, 0xADAA0A68U, 0x9573A993U, 0x1128C8B0U
};
/*
* Take the core out of reset
*/
XSecure_ReleaseReset(XSECURE_ECDSA_RSA_BASEADDR,
XSECURE_ECDSA_RSA_RESET_OFFSET);
Status = P384_validatekey((u8 *)QxCord, (u8 *)QyCord);
if(Status != XST_SUCCESS) {
Status = XSECURE_ECC_KAT_KEY_NOTVALID_ERROR;
goto END;
}
Status = P384_ecdsaverify((u8 *)HashVal, (u8 *)QxCord, (u8 *)QyCord,
(u8 *)SignR, (u8 *)SignS);
if(Status != XST_SUCCESS) {
Status = XSECURE_ECC_KAT_FAILED_ERROR;
goto END;
}
END:
XSecure_SetReset(XSECURE_ECDSA_RSA_BASEADDR,
XSECURE_ECDSA_RSA_RESET_OFFSET);
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_psm_api.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_defs.h"
#include "xpm_psm_api.h"
#include "xplmi_modules.h"
#include "xpm_common.h"
#include "xpm_core.h"
#include "xpm_device.h"
#include "xpm_ipi.h"
#include "xpm_regs.h"
#include "xpm_subsystem.h"
#include "xpm_requirement.h"
#include "sleep.h"
#define PSM_TO_PLM_EVENT_ADDR (0xFFC3FF00U)
#define PSM_TO_PLM_EVENT_VERSION (0x1U)
#define PWR_UP_EVT (0x1U)
#define PWR_DWN_EVT (0x100U)
#ifdef STDOUT_BASEADDRESS
#if (STDOUT_BASEADDRESS == 0xFF000000U)
#define NODE_UART PM_DEV_UART_0 /* Assign node ID with UART0 device ID */
#elif (STDOUT_BASEADDRESS == 0xFF010000U)
#define NODE_UART PM_DEV_UART_1 /* Assign node ID with UART1 device ID */
#endif
#endif
static XPlmi_ModuleCmd XPlmi_PsmCmds[PSM_API_MAX+1];
static XPlmi_Module XPlmi_Psm =
{
XPLMI_MODULE_XILPSM_ID,
XPlmi_PsmCmds,
PSM_API_MAX+1,
};
static u32 ProcDevList[PROC_DEV_MAX] = {
[ACPU_0] = PM_DEV_ACPU_0,
[ACPU_1] = PM_DEV_ACPU_1,
[RPU0_0] = PM_DEV_RPU0_0,
[RPU0_1] = PM_DEV_RPU0_1,
};
/* This replicates PsmToPlmEvent stored at PSM reserved RAM location */
static volatile struct PsmToPlmEvent_t *PsmToPlmEvent =
(struct PsmToPlmEvent_t *)PSM_TO_PLM_EVENT_ADDR;
static int XPm_ProcessPsmCmd(XPlmi_Cmd * Cmd)
{
int Status = XST_FAILURE, EventStatus;
u32 Idx;
XPm_Power *Lpd;
/* Ack the IPI interrupt first */
PmOut32(IPI_PMC_ISR_ADDR, PSM_IPI_BIT);
PmDbg("Processing Psm Event\n\r");
/* Check for the version of the PsmToPlmEvent structure */
if (PsmToPlmEvent->Version != PSM_TO_PLM_EVENT_VERSION) {
PmErr("PSM-PLM are out of sync. Can't process PSM event\n\r");
goto done;
} else {
Status = XST_SUCCESS;
}
Lpd = XPmPower_GetById(PM_POWER_LPD);
if (NULL == Lpd) {
goto done;
}
/* Check for the power up/down event register */
for (Idx = 0; ((u8)XPM_POWER_STATE_OFF != Lpd->Node.State) && Idx < ARRAY_SIZE(ProcDevList); Idx++) {
if (PsmToPlmEvent->Event[Idx] == PWR_UP_EVT) {
/* Clear power up event register bit */
PsmToPlmEvent->Event[Idx] = 0;
EventStatus = XPm_WakeUpEvent(ProcDevList[Idx]);
if (EventStatus != XST_SUCCESS) {
Status = EventStatus;
PmErr("Err %d in wakeup of 0x%x\r\n",
EventStatus, ProcDevList[Idx]);
}
} else if (PsmToPlmEvent->Event[Idx] == PWR_DWN_EVT) {
/* Clear power down event register bit */
PsmToPlmEvent->Event[Idx] = 0;
EventStatus = XPm_PwrDwnEvent(ProcDevList[Idx]);
if (EventStatus != XST_SUCCESS) {
Status = EventStatus;
PmErr("Err %d in powerdown of 0x%x\r\n",
EventStatus, ProcDevList[Idx]);
}
} else {
/* Required due to MISRA */
PmDbg("Invalid PSM event %d\r\n", PsmToPlmEvent->Event[Idx]);
}
}
Cmd->Response[0] = (u32)Status;
done:
if (XST_SUCCESS == Status) {
Cmd->ResumeHandler = NULL;
} else {
PmErr("Error %d in handling PSM event\r\n", Status);
}
return Status;
}
/****************************************************************************/
/**
* @brief Initialize PSM module which processes IPI from PSM
*
* @param None
*
* @return None
*
* @note None
*
****************************************************************************/
void XPm_PsmModuleInit(void)
{
u32 Idx;
for (Idx = 1; Idx < XPlmi_Psm.CmdCnt; Idx++) {
XPlmi_PsmCmds[Idx].Handler = XPm_ProcessPsmCmd;
}
XPlmi_ModuleRegister(&XPlmi_Psm);
}
/****************************************************************************/
/**
* @brief This Function will power up processor by sending IPI to PSM for
* performing direct power up operation.
*
* @param DeviceId Device ID of processor
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
* @note none
*
****************************************************************************/
XStatus XPm_DirectPwrUp(const u32 DeviceId)
{
XStatus Status = XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
Payload[0] = PSM_API_DIRECT_PWR_UP;
Payload[1] = DeviceId;
Status = XPm_IpiSend(PSM_IPI_INT_MASK, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_IpiReadStatus(PSM_IPI_INT_MASK);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This Function will power down processor by sending IPI to PSM for
* performing direct power down operation.
*
* @param DeviceId Device ID of processor
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
* @note none
*
****************************************************************************/
XStatus XPm_DirectPwrDwn(const u32 DeviceId)
{
XStatus Status = XST_FAILURE;
u32 Payload[PAYLOAD_ARG_CNT];
Payload[0] = PSM_API_DIRECT_PWR_DWN;
Payload[1] = DeviceId;
Status = XPm_IpiSend(PSM_IPI_INT_MASK, Payload);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPm_IpiReadStatus(PSM_IPI_INT_MASK);
done:
return Status;
}
/****************************************************************************/
/**
* @brief This Function is called by PSM to perform actions to finish suspend
* procedur of processor.
*
* @param DeviceId Device ID of processor
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
* @note none
*
****************************************************************************/
XStatus XPm_PwrDwnEvent(const u32 DeviceId)
{
XStatus Status = XST_FAILURE;
XPm_Core *Core;
XPm_Subsystem *Subsystem;
u32 SubsystemId;
XPm_Power *Lpd;
if (((u32)XPM_NODECLASS_DEVICE != NODECLASS(DeviceId)) ||
((u32)XPM_NODESUBCL_DEV_CORE != NODESUBCLASS(DeviceId))) {
Status = XST_INVALID_PARAM;
goto done;
}
Core = (XPm_Core *)XPmDevice_GetById(DeviceId);
if ((u8)XPM_DEVSTATE_SUSPENDING != Core->Device.Node.State) {
Status = XST_FAILURE;
goto done;
}
if (NULL != Core->CoreOps->PowerDown) {
Status = Core->CoreOps->PowerDown(Core);
}
SubsystemId = XPmDevice_GetSubsystemIdOfCore((XPm_Device *)Core);
Subsystem = XPmSubsystem_GetById(SubsystemId);
if (NULL == Subsystem) {
Status = XST_FAILURE;
goto done;
}
if ((u8)SUSPENDING == Subsystem->State) {
Status = XPmRequirement_UpdateScheduled(Subsystem, 1U);
if (XST_SUCCESS != Status) {
goto done;
}
/* Release devices requested by PLM to turn of LPD domain */
Lpd = XPmPower_GetById(PM_POWER_LPD);
if (((Lpd->UseCount > 0U) && (Lpd->UseCount <= 3U)) &&
(((u32)XPM_NODETYPE_DEV_CORE_APU == NODETYPE(DeviceId)) ||
((u32)XPM_NODETYPE_DEV_CORE_RPU == NODETYPE(DeviceId)))) {
Status = XPmDevice_Release(PM_SUBSYS_PMC, PM_DEV_PSM_PROC);
if (XST_SUCCESS != Status) {
PmErr("Error %d in XPmDevice_Release(PM_SUBSYS_DEFAULT, PM_DEV_PSM_PROC)\r\n");
goto done;
}
Status = XPmDevice_Release(PM_SUBSYS_PMC, PM_DEV_IPI_PMC);
if (XST_SUCCESS != Status) {
PmErr("Error %d in XPmDevice_Release(PM_SUBSYS_PMC, PM_DEV_IPI_PMC)\r\n");
goto done;
}
#ifdef DEBUG_UART_PS
XPlmi_ResetLpdInitialized();
/* Wait for UART buffer to flush */
usleep(1000);
Status = XPmDevice_Release(PM_SUBSYS_PMC, NODE_UART);
if (XST_SUCCESS != Status) {
PmErr("PMC Error %d in XPmDevice_Release(PM_SUBSYS_DEFAULT, PM_DEV_UART_0)\r\n");
goto done;
}
#endif
}
Status = XPmSubsystem_SetState(SubsystemId, (u32)SUSPENDED);
} else {
Status = XST_SUCCESS;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief This Function is called by PSM to wake processor.
*
* @param DeviceId Device ID of processor
*
* @return XST_SUCCESS if successful else XST_FAILURE or an error code.
*
* @note none
*
****************************************************************************/
XStatus XPm_WakeUpEvent(const u32 DeviceId)
{
return XPm_RequestWakeUp(PM_SUBSYS_PMC, DeviceId, 0, 0, 0);
}
<file_sep>/python_drivers/qutag_examples/qutag-GetCoincCounter-LivePlotting-example.py
# Example for using the Coincidence Counters with python + quTAG
#
# Author: qutools GmbH
# Last edited: Sep 2019
#
# Tested with python 3.7.3 (32bit), numpy-1.13.3 and Windows 7 (64bit)
#
# This is demo code. Use at your own risk. No warranties.
#
# It may be used and modified with no restriction; raw copies as well as
# modified versions may be distributed without limitation.
# for plotting
import matplotlib.pyplot as plt
import matplotlib.animation as animation
from matplotlib import style
# for sleep
import time
# This code shows how to get event rates and coincidences from a quTAG connected via USB.
# Additionally we are plotting the data "live" with matplotlib.
# Import the python wrapper which wraps the DLL functions.
# The wrapper should be in the same directory like this code in the folder '..\QUTAG-V1.5.0\userlib\src'.
try:
import QuTAG
except:
print("Time Tagger wrapper QuTAG.py is not in the search path.")
# Initialize the quTAG device
qutag = QuTAG.QuTAG()
# Read back device parameters: coincidence window in bins (bin width corresponds to timebase) and exposuretime in ms
# We use the exposure time for the y-axis in the plot
na, coincWin, expTime = qutag.getDeviceParams()
print("Coincidence window",coincWin, "bins, exposure time",expTime, "ms")
# Init plotting with mathplotlib
style.use('fivethirtyeight')
fig = plt.figure()
fig.set_size_inches(10,7)
subplt = fig.add_subplot(1,1,1)
# Variables for the printed channels in the plot
channel_plot1 = 1 # quTAG channel 1
channel_plot2 = 2
# Arrays for saving data for plotting
xs1 = []
ys1 = []
xs2 = []
ys2 = []
# Increment in loop for plotting when new data comes from quTAG
newdata = 0
# Let's get count rates and coincidences of the device in a loop for plotting.
for i in range(1000):
time.sleep(0.1)
# Get the data from quTAG.
data,updates = qutag.getCoincCounters()
print("Data: ", data)
# updates Output: Number of data updates by the device since the last call. Pointer may be NULL.
# data Output: Counter Values. The array must have at least 31 elements.
# The Counters come in the following channel order with single counts and coincidences:
# 0(5), 1, 2, 3, 4, 1/2, 1/3, 2/3, 1/4, 2/4, 3/4, 1/5, 2/5, 3/5, 4/5, 1/2/3, 1/2/4, 1/3/4, 2/3/4, 1/2/5, 1/3/5, 2/3/5, 1/4/5, 2/4/5, 3/4/5, 1/2/3/4, 1/2/3/5, 1/2/4/5, 1/3/4/5, 2/3/4/5, 1/2/3/4/5
### see 'tdcbase.h' file reference for more info: function TDC_getCoincCounters(Int32 *data, Int32 *updates)
if (updates == 0):
# No new data...
print("waiting for new data...")
else:
# Push the countrates of channel 1 & 2 in arrays for plotting...
newdata += 1
xs1.append(newdata*expTime/500)
ys1.append(data[channel_plot1])
xs2.append(newdata*expTime/500)
ys2.append(data[channel_plot2])
# Plotting...
plt.cla()
subplt.set_title('quTAG count rates')
plt.xlabel('Time [s]')
plt.ylabel('Countrate [1/' + str(expTime/1000) +'s]')
# Let's remove old data from the plotting array, so only e.g. the last 30 datapoints are plotted
if (len(xs1) > 30):
xs1.pop(0)
ys1.pop(0)
xs2.pop(0)
ys2.pop(0)
plt.plot(xs1,ys1, '-', label="Ch " + str(channel_plot1))
plt.plot(xs2,ys2, '--', label="Ch " + str(channel_plot2))
plt.legend()
plt.pause(0.01)
# Disconnects a connected device and stops the internal event loop.
qutag.deInitialize()
<file_sep>/c_drivers/drivers/gpio.c
#include "gpio.h"
#include "xgpio.h"
#define GPIO_EXAMPLE_DEVICE_ID XPAR_GPIO_0_DEVICE_ID
XGpio Gpio; /* The Instance of the GPIO Driver */
#define RST_BIT 3
#define WRITE_BIT 2
#define SCLK_BIT 0
#define SDATA_BIT 1
#define P_WRITE_BIT 4
#define P_SCLK_BIT 5
#define P_SDATA_BIT 6
u32 gpio_state;
uint8_t gpio_init()
{
gpio_state = 0;
if (XGpio_Initialize(&Gpio, GPIO_EXAMPLE_DEVICE_ID) != XST_SUCCESS)
{
return 1;
}
//set channel 1 to be all outputs
XGpio_SetDataDirection(&Gpio, 1, 0);
XGpio_SetDataDirection(&Gpio, 2, 0x1);
//Turn all outputs off by default
XGpio_DiscreteWrite(&Gpio, 1, 0);
XGpio_DiscreteWrite(&Gpio, 2, 0);
//Put the reset line in the correct state
gpio_reset_pulse_gen();
return XST_SUCCESS;
}
void gpio_set_pin(u8 bit, u8 value)
{
u32 new_gpio_state;
if(value){
new_gpio_state = gpio_state | (0x01 << bit);
}
else
{
new_gpio_state = gpio_state & ~(0x01 << bit);
}
XGpio_DiscreteWrite(&Gpio, 1, new_gpio_state);
gpio_state = new_gpio_state;
}
u8 gpio_get_busy()
{
u32 result = XGpio_DiscreteRead(&Gpio, 2);
return (u8)(result & 0x01);
}
//Resets the fabric in the 250MHz clock domain
void gpio_reset_pulse_gen()
{
gpio_set_pin(RST_BIT, 0);
gpio_set_pin(RST_BIT, 1);
}
//Sends a command to the pulse generator RTL via FIFO
void gpio_send_command(uint32_t value)
{
//First shift the command into the register
for(int i = 0; i < 32; i++)
{
//Set the output to the correct bit
u8 current_bit = (value & (1 << i)) == 0 ? 0 : 1;
gpio_set_pin(SDATA_BIT, current_bit);
//cycle the cycles sclk
gpio_set_pin(SCLK_BIT, 0x01);
gpio_set_pin(SCLK_BIT, 0x00);
}
//Then write the command into the fifo
gpio_set_pin(WRITE_BIT, 0x01);
gpio_set_pin(WRITE_BIT, 0x00);
}
//Sends a command to the pulse generator RTL via FIFO
void gpio_queue_pulse(uint32_t value)
{
//First shift the command into the register
for(int i = 0; i < 32; i++)
{
//Set the output to the correct bit
u8 current_bit = (value & (1 << i)) == 0 ? 0 : 1;
gpio_set_pin(P_SDATA_BIT, current_bit);
//cycle the cycles sclk
gpio_set_pin(P_SCLK_BIT, 0x01);
gpio_set_pin(P_SCLK_BIT, 0x00);
}
//Then write the command into the fifo
gpio_set_pin(P_WRITE_BIT, 0x01);
gpio_set_pin(P_WRITE_BIT, 0x00);
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/uart1.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _UART1_H_
#define _UART1_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* UART1 Base Address
*/
#define UART1_BASEADDR ((u32)0XFF010000U)
/**
* Register: UART1_CONTROL_REG0
*/
#define UART1_CONTROL_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000000U) )
#define UART1_CONTROL_REG0_STPBRK_SHIFT 8
#define UART1_CONTROL_REG0_STPBRK_WIDTH 1
#define UART1_CONTROL_REG0_STPBRK_MASK ((u32)0X00000100U)
#define UART1_CONTROL_REG0_STTBRK_SHIFT 7
#define UART1_CONTROL_REG0_STTBRK_WIDTH 1
#define UART1_CONTROL_REG0_STTBRK_MASK ((u32)0X00000080U)
#define UART1_CONTROL_REG0_RSTTO_SHIFT 6
#define UART1_CONTROL_REG0_RSTTO_WIDTH 1
#define UART1_CONTROL_REG0_RSTTO_MASK ((u32)0X00000040U)
#define UART1_CONTROL_REG0_TXDIS_SHIFT 5
#define UART1_CONTROL_REG0_TXDIS_WIDTH 1
#define UART1_CONTROL_REG0_TXDIS_MASK ((u32)0X00000020U)
#define UART1_CONTROL_REG0_TXEN_SHIFT 4
#define UART1_CONTROL_REG0_TXEN_WIDTH 1
#define UART1_CONTROL_REG0_TXEN_MASK ((u32)0X00000010U)
#define UART1_CONTROL_REG0_RXDIS_SHIFT 3
#define UART1_CONTROL_REG0_RXDIS_WIDTH 1
#define UART1_CONTROL_REG0_RXDIS_MASK ((u32)0X00000008U)
#define UART1_CONTROL_REG0_RXEN_SHIFT 2
#define UART1_CONTROL_REG0_RXEN_WIDTH 1
#define UART1_CONTROL_REG0_RXEN_MASK ((u32)0X00000004U)
#define UART1_CONTROL_REG0_TXRES_SHIFT 1
#define UART1_CONTROL_REG0_TXRES_WIDTH 1
#define UART1_CONTROL_REG0_TXRES_MASK ((u32)0X00000002U)
#define UART1_CONTROL_REG0_RXRES_SHIFT 0
#define UART1_CONTROL_REG0_RXRES_WIDTH 1
#define UART1_CONTROL_REG0_RXRES_MASK ((u32)0X00000001U)
/**
* Register: UART1_MODE_REG0
*/
#define UART1_MODE_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000004U) )
#define UART1_MODE_REG0_WSIZE_SHIFT 12
#define UART1_MODE_REG0_WSIZE_WIDTH 2
#define UART1_MODE_REG0_WSIZE_MASK ((u32)0X00003000U)
#define UART1_MODE_REG0_IRMODE_SHIFT 11
#define UART1_MODE_REG0_IRMODE_WIDTH 1
#define UART1_MODE_REG0_IRMODE_MASK ((u32)0X00000800U)
#define UART1_MODE_REG0_UCLKEN_SHIFT 10
#define UART1_MODE_REG0_UCLKEN_WIDTH 1
#define UART1_MODE_REG0_UCLKEN_MASK ((u32)0X00000400U)
#define UART1_MODE_REG0_CHMODE_SHIFT 8
#define UART1_MODE_REG0_CHMODE_WIDTH 2
#define UART1_MODE_REG0_CHMODE_MASK ((u32)0X00000300U)
#define UART1_MODE_REG0_NBSTOP_SHIFT 6
#define UART1_MODE_REG0_NBSTOP_WIDTH 2
#define UART1_MODE_REG0_NBSTOP_MASK ((u32)0X000000C0U)
#define UART1_MODE_REG0_PAR_SHIFT 3
#define UART1_MODE_REG0_PAR_WIDTH 3
#define UART1_MODE_REG0_PAR_MASK ((u32)0X00000038U)
#define UART1_MODE_REG0_CHRL_SHIFT 1
#define UART1_MODE_REG0_CHRL_WIDTH 2
#define UART1_MODE_REG0_CHRL_MASK ((u32)0X00000006U)
#define UART1_MODE_REG0_CLKS_SHIFT 0
#define UART1_MODE_REG0_CLKS_WIDTH 1
#define UART1_MODE_REG0_CLKS_MASK ((u32)0X00000001U)
/**
* Register: UART1_INTRPT_EN_REG0
*/
#define UART1_INTRPT_EN_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000008U) )
#define UART1_INTRPT_EN_REG0_RBRK_SHIFT 13
#define UART1_INTRPT_EN_REG0_RBRK_WIDTH 1
#define UART1_INTRPT_EN_REG0_RBRK_MASK ((u32)0X00002000U)
#define UART1_INTRPT_EN_REG0_TOVR_SHIFT 12
#define UART1_INTRPT_EN_REG0_TOVR_WIDTH 1
#define UART1_INTRPT_EN_REG0_TOVR_MASK ((u32)0X00001000U)
#define UART1_INTRPT_EN_REG0_TNFUL_SHIFT 11
#define UART1_INTRPT_EN_REG0_TNFUL_WIDTH 1
#define UART1_INTRPT_EN_REG0_TNFUL_MASK ((u32)0X00000800U)
#define UART1_INTRPT_EN_REG0_TTRIG_SHIFT 10
#define UART1_INTRPT_EN_REG0_TTRIG_WIDTH 1
#define UART1_INTRPT_EN_REG0_TTRIG_MASK ((u32)0X00000400U)
#define UART1_INTRPT_EN_REG0_DMSI_SHIFT 9
#define UART1_INTRPT_EN_REG0_DMSI_WIDTH 1
#define UART1_INTRPT_EN_REG0_DMSI_MASK ((u32)0X00000200U)
#define UART1_INTRPT_EN_REG0_TIMEOUT_SHIFT 8
#define UART1_INTRPT_EN_REG0_TIMEOUT_WIDTH 1
#define UART1_INTRPT_EN_REG0_TIMEOUT_MASK ((u32)0X00000100U)
#define UART1_INTRPT_EN_REG0_PARE_SHIFT 7
#define UART1_INTRPT_EN_REG0_PARE_WIDTH 1
#define UART1_INTRPT_EN_REG0_PARE_MASK ((u32)0X00000080U)
#define UART1_INTRPT_EN_REG0_FRAME_SHIFT 6
#define UART1_INTRPT_EN_REG0_FRAME_WIDTH 1
#define UART1_INTRPT_EN_REG0_FRAME_MASK ((u32)0X00000040U)
#define UART1_INTRPT_EN_REG0_ROVR_SHIFT 5
#define UART1_INTRPT_EN_REG0_ROVR_WIDTH 1
#define UART1_INTRPT_EN_REG0_ROVR_MASK ((u32)0X00000020U)
#define UART1_INTRPT_EN_REG0_TFUL_SHIFT 4
#define UART1_INTRPT_EN_REG0_TFUL_WIDTH 1
#define UART1_INTRPT_EN_REG0_TFUL_MASK ((u32)0X00000010U)
#define UART1_INTRPT_EN_REG0_TEMPTY_SHIFT 3
#define UART1_INTRPT_EN_REG0_TEMPTY_WIDTH 1
#define UART1_INTRPT_EN_REG0_TEMPTY_MASK ((u32)0X00000008U)
#define UART1_INTRPT_EN_REG0_RFUL_SHIFT 2
#define UART1_INTRPT_EN_REG0_RFUL_WIDTH 1
#define UART1_INTRPT_EN_REG0_RFUL_MASK ((u32)0X00000004U)
#define UART1_INTRPT_EN_REG0_REMPTY_SHIFT 1
#define UART1_INTRPT_EN_REG0_REMPTY_WIDTH 1
#define UART1_INTRPT_EN_REG0_REMPTY_MASK ((u32)0X00000002U)
#define UART1_INTRPT_EN_REG0_RTRIG_SHIFT 0
#define UART1_INTRPT_EN_REG0_RTRIG_WIDTH 1
#define UART1_INTRPT_EN_REG0_RTRIG_MASK ((u32)0X00000001U)
/**
* Register: UART1_INTRPT_DIS_REG0
*/
#define UART1_INTRPT_DIS_REG0 ( ( UART1_BASEADDR ) + ((u32)0X0000000CU) )
#define UART1_INTRPT_DIS_REG0_RBRK_SHIFT 13
#define UART1_INTRPT_DIS_REG0_RBRK_WIDTH 1
#define UART1_INTRPT_DIS_REG0_RBRK_MASK ((u32)0X00002000U)
#define UART1_INTRPT_DIS_REG0_TOVR_SHIFT 12
#define UART1_INTRPT_DIS_REG0_TOVR_WIDTH 1
#define UART1_INTRPT_DIS_REG0_TOVR_MASK ((u32)0X00001000U)
#define UART1_INTRPT_DIS_REG0_TNFUL_SHIFT 11
#define UART1_INTRPT_DIS_REG0_TNFUL_WIDTH 1
#define UART1_INTRPT_DIS_REG0_TNFUL_MASK ((u32)0X00000800U)
#define UART1_INTRPT_DIS_REG0_TTRIG_SHIFT 10
#define UART1_INTRPT_DIS_REG0_TTRIG_WIDTH 1
#define UART1_INTRPT_DIS_REG0_TTRIG_MASK ((u32)0X00000400U)
#define UART1_INTRPT_DIS_REG0_DMSI_SHIFT 9
#define UART1_INTRPT_DIS_REG0_DMSI_WIDTH 1
#define UART1_INTRPT_DIS_REG0_DMSI_MASK ((u32)0X00000200U)
#define UART1_INTRPT_DIS_REG0_TIMEOUT_SHIFT 8
#define UART1_INTRPT_DIS_REG0_TIMEOUT_WIDTH 1
#define UART1_INTRPT_DIS_REG0_TIMEOUT_MASK ((u32)0X00000100U)
#define UART1_INTRPT_DIS_REG0_PARE_SHIFT 7
#define UART1_INTRPT_DIS_REG0_PARE_WIDTH 1
#define UART1_INTRPT_DIS_REG0_PARE_MASK ((u32)0X00000080U)
#define UART1_INTRPT_DIS_REG0_FRAME_SHIFT 6
#define UART1_INTRPT_DIS_REG0_FRAME_WIDTH 1
#define UART1_INTRPT_DIS_REG0_FRAME_MASK ((u32)0X00000040U)
#define UART1_INTRPT_DIS_REG0_ROVR_SHIFT 5
#define UART1_INTRPT_DIS_REG0_ROVR_WIDTH 1
#define UART1_INTRPT_DIS_REG0_ROVR_MASK ((u32)0X00000020U)
#define UART1_INTRPT_DIS_REG0_TFUL_SHIFT 4
#define UART1_INTRPT_DIS_REG0_TFUL_WIDTH 1
#define UART1_INTRPT_DIS_REG0_TFUL_MASK ((u32)0X00000010U)
#define UART1_INTRPT_DIS_REG0_TEMPTY_SHIFT 3
#define UART1_INTRPT_DIS_REG0_TEMPTY_WIDTH 1
#define UART1_INTRPT_DIS_REG0_TEMPTY_MASK ((u32)0X00000008U)
#define UART1_INTRPT_DIS_REG0_RFUL_SHIFT 2
#define UART1_INTRPT_DIS_REG0_RFUL_WIDTH 1
#define UART1_INTRPT_DIS_REG0_RFUL_MASK ((u32)0X00000004U)
#define UART1_INTRPT_DIS_REG0_REMPTY_SHIFT 1
#define UART1_INTRPT_DIS_REG0_REMPTY_WIDTH 1
#define UART1_INTRPT_DIS_REG0_REMPTY_MASK ((u32)0X00000002U)
#define UART1_INTRPT_DIS_REG0_RTRIG_SHIFT 0
#define UART1_INTRPT_DIS_REG0_RTRIG_WIDTH 1
#define UART1_INTRPT_DIS_REG0_RTRIG_MASK ((u32)0X00000001U)
/**
* Register: UART1_INTRPT_MASK_REG0
*/
#define UART1_INTRPT_MASK_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000010U) )
#define UART1_INTRPT_MASK_REG0_RBRK_SHIFT 13
#define UART1_INTRPT_MASK_REG0_RBRK_WIDTH 1
#define UART1_INTRPT_MASK_REG0_RBRK_MASK ((u32)0X00002000U)
#define UART1_INTRPT_MASK_REG0_TOVR_SHIFT 12
#define UART1_INTRPT_MASK_REG0_TOVR_WIDTH 1
#define UART1_INTRPT_MASK_REG0_TOVR_MASK ((u32)0X00001000U)
#define UART1_INTRPT_MASK_REG0_TNFUL_SHIFT 11
#define UART1_INTRPT_MASK_REG0_TNFUL_WIDTH 1
#define UART1_INTRPT_MASK_REG0_TNFUL_MASK ((u32)0X00000800U)
#define UART1_INTRPT_MASK_REG0_TTRIG_SHIFT 10
#define UART1_INTRPT_MASK_REG0_TTRIG_WIDTH 1
#define UART1_INTRPT_MASK_REG0_TTRIG_MASK ((u32)0X00000400U)
#define UART1_INTRPT_MASK_REG0_DMSI_SHIFT 9
#define UART1_INTRPT_MASK_REG0_DMSI_WIDTH 1
#define UART1_INTRPT_MASK_REG0_DMSI_MASK ((u32)0X00000200U)
#define UART1_INTRPT_MASK_REG0_TIMEOUT_SHIFT 8
#define UART1_INTRPT_MASK_REG0_TIMEOUT_WIDTH 1
#define UART1_INTRPT_MASK_REG0_TIMEOUT_MASK ((u32)0X00000100U)
#define UART1_INTRPT_MASK_REG0_PARE_SHIFT 7
#define UART1_INTRPT_MASK_REG0_PARE_WIDTH 1
#define UART1_INTRPT_MASK_REG0_PARE_MASK ((u32)0X00000080U)
#define UART1_INTRPT_MASK_REG0_FRAME_SHIFT 6
#define UART1_INTRPT_MASK_REG0_FRAME_WIDTH 1
#define UART1_INTRPT_MASK_REG0_FRAME_MASK ((u32)0X00000040U)
#define UART1_INTRPT_MASK_REG0_ROVR_SHIFT 5
#define UART1_INTRPT_MASK_REG0_ROVR_WIDTH 1
#define UART1_INTRPT_MASK_REG0_ROVR_MASK ((u32)0X00000020U)
#define UART1_INTRPT_MASK_REG0_TFUL_SHIFT 4
#define UART1_INTRPT_MASK_REG0_TFUL_WIDTH 1
#define UART1_INTRPT_MASK_REG0_TFUL_MASK ((u32)0X00000010U)
#define UART1_INTRPT_MASK_REG0_TEMPTY_SHIFT 3
#define UART1_INTRPT_MASK_REG0_TEMPTY_WIDTH 1
#define UART1_INTRPT_MASK_REG0_TEMPTY_MASK ((u32)0X00000008U)
#define UART1_INTRPT_MASK_REG0_RFUL_SHIFT 2
#define UART1_INTRPT_MASK_REG0_RFUL_WIDTH 1
#define UART1_INTRPT_MASK_REG0_RFUL_MASK ((u32)0X00000004U)
#define UART1_INTRPT_MASK_REG0_REMPTY_SHIFT 1
#define UART1_INTRPT_MASK_REG0_REMPTY_WIDTH 1
#define UART1_INTRPT_MASK_REG0_REMPTY_MASK ((u32)0X00000002U)
#define UART1_INTRPT_MASK_REG0_RTRIG_SHIFT 0
#define UART1_INTRPT_MASK_REG0_RTRIG_WIDTH 1
#define UART1_INTRPT_MASK_REG0_RTRIG_MASK ((u32)0X00000001U)
/**
* Register: UART1_CHNL_INT_STS_REG0
*/
#define UART1_CHNL_INT_STS_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000014U) )
#define UART1_CHNL_INT_STS_REG0_RBRK_SHIFT 13
#define UART1_CHNL_INT_STS_REG0_RBRK_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_RBRK_MASK ((u32)0X00002000U)
#define UART1_CHNL_INT_STS_REG0_TOVR_SHIFT 12
#define UART1_CHNL_INT_STS_REG0_TOVR_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_TOVR_MASK ((u32)0X00001000U)
#define UART1_CHNL_INT_STS_REG0_TNFUL_SHIFT 11
#define UART1_CHNL_INT_STS_REG0_TNFUL_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_TNFUL_MASK ((u32)0X00000800U)
#define UART1_CHNL_INT_STS_REG0_TTRIG_SHIFT 10
#define UART1_CHNL_INT_STS_REG0_TTRIG_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_TTRIG_MASK ((u32)0X00000400U)
#define UART1_CHNL_INT_STS_REG0_DMSI_SHIFT 9
#define UART1_CHNL_INT_STS_REG0_DMSI_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_DMSI_MASK ((u32)0X00000200U)
#define UART1_CHNL_INT_STS_REG0_TIMEOUT_SHIFT 8
#define UART1_CHNL_INT_STS_REG0_TIMEOUT_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_TIMEOUT_MASK ((u32)0X00000100U)
#define UART1_CHNL_INT_STS_REG0_PARE_SHIFT 7
#define UART1_CHNL_INT_STS_REG0_PARE_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_PARE_MASK ((u32)0X00000080U)
#define UART1_CHNL_INT_STS_REG0_FRAME_SHIFT 6
#define UART1_CHNL_INT_STS_REG0_FRAME_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_FRAME_MASK ((u32)0X00000040U)
#define UART1_CHNL_INT_STS_REG0_ROVR_SHIFT 5
#define UART1_CHNL_INT_STS_REG0_ROVR_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_ROVR_MASK ((u32)0X00000020U)
#define UART1_CHNL_INT_STS_REG0_TFUL_SHIFT 4
#define UART1_CHNL_INT_STS_REG0_TFUL_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_TFUL_MASK ((u32)0X00000010U)
#define UART1_CHNL_INT_STS_REG0_TEMPTY_SHIFT 3
#define UART1_CHNL_INT_STS_REG0_TEMPTY_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_TEMPTY_MASK ((u32)0X00000008U)
#define UART1_CHNL_INT_STS_REG0_RFUL_SHIFT 2
#define UART1_CHNL_INT_STS_REG0_RFUL_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_RFUL_MASK ((u32)0X00000004U)
#define UART1_CHNL_INT_STS_REG0_REMPTY_SHIFT 1
#define UART1_CHNL_INT_STS_REG0_REMPTY_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_REMPTY_MASK ((u32)0X00000002U)
#define UART1_CHNL_INT_STS_REG0_RTRIG_SHIFT 0
#define UART1_CHNL_INT_STS_REG0_RTRIG_WIDTH 1
#define UART1_CHNL_INT_STS_REG0_RTRIG_MASK ((u32)0X00000001U)
/**
* Register: UART1_BAUD_RATE_GEN_REG0
*/
#define UART1_BAUD_RATE_GEN_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000018U) )
#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0
#define UART1_BAUD_RATE_GEN_REG0_CD_WIDTH 16
#define UART1_BAUD_RATE_GEN_REG0_CD_MASK ((u32)0X0000FFFFU)
/**
* Register: UART1_RCVR_TIMEOUT_REG0
*/
#define UART1_RCVR_TIMEOUT_REG0 ( ( UART1_BASEADDR ) + ((u32)0X0000001CU) )
#define UART1_RCVR_TIMEOUT_REG0_RTO_SHIFT 0
#define UART1_RCVR_TIMEOUT_REG0_RTO_WIDTH 8
#define UART1_RCVR_TIMEOUT_REG0_RTO_MASK ((u32)0X000000FFU)
/**
* Register: UART1_RCVR_FIFO_TRIGGER_LEVEL0
*/
#define UART1_RCVR_FIFO_TRIGGER_LEVEL0 ( ( UART1_BASEADDR ) + ((u32)0X00000020U) )
#define UART1_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_SHIFT 0
#define UART1_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_WIDTH 6
#define UART1_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_MASK ((u32)0X0000003FU)
/**
* Register: UART1_MODEM_CTRL_REG0
*/
#define UART1_MODEM_CTRL_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000024U) )
#define UART1_MODEM_CTRL_REG0_FCM_SHIFT 5
#define UART1_MODEM_CTRL_REG0_FCM_WIDTH 1
#define UART1_MODEM_CTRL_REG0_FCM_MASK ((u32)0X00000020U)
#define UART1_MODEM_CTRL_REG0_RTS_SHIFT 1
#define UART1_MODEM_CTRL_REG0_RTS_WIDTH 1
#define UART1_MODEM_CTRL_REG0_RTS_MASK ((u32)0X00000002U)
#define UART1_MODEM_CTRL_REG0_DTR_SHIFT 0
#define UART1_MODEM_CTRL_REG0_DTR_WIDTH 1
#define UART1_MODEM_CTRL_REG0_DTR_MASK ((u32)0X00000001U)
/**
* Register: UART1_MODEM_STS_REG0
*/
#define UART1_MODEM_STS_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000028U) )
#define UART1_MODEM_STS_REG0_FCMS_SHIFT 8
#define UART1_MODEM_STS_REG0_FCMS_WIDTH 1
#define UART1_MODEM_STS_REG0_FCMS_MASK ((u32)0X00000100U)
#define UART1_MODEM_STS_REG0_DCD_SHIFT 7
#define UART1_MODEM_STS_REG0_DCD_WIDTH 1
#define UART1_MODEM_STS_REG0_DCD_MASK ((u32)0X00000080U)
#define UART1_MODEM_STS_REG0_RI_SHIFT 6
#define UART1_MODEM_STS_REG0_RI_WIDTH 1
#define UART1_MODEM_STS_REG0_RI_MASK ((u32)0X00000040U)
#define UART1_MODEM_STS_REG0_DSR_SHIFT 5
#define UART1_MODEM_STS_REG0_DSR_WIDTH 1
#define UART1_MODEM_STS_REG0_DSR_MASK ((u32)0X00000020U)
#define UART1_MODEM_STS_REG0_CTS_SHIFT 4
#define UART1_MODEM_STS_REG0_CTS_WIDTH 1
#define UART1_MODEM_STS_REG0_CTS_MASK ((u32)0X00000010U)
#define UART1_MODEM_STS_REG0_DDCD_SHIFT 3
#define UART1_MODEM_STS_REG0_DDCD_WIDTH 1
#define UART1_MODEM_STS_REG0_DDCD_MASK ((u32)0X00000008U)
#define UART1_MODEM_STS_REG0_TERI_SHIFT 2
#define UART1_MODEM_STS_REG0_TERI_WIDTH 1
#define UART1_MODEM_STS_REG0_TERI_MASK ((u32)0X00000004U)
#define UART1_MODEM_STS_REG0_DDSR_SHIFT 1
#define UART1_MODEM_STS_REG0_DDSR_WIDTH 1
#define UART1_MODEM_STS_REG0_DDSR_MASK ((u32)0X00000002U)
#define UART1_MODEM_STS_REG0_DCTS_SHIFT 0
#define UART1_MODEM_STS_REG0_DCTS_WIDTH 1
#define UART1_MODEM_STS_REG0_DCTS_MASK ((u32)0X00000001U)
/**
* Register: UART1_CHANNEL_STS_REG0
*/
#define UART1_CHANNEL_STS_REG0 ( ( UART1_BASEADDR ) + ((u32)0X0000002CU) )
#define UART1_CHANNEL_STS_REG0_RBRK_SHIFT 15
#define UART1_CHANNEL_STS_REG0_RBRK_WIDTH 1
#define UART1_CHANNEL_STS_REG0_RBRK_MASK ((u32)0X00008000U)
#define UART1_CHANNEL_STS_REG0_TNFUL_SHIFT 14
#define UART1_CHANNEL_STS_REG0_TNFUL_WIDTH 1
#define UART1_CHANNEL_STS_REG0_TNFUL_MASK ((u32)0X00004000U)
#define UART1_CHANNEL_STS_REG0_TTRIG_SHIFT 13
#define UART1_CHANNEL_STS_REG0_TTRIG_WIDTH 1
#define UART1_CHANNEL_STS_REG0_TTRIG_MASK ((u32)0X00002000U)
#define UART1_CHANNEL_STS_REG0_FDELT_SHIFT 12
#define UART1_CHANNEL_STS_REG0_FDELT_WIDTH 1
#define UART1_CHANNEL_STS_REG0_FDELT_MASK ((u32)0X00001000U)
#define UART1_CHANNEL_STS_REG0_TACTIVE_SHIFT 11
#define UART1_CHANNEL_STS_REG0_TACTIVE_WIDTH 1
#define UART1_CHANNEL_STS_REG0_TACTIVE_MASK ((u32)0X00000800U)
#define UART1_CHANNEL_STS_REG0_RACTIVE_SHIFT 10
#define UART1_CHANNEL_STS_REG0_RACTIVE_WIDTH 1
#define UART1_CHANNEL_STS_REG0_RACTIVE_MASK ((u32)0X00000400U)
#define UART1_CHANNEL_STS_REG0_DMSI_SHIFT 9
#define UART1_CHANNEL_STS_REG0_DMSI_WIDTH 1
#define UART1_CHANNEL_STS_REG0_DMSI_MASK ((u32)0X00000200U)
#define UART1_CHANNEL_STS_REG0_TIMEOUT_SHIFT 8
#define UART1_CHANNEL_STS_REG0_TIMEOUT_WIDTH 1
#define UART1_CHANNEL_STS_REG0_TIMEOUT_MASK ((u32)0X00000100U)
#define UART1_CHANNEL_STS_REG0_PARE_SHIFT 7
#define UART1_CHANNEL_STS_REG0_PARE_WIDTH 1
#define UART1_CHANNEL_STS_REG0_PARE_MASK ((u32)0X00000080U)
#define UART1_CHANNEL_STS_REG0_FRAME_SHIFT 6
#define UART1_CHANNEL_STS_REG0_FRAME_WIDTH 1
#define UART1_CHANNEL_STS_REG0_FRAME_MASK ((u32)0X00000040U)
#define UART1_CHANNEL_STS_REG0_ROVR_SHIFT 5
#define UART1_CHANNEL_STS_REG0_ROVR_WIDTH 1
#define UART1_CHANNEL_STS_REG0_ROVR_MASK ((u32)0X00000020U)
#define UART1_CHANNEL_STS_REG0_TFUL_SHIFT 4
#define UART1_CHANNEL_STS_REG0_TFUL_WIDTH 1
#define UART1_CHANNEL_STS_REG0_TFUL_MASK ((u32)0X00000010U)
#define UART1_CHANNEL_STS_REG0_TEMPTY_SHIFT 3
#define UART1_CHANNEL_STS_REG0_TEMPTY_WIDTH 1
#define UART1_CHANNEL_STS_REG0_TEMPTY_MASK ((u32)0X00000008U)
#define UART1_CHANNEL_STS_REG0_RFUL_SHIFT 2
#define UART1_CHANNEL_STS_REG0_RFUL_WIDTH 1
#define UART1_CHANNEL_STS_REG0_RFUL_MASK ((u32)0X00000004U)
#define UART1_CHANNEL_STS_REG0_REMPTY_SHIFT 1
#define UART1_CHANNEL_STS_REG0_REMPTY_WIDTH 1
#define UART1_CHANNEL_STS_REG0_REMPTY_MASK ((u32)0X00000002U)
#define UART1_CHANNEL_STS_REG0_RTRIG_SHIFT 0
#define UART1_CHANNEL_STS_REG0_RTRIG_WIDTH 1
#define UART1_CHANNEL_STS_REG0_RTRIG_MASK ((u32)0X00000001U)
/**
* Register: UART1_TX_RX_FIFO0
*/
#define UART1_TX_RX_FIFO0 ( ( UART1_BASEADDR ) + ((u32)0X00000030U) )
#define UART1_TX_RX_FIFO0_FIFO_SHIFT 0
#define UART1_TX_RX_FIFO0_FIFO_WIDTH 8
#define UART1_TX_RX_FIFO0_FIFO_MASK ((u32)0X000000FFU)
/**
* Register: UART1_BAUD_RATE_DIVIDER_REG0
*/
#define UART1_BAUD_RATE_DIVIDER_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000034U) )
#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0
#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_WIDTH 8
#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK ((u32)0X000000FFU)
/**
* Register: UART1_FLOW_DELAY_REG0
*/
#define UART1_FLOW_DELAY_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000038U) )
#define UART1_FLOW_DELAY_REG0_FDEL_SHIFT 0
#define UART1_FLOW_DELAY_REG0_FDEL_WIDTH 6
#define UART1_FLOW_DELAY_REG0_FDEL_MASK ((u32)0X0000003FU)
/**
* Register: UART1_IR_MIN_RCV_PULSE_WDTH0
*/
#define UART1_IR_MIN_RCV_PULSE_WDTH0 ( ( UART1_BASEADDR ) + ((u32)0X0000003CU) )
#define UART1_IR_MIN_RCV_PULSE_WDTH0_PMN_SHIFT 0
#define UART1_IR_MIN_RCV_PULSE_WDTH0_PMN_WIDTH 16
#define UART1_IR_MIN_RCV_PULSE_WDTH0_PMN_MASK ((u32)0X0000FFFFU)
/**
* Register: UART1_IR_TRANSMITTED_PULSE_WDTH0
*/
#define UART1_IR_TRANSMITTED_PULSE_WDTH0 ( ( UART1_BASEADDR ) + ((u32)0X00000040U) )
#define UART1_IR_TRANSMITTED_PULSE_WDTH0_PWID_SHIFT 0
#define UART1_IR_TRANSMITTED_PULSE_WDTH0_PWID_WIDTH 8
#define UART1_IR_TRANSMITTED_PULSE_WDTH0_PWID_MASK ((u32)0X000000FFU)
/**
* Register: UART1_TX_FIFO_TRIGGER_LEVEL0
*/
#define UART1_TX_FIFO_TRIGGER_LEVEL0 ( ( UART1_BASEADDR ) + ((u32)0X00000044U) )
#define UART1_TX_FIFO_TRIGGER_LEVEL0_TTRIG_SHIFT 0
#define UART1_TX_FIFO_TRIGGER_LEVEL0_TTRIG_WIDTH 6
#define UART1_TX_FIFO_TRIGGER_LEVEL0_TTRIG_MASK ((u32)0X0000003FU)
/**
* Register: UART1_RX_FIFO_BYTE_STATUS
*/
#define UART1_RX_FIFO_BYTE_STATUS ( ( UART1_BASEADDR ) + ((u32)0X00000048U) )
#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_SHIFT 11
#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_MASK ((u32)0X00000800U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_SHIFT 10
#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_MASK ((u32)0X00000400U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_SHIFT 9
#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_MASK ((u32)0X00000200U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_SHIFT 8
#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_MASK ((u32)0X00000100U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_SHIFT 7
#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_MASK ((u32)0X00000080U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_SHIFT 6
#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_MASK ((u32)0X00000040U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_SHIFT 5
#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_MASK ((u32)0X00000020U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_SHIFT 4
#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_MASK ((u32)0X00000010U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_SHIFT 3
#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_MASK ((u32)0X00000008U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_SHIFT 2
#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_MASK ((u32)0X00000004U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_SHIFT 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_MASK ((u32)0X00000002U)
#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_SHIFT 0
#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_WIDTH 1
#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_MASK ((u32)0X00000001U)
#ifdef __cplusplus
}
#endif
#endif /* _UART1_H_ */
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/axipmon_v6_8/src/xaxipmon_sinit.c
/******************************************************************************
* Copyright (C) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxipmon_sinit.c
* @addtogroup axipmon_v6_8
* @{
*
* This file contains the implementation of the XAxiPmon driver's static
* initialization functionality.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 02/27/12 First release
* 2.00a bss 06/23/12 Updated to support v2_00a version of IP.
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xaxipmon.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern XAxiPmon_Config XAxiPmon_ConfigTable[];
/*****************************************************************************/
/**
*
* This function looks up the device configuration based on the unique device ID.
* The table XAxiPmon_ConfigTable contains the configuration info for each device
* in the system.
*
* @param DeviceId contains the ID of the device for which the
* device configuration pointer is to be returned.
*
* @return
* - A pointer to the configuration found.
* - NULL if the specified device ID was not found.
*
* @note None.
*
******************************************************************************/
XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId)
{
XAxiPmon_Config *CfgPtr = NULL;
u32 Index;
for (Index=0U; Index < (u32)XPAR_XAXIPMON_NUM_INSTANCES; Index++) {
if (XAxiPmon_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XAxiPmon_ConfigTable[Index];
break;
}
}
return (XAxiPmon_Config *)CfgPtr;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/pm_common.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file pm_common.h
*
* Definitions of commonly used macros and data types needed for
* PU Power Management. This file should be common for all PU's.
*****************************************************************************/
#ifndef PM_COMMON_H
#define PM_COMMON_H
#include "xparameters.h"
#include "xil_io.h"
#include "xil_exception.h"
#include "xil_types.h"
#include "xstatus.h"
#include "xipipsu.h"
#include "pm_defs.h"
#ifdef DEBUG_MODE
#include "xil_printf.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#define PM_ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
/* 1 for API ID + 5 for API arguments + 1 for Reserved + 1 for CRC */
#define PAYLOAD_ARG_CNT 8U
/* 1 for status + 3 for values + 3 for Reserved + 1 for CRC */
#define RESPONSE_ARG_CNT 8U
#define PM_IPI_TIMEOUT (~0U)
#define IPI_PMU_PM_INT_MASK XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK
/**
* XPm_Master - Master structure
*/
struct XPm_Master {
const enum XPmNodeId node_id; /**< Node ID */
const u32 pwrctl; /** < Power Control Register Address */
const u32 pwrdn_mask; /**< Power Down Mask */
XIpiPsu *ipi; /**< IPI Instance */
};
enum XPmNodeId pm_get_subsystem_node(void);
struct XPm_Master *pm_get_master(const u32 cpuid);
struct XPm_Master *pm_get_master_by_node(const enum XPmNodeId nid);
#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 0x00000001U
#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 0x00000002U
#define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 0x00000004U
#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 0x00000008U
#define IPI_W0_TO_W6_SIZE 28U
#define IPI_RPU_MASK 0x00000100U
#define UNDEFINED_CPUID (~0U)
#define pm_read(addr) Xil_In32(addr)
#define pm_write(addr, value) Xil_Out32(addr, value)
#define pm_enable_int() Xil_ExceptionEnable()
#define pm_disable_int() Xil_ExceptionDisable()
/* Conditional debugging prints */
#ifdef DEBUG_MODE
#define pm_dbg xil_printf
#else
#define pm_dbg(...) {}
#endif
#ifndef bool
#define bool u8
#define true 1U
#define false 0U
#endif
void XPm_ClientSuspend(const struct XPm_Master *const master);
void XPm_ClientAbortSuspend(void);
void XPm_ClientWakeup(const struct XPm_Master *const master);
void XPm_ClientSuspendFinalize(void);
void XPm_ClientSetPrimaryMaster(void);
/* Do not modify below this line */
extern const enum XPmNodeId subsystem_node;
extern struct XPm_Master *primary_master;
#ifdef __cplusplus
}
#endif
#endif /* PM_COMMON_H */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_powerdomain.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_defs.h"
#include "xpm_common.h"
#include "xpm_node.h"
#include "xpm_npdomain.h"
#include "xpm_core.h"
#include "xpm_psm.h"
#include "xpm_pmc.h"
#include "xpm_powerdomain.h"
#include "xpm_pslpdomain.h"
#include "xpm_pldomain.h"
#include "xpm_bisr.h"
#include "xpm_device.h"
#include "xpm_gic_proxy.h"
#include "xpm_regs.h"
#include "xpm_board.h"
#include "xpm_api.h"
static u8 SystemResetFlag;
static u8 DomainPORFlag;
static u32 PsmApuPwrState;
XStatus XPmPowerDomain_Init(XPm_PowerDomain *PowerDomain, u32 Id,
u32 BaseAddress, XPm_Power *Parent,
struct XPm_PowerDomainOps *Ops)
{
XStatus Status = XST_FAILURE;
u16 InitMask = 0;
Status = XPmPower_Init(&PowerDomain->Power, Id, BaseAddress, Parent);
if (XST_SUCCESS != Status) {
goto done;
}
PowerDomain->Children = NULL;
PowerDomain->DomainOps = Ops;
if ((NULL != Ops) && (NULL != Ops->ScanClear)) {
InitMask |= BIT(FUNC_SCAN_CLEAR);
}
if ((NULL != Ops) && (NULL != Ops->Bisr)) {
InitMask |= BIT(FUNC_BISR);
}
if ((NULL != Ops) && (NULL != Ops->Mbist)) {
InitMask |= BIT(FUNC_MBIST_CLEAR);
}
if ((NULL != Ops) && (NULL != Ops->Lbist)) {
InitMask |= BIT(FUNC_LBIST);
}
PowerDomain->InitMask = InitMask;
Status = XST_SUCCESS;
done:
return Status;
}
#define BITMASK_LOWER_15_BITS (0x7fffU)
#define BITMASK_UPPER_17_BITS (0xffff8000U)
#define GET_DELTA_AT_OFFSET(array, x) (0xfU & (array[(x) / 32U] >> ((x) % 32U)))
XStatus XPmPowerDomain_ApplyAmsTrim(u32 DestAddress, u32 PowerDomainId, u32 SateliteIdx)
{
XStatus Status = XST_FAILURE;
u32 EfuseCacheBaseAddress, StartbitOffset, RegValue, i, DeltaVal = 0;
static u32 OffsetVal,SlopeVal,ProcessVal,ResistorVal,BjtOffsetVal,ExtOffsetVal,AnaSpareVal,DigSpareVal,Arr[8];
static u32 CacheRead=0;
static u32 BipSelVal, TsensSelVal, TsensBiasVal;
if (0U == DestAddress) {
goto done;
}
XPm_Device *EfuseCache = XPmDevice_GetById(PM_DEV_EFUSE_CACHE);
if (NULL == EfuseCache) {
Status = XST_FAILURE;
goto done;
}
EfuseCacheBaseAddress = EfuseCache->Node.BaseAddress;
/* Unlock writes */
PmOut32(DestAddress + NPI_PCSR_LOCK_OFFSET, PCSR_UNLOCK_VAL);
if (0U == CacheRead) {
/* Read EFUSE_CACHE.TSENS_INT_OFFSET_5_0*/
PmIn32(EfuseCacheBaseAddress + EFUSE_CACHE_TRIM_AMS_3_OFFSET, RegValue);
OffsetVal = (RegValue & EFUSE_CACHE_TRIM_AMS_3_TSENS_INT_OFFSET_5_0_MASK) >> EFUSE_CACHE_TRIM_AMS_3_TSENS_INT_OFFSET_5_0_SHIFT;
/* Read EFUSE_CACHE.TSENS_SLOPE_5_0 */
SlopeVal = (RegValue & EFUSE_CACHE_TRIM_AMS_3_TSENS_SLOPE_5_0_MASK) >> EFUSE_CACHE_TRIM_AMS_3_TSENS_SLOPE_5_0_SHIFT;
/* Read EFUSE_CACHE.IXPCM_PROCESS_15_0 */
PmIn32(EfuseCacheBaseAddress + EFUSE_CACHE_TRIM_AMS_11_OFFSET, RegValue);
ProcessVal = (RegValue & EFUSE_CACHE_TRIM_AMS_11_IXPCM_PROCESS_15_0_MASK) >> EFUSE_CACHE_TRIM_AMS_11_IXPCM_PROCESS_15_0_SHIFT;
/* Read EFUSE_CACHE.RES_PROCESS_6_0 */
PmIn32(EfuseCacheBaseAddress + EFUSE_CACHE_TRIM_AMS_11_OFFSET, RegValue);
ResistorVal = (RegValue & EFUSE_CACHE_TRIM_AMS_11_RES_PROCESS_0_MASK) >> EFUSE_CACHE_TRIM_AMS_11_RES_PROCESS_0_SHIFT;
PmIn32(EfuseCacheBaseAddress + EFUSE_CACHE_TRIM_AMS_12_OFFSET, RegValue);
ResistorVal |= (((RegValue & EFUSE_CACHE_TRIM_AMS_12_RES_PROCESS_6_1_MASK) >> EFUSE_CACHE_TRIM_AMS_12_RES_PROCESS_6_1_SHIFT) << 1);
/* Read EFUSE_CACHE.BJT_PROCESS_3_0 */
BjtOffsetVal = (RegValue & EFUSE_CACHE_TRIM_AMS_12_BJT_PROCESS_3_0_MASK) >> EFUSE_CACHE_TRIM_AMS_12_BJT_PROCESS_3_0_SHIFT;
/* Read EFUSE_CACHE.TSENS_EXT_OFFSET_5_0*/
ExtOffsetVal = (RegValue & EFUSE_CACHE_TRIM_AMS_12_TSENS_EXT_OFFSET_5_0_MASK) >> EFUSE_CACHE_TRIM_AMS_12_TSENS_EXT_OFFSET_5_0_SHIFT;
/* Read EFUSE_CACHE.SHARED_SPARE_1_0 */
AnaSpareVal = (RegValue & EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_1_0_MASK) >> EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_1_0_SHIFT;
/* Read EFUSE_CACHE.SHARED_SPARE_14_2 */
DigSpareVal = (RegValue & EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_14_2_MASK) >> EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_14_2_SHIFT;
TsensSelVal = (RegValue & EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_2_MASK) >> EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_2_SHIFT;
BipSelVal = (RegValue & EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_6_MASK) >> EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_6_SHIFT;
TsensBiasVal = (RegValue & EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_4_3_MASK) >> EFUSE_CACHE_TRIM_AMS_12_SHARED_SPARE_4_3_SHIFT;
}
/* Copy EFUSE_CACHE.TSENS_INT_OFFSET_5_0 to dest_reg.EFUSE_CONFIG0[5:0] */
PmRmw32(DestAddress + EFUSE_CONFIG0_OFFSET, EFUSE_CONFIG0_OFFSET_MASK, (OffsetVal << EFUSE_CONFIG0_OFFSET_SHIFT));
/* Copy EFUSE_CACHE.TSENS_SLOPE_5_0 to dest_reg.EFUSE_CONFIG0[11:6] */
PmRmw32(DestAddress + EFUSE_CONFIG0_OFFSET, EFUSE_CONFIG0_SLOPE_MASK, (SlopeVal << EFUSE_CONFIG0_SLOPE_SHIFT));
/* Copy EFUSE_CACHE.IXPCM_PROCESS_15_0 to dest_reg.EFUSE_CONFIG0[31:16] */
PmRmw32(DestAddress + EFUSE_CONFIG0_OFFSET, EFUSE_CONFIG0_PROCESS_MASK, (ProcessVal << EFUSE_CONFIG0_PROCESS_SHIFT));
/* Copy EFUSE_CACHE.RES_PROCESS_6_0 to dest_reg.EFUSE_CONFIG1[6:0] */
PmRmw32(DestAddress + EFUSE_CONFIG1_OFFSET, EFUSE_CONFIG1_RESISTOR_MASK, (ResistorVal << EFUSE_CONFIG1_RESISTOR_SHIFT));
/* Copy EFUSE_CACHE.BJT_PROCESS_3_0 to dest_reg.EFUSE_CONFIG1[10:7] */
PmRmw32(DestAddress + EFUSE_CONFIG1_OFFSET, EFUSE_CONFIG1_BJT_OFFSET_MASK, (BjtOffsetVal << EFUSE_CONFIG1_BJT_OFFSET_SHIFT));
/* Copy EFUSE_CACHE.TSENS_EXT_OFFSET_5_0 to dest_reg.EFUSE_CONFIG1[16:11] */
PmRmw32(DestAddress + EFUSE_CONFIG1_OFFSET, EFUSE_CONFIG1_EXT_OFFSET_MASK, (ExtOffsetVal << EFUSE_CONFIG1_EXT_OFFSET_SHIFT));
/* Copy EFUSE_CACHE.SHARED_SPARE_1_0 to dest_reg.EFUSE_CONFIG1[18:17] */
PmRmw32(DestAddress + EFUSE_CONFIG1_OFFSET, EFUSE_CONFIG1_ANA_SPARE_MASK, (AnaSpareVal << EFUSE_CONFIG1_ANA_SPARE_SHIFT));
/* Copy EFUSE_CACHE.SHARED_SPARE_14_2 to dest_reg.EFUSE_CONFIG1[31:19] */
PmRmw32(DestAddress + EFUSE_CONFIG1_OFFSET, EFUSE_CONFIG1_DIG_SPARE_MASK, (DigSpareVal << EFUSE_CONFIG1_DIG_SPARE_SHIFT));
/* Copy EFUSE_CACHE.TRIM_AMS_12.SHARED_SPARE_2 to dest_reg.CAL_SM_BIP_TSENS[1] */
PmRmw32(DestAddress + CAL_SM_BIP_TSENS_OFFSET, CAL_SM_BIP_TSENS_TSENS_MASK, (TsensSelVal << CAL_SM_BIP_TSENS_TSENS_SHIFT));
/* Copy EFUSE_CACHE.TRIM_AMS_12.SHARED_SPARE_6 to dest_reg.CAL_SM_BIP_TSENS[0] */
PmRmw32(DestAddress + CAL_SM_BIP_TSENS_OFFSET, CAL_SM_BIP_TSENS_BIP_MASK, (BipSelVal << CAL_SM_BIP_TSENS_BIP_SHIFT));
/* Copy EFUSE_CACHE.TRIM_AMS_12.SHARED_SPARE_3_4 to dest_reg.TSENS_BIAS_CTRL[1:0] */
PmRmw32(DestAddress + TSENS_BIAS_CTRL_OFFSET, TSENS_BIAS_VAL_MASK, (TsensBiasVal << TSENS_BIAS_VAL_SHIFT));
if (0U == CacheRead) {
/* Copy 256 bits of TSENS_DELTA value to array */
PmIn32(EfuseCacheBaseAddress + EFUSE_CACHE_TRIM_AMS_3_OFFSET, RegValue);
/*Store 17 bits from current register */
Arr[0] = (RegValue & EFUSE_CACHE_TRIM_AMS_3_TSENS_DELTA_16_0_MASK) >> EFUSE_CACHE_TRIM_AMS_3_TSENS_DELTA_16_0_SHIFT;
for (i = 0; i < 8U; i++) {
u32 Address = (EfuseCacheBaseAddress + EFUSE_CACHE_TRIM_AMS_4_OFFSET + (i*4U));
PmIn32(Address, RegValue);
/* current element already have 17 bits stored from prev register,
store 15 bits from current register to current element */
Arr[i] |= (RegValue & BITMASK_LOWER_15_BITS) << 17;
/* store 17 bits from current register to next element */
if (i != 7U) {
Arr[i + 1U] = (RegValue & BITMASK_UPPER_17_BITS) >> 15;
}
}
/* Set cache read to avoid multiple reads */
CacheRead = 1;
}
switch (NODEINDEX(PowerDomainId)) {
case (u32)XPM_NODEIDX_POWER_PMC:
if (0U == SateliteIdx) {
/* Copy EFUSE_CACHE.TSENS_DELTA_3_0 to PMC_SYSMON.SAT0_EFUSE_CONFIG0[15:12] */
DeltaVal = GET_DELTA_AT_OFFSET(Arr, 0U);
} else if (1U == SateliteIdx) {
/* Copy EFUSE_CACHE.TSENS_DELTA_7_4 to PMC_SYSMON.SAT1_EFUSE_CONFIG0[15:12] */
DeltaVal = GET_DELTA_AT_OFFSET(Arr, 4U);
} else {
/* Required due to MISRA */
PmDbg("[%d] Invalid SateliteIdx\r\n", __LINE__);
}
Status = XST_SUCCESS;
break;
case (u32)XPM_NODEIDX_POWER_LPD:
/* Copy EFUSE_CACHE.TSENS_DELTA_11_8 to LPD_SYSMON_SAT.EFUSE_CONFIG0[15:12] */
DeltaVal = GET_DELTA_AT_OFFSET(Arr, 8U);
Status = XST_SUCCESS;
break;
case (u32)XPM_NODEIDX_POWER_FPD:
/* Copy EFUSE_CACHE.TSENS_DELTA_15_12 to FPD_SYSMON_SAT.EFUSE_CONFIG0[15:12] */
DeltaVal = GET_DELTA_AT_OFFSET(Arr, 12U);
Status = XST_SUCCESS;
break;
case (u32)XPM_NODEIDX_POWER_NOC:
StartbitOffset = 16U + (SateliteIdx * 4U);
/* Copy EFUSE_CACHE.TSENS_DELTA_STARTBIT_ENDBIT to AMS_SAT_N.EFUSE_CONFIG0[15:12] */
DeltaVal = GET_DELTA_AT_OFFSET(Arr, StartbitOffset);
Status = XST_SUCCESS;
break;
default:
Status = XST_FAILURE;
break;
}
if (XST_SUCCESS != Status) {
goto done;
}
if (0U != DeltaVal) {
PmRmw32(DestAddress + EFUSE_CONFIG0_OFFSET, EFUSE_CONFIG0_DELTA_MASK, (DeltaVal << EFUSE_CONFIG0_DELTA_SHIFT));
}
/* Lock writes */
PmOut32(DestAddress + NPI_PCSR_LOCK_OFFSET, 1);
done:
return Status;
}
XStatus XPm_PowerUpLPD(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
if ((u8)XPM_POWER_STATE_ON == Node->State) {
Status = XST_SUCCESS;
goto done;
} else {
/* TODO: LPD CDO should be rexecuted. Right now we don't have separate LPD
* CDO so calling house cleaning commands here
*/
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_INIT_START, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_SCAN_CLEAR, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_LBIST, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
/*
* Release SRST for PS-LPD
*/
Status = XPmReset_AssertbyId(PM_RST_PS_SRST, (u32)PM_RESET_ACTION_RELEASE);
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_BISR, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_MBIST_CLEAR, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_INIT_FINISH, NULL, 0);
}
done:
return Status;
}
XStatus XPm_PowerDwnLPD(void)
{
XStatus Status = XST_FAILURE;
XPm_PsLpDomain *LpDomain = (XPm_PsLpDomain *)XPmPower_GetById(PM_POWER_LPD);
if (NULL == LpDomain) {
goto done;
}
XPm_Device *AmsRoot = XPmDevice_GetById(PM_DEV_AMS_ROOT);
if (NULL == AmsRoot) {
Status = XST_FAILURE;
goto done;
}
/* Unlock configuration and system registers for write operation */
PmOut32(AmsRoot->Node.BaseAddress + AMS_ROOT_REG_PCSR_LOCK_OFFSET,
PCSR_UNLOCK_VAL);
/* Disable the SSC interface to PS LPD satellite */
PmRmw32(AmsRoot->Node.BaseAddress + AMS_ROOT_TOKEN_MNGR_OFFSET,
AMS_ROOT_TOKEN_MNGR_BYPASS_LPD_MASK,
AMS_ROOT_TOKEN_MNGR_BYPASS_LPD_MASK);
/* Lock configuration and system registers */
PmOut32(AmsRoot->Node.BaseAddress + AMS_ROOT_REG_PCSR_LOCK_OFFSET, 1);
/* Isolate PS_PL */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_PL_TEST, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_PL, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate PS_CPM domains */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_CPM_DFX, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_CPM, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate LP-SoC */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate PS_PMC domains */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_LPD_DFX, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_LPD, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Assert reset for PS SRST */
Status = XPmReset_AssertbyId(PM_RST_PS_SRST, (u32)PM_RESET_ACTION_ASSERT);
/* Assert POR for PS-LPD */
Status = XPmReset_AssertbyId(PM_RST_PS_POR, (u32)PM_RESET_ACTION_ASSERT);
/*TODO: Send PMC_I2C command to turn off PS-LPD power rail */
LpDomain->LpdBisrFlags &= (u8)(~(LPD_BISR_DATA_COPIED | LPD_BISR_DONE));
done:
if (XST_SUCCESS != Status) {
PmErr("Returned %d\r\n", Status);
}
return Status;
}
XStatus XPm_PowerUpFPD(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
XPm_Psm *Psm;
/*
* Power up FPD power rail
* Compiler flag CUSTOM_PMBUS must be set
*/
Status = XPmBoard_ControlRail(RAIL_POWER_UP, POWER_RAIL_FPD);
if (XST_SUCCESS != Status) {
PmErr("Control power rail for FPD failure during power up\r\n");
goto done;
}
Psm = (XPm_Psm *)XPmDevice_GetById(PM_DEV_PSM_PROC);
if (NULL == Psm) {
Status = XST_FAILURE;
goto done;
}
if ((u8)XPM_POWER_STATE_ON != Node->State) {
/* Restore the PSM APU power state register */
PmOut32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_APU_POWER_STATUS_INIT_OFFSET, PsmApuPwrState);
PmInfo("Reloading FPD CDO\r\n");
Status = XLoader_ReloadImage(Node->Id);
if (XST_SUCCESS != Status) {
PmErr("Error while reloading FPD CDO\r\n");
}
XPm_GicProxy.Clear();
}
done:
return Status;
}
XStatus XPm_PowerDwnFPD(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
XPm_Psm *Psm;
XPm_Core *ApuCore = (XPm_Core *)XPmDevice_GetById(PM_DEV_ACPU_0);
XPm_Device *AmsRoot = XPmDevice_GetById(PM_DEV_AMS_ROOT);
if (NULL == AmsRoot) {
goto done;
}
/* Unlock configuration and system registers for write operation */
PmOut32(AmsRoot->Node.BaseAddress + AMS_ROOT_REG_PCSR_LOCK_OFFSET,
PCSR_UNLOCK_VAL);
/* Disable the SSC interface to PS FPD satellite */
PmRmw32(AmsRoot->Node.BaseAddress + AMS_ROOT_TOKEN_MNGR_OFFSET,
AMS_ROOT_TOKEN_MNGR_BYPASS_FPD_MASK,
AMS_ROOT_TOKEN_MNGR_BYPASS_FPD_MASK);
/* Lock configuration and system registers */
PmOut32(AmsRoot->Node.BaseAddress + AMS_ROOT_REG_PCSR_LOCK_OFFSET, 1);
/* Isolate FPD-NoC */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_FPD_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate FPD-PL */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_FPD_PL, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_FPD_PL_TEST, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPsm_SendPowerDownReq(Node->BaseAddress);
/* Assert SRST for FPD */
Status = XPmReset_AssertbyId(PM_RST_FPD, (u32)PM_RESET_ACTION_ASSERT);
/* Assert POR for FPD */
Status = XPmReset_AssertbyId(PM_RST_FPD_POR, (u32)PM_RESET_ACTION_ASSERT);
/*
* Power down FPD power rail
* Compiler flag CUSTOM_PMBUS must be set
*/
Status = XPmBoard_ControlRail(RAIL_POWER_DOWN, POWER_RAIL_FPD);
if (XST_SUCCESS != Status) {
PmErr("Control power rail for FPD failure during power down\r\n");
goto done;
}
Psm = (XPm_Psm *)XPmDevice_GetById(PM_DEV_PSM_PROC);
if (NULL == Psm) {
Status = XST_FAILURE;
goto done;
}
/* Enable GIC proxy only if resume path is set */
if ((NULL != ApuCore) &&
(XST_SUCCESS == ApuCore->CoreOps->HasResumeAddr(ApuCore))) {
XPm_GicProxy.Enable();
/* Store the PSM APU power state register */
PmIn32(Psm->PsmGlobalBaseAddr + PSM_GLOBAL_APU_POWER_STATUS_INIT_OFFSET, PsmApuPwrState);
}
done:
return Status;
}
XStatus XPm_PowerUpPLD(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
if ((u8)XPM_POWER_STATE_ON == Node->State) {
Status = XST_SUCCESS;
goto done;
} else {
/* TODO: PLD CDO should be rexecuted. Right now we don't have separate PLD
* CDO so calling house cleaning commands here
*/
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_INIT_START, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_HOUSECLEAN_PL, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_INIT_FINISH, NULL, 0);
}
done:
return Status;
}
XStatus XPm_PowerDwnPLD(void)
{
XStatus Status = XST_FAILURE;
/* Isolate PL-NoC */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate FPD-PL */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_FPD_PL, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_FPD_PL_TEST, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate LPD-PL */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_PL, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_PL_TEST, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate PL-PMC */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_PL, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_PL_TEST, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_PL_CFRAME, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate VCCINT_RAM from VCCINT */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_VCCRAM_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_VCCAUX_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_VCCAUX_VCCRAM, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate PL_CPM */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_CPM_PCIEA0_ATTR, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_CPM_PCIEA1_ATTR, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_CPM_RST_CPI0, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_CPM_RST_CPI1, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Reset Houseclean flag for PL */
HcleanDone = 0U;
/* Assert POR PL */
Status = XPmReset_AssertbyId(PM_RST_PL_POR, (u32)PM_RESET_ACTION_ASSERT);
/* TODO: Send PMC_I2C command to turn of PLD power rail */
done:
return Status;
}
XStatus XPm_PowerUpME(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
(void)Node;
/* TODO: Reload ME CDO */
Status = XST_SUCCESS;
return Status;
}
XStatus XPm_PowerDwnME(void)
{
XStatus Status = XST_FAILURE;
/* TODO: Isolate ME */
/* TODO: Assert POR ME */
/* TODO: Send PMC_I2C command to turn of ME power rail */
Status = XST_SUCCESS;
return Status;
}
XStatus XPm_PowerUpCPM(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
(void)Node;
/* TODO: Reload CPM CDO */
Status = XST_SUCCESS;
return Status;
}
XStatus XPm_PowerDwnCPM(void)
{
XStatus Status = XST_FAILURE;
/* Isolate LPD-CPM */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_CPM, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_CPM_DFX, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate PL_CPM */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_CPM_PCIEA0_ATTR, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_CPM_PCIEA1_ATTR, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_CPM_RST_CPI0, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_CPM_RST_CPI1, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Assert POR for CPM */
Status = XPmReset_AssertbyId(PM_RST_CPM_POR, (u32)PM_RESET_ACTION_ASSERT);
/* TODO: Send PMC_I2C command to turn off CPM power rail */
done:
return Status;
}
XStatus XPm_PowerUpNoC(XPm_Node *Node)
{
XStatus Status = XST_FAILURE;
if ((u8)XPM_POWER_STATE_ON == Node->State) {
Status = XST_SUCCESS;
goto done;
} else {
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_INIT_START, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_SCAN_CLEAR, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_BISR, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_MBIST_CLEAR, NULL, 0);
if (XST_SUCCESS != Status) {
goto done;
}
Status = XPmPowerDomain_InitDomain((XPm_PowerDomain *)Node, (u32)FUNC_INIT_FINISH, NULL, 0);
}
done:
return Status;
}
XStatus XPm_PowerDwnNoC(void)
{
XStatus Status = XST_FAILURE;
XPm_Device *AmsRoot = XPmDevice_GetById(PM_DEV_AMS_ROOT);
XPm_NpDomain *NpDomain = (XPm_NpDomain *)XPmPower_GetById(PM_POWER_NOC);
if ((NULL == AmsRoot) || (NULL == NpDomain)) {
Status = XST_FAILURE;
goto done;
}
/* Unlock configuration and system registers for write operation */
PmOut32(AmsRoot->Node.BaseAddress + AMS_ROOT_REG_PCSR_LOCK_OFFSET,
PCSR_UNLOCK_VAL);
/* PL satellite depends on NPD and not PLD so disable the SSC interface to PL satellite
while powering down NPD*/
PmRmw32(AmsRoot->Node.BaseAddress + AMS_ROOT_TOKEN_MNGR_OFFSET,
AMS_ROOT_TOKEN_MNGR_BYPASS_PL_MASK,
AMS_ROOT_TOKEN_MNGR_BYPASS_PL_MASK);
/* Lock configuration and system registers */
PmOut32(AmsRoot->Node.BaseAddress + AMS_ROOT_REG_PCSR_LOCK_OFFSET, 1);
/* Isolate FPD-NoC domain */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_FPD_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate LPD-NoC domain */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_LPD_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate PL-NoC domain */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PL_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate VCCAUX-NoC domain */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_VCCAUX_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate VCCRAM-NoC domain */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_VCCRAM_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate PMC-NoC domain */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_SOC, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Isolate PMC-NoC NPI domain */
Status = XPmDomainIso_Control((u32)XPM_NODEIDX_ISO_PMC_SOC_NPI, TRUE_VALUE);
if (XST_SUCCESS != Status) {
goto done;
}
/* Assert POR for NoC */
Status = XPmReset_AssertbyId(PM_RST_NOC_POR, (u32)PM_RESET_ACTION_ASSERT);
/* TODO: Send PMC_I2C command to turn off NoC power rail */
NpDomain->BisrDataCopied = 0;
done:
return Status;
}
XStatus XPmPower_CheckPower(u32 VoltageRailMask)
{
XStatus Status = XST_FAILURE;
u32 RegVal;
XPm_Pmc *Pmc;
Pmc = (XPm_Pmc *)XPmDevice_GetById(PM_DEV_PMC_PROC);
if (NULL == Pmc) {
Status = XST_SUCCESS;
goto done;
}
PmIn32(Pmc->PmcGlobalBaseAddr + PWR_SUPPLY_STATUS_OFFSET, RegVal);
if((RegVal & VoltageRailMask) != VoltageRailMask) {
Status = XST_FAILURE;
goto done;
}
Status = XST_SUCCESS;
done:
return Status;
}
static void XPmPower_UpdateResetFlags(XPm_PowerDomain *PwrDomain,
enum XPmInitFunctions FuncId)
{
XPm_ResetNode *Reset;
u32 ResetId;
u32 PmcSysResetMask = (CRP_RESET_REASON_SLR_SYS_MASK |
CRP_RESET_REASON_SW_SYS_MASK |
CRP_RESET_REASON_ERR_SYS_MASK |
CRP_RESET_REASON_DAP_SYS_MASK);
u32 DomainStatusMask = (u32)1U << (NODEINDEX(PwrDomain->Power.Node.Id) - 1U);
/* Clear System Reset and domain POR reset flags */
SystemResetFlag = 0;
DomainPORFlag = 0;
if (FUNC_INIT_FINISH == FuncId) {
/*
* Mark domain init status bit in DomainInitStatusReg if
* initialization is done.
*/
if (PwrDomain->InitFlag == PwrDomain->InitMask) {
PmRmw32(XPM_DOMAIN_INIT_STATUS_REG, DomainStatusMask,
DomainStatusMask);
}
} else if (FUNC_INIT_START == FuncId) {
PwrDomain->InitFlag = 0;
/*
* All sequences should be executed on PMC_POR. During PMC_POR
* power domain bit in XPM_DOMAIN_INIT_STATUS_REG is 0. So
* don't set DomainPORFlag or SystemResetFlag flags.
*/
if (0U == (XPm_In32(XPM_DOMAIN_INIT_STATUS_REG) &
DomainStatusMask)) {
goto done;
}
switch (NODEINDEX(PwrDomain->Power.Node.Id)) {
case (u32)XPM_NODEIDX_POWER_LPD:
ResetId = PM_RST_PS_POR;
break;
case (u32)XPM_NODEIDX_POWER_FPD:
ResetId = PM_RST_FPD_POR;
break;
case (u32)XPM_NODEIDX_POWER_NOC:
ResetId = PM_RST_NOC_POR;
break;
case (u32)XPM_NODEIDX_POWER_CPM:
ResetId = PM_RST_CPM_POR;
break;
default:
ResetId = 0;
break;
}
/* Check for POR reset for a domain is occurred or not. */
if (0U != ResetId) {
Reset = XPmReset_GetById(ResetId);
if (XPM_RST_STATE_ASSERTED ==
Reset->Ops->GetState(Reset)) {
DomainPORFlag = 1;
goto done;
}
}
/* Check for system reset is occurred or not. */
if (0U != (ResetReason & PmcSysResetMask)) {
SystemResetFlag = 1;
}
} else {
/* Required by MISRA */
}
done:
return;
}
XStatus XPmPowerDomain_InitDomain(XPm_PowerDomain *PwrDomain, u32 Function,
u32 *Args, u32 NumArgs)
{
XStatus Status = XST_FAILURE;
struct XPm_PowerDomainOps *Ops = PwrDomain->DomainOps;
if (((u8)XPM_POWER_STATE_ON == PwrDomain->Power.Node.State) && (Function != (u32)FUNC_XPPU_CTRL)) {
Status = XST_SUCCESS;
goto done;
}
/* Check PL power up at every init node command to see if we can run Pl houseclean*/
(void)XPmPlDomain_InitandHouseclean();
switch (Function) {
case (u32)FUNC_INIT_START:
PwrDomain->Power.Node.State = (u8)XPM_POWER_STATE_INITIALIZING;
XPmPower_UpdateResetFlags(PwrDomain, FUNC_INIT_START);
if ((NULL != Ops) && (NULL != Ops->InitStart)) {
Status = Ops->InitStart(Args, NumArgs);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XST_SUCCESS;
break;
case (u32)FUNC_INIT_FINISH:
if ((u8)XPM_POWER_STATE_INITIALIZING != PwrDomain->Power.Node.State) {
Status = XST_FAILURE;
goto done;
}
if ((NULL != Ops) && (NULL != Ops->InitFinish)) {
Status = Ops->InitFinish(Args, NumArgs);
if (XST_SUCCESS != Status) {
goto done;
}
}
PwrDomain->Power.Node.State = (u8)XPM_POWER_STATE_ON;
if (PM_POWER_PLD == PwrDomain->Power.Node.Id) {
/* Request PLD0 device once PL is housecleaned. */
Status = XPmDevice_Request(PM_SUBSYS_PMC, PM_DEV_PLD_0,
XPM_MAX_CAPABILITY,
XPM_MAX_QOS);
if (XST_SUCCESS != Status) {
break;
}
} else if (PM_POWER_ME == PwrDomain->Power.Node.Id) {
/* Request AIE device once AIE intialization is done. */
Status = XPmDevice_Request(PM_SUBSYS_PMC, PM_DEV_AIE,
XPM_MAX_CAPABILITY,
XPM_MAX_QOS);
if (XST_SUCCESS != Status) {
break;
}
} else {
/* Required for MISRA */
}
Status = XPmDomainIso_ProcessPending(PwrDomain->Power.Node.Id);
if (XST_SUCCESS != Status) {
goto done;
}
XPmPower_UpdateResetFlags(PwrDomain, FUNC_INIT_FINISH);
Status = XST_SUCCESS;
break;
case (u32)FUNC_SCAN_CLEAR:
if ((u8)XPM_POWER_STATE_INITIALIZING != PwrDomain->Power.Node.State) {
Status = XST_FAILURE;
goto done;
}
/* Skip in case of system reset or POR of a domain */
/* HACK: Don't skip scanclear for AIE */
if (((1U == SystemResetFlag) || (1U == DomainPORFlag)) &&
(PwrDomain->Power.Node.Id != PM_POWER_ME)) {
Status = XST_SUCCESS;
goto done;
}
if ((NULL != Ops) && (NULL != Ops->ScanClear)) {
Status = Ops->ScanClear(Args, NumArgs);
if (XST_SUCCESS != Status) {
goto done;
}
PwrDomain->InitFlag |= BIT(FUNC_SCAN_CLEAR);
}
Status = XST_SUCCESS;
break;
case (u32)FUNC_BISR:
if ((u8)XPM_POWER_STATE_INITIALIZING != PwrDomain->Power.Node.State) {
Status = XST_FAILURE;
goto done;
}
/* Skip in case of system reset */
if ((1U == SystemResetFlag) &&
(PwrDomain->Power.Node.Id != PM_POWER_NOC)) {
Status = XST_SUCCESS;
goto done;
}
if ((NULL != Ops) && (NULL != Ops->Bisr)) {
Status = Ops->Bisr(Args, NumArgs);
if (XST_SUCCESS != Status) {
goto done;
}
PwrDomain->InitFlag |= BIT(FUNC_BISR);
}
Status = XST_SUCCESS;
break;
case (u32)FUNC_LBIST:
if ((u8)XPM_POWER_STATE_INITIALIZING != PwrDomain->Power.Node.State) {
Status = XST_FAILURE;
goto done;
}
/* Skip in case of system reset or POR of a domain */
if ((1U == SystemResetFlag) || (1U == DomainPORFlag)) {
Status = XST_SUCCESS;
goto done;
}
if ((NULL != Ops) && (NULL != Ops->Lbist)) {
Status = Ops->Lbist(Args, NumArgs);
if (XST_SUCCESS != Status) {
goto done;
}
PwrDomain->InitFlag |= BIT(FUNC_LBIST);
}
Status = XST_SUCCESS;
break;
case (u32)FUNC_MBIST_CLEAR:
if ((u8)XPM_POWER_STATE_INITIALIZING != PwrDomain->Power.Node.State) {
Status = XST_FAILURE;
goto done;
}
/* Skip in case of system reset or POR of a domain */
if ((1U == SystemResetFlag) || (1U == DomainPORFlag)) {
Status = XST_SUCCESS;
goto done;
}
if ((NULL != Ops) && (NULL != Ops->Mbist)) {
Status = Ops->Mbist(Args, NumArgs);
if (XST_SUCCESS != Status) {
goto done;
}
PwrDomain->InitFlag |= BIT(FUNC_MBIST_CLEAR);
}
Status = XST_SUCCESS;
break;
case (u32)FUNC_HOUSECLEAN_PL:
if ((u8)XPM_POWER_STATE_INITIALIZING != PwrDomain->Power.Node.State) {
Status = XST_FAILURE;
goto done;
}
if ((NULL != Ops) && (NULL != Ops->PlHouseclean)) {
Status = Ops->PlHouseclean(Args, NumArgs);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XST_SUCCESS;
break;
case (u32)FUNC_MEM_INIT:
if ((u8)XPM_POWER_STATE_INITIALIZING != PwrDomain->Power.Node.State) {
Status = XST_FAILURE;
goto done;
}
if ((NULL != Ops) && (NULL != Ops->MemInit)) {
Status = Ops->MemInit(Args, NumArgs);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XST_SUCCESS;
break;
case (u32)FUNC_HOUSECLEAN_COMPLETE:
if ((u8)XPM_POWER_STATE_INITIALIZING != PwrDomain->Power.Node.State) {
Status = XST_FAILURE;
goto done;
}
if ((NULL != Ops) && (NULL != Ops->HcComplete)) {
Status = Ops->HcComplete(Args, NumArgs);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XST_SUCCESS;
break;
case (u32)FUNC_XPPU_CTRL:
if ((u8)XPM_POWER_STATE_ON != PwrDomain->Power.Node.State) {
Status = XST_FAILURE;
goto done;
}
if ((NULL != Ops) && (NULL != Ops->XppuCtrl)) {
Status = Ops->XppuCtrl(Args, NumArgs);
if (XST_SUCCESS != Status) {
goto done;
}
}
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
done:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_psm.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PSM_H_
#define XPM_PSM_H_
#include "xpm_core.h"
#ifdef __cplusplus
extern "C" {
#endif
/* PSM Global Registers */
#define PSM_GLOBAL_CNTRL (0x00000000U)
#define PSM_GLOBAL_PWR_STATE (0x00000100U)
#define PSM_GLOBAL_REQ_PWRUP_EN (0x00000118U)
#define PSM_GLOBAL_REQ_PWRUP_TRIG (0x00000120U)
#define PSM_GLOBAL_REQ_PWRDWN_STAT (0x00000210U)
#define PSM_GLOBAL_REQ_PWRDWN_EN (0x00000218U)
#define PSM_GLOBAL_REQ_PWRDWN_TRIG (0x00000220U)
#define PSM_GLOBAL_PWR_CTRL_EN (0x0000071CU)
#define PSM_GLOBAL_PWR_CTRL_DIS (0x00000720U)
#define PSM_GLOBAL_PWR_CTRL_TRIG (0x00000724U)
#define PSM_GLOBAL_WAKEUP_EN (0x00000708U)
#define PSM_GLOBAL_WAKEUP_DIS (0x0000070CU)
#define PSM_GLOBAL_WAKEUP_TRIG (0x00000710U)
#define PSM_GLOBAL_REG_GLOBAL_CNTRL_FW_IS_PRESENT_MASK (0x00000010U)
#define XPM_PSM_WAKEUP_MASK BIT(2)
#define XPM_MAX_POLL_TIMEOUT (0x10000000U)
#define ENABLE_WFI(BitMask) XPmPsm_RegWrite(PSM_GLOBAL_PWR_CTRL_EN, BitMask)
#define DISABLE_WFI(BitMask) XPmPsm_RegWrite(PSM_GLOBAL_PWR_CTRL_DIS, BitMask)
#define ENABLE_WAKE(BitMask) XPmPsm_RegWrite(PSM_GLOBAL_WAKEUP_EN, BitMask)
#define DISABLE_WAKE(BitMask) XPmPsm_RegWrite(PSM_GLOBAL_WAKEUP_DIS, BitMask)
typedef struct XPm_Psm XPm_Psm;
/**
* The PSM processor class.
*/
struct XPm_Psm {
XPm_Core Core; /**< Processor core device */
u32 PsmGlobalBaseAddr; /**< PSM Global register module base address */
u32 CrlBaseAddr; /**< CRL module base address */
};
/************************** Function Prototypes ******************************/
XStatus XPmPsm_Init(XPm_Psm *Psm,
u32 Ipi,
u32 *BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock, XPm_ResetNode *Reset);
XStatus XPmPsm_SendPowerUpReq(u32 BitMask);
XStatus XPmPsm_SendPowerDownReq(u32 BitMask);
u32 XPmPsm_FwIsPresent(void);
void XPmPsm_RegWrite(const u32 Offset, const u32 Value);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_PSM_H_ */
<file_sep>/vitis_workspace/test_proj_ethernet/src/echo.c
/*
* Copyright (C) 2009 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include <string.h>
#include "lwip/err.h"
#include "lwip/tcp.h"
#if defined (__arm__) || defined (__aarch64__)
#include "xil_printf.h"
#endif
int transfer_data() {
return 0;
}
void print_app_header()
{
#if (LWIP_IPV6==0)
xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
#else
xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
#endif
xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
}
err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
struct pbuf *p, err_t err)
{
/* do not read the packet if we are not in ESTABLISHED state */
if (!p) {
tcp_close(tpcb);
tcp_recv(tpcb, NULL);
return ERR_OK;
}
/* indicate that the packet has been received */
tcp_recved(tpcb, p->len);
/* echo back the payload */
/* in this case, we assume that the payload is < TCP_SND_BUF */
if (tcp_sndbuf(tpcb) > p->len) {
//Load whatever was in the payload into the UART queue
//Replace all of the packed payload with 0s and send it back
err = tcp_write(tpcb, p->payload, p->len, 1);
} else
xil_printf("no space in tcp_sndbuf\n\r");
/* free the received pbuf */
pbuf_free(p);
return ERR_OK;
}
err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
{
static int connection = 1;
/* set the receive callback for this connection */
tcp_recv(newpcb, recv_callback);
/* just use an integer number indicating the connection id as the
callback argument */
tcp_arg(newpcb, (void*)(UINTPTR)connection);
/* increment for subsequent accepted connections */
connection++;
return ERR_OK;
}
int start_application()
{
struct tcp_pcb *pcb;
err_t err;
unsigned port = 7;
/* create new TCP PCB structure */
pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
if (!pcb) {
xil_printf("Error creating PCB. Out of Memory\n\r");
return -1;
}
/* bind to specified @port */
err = tcp_bind(pcb, IP_ANY_TYPE, port);
if (err != ERR_OK) {
xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
return -2;
}
/* we do not need any arguments to callback functions */
tcp_arg(pcb, NULL);
/* listen for connections */
pcb = tcp_listen(pcb);
if (!pcb) {
xil_printf("Out of memory while tcp_listen\n\r");
return -3;
}
/* specify callback to use for incoming connections */
tcp_accept(pcb, accept_callback);
xil_printf("TCP echo server started @ port %d\n\r", port);
return 0;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/client/pm_callbacks.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "pm_callbacks.h"
static XPm_Notifier* NotifierList = NULL;
/****************************************************************************/
/**
* @brief Add notifier into the list
*
* @param Notifier Pointer to notifier object which needs to be added
* in the list
*
* @return Returns XST_SUCCESS if notifier is added /
* XST_INVALID_PARAM if given notifier argument is NULL
*
* @note None
*
****************************************************************************/
XStatus XPm_NotifierAdd(XPm_Notifier* const Notifier)
{
XStatus Status = (s32)XST_FAILURE;
if (NULL == Notifier) {
Status = (s32)XST_INVALID_PARAM;
goto done;
}
Notifier->received = 0U;
/* New notifiers are added at the front of list */
Notifier->next = NotifierList;
NotifierList = Notifier;
Status = (s32)XST_SUCCESS;
done:
return Status;
}
/****************************************************************************/
/**
* @brief Remove notifier from the list
*
* @param Notifier Pointer to notifier object to be removed from list
*
* @return Returns XST_SUCCESS if notifier is removed /
* XST_INVALID_PARAM if given notifier pointer is NULL /
* XST_FAILURE if notifier is not found
*
* @note None
*
****************************************************************************/
XStatus XPm_NotifierRemove(XPm_Notifier* const Notifier)
{
XStatus Status = (s32)XST_FAILURE;
XPm_Notifier* Curr;
XPm_Notifier* Prev = NULL;
if (NULL == Notifier) {
Status = (s32)XST_INVALID_PARAM;
goto done;
}
Curr = NotifierList;
while (NULL != Curr) {
if (Notifier == Curr) {
if (NULL != Prev) {
Prev->next = Curr->next;
} else {
NotifierList = Curr->next;
}
Status = (s32)XST_SUCCESS;
break;
}
Prev = Curr;
Curr = Curr->next;
}
done:
return Status;
}
/****************************************************************************/
/**
* @brief Call to process notification event
*
* @param Node Device which is the subject of notification
* @param Event Event which is the subject of notification
* @param Oppoint Operating point of the device in question
*
* @return None
*
* @note None
*
****************************************************************************/
void XPm_NotifierProcessEvent(const u32 Node, const enum XPmNotifyEvent Event,
const u32 Oppoint)
{
XPm_Notifier* Notifier = NULL;
/* Validate the notifier list */
if (NULL != NotifierList) {
Notifier = NotifierList;
}
while (NULL != Notifier) {
if ((Node == Notifier->node) &&
(Event == Notifier->event)) {
Notifier->oppoint = Oppoint;
Notifier->received++;
if (NULL != Notifier->callback) {
Notifier->callback(Notifier);
}
/* There could be multiple pairs with different notifiers */
}
Notifier = Notifier->next;
}
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/resetps_v1_3/src/xresetps_sinit.c
/******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xresetps_sinit.c
* @addtogroup xresetps_v1_3
* @{
*
* This file contains method for static initialization (compile-time) of the
* driver.
*
* <pre>
* MODIFICATION HISTORY:
* Ver Who Date Changes
* ----- ------ -------- ----------------------------------------------
* 1.00 cjp 09/05/17 First release
* 1.1 Nava 04/20/18 Fixed compilation warnings.
* 1.2 cjp 04/27/18 Updated for clockps interdependency
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xresetps.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*************************** Variable Definitions ****************************/
extern XResetPs_Config XResetPs_ConfigTable[XPAR_XRESETPS_NUM_INSTANCES];
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* contains the configuration info for each device in the system.
*
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
*
******************************************************************************/
XResetPs_Config *XResetPs_LookupConfig(u16 DeviceId)
{
XResetPs_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; Index < (u32)XPAR_XRESETPS_NUM_INSTANCES; Index++) {
if (XResetPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XResetPs_ConfigTable[Index];
break;
}
}
return (XResetPs_Config *)CfgPtr;
}
/** @} */
<file_sep>/python_drivers/alice_test_run.py
# -*- coding: utf-8 -*-
"""
Created on Wed Jul 1 12:19:37 2020
@author: tianlab01
"""
import time_sync
import james_utils
import tdc_wrapper
server_ip = "192.168.56.1"
tdc = tdc_wrapper.tdc_wrapper(15,0,tdc_wrapper.MODE_CLIENT,"192.168.56.1")
ts = time_sync.time_sync(james_utils.ALICE_PORT, server_ip, time_sync.CLIENT, tdc)
ts.start_client_sync()
ts.board.close_board()<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_domain_iso.c
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpm_domain_iso.h"
#include "xpm_regs.h"
#include "xpm_powerdomain.h"
#include "xpm_device.h"
#include "xpm_pldomain.h"
/*TODO: Below data should come from topology */
static XPm_Iso XPmDomainIso_List[XPM_NODEIDX_ISO_MAX] = {
[XPM_NODEIDX_ISO_FPD_PL_TEST] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_FPD_PL_TEST),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_TEST_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_FPD, PM_DEV_PLD_0 },
},
[XPM_NODEIDX_ISO_FPD_PL] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_FPD_PL),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_FPD, PM_DEV_PLD_0 },
},
[XPM_NODEIDX_ISO_FPD_SOC] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_FPD_SOC),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_SOC_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_FPD, PM_POWER_NOC},
},
[XPM_NODEIDX_ISO_LPD_CPM_DFX] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_LPD_CPM_DFX),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_DFX_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_LPD, PM_POWER_CPM },
},
[XPM_NODEIDX_ISO_LPD_CPM] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_LPD_CPM),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_LPD, PM_POWER_CPM },
},
[XPM_NODEIDX_ISO_LPD_PL_TEST] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_LPD_PL_TEST),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_TEST_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_LPD, PM_DEV_PLD_0 },
},
[XPM_NODEIDX_ISO_LPD_PL] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_LPD_PL),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_LPD, PM_DEV_PLD_0 },
},
[XPM_NODEIDX_ISO_LPD_SOC] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_LPD_SOC),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_SOC_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_LPD, PM_POWER_NOC },
},
[XPM_NODEIDX_ISO_PMC_LPD_DFX] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PMC_LPD_DFX),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_DFX_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_PMC, PM_POWER_LPD },
},
[XPM_NODEIDX_ISO_PMC_LPD] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PMC_LPD),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_PMC, PM_POWER_LPD },
},
[XPM_NODEIDX_ISO_PMC_PL_CFRAME] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PMC_PL_CFRAME),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_PMC, PM_DEV_PLD_0 },
},
[XPM_NODEIDX_ISO_PMC_PL_TEST] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PMC_PL_TEST),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_PMC, PM_DEV_PLD_0 },
},
[XPM_NODEIDX_ISO_PMC_PL] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PMC_PL),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_PMC, PM_DEV_PLD_0 },
},
[XPM_NODEIDX_ISO_PMC_SOC_NPI] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PMC_SOC_NPI),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_NPI_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_PMC, PM_POWER_NOC },
},
[XPM_NODEIDX_ISO_PMC_SOC] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PMC_SOC),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_PMC, PM_POWER_NOC },
},
[XPM_NODEIDX_ISO_PL_SOC] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PL_SOC),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_PL_SOC_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_NOC },
},
[XPM_NODEIDX_ISO_VCCAUX_SOC] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_VCCAUX_SOC),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_SOC_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_PMC, PM_POWER_NOC },
},
[XPM_NODEIDX_ISO_VCCRAM_SOC] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_VCCRAM_SOC),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCRAM_SOC_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_NOC },
},
[XPM_NODEIDX_ISO_VCCAUX_VCCRAM] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_VCCAUX_VCCRAM),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_VCCRAM_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_NOC },
},
[XPM_NODEIDX_ISO_PL_CPM_PCIEA0_ATTR] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PL_CPM_PCIEA0_ATTR),
.Node.BaseAddress = PCIEA_ATTRIB_0_FABRICEN,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PCIEA_ATTRIB_0_FABRICEN_ATTR_SHIFT),
.Polarity = (u8)PM_ACTIVE_LOW,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_CPM },
},
[XPM_NODEIDX_ISO_PL_CPM_PCIEA1_ATTR] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PL_CPM_PCIEA1_ATTR),
.Node.BaseAddress = PCIEA_ATTRIB_1_FABRICEN,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PCIEA_ATTRIB_1_FABRICEN_ATTR_SHIFT),
.Polarity = (u8)PM_ACTIVE_LOW,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_CPM },
},
[XPM_NODEIDX_ISO_PL_CPM_RST_CPI0] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PL_CPM_RST_CPI0),
.Node.BaseAddress = CPM_CRCPM_RST_CPI0,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(CPM_CRCPM_RST_CPI0_RESET_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_CPM },
},
[XPM_NODEIDX_ISO_PL_CPM_RST_CPI1] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_PL_CPM_RST_CPI1),
.Node.BaseAddress = CPM_CRCPM_RST_CPI1,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(CPM_CRCPM_RST_CPI1_RESET_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_CPM },
},
[XPM_NODEIDX_ISO_GEM_TSU_CLK] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_GEM_TSU_CLK),
.Node.BaseAddress = CRL_RCLK_CTRL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = CRL_RCLK_CTRL_CLKACT_GEM_TSU_MASK,
.Polarity = (u8)PM_ACTIVE_LOW,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_LPD },
},
[XPM_NODEIDX_ISO_GEM0_TXRX_CLK] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_GEM0_TXRX_CLK),
.Node.BaseAddress = CRL_RCLK_CTRL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = CRL_RCLK_CTRL_CLKACT_GEM0_TXRX_MASK,
.Polarity = (u8)PM_ACTIVE_LOW,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_LPD },
},
[XPM_NODEIDX_ISO_GEM1_TXRX_CLK] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_GEM1_TXRX_CLK),
.Node.BaseAddress = CRL_RCLK_CTRL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = CRL_RCLK_CTRL_CLKACT_GEM1_TXRX_MASK,
.Polarity = (u8)PM_ACTIVE_LOW,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_LPD },
},
[XPM_NODEIDX_ISO_LPD_CPM5_DFX] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_LPD_CPM5_DFX),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_DFX_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_LPD, PM_POWER_CPM5 },
},
[XPM_NODEIDX_ISO_LPD_CPM5] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_LPD_CPM5),
.Node.BaseAddress = PMC_GLOBAL_DOMAIN_ISO_CONTROL,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = BIT(PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_SHIFT),
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_POWER_LPD, PM_POWER_CPM5 },
},
[XPM_NODEIDX_ISO_XRAM_PL_AXI0] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_XRAM_PL_AXI0),
.Node.BaseAddress = XRAM_SLCR_BASEADDR + XRAM_SLCR_PCSR_PCR_OFFSET,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = XRAM_SLCR_PCSR_ODISABLE_PL_AXI0_MASK,
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_LPD },
},
[XPM_NODEIDX_ISO_XRAM_PL_AXI1] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_XRAM_PL_AXI1),
.Node.BaseAddress = XRAM_SLCR_BASEADDR + XRAM_SLCR_PCSR_PCR_OFFSET,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = XRAM_SLCR_PCSR_ODISABLE_PL_AXI1_MASK,
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_LPD },
},
[XPM_NODEIDX_ISO_XRAM_PL_AXI2] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_XRAM_PL_AXI2),
.Node.BaseAddress = XRAM_SLCR_BASEADDR + XRAM_SLCR_PCSR_PCR_OFFSET,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = XRAM_SLCR_PCSR_ODISABLE_PL_AXI2_MASK,
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_LPD },
},
[XPM_NODEIDX_ISO_XRAM_PL_AXILITE] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_XRAM_PL_AXILITE),
.Node.BaseAddress = XRAM_SLCR_BASEADDR + XRAM_SLCR_PCSR_PCR_OFFSET,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = XRAM_SLCR_PCSR_ODISABLE_PL_AXILITE_MASK,
.Polarity = (u8)PM_ACTIVE_HIGH,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_LPD },
},
[XPM_NODEIDX_ISO_XRAM_PL_FABRIC] = {
.Node.Id = ISOID(XPM_NODEIDX_ISO_XRAM_PL_FABRIC),
.Node.BaseAddress = XRAM_SLCR_BASEADDR + XRAM_SLCR_PCSR_PCR_OFFSET,
.Node.State = (u8)PM_ISOLATION_ON,
.Mask = XRAM_SLCR_PCSR_FABRICEN_MASK,
.Polarity = (u8)PM_ACTIVE_LOW,
.DependencyNodeHandles = { PM_DEV_PLD_0, PM_POWER_LPD },
},
};
static XStatus XPmDomainIso_CheckDependencies(u32 IsoIdx)
{
XStatus Status = XST_FAILURE;
u32 i=0, NodeId;
XPm_PowerDomain *PwrDomainNode;
XPm_Device *Device;
for (i = 0; i < 2U; i++) {
NodeId = XPmDomainIso_List[IsoIdx].DependencyNodeHandles[i];
if (NODECLASS(NodeId) == (u32)XPM_NODECLASS_POWER) {
PwrDomainNode = (XPm_PowerDomain *) XPmPower_GetById(NodeId);
if ((NULL != PwrDomainNode) &&
(PwrDomainNode->Power.Node.State != (u8)XPM_POWER_STATE_ON) &&
(PwrDomainNode->Power.Node.State != (u8)XPM_POWER_STATE_INITIALIZING)) {
Status = XST_FAILURE;
goto done;
}
Status = XST_SUCCESS;
} else if (PM_DEV_PLD_0 == NodeId) {
Device = XPmDevice_GetById(NodeId);
if ((NULL != Device) &&
((u8)XPM_DEVSTATE_RUNNING != Device->Node.State)) {
Status = XST_FAILURE;
}
} else {
Status = XST_FAILURE;
goto done;
}
}
done:
return Status;
}
static inline void XramIsoUnmask(u32 IsoIdx)
{
u32 BaseAddr = XRAM_SLCR_BASEADDR + XRAM_SLCR_PCSR_MASK_OFFSET;
u32 Mask = XPmDomainIso_List[IsoIdx].Mask;
XPm_RMW32(BaseAddr, Mask, Mask);
}
static inline void XramIsoMask(u32 IsoIdx)
{
u32 BaseAddr = XRAM_SLCR_BASEADDR + XRAM_SLCR_PCSR_MASK_OFFSET;
u32 Mask = XPmDomainIso_List[IsoIdx].Mask;
XPm_RMW32(BaseAddr, Mask, ~Mask);
}
static void EnablePlXramIso(void)
{
u32 i;
u32 IsoIdx = (u32)XPM_NODEIDX_ISO_XRAM_PL_FABRIC;
u32 Mask = XPmDomainIso_List[IsoIdx].Mask;
for (i = (u32)XPM_NODEIDX_ISO_XRAM_PL_AXI0;
i <= (u32)(XPM_NODEIDX_ISO_XRAM_PL_AXILITE);
++i) {
if ((u8)PM_ISOLATION_OFF == XPmDomainIso_List[i].Node.State) {
goto done;
}
}
if ((u8)PM_ISOLATION_ON != XPmDomainIso_List[IsoIdx].Node.State) {
XramIsoUnmask((u32)XPM_NODEIDX_ISO_XRAM_PL_FABRIC);
XPm_RMW32(XPmDomainIso_List[IsoIdx].Node.BaseAddress, Mask, 0);
XPmDomainIso_List[IsoIdx].Node.State = (u8)PM_ISOLATION_ON;
XramIsoMask((u32)XPM_NODEIDX_ISO_XRAM_PL_FABRIC);
}
done:
return;
}
static void DisablePlXramIso(void)
{
u32 IsoIdx = (u32)XPM_NODEIDX_ISO_XRAM_PL_FABRIC;
u32 Mask = XPmDomainIso_List[IsoIdx].Mask;
if ((u8)PM_ISOLATION_OFF != XPmDomainIso_List[IsoIdx].Node.State) {
XramIsoUnmask((u32)XPM_NODEIDX_ISO_XRAM_PL_FABRIC);
XPm_RMW32(XPmDomainIso_List[IsoIdx].Node.BaseAddress, Mask, Mask);
XPmDomainIso_List[IsoIdx].Node.State = (u8)PM_ISOLATION_OFF;
XramIsoMask((u32)XPM_NODEIDX_ISO_XRAM_PL_FABRIC);
}
return;
}
XStatus XPmDomainIso_Control(u32 IsoIdx, u32 Enable)
{
XStatus Status = XST_FAILURE;
u32 Mask;
if (IsoIdx >= (u32)XPM_NODEIDX_ISO_MAX)
{
Status = XST_INVALID_PARAM;
goto done;
}
Mask = XPmDomainIso_List[IsoIdx].Mask;
if ((IsoIdx <= (u32)XPM_NODEIDX_ISO_XRAM_PL_AXILITE) &&
(IsoIdx >= (u32)XPM_NODEIDX_ISO_XRAM_PL_AXI0)) {
XramIsoUnmask(IsoIdx);
}
if ((TRUE_VALUE == Enable) || (TRUE_PENDING_REMOVE == Enable)) {
if (XPmDomainIso_List[IsoIdx].Polarity == (u8)PM_ACTIVE_HIGH) {
XPm_RMW32(XPmDomainIso_List[IsoIdx].Node.BaseAddress, Mask, Mask);
} else {
XPm_RMW32(XPmDomainIso_List[IsoIdx].Node.BaseAddress, Mask, 0);
}
/* Mark node state appropriately */
XPmDomainIso_List[IsoIdx].Node.State = (TRUE_VALUE == Enable) ?
(u8)PM_ISOLATION_ON : (u8)PM_ISOLATION_REMOVE_PENDING;
if ((IsoIdx <= (u32)XPM_NODEIDX_ISO_XRAM_PL_AXILITE) &&
(IsoIdx >= (u32)XPM_NODEIDX_ISO_XRAM_PL_AXI0)) {
EnablePlXramIso();
}
} else if(Enable == FALSE_IMMEDIATE) {
if (XPmDomainIso_List[IsoIdx].Polarity == (u8)PM_ACTIVE_HIGH) {
XPm_RMW32(XPmDomainIso_List[IsoIdx].Node.BaseAddress, Mask, 0);
} else {
XPm_RMW32(XPmDomainIso_List[IsoIdx].Node.BaseAddress, Mask, Mask);
}
XPmDomainIso_List[IsoIdx].Node.State = (u8)PM_ISOLATION_OFF;
} else {
Status = XPmDomainIso_CheckDependencies(IsoIdx);
if(XST_SUCCESS != Status)
{
/* Mark it pending */
XPmDomainIso_List[IsoIdx].Node.State = (u8)PM_ISOLATION_REMOVE_PENDING;
Status = XST_SUCCESS;
goto done;
}
if ((IsoIdx <= (u32)XPM_NODEIDX_ISO_XRAM_PL_AXILITE) &&
(IsoIdx >= (u32)XPM_NODEIDX_ISO_XRAM_PL_AXI0)) {
DisablePlXramIso();
}
if (XPmDomainIso_List[IsoIdx].Polarity == (u8)PM_ACTIVE_HIGH) {
XPm_RMW32(XPmDomainIso_List[IsoIdx].Node.BaseAddress, Mask, 0);
} else {
XPm_RMW32(XPmDomainIso_List[IsoIdx].Node.BaseAddress, Mask, Mask);
}
XPmDomainIso_List[IsoIdx].Node.State = (u8)PM_ISOLATION_OFF;
}
Status = XST_SUCCESS;
done:
if ((IsoIdx <= (u32)XPM_NODEIDX_ISO_XRAM_PL_AXILITE) &&
(IsoIdx >= (u32)XPM_NODEIDX_ISO_XRAM_PL_AXI0)) {
XramIsoMask(IsoIdx);
}
return Status;
}
XStatus XPmDomainIso_ProcessPending(u32 PowerDomainId)
{
XStatus Status = XST_FAILURE;
u32 i;
(void)PowerDomainId;
for(i=0; i< ARRAY_SIZE(XPmDomainIso_List); i++)
{
if (XPmDomainIso_List[i].Node.State == (u8)PM_ISOLATION_REMOVE_PENDING) {
Status = XPmDomainIso_Control(i, FALSE_VALUE);
} else {
Status = XST_SUCCESS;
}
}
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilskey_v6_9/src/xilskey_eps_zynqmp.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xilskey_eps_zynqmp.c
* This file contains the PS eFUSE API's of ZynqMp to program/read the
* eFUSE array.
*
* @note None.
*
* </pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ------------------------------------------------------
* 4.0 vns 10/01/15 First release
* vns 10/20/15 Modified XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits API
* when reading from efuse memory to return both bits
* of secure control feature for RSA enable, PPK hash
* bits invalid bits.
* 6.0 vns 07/18/16 PR #1968, Provided User FUSEs single bit programming
* Removed JTAG User code programming and reading
* feature. Added temperature and voltage checks, while
* programming and reading eFUSE array. Added separate
* function to set timing parameters and sysmon PSU
* driver initialization. Added init function while
* from eFUSE. Added appropriate error codes on failure
* returns.
* vns 08/24/16 Fixed eFUSE ZynqMP programming by adding unlocking
* before eFUSE PS initialization.
* 6.2 vns 02/18/17 Added margin reads for verifying, added CRC check,
* Removed temperature checks for each bit. Added
* temperature checks in all read APIs.
* 6.4 vns 02/19/18 Added efuse cache reload call in function
* XilSKey_ZynqMp_EfusePs_Write(), so on successful
* efuse programming, programmed fuses can directly read
* from cache of the efuse.
* 6.6 vns 06/06/18 Added doxygen tags
* vns 09/18/18 Added APIs to support eFUSE programming from linux
* vns 10/11/18 Added support to re-program non-zero SPKID
* 6.7 arc 01/05/19 Fixed MISRA-C violations.
* arc 25/02/19 Added NULL checks and validations for input params
* and add timeouts and status info
* arc 03/15/19 Modified initial default status value as XST_FAILURE
* 6.7 psl 03/21/19 Fixed MISRA-C violation.
* 6.8 psl 06/07/19 Added doxygen tags
* psl 06/25/19 Fixed Coverity warnings.
* psl 06/28/19 Added doxygen tags.
* psl 07/05/19 Added Asserts for validation.
* psl 07/12/19 Corrected length of data to read for
* XilSKey_EfusePs_ConvertBytesBeToLe function.
* psl 07/23/19 Fixed input validations.
* vns 08/07/19 Fixed CTRL LOCK in XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits
* psl 08/13/19 Fixed MISRA-C violation
* vns 08/29/19 Initialized Status variables
* vns 09/17/19 Removed Tbits programming from library as they are to be
* programmed under manufacturing list.
* 6.9 kpt 02/16/20 Fixed coverity warnings
* 02/27/20 Added Error codes in
* XilSKey_ZynqMp_EfusePs_WriteBit
* 02/27/20 Removed extra ppk hash zeroes checking in
* XilSKey_ZynqMp_EfusePs_Write
* 03/18/20 Replaced while loop with Xil_WaitForEvents in
* XilSKey_ZynqMp_EfusePs_WriteBit,
* XilSKey_ZynqMp_EfusePs_ReadRow.
* vns 03/18/20 Fixed Armcc compilation errors
* kal 03/18/20 Removed Temp and Voltage check while checking AES key
* CRC.
* kpt 03/17/20 Replaced direct eFuse reads with cache reads
* and Error code is returned when user chooses
* read option as eFuse.
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files *********************************/
#include "xilskey_eps_zynqmp.h"
#include "xilskey_eps_zynqmp_hw.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions ******************************/
/*
* XilSKey_UsrFuses holds the User FUSES which needs to be
* actually programmed
*/
typedef struct {
u8 UserFuse[XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BITS];
}XilSKey_UsrFuses;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
static u8 Init_Done;
/************************** Function Prototypes *****************************/
static INLINE u32 XilSKey_ZynqMp_EfusePsWrite_Checks(
XilSKey_ZynqMpEPs *InstancePtr);
static INLINE u32 XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(u8 *Data,
u8 RowStart, u8 RowEnd, XskEfusePs_Type EfuseType);
static INLINE u32 XilSKey_ZynqMp_EfusePs_WriteBit(u8 Row, u8 Column,
XskEfusePs_Type EfuseType);
static INLINE u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrl(
XilSKey_ZynqMpEPs *InstancePtr);
static INLINE u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrlBits(
XilSKey_ZynqMpEPs *InstancePtr);
static INLINE u32 XilSKey_ZynqMp_EfusePs_Write_UsrCtrlBits(
XilSKey_ZynqMpEPs *InstancePtr);
static INLINE void XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits_Regs(
XilSKey_SecCtrlBits *ReadBackSecCtrlBits);
static INLINE u32 XilSKey_ZynqMp_EfusePs_CheckZeros_BfrPrgrmg(
XilSKey_ZynqMpEPs *InstancePtr);
static INLINE u32 XilSKey_ZynqMp_EfusePs_UserFuses_WriteChecks(
XilSKey_ZynqMpEPs *InstancePtr, XilSKey_UsrFuses *ToBePrgrmd);
static INLINE u32 XilSKey_ZynqMp_EfusePs_UserFuses_TobeProgrammed(
u8 *UserFuses_Write, u8 *UserFuses_Read,
XilSKey_UsrFuses *UserFuses_ToBePrgrmd);
void XilSKey_ZynqMp_EfusePs_SetTimerValues(void);
u32 XilSKey_ZynqMp_EfusePs_SetWriteConditions(void);
u32 XilSKey_ZynqMp_EfusePs_ReadRow(u8 Row, XskEfusePs_Type EfuseType,
u32 *RowData);
u32 XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(u8 Row, u8 Column,
XskEfusePs_Type EfuseType);
u32 XilSKey_ZynqMp_EfusePs_CheckForZeros(u8 RowStart, u8 RowEnd,
XskEfusePs_Type EfuseType);
static INLINE u32 XilSKey_ZynqMp_EfusePs_Enable_Rsa(u8 *SecBits_read);
u32 XilSKey_ZynqMp_EfusePs_Init(void);
static u32 XilSKey_ZynqMpEfuseRead(const u32 AddrHigh, const u32 AddrLow);
static u32 XilSKey_ZynqMpEfuseWrite(const u32 AddrHigh, const u32 AddrLow);
u32 XilSKey_ZynqMp_EfusePs_ReadPufChash(u32 *Address, u8 ReadOption);
static u32 XilSkey_ZynqMpUsrFuseRd(u32 Offset, u32 *Buffer, u32 Size, u8 UsrFuseNum);
/************************** Function Definitions *****************************/
/***************************************************************************/
/**
* This function is used to program the PS eFUSE of ZynqMP, based on user
* inputs
*
* @param InstancePtr Pointer to the XilSKey_ZynqMpEPs.
*
* @return
* - XST_SUCCESS if programs successfully.
* - Errorcode on failure
*
* @note After eFUSE programming is complete, the cache is automatically
* reloaded so all programmed eFUSE bits can be directly read from cache.
*
****************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_Write(XilSKey_ZynqMpEPs *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
u8 AesKeyInBits[XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BITS] = {0};
u8 Ppk0InBits[XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS] = {0};
u8 Ppk1InBits[XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS] = {0};
u8 SpkIdInBits[XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BITS] = {0};
u8 SpkIdInBitsRd[XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BITS] = {0};
XilSKey_UsrFuses UsrFuses_ToPrgm[8] = {0};
u32 AesCrc;
u32 SpkId;
u8 Column;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Initialize the ADC */
Status = XilSKey_ZynqMp_EfusePs_Init();
if (Status != (u32)XST_SUCCESS) {
goto UNLOCK;
}
/**
* Check the temperature and voltage(VCC_AUX and VCC_PINT_LP)
*/
Status = XilSKey_ZynqMp_EfusePs_Temp_Vol_Checks();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Unlock the controller */
XilSKey_ZynqMp_EfusePs_CtrlrUnLock();
/* Check the unlock status */
if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus() != 0U) {
Status = (u32)(XSK_EFUSEPS_ERROR_CONTROLLER_LOCK);
goto UNLOCK;
}
/* Conditions to check programming is possible or not */
Status = XilSKey_ZynqMp_EfusePsWrite_Checks(InstancePtr);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_BEFORE_PROGRAMMING);
goto UNLOCK;
}
if (InstancePtr->PrgrmSpkID == TRUE) {
XilSKey_Efuse_ConvertBitsToBytes((u8 *)(InstancePtr->SpkId),
SpkIdInBits, XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BITS);
SpkId = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_SPK_ID_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&SpkId,
SpkIdInBitsRd, XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BITS);
/* Check if it is poosible to program or not */
for (Column = 0U; Column < XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BITS;
Column++) {
/* If user requests a non-zero bit */
if ((SpkIdInBits[Column] == 0U) &&
(SpkIdInBitsRd[Column] == 1U)) {
Status = (u32)XSK_EFUSEPS_ERROR_BEFORE_PROGRAMMING |
(u32)XSK_EFUSEPS_ERROR_SPKID_BIT_CANT_REVERT;
goto UNLOCK;
}
if ((SpkIdInBits[Column] == 1U) &&
(SpkIdInBitsRd[Column] == 1U)) {
SpkIdInBits[Column] = 0U;
}
}
}
/* Validation of requested User FUSES bits */
Status = XilSKey_ZynqMp_EfusePs_UserFuses_WriteChecks(
InstancePtr, &UsrFuses_ToPrgm[0]);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_BEFORE_PROGRAMMING);
goto UNLOCK;
}
/* Setting all the conditions for writing into eFuse */
Status = XilSKey_ZynqMp_EfusePs_SetWriteConditions();
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_BEFORE_PROGRAMMING);
goto END;
}
/* Check for Zeros for Programming eFuse */
Status = XilSKey_ZynqMp_EfusePs_CheckZeros_BfrPrgrmg(InstancePtr);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_BEFORE_PROGRAMMING);
goto END;
}
if (InstancePtr->PrgrmAesKey == TRUE) {
XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->AESKey,
AesKeyInBits, XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BITS);
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
AesKeyInBits,XSK_ZYNQMP_EFUSEPS_AES_KEY_START_ROW,
XSK_ZYNQMP_EFUSEPS_AES_KEY_END_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_AES_KEY);
goto END;
}
/* Reload cache to verify CRC of programmed AES key */
Status = XilSKey_ZynqMp_EfusePs_CacheLoad();
if (Status != (u32)XST_SUCCESS) {
Status = Status | (u32)XSK_EFUSEPS_ERROR_VERIFICATION |
(u32)XSK_EFUSEPS_ERROR_WRITE_AES_KEY;
goto END;
}
/* Calculates AES key's CRC */
AesCrc = XilSkey_CrcCalculation_AesKey(&InstancePtr->AESKey[0]);
/* Verifies the Aes key programmed with CRC */
Status = XilSKey_ZynqMp_EfusePs_CheckAesKeyCrc(AesCrc);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)XSK_EFUSEPS_ERROR_VERIFICATION |
(u32)XSK_EFUSEPS_ERROR_WRITE_AES_KEY;
goto END;
}
}
if (InstancePtr->PrgrmUser0Fuse == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
UsrFuses_ToPrgm[XSK_ZYNQMP_EFUSEPS_USR0_FUSE].UserFuse,
XSK_ZYNQMP_EFUSEPS_USR0_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_USR0_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_USER0_FUSE);
goto END;
}
}
if (InstancePtr->PrgrmUser1Fuse == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
UsrFuses_ToPrgm[XSK_ZYNQMP_EFUSEPS_USR1_FUSE].UserFuse,
XSK_ZYNQMP_EFUSEPS_USR1_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_USR1_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_USER1_FUSE);
goto END;
}
}
if (InstancePtr->PrgrmUser2Fuse == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
UsrFuses_ToPrgm[XSK_ZYNQMP_EFUSEPS_USR2_FUSE].UserFuse,
XSK_ZYNQMP_EFUSEPS_USR2_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_USR2_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_USER2_FUSE);
goto END;
}
}
if (InstancePtr->PrgrmUser3Fuse == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
UsrFuses_ToPrgm[XSK_ZYNQMP_EFUSEPS_USR3_FUSE].UserFuse,
XSK_ZYNQMP_EFUSEPS_USR3_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_USR3_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_USER3_FUSE);
goto END;
}
}
if (InstancePtr->PrgrmUser4Fuse == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
UsrFuses_ToPrgm[XSK_ZYNQMP_EFUSEPS_USR4_FUSE].UserFuse,
XSK_ZYNQMP_EFUSEPS_USR4_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_USR4_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_USER4_FUSE);
goto END;
}
}
if (InstancePtr->PrgrmUser5Fuse == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
UsrFuses_ToPrgm[XSK_ZYNQMP_EFUSEPS_USR5_FUSE].UserFuse,
XSK_ZYNQMP_EFUSEPS_USR5_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_USR5_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_USER5_FUSE);
goto END;
}
}
if (InstancePtr->PrgrmUser6Fuse == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
UsrFuses_ToPrgm[XSK_ZYNQMP_EFUSEPS_USR6_FUSE].UserFuse,
XSK_ZYNQMP_EFUSEPS_USR6_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_USR6_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_USER6_FUSE);
goto END;
}
}
if (InstancePtr->PrgrmUser7Fuse == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
UsrFuses_ToPrgm[XSK_ZYNQMP_EFUSEPS_USR7_FUSE].UserFuse,
XSK_ZYNQMP_EFUSEPS_USR7_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_USR7_FUSE_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_USER7_FUSE);
goto END;
}
}
if (InstancePtr->PrgrmSpkID == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
SpkIdInBits, XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW,
XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_SPK_ID);
goto END;
}
}
if (InstancePtr->PrgrmPpk0Hash == TRUE) {
/* Programming SHA3 hash(384 bit) into Efuse PPK0 */
XilSKey_Efuse_ConvertBitsToBytes(
InstancePtr->Ppk0Hash, Ppk0InBits,
XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS);
Status =
XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
Ppk0InBits, XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW,
XSK_ZYNQMP_EFUSEPS_PPK0_SHA3_HASH_END_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_PPK0_HASH);
goto END;
}
}
if (InstancePtr->PrgrmPpk1Hash == TRUE) {
/* Programming SHA3 hash(384 bit) into Efuse PPK1 */
XilSKey_Efuse_ConvertBitsToBytes(
InstancePtr->Ppk1Hash, Ppk1InBits,
XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS);
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(
Ppk1InBits, XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW,
XSK_ZYNQMP_EFUSEPS_PPK1_SHA3_HASH_END_ROW,
XSK_ZYNQMP_EFUSEPS_EFUSE_0);
if (Status != (u32)XST_SUCCESS) {
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_PPK1_HASH);
goto END;
}
}
/* Programming Secure and control bits */
Status = XilSKey_ZynqMp_EfusePs_Write_SecCtrl(InstancePtr);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Reload the cache */
Status = XilSKey_ZynqMp_EfusePs_CacheLoad();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Check the temperature and voltage(VCC_AUX and VCC_PINT_LP) */
Status = XilSKey_ZynqMp_EfusePs_Temp_Vol_Checks();
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status | (u32)XSK_EFUSEPS_ERROR_CMPLTD_EFUSE_PRGRM_WITH_ERR);
goto END;
}
END:
XilSKey_ZynqMp_EfusePS_PrgrmDisable();
UNLOCK:
/* Lock the controller back */
XilSKey_ZynqMp_EfusePs_CtrlrLock();
return Status;
}
/*****************************************************************************/
/**
* This function is used to read the PS eFUSE secure control bits from cache or
* eFUSE based on user input provided.
*
* @param ReadBackSecCtrlBits Pointer to the XilSKey_SecCtrlBits
* which holds the read secure control bits.
* @param ReadOption Indicates whether or not to read from the actual
* eFUSE array or from the eFUSE cache.
* - 0(XSK_EFUSEPS_READ_FROM_CACHE) Reads from eFUSE cache
* - 1(XSK_EFUSEPS_READ_FROM_EFUSE) Reads from eFUSE array
*
* @return
* - XST_SUCCESS if reads successfully
* - XST_FAILURE if reading is failed
*
* @note It is highly recommended to read from eFuse cache.
* Because reading from efuse may reduce the life of the efuse.
* And Cache reload is required for obtaining updated values for
* ReadOption 0.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits(
XilSKey_SecCtrlBits *ReadBackSecCtrlBits, u8 ReadOption)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(ReadBackSecCtrlBits != NULL);
Xil_AssertNonvoid((ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) ||
(ReadOption == XSK_EFUSEPS_READ_FROM_EFUSE));
if (ReadOption == 0U) {
XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits_Regs(
ReadBackSecCtrlBits);
Status = (u32)XST_SUCCESS;
}
else {
Status = (u32)XSK_EFUSEPS_RD_FROM_EFUSE_NOT_ALLOWED;
}
return Status;
}
/*****************************************************************************/
/**
* This function is used to read the PS eFUSE secure control bits from cache
* or from eFUSE array based on user selection.
*
* @param ReadBackSecCtrlBits is the pointer to the XilSKey_SecCtrlBits
* which holds the read secure control bits.
*
*
* @return
* - XST_SUCCESS if reads successfully
* - XST_FAILURE if reading is failed
*
* @note It is highly recommended to read from eFuse cache.
* Because reading from efuse may reduce the life of the efuse.
* And Cache reload is required for obtaining updated values for
* ReadOption 0.
*
******************************************************************************/
static INLINE void XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits_Regs(
XilSKey_SecCtrlBits *ReadBackSecCtrlBits)
{
u32 RegData = 0U;
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
u32 Silicon_Ver;
#endif
RegData = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_OFFSET);
ReadBackSecCtrlBits->UserWrLk0 =
(u8)(RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_MASK);
ReadBackSecCtrlBits->UserWrLk1 =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_MASK) >>
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_SHIFT);
ReadBackSecCtrlBits->UserWrLk2 =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_MASK) >>
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_SHIFT);
ReadBackSecCtrlBits->UserWrLk3 =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_MASK) >>
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_SHIFT);
ReadBackSecCtrlBits->UserWrLk4 =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_MASK) >>
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_SHIFT);
ReadBackSecCtrlBits->UserWrLk5 =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_MASK) >>
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_SHIFT);
ReadBackSecCtrlBits->UserWrLk6 =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_MASK) >>
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_SHIFT);
ReadBackSecCtrlBits->UserWrLk7 =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_MASK) >>
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_SHIFT);
ReadBackSecCtrlBits->LBistEn =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_LBIST_EN_MASK) >>
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_LBIST_EN_SHIFT);
ReadBackSecCtrlBits->LpdScEn =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_LPD_SC_EN_MASK) >>
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_LPD_SC_EN_SHIFT);
ReadBackSecCtrlBits->FpdScEn =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_FPD_SC_EN_MASK) >>
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_FPD_SC_EN_SHIFT);
RegData = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_OFFSET);
ReadBackSecCtrlBits->AesKeyRead =
(u8)(RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_MASK);
ReadBackSecCtrlBits->AesKeyWrite =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_SHIFT);
ReadBackSecCtrlBits->EncOnly =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_SHIFT);
ReadBackSecCtrlBits->BbramDisable =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_SHIFT);
ReadBackSecCtrlBits->ErrorDisable =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_SHIFT);
ReadBackSecCtrlBits->JtagDisable =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_SHIFT);
ReadBackSecCtrlBits->DFTDisable =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_SHIFT);
ReadBackSecCtrlBits->ProgGate =
(u8)((RegData & (u32)XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_MASK) >>
(u32)XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_SHIFT);
ReadBackSecCtrlBits->SecureLock =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_SHIFT);
/*
* RSA authentication enable is
* 11:25 bits from silicon version 3.0 and
* 24:25 bits for 1.0 and 2.0 silicon version
*/
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
Silicon_Ver = XGetPSVersion_Info();
if (Silicon_Ver > (u32)XPS_VERSION_2) {
ReadBackSecCtrlBits->RSAEnable =
(u16)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_SHIFT);
}
else {
ReadBackSecCtrlBits->RSAEnable =
(u16)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_MASK) >>
(u32)XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT14);
}
#endif
ReadBackSecCtrlBits->PPK0WrLock =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_SHIFT);
ReadBackSecCtrlBits->PPK0InVld =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_SHIFT);
ReadBackSecCtrlBits->PPK1WrLock =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_SHIFT);
ReadBackSecCtrlBits->PPK1InVld =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_MASK) >>
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_SHIFT);
/* Read PBR error */
RegData = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_OFFSET);
ReadBackSecCtrlBits->PbrBootErr = (u8)(RegData &
XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_MASK);
/* Read Reserved bits */
RegData = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_RESERVED_OFFSET);
ReadBackSecCtrlBits->Reserved1 = (u16)(RegData &
XSK_ZYNQMP_EFUSEPS_RESERVED1_MASK);
ReadBackSecCtrlBits->Reserved2 = (u16)(RegData &
XSK_ZYNQMP_EFUSEPS_RESERVED2_MASK) >>
XSK_ZYNQMP_EFUSEPS_RESERVED_SHIFT;
}
/*****************************************************************************/
/**
* This function performs pre checks for programming all the specified bits.
*
* @param InstancePtr is the pointer to the XilSKey_ZynqMpEPs.
*
* @return
* XST_SUCCESS - if all the conditions for programming is satisfied
* Errorcode - if any of the conditions are not met
*
* @note None.
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePsWrite_Checks(
XilSKey_ZynqMpEPs *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Read secure and control bits */
Status = XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits(
&(InstancePtr->ReadBackSecCtrlBits), XSK_EFUSEPS_READ_FROM_CACHE);
if(Status != (u32)XST_SUCCESS) {
goto END;
}
if (InstancePtr->PrgrmAesKey == TRUE) {
if (InstancePtr->ReadBackSecCtrlBits.AesKeyWrite ==
TRUE) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_AES_KEY);
goto END;
}
}
if (InstancePtr->PrgrmSpkID == TRUE) {
if (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PGM_LOCK_OFFSET) != 0x00U) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_SPK_ID);
goto END;
}
}
if (((InstancePtr->PrgrmUser0Fuse == TRUE) &&
(InstancePtr->ReadBackSecCtrlBits.UserWrLk0 == TRUE))) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_USER0_FUSE);
goto END;
}
if (((InstancePtr->PrgrmUser1Fuse == TRUE) &&
(InstancePtr->ReadBackSecCtrlBits.UserWrLk1 == TRUE))) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_USER1_FUSE);
goto END;
}
if (((InstancePtr->PrgrmUser2Fuse == TRUE) &&
(InstancePtr->ReadBackSecCtrlBits.UserWrLk2 == TRUE))) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_USER2_FUSE);
goto END;
}
if (((InstancePtr->PrgrmUser3Fuse == TRUE) &&
(InstancePtr->ReadBackSecCtrlBits.UserWrLk3 == TRUE))) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_USER3_FUSE);
goto END;
}
if (((InstancePtr->PrgrmUser4Fuse == TRUE) &&
(InstancePtr->ReadBackSecCtrlBits.UserWrLk4 == TRUE))) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_USER4_FUSE);
goto END;
}
if (((InstancePtr->PrgrmUser5Fuse == TRUE) &&
(InstancePtr->ReadBackSecCtrlBits.UserWrLk5 == TRUE))) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_USER5_FUSE);
goto END;
}
if (((InstancePtr->PrgrmUser6Fuse == TRUE) &&
(InstancePtr->ReadBackSecCtrlBits.UserWrLk6 == TRUE))) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_USER6_FUSE);
goto END;
}
if (((InstancePtr->PrgrmUser7Fuse == TRUE) &&
(InstancePtr->ReadBackSecCtrlBits.UserWrLk7 == TRUE))) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_USER7_FUSE);
goto END;
}
if (InstancePtr->PrgrmPpk0Hash == TRUE) {
if (InstancePtr->ReadBackSecCtrlBits.PPK0WrLock ==
TRUE) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_PPK0_HASH);
goto END;
}
}
if (InstancePtr->PrgrmPpk1Hash == TRUE) {
if (InstancePtr->ReadBackSecCtrlBits.PPK1WrLock ==
TRUE) {
Status = ((u32)XSK_EFUSEPS_ERROR_FUSE_PROTECTED |
(u32)XSK_EFUSEPS_ERROR_WRITE_PPK1_HASH);
goto END;
}
}
END:
return Status;
}
/*****************************************************************************/
/* This function programs and verifys the Row range provided with provided data.
*
* @param Data is a pointer to an array which contains data to be
* programmed.
* @param RowStart holds the row number from which data programming has to
* be started.
* @param RowEnd holds the row number till which data programming has to
* be performed.
* @param EfuseType holds the type of the efuse in which programming rows
* resides in.
*
* @return
* XST_SUCCESS - On success
* XST_FAILURE - on Failure
*
* @note None.
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(u8 *Data,
u8 RowStart, u8 RowEnd, XskEfusePs_Type EfuseType)
{
u8 Row;
u8 Column;
u32 Status = (u32)XST_FAILURE;
u32 Bit;
u8 Bit_u8;
if (RowStart > RowEnd) {
goto END;
}
for (Row = RowStart; Row <= RowEnd; Row++) {
for (Column = 0U; Column < 32U; Column++) {
Bit_u8 = (Row - RowStart);
Bit = (u32)Bit_u8 * (u32)XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW;
Bit = Bit + (u32)Column;
if (Data[Bit] != 0U) {
Status =
XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
Column, EfuseType);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
}
}
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/* This function programs and verifies the particular bit of eFUSE array
*
* @param Row specifies the row number.
* @param Column specifies the column number.
* @param EfuseType specifies the eFUSE type.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note None.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(u8 Row, u8 Column,
XskEfusePs_Type EfuseType)
{
u32 RowDataVal = 0U;
u32 Status = (u32)XST_FAILURE;
u8 MarginRead;
u32 ReadReg;
/* Programming bit */
Status = XilSKey_ZynqMp_EfusePs_WriteBit(Row, Column, EfuseType);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/*
* If Row Belongs to AES key can't verify the bit
* as AES key can be checked only CRC
*/
if ((Row >= XSK_ZYNQMP_EFUSEPS_AES_KEY_START_ROW) &&
(Row <= XSK_ZYNQMP_EFUSEPS_AES_KEY_END_ROW)) {
Status = (u32)XST_SUCCESS;
goto END;
}
/* verifying the programmed bit */
for (MarginRead = XSK_ZYNQMP_EFUSEPS_CFG_NORMAL_RD;
MarginRead <= XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_2_RD;
MarginRead++) {
ReadReg = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_CFG_OFFSET) &
(~XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_MASK);
ReadReg = ReadReg |
(u32)((u32)MarginRead << (u32)XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_SHIFT);
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \
XSK_ZYNQMP_EFUSEPS_CFG_OFFSET, ReadReg);
Status = XilSKey_ZynqMp_EfusePs_ReadRow(Row, EfuseType, &RowDataVal);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
if (((RowDataVal >> Column) & 0x01U) == 0x00U) {
Status = (u32)XSK_EFUSEPS_ERROR_VERIFICATION;
goto END;
}
}
END:
return Status;
}
/*****************************************************************************/
/*
* This function returns particular row data directly from eFUSE array.
*
* @param Row specifies the row number to read.
* @param EfuseType specifies the eFUSE type.
* @param RowData is a pointer to 32 bit variable to hold the data read
* from provided data
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note None.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_ReadRow(u8 Row, XskEfusePs_Type EfuseType,
u32 *RowData)
{
u32 WriteValue;
u32 Events = 0U;
u32 EventsMask;
u32 EfusePsType;
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(RowData != NULL);
Xil_AssertNonvoid((EfuseType == XSK_ZYNQMP_EFUSEPS_EFUSE_0) ||
(EfuseType == XSK_ZYNQMP_EFUSEPS_EFUSE_2) || (EfuseType ==
XSK_ZYNQMP_EFUSEPS_EFUSE_3));
Xil_AssertNonvoid(Row <= XSK_ZYNQMP_EFUSEPS_PPK1_SHA3_HASH_END_ROW);
EfusePsType = (u32)EfuseType;
WriteValue = ((EfusePsType << (u32)XSK_ZYNQMP_EFUSEPS_RD_ADDR_SHIFT) &
(u32)XSK_ZYNQMP_EFUSEPS_RD_ADDR_MASK) |
(((u32)Row << (u32)XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_SHIFT) &
(u32)XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_MASK);
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_RD_ADDR_OFFSET, WriteValue);
EventsMask = XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_MASK |
XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_MASK;
Status = Xil_WaitForEvents((XSK_ZYNQMP_EFUSEPS_BASEADDR +
(u32)XSK_ZYNQMP_EFUSEPS_ISR_OFFSET),
EventsMask, EventsMask, (u32)XSK_POLL_TIMEOUT, &Events);
if ((Events & XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_MASK) != 0U) {
Status = (u32)XSK_EFUSEPS_ERROR_READ;
}
else if ((Events & XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_MASK) == 0U) {
Status = (u32)XSK_EFUSEPS_ERROR_READ_NOT_DONE;
}
else {
*RowData =
XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_RD_DATA_OFFSET);
Status = (u32)XST_SUCCESS;
}
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_ISR_OFFSET,
XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_ISR_OFFSET));
return Status;
}
/*****************************************************************************/
/*
* This function programs a particular bit.
*
* @param Row specifies the row number to program.
* @param Column specifies the column number to program.
* @param EfuseType specifies the eFUSE type.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note None.
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_WriteBit(u8 Row, u8 Column,
XskEfusePs_Type EfuseType)
{
u32 WriteValue;
u32 Events = 0U;
u32 EventsMask;
u32 EfusePsType = (u32)EfuseType;
u32 Status = (u32)XST_FAILURE;
WriteValue = ((EfusePsType << (u32)XSK_ZYNQMP_EFUSEPS_PGM_ADDR_SHIFT) &
(u32)XSK_ZYNQMP_EFUSEPS_PGM_ADDR_MASK) |
(((u32)Row << (u32)XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_SHIFT) &
(u32)XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_MASK) |
((u32)Column & (u32)XSK_ZYNQMP_EFUSEPS_PGM_ADDR_COL_MASK);
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PGM_ADDR_OFFSET, WriteValue);
EventsMask = XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_MASK |
XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_MASK;
Status = Xil_WaitForEvents((XSK_ZYNQMP_EFUSEPS_BASEADDR +
(u32)XSK_ZYNQMP_EFUSEPS_ISR_OFFSET),
EventsMask, EventsMask, (u32)XSK_POLL_TIMEOUT, &Events);
if ((Events & XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_MASK) != 0U) {
Status = (u32)XSK_EFUSEPS_ERROR_PROGRAMMING;
}
else if ((Events & XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_MASK) == 0U) {
Status = (u32)XSK_EFUSEPS_ERROR_PGM_NOT_DONE;
}
else {
Status = (u32)XST_SUCCESS;
}
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_ISR_OFFSET,
XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_ISR_OFFSET));
return Status;
}
/*****************************************************************************/
/*
* This function reloads the cache of eFUSE so that can be directly read from
* cache.
*
* @param None.
*
* @return
* - XST_SUCCESS on successful cache reload
* - ErrorCode on failure
*
* @note Not recommended to call this API
* frequently, if this API is called all the cache memory is reloded
* by reading eFUSE array, reading eFUSE bit multiple times may
* diminish the life time.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_CacheLoad(void)
{
volatile u32 CacheStatus;
u32 Status = (u32)XST_FAILURE;
/* Check the unlock status */
if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus() != 0U) {
XilSKey_ZynqMp_EfusePs_CtrlrUnLock();
}
/* Reload cache */
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_OFFSET,
XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_MASK);
CacheStatus = XilSKey_ZynqMp_EfusePs_Status() &
(XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_MASK |
XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_MASK);
/* Waiting for cache loading completion */
while(CacheStatus == XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_MASK) {
CacheStatus = XilSKey_ZynqMp_EfusePs_Status() &
(XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_MASK);
if ((CacheStatus) == (u32)XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_MASK) {
break;
}
}
CacheStatus = XilSKey_ZynqMp_EfusePs_Status();
if ((CacheStatus & XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_MASK) == 0x00U) {
Status = (u32)XSK_EFUSEPS_ERROR_CACHE_LOAD;
goto END;
}
CacheStatus = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_ISR_OFFSET);
if ((CacheStatus & XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_MASK) ==
XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_MASK) {
Status = (u32)XSK_EFUSEPS_ERROR_CACHE_LOAD;
goto END;
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/*
* This function sets all the required parameters to program eFUSE array.
*
* @param None.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note None.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_SetWriteConditions(void)
{
u32 ReadReg;
u32 Status = (u32)XST_FAILURE;
/* Enable Program enable bit */
XilSKey_ZynqMp_EfusePS_PrgrmEn();
/* Setting the timing Constraints */
XilSKey_ZynqMp_EfusePs_SetTimerValues();
/* Read status and verify Tbits are read properly or not */
ReadReg = XilSKey_ZynqMp_EfusePs_Status();
if ((ReadReg & (XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_MASK |
XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_MASK |
XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_MASK)) !=
(XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_MASK |
XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_MASK |
XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_MASK)) {
/* T bits pattern is incorrect */
Status = (u32)XSK_EFUSEPS_ERROR_IN_TBIT_PATTERN;
}
else {
Status = (u32)XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/*
* This function sets timers for programming and reading from eFUSE.
*
* @param None
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XilSKey_ZynqMp_EfusePs_SetTimerValues(void)
{
u32 ReadReg;
ReadReg = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_CFG_OFFSET) &
~(XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_MASK);
ReadReg = ReadReg |
((XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_2_RD <<
XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_SHIFT) |
(XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_MASK));
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_CFG_OFFSET, ReadReg);
/* Initialized Timer */
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_TPGM_OFFSET,
((u32)XilSKey_ZynqMp_EfusePs_Tprgrm() &
XSK_ZYNQMP_EFUSEPS_TPGM_VAL_MASK));
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_TRD_OFFSET,
((u32)XilSKey_ZynqMp_EfusePs_Trd() &
XSK_ZYNQMP_EFUSEPS_TRD_VAL_MASK));
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_TSU_H_PS_OFFSET,
((u32)XilSKey_ZynqMp_EfusePs_TsuHPs() &
XSK_ZYNQMP_EFUSEPS_TSU_H_PS_VAL_MASK));
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_OFFSET,
((u32)XilSKey_ZynqMp_EfusePs_TsuHPsCs() &
XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_MASK));
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_TSU_H_CS_OFFSET,
((u32)XilSKey_ZynqMp_EfusePs_TsuHCs() &
XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_DEFVAL));
#endif
}
/*****************************************************************************/
/*
* This function programs secure control bits specified by user.
*
* @param InstancePtr is an instance of efuseps of Zynq MP.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note None.
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrl(
XilSKey_ZynqMpEPs *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Programming Secure and control bits of eFuse */
Status = XilSKey_ZynqMp_EfusePs_Write_SecCtrlBits(InstancePtr);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Programming User control bits */
Status = XilSKey_ZynqMp_EfusePs_Write_UsrCtrlBits(InstancePtr);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
END:
return Status;
}
/*****************************************************************************/
/*
* This function programs secure control bits of eFUSE
*
* @param InstancePtr is an instance of efuseps of ZynqMp.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note None.
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrlBits(
XilSKey_ZynqMpEPs *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0;
u32 Row;
u32 RowDataVal = 0U;
u8 DataInBits[XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW] = {0};
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Row = XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW;
if ((InstancePtr->PrgrmgSecCtrlBits.AesKeyRead != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.AesKeyWrite != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.EncOnly != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.BbramDisable != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.ErrorDisable != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.JtagDisable != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.DFTDisable != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.ProgGate != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.SecureLock != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.RSAEnable != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.PPK0WrLock != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.PPK0InVld != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.PPK1WrLock != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.PPK1InVld != 0x00U)) {
RowDataVal = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&RowDataVal, DataInBits,
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
}
if ((InstancePtr->PrgrmgSecCtrlBits.AesKeyRead != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_AES_RDLK] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
XSK_ZYNQMP_EFUSEPS_SEC_AES_RDLK, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_AES_CRC_LK_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.AesKeyWrite != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_AES_WRLK] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_AES_WRLK, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_AES_WR_LK_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.EncOnly != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_ENC_ONLY] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_ENC_ONLY, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_USE_AESONLY_EN_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.BbramDisable != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_BRAM_DIS] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_BRAM_DIS, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_BBRAM_DIS_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.ErrorDisable != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_ERR_DIS] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_ERR_DIS, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_PMU_ERR_DIS_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.JtagDisable != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_JTAG_DIS] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_JTAG_DIS, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_JTAG_DIS_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.DFTDisable != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_DFT_DIS] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_DFT_DIS, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_DFT_MODE_DIS_BIT);
goto END;
}
}
if (InstancePtr->PrgrmgSecCtrlBits.ProgGate != 0x00U) {
if (DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE0] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE0, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_PROG_GATE0_DIS_BIT);
goto END;
}
}
if (DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE1] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE1, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_PROG_GATE1_DIS_BIT);
goto END;
}
}
if (DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE2] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE2, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_PROG_GATE2_DIS_BIT);
goto END;
}
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.SecureLock != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_LOCK] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_LOCK, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_SEC_LOCK_BIT);
goto END;
}
}
if (InstancePtr->PrgrmgSecCtrlBits.RSAEnable != 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_Enable_Rsa(DataInBits);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status | (u32)XSK_EFUSEPS_ERROR_WRITE_RSA_AUTH_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.PPK0WrLock != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK0_WRLK] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_PPK0_WRLK, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_PPK0_WR_LK_BIT);
goto END;
}
}
if (InstancePtr->PrgrmgSecCtrlBits.PPK0InVld != 0x00U) {
if (DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT1]
== 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT1,
EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_PPK0_RVK_BIT);
goto END;
}
}
if (DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT2]
== 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT2,
EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_PPK0_RVK_BIT);
goto END;
}
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.PPK1WrLock != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK1_WRLK] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_PPK1_WRLK, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_PPK1_WR_LK_BIT);
goto END;
}
}
if (InstancePtr->PrgrmgSecCtrlBits.PPK1InVld != 0x00U) {
if (DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT1]
== 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT1,
EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_PPK1_RVK_BIT);
goto END;
}
}
if (DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT2]
== 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT2,
EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRTIE_PPK1_RVK_BIT);
goto END;
}
}
}
/* Programming PBR BOOT Error */
if (InstancePtr->PrgrmgSecCtrlBits.PbrBootErr == TRUE) {
Row = XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW;
RowDataVal = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&RowDataVal, DataInBits,
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
if (DataInBits[XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_0] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_0,
EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_PBR_BOOT_ERR_BIT);
goto END;
}
}
if (DataInBits[XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_1] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_1,
EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_PBR_BOOT_ERR_BIT);
goto END;
}
}
if (DataInBits[XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_2] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_2,
EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)(Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_PBR_BOOT_ERR_BIT);
goto END;
}
}
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/*
* This function programs misc user control bits of eFUSE
*
* @param InstancePtr is an instance of efuseps of ZynqMp.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note None.
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_Write_UsrCtrlBits(
XilSKey_ZynqMpEPs *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0;
u8 Row = XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW;
u8 DataInBits[XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW] = {0};
u32 RowDataVal = 0U;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk0 != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.UserWrLk1 != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.UserWrLk2 != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.UserWrLk3 != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.UserWrLk4 != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.UserWrLk5 != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.UserWrLk6 != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.UserWrLk7 != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.LBistEn != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.FpdScEn != 0x00U) ||
(InstancePtr->PrgrmgSecCtrlBits.LpdScEn != 0x00U)) {
RowDataVal = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&RowDataVal, DataInBits,
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
}
else {
Status = (u32)XST_SUCCESS;
goto END;
}
if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk0 != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_0] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_0, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRTIE_USER0_LK_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk1 != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_1] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_1, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRTIE_USER1_LK_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk2 != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_2] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_2, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRTIE_USER2_LK_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk3 != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_3] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_3, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRTIE_USER3_LK_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk4 != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_4] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_4, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRTIE_USER4_LK_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk5 != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_5] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_5, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRTIE_USER5_LK_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk6 != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_6] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_6, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRTIE_USER6_LK_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk7 != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_7] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_USR_WRLK_7, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRTIE_USER7_LK_BIT);
goto END;
}
}
if ((InstancePtr->PrgrmgSecCtrlBits.LBistEn != 0x00U) &&
(DataInBits[XSK_ZYNQMP_EFUSEPS_LBIST_EN] == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_LBIST_EN, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status | (u32)XSK_EFUSEPS_ERROR_WRITE_LBIST_EN_BIT);
goto END;
}
}
if (InstancePtr->PrgrmgSecCtrlBits.LpdScEn != 0x00U) {
if (DataInBits[XSK_ZYNQMP_EFUSEPS_LPD_SC_EN_0] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_LPD_SC_EN_0, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_LPD_SC_EN_BIT);
goto END;
}
}
if (DataInBits[XSK_ZYNQMP_EFUSEPS_LPD_SC_EN_1] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_LPD_SC_EN_1, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_LPD_SC_EN_BIT);
goto END;
}
}
if (DataInBits[XSK_ZYNQMP_EFUSEPS_LPD_SC_EN_2] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_LPD_SC_EN_2, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_LPD_SC_EN_BIT);
goto END;
}
}
}
if (InstancePtr->PrgrmgSecCtrlBits.FpdScEn != 0x00U) {
if (DataInBits[XSK_ZYNQMP_EFUSEPS_FPD_SC_EN_0] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_FPD_SC_EN_0, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_FPD_SC_EN_BIT);
goto END;
}
}
if (DataInBits[XSK_ZYNQMP_EFUSEPS_FPD_SC_EN_1] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_FPD_SC_EN_1, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_FPD_SC_EN_BIT);
goto END;
}
}
if (DataInBits[XSK_ZYNQMP_EFUSEPS_FPD_SC_EN_2] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_FPD_SC_EN_2, EfuseType);
if (Status != (u32)XST_SUCCESS) {
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_FPD_SC_EN_BIT);
goto END;
}
}
}
END:
return Status;
}
/*****************************************************************************/
/**
* This function performs the CRC check of AES key
*
* @param CrcValue A 32 bit CRC value of an expected AES key.
*
* @return
* - XST_SUCCESS on successful CRC check.
* - ErrorCode on failure
*
* @note For Calculating the CRC of the AES key use the
* XilSKey_CrcCalculation() function or
* XilSkey_CrcCalculation_AesKey() function
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_CheckAesKeyCrc(u32 CrcValue)
{
u32 Status = (u32)XST_FAILURE;
u32 ReadReg = 0U;
u32 TimeOut = 0U;
/* Check the unlock status */
if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus() != 0U) {
/* Unlock the controller */
XilSKey_ZynqMp_EfusePs_CtrlrUnLock();
}
/* Set the timing constraints */
XilSKey_ZynqMp_EfusePs_SetTimerValues();
/* writing CRC value to check AES key's CRC */
XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_AES_CRC_OFFSET,
(CrcValue & XSK_ZYNQMP_EFUSEPS_AES_CRC_VAL_MASK));
while (TimeOut < XSK_POLL_TIMEOUT) {
/* Poll for CRC Done bit */
ReadReg = XilSKey_ZynqMp_EfusePs_Status();
if ((ReadReg & XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_MASK) !=
0x00U) {
break;
}
TimeOut = TimeOut + 1U;
}
if ((ReadReg & XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_MASK) ==
0x00U) {
Status = (u32)XST_FAILURE;
goto END;
}
if ((ReadReg & XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_PASS_MASK) == 0x00U) {
Status = (u32)XST_FAILURE;
}
END:
return Status;
}
/*****************************************************************************/
/**
* This function is used to read a user fuse from the eFUSE or cache
*
* @param UseFusePtr Pointer to an array which holds the readback
* user fuse.
* @param UserFuse_Num A variable which holds the user fuse number.
* Range is (User fuses: 0 to 7)
* @param ReadOption Indicates whether or not to read from the actual
* eFUSE array or from the eFUSE cache.
* - 0(XSK_EFUSEPS_READ_FROM_CACHE) Reads from eFUSE cache
* - 1(XSK_EFUSEPS_READ_FROM_EFUSE) Reads from eFUSE array
* @return
* - XST_SUCCESS on successful read
* - ErrorCode on failure
* @note It is highly recommended to read from eFuse cache.
* Because reading from efuse may reduce the life of the efuse.
* And Cache reload is required for obtaining updated values for
* ReadOption 0.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_ReadUserFuse(u32 *UseFusePtr, u8 UserFuse_Num,
u8 ReadOption)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(UseFusePtr != NULL);
Xil_AssertNonvoid(UserFuse_Num <= (XSK_ZYNQMP_EFUSEPS_USR_FUSE_REG_NUM
- 1U));
Xil_AssertNonvoid((ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) ||
(ReadOption == XSK_EFUSEPS_READ_FROM_EFUSE));
if (ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) {
*UseFusePtr = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
(XSK_ZYNQMP_EFUSEPS_USER_0_OFFSET
+ ((u32)UserFuse_Num * 4U)));
Status = (u32)XST_SUCCESS;
}
else {
Status = (u32)XSK_EFUSEPS_RD_FROM_EFUSE_NOT_ALLOWED;
}
return Status;
}
/*****************************************************************************/
/**
* This function is used to read the PPK0 hash from an eFUSE or eFUSE cache.
*
* @param Ppk0Hash A pointer to an array which holds the readback
* PPK0 hash.
* @param ReadOption Indicates whether or not to read from the actual
* eFUSE array or from the eFUSE cache.
* - 0(XSK_EFUSEPS_READ_FROM_CACHE) Reads from eFUSE cache
* - 1(XSK_EFUSEPS_READ_FROM_EFUSE) Reads from eFUSE array
*
* @return
* - XST_SUCCESS on successful read
* - ErrorCode on failure
* @note It is highly recommended to read from eFuse cache.
* Because reading from efuse may reduce the life of the efuse.
* And Cache reload is required for obtaining updated values for
* ReadOption 0.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_ReadPpk0Hash(u32 *Ppk0Hash, u8 ReadOption)
{
u32 Status = (u32)XST_FAILURE;
s32 RegNum;
u32 DataRead;
s32 Reg = (s32)(XSK_ZYNQMP_EFUSEPS_PPK_HASH_REG_NUM - 1U);
u32 * Ppk0hashPtr = Ppk0Hash;
/* Assert validates the input arguments */
Xil_AssertNonvoid(Ppk0hashPtr != NULL);
Xil_AssertNonvoid((ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) ||
(ReadOption == XSK_EFUSEPS_READ_FROM_EFUSE));
if (ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) {
for (RegNum = Reg; RegNum >= (s32)0; RegNum--) {
DataRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PPK0_0_OFFSET
+ ((u32)RegNum * 4U));
XilSKey_EfusePs_ConvertBytesBeToLe((u8 *)&DataRead, (u8 *)Ppk0hashPtr, 1U);
Ppk0hashPtr++;
}
Status = (u32)XST_SUCCESS;
}
else {
Status = (u32)XSK_EFUSEPS_RD_FROM_EFUSE_NOT_ALLOWED;
}
return Status;
}
/*****************************************************************************/
/**
* This function is used to read the PPK1 hash from eFUSE or cache.
*
* @param Ppk1Hash Pointer to an array which holds the readback
* PPK1 hash.
* @param ReadOption Indicates whether or not to read from the actual
* eFUSE array or from the eFUSE cache.
* - 0(XSK_EFUSEPS_READ_FROM_CACHE) Reads from eFUSE cache
* - 1(XSK_EFUSEPS_READ_FROM_EFUSE) Reads from eFUSE array
*
* @return
* - XST_SUCCESS on successful read
* - ErrorCode on failure
*
* @note It is highly recommended to read from eFuse cache.
* Because reading from efuse may reduce the life of the efuse.
* And Cache reload is required for obtaining updated values for
* ReadOption 0.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_ReadPpk1Hash(u32 *Ppk1Hash, u8 ReadOption)
{
u32 Status = (u32)XST_FAILURE;
s32 RegNum;
u32 DataRead;
s32 Reg = (s32)(XSK_ZYNQMP_EFUSEPS_PPK_HASH_REG_NUM - 1U);
u32 * Ppk1hashPtr = Ppk1Hash;
/* Assert validates the input arguments */
Xil_AssertNonvoid(Ppk1hashPtr != NULL);
Xil_AssertNonvoid((ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) ||
(ReadOption == XSK_EFUSEPS_READ_FROM_EFUSE));
if (ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) {
for (RegNum = Reg; RegNum >= (s32)0; RegNum--) {
DataRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PPK1_0_OFFSET
+ ((u32)RegNum * 4U));
XilSKey_EfusePs_ConvertBytesBeToLe((u8 *)&DataRead, (u8 *)Ppk1hashPtr, 1U);
Ppk1hashPtr++;
}
Status = (u32)XST_SUCCESS;
}
else {
Status = (u32)XSK_EFUSEPS_RD_FROM_EFUSE_NOT_ALLOWED;
}
return Status;
}
/*****************************************************************************/
/**
* This function is used to read SPKID from eFUSE or cache based on user's
* read option.
*
* @param SpkId Pointer to a 32 bit variable which holds SPK ID.
* @param ReadOption Indicates whether or not to read from the actual
* eFUSE array or from the eFUSE cache.
* - 0(XSK_EFUSEPS_READ_FROM_CACHE) Reads from eFUSE cache
* - 1(XSK_EFUSEPS_READ_FROM_EFUSE) Reads from eFUSE array
*
* @return
* - XST_SUCCESS on successful read
* - ErrorCode on failure
* @note It is highly recommended to read from eFuse cache.
* Because reading from efuse may reduce the life of the efuse.
* And Cache reload is required for obtaining updated values for
* ReadOption 0.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_ReadSpkId(u32 *SpkId, u8 ReadOption)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(SpkId != NULL);
Xil_AssertNonvoid((ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) ||
(ReadOption == XSK_EFUSEPS_READ_FROM_EFUSE));
if (ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) {
*SpkId = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_SPK_ID_OFFSET);
Status = (u32)XST_SUCCESS;
}
else {
Status = (u32)XSK_EFUSEPS_RD_FROM_EFUSE_NOT_ALLOWED;
}
return Status;
}
/*****************************************************************************/
/**
* This function is used to read DNA from eFUSE.
*
* @param DnaRead Pointer to an array of 3 x u32 words which holds the
* readback DNA.
*
* @return None.
*
******************************************************************************/
void XilSKey_ZynqMp_EfusePs_ReadDna(u32 *DnaRead)
{
u32 *DnaPtr;
/* Assert validates the input arguments */
Xil_AssertVoid(DnaRead != NULL);
DnaPtr = DnaRead;
*DnaPtr = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_DNA_0_OFFSET);
DnaPtr++;
*DnaPtr = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_DNA_1_OFFSET);
DnaPtr++;
*DnaPtr = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_DNA_2_OFFSET);
}
/*****************************************************************************/
/*
* This function is used verify eFUSE keys for Zeros
*
* @param RowStart is row number from which verification has to be
* started.
* @param RowEnd is row number till which verification has to be
* ended.
* @param EfuseType is the type of the eFUSE in which these rows reside.
*
* @return XST_SUCCESS if keys are not programmed.
* Errorcode on failure.
*
* @note None.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_CheckForZeros(u8 RowStart, u8 RowEnd,
XskEfusePs_Type EfuseType)
{
u32 Status = (u32)XST_FAILURE;
u8 Row;
u32 RowDataVal = 0U;
for (Row = RowStart; Row <= RowEnd; Row++) {
Status = XilSKey_ZynqMp_EfusePs_ReadRow(Row, EfuseType,
&RowDataVal);
if (Status != (u32)XST_SUCCESS) {
break;
}
if (RowDataVal != 0x00U) {
Status = (u32)XST_FAILURE;
break;
}
}
return Status;
}
/*****************************************************************************/
/*
* This function is used verify eFUSE keys for Zeros before programming.
*
* @param InstancePtr is a pointer to eFUSE ps instance.
*
* @return
* - XST_SUCCESS if keys are not programmed
* - ErrorCode if keys are already programmed.
*
* @note None.
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_CheckZeros_BfrPrgrmg(
XilSKey_ZynqMpEPs *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
u32 PpkHashVal[XSK_ZYNQMP_EFUSEPS_PPK_HASH_REG_NUM] = {0U};
u32 Offset;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Check for AES key with All zeros */
if (InstancePtr->PrgrmAesKey == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_CheckAesKeyCrc(
XSK_ZYNQMP_EFUSEPS_CRC_AES_ZEROS);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)XSK_EFUSEPS_ERROR_AES_ALREADY_PROGRAMMED;
goto END;
}
}
/* Check Zeros for PPK0 hash */
if (InstancePtr->PrgrmPpk0Hash == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_ReadPpk0Hash(PpkHashVal,
XSK_EFUSEPS_READ_FROM_CACHE);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
for (Offset = 0U; Offset < XSK_ZYNQMP_EFUSEPS_PPK_HASH_REG_NUM;
Offset++) {
if (PpkHashVal[Offset] != 0X00U) {
Status = (u32)XSK_EFUSEPS_ERROR_PPK0_HASH_ALREADY_PROGRAMMED;
goto END;
}
}
}
/* Check Zeros for PPK1 hash */
if (InstancePtr->PrgrmPpk1Hash == TRUE) {
Status = XilSKey_ZynqMp_EfusePs_ReadPpk1Hash(PpkHashVal,
XSK_EFUSEPS_READ_FROM_CACHE);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
for (Offset = 0U; Offset < XSK_ZYNQMP_EFUSEPS_PPK_HASH_REG_NUM;
Offset++) {
if (PpkHashVal[Offset] != 0X00U) {
Status = (u32)XSK_EFUSEPS_ERROR_PPK1_HASH_ALREADY_PROGRAMMED;
goto END;
}
}
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/*
* This function throws an error if user requests already programmed User FUSE
* bit to revert, and copies the bits to be programmed in particular row into
* provided UserFuses_TobePrgrmd pointer.
*
* @param UserFuses_Write is a pointer to user requested programming bits
* of an User FUSE row.
* @param UserFuses_Read is a pointer to already programmed bits of User
* FUSE row on eFUSE.
* @param UserFuses_TobePrgrmd holds User FUSE row bits which needs to be
* programmed actually.
*
* @return
* - XST_FAILURE: Returns error if user requests programmed bit to
* revert
* - XST_SUCCESS: If User requests valid bits.
*
* @note If user requests a non-zero bit for making to zero throws an
* error which is not possible
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_UserFuses_TobeProgrammed(
u8 *UserFuses_Write, u8 *UserFuses_Read,
XilSKey_UsrFuses *UserFuses_ToBePrgrmd)
{
u32 UserFuseColumn;
u32 Status;
for (UserFuseColumn = 0U; UserFuseColumn < 32U; UserFuseColumn++) {
/* If user requests a non-zero bit for making to zero throws an error*/
if ((UserFuses_Write[UserFuseColumn] == 0U) &&
(UserFuses_Read[UserFuseColumn] == 1U)) {
Status = (u32)XST_FAILURE;
goto END;
}
if ((UserFuses_Write[UserFuseColumn] == 1U) &&
(UserFuses_Read[UserFuseColumn] == 0U)) {
UserFuses_ToBePrgrmd->UserFuse[UserFuseColumn] = 1U;
}
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/*
* This function throws an error if user requests already programmed User FUSE
* bit to revert, and copies the User FUSE bits which needs actually to be
* programmed into provided UserFuses_TobePrgrmd pointer.
*
* @param InstancePtr is a pointer to eFUSE ps instance.
* @param UserFuses_TobePrgrmd holds User FUSE bits which needs to be
* actually programmed.
*
* @return
* - ErrorCode if user requests programmed bit to revert.
* - XST_SUCCESS if user requests valid bits
*
* @note If user requests a non-zero bit for making to zero throws an
* error which is not possible
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_UserFuses_WriteChecks(
XilSKey_ZynqMpEPs *InstancePtr, XilSKey_UsrFuses *ToBePrgrmd)
{
u8 UserFuses_Read[8][32] = {{0},{0},{0},{0},{0},{0},{0},{0}};
u8 UserFuses_Write[8][32] = {{0},{0},{0},{0},{0},{0},{0},{0}};
u32 UserFuseRead;
XilSKey_UsrFuses *UserEFuseToPrg;
u32 Status = (u32)XST_FAILURE;
if (InstancePtr->PrgrmUser0Fuse == TRUE) {
UserFuseRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_USER_0_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&UserFuseRead,
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR0_FUSE][0],
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->User0Fuses,
&(UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR0_FUSE][0]),
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
UserEFuseToPrg = (ToBePrgrmd + (u32)XSK_ZYNQMP_EFUSEPS_USR0_FUSE);
/* Checking whether requested User FUSE bit programming is possible */
if (XilSKey_ZynqMp_EfusePs_UserFuses_TobeProgrammed(
&UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR0_FUSE][0],
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR0_FUSE][0],
UserEFuseToPrg) != (u32)XST_SUCCESS) {
Status = ((u32)XSK_EFUSEPS_ERROR_WRITE_USER0_FUSE |
(u32)XSK_EFUSEPS_ERROR_USER_BIT_CANT_REVERT);
goto END;
}
}
if (InstancePtr->PrgrmUser1Fuse == TRUE) {
UserFuseRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_USER_1_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&UserFuseRead,
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR1_FUSE][0],
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->User1Fuses,
&(UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR1_FUSE][0]),
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
UserEFuseToPrg = (ToBePrgrmd + (u32)XSK_ZYNQMP_EFUSEPS_USR1_FUSE);
/* Checking whether requested User FUSE bit programming is possible */
if (XilSKey_ZynqMp_EfusePs_UserFuses_TobeProgrammed(
&UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR1_FUSE][0],
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR1_FUSE][0],
UserEFuseToPrg) != (u32)XST_SUCCESS) {
Status = ((u32)XSK_EFUSEPS_ERROR_WRITE_USER1_FUSE |
(u32)XSK_EFUSEPS_ERROR_USER_BIT_CANT_REVERT);
goto END;
}
}
if (InstancePtr->PrgrmUser2Fuse == TRUE) {
UserFuseRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_USER_2_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&UserFuseRead,
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR2_FUSE][0],
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->User2Fuses,
&(UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR2_FUSE][0]),
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
UserEFuseToPrg = (ToBePrgrmd + (u32)XSK_ZYNQMP_EFUSEPS_USR2_FUSE);
/* Checking whether requested User FUSE bit programming is possible */
if (XilSKey_ZynqMp_EfusePs_UserFuses_TobeProgrammed(
&UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR2_FUSE][0],
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR2_FUSE][0],
UserEFuseToPrg) != (u32)XST_SUCCESS) {
Status = ((u32)XSK_EFUSEPS_ERROR_WRITE_USER2_FUSE |
(u32)XSK_EFUSEPS_ERROR_USER_BIT_CANT_REVERT);
goto END;
}
}
if (InstancePtr->PrgrmUser3Fuse == TRUE) {
UserFuseRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_USER_3_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&UserFuseRead,
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR3_FUSE][0],
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->User3Fuses,
&(UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR3_FUSE][0]),
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
UserEFuseToPrg = (ToBePrgrmd + (u32)XSK_ZYNQMP_EFUSEPS_USR3_FUSE);
/* Checking whether requested User FUSE bit programming is possible */
if (XilSKey_ZynqMp_EfusePs_UserFuses_TobeProgrammed(
&UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR3_FUSE][0],
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR3_FUSE][0],
UserEFuseToPrg) != (u32)XST_SUCCESS) {
Status = ((u32)XSK_EFUSEPS_ERROR_WRITE_USER3_FUSE |
(u32)XSK_EFUSEPS_ERROR_USER_BIT_CANT_REVERT);
goto END;
}
}
if (InstancePtr->PrgrmUser4Fuse == TRUE) {
UserFuseRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_USER_4_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&UserFuseRead,
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR4_FUSE][0],
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->User4Fuses,
&(UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR4_FUSE][0]),
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
UserEFuseToPrg = (ToBePrgrmd + (u32)XSK_ZYNQMP_EFUSEPS_USR4_FUSE);
/* Checking whether requested User FUSE bit programming is possible */
if (XilSKey_ZynqMp_EfusePs_UserFuses_TobeProgrammed(
&UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR4_FUSE][0],
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR4_FUSE][0],
UserEFuseToPrg) != (u32)XST_SUCCESS) {
Status = ((u32)XSK_EFUSEPS_ERROR_WRITE_USER4_FUSE |
(u32)XSK_EFUSEPS_ERROR_USER_BIT_CANT_REVERT);
goto END;
}
}
if (InstancePtr->PrgrmUser5Fuse == TRUE) {
UserFuseRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_USER_5_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&UserFuseRead,
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR5_FUSE][0],
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->User5Fuses,
&(UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR5_FUSE][0]),
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
UserEFuseToPrg = (ToBePrgrmd + (u32)XSK_ZYNQMP_EFUSEPS_USR5_FUSE);
/* Checking whether requested User FUSE bit programming is possible */
if (XilSKey_ZynqMp_EfusePs_UserFuses_TobeProgrammed(
&UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR5_FUSE][0],
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR5_FUSE][0],
UserEFuseToPrg) != (u32)XST_SUCCESS) {
Status = ((u32)XSK_EFUSEPS_ERROR_WRITE_USER5_FUSE |
(u32)XSK_EFUSEPS_ERROR_USER_BIT_CANT_REVERT);
goto END;
}
}
if (InstancePtr->PrgrmUser6Fuse == TRUE) {
UserFuseRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_USER_6_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&UserFuseRead,
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR6_FUSE][0],
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->User6Fuses,
&(UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR6_FUSE][0]),
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
UserEFuseToPrg = (ToBePrgrmd + (u32)XSK_ZYNQMP_EFUSEPS_USR6_FUSE);
/* Checking whether requested User FUSE bit programming is possible */
if (XilSKey_ZynqMp_EfusePs_UserFuses_TobeProgrammed(
&UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR6_FUSE][0],
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR6_FUSE][0],
UserEFuseToPrg) != (u32)XST_SUCCESS) {
Status = ((u32)XSK_EFUSEPS_ERROR_WRITE_USER6_FUSE |
(u32)XSK_EFUSEPS_ERROR_USER_BIT_CANT_REVERT);
goto END;
}
}
if (InstancePtr->PrgrmUser7Fuse == TRUE) {
UserFuseRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_USER_7_OFFSET);
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&UserFuseRead,
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR7_FUSE][0],
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->User7Fuses,
&(UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR7_FUSE][0]),
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
UserEFuseToPrg = (ToBePrgrmd + XSK_ZYNQMP_EFUSEPS_USR7_FUSE);
/* Checking whether requested User FUSE bit programming is possible */
if (XilSKey_ZynqMp_EfusePs_UserFuses_TobeProgrammed(
&UserFuses_Write[XSK_ZYNQMP_EFUSEPS_USR7_FUSE][0],
&UserFuses_Read[XSK_ZYNQMP_EFUSEPS_USR7_FUSE][0],
UserEFuseToPrg) != (u32)XST_SUCCESS) {
Status = ((u32)XSK_EFUSEPS_ERROR_WRITE_USER7_FUSE |
(u32)XSK_EFUSEPS_ERROR_USER_BIT_CANT_REVERT);
goto END;
}
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/*
* This function programs RSA enable secure control bits of eFUSE
*
* @param SecBits_read is a pointer which holds 32 bits of secure
* control register.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note For ZynqMP silicon version 1.0 and 2.0 RSA authentication is
* enabled only by programming 24 and 25 bits of SEC_CTRL register
* but from silicon V3.0 bits 11:25 should be programmed
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_Enable_Rsa(
u8 *SecBits_read)
{
u32 Bit;
u32 Status = (u32)XST_FAILURE;
XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0;
u32 Row = XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW;
u32 BitStart = 0U;
u32 BitEnd = 0U;
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
u32 Silicon_Ver = XGetPSVersion_Info();
/* Program all 15 bits to enable RSA authentication */
if (Silicon_Ver > (u32)XPS_VERSION_2) {
BitStart = (u32)XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT1;
BitEnd = (u32)XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT15;
}
/* Program only 24 and 25 bits of SEC_CTRL register */
else {
BitStart = (u32)XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT14;
BitEnd = (u32)XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT15;
}
#endif
for (Bit = BitStart; Bit <= BitEnd; Bit++) {
/* Program only if the bit is not already programmed */
if (SecBits_read[Bit] == 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit((u8)Row,
(u8)Bit, EfuseType);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
}
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/*
* This function initializes sysmonpsu driver.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_Init(void)
{
u32 Status = (u32)XST_FAILURE;
#if defined (XSK_OVERRIDE_SYSMON_CFG)
if (Init_Done != TRUE) {
/* Initialize sysmon PSU */
Status = XilSKey_EfusePs_XAdcInit();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
Init_Done = TRUE;
}
Status = (u32)XST_SUCCESS;
#else
Status = XilSKey_EfusePs_XAdcCfgValidate();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
#endif
END:
return Status;
}
/*****************************************************************************/
/*
* This function is used by PMUFW IPI call handler for programming eFUSE
*
* @param AddrHigh Higher 32-bit address of the XilSKey_Efuse structure.
* @param AddrLow Lower 32-bit address of the XilSKey_Efuse structure.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
******************************************************************************/
u32 XilSkey_ZynqMpEfuseAccess(const u32 AddrHigh, const u32 AddrLow)
{
u32 Status = (u32)XST_FAILURE;
u64 Addr = ((u64)AddrHigh << 32U) | (u64)AddrLow;
XilSKey_Efuse *EfuseAccess = (XilSKey_Efuse *)(UINTPTR)Addr;
/* Read bits */
if (EfuseAccess->Flag == 0x0U) {
Status = XilSKey_ZynqMpEfuseRead(AddrHigh, AddrLow);
}
/* Write bits */
else {
Status = XilSKey_ZynqMpEfuseWrite(AddrHigh, AddrLow);
}
return Status;
}
/*****************************************************************************/
/*
* This function provides support to program eFUSE memory
*
* @param AddrHigh Higher 32-bit address of the XilSKey_Efuse
* structure.
* @param AddrLow Lower 32-bit address of the XilSKey_Efuse
structure.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note None.
*
******************************************************************************/
static u32 XilSKey_ZynqMpEfuseWrite(const u32 AddrHigh, const u32 AddrLow)
{
u32 Status = (u32)XST_FAILURE;
u64 Addr = ((u64)AddrHigh << 32U) | (u64)AddrLow;
XilSKey_Efuse *EfuseAccess = (XilSKey_Efuse *)(UINTPTR)Addr;
u8 *Val = (u8 *)(UINTPTR)EfuseAccess->Src;
u32 *Val32;
XilSKey_ZynqMpEPs EfuseInstance = {0};
u8 Index;
u32 ReadReg;
switch(EfuseAccess->Offset) {
case (XSK_ZYNQMP_EFUSEPS_USER_0_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmUser0Fuse = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES;
Index++) {
EfuseInstance.User0Fuses[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_USER_1_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmUser1Fuse = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES;
Index++) {
EfuseInstance.User1Fuses[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_USER_2_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmUser2Fuse = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES;
Index++) {
EfuseInstance.User2Fuses[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_USER_3_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmUser3Fuse = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES;
Index++) {
EfuseInstance.User3Fuses[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_USER_4_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmUser4Fuse = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES;
Index++) {
EfuseInstance.User4Fuses[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_USER_5_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmUser5Fuse = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES;
Index++) {
EfuseInstance.User5Fuses[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_USER_6_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmUser6Fuse = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES;
Index++) {
EfuseInstance.User6Fuses[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_USER_7_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmUser7Fuse = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_USER_FUSE_ROW_LEN_IN_BYTES;
Index++) {
EfuseInstance.User7Fuses[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
Val32 = (u32 *)Val;
ReadReg = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_OFFSET);
*Val32 = *Val32 & (~ReadReg);
/* No new bits needs to be programmed */
if (*Val32 == 0x00U) {
Status = (u32)XST_SUCCESS;
goto END;
}
if ((*Val32 &
((u32)XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_RESERVED_MASK |
(u32)XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_LBIST_EN_MASK)) != 0U) {
Status = (u32)XSK_EFUSEPS_ERROR_RESRVD_BITS_PRGRMG;
goto END;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.UserWrLk0 = TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.UserWrLk1 = TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.UserWrLk2 = TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.UserWrLk3 = TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.UserWrLk4 = TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.UserWrLk5 = TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.UserWrLk6 = TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.UserWrLk7 = TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_FPD_SC_EN_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.FpdScEn = TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_LPD_SC_EN_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.LpdScEn = TRUE;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_SEC_CTRL_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
Val32 = (u32 *)Val;
ReadReg = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_OFFSET);
/* Only taking the bits to be programmed */
*Val32 = *Val32 & (~ReadReg);
if (*Val32 == 0x00U) {
Status = (u32)XST_SUCCESS;
goto END;
}
if ((*Val32 &
(XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_MASK |
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_MASK |
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_MASK |
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_MASK)) !=
0x00U) {
Status = (u32)XSK_EFUSEPS_ERROR_RESRVD_BITS_PRGRMG;
goto END;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_MASK) != 0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.AesKeyRead =
TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_MASK) != 0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.AesKeyWrite =
TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.BbramDisable =
TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_MASK) != 0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.ErrorDisable =
TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_MASK) != 0x00U){
EfuseInstance.PrgrmgSecCtrlBits.ProgGate = TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_MASK) != 0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.SecureLock =
TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.PPK0WrLock =
TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.PPK0InVld =
TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.PPK1WrLock =
TRUE;
}
if ((*Val32 &
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_MASK) !=
0x00U) {
EfuseInstance.PrgrmgSecCtrlBits.PPK1InVld =
TRUE;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_SPK_ID_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmSpkID = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BYTES;
Index++) {
EfuseInstance.SpkId[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_AES_KEY_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size !=
(XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BYTES >> 2U)) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmAesKey = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BYTES;
Index++) {
EfuseInstance.AESKey[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_PPK0_0_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size !=
(XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES >> 2)) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmPpk0Hash = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES;
Index++) {
EfuseInstance.Ppk0Hash[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_PPK1_0_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size !=
(XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES >> 2U)) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
EfuseInstance.PrgrmPpk1Hash = TRUE;
for (Index = 0U;
Index < XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES;
Index++) {
EfuseInstance.Ppk1Hash[Index] = *Val;
Val = Val + 1U;
}
Status = (u32)XST_SUCCESS;
break;
default:
Status = (u32)XSK_EFUSEPS_ERROR_ADDR_ACCESS;
break;
}
if (Status == (u32)XST_SUCCESS) {
Status = XilSKey_ZynqMp_EfusePs_Write(&EfuseInstance);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
}
END:
return Status;
}
/*****************************************************************************/
/*
* This function provides support to read user eFUSEs
*
* @param Offset Offset specifies the user fuses offset to be read.
* @param Buffer Requested user fuses values will be stored in this
* pointer.
* @param Size To be specified in words.
* @param UsrFuseNum Userfuse number
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note None.
*
******************************************************************************/
static u32 XilSkey_ZynqMpUsrFuseRd(u32 Offset, u32 *Buffer,
u32 Size, u8 UsrFuseNum)
{
u32 Status = (u32)XST_FAILURE;
u8 FuseNum = UsrFuseNum;
u32 *Value = Buffer;
u32 Words = Size;
/* Check if the requested bytes are exceeding */
if ((Offset + (Words * XSK_EFUSEPS_BYTES_IN_WORD) -
XSK_EFUSEPS_BYTES_IN_WORD) >
((XSK_ZYNQMP_EFUSEPS_USER_7_OFFSET & 0xFFU))) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
do {
Status = XilSKey_ZynqMp_EfusePs_ReadUserFuse(Value, FuseNum,
XSK_EFUSEPS_READ_FROM_CACHE);
Value++;
FuseNum++;
Words--;
} while (Words != 0U);
END:
return Status;
}
/*****************************************************************************/
/*
* This function provides support to read eFUSE memory
*
* @param AddrHigh Higher 32-bit address of the
* XilSKey_Efuse structure.
* @param AddrLow Lower 32-bit address of the XilSKey_Efuse
* structure.
*
* @return
* XST_SUCCESS - On success
* ErrorCode - on Failure
*
* @note None.
*
******************************************************************************/
static u32 XilSKey_ZynqMpEfuseRead(const u32 AddrHigh, const u32 AddrLow)
{
u32 Status = (u32)XST_FAILURE;
u64 Addr = ((u64)AddrHigh << 32) | (u64)AddrLow;
XilSKey_Efuse *EfuseAccess = (XilSKey_Efuse *)(UINTPTR)Addr;
u32 *Val = (u32 *)(UINTPTR)EfuseAccess->Src;
u8 UsrEfuseNo;
switch(EfuseAccess->Offset) {
case (XSK_ZYNQMP_EFUSEPS_DNA_0_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size !=
(XSK_ZYNQMP_EFUSEPS_DNA_LEN_IN_BYTES >> 2)) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
XilSKey_ZynqMp_EfusePs_ReadDna(Val);
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_USER_0_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
UsrEfuseNo = XSK_ZYNQMP_EFUSEPS_USR0_FUSE;
Status = XilSkey_ZynqMpUsrFuseRd(EfuseAccess->Offset,
Val, EfuseAccess->Size,
UsrEfuseNo);
break;
case (XSK_ZYNQMP_EFUSEPS_USER_1_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
UsrEfuseNo = XSK_ZYNQMP_EFUSEPS_USR1_FUSE;
Status = XilSkey_ZynqMpUsrFuseRd(EfuseAccess->Offset,
Val,
EfuseAccess->Size,
UsrEfuseNo);
break;
case (XSK_ZYNQMP_EFUSEPS_USER_2_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
UsrEfuseNo = XSK_ZYNQMP_EFUSEPS_USR2_FUSE;
Status = XilSkey_ZynqMpUsrFuseRd(EfuseAccess->Offset,
Val,
EfuseAccess->Size,
UsrEfuseNo);
break;
case (XSK_ZYNQMP_EFUSEPS_USER_3_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
UsrEfuseNo = XSK_ZYNQMP_EFUSEPS_USR3_FUSE;
Status = XilSkey_ZynqMpUsrFuseRd(EfuseAccess->Offset,
Val,
EfuseAccess->Size,
UsrEfuseNo);
break;
case (XSK_ZYNQMP_EFUSEPS_USER_4_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
UsrEfuseNo = XSK_ZYNQMP_EFUSEPS_USR4_FUSE;
Status = XilSkey_ZynqMpUsrFuseRd(EfuseAccess->Offset,
Val,
EfuseAccess->Size,
UsrEfuseNo);
break;
case (XSK_ZYNQMP_EFUSEPS_USER_5_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
UsrEfuseNo = XSK_ZYNQMP_EFUSEPS_USR5_FUSE;
Status = XilSkey_ZynqMpUsrFuseRd(EfuseAccess->Offset,
Val,
EfuseAccess->Size,
UsrEfuseNo);
break;
case (XSK_ZYNQMP_EFUSEPS_USER_6_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
UsrEfuseNo = XSK_ZYNQMP_EFUSEPS_USR6_FUSE;
Status = XilSkey_ZynqMpUsrFuseRd(EfuseAccess->Offset,
Val,
EfuseAccess->Size,
UsrEfuseNo);
break;
case (XSK_ZYNQMP_EFUSEPS_USER_7_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
UsrEfuseNo = XSK_ZYNQMP_EFUSEPS_USR7_FUSE;
Status = XilSkey_ZynqMpUsrFuseRd(EfuseAccess->Offset,
Val,
EfuseAccess->Size,
UsrEfuseNo);
break;
case (XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
*Val = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_OFFSET);
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_PUF_CHASH_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
*Val = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PUF_CHASH_OFFSET);
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_PUF_MISC_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
*Val = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PUF_MISC_OFFSET);
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_SEC_CTRL_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
*Val = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_SEC_CTRL_OFFSET);
Status = (u32)XST_SUCCESS;
break;
case (XSK_ZYNQMP_EFUSEPS_SPK_ID_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size != XSK_EFUSEPS_ONE_WORD) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_ReadSpkId(Val,
XSK_EFUSEPS_READ_FROM_CACHE);
break;
case (XSK_ZYNQMP_EFUSEPS_PPK0_0_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size !=
(XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES >> 2)) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_ReadPpk0Hash(Val,
XSK_EFUSEPS_READ_FROM_CACHE);
break;
case (XSK_ZYNQMP_EFUSEPS_PPK1_0_OFFSET &
XSK_EFUSEPS_OFFSET_MASK):
if (EfuseAccess->Size !=
(XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES >> 2)) {
Status = (u32)XSK_EFUSEPS_ERROR_BYTES_REQUEST;
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_ReadPpk1Hash(Val,
XSK_EFUSEPS_READ_FROM_CACHE);
break;
default:
Status = (u32)XSK_EFUSEPS_ERROR_ADDR_ACCESS;
break;
}
END:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilfpga_v5_2/src/interface/zynqmp/xilfpga_ipi_pcap.c
/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilfpga_ipi_pcap.c
*
* This file contains the definitions of bitstream loading functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- ----- -------- -------------------------------------------------------
* 5.2 Nava 14/02/20 Added Bitstream loading support by using IPI services.
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xilfpga.h"
#include "xilmailbox.h"
/************************** Constant Definitions *****************************/
#define PM_FPGA_LOAD 0x16U
#define PM_FPGA_GET_STATUS 0x17U
#define PM_FPGA_READ 0x2EU
#define FPGA_MSG_LEN 0x5U
#define FPGA_DATA_READBACK 0x1U
#define FPGA_REG_READBACK 0x0U
#define GET_STATUS_MSG_LEN 0x1U
#define FPGA_IPI_TYPE_BLOCKING 0x1U
#define FPGA_IPI_RESP1 0x1U
#define FPGA_IPI_RESP2 0x2U
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static u32 XFpga_IPI_WriteToPl(XFpga *InstancePtr);
static u32 XFpga_IPI_GetPLConfigDataPcap(const XFpga *InstancePtr);
static u32 XFpga_IPI_GetPLConfigRegPcap(const XFpga *InstancePtr);
static u32 XFpga_IPI_PcapStatus(void);
/************************** Variable Definitions *****************************/
XMailbox XMboxInstance;
/*****************************************************************************/
/* This API when called initializes the XFPGA interface with default settings.
* It Sets function pointers for the instance.
*
* @param InstancePtr Pointer to the XFgpa structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
******************************************************************************/
u32 XFpga_Initialize(XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
(void)memset(InstancePtr, 0U, sizeof(*InstancePtr));
InstancePtr->XFpga_WriteToPl = XFpga_IPI_WriteToPl;
InstancePtr->XFpga_GetConfigData = XFpga_IPI_GetPLConfigDataPcap;
InstancePtr->XFpga_GetConfigReg = XFpga_IPI_GetPLConfigRegPcap;
InstancePtr->XFpga_GetInterfaceStatus = XFpga_IPI_PcapStatus;
Status = XMailbox_Initialize(&XMboxInstance, 0U);
return Status;
}
/*****************************************************************************/
/* This function writes bitstream data into the PL.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_IPI_WriteToPl(XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
u32 ReqBuffer[FPGA_MSG_LEN] = {0};
UINTPTR BitstreamAddr = InstancePtr->WriteInfo.BitstreamAddr;
ReqBuffer[0U] = PM_FPGA_LOAD;
ReqBuffer[1U] = UPPER_32_BITS(BitstreamAddr);
ReqBuffer[2U] = (u32)BitstreamAddr;
ReqBuffer[3U] = InstancePtr->WriteInfo.AddrPtr_Size;
ReqBuffer[4U] = InstancePtr->WriteInfo.Flags;
/* Send an IPI Req Message */
Status = XMailbox_SendData(&XMboxInstance, XMAILBOX_IPI3, ReqBuffer,
FPGA_MSG_LEN, XILMBOX_MSG_TYPE_REQ,
FPGA_IPI_TYPE_BLOCKING);
if (Status != XST_SUCCESS) {
goto END;
}
Status = XMailbox_Recv(&XMboxInstance, XMAILBOX_IPI3, ReqBuffer,
FPGA_IPI_RESP1, XILMBOX_MSG_TYPE_RESP);
if (Status != XST_SUCCESS) {
goto END;
}
Status = ReqBuffer[0U];
END:
return Status;
}
/*****************************************************************************/
/**
*
* This function performs the readback of fpga configuration data/registers.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return
* - XFPGA_SUCCESS if successful
* - XFPGA_FAILURE if unsuccessful
*
* @note None.
****************************************************************************/
static u32 XFpga_IPI_GetPLConfigDataPcap(const XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
u32 ReqBuffer[FPGA_MSG_LEN] = {0};
UINTPTR ReadbackAddr = InstancePtr->ReadInfo.ReadbackAddr;
ReqBuffer[0U] = PM_FPGA_READ;
ReqBuffer[1U] = InstancePtr->ReadInfo.ConfigReg_NumFrames;
ReqBuffer[2U] = (u32)ReadbackAddr;
ReqBuffer[3U] = UPPER_32_BITS(ReadbackAddr);
ReqBuffer[4U] = FPGA_DATA_READBACK;
/* Send an IPI Req Message */
Status = XMailbox_SendData(&XMboxInstance, XMAILBOX_IPI3, ReqBuffer,
FPGA_MSG_LEN, XILMBOX_MSG_TYPE_REQ,
FPGA_IPI_TYPE_BLOCKING);
if (Status != XST_SUCCESS) {
goto END;
}
Status = XMailbox_Recv(&XMboxInstance, XMAILBOX_IPI3, ReqBuffer,
FPGA_IPI_RESP2, XILMBOX_MSG_TYPE_RESP);
if (Status != XST_SUCCESS) {
goto END;
}
Status = ReqBuffer[0U];
END:
return Status;
}
/*****************************************************************************/
/**
*
* This function performs the readback of fpga configuration data/registers.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return
* - XFPGA_SUCCESS if successful
* - XFPGA_FAILURE if unsuccessful
*
* @note None.
****************************************************************************/
static u32 XFpga_IPI_GetPLConfigRegPcap(const XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
u32 ReqBuffer[FPGA_MSG_LEN] = {0};
UINTPTR ReadbackAddr = InstancePtr->ReadInfo.ReadbackAddr;
ReqBuffer[0U] = PM_FPGA_READ;
ReqBuffer[1U] = InstancePtr->ReadInfo.ConfigReg_NumFrames;
ReqBuffer[2U] = (u32)ReadbackAddr;
ReqBuffer[3U] = UPPER_32_BITS(ReadbackAddr);
ReqBuffer[4U] = FPGA_REG_READBACK;
/* Send an IPI Req Message */
Status = XMailbox_SendData(&XMboxInstance, XMAILBOX_IPI3, ReqBuffer,
FPGA_MSG_LEN, XILMBOX_MSG_TYPE_REQ,
FPGA_IPI_TYPE_BLOCKING);
if (Status != XST_SUCCESS) {
goto END;
}
Status = XMailbox_Recv(&XMboxInstance, XMAILBOX_IPI3, ReqBuffer,
FPGA_IPI_RESP2, XILMBOX_MSG_TYPE_RESP);
if (Status != XST_SUCCESS) {
goto END;
}
memcpy((char *)ReadbackAddr, (char *)&ReqBuffer[1U],
sizeof(ReqBuffer[1U]));
Status = ReqBuffer[0U];
END:
return Status;
}
/*****************************************************************************/
/** Provides the STATUS of PCAP interface
*
* @param None
*
* @return Status of the PCAP interface.
*
*****************************************************************************/
static u32 XFpga_IPI_PcapStatus(void)
{
u32 Status = XFPGA_FAILURE;
u32 RegVal = XFPGA_INVALID_INTERFACE_STATUS;
u32 ReqBuffer[FPGA_IPI_RESP2] = {0};
ReqBuffer[0U] = PM_FPGA_GET_STATUS;
/* Send an IPI Req Message */
Status = XMailbox_SendData(&XMboxInstance, XMAILBOX_IPI3, ReqBuffer,
GET_STATUS_MSG_LEN, XILMBOX_MSG_TYPE_REQ,
FPGA_IPI_TYPE_BLOCKING);
if (Status != XST_SUCCESS) {
goto END;
}
Status = XMailbox_Recv(&XMboxInstance, XMAILBOX_IPI3, ReqBuffer,
FPGA_IPI_RESP2, XILMBOX_MSG_TYPE_RESP);
if (Status != XST_SUCCESS) {
goto END;
}
RegVal = ReqBuffer[1U];
END:
return RegVal;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_mod_legacy.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_default.h"
#include "xpfw_rom_interface.h"
#include "xpfw_config.h"
#include "xpfw_core.h"
#include "xpfw_events.h"
#include "xpfw_module.h"
#include "xpfw_mod_legacy.h"
/* CfgInit Handler */
static void LegacyCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData,
u32 Len)
{
/* Used for Power Up/Dn request handling */
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_REQ_PWRUP) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,"LegacyCfgInit: Failed to register "
"event ID: %d\r\n",XPFW_EV_REQ_PWRUP)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_REQ_PWRDN) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,"LegacyCfgInit: Failed to register "
"event ID: %d\r\n",XPFW_EV_REQ_PWRDN)
}
if (XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_REQ_ISOLATION) != XST_SUCCESS) {
XPfw_Printf(DEBUG_DETAILED,"LegacyCfgInit: Failed to register "
"event ID: %d\r\n",XPFW_EV_REQ_ISOLATION)
}
XPfw_Printf(DEBUG_DETAILED,"LEGACY PWR UP/DN/ISO (MOD-%d): "
"Initialized.\r\n", ModPtr->ModId);
}
/* Event Handler */
static void LegacyEventHandler(const XPfw_Module_t *ModPtr, u32 EventId)
{
if (XPFW_EV_REQ_PWRUP == EventId) {
/* Call ROM Handler for PwrUp */
XPfw_Printf(DEBUG_DETAILED,"XPFW: Calling ROM PWRUP Handler..");
XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUP_REQS]();
XPfw_Printf(DEBUG_DETAILED,"Done\r\n");
}
if (XPFW_EV_REQ_PWRDN == EventId) {
/* Call ROM Handler for PwrDn */
XPfw_Printf(DEBUG_DETAILED,"XPFW: Calling ROM PWRDN Handler..");
XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDN_REQS]();
XPfw_Printf(DEBUG_DETAILED,"Done\r\n");
}
if (XPFW_EV_REQ_ISOLATION == EventId) {
/* Call ROM Handler for Isolation */
XPfw_Printf(DEBUG_DETAILED,"XPFW: Calling ROM Isolation Handler..");
XpbrServHndlrTbl[XPBR_SERV_EXT_ISO_REQS]();
XPfw_Printf(DEBUG_DETAILED,"Done\r\n");
}
}
/*
* Create a Mod and assign the Handlers. We will call this function
* from XPfw_UserStartup()
*/
void ModLegacyInit(void)
{
const XPfw_Module_t *LegacyModPtr = XPfw_CoreCreateMod();
if (XST_SUCCESS != XPfw_CoreSetCfgHandler(LegacyModPtr, LegacyCfgInit)) {
XPfw_Printf(DEBUG_DETAILED,"Legacy: Set Cfg handler failed\r\n");
} else if (XST_SUCCESS !=
XPfw_CoreSetEventHandler(LegacyModPtr, LegacyEventHandler)) {
XPfw_Printf(DEBUG_DETAILED,"Legacy: Set Event handler failed\r\n");
}
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_9/src/xrtcpsu_sinit.c
/******************************************************************************
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrtcpsu_sinit.c
* @addtogroup rtcpsu_v1_9
* @{
*
* This file contains the implementation of the XRtcPsu driver's static
* initialization functionality.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00 kvn 04/21/15 First release.
* 1.7 sne 03/01/19 Added Versal support.
* 1.7 sne 03/01/19 Fixed violations according to MISRAC-2012 standards
* modified the code such as
* No brackets to loop body,Declared the poiner param
* as Pointer to const,No brackets to then/else,
* Literal value requires a U suffix,Casting operation to a pointer
* Array has no bounds specified,Logical conjunctions need brackets.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xrtcpsu.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern XRtcPsu_Config XRtcPsu_ConfigTable[XPAR_XRTCPSU_NUM_INSTANCES];
/*****************************************************************************/
/**
*
* This function looks for the device configuration based on the unique device
* ID. The table XRtcPsu_ConfigTable[] contains the configuration information for
* each device in the system.
*
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
*
******************************************************************************/
XRtcPsu_Config *XRtcPsu_LookupConfig(u16 DeviceId)
{
XRtcPsu_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; Index < (u32)XPAR_XRTCPSU_NUM_INSTANCES; Index++) {
if (XRtcPsu_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XRtcPsu_ConfigTable[Index];
break;
}
}
return (XRtcPsu_Config *)CfgPtr;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/rfdc_v8_0/src/xrfdc_mixer.c
/******************************************************************************
* Copyright (C) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xrfdc_mixer.c
* @addtogroup rfdc_v8_0
* @{
*
* Contains the interface functions of the Mixer Settings in XRFdc driver.
* See xrfdc.h for a detailed description of the device and driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 5.0 sk 08/06/18 Initial release
* 5.1 cog 01/29/19 Replace structure reference ADC checks with
* function.
* cog 01/29/19 XRFdc_SetCoarseMixer and MixerRangeCheck now need
* Tile_id as a parameter.
* cog 01/29/19 Rename DataType to MixerInputDataType for
* readability.
* 7.0 cog 05/13/19 Formatting changes.
* cog 06/12/19 Fixed issue where positive NCO frequencies were not
* being set correctly.
* cog 07/03/19 Added new off mode for mixers (both mixers off).
* cog 08/02/19 Formatting changes.
* cog 09/01/19 Changed the MACRO for turning off the mixer.
* cog 09/01/19 Fixed issue where going from calibration mode 1 to
* any calibration mode caused the course mixer mode to
* be incorrect.
* cog 09/19/19 Calibration mode 1 does not need the frequency shifting workaround
* for Gen 3 devices.
* 7.1 cog 11/28/19 Prevent setting non compliant mixer settings when in the bypass
* datapath mode.
* cog 12/20/19 Metal log messages are now more descriptive.
* 12/23/19 Fabric rate is now auto-corrected when changing a miixer from IQ
* to real (and vice versa).
* cog 01/29/20 Fixed metal log typos.
* 8.0 cog 02/10/20 Updated addtogroup.
* cog 03/05/20 IMR datapath modes require the frequency word to be doubled.
* cog 03/23/20 Relegate the datapath being in bypass mode to a warning when
* getting mixer parameters.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xrfdc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
static void XRFdc_SetFineMixer(XRFdc *InstancePtr, u32 BaseAddr, XRFdc_Mixer_Settings *MixerSettingsPtr);
static void XRFdc_SetCoarseMixer(XRFdc *InstancePtr, u32 Type, u32 BaseAddr, u32 Tile_Id, u32 Block_Id,
u32 CoarseMixFreq, XRFdc_Mixer_Settings *MixerSettingsPtr);
static u32 XRFdc_MixerRangeCheck(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
XRFdc_Mixer_Settings *MixerSettingsPtr);
static void XRFdc_MixersOff(XRFdc *InstancePtr, u32 BaseAddr);
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* The API is used to update various mixer settings, fine, coarse, NCO etc.
* Mixer/NCO settings passed are used to update the corresponding
* block level registers. Driver structure is updated with the new values.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param MixerSettingsPtr Pointer to the XRFdc_Mixer_Settings structure
* in which the Mixer/NCO settings are passed.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note FineMixerScale in Mixer_Settings structure can have 3 values.
* XRFDC_MIXER_SCALE_* represents the valid values.
* XRFDC_MIXER_SCALE_AUTO - If mixer mode is R2C, Mixer Scale is
* set to 1 and for other modes mixer scale is set to 0.7
* XRFDC_MIXER_SCALE_1P0 - To set fine mixer scale to 1.
* XRFDC_MIXER_SCALE_0P7 - To set fine mixer scale to 0.7.
*
******************************************************************************/
u32 XRFdc_SetMixerSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
XRFdc_Mixer_Settings *MixerSettingsPtr)
{
u32 Status;
u16 ReadReg;
u32 BaseAddr;
double SamplingRate;
s64 Freq;
s32 PhaseOffset;
u32 NoOfBlocks;
u32 Index;
XRFdc_Mixer_Settings *MixerConfigPtr;
u8 CalibrationMode = 0U;
u32 CoarseMixFreq;
double NCOFreq;
u32 NyquistZone = 0U;
u32 Offset;
u32 DatapathMode;
u32 FabricRate;
u32 BWDiv = XRFDC_FULL_BW_DIVISOR;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(MixerSettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
goto RETURN_PATH;
}
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
if (Type == XRFDC_DAC_TILE) {
DatapathMode = XRFdc_RDReg(InstancePtr, XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id),
XRFDC_DAC_DATAPATH_OFFSET, XRFDC_DATAPATH_MODE_MASK);
switch (DatapathMode) {
case XRFDC_DAC_INT_MODE_FULL_BW_BYPASS:
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR,
"\n Can't set mixer as DAC %u DUC %u is in bypass mode in %s\r\n", Tile_Id,
Block_Id, __func__);
goto RETURN_PATH;
case XRFDC_DAC_INT_MODE_HALF_BW_IMR:
BWDiv = XRFDC_HALF_BW_DIVISOR;
break;
case XRFDC_DAC_INT_MODE_FULL_BW:
default:
BWDiv = XRFDC_FULL_BW_DIVISOR;
break;
}
}
}
Status = XRFdc_MixerRangeCheck(InstancePtr, Type, Tile_Id, Block_Id, MixerSettingsPtr);
if (Status != XRFDC_SUCCESS) {
goto RETURN_PATH;
}
Index = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
NoOfBlocks = XRFDC_NUM_OF_BLKS2;
if (Block_Id == XRFDC_BLK_ID1) {
Index = XRFDC_BLK_ID2;
NoOfBlocks = XRFDC_NUM_OF_BLKS4;
}
} else {
NoOfBlocks = Block_Id + 1U;
}
for (; Index < NoOfBlocks; Index++) {
if (Type == XRFDC_ADC_TILE) {
/* ADC */
MixerConfigPtr =
&InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].Mixer_Settings;
SamplingRate = InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.SampleRate;
} else {
/* DAC */
MixerConfigPtr =
&InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Index].Mixer_Settings;
SamplingRate = InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.SampleRate / BWDiv;
}
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Index);
if (SamplingRate <= 0) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Incorrect Sampling rate (%2.4f GHz) for %s %u in %s\r\n",
SamplingRate, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
} else {
metal_log(METAL_LOG_DEBUG, "\n Sampling rate is %2.4f GHz for %s %u in %s\r\n", SamplingRate,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
}
SamplingRate *= XRFDC_MILLI;
/* Set MixerInputDataType for ADC and DAC */
if (Type == XRFDC_DAC_TILE) {
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_DAC_ITERP_DATA_OFFSET);
FabricRate = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET,
XRFDC_DAC_FAB_RATE_RD_MASK);
FabricRate = FabricRate >> XRFDC_FAB_RATE_RD_SHIFT;
if (((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2C) ||
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2R)) &&
(InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_REAL)) {
ReadReg |= XRFDC_DAC_INTERP_DATA_MASK;
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Index].MixerInputDataType =
XRFDC_DATA_TYPE_IQ;
FabricRate <<= 1;
} else if ((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_R2R) &&
(InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ)) {
InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Index].MixerInputDataType =
XRFDC_DATA_TYPE_REAL;
ReadReg &= ~XRFDC_DAC_INTERP_DATA_MASK;
FabricRate >>= 1;
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_DAC_FAB_RATE_RD_MASK,
(FabricRate << XRFDC_FAB_RATE_RD_SHIFT));
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_DAC_ITERP_DATA_OFFSET, ReadReg);
} else {
FabricRate = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET,
XRFDC_ADC_FAB_RATE_WR_MASK);
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_DECI_CONFIG_OFFSET);
ReadReg &= ~XRFDC_DEC_CFG_MASK;
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) {
ReadReg |= XRFDC_DEC_CFG_4GSPS_MASK;
} else if ((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2C) ||
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_R2C)) {
ReadReg |= XRFDC_DEC_CFG_IQ_MASK;
} else {
ReadReg |= XRFDC_DEC_CFG_CHA_MASK;
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_DECI_CONFIG_OFFSET, ReadReg);
if ((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2C) &&
(InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_REAL)) {
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType =
XRFDC_DATA_TYPE_IQ;
FabricRate <<= 1;
} else if (((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_R2C) ||
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_R2R)) &&
(InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType ==
XRFDC_DATA_TYPE_IQ)) {
InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Index].MixerInputDataType =
XRFDC_DATA_TYPE_REAL;
FabricRate >>= 1;
}
if (XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_FABRIC_RATE_OFFSET,
XRFDC_ADC_FAB_RATE_WR_MASK, FabricRate);
}
}
/* Set NCO Phase Mode */
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
if ((Index == XRFDC_BLK_ID0) || (Index == XRFDC_BLK_ID2)) {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_NCO_PHASE_MOD_OFFSET,
XRFDC_NCO_PHASE_MOD_EVEN);
} else {
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_NCO_PHASE_MOD_OFFSET,
XRFDC_NCO_PHASE_MODE_ODD);
}
}
/* Update NCO, CoarseMix freq based on calibration mode */
CoarseMixFreq = MixerSettingsPtr->CoarseMixFreq;
NCOFreq = MixerSettingsPtr->Freq;
if (Type == XRFDC_ADC_TILE) {
Status = XRFdc_GetCalibrationMode(InstancePtr, Tile_Id, Block_Id, &CalibrationMode);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if (CalibrationMode == XRFDC_CALIB_MODE1) {
switch (CoarseMixFreq) {
case XRFDC_COARSE_MIX_BYPASS:
CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO;
break;
case XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR:
CoarseMixFreq = XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR;
break;
case XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO:
CoarseMixFreq = XRFDC_COARSE_MIX_BYPASS;
break;
case XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR:
CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR;
break;
default:
CoarseMixFreq = XRFDC_COARSE_MIX_OFF;
break;
}
NCOFreq -= SamplingRate / 2.0;
}
}
}
if ((NCOFreq < -(SamplingRate / 2.0)) || (NCOFreq > (SamplingRate / 2.0))) {
Status = XRFdc_GetNyquistZone(InstancePtr, Type, Tile_Id, Block_Id, &NyquistZone);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
do {
if (NCOFreq < -(SamplingRate / 2.0)) {
NCOFreq += SamplingRate;
}
if (NCOFreq > (SamplingRate / 2.0)) {
NCOFreq -= SamplingRate;
}
} while ((NCOFreq < -(SamplingRate / 2.0)) || (NCOFreq > (SamplingRate / 2.0)));
if ((NyquistZone == XRFDC_EVEN_NYQUIST_ZONE) && (NCOFreq != 0)) {
NCOFreq *= -1;
}
}
/* NCO Frequency */
Freq = ((NCOFreq * XRFDC_NCO_FREQ_MULTIPLIER) / SamplingRate);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_NCO_FQWD_LOW_OFFSET, (u16)Freq);
ReadReg = (Freq >> XRFDC_NCO_FQWD_MID_SHIFT) & XRFDC_NCO_FQWD_MID_MASK;
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_NCO_FQWD_MID_OFFSET, (u16)ReadReg);
ReadReg = (Freq >> XRFDC_NCO_FQWD_UPP_SHIFT) & XRFDC_NCO_FQWD_UPP_MASK;
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_NCO_FQWD_UPP_OFFSET, (u16)ReadReg);
/* Phase Offset */
PhaseOffset = ((MixerSettingsPtr->PhaseOffset * XRFDC_NCO_PHASE_MULTIPLIER) /
XRFDC_MIXER_PHASE_OFFSET_UP_LIMIT);
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_NCO_PHASE_LOW_OFFSET, (u16)PhaseOffset);
ReadReg = (PhaseOffset >> XRFDC_NCO_PHASE_UPP_SHIFT) & XRFDC_NCO_PHASE_UPP_MASK;
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_NCO_PHASE_UPP_OFFSET, ReadReg);
switch (MixerSettingsPtr->MixerType) {
case XRFDC_MIXER_TYPE_COARSE:
XRFdc_SetCoarseMixer(InstancePtr, Type, BaseAddr, Tile_Id, Index, CoarseMixFreq,
MixerSettingsPtr);
break;
case XRFDC_MIXER_TYPE_FINE:
XRFdc_SetFineMixer(InstancePtr, BaseAddr, MixerSettingsPtr);
break;
default:
XRFdc_MixersOff(InstancePtr, BaseAddr);
break;
}
/* Fine Mixer Scale */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET);
if (MixerSettingsPtr->FineMixerScale == XRFDC_MIXER_SCALE_1P0) {
ReadReg |= XRFDC_FINE_MIX_SCALE_MASK;
InstancePtr->UpdateMixerScale = 0x1U;
} else if (MixerSettingsPtr->FineMixerScale == XRFDC_MIXER_SCALE_0P7) {
ReadReg &= ~XRFDC_FINE_MIX_SCALE_MASK;
InstancePtr->UpdateMixerScale = 0x1U;
} else {
InstancePtr->UpdateMixerScale = 0x0U;
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET, ReadReg);
/* Event Source */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_NCO_UPDT_OFFSET, XRFDC_NCO_UPDT_MODE_MASK,
MixerSettingsPtr->EventSource);
if (MixerSettingsPtr->EventSource == XRFDC_EVNT_SRC_IMMEDIATE) {
if (Type == XRFDC_ADC_TILE) {
Offset = XRFDC_ADC_UPDATE_DYN_OFFSET;
} else {
Offset = XRFDC_DAC_UPDATE_DYN_OFFSET;
}
XRFdc_ClrSetReg(InstancePtr, BaseAddr, Offset, XRFDC_UPDT_EVNT_MASK, XRFDC_UPDT_EVNT_NCO_MASK);
}
/* Update the instance with new values */
MixerConfigPtr->EventSource = MixerSettingsPtr->EventSource;
MixerConfigPtr->PhaseOffset = MixerSettingsPtr->PhaseOffset;
MixerConfigPtr->MixerMode = MixerSettingsPtr->MixerMode;
MixerConfigPtr->CoarseMixFreq = MixerSettingsPtr->CoarseMixFreq;
MixerConfigPtr->Freq = MixerSettingsPtr->Freq;
MixerConfigPtr->MixerType = MixerSettingsPtr->MixerType;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
* Static API used to do the Mixer Settings range check.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param MixerSettingsPtr Pointer to the XRFdc_Mixer_Settings structure
* in which the Mixer/NCO settings are passed.
*
* @return
* - XRFDC_SUCCESS if mixer settings are within the range.
* - XRFDC_FAILURE if mixer settings are not in valid range
*
* @note None.
*
******************************************************************************/
static u32 XRFdc_MixerRangeCheck(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
XRFdc_Mixer_Settings *MixerSettingsPtr)
{
u32 Status;
if ((MixerSettingsPtr->PhaseOffset >= XRFDC_MIXER_PHASE_OFFSET_UP_LIMIT) ||
(MixerSettingsPtr->PhaseOffset <= XRFDC_MIXER_PHASE_OFFSET_LOW_LIMIT)) {
metal_log(METAL_LOG_ERROR, "\n Invalid phase offset value (%lf) for %s %u block %u in %s\r\n",
MixerSettingsPtr->PhaseOffset, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id,
__func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((MixerSettingsPtr->EventSource > XRFDC_EVNT_SRC_PL) ||
((MixerSettingsPtr->EventSource == XRFDC_EVNT_SRC_MARKER) && (Type == XRFDC_ADC_TILE))) {
metal_log(METAL_LOG_ERROR, "\n Invalid event source selection (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->EventSource, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id,
__func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (MixerSettingsPtr->MixerMode > XRFDC_MIXER_MODE_R2R) {
metal_log(METAL_LOG_ERROR, "\n Invalid fine mixer mode in (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->MixerMode, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id,
__func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if ((MixerSettingsPtr->CoarseMixFreq != XRFDC_COARSE_MIX_OFF) &&
(MixerSettingsPtr->CoarseMixFreq != XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO) &&
(MixerSettingsPtr->CoarseMixFreq != XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR) &&
(MixerSettingsPtr->CoarseMixFreq != XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR) &&
(MixerSettingsPtr->CoarseMixFreq != XRFDC_COARSE_MIX_BYPASS)) {
metal_log(METAL_LOG_ERROR, "\n Invalid coarse mix frequency value (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->CoarseMixFreq, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id,
__func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
if (MixerSettingsPtr->FineMixerScale > XRFDC_MIXER_SCALE_0P7) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid Mixer Scale (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->PhaseOffset, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id,
__func__);
goto RETURN_PATH;
}
if (((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_R2C) && (Type == XRFDC_DAC_TILE)) ||
((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2R) && (Type == XRFDC_ADC_TILE))) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid Mixer mode (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->MixerMode, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id,
__func__);
goto RETURN_PATH;
}
if ((MixerSettingsPtr->MixerType != XRFDC_MIXER_TYPE_FINE) &&
(MixerSettingsPtr->MixerType != XRFDC_MIXER_TYPE_COARSE) &&
(MixerSettingsPtr->MixerType != XRFDC_MIXER_TYPE_OFF)) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid Mixer Type (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->MixerType, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id,
__func__);
goto RETURN_PATH;
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE) &&
((MixerSettingsPtr->EventSource == XRFDC_EVNT_SRC_SLICE) ||
(MixerSettingsPtr->EventSource == XRFDC_EVNT_SRC_IMMEDIATE))) {
Status = XRFDC_FAILURE;
metal_log(
METAL_LOG_ERROR,
"\n Invalid Event Source (%u), event source is not supported in 4GSPS ADC for ADC %u block %u in %s\r\n",
MixerSettingsPtr->EventSource, Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if (((MixerSettingsPtr->MixerType == XRFDC_MIXER_TYPE_COARSE) &&
(MixerSettingsPtr->CoarseMixFreq == XRFDC_COARSE_MIX_OFF)) ||
((MixerSettingsPtr->MixerType == XRFDC_MIXER_TYPE_FINE) &&
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_OFF))) {
Status = XRFDC_FAILURE;
metal_log(
METAL_LOG_ERROR,
"\n Invalid Combination of Mixer type (%u) Mixer mode (%u)/Coarse Mix Frequency (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->MixerType, MixerSettingsPtr->MixerMode, MixerSettingsPtr->CoarseMixFreq,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((MixerSettingsPtr->MixerType == XRFDC_MIXER_TYPE_COARSE) &&
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_OFF)) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR,
"\n Invalid Combination of Mixer type (%u) and Mixer mode (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->MixerType, MixerSettingsPtr->MixerMode,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((MixerSettingsPtr->MixerType == XRFDC_MIXER_TYPE_FINE) &&
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_R2R)) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR,
"\n Invalid Combination of Mixer type (%u) and Mixer mode (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->MixerType, MixerSettingsPtr->MixerMode,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((MixerSettingsPtr->MixerType == XRFDC_MIXER_TYPE_COARSE) &&
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_R2R) &&
(MixerSettingsPtr->CoarseMixFreq != XRFDC_COARSE_MIX_BYPASS)) {
Status = XRFDC_FAILURE;
metal_log(
METAL_LOG_ERROR,
"\n Invalid Combination of Mixer type (%u) and Mixer mode (%u) (non-bypass) for %s %u block %u in %s\r\n",
MixerSettingsPtr->MixerType, MixerSettingsPtr->MixerMode,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
if ((MixerSettingsPtr->MixerType == XRFDC_MIXER_TYPE_OFF) &&
(MixerSettingsPtr->MixerMode != XRFDC_MIXER_MODE_OFF)) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR,
"\n Invalid Combination of Mixer type (%u) and Mixer mode (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->MixerType, MixerSettingsPtr->MixerMode,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
goto RETURN_PATH;
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
* Static API used to turn off Fine & Coarse Mixers.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddr is ADC or DAC base address.
*
* @return
* - None
*
* @note Static API
*
******************************************************************************/
static void XRFdc_MixersOff(XRFdc *InstancePtr, u32 BaseAddr)
{
/* Coarse Mixer is OFF */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET, XRFDC_MIX_CFG0_MASK, XRFDC_CRSE_MIX_OFF);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET, XRFDC_MIX_CFG1_MASK, XRFDC_CRSE_MIX_OFF);
/* Fine mixer mode is OFF */
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET, XRFDC_MIXER_MODE_OFF);
}
/*****************************************************************************/
/**
* Static API used to set the Fine Mixer.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param BaseAddr is ADC or DAC base address.
* @param MixerSettingsPtr Pointer to the XRFdc_Mixer_Settings structure
* in which the Mixer/NCO settings are passed.
*
* @return
* - None
*
* @note Static API
*
******************************************************************************/
static void XRFdc_SetFineMixer(XRFdc *InstancePtr, u32 BaseAddr, XRFdc_Mixer_Settings *MixerSettingsPtr)
{
if (MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2C) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET,
(XRFDC_SEL_I_IQ_MASK | XRFDC_SEL_Q_IQ_MASK | XRFDC_EN_I_IQ_MASK | XRFDC_EN_Q_IQ_MASK),
(XRFDC_EN_I_IQ_MASK | XRFDC_EN_Q_IQ_MASK | XRFDC_I_IQ_COS_MINSIN | XRFDC_Q_IQ_SIN_COS));
} else if (MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2R) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET,
(XRFDC_EN_I_IQ_MASK | XRFDC_SEL_I_IQ_MASK | XRFDC_EN_Q_IQ_MASK),
(XRFDC_EN_I_IQ_MASK | XRFDC_I_IQ_COS_MINSIN));
} else if (MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_R2C) {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET,
(XRFDC_EN_I_IQ_MASK | XRFDC_EN_Q_IQ_MASK | XRFDC_SEL_I_IQ_MASK | XRFDC_SEL_Q_IQ_MASK |
XRFDC_FINE_MIX_SCALE_MASK),
(XRFDC_EN_I_IQ | XRFDC_EN_Q_IQ | XRFDC_I_IQ_COS_MINSIN | XRFDC_Q_IQ_SIN_COS |
XRFDC_FINE_MIX_SCALE_MASK));
} else {
/* Fine mixer mode is OFF */
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET, XRFDC_MIXER_MODE_OFF);
}
/* Coarse Mixer is OFF */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET, XRFDC_MIX_CFG0_MASK, XRFDC_CRSE_MIX_OFF);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET, XRFDC_MIX_CFG1_MASK, XRFDC_CRSE_MIX_OFF);
}
/*****************************************************************************/
/**
* Static API used to set the Coarse Mixer.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param BaseAddr is ADC or DAC base address.
* @param Block_Id is ADC/DAC block number inside the tile.
* @param CoarseMixFreq is ADC or DAC Coarse mixer frequency.
* @param MixerSettingsPtr Pointer to the XRFdc_Mixer_Settings structure
* in which the Mixer/NCO settings are passed.
*
* @return
* - None
*
* @note Static API
*
******************************************************************************/
static void XRFdc_SetCoarseMixer(XRFdc *InstancePtr, u32 Type, u32 BaseAddr, u32 Tile_Id, u32 Block_Id,
u32 CoarseMixFreq, XRFdc_Mixer_Settings *MixerSettingsPtr)
{
u16 ReadReg;
if (CoarseMixFreq == XRFDC_COARSE_MIX_BYPASS) {
/* Coarse Mix BYPASS */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET, XRFDC_MIX_CFG0_MASK,
XRFDC_CRSE_MIX_BYPASS);
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET);
ReadReg &= ~XRFDC_MIX_CFG1_MASK;
if ((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2C) ||
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2R)) {
ReadReg |= XRFDC_CRSE_MIX_BYPASS;
} else {
ReadReg |= XRFDC_CRSE_MIX_OFF;
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET, (u16)ReadReg);
} else if (CoarseMixFreq == XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO) {
/* Coarse Mix freq Fs/2 */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET);
ReadReg &= ~XRFDC_MIX_CFG0_MASK;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
ReadReg |= XRFDC_CRSE_MIX_I_Q_FSBYTWO;
} else {
if ((Block_Id % 2U) == 0U) {
ReadReg |= XRFDC_CRSE_MIX_BYPASS;
} else {
ReadReg |= XRFDC_CRSE_4GSPS_ODD_FSBYTWO;
}
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET, (u16)ReadReg);
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET);
ReadReg &= ~XRFDC_MIX_CFG1_MASK;
if ((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2C) ||
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2R)) {
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
ReadReg |= XRFDC_CRSE_MIX_I_Q_FSBYTWO;
} else {
ReadReg |=
((Block_Id % 2U) == 0U) ? XRFDC_CRSE_MIX_BYPASS : XRFDC_CRSE_4GSPS_ODD_FSBYTWO;
}
} else {
ReadReg |= XRFDC_CRSE_MIX_OFF;
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET, (u16)ReadReg);
} else if (CoarseMixFreq == XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR) {
/* Coarse Mix freq Fs/4 */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET);
ReadReg &= ~XRFDC_MIX_CFG0_MASK;
if ((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2C) ||
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2R)) {
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
ReadReg |= XRFDC_CRSE_MIX_I_FSBYFOUR;
} else {
ReadReg |= ((Block_Id % 2U) == 0U) ? XRFDC_CRSE_MIX_I_Q_FSBYTWO :
XRFDC_CRSE_MIX_I_ODD_FSBYFOUR;
}
} else {
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
ReadReg |= XRFDC_CRSE_MIX_R_I_FSBYFOUR;
} else {
ReadReg |= ((Block_Id % 2U) == 0U) ? XRFDC_CRSE_MIX_I_Q_FSBYTWO : XRFDC_CRSE_MIX_OFF;
}
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET, (u16)ReadReg);
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET);
ReadReg &= ~XRFDC_MIX_CFG1_MASK;
if ((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2C) ||
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2R)) {
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
ReadReg |= XRFDC_CRSE_MIX_Q_FSBYFOUR;
} else {
ReadReg |= ((Block_Id % 2U) == 0U) ? XRFDC_CRSE_MIX_I_Q_FSBYTWO :
XRFDC_CRSE_MIX_Q_ODD_FSBYFOUR;
}
} else {
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
ReadReg |= XRFDC_CRSE_MIX_R_Q_FSBYFOUR;
} else {
ReadReg |= ((Block_Id % 2U) == 0U) ? XRFDC_CRSE_MIX_OFF : XRFDC_CRSE_MIX_Q_ODD_FSBYFOUR;
}
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET, (u16)ReadReg);
} else if (CoarseMixFreq == XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR) {
/* Coarse Mix freq -Fs/4 */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET);
ReadReg &= ~XRFDC_MIX_CFG0_MASK;
if ((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2C) ||
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2R)) {
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
ReadReg |= XRFDC_CRSE_MIX_I_MINFSBYFOUR;
} else {
ReadReg |= ((Block_Id % 2U) == 0U) ? XRFDC_CRSE_MIX_I_Q_FSBYTWO :
XRFDC_CRSE_MIX_Q_ODD_FSBYFOUR;
}
} else {
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
ReadReg |= XRFDC_CRSE_MIX_R_I_MINFSBYFOUR;
} else {
ReadReg |= ((Block_Id % 2U) == 0U) ? XRFDC_CRSE_MIX_I_Q_FSBYTWO : XRFDC_CRSE_MIX_OFF;
}
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET, (u16)ReadReg);
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET);
ReadReg &= ~XRFDC_MIX_CFG1_MASK;
if ((MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2C) ||
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_C2R)) {
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
ReadReg |= XRFDC_CRSE_MIX_Q_MINFSBYFOUR;
} else {
ReadReg |= ((Block_Id % 2U) == 0U) ? XRFDC_CRSE_MIX_I_Q_FSBYTWO :
XRFDC_CRSE_MIX_I_ODD_FSBYFOUR;
}
} else {
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
ReadReg |= XRFDC_CRSE_MIX_R_Q_MINFSBYFOUR;
} else {
ReadReg |= ((Block_Id % 2U) == 0U) ? XRFDC_CRSE_MIX_OFF : XRFDC_CRSE_MIX_I_ODD_FSBYFOUR;
}
}
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET, (u16)ReadReg);
} else if (CoarseMixFreq == XRFDC_COARSE_MIX_OFF) {
/* Coarse Mix OFF */
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET, XRFDC_MIX_CFG0_MASK,
XRFDC_CRSE_MIX_OFF);
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET, XRFDC_MIX_CFG1_MASK,
XRFDC_CRSE_MIX_OFF);
} else {
metal_log(METAL_LOG_ERROR, "\n Invalid Coarse Mixer frequency (%u) for %s %u block %u in %s\r\n",
MixerSettingsPtr->CoarseMixFreq, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id,
__func__);
}
/* Fine mixer mode is OFF */
XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET, XRFDC_MIXER_MODE_OFF);
}
/*****************************************************************************/
/**
*
* The API returns back Mixer/NCO settings to the caller.
*
* @param InstancePtr is a pointer to the XRfdc instance.
* @param Type is ADC or DAC. 0 for ADC and 1 for DAC
* @param Tile_Id Valid values are 0-3.
* @param Block_Id is ADC/DAC block number inside the tile. Valid values
* are 0-3.
* @param MixerSettingsPtr Pointer to the XRFdc_Mixer_Settings structure
* in which the Mixer/NCO settings are passed.
*
* @return
* - XRFDC_SUCCESS if successful.
* - XRFDC_FAILURE if error occurs.
*
* @note FineMixerScale in Mixer_Settings structure can have 3 values.
* XRFDC_MIXER_SCALE_* represents the valid values.
* XRFDC_MIXER_SCALE_AUTO - If mixer mode is R2C, Mixer Scale is
* set to 1 and for other modes mixer scale is set to 0.7
* XRFDC_MIXER_SCALE_1P0 - To set fine mixer scale to 1.
* XRFDC_MIXER_SCALE_0P7 - To set fine mixer scale to 0.7.
*
******************************************************************************/
u32 XRFdc_GetMixerSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
XRFdc_Mixer_Settings *MixerSettingsPtr)
{
u32 Status;
u32 BaseAddr;
u64 ReadReg;
u64 ReadReg_Mix1;
double SamplingRate;
s64 Freq;
s32 PhaseOffset;
u32 Block;
u8 CalibrationMode = 0U;
XRFdc_Mixer_Settings *MixerConfigPtr;
u32 NyquistZone = 0U;
double NCOFreq;
u32 FineMixerMode;
u32 CoarseMixerMode = 0x0;
u32 BWDiv = XRFDC_FULL_BW_DIVISOR;
u32 DatapathMode;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(MixerSettingsPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
Status = XRFdc_CheckDigitalPathEnabled(InstancePtr, Type, Tile_Id, Block_Id);
if (Status != XRFDC_SUCCESS) {
goto RETURN_PATH;
}
Block = Block_Id;
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 1) && (Type == XRFDC_ADC_TILE)) {
if (Block_Id == XRFDC_BLK_ID1) {
Block_Id = XRFDC_BLK_ID3;
}
if (Block_Id == XRFDC_BLK_ID0) {
Block_Id = XRFDC_BLK_ID1;
}
}
if (InstancePtr->RFdc_Config.IPType >= XRFDC_GEN3) {
if (Type == XRFDC_DAC_TILE) {
DatapathMode = XRFdc_RDReg(InstancePtr, XRFDC_BLOCK_BASE(XRFDC_DAC_TILE, Tile_Id, Block_Id),
XRFDC_DAC_DATAPATH_OFFSET, XRFDC_DATAPATH_MODE_MASK);
switch (DatapathMode) {
case XRFDC_DAC_INT_MODE_FULL_BW_BYPASS:
metal_log(METAL_LOG_WARNING, "\n DAC %u DUC %u is in bypass mode in %s\r\n", Tile_Id,
Block_Id, __func__);
BWDiv = XRFDC_FULL_BW_DIVISOR;
break;
case XRFDC_DAC_INT_MODE_HALF_BW_IMR:
BWDiv = XRFDC_HALF_BW_DIVISOR;
break;
case XRFDC_DAC_INT_MODE_FULL_BW:
default:
BWDiv = XRFDC_FULL_BW_DIVISOR;
break;
}
}
}
if (Type == XRFDC_ADC_TILE) {
/* ADC */
SamplingRate = InstancePtr->ADC_Tile[Tile_Id].PLL_Settings.SampleRate;
MixerConfigPtr = &InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].Mixer_Settings;
} else {
/* DAC */
SamplingRate = InstancePtr->DAC_Tile[Tile_Id].PLL_Settings.SampleRate / BWDiv;
MixerConfigPtr = &InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].Mixer_Settings;
}
if (SamplingRate <= 0) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Incorrect Sampling rate (%2.4f GHz) for %s %u in %s\r\n", SamplingRate,
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
goto RETURN_PATH;
}
BaseAddr = XRFDC_BLOCK_BASE(Type, Tile_Id, Block_Id);
SamplingRate *= XRFDC_MILLI;
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG0_OFFSET, XRFDC_MIX_CFG0_MASK);
ReadReg_Mix1 = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_ADC_MXR_CFG1_OFFSET, XRFDC_MIX_CFG1_MASK);
MixerSettingsPtr->CoarseMixFreq = 0x20;
/* Identify CoarseMixFreq and CoarseMixerMode */
if (ReadReg == XRFDC_CRSE_MIX_BYPASS) {
if (ReadReg_Mix1 == XRFDC_CRSE_MIX_BYPASS) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_BYPASS;
CoarseMixerMode = XRFDC_MIXER_MODE_C2C;
} else if (ReadReg_Mix1 == XRFDC_CRSE_MIX_OFF) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_BYPASS;
CoarseMixerMode = XRFDC_MIXER_MODE_R2R;
if (MixerConfigPtr->MixerMode == XRFDC_MIXER_MODE_R2C) {
CoarseMixerMode = XRFDC_MIXER_MODE_R2C;
}
}
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
if ((ReadReg_Mix1 == XRFDC_CRSE_MIX_I_Q_FSBYTWO) && (ReadReg == XRFDC_CRSE_MIX_I_Q_FSBYTWO)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO;
CoarseMixerMode = XRFDC_MIXER_MODE_C2C;
} else if ((ReadReg_Mix1 == XRFDC_CRSE_MIX_OFF) && (ReadReg == XRFDC_CRSE_MIX_I_Q_FSBYTWO)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO;
CoarseMixerMode = XRFDC_MIXER_MODE_R2C;
}
} else {
if (ReadReg == XRFDC_CRSE_4GSPS_ODD_FSBYTWO) {
if (ReadReg_Mix1 == XRFDC_CRSE_4GSPS_ODD_FSBYTWO) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO;
CoarseMixerMode = XRFDC_MIXER_MODE_C2C;
} else if (ReadReg_Mix1 == XRFDC_CRSE_MIX_OFF) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO;
CoarseMixerMode = XRFDC_MIXER_MODE_R2C;
}
}
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
if ((ReadReg_Mix1 == XRFDC_CRSE_MIX_Q_FSBYFOUR) && (ReadReg == XRFDC_CRSE_MIX_I_FSBYFOUR)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR;
CoarseMixerMode = XRFDC_MIXER_MODE_C2C;
} else if ((ReadReg_Mix1 == XRFDC_CRSE_MIX_R_Q_FSBYFOUR) &&
(ReadReg == XRFDC_CRSE_MIX_R_I_MINFSBYFOUR)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR;
CoarseMixerMode = XRFDC_MIXER_MODE_R2C;
}
} else {
if ((ReadReg == XRFDC_CRSE_MIX_I_ODD_FSBYFOUR) && (ReadReg_Mix1 == XRFDC_CRSE_MIX_Q_ODD_FSBYFOUR)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR;
CoarseMixerMode = XRFDC_MIXER_MODE_C2C;
} else if ((ReadReg == XRFDC_CRSE_MIX_OFF) && (ReadReg_Mix1 == XRFDC_CRSE_MIX_Q_ODD_FSBYFOUR)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR;
CoarseMixerMode = XRFDC_MIXER_MODE_R2C;
}
}
if ((XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id) == 0) || (Type == XRFDC_DAC_TILE)) {
if ((ReadReg_Mix1 == XRFDC_CRSE_MIX_I_FSBYFOUR) && (ReadReg == XRFDC_CRSE_MIX_Q_FSBYFOUR)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR;
CoarseMixerMode = XRFDC_MIXER_MODE_C2C;
} else if ((ReadReg_Mix1 == XRFDC_CRSE_MIX_R_Q_MINFSBYFOUR) &&
(ReadReg == XRFDC_CRSE_MIX_R_I_MINFSBYFOUR)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR;
CoarseMixerMode = XRFDC_MIXER_MODE_R2C;
}
} else {
if ((ReadReg == XRFDC_CRSE_MIX_Q_ODD_FSBYFOUR) && (ReadReg_Mix1 == XRFDC_CRSE_MIX_I_ODD_FSBYFOUR)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR;
CoarseMixerMode = XRFDC_MIXER_MODE_C2C;
} else if ((ReadReg == XRFDC_CRSE_MIX_OFF) && (ReadReg_Mix1 == XRFDC_CRSE_MIX_I_ODD_FSBYFOUR)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR;
CoarseMixerMode = XRFDC_MIXER_MODE_R2C;
}
}
if ((ReadReg == XRFDC_CRSE_MIX_OFF) && (ReadReg_Mix1 == XRFDC_CRSE_MIX_OFF)) {
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_OFF;
CoarseMixerMode = XRFDC_MIXER_MODE_C2C;
}
if (MixerSettingsPtr->CoarseMixFreq == 0x20U) {
metal_log(METAL_LOG_ERROR,
"\n Coarse mixer settings not match any of the modes for %s %u block %u in %s\r\n",
(Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id, __func__);
}
if ((MixerConfigPtr->MixerMode == XRFDC_MIXER_MODE_C2R) && (CoarseMixerMode == XRFDC_MIXER_MODE_C2C)) {
CoarseMixerMode = XRFDC_MIXER_MODE_C2R;
}
/* Identify FineMixerMode */
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET, (XRFDC_EN_I_IQ_MASK | XRFDC_EN_Q_IQ_MASK));
if (ReadReg == 0xFU) {
FineMixerMode = XRFDC_MIXER_MODE_C2C;
} else if (ReadReg == 0x3U) {
FineMixerMode = XRFDC_MIXER_MODE_C2R;
} else if (ReadReg == 0x5U) {
FineMixerMode = XRFDC_MIXER_MODE_R2C;
} else {
FineMixerMode = XRFDC_MIXER_MODE_OFF;
}
if (FineMixerMode != XRFDC_MIXER_MODE_OFF) {
MixerSettingsPtr->MixerType = XRFDC_MIXER_TYPE_FINE;
MixerSettingsPtr->MixerMode = FineMixerMode;
} else if (MixerSettingsPtr->CoarseMixFreq != XRFDC_COARSE_MIX_OFF) {
MixerSettingsPtr->MixerType = XRFDC_MIXER_TYPE_COARSE;
MixerSettingsPtr->MixerMode = CoarseMixerMode;
} else {
MixerSettingsPtr->MixerType = XRFDC_MIXER_TYPE_OFF;
MixerSettingsPtr->MixerMode = XRFDC_MIXER_MODE_OFF;
}
/* Identify Fine Mixer Scale */
ReadReg = XRFdc_RDReg(InstancePtr, BaseAddr, XRFDC_MXR_MODE_OFFSET, XRFDC_FINE_MIX_SCALE_MASK);
if (InstancePtr->UpdateMixerScale == 0x0U) {
MixerSettingsPtr->FineMixerScale = XRFDC_MIXER_SCALE_AUTO;
} else if ((ReadReg != 0U) && (InstancePtr->UpdateMixerScale == 0x1U)) {
MixerSettingsPtr->FineMixerScale = XRFDC_MIXER_SCALE_1P0;
} else if (InstancePtr->UpdateMixerScale == 0x1U) {
MixerSettingsPtr->FineMixerScale = XRFDC_MIXER_SCALE_0P7;
} else {
metal_log(METAL_LOG_ERROR, "\n Invalid Fine mixer scale in (%u) for %s %u block %u in %s\r\n",
InstancePtr->UpdateMixerScale, (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, Block_Id,
__func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}
/* Phase Offset */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_NCO_PHASE_UPP_OFFSET);
PhaseOffset = ReadReg << XRFDC_NCO_PHASE_UPP_SHIFT;
PhaseOffset |= XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_NCO_PHASE_LOW_OFFSET);
PhaseOffset &= XRFDC_NCO_PHASE_MASK;
PhaseOffset = ((PhaseOffset << 14) >> 14);
MixerSettingsPtr->PhaseOffset = ((PhaseOffset * 180.0) / XRFDC_NCO_PHASE_MULTIPLIER);
/* NCO Frequency */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_NCO_FQWD_UPP_OFFSET);
Freq = ReadReg << XRFDC_NCO_FQWD_UPP_SHIFT;
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_NCO_FQWD_MID_OFFSET);
Freq |= ReadReg << XRFDC_NCO_FQWD_MID_SHIFT;
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_ADC_NCO_FQWD_LOW_OFFSET);
Freq |= ReadReg;
Freq &= XRFDC_NCO_FQWD_MASK;
Freq = (Freq << 16) >> 16;
MixerSettingsPtr->Freq = ((Freq * SamplingRate) / XRFDC_NCO_FREQ_MULTIPLIER);
/* Event Source */
ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, XRFDC_NCO_UPDT_OFFSET);
MixerSettingsPtr->EventSource = ReadReg & XRFDC_NCO_UPDT_MODE_MASK;
/* Update NCO, CoarseMix freq based on calibration mode */
NCOFreq = MixerConfigPtr->Freq;
if (Type == XRFDC_ADC_TILE) {
Status = XRFdc_GetCalibrationMode(InstancePtr, Tile_Id, Block, &CalibrationMode);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if (CalibrationMode == XRFDC_CALIB_MODE1) {
switch (MixerSettingsPtr->CoarseMixFreq) {
case XRFDC_COARSE_MIX_BYPASS:
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO;
break;
case XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR:
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR;
break;
case XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO:
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_BYPASS;
MixerSettingsPtr->MixerMode =
(MixerSettingsPtr->MixerMode == XRFDC_MIXER_MODE_R2C) ?
XRFDC_MIXER_MODE_R2R :
XRFDC_MIXER_MODE_C2C;
break;
case XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR:
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR;
break;
default:
MixerSettingsPtr->CoarseMixFreq = XRFDC_COARSE_MIX_OFF;
break;
}
NCOFreq = (MixerConfigPtr->Freq - (SamplingRate / 2.0));
}
}
}
if ((NCOFreq > (SamplingRate / 2.0)) || (NCOFreq < -(SamplingRate / 2.0))) {
Status = XRFdc_GetNyquistZone(InstancePtr, Type, Tile_Id, Block, &NyquistZone);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}
if ((NyquistZone == XRFDC_EVEN_NYQUIST_ZONE) && (MixerSettingsPtr->Freq != 0)) {
MixerSettingsPtr->Freq *= -1;
}
do {
if (NCOFreq < -(SamplingRate / 2.0)) {
NCOFreq += SamplingRate;
MixerSettingsPtr->Freq -= SamplingRate;
}
if (NCOFreq > (SamplingRate / 2.0)) {
NCOFreq -= SamplingRate;
MixerSettingsPtr->Freq += SamplingRate;
}
} while ((NCOFreq > (SamplingRate / 2.0)) || (NCOFreq < -(SamplingRate / 2.0)));
}
if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
if ((Type == XRFDC_ADC_TILE) && (CalibrationMode == XRFDC_CALIB_MODE1)) {
MixerSettingsPtr->Freq += (SamplingRate / 2.0);
}
}
Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_power.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* Power nodes (power islands and power domains) related structures
* and functions
*********************************************************************/
#ifndef PM_POWER_H_
#define PM_POWER_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_common.h"
#include "pm_node.h"
#include "pm_master.h"
#include "xpfw_rom_interface.h"
typedef struct PmPowerClass PmPowerClass;
typedef struct PmSlaveTcm PmSlaveTcm;
/*********************************************************************
* Macros
********************************************************************/
/* States of power island/domain */
#define PM_PWR_STATE_OFF 0U
#define PM_PWR_STATE_ON 1U
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmPower - Structure for power related nodes
* Basically an abstraction of power islands and power domains.
* Not all power entities in the system have this struct. If a node
* has its own power, which does not depend to other nodes, its power
* is controlled within its transition actions. Otherwise, this power
* structure must exist.
* @node Node structure of this power entity
* @class If power node has derived structure this is the pointer the class
* @children Pointer to the array of children
* @powerUp Handler for powering up the node
* @powerDown Handler for powering down the node
* @pwrDnLatency Latency (in us) for transition to OFF state
* @pwrUpLatency Latency (in us) for transition to ON state
* @childCnt Number of childs in children array
* @forcePerms ORed masks of masters which are allowed to force power down this
* power node
* @useCount How many nodes currently use this power node
*/
typedef struct PmPower {
PmNode node;
PmPowerClass* const class;
PmNode** const children;
s32 (*const powerUp)(void);
s32 (*const powerDown)(void);
const u32 pwrDnLatency;
const u32 pwrUpLatency;
u32 forcePerms;
const u8 childCnt;
u8 useCount;
} PmPower;
/**
* PmPowerDomain - Structure for power domains (do not have power parent)
* @power Basic power structure
* @supplyCheckHook PMU-ROM hook to check power supply on power up
* @supplyCheckHookId PMU-ROM service ID for the supply check
*/
typedef struct PmPowerDomain {
PmPower power;
u32 (*const supplyCheckHook)(const XpbrServHndlr_t RomHandler);
enum xpbr_serv_ext_id supplyCheckHookId;
} PmPowerDomain;
/**
* PmPowerIslandRpu - Structure for RPU power island
* @power Basic power structure
* @deps ORed IDs of TCMs which currently depend on the island's state
*/
typedef struct PmPowerIslandRpu {
PmPower power;
u8 deps;
} PmPowerIslandRpu;
/**
* PmPowerClass - Power class to model properties of PmPower derived objects
* @construct Constructor for the power node, call only once on startup
* @forceDown Puts power node in the lowest power state
*/
typedef struct PmPowerClass {
void (*const construct)(PmPower* const power);
void (*const forceDown)(PmPower* const power);
} PmPowerClass;
/*********************************************************************
* Global data declarations
********************************************************************/
extern PmPower pmPowerIslandApu_g;
extern PmPowerIslandRpu pmPowerIslandRpu_g;
extern PmPowerDomain pmPowerDomainFpd_g;
extern PmPowerDomain pmPowerDomainLpd_g;
extern PmPowerDomain pmPowerDomainPld_g;
extern PmNodeClass pmNodeClassPower_g;
/*********************************************************************
* Function declarations
********************************************************************/
void PmPowerReleaseParent(PmNode* const node);
void PmPowerReleaseRpu(PmSlaveTcm* const tcm);
s32 PmPowerRequestRpu(PmSlaveTcm* const tcm);
s32 PmPowerRequestParent(PmNode* const node);
s32 PmPowerUpdateLatencyReq(const PmNode* const node);
void PmFpdSaveContext(void);
void PmFpdRestoreContext(void);
s32 PmPowerDown(PmPower* const power);
#ifdef __cplusplus
}
#endif
#endif /* PM_POWER_H_ */
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/ipipsu_v2_6/src/xipipsu.c
/******************************************************************************
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xipipsu.c
* @addtogroup ipipsu_v2_6
* @{
*
* This file contains the implementation of the interface functions for XIpiPsu
* driver. Refer to the header file xipipsu.h for more detailed information.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ----------------------------------------------
* 1.00 mjr 03/15/15 First Release
* 2.0 mjr 01/22/16 Fixed response buffer address
* calculation. CR# 932582.
* 2.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance
* 2.2 kvn 02/17/17 Add support for updating ConfigTable at run time
* 2.4 sd 07/11/18 Fix a doxygen reported warning
* 2.6 sd 04/02/20 Restructured the code for more readability and modularity
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xipipsu.h"
#include "xipipsu_hw.h"
/************************** Variable Definitions *****************************/
extern XIpiPsu_Config XIpiPsu_ConfigTable[XPAR_XIPIPSU_NUM_INSTANCES];
/****************************************************************************/
/**
* Initialize the Instance pointer based on a given Config Pointer
*
* @param InstancePtr is a pointer to the instance to be worked on
* @param CfgPtr is the device configuration structure containing required
* hardware build data
* @param EffectiveAddress is the base address of the device. If address
* translation is not utilized, this parameter can be passed in using
* CfgPtr->Config.BaseAddress to specify the physical base address.
* @return XST_SUCCESS if initialization was successful
* XST_FAILURE in case of failure
*
*/
XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
UINTPTR EffectiveAddress)
{
u32 Index;
/* Verify arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CfgPtr != NULL);
/* Set device base address and ID */
InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
InstancePtr->Config.BaseAddress = EffectiveAddress;
InstancePtr->Config.BitMask = CfgPtr->BitMask;
InstancePtr->Config.IntId = CfgPtr->IntId;
InstancePtr->Config.TargetCount = CfgPtr->TargetCount;
for (Index = 0U; Index < CfgPtr->TargetCount; Index++) {
InstancePtr->Config.TargetList[Index].Mask =
CfgPtr->TargetList[Index].Mask;
InstancePtr->Config.TargetList[Index].BufferIndex =
CfgPtr->TargetList[Index].BufferIndex;
}
/* Mark the component as Ready */
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return (XST_SUCCESS);
}
/**
* @brief Reset the given IPI register set.
* This function can be called to disable the IPIs from all
* the sources and clear any pending IPIs in status register
*
* @param InstancePtr is the pointer to current IPI instance
*
*/
void XIpiPsu_Reset(XIpiPsu *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/**************Disable***************/
XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_IDR_OFFSET,
XIPIPSU_ALL_MASK);
/**************Clear***************/
XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_ISR_OFFSET,
XIPIPSU_ALL_MASK);
}
/**
* @brief Trigger an IPI to a Destination CPU
*
* @param InstancePtr is the pointer to current IPI instance
* @param DestCpuMask is the Mask of the CPU to which IPI is to be triggered
*
*
* @return XST_SUCCESS if successful
* XST_FAILURE if an error occurred
*/
XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Trigger an IPI to the Target */
XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_TRIG_OFFSET,
DestCpuMask);
return XST_SUCCESS;
}
/**
* @brief Poll for an acknowledgement using Observation Register
*
* @param InstancePtr is the pointer to current IPI instance
* @param DestCpuMask is the Mask of the destination CPU from which ACK is expected
* @param TimeOutCount is the Count after which the routines returns failure
*
* @return XST_SUCCESS if successful
* XST_FAILURE if a timeout occurred
*/
XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
u32 TimeOutCount)
{
u32 Flag, PollCount;
XStatus Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
PollCount = 0U;
/* Poll the OBS register until the corresponding DestCpu bit is cleared */
do {
Flag = (XIpiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XIPIPSU_OBS_OFFSET)) & (DestCpuMask);
PollCount++;
/* Check if the IPI was Acknowledged by the Target or we Timed Out*/
} while ((0x00000000U != Flag) && (PollCount < TimeOutCount));
if (PollCount >= TimeOutCount) {
Status = XST_FAILURE;
} else {
Status = XST_SUCCESS;
}
return Status;
}
/**
* @brief Read an Incoming Message from a Source
*
* @param InstancePtr is the pointer to current IPI instance
* @param SrcCpuMask is the Device Mask for the CPU which has sent the message
* @param MsgPtr is the pointer to Buffer to which the read message needs to be stored
* @param MsgLength is the length of the buffer/message
* @param BufferType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
*
* @return XST_SUCCESS if successful
* XST_FAILURE if an error occurred
*/
XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
u32 MsgLength, u8 BufferType)
{
u32 *BufferPtr;
u32 Index;
XStatus Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(MsgPtr != NULL);
Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr, SrcCpuMask,
InstancePtr->Config.BitMask, BufferType);
if (BufferPtr != NULL) {
/* Copy the IPI Buffer contents into Users's Buffer*/
for (Index = 0U; Index < MsgLength; Index++) {
MsgPtr[Index] = BufferPtr[Index];
}
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
return Status;
}
/**
* @brief Send a Message to Destination
*
* @param InstancePtr is the pointer to current IPI instance
* @param DestCpuMask is the Device Mask for the destination CPU
* @param MsgPtr is the pointer to Buffer which contains the message to be sent
* @param MsgLength is the length of the buffer/message
* @param BufferType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
*
* @return XST_SUCCESS if successful
* XST_FAILURE if an error occurred
*/
XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
u32 MsgLength, u8 BufferType)
{
u32 *BufferPtr;
u32 Index;
XStatus Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(MsgPtr != NULL);
Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr,
InstancePtr->Config.BitMask, DestCpuMask, BufferType);
if (BufferPtr != NULL) {
/* Copy the Message to IPI Buffer */
for (Index = 0U; Index < MsgLength; Index++) {
BufferPtr[Index] = MsgPtr[Index];
}
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
return Status;
}
/*****************************************************************************/
/**
*
* Set up the device configuration based on the unique device ID. A table
* contains the configuration info for each device in the system.
*
* @param DeviceId contains the ID of the device to set up the
* configuration for.
* @param ConfigTblPtr is the device configuration structure containing required
* hardware build data
*
* @return A pointer to the device configuration for the specified
* device ID. See xipipsu.h for the definition of
* XIpiPsu_Config.
*
* @note This is for safety use case where in this function has to
* be called before CfgInitialize. So that driver will be
* initialized with the provided configuration. For non-safe
* use cases, this is not needed.
*
******************************************************************************/
void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr)
{
u32 Index;
Xil_AssertVoid(ConfigTblPtr != NULL);
for (Index = 0U; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) {
XIpiPsu_ConfigTable[Index].BaseAddress = ConfigTblPtr->BaseAddress;
XIpiPsu_ConfigTable[Index].BitMask = ConfigTblPtr->BitMask;
XIpiPsu_ConfigTable[Index].BufferIndex = ConfigTblPtr->BufferIndex;
XIpiPsu_ConfigTable[Index].IntId = ConfigTblPtr->IntId;
}
}
}
/** @} */
<file_sep>/python_drivers/time_sync.py
# -*- coding: utf-8 -*-
"""
Created on Wed Jul 1 10:46:08 2020
@author: tianlab01
"""
import math as Math
import socket
import pulse_gen
import time
import tdc_wrapper
import ssl
import os.path
from OpenSSL import crypto
import james_utils
import threading
import datetime
#Should bob log the received time bin encoded frames to a file?
BOB_FILE_DEBUG = 0
#Open a secure socket?
SECURE_MODE = 1
REL_NUM_PULSES = 15 #Use 10 pulses to do phase measurement
PERIOD_DIFF_THRESHOLD = 0.1
CLIENT = 0
SERVER = 1
SERVER_ACK = b'\x66'
SERVER_ACK_BYTE = 0x66
CLIENT_TIMEOUT = 30 #5 second timeout
SERVER_TIMEOUT = 30 #Long timeout for the server
TIMEOUT_LONG = 60
#Server commands
SERVER_RECEIVE_PULSE = 4
SERVER_SEND_PULSE = 5
SERVER_EXIT = 6
SERVER_PING = 7
SERVER_PHASE_MEAS = 8
SERVER_SET_BIN_SIZE = 9 # bin size in picoseconds
SERVER_SET_BIN_NUMBER = 10 #Must be a power of 2
SERVER_RECEIVE_PHOTON = 11
SERVER_CLOSE_CONNECTION = 12
SERVER_RECEIVE_STREAM = 13
#Stream variables
FEI_THRESHOLD = 5 #First encoded photon theshold, number of avg periods over which next pulse will be treated as the first encoded photon
INFER_TICK = 1 #Calculate the expected tick position every time we decode a photon
PERIOD_OVERRIDE = 0#Use the internal period instead of the measured period
#Bob's responses
TDC_SUCCESS = 8
#IP of the BOB
SERVER_IP = "127.0.0.1"
pem_path = 'C:\certs\certchain.pem'
key_path = 'C:\certs\private.key'
SSL_PATH = 'C:\certs'
FAIL_TIMESTAMP_NO_PHOTON = 99999999999999
FAIL_TIMESTAMP_BAD_RANGE = 99999999999998
FAIL_TIMESTAMP_NEG_OFFSET = 99999999999997
TIMESTAMP_BYTE_LEN = 20
class encoded_photon:
bin_size = 0 # in picoseconds
bin_number = 0
timestamp = 0
value = 0
valid = 0
def __init__(self, bin_size, bin_number, timestamp, value, valid):
self.bin_size = bin_size
self.bin_number = bin_number
self.timestamp = timestamp
self.value = value
self.valid = valid
class time_sync:
s = 0 #Socket for this class
sck_u = 0 #Unsecure version of the socket
server_ip = ""#IP which this machine will try to connect if it is in client mode
mode = CLIENT
board = 0
tdc= 0
port = 25566
time_diff = 0
path_len = 0
channel_send = 0
channel_receive = 0
t_a_r = 0
t_a_s = 0
t_b_r = 0
t_b_s = 0
socket_dead = 0
dummy_mode = 0
#Variables for current relative sync state
last_tick = 0
avg_period = 0
bin_size = 500
bin_number = 16
photons_received = []
period = 0#from client
shutdown_flag = 0
def __init__(self, COM_PORT, s_ip, m, tdc_obj):
#save the other parameters
self.server_ip = s_ip
self.mode = m
#initialize the socket
self.init_socket()
#Initialize the FPGA
if(m == CLIENT):
self.board = pulse_gen.pulse_gen(COM_PORT)
#initialize the tdc
self.tdc = tdc_obj
if(m == CLIENT):
print("Initialized time sync in CLIENT mode")
self.channel_send = james_utils.ALICE_CHANNEL_SEND
self.channel_receive = james_utils.ALICE_CHANNEL_RECEIVE
else:
print("Initialized time sync in SERVER mode")
self.channel_send = james_utils.BOB_CHANNEL_SEND
self.channel_receive = james_utils.BOB_CHANNEL_RECEIVE
return
#Sets up the secure socket for client and server modes
#Should only be called from inside this object, not by user
def init_socket(self):
if(SECURE_MODE):
print("Initializing socket in secure mode")
#Make sure we have an SSL key
self.check_key()
#SSL Stuff
context = ssl.SSLContext(ssl.PROTOCOL_TLS_SERVER)
context.load_cert_chain(pem_path, key_path)
#Open a secure socket
if(self.mode == CLIENT):
self.sck_u = socket.socket(socket.AF_INET, socket.SOCK_STREAM, 0)
#self.s = context.wrap_socket(self.sck_u, server_hostname=SERVER_IP)
#self.s = ssl.wrap_socket(self.sck_u, ca_certs=pem_path, cert_reqs=ssl.CERT_REQUIRED)
self.s = ssl.wrap_socket(self.sck_u, ca_certs=pem_path)
else:
self.sck_u = socket.socket(socket.AF_INET, socket.SOCK_STREAM, 0)
#self.s = context.wrap_socket(self.sck_u, server_side=True)
else:
print("Initializing socket in UNSECURE(!) mode")
self.sck_u = socket.socket()
self.s = self.sck_u
#Set the socket timeout if we're the client
if(self.mode == CLIENT):
self.s.settimeout(CLIENT_TIMEOUT)
#self.sck_u.settimeout(CLIENT_TIMEOUT)
else:
#Set the timeout to none if we're the server so that we always block on receiving bytes
#self.s.settimeout(SERVER_TIMEOUT)
self.sck_u.settimeout(SERVER_TIMEOUT)
return
#Connects Alice to Bob
#Should only be called from inside this object, not by user
def connect_to_server(self):
if(self.mode != CLIENT):
print("Error, cannot connect to server while in server mode")
return -1
print("Attempting to connect to server")
#Open a totally new socket every time
self.sck_u = socket.socket(socket.AF_INET, socket.SOCK_STREAM, 0)
self.s = ssl.wrap_socket(self.sck_u, ca_certs=pem_path)
self.s.settimeout(CLIENT_TIMEOUT)
#connect to the client
self.s.connect((self.server_ip, self.port))
time.sleep(0.1)
if(self.is_socket_alive(self.s)):
print("Error, failed to connect to server")
return -1
else:
print("Connected to server!")
if(SECURE_MODE):
if(self.s.version()):
print("SSL version: " + self.s.version())
else:
print("Warning, socket is NOT SECURE!")
return 0
#Disconnects Alice from Bob
#Should only be called from inside this object, not by user
def disconnect_from_server(self):
if(self.mode != CLIENT):
print("Error, cannot ping server while in server mode")
return -1
print("Closing connection to server")
self.s.send(bytearray([SERVER_CLOSE_CONNECTION]))
#self.s.send(bytearray([SERVER_EXIT]))
if(self.wait_ack(self.s)):
print("Error, no ACK received from server while closing connection")
if(SECURE_MODE):
self.s.shutdown(socket.SHUT_RDWR)
self.s.close()
#Returns socket object on successful connection
#Returns 0 otherwise
#Should only be called from inside this object, not by user
def wait_connection(self, sck):
if(self.mode == CLIENT):
print("Error, cannot call wait_connection in client mode!")
return 0
#Keep trying to connect
while(not self.shutdown_flag):
try:
#Once a client connects we'll be here
c, addr = sck.accept() # Establish connection with client.
print("Got a connection from " + addr[0])
if(SECURE_MODE):
try:
c_s = ssl.wrap_socket(c,
server_side=True,
certfile=pem_path,
keyfile=key_path,
ssl_version=ssl.PROTOCOL_TLS)
except:
print("Unknown error while performing TLS handshake, still waiting for client connection")
continue
else:
c_s = c
c_s.settimeout(SERVER_TIMEOUT)
return c_s
except socket.timeout:
#print("Waiting for client connection...")
aaa = 1
except:
print("Unknown error while waiting for client connection")
raise
return 0
#Checks if the SSL key exists and generates a new one if it does not
#Should only be called from inside this object, not by user
def check_key(self):
#If the key already exists
if(os.path.exists(key_path) and os.path.exists(pem_path)):
print("SSL Key found, skiping key generation...")
return
#Generate a key
print("No SSL key found, generating key...")
cert_gen()
return
#Checks the connection between Alice and Bob
#Should only be called from inside this object, not by user
def ping_server(self):
if(self.mode != CLIENT):
print("Error, cannot ping server while in server mode")
return -1
#Send the ping server command
self.s.send(bytearray([SERVER_PING]))
if(self.wait_ack(self.s)):
print("Error, bad ACK received from server while pinging")
return -1
#receive the timestamp
if(james_utils.receive_timestamp(self.s) != 1234567890):
print("Error, bad timestamp received from server while pinging")
return -1
else:
print("Server ping test success!")
return 0
#Starts the server's command handler
#Returns 0 on success
#must be called in server mode, should not be called by user
def start_server(self):
if(self.mode == CLIENT):
print("Error, start_server must be called with the object in server mode!")
return -1
#Start the user shutdown handlong thread
t = threading.Thread(target=self.user_quit, args=(1,))
t.start()
host = socket.gethostname() # Get local machine name
self.sck_u.bind((host, self.port))
#self.s.bind((host, self.port))
#Start listening for a connection
self.sck_u.listen(5)
#self.s.listen(5)
print("Waiting for connection from client...")
#Once a client connects we'll be here
c = self.wait_connection(self.sck_u)
if(c == 0):
print("Server exit while waiting for client")
return -1
print("Waiting for command from client...")
while(self.server_handle_command(c)):
if(self.is_socket_alive(c) or self.socket_dead):
self.socket_dead = 0
print("Client has closed connection, waiting for new connection...")
c = self.wait_connection(self.sck_u)
if(c == 0):
print("Closing server")
self.sck_u.close()
return -1
#print("Waiting for command from client...")
#else:
#print("Socket is alive, waiting for next command...")
print("Closing server...")
return 0
#Server side command handler, handles incomming commands from client
#Returns 0 on server exit
#Should not be called by user
def server_handle_command(self, sck):
#If the shutdown flag is active:
if(self.shutdown_flag):
#Close the socket and stop the server
sck.close()
self.sck_u.close()
return 0
#Receive one command byte from the client
client_cmd = james_utils.receive_bytes(sck, 1)
if(client_cmd == -1 or client_cmd == -2 or client_cmd == -3):
if(client_cmd == -1):
#print("Timed out waiting for command")
return 1
else:
#print("Client socket closed")
self.socket_dead = 1
return 1
if(client_cmd[0] == SERVER_SEND_PULSE):
sck.send(SERVER_ACK)
print("Command received: SERVER_SEND_PULSE")
self.pulse_bob_to_alice(sck)
return 1
elif(client_cmd[0] == SERVER_RECEIVE_PULSE):
sck.send(SERVER_ACK)
print("Command received: SERVER_RECEIVE_PULSE")
self.pulse_alice_to_bob(sck)
return 1
elif(client_cmd[0] == SERVER_CLOSE_CONNECTION):
sck.send(SERVER_ACK)
print("Command receved: SERVER_CLOSE_CONNECTION")
sck.close()
self.socket_dead = 1
return 1
elif(client_cmd[0] == SERVER_EXIT):
sck.send(SERVER_ACK)
print("Command received: SERVER_EXIT")
sck.close()
self.sck_u.close()
return 0
elif(client_cmd[0] == SERVER_PING):
sck.send(SERVER_ACK)
print("Command received: SERVER_PING")
print("Sending timestamp 1234567890")
james_utils.send_timestamp(sck, 1234567890)
return 1
elif(client_cmd[0] == SERVER_PHASE_MEAS):
sck.send(SERVER_ACK)
print("Command received: SERVER_PHASE_MEAS")
if(self.bob_relative(sck)):
print("Relative time sync failed!")
return 1
elif(client_cmd[0] == SERVER_SET_BIN_SIZE):
print("Command received: SERVER_SET_BIN_SIZE")
self.bin_size = james_utils.receive_timestamp(sck)
if(self.bin_size == -1):
print("Failed to receive bin size from Alice!")
return 1
sck.send(SERVER_ACK)
print("Bin size set to " + str(self.bin_size))
return 1
elif(client_cmd[0] == SERVER_SET_BIN_NUMBER):
print("Command received: SERVER_SET_BIN_NUMBER")
self.bin_number = james_utils.receive_timestamp(sck)
if(self.bin_number == -1):
print("Failed to receive bin number from Alice!")
return 1
elif(not Math.log2(self.bin_number).is_integer()):
print("Error, Alice's bin number must be a multiple of 2, defaulting to 2")
self.bin_number = 2
else:
print("Bin number to " + str(self.bin_number))
sck.send(SERVER_ACK)
return 1
elif(client_cmd[0]== SERVER_RECEIVE_PHOTON):
print("Command received: SERVER_RECEIVE_PHOTON")
res = self.receive_encoded_photon(sck)
if(not isinstance(res, encoded_photon)):
print("Failed to receive photon")
self.photons_received.append(res)
return 1
elif(client_cmd[0] == SERVER_RECEIVE_STREAM):
print("Command received: SERVER_RECEIVE_STREAM")
sck.send(SERVER_ACK)
self.receive_stream(sck)
#self.shutdown_flag = 1
return 1
else:
print("Invalid command received: " + str(client_cmd[0]))
return 1
#CLIENT SIDE SYNC PROCEDURE
#Returns the time difference between server and client in picoseconds
#Returns -1 on error
#This function can be called by the user to do an absolute time synchronization
def start_client_sync(self):
self.connect_to_server()
if(self.mode == SERVER):
print("Error, start_time_sync must be called in client mode!")
return -1
#connect to the client
#self.s.connect((self.server_ip, self.port))
if(self.ping_server()):
print("Error communicating with server, unable to perform time synchronization")
self.disconnect_from_server()
return -1
print("Connected to server, performing time synchronization...")
if(self.do_sync(self.s) == -1):
print("Time sync failed!")
self.disconnect_from_server()
return -1
else:
print("Time sync success! time_diff = " + str(self.time_diff) + ", path_len = " + str(self.path_len))
self.disconnect_from_server()
return 0
#Checks the connection to the FPGA
#returns 0 on success
def check_board(self):
return self.board.ping_board()
#Waits to receive an ACK from the server
#Returns 0 on success
#Should not be called by user
def wait_ack(self, sck):
ack_res = james_utils.receive_bytes(self.s, 1)
return self.check_ack(ack_res)
#returns 0 on success
#Should not be called by user
def check_ack(self, ack_res):
if(isinstance(ack_res, int)):
print("Timed out waiting for ACK")
return -1
elif(ack_res[0] == SERVER_ACK_BYTE):
print("Received ACK!")
return 0
else:
print("Bad ACK received: " + hex(ack_res[0]) + ", was an invalid command sent to the server?")
return -1
#Returns 0 on success
#Internal function for absolute time synchronization
#Should not be called by user
def do_sync(self, sck):
ret_val = 0
if(self.board.ping_board()):
print("Error, unable to connect to FPGA board")
return -1
#If we're using the tdc server then clear all pulses before proceeding
self.tdc.clear_all()
#Set the period to something fast
self.board.set_period(10)
num_tries = 10
while(num_tries):
#Tell bob to receive a pulse
sck.send(bytearray([SERVER_RECEIVE_PULSE]))
if(self.wait_ack(sck)):
print("Error, no ACK received from server while telling it to receive a pulse")
return -1
#Send a pulse
if(self.pulse_alice_to_bob(sck)):
print("Sending pulse from Alice to Bob failed, retrying...")
num_tries -= 1
else:
print("Successfully sent pulse from Alice to Bob!")
break
if(num_tries == 0):
print("Ran out of tries while trying to send pulse from Alice to Bob!")
ret_val = -1
num_tries = 10
while(num_tries):
#Tell bob to receive a pulse
sck.send(bytearray([SERVER_SEND_PULSE]))
if(self.wait_ack(sck)):
print("Error, no ACK received from server while telling it to send a pulse")
return -1
#Send a pulse
if(self.pulse_bob_to_alice(sck)):
print("Sending pulse from Bob to Alice failed, retrying...")
num_tries -= 1
else:
print("Successfully sent pulse from Bob to Alice!")
break
if(num_tries == 0):
print("Ran out of tries while trying to send pulse from Bob to Alice!")
ret_val = -1
self.calc_path_len()
self.calc_time_diff()
return ret_val
#Returns 0 on success
#Sends a pulse from Alice to Bob, used for absolute sync
#Should not be called by user
def pulse_alice_to_bob(self, sck):
ret_val = 0
#If we are Alice
if(self.mode == CLIENT):
#Wait for a bit so bob's tdc is reay
#time.sleep(1)
#Start alice's tdc
if(self.tdc.start_record()):#If it fails to start
return -1
#Send a pulse
print("Sending pulse to Bob")
self.board.send_pulse(0,0)
#Wait for the TDC to pick up the pulse
#time.sleep(1)
#Stop our TDC and recover the timestamp
self.t_a_s = self.tdc.end_record(self.channel_send)
if(self.t_a_s < 1):
print("Error, Alice did not detect her own pulse on her TDC")
ret_val = -1
else:
print("Alice detected her own pulse! t_a_s = " + str(self.t_a_s))
#Receive the timestamp sent by bob
self.t_b_r = james_utils.receive_timestamp(sck)
if(self.t_b_r == 0):
print("Error, Bob did not detect Alice's pulse!")
ret_val = -1
else:
print("Bob detected Alice's pulse! t_b_r = " + str(self.t_b_r))
#Must be Bob (server)
else:
print("Waiting for pulse from Alice...")
self.t_b_r = self.tdc.wait_pulse(self.channel_receive)
if(self.t_b_r == 0):
print("Error, Bob did not receive a pulse from Alice!")
ret_val = -1
else:
print("Bob received Alice's pulse! t_b_r = " + str(self.t_b_r))
james_utils.send_timestamp(sck, self.t_b_r)
return ret_val
#Returns 0 on success
#Sends a pulse from Bob to Alice, used for abolute time sync
#Should not be called by user
def pulse_bob_to_alice(self, sck):
ret_val = 0
#If we are Bob
if(self.mode != CLIENT):
print("Sending pulse to Alice...")
#Wait for a bit so Alice's tdc is reay
#time.sleep(1)
#Start bob's tdc
if(self.tdc.start_record()):#If it fails to start
return -1
self.board.send_pulse(0,0)
#Wait for the TDC to pick up the pulse
#time.sleep(1)
#Stop our TDC and recover the timestamp
self.t_b_s = self.tdc.end_record(self.channel_send)
if(self.t_b_s < 1):
print("Error, Bob did not detect his own pulse!")
ret_val = -1
else:
print("Bob detected his own pulse! t_a_s = " + str(self.t_b_s))
#Send the timestamp to Alice
james_utils.send_timestamp(sck, self.t_b_s)
#Must be Alice
else:
print("Waiting for pulse from Bob...")
self.t_a_r = self.tdc.wait_pulse(self.channel_receive)
if(self.t_a_r == 0):
print("Error, Alice did not receive a pulse from Bob!")
ret_val = -1
else:
print("Alice received Bob's pulse! t_a_r = " + str(self.t_a_r))
self.t_b_s = james_utils.receive_timestamp(sck)
if(self.t_b_s < 1):
print("Error ,Bob did not detect his own pulse!")
ret_val = -1
else:
print("Bob detected his own pulse! t_b_s = " + str(self.t_b_s))
return ret_val
#Returns 0 if connection is active
#Should only be called by object, not by user
def is_socket_alive(self, sock):
if(SECURE_MODE):
#Cannot use this method to detect a dead socket in secure mode, must detect it when we go to read from it
return 0
# if(self.mode == CLIENT):
# return 0
# retval = 0
# self.sck_u.settimeout(0.01)
# try:
# #If this returns something that isn't None then we are connected
# if(len(self.sck_u.recv(16, socket.MSG_PEEK)) > 0):
# retval = 0
# else:
# retval = -1
# except socket.timeout:
# retval = 0
# self.sck_u.settimeout(SERVER_TIMEOUT)
# return retval
else:
sock.settimeout(0.01)
retval = 0
try:
# this will try to read bytes without blocking and also without removing them from buffer (peek only)
data = sock.recv(16, socket.MSG_PEEK)
#data = self.sck_u.recv(0)
if len(data) == 0:
retval = -1
except socket.timeout:
#Timeout indicates active connection
retval = 0
if(self.mode == CLIENT):
sock.settimeout(CLIENT_TIMEOUT)
else:
sock.settimeout(SERVER_TIMEOUT)
return retval
#Calculates path length based on arrival times
#Should only be called by object
def calc_path_len(self):
self.path_len = ((self.t_a_r - self.t_a_s) - (self.t_b_s - self.t_b_r)) / 2
#Calculates time difference based on arrival times
#Should only be called by object
def calc_time_diff(self):
self.time_diff = (self.t_b_r + self.t_b_s - self.t_a_r - self.t_a_s) / 2
#Helper function to allow bob to quit via console
#Should only be called by object
def user_quit(self, arg1):
#return
res = input()
print("[USER] Local user has stopped server")
self.shutdown_flag = 1
return
##############################################################
#Phase Measurement Routines for Relative Time Synchronization#
##############################################################
#Sets the protocol parameters for transmitting keys
#Should be called by user before doing key transmission
def set_protocol(self, bin_size, bin_number, period):
rv = self.set_bin_size(bin_size)
rv += self.set_bin_number(bin_number)
rv += self.set_period(period)
return
#Sets bin size for both Alice and Bob
#Returns 0 on success, val in picoseconds
#Should only be called by object
def set_bin_size(self, val):
if(val < 250 or val % 250 != 0):
print("Error, bin size must be a multiple of 250ps")
return -1
self.bin_size = val
if(self.connect_to_server()):
print("Failed to connect to server while setting bin size")
return -1
self.s.send(bytearray([SERVER_SET_BIN_SIZE]))
james_utils.send_timestamp(self.s, self.bin_size)
if(self.wait_ack(self.s)):
print("Bad ack receved from server while setting bin size")
self.disconnect_from_server()
return -1
self.disconnect_from_server()
return 0
#Sets bin number for both Alice and Bob
#Returns 0 on success
#Should only be called by object
def set_bin_number(self, num):
if(not Math.log2(num).is_integer()):
print("Error, bin number must be a multiple of 2")
return -1
self.bin_number = num
if(self.connect_to_server()):
print("Failed to connect to server while setting bin size")
return -1
self.s.send(bytearray([SERVER_SET_BIN_NUMBER]))
james_utils.send_timestamp(self.s, self.bin_number)
if(self.wait_ack(self.s)):
print("Bad ack receved from server while setting bin number")
self.disconnect_from_server()
return -1
self.disconnect_from_server()
return 0
#Sets period for both Alice and Bob
#Should only be called by object
#Val should be in picoseconds, returns 0 on success
def set_period(self, val):
if(val < self.bin_size * self.bin_number):
print("Error, period must be larger than bin_size * bin_number, try setting those values first")
return -1
if(self.board.set_period(val / 4000)):
print("Error setting bin size on board")
return -1
self.period = val
return 0
#Depreciated, do not use
def relative_time_sync(self):
#Must be called as alice
if(self.mode != CLIENT):
print("Error, relative_time_sync must be called as Alice")
return -1
if(self.connect_to_server()):
print("Error, could not connect to server (Bob)")
return -1
#Send the phase measurement command
self.s.send(bytearray([SERVER_PHASE_MEAS]))
#time.sleep(0.25)
if(self.wait_ack(self.s)):
print("Error, no ACK received from Bob while attempting relative synchronization")
return -1
self.tdc.clear_all()
#Otherwise just turn on phase measurement mode for a moment and leave
self.board.toggle_phase_meas(REL_NUM_PULSES)
self.s.send(bytearray([0x00]))
#time.sleep(5)
if(self.wait_ack(self.s)):
print("Relative time synch failed!")
self.disconnect_from_server()
return -1
self.disconnect_from_server()
return 0
#Bob's routine for synchronization
#Depreciated, do not use
def bob_relative(self, socket):
#wait until alice sends us an ack and then receive the pulses
ack = james_utils.receive_bytes(socket, 1)
if(isinstance(ack, int) or ack[0] != 0x00):
print("Bad responce received from Alice while attempting relative synchronization")
return -1
print("Waiting for pulses to be collected")
#Give the server a moment to finish collecting pulses
#time.sleep(0.5)
time_now = time.time()
pulses = []
while(time.time() < time_now + 5):
pulses = self.tdc.end_record(self.channel_receive, 1)
if(len(pulses) > 1):
break
if(len(pulses) < 1):
print("Error, did not receive any pulses from Alice during relative phase synchronization")
socket.send(bytearray([0xFF]))#Send a back ACK
return -1
#Calculate the difference between all of the pulses
diffs = []
for i in range(0, len(pulses) - 1):
diffs.append(pulses[i+1]-pulses[i])
#Throwous all of the differences that are greater than 1.5 times the smallest
diffs_final = []
for d in diffs:
if(d < min(diffs)*1.5):
diffs_final.append(d)
#Calculate the average and stdev and report
self.last_tick = pulses[len(pulses) - 1]
self.avg_period = round(sum(diffs_final)/len(diffs_final))
print("[RELATIVE SYNC] Pulses received: " + str(len(pulses)) + ", pulses rejected: " + str(len(diffs) - len(diffs_final)) + ", last tick: " + str(self.last_tick) + ", avg period: " + str(self.avg_period))
#Send an ack back to Alice indicating sucess
socket.send(SERVER_ACK)
return 0
#Depreciated, do not use
def send_encoded_photon(self, val):
if(self.mode != CLIENT):
print("Error, send_encoded_photon must be called in client mode")
return -1
if(self.connect_to_server()):
print("Error connecting to server (Bob)")
return -1
#tell bob to receive a photon
self.s.send(bytearray([SERVER_RECEIVE_PHOTON]))
#bin_size in picoseconds
#Divide by 250 to get num samples
offset = round((self.bin_size * val) + (self.bin_size * 0.5))# in picoseconds
if(offset >= self.bin_number * self.bin_size):
print("Value too lange, must be smaller than bin_num * bin_size")
#convert offset to number of samples
coarse_delay = offset / 4000
fine_delay = (offset / 250) % 16
if(self.board.send_pulse(coarse_delay, fine_delay)):
print("Error while sending encoded photon")
#Return the value sent back from bob
res = james_utils.receive_timestamp(self.s)
self.disconnect_from_server()
if(res == FAIL_TIMESTAMP_NO_PHOTON):
print("Error, bob did not receive encoded photon!")
return -1
elif(res == FAIL_TIMESTAMP_BAD_RANGE):
print("Error, Bob received the photon but it fell outside the allowable range!")
return res
#Depreciated, do not use
def receive_encoded_photon(self, sck):
if(self.mode != SERVER):
print("Error, send_encoded_photon must be called in server mode")
return -1
#Try to receive one photon
ts = self.tdc.wait_pulse(self.channel_receive)
if(ts == 0):
print("Error, no encoded photon received!")
james_utils.send_timestamp(sck, FAIL_TIMESTAMP_NO_PHOTON)
return -1
#Subtract out the last tick
ts_rel = ts - self.last_tick
#Determine the offset from the most recent dick
offset = ts_rel % self.avg_period
#If the offset falls outside of the time bin
if(offset > self.bin_number * self.bin_size):
print("Error, received a photon which falls outside of the allowable range, offset was " + str(offset) + ", allowable range was " + str(self.bin_number * self.bin_size))
print("TS was " + str(ts) + ", TS rel was " + str(ts_rel))
james_utils.send_timestamp(sck, FAIL_TIMESTAMP_BAD_RANGE)
return -1
#Otherwise determine the time bin and
final_val = Math.floor(float(offset) / float(self.bin_size))
print("Timestamp was " + str(ts) + ", relative timestamp was " + str(ts_rel) + ", offset was " + str(offset) + ", final value was " + str(final_val))
#Send the value back to alice
james_utils.send_timestamp(sck, final_val)
return encoded_photon(self.bin_size, self.bin_number, ts, final_val, 1)
#Sends a stream of encoded pulses from Alice to Bob
#Should be used by user to test encoded pulse transmission
#Returns -1 on fail
#Returns bob's decoded values on success
def send_stream(self, vals, num_sync_pulse, num_dead_pulse, pulse_len, pulse_amp, look_for_entangled_pair = 0):
if(self.mode != CLIENT):
print("Error, send_encoded_photon must be called in client mode")
return -1
if(self.connect_to_server()):
print("Error connecting to server (Bob)")
return -1
if(self.board.ping_board()):
print("Unable to communicate with FPGA, cannot send stream")
return -1
self.board.clear_queue()
self.board.set_pulse_len(pulse_len)
self.board.set_amplitude(pulse_amp)
#tell bob to receive a photon
self.s.send(bytearray([SERVER_RECEIVE_STREAM]))
if(self.wait_ack(self.s)):
print("Bad ack received from Bob while telling him to receive a stream of photons")
self.disconnect_from_server()
return -1
val_coarse = []
val_fine = []
for v in vals:
if(v > self.bin_number-1 or v < 0):
print("Bad value " + str(v) + ", too large, must be smaller than number of bins")
self.disconnect_from_server()
return -1
c, f = james_utils.val_to_coarse_fine(v, self.bin_size)
val_coarse.append(c)
val_fine.append(f)
#print("Val " + str(v) + " has coarse: " + str(c) + ", fine: " + str(f))
total_pulses = len(val_coarse) + num_sync_pulse
#Load the values to be sent
for i in range(0, len(val_coarse)):
self.board.load_pulse(val_coarse[i], val_fine[i])
self.tdc.clear_all()#Clear any old pulses
self.tdc.set_record(1)
time.sleep(0.1)
#Send the pulses
print("Sending pulses")
self.board.sync_and_stream(num_sync_pulse, num_dead_pulse)
#Tell bob the expected number of pulses
#wait_time = ((num_sync_pulse + len(vals) + num_dead_pulse) * self.period)/1000000000000
#print("Waiting " + str(wait_time) + " seconds")
#time.sleep(wait_time + 0.1)
print("Waiting for TDC to finish...")
#while(self.tdc.is_busy()):
# a = 1
while(self.board.get_busy()):
print("Board was busy")
expected_num_pulses = (num_sync_pulse + len(vals)) * 0.95
times_waited = 0
while(self.tdc.get_num_pulses() < (expected_num_pulses*3) and times_waited < 2):
print("Still waiting on TDC...")
time.sleep(0.5)
times_waited += 1
if(times_waited > 10):
print("Warning, timed out waiting for tdc to finish")
self.tdc.set_record(0)
print("Sending timing info to Bob")
#Send over the stream information
james_utils.send_timestamp(self.s, total_pulses)
james_utils.send_timestamp(self.s, num_sync_pulse)
james_utils.send_timestamp(self.s, num_dead_pulse)
james_utils.send_timestamp(self.s, self.period)
#Readout our encoded pulse list so
alice_entangled_pulse_timestamp = 0
if(look_for_entangled_pair == 1):
print("Receiving pulse list for entangled photon detection")
pulse_list = self.tdc.end_record(self.channel_receive,1)
if(len(pulse_list) < 5):
print("Failed to retreive pulses on Alices end, cannot accomplish absolute synchronization")
else:
decoded_vals, a, b, alice_entangled_pulse_timestamp = james_utils.decode_pulse_list(pulse_list, self.period, self.bin_number, self.bin_size, num_sync_pulse)
print("Waiting for Bob to finish")
#Set the socket timeout to something long
self.s.settimeout(TIMEOUT_LONG)
#Get the timestamp of the entangled pulse from Bob
entangled_pulse_timestamp = james_utils.receive_timestamp(self.s)
#Wait to get back the number of extracted values
bob_extracted_values_len = james_utils.receive_timestamp(self.s)
if(bob_extracted_values_len < 1):
print("Failed to receive extracted values from Bob")
self.disconnect_from_server()
return -1
self.s.settimeout(CLIENT_TIMEOUT)
bob_extracted_values = []
#Loop and receive all values
for i in range(0, bob_extracted_values_len):
bob_extracted_values.append(james_utils.receive_timestamp(self.s))
#For profiling purposes
#self.s.send(bytearray([SERVER_EXIT]))
print("Alice entangled timestamp was " + str(alice_entangled_pulse_timestamp) + ", Bob entangled timestmap was " + str(entangled_pulse_timestamp))
self.disconnect_from_server()
return bob_extracted_values, alice_entangled_pulse_timestamp, entangled_pulse_timestamp
#Receives a stream at Bob's end and decodes it
#Should only be called by object, not by user
def receive_stream(self, sck):
#TDC fires on Alice's side here
#Receive the expected number of pulses
print("Waiting to receive number of expected pulses from Alice")
sck.settimeout(TIMEOUT_LONG)
num_pulses = james_utils.receive_timestamp(sck)
num_sync_pulses = james_utils.receive_timestamp(sck)
num_dead_pulses = james_utils.receive_timestamp(sck)
self.period = james_utils.receive_timestamp(sck)
sck.settimeout(SERVER_TIMEOUT)
if(num_pulses < 5 ):
print("Error, number of expected pulses less than 5")
return -1
#Check our tdc
pulse_list = self.tdc.end_record(self.channel_receive,1)
#pulse_list = self.tdc.dump_all(self.channel_receive)
if(len(pulse_list) < 2):
print("Error, did not receive pulses!")
james_utils.send_timestamp(sck, 0)
return -1
print("Expected " + str(num_pulses) + ", got " + str(len(pulse_list)) + " pulses")
#decoded_vals = self.analyze_pulse_list(pulse_list, num_pulses, num_sync_pulses, num_dead_pulses)
decoded_vals, a, b, entangled_pulse_timestamp, d = james_utils.decode_pulse_list(pulse_list, self.period, self.bin_number, self.bin_size, num_sync_pulses)
print("Done decoding")
print("Got: ")
#res_str = "got: "
#for i in decoded_vals:
# if(i < 100):
# res_str += str(i) + ","
#print(res_str)
print(str(decoded_vals))
#Send the entangled pulse timestamp
james_utils.send_timestamp(sck, entangled_pulse_timestamp)
#Send the length of decoded vals and then each val
james_utils.send_timestamp(sck, len(decoded_vals))
for v in decoded_vals:
james_utils.send_timestamp(sck, v)
return 0 #We're done
#Does certificate generation for SSL socket
def cert_gen(
emailAddress="<EMAIL>",
commonName="cn",
countryName="CA",
localityName="SB",
stateOrProvinceName="Illinois",
organizationName="UC",
organizationUnitName="QC",
serialNumber=0,
validityStartInSeconds=0,
validityEndInSeconds=10*365*24*60*60,
KEY_FILE = key_path,
CERT_FILE =pem_path):
#can look at generated file using openssl:
#openssl x509 -inform pem -in selfsigned.crt -noout -text
# create a key pair
k = crypto.PKey()
k.generate_key(crypto.TYPE_RSA, 4096)
#Create the directory if it does not exist
if not os.path.exists(SSL_PATH):
os.makedirs(SSL_PATH)
# create a self-signed cert
cert = crypto.X509()
cert.get_subject().C = countryName
cert.get_subject().ST = stateOrProvinceName
cert.get_subject().L = localityName
cert.get_subject().O = organizationName
cert.get_subject().OU = organizationUnitName
cert.get_subject().CN = commonName
cert.get_subject().emailAddress = emailAddress
cert.set_serial_number(serialNumber)
cert.gmtime_adj_notBefore(0)
cert.gmtime_adj_notAfter(validityEndInSeconds)
cert.set_issuer(cert.get_subject())
cert.set_pubkey(k)
cert.sign(k, 'sha512')
with open(CERT_FILE, "wt+") as f:
f.write(crypto.dump_certificate(crypto.FILETYPE_PEM, cert).decode("utf-8"))
with open(KEY_FILE, "wt+") as f:
f.write(crypto.dump_privatekey(crypto.FILETYPE_PEM, k).decode("utf-8"))
# #depreciated, do not use
# def val_to_coarse_fine(self, val):
# offset = self.val_to_offset(val)
# c = Math.floor(offset / 4000)
# f = Math.floor((offset/250)%16)
# return c,f
# #Depreciated, do not use
# def val_to_offset(self, val):
# return (val * self.bin_size) + (0.5 * self.bin_size)
# #Depreciated, do not use
# def offset_to_val(self, offset):
# if(offset > self.bin_number * self.bin_size):
# print("Error, received photon outside of allowed range, should not happen here")
# return FAIL_TIMESTAMP_BAD_RANGE
# val = Math.floor(offset/self.bin_size)
# return val
# #Depreciated, do not use
# #-1 is did not detect, -2 is fell outsize allowable range
# def analyze_pulse_list(self, pulse_list, expected_num_pulses, num_sync_pulses, num_dead_pulses):
# #For profiling purposes
# #self.shutdown_flag = 1
# if(self.period < 5):
# print("Expected period too small, aborting decode")
# return []
# #Convert pulses to relative first
# p_offset = pulse_list[0]
# for i in range(0, len(pulse_list)):
# #print("Got pulse: " + str(pulse_list[i]))
# pulse_list[i] -= p_offset
# ##################################################
# ##Relative synchronization happening here
# diffs_pre = []
# max_diff = 0
# first_encoded_index = 0
# #Figure out the largest difference to find the first encoded photon
# for i in range(0, len(pulse_list)-1):
# d = pulse_list[i+1] - pulse_list[i]
# #If we find a larger difference
# if(d > max_diff):
# max_diff = d
# first_encoded_index = i+1#Record this index
# #Calculate the calibration differences
# for i in range(0, first_encoded_index - 1):
# diffs_pre.append(pulse_list[i+1] - pulse_list[i])
# diffs = []
# #Throw out any that are too large
# for i in range(0, len(diffs_pre)):
# if(diffs_pre[i] < min(diffs_pre) *1.5):
# diffs.append(diffs_pre[i])
# #Sanity check on diffs
# if(len(diffs) > num_sync_pulses):
# print("Error, too many sync pulses received, aborting decode")
# file = open("bob_pulse_analysis_log.txt",'a')
# file.write(datetime.datetime.now().strftime("\n================\n%I:%M%p on %B %d, %Y\nError, too many sync pulses received, aborting decode\n"))
# file.close()
# return []
# ####################################################
# #Start the time bin counter
# avg_period = sum(diffs) / len(diffs)
# #If the avg period is too far off
# if(abs((avg_period - self.period)/min(avg_period, self.period)) > PERIOD_DIFF_THRESHOLD):
# print("Average period too far outsize of allowable bounds, aborting")
# file = open("bob_pulse_analysis_log.txt",'a')
# file.write(datetime.datetime.now().strftime("\n================\n%I:%M%p on %B %d, %Y\nAverage period too far outsize of allowable bounds, aborting\n"))
# file.close()
# return []
# if(PERIOD_OVERRIDE):
# avg_period = self.period #Use this period for stability
# #If the time between the last sync pulse and first encoded pulse is too small
# if(pulse_list[first_encoded_index] - pulse_list[first_encoded_index-1] < self.period):
# print("Time between sync pulses and first encoded pulse was too short")
# file = open("bob_pulse_analysis_log.txt",'a')
# file.write(datetime.datetime.now().strftime("\n================\n%I:%M%p on %B %d, %Y\nTime between sync pulses and first encoded pulse was too short, aborting\n"))
# file.close()
# return []
# current_clock_tick = pulse_list[first_encoded_index - 1]
# decoded_vals = []
# offsets = []
# succ_vals = 0
# for j in range(first_encoded_index, len(pulse_list)):
# while(current_clock_tick < pulse_list[j] - avg_period):
# #If we're having to increment after the first pulse then we've missed one
# if(j != first_encoded_index):
# print("Detected missing pulse number " + str(j - first_encoded_index))
# decoded_vals.append(FAIL_TIMESTAMP_NO_PHOTON)
# offsets.append(FAIL_TIMESTAMP_NO_PHOTON)
# current_clock_tick += avg_period
# offset = pulse_list[j] - current_clock_tick
# offsets.append(offset)
# if(offset < 0):
# print("Fatal error, offset was less than 0!")
# decoded_vals.append(FAIL_TIMESTAMP_NEG_OFFSET)
# current_clock_tick += avg_period#Go to next pulse
# elif(INFER_TICK):
# #Figure out the offset we should have had
# val = self.offset_to_val(offset)
# decoded_vals.append(val)
# exact_offset = self.val_to_offset(val)
# if(val >= 0 and val < self.bin_number):#If the decode is valid
# succ_vals += 1
# current_clock_tick = pulse_list[j] - exact_offset + avg_period#nfer the last clock tick and update
# else:
# current_clock_tick += avg_period#Go to next pulse
# else:
# decoded_vals.append(self.offset_to_val(offset))
# succ_vals += 1
# current_clock_tick += avg_period#Go to next pulse
# print("[ANALYZE STREAM RESULTS] Sync pulses: " + str(first_encoded_index) + ", decoded pulses: " + str(succ_vals) + ", avg period: " + str(avg_period))
# dv_str = "Decoded values: "
# for d in decoded_vals:
# dv_str += str(d) + ", "
# #print(dv_str)
# #log to file
# if(BOB_FILE_DEBUG):
# file = open("bob_pulse_analysis_log.txt",'a')
# file.write(datetime.datetime.now().strftime("\n================\n%I:%M%p on %B %d, %Y\n"))
# file.write("Expected " + str(expected_num_pulses) + ", got " + str(len(pulse_list)) + " pulses, used " + str(len(diffs) + 1) + " pulses to calculate period")
# for p in pulse_list:
# file.write(str(p) + "\n")
# for i in range(0, len(offsets)):
# file.write("offset: " + str(offsets[i]) + ", became value " + str(decoded_vals[i]) + "\n")
# file.close()
# return decoded_vals
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_board.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_BOARD_H_
#define XPM_BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xparameters.h"
#include "xstatus.h"
#include "xil_types.h"
/************************** I2C Configurations *******************************/
#define IIC_DEVICE_ID 0
#define IIC_CLK_FREQ_HZ 100000000
#define IIC_SCLK_RATE 400000
#define IIC_BASE_ADDR PMC_I2C_ADDR
/************************** Address Definitions ******************************/
#define PMC_I2C_ADDR 0xF1000000U
#define I2C0_MUX_ADDR 0x74
#define PSFP_REGULATOR_ADDR 0x0A
#define PSLP_REGULATOR_ADDR 0x09
/************************ MUX Channel Definitions ****************************/
/***************** Channels 5-7 are currently not configured *****************/
#define MUX_SEL_CHANNEL_0 0x01
#define MUX_SEL_CHANNEL_1 0x02
#define MUX_SEL_CHANNEL_2 0x04
#define MUX_SEL_CHANNEL_3 0x08
#define MUX_SEL_CHANNEL_4 0x10
/************************** Variable Definitions *****************************/
enum power_rail_id {
POWER_RAIL_FPD,
POWER_RAIL_LPD,
};
enum power_rail_function {
RAIL_POWER_UP,
RAIL_POWER_DOWN,
};
/************************** Function Prototypes ******************************/
XStatus XPmBoard_ControlRail(const enum power_rail_function Function,
const enum power_rail_id PowerRegulatorId);
#ifdef __cplusplus
}
#endif
#endif /* XPM_BOARD_H_ */
<file_sep>/c_drivers/drivers/cmd_handler.h
#ifndef _CMD_HANDLER_H_
#define _CMD_HANDLER_H_
#include "xgpio.h"
u8 cmd_init();
void cmd_update_state();
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/csudma_v1_6/src/xcsudma_sinit.c
/******************************************************************************
* Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcsudma_sinit.c
* @addtogroup csudma_v1_6
* @{
*
* This file contains static initialization methods for Xilinx CSU_DMA core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------------
* 1.0 vnsld 22/10/14 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xcsudma.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* XCsuDma_LookupConfig returns a reference to an XCsuDma_Config structure
* based on the unique device id, <i>DeviceId</i>. The return value will refer
* to an entry in the device configuration table defined in the xcsudma_g.c
* file.
*
* @param DeviceId is the unique device ID of the device for the lookup
* operation.
*
* @return CfgPtr is a reference to a config record in the configuration
* table (in xcsudma_g.c) corresponding to <i>DeviceId</i>, or
* NULL if no match is found.
*
* @note None.
******************************************************************************/
XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId)
{
extern XCsuDma_Config XCsuDma_ConfigTable[XPAR_XCSUDMA_NUM_INSTANCES];
XCsuDma_Config *CfgPtr = NULL;
u32 Index;
/* Checks all the instances */
for (Index = (u32)0x0; Index < (u32)(XPAR_XCSUDMA_NUM_INSTANCES);
Index++) {
if (XCsuDma_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XCsuDma_ConfigTable[Index];
break;
}
}
return (XCsuDma_Config *)CfgPtr;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/axipmon_v6_8/src/xaxipmon_selftest.c
/******************************************************************************
* Copyright (C) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxipmon_selftest.c
* @addtogroup axipmon_v6_8
* @{
*
* This file contains a diagnostic self test function for the XAxiPmon driver.
* The self test function does a simple read/write test of the Alarm Threshold
* Register.
*
* See XAxiPmon.h for more information.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 02/24/12 First release
* 2.00a bss 06/23/12 Updated to support v2_00a version of IP.
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xaxipmon.h"
/************************** Constant Definitions ****************************/
/*
* The following constant defines the test value to be written
* to the Range Registers of Incrementers
*/
#define XAPM_TEST_RANGEUPPER_VALUE 16U /**< Test Value for Upper Range */
#define XAPM_TEST_RANGELOWER_VALUE 8U /**< Test Value for Lower Range */
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/*****************************************************************************/
/**
*
* Run a self-test on the driver/device. The test
* - Resets the device,
* - Writes a value into the Range Registers of Incrementer 0 and reads
* it back for comparison.
* - Resets the device again.
*
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return
* - XST_SUCCESS if the value read from the Range Register of
* Incrementer 0 is the same as the value written.
* - XST_FAILURE Otherwise
*
* @note This is a destructive test in that resets of the device are
* performed. Refer to the device specification for the
* device status after the reset operation.
*
******************************************************************************/
s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr)
{
s32 Status;
u16 RangeUpper = 0U;
u16 RangeLower = 0U;
/*
* Assert the argument
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Reset the device to get it back to its default state
*/
(void)XAxiPmon_ResetMetricCounter(InstancePtr);
XAxiPmon_ResetGlobalClkCounter(InstancePtr);
/*
* Write a value into the Incrementer register and
* read it back, and do the comparison
*/
XAxiPmon_SetIncrementerRange(InstancePtr, XAPM_INCREMENTER_0,
XAPM_TEST_RANGEUPPER_VALUE,
XAPM_TEST_RANGELOWER_VALUE);
XAxiPmon_GetIncrementerRange(InstancePtr, XAPM_INCREMENTER_0,
&RangeUpper, &RangeLower);
if ((RangeUpper == XAPM_TEST_RANGEUPPER_VALUE) &&
(RangeLower == XAPM_TEST_RANGELOWER_VALUE)) {
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;
}
/*
* Reset the device again to its default state.
*/
(void)XAxiPmon_ResetMetricCounter(InstancePtr);
XAxiPmon_ResetGlobalClkCounter(InstancePtr);
/*
* Return the test result.
*/
return Status;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_clock.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
#include "pm_common.h"
#include "pm_clock.h"
#include "pm_power.h"
#include "pm_usb.h"
#include "pm_periph.h"
#include "pm_ddr.h"
#include "pm_pll.h"
#include "crf_apb.h"
#include "crl_apb.h"
#include "afi.h"
/*********************************************************************
* Macros
********************************************************************/
#define CONNECT(clk, nd) \
{ \
.clock = &(clk), \
.node = &(nd), \
.nextClock = NULL, \
.nextNode = NULL, \
}
#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASE + 0x300U)
#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASE + 0x304U)
#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASE + 0x308U)
#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100U)
#define PM_CLOCK_TYPE_DIV0 (1U << 1U) /* bits 13:8 */
#define PM_CLOCK_TYPE_DIV1 (1U << 2U) /* bits 21:16 */
#define PM_CLOCK_TYPE_GATE24 (1U << 3U) /* bit 24 */
#define PM_CLOCK_TYPE_GATE25 (1U << 4U) /* bit 25 */
#define PM_CLOCK_TYPE_GATE26 (1U << 5U) /* bit 26 */
#define PM_CLOCK_TYPE_SYSTEM (1U << 6U) /* system level clock */
#define PM_CLOCK_TYPE_GATES (PM_CLOCK_TYPE_GATE24 | \
PM_CLOCK_TYPE_GATE25 | \
PM_CLOCK_TYPE_GATE26)
#define PM_CLOCK_HAS_DIV0(clk) (0U != ((clk)->type & PM_CLOCK_TYPE_DIV0))
#define PM_CLOCK_HAS_DIV1(clk) (0U != ((clk)->type & PM_CLOCK_TYPE_DIV1))
#define PM_DIV0_SHIFT 8U
#define PM_DIV1_SHIFT 16U
#define PM_DIV_MASK 0x3FU
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmClockCtrlMethods - Structure that encapsulates clock control methods
* @initParent Called during the boot to discover initial mux configuration
* @getParent Get mux select of the current clock parent
* @setParent Set clock parent (configure clock's mux)
* @getGate Get state of the clock gate
* @setGate Configure gate of this clock (activate or gate the clock)
* @getDivider Get currently configured divider of the clock
* @setDivider Set clock divider value
*/
typedef struct PmClockCtrlMethods {
void (*const initParent)(PmClock* const clock);
s32 (*const getParent)(PmClock* const clock, u32 *const select);
s32 (*const setParent)(PmClock* const clock, const u32 select);
s32 (*const getGate)(PmClock* const clock, u8* const enable);
s32 (*const setGate)(PmClock* const clock, const u8 enable);
s32 (*const getDivider)(PmClock* const clock, const u32 divId,
u32* const val);
s32 (*const setDivider)(PmClock* const clock, const u32 divId,
const u32 val);
} PmClockCtrlMethods;
/**
* PmClockClass - Structure that encapsulates essential clock methods
* @request Pointer to the function that is used to request clock
* @release Pointer to the function that is used to release clock
* @ctrl Pointer to struct that encapsulates other clock specific methods
* @getPerms Get permissions (which master can control this clock)
*
* @note A class of clocks for which the maintenance of use count is
* important must implement request/release methods. Other clock control
* methods are optional and depend on a particular clock class. If none of this
* is relevant for certain clock, e.g. oscillator, the class doesn't have to
* be defined.
*/
typedef struct PmClockClass {
PmClock* (*const request)(PmClock* const clock);
PmClock* (*const release)(PmClock* const clock);
u32 (*const getPerms)(const PmClock* const clock);
const PmClockCtrlMethods* const ctrl;
} PmClockClass;
/*
* PmClockPll - Structure for PLL-output clock
* @base Base clock structure
* @pll Pointer to the PLL that generates this clock
* @useCount Number of requests towards this clock
*/
typedef struct PmClockPll {
PmClock base;
PmPll* const pll;
u8 useCount;
} PmClockPll;
/**
* PmClockCrossDom - Clock structure for PLL cross-domain clocks
* @base Base clock structure
* @parent Pointer to the parent that drives this clock
* @ctrlAddr Address of the control register of the clock
* @useCount Number of requests towards this clock
*/
typedef struct PmClockCrossDom {
PmClock base;
PmClockPll* parent;
const u32 ctrlAddr;
u8 useCount;
} PmClockCrossDom;
/**
* PmClockSel2ClkIn - Pair of multiplexer select value and selected clock input
* @clkIn Pointer to input clock that is selected with the 'select' value
* @select Select value of the clock multiplexer
*/
typedef struct {
PmClock* const clkIn;
const u8 select;
} PmClockSel2ClkIn;
/**
* PmClockMux - Structure encapsulates MUX select values to clock input mapping
* @inputs Mux select to pll mapping at the input of the multiplexer
* @size Size of the inputs array
* @bits Number of bits of mux select
* @shift Number of bits to shift 'bits' in order to get mux select mask
*/
typedef struct {
const PmClockSel2ClkIn* const inputs;
const u8 size;
const u8 bits;
const u8 shift;
} PmClockMux;
/**
* PmClockGen - Generic on-chip clock structure
* @base Base clock structure
* @parent Pointer to the current parent that drives this clock
* @users Pointer to the list of nodes that use this clock
* @mux Mux model for this clock (models possible parents and selects)
* @ctrlAddr Address of the control register of the clock
* @ctrlVal Value of control register found at boot
* @type Type of the clock (specifies available dividers and gate, and
* whether it's the system clock)
* @useCount Number of requests towards this clock
*/
typedef struct PmClockGen {
PmClock base;
PmClock* parent;
PmClockHandle* users;
PmClockMux* const mux;
const u32 ctrlAddr;
u32 ctrlVal;
const u8 type;
u8 useCount;
} PmClockGen;
/**
* PmClockHandle - Models a clock/node pair (node using the clock)
* @clock Pointer to the clock used by the node
* @node Pointer to the node that uses the clock
* @nextClock Pointer to the next clock used by the node
* @nextNode Pointer to the next node that uses the clock
*/
typedef struct PmClockHandle {
PmClockGen* clock;
PmNode* node;
PmClockHandle* nextClock;
PmClockHandle* nextNode;
} PmClockHandle;
/**
* PmClockRequestInt() - Wrapper function for a chained requesting of a clock
* @clock Pointer to the clock to be requested
*
* @note This function implements non-recursive chained requesting of
* a clock and all its parents. Such an approach is required
* because recursion is not allowed due to the MISRA.
*/
static void PmClockRequestInt(PmClock* const clock)
{
PmClock* clk = clock;
while (NULL != clk) {
if ((clk->class != NULL) && (clk->class->request != NULL)) {
clk = clk->class->request(clk);
} else {
clk = NULL;
}
}
}
/**
* PmClockReleaseInt() - Wrapper function for a chained releasing of a clock
* @clock Pointer to the clock to be released
*
* @note This function implements non-recursive chained releasing of
* a clock and all its parents. Such an approach is required
* because recursion is not allowed due to the MISRA.
*/
static void PmClockReleaseInt(PmClock* const clock)
{
PmClock* clk = clock;
while (NULL != clk) {
if ((clk->class != NULL) && (clk->class->release != NULL)) {
clk = clk->class->release(clk);
} else {
clk = NULL;
}
}
}
/******************************************************************************/
/* Pll output clock models */
/**
* PmClockRequestPll() - PLL specific request clock method
* @clock Pointer to a PLL clock
*
* @return This function always returns NULL because the PLL has no clock
* parent (its parent is a PLL which is not modeled as a clock)
*/
static PmClock* PmClockRequestPll(PmClock* const clock)
{
PmClockPll* pclk = (PmClockPll*)clock->derived;
if (0U == pclk->useCount++) {
PmPllRequest(pclk->pll);
}
return NULL;
}
/**
* PmClockReleasePll() - PLL specific release clock method
* @clock Pointer to a PLL clock
*
* @return This function always returns NULL because the PLL has no clock
* parent (its parent is a PLL which is not modeled as a clock)
*/
static PmClock* PmClockReleasePll(PmClock* const clock)
{
PmClockPll* pclk = (PmClockPll*)clock->derived;
if (0U == --pclk->useCount) {
PmPllRelease(pclk->pll);
}
return NULL;
}
/**
* PmClockGetPllPerms() - Get permissions (which master can control this clock)
* @clock Pointer to a PLL clock
*
* @return This function ORed ipi masks of masters that are allowed to
* control this clock
*/
static u32 PmClockGetPllPerms(const PmClock* const clock)
{
const PmClockPll* pclk = (PmClockPll*)clock->derived;
return PmPllGetPermissions(pclk->pll);
}
static PmClockClass pmClockClassPll = {
.request = PmClockRequestPll,
.release = PmClockReleasePll,
.getPerms = PmClockGetPllPerms,
.ctrl = NULL,
};
static PmClockPll pmClockApll = {
.base = {
.derived = &pmClockApll,
.class = &pmClockClassPll,
.id = PM_CLOCK_APLL,
},
.pll = &pmApll_g,
.useCount = 0U,
};
static PmClockPll pmClockDpll = {
.base = {
.derived = &pmClockDpll,
.class = &pmClockClassPll,
.id = PM_CLOCK_DPLL,
},
.pll = &pmDpll_g,
.useCount = 0U,
};
static PmClockPll pmClockVpll = {
.base = {
.derived = &pmClockVpll,
.class = &pmClockClassPll,
.id = PM_CLOCK_VPLL,
},
.pll = &pmVpll_g,
.useCount = 0U,
};
static PmClockPll pmClockRpll = {
.base = {
.derived = &pmClockRpll,
.class = &pmClockClassPll,
.id = PM_CLOCK_RPLL,
},
.pll = &pmRpll_g,
.useCount = 0U,
};
static PmClockPll pmClockIOpll = {
.base = {
.derived = &pmClockIOpll,
.class = &pmClockClassPll,
.id = PM_CLOCK_IOPLL,
},
.pll = &pmIOpll_g,
.useCount = 0U,
};
/******************************************************************************/
/* On-chip/generic clocks that can drive PM nodes */
/**
* PmClockRequestGen() - Request clock method for generic clocks
* @clock Pointer to a generic clock
*
* @return Pointer to the parent clock
*/
static PmClock* PmClockRequestGen(PmClock* const clock)
{
PmClockGen* clk = (PmClockGen*)clock->derived;
PmClock* parent = NULL;
if (0U == clk->useCount++) {
parent = clk->parent;
}
return parent;
}
/**
* PmClockReleaseGen() - Release clock method for generic clocks
* @clock Pointer to a generic clock
*
* @return Pointer to the parent clock
*/
static PmClock* PmClockReleaseGen(PmClock* const clock)
{
PmClockGen* clk = (PmClockGen*)clock->derived;
PmClock* parent = NULL;
if (0U == --clk->useCount) {
parent = clk->parent;
}
return parent;
}
/**
* PmClockGenInitParent() - Initialize parent method for generic clocks
* @clock Pointer to the target clock
*
* @note After the the PMU-FW is loaded the only way to change the
* parent is using set parent method, which updates the parent
* pointer. Therefore this function just returns the parent
* pointer. The get parent function should not be called before the
* clocks are initialized.
*/
static void PmClockGenInitParent(PmClock* const clock)
{
PmClockGen* clk = (PmClockGen*)clock->derived;
u32 select, i;
if (NULL == clk->mux) {
goto done;
}
select = XPfw_Read32(clk->ctrlAddr);
select = (select >> clk->mux->shift) & MASK_OF_BITS(clk->mux->bits);
for (i = 0U; i < clk->mux->size; i++) {
if (select == clk->mux->inputs[i].select) {
clk->parent = clk->mux->inputs[i].clkIn;
break;
}
}
if (clk->parent) {
if (clk->parent->class == &pmClockClassPll) {
PmClockPll* pclk = (PmClockPll*)clk->parent->derived;
pclk->pll->childCount++;
}
}
done:
return;
}
/**
* PmClockGenSetParent() - Set parent method for generic clocks
* @clock Pointer to the target clock
* @select Mux select value
*
* @return Status of performing the operation:
* XST_SUCCESS if parent is set
* XST_NO_FEATURE if clock has no multiplexer
* XST_INVALID_PARAM if given parent is invalid/cannot be set
*/
static s32 PmClockGenSetParent(PmClock* const clock, const u32 select)
{
s32 status;
u32 i;
PmClockGen* clk = (PmClockGen*)clock->derived;
PmClock* new_parent = NULL;
if (NULL == clk->mux) {
status = XST_NO_FEATURE;
goto done;
}
if (select > MASK_OF_BITS(clk->mux->bits)) {
status = XST_INVALID_PARAM;
goto done;
}
/* Check if mux inputs are modeled (if not just configure the select) */
if (NULL == clk->mux->inputs) {
XPfw_RMW32(clk->ctrlAddr,
MASK_OF_BITS(clk->mux->bits) << clk->mux->shift,
select << clk->mux->shift);
status = XST_SUCCESS;
goto done;
}
/* Figure out what is the newly selected parent (if select is valid) */
status = XST_INVALID_PARAM;
for (i = 0U; i < clk->mux->size; i++) {
if (select == clk->mux->inputs[i].select) {
new_parent = clk->mux->inputs[i].clkIn;
status = XST_SUCCESS;
break;
}
}
if (XST_SUCCESS != status) {
status = XST_INVALID_PARAM;
goto done;
}
if (new_parent == clk->parent) {
goto done;
}
if (NULL != new_parent) {
PmClockRequestInt(new_parent);
}
if (new_parent->class == &pmClockClassPll) {
PmClockPll* pclk = (PmClockPll*)new_parent->derived;
pclk->pll->childCount++;
}
XPfw_RMW32(clk->ctrlAddr,
MASK_OF_BITS(clk->mux->bits) << clk->mux->shift,
select << clk->mux->shift);
if (NULL != clk->parent) {
PmClockReleaseInt(clk->parent);
if (clk->parent->class == &pmClockClassPll) {
PmClockPll* pclk = (PmClockPll*)clk->parent->derived;
pclk->pll->childCount--;
}
}
clk->parent = new_parent;
done:
return status;
}
/**
* PmClockGenGetParent() - Get parent method for generic clocks
* @clock Pointer to the target clock
* @select Location to store clock select value
*
* @return Status of getting the mux select value
*/
static s32 PmClockGenGetParent(PmClock* const clock, u32 *const select)
{
PmClockGen* clk = (PmClockGen*)clock->derived;
s32 status = XST_NO_FEATURE;
u32 val;
if (NULL == clk->mux) {
goto done;
}
val = XPfw_Read32(clk->ctrlAddr);
val = (val >> clk->mux->shift) & MASK_OF_BITS(clk->mux->bits);
*select = val;
status = XST_SUCCESS;
done:
return status;
}
/**
* PmClockGateGetShift() - Get gate shift from gate flag
* @clk Generic clock
* @shift Location where the shift should be stored
*
* @return Status of getting the gate
*/
static s32 PmClockGateGetShift(const PmClockGen* const clk, u8* const shift)
{
s32 status = XST_SUCCESS;
switch (clk->type & PM_CLOCK_TYPE_GATES) {
case PM_CLOCK_TYPE_GATE24:
*shift = 24U;
break;
case PM_CLOCK_TYPE_GATE25:
*shift = 25U;
break;
case PM_CLOCK_TYPE_GATE26:
*shift = 26U;
break;
default:
status = XST_NO_FEATURE;
break;
}
return status;
}
/**
* PmClockGenSetGateState() - Set state of generic clock gate
* @clock Generic clock
* @enable Gate flag to set: 0=disable, 1=enable
*
* @return Status of setting the gate state:
* XST_SUCCESS if state is set
* XST_NO_FEATURE if the given clock has no gate
*/
static s32 PmClockGenSetGateState(PmClock* const clock, const u8 enable)
{
u8 shift = 0x0U;
PmClockGen* clk = (PmClockGen*)clock->derived;
s32 status = PmClockGateGetShift(clk, &shift);
if (XST_SUCCESS == status) {
XPfw_RMW32(clk->ctrlAddr, 1U << shift, enable << shift);
}
return status;
}
/**
* PmClockGenGetGateState() - Get state of generic clock gate
* @clock Generic clock
* @enable Location where the state should be stored
*
* @return Status of getting the gate state:
* XST_SUCCESS if enable location is updated
* XST_NO_FEATURE if the given clock has no gate
*/
static s32 PmClockGenGetGateState(PmClock* const clock, u8* const enable)
{
u8 shift = 0x0U;
PmClockGen* clk = (PmClockGen*)clock->derived;
s32 status = PmClockGateGetShift(clk, &shift);
if (XST_SUCCESS == status) {
*enable = (XPfw_Read32(clk->ctrlAddr) >> shift) & 1U;
}
return status;
}
/**
* PmClockGenSetDivider() - Generic clock method to set clock divider
* @clock Target clock
* @divId Identifier of the divider to be set
* @val Divider value to be set
*
* @return Status of setting the divider:
* XST_SUCCESS the divider is configured as requested
* XST_NO_FEATURE if clock has no divider
* XST_INVALID_PARAM the requested value is out of physically
* configurable divider's scope
*/
static s32 PmClockGenSetDivider(PmClock* const clock, const u32 divId,
const u32 val)
{
s32 status = XST_SUCCESS;
PmClockGen* clk = (PmClockGen*)clock->derived;
u8 shift;
if (((PM_CLOCK_DIV0_ID == divId) && !PM_CLOCK_HAS_DIV0(clk)) ||
((PM_CLOCK_DIV1_ID == divId) && !PM_CLOCK_HAS_DIV1(clk))) {
/* Clock has no divider with specified ID */
status = XST_NO_FEATURE;
goto done;
}
if (val > PM_DIV_MASK) {
/* Given div value is out of scope */
status = XST_INVALID_PARAM;
goto done;
}
if (PM_CLOCK_DIV0_ID == divId) {
shift = PM_DIV0_SHIFT;
} else if (PM_CLOCK_DIV1_ID == divId) {
shift = PM_DIV1_SHIFT;
} else {
status = XST_INVALID_PARAM;
goto done;
}
XPfw_RMW32(clk->ctrlAddr, PM_DIV_MASK << shift, val << shift);
done:
return status;
}
/**
* PmClockGenGetDivider() - Generic clock method to get clock divider
* @clock Target clock
* @divId Identifier of the divider whose value should be get
* @val Location where the divider value needs to be stored
*
* @return Status of getting the divider:
* XST_SUCCESS the divider value is stored in 'div' location
* XST_NO_FEATURE if clock has no divider
*/
static s32 PmClockGenGetDivider(PmClock* const clock, const u32 divId,
u32* const val)
{
s32 status = XST_SUCCESS;
PmClockGen* clk = (PmClockGen*)clock->derived;
u32 reg;
u8 shift;
if (((PM_CLOCK_DIV0_ID == divId) && !PM_CLOCK_HAS_DIV0(clk)) ||
((PM_CLOCK_DIV1_ID == divId) && !PM_CLOCK_HAS_DIV1(clk))) {
/* Clock has no divider with specified ID */
status = XST_NO_FEATURE;
goto done;
}
if (PM_CLOCK_DIV0_ID == divId) {
shift = PM_DIV0_SHIFT;
} else if (PM_CLOCK_DIV1_ID == divId) {
shift = PM_DIV1_SHIFT;
} else {
status = XST_INVALID_PARAM;
goto done;
}
reg = XPfw_Read32(clk->ctrlAddr);
*val = (reg >> shift) & PM_DIV_MASK;
done:
return status;
}
/**
* PmClockGenGetPerms() - Get permissions (which master can control this clock)
* @clock Pointer to a PLL clock
*
* @return This function ORed ipi masks of masters that are allowed to
* control this clock
*/
static u32 PmClockGenGetPerms(const PmClock* const clock)
{
PmClockHandle* ch;
const PmClockGen* clk = (PmClockGen*)clock->derived;
u32 permissions = 0U;
/* If this is a system clock no one has permission to control it */
if (0U != (PM_CLOCK_TYPE_SYSTEM & clk->type)) {
goto done;
}
ch = clk->users;
while (NULL != ch) {
permissions |= PmNodeGetPermissions(ch->node);
ch = ch->nextNode;
}
done:
return permissions;
}
static PmClockCtrlMethods pmClockGenCtrlMethods = {
.initParent = PmClockGenInitParent,
.getParent = PmClockGenGetParent,
.setParent = PmClockGenSetParent,
.getGate = PmClockGenGetGateState,
.setGate = PmClockGenSetGateState,
.getDivider = PmClockGenGetDivider,
.setDivider = PmClockGenSetDivider,
};
static PmClockClass pmClockClassGen = {
.request = PmClockRequestGen,
.release = PmClockReleaseGen,
.getPerms = PmClockGenGetPerms,
.ctrl = &pmClockGenCtrlMethods,
};
/******************************************************************************/
/* Pll output cross domain clock models */
/**
* PmClockRequestCrossDom() - Request clock method for cross-domain clocks
* @clock Pointer to a cross-domain clock
*
* @return Pointer to the parent clock
*/
static PmClock* PmClockRequestCrossDom(PmClock* const clock)
{
PmClockCrossDom* clk = (PmClockCrossDom*)clock->derived;
PmClock* parent = NULL;
if (0U == clk->useCount++) {
parent = &clk->parent->base;
}
return parent;
}
/**
* PmClockReleaseCrossDom() - Release clock method for cross-domain clocks
* @clock Pointer to a cross-domain clock
*
* @return Pointer to the parent clock
*/
static PmClock* PmClockReleaseCrossDom(PmClock* const clock)
{
PmClockCrossDom* clk = (PmClockCrossDom*)clock->derived;
PmClock* parent = NULL;
if (0U == --clk->useCount) {
parent = &clk->parent->base;
}
return parent;
}
/**
* PmClockCrossDomSetDivider() - Cross-domain clock method to set clock divider
* @clock Target clock
* @divId Identifier of the divider to be set
* @val Divider value to be set
*
* @return Status of setting the divider:
* XST_SUCCESS the divider is configured as requested
* XST_NO_FEATURE if clock has no divider
* XST_INVALID_PARAM the requested value is out of physically
* configurable divider's scope
*/
static s32 PmClockCrossDomSetDivider(PmClock* const clock, const u32 divId,
const u32 val)
{
s32 status = XST_SUCCESS;
PmClockCrossDom* clk = (PmClockCrossDom*)clock->derived;
if (PM_CLOCK_DIV0_ID != divId) {
/* Cross-domain clocks have only one divisor */
status = XST_NO_FEATURE;
goto done;
}
if (val > PM_DIV_MASK) {
/* Given div value is out of scope */
status = XST_INVALID_PARAM;
goto done;
}
XPfw_RMW32(clk->ctrlAddr, PM_DIV_MASK << PM_DIV0_SHIFT,
val << PM_DIV0_SHIFT);
done:
return status;
}
/**
* PmClockCrossDomGetDivider() - Cross-domain clock method to get clock divider
* @clock Target clock
* @divId Identifier of the divider whose value should be get
* @val Location where the divider value needs to be stored
*
* @return Status of getting the divider:
* XST_SUCCESS the divider value is stored in 'div' location
* XST_NO_FEATURE if clock has no divider
*/
static s32 PmClockCrossDomGetDivider(PmClock* const clock, const u32 divId,
u32* const val)
{
s32 status = XST_SUCCESS;
PmClockCrossDom* clk = (PmClockCrossDom*)clock->derived;
if (PM_CLOCK_DIV0_ID != divId) {
/* Cross-domain clocks have only one divisor */
status = XST_NO_FEATURE;
goto done;
}
*val = (XPfw_Read32(clk->ctrlAddr) >> PM_DIV0_SHIFT) & PM_DIV_MASK;
done:
return status;
}
/**
* PmClockCrossDomGetPerms() - Get permissions (which master can control clock)
* @clock Pointer to a cross-domain clock
*
* @return This function ORed ipi masks of masters that are allowed to
* control this clock
*/
static u32 PmClockCrossDomGetPerms(const PmClock* const clock)
{
const PmClockCrossDom* clk = (PmClockCrossDom*)clock->derived;
u32 permissions = 0U;
/* Inherit permissions from PLL output clock (parent) */
if ((NULL != clk->parent->base.class) &&
(NULL != clk->parent->base.class->getPerms)) {
permissions =
clk->parent->base.class->getPerms(&clk->parent->base);
}
return permissions;
}
static PmClockCtrlMethods pmClockCrossDomCtrlMethods = {
.initParent = NULL,
.getParent = NULL,
.setParent = NULL,
.getGate = NULL,
.setGate = NULL,
.getDivider = PmClockCrossDomGetDivider,
.setDivider = PmClockCrossDomSetDivider,
};
static PmClockClass pmClockClassCrossDom = {
.request = PmClockRequestCrossDom,
.release = PmClockReleaseCrossDom,
.getPerms = PmClockCrossDomGetPerms,
.ctrl = &pmClockCrossDomCtrlMethods,
};
static PmClockCrossDom pmClockIOpllToFpd = {
.base = {
.derived = &pmClockIOpllToFpd,
.class = &pmClockClassCrossDom,
.id = PM_CLOCK_IOPLL_TO_FPD,
},
.parent = &pmClockIOpll,
.ctrlAddr = CRL_APB_IOPLL_TO_FPD_CTRL,
.useCount = 0U,
};
static PmClockCrossDom pmClockRpllToFpd = {
.base = {
.derived = &pmClockRpllToFpd,
.class = &pmClockClassCrossDom,
.id = PM_CLOCK_RPLL_TO_FPD,
},
.parent = &pmClockRpll,
.ctrlAddr = CRL_APB_RPLL_TO_FPD_CTRL,
.useCount = 0U,
};
static PmClockCrossDom pmClockDpllToLpd = {
.base = {
.derived = &pmClockDpllToLpd,
.class = &pmClockClassCrossDom,
.id = PM_CLOCK_DPLL_TO_LPD,
},
.parent = &pmClockDpll,
.ctrlAddr = CRF_APB_DPLL_TO_LPD_CTRL,
.useCount = 0U,
};
static PmClockCrossDom pmClockVpllToLpd = {
.base = {
.derived = &pmClockVpllToLpd,
.class = &pmClockClassCrossDom,
.id = PM_CLOCK_VPLL_TO_LPD,
},
.parent = &pmClockVpll,
.ctrlAddr = CRF_APB_VPLL_TO_LPD_CTRL,
.useCount = 0U,
};
static const PmClockSel2ClkIn advSel2ClkIn[] = {
{
.clkIn = &pmClockApll.base,
.select = 0U,
}, {
.clkIn = &pmClockDpll.base,
.select = 2U,
}, {
.clkIn = &pmClockVpll.base,
.select = 3U,
},
};
static PmClockMux advMux = {
.inputs = advSel2ClkIn,
.size = ARRAY_SIZE(advSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn avdSel2ClkIn[] = {
{
.clkIn = &pmClockApll.base,
.select = 0U,
}, {
.clkIn = &pmClockVpll.base,
.select = 2U,
}, {
.clkIn = &pmClockDpll.base,
.select = 3U,
},
};
static PmClockMux avdMux = {
.inputs = avdSel2ClkIn,
.size = ARRAY_SIZE(avdSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn aiodSel2ClkIn[] = {
{
.clkIn = &pmClockApll.base,
.select = 0U,
}, {
.clkIn = &pmClockIOpllToFpd.base,
.select = 2U,
}, {
.clkIn = &pmClockDpll.base,
.select = 3U,
},
};
static PmClockMux aiodMux = {
.inputs = aiodSel2ClkIn,
.size = ARRAY_SIZE(aiodSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn vdrSel2ClkIn[] = {
{
.clkIn = &pmClockVpll.base,
.select = 0U,
}, {
.clkIn = &pmClockDpll.base,
.select = 2U,
}, {
.clkIn = &pmClockRpllToFpd.base,
.select = 3U,
},
};
static PmClockMux vdrMux = {
.inputs = vdrSel2ClkIn,
.size = ARRAY_SIZE(vdrSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn dvSel2ClkIn[] = {
{
.clkIn = &pmClockDpll.base,
.select = 0U,
}, {
.clkIn = &pmClockVpll.base,
.select = 1U,
},
};
static PmClockMux dvMux = {
.inputs = dvSel2ClkIn,
.size = ARRAY_SIZE(dvSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn iovdSel2ClkIn[] = {
{
.clkIn = &pmClockIOpllToFpd.base,
.select = 0U,
}, {
.clkIn = &pmClockVpll.base,
.select = 2U,
}, {
.clkIn = &pmClockDpll.base,
.select = 3U,
},
};
static PmClockMux iovdMux = {
.inputs = iovdSel2ClkIn,
.size = ARRAY_SIZE(iovdSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn ioadSel2ClkIn[] = {
{
.clkIn = &pmClockIOpllToFpd.base,
.select = 0U,
}, {
.clkIn = &pmClockApll.base,
.select = 2U,
}, {
.clkIn = &pmClockDpll.base,
.select = 3U,
},
};
static PmClockMux ioadMux = {
.inputs = ioadSel2ClkIn,
.size = ARRAY_SIZE(ioadSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn iodaSel2ClkIn[] = {
{
.clkIn = &pmClockIOpllToFpd.base,
.select = 0U,
}, {
.clkIn = &pmClockDpll.base,
.select = 2U,
}, {
.clkIn = &pmClockApll.base,
.select = 3U,
},
};
static PmClockMux iodaMux = {
.inputs = iodaSel2ClkIn,
.size = ARRAY_SIZE(iodaSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn iorSel2ClkIn[] = {
{
.clkIn = &pmClockIOpll.base,
.select = 0U,
}, {
.clkIn = &pmClockRpll.base,
.select = 2U,
},
};
static PmClockMux iorMux = {
.inputs = iorSel2ClkIn,
.size = ARRAY_SIZE(iorSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn iordFpdSel2ClkIn[] = {
{
.clkIn = &pmClockIOpllToFpd.base,
.select = 0U,
}, {
.clkIn = &pmClockRpllToFpd.base,
.select = 2U,
}, {
.clkIn = &pmClockDpll.base,
.select = 3U,
},
};
static PmClockMux iordFpdMux = {
.inputs = iordFpdSel2ClkIn,
.size = ARRAY_SIZE(iordFpdSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn iordSel2ClkIn[] = {
{
.clkIn = &pmClockIOpll.base,
.select = 0U,
}, {
.clkIn = &pmClockRpll.base,
.select = 2U,
}, {
.clkIn = &pmClockDpllToLpd.base,
.select = 3U,
},
};
static PmClockMux iordMux = {
.inputs = iordSel2ClkIn,
.size = ARRAY_SIZE(iordSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn iorvSel2ClkIn[] = {
{
.clkIn = &pmClockIOpll.base,
.select = 0U,
}, {
.clkIn = &pmClockRpll.base,
.select = 2U,
}, {
.clkIn = &pmClockVpllToLpd.base,
.select = 3U,
},
};
static PmClockMux iorvMux = {
.inputs = iorvSel2ClkIn,
.size = ARRAY_SIZE(iorvSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
static const PmClockSel2ClkIn riodSel2ClkIn[] = {
{
.clkIn = &pmClockRpll.base,
.select = 0U,
}, {
.clkIn = &pmClockIOpll.base,
.select = 2U,
}, {
.clkIn = &pmClockDpllToLpd.base,
.select = 3U,
},
};
static PmClockMux riodMux = {
.inputs = riodSel2ClkIn,
.size = ARRAY_SIZE(riodSel2ClkIn),
.bits = 2U,
.shift = 0U,
};
/* CRF_APB clocks */
static PmClockGen pmClockAcpu = {
.base = {
.derived = &pmClockAcpu,
.class = &pmClockClassGen,
.id = PM_CLOCK_ACPU,
},
.parent = NULL,
.users = NULL,
.mux = &advMux,
.ctrlAddr = CRF_APB_ACPU_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0,
.useCount = 0U,
};
static PmClockGen pmClockAcpuFull = {
.base = {
.derived = &pmClockAcpuFull,
.class = &pmClockClassGen,
.id = PM_CLOCK_ACPU_FULL,
},
.parent = &pmClockAcpu.base,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRF_APB_ACPU_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockAcpuHalf = {
.base = {
.derived = &pmClockAcpuHalf,
.class = &pmClockClassGen,
.id = PM_CLOCK_ACPU_HALF,
},
.parent = &pmClockAcpu.base,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRF_APB_ACPU_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE25,
.useCount = 0U,
};
static PmClockGen pmClockDbgTrace = {
.base = {
.derived = &pmClockDbgTrace,
.class = &pmClockClassGen,
.id = PM_CLOCK_DBG_TRACE,
},
.parent = NULL,
.users = NULL,
.mux = &iodaMux,
.ctrlAddr = CRF_APB_DBG_TRACE_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24 |
PM_CLOCK_TYPE_SYSTEM,
.useCount = 0U,
};
static PmClockGen pmClockDbgFpd = {
.base = {
.derived = &pmClockDbgFpd,
.class = &pmClockClassGen,
.id = PM_CLOCK_DBG_FPD,
},
.parent = NULL,
.users = NULL,
.mux = &iodaMux,
.ctrlAddr = CRF_APB_DBG_FPD_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24 |
PM_CLOCK_TYPE_SYSTEM,
.useCount = 0U,
};
static PmClockGen pmClockDpVideo = {
.base = {
.derived = &pmClockDpVideo,
.class = &pmClockClassGen,
.id = PM_CLOCK_DP_VIDEO_REF,
},
.parent = NULL,
.users = NULL,
.mux = &vdrMux,
.ctrlAddr = CRF_APB_DP_VIDEO_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockDpAudio = {
.base = {
.derived = &pmClockDpAudio,
.class = &pmClockClassGen,
.id = PM_CLOCK_DP_AUDIO_REF,
},
.parent = NULL,
.users = NULL,
.mux = &vdrMux,
.ctrlAddr = CRF_APB_DP_AUDIO_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockDpStc = {
.base = {
.derived = &pmClockDpStc,
.class = &pmClockClassGen,
.id = PM_CLOCK_DP_STC_REF,
},
.parent = NULL,
.users = NULL,
.mux = &vdrMux,
.ctrlAddr = CRF_APB_DP_STC_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockDdr __attribute__((__section__(".srdata"))) = {
.base = {
.derived = &pmClockDdr,
.class = &pmClockClassGen,
.id = PM_CLOCK_DDR_REF,
},
.parent = NULL,
.users = NULL,
.mux = &dvMux,
.ctrlAddr = CRF_APB_DDR_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0,
.useCount = 0U,
};
static PmClockGen pmClockGpu = {
.base = {
.derived = &pmClockGpu,
.class = &pmClockClassGen,
.id = PM_CLOCK_GPU_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iovdMux,
.ctrlAddr = CRF_APB_GPU_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockGpuPp0 = {
.base = {
.derived = &pmClockGpuPp0,
.class = &pmClockClassGen,
.id = PM_CLOCK_GPU_PP0_REF,
},
.parent = &pmClockGpu.base,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRF_APB_GPU_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE25,
.useCount = 0U,
};
static PmClockGen pmClockGpuPp1 = {
.base = {
.derived = &pmClockGpuPp1,
.class = &pmClockClassGen,
.id = PM_CLOCK_GPU_PP1_REF,
},
.parent = &pmClockGpu.base,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRF_APB_GPU_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE26,
.useCount = 0U,
};
static PmClockGen pmClockSata = {
.base = {
.derived = &pmClockSata,
.class = &pmClockClassGen,
.id = PM_CLOCK_SATA_REF,
},
.parent = NULL,
.users = NULL,
.mux = &ioadMux,
.ctrlAddr = CRF_APB_SATA_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockPcie = {
.base = {
.derived = &pmClockPcie,
.class = &pmClockClassGen,
.id = PM_CLOCK_PCIE_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordFpdMux,
.ctrlAddr = CRF_APB_PCIE_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockGdma = {
.base = {
.derived = &pmClockGdma,
.class = &pmClockClassGen,
.id = PM_CLOCK_GDMA_REF,
},
.parent = NULL,
.users = NULL,
.mux = &avdMux,
.ctrlAddr = CRF_APB_GDMA_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockDpDma = {
.base = {
.derived = &pmClockDpDma,
.class = &pmClockClassGen,
.id = PM_CLOCK_DPDMA_REF,
},
.parent = NULL,
.users = NULL,
.mux = &avdMux,
.ctrlAddr = CRF_APB_DPDMA_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockTopSwMain __attribute__((__section__(".srdata"))) = {
.base = {
.derived = &pmClockTopSwMain,
.class = &pmClockClassGen,
.id = PM_CLOCK_TOPSW_MAIN,
},
.parent = NULL,
.users = NULL,
.mux = &avdMux,
.ctrlAddr = CRF_APB_TOPSW_MAIN_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24 |
PM_CLOCK_TYPE_SYSTEM,
.useCount = 0U,
};
static PmClockGen pmClockTopSwLsBus __attribute__((__section__(".srdata"))) = {
.base = {
.derived = &pmClockTopSwLsBus,
.class = &pmClockClassGen,
.id = PM_CLOCK_TOPSW_LSBUS,
},
.parent = NULL,
.users = NULL,
.mux = &aiodMux,
.ctrlAddr = CRF_APB_TOPSW_LSBUS_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24 |
PM_CLOCK_TYPE_SYSTEM,
.useCount = 0U,
};
static PmClockGen pmClockDbgTstmp = {
.base = {
.derived = &pmClockDbgTstmp,
.class = &pmClockClassGen,
.id = PM_CLOCK_DBG_TSTMP,
},
.parent = NULL,
.users = NULL,
.mux = &iodaMux,
.ctrlAddr = CRF_APB_DBG_TSTMP_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_SYSTEM,
.useCount = 0U,
};
/* CRL_APB clocks */
static PmClockGen pmClockUsb3Dual = {
.base = {
.derived = &pmClockUsb3Dual,
.class = &pmClockClassGen,
.id = PM_CLOCK_USB3_DUAL_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_USB3_DUAL_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE25,
.useCount = 0U,
};
static PmClockGen pmClockGem0RefUngated = {
.base = {
.derived = &pmClockGem0RefUngated,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM0_REF_UNGATED,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_GEM0_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.useCount = 0U,
};
static PmClockGen pmClockGem1RefUngated = {
.base = {
.derived = &pmClockGem1RefUngated,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM1_REF_UNGATED,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_GEM1_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.useCount = 0U,
};
static PmClockGen pmClockGem2RefUngated = {
.base = {
.derived = &pmClockGem2RefUngated,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM2_REF_UNGATED,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_GEM2_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.useCount = 0U,
};
static PmClockGen pmClockGem3RefUngated = {
.base = {
.derived = &pmClockGem3RefUngated,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM3_REF_UNGATED,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_GEM3_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.useCount = 0U,
};
static PmClockGen pmClockUsb0Bus = {
.base = {
.derived = &pmClockUsb0Bus,
.class = &pmClockClassGen,
.id = PM_CLOCK_USB0_BUS_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_USB0_BUS_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE25,
.useCount = 0U,
};
static PmClockGen pmClockUsb1Bus = {
.base = {
.derived = &pmClockUsb1Bus,
.class = &pmClockClassGen,
.id = PM_CLOCK_USB1_BUS_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_USB1_BUS_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE25,
.useCount = 0U,
};
static PmClockGen pmClockQSpi = {
.base = {
.derived = &pmClockQSpi,
.class = &pmClockClassGen,
.id = PM_CLOCK_QSPI_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_QSPI_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockSdio0 = {
.base = {
.derived = &pmClockSdio0,
.class = &pmClockClassGen,
.id = PM_CLOCK_SDIO0_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iorvMux,
.ctrlAddr = CRL_APB_SDIO0_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockSdio1 = {
.base = {
.derived = &pmClockSdio1,
.class = &pmClockClassGen,
.id = PM_CLOCK_SDIO1_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iorvMux,
.ctrlAddr = CRL_APB_SDIO1_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockUart0 = {
.base = {
.derived = &pmClockUart0,
.class = &pmClockClassGen,
.id = PM_CLOCK_UART0_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_UART0_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockUart1 = {
.base = {
.derived = &pmClockUart1,
.class = &pmClockClassGen,
.id = PM_CLOCK_UART1_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_UART1_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockSpi0 = {
.base = {
.derived = &pmClockSpi0,
.class = &pmClockClassGen,
.id = PM_CLOCK_SPI0_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_SPI0_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockSpi1 = {
.base = {
.derived = &pmClockSpi1,
.class = &pmClockClassGen,
.id = PM_CLOCK_SPI1_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_SPI1_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockCan0Ref = {
.base = {
.derived = &pmClockCan0Ref,
.class = &pmClockClassGen,
.id = PM_CLOCK_CAN0_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_CAN0_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockCan1Ref = {
.base = {
.derived = &pmClockCan1Ref,
.class = &pmClockClassGen,
.id = PM_CLOCK_CAN1_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_CAN1_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockCpuR5 = {
.base = {
.derived = &pmClockCpuR5,
.class = &pmClockClassGen,
.id = PM_CLOCK_CPU_R5,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_CPU_R5_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1,
.useCount = 0U,
};
static PmClockGen pmClockCpuR5Core = {
.base = {
.derived = &pmClockCpuR5Core,
.class = &pmClockClassGen,
.id = PM_CLOCK_CPU_R5_CORE,
},
.parent = &pmClockCpuR5.base,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRL_APB_CPU_R5_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE25,
.useCount = 0U,
};
static PmClockGen pmClockIouSwitch = {
.base = {
.derived = &pmClockIouSwitch,
.class = &pmClockClassGen,
.id = PM_CLOCK_IOU_SWITCH,
},
.parent = NULL,
.users = NULL,
.mux = &riodMux,
.ctrlAddr = CRL_APB_IOU_SWITCH_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24 |
PM_CLOCK_TYPE_SYSTEM,
.useCount = 0U,
};
static PmClockGen pmClockCsuPll = {
.base = {
.derived = &pmClockCsuPll,
.class = &pmClockClassGen,
.id = PM_CLOCK_CSU_PLL,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_CSU_PLL_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockPcap = {
.base = {
.derived = &pmClockPcap,
.class = &pmClockClassGen,
.id = PM_CLOCK_PCAP,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_PCAP_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockLpdSwitch = {
.base = {
.derived = &pmClockLpdSwitch,
.class = &pmClockClassGen,
.id = PM_CLOCK_LPD_SWITCH,
},
.parent = NULL,
.users = NULL,
.mux = &riodMux,
.ctrlAddr = CRL_APB_LPD_SWITCH_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24 |
PM_CLOCK_TYPE_SYSTEM,
.useCount = 0U,
};
static PmClockGen pmClockLpdLsBus = {
.base = {
.derived = &pmClockLpdLsBus,
.class = &pmClockClassGen,
.id = PM_CLOCK_LPD_LSBUS,
},
.parent = NULL,
.users = NULL,
.mux = &riodMux,
.ctrlAddr = CRL_APB_LPD_LSBUS_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24 |
PM_CLOCK_TYPE_SYSTEM,
.useCount = 0U,
};
static PmClockGen pmClockDbgLpd = {
.base = {
.derived = &pmClockDbgLpd,
.class = &pmClockClassGen,
.id = PM_CLOCK_DBG_LPD,
},
.parent = NULL,
.users = NULL,
.mux = &riodMux,
.ctrlAddr = CRL_APB_DBG_LPD_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24 |
PM_CLOCK_TYPE_SYSTEM,
.useCount = 0U,
};
static PmClockGen pmClockNand = {
.base = {
.derived = &pmClockNand,
.class = &pmClockClassGen,
.id = PM_CLOCK_NAND_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_NAND_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockAdma = {
.base = {
.derived = &pmClockAdma,
.class = &pmClockClassGen,
.id = PM_CLOCK_ADMA_REF,
},
.parent = NULL,
.users = NULL,
.mux = &riodMux,
.ctrlAddr = CRL_APB_ADMA_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockPl0 = {
.base = {
.derived = &pmClockPl0,
.class = &pmClockClassGen,
.id = PM_CLOCK_PL0_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_PL0_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockPl1 = {
.base = {
.derived = &pmClockPl1,
.class = &pmClockClassGen,
.id = PM_CLOCK_PL1_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_PL1_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockPl2 = {
.base = {
.derived = &pmClockPl2,
.class = &pmClockClassGen,
.id = PM_CLOCK_PL2_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_PL2_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockPl3 = {
.base = {
.derived = &pmClockPl3,
.class = &pmClockClassGen,
.id = PM_CLOCK_PL3_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_PL3_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockGemTsuRef = {
.base = {
.derived = &pmClockGemTsuRef,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM_TSU_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_GEM_TSU_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockDll = {
.base = {
.derived = &pmClockDll,
.class = &pmClockClassGen,
.id = PM_CLOCK_DLL_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iorMux,
.ctrlAddr = CRL_APB_DLL_REF_CTRL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static PmClockGen pmClockAms = {
.base = {
.derived = &pmClockAms,
.class = &pmClockClassGen,
.id = PM_CLOCK_AMS_REF,
},
.parent = NULL,
.users = NULL,
.mux = &riodMux,
.ctrlAddr = CRL_APB_AMS_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24 |
PM_CLOCK_TYPE_SYSTEM, /* because of the commit 7611b2fc18 */
.useCount = 0U,
};
static PmClockGen pmClockI2C0 = {
.base = {
.derived = &pmClockI2C0,
.class = &pmClockClassGen,
.id = PM_CLOCK_I2C0_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_I2C0_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static PmClockGen pmClockI2C1 = {
.base = {
.derived = &pmClockI2C1,
.class = &pmClockClassGen,
.id = PM_CLOCK_I2C1_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordMux,
.ctrlAddr = CRL_APB_I2C1_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_DIV1 | PM_CLOCK_TYPE_GATE24,
.useCount = 0U,
};
static const PmClockSel2ClkIn iordPsRefSel2ClkIn[] = {
{
.clkIn = &pmClockIOpll.base,
.select = 0U,
}, {
.clkIn = &pmClockRpll.base,
.select = 2U,
}, {
.clkIn = &pmClockDpllToLpd.base,
.select = 3U,
}, {
.clkIn = NULL, /* oscillator */
.select = 4U,
}, {
.clkIn = NULL, /* oscillator */
.select = 5U,
}, {
.clkIn = NULL, /* oscillator */
.select = 6U,
}, {
.clkIn = NULL, /* oscillator */
.select = 7U,
},
};
static PmClockMux iordPsRefMux = {
.inputs = iordPsRefSel2ClkIn,
.size = ARRAY_SIZE(iordPsRefSel2ClkIn),
.bits = 3U,
.shift = 0U,
};
static PmClockGen pmClockTimeStamp = {
.base = {
.derived = &pmClockTimeStamp,
.class = &pmClockClassGen,
.id = PM_CLOCK_TIMESTAMP_REF,
},
.parent = NULL,
.users = NULL,
.mux = &iordPsRefMux,
.ctrlAddr = CRL_APB_TIMESTAMP_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_DIV0 | PM_CLOCK_TYPE_GATE24 |
PM_CLOCK_TYPE_SYSTEM,
.useCount = 0U,
};
static PmClockMux can0MioMux = {
.inputs = NULL,
.size = 0U,
.bits = 7U,
.shift = 0U,
};
static PmClockGen pmClockCan0Mio = {
.base = {
.derived = &pmClockCan0Mio,
.class = &pmClockClassGen,
.id = PM_CLOCK_CAN0_MIO,
},
.parent = NULL,
.users = NULL,
.mux = &can0MioMux,
.ctrlAddr = IOU_SLCR_CAN_MIO_CTRL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static const PmClockSel2ClkIn can0Sel2ClkIn[] = {
{
.clkIn = &pmClockCan0Ref.base,
.select = 0U,
}, {
.clkIn = &pmClockCan0Mio.base,
.select = 1U,
},
};
static PmClockMux can0Mux = {
.inputs = can0Sel2ClkIn,
.size = ARRAY_SIZE(can0Sel2ClkIn),
.bits = 1U,
.shift = 7U,
};
static PmClockGen pmClockCan0 = {
.base = {
.derived = &pmClockCan0,
.class = &pmClockClassGen,
.id = PM_CLOCK_CAN0,
},
.parent = NULL,
.users = NULL,
.mux = &can0Mux,
.ctrlAddr = IOU_SLCR_CAN_MIO_CTRL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static PmClockMux can1MioMux = {
.inputs = NULL,
.size = 0U,
.bits = 7U,
.shift = 15U,
};
static PmClockGen pmClockCan1Mio = {
.base = {
.derived = &pmClockCan1Mio,
.class = &pmClockClassGen,
.id = PM_CLOCK_CAN1_MIO,
},
.parent = NULL,
.users = NULL,
.mux = &can1MioMux,
.ctrlAddr = IOU_SLCR_CAN_MIO_CTRL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static const PmClockSel2ClkIn can1Sel2ClkIn[] = {
{
.clkIn = &pmClockCan1Ref.base,
.select = 0U,
}, {
.clkIn = &pmClockCan1Mio.base,
.select = 1U,
},
};
static PmClockMux can1Mux = {
.inputs = can1Sel2ClkIn,
.size = ARRAY_SIZE(can1Sel2ClkIn),
.bits = 1U,
.shift = 22U,
};
static PmClockGen pmClockCan1 = {
.base = {
.derived = &pmClockCan1,
.class = &pmClockClassGen,
.id = PM_CLOCK_CAN1,
},
.parent = NULL,
.users = NULL,
.mux = &can1Mux,
.ctrlAddr = IOU_SLCR_CAN_MIO_CTRL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static const PmClockSel2ClkIn gemTsuSel2ClkIn[] = {
{
.clkIn = &pmClockGemTsuRef.base,
.select = 0U,
}, {
.clkIn = NULL,
.select = 1U,
}, {
.clkIn = &pmClockGemTsuRef.base,
.select = 2U,
}, {
.clkIn = NULL,
.select = 3U,
},
};
static PmClockMux gemTsuMux = {
.inputs = gemTsuSel2ClkIn,
.size = ARRAY_SIZE(gemTsuSel2ClkIn),
.bits = 2U,
.shift = 20U,
};
static PmClockGen pmClockGemTsu = {
.base = {
.derived = &pmClockGemTsu,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM_TSU,
},
.parent = NULL,
.users = NULL,
.mux = &gemTsuMux,
.ctrlAddr = IOU_SLCR_GEM_CLK_CTRL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static const PmClockSel2ClkIn gem0RefSel2ClkIn[] = {
{
.clkIn = &pmClockGem0RefUngated.base,
.select = 0U,
}, {
.clkIn = NULL,
.select = 1U,
},
};
static PmClockMux gem0RefMux = {
.inputs = gem0RefSel2ClkIn,
.size = ARRAY_SIZE(gem0RefSel2ClkIn),
.bits = 1U,
.shift = 1U,
};
static PmClockGen pmClockGem0Ref = {
.base = {
.derived = &pmClockGem0Ref,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM0_REF,
},
.parent = NULL,
.users = NULL,
.mux = &gem0RefMux,
.ctrlAddr = IOU_SLCR_GEM_CLK_CTRL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static const PmClockSel2ClkIn gem1RefSel2ClkIn[] = {
{
.clkIn = &pmClockGem1RefUngated.base,
.select = 0U,
}, {
.clkIn = NULL,
.select = 1U,
},
};
static PmClockMux gem1RefMux = {
.inputs = gem1RefSel2ClkIn,
.size = ARRAY_SIZE(gem1RefSel2ClkIn),
.bits = 1U,
.shift = 6U,
};
static PmClockGen pmClockGem1Ref = {
.base = {
.derived = &pmClockGem1Ref,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM1_REF,
},
.parent = NULL,
.users = NULL,
.mux = &gem1RefMux,
.ctrlAddr = IOU_SLCR_GEM_CLK_CTRL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static const PmClockSel2ClkIn gem2RefSel2ClkIn[] = {
{
.clkIn = &pmClockGem2RefUngated.base,
.select = 0U,
}, {
.clkIn = NULL,
.select = 1U,
},
};
static PmClockMux gem2RefMux = {
.inputs = gem2RefSel2ClkIn,
.size = ARRAY_SIZE(gem2RefSel2ClkIn),
.bits = 1U,
.shift = 11U,
};
static PmClockGen pmClockGem2Ref = {
.base = {
.derived = &pmClockGem2Ref,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM2_REF,
},
.parent = NULL,
.users = NULL,
.mux = &gem2RefMux,
.ctrlAddr = IOU_SLCR_GEM_CLK_CTRL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static const PmClockSel2ClkIn gem3RefSel2ClkIn[] = {
{
.clkIn = &pmClockGem3RefUngated.base,
.select = 0U,
}, {
.clkIn = NULL,
.select = 1U,
},
};
static PmClockMux gem3RefMux = {
.inputs = gem3RefSel2ClkIn,
.size = ARRAY_SIZE(gem3RefSel2ClkIn),
.bits = 1U,
.shift = 16U,
};
static PmClockGen pmClockGem3Ref = {
.base = {
.derived = &pmClockGem3Ref,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM3_REF,
},
.parent = NULL,
.users = NULL,
.mux = &gem3RefMux,
.ctrlAddr = IOU_SLCR_GEM_CLK_CTRL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static PmClockGen pmClockGem0Tx = {
.base = {
.derived = &pmClockGem0Tx,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM0_TX,
},
.parent = &pmClockGem0Ref.base,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRL_APB_GEM0_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE25,
.useCount = 0U,
};
static PmClockGen pmClockGem1Tx = {
.base = {
.derived = &pmClockGem1Tx,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM1_TX,
},
.parent = &pmClockGem1Ref.base,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRL_APB_GEM1_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE25,
.useCount = 0U,
};
static PmClockGen pmClockGem2Tx = {
.base = {
.derived = &pmClockGem2Tx,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM2_TX,
},
.parent = &pmClockGem2Ref.base,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRL_APB_GEM2_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE25,
.useCount = 0U,
};
static PmClockGen pmClockGem3Tx = {
.base = {
.derived = &pmClockGem3Tx,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM3_TX,
},
.parent = &pmClockGem3Ref.base,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRL_APB_GEM3_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE25,
.useCount = 0U,
};
static PmClockGen pmClockGem0Rx = {
.base = {
.derived = &pmClockGem0Rx,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM0_RX,
},
.parent = NULL,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRL_APB_GEM0_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE26,
.useCount = 0U,
};
static PmClockGen pmClockGem1Rx = {
.base = {
.derived = &pmClockGem1Rx,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM1_RX,
},
.parent = NULL,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRL_APB_GEM1_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE26,
.useCount = 0U,
};
static PmClockGen pmClockGem2Rx = {
.base = {
.derived = &pmClockGem2Rx,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM2_RX,
},
.parent = NULL,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRL_APB_GEM2_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE26,
.useCount = 0U,
};
static PmClockGen pmClockGem3Rx = {
.base = {
.derived = &pmClockGem3Rx,
.class = &pmClockClassGen,
.id = PM_CLOCK_GEM3_RX,
},
.parent = NULL,
.users = NULL,
.mux = NULL,
.ctrlAddr = CRL_APB_GEM3_REF_CTRL,
.ctrlVal = 0U,
.type = PM_CLOCK_TYPE_GATE26,
.useCount = 0U,
};
static const PmClockSel2ClkIn wdtSel2ClkIn[] = {
{
.clkIn = &pmClockTopSwLsBus.base,
.select = 0U,
}, {
.clkIn = NULL,
.select = 1U,
},
};
static PmClockMux wdtMux = {
.inputs = wdtSel2ClkIn,
.size = ARRAY_SIZE(wdtSel2ClkIn),
.bits = 1U,
.shift = 0U,
};
static PmClockGen pmClockFpdWdt = {
.base = {
.derived = &pmClockFpdWdt,
.class = &pmClockClassGen,
.id = PM_CLOCK_WDT,
},
.parent = NULL,
.users = NULL,
.mux = &wdtMux,
.ctrlAddr = FPD_SLCR_WDT_CLK_SEL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
static PmClockGen pmClockLpdWdt = {
.base = {
.derived = &pmClockLpdWdt,
.class = &pmClockClassGen,
.id = PM_CLOCK_LPD_WDT,
},
.parent = NULL,
.users = NULL,
.mux = &wdtMux,
.ctrlAddr = IOU_SLCR_WDT_CLK_SEL,
.ctrlVal = 0U,
.type = 0U,
.useCount = 0U,
};
#ifdef ENABLE_POS
static PmClockGen* pmDdrClocks [] = {
&pmClockDdr,
&pmClockTopSwMain,
&pmClockTopSwLsBus,
};
#endif
static PmClock* pmClocks[] = {
&pmClockIOpll.base,
&pmClockRpll.base,
&pmClockApll.base,
&pmClockDpll.base,
&pmClockVpll.base,
&pmClockIOpllToFpd.base,
&pmClockRpllToFpd.base,
&pmClockDpllToLpd.base,
&pmClockVpllToLpd.base,
&pmClockAcpu.base,
&pmClockAcpuFull.base,
&pmClockAcpuHalf.base,
&pmClockDbgTrace.base,
&pmClockDbgFpd.base,
&pmClockDpVideo.base,
&pmClockDpAudio.base,
&pmClockDpStc.base,
&pmClockDdr.base,
&pmClockGpu.base,
&pmClockGpuPp0.base,
&pmClockGpuPp1.base,
&pmClockSata.base,
&pmClockPcie.base,
&pmClockGdma.base,
&pmClockDpDma.base,
&pmClockTopSwMain.base,
&pmClockTopSwLsBus.base,
&pmClockDbgTstmp.base,
&pmClockUsb3Dual.base,
&pmClockGem0RefUngated.base,
&pmClockGem1RefUngated.base,
&pmClockGem2RefUngated.base,
&pmClockGem3RefUngated.base,
&pmClockUsb0Bus.base,
&pmClockUsb1Bus.base,
&pmClockQSpi.base,
&pmClockSdio0.base,
&pmClockSdio1.base,
&pmClockUart0.base,
&pmClockUart1.base,
&pmClockSpi0.base,
&pmClockSpi1.base,
&pmClockCan0Ref.base,
&pmClockCan1Ref.base,
&pmClockCpuR5.base,
&pmClockCpuR5Core.base,
&pmClockIouSwitch.base,
&pmClockCsuPll.base,
&pmClockPcap.base,
&pmClockLpdSwitch.base,
&pmClockLpdLsBus.base,
&pmClockDbgLpd.base,
&pmClockNand.base,
&pmClockAdma.base,
&pmClockPl0.base,
&pmClockPl1.base,
&pmClockPl2.base,
&pmClockPl3.base,
&pmClockGemTsuRef.base,
&pmClockDll.base,
&pmClockAms.base,
&pmClockI2C0.base,
&pmClockI2C1.base,
&pmClockTimeStamp.base,
&pmClockCan0.base,
&pmClockCan1.base,
&pmClockCan0Mio.base,
&pmClockCan1Mio.base,
&pmClockGemTsu.base,
&pmClockGem0Ref.base,
&pmClockGem1Ref.base,
&pmClockGem2Ref.base,
&pmClockGem3Ref.base,
&pmClockGem0Tx.base,
&pmClockGem1Tx.base,
&pmClockGem2Tx.base,
&pmClockGem3Tx.base,
&pmClockGem0Rx.base,
&pmClockGem1Rx.base,
&pmClockGem2Rx.base,
&pmClockGem3Rx.base,
&pmClockFpdWdt.base,
&pmClockLpdWdt.base,
};
static PmClockHandle pmClockHandles[] = {
CONNECT(pmClockAcpu, pmPowerIslandApu_g.node),
CONNECT(pmClockAcpuHalf, pmPowerIslandApu_g.node),
CONNECT(pmClockAcpuFull, pmPowerIslandApu_g.node),
CONNECT(pmClockDpVideo, pmSlaveDP_g.node),
CONNECT(pmClockDpAudio, pmSlaveDP_g.node),
CONNECT(pmClockDpStc, pmSlaveDP_g.node),
CONNECT(pmClockDpDma, pmSlaveDP_g.node),
CONNECT(pmClockDdr, pmSlaveDdr_g.node),
CONNECT(pmClockTopSwMain, pmSlaveDdr_g.node),
CONNECT(pmClockTopSwLsBus, pmSlaveDdr_g.node),
CONNECT(pmClockGpu, pmSlaveGpu_g.node),
CONNECT(pmClockGpuPp0, pmSlaveGpu_g.node),
CONNECT(pmClockGpuPp1, pmSlaveGpu_g.node),
CONNECT(pmClockSata, pmSlaveSata_g.node),
CONNECT(pmClockPcie, pmSlavePcie_g.node),
CONNECT(pmClockGdma, pmSlaveGdma_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveGdma_g.node),
CONNECT(pmClockGem0RefUngated, pmSlaveEth0_g.node),
CONNECT(pmClockGem0Ref, pmSlaveEth0_g.node),
CONNECT(pmClockGem0Tx, pmSlaveEth0_g.node),
CONNECT(pmClockGem0Rx, pmSlaveEth0_g.node),
CONNECT(pmClockGemTsu, pmSlaveEth0_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveEth0_g.node),
CONNECT(pmClockGem1RefUngated, pmSlaveEth1_g.node),
CONNECT(pmClockGem1Ref, pmSlaveEth1_g.node),
CONNECT(pmClockGem1Tx, pmSlaveEth1_g.node),
CONNECT(pmClockGem1Rx, pmSlaveEth1_g.node),
CONNECT(pmClockGemTsu, pmSlaveEth1_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveEth1_g.node),
CONNECT(pmClockGem2RefUngated, pmSlaveEth2_g.node),
CONNECT(pmClockGem2Ref, pmSlaveEth2_g.node),
CONNECT(pmClockGem2Tx, pmSlaveEth2_g.node),
CONNECT(pmClockGem2Rx, pmSlaveEth2_g.node),
CONNECT(pmClockGemTsu, pmSlaveEth2_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveEth2_g.node),
CONNECT(pmClockGem3RefUngated, pmSlaveEth3_g.node),
CONNECT(pmClockGem3Ref, pmSlaveEth3_g.node),
CONNECT(pmClockGem3Tx, pmSlaveEth3_g.node),
CONNECT(pmClockGem3Rx, pmSlaveEth3_g.node),
CONNECT(pmClockGemTsu, pmSlaveEth3_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveEth3_g.node),
CONNECT(pmClockUsb3Dual, pmSlaveUsb0_g.slv.node),
CONNECT(pmClockUsb0Bus, pmSlaveUsb0_g.slv.node),
CONNECT(pmClockUsb3Dual, pmSlaveUsb1_g.slv.node),
CONNECT(pmClockUsb1Bus, pmSlaveUsb1_g.slv.node),
CONNECT(pmClockQSpi, pmSlaveQSpi_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveQSpi_g.node),
CONNECT(pmClockSdio0, pmSlaveSD0_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveSD0_g.node),
CONNECT(pmClockDll, pmSlaveSD0_g.node),
CONNECT(pmClockSdio1, pmSlaveSD1_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveSD1_g.node),
CONNECT(pmClockDll, pmSlaveSD1_g.node),
CONNECT(pmClockUart0, pmSlaveUart0_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveUart0_g.node),
CONNECT(pmClockUart1, pmSlaveUart1_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveUart1_g.node),
CONNECT(pmClockSpi0, pmSlaveSpi0_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveSpi0_g.node),
CONNECT(pmClockSpi1, pmSlaveSpi1_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveSpi1_g.node),
CONNECT(pmClockCan0, pmSlaveCan0_g.node),
CONNECT(pmClockCan0Ref, pmSlaveCan0_g.node),
CONNECT(pmClockCan0Mio, pmSlaveCan0_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveCan0_g.node),
CONNECT(pmClockCan1, pmSlaveCan1_g.node),
CONNECT(pmClockCan1Ref, pmSlaveCan1_g.node),
CONNECT(pmClockCan1Mio, pmSlaveCan1_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveCan1_g.node),
CONNECT(pmClockCpuR5, pmPowerIslandRpu_g.power.node),
CONNECT(pmClockCpuR5Core, pmPowerIslandRpu_g.power.node),
CONNECT(pmClockCsuPll, pmSlavePcap_g.node),
CONNECT(pmClockPcap, pmSlavePcap_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveTtc0_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveTtc1_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveTtc2_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveTtc3_g.node),
CONNECT(pmClockNand, pmSlaveNand_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveNand_g.node),
CONNECT(pmClockAdma, pmSlaveAdma_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveAdma_g.node),
CONNECT(pmClockPl0, pmSlavePl_g.node),
CONNECT(pmClockPl1, pmSlavePl_g.node),
CONNECT(pmClockPl2, pmSlavePl_g.node),
CONNECT(pmClockPl3, pmSlavePl_g.node),
CONNECT(pmClockI2C0, pmSlaveI2C0_g.node),
CONNECT(pmClockI2C1, pmSlaveI2C1_g.node),
CONNECT(pmClockFpdWdt, pmSlaveFpdWdt_g.node),
CONNECT(pmClockLpdLsBus, pmSlaveGpio_g.node),
};
/**
* PmClockConstructList() - Link clock handles into clock's/node's lists
*/
void PmClockConstructList(void)
{
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmClockHandles); i++) {
PmClockHandle* ch = &pmClockHandles[i];
/* Add the clock at the beginning of the node's clocks list */
ch->nextClock = ch->node->clocks;
ch->node->clocks = ch;
/* Add the node at the beginning of the clock's users list */
ch->nextNode = ch->clock->users;
ch->clock->users = ch;
}
}
/**
* PmClockInit() - Initialize clock parent pointers according to hardware config
*/
void PmClockInit(void)
{
u32 i;
/* Initialize parents if possible for a particular clock */
for (i = 0U; i < ARRAY_SIZE(pmClocks); i++) {
PmClock* clk = pmClocks[i];
if ((NULL != clk->class) && (NULL != clk->class->ctrl) &&
(NULL != clk->class->ctrl->initParent)) {
clk->class->ctrl->initParent(clk);
}
}
}
/**
* @PmClockIsActive() Check if any clock for a given node is active
* @node Node whose clocks need to be checked
*
* @return XST_SUCCESS if any one clock for given node is active
* XST_FAILURE if all clocks for given node are inactive
*/
s32 PmClockIsActive(PmNode* const node)
{
PmClockHandle* ch = node->clocks;
s32 status = XST_FAILURE;
while (NULL != ch) {
PmClock* clk = &ch->clock->base;
if ((NULL != clk->class) &&
(NULL != clk->class->ctrl) &&
(NULL != clk->class->ctrl->getGate)) {
u8 enable = 0U;
s32 ret = clk->class->ctrl->getGate(clk, &enable);
if (XST_SUCCESS == ret) {
if (1U == enable) {
status = XST_SUCCESS;
goto done;
}
} else {
PmErr("Clock #%lu model\r\n", clk->id);
}
}
ch = ch->nextClock;
}
done:
return status;
}
/**
* @PmClockSave() - Save control register values for clocks used by the node
* @node Node whose clock control regs need to be saved
*/
void PmClockSave(PmNode* const node)
{
PmClockHandle* ch = node->clocks;
while (NULL != ch) {
ch->clock->ctrlVal = XPfw_Read32(ch->clock->ctrlAddr);
ch = ch->nextClock;
}
}
/**
* PmClockRestore() - Restore control register values for clocks of the node
* @node Node whose clock control registers need to be restored
*/
void PmClockRestore(PmNode* const node)
{
PmClockHandle* ch = node->clocks;
while (NULL != ch) {
/* Restore the clock configuration if needed */
if (0U != ch->clock->ctrlVal) {
XPfw_Write32(ch->clock->ctrlAddr, ch->clock->ctrlVal);
}
ch = ch->nextClock;
}
}
/**
* PmClockRequest() - Request clocks used by the given node
* @node Node whose clocks need to be requested
* @return XST_SUCCESS if the request is processed correctly, or error code
* if a PLL parent needed to be locked and the locking has failed.
* @note The dependency toward a PLL parent is automatically resolved
*/
s32 PmClockRequest(PmNode* const node)
{
PmClockHandle* ch = node->clocks;
s32 status = XST_SUCCESS;
if (0U != (NODE_LOCKED_CLOCK_FLAG & node->flags)) {
PmWarn("%s double request\r\n", node->name);
goto done;
}
while (NULL != ch) {
PmClockRequestInt(&ch->clock->base);
ch = ch->nextClock;
}
node->flags |= NODE_LOCKED_CLOCK_FLAG;
done:
return status;
}
/**
* PmClockRelease() - Release clocks used by the given node
* @node Node whose clocks are released
*
* @note If a PLL parent of a released clock have no other users, the
* PM framework will suspend that PLL.
*/
void PmClockRelease(PmNode* const node)
{
PmClockHandle* ch = node->clocks;
if (0U == (NODE_LOCKED_CLOCK_FLAG & node->flags)) {
PmWarn("%s double release\r\n", node->name);
goto done;
}
while (NULL != ch) {
PmClockReleaseInt(&ch->clock->base);
ch = ch->nextClock;
}
node->flags &= ~NODE_LOCKED_CLOCK_FLAG;
done:
return;
}
/**
* PmClockGetById() - Get clock structure based on clock ID
* @clockId ID of the clock to get
*
* @return Pointer to the clock structure if found, otherwise NULL
*/
PmClock* PmClockGetById(const u32 clockId)
{
u32 i;
PmClock* clock = NULL;
for (i = 0U; i < ARRAY_SIZE(pmClocks); i++) {
if (clockId == pmClocks[i]->id) {
clock = pmClocks[i];
break;
}
}
return clock;
}
/**
* PmClockCheckForCtrl() - Common function for checking validity
* @clock Clock to be checked
*
* @return XST_INVALID_PARAM if clock argument in NULL
* XST_SUCCESS if clock is valid, has class and control methods
* XST_NO_FEATURE otherwise
*/
static s32 PmClockCheckForCtrl(const PmClock* const clock)
{
s32 status = XST_SUCCESS;
if (NULL == clock) {
status = XST_INVALID_PARAM;
goto done;
}
if ((NULL == clock->class) || (NULL == clock->class->ctrl)) {
status = XST_NO_FEATURE;
goto done;
}
done:
return status;
}
/**
* PmClockMuxSetParent() - Configure clock mux
* @clock Pointer to the clock structure
* @select Mux select value
*
* @return XST_SUCCESS if the mux is configured
* XST_NO_FEATURE if the clock has no mux
* XST_INVALID_PARAM if select value is invalid
*/
s32 PmClockMuxSetParent(PmClock* const clock, const u32 select)
{
s32 status = PmClockCheckForCtrl(clock);
if ((XST_SUCCESS != status) || (NULL == clock->class->ctrl->setParent)) {
status = XST_NO_FEATURE;
goto done;
}
status = clock->class->ctrl->setParent(clock, select);
done:
return status;
}
/**
* PmClockMuxGetParent() - Get clock parent (mux select value)
* @clock Pointer to the target clock
* @select Location to store mux select value of the current parent
*
* @return Status of getting the parent: XST_SUCCESS if the parent pointer
* is stored into 'parent' or error code
*/
s32 PmClockMuxGetParent(PmClock* const clock, u32 *const select)
{
s32 status = PmClockCheckForCtrl(clock);
if ((XST_SUCCESS != status) || (NULL == clock->class->ctrl->getParent)) {
status = XST_NO_FEATURE;
goto done;
}
status = clock->class->ctrl->getParent(clock, select);
done:
return status;
}
/**
* PmClockGateSetState() - Activate/gate the clock
* @clock Pointer to the clock structure
* @enable 1=enable the clock, 0=disable the clock
*
* @return XST_SUCCESS if the clock is configured
* XST_NO_FEATURE if the clock has no gate
*/
s32 PmClockGateSetState(PmClock* const clock, const u8 enable)
{
s32 status = PmClockCheckForCtrl(clock);
if ((XST_SUCCESS != status) || (NULL == clock->class->ctrl->setGate)) {
status = XST_NO_FEATURE;
goto done;
}
#if ((STDOUT_BASEADDRESS == XPAR_PSU_UART_0_BASEADDR) && defined(DEBUG_MODE))
if (&pmClockUart0.base == clock) {
goto done;
}
#endif
#if ((STDOUT_BASEADDRESS == XPAR_PSU_UART_1_BASEADDR) && defined(DEBUG_MODE))
if (&pmClockUart1.base == clock) {
goto done;
}
#endif
/*
* This is added because equivalent functionality added in commit
* 2a1b15d8b2 has been removed from PmMmioWrite in pm_core.c
*/
if (&pmClockAms.base == clock) {
goto done;
}
status = clock->class->ctrl->setGate(clock, enable);
done:
return status;
}
/**
* PmClockGateGetState() - Get state of the clock gate
* @clock Pointer to the target clock
* @enable Location where the state will be returned
*
* @return XST_SUCCESS if the clock state is get/enable location is updated
* XST_NO_FEATURE if the clock has no gate
*/
s32 PmClockGateGetState(PmClock* const clock, u8* const enable)
{
s32 status = PmClockCheckForCtrl(clock);
if ((XST_SUCCESS != status) || (NULL == clock->class->ctrl->getGate)) {
status = XST_NO_FEATURE;
goto done;
}
status = clock->class->ctrl->getGate(clock, enable);
done:
return status;
}
/**
* PmClockDividerSetVal() - Set divider of the clock
* @clock Pointer to the target clock
* @divId Identifier for the divider to be set
* @val Divider value to be set
*
* @return Status of performing the operation:
* XST_SUCCESS the divider is set as requested
* XST_NO_FEATURE the target clock has no divider
* XST_INVALID_PARAM if given clock is NULL
*/
s32 PmClockDividerSetVal(PmClock* const clock, const u32 divId, const u32 val)
{
s32 status = PmClockCheckForCtrl(clock);
if ((XST_SUCCESS != status) || (NULL == clock->class->ctrl->setDivider)) {
status = XST_NO_FEATURE;
goto done;
}
status = clock->class->ctrl->setDivider(clock, divId, val);
done:
return status;
}
/**
* PmClockDividerGetVal() - Get divider of the clock
* @clock Pointer to the target clock
* @divId Identifier of the clock's divider
* @val Location where the divider value needs to be stored
*
* @return Status of performing the operation:
* XST_SUCCESS the divider location is updated (got divider)
* XST_NO_FEATURE the target clock has no divider
* XST_INVALID_PARAM if given clock is NULL
*/
s32 PmClockDividerGetVal(PmClock* const clock, const u32 divId, u32* const val)
{
s32 status = PmClockCheckForCtrl(clock);
if ((XST_SUCCESS != status) || (NULL == clock->class->ctrl->getDivider)) {
status = XST_NO_FEATURE;
goto done;
}
status = clock->class->ctrl->getDivider(clock, divId, val);
done:
return status;
}
/**
* PmClockCheckPermission() - Check permission for master to control the clock
* @clock Pointer to the target clock
* @ipiMask Master's IPI mask
*
* @return Status of performing the check:
* XST_SUCCESS the permission is granted
* XST_PM_NO_ACCESS if control is not allowed
*/
s32 PmClockCheckPermission(const PmClock* const clock, const u32 ipiMask)
{
s32 status = XST_SUCCESS;
u32 perms;
if ((NULL == clock) || (NULL == clock->class) ||
(NULL == clock->class->getPerms)) {
status = XST_PM_NO_ACCESS;
goto done;
}
perms = clock->class->getPerms(clock);
/*
* Access is not allowed if master is not permissible or the resource
* is shared (multiple masters are permissible)
*/
if ((0U == (perms & ipiMask)) ||( __builtin_popcount(perms) > 1)) {
status = XST_PM_NO_ACCESS;
goto done;
}
done:
return status;
}
#ifdef ENABLE_POS
/**
* PmClockRestoreDdr() - Restore state of clocks related to DDR node
*/
void PmClockRestoreDdr(void)
{
u32 i;
for (i = 0U; i < ARRAY_SIZE(pmDdrClocks); i++) {
PmClockRequestInt(&pmDdrClocks[i]->base);
XPfw_Write32(pmDdrClocks[i]->ctrlAddr, pmDdrClocks[i]->ctrlVal);
}
}
#endif
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/csu.h
/******************************************************************************
* Copyright (c) 2016 -2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _CSU_H_
#define _CSU_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* CSU Base Address
*/
#define CSU_BASEADDR 0XFFCA0000
#define CSU_VERSION_EMPTY_SHIFT 20
#define CSU_VERSION_PL_STATE_SHIFT 29
/**
* Register: CSU_STATUS
*/
#define CSU_STATUS ( ( CSU_BASEADDR ) + 0X00000000 )
#define CSU_STATUS_UNUSED_SHIFT 2
#define CSU_STATUS_UNUSED_WIDTH 30
#define CSU_STATUS_UNUSED_MASK 0XFFFFFFFC
#define CSU_STATUS_BOOT_ENC_SHIFT 1
#define CSU_STATUS_BOOT_ENC_WIDTH 1
#define CSU_STATUS_BOOT_ENC_MASK 0X00000002
#define CSU_STATUS_BOOT_AUTH_SHIFT 0
#define CSU_STATUS_BOOT_AUTH_WIDTH 1
#define CSU_STATUS_BOOT_AUTH_MASK 0X00000001
/**
* Register: CSU_CTRL
*/
#define CSU_CTRL ( ( CSU_BASEADDR ) + 0X00000004 )
#define CSU_CTRL_SLVERR_ENABLE_SHIFT 4
#define CSU_CTRL_SLVERR_ENABLE_WIDTH 1
#define CSU_CTRL_SLVERR_ENABLE_MASK 0X00000010
#define CSU_CTRL_CSU_CLK_SEL_SHIFT 0
#define CSU_CTRL_CSU_CLK_SEL_WIDTH 1
#define CSU_CTRL_CSU_CLK_SEL_MASK 0X00000001
/**
* Register: CSU_SSS_CFG
*/
#define CSU_SSS_CFG ( ( CSU_BASEADDR ) + 0X00000008 )
#define CSU_SSS_CFG_PSTP_SSS_SHIFT 16
#define CSU_SSS_CFG_PSTP_SSS_WIDTH 4
#define CSU_SSS_CFG_PSTP_SSS_MASK 0X000F0000
#define CSU_SSS_CFG_SHA_SSS_SHIFT 12
#define CSU_SSS_CFG_SHA_SSS_WIDTH 4
#define CSU_SSS_CFG_SHA_SSS_MASK 0X0000F000
#define CSU_SSS_CFG_AES_SSS_SHIFT 8
#define CSU_SSS_CFG_AES_SSS_WIDTH 4
#define CSU_SSS_CFG_AES_SSS_MASK 0X00000F00
#define CSU_SSS_CFG_DMA_SSS_SHIFT 4
#define CSU_SSS_CFG_DMA_SSS_WIDTH 4
#define CSU_SSS_CFG_DMA_SSS_MASK 0X000000F0
#define CSU_SSS_CFG_PCAP_SSS_SHIFT 0
#define CSU_SSS_CFG_PCAP_SSS_WIDTH 4
#define CSU_SSS_CFG_PCAP_SSS_MASK 0X0000000F
/**
* Register: CSU_DMA_RESET
*/
#define CSU_DMA_RESET ( ( CSU_BASEADDR ) + 0X0000000C )
#define CSU_DMA_RESET_RESET_SHIFT 0
#define CSU_DMA_RESET_RESET_WIDTH 1
#define CSU_DMA_RESET_RESET_MASK 0X00000001
/**
* Register: CSU_MULTI_BOOT
*/
#define CSU_MULTI_BOOT ( ( CSU_BASEADDR ) + 0X00000010 )
#define CSU_MULTI_BOOT_SSSS_MULTI_BOOT_ADDR_SHIFT 0
#define CSU_MULTI_BOOT_SSSS_MULTI_BOOT_ADDR_WIDTH 32
#define CSU_MULTI_BOOT_SSSS_MULTI_BOOT_ADDR_MASK 0XFFFFFFFF
/**
* Register: CSU_TAMPER_TRIG
*/
#define CSU_TAMPER_TRIG ( ( CSU_BASEADDR ) + 0X00000014 )
#define CSU_TAMPER_TRIG_TAMPER_SHIFT 0
#define CSU_TAMPER_TRIG_TAMPER_WIDTH 1
#define CSU_TAMPER_TRIG_TAMPER_MASK 0X00000001
/**
* Register: CSU_FT_STATUS
*/
#define CSU_FT_STATUS ( ( CSU_BASEADDR ) + 0X00000018 )
#define CSU_FT_STATUS_R_UE_SHIFT 31
#define CSU_FT_STATUS_R_UE_WIDTH 1
#define CSU_FT_STATUS_R_UE_MASK 0X80000000
#define CSU_FT_STATUS_R_VOTER_ERROR_SHIFT 30
#define CSU_FT_STATUS_R_VOTER_ERROR_WIDTH 1
#define CSU_FT_STATUS_R_VOTER_ERROR_MASK 0X40000000
#define CSU_FT_STATUS_R_COMP_ERR_23_SHIFT 29
#define CSU_FT_STATUS_R_COMP_ERR_23_WIDTH 1
#define CSU_FT_STATUS_R_COMP_ERR_23_MASK 0X20000000
#define CSU_FT_STATUS_R_COMP_ERR_13_SHIFT 28
#define CSU_FT_STATUS_R_COMP_ERR_13_WIDTH 1
#define CSU_FT_STATUS_R_COMP_ERR_13_MASK 0X10000000
#define CSU_FT_STATUS_R_COMP_ERR_12_SHIFT 27
#define CSU_FT_STATUS_R_COMP_ERR_12_WIDTH 1
#define CSU_FT_STATUS_R_COMP_ERR_12_MASK 0X08000000
#define CSU_FT_STATUS_R_MISMATCH_23_A_SHIFT 26
#define CSU_FT_STATUS_R_MISMATCH_23_A_WIDTH 1
#define CSU_FT_STATUS_R_MISMATCH_23_A_MASK 0X04000000
#define CSU_FT_STATUS_R_MISMATCH_13_A_SHIFT 25
#define CSU_FT_STATUS_R_MISMATCH_13_A_WIDTH 1
#define CSU_FT_STATUS_R_MISMATCH_13_A_MASK 0X02000000
#define CSU_FT_STATUS_R_MISMATCH_12_A_SHIFT 24
#define CSU_FT_STATUS_R_MISMATCH_12_A_WIDTH 1
#define CSU_FT_STATUS_R_MISMATCH_12_A_MASK 0X01000000
#define CSU_FT_STATUS_R_FT_ST_MISMATCH_SHIFT 23
#define CSU_FT_STATUS_R_FT_ST_MISMATCH_WIDTH 1
#define CSU_FT_STATUS_R_FT_ST_MISMATCH_MASK 0X00800000
#define CSU_FT_STATUS_R_CPU_ID_MISMATCH_SHIFT 22
#define CSU_FT_STATUS_R_CPU_ID_MISMATCH_WIDTH 1
#define CSU_FT_STATUS_R_CPU_ID_MISMATCH_MASK 0X00400000
#define CSU_FT_STATUS_R_SLEEP_RESET_SHIFT 19
#define CSU_FT_STATUS_R_SLEEP_RESET_WIDTH 1
#define CSU_FT_STATUS_R_SLEEP_RESET_MASK 0X00080000
#define CSU_FT_STATUS_R_MISMATCH_23_B_SHIFT 18
#define CSU_FT_STATUS_R_MISMATCH_23_B_WIDTH 1
#define CSU_FT_STATUS_R_MISMATCH_23_B_MASK 0X00040000
#define CSU_FT_STATUS_R_MISMATCH_13_B_SHIFT 17
#define CSU_FT_STATUS_R_MISMATCH_13_B_WIDTH 1
#define CSU_FT_STATUS_R_MISMATCH_13_B_MASK 0X00020000
#define CSU_FT_STATUS_R_MISMATCH_12_B_SHIFT 16
#define CSU_FT_STATUS_R_MISMATCH_12_B_WIDTH 1
#define CSU_FT_STATUS_R_MISMATCH_12_B_MASK 0X00010000
#define CSU_FT_STATUS_N_UE_SHIFT 15
#define CSU_FT_STATUS_N_UE_WIDTH 1
#define CSU_FT_STATUS_N_UE_MASK 0X00008000
#define CSU_FT_STATUS_N_VOTER_ERROR_SHIFT 14
#define CSU_FT_STATUS_N_VOTER_ERROR_WIDTH 1
#define CSU_FT_STATUS_N_VOTER_ERROR_MASK 0X00004000
#define CSU_FT_STATUS_N_COMP_ERR_23_SHIFT 13
#define CSU_FT_STATUS_N_COMP_ERR_23_WIDTH 1
#define CSU_FT_STATUS_N_COMP_ERR_23_MASK 0X00002000
#define CSU_FT_STATUS_N_COMP_ERR_13_SHIFT 12
#define CSU_FT_STATUS_N_COMP_ERR_13_WIDTH 1
#define CSU_FT_STATUS_N_COMP_ERR_13_MASK 0X00001000
#define CSU_FT_STATUS_N_COMP_ERR_12_SHIFT 11
#define CSU_FT_STATUS_N_COMP_ERR_12_WIDTH 1
#define CSU_FT_STATUS_N_COMP_ERR_12_MASK 0X00000800
#define CSU_FT_STATUS_N_MISMATCH_23_A_SHIFT 10
#define CSU_FT_STATUS_N_MISMATCH_23_A_WIDTH 1
#define CSU_FT_STATUS_N_MISMATCH_23_A_MASK 0X00000400
#define CSU_FT_STATUS_N_MISMATCH_13_A_SHIFT 9
#define CSU_FT_STATUS_N_MISMATCH_13_A_WIDTH 1
#define CSU_FT_STATUS_N_MISMATCH_13_A_MASK 0X00000200
#define CSU_FT_STATUS_N_MISMATCH_12_A_SHIFT 8
#define CSU_FT_STATUS_N_MISMATCH_12_A_WIDTH 1
#define CSU_FT_STATUS_N_MISMATCH_12_A_MASK 0X00000100
#define CSU_FT_STATUS_N_FT_ST_MISMATCH_SHIFT 7
#define CSU_FT_STATUS_N_FT_ST_MISMATCH_WIDTH 1
#define CSU_FT_STATUS_N_FT_ST_MISMATCH_MASK 0X00000080
#define CSU_FT_STATUS_N_CPU_ID_MISMATCH_SHIFT 6
#define CSU_FT_STATUS_N_CPU_ID_MISMATCH_WIDTH 1
#define CSU_FT_STATUS_N_CPU_ID_MISMATCH_MASK 0X00000040
#define CSU_FT_STATUS_N_SLEEP_RESET_SHIFT 3
#define CSU_FT_STATUS_N_SLEEP_RESET_WIDTH 1
#define CSU_FT_STATUS_N_SLEEP_RESET_MASK 0X00000008
#define CSU_FT_STATUS_N_MISMATCH_23_B_SHIFT 2
#define CSU_FT_STATUS_N_MISMATCH_23_B_WIDTH 1
#define CSU_FT_STATUS_N_MISMATCH_23_B_MASK 0X00000004
#define CSU_FT_STATUS_N_MISMATCH_13_B_SHIFT 1
#define CSU_FT_STATUS_N_MISMATCH_13_B_WIDTH 1
#define CSU_FT_STATUS_N_MISMATCH_13_B_MASK 0X00000002
#define CSU_FT_STATUS_N_MISMATCH_12_B_SHIFT 0
#define CSU_FT_STATUS_N_MISMATCH_12_B_WIDTH 1
#define CSU_FT_STATUS_N_MISMATCH_12_B_MASK 0X00000001
/**
* Register: CSU_ISR
*/
#define CSU_ISR ( ( CSU_BASEADDR ) + 0X00000020 )
#define CSU_ISR_UNUSED31_SHIFT 31
#define CSU_ISR_UNUSED31_WIDTH 1
#define CSU_ISR_UNUSED31_MASK 0X80000000
#define CSU_ISR_UNUSED30_SHIFT 30
#define CSU_ISR_UNUSED30_WIDTH 1
#define CSU_ISR_UNUSED30_MASK 0X40000000
#define CSU_ISR_UNUSED29_SHIFT 29
#define CSU_ISR_UNUSED29_WIDTH 1
#define CSU_ISR_UNUSED29_MASK 0X20000000
#define CSU_ISR_UNUSED28_SHIFT 28
#define CSU_ISR_UNUSED28_WIDTH 1
#define CSU_ISR_UNUSED28_MASK 0X10000000
#define CSU_ISR_UNUSED27_SHIFT 27
#define CSU_ISR_UNUSED27_WIDTH 1
#define CSU_ISR_UNUSED27_MASK 0X08000000
#define CSU_ISR_UNUSED26_SHIFT 26
#define CSU_ISR_UNUSED26_WIDTH 1
#define CSU_ISR_UNUSED26_MASK 0X04000000
#define CSU_ISR_UNUSED25_SHIFT 25
#define CSU_ISR_UNUSED25_WIDTH 1
#define CSU_ISR_UNUSED25_MASK 0X02000000
#define CSU_ISR_UNUSED24_SHIFT 24
#define CSU_ISR_UNUSED24_WIDTH 1
#define CSU_ISR_UNUSED24_MASK 0X01000000
#define CSU_ISR_UNUSED23_SHIFT 23
#define CSU_ISR_UNUSED23_WIDTH 1
#define CSU_ISR_UNUSED23_MASK 0X00800000
#define CSU_ISR_UNUSED22_SHIFT 22
#define CSU_ISR_UNUSED22_WIDTH 1
#define CSU_ISR_UNUSED22_MASK 0X00400000
#define CSU_ISR_UNUSED21_SHIFT 21
#define CSU_ISR_UNUSED21_WIDTH 1
#define CSU_ISR_UNUSED21_MASK 0X00200000
#define CSU_ISR_UNUSED20_SHIFT 20
#define CSU_ISR_UNUSED20_WIDTH 1
#define CSU_ISR_UNUSED20_MASK 0X00100000
#define CSU_ISR_UNUSED19_SHIFT 19
#define CSU_ISR_UNUSED19_WIDTH 1
#define CSU_ISR_UNUSED19_MASK 0X00080000
#define CSU_ISR_UNUSED18_SHIFT 18
#define CSU_ISR_UNUSED18_WIDTH 1
#define CSU_ISR_UNUSED18_MASK 0X00040000
#define CSU_ISR_UNUSED17_SHIFT 17
#define CSU_ISR_UNUSED17_WIDTH 1
#define CSU_ISR_UNUSED17_MASK 0X00020000
#define CSU_ISR_UNUSED16_SHIFT 16
#define CSU_ISR_UNUSED16_WIDTH 1
#define CSU_ISR_UNUSED16_MASK 0X00010000
#define CSU_ISR_CSU_PL_ISO_SHIFT 15
#define CSU_ISR_CSU_PL_ISO_WIDTH 1
#define CSU_ISR_CSU_PL_ISO_MASK 0X00008000
#define CSU_ISR_CSU_RAM_ECC_ERROR_SHIFT 14
#define CSU_ISR_CSU_RAM_ECC_ERROR_WIDTH 1
#define CSU_ISR_CSU_RAM_ECC_ERROR_MASK 0X00004000
#define CSU_ISR_TAMPER_SHIFT 13
#define CSU_ISR_TAMPER_WIDTH 1
#define CSU_ISR_TAMPER_MASK 0X00002000
#define CSU_ISR_PUF_ACC_ERROR_SHIFT 12
#define CSU_ISR_PUF_ACC_ERROR_WIDTH 1
#define CSU_ISR_PUF_ACC_ERROR_MASK 0X00001000
#define CSU_ISR_APB_SLVERR_SHIFT 11
#define CSU_ISR_APB_SLVERR_WIDTH 1
#define CSU_ISR_APB_SLVERR_MASK 0X00000800
#define CSU_ISR_TMR_FATAL_SHIFT 10
#define CSU_ISR_TMR_FATAL_WIDTH 1
#define CSU_ISR_TMR_FATAL_MASK 0X00000400
#define CSU_ISR_PL_SEU_ERROR_SHIFT 9
#define CSU_ISR_PL_SEU_ERROR_WIDTH 1
#define CSU_ISR_PL_SEU_ERROR_MASK 0X00000200
#define CSU_ISR_AES_ERROR_SHIFT 8
#define CSU_ISR_AES_ERROR_WIDTH 1
#define CSU_ISR_AES_ERROR_MASK 0X00000100
#define CSU_ISR_PCAP_WR_OVERFLOW_SHIFT 7
#define CSU_ISR_PCAP_WR_OVERFLOW_WIDTH 1
#define CSU_ISR_PCAP_WR_OVERFLOW_MASK 0X00000080
#define CSU_ISR_PCAP_RD_OVERFLOW_SHIFT 6
#define CSU_ISR_PCAP_RD_OVERFLOW_WIDTH 1
#define CSU_ISR_PCAP_RD_OVERFLOW_MASK 0X00000040
#define CSU_ISR_PL_POR_B_SHIFT 5
#define CSU_ISR_PL_POR_B_WIDTH 1
#define CSU_ISR_PL_POR_B_MASK 0X00000020
#define CSU_ISR_PL_INIT_SHIFT 4
#define CSU_ISR_PL_INIT_WIDTH 1
#define CSU_ISR_PL_INIT_MASK 0X00000010
#define CSU_ISR_PL_DONE_SHIFT 3
#define CSU_ISR_PL_DONE_WIDTH 1
#define CSU_ISR_PL_DONE_MASK 0X00000008
#define CSU_ISR_SHA_DONE_SHIFT 2
#define CSU_ISR_SHA_DONE_WIDTH 1
#define CSU_ISR_SHA_DONE_MASK 0X00000004
#define CSU_ISR_RSA_DONE_SHIFT 1
#define CSU_ISR_RSA_DONE_WIDTH 1
#define CSU_ISR_RSA_DONE_MASK 0X00000002
#define CSU_ISR_AES_DONE_SHIFT 0
#define CSU_ISR_AES_DONE_WIDTH 1
#define CSU_ISR_AES_DONE_MASK 0X00000001
/**
* Register: CSU_IMR
*/
#define CSU_IMR ( ( CSU_BASEADDR ) + 0X00000024 )
#define CSU_IMR_UNUSED31_SHIFT 31
#define CSU_IMR_UNUSED31_WIDTH 1
#define CSU_IMR_UNUSED31_MASK 0X80000000
#define CSU_IMR_UNUSED30_SHIFT 30
#define CSU_IMR_UNUSED30_WIDTH 1
#define CSU_IMR_UNUSED30_MASK 0X40000000
#define CSU_IMR_UNUSED29_SHIFT 29
#define CSU_IMR_UNUSED29_WIDTH 1
#define CSU_IMR_UNUSED29_MASK 0X20000000
#define CSU_IMR_UNUSED28_SHIFT 28
#define CSU_IMR_UNUSED28_WIDTH 1
#define CSU_IMR_UNUSED28_MASK 0X10000000
#define CSU_IMR_UNUSED27_SHIFT 27
#define CSU_IMR_UNUSED27_WIDTH 1
#define CSU_IMR_UNUSED27_MASK 0X08000000
#define CSU_IMR_UNUSED26_SHIFT 26
#define CSU_IMR_UNUSED26_WIDTH 1
#define CSU_IMR_UNUSED26_MASK 0X04000000
#define CSU_IMR_UNUSED25_SHIFT 25
#define CSU_IMR_UNUSED25_WIDTH 1
#define CSU_IMR_UNUSED25_MASK 0X02000000
#define CSU_IMR_UNUSED24_SHIFT 24
#define CSU_IMR_UNUSED24_WIDTH 1
#define CSU_IMR_UNUSED24_MASK 0X01000000
#define CSU_IMR_UNUSED23_SHIFT 23
#define CSU_IMR_UNUSED23_WIDTH 1
#define CSU_IMR_UNUSED23_MASK 0X00800000
#define CSU_IMR_UNUSED22_SHIFT 22
#define CSU_IMR_UNUSED22_WIDTH 1
#define CSU_IMR_UNUSED22_MASK 0X00400000
#define CSU_IMR_UNUSED21_SHIFT 21
#define CSU_IMR_UNUSED21_WIDTH 1
#define CSU_IMR_UNUSED21_MASK 0X00200000
#define CSU_IMR_UNUSED20_SHIFT 20
#define CSU_IMR_UNUSED20_WIDTH 1
#define CSU_IMR_UNUSED20_MASK 0X00100000
#define CSU_IMR_UNUSED19_SHIFT 19
#define CSU_IMR_UNUSED19_WIDTH 1
#define CSU_IMR_UNUSED19_MASK 0X00080000
#define CSU_IMR_UNUSED18_SHIFT 18
#define CSU_IMR_UNUSED18_WIDTH 1
#define CSU_IMR_UNUSED18_MASK 0X00040000
#define CSU_IMR_UNUSED17_SHIFT 17
#define CSU_IMR_UNUSED17_WIDTH 1
#define CSU_IMR_UNUSED17_MASK 0X00020000
#define CSU_IMR_UNUSED16_SHIFT 16
#define CSU_IMR_UNUSED16_WIDTH 1
#define CSU_IMR_UNUSED16_MASK 0X00010000
#define CSU_IMR_CSU_PL_ISO_SHIFT 15
#define CSU_IMR_CSU_PL_ISO_WIDTH 1
#define CSU_IMR_CSU_PL_ISO_MASK 0X00008000
#define CSU_IMR_CSU_RAM_ECC_ERROR_SHIFT 14
#define CSU_IMR_CSU_RAM_ECC_ERROR_WIDTH 1
#define CSU_IMR_CSU_RAM_ECC_ERROR_MASK 0X00004000
#define CSU_IMR_TAMPER_SHIFT 13
#define CSU_IMR_TAMPER_WIDTH 1
#define CSU_IMR_TAMPER_MASK 0X00002000
#define CSU_IMR_PUF_ACC_ERROR_SHIFT 12
#define CSU_IMR_PUF_ACC_ERROR_WIDTH 1
#define CSU_IMR_PUF_ACC_ERROR_MASK 0X00001000
#define CSU_IMR_APB_SLVERR_SHIFT 11
#define CSU_IMR_APB_SLVERR_WIDTH 1
#define CSU_IMR_APB_SLVERR_MASK 0X00000800
#define CSU_IMR_TMR_FATAL_SHIFT 10
#define CSU_IMR_TMR_FATAL_WIDTH 1
#define CSU_IMR_TMR_FATAL_MASK 0X00000400
#define CSU_IMR_PL_SEU_ERROR_SHIFT 9
#define CSU_IMR_PL_SEU_ERROR_WIDTH 1
#define CSU_IMR_PL_SEU_ERROR_MASK 0X00000200
#define CSU_IMR_AES_ERROR_SHIFT 8
#define CSU_IMR_AES_ERROR_WIDTH 1
#define CSU_IMR_AES_ERROR_MASK 0X00000100
#define CSU_IMR_PCAP_WR_OVERFLOW_SHIFT 7
#define CSU_IMR_PCAP_WR_OVERFLOW_WIDTH 1
#define CSU_IMR_PCAP_WR_OVERFLOW_MASK 0X00000080
#define CSU_IMR_PCAP_RD_OVERFLOW_SHIFT 6
#define CSU_IMR_PCAP_RD_OVERFLOW_WIDTH 1
#define CSU_IMR_PCAP_RD_OVERFLOW_MASK 0X00000040
#define CSU_IMR_PL_POR_B_SHIFT 5
#define CSU_IMR_PL_POR_B_WIDTH 1
#define CSU_IMR_PL_POR_B_MASK 0X00000020
#define CSU_IMR_PL_INIT_SHIFT 4
#define CSU_IMR_PL_INIT_WIDTH 1
#define CSU_IMR_PL_INIT_MASK 0X00000010
#define CSU_IMR_PL_DONE_SHIFT 3
#define CSU_IMR_PL_DONE_WIDTH 1
#define CSU_IMR_PL_DONE_MASK 0X00000008
#define CSU_IMR_SHA_DONE_SHIFT 2
#define CSU_IMR_SHA_DONE_WIDTH 1
#define CSU_IMR_SHA_DONE_MASK 0X00000004
#define CSU_IMR_RSA_DONE_SHIFT 1
#define CSU_IMR_RSA_DONE_WIDTH 1
#define CSU_IMR_RSA_DONE_MASK 0X00000002
#define CSU_IMR_AES_DONE_SHIFT 0
#define CSU_IMR_AES_DONE_WIDTH 1
#define CSU_IMR_AES_DONE_MASK 0X00000001
/**
* Register: CSU_IER
*/
#define CSU_IER ( ( CSU_BASEADDR ) + 0X00000028 )
#define CSU_IER_UNUSED31_SHIFT 31
#define CSU_IER_UNUSED31_WIDTH 1
#define CSU_IER_UNUSED31_MASK 0X80000000
#define CSU_IER_UNUSED30_SHIFT 30
#define CSU_IER_UNUSED30_WIDTH 1
#define CSU_IER_UNUSED30_MASK 0X40000000
#define CSU_IER_UNUSED29_SHIFT 29
#define CSU_IER_UNUSED29_WIDTH 1
#define CSU_IER_UNUSED29_MASK 0X20000000
#define CSU_IER_UNUSED28_SHIFT 28
#define CSU_IER_UNUSED28_WIDTH 1
#define CSU_IER_UNUSED28_MASK 0X10000000
#define CSU_IER_UNUSED27_SHIFT 27
#define CSU_IER_UNUSED27_WIDTH 1
#define CSU_IER_UNUSED27_MASK 0X08000000
#define CSU_IER_UNUSED26_SHIFT 26
#define CSU_IER_UNUSED26_WIDTH 1
#define CSU_IER_UNUSED26_MASK 0X04000000
#define CSU_IER_UNUSED25_SHIFT 25
#define CSU_IER_UNUSED25_WIDTH 1
#define CSU_IER_UNUSED25_MASK 0X02000000
#define CSU_IER_UNUSED24_SHIFT 24
#define CSU_IER_UNUSED24_WIDTH 1
#define CSU_IER_UNUSED24_MASK 0X01000000
#define CSU_IER_UNUSED23_SHIFT 23
#define CSU_IER_UNUSED23_WIDTH 1
#define CSU_IER_UNUSED23_MASK 0X00800000
#define CSU_IER_UNUSED22_SHIFT 22
#define CSU_IER_UNUSED22_WIDTH 1
#define CSU_IER_UNUSED22_MASK 0X00400000
#define CSU_IER_UNUSED21_SHIFT 21
#define CSU_IER_UNUSED21_WIDTH 1
#define CSU_IER_UNUSED21_MASK 0X00200000
#define CSU_IER_UNUSED20_SHIFT 20
#define CSU_IER_UNUSED20_WIDTH 1
#define CSU_IER_UNUSED20_MASK 0X00100000
#define CSU_IER_UNUSED19_SHIFT 19
#define CSU_IER_UNUSED19_WIDTH 1
#define CSU_IER_UNUSED19_MASK 0X00080000
#define CSU_IER_UNUSED18_SHIFT 18
#define CSU_IER_UNUSED18_WIDTH 1
#define CSU_IER_UNUSED18_MASK 0X00040000
#define CSU_IER_UNUSED17_SHIFT 17
#define CSU_IER_UNUSED17_WIDTH 1
#define CSU_IER_UNUSED17_MASK 0X00020000
#define CSU_IER_UNUSED16_SHIFT 16
#define CSU_IER_UNUSED16_WIDTH 1
#define CSU_IER_UNUSED16_MASK 0X00010000
#define CSU_IER_CSU_PL_ISO_SHIFT 15
#define CSU_IER_CSU_PL_ISO_WIDTH 1
#define CSU_IER_CSU_PL_ISO_MASK 0X00008000
#define CSU_IER_CSU_RAM_ECC_ERROR_SHIFT 14
#define CSU_IER_CSU_RAM_ECC_ERROR_WIDTH 1
#define CSU_IER_CSU_RAM_ECC_ERROR_MASK 0X00004000
#define CSU_IER_TAMPER_SHIFT 13
#define CSU_IER_TAMPER_WIDTH 1
#define CSU_IER_TAMPER_MASK 0X00002000
#define CSU_IER_PUF_ACC_ERROR_SHIFT 12
#define CSU_IER_PUF_ACC_ERROR_WIDTH 1
#define CSU_IER_PUF_ACC_ERROR_MASK 0X00001000
#define CSU_IER_APB_SLVERR_SHIFT 11
#define CSU_IER_APB_SLVERR_WIDTH 1
#define CSU_IER_APB_SLVERR_MASK 0X00000800
#define CSU_IER_TMR_FATAL_SHIFT 10
#define CSU_IER_TMR_FATAL_WIDTH 1
#define CSU_IER_TMR_FATAL_MASK 0X00000400
#define CSU_IER_PL_SEU_ERROR_SHIFT 9
#define CSU_IER_PL_SEU_ERROR_WIDTH 1
#define CSU_IER_PL_SEU_ERROR_MASK 0X00000200
#define CSU_IER_AES_ERROR_SHIFT 8
#define CSU_IER_AES_ERROR_WIDTH 1
#define CSU_IER_AES_ERROR_MASK 0X00000100
#define CSU_IER_PCAP_WR_OVERFLOW_SHIFT 7
#define CSU_IER_PCAP_WR_OVERFLOW_WIDTH 1
#define CSU_IER_PCAP_WR_OVERFLOW_MASK 0X00000080
#define CSU_IER_PCAP_RD_OVERFLOW_SHIFT 6
#define CSU_IER_PCAP_RD_OVERFLOW_WIDTH 1
#define CSU_IER_PCAP_RD_OVERFLOW_MASK 0X00000040
#define CSU_IER_PL_POR_B_SHIFT 5
#define CSU_IER_PL_POR_B_WIDTH 1
#define CSU_IER_PL_POR_B_MASK 0X00000020
#define CSU_IER_PL_INIT_SHIFT 4
#define CSU_IER_PL_INIT_WIDTH 1
#define CSU_IER_PL_INIT_MASK 0X00000010
#define CSU_IER_PL_DONE_SHIFT 3
#define CSU_IER_PL_DONE_WIDTH 1
#define CSU_IER_PL_DONE_MASK 0X00000008
#define CSU_IER_SHA_DONE_SHIFT 2
#define CSU_IER_SHA_DONE_WIDTH 1
#define CSU_IER_SHA_DONE_MASK 0X00000004
#define CSU_IER_RSA_DONE_SHIFT 1
#define CSU_IER_RSA_DONE_WIDTH 1
#define CSU_IER_RSA_DONE_MASK 0X00000002
#define CSU_IER_AES_DONE_SHIFT 0
#define CSU_IER_AES_DONE_WIDTH 1
#define CSU_IER_AES_DONE_MASK 0X00000001
/**
* Register: CSU_IDR
*/
#define CSU_IDR ( ( CSU_BASEADDR ) + 0X0000002C )
#define CSU_IDR_UNUSED31_SHIFT 31
#define CSU_IDR_UNUSED31_WIDTH 1
#define CSU_IDR_UNUSED31_MASK 0X80000000
#define CSU_IDR_UNUSED30_SHIFT 30
#define CSU_IDR_UNUSED30_WIDTH 1
#define CSU_IDR_UNUSED30_MASK 0X40000000
#define CSU_IDR_UNUSED29_SHIFT 29
#define CSU_IDR_UNUSED29_WIDTH 1
#define CSU_IDR_UNUSED29_MASK 0X20000000
#define CSU_IDR_UNUSED28_SHIFT 28
#define CSU_IDR_UNUSED28_WIDTH 1
#define CSU_IDR_UNUSED28_MASK 0X10000000
#define CSU_IDR_UNUSED27_SHIFT 27
#define CSU_IDR_UNUSED27_WIDTH 1
#define CSU_IDR_UNUSED27_MASK 0X08000000
#define CSU_IDR_UNUSED26_SHIFT 26
#define CSU_IDR_UNUSED26_WIDTH 1
#define CSU_IDR_UNUSED26_MASK 0X04000000
#define CSU_IDR_UNUSED25_SHIFT 25
#define CSU_IDR_UNUSED25_WIDTH 1
#define CSU_IDR_UNUSED25_MASK 0X02000000
#define CSU_IDR_UNUSED24_SHIFT 24
#define CSU_IDR_UNUSED24_WIDTH 1
#define CSU_IDR_UNUSED24_MASK 0X01000000
#define CSU_IDR_UNUSED23_SHIFT 23
#define CSU_IDR_UNUSED23_WIDTH 1
#define CSU_IDR_UNUSED23_MASK 0X00800000
#define CSU_IDR_UNUSED22_SHIFT 22
#define CSU_IDR_UNUSED22_WIDTH 1
#define CSU_IDR_UNUSED22_MASK 0X00400000
#define CSU_IDR_UNUSED21_SHIFT 21
#define CSU_IDR_UNUSED21_WIDTH 1
#define CSU_IDR_UNUSED21_MASK 0X00200000
#define CSU_IDR_UNUSED20_SHIFT 20
#define CSU_IDR_UNUSED20_WIDTH 1
#define CSU_IDR_UNUSED20_MASK 0X00100000
#define CSU_IDR_UNUSED19_SHIFT 19
#define CSU_IDR_UNUSED19_WIDTH 1
#define CSU_IDR_UNUSED19_MASK 0X00080000
#define CSU_IDR_UNUSED18_SHIFT 18
#define CSU_IDR_UNUSED18_WIDTH 1
#define CSU_IDR_UNUSED18_MASK 0X00040000
#define CSU_IDR_UNUSED17_SHIFT 17
#define CSU_IDR_UNUSED17_WIDTH 1
#define CSU_IDR_UNUSED17_MASK 0X00020000
#define CSU_IDR_UNUSED16_SHIFT 16
#define CSU_IDR_UNUSED16_WIDTH 1
#define CSU_IDR_UNUSED16_MASK 0X00010000
#define CSU_IDR_CSU_PL_ISO_SHIFT 15
#define CSU_IDR_CSU_PL_ISO_WIDTH 1
#define CSU_IDR_CSU_PL_ISO_MASK 0X00008000
#define CSU_IDR_CSU_RAM_ECC_ERROR_SHIFT 14
#define CSU_IDR_CSU_RAM_ECC_ERROR_WIDTH 1
#define CSU_IDR_CSU_RAM_ECC_ERROR_MASK 0X00004000
#define CSU_IDR_TAMPER_SHIFT 13
#define CSU_IDR_TAMPER_WIDTH 1
#define CSU_IDR_TAMPER_MASK 0X00002000
#define CSU_IDR_PUF_ACC_ERROR_SHIFT 12
#define CSU_IDR_PUF_ACC_ERROR_WIDTH 1
#define CSU_IDR_PUF_ACC_ERROR_MASK 0X00001000
#define CSU_IDR_APB_SLVERR_SHIFT 11
#define CSU_IDR_APB_SLVERR_WIDTH 1
#define CSU_IDR_APB_SLVERR_MASK 0X00000800
#define CSU_IDR_TMR_FATAL_SHIFT 10
#define CSU_IDR_TMR_FATAL_WIDTH 1
#define CSU_IDR_TMR_FATAL_MASK 0X00000400
#define CSU_IDR_PL_SEU_ERROR_SHIFT 9
#define CSU_IDR_PL_SEU_ERROR_WIDTH 1
#define CSU_IDR_PL_SEU_ERROR_MASK 0X00000200
#define CSU_IDR_AES_ERROR_SHIFT 8
#define CSU_IDR_AES_ERROR_WIDTH 1
#define CSU_IDR_AES_ERROR_MASK 0X00000100
#define CSU_IDR_PCAP_WR_OVERFLOW_SHIFT 7
#define CSU_IDR_PCAP_WR_OVERFLOW_WIDTH 1
#define CSU_IDR_PCAP_WR_OVERFLOW_MASK 0X00000080
#define CSU_IDR_PCAP_RD_OVERFLOW_SHIFT 6
#define CSU_IDR_PCAP_RD_OVERFLOW_WIDTH 1
#define CSU_IDR_PCAP_RD_OVERFLOW_MASK 0X00000040
#define CSU_IDR_PL_POR_B_SHIFT 5
#define CSU_IDR_PL_POR_B_WIDTH 1
#define CSU_IDR_PL_POR_B_MASK 0X00000020
#define CSU_IDR_PL_INIT_SHIFT 4
#define CSU_IDR_PL_INIT_WIDTH 1
#define CSU_IDR_PL_INIT_MASK 0X00000010
#define CSU_IDR_PL_DONE_SHIFT 3
#define CSU_IDR_PL_DONE_WIDTH 1
#define CSU_IDR_PL_DONE_MASK 0X00000008
#define CSU_IDR_SHA_DONE_SHIFT 2
#define CSU_IDR_SHA_DONE_WIDTH 1
#define CSU_IDR_SHA_DONE_MASK 0X00000004
#define CSU_IDR_RSA_DONE_SHIFT 1
#define CSU_IDR_RSA_DONE_WIDTH 1
#define CSU_IDR_RSA_DONE_MASK 0X00000002
#define CSU_IDR_AES_DONE_SHIFT 0
#define CSU_IDR_AES_DONE_WIDTH 1
#define CSU_IDR_AES_DONE_MASK 0X00000001
/**
* Register: CSU_JTAG_CHAIN_CFG
*/
#define CSU_JTAG_CHAIN_CFG ( ( CSU_BASEADDR ) + 0X00000030 )
#define CSU_JTAG_CHAIN_CFG_SSSS_LINK_ARM_DAP_SHIFT 1
#define CSU_JTAG_CHAIN_CFG_SSSS_LINK_ARM_DAP_WIDTH 1
#define CSU_JTAG_CHAIN_CFG_SSSS_LINK_ARM_DAP_MASK 0X00000002
#define CSU_JTAG_CHAIN_CFG_SSSS_LINK_PL_TAP_SHIFT 0
#define CSU_JTAG_CHAIN_CFG_SSSS_LINK_PL_TAP_WIDTH 1
#define CSU_JTAG_CHAIN_CFG_SSSS_LINK_PL_TAP_MASK 0X00000001
/**
* Register: CSU_JTAG_CHAIN_STATUS
*/
#define CSU_JTAG_CHAIN_STATUS ( ( CSU_BASEADDR ) + 0X00000034 )
#define CSU_JTAG_CHAIN_STATUS_ARM_DAP_SHIFT 1
#define CSU_JTAG_CHAIN_STATUS_ARM_DAP_WIDTH 1
#define CSU_JTAG_CHAIN_STATUS_ARM_DAP_MASK 0X00000002
#define CSU_JTAG_CHAIN_STATUS_PL_TAP_SHIFT 0
#define CSU_JTAG_CHAIN_STATUS_PL_TAP_WIDTH 1
#define CSU_JTAG_CHAIN_STATUS_PL_TAP_MASK 0X00000001
/**
* Register: CSU_JTAG_SEC
*/
#define CSU_JTAG_SEC ( ( CSU_BASEADDR ) + 0X00000038 )
#define CSU_JTAG_SEC_SSSS_DDRPHY_SEC_SHIFT 12
#define CSU_JTAG_SEC_SSSS_DDRPHY_SEC_WIDTH 3
#define CSU_JTAG_SEC_SSSS_DDRPHY_SEC_MASK 0X00007000
#define CSU_JTAG_SEC_SSSS_PLTAP_EN_SHIFT 9
#define CSU_JTAG_SEC_SSSS_PLTAP_EN_WIDTH 3
#define CSU_JTAG_SEC_SSSS_PLTAP_EN_MASK 0X00000E00
#define CSU_JTAG_SEC_SSSS_PMU_SEC_SHIFT 6
#define CSU_JTAG_SEC_SSSS_PMU_SEC_WIDTH 3
#define CSU_JTAG_SEC_SSSS_PMU_SEC_MASK 0X000001C0
#define CSU_JTAG_SEC_SSSS_PLTAP_SEC_SHIFT 3
#define CSU_JTAG_SEC_SSSS_PLTAP_SEC_WIDTH 3
#define CSU_JTAG_SEC_SSSS_PLTAP_SEC_MASK 0X00000038
#define CSU_JTAG_SEC_SSSS_DAP_SEC_SHIFT 0
#define CSU_JTAG_SEC_SSSS_DAP_SEC_WIDTH 3
#define CSU_JTAG_SEC_SSSS_DAP_SEC_MASK 0X00000007
/**
* Register: CSU_JTAG_DAP_CFG
*/
#define CSU_JTAG_DAP_CFG ( ( CSU_BASEADDR ) + 0X0000003C )
#define CSU_JTAG_DAP_CFG_SSSS_RPU_SPNIDEN_SHIFT 7
#define CSU_JTAG_DAP_CFG_SSSS_RPU_SPNIDEN_WIDTH 1
#define CSU_JTAG_DAP_CFG_SSSS_RPU_SPNIDEN_MASK 0X00000080
#define CSU_JTAG_DAP_CFG_SSSS_RPU_SPIDEN_SHIFT 6
#define CSU_JTAG_DAP_CFG_SSSS_RPU_SPIDEN_WIDTH 1
#define CSU_JTAG_DAP_CFG_SSSS_RPU_SPIDEN_MASK 0X00000040
#define CSU_JTAG_DAP_CFG_SSSS_RPU_NIDEN_SHIFT 5
#define CSU_JTAG_DAP_CFG_SSSS_RPU_NIDEN_WIDTH 1
#define CSU_JTAG_DAP_CFG_SSSS_RPU_NIDEN_MASK 0X00000020
#define CSU_JTAG_DAP_CFG_SSSS_RPU_DBGEN_SHIFT 4
#define CSU_JTAG_DAP_CFG_SSSS_RPU_DBGEN_WIDTH 1
#define CSU_JTAG_DAP_CFG_SSSS_RPU_DBGEN_MASK 0X00000010
#define CSU_JTAG_DAP_CFG_SSSS_APU_SPNIDEN_SHIFT 3
#define CSU_JTAG_DAP_CFG_SSSS_APU_SPNIDEN_WIDTH 1
#define CSU_JTAG_DAP_CFG_SSSS_APU_SPNIDEN_MASK 0X00000008
#define CSU_JTAG_DAP_CFG_SSSS_APU_SPIDEN_SHIFT 2
#define CSU_JTAG_DAP_CFG_SSSS_APU_SPIDEN_WIDTH 1
#define CSU_JTAG_DAP_CFG_SSSS_APU_SPIDEN_MASK 0X00000004
#define CSU_JTAG_DAP_CFG_SSSS_APU_NIDEN_SHIFT 1
#define CSU_JTAG_DAP_CFG_SSSS_APU_NIDEN_WIDTH 1
#define CSU_JTAG_DAP_CFG_SSSS_APU_NIDEN_MASK 0X00000002
#define CSU_JTAG_DAP_CFG_SSSS_APU_DBGEN_SHIFT 0
#define CSU_JTAG_DAP_CFG_SSSS_APU_DBGEN_WIDTH 1
#define CSU_JTAG_DAP_CFG_SSSS_APU_DBGEN_MASK 0X00000001
/**
* Register: CSU_IDCODE
*/
#define CSU_IDCODE ( ( CSU_BASEADDR ) + 0X00000040 )
#define CSU_IDCODE_IDCODE_SHIFT 0
#define CSU_IDCODE_IDCODE_WIDTH 32
#define CSU_IDCODE_IDCODE_MASK 0XFFFFFFFF
/**
* Register: CSU_VERSION
*/
#define CSU_VERSION ( ( CSU_BASEADDR ) + 0X00000044 )
#define CSU_VERSION_PLATFORM_VERSION_SHIFT 16
#define CSU_VERSION_PLATFORM_VERSION_WIDTH 4
#define CSU_VERSION_PLATFORM_VERSION_MASK 0X000F0000
#define CSU_VERSION_PLATFORM_SHIFT 12
#define CSU_VERSION_PLATFORM_WIDTH 4
#define CSU_VERSION_PLATFORM_MASK 0X0000F000
#define CSU_VERSION_RTL_VERSION_SHIFT 4
#define CSU_VERSION_RTL_VERSION_WIDTH 8
#define CSU_VERSION_RTL_VERSION_MASK 0X00000FF0
#define CSU_VERSION_PS_VERSION_SHIFT 0
#define CSU_VERSION_PS_VERSION_WIDTH 4
#define CSU_VERSION_PS_VERSION_MASK 0X0000000F
/**
* Register: CSU_ROM_DIGEST_0
*/
#define CSU_ROM_DIGEST_0 ( ( CSU_BASEADDR ) + 0X00000050 )
#define CSU_ROM_DIGEST_0_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_0_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_0_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_1
*/
#define CSU_ROM_DIGEST_1 ( ( CSU_BASEADDR ) + 0X00000054 )
#define CSU_ROM_DIGEST_1_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_1_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_1_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_2
*/
#define CSU_ROM_DIGEST_2 ( ( CSU_BASEADDR ) + 0X00000058 )
#define CSU_ROM_DIGEST_2_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_2_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_2_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_3
*/
#define CSU_ROM_DIGEST_3 ( ( CSU_BASEADDR ) + 0X0000005C )
#define CSU_ROM_DIGEST_3_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_3_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_3_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_4
*/
#define CSU_ROM_DIGEST_4 ( ( CSU_BASEADDR ) + 0X00000060 )
#define CSU_ROM_DIGEST_4_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_4_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_4_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_5
*/
#define CSU_ROM_DIGEST_5 ( ( CSU_BASEADDR ) + 0X00000064 )
#define CSU_ROM_DIGEST_5_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_5_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_5_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_6
*/
#define CSU_ROM_DIGEST_6 ( ( CSU_BASEADDR ) + 0X00000068 )
#define CSU_ROM_DIGEST_6_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_6_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_6_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_7
*/
#define CSU_ROM_DIGEST_7 ( ( CSU_BASEADDR ) + 0X0000006C )
#define CSU_ROM_DIGEST_7_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_7_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_7_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_8
*/
#define CSU_ROM_DIGEST_8 ( ( CSU_BASEADDR ) + 0X00000070 )
#define CSU_ROM_DIGEST_8_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_8_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_8_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_9
*/
#define CSU_ROM_DIGEST_9 ( ( CSU_BASEADDR ) + 0X00000074 )
#define CSU_ROM_DIGEST_9_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_9_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_9_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_10
*/
#define CSU_ROM_DIGEST_10 ( ( CSU_BASEADDR ) + 0X00000078 )
#define CSU_ROM_DIGEST_10_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_10_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_10_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_ROM_DIGEST_11
*/
#define CSU_ROM_DIGEST_11 ( ( CSU_BASEADDR ) + 0X0000007C )
#define CSU_ROM_DIGEST_11_DIGEST_SHIFT 0
#define CSU_ROM_DIGEST_11_DIGEST_WIDTH 32
#define CSU_ROM_DIGEST_11_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_STATUS
*/
#define CSU_AES_STATUS ( ( CSU_BASEADDR ) + 0X00001000 )
#define CSU_AES_STATUS_OKR_ZEROED_SHIFT 11
#define CSU_AES_STATUS_OKR_ZEROED_WIDTH 1
#define CSU_AES_STATUS_OKR_ZEROED_MASK 0X00000800
#define CSU_AES_STATUS_BOOT_ZEROED_SHIFT 10
#define CSU_AES_STATUS_BOOT_ZEROED_WIDTH 1
#define CSU_AES_STATUS_BOOT_ZEROED_MASK 0X00000400
#define CSU_AES_STATUS_KUP_ZEROED_SHIFT 9
#define CSU_AES_STATUS_KUP_ZEROED_WIDTH 1
#define CSU_AES_STATUS_KUP_ZEROED_MASK 0X00000200
#define CSU_AES_STATUS_AES_KEY_ZEROED_SHIFT 8
#define CSU_AES_STATUS_AES_KEY_ZEROED_WIDTH 1
#define CSU_AES_STATUS_AES_KEY_ZEROED_MASK 0X00000100
#define CSU_AES_STATUS_BLACK_KEY_DONE_SHIFT 5
#define CSU_AES_STATUS_BLACK_KEY_DONE_WIDTH 1
#define CSU_AES_STATUS_BLACK_KEY_DONE_MASK 0X00000020
#define CSU_AES_STATUS_KEY_INIT_DONE_SHIFT 4
#define CSU_AES_STATUS_KEY_INIT_DONE_WIDTH 1
#define CSU_AES_STATUS_KEY_INIT_DONE_MASK 0X00000010
#define CSU_AES_STATUS_GCM_TAG_PASS_SHIFT 3
#define CSU_AES_STATUS_GCM_TAG_PASS_WIDTH 1
#define CSU_AES_STATUS_GCM_TAG_PASS_MASK 0X00000008
#define CSU_AES_STATUS_DONE_SHIFT 2
#define CSU_AES_STATUS_DONE_WIDTH 1
#define CSU_AES_STATUS_DONE_MASK 0X00000004
#define CSU_AES_STATUS_READY_SHIFT 1
#define CSU_AES_STATUS_READY_WIDTH 1
#define CSU_AES_STATUS_READY_MASK 0X00000002
#define CSU_AES_STATUS_BUSY_SHIFT 0
#define CSU_AES_STATUS_BUSY_WIDTH 1
#define CSU_AES_STATUS_BUSY_MASK 0X00000001
/**
* Register: CSU_AES_KEY_SRC
*/
#define CSU_AES_KEY_SRC ( ( CSU_BASEADDR ) + 0X00001004 )
#define CSU_AES_KEY_SRC_KEY_SRC_SHIFT 0
#define CSU_AES_KEY_SRC_KEY_SRC_WIDTH 4
#define CSU_AES_KEY_SRC_KEY_SRC_MASK 0X0000000F
/**
* Register: CSU_AES_KEY_LOAD
*/
#define CSU_AES_KEY_LOAD ( ( CSU_BASEADDR ) + 0X00001008 )
#define CSU_AES_KEY_LOAD_KEY_LOAD_SHIFT 0
#define CSU_AES_KEY_LOAD_KEY_LOAD_WIDTH 1
#define CSU_AES_KEY_LOAD_KEY_LOAD_MASK 0X00000001
/**
* Register: CSU_AES_START_MSG
*/
#define CSU_AES_START_MSG ( ( CSU_BASEADDR ) + 0X0000100C )
#define CSU_AES_START_MSG_START_MSG_SHIFT 0
#define CSU_AES_START_MSG_START_MSG_WIDTH 1
#define CSU_AES_START_MSG_START_MSG_MASK 0X00000001
/**
* Register: CSU_AES_RESET
*/
#define CSU_AES_RESET ( ( CSU_BASEADDR ) + 0X00001010 )
#define CSU_AES_RESET_RESET_SHIFT 0
#define CSU_AES_RESET_RESET_WIDTH 1
#define CSU_AES_RESET_RESET_MASK 0X00000001
/**
* Register: CSU_AES_KEY_CLEAR
*/
#define CSU_AES_KEY_CLEAR ( ( CSU_BASEADDR ) + 0X00001014 )
#define CSU_AES_KEY_CLEAR_AES_OKR_ZERO_SHIFT 3
#define CSU_AES_KEY_CLEAR_AES_OKR_ZERO_WIDTH 1
#define CSU_AES_KEY_CLEAR_AES_OKR_ZERO_MASK 0X00000008
#define CSU_AES_KEY_CLEAR_AES_BOOT_ZERO_SHIFT 2
#define CSU_AES_KEY_CLEAR_AES_BOOT_ZERO_WIDTH 1
#define CSU_AES_KEY_CLEAR_AES_BOOT_ZERO_MASK 0X00000004
#define CSU_AES_KEY_CLEAR_AES_KUP_ZERO_SHIFT 1
#define CSU_AES_KEY_CLEAR_AES_KUP_ZERO_WIDTH 1
#define CSU_AES_KEY_CLEAR_AES_KUP_ZERO_MASK 0X00000002
#define CSU_AES_KEY_CLEAR_AES_KEY_ZERO_SHIFT 0
#define CSU_AES_KEY_CLEAR_AES_KEY_ZERO_WIDTH 1
#define CSU_AES_KEY_CLEAR_AES_KEY_ZERO_MASK 0X00000001
/**
* Register: CSU_AES_CFG
*/
#define CSU_AES_CFG ( ( CSU_BASEADDR ) + 0X00001018 )
#define CSU_AES_CFG_ENCRYPT_DECRYPT_N_SHIFT 0
#define CSU_AES_CFG_ENCRYPT_DECRYPT_N_WIDTH 1
#define CSU_AES_CFG_ENCRYPT_DECRYPT_N_MASK 0X00000001
/**
* Register: CSU_AES_KUP_WR
*/
#define CSU_AES_KUP_WR ( ( CSU_BASEADDR ) + 0X0000101C )
#define CSU_AES_KUP_WR_IV_WRITE_SHIFT 1
#define CSU_AES_KUP_WR_IV_WRITE_WIDTH 1
#define CSU_AES_KUP_WR_IV_WRITE_MASK 0X00000002
#define CSU_AES_KUP_WR_KUP_WRITE_SHIFT 0
#define CSU_AES_KUP_WR_KUP_WRITE_WIDTH 1
#define CSU_AES_KUP_WR_KUP_WRITE_MASK 0X00000001
/**
* Register: CSU_AES_KUP_0
*/
#define CSU_AES_KUP_0 ( ( CSU_BASEADDR ) + 0X00001020 )
#define CSU_AES_KUP_0_AES_KEY_SHIFT 0
#define CSU_AES_KUP_0_AES_KEY_WIDTH 32
#define CSU_AES_KUP_0_AES_KEY_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_KUP_1
*/
#define CSU_AES_KUP_1 ( ( CSU_BASEADDR ) + 0X00001024 )
#define CSU_AES_KUP_1_AES_KEY_SHIFT 0
#define CSU_AES_KUP_1_AES_KEY_WIDTH 32
#define CSU_AES_KUP_1_AES_KEY_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_KUP_2
*/
#define CSU_AES_KUP_2 ( ( CSU_BASEADDR ) + 0X00001028 )
#define CSU_AES_KUP_2_AES_KEY_SHIFT 0
#define CSU_AES_KUP_2_AES_KEY_WIDTH 32
#define CSU_AES_KUP_2_AES_KEY_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_KUP_3
*/
#define CSU_AES_KUP_3 ( ( CSU_BASEADDR ) + 0X0000102C )
#define CSU_AES_KUP_3_AES_KEY_SHIFT 0
#define CSU_AES_KUP_3_AES_KEY_WIDTH 32
#define CSU_AES_KUP_3_AES_KEY_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_KUP_4
*/
#define CSU_AES_KUP_4 ( ( CSU_BASEADDR ) + 0X00001030 )
#define CSU_AES_KUP_4_AES_KEY_SHIFT 0
#define CSU_AES_KUP_4_AES_KEY_WIDTH 32
#define CSU_AES_KUP_4_AES_KEY_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_KUP_5
*/
#define CSU_AES_KUP_5 ( ( CSU_BASEADDR ) + 0X00001034 )
#define CSU_AES_KUP_5_AES_KEY_SHIFT 0
#define CSU_AES_KUP_5_AES_KEY_WIDTH 32
#define CSU_AES_KUP_5_AES_KEY_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_KUP_6
*/
#define CSU_AES_KUP_6 ( ( CSU_BASEADDR ) + 0X00001038 )
#define CSU_AES_KUP_6_AES_KEY_SHIFT 0
#define CSU_AES_KUP_6_AES_KEY_WIDTH 32
#define CSU_AES_KUP_6_AES_KEY_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_KUP_7
*/
#define CSU_AES_KUP_7 ( ( CSU_BASEADDR ) + 0X0000103C )
#define CSU_AES_KUP_7_AES_KEY_SHIFT 0
#define CSU_AES_KUP_7_AES_KEY_WIDTH 32
#define CSU_AES_KUP_7_AES_KEY_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_IV_0
*/
#define CSU_AES_IV_0 ( ( CSU_BASEADDR ) + 0X00001040 )
#define CSU_AES_IV_0_AES_IV_SHIFT 0
#define CSU_AES_IV_0_AES_IV_WIDTH 32
#define CSU_AES_IV_0_AES_IV_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_IV_1
*/
#define CSU_AES_IV_1 ( ( CSU_BASEADDR ) + 0X00001044 )
#define CSU_AES_IV_1_AES_IV_SHIFT 0
#define CSU_AES_IV_1_AES_IV_WIDTH 32
#define CSU_AES_IV_1_AES_IV_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_IV_2
*/
#define CSU_AES_IV_2 ( ( CSU_BASEADDR ) + 0X00001048 )
#define CSU_AES_IV_2_AES_IV_SHIFT 0
#define CSU_AES_IV_2_AES_IV_WIDTH 32
#define CSU_AES_IV_2_AES_IV_MASK 0XFFFFFFFF
/**
* Register: CSU_AES_IV_3
*/
#define CSU_AES_IV_3 ( ( CSU_BASEADDR ) + 0X0000104C )
#define CSU_AES_IV_3_AES_IV_DLC_SHIFT 0
#define CSU_AES_IV_3_AES_IV_DLC_WIDTH 32
#define CSU_AES_IV_3_AES_IV_DLC_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_START
*/
#define CSU_SHA_START ( ( CSU_BASEADDR ) + 0X00002000 )
#define CSU_SHA_START_START_MSG_SHIFT 0
#define CSU_SHA_START_START_MSG_WIDTH 1
#define CSU_SHA_START_START_MSG_MASK 0X00000001
/**
* Register: CSU_SHA_RESET
*/
#define CSU_SHA_RESET ( ( CSU_BASEADDR ) + 0X00002004 )
#define CSU_SHA_RESET_RESET_SHIFT 0
#define CSU_SHA_RESET_RESET_WIDTH 1
#define CSU_SHA_RESET_RESET_MASK 0X00000001
/**
* Register: CSU_SHA_DONE
*/
#define CSU_SHA_DONE ( ( CSU_BASEADDR ) + 0X00002008 )
#define CSU_SHA_DONE_SHA_DONE_SHIFT 0
#define CSU_SHA_DONE_SHA_DONE_WIDTH 1
#define CSU_SHA_DONE_SHA_DONE_MASK 0X00000001
/**
* Register: CSU_SHA_DIGEST_0
*/
#define CSU_SHA_DIGEST_0 ( ( CSU_BASEADDR ) + 0X00002010 )
#define CSU_SHA_DIGEST_0_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_0_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_0_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_1
*/
#define CSU_SHA_DIGEST_1 ( ( CSU_BASEADDR ) + 0X00002014 )
#define CSU_SHA_DIGEST_1_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_1_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_1_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_2
*/
#define CSU_SHA_DIGEST_2 ( ( CSU_BASEADDR ) + 0X00002018 )
#define CSU_SHA_DIGEST_2_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_2_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_2_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_3
*/
#define CSU_SHA_DIGEST_3 ( ( CSU_BASEADDR ) + 0X0000201C )
#define CSU_SHA_DIGEST_3_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_3_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_3_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_4
*/
#define CSU_SHA_DIGEST_4 ( ( CSU_BASEADDR ) + 0X00002020 )
#define CSU_SHA_DIGEST_4_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_4_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_4_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_5
*/
#define CSU_SHA_DIGEST_5 ( ( CSU_BASEADDR ) + 0X00002024 )
#define CSU_SHA_DIGEST_5_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_5_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_5_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_6
*/
#define CSU_SHA_DIGEST_6 ( ( CSU_BASEADDR ) + 0X00002028 )
#define CSU_SHA_DIGEST_6_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_6_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_6_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_7
*/
#define CSU_SHA_DIGEST_7 ( ( CSU_BASEADDR ) + 0X0000202C )
#define CSU_SHA_DIGEST_7_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_7_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_7_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_8
*/
#define CSU_SHA_DIGEST_8 ( ( CSU_BASEADDR ) + 0X00002030 )
#define CSU_SHA_DIGEST_8_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_8_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_8_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_9
*/
#define CSU_SHA_DIGEST_9 ( ( CSU_BASEADDR ) + 0X00002034 )
#define CSU_SHA_DIGEST_9_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_9_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_9_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_10
*/
#define CSU_SHA_DIGEST_10 ( ( CSU_BASEADDR ) + 0X00002038 )
#define CSU_SHA_DIGEST_10_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_10_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_10_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_SHA_DIGEST_11
*/
#define CSU_SHA_DIGEST_11 ( ( CSU_BASEADDR ) + 0X0000203C )
#define CSU_SHA_DIGEST_11_DIGEST_SHIFT 0
#define CSU_SHA_DIGEST_11_DIGEST_WIDTH 32
#define CSU_SHA_DIGEST_11_DIGEST_MASK 0XFFFFFFFF
/**
* Register: CSU_PCAP_PROG
*/
#define CSU_PCAP_PROG_REG ( ( CSU_BASEADDR ) + 0X00003000 )
#define CSU_PCAP_PROG_PCFG_PROG_B_SHIFT_VAL 0
#define CSU_PCAP_PROG_PCFG_PROG_B_WIDTH_VAL 1
#define CSU_PCAP_PROG_PCFG_PROG_B_MASK_VAL 0X00000001
/**
* Register: CSU_PCAP_RDWR
*/
#define CSU_PCAP_RDWR_REG ( ( CSU_BASEADDR ) + 0X00003004 )
#define CSU_PCAP_RDWR_PCAP_RDWR_B_SHIFT_VAL 0
#define CSU_PCAP_RDWR_PCAP_RDWR_B_WIDTH_VAL 1
#define CSU_PCAP_RDWR_PCAP_RDWR_B_MASK_VAL 0X00000001
/**
* Register: CSU_PCAP_CTRL
*/
#define CSU_PCAP_CTRL_REG ( ( CSU_BASEADDR ) + 0X00003008 )
#define CSU_PCAP_CTRL_PCFG_GSR_SHIFT 3
#define CSU_PCAP_CTRL_PCFG_GSR_WIDTH 1
#define CSU_PCAP_CTRL_PCFG_GSR_MASK 0X00000008
#define CSU_PCAP_CTRL_PCFG_GTS_SHIFT 2
#define CSU_PCAP_CTRL_PCFG_GTS_WIDTH 1
#define CSU_PCAP_CTRL_PCFG_GTS_MASK 0X00000004
#define CSU_PCAP_CTRL_PCFG_POR_CNT_4K_SHIFT 1
#define CSU_PCAP_CTRL_PCFG_POR_CNT_4K_WIDTH 1
#define CSU_PCAP_CTRL_PCFG_POR_CNT_4K_MASK 0X00000002
#define CSU_PCAP_CTRL_PCAP_PR_SHIFT 0
#define CSU_PCAP_CTRL_PCAP_PR_WIDTH 1
#define CSU_PCAP_CTRL_PCAP_PR_MASK_VAL 0X00000001
/**
* Register: CSU_PCAP_RESET
*/
#define CSU_PCAP_RESET_REG ( ( CSU_BASEADDR ) + 0X0000300C )
#define CSU_PCAP_RESET_SHIFT 0
#define CSU_PCAP_RESET_WIDTH 1
#define CSU_PCAP_RESET_MASK 0X00000001
/**
* Register: CSU_PCAP_STATUS
*/
#define CSU_PCAP_STATUS_REG ( ( CSU_BASEADDR ) + 0X00003010 )
#define CSU_PCAP_STATUS_PCFG_FUSE_PL_DIS_SHIFT 31
#define CSU_PCAP_STATUS_PCFG_FUSE_PL_DIS_WIDTH 1
#define CSU_PCAP_STATUS_PCFG_FUSE_PL_DIS_MASK 0X80000000
#define CSU_PCAP_STATUS_PCFG_PL_CFG_USED_SHIFT 30
#define CSU_PCAP_STATUS_PCFG_PL_CFG_USED_WIDTH 1
#define CSU_PCAP_STATUS_PCFG_PL_CFG_USED_MASK 0X40000000
#define CSU_PCAP_STATUS_PCFG_IS_ZYNQ_SHIFT 29
#define CSU_PCAP_STATUS_PCFG_IS_ZYNQ_WIDTH 1
#define CSU_PCAP_STATUS_PCFG_IS_ZYNQ_MASK 0X20000000
#define CSU_PCAP_STATUS_PCFG_GWE_SHIFT 13
#define CSU_PCAP_STATUS_PCFG_GWE_WIDTH 1
#define CSU_PCAP_STATUS_PCFG_GWE_MASK 0X00002000
#define CSU_PCAP_STATUS_PCFG_MCAP_MODE_SHIFT 12
#define CSU_PCAP_STATUS_PCFG_MCAP_MODE_WIDTH 1
#define CSU_PCAP_STATUS_PCFG_MCAP_MODE_MASK 0X00001000
#define CSU_PCAP_STATUS_PL_GTS_USR_B_SHIFT 11
#define CSU_PCAP_STATUS_PL_GTS_USR_B_WIDTH 1
#define CSU_PCAP_STATUS_PL_GTS_USR_B_MASK 0X00000800
#define CSU_PCAP_STATUS_PL_GTS_CFG_B_SHIFT 10
#define CSU_PCAP_STATUS_PL_GTS_CFG_B_WIDTH 1
#define CSU_PCAP_STATUS_PL_GTS_CFG_B_MASK 0X00000400
#define CSU_PCAP_STATUS_PL_GPWRDWN_B_SHIFT 9
#define CSU_PCAP_STATUS_PL_GPWRDWN_B_WIDTH 1
#define CSU_PCAP_STATUS_PL_GPWRDWN_B_MASK 0X00000200
#define CSU_PCAP_STATUS_PL_GHIGH_B_SHIFT 8
#define CSU_PCAP_STATUS_PL_GHIGH_B_WIDTH 1
#define CSU_PCAP_STATUS_PL_GHIGH_B_MASK 0X00000100
#define CSU_PCAP_STATUS_PL_FST_CFG_SHIFT 7
#define CSU_PCAP_STATUS_PL_FST_CFG_WIDTH 1
#define CSU_PCAP_STATUS_PL_FST_CFG_MASK 0X00000080
#define CSU_PCAP_STATUS_PL_CFG_RESET_B_SHIFT 6
#define CSU_PCAP_STATUS_PL_CFG_RESET_B_WIDTH 1
#define CSU_PCAP_STATUS_PL_CFG_RESET_B_MASK 0X00000040
#define CSU_PCAP_STATUS_PL_SEU_ERROR_SHIFT 5
#define CSU_PCAP_STATUS_PL_SEU_ERROR_WIDTH 1
#define CSU_PCAP_STATUS_PL_SEU_ERROR_MASK 0X00000020
#define CSU_PCAP_STATUS_PL_EOS_SHIFT 4
#define CSU_PCAP_STATUS_PL_EOS_WIDTH 1
#define CSU_PCAP_STATUS_PL_EOS_MASK 0X00000010
#define CSU_PCAP_STATUS_PL_DONE_SHIFT_VAL 3
#define CSU_PCAP_STATUS_PL_DONE_WIDTH_VAL 1
#define CSU_PCAP_STATUS_PL_DONE_MASK_VAL 0X00000008
#define CSU_PCAP_STATUS_PL_INIT_SHIFT_VAL 2
#define CSU_PCAP_STATUS_PL_INIT_WIDTH_VAL 1
#define CSU_PCAP_STATUS_PL_INIT_MASK_VAL 0X00000004
#define CSU_PCAP_STATUS_RD_IDLE_SHIFT 1
#define CSU_PCAP_STATUS_RD_IDLE_WIDTH 1
#define CSU_PCAP_STATUS_RD_IDLE_MASK 0X00000002
#define CSU_PCAP_STATUS_WR_IDLE_SHIFT 0
#define CSU_PCAP_STATUS_WR_IDLE_WIDTH 1
#define CSU_PCAP_STATUS_WR_IDLE_MASK 0X00000001
/**
* Register: CSU_TAMPER_STATUS
*/
#define CSU_TAMPER_STATUS ( ( CSU_BASEADDR ) + 0X00005000 )
#define CSU_TAMPER_STATUS_TAMPER_13_SHIFT 13
#define CSU_TAMPER_STATUS_TAMPER_13_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_13_MASK 0X00002000
#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12
#define CSU_TAMPER_STATUS_TAMPER_12_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0X00001000
#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11
#define CSU_TAMPER_STATUS_TAMPER_11_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0X00000800
#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10
#define CSU_TAMPER_STATUS_TAMPER_10_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0X00000400
#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9
#define CSU_TAMPER_STATUS_TAMPER_9_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0X00000200
#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8
#define CSU_TAMPER_STATUS_TAMPER_8_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0X00000100
#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7
#define CSU_TAMPER_STATUS_TAMPER_7_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0X00000080
#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6
#define CSU_TAMPER_STATUS_TAMPER_6_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0X00000040
#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5
#define CSU_TAMPER_STATUS_TAMPER_5_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0X00000020
#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4
#define CSU_TAMPER_STATUS_TAMPER_4_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0X00000010
#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3
#define CSU_TAMPER_STATUS_TAMPER_3_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0X00000008
#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2
#define CSU_TAMPER_STATUS_TAMPER_2_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0X00000004
#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1
#define CSU_TAMPER_STATUS_TAMPER_1_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0X00000002
#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0
#define CSU_TAMPER_STATUS_TAMPER_0_WIDTH 1
#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0X00000001
/**
* Register: CSU_TAMPER_0
*/
#define CSU_TAMPER_0 ( ( CSU_BASEADDR ) + 0X00005004 )
#define CSU_TAMPER_0_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_0_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_0_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_0_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_0_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_0_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_0_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_0_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_0_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_0_SYS_RESET_SHIFT 1
#define CSU_TAMPER_0_SYS_RESET_WIDTH 1
#define CSU_TAMPER_0_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_0_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_0_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_0_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_1
*/
#define CSU_TAMPER_1 ( ( CSU_BASEADDR ) + 0X00005008 )
#define CSU_TAMPER_1_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_1_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_1_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_1_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_1_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_1_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_1_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_1_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_1_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_1_SYS_RESET_SHIFT 1
#define CSU_TAMPER_1_SYS_RESET_WIDTH 1
#define CSU_TAMPER_1_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_1_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_1_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_1_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_2
*/
#define CSU_TAMPER_2 ( ( CSU_BASEADDR ) + 0X0000500C )
#define CSU_TAMPER_2_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_2_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_2_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_2_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_2_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_2_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_2_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_2_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_2_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_2_SYS_RESET_SHIFT 1
#define CSU_TAMPER_2_SYS_RESET_WIDTH 1
#define CSU_TAMPER_2_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_2_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_2_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_2_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_3
*/
#define CSU_TAMPER_3 ( ( CSU_BASEADDR ) + 0X00005010 )
#define CSU_TAMPER_3_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_3_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_3_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_3_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_3_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_3_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_3_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_3_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_3_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_3_SYS_RESET_SHIFT 1
#define CSU_TAMPER_3_SYS_RESET_WIDTH 1
#define CSU_TAMPER_3_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_3_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_3_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_3_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_4
*/
#define CSU_TAMPER_4 ( ( CSU_BASEADDR ) + 0X00005014 )
#define CSU_TAMPER_4_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_4_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_4_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_4_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_4_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_4_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_4_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_4_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_4_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_4_SYS_RESET_SHIFT 1
#define CSU_TAMPER_4_SYS_RESET_WIDTH 1
#define CSU_TAMPER_4_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_4_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_4_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_4_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_5
*/
#define CSU_TAMPER_5 ( ( CSU_BASEADDR ) + 0X00005018 )
#define CSU_TAMPER_5_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_5_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_5_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_5_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_5_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_5_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_5_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_5_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_5_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_5_SYS_RESET_SHIFT 1
#define CSU_TAMPER_5_SYS_RESET_WIDTH 1
#define CSU_TAMPER_5_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_5_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_5_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_5_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_6
*/
#define CSU_TAMPER_6 ( ( CSU_BASEADDR ) + 0X0000501C )
#define CSU_TAMPER_6_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_6_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_6_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_6_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_6_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_6_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_6_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_6_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_6_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_6_SYS_RESET_SHIFT 1
#define CSU_TAMPER_6_SYS_RESET_WIDTH 1
#define CSU_TAMPER_6_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_6_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_6_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_6_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_7
*/
#define CSU_TAMPER_7 ( ( CSU_BASEADDR ) + 0X00005020 )
#define CSU_TAMPER_7_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_7_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_7_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_7_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_7_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_7_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_7_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_7_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_7_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_7_SYS_RESET_SHIFT 1
#define CSU_TAMPER_7_SYS_RESET_WIDTH 1
#define CSU_TAMPER_7_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_7_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_7_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_7_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_8
*/
#define CSU_TAMPER_8 ( ( CSU_BASEADDR ) + 0X00005024 )
#define CSU_TAMPER_8_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_8_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_8_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_8_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_8_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_8_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_8_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_8_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_8_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_8_SYS_RESET_SHIFT 1
#define CSU_TAMPER_8_SYS_RESET_WIDTH 1
#define CSU_TAMPER_8_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_8_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_8_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_8_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_9
*/
#define CSU_TAMPER_9 ( ( CSU_BASEADDR ) + 0X00005028 )
#define CSU_TAMPER_9_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_9_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_9_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_9_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_9_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_9_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_9_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_9_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_9_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_9_SYS_RESET_SHIFT 1
#define CSU_TAMPER_9_SYS_RESET_WIDTH 1
#define CSU_TAMPER_9_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_9_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_9_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_9_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_10
*/
#define CSU_TAMPER_10 ( ( CSU_BASEADDR ) + 0X0000502C )
#define CSU_TAMPER_10_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_10_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_10_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_10_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_10_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_10_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_10_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_10_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_10_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_10_SYS_RESET_SHIFT 1
#define CSU_TAMPER_10_SYS_RESET_WIDTH 1
#define CSU_TAMPER_10_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_10_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_10_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_10_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_11
*/
#define CSU_TAMPER_11 ( ( CSU_BASEADDR ) + 0X00005030 )
#define CSU_TAMPER_11_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_11_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_11_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_11_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_11_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_11_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_11_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_11_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_11_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_11_SYS_RESET_SHIFT 1
#define CSU_TAMPER_11_SYS_RESET_WIDTH 1
#define CSU_TAMPER_11_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_11_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_11_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_11_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_12
*/
#define CSU_TAMPER_12 ( ( CSU_BASEADDR ) + 0X00005034 )
#define CSU_TAMPER_12_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_12_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_12_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_12_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_12_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_12_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_12_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_12_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_12_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_12_SYS_RESET_SHIFT 1
#define CSU_TAMPER_12_SYS_RESET_WIDTH 1
#define CSU_TAMPER_12_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_12_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_12_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_12_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_13
*/
#define CSU_TAMPER_13 ( ( CSU_BASEADDR ) + 0X00005038 )
#define CSU_TAMPER_13_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_13_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_13_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_13_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_13_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_13_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_13_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_13_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_13_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_13_SYS_RESET_SHIFT 1
#define CSU_TAMPER_13_SYS_RESET_WIDTH 1
#define CSU_TAMPER_13_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_13_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_13_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_13_SYS_INTERRUPT_MASK 0X00000001
/**
* Register: CSU_TAMPER_14
*/
#define CSU_TAMPER_14 ( ( CSU_BASEADDR ) + 0X0000503C )
#define CSU_TAMPER_14_BBRAM_ERASE_SHIFT 4
#define CSU_TAMPER_14_BBRAM_ERASE_WIDTH 1
#define CSU_TAMPER_14_BBRAM_ERASE_MASK 0X00000010
#define CSU_TAMPER_14_SEC_LOCKDOWN_1_SHIFT 3
#define CSU_TAMPER_14_SEC_LOCKDOWN_1_WIDTH 1
#define CSU_TAMPER_14_SEC_LOCKDOWN_1_MASK 0X00000008
#define CSU_TAMPER_14_SEC_LOCKDOWN_0_SHIFT 2
#define CSU_TAMPER_14_SEC_LOCKDOWN_0_WIDTH 1
#define CSU_TAMPER_14_SEC_LOCKDOWN_0_MASK 0X00000004
#define CSU_TAMPER_14_SYS_RESET_SHIFT 1
#define CSU_TAMPER_14_SYS_RESET_WIDTH 1
#define CSU_TAMPER_14_SYS_RESET_MASK 0X00000002
#define CSU_TAMPER_14_SYS_INTERRUPT_SHIFT 0
#define CSU_TAMPER_14_SYS_INTERRUPT_WIDTH 1
#define CSU_TAMPER_14_SYS_INTERRUPT_MASK 0X00000001
#ifdef __cplusplus
}
#endif
#endif /* _CSU_H_ */
<file_sep>/vitis_workspace/test_proj_pulse_ctrl/src/helloworld.c
/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/
#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "../drivers/cmd_handler.h"
int main()
{
init_platform();
print("Initializing board...\n\r");
if(cmd_init())
{
print("Failed to initialize board!\r\n");
}
else
{
print("Successfully initialized board!\r\n");
}
print("Waiting for command...\r\n");
while(1)
{
cmd_update_state();
}
cleanup_platform();
return 0;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_restart.h
/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPFW_RESTART_H_
#define XPFW_RESTART_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
#include "pm_master.h"
#define FSBL_STORE_ADDR (XPAR_MICROBLAZE_DDR_RESERVE_SA + 0x80000U)
#define FSBL_LOAD_ADDR 0xFFFC0000U
#define FSBL_IMAGE_SIZE (170U*1024U)
#define SHA3_HASH_LENGTH_IN_WORDS 12U
#define FSBL_STATE_PROC_SHIFT (0x1U)
#define FSBL_RUNNING_ON_A53 (0x1U << FSBL_STATE_PROC_SHIFT)
#define FSBL_RUNNING_ON_R5_0 (0x2U << FSBL_STATE_PROC_SHIFT)
#define FSBL_RUNNING_ON_R5_L (0x3U << FSBL_STATE_PROC_SHIFT)
#define FSBL_STATE_PROC_INFO_MASK (0x3U << FSBL_STATE_PROC_SHIFT)
#define FSBL_ENCRYPTION_STS_MASK (0x8U)
/* Structure for FSBL copy and APU restart */
typedef struct FSBL_Store_Restore_Info_Struct {
u32 FSBLImageHash[SHA3_HASH_LENGTH_IN_WORDS];
u8 IsOCM_Used;
}FSBL_Store_Restore_Info_Struct;
extern FSBL_Store_Restore_Info_Struct FSBL_Store_Restore_Info;
s32 XPfw_RecoveryInit(void);
void XPfw_RecoveryHandler(u8 ErrorId);
void XPfw_RecoveryAck(PmMaster *Master);
#if defined(USE_DDR_FOR_APU_RESTART) && defined(ENABLE_SECURE)
s32 XPfw_StoreFsblToDDR(void);
s32 XPfw_RestoreFsblToOCM(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* XPFW_RESTART_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilskey_v6_9/src/xilskey_eps_zynqmp_puf.c
/******************************************************************************
* Copyright (c) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xilskey_eps_zynqmp_puf.c
* This file contains the APIs for registering PUF, eFUSE programming and reading
* the PUF helper data, CHASH and Auxiliary data.
*
* </pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- --------------------------------------------------------
* 6.1 vns 10/17/16 First release.
* vns 11/07/16 Fixed shutter value to 0x0100005e, as sysosc selection
* is fixed for PUF registration.
* 6.2 vns 02/18/17 Added masking for PUF auxiliary read.
* 6.6 vns 06/06/18 Added doxygen tags
* 6.7 arc 01/05/19 Fixed MISRA-C violations.
* arc 03/15/19 Modified initial default status value as XST_FAILURE
* mmd 03/17/19 Handled buffer underflow issue and added timeouts during
* syndrome data reading
* rama 03/25/19 Added polling routine for PUF ready state
* 6.8 psl 06/07/19 Added doxygen tags.
* psl 06/25/19 Fixed Coverity warnings.
* psl 06/28/19 Added doxygen tags.
* psl 07/05/19 Added Asserts for validation.
* psl 07/23/19 Fixed input validation.
* psl 07/29/19 Fixed MISRA-C violation
* vns 08/29/19 Initialized Status variables
* 6.9 kpt 02/16/20 Fixed Coverity warnings
* kpt 02/27/20 Removed XilSKey_Puf_Debug2
* which is used only for debug purpose
* vns 03/18/20 Fixed Armcc compilation errors
* kal 03/18/20 Added Temp and Voltage checks before writing Puf Helper
* data, Puf Chash and Puf Aux.
* kpt 03/17/20 Replaced direct eFuse reads with cache reads
* and Error code is returned when user chooses
* read option as eFuse
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files *********************************/
#include "xilskey_eps_zynqmp_puf.h"
#include "xilskey_eps_zynqmp_hw.h"
#include "sleep.h"
/************************** Constant Definitions *****************************/
#define XILSKEY_PUF_STATUS_SYN_WRD_RDY_TIMEOUT (500000U)
/**************************** Type Definitions ******************************/
typedef enum {
XSK_EFUSEPS_PUF_REGISTRATION_STARTED,
XSK_EFUSEPS_PUF_REGISTRATION_COMPLETE
} XilsKey_PufRegistrationState;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
u32 XilSKey_ZynqMp_EfusePs_SetWriteConditions(void);
u32 XilSKey_ZynqMp_EfusePs_CheckForZeros(u8 RowStart, u8 RowEnd,
XskEfusePs_Type EfuseType);
u32 XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(u8 Row, u8 Column,
XskEfusePs_Type EfuseType);
u32 XilSKey_ZynqMp_EfusePs_ReadRow(u8 Row, XskEfusePs_Type EfuseType,
u32 *RowData);
u32 XilSKey_ZynqMp_EfusePs_Init(void);
void XilSKey_ZynqMp_EfusePs_SetTimerValues(void);
static INLINE u32 XilSkey_Puf_Validate_Access_Rules(u8 RequestType);
static INLINE u32 XilSKey_ZynqMp_EfusePs_CheckZeros_Puf(void);
static INLINE u32 XilSKey_ZynqMp_EfusePs_PufRowWrite(u8 Row, u8 *Data,
XskEfusePs_Type EfuseType);
static INLINE void XilSKey_Read_Puf_EfusePs_SecureBits_Regs(
XilSKey_Puf_Secure *SecureBits);
static u32 XilSKey_WaitForPufStatus(u32 *PufStatus);
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* This function programs the PS eFUSEs with the PUF helper data.
*
* @param InstancePtr Pointer to the XilSKey_Puf instance.
*
* @return
* - XST_SUCCESS if programs successfully.
* - Errorcode on failure
*
* @note To generate PufSyndromeData please use
* XilSKey_Puf_Registration API
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_WritePufHelprData(XilSKey_Puf *InstancePtr)
{
u8 Row;
u32 Data;
u32 *DataPtr;
u32 *TempPtr;
XskEfusePs_Type EfuseType;
u8 DataInBits[32] = {0};
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Initialize the ADC */
Status = XilSKey_ZynqMp_EfusePs_Init();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Vol and temperature checks */
Status = XilSKey_ZynqMp_EfusePs_Temp_Vol_Checks();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
DataPtr = InstancePtr->EfuseSynData;
TempPtr = InstancePtr->EfuseSynData;
/* Unlock the controller */
XilSKey_ZynqMp_EfusePs_CtrlrUnLock();
/* Check the unlock status */
if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus() != 0U) {
Status = (u32)(XSK_EFUSEPS_ERROR_CONTROLLER_LOCK);
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_SetWriteConditions();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Check for zeros */
Status = XilSKey_ZynqMp_EfusePs_CheckZeros_Puf();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_2;
/* Write Helper Data */
for (Row = 0U; Row <= XSK_ZYNQMP_EFUSEPS_PUF_ROW_END; Row++) {
if (Row == 0U) {
Data = (u32)(((*DataPtr) &
XSK_ZYNQMP_EFUSEPS_PUF_ROW_UPPER_MASK) >>
XSK_ZYNQMP_EFUSEPS_PUF_ROW_HALF_WORD_SHIFT);
}
else {
Data = (u32)((((*DataPtr) &
XSK_ZYNQMP_EFUSEPS_PUF_ROW_UPPER_MASK) >>
XSK_ZYNQMP_EFUSEPS_PUF_ROW_HALF_WORD_SHIFT) |
(((*TempPtr) & XSK_ZYNQMP_EFUSEPS_PUF_ROW_LOWER_MASK) <<
XSK_ZYNQMP_EFUSEPS_PUF_ROW_HALF_WORD_SHIFT));
}
TempPtr = DataPtr;
DataPtr++;
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&Data, DataInBits,
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
Status = XilSKey_ZynqMp_EfusePs_PufRowWrite(Row, DataInBits, EfuseType);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
}
DataPtr--;
EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_3;
for (Row = 0U; Row <= XSK_ZYNQMP_EFUSEPS_PUF_ROW_END; Row++) {
if (Row == 0U) {
Data = (u32)((*DataPtr) &
XSK_ZYNQMP_EFUSEPS_PUF_ROW_LOWER_MASK);
}
else {
Data = *DataPtr;
}
DataPtr++;
XilSKey_Efuse_ConvertBitsToBytes((u8 *)&Data, DataInBits,
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
Status = XilSKey_ZynqMp_EfusePs_PufRowWrite(Row, DataInBits,
EfuseType);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
}
END:
/* Lock the controller back */
XilSKey_ZynqMp_EfusePs_CtrlrLock();
XilSKey_ZynqMp_EfusePS_PrgrmDisable();
return Status;
}
/*****************************************************************************/
/**
* This function reads the PUF helper data from eFUSE.
*
* @param Address Pointer to data array which holds the PUF helper
* data read from eFUSEs.
*
* @return
* - XST_SUCCESS if reads successfully.
* - Errorcode on failure.
*
* @note This function only reads from eFUSE non-volatile memory. There
* is no option to read from Cache.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_ReadPufHelprData(u32 *Address)
{
u32 Status = (u32)XST_FAILURE;
u32 Row;
u32 RowDataVal[128] = {0U};
u32 *PtrEfuse2 = &RowDataVal[0];
u32 *PtrEfuse3 = &RowDataVal[64];
u32 *AddrPtr;
u32 Temp;
/* Assert validates the input arguments */
Xil_AssertNonvoid(Address != NULL);
AddrPtr = (u32 *)Address;
/* Unlock the controller */
XilSKey_ZynqMp_EfusePs_CtrlrUnLock();
/* Check the unlock status */
if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus() != 0U) {
Status = (u32)(XSK_EFUSEPS_ERROR_CONTROLLER_LOCK);
goto END;
}
/* Setting the timing Constraints */
XilSKey_ZynqMp_EfusePs_SetTimerValues();
for (Row = 0U; Row <= XSK_ZYNQMP_EFUSEPS_PUF_ROW_END; Row++) {
Status = XilSKey_ZynqMp_EfusePs_ReadRow((u8)Row,
XSK_ZYNQMP_EFUSEPS_EFUSE_2, PtrEfuse2);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_ReadRow((u8)Row,
XSK_ZYNQMP_EFUSEPS_EFUSE_3, PtrEfuse3);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
PtrEfuse2++;
PtrEfuse3++;
}
for (Row = 0U; Row < XSK_ZYNQMP_EFUSEPS_PUF_ROW_END; Row++) {
Temp = (RowDataVal[Row] & XSK_ZYNQMP_EFUSEPS_PUF_ROW_LOWER_MASK) <<
XSK_ZYNQMP_EFUSEPS_PUF_ROW_HALF_WORD_SHIFT;
Temp = ((RowDataVal[Row + 1] &
XSK_ZYNQMP_EFUSEPS_PUF_ROW_UPPER_MASK) >>
XSK_ZYNQMP_EFUSEPS_PUF_ROW_HALF_WORD_SHIFT) | Temp;
*AddrPtr = Temp;
AddrPtr++;
}
for (Row = XSK_ZYNQMP_EFUSEPS_PUF_ROW_END;
Row < (XSK_ZYNQMP_EFUSEPS_PUF_TOTAL_ROWS - 1U);
Row++) {
if (Row == XSK_ZYNQMP_EFUSEPS_PUF_ROW_END) {
Temp = (RowDataVal[Row] &
XSK_ZYNQMP_EFUSEPS_PUF_ROW_LOWER_MASK) <<
XSK_ZYNQMP_EFUSEPS_PUF_ROW_HALF_WORD_SHIFT;
Temp = Temp | ((RowDataVal[Row + 1] &
XSK_ZYNQMP_EFUSEPS_PUF_ROW_LOWER_MASK));
}
else {
Temp = RowDataVal[Row + 1];
}
*AddrPtr = Temp;
AddrPtr++;
}
END:
/* Lock the controller back */
XilSKey_ZynqMp_EfusePs_CtrlrLock();
return Status;
}
/*****************************************************************************/
/**
* This function programs eFUSE with CHash value.
*
* @param InstancePtr Pointer to the XilSKey_Puf instance.
*
* @return
* - XST_SUCCESS if chash is programmed successfully.
* - An Error code on failure
*
* @note To generate the CHash value, please use
* XilSKey_Puf_Registration function.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_WritePufChash(XilSKey_Puf *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
u8 Value[32] = {0U};
u8 Column;
XskEfusePs_Type EfuseType;
u32 RowDataVal = 0U;
u8 *PufChash;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Initialize the ADC */
Status = XilSKey_ZynqMp_EfusePs_Init();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Vol and temperature checks */
Status = XilSKey_ZynqMp_EfusePs_Temp_Vol_Checks();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
PufChash = (u8 *)&(InstancePtr->Chash);
/* Unlock the controller */
XilSKey_ZynqMp_EfusePs_CtrlrUnLock();
/* Check the unlock status */
if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus() != 0U) {
Status = (u32)(XSK_EFUSEPS_ERROR_CONTROLLER_LOCK);
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_SetWriteConditions();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0;
/* Check for Zeros */
XilSKey_ZynqMp_EfusePs_ReadPufChash(&RowDataVal,
XSK_EFUSEPS_READ_FROM_CACHE);
if (RowDataVal != 0X00U) {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_CHASH_ALREADY_PROGRAMMED;
goto END;
}
XilSKey_Efuse_ConvertBitsToBytes((u8 *)PufChash, Value,
XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW);
for (Column = 0U; Column < XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW;
Column++) {
if (Value[Column] != 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(
XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW,
Column, EfuseType);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
}
}
END:
/* Lock the controller back */
XilSKey_ZynqMp_EfusePs_CtrlrLock();
XilSKey_ZynqMp_EfusePS_PrgrmDisable();
return Status;
}
/*****************************************************************************/
/**
* This function reads eFUSE PUF CHash data from the eFUSE array or
* cache based on the user read option.
*
* @param Address Pointer which holds the read back value of the chash.
* @param ReadOption Indicates whether or not to read from the actual
* eFUSE array or from the eFUSE cache.
* - 0(XSK_EFUSEPS_READ_FROM_CACHE) Reads from cache
* - 1(XSK_EFUSEPS_READ_FROM_EFUSE) Reads from eFUSE array
*
* @return
* - XST_SUCCESS if programs successfully.
* - Errorcode on failure
*
* @note Cache reload is required for obtaining updated values for
* reading from cache..
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_ReadPufChash(u32 *Address, u8 ReadOption)
{
u32 Status = (u32)XST_FAILURE;
u32 *ChashPtr;
/* Assert validates the input arguments */
Xil_AssertNonvoid(Address != NULL);
Xil_AssertNonvoid((ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) ||
(ReadOption == XSK_EFUSEPS_READ_FROM_EFUSE));
ChashPtr = (u32 *)Address;
if (ReadOption == XSK_EFUSEPS_READ_FROM_EFUSE) {
Status = (u32)XSK_EFUSEPS_RD_FROM_EFUSE_NOT_ALLOWED;
}
else {
*ChashPtr = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PUF_CHASH_OFFSET);
Status = (u32)XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/**
* This function programs eFUSE PUF auxiliary data.
*
* @param InstancePtr Pointer to the XilSKey_Puf instance.
*
* @return
* - XST_SUCCESS if the eFUSE is programmed successfully.
* - Errorcode on failure
*
* @note To generate auxiliary data, please use
* XilSKey_Puf_Registration function.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_WritePufAux(XilSKey_Puf *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
u8 Value[32] = {0U};
u8 Column;
XskEfusePs_Type EfuseType;
u32 RowDataVal;
u8 *AuxValue;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Initialize the ADC */
Status = XilSKey_ZynqMp_EfusePs_Init();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Vol and temperature checks */
Status = XilSKey_ZynqMp_EfusePs_Temp_Vol_Checks();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
AuxValue = (u8 *)&(InstancePtr->Aux);
/* Unlock the controller */
XilSKey_ZynqMp_EfusePs_CtrlrUnLock();
/* Check the unlock status */
if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus() != 0U) {
Status = (u32)(XSK_EFUSEPS_ERROR_CONTROLLER_LOCK);
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_SetWriteConditions();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0;
/* Check for Zeros */
XilSKey_ZynqMp_EfusePs_ReadPufAux(&RowDataVal,
XSK_EFUSEPS_READ_FROM_CACHE);
if ((RowDataVal & XSK_ZYNQMP_EFUSEPS_PUF_MISC_AUX_MASK) != 0x00U) {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_AUX_ALREADY_PROGRAMMED;
goto END;
}
XilSKey_Efuse_ConvertBitsToBytes((u8 *)AuxValue, Value,
XSK_ZYNQMP_PUF_AUX_LEN_IN_BITS);
for (Column = 0U; Column < XSK_ZYNQMP_PUF_AUX_LEN_IN_BITS;
Column++) {
if (Value[Column] != 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(
XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW,
Column, EfuseType);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
}
}
END:
/* Lock the controller back */
XilSKey_ZynqMp_EfusePs_CtrlrLock();
XilSKey_ZynqMp_EfusePS_PrgrmDisable();
return Status;
}
/*****************************************************************************/
/**
* This function reads eFUSE PUF auxiliary data from eFUSE array
* or cache based on user read option.
*
* @param Address Pointer which holds the read back value of PUF's
* auxiliary data.
* @param ReadOption Indicates whether or not to read from the actual
* eFUSE array or from the eFUSE cache.
* - 0(XSK_EFUSEPS_READ_FROM_CACHE) Reads from cache
* - 1(XSK_EFUSEPS_READ_FROM_EFUSE) Reads from eFUSE array
*
* @return
* - XST_SUCCESS if PUF auxiliary data is read successfully.
* - Errorcode on failure
*
* @note Cache reload is required for obtaining updated values for
* reading from cache.
*
******************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_ReadPufAux(u32 *Address, u8 ReadOption)
{
u32 Status = (u32)XST_FAILURE;
u32 *AuxPtr;
/* Assert validates the input arguments */
Xil_AssertNonvoid(Address != NULL);
Xil_AssertNonvoid((ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) ||
(ReadOption == XSK_EFUSEPS_READ_FROM_EFUSE));
AuxPtr = (u32 *)Address;
if (ReadOption == XSK_EFUSEPS_READ_FROM_EFUSE) {
Status = (u32)XSK_EFUSEPS_RD_FROM_EFUSE_NOT_ALLOWED;
}
else {
*AuxPtr = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PUF_MISC_OFFSET) &
XSK_ZYNQMP_EFUSEPS_PUF_MISC_AUX_MASK;
Status = (u32)XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/**
* This function will poll for syndrome word is ready in the PUF_WORD register
* or till the timeout occurs.
*
* @param PufStatus Pointer to pufstatus.
*
* @return XST_SUCCESS - In case of Success
* XST_FAILURE - In case of Timeout.
*
* @note None.
*
******************************************************************************/
static u32 XilSKey_WaitForPufStatus(u32 *PufStatus)
{
u32 Timeout = XILSKEY_PUF_STATUS_SYN_WRD_RDY_TIMEOUT/100U;
u32 TimeoutFlag = (u32)XST_FAILURE;
while(Timeout != 0U) {
*PufStatus = XilSKey_ReadReg(XSK_ZYNQMP_CSU_BASEADDR,
XSK_ZYNQMP_CSU_PUF_STATUS);
if ((*PufStatus & XSK_ZYNQMP_CSU_PUF_STATUS_SYN_WRD_RDY_MASK) ==
XSK_ZYNQMP_CSU_PUF_STATUS_SYN_WRD_RDY_MASK) {
TimeoutFlag = (u32)XST_SUCCESS;
goto done;
}
usleep(100U);
Timeout--;
}
done:
return TimeoutFlag;
}
/*****************************************************************************/
/**
* This function performs registration of PUF which generates a new KEK
* and associated CHash, Auxiliary and PUF-syndrome data which are unique for
* each silicon.
*
* @param InstancePtr Pointer to the XilSKey_Puf instance.
*
* @return
- XST_SUCCESS if registration/re-registration was successful.
* - ERROR if registration was unsuccessful
*
* @note With the help of generated PUF syndrome data, it will be possible
* to re-generate same PUF KEK.
*
*****************************************************************************/
u32 XilSKey_Puf_Registration(XilSKey_Puf *InstancePtr)
{
u32 Status = (u32)XST_FAILURE;
u32 PufStatus = 0U;
u32 Index = 0U;
u32 Debug = XSK_PUF_DEBUG_GENERAL;
u32 MaxSyndromeSizeInWords;
XilsKey_PufRegistrationState RegistrationStatus;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
xPuf_printf(Debug,"API: PUF Registration\r\n");
/* Update the shutter value, as forced sysoc selection */
InstancePtr->ShutterValue = XSK_ZYNQMP_PUF_SHUTTER_VALUE;
Status = XilSkey_Puf_Validate_Access_Rules(XSK_ZYNQMP_PUF_REGISTRATION);
if(Status != (u32)XST_SUCCESS) {
xPuf_printf(Debug,"API: Registration Failed:0x%08x\r\n",
Status);
goto ENDF;
}
/* Update the PUF configuration registers */
XilSKey_WriteReg(XSK_ZYNQMP_CSU_BASEADDR,
XSK_ZYNQMP_CSU_PUF_CFG0, XSK_ZYNQMP_PUF_CFG0_INIT_VAL);
if (InstancePtr->RegistrationMode == XSK_ZYNQMP_PUF_MODE4K) {
XilSKey_WriteReg(XSK_ZYNQMP_CSU_BASEADDR,
XSK_ZYNQMP_CSU_PUF_CFG1, XSK_ZYNQMP_PUF_CFG1_INIT_VAL_4K);
MaxSyndromeSizeInWords = XSK_ZYNQMP_MAX_RAW_4K_PUF_SYN_LEN;
}
else {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_INVALID_REG_MODE;
xPuf_printf(Debug,"API:Invalid Registration Mode:0x%08x\r\n",
Status);
goto ENDF;
}
/* Configure the PUF shutter Value */
XilSKey_WriteReg(XSK_ZYNQMP_CSU_BASEADDR, XSK_ZYNQMP_CSU_PUF_SHUT,
InstancePtr->ShutterValue);
/**
* Request PUF to register.
* This will trigger an interrupt to CSUROM
*/
XilSKey_WriteReg(XSK_ZYNQMP_CSU_BASEADDR, XSK_ZYNQMP_CSU_PUF_CMD,
XSK_ZYNQMP_PUF_REGISTRATION);
RegistrationStatus = XSK_EFUSEPS_PUF_REGISTRATION_STARTED;
do {
Status = XilSKey_WaitForPufStatus(&PufStatus);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_TIMEOUT;
break;
}
if ((PufStatus & XSK_ZYNQMP_CSU_PUF_STATUS_OVERFLOW_MASK) ==
XSK_ZYNQMP_CSU_PUF_STATUS_OVERFLOW_MASK) {
xPuf_printf(Debug, "API: Overflow warning\r\n");
Status = (u32)XSK_EFUSEPS_ERROR_PUF_DATA_OVERFLOW;
break;
}
InstancePtr->SyndromeData[Index] =
XilSKey_ReadReg(XSK_ZYNQMP_CSU_BASEADDR,XSK_ZYNQMP_CSU_PUF_WORD);
if ((PufStatus & XSK_ZYNQMP_CSU_PUF_STATUS_KEY_RDY_MASK) ==
XSK_ZYNQMP_CSU_PUF_STATUS_KEY_RDY_MASK) {
if (Index < MaxSyndromeSizeInWords) {
xPuf_printf(Debug,
"API: Underflow warning (Syndrome Data Length = %d)\r\n",
Index);
Status = (u32)XSK_EFUSEPS_ERROR_PUF_DATA_UNDERFLOW;
break;
}
RegistrationStatus = XSK_EFUSEPS_PUF_REGISTRATION_COMPLETE;
/* Capture CHASH & AUX */
InstancePtr->Chash = InstancePtr->SyndromeData[Index];
InstancePtr->Aux = ((PufStatus &
XSK_ZYNQMP_CSU_PUF_STATUS_AUX_MASK) >> 4U);
/* Also move the CHASH & AUX into array */
InstancePtr->SyndromeData[XSK_ZYNQMP_PUF_SYN_LEN - 2U] =
InstancePtr->Chash;
InstancePtr->SyndromeData[XSK_ZYNQMP_PUF_SYN_LEN - 1U] =
((PufStatus & XSK_ZYNQMP_CSU_PUF_STATUS_AUX_MASK) << 4U);
Status = (u32)XST_SUCCESS;
xPuf_printf(Debug,"API: PUF Helper Data Generated!!!\r\n");
break;
}
Index++;
if (Index > MaxSyndromeSizeInWords)
{
xPuf_printf(Debug, "API: Overflow warning\r\n");
Status = (u32)XSK_EFUSEPS_ERROR_PUF_DATA_OVERFLOW;
break;
}
} while (RegistrationStatus != XSK_EFUSEPS_PUF_REGISTRATION_COMPLETE);
ENDF:
return Status;
}
/*****************************************************************************/
/**
* This function regenerates the PUF data so that the PUF's output can be used
* as the key source to the AES-GCM hardware cryptographic engine.
*
* @param InstancePtr is a pointer to the XilSKey_Puf instance.
*
* @return
* - XST_SUCCESS if regeneration was successful.
* - ERROR if regeneration was unsuccessful
*
******************************************************************************/
u32 XilSKey_Puf_Regeneration(XilSKey_Puf *InstancePtr)
{
u32 PufStatus;
u32 Status = (u32)XST_FAILURE;
u32 PufChash = 0U;
u32 Debug = XSK_PUF_DEBUG_GENERAL;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Status = XilSKey_ZynqMp_EfusePs_ReadPufChash(&PufChash,
XSK_EFUSEPS_READ_FROM_CACHE);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
if (PufChash == 0U) {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_INVALID_REQUEST;
xPuf_printf(Debug,"PUF regeneration is not allowed"
", as PUF data is not stored in eFuse\r\n");
goto END;
}
xPuf_printf(Debug,"API: PUF Regeneration\r\n");
/* Update the PUF configuration registers */
XilSKey_WriteReg(XSK_ZYNQMP_CSU_BASEADDR,
XSK_ZYNQMP_CSU_PUF_CFG0, XSK_ZYNQMP_PUF_CFG0_INIT_VAL);
/* Configure the PUF shutter Value */
XilSKey_WriteReg(XSK_ZYNQMP_CSU_BASEADDR, XSK_ZYNQMP_CSU_PUF_SHUT,
XSK_ZYNQMP_PUF_SHUTTER_VALUE);
/* PUF key to device key */
XilSKey_WriteReg(XSK_ZYNQMP_CSU_BASEADDR, XSK_ZYNQMP_CSU_PUF_CMD,
XSK_ZYNQMP_PUF_REGENERATION);
/* Wait till the data word ready */
usleep(3000);
PufStatus = XilSKey_ReadReg(XSK_ZYNQMP_CSU_BASEADDR,
XSK_ZYNQMP_CSU_ISR);
if ((PufStatus & XSK_ZYNQMP_CSU_ISR_PUF_ACC_ERROR_MASK) != 0x0U) {
xPuf_printf(Debug,"PufStatus : 0x%x \r\n", PufStatus);
Status = (u32)XSK_EFUSEPS_ERROR_PUF_ACCESS;
}
END:
return Status;
}
/*****************************************************************************/
/**
* This function programs the eFUSE PUF secure bits
*
* @param WriteSecureBits Pointer to the XilSKey_Puf_Secure
* structure
*
* @return
* - XST_SUCCESS if eFUSE PUF secure bits are programmed successfully.
* - Errorcode on failure.
*
******************************************************************************/
u32 XilSKey_Write_Puf_EfusePs_SecureBits(XilSKey_Puf_Secure *WriteSecureBits)
{
u32 Status = (u32)XST_FAILURE;
XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0;
u8 Row = XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW;
XilSKey_Puf_Secure SecureBits;
u32 Debug = XSK_PUF_DEBUG_GENERAL;
/* Assert validates the input arguments */
Xil_AssertNonvoid(WriteSecureBits != NULL);
/* If user requests any of the secure bit to be programmed */
if ((WriteSecureBits->SynInvalid != 0x00U) ||
(WriteSecureBits->SynWrLk != 0x00U) ||
(WriteSecureBits->RegisterDis != 0x00U) ||
(WriteSecureBits->Reserved != 0x00U)) {
/* Unlock the controller */
XilSKey_ZynqMp_EfusePs_CtrlrUnLock();
/* Check the unlock status */
if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus() != 0U) {
Status = (u32)(XSK_EFUSEPS_ERROR_CONTROLLER_LOCK);
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_SetWriteConditions();
if (Status != (u32)XST_SUCCESS) {
goto END;
}
XilSKey_Read_Puf_EfusePs_SecureBits_Regs(&SecureBits);
}
else {
Status = (u32)XST_SUCCESS;
goto END;
}
if ((WriteSecureBits->SynInvalid != 0x00U) &&
(SecureBits.SynInvalid == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_PUF_SYN_INVALID, EfuseType);
if (Status != (u32)XST_SUCCESS) {
xPuf_printf(Debug,"API: Failed programming Syndrome"
" invalid bit\r\n");
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_PUF_SYN_INVLD);
goto END;
}
}
if ((WriteSecureBits->SynWrLk != 0x00U) &&
(SecureBits.SynWrLk == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_PUF_SYN_LOCK, EfuseType);
if (Status != (u32)XST_SUCCESS) {
xPuf_printf(Debug,"API: Failed programming Syndrome"
" write lock bit\r\n");
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_PUF_SYN_WRLK);
goto END;
}
}
if ((WriteSecureBits->RegisterDis != 0x00U) &&
(SecureBits.RegisterDis == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_PUF_REG_DIS, EfuseType);
if (Status != (u32)XST_SUCCESS) {
xPuf_printf(Debug,"API: Failed programming register"
" disable bit\r\n");
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_PUF_SYN_REG_DIS);
goto END;
}
}
if ((WriteSecureBits->Reserved != 0x00U) &&
(SecureBits.Reserved == 0x00U)) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
XSK_ZYNQMP_EFUSEPS_PUF_RESERVED, EfuseType);
if (Status != (u32)XST_SUCCESS) {
xPuf_printf(Debug,"API: Failed programming reserved"
" bit\r\n");
Status = (Status |
(u32)XSK_EFUSEPS_ERROR_WRITE_PUF_RESERVED_BIT);
goto END;
}
}
Status = XilSKey_ZynqMp_EfusePs_CacheLoad();
END:
/* Lock the controller back */
XilSKey_ZynqMp_EfusePs_CtrlrLock();
XilSKey_ZynqMp_EfusePS_PrgrmDisable();
return Status;
}
/*****************************************************************************/
/**
* This function is used to read the PS eFUSE PUF secure bits from cache
* or from eFUSE array.
*
* @param SecureBits Pointer to the XilSKey_Puf_Secure structure
* which holds the read eFUSE secure bits from the PUF.
* @param ReadOption Indicates whether or not to read from the actual
* eFUSE array or from the eFUSE cache.
* - 0(XSK_EFUSEPS_READ_FROM_CACHE) Reads from cache
* - 1(XSK_EFUSEPS_READ_FROM_EFUSE) Reads from eFUSE array
*
* @return
* - XST_SUCCESS if reads successfully.
* - Errorcode on failure.
*
******************************************************************************/
u32 XilSKey_Read_Puf_EfusePs_SecureBits(
XilSKey_Puf_Secure *SecureBitsRead, u8 ReadOption)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(SecureBitsRead != NULL);
Xil_AssertNonvoid((ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) ||
(ReadOption == XSK_EFUSEPS_READ_FROM_EFUSE));
if (ReadOption == XSK_EFUSEPS_READ_FROM_CACHE) {
XilSKey_Read_Puf_EfusePs_SecureBits_Regs(
SecureBitsRead);
Status = XST_SUCCESS;
}
else {
Status = (u32)XSK_EFUSEPS_RD_FROM_EFUSE_NOT_ALLOWED;
}
return Status;
}
/*****************************************************************************/
/**
* This function is used to read the PS eFUSE PUF secure bits from cache
* or from eFUSE array based on user selection.
*
* @param SecureBits is the pointer to the XilSKey_Puf_Secure
* which holds the read eFUSE secure bits of PUF.
*
* @note None.
*
******************************************************************************/
static INLINE void XilSKey_Read_Puf_EfusePs_SecureBits_Regs(
XilSKey_Puf_Secure *SecureBits)
{
u32 RegData = 0U;
RegData = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR,
XSK_ZYNQMP_EFUSEPS_PUF_MISC_OFFSET);
SecureBits->SynInvalid =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_INVLD_MASK) >>
XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_INVLD_SHIFT);
SecureBits->SynWrLk =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_WRLK_MASK) >>
XSK_ZYNQMP_EFUSEPS_PUF_MISC_SYN_WRLK_SHIFT);
SecureBits->RegisterDis =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_PUF_MISC_REG_DIS_MASK) >>
XSK_ZYNQMP_EFUSEPS_PUF_MISC_REG_DIS_SHIFT);
SecureBits->Reserved =
(u8)((RegData & XSK_ZYNQMP_EFUSEPS_PUF_MISC_RESERVED_MASK) >>
XSK_ZYNQMP_EFUSEPS_PUF_MISC_RESERVED_SHIFT);
}
/***************************************************************************/
/**
* This API programs the given data into specified row of eFUSE.
*
* @param Row specifies the row number to be programmed.
* @param Data is pointer to 32 bit variable which holds data to be
* programmed.
*
* @return
* - XST_SUCCESS if programs successfully.
* - Errorcode on failure
*
* @note None.
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_PufRowWrite(u8 Row,
u8 *Data, XskEfusePs_Type EfuseType)
{
u8 Column;
u32 Status = (u32)XST_FAILURE;
for (Column = 0U; Column < XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW;
Column++) {
if (Data[Column] != 0x00U) {
Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row,
Column, EfuseType);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
}
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/***************************************************************************/
/**
* This function checks whether PUF is already programmed or not.
*
* @param None.
*
* @return
* - XST_SUCCESS if all rows are zero
* - Errorcode if already programmed.
*
* @note None.
*
******************************************************************************/
static INLINE u32 XilSKey_ZynqMp_EfusePs_CheckZeros_Puf(void)
{
u32 RowDataVal = 0U;
u32 Status = (u32)XST_FAILURE;
/*
* By the time of checking PUF syndrome data T bits
* might be programmed so complete 0th row cannot
* be checked as zeroth row contains Tbits
*/
Status = XilSKey_ZynqMp_EfusePs_ReadRow(
XSK_ZYNQMP_EFUSEPS_PUF_ROW_START,
XSK_ZYNQMP_EFUSEPS_EFUSE_2, &RowDataVal);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
if ((RowDataVal & (~(XSK_ZYNQMP_EFUSEPS_TBITS_MASK <<
XSK_ZYNQMP_EFUSEPS_TBITS_SHIFT))) != 0x00U) {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_DATA_ALREADY_PROGRAMMED;
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_ReadRow(
XSK_ZYNQMP_EFUSEPS_PUF_ROW_START,
XSK_ZYNQMP_EFUSEPS_EFUSE_3, &RowDataVal);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
if ((RowDataVal & (~(XSK_ZYNQMP_EFUSEPS_TBITS_MASK <<
XSK_ZYNQMP_EFUSEPS_TBITS_SHIFT))) != 0x00U) {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_DATA_ALREADY_PROGRAMMED;
goto END;
}
if (XilSKey_ZynqMp_EfusePs_CheckForZeros(
(XSK_ZYNQMP_EFUSEPS_PUF_ROW_START + 1U),
XSK_ZYNQMP_EFUSEPS_PUF_ROW_END, XSK_ZYNQMP_EFUSEPS_EFUSE_2) !=
(u32)XST_SUCCESS) {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_DATA_ALREADY_PROGRAMMED;
goto END;
}
if (XilSKey_ZynqMp_EfusePs_CheckForZeros(
(XSK_ZYNQMP_EFUSEPS_PUF_ROW_START + 1U),
XSK_ZYNQMP_EFUSEPS_PUF_ROW_END,
XSK_ZYNQMP_EFUSEPS_EFUSE_3) != (u32)XST_SUCCESS) {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_DATA_ALREADY_PROGRAMMED;
goto END;
}
END:
return Status;
}
/*****************************************************************************/
/**
*
* Validates the PUF access rules
*
* @param RequestType is an input to validate the access rules against
* Registration, Re-registration, Testmode1 & Testmode2
*
* @return XST_SUCCESS if validation was successful.
* ERROR if validation failed
*
* @note None
*
******************************************************************************/
static INLINE u32 XilSkey_Puf_Validate_Access_Rules(u8 RequestType)
{
u32 PufChash = 0U;
u32 PufAux = 0U;
u32 Status = (u32)XST_FAILURE;
u32 Debug = XSK_PUF_DEBUG_GENERAL;
XilSKey_SecCtrlBits ReadSecCtrlBits = {0U};
XilSKey_Puf_Secure PufSecureBits = {0U};
/* Read secure control register for RSA bits value from eFUSE */
Status = XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits(&ReadSecCtrlBits,
XSK_EFUSEPS_READ_FROM_CACHE);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
/* Reading PUF secure bits */
Status = XilSKey_Read_Puf_EfusePs_SecureBits(&PufSecureBits,
XSK_EFUSEPS_READ_FROM_CACHE);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_ReadPufAux(&PufAux,
XSK_EFUSEPS_READ_FROM_CACHE);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
Status = XilSKey_ZynqMp_EfusePs_ReadPufChash(&PufChash,
XSK_EFUSEPS_READ_FROM_CACHE);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
if (RequestType == XSK_ZYNQMP_PUF_REGISTRATION) {
/**
* To allow registration
* 1. Make sure that PUF registration is not disabled
* 2. If it re-registration then
* 2.1 Make sure that use RSA bits set in eFUSE.
*/
if (PufSecureBits.RegisterDis != 0U ) {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_REG_DISABLED;
xPuf_printf(Debug,
"API: PUF Registration not allowed "
"(Disabled in eFUSE):0x%08x\r\n",Status);
}
else if ((PufChash != 0U) || (PufAux != 0U)) {
if (ReadSecCtrlBits.RSAEnable == 0U) {
Status =
(u32)XSK_EFUSEPS_ERROR_PUF_REG_WO_AUTH;
xPuf_printf(Debug,
"API:Registration not allowed w/o "
"Authentication:0x%08x\r\n", Status);
}
}
else {
Status = (u32)XST_SUCCESS;
}
}
else {
Status = (u32)XSK_EFUSEPS_ERROR_PUF_INVALID_REQUEST;
xPuf_printf(Debug,
"API: Invalid Request type for validation:0x%08x\r\n",
Status);
}
END:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/libsrc/clockps_v1_2/src/xclockps_hw.h
/******************************************************************************
* Copyright (C) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xclockps_hw.h
* @addtogroup xclockps_v1_2
* @{
*
* This file contains the hardware details for the System Clock controller.
*
* <pre>
* MODIFICATION HISTORY:
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------
* 1.00 cjp 02/09/18 First release
* </pre>
*
******************************************************************************/
#ifndef XCLOCK_HW_H /* prevent circular inclusions */
#define XCLOCK_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/* CRL APB register defines */
#define CRL_APB_BASE_ADDR XPAR_PSU_CRL_APB_S_AXI_BASEADDR
#define IOPLL_CTRL (u32)(CRL_APB_BASE_ADDR + 0x20)
#define RPLL_CTRL (u32)(CRL_APB_BASE_ADDR + 0x30)
#define IOPLL_TO_FPD_CTRL (u32)(CRL_APB_BASE_ADDR + 0x44)
#define RPLL_TO_FPD_CTRL (u32)(CRL_APB_BASE_ADDR + 0x48)
#define USB3_DUAL_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x4C)
#define GEM0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x50)
#define GEM1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x54)
#define GEM2_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x58)
#define GEM3_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x5C)
#define USB0_BUS_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x60)
#define USB1_BUS_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x64)
#define QSPI_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x68)
#define SDIO0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x6C)
#define SDIO1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x70)
#define UART0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x74)
#define UART1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x78)
#define SPI0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x7C)
#define SPI1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x80)
#define CAN0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x84)
#define CAN1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x88)
#define CPU_R5_CTRL (u32)(CRL_APB_BASE_ADDR + 0x90)
#define IOU_SWITCH_CTRL (u32)(CRL_APB_BASE_ADDR + 0x9C)
#define CSU_PLL_CTRL (u32)(CRL_APB_BASE_ADDR + 0xA0)
#define PCAP_CTRL (u32)(CRL_APB_BASE_ADDR + 0xA4)
#define LPD_SWITCH_CTRL (u32)(CRL_APB_BASE_ADDR + 0xA8)
#define LPD_LBUS_CTRL (u32)(CRL_APB_BASE_ADDR + 0xAC)
#define DBG_LPD_CTRL (u32)(CRL_APB_BASE_ADDR + 0xB0)
#define NAND_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xB4)
#define LPDDMA_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xB8)
#define PL0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xC0)
#define PL1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xC4)
#define PL2_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xC8)
#define PL3_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xCC)
#define GEM_TSU_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x100)
#define DLL_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x104)
#define PSSYSMON_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x108)
#define I2C0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x120)
#define I2C1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x124)
#define TSTMP_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x128)
/* CRF APB register defines */
#define CRF_APB_BASE_ADDR XPAR_PSU_CRF_APB_S_AXI_BASEADDR
#define APLL_CTRL (u32)(CRF_APB_BASE_ADDR + 0x20)
#define DPLL_CTRL (u32)(CRF_APB_BASE_ADDR + 0x2C)
#define VPLL_CTRL (u32)(CRF_APB_BASE_ADDR + 0x38)
#define APLL_TO_LPD_CTRL (u32)(CRF_APB_BASE_ADDR + 0x48)
#define PLL_STATUS (u32)(CRF_APB_BASE_ADDR + 0x44)
#define DPLL_TO_LPD_CTRL (u32)(CRF_APB_BASE_ADDR + 0x4C)
#define VPLL_TO_LPD_CTRL (u32)(CRF_APB_BASE_ADDR + 0x50)
#define ACPU_CTRL (u32)(CRF_APB_BASE_ADDR + 0x60)
#define DBG_TRACE_CTRL (u32)(CRF_APB_BASE_ADDR + 0x64)
#define DBG_FPD_CTRL (u32)(CRF_APB_BASE_ADDR + 0x68)
#define DP_VIDEO_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0x70)
#define DP_AUDIO_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0x74)
#define DP_STC_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0x7C)
#define DDR_CTRL (u32)(CRF_APB_BASE_ADDR + 0x80)
#define GPU_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0x84)
#define SATA_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0xA0)
#define PCIE_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0xB4)
#define FPDDMA_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0xB8)
#define DPDMA_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0xBC)
#define TOPSW_MAIN_CTRL (u32)(CRF_APB_BASE_ADDR + 0xC0)
#define TOPSW_LSBUS_CTRL (u32)(CRF_APB_BASE_ADDR + 0xC4)
#define GTGREF0_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0xC8)
#define DBG_TSTMP_CTRL (u32)(CRF_APB_BASE_ADDR + 0xF8)
/* IOU SLCR defines */
#define IOU_SLCR_BASE_ADDR XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR
#define WDT_CLK_SEL (u32)(IOU_SLCR_BASE_ADDR + 0x300)
#define CAN_CLK_CTRL (u32)(IOU_SLCR_BASE_ADDR + 0x304)
#define GEM_CLK_CTRL (u32)(IOU_SLCR_BASE_ADDR + 0x308)
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilfpga_v5_2/src/interface/zynqmp/xilfpga_pcap.c
/******************************************************************************
* Copyright (c) 2016 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilfpga_pcap.c
*
* This file contains the definitions of bitstream loading functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 Nava 08/06/16 Initial release
* 1.1 Nava 16/11/16 Added PL power-up sequence.
* 2.0 Nava 10/1/17 Added Encrypted bitstream loading support.
* 2.0 Nava 16/02/17 Added Authenticated bitstream loading support.
* 2.1 Nava 06/05/17 Correct the check logic issues in
* XFpga_PL_BitStream_Load()
* to avoid the unwanted blocking conditions.
* 3.0 Nava 12/05/17 Added PL configuration registers readback support.
* 4.0 Nava 08/02/18 Added Authenticated and Encypted Bitstream
* loading support.
* 4.0 Nava 02/03/18 Added the legacy bit file loading feature support
* from U-boot.
* and improve the error handling support by returning the
* proper ERROR value upon error conditions.
* 4.1 Nava 7/03/18 For Secure Bitstream loading to avoid the Security
* violations Need to Re-validate the User Crypto flags
* with the Image Crypto operation by using the internal
* memory.To Fix this added a new API
* XFpga_ReValidateCryptoFlags().
* 4.1 Nava 16/04/18 Added partial bitstream loading support.
* 4.2 Nava 08/06/16 Refactor the xilfpga library to support
* different PL programming Interfaces.
* 4.2 adk 11/07/18 Added support for readback of PL configuration data.
* 4.2 Nava 22/07/18 Added XFpga_SelectEndianess() new API to Support
* programming the vivado generated .bit and .bin files.
* 4.2 Nava 16/08/18 Modified the PL data handling Logic to support
* different PL programming interfaces.
* 4.2 adk 23/08/18 Added support for unaligned bitstream programming.
* 4.2 adk 28/08/18 Fixed misra-c required standard violations.
* 4.2 Nava 15/09/18 Fixed global function call-backs issue.
* 5.0 Nava 10/01/19 Improve the PS-PL resets handling.
* 5.0 Nava 10/01/19 Improve the Image validation handling logic for
* bootgen created Bitstream Images.
* 5.0 Div 21/01/19 Fixed misra-c required standard violations.
* 5.0 Nava 06/02/19 Remove redundant API's from the interface agnostic layer
* and make the existing API's generic to support both
* ZynqMP and versal platforms.
* 5.0 Nava 26/02/19 Fix for power-up PL issue with pmufw.
* 5.0 Nava 26/02/19 Update the data handling logic to avoid the code
* duplication
* 5.0 Nava 28/02/19 Handling all the 4 PS-PL resets irrespective of the
* design configuration.
* 5.0 vns 12/03/19 Modified secure stream switch related functions.
* 5.0 Nava 19/03/19 In the current implementation, the SecureIv variable
* is sharing between xilfpga and Xilsecure libraries.
* To avoid data sharing conflicts removed SecureIV
* shared variable dependency.
* 5.0 Nava 21/03/19 Added Address alignment check. As CSUDMA expects word
* aligned address. In case user passes an unaligned
* address return error.
* 5.0 sne 27/03/19 Fixed misra-c violations.
* 5.0 Nava 23/04/19 Optimize the API's logic to avoid code duplication.
* 5.1 Nava 27/06/19 Adds support to clear out the SHA3 engine.
* 5.1 Nava 05/07/19 Zeroize the Secure data to avoid security violations.
* 5.1 Nava 16/07/19 Begin all functions return status with failure and return
* to success only on successful completion of the operation
* of the functions.
* 5.1 Nava 16/07/19 Improve error handling in the bitstream validation path.
* 5.2 Nava 11/10/19 Clear the key info from DDR or Physical memory Once it
* preserves into the internal memory.
* 5.2 Nava 1/11/19 Clear the Aes-key info from internal memory after
* completion of its usage.
* 5.2 Nava 14/11/19 Rename the XFpga_GetPLConfigData() function name
* to improve the code readability.
* 5.2 Nava 06/12/19 Removed unwanted pcap interface status check In
* XFpga_DecrypSecureHdr path.
* 5.2 Nava 18/12/19 Fix for security violation in the readback path.
* 5.2 Nava 02/01/20 Added conditional compilation support for readback feature.
* 5.2 Nava 21/01/20 Replace event poll logic with Xil_WaitForEvent() API.
* 5.2 Nava 20/02/20 Updated SECURE_MODE check handling logic by using conditional
* compilation macro to Optimize XFpga_Validate BitstreamImage
* function
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xilfpga.h"
/************************** Constant Definitions *****************************/
#ifdef __MICROBLAZE__
#define XPBR_SERV_EXT_PWRUPPLD 119U
#define XPBR_SERV_EXT_PLNONPCAPISO 162U
#define XPBR_SERV_EXT_TBL_MAX 256U
#endif
#define WORD_LEN 4U /* Bytes */
#ifdef XFPGA_SECURE_MODE
#define KEY_LEN 64U /* Bytes */
#define IV_LEN 24U /* Bytes */
#define GCM_TAG_LEN 128U /* Bytes */
#define MAX_NIBBLES 8U
#define SIGNATURE_LEN 512U /* Bytes */
#define RSA_HASH_LEN 48U /* Bytes */
#define HASH_LEN 48U /* Bytes */
#define OCM_PL_ADDR XFPGA_OCM_ADDRESS
#define AC_LEN (0xEC0U)
#define PL_PARTATION_SIZE (0x800000U)
#define PL_CHUNK_SIZE_BYTES (1024U * 56U)
#define NUM_OF_PL_CHUNKS(Size) ((Size) / PL_CHUNK_SIZE_BYTES)
#endif
/**
* Name Configuration Type1 packet headers masks
*/
#define XDC_TYPE_SHIFT 29U
#define XDC_REGISTER_SHIFT 13U
#define XDC_OP_SHIFT 27U
#define XDC_TYPE_1 1U
#define XDC_TYPE_2 2U
#define OPCODE_NOOP 0U
#define OPCODE_READ 1U
#define OPCODE_WRITE 2U
#define XFPGA_DESTINATION_PCAP_ADDR (0XFFFFFFFFU)
#define XFPGA_PART_IS_ENC (0x00000080U)
#define XFPGA_PART_IS_AUTH (0x00008000U)
#define DUMMY_BYTE (0xFFU)
#define SYNC_BYTE_POSITION 64U
#define BOOTGEN_DATA_OFFSET 0x2800U
#define XFPGA_ADDR_WORD_ALIGN_MASK (0x3U)
#define XFPGA_AES_TAG_SIZE (XSECURE_SECURE_HDR_SIZE + \
XSECURE_SECURE_GCM_TAG_SIZE) /* AES block decryption tag size */
#define XFPGA_REG_CONFIG_CMD_LEN 9U
#define XFPGA_DATA_CONFIG_CMD_LEN 88U
/* Firmware State Definitions */
#define XFPGA_FIRMWARE_STATE_UNKNOWN 0U
#define XFPGA_FIRMWARE_STATE_SECURE 1U
#define XFPGA_FIRMWARE_STATE_NONSECURE 2U
/* PS-PL Reset Time */
#define XFPGA_PS_PL_RESET_TIME_US 1U
/**************************** Type Definitions *******************************/
#ifdef __MICROBLAZE__
typedef u32 (*XpbrServHndlr_t) (void);
#endif
/***************** Macros (Inline Functions) Definitions *********************/
#define ARRAY_LENGTH(array) (sizeof((array))/sizeof((array)[0]))
#ifdef XFPGA_SECURE_READBACK_MODE
#define XFPGA_SECURE_READBACK_MODE_EN 1U
#else
#define XFPGA_SECURE_READBACK_MODE_EN 0U
#endif
/************************** Function Prototypes ******************************/
static u32 XFpga_PcapWaitForDone(void);
static u32 XFpga_PcapWaitForidle(void);
static u32 XFpga_WriteToPcap(u32 Size, UINTPTR BitstreamAddr);
static u32 XFpga_PcapInit(u32 Flags);
static u32 XFpga_PLWaitForDone(void);
static u32 XFpga_PowerUpPl(void);
static u32 XFpga_IsolationRestore(void);
void XFpga_PsPlGpioResetsLow(void);
void XFpga_PsPlGpioResetsHigh(void);
static u32 Xfpga_RegAddr(u8 Register, u8 OpCode, u16 Size);
static u32 Xfpga_Type2Pkt(u8 OpCode, u32 Size);
static u32 XFpga_ValidateCryptoFlags(const XSecure_ImageInfo *ImageInfo,
u32 flags);
static u32 XFpga_ValidateBitstreamImage(XFpga *InstancePtr);
static u32 XFpga_PreConfigPcap(XFpga *InstancePtr);
static u32 XFpga_WriteToPlPcap(XFpga *InstancePtr);
static u32 XFpga_PostConfigPcap(XFpga *InstancePtr);
static u32 XFpga_PcapStatus(void);
static u32 XFpga_GetConfigRegPcap(const XFpga *InstancePtr);
static u32 XFpga_GetPLConfigDataPcap(const XFpga *InstancePtr);
static void XFpga_SetFirmwareState(u8 State);
static u8 XFpga_GetFirmwareState(void);
static u32 XFpga_SelectEndianess(u8 *Buf, u32 Size, u32 *Pos);
#ifdef XFPGA_SECURE_MODE
static u32 XFpga_SecureLoadToPl(XFpga *InstancePtr);
static u32 XFpga_WriteEncryptToPcap(XFpga *InstancePtr);
static u32 XFpga_SecureBitstreamLoad(XFpga *InstancePtr);
static u32 XFpga_AuthPlChunksDdrOcm(XFpga *InstancePtr, u32 Size);
static u32 XFpga_AuthPlChunks(UINTPTR BitstreamAddr, u32 Size, UINTPTR AcAddr);
static u32 XFpga_ReAuthPlChunksWriteToPl(XFpgaPs_PlPartition *PlAesInfo,
UINTPTR BitstreamAddr,
u32 Size, u32 Flags);
static u32 XFpga_DecrptPlChunks(XFpgaPs_PlPartition *PartitionParams,
u64 ChunkAdrs, u32 ChunkSize);
static u32 XFpga_DecrptSetUpNextBlk(XFpgaPs_PlPartition *PartitionParams);
static void XFpga_DmaPlCopy(XCsuDma *InstancePtr, UINTPTR Src,
u32 Size, u8 EnLast);
static u32 XFpga_DecrptPl(XFpgaPs_PlPartition *PartitionParams,
u64 ChunkAdrs, u32 ChunkSize);
static u32 XFpga_DecrypSecureHdr(XSecure_Aes *InstancePtr, u64 SrcAddr);
static u32 XFpga_AesInit(XSecure_Aes *InstancePtr, u32 *AesKupKey,
u32* IvPtr, char *KeyPtr, u32 Flags);
#endif
#ifdef __MICROBLAZE__
extern const XpbrServHndlr_t XpbrServHndlrTbl[XPBR_SERV_EXT_TBL_MAX];
#endif
/************************** Variable Definitions *****************************/
static XCsuDma *CsuDmaPtr;
/* Xilinx ZynqMp Vivado generated Bitstream header format */
static const u8 VivadoBinFormat[] = {
0x00U, 0x00U, 0x00U, 0xBBU, /* Bus Width Sync Word */
0x11U, 0x22U, 0x00U, 0x44U, /* Bus Width Detect Pattern */
0xFFU, 0xFFU, 0xFFU, 0xFFU,
0xFFU, 0xFFU, 0xFFU, 0xFFU,
0xAAU, 0x99U, 0x55U, 0x66U, /* Sync Word */
};
/* Xilinx ZynqMp Bootgen generated Bitstream header format */
static const u8 BootgenBinFormat[] = {
0xBBU, 0x00U, 0x00U, 0x00U, /* Bus Width Sync Word */
0x44U, 0x00U, 0x22U, 0x11U, /* Bus Width Detect Pattern */
0xFFU, 0xFFU, 0xFFU, 0xFFU,
0xFFU, 0xFFU, 0xFFU, 0xFFU,
0x66U, 0x55U, 0x99U, 0xAAU, /* Sync Word */
};
/*****************************************************************************/
/* This API when called initializes the XFPGA interface with default settings.
* It Sets function pointers for the instance.
*
* @param InstancePtr Pointer to the XFgpa structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
******************************************************************************/
u32 XFpga_Initialize(XFpga *InstancePtr) {
u32 Status = XFPGA_FAILURE;
(void)memset(InstancePtr, 0, sizeof(*InstancePtr));
InstancePtr->XFpga_ValidateBitstream = XFpga_ValidateBitstreamImage;
InstancePtr->XFpga_PreConfig = XFpga_PreConfigPcap;
InstancePtr->XFpga_WriteToPl = XFpga_WriteToPlPcap;
InstancePtr->XFpga_PostConfig = XFpga_PostConfigPcap;
InstancePtr->XFpga_GetInterfaceStatus = XFpga_PcapStatus;
InstancePtr->XFpga_GetConfigReg = XFpga_GetConfigRegPcap;
InstancePtr->XFpga_GetConfigData = XFpga_GetPLConfigDataPcap;
/* Initialize CSU DMA driver */
CsuDmaPtr = Xsecure_GetCsuDma();
if (CsuDmaPtr == NULL) {
Status = XFPGA_PCAP_UPDATE_ERR(XFPGA_ERROR_CSUDMA_INIT_FAIL,
XFPGA_FAILURE);
} else {
Status = XFPGA_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/* This function validate the Image image's boot header and image header,
* also copies all the required details to the ImageInfo pointer.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return Returns Status
* - XST_SUCCESS on success
* - Error code on failure
* - XSECURE_AUTH_NOT_ENABLED - represents image is not
* authenticated.
*
*****************************************************************************/
static u32 XFpga_ValidateBitstreamImage(XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
XSecure_ImageInfo *ImageHdrDataPtr =
&InstancePtr->PLInfo.SecureImageInfo;
u32 BitstreamPos = 0U;
u32 PartHeaderOffset = 0U;
#ifndef XFPGA_SECURE_MODE
if (InstancePtr->WriteInfo.Flags & XFPGA_SECURE_FLAGS != 0U) {
Status = XFPGA_PCAP_UPDATE_ERR((u32)XFPGA_ERROR_SECURE_MODE_EN,
(u32)0U);
Xfpga_Printf(XFPGA_DEBUG, "Fail to load: Enable secure mode "
"and try Error Code: 0x%08x\r\n", Status);
goto END;
}
#endif
if ((InstancePtr->WriteInfo.BitstreamAddr &
XFPGA_ADDR_WORD_ALIGN_MASK) != 0U) {
/* If the Address is not Word aligned return failure */
Status = XFPGA_ERROR_UNALIGN_ADDR;
goto END;
}
if ((InstancePtr->WriteInfo.Flags & XFPGA_SECURE_FLAGS) == 0U) {
/* eFUSE checks */
if ((XSecure_IsRsaEnabled() == XSECURE_ENABLED) ||
(XSecure_IsEncOnlyEnabled() == XSECURE_ENABLED)) {
Status = XFPGA_PCAP_UPDATE_ERR(
(u32)XFPGA_ERROR_EFUSE_CHECK, (u32)0U);
goto END;
}
if((u32)(memcmp((u8 *)(InstancePtr->WriteInfo.BitstreamAddr +
BOOTGEN_DATA_OFFSET + SYNC_BYTE_POSITION),
BootgenBinFormat, ARRAY_LENGTH(BootgenBinFormat)))== 0U) {
BitstreamPos = BOOTGEN_DATA_OFFSET;
} else {
Status = XFpga_SelectEndianess(
(u8 *)InstancePtr->WriteInfo.BitstreamAddr,
(u32)InstancePtr->WriteInfo.AddrPtr_Size,
&BitstreamPos);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(Status, (u32)0U);
goto END;
}
goto UPDATE;
}
}
Status = XSecure_AuthenticationHeaders(
(u8 *)InstancePtr->WriteInfo.BitstreamAddr,
ImageHdrDataPtr);
if (Status != XFPGA_SUCCESS) {
if (Status != XSECURE_AUTH_NOT_ENABLED) {
Status = XFPGA_PCAP_UPDATE_ERR(XFPGA_ERROR_HDR_AUTH, Status);
goto END;
}
}
/* Validate the User Flags for the Image Crypto operation */
Status = XFpga_ValidateCryptoFlags(ImageHdrDataPtr,
InstancePtr->WriteInfo.Flags);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR((u32)XFPGA_ERROR_CRYPTO_FLAGS, (u32)0U);
Xfpga_Printf(XFPGA_DEBUG,
"Crypto flags not matched with Image crypto operation "
"with Error Code:0x%08x\r\n", Status);
goto END;
}
UPDATE:
if ((InstancePtr->WriteInfo.Flags & XFPGA_SECURE_FLAGS) == 0U) {
if (BitstreamPos == BOOTGEN_DATA_OFFSET) {
PartHeaderOffset = Xil_In32(
InstancePtr->WriteInfo.BitstreamAddr
+ PARTATION_HEADER_OFFSET);
InstancePtr->WriteInfo.AddrPtr_Size =
Xil_In32(InstancePtr->WriteInfo.BitstreamAddr +
PartHeaderOffset) * WORD_LEN;
} else {
InstancePtr->WriteInfo.AddrPtr_Size -= BitstreamPos;
}
InstancePtr->WriteInfo.BitstreamAddr += BitstreamPos;
}
END:
return Status;
}
/*****************************************************************************/
/** This function prepare the FPGA to receive configuration data.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
* - XFPGA_ERROR_PL_POWER_UP
* - XFPGA_ERROR_PL_ISOLATION
* - XPFGA_ERROR_PCAP_INIT
*
*****************************************************************************/
static u32 XFpga_PreConfigPcap(XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
u32 RegVal;
/* Enable the PCAP clk */
RegVal = Xil_In32(PCAP_CLK_CTRL);
Xil_Out32(PCAP_CLK_CTRL, RegVal | PCAP_CLK_EN_MASK);
if ((InstancePtr->WriteInfo.Flags & XFPGA_PARTIAL_EN) == 0U) {
/* Power-Up PL */
Status = XFpga_PowerUpPl();
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG,
"XFPGA_ERROR_PL_POWER_UP\r\n");
Status = XFPGA_PCAP_UPDATE_ERR(
(u32)XFPGA_ERROR_PL_POWER_UP, (u32)0U);
goto END;
}
/* PS PL Isolation Restore */
Status = XFpga_IsolationRestore();
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG,
"XFPGA_ERROR_PL_ISOLATION\r\n");
Status = XFPGA_PCAP_UPDATE_ERR(
(u32)XFPGA_ERROR_PL_ISOLATION, (u32)0U);
goto END;
}
}
Status = XFpga_PcapInit(InstancePtr->WriteInfo.Flags);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR((u32)XPFGA_ERROR_PCAP_INIT, (u32)0U);
}
END:
return Status;
}
/*****************************************************************************/
/* This function write count bytes of configuration data into the PL.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
* - XFPGA_ERROR_BITSTREAM_LOAD_FAIL
*
*****************************************************************************/
static u32 XFpga_WriteToPlPcap(XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
u32 BitstreamSize;
if ((InstancePtr->WriteInfo.Flags & XFPGA_SECURE_FLAGS) != 0U)
#ifdef XFPGA_SECURE_MODE
{
Status = XFpga_SecureLoadToPl(InstancePtr);
if (Status != XFPGA_SUCCESS) {
/* Clear the PL house */
Xil_Out32(CSU_PCAP_PROG, 0x0U);
usleep(PL_RESET_PERIOD_IN_US);
Xil_Out32(CSU_PCAP_PROG,
CSU_PCAP_PROG_PCFG_PROG_B_MASK);
}
}
#else
{
Status = XFPGA_PCAP_UPDATE_ERR(XFPGA_ERROR_SECURE_MODE_EN, 0U);
goto END;
}
#endif
else {
BitstreamSize = (u32)InstancePtr->WriteInfo.AddrPtr_Size;
Status = XFpga_WriteToPcap(BitstreamSize/WORD_LEN,
InstancePtr->WriteInfo.BitstreamAddr);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(
(u32)XFPGA_ERROR_BITSTREAM_LOAD_FAIL, (u32)0U);
}
}
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG,
"FPGA fail to write Bitstream into PL Error Code: 0x%08x\r\n",
Status);
goto END;
}
Status = XFpga_PLWaitForDone();
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(Status, (u32)0U);
Xfpga_Printf(XFPGA_DEBUG,
"FPGA fail to get the PCAP Done status Error Code:0x%08x\r\n",
Status);
}
END:
return Status;
}
/*****************************************************************************/
/** This Function sets FPGA into operating state after writing Configuration
* data.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
* - XFPGA_ERROR_PL_POWER_UP
* @note:
* PS_PL Isolation (Non PCAP) Enable/Disable should be done before
* and after writing the configuring data into the PL.The relevant
* register to enable/disable the PS_PL Isolation is part of the
* XPBR domain. So those registers can be accessed only through
* PMU_ROM code. PMU_ROM interface is having a separate call for
* PS_PL Isolation Enable and we are handlings this logic as part
* XFpga_PreConfigPcap() API. But to Disable the isolation PMU_ROM
* interface doesn't have any separate call. The PS_PL isolation
* disable logic is part of the Power_up sequence. So to disable
* the PS_PL Isolation we should call PL Power_up again in the
* Post_config sequence.
*
*****************************************************************************/
static u32 XFpga_PostConfigPcap(XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
u8 EndianType = 0U;
u32 RegVal;
if ((InstancePtr->WriteInfo.Flags & XFPGA_PARTIAL_EN) == 0U) {
/* PS-PL reset Low */
XFpga_PsPlGpioResetsLow();
usleep(XFPGA_PS_PL_RESET_TIME_US);
/* Power-Up PL */
Status = XFpga_PowerUpPl();
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG,
"XFPGA_ERROR_PL_POWER_UP\r\n");
Status = XFPGA_PCAP_UPDATE_ERR(
(u32)XFPGA_ERROR_PL_POWER_UP, (u32)0U);
}
/* PS-PL reset high*/
if (Status == XFPGA_SUCCESS) {
XFpga_PsPlGpioResetsHigh();
}
} else {
Status = XFPGA_SUCCESS;
}
/* Disable the PCAP clk */
RegVal = Xil_In32(PCAP_CLK_CTRL);
Xil_Out32(PCAP_CLK_CTRL, RegVal & ~(PCAP_CLK_EN_MASK));
if ((Status == XFPGA_SUCCESS) &&
((InstancePtr->WriteInfo.Flags & XFPGA_SECURE_FLAGS) != 0U)) {
XFpga_SetFirmwareState(XFPGA_FIRMWARE_STATE_SECURE);
} else if (Status == XFPGA_SUCCESS) {
XFpga_SetFirmwareState(XFPGA_FIRMWARE_STATE_NONSECURE);
} else {
XFpga_SetFirmwareState(XFPGA_FIRMWARE_STATE_UNKNOWN);
}
RegVal = XCsuDma_ReadReg(CsuDmaPtr->Config.BaseAddress,
((u32)(XCSUDMA_CTRL_OFFSET) +
((u32)XCSUDMA_SRC_CHANNEL *
(u32)(XCSUDMA_OFFSET_DIFF))));
RegVal |= ((u32)EndianType << (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) &
(u32)(XCSUDMA_CTRL_ENDIAN_MASK);
XCsuDma_WriteReg(CsuDmaPtr->Config.BaseAddress,
((u32)(XCSUDMA_CTRL_OFFSET) +
((u32)XCSUDMA_SRC_CHANNEL *
(u32)(XCSUDMA_OFFSET_DIFF))), RegVal);
return Status;
}
/*****************************************************************************/
/** Performs the necessary initialization of PCAP interface
*
* @param Flags Provides information about Crypto operation needs
* to be performed on the given Image (or) Data.
*
*@return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_PcapInit(u32 Flags)
{
u32 Status = XFPGA_FAILURE;
u32 RegVal;
/* Take PCAP out of Reset */
RegVal = Xil_In32(CSU_PCAP_RESET);
RegVal &= (~CSU_PCAP_RESET_RESET_MASK);
Xil_Out32(CSU_PCAP_RESET, RegVal);
/* Select PCAP mode and change PCAP to write mode */
RegVal = CSU_PCAP_CTRL_PCAP_PR_MASK;
Xil_Out32(CSU_PCAP_CTRL, RegVal);
Xil_Out32(CSU_PCAP_RDWR, 0x0U);
/* Reset PL */
if ((Flags & XFPGA_PARTIAL_EN) == 0U) {
Xil_Out32(CSU_PCAP_PROG, 0x0U);
usleep(PL_RESET_PERIOD_IN_US);
Xil_Out32(CSU_PCAP_PROG, CSU_PCAP_PROG_PCFG_PROG_B_MASK);
}
/*
* Wait for PL_init completion
*/
Status = Xil_WaitForEvent(CSU_PCAP_STATUS,
CSU_PCAP_STATUS_PL_INIT_MASK,
CSU_PCAP_STATUS_PL_INIT_MASK,
PL_DONE_POLL_COUNT);
return Status;
}
/*****************************************************************************/
/** Waits for PCAP transfer to complete
*
* @param None
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_PcapWaitForDone(void)
{
u32 Status = XFPGA_FAILURE;
Status = Xil_WaitForEvent(CSU_PCAP_STATUS,
PCAP_STATUS_PCAP_WR_IDLE_MASK,
PCAP_STATUS_PCAP_WR_IDLE_MASK,
PL_DONE_POLL_COUNT);
return Status;
}
/*****************************************************************************/
/** Writes data to PCAP interface
*
* @param Size Number of bytes that the DMA should write to the
* PCAP interface
* @param BitstreamAddr Linear Bitstream memory base address
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*****************************************************************************/
static u32 XFpga_WriteToPcap(u32 Size, UINTPTR BitstreamAddr)
{
u32 Status = XFPGA_FAILURE;
/*
* Setup the SSS, setup the PCAP to receive from DMA source
*/
Xil_Out32(CSU_CSU_SSS_CFG, XFPGA_CSU_SSS_SRC_SRC_DMA);
Xil_Out32(CSU_PCAP_RDWR, 0x0U);
/* Setup the source DMA channel */
XCsuDma_Transfer(CsuDmaPtr, XCSUDMA_SRC_CHANNEL, BitstreamAddr, Size, 0U);
/* wait for the SRC_DMA to complete and the pcap to be IDLE */
Status = XCsuDma_WaitForDoneTimeout(CsuDmaPtr, XCSUDMA_SRC_CHANNEL);
if (Status != XFPGA_SUCCESS) {
goto END;
}
/* Acknowledge the transfer has completed */
XCsuDma_IntrClear(CsuDmaPtr, XCSUDMA_SRC_CHANNEL, XCSUDMA_IXR_DONE_MASK);
Status = XFpga_PcapWaitForDone();
END:
return Status;
}
/*****************************************************************************/
/** This function waits for PCAP to come to idle state.
*
* @param None
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*****************************************************************************/
static u32 XFpga_PcapWaitForidle(void)
{
u32 Status = XFPGA_FAILURE;
Status = Xil_WaitForEvent(CSU_PCAP_STATUS,
PCAP_STATUS_PCAP_RD_IDLE_MASK,
PCAP_STATUS_PCAP_RD_IDLE_MASK,
PL_DONE_POLL_COUNT);
return Status;
}
/*****************************************************************************/
/** This function is used to Validate the user provided crypto flags
* with Image crypto flags.
* @param ImageInfo Pointer to XSecure_ImageInfo structure.
* @param Flags It provides the information about Crypto operation needs
* to be performed on the given Image (or) Data.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_ValidateCryptoFlags(const XSecure_ImageInfo *ImageInfo,
u32 Flags)
{
u32 Status = XFPGA_FAILURE;
u8 IsImageAuthenticated = 0U;
u8 IsImageUserKeyEncrypted = 0U;
u8 IsImageDevKeyEncrypted = 0U;
u8 IsFlagSetToAuthentication = 0U;
u8 IsFlagSetToUserKeyEncryption = 0U;
u8 IsFlagSetToDevKeyEncryption = 0U;
if ((ImageInfo->PartitionHdr->PartitionAttributes &
XSECURE_PH_ATTR_AUTH_ENABLE) != 0U) {
IsImageAuthenticated = 1U;
}
if ((ImageInfo->PartitionHdr->PartitionAttributes &
XSECURE_PH_ATTR_ENC_ENABLE) != 0U) {
if ((ImageInfo->KeySrc == XFPGA_KEY_SRC_EFUSE_RED) ||
(ImageInfo->KeySrc == XFPGA_KEY_SRC_BBRAM_RED) ||
(ImageInfo->KeySrc == XFPGA_KEY_SRC_EFUSE_BLK) ||
(ImageInfo->KeySrc == XFPGA_KEY_<KEY>) ||
(ImageInfo->KeySrc == XFPGA_KEY_SRC_EFUSE_GRY) ||
(ImageInfo->KeySrc == XFPGA_KEY_SRC_BH_GRY)) {
IsImageDevKeyEncrypted = 1U;
} else if (ImageInfo->KeySrc == XFPGA_KEY_SRC_KUP) {
IsImageUserKeyEncrypted = 1U;
} else {
goto END;
}
}
if (((Flags & XFPGA_AUTHENTICATION_DDR_EN) != 0U) ||
((Flags & XFPGA_AUTHENTICATION_OCM_EN) != 0U)) {
IsFlagSetToAuthentication = 1U;
}
if ((Flags & XFPGA_ENCRYPTION_USERKEY_EN) != 0U) {
IsFlagSetToUserKeyEncryption = 1U;
}
if ((Flags & XFPGA_ENCRYPTION_DEVKEY_EN) != 0U) {
IsFlagSetToDevKeyEncryption = 1U;
}
if ((IsImageAuthenticated == IsFlagSetToAuthentication) &&
(IsImageDevKeyEncrypted == IsFlagSetToDevKeyEncryption) &&
(IsImageUserKeyEncrypted == IsFlagSetToUserKeyEncryption)) {
Status = XFPGA_SUCCESS;
}
END:
return Status;
}
#ifdef XFPGA_SECURE_MODE
/*****************************************************************************/
/** Loads the secure Bitstream into the PL.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_SecureLoadToPl(XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
switch (InstancePtr->WriteInfo.Flags &
XFPGA_SECURE_FLAGS) {
case XFPGA_AUTHENTICATION_DDR_EN:
case XFPGA_AUTH_ENC_USERKEY_DDR:
case XFPGA_AUTH_ENC_DEVKEY_DDR:
case XFPGA_AUTHENTICATION_OCM_EN:
case XFPGA_AUTH_ENC_USERKEY_OCM:
case XFPGA_AUTH_ENC_DEVKEY_OCM:
Status = XFpga_SecureBitstreamLoad(InstancePtr);
break;
case XFPGA_ENCRYPTION_USERKEY_EN:
#ifdef XSECURE_TRUSTED_ENVIRONMENT
case XFPGA_ENCRYPTION_DEVKEY_EN:
#endif
Status = XFpga_WriteEncryptToPcap(InstancePtr);
break;
default:
Xfpga_Printf(XFPGA_DEBUG, "Invalid Option\r\n");
break;
}
return Status;
}
/*****************************************************************************/
/* This function authenticates the Bitstream by using on-chip/external memory.
* Sends the data to PCAP in blocks via AES engine if encryption
* exists or directly to PCAP by CSUDMA if an encryption is not enabled.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_SecureBitstreamLoad(XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
XFpgaPs_PlPartition *PlAesInfoPtr = &InstancePtr->PLInfo.PlAesInfo;
const XSecure_ImageInfo *ImageInfo = &InstancePtr->PLInfo.SecureImageInfo;
u32 PartationLen;
u32 PartationOffset;
u32 PartationAcOffset;
u32 AesKupKey[XSECURE_KEY_LEN];
/* Authenticate the PL Partation's */
if ( InstancePtr->PLInfo.SecureOcmState == 0U) {
PartationOffset = ImageInfo->PartitionHdr->DataWordOffset
* XSECURE_WORD_LEN;
PartationAcOffset =
ImageInfo->PartitionHdr->AuthCertificateOffset
* XSECURE_WORD_LEN;
PartationLen = PartationAcOffset - PartationOffset;
InstancePtr->PLInfo.TotalBitPartCount =
(u32)(PartationLen/PL_PARTATION_SIZE);
InstancePtr->PLInfo.RemaningBytes = PartationLen -
((u32)InstancePtr->PLInfo.TotalBitPartCount *
PL_PARTATION_SIZE);
InstancePtr->PLInfo.BitAddr = PartationOffset +
InstancePtr->WriteInfo.BitstreamAddr;
InstancePtr->PLInfo.AcPtr = PartationAcOffset +
InstancePtr->WriteInfo.BitstreamAddr;
if (((InstancePtr->WriteInfo.Flags &
XFPGA_ENCRYPTION_USERKEY_EN) != 0U)||
((InstancePtr->WriteInfo.Flags &
XFPGA_ENCRYPTION_DEVKEY_EN) != 0U)) {
PlAesInfoPtr->PlEncrypt.NextBlkLen = 0U;
PlAesInfoPtr->Hdr = 0U;
(void)memset(PlAesInfoPtr->SecureHdr, 0U,
XSECURE_SECURE_HDR_SIZE + XSECURE_SECURE_GCM_TAG_SIZE);
PlAesInfoPtr->PlEncrypt.SecureAes =
&InstancePtr->PLInfo.Secure_Aes;
Status = XFpga_AesInit(
PlAesInfoPtr->PlEncrypt.SecureAes,
AesKupKey, ImageInfo->Iv,
(char *)(InstancePtr->WriteInfo.AddrPtr_Size),
InstancePtr->WriteInfo.Flags);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(
XFPGA_ERROR_AES_INIT, Status);
goto END;
}
}
InstancePtr->PLInfo.SecureOcmState = 1U;
}
while ((u32)InstancePtr->PLInfo.TotalBitPartCount != 0U) {
Status = XFpga_AuthPlChunksDdrOcm(InstancePtr, PL_PARTATION_SIZE);
if (Status != XFPGA_SUCCESS) {
goto END;
}
}
if ((InstancePtr->PLInfo.RemaningBytes != 0U) &&
((u32)InstancePtr->PLInfo.TotalBitPartCount == 0U)){
Status = XFpga_AuthPlChunksDdrOcm(InstancePtr,
InstancePtr->PLInfo.RemaningBytes);
if (Status != XFPGA_SUCCESS) {
goto END;
} else {
InstancePtr->PLInfo.RemaningBytes = 0U;
}
}
END:
/* Clear local user key */
(void)memset(AesKupKey, 0U, XSECURE_KEY_LEN * XSECURE_WORD_LEN);
/* Zeroize the Secure data*/
(void)memset(&InstancePtr->PLInfo.SecureImageInfo, 0,
sizeof(InstancePtr->PLInfo.SecureImageInfo));
(void)memset(&InstancePtr->PLInfo.PlAesInfo, 0,
sizeof(InstancePtr->PLInfo.PlAesInfo));
return Status;
}
/*****************************************************************************/
/* This function authenticates the Bitstream by using on-chip/external memory.
* Sends the data to PCAP in blocks via AES engine if encryption
* exists or directly to PCAP by CSUDMA if an encryption is not enabled.
*
* @param InstancePtr Pointer to the XFpga structure.
* @param Size Number of bytes that the DMA should write to the
* PCAP interface.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_AuthPlChunksDdrOcm(XFpga *InstancePtr, u32 Size)
{
u32 Status = XFPGA_FAILURE;
XFpgaPs_PlPartition *PlAesInfoPtr = &InstancePtr->PLInfo.PlAesInfo;
XSecure_ImageInfo *ImageInfo = &InstancePtr->PLInfo.SecureImageInfo;
/* Copy authentication certificate to internal memory */
Status = XSecure_MemCopy((u8 *)AcBuf, (u8 *)InstancePtr->PLInfo.AcPtr,
XSECURE_AUTH_CERT_MIN_SIZE/(u32)XSECURE_WORD_LEN);
if (Status != XST_SUCCESS) {
goto END;
}
/*Verify Spk */
Status = XSecure_VerifySpk((u8 *)AcBuf, ImageInfo->EfuseRsaenable);
if (Status != (u32)XST_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(
XFPGA_ERROR_OCM_AUTH_VERIFY_SPK,
Status);
goto END;
}
/* Authenticate Partition */
if(InstancePtr->WriteInfo.Flags & XFPGA_AUTHENTICATION_DDR_EN) {
Status = XSecure_PartitionAuthentication(CsuDmaPtr,
(u8 *)InstancePtr->PLInfo.BitAddr, Size,
(u8 *)(UINTPTR)AcBuf);
if (Status != (u32)XST_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(
XFPGA_ERROR_DDR_AUTH_PARTITION,
Status);
goto END;
}
if (((InstancePtr->WriteInfo.Flags &
XFPGA_ENCRYPTION_USERKEY_EN)!= 0U)||
((InstancePtr->WriteInfo.Flags &
XFPGA_ENCRYPTION_DEVKEY_EN) != 0U)) {
Status = XFpga_DecrptPlChunks(PlAesInfoPtr,
InstancePtr->PLInfo.BitAddr,
Size);
} else {
Status = XFpga_WriteToPcap(Size/WORD_LEN,
InstancePtr->PLInfo.BitAddr);
}
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(
(u32)XFPGA_ERROR_DDR_AUTH_WRITE_PL, (u32)0U);
goto END;
}
} else {
Status = XFpga_AuthPlChunks(
(UINTPTR)InstancePtr->PLInfo.BitAddr,
Size, (UINTPTR)AcBuf);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(
XFPGA_ERROR_OCM_AUTH_PARTITION, Status);
goto END;
}
Status = XFpga_ReAuthPlChunksWriteToPl(PlAesInfoPtr,
(UINTPTR)InstancePtr->PLInfo.BitAddr,
Size, InstancePtr->WriteInfo.Flags);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(
(u32)XFPGA_ERROR_OCM_REAUTH_WRITE_PL, (u32)0U);
goto END;
}
}
if (InstancePtr->PLInfo.TotalBitPartCount != 0U) {
InstancePtr->PLInfo.AcPtr += AC_LEN;
InstancePtr->PLInfo.BitAddr += Size;
InstancePtr->PLInfo.TotalBitPartCount--;
}
END:
return Status;
}
/*****************************************************************************/
/*
* This function performs authentication the Blocks and store the
* This SHA3 hashes on secure memory.
*
* @param BitstreamAddr Linear memory address
* @param Size Number of bytes that the DMA should write to the
* PCAP interface.
* @param AcAddr authentication certificate base address.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
* @note None.
*
******************************************************************************/
static u32 XFpga_AuthPlChunks(UINTPTR BitstreamAddr, u32 Size, UINTPTR AcAddr)
{
u32 Status = XFPGA_FAILURE;
XSecure_Sha3 Secure_Sha3 = {0U};
u64 OcmAddr = OCM_PL_ADDR;
u32 ChunkSize;
u32 OcmChunkAddr = (u32)OCM_PL_ADDR + PL_CHUNK_SIZE_BYTES;
u32 RemainingBytes;
XSecure_RsaKey Key;
u8 *AcPtr = (u8 *)(UINTPTR)AcAddr;
u8 *Signature = (AcPtr + XSECURE_AUTH_CERT_PARTSIG_OFFSET);
u8 Sha3Hash[HASH_LEN] = {0U};
UINTPTR Temp_BitstreamAddr = BitstreamAddr;
Status = XSecure_Sha3Initialize(&Secure_Sha3, CsuDmaPtr);
if (Status != XST_SUCCESS) {
goto END;
}
(void)XSecure_Sha3Start(&Secure_Sha3);
RemainingBytes = Size;
while (RemainingBytes > 0) {
if (RemainingBytes > PL_CHUNK_SIZE_BYTES) {
ChunkSize = PL_CHUNK_SIZE_BYTES;
} else {
ChunkSize = RemainingBytes;
}
Status = XSecure_MemCopy((u8 *)(UINTPTR)OcmAddr,
(u8 *)(UINTPTR)Temp_BitstreamAddr,
ChunkSize/WORD_LEN);
if (Status != XFPGA_SUCCESS) {
goto END;
}
/* Generating SHA3 hash */
Status = XSecure_Sha3Update(&Secure_Sha3,
(u8 *)(UINTPTR)OcmAddr, ChunkSize);
if (Status != XST_SUCCESS) {
goto END;
}
XSecure_Sha3_ReadHash(&Secure_Sha3, Sha3Hash);
/* Copy SHA3 hash into the OCM */
(void)memcpy((u8 *)(UINTPTR)OcmChunkAddr, (u8 *)Sha3Hash, HASH_LEN);
OcmChunkAddr = OcmChunkAddr + HASH_LEN;
Temp_BitstreamAddr = Temp_BitstreamAddr + ChunkSize;
RemainingBytes = RemainingBytes - ChunkSize;
}
/* Copy AC into the OCM */
Status = XSecure_MemCopy((u8 *)(UINTPTR)OcmAddr, (u8 *)(UINTPTR)AcAddr,
AC_LEN/WORD_LEN);
if (Status != XFPGA_SUCCESS) {
goto END;
}
Status = XSecure_Sha3Update(&Secure_Sha3, (u8 *)(UINTPTR)OcmAddr,
AC_LEN - XSECURE_PARTITION_SIG_SIZE);
if (Status != XST_SUCCESS) {
goto END;
}
Status = XSecure_Sha3Finish(&Secure_Sha3, Sha3Hash);
if (Status != XST_SUCCESS) {
goto END;
}
/* Calculate Hash on the given signature and compare with Sha3Hash */
AcPtr += ((u32)XSECURE_RSA_AC_ALIGN + XSECURE_PPK_SIZE);
Key.Modulus = AcPtr;
AcPtr += XSECURE_SPK_MOD_SIZE;
Key.Exponentiation = AcPtr;
AcPtr += XSECURE_SPK_MOD_EXT_SIZE;
Key.Exponent = AcPtr;
Status = XSecure_DataAuth(Signature, &Key, Sha3Hash);
END:
/* Set SHA under reset */
XSecure_SetReset(Secure_Sha3.BaseAddress,
XSECURE_CSU_SHA3_RESET_OFFSET);
return Status;
}
/*****************************************************************************/
/* This function Re-authenticates the Bitstream by using on-chip memory.
* Sends the data to PCAP in blocks via AES engine if encryption
* exists or directly to PCAP by CSUDMA if an encryption is not enabled.
*
* @param PlAesInfo is a pointer to XFpgaPs_PlPartition
* @param BitstreamAddr Linear memory secure image base address
* @param Flags It provides the information about Crypto operation needs
* to be performed on the given Image (or) Data.
* @param Size Number of bytes that the DMA should write to the
* PCAP interface.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_ReAuthPlChunksWriteToPl(XFpgaPs_PlPartition *PlAesInfo,
UINTPTR BitstreamAddr,
u32 Size, u32 Flags)
{
u32 Status = XFPGA_FAILURE;
XSecure_Sha3 Secure_Sha3;
u64 OcmAddr = OCM_PL_ADDR;
u32 ChunkSize;
u32 OcmChunkAddr = (u32)OCM_PL_ADDR + PL_CHUNK_SIZE_BYTES;
u32 RemainingBytes;
u8 Sha3Hash[HASH_LEN] = {0U};
UINTPTR Temp_BitstreamAddr = BitstreamAddr;
Status = XSecure_Sha3Initialize(&Secure_Sha3, CsuDmaPtr);
if (Status != XST_SUCCESS) {
goto END;
}
(void)XSecure_Sha3Start(&Secure_Sha3);
RemainingBytes = Size;
while (RemainingBytes > 0) {
if (RemainingBytes > PL_CHUNK_SIZE_BYTES) {
ChunkSize = PL_CHUNK_SIZE_BYTES;
} else {
ChunkSize = RemainingBytes;
}
Status = XSecure_MemCopy((u8 *)(UINTPTR)OcmAddr,
(u8 *)(UINTPTR)Temp_BitstreamAddr,
ChunkSize/WORD_LEN);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_FAILURE;
goto END;
}
/* Generating SHA3 hash */
Status = XSecure_Sha3Update(&Secure_Sha3,
(u8 *)(UINTPTR)OcmAddr, ChunkSize);
if (Status != XST_SUCCESS) {
goto END;
}
XSecure_Sha3_ReadHash(&Secure_Sha3, Sha3Hash);
/* Compare SHA3 hash with OCM Stored hash*/
if (memcmp((u8 *)((UINTPTR)OcmChunkAddr),
(u8 *)Sha3Hash, HASH_LEN)!= 0) {
Status = XFPGA_FAILURE;
} else {
OcmChunkAddr = OcmChunkAddr + HASH_LEN;
}
if (Status == XFPGA_FAILURE) {
goto END;
}
if (((Flags & XFPGA_ENCRYPTION_USERKEY_EN) != 0U)
|| ((Flags & XFPGA_ENCRYPTION_DEVKEY_EN) != 0U)) {
Status = XFpga_DecrptPlChunks(PlAesInfo, OcmAddr,
ChunkSize);
} else {
Status = XFpga_WriteToPcap(ChunkSize/WORD_LEN, OcmAddr);
}
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_FAILURE;
goto END;
}
Temp_BitstreamAddr = Temp_BitstreamAddr + ChunkSize;
RemainingBytes = RemainingBytes - ChunkSize;
}
Status = XSecure_Sha3Finish(&Secure_Sha3, Sha3Hash);
END:
/* Set SHA under reset */
XSecure_SetReset(Secure_Sha3.BaseAddress,
XSECURE_CSU_SHA3_RESET_OFFSET);
return Status;
}
/*****************************************************************************/
/* This is the function to write Encrypted data into PCAP interface
*
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_WriteEncryptToPcap(XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
XSecure_ImageInfo *ImageHdrInfo = &InstancePtr->PLInfo.SecureImageInfo;
XSecure_Aes Secure_Aes = {0};
u8 *EncSrc;
u32 AesKupKey[XSECURE_KEY_LEN];
Status = XFpga_AesInit(&Secure_Aes, AesKupKey, ImageHdrInfo->Iv,
(char *)InstancePtr->WriteInfo.AddrPtr_Size,
InstancePtr->WriteInfo.Flags);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(
XFPGA_ERROR_AES_INIT, Status);
goto END;
}
EncSrc = (u8 *)(UINTPTR)(InstancePtr->WriteInfo.BitstreamAddr +
((ImageHdrInfo->PartitionHdr->DataWordOffset) *
XSECURE_WORD_LEN));
Status = (u32)XSecure_AesDecrypt(&Secure_Aes,
(u8 *) XFPGA_DESTINATION_PCAP_ADDR, EncSrc,
ImageHdrInfo->PartitionHdr->UnEncryptedDataWordLength *
XSECURE_WORD_LEN);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(
XFPGA_ERROR_AES_DECRYPT_PL, Status);
goto END;
}
Status = XFpga_PcapWaitForDone();
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_PCAP_UPDATE_ERR(Status, (u32)0U);
}
END:
/* Clear local user key */
(void)memset(AesKupKey, 0, XSECURE_KEY_LEN * XSECURE_WORD_LEN);
return Status;
}
/******************************************************************************/
/*
* This API decrypts the chunks of data
*
* @param PartitionParams is a pointer to XFpgaPs_PlPartition
* @param ChunkAdrs holds the address of chunk address
* @param ChunkSize holds the size of chunk
*
* @return
* Error code on failure
* XFPGA_SUCCESS on success
*
* @note None.
*
******************************************************************************/
static u32 XFpga_DecrptPlChunks(XFpgaPs_PlPartition *PartitionParams,
u64 ChunkAdrs, u32 ChunkSize)
{
u32 Status = XFPGA_FAILURE;
UINTPTR SrcAddr = (u64)ChunkAdrs;
u32 Size = ChunkSize;
u64 NextBlkAddr = 0U;
XSecure_SssInitialize(&PartitionParams->SssInstance);
/* If this is the first block to be decrypted it is the secure header */
if (PartitionParams->PlEncrypt.NextBlkLen == 0x00U) {
Status = XSecure_AesDecryptInit(PartitionParams->PlEncrypt.SecureAes,
(u8 *)XSECURE_DESTINATION_PCAP_ADDR, XSECURE_SECURE_HDR_SIZE,
(u8 *)(SrcAddr + XSECURE_SECURE_HDR_SIZE));
if (Status != XST_SUCCESS) {
goto END;
}
/*
* Configure AES engine to push decrypted Key and IV in the
* block to the CSU KEY and IV registers.
*/
XSecure_WriteReg(
PartitionParams->PlEncrypt.SecureAes->BaseAddress,
XSECURE_CSU_AES_KUP_WR_OFFSET,
XSECURE_CSU_AES_IV_WR | XSECURE_CSU_AES_KUP_WR);
/* Decrypting the Secure header */
Status = (u32)XSecure_AesDecryptUpdate(
PartitionParams->PlEncrypt.SecureAes,
(u8 *)(SrcAddr), XSECURE_SECURE_HDR_SIZE);
if (Status != XFPGA_SUCCESS) {
Status = XFPGA_FAILURE;
goto END;
}
PartitionParams->PlEncrypt.SecureAes->KeySel =
XSECURE_CSU_AES_KEY_SRC_KUP;
Status = XSecure_AesKeySelNLoad(PartitionParams->PlEncrypt.SecureAes);
if (Status != XST_SUCCESS) {
goto END;
}
/* Point IV to the CSU IV register. */
PartitionParams->PlEncrypt.SecureAes->Iv =
(u32 *)(PartitionParams->PlEncrypt.SecureAes->BaseAddress +
(UINTPTR)XSECURE_CSU_AES_IV_0_OFFSET);
/*
* Remaining size and source address
* of the data to be processed
*/
Size = ChunkSize -
XSECURE_SECURE_HDR_SIZE - XSECURE_SECURE_GCM_TAG_SIZE;
SrcAddr = ChunkAdrs +
XSECURE_SECURE_HDR_SIZE+XSECURE_SECURE_GCM_TAG_SIZE;
/*
* Decrypt next block after Secure header and
* update the required fields
*/
Status = XFpga_DecrptSetUpNextBlk(PartitionParams);
if (Status != XFPGA_SUCCESS) {
goto END;
}
Status = XFpga_DecrptPl(PartitionParams,
(UINTPTR)SrcAddr, Size);
if (Status != XFPGA_SUCCESS) {
goto END;
}
/*
* If status is true or false return the status
* As remaining data also processed in above API
*/
goto END;
}
/*
* If previous chunk has portion of left header,
* which needs to be processed along with this chunk
*/
else if (PartitionParams->Hdr != 0x00U) {
/* Configure AES engine */
Status = XSecure_SssAes(&PartitionParams->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_PCAP);
if (Status != XST_SUCCESS) {
goto END;
}
(void)memcpy((u8 *)(PartitionParams->SecureHdr
+ PartitionParams->Hdr), (u8 *)(UINTPTR)SrcAddr,
XFPGA_AES_TAG_SIZE - PartitionParams->Hdr);
Status = XFpga_DecrypSecureHdr(
PartitionParams->PlEncrypt.SecureAes,
(u64)(UINTPTR)PartitionParams->SecureHdr);
if (Status != XFPGA_SUCCESS) {
goto END;
}
Size = Size - (XFPGA_AES_TAG_SIZE - PartitionParams->Hdr);
if (Size != 0x00U) {
NextBlkAddr = SrcAddr +
((u64)XFPGA_AES_TAG_SIZE - (u64)PartitionParams->Hdr);
}
PartitionParams->Hdr = 0U;
(void)memset(PartitionParams->SecureHdr, 0U, XFPGA_AES_TAG_SIZE);
/*
* This means we are done with Secure header and Block 0
* And now we can change the AES key source to KUP.
*/
PartitionParams->PlEncrypt.SecureAes->KeySel =
XSECURE_CSU_AES_KEY_SRC_KUP;
Status = XSecure_AesKeySelNLoad(PartitionParams->PlEncrypt.SecureAes);
if (Status != XST_SUCCESS) {
goto END;
}
Status = XFpga_DecrptSetUpNextBlk(PartitionParams);
if (Status != XFPGA_SUCCESS) {
goto END;
}
if ((NextBlkAddr != 0x00U) &&
(PartitionParams->PlEncrypt.SecureAes->SizeofData != 0U)) {
Status = XFpga_DecrptPl(PartitionParams,
(UINTPTR)NextBlkAddr, Size);
if (Status != XFPGA_SUCCESS) {
goto END;
}
}
} else {
Status = XFpga_DecrptPl(PartitionParams, SrcAddr, Size);
}
END:
return Status;
}
/******************************************************************************/
/*
* This function calculates the next block size and updates the required
* parameters.
*
* @param PartitionParams is a pointer to XFpgaPs_PlPartition
*
* @return
* Error code on failure
* XFPGA_SUCCESS on success
*
* @note None
*
******************************************************************************/
static u32 XFpga_DecrptSetUpNextBlk(XFpgaPs_PlPartition *PartitionParams)
{
u32 Status = XFPGA_FAILURE;
/* Length of next block */
PartitionParams->PlEncrypt.NextBlkLen =
Xil_Htonl(XSecure_ReadReg(
PartitionParams->PlEncrypt.SecureAes->BaseAddress,
XSECURE_CSU_AES_IV_3_OFFSET)) * WORD_LEN;
PartitionParams->PlEncrypt.SecureAes->Iv =
(u32 *)(PartitionParams->PlEncrypt.SecureAes->BaseAddress +
(UINTPTR)XSECURE_CSU_AES_IV_0_OFFSET);
/* Configure the SSS for AES. */
Status = XSecure_SssAes(&PartitionParams->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_PCAP);
if (Status != XST_SUCCESS) {
goto END;
}
/* Start the message. */
XSecure_WriteReg(PartitionParams->PlEncrypt.SecureAes->BaseAddress,
XSECURE_CSU_AES_START_MSG_OFFSET,
XSECURE_CSU_AES_START_MSG);
/* Transfer IV of the next block */
XFpga_DmaPlCopy(PartitionParams->PlEncrypt.SecureAes->CsuDmaPtr,
(UINTPTR)PartitionParams->PlEncrypt.SecureAes->Iv,
XSECURE_SECURE_GCM_TAG_SIZE/WORD_LEN, 0U);
PartitionParams->PlEncrypt.SecureAes->SizeofData =
PartitionParams->PlEncrypt.NextBlkLen;
XSecure_WriteReg(PartitionParams->PlEncrypt.SecureAes->BaseAddress,
XSECURE_CSU_AES_KUP_WR_OFFSET, 0x0U);
END:
return Status;
}
/******************************************************************************/
/*
* This function is used to copy data to AES/PL.
*
* @param InstancePtr is an instance of CSUDMA
* @param Src holds the source Address
* @param Size of the data
* @param EnLast - 0 or 1
*
* @return None
*
* @note None
*
******************************************************************************/
static void XFpga_DmaPlCopy(XCsuDma *InstancePtr, UINTPTR Src, u32 Size,
u8 EnLast)
{
/* Data transfer */
XCsuDma_Transfer(InstancePtr, XCSUDMA_SRC_CHANNEL, (UINTPTR)Src,
Size, EnLast);
/* Polling for transfer to be done */
XCsuDma_WaitForDone(InstancePtr, XCSUDMA_SRC_CHANNEL);
/* To acknowledge the transfer has completed */
XCsuDma_IntrClear(InstancePtr, XCSUDMA_SRC_CHANNEL,
XCSUDMA_IXR_DONE_MASK);
}
/******************************************************************************/
/*
* This function sends data to AES engine which needs to be decrypted till the
* end of the encryption block.
*
* @param PartitionParams is a pointer to XFpgaPs_PlPartition
* @param ChunkAdrs is a pointer to the data location
* @param ChunkSize is the remaining chunk size
*
* @return
* Error code on failure
* XFPGA_SUCCESS on success
*
* @note None
*
*****************************************************************************/
static u32 XFpga_DecrptPl(XFpgaPs_PlPartition *PartitionParams,
u64 ChunkAdrs, u32 ChunkSize)
{
u32 Size = ChunkSize;
u32 Status = XFPGA_FAILURE;
u64 SrcAddr = (u64)ChunkAdrs;
XCsuDma_Configure ConfigurValues = {0U};
UINTPTR NextBlkAddr = 0U;
do {
/* Enable byte swapping */
XCsuDma_GetConfig(
PartitionParams->PlEncrypt.SecureAes->CsuDmaPtr,
XCSUDMA_SRC_CHANNEL, &ConfigurValues);
ConfigurValues.EndianType = 1U;
XCsuDma_SetConfig(
PartitionParams->PlEncrypt.SecureAes->CsuDmaPtr,
XCSUDMA_SRC_CHANNEL, &ConfigurValues);
/* Configure SSS for AES engine */
Status = XSecure_SssAes(&PartitionParams->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_PCAP);
if (Status != XST_SUCCESS) {
goto END;
}
if (PartitionParams->PlEncrypt.SecureAes->SizeofData != 0U) {
/* Send whole chunk of data to AES */
if ((Size <=
(PartitionParams->PlEncrypt.SecureAes->
SizeofData))) {
XFpga_DmaPlCopy(
PartitionParams->PlEncrypt.SecureAes->CsuDmaPtr,
(UINTPTR)SrcAddr, Size/WORD_LEN, 0U);
PartitionParams->
PlEncrypt.SecureAes->SizeofData =
PartitionParams->PlEncrypt.SecureAes->SizeofData
- Size;
Size = 0U;
} else {
/*
* If data to be processed is not zero
* and chunk of data is greater
*/
/* First transfer whole data other than secure header */
XFpga_DmaPlCopy(
PartitionParams->PlEncrypt.SecureAes->CsuDmaPtr,
(UINTPTR)SrcAddr,
PartitionParams->
PlEncrypt.SecureAes->SizeofData/WORD_LEN, 0U);
SrcAddr = SrcAddr + (u64)PartitionParams->
PlEncrypt.SecureAes->SizeofData;
Size = Size - PartitionParams->
PlEncrypt.SecureAes->SizeofData;
PartitionParams->
PlEncrypt.SecureAes->SizeofData = 0U;
/*
* when data to be processed is greater than
* remaining data of the encrypted block
* and part of GCM tag and secure header of
* next block also exists with chunk,
* copy that portion for proceessing along
* with next chunk of data
*/
if (Size < (XSECURE_SECURE_HDR_SIZE +
XSECURE_SECURE_GCM_TAG_SIZE)) {
if(SrcAddr == (UINTPTR)NULL) {
goto END;
}
(void)memcpy(PartitionParams->SecureHdr,
(u8 *)(UINTPTR)SrcAddr, Size);
PartitionParams->Hdr = (u8)Size;
Size = 0U;
}
}
}
/* Wait PCAP done */
Status = XFpga_PcapWaitForDone();
if (Status != XFPGA_SUCCESS) {
goto END;
}
/* Configure AES engine */
Status = XSecure_SssAes(&PartitionParams->SssInstance,
XSECURE_SSS_DMA0, XSECURE_SSS_PCAP);
if (Status != XST_SUCCESS) {
goto END;
}
XCsuDma_GetConfig(
PartitionParams->PlEncrypt.SecureAes->CsuDmaPtr,
XCSUDMA_SRC_CHANNEL, &ConfigurValues);
ConfigurValues.EndianType = 0U;
XCsuDma_SetConfig(
PartitionParams->PlEncrypt.SecureAes->CsuDmaPtr,
XCSUDMA_SRC_CHANNEL, &ConfigurValues);
/* Decrypting secure header and GCM tag address */
if ((PartitionParams->PlEncrypt.SecureAes->SizeofData == 0U) &&
(Size != 0U)) {
Status = XFpga_DecrypSecureHdr(
PartitionParams->PlEncrypt.SecureAes, SrcAddr);
if (Status != XFPGA_SUCCESS) {
goto END;
}
Size = Size - (XSECURE_SECURE_HDR_SIZE +
XSECURE_SECURE_GCM_TAG_SIZE);
if (Size != 0x00U) {
NextBlkAddr = SrcAddr +
XSECURE_SECURE_HDR_SIZE +
XSECURE_SECURE_GCM_TAG_SIZE;
}
/*
* This means we are done with Secure header and Block 0
* And now we can change the AES key source to KUP.
*/
PartitionParams->PlEncrypt.SecureAes->KeySel =
XSECURE_CSU_AES_KEY_SRC_KUP;
Status = XSecure_AesKeySelNLoad(
PartitionParams->PlEncrypt.SecureAes);
if (Status != XST_SUCCESS) {
goto END;
}
Status = XFpga_DecrptSetUpNextBlk(PartitionParams);
if (Status != XFPGA_SUCCESS) {
goto END;
}
if ((NextBlkAddr != 0x00U) &&
(PartitionParams->PlEncrypt.SecureAes->SizeofData != 0U)) {
SrcAddr = NextBlkAddr;
} else {
break;
}
}
} while (Size != 0x00U);
END:
return Status;
}
/******************************************************************************/
/*
* This function decrypts the secure header when key rolling is enabled
*
* @param InstancePtr is an instance AES engine.
* @param SrcAddr holds the address of secure header
*
* @return
* Error code on failure
* XFPGA_SUCCESS on success
*
* @note None
*
******************************************************************************/
static u32 XFpga_DecrypSecureHdr(XSecure_Aes *InstancePtr, u64 SrcAddr)
{
XCsuDma_Configure ConfigurValues = {0U};
u32 GcmStatus;
u32 Status = XFPGA_FAILURE;
XCsuDma_GetConfig(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL,
&ConfigurValues);
ConfigurValues.EndianType = 1U;
XCsuDma_SetConfig(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL,
&ConfigurValues);
/*
* Push secure header before that configure to
* push IV and key to csu engine
*/
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_AES_KUP_WR_OFFSET,
XSECURE_CSU_AES_IV_WR | XSECURE_CSU_AES_KUP_WR);
XCsuDma_IntrClear(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL,
XCSUDMA_IXR_DONE_MASK);
/* PUSH Secure hdr */
XFpga_DmaPlCopy(InstancePtr->CsuDmaPtr, SrcAddr,
XSECURE_SECURE_HDR_SIZE/WORD_LEN, 1U);
/* Restore Key write register to 0. */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_AES_KUP_WR_OFFSET, 0x0U);
/* Push the GCM tag. */
XFpga_DmaPlCopy(InstancePtr->CsuDmaPtr,
SrcAddr + XSECURE_SECURE_HDR_SIZE,
XSECURE_SECURE_GCM_TAG_SIZE/WORD_LEN, 1U);
/* Disable CSU DMA Src channel for byte swapping. */
XCsuDma_GetConfig(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL,
&ConfigurValues);
ConfigurValues.EndianType = 0U;
XCsuDma_SetConfig(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL,
&ConfigurValues);
Status = XSecure_AesWaitForDone(InstancePtr);
if (Status != XST_SUCCESS) {
goto END;
}
/* Get the AES status to know if GCM check passed. */
GcmStatus = XSecure_ReadReg(InstancePtr->BaseAddress,
XSECURE_CSU_AES_STS_OFFSET) &
XSECURE_CSU_AES_STS_GCM_TAG_OK;
if (GcmStatus == 0U) {
Xfpga_Printf(XFPGA_DEBUG, "GCM TAG NOT Matched\r\n");
XSecure_SetReset(InstancePtr->BaseAddress,
XSECURE_CSU_AES_RESET_OFFSET);
Status = XFPGA_FAILURE;
} else {
Status = XFPGA_SUCCESS;
}
END:
return Status;
}
/*****************************************************************************/
/* This function initializes the instance pointer.
*
* @param InstancePtr Pointer to the XSecure_Aes instance.
* @param CsuDmaPtr Pointer to the XCsuDma instance.
* @param IvPtr Pointer to the Initialization Vector for decryption
* @param KeyPtr Pointer to Aes decryption key in case KUP key is used.
* Passes `Null` if device key is to be used.
* @param Flags It provides the information about Crypto operation needs
* to be performed on the given Image (or) Data.
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_AesInit(XSecure_Aes *InstancePtr,
u32 *AesKupKey, u32* IvPtr,
char *KeyPtr, u32 Flags)
{
u32 Status = XFPGA_FAILURE;
if ((Flags & XFPGA_ENCRYPTION_USERKEY_EN) != 0U) {
Status = Xil_ConvertStringToHex(KeyPtr,
AesKupKey, KEY_LEN);
/* Clear the key info from DDR or Physical memory */
(void)memset(KeyPtr, 0U, KEY_LEN);
if (Status != XFPGA_SUCCESS) {
goto END;
}
/* Xilsecure expects Key in big endian form */
for (u8 Index = 0U; Index < XSECURE_KEY_LEN; Index++) {
AesKupKey[Index] = Xil_Htonl(AesKupKey[Index]);
}
/* Initialize the Aes driver so that it's ready to use */
Status = XSecure_AesInitialize(InstancePtr, CsuDmaPtr,
XSECURE_CSU_AES_KEY_SRC_KUP,
IvPtr, AesKupKey);
if (Status != XST_SUCCESS) {
goto END;
}
} else {
/* Initialize the Aes driver so that it's ready to use */
Status = XSecure_AesInitialize(InstancePtr, CsuDmaPtr,
XSECURE_CSU_AES_KEY_SRC_DEV,
IvPtr, NULL);
if (Status != XST_SUCCESS) {
goto END;
}
}
END:
return Status;
}
#endif
/****************************************************************************/
/* This function waits for PL Done bit to be set or till timeout and resets
* PCAP after this.
*
* @param None
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_PLWaitForDone(void)
{
u32 Status = XFPGA_FAILURE;
u32 RegVal = 0U;
Status = Xil_WaitForEvent(CSU_PCAP_STATUS,
CSU_PCAP_STATUS_PL_DONE_MASK,
CSU_PCAP_STATUS_PL_DONE_MASK,
PL_DONE_POLL_COUNT);
if (Status != XST_SUCCESS) {
Status = XFPGA_ERROR_PCAP_PL_DONE;
goto END;
}
/* Reset PCAP after data transfer */
RegVal = Xil_In32(CSU_PCAP_RESET);
RegVal = RegVal | CSU_PCAP_RESET_RESET_MASK;
Xil_Out32(CSU_PCAP_RESET, RegVal);
Status = Xil_WaitForEvent(CSU_PCAP_RESET,
CSU_PCAP_RESET_RESET_MASK,
CSU_PCAP_RESET_RESET_MASK,
PL_DONE_POLL_COUNT);
END:
return Status;
}
/*****************************************************************************/
/*
* This function is used to power-up the PL
*
* @param None
*
* @return Returns Status
* - XFPGA_SUCCESS on success
* - Error code on failure
*
*****************************************************************************/
static u32 XFpga_PowerUpPl(void)
{
u32 Status = XFPGA_FAILURE;
#ifdef __MICROBLAZE__
Status = XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPPLD]();
#else
Xil_Out32(PMU_GLOBAL_PWRUP_EN, PMU_GLOBAL_PWR_PL_MASK);
Xil_Out32(PMU_GLOBAL_PWRUP_TRIG, PMU_GLOBAL_PWR_PL_MASK);
Status = Xil_WaitForEvent(PMU_GLOBAL_PWRUP_STATUS,
PMU_GLOBAL_PWR_PL_MASK, 0U,
PL_DONE_POLL_COUNT);
if (Status != XST_SUCCESS) {
Status = XFPGA_ERROR_PL_POWER_UP;
} else {
Status = XFPGA_SUCCESS;
}
#endif
return Status;
}
/*************************************************************************/
/*
* This function is used to request isolation restore, through PMU
*
* @param None.
*
* @return
* - XFPGA_SUCCESS if successful
* - XFPGA_ERROR_PL_ISOLATION if unsuccessful
*
* @note None.
*
**************************************************************************/
static u32 XFpga_IsolationRestore(void)
{
u32 Status = XFPGA_FAILURE;
#ifdef __MICROBLAZE__
Status = XpbrServHndlrTbl[XPBR_SERV_EXT_PLNONPCAPISO]();
#else
/* Isolation request enable */
Xil_Out32(PMU_GLOBAL_ISO_INT_EN, PMU_GLOBAL_ISO_NONPCAP_MASK);
/* Trigger Isolation request */
Xil_Out32(PMU_GLOBAL_ISO_TRIG, PMU_GLOBAL_ISO_NONPCAP_MASK);
/* Poll for Isolation complete */
Status = Xil_WaitForEvent(PMU_GLOBAL_ISO_STATUS,
PMU_GLOBAL_ISO_NONPCAP_MASK, 0U,
PL_DONE_POLL_COUNT);
if (Status != XST_SUCCESS) {
Status = XFPGA_ERROR_PL_ISOLATION;
} else {
Status = XFPGA_SUCCESS;
}
#endif
return Status;
}
/**************************************************************************/
/*
* This function is used to start reset of the PL from PS EMIO pins
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XFpga_PsPlGpioResetsLow(void)
{
u32 RegVal = 0U;
/* Set EMIO Direction */
RegVal = Xil_In32(GPIO_DIRM_5_EMIO) | GPIO_PS_PL_DIRM_MASK;
Xil_Out32(GPIO_DIRM_5_EMIO, RegVal);
/*De-assert the EMIO with the required Mask */
Xil_Out32(GPIO_MASK_DATA_5_MSW, GPIO_LOW_DATA_MSW_VAL);
}
/***************************************************************************/
/*
* This function is used to release reset of the PL from PS EMIO pins
*
* @param None.
*
* @return None.
*
* @note None.
*
***************************************************************************/
void XFpga_PsPlGpioResetsHigh(void)
{
u32 RegVal = 0U;
/* Set EMIO Direction */
RegVal = Xil_In32(GPIO_DIRM_5_EMIO) | GPIO_PS_PL_DIRM_MASK;
Xil_Out32(GPIO_DIRM_5_EMIO, RegVal);
/*Assert the EMIO with the required Mask */
Xil_Out32(GPIO_MASK_DATA_5_MSW, GPIO_HIGH_DATA_MSW_VAL);
}
/*****************************************************************************/
/** Provides the STATUS of PCAP interface
*
* @param None
*
* @return Status of the PCAP interface.
*
*****************************************************************************/
static u32 XFpga_PcapStatus(void)
{
return Xil_In32(CSU_PCAP_STATUS);
}
/*****************************************************************************/
/**
* @ingroup xfpga_apis
* Returns the value of the specified configuration register.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return
* - XFPGA_SUCCESS if successful
* - XFPGA_FAILURE if unsuccessful
*
*
****************************************************************************/
static u32 XFpga_GetConfigRegPcap(const XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
u32 RegVal;
UINTPTR Address = InstancePtr->ReadInfo.ReadbackAddr;
u32 CmdIndex;
u32 CmdBuf[XFPGA_REG_CONFIG_CMD_LEN];
Status = XFpga_GetFirmwareState();
if ((Status == XFPGA_FIRMWARE_STATE_SECURE) &&
(XFPGA_SECURE_READBACK_MODE_EN == 0U)) {
Xfpga_Printf(XFPGA_DEBUG, "Operation not permitted\n\r");
Status = XFPGA_FAILURE;
goto END;
}
/* Enable the PCAP clk */
RegVal = Xil_In32(PCAP_CLK_CTRL);
Xil_Out32(PCAP_CLK_CTRL, RegVal | PCAP_CLK_EN_MASK);
/*
* Register Readback in non secure mode
* Create the data to be written to read back the
* Configuration Registers from PL Region.
*/
CmdIndex = 0U;
CmdBuf[CmdIndex] = 0xFFFFFFFFU; /* Dummy Word */
CmdIndex++;
CmdBuf[CmdIndex] = 0x000000BBU; /* Bus Width Sync Word */
CmdIndex++;
CmdBuf[CmdIndex] = 0x11220044U; /* Bus Width Detect */
CmdIndex++;
CmdBuf[CmdIndex] = 0xFFFFFFFFU; /* Dummy Word */
CmdIndex++;
CmdBuf[CmdIndex] = 0xAA995566U; /* Sync Word */
CmdIndex++;
CmdBuf[CmdIndex] = 0x20000000U; /* Type 1 NOOP Word 0 */
CmdIndex++;
CmdBuf[CmdIndex] =
Xfpga_RegAddr((u8)(InstancePtr->ReadInfo.ConfigReg_NumFrames),
OPCODE_READ, 0x1U);
CmdIndex++;
CmdBuf[CmdIndex] = 0x20000000U; /* Type 1 NOOP Word 0 */
CmdIndex++;
CmdBuf[CmdIndex] = 0x20000000U; /* Type 1 NOOP Word 0 */
CmdIndex++;
/* Take PCAP out of Reset */
RegVal = Xil_In32(CSU_PCAP_RESET);
RegVal &= (~CSU_PCAP_RESET_RESET_MASK);
Xil_Out32(CSU_PCAP_RESET, RegVal);
/* Flush the DMA buffer */
Xil_DCacheFlushRange(Address, 256U);
/* Set up the Destination DMA Channel*/
XCsuDma_Transfer(CsuDmaPtr, XCSUDMA_DST_CHANNEL, Address, 1U, 0U);
/* Setup the source DMA channel */
Status = XFpga_PcapWaitForDone();
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG, "Write to PCAP Failed\n\r");
Status = XFPGA_FAILURE;
goto END;
}
Status = XFpga_WriteToPcap(CmdIndex, (UINTPTR)CmdBuf);
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG, "Write to PCAP Failed\n\r");
Status = XFPGA_FAILURE;
goto END;
}
/*
* Setup the SSS, setup the DMA to receive from PCAP source
*/
Xil_Out32(CSU_CSU_SSS_CFG, XFPGA_CSU_SSS_SRC_DST_DMA);
Xil_Out32(CSU_PCAP_RDWR, 0x1U);
/* wait for the DST_DMA to complete and the pcap to be IDLE */
Status = XCsuDma_WaitForDoneTimeout(CsuDmaPtr, XCSUDMA_DST_CHANNEL);
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG, "Read from PCAP Failed\n\r");
Status = XFPGA_FAILURE;
goto END;
}
/* Acknowledge the transfer has completed */
XCsuDma_IntrClear(CsuDmaPtr, XCSUDMA_DST_CHANNEL, XCSUDMA_IXR_DONE_MASK);
CmdIndex = 0U;
CmdBuf[CmdIndex] = 0x30008001U; /* Type 1 Write 1 word to CMD */
CmdIndex++;
CmdBuf[CmdIndex] = 0x0000000DU; /* DESYNC command */
CmdIndex++;
CmdBuf[CmdIndex] = 0x20000000U; /* NOOP Word*/
CmdIndex++;
CmdBuf[CmdIndex] = 0x20000000U; /* NOOP Word */
CmdIndex++;
Status = XFpga_WriteToPcap(CmdIndex, (UINTPTR)CmdBuf);
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG, "Write to PCAP Failed\n\r");
Status = XFPGA_FAILURE;
goto END;
}
END:
/* Disable the PCAP clk */
RegVal = Xil_In32(PCAP_CLK_CTRL);
Xil_Out32(PCAP_CLK_CTRL, RegVal & ~(PCAP_CLK_EN_MASK));
return Status;
}
/*****************************************************************************/
/**
*
* This function performs the readback of fpga configuration data.
*
* @param InstancePtr Pointer to the XFpga structure.
*
* @return
* - XFPGA_SUCCESS if successful
* - XFPGA_FAILURE if unsuccessful
*
* @note None.
****************************************************************************/
static u32 XFpga_GetPLConfigDataPcap(const XFpga *InstancePtr)
{
u32 Status = XFPGA_FAILURE;
UINTPTR Address = InstancePtr->ReadInfo.ReadbackAddr;
u32 NumFrames = InstancePtr->ReadInfo.ConfigReg_NumFrames;
u32 RegVal;
u32 cmdindex;
u32 CmdBuf[XFPGA_DATA_CONFIG_CMD_LEN];
s32 i;
Status = XFpga_GetFirmwareState();
if (Status == XFPGA_FIRMWARE_STATE_UNKNOWN) {
Xfpga_Printf(XFPGA_DEBUG, "Error while reading configuration "
"data from FPGA\n\r");
Status = XFPGA_ERROR_PLSTATE_UNKNOWN;
goto END;
}
if ((Status == XFPGA_FIRMWARE_STATE_SECURE) &&
(XFPGA_SECURE_READBACK_MODE_EN == 0U)) {
Xfpga_Printf(XFPGA_DEBUG, "Operation not permitted\n\r");
Status = XFPGA_FAILURE;
goto END;
}
/* Enable the PCAP clk */
RegVal = Xil_In32(PCAP_CLK_CTRL);
/*
* There is no h/w flow control for pcap read
* to prevent the FIFO from over flowing, reduce
* the PCAP operating frequency.
*/
RegVal |= 0x3F00U;
Xil_Out32(PCAP_CLK_CTRL, RegVal | PCAP_CLK_EN_MASK);
/* Take PCAP out of Reset */
Status = XFpga_PcapInit(1U);
if (Status != XFPGA_SUCCESS) {
Status = XPFGA_ERROR_PCAP_INIT;
Xfpga_Printf(XFPGA_DEBUG, "PCAP init failed\n\r");
goto END;
}
cmdindex = 0U;
/* Step 1 */
CmdBuf[cmdindex] = 0xFFFFFFFFU; /* Dummy Word */
cmdindex++;
CmdBuf[cmdindex] = 0x000000BBU; /* Bus Width Sync Word */
cmdindex++;
CmdBuf[cmdindex] = 0x11220044U; /* Bus Width Detect */
cmdindex++;
CmdBuf[cmdindex] = 0xFFFFFFFFU; /* Dummy Word */
cmdindex++;
CmdBuf[cmdindex] = 0xAA995566U; /* Sync Word */
cmdindex++;
/* Step 2 */
CmdBuf[cmdindex] = 0x02000000U; /* Type 1 NOOP Word 0 */
cmdindex++;
/* Step 3 */ /* Type 1 Write 1 Word to CMD */
CmdBuf[cmdindex] = Xfpga_RegAddr(CMD, OPCODE_WRITE, 0x1U);
cmdindex++;
CmdBuf[cmdindex] = 0x0000000BU; /* SHUTDOWN Command */
cmdindex++;
CmdBuf[cmdindex] = 0x02000000U; /* Type 1 NOOP Word 0 */
cmdindex++;
/* Step 4 */ /* Type 1 Write 1 Word to CMD */
CmdBuf[cmdindex] = Xfpga_RegAddr(CMD, OPCODE_WRITE, 0x1U);
cmdindex++;
CmdBuf[cmdindex] = 0x00000007U; /* RCRC Command */
cmdindex++;
CmdBuf[cmdindex] = 0x20000000U; /* Type 1 NOOP Word 0 */
cmdindex++;
/* Step 5 --- 5 NOOPS Words */
for (i = 0 ; i < (s32)5 ; i++) {
CmdBuf[cmdindex] = 0x20000000U;
cmdindex++;
}
/* Step 6 */ /* Type 1 Write 1 Word to CMD */
CmdBuf[cmdindex] = Xfpga_RegAddr(CMD, OPCODE_WRITE, 0x1U);
cmdindex++;
CmdBuf[cmdindex] = 0x00000004U; /* RCFG Command */
cmdindex++;
CmdBuf[cmdindex] = 0x20000000U; /* Type 1 NOOP Word 0 */
cmdindex++;
/* Step 7 */ /* Type 1 Write 1 Word to FAR */
CmdBuf[cmdindex] = Xfpga_RegAddr(FAR1, OPCODE_WRITE, 0x1U);
cmdindex++;
CmdBuf[cmdindex] = 0x00000000U; /* FAR Address = 00000000 */
cmdindex++;
/* Step 8 */ /* Type 1 Read 0 Words from FDRO */
CmdBuf[cmdindex] = Xfpga_RegAddr(FDRO, OPCODE_READ, 0U);
cmdindex++;
/* Type 2 Read Wordlenght Words from FDRO */
CmdBuf[cmdindex] = Xfpga_Type2Pkt(OPCODE_READ, NumFrames);
cmdindex++;
/* Step 9 --- 64 NOOPS Words */
for (i = 0 ; i < (s32)64 ; i++) {
CmdBuf[cmdindex] = 0x20000000U;
cmdindex++;
}
XCsuDma_EnableIntr(CsuDmaPtr, XCSUDMA_DST_CHANNEL,
XCSUDMA_IXR_DST_MASK);
/* Flush the DMA buffer */
Xil_DCacheFlushRange(Address, NumFrames * 4U);
/* Set up the Destination DMA Channel*/
XCsuDma_Transfer(CsuDmaPtr, XCSUDMA_DST_CHANNEL,
Address, NumFrames, 0U);
Status = XFpga_PcapWaitForDone();
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG, "Write to PCAP Failed\n\r");
Status = XFPGA_FAILURE;
goto END;
}
Status = XFpga_WriteToPcap(cmdindex, (UINTPTR)CmdBuf);
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG, "Write to PCAP Failed\n\r");
Status = XFPGA_FAILURE;
goto END;
}
/*
* Setup the SSS, setup the DMA to receive from PCAP source
*/
Xil_Out32(CSU_CSU_SSS_CFG, XFPGA_CSU_SSS_SRC_DST_DMA);
Xil_Out32(CSU_PCAP_RDWR, 0x1U);
/* wait for the DST_DMA to complete and the pcap to be IDLE */
Status = XCsuDma_WaitForDoneTimeout(CsuDmaPtr, XCSUDMA_DST_CHANNEL);
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG, "Read from PCAP Failed\n\r");
Status = XFPGA_FAILURE;
goto END;
}
/* Acknowledge the transfer has completed */
XCsuDma_IntrClear(CsuDmaPtr, XCSUDMA_DST_CHANNEL, XCSUDMA_IXR_DONE_MASK);
Status = XFpga_PcapWaitForidle();
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG, "Reading data from PL through PCAP Failed\n\r");
Status = XFPGA_FAILURE;
goto END;
}
cmdindex = 0U;
/* Step 11 */
CmdBuf[cmdindex] = 0x20000000U; /* Type 1 NOOP Word 0 */
cmdindex++;
/* Step 12 */
CmdBuf[cmdindex] = 0x30008001U; /* Type 1 Write 1 Word to CMD */
cmdindex++;
CmdBuf[cmdindex] = 0x00000005U; /* START Command */
cmdindex++;
CmdBuf[cmdindex] = 0x20000000U; /* Type 1 NOOP Word 0 */
cmdindex++;
/* Step 13 */
CmdBuf[cmdindex] = 0x30008001U; /* Type 1 Write 1 Word to CMD */
cmdindex++;
CmdBuf[cmdindex] = 0x00000007U; /* RCRC Command */
cmdindex++;
CmdBuf[cmdindex] = 0x20000000U; /* Type 1 NOOP Word 0 */
cmdindex++;
/* Step 14 */
CmdBuf[cmdindex] = 0x30008001U; /* Type 1 Write 1 Word to CMD */
cmdindex++;
CmdBuf[cmdindex] = 0x0000000DU; /* DESYNC Command */
cmdindex++;
/* Step 15 */
CmdBuf[cmdindex] = 0x20000000U; /* Type 1 NOOP Word 0 */
cmdindex++;
CmdBuf[cmdindex] = 0x20000000U; /* Type 1 NOOP Word 0 */
cmdindex++;
Status = XFpga_WriteToPcap(cmdindex, (UINTPTR)CmdBuf);
if (Status != XFPGA_SUCCESS) {
Xfpga_Printf(XFPGA_DEBUG, "Write to PCAP 1 Failed\n\r");
Status = XFPGA_FAILURE;
}
END:
/* Disable the PCAP clk */
RegVal = Xil_In32(PCAP_CLK_CTRL);
Xil_Out32(PCAP_CLK_CTRL, RegVal & ~(PCAP_CLK_EN_MASK));
return Status;
}
/****************************************************************************/
/*
*
* Generates a Type 1 packet header that reads back the requested Configuration
* register.
*
* @param Register is the address of the register to be read back.
* @param OpCode is the read/write operation code.
* @param Size is the size of the word to be read.
*
* @return Type 1 packet header to read the specified register
*
* @note None.
*
*****************************************************************************/
static u32 Xfpga_RegAddr(u8 Register, u8 OpCode, u16 Size)
{
/*
* Type 1 Packet Header Format
* The header section is always a 32-bit word.
*
* HeaderType | Opcode | Register Address | Reserved | Word Count
* [31:29] [28:27] [26:13] [12:11] [10:0]
* --------------------------------------------------------------
* 001 xx RRRRRRRRRxxxxx RR xxxxxxxxxxx
*
* �R� means the bit is not used and reserved for future use.
* The reserved bits should be written as 0s.
*
* Generating the Type 1 packet header which involves sifting of Type 1
* Header Mask, Register value and the OpCode which is 01 in this case
* as only read operation is to be carried out and then performing OR
* operation with the Word Length.
*/
return ((u32)(((u32)XDC_TYPE_1 << (u32)XDC_TYPE_SHIFT) |
((u32)Register << (u32)XDC_REGISTER_SHIFT) |
((u32)OpCode << (u32)XDC_OP_SHIFT)) | (u32)Size);
}
/****************************************************************************/
/**
*
* Generates a Type 2 packet header that reads back the requested Configuration
* register.
*
* @param OpCode is the read/write operation code.
* @param Size is the size of the word to be read.
*
* @return Type 2 packet header to read the specified register
*
* @note None.
*****************************************************************************/
static u32 Xfpga_Type2Pkt(u8 OpCode, u32 Size)
{
/*
* Type 2 Packet Header Format
* The header section is always a 32-bit word.
*
* HeaderType | Opcode | Word Count
* [31:29] [28:27] [26:0]
* --------------------------------------------------------------
* 010 xx xxxxxxxxxxxxx
*
* �R� means the bit is not used and reserved for future use.
* The reserved bits should be written as 0s.
*
* Generating the Type 2 packet header which involves sifting of Type 2
* Header Mask, OpCode and then performing OR
* operation with the Word Length.
*/
return ((u32)(((u32)XDC_TYPE_2 << (u32)XDC_TYPE_SHIFT) |
((u32)OpCode << (u32)XDC_OP_SHIFT)) | (u32)Size);
}
/*****************************************************************************/
/** Sets the library firmware state
*
* @param State xilfpga firmware state
*
* @return None
*****************************************************************************/
static void XFpga_SetFirmwareState(u8 State)
{
u32 RegVal;
/* Set Firmware State in PMU GLOBAL GEN STORAGE1 Register */
RegVal = Xil_In32(PMU_GLOBAL_GEN_STORAGE5);
RegVal &= ~XFPGA_STATE_MASK;
RegVal |= ((u32)State << XFPGA_STATE_SHIFT);
Xil_Out32(PMU_GLOBAL_GEN_STORAGE5, RegVal);
}
/*****************************************************************************/
/** Returns the library firmware state
*
* @param None
*
* @return library firmware state
*****************************************************************************/
static u8 XFpga_GetFirmwareState(void)
{
return (Xil_In32(PMU_GLOBAL_GEN_STORAGE5) & XFPGA_STATE_MASK) >>
XFPGA_STATE_SHIFT;
}
/*****************************************************************************/
/* This function is responsible for identifying the Bitstream Endianness,
* and set the required csudma configurations before transfer the data
* into the PL.
*
* @param Buf Linear memory image base address
* @param Size Size of the Bitstream Image(Number of bytes).
* @Param Pos Bitstream First Dummy Word position.
*
* @return
* - XFPGA_SUCCESS if successful
* - XFPGA_ERROR_BITSTREAM_FORMAT if unsuccessful
*
*****************************************************************************/
static u32 XFpga_SelectEndianess(u8 *Buf, u32 Size, u32 *Pos)
{
u32 Index;
u32 RegVal;
u32 Status = XFPGA_ERROR_BITSTREAM_FORMAT;
u8 EndianType = 0U;
u8 BitHdrSize = ARRAY_LENGTH(BootgenBinFormat);
u32 IsBitNonAligned;
/* Check for Bitstream Size */
if(Size ==0U){
goto END;
}
/* Check For Header length */
if(BitHdrSize ==0U){
goto END;
}
for (Index = 0U; Index <= BOOTGEN_DATA_OFFSET; Index++) {
/* Find the First Dummy Byte */
if (Buf[Index] == DUMMY_BYTE) {
/* For Bootgen generated Bin files */
if ((memcmp(&Buf[Index + SYNC_BYTE_POSITION],
BootgenBinFormat, BitHdrSize)) == 0) {
EndianType = 0U;
Status = XFPGA_SUCCESS;
break;
}
/* For Vivado generated Bit files */
if ((memcmp(&Buf[Index + SYNC_BYTE_POSITION],
VivadoBinFormat, BitHdrSize)) == 0) {
EndianType = 1U;
Status = XFPGA_SUCCESS;
break;
}
}
}
if (Status != XFPGA_SUCCESS) {
goto END;
}
IsBitNonAligned = Index % 4U;
if (IsBitNonAligned != 0U) {
(void)memcpy(Buf, Buf + IsBitNonAligned, Size - IsBitNonAligned);
Index -= IsBitNonAligned;
}
RegVal = XCsuDma_ReadReg(CsuDmaPtr->Config.BaseAddress,
((u32)(XCSUDMA_CTRL_OFFSET) +
((u32)XCSUDMA_SRC_CHANNEL *
(u32)(XCSUDMA_OFFSET_DIFF))));
RegVal |= ((u32)EndianType << (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) &
(u32)(XCSUDMA_CTRL_ENDIAN_MASK);
XCsuDma_WriteReg(CsuDmaPtr->Config.BaseAddress,
((u32)(XCSUDMA_CTRL_OFFSET) +
((u32)XCSUDMA_SRC_CHANNEL *
(u32)(XCSUDMA_OFFSET_DIFF))), RegVal);
*Pos = Index;
END:
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_mod_common.c
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_default.h"
#include "xpfw_config.h"
#include "xpfw_core.h"
#include "xpfw_module.h"
#include "xpfw_error_manager.h"
#include "xpfw_restart.h"
#include "xpfw_mod_wdt.h"
#if defined(ENABLE_SCHEDULER) && (defined(ENABLE_EM) || defined(ENABLE_WDT) || defined(ENABLE_SECURE))
const XPfw_Module_t *CommonModPtr;
/****************************************************************************/
/**
* @brief This scheduler task checks for FSBL execution completion and
* performs other module's operation which are dependent on this.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
static void CheckFsblCompletion(void)
{
s32 Status;
u32 FsblCompletionStatus = XPfw_Read32(PMU_GLOBAL_GLOBAL_GEN_STORAGE5);
if (FSBL_COMPLETION == (FsblCompletionStatus & FSBL_COMPLETION)) {
#ifdef ENABLE_EM
/* Clear previous PLL lock errors if any */
XPfw_Write32(PMU_GLOBAL_ERROR_STATUS_2, PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_MASK);
/* Set PS Error Out action for PLL lock errors */
if (XST_SUCCESS !=
XPfw_EmSetAction(EM_ERR_ID_PLL_LOCK, EM_ACTION_PSERR, NULL)) {
XPfw_Printf(DEBUG_DETAILED,"Common: Set error action for "
"PLL Lock errors failed\r\n");
}
/*
* Once FSBL execution is completed, PMU need to enable the LPD/FPD WDT
* error and set the error action as FSBL disables while exiting.
*/
if (FSBL_RUNNING_ON_A53 ==
(FsblCompletionStatus & FSBL_STATE_PROC_INFO_MASK)) {
if (XST_SUCCESS != XPfw_EmSetAction(EM_ERR_ID_FPD_SWDT,
SWDT_EM_ACTION, ErrorTable[EM_ERR_ID_FPD_SWDT].Handler)) {
XPfw_Printf(DEBUG_DETAILED,"Common: Set error action for "
"FPD WDT error failed\r\n");
}
if (XST_SUCCESS != XPfw_EmSetAction(EM_ERR_ID_LPD_SWDT,
EM_ACTION_SRST, ErrorTable[EM_ERR_ID_LPD_SWDT].Handler)) {
XPfw_Printf(DEBUG_DETAILED,"Common: Set error action for "
"LPD WDT error failed\r\n");
}
} else {
if (XST_SUCCESS != XPfw_EmSetAction(EM_ERR_ID_FPD_SWDT,
EM_ACTION_SRST, ErrorTable[EM_ERR_ID_FPD_SWDT].Handler)) {
XPfw_Printf(DEBUG_DETAILED,"Common: Set error action for "
"FPD WDT error failed\r\n");
}
if (XST_SUCCESS != XPfw_EmSetAction(EM_ERR_ID_LPD_SWDT,
SWDT_EM_ACTION, ErrorTable[EM_ERR_ID_LPD_SWDT].Handler)) {
XPfw_Printf(DEBUG_DETAILED,"Common: Set error action for "
"LPD WDT error failed\r\n");
}
}
/* If ENABLE_RECOVERY is defined, PMU need to call this function and
* set FPD/LPD WDT error action accordingly after FSBL execution
* is completed.
*/
if ((u32)XST_SUCCESS == XPfw_RecoveryInit()) {
/* This is to enable FPD/LPD WDT and enable recovery mechanism when
* ENABLE_RECOVERY flag is defined.
*/
}
#endif
#if defined(USE_DDR_FOR_APU_RESTART) && defined(ENABLE_SECURE)
/*
* Store FSBL to reserved DDR memory location.
*/
Status = XPfw_StoreFsblToDDR();
if (XST_SUCCESS != Status) {
XPfw_Printf(DEBUG_ERROR,"%s: Error! Storing FSBL for "
"APU-only restart failed. APU-only warm-restart "
"may not work\r\n", __func__);
}
#endif
#ifdef ENABLE_WDT
/*
* Initialization of PMU WDT
*/
InitCsuPmuWdt();
#endif
Status = XPfw_CoreRemoveTask(CommonModPtr, (u32)CHECK_FSBL_COMPLETION,
CheckFsblCompletion);
if (XST_FAILURE == Status) {
XPfw_Printf(DEBUG_ERROR,"Common (MOD-%d):Removing Common config task "
"failed.", CommonModPtr->ModId);
}
}
}
/****************************************************************************/
/**
* @brief Module init which schedules a task for checking FSBL completion.
*
* @param ModPtr Module pointer
* CfgData Module config data
* Len Length of config data
*
* @return None.
*
* @note None.
*
****************************************************************************/
static void CommonCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
{
s32 Status;
/*
* Schedule a task to check for FSBL completion and do the following:
* EM Module:
* - Clear PLL lock errors occurred during FSBL initialization
* - Enable PLL lock errors and set error action
* - Set error action for FPD WDT and LPD WDT errors
* WDT Module:
* - Call PMU WDT initialize function
* Common functionality:
* - If ENABLE_SECURE is defined, store the FSBL image to reserved
* DDR memory location
*/
Status = XPfw_CoreScheduleTask(ModPtr, CHECK_FSBL_COMPLETION, CheckFsblCompletion);
if (XST_FAILURE == Status) {
XPfw_Printf(DEBUG_ERROR,"Common (MOD-%d):Scheduling Common Cfg task failed.",
ModPtr->ModId);
}
}
/****************************************************************************/
/**
* @brief Module init which schedules a task for
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
/*
* Create a Mod and assign the Handlers. We will call this function
* from XPfw_UserStartup()
*/
void ModCommonInit(void)
{
CommonModPtr = XPfw_CoreCreateMod();
if (XST_SUCCESS != XPfw_CoreSetCfgHandler(CommonModPtr, CommonCfgInit)) {
XPfw_Printf(DEBUG_DETAILED,"Common: Set Cfg handler failed\r\n");
}
}
#else
void ModCommonInit(void) { }
#endif /* ENABLE_SCHEDULER */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pll.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PLL_H_
#define XPM_PLL_H_
#include "xpm_clock.h"
#include "xpm_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* The PLL class. This is the class to represent pll nodes.
*/
typedef struct XPm_PllParam {
uint8_t Shift;
uint8_t Width;
} XPm_PllParam;
struct XPm_PllTopology {
uint16_t Id;
XPm_PllParam ConfigParams[PM_PLL_PARAM_MAX];
uint8_t ResetShift;
uint8_t BypassShift;
uint8_t LockShift;
uint8_t StableShift;
uint8_t PllReg3Offset;
};
typedef struct XPm_PllClockNode XPm_PllClockNode;
/**
* PmPllContext - Structure for saving context of PLL registers.
* Contains variable to store default content of:
* @ctrl Control register
* @cfg Configuration register
* @frac Fractional control register
* @flag Indicates context saved or not
*
* Note: context of the PLL is saved when PM framework suspends a PLL (when
* no node requires PLL to be locked).
*/
typedef struct PmPllContext {
u32 Ctrl;
u32 Cfg;
u32 Frac;
u8 Flag;
} PmPllContext;
struct XPm_PllClockNode {
XPm_ClockNode ClkNode;
u32 StatusReg;
u32 ConfigReg;
u32 FracConfigReg;
u8 PllMode;
struct XPm_PllTopology *Topology;
PmPllContext Context;
};
#define ISPLL(id) ((NODECLASS(id) == (u32)XPM_NODECLASS_CLOCK) && \
(NODESUBCLASS(id) == (u32)XPM_NODESUBCL_CLOCK_PLL) && \
(NODEINDEX(id) < (u32)XPM_NODEIDX_CLK_MAX))
#define RESET_SHIFT 0U
#define BYPASS_SHIFT 3U
#define GEN_LOCK_SHIFT 0U
#define NPLL_LOCK_SHIFT 1U
#define GEN_STABLE_SHIFT 2U
#define NPLL_STABLE_SHIFT 3U
#define GEN_REG3_OFFSET 0x68U
#define NPLL_REG3_OFFSET 0xA8U
#define PPLL_REG3_OFFSET 0x78U
#define PLL_REG3_CP_RES_H_SHIFT 20U
#define PLL_REG3_CP_RES_H_WIDTH 2U
#define PLLPARAMS { \
[PM_PLL_PARAM_ID_DIV2] = { \
.Shift = 16U, \
.Width = 2U, \
}, \
[PM_PLL_PARAM_ID_FBDIV] = { \
.Shift = 8U, \
.Width = 7U, \
}, \
[PM_PLL_PARAM_ID_DATA] = { \
.Shift = 0U, \
.Width = 16U, \
}, \
[PM_PLL_PARAM_ID_PRE_SRC] = { \
.Shift = 20U, \
.Width = 3U, \
}, \
[PM_PLL_PARAM_ID_POST_SRC] = { \
.Shift = 24U, \
.Width = 3U, \
}, \
[PM_PLL_PARAM_ID_LOCK_DLY] = { \
.Shift = 25U, \
.Width = 7U, \
}, \
[PM_PLL_PARAM_ID_LOCK_CNT] = { \
.Shift = 13U, \
.Width = 10U, \
}, \
[PM_PLL_PARAM_ID_LFHF] = { \
.Shift = 10U, \
.Width = 2U, \
}, \
[PM_PLL_PARAM_ID_CP] = { \
.Shift = 5U, \
.Width = 4U, \
}, \
[PM_PLL_PARAM_ID_RES] = { \
.Shift = 0U, \
.Width = 4U, \
}, \
}
/* TBD: TImeout value need to be defined as per spec */
#define PLL_LOCK_TIMEOUT 0x10000U
/* PLL Flags */
#define PLL_RESET_ASSERT 1U
#define PLL_RESET_RELEASE 2U
#define PLL_RESET_PULSE (PLL_RESET_ASSERT | PLL_RESET_RELEASE)
#define PM_PLL_CONTEXT_SAVED 1U
/* PLL states: */
#define PM_PLL_STATE_RESET 0U
#define PM_PLL_STATE_LOCKED 1U
#define PM_PLL_STATE_SUSPENDED 2U
#define PLL_FRAC_CFG_ENABLED_MASK (0x80000000U)
/************************** Function Prototypes ******************************/
XStatus XPmClockPll_AddNode(u32 Id, u32 ControlReg, u8 TopologyType,
u16 *Offsets, u32 PowerDomainId, u8 ClkFlags);
XStatus XPmClockPll_AddParent(u32 Id, u32 *Parents, u8 NumParents);
XStatus XPmClockPll_Request(u32 PllId);
XStatus XPmClockPll_Release(u32 PllId);
XStatus XPmClockPll_SetMode(XPm_PllClockNode *Pll, u32 Mode);
XStatus XPmClockPll_GetMode(XPm_PllClockNode *Pll, u32 *Mode);
XStatus XPmClockPll_Suspend(XPm_PllClockNode *Pll);
XStatus XPmClockPll_Resume(XPm_PllClockNode *Pll);
XStatus XPmClockPll_Reset(XPm_PllClockNode *Pll, uint8_t Flags);
XStatus XPmClockPll_SetParam(XPm_PllClockNode *Pll, u32 Param,u32 Value);
XStatus XPmClockPll_GetParam(XPm_PllClockNode *Pll, u32 Param,u32 *Val);
int XPmClockPll_QueryMuxSources(u32 Id, u32 Index, u32 *Resp);
int XPmClockPll_GetWakeupLatency(const u32 Id, u32 *Latency);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_PLL_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_node.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_NODE_H_
#define XPM_NODE_H_
#include <xil_types.h>
#include <xstatus.h>
#include "xpm_nodeid.h"
#ifdef __cplusplus
extern "C" {
#endif
#define NODE_IDLE_DONE (0x4U)
typedef struct XPm_Node XPm_Node;
/**
* The node class. This is the base class for all the power, clock, pin and
* reset node classes.
*/
struct XPm_Node {
u32 Id; /**< Node ID: For LibPM clock and pin APIs */
u32 BaseAddress; /**< Base address: Specify to node type */
u16 LatencyMarg; /**< lowest latency requirement - powerup latency */
u8 State; /**< Node state: Specific to node type */
u8 Flags;
};
/************************** Function Prototypes ******************************/
void XPmNode_Init(XPm_Node *Node, u32 Id, u8 State, u32 BaseAddress);
#define NODE_CLASS_SHIFT 26U
#define NODE_SUBCLASS_SHIFT 20U
#define NODE_TYPE_SHIFT 14U
#define NODE_INDEX_SHIFT 0U
#define NODE_CLASS_MASK_BITS 0x3FU
#define NODE_SUBCLASS_MASK_BITS 0x3FU
#define NODE_TYPE_MASK_BITS 0x3FU
#define NODE_INDEX_MASK_BITS 0x3FFFU
#define NODE_CLASS_MASK ((u32)NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
#define NODE_SUBCLASS_MASK ((u32)NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT)
#define NODE_TYPE_MASK ((u32)NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT)
#define NODE_INDEX_MASK ((u32)NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT)
#define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \
((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
(((SUBCLASS) & NODE_SUBCLASS_MASK_BITS) << NODE_SUBCLASS_SHIFT) | \
(((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
(((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
#define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
#define NODESUBCLASS(ID) (((ID) & NODE_SUBCLASS_MASK) >> NODE_SUBCLASS_SHIFT)
#define NODETYPE(ID) (((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT)
#define NODEINDEX(ID) (((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT)
#define LMIONODEID(PIN_NUM) NODEID(XPM_NODECLASS_STMIC,\
XPM_NODESUBCL_PIN, XPM_NODETYPE_LPD_MIO, (PIN_NUM) + XPM_NODEIDX_STMIC_LMIO_0)
#define PMIONODEID(PIN_NUM) NODEID(XPM_NODECLASS_STMIC,\
XPM_NODESUBCL_PIN, XPM_NODETYPE_PMC_MIO, (PIN_NUM) + XPM_NODEIDX_STMIC_PMIO_0)
/* Node class types */
typedef enum class {
XPM_NODECLASS_MIN,
XPM_NODECLASS_POWER,
XPM_NODECLASS_CLOCK,
XPM_NODECLASS_RESET,
XPM_NODECLASS_MEMIC,
XPM_NODECLASS_STMIC,
XPM_NODECLASS_DEVICE,
XPM_NODECLASS_SUBSYSTEM,
XPM_NODECLASS_ISOLATION,
XPM_NODECLASS_PROTECTION,
XPM_NODECLASS_EVENT,
XPM_NODECLASS_MONITOR,
XPM_NODECLASS_MAX
} XPm_NodeClass;
/* Node subclass types */
typedef enum {
/* Power nodes */
XPM_NODESUBCL_POWER_ISLAND=1,
XPM_NODESUBCL_POWER_DOMAIN,
} XPm_PowerNodeSubclass;
typedef enum {
/* Clock nodes */
XPM_NODESUBCL_CLOCK_PLL=1,
XPM_NODESUBCL_CLOCK_OUT,
XPM_NODESUBCL_CLOCK_REF,
} XPm_ClockNodeSubclass;
typedef enum {
/* Reset nodes */
XPM_NODESUBCL_RESET_PERIPHERAL=1,
XPM_NODESUBCL_RESET_DBG,
XPM_NODESUBCL_RESET_POR,
XPM_NODESUBCL_RESET_SRST,
} XPm_ResetNodeSubclass;
typedef enum {
/* MEMIC subclasses */
XPM_NODESUBCL_MEMIC_NOC,
} XPm_MemicNodeSubclass;
typedef enum {
/* Pin nodes */
XPM_NODESUBCL_PIN=1,
} XPm_PinNodeSubclass;
typedef enum {
/* Device types */
XPM_NODESUBCL_DEV_CORE=1,
XPM_NODESUBCL_DEV_PERIPH,
XPM_NODESUBCL_DEV_MEM,
XPM_NODESUBCL_DEV_SOC,
XPM_NODESUBCL_DEV_MEM_CTRLR,
XPM_NODESUBCL_DEV_PHY,
XPM_NODESUBCL_DEV_PL,
} XPm_DeviceNodeSubclass;
typedef enum {
/* Subsystem classes */
XPM_NODESUBCL_SUBSYSTEM=0,
} XPm_SubsystemSubclass;
typedef enum {
/* isoaltion subclasses */
XPM_NODESUBCL_ISOLATION=0,
} XPm_IsolationSubclass;
typedef enum {
/* Protection subclasses */
XPM_NODESUBCL_PROT_XPPU,
XPM_NODESUBCL_PROT_XMPU,
} XPm_ProtNodeSubclass;
typedef enum {
/* Monitor subclasses */
XPM_NODESUBCL_MONITOR_SYSMON,
} XPm_MonitorSubclass;
/* Node types */
typedef enum {
/* Power nodes */
XPM_NODETYPE_POWER_ISLAND=1,
XPM_NODETYPE_POWER_DOMAIN_PMC,
XPM_NODETYPE_POWER_DOMAIN_PS_FULL,
XPM_NODETYPE_POWER_DOMAIN_PS_LOW,
XPM_NODETYPE_POWER_DOMAIN_NOC,
XPM_NODETYPE_POWER_DOMAIN_CPM,
XPM_NODETYPE_POWER_DOMAIN_ME,
XPM_NODETYPE_POWER_DOMAIN_PL,
XPM_NODETYPE_POWER_ISLAND_XRAM,
} XPm_PowerNodeType;
typedef enum {
/* Clock nodes */
XPM_NODETYPE_CLOCK_PLL=1,
XPM_NODETYPE_CLOCK_OUT,
XPM_NODETYPE_CLOCK_REF,
XPM_NODETYPE_CLOCK_SUBNODE,
} XPm_ClockNodeType;
typedef enum {
/* Reset nodes */
XPM_NODETYPE_RESET_PERIPHERAL=1,
XPM_NODETYPE_RESET_DBG,
XPM_NODETYPE_RESET_POR,
XPM_NODETYPE_RESET_SRST,
} XPm_ResetNodeType;
typedef enum {
/* MEMIC node types */
XPM_NODETYPE_MEMIC_MASTER,
XPM_NODETYPE_MEMIC_SLAVE,
} XPm_MemicNodeType;
typedef enum {
/* Pin nodes */
XPM_NODETYPE_LPD_MIO=1,
XPM_NODETYPE_PMC_MIO,
} XPm_PinNodeType;
typedef enum {
/* Device types */
XPM_NODETYPE_DEV_CORE_PMC=1,
XPM_NODETYPE_DEV_CORE_PSM,
XPM_NODETYPE_DEV_CORE_APU,
XPM_NODETYPE_DEV_CORE_RPU,
XPM_NODETYPE_DEV_OCM,
XPM_NODETYPE_DEV_TCM,
XPM_NODETYPE_DEV_L2CACHE,
XPM_NODETYPE_DEV_DDR,
XPM_NODETYPE_DEV_PERIPH,
XPM_NODETYPE_DEV_SOC,
XPM_NODETYPE_DEV_GT,
XPM_NODETYPE_DEV_EFUSE,
XPM_NODETYPE_DEV_XRAM,
} XPm_DeviceNodeType;
typedef enum {
/* Subsystem types */
XPM_NODETYPE_SUBSYSTEM=0,
} XPm_SubsystemTypes;
typedef enum {
/* isoaltion types */
XPM_NODETYPE_ISOLATION=0,
} XPm_IsolationTypes;
typedef enum {
/* Protection types */
XPM_NODETYPE_PROTECTION=0,
} XPm_ProtTypes;
typedef enum {
/* Monitor types */
XPM_NODETYPE_MONITOR_SYSMON_PMC,
XPM_NODETYPE_MONITOR_SYSMON_PS,
XPM_NODETYPE_MONITOR_SYSMON_NPD,
} XPm_MonitorType;
/* All node IDs */
typedef enum {
/* Power nodes */
XPM_NODEIDX_POWER_MIN,
/* Power domains */
XPM_NODEIDX_POWER_PMC,
XPM_NODEIDX_POWER_LPD,
XPM_NODEIDX_POWER_FPD,
XPM_NODEIDX_POWER_NOC,
XPM_NODEIDX_POWER_ME,
XPM_NODEIDX_POWER_PLD,
XPM_NODEIDX_POWER_CPM,
XPM_NODEIDX_POWER_PL_SYSMON,
/* LPD power islands */
XPM_NODEIDX_POWER_RPU0_0,
XPM_NODEIDX_POWER_GEM0,
XPM_NODEIDX_POWER_GEM1,
XPM_NODEIDX_POWER_OCM_0,
XPM_NODEIDX_POWER_OCM_1,
XPM_NODEIDX_POWER_OCM_2,
XPM_NODEIDX_POWER_OCM_3,
XPM_NODEIDX_POWER_TCM_0_A,
XPM_NODEIDX_POWER_TCM_0_B,
XPM_NODEIDX_POWER_TCM_1_A,
XPM_NODEIDX_POWER_TCM_1_B,
/* FPD power islands */
XPM_NODEIDX_POWER_ACPU_0,
XPM_NODEIDX_POWER_ACPU_1,
XPM_NODEIDX_POWER_L2_BANK_0,
/* XRAM power islands */
XPM_NODEIDX_POWER_XRAM_0,
XPM_NODEIDX_POWER_XRAM_1,
XPM_NODEIDX_POWER_XRAM_2,
XPM_NODEIDX_POWER_XRAM_3,
XPM_NODEIDX_POWER_XRAM_4,
XPM_NODEIDX_POWER_XRAM_5,
XPM_NODEIDX_POWER_XRAM_6,
XPM_NODEIDX_POWER_XRAM_7,
XPM_NODEIDX_POWER_XRAM_8,
XPM_NODEIDX_POWER_XRAM_9,
XPM_NODEIDX_POWER_XRAM_10,
XPM_NODEIDX_POWER_XRAM_11,
XPM_NODEIDX_POWER_XRAM_12,
XPM_NODEIDX_POWER_XRAM_13,
XPM_NODEIDX_POWER_XRAM_14,
XPM_NODEIDX_POWER_XRAM_15,
/* CPM 5 Power Domain */
XPM_NODEIDX_POWER_CPM5,
XPM_NODEIDX_POWER_MAX,
} XPm_PowerNodeIndex;
typedef enum {
XPM_NODEIDX_CLK_MIN,
XPM_NODEIDX_CLK_PMC_PLL,
XPM_NODEIDX_CLK_APU_PLL,
XPM_NODEIDX_CLK_RPU_PLL,
XPM_NODEIDX_CLK_CPM_PLL,
XPM_NODEIDX_CLK_NOC_PLL,
XPM_NODEIDX_CLK_PLL_MAX,
XPM_NODEIDX_CLK_PMC_PRESRC,
XPM_NODEIDX_CLK_PMC_POSTCLK,
XPM_NODEIDX_CLK_PMC_PLL_OUT,
XPM_NODEIDX_CLK_PPLL,
XPM_NODEIDX_CLK_NOC_PRESRC,
XPM_NODEIDX_CLK_NOC_POSTCLK,
XPM_NODEIDX_CLK_NOC_PLL_OUT,
XPM_NODEIDX_CLK_NPLL,
XPM_NODEIDX_CLK_APU_PRESRC,
XPM_NODEIDX_CLK_APU_POSTCLK,
XPM_NODEIDX_CLK_APU_PLL_OUT,
XPM_NODEIDX_CLK_APLL,
XPM_NODEIDX_CLK_RPU_PRESRC,
XPM_NODEIDX_CLK_RPU_POSTCLK,
XPM_NODEIDX_CLK_RPU_PLL_OUT,
XPM_NODEIDX_CLK_RPLL,
XPM_NODEIDX_CLK_CPM_PRESRC,
XPM_NODEIDX_CLK_CPM_POSTCLK,
XPM_NODEIDX_CLK_CPM_PLL_OUT,
XPM_NODEIDX_CLK_CPLL,
XPM_NODEIDX_CLK_PPLL_TO_XPD,
XPM_NODEIDX_CLK_NPLL_TO_XPD,
XPM_NODEIDX_CLK_APLL_TO_XPD,
XPM_NODEIDX_CLK_RPLL_TO_XPD,
XPM_NODEIDX_CLK_EFUSE_REF,
XPM_NODEIDX_CLK_SYSMON_REF,
XPM_NODEIDX_CLK_IRO_SUSPEND_REF,
XPM_NODEIDX_CLK_USB_SUSPEND,
XPM_NODEIDX_CLK_SWITCH_TIMEOUT,
XPM_NODEIDX_CLK_RCLK_PMC,
XPM_NODEIDX_CLK_RCLK_LPD,
XPM_NODEIDX_CLK_WDT,
XPM_NODEIDX_CLK_TTC0,
XPM_NODEIDX_CLK_TTC1,
XPM_NODEIDX_CLK_TTC2,
XPM_NODEIDX_CLK_TTC3,
XPM_NODEIDX_CLK_GEM_TSU,
XPM_NODEIDX_CLK_GEM_TSU_LB,
XPM_NODEIDX_CLK_MUXED_IRO_DIV2,
XPM_NODEIDX_CLK_MUXED_IRO_DIV4,
XPM_NODEIDX_CLK_PSM_REF,
XPM_NODEIDX_CLK_GEM0_RX,
XPM_NODEIDX_CLK_GEM0_TX,
XPM_NODEIDX_CLK_GEM1_RX,
XPM_NODEIDX_CLK_GEM1_TX,
XPM_NODEIDX_CLK_CPM_CORE_REF,
XPM_NODEIDX_CLK_CPM_LSBUS_REF,
XPM_NODEIDX_CLK_CPM_DBG_REF,
XPM_NODEIDX_CLK_CPM_AUX0_REF,
XPM_NODEIDX_CLK_CPM_AUX1_REF,
XPM_NODEIDX_CLK_QSPI_REF,
XPM_NODEIDX_CLK_OSPI_REF,
XPM_NODEIDX_CLK_SDIO0_REF,
XPM_NODEIDX_CLK_SDIO1_REF,
XPM_NODEIDX_CLK_PMC_LSBUS_REF,
XPM_NODEIDX_CLK_I2C_REF,
XPM_NODEIDX_CLK_TEST_PATTERN_REF,
XPM_NODEIDX_CLK_DFT_OSC_REF,
XPM_NODEIDX_CLK_PMC_PL0_REF,
XPM_NODEIDX_CLK_PMC_PL1_REF,
XPM_NODEIDX_CLK_PMC_PL2_REF,
XPM_NODEIDX_CLK_PMC_PL3_REF,
XPM_NODEIDX_CLK_CFU_REF,
XPM_NODEIDX_CLK_SPARE_REF,
XPM_NODEIDX_CLK_NPI_REF,
XPM_NODEIDX_CLK_HSM0_REF,
XPM_NODEIDX_CLK_HSM1_REF,
XPM_NODEIDX_CLK_SD_DLL_REF,
XPM_NODEIDX_CLK_FPD_TOP_SWITCH,
XPM_NODEIDX_CLK_FPD_LSBUS,
XPM_NODEIDX_CLK_ACPU,
XPM_NODEIDX_CLK_DBG_TRACE,
XPM_NODEIDX_CLK_DBG_FPD,
XPM_NODEIDX_CLK_LPD_TOP_SWITCH,
XPM_NODEIDX_CLK_ADMA,
XPM_NODEIDX_CLK_LPD_LSBUS,
XPM_NODEIDX_CLK_CPU_R5,
XPM_NODEIDX_CLK_CPU_R5_CORE,
XPM_NODEIDX_CLK_CPU_R5_OCM,
XPM_NODEIDX_CLK_CPU_R5_OCM2,
XPM_NODEIDX_CLK_IOU_SWITCH,
XPM_NODEIDX_CLK_GEM0_REF,
XPM_NODEIDX_CLK_GEM1_REF,
XPM_NODEIDX_CLK_GEM_TSU_REF,
XPM_NODEIDX_CLK_USB0_BUS_REF,
XPM_NODEIDX_CLK_UART0_REF,
XPM_NODEIDX_CLK_UART1_REF,
XPM_NODEIDX_CLK_SPI0_REF,
XPM_NODEIDX_CLK_SPI1_REF,
XPM_NODEIDX_CLK_CAN0_REF,
XPM_NODEIDX_CLK_CAN1_REF,
XPM_NODEIDX_CLK_I2C0_REF,
XPM_NODEIDX_CLK_I2C1_REF,
XPM_NODEIDX_CLK_DBG_LPD,
XPM_NODEIDX_CLK_TIMESTAMP_REF,
XPM_NODEIDX_CLK_DBG_TSTMP,
XPM_NODEIDX_CLK_CPM_TOPSW_REF,
XPM_NODEIDX_CLK_USB3_DUAL_REF,
XPM_NODEIDX_CLK_OUTCLK_MAX,
XPM_NODEIDX_CLK_REF_CLK,
XPM_NODEIDX_CLK_PL_ALT_REF_CLK,
XPM_NODEIDX_CLK_MUXED_IRO,
XPM_NODEIDX_CLK_PL_EXT,
XPM_NODEIDX_CLK_PL_LB,
XPM_NODEIDX_CLK_MIO_50_OR_51,
XPM_NODEIDX_CLK_MIO_24_OR_25,
XPM_NODEIDX_CLK_EMIO,
XPM_NODEIDX_CLK_MIO,
XPM_NODEIDX_CLK_REF_MAX,
XPM_NODEIDX_CLK_XRAM_MAIN_CLK,
XPM_NODEIDX_CLK_XRAM_APB,
XPM_NODEIDX_CLK_MAX,
} XPm_ClockNodeIndex;
typedef enum {
/* Reset nodes */
XPM_NODEIDX_RST_MIN,
XPM_NODEIDX_RST_PMC_POR,
XPM_NODEIDX_RST_PMC,
XPM_NODEIDX_RST_PS_POR,
XPM_NODEIDX_RST_PL_POR,
XPM_NODEIDX_RST_NOC_POR,
XPM_NODEIDX_RST_FPD_POR,
XPM_NODEIDX_RST_ACPU_0_POR,
XPM_NODEIDX_RST_ACPU_1_POR,
XPM_NODEIDX_RST_OCM2_POR,
XPM_NODEIDX_RST_PS_SRST,
XPM_NODEIDX_RST_PL_SRST,
XPM_NODEIDX_RST_NOC,
XPM_NODEIDX_RST_NPI,
XPM_NODEIDX_RST_SYS_RST_1,
XPM_NODEIDX_RST_SYS_RST_2,
XPM_NODEIDX_RST_SYS_RST_3,
XPM_NODEIDX_RST_FPD,
XPM_NODEIDX_RST_PL0,
XPM_NODEIDX_RST_PL1,
XPM_NODEIDX_RST_PL2,
XPM_NODEIDX_RST_PL3,
XPM_NODEIDX_RST_APU,
XPM_NODEIDX_RST_ACPU_0,
XPM_NODEIDX_RST_ACPU_1,
XPM_NODEIDX_RST_ACPU_L2,
XPM_NODEIDX_RST_ACPU_GIC,
XPM_NODEIDX_RST_RPU_ISLAND,
XPM_NODEIDX_RST_RPU_AMBA,
XPM_NODEIDX_RST_R5_0,
XPM_NODEIDX_RST_R5_1,
XPM_NODEIDX_RST_SYSMON_PMC_SEQ_RST,
XPM_NODEIDX_RST_SYSMON_PMC_CFG_RST,
XPM_NODEIDX_RST_SYSMON_FPD_CFG_RST,
XPM_NODEIDX_RST_SYSMON_FPD_SEQ_RST,
XPM_NODEIDX_RST_SYSMON_LPD,
XPM_NODEIDX_RST_PDMA_RST1,
XPM_NODEIDX_RST_PDMA_RST0,
XPM_NODEIDX_RST_ADMA,
XPM_NODEIDX_RST_TIMESTAMP,
XPM_NODEIDX_RST_OCM,
XPM_NODEIDX_RST_OCM2_RST,
XPM_NODEIDX_RST_IPI,
XPM_NODEIDX_RST_SBI,
XPM_NODEIDX_RST_LPD,
XPM_NODEIDX_RST_QSPI,
XPM_NODEIDX_RST_OSPI,
XPM_NODEIDX_RST_SDIO_0,
XPM_NODEIDX_RST_SDIO_1,
XPM_NODEIDX_RST_I2C_PMC,
XPM_NODEIDX_RST_GPIO_PMC,
XPM_NODEIDX_RST_GEM_0,
XPM_NODEIDX_RST_GEM_1,
XPM_NODEIDX_RST_SPARE,
XPM_NODEIDX_RST_USB_0,
XPM_NODEIDX_RST_UART_0,
XPM_NODEIDX_RST_UART_1,
XPM_NODEIDX_RST_SPI_0,
XPM_NODEIDX_RST_SPI_1,
XPM_NODEIDX_RST_CAN_FD_0,
XPM_NODEIDX_RST_CAN_FD_1,
XPM_NODEIDX_RST_I2C_0,
XPM_NODEIDX_RST_I2C_1,
XPM_NODEIDX_RST_GPIO_LPD,
XPM_NODEIDX_RST_TTC_0,
XPM_NODEIDX_RST_TTC_1,
XPM_NODEIDX_RST_TTC_2,
XPM_NODEIDX_RST_TTC_3,
XPM_NODEIDX_RST_SWDT_FPD,
XPM_NODEIDX_RST_SWDT_LPD,
XPM_NODEIDX_RST_USB,
XPM_NODEIDX_RST_DPC,
XPM_NODEIDX_RST_PMCDBG,
XPM_NODEIDX_RST_DBG_TRACE,
XPM_NODEIDX_RST_DBG_FPD,
XPM_NODEIDX_RST_DBG_TSTMP,
XPM_NODEIDX_RST_RPU0_DBG,
XPM_NODEIDX_RST_RPU1_DBG,
XPM_NODEIDX_RST_HSDP,
XPM_NODEIDX_RST_DBG_LPD,
XPM_NODEIDX_RST_CPM_POR,
XPM_NODEIDX_RST_CPM,
XPM_NODEIDX_RST_CPMDBG,
XPM_NODEIDX_RST_PCIE_CFG,
XPM_NODEIDX_RST_PCIE_CORE0,
XPM_NODEIDX_RST_PCIE_CORE1,
XPM_NODEIDX_RST_PCIE_DMA,
XPM_NODEIDX_RST_CMN,
XPM_NODEIDX_RST_L2_0,
XPM_NODEIDX_RST_L2_1,
XPM_NODEIDX_RST_ADDR_REMAP,
XPM_NODEIDX_RST_CPI0,
XPM_NODEIDX_RST_CPI1,
XPM_NODEIDX_RST_XRAM,
XPM_NODEIDX_RST_AIE_ARRAY,
XPM_NODEIDX_RST_AIE_SHIM,
XPM_NODEIDX_RST_MAX,
} XPm_ResetNodeIndex;
typedef enum {
/* MEMIC nodes */
XPM_NODEIDX_MEMIC_NMU_0,
XPM_NODEIDX_MEMIC_NMU_1,
XPM_NODEIDX_MEMIC_NMU_2,
XPM_NODEIDX_MEMIC_NMU_3,
XPM_NODEIDX_MEMIC_NMU_4,
XPM_NODEIDX_MEMIC_NMU_5,
XPM_NODEIDX_MEMIC_NMU_6,
XPM_NODEIDX_MEMIC_NMU_7,
XPM_NODEIDX_MEMIC_NMU_8,
XPM_NODEIDX_MEMIC_NMU_9,
XPM_NODEIDX_MEMIC_NMU_10,
XPM_NODEIDX_MEMIC_NMU_11,
XPM_NODEIDX_MEMIC_NMU_12,
XPM_NODEIDX_MEMIC_NMU_13,
XPM_NODEIDX_MEMIC_NMU_14,
XPM_NODEIDX_MEMIC_NMU_15,
XPM_NODEIDX_MEMIC_NMU_16,
XPM_NODEIDX_MEMIC_NMU_17,
XPM_NODEIDX_MEMIC_NMU_18,
XPM_NODEIDX_MEMIC_NMU_19,
XPM_NODEIDX_MEMIC_NMU_20,
XPM_NODEIDX_MEMIC_NMU_21,
XPM_NODEIDX_MEMIC_NMU_22,
XPM_NODEIDX_MEMIC_NMU_23,
XPM_NODEIDX_MEMIC_NMU_24,
XPM_NODEIDX_MEMIC_NMU_25,
XPM_NODEIDX_MEMIC_NMU_26,
XPM_NODEIDX_MEMIC_NMU_27,
XPM_NODEIDX_MEMIC_NMU_28,
XPM_NODEIDX_MEMIC_NMU_29,
XPM_NODEIDX_MEMIC_NMU_30,
XPM_NODEIDX_MEMIC_NMU_31,
XPM_NODEIDX_MEMIC_NMU_32,
XPM_NODEIDX_MEMIC_NMU_33,
XPM_NODEIDX_MEMIC_NMU_34,
XPM_NODEIDX_MEMIC_NMU_35,
XPM_NODEIDX_MEMIC_NMU_36,
XPM_NODEIDX_MEMIC_NMU_37,
XPM_NODEIDX_MEMIC_NMU_38,
XPM_NODEIDX_MEMIC_NMU_39,
XPM_NODEIDX_MEMIC_NMU_40,
XPM_NODEIDX_MEMIC_NMU_41,
XPM_NODEIDX_MEMIC_NMU_42,
XPM_NODEIDX_MEMIC_NMU_43,
XPM_NODEIDX_MEMIC_NMU_44,
XPM_NODEIDX_MEMIC_NMU_45,
XPM_NODEIDX_MEMIC_NMU_46,
XPM_NODEIDX_MEMIC_NMU_47,
XPM_NODEIDX_MEMIC_NMU_48,
XPM_NODEIDX_MEMIC_NMU_49,
XPM_NODEIDX_MEMIC_NMU_50,
XPM_NODEIDX_MEMIC_NMU_51,
XPM_NODEIDX_MEMIC_NMU_52,
XPM_NODEIDX_MEMIC_NMU_53,
XPM_NODEIDX_MEMIC_NSU_0,
XPM_NODEIDX_MEMIC_NSU_1,
XPM_NODEIDX_MEMIC_NSU_2,
XPM_NODEIDX_MEMIC_NSU_3,
XPM_NODEIDX_MEMIC_NSU_4,
XPM_NODEIDX_MEMIC_NSU_5,
XPM_NODEIDX_MEMIC_NSU_6,
XPM_NODEIDX_MEMIC_NSU_7,
XPM_NODEIDX_MEMIC_NSU_8,
XPM_NODEIDX_MEMIC_NSU_9,
XPM_NODEIDX_MEMIC_NSU_10,
XPM_NODEIDX_MEMIC_NSU_11,
XPM_NODEIDX_MEMIC_NSU_12,
XPM_NODEIDX_MEMIC_NSU_13,
XPM_NODEIDX_MEMIC_NSU_14,
XPM_NODEIDX_MEMIC_NSU_15,
XPM_NODEIDX_MEMIC_NSU_16,
XPM_NODEIDX_MEMIC_NSU_17,
XPM_NODEIDX_MEMIC_NSU_18,
XPM_NODEIDX_MEMIC_NSU_19,
XPM_NODEIDX_MEMIC_NSU_20,
XPM_NODEIDX_MEMIC_NSU_21,
XPM_NODEIDX_MEMIC_NSU_22,
XPM_NODEIDX_MEMIC_NSU_23,
XPM_NODEIDX_MEMIC_NSU_24,
XPM_NODEIDX_MEMIC_NSU_25,
XPM_NODEIDX_MEMIC_NSU_26,
XPM_NODEIDX_MEMIC_NSU_27,
XPM_NODEIDX_MEMIC_NSU_28,
XPM_NODEIDX_MEMIC_NSU_29,
XPM_NODEIDX_MEMIC_NSU_30,
XPM_NODEIDX_MEMIC_NSU_31,
XPM_NODEIDX_MEMIC_NSU_32,
XPM_NODEIDX_MEMIC_NSU_33,
XPM_NODEIDX_MEMIC_NSU_34,
XPM_NODEIDX_MEMIC_NSU_35,
XPM_NODEIDX_MEMIC_NSU_36,
XPM_NODEIDX_MEMIC_NSU_37,
XPM_NODEIDX_MEMIC_NSU_38,
XPM_NODEIDX_MEMIC_NSU_39,
XPM_NODEIDX_MEMIC_NSU_40,
XPM_NODEIDX_MEMIC_NSU_41,
XPM_NODEIDX_MEMIC_NSU_42,
XPM_NODEIDX_MEMIC_NSU_43,
XPM_NODEIDX_MEMIC_NSU_44,
XPM_NODEIDX_MEMIC_NSU_45,
XPM_NODEIDX_MEMIC_NSU_46,
XPM_NODEIDX_MEMIC_NSU_47,
XPM_NODEIDX_MEMIC_NSU_48,
XPM_NODEIDX_MEMIC_NSU_49,
XPM_NODEIDX_MEMIC_MAX,
} XPm_MemicNodeIndex;
typedef enum {
/* MIO nodes */
XPM_NODEIDX_STMIC_MIN,
XPM_NODEIDX_STMIC_LMIO_0,
XPM_NODEIDX_STMIC_LMIO_1,
XPM_NODEIDX_STMIC_LMIO_2,
XPM_NODEIDX_STMIC_LMIO_3,
XPM_NODEIDX_STMIC_LMIO_4,
XPM_NODEIDX_STMIC_LMIO_5,
XPM_NODEIDX_STMIC_LMIO_6,
XPM_NODEIDX_STMIC_LMIO_7,
XPM_NODEIDX_STMIC_LMIO_8,
XPM_NODEIDX_STMIC_LMIO_9,
XPM_NODEIDX_STMIC_LMIO_10,
XPM_NODEIDX_STMIC_LMIO_11,
XPM_NODEIDX_STMIC_LMIO_12,
XPM_NODEIDX_STMIC_LMIO_13,
XPM_NODEIDX_STMIC_LMIO_14,
XPM_NODEIDX_STMIC_LMIO_15,
XPM_NODEIDX_STMIC_LMIO_16,
XPM_NODEIDX_STMIC_LMIO_17,
XPM_NODEIDX_STMIC_LMIO_18,
XPM_NODEIDX_STMIC_LMIO_19,
XPM_NODEIDX_STMIC_LMIO_20,
XPM_NODEIDX_STMIC_LMIO_21,
XPM_NODEIDX_STMIC_LMIO_22,
XPM_NODEIDX_STMIC_LMIO_23,
XPM_NODEIDX_STMIC_LMIO_24,
XPM_NODEIDX_STMIC_LMIO_25,
XPM_NODEIDX_STMIC_PMIO_0,
XPM_NODEIDX_STMIC_PMIO_1,
XPM_NODEIDX_STMIC_PMIO_2,
XPM_NODEIDX_STMIC_PMIO_3,
XPM_NODEIDX_STMIC_PMIO_4,
XPM_NODEIDX_STMIC_PMIO_5,
XPM_NODEIDX_STMIC_PMIO_6,
XPM_NODEIDX_STMIC_PMIO_7,
XPM_NODEIDX_STMIC_PMIO_8,
XPM_NODEIDX_STMIC_PMIO_9,
XPM_NODEIDX_STMIC_PMIO_10,
XPM_NODEIDX_STMIC_PMIO_11,
XPM_NODEIDX_STMIC_PMIO_12,
XPM_NODEIDX_STMIC_PMIO_13,
XPM_NODEIDX_STMIC_PMIO_14,
XPM_NODEIDX_STMIC_PMIO_15,
XPM_NODEIDX_STMIC_PMIO_16,
XPM_NODEIDX_STMIC_PMIO_17,
XPM_NODEIDX_STMIC_PMIO_18,
XPM_NODEIDX_STMIC_PMIO_19,
XPM_NODEIDX_STMIC_PMIO_20,
XPM_NODEIDX_STMIC_PMIO_21,
XPM_NODEIDX_STMIC_PMIO_22,
XPM_NODEIDX_STMIC_PMIO_23,
XPM_NODEIDX_STMIC_PMIO_24,
XPM_NODEIDX_STMIC_PMIO_25,
XPM_NODEIDX_STMIC_PMIO_26,
XPM_NODEIDX_STMIC_PMIO_27,
XPM_NODEIDX_STMIC_PMIO_28,
XPM_NODEIDX_STMIC_PMIO_29,
XPM_NODEIDX_STMIC_PMIO_30,
XPM_NODEIDX_STMIC_PMIO_31,
XPM_NODEIDX_STMIC_PMIO_32,
XPM_NODEIDX_STMIC_PMIO_33,
XPM_NODEIDX_STMIC_PMIO_34,
XPM_NODEIDX_STMIC_PMIO_35,
XPM_NODEIDX_STMIC_PMIO_36,
XPM_NODEIDX_STMIC_PMIO_37,
XPM_NODEIDX_STMIC_PMIO_38,
XPM_NODEIDX_STMIC_PMIO_39,
XPM_NODEIDX_STMIC_PMIO_40,
XPM_NODEIDX_STMIC_PMIO_41,
XPM_NODEIDX_STMIC_PMIO_42,
XPM_NODEIDX_STMIC_PMIO_43,
XPM_NODEIDX_STMIC_PMIO_44,
XPM_NODEIDX_STMIC_PMIO_45,
XPM_NODEIDX_STMIC_PMIO_46,
XPM_NODEIDX_STMIC_PMIO_47,
XPM_NODEIDX_STMIC_PMIO_48,
XPM_NODEIDX_STMIC_PMIO_49,
XPM_NODEIDX_STMIC_PMIO_50,
XPM_NODEIDX_STMIC_PMIO_51,
XPM_NODEIDX_STMIC_MAX,
} XPm_StmicNodeIndex;
typedef enum {
/* Device nodes */
XPM_NODEIDX_DEV_MIN,
/* Processor devices */
XPM_NODEIDX_DEV_PMC_PROC,
XPM_NODEIDX_DEV_PSM_PROC,
XPM_NODEIDX_DEV_ACPU_0,
XPM_NODEIDX_DEV_ACPU_1,
XPM_NODEIDX_DEV_RPU0_0,
XPM_NODEIDX_DEV_RPU0_1,
/* Memory devices */
XPM_NODEIDX_DEV_OCM_0,
XPM_NODEIDX_DEV_OCM_1,
XPM_NODEIDX_DEV_OCM_2,
XPM_NODEIDX_DEV_OCM_3,
XPM_NODEIDX_DEV_TCM_0_A,
XPM_NODEIDX_DEV_TCM_0_B,
XPM_NODEIDX_DEV_TCM_1_A,
XPM_NODEIDX_DEV_TCM_1_B,
XPM_NODEIDX_DEV_L2_BANK_0,
XPM_NODEIDX_DEV_DDR_0,
XPM_NODEIDX_DEV_DDR_1,
XPM_NODEIDX_DEV_DDR_2,
XPM_NODEIDX_DEV_DDR_3,
XPM_NODEIDX_DEV_DDR_4,
XPM_NODEIDX_DEV_DDR_5,
XPM_NODEIDX_DEV_DDR_6,
XPM_NODEIDX_DEV_DDR_7,
/* LPD Peripheral devices */
XPM_NODEIDX_DEV_USB_0,
XPM_NODEIDX_DEV_GEM_0,
XPM_NODEIDX_DEV_GEM_1,
XPM_NODEIDX_DEV_SPI_0,
XPM_NODEIDX_DEV_SPI_1,
XPM_NODEIDX_DEV_I2C_0,
XPM_NODEIDX_DEV_I2C_1,
XPM_NODEIDX_DEV_CAN_FD_0,
XPM_NODEIDX_DEV_CAN_FD_1,
XPM_NODEIDX_DEV_UART_0,
XPM_NODEIDX_DEV_UART_1,
XPM_NODEIDX_DEV_GPIO,
XPM_NODEIDX_DEV_TTC_0,
XPM_NODEIDX_DEV_TTC_1,
XPM_NODEIDX_DEV_TTC_2,
XPM_NODEIDX_DEV_TTC_3,
XPM_NODEIDX_DEV_SWDT_LPD,
/* FPD Peripheral devices */
XPM_NODEIDX_DEV_SWDT_FPD,
/* PMC Peripheral devices */
XPM_NODEIDX_DEV_OSPI,
XPM_NODEIDX_DEV_QSPI,
XPM_NODEIDX_DEV_GPIO_PMC,
XPM_NODEIDX_DEV_I2C_PMC,
XPM_NODEIDX_DEV_SDIO_0,
XPM_NODEIDX_DEV_SDIO_1,
XPM_NODEIDX_DEV_PL_0,
XPM_NODEIDX_DEV_PL_1,
XPM_NODEIDX_DEV_PL_2,
XPM_NODEIDX_DEV_PL_3,
XPM_NODEIDX_DEV_RTC,
XPM_NODEIDX_DEV_ADMA_0,
XPM_NODEIDX_DEV_ADMA_1,
XPM_NODEIDX_DEV_ADMA_2,
XPM_NODEIDX_DEV_ADMA_3,
XPM_NODEIDX_DEV_ADMA_4,
XPM_NODEIDX_DEV_ADMA_5,
XPM_NODEIDX_DEV_ADMA_6,
XPM_NODEIDX_DEV_ADMA_7,
XPM_NODEIDX_DEV_IPI_0,
XPM_NODEIDX_DEV_IPI_1,
XPM_NODEIDX_DEV_IPI_2,
XPM_NODEIDX_DEV_IPI_3,
XPM_NODEIDX_DEV_IPI_4,
XPM_NODEIDX_DEV_IPI_5,
XPM_NODEIDX_DEV_IPI_6,
/* Entire SoC */
XPM_NODEIDX_DEV_SOC,
/* DDR memory controllers */
XPM_NODEIDX_DEV_DDRMC_0,
XPM_NODEIDX_DEV_DDRMC_1,
XPM_NODEIDX_DEV_DDRMC_2,
XPM_NODEIDX_DEV_DDRMC_3,
/* GT devices */
XPM_NODEIDX_DEV_GT_0,
XPM_NODEIDX_DEV_GT_1,
XPM_NODEIDX_DEV_GT_2,
XPM_NODEIDX_DEV_GT_3,
XPM_NODEIDX_DEV_GT_4,
XPM_NODEIDX_DEV_GT_5,
XPM_NODEIDX_DEV_GT_6,
XPM_NODEIDX_DEV_GT_7,
XPM_NODEIDX_DEV_GT_8,
XPM_NODEIDX_DEV_GT_9,
XPM_NODEIDX_DEV_GT_10,
XPM_NODEIDX_DEV_EFUSE_CACHE,
XPM_NODEIDX_DEV_AMS_ROOT,
/* XRAM devices */
XPM_NODEIDX_DEV_XRAM_0,
XPM_NODEIDX_DEV_XRAM_1,
XPM_NODEIDX_DEV_XRAM_2,
XPM_NODEIDX_DEV_XRAM_3,
XPM_NODEIDX_DEV_XRAM_4,
XPM_NODEIDX_DEV_XRAM_5,
XPM_NODEIDX_DEV_XRAM_6,
XPM_NODEIDX_DEV_XRAM_7,
XPM_NODEIDX_DEV_XRAM_8,
XPM_NODEIDX_DEV_XRAM_9,
XPM_NODEIDX_DEV_XRAM_10,
XPM_NODEIDX_DEV_XRAM_11,
XPM_NODEIDX_DEV_XRAM_12,
XPM_NODEIDX_DEV_XRAM_13,
XPM_NODEIDX_DEV_XRAM_14,
XPM_NODEIDX_DEV_XRAM_15,
/* GTM devices */
XPM_NODEIDX_DEV_GTM_0,
XPM_NODEIDX_DEV_GTM_1,
XPM_NODEIDX_DEV_GTM_2,
XPM_NODEIDX_DEV_GTM_3,
XPM_NODEIDX_DEV_GTM_4,
/* GTYP devices */
XPM_NODEIDX_DEV_GTYP_0,
XPM_NODEIDX_DEV_GTYP_1,
XPM_NODEIDX_DEV_GTYP_2,
XPM_NODEIDX_DEV_GTYP_CPM5_0,
XPM_NODEIDX_DEV_GTYP_CPM5_1,
XPM_NODEIDX_DEV_GTYP_CPM5_2,
XPM_NODEIDX_DEV_GTYP_CPM5_3,
XPM_NODEIDX_DEV_AIE,
XPM_NODEIDX_DEV_IPI_PMC,
XPM_NODEIDX_DEV_MAX
} XPm_DeviceNodeIndex;
typedef enum {
/* PL Device nodes */
XPM_NODEIDX_DEV_PLD_0,
XPM_NODEIDX_DEV_PLD_MAX = 32,
} XPm_PlDeviceNodeIndex;
/**
* Subsystem IDs
*/
typedef enum {
XPM_NODEIDX_SUBSYS_DEFAULT,
XPM_NODEIDX_SUBSYS_PMC,
} XPm_SubsystemId;
/**
* Isolation IDs
*/
typedef enum {
XPM_NODEIDX_ISO_FPD_PL_TEST,
XPM_NODEIDX_ISO_FPD_PL,
XPM_NODEIDX_ISO_FPD_SOC,
XPM_NODEIDX_ISO_LPD_CPM_DFX,
XPM_NODEIDX_ISO_LPD_CPM,
XPM_NODEIDX_ISO_LPD_PL_TEST,
XPM_NODEIDX_ISO_LPD_PL,
XPM_NODEIDX_ISO_LPD_SOC,
XPM_NODEIDX_ISO_PMC_LPD_DFX,
XPM_NODEIDX_ISO_PMC_LPD,
XPM_NODEIDX_ISO_PMC_PL_CFRAME,
XPM_NODEIDX_ISO_PMC_PL_TEST,
XPM_NODEIDX_ISO_PMC_PL,
XPM_NODEIDX_ISO_PMC_SOC_NPI,
XPM_NODEIDX_ISO_PMC_SOC,
XPM_NODEIDX_ISO_PL_SOC,
XPM_NODEIDX_ISO_VCCAUX_SOC,
XPM_NODEIDX_ISO_VCCRAM_SOC,
XPM_NODEIDX_ISO_VCCAUX_VCCRAM,
XPM_NODEIDX_ISO_PL_CPM_PCIEA0_ATTR,
XPM_NODEIDX_ISO_PL_CPM_PCIEA1_ATTR,
XPM_NODEIDX_ISO_PL_CPM_RST_CPI0,
XPM_NODEIDX_ISO_PL_CPM_RST_CPI1,
XPM_NODEIDX_ISO_GEM_TSU_CLK,
XPM_NODEIDX_ISO_GEM0_TXRX_CLK,
XPM_NODEIDX_ISO_GEM1_TXRX_CLK,
XPM_NODEIDX_ISO_CPM5_PL,
XPM_NODEIDX_ISO_CPM5_PL_AXIMM,
XPM_NODEIDX_ISO_CPM5_PL_CHI0,
XPM_NODEIDX_ISO_CPM5_PL_CHI1,
XPM_NODEIDX_ISO_CPM5_PL_TST,
XPM_NODEIDX_ISO_CPM5_PL_PCIEA0_MPIO,
XPM_NODEIDX_ISO_CPM5_PL_PCIEA1_MPIO,
XPM_NODEIDX_ISO_CPM5_RAM,
/* Remove below ones later if they don't need special handling and
same as LPD_CPM and LPD_CPM_DFX */
XPM_NODEIDX_ISO_LPD_CPM5,
XPM_NODEIDX_ISO_LPD_CPM5_DFX,
XPM_NODEIDX_ISO_XRAM_PL_AXI0,
XPM_NODEIDX_ISO_XRAM_PL_AXI1,
XPM_NODEIDX_ISO_XRAM_PL_AXI2,
XPM_NODEIDX_ISO_XRAM_PL_AXILITE,
XPM_NODEIDX_ISO_XRAM_PL_FABRIC,
XPM_NODEIDX_ISO_MAX,
} XPm_IsolationId;
/**
* Protection IDs
*/
typedef enum {
XPM_NODEIDX_PROT_MIN,
XPM_NODEIDX_PROT_XPPU_LPD,
XPM_NODEIDX_PROT_XPPU_PMC,
XPM_NODEIDX_PROT_XPPU_PMC_NPI,
XPM_NODEIDX_PROT_XMPU_FPD_SLAVES,
XPM_NODEIDX_PROT_XMPU_OCM,
XPM_NODEIDX_PROT_XMPU_PMC,
XPM_NODEIDX_PROT_XMPU_XRAM_0,
XPM_NODEIDX_PROT_XMPU_XRAM_1,
XPM_NODEIDX_PROT_XMPU_XRAM_2,
XPM_NODEIDX_PROT_XMPU_XRAM_3,
XPM_NODEIDX_PROT_MAX,
} XPm_ProtectionId;
/**
* Monitor node Ids
*/
typedef enum {
XPM_NODEIDX_MONITOR_MIN,
XPM_NODEIDX_MONITOR_SYSMON_PMC_0,
XPM_NODEIDX_MONITOR_SYSMON_PMC_1,
XPM_NODEIDX_MONITOR_SYSMON_PS_LPD,
XPM_NODEIDX_MONITOR_SYSMON_PS_FPD,
XPM_NODEIDX_MONITOR_SYSMON_NPD_MIN,
XPM_NODEIDX_MONITOR_SYSMON_NPD_0 = XPM_NODEIDX_MONITOR_SYSMON_NPD_MIN,
XPM_NODEIDX_MONITOR_SYSMON_NPD_1,
XPM_NODEIDX_MONITOR_SYSMON_NPD_2,
XPM_NODEIDX_MONITOR_SYSMON_NPD_3,
XPM_NODEIDX_MONITOR_SYSMON_NPD_4,
XPM_NODEIDX_MONITOR_SYSMON_NPD_5,
XPM_NODEIDX_MONITOR_SYSMON_NPD_6,
XPM_NODEIDX_MONITOR_SYSMON_NPD_7,
XPM_NODEIDX_MONITOR_SYSMON_NPD_8,
XPM_NODEIDX_MONITOR_SYSMON_NPD_9,
XPM_NODEIDX_MONITOR_SYSMON_NPD_10,
XPM_NODEIDX_MONITOR_SYSMON_NPD_11,
XPM_NODEIDX_MONITOR_SYSMON_NPD_12,
XPM_NODEIDX_MONITOR_SYSMON_NPD_13,
XPM_NODEIDX_MONITOR_SYSMON_NPD_14,
XPM_NODEIDX_MONITOR_SYSMON_NPD_15,
XPM_NODEIDX_MONITOR_SYSMON_NPD_16,
XPM_NODEIDX_MONITOR_SYSMON_NPD_17,
XPM_NODEIDX_MONITOR_SYSMON_NPD_18,
XPM_NODEIDX_MONITOR_SYSMON_NPD_19,
XPM_NODEIDX_MONITOR_SYSMON_NPD_20,
XPM_NODEIDX_MONITOR_SYSMON_NPD_21,
XPM_NODEIDX_MONITOR_SYSMON_NPD_22,
XPM_NODEIDX_MONITOR_SYSMON_NPD_23,
XPM_NODEIDX_MONITOR_SYSMON_NPD_24,
XPM_NODEIDX_MONITOR_SYSMON_NPD_25,
XPM_NODEIDX_MONITOR_SYSMON_NPD_26,
XPM_NODEIDX_MONITOR_SYSMON_NPD_27,
XPM_NODEIDX_MONITOR_SYSMON_NPD_28,
XPM_NODEIDX_MONITOR_SYSMON_NPD_29,
XPM_NODEIDX_MONITOR_SYSMON_NPD_30,
XPM_NODEIDX_MONITOR_SYSMON_NPD_31,
XPM_NODEIDX_MONITOR_SYSMON_NPD_32,
XPM_NODEIDX_MONITOR_SYSMON_NPD_33,
XPM_NODEIDX_MONITOR_SYSMON_NPD_34,
XPM_NODEIDX_MONITOR_SYSMON_NPD_35,
XPM_NODEIDX_MONITOR_SYSMON_NPD_36,
XPM_NODEIDX_MONITOR_SYSMON_NPD_37,
XPM_NODEIDX_MONITOR_SYSMON_NPD_38,
XPM_NODEIDX_MONITOR_SYSMON_NPD_39,
XPM_NODEIDX_MONITOR_SYSMON_NPD_40,
XPM_NODEIDX_MONITOR_SYSMON_NPD_41,
XPM_NODEIDX_MONITOR_SYSMON_NPD_42,
XPM_NODEIDX_MONITOR_SYSMON_NPD_43,
XPM_NODEIDX_MONITOR_SYSMON_NPD_44,
XPM_NODEIDX_MONITOR_SYSMON_NPD_45,
XPM_NODEIDX_MONITOR_SYSMON_NPD_46,
XPM_NODEIDX_MONITOR_SYSMON_NPD_47,
XPM_NODEIDX_MONITOR_SYSMON_NPD_48,
XPM_NODEIDX_MONITOR_SYSMON_NPD_49,
XPM_NODEIDX_MONITOR_SYSMON_NPD_50,
XPM_NODEIDX_MONITOR_SYSMON_NPD_51,
XPM_NODEIDX_MONITOR_SYSMON_NPD_52,
XPM_NODEIDX_MONITOR_SYSMON_NPD_53,
XPM_NODEIDX_MONITOR_SYSMON_NPD_54,
XPM_NODEIDX_MONITOR_SYSMON_NPD_55,
XPM_NODEIDX_MONITOR_SYSMON_NPD_56,
XPM_NODEIDX_MONITOR_SYSMON_NPD_57,
XPM_NODEIDX_MONITOR_SYSMON_NPD_58,
XPM_NODEIDX_MONITOR_SYSMON_NPD_59,
XPM_NODEIDX_MONITOR_SYSMON_NPD_MAX,
XPM_NODEIDX_MONITOR_MAX,
} XPm_MonitorId;
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_NODE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_xpu.c
/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_default.h"
#include "xpfw_xpu.h"
/* XMPU/XPPU configiguration register addresses */
#define XMPU_DDR_0_BASE_ADDR 0xFD000000U
#define XMPU_DDR_1_BASE_ADDR 0xFD010000U
#define XMPU_DDR_2_BASE_ADDR 0xFD020000U
#define XMPU_DDR_3_BASE_ADDR 0xFD030000U
#define XMPU_DDR_4_BASE_ADDR 0xFD040000U
#define XMPU_DDR_5_BASE_ADDR 0xFD050000U
#define XMPU_FPD_BASE_ADDR 0xFD5D0000U
#define XMPU_OCM_BASE_ADDR 0xFFA70000U
#define XPPU_BASE_ADDR 0xFF980000U
#define XPPU_POISON_OFFSET_ADDR 0xFF9CFF00U
/* XPU status register offsets */
#define XPU_ISR_OFFSET 0x10U
#define XPU_IER_OFFSET 0x18U
#define XPU_ERR_STATUS_1_OFFSET 0x04U
#define XPU_ERR_STATUS_2_OFFSET 0x08U
#define XPU_POISON_OFFSET 0x0CU
/* XMPU error IDs to identify each error */
#define XMPU_REG_ACC_ERR_ON_APB 0x1U
#define XMPU_READ_PERMISSION_VIOLATION 0x2U
#define XMPU_WRITE_PERMISSION_VIOLATION 0x4U
#define XMPU_SECURITY_VIOLATION_ERR 0x8U
/* XPPU error IDs to identify each error */
#define XPPU_REG_ACC_ERR_ON_APB 0x1U
#define XPPU_MID_NOT_FOUND 0x2U
#define XPPU_MWRITE_PERMISSON_VIOLATION 0x4U
#define XPPU_MID_PARITY_ERROR 0x8U
#define XPPU_MID_ACCESS_VIOLATION 0x20U
#define XPPU_TRUSTZONE_VIOLATION 0x40U
#define XPPU_APPER_PARITY_ERROR 0x80U
#ifdef XPU_INTR_DEBUG_PRINT_ENABLE
struct XpuMasterID {
u32 MasterID;
u32 MasterIDLimit;
char MasterName[11];
};
/* XPU master ID LUT to identify master which caused the violation */
static struct XpuMasterID XpuMasterIDLUT[] =
{
{ 0x00U, 0x0FU, "RPU0" },
{ 0x10U, 0x1FU, "RPU1" },
{ 0x40U, 0x40U, "PMU MB" },
{ 0x50U, 0x50U, "CSU MB" },
{ 0x51U, 0x51U, "CSU DMA" },
{ 0x60U, 0x60U, "USB0" },
{ 0x61U, 0x61U, "USB1" },
{ 0x62U, 0x62U, "DAP" },
{ 0x68U, 0x6FU, "ADMA" },
{ 0x70U, 0x70U, "SD0" },
{ 0x71U, 0x71U, "SD1" },
{ 0x72U, 0x72U, "NAND" },
{ 0x73U, 0x73U, "QSPI" },
{ 0x74U, 0x74U, "GEM0" },
{ 0x75U, 0x75U, "GEM1" },
{ 0x76U, 0x76U, "GEM2" },
{ 0x77U, 0x77U, "GEM3" },
{ 0x80U, 0xBFU, "APU" },
{ 0xC0U, 0xC3U, "SATA" },
{ 0xC4U, 0xC4U, "GPU" },
{ 0xC5U, 0xC5U, "CoreSight" },
{ 0xD0U, 0xD0U, "PCIe" },
{ 0xE0U, 0xE7U, "DPDMA" },
{ 0xE8U, 0xEFU, "GDMA" },
{ 0x200U, 0x23FU, "AFI FM0" },
{ 0x240U, 0x27FU, "AFI FM1" },
{ 0x280U, 0x2BFU, "AFI FM2" },
{ 0x2C0U, 0x2FFU, "AFI FM3" },
{ 0x300U, 0x33FU, "AFI FM4" },
{ 0x340U, 0x37FU, "AFI FM5" },
{ 0x380U, 0x3BFU, "AFI FM LPD" },
};
#endif
struct XpuReg {
u32 BaseAddress;
u32 MaskAll;
char CfgName[5];
};
static struct XpuReg XpuRegList[] =
{
{
.BaseAddress = XMPU_DDR_0_BASE_ADDR,
.MaskAll = (u32)0xFU,
.CfgName = "DDR0",
},
{
.BaseAddress = XMPU_DDR_1_BASE_ADDR,
.MaskAll = (u32)0xFU,
.CfgName = "DDR1",
},
{
.BaseAddress = XMPU_DDR_2_BASE_ADDR,
.MaskAll = (u32)0xFU,
.CfgName = "DDR2",
},
{
.BaseAddress = XMPU_DDR_3_BASE_ADDR,
.MaskAll = (u32)0xFU,
.CfgName = "DDR3",
},
{
.BaseAddress = XMPU_DDR_4_BASE_ADDR,
.MaskAll = (u32)0xFU,
.CfgName = "DDR4",
},
{
.BaseAddress = XMPU_DDR_5_BASE_ADDR,
.MaskAll = (u32)0xFU,
.CfgName = "DDR5",
},
{
.BaseAddress = XMPU_FPD_BASE_ADDR,
.MaskAll = (u32)0xFU,
.CfgName = "FPD",
},
{
.BaseAddress = XMPU_OCM_BASE_ADDR,
.MaskAll = (u32)0xFU,
.CfgName = "OCM",
},
{
.BaseAddress = XPPU_BASE_ADDR,
.MaskAll = (u32)0xEFU,
.CfgName = "XPPU",
},
};
/**
* Enable interrupts for all XMPU/XPPU Instances
*/
void XPfw_XpuIntrInit(void)
{
u32 Idx;
XPfw_Printf(DEBUG_DETAILED,"EM: Enabling XMPU/XPPU interrupts\r\n");
for(Idx = 0U; Idx < ARRAYSIZE(XpuRegList);Idx++) {
/* Enable all the Interrupts for this XMPU/XPPU Instance */
XPfw_Write32(XpuRegList[Idx].BaseAddress + XPU_IER_OFFSET,
XpuRegList[Idx].MaskAll);
}
}
/**
* Ack interrupts for all XMPU/XPPU Instances so that any new
* interrupts occurring later can trigger an Error interrupt to PMU
*/
void XPfw_XpuIntrAck(void)
{
u32 Idx;
u32 XpuIntSts = 0U;
#ifdef XPU_INTR_DEBUG_PRINT_ENABLE
u32 Addr = 0U;
u32 MasterID = 0U;
u32 PoisonReg = 0U;
u32 Offset = 0U;
u32 MasterIdx;
#endif
for (Idx = 0U; (Idx < ARRAYSIZE(XpuRegList)) && (XpuIntSts == 0U); Idx++) {
XpuIntSts = XPfw_Read32(XpuRegList[Idx].BaseAddress + XPU_ISR_OFFSET);
#ifdef XPU_INTR_DEBUG_PRINT_ENABLE
Addr = XPfw_Read32(XpuRegList[Idx].BaseAddress + XPU_ERR_STATUS_1_OFFSET);
MasterID = XPfw_Read32(XpuRegList[Idx].BaseAddress + XPU_ERR_STATUS_2_OFFSET);
PoisonReg = XPfw_Read32(XpuRegList[Idx].BaseAddress + XPU_POISON_OFFSET);
if ((Idx < (ARRAYSIZE(XpuRegList) - 1U)) && (XpuIntSts != 0U)) {
switch (XpuIntSts) {
case XMPU_REG_ACC_ERR_ON_APB:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XMPU %s Register Access "
"Error on APB\r\n", XpuRegList[Idx].CfgName);
}
break;
case XMPU_READ_PERMISSION_VIOLATION:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XMPU %s Read permission "
"violation occurred\r\n", XpuRegList[Idx].CfgName);
}
break;
case XMPU_WRITE_PERMISSION_VIOLATION:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XMPU %s Write permission "
"violation occurred\r\n", XpuRegList[Idx].CfgName);
}
break;
case XMPU_SECURITY_VIOLATION_ERR:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XMPU %s Security violation"
" occurred\r\n", XpuRegList[Idx].CfgName);
}
break;
default:
/* Empty default case */
break;
}
XPfw_Printf(DEBUG_DETAILED,"EM: Address of poisoned operation: "
"0x%x%s\r\n",Addr,"XXX");
for(MasterIdx = 0U; MasterIdx < ARRAYSIZE(XpuMasterIDLUT);
++MasterIdx) {
if ((MasterID >= XpuMasterIDLUT[MasterIdx].MasterID) &&
(MasterID <= XpuMasterIDLUT[MasterIdx].MasterIDLimit)) {
XPfw_Printf(DEBUG_DETAILED,"EM: Master Device of poisoned "
"operation: %s\r\n",
XpuMasterIDLUT[MasterIdx].MasterName);
break;
}
}
XPfw_Printf(DEBUG_DETAILED,"EM: Poison register: 0x%x\r\n",
PoisonReg);
} else if ((Idx == (ARRAYSIZE(XpuRegList) - 1U)) && (XpuIntSts != 0U)) {
Offset = XPfw_Read32(XPPU_POISON_OFFSET_ADDR);
switch (XpuIntSts) {
case XPPU_REG_ACC_ERR_ON_APB:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XPPU Register access error"
" on APB. A register access was requested to an "
"unimplemented register location\r\n");
}
break;
case XPPU_MID_NOT_FOUND:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XPPU Master ID "
"not found\r\n");
}
break;
case XPPU_MWRITE_PERMISSON_VIOLATION:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XPPU Read permission "
"violation. Master attempted a write, but the master "
"has read-only permission\r\n");
}
break;
case XPPU_MID_PARITY_ERROR:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XPPU Master ID parity "
"error\r\n");
}
break;
case XPPU_MID_ACCESS_VIOLATION:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XPPU Master ID access "
"violation\r\n");
}
break;
case XPPU_TRUSTZONE_VIOLATION:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XPPU TrustZone Violation. "
"A non-secure master attempted to access a secure "
"memory location\r\n");
}
break;
case XPPU_APPER_PARITY_ERROR:
{
XPfw_Printf(DEBUG_DETAILED,"EM: XPPU Aperture parity "
"Error\r\n");
}
break;
default:
/* Empty default case */
break;
}
Addr = (Addr << 12) | Offset;
XPfw_Printf(DEBUG_DETAILED,"EM: Address of poisoned operation: "
"0x%x\r\n",Addr);
for(MasterIdx = 0U; MasterIdx < ARRAYSIZE(XpuMasterIDLUT);
++MasterIdx) {
if ((MasterID >= XpuMasterIDLUT[MasterIdx].MasterID) &&
(MasterID <= XpuMasterIDLUT[MasterIdx].MasterIDLimit)) {
XPfw_Printf(DEBUG_DETAILED,"EM: Master Device of poisoned "
"operation: %s\r\n",
XpuMasterIDLUT[MasterIdx].MasterName);
break;
}
}
XPfw_Printf(DEBUG_DETAILED,"EM: Poison register : 0x%x\r\n",
PoisonReg);
} else {
/* For MISRA C compliance */
}
#endif
/* Ack the Interrupts */
XPfw_Write32(XpuRegList[Idx].BaseAddress + XPU_ISR_OFFSET,
XpuRegList[Idx].MaskAll);
}
}
/**
* A placeholder for handling XPPU/XMPU errors
* This routine is called when ever a XMPU/XPPU error occurs
* It prints a message if debug is enabled and Acks the errors
*
* @param ErrorId is the error identifier passed by Error Manager
*/
void XPfw_XpuIntrHandler(u8 ErrorId)
{
XPfw_Printf(DEBUG_DETAILED,
"============================================================\r\n");
XPfw_Printf(DEBUG_DETAILED,"EM: XMPU/XPPU violation occurred "
"(ErrorId: %d)\r\n", ErrorId);
XPfw_XpuIntrAck();
XPfw_Printf(DEBUG_DETAILED,
"============================================================\r\n");
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/xilskey_v6_9/src/xilskey_utils.c
/******************************************************************************
* Copyright (c) 2013 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xilskey_utils.c
*
*
* @note None.
*
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- --------------------------------------------------------
* 1.00a rpoolla 04/26/13 First release
* 2.00 hk 22/01/14 Corrected PL voltage checks to VCCINT and VCCAUX.
* CR#768077
* 2.1 kvn 04/01/15 Fixed warnings. CR#716453.
* 3.00 vns 31/07/15 Added efuse functionality for Ultrascale.
* 4.0 vns 10/01/15 Modified conditional compilation
* to support ZynqMp platform also.
* Added new API Xsk_Ceil
* Modified Xilskey_CrcCalculation() API for providing
* support for efuse ZynqMp also.
* 6.0 vns 07/07/16 Modified XilSKey_Timer_Intialise API to initialize
* TimerTicks to 10us. As Hardware module only takes
* care of programming time(5us), through software we
* only need to control hardware module.
* Modified sysmon read to 16 bit resolution as
* sysmon driver has modified conversion formulae
* to 16 bit resolution.
* vns 07/18/16 Initialized sysmonpsu driver and added
* XilSKey_ZynqMP_EfusePs_ReadSysmonVol and
* XilSKey_ZynqMP_EfusePs_ReadSysmonTemp functions
* 6.6 vns 06/06/18 Added doxygen tags
* 6.7 arc 01/05/19 Fixed MISRA-C violations.
* vns 02/09/19 Fixed buffer overflow access in
* XilSKey_Efuse_ConvertStringToHexLE()
* arc 25/02/19 Added asserts for pointer parameter for NULL
* verification
* Fixed Length parameter as length in bits for
* XilSKey_Efuse_ConvertStringToHexBE and added length
* validations
* arc 03/13/19 Added assert to validate lengths in
* XilSKey_Efuse_ValidateKey()
* arc 03/15/19 Modified initial default status value as XST_FAILURE
* 6.7 psl 03/21/19 Fixed MISRA-C violation.
* vns 03/23/19 Fixed CRC calculation for Ultra plus
* arc 04/04/19 Fixed CPP warnings.
* 6.8 psl 06/07/19 Added doxygen tags.
* psl 06/25/19 Fixed Coverity warnings.
* psl 06/28/19 Added doxygen tags.
* psl 07/29/19 Fixed MISRA-C violation.
* vns 08/29/19 Initialized Status variables
* mmd 07/31/19 Avoided reconfiguration of sysmon, if it is in use
* 6.9 kpt 02/16/20 Fixed coverity warnings
* 02/27/20 Replaced XSYSMON_DEVICE_ID with XSYSMON_PSU_DEVICE_ID
* vns 03/18/20 Fixed Armcc compilation errors
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xil_io.h"
#include "xil_types.h"
#include "xilskey_utils.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
#ifdef XSK_ZYNQ_PLATFORM
static XAdcPs XAdcInst; /**< XADC driver instance */
u16 XAdcDevId; /**< XADC Device ID */
#endif
#ifdef XSK_MICROBLAZE_PLATFORM
XTmrCtr XTmrCtrInst;
#endif
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
static XSysMonPsu XSysmonInst; /* Sysmon PSU instance */
static u16 XSysmonDevId; /* Sysmon PSU device ID */
#endif
u32 TimerTicksfor100ns; /**< Global Variable to store ticks/100ns*/
u32 TimerTicksfor1000ns; /**< Global Variable for 10 micro secs for microblaze */
/************************** Function Prototypes *****************************/
static u32 XilSKey_EfusePs_ConvertCharToNibble (char InChar, u8 *Num);
#ifdef XSK_MICROBLAZE_PLATFORM
extern void Jtag_Read_Sysmon(u8 Row, u32 *Row_Data);
#endif
u32 XilSKey_RowCrcCalculation(u32 PrevCRC, u32 Data, u32 Addr);
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
static INLINE void XilSKey_ZynqMP_EfusePs_ReadSysmonVol(
XSKEfusePs_XAdc *XAdcInstancePtr);
static INLINE void XilSKey_ZynqMP_EfusePs_ReadSysmonTemp(
XSKEfusePs_XAdc *XAdcInstancePtr);
#ifndef XSK_OVERRIDE_SYSMON_CFG
static u32 XilSKey_Is_Valid_SysMon_Cfg(XSysMonPsu *InstancePtr);
#endif
#endif
/***************************************************************************/
/**
* This function is used to initialize the XADC driver
*
* @return
* - XST_SUCCESS in case of no errors.
* - XSK_EFUSEPS_ERROR_XADC_CONFIG Error occurred with XADC config.
* - XSK_EFUSEPS_ERROR_XADC_INITIALIZE Error occurred while XADC initialization
* - XSK_EFUSEPS_ERROR_XADC_SELF_TEST Error occurred in XADC self test.
*
* TDD Cases:
*
****************************************************************************/
u32 XilSKey_EfusePs_XAdcInit (void)
{
u32 Status = (u32)XST_FAILURE;
#if defined(XSK_ZYNQ_PLATFORM)
XAdcPs_Config *ConfigPtr;
XAdcPs *XAdcInstPtr = &XAdcInst;
/**
* specify the Device ID that is
* generated in xparameters.h
*/
XAdcDevId = XADC_DEVICE_ID;
/**
* Initialize the XAdc driver.
*/
ConfigPtr = XAdcPs_LookupConfig(XAdcDevId);
if (NULL == ConfigPtr) {
Status = (u32)XSK_EFUSEPS_ERROR_XADC_CONFIG;
goto END;
}
Status = (u32)XAdcPs_CfgInitialize(XAdcInstPtr, ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)XSK_EFUSEPS_ERROR_XADC_INITIALIZE;
goto END;
}
/**
* Self Test the XADC/ADC device
*/
Status = (u32)XAdcPs_SelfTest(XAdcInstPtr);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)XSK_EFUSEPS_ERROR_XADC_SELF_TEST;
goto END;
}
/**
* Disable the Channel Sequencer before configuring the Sequence
* registers.
*/
XAdcPs_SetSequencerMode(XAdcInstPtr, XADCPS_SEQ_MODE_SAFE);
Status = (u32)XST_SUCCESS;
#elif defined(XSK_ZYNQ_ULTRA_MP_PLATFORM)
XSysMonPsu_Config *ConfigPtr;
XSysMonPsu *XSysmonInstPtr = &XSysmonInst;
/**
* specify the Device ID that is
* generated in xparameters.h
*/
XSysmonDevId = (u16)XSYSMON_PSU_DEVICE_ID;
/**
* Initialize the XAdc driver.
*/
ConfigPtr = XSysMonPsu_LookupConfig(XSysmonDevId);
if (NULL == ConfigPtr) {
Status = (u32)XSK_EFUSEPS_ERROR_XADC_CONFIG;
goto END;
}
Status = (u32)XSysMonPsu_CfgInitialize(XSysmonInstPtr, ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)XSK_EFUSEPS_ERROR_XADC_INITIALIZE;
goto END;
}
/**
* Self Test for sysmon device
*/
Status = (u32)XSysMonPsu_SelfTest(XSysmonInstPtr);
if (Status != (u32)XST_SUCCESS) {
Status = (u32)XSK_EFUSEPS_ERROR_XADC_SELF_TEST;
goto END;
}
/**
* Disable the Channel Sequencer before configuring the Sequence
* registers.
*/
XSysMonPsu_SetSequencerMode(XSysmonInstPtr,
XSM_SEQ_MODE_SAFE, XSYSMON_PS);
Status = (u32)XST_SUCCESS;
#else
goto END;
#endif
END:
return Status;
}
/***************************************************************************/
/**
* This function reads current value of the temperature from sysmon.
*
* @param XAdcInstancePtr Pointer to the XSKEfusePs_XAdc.
*
* @return None
*
* @note Read temperature will be stored in XSKEfusePS_XAdc pointer's
* temperature
*
****************************************************************************/
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
static INLINE void XilSKey_ZynqMP_EfusePs_ReadSysmonTemp(
XSKEfusePs_XAdc *XAdcInstancePtr)
{
XSysMonPsu *XSysmonInstPtr = &XSysmonInst;
if (NULL == XAdcInstancePtr) {
goto END;
}
/**
* Read the on-chip Temperature Data (Current)
* from the Sysmon PSU data registers.
*/
XAdcInstancePtr->Temp = (u32)XSysMonPsu_GetAdcData(XSysmonInstPtr,
XSM_CH_TEMP, XSYSMON_PS);
xeFUSE_printf(XSK_EFUSE_DEBUG_GENERAL,
"Read Temperature Value: %0x -> %d in Centigrades \n",
XAdcInstancePtr->Temp,
(int )XSysMonPsu_RawToTemperature_OnChip((float)XAdcInstancePtr->Temp));
END:
return;
}
/***************************************************************************/
/**
* This function reads current value of the specified voltage from sysmon.
*
* @param XAdcInstancePtr Pointer to the XSKEfusePs_XAdc.
* Voltage typ should be specified in XAdcInstancePtr's
* structure member VType.
* XSK_EFUSEPS_VPAUX - Reads PS VCC Auxiliary voltage
* XSK_EFUSEPS_VPINT - Reads VCC INT LP voltage
*
* @return None
*
* @note Read voltage will be stored in XSKEfusePS_XAdc pointer's
* voltage
*
****************************************************************************/
static INLINE void XilSKey_ZynqMP_EfusePs_ReadSysmonVol(
XSKEfusePs_XAdc *XAdcInstancePtr)
{
XSysMonPsu *XSysmonInstPtr = &XSysmonInst;
u8 V;
if (NULL == XAdcInstancePtr) {
goto END;
}
/**
* Read the VccPint/PAUX Voltage Data (Current/Maximum/Minimum) from
* Sysmon data registers.
*/
switch (XAdcInstancePtr->VType)
{
case XSK_EFUSEPS_VPAUX:
V = XSM_CH_SUPPLY3;
break;
case XSK_EFUSEPS_VPINT:
default:
V = XSM_CH_SUPPLY1;
break;
}
XAdcInstancePtr->V = (u32)XSysMonPsu_GetAdcData(XSysmonInstPtr, V,
XSYSMON_PS);
xeFUSE_printf(XSK_EFUSE_DEBUG_GENERAL,
"Read Voltage Value: %0x -> %d in Volts \n",
XAdcInstancePtr->V,
(int )XSysMonPsu_RawToVoltage((float)XAdcInstancePtr->V));
END:
return;
}
#endif
/***************************************************************************/
/**
* This function is used to copy the min, max and current value of the
* temperature and voltage which are read from XADC.
*
* @param XAdcInstancePtr Pointer to the XSKEfusePs_XAdc. User has to
* fill the VType to specify the type of voltage. Valid values
* for VType are
* - XSK_EFUSEPS_VPINT
* - XSK_EFUSEPS_VPDRO
* - XSK_EFUSEPS_VPAUX
* - XSK_EFUSEPS_VINT
* - XSK_EFUSEPS_VAUX
*
* @return none
*
* TDD Cases:
*
****************************************************************************/
void XilSKey_EfusePs_XAdcReadTemperatureAndVoltage(XSKEfusePs_XAdc *XAdcInstancePtr)
{
#ifdef XSK_ZYNQ_PLATFORM
XAdcPs *XAdcInstPtr = &XAdcInst;
u8 V, VMin, VMax;
#endif
if (NULL == XAdcInstancePtr) {
goto END;
}
#ifdef XSK_MICROBLAZE_PLATFORM
/* Temperature */
Jtag_Read_Sysmon(XSK_SYSMON_TEMP_ROW, &(XAdcInstancePtr->Temp));
/* Voltage */
Jtag_Read_Sysmon(XSK_SYSMON_VOL_ROW, &(XAdcInstancePtr->V));
#endif
#ifdef XSK_ZYNQ_PLATFORM
/**
* Read the on-chip Temperature Data (Current/Maximum/Minimum)
* from the ADC data registers.
*/
XAdcInstancePtr->Temp = XAdcPs_GetAdcData(XAdcInstPtr, XADCPS_CH_TEMP);
XAdcInstancePtr->TempMin =
XAdcPs_GetMinMaxMeasurement(XAdcInstPtr, XADCPS_MIN_TEMP);
XAdcInstancePtr->TempMax =
XAdcPs_GetMinMaxMeasurement(XAdcInstPtr, XADCPS_MAX_TEMP);
xeFUSE_printf(XSK_EFUSE_DEBUG_GENERAL,
"Read Temperature Value: %0x -> %d in Centigrades \n",
XAdcInstancePtr->Temp,
(int )XAdcPs_RawToTemperature(XAdcInstancePtr->Temp));
/**
* Read the VccPint Voltage Data (Current/Maximum/Minimum) from the
* ADC data registers.
*/
switch (XAdcInstancePtr->VType)
{
case XSK_EFUSEPS_VINT:
V = XADCPS_CH_VCCINT;
VMax = XADCPS_MAX_VCCINT;
VMin = XADCPS_MIN_VCCINT;
break;
case XSK_EFUSEPS_VAUX:
V = XADCPS_CH_VCCAUX;
VMax = XADCPS_MAX_VCCAUX;
VMin = XADCPS_MIN_VCCAUX;
break;
case XSK_EFUSEPS_VPAUX:
V = XADCPS_CH_VCCPAUX;
VMax = XADCPS_MAX_VCCPAUX;
VMin = XADCPS_MIN_VCCPAUX;
break;
case XSK_EFUSEPS_VPDRO:
V = XADCPS_CH_VCCPDRO;
VMax = XADCPS_MAX_VCCPDRO;
VMin = XADCPS_MIN_VCCPDRO;
break;
case XSK_EFUSEPS_VPINT:
default:
V = XADCPS_CH_VCCPINT;
VMax = XADCPS_MAX_VCCPINT;
VMin = XADCPS_MIN_VCCPINT;
break;
}
XAdcInstancePtr->V = XAdcPs_GetAdcData(XAdcInstPtr, V);
XAdcInstancePtr->VMin = XAdcPs_GetMinMaxMeasurement(XAdcInstPtr, VMin);
XAdcInstancePtr->VMax = XAdcPs_GetMinMaxMeasurement(XAdcInstPtr, VMax);
xeFUSE_printf(XSK_EFUSE_DEBUG_GENERAL,
"Read Voltage Value: %0x -> %d in Volts \n",
XAdcInstancePtr->V,
(int )XAdcPs_RawToVoltage(XAdcInstancePtr->V));
#endif
END:
return;
}
/***************************************************************************/
/**
* This function checks temperature and voltage ranges of ZynqMP to access
* PS eFUSE
*
* @param None
* @return
* Error code: On failure
* XST_SUCCESS on Success
*
* @note This function returns XST_SUCCESS if we try to access eFUSE
* on the Remus, as Sysmon access is not permitted on Remus.
*
****************************************************************************/
u32 XilSKey_ZynqMp_EfusePs_Temp_Vol_Checks(void)
{
u32 Status = (u32)XST_FAILURE;
/**
* Check the temperature and voltage(VCC_AUX and VCC_PINT_LP)
*/
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
XSKEfusePs_XAdc XAdcInstance = {0U};
XilSKey_ZynqMP_EfusePs_ReadSysmonTemp(&XAdcInstance);
if ((XAdcInstance.Temp < (u32)XSK_EFUSEPS_TEMP_MIN_RAW) ||
((XAdcInstance.Temp > (u32)XSK_EFUSEPS_TEMP_MAX_RAW))) {
Status = (u32)XSK_EFUSEPS_ERROR_READ_TMEPERATURE_OUT_OF_RANGE;
goto END;
}
XAdcInstance.VType = XSK_EFUSEPS_VPAUX;
XilSKey_ZynqMP_EfusePs_ReadSysmonVol(&XAdcInstance);
if ((XAdcInstance.V < (u32)XSK_EFUSEPS_VPAUX_MIN_RAW) ||
((XAdcInstance.V > (u32)XSK_EFUSEPS_VPAUX_MAX_RAW))) {
Status = (u32)XSK_EFUSEPS_ERROR_READ_VCCPAUX_VOLTAGE_OUT_OF_RANGE;
goto END;
}
XAdcInstance.VType = XSK_EFUSEPS_VPINT;
XilSKey_ZynqMP_EfusePs_ReadSysmonVol(&XAdcInstance);
if ((XAdcInstance.V < (u32)XSK_EFUSEPS_VCC_PSINTLP_MIN_RAW) ||
((XAdcInstance.V > (u32)XSK_EFUSEPS_VCC_PSINTLP_MAX_RAW))) {
Status = (u32)XSK_EFUSEPS_ERROR_READ_VCCPAUX_VOLTAGE_OUT_OF_RANGE;
goto END;
}
Status = (u32)XST_SUCCESS;
END:
#endif
return Status;
}
/****************************************************************************/
/**
*
* Initializes the global timer & starts it.
* Calculates the timer ticks for 1us.
*
*
*
* @param None.
*
* @return
*
* None
*
* @note None.
*
*****************************************************************************/
void XilSKey_Efuse_StartTimer(void)
{
#ifdef XSK_ARM_PLATFORM
/**
* Disable the Timer counter
*/
Xil_Out32(XSK_GLOBAL_TIMER_CTRL_REG,0);
/**
* Write the lower 32 bit timer counter register.
*/
Xil_Out32(XSK_GLOBAL_TIMER_COUNT_REG_LOW, 0x0);
/**
* Write the upper 32 bit timer counter register.
*/
Xil_Out32(XSK_GLOBAL_TIMER_COUNT_REG_HIGH, 0x0);
/**
* Enable the Timer counter
*/
Xil_Out32(XSK_GLOBAL_TIMER_CTRL_REG,0x1);
#else
XTmrCtr_SetOptions(&XTmrCtrInst, XSK_TMRCTR_NUM,
XTC_AUTO_RELOAD_OPTION);
XTmrCtr_Start(&XTmrCtrInst, XSK_TMRCTR_NUM);
#endif
}
/****************************************************************************/
/**
*
* Returns the timer ticks from start of timer to till now.
*
* @return
*
* t - Timer ticks lapsed till now.
*
* @note None.
*
*****************************************************************************/
u64 XilSKey_Efuse_GetTime(void)
{
volatile u64 t;
#ifdef XSK_ARM_PLATFORM
volatile u32 t_hi, t_lo;
u32 TiHi;
u32 TiLo;
do {
t_hi = Xil_In32(XSK_GLOBAL_TIMER_COUNT_REG_HIGH);
t_lo = Xil_In32(XSK_GLOBAL_TIMER_COUNT_REG_LOW);
TiHi = t_hi;
TiLo = t_lo;
}while(TiHi != Xil_In32(XSK_GLOBAL_TIMER_COUNT_REG_HIGH));
t = (((u64) TiHi) << 32U) | (u64) TiLo;
#else
t = XTmrCtr_GetValue(&XTmrCtrInst, XSK_TMRCTR_NUM);
#endif
return t;
}
/****************************************************************************/
/**
*
* Calculates the timer ticks to wait to set the time out
*
* @param t - timer ticks to wait to set the timeout
* @param us - Timeout period in us
*
*
* @return
* None.
*
* @note None.
*
*****************************************************************************/
void XilSKey_Efuse_SetTimeOut(volatile u64* t, u64 us)
{
volatile u64 t_end;
t_end = XilSKey_Efuse_GetTime();
/**
* us: time to wait in microseconds. Convert to clock ticks and
* add to current time.
*/
t_end += (us * TimerTicksfor100ns);
*t = t_end;
}
/****************************************************************************/
/**
*
* Checks whether the timer has been expired or not
*
* @param t - timeout value in us
*
* @return
*
* t_end - Returns the global timer value in case of timer expired
*
* @note None.
*
*****************************************************************************/
u8 XilSKey_Efuse_IsTimerExpired(u64 t)
{
u64 t_end;
t_end = XilSKey_Efuse_GetTime();
return t_end >= t;
}
/****************************************************************************/
/**
* Converts the char into the equivalent nibble.
* Ex: 'a' -> 0xa, 'A' -> 0xa, '9'->0x9
*
* @param InChar is input character. It has to be between 0-9,a-f,A-F
* @param Num is the output nibble.
* @return
* - XST_SUCCESS no errors occurred.
* - XST_FAILURE an error when input parameters are not valid
****************************************************************************/
static u32 XilSKey_EfusePs_ConvertCharToNibble (char InChar, u8 *Num)
{
u32 Status = (u32)XST_FAILURE;
/**
* Convert the char to nibble
*/
if ((InChar >= '0') && (InChar <= '9')) {
*Num = (u8)InChar - (u8)'0';
}
else if ((InChar >= 'a') && (InChar <= 'f')) {
*Num = (u8)InChar - (u8)'a' + 10U;
}
else if ((InChar >= 'A') && (InChar <= 'F')) {
*Num = (u8)InChar - (u8)'A' + 10U;
}
else {
Status = (u32)XSK_EFUSEPS_ERROR_STRING_INVALID;
goto END;
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/****************************************************************************/
/**
* Converts the string into the equivalent Hex buffer.
* Ex: "abc123" -> {0xab, 0xc1, 0x23}
*
* @param Str is a Input String. Will support the lower and upper case values.
* Value should be between 0-9, a-f and A-F
*
* @param Buf is Output buffer.
* @param Len of the input string. Should have even values
* @return
* - XST_SUCCESS no errors occurred.
* - XST_FAILURE an error when input parameters are not valid
* - an error when input buffer has invalid values
*
* TDD Test Cases:
---Initialization---
Len is odd
Len is zero
Str is NULL
Buf is NULL
---Functionality---
Str input with only numbers
Str input with All values in A-F
Str input with All values in a-f
Str input with values in a-f, 0-9, A-F
Str input with values in a-z, 0-9, A-Z
Boundary Cases
Memory Bounds of buffer checking
****************************************************************************/
u32 XilSKey_Efuse_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len)
{
u32 ConvertedLen;
u8 LowerNibble = 0U, UpperNibble = 0U;
u32 Status = (u32)XST_FAILURE;
/**
* Check the parameters
*/
if (Str == NULL) {
Status = (u32)XSK_EFUSEPS_ERROR_PARAMETER_NULL;
goto END;
}
if (Buf == NULL) {
Status = (u32)XSK_EFUSEPS_ERROR_PARAMETER_NULL;
goto END;
}
/**
* Len has to be multiple of 2
*/
if ((Len == 0U) || ((Len%2U) == 1U)) {
Status = (u32)XSK_EFUSEPS_ERROR_PARAMETER_NULL;
goto END;
}
if(Len != (strlen(Str)*4U)) {
Status = (u32)XSK_EFUSEPS_ERROR_PARAMETER_NULL;
goto END;
}
ConvertedLen = 0U;
while (ConvertedLen < (Len/4U)) {
/**
* Convert char to nibble
*/
if (XilSKey_EfusePs_ConvertCharToNibble (Str[ConvertedLen],&UpperNibble)
== (u32)XST_SUCCESS) {
/**
* Convert char to nibble
*/
if (XilSKey_EfusePs_ConvertCharToNibble (Str[ConvertedLen+1],
&LowerNibble) == (u32)XST_SUCCESS) {
/**
* Merge upper and lower nibble to Hex
*/
Buf[ConvertedLen/2] =
(UpperNibble << 4U) | LowerNibble;
}
else {
/**
* Error converting Lower nibble
*/
Status = (u32)XSK_EFUSEPS_ERROR_STRING_INVALID;
goto END;
}
}
else {
/**
* Error converting Upper nibble
*/
Status = (u32)XSK_EFUSEPS_ERROR_STRING_INVALID;
goto END;
}
/**
* Converted upper and lower nibbles
*/
xeFUSE_printf(XSK_EFUSE_DEBUG_GENERAL,"Converted %c%c to %0x\n",
Str[ConvertedLen],Str[ConvertedLen+1],Buf[ConvertedLen/2]);
ConvertedLen += 2U;
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/****************************************************************************/
/**
* Converts the string into the equivalent Hex buffer.
* Ex: "abc123" -> {0x23, 0xc1, 0xab}
*
* @param Str is a Input String. Will support the lower and upper case values.
* Value should be between 0-9, a-f and A-F
*
* @param Buf is Output buffer.
* @param Len of the input string. Should have even values
* @return
* - XST_SUCCESS no errors occurred.
* - XST_FAILURE an error when input parameters are not valid
* - an error when input buffer has invalid values
*
* TDD Test Cases:
---Initialization---
Len is odd
Len is zero
Str is NULL
Buf is NULL
---Functionality---
Str input with only numbers
Str input with All values in A-F
Str input with All values in a-f
Str input with values in a-f, 0-9, A-F
Str input with values in a-z, 0-9, A-Z
Boundary Cases
Memory Bounds of buffer checking
****************************************************************************/
u32 XilSKey_Efuse_ConvertStringToHexLE(const char * Str, u8 * Buf, u32 Len)
{
u32 ConvertedLen;
u8 LowerNibble = 0U, UpperNibble = 0U;
u32 StrIndex;
u32 Status = (u32)XST_FAILURE;
/**
* Check the parameters
*/
if (Str == NULL) {
Status = (u32)XSK_EFUSEPS_ERROR_PARAMETER_NULL;
goto END;
}
if (Buf == NULL) {
Status = (u32)XSK_EFUSEPS_ERROR_PARAMETER_NULL;
goto END;
}
/**
* Len has to be multiple of 2
*/
if ((Len == 0U) || ((Len % 2U) == 1U)) {
Status = (u32)XSK_EFUSEPS_ERROR_PARAMETER_NULL;
goto END;
}
if(Len != (strlen(Str)*4U)) {
Status = (u32)XSK_EFUSEPS_ERROR_PARAMETER_NULL;
goto END;
}
StrIndex = (Len/8U) - 1U;
ConvertedLen = 0U;
while (ConvertedLen < (Len/4U)) {
/**
* Convert char to nibble
*/
if (XilSKey_EfusePs_ConvertCharToNibble (Str[ConvertedLen],
&UpperNibble) == (u32)XST_SUCCESS) {
/**
* Convert char to nibble
*/
if (XilSKey_EfusePs_ConvertCharToNibble (Str[ConvertedLen+1],
&LowerNibble) == (u32)XST_SUCCESS) {
/**
* Merge upper and lower nibble to Hex
*/
Buf[StrIndex] =
(UpperNibble << 4U) | LowerNibble;
StrIndex = StrIndex - 1U;
}
else {
/**
* Error converting Lower nibble
*/
Status = (u32)XSK_EFUSEPS_ERROR_STRING_INVALID;
goto END;
}
}
else {
/**
* Error converting Upper nibble
*/
Status = (u32)XSK_EFUSEPS_ERROR_STRING_INVALID;
goto END;
}
/**
* Converted upper and lower nibbles
*/
ConvertedLen += 2U;
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/***************************************************************************/
/**
* This function is used to convert the Big Endian Byte data to
* Little Endian Byte data
* For ex: 1234567890abcdef -> 78563412efcdab90
*
* @param Be Big endian data
* @param Le Little endian data
* @param Len Length of data to be converted and it should be in number of
* words (multiple of 4 bytes)
* @return None.
*
* TDD Test Cases:
*
****************************************************************************/
void XilSKey_EfusePs_ConvertBytesBeToLe(const u8 *Be, u8 *Le, u32 Len)
{
u32 Index;
u32 Length;
if ((Be == NULL) || (Le == NULL) || (Len == 0U)) {
goto END;
}
Length = Len * 4U;
for (Index = 0U; Index < Length; Index = Index+4U) {
Le[Index+3]=Be[Index];
Le[Index+2]=Be[Index+1];
Le[Index+1]=Be[Index+2];
Le[Index]=Be[Index+3];
}
END:
return;
}
/****************************************************************************/
/**
* Convert the Bits to Bytes in Little Endian format
* Ex: 0x5C -> {0, 0, 1, 1, 1, 0, 1, 0}
*
* @param Bits Input Buffer.
* @param Bytes is Output buffer.
* @param Len of the input buffer in bits
* @return None
Test Cases:
Input with All Zeroes
Input with All Ones
Input Little Endian (General Cases )
Input Check Big Endian - False case
Check for Len not a multiple of 8
Check for Len 0
Memory Bounds of buffer checking
****************************************************************************/
void XilSKey_Efuse_ConvertBitsToBytes(const u8 * Bits, u8 * Bytes, u32 Len)
{
u8 Data;
u32 Index, BitIndex = 0U, ByteIndex = 0U;
u32 BytLen = Len;
/* Assert validates the input arguments */
Xil_AssertVoid(Bits != NULL);
Xil_AssertVoid(Bytes != NULL);
/**
* Make sure the bytes array is 0'ed first.
*/
for(Index = 0U; Index < BytLen; Index++) {
Bytes[Index] = 0U;
}
while(BytLen != 0U) {
/**
* Convert 8 Bit One Byte to 1 Bit 8 Bytes
*/
for(Index = 0U; Index < 8U; Index++) {
/**
* Convert from LSB -> MSB - Little Endian
*/
Data = (Bits[BitIndex] >> Index) & 0x1U;
Bytes[ByteIndex] = Data;
ByteIndex++;
BytLen--;
/**
* If len is not Byte aligned
*/
if(BytLen == 0U) {
goto END;
}
}
BitIndex++;
}
END:
return;
}
/****************************************************************************/
/**
* Convert the Bytes to Bits in little endian format
* 0th byte is LSB, 7th byte is MSB
* Ex: {0, 0, 1, 1, 1, 0, 1, 0} -> 0x5C
*
* @param Bytes Input Buffer.
* @param Bits is Output buffer.
* @param Len of the input buffer.
* @return None
Test Cases:
Input with All Zeroes
Input with All Ones
Input Little Endian (General Cases )
Input Check Big Endian - False case
Check for Len not a multiple of 8
Check for Len 0
Memory Bounds of buffer checking
****************************************************************************/
void XilSKey_EfusePs_ConvertBytesToBits(const u8 * Bytes, u8 * Bits , u32 Len)
{
u8 Tmp;
u32 Index, BitIndex = 0U, ByteIndex = 0U;
u32 BytLen = Len;
/* Assert validates the input arguments */
Xil_AssertVoid(Bytes != NULL);
Xil_AssertVoid(Bits != NULL);
/**
* Make sure the bits array is 0 first.
*/
for(Index = 0U; Index < (((BytLen % 8U) != 0U) ? ((BytLen / 8U) + 1U) : (BytLen / 8U)); Index++) {
Bits[Index] = 0U;
}
while(BytLen != 0U) {
/**
* Convert 1 Bit 8 Bytes to 8 Bit 1 Byte
*/
for(Index = 0U; Index < 8U; Index++) {
/**
* Store from LSB -> MSB - Little Endian
*/
Tmp = (Bytes[ByteIndex]) & 0x1U;
Bits[BitIndex] |= (Tmp << Index);
ByteIndex++;
BytLen--;
/**
* If Len is not Byte aligned
*/
if(BytLen == 0U) {
goto END;
}
}
BitIndex++;
}
END:
return;
}
/****************************************************************************/
/**
* Validate the key for proper characters & proper length
*
*
* @param Key - Hash Key
* @param Len - Valid length of key
*
* @return
* XST_SUCCESS - In case of Success
* XST_FAILURE - In case of Failure
****************************************************************************/
u32 XilSKey_Efuse_ValidateKey(const char *Key, u32 Len)
{
u32 i;
u32 Status = (u32)XST_FAILURE;
Xil_AssertNonvoid(Key != NULL);
Xil_AssertNonvoid((Len == XSK_STRING_SIZE_2) ||
(Len == XSK_STRING_SIZE_6) ||
(Len == XSK_STRING_SIZE_8) ||
(Len == XSK_STRING_SIZE_64) ||
(Len == XSK_STRING_SIZE_96));
/**
* Make sure the key has valid length
*/
if (strlen(Key) != Len) {
Status = ((u32)XSK_EFUSEPL_ERROR_KEY_VALIDATION |
(u32)XSK_EFUSEPL_ERROR_NOT_VALID_KEY_LENGTH);
goto END;
}
/**
* Make sure the key has valid characters
*/
for(i = 0U; i < strlen(Key); i++) {
if(XilSKey_Efuse_IsValidChar(&Key[i]) != (u32)XST_SUCCESS) {
Status = ((u32)XSK_EFUSEPL_ERROR_KEY_VALIDATION |
(u32)XSK_EFUSEPL_ERROR_NOT_VALID_KEY_CHAR);
goto END;
}
}
Status = (u32)XSK_EFUSEPL_ERROR_NONE;
END:
return Status;
}
/****************************************************************************/
/**
* Checks whether the passed character is a valid hash key character
*
*
* @param c - Character to check proper value
*
* @return
* XST_SUCCESS - In case of Success
* XST_FAILURE - In case of Failure
****************************************************************************/
u32 XilSKey_Efuse_IsValidChar(const char *c)
{
char ValidChars[] = "0123456789abcdefABCDEF";
char *RetVal;
u32 Status = (u32)XST_FAILURE;
if(c == NULL) {
Status = (u32)XST_FAILURE;
goto END;
}
RetVal = strchr(ValidChars, (int)*c);
if(RetVal != NULL) {
Status = (u32)XST_SUCCESS;
}
END:
return Status;
}
/****************************************************************************/
/**
* This API initializes the Timer based on platform
*
* @param None.
*
* @return RefClk will be returned.
*
* @note None.
*
****************************************************************************/
u32 XilSKey_Timer_Intialise(void)
{
u32 RefClk;
#if defined(XSK_ZYNQ_PLATFORM)
u32 ArmPllFdiv;
u32 ArmClkDivisor;
TimerTicksfor100ns = 0U;
/**
* Extract PLL FDIV value from ARM PLL Control Register
*/
ArmPllFdiv = ((Xil_In32(XSK_ARM_PLL_CTRL_REG) >> 12U) & 0x7FU);
if(ArmPllFdiv == 0U) {
return (u32)XST_FAILURE;
}
/**
* Extract Clock divisor value from ARM Clock Control Register
*/
ArmClkDivisor = ((Xil_In32(XSK_ARM_CLK_CTRL_REG) >> 8U) & 0x3FU);
if( ArmClkDivisor == 0U) {
return (u32)XST_FAILURE;
}
/**
* Initialize the variables
*/
RefClk = ((XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ * ArmClkDivisor)/
ArmPllFdiv);
/**
* Calculate the Timer ticks per 100ns
*/
TimerTicksfor100ns =
(((RefClk * ArmPllFdiv)/ArmClkDivisor) / 2U) / 10000000U;
#elif defined(XSK_MICROBLAZE_PLATFORM)
u32 Status = (u32)XST_FAILURE;
TimerTicksfor1000ns = 0U;
RefClk = XSK_EFUSEPL_CLCK_FREQ_ULTRA;
Status = (u32)XTmrCtr_Initialize(&XTmrCtrInst, (u16)XTMRCTR_DEVICE_ID);
if (Status == (u32)XST_FAILURE) {
return (u32)XST_FAILURE;
}
/*
* Perform a self-test to ensure that the hardware was built
* correctly.
*/
Status = (u32)XTmrCtr_SelfTest(&XTmrCtrInst, XSK_TMRCTR_NUM);
if (Status != (u32)XST_SUCCESS) {
return (u32)XST_FAILURE;
}
TimerTicksfor1000ns = XSK_EFUSEPL_CLCK_FREQ_ULTRA/100000U;
#else
RefClk = 0U;
#endif
return RefClk;
}
/****************************************************************************/
/**
* Copies one string to other from specified location
*
* @param Src is a pointer to Source string.
* @param Dst is a pointer to Destination string.
* @param From which position to be copied.
* @param To which position to be copied.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XilSKey_StrCpyRange(u8 *Src, u8 *Dst, u32 From, u32 To)
{
u32 Index, J = 0U;
u32 SrcLength = strlen((char *)Src);
if (To >= SrcLength) {
goto END;
}
for (Index = From; Index <= To; Index++) {
Dst[J] = Src[Index];
J = J + 1U;
}
END:
Dst[J] = (u8)'\0';
}
/****************************************************************************/
/**
* This function Calculates CRC value based on hexadecimal string passed.
*
* @param Key Pointer to the string contains AES key in hexadecimal
* of length less than or equal to 64.
*
* @return
* - On Success returns the Crc of AES key value.
* - On failure returns the error code when string length
* is greater than 64
*
* @note
* If the length of the string provided is less than 64, this function
* appends the string with zeros.
* For calculation of AES key's CRC one can use
* u32 XilSKey_CrcCalculation(u8 *Key) API or reverse polynomial
* 0x82F63B78.
* @cond xilskey_internal
* @{
* In Microblaze CRC will be calculated from 8th word of key to 0th
* word whereas in ZynqMp Ultrascale's PS eFuse from 0th word to
* 8th word
* @}
@endcond
*
****************************************************************************/
u32 XilSKey_CrcCalculation(u8 *Key)
{
u32 CrcReturn = 0U;
u32 Index;
u8 MaxIndex = 8U;
#if defined (XSK_MICROBLAZE_PLATFORM) || \
defined (XSK_ZYNQ_ULTRA_MP_PLATFORM)
u32 Key_32 = 0U;
u32 Status;
u8 Key_Hex[4U] = {0};
u8 Key_8[9U] = {0};
#endif
#ifdef XSK_MICROBLAZE_PLATFORM
u8 Row = 0U;
#endif
u8 FullKey[65U] = {0U};
u32 Length = strlen((char *)Key);
if (Length > 64U) {
CrcReturn = (u32)XSK_EFUSEPL_ERROR_NOT_VALID_KEY_LENGTH;
goto END;
}
if (Length < 64U) {
XilSKey_StrCpyRange(Key, &FullKey[64U - Length + 1U], 0U, Length-1U);
}
else {
XilSKey_StrCpyRange(Key, FullKey, 0U, Length-1U);
}
#ifdef XSK_MICROBLAZE_ULTRA_PLUS
MaxIndex = 16U;
Row = 5U;
#endif
#ifdef XSK_MICROBLAZE_ULTRA
MaxIndex = 8U;
Row = 20U;
#endif
for (Index = 0U; Index < MaxIndex; Index++) {
#ifdef XSK_MICROBLAZE_PLATFORM
#ifdef XSK_MICROBLAZE_ULTRA
XilSKey_StrCpyRange(FullKey, Key_8, ((7U - Index) * 8U),
((((7U - Index) + 1U) * 8U) - 1U));
#endif
#ifdef XSK_MICROBLAZE_ULTRA_PLUS
XilSKey_StrCpyRange(FullKey, Key_8, (64U - ((Index + 1U) * 4U)),
(63U - (Index * 4U)));
#endif
#endif
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
XilSKey_StrCpyRange(FullKey, Key_8, ((Index) * 8U),
((((Index) * 8U) + 8U) - 1U));
#endif
#if defined (XSK_MICROBLAZE_ULTRA) || \
defined (XSK_ZYNQ_ULTRA_MP_PLATFORM)
Status = XilSKey_Efuse_ConvertStringToHexBE((char *)Key_8,
Key_Hex, 32U);
if (Status != (u32)XST_SUCCESS) {
CrcReturn = Status;
goto END;
}
Key_32 = (((u32)Key_Hex[0U] << 24U) | ((u32)Key_Hex[1U] << 16U) |
((u32)Key_Hex[2U] << 8U) | ((u32)Key_Hex[3U]));
#endif
#ifdef XSK_MICROBLAZE_ULTRA_PLUS
Status = XilSKey_Efuse_ConvertStringToHexBE((char *)Key_8,
Key_Hex, 16U);
if (Status != (u32)XST_SUCCESS) {
CrcReturn = Status;
goto END;
}
Key_32 = ((u32)Key_Hex[0U] << 8U) | (u32)Key_Hex[1U];
#endif
#ifdef XSK_MICROBLAZE_PLATFORM
CrcReturn = XilSKey_RowCrcCalculation(CrcReturn, Key_32, (u32)Row + Index);
#endif
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
CrcReturn = XilSKey_RowCrcCalculation(CrcReturn, Key_32, (u32)8U - Index);
#endif
}
END:
return CrcReturn;
}
/****************************************************************************/
/**
* Calculates CRC value for each row of AES key.
*
* @param PrevCRC holds the prev row's CRC.
* @param Data holds the present row's key.
* @param Addr stores the current row number.
*
* @return Crc of current row.
*
* @note None.
*
****************************************************************************/
u32 XilSKey_RowCrcCalculation(u32 PrevCRC, u32 Data, u32 Addr)
{
u32 Crc = PrevCRC;
u32 Value = Data;
u32 Row = Addr;
u32 Index;
for (Index = 0U; Index < 32U; Index++) {
if ((((Value & 0x1U) ^ Crc) & 0x1U) != 0U) {
Crc = ((Crc >> 1U) ^ REVERSE_POLYNOMIAL);
}
else {
Crc = Crc >> 1U;
}
Value = Value >> 1U;
}
for (Index = 0U; Index < 5U; Index++) {
if ((((Row & 0x1U) ^ Crc) & 0x1U) != 0U) {
Crc = ((Crc >> 1U) ^ REVERSE_POLYNOMIAL);
}
else {
Crc = Crc >> 1U;
}
Row = Row >> 1U;
}
return Crc;
}
/****************************************************************************/
/**
* This API reverse the value.
*
* @param Input is a 32 bit variable
*
* @return Reverse the given value.
*
* @note None.
*
****************************************************************************/
u32 XilSKey_Efuse_ReverseHex(u32 Input)
{
u32 Index = 0U;
u32 Rev = 0U;
u32 Bit;
u32 InputVar = Input;
while (Index < 32U) {
Index = Index + 1U;
Bit = InputVar & 1U;
InputVar = InputVar >> 1U;
Rev = Rev ^ Bit;
if (Index < 32U) {
Rev = Rev << 1U;
}
}
return Rev;
}
/****************************************************************************/
/**
* Calculates CRC value of the provided key. Key should be provided in
* hexa buffer.
*
* @param Key Pointer to an array of 32 bytes, which holds an AES key.
*
* @return Crc of provided AES key value.
*
* @cond xilskey_internal
* @{
* In Microblaze CRC will be calculated from 8th word of key to 0th
* word whereas in ZynqMp Ultrascale's PS eFuse from 0th word to
* 8th word
* @}
@endcond
* To calculate CRC on the AES key in string format please use
* XilSKey_CrcCalculation.
*
****************************************************************************/
u32 XilSkey_CrcCalculation_AesKey(u8 *Key)
{
u32 Crc = 0U;
u32 Index;
u32 MaxIndex;
u32 Index1 = 0xFFFFFFFFU;
#if defined (XSK_MICROBLAZE_PLATFORM) || \
defined (XSK_ZYNQ_ULTRA_MP_PLATFORM)
u32 Key_32 = 0U;
#endif
#ifdef XSK_MICROBLAZE_PLATFORM
u32 Row = 0U;
#endif
#if defined(XSK_MICROBLAZE_ULTRA_PLUS)
MaxIndex = 16U;
Row = 5U;
#elif defined(XSK_MICROBLAZE_ULTRA)
MaxIndex = 8U;
Row = 20U;
#elif defined(XSK_ZYNQ_ULTRA_MP_PLATFORM)
MaxIndex = 8U;
#else
/* Not supported for other than above platforms */
MaxIndex = 0U;
(void) Key;
#endif
for (Index = 0U; Index < MaxIndex; Index++) {
#if defined(XSK_MICROBLAZE_ULTRA)
Index1 = (Index * 4U);
#elif defined(XSK_MICROBLAZE_ULTRA_PLUS)
Index1 = (Index * 2U);
#elif defined(XSK_ZYNQ_ULTRA_MP_PLATFORM)
Index1 = (((u32)7U - Index) * 4U);
#else
Crc = Index1;
break;
#endif
#if defined XSK_MICROBLAZE_ULTRA || \
defined XSK_ZYNQ_ULTRA_MP_PLATFORM
Key_32 = ((u32)Key[Index1 + 3U] << 24U) | ((u32)Key[Index1 + 2U] << 16U) |
((u32)Key[Index1 + 1U] << 8U) | ((u32)Key[Index1 + 0U]);
#endif
#if defined(XSK_MICROBLAZE_ULTRA_PLUS)
Key_32 = ((u32)Key[Index1 + 1U] << 8U) | (u32)Key[Index1];
#endif
#ifdef XSK_MICROBLAZE_PLATFORM
Crc = XilSKey_RowCrcCalculation(Crc, Key_32, (u32)(Row + Index));
#endif
#ifdef XSK_ZYNQ_ULTRA_MP_PLATFORM
Crc = XilSKey_RowCrcCalculation(Crc, Key_32, (u32)8U - Index);
#endif
}
return Crc;
}
#if defined (XSK_ZYNQ_ULTRA_MP_PLATFORM) && !defined (XSK_OVERRIDE_SYSMON_CFG)
/***************************************************************************/
/**
* This function is used to check ADC configuration is suitable for XilsKey
*
* @return
* - XST_SUCCESS in case of valid ADC configuration for XilSKey
* - XST_FAILURE in case of invalid ADC configuration for XilSKey
* - XSK_EFUSEPS_ERROR_XADC_CONFIG Error occurred with XADC config
*
* TDD Cases:
*
****************************************************************************/
u32 XilSKey_EfusePs_XAdcCfgValidate (void)
{
u32 Status = (u32)XST_FAILURE;
XSysMonPsu_Config *ConfigPtr;
XSysMonPsu *XSysmonInstPtr = &XSysmonInst;
/**
* specify the Device ID that is
* generated in xparameters.h
*/
XSysmonDevId = (u16)XSYSMON_PSU_DEVICE_ID;
/**
* Initialize the XAdc driver.
*/
ConfigPtr = XSysMonPsu_LookupConfig(XSysmonDevId);
if (NULL == ConfigPtr) {
Status = (u32)XSK_EFUSEPS_ERROR_XADC_CONFIG;
goto END;
}
XSysMonPsu_InitInstance(XSysmonInstPtr, ConfigPtr);
Status = XilSKey_Is_Valid_SysMon_Cfg(XSysmonInstPtr);
END:
return Status;
}
/****************************************************************************/
/**
* This function checks if sysmon is configured correctly for XilSKey
* functions to monitor LPD temperature, VPINT, and VPAUX.
*
* @param InstancePtr Instance pointer of SysMon.
*
* @return XST_SUCCESS - If sysmon is configured for XilSKey library usage.
* XST_FAILURE - If sysmon is not configured correctly for XilSKey
* library usage.
* @note None.
*
****************************************************************************/
static u32 XilSKey_Is_Valid_SysMon_Cfg(XSysMonPsu *InstancePtr)
{
u32 Status = XST_FAILURE;
u32 CfgData;
u32 SeqMode;
u32 SleepMode;
u32 Mask;
/* Calculate the effective baseaddress based on the Sysmon instance. */
u32 EffectiveBaseAddress =
XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
XSYSMON_PS);
/* Read Cfg1 and make sure channels are configured to read in loop */
CfgData = Xil_In32(EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET);
SeqMode = (CfgData & XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK) >>
XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT;
if ((SeqMode != XSM_SEQ_MODE_SAFE) &&
(SeqMode != XSM_SEQ_MODE_CONTINPASS)) {
goto END;
}
/* When in continuous pass mode, make sure it includes below channels
* for sampling
* 1. Supply 1 (VPINT)
* 2. Supply 3 (VPAUX)
* 3. LPD Temperature
*/
if (XSM_SEQ_MODE_CONTINPASS == SeqMode) {
/* Get Channel sequence mask */
CfgData = Xil_In32(EffectiveBaseAddress +
XSYSMONPSU_SEQ_CH0_OFFSET);
Mask = XSYSMONPSU_SEQ_CH0_SUP3_MASK |
XSYSMONPSU_SEQ_CH0_SUP1_MASK |
XSYSMONPSU_SEQ_CH0_TEMP_MASK;
/* Make sure required channels for XilSKey are enabled */
if ((CfgData & Mask) != Mask) {
goto END;
}
}
/* Read Cfg2 and make sure sysmon is not in power save mode */
CfgData = Xil_In32(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET);
SleepMode = (CfgData & XSYSMONPSU_CFG_REG2_PWR_DOWN_MASK) >>
XSYSMONPSU_CFG_REG2_PWR_DOWN_SHIFT;
if (XSM_PWR_MODE_NORMAL == SleepMode) {
Status = XST_SUCCESS;
}
END:
return Status;
}
#endif
/****************************************************************************/
/**
*
* This function provides correct SLR number to be accessed for corresponding
* config order index.
*
* @param ConfigOrderIndex provide config order index of SLR
* @param SlrNum Pointer to SLR number, where this API updates with
* corresponding SLR number.
*
* @return None.
*
* @note If master SLR of target device is SLR0 then both config order index
* and SLR number are same in order.
* If master SLR of target device is SLR1 then config order and SLR
* numbers are as below.
* SLR 1 = config order index 0
* SLR 0 = config order index 1
* SLR 2 = config order index 2
* SLR 3 = config order index 3
* Configuration order index is the order of SLRs starting from master
* followed by slaves.
*
*****************************************************************************/
void XilSKey_GetSlrNum(u32 MasterSlrNum, u32 ConfigOrderIndex, u32 *SlrNum)
{
/* If master SLR is SLR 0 */
if (MasterSlrNum == XSK_SLR_NUM_0) {
*SlrNum = ConfigOrderIndex;
}
else {
/* If master SLR is SLR 1 */
if (ConfigOrderIndex == XSK_SLR_CONFIG_ORDER_0) {
/* Master SLR is 1 */
*SlrNum = XSK_SLR_NUM_1;
}
else if (ConfigOrderIndex == XSK_SLR_CONFIG_ORDER_1) {
/* SLave 0 is SLR 0 */
*SlrNum = XSK_SLR_NUM_0;
}
else {
/* remaining are same */
*SlrNum = ConfigOrderIndex;
}
}
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_core.h
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPFW_CORE_H_
#define XPFW_CORE_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xpfw_module.h"
#include "xpfw_scheduler.h"
#define XPFW_MAX_MOD_COUNT 32U
typedef struct {
XPfw_Module_t ModList[XPFW_MAX_MOD_COUNT];
XPfw_Scheduler_t Scheduler;
u16 IsReady;
u8 ModCount;
u8 Mode; /**< Mode - Safety Diagnostics Mode / Normal Mode */
} XPfw_Core_t;
XStatus XPfw_CoreInit(u32 Options);
XStatus XPfw_CoreConfigure(void);
XStatus XPfw_CoreDispatchEvent( u32 EventId);
const XPfw_Module_t *XPfw_CoreCreateMod(void);
XStatus XPfw_CoreScheduleTask(const XPfw_Module_t *ModPtr, u32 Interval, VoidFunction_t CallbackRef);
s32 XPfw_CoreRemoveTask(const XPfw_Module_t *ModPtr, u32 Interval, VoidFunction_t CallbackRef);
XStatus XPfw_CoreStopScheduler(void);
XStatus XPfw_CoreLoop(void);
void XPfw_CorePrintStats(void);
XStatus XPfw_CoreRegisterEvent(const XPfw_Module_t *ModPtr, u32 EventId);
XStatus XPfw_CoreDeRegisterEvent(const XPfw_Module_t *ModPtr, u32 EventId);
XStatus XPfw_CoreDispatchIpi(u32 IpiNum, u32 SrcMask);
void XPfw_CoreTickHandler(void);
XStatus XPfw_CoreIsReady(void);
XStatus XPfw_CoreSetCfgHandler(const XPfw_Module_t *ModPtr, XPfwModCfgInitHandler_t CfgHandler);
XStatus XPfw_CoreSetEventHandler(const XPfw_Module_t *ModPtr, XPfwModEventHandler_t EventHandlerFn);
XStatus XPfw_CoreSetIpiHandler(const XPfw_Module_t *ModPtr, XPfwModIpiHandler_t IpiHandlerFn, u16 IpiId);
void XPfw_EnableSlvErr(void);
#ifdef __cplusplus
}
#endif
#endif /* XPFW_CORE_H_ */
<file_sep>/c_drivers/drivers_old_pre_gpio_debug/uart.h
#ifndef _UART_H_
#define _UART_H_
//Functions
uint8_t uart_init_polled();
uint8_t uart_init_interrupt();
uint8_t uart_send_byte(uint8_t data_byte);
uint32_t uart_receive_bytes(uint32_t num_bytes, uint8_t * buff);
//Reads a byte from the uart buffer
uint8_t uart_get_buffer_byte();
uint32_t uart_get_buffer_size();
void uart_clear_buffer();
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilsecure_v4_2/src/xsecure_rsa.c
/******************************************************************************
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_rsa.c
*
* This file contains the implementation of the interface functions for RSA
* driver. Refer to the header file xsecure_sha.h for more detailed information.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 ba 10/13/14 Initial release
* 1.1 ba 12/11/15 Added support for NIST approved SHA-3 in 2.0 silicon
* 2.0 vns 03/15/17 Fixed compilation warning, and corrected SHA2 padding
* verification for silicon version other than 1.0
* 2.2 vns 07/06/17 Added doxygen tags
* vns 17/08/17 Added APIs XSecure_RsaPublicEncrypt and
* XSecure_RsaPrivateDecrypt.As per functionality
* XSecure_RsaPublicEncrypt is same as XSecure_RsaDecrypt.
* 3.1 vns 11/04/18 Added support for 512, 576, 704, 768, 992, 1024, 1152,
* 1408, 1536, 1984, 3072 key sizes, where previous verision
* has support only 2048 and 4096 key sizes.
* 3.2 vns 04/30/18 Added check for private RSA key decryption, such that only
* data to be decrypted should always be lesser than modulus
* 4.0 arc 18/12/18 Fixed MISRA-C violations.
* vns 21/12/18 Added RSA key zeroization after RSA operation
* arc 03/06/19 Added input validations
* vns 03/12/19 Modified as part of XilSecure code re-arch.
* psl 03/26/19 Fixed MISRA-C violation
* 4.1 kal 05/20/19 Updated doxygen tags
* 4.2 kpt 01/07/20 Resolved CR-1049149,1049107,1049116,1049115,1049118
* and Replaced Magic Numbers with Macros
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsecure_rsa.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* @brief
* This function initializes a a XSecure_Rsa structure with the default values
* required for operating the RSA cryptographic engine.
*
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
* @param Mod A character Pointer which contains the key
* Modulus of key size.
* @param ModExt A Pointer to the pre-calculated exponential
* (R^2 Mod N) value.
* - NULL - if user doesn't have pre-calculated R^2 Mod N value,
* control will take care of this calculation internally.
* @param ModExpo Pointer to the buffer which contains key
* exponent.
*
* @return XST_SUCCESS if initialization was successful.
*
* @note `Modulus`, `ModExt` and `ModExpo` are part of prtition signature
* when authenticated boot image is generated by bootgen, else the
* all of them should be extracted from the key.
*
******************************************************************************/
s32 XSecure_RsaInitialize(XSecure_Rsa *InstancePtr, u8 *Mod, u8 *ModExt,
u8 *ModExpo)
{
u32 Status = XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Mod != NULL);
Xil_AssertNonvoid(ModExpo != NULL);
Status = XSecure_RsaCfgInitialize(InstancePtr);
if (Status != (u32)XST_SUCCESS) {
goto END;
}
InstancePtr->Mod = Mod;
InstancePtr->ModExt = ModExt;
InstancePtr->ModExpo = ModExpo;
InstancePtr->SizeInWords = XSECURE_RSA_4096_SIZE_WORDS;
InstancePtr->RsaState = XSECURE_RSA_INITIALIZED;
Status = XST_SUCCESS;
END:
return (s32)Status;
}
/*****************************************************************************/
/**
* @brief
* This function verifies the RSA decrypted data provided is either matching
* with the provided expected hash by taking care of PKCS padding.
*
* @param Signature Pointer to the buffer which holds the decrypted
* RSA signature
* @param Hash Pointer to the buffer which has the hash
* calculated on the data to be authenticated.
* @param HashLen Length of Hash used.
* - For SHA3 it should be 48 bytes
* - For SHA2 it should be 32 bytes
*
* @return
* - XST_SUCCESS if decryption was successful.
* - XST_FAILURE in case of mismatch.
*
******************************************************************************/
u32 XSecure_RsaSignVerification(u8 *Signature, u8 *Hash, u32 HashLen)
{
u8 * Tpadding = (u8 *)XNULL;
u32 PadLength;
u8 * PadPtr = (u8 *)XNULL;
volatile u32 sign_index;
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(Signature != NULL);
Xil_AssertNonvoid(Hash != NULL);
Xil_AssertNonvoid(HashLen == XSECURE_HASH_TYPE_SHA3);
PadLength = XSECURE_FSBL_SIG_SIZE - XSECURE_RSA_BYTE_PAD_LENGTH
- XSECURE_RSA_T_PAD_LENGTH - HashLen;
PadPtr = Signature;
Tpadding = XSecure_RsaGetTPadding();
/*
* Re-Create PKCS#1v1.5 Padding
* MSB ------------------------------------------------------------LSB
* 0x0 || 0x1 || 0xFF(for 202 bytes) || 0x0 || T_padding || SHA384 Hash
*/
if (XSECURE_RSA_BYTE_PAD1 != *PadPtr)
{
goto ENDF;
}
PadPtr++;
if (XSECURE_RSA_BYTE_PAD2 != *PadPtr)
{
goto ENDF;
}
PadPtr++;
for (sign_index = 0U; sign_index < PadLength; sign_index++)
{
if (XSECURE_RSA_BYTE_PAD3 != *PadPtr)
{
goto ENDF;
}
PadPtr++;
}
if (XSECURE_RSA_BYTE_PAD1 != *PadPtr)
{
goto ENDF;
}
PadPtr++;
for (sign_index = 0U; sign_index < XSECURE_RSA_T_PAD_LENGTH; sign_index++)
{
if (*PadPtr != Tpadding[sign_index])
{
goto ENDF;
}
PadPtr++;
}
for (sign_index = 0U; sign_index < HashLen; sign_index++)
{
if (*PadPtr != Hash[sign_index])
{
goto ENDF;
}
PadPtr++;
}
if (sign_index == HashLen)
{
Status = (u32)XST_SUCCESS;
}
ENDF:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function handles the RSA encryption with the public key components
* provided when initializing the RSA cryptographic core with the
* XSecure_RsaInitialize function.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
* @param Input Pointer to the buffer which contains the input
* data to be encrypted.
* @param Size Key size in bytes, Input size also should be
* same as Key size mentioned.Inputs supported are
* - XSECURE_RSA_4096_KEY_SIZE
* - XSECURE_RSA_2048_KEY_SIZE
* - XSECURE_RSA_3072_KEY_SIZE
* @param Result Pointer to the buffer where resultant decrypted
* data to be stored .
*
* @return
* - XST_SUCCESS if encryption was successful.
* - Error code on failure
*
* @note The Size passed here needs to match the key size used in the
* XSecure_RsaInitialize function.
*
******************************************************************************/
s32 XSecure_RsaPublicEncrypt(XSecure_Rsa *InstancePtr, u8 *Input, u32 Size,
u8 *Result)
{
s32 ErrorCode;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Result != NULL);
Xil_AssertNonvoid(Input != NULL);
Xil_AssertNonvoid(Size != 0x00U);
Xil_AssertNonvoid(InstancePtr->RsaState == XSECURE_RSA_INITIALIZED);
ErrorCode = (s32)XSecure_RsaOperation(InstancePtr, Input, Result,
XSECURE_RSA_SIGN_ENC, Size);
return ErrorCode;
}
/*****************************************************************************/
/**
* @brief
* This function handles the RSA decryption with the private key components
* provided when initializing the RSA cryptographic core with the
* XSecure_RsaInitialize function.
*
* @param InstancePtr Pointer to the XSecure_Rsa instance.
* @param Input Pointer to the buffer which contains the input
* data to be decrypted.
* @param Size Key size in bytes, Input size also should be
* same as Key size mentioned. Inputs supported are
* - XSECURE_RSA_4096_KEY_SIZE,
* - XSECURE_RSA_2048_KEY_SIZE
* - XSECURE_RSA_3072_KEY_SIZE
* @param Result Pointer to the buffer where resultant decrypted
* data to be stored .
*
* @return
* - XST_SUCCESS if decryption was successful.
* - XSECURE_RSA_DATA_VALUE_ERROR - if input data is greater than modulus.
* - XST_FAILURE - on RSA operation failure.
*
* @note The Size passed in needs to match the key size used in the
* XSecure_RsaInitialize function..
*
******************************************************************************/
s32 XSecure_RsaPrivateDecrypt(XSecure_Rsa *InstancePtr, u8 *Input, u32 Size,
u8 *Result)
{
s32 Status = (s32)XSECURE_RSA_DATA_VALUE_ERROR;
u32 idx;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Result != NULL);
Xil_AssertNonvoid(Input != NULL);
Xil_AssertNonvoid(Size != 0x00U);
Xil_AssertNonvoid(InstancePtr->RsaState == XSECURE_RSA_INITIALIZED);
/*
* Input data should always be smaller than modulus
* One byte is being checked at a time to make sure the input data
* is smaller than the modulus
*/
for (idx = 0U; idx < Size; idx++) {
if ((*(u8 *)(InstancePtr->Mod + idx)) > (*(u8 *)(Input + idx))) {
Status = (s32)XSecure_RsaOperation(InstancePtr, Input, Result,
XSECURE_RSA_SIGN_DEC, Size);
break;
}
if ((*(u8 *)(InstancePtr->Mod + idx)) < (*(u8 *)(Input + idx))) {
break;
}
}
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_gpp.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* GPU Pixel Processors slaves data structures
*********************************************************************/
#ifndef PM_GPP_H_
#define PM_GPP_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_slave.h"
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmSlaveGpp - Slave wrapper structure used for GPP
* @slv Base slave structure
* @PwrDn Pointer to power down PMU-ROM handler
* @PwrUp Pointer to power up PMU-ROM handler
*/
typedef struct PmSlaveGpp {
PmSlave slv;
PmTranHandler PwrDn;
PmTranHandler PwrUp;
u32 (*const reset)(void);
} PmSlaveGpp;
/*********************************************************************
* Global data declarations
********************************************************************/
extern PmSlaveGpp pmSlaveGpuPP0_g;
extern PmSlaveGpp pmSlaveGpuPP1_g;
extern PmSlaveGpp pmSlaveVcu_g;
#ifdef __cplusplus
}
#endif
#endif /* PM_GPP_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/pm_client.c
/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*
* CONTENT
* Each PU client in the system have such file with definitions of
* masters in the subsystem and functions for getting information
* about the master.
*/
#include "pm_client.h"
#include "xparameters.h"
#include "xil_cache.h"
#include <xreg_cortexa53.h>
#include <xpseudo_asm.h>
/* Mask to get affinity level 0 */
#define PM_AFL0_MASK 0xFF
static struct XPm_Master pm_apu_0_master = {
.node_id = NODE_APU_0,
.pwrctl = APU_PWRCTL,
.pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = NULL,
};
static struct XPm_Master pm_apu_1_master = {
.node_id = NODE_APU_1,
.pwrctl = APU_PWRCTL,
.pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = NULL,
};
static struct XPm_Master pm_apu_2_master = {
.node_id = NODE_APU_2,
.pwrctl = APU_PWRCTL,
.pwrdn_mask = APU_2_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = NULL,
};
static struct XPm_Master pm_apu_3_master = {
.node_id = NODE_APU_3,
.pwrctl = APU_PWRCTL,
.pwrdn_mask = APU_3_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = NULL,
};
/* Order in pm_master_all array must match cpu ids */
static struct XPm_Master *const pm_masters_all[] = {
&pm_apu_0_master,
&pm_apu_1_master,
&pm_apu_2_master,
&pm_apu_3_master,
};
/**
* pm_get_master() - returns pointer to the master structure
* @cpuid: id of the cpu whose master struct pointer should be returned
*
* Return: pointer to a master structure if master is found, otherwise NULL
*/
struct XPm_Master *pm_get_master(const u32 cpuid)
{
struct XPm_Master *master = NULL;
if (cpuid < PM_ARRAY_SIZE(pm_masters_all)) {
master = pm_masters_all[cpuid];
goto done;
}
done:
return master;
}
/**
* pm_get_master_by_node() - returns pointer to the master structure
* @nid: ndoe id of the cpu master
*
* Return: pointer to a master structure if master is found, otherwise NULL
*/
struct XPm_Master *pm_get_master_by_node(const enum XPmNodeId nid)
{
u8 i;
struct XPm_Master *master = NULL;
for (i = 0U; i < PM_ARRAY_SIZE(pm_masters_all); i++) {
if (nid == pm_masters_all[i]->node_id) {
master = pm_masters_all[i];
goto done;
}
}
done:
return master;
}
static u32 pm_get_cpuid(const enum XPmNodeId node)
{
u32 i;
u32 ret;
for (i = 0U; i < PM_ARRAY_SIZE(pm_masters_all); i++) {
if (pm_masters_all[i]->node_id == node) {
ret = i;
goto done;
}
}
ret = UNDEFINED_CPUID;
done:
return ret;
}
const enum XPmNodeId subsystem_node = NODE_APU;
struct XPm_Master *primary_master = &pm_apu_0_master;
void XPm_ClientSuspend(const struct XPm_Master *const master)
{
u32 pwrdn_req;
/* Disable interrupts at processor level */
pm_disable_int();
/* Set powerdown request */
if (NULL != master) {
pwrdn_req = pm_read(master->pwrctl);
pwrdn_req |= master->pwrdn_mask;
pm_write(master->pwrctl, pwrdn_req);
}
}
void XPm_ClientAbortSuspend(void)
{
u32 pwrdn_req;
if (NULL != primary_master) {
pwrdn_req = pm_read(primary_master->pwrctl);
/* Clear powerdown request */
pwrdn_req &= ~primary_master->pwrdn_mask;
pm_write(primary_master->pwrctl, pwrdn_req);
/* Enable interrupts at processor level */
pm_enable_int();
}
}
void XPm_ClientWakeup(const struct XPm_Master *const master)
{
u32 cpuid = pm_get_cpuid(master->node_id);
if (UNDEFINED_CPUID != cpuid) {
u32 val = pm_read(master->pwrctl);
val &= ~(master->pwrdn_mask);
pm_write(master->pwrctl, val);
}
}
/**
* XPm_ClientSuspendFinalize() - Finalize suspend procedure by executing
* wfi instruction
*/
void XPm_ClientSuspendFinalize(void)
{
u32 ctrlReg;
/* Flush the data cache only if it is enabled */
#ifdef __aarch64__
ctrlReg = mfcp(SCTLR_EL3);
if ((XREG_CONTROL_DCACHE_BIT & ctrlReg) != 0U) {
Xil_DCacheFlush();
}
#else
ctrlReg = mfcp(XREG_CP15_SYS_CONTROL);
if ((XREG_CP15_CONTROL_C_BIT & ctrlReg) != 0U) {
Xil_DCacheFlush();
}
#endif
pm_dbg("Going to WFI...\n");
__asm__("wfi");
pm_dbg("WFI exit...\n");
}
/**
* XPm_ClientSetPrimaryMaster() - Set primary master based on master ID
*/
void XPm_ClientSetPrimaryMaster(void)
{
u32 master_id;
#ifdef __aarch64__
master_id = mfcp(MPIDR_EL1);
#else
master_id = mfcp(XREG_CP15_MULTI_PROC_AFFINITY);
#endif
master_id &= PM_AFL0_MASK;
primary_master = pm_masters_all[master_id];
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/include/xiicps_xfer.h
/******************************************************************************
* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_xfer.h
* @addtogroup iicps_v3_11
* @{
*
* Contains implementation of required helper functions for the XIicPs driver.
* See xiicps.h for detailed description of the device and driver.
*
* <pre> MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------------
* 3.11 rna 12/10/19 First release
* </pre>
*
******************************************************************************/
#ifndef XIICPS_XFER_H /* prevent circular inclusions */
#define XIICPS_XFER_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xiicps.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
static INLINE u32 XIicPs_RxDataValid(XIicPs *InstancePtr)
{
return ((XIicPs_ReadReg(InstancePtr->Config.BaseAddress, XIICPS_SR_OFFSET))
& XIICPS_SR_RXDV_MASK);
}
static INLINE u32 XIicPs_RxFIFOFull(XIicPs *InstancePtr, s32 ByteCountVar)
{
u32 Status = 0;
Status = (u32)(XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_TRANS_SIZE_OFFSET) !=(u32)(ByteCountVar -
(s32)XIICPS_FIFO_DEPTH));
return Status;
}
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/*
* This function prepares a device to transfer as a master.
*/
s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
/*
* This function handles continuation of sending data.
*/
void MasterSendData(XIicPs *InstancePtr);
/*
* This function handles continuation of receiving data.
*/
s32 SlaveRecvData(XIicPs *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_periph.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PERIPH_H_
#define XPM_PERIPH_H_
#include "xpm_device.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct XPm_Periph XPm_Periph;
/* Core Operations */
struct XPm_PeriphOps {
void (*SetWakeupSource)(XPm_Periph *Periph, u8 Enable);
};
/**
* The processor core class. This is the base class for all processor cores.
*/
struct XPm_Periph {
XPm_Device Device; /**< Device: Base class */
struct XPm_PeriphOps *PeriphOps; /**< Core operations */
u32 GicProxyMask; /**< GIC Proxy Mask */
u32 GicProxyGroup; /**< GIC Proxy Group */
u32 WakeProcId; /**< ID of processor which needs to wake on GIC interrupt */
};
/************************** Function Prototypes ******************************/
XStatus XPmPeriph_Init(XPm_Periph *Periph, u32 Id, u32 BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock,
XPm_ResetNode *Reset, u32 GicProxyMask,
u32 GicProxyGroup);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_PERIPH_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/client/pm_api_sys.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/**
* @file pm_api_sys.h
*
* @addtogroup xpm_versal_apis XilPM Versal APIs
* @{
*****************************************************************************/
#ifndef PM_API_SYS_H_
#define PM_API_SYS_H_
#include "pm_client.h"
#include "xpm_defs.h"
#include "xpm_err.h"
#include "xpm_nodeid.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* pm_init_suspend - Init suspend callback arguments (save for custom handling)
*/
struct pm_init_suspend {
volatile u8 received; /**< Has init suspend callback been received/handled */
enum XPmSuspendReason reason; /**< Reason of initializing suspend */
u32 latency; /**< Maximum allowed latency */
u32 state; /**< Targeted sleep/suspend state */
u32 timeout; /**< Period of time the client has to response */
};
/*
* pm_acknowledge - Acknowledge callback arguments (save for custom handling)
*/
struct pm_acknowledge {
volatile u8 received; /**< Has acknowledge argument been received? */
u32 node; /**< Node argument about which the acknowledge is */
XStatus status; /**< Acknowledged status */
u32 opp; /**< Operating point of node in question */
};
/**
* XPm_NodeStatus - struct containing node status information
*/
typedef struct XPm_NdStatus {
u32 status; /**< Node power state */
u32 requirements; /**< Current requirements asserted on the node (slaves only) */
u32 usage; /**< Usage information (which master is currently using the slave) */
} XPm_NodeStatus;
/**
* XPm_Notifier - Notifier structure registered with a callback by app
*/
typedef struct XPm_Ntfier {
/**
* Custom callback handler to be called when the notification is
* received. The custom handler would execute from interrupt
* context, it shall return quickly and must not block! (enables
* event-driven notifications)
*/
void (*const callback)(struct XPm_Ntfier* const notifier);
const u32 node; /**< Node argument (the node to receive notifications about) */
enum XPmNotifyEvent event; /**< Event argument (the event type to receive notifications about) */
u32 flags; /**< Flags */
/**
* Operating point of node in question. Contains the value updated
* when the last event notification is received. User shall not
* modify this value while the notifier is registered.
*/
volatile u32 oppoint;
/**
* How many times the notification has been received - to be used
* by application (enables polling). User shall not modify this
* value while the notifier is registered.
*/
volatile u32 received;
/**
* Pointer to next notifier in linked list. Must not be modified
* while the notifier is registered. User shall not ever modify
* this value.
*/
struct XPm_Ntfier* next;
} XPm_Notifier;
/* Global data declarations */
extern struct pm_init_suspend pm_susp;
extern struct pm_acknowledge pm_ack;
XStatus XPm_InitXilpm(XIpiPsu *IpiInst);
enum XPmBootStatus XPm_GetBootStatus(void);
XStatus XPm_GetChipID(u32* IDCode, u32 *Version);
XStatus XPm_GetApiVersion(u32 *Version);
XStatus XPm_RequestNode(const u32 DeviceId, const u32 Capabilities,
const u32 QoS, const u32 Ack);
XStatus XPm_ReleaseNode(const u32 DeviceId);
XStatus XPm_SetRequirement(const u32 DeviceId, const u32 Capabilities,
const u32 QoS, const u32 Ack);
XStatus XPm_GetNodeStatus(const u32 DeviceId,
XPm_NodeStatus *const NodeStatus);
XStatus XPm_ResetAssert(const u32 ResetId, const u32 Action);
XStatus XPm_ResetGetStatus(const u32 ResetId, u32 *const State);
XStatus XPm_PinCtrlRequest(const u32 PinId);
XStatus XPm_PinCtrlRelease(const u32 PinId);
XStatus XPm_PinCtrlSetFunction(const u32 PinId, const u32 FunctionId);
XStatus XPm_PinCtrlGetFunction(const u32 PinId, u32 *const FunctionId);
XStatus XPm_PinCtrlSetParameter(const u32 PinId, const u32 ParamId, const u32 ParamVal);
XStatus XPm_PinCtrlGetParameter(const u32 PinId, const u32 ParamId, u32 *const ParamVal);
XStatus XPm_DevIoctl(const u32 DeviceId, const u32 IoctlId, const u32 Arg1,
const u32 Arg2, u32 *const Response);
XStatus XPm_ClockEnable(const u32 ClockId);
XStatus XPm_ClockDisable(const u32 ClockId);
XStatus XPm_ClockGetStatus(const u32 ClockId, u32 *const State);
XStatus XPm_ClockSetDivider(const u32 ClockId, const u32 Divider);
XStatus XPm_ClockGetDivider(const u32 ClockId, u32 *const Divider);
XStatus XPm_ClockSetParent(const u32 ClockId, const u32 ParentIdx);
XStatus XPm_ClockGetParent(const u32 ClockId, u32 *const ParentIdx);
XStatus XPm_PllSetParameter(const u32 ClockId,
const enum XPm_PllConfigParams ParamId,
const u32 Value);
XStatus XPm_PllGetParameter(const u32 ClockId,
const enum XPm_PllConfigParams ParamId,
u32 *const Value);
XStatus XPm_PllSetMode(const u32 ClockId, const u32 Value);
XStatus XPm_PllGetMode(const u32 ClockId, u32 *const Value);
XStatus XPm_SelfSuspend(const u32 DeviceId, const u32 Latency, const u8 State,
const u64 Address);
XStatus XPm_RequestWakeUp(const u32 TargetDevId, const u8 SetAddress,
const u64 Address, const u32 Ack);
void XPm_SuspendFinalize(void);
XStatus XPm_RequestSuspend(const u32 TargetSubsystemId, const u32 Ack,
const u32 Latency, const u32 State);
XStatus XPm_AbortSuspend(const enum XPmAbortReason Reason);
XStatus XPm_ForcePowerDown(const u32 TargetDevId, const u32 Ack);
XStatus XPm_SystemShutdown(const u32 Type, const u32 SubType);
XStatus XPm_SetWakeUpSource(const u32 TargetDeviceId,
const u32 DeviceId, const u32 Enable);
XStatus XPm_Query(const u32 QueryId, const u32 Arg1, const u32 Arg2,
const u32 Arg3, u32 *const Data);
int XPm_SetMaxLatency(const u32 DeviceId, const u32 Latency);
XStatus XPm_GetOpCharacteristic(const u32 DeviceId,
const enum XPmOpCharType Type,
u32 *const Result);
int XPm_InitFinalize(void);
int XPm_RegisterNotifier(XPm_Notifier* const Notifier);
int XPm_UnregisterNotifier(XPm_Notifier* const Notifier);
void XPm_NotifyCb(const u32 Node, const enum XPmNotifyEvent Event,
const u32 Oppoint);
void XPm_InitSuspendCb(const enum XPmSuspendReason Reason,
const u32 Latency, const u32 State, const u32 Timeout);
void XPm_AcknowledgeCb(const u32 Node, const XStatus Status, const u32 Oppoint);
int XPm_SetConfiguration(const u32 Address);
int XPm_ClockSetRate(const u32 ClockId, const u32 Rate);
int XPm_ClockGetRate(const u32 ClockId, u32 *const Rate);
int XPm_MmioWrite(const u32 Address, const u32 Mask, const u32 Value);
int XPm_MmioRead(const u32 Address, u32 *const Value);
#ifdef __cplusplus
}
#endif
#endif /* PM_API_SYS_H_ */
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_version.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef ZYNQMP_XPFW_VERSION__H_
#define ZYNQMP_XPFW_VERSION__H_
#ifdef __cplusplus
extern "C" {
#endif
#define ZYNQMP_XPFW_VERSION "2020.1"
#ifdef __cplusplus
}
#endif
#endif /* ZYNQMP_XPFW_VERSION__H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_device_idle.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_DEVICE_IDLE_H_
#define XPM_DEVICE_IDLE_H_
#include "xparameters.h"
#include "xpm_node.h"
#include "xpm_device.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct XPmDevice_SoftResetInfo {
u32 DeviceId;
void (*SoftRst)(u32 BaseAddress); /**< Individual IP soft reset function */
void (*IdleHook)(u16 DeviceId, u32 BaseAddress); /**< Hook function for idling */
u16 IdleHookArgs;
} XPmDevice_SoftResetInfo;
#if defined(XPAR_PSV_QSPI_0_DEVICE_ID)
#include "xqspipsu.h"
void NodeQspiIdle(u16 DeviceId, u32 BaseAddress);
#endif
#if defined(XPAR_PSV_OSPI_0_DEVICE_ID)
#include "xospipsv.h"
void NodeOspiIdle(u16 DeviceId, u32 BaseAddress);
#endif
#if defined(XPAR_PSV_SD_0_DEVICE_ID) || defined(XPAR_PSV_SD_1_DEVICE_ID)
#include "xsdps.h"
void NodeSdioIdle(u16 DeviceId, u32 BaseAddress);
#endif
#if defined(XPAR_XUSBPSU_0_DEVICE_ID)
#include "xusbpsu.h"
void NodeUsbIdle(u16 DeviceId, u32 BaseAddress);
#endif
#if defined(XPAR_PSV_ETHERNET_0_DEVICE_ID) || defined(XPAR_PSV_ETHERNET_1_DEVICE_ID)
#include "xemacps_hw.h"
void NodeGemIdle(u16 DeviceId, u32 BaseAddress);
#endif
#if defined(XPAR_PSV_GDMA_0_DEVICE_ID) || defined(XPAR_PSV_ADMA_0_DEVICE_ID)
#include "xzdma_hw.h"
void NodeZdmaIdle(u16 DeviceId, u32 BaseAddress);
#endif
void XPmDevice_SoftResetIdle(XPm_Device *Device, const u32 IdleReq);
#ifdef __cplusplus
}
#endif
#endif /* XPM_DEVICE_IDLE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_pin.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_PIN_H_
#define XPM_PIN_H_
#include "xpm_node.h"
#include "xpm_pinfunc.h"
#include "xpm_device.h"
#include "xpm_api.h"
#ifdef __cplusplus
extern "C" {
#endif
/* IOU_SLCR register related macros */
#define BITS_IN_REG (32U)
#define PINS_PER_BANK (26U)
#define BNK_OFFSET (0x200U)
#define PINNUM(Id) ((NODEINDEX(Id) - (u32)XPM_NODEIDX_STMIC_LMIO_0) % PINS_PER_BANK)
#define SEL_SLEW (0x00000120U)
#define EN_WK_PD (0x00000110U)
#define EN_WK_PU (0x00000114U)
#define EN_RX_SCHMITT_HYST (0x0000010CU)
#define SEL_DRV0 (0x00000118U)
#define SEL_DRV1 (0x0000011CU)
#define SEL_DRV_WIDTH (2U)
#define SEL_DRV0_MASK(PinIdx) ((u32)0x3U << (PINNUM(PinIdx)))
#define SEL_DRV1_MASK(PinIdx) ((u32)0x3U << (PINNUM(PinIdx) - (BITS_IN_REG / SEL_DRV_WIDTH)))
#define VMODE (0x0000015CU)
#define VMODE_MASK (0x1U)
#define TRI_STATE (0x200U)
/* Pin states */
typedef enum {
XPM_PINSTATE_UNUSED,
XPM_PINSTATE_ASSIGNED,
} XPm_PinState;
typedef struct XPm_PinNode XPm_PinNode;
/**
* The Pin class.
*/
struct XPm_PinNode {
XPm_Node Node; /**< Node: Base class */
XPm_PinFunc *PinFunc; /**< Function that this pin is allocated to */
u16 *Groups; /**< Array of group identifier supported by this pin */
u16 SubsysIdx; /**< Subsystem Idx of the owner who is using this pin */
u8 NumGroups; /**< Number of function groups allocated to this pin */
u8 Bank:2; /**< Specifies the bank number */
u8 BiasStatus:1; /**< BiasStatus: 0 – Disable; 1 – Enable */
u8 PullCtrl:1; /**< PullCtrl: 0 – Pull Down; 1 – Pull Up */
u8 TriState:1; /**< TriState: 0 – Disable; 1 – Enable */
};
/************************** Function Prototypes ******************************/
XStatus XPmPin_Init(XPm_PinNode *Pin, u32 PinId, u32 BaseAddress);
XPm_PinNode *XPmPin_GetById(u32 PinId);
XStatus XPmPin_SetPinFunction(u32 PinId, u32 FuncId);
XStatus XPmPin_GetPinFunction(u32 PinId, u32 *FuncId);
XStatus XPmPin_SetPinConfig(u32 PinId, u32 Param, u32 Value);
XStatus XPmPin_GetPinConfig(u32 PinId, u32 Param, u32 *Value);
XStatus XPmPin_GetNumPins(u32 *NumPins);
XStatus XPmPin_GetPinGroups(u32 PinId, u32 Index, u16 *Groups);
XStatus XPmPin_CheckPerms(const u32 SubsystemId, const u32 PinId);
XStatus XPmPin_Release(const u32 SubsystemId, const u32 PinId);
XStatus XPmPin_Request(const u32 SubsystemId, const u32 PinId);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_PIN_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/csudma.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _CSUDMA_H_
#define _CSUDMA_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* CSUDMA Base Address
*/
#define CSUDMA_BASEADDR 0XFFC80000
/**
* Register: CSUDMA_CSUDMA_SRC_ADDR
*/
#define CSUDMA_CSUDMA_SRC_ADDR ( ( CSUDMA_BASEADDR ) + 0X00000000 )
#define CSUDMA_CSUDMA_SRC_ADDR_ADDR_SHIFT 2
#define CSUDMA_CSUDMA_SRC_ADDR_ADDR_WIDTH 30
#define CSUDMA_CSUDMA_SRC_ADDR_ADDR_MASK 0XFFFFFFFC
/**
* Register: CSUDMA_CSUDMA_SRC_SIZE
*/
#define CSUDMA_CSUDMA_SRC_SIZE ( ( CSUDMA_BASEADDR ) + 0X00000004 )
#define CSUDMA_CSUDMA_SRC_SIZE_SIZE_SHIFT 2
#define CSUDMA_CSUDMA_SRC_SIZE_SIZE_WIDTH 27
#define CSUDMA_CSUDMA_SRC_SIZE_SIZE_MASK 0X1FFFFFFC
#define CSUDMA_CSUDMA_SRC_SIZE_LAST_WORD_SHIFT 0
#define CSUDMA_CSUDMA_SRC_SIZE_LAST_WORD_WIDTH 1
#define CSUDMA_CSUDMA_SRC_SIZE_LAST_WORD_MASK 0X00000001
/**
* Register: CSUDMA_CSUDMA_SRC_STS
*/
#define CSUDMA_CSUDMA_SRC_STS ( ( CSUDMA_BASEADDR ) + 0X00000008 )
#define CSUDMA_CSUDMA_SRC_STS_DONE_CNT_SHIFT 13
#define CSUDMA_CSUDMA_SRC_STS_DONE_CNT_WIDTH 3
#define CSUDMA_CSUDMA_SRC_STS_DONE_CNT_MASK 0X0000E000
#define CSUDMA_CSUDMA_SRC_STS_SRC_FIFO_LEVEL_SHIFT 5
#define CSUDMA_CSUDMA_SRC_STS_SRC_FIFO_LEVEL_WIDTH 8
#define CSUDMA_CSUDMA_SRC_STS_SRC_FIFO_LEVEL_MASK 0X00001FE0
#define CSUDMA_CSUDMA_SRC_STS_RD_OUTSTANDING_SHIFT 1
#define CSUDMA_CSUDMA_SRC_STS_RD_OUTSTANDING_WIDTH 4
#define CSUDMA_CSUDMA_SRC_STS_RD_OUTSTANDING_MASK 0X0000001E
#define CSUDMA_CSUDMA_SRC_STS_BUSY_SHIFT 0
#define CSUDMA_CSUDMA_SRC_STS_BUSY_WIDTH 1
#define CSUDMA_CSUDMA_SRC_STS_BUSY_MASK 0X00000001
/**
* Register: CSUDMA_CSUDMA_SRC_CTRL
*/
#define CSUDMA_CSUDMA_SRC_CTRL ( ( CSUDMA_BASEADDR ) + 0X0000000C )
#define CSUDMA_CSUDMA_SRC_CTRL_APB_ERR_RESP_SHIFT 24
#define CSUDMA_CSUDMA_SRC_CTRL_APB_ERR_RESP_WIDTH 1
#define CSUDMA_CSUDMA_SRC_CTRL_APB_ERR_RESP_MASK 0X01000000
#define CSUDMA_CSUDMA_SRC_CTRL_ENDIANNESS_SHIFT 23
#define CSUDMA_CSUDMA_SRC_CTRL_ENDIANNESS_WIDTH 1
#define CSUDMA_CSUDMA_SRC_CTRL_ENDIANNESS_MASK 0X00800000
#define CSUDMA_CSUDMA_SRC_CTRL_AXI_BRST_TYPE_SHIFT 22
#define CSUDMA_CSUDMA_SRC_CTRL_AXI_BRST_TYPE_WIDTH 1
#define CSUDMA_CSUDMA_SRC_CTRL_AXI_BRST_TYPE_MASK 0X00400000
#define CSUDMA_CSUDMA_SRC_CTRL_TIMEOUT_VAL_SHIFT 10
#define CSUDMA_CSUDMA_SRC_CTRL_TIMEOUT_VAL_WIDTH 12
#define CSUDMA_CSUDMA_SRC_CTRL_TIMEOUT_VAL_MASK 0X003FFC00
#define CSUDMA_CSUDMA_SRC_CTRL_FIFO_THRESH_SHIFT 2
#define CSUDMA_CSUDMA_SRC_CTRL_FIFO_THRESH_WIDTH 8
#define CSUDMA_CSUDMA_SRC_CTRL_FIFO_THRESH_MASK 0X000003FC
#define CSUDMA_CSUDMA_SRC_CTRL_PAUSE_STRM_SHIFT 1
#define CSUDMA_CSUDMA_SRC_CTRL_PAUSE_STRM_WIDTH 1
#define CSUDMA_CSUDMA_SRC_CTRL_PAUSE_STRM_MASK 0X00000002
#define CSUDMA_CSUDMA_SRC_CTRL_PAUSE_MEM_SHIFT 0
#define CSUDMA_CSUDMA_SRC_CTRL_PAUSE_MEM_WIDTH 1
#define CSUDMA_CSUDMA_SRC_CTRL_PAUSE_MEM_MASK 0X00000001
/**
* Register: CSUDMA_CSUDMA_SRC_CRC
*/
#define CSUDMA_CSUDMA_SRC_CRC ( ( CSUDMA_BASEADDR ) + 0X00000010 )
#define CSUDMA_CSUDMA_SRC_CRC_CRC_SHIFT 0
#define CSUDMA_CSUDMA_SRC_CRC_CRC_WIDTH 32
#define CSUDMA_CSUDMA_SRC_CRC_CRC_MASK 0XFFFFFFFF
/**
* Register: CSUDMA_CSUDMA_SRC_I_STS
*/
#define CSUDMA_CSUDMA_SRC_I_STS ( ( CSUDMA_BASEADDR ) + 0X00000014 )
#define CSUDMA_CSUDMA_SRC_I_STS_INVALID_APB_SHIFT 6
#define CSUDMA_CSUDMA_SRC_I_STS_INVALID_APB_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_STS_INVALID_APB_MASK 0X00000040
#define CSUDMA_CSUDMA_SRC_I_STS_THRESH_HIT_SHIFT 5
#define CSUDMA_CSUDMA_SRC_I_STS_THRESH_HIT_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_STS_THRESH_HIT_MASK 0X00000020
#define CSUDMA_CSUDMA_SRC_I_STS_TIMEOUT_MEM_SHIFT 4
#define CSUDMA_CSUDMA_SRC_I_STS_TIMEOUT_MEM_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_STS_TIMEOUT_MEM_MASK 0X00000010
#define CSUDMA_CSUDMA_SRC_I_STS_TIMEOUT_STRM_SHIFT 3
#define CSUDMA_CSUDMA_SRC_I_STS_TIMEOUT_STRM_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_STS_TIMEOUT_STRM_MASK 0X00000008
#define CSUDMA_CSUDMA_SRC_I_STS_AXI_RDERR_SHIFT 2
#define CSUDMA_CSUDMA_SRC_I_STS_AXI_RDERR_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_STS_AXI_RDERR_MASK 0X00000004
#define CSUDMA_CSUDMA_SRC_I_STS_DONE_SHIFT 1
#define CSUDMA_CSUDMA_SRC_I_STS_DONE_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_STS_DONE_MASK 0X00000002
#define CSUDMA_CSUDMA_SRC_I_STS_MEM_DONE_SHIFT 0
#define CSUDMA_CSUDMA_SRC_I_STS_MEM_DONE_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_STS_MEM_DONE_MASK 0X00000001
/**
* Register: CSUDMA_CSUDMA_SRC_I_EN
*/
#define CSUDMA_CSUDMA_SRC_I_EN ( ( CSUDMA_BASEADDR ) + 0X00000018 )
#define CSUDMA_CSUDMA_SRC_I_EN_INVALID_APB_SHIFT 6
#define CSUDMA_CSUDMA_SRC_I_EN_INVALID_APB_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_EN_INVALID_APB_MASK 0X00000040
#define CSUDMA_CSUDMA_SRC_I_EN_THRESH_HIT_SHIFT 5
#define CSUDMA_CSUDMA_SRC_I_EN_THRESH_HIT_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_EN_THRESH_HIT_MASK 0X00000020
#define CSUDMA_CSUDMA_SRC_I_EN_TIMEOUT_MEM_SHIFT 4
#define CSUDMA_CSUDMA_SRC_I_EN_TIMEOUT_MEM_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_EN_TIMEOUT_MEM_MASK 0X00000010
#define CSUDMA_CSUDMA_SRC_I_EN_TIMEOUT_STRM_SHIFT 3
#define CSUDMA_CSUDMA_SRC_I_EN_TIMEOUT_STRM_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_EN_TIMEOUT_STRM_MASK 0X00000008
#define CSUDMA_CSUDMA_SRC_I_EN_AXI_RDERR_SHIFT 2
#define CSUDMA_CSUDMA_SRC_I_EN_AXI_RDERR_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_EN_AXI_RDERR_MASK 0X00000004
#define CSUDMA_CSUDMA_SRC_I_EN_DONE_SHIFT 1
#define CSUDMA_CSUDMA_SRC_I_EN_DONE_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_EN_DONE_MASK 0X00000002
#define CSUDMA_CSUDMA_SRC_I_EN_MEM_DONE_SHIFT 0
#define CSUDMA_CSUDMA_SRC_I_EN_MEM_DONE_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_EN_MEM_DONE_MASK 0X00000001
/**
* Register: CSUDMA_CSUDMA_SRC_I_DIS
*/
#define CSUDMA_CSUDMA_SRC_I_DIS ( ( CSUDMA_BASEADDR ) + 0X0000001C )
#define CSUDMA_CSUDMA_SRC_I_DIS_INVALID_APB_SHIFT 6
#define CSUDMA_CSUDMA_SRC_I_DIS_INVALID_APB_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_DIS_INVALID_APB_MASK 0X00000040
#define CSUDMA_CSUDMA_SRC_I_DIS_THRESH_HIT_SHIFT 5
#define CSUDMA_CSUDMA_SRC_I_DIS_THRESH_HIT_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_DIS_THRESH_HIT_MASK 0X00000020
#define CSUDMA_CSUDMA_SRC_I_DIS_TIMEOUT_MEM_SHIFT 4
#define CSUDMA_CSUDMA_SRC_I_DIS_TIMEOUT_MEM_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_DIS_TIMEOUT_MEM_MASK 0X00000010
#define CSUDMA_CSUDMA_SRC_I_DIS_TIMEOUT_STRM_SHIFT 3
#define CSUDMA_CSUDMA_SRC_I_DIS_TIMEOUT_STRM_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_DIS_TIMEOUT_STRM_MASK 0X00000008
#define CSUDMA_CSUDMA_SRC_I_DIS_AXI_RDERR_SHIFT 2
#define CSUDMA_CSUDMA_SRC_I_DIS_AXI_RDERR_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_DIS_AXI_RDERR_MASK 0X00000004
#define CSUDMA_CSUDMA_SRC_I_DIS_DONE_SHIFT 1
#define CSUDMA_CSUDMA_SRC_I_DIS_DONE_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_DIS_DONE_MASK 0X00000002
#define CSUDMA_CSUDMA_SRC_I_DIS_MEM_DONE_SHIFT 0
#define CSUDMA_CSUDMA_SRC_I_DIS_MEM_DONE_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_DIS_MEM_DONE_MASK 0X00000001
/**
* Register: CSUDMA_CSUDMA_SRC_I_MASK
*/
#define CSUDMA_CSUDMA_SRC_I_MASK ( ( CSUDMA_BASEADDR ) + 0X00000020 )
#define CSUDMA_CSUDMA_SRC_I_MASK_INVALID_APB_SHIFT 6
#define CSUDMA_CSUDMA_SRC_I_MASK_INVALID_APB_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_MASK_INVALID_APB_MASK 0X00000040
#define CSUDMA_CSUDMA_SRC_I_MASK_THRESH_HIT_SHIFT 5
#define CSUDMA_CSUDMA_SRC_I_MASK_THRESH_HIT_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_MASK_THRESH_HIT_MASK 0X00000020
#define CSUDMA_CSUDMA_SRC_I_MASK_TIMEOUT_MEM_SHIFT 4
#define CSUDMA_CSUDMA_SRC_I_MASK_TIMEOUT_MEM_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_MASK_TIMEOUT_MEM_MASK 0X00000010
#define CSUDMA_CSUDMA_SRC_I_MASK_TIMEOUT_STRM_SHIFT 3
#define CSUDMA_CSUDMA_SRC_I_MASK_TIMEOUT_STRM_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_MASK_TIMEOUT_STRM_MASK 0X00000008
#define CSUDMA_CSUDMA_SRC_I_MASK_AXI_RDERR_SHIFT 2
#define CSUDMA_CSUDMA_SRC_I_MASK_AXI_RDERR_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_MASK_AXI_RDERR_MASK 0X00000004
#define CSUDMA_CSUDMA_SRC_I_MASK_DONE_SHIFT 1
#define CSUDMA_CSUDMA_SRC_I_MASK_DONE_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_MASK_DONE_MASK 0X00000002
#define CSUDMA_CSUDMA_SRC_I_MASK_MEM_DONE_SHIFT 0
#define CSUDMA_CSUDMA_SRC_I_MASK_MEM_DONE_WIDTH 1
#define CSUDMA_CSUDMA_SRC_I_MASK_MEM_DONE_MASK 0X00000001
/**
* Register: CSUDMA_CSUDMA_SRC_CTRL2
*/
#define CSUDMA_CSUDMA_SRC_CTRL2 ( ( CSUDMA_BASEADDR ) + 0X00000024 )
#define CSUDMA_CSUDMA_SRC_CTRL2_RAM_EMASA_SHIFT 27
#define CSUDMA_CSUDMA_SRC_CTRL2_RAM_EMASA_WIDTH 1
#define CSUDMA_CSUDMA_SRC_CTRL2_RAM_EMASA_MASK 0X08000000
#define CSUDMA_CSUDMA_SRC_CTRL2_ARCACHE_SHIFT 24
#define CSUDMA_CSUDMA_SRC_CTRL2_ARCACHE_WIDTH 3
#define CSUDMA_CSUDMA_SRC_CTRL2_ARCACHE_MASK 0X07000000
#define CSUDMA_CSUDMA_SRC_CTRL2_ROUTE_BIT_SHIFT 23
#define CSUDMA_CSUDMA_SRC_CTRL2_ROUTE_BIT_WIDTH 1
#define CSUDMA_CSUDMA_SRC_CTRL2_ROUTE_BIT_MASK 0X00800000
#define CSUDMA_CSUDMA_SRC_CTRL2_TIMEOUT_EN_SHIFT 22
#define CSUDMA_CSUDMA_SRC_CTRL2_TIMEOUT_EN_WIDTH 1
#define CSUDMA_CSUDMA_SRC_CTRL2_TIMEOUT_EN_MASK 0X00400000
#define CSUDMA_CSUDMA_SRC_CTRL2_RAM_EMAB_SHIFT 19
#define CSUDMA_CSUDMA_SRC_CTRL2_RAM_EMAB_WIDTH 3
#define CSUDMA_CSUDMA_SRC_CTRL2_RAM_EMAB_MASK 0X00380000
#define CSUDMA_CSUDMA_SRC_CTRL2_RAM_EMAA_SHIFT 16
#define CSUDMA_CSUDMA_SRC_CTRL2_RAM_EMAA_WIDTH 3
#define CSUDMA_CSUDMA_SRC_CTRL2_RAM_EMAA_MASK 0X00070000
#define CSUDMA_CSUDMA_SRC_CTRL2_TIMEOUT_PRE_SHIFT 4
#define CSUDMA_CSUDMA_SRC_CTRL2_TIMEOUT_PRE_WIDTH 12
#define CSUDMA_CSUDMA_SRC_CTRL2_TIMEOUT_PRE_MASK 0X0000FFF0
#define CSUDMA_CSUDMA_SRC_CTRL2_MAX_OUTS_CMDS_SHIFT 0
#define CSUDMA_CSUDMA_SRC_CTRL2_MAX_OUTS_CMDS_WIDTH 4
#define CSUDMA_CSUDMA_SRC_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000F
/**
* Register: CSUDMA_CSUDMA_SRC_ADDR_MSB
*/
#define CSUDMA_CSUDMA_SRC_ADDR_MSB ( ( CSUDMA_BASEADDR ) + 0X00000028 )
#define CSUDMA_CSUDMA_SRC_ADDR_MSB_ADDR_MSB_SHIFT 0
#define CSUDMA_CSUDMA_SRC_ADDR_MSB_ADDR_MSB_WIDTH 17
#define CSUDMA_CSUDMA_SRC_ADDR_MSB_ADDR_MSB_MASK 0X0001FFFF
/**
* Register: CSUDMA_CSUDMA_DST_ADDR
*/
#define CSUDMA_CSUDMA_DST_ADDR ( ( CSUDMA_BASEADDR ) + 0X00000800 )
#define CSUDMA_CSUDMA_DST_ADDR_ADDR_SHIFT 2
#define CSUDMA_CSUDMA_DST_ADDR_ADDR_WIDTH 30
#define CSUDMA_CSUDMA_DST_ADDR_ADDR_MASK 0XFFFFFFFC
/**
* Register: CSUDMA_CSUDMA_DST_SIZE
*/
#define CSUDMA_CSUDMA_DST_SIZE ( ( CSUDMA_BASEADDR ) + 0X00000804 )
#define CSUDMA_CSUDMA_DST_SIZE_SIZE_SHIFT 2
#define CSUDMA_CSUDMA_DST_SIZE_SIZE_WIDTH 27
#define CSUDMA_CSUDMA_DST_SIZE_SIZE_MASK 0X1FFFFFFC
/**
* Register: CSUDMA_CSUDMA_DST_STS
*/
#define CSUDMA_CSUDMA_DST_STS ( ( CSUDMA_BASEADDR ) + 0X00000808 )
#define CSUDMA_CSUDMA_DST_STS_DONE_CNT_SHIFT 13
#define CSUDMA_CSUDMA_DST_STS_DONE_CNT_WIDTH 3
#define CSUDMA_CSUDMA_DST_STS_DONE_CNT_MASK 0X0000E000
#define CSUDMA_CSUDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5
#define CSUDMA_CSUDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8
#define CSUDMA_CSUDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0
#define CSUDMA_CSUDMA_DST_STS_WR_OUTSTANDING_SHIFT 1
#define CSUDMA_CSUDMA_DST_STS_WR_OUTSTANDING_WIDTH 4
#define CSUDMA_CSUDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001E
#define CSUDMA_CSUDMA_DST_STS_BUSY_SHIFT 0
#define CSUDMA_CSUDMA_DST_STS_BUSY_WIDTH 1
#define CSUDMA_CSUDMA_DST_STS_BUSY_MASK 0X00000001
/**
* Register: CSUDMA_CSUDMA_DST_CTRL
*/
#define CSUDMA_CSUDMA_DST_CTRL ( ( CSUDMA_BASEADDR ) + 0X0000080C )
#define CSUDMA_CSUDMA_DST_CTRL_SSS_FIFOTHRESH_SHIFT 25
#define CSUDMA_CSUDMA_DST_CTRL_SSS_FIFOTHRESH_WIDTH 7
#define CSUDMA_CSUDMA_DST_CTRL_SSS_FIFOTHRESH_MASK 0XFE000000
#define CSUDMA_CSUDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24
#define CSUDMA_CSUDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1
#define CSUDMA_CSUDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000
#define CSUDMA_CSUDMA_DST_CTRL_ENDIANNESS_SHIFT 23
#define CSUDMA_CSUDMA_DST_CTRL_ENDIANNESS_WIDTH 1
#define CSUDMA_CSUDMA_DST_CTRL_ENDIANNESS_MASK 0X00800000
#define CSUDMA_CSUDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22
#define CSUDMA_CSUDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1
#define CSUDMA_CSUDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000
#define CSUDMA_CSUDMA_DST_CTRL_TIMEOUT_VAL_SHIFT 10
#define CSUDMA_CSUDMA_DST_CTRL_TIMEOUT_VAL_WIDTH 12
#define CSUDMA_CSUDMA_DST_CTRL_TIMEOUT_VAL_MASK 0X003FFC00
#define CSUDMA_CSUDMA_DST_CTRL_FIFO_THRESH_SHIFT 2
#define CSUDMA_CSUDMA_DST_CTRL_FIFO_THRESH_WIDTH 8
#define CSUDMA_CSUDMA_DST_CTRL_FIFO_THRESH_MASK 0X000003FC
#define CSUDMA_CSUDMA_DST_CTRL_PAUSE_STRM_SHIFT 1
#define CSUDMA_CSUDMA_DST_CTRL_PAUSE_STRM_WIDTH 1
#define CSUDMA_CSUDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002
#define CSUDMA_CSUDMA_DST_CTRL_PAUSE_MEM_SHIFT 0
#define CSUDMA_CSUDMA_DST_CTRL_PAUSE_MEM_WIDTH 1
#define CSUDMA_CSUDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001
/**
* Register: CSUDMA_CSUDMA_DST_I_STS
*/
#define CSUDMA_CSUDMA_DST_I_STS ( ( CSUDMA_BASEADDR ) + 0X00000814 )
#define CSUDMA_CSUDMA_DST_I_STS_FIFO_OVERFLOW_SHIFT 7
#define CSUDMA_CSUDMA_DST_I_STS_FIFO_OVERFLOW_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_STS_FIFO_OVERFLOW_MASK 0X00000080
#define CSUDMA_CSUDMA_DST_I_STS_INVALID_APB_SHIFT 6
#define CSUDMA_CSUDMA_DST_I_STS_INVALID_APB_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_STS_INVALID_APB_MASK 0X00000040
#define CSUDMA_CSUDMA_DST_I_STS_THRESH_HIT_SHIFT 5
#define CSUDMA_CSUDMA_DST_I_STS_THRESH_HIT_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_STS_THRESH_HIT_MASK 0X00000020
#define CSUDMA_CSUDMA_DST_I_STS_TIMEOUT_MEM_SHIFT 4
#define CSUDMA_CSUDMA_DST_I_STS_TIMEOUT_MEM_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_STS_TIMEOUT_MEM_MASK 0X00000010
#define CSUDMA_CSUDMA_DST_I_STS_TIMEOUT_STRM_SHIFT 3
#define CSUDMA_CSUDMA_DST_I_STS_TIMEOUT_STRM_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_STS_TIMEOUT_STRM_MASK 0X00000008
#define CSUDMA_CSUDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2
#define CSUDMA_CSUDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004
#define CSUDMA_CSUDMA_DST_I_STS_DONE_SHIFT 1
#define CSUDMA_CSUDMA_DST_I_STS_DONE_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_STS_DONE_MASK 0X00000002
/**
* Register: CSUDMA_CSUDMA_DST_I_EN
*/
#define CSUDMA_CSUDMA_DST_I_EN ( ( CSUDMA_BASEADDR ) + 0X00000818 )
#define CSUDMA_CSUDMA_DST_I_EN_FIFO_OVERFLOW_SHIFT 7
#define CSUDMA_CSUDMA_DST_I_EN_FIFO_OVERFLOW_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_EN_FIFO_OVERFLOW_MASK 0X00000080
#define CSUDMA_CSUDMA_DST_I_EN_INVALID_APB_SHIFT 6
#define CSUDMA_CSUDMA_DST_I_EN_INVALID_APB_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_EN_INVALID_APB_MASK 0X00000040
#define CSUDMA_CSUDMA_DST_I_EN_THRESH_HIT_SHIFT 5
#define CSUDMA_CSUDMA_DST_I_EN_THRESH_HIT_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_EN_THRESH_HIT_MASK 0X00000020
#define CSUDMA_CSUDMA_DST_I_EN_TIMEOUT_MEM_SHIFT 4
#define CSUDMA_CSUDMA_DST_I_EN_TIMEOUT_MEM_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_EN_TIMEOUT_MEM_MASK 0X00000010
#define CSUDMA_CSUDMA_DST_I_EN_TIMEOUT_STRM_SHIFT 3
#define CSUDMA_CSUDMA_DST_I_EN_TIMEOUT_STRM_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_EN_TIMEOUT_STRM_MASK 0X00000008
#define CSUDMA_CSUDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2
#define CSUDMA_CSUDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004
#define CSUDMA_CSUDMA_DST_I_EN_DONE_SHIFT 1
#define CSUDMA_CSUDMA_DST_I_EN_DONE_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_EN_DONE_MASK 0X00000002
/**
* Register: CSUDMA_CSUDMA_DST_I_DIS
*/
#define CSUDMA_CSUDMA_DST_I_DIS ( ( CSUDMA_BASEADDR ) + 0X0000081C )
#define CSUDMA_CSUDMA_DST_I_DIS_FIFO_OVERFLOW_SHIFT 7
#define CSUDMA_CSUDMA_DST_I_DIS_FIFO_OVERFLOW_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_DIS_FIFO_OVERFLOW_MASK 0X00000080
#define CSUDMA_CSUDMA_DST_I_DIS_INVALID_APB_SHIFT 6
#define CSUDMA_CSUDMA_DST_I_DIS_INVALID_APB_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040
#define CSUDMA_CSUDMA_DST_I_DIS_THRESH_HIT_SHIFT 5
#define CSUDMA_CSUDMA_DST_I_DIS_THRESH_HIT_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_DIS_THRESH_HIT_MASK 0X00000020
#define CSUDMA_CSUDMA_DST_I_DIS_TIMEOUT_MEM_SHIFT 4
#define CSUDMA_CSUDMA_DST_I_DIS_TIMEOUT_MEM_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_DIS_TIMEOUT_MEM_MASK 0X00000010
#define CSUDMA_CSUDMA_DST_I_DIS_TIMEOUT_STRM_SHIFT 3
#define CSUDMA_CSUDMA_DST_I_DIS_TIMEOUT_STRM_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_DIS_TIMEOUT_STRM_MASK 0X00000008
#define CSUDMA_CSUDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2
#define CSUDMA_CSUDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004
#define CSUDMA_CSUDMA_DST_I_DIS_DONE_SHIFT 1
#define CSUDMA_CSUDMA_DST_I_DIS_DONE_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_DIS_DONE_MASK 0X00000002
/**
* Register: CSUDMA_CSUDMA_DST_I_MASK
*/
#define CSUDMA_CSUDMA_DST_I_MASK ( ( CSUDMA_BASEADDR ) + 0X00000820 )
#define CSUDMA_CSUDMA_DST_I_MASK_FIFO_OVERFLOW_SHIFT 7
#define CSUDMA_CSUDMA_DST_I_MASK_FIFO_OVERFLOW_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_MASK_FIFO_OVERFLOW_MASK 0X00000080
#define CSUDMA_CSUDMA_DST_I_MASK_INVALID_APB_SHIFT 6
#define CSUDMA_CSUDMA_DST_I_MASK_INVALID_APB_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_MASK_INVALID_APB_MASK 0X00000040
#define CSUDMA_CSUDMA_DST_I_MASK_THRESH_HIT_SHIFT 5
#define CSUDMA_CSUDMA_DST_I_MASK_THRESH_HIT_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_MASK_THRESH_HIT_MASK 0X00000020
#define CSUDMA_CSUDMA_DST_I_MASK_TIMEOUT_MEM_SHIFT 4
#define CSUDMA_CSUDMA_DST_I_MASK_TIMEOUT_MEM_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_MASK_TIMEOUT_MEM_MASK 0X00000010
#define CSUDMA_CSUDMA_DST_I_MASK_TIMEOUT_STRM_SHIFT 3
#define CSUDMA_CSUDMA_DST_I_MASK_TIMEOUT_STRM_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_MASK_TIMEOUT_STRM_MASK 0X00000008
#define CSUDMA_CSUDMA_DST_I_MASK_AXI_BRESP_ERR_SHIFT 2
#define CSUDMA_CSUDMA_DST_I_MASK_AXI_BRESP_ERR_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_MASK_AXI_BRESP_ERR_MASK 0X00000004
#define CSUDMA_CSUDMA_DST_I_MASK_DONE_SHIFT 1
#define CSUDMA_CSUDMA_DST_I_MASK_DONE_WIDTH 1
#define CSUDMA_CSUDMA_DST_I_MASK_DONE_MASK 0X00000002
/**
* Register: CSUDMA_CSUDMA_DST_CTRL2
*/
#define CSUDMA_CSUDMA_DST_CTRL2 ( ( CSUDMA_BASEADDR ) + 0X00000824 )
#define CSUDMA_CSUDMA_DST_CTRL2_RAM_EMASA_SHIFT 27
#define CSUDMA_CSUDMA_DST_CTRL2_RAM_EMASA_WIDTH 1
#define CSUDMA_CSUDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000
#define CSUDMA_CSUDMA_DST_CTRL2_AWCACHE_SHIFT 24
#define CSUDMA_CSUDMA_DST_CTRL2_AWCACHE_WIDTH 3
#define CSUDMA_CSUDMA_DST_CTRL2_AWCACHE_MASK 0X07000000
#define CSUDMA_CSUDMA_DST_CTRL2_ROUTE_BIT_SHIFT 23
#define CSUDMA_CSUDMA_DST_CTRL2_ROUTE_BIT_WIDTH 1
#define CSUDMA_CSUDMA_DST_CTRL2_ROUTE_BIT_MASK 0X00800000
#define CSUDMA_CSUDMA_DST_CTRL2_TIMEOUT_EN_SHIFT 22
#define CSUDMA_CSUDMA_DST_CTRL2_TIMEOUT_EN_WIDTH 1
#define CSUDMA_CSUDMA_DST_CTRL2_TIMEOUT_EN_MASK 0X00400000
#define CSUDMA_CSUDMA_DST_CTRL2_RAM_EMAB_SHIFT 19
#define CSUDMA_CSUDMA_DST_CTRL2_RAM_EMAB_WIDTH 3
#define CSUDMA_CSUDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000
#define CSUDMA_CSUDMA_DST_CTRL2_RAM_EMAA_SHIFT 16
#define CSUDMA_CSUDMA_DST_CTRL2_RAM_EMAA_WIDTH 3
#define CSUDMA_CSUDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000
#define CSUDMA_CSUDMA_DST_CTRL2_TIMEOUT_PRE_SHIFT 4
#define CSUDMA_CSUDMA_DST_CTRL2_TIMEOUT_PRE_WIDTH 12
#define CSUDMA_CSUDMA_DST_CTRL2_TIMEOUT_PRE_MASK 0X0000FFF0
#define CSUDMA_CSUDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0
#define CSUDMA_CSUDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4
#define CSUDMA_CSUDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000F
/**
* Register: CSUDMA_CSUDMA_DST_ADDR_MSB
*/
#define CSUDMA_CSUDMA_DST_ADDR_MSB ( ( CSUDMA_BASEADDR ) + 0X00000828 )
#define CSUDMA_CSUDMA_DST_ADDR_MSB_ADDR_MSB_SHIFT 0
#define CSUDMA_CSUDMA_DST_ADDR_MSB_ADDR_MSB_WIDTH 17
#define CSUDMA_CSUDMA_DST_ADDR_MSB_ADDR_MSB_MASK 0X0001FFFF
/**
* Register: CSUDMA_CSUDMA_SAFETY_CHK
*/
#define CSUDMA_CSUDMA_SAFETY_CHK ( ( CSUDMA_BASEADDR ) + 0X00000FF8 )
#define CSUDMA_CSUDMA_SAFETY_CHK_CHK_VAL_SHIFT 0
#define CSUDMA_CSUDMA_SAFETY_CHK_CHK_VAL_WIDTH 32
#define CSUDMA_CSUDMA_SAFETY_CHK_CHK_VAL_MASK 0XFFFFFFFF
/**
* Register: CSUDMA_CSUDMA_FUTURE_ECO
*/
#define CSUDMA_CSUDMA_FUTURE_ECO ( ( CSUDMA_BASEADDR ) + 0X00000FFC )
#define CSUDMA_CSUDMA_FUTURE_ECO_VAL_SHIFT 0
#define CSUDMA_CSUDMA_FUTURE_ECO_VAL_WIDTH 32
#define CSUDMA_CSUDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFF
#ifdef __cplusplus
}
#endif
#endif /* _CSUDMA_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_gpp.c
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#include "xpfw_config.h"
#ifdef ENABLE_PM
/*********************************************************************
* GPU Pixel Processors slaves FSM implementation
*********************************************************************/
#include "pm_gpp.h"
#include "pm_common.h"
#include "pm_power.h"
#include "xpfw_rom_interface.h"
/* A GPP has its own power islands and dependencies to the FPD power parent */
#define PM_GPP_SLAVE_STATE_OFF 0U
#define PM_GPP_SLAVE_STATE_ON 1U
static const u8 pmGppStates[] = {
[PM_GPP_SLAVE_STATE_OFF] = 0U,
[PM_GPP_SLAVE_STATE_ON] = PM_CAP_ACCESS | PM_CAP_CONTEXT | PM_CAP_POWER,
};
/* GPP slave transitions (from which to which state slave can transits) */
static const PmStateTran pmGppTransitions[] = {
{
.fromState = PM_GPP_SLAVE_STATE_ON,
.toState = PM_GPP_SLAVE_STATE_OFF,
.latency = PM_DEFAULT_LATENCY,
}, {
.fromState = PM_GPP_SLAVE_STATE_OFF,
.toState = PM_GPP_SLAVE_STATE_ON,
.latency = PM_DEFAULT_LATENCY,
},
};
/**
* PmGppFsmHandler() - FSM handler of a GPP slave
* @slave Slave whose state should be changed
* @nextState State the slave should enter
*
* @return Status of performing transition action
*/
static s32 PmGppFsmHandler(PmSlave* const slave, const PmStateId nextState)
{
s32 status = XST_PM_INTERNAL;
PmSlaveGpp* gpp = (PmSlaveGpp*)slave->node.derived;
switch (slave->node.currState) {
case PM_GPP_SLAVE_STATE_ON:
if (PM_GPP_SLAVE_STATE_OFF == nextState) {
/* ON -> OFF*/
status = gpp->PwrDn();
} else {
status = XST_NO_FEATURE;
}
break;
case PM_GPP_SLAVE_STATE_OFF:
if (PM_GPP_SLAVE_STATE_ON == nextState) {
/* OFF -> ON */
status = gpp->PwrUp();
if ((XST_SUCCESS == status) && (NULL != gpp->reset)) {
status = gpp->reset();
}
} else {
status = XST_NO_FEATURE;
}
break;
default:
PmNodeLogUnknownState(&slave->node, slave->node.currState);
break;
}
return status;
}
static const PmSlaveFsm pmSlaveGppFsm = {
DEFINE_SLAVE_STATES(pmGppStates),
DEFINE_SLAVE_TRANS(pmGppTransitions),
.enterState = PmGppFsmHandler,
};
static u8 pmGppSlavePowers[] = {
DEFAULT_POWER_OFF,
DEFAULT_POWER_ON,
};
PmSlaveGpp pmSlaveGpuPP0_g = {
.slv = {
.node = {
.derived = &pmSlaveGpuPP0_g,
.nodeId = NODE_GPU_PP_0,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_GPP_SLAVE_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGppSlavePowers),
DEFINE_NODE_NAME("gpupp0"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmSlaveGppFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnPp0Handler,
.PwrUp = XpbrPwrUpPp0Handler,
.reset = XpbrRstPp0Handler,
};
PmSlaveGpp pmSlaveGpuPP1_g = {
.slv = {
.node = {
.derived = &pmSlaveGpuPP1_g,
.nodeId = NODE_GPU_PP_1,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_GPP_SLAVE_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGppSlavePowers),
DEFINE_NODE_NAME("gpupp1"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmSlaveGppFsm,
.flags = 0U,
},
.PwrDn = XpbrPwrDnPp1Handler,
.PwrUp = XpbrPwrUpPp1Handler,
.reset = XpbrRstPp1Handler,
};
/**
* PmGpuFsmHandler() - FSM handler of a GPU slave
* @slave Slave whose state should be changed
* @nextState State the slave should enter
*
* @return Status of performing transition action
*/
static s32 PmGpuFsmHandler(PmSlave* const slave, const PmStateId nextState)
{
s32 status = XST_PM_INTERNAL;
switch (slave->node.currState) {
case PM_GPP_SLAVE_STATE_ON:
if (PM_GPP_SLAVE_STATE_OFF == nextState) {
/* ON -> OFF*/
status = pmSlaveGpuPP0_g.PwrDn();
if (XST_SUCCESS != status) {
goto done;
}
status = pmSlaveGpuPP1_g.PwrDn();
if (XST_SUCCESS != status) {
goto done;
}
} else {
status = XST_NO_FEATURE;
}
break;
case PM_GPP_SLAVE_STATE_OFF:
if (PM_GPP_SLAVE_STATE_ON == nextState) {
/* OFF -> ON */
status = pmSlaveGpuPP0_g.PwrUp();
if ((XST_SUCCESS == status) && (NULL != pmSlaveGpuPP0_g.reset)) {
status = pmSlaveGpuPP0_g.reset();
}
if (XST_SUCCESS != status) {
goto done;
}
status = pmSlaveGpuPP1_g.PwrUp();
if ((XST_SUCCESS == status) && (NULL != pmSlaveGpuPP1_g.reset)) {
status = pmSlaveGpuPP1_g.reset();
}
if (XST_SUCCESS != status) {
goto done;
}
} else {
status = XST_NO_FEATURE;
}
break;
default:
PmNodeLogUnknownState(&slave->node, slave->node.currState);
break;
}
done:
return status;
}
static const PmSlaveFsm pmSlaveGpuFsm = {
DEFINE_SLAVE_STATES(pmGppStates),
DEFINE_SLAVE_TRANS(pmGppTransitions),
.enterState = PmGpuFsmHandler,
};
PmSlave pmSlaveGpu_g = {
.node = {
.derived = &pmSlaveGpu_g,
.nodeId = NODE_GPU,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainFpd_g.power,
.clocks = NULL,
.currState = PM_GPP_SLAVE_STATE_ON,
.latencyMarg = MAX_LATENCY,
.flags = 0U,
DEFINE_PM_POWER_INFO(pmGppSlavePowers),
DEFINE_NODE_NAME("gpu"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmSlaveGpuFsm,
.flags = 0U,
};
#pragma weak pmUserHookVcuPwrDn
u32 pmUserHookVcuPwrDn(void)
{
return XST_SUCCESS;
}
#pragma weak pmUserHookVcuPwrUp
u32 pmUserHookVcuPwrUp(void)
{
return XST_SUCCESS;
}
static u32 pmSlvVcuPwrDn(void)
{
return pmUserHookVcuPwrDn();
}
static u32 pmSlvVcuPwrUp(void)
{
return pmUserHookVcuPwrUp();
}
PmSlaveGpp pmSlaveVcu_g = {
.slv = {
.node = {
.derived = &pmSlaveVcu_g,
.nodeId = NODE_VCU,
.class = &pmNodeClassSlave_g,
.parent = &pmPowerDomainPld_g.power,
.clocks = NULL,
.currState = PM_GPP_SLAVE_STATE_ON,
.latencyMarg = MAX_LATENCY,
DEFINE_PM_POWER_INFO(pmGppSlavePowers),
DEFINE_NODE_NAME("vcu"),
},
.class = NULL,
.reqs = NULL,
.wake = NULL,
.slvFsm = &pmSlaveGppFsm,
.flags = 0U,
},
.PwrDn = pmSlvVcuPwrDn,
.PwrUp = pmSlvVcuPwrUp,
.reset = NULL,
};
#endif
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilsecure_v4_2/src/versal/xsecure_ecdsa.h
/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_ecdsa.h
* @addtogroup xsecure_ecdsa_apis XilSecure ECDSA APIs
* @{
* @cond xsecure_internal
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.0 vns 03/27/19 First Release
* 4.2 har 11/07/19 Typo correction to enable compilation in C++
*
* </pre>
*
* @endcond
******************************************************************************/
#ifndef XSECURE_ECDSA_H_
#define XSECURE_ECDSA_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xsecure_utils.h"
/************************** Constant Definitions ****************************/
#define XSECURE_ECC_DATA_SIZE_WORDS (12U)
/***************************** Type Definitions ******************************/
/***************************** Function Prototypes ***************************/
/*****************************************************************************/
/**
* @brief
* This function validates public key for p384 curve.
*
* @param Qx Pointer to the x co-ordinate of ECC point.
* @param Qy Pointer to the y co-ordinate of ECC point.
*
* @return XST_SUCCESS if verification was successful.
*
*
******************************************************************************/
int P384_validatekey(unsigned char *Qx, unsigned char *Qy);
/*****************************************************************************/
/**
* @brief
* This function verifies ECDSA signature(r,s) of the hash 'z'
* (truncated to the group order size) using the public key 'Q'
*
* @param Z Pointer to the expected hash of the signed data.
* @param Qx Pointer to the x co-ordinate of ECC point.
* @param Qy Pointer to the y co-ordinate of ECC point.
* @param r Pointer to the r component of signature pair (r,s)
* @param s Pointer to the s component of signature pair (r,s)
*
* @return XST_SUCCESS if verification was successful.
*
*
******************************************************************************/
int P384_ecdsaverify(unsigned char *z, unsigned char *Qx,
unsigned char *Qy, unsigned char *r, unsigned char *s);
u32 XSecure_EcdsaKat(void);
#ifdef __cplusplus
}
#endif
#endif
/* @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_master.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* This file contains PM master related data structures and
* functions for accessing them.
*********************************************************************/
#ifndef PM_MASTER_H_
#define PM_MASTER_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_slave.h"
#include "pm_common.h"
#include "pm_proc.h"
#include "pm_node.h"
#include "pm_power.h"
#include "xil_types.h"
#include "pm_gic_proxy.h"
typedef struct PmMaster PmMaster;
typedef struct PmRequirement PmRequirement;
/*********************************************************************
* Enum definitions
********************************************************************/
typedef enum {
PM_MASTER_EVENT_WAKE,
PM_MASTER_EVENT_SLEEP,
PM_MASTER_EVENT_SELF_SUSPEND,
PM_MASTER_EVENT_ABORT_SUSPEND,
PM_MASTER_EVENT_FORCED_PROC,
PM_MASTER_EVENT_FORCE_DOWN,
} PmMasterEvent;
/*********************************************************************
* Macros
********************************************************************/
/* Master state definitions */
/* Master is active if at least one of its processors is in active state */
#define PM_MASTER_STATE_ACTIVE 1U
/* Master is suspending if the last awake processor is in suspending state */
#define PM_MASTER_STATE_SUSPENDING 2U
/* Master is suspended if the last standing processor was properly suspended */
#define PM_MASTER_STATE_SUSPENDED 3U
/*
* Master is killed if the last standing processor or the power parent was
* forced to power down
*/
#define PM_MASTER_STATE_KILLED 4U
/* Master has not sent notification that it has initialized PM */
#define PM_MASTER_STATE_UNINITIALIZED 5U
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmSuspendRequest() - For tracking information about request suspend being
* processed at the moment
* @initiator Master which has requested suspend
* @acknowledge Acknowledge argument provided with the request suspend call
*/
typedef struct {
const PmMaster* initiator;
u32 acknowledge;
} PmSuspendRequest;
/**
* PmMaster - contains PM master related information
* @procs Pointer to the array of processors within the master
* @wakeProc Processor to wake-up (pointer to the processor that has been
* suspended the last)
* @reqs Pointer to the master's list of requirements for slaves'
* capabilities. For every slave that the master can use there has
* to be a dedicated requirements structure
* @nextMaster Pointer to the next used master in the system
* @gic If the master has its own GIC which is controlled by the PMU,
* this is a pointer to it.
* @evalState Function to be called when a state specified by the master
* needs to be evaluated (implicit scheduling of requirements)
* @remapAddr Remap address (used when master's and PMU's memory map differ)
* @memories Pointer to the array of memories used by the master
* @ipiMask Mask dedicated to the master in IPI registers
* @nid Placeholder nodeId - used to encode request suspend for group of
* processors sharing the same communication channel. When PM
* receives this nid as request suspend argument, it initiates
* init suspend to the master. At the PU, in init_suspend_cb
* implementation, the request is mappend to actual suspend of all
* processors in the PU. In RPU case, this data could be
* initialized from PCW, based on RPU configuration.
* @procsCnt Number of processors within the master
* @wakePerms ORed ipi masks of masters which can wake-up this master
* @suspendPerms ORed ipi masks of masters which can request this master to
* suspend
* @suspendRequest Captures info about the ongoing suspend request (this master
* is the target which suppose to suspend). At any moment only
* one suspend request can be active for one target/master
* @suspendTimeout Timeout which specifies how much time the master has to
* complete suspend, otherwise it is considered to be unresponsive
* @state State of the master which is a combination of the states of its
* processors and also depends on the order in which processors
* enter their states.
* @name Master name
*/
typedef struct PmMaster {
PmSuspendRequest suspendRequest;
PmProc** const procs;
PmProc* wakeProc;
PmRequirement* reqs;
PmMaster* nextMaster;
const PmGicProxy* const gic;
s32 (*const evalState)(const u32 state);
u32 (*const remapAddr)(const u32 address);
const PmSlave** const memories;
const char* const name;
u32 ipiMask;
u32 wakePerms;
u32 suspendPerms;
u32 suspendTimeout;
PmNodeId nid;
const u8 procsCnt;
u8 state;
} PmMaster;
/**
* PmMasterConfig - Structure to store master configuration data
* @ipiMask IPI mask assigned to the master
* @suspendTimeout Master's suspend timeout
* @suspendPerms Permissions to request suspend of other masters
* @wakePerms Permissions to request wake of other masters
*/
typedef struct PmMasterConfig {
u32 ipiMask;
u32 suspendTimeout;
u32 suspendPerms;
u32 wakePerms;
} PmMasterConfig;
/*********************************************************************
* Global data declarations
********************************************************************/
extern PmMaster pmMasterApu_g;
extern PmMaster pmMasterRpu_g;
extern PmMaster pmMasterRpu0_g;
extern PmMaster pmMasterRpu1_g;
/*********************************************************************
* Function declarations
********************************************************************/
/* Get functions */
PmMaster* PmGetMasterByIpiMask(const u32 mask);
PmMaster* PmMasterGetNextFromIpiMask(u32* const mask);
PmProc* PmGetProcByWfiStatus(const u32 mask);
PmProc* PmGetProcOfThisMaster(const PmMaster* const master,
const PmNodeId nodeId);
s32 PmMasterWakeProc(PmProc* const proc);
s32 PmMasterFsm(PmMaster* const master, const PmMasterEvent event);
s32 PmMasterRestart(PmMaster* const master);
s32 PmMasterInitFinalize(PmMaster* const master);
void PmMasterDefaultConfig(void);
void PmMasterSetConfig(PmMaster* const mst, const PmMasterConfig* const cfg);
void PmMasterClearConfig(void);
#ifdef IDLE_PERIPHERALS
void PmMasterIdleSystem(void);
#endif
bool PmCanRequestSuspend(const PmMaster* const reqMaster,
const PmMaster* const respMaster);
bool PmIsRequestedToSuspend(const PmMaster* const master);
s32 PmMasterSuspendAck(PmMaster* const mst, const s32 response);
PmMaster* PmMasterGetPlaceholder(const PmNodeId nodeId);
s32 PmMasterWake(const PmMaster* const mst);
s32 PmWakeMasterBySlave(const PmSlave * const slave);
/* Inline functions for checking the state of the master */
static inline bool PmMasterIsSuspending(const PmMaster* const master)
{
return PM_MASTER_STATE_SUSPENDING == master->state;
}
static inline bool PmMasterIsSuspended(const PmMaster* const master)
{
return PM_MASTER_STATE_SUSPENDED == master->state;
}
static inline bool PmMasterIsKilled(const PmMaster* const master)
{
return PM_MASTER_STATE_KILLED == master->state;
}
static inline bool PmMasterIsActive(const PmMaster* const master)
{
return PM_MASTER_STATE_ACTIVE == master->state;
}
static inline bool PmMasterCanReceiveCb(const PmMaster* const master)
{
return (PM_MASTER_STATE_KILLED != master->state) &&
(PM_MASTER_STATE_UNINITIALIZED != master->state);
}
/**
* PmMasterCanRequestWake() - Check if master has permissions to request wake
* @requestor Master which requested wake
* @target Target master to wake
*
* @return True if master has permission to request wake, false otherwise
*/
static inline bool PmMasterCanRequestWake(const PmMaster* const requestor,
const PmMaster* const target)
{
return 0U != (requestor->ipiMask & target->wakePerms);
}
bool PmMasterCanForceDown(const PmMaster* const master,
const PmPower* const power);
bool PmMasterIsLastSuspending(const PmMaster* const master);
bool PmMasterIsUniqueWakeup(const PmSlave* const slave);
s32 PmMasterReleaseAll(void);
#ifdef __cplusplus
}
#endif
#endif /* PM_MASTER_H_ */
<file_sep>/notes.txt
Settings for 8/25/2020
Getting 352k counts on Ch1, 530k on Ch2
Coincidence is 13k
Laser power: 6dBm Id photonics laser
EDFA: 371.3mW with bias off
I1 = 550mA
I2 = 2.834A
R_SHG = 2.3kOhms
T_spdc = 56.17 - 56.23
Pulse length was 250ps * 64<file_sep>/python_drivers/decode_alg_raw_data_test.py
# -*- coding: utf-8 -*-
"""
Created on Fri Aug 28 12:16:06 2020
@author: tianlab01
"""
#expected_period = 500000
#expected_period = 653059
expected_period = 750000
expected_bin_num = 4
expected_bin_size = 100000
expected_num_sync_pulses = 100
import james_utils as ju
import matplotlib.pyplot as plt
import mplcursors
f = open("pulse_stream_test.txt", "r")
lines = f.readlines()
pulse_lists = []
for l in lines:
p_str_list = l.split(",")
pl = []
for p in p_str_list:
try:
pl.append(int(p))
except:
print("Line end")
pulse_lists.append(pl)
for pl in pulse_lists:
pl_dupe = pl.copy()
decoded_vals, bin_starts, last_sync_pulse_timestamp, entangled_timestamp, valid_sync_pulse_timestamps = ju.decode_pulse_list(pl, expected_period, expected_bin_num, expected_bin_size, expected_num_sync_pulses)
decode_str = "Decoded: "
for d in decoded_vals:
if(d < 20):
decode_str += str(d) + ","
elif (d == ju.FAIL_TIMESTAMP_BAD_RANGE):
decode_str += "br,"
elif (d == ju.FAIL_TIMESTAMP_NO_PHOTON):
decode_str += "np,"
else:
decode_str += ".,"
print(decode_str)
pl = ju.remove_duplicate_pulses(pl, expected_period)
#pl = pl_dupe
first_small_delay = 0
sec = 0
consecutives = 0
pl.sort()
for i in range(0, len(pl)-1):
if(consecutives > 7):
print("Pulses start at i = " + str(i))
first_small_delay = pl[i]
sec = pl[i+1]
break
if(abs(pl[i+1] - pl[i]) < expected_period*3):
consecutives += 1
else:
consecutives = 0
print("Diff was " + str(sec - first_small_delay))
pl_y = []
bs_y = []
vspt = []
for p in pl:
pl_y.append(1)
if(len(decode_str) > 20):
for b in bin_starts:
bs_y.append(1)
for v in valid_sync_pulse_timestamps:
vspt.append(1)
fig = plt.figure()
plt.scatter(pl, pl_y, color='blue', label="Timestamps")
plt.scatter([first_small_delay, sec], [1,1], color='black', label="First Small Delay")
if(len(decode_str) > 20):
plt.scatter(bin_starts, bs_y, color='red', label="Bin Starts")
plt.scatter(valid_sync_pulse_timestamps, vspt, color='orange', label="Valid Sync Pulses")
plt.scatter([last_sync_pulse_timestamp], [1], color='green', label="Sync end")
axes = plt.gca()
#axes.set_xlim([-1,1])
#axes.set_ylim([-1500,1500])
axes.legend()
#plt.xlabel('B(T)',fontsize=16)
#plt.ylabel('R(Ω)',fontsize=16)
#fig.canvas.mpl_connect('motion_notify_event', on_plot_hover)
mplcursors.cursor(hover=True)
plt.show()
#a = input("Continue?")
#plt.clf()
break
<file_sep>/python_drivers/bob_test_run.py
# -*- coding: utf-8 -*-
"""
Created on Wed Jul 1 11:53:50 2020
@author: tianlab01
"""
import time_sync
import james_utils
import tdc_wrapper
tdc = tdc_wrapper.tdc_wrapper(3,0,tdc_wrapper.MODE_CLIENT,"192.168.56.1")
home_ip = ""
ts = time_sync.time_sync(james_utils.BOB_PORT, home_ip, time_sync.SERVER, tdc)
ts.start_server()
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/xpfw_crc.c
/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xpfw_config.h"
#include "xpfw_crc.h"
#ifdef ENABLE_IPI_CRC
/*****************************************************************************/
/**
*
* This function calculates the CRC for the data
*
* @param BufAddr - buffer on which CRC is calculated
* @param BufSize - size of the buffer
*
* @return Checksum - 16 bit CRC value
*
* @note None.
*
******************************************************************************/
u32 XPfw_CalculateCRC(u32 BufAddr, u32 BufSize)
{
const u32 CrcInit = 0x4F4EU;
const u32 Order = 16U;
const u32 Polynom = 0x8005U;
u32 i;
u32 j;
u32 c;
u32 Bit;
u32 Crc = CrcInit;
u32 DataIn;
u32 CrcMask, CrcHighBit;
CrcMask = ((u32)(((u32)1 << (Order - (u32)1)) -(u32)1) << (u32)1) | (u32)1;
CrcHighBit = (u32)((u32)1 << (Order - (u32)1));
for(i = 0U; i < BufSize; i++) {
DataIn = Xil_In8(BufAddr + i);
c = (u32)DataIn;
j = 0x80U;
while(j != 0U) {
Bit = Crc & CrcHighBit;
Crc <<= 1U;
if((c & j) != 0U) {
Bit ^= CrcHighBit;
}
if(Bit != 0U) {
Crc ^= Polynom;
}
j >>= 1U;
}
Crc &= CrcMask;
}
return Crc;
}
#endif /* ENABLE_IPI_CRC */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/iicps_v3_11/src/xiicps_selftest.c
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_selftest.c
* @addtogroup iicps_v3_11
* @{
*
* This component contains the implementation of selftest functions for the
* XIicPs driver component.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------
* 1.00a drg/jz 01/30/10 First release
* 1.00a sdm 09/22/11 Removed unused code
* 3.0 sk 11/03/14 Removed TimeOut Register value check
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xiicps.h"
/************************** Constant Definitions *****************************/
#define REG_TEST_VALUE 0x00000005U
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* @brief
* Runs a self-test on the driver/device. The self-test is destructive in that
* a reset of the device is performed in order to check the reset values of
* the registers and to get the device into a known state.
*
* Upon successful return from the self-test, the device is reset.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @return
* - XST_SUCCESS if successful.
* - XST_REGISTER_ERROR indicates a register did not read or write
* correctly
*
* @note None.
*
******************************************************************************/
s32 XIicPs_SelfTest(XIicPs *InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/*
* All the IIC registers should be in their default state right now.
*/
if ((XIICPS_CR_RESET_VALUE !=
XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET)) ||
(XIICPS_IXR_ALL_INTR_MASK !=
XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_IMR_OFFSET))) {
return (s32)XST_FAILURE;
}
XIicPs_Reset(InstancePtr);
/*
* Write, Read then write a register
*/
XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_SLV_PAUSE_OFFSET)) {
return (s32)XST_FAILURE;
}
XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
XIICPS_SLV_PAUSE_OFFSET, 0U);
XIicPs_Reset(InstancePtr);
return (s32)XST_SUCCESS;
}
/** @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilpm_v3_1/src/versal/server/xpm_device.h
/******************************************************************************
* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPM_DEVICE_H_
#define XPM_DEVICE_H_
#include "xpm_node.h"
#include "xpm_power.h"
#include "xpm_clock.h"
#include "xpm_reset.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DDRMC_DEVID(IDX) NODEID((u32)XPM_NODECLASS_DEVICE, \
(u32)XPM_NODESUBCL_DEV_MEM_CTRLR, \
(u32)XPM_NODETYPE_DEV_DDR, (IDX))
#define GT_DEVID(IDX) NODEID((u32)XPM_NODECLASS_DEVICE, \
(u32)XPM_NODESUBCL_DEV_PHY, \
(u32)XPM_NODETYPE_DEV_GT, (IDX))
#define DEFINE_DEV_STATES(S) .States = (S), \
.StatesCnt = ARRAY_SIZE(S)
#define DEFINE_DEV_TRANS(T) .Trans = (T), \
.TransCnt = ARRAY_SIZE(T)
#define DEVICE_NO_IDLE_REQ (0U)
#define DEVICE_IDLE_REQ (1U)
/* Device states */
typedef enum {
XPM_DEVSTATE_UNUSED,
XPM_DEVSTATE_RUNNING,
XPM_DEVSTATE_PWR_ON, /* Power up the island/domain */
XPM_DEVSTATE_CLK_ON, /* Enable clock */
XPM_DEVSTATE_RST_OFF, /* De-assert reset */
XPM_DEVSTATE_RST_ON, /* Assert reset */
XPM_DEVSTATE_CLK_OFF, /* Disable clock */
XPM_DEVSTATE_PWR_OFF, /* Power down */
XPM_DEVSTATE_SUSPENDING,
XPM_DEVSTATE_RUNTIME_SUSPEND,
} XPm_DeviceState;
/* Device events */
typedef enum {
XPM_DEVEVENT_BRINGUP_ALL,
XPM_DEVEVENT_BRINGUP_CLKRST,
XPM_DEVEVENT_SHUTDOWN,
XPM_DEVEVENT_TIMER,
XPM_DEVEVENT_RUNTIME_SUSPEND,
} XPm_DeviceEvent;
typedef struct XPm_DeviceNode XPm_Device;
typedef struct XPm_DeviceOps XPm_DeviceOps;
/* Device Operations */
struct XPm_DeviceOps {
XStatus (*Request)(XPm_Device *Device, XPm_Subsystem *Subsystem,
u32 Capabilities, const u32 QoS);
/**< Request: Request the device */
XStatus (*SetRequirement)(XPm_Device *Device,
XPm_Subsystem *Subsystem,
u32 Capabilities, const u32 QoS);
/**< SetRequirement: Set the device requirement */
XStatus (*Release)(XPm_Device *Device,
XPm_Subsystem *Subsystem);
/**< Release: Release the device */
};
/* Transition for a state in finite state machine */
typedef struct {
const u32 Latency; /**< Transition latency in microseconds */
const u32 FromState; /**< From which state the transition is taken */
const u32 ToState; /**< To which state the transition is taken */
} XPm_StateTran;
/* Device capability in each state */
typedef struct {
const u8 State; /**< Device state */
const u32 Cap; /**< Capability associated with state */
} XPm_StateCap;
/* Device Finite state machine */
typedef struct {
const XPm_StateCap* const States; /**< Pointer to states array. */
XStatus (*const EnterState)(XPm_Device* const Device, const u32 NextState);
/**< Pointer to a function that executes FSM actions to enter a state*/
const XPm_StateTran* const Trans;
/**< Pointer to array of transitions of the FSM */
const u8 StatesCnt; /**< Number of elements in states array */
const u8 TransCnt; /**< Number of elements in transition array */
} XPm_DeviceFsm;
/**
* The device class. This is the base class for all the processor core,
* memory bank and peripheral classes.
*/
struct XPm_DeviceNode {
XPm_Node Node; /**< Node: Base class */
XPm_Power *Power; /**< Device power node */
XPm_ClockHandle *ClkHandles; /**< Head of the list of device clocks */
XPm_ResetHandle *RstHandles; /**< Head of the list device resets */
struct XPm_Reqm *Requirements;
/**< Head of the list of requirements for all subsystems */
struct XPm_Reqm *PendingReqm; /**< Requirement being updated */
u8 WfDealloc; /**< Deallocation is pending */
u8 WfPwrUseCnt; /**< Pending power use count */
XPm_DeviceOps *DeviceOps; /**< Device operations */
const XPm_DeviceFsm* DeviceFsm; /**< Device finite state machine */
XStatus (* HandleEvent)(XPm_Node *Node, u32 Event);
/**< HandleEvent: Pointer to event handler */
};
/************************** Function Prototypes ******************************/
XStatus XPmDevice_Init(XPm_Device *Device,
u32 Id,
u32 BaseAddress,
XPm_Power *Power, XPm_ClockNode *Clock, XPm_ResetNode *Reset);
XStatus XPmDevice_AddClock(XPm_Device *Device, XPm_ClockNode *Clock);
XStatus XPmDevice_AddReset(XPm_Device *Device, XPm_ResetNode *Reset);
XStatus XPmDevice_Reset(XPm_Device *Device, const XPm_ResetActions Action);
int XPmDevice_CheckPermissions(XPm_Subsystem *Subsystem, u32 DeviceId);
XPm_Device *XPmDevice_GetById(const u32 DeviceId);
XPm_Device *XPmDevice_GetByIndex(const u32 DeviceIndex);
XPm_Device *XPmDevice_GetPlDeviceByIndex(const u32 DeviceIndex);
XStatus XPm_CheckCapabilities(XPm_Device *Device, u32 Caps);
XStatus XPmDevice_Request(const u32 SubsystemId, const u32 DeviceId,
const u32 Capabilities, const u32 QoS);
XStatus XPmDevice_Release(const u32 SubsystemId, const u32 DeviceId);
XStatus XPmDevice_SetRequirement(const u32 SubsystemId, const u32 DeviceId,
const u32 Capabilities, const u32 QoS);
struct XPm_Reqm *XPmDevice_FindRequirement(const u32 DeviceId,
const u32 SubsystemId);
XStatus XPmDevice_GetStatus(const u32 SubsystemId,
const u32 DeviceId,
XPm_DeviceStatus *const DeviceStatus);
XStatus XPmDevice_AddParent(u32 Id, u32 *Parents, u32 NumParents);
XStatus XPmDevice_GetPermissions(XPm_Device *Device, u32 *PermissionMask);
u32 XPmDevice_GetSubsystemIdOfCore(XPm_Device *Device);
int XPmDevice_SetMaxLatency(const u32 SubsystemId, const u32 DeviceId,
const u32 Latency);
XStatus XPmDevice_ChangeState(XPm_Device *Device, const u32 NextState);
XStatus XPmDevice_UpdateStatus(XPm_Device *Device);
XStatus XPmDevice_BringUp(XPm_Device *Device);
u32 XPmDevice_GetUsageStatus(XPm_Subsystem *Subsystem, XPm_Device *Device);
int XPmDevice_IsClockActive(XPm_Device *Device);
int XPmDevice_IsRequested(const u32 DeviceId, const u32 SubsystemId);
int XPmDevice_GetWakeupLatency(const u32 DeviceId, u32 *Latency);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* XPM_DEVICE_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_usb.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
/*********************************************************************
* USB slaves data structures
*********************************************************************/
#ifndef PM_USB_H_
#define PM_USB_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_slave.h"
#include "xpfw_aib.h"
/*********************************************************************
* Structure definitions
********************************************************************/
/**
* PmSlaveUsb - Structure used for Usb
* @slv Base slave structure
* @PwrDn Pointer to a power down pmu-rom handler
* @PwrUp Pointer to a power up pmu-rom handler
* @rstId USB reset ID
*/
typedef struct PmSlaveUsb {
PmSlave slv;
PmTranHandler PwrDn;
PmTranHandler PwrUp;
const u32 rstId;
const enum XPfwAib aibId;
} PmSlaveUsb;
/*********************************************************************
* Global data declarations
********************************************************************/
extern PmSlaveUsb pmSlaveUsb0_g;
extern PmSlaveUsb pmSlaveUsb1_g;
#ifdef __cplusplus
}
#endif
#endif /* PM_USB_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/pm_periph.h
/*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*/
#ifndef PM_PERIPH_H_
#define PM_PERIPH_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "pm_slave.h"
/*********************************************************************
* Global data declarations
********************************************************************/
extern PmSlave pmSlaveTtc0_g;
extern PmSlave pmSlaveTtc1_g;
extern PmSlave pmSlaveTtc2_g;
extern PmSlave pmSlaveTtc3_g;
extern PmSlave pmSlaveSata_g;
extern PmSlave pmSlaveUart0_g;
extern PmSlave pmSlaveUart1_g;
extern PmSlave pmSlaveSpi0_g;
extern PmSlave pmSlaveSpi1_g;
extern PmSlave pmSlaveI2C0_g;
extern PmSlave pmSlaveI2C1_g;
extern PmSlave pmSlaveSD0_g;
extern PmSlave pmSlaveSD1_g;
extern PmSlave pmSlaveCan0_g;
extern PmSlave pmSlaveCan1_g;
extern PmSlave pmSlaveEth0_g;
extern PmSlave pmSlaveEth1_g;
extern PmSlave pmSlaveEth2_g;
extern PmSlave pmSlaveEth3_g;
extern PmSlave pmSlaveAdma_g;
extern PmSlave pmSlaveGdma_g;
extern PmSlave pmSlaveDP_g;
extern PmSlave pmSlaveNand_g;
extern PmSlave pmSlaveQSpi_g;
extern PmSlave pmSlaveGpio_g;
extern PmSlave pmSlaveIpiApu_g;
extern PmSlave pmSlaveIpiRpu0_g;
extern PmSlave pmSlaveIpiRpu1_g;
extern PmSlave pmSlaveIpiPl0_g;
extern PmSlave pmSlaveIpiPl1_g;
extern PmSlave pmSlaveIpiPl2_g;
extern PmSlave pmSlaveIpiPl3_g;
extern PmSlave pmSlaveGpu_g;
extern PmSlave pmSlavePcie_g;
extern PmSlave pmSlavePcap_g;
extern PmSlave pmSlaveRtc_g;
extern PmSlave pmSlavePl_g;
extern PmSlave pmSlaveFpdWdt_g;
/**
* PmWakeEventEth - Ethernet wake event, derived from PmWakeEvent
* @wake Basic PmWakeEvent structure
* @baseAddr Base Address of Ethernet
* @receiveQptr Receive queue pointer of ethernet
* @receiveQ1ptr Receive queue-1 pointer of ethernet
* @wakeEnabled Flag to check whether ethernet wakeup is enabled or not
* @subClass Pointer to the class specific to the derived structure
* @subWake Pointer to wake structure of derived class
*/
typedef struct PmWakeEventEth {
PmWakeEvent wake;
const u32 baseAddr;
u32 receiveQptr;
u32 receiveQ1ptr;
u32 receiveHighptr;
bool wakeEnabled;
PmWakeEventClass* const subClass;
PmWakeEvent* const subWake;
} PmWakeEventEth;
#ifdef __cplusplus
}
#endif
#endif /* PM_PERIPH_H_ */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/dpdma_v1_2/src/xdpdma_intr.c
/*******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xdpdma_intr.c
*
* This file contains functions related to XDpPsu interrupt handling.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 aad 01/17/17 Initial release.
* </pre>
*
*******************************************************************************/
/******************************* Include Files ********************************/
#include "xdpdma.h"
/*************************************************************************/
/**
*
* This function enables the interrupts that are required.
*
* @param InstancePtr is pointer to the instance of DPDMA
*
* @param Mask is mask to XDPDMA_IEN register
*
* @return None.
*
* @note None.
*
* **************************************************************************/
void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask)
{
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_IEN, Mask);
}
/*************************************************************************/
/**
*
* This function handles the interrupts generated by DPDMA
*
* @param InstancePtr is pointer to the instance of the DPDMA
*
* @return None.
*
* @note None.
*
* **************************************************************************/
void XDpDma_InterruptHandler(XDpDma *InstancePtr)
{
u32 RegVal;
RegVal = XDpDma_ReadReg(InstancePtr->Config.BaseAddr,
XDPDMA_ISR);
if(RegVal & XDPDMA_ISR_VSYNC_INT_MASK) {
XDpDma_VSyncHandler(InstancePtr);
}
if(RegVal & XDPDMA_ISR_DSCR_DONE4_MASK) {
XDpDma_SetChannelState(InstancePtr, AudioChan0, XDPDMA_DISABLE);
InstancePtr->Audio[0].Current = NULL;
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
XDPDMA_ISR_DSCR_DONE4_MASK);
}
if(RegVal & XDPDMA_ISR_DSCR_DONE5_MASK) {
XDpDma_SetChannelState(InstancePtr, AudioChan1, XDPDMA_DISABLE);
InstancePtr->Audio[1].Current = NULL;
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
XDPDMA_ISR_DSCR_DONE5_MASK);
}
}
/*************************************************************************/
/**
*
* This function handles frame new frames on VSync
*
* @param InstancePtr is pointer to the instance of the driver.
*
* @return None.
*
* @note None.
*
* **************************************************************************/
void XDpDma_VSyncHandler(XDpDma *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
/* Video Channel Trigger/Retrigger Handler */
if(InstancePtr->Video.TriggerStatus == XDPDMA_TRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, VideoChan);
XDpDma_SetChannelState(InstancePtr, VideoChan,
XDPDMA_ENABLE);
XDpDma_Trigger(InstancePtr, VideoChan);
}
else if(InstancePtr->Video.TriggerStatus == XDPDMA_RETRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, VideoChan);
XDpDma_ReTrigger(InstancePtr, VideoChan);
}
/* Graphics Channel Trigger/Retrigger Handler */
if(InstancePtr->Gfx.TriggerStatus == XDPDMA_TRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, GraphicsChan);
XDpDma_SetChannelState(InstancePtr, GraphicsChan,
XDPDMA_ENABLE);
XDpDma_Trigger(InstancePtr, GraphicsChan);
}
else if(InstancePtr->Gfx.TriggerStatus == XDPDMA_RETRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, GraphicsChan);
XDpDma_ReTrigger(InstancePtr, GraphicsChan);
}
/* Audio Channel 0 Trigger Handler */
if(InstancePtr->Audio[0].TriggerStatus == XDPDMA_TRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, AudioChan0);
XDpDma_SetChannelState(InstancePtr, AudioChan0,
XDPDMA_ENABLE);
XDpDma_Trigger(InstancePtr, AudioChan0);
}
/* Audio Channel 1 Trigger Handler */
if(InstancePtr->Audio[1].TriggerStatus == XDPDMA_TRIGGER_EN) {
XDpDma_SetupChannel(InstancePtr, AudioChan1);
XDpDma_SetChannelState(InstancePtr, AudioChan1,
XDPDMA_ENABLE);
XDpDma_Trigger(InstancePtr, AudioChan1);
}
/* Clear VSync Interrupt */
XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
XDPDMA_ISR_VSYNC_INT_MASK);
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilsecure_v4_2/src/xsecure_rsa.h
/******************************************************************************
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_rsa.h
* @addtogroup xsecure_rsa_apis XilSecure RSA APIs
* @{
* @cond xsecure_internal
* This file contains hardware interface related information for RSA device
*
* This driver supports the following features:
*
* - RSA 4096 based decryption
* - verification/authentication of decrypted data
*
* <b>Initialization & Configuration</b>
*
* The Rsa driver instance can be initialized
* in the following way:
*
* - XSecure_RsaInitialize(XSecure_Rsa *InstancePtr, u8* EncText,
* u8 *Mod, u8 *ModExt, u8 *ModExpo)
*
* The method used for RSA decryption needs precalculated value off R^2 mod N
* which is generated by bootgen and is present in the signature along with
* modulus and exponent.
*
* @note
* -The format of the public key( modulus, exponent and precalculated
* R^2 mod N should be same as specified by the bootgen
*
* -For matching, PKCS paddding scheme has to be applied in the manner
* specified by the bootgen.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 ba 10/10/14 Initial release
* 2.2 vns 07/06/17 Added doxygen tags
* vns 17/08/17 Added APIs XSecure_RsaPublicEncrypt and
* XSecure_RsaPrivateDecrypt.As per functionality
* XSecure_RsaPublicEncrypt is same as XSecure_RsaDecrypt.
* 3.1 vns 11/04/18 Added support for 512, 576, 704, 768, 992, 1024, 1152,
* 1408, 1536, 1984, 3072 key sizes, where previous verision
* has support only 2048 and 4096 key sizes.
* 3.2 vns 04/30/18 Added error code XSECURE_RSA_DATA_VALUE_ERROR
* 4.0 arc 18/12/18 Fixed MISRA-C violations.
* vns 03/12/19 Modified as part of XilSecure code re-arch.
* Moved all macro definitions and instance structure to
* xsecure_rsa_core.h
* 4.2 har 11/07/19 Typo correction to enable compilation in C++
* 4.3 kpt 01/07/20 Added Macros for Magic Numbers in xsecure_rsa.c
* </pre>
*
* @endcond
******************************************************************************/
#ifndef XSECURE_RSA_H_
#define XSECURE_RSA_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xsecure_rsa_core.h"
/************************** Constant Definitions ****************************/
#define XSECURE_RSA_BYTE_PAD_LENGTH (3U) /**< PKCS Byte Padding */
#define XSECURE_RSA_T_PAD_LENGTH (19U) /**< PKCS T Padding */
#define XSECURE_RSA_BYTE_PAD1 (0X00U) /**<PKCS T Padding Byte */
#define XSECURE_RSA_BYTE_PAD2 (0X01U) /**<PKCS T Padding Byte */
#define XSECURE_RSA_BYTE_PAD3 (0XFFU) /**<PKCS T Padding Byte */
/***************************** Type Definitions ******************************/
/***************************** Function Prototypes ***************************/
/* Initialization */
s32 XSecure_RsaInitialize(XSecure_Rsa *InstancePtr, u8 *Mod, u8 *ModExt,
u8 *ModExpo);
/* RSA Signature Validation, assuming PKCS padding */
u32 XSecure_RsaSignVerification(u8 *Signature, u8 *Hash, u32 HashLen);
/* XSecure_RsaPublicEncrypt performs same as XSecure_RsaDecrypt API */
s32 XSecure_RsaPublicEncrypt(XSecure_Rsa *InstancePtr, u8 *Input, u32 Size,
u8 *Result);
s32 XSecure_RsaPrivateDecrypt(XSecure_Rsa *InstancePtr, u8 *Input, u32 Size,
u8 *Result);
#ifdef __cplusplus
}
#endif
#endif /* XSECURE_RSA_H_ */
/* @} */
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/libsrc/xilsecure_v4_2/src/versal/xsecure_sss.c
/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsecure_sss.c
* This file contains functions for SSS switch configurations.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 4.2 har 03/26/20 Initial release
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsecure_sss.h"
#include "xsecure_utils.h"
/************************** Constant Definitions *****************************/
/* XSecure_SssLookupTable[Input source][Resource] */
static const u8 XSecure_SssLookupTable
[XSECURE_SSS_MAX_SRCS][XSECURE_SSS_MAX_SRCS] = {
/*+----+-----+-----+-----+-----+-----+-----+--------+
*|DMA0| DMA1| PTPI| AES | SHA | SBI | PZM |Invalid |
*+----+-----+-----+-----+-----+-----+-----+--------+
* 0x00 = INVALID value
*/
{0x0DU, 0x00U, 0x00U, 0x06U, 0x00U, 0x0BU, 0x03U, 0x00U}, /* DMA0 */
{0x00U, 0x09U, 0x00U, 0x07U, 0x00U, 0x0EU, 0x04U, 0x00U}, /* DMA1 */
{0x0DU, 0x0AU, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U}, /* PTPI */
{0x0EU, 0x05U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U}, /* AES */
{0x0CU, 0x07U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U}, /* SHA */
{0x05U, 0x0BU, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U}, /* SBI */
{0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U}, /* PZI */
{0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U}, /* Invalid */
};
/************************** Function Prototypes ******************************/
static u32 XSecure_SssDmaSrc(u16 DmaId, XSecure_SssSrc *Resource);
static u32 XSecure_SssCfg (XSecure_Sss *InstancePtr, XSecure_SssSrc Resource,
XSecure_SssSrc InputSrc, XSecure_SssSrc OutputSrc);
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* @brief
* This function initializes the secure stream switch instance.
*
* @param InstancePtr Instance pointer to the XSecure_Sss.
*
*****************************************************************************/
void XSecure_SssInitialize (XSecure_Sss *InstancePtr)
{
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
InstancePtr->Address = XSECURE_SSS_ADDRESS;
}
/*****************************************************************************/
/**
* @brief
* This function configures the secure stream switch for AES engine.
*
* @param InstancePtr Instance pointer to the XSecure_Sss
* @param InputSrc Input DMA to be selected for AES engine.
* @param OutputSrc Output DMA to be selected for AES engine.
*
* @return - XST_SUCCESS - on successful configuration of the switch
* - XST_FAILURE - on failure to configure switch
*
* @note InputSrc, OutputSrc are of type XSecure_SssSrc.
*
*****************************************************************************/
u32 XSecure_SssAes(XSecure_Sss *InstancePtr,
XSecure_SssSrc InputSrc, XSecure_SssSrc OutputSrc)
{
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((InputSrc >= XSECURE_SSS_DMA0) &&
(InputSrc < XSECURE_SSS_INVALID));
Xil_AssertNonvoid((OutputSrc >= XSECURE_SSS_DMA0) &&
(OutputSrc < XSECURE_SSS_INVALID));
return XSecure_SssCfg(InstancePtr, XSECURE_SSS_AES,
InputSrc, OutputSrc);
}
/*****************************************************************************/
/**
* @brief
* This function configures the secure stream switch for SHA hardware engine.
*
* @param InstancePtr Instance pointer to the XSecure_Sss
* @param DmaId Device ID of DMA which is to be used as an
* input to the SHA engine.
*
* @return - XST_SUCCESS - on successful configuration of the switch.
* - XST_FAILURE - on failure to configure switch
*
*****************************************************************************/
u32 XSecure_SssSha(XSecure_Sss *InstancePtr, u16 DmaId)
{
XSecure_SssSrc InputSrc = XSECURE_SSS_INVALID;
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((DmaId == 0U) || (DmaId == 1U));
Status = XSecure_SssDmaSrc(DmaId, &InputSrc);
if (Status != XST_SUCCESS) {
goto END;
}
Status = XSecure_SssCfg(InstancePtr, XSECURE_SSS_SHA, InputSrc,
XSECURE_SSS_INVALID);
END:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function configures secure stream switch to set DMA in loop back mode.
*
* @param InstancePtr Instance pointer to the XSecure_Sss
* @param DmaId Device ID of DMA.
*
* @return - XST_SUCCESS - on successful configuration of the switch.
* - XST_FAILURE - on failure to configure switch
*
*****************************************************************************/
u32 XSecure_SssDmaLoopBack(XSecure_Sss *InstancePtr, u16 DmaId)
{
XSecure_SssSrc Resource = XSECURE_SSS_INVALID;
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((DmaId == 0U) || (DmaId == 1U));
Status = XSecure_SssDmaSrc(DmaId, &Resource);
if (Status != XST_SUCCESS) {
goto END;
}
Status = XSecure_SssCfg(InstancePtr, Resource, Resource,
XSECURE_SSS_INVALID);
END:
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function sets the DMA source of type XSecure_SssSrc based on the
* provided DMA device ID.
*
* @param InstancePtr Instance pointer to the XSecure_Sss
* @param DmaId Device ID of DMA.
* @param Resource DMA source is updated into the pointer.
*
* @return
* - XST_SUCCESS if DMA ID is correct
* - XST_FAILURE on wrong DMA ID
*
*****************************************************************************/
static u32 XSecure_SssDmaSrc(u16 DmaId, XSecure_SssSrc *Resource)
{
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(Resource != NULL);
Xil_AssertNonvoid((DmaId == 0U) || (DmaId == 1U));
if (DmaId == 0U) {
*Resource = XSECURE_SSS_DMA0;
Status = (u32)XST_SUCCESS;
}
else {
*Resource = XSECURE_SSS_DMA1;
Status = (u32)XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/**
* @brief
* This function configures the secure stream switch.
*
* @param InstancePtr Instance pointer to the XSecure_Sss
* @param Resource Resource for which input and output paths to be
* configured.
* @param InputSrc Input source to be selected for the resource.
* @param OutputSrc Output source to be selected for the resource.
*
* @return - XST_SUCCESS - on successful configuration of the switch
* - XST_FAILURE - on unsuccessful configuration of the switch
*
* @note Resource, InputSrc, OutputSrc are of type XSecure_SssSrc.
*
*****************************************************************************/
static u32 XSecure_SssCfg (XSecure_Sss *InstancePtr, XSecure_SssSrc Resource,
XSecure_SssSrc InputSrc, XSecure_SssSrc OutputSrc)
{
u32 InputSrcCfg = 0x0U;
u32 OutputSrcCfg = 0x0U;
volatile u32 InputSrcCfgRedundant = 0x0U;
volatile u32 OutputSrcCfgRedundant = 0x0U;
u32 SssCfg = 0x0U;
u32 Status = (u32)XST_FAILURE;
/* Assert validates the input arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((InputSrc >= XSECURE_SSS_DMA0) &&
(InputSrc <= XSECURE_SSS_INVALID));
Xil_AssertNonvoid((OutputSrc >= XSECURE_SSS_DMA0) &&
(OutputSrc <= XSECURE_SSS_INVALID));
Xil_AssertNonvoid((Resource >= XSECURE_SSS_DMA0) &&
(Resource <= XSECURE_SSS_INVALID));
/*
* Configure source of the input for given resource
* i.e Configure given InputSrc as a input for given Resource
*/
InputSrcCfg = (u32) XSecure_SssLookupTable [Resource][InputSrc] <<
(XSECURE_SSS_CFG_LEN_IN_BITS * (u32)Resource);
/*
* SSS allows configuring only input source for any Resources
* connected to it. So to define output source of given Resource,
* configure given Resource as input to source mentioned by OutputSrc
*/
OutputSrcCfg = (u32) XSecure_SssLookupTable [OutputSrc][Resource] <<
(XSECURE_SSS_CFG_LEN_IN_BITS * (u32)OutputSrc);
/* Recalculating to verify values */
InputSrcCfgRedundant = (u32) XSecure_SssLookupTable [Resource][InputSrc] <<
(XSECURE_SSS_CFG_LEN_IN_BITS * (u32)Resource);
OutputSrcCfgRedundant = (u32) XSecure_SssLookupTable [OutputSrc][Resource] <<
(XSECURE_SSS_CFG_LEN_IN_BITS * (u32)OutputSrc);
SssCfg = InputSrcCfg | OutputSrcCfg;
if ((SssCfg ^ (InputSrcCfgRedundant | OutputSrcCfgRedundant)) == 0U) {
Status = XSecure_SecureOut32(InstancePtr->Address, SssCfg);
}
return Status;
}
<file_sep>/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/libsrc/libmetal_v2_1/src/libmetal/cmake/platforms/toolchain.cmake
set (CMAKE_SYSTEM_PROCESSOR "microblaze" CACHE STRING "")
set (MACHINE "microblaze_generic")
set (CROSS_PREFIX "mb-" CACHE STRING "")
set (CMAKE_C_FLAGS " -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mxl-soft-mul -mcpu=v9.2 -mlittle-endian -g -ffunction-sections -fdata-sections -Wall -Wextra -Os -flto -ffat-lto-objects -IC:/James/vitis_workspace/test_proj_plat/zynqmp_pmufw/zynqmp_pmufw_bsp/psu_pmu_0/include" CACHE STRING "")
set (CMAKE_SYSTEM_NAME "Generic" CACHE STRING "")
include (CMakeForceCompiler)
CMAKE_FORCE_C_COMPILER ("${CROSS_PREFIX}gcc" GNU)
CMAKE_FORCE_CXX_COMPILER ("${CROSS_PREFIX}g++" GNU)
set (CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER CACHE STRING "")
set (CMAKE_FIND_ROOT_PATH_MODE_LIBRARY NEVER CACHE STRING "")
set (CMAKE_FIND_ROOT_PATH_MODE_INCLUDE NEVER CACHE STRING "")
| c26cca76cfccaabd25bfd8d8fd62148fdc72d4f0 | [
"CMake",
"Makefile",
"INI",
"Python",
"Text",
"C"
] | 341 | C | fluorine21/quantum_time_sync | cfc13d8814388bdc1021666a505050f617e39726 | b0c7657488ffb5269fc8c7dbc40dbec22a40ac22 |
refs/heads/master | <repo_name>DanSh21/todolist<file_sep>/src/App.js
import React from 'react';
import logo from './logo.svg';
import './App.css';
import { Route, BrowserRouter as Router } from 'react-router-dom';
import TodoList from './containers/TodoList';
import Auth from './containers/Auth';
import { makeStyles } from '@material-ui/core';
import Button from '@material-ui/core/Button';
const useStyles = makeStyles(theme => ({
root: {
height: '100vh',
backgroundColor: '#503ab7',
},
authButton: {
position: 'absolute',
top: 20,
left: 20,
backgroundColor: '#fff',
}
}))
function App() {
const classes = useStyles();
return (
<div className={classes.root}>
<Router>
<Route exact path="/" component={Auth} />
<Route exact path="/list" component={TodoList} />
</Router>
</div>
);
}
export default App;
<file_sep>/src/components/Dialog.js
import React from 'react';
import Button from '@material-ui/core/Button';
import TextField from '@material-ui/core/TextField';
import Dialog from '@material-ui/core/Dialog';
import DialogActions from '@material-ui/core/DialogActions';
import DialogContent from '@material-ui/core/DialogContent';
import DialogTitle from '@material-ui/core/DialogTitle';
export default function FormDialog(props) {
let [open, setOpen] = React.useState(false);
let [text, setText] = React.useState({ ...props.text });
open = props.open;
React.useEffect(() => {
setText(props.text);
}, [props.text])
const handleClose = () => {
setOpen(false);
props.handleCloseDialog(false);
};
const handleSubmit = () => {
setOpen(false);
props.handleCloseDialog(false);
props.handleSubmit(props.id, text, props.status);
};
const handleChange = (event) => {
setText(event.target.value)
};
return (
<div>
<Dialog open={open} onClose={handleClose} aria-labelledby="form-dialog-title">
<DialogTitle id="form-dialog-title">Edit task #{props.id}</DialogTitle>
<DialogContent>
<TextField
autoFocus
margin="dense"
id="text"
label="Text of task"
fullWidth
value={text}
onChange={handleChange}
/>
</DialogContent>
<DialogActions>
<Button onClick={handleSubmit} color="primary">
Submit
</Button>
</DialogActions>
</Dialog>
</div>
);
}<file_sep>/src/Storage.js
export const initialState = {
todo: {
token: null,
total: 0,
tasks: []
}
}
export const loadState = () => {
try {
const serializedStorage = localStorage.getItem('token');
console.log(serializedStorage);
if (serializedStorage === null) {
return initialState;
}
// console.log('SAVE',serializedStorage);
initialState.todo.token = JSON.parse(serializedStorage);
return initialState;
} catch (error) {
return initialState;
}
}
export const saveState = (state) => {
try {
const serializedStorage = JSON.stringify(state);
// console.log('STAT', state)
localStorage.setItem('token', serializedStorage);
} catch (error) {
return null;
}
} | 6dd64e65d7e6c157e335c0e155fe8e101b358ba9 | [
"JavaScript"
] | 3 | JavaScript | DanSh21/todolist | d525092b04b4ebe245c891a8e5eb48a24719b6f3 | e1f046a7e6fd6eeafa8dba9dac78beb55255ea4a |
refs/heads/master | <file_sep>/*
* @Author: <NAME>
* June 21, 2017
*/
$(document).ready(function()
{
// $('.menu-toggle').click(function(){
// $(this).toggleClass('active');
// $('.left-nav').ToggleClass("active");
// });
});
<file_sep>file.reference.vetdesign-public_html=public_html
file.reference.vetdesign-test=test
files.encoding=UTF-8
site.root.folder=${file.reference.vetdesign-public_html}
test.folder=${file.reference.vetdesign-test}
<file_sep>-- phpMyAdmin SQL Dump
-- version 4.2.7.1
-- http://www.phpmyadmin.net
--
-- Host: localhost
-- Generation Time: Jul 15, 2017 at 03:41 PM
-- Server version: 5.5.39
-- PHP Version: 5.4.31
SET SQL_MODE = "NO_AUTO_VALUE_ON_ZERO";
SET time_zone = "+00:00";
/*!40101 SET @OLD_CHARACTER_SET_CLIENT=@@CHARACTER_SET_CLIENT */;
/*!40101 SET @OLD_CHARACTER_SET_RESULTS=@@CHARACTER_SET_RESULTS */;
/*!40101 SET @OLD_COLLATION_CONNECTION=@@COLLATION_CONNECTION */;
/*!40101 SET NAMES utf8 */;
--
-- Database: `vet`
--
-- --------------------------------------------------------
--
-- Table structure for table `breed`
--
CREATE TABLE IF NOT EXISTS `breed` (
`id` int(11) NOT NULL,
`name` varchar(125) NOT NULL
) ENGINE=InnoDB DEFAULT CHARSET=latin1 AUTO_INCREMENT=1 ;
-- --------------------------------------------------------
--
-- Table structure for table `customer`
--
CREATE TABLE IF NOT EXISTS `customer` (
`id` int(11) NOT NULL,
`lastname` varchar(125) NOT NULL,
`firstname` varchar(125) NOT NULL,
`address` varchar(225) NOT NULL,
`mobile` varchar(15) NOT NULL,
`email` varchar(50) NOT NULL,
`username` varchar(125) NOT NULL,
`password` varchar(125) NOT NULL,
`enabled` tinyint(1) NOT NULL
) ENGINE=InnoDB DEFAULT CHARSET=latin1 AUTO_INCREMENT=1 ;
-- --------------------------------------------------------
--
-- Table structure for table `doctor`
--
CREATE TABLE IF NOT EXISTS `doctor` (
`id` int(11) NOT NULL,
`lastname` varchar(125) NOT NULL,
`firstname` varchar(125) NOT NULL,
`mobile` varchar(15) NOT NULL,
`mon` tinyint(1) NOT NULL,
`tue` tinyint(1) NOT NULL,
`wed` tinyint(1) NOT NULL,
`thur` tinyint(1) NOT NULL,
`fri` tinyint(1) NOT NULL,
`sat` tinyint(1) NOT NULL,
`sun` tinyint(1) NOT NULL,
`time_in` time NOT NULL,
`time_out` time NOT NULL,
`enabled` tinyint(1) NOT NULL
) ENGINE=InnoDB DEFAULT CHARSET=latin1 AUTO_INCREMENT=1 ;
-- --------------------------------------------------------
--
-- Table structure for table `order`
--
CREATE TABLE IF NOT EXISTS `order` (
`id` int(11) NOT NULL,
`cutomer_id` int(11) NOT NULL,
`date_added` datetime NOT NULL,
`billing_name` varchar(225) NOT NULL,
`billing_address` varchar(225) NOT NULL,
`billing_email` varchar(50) NOT NULL,
`billing_mobile` int(15) NOT NULL,
`status` varchar(125) NOT NULL,
`note` varchar(512) NOT NULL
) ENGINE=InnoDB DEFAULT CHARSET=latin1 AUTO_INCREMENT=1 ;
-- --------------------------------------------------------
--
-- Table structure for table `order_line`
--
CREATE TABLE IF NOT EXISTS `order_line` (
`id` int(11) NOT NULL,
`order_id` int(11) NOT NULL,
`product_id` int(11) NOT NULL,
`quantity` int(11) NOT NULL,
`price` decimal(11,2) NOT NULL,
`total` decimal(11,2) NOT NULL
) ENGINE=InnoDB DEFAULT CHARSET=latin1 AUTO_INCREMENT=1 ;
-- --------------------------------------------------------
--
-- Table structure for table `pet`
--
CREATE TABLE IF NOT EXISTS `pet` (
`id` int(11) NOT NULL,
`owner_id` int(11) NOT NULL,
`name` varchar(225) NOT NULL,
`breed_id` int(11) NOT NULL,
`specie_id` int(11) NOT NULL,
`sex` tinyint(1) NOT NULL COMMENT '1 - Male, 2 - Female'
) ENGINE=InnoDB DEFAULT CHARSET=latin1 AUTO_INCREMENT=1 ;
-- --------------------------------------------------------
--
-- Table structure for table `product`
--
CREATE TABLE IF NOT EXISTS `product` (
`id` int(11) NOT NULL,
`name` varchar(225) NOT NULL,
`description` text NOT NULL,
`price` decimal(11,2) NOT NULL,
`image` varchar(125) NOT NULL,
`enabled` tinyint(1) NOT NULL
) ENGINE=InnoDB DEFAULT CHARSET=latin1 AUTO_INCREMENT=1 ;
-- --------------------------------------------------------
--
-- Table structure for table `service`
--
CREATE TABLE IF NOT EXISTS `service` (
`id` int(11) NOT NULL,
`name` varchar(225) NOT NULL,
`description` text NOT NULL,
`price` decimal(11,2) NOT NULL,
`image` varchar(125) NOT NULL,
`enabled` tinyint(1) NOT NULL
) ENGINE=InnoDB DEFAULT CHARSET=latin1 AUTO_INCREMENT=1 ;
-- --------------------------------------------------------
--
-- Table structure for table `specie`
--
CREATE TABLE IF NOT EXISTS `specie` (
`id` int(11) NOT NULL,
`name` varchar(125) NOT NULL
) ENGINE=InnoDB DEFAULT CHARSET=latin1 AUTO_INCREMENT=1 ;
--
-- Indexes for dumped tables
--
--
-- Indexes for table `breed`
--
ALTER TABLE `breed`
ADD PRIMARY KEY (`id`);
--
-- Indexes for table `customer`
--
ALTER TABLE `customer`
ADD PRIMARY KEY (`id`);
--
-- Indexes for table `doctor`
--
ALTER TABLE `doctor`
ADD PRIMARY KEY (`id`);
--
-- Indexes for table `order`
--
ALTER TABLE `order`
ADD PRIMARY KEY (`id`);
--
-- Indexes for table `order_line`
--
ALTER TABLE `order_line`
ADD PRIMARY KEY (`id`);
--
-- Indexes for table `pet`
--
ALTER TABLE `pet`
ADD PRIMARY KEY (`id`);
--
-- Indexes for table `product`
--
ALTER TABLE `product`
ADD PRIMARY KEY (`id`);
--
-- Indexes for table `service`
--
ALTER TABLE `service`
ADD PRIMARY KEY (`id`);
--
-- Indexes for table `specie`
--
ALTER TABLE `specie`
ADD PRIMARY KEY (`id`);
--
-- AUTO_INCREMENT for dumped tables
--
--
-- AUTO_INCREMENT for table `breed`
--
ALTER TABLE `breed`
MODIFY `id` int(11) NOT NULL AUTO_INCREMENT;
--
-- AUTO_INCREMENT for table `customer`
--
ALTER TABLE `customer`
MODIFY `id` int(11) NOT NULL AUTO_INCREMENT;
--
-- AUTO_INCREMENT for table `doctor`
--
ALTER TABLE `doctor`
MODIFY `id` int(11) NOT NULL AUTO_INCREMENT;
--
-- AUTO_INCREMENT for table `order`
--
ALTER TABLE `order`
MODIFY `id` int(11) NOT NULL AUTO_INCREMENT;
--
-- AUTO_INCREMENT for table `order_line`
--
ALTER TABLE `order_line`
MODIFY `id` int(11) NOT NULL AUTO_INCREMENT;
--
-- AUTO_INCREMENT for table `pet`
--
ALTER TABLE `pet`
MODIFY `id` int(11) NOT NULL AUTO_INCREMENT;
--
-- AUTO_INCREMENT for table `product`
--
ALTER TABLE `product`
MODIFY `id` int(11) NOT NULL AUTO_INCREMENT;
--
-- AUTO_INCREMENT for table `service`
--
ALTER TABLE `service`
MODIFY `id` int(11) NOT NULL AUTO_INCREMENT;
--
-- AUTO_INCREMENT for table `specie`
--
ALTER TABLE `specie`
MODIFY `id` int(11) NOT NULL AUTO_INCREMENT;
/*!40101 SET CHARACTER_SET_CLIENT=@OLD_CHARACTER_SET_CLIENT */;
/*!40101 SET CHARACTER_SET_RESULTS=@OLD_CHARACTER_SET_RESULTS */;
/*!40101 SET COLLATION_CONNECTION=@OLD_COLLATION_CONNECTION */;
<file_sep>/*
* @Author: <NAME>
* June 21, 2017
*/
var ToothPlugin = function()
{
var BASE_WIDTH = 600;
var BASE_HEIGHT = 425;
var tooth_data_upper = [];
tooth_data_upper[11] = '{"top" : "1%","margin" : "40%","width" : 57, "height": 74, "radius" : "50% 50% 50% 50% / 30% 30% 70% 70%", "rotate" : "0deg"}';
tooth_data_upper[12] = '{"top" : "6%","margin" : "32%","width" : 49, "height": 67, "radius" : "50% 50% 50% 50% / 30% 30% 70% 70%", "rotate" : "-31deg"}';
tooth_data_upper[13] = '{"top" : "13%","margin" : "25%","width" : 50, "height": 70, "radius" : "50% 50% 50% 50% / 13% 30% 57% 86%", "rotate" : "-60deg"}';
tooth_data_upper[14] = '{"top" : "23%","margin" : "19%","width" : 55, "height": 79, "radius" : "50% 50% 50% 50% / 72% 40% 55% 46%", "rotate" : "-79deg"}';
tooth_data_upper[15] = '{"top" : "36%","margin" : "13%","width" : 61, "height": 78, "radius" : "50% 50% 50% 50% / 54% 40% 55% 46%", "rotate" : "-80deg"}';
tooth_data_upper[16] = '{"top" : "49%","margin" : "11%","width" : 58, "height": 87, "radius" : "50% 50% 50% 50% / 41% 46% 64% 46%", "rotate" : "-74deg"}';
tooth_data_upper[17] = '{"top" : "62%","margin" : "9%","width" : 58, "height": 93, "radius" : "50% 50% 50% 50% / 22% 18% 76% 46%", "rotate" : "-76deg"}';
tooth_data_upper[18] = '{"top" : "79%","margin" : "4%","width" : 85, "height": 93, "radius" : "50% 50% 50% 50% / 40% 35% 78% 46%", "rotate" : "-93deg"}';
tooth_data_upper[21] = '{"top" : "1%","margin" : "40%","width" : 57, "height": 74, "radius" : "50% 50% 50% 50% / 30% 30% 70% 70%", "rotate" : "0deg"}';
tooth_data_upper[22] = '{"top" : "6%","margin" : "32%","width" : 49, "height": 67, "radius" : "50% 50% 50% 50% / 30% 30% 70% 70%", "rotate" : "27deg"}';
tooth_data_upper[23] = '{"top" : "13%","margin" : "25%","width" : 52, "height": 70, "radius" : "50% 50% 50% 50% / 30% 13% 86% 57%", "rotate" : "45deg"}';
tooth_data_upper[24] = '{"top" : "23%","margin" : "20%","width" : 55, "height": 79, "radius" : "50% 50% 50% 50% / 72% 40% 55% 46%", "rotate" : "59deg"}';
tooth_data_upper[25] = '{"top" : "36%","margin" : "14%","width" : 61, "height": 78, "radius" : "50% 50% 50% 50% / 54% 40% 55% 46%", "rotate" : "59deg"}';
tooth_data_upper[26] = '{"top" : "49%","margin" : "11%","width" : 58, "height": 87, "radius" : "50% 50% 50% 50% / 41% 46% 64% 46%", "rotate" : "66deg"}';
tooth_data_upper[27] = '{"top" : "62%","margin" : "9%","width" : 58, "height": 93, "radius" : "50% 50% 50% 50% / 22% 18% 76% 46%", "rotate" : "68deg"}';
tooth_data_upper[28] = '{"top" : "79%","margin" : "4%","width" : 85, "height": 93, "radius" : "50% 50% 50% 50% / 64% 32% 78% 46%", "rotate" : "66deg"}';
var tooth_data_lower = [];
tooth_data_lower[31] = '{"bottom" : "1%","margin" : "40%","width" : 57, "height": 74, "radius" : "50% 50% 50% 50% / 70% 70% 30% 30%", "rotate" : "0deg"}';
tooth_data_lower[32] = '{"bottom" : "6%","margin" : "32%","width" : 49, "height": 67, "radius" : "50% 50% 50% 50% / 70% 70% 30% 30%", "rotate" : "-31deg"}';
tooth_data_lower[33] = '{"bottom" : "13%","margin" : "25%","width" : 50, "height": 70, "radius" : "50% 50% 50% 50% / 57% 86% 13% 30%", "rotate" : "-60deg"}';
tooth_data_lower[34] = '{"bottom" : "23%","margin" : "19%","width" : 55, "height": 79, "radius" : "50% 50% 50% 50% / 55% 46% 72% 40%", "rotate" : "-79deg"}';
tooth_data_lower[35] = '{"bottom" : "36%","margin" : "14%","width" : 61, "height": 78, "radius" : "50% 50% 50% 50% / 55% 46% 54% 40%", "rotate" : "-80deg"}';
tooth_data_lower[36] = '{"bottom" : "49%","margin" : "11%","width" : 58, "height": 87, "radius" : "50% 50% 50% 50% / 64% 46% 41% 46%", "rotate" : "-74deg"}';
tooth_data_lower[37] = '{"bottom" : "62%","margin" : "8%","width" : 58, "height": 93, "radius" : "50% 50% 50% 50% / 76% 46% 22% 18%", "rotate" : "-76deg"}';
tooth_data_lower[38] = '{"bottom" : "79%","margin" : "4%","width" : 85, "height": 93, "radius" : "50% 50% 50% 50% / 78% 46% 40% 35%", "rotate" : "-93deg"}';
tooth_data_lower[41] = '{"bottom" : "1%","margin" : "40%","width" : 57, "height": 74, "radius" : "50% 50% 50% 50% / 70% 70% 30% 30%", "rotate" : "0deg"}';
tooth_data_lower[42] = '{"bottom" : "6%","margin" : "32%","width" : 49, "height": 67, "radius" : "50% 50% 50% 50% / 70% 70% 30% 30%", "rotate" : "27deg"}';
tooth_data_lower[43] = '{"bottom" : "13%","margin" : "25%","width" : 52, "height": 70, "radius" : "50% 50% 50% 50% / 86% 57% 30% 13%", "rotate" : "45deg"}';
tooth_data_lower[44] = '{"bottom" : "23%","margin" : "20%","width" : 55, "height": 79, "radius" : "50% 50% 50% 50% / 55% 46% 72% 40%", "rotate" : "59deg"}';
tooth_data_lower[45] = '{"bottom" : "36%","margin" : "14%","width" : 61, "height": 78, "radius" : "50% 50% 50% 50% / 55% 46% 54% 40%", "rotate" : "59deg"}';
tooth_data_lower[46] = '{"bottom" : "49%","margin" : "11%","width" : 58, "height": 87, "radius" : "50% 50% 50% 50% / 64% 46% 41% 46%", "rotate" : "66deg"}';
tooth_data_lower[47] = '{"bottom" : "62%","margin" : "8%","width" : 58, "height": 93, "radius" : "50% 50% 50% 50% / 76% 46% 22% 18%", "rotate" : "68deg"}';
tooth_data_lower[48] = '{"bottom" : "79%","margin" : "4%","width" : 85, "height": 93, "radius" : "50% 50% 50% 50% / 78% 46% 64% 32%", "rotate" : "66deg"}';
var DIMEN_RATIO_HEIGHT = function(ACTUAL_WIDTH)
{
var ACTUAL_HEIGHT = (ACTUAL_WIDTH * BASE_HEIGHT) / BASE_WIDTH;
return ACTUAL_HEIGHT;
};
var DIMEN_MULTIPLIER = function(ACTUAL_WIDTH)
{
return ACTUAL_WIDTH / BASE_WIDTH;
};
return{
toothData : tooth_data_upper,
init : function(container){
var ACTUAL_WIDTH = $(container).width();
var ACTUAL_HEIGHT = DIMEN_RATIO_HEIGHT(ACTUAL_WIDTH);
$(container).children('.upper').height(ACTUAL_HEIGHT+"px");
$(container).children('.lower').height(ACTUAL_HEIGHT+"px");
$(container).height((ACTUAL_HEIGHT * 2 + 20)+"px");
var MUL = DIMEN_MULTIPLIER(ACTUAL_WIDTH);
//upper
for(ctr = 11; ctr <= 28; ctr++)
{
if(tooth_data_upper[ctr] != null)
{
var new_span = $("<span></span>");
new_span.attr('data-number',ctr);
new_span.html("<number>"+ctr+"</number>");
var elem_prop = JSON.parse(tooth_data_upper[ctr]);
if(ctr <= 18)
{
var css_list = {
"width" : MUL * elem_prop.width + "px",
"height" : MUL * elem_prop.height + "px",
"border-radius" : elem_prop.radius,
"transform" : "rotate("+elem_prop.rotate+")",
"left" : elem_prop.margin,
"top" : elem_prop.top
};
}
else
{
var css_list = {
"width" : MUL * elem_prop.width + "px",
"height" : MUL * elem_prop.height + "px",
"border-radius" : elem_prop.radius,
"transform" : "rotate("+elem_prop.rotate+")" ,
"right" : elem_prop.margin,
"top" : elem_prop.top
};
}
new_span.css(css_list);
new_span.addClass("tooth");
$(container).children('.upper').append(new_span);
}
}
//lower
for(ctr = 31; ctr <= 48; ctr++)
{
if(tooth_data_lower[ctr] != null)
{
var new_span = $("<span></span>");
new_span.attr('data-number',ctr);
new_span.html("<number>"+ctr+"</number>");
var elem_prop = JSON.parse(tooth_data_lower[ctr]);
console.log(elem_prop);
if(ctr <= 38)
{
var css_list = {
"width" : MUL * elem_prop.width + "px",
"height" : MUL * elem_prop.height + "px",
"border-radius" : elem_prop.radius,
"transform" : "rotate("+elem_prop.rotate+")",
"right" : elem_prop.margin,
"bottom" : elem_prop.bottom
};
}
else
{
var css_list = {
"width" : MUL * elem_prop.width + "px",
"height" : MUL * elem_prop.height + "px",
"border-radius" : elem_prop.radius,
"transform" : "rotate("+elem_prop.rotate+")" ,
"left" : elem_prop.margin,
"bottom" : elem_prop.bottom
};
}
new_span.css(css_list);
new_span.addClass("tooth");
console.log(new_span);
$(container).children('.lower').append(new_span);
}
}
$(container).on("click",".tooth", function(){
$(this).toggleClass("selected");
});
}
};
};
var tooth = new ToothPlugin();
| 0ea1e13b86b760b713316c1bbff8dfedc3095f0d | [
"JavaScript",
"SQL",
"INI"
] | 4 | JavaScript | projpetvet/webdesign | 5b858aa26e17390bcb06ceceac197bb7c343776c | 5f9efbad49e5743b70f068efc6b464dbb8fbce52 |
refs/heads/master | <file_sep>package com.cloudbees.genapp.metadata.resource;
/*
* Copyright 2010-2013, CloudBees Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
import java.util.Map;
/**
* This class stores properties for a given section (i.e. java, tomcat7, glassfish3, etc...)
*/
public class RuntimeProperty {
private Map<String, String> parameters;
private String section;
/**
* Create a new RuntimeProperty from the section name and a map of key-value pairs.
* @param section The parent section of the parameters.
* @param parameters A key-value map of the parameters.
*/
public RuntimeProperty (String section, Map<String, String> parameters) {
this.parameters = parameters;
this.section = section;
}
public String getSectionName() {
return section;
}
public String getParameter(String parameterName) {
return parameters.get(parameterName);
}
public Map<String, String> getParameters() {
return parameters;
}
}
<file_sep> # Glassfish3 ClickStack plugin
#
# TODO: SSL port?
plugin_name = glassfish3-full-plugin
publish_bucket = cloudbees-clickstack
publish_repo = testing
publish_url = s3://$(publish_bucket)/$(publish_repo)/
deps = lib/glassfish.zip lib/jmxtrans-agent.jar lib/cloudbees-jmx-invoker.jar lib/mysql-connector-java.jar
pkg_files = README.md LICENSE setup functions control server lib java
include plugin.mk
lib:
mkdir -p lib
deps:
cd java; make deps
clean:
rm -rf lib
cd java; make clean
glassfish_ver = 3.1.2.2
glassfish_src = "http://download.java.net/glassfish/$(glassfish_ver)/release/glassfish-$(glassfish_ver).zip"
glassfish_src_md5 = ae8e17e9dcc80117cb4b39284302763f
lib/glassfish.zip: lib/genapp-setup-glassfish3.jar
curl -fLo lib/glassfish.zip "$(glassfish_src)"
$(call check-md5,lib/glassfish.zip,$(glassfish_src_md5))
JAVA_SOURCES := $(shell find genapp-setup-glassfish3/src -name "*.java")
JAVA_JARS = $(shell find genapp-setup-glassfish3/target -name "*.jar")
lib/genapp-setup-glassfish3.jar: $(JAVA_SOURCES) $(JAVA_JARS) lib
cd genapp-setup-glassfish3; \
mvn -q clean test assembly:single; \
cd target; \
cp genapp-setup-glassfish3-*-jar-with-dependencies.jar \
$(CURDIR)/lib/genapp-setup-glassfish3.jar
jmxtrans_agent_ver = 1.0.4
jmxtrans_agent_url = http://repo1.maven.org/maven2/org/jmxtrans/agent/jmxtrans-agent/$(jmxtrans_agent_ver)/jmxtrans-agent-$(jmxtrans_agent_ver).jar
jmxtrans_agent_md5 = 3e6f619d2c07841812704627ed96a991
lib/jmxtrans-agent.jar: lib
curl -fLo lib/jmxtrans-agent.jar "$(jmxtrans_agent_url)"
$(call check-md5,lib/jmxtrans-agent.jar,$(jmxtrans_agent_md5))
jmx_invoker_ver = 1.0.2
jmx_invoker_src = http://repo1.maven.org/maven2/com/cloudbees/cloudbees-jmx-invoker/$(jmx_invoker_ver)/cloudbees-jmx-invoker-$(jmx_invoker_ver)-jar-with-dependencies.jar
jmx_invoker_md5 = c880f7545775529cfce6ea6b67277453
lib/cloudbees-jmx-invoker.jar: lib
mkdir -p lib
curl -fLo lib/cloudbees-jmx-invoker-jar-with-dependencies.jar "$(jmx_invoker_src)"
# $(call check-md5,lib/cloudbees-jmx-invoker-jar-with-dependencies.jar,$(jmx_invoker_md5))
mysql_connector_ver = 5.1.25
mysql_connector_url = http://repo1.maven.org/maven2/mysql/mysql-connector-java/$(mysql_connector_ver)/mysql-connector-java-$(mysql_connector_ver).jar
mysql_connector_md5 = 46696baf8207192077ab420e5bfdc096
lib/mysql-connector-java.jar: lib
curl -fLo lib/mysql-connector-java.jar "$(mysql_connector_url)"
$(call check-md5,lib/mysql-connector-java.jar,$(mysql_connector_md5))
<file_sep>#!/bin/bash
set -u
set -e
. "$plugin_dir/functions"
create_app_skel
install_glassfish
install_app
install_java_agent
install_jmx_invoker
install_jmxtrans_agent
install_java_control_functions
install_server_config
write_config
write_java_opts
install_mysql_connector_jar
write_control
<file_sep>#!/bin/bash
set -e
set -u
control_dir="$(dirname $0)"
. "$control_dir/java/functions"
. "$control_dir/config"
. "$control_dir/env_safe"
export JAVA_HOME=$JAVA_HOME
export PATH=$JAVA_HOME/bin:$PATH
java_opts="$(java_opts $control_dir)"
exec bash -c "
$java \
$java_opts \
-Dapp_port=$port \
-Dglassfish_work_dir=\"$glassfish_work_dir\" \
-Djava.io.tmpdir=\"$app_tmp\" \
-Dderby.stream.error.file=\"$log_dir/derby.log\" \
-jar $glassfish_base/modules/glassfish.jar
"
<file_sep># -*-shell-script-*-
. "$genapp_functions/core"
. "$plugin_dir/java/functions"
glassfish_dir="$app_dir/glassfish3"
glassfish_base="$glassfish_dir/glassfish"
glassfish_domain="$glassfish_base/domains/domain1"
glassfish_lib_dir="$glassfish_domain/lib"
glassfish_work_dir="$glassfish_domain/work"
create_app_skel() {
echo "Creating application skeleton at $app_dir"
chmod 750 "$app_dir"
mkdir -m 770 "$app_dir/tmp"
mkdir -m 750 "$genapp_dir/lib"
# We need to initialize this file as it is going to be sourced later.
# Also, install_server_config step requires pre-existing files.
touch "$control_dir/env_safe"
chmod 640 "$control_dir/env_safe"
}
install_glassfish() {
echo "Installing glassfish"
unzip -qd "$app_dir" "$plugin_dir/lib/glassfish.zip"
# Make all files readable for the start script.
chmod -R o-rwx,g+r "$glassfish_dir"
# Make all directories executable for the start script.
find "$glassfish_dir" -type d -print0 | xargs -0 chmod g+x
# Make the glassfish_domain directory writable for the start script.
chmod -R g+w "$glassfish_domain"
}
install_jmx_invoker() {
cp $plugin_dir/lib/cloudbees-jmx-invoker-jar-with-dependencies.jar $genapp_dir/lib/
install -m 750 $plugin_dir/control/jmx_invoker $control_dir
}
install_jmxtrans_agent() {
# The jmxtrans agent takes care of metrics reporting
# which can be accessed with the control script stats-appstat
echo "Installing jmxtrans-agent"
_agent_config_file="$plugin_dir/server/conf/glassfish3-metrics.xml"
_agent_config_file_dest="$glassfish_domain/config/glassfish3-metrics.xml"
install -m 640 "$_agent_config_file" "$_agent_config_file_dest"
_agent_jar_file="$plugin_dir/lib/jmxtrans-agent.jar"
_agent_jar_dest="$genapp_dir/lib/jmxtrans-agent.jar"
install -m 750 "$_agent_jar_file" "$_agent_jar_dest"
_agent_data_dest="$log_dir/glassfish3-metrics.data"
_java_opts="-javaagent:\"$_agent_jar_dest\"=\"$_agent_config_file_dest\""
_java_opts+=" -Dglassfish3_metrics_data_file=\"$_agent_data_dest\""
_agent_opts_file="$control_dir/java-opts-60-jmxtrans-agent"
echo "$_java_opts" >> "$_agent_opts_file"
}
install_mysql_connector_jar() {
echo "Installing mysql-connector"
_mysql_connector_jar_file="$plugin_dir/lib/mysql-connector-java.jar"
_mysql_connector_jar_dest="$glassfish_lib_dir/"
install -m 750 "$_mysql_connector_jar_file" "$_mysql_connector_jar_dest"
}
install_app() {
echo "Copying application war to $glassfish_domain/autodeploy"
cp "$pkg_dir/app.war" "$glassfish_domain/autodeploy"
lcount=$(unzip -l $pkg_dir/app.war | grep META-INF/lib/ | wc -l)
echo "found $lcount files matching meta-inf/lib/"
if [ "$lcount" -eq 0 ]; then
echo "No lib provided under META-INF/lib."
else
unzip -jo "$pkg_dir/app.war" "META-INF/lib/"* -d "$glassfish_domain/lib"
fi
}
install_server_config() {
# We install the base configuration, which will be overwritten with
# the metadata by the genapp-setup-glassfish3 jar.
echo "Installing server config"
cp "$plugin_dir/server/conf/domain.xml" "$glassfish_domain/config/"
echo "Injecting metadata into domain.xml"
# This jar writes metadata to:
# $control_dir/env_safe
# $glassfish_domain/config/domain.xml
$(find_java) -jar "$plugin_dir/lib/genapp-setup-glassfish3.jar"
chmod 640 "$glassfish_domain/config/domain.xml"
}
write_config() {
_config="$control_dir/config"
echo "Writing configuration to $_config"
java=$(find_java)
echo "Using Java at $java"
echo "java=\"$java\"" >> "$_config"
java_home="$(dirname $(dirname $java))"
echo "Using JAVA_HOME at $java_home"
echo "JAVA_HOME=\"$java_home\"" >> "$_config"
echo "app_dir=\"$app_dir\"" >> "$_config"
echo "genapp_dir=\"$genapp_dir\"" >> "$_config"
echo "port=$app_port" >> "$_config"
echo "glassfish_home=\"$glassfish_dir\"" >> "$_config"
echo "glassfish_base=\"$glassfish_base\"" >> "$_config"
echo "glassfish_domain=\"$glassfish_domain\"" >> "$_config"
echo "glassfish_work_dir=\"$glassfish_work_dir\"" >> "$_config"
echo "app_tmp=\"$app_dir/tmp\"" >> "$_config"
echo "log_dir=\"$log_dir\"" >> "$_config"
}
write_control() {
echo "Writing control scripts to $control_dir"
install -m 550 "$plugin_dir/control/"* "$control_dir/"
}
<file_sep># GlassFish v3 Full ClickStack
# Step by Step tutorial to use GlassFish 3 Full Profile
## Create a Glassfish3 container
```
bees app:deploy -a my-glassfish3-app -t glassfish3-full path/to/my/app.war
```
## Create a MySQL Database
```
bees db:create my-glassfish3-db
```
## Bind the MySQL Database to the Glassfish container
```
bees app:bind -a my-glassfish3-app -db my-glassfish3-db -as mydb
```
Supported JNDI names:
* `jdbc/mydb` : unqualified relative JNDI name is **OK**
* `java:comp/env/jdbc/mydb`: qualified private name is **OK**
* <del><code>java:jdbc/mydb</code></del> and <del><code>java:/jdbc/mydb</code></del>: qualified relative names are **KO**
* <del><code>java:global/env/jdbc/mydb</code></del>: qualified global name does **NOT work**
Samples:
```java
Context ctx = new InitialContext();
DataSource ds = (DataSource) ctx.lookup("jdbc/mydb");
DataSource ds = (DataSource) ctx.lookup("java:comp/env/jdbc/mydb");
```
## Restart Glassfish
```
bees app:restart -a my-glassfish3-app
```
# JMX-Invoker
See [RUN@cloud >> CloudBees JMX Invoker](https://developer.cloudbees.com/bin/view/RUN/CloudBees_JMX_Invoker)
| e1ffb98f9905857d5098b5568c23f7cbf6a80228 | [
"Markdown",
"Java",
"Makefile",
"Shell"
] | 6 | Java | CloudBees-community/glassfish3-full-clickstack | 0b29cb94c23a65ab2902866691223b9b03f5fa56 | 3e1d9d941c765b2f3f4311db794030ba1e5c03ab |
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