Add batch 5 (Luthiraa_TALOS-V2, dawsonjon_fpu, The-OpenROAD-Project_OpenROAD-flow-scripts, antonblanchard_microwatt, alexforencich_verilog-i2c)
784ee2c verified FakeRAM2.0
FakeRAM2.0 aims to build a fake memory compiler which can be used by Physical Design research teams to get memory models (Liberty, LEF and Verilog) compatible with the PDK of their choice.
Inputs : configuration file eg. example_input_file.cfg
Run command : python run.py
Originally located at https://github.com/The-OpenROAD-Project/FakeRAM2.0