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784ee2c | 1 2 3 4 5 6 7 8 9 | # FakeRAM2.0
FakeRAM2.0 aims to build a fake memory compiler which can be used by Physical Design research teams to get memory models (Liberty, LEF and Verilog) compatible with the PDK of their choice. <br/>
Inputs : configuration file eg. example_input_file.cfg <br/>
Run command : python run.py <example_input_file name> <br/>
Originally located at https://github.com/The-OpenROAD-Project/FakeRAM2.0
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