verilog_data-1 / The-OpenROAD-Project_OpenROAD-flow-scripts /flow /designs /src /tinyRocket /README.md
Add batch 5 (Luthiraa_TALOS-V2, dawsonjon_fpu, The-OpenROAD-Project_OpenROAD-flow-scripts, antonblanchard_microwatt, alexforencich_verilog-i2c)
784ee2c verified Summary
RISC-V Rocket Chip design (TinyConfig). Currently has about 30,000 cells.
Source
Contributed by Ben Keller on Jun 25 2019. Original source available here.
Modifications
- Use the default TinyConfig.
- Turn the IMem and DMem sizes down to minimum.
- Mapped some memory macros instead.
- Target RocketTile for synthesis, which is the actual processor (this avoids all the system bus overhead included in the top level).
- Added sdc timing constraints.
- Added LICENSE files from here.