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784ee2c | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 | # Summary
RISC-V Rocket Chip design (TinyConfig).
Currently has about 30,000 cells.
# Source
Contributed by Ben Keller on Jun 25 2019.
Original source [available here](https://github.com/chipsalliance/rocket-chip).
# Modifications
- Use the default TinyConfig.
- Turn the IMem and DMem sizes down to minimum.
- Mapped some memory macros instead.
- Target RocketTile for synthesis, which is the actual processor (this avoids all the system bus overhead included in the top level).
- Added sdc timing constraints.
- Added LICENSE files from [here](https://github.com/chipsalliance/rocket-chip).
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