hexsha stringlengths 40 40 | repo stringlengths 7 114 | path stringlengths 4 124 | license listlengths 1 9 | language stringclasses 1
value | identifier stringlengths 1 71 | return_type stringlengths 1 749 ⌀ | original_string stringlengths 76 22.7k | original_docstring stringlengths 16 7.61k | docstring stringlengths 16 2.47k | docstring_tokens listlengths 6 477 | code stringlengths 14 10.2k | code_tokens listlengths 6 996 | short_docstring stringlengths 2 644 | short_docstring_tokens listlengths 1 116 | comment listlengths 1 89 | parameters listlengths 0 64 | docstring_params dict |
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a80ea0e7fffd9d28a84425769522d9a2dccb48f5 | Blebowski/Reg_Map_Gen | ip_xact/h_addr_generator.py | [
"MIT"
] | Python | write_reg_field_enums | null | def write_reg_field_enums(self, reg):
"""
Write enumerated values of all register fields within IP-XACT register
object as C enums. Name of the C enum is:
<prefix>_<register_name>_<field_name>
"""
for (i,field) in enumerate(sorted(reg.field, key=lambda a: a.bitOffset)):
# Skip field if there are no en... |
Write enumerated values of all register fields within IP-XACT register
object as C enums. Name of the C enum is:
<prefix>_<register_name>_<field_name>
| Write enumerated values of all register fields within IP-XACT register
object as C enums. Name of the C enum is:
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] | def write_reg_field_enums(self, reg):
for (i,field) in enumerate(sorted(reg.field, key=lambda a: a.bitOffset)):
if (field.enumeratedValues == []):
continue
enum_elements = self.create_field_enum_decls(field)
enum_name = (self.prefix + "_" + reg.name + "_" + field.name).lower()
self.headerGen.create_en... | [
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a80ea0e7fffd9d28a84425769522d9a2dccb48f5 | Blebowski/Reg_Map_Gen | ip_xact/h_addr_generator.py | [
"MIT"
] | Python | sort_regs_to_wrd_groups | <not_specific> | def sort_regs_to_wrd_groups(self, regs):
"""
Sort list of IP-XACT register objects into groups. Each group is
represented by a list. Each list contains registers located within
a single memory word.
"""
regGroups = [[]]
lowInd = 0
# Sort the registers from field map into sub-lists
for reg in sorted(... |
Sort list of IP-XACT register objects into groups. Each group is
represented by a list. Each list contains registers located within
a single memory word.
| Sort list of IP-XACT register objects into groups. Each group is
represented by a list. Each list contains registers located within
a single memory word. | [
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] | def sort_regs_to_wrd_groups(self, regs):
regGroups = [[]]
lowInd = 0
for reg in sorted(regs, key=lambda a: a.addressOffset):
if (reg.addressOffset >= lowInd + self.wrdWidthByte):
lowInd = reg.addressOffset - reg.addressOffset % 4
regGroups.append([])
regGroups[-1].append(reg)
return regGroups | [
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a80ea0e7fffd9d28a84425769522d9a2dccb48f5 | Blebowski/Reg_Map_Gen | ip_xact/h_addr_generator.py | [
"MIT"
] | Python | write_reg_unions_and_enums | null | def write_reg_unions_and_enums(self, regs):
"""
Write registers from IP-XACT registers object into generator output.
Following artifacts are written:
- union for each memory word with registers
- enums for each enumerated values of register fields
"""
# First sort the registerinto word-aligned groups.
... |
Write registers from IP-XACT registers object into generator output.
Following artifacts are written:
- union for each memory word with registers
- enums for each enumerated values of register fields
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Following artifacts are written:
union for each memory word with registers
enums for each enumerated values of register fields | [
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regGroups = self.sort_regs_to_wrd_groups(regs)
for regGroup in regGroups:
self.write_reg_group_union(regGroup)
for reg in regGroup:
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a80ea0e7fffd9d28a84425769522d9a2dccb48f5 | Blebowski/Reg_Map_Gen | ip_xact/h_addr_generator.py | [
"MIT"
] | Python | write_mem_map_fields | null | def write_mem_map_fields(self):
"""
Process registers within "memBlock" IP-XACT memory block and write to
register output.
"""
for block in self.memMap.addressBlock:
# Skip memory blocks.
if (block.usage == "memory"):
continue
# Write unions and enums of registers within memory block
... |
Process registers within "memBlock" IP-XACT memory block and write to
register output.
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for block in self.memMap.addressBlock:
if (block.usage == "memory"):
continue
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} |
a80ea0e7fffd9d28a84425769522d9a2dccb48f5 | Blebowski/Reg_Map_Gen | ip_xact/h_addr_generator.py | [
"MIT"
] | Python | write_mem_map_addr_enum | null | def write_mem_map_addr_enum(self):
"""
Write addresses of registers within "memBlock" IP-XACT memory block as
enum to generator output.
"""
cmnt = "{} memory map".format(self.memMap.name)
self.headerGen.write_comment(cmnt, 0, small=True)
decls = []
for block in self.memMap.addressBlock:
for reg in... |
Write addresses of registers within "memBlock" IP-XACT memory block as
enum to generator output.
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cmnt = "{} memory map".format(self.memMap.name)
self.headerGen.write_comment(cmnt, 0, small=True)
decls = []
for block in self.memMap.addressBlock:
for reg in sorted(block.register, key=lambda a: a.addressOffset):
decls.append(LanDeclaration((self.prefix + "_" + reg.nam... | [
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a80ea0e7fffd9d28a84425769522d9a2dccb48f5 | Blebowski/Reg_Map_Gen | ip_xact/h_addr_generator.py | [
"MIT"
] | Python | create_addrMap_package | null | def create_addrMap_package(self, name):
"""
Create C header file package for "memMap" IP-XACT memory block.
Package contains:
1. Enum with addresses of each register
2. Unions for each memory word with registers.
3. Enums for each enumerated values of Register fields.
"""
self.headerGen.wr_nl()
sel... |
Create C header file package for "memMap" IP-XACT memory block.
Package contains:
1. Enum with addresses of each register
2. Unions for each memory word with registers.
3. Enums for each enumerated values of Register fields.
| Create C header file package for "memMap" IP-XACT memory block.
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2. Unions for each memory word with registers.
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self.headerGen.wr_nl()
self.headerGen.create_package((self.prefix + "_" + name).upper())
self.headerGen.wr_nl()
if (self.memMap):
print ("Writin... | [
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | is_supported_layout | <not_specific> | def is_supported_layout(self, layout):
"""
Finds out whether the layout is supported by the basic lyx packages.
Arguments:
layout Name of the lyx layout
Returns:
True id supported, False otherwise
"""
for styleGroup in LyxGenerator.supStyles:
for styleIter in styleGroup:
if (styleIter == layou... |
Finds out whether the layout is supported by the basic lyx packages.
Arguments:
layout Name of the lyx layout
Returns:
True id supported, False otherwise
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layout Name of the lyx layout
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | insert_layout | <not_specific> | def insert_layout(self, layout):
"""
Insert lyx layout into the generator output (Chapter, Section etc...)
Arguments:
layout Name of the lyx layout
"""
if (not self.is_supported_layout(layout)):
return False
self.wr_line("\\begin_layout {}\n".format(layout))
self.append_line("\\end_layout\n") |
Insert lyx layout into the generator output (Chapter, Section etc...)
Arguments:
layout Name of the lyx layout
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Arguments:
layout Name of the lyx layout | [
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self.wr_line("\\begin_layout {}\n".format(layout))
self.append_line("\\end_layout\n") | [
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | insert_inset | null | def insert_inset(self, inset, options=[]):
"""
Insert lyx inset into the generator output (Text, Tabular, ERT)
Arguments:
layout Name of the lyx inset.
"""
self.wr_line("\\begin_inset {}\n".format(inset))
for option in options:
self.wr_line("{} {}\n".format(option[0], option[1]))
self.append_line("... |
Insert lyx inset into the generator output (Text, Tabular, ERT)
Arguments:
layout Name of the lyx inset.
| Insert lyx inset into the generator output (Text, Tabular, ERT)
Arguments:
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | insert_table_cell | null | def insert_table_cell(self, cell):
"""
Insert Table cell into the into the generator output.
Arguments:
cell Cell to insert in format:
[cellOptions, cellTextOptions, cellText, cellLabel, cellColor]
where:
cellOptions - Dictionary with cell options such as:
{"alignment":"center", "bottom... |
Insert Table cell into the into the generator output.
Arguments:
cell Cell to insert in format:
[cellOptions, cellTextOptions, cellText, cellLabel, cellColor]
where:
cellOptions - Dictionary with cell options such as:
{"alignment":"center", "bottomline":"true"}
cellTextOptions - Tex... | Insert Table cell into the into the generator output. | [
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] | def insert_table_cell(self, cell):
self.insert_html_table_tag("cell", cell[0], endTag=True)
self.insert_inset("Text")
self.wr_line("\n")
self.write_layout_text("Plain Layout", cell[2], textOptions=cell[1],
label=cell[3], color=cell[4])
self.wr_line("\n")
self.commit_append_line(2) | [
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | insert_table | null | def insert_table(self, table):
"""
Insert lyx table into the generator output.
Arguments:
table Lyx table in the following format:
[tableOptions, tableCells] where:
tableOptions has following format:
[tagName, tagOptions] where:
tagName - name of HTML options tag
t... |
Insert lyx table into the generator output.
Arguments:
table Lyx table in the following format:
[tableOptions, tableCells] where:
tableOptions has following format:
[tagName, tagOptions] where:
tagName - name of HTML options tag
tagOptions - dictionary with HTML tag... | Insert lyx table into the generator output. | [
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] | def insert_table(self, table):
tableOptions = table[0]
cells = table[1]
self.insert_layout("Standard")
self.wr_line("\\noindent\n")
self.wr_line("\\align center\n")
self.insert_inset("Tabular")
tableDimension = {"version" : "3", "rows" : '{}'.format(len(cells)),
"columns" : '{}'.format(len(cells[0]... | [
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | replace_reserved_sign | <not_specific> | def replace_reserved_sign(self, text):
"""
Replace reserved character of "_" in the lyx hypertext function.
Arguments:
text Text to replace the option in
Returns:
Text with reserved characters replaced with according backslash
option.
"""
retVal = ""
for char in text:
if (char == "_"):
re... |
Replace reserved character of "_" in the lyx hypertext function.
Arguments:
text Text to replace the option in
Returns:
Text with reserved characters replaced with according backslash
option.
| Replace reserved character of "_" in the lyx hypertext function.
Arguments:
text Text to replace the option in
Returns:
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retVal = ""
for char in text:
if (char == "_"):
retVal += "\\backslash textunderscore "
elif (char == """\ """):
retVal += "\\"
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | insert_ref | null | def insert_ref(self, labelText, ref):
"""
Insert label or reference into the generator output.
Arguments:
labelText Text to write into the label
ref Label type. At the moment can be:
"label" - LabelText is written and label object is
created directly behind.
"hyperref" - Hyperref ... |
Insert label or reference into the generator output.
Arguments:
labelText Text to write into the label
ref Label type. At the moment can be:
"label" - LabelText is written and label object is
created directly behind.
"hyperref" - Hyperref object is created with
"labelTe... | Insert label or reference into the generator output.
Arguments:
labelText Text to write into the label
ref Label type. At the moment can be:
"label" - LabelText is written and label object is
created directly behind.
"hyperref" - Hyperref object is created with
"labelText" placed in the hyperr... | [
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self.insert_inset("ERT")
self.wr_line("status open\n")
self.insert_layout("Plain Layout")
self.wr_line("\\backslash\n")
if (ref == "label"):
labelStr = "{"+"{}".format(labelText)+"}"
self.wr_line("{}{}".format(ref, labelStr))
if (ref == "hyperref"):
refString =... | [
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | insert_color | null | def insert_color(self, color):
"""
Insert color inset to a table cell
Arguments:
color
"""
self.insert_inset("ERT")
self.wr_line("status open\n")
self.insert_layout("Plain Layout")
self.wr_line("\\backslash\n")
colorStr = "cellcolor{" + color+"}\n"
self.wr_line(colorStr)
self.commit_append... |
Insert color inset to a table cell
Arguments:
color
| Insert color inset to a table cell
Arguments:
color | [
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self.insert_inset("ERT")
self.wr_line("status open\n")
self.insert_layout("Plain Layout")
self.wr_line("\\backslash\n")
colorStr = "cellcolor{" + color+"}\n"
self.wr_line(colorStr)
self.commit_append_line(2) | [
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | write_layout_text | null | def write_layout_text(self, layoutType, text, textOptions=None, label=None,
color=None):
"""
Insert layout type into the generator output and append a simple text.
If text options are specified then the text in the layout is printed
with these options.
Arguments:
layoutType Name of the layout as in... |
Insert layout type into the generator output and append a simple text.
If text options are specified then the text in the layout is printed
with these options.
Arguments:
layoutType Name of the layout as in "insert_layout"
text Text to be written in the layout.
textOptions Text options as specifie... | Insert layout type into the generator output and append a simple text.
If text options are specified then the text in the layout is printed
with these options.
Arguments:
layoutType Name of the layout as in "insert_layout"
text Text to be written in the layout.
textOptions Te... | [
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self.insert_text_options(textOptions)
if (label == "hyperref"):
self.insert_ref(text, label)
elif (label != None):
self.wr_line(text)
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | build_table_options | <not_specific> | def build_table_options(self, columnCount, rowCount, longTable=False):
"""
Creates default table options object with default column alignment
set to center of the cell.
Arguments:
columnCount Number of table columns
rowCount Number of table rows
Returns:
New table options object which can be used i... |
Creates default table options object with default column alignment
set to center of the cell.
Arguments:
columnCount Number of table columns
rowCount Number of table rows
Returns:
New table options object which can be used in "insert_html_table_tag"
function.
| Creates default table options object with default column alignment
set to center of the cell.
Arguments:
columnCount Number of table columns
rowCount Number of table rows
Returns:
New table options object which can be used in "insert_html_table_tag"
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | build_table_cells | <not_specific> | def build_table_cells(self, columnCount, rowCount, defCellText):
"""
Creates default table cell objects with standard cell attributes.
Arguments:
columnCount Number of table columns
rowCount Number of table rows
defCellText Text which should be put to the cell by default.
Returns:
New table cells... |
Creates default table cell objects with standard cell attributes.
Arguments:
columnCount Number of table columns
rowCount Number of table rows
defCellText Text which should be put to the cell by default.
Returns:
New table cells object which has the structure as tableCells in
the table argument... | Creates default table cell objects with standard cell attributes.
Arguments:
columnCount Number of table columns
rowCount Number of table rows
defCellText Text which should be put to the cell by default.
Returns:
New table cells object which has the structure as tableCells in
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | build_table | <not_specific> | def build_table(self, columnCount, rowCount, defCellText="Reserved", longTable=False):
"""
Builds the table
Arguments:
columnCount Number of table columns
rowCount Number of table rows
defCellText Text which should be put to the cell by default.
Returns:
New table object with structure as "table... |
Builds the table
Arguments:
columnCount Number of table columns
rowCount Number of table rows
defCellText Text which should be put to the cell by default.
Returns:
New table object with structure as "table" argument in "insert_table"
function.
| Builds the table
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columnCount Number of table columns
rowCount Number of table rows
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | insert_new_page | null | def insert_new_page(self):
"""
Write new page into the generator output.
"""
self.insert_layout("Standard")
self.insert_inset("Newpage newpage")
self.commit_append_line(2) |
Write new page into the generator output.
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | write_comm_line | null | def write_comm_line(self, gap=2):
"""
Write comment line to the lyx document
"""
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e6f45d794ee4ac7292c7336604536894efbd7955 | Blebowski/Reg_Map_Gen | languages/gen_lyx.py | [
"MIT"
] | Python | write_comment | null | def write_comment(self, input, gap, caption=None, small=False):
"""
Write comment to the lyx document
"""
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
"MIT"
] | Python | write_comm_line | null | def write_comm_line(self, gap=2):
"""
Write C comment line in format: (gap)/******/ aligned to 80 characters
Arguments:
gap Number of tabs before the comment line
"""
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Write C comment line in format: (gap)/******/ aligned to 80 characters
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gap Number of tabs before the comment line | [
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
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] | Python | write_comment | <not_specific> | def write_comment(self, input, gap, caption=None, small=False):
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Write C comment line aligned to 80 characters in format:
/* COMMENT */
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/*
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gap Number of tabs before the comment
caption Caption to append to the ... |
Write C comment line aligned to 80 characters in format:
/* COMMENT */
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/*
* COMMENT LONGER THAN 80 CHARACTERS SPLIT BETWEEN LINES
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Arguments:
gap Number of tabs before the comment
caption Caption to append to the comment in the first line
small So far no meaning for C implement... | Write C comment line aligned to 80 characters in format:
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small So far no meaning for C implementation | [
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return None
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
"MIT"
] | Python | create_enum | null | def create_enum(self, name, decls):
"""
Create a C enum. Align to the maximum declaration name within the
elements declaration list.
Arguments:
name Enum name
decls List of enum elements as declarations
"""
self.__wr_line("enum {} {}\n".format(name, "{"))
# Check the maximum string length in t... |
Create a C enum. Align to the maximum declaration name within the
elements declaration list.
Arguments:
name Enum name
decls List of enum elements as declarations
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
"MIT"
] | Python | write_decl | <not_specific> | def write_decl(self, decl):
"""
Create simple C declaration. This function supports:
- simple variable declaration (initialized, non-initialized)
- enum element declaration (value must be specified on declarations)
- bitfield element declaration (bitWidth must be specified)
Arguments:
decl Declarati... |
Create simple C declaration. This function supports:
- simple variable declaration (initialized, non-initialized)
- enum element declaration (value must be specified on declarations)
- bitfield element declaration (bitWidth must be specified)
Arguments:
decl Declaration to create
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decl Declaration to create | [
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
"MIT"
] | Python | __write_structure_norm | null | def __write_structure_norm(self, decls):
"""
Write structure declaration without bitfields
Arguments:
decls Structure elements
"""
for decl in decls:
self.write_decl(decl) |
Write structure declaration without bitfields
Arguments:
decls Structure elements
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decls Structure elements | [
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
"MIT"
] | Python | __insert_rsvd_bitfield | <not_specific> | def __insert_rsvd_bitfield(self, decls, neighbour, index):
"""
Fill the declarations list with reserved bitfields on missing indices.
Arguments:
decls List of declarations to extend
neighbour Neighbour to copy the element declaration into the
reserved field declaration
index Last filled bit by... |
Fill the declarations list with reserved bitfields on missing indices.
Arguments:
decls List of declarations to extend
neighbour Neighbour to copy the element declaration into the
reserved field declaration
index Last filled bit by previous declaration
Returns:
Index of last filled bit wit... | Fill the declarations list with reserved bitfields on missing indices.
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decls List of declarations to extend
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decl = copy.copy(neighbour)
high = ""
if (neighbour.bitIndex - index > 1):
high = "_{}".format(neighbour.bitIndex - 1)
decl.name = "reserved{}_{}".format(high, index)
decl.bitIndex = index
decl.comment = None
decl.bitWidth = neighbour.bitIndex ... | [
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
"MIT"
] | Python | __write_structure_bitfields | null | def __write_structure_bitfields(self, decls, bitFieldWidth):
"""
Create structure declaration with bitfields.
Arguments:
decls List of declarations describing the structure
elements
bitFieldWidth Width of the bitfield to create
"""
# Copy the list of declarations and insert the reserved valu... |
Create structure declaration with bitfields.
Arguments:
decls List of declarations describing the structure
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bitFieldWidth Width of the bitfield to create
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bitFieldWidth Width of the bitfield to create | [
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tmp = copy.copy(decls)
index = 0
tmp.append(copy.copy(tmp[-1]))
tmp[-1].bitIndex = bitFieldWidth
for item in tmp:
if (item.bitIndex > index):
index = self.__insert_rsvd_bitfield(tmp, item, index)
else:
index = index + item.bitWidth
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
"MIT"
] | Python | __get_type_size | <not_specific> | def __get_type_size(self, type):
"""
Get bit size of given type
Arguments:
type Declaration type to get the size
Returns:
Bit size of the given type
"""
if (not self.is_supported_type(type)):
return 0
for i,iter in enumerate(self.supportedTypes):
if (iter == type):
return self.typeSize... |
Get bit size of given type
Arguments:
type Declaration type to get the size
Returns:
Bit size of the given type
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Arguments:
type Declaration type to get the size
Returns:
Bit size of the given type | [
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if (not self.is_supported_type(type)):
return 0
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if (iter == type):
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
"MIT"
] | Python | create_union | null | def create_union(self, name, decls):
"""
Create union with declarations.
Arguments:
name Union name
decls List with declarations contained within the union.
"""
self.__wr_line("{}union {} {}\n".format(" " * (decls[0].gap - 1),
name, "{"))
for decl in decls:
# Recursive
if (type(decl... |
Create union with declarations.
Arguments:
name Union name
decls List with declarations contained within the union.
| Create union with declarations.
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name Union name
decls List with declarations contained within the union. | [
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self.__wr_line("{}union {} {}\n".format(" " * (decls[0].gap - 1),
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for decl in decls:
if (type(decl) == list):
self.create_structure(name + "_s", decl)
else:
self.write_decl(decl)
self.__wr_line("{}{};\n".format(" " * (decls[0].gap - 1), "}")) | [
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
"MIT"
] | Python | create_structure | null | def create_structure(self, name, decls):
"""
Create structure, either with or without bitfields.
Arguments:
name structure name
decls List with declarations contained within the structure.
"""
self.__wr_line("{}struct {} {}\n".format(" " * (decls[0].gap - 1),
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Create structure, either with or without bitfields.
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name structure name
decls List with declarations contained within the structure. | [
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fd96c1834c07117b5394fc973aeb9523c10e9489 | Blebowski/Reg_Map_Gen | languages/gen_h.py | [
"MIT"
] | Python | create_includes | null | def create_includes(self, includeList):
"""
Create C header includes.
Arguments:
includeList List of C includes
"""
for include in includeList:
self.__wr_line("#include {}\n") |
Create C header includes.
Arguments:
includeList List of C includes
| Create C header includes.
Arguments:
includeList List of C includes | [
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for include in includeList:
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2acb01c0bfd19c438ad0fafacb6cdc89fedf9d45 | Blebowski/Reg_Map_Gen | ip_xact/kern_h_addr_generator.py | [
"MIT"
] | Python | write_mem_map_addr_enum | null | def write_mem_map_addr_enum(self):
"""
Write addresses of registers within "memBlock" IP-XACT memory block as
enum to generator output.
"""
cmnt = "{} memory map".format(self.memMap.name)
self.headerGen.write_comment(cmnt, 0, small=True)
decls = []
for block in self.memMap.addressBlock:
for reg in s... |
Write addresses of registers within "memBlock" IP-XACT memory block as
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cmnt = "{} memory map".format(self.memMap.name)
self.headerGen.write_comment(cmnt, 0, small=True)
decls = []
for block in self.memMap.addressBlock:
for reg in sorted(block.register, key=lambda a: a.addressOffset):
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2acb01c0bfd19c438ad0fafacb6cdc89fedf9d45 | Blebowski/Reg_Map_Gen | ip_xact/kern_h_addr_generator.py | [
"MIT"
] | Python | create_addrMap_package | null | def create_addrMap_package(self, name):
"""
Create C header file package for "memMap" IP-XACT memory block.
Package contains for each register within memory block:
1. Define with register address offset.
2. Defines for each register field.
"""
self.headerGen.wr_nl()
self.headerGen.write_comment("This ... |
Create C header file package for "memMap" IP-XACT memory block.
Package contains for each register within memory block:
1. Define with register address offset.
2. Defines for each register field.
| Create C header file package for "memMap" IP-XACT memory block.
Package contains for each register within memory block:
1. Define with register address offset.
2. Defines for each register field. | [
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self.headerGen.wr_nl()
self.headerGen.create_package((self.prefix + "_" + name).upper())
self.headerGen.wr_nl()
self.headerGen.write_include("linux/bits.h")
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | commit_to_file | null | def commit_to_file(self):
"""
Commit the generator output into the output file.
"""
for line in self.hdlGen.out :
self.of.write(line)
self.hdlGen.out = [] |
Commit the generator output into the output file.
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for line in self.hdlGen.out :
self.of.write(line)
self.hdlGen.out = [] | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_reg_ports | <not_specific> | def create_reg_ports(self, block, signDict):
"""
Creates declarations for Output/Input ports of an entity which
correspond to values Written / Read to / from registers.
Declarations have following format:
signal <block_name>_in : in <block_name>_in_t
signal <block_name>_out : in <block_name>_out_t
... |
Creates declarations for Output/Input ports of an entity which
correspond to values Written / Read to / from registers.
Declarations have following format:
signal <block_name>_in : in <block_name>_in_t
signal <block_name>_out : in <block_name>_out_t
Declarations are appended to signDict dictionary.
... | Creates declarations for Output/Input ports of an entity which
correspond to values Written / Read to / from registers.
Declarations have following format:
signal _in : in _in_t
signal _out : in _out_t
Declarations are appended to signDict dictionary. | [
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if (not checkIsDict(signDict)):
return
reg_ports = ["out", "in"]
for reg_port in reg_ports:
port = LanDeclaration(block.name + "_" + reg_port, value=None)
port.direction = reg_port
port.type = block.name + "_" + reg_port + "_t"
port.bitWidth = 0
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_wr_reg_sel_decl | null | def create_wr_reg_sel_decl(self, block, signDict):
"""
Create declaration of register selector signal for writable
registers within a memory block. Width of register selector is number of
words within a block which contain at least one writable register.
"""
signDict["reg_sel"] = LanDeclaration("reg_sel", v... |
Create declaration of register selector signal for writable
registers within a memory block. Width of register selector is number of
words within a block which contain at least one writable register.
| Create declaration of register selector signal for writable
registers within a memory block. Width of register selector is number of
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signDict["reg_sel"] = LanDeclaration("reg_sel", value = None)
signDict["reg_sel"].type = "std_logic"
signDict["reg_sel"].specifier = "signal"
signDict["reg_sel"].bitWidth = self.calc_blk_wrd_count(block) | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | calc_addr_vect_value | <not_specific> | def calc_addr_vect_value(self, block):
"""
Calculate address vector value for address decoder for reach register
word.
"""
vect_val = ""
addr_entry_width = self.calc_wrd_address_width(block)
# Check if register is present on a given word, if yes, append it to the
# vector.
[low_addr, high_addr] = sel... |
Calculate address vector value for address decoder for reach register
word.
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] | def calc_addr_vect_value(self, block):
vect_val = ""
addr_entry_width = self.calc_wrd_address_width(block)
[low_addr, high_addr] = self.calc_blk_wrd_span(block)
high_addr += self.wrdWidthByte
for wrd_addr in range(low_addr, high_addr, self.wrdWidthByte):
regs_in_wrd = self.get_regs_from_word(wrd_addr, bloc... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_addr_vect_decl | null | def create_addr_vect_decl(self, block, signDict):
"""
Create declaration of Address vector constant which is an input to
Address decoder.
"""
signDict["addr_vect"] = LanDeclaration("addr_vect", value = None)
signDict["addr_vect"].type = "std_logic"
signDict["addr_vect"].specifier = "constant"
signDict["... |
Create declaration of Address vector constant which is an input to
Address decoder.
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signDict["addr_vect"] = LanDeclaration("addr_vect", value = None)
signDict["addr_vect"].type = "std_logic"
signDict["addr_vect"].specifier = "constant"
signDict["addr_vect"].value = self.calc_addr_vect_value(block)
addr_vect_size = self.calc_blk_wrd_count(bloc... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_read_data_mux_in_decl | null | def create_read_data_mux_in_decl(self, block, signDict):
"""
Create declaration of read data multiplexor input signal. Length of
read data mux input covers the minimum necessary length to cover
all words with readable registers.
"""
signDict["read_data_mux_in"] = LanDeclaration("read_data_mux_in", value = N... |
Create declaration of read data multiplexor input signal. Length of
read data mux input covers the minimum necessary length to cover
all words with readable registers.
| Create declaration of read data multiplexor input signal. Length of
read data mux input covers the minimum necessary length to cover
all words with readable registers. | [
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signDict["read_data_mux_in"] = LanDeclaration("read_data_mux_in", value = None)
signDict["read_data_mux_in"].type = "std_logic"
[low_addr, high_addr] = self.calc_blk_wrd_span(block, ["read"])
high_addr += self.wrdWidthByte
signDict["read_data_mux_in"].b... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_read_data_mask_n_decl | null | def create_read_data_mask_n_decl(self, block, signDict):
"""
Create declaration of Read data mask signal for Read data multiplexor.
"""
signDict["read_data_mask_n"] = LanDeclaration("read_data_mask_n", value = None)
signDict["read_data_mask_n"].type = "std_logic"
signDict["read_data_mask_n"].bitWidth = self... |
Create declaration of Read data mask signal for Read data multiplexor.
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] | def create_read_data_mask_n_decl(self, block, signDict):
signDict["read_data_mask_n"] = LanDeclaration("read_data_mask_n", value = None)
signDict["read_data_mask_n"].type = "std_logic"
signDict["read_data_mask_n"].bitWidth = self.wrdWidthBit
signDict["read_data_mask_n"].specifier = "signal" | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_write_data_int_decl | null | def create_write_data_int_decl(self, block, signDict):
"""
Create declaration for internal record with data written to writable
registers.
"""
name = block.name + "_out"
signDict[name + "_i"] = LanDeclaration(name + "_i", value = None)
signDict[name + "_i"].type = name + "_t"
signDict[name + "_i"].speci... |
Create declaration for internal record with data written to writable
registers.
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] | def create_write_data_int_decl(self, block, signDict):
name = block.name + "_out"
signDict[name + "_i"] = LanDeclaration(name + "_i", value = None)
signDict[name + "_i"].type = name + "_t"
signDict[name + "_i"].specifier = "signal" | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_read_mux_ena_int_decl | null | def create_read_mux_ena_int_decl(self, signDict):
"""
Create declaration for read data multiplexor enable. This allows keeping
or clearing read data signal after data were read.
"""
signDict["read_mux_ena"] = LanDeclaration("read_mux_ena", value = None)
signDict["read_mux_ena"].type = "std_logic"
signDict... |
Create declaration for read data multiplexor enable. This allows keeping
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signDict["read_mux_ena"] = LanDeclaration("read_mux_ena", value = None)
signDict["read_mux_ena"].type = "std_logic"
signDict["read_mux_ena"].bitWidth = 1
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_internal_decls | <not_specific> | def create_internal_decls(self, block, signDict):
"""
Create declarations of internal signals of architecture of register
memory block. Following declarations are created:
- Write selector signal for all writable registers
- Address vector input to address decoder
- Read data multiplexor input vector.
... |
Create declarations of internal signals of architecture of register
memory block. Following declarations are created:
- Write selector signal for all writable registers
- Address vector input to address decoder
- Read data multiplexor input vector.
- Read data mask signal from byte enable signals
... | Create declarations of internal signals of architecture of register
memory block. Following declarations are created:
Write selector signal for all writable registers
Address vector input to address decoder
Read data multiplexor input vector.
Read data mask signal from byte enable signals
Internal signal for output reg... | [
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if (not checkIsDict(signDict)):
return;
self.create_wr_reg_sel_decl(block, signDict)
self.create_addr_vect_decl(block, signDict)
self.create_read_data_mux_in_decl(block, signDict)
self.create_read_data_mask_n_decl(block, signDict)
self.create_write_data_... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | append_reg_byte_val | <not_specific> | def append_reg_byte_val(self, block, reg, byte_ind, read_wrd):
"""
Append name of a register if it is located on a given byte within a
memory word.
Returns:
[pad_zeroes, read_wrd]
pad_zeroes - If zeores should be padded instead of this register
read_wrd - Appended value of word value
"""
reg_offs... |
Append name of a register if it is located on a given byte within a
memory word.
Returns:
[pad_zeroes, read_wrd]
pad_zeroes - If zeores should be padded instead of this register
read_wrd - Appended value of word value
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reg_offset = reg.addressOffset % self.wrdWidthByte
reg_bytes = reg.size / 8
if (reg_offset == byte_ind):
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appendix = "_out_i."
else:
appendix = "_in."
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_read_wrd_from_regs | <not_specific> | def create_read_wrd_from_regs(self, regs_in_wrd, block):
"""
Create single read word input to read data multiplexor input. Readable
registers are implemented.
"""
read_wrd = " "
for byte_ind in range(self.wrdWidthByte - 1, -1, -1):
pad_zeroes = True
for reg in regs_in_wrd:
# Skip registers w... |
Create single read word input to read data multiplexor input. Readable
registers are implemented.
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read_wrd = " "
for byte_ind in range(self.wrdWidthByte - 1, -1, -1):
pad_zeroes = True
for reg in regs_in_wrd:
if (not (self.reg_has_access_type(reg, ["read"]))):
continue;
[pad_zeroes, read_wrd] = self.append_reg_byte_val(block, reg,
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_read_data_mux_in | null | def create_read_data_mux_in(self, block):
"""
Create driver for read data multiplexor input signal. Read data
multiplexor is a long vector with read data concatenated to
long std_logic vector.
"""
self.hdlGen.write_comment("Read data driver", gap = 2)
self.hdlGen.push_parallel_assignment("read_data_mux_in... |
Create driver for read data multiplexor input signal. Read data
multiplexor is a long vector with read data concatenated to
long std_logic vector.
| Create driver for read data multiplexor input signal. Read data
multiplexor is a long vector with read data concatenated to
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self.hdlGen.write_comment("Read data driver", gap = 2)
self.hdlGen.push_parallel_assignment("read_data_mux_in")
self.hdlGen.wr_line("\n")
[low_addr, high_addr] = self.calc_blk_wrd_span(block, ["read"])
high_addr += self.wrdWidthByte
for addr in reversed(range(low_ad... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | calc_addr_indices | <not_specific> | def calc_addr_indices(self, block):
"""
Calculates low and high index of address vector necessary for addressing
given memory block. Each word is addressed and LSBs of address to address
within a word is truncated.
"""
addr_lind = self.calc_addr_width_from_size(self.wrdWidthByte)
addr_hi... |
Calculates low and high index of address vector necessary for addressing
given memory block. Each word is addressed and LSBs of address to address
within a word is truncated.
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given memory block. Each word is addressed and LSBs of address to address
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addr_lind = self.calc_addr_width_from_size(self.wrdWidthByte)
addr_hind = self.calc_addr_width_from_size(block.range) - 1
return [addr_hind, addr_lind] | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_addr_decoder | null | def create_addr_decoder(self, block):
"""
Create instance of address decoder for writable registers.
"""
path = os.path.join(ROOT_PATH, self.template_sources["addr_dec_template_path"])
addr_dec = self.hdlGen.load_entity_template(path)
addr_dec.isInstance = True
addr_dec.value = addr_dec.name.lower(... |
Create instance of address decoder for writable registers.
| Create instance of address decoder for writable registers. | [
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] | def create_addr_decoder(self, block):
path = os.path.join(ROOT_PATH, self.template_sources["addr_dec_template_path"])
addr_dec = self.hdlGen.load_entity_template(path)
addr_dec.isInstance = True
addr_dec.value = addr_dec.name.lower() + "_" + block.name.lower() + "_comp"
addr_dec.gap = 2
addr_dec.generics["a... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | calc_reg_data_mask | <not_specific> | def calc_reg_data_mask(self, reg):
"""
Calculates data mask of given register. Data mask contains "1" for each bit
which is implemented in the register, "0" for each bit which is not
implemented in a register.
"""
# Suppose there is no implemented register
data_mask = ["0" for x in range(reg.size)]... |
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | calc_autoclear_mask | <not_specific> | def calc_autoclear_mask(self, reg):
"""
Calculate mask for autoclear feature of memory register. Bits of memory
register marked as "clear" in "write action" will be automatically cleared
after write (One-shot like).
"""
# Suppose no bit is autoclear
autoclearMask = ["0" for x in range(reg.size)]
# Go t... |
Calculate mask for autoclear feature of memory register. Bits of memory
register marked as "clear" in "write action" will be automatically cleared
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | calc_reg_byte_enable_vector | <not_specific> | def calc_reg_byte_enable_vector(self, reg):
"""
Create byte enable vector for a register. Position of register within
a memory word is considered.
"""
l_be_ind = reg.addressOffset % 4
h_be_ind = l_be_ind + int(reg.size / 8) - 1
return self.hdlGen.format_vector_range("be", h_be_ind, l_be_ind) |
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] | def calc_reg_byte_enable_vector(self, reg):
l_be_ind = reg.addressOffset % 4
h_be_ind = l_be_ind + int(reg.size / 8) - 1
return self.hdlGen.format_vector_range("be", h_be_ind, l_be_ind) | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | fill_reg_inst_generics | null | def fill_reg_inst_generics(self, reg, reg_inst):
"""
Fill Generic values of VHDL register instance from IP-XACT register
object.
"""
reg_inst.generics["data_width"].value = reg.size
reg_inst.generics["data_mask"].value = self.calc_reg_data_mask(reg)
reg_inst.generics["reset_polarity"].value = "reset_polar... |
Fill Generic values of VHDL register instance from IP-XACT register
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] | def fill_reg_inst_generics(self, reg, reg_inst):
reg_inst.generics["data_width"].value = reg.size
reg_inst.generics["data_mask"].value = self.calc_reg_data_mask(reg)
reg_inst.generics["reset_polarity"].value = "reset_polarity".upper()
reg_inst.generics["reset_value"].value = self.calc_reg_rstval_mask(reg)
reg... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | fill_reg_ports | null | def fill_reg_ports(self, block, reg, reg_inst):
"""
Fill ports for register instance from IP-XACT register object
"""
reg_inst.ports["clk_sys"].value = "clk_sys"
reg_inst.ports["res_n"].value = "res_n"
reg_value = (block.name + "_out_i." + reg.name).lower()
reg_inst.ports["reg_value"].value = reg_value
... |
Fill ports for register instance from IP-XACT register object
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reg_inst.ports["clk_sys"].value = "clk_sys"
reg_inst.ports["res_n"].value = "res_n"
reg_value = (block.name + "_out_i." + reg.name).lower()
reg_inst.ports["reg_value"].value = reg_value
l_ind = (reg.addressOffset * 8) % self.wrdWidthBit
h_ind = l_ind + reg.siz... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_reg_instance | null | def create_reg_instance(self, block, reg):
"""
Create register instance from IP-XACT register object. If "isPresent" property
is set, parameter name is searched in IP-XACT input and it's name is used
as generic condition for register presence.
"""
# Load register template path and create basic i... |
Create register instance from IP-XACT register object. If "isPresent" property
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path = os.path.join(ROOT_PATH, self.template_sources["reg_template_path"])
reg_inst = self.hdlGen.load_entity_template(path)
reg_inst.isInstance = True
reg_inst.intType = "entity"
reg_inst.value = reg.name.lower() + "_reg_comp"
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | fill_access_signaller_generics | null | def fill_access_signaller_generics(self, reg, signaller_inst):
"""
Fill generics for VHDL access signaller instance from IP-XACT register
object.
"""
signaller_inst.generics["reset_polarity"].value = "reset_polarity".upper()
signaller_inst.generics["data_width"].value = reg.size
# Read signalling capabil... |
Fill generics for VHDL access signaller instance from IP-XACT register
object.
| Fill generics for VHDL access signaller instance from IP-XACT register
object. | [
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] | def fill_access_signaller_generics(self, reg, signaller_inst):
signaller_inst.generics["reset_polarity"].value = "reset_polarity".upper()
signaller_inst.generics["data_width"].value = reg.size
if (self.is_reg_read_indicate(reg)):
signaller_inst.generics["read_signalling"].value = True
else:
signaller_inst... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | fill_access_signaller_ports | null | def fill_access_signaller_ports(self, block, reg, signaller_inst):
"""
Fill ports for VHDL access signaller instance from IP-XACT register
object.
"""
signaller_inst.ports["clk_sys"].value = "clk_sys"
signaller_inst.ports["res_n"].value = "res_n"
# Get word index from address decoder
reg_sel_index = se... |
Fill ports for VHDL access signaller instance from IP-XACT register
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] | def fill_access_signaller_ports(self, block, reg, signaller_inst):
signaller_inst.ports["clk_sys"].value = "clk_sys"
signaller_inst.ports["res_n"].value = "res_n"
reg_sel_index = self.get_wrd_index(block, reg) - 1
signaller_inst.ports["cs"].value = \
self.hdlGen.format_vector_index("reg_sel", reg_sel_index)
... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_access_signaller | null | def create_access_signaller(self, block, reg):
"""
Create access signaller components for registers which have this feature
enabled.
"""
path = os.path.join(ROOT_PATH, self.template_sources["access_signaller_template_path"])
signaller_inst = self.hdlGen.load_entity_template(path)
signaller_inst.isInstance... |
Create access signaller components for registers which have this feature
enabled.
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path = os.path.join(ROOT_PATH, self.template_sources["access_signaller_template_path"])
signaller_inst = self.hdlGen.load_entity_template(path)
signaller_inst.isInstance = True
signaller_inst.intType = "entity"
signaller_inst.value = reg.name.lower() + "_access_s... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_write_reg_instances | null | def create_write_reg_instances(self, block):
"""
Create VHDL instance for each writable register in a memory block.
"""
for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):
# Create register instances for writable registers
if (self.reg_has_access_type(reg, ["write"])):
self... |
Create VHDL instance for each writable register in a memory block.
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for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):
if (self.reg_has_access_type(reg, ["write"])):
self.create_reg_instance(block, reg)
if (self.is_reg_write_indicate(reg) or self.is_reg_read_indicate(reg)):
self.create_access_signa... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_read_data_mux_instance | null | def create_read_data_mux_instance(self, block):
"""
Create instance of Read data multiplexor.
"""
path = os.path.join(ROOT_PATH, self.template_sources["data_mux_template_path"])
# Load data mux template
data_mux = self.hdlGen.load_entity_template(path)
data_mux.isInstance = True
data_mux.value = ... |
Create instance of Read data multiplexor.
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path = os.path.join(ROOT_PATH, self.template_sources["data_mux_template_path"])
data_mux = self.hdlGen.load_entity_template(path)
data_mux.isInstance = True
data_mux.value = (data_mux.name + "_"+ block.name + "_comp").lower()
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_read_data_mask_driver | null | def create_read_data_mask_driver(self):
"""
Create driver for read data mask signal from byte enable inputs of memory
bus.
"""
self.hdlGen.write_comment("Read data mask - Byte enables", gap = 4)
self.hdlGen.push_parallel_assignment(signalName = "read_data_mask_n", gap = 4)
wrd_line = ""
byte_lst = []
... |
Create driver for read data mask signal from byte enable inputs of memory
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] | def create_read_data_mask_driver(self):
self.hdlGen.write_comment("Read data mask - Byte enables", gap = 4)
self.hdlGen.push_parallel_assignment(signalName = "read_data_mask_n", gap = 4)
wrd_line = ""
byte_lst = []
for byte in range(self.wrdWidthByte - 1, -1, -1):
be_ind = self.hdlGen.format_vector_index("... | [
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} |
99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_reg_cond_generics | null | def create_reg_cond_generics(self, block, entity):
"""
Add conditional generic definitions into entity declaration. Parameter
"isPresent" of each IP-XACT register is added as generic boolean input.
Parameter look-up is performed for each found parameter.
"""
for reg in block.register:
if (reg.isPresent !... |
Add conditional generic definitions into entity declaration. Parameter
"isPresent" of each IP-XACT register is added as generic boolean input.
Parameter look-up is performed for each found parameter.
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for reg in block.register:
if (reg.isPresent != ""):
paramName = self.parameter_lookup(reg.isPresent)
entity.generics[paramName] = LanDeclaration(paramName, value = 0)
entity.generics[paramName].value = "true"
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_reg_block_template | <not_specific> | def create_reg_block_template(self, block):
"""
Load memory bus entity template, add ports for register inputs, outputs.
Create declaration of register block entity.
"""
# Load memory bus template and create entity definition
path = os.path.join(ROOT_PATH, self.template_sources["mem_bus_template_path"])
e... |
Load memory bus entity template, add ports for register inputs, outputs.
Create declaration of register block entity.
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] | def create_reg_block_template(self, block):
path = os.path.join(ROOT_PATH, self.template_sources["mem_bus_template_path"])
entity = self.hdlGen.load_entity_template(path)
entity.intType = "entity"
entity.isInstance = False
entity.name = block.name.lower() + "_reg_map"
self.create_reg_ports(block, entity.p... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_write_reg_record_driver | null | def create_write_reg_record_driver(self, block):
"""
Create driver for write registe record. Internal signal is connected
to output port.
"""
dest = block.name + "_out"
src = dest + "_i"
self.hdlGen.create_signal_connection(dest, src, gap = 4) |
Create driver for write registe record. Internal signal is connected
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] | def create_write_reg_record_driver(self, block):
dest = block.name + "_out"
src = dest + "_i"
self.hdlGen.create_signal_connection(dest, src, gap = 4) | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_reg_access_cover_point | null | def create_reg_access_cover_point(self, block, reg, acc_type):
"""
Create cover point for write/read to/from a register.
"""
# Get index of memory word for the register
reg_sel_index = self.get_wrd_index(block, reg) - 1
# Calcuate byte enable indices
l_be_ind = reg.addressOffset % 4
h_be_ind = l_be_ind... |
Create cover point for write/read to/from a register.
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] | def create_reg_access_cover_point(self, block, reg, acc_type):
reg_sel_index = self.get_wrd_index(block, reg) - 1
l_be_ind = reg.addressOffset % 4
h_be_ind = l_be_ind + int(reg.size / 8) - 1
be_lst = []
for i in range(l_be_ind, h_be_ind + 1):
be_lst.append(self.hdlGen.format_logic_op(
[self.hdlGe... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_reg_access_cover_points | null | def create_reg_access_cover_points(self, block):
"""
Create cover points to monitor functional coverage within the
generated block. Following points are created:
1. Write cover point for each writable register.
2. Read cover point for each readable register.
"""
# Add comments for readabiliy
self.hdlG... |
Create cover points to monitor functional coverage within the
generated block. Following points are created:
1. Write cover point for each writable register.
2. Read cover point for each readable register.
| Create cover points to monitor functional coverage within the
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2. Read cover point for each readable register. | [
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self.hdlGen.write_comment("<RELEASE_OFF>", gap = 4, small=True)
self.hdlGen.write_comment("Functional coverage", gap = 4)
if (type(self.hdlGen) == VhdlGenerator):
self.hdlGen.write_comment(" psl default clock is " \
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_read_data_mux_ena | null | def create_read_data_mux_ena(self):
"""
Create driver for read data multiplexor enable signal. If read data
should be cleared after transaction, enable is constantly at logic 1,
thus next cycle will data will be cleared, read mux output flop is
permanently enabled. If read data should not be cleared, flop is... |
Create driver for read data multiplexor enable signal. If read data
should be cleared after transaction, enable is constantly at logic 1,
thus next cycle will data will be cleared, read mux output flop is
permanently enabled. If read data should not be cleared, flop is
enabled only by new transaction.
| Create driver for read data multiplexor enable signal. If read data
should be cleared after transaction, enable is constantly at logic 1,
thus next cycle will data will be cleared, read mux output flop is
permanently enabled. If read data should not be cleared, flop is
enabled only by new transaction. | [
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self.hdlGen.write_comment("Read data multiplexor enable ", gap = 4)
self.hdlGen.create_if_generate(name="read_data_keep_gen",
condition="clear_read_data".upper(), value="false", gap = 4)
self.hdlGen.create_signal_connection(result="read_mux_ena",
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} |
99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | write_reg_block | null | def write_reg_block(self, block):
"""
Create register block in VHDL from IP-XACT memory block object.
"""
# Write file introduction
self.hdlGen.wr_nl()
self.hdlGen.write_comment("Register map implementation of: " +
block.name, gap = 0)
self.hdlGen.write_gen_note()
self.hdlGen.wr_nl()
if (... |
Create register block in VHDL from IP-XACT memory block object.
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self.hdlGen.wr_nl()
self.hdlGen.write_comment("Register map implementation of: " +
block.name, gap = 0)
self.hdlGen.write_gen_note()
self.hdlGen.wr_nl()
if (type(self.hdlGen) == VhdlGenerator):
self.hdlGen.create_includes("ieee", ["std_logic_1164.all"])
self.hdlGen.... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_output_reg_record | null | def create_output_reg_record(self, block):
"""
Create record for writable registers from IP-XACT memory block object.
If register write should be indicated, additional <reg_name>_write signal
is added.
If register read should be indicated, additional <reg_name>_read signal is
added.
"""
outDecls = []
... |
Create record for writable registers from IP-XACT memory block object.
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If register read should be indicated, additional <reg_name>_read signal is
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If register read should be indicated, additional _read signal is
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outDecls = []
outName = block.name + "_out_t"
for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):
if ("write" in reg.access):
outDecls.append(LanDeclaration(reg.name, value=""))
outDecls[-1].type = "std_logic_vector"
outDecls[-1]... | [
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_input_reg_record | null | def create_input_reg_record(self, block):
"""
Create record for readable registers from IP-XACT memory block object.
"""
# Input Declarations record
inDecls = []
inName = block.name + "_in_t"
for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):
# All registers with read, but... |
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | create_mem_block_records | null | def create_mem_block_records(self, block):
"""
Create records for register module input/outputs. Each writable
register is present in "write record". Each readable register is
present in a read record.
"""
self.hdlGen.wr_nl()
self.create_output_reg_record(block)
self.hdlGen.wr_nl()
self.hdlGen.wr_n... |
Create records for register module input/outputs. Each writable
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self.create_output_reg_record(block)
self.hdlGen.wr_nl()
self.hdlGen.wr_nl()
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99b963c1043d0eb1fdaec12ddf6477d8aa78233b | Blebowski/Reg_Map_Gen | ip_xact/vhdl_reg_map_generator.py | [
"MIT"
] | Python | write_reg_map_pkg | null | def write_reg_map_pkg(self):
"""
Create package with declarations of register map input / output
records.
"""
self.hdlGen.wr_nl()
self.hdlGen.write_comment("Register map package for: " +
self.memMap.name, gap = 0)
self.hdlGen.write_gen_note()
self.hdlGen.wr_nl()
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Create package with declarations of register map input / output
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self.hdlGen.wr_nl()
self.hdlGen.write_comment("Register map package for: " +
self.memMap.name, gap = 0)
self.hdlGen.write_gen_note()
self.hdlGen.wr_nl()
if (type(self.hdlGen) == VhdlGenerator):
self.hdlGen.create_includes("ieee", ["std_logic_1164.all"])
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e0fb5cab25f1409645052b24ff78664e54349c65 | LUMC/fastq-filter | src/fastq_filter/__init__.py | [
"MIT"
] | Python | file_to_fastq_records | Generator[dnaio.Sequence,
None, None] | def file_to_fastq_records(filepath: str) -> Generator[dnaio.Sequence,
None, None]:
"""Parse a FASTQ file into a generator of Sequence objects"""
opener = functools.partial(xopen.xopen, threads=0)
with dnaio.open(filepath, opener=opener) as record_h: # t... | Parse a FASTQ file into a generator of Sequence objects | Parse a FASTQ file into a generator of Sequence objects | [
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opener = functools.partial(xopen.xopen, threads=0)
with dnaio.open(filepath, opener=opener) as record_h:
yield from record_h | [
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e0fb5cab25f1409645052b24ff78664e54349c65 | LUMC/fastq-filter | src/fastq_filter/__init__.py | [
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] | Python | filter_string_to_filters | List[Callable[[dnaio.Sequence], bool]] | def filter_string_to_filters(filter_string: str
) -> List[Callable[[dnaio.Sequence], bool]]:
"""Convert a filter string such as 'min_length:50|mean_quality:20 into
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] | def filter_string_to_filters(filter_string: str
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filters: List[Callable[[dnaio.Sequence], bool]] = []
for single_filter_string in filter_string.split('|'):
filter_name, filter_argstring = single_filter_string.split(':')
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e0fb5cab25f1409645052b24ff78664e54349c65 | LUMC/fastq-filter | src/fastq_filter/__init__.py | [
"MIT"
] | Python | filter_fastq | null | def filter_fastq(filter_string: str,
input_file: str,
output_file: str,
compression_level: int = DEFAULT_COMPRESSION_LEVEL):
"""
Filter a FASTQ input file with the filters in filter_string and write
the results to the output file.
:param filter_string:... |
Filter a FASTQ input file with the filters in filter_string and write
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a7b14669424c8786864aad05590228f45fb793c7 | csmoore/solutions-geoprocessing-toolbox | operational_graphics/toolboxes/scripts/CanvasAreaGRG.py | [
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] | Python | RotateXY | <not_specific> | def RotateXY(x, y, xc=0, yc=0, angle=0, units="DEGREES"):
"""Rotate an xy cooordinate about a specified origin
x,y xy coordinates
xc,yc center of rotation
angle angle
units "DEGREES" (default) or "RADIANS"
"""
import math
x = x - xc
y ... | Rotate an xy cooordinate about a specified origin
x,y xy coordinates
xc,yc center of rotation
angle angle
units "DEGREES" (default) or "RADIANS"
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x = x - xc
y = y - yc
angle = angle * -1
if units == "DEGREES":
angle = math.radians(angle)
xr = (x * math.cos(angle)) - (y * math.sin(angle)) + xc
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... |
735ae7be40ab0ec8b6c7c697322a935bb9c315af | RMeli/gninascripts | show_xyz_arrows.py | [
"BSD-3-Clause"
] | Python | draw_arrow | null | def draw_arrow(xyz1,xyz2, radius=0.5, gap=0.0, hlength=-1, hradius=-1,
color='blue red', name=''):
'''
Draw an arrow; borrows heavily from cgi arrows.
'''
radius, gap = float(radius), float(gap)
hlength, hradius = float(hlength), float(hradius)
xyz1 = list(xyz1)
xyz2 = list(xyz2)
... |
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radius, gap = float(radius), float(gap)
hlength, hradius = float(hlength), float(hradius)
xyz1 = list(xyz1)
xyz2 = list(xyz2)
try:
color1, color2 = color.split()
except:
... | [
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e317b24329436de9132aaca92776980a4560caf1 | RMeli/gninascripts | affinity_search/outputjson.py | [
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] | Python | makejson | <not_specific> | def makejson():
'''return dictionary of config options from makemodel'''
opts = makemodel.getoptions()
d=OrderedDict()
for (name,vals) in sorted(opts.items()):
paramsize=1
if type(vals) == tuple:
options=list(map(str,vals))
paramtype="enum"
data=OrderedDict([("name",name), ("type", paramtype), ("size"... | return dictionary of config options from makemodel | return dictionary of config options from makemodel | [
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opts = makemodel.getoptions()
d=OrderedDict()
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paramsize=1
if type(vals) == tuple:
options=list(map(str,vals))
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5abe899c45da243e05c4cd40b01eeef70ec5d66c | RMeli/gninascripts | simple_grid_visualization.py | [
"BSD-3-Clause"
] | Python | make_points | null | def make_points(atom,val_range,root,mapping):#TODO -- make sure this works
'''
Function that makes the points needed for the types file.
'''
if not os.path.isdir(root+atom):
os.mkdir(root+atom)
counter=0
for x in val_range:
pos=[x,0.0,0.0]
pos=struct.pack('f'*len(pos),*pos)
identity=[mapping]
identity... |
Function that makes the points needed for the types file.
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if not os.path.isdir(root+atom):
os.mkdir(root+atom)
counter=0
for x in val_range:
pos=[x,0.0,0.0]
pos=struct.pack('f'*len(pos),*pos)
identity=[mapping]
identity=struct.pack('i'*len(identity),*identity)
with open(root+atom+'/'+atom+'_'+str(counter)+'.gninatyp... | [
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5abe899c45da243e05c4cd40b01eeef70ec5d66c | RMeli/gninascripts | simple_grid_visualization.py | [
"BSD-3-Clause"
] | Python | make_types | <not_specific> | def make_types(atom, root, receptor):
'''
Function that writes a types file for all the points created from make_points in root
Returns the name of the file
'''
def atoi(text):
return int(text) if text.isdigit() else text
def natural_keys(text):
return [ atoi(c) for c in re.split(r'(\d+)', text) ]
gninat... |
Function that writes a types file for all the points created from make_points in root
Returns the name of the file
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def atoi(text):
return int(text) if text.isdigit() else text
def natural_keys(text):
return [ atoi(c) for c in re.split(r'(\d+)', text) ]
gninatypes=glob.glob(root+atom+'/'+atom+'*.gninatypes')
gninatypes.sort(key=natural_keys)
filename=root+receptor.split('/')[-1].split('... | [
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f3b814a3c4213df11522a987d48af8c2302c64f9 | RMeli/gninascripts | generate_counterexample_typeslines.py | [
"BSD-3-Clause"
] | Python | calc_ligand_dic | <not_specific> | def calc_ligand_dic(lines,ligand_suffix):
'''
This function will parse the input list of lines and construct 2 dictionaries
1) ligand name -> [docked files with that ligand]
2) docked_filename -> crystal_file for that pose
'''
data={}
docked_lookup={}
for line in lines:
#1) Getting the crystal ligand file... |
This function will parse the input list of lines and construct 2 dictionaries
1) ligand name -> [docked files with that ligand]
2) docked_filename -> crystal_file for that pose
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1) ligand name -> [docked files with that ligand]
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data={}
docked_lookup={}
for line in lines:
ligfile=re.split('--autobox_ligand ',line)[1].split()[0]
ligname=ligfile.split('/')[-1].split(ligand_suffix)[0].split('_')[1]
if ligname not in data:
data[ligname]=[]
outfile=re.split('-o ',line)[1].split()[0]
data[lig... | [
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f3b814a3c4213df11522a987d48af8c2302c64f9 | RMeli/gninascripts | generate_counterexample_typeslines.py | [
"BSD-3-Clause"
] | Python | run_obrms | <not_specific> | def run_obrms(ligand_file,crystal_file):
'''
This function returns a list of rmsds of the docked ligand file to the crystal file. The list is in the order of the poses.
'''
rmsds=subprocess.check_output(f'obrms {ligand_file} {crystal_file}',shell=True)
rmsds=str(rmsds,'utf-8').rstrip().split('\n')
rmsds=[float(x... |
This function returns a list of rmsds of the docked ligand file to the crystal file. The list is in the order of the poses.
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rmsds=subprocess.check_output(f'obrms {ligand_file} {crystal_file}',shell=True)
rmsds=str(rmsds,'utf-8').rstrip().split('\n')
rmsds=[float(x.split()[-1]) for x in rmsds]
return rmsds | [
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f3b814a3c4213df11522a987d48af8c2302c64f9 | RMeli/gninascripts | generate_counterexample_typeslines.py | [
"BSD-3-Clause"
] | Python | run_obrms_cross | <not_specific> | def run_obrms_cross(filename):
'''
This function returns a pandas dataframe of the RMSD between every pose and every other pose, which is generated using obrms -x
'''
csv=subprocess.check_output('obrms -x '+filename,shell=True)
csv=str(csv,'utf-8').rstrip().split('\n')
data=pd.DataFrame([x.split(',')[1:] for x i... |
This function returns a pandas dataframe of the RMSD between every pose and every other pose, which is generated using obrms -x
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csv=str(csv,'utf-8').rstrip().split('\n')
data=pd.DataFrame([x.split(',')[1:] for x in csv],dtype=float)
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e7859b5a2fcb7417309d15662e9b2b9d5669e42e | RMeli/gninascripts | compute_row.py | [
"BSD-3-Clause"
] | Python | compute_ligand_similarity | <not_specific> | def compute_ligand_similarity(smiles, pair):
'''
Input a list of smiles, and a pair to compute the similarity.
Returns the indices of the pair and the similarity
'''
(a,b) = pair
smi_a = smiles[a]
mol_a = AllChem.MolFromSmiles(smi_a)
if mol_a == None:
mol_a = AllChem.MolFromSmil... |
Input a list of smiles, and a pair to compute the similarity.
Returns the indices of the pair and the similarity
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Returns the indices of the pair and the similarity | [
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(a,b) = pair
smi_a = smiles[a]
mol_a = AllChem.MolFromSmiles(smi_a)
if mol_a == None:
mol_a = AllChem.MolFromSmiles(smi_a, sanitize=False)
fp_a = FingerprintMols.FingerprintMol(mol_a)
smi_b = smiles[b]
mol_b = AllChem.MolFromSmiles(smi_b)
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2a19339a2c728b71605ae82767f3e6f75c337ba9 | RMeli/gninascripts | train.py | [
"BSD-3-Clause"
] | Python | write_model_file | null | def write_model_file(model_file, template_file, train_file, test_file, root_folder, avg_rotations=False,
percent_reduc=False,train_file2=None, ratio=None, root_folder2=None, test_root_folder=None):
'''Writes a model prototxt file based on a provided template file
with certain placeholders r... | Writes a model prototxt file based on a provided template file
with certain placeholders replaced in each MolGridDataLayer.
For the source parameter, "TRAINFILE" is replaced with train_file
and "TESTFILE" is replaced with test_file.
For the root_folder parameter, "DATA_ROOT" is replaced with root_folder... | Writes a model prototxt file based on a provided template file
with certain placeholders replaced in each MolGridDataLayer.
For the source parameter, "TRAINFILE" is replaced with train_file
and "TESTFILE" is replaced with test_file.
For the root_folder parameter, "DATA_ROOT" is replaced with root_folder,
unless the lay... | [
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percent_reduc=False,train_file2=None, ratio=None, root_folder2=None, test_root_folder=None):
netparam = NetParameter()
with open(template_file, 'r') as f:
prototxt.Merge(f.read()... | [
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2a19339a2c728b71605ae82767f3e6f75c337ba9 | RMeli/gninascripts | train.py | [
"BSD-3-Clause"
] | Python | write_solver_file | null | def write_solver_file(solver_file, train_model, test_models, type, base_lr, momentum, weight_decay,
lr_policy, gamma, power, random_seed, max_iter, clip_gradients, snapshot_prefix,display=0):
'''Writes a solver prototxt file with parameters set to the
corresponding argument values. In part... | Writes a solver prototxt file with parameters set to the
corresponding argument values. In particular, the train_net
parameter is set to train_model, and a test_net parameter is
added for each of test_models, which should be a list. | Writes a solver prototxt file with parameters set to the
corresponding argument values. In particular, the train_net
parameter is set to train_model, and a test_net parameter is
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param = SolverParameter()
param.train_net = train_model
for test_model in test_models:
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2a19339a2c728b71605ae82767f3e6f75c337ba9 | RMeli/gninascripts | train.py | [
"BSD-3-Clause"
] | Python | check_improvement | <not_specific> | def check_improvement(testval, ratio, gold, gold_i, current_i, want_bigger):
'''Function that computes if training has improved.
Returns a tuple: (best_val, i, to_snap)'''
#indicators that we are at the first testing iteration and just need to return.
if gold==np.inf or gold==0:
return (testva... | Function that computes if training has improved.
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if gold==np.inf or gold==0:
return (testval, current_i, True)
best_val=gold
i=gold_i
to_snap=False
if want_bigger:
if (testval-gold) / gold > ratio:
best_val=testval
i=current_i
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2a19339a2c728b71605ae82767f3e6f75c337ba9 | RMeli/gninascripts | train.py | [
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] | Python | freemem | null | def freemem():
'''Free intermediate blobs from all networks. These will be reallocated as needed.'''
net = solver.net
if net.clearblobs:
#solver will need values in output blobs
for (bname, blob) in net.blobs.items():
if bname not in net.outputs:
... | Free intermediate blobs from all networks. These will be reallocated as needed. | Free intermediate blobs from all networks. These will be reallocated as needed. | [
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net = solver.net
if net.clearblobs:
for (bname, blob) in net.blobs.items():
if bname not in net.outputs:
blob.clear()
for k in test_nets.keys():
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2a19339a2c728b71605ae82767f3e6f75c337ba9 | RMeli/gninascripts | train.py | [
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'''Put results into test/train structure'''
test.y_true = result.y_true
test.y_score = result.y_score
test.y_aff = result.y_aff
test.y_predaff = result.y_predaff
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test.y_true = result.y_true
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test.y_aff = result.y_aff
test.y_predaff = result.y_predaff
test.rmsd_true = result.rmsd_true
test.rmsd_pred = result.rmsd_pred
if result.auc is not None:
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a50abf1ed0d8ebda7a3cb3363ddbd93e89be7ecb | RMeli/gninascripts | affinity_search/ga_addrequests.py | [
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] | Python | cleanparams | <not_specific> | def cleanparams(p):
'''standardize params that do not matter'''
modeldefaults = makemodel.getdefaults()
for i in range(1,6):
if p['conv%d_width'%i] == 0:
for suffix in ['func', 'init', 'norm', 'size', 'stride', 'width']:
name = 'conv%d_%s'%(i,suffix)
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modeldefaults = makemodel.getdefaults()
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for suffix in ['func', 'init', 'norm', 'size', 'stride', 'width']:
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a50abf1ed0d8ebda7a3cb3363ddbd93e89be7ecb | RMeli/gninascripts | affinity_search/ga_addrequests.py | [
"BSD-3-Clause"
] | Python | randParam | <not_specific> | def randParam(param, choices):
'''randomly select a choice for param'''
if isinstance(choices, makemodel.Range): #discretize
choices = np.linspace(choices.min,choices.max, 9)
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if isinstance(choices, makemodel.Range):
choices = np.linspace(choices.min,choices.max, 9)
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a50abf1ed0d8ebda7a3cb3363ddbd93e89be7ecb | RMeli/gninascripts | affinity_search/ga_addrequests.py | [
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] | Python | mutateIndividual | <not_specific> | def mutateIndividual(ind, indpb=0.05):
'''for each param, with prob indpb randomly sample another choice'''
options = makemodel.getoptions()
for (param,choices) in options.items():
if np.random.rand() < indpb:
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ind[param] = randParam(param, choices)
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a50abf1ed0d8ebda7a3cb3363ddbd93e89be7ecb | RMeli/gninascripts | affinity_search/ga_addrequests.py | [
"BSD-3-Clause"
] | Python | runGA | <not_specific> | def runGA(pop):
'''run GA with early stopping if not improving'''
hof = tools.HallOfFame(10)
stats = tools.Statistics(lambda ind: ind.fitness.values)
stats.register("avg", np.mean)
stats.register("std", np.std)
stats.register("min", np.min)
stats.register("max", np.max)
best = 0
... | run GA with early stopping if not improving | run GA with early stopping if not improving | [
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] | def runGA(pop):
hof = tools.HallOfFame(10)
stats = tools.Statistics(lambda ind: ind.fitness.values)
stats.register("avg", np.mean)
stats.register("std", np.std)
stats.register("min", np.min)
stats.register("max", np.max)
best = 0
pop = toolbox.clone(pop)
for i in range(40):
p... | [
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a50abf1ed0d8ebda7a3cb3363ddbd93e89be7ecb | RMeli/gninascripts | affinity_search/ga_addrequests.py | [
"BSD-3-Clause"
] | Python | addrows | null | def addrows(config,host,db,password):
'''add rows from fname into database, starting at row start'''
conn = MySQLdb.connect (host = host,user = "opter",passwd=password,db=db)
cursor = conn.cursor()
items = list(config.items())
names = ','.join([str(n) for (n,v) in items])
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conn = MySQLdb.connect (host = host,user = "opter",passwd=password,db=db)
cursor = conn.cursor()
items = list(config.items())
names = ','.join([str(n) for (n,v) in items])
values = ','.join(['%s' for (n,v) in items])
names += ',id'
values += ',"REQUESTED... | [
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b9bccff5ac8d1e7947db64b57d5b562c061fb325 | RMeli/gninascripts | create_caches.py | [
"BSD-3-Clause"
] | Python | writemol | <not_specific> | def writemol(root, mol, out):
'''mol is gninatypes file, write it in the appropriate binary format to out'''
fname = root+'/'+mol
try:
with open(fname,'rb') as gninatype:
if len(fname) > 255:
print("Skipping",mol,"since filename is too long")
return
... | mol is gninatypes file, write it in the appropriate binary format to out | mol is gninatypes file, write it in the appropriate binary format to out | [
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fname = root+'/'+mol
try:
with open(fname,'rb') as gninatype:
if len(fname) > 255:
print("Skipping",mol,"since filename is too long")
return
s = bytes(mol)
out.write(struct.pack('b',len(s)))
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18fea99a1349e09cd4ede82e4bdb889ff11565f0 | RMeli/gninascripts | affinity_search/cleanparams.py | [
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] | Python | cleanparams | <not_specific> | def cleanparams(p):
'''standardize params that do not matter'''
for i in range(1,6):
if p['conv%d_width'%i] == 0:
for suffix in ['func', 'init', 'norm', 'size', 'stride', 'width']:
name = 'conv%d_%s'%(i,suffix)
p[name] = modeldefaults[name]
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for i in range(1,6):
if p['conv%d_width'%i] == 0:
for suffix in ['func', 'init', 'norm', 'size', 'stride', 'width']:
name = 'conv%d_%s'%(i,suffix)
p[name] = modeldefaults[name]
if p['pool%d_size'%i] == 0:
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3cfa26ec8644609c845746a68d8a6cc9c1268e7b | RMeli/gninascripts | affinity_search/populaterequests.py | [
"BSD-3-Clause"
] | Python | addrows | null | def addrows(fname,host,db,password,start=0):
'''add rows from fname into database, starting at row start'''
data = pd.read_csv(fname,delim_whitespace=True,header=None)
colnames = ['P1','P2']
for (name,val) in sorted(opts.items()):
colnames.append(name)
data.columns = colnames
da... | add rows from fname into database, starting at row start | add rows from fname into database, starting at row start | [
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data = pd.read_csv(fname,delim_whitespace=True,header=None)
colnames = ['P1','P2']
for (name,val) in sorted(opts.items()):
colnames.append(name)
data.columns = colnames
data = data.drop(['P1','P2'],axis=1)
conn = MySQLdb.connect (host = host,u... | [
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"docstring_tokens": ... |
592babced10618460d376fed85830dcc304c7a62 | RMeli/gninascripts | affinity_search/makemodel.py | [
"BSD-3-Clause"
] | Python | add_conv_args | null | def add_conv_args(n,defaultwidth):
'''add arguments for layer n, in the form conv<n>_<arg>
A conv unit consists of a pool layer, a convolutional layer,
a normalization layer, and a non-linear layer
The pool layer is defined by kernel size
The conv layer is defined by kernel size, stride, initializa... | add arguments for layer n, in the form conv<n>_<arg>
A conv unit consists of a pool layer, a convolutional layer,
a normalization layer, and a non-linear layer
The pool layer is defined by kernel size
The conv layer is defined by kernel size, stride, initialization, and output width
Note that a wid... | add arguments for layer n, in the form conv_
A conv unit consists of a pool layer, a convolutional layer,
a normalization layer, and a non-linear layer
The pool layer is defined by kernel size
The conv layer is defined by kernel size, stride, initialization, and output width
Note that a width of zero indicates the lack... | [
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parser.add_argument('--pool%d_size'%n,type=int,help="Pooling size for layer %d"%n,default=2 if defaultwidth > 0 else 0,choices=(0,2,4,8))
parser.add_argument('--pool%d_type'%n,type=str,help="Pooling type for layer %d"%n,default='MAX',choices=('MAX','AVE'))
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The conv layer is defined by kernel size, stride, initialization, and output width
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592babced10618460d376fed85830dcc304c7a62 | RMeli/gninascripts | affinity_search/makemodel.py | [
"BSD-3-Clause"
] | Python | create_model | <not_specific> | def create_model(args):
'''Generate the model defined by args; first line (comment) contains solver/train.py arguments'''
m = '# --base_lr %f --momentum %f --weight_decay %f -- solver %s\n' % (10**args.base_lr_exp,args.momentum,10**args.weight_decay_exp,args.solver)
#test input
m += '''
layer {
name: ... | Generate the model defined by args; first line (comment) contains solver/train.py arguments | Generate the model defined by args; first line (comment) contains solver/train.py arguments | [
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] | def create_model(args):
m = '# --base_lr %f --momentum %f --weight_decay %f -- solver %s\n' % (10**args.base_lr_exp,args.momentum,10**args.weight_decay_exp,args.solver)
m += '''
layer {
name: "data"
type: "MolGridData"
top: "data"
top: "label"
top: "affinity"
include {
phase: TEST
}
molgrid_... | [
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"#loss",
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"type": null,
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"docstring_tokens": [],
"default": null,
"is_optional": null
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],
"outlier_params": [],
"others": []
} |
cfd23fb632d49990e523d69c81900e687c7c431a | RMeli/gninascripts | affinity_search/evaluate_cross.py | [
"BSD-3-Clause"
] | Python | reduce_results | <not_specific> | def reduce_results(results, index, which):
'''Return results with only one tuple for every pocket-ligand value,
taking the one with the max value at index in the tuple (predicted affinity or pose score)
'''
res = dict() #indexed by pocketligand
for r in results:
lname = r[3]
m = re.s... | Return results with only one tuple for every pocket-ligand value,
taking the one with the max value at index in the tuple (predicted affinity or pose score)
| Return results with only one tuple for every pocket-ligand value,
taking the one with the max value at index in the tuple (predicted affinity or pose score) | [
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] | def reduce_results(results, index, which):
res = dict()
for r in results:
lname = r[3]
m = re.search(r'(\S+)/...._._rec_...._(\S+)_(lig|uff_min)',lname)
pocket = m.group(1)
lig = m.group(2)
key = pocket+':'+lig
if key not in res:
res[key] = r
... | [
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] | {
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"docstring_tokens... |
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