hexsha stringlengths 40 40 | repo stringlengths 7 114 | path stringlengths 4 124 | license listlengths 1 9 | language stringclasses 1
value | identifier stringlengths 1 71 | return_type stringlengths 1 749 ⌀ | original_string stringlengths 76 22.7k | original_docstring stringlengths 16 7.61k | docstring stringlengths 16 2.47k | docstring_tokens listlengths 6 477 | code stringlengths 14 10.2k | code_tokens listlengths 6 996 | short_docstring stringlengths 2 644 | short_docstring_tokens listlengths 1 116 | comment listlengths 1 89 | parameters listlengths 0 64 | docstring_params dict |
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
"CC0-1.0",
"BSD-3-Clause"
] | Python | LF_CG_DISTANCE_LONG | <not_specific> | def LF_CG_DISTANCE_LONG(c):
"""
This LF is designed to make sure that the compound mention
and the gene mention aren't too far from each other.
"""
return -1 if len(list(get_between_tokens(c))) > 25 else 0 |
This LF is designed to make sure that the compound mention
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
"CC0-1.0",
"BSD-3-Clause"
] | Python | LF_CG_ALLOWED_DISTANCE | <not_specific> | def LF_CG_ALLOWED_DISTANCE(c):
"""
This LF is designed to make sure that the compound mention
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each other
"""
return 0 if any([
LF_CG_DISTANCE_LONG(c),
LF_CG_DISTANCE_SHORT(c)
]) else 1 if random.random() < 0.65 e... |
This LF is designed to make sure that the compound mention
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| This LF is designed to make sure that the compound mention
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
"CC0-1.0",
"BSD-3-Clause"
] | Python | LF_CG_NO_VERB | <not_specific> | def LF_CG_NO_VERB(c):
"""
This label function is designed to fire if a given
sentence doesn't contain a verb. Helps cut out some of the titles
hidden in Pubtator abstracts
"""
if len([x for x in nltk.pos_tag(word_tokenize(c.get_parent().text)) if "VB" in x[1]]) == 0:
if "correlates with... |
This label function is designed to fire if a given
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if len([x for x in nltk.pos_tag(word_tokenize(c.get_parent().text)) if "VB" in x[1]]) == 0:
if "correlates with" in c.get_parent().text:
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
"CC0-1.0",
"BSD-3-Clause"
] | Python | LF_CG_PARENTHETICAL_DESC | <not_specific> | def LF_CG_PARENTHETICAL_DESC(c):
"""
This label function looks for mentions that are in paranthesis.
Some of the gene mentions are abbreviations rather than names of a gene.
"""
if ")" in c[1].get_span() and "(" in list(get_left_tokens(c[1], window=1)):
if LF_CG_DISTANCE_SHORT(c):
... |
This label function looks for mentions that are in paranthesis.
Some of the gene mentions are abbreviations rather than names of a gene.
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] | def LF_CG_PARENTHETICAL_DESC(c):
if ")" in c[1].get_span() and "(" in list(get_left_tokens(c[1], window=1)):
if LF_CG_DISTANCE_SHORT(c):
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
"CC0-1.0",
"BSD-3-Clause"
] | Python | LF_CG_BICLUSTER_BINDS | <not_specific> | def LF_CG_BICLUSTER_BINDS(c):
"""
This label function uses the bicluster data located in the
A global network of biomedical relationships
"""
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@sen_p... |
This label function uses the bicluster data located in the
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] | def LF_CG_BICLUSTER_BINDS(c):
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@sen_pos")
if not(query.empty):
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return 1
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
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] | Python | LF_CG_BICLUSTER_AGONISM | <not_specific> | def LF_CG_BICLUSTER_AGONISM(c):
"""
This label function uses the bicluster data located in the
A global network of biomedical relationships
"""
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@sen... |
This label function uses the bicluster data located in the
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] | def LF_CG_BICLUSTER_AGONISM(c):
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@sen_pos")
if not(query.empty):
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
"CC0-1.0",
"BSD-3-Clause"
] | Python | LF_CG_BICLUSTER_ANTAGONISM | <not_specific> | def LF_CG_BICLUSTER_ANTAGONISM(c):
"""
This label function uses the bicluster data located in the
A global network of biomedical relationships
"""
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@... |
This label function uses the bicluster data located in the
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] | def LF_CG_BICLUSTER_ANTAGONISM(c):
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@sen_pos")
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
"CC0-1.0",
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] | Python | LF_CG_BICLUSTER_INC_EXPRESSION | <not_specific> | def LF_CG_BICLUSTER_INC_EXPRESSION(c):
"""
This label function uses the bicluster data located in the
A global network of biomedical relationships
"""
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_nu... |
This label function uses the bicluster data located in the
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] | def LF_CG_BICLUSTER_INC_EXPRESSION(c):
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@sen_pos")
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
"CC0-1.0",
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] | Python | LF_CG_BICLUSTER_DEC_EXPRESSION | <not_specific> | def LF_CG_BICLUSTER_DEC_EXPRESSION(c):
"""
This label function uses the bicluster data located in the
A global network of biomedical relationships
"""
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_nu... |
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] | def LF_CG_BICLUSTER_DEC_EXPRESSION(c):
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@sen_pos")
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
"CC0-1.0",
"BSD-3-Clause"
] | Python | LF_CG_BICLUSTER_AFF_EXPRESSION | <not_specific> | def LF_CG_BICLUSTER_AFF_EXPRESSION(c):
"""
This label function uses the bicluster data located in the
A global network of biomedical relationships
"""
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_nu... |
This label function uses the bicluster data located in the
A global network of biomedical relationships
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] | def LF_CG_BICLUSTER_AFF_EXPRESSION(c):
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@sen_pos")
if not(query.empty):
if query["E"].sum() > 0.0:
return 1
return 0 | [
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ae2086908c37946bf640a0565011053391bf202e | ajlee21/snorkeling | playground/compound_disease/transfer_learning_experiment/data/label_functions/compound_gene_lf.py | [
"CC0-1.0",
"BSD-3-Clause"
] | Python | LF_CG_BICLUSTER_INHIBITS | <not_specific> | def LF_CG_BICLUSTER_INHIBITS(c):
"""
This label function uses the bicluster data located in the
A global network of biomedical relationships
"""
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@se... |
This label function uses the bicluster data located in the
A global network of biomedical relationships
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] | def LF_CG_BICLUSTER_INHIBITS(c):
sen_pos = c.get_parent().position
pubmed_id = c.get_parent().document.name
query = bicluster_dep_df.query("pubmed_id==@pubmed_id&sentence_num==@sen_pos")
if not(query.empty):
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26033c58609251606b428b6e0ecb4103795e8d18 | charlestacc/mecatronique | model.py | [
"MIT"
] | Python | update | null | def update(self, dt):
"""Given the current state of the robot (speeds of the wheels) and a time step (dt),
calculates the new position of the robot.
The speed of the wheels are assumed constant during dt.
Arguments:
dt {float} -- Travel time in seconds
"""
... | Given the current state of the robot (speeds of the wheels) and a time step (dt),
calculates the new position of the robot.
The speed of the wheels are assumed constant during dt.
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dt {float} -- Travel time in seconds
| Given the current state of the robot (speeds of the wheels) and a time step (dt),
calculates the new position of the robot.
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dt {float} -- Travel time in seconds | [
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dtheta= rotation_speed*dt
if rotation_speed !=0 :
dx= (linear_speed/rotation_speed) * math.sin(dtheta)
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0da01d90bca294e47d17910780c91c1c96d3fcba | charlestacc/mecatronique | main.py | [
"MIT"
] | Python | play | <not_specific> | def play(self):
""" An inifinite loop that manages the display and the robot interactions
"""
print("Current mode is '{}'".format(self.get_mode()))
speed_multiplier = 1
while True:
mode = self.get_mode()
# 'e' for 'event'
for e in pygame.event.... | An inifinite loop that manages the display and the robot interactions
| An inifinite loop that manages the display and the robot interactions | [
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] | def play(self):
print("Current mode is '{}'".format(self.get_mode()))
speed_multiplier = 1
while True:
mode = self.get_mode()
for e in pygame.event.get():
if e.type == QUIT:
sys.exit()
elif e.type == KEYUP:
... | [
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] | [
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} |
0da01d90bca294e47d17910780c91c1c96d3fcba | charlestacc/mecatronique | main.py | [
"MIT"
] | Python | asserv | null | def asserv(self, m=None):
"""Sets the speeds of the 2 motors to get the robot to its destination point
"""
if m == None:
m = self.m
distance = math.sqrt(
(m.x_goal - m.x) * (m.x_goal - m.x) + (m.y_goal - m.y) * (m.y_goal - m.y)
) #calcul la distance entre ... | Sets the speeds of the 2 motors to get the robot to its destination point
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] | def asserv(self, m=None):
if m == None:
m = self.m
distance = math.sqrt(
(m.x_goal - m.x) * (m.x_goal - m.x) + (m.y_goal - m.y) * (m.y_goal - m.y)
)
dx=m.x_goal-m.x
dy=m.y_goal-m.y
if dy==0 and dx==0:
angle_diff=0
else :
... | [
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... |
0da01d90bca294e47d17910780c91c1c96d3fcba | charlestacc/mecatronique | main.py | [
"MIT"
] | Python | angle_diff | <not_specific> | def angle_diff(self, a, b):
"""Returns the smallest distance between 2 angles
"""
# TODO #modulo 2pi et recuperer l'angle le plus petit !
d = a - b
d = ((d + math.pi) % (2 * math.pi)) - math.pi
return d | Returns the smallest distance between 2 angles
| Returns the smallest distance between 2 angles | [
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] | def angle_diff(self, a, b):
d = a - b
d = ((d + math.pi) % (2 * math.pi)) - math.pi
return d | [
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... |
1a8cb9157c1769da759fe1aaae6a4dc2d9750bd7 | SergeyKanzhelev/anthos-appconfig | tests/artifacts/drivers/simple_hello/hello_app_drv_py.py | [
"Apache-2.0"
] | Python | hello | <not_specific> | def hello():
"""Return a friendly HTTP greeting."""
collection = [
{'call': 'http://httpbin.org/get'},
]
next_call = collection.pop()['call']
print('next_call-[{}]-[{}]'.format(next_call, collection))
text = RestHelper.call_with_sequence(next_call, collection)
print(APP_LOG_PREFIX_SUCCESS + ':Call:Re... | Return a friendly HTTP greeting. | Return a friendly HTTP greeting. | [
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"friendly",
"HTTP",
"greeting",
"."
] | def hello():
collection = [
{'call': 'http://httpbin.org/get'},
]
next_call = collection.pop()['call']
print('next_call-[{}]-[{}]'.format(next_call, collection))
text = RestHelper.call_with_sequence(next_call, collection)
print(APP_LOG_PREFIX_SUCCESS + ':Call:Result[{}]'.format(text))
return text | [
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} |
1b205d8a82cc286eb7f63a10d2d6785bf9f25154 | oarepo/flask-taxonomies | flask_taxonomies/views/taxonomy.py | [
"MIT"
] | Python | delete_taxonomy | <not_specific> | def delete_taxonomy(code=None):
"""
Deletes a taxonomy.
Note: this call is destructive in a sense that all its terms, regardless if used or not,
are deleted as well. A tight user permissions should be employed.
"""
try:
tax = current_flask_taxonomies.get_taxonomy(code=code)
except N... |
Deletes a taxonomy.
Note: this call is destructive in a sense that all its terms, regardless if used or not,
are deleted as well. A tight user permissions should be employed.
| Deletes a taxonomy.
Note: this call is destructive in a sense that all its terms, regardless if used or not,
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try:
tax = current_flask_taxonomies.get_taxonomy(code=code)
except NoResultFound:
json_abort(404, {})
return
current_flask_taxonomies.permissions.taxonomy_delete.enforce(request=request, code=code)
current_flask_taxonomies.delete_taxonomy(tax)
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] | [
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],
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} |
19c9a85ec4aedc05a7d952d6a1e67b74baa97870 | oarepo/flask-taxonomies | flask_taxonomies/views/taxonomy_term.py | [
"MIT"
] | Python | taxonomy_move_term | <not_specific> | def taxonomy_move_term(code=None, slug=None, prefer=None, page=None, size=None, destination='',
rename='', q=None):
"""Move term into a new parent or rename it."""
if q:
json_abort(422, {
'message': 'Query not appropriate when moving term',
'reason': 'searc... | Move term into a new parent or rename it. | Move term into a new parent or rename it. | [
"Move",
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"a",
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] | def taxonomy_move_term(code=None, slug=None, prefer=None, page=None, size=None, destination='',
rename='', q=None):
if q:
json_abort(422, {
'message': 'Query not appropriate when moving term',
'reason': 'search-query-not-allowed'
})
try:
tax... | [
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645d9d007ccb4c1a6707a2e291b318849269a5f0 | oarepo/flask-taxonomies | flask_taxonomies/bulk.py | [
"MIT"
] | Python | bulk_taxonomy_query | List[SingleQueryResult] | def bulk_taxonomy_query(
db,
taxonomy_code,
query_data,
query_function,
query_combining_function,
result_preprocess_function,
result_match_function
) -> List[SingleQueryResult]:
"""
Selects taxonomy terms by multiple search criteria.
It works the foll... |
Selects taxonomy terms by multiple search criteria.
It works the following way:
1. query_data is an array of query data (for example, oai-pmh records). Items in this array are
called 'd'
Each 'd' is converted to an array of query criteria via the query_function function.
2. An a... | Selects taxonomy terms by multiple search criteria.
It works the following way.
1. query_data is an array of query data (for example, oai-pmh records). Items in this array are
called 'd'
Each 'd' is converted to an array of query criteria via the query_function function.
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d7edffc71ecc1ddf804c91c5f95a9a14b577979a | oarepo/flask-taxonomies | flask_taxonomies/routing.py | [
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"""Register an additional mediatype handler on an existing HeaderRouter."""
def decorator(func):
for value in values:
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d7edffc71ecc1ddf804c91c5f95a9a14b577979a | oarepo/flask-taxonomies | flask_taxonomies/routing.py | [
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:param args: the accepted mediatypes, as strings
:returns: an HeaderRouter class to be initialized
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d7edffc71ecc1ddf804c91c5f95a9a14b577979a | oarepo/flask-taxonomies | flask_taxonomies/routing.py | [
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:returns: an HeaderRouter class to be initialized
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2f92970110f4cbc7e9fab19a9fb534012c6150f1 | oarepo/flask-taxonomies | flask_taxonomies/api.py | [
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return_descendants_busy_count=False):
"""Return a list of all available taxonomies."""
session = session or self.session
query_parts = [Taxonomy]
if return_descendants_count:
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2f92970110f4cbc7e9fab19a9fb534012c6150f1 | oarepo/flask-taxonomies | flask_taxonomies/api.py | [
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ti = _coerce_ti(ti)
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920596803da39552a6db722b9ade103e5a2de9bd | MHC-CycleGAN-Research/Our-UNet-Code | data.py | [
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use the same seed for image_datagen and mask_datagen to ensure the transformation for image and mask is the same
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306b75bd082c83be66995ba296c654055923b294 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_tb_addr_generator.py | [
"MIT"
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"""
Commit the generator output into the output file.
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306b75bd082c83be66995ba296c654055923b294 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_tb_addr_generator.py | [
"MIT"
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# Write register type enum
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reg_type_enum.append(LanDeclaration("reg_none", ""))
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306b75bd082c83be66995ba296c654055923b294 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_tb_addr_generator.py | [
"MIT"
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306b75bd082c83be66995ba296c654055923b294 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_tb_addr_generator.py | [
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| Write addresses and address block head for IP-XACT memory map to
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] | def write_mem_map_addr(self):
for block in self.memMap.addressBlock:
self.write_addrbl_reg_list(block)
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} |
306b75bd082c83be66995ba296c654055923b294 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_tb_addr_generator.py | [
"MIT"
] | Python | create_addrMap_package | null | def create_addrMap_package(self, name):
"""
Create a VHDL package to the address generator output. Insert basic
IEEE include: std_logic_1164.all. Add list of registers.
Arguments:
name VHDL pacakge name
"""
self.vhdlGen.wr_nl()
self.vhdlGen.write_comm_line(gap=0)
if (self.memMap != None):
print (... |
Create a VHDL package to the address generator output. Insert basic
IEEE include: std_logic_1164.all. Add list of registers.
Arguments:
name VHDL pacakge name
| Create a VHDL package to the address generator output. Insert basic
IEEE include: std_logic_1164.all. Add list of registers.
Arguments:
name VHDL pacakge name | [
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] | def create_addrMap_package(self, name):
self.vhdlGen.wr_nl()
self.vhdlGen.write_comm_line(gap=0)
if (self.memMap != None):
print ("Writing testbench addresses of '%s' register map" % self.memMap.name)
self.vhdlGen.write_comment("Memory map for: {}".format(
self.memMap.name), 0, small=True)
self... | [
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e098b11d62e6660020b3a662389d296480a0c573 | Blebowski/Reg_Map_Gen | languages/gen_base.py | [
"MIT"
] | Python | wr_line | null | def wr_line(self, line):
"""
Write single line to the generator output.
Arguments:
line Line to write into the output source code
"""
self.out.append(line) |
Write single line to the generator output.
Arguments:
line Line to write into the output source code
| Write single line to the generator output.
Arguments:
line Line to write into the output source code | [
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] | def wr_line(self, line):
self.out.append(line) | [
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e098b11d62e6660020b3a662389d296480a0c573 | Blebowski/Reg_Map_Gen | languages/gen_base.py | [
"MIT"
] | Python | append_line | null | def append_line(self, line):
"""
Push the line to the generator stack.
Arguments:
line Line to write into the output source code
"""
self.appendText.insert(0, line) |
Push the line to the generator stack.
Arguments:
line Line to write into the output source code
| Push the line to the generator stack.
Arguments:
line Line to write into the output source code | [
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"docstring_tokens": [... |
e098b11d62e6660020b3a662389d296480a0c573 | Blebowski/Reg_Map_Gen | languages/gen_base.py | [
"MIT"
] | Python | wr_nl | null | def wr_nl(self):
"""
Write new line into the generator output.
"""
self.wr_line("\n") |
Write new line into the generator output.
| Write new line into the generator output. | [
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] | def wr_nl(self):
self.wr_line("\n") | [
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] | [
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}
],
"outlier_params": [],
"others": []
} |
e098b11d62e6660020b3a662389d296480a0c573 | Blebowski/Reg_Map_Gen | languages/gen_base.py | [
"MIT"
] | Python | commit_append_line | null | def commit_append_line(self, count):
"""
Pop number of elements from the generator stack and write it to the
generator output.
Arguments:
count Number of items to pop
"""
for i in range(0, min(count, len(self.appendText))):
self.wr_line(self.appendText[0])
self.appendText.pop(0) |
Pop number of elements from the generator stack and write it to the
generator output.
Arguments:
count Number of items to pop
| Pop number of elements from the generator stack and write it to the
generator output.
Arguments:
count Number of items to pop | [
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] | def commit_append_line(self, count):
for i in range(0, min(count, len(self.appendText))):
self.wr_line(self.appendText[0])
self.appendText.pop(0) | [
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e098b11d62e6660020b3a662389d296480a0c573 | Blebowski/Reg_Map_Gen | languages/gen_base.py | [
"MIT"
] | Python | write_comm_line | null | def write_comm_line(self, gap=2):
"""
Write full comment line to the generator output.
Arguments:
gap Number of tabs before the comment line
"""
pass |
Write full comment line to the generator output.
Arguments:
gap Number of tabs before the comment line
| Write full comment line to the generator output.
Arguments:
gap Number of tabs before the comment line | [
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] | def write_comm_line(self, gap=2):
pass | [
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"docstring_tokens": []... |
e098b11d62e6660020b3a662389d296480a0c573 | Blebowski/Reg_Map_Gen | languages/gen_base.py | [
"MIT"
] | Python | write_comment | null | def write_comment(self, input, gap, caption=None, small=False):
"""
Write comment in the language specific format into the generator
output.
Arguments:
input Text of the comment to write
gap Number of tabs before the comment
caption Caption of the comment
small Small comment is as compact as po... |
Write comment in the language specific format into the generator
output.
Arguments:
input Text of the comment to write
gap Number of tabs before the comment
caption Caption of the comment
small Small comment is as compact as possible, Big comment
takes more lines. Depends on particular lan... | Write comment in the language specific format into the generator
output.
Arguments:
input Text of the comment to write
gap Number of tabs before the comment
caption Caption of the comment
small Small comment is as compact as possible, Big comment
takes more lines. Depends... | [
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | commit_to_file | null | def commit_to_file(self, of, text):
"""
Write a text into the output file
Arguments:
of Open output file
text List of strings to write
"""
for line in text :
of.write(line) |
Write a text into the output file
Arguments:
of Open output file
text List of strings to write
| Write a text into the output file
Arguments:
of Open output file
text List of strings to write | [
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for line in text :
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | move_till_text | null | def move_till_text(self, of, text):
"""
Move till text in a file. The file must be opened for reading.
Arguments:
of Output file
text Text until which to move in a file
"""
line = "BEGIN"
while (line != None):
line = of.read()
if (line == text):
break |
Move till text in a file. The file must be opened for reading.
Arguments:
of Output file
text Text until which to move in a file
| Move till text in a file. The file must be opened for reading.
Arguments:
of Output file
text Text until which to move in a file | [
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line = "BEGIN"
while (line != None):
line = of.read()
if (line == text):
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | addr_reg_lookup | <not_specific> | def addr_reg_lookup(self, fieldReg):
"""
Search the "memMap" for register with the same address offset aligned
to memory word and return it.
Arguments:
fieldReg Register from the field map to search for in the address
map.
"""
for block in self.memMap.addressBlock:
for reg in block.register:
... |
Search the "memMap" for register with the same address offset aligned
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Arguments:
fieldReg Register from the field map to search for in the address
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| Search the "memMap" for register with the same address offset aligned
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Arguments:
fieldReg Register from the field map to search for in the address
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | align_addr_to_wrd | <not_specific> | def align_addr_to_wrd(self, addr):
"""
Align address of a register to word address.
"""
return math.floor(addr - (addr % self.wrdWidthByte)) |
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | reg_is_access_type | <not_specific> | def reg_is_access_type(self, reg, accesses):
"""
Check if register is explicitly of given access type. If input
access type is sub-set of register access type, False is returned.
E.g.:
register access type: read-writeOnce
searched access type: write-Once
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"""
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | reg_has_access_type | <not_specific> | def reg_has_access_type(self, reg, accesses):
"""
Check if register contains given access type. If input access type
is sub-set of register acces type, True is returned.
E.g.:
register access type: read-writeOnce
searched access type: write-Once
True is returned
"""
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | is_reg_write_indicate | <not_specific> | def is_reg_write_indicate(self, reg):
"""
Check if register contains at least one field which has write
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"""
for field in sorted(reg.field, key=lambda a: a.bitOffset):
if (field.modifiedWriteValue == "modify"):
return True
return False |
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | is_reg_read_indicate | <not_specific> | def is_reg_read_indicate(self, reg):
"""
Check if any field of a register has readAction set to "modify"
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"""
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Check if any field of a register has readAction set to "modify"
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | calc_blk_wrd_span | <not_specific> | def calc_blk_wrd_span(self, block, accesses=[""]):
"""
Calculate minimal address span for address block with registers of
given access types.
Returns:
[low_addr, high_addr] - Lowest higher addresses within a block
with registers of given access types.
"""
low_addr = block.range
high_addr = 0
for... |
Calculate minimal address span for address block with registers of
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | calc_blk_wrd_count | <not_specific> | def calc_blk_wrd_count(self, block, accesses=[""]):
"""
Calculate number of memory words in a block occupied by a registers
of this block.
Arguments:
block Block object
accesses List of register access types that should be considered.
If not specified, every register is considered.
"""
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Calculate number of memory words in a block occupied by a registers
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | parameter_lookup | <not_specific> | def parameter_lookup(self, uid):
"""
Search for paramater in loaded IP-XACT component. Returns name of
the parameter if found, false otherwise.
"""
for parameter in self.pyXactComp.parameters.parameter:
if (parameter.parameterId == uid):
return parameter.name
return None |
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for parameter in self.pyXactComp.parameters.parameter:
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | calc_wrd_address_width | <not_specific> | def calc_wrd_address_width(self, block):
"""
Calculate number of bits from address, necessary to address a word
within an address block.
"""
addr_width = self.calc_addr_width_from_size(block.range * 8) - \
self.calc_addr_width_from_size(self.wrdWidthBit)
return addr_width |
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addr_width = self.calc_addr_width_from_size(block.range * 8) - \
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return addr_width | [
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1af489f8bd506bd1de34e90f3966005db704c1c9 | Blebowski/Reg_Map_Gen | ip_xact/addr_generator.py | [
"MIT"
] | Python | calc_reg_rstval_mask | <not_specific> | def calc_reg_rstval_mask(self, reg):
"""
Calculate mask or reset values for given register. Reset mask contains
value of reset after "res_n" input is released.
"""
# Suppose all registers are reset to zero
rst_mask = ["0" for x in range(reg.size)]
# Go through fields and replace each bit index by a reset... |
Calculate mask or reset values for given register. Reset mask contains
value of reset after "res_n" input is released.
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] | def calc_reg_rstval_mask(self, reg):
rst_mask = ["0" for x in range(reg.size)]
for field in sorted(reg.field, key=lambda a: a.bitOffset):
if (field.resets == None):
continue;
remainder = field.resets.reset.value
for j in range(field.bitWidth):
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2ed722c312a6286129709a411614f13deadb85b7 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_addr_generator.py | [
"MIT"
] | Python | write_reg_enums | <not_specific> | def write_reg_enums(self, field):
"""
Write IP-XACT register object enums as VHDL constants (std_logic) to the
generator output.
Arguments:
field Register field object (parsed from pyXact) whose
enums to write.
"""
if (field.enumeratedValues == []):
return False
self.vhdlGen.wr_nl()
se... |
Write IP-XACT register object enums as VHDL constants (std_logic) to the
generator output.
Arguments:
field Register field object (parsed from pyXact) whose
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| Write IP-XACT register object enums as VHDL constants (std_logic) to the
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Arguments:
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if (field.enumeratedValues == []):
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self.vhdlGen.write_comment('"{}" field enumerated values'.format(
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for es in field.enumeratedValues:
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2ed722c312a6286129709a411614f13deadb85b7 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_addr_generator.py | [
"MIT"
] | Python | write_res_vals | <not_specific> | def write_res_vals(self, field):
"""
Write restart values of IP-XACT register field as VHDL constants
(std_logic) to the generator output.
Arguments:
field Register field object (parsed from pyXact) whose
restart values to write.
"""
if (field.resets == None):
return False
if (fie... |
Write restart values of IP-XACT register field as VHDL constants
(std_logic) to the generator output.
Arguments:
field Register field object (parsed from pyXact) whose
restart values to write.
| Write restart values of IP-XACT register field as VHDL constants
(std_logic) to the generator output.
Arguments:
field Register field object (parsed from pyXact) whose
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if (field.resets == None):
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if (field.resets.reset == None):
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2ed722c312a6286129709a411614f13deadb85b7 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_addr_generator.py | [
"MIT"
] | Python | write_reg_field | null | def write_reg_field(self, field, reg):
"""
Write IP-XACT register field indices as VHDL constants. Use "wrdWidthBit"
property to concatenate register indices into word aligned sizes.
E.g. register with 0x1 offset will start at index 8, 0x2 at index 16 etc...
Write to the generator output.
Arguments:
fie... |
Write IP-XACT register field indices as VHDL constants. Use "wrdWidthBit"
property to concatenate register indices into word aligned sizes.
E.g. register with 0x1 offset will start at index 8, 0x2 at index 16 etc...
Write to the generator output.
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field Register field object (parsed from pyXac... | Write IP-XACT register field indices as VHDL constants. Use "wrdWidthBit"
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bitIndexL = field.bitOffset
bitIndexH = field.bitOffset + field.bitWidth-1
bitIndexL = bitIndexL + ((reg.addressOffset*8) % self.wrdWidthBit)
bitIndexH = bitIndexH + ((reg.addressOffset*8) % self.wrdWidthBit)
if (bitIndexH == bitIndexL):
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2ed722c312a6286129709a411614f13deadb85b7 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_addr_generator.py | [
"MIT"
] | Python | write_reg | null | def write_reg(self, reg, writeFields, writeEnums, writeReset):
"""
Write IP-XACT register as set of VHDL constants to the generator output.
Following constants are written:
- Register field indices
- Enums for each field of a register
- Reset values for each field of a r... |
Write IP-XACT register as set of VHDL constants to the generator output.
Following constants are written:
- Register field indices
- Enums for each field of a register
- Reset values for each field of a register
Arguments:
reg Register field object (parsed from pyX... | Write IP-XACT register as set of VHDL constants to the generator output.
Following constants are written:
Register field indices
Enums for each field of a register
Reset values for each field of a register
Arguments:
reg Register field object (parsed from pyXact) to write
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capt = '{} register'.format(reg.name.upper())
self.vhdlGen.write_comment(reg.description, 2, caption=capt)
if (writeFields == True):
for field in sorted(reg.field, key=lambda a: a.bitOffset):
self.write_reg_field(field, reg)
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2ed722c312a6286129709a411614f13deadb85b7 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_addr_generator.py | [
"MIT"
] | Python | write_regs | null | def write_regs(self, regs):
"""
Write multiple registers as sets of VHDL constants.
Arguments:
regs List of register objects as parsed by pyxact framework.
"""
for reg in sorted(regs, key=lambda a: a.addressOffset):
self.write_reg(reg, True, True, True) |
Write multiple registers as sets of VHDL constants.
Arguments:
regs List of register objects as parsed by pyxact framework.
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Arguments:
regs List of register objects as parsed by pyxact framework. | [
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2ed722c312a6286129709a411614f13deadb85b7 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_addr_generator.py | [
"MIT"
] | Python | write_addrbl_head | null | def write_addrbl_head(self, addressBlock):
"""
Write IP-XACT address block as VHDL constant to generator output.
Arguments:
addressBlock Address block to write (parsed from pyXact framework)
"""
# Write capital comment with name of the address Block
self.vhdlGen.write_comm_line()
self.vhdlGen.write_co... |
Write IP-XACT address block as VHDL constant to generator output.
Arguments:
addressBlock Address block to write (parsed from pyXact framework)
| Write IP-XACT address block as VHDL constant to generator output.
Arguments:
addressBlock Address block to write (parsed from pyXact framework) | [
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self.vhdlGen.write_comm_line()
self.vhdlGen.write_comment("Address block: {}".format(addressBlock.name), 2)
self.vhdlGen.write_comm_line()
bitWidth = 4
decl = LanDeclaration(addressBlock.name+"_BLOCK",
addressBlock.baseAddress/addressBlock.range,
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2ed722c312a6286129709a411614f13deadb85b7 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_addr_generator.py | [
"MIT"
] | Python | write_addrbl_regs | null | def write_addrbl_regs(self, addressBlock):
"""
Write IP-XACT Address block register addresses as VHDL constants to
generator output.
Arguments:
addressBlock Address block to write as parsed by pyXact.
"""
for reg in sorted(addressBlock.register, key=lambda a: a.addressOffset):
decl = LanDeclara... |
Write IP-XACT Address block register addresses as VHDL constants to
generator output.
Arguments:
addressBlock Address block to write as parsed by pyXact.
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addressBlock Address block to write as parsed by pyXact. | [
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for reg in sorted(addressBlock.register, key=lambda a: a.addressOffset):
decl = LanDeclaration(reg.name+"_ADR",
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generator output. | [
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] | [
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"docstring_to... |
2ed722c312a6286129709a411614f13deadb85b7 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_addr_generator.py | [
"MIT"
] | Python | write_mem_map_addr | null | def write_mem_map_addr(self):
"""
Write addresses and address block head for IP-XACT memory map to
generator output.
"""
for block in self.memMap.addressBlock:
self.write_addrbl_head(block)
self.write_addrbl_regs(block)
self.vhdlGen.wr_nl() |
Write addresses and address block head for IP-XACT memory map to
generator output.
| Write addresses and address block head for IP-XACT memory map to
generator output. | [
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] | def write_mem_map_addr(self):
for block in self.memMap.addressBlock:
self.write_addrbl_head(block)
self.write_addrbl_regs(block)
self.vhdlGen.wr_nl() | [
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} |
2ed722c312a6286129709a411614f13deadb85b7 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_addr_generator.py | [
"MIT"
] | Python | write_mem_map_fields | null | def write_mem_map_fields(self):
"""
Write fields, enums and reset values of IP-XACT memory map to generator
output.
"""
for block in self.memMap.addressBlock:
self.write_regs(block.register) |
Write fields, enums and reset values of IP-XACT memory map to generator
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] | def write_mem_map_fields(self):
for block in self.memMap.addressBlock:
self.write_regs(block.register) | [
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2ed722c312a6286129709a411614f13deadb85b7 | Blebowski/Reg_Map_Gen | ip_xact/vhdl_addr_generator.py | [
"MIT"
] | Python | create_addrMap_package | null | def create_addrMap_package(self, name):
"""
Create a VHDL package to the address generator output. Insert basic
IEEE include: std_logic_1164.all. Add address definitions, create
constants for enums and reset values.
Arguments:
name VHDL pacakge name
"""
self.vhdlGen.wr_nl()
self.vhdlGen.write_comm_l... |
Create a VHDL package to the address generator output. Insert basic
IEEE include: std_logic_1164.all. Add address definitions, create
constants for enums and reset values.
Arguments:
name VHDL pacakge name
| Create a VHDL package to the address generator output. Insert basic
IEEE include: std_logic_1164.all. Add address definitions, create
constants for enums and reset values.
Arguments:
name VHDL pacakge name | [
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self.vhdlGen.wr_nl()
self.vhdlGen.write_comm_line(gap=0)
if (self.memMap != None):
print ("Writing addresses of '%s' register map" % self.memMap.name)
self.vhdlGen.write_comment("Memory map for: {}".format(
self.memMap.name), 0, small=True)
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69c3fbef593faf65176cf1bea85b627a2f16f3b7 | Blebowski/Reg_Map_Gen | VhdlRegMapGeneratorWrapper.py | [
"MIT"
] | Python | write_reg_map_package | null | def write_reg_map_package(self, vhdlGen, dir_path):
"""
Create package with records for register blocks within an address block.
"""
reg_map_pkg_name = os.path.join(dir_path, vhdlGen.memMap.name.lower() + "_pkg.vhd")
of = open(reg_map_pkg_name, 'w')
vhdlGen.set_of(of)
write_license(self.lic_text, '-',... |
Create package with records for register blocks within an address block.
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] | def write_reg_map_package(self, vhdlGen, dir_path):
reg_map_pkg_name = os.path.join(dir_path, vhdlGen.memMap.name.lower() + "_pkg.vhd")
of = open(reg_map_pkg_name, 'w')
vhdlGen.set_of(of)
write_license(self.lic_text, '-', of)
vhdlGen.write_reg_map_pkg()
vhdlGen.commit_to_file()
of.close() | [
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69c3fbef593faf65176cf1bea85b627a2f16f3b7 | Blebowski/Reg_Map_Gen | VhdlRegMapGeneratorWrapper.py | [
"MIT"
] | Python | write_reg_map_implementation | null | def write_reg_map_implementation(self, vhdlGen, dir_path):
"""
Write register map implementation. Create separate entity file for
each register memory block.
"""
for block in vhdlGen.memMap.addressBlock:
print("Processing memory block: " + block.name)
if (block.usage == "register"):
file_path = ... |
Write register map implementation. Create separate entity file for
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] | def write_reg_map_implementation(self, vhdlGen, dir_path):
for block in vhdlGen.memMap.addressBlock:
print("Processing memory block: " + block.name)
if (block.usage == "register"):
file_path = os.path.join(dir_path, block.name.lower() + "_reg_map.vhd")
of = open(file_path, 'w')
vhdlGen.set_of(of)
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69c3fbef593faf65176cf1bea85b627a2f16f3b7 | Blebowski/Reg_Map_Gen | VhdlRegMapGeneratorWrapper.py | [
"MIT"
] | Python | copy_reg_map_sources | null | def copy_reg_map_sources(self, vhdlGen, dir_path, destDir):
"""
Copy VHDL templates to destination directory!
"""
for templ_name, templ_path in vhdlGen.template_sources.items():
src_path = os.path.join(ROOT_PATH, templ_path)
dest_path = os.path.join(ROOT_PATH, destDir)
dest_path = os.path.join(dest_pat... |
Copy VHDL templates to destination directory!
| Copy VHDL templates to destination directory! | [
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"VHDL",
"templates",
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"destination",
"directory!"
] | def copy_reg_map_sources(self, vhdlGen, dir_path, destDir):
for templ_name, templ_path in vhdlGen.template_sources.items():
src_path = os.path.join(ROOT_PATH, templ_path)
dest_path = os.path.join(ROOT_PATH, destDir)
dest_path = os.path.join(dest_path, os.path.basename(templ_path))
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af36aa6e86610020d1f8c6f79faf17bef3a17034 | Blebowski/Reg_Map_Gen | ip_xact/lyx_addr_generator.py | [
"MIT"
] | Python | is_reg_present | <not_specific> | def is_reg_present(self, reg):
"""
Check whether register should be written to documentation. Affected by:
1. Skip conditional attribute in document config.
2. isPresent IP-XACT parameter of register. Parameter value read
from config file!
"""
if (self.config["skip_c... |
Check whether register should be written to documentation. Affected by:
1. Skip conditional attribute in document config.
2. isPresent IP-XACT parameter of register. Parameter value read
from config file!
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1. Skip conditional attribute in document config.
2. isPresent IP-XACT parameter of register. Parameter value read
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if (self.config["skip_conditional"] == False):
return True
param_name = self.parameter_lookup(reg.isPresent)
if (param_name == None):
return True
if (self.config["parameters"][param_name] == True):
return True
return False | [
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af36aa6e86610020d1f8c6f79faf17bef3a17034 | Blebowski/Reg_Map_Gen | ip_xact/lyx_addr_generator.py | [
"MIT"
] | Python | reg_append_short_enums | <not_specific> | def reg_append_short_enums(self, field):
"""
Create line with enums for given register field. Enum name and description
are addedd to each line.
"""
appendText = ""
if (field.enumeratedValues == []):
return appendText
if (len(field.enumeratedValues[0].enumeratedValue) > 0):
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af36aa6e86610020d1f8c6f79faf17bef3a17034 | Blebowski/Reg_Map_Gen | ip_xact/lyx_addr_generator.py | [
"MIT"
] | Python | write_reg_field_desc | null | def write_reg_field_desc(self, reg):
"""
Write description of register fields. Each field will have enums listed
if enums are defined.
"""
for field in sorted(reg.field, key=lambda a: a.bitOffset):
self.lyxGen.insert_layout("Description")
descText = field.description
descText += self.reg_... |
Write description of register fields. Each field will have enums listed
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for field in sorted(reg.field, key=lambda a: a.bitOffset):
self.lyxGen.insert_layout("Description")
descText = field.description
descText += self.reg_append_short_enums(field)
self.lyxGen.wr_line("{} {}\n".format(field.name, descText))
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af36aa6e86610020d1f8c6f79faf17bef3a17034 | Blebowski/Reg_Map_Gen | ip_xact/lyx_addr_generator.py | [
"MIT"
] | Python | write_reg_header | null | def write_reg_header(self, block, reg):
"""
Write register header with:
- Register name (Subsection)
- Register type
- Register address
- Register size
- Conditional presence note (optional)
- Description
"""
# Add the Section title
self.lyxGen.write_layout_text("Subsection", "{}\n".format(r... |
Write register header with:
- Register name (Subsection)
- Register type
- Register address
- Register size
- Conditional presence note (optional)
- Description
| Write register header with:
Register name (Subsection)
Register type
Register address
Register size
Conditional presence note (optional)
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] | def write_reg_header(self, block, reg):
self.lyxGen.write_layout_text("Subsection", "{}\n".format(reg.name),
label="label")
self.lyxGen.write_layout_text("Description", "Type: {}\n".format(
reg.access))
self.lyxGen.write_layout_text("Description", "Offset: {}\n".format(
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Conditional presence note (optional)
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4477b58f187fe8ab560404da79b99b31dbdd2540 | Blebowski/Reg_Map_Gen | languages/gen_lan_base.py | [
"MIT"
] | Python | is_supported_type | <not_specific> | def is_supported_type(self, type):
"""
Check if declaration type is supported by this language generator
Arguments:
type Declaration type
"""
for i in self.supportedTypes:
if (type == i):
return True
print("{} is not supported type for {} class".format(
type, self.__class__.__name__))
ret... |
Check if declaration type is supported by this language generator
Arguments:
type Declaration type
| Check if declaration type is supported by this language generator
Arguments:
type Declaration type | [
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for i in self.supportedTypes:
if (type == i):
return True
print("{} is not supported type for {} class".format(
type, self.__class__.__name__))
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4477b58f187fe8ab560404da79b99b31dbdd2540 | Blebowski/Reg_Map_Gen | languages/gen_lan_base.py | [
"MIT"
] | Python | create_includes | null | def create_includes(self, includeList):
"""
Create includes in the language generator output
Arguments:
includeList List of includes to be written
"""
pass |
Create includes in the language generator output
Arguments:
includeList List of includes to be written
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includeList List of includes to be written | [
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4477b58f187fe8ab560404da79b99b31dbdd2540 | Blebowski/Reg_Map_Gen | languages/gen_lan_base.py | [
"MIT"
] | Python | write_decl | null | def write_decl(self, decl):
"""
Write declaration into the language generator output
Arguments:
decl Declaration to write (LanDeclaration)
"""
pass |
Write declaration into the language generator output
Arguments:
decl Declaration to write (LanDeclaration)
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4477b58f187fe8ab560404da79b99b31dbdd2540 | Blebowski/Reg_Map_Gen | languages/gen_lan_base.py | [
"MIT"
] | Python | create_package | null | def create_package(self, name):
"""
Create language specific package into the language generator output
Arguments:
name Package name
"""
pass |
Create language specific package into the language generator output
Arguments:
name Package name
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Arguments:
name Package name | [
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4477b58f187fe8ab560404da79b99b31dbdd2540 | Blebowski/Reg_Map_Gen | languages/gen_lan_base.py | [
"MIT"
] | Python | create_structure | null | def create_structure(self, name, decls):
"""
Create a structure into the language generator output.
Arguments:
name Structure name
decls List of structure declarations
"""
pass |
Create a structure into the language generator output.
Arguments:
name Structure name
decls List of structure declarations
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Arguments:
name Structure name
decls List of structure declarations | [
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4477b58f187fe8ab560404da79b99b31dbdd2540 | Blebowski/Reg_Map_Gen | languages/gen_lan_base.py | [
"MIT"
] | Python | create_enum | null | def create_enum(self, name, decls):
"""
Create an enum into the language generator output
Arguments:
name Enum name
decls List of enum declarations
"""
pass |
Create an enum into the language generator output
Arguments:
name Enum name
decls List of enum declarations
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Arguments:
name Enum name
decls List of enum declarations | [
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] | def create_enum(self, name, decls):
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | write_comm_line | null | def write_comm_line(self, gap=2):
"""
Write VHDL comment line in format: (gap)---- aligned to 80 characters
Arguments:
gap Number of tabs before the comment line
"""
self.__wr_line('{:{fill}<80}\n'.format(" " * gap, fill=self.commentSign)) |
Write VHDL comment line in format: (gap)---- aligned to 80 characters
Arguments:
gap Number of tabs before the comment line
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gap Number of tabs before the comment line | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | write_comment | null | def write_comment(self, input, gap=0, caption=None, small=False, wrapLine=True):
"""
Write VHDL comment in format:
--------------------------------------------------------------------
-- caption
--
-- Comment text
--------------------------------------------------------------------
Arguments:
i... |
Write VHDL comment in format:
--------------------------------------------------------------------
-- caption
--
-- Comment text
--------------------------------------------------------------------
Arguments:
input Text of the comment
gap Number of tabs before the comment line
caption ... | Write VHDL comment in format:
caption
Comment text
input Text of the comment
gap Number of tabs before the comment line
caption Text of the caption
small If set to True the first and last line of above described
format are ommitted | [
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if (small == False):
self.write_comm_line(gap)
if (caption != None):
self.__wr_line(" " * gap + self.commentSign + self.commentSign +
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if (wrapLine):
lines = split_string(in... | [
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"docstring_tokens": ... |
9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | create_includes | <not_specific> | def create_includes(self, library, includeList):
"""
Create VHDL include list from a library.
Arguments:
includeList List of includes from given library
"""
if (includeList == None):
return False
self.__wr_line("Library {};\n".format(library))
for include in includeList:
self.__wr_line("use {... |
Create VHDL include list from a library.
Arguments:
includeList List of includes from given library
| Create VHDL include list from a library.
Arguments:
includeList List of includes from given library | [
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if (includeList == None):
return False
self.__wr_line("Library {};\n".format(library))
for include in includeList:
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | format_int_std_log_decl_val | <not_specific> | def format_int_std_log_decl_val(self, decl):
"""
Format value of std_logic or std_logic_vector declaration given as
integer value.
"""
strVal = ""
# For single bit, this is written as '1', '0'
if (decl.bitWidth == 1):
strVal = "'{}'".format(decl.value)
return strVal
# If width is multiple of 4 -... |
Format value of std_logic or std_logic_vector declaration given as
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| Format value of std_logic or std_logic_vector declaration given as
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strVal = ""
if (decl.bitWidth == 1):
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return strVal
if (decl.bitWidth % 4 == 0):
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hPref = 'x'
else:
fmt = ':0{}b'.format(math.ceil(float(decl.bitWidth)))
hPref... | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | format_str_std_log_decl_val | <not_specific> | def format_str_std_log_decl_val(self, decl):
"""
Format value of std_logic or std_logic_vector declaration given as
string object.
"""
strVal = ""
if (decl.bitWidth == 1):
strVal = "'" + decl.value + "'"
else:
strVal = '"' + decl.value + '"'
return strVal |
Format value of std_logic or std_logic_vector declaration given as
string object.
| Format value of std_logic or std_logic_vector declaration given as
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] | def format_str_std_log_decl_val(self, decl):
strVal = ""
if (decl.bitWidth == 1):
strVal = "'" + decl.value + "'"
else:
strVal = '"' + decl.value + '"'
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | format_std_log_decl_val | <not_specific> | def format_std_log_decl_val(self, decl):
"""
Create VHDL declaration of std_logic or std_logic_vector!
CAN be used for declaration of signal, constant, generic, IO
port of entity or element of VHDL record.
decl Declaration object
"""
strVal = ""
# If value of declaration is a string try to parse it ... |
Create VHDL declaration of std_logic or std_logic_vector!
CAN be used for declaration of signal, constant, generic, IO
port of entity or element of VHDL record.
decl Declaration object
| Create VHDL declaration of std_logic or std_logic_vector.
CAN be used for declaration of signal, constant, generic, IO
port of entity or element of VHDL record.
decl Declaration object | [
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strVal = ""
if (type(decl.value) == str):
strVal = self.format_str_std_log_decl_val(decl)
else:
strVal = self.format_int_std_log_decl_val(decl)
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | format_std_log_decl_type | <not_specific> | def format_std_log_decl_type(self, decl):
"""
Formats "type" specifier for std_logic and std_logic_vector.
types. Supports Integer and String Bitwidths.
decl Declaration object
"""
strType = decl.type
# If Both bounds are given, use the bounds
if (decl.upBound != None and decl.lowBound != None):
... |
Formats "type" specifier for std_logic and std_logic_vector.
types. Supports Integer and String Bitwidths.
decl Declaration object
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decl Declaration object | [
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strType = decl.type
if (decl.upBound != None and decl.lowBound != None):
if (decl.type == "std_logic"):
strType += "_vector"
strType += "({} downto {})".format(decl.upBound, decl.lowBound)
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | format_decl_type_and_val | <not_specific> | def format_decl_type_and_val(self, decl):
"""
Format value of a declaration into string.
"""
strType = ""
strVal = ""
# For std_logic or std_logic_vector parse it separately
if (decl.type == "std_logic" or decl.type == "std_logic_vector"):
if (decl.value != "" and decl.value != None):
strVal = sel... |
Format value of a declaration into string.
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] | def format_decl_type_and_val(self, decl):
strType = ""
strVal = ""
if (decl.type == "std_logic" or decl.type == "std_logic_vector"):
if (decl.value != "" and decl.value != None):
strVal = self.format_std_log_decl_val(decl)
strType = self.format_std_log_decl_type(decl)
else:
strType = decl.type
s... | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | format_decl_dir | <not_specific> | def format_decl_dir(self, decl):
"""
Format declaration direction into a string. If no direction is
specified, empty string is chosen
"""
dirStr = ""
if (decl.direction != "" and decl.direction != None):
dirStr = decl.direction
return dirStr |
Format declaration direction into a string. If no direction is
specified, empty string is chosen
| Format declaration direction into a string. If no direction is
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dirStr = ""
if (decl.direction != "" and decl.direction != None):
dirStr = decl.direction
return dirStr | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | format_decl_name | <not_specific> | def format_decl_name(self, decl):
"""
Format name of a declaration into a string.
"""
if (decl.specifier == "constant"):
return decl.name.upper()
else:
return decl.name.lower() |
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return decl.name.upper()
else:
return decl.name.lower() | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | write_decl | <not_specific> | def write_decl(self, decl):
"""
Create VHDL declaration of simple type. CAN be used for either
component ports (with direction), generics or signal/constant
declaration without binding to entity/component.
Arguments:
decl Declaration object
"""
[strType, strVal] = self.format_decl_type... |
Create VHDL declaration of simple type. CAN be used for either
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | format_vector_range | <not_specific> | def format_vector_range(self, signalName, u_ind, l_ind, direction = "downto"):
"""
Format declaration of vector range.
"""
return "{}({} {} {})".format(signalName, u_ind, direction, l_ind); |
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | format_decls | null | def format_decls(self, decls, gap, alignLeft, alignRight, alignLen, wrap):
"""
Format list or dictionary of declarations to have common alignment
settings!
"""
lst = []
if (type(decls) == list):
lst = decls
elif (type(decls) == dict):
for key, value in decls.items():
lst.append(value)
for ... |
Format list or dictionary of declarations to have common alignment
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lst = []
if (type(decls) == list):
lst = decls
elif (type(decls) == dict):
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | write_connection | null | def write_connection(self, decl, specDir = False):
"""
Create component port or generic connection on VHDL entity.
Arguments:
decl Declaration object
specDir If Direction should be specified in the connection
in VHDL comment
"""
portDelim = ""
if (decl.addSemicoln):
portDelim = ","... |
Create component port or generic connection on VHDL entity.
Arguments:
decl Declaration object
specDir If Direction should be specified in the connection
in VHDL comment
| Create component port or generic connection on VHDL entity.
Arguments:
decl Declaration object
specDir If Direction should be specified in the connection
in VHDL comment | [
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] | def write_connection(self, decl, specDir = False):
portDelim = ""
if (decl.addSemicoln):
portDelim = ","
pref = " {} {} ".format(" " * decl.gap, decl.name)
pref = pref + " " * (40 - len(pref)) + "=>"
post = " {} {}".format(decl.value, portDelim)
if (specDir and (decl.direction != None and decl.direction ... | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | create_package | null | def create_package(self, name):
"""
Create VHDL package.
Arguments:
name name of the package
"""
self.__wr_line("package {} is\n".format(name))
self.append_line("end package;\n") |
Create VHDL package.
Arguments:
name name of the package
| Create VHDL package.
Arguments:
name name of the package | [
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] | def create_package(self, name):
self.__wr_line("package {} is\n".format(name))
self.append_line("end package;\n") | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | create_structure | <not_specific> | def create_structure(self, name, decls, gap=0):
"""
Create VHDL record.
Arguments:
decls Declaration structures
"""
if (not decls):
return False
self.__wr_line(" " * gap + "type {} is record\n".format(name))
for decl in decls:
self.write_decl(decl)
self.__wr_line(" " * gap + "end record;\n")
... |
Create VHDL record.
Arguments:
decls Declaration structures
| Create VHDL record.
Arguments:
decls Declaration structures | [
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if (not decls):
return False
self.__wr_line(" " * gap + "type {} is record\n".format(name))
for decl in decls:
self.write_decl(decl)
self.__wr_line(" " * gap + "end record;\n")
return True | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | create_enum | <not_specific> | def create_enum(self, name, decls, gap=0):
"""
Create VHDL enum.
Arguments:
decls Declaration structures
"""
if (not decls):
return False
self.__wr_line(" " * gap + "type {} is (\n".format(name))
for (i,item) in enumerate(decls):
self.__wr_line(" " * item.gap + item.name)
if (i == len(decls)... |
Create VHDL enum.
Arguments:
decls Declaration structures
| Create VHDL enum.
Arguments:
decls Declaration structures | [
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] | def create_enum(self, name, decls, gap=0):
if (not decls):
return False
self.__wr_line(" " * gap + "type {} is (\n".format(name))
for (i,item) in enumerate(decls):
self.__wr_line(" " * item.gap + item.name)
if (i == len(decls) - 1):
self.__wr_line('\n')
else:
self.__wr_line(',\n')
self.__wr_... | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | write_ports_or_declarations | null | def write_ports_or_declarations(self, decl, decls, isInstance):
"""
Writes Dictionary of ports or declarations.
Arguments:
decl Declaration object of entity for which
decls Declarations List (VhdlCompDeclaration)
isInstance "True" indicates ports should be written.... |
Writes Dictionary of ports or declarations.
Arguments:
decl Declaration object of entity for which
decls Declarations List (VhdlCompDeclaration)
isInstance "True" indicates ports should be written.
| Writes Dictionary of ports or declarations.
Arguments:
decl Declaration object of entity for which
decls Declarations List (VhdlCompDeclaration)
isInstance "True" indicates ports should be written. | [
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... | def write_ports_or_declarations(self, decl, decls, isInstance):
for (i, key) in enumerate(decls):
if (i == len(decls) - 1 and decl.intType != "architecture"):
decls[key].addSemicoln = False
else:
decls[key].addSemicoln = True
if (isInstance):
self.write_connection(decls[key], specDir = True)
e... | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | format_entity_decl | <not_specific> | def format_entity_decl(self, decl, base_indent=4, alignLen=30):
"""
Format declaration of entity or architecture with increasing indent for
"""
if (decl.intType != "entity" and decl.intType != "architecture"):
print("ERROR: Unsupported declaration type:" + decl.intType + \
" Should be entity or arc... |
Format declaration of entity or architecture with increasing indent for
| Format declaration of entity or architecture with increasing indent for | [
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] | def format_entity_decl(self, decl, base_indent=4, alignLen=30):
if (decl.intType != "entity" and decl.intType != "architecture"):
print("ERROR: Unsupported declaration type:" + decl.intType + \
" Should be entity or architecture!")
return
self.format_decls(decl.ports, gap=base_indent+2, alignLeft=Tru... | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | create_comp_instance | <not_specific> | def create_comp_instance(self, decl):
"""
Create component instance of VHDL entity, entity declaration, component
declaration or architecture declaration.
Arguments:
decl Declaration object (VhdlCompDeclaration)
specDir If Direction should be specified in the connection
in VHDL comment... |
Create component instance of VHDL entity, entity declaration, component
declaration or architecture declaration.
Arguments:
decl Declaration object (VhdlCompDeclaration)
specDir If Direction should be specified in the connection
in VHDL comment
| Create component instance of VHDL entity, entity declaration, component
declaration or architecture declaration.
Arguments:
decl Declaration object (VhdlCompDeclaration)
specDir If Direction should be specified in the connection
in VHDL comment | [
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titleStr = ["generic {}(\n", "port {}(\n"]
mapSuf = ""
semicoln = ""
gstr = " " * decl.gap
self.__wr_line("\n")
if (decl.intType == "entity"):
if (decl.isInstance):
title = decl.value + " : " + decl.name + "\n"
mapSuf = "map"
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | create_gate | null | def create_gate(self, result, signals, gate, gap=2):
"""
Create basic logic function two two signals.
Arguments:
result Name of resulting signal
signals List with original signal names
gate String with gate function
"""
gStr = " " * gap
line = gStr+result... |
Create basic logic function two two signals.
Arguments:
result Name of resulting signal
signals List with original signal names
gate String with gate function
| Create basic logic function two two signals.
Arguments:
result Name of resulting signal
signals List with original signal names
gate String with gate function | [
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] | def create_gate(self, result, signals, gate, gap=2):
gStr = " " * gap
line = gStr+result+" <= "+signals[0]+" "+ gate+" "+signals[1]+";\n"
self.__wr_line(line) | [
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9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | is_valid_dir | <not_specific> | def is_valid_dir(self, direction):
"""
Checks if specified direction is valid in VHDL.
Accepts: in, out, inout, buffer
"""
acceptDirs = ["in", "out", "buffer", "inout"]
for acceptDir in acceptDirs:
if (direction == acceptDir):
return True
return False |
Checks if specified direction is valid in VHDL.
Accepts: in, out, inout, buffer
| Checks if specified direction is valid in VHDL.
Accepts: in, out, inout, buffer | [
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] | def is_valid_dir(self, direction):
acceptDirs = ["in", "out", "buffer", "inout"]
for acceptDir in acceptDirs:
if (direction == acceptDir):
return True
return False | [
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] | {
"returns": [],
"raises": [],
"params": [
{
"identifier": "self",
"type": null,
"docstring": null,
"docstring_tokens": [],
"default": null,
"is_optional": null
},
{
"identifier": "direction",
"type": null,
"docstring": null,
"docstring_token... |
9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | strip_spaces | <not_specific> | def strip_spaces(self, string):
"""
Strips spaces from a string and returns string without spaces
"""
return "".join([x for x in string if x != " "]) |
Strips spaces from a string and returns string without spaces
| Strips spaces from a string and returns string without spaces | [
"Strips",
"spaces",
"from",
"a",
"string",
"and",
"returns",
"string",
"without",
"spaces"
] | def strip_spaces(self, string):
return "".join([x for x in string if x != " "]) | [
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] | [
{
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},
{
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}
] | {
"returns": [],
"raises": [],
"params": [
{
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"docstring_tokens": [],
"default": null,
"is_optional": null
},
{
"identifier": "string",
"type": null,
"docstring": null,
"docstring_tokens":... |
9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | parse_gen_or_port | <not_specific> | def parse_gen_or_port(self, line):
"""
Parses input line which is a port or generic declaration into a
declaration object.
On ports, direction must be specified. On generics, it must NOT be
speciffied.
If line could not be parsed, None is returned. Otherwise declaration
object is returned.
Each line mu... |
Parses input line which is a port or generic declaration into a
declaration object.
On ports, direction must be specified. On generics, it must NOT be
speciffied.
If line could not be parsed, None is returned. Otherwise declaration
object is returned.
Each line must start with 'signal' for port declarat... | Parses input line which is a port or generic declaration into a
declaration object.
On ports, direction must be specified. On generics, it must NOT be
speciffied.
If line could not be parsed, None is returned. Otherwise declaration
object is returned.
Each line must start with 'signal' for port declarations, or 'consta... | [
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"be",
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"I... | def parse_gen_or_port(self, line):
decl = LanDeclaration("new", value="")
cmn_re = re.compile("[\w]+")
wrds = cmn_re.findall(line)
if (len(wrds) > 2 and
(wrds[0] == "signal" or wrds[0] == "constant")):
decl.specifier = wrds[0]
else:
return None
if (wrds[0] == "signal" and (not self.is_valid_dir(wr... | [
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{
"param": "self",
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},
{
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}
] | {
"returns": [],
"raises": [],
"params": [
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"default": null,
"is_optional": null
},
{
"identifier": "line",
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"docstring": null,
"docstring_tokens": [... |
9f7eafa33f712a4d8b0f0494e7c64bdc44b95501 | Blebowski/Reg_Map_Gen | languages/gen_vhdl.py | [
"MIT"
] | Python | load_entity_template | <not_specific> | def load_entity_template(self, path):
"""
Load entity template from VHDL file. Recognizes: entity name,
Entity ports, generics. Note that on each generic "constant"
must be explicitly specified. On each port "signal" must be
explicitly specified. Direction must be specified on each signal!
Parsing sto... |
Load entity template from VHDL file. Recognizes: entity name,
Entity ports, generics. Note that on each generic "constant"
must be explicitly specified. On each port "signal" must be
explicitly specified. Direction must be specified on each signal!
Parsing stops upon "architecture" definition start.
... | Load entity template from VHDL file. Recognizes: entity name,
Entity ports, generics. Note that on each generic "constant"
must be explicitly specified. On each port "signal" must be
explicitly specified. Direction must be specified on each signal.
Parsing stops upon "architecture" definition start.
Return declaration ... | [
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... | def load_entity_template(self, path):
if (not(path.endswith(".vhd"))):
print("Only VHDL files are supported for parsing!")
return
fd = open(path)
ent_re = re.compile("^[ ]*entity[ ]*[\w]+[ ]*is$")
architecture_re = re.compile("^[ ]*architecture[ ]+[\w]+[ ]+of[ ]+[\w]+[ ]+is[ ]*$")
entity = LanDeclaratio... | [
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"... | Load entity template from VHDL file. | [
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{
"param": "self",
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},
{
"param": "path",
"type": null
}
] | {
"returns": [],
"raises": [],
"params": [
{
"identifier": "self",
"type": null,
"docstring": null,
"docstring_tokens": [],
"default": null,
"is_optional": null
},
{
"identifier": "path",
"type": null,
"docstring": null,
"docstring_tokens": [... |
a80ea0e7fffd9d28a84425769522d9a2dccb48f5 | Blebowski/Reg_Map_Gen | ip_xact/h_addr_generator.py | [
"MIT"
] | Python | create_reg_field_decl | <not_specific> | def create_reg_field_decl(self, reg, field):
"""
Create declaration object from IP-XACT register and field object.
"""
fieldDecl = LanDeclaration(name=field.name.lower(), value=0)
fieldDecl.type = "uint{}_t".format(self.wrdWidthBit)
fieldDecl.bitWidth = field.bitWidth
fieldDecl.gap = 2
fieldDecl.alignLe... |
Create declaration object from IP-XACT register and field object.
| Create declaration object from IP-XACT register and field object. | [
"Create",
"declaration",
"object",
"from",
"IP",
"-",
"XACT",
"register",
"and",
"field",
"object",
"."
] | def create_reg_field_decl(self, reg, field):
fieldDecl = LanDeclaration(name=field.name.lower(), value=0)
fieldDecl.type = "uint{}_t".format(self.wrdWidthBit)
fieldDecl.bitWidth = field.bitWidth
fieldDecl.gap = 2
fieldDecl.alignLen = 40
fieldDecl.bitIndex = field.bitOffset + \
((int(reg.addressOffset)*8)... | [
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] | [
"\"\"\"\n\t\tCreate declaration object from IP-XACT register and field object.\n\t\t\"\"\""
] | [
{
"param": "self",
"type": null
},
{
"param": "reg",
"type": null
},
{
"param": "field",
"type": null
}
] | {
"returns": [],
"raises": [],
"params": [
{
"identifier": "self",
"type": null,
"docstring": null,
"docstring_tokens": [],
"default": null,
"is_optional": null
},
{
"identifier": "reg",
"type": null,
"docstring": null,
"docstring_tokens": []... |
a80ea0e7fffd9d28a84425769522d9a2dccb48f5 | Blebowski/Reg_Map_Gen | ip_xact/h_addr_generator.py | [
"MIT"
] | Python | write_reg_group_union | null | def write_reg_group_union(self, regGroup):
"""
Write group of IP-XACT register objects as a single union to generator
output. Group of registers should reside within the same memory word.
Example of union with 32 bit wrdWidth:
union <joined_name> {
uint32 u32;
struct <joined_name>_s {
uint32 b... |
Write group of IP-XACT register objects as a single union to generator
output. Group of registers should reside within the same memory word.
Example of union with 32 bit wrdWidth:
union <joined_name> {
uint32 u32;
struct <joined_name>_s {
uint32 bitfield_first : <width_of_bitfield>)
...
... | Write group of IP-XACT register objects as a single union to generator
output. Group of registers should reside within the same memory word.
Example of union with 32 bit wrdWidth:
union {
uint32 u32;
struct _s {
uint32 bitfield_first : )
uint32 bitfield_last :
}
Name of union is concatenated from all register ... | [
"Write",
"group",
"of",
"IP",
"-",
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"register",
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"as",
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"should",
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"word",
".",
"Example",
"of",
"union",
"wit... | def write_reg_group_union(self, regGroup):
fielDecls = []
enumDecl = []
unName = self.prefix + "_"
for (j,reg) in enumerate(regGroup):
for (i,field) in enumerate(sorted(reg.field, key=lambda a: a.bitOffset)):
fieldDecl = self.create_reg_field_decl(reg, field)
fieldDecl.comment = None
if (i == 0):... | [
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"\"\"\"\n\t\tWrite group of IP-XACT register objects as a single union to generator\n\t\toutput. Group of registers should reside within the same memory word.\n\n\t\tExample of union with 32 bit wrdWidth:\n\t\t\tunion <joined_name> {\n\t\t\t\tuint32 u32;\n\t\t\t\tstruct <joined_name>_s {\n\t\t\t\t\tuint32 bitfield... | [
{
"param": "self",
"type": null
},
{
"param": "regGroup",
"type": null
}
] | {
"returns": [],
"raises": [],
"params": [
{
"identifier": "self",
"type": null,
"docstring": null,
"docstring_tokens": [],
"default": null,
"is_optional": null
},
{
"identifier": "regGroup",
"type": null,
"docstring": null,
"docstring_tokens... |
a80ea0e7fffd9d28a84425769522d9a2dccb48f5 | Blebowski/Reg_Map_Gen | ip_xact/h_addr_generator.py | [
"MIT"
] | Python | create_field_enum_decls | <not_specific> | def create_field_enum_decls(self, field):
"""
Create declaration objects for enumerated values of IP-XACT field object.
"""
enum_decls = []
if (len(field.enumeratedValues[0].enumeratedValue) > 0):
for es in field.enumeratedValues:
for (i,e) in enumerate(sorted(es.enumeratedValue, key=lambda x: x.val... |
Create declaration objects for enumerated values of IP-XACT field object.
| Create declaration objects for enumerated values of IP-XACT field object. | [
"Create",
"declaration",
"objects",
"for",
"enumerated",
"values",
"of",
"IP",
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"XACT",
"field",
"object",
"."
] | def create_field_enum_decls(self, field):
enum_decls = []
if (len(field.enumeratedValues[0].enumeratedValue) > 0):
for es in field.enumeratedValues:
for (i,e) in enumerate(sorted(es.enumeratedValue, key=lambda x: x.value)):
enum_decl = LanDeclaration((e.name).upper(), e.value)
enum_decl.intType = "... | [
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] | [
"\"\"\"\n\t\tCreate declaration objects for enumerated values of IP-XACT field object.\n\t\t\"\"\""
] | [
{
"param": "self",
"type": null
},
{
"param": "field",
"type": null
}
] | {
"returns": [],
"raises": [],
"params": [
{
"identifier": "self",
"type": null,
"docstring": null,
"docstring_tokens": [],
"default": null,
"is_optional": null
},
{
"identifier": "field",
"type": null,
"docstring": null,
"docstring_tokens": ... |
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