repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
cheriot-rtos | github_2023 | others | 84 | CHERIoT-Platform | rmn30 | @@ -0,0 +1,55 @@
+Interrupt handling in CHERIoT RTOS
+==================================
+
+CHERIoT RTOS does not allow user code to run directly from the interrupt handler.
+The scheduler has a separate stack that is used to run interrupt handler and this then maps interrupts to scheduler events. | ```suggestion
The scheduler has a separate stack that is used to run the interrupt handler and this then maps interrupts to scheduler events.
``` |
cheriot-rtos | github_2023 | others | 84 | CHERIoT-Platform | rmn30 | @@ -0,0 +1,100 @@
+Static sealed objects in CHERIoT RTOS
+=====================================
+
+CHERIoT is a capability system.
+This extends from the hardware (all memory accesses require an authorising capability in a register, provided as an operand to an instruction) up through the software abstractions in the R... | ```suggestion
This problem is addressed by providing a mechanism for provisioning software-defined capabilities (managed by one compartment) to another compartment at *build time*.
``` |
cheriot-rtos | github_2023 | others | 84 | CHERIoT-Platform | rmn30 | @@ -0,0 +1,100 @@
+Static sealed objects in CHERIoT RTOS
+=====================================
+
+CHERIoT is a capability system.
+This extends from the hardware (all memory accesses require an authorising capability in a register, provided as an operand to an instruction) up through the software abstractions in the R... | ```suggestion
It gives the unique symbol name for the sealing key (which includes the compartment name, `static_sealing_inner`, and the key name, `SealingType`) and indicates that it is a sealing key.
``` |
cheriot-rtos | github_2023 | cpp | 82 | CHERIoT-Platform | nwf-msr | @@ -316,29 +315,395 @@ namespace
return capability;
}
+ /**
+ * Object representing a claim. When a heap object is claimed, an instance
+ * of this structure exists to track the reference count per claimer.
+ */
+ class Claim
+ {
+ /**
+ * The identifier of the owning allocation capability.
+ */
+ uint... | A single...? |
cheriot-rtos | github_2023 | cpp | 82 | CHERIoT-Platform | nwf-msr | @@ -316,29 +315,395 @@ namespace
return capability;
}
+ /**
+ * Object representing a claim. When a heap object is claimed, an instance
+ * of this structure exists to track the reference count per claimer.
+ */
+ class Claim
+ {
+ /**
+ * The identifier of the owning allocation capability.
+ */
+ uint... | ```suggestion
// Drop the reference. If this results in the last reference going away,
``` |
cheriot-rtos | github_2023 | cpp | 82 | CHERIoT-Platform | nwf-msr | @@ -316,29 +315,395 @@ namespace
return capability;
}
+ /**
+ * Object representing a claim. When a heap object is claimed, an instance
+ * of this structure exists to track the reference count per claimer.
+ */
+ class Claim
+ {
+ /**
+ * The identifier of the owning allocation capability.
+ */
+ uint... | if we can... free it now, because it is otherwise unclaimed? |
cheriot-rtos | github_2023 | others | 79 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,120 @@
+Design of the allocator claims model
+====================================
+
+This document describes the design of the claim model that the allocator should provide and how it should be implemented.
+
+The problem
+-----------
+
+Consider the scenario where compartment A passes a heap buffer to comp... | ```suggestion
This is a concurrent operation and so sets the stage for classic TOCTOU problems.
```
as we haven't actually said that B has performed any Checks yet. |
cheriot-rtos | github_2023 | others | 79 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,120 @@
+Design of the allocator claims model
+====================================
+
+This document describes the design of the claim model that the allocator should provide and how it should be implemented.
+
+The problem
+-----------
+
+Consider the scenario where compartment A passes a heap buffer to comp... | :+1: |
cheriot-rtos | github_2023 | others | 79 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,120 @@
+Design of the allocator claims model
+====================================
+
+This document describes the design of the claim model that the allocator should provide and how it should be implemented.
+
+The problem
+-----------
+
+Consider the scenario where compartment A passes a heap buffer to comp... | This traversal would have to be done with interrupts off. In LF SMR's use of hazards, there's a global cooperative assumption that threads will not share their local copies of pointers, so that the number of copies of a given pointer in the hazard lists is strictly decreasing with time. That's not necessarily true of... |
cheriot-rtos | github_2023 | others | 79 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,120 @@
+Design of the allocator claims model
+====================================
+
+This document describes the design of the claim model that the allocator should provide and how it should be implemented.
+
+The problem
+-----------
+
+Consider the scenario where compartment A passes a heap buffer to comp... | In the spirit of "O(n) but n is 3", it could suffice to just have a single list of all claims. If that's too flippant, a small hash table keyed on address could also work. In either case, we'd just need one bit in the header to bring the (potential) claims to deallocation's attention. |
cheriot-rtos | github_2023 | others | 79 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,120 @@
+Design of the allocator claims model
+====================================
+
+This document describes the design of the claim model that the allocator should provide and how it should be implemented.
+
+The problem
+-----------
+
+Consider the scenario where compartment A passes a heap buffer to comp... | What happens on saturation, the object becomes immortal? |
cheriot-rtos | github_2023 | others | 79 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,120 @@
+Design of the allocator claims model
+====================================
+
+This document describes the design of the claim model that the allocator should provide and how it should be implemented.
+
+The problem
+-----------
+
+Consider the scenario where compartment A passes a heap buffer to comp... | Ack; I had a comment here and I'm not sure where it went. :(
In any case: how is compartment B notified that ownership of the object has transferred from compartment A? When does either compartment B or the allocator know to free the object? |
cheriot-rtos | github_2023 | others | 79 | CHERIoT-Platform | rmn30 | @@ -0,0 +1,120 @@
+Design of the allocator claims model
+====================================
+
+This document describes the design of the claim model that the allocator should provide and how it should be implemented.
+
+The problem
+-----------
+
+Consider the scenario where compartment A passes a heap buffer to comp... | The allocators traversal could do a subobject check, although we could really do with an `issubset` instruction for that. |
cheriot-rtos | github_2023 | others | 34 | CHERIoT-Platform | rmn30 | @@ -6,10 +6,9 @@ SECTIONS
. = 0;
.compartment_export_table : ALIGN(8)
{
- # Space for the compartment's PCC and GDC
+ # Space for the compartment's PCC and GDC and an empty thingy. | ```suggestion
# Space for the compartment's PCC and GDC and -1 for no compartment_error_handler
``` |
cheriot-rtos | github_2023 | others | 74 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,155 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+#pragma once
+
+#include <stdint.h>
+
+/**
+ * Concept for checking that a UART driver exposes the right interface.
+ */
+template<typename T>
+concept IsUart = requires(volatile T *v, uint8_t byte)
+{
+ {v->init()};... | Maybe add `static_assert(std::is_standard_layout<Uart>);`
Maybe move the `static_assert(IsUart<Uart>);` outside the `#ifndef CHERIOT_PLATFORM_CUSTOM_UART`, since it probably should hold even of other people's `Uart`s? |
cheriot-rtos | github_2023 | others | 74 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,155 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+#pragma once
+
+#include <stdint.h>
+
+/**
+ * Concept for checking that a UART driver exposes the right interface.
+ */
+template<typename T>
+concept IsUart = requires(volatile T *v, uint8_t byte)
+{
+ {v->init()};... | The 16550 often leaves me speechless as well, but an empty doc comment feels wrong. |
cheriot-rtos | github_2023 | others | 74 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,155 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+#pragma once
+
+#include <stdint.h>
+
+/**
+ * Concept for checking that a UART driver exposes the right interface.
+ */
+template<typename T>
+concept IsUart = requires(volatile T *v, uint8_t byte)
+{
+ {v->init()};... | Switch the order of clearing the latch and the other setup, so that `otherSetup` could, say, kick on IRQs if desired?
```suggestion
// Clear the divisor latch
lineControl = 0x03;
// Run any other setup that we were asked to do.
otherSetup();
``` |
cheriot-rtos | github_2023 | cpp | 78 | CHERIoT-Platform | nwf-msr | @@ -460,11 +460,44 @@ namespace
(size == (LA_ABS(__export_mem_heap_end) -
LA_ABS(__export_mem_heap))))
{
+ Debug::log("Rounding heap ({}--{}) region",
+ target,
+ target + size);
+ // FIXME: This should not be hard coded.
+ static conste... | This is assuming that `end` is suitably aligned. We should probably assert that `(end & ~sizeMask) == 0`?
That is, I don't think it's worth trying to compensate for the case that it isn't, because it really should be, but all the same, an assertion wouldn't go amiss. |
cheriot-rtos | github_2023 | cpp | 78 | CHERIoT-Platform | nwf-msr | @@ -460,11 +460,44 @@ namespace
(size == (LA_ABS(__export_mem_heap_end) -
LA_ABS(__export_mem_heap))))
{
+ Debug::log("Rounding heap ({}--{}) region",
+ target,
+ target + size);
+ // FIXME: This should not be hard coded.
+ static conste... | Isn't that equivalent to
```suggestion
size_t sizeMask =
__builtin_cheri_representable_alignment_mask(size);
Debug::log("Applying mask {} to size", sizeMask);
size_t roundedSize = size & sizeMask;
```
The intermediate steps are different, in that CRAM is going to give you all ones to t... |
cheriot-rtos | github_2023 | cpp | 77 | CHERIoT-Platform | nwf-msr | @@ -1214,7 +1214,19 @@ extern "C" SchedulerEntryInfo loader_entry_point(const ImgHdr &imgHdr,
// accesses these in the revoker is very small and amenable to auditing
// (the only memory accesses are a load and a store back at the same
// location, with interrupts disabled, to trigger the load barrier).
- auto sca... | ```suggestion
// things worse and is another good reason to use a hardware revoker.
``` |
cheriot-rtos | github_2023 | cpp | 77 | CHERIoT-Platform | nwf-msr | @@ -1214,7 +1214,19 @@ extern "C" SchedulerEntryInfo loader_entry_point(const ImgHdr &imgHdr,
// accesses these in the revoker is very small and amenable to auditing
// (the only memory accesses are a load and a store back at the same
// location, with interrupts disabled, to trigger the load barrier).
- auto sca... | Since we aren't doing the type-level enumeration thing, perhaps
```suggestion
/* Precise: */ false>(
``` |
cheriot-rtos | github_2023 | cpp | 45 | CHERIoT-Platform | nwf-msr | @@ -35,7 +35,7 @@ namespace sched
/**
* The real type of this subclass.
*/
- enum class Type : uint8_t
+ enum class Type : uint32_t | Add a comment that this type is deliberately chosen for compatibility with the allocator-based mechanism (xref `sdk/core/allocator/token.h:/^struct SObjStruct`)?
That said, I don't think we're guaranteed that this one pads after the type like `SObjStruct`s do... I don't think we need it to, necessarily, but it might... |
cheriot-rtos | github_2023 | cpp | 45 | CHERIoT-Platform | nwf-msr | @@ -568,14 +574,11 @@ namespace
}
return false;
};
- bool found = false;
- for (auto &compartment : image.privilegedCompartments)
+ bool found = findExport(image.allocator());
+ if (!found && findExport(image.scheduler())) | It's possibly a bit of a pity that the scheduler isn't represented as a `PrivilegedCompartment` and so we have to special-case these two. |
cheriot-rtos | github_2023 | cpp | 71 | CHERIoT-Platform | rmn30 | @@ -44,6 +44,12 @@ typedef struct
[[cheri::interrupt_state(disabled)]] uint16_t __cheri_compartment("sched")
thread_id_get(void);
+/**
+ * Returns a cacheable (read-only) pointer to a global owned by the scheduler
+ * that contains the current thread ID. Reading this pointer will return the | Incomplete sentence. |
cheriot-rtos | github_2023 | others | 12 | CHERIoT-Platform | saaramar | @@ -180,10 +180,10 @@ compartment_switcher_entry:
cjr cs0
.Lzero_arguments_start:
zeroRegisters a0, a1, a2, a3, a4, a5, t0
- // Enable interrupts of the interrupt-disable bit is not set in flags
- bnez t1, .Lskip_interrupt_disable
- csrsi mstatus, 0x8
-.Lskip_interrupt_disable:
+ // Disable interrupts if th... | There is an extra space there |
cheriot-rtos | github_2023 | others | 70 | CHERIoT-Platform | nwf-msr | @@ -219,15 +219,13 @@ after_zero:
csetaddr cs0, cs0, gp
// The target capability is in ct1. Unseal, check tag and load the entry point offset.
cunseal ct1, ct1, cs0
- // Make sure the export table is valid
- cgettag s0, ct1
- beqz s0, .Linvalid_entry
- // Load the ent... | While you're in the neighborhood, that should be "know", not "known". |
cheriot-rtos | github_2023 | others | 70 | CHERIoT-Platform | nwf-msr | @@ -550,19 +547,12 @@ exception_entry_asm:
// Fetch the base of compartment stack before cincoffset for later
// comparison. The subsequent cincoffset could cause the base to change,
// if the capability becomes unrepresentable. Even though that would clear
- // the tag, which we will detect in check_compartment_... | That last sentence's grammar leaves something to be desired. Perhaps "In that case, the tag will be cleared, and that will cause a trap later in the switcher, forcing an unwind back to the caller" or somesuch? |
cheriot-rtos | github_2023 | others | 70 | CHERIoT-Platform | rmn30 | @@ -550,19 +547,12 @@ exception_entry_asm:
// Fetch the base of compartment stack before cincoffset for later
// comparison. The subsequent cincoffset could cause the base to change,
// if the capability becomes unrepresentable. Even though that would clear
- // the tag, which we will detect in check_compartment_... | Should say fault in the error handler path? |
cheriot-rtos | github_2023 | others | 59 | CHERIoT-Platform | davidchisnall | @@ -16,6 +16,11 @@ option("scheduler-accounting")
set_description("Track per-thread cycle counts in the scheduler");
set_showmenu(true)
+option("stack-low-water-mark")
+ set_default(false)
+ set_description("Build with support for stack low water mark");
+ set_showmenu(true) | This should probably be part of the board config. |
cheriot-rtos | github_2023 | cpp | 59 | CHERIoT-Platform | davidchisnall | @@ -44,33 +44,41 @@ struct TrustedStackFrame
template<size_t NFrames>
struct TrustedStackGeneric
{
- void *mepcc;
- void *c1;
- void *csp;
- void *cgp;
- void *c4;
- void *c5;
- void *c6;
- void *c7;
- void *c8;
- void *c9;
- void *c10;
- void *c11;
- void *c12;
- void *c13;... | ```suggestion
uint8_t padding[
#ifdef CONFIG_MSLWM
13
#else
5
#endif
];
``` |
cheriot-rtos | github_2023 | others | 59 | CHERIoT-Platform | davidchisnall | @@ -181,8 +180,24 @@ compartment_switcher_entry:
cgetbase s1, csp
csetaddr csp, csp, s1
sub s1, s0, s1
- csetboundsexact csp, csp, s1
- zero_stack sp, s0, gp
+ csetboundsexact ct2, csp, s1
+ csetaddr csp, ct2, s0
+#ifdef CONFIG_MSLWM
+ // read and align t... | Please can you turn 0abc1 and 0xbc2 into symbolic constants? |
cheriot-rtos | github_2023 | others | 59 | CHERIoT-Platform | davidchisnall | @@ -181,8 +180,24 @@ compartment_switcher_entry:
cgetbase s1, csp
csetaddr csp, csp, s1
sub s1, s0, s1
- csetboundsexact csp, csp, s1
- zero_stack sp, s0, gp
+ csetboundsexact ct2, csp, s1
+ csetaddr csp, ct2, s0
+#ifdef CONFIG_MSLWM
+ // read and align t... | We probably need to zero the whole thing if the address is not in bounds. I think that is not needed on the return path though. |
cheriot-rtos | github_2023 | others | 59 | CHERIoT-Platform | davidchisnall | @@ -232,6 +232,11 @@ rule("firmware")
add_defines("SIMULATION")
end
+ if board.stack_high_water_mark then | At least the Sail json should probably be updated to include this. |
cheriot-rtos | github_2023 | others | 59 | CHERIoT-Platform | davidchisnall | @@ -607,6 +646,13 @@ exception_entry_asm:
// Load the trusted stack pointer to ct1
cspecialr ct1, mtdc
+#ifdef CONFIG_MSHWM
+ // Update the spilled copy of the stack high watermark to ensure that we | Technically, it should be high-water mark, but this is probably fine. |
cheriot-rtos | github_2023 | cpp | 65 | CHERIoT-Platform | nwf-msr | @@ -1323,22 +1327,25 @@ class MState
}
void ok_any_chunk(MChunkHeader *p)
{
- bool thisShadowBit =
- revoker.shadow_bit_get(CHERI::Capability{p}.address());
- Debug::Assert(thisShadowBit,
- "Chunk header does not point to a set shadow bit: {}",
- p);
- MChunkHeader *next = p->c... | This assert and the next can live outside the `if contexpr`, yes? |
cheriot-rtos | github_2023 | cpp | 44 | CHERIoT-Platform | davidchisnall | @@ -413,19 +413,19 @@ int __cheri_compartment("sched")
}
return typed_op<Event>(evt, [&](Event &event) {
return event.bits_wait(
- retBits, bitsToWait, clearOnExit, waitAll, timeout);
+ retBits, bitsToWait, flags & EventWaitClearOnExit, flags & EventWaitAll, timeout); | It would be nice to wrap this in the same kind of template that I did for PAL features in snmalloc. Something like:
```
template<EventWaitFlags Desired>
bool has_event_flag(int eventFlags)
{
return eventFlags & int(Desired);
}
```
I am always somewhat nervous of raw `&` for checking bitfields because y... |
cheriot-rtos | github_2023 | cpp | 44 | CHERIoT-Platform | davidchisnall | @@ -403,8 +404,7 @@ int __cheri_compartment("sched")
void *evt,
uint32_t *retBits,
uint32_t bitsToWait,
- bool clearOnExit,
- bool waitAll)
+ int flags) | Can we use a fixed-width type here please? |
cheriot-rtos | github_2023 | cpp | 44 | CHERIoT-Platform | davidchisnall | @@ -48,8 +58,22 @@ int __cheri_compartment("sched") event_bits_wait(Timeout *timeout,
void *evt,
uint32_t *retBits,
uint32_t bitsToWait,
- ... | I think GitHub has screwed up rendering the diff here, there's no } for this enum definition in the UI. |
cheriot-rtos | github_2023 | cpp | 44 | CHERIoT-Platform | davidchisnall | @@ -98,3 +121,24 @@ int __cheri_compartment("sched")
event_delete(struct SObjStruct *heapCapability, void *evt);
__END_DECLS
+
+#ifdef __cplusplus | Not sure these should go in the public header: I don't see them as being useful for anything other than the scheduler (a helper for constructing the flags would be). |
cheriot-rtos | github_2023 | cpp | 55 | CHERIoT-Platform | rmn30 | @@ -105,7 +110,17 @@ namespace sched
size_t mepc,
size_t mtval)
{
+ // The cycle count value the last time the scheduler returned.
bool schedNeeded;
+ if constexpr (sched::Accounting)
+ {
+ uint64_t... | Minor nit: I would prefer to introduce a new local `cyclesElapsed` here. |
cheriot-rtos | github_2023 | cpp | 55 | CHERIoT-Platform | rmn30 | @@ -105,7 +110,17 @@ namespace sched
size_t mepc,
size_t mtval)
{
+ // The cycle count value the last time the scheduler returned.
bool schedNeeded;
+ if constexpr (sched::Accounting)
+ {
+ uint64_t... | `threadCycleCounter` would be a more descriptive name. |
cheriot-rtos | github_2023 | cpp | 55 | CHERIoT-Platform | rmn30 | @@ -45,6 +45,11 @@ void simulation_exit(uint32_t code)
#endif
+/**
+ * The value of the cycle counter at the last scheduling event.
+ */
+static uint64_t cyclesAtLastSchedulingEvent; | Since this is not atomic and will take two 32-bit loads / stores to access I guess we have to make sure that all accesses are with interrupts disabled? |
cheriot-rtos | github_2023 | cpp | 55 | CHERIoT-Platform | rmn30 | @@ -642,3 +661,20 @@ int multiwaiter_wait(Timeout *timeout,
return 0;
});
}
+
+#ifdef SCHEDULER_ACCOUNTING
+[[cheri::interrupt_state(disabled)]] uint64_t thread_elapsed_cycles_idle() | Is this interrupts disabled to ensure atomicity of access to `Thread::idleThreadCycles`. If so a comment would not go amiss. |
cheriot-rtos | github_2023 | cpp | 55 | CHERIoT-Platform | rmn30 | @@ -42,3 +42,12 @@
})
#define BARRIER() __asm volatile("" : : : "memory")
+
+/**
+ * Read the cycle counter. Returns the number of cycles since boot as a 64-bit
+ * value.
+ */
+static inline uint64_t rdcycle64()
+{
+ return CSR_READ64(mcycle); | Do we want to make this `minstret` on Sail? |
cheriot-rtos | github_2023 | others | 40 | CHERIoT-Platform | rmn30 | @@ -97,6 +97,25 @@ switcher_scheduler_entry_csp:
bnez t2, .Lforce_unwind
.endm
+.macro zero_stack base top scratch | Add a comment saying that `base` has its address changed and `scratch` is clobbered (obvs). |
cheriot-rtos | github_2023 | others | 40 | CHERIoT-Platform | rmn30 | @@ -97,6 +97,25 @@ switcher_scheduler_entry_csp:
bnez t2, .Lforce_unwind
.endm
+.macro zero_stack base top scratch
+ addi \scratch, \top, -32
+ bge \base, \scratch, 1f
+ // Zero the stack used by the callee.
+0:
+ csc cnull, 0(c\base)
+ csc c... | What is `ct2` referenced here. |
cheriot-rtos | github_2023 | others | 40 | CHERIoT-Platform | rmn30 | @@ -95,6 +95,42 @@ switcher_scheduler_entry_csp:
// make sure the caller's CSP is unsealed
cgettype t2, \reg
bnez t2, .Lforce_unwind
+ // Check that the base is 16-byte aligned
+ cgetbase t2, csp
+ andi t2, t2, 0xf
+ bnez t2, .Lforce_unwind
+ // Check ... | Should this be `bgt`? If base was 16-byte but not 32-byte aligned we would get here `\cbase == \top` but still have 16 bytes to zero. |
cheriot-rtos | github_2023 | others | 40 | CHERIoT-Platform | rmn30 | @@ -95,6 +95,42 @@ switcher_scheduler_entry_csp:
// make sure the caller's CSP is unsealed
cgettype t2, \reg
bnez t2, .Lforce_unwind
+ // Check that the base is 16-byte aligned
+ cgetbase t2, csp
+ andi t2, t2, 0xf
+ bnez t2, .Lforce_unwind
+ // Check ... | Can this ever execute more than once? |
cheriot-rtos | github_2023 | cpp | 40 | CHERIoT-Platform | rmn30 | @@ -35,15 +35,30 @@ namespace
};
constexpr ThreadConfig ThreadConfigs[] = CONFIG_THREADS;
+ /**
+ * Round up to a multiple of `Multiple`, which must be a power of two.
+ */
+ template<size_t Multiple>
+ constexpr size_t round_up(size_t value)
+ {
+ static_assert((Multiple & (Multiple - 1)) == 0,
+ ... | An explanation of the bit-twiddling might be nice, maybe with reference if you found it somehwere? |
cheriot-rtos | github_2023 | cpp | 40 | CHERIoT-Platform | rmn30 | @@ -35,15 +35,30 @@ namespace
};
constexpr ThreadConfig ThreadConfigs[] = CONFIG_THREADS;
+ /**
+ * Round up to a multiple of `Multiple`, which must be a power of two.
+ */
+ template<size_t Multiple>
+ constexpr size_t round_up(size_t value)
+ {
+ static_assert((Multiple & (Multiple - 1)) == 0,
+ ... | Should include a test for already rounded value:
```suggestion
static_assert(round_up<8>(17) == 24);
static_assert(round_up<8>(8) == 8);
``` |
cheriot-rtos | github_2023 | others | 40 | CHERIoT-Platform | rmn30 | @@ -95,6 +95,40 @@ switcher_scheduler_entry_csp:
// make sure the caller's CSP is unsealed
cgettype t2, \reg
bnez t2, .Lforce_unwind
+ // Check that the base is 16-byte aligned
+ cgetbase t2, csp
+ andi t2, t2, 0xf
+ bnez t2, .Lforce_unwind
+ // Check ... | Should mention that `base` and `top` must be 16-byte aligned as I think this is important to the implementation. A unit test for this macro would be good... |
cheriot-rtos | github_2023 | cpp | 43 | CHERIoT-Platform | rmn30 | @@ -11,8 +11,12 @@ using Debug = ConditionalDebug<DEBUG_ALLOCBENCH, "Allocator benchmark">;
*/
void __cheri_compartment("allocbench") run()
{
+ // Make sure sail doesn't print annoying log messages in the middle of the | Is it worth noting that this could be removed once Sail makes s release with this fix: https://github.com/rems-project/sail/commit/362254783e2c0a12b5393169d883ebe5621baa6f |
cheriot-rtos | github_2023 | cpp | 36 | CHERIoT-Platform | davidchisnall | @@ -940,7 +940,7 @@ extern "C" SchedulerEntryInfo loader_entry_point(const ImgHdr &imgHdr,
SchedulerEntryInfo ret;
volatile Uart *uart16550;
- // Populate the 4 roots from system registers. | This actually does populate the four software roots, from the three hardware roots. |
cheriot-rtos | github_2023 | others | 36 | CHERIoT-Platform | davidchisnall | @@ -339,6 +402,15 @@ exception_entry_asm:
reloadRegisters c1, cgp, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, csp
mret
+.Lreentrant_exception: | I'm not sure what we're expecting to happen here. The exception code runs with interrupts disabled, so we should only ever hit this path if we take a trap while handling an interrupt. That can only happen in the case of total internal consistency failure and at that point we should just die. We could achieve that by... |
cheriot-rtos | github_2023 | others | 36 | CHERIoT-Platform | davidchisnall | @@ -32,30 +32,30 @@ start:
la_abs a3, bootStack
li a1, BOOT_STACK_SIZE
- cspecialr ca2, mtdc
- li a4, ~CHERI_PERM_STORE_LOCAL
+ cspecialr ca4, mtdc // Keep the RW memory root in ca4 throughout
+ li a2, ~CHERI_PERM_STORE_LOCAL | :set list |
cheriot-rtos | github_2023 | others | 36 | CHERIoT-Platform | davidchisnall | @@ -303,20 +314,15 @@ exception_entry_asm:
// ca3, used for mtval
zeroAllRegistersExcept ra, sp, gp, a0, a1, a2, a3
- // Call the scheduler. This returns two values via ca0. The first is a
- // sealed trusted stack capability, the second is a return value to be
- // provided to threads that voluntarily yielded.... | This can install a non-null, untagged capability in MTDC. This doesn't matter in release builds, but breaks the debug-mode check. If you move it below the clw, then the clw checks the tag, but please add a comment explaining it. |
cheriot-rtos | github_2023 | cpp | 35 | CHERIoT-Platform | rmn30 | @@ -105,13 +105,18 @@ namespace
*/
FirstDataSealingType = 9,
+ /**
+ * The sealing type used for sealed export table entries. | Why does the comment say export table entries but the name is `ImportTableEntries`? |
cheriot-rtos | github_2023 | cpp | 28 | CHERIoT-Platform | JerryHsia-MS | @@ -8,6 +8,26 @@ using namespace CHERI;
bool *threadStackTestFailed;
+/*
+ * Define a macro that gets a __cheri_callback capability and calls it, while
+ * support adding instruction before the call. This is used to avoid code
+ * duplication, in cases we want to call a __cheri_callback in multiple
+ * places whil... | Very Nit: `fn` should probably have a better name like `handle` because it is not really a function. |
cheriot-rtos | github_2023 | cpp | 28 | CHERIoT-Platform | JerryHsia-MS | @@ -89,8 +108,7 @@ void test_stack_invalid_on_call(bool *outTestFailed,
{
threadStackTestFailed = outTestFailed;
- __asm__ volatile("ccleartag csp, csp\n"
- "csh zero, 0(cnull)\n");
+ CALL_CHERI_CALLBACK(fn, "move a0, %1\nccleartag csp, csp\n", 0); | Is the `move` instruction useless? Might be better with a comment. |
cheriot-rtos | github_2023 | cpp | 28 | CHERIoT-Platform | davidchisnall | @@ -8,6 +8,31 @@ using namespace CHERI;
bool *threadStackTestFailed;
+/*
+ * Define a macro that gets a __cheri_callback capability and calls it, while
+ * support adding instruction before the call. This is used to avoid code
+ * duplication, in cases we want to call a __cheri_callback in multiple
+ * places whil... | These clobbers are wrong. The call clobbers everything except cs0 and cs1 |
cheriot-rtos | github_2023 | others | 22 | CHERIoT-Platform | davidchisnall | @@ -91,11 +91,21 @@ compartment_switcher_entry:
// XXX: This line is useless, only for mscratch to show up in debugging.
cmove ct2, ct2
#endif
- clhu tp, TrustedStack_offset_frameoffset(ct2)
+
// make sure the trusted stack is still in bounds
- cgetlen t2, ct2
- bgeu tp, t2... | Can these be moved before we access mscratch? We don't need access to any privileged state to do these checks. |
cheriot-rtos | github_2023 | others | 22 | CHERIoT-Platform | davidchisnall | @@ -415,6 +425,13 @@ exception_entry_asm:
li a1, 0
// If we don't have enough space, give up and force unwind
bltu t1, tp, .Lforce_unwind
+ // make sure the caller's CSP is valid
+ cgettag t1, ct0
+ beqz t1, .Lforce_unwind
+ // make sure the caller's CSP has the expected permissions
+ c... | These checks are the same as above, can you make them a macro? We should also add a sealing check. |
cheriot-rtos | github_2023 | others | 22 | CHERIoT-Platform | davidchisnall | @@ -79,23 +79,47 @@ switcher_scheduler_entry_csp:
forall reloadOne, \reg1, \regs
.endm
+/**
+ * Verify the compartment stack is valid, with the expected permissions and
+ * unsealed.
+ * This macro assumes t2 and tp are available to use.
+ */
+.macro check_compartment_stack_integrity reg
+ // make sure the caller'... | Can you fix indenting? It looks like you're mixing tabs and spaces. |
cheriot-rtos | github_2023 | others | 22 | CHERIoT-Platform | davidchisnall | @@ -79,23 +79,47 @@ switcher_scheduler_entry_csp:
forall reloadOne, \reg1, \regs
.endm
+/**
+ * Verify the compartment stack is valid, with the expected permissions and
+ * unsealed.
+ * This macro assumes t2 and tp are available to use.
+ */
+.macro check_compartment_stack_integrity reg
+ // make sure the caller'... | ```
// compartment's csp is valid. If not, force unwind.
``` |
cheriot-rtos | github_2023 | cpp | 22 | CHERIoT-Platform | davidchisnall | @@ -44,3 +44,5 @@ EXPORT_ASSEMBLY_SIZE(TrustedStackFrame, (7 * 8))
#define TSTACKOFFSET_FIRSTFRAME \
(TrustedStack_offset_frameoffset + TSTACK_HEADER_SZ)
+
+#define COMPARTMENT_STACK_PERMISSIONS 0x7e | Can you add a doc comment explaining this macro? |
cheriot-rtos | github_2023 | cpp | 27 | CHERIoT-Platform | nwf-msr | @@ -4,10 +4,37 @@
#pragma once
#include <cdefs.h>
+#include <compartment-macros.h>
#include <stddef.h>
#include <stdint.h>
#include <timeout.h>
+#ifndef MALLOC_DEFAULT_QUOTA
+# define MALLOC_DEFAULT_QUOTA 4096
+#endif
+struct MallocCapability | Hm. I think I know why you called this a `Capability`, and I don't completely disagree, but I might prefer `MallocCapabilityState` or `MallocAuthorityState` or something along those lines: it's not a CHERI capability, and (an instance of) *this structure* isn't presented as a capability would be, in general: a (sealed)... |
cheriot-rtos | github_2023 | cpp | 27 | CHERIoT-Platform | nwf-msr | @@ -4,10 +4,37 @@
#pragma once
#include <cdefs.h>
+#include <compartment-macros.h>
#include <stddef.h>
#include <stdint.h>
#include <timeout.h>
+#ifndef MALLOC_DEFAULT_QUOTA
+# define MALLOC_DEFAULT_QUOTA 4096
+#endif
+struct MallocCapability
+{
+ size_t quota;
+ size_t unused;
+ uintptr_t reserved[2]; | I might reserve more space; we might want to have these...
- know a small identifier for themselves (another `uint16_t`),
- be intrusively indexed on that identifier by a list or tree or something (2 or 3 `uintptr_t`s, a la `MChunk` or `TChunk`)
- have a hierarchical relationship amongst themselves (perhaps as a ros... |
cheriot-rtos | github_2023 | cpp | 27 | CHERIoT-Platform | nwf-msr | @@ -52,15 +85,15 @@ void *__cheri_compartment("alloc") heap_allocate(size_t size, Timeout *timeout);
* Memory returned from this interface is guaranteed to be zeroed.
*/
void *__cheri_compartment("alloc")
- heap_allocate_array(size_t nmemb, size_t size, Timeout *timeout);
+ heap_allocate_array(struct SObjStruct ... | Do you want to have an `ifdef __cplusplus` overload for this and for `heap_free`, too? |
cheriot-rtos | github_2023 | cpp | 27 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,174 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+#pragma once
+#include <cdefs.h>
+
+/**
+ * Provide a capability of the type `volatile type *` referring to the MMIO
+ * region exported in the linker script with `name` as its name. This macro
+ * can be used only ... | I know it's not part of this PR, but this comment really should be expanded to include something about this macro being useful *only* within a preprocessor expression. (It's probably best to limit it to preprocessor evaluation contexts rather than pursue terrors like http://hmijailblog.blogspot.com/2016/03/an-isdefine... |
cheriot-rtos | github_2023 | cpp | 27 | CHERIoT-Platform | nwf-msr | @@ -155,4 +162,58 @@ namespace sched
void exception_entry_asm(void);
__END_DECLS
+ template<typename T>
+ struct HeapObject
+ {
+ class Deleter
+ {
+ struct SObjStruct *heapCapability;
+
+ public:
+ Deleter(struct SObjStruct *heapCapability)
+ : heapCapability(heapCapability)
+ {
+ }
+ void oper... | Should that be `heap_free(heapCapability, object)`? |
cheriot-rtos | github_2023 | others | 19 | CHERIoT-Platform | rmn30 | @@ -315,6 +324,14 @@ exception_entry_asm:
reloadRegisters c1, cgp, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, csp
mret
+.Linvalid_csp_permissions:
+ cjal .Lpop_trusted_stack_frame
+ csh zero, 0(cnull) | This will trap. Was it committed by mistake? If not how will the subsequent instructions be reached? |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -123,11 +123,23 @@ namespace
*/
Allocator,
+ /**
+ * The first sealing key that is reserved for use by the allocator's
+ * software sealing mechanism and used for static sealing types,
+ */
+ FirstStaticSoftware = 16,
+
+ /**
+ * The first sealing key in the space that the allocator will
+ * dy... | While you're in the neighborhood, that comment is stale. |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -245,6 +257,50 @@ namespace
return cgp;
}
+ /**
+ * Returns a sealing capability to use for statically allocated sealing
+ * keys.
+ */
+ uint16_t allocate_static_sealing_key()
+ {
+ static uint16_t nextValue = FirstStaticSoftware;
+ // We currently stash the allocated key value in the export table. We
... | ```suggestion
// that space, but 2^16 static sealing keys will require over 768 KiB
``` |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -435,6 +502,51 @@ namespace
return buildMMIO();
}
+ // Privileged compartments don't have sealed objects.
+ if constexpr (!std::is_same_v<
+ std::remove_cvref_t<decltype(sourceCompartment)>,
+ ImgHdr::PrivilegedCompartment>)
+ {
+ if (contains(sourceCompartment.sealedO... | What is `0x10000`? I was sort of expecting to see something about `FirstDynamicSoftware` here or somesuch. (Values larger than that are certainly invalid, so that could be an offset applied to the address of the export table?)
If a dynamic approach is necessary, is there no other metadata in the export table entry... |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -435,6 +502,51 @@ namespace
return buildMMIO();
}
+ // Privileged compartments don't have sealed objects.
+ if constexpr (!std::is_same_v<
+ std::remove_cvref_t<decltype(sourceCompartment)>,
+ ImgHdr::PrivilegedCompartment>)
+ {
+ if (contains(sourceCompartment.sealedO... | If we haven't visited yet? That seems a little worrying as an approach. From our discussion, I thought we could get away with two passes without the need to re-visit anything? |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -874,10 +1060,8 @@ extern "C" SchedulerEntryInfo loader_entry_point(const ImgHdr &imgHdr,
switcherKey.bounds() = 1;
setSealingKey(imgHdr.scheduler(), Scheduler);
setSealingKey(imgHdr.allocator(), Allocator);
- setSealingKey(imgHdr.allocator(),
- static_cast<SealingType>(0x1000000),
- ... | `0xff000000` is `2**32 - FirstDynamicSoftware`? |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -862,9 +868,22 @@ namespace loader
static constexpr uint8_t InterruptStatusMask = uint8_t(0b11)
<< InterruptStatusShift;
+ /**
+ * The flag indicating that this is a fake entry used to identify
+ * sealing types. Nothing should refer to this other than an ... | Is that right? Don't the statically sealed objects also refer to the export table entry to specify what type they're sealed under? |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -49,6 +49,112 @@
ret; \
})
+/**
+ * Helper macro, used by `STATIC_SEALING_TYPE`. Do not use this directly, it
+ * exists to avoid error-prone copying and pasting of the mangled name for a
+ * static sealing type.
+ */
+#define CHERIOT_EMIT_STA... | Assuming this is `SealingTypeEntry`, could you bring it into the assembler via an `i`-type input rather than as a constant? Failing that, a comment for `grep` to find? |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,51 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+#define TEST_NAME "Static sealing (inner compartment)"
+#include "static_sealing.h"
+#include "tests.hh"
+
+using namespace CHERI;
+
+void test_static_sealed_object(Sealed<TestType> obj)
+{
+ // Get our static sealing... | ```suggestion
keyCap.address() >= FirstStaticSoftware,
``` |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,51 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+#define TEST_NAME "Static sealing (inner compartment)"
+#include "static_sealing.h"
+#include "tests.hh"
+
+using namespace CHERI;
+
+void test_static_sealed_object(Sealed<TestType> obj)
+{
+ // Get our static sealing... | ```suggestion
TEST(keyCap.address() < FirstDynamicSoftware,
``` |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,51 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+#define TEST_NAME "Static sealing (inner compartment)"
+#include "static_sealing.h"
+#include "tests.hh"
+
+using namespace CHERI;
+
+void test_static_sealed_object(Sealed<TestType> obj)
+{
+ // Get our static sealing... | ```suggestion
TEST(unsealed->value == 42, "Unexpected value in static sealed object");
``` |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,51 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+#define TEST_NAME "Static sealing (inner compartment)"
+#include "static_sealing.h"
+#include "tests.hh"
+
+using namespace CHERI;
+
+void test_static_sealed_object(Sealed<TestType> obj)
+{
+ // Get our static sealing... | ```suggestion
"Incorrect permissions on static sealing key {}",
``` |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -0,0 +1,51 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+#define TEST_NAME "Static sealing (inner compartment)"
+#include "static_sealing.h"
+#include "tests.hh"
+
+using namespace CHERI;
+
+void test_static_sealed_object(Sealed<TestType> obj)
+{
+ // Get our static sealing... | ```suggestion
"Incorrect permissions on unsealed statically sealed object {}",
``` |
cheriot-rtos | github_2023 | cpp | 16 | CHERIoT-Platform | nwf-msr | @@ -49,6 +49,113 @@
ret; \
})
+/**
+ * Helper macro, used by `STATIC_SEALING_TYPE`. Do not use this directly, it
+ * exists to avoid error-prone copying and pasting of the mangled name for a
+ * static sealing type.
+ */
+#define CHERIOT_EMIT_STA... | GitHub has seemingly eaten my earlier suggestion that this be brought in by name via `"i"(SealingTypeEntry)` |
cheriot-rtos | github_2023 | cpp | 18 | CHERIoT-Platform | davidchisnall | @@ -1056,21 +1079,48 @@ class MState
* @param mem the user cap which has been checked, but has not been
* rederived into an internal cap yet
*/
- void mspace_free(CHERI::Capability<void> mem)
+ int mspace_free(CHERI::Capability<void> mem) | Please document what the return value is. |
cheriot-rtos | github_2023 | cpp | 18 | CHERIoT-Platform | davidchisnall | @@ -215,15 +215,9 @@ namespace
{
return -EINVAL;
}
- /*
- * Since we use the shadow bits to detect valid frees, we need to consult
- * the revoker on whether the user cap is valid.
- */
- if (!revoker.is_free_cap_valid(mem))
- {
- return -EINVAL;
- }
- gm->mspace_free(mem);
+ int rv = gm->mspace_free(mem);
+... | Clang-tidy should complain here. |
cheriot-rtos | github_2023 | others | 8 | CHERIoT-Platform | davidchisnall | @@ -311,6 +315,9 @@ exception_entry_asm:
reloadRegisters c1, cgp, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, csp
mret
+.Lforce_unwind_with_return_values: | Can you leave a comment explaining why this is sufficient?
Other registers have been trampled by the call and so need zeroing. Are they zeroed somewhere else later on?
I believe you may also need to set the inForcedUnwind flag here, to allow returning to a frame that doesn't have an error handler. |
cheriot-rtos | github_2023 | others | 8 | CHERIoT-Platform | davidchisnall | @@ -311,6 +315,16 @@ exception_entry_asm:
reloadRegisters c1, cgp, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, csp
mret
+.Linvalid_entry:
+// Mark this threads as in the middle of a forced unwind. | Can you expand this to explain *why* (we want to resume rather than unwind if the compartment doesn't have an error handler)? |
cheriot-rtos | github_2023 | cpp | 8 | CHERIoT-Platform | davidchisnall | @@ -40,3 +40,9 @@ void test_compartment_call()
compartment_call_inner(value, value, &value, value, &value, value, value);
TEST(ret == 0, "compartment_call_inner returend {}", ret);
}
+
+void test_compartment_call()
+{
+ test_number_of_arguments();
+ test_incorrect_export_table(NULL); | ```suggestion
test_incorrect_export_table(nullptr);
``` |
cheriot-rtos | github_2023 | cpp | 8 | CHERIoT-Platform | davidchisnall | @@ -10,6 +10,12 @@
using namespace CHERI;
+extern "C" ErrorRecoveryBehaviour
+compartment_error_handler(ErrorState *frame, size_t mcause, size_t mtval)
+{
+ return ErrorRecoveryBehaviour::ForceUnwind;
+}
+ | This should be the default, do we need it to exist? |
cheriot-rtos | github_2023 | cpp | 8 | CHERIoT-Platform | davidchisnall | @@ -95,4 +101,17 @@ int compartment_call_inner(int x0,
debug_log("Seven arguments");
verify_arguments(x0, x1, *x2, x3, *x4, x5, x6);
return 0;
+}
+
+void test_incorrect_export_table(__cheri_callback void (*fn)())
+{
+ /*
+ * Trigger a cross-compartment call with an invalid export entry.
+ */
+
+ debug_lo... | Without an error handler, this should be reachable. Can we make sure that this path is tested? |
cheriot-rtos | github_2023 | others | 8 | CHERIoT-Platform | davidchisnall | @@ -336,10 +349,10 @@ exception_entry_asm:
LoadCapPCC cs0, compartment_switcher_sealing_key
// ca2 at this point was loaded by .Lpop_trusted_stack_frame from the pcc
// in the trusted stack and so should always be sealed as a sentry type.
- cgettype gp, cra
+ cgettype gp, ca2 | This looks like it's accidentally reverting a fix? |
cheriot-rtos | github_2023 | cpp | 17 | CHERIoT-Platform | nwf-msr | @@ -1966,6 +1979,8 @@ class MState
unlink_chunk(MChunk::from_header(prev), prev->size_get());
ds::linked_list::unsafe_remove_link(prev, p);
p->clear();
+ // p is no longer a header. Clear the shadow bit.
+ revoker.shadow_paint_single(CHERI::Capability{p}.address(), false); | Maybe move the `shadow_paint_single` into `->clear`? |
cheriot-rtos | github_2023 | cpp | 17 | CHERIoT-Platform | nwf-msr | @@ -2155,15 +2173,22 @@ class MState
// If we reached here, then it means we took a real chunk off the free
// list without errors. Zero the user portion metadata.
size_t size = p->size_get();
- // We sanity check that things off the free list are indeed zeroed out.
- Debug::Assert(capaligned_range_do(p->bod... | I'm still a C++ novice, but I think you can avoid needing to change the `capaligned_range_do` interface by using `&word` here instead: that will turn your `void *&word` into a `void **`. |
cheriot-rtos | github_2023 | cpp | 1 | CHERIoT-Platform | davidchisnall | @@ -0,0 +1,642 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+/**
+ * @file A (circular) doubly linked list, abstracted over cons cell
+ * representations.
+ */
+
+#pragma once
+
+#include <concepts>
+#include <ds/pointer.h>
+
+namespace ds::linked_list
+{
+
+ namespace cell
+ ... | Please don't use abbreviations in names (as per the style guide). Does Prim stand for primitive? Prime? Per the comment, I presume primitive, though it's not really clear what 'primitive' means here. Can it have a more descriptive name (e.g. `CellOperations`)? |
cheriot-rtos | github_2023 | cpp | 1 | CHERIoT-Platform | davidchisnall | @@ -0,0 +1,642 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+/**
+ * @file A (circular) doubly linked list, abstracted over cons cell
+ * representations.
+ */
+
+#pragma once
+
+#include <concepts>
+#include <ds/pointer.h>
+
+namespace ds::linked_list
+{
+
+ namespace cell
+ ... | Can this not use a requires clause instead of `enable_if`? |
cheriot-rtos | github_2023 | cpp | 1 | CHERIoT-Platform | davidchisnall | @@ -0,0 +1,642 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+/**
+ * @file A (circular) doubly linked list, abstracted over cons cell
+ * representations.
+ */
+
+#pragma once
+
+#include <concepts>
+#include <ds/pointer.h>
+
+namespace ds::linked_list
+{
+
+ namespace cell
+ ... | Is this the same as `emplace` in standard-library terminology? |
cheriot-rtos | github_2023 | cpp | 1 | CHERIoT-Platform | davidchisnall | @@ -0,0 +1,642 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+/**
+ * @file A (circular) doubly linked list, abstracted over cons cell
+ * representations.
+ */
+
+#pragma once
+
+#include <concepts>
+#include <ds/pointer.h>
+
+namespace ds::linked_list
+{
+
+ namespace cell
+ ... | ```suggestion
Pointer *prev = this;
Pointer *next = this;
``` |
cheriot-rtos | github_2023 | cpp | 1 | CHERIoT-Platform | davidchisnall | @@ -0,0 +1,642 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+/**
+ * @file A (circular) doubly linked list, abstracted over cons cell
+ * representations.
+ */
+
+#pragma once
+
+#include <concepts>
+#include <ds/pointer.h>
+
+namespace ds::linked_list
+{
+
+ namespace cell
+ ... | Why is this not a constructor? |
cheriot-rtos | github_2023 | cpp | 1 | CHERIoT-Platform | davidchisnall | @@ -0,0 +1,642 @@
+// Copyright Microsoft and CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+/**
+ * @file A (circular) doubly linked list, abstracted over cons cell
+ * representations.
+ */
+
+#pragma once
+
+#include <concepts>
+#include <ds/pointer.h>
+
+namespace ds::linked_list
+{
+
+ namespace cell
+ ... | It feels like this would be cleaner if you exposed a `next()` that had an `operator==` (or, since it's the future now, an `operator<=>`) implemented. |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.