repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
cheriot-rtos | github_2023 | others | 363 | CHERIoT-Platform | rmn30 | @@ -812,6 +812,15 @@ namespace CHERI
return permission_set_from_pointer(ptr);
}
+ /**
+ * Drop some permissions from this capability | Is it worth extending this comment to say that you must use this if dropping global from a sealed cap and that it may produce very slightly smaller code? |
cheriot-rtos | github_2023 | cpp | 363 | CHERIoT-Platform | rmn30 | @@ -240,13 +240,55 @@ namespace
}
} // namespace
+void check_sealed_scoping()
+{
+ Capability<void> o{switcher_current_thread()};
+ TEST(o.is_valid() && (o.type() == CheriSealTypeSealedTrustedStacks),
+ "Shared object cap not as expected: {}",
+ o);
+
+ // Take the address of the o cap, requiring that it... | I had to add this cast in the same situation recently and it is slightly annoying. Could we have an implicit conversion or is that a bad idea? You can also get rid of if you make `oLocal1` `const` as there is a `const` version of the `permissions` method that returns a `PermissionSet`. |
cheriot-rtos | github_2023 | others | 363 | CHERIoT-Platform | davidchisnall | @@ -812,6 +812,20 @@ namespace CHERI
return permission_set_from_pointer(ptr);
}
+ /**
+ * Drop some permissions from this capability.
+ *
+ * Because this function computes the permission mask by clearing bits
+ * in the PermissionSet::omnipotent() all-ones mask, rather than from
+ * the set of perm... | We already have a without method on PermissionSet, please can you make the naming of this consistent? |
cheriot-rtos | github_2023 | others | 364 | CHERIoT-Platform | nwf | @@ -2,7 +2,7 @@
"devices": {
"shadow" : {
"start" : 0x30000000,
- "end" : 0x30004000
+ "length": 0x30000800 | That seems wrong? |
cheriot-rtos | github_2023 | others | 364 | CHERIoT-Platform | nwf | @@ -47,17 +47,17 @@
},
"instruction_memory": {
"start": 0x00101000,
- "end": 0x00140000
+ "end": 0x00120000
},
"heap": {
- "end": 0x00140000
+ "end": 0x00120000
},
"revokable_memory_start": 0x00100000,
"defines" : [
"IBEX",
"S... | Can this not be computed from the `["devices"]["shadow"]["length"]` value somehow? |
cheriot-rtos | github_2023 | others | 364 | CHERIoT-Platform | nwf | @@ -0,0 +1,52 @@
+[35mAllocating compartment[0m: ----- Simple Case -----
+[35mAllocating compartment[0m: Allocated: 0x109910 (v:1 0x109910-0x109940 l:0x30 o:0x0 p: G RWcgm- -- ---) | Any example that includes addresses are specific to a particular board and its memory map... should we include the board in the directory path? |
cheriot-rtos | github_2023 | others | 364 | CHERIoT-Platform | nwf | @@ -0,0 +1,55 @@
+#!/bin/bash
+
+set -e
+
+if [ -z "${SONATA_SIMULATOR}" ] ; then
+ SONATA_SIMULATOR=/cheriot-tools/bin/sonata_simulator
+fi | Purely stylistically, these can all be, for example,
```
: ${SONATA_SIMULATOR:=/cheriot-tools/bin/sonata_simulator}
``` |
cheriot-rtos | github_2023 | others | 364 | CHERIoT-Platform | nwf | @@ -0,0 +1,55 @@
+#!/bin/bash
+
+set -e
+
+if [ -z "${SONATA_SIMULATOR}" ] ; then
+ SONATA_SIMULATOR=/cheriot-tools/bin/sonata_simulator
+fi
+
+if [ -z "${SONATA_SIMULATOR_BOOT_STUB}" ] ; then
+ SONATA_SIMULATOR_BOOT_STUB=/cheriot-tools/elf/sonata_simulator_boot_stub
+fi
+
+if [ -z "$1" ] ; then
+ echo You must specify... | Possibly make this also parametric as the above paths? |
cheriot-rtos | github_2023 | others | 364 | CHERIoT-Platform | nwf | @@ -0,0 +1,55 @@
+#!/bin/bash
+
+set -e
+
+if [ -z "${SONATA_SIMULATOR}" ] ; then
+ SONATA_SIMULATOR=/cheriot-tools/bin/sonata_simulator
+fi
+
+if [ -z "${SONATA_SIMULATOR_BOOT_STUB}" ] ; then
+ SONATA_SIMULATOR_BOOT_STUB=/cheriot-tools/elf/sonata_simulator_boot_stub
+fi
+
+if [ -z "$1" ] ; then
+ echo You must specify... | I kinda wish this were an `expect` script, but I guess this is fine too. :) |
cheriot-rtos | github_2023 | cpp | 373 | CHERIoT-Platform | nwf | @@ -923,17 +923,22 @@ __cheriot_minimum_stack(0x1c0) ssize_t
return 0;
}
-__cheriot_minimum_stack(0xf0) int heap_can_free(SObj heapCapability,
- void *rawPointer)
+__cheriot_minimum_stack(0x260) int heap_can_free(SObj heapCapability,
+ ... | ```suggestion
// insufficient stack immediately after `heap_can_free` has said that it's
``` |
cheriot-rtos | github_2023 | others | 361 | CHERIoT-Platform | davidchisnall | @@ -46,23 +30,45 @@ struct SonataPulseWidthModulation
* as only an 8 bit counter is being used.
*/
uint32_t period;
- } outputs[OutputCount];
- /*
- * Sets the output of a specified pulse-width modulated output.
- *
- * The first argument is the index of the output. The second argument is
- * the perio... | Is there a reason that this isn't a `std::array`? It looks like it's equivalent to a subset of `std:array`. |
cheriot-rtos | github_2023 | others | 361 | CHERIoT-Platform | davidchisnall | @@ -1,37 +1,21 @@
#pragma once
+#include <array> | I think this is stale now? |
cheriot-rtos | github_2023 | others | 361 | CHERIoT-Platform | davidchisnall | @@ -46,23 +30,45 @@ struct SonataPulseWidthModulation
* as only an 8 bit counter is being used.
*/
uint32_t period;
- } outputs[OutputCount];
- /*
- * Sets the output of a specified pulse-width modulated output.
- *
- * The first argument is the index of the output. The second argument is
- * the perio... | Maybe call this `LcdBacklight`? It's a bit confusing to have a thing called Lcd that isn't the LCD interface. |
cheriot-rtos | github_2023 | others | 358 | CHERIoT-Platform | rmn30 | @@ -1659,6 +1659,7 @@ exception_entry_asm:
* mtdc: pointer to TrustedStack
*/
csrw mcause, MCAUSE_THREAD_EXIT
+ csrw mtval, MCAUSE_THREAD_EXIT | Worth a comment here to indicate that this avoids a small info leak to the scheduler? |
cheriot-rtos | github_2023 | others | 358 | CHERIoT-Platform | rmn30 | @@ -274,21 +274,19 @@ __Z26compartment_switcher_entryz:
* and to be run with interrupts deferred, we'd like the switcher, and
* especially its stack-zeroing, to be preemtable.
*/
- cincoffset ct2, csp, -SPILL_SLOT_SIZE
.Lswitch_entry_first_spill:
/*
* FROM: above
* ITO: .Lswitch_just_return (vi... | Unfortunately the negative offset means we don't get to use compressed `c.scsp` instruction here. `ct2` is also not accessible to the compressed `c.csc` so the instruction saved is still a net win. Remind me why we can't do the `cincoffset` before into `sp`? So that we can recover `csp` on entry in the case where the c... |
cheriot-rtos | github_2023 | others | 358 | CHERIoT-Platform | rmn30 | @@ -1021,6 +1050,14 @@ exception_entry_asm:
csetaddr csp, csp, gp
cunseal csp, ca0, csp
// Atlas update: sp: unsealed target thread trusted stack pointer
+ /*
+ * LOCAL SEAL: if the scheduler has shed GL(obal) of the reference it gave
+ * us in a0, then sp will also lack GL(obal) after unse... | > which will likely prove challenging for the scheduler
I think this is understatement?! I'm not so familiar with the scheduler but presumably it keeps the sealed trusted stack pointers in global data structures. It sounds like this would only allow the scheduler to crash itself so not really an issue but I wonder i... |
cheriot-rtos | github_2023 | others | 362 | CHERIoT-Platform | rmn30 | @@ -127,8 +115,12 @@ _Z16token_obj_unsealP10SKeyStructP10SObjStruct:
.hidden _Z23token_obj_unseal_staticP10SKeyStructP10SObjStruct
.globl _Z23token_obj_unseal_staticP10SKeyStructP10SObjStruct
_Z23token_obj_unseal_staticP10SKeyStructP10SObjStruct:
- li a2, CheriSealTypeStaticToken
- j .Ltoken_unseal... | I guess we could avoid these extra instructions by having three versions of `__sealingKey` in memory and loading the appropriate one? I think that would be a net win on space and cycles? |
cheriot-rtos | github_2023 | cpp | 362 | CHERIoT-Platform | rmn30 | @@ -1267,15 +1267,31 @@ extern "C" SchedulerEntryInfo loader_entry_point(const ImgHdr &imgHdr,
sizeof(void *),
PermissionSet{Permission::Global, Permission::Unseal});
- setSealingKey(imgHdr.allocator(), Allocator);
+ /*
+ * The token library unseals both static and dynamic objects, so... | Could we have a `static_assert` here that `StaticToken == (Allocator + 1)`? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | rmn30 | @@ -183,159 +188,266 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
+ /*
+ * Atlas:
+ * mtdc: thread trusted stack pointer
+ * ra: caller return address (nominally; corruption is on them) | > (nominally; corruption is on them)
I think that this is entered via an interrupt disabling sentry so we can be sure that `ra` is a return sentry to the caller. If we ever change that to interrupt inheriting we'd lose that guarantee but I agree it doesn't matter much. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | rmn30 | @@ -183,159 +188,266 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
+ /*
+ * Atlas:
+ * mtdc: thread trusted stack pointer
+ * ra: caller return address (nominally; corruption is on them)
+ * sp: nominally, caller's stack pointe... | ```suggestion
* forcibly unwind if none. Nothing secret from the switcher would be visible.
``` |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Specifically, this is the capability to arguments that don’t fit in registers (including variadic ones).
Note: The caller is not required to zero this, we do, just like a0-a5. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Do we actually rely on this property? I would hope that without it we could accept any return sentry here. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | This took a couple of attempts to parse. The caller is asserting that they don’t care about the values in caller-save registers. There is no obligation to spill them, they may simply be unused. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | I don’t think that’s a safe assumption. What happens if:
- I clear store global from CSP and don’t have local things in cs0?
- I put a heap cap in CSP and free it in another thread? I think this can’t happen yet but will be possible once the switcher runs with interrupts enabled (or we do multicore).
After more ... |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Not that this check checks for store local which ensures that this is a stack and so later accesses cannot fault. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | We might be able to remove this now. I think Ibex and Sail both log cspecialr, it was only Flute that didn't, so we needed to do a cmove to make it log the value. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Maybe explicitly state that the trusted stack grows upwards (i.e. 0 is the initial trusted stack frame, 1 the first cross-compartment call, and so on). |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | We can probably skip this. We've spilled cs0 at this point, so we could use cs0 instead of t2 on line 275 and 282 and therefore preserve the value of ct2. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Still? I guess there was a brief two-instruction period when it wasn't, but I wouldn't want to rely on that. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Clarify that this is the modified csp that includes the save area? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Can you leave a not for formal verification: Ideally, we'd prove that this store is dead and remove this instruction. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Specifically, the length of the new stack. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | This doesn't appear to be used, can we view it as dead at this point? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | ```suggestion
* a0, a1, a2, a3, a4, a5, t0: (still) call argument values / to be zeroed
*/
``` |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | It would be nice to have a different annotation for deltas to the atlas and complete atlases. It would also be nice if the delta atlases included registers that are now dead. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | While you're making things symbolic constants... |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Maybe say explicitly that it's populated by the caller and we've kept that register live throughout this? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Or an untagged capability if the caller is malicious. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Maybe flag this as a proof obligation? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | I've lost track. The clobber of tp is the trusted stack frame?
Can the comment say that explicitly? Terminology like 'drop the reference' is confusing if it means clobbering a register. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Isn't tp now the minimum stack size for the callee? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Isn't it the size of the stack? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | And `.Lafter_zero`? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Vector? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Implicit clobber of cra. Not essential, because the value will be in pcc as well. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -713,77 +1181,147 @@ exception_entry_asm:
cmove csp, ca0
.Linvoke_error_handler:
- // Clear all registers except:
- // cra is set by cjalr. csp and cgp are needed for the called compartment.
- // ca0, used for the register state
- // ca1, used for mcause
- // ca2, used for mtval
+ /*
+ * FROM: ab... | Why is there a label here? Just for documentation? (I accidentally saw this one first, because GitHub scrolled me near the end early on by accident, but I find this makes it hard to read throughout) |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Might be worth having two kinds of dead to use consistently:
- Dead, must not leak.
- Dead, may leak but shouldn't.
I'm not sure if it's worth this distinction though because the risk if we get it wrong is high, so it's probably better to just have a rule 'do not leak dead register values'. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | I find this somewhat misleading, because we have two notions of well-bracketed. We cannot assume intra-compartment well-bracketed control flow, but we can assume / enforce well-bracketed cross-compartment control flow. If something deeply nested in a compartment invokes this return sentry, that's fine, we pop the top... |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Why is this a label? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | This is reached *after* we've done the stack checks, so csp contains the store things? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | What happens if csp is write-only? We fault here and force unwind (I think we have a test for that, and I think it passes?)? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | ```suggestion
// Zero everything else
zeroAllRegistersExcept ra, sp, gp, s0, s1, a0
```
NFC. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | I don't think interrupts are either of those things? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | I know we still have the header with the silly name, but can we avoid tstack as a contraction? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | It would be nice if the atlases could capture this. We have a load of live-in mtdc, but it's almost an invariant that mtdc contains the trusted stack on every code path, except for a few where it contains the (untrusted) captured csp. That's possibly a better property to document than the fact that mtdc is live in. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | As previously, I think this can go. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Can you check the disassembly. In an older version, this kind of comment was breaking line numbers. I think it's fixed, but that's why I avoided multi-line comments originally. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Can you document that this is writing 0 but we can't do `cspecialw mtcc, cnull` because `cspecialw` is actually an alias for `cspecialrw` and `cnull` as the source means 'don't write'?
I'd prefer an explicit move from cnull here because the branch guarantees only that the address is 0. `csp` may still be tagged and... |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | Maybe rename it to something like `.Lexiting_threads_rejoin`? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -183,222 +190,479 @@ switcher_scheduler_entry_csp:
.p2align 2
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
- cincoffset csp, csp, -SPILL_SLOT_SIZE
- csc cs0, SPILL_SLOT_cs0(csp)
- csc cs1, SPILL_SLOT_cs1(csp)
- csc cgp, SPILL... | mtval? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -414,25 +678,39 @@ exception_entry_asm:
csrr t1, mcause
csw t1, TrustedStack_offset_mcause(csp)
- // If we hit one of the exception conditions that we should let
- // compartments handle then deliver it to the compartment.
- // CHERI exception code.
- li a0, 0x1c
+ ... | The name of the label is more accurate than the comment, because we only *might* let the compartment handle it. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -414,25 +678,39 @@ exception_entry_asm:
csrr t1, mcause
csw t1, TrustedStack_offset_mcause(csp)
- // If we hit one of the exception conditions that we should let
- // compartments handle then deliver it to the compartment.
- // CHERI exception code.
- li a0, 0x1c
+ ... | Doc-only label? Can we annotate these in some way so I don't look for jumps to it? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -444,57 +722,106 @@ exception_entry_asm:
LoadCapPCC csp, switcher_scheduler_entry_csp
LoadCapPCC cgp, switcher_scheduler_entry_cgp
LoadCapPCC cra, switcher_scheduler_entry_pcc
+ /*
+ * Atlas:
+ * ra, gp: scheduler compartment context
+ * sp: scheduler thread context
+ * a0: seale... | Note that the scheduler can reach the compartment-call entry point, we should document that the zero-mtdc defends against it trying to do cross-compartment calls from here. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -444,57 +722,106 @@ exception_entry_asm:
LoadCapPCC csp, switcher_scheduler_entry_csp
LoadCapPCC cgp, switcher_scheduler_entry_cgp
LoadCapPCC cra, switcher_scheduler_entry_pcc
+ /*
+ * Atlas:
+ * ra, gp: scheduler compartment context
+ * sp: scheduler thread context
+ * a0: seale... | We could also remove mcall (or treat it as a local error that goes to the error handler) and expose a yield entry point, if that would simplify the code. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -504,207 +831,348 @@ exception_entry_asm:
csrw CSR_MSHWMB, ra
#endif
cspecialw mepcc, ct2
- // csp (c2) will be loaded last and will overwrite the trusted stack pointer
- // with the thread's stack pointer.
+
+ /*
+ * reloadRegisters restores registers in the order given, and we ensure t... | We never fall through from here and `.Linstall_return_context` has no predecessors, so I think this can be simplified by:
- Move `.Lhandle_error_in_switcher` above `.Linstall_return_context`
- Remove the `j .Lhandle_error_in_switcher`.
- Invert the condition on 918 and have the normal path be the fallthrough on... |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -504,207 +831,348 @@ exception_entry_asm:
csrw CSR_MSHWMB, ra
#endif
cspecialw mepcc, ct2
- // csp (c2) will be loaded last and will overwrite the trusted stack pointer
- // with the thread's stack pointer.
+
+ /*
+ * reloadRegisters restores registers in the order given, and we ensure t... | This lacks an atlas / live ins, but the label goes away if you make the change above. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -504,207 +831,348 @@ exception_entry_asm:
csrw CSR_MSHWMB, ra
#endif
cspecialw mepcc, ct2
- // csp (c2) will be loaded last and will overwrite the trusted stack pointer
- // with the thread's stack pointer.
+
+ /*
+ * reloadRegisters restores registers in the order given, and we ensure t... | Don't we want to hit the thread exit path in that case? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -504,207 +831,348 @@ exception_entry_asm:
csrw CSR_MSHWMB, ra
#endif
cspecialw mepcc, ct2
- // csp (c2) will be loaded last and will overwrite the trusted stack pointer
- // with the thread's stack pointer.
+
+ /*
+ * reloadRegisters restores registers in the order given, and we ensure t... | Missing atlas, live-ins, predecessors. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -504,207 +831,348 @@ exception_entry_asm:
csrw CSR_MSHWMB, ra
#endif
cspecialw mepcc, ct2
- // csp (c2) will be loaded last and will overwrite the trusted stack pointer
- // with the thread's stack pointer.
+
+ /*
+ * reloadRegisters restores registers in the order given, and we ensure t... | Why did you change the comment style here? We don't put comments on the end of lines anywhere else in the switcher, do we? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | davidchisnall | @@ -713,77 +1181,147 @@ exception_entry_asm:
cmove csp, ca0
.Linvoke_error_handler:
- // Clear all registers except:
- // cra is set by cjalr. csp and cgp are needed for the called compartment.
- // ca0, used for the register state
- // ca1, used for mcause
- // ca2, used for mtval
+ /*
+ * FROM: ab... | Maybe not this PR, but I think we can assume MSHWM now. We haven't tested without it for ages and I expect everyone to use it. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -119,33 +159,12 @@ switcher_scheduler_entry_csp:
forall reloadOne, \reg1, \regs
.endm
-/**
- * Verify the compartment stack is valid, with the expected permissions and
- * unsealed.
- * This macro assumes t2 and tp are available to use.
- */
-.macro check_compartment_stack_integrity reg
- // Check that the call... | How is top still a cap, addi instruction is used. c\base is still a cap? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | How can this be invoked except through a cross-compartment call? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | Line 190: What are hazard pointers? (Can't comment on a non changed line on git) |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | Good to state all registers except tp, t2 (which are both dead as explained below) and zero (which is unnecessary) |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | For tail call optimization? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | Maybe link to the documentation in the ISA doc also (Section 5.4)? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | Not sure what you mean here. Yes, if the lowest address is less than the base, this is guaranteed. But there could be other bounds check violations (higher than top, etc), no? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | Stack sizes are guaranteed to be between the 2^12 and 2^13 range (i.e. between 4089 and 8176) ? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | The LIVE OUT doesn't capture, for instance ct2 which is still alive and used. Not sure if LIVE OUT is helping. Just having alive, dead-again and dead-still list would suffice. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | Simpler to state as follows:
// s0 = old csp's address
// csp = {base = old csp's base, length = offset of old csp's top from base, address = old csp's address, tag = old csp's tag, permission = old csp's permission}
|
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | What does "stack boundary between ..." mean? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | new t2 is "dead-again", so referring to it is not very helpful. Better to use the old values instead of a "dead-again" value. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | What happens if the high water mark is below the base of the stack?
|
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +203,275 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | Finished reviewing till this line. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +206,285 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | Easier to specify what the length is |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | vmurali | @@ -184,99 +206,285 @@ switcher_scheduler_entry_csp:
.type __Z26compartment_switcher_entryz,@function
__Z26compartment_switcher_entryz:
/*
- * Spill caller-save registers carefully. If we find ourselves unable to do
- * so, we'll return an error to the caller (via the exception path; see
- * .Lhandle_error_in_... | Hmm, what's the guarantee that this wouldn't fail?
Is there a better way to carve things out so that we dont fail here instead of trying to use csetboundsexact and failing? Perhaps get the cap with the same base but smaller length? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | rmn30 | @@ -27,6 +27,21 @@
#define SPILL_SLOT_pcc 24
#define SPILL_SLOT_SIZE 32
+/*
+ * RISC-V custom-use mcause values for RTOS internal use.
+ * See also include/priv/riscv.h, which defines the same names and values in C | maybe we should have a c header file with the macro definitions and include it in both places? |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | rmn30 | @@ -298,98 +512,190 @@ __Z26compartment_switcher_entryz:
// Get the flags field into tp
clbu tp, ExportEntry_offset_flags(ct1)
+ // Atlas update: tp: callee entry flags field
+
+ // All ExportEntry state has been consulted; move to ExportTable header
cgetbase s1, ct1
csetaddr ... | This instruction actually enable interrupts, right? In that case the label should be called `skip_interrupts_enable`. |
cheriot-rtos | github_2023 | others | 320 | CHERIoT-Platform | rmn30 | @@ -298,98 +512,190 @@ __Z26compartment_switcher_entryz:
// Get the flags field into tp
clbu tp, ExportEntry_offset_flags(ct1)
+ // Atlas update: tp: callee entry flags field
+
+ // All ExportEntry state has been consulted; move to ExportTable header
cgetbase s1, ct1
csetaddr ... | Maybe a more informative name for this label would be `switcher_after_compartment_call`? |
cheriot-rtos | github_2023 | c | 353 | CHERIoT-Platform | davidchisnall | @@ -300,3 +302,9 @@ typedef union
__divmoddi4(a, b, &r);
return r;
}
+
+// Return the product of a and b
+[[clang::no_builtin]] arith64_u64 __multi3(arith64_u64 a, arith64_u64 b) | I think this should be s64 not u64, it doesn’t actually affect codegen. |
cheriot-rtos | github_2023 | cpp | 346 | CHERIoT-Platform | davidchisnall | @@ -258,6 +258,15 @@ namespace sched
size_t mepc,
size_t mtval)
{
+#if !defined(NDEBUG) | We don’t really use these macros anywhere, this should probably be a constexpr if on the scheduler debug flag. |
cheriot-rtos | github_2023 | cpp | 346 | CHERIoT-Platform | davidchisnall | @@ -258,6 +258,15 @@ namespace sched
size_t mepc,
size_t mtval)
{
+#if !defined(NDEBUG)
+ /* Ensure that we got here from an IRQ-s deferred context */
+ void *returnAddress = __builtin_return_address(0);
... | This can use Capability::type, which you can do without a cast if you make the 263 a Capability instead of a bare pointer. |
cheriot-rtos | github_2023 | cpp | 346 | CHERIoT-Platform | davidchisnall | @@ -258,6 +258,15 @@ namespace sched
size_t mepc,
size_t mtval)
{
+ if constexpr (DebugScheduler)
+ {
+ /* Ensure that we got here from an IRQ-s deferred context */
+ auto returnAddress = Capability{_... | I would write this as:
```suggestion
Capability returnAddress{__builtin_return_address(0)};
```
But I don't think it matters too much.
|
cheriot-rtos | github_2023 | cpp | 343 | CHERIoT-Platform | davidchisnall | @@ -92,7 +92,7 @@ struct CheckSize
#else
# define EXPORT_ASSEMBLY_NAME(name, value)
# define EXPORT_ASSEMBLY_EXPRESSION(name, expression, value)
-# define EXPORT_ASSEMBLY_OFFSET(structure, field, name, value)
+# define EXPORT_ASSEMBLY_OFFSET(structure, field, name) | ```suggestion
# define EXPORT_ASSEMBLY_OFFSET(structure, field, value)
```
For consistency with the other definition. |
cheriot-rtos | github_2023 | others | 343 | CHERIoT-Platform | davidchisnall | @@ -1,16 +1,29 @@
+#include <unwind-assembly.h>
+
+/**
+ * A direct re-implementation of unwind.h's cleanup_unwind() as a stackless
+ * error handler.
+ *
+ * If there is no registered CleanupList structure (equivalently, there's no
+ * CHERIOT_DURING block active at the time of the fault), then this requests
+ * unwnd... | ```suggestion
* unwinding out of the compartment. Otherwise, we will longjmp() out to the
``` |
cheriot-rtos | github_2023 | others | 345 | CHERIoT-Platform | davidchisnall | @@ -786,6 +789,12 @@ exception_entry_asm:
// Call the handler.
cjalr cra
+ /*
+ * Now that we're back, defer interrupts again before we do anything that
+ * manipulates the TrustedStack.
+ */
+ csrci mstatus, 0x8
+ | Is this necessary? I believe it's fine to take interrupts here and we'll just handle the sentry on the way back. |
cheriot-rtos | github_2023 | cpp | 345 | CHERIoT-Platform | rmn30 | @@ -10,9 +10,18 @@
int crashes = 0;
std::atomic<bool> expectFault;
+static void test_irqs_are_enabled()
+{
+ void *r = __builtin_return_address(0);
+ TEST(__builtin_cheri_type_get(r) == CheriSealTypeReturnSentryEnabling, | For future reference: we have `TEST_EQUAL` which gives better error messages in this situation. |
cheriot-rtos | github_2023 | cpp | 339 | CHERIoT-Platform | rmn30 | @@ -0,0 +1,43 @@
+// Copyright CHERIoT Contributors.
+// SPDX-License-Identifier: MIT
+
+#pragma once
+#include <assembly-helpers.h>
+
+/*
+ * Constant to represent the raw permissions of the compartment CSP. We use
+ * this in the switcher, to verify the CSP comes from the compartment is exactly | ```suggestion
* this in the switcher, to verify the permissions of the CSP that comes from the compartment are exactly
``` |
cheriot-rtos | github_2023 | cpp | 339 | CHERIoT-Platform | rmn30 | @@ -21,6 +21,25 @@ struct CheckSize
static constexpr bool value = Real == Expected;
};
+/**
+ * Export a macro into assembly named `name` with value `value`. In C++, this
+ * macro will report an error if the provided value does not equal the constexpr
+ * evaluation of `expression`.
+ */
+# define EXPORT_ASSEMBL... | It took me a minute to work out why we need both of these macros. I guess this one is just the same as `EXPORT_ASSEMBLY_EXPRESSION(name, name, val)` but without a name collision? That makes me think maybe we should use `{}` around the definition below? |
cheriot-rtos | github_2023 | cpp | 339 | CHERIoT-Platform | rmn30 | @@ -75,6 +75,7 @@ namespace priv
constexpr size_t MCAUSE_LOAD_PAGE_FAULT = 13;
constexpr size_t MCAUSE_STORE_PAGE_FAULT = 15;
constexpr size_t MCAUSE_THREAD_EXIT = 24;
+ constexpr size_t MCAUSE_THREAD_INTERRUPT = 25;
constexpr size_t MCAUSE_CHERI = 28; | This could be a separate PR but these constants are needed in error handlers so we should make them more publicly available in the SDK. |
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