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H: How to control the gain of more than one TDA2030/2050 IC with a single potentiometer?
I am on a project of making a music system which will be able to output 6 speakers. I want to control the gain of each six TDA2030/50 ICs with a single potentiometer.
Here is a schematic example of 2 ICs controlling with a single potentiometer, I have tried but does not seem to work correctly.
simulate this circuit – Schematic created using CircuitLab
When I tried this schematic, I get music sound but also with music, it offers some free noises.
Now some of you may think that this might be the answer I am looking for but, unfortunately, the answer schematic given here is not understandable to me as a beginner, and I don't want to use another TDA IC to generate a static voltage or something like that which may create difficulties for me to understand. I only want to use either BJTs (2N2222A) or MOSFETs (IRFZ44N), so if anyone here has a solution for me, please do me a favor by sharing it with a proper understandable schematic and pointing my mistakes respectively for a beginner like me.
Please avoid suggesting any kinds of ICs for performing this action till there are other ways left.
AI: If we look at the functional schematic in the datasheet:
then it is easy to recognize the common non-inverting (opamp based) amplifier structure. I marked the feedback which sets the gain.
The TDA2030 does not have an input for adjusting the gain.
I do not "see" how your proposed circuit can even work as the transistors cannot "work like a resistor" in the way that would be needed for this. And even if it worked, the transistor will be somewhat non-linear and that will introduce distortion in the feedback circuit which really should be linear.
The solutions that I see are to use a different audio amplifier, one that does have a volume (or gain) control input.
If you want to keep using the TDA2030 or any other amplifier without a volume control input then for two channels, use a "stereo potmeter". For more channels, use a volume control IC, this is what is used in many commercial multi-channel amplifiers. |
H: Automatic CAN bus termination
I have two CAN busses which are each terminated on each end by a 120Ω resistor, as shown in the diagram below. The CAN bus consists of a CAN high, CAN low and ground connection. To terminate it, a 120Ω resistor connects CAN high and CAN low.
Sometimes I want to use both CAN busses completely separate but in some situations, I want to connect the devices D3 and D4 together, making a single bigger CAN bus.
To connect the two, I need to remove the two resistors R2 and R3 and then connect the CAN bus together.
My CAN connection currently terminates in a D-SUB connector X1 (at each end D1, D3, D4, D6) to easily connect other CAN devices. At the same time I have a switch (S1) that will enable or disable the CAN bus termination, as can be seen in the schematic below.
What I want to do is to remove the manual operation of the switch S1 by including something in the D-Sub connector X1. When nothing is connected to it, the terminating resistor R1 will connect CAN high and CAN low. But when I connect another device to the connector X1, the resistor R1 will not connect CAN high and CAN low anymore.
I would appreciate any tips that point me towards a possible solution. I should also mention that connecting and disconnecting any device will happen when everything is powered off and does not need to happen during operation.
AI: The first thing you must do is to fix your incorrect connector pin-out and turn it into CAN. DB9 connectors for CAN are widely standardized and professional engineers follow industry standards. You should have CANHI=7, CANLO=2, GND=3.
Once you have turned your pin-out into CAN, the simplest solution might be to buy pre-made DB9 terminators and plug those in whenever you don't connect the buses together. For example these: https://www.kvaser.com/product/kvaser-d-sub-9-pin-120-ohm-termination-adapter-2/ (though Kvaser specifically are ridiculously expensive - there's plenty of 2nd source doing the same thing for a 10th of the price).
Alternatively, you could also connect two pins of the DB9 connector together at each end (to once again violate the standard pin-out...) and then have that signal activate an analog switch, which in turn enables the resistor on that board only. Larger BOM but cheaper external adapters. |
H: Why the output voltage of a transfer function is not equal to zero when the exciting signal is at the frequency of the zero
I was reading this document and I found something that I did not understand ...
https://cbasso.pagesperso-orange.fr/Downloads/PPTs/Chris%20Basso%20APEC%20seminar%202016.pdf
Suppose the following transfer function :
$$\frac{Vout(s)}{Vin(s)} = \frac{1+\frac{s}{w_z}}{1+\frac{s}{w_p}}$$
When :
$$s = -w_z <=> Vout(-w_z) = 0 $$
The question is what is s ? In the Laplace domain s is defined as :
$$s = \sigma + jw$$
In the Fourier domaine sigma is equal to 0. So Fourier domaine is included in the Laplace domaine. Suppose s is equal to :
$$s = jw$$
Then
$$-w_z = jw$$
or
$$w = jw_z$$
And now how I can apply a signal at a frequency :
$$f = 2\pi \cdot jw_z$$ ?
Thank you very much and have a nice day !
AI: Why the output voltage of a transfer function is not equal to zero
when the exciting signal is at the frequency of the zero
Setting the denominator to 1 (because you are talking about the zero conditions rather than poles), we get: -
$$H(s) = 1+\dfrac{s}{\omega_z}$$
And, if the imaginary part of s is chosen to be \$j\omega_z\$, the transfer function is: -
$$H(s) = 1+j$$
And clearly that isn't zero but, how to find a value of s that produces a zero?
To make this happen means we have to set the TF to zero and solve for s in its general form: -
$$0 = 1+\dfrac{\alpha+j\omega}{\omega_z}$$
$$-1 = \dfrac{\alpha+j\omega}{\omega_z}$$
$$-\omega_z = \alpha+j\omega$$
$$j\omega = -\alpha - \omega_z$$
But, in the real world of signal generators, oscilloscopes and bode plots, we cannot make our signal like that; the "zero" does occur, but not along any axis we can see on a bode plot. If you plotted the pole zero diagram (this of course includes an axis for \$\sigma\$ as well as \$j\omega\$) you would see it. But, the pole zero diagram is really an abstraction from the real world and, is mathematically useful but only if you grasp it.
Fourier is along the \$j\omega\$ axis and, Laplace is the fuller story to put it simply.
For instance, an example diagram I have shows the bode plot of a 2nd order low pass filter and the pole-zero diagram combined: -
If you looked at the bode plot part (our real world of oscilloscopes and generators) you would see this: -
And behind the bode plot (into the page so to speak) you can see a pole. In other words, what we see in the world of oscilloscopes and signal generators is just a thin slice of a bigger mathematical picture called the pole zero diagram. |
H: Timers prescale and postscale
So i understand that a prescaler divides a clock, and PR2 is the period register which when the timer TMR2 reaches the value it increments from 0.
Why is a post scaler needed to divide a non-clock signal.
From the diagram it looks like the post scaler is trying to divide the comparator signal for when the first timer TMR2 reaches PR2 value.
I dont understand, couldnt another timer be used to identify when TMR2 reaches N iterations of reset?
Essentially i dont know what a post scaler performs and why it is used to divide a non-clock signal
AI: This is just an added feature to the timer that allows it to further divide the comparator output by a value from 1 - 16.
Some MCUs have this feature and others don't. It's not strictly necessary but clearly the designers of this one thought it was useful enough that they included it.
Obviously if you set it to "1" it will have no effect. |
H: How to fix an N-channel MOSFET that's always on, without using resistors
First things first: I'm very new to electronics
Getting right into it: I am trying to use an N-channel MOSFET as a LED strip light switch, with 12V at 1.5A supplied to the source and 4.5V from a battery supplied to the gate:
simulate this circuit – Schematic created using CircuitLab
However, I find that even without connecting the wires to my battery, my mosfet seems to allow flow from source to drain.
I'm hoping that someone may be able to tell me what is wrong and how I can fix it. The MOSFET I have is an FQU13N10L.
In addition I also have some particulars about the answers:
This circuit is just a test for a larger project which involves about 60 MOSFETs on a breadboard, which cramps my breadboard. I need a solution that does not involve resistors or capacitors that will cramp up a lot of space on my bread board;
Second, if needed I can change the 4.5V to be 3V or 3.3V by using different batteries;
Third, it may be important to note that the gate voltage of 4.5V is controlled by a GPIO pin on a PIC microcontroller. I do not know if that matters but I need nothing to go through the 4.5 lines that may hurt the microcontroller, which can not handle 12V.
I apologize if I sound demanding in this, I am just trying to be as clear in my purpose as possible, thank you for all your answers
AI: Leaving the gate floating (when the switch is open) can lead to what you are seeing; the gate is high-impedance and charge can accumulate on it, switching the FET.
It needs a pull-down resistor on its gate to make things predictable (explicitly driving the gate to 0 V when the switch is open), space or no space on your breadboard.
I don't know about the PIC you are using; it may have internal pull-up and/or pull-down resistors you can activate in code, or actively drive its pins high and low.
You could use this instead of external pull-down resistors when you drive the gates directly from the PIC's IO pins. It would leave the gates in an undefined state until the PIC has booted up and has configured the pins, though. |
H: Circuit analysis technique, is there a different way to solve the question?
The above question I solved it as follows:
But, I noticed the following:
Is there a different method to solve this question?
AI: None of the four stated answers are correct. Using Millman's theorem, the voltage between A and B is 23.377 volts. If you ignore the 2 Ω resistor (i.e. consider it to be open circuit) then the answer is 38.298 volts and this matches one of the four given answers. |
H: How does a repeater convert light from a fibre-optic cable into binary?
I'm just starting out in Computer Science and currently learning about transmission of data in fibre-optic cables. I understand fibre-optic attenuation and that a repeater will then take this light and amplify it.
My question is, how is the repeater doing this? What is the process in which the repeater takes light in and converts this to binary code? I completely understand the physical pulses represent 1 and 0, but how is this being read by the repeater?
To my very little understanding, I'm assuming the light is not pulsing any electrical current of any kind to be read by transistors like how they would be in a physical computer.
Thanks.
AI: How does a repeater convert light from a fibre-optic cable into
binary?
The received light is converted to an electrical signal using (typically) a photodiode: -
It converts incident light power into a current. The current is (usually) converted to a voltage using a TIA (transimpedance amplifier): -
And the voltage can be converted into a series of logic bits using a voltage comparator: -
That's the simple story.
The more complex story involves automatic gain circuits in case the light level changes over time and distance (usually the case). The more complex story can involve a tweaking of the hardware based on what data is received i.e. if error rate appears to be a little too high, there can be feedback to the hardware that tweaks things this way or that way in order to reduce the error rate. |
H: Generate N pulse with a fix frequency STM32f107
I need to know how to generate N pulse with STM32f107 without any external sampling.
Could you provide me any good reference?
Thanks
AI: I can think of 3 possible ways to generate N pulses.
The first method is obvious: Generate a PWM with 50% duty cycle using a TIM module. Count overflows with update event interrupt. In the interrupt, stop TIM when you reach N overflows. This method has some interrupt overhead and may not be suitable if the required frequency is high.
The second method is a little bit strange: You can abuse an SPI module. In this case your frequency and N options are limited: You can only choose one of the possible SPI clock options and N must be divisible by 8 (Not STM32F107 but some other devices may provide more flexible options for N). Using DMA, send N / 8 bytes, and the SPI clock pin will generate your N pulses. This methods doesn't need interrupts, but you may set a DMA transfer complete interrupt to be notified when the transmission of the N pulses is completed.
This one is the modified version of the first method. Instead of counting pulses in the interrupt service routine (ISR), you can configure another TIM module to be the slave of the first one. The master TIM generates the pulses as usual, but each update event causes slave timer to increase its counter value. You can configure the slave timer to generate interrupt when the required pulse count is reached. Compared to the first method, this method has no periodic interrupt overhead, but it costs you an additional TIM module. Also in very high frequencies and in the presence of other high priority interrupts, you may get additional pulses as the ISR may need some time to find a chance to run and disable the master timer. |
H: Switchable current shunt resistor
Looking at the reference design given for INA826 in the image below, what would my best options be if i wanted to replace J8 with something allowing me to switch in R19 (sense resistor) from a microcontroller (3.3v GPIO)? I am thinking something like a FET, but my design knowledge on the subject is not strong enough to know how to do this with the lowest possible impact on my current readings?
The final circuit will be used to measure inputs on J9:
Voltage: +/-10V, +/-5V, 0-10V, 0-5V, mV Inputs
Current: +/-25mA, +/-20mA, 0-20mA, 4-20mA, 5-25mA
So the solution should preferably support bipolar loops.
AI: Given that your input is bipolar (bidirectional TVS diode was a hint and confirmation in a comment) a convention MOSFET is ruled out. I would suggest this type of device from Panasonic: -
It's got low capacitance and sub 1 Ω on-resistance. There are plenty of other variants (also from Panasonic) to be found in this data sheet. |
H: 555 one shot missing a beat
I built a monostable multivibrator circuit with a 7555 chip.
It has 1MΩ and 4.7μF components for timing, giving a pulse width of 5.17 seconds. It also has an RC on the trigger with 10kΩ and 0.33μF for a time constant of 3.3ms, allowing it to trigger at power on. Power is provided by a 5V signal.
Everything looks happy and as expected, for the most part, except there is a weird situation that I can't seem to get a handle on.
For example, here I'm using a pulse function generator on the input. This input is a single power input for the VCC and trigger/timer RC filters. When I bring the 5V signal high for ~2 seconds, then bring it low for 50ms, it retriggers and starts over, just as I would want it to.
BUT! When I bring that signal high for ~2 seconds and then low for just 10ms, something happens where the timer is not restarted. If I keep that input going, it only functions every other cycle.
If it was the trigger signal not having time to get low enough, that wouldn't trigger every other time. It can't be the timing capacitor not discharging fast enough because we see it is getting right down to 0. Scope traces are trigger signal in purple, threshold/discharge signal in yellow.
Why in the world could this be happening?
AI: You mustn't be switching VCC!
By doing that you're relying on the power-up behaviour of the ICM7555 every time. And that's undefined, far as I read the datasheet. So, what happens isn't that surprising: you're taking away the power supply, and that puts TR, CV, DIS and THR all above the supply voltage. That is outside of what is allowed for operation. In fact, the datasheet even says that's outside of the maximum (damage-free) regions. So, that's a design fault!
Instead, keep VCC at a constant voltage (e.g. 5V, or whatever between 4.7 and 18 V youhave at hand), and only change the voltage at the TR input.
(also, unless you're doing anything else with the same pulse, too: The job of a pulse generator is to make defined-width pulses. Not quite sure you really want your circuit if you have a pulse generator. Also, resistors and large capacitors are not exact at all and thermally stable; a (7)55 is really not an acceptable approach if you need precision in timing.) |
H: Can a 1S BMS be used for a parallel arrangement of 4 Li-ion batteries?
Currently I am on a Mini UPS for a modem router project. So my router needs a 12V and 0.6A current. I have four 3.7V, 2800mAh Li-ion batteries.
So I need to keep the voltage at 3.7V but I need to increase the total battery pack capacity for long periods of use.
So I connected all the batteries in parallel to achieve this.
2800 × 4 = 11200mAh and 3.7V
Finally, I used a DC step-up converter to transform 3.7V to 12V.
My question is: Can I use a 1S 3.7V charging BMS to charge all batteries that are connected in parallel? Could it cause any damage to the batteries?
Or is a 1S BMS only for a single cell?
AI: As far as LV cutoff is concerned. OK
But for CV cutoff to say 5% of CC with 4 cells sharing current, each cell must go to 1/4 of 5% CC to trip the CV cutoff. This extends the aging time during CV.
So if you can reduce CV from 4.2 to 4.0 that might be better as it will spend closer to the same time charging the higher ESR double layer charge as 1 cell.
Otherwise the CC rate will be shared and thus take 4 times longer from 3.8 to CV levels.
Consider the simple equivalent cct as C*ESR // C/x * ESR * y so the secondary charge time constant ought to be the same as for 1 cell to give an equal compromise to longevity vs storage capacity. Where x,y are variables of the double layer charge effect that causes the effective memory when you change the CV instantly then shortly after remove all charger or load and it restores back to nearly the same previous voltage.
In Short (no pun) it will work but I recommend you tweak the charging profile.. Max CC and reduce CV
The only other factor is does the BMS actually measure battery current or just charger current? If the Latter, beware of overextended CV times during load > I cutoff. |
H: Is it damaging to drain an Eaton HS Supercapacitor below its minimum working voltage?
I have a Eaton HS Supercapacitor that is rated at a maximum of 3.8V, but I noticed on the data sheet there is a "Minimum working voltage 2.2 V". Will using the capacitor to power a boost converter that will drain it below 2.2V be damaging to the cap?
https://www.mouser.com/datasheet/2/87/Eaton_supercapacitor-hybrid-cylindrical-cells-data-1847238.pdf
AI: Eaton HS model is not a regular supercapacitor, but it is a hybrid supercapacitor.
It is a hybrid of regular supercapacitor and lithium-ion cell.
So same restrictions apply due to the lithium-ion cell technogy - the lithium-ion part of the hybrid capacitor will get damaged when it is discharged below safe voltage. |
H: Gain of an amplifier
What will happen if an amplifier's gain is not stable? I can understand it may drive the amplifier into saturation, any other reason?
What if the gain is changing in such a way that the amplifier stays in active region, in that case will any distortion occur?
Likely not. But then what kind of problem may arise in the second case?
AI: I'll just try and answer the main thrust of your question, as I understand it. But first let me add that I believe you are asking about a gain that varies with the signal itself, as you mentioned "staying in active region" and "drive the amplifier into saturation." I also suspect you are talking about a single-stage case (or, at least, a grouping that can be treated similarly), but I'll try and broaden out the answer to include a small nod to a larger system. Finally, I think you are referring to the common case of voltage gain variation with signal.
A single amplifier stage almost always has some variation of voltage gain. Sometimes, the design goal for a single stage is to minimize that variation. But there are also times where the design goal is to maximize the voltage gain at almost any cost, because the designer also intends on using global negative feedback to perform two key purposes: establishing a precision overall voltage gain as well as correcting distortions in the signal caused by gain variations in individual stages.
The classic case of a well-designed amplifier stage where the voltage gain varies quite widely with the signal, and therefore highly distorts the signal -- but acceptably so when global negative feedback is applied across multiple stages in order to correct that distortion -- is this AC-grounded BJT amplifier stage with single-ended input and output:
simulate this circuit – Schematic created using CircuitLab
The voltage gain itself varies substantially with the signal because the emitter current varies significantly and \$r_e^{'}\$ itself varies inversely with that same emitter current. Even designed well, any significant, finite input signal will be noticeably distorted at the output.
However, that type of stage is still used because it also provides high voltage gain and it can be made to function well within a larger amplifier system if appropriate global NFB is included in the final amplifier design.
But please note that this type of amplifier should be only considered in cases where global NFB is intended or else where the distortion itself is acceptable for the purposes.
Even in a full amplifier system, there will be signal-dependent voltage gain variations. But these can always be reduced to an acceptable level, with attention to details. |
H: Is sum of currents equal to capacitor current for NMOS Inverter with Capacitor as Load?
I found this in my lecture notes and could not understand how drain current is equal to sum of load and (IL) capacitor currents (ICL) given in the figure for a NMOS Inverter with capacitor load. By looking at the direction of currents, I would assume load current would be equal to sum of drain and capacitor load currents.
I would appreciate if there is anyone who can make it clear for me.
AI: Use mesh current at the node between the load, the source of the fet and the terminal of C_L
\$I_L = I_D + I_{CL} \$
rearranging gets this equation:
\$I_{CL} = I_L - I_D \$
So it doesn't make sense that they didn't follow their own nomenclature with the arrows. |
H: Is a Δ-Y conversion a must?
Can the equivalent impedance be solved without Delta to Wye transformation?
AI: Mesh Analysis
Re-drawn, you can see that there are 5 mesh analysis loop currents:
simulate this circuit – Schematic created using CircuitLab
If you use mesh analysis then set \$V_1=1\:\text{V}\$ and solve for the unknown loop currents. The resistance is \$R_\text{TOTAL}=\frac{V_1=1\:\text{V}}{I_{\text{L}_1}}\$.
Nodal Analysis
You can see that there are 9 unknown voltage nodes for nodal analysis.
simulate this circuit
If you use nodal analysis then set \$I_1=1\:\text{A}\$ and solve for the unknown node voltages. The resistance is \$R_\text{TOTAL}=\frac{V_{\text{N}_1}}{I_1=1\:\text{A}}\$.
Combo Approach
It just crossed my mind that you could try a further simplification prior to analysis in order to reduce the number of simultaneous equations to solve.
If you look at the nodal analysis schematic above, you can see some simplifications:
Remove \$R_2\$ and \$R_6\$ (short them out.) These are "series resistances" that can be added back after additional analysis, since they are in series with the remaining circuit.
Apply a Norton to Thevenin conversion of \$I_1\$ in parallel with \$R_8\$.
You now have the following simplified schematic that can be solved using mesh analysis with 4 loops instead of 5.
simulate this circuit
Here, you'd compute \$R_\text{MESH}=\frac{V_\text{TH}=1.2\:\text{kV}}{I_{\text{L}_1}}\$. Once you solve that, you can then add back the values of series resistors, \$R_2\$ and \$R_6\$, and that should be the same as the computed results from the earlier two examples, as well. In short, \$R_\text{TOTAL}=R_\text{MESH}+R_2+R_6\$. |
H: Driving a 5 V logic input from a 3.3 V output
I have a device which requires a 5 V logic input. That input ordinarily needs to be high and the device is activated when the input goes low. I need to drive this from a 3.3 V output (Raspberry Pi GPIO) which is low when the Raspberry Pi is booting.
In summary: when the RasPi's 3.3 V pin is low, the 5 V input needs to be high and vice versa.
What is the best way to achieve this? I'm thinking of using a PNP transistor but I'm struggling to understand how to drive this, as the 3.3 V input isn't enough to stop the transistor passing current.
I've seen a few example circuits that pair the PNP with an NPN but these all require the input to the NPN to be high before the PNP passes current.
Is a Logic Level Converter a more sensible way to achieve this?
AI: You need an inverter.
If you go shopping, you can find a logic family that will work correctly with a 3.3V input and output 0-5V. 74HCTxx an 74ACTxx families do this, for instance. If you're doing surface-mount, you can get a one-gate inverter that'll do it.
You can also use an NPN transistor and a few resistors. This will be slower, and may not meet the input slew rate specifications for the following stage - but it'll probably work.
simulate this circuit – Schematic created using CircuitLab |
H: Effects of low voltage on power grids?
I understand that if load is suddenly ramped up on a power grid:
A sudden increase in current is caused by adding these parallel loads to the circuit.
The current increase thus increases the torque required from spinning generation in order to maintain the speed required for its designed voltage and frequency output. For example a generator designed to output 32 kV at 3600 RPM will see a voltage drop if the speed (and thus Hz) drop.
Since the generator cannot immediately increase its torque there is a brief slow down, which in turn causes a frequency drop and thus a voltage drop.
My question is what some of the dangers of this drop are for the grid? How can this lead to a cascading problem (a blackout)?
AI: My question is what some of the dangers of this drop are for the grid? How can this lead to a cascading problem (a blackout)?
Under voltage will cause induction motor load to start drawing excessive reactive (var) from the system. Further exacerbating the under voltage condition and possibly leading to voltage collapse.
Capacitor banks used for voltage support drop off per \$Q=\frac{V^2}{X_C}\$ so a 10% drop in voltage means the cap bank will put out 19% less reactive var support. Here is good overview by Carson Taylor on how this affects the "nose curve" used in voltage stability analysis.
Tripping of elements during a stressed condition (e.g. generators tripping or lines tripping) overloads remaining lines and can lead to further tripping. NERC PRC-23 (for transmission line protection) and NERC PRC-025 (for generators) now require relays to be much more resistant to tripping on load as compared to pre-2003 (in North America). Here is a good read on the specific topic of distance relays (introduction is good short read). |
H: Safe to use series resistors for powering common anode RGB LED from single constant current source?
I have a 3-9W common anode RGB LED (https://cdn-shop.adafruit.com/product-files/2524/FD-9RGB-Y2.pdf) and want to vary each leg's voltage with PWM through FETs, namely IRLZ44Ns, and an Arduino, in a similar config to this: https://jasonwebb.io/wp-content/uploads/2010/12/schematic.png.
I am hoping to use a single current controlled source (https://www.ledsales.com.au/index.php?main_page=product_info&cPath=200_248&products_id=1508) and run each coloured element of the LED at 700mA by impedance matching each leg but am worried that the 2.1A from the source will just go through the path of least resistance when the source first powers on, and burn out the red LED. I was planning to limit the source to 5V (each element runs at below 4V) and calculated values of 2-5 ohms for each series resistor based on a 5V supply and the LED's different forward voltages.
I've been scouring Arduino and SE posts to find a solution but have come up with conflicting opinions as to the behaviour of the CC source, and also saw that current limiters on the output legs, like LM317s, might interfere with the high speed switching I need from PWM.
So I wanted to confirm if I am safe using series resistors in this configuration or if I should just use a 6-pin RGB LED and multiple CC sources instead. Thank you.
Edit: Added circuit diagram and my own measurements for the LED's forward voltage and current, as the datasheet is incorrect.
Sample resistor calc for red LED at 700mA: \$ \frac{5-2.36} {0.7} = 3.77\Omega\$
AI: A constant current source is a voltage source with a feedback loop that regulates current. The purpose is to avoid the current limiting resistors that waste energy and/or provide more precise control of brightness without needing PWM.
You've designed a circuit that adds the PWM and current limiting resistors back in, in which case using the constant current source is unnecessary. Either use a constant voltage source, or get a constant current source with a PWM input to control brightness. |
H: How To Save A Matrix In Flash Memory In STM32
i'm new in stm32 and in embedded world in general. I'm using a nucleo64 f446re and I want to save a matrix in the flash memory.
Can I use CONST to do this?
AI: Yes, declaring your array as const in C language will leave the data in program flash memory area and access it there on STM32 MCUs. |
H: Is Millman's Theorem approach here correct?
The question is as follows:
My answer is as follows:
However, per the source the answer is:
AI: Well, if it's of any help, I also get the same numbers as you. I calculated \$V_L\$ to be 4.7646 volts and I got a current magnitude of 1.0654 amps. I didn't bother to calculate the phase angles.
Is Millman's Theorem approach here correct?
Yes it is and I expect that the "formal" answer given has got some rounding errors. They also appear to be calculating \$V_L\$ to be exactly 5 volts and that is a mistake. I'd consider changing your text books if I were you because that's two questions you have delivered where the formal answer is either wrong or dubious. |
H: What is this thermal adhesive? (heat transfer compound)
Well generally I I encounter this thermal adhesive. for example in inverter (brand: allen bradley). But it is different from I've seen before. It is very solid and generally using at very strange places, such as between 2 capacitors or at leads of a mosfet or top of capacitors block. Also it is very hard the repair a circuit, if that glue was used. Actually I cant find this stuff at store or web and I didnt understand why people use this?
this mine used. It is very liqued.
AI: Looks allot like a RTV silicone, such as DC744
This is for mechanical support. (In theory at least - not sure if the sloppy application here does any good) |
H: Inrush current in the Boost Converter during start
I am making a 400V 1kW boost converter but in the LT-SPICE simulation, it is drawing a huge current of 50-60A at the start for 1ms-3ms, but the current comes down to 12A after that.
The inductor current rating is 20A and I will be making PCB trace for 25-30A rating. I am afraid that the large current at the start might damage the costly components and PCB trace.
Please suggest me how to solve the problem and what do people do In practical boost converters?
AI: This problem is unrelated to the boost-control mechanism/circuit but can be made worse by it if the boost control circuit is activated before the output capacitors are charged to the input supply DC voltage. In other words, it's a regular inrush problem suffered by most circuits that seek to charge high value electrolytic capacitors from a high(ish) supply voltage.
Please suggest me how to solve the problem and what do people do In
practical boost converters?
The problem that you need to overcome is the initial inrush current and this is partially alleviated by R3 being 3 Ω: -
Ignoring the slight reducing-effect that the inductors will have, the inrush current is 200 volts divided by 3 Ω = 66 amps. OK, you are seeing 50 to 60 amps and this is due to the inductors being a reasonable blocking impedance on power up.
If you want to avoid this initial surge then using an NTC thermistor can be a good choice. It has a fairly high initial (cold) resistance (several tens of Ω) dropping to sub Ω values within a few milliseconds as it warms over that short period in time.
Another method is to pre-charge the capacitors to the 200 volt supply voltage prior to switching in the main power circuit. Once the capacitors are charged, you have full control of currents via the boost mechanism. |
H: ADS1115 ADC input filter - active or passive?
I want to implement an ADC as part of my bachelor's thesis.
The datasheet of the ADS1115 show that there is no filtering done by the ADC chip before the multiplexer. As I read here, it is good practice to use a filter before the input.
I am currently trying to decide on what kind of filtering would be best for the ADS1115 inputs.
I read online from some people that passive lowpass filtering should do just fine.
I remember my professor stating in a lecture that active filtering in general is simply better than passive filtering.
In any case I would appreciate any input.
AI: Summary:
A band pass of 300Hz to 1MHz won't do you any good - the ADS1115 can only sample at maximum 860 samples per second.
You cannot capture a signal above 400 Hz with the ADS1115.
TI recommends a simple RC low pass filter to reduce aliasing.
An RC low pass is adequate because the ADS1115 samples at a much higher rate and decimates and filters down to the set output sampling rate.
Details:
As always, start with the datasheet
The ADS1115 will be of no use for a signal between 300 Hz and 1MHz. It has a maximum data rate of 860 samples per second - that's just about adequate for signals up to between 300 and 400 Hz. Above that you will get aliasing and a much reduced signal level. In other words, you can sample signals up to about 400Hz with the ADS1115.
All you need is a low pass.
On page 33, you will find this recommendation:
A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally,any signal beyond fMOD/ 2 is attenuated to a level below the noise floor of the ADC. The digital filter of the ADS111x attenuate signals to a certain degree,as shown in Figure21. In addition,noise components are usually smaller in magnitude than the actual sensor signal. Therefore, use a first-order RC filter with a cutoff frequency set at the output data rate or 10x higher as a generally good starting point for a system design.
fMod is the modulation frequency of the delta-sigma converter in the chip. It is the effective sampling rate that the signal "sees." In the ADS1115, fMod is 250kHz. To avoid aliasing, you need to reduce signal content above 125kHz.
The ADS1115 has digital filtering to remove stuff between the final (output) sampling rate and fMod/2.
An effective filter starts at your selected sampling rate. If you are sampling at 860 samples per second, the you need an RC low pass with a cut off of 860 Hz. For example, 1.6k and 100nF provides a cutoff of 884Hz and an attenuation of about 45dB at 125kHz. |
H: How to make a 500-1000ms timer circuit
There are countless applications for delays of a few hundred milliseconds up to a few seconds. I have not been able to find some elegant solution, but I am sure that there must be a way, and that some of the expertise in here has a neat little circuit that is much better than whatever I can come up with.
And before I get the obvious answer: A 555 with a 1000uF cap is a fun breadboard experiment, but the huge electrolytic capacitor is absolutely impractical on any "real" miniaturized PCB's. Surely there must be a more practical/professional way.
I find it really strange that the big IC manufacturers doesn't have a simple sot-23 delay timer. Components such as TLP5010 is real close, but not quite bullseye. It can be coerced into a functional circuit with some additional components, but it still feels like a square wheel. So without any off-the-shelf options: Please share your favorite timer circuit.
AI: find it really strange that the big IC manufacturers doesn't have a...
But they do! Analogue Devices TimerBlox. There's a lot of them and they can do many things, but in a nutshell, they'll do 1 us to 39 days. Better than a 555.
Simple application from one of the data sheets:-
'programmed' like so:- |
H: 555 timer Theremin - capacitor choice, and question about mixing signals
I'm trying to create 555-timer based Theremin, but I have a few questions that I don't quite understand. For now, I'm building it on a breadboard (yes, I know it's not the best option), but I don't want to commit yet to some schematic that might be wrong. My current idea is to use 555 timer in 150 kHz range.
For this, I have 50 pF C, R1 of 1 kOhm and R2 of 100 kOhm (following this convention).
Checking with an oscilloscope I get around 100 kHz. But when I connect a wire (antenna) to pin6 I don't get any change in frequency. My idea was that connecting an antenna to pin6 would create a capacitor in parallel with 50 pF, and that my hand should then vary that capacitance, thus varying frequency. But the only change in frequency occurs if I touch the bare wire, not by proximity.
Am I doing something conceptually wrong, or is my 50 pF capacitance too large (I'm guessing "antenna" capacitance is probably less than 5 pF?)
Oscillator difference
My other question is concerned with mixing of two signals for Theremin (one from fixed oscillator, one from variable oscillator - the one connected to antenna). I've seen schematics where op-amp is used to subtract signals, but I'm not sure how relative phase of the signals affects the output of the op-amp? Surely this all works only if they are in phase? How is this problem solved in other signal mixers?
AI: Theremins are based on LC oscillators, using the self capacitance of the external L (antenna) which obviously varies with hand position.
So, an RC oscillator (555) is a poor choice.
(So is using a crystal oscillator for the reference, as I found. Both oscillators should be similar, so that their thermal drifts are similar. Mine drifted like crazy because the reference was too stable! Yes, I walked right into that one.)
And as commented, mixing is at RF, producing a beat frequency which is low pass filtered to produce the audio.
You want both oscillator waveforms to be reasonably close to sinusoidal; mixing square or sawtooth waveforms from an RC oscillator - or using an XOR gate as a mixer - will produce something decidedly nasty sounding.
The classic Theremin sound relied on the much softer sound (fewer odd harmonics) of vacuum tube "detector" circuits like the "anode bend" using the non-linear portion of a tube's characteristic. You can do something similar with a diode mixer, or a transistor or FET biased just out of cutoff (not enough collector current for symmetrical operation : turn the base bias voltage down until it sounds right) |
H: Playing a sound when turning off a circuit
For my project, I am looking to have this (mock-up) circuit play a sound, e.g. the Windows XP shutdown sound, the moment it is powered off.
I have looked at capacitors, relays, opto-couplers, and a bunch of tutorials but they all only can delay the moment the circuit is powered off or act as a timer as to how long the circuit will run, which is not what I want and I can't find anything about this anywhere.
Am I missing something fundamental or is this just not possible?
simulate this circuit – Schematic created using CircuitLab
(Intentionally left out the speaker and potentially needed SD card module)
AI: Set up a button that is sensed by your microcontroller. This triggers the sound then programmatically turns the power off to the system. Options to turn power off are: have the microcontroller go to sleep, turn your buck regulator off, a high side switch, or a relay. You'll need no supercapacitor or secondary power supply. |
H: Amplifier noise output against source resistance
I’m doing an experiment measuring the noise output of a two stage amplifier with different source resistances.
I’ve found results for a range of resistances. I have plotted these results noise output in dB against source resistance on a log-linear graph (resistance plotted logarithmically.) I get an S shape.
I’m struggling to fully explain this shape. With the noise model I have the noise would continue increasing at higher resistances.
Why does it start to flatten out? The amplifier is nowhere near saturation.
AI: with the noise model I have the noise would continue increasing at higher resistances , why does it start to flatten out?
The problem is that you are assuming your 2 stage amplifier has infinite input impedance. It clearly doesn't and therefore the finite input impedance value will limit the maximum thermal noise. Making your source resistance even bigger is not going to change this because, in effect, that source resistance is in parallel with the amplifier's input impedance. You'll reach a point where increasing the source resistance does not affect the noise and that is what you see. |
H: CMOS inverter: circular reasoning to understand it?
I am confused by a litte detail with CMOS inverter. Note that I am really a beginner in CMOS "theory". Here is the electrical circuit:
At "first view", I understand the principle. If \$V_{in}\$ is high (\$V_{in}=V_{DD}\$), then the PMOS will be open and the NMOS closed. Thus \$V_{out}=0\$.
Reciprocally, \$V_{in}=0\$ implies the PMOS closed and NMOS closed thus \$V_{out}=V_{DD}\$
My question
I have trouble when I look at the details. Let us consider \$V_{in}\$ high for instance. A PMOS will be closed for \$V_{GS} < V_{Tp}<0\$ (threshold voltage), and \$V_{GS} > V_{Tn}>0\$ for NMOS.
But for this I must identify where are source and drain. To identify where is the source and the drain of a transistor, I must find which one has the highest voltage.
But as I do not know \$V_{out}\$ how can I find them ? \$V_{out}\$ is what I try to find so I am not supposed to know it (else the reasoning is circular)...
Is there an implicit assumption that "by design", for CMOS circuit, any voltage in the circuit will verify \$0 < V < V_{DD}\$. Applying this to \$V_{out}\$ I can deduce source and drain for both transistors and solve my issue ?
Because "in principle", I could imagine some negative voltages and because of that identifying what is source and drain is not straightforward here.
AI: To identify where is the source and the drain of a transistor, I must find which one has the highest voltage.
But as I do not know \$V_{out}\$ how can I find them ? \$V_{out}\$ is what I try to find so I am not supposed to know it?
You know that the output voltage will never be greater than \$V_{DD}\$ or less than \$V_{SS}\$.
Therefore, for the PMOS device on the high side, the source is always the terminal connected to \$V_{DD}\$ and for the NMOS device on the low side, the source is the terminal connected to \$V_{SS}\$.
As others have pointed out in comments, if you're building this from three-terminal discrete MOSFETs you must properly connect the terminals designated by the manufacturer as the source and drain correctly or the body diode will conduct, and the FET will not be able to block current. If you're building the device within an IC, then you'll be able to connect the bulk terminal to the correct voltage rail, and the device will behave symmetrically, provided you don't try to drive either source or drain terminal beyond the rails. |
H: LTSpice transient simulation of LC circuit
I've a question about the LTSpice simulation of the following simple LC circuit driven by a DC current source.
The first simulation (A) looks good from point of view of initial conditions for either voltage cap V(n001)=0 and inductor current I(L1)=0. As shown in the first picture the Initial Transient Solution (ITS) for the inductor current looks ok.
Consider now the second simulation (B) in which the initial condition has been set just for the inductor current I(L1)=0. This time, as shown in the second picture, that condition seems to be not honored (the initial inductor current results in 10A)
Can you help me in understanding the reason behind it ? Thanks
Edit: based on comments I've done another simulation (C) without any initial condition. As you can see the solver is able to work out the Initial Transient Solution (ITS) different from the previous two (A & B).
Can you point me to some book (or documentation) about how Spice works under the hood ? Thanks
AI: It does the same in micro-cap. Basically, with any simulator, it tries to ascertain the steady-state initial conditions and, in certain circumstances, it needs to be explicitly told what those initial conditions are. This is one of those circumstances; a current source feeding a capacitor.
The simulator tries to determine the steady state conditions then, once evaluated, it will produce a transient response. But, what are those steady state conditions you might ask. For a simulator, it makes use of the leakage resistance it applies to every circuit node and the default value for micro-cap appears to be 200 MΩ. I get a peak voltage of 2 GV and 2 GV/ 10 amps = 200 MΩ.
In some circumstances (such as these) you need to "force the hand of the simulator" so that the initial conditions are defined as in .ic V(1) = 0. |
H: Unknown symbol - sort of distant switch
I have some technical drawings and I am looking for the name of a pair of components (or maybe two disctinct components) whose symbols I cannot identify. I understand one is a type of switch controlled by the other component which is connected to a NI-6008 USB card. The two are drawn separately but I do not know if they are linked in reality, simply avoiding additional wires on the schematic.
What are the following symbols?
AI: Try this: -
There are many variations on this general theme that you should you google: -
Picture from here.
Picture from here |
H: What is the purpose of transistors in the feedback of this OP-AMP?
What is the purpose of the transistors in the feedback arrangement of this OP-AMP?
I am mostly interested in the purpose and general use of this kind of "trick", and perhaps also what it does in the circuit where I saw it.
The circuit occurs in a bass-boosting audio circuit "DBX 100" of which the schematics are found here:
https://elektrotanya.com/dbx_100-boom-box_main_schematics.pdf/download.html
There's a similar arrangement discussed here, Op amp with transistor in feedback, but I'd like to better understand the specific role of the transistor.
Maybe hysteresis? Diode in positive feedback?
AI: I spoke too soon. It is a schematic reverse engineering error. This cct will saturate with open loop gain and positive feedback.
But as a soft limiter followed another soft limiter with an active LPF, it converts it into a limited soft fuzzy bass. |
H: Don't understand the current direction in a flyback diode circuit
I'm aware of that, in a circuit, inductive loads need to be protected with a flyback diode because if the circuit gets open the magnetic field will collapse forcing a current flow in the opposite direction.
What I don't understand is that last part: opposite direction, let me explain:
Let's take the following flyback diode example at normal operation (circuit closed):
Suppose now that the circuit opens. My understanding of what a current in the opposite direction should be is the blue line, and the actual current flow that must happen (otherwise the flyback diode needs to be inverted) is shown in red:
So, why is the actual current flow (red) described as in the opposite direction while it is going in the same direction as before?
AI: The loudspeaker is an inductor; so you have to create a good notion about its behavior. Here is a simple explanation.
Both capacitors and inductors are accumulating elements. They accumulate energy; so they can be considered as sources... rechargeable sources.
The capacitor can be thought of as a voltage source containing potential energy (as a tensioned spring). So, when discharges, it retains its polarity and passes a current in an opposite direction (the spring returns).
The inductor can be thought of as a current source containing kinetic energy (like an inert moving object). So, when it discharges (step 4 in Fig. 2 below), it reverses its polarity and passes a current in the same direction (the object continues moving in the same direction).
You can investigate the inductor behavior by this attractive Flash movie. This is an exe file with embedded Flash player (it is absolutely safe since it is uploaded on my site of circuit-fantasia.com); so play and have fun. Here are two typical steps:
Fig. 1. The inductor is charging
Fig. 2. The inductor is discharging
Also, you can find an explanation of this clever circuit trick in another answer. |
H: How to select a CC replacement led driver?
I have a led ramp in my bathroom. It's dead. The led driver isn't providing any volts on it's output side.
The previous driver was an EBIR AED06-700IIP44 but I can't find a new one.
It's a constant current 700mA IP44 led driver that supply up to 13V and 6W.
I'm not at ease with cc stuff and I can't find another brand with the same characteristics.
==> Except for the mandatory "700mA cc", what should I focus on ? 6W ? 13V max ? both ? or it doesn't matter ?
At amazon I found a Goobay 30602 LED driver cc 700 mA/Class II/17V max/12 W Max.
Could it be a good replacement part ?
AI: You need an led driver that can provide 700mA at 13V.
Constant current drivers typically have a voltage range in which they can provide the specified current (often refered to as "constant current region"). That's like with a CV power supply, which has a specific current range in which it can provide the nominal voltage. While the rated current for a CV psu typically starts a 0A, led drivers often operate only above a minimum output voltage. If you don't want to dim(-to-off) the leds, it is only important to have a driver with the rated current and a max operating voltage above the leds' voltage rating.
If you want to dim the leds to off, additionally the driver's minimum output voltage has to be below the leds' threshold voltage.
The Goobay 30602 LED driver you propse appears to work at a minimum power of 0.5W while providing no more than 700mA, so this driver should be suitable for your leds. |
H: What's the difference between using 3.7v and 9v as phantom for electret mic?
I'd like to pass from a mic/filter/amp circuit with the LM386 and powered by a 9v battery in single supply to a 3.7v equivalent using the PAM8403. In hi-fi audio the phantom DC is 48v. Is there any downside in using a voltage as low as 3.7?
AI: The electret phantom power only drives the Idss of a JFET with a crystal ceramic mic. such that the gain and DC rise with the pullup resistor. So it is ~ 1mA. The expected max input of the PAM8403 on 5V at max gain of 24dB (~21) supply is +/-0.5V which you could get by shouting into it. So it is not the "Line Levels" expected from PAM8403 and needs a 10x gain AC coupled.
Pro Audio Phantom power is another beast with moving-coil and amplifier for high quality. But some run on 3V and 1mA like Sony.
Take these mics, which all use 48 volts. A Sennheiser MKH800 draws 3.0 mA, a Neumann U87 draws .8 mA, while a Shure KSM 32 draws 4.6 mA and all Earthworks models draw 10 mA. |
H: DIY Bluetooth speaker - Some power related questions
I'm new to electronics and I'm making a DIY Bluetooth speaker. The problem I have is with powering the circuit. I plan to use 2 18650 2200mAh 3.7V lithium-ion batteries in series and use an XL6009 step-up converter to boost the 8.4 volts to 12V needed by the TDA7266 Amplifier Board. Also, I'll be using an LM2596 step-down converter for the 5V needed to power the VHM-314 Bluetooth Audio Receiver Board. To charge the 2 18650's, I'm using the HX-2S-A2 BMS module and TP5100 Lithium Battery Charger.
1: Am I doing it right?
2: What kind of adaptor should I use to charge the batteries?
3: Can I use an MDY-03-AF Xiaomi Adaptor to power the circuit and charge the batteries?
4: Do I need any type of Relay in this circuit?
5: How can I automatically stop using the batteries when the adaptor is connected?
And here we have my crappy schematics (Sorry!):
Information for the MDY-03-AF Adaptor:
Model : MDY-03-AF
Quick Charger 2.0
Output : DC5V-2A / 9V-1.2A / 12V-1A
Input : AC 100-240V, 50/60Hz, 0.5A
AI: 1: Not entirely by the looks of it
2: 12V 2A adapter typically, but do check the manual of the specific TP5100 module you have, as there must be many different ones made and sold.
3: No, for many reasons. First is that you get only standard 5V out unless you make something that fakes to be a quickcharge module to get 12V out. Even if you manage to do that, it can only output 1A at 12V and it can't give 2A to the charger.
4: Not sure what would you plan to use the relay for.
5: Add some circuitry to change the components to be supplied from charging port, but then the power supply must provide charging current plus the component operating current. |
H: Implement boolean function as multiplexer
Implement and as a multiplexer:
How is that working? When I repeat from before:
Y | out
0 | 0
1 | X
So, this means, when Y = 1, then the output = X
I'm not sure how to understand this. So far, I'm only used to things like "if X=1 and Y=1, then out=1".
My issue is probably somehow connected to the output. I'm only familiar with truth tables like this:
but in this case here, I can only switch between 0 and X. I also found:
AI: First let's see how a multiplexor works. In your case you have a 2-1 (or 2 to 1) multiplexor.
So looking at your diagram, the multiplexor has the following:
2 data inputs: 0 and 1 (0 has a 0 connected and 1 has the value of X connected)
1 control input: Y
1 output: X and Y
So when Y is a logic level 0, the value on the input 0 (a logic level 0 in this case) is seen on the output.
And when Y is a logic level 1, the value on the input 1 (a logic level X in this case) is seen on the output.
If you think about it, when Y is a logic level 0, a logic level 0 is always on the output as a logic level 0 is hardwired to this input. So this equates X and Y.
Now when Y is a logic level 1, the output will be whatever logic level X is at.
You should see that whatever logic level Y is, the multiplexor output always equals the boolean value of X and Y.
EDIT
With 2 to 1 multiplexors like you have in your question, the control input (Y in your case) can be two logic levels, a 0 or a 1. What the two inputs labelled 0 and 1 on the multiplexor mean, is that when Y = 0, the output will equal the logic level connected to 0, and when Y = 1, the output will equal the logic level connected to input 1.
Think of a multiplexor working like the switch in the image below:
When Sel = 0, the output will equal the logic level of I0 and when Sel = 1, the output will equal the logic level of I1
Hope this helps! |
H: If I have a signal that switches between 5MHz and 4MHz faster than the sample rate of the ADC on a spectrum analyzer
Basically, what happens if your signal is switching between frequencies faster than the sample rate of the ADC in the spectrum analyzer? I have been curious as to what would happen in this case, would aliasing from sampling occur?
From what I understand about spectrum analyzers is that they use RF mixer magic and a band pass filter to bring an extremely high frequency signal into a frequency range that can be sampled by a relatively “cheap” and “slow” ADC. From what I understand, I don’t think that magic works to also bring down the switching rate of a signal switching between two frequencies.
A follow up question would be if the amplitude of a 5MHz signal is changing from lets say 10dB to 50dB every 10ns, would an ADC on a spectrum analyzer that samples every 25ns be able to capture the event without aliasing?
From what I understand about sampling is that aliasing would occur and you need a faster ADC (probably a time interleaved ADC) in your spectrum analyzer to capture the event where a signal is switching frequencies or amplitudes faster than the sample rate of the ADC.
If it is possible can you explain how it works?
AI: If the signal is changing faster than the bandwidth of the bandpass filter, then the following circuitry won't see the effect as the signal changing -- they'll see the effect in the frequency domain.
For instance, if the signal is changing between 5MHz and 4MHz, randomly every 500ns, but staying phase coherent (meaning that there's no time-domain jump discontinuities in the signal), then the signal is MSK modulated, and when you look at it with a spectrum analyzer that's set up correctly, you'll see a classic MSK spectrum like this one from Wikimedia Commons.
In this case "properly set up" would mean that you want an IF bandwidth that is much less than the modulation rate (i.e., less than 200kHz), and a sweep rate that's low enough that the filter bandwidth doesn't distort the signal (although you don't have to worry about that anymore -- a spectrum analyzer with a computer in it won't let you make that mistake).
In the case of your signal at 5MHz that's being "switched between 10dB and 50dB every 20ns", you reformulate that statement to say that the signal is being chopped at 25MHz. In that case what a properly set up spectrum analyzer would show you peaks at 5MHz, 20MHz, 30MHz, then 70MHz & 80MHz, then 120MHz & 130MHz, repeating every 50MHz. -- basically you'd see peaks at \$(25\mathrm{MHz})(2n - 1) \pm 5\mathrm{MHz}\$ for all \$n \in \mathbb{I}\$.
Google "frequency mixing", "mixer" or "heterodyning" for more details. The hand-wavy answer is that when you multiply two sine waves together in the time domain, in the frequency domain you get signals at the sum and difference of their frequencies -- so a 5MHz sine wave multiplied by 25MHz gives you tones at 20MHz and 30MHz. A 25MHz square wave can be decomposed into sine waves at 25MHz, 75MHz, 125MHz, etc. -- so you get this sine wave multiplication effect at all of those frequencies.
A more comprehensive answer has to do with the properties of the Fourier transform (a spectrum analyzer is basically an analog computer dedicated to finding the Fourier transform of its input -- sorta kinda). I can't really go into that here, but if you're interested in this stuff you probably want to pick up a book on signal processing and start studying. |
H: How is this capacitor connected between the inverting input and ground being used?
I found a schematic for a lithium polymer battery charging circuit where an op amp is used as a comparator. The battery voltage (adjusted by a pot on the left) is compared with a 3V reference provided by a zener diode. Can anyone tell why the 1 uF capacitor was included between the inverting input of the op amp and ground? Here's the schematic:
from https://www.homemade-circuits.com/usb-automatic-li-ion-battery-charger/
AI: It is just stabilizing the voltage on the output of the voltage divider formed by the potentiometer. |
H: Loud hum emitting from output stage of Raspberry Pi guitar pedal
I've been trying to implement the electrosmash Pedal Pi project using a Raspberry Pi 4 Model B, breadboards, and parts purchased from DigiKey.
For reference, here is the overall schematic of the build:
So far, I've built the input stage, and the power supply stage which seem to work fine. My struggle currently is with the output stage. When I plug in the output jack into my amplifier, there is an incredibly loud hum emitting.
Here is what I have tried:
I disconnected PWM0 and PWM 1 from the raspberry pi. When I do that, there is still a loud noise, which leads me to believe that the noise isn't coming from the PWM pins.
I have plugged in my 1/4 inch jack into my amp and disconnected the other end. The amp did not create any hum at this point which leads me to believe that the issue is not with the amp.
I have tried changing out the op amp for a spare one I have, and the humming persists.
I have tried changing the C6 capacitor to an arbitrarily higher capacitor (I believe 0.1uF) and that did not change the humming.
I'm not quite sure how to debug this, and it's been quite a roadblock since I can't distinguish the output from the PWM pins through all the noise.
Further details:
The parts I am using for the circuit are:
R6, R9, R10: RES 4.7K OHM 1/4W 1% AXIAL (DigiKey Link)
C6, C7, C8: CAP CER 6800PF 50V X7R RADIAL (DigiKey Link)
R7: RES 300K OHM 1/4W 1% AXIAL (DigiKey Link)
MCP6002: MCP6002-E/P-ND (DigiKey Link)
C9: CAP ALUM 4.7UF 20% 25V RADIAL (DigiKey Link)
My breadboard layout for the output stage looks like:
where the output jack is on a separate PCB, following the schematic.
AI: I had made an incorrect assumption about the pins of the Jack (referenced here: https://www.digikey.ca/en/products/detail/switchcraft-inc/SN37A14B/1288988). I had assumed the pin orientation was parallel, assuming the furthermost pin from the base would be the "tip" or positive, and that all subsequent pins would be "ground". However, that proved to not be the case. After resurrecting my issue, the loud "hum" subsided. Thank you all for your kind suggestions! There is still a slight amount of noise remaining, which I am sure will be fixed by your suggestions. But the bulk of my issues have been fixed. Thank you! |
H: Can we make a transformerless 220V to 12V converter without a Zener doide?
I saw many circuits have a Zener diode, but a guy from Youtube lighted up a 12V LED without a 12V Zener diode in the cicuit.
How is that?
AI: You don't have to have a Zener diode in the circuit if you are powering LEDs.
A transformerless AC power supply without the Zener diode is a sort of really lame constant current source.
LEDs do best when powered from a constant current source.
You can approximate a constant current source by using a resistor in series with a voltage source. The typical "DC voltage source and series resistor" circuit for driving LEDs is a sort of half-assed constant current source.
In your example circuit, C1 limits the current. At 50Hz, it has an impedance of about 32 kilo ohms. For 230VAC, that means a peak current of about 20 milliamperes. No matter what, you can't draw more than about 20 milliamperes out of that circuit continuously.
If your LED can handle 20 milliamperes, then the voltage output of the circuit will drop to the forward voltage of the LED. You don't have to regulate the voltage. The current limit and the LED will take care of that.
The Zener diode turns the current source in a transformerless powersupply into a (near) constant voltage source.
Normally, you'd want that. Microprocessors and other devices require a constant voltage, not a constant current.
Here is the circuit I traced out of a broken 230VAC LED light bulb:
It uses a transformerless power supply with no voltage regulation. It depends on the input voltage being well regulated in order to provide a constant current to the LEDs. It has no Zener to regulate the voltage. The LEDs and the (near) constant current do that.
The AC power is mostly well behaved, but not always. It gets spikes and noise and over voltage.
This circuit has next to no protection against over voltage, which is why it was broken.
At some point, it got a little too much voltage and allowed a little too much current to the LEDs. That destroyed one LED, causing me to replace the bulb and have a look at the circuit.
As noted in the comments, you should avoid transformerless power supplies.
They are dangerous, and can potentially kill you if you touch any point inside of them - even the supposedly low voltage output.
If you build one, it should only be operated enclosed in an insulated housing. It should not have any connections to anything outside the box except for the AC in.
All points in the circuit must be regarded as being at line voltage at all times. |
H: Voltage and Current Stability in a Voltage Divider
simulate this circuit – Schematic created using CircuitLab
The voltage divider is used in many circuits such as biasing the base of a transistor, etc.
Why is the voltage in the circuit on the left considered more stable than in the circuit on the right, if the voltage and current in the load is the same in both circuits?
EDIT: I have edited the circuit to clarify
My question refers to ..., if the load consumption changes, its resistance will change
So why is the voltage on the load more stable with a voltage divider than without a voltage divider?
Thank you
AI: The load voltage is dependant of the "bottom" resistor in the voltage divider, thus it will be dependant on the parallel between the load equivalent resistor and R2 in left circuit, and the load equivalent resistor alone in the right one.
That said, if the load resistor changes also the load voltage will change, and this is a pretty undesiderable thing in a voltage reference. Paralleling the (probably high) resistor of the load to a (much smaller) resistor will make the load voltage more stable because the high load resistor contribution in the parallel resistor computation is more and more negligible as the load resistor get higher and R2 gets lower.
Anyway, this circuit is not the best for voltage stability. I would rather use the circuit proposed by Transistor in the post above. |
H: Should RF output of (30+j10) Ohms be matched to 50Ohms for antenna matching network?
I'm designing a matching network for a 2.4GHz inverted F antenna. I am using an ESP32-D0WDQ6 MCU, and reading from the datasheet, the output impedance for the RF pins is (30+j10) Ohms. (DATASHEET in section 2.5 on page 7)
Should the matching network be set to 50 Ohms? Or should it be set at (30+j10) Ohms?
EDIT: anyone reading this should read the further comments with Andy AKA's answer for completeness.
AI: If your antenna is 50 Ω and your source is 30 Ω + j10 Ω then, add a series capacitor of -j10 Ω to cancel out the +j10 Ω effect of the inductor.
This now means you are trying to match 30 Ω resistive to an antenna of 50 Ω resistive.
Then use an L-pad calculator like this: -
You can double check the formula derivation on that site.
Series inductance needs to be about 1.6 nH
Parallel capacitance needs to be about 1.1 pF
Then, if you went back to the start of the problem and analysed what value of inductance is needed to produce the j10 Ω in your driver output impedance, you'd calculate it to be 0.663 nH at 2.4 GHz.
This means that you can actually dispense with the added series capacitor of -j10 Ω (as originally proposed) because you need 1.624 nH from the above calculator. The upshot of this is that 1.624 nH might as well be 1.663 nH so, the external series inductor you need to add is 1 nH. |
H: Send Data With Usart STM32
I have to send data using the usart2 in my nucleo64 stm32f446re board.
The type of data I have to send is float but until now I always send uint8_t using this code;
char msg[1];
for(int i = 0 ; i < Nbit*Sb ; i++)
{
sprintf(msg, "%d ", sigTX[i]);
HAL_UART_Transmit(&huart2, (uint8_t *)msg, strlen(msg), HAL_MAX_DELAY);
}
Because sigTX is a pointer to float data in an array, I try to change the code using msg[4], in order to have 32 bit, and in HAL_UART_transmit I put (int32 *)msg, in order to send data with sign.
This doesn't work, so can someone say to me where is the mistake?
Sorry, but I'm new in embedded world.
AI: While the other answers focus on sending one float at a time, and you want to send the whole array of floats anyway, it can be sent with a single call.
Assuming sigTX is a pointer, and you want to send Nbit*Sb amount of floats:
HAL_UART_Transmit(&huart2, (uint8_t *)sigTX, sizeof(float)*Nbit*Sb, HAL_MAX_DELAY); |
H: Can a short circuit kill the USB port of a PC?
I use a cut USB cable as a 5V power supply from my laptop.
If the two wires on the other side happen to touch each other, will it kill my USB port?
Just to be cautious.
AI: It could, depending on how it is built, and how you will short it.
If simply shorting 5V to GND, it could survive many events. Shorting 5V to data pins can damage the data pins. Shorting 5V to some other higher voltage in the circuit can damage the whole laptop.
If you like to have working USB ports and laptops, don't use your laptop as a power supply. |
H: Debugging long 1-wire line with Raspberry PI
I'm trying to setup a network of temperature sensors for my house connected to a Raspberry PI. I'm using Cat6 unshielded cable (data + ground running on one pair, 5v/ground running on another). To test. the lines (5v, GPIO4, Ground) from the RPI are connected to a breadboard, which has a pair of punchdown blocks pushed into it; ~60m of unshielded CAT6 UTP is run between the two blocks. If I connect my DS18B20 direct to the RPI without the CAT6, it works fine - the RPI detects it and it shows up under "/sys/bus/w1/devices"; if I connect it to the punchdown block at the far end of the CAT6, I either get nothing at all, or an unstable collection of "ghost" devices with incorrect IDs under there. Interestingly, if I connect the sensor direct to the RPI, but also connect the CAT6 after it (with nothing on the end), it doesn't work any more.
Things I've tried:
Using RPI internal pull-up on 1-wire bus, or using external 4.7k resistor between the RPI 5v line and the data line
Putting a schottky diode between the ground and the signal line next to the sensor (Using a Vishay 1N5817 - should I be using a different diode?)
Powering the sensor with a 5v line from the RPI GPIO, or letting it use parasite power from the data line
Putting a 100 ohm resistor in series with the data pin of the sensor (this shouldn't really be necessary with only one sensor - it seems mainly relevant for reducing signal reflections in networks with longer stubs - but I tried it anyway)
I've also measured the resistance and capacitance of the cable, which come to about 6ohms each way for resistance, and 2.8nF of capacitance between the data line and ground. AFAICT the resistance should be fine (these devices draw very little power). I'm not sure if the capacitance is an issue but I would assume not since this is pretty much bang on for CAT6 cable (14pF/foot) and a 60m run is well within what should be possible for a 1 wire bus over CAT6 from everything I've read.
What else can I try? Ideally things that don't require an oscilloscope since I I don't currently have one...
AI: The real reason is that the cable adds up just so much capacitance, that the internal weak pull-up of the Raspberry Pi or even an external 4.7kohm resistor is not strong enough to charge the cable capacitance fast enough to logic high level, so devices on the bus sample the data pin while the voltage is still rising, but is not yet reliably detected as logic high.
The internal pull-up is in the order of 50 kilo-ohms or so.
Another problem is that the pull-up resistor for the GPIO can't be connected to 5V, the Raspberry Pi IO pin is not 5V tolerant, and it will get clamped to about 3.6V by as the internal protection diodes start to conduct current. Fortunately, 4k7 does not allow a lot of current to flow, so it is not immediately damaged, but this is something that should not be done.
Generally the strongest pull-up value to 5V accepted by the electrical specs is 1k5 which allows for 3.3mA. Converting that to 3.3V pull-up means 1 kohm to 3.3V, so you can put a stronger pull-up, as long as it is to 3.3V.
The DS1820B will understand 3.3V as logic 1, and it can pull at least 4mA on data pin, so it can be possible to drop the pull-up resistor value to 825 ohms. The Raspberry Pi IO pins should be able to handle much more than 4mA of sink current.
So simply change the pull-up to be stronger, and connect the pull-up to 3.3V. Keep the sensor supply voltage at 5V like it is. |
H: Is current waveform of given dc-dc converter correct?
I don't understand how current (in continuous mode of operation ) at steady state is bounded for this dc-dc converter circuit.
What I thought qualitatively that current should keep increasing like this -
My analysis was something like that -
At t=0 ;
We close the switch and initially inductor has zero intial current ,and after that current keep increasing and reaches to some value
$$I1max$$
and at that instant we open the switch which causes inductor current to decay through resistive load and reaches to a value
$$I1min$$
and then again switch closes and again current of inductor rises and just before opening of switch current will be
$$I2max$$
BUT
$$I2max > I1max $$
Because this time inital condition is I1min while previously it was zero ,and hence we can say that as time passes initial condition keep increasing and which causes current to increase in every cycle and hence it become a unbounded function!
But whatever I analysed is not what actually happens so where did I make mistake in my analysis ? Or this waveform is not correct?
AI: The mistake you have made is that you have assumed that the peak current will rise linearly with time (at the end of each charging cycle) and for all time. It won't because of the load resistor; it ultimately limits the current to a maximum value: -
$$I_{0(pk)} = \dfrac{V_S}{R_{LOAD}}$$
You physically cannot get a load current higher than the above. |
H: Why the voltage is zero?
The question is asking to find ID1 and ID2 of the two ideal diodes in the circuit below:
I solved it as follows:
The correct solution is as follows:
I would like to know where is my mistake. Also, why did he assume that the voltage at the anodes to be zero? why not 3 or 2 volts? How did he arrive to zero?
The source:
I know the question numbers are different,however, they are the most relevant to the question asked.
AI: Clearly, with a little effort, the solution that is given as correct is wrong. Just analyse the current through D1 with D2 disconnected: -
The maximum current that can flow through D1 (assuming it is ideal with zero volt drop i.e. conditions that maximize current flow), is 6 volts / 43 kΩ = 0.1395 mA or 139.5 μA.
Given that the so-called correct solution is 409 μA, it is clearly miles off.
You cannot trust the so-called "correct solution".
I would like to know where is my mistake.
I would say (given the recent history of you posting questions that supposedly have "correct answer") that your mistake is in trusting these sites or books.
Also, why did he assume that the voltage at the anodes to be zero? why
not 3 or 2 volts? How did he arrive to zero?
I've established that the "correct solution" source is faulty so there's no point trying to wonder what they did. |
H: JFET self biasing
I'm learning JFET self biasing. what I've understood so far is the resistor R_s is used to create a bias voltage as shown. since no gate current flows that means no current in R_G so the potential of the gate is Zero because it is like connecting the gate with the zero potential (ground), then what is the purpose of the resistor R_G? they could have directly shorted the gate with ground, why this extra resistor?
AI: There will be current in that resistor, and there also will be no (DC) current into the gate. Here, take a look: |
H: Why the voltage is assumed zero Confusing
The question asks to solve for I and V.
Why the voltage is assumed to be zero?
Here is the solution
How did he arrive that V = 0 volts.
If he says it’s 2 volts would it be wrong? Why?
I am confused.
This example is from microelectronic circuits by sedra smith sixth edition page#182.
Just confused how is V = 0 volts
AI: If an ideal diode is conducting, the voltage across it is 0V (by the definition of ideal that this book seems to use). That means that the diode can be viewed as a short circuit, and the ground node on the left diode's anode is "shorted" through the two ideal diodes to the node at the right diode's anode. Hence \$V = 0\ \mathrm V\$.
This actually also works if you assume the other common definition of an ideal diode, that a conducting ideal diode has exactly 0.7 (or 0.65, or 0.6, or whatever) volts across it, because you'll then have two identical voltage sources in series, but in opposite directions, so the overall voltage comes out to be zero.
With real diodes, the forward voltage depends (slightly) on the forward current, and the two diodes in this circuit have different currents through them, so the voltage at \$V\$ will come out to be a few millivolts, though small enough to ignore for many purposes. |
H: Why doesn't function generator documentation ever mention the maximum output current?
The output impedance mentioned, but how does this translate to maximum current? What happens if you short circuit the output of a function generator?
Let's take the XR-2206 for example.
The datasheet states an output impedance only for triangle wave of 600 ohms and nothing for the other wave forms.
Why is this 'never' important?
AI: There is output impedance mentioned, but how does this translate to max. current?
I = V/R, so assuming you know the voltage you can calculate the current.
Why is this 'never' important?
If you're going to be driving a load then presumably you would use a driver IC or amplifier suitable for that load, making the current limit irrelevant. |
H: Is there a way to take a battery power source at 7.1volts 15Amps and convert it to 5volts 4Amps?
I'm somewhat new to electrical engineering, I've been messing around with Raspberry Pi and I'm trying to use a 18650 battery pack (2 batteries) to power a Raspberry Pi (and some other things such as a Fan HAT).
I'm trying to convert that 7.1volt 15Amp battery pack to something around 5volt 4Amp. How should I go about doing this? Would it be easier to try and find a battery pack for 5volts 4amps?
AI: First, when you see a power supply rated at \$V\$ volts and \$A\$ amps, it usually means that it'll produce \$V\$ volts at up to \$A\$ amps. If you present that supply with a device that'll take \$V\$ volts and consume \$A / 3\$ amps -- that's what'll happen. For any given load presented with any given voltage, it'll take what current it takes. A source cannot force a voltage and current on a load -- only one or the other.
Moreover, when a battery pack is marked \$V\$ volts, it's just understood that the rating is nominal. For batteries, that's usually the voltage at the middle of their useful discharge curve. So your "7.1V" battery pack will put out 8V or more when it's freshly charged, and as low as 6.4" when it's discharged. Moreover, Li-anything batteries (Li-Ion, Li-polymer, Li-Fe, etc.) pretty much kill themselves when you discharge them too far, so you need to use a circuit that has a low-voltage cutoff, or you need to lay in a supply of extra cells. You also need to be careful if through accident you do over-discharge them, because unprotected cells that have been discharged too far can catch fire when you recharge them.
Second, there's an infinite number of ways you can skin this cat, but there's three that I'm going to mention:
Obvious, but don't do this: use a resistor that drops 2.1V at 4A. This seems like a good idea, but both the battery voltage and the load current will vary, so you'll get just about anything but 5V at the output.
Electrically easy, but thermally hard: use a 5V linear regulator rated for 5A, like a 7805, and a big heat sink. Linear regulators work by passing the load current and dropping voltage through the device, which basically means they burn up a bunch of power as a price of electrical simplicity. So with an 8V battery your regulator will need to dissipate 12W -- this will require a big heat sink.
A bit harder, with pitfalls, but efficient and cool (in the sense that you can touch bits of the circuit and not get burnt): Use a buck converter as @Hearth mentions. You can buy cheap no-name modules for this off of eBay, you can buy more trusty modules for this from distributors like DigiKey, Mouser, etc., in the US or Farnell in Europe. The cheap modules tend to just copy the datasheet circuit, and don't always do the job.
You mention a fan -- this can be problematical, because typically a circuit with a motor in it that's rated for a current and voltage will give you the current that the motor will need once it is spinning. There may be some "inrush" current, possibly much higher, needed to actually start the motor. I say "may" because one could design a fan circuit to limit the inrush current -- I just have little faith that it's actually done.
So I recommend that, first, you have a separate buck converter for your "clean" 5V supplies (your Arduino and any other logic) and your "dirty" 5V supplies (your fan module). Then I recommend that you read the fan module's datasheet carefully for inrush current. Batteries can easily handle brief overloads (i.e., a battery rated for 4A could do 12A for 1/10th of a second, no problem). Buck converters can't (unless "brief" means 10 milliseconds, and maybe not then). So your "dirty" 5V supply needs to be sized for the inrush current of any motors & whatnot.
And shop carefully for your module -- I can't tell you who's reliable beyond CUI and TI, and I don't even know if CUI makes modules. But if you get something cheap from a surplus place, an auction house, or someone that also sells dishware, you'll be disappointed. |
H: How to make sure that my compensated attenuator would work for certain pulse widths?
I have an input (one-shot) pulse that has to be attenuated by 1/2 (half). The input pulse would be of variable width in between 1us and 100ms and would have a variable amplitude: one voltage level would always be ground (0V) while another level would vary within ±3V (the height would vary within ±3V). So I saw a compensated attenuator as explained here and tried to simulate it. Searching a bit online, I came to the conclusion that R1*C1 = R2*C2 should be satisfied for a square output.
After some trial and error, I could find a value (of R and C, also making sure R1C1=R2C2) that seems to work in LTSpice but I am not sure if this would work for the entire range. Also, the attenuator output is buffered by a voltage follower as well. Below is the subcircuit. 'V_out' is the original pulse and 'op_out_bias' is the output of the opamp. The output of the attenuator is (almost, the difference can't be seen at this zoom level) exactly the same as the output of the opamp.
So first of all, is this the right way to achieve attenuation (by a fixed factor) of a single pulse? How to formally (or informally) make sure that the circuit works for the above-mentioned parameter range (of width and amplitude)?
Note: I have tried different parameters (within the above range) in LTspice and so far it seems to work just fine.
Edit: I am adding the rest of the circuit. I didn't think it was that relevant (I apologize for that). The source is an output of an analog switch (SPDT, ADG619) that is being controlled by a pulse generator. The inputs of the switch are ground and a DAC output (didn't decide on the DAC) through another buffer. Below is the picture:
AI: The compensated attenuator is used when the goal is to minimize the loading on the source, which is what you need in a scope probe. Notice that the resistor values (in the example you linked) are very large.
A pulse would not typically be called an "ac signal" although it has some high frequency ac components. Your pulses are fairly wide and the edges aren't terribly fast so your situation isn't as tricky as designing a scope probe. A scope probe is also at the end of a relatively long cable so the probe has to compensate for the capacitance of the cable...you don't need to do that.
In your case you aren't worried about loading the source, you just want to reduce the amplitude of the signal. So you can use resistors with much smaller values, and your 10pF capacitors aren't doing much for you. |
H: Is it possible to use an electrical motor with a constant torque while simultaneously turning against it?
I've been thinking about whether it is possible to have an electrical motor output a constant torque against which one can then apply a force without breaking the motor?
I guess the best example would be barbells or some other weight. The motor would pull a certain amount, and at the same time, a force pulls against the torque.
Another example would be a heavy door that is supposed to close when let go, but not as forceful to avoid noise, so the motor would pull against the weight of the door, but the door is still closing, albeit slower.
I have no experience with motors whatsoever, but I would think that one best takes a brushless torque motor. The question now is, is it possible to turn against the torque without breaking the motor?
Thanks!
AI: All the things you are talking about can be done with motors provided that the motor is controlled intelligently. Some types of control may require shaft position sensors on the motor.
Motors can be controlled to apply constant torque, or constant speed, or to hold a specific position (constant position) or various combinations of these things. For example you can tell a motor to hold a specific position but with a low programmed torque limit. Then if you move it away from that position in either direction it will resist you but with gentle force. If you move the motor then let go, the motor will return to the set position.
AC induction motors, brushed DC motors, and brushless DC motors all can be controlled in this fashion. There are tradeoffs between the different types. Often BLDC is the highest performance and highest efficiency.
One comment about torque because I think you have a wrong idea about what fixed torque means. The motor applies torque to the drive shaft. The load also applies torque. In a typical machine, the two torques are equal and opposite meaning the net torque is zero. Now this next statement is very important: If the motor torque and load torque are not exactly equal and opposite, the motor will either be speeding up or slowing down. If you instruct a motor controller to make maximum torque with no load, the motor will spin up to speed very rapidly. So you shouldn't have the idea that you can command a motor to output a torque and you can then push against it. You can command the motor controller to hold a position and push against it. But pure torque output will usually lead to runaway speed if you remove the load on the motor. |
H: ± usage and absolute sign ambiguity
This is from the Datasheet for Texas Instrument's NE5532:
Does this mean I can safely supply Vcc- = 0V, Vcc+ = 30V, and let all other voltages swing within that range?
If that's the case, then that would be one of the ways I've been reading these datasheets the wrong way. Values would usually show up like this:
I used to think that that meant the absolute maximum potential difference between the supply pins should be 22V.
Why is it expressed as ±22V when they could just say 44V?
Why use the ± symbol at all?
Why say 'absolute' then present a negative value?
AI: You are almost right.
One other very important characteristic is the common-mode range: In conventional opamps this must not get closer to the supply rails that ~2V. For the NE5532 it is shown as below. Note that when supplying +/-15V the device is only guaranteed to work if the inputs are in the range of +/-12V. A typical device will go about a volt further than that to +/-13V.
The device won't be damaged if either input goes to either the positive or negative rail but it won't function as an amplifier. In fact with some devices, the gain may actually reverse and the negative feedback will turn positive causing latchup.
Most opamps of this type have traditionally been used with dual supply rails so the convention is is to describe the supplies as +/-. You could use it as a single supply but the inputs and outputs wouldn't be able to go to ground.
Some amplifiers, commonly referred to as single-supply devices do allow the inputs to go down to ground. Others referred to as rail-to-tail allow signals (input, output or both) to go to either supply and the device still operate. There are often compromises in the operation of such devices though so you need to study the datasheet catefully.
Also be very careful about the distinction between the maximum ratings where the device may suffer damage and the values shown in the characteristics table where the conditions required for normal operation are described |
H: How to activate one LED separately in a group of LEDs?
I want to activate one LED in a group of LEDs depending resistance varies linearly depending on the temperature.
I am using variable resistance that Controls how LEDs will light.
LED1 and LED 2 and LED 3 Depends on Variable resistivity
The problem I have encountered with my circuit, all LEDs turn on at the same time.
Maybe the solution is to use the transistors, but I have no information about which type to use them.
Can somebody help?
[
AI: If you can imagine single supply comparators and CMOS 4xxx series logic on 10V with a 8k pot +4K R to simulate your sensor, this is it. |
H: why does the Stm32f103c8t6 Board need an ST-Link V2?
Well I am starting a course on embedded systems on udemy and it seems I need an M3 or M4 ARM cortex MCU so I can follow on the projects. The course itself recommend the Discovery board, but I was aiming for the stm32f103c8t6 Datasheet
It seems that there's no much information about the board in terms of programming on the stm32 IDE as everyone is using it with the Arduino IDE .
I was wondering If I will need additional hardware beside it like an st link v2 ( which I don't know it's purpose yet ,but that's what I got after some searching ). in order to be able to program and debug nicely along the course
The first part of the course is in the following link in case someone needed more details The Course
AI: why does the Stm32f103c8t6 Board need an ST-Link V2?
You do not "need" it but you "need" a way to write your program to the flash on the part.
Well I am starting a course on embedded systems on udemy and it seems I need an M3 or M4 ARM cortex MCU so I can follow on the projects. The course itself recommend the Discovery board, but I was aiming for the stm32f103c8t6 Datasheet
I watched most of the (first) class so far. It is almost all about the C language in general but does walk you through the chip document to show you registers and bits, as well as how to write code to access them.
The part on the stm32f4 and the part on the stm32 blue pill are not the same and are not compatible. The cortex-m3/4 is not relevant with respect to addressing and using the peripherals. So the concepts and tools will all work the same, the exact addresses and bits will not.
It seems that there's no much information about the board in terms of programming on the stm32 IDE as everyone is using it with the Arduino IDE.
I would have to disagree with this in a few ways, I would say percentage wise nobody is using the Arduino IDE. The truth is somewhere between everyone and no one. The cost of the blue pill makes it easy for people to use with all of the various solutions, not limited in any way to the Arduino. Most folks are not using Arduino.
st and arm have plenty of information along with countless examples across the internet about how to program these mcus. And as a result these stm32f4discovery boards as well as countless examples that are specifically for these blue pill boards.
The class uses the ST IDE and the stm32f103 is still an available product so I cant see that one of their tool choices supports this part. The blue pill is just a breakout board with a crystal, so while they may or may not
support the board (knowledge of where the led is??) there should be support for the part.
I was wondering If I will need additional hardware beside it like an st link v2 ( which I don't know it's purpose yet ,but that's what I got after some searching ). in order to be able to program and debug nicely along the course
The (authentic) stm32f4 discovery has an stlink on the board, so you do not need to buy one separately.
The blue pill does not have debugger hardware on it, you have to buy that separately. The stlink of any flavor is just one possible solution, it is not the only solution, so therefore not "required".
When you read the documentation about the stm32 chip and the arm cores (go to the arm website) you find that there is an swd (single wire debug) interface to the arm core which the stm32 parts will expose. Stlink is essentially a usb protocol that you use to talk to a debugger (in this case external hardware between your development computer and the target mcu). The stlink solution is a path essentially to the swd protocol so that with software that speaks the stlink protocol you can talk to the arm core. With access to the arm core you can do, among other things, write your program to flash so that it can be run when reset or powered on.
There are other paths, usb protocols if you will to hardware (boards) that then speaks swd for you. Most notably but not limited to jlink and ftdi based boards in particular those with MPSSE.
The stm32f103 part also includes a bootloader (software) from st, not an arm thing. This provides access through that interface to write your program into the flash. (also documented on st's website) And there are too many to even mention solutions here, costing from around a dollar to maybe 15.
The blue pill may come pre programmed with an application that works as a bootloader that speaks a well known usb protocol that the Arduino IDE also supports. But this is the same application flash area where your programs will live so if you mess this up then you cannot use this interface anymore you have to use one of the ones above, with external hardware, to reprogram this bootloader into the application flash so that you can to back and try again using the Arduino IDE. The stm32f4 discovery does not have this problem there is a separate debugger and target mcu the debugger hardware can reprogram the target mcu independent of bugs in your code (those that do not destroy the hardware).
So back to the title question:
why does the Stm32f103c8t6 Board need an ST-Link V2?
You do not "need" it but you "need" a way to write your program to the flash on the part and that might desire an SWD solution of which the stlink is one (but not the only one).
The stlink version should not matter.
SWD is not your only path in, and stlink is not the only swd solution. There are lower cost solutions to program the blue pill (that may or may not be compatible directly with the arduino ide).
The class or this first one is at least mostly C language stuff not using the board but using your computer. When it does use the card it does rely on the stlink interface. Where the lecturer will click a button on the GUI and a second or seconds later the board is programmed and the led is blinking or whatever. That few seconds might take you a few weeks to get working for you depending on ability to find the right info and experiment, it might take me an afternoon for example. But I hope, but not necessarily expect the IDE to "just work". You might get lucky.
This class moved on quickly into adding another piece of hardware that perhaps you want to buy to add to the stm32f4discovery. One thing I often struggle with is sticking to someones sandbox, I eventually build my own. Although the board is expensive relative to perfectly valid alternatives for the same goal, for the class I would recommend you buy the hardware used by the class. At the same time IMO you can watch this class without any MCU boards and then make your own decision. You can take that knowledge and attempt to use the Arduino IDE if you wish and the blue pill, or search for folks using the ST IDE and the blue pill.
IMO the blue pill boards are low quality I have ordered many and had a number of them arrive non-functional. Likewise there is an stm32f4 discovery clone that is low cost, it does support dfu-util, but like the blue pill might just work, but no surprise if it does not. And I have had a percentage of those be bad or marginal. So while trying to learn you may also be struggling with hardware issues. The nucleo boards are so far pretty good and you do not need additional hardware to make the mcu work and one would expect there to be direct support in one of the st IDEs. Same goes for similar boards from the other vendors (ti, atmel/microchip, nxp, etc). |
H: Error in constant current sink circuit and current regulator
I have found a circuit online, which is supposed to be a steady current sink:
simulate this circuit – Schematic created using CircuitLab
and every time I simulate in LTSpice, if I change Vc, the current through RL is changed and I don't understand why this is happening. Can anyone help?
I have another circuit (which is my own invention) and it kind of has the same working principle. It is a current regulator without using any feedback, and it is this:
simulate this circuit
R3 is the load and it still shows odd results when run it. Above the zener voltage, it should work like a constant current sink and below the zener voltage of the diode, it should work like a NPN circuit with some base voltage and some collector current for output.
AI: Conceptually Simple Current Source
When considering a circuit that creates a current source from a low impedance voltage source, perhaps the easiest to conceive is this:
simulate this circuit – Schematic created using CircuitLab
The current regulation of this circuit, with respect to changes in the load, is:
$$\%\,I_\text{LOAD} = \left[\frac{-1}{1+\frac{R_\text{DROP}}{R_\text{LOAD}}}\right]\cdot \%\,R_\text{LOAD}$$
In short, the larger \$R_\text{DROP}\$ is the better. But this means that \$V_\text{SRC}\$ needs to be larger. So, a nearly ideal current source can be fabricated from a very, very high voltage source and a corresponding very, very large voltage-dropping resistor.
For example, suppose \$R_\text{LOAD}=100\:\Omega\$ and you want a constant current of \$I_\text{LOAD}=100\:\text{mA}\$. You could use \$V_\text{SRC}=100\:\text{V}\$ and \$R_\text{DROP}=\frac{V_\text{SRC}-R_\text{LOAD}\cdot I_\text{LOAD}}{I_\text{LOAD}}=990\:\Omega\$. This would provide regulation equivalent to about \$\%\,I_\text{LOAD} = 0.092\cdot \%\,R_\text{LOAD}\$. A 10% increase in \$R_\text{LOAD}\$ would exhibit only a -0.9% variation in \$I_\text{LOAD}\$, or a change of about \$-900\:\mu\text{A}\$ to \$I_\text{LOAD}\approx 99.1\:\text{mA}\$. The price is that you need a higher voltage supply (which is more complex) and have to waste an additional \$9.9\:\text{W}\$ in the dropping resistor to deliver a constant current into a roughly \$1\:\text{W}\$ load.
That may be good enough. Who can say? But it's simple to conceive. And it is very easy to see how to improve the current regulation with respect to load changes. Just use a still higher voltage for your power supply and a larger valued dropping resistor to go along with it and waste still more power (and add complexity and safety issues.)
This method is very commonly used when the load is an LED. In part, this is because the LED is a non-linear device and in part this is also because the regulation needs for LEDs are often fairly loose, so a lower voltage works well enough for the purposes. But it's also a pretty bad choice in other cases.
Your Circuits
Below left is one, below right is another, and I've added the middle one to act as a transition schematic between the two (mostly because it's commonly found in practice):
simulate this circuit
I won't spend a lot of time on them. Just a few points.
The schematic on the left has an advantage of a wider compliance voltage range for the load, because two diode drops aren't a lot of overhead -- leaving more of the available supply voltage for the load. But diodes vary a fair amount, one to another, and their voltage drop is highly affected by ambient temperature and, to a degree, by the current in them as well. Variations in the load lead to variations in the base current of the BJT and impact to a small degree the current in the diodes, as well. Those load variations, as well as temperature, also affect the BJT's base-emitter voltage and that also impacts the load current.
The middle schematic is used because it doesn't require two voltage supplies. That's an advantage. But it also has the disadvantage that the current in the zener can vary widely and this does impact its voltage and therefore the load current.
The right hand schematic isn't found as often because of the dual-supply requirement. (This is the one you call your own invention.) But it does permit setting the zener current independently from the compliance voltage source used for the load. Still, the requirement for an extra voltage source is an annoyance.
While I've kept your idea as you wrote it, most of us would probably gravitate away from requiring a separate voltage supply and would, instead, more likely move towards replacing your zener's resistor with a constant current source tied to the original voltage rail. It achieves the goal without needing a new voltage rail. (Less parts, smaller, and probably lower power, as well.)
The disadvantage of both middle and right schematics, vs the left schematic, is the loss of voltage headroom. So there's a price to pay.
And all of them suffer from temperature variations, to some degree from part variations, and from the Early Effect in the BJT.
Two Additions to Consider
Here are two improvements:
simulate this circuit
The left side replaces your diodes or zener with an active BJT that measures the current in \$R_\text{ISET}\$ and makes adjustments to the base voltage of \$Q_1\$. This is much better because it also takes into account \$Q_1\$'s Early Effect by measuring it, too, and correcting for it. So this is a big improvement in that sense. However, it remains sensitive to \$Q_2\$'s temperature and part variations. It also is sensitive to the supply voltage because that can greatly increase the current in \$R_1\$ and thereby require higher collector currents in \$Q_2\$ which affects the base-emitter voltage and thereby also the collector current of \$Q_1\$. So it will still respond somewhat to wide swings in the supply voltage, causing load current variation with supply voltage. It's just a bit better on a few scores. And it can be better designed/managed, if you put some work into it.
It would be possible to consider replacing \$R_1\$ with an active current source -- just as I suggested one could also do with the earlier "middle" schematic and that would improve it's behavior with changes in the supply voltage. But it comes at the cost of added voltage overhead and more parts. So, like everything, there are trade-offs to consider.
Just a last note on the left side schematic. Although it does respond a lot to temperature variations in \$Q_2\$, it is relatively immune to temperature variations in \$Q_1\$. Since most of the power dissipation is in \$Q_1\$, which heats it up, and since it is possible (usually) to keep \$Q_2\$ at some distance from it, this helps limit the temperature response of the circuit to ambient changes and not to ambient changes plus thermal changes due to load or power supply variations. If one arranged for \$Q_1\$ to be thermally stable somehow, it would be pretty decent. Unfortunately, that would likely make the circuit unaffordably complex for the benefit.
The right side schematic is about as close to perfect as you are likely to find. The TLV431 device has a lot of internal parts and some very crafted design work so that it is relatively stable over a very very wide range of ambient temperatures. It just works. Period. It also works well over almost three magnitudes of operating current, so you can pretty much just use \$R_1\$ without worrying about replacing it with a current source, too. This makes this right side schematic almost like gold. It corrects for the Early Effect in \$Q_1\$, too, as well as temperature effects on \$Q_1\$, too.
Here's a Spice run. I didn't vary the load, but I varied the operating temperature from \$0^\circ\text{C}\$ to \$55^\circ\text{C}\$ and varied \$Q_1\$ over quite a range of possible behaviors. The left side of the display below includes the entire supply voltage range from \$0\:\text{V}\$ to \$20\:\text{V}\$, while the right side shows the supply voltage range from \$3\:\text{V}\$ to \$20\:\text{V}\$ in order to zoom up on the variations better. Both the TLV431 and 2-BJT designs were set for about \$16\:\text{mA}\$, which I just picked out of the air for these purposes.
I think you can see the difference that a TLV431 makes.
Summary
Sensitivity equations are also very, very useful in helping to both quantitatively estimate how a variation of an input parameter impacts a design goal's output parameter. The process allows you to first find out which is of more concern and then also if that concern is sufficient to warrant more design effort. Or, alternately, to realize that that the design goals have been met and the design can be considered complete.
Another approach used by many is to just perform lots of Spice runs (or use lots of Excel runs) to achieve similar results.
Note: Pete W mentioned in a comment below that the LM4041 is a high-side device similar to the TLV431 device. I hadn't known about it and now I'm glad to hear of it. So I'm making a note about it within the answer to capture the option. Sometimes, you want a controllable high-side source rather than a sink, depending on load requirements. So that's a nice catch from Pete W. Thanks! |
H: 0.1 uF in parallel with larger >1 uF to reduce noise from IC
Back in the day when we would use an electrolytic capacitor across the supply of a IC we would always put a 100nf Ceramic in parallel because (if I remember correctly) electrolytics had inherent inductive properties that would not suppress the HF noise on the power rails.
However, these days, high value ceramics exist (I regularly use 47 uF SMD in an 0805 package).
So does this mean, that I can get rid of the 100 nF (Ceramic) in parallel with the 47 uF (ceramic) caps because the 47 uF is ceramic and hence does not have the inductive properties of the electrolytics?
thanks
AI: It is recommended to decouple with multiple caps but it depends on the circuit, chips overall design.
Higher caps, even MLC have higher SR, thus their filtering ability at higher frequencies drops significantly.
from here.
As an example, typically ADC for instance, which has a high-speed logic side and a low noise analog side often requires 0.1uF and 10uF decoupling on both their analog and logic supply. Same goes for some opamp, clock sources, etc..
Back in the day when we would use an electrolytic capacitor across the
supply of a IC we would always put a 100nf Ceramic in parallel because
(if I remember correctly) electrolytics had inherent inductive
properties that would not suppress the HF noise on the power rails.
However, these days, high value ceramics exist (I regularly use 47 uF
SMD in an 0805 package).
It is true, caps got better and today's Ceramic has much lower SR than old electrolytic. But, as electronics has evolved, we now deal with much higher frequencies than in the old days, with microcontrollers often running in the 100Mhz range, clocks in the Mhz, and other buses in the Mhz range as well, without talking about CPU, RAM, etc.. Only using large ceramic caps will probably give you some issues and EMC problems.
If you look at reference schematics, IC will almost always have a 0.1uF decoupling cap, sometimes a 1uF or 10uF caps on some chips, and a few bulk caps.
Example from an opamp datasheet:
The EEVBlog has a very nice video about decoupling caps. |
H: Charging four cells in series with a TP4056
I am using a TP4056 module to charge four Li-ion cells in series using four of the modules.
The red wires in the diagram represent wires for positive terminals and black wires for the negative terminal, while blue wires and green wires are used for connections.
When I tried charging with this circuit the circuit burned out and the TP4056 and other components in the module started emitting flames and, obviously, the circuit failed to do what it was supposed to do.
Could anyone tell me the right circuit or changes I can make in the present circuit?
I have already considered problems like the circuit getting shorted or too much input and have taken care of that already, yet the circuit failed.
When tested with two cells in series it worked fine, but it failed with four cells.
AI: This is NOT going to work!
The - input and - output of the TP4056 module are connected and that will short your battery. I have indicated one of the shorts in purple:
To be able to charge 4 cells in series with 4 TP4056 modules you would need 4 separate, isolated power supplies.
But I would not recommend that. The proper way to charge 4 cells in series is by using a charger that is designed for that task. It should include balancing so that all cells will be charged to the same voltage despite differences in capacity between the cells. |
H: TDA2030 strange startup noise problem suppression
As a newcomer in electronics as a hobby field, before starting, my humble request to everyone is to not get annoyed by my questions which sometimes may be little silly.
So lets get started: I have started studying a little about opamps for audio amplifying and the IC I am using is a TDA2030. In previous circuits, I used to have a potentiometer to control the gain of the opamp, and that method worked very well,
Then I realized that I can't use a potentiometer everywhere to control gain of this IC so I found another formal way to do this; the diagram is shown below:
simulate this circuit – Schematic created using CircuitLab
When I start this circuit up, I get very high noise for a few seconds from starting time, every time. The noise goes away automatically after a while; it takes almost 1-2 mins to get pure sound without any noise. So what I want is: as soon as I start the circuit, the noise is removed.
First Question:
Am I missing some other components which is making it behave so? If yes so what are those and please explain their functionality. And what is the cause of this startup-time noise?
Last question:
When I discharged the Capacitor C1 before running the amplifier, this produces same noise for few seconds again. Why so? Does the capacitor's charged or discharged state matter here? Or is it the original functional procedure of the IC?
Thanks for your precious time, and please always put a schematic with example for my better understanding which will be more preferable to me.
AI: The problem is that you haven't got a pull-down resistor on the non-inverting input: -
Transistor amplifiers of this type (and op-amps) need to have their inputs biased correctly and that means adding resistors where appropriate. The inverting input on your schematic is fine because the input is biased by the feedback resistor (R2 in your schematic).
So, because you have a single sided supply, you need to do this: -
You also need to add power supply decoupling capacitors as indicated by C3 and C5 in the diagram at the top of my answer. And, in case you still get some noise, you might need to do this: -
Image from TDA2030 data sheet. |
H: Where is my MISTAKE in my solution?
This is the second time I keep asking the SAME thing. I hope I finally understand.
The question is as shown below:
with its answer:
Below is my answer for part a. PLEASE tell me where is my mistake!
FYI the accurate answer is that both are conducting. But what is wrong with my assumption.
Thanks in advance.
AI: the accurate answer is that both are conducting. But what is wrong
with my assumption.
There's nothing wrong with your assumption; it's just an assumption that tests a hypotheses. So, you make an assumption and you find that for an ideal diode, the voltage at V is -3.333 volts. The assumption you made, in effect, disconnects D1: -
It's what you do next with the voltage being -3.333 volts that is important - you TEST that initial assumption.
So, if V = -3.333 volts then (with ideal diodes), the voltage at the cathode of D1 is also -3.333 volts and this cannot be possibly true (because it means D1 would certainly be conducting).
Conclusion: the initial assumption is false. But, it's certainly not incorrect to make what is proven to be a false assumption - this is part of the process of getting to the truth. |
H: SPST pin configuration
I ordered a SPST switch (Through hole type) from distributors and also download the cad file for PCB layout from the same website. I am now confused with the pin configuration, in the footprints it has 3 holes. Usually the SPST switch has only 2 pins right?. I have gone through the datasheet but I did not understand it completely about the pins because they have the same diagram for SPST and SPDT I suppose.
My question is, if it has 3 pins then what will be the pin connection if I want to just turn ON and OFF the circuit and If it has only 2 pins then which pin should I ignore(delete) in the footprints. I attach the footprints picture and datasheet link with this. Footprints which I downloaded are perfect with the measurements (for 3 Pins). Please let me know if u have any leads on this. Thank you
https://eu.mouser.com/datasheet/2/221/MS-100406-1174115.pdf
AI: The SPST model should only have two pins as can also be seen in the datasheet, although it is not clearly labeled. Removing either pin 1 or 3 should work, since the pin spacing is equal. |
H: What is the stability of a digital signal processed by a filter with z-transform?
I have a question from the book FE Electrical and Computer Review Manual by Michael R. Lindeburg page# DE X-1 with its answer as follows:
I tried to solve it as follows:
I don't understand why is it when z = -2 the system is unstable?
AI: The mistake was here: -
You assumed that the rules that apply on the s-plane also apply to the z-plane. They don't because when you map the left hand side of the s-plane to the z-plane you get a unit circle: -
It's a unit circle (amplitude 1) because the s-plane Nyquist frequency is \$\pi\$ radians per second (0.5 Hz). So, everything inside the rectangle on the left side of the s-plane bounded by the top horizontal magenta/purple line down to the lower horizontal dotted black line is within or on the unit circle in the z-plane.
So, given that you calculated z-plane pole values of -1 and -2, the -2 pole is clearly unstable. |
H: Does a battery powered resistor have Johnson Noise?
The mean noise voltage for Johnson (Thermal) Noise is given by the formula:
\$ v_n = \sqrt{4kTR\Delta{f}} \$.
The bigger the resistance of a resistor or the higher the frequency of a voltage supply, the higher the thermal noise the resistor will have. Does the formula also indicate if the voltage is supplied by a battery (DC, or a voltage of 0Hz frequency), any noise you measured on the resistor cannot be due to thermal noise because:
\$ v_n = \sqrt{4kTR \cdot 0} = 0V \$ ?
[Edit]
The question should be - what is \$ \Delta f? \$
AI: yes. Even a resistor with no power source will generate Johnson noise. This is thermal noise due to random movement of electrons in the resistor itself.
f in the formula is the bandwidth across which you wish to calculate the noise, it has nothing to do with the signal applied (or not) to the resistor. |
H: Correct schottky diode selection
So I'm using the LMR16006 DC/DC converter which is suggesting to place a Schottky diode from the SW pin to ground with a voltage rating 25% higher than my input voltage, which is 50V. Hence, the voltage rating should be at least 62.5V.
Datasheet: https://www.ti.com/lit/ds/symlink/lmr16006.pdf
How much would it matter if I would take, for instance, a 60V diode?
Then, I'm struggling with the current rating.
For instance, I'm looking at components at DigiKey at this moment and I've made a list like this:
https://www.digikey.nl/products/en/discrete-semiconductor-products/diodes-rectifiers-single/280?k=schottky+diod&k=&pkeyword=schottky+diod&sv=0&pv914=119750&pv914=167594&sf=0&FV=-8%7C280%2Cmu70V%7C2071&quantity=&ColumnSort=0&page=1&stock=1&cad=1&pageSize=25
The datasheet tells me: ", the current rating for the diode should be equal or greater to the maximum output current for best reliability in most applications". Does this comply with the "Current - Average Rectified (Io)" in the list I obtained above? What does a higher or lower current mean in the application?
I assume an output current of 700mA in my system.
As I'm learning, I truly like some explanations on value choices
I've included a schematic in which D1 is the diode I'm talking about.
AI: From your search results I just picked this one to go off in my explanation. https://www.diodes.com/assets/Datasheets/ds30018.pdf (B170/B)
Its all about how the system is designed. If your system is designed to work at 50V and there are limiters in place to keep max voltage under 60V then a 60V diode would be fine. Therefore, you should pick a diode with a reverse voltage that is higher than a voltage you expect to see. 25% higher than the max voltage is a good metric to go by, but higher is for the most part normally better.
As for output current it pretty simple. 700mA is your average rectified current. Pick a diode with a higher average rectified current, like 1A.
For more information. The diode only conducts current when the mosfet is off. Therefore, your average current is actually less than 700mA because of the Ton time. These two images here show what happens during the off state of your mosfet. As you can see current through the diode starts at Imax and falls over time to Imin. These values can be found by using the "9.2.2.2 Output Inductor Selection" section of your technical documentation. Assuming a 40% ripple current will show that your peak current will be .98 A. Which is under even the average rectified current of the diode I picked.
Sources: https://en.wikipedia.org/wiki/Buck_converter |
H: Why don't I need device drivers for a UART to communicate with a Linux box but need device drivers if USB is to be used for communication?
I have a Linux box. I want to troubleshoot certain things and I was told that I need to custom solder pins to communicate using UART as perhaps it doesnt have device drivers to communicate using a USB port which is only there for charging and missing drivers to use TTL.
Why don't I need device drivers to communicate with Linux using UART but need to add drivers if I have to use the USB port?
This is incontext to this blog where author mentions:
Loading the code
Point 1). is easy; by powering ON the RetroMini while pressing B, the CPU will switch into a special mode where it will listen for commands on the USB bus. By sending specially crafted commands, it is possible to load custom code to the RetroMini
and then
Debugging the code via UART
The simplest way to debug your code is to just make it print stuff to the output console. Print register contents, print “success” if your check worked, print “oh noes” if it failed… If your program outputs text to the console, the whole process of writing a program becomes much easier.
Despite the fact that USB port is present, then why the need to solder extra wires to use UART protocol?
AI: It does need drivers - but you are using a standard protocol (USB CDC), so Linux already has the drivers built-in. The USB/UART chip knows how to speak the USB CDC protocol, and so does Linux.
If you have your own chip that speaks USB (but not CDC) then you will need to give Linux a driver so it knows how to speak the chip's protocol.
You could also use a standard USB protocol - like CDC or MSC or any other standard device class that your computer has a driver for. Then, your computer can use that driver. |
H: Training Kit for SMD components
I created my first circuit with a microcontroller, an stm32f446 in lqfp64 package. However I have soldered such tiny parts and I'm struggling a bit and already destroyed one of three chips I bought.
Is there any kind of training kit? I do not want to spend each time 10 bucks for training purposes.
AI: Buy the cheapest IC and SMD parts you can find on ebay, and pratice with them. It doesn't matter what they do.
You can also buy some SMD to DIP boards for cheap, that matches the IC package, to practice solder on. |
H: Is measurement uncertainty 2 times standard deviation or 2 times standard error?
Textbooks and online sources often say the industry standard for uncertainty is given at a confidence interval of 95 %. This means out of 100 measurements, 95 would achieve the specified value and deviate around this value in range of the +/- uncertainty given. For example temperature sensor: states uncertainty of 1 deg C within a certain range. So 95% of the time the uncertainty is within this range.
However i am not sure how this uncertainty is calculated. Is the uncertainty 2 times standard deviation or 2 times standard error?
If for example a temperature sensor says it measures temperature with an uncertainty of +/- 1 deg C, then did the manufacturer test this sensor say a thousand times at a controlled temperature, for example 25 C, calculated the mean to be 25 C of those 1000 measurements, and then give this uncertainty as +/- 2 times standard deviation/standard error to get the final uncertainty of +/- 1 deg C ?
Here is the source of the formulas and uncertainty explanantion: https://andyjconnelly.wordpress.com/2017/05/16/uncertainty-and-repeats/
AI: It can depend on the manufacturer how well they actually measure their limits for guarantees. Usually the actual methodology is not documented in great detail, though they may have some type of general documentation. I've done the measurements for a few of these lines on datasheets. Basically, it is a guarantee by the manufacturer that the value will fall within the limits. Usually what's at stake is mainly the manufacturer's reputation -- there is often a clause somewhere that they will not be liable for other damages, though major customers do sometimes ask for big payments if they need to upgrade equipment in the field because a batch of parts was out of spec.
The simplest case is when the parameter is tested at production. In that case, we normally calculate the 6-sigma reproducibility and the 6-sigma repeatability errors and use those margins, often padding more to a round number. Reproducibility errors are based on testing on different testers and using different test boards/sites. Repeatability errors are based on repeating the test on the same part multiple times (often re-inserting into the socket).
The somewhat trickier parameters are ones that are not possible to measure at production test. Often this is because it takes too long to measure (e.g., sweeping temperature after packaging) or we don't have the right instruments on the tester. We have to measure these in the lab using slower methods (e.g., sweeping temperature 1 part at a time). Again, we often use 6-sigma margins on measurements, but this can sometimes be much more than you would think. For example, if the part has a type of internal comparison that runs once every clock period, we calculate how many times it would run at max speed over 10 years, and then extrapolate/calculate so that less than 1 part sold per million would fail once in that 10 years (1 ppm is actually a bit better than 6-sigma). That extreme example is really only if this type of failure would cause the part to become useless (e.g., requiring a power cycle).
The above is what we do for a "competitive" parameter -- one that distinguishes our part from the competition and is the reason somewhat would choose our part. If it's a parameter that is not very important, we sometimes use much larger margins just in case we did something wrong (e.g., missing some cause of variation). That way we don't get returns for parameters that we don't really care much about.
The other main strategy for specifying competitive parameters (like if the competitor is not using such a rigorous method) is to put a footnote that says exactly what is meant, e.g., "3-sigma in condition X with N=100." That's more of a marketing decision than an engineering one though. |
H: Correct way to wire USB 2.0 Type C connector?
I'm playing around with building a simple keyboard, that will have just few buttons, nothing complex.
I have decided to use USB 2.0 Type C connector, like this or this.
Now when following USB 3.0 specs, it says we should use pull down resistors on CC1 and CC2 so that host can tell if device is on or not and also resolve orientation.
But USB 2.0 specs says we should use pull up resistors on D+ or D- lines and that without them host would not recognize device.
I'm confused what to do here since I have both CC1 and CC2 but also D+ and D-.
Should I follow USB 3.0 specs and pull down only CC1 and CC2 lines like this:
Or should I also pull D- up to 5V like this, while pulling CC1 and CC2 to the ground like this:
I would be thankful to someone who could explain how to use these 2.0 Type C connectors and point me to some specification I could read. And explain why use pullup on D- when I already pulled CC1 and CC1 down to ground? Or can I just ignore CC1 and CC2 lines and just use pullup on D- line if it's USB 2.0?
Edit:
MCU I'm using does not have internal pullup or pulldown resistors.
Pull up on D- should go through 1.5k resistor, I missed that one.
AI: You want a Type C so connect the CC pins as per Type C as they don't exist in USB 2.
The rest must be done according to USB 2.
If you want to read more about it then the read the USB specs, they have everything you need.
You have also shorted D- directly to 5V, that will damage your PC and your device, don't do that. Besides the pull-up resistor would not be connected to 5V to begin with, but to 3.3V.
Depending on which USB chip you are going to use, the pull-up might be internal, so without knowing what is connected to your connctor, there is no way to answer if you should have a pull-up or not. |
H: Reactance to varying DC
Input signal (a) is AC.
Input signal (b) is varying DC.
As (b) has a frequency but does not change direction, does the capacitor's reactance have a different effect
than input signal (a)?
AI: A capacitor's reactance depends only on the value of capacitance and the frequency of the signal presented to it. Your example (b) has the same frequency as example (a), with the addition of a DC component, which has zero frequency. The long term effect of the DC component is to charge the capacitor to 5 volts. After that its reactance would be the same as in example (a). This charging takes place exponentially with time constant RC, so that as a practical matter after 4 or 5 time constants, equilibrium is reached. |
H: How to get a clean 50 kHz square-wave with 555 timer (Astable Mode)?
I can't get a pure square wave above a few kilohertz. Everything is fine at the lower frequencies, but I would like a clock speed of between 50 and 100 kilohertz. Unfortunately, there is a distortion on the rising edge. Is it possible? Is that the nature of this chip?
Here is 28kHz waveform example.
AI: The usual reason for ringing is wire inductance including ground clip resonating with the probe cable capacitance. With you short all the leads incl. gnd clip to 1cm that inductance of ~<10nH/cm will make it better. To improve further requires a load resistor, either pullup to Vcc or down or both. |
H: How dense is SRAM compared to random logic?
Modern CPUs always have some on-chip cache, typically more than one level. This takes a lot of die area; static RAM is generally reckoned at six transistors per bit.
That having been said, the preponderance of area taken by static RAM, is not quite what you would expect just from raw transistor count; such a regular structure takes less area per transistor than the random logic constituting the rest of the CPU.
Roughly how much denser is static RAM than random logic? Would it be approximately accurate to say that it typically takes half as much area per transistor, or a third as much?
AI: You can get a very rough idea from the published transistor densities, with the caveat that real products are often dramatically different then isolated cells. For example, TSMC 7nm has a 0.027 square micron SRAM cell. That's 222 million transistors per mm square:
https://en.wikichip.org/wiki/7_nm_lithography_process
Conversely, they claim only about 90 million transistors per mm square for logic, so more than double the density. |
H: Output behavior of CMOS
Assume a CMOS-cell, which is an inverter(?) here and hence, the input is connected to both transistors, but please let's treat the transistors independent from each other.
V_0 = 5 V, when upper transistor is conducting and lower not.
V_0 = 0 V, when lower transistor is conducting and upper not.
What is V_0 in case both are conducting?
AI: The transfer characteristic of a CMOS inverter would look like this:
Since we are leaving the realm of digital signals, it is not a matter of which transistors are conducting, but rather how much the individual transistors are conducting. So strictly speaking, both transistors are conducting for most of the input voltage range shown in the graph. The exact voltage depends on the input voltage and the specific transistor parameters.
A state of both transistors conducting significantly is not desirable since you effectively short circuit the supply voltage. Nevertheless this state occurs for a logic transition at the input, but only for a very short time. |
H: Newbie Assistance - Understanding Fairy Lights
I'm VERY new to EE and am learning the basics. My first goal is wiring up some small lights for my son's LEGO projects, and am trying to sort out the basics here.
Right now, I'm attempting to piece together a mental model of how wiring up several LEDs work, mostly vis-a-vis attaching them to an Arduino. I've run into several hurdles here (seemingly a simple project) and keep coming back to the simplicity of a small strand of fairy LED lights.
The output of the Arduino is 5v. I'm comparing it to a strand of fairy lights I have which take 4xAA Batteries, for a total of 6V.
I've read the following:
A white LED needs about 3V to operate, and requites around 20mA of current to have decent brightness.
Each pin of the Arudino can only output safely 20 or 30mA. Thus, I can only safely run 1 LED, maybe 2 if I'm feeling risky, per pin on an Arduino.. Even if they're in parallel.
AA batteries can output about 50mA constant current.. 4 AA batteries would be 200 mA, no?
At the same time, this little pack of fairy lights on 6V can run like 50 white LEDs with no resistor as near as I can tell.
So how does the magic of the fairy lights actually work? What am I missing? Why is it that trying to wire up 6 little LEDs to my son's LEGO house is apparently going to require six separate pin connections, each with a resistor, etc.
AI: Many LEDs, including some white ones, will make a decent light at far less than 20ma. I have some green and red ones that are unpleasantly bright at less than 1ma. White ones can be found that are relatively bright on 5ma. Some amber/yellow ones can also be ultra bright at 1ma. Red and yellow ones only take just under 2v each to light up, so you can put two in series for twice the light at the same current running from a 5v supply. Try maybe two ultra-bright reds in series, with a 1k resistor in series with them, and see what kind of light you get.
Batteries in series don't increase their current capability. Higher voltage should mean more current according to Ohm's Law but that doesn't make the internal resistance of each battery go down. 4 batteries in series, then, is also their 4 resistances in series: 4 times the voltage but also 4 times the resistance means no gain in current capability. |
H: What is the 0V reference for MOV's input protection on power supply?
In some application notes for MOVs I see example usage in power supply design where each input line (N, L) from the mains are protected with a MOV to a ground voltage reference (as well as a differential mode MOV protection between the input lines)
What I don't understand is what is the 0V "ground" reference these application notes are referring to?
It is both regulatory and practically impossible to use the PE (=FG) since even the smallest MOV current could trigger the earth protection circuit breaker.
AI: What I don't understand is what is the 0V "ground" reference these
application notes are referring to?
Well, despite you thinking this: -
It is both regulatory and practically impossible to use the PE (=FG)
since even the smallest MOV current could trigger the earth protection
circuit breaker.
The answer is still actually the "protective earth" (PE). If a surge causes a live-neutral imbalance current, then it may trip an RCD (UK) or GFCI (US). That cannot be avoided other than by designing the power supply AC interface to not require a protective earth point and hence it's impossible to utilize surge protectors connected to PE. |
H: Why does FPGA PCI Express Tx output have on-chip termination of 100 Ohm?
The Intel Cyclone IV FPGA supports PCI Express (PCIe) generation 1, and the IO standard for the Tx output is PCML at 1.5 V.
The Cyclone IV Device Handbook volume 2 page 1-13 describes that the Tx output supports 100 Ohm termination. The related figure is this:
I understand that termination is often used at the receiver end to avoid reflections.
Why is there termination at the transmitter end for the PCIe PCML IO standard?
AI: There is termination on the transmitter end due to the same reason, to terminate reflections that arrive back to the transmitter for some reason, and also to drive the 100 ohm transmission line at 100 ohm source impedance, as otherwise the current mode output would have extremely high impedance.
As PCIe lanes are AC coupled, it is also there to bias the current-mode driver output correctly as the output drive current is such that it requires double termination to output correct voltage swings. |
H: Why does diode keep conducting even after voltage across it is negative
consider single phase two pulse semiconverter asymmetric configuration.
simulate this circuit – Schematic created using CircuitLab
Note the high value of inductance L1.
Let a be trigger angle of SCR, which is greater than t = arcsin(E/Vs). Now the SCR will work from a to pi-t and maybe beyond if current does not fall below holding current. But would not the diode D2 turn off after pi-t because voltage falls below zero?
Why does using a high value of inductance allows current to flow in D2 beyond pi-t and upto pi+a ? Does the emf E play no role in switching off the diode?
What actually happens after pi-t to pi+a? I assume that D3 cannot start conducting before pi+t and SCR4 cannot start conducting before pi+a. So where does the inductor current go?
AI: The inductor's stored magnetic energy will try and keep current flowing through both itself and D2 by generating sufficient back-emf to forward bias D2. That's pretty much what an inductor will do in this situation.
Why does diode keep conducting even after voltage across it is
negative
You might think that it's negative but, until the inductor has pretty-much got rid of most of its stored energy, the diode will be kept forward biased (like it or not). |
H: PWM edges issue on a STM32F0 micro
I have a STM32F051R8 (STM32F0 discovery board) I am trying to use to generate a PWM using a timer and change the pulse width at runtime. My code is:
// configuration
htim1.Instance = TIM1;
htim1.Init.Prescaler = 0;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
htim1.Init.Period = 65535;
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim1.Init.RepetitionCounter = 0;
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
// runtime
if(HAL_GPIO_ReadPin (GPIOA, B1_Pin)) {
// Set The LED ON!
HAL_GPIO_WritePin(GPIOC, LD4_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(GPIOC, LD3_Pin, GPIO_PIN_RESET);
__HAL_TIM_SET_COMPARE(&htim1, TIM_CHANNEL_1, 750);
htim1.Instance->CCR1 = 65534/2;
} else {
// Else .. Turn LED OFF!
HAL_GPIO_WritePin(GPIOC, LD3_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(GPIOC, LD4_Pin, GPIO_PIN_RESET);
__HAL_TIM_SET_COMPARE(&htim1, TIM_CHANNEL_1, 500);
htim1.Instance->CCR1 = 65534/4;
}
My problem is the signal looks like this:
Why are the waves like that? I thought they were supposed to be square. Am I doing something wrong, or is there some kind of setting I must apply?
AI: That looks very much like a problem with the compensation adjustment on your probes.
Your scope should have a calibration signal output. Check that your scope shows a nice square wave when the probe is connected to the calibration output.
If the calibrstion output doesn't look nice and square with straight, vertical edges and flat, horizontal tops and bottoms, adjust the compensation screw on your probe to get the square wave square.
A digital output from a microprocessor should normally have straight edges and a flat top and bottom. If it doesn't then you either have too much of a load on it or the scope (probes) need to be adjusted. |
H: How can I determine PD for given impulse, based on transient thermal impedance for BJT?
I have (selected) a BJT to work with rectified mains application.
Transistor is PBHV9560Z (600 V, 0.5 A PNP)
https://assets.nexperia.com/documents/data-sheet/PBHV9560Z.pdf
Under normal operation conditions, this BJT can dissipate 0.5W without heatsink. Maximum current should be 0.5A.
One thing is not clear to me, I have a pulse of 9.64W (average) for about 100ms. Current is well in range but due to VCE of 260V, power reaches this level.
I'm not sure this is OK or not because datasheet don't specify a digested SOA (like for MOSFETs or other BJTs).
How can I estimate maximum allowable PD based on given transient thermal impedance for my case of 100ms?
Thanks in advance.
AI: Looking at this graph and assuming the duty cycle is low (say 0.05) then, the transient thermal impedance for 100 ms is 20 K/W: -
That means it would warm by 400 K (in 100 ms) and that would be unacceptable by a mile. Even if the duty cycle were virtually zero, the impedance would only drop to about 12 K/W at 100 ms and it would still warm by 240 K. |
H: Parallel resistor before voltage amplifier
For my project, I would like to amplify the output from a photodetector for subsequent analysis with an oscilloscope.
The output of the photodetector is a current. Since we are using a voltage-amplifier, we would like to "convert" this output to a voltage by having a resistor after the photodetector but before the amplifier. Would you recommend using a resistor in series (e.g. a 50 Ohm series resistor) or would you rather use a t-piece with e.g. a 50 Ohm termination?
It would be really interesting to know the difference between those two options.
Thanks a lot for your help!! :)
AI: You could do it like the first diagram. The input current generates a voltage across R1, which is buffered and amplified by the amplifier. Unfortunately, you run into a very nasty compromise if you want speed from this arrangement. The voltage on the input of the amplifier has to move, which means it has to charge Cstray. Cstray and R1 form a lowpass time constant on the response of the system. Choose a big R1 for lots of gain, or a small R1 for lots of bandwidth, but you sacrifice the other parameter.
Cstray is inescapable. Photodiodes tend to have a large self capacitance, even if you can reduce that of connectors and cabling, and the amplifier input.
simulate this circuit – Schematic created using CircuitLab
In the second diagram, the virtual ground connection of the second amplifier 'short circuits' Cstray to ground. The amplifier input node does not have to move. You can choose R2 for gain alone, the amplifier takes care of the bandwidth. Spend more on the amplifier, you get more bandwidth. This configuration is called a TransImpedance amplifier, as R2 defines the ratio of voltage out to current in. |
H: How to ensure signals from multiple different clocks are in phase?
I am designing a pcb where I have a signal of 10 MHz logic signal with 50% duty cycle that might be coming from different clocks. I will be using a pll frequency synthesizer to turn this into a 50% duty cycle 1 Hz signal. Is there any way I can ensure that the 1 Hz signal is initiated by the same rising edge from the 10 MHz signal in multiple setups? E.g. If I have two of these setups, each stemming from the same clock/clocks of significant precision and accuracy, how do I ensure that the two 1 Hz signals will always be in phase?
P.S. if anyone also has any suggestions or sources they can refer me to on how to build PLL circuits, it would be very appreciated.
I am a student with not much experience in electronics, therefore I apologize for any mistakes/poor communication of the problem.
AI: exactly per jwh20 in the comments:
Use a counter aka frequency divider (wiki link, see "digital dividers" section), from the common clock. You can divide by any positive integer value, not just powers of two. Look up "counter" IC's. If you are in a microcontroller, the same can be done with common on-chip timer/counter hardware.
With a ratio of 10e6 you will need 24 bits, if for any reason you are forced to use something with fewer bits, you can use multiple counter/dividers with fewer bits in series.
HOWEVER! as I overlooked, to get the 1Hz outputs in phase, a common trigger would be required to start the counting, which makes the benefit unclear. |
H: Define the purpose of these components in the operation of this low side driver
I am trying to understand the operation of the following low side driver circuit I found in a schematic of an old pinball machine (redrawn for clarity):
L1 is a Solenoid and Q1 is a Darlington BJT (TIP120).
What is the purpose of C1, R2 and D1 and how does it affect the
circuits operation?
What would be the likely outcome if C1, R2 and D1 where removed from the circuit?
If the 7407 open collector buffer and R1 pullup were removed, and assuming the MCU pin could supply sufficient current to drive the Darlington directly with the appropriate current limiting resistor, would C1, R2 and D1 remain unchanged?
AI: C1 helps keep Q1 from turning off too fast. D2 may not be enough to prevent the inductive kickback from harming the driver. Stopping current through an inductor more slowly limits the peak voltages produced. R2 helps pull the base of Q1 down so it can turn off completely since D1 prevents the driver from sinking any current from the base. D1 further protects the driver from voltage spikes, as well as providing a bit of voltage drop between the driver and the darlington so it doesn't conduct when it is supposed to be off. (As per SteveSh's comment, the 7407 may have up to 0.7 V on it's output when off).
A blown driver.
They should stay unchanged. If the MCU is not open collector (push-pull, for instance, which is common in MCUs) you will need a series resistor to limit the current. |
H: How much skew correction can typically be applied to DQS during DDR4 link training?
My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync.
Is there some standard (e.g. JEDEC-defined) limit to the amount of skew correction that can be applied to DQS during link training on a DDR4 memory controller? If there's no standard limit, is there a general ballpark timing correction range that DDR4 memory controller implementations typically allow for?
AI: A more thorough dig through the JEDEC DDR4 SDRAM spec revealed what I was looking for. The link training for correcting skew between DQS and CK is implemented in a feature called Write Levelling. The timing details for this are on pages 195 to 196 of the spec. The timing range for the write levelling output delay (tWLO) is specified as 0ns to 9.5ns for DDR4-2400. Timings for the other speeds are marked TBD in the copy of the spec I was able to find.
Beyond the spec, this article was very helpful in describing the procedure in further detail.
I was not able to find any information on typical tWLO values in practical implementations. 9.5ns seems like a very long delay considering typical DQS cycle times, so I would expect it to be far lower than that in practice. |
H: Parallel-series RC circuit
I wanted to calculate frequencies of filter
The module of impedance which I got is equal
What is the frequency cutoff of this circuit?
I've made a simulation but I wanted to get frequency cutoff.
AI: Passive transfer functions require an impedance ratio just as 2 resistors provide in series-shunt.
Here's an example with your 2 reactive parts creating 3 break points and -6dB above them all.
Use this as an example to check your homework. (20 dB /decade showing last break point at -9 dB.) This will also test your skills at reading log plots.. |
H: How Ethernet uses full bandwidth of the link if one host is sending more than one frame for different hosts?
I followed from this question.
We know that modern Ethernet is full-duplex. At the same time, we can send or receive the signal. Suppose I consider one LAN where multiple hosts are connected by different ports of switch.
Let's take Host A connected to switch port N via a baseband link. Consider if A starts sending its intended signal to switch port N for host B and C at the same time.
My question is: how does Host A use the entire bandwidth of that baseband link, despite it sending multiple signals (frames) for different intended hosts at the same time?
AI: The term ‘multiplexing’ means different things in different contexts.
Eg. WDM (Wavelength Division Multiplexing) is a method of using two (or more) different colored lasers to send the data on a common optic fiber. Magic optical techniques are used to combine and separate the different colors. In terms of data being sent down one laser color, it is serial (there are probably more advanced techniques used in the very fast telco stuff).
In the case of VDSL (Very high-speed Digital Subscriber Line), multiple bits are sent at the same time. Does this mean that packets for Google and Facebook are sent at the same time or that one packet is split into multiple channels? Either is possible, but the latter is more likely.
So we can talk of multiplexing sockets over ethernet and multiplexing bits over VDSL; two very different techniques with the same concept. So don’t conflate all uses of the term ‘multiplex’ to mean the same thing. And multiplexing does not imply many things at one time.
Think of transferring data packets like a courier system - eg. Fedex. You put your various bits in a box. Your box goes into a van with other boxes. The boxes go to sorting points to go onto different modes of transport. At the destination the boxes get sorted and your box gets delivered to the ultimate destination. The receiver opens the box and separates the various bits. That’s basically the internet. |
H: What Does This JFET Do If Vgs is Always 0V
I'm trying to understand this reference circuit that I found in the datasheet for a piezo accelerometer.
I don't understand what the purpose is if the gate and source are common. My best guess after some research is that the JFET provides a known impedance for the output.
AI: It is being used as a current sink.
With the gate shorted to the source the drain current will be Idss which is the maximum current through the FET under normal conditions. Since this current is nearly constant over most of the range of drain to source voltages it can be used as a relatively stable constant current source or sink.
The current can also be set to a lower value by adding a resistor in series with the source.
simulate this circuit – Schematic created using CircuitLab
You can get constant current 'diodes' that are basically an FET in a two pin package with the source and gate shorted internally. |
H: Trying to understand Integral nonlinearity in DAC/ADC
So here's the definition of INL:
it is mentioned (underlined in red) that one of the lines can be a line drawn between the end points of the transfer function but in (a) that line appears to pass in the center of the perfect transfer function and not in the end points, am i missing something?
Same thing happens here:
in this case the INL is defined as the deviation of the mid-points of the quantization steps between the ideal and real transfer function, where the ideal transfer function is exactly situated in the mid points of the perfect transfer function (not the end points).
In the first image there's also this:
"The name integral nonlinearity derives from the fact that the summation of the differential nonlinearities from the bottom up to a particular step, determines the value of the integral nonlinearity at that step."
How so? If i add the previous 2 errors in the last image i provided here i will get the next error?
Also in these 2 images :
Why is the Vlsb measured equal to the difference between two digital voltages divided by 2n -2 in ADC, why not just 2n?
Why is INL only defined for 2n - 1 points for ADC and 2n points for DAC and DNL only defined for 2n -2 for ADC and 2n -1 for DAC?
And last question is related with the picture below:
Why does the ADC only have 2n -1 voltages?
AI: It is important to consider how DNL and INL are measured for DAC and ADC devices.
For a DAC, each point in the transfer function is determined by measuring the analog output level at each DAC code. There are \$2^N\$ codes and \$2^N\$ resulting analog output levels.
Since INL is defined by the difference between measured and ideal outputs for each code, it is defined for \$2^N\$ points, between code \$0\$ and code \$(2^N-1)\$.
DNL is determined by the difference in the measured outputs for two adjacent codes (denoted as codes \$n\$ and \$n+1\$ in the equations in the question). The last defined DNL point is determined by the difference between codes \$(2^N-2)\$ and \$(2^N-1)\$, since \$(2^N-1)\$ is the last defined code. We can see that, at the full scale of the DAC, \$n\$ corresponds to code \$(2^N-2)\$ (and \$n+1\$ corresponds to \$(2^N-1)\$). Thus, DNL is defined when \$n\$ is in the range of \$0\$ and \$(2^N-2)\$.
For an ADC, measurements are made by observing the locations of the transition points between codes. An ADC with \$2^N\$ codes has \$(2^N-1)\$ transition points.
Note: Transitions can be located by observing when the digital output is toggling between two adjacent codes. This can be accomplished by using a variable analog input source (often controlled by a servo loop) and determining the transition points. (Transitions may also be located statistically using a histogram test, but that is outside the scope of this answer).
For an ADC, the INL is defined by the difference between the measured transition point and the ideal transition point for each transition. Since there are \$(2^N-1)\$ transitions, we have \$(2^N-1)\$ defined INL values, in the range of \$0\$ and \$(2^N-2)\$.
The DNL is determined by the measured difference between two adjacent transitions and the ideal difference between those two transitions. Because there are \$(2^N-1)\$ transitions (numbered \$0\$ to \$(2^N-2)\$), the last defined DNL point is based on the difference between transitions \$(2^N-3)\$ and \$(2^N-2)\$. So, in this case, \$n\$ corresponds to transition \$(2^N−3)\$ and \$n+1\$ corresponds to \$(2^N−2)\$). Thus, DNL is defined when \$n\$ is in the range of \$0\$ and \$(2^N-3)\$. |
H: Light to Sound Device
I need a device that coverts blinking light to sound. What device would this be or called? Can this be done simply without soldering?
AI: Without soldering the next best thing is breadboarding, which is for usually for prototyping but can be permanent if you're careful with not disconnecting anything from it. You will need an LDR (light dependent resistor) in a voltage divider and a transistor to power a piezo buzzer. Take this circuit and replace the LED with a piezo buzzer build-electronic-circuits.com/ldr-circuit-diagram There are plenty of tutorials on how to breadboard on YT.
It might also be worth seeing if you can just wire the piezo in parallel with the light |
H: Generate AC PWM using DC PWM LM741
Hi all, this is a LM 741 square wave generator. I want to modify it such that the dc input (PWM) (from 0V,5V) to correspond to the AC output (PWM) (from 5V,-5V). So, the dc input duty cycle should be the same as the output duty cycle of op-amp. How to modify this op-amp to do this task?
Thank you
AI: Sounds like you wanted to take the input PWM, turn it into an analog voltage (by a low pass RC filter), then turn that into PWM again (this can be done by comparing the voltage to a generated triangle wave), this would be only useful if you wanted to keep the duty cycle the same but change the frequency.
It will be so much easier to instead use an inverting amplifier to just change the voltage range. The gain needs to be -2 (0V,5V to -5V,+5V so double the range) and the non-inverting input voltage (Vref) needs to be 1.667V (calculated using the steps in https://www.ti.com/lit/an/sboa264a/sboa264a.pdf?ts=1647579746911 ) |
H: What is the purpose of these different-value capacitors?
I guess I am trying to figure out why we wouldn't just consolidate these into one single 22.11uF capacitor.
My initial understanding was that each capacitor was better at filtering certain frequencies, but the 22uF capacitor should theoretically always be better at filtering than the 0.1uF and 0.01uF capacitors.
Am I missing something?
AI: Each size of capacitor is good at filtering a particular range of frequencies of supply noise (since each capacitor has parasitic inductance forming sort of an LC band-pass filter), together they have a wider range. Good explanation by EEVBlog: https://www.youtube.com/watch?v=BcJ6UdDx1vg |
H: ks0108 vs NT7108 lcd controller
I need to replace a LCD display that has built in a ks0108 controller.
I have found a replacement that really fit all the specs (dimensions, resolution, maH, Voltage) but has a Neotec NT7108 Built in controller instead.
on the web i found this source:
http://serdisplib.sourceforge.net/ser/ks0108.html
that says that the 2 different controller are compliant.
I'm not 100% sure if I can replace a ks0108 with a NT7108 and/or if is going to be a problem of any sort.
"Compliant" would lead me to think that i won't have problems but the website is unknown to me and need to be sure.
I never have selected neither worked with displays before, so i need some help here. Thanks
AI: I had a look in the KS0108 datasheet and the NT7108 datasheet and they do indeed seem extremely similar.
They are pin compatible, have the same electrical specifications, timing specifications and the same set of instructions/registers.
They are basically the same chip from two different manufacturers. |
H: LM324N op amp not turning on if the negative input is above certain voltage
I built the following circuit (I'm using LM324N) and am having difficulty understanding why the op amp is not turning on.
Here are some more observations:
When the potentiometer is set to less than 4V, the led turns on as expected.
When I set the potentiometer to output around 4.2V and above the led turns off.
If I touch the the end of the potentiometer or the negative terminal of the op amp with my hand or a voltmeter the led turns on.
The output voltage of the op amp measures to be 0 when the potentiometer is set to 4.2V.
AI: The LM324N has an input voltage range of 0 to V+-1.5 V. So the upper limit of the inputs with 5 V supply is 3.5 V.
Your 4.3 and 5 V inputs are above this limit, so the OP amp will not work as you intend.
To solve this you could do one of the following:
Change to an OP amp with rail-to-rail inputs
Use higher supply voltage for the OP amp
Lower the input voltages, using voltage dividers or similar |
H: Active load vs active diode
It makes sense that when VGS = VDS, the channel resistance (lower slope) is large compared to the resistance in ohmic region (steeper slope,) so a MOSFET can be used as a resistor.
From a previous chapter I know that a BJT acts as a diode when the base is connected to the collector.
As I'm new to MOSFET circuits, I always compare MOSFETs to BJTs to understand better. Almost all the BJT circuits work just fine (logic/functionality wise) when we replace the BJT with a MOSFET.
Now it is confusing because with a BJT, the arrangement gives a diode fixing the base emitter drop to around 0.7 V.
Sith MOSFET, the arrangement gives just a resistor, not a diode.
Gate-drain shorted MOSFET gives a resistor, but base-collector shorted BJT gives a diode. Why?
AI: Now it is confusing because with bjt, the arrangement gives a diode
fixing the base emitter drop to around 0.7V. But with mosfet, the
arrangement gives just a resistor, not a diode.
It's all about the scale of things.
An NPN BJT with the base shorted to the collector looks like a diode with approximately 0.7 volt drop because; the forward-biased base-emitter region is basically a diode (a PN junction) with 0.7 volt forward volt-drop. Sure there are a few intricacies involved but, the bottom line is this.
For a MOSFET, the gate-source region is high-impedance and thus the gate-source voltage can rise (within reason) to cause drain-to-source conduction without any current flowing into the gate. Hence the volt-drop of an N channel MOSFET when gate connects to the drain is like a diode but scaled much bigger that a BJT.
The upshot of this is that the MOSFET appears more linear and like a resistor but, if you pushed the applied voltage a bit further it would start to behave non-linearly and more like a diode but, a diode with a much bigger forward volt-drop than that associated with a normal diode or a BJT. |
H: FFC USB Board Design
I'm working on two little pcbs to emulate a USB-C usb A cable by FFC. In the future I would like this designs on other PCB avoiding USB wires and connectors. For this, I want to test it with the next design: with other female USB A cable and checking if the FFC and minipcbs works fine. My question is: Would you add any usb protection to the female USB connector? Or for this job is this protection not necessary?
Thank you so much.
USB A schematic mini board.
USB C schematic mini board.
AI: I would probably add a TVS diode array to the superspeed lines.
The good thing about these is their pin layout often adheres to a "flow through" design, where the device goes directly over the superspeed lines without breaking the transmission line, meaning when prototyping, you have the option to test them with and without.
Something like a TPD4EUSB30DQAR.
Datasheet
Or Semtech's RClamp3346P, which includes protection for the USB 2.0 lines.
Datasheet
If you do use these, consider removing a GND cut-out underneath any SMD components to reduce parasitic capacitance.
One final comment - I would recommend adding some stitching vias near to your signal vias in the middle of each board, as the reference plane changes here (especially if these traces are superspeed) |
H: ADF4106 PLL output voltage lower than ATmega8A input voltage
I am working on making a frequency synthesizer getting ~900 MHz out of a VCO, using ADF4106 PLL.
Now, for programming the PLL, I am intending to use AVR ATmega8A microcontroller.
Everything is good, but the problem that I have stumbled upon is, the datasheet of Atmega8A says, minimum logic input high voltage is 0.6Vcc.
I intend to use 3.3 V Vcc. So, if I am right, the microcontroller needs minimum 1.98 V for appropriate detection of a high input, which seems pretty high for logic input.
Now the ADF4106 datasheet says, minimum output high voltage is 1.4 V. Which is ~0.6 V lower than the minimum needed.
I want to get a lock detect from the MUXOUT and read serial data. Now if the ADF4106 gets a lock detect or as part of serial data it gets the MUXOUT pin high, that is, raised to 1.4 V, what if my microcontroller cannot detect it as it is less than 1.98 V?
Is it that the minimum output high voltage that the ADF4106 mentions just the worst case, while generally it would actually be above 2 V? Or the ATmega8A should detect high input well at 1.4 V, it is just some worst case likewise? Or is it something I should actually worry about?
If it should actually be a concern, what should be the easiest way to overcome the problem? Or am I missing something or mistaking anywhere?
Datasheets of ADF4016 and ATmega8A:
https://www.analog.com/media/en/technical-documentation/data-sheets/ADF4106.pdf
https://ww1.microchip.com/downloads/en/DeviceDoc/ATmega8A-Data-Sheet-DS40001974B.pdf
AI: Use the CMOS output rather than open-drain with a pull-up to 1.8V, and a 3.3V DVdd power supply and you will have compatible logic levels. |
H: MOSFET switch not switching
I'm comfortable using BJTs but this is the first time I've used MOSFETs. I'm having to drive a larger current (>500mA) so it was this or using loads of BJTs to share the load.
I've created the circuit below:
It's to drive an electromagnet at 24VDC. The magnet has ≈ 200Ω so I represented that by the resistor R1.
When it's closed it seems to do what I expected, allow current to flow.
When I put the gate to ground though I expected the current to stop flowing (or reduce to a negligible level) however all I'm seeing is a small decrease.
AI: Try this:
What matters is the voltage between gate and source. This way you apply the 5V where it is needed. |
H: Why does my Push-Pull-Transistor blow up?
I'm currently working on a buffered voltage divider, followed by a Push-Pull stage to be able to source/sink up to 500mA per rail.
The whole thing will is powered by 36VDC, then it's split by half through a 10k voltage divider, followed by a NE5532 as voltage follower to stabilize the new center. This thing then runs through a push-pull stage using a complementary NPN/PNP package which then feeds into two voltage regulators, 7815 and 7915 for a +/-15VDC around the voltage divider reference.
My problem now is:
For some reason my push/pull package blows violently when I apply input voltage. The circuit works fine without it but the poor NE5532 is running really hot and is getting unstable under a bit of load.
Could somebody help me to find the reason for that behaviour? What am I missing here?
Link to dataheet of used NPN/PNP package: ZXTD4591E6 NPN/PNP SOT23
AI: Your op-amp is sophisticated enough to protect itself. However, your transistors are certainly not and, quite likely, you are (or will be) running them beyond their safe operating area (SOA): -
For example, if the upper transistor is dropping 15 volts (and it's highly likely to be more) from the upper input supply (in order to regulate), then the peak DC current that the upper transistor can pass before exceeding its SOA is about 32 mA. I've shown that as a red dot on the graph above.
So, I just made up this example but you can do the math yourself. Look at the graph above and place your own numbers on it. |
H: Can't use a polygon to define a board shape in Altium. How to do it?
I have this small single layer LED PCB I created in Altium, with a Polygon poured on the top layer defining the board limits.
When I try to create the board shape by using the polygon as reference, Altium says it can't find the complete polygon, and doesn't define the board shape based on it.
If I try to copy the polygon and convert it to its original primitives, all the primitives disappear.
I created the polygon by using arcs and tracks on the top layer.
Is there another way for me to define it as the shape for the PCB?
AI: Took me a while as well:
Duplicate the polygon, e.g. on a mechanical layer
Select the polygon, set fill style to 'none'.
Tools -> Convert -> Explode Polygon to Free Primitives (now you have a set of tracks)
Select all tracks
Design -> Board Shape -> Define Board Shape from Selected Primitives |
H: Decoding unknown UART
I'm struggling with a project here. I have an Elechomes EC5501 air humidifier that I want to make "smart". When taking it apart, I found out it uses a circuit board similar in most points to this one here.
But on mine, there is a 4-pin connector labeled "UART" that connects the humidifier with the display. By measuring I found out there is a 5V pin, a GND pin, and 2 RX/TX pins that enable communication between the user interface (display with touch buttons) and the main unit with ultrasonic + thermal humidification and the humidity sensor. I now built a small connector that goes between those plugs and has all 4 wires go out so I can measure on them. When rigging up my logic analyzer I get the following communication coming up every ~8 ms:
This should be the communication of the display unit asking for a sensor reading (Channel 1) and possibly what is the main unit's answer (Channel 0). What brings me to this conclusion is the Ch1 line going low just a few µs before the signal on Ch0 starting. Also Ch0 looks like DHT11-type answer code for me - long pulse = 1, short pulse = 0.
As you see, there is a significant long low-time on Ch1 in between (see red circle). This makes it nearly impossible for me to fit a UART analysis in in Saleae Logic without it throwing frame errors. What also makes me wonder are two thing:
1.) There are some very short pulses in between with a high-time of 600 ns. I think I can possibly just ignore those (see red circle).
2.) the shortest pulses I can measure besides on this line are 16-20 µs long. This would make a Baudrate between 50000 and 62500 - so possibly 57600? The strange thing is, although the display should just ask for values as I don't do anything on it, the codes seem to change a bit every time:
Those are 4 adjacent requests. Does anybody have an idea on how to interpret this?
If you want to have a closer look, the file is uploaded for viewing in Saleae Logic right here.
EDIT: Just realized the short pulses might still be important. It seems that there are 9 pulses transmitted on CH0, and then there comes a short pulse on Ch1, followed by a short pause on both channel before CH0 starts to transmit the next 9 (or, in one case, 10) bits.
There is a small IC on the bottom side of the circuit board with a SOIC-16 package, but without any labeling.
AI: Ok I think it is in fact I2C, Ch 0 = SCL, Ch 1 = SDA
Notable features of the waveform:
I2C has 9 pulses for each byte + ACK bit
the very short pulse you see might be the ACK bit. The master stops pulling the line low and there is an instant before the servant pulls the line low to acknowledge)
the start condition for I2C is SDA goes low, then SCK goes low, which is what we see
the stop condition is SCL goes high then SDA going high, which is what we see
Do you see a pair of resistors near the traces of this signal?
Decoding with Logic, the device address is always 0x50, the last byte is a checksum, which is the sum of the first 2 bytes in a burst plus 0xA0. E.g. 0x06+0x66+0xA0 = 0x0C (trimmed to 8 bits) |
H: Is there anything wrong with this SSR circuit?
I am a mechanical engineering student currently interning at a small company. We make solenoid valves and some tests require that we cycle the valves many times. This is a circuit that I came up with for an optically isolated MOSFET relay. Ideally, the IN and OUT voltages should be the same. The opto-isolator is triggered by an Arduino Micro. The purpose of the zener diode is to guard the MOSFET gate against overvoltage as its Vgs is +-30 V and it is possible that some solenoids will require voltages greater than 30 V. I have already tested a breadboard prototype up to 28 V and it appears to work as I expect it to. Is there anything incorrect, unnecessary, or bad practice about this circuit? Or is there a simpler way to do it?
AI: You need to add a reverse-biased diode across the solenoid terminals to absorb the EMF generated when the solenoid current is suddenly shut off. This is also called a "free-wheeling" diode or a "flyback" diode. It is needed to protect the MOSFET. |
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