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H: 555 NOISE BUTTON/ OP AMP
I have this circuit from the image below that I am designing myself.
part of this circuit is cut so 2 78xx is present.
This circuit is being designed and tested in parts.
This part of the circuit has to work basically by amplifying the signal from the electret microphone, as it will also work by sounding a siren sound generated by the 555 when the button is pressed.
The part of lm386 is ok, without noise.
the problem is when I connect output 3 of the 555 to one end of the button and the other to input 3 of the op amp;
the siren sounds very low in the background when I do this.
already tried to solve even with transistor and nothing solved.
does anyone have any tips on how can i solve this ?.
Thanks in advance
obs. I've tested it with other buttons, it seems that the buttons continue to drive even in cut
AI: Pin 5 of a 555 is usually 2/3rds of the 12V supply which is +8V. You can force it up to 11.6V and force it down to 4.4V. The output of the left side 555 driving yours forces it up to +10.7V and down too far to almost 0V. So attenuate the 0V to +10.7V down to 0V to +7.2V and capacitor-couple it into pin 5 of the frequency shifting 555.
Then the output level from the siren 555 will be WAY TOO LOUD and it will need its own volume control. |
H: Decoupling Capacitors: What happens to the DC on the cap once noise is introduced and it shorts?
simulate this circuit – Schematic created using CircuitLab
I've been using decoupling caps for a while now and I understand their purpose in keeping DC signals clean since capacitors allow high frequency signals through that get passed into ground and don't show up on the capacitor as built up charge in DC form, so they don't disturb the signal on the load.
What I've been wondering for a while is, if a random noise spike is introduced into the system from the power source or from an external source through capacitive coupling, what happens to the charge already stored on the capacitor? If the capacitor is fully charged to 1v as shown in the schematic, and it then instantaneously acts as a short to bypass the high frequency noise into ground, would a short show up on the load? Would the load have 0 volts applied to it in that instant? If this is the case, would the load not be disturbed in operation for that nanosecond in which the capacitor shorts? I'm just having a hard time understanding exactly how the capacitor can bypass charge and act as a short while still maintaining its charge built up from the DC source.
It's been explained to me in school that caps block DC but pass AC, but I feel like that on its own doesn't explain decoupling well enough. Thanks for your time.
AI: The capacitor does not "short out", it has charged up to a constant voltage by storing energy as electrical charge, and if something external tries to change the voltage over the capacitor, it means that more or less charge is needed to change the capacitor voltage up or down, and moving charges means is current flowing.
So in short, a capacitor wants to keep the voltage over it constant, and resists any voltage changes by combating it with current. So voltage spikes get attenuated because the capacitor uses energy of the spike to change charge, and the larger the capacitance is, the less the spike can change the capacitor voltage. |
H: Transformer switch off spike
From Wikipedia:
When a transformer, electromagnet, or other inductive load is switched
off, the inductor increases the voltage across the switch or breaker
and cause extended arcing. When a transformer is switched off on its
primary side, inductive kick produces a voltage spike on the secondary
that can damage insulation and connected loads.
How to avoid transformer switch off spike and protect the circuit?
Is it something that we should be worried about for low power designs (e.g. step down 2A transformer)?
AI: How to avoid transformer switch off spike and protect the circuit?
It's a bit of a red herring for most loads because the induced voltage on the secondary is usually adequately "snubbed" by the load itself. This is how a flyback transformer works; energy is stored in the magnetic field of the core during the 1st half of the cycle and is released into the secondary on the 2nd half of the cycle.
So, a load would naturally "contain" the small amount of energy in the transformer's magnetic field should the primary become suddenly disconnected.
Having said all of the above, the wiki page linked in the question is entitled: -
Inrush current
So, given that the inrush current in a transformer can be significantly higher than its normal running current, some consideration should be made.
If the core is not saturating, the inrush current of the primary can be up to twice\$^{\text{NOTE 1}}\$ the normal-running peak magnetization current so, we should be wary of this doubling of current and note that if the supply were disconnected after half a cycle of the voltage being applied (that voltage being applied at a zero-crossing point for worst effect) we would witness a peak magnetization current twice as high as the normal peak of magnetization current.
Making a comparison is probably a good idea to put things into perspective. Imagine we have a 1 kVA 1:1 transformer supplying 250 V AC to a 1 kW load. The load current will be 4 amps. For a transformer of this size the magnetization inductance might be 10 henries. This implies that the "normal" magnetization current will be about 80 mA RMS. This has a peak value of 113 mA and, with the 10 henries inductance represents a peak stored energy of 63 mJ.
Given that the load (1 kW) is "handling" energy at a rate of 1 joule per millisecond I would say that most normal loads will survive the extra surge energy of 63 mJ (or 4 times that if the primary is disconnected at the worst possible moment during the worst case inrush scenario.
Is it something that we should be worried about for low power designs
I'd be concerned but not worried AND I would simulate the worst case scenarios to see what problems might occur. This is the power of simulation.
\$\text{NOTE 1}\$ - if the core saturates, then the inrush current can be very much higher than twice but, because the peak flux is clamped by the effect of saturation, it is sufficient to analyse the non-saturating situation (in my opinion). |
H: Why is actual SOC of a battery actually higher than what is displayed
So I read a document today which said that a higher SOC level (around 20%) is displayed as 0% to the user in vehicles, thus reducing the total capacity of the battery.
My question is that why is that done? Why do we limit the depth of discharge? I know for some batteries like NiMH there are memory effects, but why do we do it for other batteries like Li-ion?
AI: The further we discharge lithium batteries, the more damaged they get (a deeper discharge is equivalent to a higher cycling count). This is particularly true for a very deep discharge, where battery voltage decreases rapidly:
Image source: batteryuniversity.com
Keeping the user from discharging the battery to this extend increases battery life time significantly, while not shorting the runtime of one battery charge too much.
I can't say if in practise it is really as much as 20% of capacity left (this seems like quite a high value), but a certain "safe guard" will keep the battery from going into deep discharge, from which it might not even be able to discover (imagine a user completly discharging the battery and then leaving the device off for several days without recharging. This would surely damage the battery. Shutting down the device at a few percent capacity left will reduce this risk a lot).
The same is true for the upper end of the charging process: If a lithium ion battery is charged to more than 80% the wear of the battery increases. Limiting the charging process to 80% can increase the life time significantly, because the damage done to the single cells when charged to more than 4 V increases as well.
Regarding your comment to memory effect at NiMH:
This effect is quite opposite: You want to discharge these batteries as far as possible, otherwise you will reduce their capacity. |
H: Car battery voltage readings different with no load - normal?
Typical car battery, 12V. While connected to the car, It read 12.38V on my multimeter. Using the absolutely same multimeter, I measured it once I disconnected it from the car - voltage went to 12.56V. This is in the span of 5 minutes. First measure was taken outside at 1C, second at home at 18C.
Car sat for 1 week straight before disconnecting it. I charged it and reconnected, after sitting for one day voltage was back to 12.4V, thus I eliminate some sort of crazy parasitic draw as else after 1 week it would be dead, not same as after one day.
Is that type of drop to be considered normal?
AI: Yes, this is perfectly normal. A battery has an internal resistance. When you add a load on to it, it becomes a resistor divider.
For example, assume you have a 12V battery and it read 12V exactly when measuring it. Imagine this battery has a 0.2 Ohm internal resistance. You then add a load of 10 Ohms.
Use the voltage divider equation [Rload/(Rbat+Rload)]*Vbat = 11.76V
This is why you get a variation in voltage measurement when you measure it with and without a load. Other environmental factors can play a part, such as temperature, but the main culprit in many cases I think you will find is the internal resistance. |
H: Number of independent KVL and KCL
I know that the number of KTL and KCL is related to the number of nodes \$N\$. For KCL there are \$N-1\$ equations while for the KTL there are \$L-(N-1)=L-N+1\$ equations. However I didn't understand how calculate \$L\$. Is it the number of elements in the circuit ? Is it the number of branches of the circuit ?
Consider the following example:
simulate this circuit – Schematic created using CircuitLab
The solution given for this circuit has 2 KTL equations and 1 KCL equation.
For the KCL is straightforward because there are only \$2\$ nodes so \$2-1=1\$ equation. For the KTL \$L-2+1=2 \Rightarrow L = 3\$. Why is that ? Should I consider only the branches entering one node ? That is \$(V1, R3)\$, \$(R2)\$ and \$(R4,R1,V2)\$ ?
Another way to figure out the number of KTL equations is by identifying the number of independent meshes. I can only see 2 meshes in this circuit but for a complex circuit how can get this value ?
AI: As Huisman explained on his answer, in KCL we have (N-1) independent equations and for KVL (L-N+1) independent equations.
But in the comments you said:
If L is the number of elements in the circuit then 6−2+1=5≠2. L must be 3 for this circuit otherwise the equation is not satisfied.
There aren't only two nodes in the circuit. The definition, as explained here pg. 6-7, is:
Branch: Represents a single circuit element.
Node: Junction point between two or more branchs.
Mesh/Loop: Closed path without repeating any nodes.
With that, we get a total of 5 nodes. You can check in the same link above the Fundamental Theorem of Network Topology to see if the values of branches, nodes and meshes you found are correct. (Yeah, this question is related to graph theory...)
Notice that in KCL you're gonna set one of the nodes as reference, that is why in this method you can find (N-1) independent equations.
__
Another way to figure out the number of KTL equations is by identifying the number of independent meshes. I can only see 2 meshes in this circuit but for a complex circuit how can get this value ?
If a mesh has a branch that belongs exclusively to her, then she is an independent mesh. In a planar circuit, you can always get (x = number of independent meshes) equations to solve.
__
Should I consider only the branches entering one node ? That is (V1,R3), (R2) and (R4,R1,V2) ?
That's one way to simplify the calculations, depending on the circuit. For the given circuit, you can reduce it to one nodal equation and find the voltage at the node shared by R2, R3 and R4. With this variable, you can find all the other parameters. |
H: How does an LC network enable a shoot through state for an inverter
I was researching about inverters when I came across the Z source inverter. The Z source inverter is unique in a sense that it enables a shoot-through or a short circuit condition by closing any two switches of the same leg. This would not be possible in a traditional inverter as such a situation would cause the switches to get damaged. But a shoot-through state in a Z source inverter is possible due to the presence of the so called "LC" network. My question is this:
1) How does the LC network prevent any damage of the switch during the short circuit stage?(this is similar to a boost converter when the inductor charges during the 'on time' of the switch in a standard PWM. The closed switch and the inductor effectively creates a short circuit but there is no damage of the switch).
2) What is the use of connecting the capacitors in an "X" like fashion in between the inductors?
AI: How does the LC network prevent any damage of the switch during the
short circuit stage?
I prefer this schematic for a Z source converter because it contains the all-important diode (red circle): -
That diode is important because without it, when T1 / T2 and/or T3 / T4 turn-on to create the shoot-through condition, energy stored in the capacitors would be lost instead of being "allowed" to produce double the supply voltage. Maybe it might be easier to see it if re-drawn: -
simulate this circuit – Schematic created using CircuitLab
In quiescent conditions node A will be at 100 volts and node B will be at 0 volts. Node C will also be at 100 volts (assuming an ideal diode)
When the switch closes (representing the shoot-through condition) the capacitors are placed in series and so node C suddenly rises to 200 volts and reverse biases the diode. This means that the applied input voltage to the inductors is twice as high. As shoot-through progresses the current ramps up as per a normal booster circuit but with potentially twice the input voltage.
What is the use of connecting the capacitors in an "X" like fashion in
between the inductors?
Hopefully, with the redrawn diagram you should be able to see that now. |
H: AVR: Why doesn't my if statement yield TRUE?
int i=0;
DDRD = 0xff;
PORTC = 0xff;
while (1)
{
if(PINC5 == 1)
{...}
I have been trying to figure out why the comparison of PC5 pin of PORTC with 1 yields False everytime. I have activated the "pull up" resistor for every pins of Port C. But still, when I compare the PC5 to 1, I don't get the expected result.
I know the proper way is to do the comparison using the bit-masking.
if((PORTC &(1<<PORTC5))==0).
But I can't figure out why the code presented above doesn't work.
I feel like I am missing some fundamentals in bit-wise operators but can't figure out what exactly. Thank you!!
The datasheet of Atmega 328P says the following:
All registers and bit references in this section are written in general form. A lower case “x” represents
the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn.
AI: PINC5 and PORTC5 are defines that equate to 5. So the code does not read status of pins of IO port C at all to get the status of the bits, it is just comparing if number 5 is number 1 and it never is. Also, PORTC is the output data register. If you want to read status of a pushbutton, you must read PINC register. |
H: Why is reading the 3T1C DRAM cell not destructive?
Could anyone help explain how the above 3T1C DRAM cell works? T means transistor and C means capacitor. Why is reading it not destructive?
AI: During a read T1 is off and T3 is on.
Then T2 controls the read line from the charge on the capacitor. Since it’s gate is very high impedance, no current is drawn from C to do that. That leaves C’s charge, hence the state of the bit, unchanged.
T2 is both the strength and weakness of this cell design. Yes, it makes readout nondestructive. But it also takes up significant space, increasing cost. As system design advanced to handle destructive reads, this design became disfavored. |
H: How is the propagation delay of a logic gate affected by the amount of inputs (fan in)?
I was trying to find out what parameters affects propagation delay and how.
When trying to discover if somehow the propagation delay could increase with the increment in the amount of inputs in a gate, I found this paragraph in section 5.7.1 of INTRODUCTION TO DIGITAL SYSTEMS by Mouhammed Ferdjallah:
"The fan-in is the number of inputs of a logic gate. For examples, a two-input AND gate has a fan-in of 2 and a three-input NAND gate has a fan-in of 3. (...) If the number of inputs is increased, the parasitic capacitance and thus the propagation delay is increased and the noise margin is lowered. Normally, the propagation delay increases as a quadratic function of the fan-in."
I'm trying to:
Find other sources that confirm that the number of inputs in a logic gate increases its propagation delay following a quadratic function.
Understand why do the parasitic capacitance increase. In a CMOS NAND gate, no matter how many inputs you have, each input drives only two transistors, one PMOS and one NMOS (in the book this section is just after the "CMOS Logic Networks" section).
AI: I can only answer in the context of standard CMOS logic gates.
For NOR and NAND gates, as the number of inputs increases you also increase the number of transistors that are connected in series. NAND gates of \$N\$ inputs have \$N\$ NMOS transistors in series while NOR gates have \$N\$ PMOS transistors in series. The series transistors have essentially the same effect as series resistors...they increase the time required to change the voltage on the load capacitance. Now you could increase the width of the series transistors to compensate for this, but that would increase the input capacitance of the gate and just move the problem to the previous logic stage.
Increasing the number of inputs for a NAND or NOR gate also increases the number of transistors that are connected in parallel, with all of their drains connected to the logic gate output. This increases the internal parasitic capacitance of the gate, further exacerbating the slower transition time. More wiring is needed to connect all of these capacitors, so even more parasitic internal capacitance.
So, if the propagation delay is proportional to \$R\times C\$, and increasing the number inputs increases both \$R\$ and \$C\$ then you could argue that the transition time is proportional to \$N^2\$. I don't think the relationship is quite that simple (not precisely \$N^2\$) but it is certainly worse than linear. |
H: Simple circuit to power a 4HP 180 V DC motor
Overview
I'm trying to make a cheap simple circuit to power and control the speed of the motor. It's going to drive a pulley and be used as simple woodsaw.
Problems
Running the motor without a resistor makes it lose control going too fast and smelling like burnt even when the dimmer is set to 120V
Running with the resistor makes the resistor smoke
Ideas
I may need to change the value of the resistor, or change it for something else to control the current, that's my question: What would fix this circuit ?
Schematic
AI: Not Feasible
This linear method dissipates 50% of 3kW Motor power at maximum power transfer.
Any attempt to apply full voltage on a stationary motor also only sees the motor winding DCR which results in up to 10x surge current initially ( or a fried resistor)
You need to buy a Motor Speed controller that matches your need to accelerate as a fraction of max acceleration which is 30kW initial power!! Some physics skills needed here. |
H: Push button for different actions in every press?
I'm trying to learn some electronics and I have something in mind that I don't know if it is possible to achieve.
I've worked before with micro-controllers (Arduino, etc) and I know I would be able to do this with code, but I would like to know if this is possible without any code/micro-controller.
I would like to have a push button and 3 LEDs.
First time you press the button, first LED will light.
Second time you press the button, second LED will light (and the first one will be off).
Third time you press the button, third LED will light and the second one will be off.
If you push it again, every LED will be off. And then the process will start again with every press of the button.
I hope I was able to explain it correctly
Is this possible??
Thanks a lot.
AI: Yes this is possible to implement with digital logic chips. The circuit requirements that you describe would require a state machine design that has four states, one for each of the LED on states and one for when they are all off. One possible design would use four D-type flip-flops designed to be connected into a chain to permit one flop to be set at a time whilst the others are cleared. Another design would require just two D-type flip-flops to count in binary as 00, 01, 10 and 11 cycling back to 00. Appropriate logic gates would then be used to decode states 01, 10, and 11 to turn on the three LEDs.
There are some specialized counter chips available that can make this digital design take less parts than a discrete gates and flip-flops design. One such chip is the 74HC4017. This specialized counter has ten outputs with only one active at a time. Clocking the part from a debounced transition of your switch would advance the active output to the next one. Since you only want four states as opposed to ten then you will have to arrange some additional circuitry such that when the counter has advanced to the fifth output active that wraps back to the master clear input to set the counter state back to the first state.
In the end this problem is easily solved with a microcontroller as you commented to in your question. The MCU can do much more that the discrete circuit in that you cam easily change the state sequence design of the LEDs if you so desire at a future time. It can also take care of debouncing the switch. |
H: Offset Voltage at Op Amp Inverting Terminal
I'm using ADA4350 as a transimpedance amplifier with various gains for feedback paths (30 ohms,3k,300k and 3 mega ohms respectively). When I give a constant current source of about 23mA as input to it, the Inverting terminal of the op amp at the first stage gets an offset voltage of 0.4 volts (ideally, it should remain at 0 volts, thus following the non Inverting terminal). However, when I give a constant current source of 15mA and 19mA , there is no offset voltage at the Inverting terminal. I saw in the datasheet that the absolute maximum rating for INN pin is 20mA. But I am confused about what this means. Does it mean that I can not use a constant current source of more that 20mA if I use an arrangement as shown in figure 61 in the datasheet?
AI: Datasheet indicates for +/-5V supply :
Linear Output Current P1 or M1, V OUT = 2 V p-p, 60 dB SFDR 18 mA rms (Typical)
Only 9mA for single 5V supply.
So 20mA is pushing the design limit. If you need more current than specified, add complementary emitter followers inside the feedback loop. This also avoids the self-heating of the Op Amp under such loads of 100mW range.
This has nothing to do with the Absolute Maximums
Input Current (IN-N, IN-P, VIN1, RF1, and REF) 20 mA
Any time the differential inputs are non-zero (within offset range) the outputs must be current limiting or saturated to rails.
warning* I just noticed in comments you are using +/-14 or 28 V when the max is 14V or +/-7V.
ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter Rating
Analog Supply Voltage 14 V |
H: Current going into the positive pole of a battery while discharging a capacitor
Please bear with me if this is a fundamental question.
Let's suppose we have an RC circuit, charging a capacitor up to the voltage of a battery of 9V. The capacitor is currently at 9V, we switch the 9V battery with a 3.3V one.
Because of the difference in potential of 5.7V between the capacitor and the battery, does current now flow into the battery?
What are the dangers when this happens? Am I trying to charge it at this point?
AI: Yes, current will flow into the battery, and in a sense you are trying to charge the battery.
The possible danger is that the battery is not designed to be recharged, or that the value of \$R\$ is not high enough to limit the current to a safe level. In either case there is the possibility of damaging the battery, perhaps causing a fire. |
H: PMOS unexpectedly passing current with capacitor on drain
I am designing a circuit to get a pulse when a switch opens. When the voltage source V1 is connected, the switch SW1 starts closed. I want Vout to briefly go high when SW1 opens. The circuit I designed looks like this:
simulate this circuit – Schematic created using CircuitLab
However, I get the opposite behaviour to what I expected when the circuit is turned on. When SW1 is closed, I would expect the drain of the MOSFET to be at 0V and pass no current. Instead, it charges the capacitor up to 2V. Then when the switch opens, the capacitor is already charged, and I don't get a pulse. According to the theory I read, when the MOSFET vSG = 0V then iD = 0A. Why is current flowing; do I need a more sophisticated model?
AI: Is this a simulation?
The leakage current from the MOSFET will charge the capacitor - it is probable that the simulator waits for conditions to stabilize before you get to time zero.
I suggest putting a resistor from the drain to ground. It can be fairly high, eg 1 megohm, to bypass the leakage current. You will also need the resistor to discharge the capacitor and allow the circuit to produce a pulse the second time the switch opens.
Also, many simulators will not function correctly if any nodes do not have a DC path to ground. |
H: How to calculate the equivalent conductance of a circuit
I have the following circuit and I'm asked to calculate the equivalent conductance at the ends of the circuit.
The textbook gives the following solution: \$G_{eq}=\frac{1-\beta}{R}\$.
My question is: why does the generator have its own resistance?
AI: The equivalent conductance is
$$G_{eq}=\frac{I_i}{V_i}$$
where \$I_i\$ is the input current and \$V_i\$ is the input voltage.
If the generator changes the result of this calculation, then of course it changes the equivalent conductance. |
H: switching regulator output filtering
I am designing and building a power supply with TPS54531 switching regulators from TI. I am double LC filtering the output. The 5 volt PH output pin feeds a 9.2uH inductor, then to a 47uF ceramic capacitor then through a 0.47uH inductor and finally to a 15uF ceramic capacitor at the output. My question is where should the V_sense resistors connect, before or after the secondary LC filter?
AI: My question is where should the V_sense resistors connect, before or
after the secondary LC filter?
It should almost certainly NOT go after the 2nd LC filter because you'll turn the circuit into a power oscillator.
With feedback systems you have to take care of not introducing too much phase shift or delay or negative feedback (desirable) becomes positive feedback (turns into an oscillator).
The regular LC filter in a switcher introduces anything up to 180 degrees of shift and this is compensated by good chip design and compensation component selection. See this: -
9.2.2.6 Compensation Components
and this: -
8.3.7
Slope Compensation In order to prevent the sub-harmonic oscillations
when operating the device at duty cycles greater than
50%, the TPS54531 device adds a built-in slope compensation which is a
compensating ramp to the switch-current signal.
Note the parts about slope compensation. Adding another LC network within the feedback loop is asking for trouble. |
H: How to calculate susceptance of an inductor in series with a resistor
Given the following part of a circuit, I have to find the susceptance.
I know that the susceptance is \$B=-\frac{1}{reactance}\$.
I know that the resistor does not have a reactance, however, my textbook's solution is \$ B=-\frac{wL}{R^2+(wL)^2} \$. Why does \$R\$ come up in the solution?
AI: Well, the definition of susceptance is the following:
$$\text{susceptance}=\Im\left(\text{admittance}\right)=\Im\left(\frac{1}{\text{impedance}}\right)\tag1$$
In formula form:
$$\text{B}=\Im\left(\underline{\text{Y}}\right)=\Im\left(\frac{1}{\underline{\text{Z}}}\right)\tag2$$
So, we get:
\begin{equation}
\begin{split}
\text{B}&=\Im\left(\frac{1}{\text{R}+\text{j}\omega\text{L}}\right)\\
\\
&=\Im\left(\frac{1}{\text{R}+\text{j}\omega\text{L}}\cdot\frac{\text{R}-\text{j}\omega\text{L}}{\text{R}-\text{j}\omega\text{L}}\right)\\
\\
&=\Im\left(\frac{\text{R}-\text{j}\omega\text{L}}{\text{R}^2+\left(\omega\text{L}\right)^2}\right)\\
\\
&=\Im\left(\frac{\text{R}}{\text{R}^2+\left(\omega\text{L}\right)^2}-\frac{\omega\text{L}}{\text{R}^2+\left(\omega\text{L}\right)^2}\cdot\text{j}\right)\\
\\
&=\Im\left(\underbrace{\frac{\text{R}}{\text{R}^2+\left(\omega\text{L}\right)^2}}_{=\space\Re}+\left(\underbrace{-\frac{\omega\text{L}}{\text{R}^2+\left(\omega\text{L}\right)^2}}_{=\space\Im}\right)\cdot\text{j}\right)\\
\\
&=-\frac{\omega\text{L}}{\text{R}^2+\left(\omega\text{L}\right)^2}
\end{split}\tag3
\end{equation}
Because the total impedance of your circuit is a series circuit of a resistor, with impedance \$\text{R}\$, and an inductor with impedance \$\text{j}\omega\text{L}\$. So:
$$\underline{\text{Z}}=\text{R}+\text{j}\omega\text{L}\tag4$$ |
H: Deriving the small signal model of this transistor
Given that the current equation for a graphene transistor is given by equation (1) I'm trying to find the small signal model of the transistor.
$$(1)\space \space i_D(V_{GS},V_{DS})=\frac{W}{L}μ(C_{ox}V_{GS}+a)V_{DS}\\
i_G=0$$
Small signal models were always given in the courses I've had. So, a problem like this is unusual for me. I gave it a go though. I used the Taylor series around the bias point for two variables and ignored the non-linear terms:
$$i_D(V_{GS},V_{DS})=i_{bias}+(V_{GS}-V_{GSbias})(\frac{\partial _{i_D}}{\partial V_{GS}})_{V_{GS}=V_{GSbias}}+(V_{DS}-V_{DSbias})(\frac{\partial _{i_D}}{\partial V_{DS}})_{V_{DS}=V_{DSbias}}\\
Δi=ΔV_{GS}(\frac{\partial _{i_D}}{\partial V_{GS}})_{V_{GS}=V_{GSbias}}+ΔV_{DS}(\frac{\partial _{i_D}}{\partial V_{DS}})_{V_{DS}=V_{DSbias}}\space \space (2)$$
I'm confident that this is the small signal equation for the current. However, this equation is causing me some confusion.
What is the transconductance gm and the resistance ro for this model?
AI: This is your general formula 2 which is valid for all fets which have source, gate and drain
The red partial derivative is the transconductance. The green one is the output conductance.
To get the actual transconductance formula calculate the red partial derivative from your model equation (it seems quite simple, like an ordinary silicon mosfet, I guess graphene transistors have more complex models) . |
H: Trouble starting a Constant Temperature Anemometer
I made a Constant Temperature Anemometer using this and this as reference. However, I'm having trouble in making it work properly. To get the circuit started I need the emitter voltage (Bridge Top) to be negative but can't seem to get it. No papers nor discussions i searched seem to have this problem. My questions are (details below):
I'm trying to find out what happened when a closed loop circuit like this has just turned on. Specifically, where should i start placing initial voltages to do analysis?
How do I achieve negative voltage at the bridge top to make the circuit work properly?
Should I change the 10k pot in the offset circuit?
When I tried this circuit, the bridge top has a positive value. This is a problem since the current booster is a PNP. The base voltage is 13V, which is above the emitter-base breakdown voltage. I assume the problem is because when I start the circuit, the initial voltage at bridge top is positive which is then amplified 1010 times and lead to saturation of the OPA37. I tried to circumvent this using a resistor between the emitter and collector like this circuit as well as placing a diode at the base like this circuit. However, it doesn't work and the bridge top is still positive even though the base voltage is already below 1V (I already replaced the transistor and verified the OPamps are not broken). Changing to NPN yields the same problem just different polarity.
I setup the offset circuit so that the pot can output voltage between ±5V using zener. However when I connected it like the circuit shown, it can't give the full ±5V range (it can't even go down to negative). I assumed the pot value is a problem due to loading effect, but TINA TI simulation proved otherwise. Not quite sure what's going on.
Note: I used a 1A ±15V Supply and a 1W resistor in place of hotwire to achieve the same condition as the simulation since it is quite complicated to factor in heat transfer. I did try using a Dantec Hotwire and have the same problem described above.
AI: The bridge should be about 10% of the emitter voltage pulled up by your operating offset.
This ought to be within the Vcm input range for desired output. But you can check that.
As far as phase margin and reactive compensation , we'll leave that for another question. |
H: Wired GFCI vs. 40v 5a battery use near spa
My wife has recently taken to running a cord out near our pool to watch TV. She's very careful, but I was thinking of doing what I can to make it safer, since the outlet in question is NOT a GFCI outlet (It's a standard US 110v outlet).
One obvious solution is an inline GFCI.
The other more expensive idea that occurred to me is using a 5ah 40v lithium battery that I can purchase a 300w inverter for.
My guess here is that if the wired TV were to go into the water, a GFCI would be better than nothing, but unsafe...whereas the battery would be practically speaking likely to be completely safe. Can anyone enlighten me as to which approach would be the safest, and if either or both is actually "safe"?
AI: My guess here is that if the wired TV were to go into the water, a GFCI would be better than nothing, but unsafe...whereas the battery would be practically speaking likely to be completely safe.
120v from an inverter is still 120v. If that goes into the pool, you could be injured or killed. Nothing about that is safe.
The whole idea of a GFCI is that if you drop something into a body of water, the voltage is interrupted once a few mA starts to flow, generally fast enough that you won't be injured. |
H: Desoldering a through hole capacitor with weird terminals
Apologies in advance if this is the wrong place to post this question.
So I've just RGB modded an old CRT TV, and now I'm trying to replace a series of capacitors to hopefully fix some screen geometry issues, and I've run into a little road block on a few of the larger high-voltage ones. The terminals on the underside have some sort of star-shaped grip that I've never seen before, and can't figure out how to detach them. I've been able to get some of the solder off with my vacuum desoldering gun, but I can't quite figure out the gripper part.
The replacements I bought on DigiKey (same capacitance/voltage rating, but the terminals are just thick stumps) don't have these, so I'm at a bit of a loss. Has anyone seen anything like this before? Thank you for your help.
AI: Nevermind, it was just some sort of rivet inside the hole; I was assuming it was all a single piece since it didn't want to fully desolder. I just needed to up the desolder gun's temp to get it to clear the hole:
(this one's a different cap than the first picture, but it's the same deal)
Thanks all for your suggestions! |
H: Make a Latching double pole single throw relay, using electronic components
I am latching a DPST relay. So I made a prototype using some transistors(ex. BC547) to enabling and disabling the latching. But I want to know whats the correct way of doing it. I have both 12V and 24V relays. And make a complete isolation to the micro controller.
AI: There are many possible ways of 'latching' a relay electronically.
The method below is one of many - whether it suits depends on the detailed requirement.
Input C will
latch the relay on when pulsed high,
allow the relay to remain in it's last "driven state when left floating and
Unlatch / deoperate the relay when pulsed low
Or, separate latch and unlatch inputs may be used.
Input B will
latch the relay on when pulsed high, and
not affect the relay when floated or held low.
Input A will
unlatch / deactivate the relay when pulsed low, and
not affect the relay when floated or held high.
The "sense" / polarity of any input can be altered by placing a simple inverter (similar to R4 & Q1) before the input.
Inputs A B C have to provide enough current to overcome the latching current provided by R3. D1 would ideally be a Schottky diode to allow input A to pull Q1-base low enough in all situations.
The relay is shown as SPST but may have other contact configurations as desired.
simulate this circuit – Schematic created using CircuitLab
Turn on:
R4 input high turns on Q1.
Q1 on pulls R1 low, turns on Q2.
Q2 on pulls R3 and relay high. Relay now on.
Q2 on via R3 turns or holds Q1 on.
Latch / float:
Any or all of of the following input states have no effect on Q1 which remains latched by Q2 via R3. Inputs :
C floating (high impedance),
A high or
B low
Delatch / Off.
Either of
- A low or
- C low
grounds Q1 base via R4 and as R4 is << R3 turns off Q1.
This turns off 2 and relay and pullup/latch path via R3.
For proper turn-off with A low, D1 should be a Schottky diode.
Then R4-left say 0.3V. Vb_Q1 ~= 0.3 + (Vcc-0.3) x (R4/R4+R3)
For eg Vcc = 5V
Vb_Q1 = 0.3 + 4.7 x 1k/(34k) = 0.44 V = OK
R3 can be larger if Vcc is larger, eg 100K for Vcc=12V
(Vcc = 12V, R3 = 100k, Vb_Q1 = 0.42V.
At higher Vcc levels, Dopt1, Ropt1 can be added for extra delatch certainty if desired. |
H: Exact meaning of the issue mentioned on Errata document
I am using PIC18F67K40. When I went through the Errata datasheet I found out that I am using A3 revision Device.
There is an item number 5.1
Can somebody explain to me what is the exact meaning of this?
I have added snap below
AI: This would only affect you if you are using the SMBus. The proper spec is as follow (from the datasheet):
In the errata the actual performance is described:
So it meets the SMBus spec if Vdd is > 4V. If Vdd < 4V (down to 2.7V) it may be as low as 0.7V.
In practice this would likely mean a reduction in noise margin rather than a failure, and only if Vdd < 4V, and only for SMBus inputs. |
H: Electronic Circuit Breaker
I want to protect from short circuit by using a miniature circuit breaker. But this has to be manually turn ON, when ever it is turned OFF. So I was thinking to make a electronic circuit breaker which cuts the power supply when ever there is a short circuit. And able to read the state of the circuit and turn it back ON using a micro controller. I am using 230V AC. And a Max Current of 16A.
AI: Something like this should work:
simulate this circuit – Schematic created using CircuitLab
The shunt resistor is 1 ohm, 1 A will cause 1 V voltage drop. set the maximum current allowed via non-inverting pin of the op amp. If voltage drop on the shunt is bigger than the reference voltage, op amp will drag it's output to negative rail and vice versa.
we configured the op amp as comparator, so the output is either high or low. connect the output of the op amp using a resistor to the digitalRead of MCU. in the program if the current is higher than what you set (digitalRead == LOW;), energize the relay and "break the circuit". you should put some delay in there too, otherwise it will keep connecting and disconnecting the relay. or you can manually connect the relay in case short circuit happened.
It's literally just four components, using miniature relays and SMD op amp/resistors it shouldn't be bigger than 4-5 centimeter.
Edit:
For AC current sensing you can use the same circuit except instead of using a shunt resistor to sense the current. Use an hall effect sensor and feed it's output to the op amp inverting pin:
ACS712 datasheet |
H: Measuring continuity on a car battery while connected - damage?
If you were to put both leads on negative and positive terminals on car battery while connected and have the meter on continuity (the one which beeps), what happens and can it fry/ruin the electronics in a car?
AI: It's unlikely to do the car electronics any harm at all. The car battery can put out hundreds of amps at 12V if it needs to. A weedy little continuity meter will have little effect on it.
But it could well fry the continuity meter if it's poorly designed. A better designed one will just go into overload mode. |
H: Simple circuit with resistors in series/parallel
Given the following circuit, I would like to find the time constant \$\tau \$. I know that at \$t\rightarrow \infty\$, the capacitor acts as an open circuit, so no current flows in it. In an RC circuit, \$\tau=R\cdot C\$, so R in this case would be \$R_1 + R_2\$.
However, given the same circuit written with Norton equivalent, I get \$R=R_1 // R_2\$.
My question is: what is the right way to find \$R\$?
AI: so R in this case would be R1+R2
No, R1 is not directly and uniquely in series with R2 hence that assumption is wrong.
The reasoning is simple; convert the voltage supply and series resistor (R1) to a current source equivalent. When you do that you'll find that the current source has R1 in parallel. And, if you look at your 2nd picture you can directly connect R1 and R2 in parallel.
So, when you reverse-convert the current source (in parallel with R1 and R2) to a voltage source, the new value for the voltage source series resistor is R1 || R2. |
H: Circuit/schematic review ATMEGA328P
Could someone suggest a place where I could request people to look over my schematic/board design?
If this is the place, here it is: https://easyeda.com/be.mihai22/project-hawk
EDIT:
As I see people started looking at this, here's what my thing looks like:
The three diagrams will form a circuit that will fly a quadcopter. It contains 3 ICs (accelerometer/barometer/magnetometer/gyro) for drone stability, one IC for detecting current/voltage.
What is more, it has an interface for raspberry pi zero which will generate + communicate a PPM signal (like a receiver) from 4G/Wifi.
I will also keep a list of things that you have suggested for change in this header:
Problems:
1. Sourcing 12V directly into ATMEGA328P Many thanks to Ron Beyer
AI: I'll add it as an answer, since the comments are getting big...
You should not supply 12V to the ATMega328. 3V3 would be a better choice here so you don't have to use level-shifting on the I2C lines.
You are pulling up the reset to 12V, change this to 3V3 as well.
You have 2 different grounds defined. This can cause problems and you should probably decide to name them the same or connect them with a 0R resistor.
No reverse voltage protection on the voltage inputs
VDDA (analog reference voltage) should be filtered, you can use a ferrite bead for this
The LED's are using 10K resistors, which may be too high for the 3V3 voltage, they will probably be so dim you can't see them.
The Inhibit pin on the LDO should be connected directly to 5V.
The input capacitor on the LDO should be between 5V and ground, not Inhibit.
10K pull-ups for the I2C lines are probably too big. You should be using something in the 2.2K-4.7K range.
If you run the ATMega and the current monitor chips on 3V3 instead of 5V, you can eliminate the I2C level-shifting.
The HMC5883L should have a 4.7uF polarized capacitor on the C1 line.
VDD on the HMC5883L should have a capacitor placed close to the power pins.
Also, check the availability of some of your parts. The CSTCE16M0V53 looks to be obsolete/End-of-life. |
H: Spectrum of LEDs
How monochromatic is the light from LEDs? I want a set of light sources which will emit light of different wavelengths, as narrow a spectrum as practical.
How wide are the spectrums of typical LEDs?
AI: You will be getting a narrow band, many LEDs have width of about 20 nm at 50% down from the peak; other LEDs have quite a wide band. The datasheets for LEDs will give you a curve for those specific to a particular LED.
Here are the graphs of LEDs I chose for a scientific imaging project based on how narrow their bands were without resorting to exotic components. I wanted a selection of colours as narrow as possible (but cheap), and bought well-known manufacturers' parts with datasheets, which I summarised as follows:
(The 400 nm line is dotted because it was an estimate. The others were traced from datasheets and normalised to give same height.)
If you need narrower:
a laser will be better than 1 nm, and can be much much better. (Given as 0.85 in datasheet of cheapest laser at a distributor). Some "broadband" lasers have a linewidth of a few to about 10 nm (Wikipedia)
some extrenely narrow bandpass filters are available, such as astronomical sodium filter, which can have a typical bandpass of 0.05 nm. Be warned they can be extremely expensive. |
H: What is the actual purpose of having a copper foil layer in PCB?
Out of several layers that make up a PCB, one of them is a layer of copper foil (see image below), What purpose does this layer serve to the PCB?
Also, some PCBs have just one copper foil layer on either sides of the substrate and some other PCBs have two layers on on each sides of the substrate. What difference does having a layer on either sides or on both sides of the substrate make?
AI: The copper is etched into conductive paths between components to connect them electrically. Components are soldered from their terminals to the copper, to make firm electrical connection, and also to keep components mechanically attached to the PCB. The more copper layers there are, the more complex wiring is possible. |
H: How can 22 awg cable over 100cm deliver 3A
I wonder how 22 AWG cable e.g. USB-A to DC power jack with 100 cm length can deliver 3A.
Why am I asking -> Using this calculator (I hope its correct) by entering values 2% drop, 1 meter, 5V, 3A gives me output 16 AWG. And I am looking for right cable to get.
What I need is stable output 5V, 1.7A (top) over 1.5m from power bank which is capable of 5V/3A over USB-A in winter condition. I mean like max -10C (most likely about -2C)
What would you suggest? Power bank has two outputs USB-C/USB-A. I can use both connectors at same time. There is absolutely not possible to use AC/DC power source.
End of cable will be most likely soldered on-board to avoid contact disruption.
Device powered via cable is ESP-32 with some LED strips (outdoor usage with movement)
AI: My suspicion is that they've calculated the 3A capability based on the shortest cable they offer in that listing, which is 50cm. 0.5m of 22 AWG copper with 3A over it has a voltage drop of about 160mV, which is reasonable enough. At one meter, however, it's more like a 320mV, which is probably pushing it a bit if you're regulating 5.0V down to 3.3V with a linear regulator, because that reduces your headroom down from 1.7V to 1.38V.
However, if you know you're only ever going to run it at 1.7A max, you could probably get away with it. In that situation the drop would be more like 180mV (~3.6%) giving you about 4.8V to work with at the device, which should be fine for regulating down to 3.3V using an ESP32 board's onboard LDO.
Keep in mind that these are slightly conservative estimates that don't leave you much wiggle-room for operational variances, so I'd recommend trying to find a slightly thicker cable. Even 20 AWG would provide a marked reduction in losses, getting you closer to 100mV drop over a meter. |
H: Generating a current between 0 - 250 mA for a load up to 40 ohms
I'm trying to use a howland current source to generate stable current for a load which is =<40 ohms. The load does not need to be connected to groud. I can work with a DAC to supply the Vin (V3 in the figure), which would help me control the load current, however, I'd like to limit the voltage used as input to 12V if possible.
AI: Rather than look up some boilerplate circuits and not understanding how they work, try designing from fundamental principles and building up from there. It sounds like you want some voltage controlled current which can drive 0-250mA through a 0-40 Ohm load - not an unreasonable task. Keep in mind the functionality of an op-amp (approximately):
1) Inputs take no current
2) Output of op-amp limited to Vpower+ and Vpower- (for rail to rail OPA)
3) When there is a negative feedback path, OPA tries to keep V+ = V-
A very simple current source according to these rules can be derived:
simulate this circuit – Schematic created using CircuitLab
In the above circuit, V+ is grounded (e.g. 0 V). Because the OPA is in negative feedback via the load resistor (RL), rule #3 tells us V- = V+ = 0V. The current Ix = (Vref-0)/Rref via Ohm's law. Rule #1 tells us that the inputs of the OPA take no current, therefore Iy = Ix via KCL. We can conclude that the above circuit is a current source where the current through the load RL, Iy = Vref/Rref. Note the current doesn't depend on the value of the load resistor RL, making it a current source.
Now your first intuition might be to take this circuit and replace Vref with a DAC. Although this might work, most likely the DAC cannot supply enough current directly (e.g. the output impedance of the DAC is not negligible). However, from the analysis above, we can see another way to control the current, through V+, which in the above circuit is simply grounded. Modifying the above circuit this way yields:
simulate this circuit
We've replaced the V+ network (which was just a connection to ground before) with the D/A converter (Vin). Therefore, Vin = V+ and furthermore, because V+ is an OPA input, it draws no current so pretty much any DAC should suffice. How does this change the equations? Recall current Ix = (Vref-0)/Rref in the first circuit. The change means now Ix = (Vref-Vin)/Rref. The same applies for Iy, therefore your load current is Iy = (Vref-Vin)/Rref. Note that you can choose appropriate fixed values for your application for Vref and Rref, e.g. if Vin = 0 and you want the output to be 250mA, then you can fix Vref = 10V, Rref = 40 Ohm. Then you can vary Vin to adjust the output current. E.g. with the above configuration, Vin = 5V will yield 125mA, etc. Obviously Vin has an inverse relationship with the current, but it sounds like Vin is coming from some microcontroller/digital source, so that shouldn't be a problem.
Note that there is an additional issue of what the op-amp power needs to be (e.g. +/- 12, or +/- 15, etc). This depends on your maximum load resistance, as the limiting factor is how high or low the output of the OPA can go. If you understand the analysis I've given you, you should be able to go ahead and solve for that given your specifications. As a hint, you will need to apply rule #2 of OPAs.
The Howland current source has an additional constraint that the feedback resistor is fixed, rather than the feedback resistor being the load itself. Nothing in your problem description suggests that you need or want this, though I suppose some OPAs may require this. |
H: Small electronic project kit
I ordered this electronics project kit which consists of a small PCB. You have to solder the components onto the board.
The components are:
Two 510 ohm resistors (green, brown, brown)
Two 33k ohm resistors (orange, orange, orange)
Two transistors
Two electrolytic capacitors
Two LEDs
Power leads red to VCC and black to ground.
After assembling the circuit here is my result. The two LEDs light up.
The booklet does not state what the circuit is supposed to do.
Is two lit up LEDs all that the circuit is supposed to produce?
What would the schematic look for like this circuit?
AI: It's almost certainly an astable multivibrator, or LED flashing circuit, which is a classical circuit and one which is often a first project.
Here's a tutorial on one.
https://www.build-electronic-circuits.com/astable-multivibrator/
Try following the tracks on the bottom of the PCB and see if you can match it to the diagram in the tutorial I linked. |
H: Stall torque for servo
My understanding of stall torque is that it's the amount of torque produced by the servo when the output is stationary. Suppose the stall torque of a servo was 10kg-cm. It can lift the a 10kg load at 0.9cm but not at 1.1cm. But does it mean it'll actually drop the load at any distance greater than 1cm? That is, it'll drop the load at distances 1.1cm, 1.2cm, 2cm, etc.?
AI: But does it mean it'll actually drop the load at any distance greater
than 1cm? That is, it'll drop the load at distances 1.1cm, 1.2cm, 2cm,
etc.?
Generally yes, assuming the stall (holding) torque specification is accurate.
A servo with worm gearing may be able to hold its position even with no power. However even a worm drive can slip if enough force is applied. If the gearing supports a certain holding torque unpowered then it should support even more holding torque when powered (assuming it doesn't jump teeth or break).
Another definition of stall torque is the load that causes it to stall. In this case at higher torque the servo may continue holding its position, or it may be pulled off until the positional error drives the motor harder (typical behavior of 'analog' hobby servos), or it may 'drop' the load until torque reduces, or it may shut down and move freely due to detecting an overload (behavior of some 'digital' hobby servos).
Note that the torque specifications of 'hobby' servos are often 'optimistic', and may even burn the servo out if an attempt is made to operate it at rated torque. |
H: What would it take to add Bluetooth capability to a digital (musical) keyboard?
I am completely new to electrical engineering. I have a software background and have an interest in tinkering with hardware.
I'm wondering what knowledge/engineering skill/equipment is required to add Bluetooth capability to an existing keyboard. The keyboard I own is a Roland EP-9.
I know there is something to do with analog-to-digital conversions. But in terms of what data is being sent to the internal speakers, I have zero understanding how that works. The issue is "I don't know what I don't know", so I'm probably communicating this incorrectly.
I don't expect a full solution, but any links to helpful documentation is greatly appreciated!
Edit: For clarification, I just want the audio output sent to a BT speaker or headphones. Currently it is sent to an internal speaker.
AI: The engineer method would be a mux or digital switch or output from the IC8 Synthe Chip on the schematic to a bluetooth audio IC. Proper grounding, decoupled analog and digital power etc.
A hacker way would be to tap the IC11 D/A output at TP4 and TP3 to get the audio before the filter IC, and route that to an internal bluetooth audio module.
But the simple tinkering method is seeing that the piano already provides a method for line out and that line out to bluetooth adapters are cheap and premade. Headphone output would work too. Buying one is the best idea when you already have audio outputs. Or a headphone out to bluetooth adapter that you could even buy at a retail store.
At best you could cut the muting control for the IC19 output inverter (q15 and q14) so that you can mute the internal speakers without muting the line out, as they are tied together. Of course this involves tearing your keyboard apart.
If you want to learn, first step is to find the EP-9 service manual which has the schematic and block diagrams and learn what does what and how. I found the manual with a quick google search. |
H: What is a Current Source?
In EveryCircuit, they have a component called a "Current Source". For example, here is a circuit I've created with a 2A current source:
Is there a such thing as a 'current source' in the real world, or is this an abstract component that helps one regulate current (for example, without having to do a voltage source + resistor).
AI: There is no such thing as a perfect current source (or a perfect voltage source, for that matter), but things like batteries are closer to a voltage source than a current source.
There are a few devices that are more like a current source over some range of operation, such as a PV cell when loaded or some types of nuclear battery.
Usually in real circuits, voltage sources are some energy source like a battery or AC voltage connected to some parts that result in a fairly constant voltage over some range of current draw.
Similarly, current sources are usually some energy source connected to a circuit that produces a fairly constant current over some range of output voltage.
Here is a simple example of a (far from ideal) current source:
simulate this circuit – Schematic created using CircuitLab
As you can see from the simulation below, the approximately 1mA current is fairly constant for output voltages from 0V to 8V, above which it decreases quite rapidly. In actuality it will work fine for output voltages well below 0V as well. |
H: How to find the time constant of a RC circuit with dependent sources
Given the following circuit, I would like to calculate the time constant \$ \tau \$.
I know that in an RC circuit \$\tau=R_{eq}\cdot C \$.
I've also found out that \$\frac{d v_{c}}{d t}=-\frac{2-\alpha}{R C} v_{c}(t)+\frac{E(1-\alpha)}{R C}\$, where \$E=e(t)\$. Let's define \$\lambda=\frac{1}{\tau}\$. My textbook considers \$\lambda=-\frac{2-\alpha}{RC}\$, so that \$\tau=-\frac{RC}{2-\alpha}\$.
Instinctively I would simplify the resistors so that I can find \$R_{eq}\$ in order to find \$\tau\$, but I don't know if that would be appropriate. Also why \$\lambda=-\frac{2-\alpha}{RC}\$?
AI: It is easier to re-draw the circuit in a simpler representation to see if things are clearer:
Then, to determine the time constant, you turn the excitation off and replace the source by a short circuit. Redraw the circuit again in this mode:
To determine the resistance seen from the capacitor's terminals, connect a test generator \$I_T\$ which develops a voltage \$V_T\$ across its terminal. Determine \$\frac{V_T}{I_T}\$ and you're done:
You can see that \$R_2\$ is in parallel with the resistance we want. Temporarily disconnect \$R_2\$ to bring it back later across the intermediate result. The equation is \$V_T=I_TR_1+kV_T\$. Factor and reorganize to find that \$R=(\frac{R_1}{1-k})||R_2\$. A quick Mathcad sheet with a SPICE sim and the operating point confirms the result:
So, unless I misinterpret the controlled source symbol (a controlled voltage source I believe), the time constant is \$\tau=C((\frac{R_1}{1-k})||R_2\$). If both resistances are equal to \$R\$, the expression simplifies to \$\tau=\frac{CR}{2-k}\$
When you determine the natural time constants of a circuit, you always turn the excitation off and look through the energy-storing element's terminal what resistance \$R\$ do you see. That \$R\$ multiplied by the capacitor in this case forms the time constant. This is the basic approach I described in the book I wrote on fast analytical circuits techniques or FACTs. |
H: Why doesn't a short-circuit immediate consume all voltage?
If we assume a short circuit, with zero resistance (not even within the battery), would this 'infinite current' deplete all voltage within the battery? For example, if I "short" a 9V alkaline battery, it will run for about an hour (though the wire gets pretty hot, if not melts) until it depletes all its power. Is this only because the battery has internal resistance, or why does the battery 'keep running'? Additionally, does a battery ever give its Amp-hours or how long it can run?
AI: Because in the real world there is nothing such as a perfect wire or a perfect battery. There are parasitic resistances, inductances, and capacitances everywhere.
Plus there is the issue of the chemical reactions in the battery that is taking place to produce that electricity. That can only happen so fast even if you had a battery with zero parasitics.
Also, I find it pretty hard to believe that your shorted 9V runs for an hour. What is your definition of depleted? Batteries are considered dead long before they reach 0V in the same way you are too tired to do useful work long before you drop dead from exhaustion. I can only assume you are talking about reaching 0V across the terminals for purely academic purposes. |
H: How to determine what wire size to use
I feel like I have gone down a rabbit hole and came out knowing nothing. I understand this is a really basic question. My son and I are building a simple RC. It is using 4 1.5v (AAA) batteries in series. So if what I have gathered is correct that is 6v. What I cannot seem to figure out is what size wire should I get. I honestly thought this would be in the spec of the wire. Maybe I am not seeing it. I need a pretty good length and want to make sure before I go off and buy this.
I know there has to be a formula for this but what I am googling is not turning it up.
AI: normally I solid grab some scrap wire and see how it goes.
For AAA current will probably be less than 1A so AWG29 or fatter should be fine
https://www.powerstream.com/Wire_Size.htm
I'm looking at the chassis wiring column.
I would use AWG24 salvaged from an old ethernet patch cable (because I gave lots of that here) |
H: How to find the critical gain K from the root locus
I am going through Ogata's Discrete-Time Control Systems and working out the following problem found on Page 262.
The problem states:
Draw root locus diagrams in the \$z\$ plane for the system shown in Figure 4-45 for the
following three sampling periods: \$T = 2\$ sec
I first obtain the Z-transform of G(s):
and I worked all the way till the very end and calculated break-away and break-in points to arrive at:
and root locus:
However I am unable to calculate the critical value \$K\$ for stability (Answer is 1.4557).
I know I need to use the magnitude condition but I am not sure which value of \$z\$ I should substitute in the formula to obtain the critical value of \$K\$.
Any suggestions would be appreciated.
AI: The root locus, and the locus of \$\small \mid z\mid=1\$ are both unit circles. The centre of the \$\small \mid z\mid=1\$ circle is at the origin, and the centre of the root locus circle is at \$\small x=-0.5232\$. We need to find either one of the two complex conjugate points where these circles intersect, and we can then determine the value of \$\small K_{cr}\$.
Thus we have the two loci:
\$\small x^2 +y^2=1\$
\$\small (x+a)^2+y^2=1\$
Solving these simultaneously gives:
\$x=-\frac{a}{2}\$
Hence, the circles intersect at:
\$x=\frac{-0.5232}{2}=\small-0.2616\$
and the corresponding \$y\$ values are \$y=\small \pm 0.9652\$
Expressing this in complex form:
\$z=\small-0.2616\pm j0.9652 \$
Now substitute one of these values in the characteristic equation, and \$\small K_{cr}\$ is determined. |
H: Discharging a capacitor without a resistor
Is the following circuit considered un-safe? That is, can a capacitor be discharged with a bare wire connecting the two terminals, or should some resistance be applied? Why or why not?
Additionally, what are the more common ways used to discharge a capacitor?
AI: It's potentially unsafe. the high discharge current could damage the switch or even the capacitor.
1000uF charged to 12V is enough to make sparks and to weld fine wires. |
H: Controlling Multiple I/O Devices
How to manage multiple Input(Sensors like Temperature, Humidity, etc..) and output(like motors, relays, etc..) devices connected to a micro controller(Arduino UNO). There are more I/O devices present than the I/O Pins. I am thinking to use demultiplexer for controlling the outputs and multiplexer for Inputs, which are connected to the micro ontroller. But not sure how to connect them(micro controller, multiplexer/demultiplexer, Input/Output Devices). So, did I choose the right choice. if yes, how to connect those. if not, what is the alternative solution.
AI: Yes, your choice is right. You can manage more inputs and outputs with MC14051B, MC14052B, MC14053B. Link of the data-sheet is- https://www.onsemi.com/pub/Collateral/MC14051B-D.PDF
To increase output voltage-
To decrease input voltage use resistors according to the voltage divider rule. |
H: Why do we need interleaved memory?
I am trying to understand the DRAM working paradigm. I just read this article about interleaved memory. It says:
Interleaved memory results in contiguous reads (which are common both
in multimedia and execution of programs) and contiguous writes (which
are used frequently when filling storage or communication buffers)
actually using each memory bank in turn, instead of using the same one
repeatedly. This results in significantly higher memory throughput as
each bank has a minimum waiting time between reads and writes.
And...
That way, contiguous memory reads and writes use each memory bank in
turn, resulting in higher memory throughput due to reduced waiting for
memory banks to become ready for the operations.
My questions are:
What prevents a DRAM bank from being ready? Refresh?
Why is the throughput significantly higher with interleaving?
My current understanding is:
DRAM needs periodic refresh to keep the stored data, which is the the D stands for. For continuous read/write against a single bank, I can think of that such r/w operations will sooner or later collide with the bank's refresh operation. When that happens, the r/w will have to wait until the refresh is done. If we interleave multiple banks, it is less likely that the collision will happen. So there will be less wait and higher throughout.
But it seems my understanding is not quite relevant to the "waiting time between reads and writes" in the first quote.
Any other reasons?
Thanks.
AI: This isn't about refresh.
The bus may be running at a higher speed than a single RAM module allows. Then you either need wait states on the bus or interleaved RAM modules, so subsequent accesses —the most common— touch the first module, then the second module, the first again etc. The bus throughput almost doubles, given subsequent reads or writes are common. |
H: Generating more energy from a tree
My son is doing a Science Fair project on dc voltage from trees. We are only getting about 1 volt when they are put in series. He's in 6th grade, what is a simple way to increase the voltage ?
AI: Apparently voltage from trees is actually a thing. Who'd have thought.
This study suggest you need to use copper electrodes for the highest voltage. Power is not specified here.
Series connection of trees may not be possible because one of the electrodes is a ground rod.
To actually use this voltage you'd need an energy harvesting circuit. Of which there are some kits available. Silabs has one.
I'm unsure if I'm allowed to share the pictures of the research site here, see for yourself:
Hao Z, Wang G, Li W, Zhang J, Kan J (2015) Effects of Electrode Material on the Voltage of a Tree-Based Energy Generator. PLoS ONE 10(8): e0136639. https://doi.org/10.1371/journal.pone.0136639 |
H: AC line isolation on multi-level PCB design
Due to space limit I had to design the PCB in multi-level form, the top front side of the PCB is AC line and under that is DC capacitors:
Is the 3mm air gap between AC line and DC capacitors enough for isolation? if not should I place a 2mm plexiglass in between them?
Edit: considering the top capacitor pin and solder, the air gap is actually 2mm.
AI: Plexiglass is not a well defined term, 2mm of certain exactly defined and approved material such as polycarbonate
is ok. I guess you mean polymethylmethacrylate (=PMMA) when you say plexiglass, not some resembling trade mark. It can be used as well in this place.
Warnings
1) There should be also certain minimum route length along the surface of the insulator (=creepage). It can be for ex. 8 millimeters for 240VAC mains. The requirements vary with operating voltage, environmental conditions, mains overvoltage category level and the end application.
2) There are as well insulation requirements for the transformer.
You really should get the safety standards for mains AC operated equipment if you are building them.
BTW: is it possible to change the lengths of the spacers? Then no extra insulators would be necessary. |
H: How can I switch solar panels on and off with a microcontroller?
I have built a li-ion 18650 7S pack as my solar backup. It is being charged by 3*250W solar panels in series (about 105V 8A.)
My charger doesn't have an option to monitor individual cell voltages. It just charges the battery pack to the given voltage (4.2V*7 = 29.4V.)
I have a BMS monitoring my pack and if a cell goes above 4.2V it generates a signal which I monitor using an ESP32.
What I want to do is turn off solar side if cell goes above 4.2V with that signal.
Can Mosfet do this job or is there a better way to achieve this?
Note: The BMS has overvoltage cutoff but if I connect the solar charger through the BMS, it cuts off the battery power to the controller while PV side is on. The controller manual clearly say that cut PV before battery.
AI: What you are asking for would ideally be handled by a properly implemented charger and balancing BMS.
However, a somewhat informal but entirely doable way of shutting down solar input is to use a suitable rated MOSFET to short circuit the solar array - or a portion of it. The MOSFET MUST be either fully on or fully off.
The solar array is not harmed by short circuiting and dissipates minimal energy.
Power dissipation = I^2R. At 8A and say a 10 milliOhm MOSFET power in the FET
= 64 x 0.010 = 0.64 Watt.
10 milliohm Rdson MOSFETS are common and cheap and even lower or much lower Rdson devices are readily available. At that power dissipation heatsinking is trivially easy.
A relay could be used for the same purpose. However, opening a 100V 8A DC contact requires switches designed for the task. At those power levels the system is potentially lethal - both due to the voltage alone and also due to the arc potential.
Unless there was a good reason to run the panels in series at 100V+ I'd favour operating them in parallel at 35V.
Related:
Using 3 x 35V panels in series to charge a 29.4V max 7S battery pack sounds very strange UNLESS you have an MPPT controller. IF you have an MPPT controller that's (potentially) fine.
A BMS usually both detects cell overvoltage AND drains current from the charging source to prevent cell overcharging. As long as the battery is reasonably well balanced a balancing BMS will be able to handle the current needed to maintain balance. |
H: How to generate 100 A at 20 kHz?
I have interesting problem to overcome and seek some advice. I need to test different hall effect sensors and magnetic cores. I am currently stack at issue of bandwidth. I tested sensors at DC using 10 turn coil and 10 A DC supply. This approach proves challenging at 20 kHz due to power capabilities of most signal generators. Considering two solution building oscillators with frequency of 20 kHz using signal amplifier and multiturn coil with compensating capacitor or generating fast step signal to measure 10% to 90% raise time. Not sure which one would be more practical in terms of cost of overall equipment.
AI: Use a transformer with a single turn shorted secondary. I'd consider getting an RM12 pot core somewhat like this: -
And, winding 100 primary turns that can be driven from an amplifier that can produce 1 or 2 amp RMS, possibly an audio amplifier driven by your signal generator.
The secondary (single turn) should be made of copper bar (or braid) and bent into place.
A certain degree of experimentation will be needed i.e. you need to be careful with the power amp output and maybe put 4 ohms in series and adjust the gain knob carefully whilst monitoring voltages, current and heat.
It can be made to work in my opinion. Tuning capacitors at 20 kHz will be a limitation in a resonant application. |
H: I2C level shifting? 2N7002DW
Can someone explain the 2N7002DW? It seems to be a two-way N-MOS (it has two circuits in one).
I have a master device that runs on 5 V and multiple slaves that run at 3.3 V and they communicate via I2C.
Why is this necessary? Why, for example, would it not be possible to use the 3.3 V signals for the I2C bus where the master runs at 5 V? What are the dangers/problems associated with that?
Now let's assume I will run both the master and the slaves at 3.3 V. Is this the correct way to pull the I2C lines up?
AI: Can someone explain this IC?
This "IC" is simply 2 separate N-channel MOSFETs bundled in the same package. This package is connected in a bidirectional level shifter fashion (however your circuit is incorrect, see below) used to translate low-speed signals from one voltage reference to the other. More info can be found on the WWW:
https://assets.nexperia.com/documents/application-note/AN10441.pdf
How does a bidirectional level shifter work?
Edit - Incorrect circuit! (refer to Michael Karas's answer to know why is that)
Why is this necessary? Why, for example, it would not be possible to use the 3V3 signals for i2c bus where the master runs at 5V?
It is rare in digital circuit design that you can mix and match different signal levels between ICs with different supplies levels. Most IC design input/output level range will be a function of their supply VCC:
to interpret a "low" level, a very common formula is Vlow = 0.3 x VCC
to interpret a "high" level, the formula becomes Vhigh = 0.7 x VCC
In your case, if you ran the 3.3V level I2C into the VCC = 5V IC, here is what the later will see:
I2C low (about ground level ~ 0V) => IC reads "0" because Vin is under its "low" threshold which in this case is: 0.3 x VCC = 1.5V
I2C high (~3.3V) => IC still reads "0" (not "1" as you'd expect) because Vin stays under its "high" threshold which in this case is: 0.7 x VCC = 3.5V
What are the dangers/problems associated with that?
From 3.3V to 5V, the problem is the one I described above, you'll misread the I2C bus instructions on the 5V IC.
From 5V to 3.3V, the main problem is activating the 3.3V IC input protection diodes which clamps the input to VCC + 0.7V. Therefore it will push current from the 5V rail through the pull-up resistor into the protection diode of the IC back into its 3.3V rail. You can calculate how much current is going through the diode will be approximately: Id = 1 / Rp (Rp = pull-up resistor value).
Using a 4.7kOhm pull-up, it gives you a current value of 0.2mA (200uA).
It may not sound much but you'll have to guarantee that your 3.3V IC can almost permanently clamp this level of current through its protection diode, otherwise, it may overheat and the input/output of the IC may become unusable.
And even if you believe you can make it work, for system reliability sake, don't :)
Now let's assume I will run both the master and the slaves at 3V3. Is this the correct way to pull the i2c lines up?
Yes, it is correct. You may not want to use "NMOSR" for the reference designator of the pull-up resistors (it is not necessary to name the reference designator based on the circuit it is used for, a simple "R" is enough, else you will get a very complex Bill of Materials) and use a unique I2C bus label name going to both ICs for simplicity and avoid confusion for both your schematic software and the reader. |
H: How is the closed loop transfer function defined for an oscillator?
an electronic oscillator is a device which can generate some signals without input signals. It is an unstable system realized with positive feedback, as shown in the following scheme:
Now I have two questions:
How is the closed loop transfer function of this device defined? The input signal does not exist.
How can we implement negative or positive feedback, if the input signal does not exist?
I know that in negative feedback the feedback signal is added to the input signal, in positive feedback is subtracted. So in the first situation we use and adder circuit, in the second one a subtractor circuit. But what do we do in this case?
AI: Just regard it as an amplifier with feedback where the real input is set to a value of zero: -
in negative feedback the feedback signal is added to the input signal,
in positive feedback is subtracted. So in the first situation we use
and adder circuit, in the second one a subtractor circuit.
Feedback +/- input is the same as feedback +/- 0 when the input is zero. |
H: What is "shadow" configuration space?
In a github project I saw a feature as follows:
Support for writing to custom shadow configuration space.
I know what PCI config space is but what is a "shadow configuration space"? I google'd but could not come across anything that explains it clearly.
Here is the link to the project: https://github.com/ufrisk/LeechCore
AI: Typically a shadow memory space/configuration/… is a memory that is a copy of the original.
It can be used to fallback in case of a problem arises, for example when you write the original configuration and there is a power down during writing. The system can detect the configuration space is not written correctly, and can copy the shadow memory to the original. |
H: Universal operator
XMN(A,B,C,D)=(A XOR B) NAND (C NOR D).
Is XMN is universal operator?
a. yes without constants.
b. yes with 0 constant
c. yes with 1 constant
d. yes with OR gate.
e. no.
What does it means universal operator with OR gate?
Is there a method without hinting variables, for example, with karno map to know if the function is universal operator?
AI: It is, because you can tie B and D low and the function is now A NAND (NOT C). Tie B, C, D low and it's an inverter, so you can make a NAND out of it, which is universal. |
H: Finding power absorbed by a voltage source
I would like to find the power absorbed by the voltage source B.
I know that \$P=VI=RI^2=(0.5\Omega)\left( \frac{4-E}{1\Omega + 0.5\Omega}\right)^2\$.
What is the "right way" to find it?
Edit: Basically it gives me three options: \$E=1[V], E=0[V], E=-2[V]\$, and I need to find \$E\$ such that B absorbs the maximum power. Textbook's solution is \$E=1[V]\$.
AI: The power equation you start with is the the power absorbed by the resistor 0.5 ohm, but you should take into account the power absorbed by the voltage source as well:
\$P=R\cdot I^2+E\cdot I = 0.5\Omega\left( \frac{4\text{ V}-E}{1\Omega + 0.5\Omega}\right)^2 + E\left( \frac{4\text{ V}-E}{1\Omega + 0.5\Omega}\right) \$
\$ P = \frac{2}{9\text{ }\Omega} \left( 16\text{ V}^2-8E+E^2 \right) +\frac{2}{9\text{ V}\Omega}3 \left( 4E-E^2 \right) = \frac{2}{9\text{ }\Omega} \left( 16\text{ V}^2+4E-2E^2 \right) \$
\$ P = \frac{4}{9\text{ }\Omega} \left( 8\text{ V}^2+2E-E^2 \right) \$
Note you need to find \$E\$ such that B absorbs the maximum power, so P should be positive.
Decent way is to find optimum for E, so \$\frac{dP}{dE}=0\$
$$\frac{dP}{dE} = \left( \frac{4}{9\text{ }\Omega} \right) \frac{d}{dE} \Bigg(8\text{ V}^2+2E-E^2 \Bigg) = \left( \frac{4}{9\text{ }\Omega} \right) \left( 2-2E \right) $$
\$\frac{dP}{dE}=0\$ for \$E=1\$ |
H: Why 0R used in voltage lines in series?
I have a question about eval board schematics of STMP1.
I noticed that zero ohm resistors were used in the PMIC reference circuit.
Why these resistors used in series to the power lines? Need I them really?
AI: Why these resistors used as series to the power lines? Need them
really?
If you have multiple circuits teeing off the same power rail and the overall circuit is quite complex, there is a good reason for putting zero ohm links in series with the individual power feeds and that reason becomes apparent when fault finding.
If one circuit is dragging the whole power rail down (due to a shorted sub-circuit somewhere), having zero ohm links helps to track down the fault because they are easily removable, easily replaceable and cheap.
Personally if the individual load current requirements are moderate and you could bear the cost of a 0.1 ohm resistor (instead of zero ohms) you could probably identify the rogue sub-circuit using a DVM across each zero ohm link. Bear also in mind that zero ohm links might be sufficiently "resistive" to facilitate this nicety.
The Vishay CRCW zero ohm link has a maximum resistance of 0.02 ohms so I suspect it could be somewhat relied upon to be about 0.01 ohms. 2 amp through 0.01 ohms is a volt drop of 20 mV and very easily seen on a modern DVM. |
H: LED lamp - connecting LEDs in parallel
I have a question about LED lamp:
Quantum Board
It has 16 strings of LEDs connected in parallel. Each string consist of 18 LEDs connected in series. It's supplied with constant current source (with max current 2800mA, what is much more than safe current for single LED/led string.) I know that connecting LEDs in parallel is not the best solution because of imperfection of LEDs while manufacturing and as a result inequality of currents through every string. But I see that is quite common solution for such lamps.
I have several assumption how it is possible:
using LEDs with very similar parameters (Vf), using LEDs with same binning. But actually, according to datasheet Samsung LM301B leds have 1V of Vf variation even inside every binning group. Possible in practice this variation is much lower.
very good thermal dissipation due to metal-core PCB
Could anyone explain how does it works? Are my suggestions the keys for the answer? Is putting a series current limiting resistor for every string and using CV source a more robust solution and why not do it in this way?
AI: using LEDs with very similar parameters (Vf), using LEDs with same binning. But actually, according to datasheet Samsung LM301B leds have 1V of Vf variation even inside every binning group.
I think you missed a decimal place there? The AY bin LM301B LEDs is actually speced with a min/max Vf of 2.6 to 2.7V. That is a very tight spec, so the difference between individual diodes will be very small.
Could anyone explain how does it works?
The absolute maximum difference is very small, the average difference smaller still, and 18 diodes are put in series. If you take a small variation and average it 18-fold, you get an absolutely tiny variation between parallel strings.
For example, if you assume the average variation is 50mV, and averaging that 18-fold will reduce that to about 12mV, or about 0.02%. That is insignificant.
Is putting a series current limiting resistor for every string and using CV source a more robust solution and why not do it in this way?
If you bought a quantum board, you paid many times what a normal LED costs for a high efficiency diode with the lowest possible forward voltage so that you can save electrical power. Putting a series resistor to drop voltage would defeat the purpose of having spent that money. |
H: Current sensing relay with delay on break for dust collection system
I am in the process of planning our a new workshop in a single car garage. I have a large 20A Dust Collector that needs to be on its own circuit or else it will trip. I also have a ceiling mounted air cleaner to get any fine particles that get airborne.
I want to setup a system where if I turn on any of my individually switched tools such as my Table Saw the air systems will turn on automatically and remain on for some time after. I also have them switched so that they can turn on manually.
As a lowly Civil Engineer I'm a little bit out of my depth clearly, but I tried to do a schematic for this. Can you gentleman tell me if I am on the right track?
I also made an album with some parts pulled from Amazon for the project.
https://i.stack.imgur.com/lFHc0.jpg
simulate this circuit – Schematic created using CircuitLab
AI: Your topology is super wonky. Here is what you are looking for. Also, the time delay relay you chose won't do what you want. This or something similar is the relay that you want.
https://www.amazon.com/Liukouu-GRT8-B1-Power-Delay-12V-240V/dp/B07VB9BMZL/ref=sr_1_5?keywords=delay+off+relay&qid=1579709274&s=home-garden&sr=1-5
simulate this circuit – Schematic created using CircuitLab |
H: Switching buzzer on and off with two transistors
I want to make a simple water level indicator with tank full alarm as shown in the diagram. What I want to achieve is, when the tank is full to 100% and water is still flowing through the inlet pipe (ie, the pump is on) the buzzer should beep. I have two outputs from IC ULN2003 for that- Pin 14 switches on when the water level is 100% and pin 15 switches on when water is flowing through the pipe. Also, I want the buzzer to stay off as long as the above-mentioned conditions are not met. Now my questions are,
1) Is the circuit right on the transistor switch side? If not, is there any other
circuit (preferably simple) which I can use?
2) Is transistor 3906 good enough for this use?
3) The resistor values, are they okay?
4) Should I give a reverse bias resistor to the transistor base as shown in the
the second diagram (R2)?
simulate this circuit – Schematic created using CircuitLab
]2]2
AI: The transistor and resistors are okay for a buzzer that draws a moderate amount of current, 100 or 150mA is fine (forced beta of 10-20).
If the buzzer is an electromagnetic type, it should have a catch diode across it. Eg. 1N4148. Reverse biased, of course.
You should have separate resistors for each LED.
There should be high value pullup resistors (eg. 100K) on pins 14 and 15. Note that this will reverse bias the LEDs to -9V (and the E-B junction of Q2, but no current flows) which is out of spec, but probably okay. |
H: Should bus transceivers be used for a legacy M68SEC000?
I'm working on designing a simple "retro computer" based on the NXP 68SEC000. The "SEC" variant (by NXP) is essentially a Motorola 68000 with a few differences. Such as the inclusion of A0 and it's a static/CMOS version.
I'm also reading through the excellent Microprocessor System Design book by Alan Clements. This book does not directly cover the 68SEC000 as it covers the "generic" 68000 from Motorola.
In the book, it references a minimal computer that has 74LS244 bus drivers between the address pins and other devices. It also has 74LS245 bus transceivers between the data bus and other devices.
My understanding is that back then, many of these chips could not drive other components very well so these bus drivers were used to boost the outputs (forgive me, I'm a newbie when it comes to electrical engineering).
However, I have designed another computer in the past based on the 65C02 which doesn't need any drivers because it's modern, static and I assume just "stronger" in its ability to drive other components. This computer proved to be very reliable and I have not seen the need for any drivers on it (yet).
I've tried to find reference designs that use the newer 68SEC000 but I cannot find anything. My searches always leads me back to the generic Motorola 68000 (just like the book).
So my question is, is there any real benefit of using these drivers and transceivers on a new design that utilizes the 68SEC000? Or, does the very nature of the CMOS/static design negate the need for them?
Some points of interest is that my design uses all new and modern parts (except for the 68SEC000). My SRAM, UART's, etc. are all modern devices.
Thanks for any help.
AI: The solution to your answer lies in the datasheet for the chip you want to use.
Look for \$Voh, Vol, Ioh, Iol\$. These characteristics tell you how the chip will drive the busses.
Next look at the chips you will be hanging on those busses and look at their complementary attributes \$Vih, Vil, Iih, Iil\$. Especially the \$Iil\$ and \$Iih\$.
Then add up all the \$Iil\$ for each chip on the bus and see if it is less than or equal to \$Iol\$ for the CPU. Then do the same for \$Iih\$ and compare the total to \$Ioh\$.
If the total input current for all the chips on the bus is less than what the CPU can provide, then you do not need drivers. If the total current is more than the CPU can provide then you do need drivers. |
H: Is there a difference between measuring the resistance using a multimeter ohm function and using the voltage / current relation?
I need to measure the electrical resistivity of a concrete sample following the procedure described in ASTM C-1760.
The procedure requires a 60V DC potential to be applied across the concrete sample (cylinder with 10cm diameter and 10cm length) and the current measured to obtain the bulk resistivity of the sample.
The problem is that I don't have a power supply capable of delivering 60V.
I was wondering if a regular multimeter can produce the same result using the ohm function. The expected sample resistivity should range 50 - 500 Ohm.m
AI: The Ohm function on your multimeter will use the voltage-current relation to determine the resistance of a sample. It will either apply a voltage and measure the current delivered, or force a current and measure the voltage required to deliver it.
But it will almost certainly not use a voltage as high as 60 V, so it won't meet the needs of your test.
Probably the ASTM spec requires a 60 V source to provide a repeatable test method that allows for breakdown of some of the thin layers of oxide material within the concrete, but not others. The higher voltage used may also be needed to accurately measure currents due to ionic transport within the never completely cured concrete.
Therefore I'd expect you need to use an actual 60 V source to achieve a compliant measurement. |
H: Inferred latch occurence in verilog
Implement the following circuit:
Note that this is a latch, so a Quartus warning about having inferred a latch is expected.
This is my implementation
module top_module (
input d,
input ena,
output q);
always @(*)
begin
if(ena==1'b1)
q=d;
else
q=q;
end endmodule
Can someone help me why there is a inferred latch even though i am solving q for every case possible?
AI: It's a latch because you allow q to be updated when ena goes high or any time d changes when ena is high. This is exactly the behavior that describes a latch. This is how you should code a latch if you intentionally want to produce one.
To generate a flip-flop you should make the block triggered by a change in ena (i.e always @(posedge ena)) rather than by any change in the inputs. |
H: Using a 555 timer and 14-stage binary divider for 2 hour timing circuit
I am researching how to design a timing circuit that will activate a relay with a push button and deactivate the relay after two hours. My understanding is that I can feed the output of a 555 timer to the input of a 14-stage binary divider. Then feed the dividers' output to a relay driver. Then, after two hours of the divider receiving pulses, its output will change thus changing the state of the relay drivers output.
My question is, can a 555 timer reliably produce a ~1Hz pulse? And if so, will this be too low of a frequency for a binary divider to reliably handle?
Thank you!
AI: Yes, 1Hz is a reasonable frequency for the 555, especially for the CMOS version. But it may not be optimal.
The temperature stability as an astable multivibrator is typically +/-150ppm/°C for the bipolar version, provided the Ra is between 1K and 100K. To stay in that range, implies a capacitor of the order of 10uF, which is a large and expensive film capacitor or a tantalum capacitor. It will operate with higher resitances, but the stability will generally be worse.
Various CMOS versions such as the LMC555 have improved temperature stability (+/-75ppm/°C typical) and you could us a resistor more in the 1M range and therefore a 1uF film capacitor or even 10x 100nF NP0 ceramic capacitors in parallel.
If you're using the bipolar version it might make more sense to add divider stages and operate at a higher frequency such as 50-200Hz. It also makes it easier to trim the oscillator if you have a reciprocal-counting frequency meter.
As to whether the dividers will work- yes, they're virtually all static and will work down to DC provided the clock edges meet specifications. The only exceptions that come to mind are GHz-range prescalers that won't work at lower frequencies (like < 50 or even 500 MHz).
If the divider you pick does not have a schmitt-trigger input then the rise and fall times may have to be fairly fast, but the 555 will produce adequate edges generally. |
H: What's wrong with this PWM-controlled constant current sink?
T10 gets very hot and starts melting within 30s, even with a heat sink and values way below its rated 15A.
Edit:
I know it is not a true PWM controlled constant current, but that what I can do with the parts that I have access to. As for the current being used at, it does not exceed 4A at full duty of the 65kHz signal.
Edit 2: So, basically, what's wrong with my circuit is my inability to correctly use the information in the datasheet. Thanks for your answers.
AI: When the load (2 ohm) is driven at 3 amps, it develops 6 volts across it and, conversely there is 6 volts from collector to ground because the supply is 12 volts. At this current the emitter resistor drops 1.5 volts therefore, the collector to emitter voltage has to equal 4.5 volts. So, the power dissipation in the transistor is 3 amps x 4.5 volts = 13.5 watts.
The thermal resistance of the transistor is 1.5 degC per watt and if this is on a Heatsink of (say) 10 degC per watt, the temperature rise of the transistor’s junction is 13.5 x 11.5 degC.
So, do you see the problem here? |
H: STM32 f401re power issue?
I get the following error when I try and upload code
Error in initializing ST-LINK device.
Reason: No device found on target.
The voltage is across VCAP1 is 0 which I find a bit odd.
I have alligned the chip as per the data sheet which can be seen in the following photo.
I am quite lost any help would much appreciated. I would think it is a power issue seeing as there is no voltage across VCAP 1? I dont belive I have fried the chip as this is the second attempt and I used anti static bags during transport and earth mat when soldering and assembling.
AI: Never mind I found the answer. Naturally 5 minutes after posting this. I hadn't set up the reference voltage. Being used to AVR I was not aware that I needed this before programming it. |
H: When does a transistor turn on
I am having a very hard time understanding when exactly a transistor turns on. For example in the following circuit from Everycircuit:
Why does the transistor turn on when the push button is off, but not when it's on? The only way it seems to make sense to me is that the voltage relative to the base is "more positive" when the resistance to from the base to the positive terminal is lower than the resistance from the base to the negative terminal. For example, if I change the resistances:
From this, how would current even have anything to do with 'turning on' the transistor at all? It seems like it's only related to voltage from the below. Could someone please describe why exactly the transistor is being turned on in these conditions? Not just conceptually but with equations as well, if possible to show the current/voltage going in and such.
AI: Update to DEMO Question with Analysis and Tests with variable supply.
The base R pair resistor divider ratio defines a Thevenin equivalent Voltage, Veq and Req which is not effective for limiting current when the LED is under the emitter. It is better to use the transistor as a switch and limit current with LED and Rs above the collector.
Even better is to add another transistor to act as a constant Vbe current limiting regulator called the WIDELAR Constant Current Limiter after 60's genius Bob Widlar who made Fairchild then National Semiconductor famous before the 741 and earned $1 million to retire early in Mexico, but was a "brilliant alcoholic"
This is my simulation of his brilliant design. If current is 20mA the regulator Vbe = 530mV with 100uA so the main upper transistor I= 530mV/Re= 19.6mA (Re=27V)
I applied 12 digital probes so you can see the absolute and relative voltage with current for each LED. I modeled the LEDs to match my 5mm excess stock that I have that are 20,000 mcd.
The triangle was just added to demonstrate the sensitivity to supply voltage.
Here the upper transistor is just a linear switch and the emitter R is a current sensor that when it reaches Vbe of 500mV it starts to shunt the switch off. Since the lower regulator only uses Ic=100uA, it's Vbe is not 0.7 but rather 530 mV.
This is because Transistors are Vbe exponential controlled current sinks when the emitter is grounded. So the high current gain of 2 transistors and more or less stable Vbe are used to keep the current constant. I chose it to drop rapidly when a 9V battery starts to get weak 8.5V so it lasts longer, yet it is the same current even on a car at 14.2V |
H: Can I somehow control a PSU-powered fan using a 4-pin fan output on the motherboard?
I have a 12V 29.4W 3-wire Delta Electronics fan that I want to power using an EVGA 750 G3 PSU and control via one of the 4-pin fan terminals on an MSI MSI Z390-A PRO ATX LGA1151 motherboard.
Not considering the wattage of the fan, I originally plugged it into a (known working) fan terminal but it of course would not turn (and the BIOS correctly reported the RPM as 0). Connecting it directly to the PSU is simple enough, but this would result in it turning at full speed at all times.
I am curious if there is a "DIY" way that I can supply the fan with power from the PSU and control how much actually reaches the fan using the output of the motherboard (using something like an optoisolator to keep the motherboard safe).
The motherboard is able to control 4-wire fans using PWM, and 3-wire fans using DC voltage level.
Is there a product or combination of parts that will do this? I originally asked this on Super User, but it was deemed more appropriate here due to the involvement of DIY electronics.
Thanks in advance!
EDIT:
The 4-pin connectors on the motherboard are indeed keyed to force correct connection of 3-pin plugs.
The BIOS includes a Fan interface that allows you to plot desired RPM vs temperature. Each fan output can individually be set to either PWM or DC voltage level control. The motherboard auto-detects what is plugged in (4 or 3 wire) and selects the appropriate setting, but it can be changed manually if desired.
The fan was not purchased through DigiKey, and came terminated with a keyed 3-hole connector (F). It also shipped with a 2-wire (but 4-wide) molex connector (M), unterminated on the opposite end.
AI: The motherboard is able to control 4-wire fans using PWM, and 3-wire
fans using DC voltage level.
I did not see anything about 3-wire fan support on that page, but if user manual says so then you don't need anything else but correct wiring on 3-pin plug. The PWM control pin will not be used, and the taho output from 3-pin fan is compatible with tach input on 4-pin fan connector. Furthermore, 4-pin connector is usually keyed in a way that forces correct connection of 3-pin plug.
Note, that if motherboard does indeed support both types of fans then most likely you have to configure fan type somewhere in BIOS.
I originally plugged it into a (known working) fan terminal but it of
course would not turn
There is nothing "of course" about this. The fan should have been working at full speed all the time and motherboard should have been able to read its RPM. That's, of course, if it is configured for 4-pin.
From the link to a fan it seems it comes without a connector. So, check your wiring first.
UPDATE:
If your problem turns out to be insufficient motherboard output wattage, then one DIY solution would be to add OpAmp in voltage follower configuration, supplied directly from PCU and controlled by voltage output from motherboard connector. Depending on motherboard driver's design you might need to add a load resistor on the control line to simulate fan motor. |
H: Does Diode Position Matter in Series?
I've put together this circuit, and (with some help from EE SE) it's working great.
I have it wired like this:
where the diode comes first off the middle transistor pin, and then the motor negative comes next. The motor negative lead and diode are not touching (except that they're in the same vertical rail).
I understand the diode is in this circuit to handle discharge of the 12V solenoid. If I wire the negative lead first, as so:
would this be equivalent to the above or does it matter where the diode is in relation to the negative lead?
AI: It is the same, as the are connected to the same node on the circuit, thus having the same voltage on both the diode and the motor negative lead. |
H: Hypothetically, 6 or more phase line with same mechanical energy?
So I don't understand a concept of mechanical to electrical energy conversion.
Let's assume I have a 3-phase generator and need X amount of mechanical power in order to get 200 Volts Phase-Neutral.
Now suppose I add some windings etc. so that I have a hypothetical 6-phase system. Would I need more mechanical energy in order to get 200 V for each phase, or can I get it by same amount X? So basically, if I have more phases do I need more mechanical power?
AI: Let's assume I have a 3-phase generator and need X amount of mechanical power in order to get 200 Volts Phase-Neutral.
You are confusing the relationship between power and voltage. For a given winding arrangement the voltage will depend on the speed. The mechanical power input required when unloaded will be that only to overcome the mechanical resistance.
Now suppose I add some windings etc. so that I have a hypothetical 6-phase system. Would I need more mechanical energy in order to get 200 V for each phase, or can I get it by same amount X?
You don't need much power to generate voltage. You do need power to generate current at that voltage.
So basically, if I have more phases do I need more mechanical power?
No. You need more mechanical power if you draw more electrical power from the generator no matter how many phases you have. In general:
$$ P_{OUT} = P_{IN} \times efficiency $$ |
H: Op-Amp Oscillation
I'm trying to design an inverting amplifier that has a gain of about ~30. It is required to be a two stage design with the first stage being none inverting and have an input impedance of >=500k. The input frequency would be ~160kHz to 200kHz. Below I've built a preliminary circuit that only has a gain of 20 for testing and ran into some oscillation issues. I've attached the scope capture of the oscillations and a schematic. Channel one is attached to Node1 of the attached schematic. The oscillations seem to occur with no input.
simulate this circuit – Schematic created using CircuitLab
Reducing the gain of the first stage (reducing R10) or increasing R6 stops the oscillations but then I can no longer meet my specification. I'm wondering what is causing this issue. I've read this post: Why is my op-amp oscillating? and am wondering if I need to go into the math of the control system and feedback stability. Any help is greatly appreciated.
UPDATED:
As suggested by Spehro Pefhany I tried grounding the input. This actually stops the oscillations. Is it possible this is due to poor layout?
Layout of the circuit. Highlighted trace is the input to the none inverting in the first stage:
I've also updated the schematic to show bypass capacitors.
AI: Your input (when open) looks like 500K||6pF maybe (Edit: maybe a bit more with the ground (??) plane), and there's a gain of almost 50, so even 0.1pF of parasitic capacitance from the output to the non-inverting input could be enough to cause oscillation at the ~1MHz you are observing. It would take even less from the 2nd op-amp output.
So it's probably layout-related. It's difficult to get something like this to work on a solderless breadboard. A dead-bug construction with a ground plane is far more likely to succeed.
Edit: From your posted layout, the output pin 1 crosses over the non-inverting input under the chip. That may be the source of your problem. Of course if the amplifier is normally connected to something that's relatively low impedance it might not be an issue. Your input impedance is maybe 100-200K at 200kHz I think (ignoring the inadvertent bootstrapping anyway). To get 500K at 200kHz is not easy without trickery that makes it happy to oscillate.
If the blue plane under the input is not AC grounded that's really bad. I don't see where it goes.
The fact that oscillation stops when the input is grounded tells us that it's getting in through the non-inverting input. |
H: AC to DC power supply questions
I have built the circuit in the diagram below with a couple of minor changes. I desire 3 DC outputs - +12, -12, and +5 volts. So, the changes I made is to use an MC7812BTG for the +12 and an MC7912BTG for the -12. Then I simply added an LM7805CT after the 7812 to get my +5. I made 2 heatsinks from a couple of L brackets I had laying around. I also added LEDs to the 3 "rails" so that I could verify they are operating. Everything else is the same as the diagram.
This is for a very small modular synthesizer case. I tested the power supply with no load and it checked out fine. Then I installed 4 modules with approximately 350 mA draw on +12 and 100 mA on -12. The +5 volt rail was not used at all. I powered the case on and it all worked as expected for about 35 or 40 minutes. Then the modules glitched and the audio "froze". These are digital modules. Anyway, turning the power switch off and back on restored the function of the synth, but just a couple minutes later it glitched again. That's when I realized how hot the case was underneath where the voltage regulators are at.
My main questions are:
Am I pushing the regulators too hard by supplying 25 volts and dropping it to 12? Should I consider a 24V transformer?
What would a "proper" heat sink consist of for these regulators? Is my "L" bracket piece of metal (3/4" wide, 1/8" thick, and 4" long, bent to L shape at center) just not enough of a heatsink?
If the 7812 is overheating, what is occurring to make the modules "glitch"? (overvoltage, undervoltage, etc.)?
Thanks in advance for any advice, comments, or stern reprimands.
AI: As others have said - a lower voltage input to the regulators will decrease power losses.
Ideally Vin is about Vout + Vdropout + Vheadroom
Where "Vheadroom" is a volt or two.
Where you have excessive Vin, dissipation in the regulator can be moved into a series resistor that can be dimensioned to withstand the dissipation.
If 5V is used, connecting the 5V regulator to Vin via a resistor will take the large thermal load off the 12V regulator.
An LM340 datasheet here has a dropout voltage of 2V typical at 1A at 25C, and somewhat less according to fig 11. Allow 2V.
At present the LM340 dissipate P = V x I = (25-12) x 0.35 = 3.9W
Adding a series resistor that drops Vin to 14V min gives:
Vin min = 12V + 2V at 1A = 14V.
Rseries = V/I = (25-14)/1A = 11 Ohms.
At 350 mA that drops only V=IR = 0.35 x 11 = 3.9V
and dissipates only
P = I^2R = 0.35^2 x 11 = 1.35 W
That's a help - but not as much as you'd wish.
If you NEVER draw more than say 400 mA continuous and have enough capacitance at the regulator input to handle any higher surges then.
P_LM340 no resistor = V x I = (24-12) x 0.4 = 4.4W
With series resistor:
Vsupply = 25V. Vin = 14V min. Imax = 0.4A
Rseries = V / I = (25-14) / 0.4 A = 27 Ohms.
Power in resistor max = I^2.R = 4.3 W
Power in LM340 = V x I = 2 x 0.4 = 0.8W.
= 0.8/4.4 = 18% of initial !!!
Use a 10W resistor to dissipate the <= 4.3 W
(A 5W resistor would notionally work, but running it at < 50% power rating extends its life.)
Use an aircooled resistor - readily available, so no resistor heatsinking is needed.
Keep the resistor away from the regulator AND away from any electrolytic capacitors.
This SE Q&A My linear voltage regulator is overheating very fast covers the subject in (great) detail. |
H: TLP175A High Load alternative
I came across this IC and it is an IC i need, but i would like to controll a heavier AC load with it, 220V 1A but this particular device is for low volatage levels. Is there high load alternative for this IC or a tool that will help me search through the alternatives in future
AI: Is there [...] a tool that will help me search through the alternatives in future
You can use distributor's sites to search for such optocoupler/solid state relay:
Search for TLP175A on e.g. mouser.com, find which product group it is in.
All Products Opto-electronics > Optocouplers/Photocouplers > MOSFET Output Optocouplers > Toshiba TLP175A(TPL,E)
Click on MOSFET Output Optocouplers and use the filters to narrow down the result.
(and you'll find Mouser doesn't have it) |
H: How to find phase shift(angle) between two signals in simulink?
So I'm doing a delta wye transformer in simulink and phase shift between these two signals should be 30 degrees, but how to show that, or calculate it? And how to find angle of each signal?
AI: Use the frequency and period of the wave.
Then the equation is:
Phase shift = 360 * time / wave period
Phase shift is in degrees and time is the time difference.
And you don’t want to find the angle of each signal rather you want to find the phase angle difference between the two sine waves. |
H: Smith chart tutorial question
I am looking at a Smith Chart tutorial on the antenna-theory.com website. Unfortunately, I'm confused by one of the examples given...I don't get the same answer, so it's safe to say I'm doing something wrong. I was hoping someone could point me in the right direction.
It's example 2 on that page. It assumes a reference impedance, Zo = 50 Ohms. It provides a reflection coefficient, Γ = -0.3 + i0.4, and calculates the corresponding load impedance, Zl = 20.27 + i*21.62 Ω using the equation below:
Zl = Zo (1+Γ) / (1-Γ)
However, I don't get the same result for Zl. My working is:
For the real component of Γ, Zl = 50Ω (1+(-0.3)) / (1-(-0.3)) = 26.9Ω
For the imaginary component: Zl = 50Ω (1+i0.4) / (1-i0.4) = 116.67 Ω
Giving Zl = 26.9 + 116.67 Ω, which is miles off their answer. I'm obviously misunderstanding something, so any help would be appreciated!
Thanks in advance
AI: For the real component of Γ, Zl = 50Ω (1+(-0.3)) / (1-(-0.3)) = 26.9Ω
For the imaginary component: Zl = 50Ω (1+i0.4) / (1-i0.4) = 116.67 Ω
You can't split up the real and imaginary components like this. Your equation needs to be
\$Z_l=50 \frac{1 + (-0.3+0.4j)}{1-(-0.3+0.4j)}\$
If you then simplify this you get to the answer they provided.
One of the nice things about a Smith chart is that you can easily convert between reflection and impedance. If you had a smith chart with a grid on it, you could plot this reflection and directly read off the answer without needing to do any math. |
H: Value of loop gain for steady state oscillations
I was reading on a book (High-Frequency Oscillator Design for Integrated Transceivers, J. van der Tang, Dieter Kasperkovitz, Arthur H.M. van Roermund) this paragraph about the start-up condition for an oscillator:
Let's consider for instance a common base Colpitts Oscillator (biasing network for the base is not shown):
Now, I may do a small signal analysis of this circuit at open loop, find the expression of the loop gain, and size the components in order to make its absolute value greater than one. But, which is the mechanism that will reduce it once the oscillator has started? Is it automatic? How can I size the components in order to make it exactly equal to 1?
AI: Non linearities in the transistor will inevitable make the loop gain equal to 1 at some peak to peak amplitude and, the natural impact of this is that the amplitude is difficult to precisely predict (not normally a big deal). The second impact is that the sine wave output will be naturally flattened on one or both peaks and, again, this is often not regarded as a big problem.
So, in short, the sine wave amplitude builds (because loop gain is greater than 1) and, as clipping starts to impact the sine wave shape, loop gain falls to exactly unity. |
H: How is the amplitude of an output signal of a binary input determined using a constellation pattern?
I understand using the pattern to find the output line single phase but how is the amplitude determined?
AI: But how is the amplitude determined?
By the length of the line from the origin to each constellation point: -
The above image has equal amplitudes for all four binary values hence they sit on the circumference of a circle.
The one below has 8 binary values and the amplitude of the inner four is smaller than the outer four. |
H: What is this connector type
Could anybody help to identify this connector type? I know it is kind of old.
AI: Looks like 5-pin 180° DIN connector. |
H: How do we explain the common-mode feedback in an intuitive way?
There are such beautiful circuit ideas that make you hold your breath and admire them silently. Such an idea is the common-mode feedback (CMFB) in fully differential amplifiers. I was not familiar with this idea and started thinking about it when I met Need for common-mode feedback.
Then a lot of questions arose: "What is the need for another negative feedback in fully differential amplifiers? What is the difference between it and the ordinary differential negative feedback? Why the latter cannot define the common-mode level? Why the outputs of the amplifier are connected to its inputs?"
In the end, I managed to understand it myself and explain it in detail. When I dug into Razavi's book, I saw that his explanation was basically the same. But my answer was pretty impulsive written because I was in a hurry to respond to OP ideas.
So the idea came to explain in an intuitive way, step by step, the necessity and nature of this idea. But how do we do it? In what order? How to get to the final solution in the colorful picture below?
AI: My intuitive understanding of the common-mode feedback is based on the concept of dual dynamic load. As I have fabricated this descriptive name to explain the idea behind CMFB in a more figurative way, I will show you the path that I walked on to reach it. There is nothing weird in my explanations as you would think from looking at these unconventional pictures. Rather, they are based on simple electrical concepts comprehensible for everyone... and this is the power of intuitive approach.
Building a half differential pair
First, I will show the main idea in four consecutive conceptual pictures (marked with letters A - D). Each of them contains four versions (numbered with 1-4 in each picture). Then, each of the versions is illustrated with a separate picture (numbered with 1 - 4) with the corresponding MOSFET implementation from the Razavi's book. The series finishes with a generalized picture 5.
A. Interacting sources. The simplest electrical circuit possible consists of two elements - source and load. Besides passive (resistor), the load can be active (another source)... in this quite more interesting case there are two interacting sources. One of them is the "initiator" and the other responds to its impact.
The combinations between both elements can be various but let's consider only these related to our subject (five MOSFET circuits with CMFB from the Razavi's book). Note there is no ground in the picture below (it is not needed yet). The four diagrams in the picture (numbered with 1 - 4) are drawn in a form consistent with the next steps.
Current source drives resistive load (1). In this arrangement, constant current flows through constant resistance and creates a voltage drop across it. This voltage is stable since it is well defined by Ohm's law and it does not change by itself.
Its magnitude can be significant.
Current source drives current source (2). Here, two equivalent current sources are connected in series (one current source serves as a dynamic load of the other source). The voltage across them is unstable and can be easily changed by itself. As above, its magnitude can be significant.
Voltage source drives current source (3). This is the perfect combination between two sources since the voltage source sets the voltage across them and the current source sets the current through them. The voltage is stable and constant... and limited by the voltage source.
Current source drives voltage source (4). This is the same perfect combination as above. It is inserted here for completeness (in the next implementations it will be used).
B. Interacting sources and sinks. Electronic circuits are supplied by a power supply which negative terminal (usually) serves as a ground. So the pairs of sources above are "stretched" between the supply rails - one of the sources in each pair is connected to the positive supply rail and acts as a source; the other is connected to ground and acts as a sink. In this arrangement, the bottom sources are driving.
C. Interacting dynamic resistors. Аlthough in electronic circuits these elements are represented by source symbols, they are not sources because they do not "produce" energy but consume it. You can convince yourself by seeing that, in Example 1 of the picture above, the voltage polarity of the current source does not correspond to the current direction (if it was a source with a big enough current magnitude, it could change the polarity). Also, its magnitude is limited to the supply voltage.
These elements are dynamic "resistors" - the "current source" is a dynamic resistor RI that keeps the current constant and the "voltage source" is a dynamic resistor RV that keeps the voltage constant. They are linear within the operating region of their IV curve (horizontal for transistors and vertical for diodes). Each pair of such elements can be thought of as a "dynamic voltage divider" consisting of two elements - pull-up and pull-down "dynamic resistors".
Generally speaking, these elements keep constant current/voltage by changing its instant resistance. Let's see how exactly they do it, for example, in case 3, where a current-stabilizing resistor RI is connected in series with a voltage-stabilizing resistor RV.
If for some reason RV decreases/increases, RI will increase/decrease so that to keep up constant the total resistance RV + RI of the network. As the supply voltage is constant, the current I = Vdd/(RV + RI) will stay constant as well.
If for another reason RI decreases/increases, RV will decrease/increase so that to keep up constant the proportion RV/(RV + RI) of the network (voltage divider). As the supply voltage is constant, the voltage Vdd.RV/(RV + RI) across RV will stay constant as well.
D. Interacting transistors and diodes. In practice, dynamic resistors are implemented by electronic elements having these properties - transistors and diodes (transistors act as current "sources", diodes - as voltage "sources").
Building a full differential pair
By pairing two identical half pairs, we can assemble the full differential pair. Let's do it in the same order as above by illustrating each of the versions by a separate picture (numbered with 1 - 4) with the corresponding MOSFET implementation from Razavi's book. Now two single-ended input voltages drive the sources; so there are two kind of input signals - common-mode input voltages (when changing them simultaneously with the same rate, in the same direction... and differential-mode input voltages (when changing them in the same manner but in opposite directions).
1. Transistor - resistor pairs. Now everything is doubled - two constant currents flow through constant resistances and create two stable voltage drops across them. We take the difference between the two single-ended output voltages as a differential output. In common mode, both currents stay constant; so, all voltages are stable. At differential mode, the two drain currents are complementary (the common source current is steered between the two transistors).
(Razavi, Fig. 9.30a)
2. Transistor - transistor pairs. In this arrangement, the lower transistors are driving and the upper transistors serve as dynamic loads. In common mode, both single-ended output voltages are unstable; so the differential output voltage is unstable as well and can be easily changed by itself. At differential mode, the two drain currents and output voltages vigorously change.
So, the problem is how to stabilize the unstable single-ended output voltages... or, in other words, how to stabilize the common-mode output voltage (the average value of the two voltages).
3. 'Diode' - transistor pairs. We remember that diodes can do a good job for us... but they are awkward to implement, have fixed forward voltage... and they are always diodes (see below). Then can we not "reverse" the behavior of transistors - make them work as diodes instead as transistors? Negative feedback will help us do this "magic"; it is enough to connect the gate to drain... and the drain current becomes an input quantity... and the gate-source voltage - an output quantity. First, we can make the lower transistors "active diodes'':
(Razavi, Fig. 9.31a)
4. Transistor - 'diode' pairs. Then, with the same success, we can make the upper transistors "active diodes":
(Razavi, Fig. 9.46a)
But a problem appears here...
5. Transistor - dual load pairs. We need these "diodes" only when there is no differential mode (i.e., during biasing or at the common mode). At differential mode, we need transistors (dynamic loads) to get a significant gain. So these elements should be able to act, depending on the mode, either as diodes or transistors. Here is the advantage of making diodes through transistors - they can act as both diodes and transistors.
But what determines the behavior of this universal element? This is the presence or absence of negative feedback. When there is a negative feedback, the transistor acts as a diode; when there is no negative feedback, the transistor acts as a transistor. So this will be a feedback acting only with respect to the common-mode output voltage; hence the name common-mode feedback (CMFB). Let's see how the general idea shown in picture 4 is implemented:
(Razavi, Fig. 9.46b)
We are approaching the culmination of our story...
We can obtain the common voltage by a simple summing feedback network consisting of two resistors R in series... and then apply it to both gates of the upper transistors.
Common mode. If, for example, both output voltages try to "move up" (common mode voltage), point B will "move up" as well. The gate-source voltages of M3 and M4 will decrease... their drain currents will decrease... and the output voltages will decrease. As a result, the negative feedback will restore both Vout1 and Vout2. So, at these common-mode voltage variations, M3 and M4 act as "diodes" because of the negative feedback. The voltage drops across them are constant... the common-mode gain is zero.
Differential mode. If we simultaneously vary the input voltages Vin1 and Vin2 but in opposite directions, the emitter voltage of the common point A will stay constant (virtual ground). The common source current is delivered by M1 and M2 and then steered between M3 and M4. The common mode feedback is not active since the average voltage (Vout1 - Vout2) is zero (another virtual ground at the middle point B). So M3 and M4 act as transistors (current "sources"), not as "diodes" (voltage "sources"). They serve as dynamic loads and the differential gain is maximum.
Let's also see how the similar general idea shown in picture 3 is implemented:
(Razavi, Fig. 9.34, page 317)
The op-amp "observes" the common-mode voltage (the average of M1 and M2 drain voltages) and drives the current sink in the source to keep this voltage constant. In differential mode, there is no negative feedback. The source current is steered between M1 and M2; Vout1 and Vout2 vigorously change.
So, CMFB modifies the behavior of both dynamic loads (transistors) in the outputs of the fully differential amplifier at common mode; it makes them act as diodes.
But still, what is the need for the common-mode feedback?
Due to the huge gain, the outputs of the differential amplifier with dynamic loads look like hypersensitive scales that cannot be easily balanced. So the output voltages Vout1 and Vout2 can hardly be held between the supply rails and they easily reach them. This can only be done with the help of the stabilizing negative feedback.
In the differential amplifier with single-ended output, both bias and input voltage affect the same output... and the negative feedback fixes the output voltage to the desired "position" (somewhere between the rails).
In our fully-differential amplifier, these functions are separated - the bias current affects only both single-ended output voltages while the input differential voltage affects only the difference between them. This difference is floating and the bias current should first set it in the middle "position" between the rails... and then keep it there. As it is too hard because of the dynamic loads, there is a need for another negative feedback to do this work... and this is the common-mode negative feedback. It will keep constant the common output voltage (the average of Vout1 and Vout2) regardless of any interferences that attempt to change it.
So "common-mode" here implies "common-output voltage", not "common-input voltage". CMFB exactly means "negative feedback that keeps the common (averaged) output voltage at some desired level between the rails".
Finally, after we revealed the secret of the fully differential amplifying stage with CMFB described in Razavi's book, let's get back to the beginning of the question and have fun with the colorful picture of the complete circuit (it represents, in a more attractive way, Fig. 9.46b from Razavi's book). |
H: How to generate desired voltage signal in a circuit?
What I am asking is a design or pulse shaping question.
We learn about analyzing circuits but not designing them in school.
Let's say I have an input signal which is a triangular wave and I want to generate some output signal with some sophisticated shape that are not simple sin or square wave or something we know.
How should we design the circuit in between to achieve that? What I can think of is to write equation of my output signal of desire in time domain somehow and take laplace of it to figure out what components in what order should be placed to achieve this signal.
AI: I want to generate some output signal with some sophisticated shape that are not simple sin or square wave or something we know. How should we design the circuit in between to achieve that?
The usual way to do this is to use store samples of the desired output waveform in a memory (EEPROM, for example), and feed them to a DAC at the correct rate, then filter the DAC output to remove aliasing effects.
With this arrangement the exact shape of the input waveform is irrelevant, provided you can derive a clean clock signal from it, and from that generate an appropriate (higher frequency) clock to drive the DAC.
Typically analog methods are only used when the desired output is something simple like the sine, square, or triangle waveforms you mentioned. Of course there may be special situations where you want to generate something more complex using analog methods, but the way to do it would then depend very much on the specific requirements that led you to need that complex waveform. |
H: How accurate are the crystals on ST's Nucleo boards?
I got myself a cheap ST Nucleo-L053R8 on discount, to play around with a couple ideas.
The main STM32L053R8 only has a low-frequency 32.768 kHz crystal for RTC, but it can also be provided with an 8 MHz clock from the included ST-Link USB programmer. The LF crystal is marked 32G501, and the ST-Link's is marked 8.000Q5G.
Does anyone have any idea how accurate these two crystals are at room temperature? The documentation doesn't seem to specify.
AI: I found the bill of materials for this board on the product page:
It has these two descriptions for some crystals:
So it looks like they are probably ±20 ppm. That is actually usually the tolerance over the full specified temperature range -- I'd expect even less variation at room temperature.
However, you did state that the 8MHz crystal is actually not present on this board, so I'm not sure if this is the right crystal. Even if it's not, there's a good chance they use the same one on the programmer. |
H: What are the pins on this jack connector?
I've bought a PJ-3053 audio jack connector. I purchased it under the impression that it would have a microphone connection, but when I put in a TRRS jack, take a multimeter and measure connections, none of the pins gives a beep with the shield from the jack I plug in. It does have 6 pins, and comes with the following schematic: .
Pin 7 is the ground it seems, pin 5 is left, 6 is right and the other 3 are unknown to me. I know there are jacks with detection in them, but for that just pin 2 and 3 would be enough, right?
AI: That appears to be a 3-pole jack with auxiliary switch.
Older stereo music systems typically used the jack socket switch contacts to switch on the internal speakers when the jack was removed. We can see this on contacts 5 and 2. The √ on 5 is the part that touches the inserted plug. When the plug is inserted the √ is pushed away from 2 so that the switch opens. It should be clear that the amplifier output would be connected to 5 and the speaker to 2. With the plug out the speakers will work. With the plug in the headphones will work but the speaker will be disconnected.
7: Sleeve / GND.
5: Tip.
2: Tip pass through. Contact is closed when unplugged. Inserting the plug disconnects 5 from 2.
6: Ring. My guess is that the black block is an insulated link which drives contact 4.
4 & 3: These form an isolated switch that is closed when the plug is removed.
3 & 4 have no contact with the audio and so could, for example, be used to signal to a device that the headphones had been plugged in and the volume be adjusted accordingly.
It doesn't have a second ring connection for a microphone.
Continuity check confirmation:
No jack:
5 & 2 are connected.
3 & 4 are connected.
There are no other connections.
Jack inserted:
Sleeve to 7.
Ring to 6.
Tip to 5.
All other pins isolated. |
H: Are FPGAs used as Cubesat flight computers?
Are FPGAs used as Cubesat flight computers and are there benefits or drawbacks in using them?
AI: Are FPGAs used as Cubesat flight computers and are there benefits or drawbacks in using them ?
Yes, they're used.
Their biggest disadvantage in a satellite is that they are essentially large chips that are very sensitive to ionizing radiation - which is a major problem in space, especially if your satellite isn't large enough to offer much shielding. Large surface + sensitive to radiation = high probability of erratic behaviour.
You'd want to use "rad-hard" (radiation hardened) components – but these get very expensive very quickly (because they're mostly used in spacecraft, transcontinental missiles, medical equipment, nuclear power plants – in short, places where you "just pay the price").
Since you're a beginner: As long as you're not 100% sure your problem can't be solved in software for a capable microcontroller, stay away from FPGAs. Hardware is hard, and FPGAs are configurable hardware and thus a whole new world, and FPGA design is really not trivial to get right the first try. Nothing you want to learn on >3·10⁴€ hardware in space. |
H: ICSP + FTDI for ATMega328P
I want to have this "debug" header with 10 pins (I could probably get away with 9) and I am wondering if the DTR pin is ok to be filtered by a capacitor for ICSP.
This is how I am sourcing these pins:
Note the capacitor in magenta. Will that affect the RST line for ICSP?
Why? Why not?
AI: I am wondering if the DTR pin is ok to be filtered by a capacitor for ICSP
No. The typical "Arduino-style" practice is to capacitively couple a signal such as DTR to the ATmega reset pin, so that a toggle of that control signal will reset the processor, but for portability the processor is able to run with either setting of the signal.
In contrast, typical usage of the ISP protocol requires that the reset signal be taken low and held there for an extended period of time. That would not work with capacitive coupling.
However, you can relocate this "problem" from the board itself, to your programmer or software.
If you do not need broad serial software compatibility, you could directly connect the reset to a header pin, and have to have software of any computer with a serial adapter where that is connected through consistently set that signal (electrically) high to allow the MCU to actually run.
You could put a capacitor in your programmer cable along with a physical switch to bypass it for ISP mode
You could make two different cable versions with and without the capacitor and label / color code them by purpose.
You could use some sort of more custom USB-serial interface in your off-board programming adapter (perhaps a custom one made from an ATmega16u2 as the Uno itself uses?) with some sort of other scheme for controlling the reset that only appropriate software would know how to trigger.
It is also perhaps possible that if you review the details of ISP programming you might be able to do it in a bunch of short steps after toggling the line before the charge bled off the capacitor. This however seems like it might be more clever than smart.
Note that an FTDI USB-serial chip (especially a base model typically intended for asynchronous serial) isn't a great way to do ISP anyway - you may really want to look at a solution where you use a "programmer" (perhaps an Arduino with the ISP sketch) for ISP but a "USB-UART" for communication, or perhaps unify the two in a custom ISP sketch firmware (though avoid software serial!!) |
H: Verilog: use calculated variable as length or index of another variable
I need to expand and truncate variables a lot in my Verilog project. The issue is that the constraints for these operations are dynamically generated.
Example:
function sometruncation;
input a, b, Z;
integer x;
begin
x = a + b;
somefunction = Z[x:0];
end
endfunction
Another example for replication:
function somereplication;
input a, b;
integer x;
begin
x = a + b;
somefunction = {x{1'b0}};
end
endfunction
Vivado is now telling me that 'x' is not a constant. I'm quite new to Verilog but according to my understanding I need to declare a parameter to get a kind of constant but this requires me to know the value beforehand, right?
Thanks in advance!
AI: For truncation, you can do a shift and mask operation.
somefunction = Z & ((2<<x)-1);
In your second example, replicating 1'b0 is unnecessary and doesn't accomplish anything. I find that the case is many other examples. You can always revert to a for loop if necessary. |
H: Capacitor in series with transistor base
I am fairly new to electronics and just had a quick question. I saw the following suggestion for a one shot trigger to wake up an ESP from for example a PIR sensor with one shot trigger and to read the data on another pin:
I do not understand how current can reach the base of the transistor and make the collector emitter path conductive. I always was under the impression that capacitors do not let current flow in a DC circuit and just charge up. I would have expected the capacitor in parallel to the base emitter path, so it would charge up and delay the current flow to the base and the resistor in series from interrupt signal to base to limit the base current. Any answer is greatly appreciated!
I am sorry if my English is not the best, it is not my first language.
AI: I always was under the impression that capacitors do not let current flow in a DC circuit and just charge up.
This isn't a DC circuit.
The input is a pulse, not a constant voltage.
When the rising edge of the pulse arrives, the capacitor voltage can't change instantaneously, so the transistor base voltage will follow the pulse. Then a momentary current will flow and the capacitor will charge, dropping the base voltage back toward zero over a few milliseconds. When the falling edge of the pulse arrives it will discharge the capacitor, requiring a momentary current in the opposite direction.
Assuming the duty cycle is low, the pulse rising edge will need be strong enough to bias the transistor briefly into forward operation. The falling edge will not affect the transistor, just pull the base slightly negative as it pulls current through the 5k resistor. |
H: What is the maximum voltage for MPPT/PWM to charge a X volt battery?
I currently have a PWM 12/24v (auto commute) with ~18V as input and a 12V battery in the output.
I wanted to switch to 24V battery and I thought about going ~36v solar panel. (18V * 2)
Then I saw online some examples of putting more in series for a higher voltage, like this one:
These solar panels are 100W and can go up to ~22V. So if I'm correct this schematic will send about 66V to the PWM/MPPT to charge a 24V battery. (two 12V in series.)
Can a charge controller handle whatever amount of voltage? And is there on this aspect a difference between MPPT and PWM?
And is there a difference in efficiency between sending 66V or 33V?
AI: At the risk of stating the obvious, the MPPT is always going to do a better job. It is "gaming the panel", making experimental adjustments upward or downward in current draw to see if that improves or worsens voltage enough to produce a net increase in V*A.
In theory, both of them, MPPT or PWM, should buck the input voltage down to an appropriate battery charge voltage given the stage of battery charging, while preserving W as much as possible through the bucking (i.e. if they buck down from 48V@4A to 24V, that should be about 8A).
However, I have been told by solar tech supports that PWM converters do not buck, and that it is impossible for output current to exceed input current: So if the panel is outputting 48V @ 4A, then the battery charge will be 24V @ 4A. And if I want the current-multiplication of bucking, I need to go with an MPPT controller. I'm not 100% sure I believe that, but I haven't been able to put meters on my setup. |
H: Elenco Digital/Analog Trainer XK-700K Output voltage off
A week ago, I was given a project by my professor to do part of it and then give it to another student. After soldering the power supply section of it and testing the resistances/voltages, I get a voltage of -10.11V as an output of a -20V voltage regulator(LM337). The regulator is connected up to a variable resistor, although I get a voltage range of 0.729 to -10.11V on it.
I am not able to ask my professor what might be affecting this , as I don't have class until next Thursday.
The assembly manual is here.
Edit: I was tired yesterday, and as such, wasn't really thinking about what to do. I had gone through the troubleshooting guide on page 19 under "No voltage at variable output", and all of the causes were not it. This morning, after studying the board, I realized that two diodes below VR2 were soldered with the opposing polarity. I just soldered it, and I got a voltage of .7V CCW and -22V CW, which is within the 30% tolerance. Thanks you for your answers!
AI: The datasheet of the LM337 shows what the parts should be (the schematic is correct) and how to calculate the setting of the potentiometer and the input voltage to get an output voltage.
The 15VAC input has a peak voltage of 15V x 1.414= -21.2V and the rectifiers reduce it to about -20V. The 120 ohm resistor and 2k pot can be calculated for the LM337 to produce at least -18V.
Make sure that the input to the LM337 is at least -18V and check the values of the 120 ohms and 2k pot. |
H: Design my own footprint or find one?
I am designing a PCB based around the STM32H7 MCU, which is a LQFP144 package. I'm designing in Altium and was using the Altium vault to find components.
I noticed my specific MCU isn't on there, but other variations e.g. STM32F7 with a package size LQFP144 are.
Just starting out in PCB design, I'm looking for some advice.
Is it more common for me to just choose the other variation on Altium vault and then adjust the pinout and design my own schematic symbol considering the package type is the same, or is it more common to start designing a footprint from scratch?
I appreciate any advice or tips!
AI: More common way to define is subjective. Whatever method you choose, be sure to review thoroughly with respect to recommended PCB foot print from the datasheet of the actual micro controller. We have seen variations in the package dimensions as well as special pads considerations. Apart from adjusting the pinout please verify about the pad dimension compliance. Have it reviewed by a third person. |
H: Can capacitors be used to make a low-impedance ECL termination voltage?
I am trying to develop a circuit in which an RF sinusoid is put into the input of the ADCMP552 PECL output comparator and then the PECL output (square wave ish) is input to the MC100EP140 phase frequency detector, ideally as LV negative ECL. I have two questions:
In general, can I use the ADCMP552 as negative LVECL (even though it's only specced for positive ECL)?
If I need to go from PECL to NECL or vice versa, I would use a blocking cap and need a 50 ohm termination to Vtt= Vcc-2V. Could I use something like the following circuit as a proper 50 ohm termination? As far as I can tell, the DC level is determined by the resistors and the high frequency impedance is only the 50 ohm resistor.
simulate this circuit – Schematic created using CircuitLab
AI: In general, can I use the ADCMP552 as negative LVECL (even though it's only specced for positive ECL)?
Yes. The chip doesn't know which node in your circuit is "ground". So you can connect VCC to the node you call ground, and the chip's AGND pin to what you think of as -3.3 V, and the chip won't know anything but that there's 3.3 V potential difference between them.
But remember the input pins will need to be kept in the correct range relative to your new supply voltages. From that datasheet that means they need to be between AGND - 0.2 and VCC - 2.0 V.
Also the control input levels will be taken relative to the voltage of the AGND pin rather than the ground of your circuit.
Could I use something like the following circuit as a proper 50 ohm termination?
Assuming the output signal is more or less DC balanced (spends about 50% of the time at logic high and 50% of the time at logic low), something like that can work.
But you'll also need to provide a DC bias that allows the ECL output pins to source a few milliamps to keep the ECL output stage biased correctly. If you don't provide 50 ohms to VCC-2, you can typically provide ~130 ohms to VCC-3.3 V instead. |
H: Is placing the ground in this small signal model wrong?
There is an example in a text where it shows the small signal model of a circuit.
Below on the left there is a transistor circuit and on the right its small signal equivalent:
I'm a bit confused whether I'm not mistaken about a point since in all editions they have the same example. Is the ground connection where I put red question mark wrong? It seems to me there shouldn't be ground there, is that correct?
AI: That is an error.
If you treat that node as ground, then there's no AC voltage across \$r_{\pi 2}\$, and so no AC output voltage. |
H: Are all linear regulators bad at filtering input ripple? (or really as bad as Dave suggests)?
Background
In EEVBlog #1116, Dave discusses a method to remove power supply ripple, and goes on to show (see 5:17 to 6:15) that you cannot count on linear regulators to remove your input ripple. He gave a concrete example in the lab: at 10 kHz input ripple and MCP1700 (a CMOS LDO), as demonstrated on the 'scope, the ripple largely passes through.
While the rest of the video is meticulously explained, I feel that he present this example in a bit of a cherry-picked manner and omitted relevant details. I remember doing exactly the thing he warns against: I had a class-A headphone amplifier, which, when powered via a specific el-cheapo wall-wart at 12V, had a whistling sound on the output, caused by the switching noise of the power supply. In that occasion I lowered and cleaned the input voltage with a LM317, which completely removed the noise.
Note I'm not saying Dave is wrong - his warning is that a linear regulator, and a LDO in particular, may not solve your problems.
I have enough intuition to guess that what he talks about likely applies mostly to LDOs, since I've heard they can have stability issues and I guess the internal compensation against oscillation makes their pass element somewhat inert, so at frequencies like the 10 kHz he tests with, things can be quite bad. I don't see how they would fail the same test at 50-120 Hz, since this is a very common usage scenario which the IC designers likely thought about.
Question
Do all linear regulators perform poorly — say, have ripple rejection less than 15dB — at some combination of frequency and load current? Assuming other conditions aren't super-bad, i.e. not talking about 125°C and/or input voltage touching the dropout zone?
On a related note, is there a linear IC design, which is particularly good at rejecting input ripple all the way up to 500 kHz?
AI: In the case of the MCP1700, Dave is certainly correct.
Here's the ripple rejection versus frequency chart from the datasheet:
The datasheet itself claims 44dB of ripple rejection at 100Hz, which agrees with the chart.
It also clearly shows how poorly it handles high frequency noise.
The LM317, on the other hand, gives you better than 50dB of ripple rejection to at least 20kHz, then gets worse (though it doesn't get as bad as the MCP1700 until well over 1MHz.)
I'd conclude that just slapping in a linear regulator won't automagically fix your problems if you have ripple from a switching power supply causing interference. You need to check the datasheet of the linear regulator and see what it does given the frequency of the switching regulator.
A look at the datasheet of the LM1117 (also an LDO) also shows better than 40dB of ripple rejection to over 100kHz.
The LM1117 has a quiescent current of 5mA, which fits in with Spehro Pefhany's idea that the problem lies with the low quiescent current.
I wouldn't generalize to "LDO regulators are bad at high frequencies."
I'd just leave it at "some linear regulators are bad at high frequencies."
Dave was definitely cherry picking, but I think (I haven't watched the video) it was to make the point that you can't just pop in just any linear regulator to clean up after your switching regulator.
I've had a chance to watch the video. It is about using a capacitive multiplier to reduce ripple. The bit at the beginning is just a short introduction to explain why you might need to look for an alternative to a linear regulator to clean up ripple.
He doesn't go into any depth on why and which linear regulators might not be adequate because it is just an introduction to get to the main theme of the video.
Summary:
need to reduce ripple
folks often use a linear regulator
it can fail (example MCP1700)
here's an alternative technique
detailed description of capacitive multiplier (major bulk of the video) |
H: Why are there three transistor pairs in a class B power amplifier circuit?
I have a class B amplifier circuit to be done in lab. Why are three pair of transistors used in this? I suppose one is a Darlington pair but what is the requirement of the third one? Also, why is there an unequal mumber of diodes even if an equal number of PNP and NPN transistors are used?
AI: Why three pair of transistors are used in this?
I see only two pairs, the two Darlington pairs. The 2N3904 and 2N3906 are for output current limiting. These two are normally off unless so much current is flowing through the 1.2 Ohm resistors that enough voltage develops across them that the 2N3904 and 2N3906 activate. That will happen around \$V_{BE}\$ = 0.6 V. So around 0.5 A needs to flow through the 1.2 ohm resistors.
Also, why there is unequal number of diodes
Note that the bottom diode is drawn as one diode but the text says: "3x 1N4005". I guess they mean 3 diodes in series. I think that is plain wrong to draw it like that as it does not make it clear that the diodes should be in series. The reason to have 3 diodes instead of 2 diodes might be that the Darlington pair at the bottom (2N3906 + TIP32C) needs a higher biasing voltage compared to the Darlington pair at the top.
Edit the "3x 1N4005" appears to refer to all three diodes that are drawn. That would mean there is indeed only one diode at the bottom side. That means that the bottom PNP Darlington pair is biased at zero current and will only "kick in" when there is some signal. My guess is that this amplifier will have significant crossover distortion as a result of that.
In a standard class B amplifier it is typical to have the same number of diodes as there are Base-Emitter voltages stacked in the transistors. Here there are two Base-Emitter voltages stacked at both sides. Adding another diodes increases the voltage across the emitter resistor (that's the 1.2 ohm resistor) and increases the biasing (also called quiescent) current. If you do that on top and bottom sides the amplifier becomes a class AB amplifier. |
H: How much does voltage affect the light frequency output of an LED?
I have a large array of LEDs that I need to be true to their datasheet light frequency emission (ex 635 nm.) The LEDs require Vtyp @ 20 mA ranging from 2.2 V to 1.2 V. Some are within 0.1 V of each other.
In the interest of minimizing the number of Zener power circuits I need to add, could I put both a 1.8 V and 1.9 V on a 1.8 V power source without much light frequency deviation? Any way to know how much or guess the direction of the deviation?
I just remember from past experience that over-volting orange LEDs color-shifted them to yellow. I never knew if this was a bandgap/voltage thing or just overheating LED caused it.
AI: Use a ready made LED driver. Based on the number of LEDs and current needed, you can choose drivers available. An example is this from analog devices.
Depending n type of power supply you have, you can narrow down to a suitable LED driver.
You can also build a constant current driver using one opamp and a transistor. I can suggest.
The wavelength will vary slightly when the temperature of the LED is varied.
I have not come across variation in wavelength due to change in drive current
Reference for wavelength vs temperature
: https://dammedia.osram.info/media/resource/hires/osram-dam-3993183/LA%20G6SP_EN.pdf |
H: How to unground microwave transformer
I'm trying to make MOT tesla coil and would like to connect secondary coil in series. The low voltage end of secondary is connected to the body of the transformer. I don't particularly want to disconnect this as it may be useful for some other projects. Is it bad to connect the secondaries in series with secondary low end attached to transformer core but not connect the core to earth ground?
AI: A MOT has one great attraction for amateur coilers, it's cheap.
Aside from that, it's the worst possible choice for powering Tesla Coils.
Let's assume you've done the obvious thing with two MOTs, which is to use one in phase, one in antiphase, to get a balanced +/- 2kV about ground, as Jasen has illustrated in his answer, with the primaries in parallel.
Voltage too Low
As you've found out, the voltage is still too low for reliable spark-gap operation. So, you're looking to stack them.
Here we need to make a distinction between the MOTs you used to be able to get 20 years ago, and those of the 2020s. Today's MOTs are value-engineered to the max. Old MOTs used to have thick insulation around both primary and secondary, which was good for the full output voltage, and then some. Today's MOTs only insulate the outside and sides of the secondary to the full HV output voltage, the inside of the secondary and the whole primary are only insulated to take mains spikes, 1500V or so.
That means although you may have seen posts from coilers saying they had lifted the core connection and put secondaries in series, or floated the core on the output of another MOT (and I've done both), that's because they were using old style over-engineered MOTs. This trick will not work as well, or at all, with today's MOTs.
There is a safe way to series two MOTs, if you have a third. Connect two MOTs together secondary to core, secondary to core. Now power a third MOT from the 'hot primary'. All insulation is now running within its design stress.
simulate this circuit – Schematic created using CircuitLab
I may have the dots round the wrong way, I've not bothered to think it through. There are only two possibilities for phasing the connection of the hot primaries, one is right, the other will give zero output.
Let's say you use six MOTs to get the output of four in series, for a balanced +/- 4kV AC from ground. That's a lot of metal, and you're still barely at a voltage that gives adequate spark-gap results.
While a series connection will get you more volts when everything is working normally, sparks from a TC can get everywhere. A little extra voltage can break down the 3kV insulation. The first sparkover from your TC could trash your MOTs.
Voltage too High
The voltage is too high for safe 'on the bench' operation. I'm not saying that mains voltages are safe, but they're safe enough to use 'on the bench'. Below 1000V, any thickness of dry clothes will insulate against an accidental contact. A MOT secondary has a peak voltage of 3000V. That will jump through a layer of clothing.
Current too High
The current is far too high. Even if you leave the shunts in, they're not current-limiting like those of a Neon Sign Transformer (NST) are. If you get a shock from an NST, you're not guarranteed to be toast, that from a MOT is almost certainly fatal.
Availability
I feel your pain, NSTs are hard to come by. All the modern ones have GFCI or are high frequency, both of which renders them unsuitable for TC use. You need an old, second-hand, big-iron NST.
Join a dedicated coilers forum, google will find them for you. Get chatting to the old timers. Some will have NSTs that they're willing to sell or lend. It's sooooo much easier to start with the right tools, an NST, than to cobble inadequate and dangerous tools together.
A Good Way to make a Tesla Coil with a MOT
The one way a MOT does make a good TC is to balanced doubler rectify it to +/- 6kV DC, then double that through resonant charging into a rotary spark gap DC coil. It works very well, but it's rather complicated for a first project. |
H: Determining the voltage of 5 phase PMSM motor
As a part of the project, I have to design a 5-Phase PMSM motor, for which want to know the following:
How to determine the voltage ?
What should be the ideal voltage to use this motor in an electric car? Provided the car has 12 battery packs of 12 volts ( i.e 144 V supply from the battery?)
If, additionally could anyone suggest me some literatue, it would be a great help.
AI: Determine the voltage based on what? On the geometric parameters?
You would have to define what do you want to optimize: power? efficiency? cost? space? To keep things simple I would pick an standard voltage level. In your case I would pick 110 V (You still need a DC/DC regulator between battery and machine)
The best book about electric machine design that I know if is in german: "Berechnung elektrischer Maschinen" (https://www.wiley-vch.de/de/fachgebiete/naturwissenschaften/physik-11ph/elektrizitaetslehre-11pha/berechnung-elektrischer-maschinen-978-3-527-40525-1). In english I like "Design of Rotating Electrical Machines" (https://www.wiley.com/en-us/Design+of+Rotating+Electrical+Machines%2C+2nd+Edition-p-9781118581575) |
H: AVR gcrt1.S behavior
So basically i have decompiled unoptimized simple program and saw that it runs through gcrt1.S, and i dived in to assembly language and tried to understand what exactly it does. here is my code and my assumption of what it does
00000034 CLR R1 Clear Register
00000035 OUT 0x3F,R1 Out to I/O location
00000036 SER R28 Set Register
00000037 LDI R29,0x08 Load immediate
00000038 OUT 0x3E,R29 Out to I/O location
00000039 OUT 0x3D,R28 Out to I/O location
0000003A CALL 0x00000040 Call subroutine
0000003C JMP 0x00000050 Jump
0000003E JMP 0x00000000 Jump
Clear R1
Clear stratus register
Set R28 1111 1111
Here is where my questions start:
Load R29 from 0x08 (PORTC ?)
OUT to SPH <-R29
OUT to SPL <-R28
Call Main
The confuision that i have is why it loads byte from PORTC register, since the default would be 0x00 anyway
Microcontroller is atmega328p link to a datasheet
AI: This has nothing to do with PORTC register.
LDI means "Load Immediate", which says take a literal value and load it directly into a register.
LDI R29,0x08
Takes the literal value 0x08 and loads it into R29.
The function is basically initialising the stack pointer to point to the end of the RAM which can be seen from the below diagram to be 0x08FF. That means we need 0x8 in SPH and 0xFF in SPL.
As to why it uses SER R28 rather than LDI R28 0xFF, I don't know. Both are functionally equivalent, the same size and have the same side-effects.
To load from a port, the IN instruction is used:
IN R29,0x08
Would be load in the value from PORTC register into R29. |
H: Smoothing out current spikes so three-phase machine doesn't exceed site's electrical supply
We are looking at installing a machine at one of our manufacturing sites that draws around 120A at 415V three-phase (we are in the UK) but the maximum current we can draw at our site is 100A before the breakers trip. We have some other equipment at the site as well, but its all much smaller so most of that 100A should be available.
The machine operates for around 5 seconds, and then does nothing for around 3 minutes while we change over parts. Is it possible to smooth out the current spikes somehow so the site's electrical supply can handle it?
I have found some information about peak shaving and load smoothing systems but they generally seem to be large battery banks for covering peaks with time periods of hours not seconds.
We have discussed increasing the electrical supply with the power company and unfortunately it is not possible without some major upgrades in the area.
AI: Typical electrical supply systems are designed based on peak load requirements. This is fundamentally because power conversion has only become popular in recent decades as power electronics came in. In your case, it would ideal if you can find a machine that consumes load in a less intermittent way e.g lower load that just runs all the time. This allows better utilisation of equipment on utility company side and yours aswell.
Additionally for the machine you are interested in, check the total KVA rating and KW rating of the machine. If the machine consumes a lot of reactive power (low power factor, e.g a motor load,) you could locally manage reactive power supply by using capacitor banks and ensure your real load on the utility supply is less than the sanctioned load.
Now if your load has a power factor close to unity, it means you require 120A of real load and would have to design a buffer such that you consume less then 100A from utilities and still manage to run an intermittent load at 120Amps. This would mean quite an investment with a battery charger, a set of batteries and an inverter that allows delivering a higher power. The solution would likely be expensive and periodic battery replacements may actually make it completely unfeasible.
There is one more option and that would be carefully overloading your supply. But this option again requires careful study of what type of load checks are implemented by your utility supplier and regulations. Some utility companies only monitor average load while some are very specific of peak load and have digital meters that log and report over consumption. |
H: DCDC converter in series
I need to convert 5V (main power supply) to +/- 30V. I have two +/-15V DCDC converters and was wondering if I can connect them in series to generate the +30V and -30V rail?
My simple schematic
I tried simulating this circuit using Mplab MINDI, but there are only DC power sources and I am not sure it is valid to connect them the way I use them. The result show +/-30V. (When I connect the DC source on both ends the Amplitude is split to +15V and -15V therefore I set the amplitude to 30V).
The datasheet for the converter is here (pdf, 224kB)
UPDATE:
After the discussion in the comments I updated my circuit. This would mean I have the separate the supply GND from my circuit GND and also adding two more converters for -30V
AI: Per the datasheet these supplies have isolated outputs, so you can offset them from the input. All you need to do is avoid creating ground loops, and let the (nominal) 0V outputs float to the midpoint of the 30V rails each one produces. |
H: Extension for CCFL tubes
I have an inverter for cold cathode lights powered via a molex connector from a PC power supply, with a PCI/PCI-E slot bracket where is placed an ON/OFF switch, and I would need to use one light at a longer distance, exactly at a distance of 7 and half metres. There is a 2-pin connector leading to the inverter. From what I have read, cables leading to a cold cathode from the inverter hasn't to be long, so it seems like that the only option is by using a 2-pin extension cable. Can it be used like this and if yes, what wire I need to use for it? Assuming there isn't such extension available to purchase, can I cut the cable and solder the wires to create an extension?
Some more information:
Input voltage of the inverter: 12 V
Output voltage of the inverter: 680 V
Current draw: 5 mA
AI: Just to make it clear: you're right that you should extend the 12 V side, not the 680 V. Not only should the bulb side wiring be short, it must also have it's insulation in good shape.
680 V @ 5 mA is about 3.4 W
By the 12 V side, that's around 360 mA at a low 80% efficiency for the inverter.
Low enough power that you shouldn't worry much about your method for extending the existing 12 V wiring.
For a very clean setup, you could buy Molex pins that can be crimped with a pair of pliers and 20 AWG wire to run from the PSU to the inverter without splicing anything. That's what I'd do.
If you want it cheaper, you could safely get away with cutting the existing wiring and soldering or using a butt connector to extend the additional 7½ meters. |
H: what is I2c address of BNO055?
I made a custom circuit with bno055 it shows i2c address 0x70 is it possible?
I used the Arduino i2c scanner. I am not getting any data aswell
nothing else is connected to Arduino nano board as well,
I am using 5v to 3v3 TTL logic level converter board as well
vdd 3v3
11 and 14 not connected to Arduino
I tested with 3v3 esp32 using Arduino i2c scanner,
Still, I am getting the same address 0x70, without the converter, above PCB directly connected to esp32
AI: No, 0x70 address should not be possible. Make sure pins PS0/PS1 (protocol select) are connected to the ground, to activate I2C protocol.
Then, depending on address selection input COM3 the BNO055 address will be either 0x28 or 0x29. Decide which address you want to use and connect COM3 pin to either GND or 3.3V directly.
Also, depending on I2C API you are using, the addresses might be represented shifted to the left (to make space for RW bit). These APIs will use 0x50 and 0x52 correspondingly. Still no 0x70 in picture. |
H: Why is this MOSFET KVL to find VDS not right?
There was an answer provided for this question I'm working on, but it seems that my answer was wrong. The sticky note has was the "correct answer" is supposed to be, but I don't understand why V-minus on the source is not included in that KVL equation.
AI: An ideal current source dictates the current, but can have any voltage across it. The voltage across it is dictated by external components.
Likewise, an ideal voltage source dictates the voltage, but can have any current flowing through it. The current is dictated by external components (which may be on their turn be controlled by the voltage of said voltage source).
Because \$V^{\_}\$ is below the ideal current source and the voltage drop across an ideal current source can be anything, it is useless to use \$V^{\_}\$: it will not say anything about \$V_S\$ |
H: Can I use a 2.4 GHz rated parabolic MIMO antenna for 700 MHz Verizon 4G LTE data?
Can I use a 2.4 GHz rated parabolic MIMO antenna for 700 MHz Verizon 4G LTE data?
It seems 700 MHz are a long ways from the range of a 2.4 GHz antenna, but I have seen people marketing similar looking parabolic antennas that claim they are wide spectrum and go down to 600 Mhz and up to 5GHz... I'm just not sure at what attenuation though?
Will the same Verizon tower switch me from 700 MHz to one of their higher frequencies with better reception?
Verizon Wireless appears to utilize multiple 4G LTE frequencies like 2.1 GHz, 1.9 GHz, 1.7 GHz, 850 MHz, and 700 MHz. I don't know if they would they would responsively switch me from 700 MHz to a higher frequency if my signal improves though as some people report??? This would be important if I need an antenna that capable of working from 700 MHz to 2.1 GHz.
How I know the band I'm using: I used my iPhone to figure out I'm using band 13 for communication with my local Verizon tower, which is 700 Mhz by following these direction. I have LTE data miles away from the tower but it's not a good connection so I'm looking to get a highly directional antenna for my JetPack 7730L.
Specific use case
Here's the 900mm-wide (about 3 feet) parabolic antenna I'm looking at so you can have a specific example to pick on.
Added 2020-01-28: I did my own test to see if Verizon switches bands based on signal quality. You can see the video here.
AI: Can I use a 2.4 GHz rated parabolic MIMO antenna for 700 MHz Verizon 4G LTE data?
The gain of an antenna, that is, how much it focuses in one direction, is pretty much proportional to its size divided by the wavelength.
Generally, antennas don't work (well) for frequencies they're not designed for, but you can consider a parabolic dish more of a reflector than an actual antenna – the feed (which is mounted in the focal point) is what actually converts the electromagnetic wave from free space to a coax waveguide (or vice versa).
So, replace the feed with something that works for 700 MHz and you got a directive antenna that's roughly only 700/2400 = 7/24 ~= 1/3 as directive as it would've been for a signal at 2.4 GHz.
Now comes the problem: you don't seem to have such a feed (and you're right, you need a multi-band antenna as feed).
In this situation, you'd just buy a cellular-optimized multi-band antenna that has some gain in itself: it typically will have less gain than what you'd get from a well-matched dish, but considering this is all a bit impossible to calibrate and do right, it'll probably work much better than trying to attach a low-gain multi-band feed to your dish.
Generally, what you want to do is quite possible illegal: in many legislations the power times the gain is limited, and if your phone is legal with the little gain its antenna has, it's probably illegal with the gain of a highly directive antenna.
Will the same Verizon tower switch me from 700 MHz to one of their higher frequencies with better reception?
Only the base station configuration of Verizon's cellular infrastructure can answer that. But, generally, the lower the frequency, the better your reception is over a long-distance link: so, 700 MHz is pretty much the best you can get.
"as some people report": Um. "some people" are a terrible source. |
H: Swapping out RJ-45 connector on Differential I2C circuit
I'm trying to use Sparkfun's Differential I2C Breakout circuit into my own design, and I'm looking to replace the RJ-45 connector. It's too big (having a footprint size of 15.24 mm x 15.24 mm), and I have some requirements that I need to meet. The original board uses an Ethernet cable to transmit the differential I2C signals across long distances. I'm trying to do the same with another connector.
Due to the environment that my project will be in, I have to use a shielded, twisted-pair cable, with the length of the slave sensor being 20 meters (max) away from the I2C master. With these constraints, I was thinking about using HDMI, due to it being readily available and meeting all of these requirements. However, based on some footprints I researched, the HDMI footprint is too big. Thus, I'm thinking about using a micro-HDMI to HDMI cable instead. HDMI has more than enough pins for my needs, but I was wondering if there were any other cable alternatives that will fit my needs and has a small PCB footprint?
EDIT: So, after some discussion and thinking, mini/micro HDMI might be okay in the long run for 3 meters, but in the long run, when I need 20 meters, HDMI is a no-go. It won't be enough to transmit power, so I'm going to need a higher gauge wire than AWG-30. I can't think of any pre-assembled cable assemblies that fit the length and other requirements for shielding, so is my only choice to make my own cables for this endeavor?
EDIT: To give more information about my board, it's more or less an I2C multiplexer board. I'm working off of a Raspberry Pi Zero and an Arduino Nano, and the size of the board is 2 inches by 3 inches. This configuration is meant to read from 8 I2C sensors, so I'm trying to fit eight differential I2C circuits onto one board. The Pi Zero and the Arduino have to be mounted on the board (though for the Pi, I'm not including the 40-pin header as it's not needed); therefore, most of the space is being taken up by the mounting holes of the Pi Zero and the Arduino's footprint, if that gives any indication of the amount of space I'm left with. So, with the 8 I2C sensors, imagine having 8 of the Differential I2C Breakout circuits on one board. I'm trying to find a connector that can deliver the two differential signal pairs as well as power/ground just like the RJ-45 used in Sparkfun's board. In terms of maximum size, given the size of the RJ-45, my max dimensions for the connector is approximately 10 mm by 10 mm. This is mainly just to ensure that there is enough space for adequate routing of the 8 differential circuits.
AI: You can use RJ14/RJ25 connectors with 4P4C plug and any 2x2 UTP cable. These are smaller than RJ45.
Note, that the original board has too much empty space and too many connectors. If all you need is one I2C line adapter, you can make PCB roughly the size of 6p6c jack footprint with all SMD parts (including I2C jack) on the other side of the board.
You can use micro HDMI cable, but those get quite expensive over 6ft. Besides, cables longer than 10m are usually heavy 24AWG with standard HDMI. Most (if not all) of long micro cables are active, i.e. they have built-in signal booster chips that require power. IMHO they are not worth it, considering relatively small footprint size reduction.
UPDATE:
Just to clarify - the reason I suggested registered jack is because it is historically used for many purposes, so one cannot really guess the function by appearance. This is not so for HDMI, USB and similar connectors, where people expect them to function a certain way. If you use them for your project expect someone eventually trying to plug expensive smartphone or camera into it, and then suing you for damages.
Have you tried a simple search for "rectangular connector"? Some of them have 0.8mm pitch and footprint smaller than HDMI/USB, for example MQ172 and DF52 series from Hirose, or CLICK-Mate from Molex and many others.
Or is it that when you say "find the right cable to go with it" you mean pre-terminated cable of required length? Then you definitely out of luck, because at 20m you won't find pre-made cable for non-common connector.
UPDATE 2:
I think by fixating on minimizing PCB footprint you are missing the whole point of miniaturization, which is to minimize the space occupied by final product including all the connections required for normal operation. Let me illustrate the point: on top is "IX Industrial" connector with PCB footprint 12.1 x 9.8 mm. Note, that routing traces to those SMD pins might take up more space yet. On the bottom is CAT5 certified 4P4C jack and RJ11 plug, with PCB footprint 12.0 x 12.55 mm.
The difference for the PCB is negligible, however the plug in the first case protrudes 18 mm more from the device. If you consider minimal bending radius of 10-conductor shielded cable comparing to 4-conductor UTP you will be adding easily 40mm to your device dimensions, while saving 2.7mm on PCB
Now, I could not find ready made IX cable longer than 5m, and that one was $50. On the other hand 20m UTP + 2 plugs can be made for about $4.50, if buying cable in bulk and crimping plugs yourself.
If all this does not sound important to you, at least go with something like MQ172 series I've mentioned above. They also have huge plugs, but at least you can terminate those yourself to the cable of any length. And the jack footprint is even smaller at 10 x 8 mm. |
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