text stringlengths 83 79.5k |
|---|
H: Confusion regarding Fixed-Biased configuration of JFET
This is the picture of a fixed-biased JFET, taken from a book :-
This is written in the book, relating to the above pic :-
I am unable to understand why \$ V_{GS} \$ has a different polarity than \$ V_{GG} \$ in the first place. Shouldn't they be of the same polarity according to the connected terminals ?
AI: Shouldn't they be of the same polarity according to the connected
terminals ?
No, the minus (-) terminal of the battery is indeed connected to the plus (+) side of \$V_{GS}\$, that is, the JFET gate (G).
All things considered, it's just an intrincate way of saying that \$V_{GS}\$ must be a negative voltage, i.e. the gate must have a negative bias voltage applied (when source is grounded).
Note: \$V_{GS}\$ means "Gate (G) to Source (S) Voltage". Voltage is a potential difference, and by definition that difference is \$V_G\$ ("positive" terminal) minus \$V_S\$ ("negative" terminal). However, such a difference can be negative (as it is in this case) because it's just a reference, a convention. The + and - signs doesn't tell you anything about which terminal is actually at a higher potential, just how the potential difference (voltage) has to be calculated. |
H: Darlington array: How to output desired voltage at uln2803a driver colectors?
Someone suggested this driver array to get the current I need:
datasheet
I also need a 12V signal and about a current of 100mA in order to control a relay coil. My 12V signal would come from a logic gate that will provide a current of I = 10mA. So here is where I need the driver. But I need to keep 12V at the driver outputs.
This is my first time working with this kind of device.
Reading datasheet I don't understand how to get Vout = 12V. It says that Vout = VCE and max rate is 50V. But it also says that Icoil = (V coil supply - VCE(sat))/Rcoil. So I don't know if VCE must be VCE(sat).
My questions:
Is V coil supply the desired VCE voltage at the output? Must I do
something in order to keep Vout = 12V when I apply Vin = 12V = VBase?
By the way, what must I do in order to keep the colector current
that coils are needing?
"The collector current rating of each darlington pair is 500mA" --> 500mA per channel, is it?
AI: Reading datasheet I don't understand how to get Vout = 12V.
You need a 12 volt power supply capable of supplying the various load currents. The ULN2803 doesn't magically produce 12 volts without a power supply and even then, its outputs are either "on" (conducting to ground) or "off" (open circuit). It has what is known as "open collector" outputs and you insert the load between a collector and the 12 volts (from the power supply). The negative end of the 12 volt power supply connects to pin 9 of the ULN2803.
You need an input of about 3 volts or higher to activate the channel of the ULN2803 you are connecting your load to. |
H: What is the formula for calculating the no load current of a 3-phase motor?
I am looking for the formula, not a rule of thumb. Is there a way to calculate the no-load current?
AI: As both Andy aka and Bimpelrekkie have commented, there is no useful formula because there are far too many variables both known and unknown. It depends on the design and type (not all motors are induction) of the motor and how well it has been maintained. By far the easiest way of finding out is to get yourself a clamp on ammeter (readily available from multiple sources) and actually measure it on the particular motor in which you are interested. |
H: TTL to NIM logic translation Logic Gate Issue
NIM is a standard used in nuclear physics. I'm facing an issue with a logic gate being used in my TTL to NIM translation circuit, and I'm not sure what is entirely wrong with it. For a little background, I'm trying to replicate a TTL to NIM logic translation circuit as demonstrated in a reference schematic linked below, but I'm having some issues regarding a specific part of the circuit, specifically the logic gate.
Here's a link to my reference schematic, but if you prefer, I'll draw out my circuit below.
simulate this circuit – Schematic created using CircuitLab
It's a little modified from the original circuit with the addition of a pull-down resistor at my TTL logic input at the gate as well as using 5 pF capacitors instead of 3.3p, but otherwise, the rest are the same.
The original schematic used an XOR gate, and it seems to be the F86 XOR gate. I used the 74LS386 quad dual-input XOR gate to substitute for it, but it doesn't seem to be working properly. Setting one input to ground, I used a switch to set the other input to 3.3 V for the TTL high input (and when the switch is open, a pull-down resistor for that input pulls it down to 0 volts for logic 0). The output of the gate goes to the rest of the circuit, which should produce a NIM-logic current signal (0 mA for logic 0, -15 mA for logic 1). However, somehow, my XOR gate output doesn't change at all, and the NIM-logic stays constant at -15 mA whether or not my input switch is closed (while the output of the logic gate is between -0.5 and -0.6 V). This behavior also occurs when a gate input is set to VCC (+5V).
Seeing as how this is not behaving correctly, I swapped out the IC with the DM7404N hex inverter IC. Logically, it should behave as if one of the XOR inputs is set to VCC, logic high. Swapping it out and putting a pull-down resistor at the input, the circuit behaves exactly as I hoped it would. The output of the inverter goes from 0.7 V to 3.4V depending on the input, and the NIM current correctly goes from -15 mA to 0. Seeing as how the circuit works with the inverter and not with the XOR gate, I was wondering what could be the reason why? I thought that perhaps the inverter circuit is more simple and allows for larger output current than the XOR gate, but I wonder if that is truly the case?
To be fair, there have been instances where using the XOR gate gives the correct intended result, but this doesn't seem to be consistent anymore. Whereas with the inverter replacing the XOR gate, it seems to work all the time.
EDIT: After reading the comments, I thought to try to use a different XOR gate of a different technology type, specifically the MC14507, the CD4030AY, and the SCC4070BE. I did some research and found that these gates are based on MOS technology which should allow for more current flow, and that seems to be the case. The NIM logic signal switches consistently, so is it safe to assume that all my problems are just using the LS XOR gate?
AI: I'm not sure how that worked even with the original 'F86 gate — it has a specified maximum IOH of -1 mA.
In any case, I would recommend ditching the gate altogether and using another differential amplifier for input.
simulate this circuit – Schematic created using CircuitLab
Q2, R3 and R4 establish the switching threshold for the TTL input. The rest of the circuit is the same as your reference.
If you still want switchable polarity, connect the 'x86 gate to the TTL in shown here. |
H: Relationship between voltage and current of a power transformer
I'm currently analyzing data from a power transformer and I stumble over the circumstance that voltage and current is almost not related to each other. Since I'm not an engineer I wonder why is this?
From my knowledge, the voltage must drop when current flows but I know it is possible to build voltage-stable circuits. This is probably also valid for transformers because I think nobody would like to have a different voltage when (hundreds) ones neighbours need power as well.
Is this (simple) explanation correct or is there another reason?
AI: you can model a transformer like this
simulate this circuit – Schematic created using CircuitLab |
H: Periodic timer not working as expected on TM4C123 MCU
I am starting to learn how to use timers/interrupts on the TM4C123 evaluation board (TM4C123GH6PM MCU).
In this example I am configuring a timer to create 1 second delays to toggle an on-board LED on and off. But when I run the code in real time on the board, the red LED appears to be on all the time. If I step through the code with breakpoints in my while(1) loop where I poll the timer register, it appears to work fine. (I am not using interrupts with this timer, just polling).
I haven't attached the individual register breakdowns from the datasheet as there are quite a few.
Has anyone got any ideas as to why this is not working as expected?
Below is my code for the example I am following from the TM4C123 datasheet:
And here is my code:
#include "include/tm4c123gh6pm.h"
#define RED_LED (1U << 1)
#define BLUE_LED (1U << 2)
#define GREEN_LED (1U << 3)
int main()
{
SYSCTL_RCGCGPIO_R = 0x20U; //Enabling clock to port F.
GPIO_PORTF_LOCK_R = 0x4C4F434BU; //Unlocking the port F lock register.
GPIO_PORTF_CR_R = 0xFFU; //Enabling the port F commit register.
GPIO_PORTF_DIR_R = 0x0EU; //Setting the port F pins as outputs.
GPIO_PORTF_DEN_R = 0x1FU; //Enabling digital writing to port F.
/* To use a GPTM, the appropriate TIMERn bit must be set in the RCGCTIMER or RCGCWTIMER
register (see page 338 and page 357). If using any CCP pins, the clock to the appropriate GPIO
module must be enabled via the RCGCGPIO register (see page 340). To find out which GPIO port
to enable, refer to Table 23-4 on page 1344. Configure the PMCn fields in the GPIOPCTL register to
assign the CCP signals to the appropriate pins (see page 688 and Table 23-5 on page 1351). */
SYSCTL_RCGCTIMER_R = 0x01U; //Enable timer 0 clock signal.
/* 1. Ensure the timer is disabled (the TnEN bit in the GPTMCTL register is cleared) before making
any changes. */
TIMER0_CTL_R &= ~(1<<0); //Disabling timer.
/* 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0000. */
TIMER0_CFG_R = 0x00000000U; //Writing 0 hex to this register.
/* 3. Configure the TnMR field in the GPTM Timer n Mode Register (GPTMTnMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode. */
TIMER0_TAMR_R |= (0x2<<0); //Setting timer 0 to periodic mode.
/* 4. Optionally configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in the GPTMTnMR register
to select whether to capture the value of the free-running timer at time-out, use an external
trigger to start counting, configure an additional trigger or interrupt, and count up or down. */
TIMER0_TAMR_R &= ~(1<<4); //Configured as count down timer.
/* 5. Load the start value into the GPTM Timer n Interval Load Register (GPTMTnILR). */
TIMER0_TAILR_R = 0x00F42400; //16,000,000Mhz clock, 1 sec delays.
/* 6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register
(GPTMIMR). */
//Interrupts are not used, I am polling the timer0 regsiter as seen below in while(1) loop.
/* 7. Set the TnEN bit in the GPTMCTL register to enable the timer and start counting. */
TIMER0_CTL_R |= (1<<0); //Enabling timer
/* 8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases,
the status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear
Register (GPTMICR). */
while(1)
{
if( (TIMER0_RIS_R & 0x00000001) == 1) //Checking if timer has finished counting.
TIMER0_ICR_R |= (1<<0); //Clearing the finished timing bit in TIMER0_RIS_R.
GPIO_PORTF_DATA_R ^= (1U << 1); //Toggling the RED_LED output.
}
}
AI: In your while loop, you forgot your squiggly brackets.
It should be:
while(1)
{
if( (TIMER0_RIS_R & 0x00000001) == 1) //Checking if timer has finished counting.
{
TIMER0_ICR_R |= (1<<0); //Clearing the finished timing bit in TIMER0_RIS_R.
GPIO_PORTF_DATA_R ^= (1U << 1); //Toggling the RED_LED output.
}
} |
H: Problem with 4-SMD Crystal / PIC16F1575
I'm trying to work with 32Mhz 4-SMD Crystal. (ASX3F-32M-FA100A4) with two capacitors: 10 pF (attached datasheet)
The IC I choosed is the PIC16f1575. And using MPLABX-IDE MCC
I performed the connection as in the pictures below.
When I select INTOSC in MCC everythings works fine, but if I change the selection INTOSC to ECH in MCC as at the picture below the IC doesnt work.
It only LED blink code in main loop.
void main(void){
SYSTEM_Initialize();
INTCONbits.GIE = 1;INTCONbits.PEIE = 1;
while (1)
{
LED_Toggle();
__delay_ms(500);
}
}
Is there a wrong connection between pic and crystal?
Is that crystal not suited for this usage?
Something missing on the code?
Rest of the configuration Code:
// CONFIG1
#pragma config FOSC = ECH // Oscillator Selection Bits->ECH, External Clock, High Power Mode (4-32 MHz); device clock supplied to CLKIN pin
#pragma config WDTE = OFF // Watchdog Timer Enable->WDT disabled
#pragma config PWRTE = OFF // Power-up Timer Enable->PWRT disabled
#pragma config MCLRE = ON // MCLR Pin Function Select->MCLR/VPP pin function is MCLR
#pragma config CP = ON // Flash Program Memory Code Protection->Program memory code protection is enabled
#pragma config BOREN = ON // Brown-out Reset Enable->Brown-out Reset enabled
#pragma config CLKOUTEN = ON // Clock Out Enable->CLKOUT function is enabled on the CLKOUT pin
// CONFIG2
#pragma config WRT = OFF // Flash Memory Self-Write Protection->Write protection off
#pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit->PPSLOCKED Bit Can Be Cleared & Set Once
#pragma config PLLEN = OFF // PLL Enable->4x PLL disabled
#pragma config STVREN = ON // Stack Overflow/Underflow Reset Enable->Stack Overflow or Underflow will cause a Reset
#pragma config BORV = LO // Brown-out Reset Voltage Selection->Brown-out Reset Voltage (Vbor), low trip point selected.
#pragma config LPBOREN = OFF // Low Power Brown-out Reset enable bit->LPBOR is disabled
#pragma config LVP = OFF // Low-Voltage Programming Enable->High-voltage on MCLR/VPP must be used for programming
And Initialization;
void OSCILLATOR_Initialize(void)
{
// SCS FOSC; SPLLEN disabled; IRCF 8MHz_HF;
OSCCON = 0x70;
// TUN 0;
OSCTUNE = 0x00;
// SBOREN disabled; BORFS disabled;
BORCON = 0x00;
}
AI: From Microchip:
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the CLKIN input. CLKOUT is
available for general purpose I/O or CLKOUT.
Figure 5-2 shows the pin connections for EC mode
This chip is not designed with an internal clock source from an RC oscillator. But it has no oscillator to run a crystal. If you want an external 32MHz clock source, you need to generate it and then apply it to the chip. |
H: Meaning of (*(__IO uint16_t*)PAGE0_BASE_ADDRESS) variable declaration
There is a variable declaration:
uint16_t status = (*(__IO uint16_t*)PAGE0_BASE_ADDRESS);
__IO is the precompiler directive that becomes the keyword volatile. PAGE0_BASE_ADDRESS is the hex address, say 0x08000000;
I can't get my head around what this statement actually does. Anyone help please?
AI: PAGE0_BASE_ADDRESS is an integer value; the subexpression (__IO uint16_t*)PAGE0_BASE_ADDRESS) expands to (volatile uint16_t*)PAGE0_BASE_ADDRESS), which casts the integer to a volatile pointer to 16-bit unsigned integer.
Finally, the outermost asterisk is used to deference this pointer. Overall, the statement reads a 16-bit integer from the given address, considering it as a pointer to volatile memory1, meaning that it must be read/written from memory each time it is accessed (i.e. the compiler should not cache it in a register or assume that its value remains the same each time the given code is executed).
1 Not the same as a volatile pointer to normal memory (i.e. uint16_t * volatile) |
H: If I am discharging a battery at 30% of its energy and then charging it at 0.8C. How long will it take to be completely charged?
Suppose that I have a lead acid battery that:
Can (and will) be discharged by using 70% of its energy (energy left is 30%)
When the battery is at 30%, I will recharge it at 0.8C.
How long will the battery need to be completely charged?
My reasoning would be the following:
$$V_n = 100 V$$
$$Capacity = 50Ah$$
Then the (theoretical) energy that the battery can deliver is 100*50=5 kWh. If I use 70% of it then that 70% is 3.5 kWh. To get the battery back to its original state (neglecting charging efficiency) I need to put 3.5 kWh back into the battery. If I recharge it at 0.8C=40Ah assuming 40 A of current through the battery then
$$t=3.5kWh/(100 V *40 A)=3150 s = 52.5 minutes$$
Bonus point: What does recharging a battery at 0.8C means? 0.8C is a measure of capacity but in practice I'll have a current running through the battery terminals. How do I reconcile the two?
AI: 1C charge or discharge rate is one battery capacity per hour. As the capacity is given in Ah, Ah/h = A.
If you've discharged 70% of your capacity, and recharge at 0.8 (80%) of your capacity per hour, recharge will take about an hour. |
H: How do I find an ADC circuit's bandwidth experimentally?
I'm trying to measure the bandwidth of a circuit that I've built. It's an analogue-to-digital converter (ADC) with some input protection and biasing. The ADC samples at a constant/fixed 50 kSa/s.
My approach is to inject a 2 V sine wave of variable frequency \$f_{in}\$ and take the maximum (\$Vmax\$) and minimum (\$Vmin\$) samples. That gives me \$Vpp = Vmax - Vmin\$, and I sweep \$fin\$ until \$ Vpp = 2 \sqrt{\frac{1}{2}}\ V \approx 1.41\ V \$.
I've read the Wikipedia articles Bandwidth (signal processing) and Half-power point, but I remain confused.
When I find the -3 dB point, what is the corresponding official bandwidth I've found? Is it \$fin\$ or \$ \frac{fin}{2} \$ with consideration of the Nyquist rate?
AI: The bandwidth is the frequency for which the output is down 3 dB. It it a function of the analog portion of your circuit and does not depend on the sample rate nor the Nyquist rate which are basically digital concepts. Thus, in your experiment, the bandwith will be the frequency, fin, for which the output has dropped by 3 dB. |
H: Transistor pad layout for efficient use of prober
As we are a materials company the expertise is not in EE, so I am asking a very simple question. I tried to search online for this, but could not find an answer. We are making transistors with our special materials and need to put many on a test chip. Hooking each one of them up with their own pads we quickly run out of pads and are limited to fewer devices.
What strategies exist to "chain" the structures together to share pads? What risks are there in doing this?
See the example of the four transistors that use 12 pads to test. Can the source and/or drain be one common pad and only need to change the tester for the gate?
Any references that would be helpful would be greatly appreciated.
AI: Any time you add probe pads, you're sacrificing the density of test devices. The density you end up with depends on how accurately you can probe, how small a probe pad you can make, and how many terminals on your transistor you can share.
A word of caution, make sure you know what the minimum pitch and pad size you can probe effectively is using your equipment. It does you no good to have twice as many structures to test if it takes you much longer to land probes.
From a typical 4 terminal device perspective, the main question is how many pads can you save by tying them together, and what can go wrong.
Body/Substrate: usually safe to connect together. Exceptions include cases where you expect a significant leakage current from any other terminal to the substrate.
Source: usually safe to connect together. You give up the ability to measure source to substrate leakage/diode of an individual device when the source voltage is different from the substrate. The RDSon of your MOSFET should be much larger than your metal resistance, or else it will impact your measurement.
Gate: This one is really tempting to short together, but it is also a dangerous one. As long as your gate current is effectively zero, like in a traditional MOSFET, you can get away with shorting gates. If you have limited isolation to your channel, like in a MESFET, JFET, or HEMT, then you should probably pass. My experience has been that a shared gate test structure fails in difficult to detect ways, and can subtly change measurements. Consider the case where you have 10 transistors in a structure with substrate, source, and gate shorted. If one of the gates has failed short, it will reduce the gate voltage seen by all 10 transistors, without giving any indication other than gate current. In that case, all 10 devices are unusable even though only 1 failed. Device failure can come from manufacturing yield or electrical over stress, and ESD protection is typically omitted in these structures.
Drain: shorting these instead of the gates is not a good idea. You would need to actively drive every gate, even those not in use. The drain current, which is one of the primary measurements, always will have IDSoff of all devices combined in parallel. Don't do this.
My preference would be to have as few shorted terminals as possible. Shorting the source is relatively low risk, but higher current measurements will suffer. Shorting all gates and shorting all sources is something I wouldn't do for anything more than a process monitoring structure, preferably not for device characterization.
Keysight has a pretty good book on transistor characterization from the measurement perspective: The Parametric Measurement Handbook. There's a lot of good general information, and there's a decent amount of up-selling a $100-500k semiconductor parameter measurement tool. |
H: ESD Protection diode polarity
I'm using the following ESD protection diode:
On the datasheet it says:
MOUNTING POSITION: Any
Does it mean I can assemble it at any polarity?
(switch cathode and anode connections)
AI: Yes. Bidirectional ESD/TVS are agnostic to mounting position because either way presents exactly the same electrical characteristics - both terminals are ANODES |
H: Help identifying tantalum capacitor marked E105
I am trying to repair a device that was handed to me. It has a broken tantalum capacitor with a missing lead, so it needs replacement. However I'm having trouble identifying its capacitance, voltage etc. I believe it's a KEMET T494 series but I can't say for sure. The markings on the capacitor are 'E105'. Does anyone have any ideas?
AI: "105" usually means 10 pF x 100000. The "5" parts represents the number of zeros in the multiplier. "104" would be 100 nF. "103" would be 10 nF and "102" would be 1 nF.
Many companies use "E" to symbolize 25 volts and, as an example I've seen "A" used to represent 4.0 volts, B to represent 6.3 volts, C to represent 10 volts, D to represent 15 (or sometimes 16) volts hence, E represents 25 volts.
But, there are other code systems for the capacitor's voltage rating such as this: -
However, and luckily, E represents 25 volts in both systems. Another system that also uses "E" to represent 25 volts: - |
H: XADC Current Sensing Reference Design
Please refer to this reference design for AC701 (snippet below).
The schematics, specifically the current sensing sections in pages 34-36, show this:
I want to understand why, for the REF output of INA333, there is a pull-up of 0.05V?
AI: I want to understand why, for the REF output of INA333, there is a
pull-up of 0.05V?
The minimum voltage that the INA333 can produce when the negative power rail is attached to 0 volts is typically 50 mV so, if the REF pin were tied directly to ground, the output would not change for inputs that might otherwise have caused a 50 mV rise in the output.
By attaching REF to 50.7 mV, it means you get linearity from the "null" input condition upwards. The price you pay is that you have a 50 mV offset but, given that your circuit implies that a differential ADC is used, this is of no-consequence. |
H: Footprint unclear part
I am trying to draw a footprint of some component which has 8 pins but in the document they shared for outline dimensions and footprint:
Outline dimensions
Footprint
There is some rectangle in the middle of the footprint. That has sx and sy dimensions. That part confused my mind. Is it silkscreen?
AI: It's a thermal pad to improve heat conductivity thus allowing the device to operate with higher electrical powers. Check the data sheet of the actual part. |
H: Why is the Digital 0 not 0V in computer systems?
I'm taking a computer system design course and my professor told us that in digital systems, the conventional voltages used to denote a digital 0 and a digital 1 have changed over the years.
Apparently, back in the 80s, 5 V was used as a 'high' and 1 V was used to denote a 'low'.
Nowadays, a 'high' is 0.75 V and a 'low' is around 0.23 V.
He added that in the near future, we may shift to a system where 0.4 V denotes a high, and 0.05 V, a low.
He argued that these values are getting smaller so that we can reduce our power consumption. If that's the case, why do we take the trouble to set the 'low' to any positive voltage at all? Why don't we just set it to the true 0 V (neutral from the power lines, I guess) voltage?
AI: You are confusing the "ideal" value with the valid input range.
In usual logic, in ideal conditions, the logical zero would be precisely 0V. However, nothing is perfect in real world, and an electronic output has a certain tolerance. The real output voltage depends on the quality of wires, EMI noise, current it needs to supply etc. To accommodate these imperfections, the logic inputs treat a whole range of voltage as 0 (or 1). See the picture in Andy's answer.
What your lecturer probably meant by 0.75V is one of the points making the logical 0 range.
Note there is also an empty range between 0 and 1. If the input voltage falls here, the input circuit cannot guarantee proper operation, so this area is said to be forbidden. |
H: Measuring the activation time of a solenoid
I'm trying to measure the activation time of a pull-type solenoid.
When the solenoid doesn't have a load connected to it, you can measure its activation time through the current it consumes.
At first, the solenoid will consume current until the magnetic field is strong enough to move the armature, at which point the current consumption decreases until the armature has reached its holding position. At that point the current will rise a bit more until it stabilizes.
However, if there is a load attached to the armature, the curve of current consumption never dips, which means that you can't quite tell at what point the armature is fully pulled in.
I'm wondering what technique could be used or is standard for measuring the time it takes the armature to reach the end position with a load.
I've thought of making the load close a circuit so you could measure the time between activation of the solenoid and the closing of the measuring circuit but I'm wondering if there are other approaches which I haven't thought of.
(p.s. if this is off-topic let me know and I'll remove the question)
Edit: Preferably the solution can be embedded in a machine with up to 1000 solenoids. This means that the added hardware (cost for example) needs to be somewhat realistic (i.e. no 200$ camera per solenoid ;) )
AI: I'm wondering if there are other approaches which I haven't thought
of.
Idea:
If you superimpose a small high frequency AC signal on top of the DC that drives the solenoid, you can infer the inductance change from the inactive to activated position. When the armature is activated, the coil inductance is usually (and measurably) higher.
The high frequency signal needs to be high enough so that one cycle provides enough time resolution but not so high that eddy current losses swamp that signal amplitude change. Feed the signal from a signal generator via an impedance that is nominally the reactance of the coil to obtain optimized signal amplitude change.
Your signal amplitude should be chosen so that its nominal amplitude barely affects normal DC operation. You might also need to DC feed the solenoid via a small impedance so that the power supply used for activating the solenoid doesn't significantly attenuate the AC signal.
A bit of experimenting might be required. |
H: Does an oscilloscope subtract voltages as phasors?
I want to measure two voltages on an oscilloscope. They are not in phase. I want to know the magnitude of the voltage difference. The oscilloscope has an in-build math function to subtract the voltages from each other. But does it do that phasor wise ? Let us say V1=10V and V2= 15V and the phase angle is 20 degrees. We want the magnitude of V1 - V2. Does the oscilloscope give 5V, or does it take the phase into considerations when subtracting ? I am using the tektronix TDS 2024C.
AI: The math subtraction function in an oscilloscope subtracts the instantaneous values of waveform 1 from the instantaneous values of waveform 2 to create a new waveform comprising all those instantaneous subtractions. A basic (or expensive) oscilloscope does not understand phasors.
Here is a pictorial example of a noisy sinewave subtracted by a clean sinewave with the output (in pink) being just the noise: -
Picture from here. |
H: Connecting and disconnecting the power supply
I have learned that powering a chip without ground is quite dangerous and might cause permanent damage to the chip or the board in general. I have also seen that happening many times in non isolated DC to DC step down converters and some microcontrollers as well.
How can I prevent that from happening? Assuming I have a board with a non isolated switching regulator and a microcontroller that is connected through a UART to a USB to serial cable or to another board. How can I prevent the current flow if the ground disconnects first or the positive line connected before ground?
AI: Its not quite the rule that ground should be connected first, instead the rule is generally power before data, If you look at a USB plug / socket you will notice the 2 outer power/ground connections are longer than the middle data connections, Same for Micro-SD card,
In these cases by having the device be powered before its connected to data lines means everything is at a known state, there will not be any pins mid way from raising from a low to a high signal.
What it sounds like your describing is a mains ground loop, things like PC power supplies have there ground tied to mains ground, so by having your UART - USB Cable connected, they share a ground, if your ground referenced power supply looses its ground connection to your circuit, It ends up completing its circuit through the wiring in your walls
In reality it is rare for this to damage a circuit, however it can make it act weird as this tends to couple in a fair bit of noise. |
H: Two-stages class AB amplifier
I'm studying the following two-stages class AB amplifier:
Basically it is a standard two-stages op-amp (i.e. the cascade of a differential pair with active current mirror followed by an inverter with active load) to which the source follower M8-M9 has been added in order to provide the single-ended output signal of the differential pair to the gates of both M5 and M6.
I have doubts about some sentences of my book.
1st question
The book says that the gain of the second stage (i.e. the inverter with active load given by M5-M6) is:
Shouldn't the gain be negative? M5 and M6 give raise indeed to an inverter.
2nd question
I think that the book has an error: the gate of M1 should be in-, while the gate of M2 should be in+.
3rd question
Since the book does not provide the expression of the total low frequency gain, I surmise that it is given by the product of the gains of the three stages. Is it correct to assume the gain of the source follower equal to 1 for semplicity?
AI: Q2: when voltage at gate M1 is increased then the drain current through M1, M3 and M4 increases that will pull up (increases) the voltage at the gates of M8 and M5. So M5 will conduct less current making the output voltage drop (decrease).
No need to simulate that :-) but if you want, confirm this by simulation.
So yes you're right, the gate of M1 is the inverting input.
Q1: because of that (written above) now the gain becomes positive. |
H: Xilinx FPGA, error creating generated clock
I just got a Digilent Basys 3 board (Artix-7 FPGA) and I am trying to create a program to transmit data over the UART-USB connection. I wrote a module but when I tried to implement it I got a timing error. I have been using the standard 100 Mhz clock which comes with the board. I now think I need something slower like 50 Mhz. I don't think I can change the standard clock since that is fixed at 100 Mhz by the board so I think I need to create a generated clock. I added the following lines to my xdc file.
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
create_generated_clock -divide_by 2 -source [get_ports clk] [get_ports clk2]
I then get the error. Generated clock clk2 has not logical path from master clock sys_clk_pin. Am I missing a step. Do I need to do something more than create it in the XDC file? Here is the header for my top level module.
module serial_emitter(
output RsTx,
input RsRx,
input clk,
input clk2,
output [3:0] an,
output [6:0] seg);
I want the slower clock to map to the clk2 input.
AI: You've constrained the clock for static timing analysis, but you never actually wrote the logic to divide a clock by two:
reg r_clk_div;
always @(posedge i_clk) begin
r_clk_div <= !r_clk_div;
end
assign o_clk2 = r_clk_div;
This should synthesize to a DFF clocked by input clock, Q tied to D through an inverter, and then the Q output is your new clock. Your constraint tells the tools that you've generated this clock from an existing clock / resource and to treat it accordingly.
Note that I don't have a reset for this divider since I didn't see one in your module, but it may not be a bad idea to avoid temporary meta stability.
Apologies for typos, I'm on mobile. |
H: How many ground and power pins to have in a connector?
I'm designing a daughter board for a project. There are 35 I/O pins that need to go to the board. How do I determine the number of ground and power pins to include? How do I determine the placement of those pins throughout the connector?
I know something like this would be bad, as I was told:
P IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO
G G IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO
I'm guessing something like this isn't much better:
P IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO G
G G IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO P
The board is for a microprocessor, I'm going from a breadboard to a PCB and am trying to learn as I go :)
23 pins are address lines, 8 data lines and 4 signal lines (Read, Write, Chip Enabled and Direction). There is no clock line on this board but there might be on others I'll be making. The clock of the microprocessor will be 50MHz or less, down to <1MHz. The connector itself will be a standard .1" pins.
AI: There's a great book from Henry Ott that covers this -- unfortunately I'm on vacation so I can't take a picture of the relevant diagram. The book is Electromagnetic Compatibility Engineering.
Here's some quick points though:
from a DC power point of view, how much current does your device require? Look at the rating of each conductor, de-rate if necessary to give yourself margin and choose accordingly the number of power pins. Remember you need 1:1 power to ground.
from a AC POV, you want to minimize the loop return area of all of your signals. You want each signal to have its own GND / return immediately adjacent -- two schemes to do this:
S G G S G G S G G S G G S (one-two ground per signal, no adjacent signals)
G S S G S S G S S G S S G (one ground per signal still, more efficient utilization of space).
The idea is to minimize crosstalk and radiated emissions. While DC follows the path of least resistance, AC follows the path of least impedance. In this case, providing a return path immediately adjacent to a signal will help minimize the size of the overall current loop, reducing your radiated emissions.
Additionally, are these all single-ended? Differential? Expected signal rate? Expected edge rates? |
H: Is it possible to boost current into a load without boosting voltage also?
If a device "D" requires X watts power, and I have a power source Y that is less than the nominal voltage recommended by the device "D", can I obtain the same performance for the device by somehow boosting the current such that Y·(boosted current) = P?
I know this is a very simplified question that doesn't take alot of factors and practical limitations into account, but rather than getting an answer to my specific problem I would like to see the idea generalized.
If this can't be generalized, maybe some rules of thumb could be given along with some edge cases where it does not work could be helpful. Note that I won't have any issues with too high current burning out the wire(awg size can be adjusted). My main issue is that I do not have a high enough voltage as the device recommends and wanna know how much I can underpower and still get satisfactory performance.
AI: Device D needs X watts so providing source Y can provide a 10% more power than device D needs you can use a boost regulator to step up the voltage to suit the voltage required by device D.
The 10% more power accounts for the losses in a boost switching regulator. In other words if Y can supply a bit more power you can convert this (at 90% power efficiency) to give you the right voltage and the right current.
My main issue is that I do not have a high enough voltage as the
device recommends and wanna know how much I can underpower and still
get satisfactory performance.
Totally unanswerable but who cares - use a boost regulator and get the right voltage. |
H: TypeMatrix keyboard connector type
I'm trying to investigate problem in my type matrix keyboard and I have two questions
how is called that connector (what type is it) on the right, it has around 25 pins +/- 2 pins?
Is it possible to read what is inside that chip on the left or debug that somehow?
Br,
bioky
AI: The connector is commonly called a flat-flex ribbon connector (FFC). Here is the section on Digikey for them: Digikey Section
Getting that sort of cover material off of devices can be challenging. You might want to try searching the internet to see if anyone has done it first, or knows what is on that particular board (search by part number). Otherwise you're going to have to try decapsulating it which can get tricky. Depending on the material it involve anything from requiring heat, to acid. |
H: Area under voltage vs time discharge curve
Will the area under a voltage vs. time graph of a battery discharge curve (with a constant current load) give the amp-hour capacity rating of the battery?
AI: No, in your case it is not the area that tells you the capacity, but the length of time before the voltage is so low that the battery is considered discharged. For example, if the battery started out a 4.0 V, then decreased over 1.9 hours to 2.7 V when you considered it empty, the capacity is 1.9 hours times the discharge current. If the discharge current was 1.3 A, for example, then the capacity was (1.9 h)(1.3 A) = 2.5 Ah.
The area under the graph is proportional to the total energy the battery delivered. Actually its merely the time integral of volts. But you said that the current was constant, so volts is proportional to power, and the time integral of power is energy. |
H: Notation on schematic for circuit with n-channel switch
I am designing a circuit with a load that will consume up to 2A @ 5V. I decided to use a slide switch rated at 100mAh to drive an N-channel MOSFET for the (relatively) high current, since a slide switch rated for 2A is significantly bulkier.
I understand that when using N-channel as a switch it is connected on the low side between the load and GND.
I'm just wondering about best practices for separating the circuit GND from the load GND that needs to go through the MOSFET. I'm guessing I should use different net names for those two GNDs.
Which one of the grounds should I call GND? The external "raw" one? Or the one that goes through the MOSFET? I already have a dozen GND nets/symbols in my circuit that should be going through the MOSFET
Should I use different symbols for the two grounds? Or same symbol with different net names?
Does anyone have an example schematic with a similar circuit I can look at for reference?
I am mainly asking about best practices and ensuring maximum readability. Thanks!
AI: If I understand correctly, you are asking what to call the net on the drain of your low-side N FET and what to call the net on the source of that transistor, correct? That's very fine to do, but check my warning further down about the danger of accidentally bypassing the transistor.
I would call the GND that is connected to the source of your transistor as "the" power GND. I would assign a net-name to the node on the drain as "LOW_SIDE_LOAD" or similar. I would not give it its own GND symbol unless it is truly spanning multiple sheets. If it is, I would have one schematic sheet with a large square drawn around the circuit element that connects it to GND through your FET. As an engineer I generally follow GND on a schematic to its source, which is usually the power supply page that ends in a connector of some type. If I saw some other GND symbol, I would follow it through the schematic until I find the tie / relationship to GND.
You should try to make it as clear as possible that any other connection between LOW_SIDE_LOAD and GND will effectively bypass your switch. This is one of the dangers of low-side switching. |
H: Sampling frequency and FFT
I have tried this example code for sampling and FFT in MATLAB, but I have noticed that when the signal frequency becomes closer to nyquist frequency , some errors ( small frequency components near the given signal frequencies ) in the frequency domain begin to show up. Is there any explanation for this situation?
close all;clear all; clc;
freq = 100;
freq1 = 1000;
freq2 = 2000;
freq3 = 3000;
freq4 = 4000;
Fs = 10000;
t = 0:1/Fs:1;
x = cos(2*pi*freq*t) + cos(2*pi*freq1*t)+cos(2*pi*freq2*t) ...
+cos(2*pi*freq3*t)+cos(2*pi*freq4*t);
tempfft = abs(fftshift(fft(x)));
figure;
stem(0:floor(Fs/2),tempfft(floor(Fs/2):Fs));
AI: In comments you said that the "errors" you're interested in are the non-zero FFT response at frequencies near the signal frequencies.
Those are caused by windowing.
Your time vector, generated by the expression 0:1/Fs:1, has 10,001 elements, and your sampling window is 1.0001 seconds. So it does not contain an integer number of cycles of any of your input signals. Therefore the truncated time domain sequence does contain components at the frequencies slightly off the intended frequencies.
If you used
t = 1/Fs:1/Fs:1
to generate the time vector, you would have full cycles of your signal waveforms, and you wouldn't see this effect. |
H: How to break apart grooved PCB
I recently got a set of 20 breakout PCBs. I didn't realize that they came in one piece- that they had not been cut apart yet. However, there are grooves between each board that are cut into the material. The grooves extend about 1/3 of the thickness through on each side, leaving about 1/3 left of circuit board in the middle.
How do I break these circuit boards apart? Is a forceful slice from a box cutter appropriate? Can I snap them apart with my bare hands? Or should I use a saw or a bandsaw to cut them apart?
AI: Bare hands should be sufficient. Grab the boards solidly and bend. Do so in a consistent fluid motion, and hold them such that the boards themselves won't bend much. You might have to work the seam in the opposite direction a few times to make them separate.
There are depanelling tools for these sorts of things, in the form of vertical wedge presses, or wheels similar to pizza cutters, but you only really need those for situations where you can't bend without damaging the boards, or when dealing with large quantities.
Doing it by hand is fine. |
H: current mirror biasing cascode
Guys My doubt is that for the following cascode configuration how can the minimum voltage needed at the drain of M1 be Vt + 2 Vov for M1 and M2 to be in saturation ?? Vov is the over drive voltage whihc is Vgs- Vt.
For saturation considering that Vds > Vov. At transistor M1 the minimum voltage should be 2Vt + 2Vov in my opinion. But it is said that it is Vt + 2 Vov , how is this so ??
AI: With the gate of M1 held at 2VT+2OV (by M3 & M4), you need VT+OV at its source (a VGS lower, or VT+OV lower), so M1's drain needs to be OV higher, or a total of VT+2OV.
M2 doesn't have to be at Vt+OV -- it could be just OV, but then (with the bias you have), you couldn't keep M1 in saturation. |
H: How to interpret Vcc and GND on integrated circuits?
I am a little confused about power supply markings on ICs. For example, if I have an IC named U1 stating that Vcc should be 5V, can I connect it this way:
simulate this circuit – Schematic created using CircuitLab
Or this way:
simulate this circuit
Or this way:
simulate this circuit
etc.
Are these correct or am I missing a point?
Also, if these are correct, then the problem would be calculating the voltage drop on the parts located between + and Vcc AND GND and -, since we don't know the resistance of the IC right?
AI: You can indeed use a resistor to cause a voltage drop on the integrated circuit power line(s). Fact it's never done that way (at least not without clamping diodes, such as a reverse-biased Zener diode) because the resistor value depends on the current consumed by the IC, which varies and can vary a lot. Instead circuits are powered with a low impedance power supply that maintains its output voltage level regardless of the consumed current — let's forget about current limitation for a second for simplicity's sake.
So if you need, say, 5V to power your IC, then you'd use a 5V voltage regulator, which keeps its output to a steady 5V as long as the current it feeds is kept in the supported component's tolerance. For instance an LM7805 in a TO-220 case typically can bear 1A output current. In general you'd also power the whole circuitry (or board) with 5 volts, not just the IC.
The 7805 is a linear regulator because it simply causes a voltage drop using a linear behaviour. As a major drawback, it produces an increasing amount of heat (that must be dissipated with a heat sink) when the input voltage increases. That's one reason why it bears a maximum input voltage. That maximum input voltage is about 35V for a 7805. |
H: OP-AMP Output Voltage
In the below schematic,
Photodiode is used ( not diode)
OP-AMP OPA 380
So, Vo = If X Rf
Case1:
IPh= A , Rf= 10K, VCC pin =5V
Vout = A X Rf = A(10K)
Case2:
IPh= A , Rf= 10K, VCC pin =3V
Vout = A X Rf = A(10K)
Does it means, Vout will be irrespective of VCC voltage?
Thank you in advance.
AI: Yes, the output voltage of your amplifier is independent of the power supply voltage, as long as that power voltage is large enough. Of course it can't be so large as to blow up the opamp either.
Note that the direction of the photocell current of the diode is down in this instance. That means the current flows right to left thru the resistor, and the right end of the resistor will therefore be at higher voltage than the left end. Due to the closed loop feedback, the opamp will make its output whatever it takes so that its negative input matches its positive input, which is ground. The output will therefore swing from ground (0 V) at no light to some maximum a full light. The power supply range must include that, plus whatever headroom the opamp needs to operate correctly.
If this is a "rail to rail" input and output opamp, then the negative output of the supply can be connected to ground, and the positive needs to be at least whatever the maximum output voltage will be due to the brightest light. |
H: Additional Resistor For Pierce Oscillator
I want to build SIM Card Reader by following a schematic from here as follow:
I realized that the clock generator (upper center) form a Pierce oscillator but with an additional resistor (R2 symbol in the schematic), which different than Pierce Oscillator circuit at wikipedia:
.
I've also found other variant of pierce oscillator as follow:
Which tapping output from the inverter instead of the capacitor like in SIM card reader schematic.
Could you please explain the use of R2? What if I removed the R2 from the schematic? And what the differences between the first and the last Pierce oscillator circuit?
AI: R2 in your main circuit forms an ~8 MHz low pass filter with the 20 pF capacitor it connects with. It has nothing to do with the oscillator circuit and my guess is that it's acting (with the 20pF cap) as a small delay to the inverter (IC1B) it feeds.
In this circuit: -
R1 is needed to bias the inverter into its linear region - now it acts like a linear amplifier and the smallish semi-sinusoidal voltage that the xtal produces at the input can be turned into a square wave at the output. Without R1, there is nothing to align the input dc voltage with the inverters linear region and it wouldn't work.
In your final circuit (or any xtal oscillator circuit like this), Rs is always present but usually the output resistance of the gate itself forms this resistor. Some while ago I did an analysis of a crystal fed like this and looked at the phase shift: -
If you CTRL-right_click on the picture you can open it in another browser page. For the equivalent circuit I chose values like so: -
L = 8.45mH
C1 = 0.03pF
C2 = 6pF
It was designed to produce 10MHz at a phase shift of 180 degrees.
Regarding Rs (R1 in my circuit sim) it is mainly thought of as limiting the power going into the xtal so as not to overstress is. This is of course very true however, if you look closely at the phase shift in the simulation, 180 degrees phase shift isn't quite reached and, by adding Rs (and Cb) you get a few more degrees and bingo, it oscillates. |
H: LTSpice Full Wave Controlled Rectifier Erronous SCR Breakover
I'm attempting to simulate a full wave SCR rectifier:
However it is not behaving correctly. In my setup V3 controls one pair of SCRs, and V4 controls the other. All the math on the side is just for setting up the pulses that control the gates. The first set of SCRs triggers properly when the gate pulse comes in, however the second set breaks over and acts like a diode. The initial current condition was put in to help the output current settle faster, so the simulation wouldn't have to take as long to run.
The model is used is one available from OnSemi Here. The breakover voltage is 400V, so it should work for this application.
Below are the traces for the current through U1 and U3, as well as their applicable gating signals. U1 (green) only starts to conduct once the gate voltage (cyan) rises.However U3 (red) starts to conduct as U1 is switching off, and well before the gate pulse occurs (blue).
So I decided to take a look at the gate currents to see what was going on. For whatever reason the U3 gate supply has a massive reverse current driven through it compared to the U1 gate.
The net result of all this is that U3 and U4 are acting like diodes and the system does not function as desired.
I'm not sure what is causing this, is there something wrong with the setup, or a parameter of the device that I missed? I picked that particular SCR just because it was the first seemingly adequate model I found that would work.
Thanks!
AI: Gate voltage for U3 should be relative to its cathode, not its anode. Likewise for U1.. You will need another voltage source tied to Vlh for those two SCRs.
Also, put a series resistor in for each gate to limit the gate current. |
H: UART Receiver Sampling Rate
I am trying to create a UART receiver in Verilog for my FPGA. I was following this guide http://www.fpga4fun.com/SerialInterface4.html
According to it the standard practice for asynchronous communication is to oversample the signal at 16 times the BAUD rate. This makes sense to me since I would need to do this to detect the first drop quickly and synchronize with the transmitting clock.
What I am wondering is why not just sample at the same frequency as the clock on my FPGA which is a lot fast than 16x the BAUD (my clock is 100 MHz). Is there any harm in doing this? I know it would probably just consume more power, but would it work or is there something I am missing?
AI: I've sampled at 8 times on one job and it was OK so there is no rule dictating that 16 is the magic number so sampling higher than this is not a problem in anthing other than handling bigger numbers in hardware. Here's a the 16x counter idea: -
From the falling edge of the start bit you "find" the start-bit's "middle" by counting to 8 then, each count of 16 thereafter you "sample" the UART received data to recreate the byte (or bytes) transmitted. Clearly if you had a 32x counter you'd get a tad more accuracy in determining the centre-point of the bit and counting at a higher rate is going to work but the numbers get bigger and the power consumption rise. |
H: How do you rewrite a transfer function to standard form?
How can I rewrite a transfer function in terms of resonance frequency \$\omega_0\$ and damping factor Q? Referred to as "standard form" in the university materials.
I'm still at it, trying to understand LCL filters, and found a gap in the university material. They always let us calculate the transfer function, then the standard form was given, so we just had to fill in the blanks and use the given function to draw a Bode plot. Now that I have a real circuit, I'm stuck. The university book only contains this section on the matter
Nilsson & Riedel has a section devoted to Bode diagrams in the appendix. It says all you need to do is divide away the poles and zeros and factor the result. Poles and zeroes seems to refer to the coefficients of the highest exponents in the numerator and denominator.
None of this is very revealing to me. Say I have the following transfer function. This is indeed in the general form, but how on earth do you factorise that? Getting rid of the poles and zeros is not very helpful either.
simulate this circuit – Schematic created using CircuitLab
$$
H(j\omega)=\frac{j\omega C_fR_f+1}{j\omega(L_1+L_2) + (j\omega)^2C_fR_f(L_1+L_2)+ (j\omega)^3 L_1L_2C_f}\\
H(j\omega)=\frac{C_fR_f}{L_1L_2C_4}\frac{j\omega+\frac{1}{C_fR_f}}{j\omega\frac{L_1+L_2}{L_1L_2C_4} + (j\omega)^2\frac{R_f(L_1+L_2)}{L_1L_2}+ (j\omega)^3 }\\
H(j\omega)=\frac{\omega C_fR_f-j}{\omega(L_1+L_2) + j\omega^2C_fR_f(L_1+L_2)+ j^2\omega^3 L_1L_2C_f}\\
$$
I put that in Wolfram Alpha, and it gave the following roots for the denominator. Besides being humongous, I don't feel they bring me much closer to a solution.
[update]
The factorization finally clicked, and I came up with the following for the undamped case:
$$
\begin{align}
H(j\omega)&=\frac{1}{(j\omega-0)((L_1+L_2) + (j\omega)^2L_1L_2C_4)} \\
j\omega&=\frac{\pm j \sqrt{4L_1L_2C_4(L_1+L_2)}}{2L_1L_2C_4} \\
H(j\omega)&=\frac{1}{(j\omega-0)(j\omega-j\frac{ \sqrt{4L_1L_2C_4(L_1+L_2)}}{2L_1L_2C_4})(j\omega+j\frac{ \sqrt{4L_1L_2C_4(L_1+L_2)}}{2L_1L_2C_4})} \\
&=\frac{1}{(j\omega)(\frac{L_1+L_2}{L_1L_2C_4}+(j\omega)^2)} \\
&=\frac{\frac{L_1L_2C_4}{L_1+L_2}}{(j\omega)(1+(j\omega)^2\frac{L_1L_2C_4}{L_1+L_2})}
\end{align}
$$
Putting this in standard form gives
$$
\begin{align}
H(j\omega)&=\frac{1}{(j\frac{\omega}{\omega_0})(1+j\frac{\omega}{\omega_1 Q}+(j\frac{\omega}{\omega_1})^2)} \\
Q&=0 \\
\omega_0&=1 \\
\omega_1&=\frac{L_1+L_2}{L_1L_2C_4}
\end{align}
$$
I hope that's not terribly wrong.
AI: To get to the standard form, you factorize the nominator and denominator polynomials. Then your polynomials will be of the the form \$K_{1}(s - z_1)(s - z_2)\cdots (s - z_n)\$ and \$K_2(s - p_1)(s - p_2)\cdots (s - p_n)\$. Then identify any complex conjugate pairs among the \$z_k\$ and multiply them out. If, for example, \$z_1 = z_2^*\$, then
$$
(s - z_1)(s - z_2) = s^2 - 2 \mathrm{Re}(z_1) s + |z_1|^2 = |z_1|^2\left(1 - \frac{2\mathrm{Re}(z_1)}{|z_1|^2}s + \frac{s^2}{|z_1|^2}\right).
$$
Now identify
$$
\begin{align}
\omega_1^2 &= |z_1|^2\\
1/Q_1 &= -\frac{2 \mathrm{Re}(z_1)}{|z_1|}
\end{align}
$$
and you get the prescribed form of the second order term.
For the remaining roots \$z_k\$, which will be real, extract the factors as
$$
(s - z_k) = -z_k (1 - \frac{s}{z_k}).
$$
and identify \$\omega_k = -z_k\$.
Repeat for the denominator roots \$p_k\$, and gather the constants to the front to get the factor \$K\$.
The roots you got from Wolfram Alpha are, up to the factors of \$i\$ that connect \$s\$ to \$\omega\$, exactly the \$p_k\$. Sometimes they do indeed end up somewhat hairy, but often it's possible to simplify them by identifying common factors (such as paralleled resistors, products RC that always appear together etc).
Finally, if the polynomial has root \$0\$ with multiplicity \$k\$, these will be factors of the form
$$
\left(\frac{s}{\omega_m}\right)^k,
$$
which you can bring to the front. The factors \$\omega_m\$ are now ambigous, as you can in principle include any of them in \$K\$, but often in practice there's some meaningful choice. For example, if you're designing a filter with a certain passband, you take \$K\$ to be the passband gain (and phase), and take the remaining part to be \$\omega_m^k\$.
The roots \$z_k\$ of the nominator are called the zeroes of the transfer function, as those are the complex values of \$s\$ where the transfer function is indeed the value zero. The roots \$p_k\$ of the denominator are the poles, since those are the values of \$s\$ where the transfer function diverges, which indeed looks like pole sticking out of the \$s\$ -plane if you plot it.
Note that factorizing a polynomial (over the complex numbers) requires finding its roots. For a second order polynomial, the quadratic formula gives you the answer immediately. For third and fourth order polynomials there's the cubic and quartic formulas. The cubic formula is already quite long, and the quartic formula is about a full page in small print, so it's often not useful in practice. For orders higher than five, there is no general formula, although special cases can often be solved.
In addition to using the general formulas, the circuit topology often provides considerable simplifications. For example, in the case of two second order sections separated by a buffer, you can analyze the two sections separately using the quadratic, and the standard form of the combined transfer function is directly the product of the standard forms of the individual sections. The same applies for any number of sections separated by buffers, which is one of the main reasons that high order filter are usually designed as series of second order sections.
If, in the end, you cannot find explicitly the roots, or they're too complicated to use, you can still learn about the your circuit by studying the discriminants, which tells you about potential complex conjugate or real roots. In your specific case (assuming you roots are correct, I didn't check), the discriminant is the term inside the square roots,
$$
\Delta = C_f L_2 R_f^2 + C_f L_1 R_f^2 - 4 L_1 L_2.
$$
If this is negative, you have a complex conjugate pair of roots leading to a second order term, and it's positive, you get two real roots. You can divide by \$L_2\$ and \$C_f\$ to get the expression
$$
\tilde{\Delta} \triangleq R_f^2\left(1 + \frac{L_1}{L_2}\right) - 4 \frac{L_1}{C_f},
$$
which has the same sign as the discriminant. From here you see, for example, that if \$C_f\$ is small enough, or \$R_f\$ is small enough, you get a complex conjugate pair. |
H: why my power calculation for this resistor is wrong?
i encountered a very simple question in a test and i easily calculated the answer
but somehow i am making a mistake because i can not find my answer between the available answers, what am i doing wrong ?
thanks.
Question : Calculate the wasted power on the 6 ohm resistor.
my current answer using KVL :
(i*2) - 16 - (4*i) + 4 + (6 * i) - (3 * (4 * i)) = 0
(- 8 * i) = 12
i = -(12 / 8) A
now power for 6 ohm resistor
p = vi = i^2 * r
p = ((12 / 8) ^ 2) * 6 = 13.5 w
AI: simulate this circuit – Schematic created using CircuitLab
Since the 4 Ω has the voltage signs marked + on the right then let's have current, i, flowing right to left through it and anti-clockwise through the circuit. Starting at R1 and going anti-clockwise we get:
4i + 16 + 2i + 12i + 6i - 4 = 0
24i + 12 = 0
i = -12 / 24 = -0.5 A
In fact, the current is running clockwise.
Now you have the current you should be able to work out the power in the 6Ω resistor.
I think your problem was falling for the 'trick'. The + and - signs are reversed on the 4Ω resistor. You calculated voltage drop on the 2Ω correctly but did it with the opposite sign on the 4Ω because the question deliberately misled you. |
H: Error when passing wire of different size to module input
I have a module to display a base 10 number on my 7-Segment display.
module displayN(input [13:0] n, input clk, input [3:0] an, input [6:0] seg);
wire [3:0] d1 = n % 10;
wire [3:0] d2 = (n / 10) % 10;
wire [3:0] d3 = (n / 100) % 10;
wire [3:0] d4 = (n / 1000) % 10;
display4(d4, d3, d2, d1, clk, an, seg);
endmodule
It takes in a 14 bit number and computes the digits and hands it off to another module which actually displays it.
Right now I am working on a program which uses a USB-UART connection and displays the value of the last byte sent on my 7-Seg. Here is my top level module.
module uart_top(input clk,
input rx,
output tx,
output [3:0] an,
output [6:0] seg);
wire [63:0] count;
wire [7:0] out;
uart_receive r(clk, rx, count, out);
reg [7:0] oreg;
always @(out) oreg = out;
displayN d4(oreg, clk, an, seg);
ila_0 i(clk, rx, out);
endmodule
This code is currently working. When the output of my uart receiver changes I copy the output to a register, and then send it to my display module. This seems to work correctly when I try it on my card. I am assuming that even though the module is expecting 14 bit it just fills 0 for the upper 14. However, when I try to pass "out" directly to the module like displayN d4(oreg, clk, an, seg); I get some error about a black box. Why can I do this for a register but not a wire?
Here is the exact error message I get during synthesis.
[Project 1-486] Could not resolve non-primitive black box cell 'displayN' instantiated as 'd4' [/home/chase/vivado-workspace/UART/UART.srcs/sources_1/new/uart_top.v:37]
Here is the schematic.
Also here is the uart_receive.
module uart_receive#(parameter BAUD_RATE = 9600,
parameter CLOCK_SPEED_MHZ = 100)
(input clk,
input rx,
output reg [63:0] read_count = 0,
output reg [7:0] data);
localparam SAMPLE_BAUD_RATE = BAUD_RATE * 8;
reg reading = 0;
reg [8:0] bit_stream = 0;
reg [3:0] bit_index = 0;
wire sample_tick;
baud_gen#(SAMPLE_BAUD_RATE, CLOCK_SPEED_MHZ) s(clk,, sample_tick);
wire baud_tick;
baud_gen#(BAUD_RATE, CLOCK_SPEED_MHZ) b(clk, !reading, baud_tick);
always @(posedge clk) begin
if(sample_tick && !reading && !rx) begin
reading <= 1;
bit_index <= 0;
end
else if(baud_tick) begin
bit_index <= bit_index + 1;
bit_stream[bit_index] <= rx;
if(bit_index == 8) begin
reading <= 0;
read_count <= read_count + 1;
data <= bit_stream[7:0];
end
end
end
endmodule
It seems to work if I remove the ila_0 i(clk, rx, out); which is the Integrated Logic Analyser I was using for debugging. I always had out hooked directly up to it even when I was using the resister in displayN. I wonder why out could not be connected to both of them at a time.
AI: Have you looked at what is being synthesized? You are performing some math (modulo) operations on the output. Inside your UART RX module, the received byte is probably in a buffer of some type. If you don't have a storage / stated up element of some type, you're asking your FPGA code to combinatorially operate on your receive data and complete all operations before the next byte comes in. Using 'out' there passes 8-bits of data raw to your display module and probably infers quite a few latches.
By registering your data (I note you used the word 'copy' -- I take it you are a computer programmer branching into FPGA?), you are increasing latency slightly but you have now stored data in a stateful manner and provided a clocked, synchronous system during which things can be done. |
H: Is it safe for babies to use any kind of battery for a wearable project?
I want to make a wearable project for babies, is the commercial batteries safe for babies? Lithium Battery or Alkaline AA Battery? or can be risk to use them? the current provide by the batteries can harm the baby?
AI: You can, just be careful with the design. Make sure all the connections are adequately insulated and robust enough to handle the loads. Use an enclosure that requires tools to open, nothing that could be opened by hand alone. Leave overhead so you're not drawing the battery close to it's operating limits. This will help insure it doesn't overheat. |
H: Can't find CD4050 library in Proteus 8?
I am using this schematic as a frequency meter. I tried to search proteus libraries for this CMOS 'CD4050 , [IC3 in this schematic]' but all I've found is 4050 CMOS non-inverting buffer with one input and one ouput, I need this specific element with all the other pins of it, not the 4050 CMOS that proteus is showing, because the whole design of circuit counts on this element 'CD4050'. Any idea how to add this element to proteus ? Where can I find the library of this element. Please advise me ASAP. Thank you all.
AI: I haven't worked with Proteus but most electronic CAD packages have similar behavior when dealing with individual gates.
That is: each gate is individual. You place all of the individual gates in your schematic as required. Then you gather the gates into the desired packages.
My CAD package names this process as "packaging". You do this in the stage between completing the schematic diagram and starting to PCB layout.
Packaging assigns the individual gates to the physical chip.
The information about this process should be in the user manual for your particular CAD program. |
H: Reversing a small synchronous gearmotor
it's been difficult to find the answer to this problem I have. My project is based on home automation.
I need to control the direction of the rotation and if possible the torque of an AC synchronous motor like this one with the Raspberry Pi 2, to close and open curtains.
The RasPi is already connected to a relay switch like this one to automaticaly turn on some lights.
Does anyone know which is the best way to control the motor?
AI: As far as I can make out that's the same type of motor used in a microwave oven for turntable drive. On startup they run alternate directions. The direction is not controllable. The fact that it's an AC motor with only two terminals gives us a clue that we won't be able to control direction.
I have wondered about why my microwave turntable reverses and found a good response by Sean B on The Naked Scientist:
Most of the time they come to rest with one pole or the other nearest
the magnet pole, attracted to it. When power is reapplied this then is
repulsed, and as the gear set will have less friction in the reverse
direction ( the gears will have some slack play, when running this
makes it noisy but allows it to run freely, and when stopped it causes
a bias) and will tend to turn into that direction with less friction.
This then gives some momentum to the rotor and it carries on in the
same direction.
It's the wrong motor for your task.
[Update]
Crouzet make range of reversible motors of the type you had selected. The motors have two coils - one for clockwise and one for anti-clockwise rotation. See here for pricing and link to datasheet. Speed is way too slow for your application but it may give you some ideas.
simulate this circuit – Schematic created using CircuitLab
Control circuit for reversible AC motor.
Stepper solution
Steppers are great for simple position control provided the movement doesn't stall. For your curtain application this means that the motor needs to have adequate power to guarantee successful motion. For a stepper solution you will need:
A suitable stepper motor.
A suitable gearbox or pulleys to give adequate torque at a mid-range speed for the motor.
A 'home' switch.
Stepper driver module.
Sequence will be:
On power-up drive the motor in the home direction (typically open) until the 'home' switch turns on.
When closing the curtain you run the stepper the required number of steps to just close.
When opening you can either move back the same number of steps or run the home routine again.
The stepper solution is more complex, noisier and requires additional low-voltage supply. The synchronous motor solution is simple and can be operated with a couple of switches. I'd be inclined to "keep it simple". |
H: power supply independent biasing
In the current mirror given below
I can see that the Iref produced strongly depends on Vdd whihc is the supply.
In the diag shown below which is power supply independent as they call it,
I do not understand how this is power supply independent. The PMOS M3 and M4 anre supply dependent as M3 is purely a diode connected transistor and it strongly depends on the supply. So my question is what makes this set up power supply independent or in other words less sensitive to the power supply ?
AI: This current supply is independent of the Voltage because the voltage source isn't the reference for the resistance.
It's a bit easier if you walk through how this stabilizes itself. When Vdd is applied a reference current is forced on M1 because it is diode tied. This reference current gets multiplied by ~K in M2 and that current flows into the resistor which produces a voltage. That Voltage takes away the amount of voltage available for the PMOS M3 mirror. That in turn forces the PMOS M4 to reduce the reference current to M1, so M2 produces less current which lowers the Voltage drop across R increasing the amount of voltage for M3 and this keeps going until it stabilizes.
As you can see in this example. I never once needed to know what Vdd was. So long as Vdd was low enough that it doesn't harm the mosfets, then the mosfets regulate themselves using the voltage feedback from a known resistor. That's why this is "supply independent (within reason)." |
H: Is here a node missing when using the node voltage method?
I am currently learning the Node voltage method to get a better know how about circuits. Let's say you have the following circuit:
This is the workout example with all the nodes. IMHO, I disagree, I think there is one node missing and the circuit should be as follows:
I thought that the definition of a branch was that it could only contain 1 and only 1 element (doesn't matter what element it is). When using the first circuit the current source I5 and the resistor R4 would be in the same branch, right?
Question: Then why is this the final answer? Am I missing something? Is it wrong to add N3?
AI: There is actually no point adding node "n3", because node "n0" and node "n3" are short circuited. If you try to solve it like this, there is actually no problem if you keep in mind that they have the same potential (Vno = Vn3), but there is no reason to make things complicated. Try to avoid extra unknowns :)
Also, there is no element between those two nodes, hard wiring is not considered as an element, so that is not a branch. |
H: Confusion in interpreting NPN transistor's saturation region
Above screen-shot is from a SPICE simulation of an NPN BJT where it shows the output characteristics Vce versus Ic. Ib is kept constant at 5uA where Vce increased from 0V to 5V.
I'm having difficulty in interpreting this plot at the saturation region. Okay so I'm gonna explain where is my confusion together with what I understand:
The output characteristics of an NPN transistor is obtained by keeping the base current Ib constant at a certain value when increasing Vce and obtaining a plot Vce versus Ic.
So as also seen in my simulation above, when Vce is below 0.2V the collector current Ic is decreasing dramatically. But according to the theory when the Vce is less than around 0.2V the transistor saturates. It acts as a closed switch. So Ic must take its highest value.
I'm confused at this point. Lets say you point the 0.1V Vce at the x-axis of the plot and go vertical until you intersect the curve, and you find 0.6mA. So simulation verifies under 0.2V the Ic decreases. But again at the same time "Vce under 0.2V" means there is saturation which means Ic must be maximum.
Why they shade that region in general? Does that mean that part of the curve shouldn't be taken into account? But then this is what simulation plots and probably I would get the same plot if I measure it.
What am I interpreting wrong here?
AI: But again at the same time "Vce under 0.2V" means there is saturation
which means Ic must be maximum
The "theory" is just a "rule of thumb" when turning a BJT on to act like a switch. The current that flows is still dependent on base current and collector voltage: -
Once the collector voltage has lowered beyond a point the BJT leaves the "active" region and enters saturation where it is "like" a base-current-controlled variable resistor. See the different rising slopes extending from the origin - if you approximated these to straight lines each has a V/I ratio just like in a MOSFET: -
Of course it can be really confusing the way that MOSFET's saturation region IS NOT the BJT's saturation region but the reason is clear if you consider that for a BJT it is saturation of the base whereas in a MOSFET (or JFET) it is saturation of the DS channel - two totally alien effects but called the same thing.
EDITED SECTION
I've added this because some internet pictures of a BJT's operating characteristic are incorrect. See below at an incorrect diagram of the BJT in saturation: -
There is NOT one line representing all base currents - each base current graph is individual and not "merged" as per the incorrect picture above. |
H: Current in a branch containing both resistor inductor?
simulate this circuit – Schematic created using CircuitLab
There is a switch in the circuit which has been closed recently so the circuit is now in transient state and we are applying KCL at node 1.
Also we cannot use Laplace transform.
Is there a method for this?
WE have to apply KCL at NODE1 , How can we write the expression for current in the branch containing capacitor and inductor? As we have for left and right branches i.e $$ (V_1 - 1)/100 $$ and $$ (V_1 - 0)/100$$
AI: Express the series L/C/R branch as a complex impedance - either via Laplace transfom: \$\small Z(s)=R+sL+\frac{1}{sC}\$, or the equivalent in the frequency domain: \$\small Z(j\omega)=R+j\omega L+\frac{1}{j\omega C}\$. As the source is a direct voltage, Laplace is the way to go. |
H: Why voltage drops when I short a battery?
When I short an AA battery, I have observed that it's voltage drops a couple hundred millivolts and when I break the short, its voltage starts to "replenish" at a decreasing speed.
What is the reason for this behavior?
AI: Actually, if you are truly shorting the battery, then its voltage will be 0 by definition.
It seems you are talking about the battery voltage shortly after abuse, like shorting. Batteries work on chemical reactions, which don't happen instantaneously. During heavy load, like being shorted, the battery is pumping charge around as much as it possibly can. Internally, charge is moved around by ions physically moving thru some electrolyte. Under heavy load, various things can happen to get in the way of efficient battery operation. Some of these things are permanent, but others can recover after some time for things to diffuse around inside the battery. This is why the open circuit voltage will be lower immediately after abuse, but will usually recover somewhat over time after that.
If you are asking why the voltage of a battery goes down with load, then the answer is in part internal resistance. A very simplistic model of a battery is a fixed voltage source with a resistance in series, also known as a Thevenin source. Even if the voltage source remains at the same level, the terminal voltage will go down with current since the drop across the resistance goes up with current.
There are also again chemical affects, so the voltage source doesn't stay fixed either. As the battery ages, both the voltage source will go down and the internal resistance will go up.
Batteries are complicated. |
H: LCD Interfacing types
I am learning LCD interfacing and came across parallel, RGB, LVDS interface so far.
I have worked on parallel 8/16 bit interface.
But have few doubts in overall interfacing of LCD.
Is RGB a parallel interface?
For TFT's with RGB pins, do we always need LCD controller to take care of all LCD control signals (HSYNC,VSYNC,DCL,DEN,RGB data pins)
If LCD datasheet has RGB pins, does it means it is compatible only for FPGA/CPLD boards which have these pins available for interface?
Can't we interface LCD with RGB interface directly to host controller?
AI: Is RGB a parallel interface?
Yes. It simply spits out the raw red-green-blue data for each pixel, repeated for every refresh of the screen. It is basically like an old analog scan-line signal, but using a parallel digital bus for the data rather than a voltage signal.
For TFT's with RGB pins, do we always need LCD controller to take care of all LCD control signals (HSYNC,VSYNC,DCL,DEN,RGB data pins)
Yes, the screen requires these signals to do anything useful. They typically have no built-in controller or memory etc, so if the data isn't continually fed into the screen it will just show black.
If LCD datasheet has RGB pins, does it means it is compatible only for FPGA/CPLD boards which have these pins available for interface?
You can get microcontrollers (such as the LPC4088 series or STM32F429) that have built in LCD controllers that will generate these signals as well.
Can't we interface LCD with RGB interface directly to host controller?
The pixel clock (rate at which pixels need to be sent to the display) is normally around 6MHz. Theoretically if you have a fast enough micro you could generate these signals in software, but normally it is much cheaper and easier to use a micro with a dedicated controller or an FPGA. |
H: Using a PAL for a seven segment display
I know next to nothing about PAL. I was wondering how one goes about programming a PAL (an old TIBPAL 16L8-25CN in my case) to drive a seven segment display, sort of like a HEF4511B. Right now I just have an arduino uno and a raspberry pi, do I have to buy an EPROM programmer? What program should I use?
AI: You need some software (ABEL, WINCUPL, PALASM) and a compatible programmer (hardware). As Bruce says, this series is OTP (one time programmable) so if you make a mistake you need another chip. There were some UV erasable (windowed) parts made with similar capabilities (different part numbers).
You can probably download at least one of the software programs for free, and if you have a universal EPROM programmer that supports PALs you may be all set save for the actual development. The software is so old you may have to run it in emulation under DOS (or equivalent) since it's probably 16-bit code.
For something more modern, look at Xilinx Coolrunner CPLDs (flash-based) but the software is a bit of a pig. |
H: Manual SPI device select
From another stackexchange question it should be possible to have the SPI device select pin always asserted given that the SPI bus only has one slave.
I have other interesting features multiplexed to my SPI device select master, so I would like to get rid of the connection altogether and connect the SPI device select slave to a logic 0V via a pull-down resistor.
Is this feasible?
AI: Although forcing the clock select should work in theory, you could have a problem with synchronization in practice.
SPI does not have framing bits. Instead, the slave knows that that a transaction always starts at the first clock transition after it is selected.
In theory, if you tie the select line low, then the salve should be ready and waiting and the 1st bit you send will be the 1st bit it receives. As long as you guys stay in sync, everything should be hunky dory.
Unfortunately it might not always work. During power up, say, there can be times when the clock line is in an intermediate state and the slave could potentially see a clock pulse when the master didn't send one. If this happens, the master and the slave will forever be out of sync.
You might be able to mitigate the risk of this start-up problem by using a clock polarity with a base of 0 and by using a pull-down resistor large enough to ensure that the clock stays low during power up by not so large that you can not actively drive it high. |
H: Given the current and voltage of a consumer electronic device, how to calculate its power draw?
Given a device that uses electricity from the wall socket (220-240V AC@50Hz or 110V AC@60HZ), and it has its current draw specific (i.e 1A), how can I calculate the power (in watts) that it consumes?
I know that for DC current, the calculation is very simple (Current multiplied by voltage) but I understood that for AC the calculation is rather more complicated.
Also, its quite unreasonable that my charger, that uses 1.5A AC, would consume 345W and only output 19V * 4.74A = 90.06W (255W turning into heat) and it won't get extremely hot. Also, it is rated above 80% efficiency, which doesn't meet the previous calculation.
How can I calculate an electric device's power usage given its current and AC voltage?
AI: Also, its quite unreasonable that my charger, that uses 1.5A AC, would
consume 345W and only output 19V * 4.74A = 90.06W
That would be unreasonable but that doesn't happen. The 1.5 A of current is at the lowest AC supply voltage that your charger can tolerate and still work. From what you are saying that sounds like 110V RMS. So now your input power will be 165 watts but that's still sounding a bit high so maybe your charger can operate at the "generally accepted" "world-standard" of 85V to 265V. At 85 volts RMS and 1.5 amps, the input power is 127.5 watts and this is a power efficiency of: -
Power efficiency = 100% x output power / inputted power = 71%.
Also, it is rated above 80% efficiency, which doesn't meet the
previous calculation.
If it is rated at above 80% efficiency this may be at the 230V range with efficiency dropping to 71% at the lower end of the range. Or you may have measured the value incorrectly.
Whether DC or AC, instantaneous power is instantaneous voltage x instantanous current. You then find that if you average the instantanous power over time, it becomes real power of which your can be billed for. Here are various scenarios: -
How can I calculate an electric device's power usage given its current
and AC voltage?
If you want to do it accurately you have to use a wattmeter and this gives you true average power - at the heart of any wattmeter is a device that multiplies the waveforms of voltage and current.
These days power supplies like yours are usually what is known as "power factor corrected" but if yours is an older type supply, the current and voltage waveforms may both look very different and not be truly in-phase. That makes simple power estimations problematic. |
H: How does a coaxial aerial cable work?
My family and I managed to break the aerial cable of our TV a few days ago.
The cable is of this kind of design:
And I believe its called a coaxial cable.
Fortunately, someone more practical than me has fixed the cable, but it made me wonder: how do these cables work?
The person in question was talking about the signal going from the outer of the inner to the inner of the outer. This made sense at the time, but I was doing a little more reading and that seemed to focus on the current flowing through the inner core, with the outer layer acting as a shield.
So, how does a signal get passed through a coaxial cable?
AI: Fortunately, someone more practical than me has fixed the cable, but
it made me wonder: how do these cables work?
The very simplest and most basic of answers is there are two conductors and one conductor carries current in one direction while the other conductor carries current in the opposite direction.
But there is a lot more to the pair of wires that make up a cable to consider if you wanted to look into it in detail. For a coax: -
For all two-wire cables there are electric fields and magnetic fields set-up between the two conductors but the beauty about coaxial cables is that these fields, in a proper installation, do not extend outside the perimeter of the coax cable.
So, how does a signal get passed through a coaxial cable?
The signal's energy exists in the gap between the outer and inner conductor and it travels through the cable to the far-end (the load) as an electromagnetic wave. This EM wave carries the power of the signal and it carries the electric field and magnetic fields in a certain ratio. This ratio is known as the characteristic impedance of the cable.
There are also losses due to the resistance of the conductors and these can be significant. There are also losses in the dielectric (the material that seperates the inner and outer conductors) and at higher frequencies this loss can limit the use of a coax cable.
Giving a simple answer to the question is really problematic if all you might know is ohms law but if you are interested there are a lot of things you can look-up on google such as: -
Characteristic impedance
Speed of propagation of signals in cables
Reflections coefficient
Voltage standing wave ratio
All the above can contribute to signal reflections such as shown below: -
A signal travels from left to right along a perfect coax cable but that coax cable changes to a different characteristic impedance at a position shown by the vertical line. When the signal "hits" that point, some energy is reflected back up the cable whilst some energy continues down to the load.
This answer may be already more complex than you are currently able to cope with so I'll stop at this point. |
H: Would a transistor be the correct device?
I am going to create the following circuits. However I need to be able to have a switch that completes the lightbulb circuit when VM1 input > 4.3v
I think a transistor may be the answer from what I have read. Please could someone give me some help. I have thought about using a relay, but this just seems to mess up the voltage to VM1
Any help is greatly appreciated.
simulate this circuit – Schematic created using CircuitLab
I believe this is the solution I was looking for. Please read this carefully before testing. POT's R1 & R2 are attached to the same wiper, so what happens to one must happen to the other. The switch SW1 is a push to break switch.
Please could you tell me if the resistors I have selected are compatible with the zener diodes I have selected. Thank you.
simulate this circuit
AI: Transistor is the correct answer but to get good control over this 4.3V threshold you may want something more than a simple transistor. Something like this:
simulate this circuit – Schematic created using CircuitLab
The LM393 in the middle is a comparator chip with open-collector output, comparing your input voltage against the reference voltage generated from the Zener diode D1 1N4731A (a 4.3V Zener diode, with R1 providing its 58mA current from a 5V supply) and shifting the signal level of 5V to 12V as required by the lamp with the pull-up resistor R3. The comparator outputs logic low when voltage on the "-" input is higher than "+" input, and high impedance (or logic high on a normal comparator, since LM393 in particular have an open-collector output) otherwise. The MOSFET M1 (any P-channel MOSFET will work here, IRF4905 is just my personal favorite) switches the lamp from the high side when it sees a low input at its gate, which is tied to the output of the comparator. |
H: Power Consumption on 220VAC vs 120VAC
I have an appliance that consumes 5mA when in standby on 220VAC mains. I'm assuming on a 120VAC 60Hz system it would also consume 5mA in standby (can't measure it). Since I haven't measured it, I guess my first question should be: Is the appliance likely to also require the same current on a 120VAC mains?
Assuming the answer to the question above is "yes"; since power is measured in watts, and wattage is V * A, are 220VAC mains inherently less energy efficient than 120VAC mains?
AI: If we examine the power draw at the power inlet of the device (and thus rule out one advantage of 220Vac over 110Vac) then if an appliance draws 5mA when powered from 220Vac its power draw via P = I*V would equate to 220 * 0.005 = 1.1Watts. [1]
If we consider two types of loads.
PASSIVE (resistive)
ACTIVE (SMPS etc.)
A passive-type load would follow Ohm's law and thus a reduction in voltage would result in a reduction of current & equally a reduction in power. This is true for heaters, lightbulbs etc...
If you were to take a 5kW electric heater from the EU and plug it into a US 110Vac outlet you would find its output is 1.25kW (give or take) as the resistive load is drawing 11A instead of 22A.
Does this make 220V more or less efficient when viewing a passive load? neither because if you wanted a 5kW electric heater you would need to correctly acquire one for the operating voltage.
Active loads however are more constant power loads and thus a reduction in input voltage will be met with an increase in current draw as it attempts to maintain its operating point.
For you example of 220Vac @ 5mA == 1.1Watts. An active load would draw whatever current is required to satisfy its load's need. So if the voltage was reduced to 110Vac the current that would be drawn would be 10mA to meet the power needs of the active circuit ( [1] is still applicable here)
Does this make 220Vac or 110Vac more efficient? Well this is where copper losses come into play & thus 110Vac would be less efficient than 220Vac systems.
[1] This is assuming that 5mA was drawn at unity displacement power factor & pure sinewave... it isn't in practice but for quick calculations to prove the concept. |
H: How plausible is the claim about a 200 kW battery solution?
Following this question posted on Aviation:SE:
Does the ARCA hoverboard violate known limits on small-diameter electric fans?
which is related to a hovering board described on the vendor site:
(source)
I would like to assess the claim this device really exists. In particular I wonder if it is possible to use the batteries to deliver 200 kW as claimed. I'm not trying to evaluate the aerodynamic aspects.
I don't see what technology could be used other than Li-ion cells. Assuming this is true, would this solution be compatible with the claimed characteristics:
Power delivered: 200 kW,
Running time: 3 min for a 110 kg user, to 6 min for a 82 kg user,
Charging time: 6 hours, reduced to 35 min using a docking station.
Taking into consideration the Li-ion characteristics with the knowledge of an electrical engineer, is there any aspect that would prevent this solution to work, e.g:
Weight, volume of the batteries (the board measures 145×76×15 cm),
Wires size (there is little room available in the box),
Current for charging (is this feasible to charge in 35 min),
Discharge time (would cells allow to be discharged in 3 to 6 min),
Cost (replacement of batteries is offered at $6,840).
No speculation please, but known facts that would definitely contradict or support the possibility of the solution. For instance, I think these deductions are correct:
For a 3 min hovering, with 200 kW, about 10 kWh are used.
Due to specific energy and density for Li-ion, this means 40 kg and 14 dm3 for the batteries.
Price of the batteries: With an optimistic 0.40 $ / Wh, this would be $4,000.
Charging 10 kWh in half an hour requires a 20 kW charger.
Assuming cos φ = 1, this would mean 91 A for 220V (well past what is usually found at home), and 5,000 A for the Li-ion cell voltage (this would require large wires that are not visible in the picture).
AI: 203kW / 36 fans = 5.6kW per fan.
Working voltage of 38V implies 10S Lipo (3.8V per cell).
5.6kW / 38V = 150A. We want 3 minutes at full power. At half power it will draw 75A for 6 minutes (max duration). A battery capacity of greater than 150*(3/60) or 75*(6/60) = 7.5Ah per fan will be required.
Can it be done?
Looks like 120mm diameter fans will fit in the space provided. Here's a 120mm fan that weighs 1kg and produces 7.5kg thrust on 12S:-
120mm 11 Blade Alloy EDF 700kv - 7000watt
On 10S it would draw about 30% less power and produce about 15% less thrust, so let's say 5kW and 6.5kg (the fans they are using may have different motors, but we can expect similar performance at the same power level).
And here's a 10S 4Ah battery that weighs 905g:-
ZIPPY Compact 4000mAh 10S 25C Lipo Pack
The board appears to use a total of 72 batteries - two batteries per fan. 2 x 4Ah = 8Ah, close to our required capacity. Max discharge rate is 4 x 25C = 100A per battery or 200A per parallel pair (and we 'only' need 150A!). Max charge rate is 5C, well above the 2C rate required for a 35 minute charge. At $67 per pack the total battery cost is $4824.
Our 72 batteries weigh 905g x 72 = 65kg. The 36 fans weigh 36kg. Add another 10% for ESCs, wiring and support structure, and we get a total board weight of ~110kg. This board should generate 6.5kg x 36 = 234kg thrust in free air. At half power thrust would be reduced to about 75%, but could be boosted by ground effect - so perhaps 210kg of 'duration' hovering thrust. Take away the weight of the board and you have a payload capacity of 100kg.
Looks possible! |
H: 3-dB Frequency of second order transfer function
How can i obtain the 3db frequency of the each transfer function ?
My attempt:
My guess is both transfer functions have the same 3db frequency.But equating the magnitude to 0.707 gives a fourth order equation which can be reduced to second order to obtain square of 3db frequency.
However, i am not able to simplify it.The exact expression however is as follows:
Is there any approximate approach for obtaining the same?
AI: I show you how to obtain the 3dB cut-off frequency for the low pass filter \$G_1(s)\$. You can calculate the cut-off frequencies of the band pass filter \$G_2(s)\$ in a similar way, as long as you know that its maximum magnitude is attained at \$\omega=\sqrt{b}\$, as pointed out in a comment by robert bristow-johnson. The latter fact can be derived by setting the derivative of \$|G_2(j\omega)|^2\$ to zero. (Note that \$b>0\$ is always satisfied for \$G_1(s)\$ and \$G_2(s)\$ to be transfer functions of causal and stable filters.)
To compute the 3dB cut-off frequency of \$G_1(s)\$ you have to solve
$$|G_1(j\omega)|^2=\frac{|G(0)|^2}{2}=\frac{1}{2b^2}\tag{1}$$
With
$$G_1(j\omega)=\frac{1}{-\omega^2+ja\omega+b}\tag{2}$$
you get
$$|G_1(j\omega)|^2=\frac{1}{(b-\omega^2)^2+a^2\omega^2}\tag{3}$$
Plugging (3) into (1) gives
$$(b-\omega^2)^2+a^2\omega^2=2b^2\tag{4}$$
With the substitution \$x=\omega^2\$, you get the following quadratic equation
$$x^2+(a^2-2b)x-b^2=0\tag{5}$$
with the positive solution
$$x_0=b-\frac{a^2}{2}+\sqrt{\left(b-\frac{a^2}{2}\right)^2+b^2}\tag{6}$$
From (6), the value of the 3dB cut-off frequency is
$$\omega_c=\sqrt{x_0}=\sqrt{b-\frac{a^2}{2}+\sqrt{\left(b-\frac{a^2}{2}\right)^2+b^2}}\tag{7}$$ |
H: Why should we use LED driver chips instead of much simpler structures?
For example: I have two led driver chips: bcr321u and RT8474AGSP
And think they both support to same output voltage and same output current etc. My question is about topological differences of them. BCR321U is definetely looks simpler and it is cheaper.
So, why do I need to use RT8474AGSP? When you consider, they both need much voltage supply and they both need an adjusted resistor for proper current flow, but RT8474AGSP configuration takes more area and so more and more expensive. In addition to that, this configuration is also an option:
If we were constrained by supply voltage, we would use boost led driver chips however, they all are buck structured so why we should chose RT8474AGSP over bcr321u and bcr321u over this simple opamp - npn structure? Where does the value of RT8474AGSP lies?
AI: Another good reason is the driver's efficiency: -
It's a current limited switching regulator there fore there is hardly any power lost in current limiting resistors or transistors unlike the other three circutis shown in the question. Here's ahow the data sheet describes the chip: -
With the internal 500kHz operating frequency, the size of the external
PWM inductor and input/output capacitors can be minimized. High
efficiency is achieved by a 100mV current sensing control. |
H: Programming/Verifying EPROMS with an elevated VCC
Many EPROM manufacturers specify a faster programming algorithm which involves temporarily raising VCC from 5V to about 6V.
If I read with this higher VCC in place, are the outputs still limited to the 5V vcc, or does my reading circuitry need to be 6V tolerant? Similarly, going in the other direction, are the EPROM inputs (data and address) 6V tolerant?
I haven't any specific EPROM manufacturer in mind: they all do variations on this theme, but the data sheets seem to be silent on this issue. They all seem to quote a maximum logic input of VCC+0.5, with out saying -which- VCC.
Maybe I'm over thinking this.
AI: If I read with this higher VCC in place, are the outputs still limited to the 5V vcc, or does my reading circuitry need to be 6V tolerant?
The outputs can reach VCC of the chip if the current is low enough. In this case your VCC is 6 Volts: Your inputs must tolerate this voltage somehow. |
H: Why is the output (in the truth table) inverted in a ic 74154 used as a demux?
I am studying Digital Principles and Applications from Malvino and Leach. I have a doubt in the demultiplexer section. This is the image of a 1 to 16 demux. I understand how it works.
So, if ABCD = 0000 and STROBE = L and DATA = H, then Y0 will be active and it should be H, while rest all inputs would be L. Also, if DATA = L and STROBE = L then all the outputs Y0 through Y15 should be L.
But when we try to implement a demultiplexer using a TTL 74154, this is the truth table that is given in the book:
Here, G1 = STROBE; G2 = DATA and outputs are Y0, Y1, Y2 etc.
Why are the outputs inverted? Is the hardware implementation circuit different than the one explained in theory?
AI: 74154 is a TTL circuit, and TTL was designed to make the best use of non-ideal transistors. In the processes of the time, bipolar NPN transistors were fastest, so all TTL circuits were designed around those.
If you have some experience using BJTs you will know that NPN transistors are best used to pull a signal to 0V (common emitter, with the output connected to the collector) and quite weak at pulling a signal high. (Common collector, with the signal connected to the emitter, which remains at 0.7V lower than the base voltage, and therefore considerably below the supply rail.
So TTL circuitry adopted asymmetric logic levels, where '0' was guaranteed to be below 0.8V, and '1' was guaranteed to be above 2.4V, less than half the nominal 5V supply rail.
Likewise a TTL output was guaranteed to sink 16mA (for the 74 series, 8mA for 74LS, other families had their own IOL ratings) but only source 0.4 mA.
This carried through to the input current requirements : you could pull an input high with very little current (40uA), but it took 1.6mA to pull an input low (0.4mA for the later 74LS).
And this carried through to the way the logic was used, and designed with. Inputs were pulled high by default, and only pulled low when necessary, to save power. So you can use a 47 kilohm resistor to pull up ( drops 1.88V at 40 uA) and a switch to pull down - and that practice is still often seen today, in active-low reset circuits, though the symmetry of CMOS makes it unnecessary.
High speed signals were usually active low, for much the same reason. And that's what is going on with the 74154... |
H: Analyzing BJT differential pair with feedback
I have an exam next week, and I need to get a real high mark to pass. Therefore I'm looking for some hard questions to solve, and this is one.
While I don't expect a full solution from you here, some guidance would be nice.
What does “assuming B of the BJTs is very high” mean?
How do we seperate the 1 mA source to the differential pair? Because the solution guide says that it is evenly distributed. How?
AI: That's not a capital "B", but a beta (β). It refers to the gain of the transistor, collector current divided by base current.
You can consider the 1 mA evenly distributed as a first order approximation. In reality, this only happens right at the cusp where the differential pair is in balance. A little off from that point, and one transistor will rapidly take more of the current than the other.
However, this circuit puts negative feedback around this differential pair, always keeping it close to the balance point. With the input at ground, the other input of the diff pair will also be held close to ground. That requires close to 10 V across the 20 kΩ resistor, which means the right transistor of the pair is drawing ½ mA, so the left one is drawing the other ½ mA. |
H: Need safe power supplies for beginner class with indicator light
In an intro electronics class in high schools, we use 6v battery packs as a way of delivering safe power for experimenting. However, the logistics of constantly getting fresh batteries, and our distaste for using so many batteries is leading to a search for an alternative.
We would like an inexpensive power supply that delivers small amounts of current (Ideally both 5V @ .2A, 12V @ .2A for example). Building such a supply as a project would be possible for a class of the more advanced students. So the question is to find a design. However, it would have to be protected from short circuits, and ideally would indicate to the student (with an LED?) when they have made a mistake and short circuited.
I found one design for a DC circuit, though this one requires DC voltage in:
Obviously I could take the above design, add a transformer and full-wave rectifier, but that's both big and clunky as well as possibly not optimal.
In an earlier question, someone suggested a 5V wall wart. student safe power supplyI can find inexpensive 5V wall warts, but would ideally like 12V as well, and have no idea if a given wall wart is short-circuit protected and even if they are, I want an indicator SHOWING when there is a short-circuit. I would like to take one and build in short circuit protection with an LED or alarm showing when a short happens, as well as a power indicator showing when it is on.
Can anyone suggest a design that we can build or buy? Since we are talking dozens of units per class, the cost has to be kept low.
AI: If you wanted to roll your own you could do it with a transformer, a full-wave bridge rectifier, a reservoir capacitor, a 7812 and a 7805, like this:
The regulators are self-protecting against overloads, so LEDs showing overcurrent would only be for the benefit of the students, but could certainly be added if desired.
Assuming a 12 volt RMS output for T1, C1 would charge up to about 17 volts, DC, which would put 5 volts across the 7812.
Then, a 200 mA load on the 12 volt line and a 200 mA load on the 5 volt line would mean the current through the 7812 would be 400 mA and it'd be dissipating: \$ \text{0.4A}\times\text{5V} = \text{ 2 watts,}\$ which means you'd need a heat sink on it to keep it from going into thermal overload.
With 12 volts on the input of the 7805 and a 200 mA load on it, it'd be dissipating 1.4 watts, so it would need a heat sink as well.
Update:
Per your your comment requesting one transformer and four regulators per table, here's a way to go about it:
I've only shown two regulator stages, for convenience, but any number can be implemented by sizing the transformer properly. |
H: How to drive 1080p with only 540 pins?
I was trying to hack a 3-D system starting from the monitor: VG248QE.
I teared it down to LCD matrix and driver. This is a 1080p(1920 x 1080) monitor so I was expecting that at least 1080(row) + 1920(columnn) = 2000 pins wired from the LCD driver to the LCD Matrix(I am not counting RGB's also!). However, I see 6 x 90 = 540 pins going to the LCD Matrix and I did not see any component(deMUX, MUX etc) on LCD matrix.
I looked up for the Driver chip online but found nothing(no datasheet!).
The question is, how does the driver drives so many pixels with so less pins? Am I not seeing MUX's embedded in LCD matrix? Or is there something else I am missing?
And just to share: VG248QE uses LCD overdrive method to achieve 1ms LCD rise/fall time and uses this chip for several levels of supply(+/-40V, 30V, 15V ...) for overdriving:
AI: A LED/LCD display is constructed of multiple panels: 16x16, 64x64, etc depends on the supplier.
These panels are mounted such to produce the 1920 x 1080 pixels
Each panel will have its own interface IC and LED/LCD driver chipset like the tlc59283
How is each panel/module controlled? via a serial interface.
If you look at a 320x240 panel such as this one you will see its interface is only 40pins wide & it clocks through D1:DH1 --> D320:DH240 as it reads in the RED, GREEN, BLUE data line to determine the hue saturation and brightness to be applied to the cell to be illuminated.
Larger displays use more panels and with vertical scan rates of say... 100Hz but with a fixed serial bandwidth per panel... a larger number of data lines are required to address each panel in a parallel fashion.
http://www.edn.com/design/led/4432914/How-to-design-LED-signage-and-LED-matrix-displays--Part-1
http://www.fujitsu.com/downloads/MICRO/fma/pdf/LCD_Backgrounder.pdf |
H: Help me identify this audio connector on a turntable
I have recently purchased a West German NECKERMAN 830 record player (1960s), which requires a separate set of speakers for audio output. Could somebody tell me the technical name for this cable so that I can purchase the correct counterpart?
AI: It appears to be a 5pin DIN plug
http://elektrotanya.com/philips_n4506.pdf/download.html
http://www.ebay.com/bhp/bang-olufsen-din
http://www.leadsdirect.co.uk/technical-library/pinouts-wiring-diagrams/din-midi-wiring/ |
H: Can a resistor start a fire?
I read that if you create a short-circuit, this produces heat and can cause a fire or damage an electronic component. The solution is to use a resistor.
The heat generated by electricity is proportional with the amount of
electricity passing through a conductor in a period of time
[Source: Make: Electronics Second Edition]
And I read in this question(What does a resistor do?), that
If I switch the power source from 5V to 9V, will I still measure the
same numbers after a resistance ?
And got this answer :
The increased electromotive force will allow more charges to flow per unit time, i.e. the current will increase.
If I connect a resistor to a high voltage source, a lot of current will pass through it and the heat will increase.
What will happen ? Does the resistor break and allow more and more current to pass? Could it start a fire ?
AI: It's somewhat unclear what you are really asking, but resistors dissipate power and heat up accordingly.
Electrical power is EMF times current. In MKS units these are measured in volts and amps, with the product of the two being watts.
Resistors are described by Ohm's law:
EMF = current x resistance
In MKS units:
volts = amps x ohms
V = A x Ω
Since power being dumped onto a resistor is volts x amps, and we can relate one to the other by Ohm's law, power is also:
W = V2/Ω
W = A2Ω
That is all to determine how much power is heating a resistor. How hot it actually gets depends on how well it can get rid of the heat. This is defined by the thermal resistance to ambient, and is dependent on the mechanical properties of the resistor.
For example, a physically small resistor might be rated at 500°C/W. If ambient is 20°C and you tried to dump 1 W onto it, it would stabalize at 520°C. That's way too hot for most resistors, so it would catch fire, vanish into a puff of greasy black smoke or the like before it got to that temperature.
On the other hand, a larger power resistor may be rated for 50°C/W. Dumping 1 W onto it would only raise its temperature to 70°C, which is likely well within its normal operating range.
This is why resistors not only come in different resistances, but also different powers. Resistors that can dissipate more power are physically bigger. Typical 0805 SMD resistors are usually good for 125 mW or so. It takes something 15-20 mm long and 5 mm in diameter to be able to dissipate a few Watts without damage. |
H: Transient simulation in Cadance
I have been trying to do a transient simulation of a Power supply independent biasing circuit in Cadance but how much ever I try I do not see the transition of the states. I always get only the steady state even if I put the stop time in nano seconds ! This is the circuit that I am trying to simulate and I have marked the nets(Voltage) that I trying to view in my transient simulation,
The simulation result looks like this(below) and the time axis is in nanoseconds range but still I do not get to see a slope or anything other than the steady state response ]2
Could there be any reason why I am not able to see the transition ??
AI: A transient simulation simulates the circuit's conditions over time. You seem to have no component in your circuit which introduces a time varying voltage.
Use a vpulse source instead of the vdc (V17), fill in it's properties so that it will step the supply voltage. Simulate that, then check that the supply voltage has the transient step that you want to simulate. If that is OK, look at the voltages inside the circuit. |
H: What standards or conventions are there for BOM line items for non-refdes parts?
Some designs have parts that may lack a reference designator because they never appear on the schematic. Examples include:
Battery holders
PCB-mounted (soldered on) fasteners such as solder-nuts
IC sockets
Jumper wires on a single sided board (if they haven't been backannotated to the schematic, that is)
Plugin modules such as keypads and LCD modules (if they haven't been given a schematic symbol)
Heatsinks
Are there any standards or conventions for how these are listed in a Bill of Materials for a circuit board?
AI: The best way to handle parts that don't appear on the schematic is to fix the schematic so that they appear. If you don't, you'll constantly be manually fixing the BOM that is automatically generated by your tools.
This applies to all the parts that belong to the immediate built board assembly. At the least, these are the parts that get soldered or otherwise mounted to the board. If the built board is part of a larger assembly, then the BOM for that assembly will show the built board as a single line item, and it can call out screws, nuts, standoffs, etc, for mounting the board into the larger unit.
And yes, this applies to sockets too. For example, here is a snippet of a larger schematic for a real commercial product that exists in the company's formal manufacturing database:
P11 is a Phoenix Contact connector that accepts a plug with screw terminals. Only P11 actually gets mounted to the board, but there always needs to be a plug with the board. That's what PLG2 is. It is there primarily for the purpose of automatically appearing on the BOM. In this case I think showing it on the schematic is also a nice visual reminder that the board comes with a screw-terminal plug. |
H: BEC or CEB NPN Transistor
I am looking for a small, inexpensive NPN transistor, similar to 2N4401 in specs, with a BEC or CEB pinout.
Does anyone know of any?
AI: that's an RF pinout, "TO92-3" eg fairchild KSP10 |
H: Is this something a P.L.C. would be able to do?
I wish to replace the zener diodes with a programmable chip, so that I can program the chip to do exactly what the zener diodes do in this circuit. This will then make the circuit universal to all my applications, and all I would need to do is reprogram the chip to use it on an application that requires different voltage limitations. In this circuit (if you need to simulate it and play with the POT's and the push to make switch to understand it, do so) they are voltage limiters, limiting either the minimum voltage d2, or limiting the maximum voltage d1 & d6.
Please read this carefully before testing. POT's R1 & R2 are attached to the same wiper, so what happens to one must happen to the other. The switch SW1 is a push to break switch.
simulate this circuit – Schematic created using CircuitLab
AI: in-fact you could probably simulate the whole circuit in software
and drive the two meters with PWM signals from the pic. |
H: Transmitting PWM binary at 400kbps (or 800kbps)
I need to send a string of bits to a chained set of RGB LEDs, each of which have their own controller IC. The datasheet for that IC, the WS2811, is here.
The protocol is quite simple: each bit, both 1 and 0, are sent as a high and a low, with different mark-space ratios, and are then strung together.
At 400kbps, the mark-space is as follows:
Binary 1: 1.2us high followed by 1.3us low (each +/- 150ns)
Binary 0: 0.5us high followed by 2.0us low (each +/- 150ns)
The data can either be sent at 400kbps or 800kbps. I'm not bothered which one I use, but I expect 400kbps will be easier to implement. (At 800kbps, the above times are halved.)
My question: How could this best be implemented? I'll probably be using a 20MHz (5MIPs) 8-bit PIC MCU to determine what data is to be sent, and I'm looking for the equivalent of a USART IC that the MCU could rely on to transmit data with the above encoding.
Possible solutions
There are three ways I envisage sending that kind of data at that speed:
Finding an IC / ASIC which is dedicated to this purpose.
Using a second MCU dedicated to receiving data from the primary MCU, and converting it directly to the above PWM encoding.
Building a dedicated transmitter out of TTL/CMOS logic ICs or similar.
For point 1, I can't find any IC that will do it. Do they exist?
For point 2, I have ideas for how it might work, but no solutions so far. One solution: Bit-banging would be very hard, having to be written in assembler given timing requirements. Another solution, although not capable of achieving the 100ns resolution for timing of the PWM signal to match the specs in the datasheet, could configure the USART on a PIC MCU to transmit synchronously - except each 4 bits transmitted would just be a hacky way of sending one PWM bit. So to send 400kbps PWM data, the USART would have to be capable of 400 x 4 = 1.6Mbps. Then, to send a PWM binary 1, the USART would send HHLL, and to send a PWM binary 0, the USART would send HLLL. This would only barely satisfy the +/-150ns timing requirements, a margin of 25ns. And I haven't found a PIC that can transmit that fast serially anyway.
So at the moment, option 3 is my only option: build dedicated hardware out of logic ICs. For example:
Construct a 25-bit shift register to output the PWM, required for a single bit. Then circuitry which fills the register accordingly depending on whether a binary 1 or 0 is to be transmitted. And since this would still be very intensive on the MCU, I would add perhaps an 8-bit latch which the MCU could write to, and allow further circuitry to process the 8 bits one at a time, for each one encoding the bit into the 25 bit shift register as a PWM cycle.
As above, but replace the 25 bit shift register with a monostable that outputs either a long or a short pulse, and another which loads a new bit every 2.5us.
Using a memory IC which acts as a lookup table, so perhaps (with extra circuitry) could be given a byte to transmit from the MCU and return data that a circuit could translate into serial data as the PWM output.
In short, I can't find a good solution! It seems like an awful lot of work for such a simple problem. How would you do it?
AI: These are popular chips, and the very popular WS2812 RGB LEDs (aka Neopixels) use the same 800KHz signal timing and protocol, so you are not alone!
The chips are not as finicky as they seem and can easily be driven from an 8-bit microconroller...
http://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
People typically bit-bang them directly from a normal GPIO pin, which does require a little bit of cycle counting to get the timing right, but does not require any additional hardware except for maybe a level shifter if you are running the MCU at low voltage. The above article includes the following very simple bit-banging code for AVR that should be trivial to convert to PIC...
// These are the timing constraints taken mostly from the WS2812 datasheets
// These are chosen to be conservative and avoid problems rather than for maximum throughput
#define T1H 900 // Width of a 1 bit in ns
#define T1L 600 // Width of a 1 bit in ns
#define T0H 400 // Width of a 0 bit in ns
#define T0L 900 // Width of a 0 bit in ns
#define RES 7000 // Width of the low gap between bits to cause a frame to latch
// Here are some convenience defines for using nanoseconds specs to generate actual CPU delays
#define NS_PER_SEC (1000000000L) // Note that this has to be SIGNED since we want to be able to check for negative values of derivatives
#define CYCLES_PER_SEC (F_CPU)
#define NS_PER_CYCLE ( NS_PER_SEC / CYCLES_PER_SEC )
#define NS_TO_CYCLES(n) ( (n) / NS_PER_CYCLE )
#define DELAY_CYCLES(n) ( ((n)>0) ? __builtin_avr_delay_cycles( n ) : __builtin_avr_delay_cycles( 0 ) ) // Make sure we never have a delay less than zero
// Actually send a bit to the string. We turn off optimizations to make sure the compile does
// not reorder things and make it so the delay happens in the wrong place.
void sendBit(bool) __attribute__ ((optimize(0)));
void sendBit( bool bitVal ) {
if ( bitVal ) { // 1-bit
bitSet( PIXEL_PORT , PIXEL_BIT );
DELAY_CYCLES( NS_TO_CYCLES( T1H ) - 2 ); // 1-bit width less overhead for the actual bit setting
// Note that this delay could be longer and everything would still work
bitClear( PIXEL_PORT , PIXEL_BIT );
DELAY_CYCLES( NS_TO_CYCLES( T1L ) - 10 ); // 1-bit gap less the overhead of the loop
} else { // 0-bit
cli(); // We need to protect this bit from being made wider by an interrupt
bitSet( PIXEL_PORT , PIXEL_BIT );
DELAY_CYCLES( NS_TO_CYCLES( T0H ) - 2 ); // 0-bit width less overhead
// **************************************************************************
// This line is really the only tight goldilocks timing in the whole program!
// **************************************************************************
bitClear( PIXEL_PORT , PIXEL_BIT );
sei();
DELAY_CYCLES( NS_TO_CYCLES( T0L ) - 10 ); // 0-bit gap less overhead of the loop
}
// Note that the inter-bit gap can be as long as you want as long as it doesn't exceed the 5us reset timeout (which is A long time)
// Here I have been generous and not tried to squeeze the gap tight but instead erred on the side of lots of extra time.
// This has thenice side effect of avoid glitches on very long strings becuase
}
void sendByte( unsigned char byte ) {
for( unsigned char bit = 0 ; bit < 8 ; bit++ ) {
sendBit( bitRead( byte , 7 ) ); // Neopixel wants bit in highest-to-lowest order
// so send highest bit (bit #7 in an 8-bit byte since they start at 0)
byte <<= 1; // and then shift left so bit 6 moves into 7, 5 moves into 6, etc
}
}
Other techniques are also possible. I've had successes getting a UART to drive them...
http://wp.josh.com/2014/09/03/inside-neouart-tricking-a-serial-port-into-being-a-signal-generator/
...which can relax the timing requirements, especially on chips that have large transmit buffers.
PJRC has also famously gotten a DMA driven PWM to generate the correct signal...
https://www.pjrc.com/teensy/td_libs_OctoWS2811.html
(scroll down to "Technical Details")
...which is very complicated, but very cool in that there is almost no CPU load.
These are all easy solutions and are there are plenty of code examples for all of them. The right choice really depends on the application and what factors are important to you. |
H: Why do you have to use the nominal voltage of the transformer for the no-load or open-circuit test?
I was wondering why exactly you have to use the nominal voltage of the transformer for the open-circuit or no-load test. Is this also the voltage over the parallel elements, even in a situation where the transormer is loaded? Or in other words, do the parallel elements produce as much losses in a loaded situation with a source applied and in a no-load situation when the nominal voltage is applied?
AI: I think I understand your question so first here's a representation of the equivalent circuit of a transformer: -
Under no load conditions the only current flowing into the primary is the current taken by the "parallel components" Xm and Rc. For a normal power transformer that current will be small compared to the current normally taken by the primary when the secondary is driving a load. For that reason you can ignore (short circuit) Xp and Rp and of course the secondary is only producing an open circuit voltage so Rs and Xs are of no consequence.
The "thing" in the middle that looks like a transformer is a perfect power transformer and because no current is being delivered to the secondary that perfect transformer takes no current.
So, it boils down to Rc and Xm being connected to the incoming power and no further components need to be analysed.
I was wondering why exactly you have to use the nominal voltage of the
transformer for the open-circuit or no-load test.
There is one very important reason for this and that is core saturation - if you don't use the normal applied voltage you'll either have too much saturation or too little and you won't have a representive measurement. Saturation of the core is non-linear with voltage so it's important to use the right applied voltage. Look at the BH curve to see why: -
You can see that it is very non-linear once you start approaching saturation and, most transformers will be designed to run at a magnetic field strength (H) in the early to mid areas of saturation. This of course means a smaller transformer size and less iron. Commercial reasons prevail.
So, to do the test justice you need to run at nominal levels.
If you were doing a test to find out the values of the series components then you'd run the primary from a variac and short circuit the output. The sort of voltage that is now applied is a fraction of the nominal voltage so core losses are low (very linear BH curve) and eddy current losses (Rc) are also quite small. |
H: Burning Intel Microcontroller using AVR programmer
Is it possible to load hex file created to Intel 8051 micro controller using AVR USBISP programmer
This is the Datasheet..
http://pdf.datasheetcatalog.com/datasheet/Intel/mXqzvzz.pdf
AI: The datasheet confirms my suspicions : you don't program these, using AVR or any other programmer.
Instead, you send your finished and fully debugged program to Intel, and they mask it directly onto the device, before packaging it and sending it to you. (Minimum order, 10000 probably). Or more likely tell you that the last buy date was about 10 years ago...
As your 80C51s are already packaged, there is nothing you can do with them except whatever they are originally programmed to do. Ask whoever you bought them from for full information...
Either the 87C51 with its EPROM can be programmed, or the Atmel variety, (or TI or another 3rd party version with Flash or EEPROM can be programmed, but not the original. The date code will give you some idea how old they are - probably about 20 years old (probably 4 digits, beginning 95 or so).
Related Q&A...
EDIT : Dim memory , backed up by the comment from MarkU...
It is also possible to bypass the internal ROM, and add an external EPROM (or more modern equivalent). The 8031 was a variant without the internal ROM, but I believe you can use the 8051 this way too.
The disadvantage in that you need (1) an external ROM, (2) an external address latch (like a 74HC373) and (3) you lose 16 of your GPIO pins, specifically P0 and P2. For details how to operate the chip in this mode, see the datasheet. (I think it's as simple as wiring the EA/VPP pin to 0V). |
H: plugging battery against the power supply
This may come across as a rather nonsensical question however I think it is worth asking simply to understand what happened.
I plugged in an electric car battery directly to a wall socket, almost immediately there was a significant explosion in the wall socket. There was a power shut down in the entire house.
The battery was fully charged, and I was not using the cable to charge the battery, I was using the cable that is utilized for distributing power.
Basically, I pit the battery own power against the wall socket.
To make a simpler analogy, imagine an external portable battery, the ones that are used for charging electronic devices. The cable has two ends, one that is utilized for charging the battery. Then you invert the side of the cable to charge the device.
Same reasoning happened with the car battery, rather than plugging the battery to charge in the wall socket. (because it was fully charged) I plugged in the other side that distributes power. Then, there was an explosion and a shut down. why?
AI: LMAO firstly I hope you are ok. Secondly what were you thinking? Thirdly it is because 12v car battery, 120v+ in your house. Fourthly there was no regulation for the power. touch the two terminals of the car battery onto a metal fence outside using a piece of wire on each terminal of the battery you will get the same effect but obviously on a much smaller scale. Fithly as above, A.C. D.C.
May I ask, what were you trying to achieve? |
H: get many different signals through one wire
I am new here. I want something done, and I strongly believe there is an IC for this job, but I don't know what it is called and I can't get the right words into google. What I want is to take many electrical signals and have them pulse in a single file line, sort of to speak. This is for sending information to a computer via USB, I would also like to know of a way to separate singles by time, like chop up a 1 second pulse into 10 bits, with the idea that I will be sending 10 signals per second.
I plan on hooking up a bunch of Potentiometers to a usb port on a computer. The Potentiometers will be attached to a skeleton figure and will tell me the rotation of a bone at any given time. I will be making the software reading the Potentiometers.
AI: what you want is multiplexer, there are many different types of muliplexing
time division and frequency division are two common types of multiplexing.
you appear to be describing time division mulplexing in your description,
It seems to me you really only need a USB extender and a USB hub on the end to connect your devices to, USB uses a complicated form of time division multiplexing internally.
hoever if you want to build your own system you want to serialize the data at the source end an deserialize is at the other end. there are SERDES chips designed to do this sort of stuff but ther are likely a million times too fast.
for analogue signals like potentiometers you might find something useful in radio control encoders, these encode potentiometers to a time division multiplexed PWM signal, you can probably decode it using a sound-card and specialized software. |
H: Is it possible to use a potentiometer as a DP3T style control?
I'll try to be specific:
I have an audio application that has 3 inputs and 1 output. The classic answer would be to use a DP3T to switch between the inputs. However, I would like to have a continuously variable output, one that blends as you sweep a potentiometer.
Say for instance if the pot was fully clockwise it would give you the signal X, at the midway point, the signal Y, and counterclockwise the signal Z, but between noon and clockwise you would also get a blend of XY. X and Z would never blend, just meet with Y towards the middle of the pot throw. Is this something that can be done with one pot and VCAs, or a one pot mixer? I'd like to stay away from multiple gang pots, unless that is the only answer because my application requires vertical PCB mount and conformity of potentiometers.
Thanks!
AI: The simplest method I know of is to use a center tapped potentiometer. Although center tapped potentiometers are very rare now days. |
H: Basic Nmos amplifier working
I am trying to understand this circuit here.
I do not understand clearly how this works. I know that the PMOS is a current source but what impact does the resistor Rb have on this ? Could anyone help me out with its working ?
AI: Rb is biasing the NMOS into saturation (a good thing).
Rb is also a bootstrap Resistor (maybe good, likely not). Based on the size of Rb, this can do a few things. It can make the NMOS, look like:
A capacitive input
A pure resistive input (nice, but not practical due to tolerances)
An inductive input
It could also turn the circuit into an oscillator by destroying the phase margin. Bootstrapping is a fun thing. |
H: Designing a gate voltage for N-channel MOSFETS for H-bridge controller
We have a project where our 2nd year students build an H-bridge controller from scratch. They learn a lot about power dissipation. We have a simplified design using IRF540 for the N-channel, IRF9540 for the P channel. These are way over-spec for the application, tiny robot motors. WE use 6V batteries, so to turn on the gate of the N-channel transistors we can use the output of the Arduino, and to turn on the gate of the Pchannel we set gate to 0V, or leave in a high-Z state with a pullup resistor.
This works. However, we were thinking of extending the exercise to show all N-channel. That's the way it's done at larger scale because the N-channel has such dramatically better on-resistance. I think the difference is 0.004 ohms vs. 0.113 ohms, so it's significant. This would require that we generate Vcc + 5V for the gate.
For a teaching circuit, with a power side of 12V, is there a simple, clean way to generate a tiny current at a voltage 5V higher than Vcc? We would like to have them build the circuit, not just use a black box.
AI: 5V is barely enough to turn on an IRF540. The specified 0.077 Ohms Rdson is achieved with 10V Gate drive. You are probably getting away with the lower drive voltage because your motors are only drawing a small current.
The simplest way to get a voltage higher than the supply is to make a 'charge pump' using a couple of capacitors and diodes. You also need a driving waveform with sufficient voltage and current, which could be produced by a 555 timer, CMOS gates, an op-amp etc. Here's an example circuit:-
simulate this circuit – Schematic created using CircuitLab
This circuit should produce about 22V (10V of boost) at 5mA. Note that this voltage exceeds the FETs Gate voltage rating, so you must limit the Gate-Source voltage to less than 20V. |
H: 10 USB Hub ICs from 1 Crystal Oscillator?
I am designing a PCB with 10 individual USB hub ICs onboard. They all require a clock input and I am wondering if it is possible to drive all the clocks from a single crystal oscillator?
The hub IC is http://www.ti.com/lit/ds/symlink/tusb4020bi.pdf
AI: Yes, you can -- take a 24MHz oscillator and feed it into a clock buffer IC such as the CDCLVC1310 (http://www.ti.com/product/cdclvc1310). The buffer IC will allow you to do easy point to point links for each hub's clock. Please read the datasheet for that part in detail -- it has many clock input options as it supports single-ended, LVDS, SSTL, etc. Additionally, the datasheet for your hub says it wants a 1.8V input clock (Section 9.1.2) -- you will need a 1.8V supply (a LDO should suffice) to power the clock buffer's I/O rail (VDDO). You could even choose a single 24MHz crystal and provide it to that part to generate the ten copies of your clock.
A single oscillator has a maximum load on its output that will likely be exceeded by 10 USB Hubs. On top of that, you'd have to route the clock in a fly-by fashion with likely AC termination (since it is a clock this is easy) or Thevenin/parallel termination at the end to prevent reflections. If you imagine your single clock-source having to fan-out (which you identified in the other answer correctly), you can see why drive requirements + branching the signal can be troublesome.
Finally, my gut suggests that running 10 hubs in phase from a signal clock course may contribute to EMC issues and slightly stronger emissions, but I cannot quantify it. It would be 24MHz regardless, but this solution puts every hub in phase with the other. A solution with 10 discrete xtals would be at the same frequency, but likely out of phase with each other. |
H: Transistor with emitter attached to another transistor's base
I made a circuit that looks something like this:
simulate this circuit – Schematic created using CircuitLab
If I touch the loose wire with my finger, the LED will light up. Could someone explain what is going on? Is there a specific name for this effect?
AI: I don't see a bias network on the base of the driver 3904, so your finger, and the resistance of your body, is giving the base of the 1st 3904 the .7 volts it needs to saturate and turn on the junction, allowing current to flow through the collector-emitter junction and driving the 2nd 3904 on, doing the same, passing current through the diode and lighting it up. |
H: Power Electronics
I am currently building a wireless charger. I have difficulty in understanding the working of the regulator (7805) to which I connect the load and measure my output power.
My power receiver circuit schematic is like this
LC circuit(receives power from transmitter circuit) -> Rectifier(converts AC to DC) -> Regulator(7805)(for stable 5V power supply) [connected to resistor load]
I have two questions to understand on the regulator:
When I disconnect my regulator(leave the circuit open) I see my DC output like 30-40V, when I close the circuit (connect my regulator) I see voltage between 7 - 20V . Does the resistor (load) connected to regulator have any impact on this decrease in voltage? Is there any relation relating the load resistance and input voltage? Or any relation for impedance matching between them?
Note: I am keen on the relation between input to regulator and load resistor
To the resistor(load) to receive maximum power are there any design calculations to be done for regulator?
Please help! I am new to power electronics, I have difficulty in understanding these concepts
Thanks
AI: With a wireless charger circuit (ignoring the 7805 voltage regulator part) your receiver coil is trying to pick up the alternating magnetic field from the transmitter. It can have a good coupling or a less-good coupling as per the picture in one of the links: -
On the right with the receive coil further away it receives less magnetic flux. So if you looked at the voltage on your receive coil you would see an AC voltage that got bigger as you approached the transmit coil.
You could do a different test that has the transmit and receive coil fixed at a certain distance. That test would be to load the receive coil with a resistor and you would find that as you try and draw power from the receive coil, the receive coil voltage would fall.
Hanging a diode bridge and smoothing capacitor on the output makes very little difference except you'd be looking at a dc voltage instead of an ac voltage.
So that's the backdrop and of course the 7805 regulator and its output load want to consume a certain amount of power - that power is determined by the load connected to the output of the 7805 and the 7805 output voltage (5V).
When I disconnect my regulator(leave the circuit open) I see my DC
output like 30-40V, when I close the circuit (connect my regulator) I
see voltage between 7 - 20V
Hopefully that should be clear now from the explanation above.
Does the resistor (load) connected to regulator have any impact on
this decrease in voltage?
On its own the 7805 will consume a few tens of milli watts but when the load resistor is connected to the 7805, that power will increase because it's using power to charge a battery (battery voltage x charging current). This might mean 5V at 1A = 5 watts but there were no details in the question about this.
Is there any relation relating the load resistance and input voltage?
Or any relation for impedance matching between them?
Yes, load resistance changing will affect the dc voltage level because even when the receive and transmit coils are adjacent there will be an imperfect leaky transformer coupling and voltage will lower when more watts are required to charge your battery.
For impedance matching, you could make an argument for developing a circuit that tried to optimize the max power output from the coils. This would toss-away the 7805 voltage regulator and replace it with a buck-boost regulator and power monitoring circuit (the same as what is used in sophisticated solar panel charging circuits to optimze the power transfer based on amount of sunlight). But this is way too complex for a simple non-contact low power charging circuit.
To the resistor(load) to receive maximum power are there any design
calculations to be done for regulator?
I've designed systems like this to provide magnetically coupled power to electronics on rotating machines and the calculations rapidly become too cumbersome so I simulate the leaky-transformer effect of the transmit and receive coils. If a working prototype isn't good enough (say for transferring a couple of watts at 40mm gap I rethink, rewind and retune. |
H: Oscilloscope measuring different voltages "across" the components when two probes are used
I'm having problems displaying two channels simultaneously on an oscilloscope when both probes are connected to measure voltages "across" the components.
To demonstrate the problem two resistors are connected in series and fed by a function generator. So the aim is to display the voltages "across" both of these resistors.
Okay so I first connect only one probe to one of the resistor's terminals as in the photo below(this photo is a bit blurry sorry):
And in this case what I measure in oscilloscope's CH1 is in the below photo:
So far so good. But now I hook up the other oscilloscope's probe to the other resistor as in the photo below:
But in this case what I measure in oscilloscope's CH1 is totally different as in the photo below:
My question is:
1-) Is my setup wrong? Is this a wrong way of displaying voltages across the components in an oscilloscope? (Is that because the probes have the same ground?) Or the oscilloscope is defect?
2-)How can I work around this issue? I was planning to see the phase difference in an AC circuit between a capacitor and a resistor for instance. For that I need voltages "across" their terminals not relative to circuit GND.
Note: I'm using a "Velleman HPG1 1MHz Pocket Function Generator" with 100Hz sine wave, and a Siglent 100MHz oscilloscope.
EDIT: Here is the basic schematics:
Each probe is connected in a way that their crocodiles and probe tips wired across resistor terminals as in my photos.
AI: Look at your picture here: -
Because the crocodile clip connections on most common o-scopes are grounded to each other at the o-scope you have effectively shorted out R1 (indicated by the red line). |
H: Connect 12V digital LED strip to Arduino
How to connect a T12V-10L-30LED-W LED strip to an Arduino?
Here is the strip specification.
And here the actual image of the strip:
The package says:
VCC: RED
GND: WHITE
DAT: GREEN
My question now is: Does the DAT input take 12V or something else? And how to wire this with an external 12V power source?
AI: The datasheet isn't that helpful =(
But to power your led strip you need an external 12V supply, for that you can either:
Get a power converter (similar to phone charger) - Or battery - and power the arduino using it(through the arduino's DC 2.1mm jack).Then connect your LED strip to the Vin pin - not the 5V! - and ground the strip directly to the power supply since the arduino can't sink more than 0.2amps.
OR
get a power converter from a regular electronics store and just cut the wires and connect them directly to your strip.
Make sure you get one that can provide 12V and supply at least 0.6amp for every one meter of the strip.
OR
you can get a 12V battery instead and connect them to the strip directly.
As for the Data line,there's not much i can help you with but it seems like your going to need to do some testing.
Someone please correct me if i'm wrong...
Power the LED strip and connect the DATA line to an analog pin and then increase the AnalogWrite from 0(0V) all the way to 255(5V). What you're looking for here is to see if it works on 5V or 3.3V. Or if the DATA line actually takes an analog input. |
H: Raspberry PI audio over Cat5e wired ancient hotel intercom
My question is can I (and how might I with minimal insanity) connect the audio output of a Raspberry PI (and/or other USB audio outputs) via say some 10-30m of Cat5 cable to some 10 or so pretty ancient looking hotel room speaker units, which might have amplifiers in, or might not!
To really understand why I'm asking what must seem like an utterly MAD question, clearly some additional information is required...
So, to briefly set the scene - my parents have moved into a new home, which was once a hotel, and as part of the EXTENSIVE renovation they decided to keep the old hotel intercom system as a bit of a nod towards its history and heritage of the place. I think it's quite wonderful so I'm glad they kept it. An electrician has already moved the central unit and replaced all wiring to the room units (I think using Cat5e) and it seems to work... at least some of it does, I at least managed to get some functions working to send voice to rooms and stuff, and make the message LED light up.
For interest, and context, here's a few photos of the central unit...
And the room units...
Now though the intercom works, the radio does not. I suspect there is no radio function in the central unit, and probably never was, though this might be an ignorant assumption on my part. I see nothing that looks like tuners (of which presumably there should be four (one for each channel on the room units)), and the chips all seem like either non audio, or stuff like op-amps and attenuators that one suspects are for the intercom audio, nothing especially obviously radio like specifically. As you can see from the photos, the circuit boards are pretty old technology.
Since radio reception in the area is truly dire even by roof aerial (and there is no roof aerial connection available near the central unit even), this might in any case be no great loss, so I was wondering if I could achieve a modern upgrade/addition to the system; an addendum to its history, in the form of internet streamed radio supplied from the central unit!
So my (first) sub question is actually, is it reasonable to expect the room units have amplifiers, and hence I should not be thinking of providing real speaker driving power from the central unit to the rooms or is this system more likely designed with all the driving power achieved in the central unit? I realise no one can know this unless they've come across a very similar system, but I imagine there is a more sensible design option that has likely been followed. Clearly any power for amplification must go over the Cat5 too, as there is no power delivered to the units separately.
If there are amplifiers in the room units, would the Raspberry PI audio out or other USB audio outputs need amplification? There seems to be enough power in such things to drive small headphone type speakers at least, so does that mean driving a bunch of amplifiers with quite a bit of cable in between is OK and can I just connect all of them in parallel or am I out of my mind?
If there not amplifiers in the room units, should I be thinking of one amplifier capable of driving all the units at once, or many separate drivers? And if I drive them from the central unit like this, should I add the impedance of the wires to that of the speakers when considering sizing?
Any extra comments/advice is of course welcome. I'm happy to do research and work at it a bit, but though I am slowly trying to get into electronics, I'm still at the stage of feeling like it's wallowing through treacle; I'm liable to make dumb mistakes on a project like this if I'm not careful.
I have 4 wires to work with, because the electrician used 4 of the 8 Cat5 cores. Not sure if this means I can get all 4 radio channels going or not, in my mind it seems possible, if one of the other wires is a ground, then there are 4 wires for 4 radio stations, but there are eight unused connections on the wall units (most of which seem to go to the radio channel knob) which worries me a bit, but if I could get one channel going only that would still be a great thing, because if nothing else my mum is a great radio fan and would love to go from room to room switching radio 4 on and off without carrying around a radio (which works very badly if it works at all anyway).
Edit (following answer post): not ideal, but I do also have this photo peering inside the wall unit! Not a lot to see, a capacitor, a few diodes probably, transformer. There's obviously not a huge amount, though there is something big and shiny I can't guess at.
AI: There's some lovely 60s brushed-aluminium-and-wood casework there! And quite a decent job by whoever renovated it, and did you the favour of labelling the wiring on the inside of the case.
You might get a better reception on /r/electronics than here, due to the open ended nature of the question. Step 1 has to be to reverse-engineer the original system, either by finding its original service manuals on the internet or by drawing a circuit diagram from the single-sided PCB. It's quite clear from just looking at it that all those unused screw terminals connect to the four-position radio channel switch. It looks like there is no local tuner as you say, the switch selects an audio signal from the screw terminals. Whether it amplifies it locally is unclear: we could do with a photo of the other side of the PCB, which will involve taking the knobs off (grub screw visible at top) and undoing the nuts on the shafts. I suspect (given your comment about power) it doesn't amplify it locally, or the amplification is only for the microphone (which I can't locate visually). |
H: Verilog: Are there some basic rules for port settings?
Iam trying to write a SPI master module by myself to learn FPGA-Verilog efficiently. Here is the spi_master module:
module spi_master(
output [15:0] tx_data,
input [15:0] rx_data,
output mosi,
input miso,
output cs,
output sck,
input start
);
reg [15:0] tx_data;
reg [3:0] tx_counter;
reg [3:0] rx_counter;
wire start;
reg cs;
reg mosi;
wire miso;
wire sck;
initial begin
tx_counter [3:0] = 4'b0;
rx_counter [3:0] = 4'b0;
end
always @(negedge sck) begin
if (cs == 0 && tx_counter != 4'b1111) begin
#(5) mosi <= tx_data[tx_counter];
#(6) tx_counter <= tx_counter + 4'b1;
end
else if(cs == 0 && tx_counter == 4'b1111) begin
#(5) cs <= 1'b1;
end
else if (cs == 1 && tx_counter == 0) begin
#(5) cs <= 1'b0;
end
end
always @(posedge sck) begin
if (cs == 0 && tx_counter <= 4'b1111 && tx_counter >= 4'b0001) begin
#1 rx_data[rx_counter] <= miso;
#2 rx_counter <= rx_counter + 4'b1;
end
end
endmodule
And here is the test module;
`include "spi_master.v"
module spi_master_tb(
);
reg clk;
reg start;
reg mosi;
wire miso;
reg cs;
reg sck;
reg [15:0] tx_data;
initial begin
clk = 0;
tx_data = 16'hF0AA;
#20 start = 1'b1;
#1000 $finish;
sck = 0;
end
always begin
#1 clk = ~clk;
end
always @(start) begin
#10 sck = ~sck; // divided clk by CLK_DIVIDER
end
spi_master SPI_block(
tx_data,
rx_data,
mosi,
miso,
cs,
sck,
start
);
endmodule
the spi_master module can be compiled without error but when I try testbench I get this error:
ERROR:HDLCompiler:1660 - "C:/Users/aozel/Desktop/FPGA Projects/myModule/../Test2/spi_master.v" Line 74: Procedural assignment to a non-register rx_data is not permitted, left-hand side should be reg/integer/time/genvar
Why is this? Also when I add: reg [15:0] rx_data; to the spi_master module this time I get this:
ERROR:HDLCompiler:661 - "C:/Users/aozel/Desktop/FPGA Projects/myModule/../Test2/spi_master.v" Line 24: Non-net port rx_data cannot be of mode input
Why is this happening? I ve read somewhere that says never set inputs as regs. But editor throws exact opposite suggestions. So, to sum up, Are there basic rules for port settings in Verilog? How should I start?
And secondly, I really did not understand why we should not use registers as inputs. Why is that? Where will I store inputs? How will I read them? I think I have to use registers for inputs which is not considered as interrupts. Can someone explain it? I d really appreciate.
AI: Just to start out, at the top of your spi_master module, you have rx_data declared as an input. Then at line 74 (I assume, I didn't count) you have
#1 rx_data[rx_counter] <= miso;
If rx_data is an input to spi_master, then spi_master should not be assigning any values to it. The values should be assigned by the instantiating module (or test bench) and given to the spi_master instance as inputs.
If the intent is that your receive data on the miso line (because you're the master) and then make it available in a parallel word to the code where your module is instantiated, then rx_data should be an output from this module.
I also see an issue where you have tx_data and mosi both declared as outputs. If the intent is to take tx_data in parallel, and convert it to serial data on the mosi line, then tx_data should be an input to your module.
I really did not understand why we should not use registers as inputs. Why is that? Where will I store inputs? How will I read them?
You can't make an input a reg because you aren't going to assign to it in the module where it is an input.
You will assign to it in the higher-level module. Whether you declare it as a reg or not in that module depends on how it's assigned to. If it's assigned in an always block, it must be a reg. If it's assigned in an assign statement, or it's the output from another module, then it must not be a reg.
Generally, I'd say you need to think more carefully about what's an output and what's an input to your module. Think about if you were drawing a block diagram of your design, and each instance of your module were represented by a block. If the the signal would be flowing out of the block, that's an output. If the signal would be flowing in to the block, that's an input. |
H: Working principles of an LDR Light Switch
This is a simple circuit which dims the LED according to the light recieved by the LDR or simply a light switch.
Can anybody explain how two BJTs opearete in the circuit, or simply how the system works?
AI: Assuming everything is biased reasonably, ...
More current through LDR1 produces more current into the base of Q1.
That produces more current into the collector of Q1, which would normally mean more current through R1.
But, the voltage at the collector of Q1 is effectively pinned by the LED D2. So what actually happens is that more current into the Q1 collector has to come from diverting current that would otherwise have gone into D2, and the voltage there only changes very slightly.
Since there's less current flowing through D2, the light output is dimmed. |
H: USB protocol PIC32mx
I am adapting a design using a PIC32MX (which is actually working) to put an extra add-on. The add-on is a fingerprint reader which communicates via UART. Regarding that I have the USB pins exposed in my design, I found a way to connect a ftdi 3.3V (https://www.sparkfun.com/products/9716) between UART and USB.
I am planning to connect my VCC ( 3.3V in my design , which I believe it can give me more than 200 mA) to the VUSB red wire cable. The other pins are straight forward.
So my questions from now are:
The purpose of the VBUS pin on the PIC32mx is to recognize if there's any device plugged or not, right? Is there any problem if I leave it not connected?
Do I need to connect the VBUSON pin to somewhere? I am already using for something else (the pin is shared/not dedicated).
AI: Q1: No. The VBUS pin is used when your PIC32MX is itself acting as a device and it tells the PIC32's USB module when it has been connected to a USB host (like a PC) by detecting the nominal 5V which should be present.
Q2: As the manual tells us, the VBUSON pin is "USB Host and OTG bus power control output". In other words, this pin turns the Vbus 5V output from your board on/off when your PIC32 is acting as a USB host.
To address a question which you haven't asked ... your PIC32 must be operating as a USB host in order for your FTDI USB UART to be of any use. This means that it must be configured correctly and running a USB host firmware stack. |
H: Can I connect the negative terminals together on two LED drivers?
I have a white, adjustable-color-temperature LED strip that I'm trying to power. The LED is basically composed of two separate LED circuits -- one at 6500K and another at 2700K. The strip has one positive lead for each circuit and a shared negative lead.
Can I connect matched, constant voltage, dimmable LED drivers like this? Is that crazy?
simulate this circuit – Schematic created using CircuitLab
AI: "Dimmable transformer" makes no sense, so I don't know what those blocks on the left are. Transformers put out AC, which your LEDs aren't going to like much.
I'll assume these things are some kind of power supply. Since line AC is coming in and these are intended for consumers, I'll also assume they are isolated. In that case, you can hook them up as you propose. Each will drive one LED string without getting in the way of the other. |
H: UART is acting weird
I programmed UART3 peripheral on LPC4088 to send a single unsigned character posiljka over Tx line. This is done by continuously copying this character into the Transmitter Holding Register (THR) which is the top of the transmitter FIFO.
So I connected my oscilloscope to the Tx line and tried to sent these characters over while recording their oscilloscope images:
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x25, 0x26.
Oscilloscope images looked fine at the beginning, but once I reached values 0x20, 0x21, 0x22, 0x23, 0x25, 0x26 I noticed that oscilloscope images for these characters look the same than those for images 0x00, 0x01, 0x02, 0x03, 0x04, 0x05. How is this possible? Here is the compressed folder with all the images (please don't pay attention to measured frequency which is wrong as oscilloscope takes wrong edges to measure it).
My C program was supposed to set UART3 communication to be 9600 8N1 which means 9600 baud rate, 8-bit character length, no parity and 1 stop bit but width of the sent character looks two times shorter to me from the beginning.
Here is the program:
#define IOCON_P0_0 (*((volatile unsigned int *) 0x4002C000))
#define IOCON_P0_1 (*((volatile unsigned int *) 0x4002C004))
#define PCONP (*((volatile unsigned int *) 0x400FC0C4))
#define THR (*((volatile unsigned int *) 0x4009C000))
#define DLL (*((volatile unsigned int *) 0x4009C000))
#define DLM (*((volatile unsigned int *) 0x4009C004))
#define LCR (*((volatile unsigned int *) 0x4009C00C))
#define LSR (*((volatile unsigned int *) 0x4009C014))
#define FDR (*((volatile unsigned int *) 0x4009C028))
int main(){
//we use UART3 on pins P0.0 and P0.1 with on-chip and external pullup-resistors
//we set P0.0 and P0.1 as U3_TXD and U3_RXD, no-pullup, no-hysteresis, no-inversion, standard-mode, open-drain (0b0100000xx00xx...)
IOCON_P0_0 &= !(0x67F);
IOCON_P0_0 |= (1<<1);
IOCON_P0_1 &= !(0x67F);
IOCON_P0_1 |= (1<<1);
//we turn on UART3
PCONP |= (1<<25);
//we set 8N1 communication in LCR (we only have to set first 2 bits because rest is already set properly by default)
//we also set LCR.DLAB = 1 so that we can aces DLL and DLM in next paragraph
LCR |= (0b11);
LCR &= !(0b0011111);
LCR |= (1<<7);
//we set DLL[0-7] = 96 and DLM[0-7] = 0 which sets baud rate to 9600 - check referenced user manual, page 510.
//we don't need to manipulate FDR register as DIVADDVAL=0 and MULVAL=1 are already set ok by default - check referenced user manual, page 510.
DLL |= 0x96;
DLM |= 0x0;
//we set LCR.DLAB = 0 back to original value and can now acess THR
LCR &= !(1<<7);
//we enable Rx and Tx FIFO
FCR |= 0b1;
while(1){
//here is where we set the character to be sent
unsigned char posiljka = (0x25);
//we input character "posiljka" into THR and send it.
THR = posiljka;
}
}
Am I missing anything?
AI: The ! operator in C is a logical operator and it produces a result which is either true (1) or false (0).
You seem to be looking for the bitwise NOT operator which is ~, not !
The result of !(0b0011111) is simply 0 (or 0b0000000 or 0x00 or however you want to represent it), while the result of ~(0b00111111) is 0b11000000.
Even if you correct this, you still have code which appears to 'contradict' itself.
You have LCR |= (0b11); which sets the least-significant 2 bits of your LCR register, and then on the next line you have LCR &= !(0b0011111); (and I'm assuming you meant ~ and not !) which immediately clears those 2 bits. |
H: How to get more watts from a 1W amplifier?
I'm a newbie in the world of electronics, and I decided to build a 3 watt amplifier.
I searched arround the web and I found the following schematic for a 1W amplifier:
(source: hackaweek.com)
Note: Put a 2k resistor in between the ground and the emmiter if you want to prevent little distortion.
My questions are:
What is the "next stage output" used for?
Can I put there more amplifiers if I want to gain more watts?
AI: This is a pre-amp for a microphone circuit. You can tell because they've tied the input to power through a resistor.
The next stage is there to feed the signal to either another amplifier stage or to feed it to a buffer stage. You'll need more reading to know which to use.
You can put more amplifiers to gain a larger signal. I hesitate to use the word "Power" because most people worry about the power as it is delivered to the load (a speaker). But be aware that your signal's Voltage gain is limited by the power rail, and that it's current gain is limited by how much current your supply can handle. |
H: Normalizing audio signal for ADC input
What is the best way to limit an audio signal for ADC input (to 0V - 3.3V) with out disrupting it harmonically? Ideally, I'd like the conditioned signal entering the ADC to be a signal uniformly spanning 0V to 3.3V. That is, I'd like to strip the original signal of its envelope and have a flat envelope at the output. I've spent the better part of a month attempting to get simulations of different VCA circuits to respond to these specifications using variations on the original input signal's envelope as the control signal. I know near-blind trial and error through simulation is not the most elegant way to go about design but I'm early in my EE studies and it's all I have.
Is there a standard scheme for this kind of signal conditioning?
Is designing a circuit, whose response is consistent across the audio band (or a good part of it), which attenuates/amplifies a signal, varying from 0.1Vpp to 6Vpp, to a uniform 3.3Vpp signal with negligible change to the harmonic content (negligible meaning that an FFT would still faithfully report the first several harmonics of the original signal) a realistic goal?
AI: What you are asking for is a non-linear operation, so will add distortion.
The details are all in the tradeoffs you haven't told us about, particularly response time. For example, suppose there is a loud passage, then it gets quieter. What metric do you use to decide this quiet isn't part of the signal that you want to keep, like a person pausing between words? Are you allowed to look ahead (store signal, then play back later)? If not, how long is long enough to decide that quiet is the new normal? Notice that you don't get to say "instantly", since audio is iherently AC, which will have regular zero crossings.
People have been dealing with these issues and making these tradeoffs in various ways for a long time, before there were even transistors. Look up something called AGC (automatic gain control).
Otherwise, without a real spec, there is little we can help with. |
H: Texas instruments C1101 RF1100 module Schematics
does anyone got schematic from this module. I tried searching around but didn't get anything except main header pin-out. There are also 2x2 pin on each corner, but there is no info about them.
AI: If you look closely, you see the four small copper lines that connect the 2x2 pins to the ground plane. My multimeter confirms this: 0.4 Ohm from ground to each of the 'pins', the same reading for shorted probes.
Besides the chip there isn't much on the PCB that could be interesting: a 26 MHz crystal, a maching network for the antenna, some power decoupling. Probably a copy of the circuit on p25 of the datasheet: |
H: Wiring identical LEDs in parallel
I am working on a project in which I am powering several 20 ma LEDs off of a 12 volt supply. I therefore need a 470 ohm resistor. The only problem is I don't know how many LEDs I will need. I know that powering say, 4 leds in parallel off of one resistor is a bad idea because of potential current differences, but if all the LEDs come in the same package from an online order, does that mean it would be safer at least?
http://www.amazon.com/gp/product/B007SJ8XP0?psc=1&redirect=true&ref_=ox_sc_act_title_2&smid=A3AGVPZHIH41EE
AI: Just because they are in the same consumer/retail/commercial package does not mean they are from the same production run, or same bin. They are not guaranteed to have the same diode properties for forward voltage or current or brightness.
You can attempt to match them for current and brightness, but the simplest solution is to use one resistor per parallel circuit. Resistors are cheap and small.
The typical efficient setup for white leds at full brightness 20mA @ 12 Volts is three leds in series with one resistor. Repeat for additional strings of three. You could do two per resistor if you adjust the resistor value. |
H: connect 2 speakers to act as a telephone
I've got this very faint memory from my childhood that my dad connected 2 pieces of old, 5 cm diameter speakers to each other with a 10 meter wire. And without any other equipment, it would transmit the sound between rooms. Not loud or anything, but volume was enough to hear what the other was saying.
Got me thinking, after all, the sound waves move the coil, that generates electricity that would move the coil in the other speaker too. If the mouth is close to the speaker, it could work.
But I never found anything like that while googling for this. Could this actually work?
AI: It's called a sound powered telephone (wiki) and they are used: -
(source: soundpoweredtelephone.com)
Wiki says: -
A sound-powered telephone is a communication device that allows users
to talk to each other with the use of a handset, similar to a
conventional telephone, but without the use of external power. This
technology has been used since at least 1944 for both routine and
emergency communication on ships to allow communication between key
locations on a vessel even if power, including batteries, is no longer
available. A sound-powered phone circuit can have two or more
stations on the same circuit. The circuit is always live, thus a user
simply begins speaking rather than dialing another station.
Sound-powered telephones are not normally connected to a telephone
exchange.
Note the hand crank magneto on the right for generating a voltage to ring the bell to attract attention. You can get the ringer magneto replaced with a battery oscillator - I designed one back in the 80s for use on British Railways - no power available! I think I've still got the prototype in my garage - it was a leaving present: - |
H: How to connect TPA7297 S-GND and PW-GND
I've just started making an amplifier for some speakers and I'm completely new to this and couldn't find any information in the documentation explaining it. So I just wanted to know if S-GND and PW-GND can be connected to a common ground back to the negative battery terminal? If not how would I go about connecting the grounds up?
Datasheet: http://www.st.com/web/en/resource/technical/document/datasheet/CD00001048.pdf
Thanks in advance :)
Will
EDIT I'm making the standalone version
AI: Yes, in most applications, the grounds can be tied together.
Note that you actually have all the documentation you need; the schematic in the datasheet for "stand-alone application" shows the grounds tied together. |
H: Best method/circuit for converting 240VAC to 5VDC (Low power)
In short, I'd like to power Arduino-like devices (small PIC devices as well) run off of a mains socket at 240VAC - which obviously can't be done with a simple wire. I assume I'd need an output anywhere between 3 and 5 volts DC.
I don't want to use a generic plug power supply as they're usually designed for higher current outputs (I'd probably need 500mA at most - the processor and a couple of LED indicators), can cost a reasonable amount and I'd like to up my electronics knowledge/DIY skills by creating something myself (even if it is just a couple of soldering joints).
Also, when I say "best", I mean either the simplest to build or most efficient (or a combination of both).
My apologies for the generic question, I've just never done this sort of thing and I'm not sure how to word it properly.
AI: The way you would need to do it is design a flyback SMPS - This is what is in every USB charger ever made... So why design it again when you can just pick one up for 5$ somewhere, the design will be long, and if not done right, it could be deadly.
Keep in mind 5V @ 500mA is not really 'low power' that was the normal USB supply for the last ~10 years. That is 2.5W...
I'll also add they are fairly efficient. A well designed USB charger with synchronous rectification should be >80% efficiency. You will be hard pressed to get this level of efficiency from your first custom design... |
H: How to combine two chip enable(/CE) signals into one with discrete components?
My VIC-20 has a few bank select lines that are used for enabling ROM chips on the cartridge port. When one of them goes low, it means that a certain 8KB region of the address space has been accessed.
Usually you can hook these up directly to the chip enable (/CE) pin of a ROM chip to essentially place that 8KB ROM into a certain slot in memory.
However, I have a 16KB ROM with only one /CE pin which means that I need to combine two bank select lines. I know I can do this with a single AND gate (since the logic is inverted), but it seems like a waste to use a quad-AND or NAND chip if there was a simpler solution.
Note, only one of the bank select lines ever goes low at a time. So the truth table would be kind of like:
A|B|O
-----
1|1|1
0|1|0
1|0|0
0|0|Never happens
Is there an elegant way to do this with discrete components?
AI: Diode-OR them:
simulate this circuit – Schematic created using CircuitLab
Either input can pull the output low, and only the pullup will pull it high. |
H: 3V7 to 5V level conversion
In my product i am using a wifi module requires 3.3v and a bunch of other components requires 5v. For this i am using 3.7v 3000mAh battery. So here i have a doubt whether to use which case or any other suggestions
case 1: To use two 3.7v battery in series becomes 7.4 so that i can use a 3.3v regulator to convert from 3.7 and a 5v regulator to convert from 7.4V as in below fig.
simulate this circuit – Schematic created using CircuitLab
case 2: Use one 3.7v battery and use a 3.3v regulator and 5v booster(if this please suggest a good circuit or module). If i use this does the power consumption increases and batter level reduces in short time? or it doesn't?
AI: Never put a load across only a single cell of a battery. You will pull the battery out of balance leading to shortened operational life. Put the 3.3V regulator either across the entire battery or after the 5V regulator. |
H: How to filter out ringing current in a local battery telephone system?
We have a network of manually-switched local-battery telephones. Here is depiction of the circuit in one telephone:
Ü transformer
OB local battery (1.5 V)
GU hook switch
F speaker
M microphone
Ind magneto (30–100 V, 15–30 Hz)
W ringer
We have a switchboard where we can manually connect subscribers with one-another. Since this can take a while, we would like to play hold-music while we establish a connection. Hold music is being played back by connecting the output of a sound card to the A and B leads of the telephone we'd like to play music to.
This works great unless the subscriber starts to crank the magneto. This fries the sound card. How can we construct a simple filter that protects the sound card from the ringing voltage, while letting the music through?
I thought about a simple high-pass filter, but I have no clue about how to construct one and I prefer to use a design someone more competent than me designed because frying sound cards is an expensive way of testing things.
I would prefer a solution that does not require any additional power source.
AI: Simply coupling the signal via a small capacitor will act as a high-pass filter, however the output waveform of a magneto is very peaky and has harmonics that could be hard to filter out without affecting the audio.
To provide complete protection you should put back-to-back Zener diodes across the signal wires wires to clamp voltage spikes, and a resistor in series to limit current. Usually a transformer is also inserted to isolate the computer's ground and provide a balanced output to the phone line.
Here's an example of a passive phone line interface (it has two identical circuits for input and output - you only need one of them).
Computer audio interface to wire-based telephone network |
H: Atmega basic circuit with or without crystal
I want to build a basic Atmega8a (DIP-28) micro-controller circuit (programed using a 10 pin ISP socket).
I have found several basic circuits. Some of them use crystal oscillator, some use internal oscillator.
1- What options we have when it comes to oscillator? (different methods of using internal and external oscillator).
2- When we use which?
3- What problems each might pose when transferring programs to the chip using an ISB programmer (say USB ASP). Which one is easier to use?
AI: First, I will really use 6 pin instead of 10.
Internally, you can use 1, 2, 4, 8 MHz. Externally, you can use from 32k-16 MHz. You probably can use higher than 16 MHz, but I haven't tested that.
Normally I will use 8 MHz internally when timing is not that important. If timing is important, I will use a high accurate 16 MHz externally. The crystal from a Uno is not considered high accuracy. The time when you use a lower frequency is when you are powering your project with a battery or the code is very simple that doesn't require high frequency. You set this up by setting the fuse.
In term of uploading, they are all the same if you plan to upload with a programmer. |
H: How to power a circuit that needs +9VDC, GND, -9VDC?
While I have an assortment of 5V, 9V, 12V wall-warts, but I don't remember ever seeing one that is 18VDC and trying to avoid a trip to specialized parts shop, since I have all other components of a circuit (of a microphone mixer) that I am building.
Here is the circuit in question:
(Source: http://www.aaroncake.net/circuits/mixer2.asp)
As one can see, it requires +9VDC, -9VDC and GND. I've never built such circuits that have negative potential (I know it is relative). Wondering if someone can help illustrate / explain, if it is possible to power this somehow using a 9VDC wall-wart ?
AI: You will probably find that two 9V wall warts will do the trick - connect the positive output from one to the negative output from another - this connection is the "new" 0V and you'll have +9V and -9V available - regard it as two 9V batteries in series with the middle (common) connection being called 0V.
Because wall warts produce isolated output voltages, they can used like this but always double check with a meter first to ensure everything looks and feels OK.
Looking at your op-amp circuit you should be able to get aways with a single 12V wall wart and a rail splitter made by two resistors across the supply. The junction of those resistors will be 6V up from the negative rail and ALL the points marked with an "earth" symbol on your circuit can connect to this point. This is a much used technique but, as always, it won't suit every target circuit but looking at your circuit it should be OK. |
H: 555 timer circuit power consumption
My goal is to have an LED flash (rather than stay on all of the time) in order to conserve battery life. So, I learned how to modify a 555 timer circuit so that the LED flashes for about 0.1Hz and remains off for ~10 seconds.
The circuit diagram is like this:
Source: http://www.electronics-tutorials.ws/waveforms/tim58.gif?81223b
Are there other components in a 555 time circuit (resistors, capacitors, 555 itself, etc) that are drawing energy and will significantly affect my battery life, even though I have greatly reduced the duty cycle?
AI: As Nasha has already pointed out, using a CMOS 555 will greatly cut down on the quiescent current required from the battery, as well as eliminate the huge shoot-through current spikes inherent in the bipolar 555's output totem-pole every time it switches.
Another area of concern is the timing capacitor's chemistry and capacitance.
In order to minimize its own leakage, the cap should be something other than electrolytic, (plastic or ceramic dielectric, say,) and its capacitance should be selected to be as small as possible and, in the circuit you've linked to, the value of the resistors should be made as large as possible since every time the cap charges and discharges all that energy is just wasted.
Also, C2 can be eliminated. |
H: Questions about FM Mic Kit Schematic
I'm currently building an FM Microphone kit and I'd like to understand its operation before physically putting it together. The documentation only provides an overview of some aspects and provides no calculations or insight into the selection of component values.
Am I correct in identifying R1 and the condenser microphone (hereafter Mic,) and R2 and R3 as voltage dividers?
Given an input of 9V, R2∩R3 will output 1.59V?
For R1∩Mic to be in voltage equilibrium with R2∩R3, the impedance of the Mic at rest must be 59KΩ?
Why is a polarised type used for C1? (a tantalum cap was provided in the kit if that helps)
What are C2 and C3 doing? Do they form some sort of lowpass filter?
To keep the LC tank oscillating, how do you calculate what power to inject each cycle? (I know it has to be in phase)
AI: You are correct
You are correct although it might be a tad lower because of a little bit of base current but the important point is that the BJT will be biased.
No this isn't important - the output impedance of the microphone circuit will be approximately 27K (R1 acts as drain resistor for the internal JFET in the mike)
C1 doesn't need to be polarized - I would pick a ceramic capacitor and avoid an electrolytic because it's unclear which side will have the more-positive voltage
C2 and C3 hardly do anything at audio frequencies but, at 100MHz they ensure that the base is strongly de-coupled - this improves the modulation process and may in fact prevent it if they were not there.
C4 injects the positive feedback power into the emitter and the collector will naturally be in phase and produce a higher AC voltage thus ensuring oscillation. There's a lot more to how this works and how the centre frequency of the tank will be slightly shifted from theoretical but this appears too much to discuss at this point. |
H: Calculate voltage and current in time dependent circuit
I'm working with this time dependent circuit, and i'm having troubles with some of the assignments.
The following values are given R1 = 1kΩ, R2 = 2kΩ, R3 = 1kΩ, C1 = 22uF and C2 = 47uF. Is delivers 20mA, and when t=0 the switch goes from connected to disconnected. The circuit is stationary for t < 0 (when sure what that means?)
First of i shall calculate the current through R2, when T<0. Is it right when i assume i should use current division? Calculate the total Ω of the circuit, and divide by R2, times the 20mA?
Next, i shall calculate the voltage across C1. That one i'm uncertain about. I have found a formula V = q/C, but i can't seem to find q, the charge, or neither how to calculate what?
Lastly i shall find an expression for the current i(t) for t>0. Here i'm a little lost, so hoping for some guidance
Might be rather easy, but for a newbie, who have been introduced to all at once, its hard to find head and tail,
Hoping for help!
AI: Typical homework problem. I think of it as two steps:
Setup of Cap. Voltage via introduced energy
Discharge of Cap. Through Connected Impedance
The current division between R3 and R1 + R2 in series gives you the setup current (I label it I_0) (since R3 < R1+R2, the most current should go into R3)
I0 * R2 Gives you the voltage in the node that is connecting R2, C1, C2 (I name the node n1 and the voltage V_0)
Total capacitance of two parallel caps is the sum C1 + C2 = C'
the time constant is then R2*C' = tau
Classic RC-exponential discharge curve, R2 is the current path:
V(t) = V_0 * e ^ -(t/tau)
and V = R*I gives V(t)/R2 = i(t)
easy as pie.
All these tools are easily searchable in any electronics schoolbook or the internet. |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.