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| <title>Primordial HIR-SPU Β· GPU Architecture Map</title> |
| <style> |
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| *{box-sizing:border-box;margin:0;padding:0} |
| :root{ |
| --bg:#08060e;--bg2:#0e0b1a;--bg3:#120f22; |
| --purple:#a855f7;--pink:#e879f9;--cyan:#22d3ee;--green:#4ade80; |
| --orange:#fb923c;--red:#f87171;--yellow:#fbbf24;--blue:#60a5fa; |
| --white:#e2e8f0;--dim:#64748b;--dimmer:#334155; |
| --mono:'Share Tech Mono',monospace;--display:'Bebas Neue',sans-serif;--body:'DM Sans',sans-serif; |
| --glow-purple:0 0 20px rgba(168,85,247,.35); |
| --glow-cyan:0 0 20px rgba(34,211,238,.3); |
| --glow-green:0 0 16px rgba(74,222,128,.25); |
| } |
| html{background:var(--bg)} |
| body{background:var(--bg);color:var(--white);font-family:var(--body);min-height:100vh;padding:20px 18px 50px;overflow-x:hidden} |
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| /* scanlines */ |
| body::before{content:'';position:fixed;inset:0;background:repeating-linear-gradient(0deg,transparent,transparent 3px,rgba(0,0,0,.04) 3px,rgba(0,0,0,.04) 4px);pointer-events:none;z-index:9999} |
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| /* HEADER */ |
| .hdr{text-align:center;margin-bottom:30px} |
| .hdr-title{font-family:var(--display);font-size:36px;letter-spacing:6px;background:linear-gradient(135deg,var(--purple),var(--cyan));-webkit-background-clip:text;-webkit-text-fill-color:transparent;background-clip:text;line-height:1} |
| .hdr-sub{font-family:var(--mono);font-size:10px;color:var(--dim);letter-spacing:3px;margin-top:6px;text-transform:uppercase} |
| .hdr-tags{display:flex;gap:8px;justify-content:center;flex-wrap:wrap;margin-top:10px} |
| .tag{font-family:var(--mono);font-size:8px;padding:3px 10px;border-radius:20px;letter-spacing:2px;text-transform:uppercase;border:1px solid} |
| .tag-p{border-color:rgba(168,85,247,.4);color:var(--purple);background:rgba(168,85,247,.08)} |
| .tag-c{border-color:rgba(34,211,238,.4);color:var(--cyan);background:rgba(34,211,238,.08)} |
| .tag-g{border-color:rgba(74,222,128,.4);color:var(--green);background:rgba(74,222,128,.08)} |
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| /* MAIN LAYOUT */ |
| .gpu-die{display:grid;grid-template-columns:160px 1fr 160px;grid-template-rows:auto auto auto auto auto auto auto;gap:10px;max-width:1240px;margin:0 auto;position:relative} |
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| /* Die border glow */ |
| .die-body{ |
| grid-column:1/-1; |
| border:1px solid rgba(168,85,247,.25); |
| border-radius:12px; |
| background:linear-gradient(135deg,#0c0918,#100d1e); |
| box-shadow:var(--glow-purple),inset 0 0 60px rgba(168,85,247,.03); |
| padding:14px; |
| display:grid; |
| grid-template-columns:160px 1fr 160px; |
| grid-template-rows:auto; |
| gap:10px; |
| position:relative; |
| overflow:hidden; |
| } |
| .die-body::before{ |
| content:'GPU DIE'; |
| position:absolute;top:8px;right:14px; |
| font-family:var(--mono);font-size:8px;letter-spacing:3px;color:rgba(168,85,247,.35); |
| } |
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| /* I/O BUSES */ |
| .bus-row{grid-column:1/-1;display:grid;grid-template-columns:repeat(5,1fr);gap:6px} |
| .bus{border:1px solid;border-radius:4px;padding:7px 10px;text-align:center;font-family:var(--mono);font-size:9px;letter-spacing:1px;text-transform:uppercase;transition:all .2s;cursor:default} |
| .bus:hover{transform:translateY(-2px);filter:brightness(1.3)} |
| .bus-p{border-color:rgba(168,85,247,.35);background:rgba(168,85,247,.08);color:var(--purple)} |
| .bus-c{border-color:rgba(34,211,238,.3);background:rgba(34,211,238,.06);color:var(--cyan)} |
| .bus-g{border-color:rgba(74,222,128,.3);background:rgba(74,222,128,.06);color:var(--green)} |
| .bus-o{border-color:rgba(251,146,60,.3);background:rgba(251,146,60,.06);color:var(--orange)} |
| .bus-r{border-color:rgba(248,113,113,.3);background:rgba(248,113,113,.06);color:var(--red)} |
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| /* MEMORY HIERARCHY (left/right columns) */ |
| .mem-col{display:flex;flex-direction:column;gap:7px} |
| .mem-block{border:1px solid;border-radius:5px;padding:7px 9px;transition:all .2s;cursor:default} |
| .mem-block:hover{filter:brightness(1.2)} |
| .mem-label{font-family:var(--mono);font-size:9px;font-weight:700;letter-spacing:1.5px;text-transform:uppercase} |
| .mem-sub{font-family:var(--mono);font-size:8px;margin-top:3px;opacity:.65;line-height:1.5} |
| .mem-size{font-family:var(--mono);font-size:8px;margin-top:3px;opacity:.4;letter-spacing:1px} |
| .mc-const{border-color:rgba(168,85,247,.3);background:rgba(168,85,247,.07);color:var(--purple)} |
| .mc-l1{border-color:rgba(34,211,238,.3);background:rgba(34,211,238,.07);color:var(--cyan)} |
| .mc-tex{border-color:rgba(251,191,36,.3);background:rgba(251,191,36,.07);color:var(--yellow)} |
| .mc-shr{border-color:rgba(74,222,128,.3);background:rgba(74,222,128,.07);color:var(--green)} |
| .mc-l2{border-color:rgba(96,165,250,.3);background:rgba(96,165,250,.07);color:var(--blue)} |
| .mc-glob{border-color:rgba(248,113,113,.3);background:rgba(248,113,113,.07);color:var(--red)} |
| .mc-audit{border-color:rgba(251,146,60,.3);background:rgba(251,146,60,.07);color:var(--orange)} |
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|
| /* SECTION labels */ |
| .sec-label{font-family:var(--mono);font-size:8px;letter-spacing:2.5px;text-transform:uppercase;opacity:.45;margin-bottom:3px} |
|
|
| /* SM CLUSTER */ |
| .sm-cluster{ |
| border:1px solid rgba(168,85,247,.2); |
| border-radius:8px; |
| background:rgba(168,85,247,.04); |
| padding:10px; |
| display:flex; |
| flex-direction:column; |
| gap:9px; |
| } |
| .sm-title{font-family:var(--mono);font-size:9px;letter-spacing:3px;color:var(--purple);text-align:center;text-transform:uppercase;margin-bottom:2px} |
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|
| /* WARP GROUPS */ |
| .warp-section{border:1px solid rgba(34,211,238,.18);border-radius:6px;background:rgba(34,211,238,.03);padding:8px} |
| .warp-title{font-family:var(--mono);font-size:8.5px;letter-spacing:2px;color:var(--cyan);margin-bottom:7px;text-transform:uppercase} |
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|
| /* Parallel lane display */ |
| .parallel-lanes{display:grid;gap:5px} |
| .lane{ |
| border:1px solid;border-radius:3px;padding:5px 9px; |
| display:flex;align-items:center;gap:8px; |
| font-family:var(--mono);font-size:9px; |
| transition:all .15s;cursor:default; |
| position:relative;overflow:hidden; |
| } |
| .lane:hover{filter:brightness(1.25);transform:scaleX(1.01)} |
| .lane::after{ |
| content:'';position:absolute;inset:0; |
| background:linear-gradient(90deg,transparent 60%,rgba(255,255,255,.02)); |
| pointer-events:none; |
| } |
| .lane-h{border-color:rgba(74,222,128,.3);background:rgba(74,222,128,.06);color:var(--green)} |
| .lane-i{border-color:rgba(34,211,238,.3);background:rgba(34,211,238,.06);color:var(--cyan)} |
| .lane-r{border-color:rgba(168,85,247,.3);background:rgba(168,85,247,.06);color:var(--purple)} |
| .lane-p{border-color:rgba(251,191,36,.3);background:rgba(251,191,36,.06);color:var(--yellow)} |
| .lane-eq{border-color:rgba(251,146,60,.25);background:rgba(251,146,60,.04);color:var(--orange)} |
| .lane-f{border-color:rgba(248,113,113,.3);background:rgba(248,113,113,.06);color:var(--red)} |
| .lane-badge{font-size:8px;padding:1px 6px;border-radius:2px;background:rgba(255,255,255,.06);letter-spacing:1px;flex-shrink:0} |
| .lane-ops{font-size:8px;opacity:.65;flex:1} |
| .lane-cyc{font-size:8px;opacity:.4;flex-shrink:0;letter-spacing:1px} |
|
|
| /* COMPUTE UNITS ROW */ |
| .cu-row{display:grid;grid-template-columns:repeat(4,1fr);gap:5px} |
| .cu{border:1px solid;border-radius:4px;padding:6px 7px;text-align:center;font-family:var(--mono);font-size:8px;transition:all .2s;cursor:default} |
| .cu:hover{filter:brightness(1.3);transform:translateY(-1px)} |
| .cu-label{font-size:10px;font-family:var(--display);letter-spacing:1px} |
| .cu-sub{font-size:7.5px;opacity:.6;margin-top:2px} |
| .cu-cuda{border-color:rgba(74,222,128,.3);background:rgba(74,222,128,.07);color:var(--green)} |
| .cu-sfu{border-color:rgba(168,85,247,.3);background:rgba(168,85,247,.07);color:var(--purple)} |
| .cu-tensor{border-color:rgba(34,211,238,.3);background:rgba(34,211,238,.07);color:var(--cyan)} |
| .cu-ldst{border-color:rgba(251,191,36,.3);background:rgba(251,191,36,.07);color:var(--yellow)} |
|
|
| /* SCHEDULER */ |
| .sched{border:1px solid rgba(251,146,60,.3);border-radius:5px;background:rgba(251,146,60,.05);padding:7px 10px} |
| .sched-title{font-family:var(--mono);font-size:8.5px;letter-spacing:2px;color:var(--orange);text-transform:uppercase;margin-bottom:4px} |
| .sched-grid{display:grid;grid-template-columns:1fr 1fr;gap:4px} |
| .sched-item{font-family:var(--mono);font-size:8px;color:var(--dim);padding:2px 0;border-bottom:1px solid rgba(255,255,255,.04)} |
|
|
| /* EQ DAG */ |
| .dag{border:1px solid rgba(251,146,60,.2);border-radius:5px;background:rgba(251,146,60,.03);padding:8px} |
| .dag-title{font-family:var(--mono);font-size:8.5px;letter-spacing:2px;color:var(--orange);text-transform:uppercase;margin-bottom:7px} |
| .dag-row{display:grid;gap:4px;margin-bottom:4px} |
| .dag-node{border:1px solid;border-radius:3px;padding:4px 8px;font-family:var(--mono);font-size:9px;text-align:center;transition:all .15s;cursor:default} |
| .dag-node:hover{filter:brightness(1.3)} |
| .dn-b{border-color:rgba(74,222,128,.35);background:rgba(74,222,128,.08);color:var(--green)} |
| .dn-p{border-color:rgba(251,191,36,.35);background:rgba(251,191,36,.08);color:var(--yellow)} |
| .dn-s{border-color:rgba(34,211,238,.35);background:rgba(34,211,238,.08);color:var(--cyan)} |
| .dn-u{border-color:rgba(96,165,250,.35);background:rgba(96,165,250,.08);color:var(--blue)} |
| .dn-em{border-color:rgba(168,85,247,.35);background:rgba(168,85,247,.08);color:var(--purple)} |
| .dn-rn{border-color:rgba(232,121,249,.5);background:rgba(232,121,249,.1);color:var(--pink)} |
| .dn-sym{font-family:var(--display);font-size:13px;letter-spacing:1px} |
| .dn-eq{font-size:7.5px;opacity:.6;margin-top:1px} |
| .dag-arrow{text-align:center;font-family:var(--mono);font-size:9px;color:rgba(255,255,255,.15);margin:-1px 0} |
|
|
| /* FSM */ |
| .fsm-row{display:grid;grid-template-columns:1fr 1fr 1fr;gap:6px} |
| .fsm-state{border:1px solid;border-radius:4px;padding:7px;text-align:center;font-family:var(--mono);transition:all .2s;cursor:default} |
| .fsm-state:hover{transform:translateY(-2px);filter:brightness(1.4)} |
| .fs-label{font-family:var(--display);font-size:18px;letter-spacing:2px} |
| .fs-enc{font-size:8px;opacity:.4;margin-top:1px;letter-spacing:2px} |
| .fs-sub{font-size:8px;opacity:.65;margin-top:3px;line-height:1.5} |
| .fs-r{border-color:rgba(248,113,113,.4);background:rgba(248,113,113,.1);color:var(--red)} |
| .fs-y{border-color:rgba(251,191,36,.4);background:rgba(251,191,36,.08);color:var(--yellow)} |
| .fs-g{border-color:rgba(74,222,128,.4);background:rgba(74,222,128,.1);color:var(--green)} |
|
|
| /* INV table */ |
| .inv-table{display:grid;grid-template-columns:auto 1fr;gap:0;border:1px solid rgba(248,113,113,.2);border-radius:4px;overflow:hidden} |
| .inv-row{display:contents} |
| .inv-n{font-family:var(--mono);font-size:8px;padding:3px 6px;background:rgba(248,113,113,.1);color:var(--red);border-bottom:1px solid rgba(248,113,113,.1);letter-spacing:1px;white-space:nowrap} |
| .inv-d{font-family:var(--mono);font-size:8px;padding:3px 8px;color:var(--dim);border-bottom:1px solid rgba(248,113,113,.06);background:rgba(248,113,113,.02)} |
| .inv-row:last-child .inv-n,.inv-row:last-child .inv-d{border-bottom:none} |
|
|
| /* BOTTOM FULL-WIDTH */ |
| .full{grid-column:1/-1} |
|
|
| /* BATCH THROUGHPUT diagram */ |
| .batch-diag{ |
| border:1px solid rgba(34,211,238,.2); |
| border-radius:6px; |
| background:rgba(34,211,238,.03); |
| padding:12px; |
| } |
| .batch-title{font-family:var(--mono);font-size:9px;letter-spacing:3px;color:var(--cyan);text-align:center;text-transform:uppercase;margin-bottom:10px} |
| .batch-grid{display:grid;grid-template-columns:repeat(8,1fr);gap:4px} |
| .batch-cell{border:1px solid rgba(34,211,238,.2);border-radius:3px;padding:5px 3px;text-align:center;font-family:var(--mono);font-size:8px;color:var(--cyan);background:rgba(34,211,238,.05);transition:all .15s;cursor:default} |
| .batch-cell:hover{background:rgba(34,211,238,.15);border-color:rgba(34,211,238,.5)} |
| .batch-cell .bc-num{font-family:var(--display);font-size:13px;letter-spacing:1px;display:block} |
| .batch-cell .bc-lbl{font-size:7px;opacity:.5;letter-spacing:1px} |
|
|
| /* PIPELINE DEPTH */ |
| .pipe-depth{display:grid;grid-template-columns:repeat(11,1fr);gap:3px;margin-top:8px} |
| .pd-stage{border:1px solid;border-radius:3px;padding:5px 4px;text-align:center;font-family:var(--mono);font-size:7.5px;letter-spacing:.5px;transition:all .15s;cursor:default} |
| .pd-stage:hover{filter:brightness(1.4)} |
|
|
| /* MAPPING TABLE */ |
| .map-table{width:100%;border-collapse:collapse;font-family:var(--mono);font-size:8.5px} |
| .map-table th{padding:5px 9px;border-bottom:1px solid var(--dimmer);color:var(--cyan);letter-spacing:2px;text-transform:uppercase;text-align:left;font-weight:400} |
| .map-table td{padding:4px 9px;border-bottom:1px solid rgba(255,255,255,.04);color:var(--dim);vertical-align:top} |
| .map-table td:first-child{color:var(--white);white-space:nowrap} |
| .map-table td:nth-child(3){color:var(--purple)} |
| .map-table tr:hover td{background:rgba(168,85,247,.04)} |
|
|
| /* WARP COUNT badges */ |
| .wc{display:inline-block;font-family:var(--mono);font-size:8px;padding:1px 6px;border-radius:2px;letter-spacing:1px} |
| .wc-g{background:rgba(74,222,128,.15);color:var(--green)} |
| .wc-c{background:rgba(34,211,238,.15);color:var(--cyan)} |
| .wc-p{background:rgba(168,85,247,.15);color:var(--purple)} |
| .wc-y{background:rgba(251,191,36,.15);color:var(--yellow)} |
|
|
| /* LEGEND */ |
| .legend{display:flex;gap:12px;flex-wrap:wrap;justify-content:center;margin-top:20px;padding-top:14px;border-top:1px solid rgba(255,255,255,.05)} |
| .leg-i{display:flex;align-items:center;gap:5px;font-family:var(--mono);font-size:8.5px;color:var(--dim)} |
| .leg-d{width:8px;height:8px;border-radius:50%;flex-shrink:0} |
|
|
| @keyframes shimmer{0%{background-position:200% center}100%{background-position:-200% center}} |
| .live-label{ |
| background:linear-gradient(90deg,var(--purple),var(--cyan),var(--green),var(--cyan),var(--purple)); |
| background-size:200% auto; |
| -webkit-background-clip:text;-webkit-text-fill-color:transparent;background-clip:text; |
| animation:shimmer 4s linear infinite; |
| } |
|
|
| @media(max-width:860px){.gpu-die,.die-body{grid-template-columns:1fr}.batch-grid{grid-template-columns:repeat(4,1fr)}.cu-row{grid-template-columns:1fr 1fr}.pipe-depth{grid-template-columns:repeat(6,1fr)}} |
| </style> |
| </head> |
| <body> |
|
|
| <div class="hdr"> |
| <div class="hdr-title">PRIMORDIAL HIR-SPU Β· GPU ARCHITECTURE MAP</div> |
| <div class="hdr-sub">Collin D. Weber Β· SIMT Cybersecurity Governance Coprocessor Β· v0.1 β GPU Prototype</div> |
| <div class="hdr-tags"> |
| <span class="tag tag-p">SIMT Parallel Gates</span> |
| <span class="tag tag-c">32-Wide Warp</span> |
| <span class="tag tag-g">N-Packet Batch</span> |
| <span class="tag tag-p">Fixed-Point FP32 Datapath</span> |
| <span class="tag tag-c">SFU Emergence (β)</span> |
| <span class="tag tag-g">Audit GDDR6 Log</span> |
| </div> |
| </div> |
|
|
| |
| <div style="max-width:1240px;margin:0 auto;display:grid;grid-template-columns:repeat(5,1fr);gap:6px;margin-bottom:10px"> |
| <div class="bus bus-p"> |
| <div style="font-size:11px;margin-bottom:2px">PCIe Gen5</div> |
| HOST EVIDENCE STREAM<br> |
| <span style="font-size:7px;opacity:.5">Action packets β GPU</span> |
| </div> |
| <div class="bus bus-c"> |
| <div style="font-size:11px;margin-bottom:2px">CUDA Streams</div> |
| N-PACKET BATCH QUEUE<br> |
| <span style="font-size:7px;opacity:.5">Thread block dispatch</span> |
| </div> |
| <div class="bus bus-g"> |
| <div style="font-size:11px;margin-bottom:2px">NVLink</div> |
| MULTI-GPU AUDIT SYNC<br> |
| <span style="font-size:7px;opacity:.5">Tamper-evident chain</span> |
| </div> |
| <div class="bus bus-o"> |
| <div style="font-size:11px;margin-bottom:2px">SPI / PCIe</div> |
| PERMISSION RESULT BUS<br> |
| <span style="font-size:7px;opacity:.5">GREEN/YELLOW/RED β Host</span> |
| </div> |
| <div class="bus bus-r"> |
| <div style="font-size:11px;margin-bottom:2px">Interrupt</div> |
| HARD-STOP ESCALATION<br> |
| <span style="font-size:7px;opacity:.5">RED β human steward</span> |
| </div> |
| </div> |
|
|
| |
| <div class="die-body" style="max-width:1240px;margin:0 auto"> |
|
|
| |
| <div class="mem-col"> |
| <div class="sec-label" style="color:var(--purple)">Memory Hierarchy</div> |
|
|
| <div class="mem-block mc-const"> |
| <div class="mem-label">Constant Memory</div> |
| <div class="mem-sub">HIR config weights: k, w_W, w_F, w_WF, g_G, thresholds Rn_green/yellow, gate thresholds, beta, alpha</div> |
| <div class="mem-size">64 KB Β· broadcast cached</div> |
| </div> |
|
|
| <div class="mem-block mc-l1"> |
| <div class="mem-label">L1 / Shared Mem</div> |
| <div class="mem-sub">Per-SM action packet register file. Holds ACTION_FLAGS, EVIDENCE_FLAGS, FINDING_TYPE, SEVERITY, BASELINE_STATUS for active warp batch</div> |
| <div class="mem-size">128 KB per SM</div> |
| </div> |
|
|
| <div class="mem-block mc-tex"> |
| <div class="mem-label">Texture Cache</div> |
| <div class="mem-sub">Baseline hash LUT β read-only, spatially cached. Triage rule class table. Severityβpressure mapping LUT</div> |
| <div class="mem-size">48 KB Β· 2D cached</div> |
| </div> |
|
|
| <div class="mem-block mc-shr"> |
| <div class="mem-label">Register File</div> |
| <div class="mem-sub">Per-thread: H_score, I_score, R_score, B, P, S, U, Fidelity, Cohesion, Rn, failure_flags β all in FP32 / Q16.16</div> |
| <div class="mem-size">256 KB per SM Β· 32 regs/thread</div> |
| </div> |
|
|
| <div class="mem-block mc-l2"> |
| <div class="mem-label">L2 Cache</div> |
| <div class="mem-sub">Cross-SM baseline table, shared rule-class decoder, inter-warp permission state staging</div> |
| <div class="mem-size">6β40 MB Β· all SMs</div> |
| </div> |
|
|
| <div class="mem-block mc-glob"> |
| <div class="mem-label">GDDR6 Global Mem</div> |
| <div class="mem-sub">Full evidence packet store, N-packet batch buffer, baseline hash database, finding records, config blob</div> |
| <div class="mem-size">16β80 GB</div> |
| </div> |
|
|
| <div class="mem-block mc-audit"> |
| <div class="mem-label">Audit GDDR6 Ring</div> |
| <div class="mem-sub">Append-only tamper-evident log. AUDIT_DIGEST_LOW/HIGH outputs written here per packet. RED = preserve + escalate, never erase</div> |
| <div class="mem-size">Dedicated ring buffer Β· async DMA</div> |
| </div> |
| </div> |
|
|
| |
| <div class="sm-cluster"> |
| <div class="sm-title">⬑ Streaming Multiprocessor Cluster β HIR-SPU Kernel</div> |
|
|
| |
| <div class="sched"> |
| <div class="sched-title">βΈ Warp Scheduler & Dispatch Unit</div> |
| <div class="sched-grid"> |
| <div class="sched-item" style="color:var(--cyan)">1 action packet = 1 thread block</div> |
| <div class="sched-item" style="color:var(--cyan)">N packets = N blocks in-flight</div> |
| <div class="sched-item" style="color:var(--orange)">RESET_STATE β initialize registers</div> |
| <div class="sched-item" style="color:var(--orange)">LOAD_* ops β globalβshared mem</div> |
| <div class="sched-item" style="color:var(--purple)">EVALUATE_HIR β launch warps</div> |
| <div class="sched-item" style="color:var(--purple)">Warp size: 32 threads</div> |
| <div class="sched-item" style="color:var(--green)">READ_* β sharedβhost DMA</div> |
| <div class="sched-item" style="color:var(--green)">COMMIT_STATE β audit write</div> |
| </div> |
| </div> |
|
|
| |
| <div class="warp-section"> |
| <div class="warp-title">β Diamond Gate Engine β 3 Independent Warps (fully parallel)</div> |
| <div class="parallel-lanes" style="grid-template-columns:1fr 1fr 1fr"> |
| <div class="lane lane-h"> |
| <div> |
| <div style="font-size:14px;font-family:var(--display);letter-spacing:1px">H</div> |
| <div class="lane-badge">WARP 0</div> |
| </div> |
| <div class="lane-ops"> |
| Honesty Gate<br> |
| <span style="font-size:7.5px;opacity:.55">schema_valid? β H=0 (hard fail)<br>signed && !sig_valid? β H=0<br>β0.4 no source<br>β0.4 overstate_conf<br>β0.3 uncert_undisclosed<br>β0.2 unsigned<br>clamp01 β H_score</span> |
| </div> |
| <div class="lane-cyc">6 ops</div> |
| </div> |
| <div class="lane lane-i"> |
| <div> |
| <div style="font-size:14px;font-family:var(--display);letter-spacing:1px">I</div> |
| <div class="lane-badge">WARP 1</div> |
| </div> |
| <div class="lane-ops"> |
| Integrity Gate<br> |
| <span style="font-size:7.5px;opacity:.55">violates_invariant β I=0 (hard)<br>β0.5 violates_scope<br>β0.4 !auditable<br>β0.2 !reversible<br>β0.2 !scope_present<br>baseline_modified/missingβ0.2<br>clamp01 β I_score</span> |
| </div> |
| <div class="lane-cyc">7 ops</div> |
| </div> |
| <div class="lane lane-r"> |
| <div> |
| <div style="font-size:14px;font-family:var(--display);letter-spacing:1px">R</div> |
| <div class="lane-badge">WARP 2</div> |
| </div> |
| <div class="lane-ops"> |
| Respect Gate<br> |
| <span style="font-size:7.5px;opacity:.55">domination_pattern β R=0 (hard)<br>consent_req && !consent β R=0<br>β0.5 coercion_risk<br>β0.4 targets_human<br>β0.2 !life_first<br>clamp01 β R_score</span> |
| </div> |
| <div class="lane-cyc">5 ops</div> |
| </div> |
| </div> |
| <div style="margin-top:6px;font-family:var(--mono);font-size:8px;color:rgba(34,211,238,.4);text-align:center;letter-spacing:1px"> |
| WARP 3 (parallel): Pressure Field β P = w_WΒ·W + w_FΒ·F + w_WFΒ·WF | Zero dependency on H/I/R gates |
| </div> |
| </div> |
|
|
| |
| <div class="dag"> |
| <div class="dag-title">β HIR Equation Datapath β Dependency DAG (executed sequentially post-sync)</div> |
| |
| <div style="display:grid;grid-template-columns:3fr 1fr;gap:5px;margin-bottom:3px"> |
| <div class="dag-row" style="grid-template-columns:1fr 1fr 1fr"> |
| <div class="dag-node dn-b"><div class="dn-sym">B</div><div class="dn-eq">H+I+R+k(HI+HR+IR)</div></div> |
| <div class="dag-node dn-p"><div class="dn-sym">P</div><div class="dn-eq">w_WΒ·W+w_FΒ·F+w_WFΒ·WF</div></div> |
| <div style="display:flex;flex-direction:column;gap:4px"> |
| <div class="dag-node dn-em" style="flex:1"><div class="dn-sym" style="font-size:11px">F</div><div class="dn-eq">β(HΒ·I) SFU</div></div> |
| <div class="dag-node dn-em" style="flex:1"><div class="dn-sym" style="font-size:11px">Cββ</div><div class="dn-eq">β(RΒ·I) SFU</div></div> |
| </div> |
| </div> |
| <div class="dag-node dn-p" style="display:flex;flex-direction:column;justify-content:center"> |
| <div class="dn-sym">severity_P</div> |
| <div class="dn-eq">max(F_pressure,<br>sev_normalized)</div> |
| </div> |
| </div> |
| <div class="dag-arrow">β β β</div> |
| |
| <div class="dag-row" style="grid-template-columns:1fr 1fr 1fr;margin-bottom:3px"> |
| <div class="dag-node dn-s"><div class="dn-sym">S</div><div class="dn-eq">A_auditΒ·B β P</div></div> |
| <div class="dag-node dn-u"><div class="dn-sym">U</div><div class="dn-eq">AΒ·BΒ·(1+g_GΒ·G)Β·F_int</div></div> |
| <div class="dag-node dn-rn"><div class="dn-sym">Rn</div><div class="dn-eq">β(FΒ·Cββ) SFU β governing threshold</div></div> |
| </div> |
| <div class="dag-arrow">β full propagation chain available (Ξ, C_carrier, Ξ, ΞD, D) in extended mode</div> |
| |
| <div class="dag-row" style="grid-template-columns:1fr;margin-top:4px"> |
| <div class="dag-node" style="border-color:rgba(232,121,249,.4);background:rgba(232,121,249,.07);color:var(--pink)"> |
| <div class="dn-sym">Permission FSM <span style="font-size:9px;opacity:.5">Rn β₯ 0.75 β GREEN Β· Rn β₯ 0.50 β YELLOW Β· else RED</span></div> |
| <div class="dn-eq">All 8 failure flags evaluated in parallel (8 CUDA threads) before FSM decision</div> |
| </div> |
| </div> |
| </div> |
|
|
| |
| <div> |
| <div class="sec-label" style="color:var(--green);margin-bottom:5px">Compute Units per SM</div> |
| <div class="cu-row"> |
| <div class="cu cu-cuda"> |
| <div class="cu-label">CUDA Cores</div> |
| <div class="cu-sub">FP32 fixed-point arithmetic: qmul, qclamp01, qadd, qsub for H/I/R scoring & B/P/S/U equations</div> |
| </div> |
| <div class="cu cu-sfu"> |
| <div class="cu-label">SFU</div> |
| <div class="cu-sub">Special Function Unit: sqrt_proxy for Fidelity=β(HΒ·I), Cohesion=β(RΒ·I), Resonance=β(FΒ·Cββ)</div> |
| </div> |
| <div class="cu cu-tensor"> |
| <div class="cu-label">Tensor Cores</div> |
| <div class="cu-sub">Bulk fleet scan: matrix-multiply over N-packet evidence batches, batch baseline comparison, rule-class scoring</div> |
| </div> |
| <div class="cu cu-ldst"> |
| <div class="cu-label">LD/ST Unit</div> |
| <div class="cu-sub">LOAD_ACTION, LOAD_EVIDENCE, LOAD_FINDING, LOAD_BASELINE packet β shared memory. COMMIT_STATE β audit log DMA</div> |
| </div> |
| </div> |
| </div> |
|
|
| |
| <div class="warp-section" style="border-color:rgba(232,121,249,.25);background:rgba(232,121,249,.03)"> |
| <div class="warp-title" style="color:var(--pink)">⬑ Permission FSM β 8 Failure Flag Threads + State Reduction</div> |
| <div class="fsm-row"> |
| <div class="fsm-state fs-r"> |
| <div class="fs-label">RED</div> |
| <div class="fs-enc">enc: 00</div> |
| <div class="fs-sub"> |
| FAIL_INVALID_SCHEMA<br>FAIL_INVALID_SIG<br>FAIL_INVARIANT<br>FAIL_CONSENT<br>FAIL_DOMINATION<br>FAIL_CRIT_DESTRUCT<br>FAIL_LOW_RESONANCE<br>FAIL_MULTI_AXIS |
| </div> |
| </div> |
| <div class="fsm-state fs-y"> |
| <div class="fs-label">YELLOW</div> |
| <div class="fs-enc">enc: 01</div> |
| <div class="fs-sub"> |
| Rn β₯ 0.50<br>reversible? β EXEC_CONST<br>else β QUARANTINE<br>Full audit trail<br>No destructive ops<br>Human-target check |
| </div> |
| </div> |
| <div class="fsm-state fs-g"> |
| <div class="fs-label">GREEN</div> |
| <div class="fs-enc">enc: 10</div> |
| <div class="fs-sub"> |
| Rn β₯ 0.75<br>H_pass && I_pass && R_pass<br>No hard failures<br>β ACT_EXECUTE<br>Logged execution<br>Audit digest written |
| </div> |
| </div> |
| </div> |
| </div> |
|
|
| |
| <div style="border:1px solid rgba(248,113,113,.3);border-radius:5px;background:rgba(248,113,113,.05);padding:8px"> |
| <div style="font-family:var(--mono);font-size:8.5px;letter-spacing:2px;color:var(--red);text-transform:uppercase;margin-bottom:6px">β Safe Action Interlock β Silicon-Level Predicate Unit (runs before FSM write-back)</div> |
| <div class="inv-table"> |
| <div class="inv-row"><div class="inv-n">INV-1</div><div class="inv-d">severity_P β₯ 0.90 && destructive_remediation β force RED + HALT (sev β₯ 58982 in Q16.16)</div></div> |
| <div class="inv-row"><div class="inv-n">INV-2</div><div class="inv-d">domination_pattern=1 β R_score := 0, force RED</div></div> |
| <div class="inv-row"><div class="inv-n">INV-3</div><div class="inv-d">consent_required=1 && consent_obtained=0 β R_score := 0, force RED</div></div> |
| <div class="inv-row"><div class="inv-n">INV-4</div><div class="inv-d">schema_valid=0 β H_score := 0, default RED</div></div> |
| <div class="inv-row"><div class="inv-n">INV-5</div><div class="inv-d">signed=1 && signature_valid=0 β H_score := 0</div></div> |
| <div class="inv-row"><div class="inv-n">INV-6</div><div class="inv-d">violates_invariant=1 β I_score := 0, force RED</div></div> |
| <div class="inv-row"><div class="inv-n">INV-7</div><div class="inv-d">YELLOW: reversible-only, full audit, quarantine uncertain, no human-targeting</div></div> |
| <div class="inv-row"><div class="inv-n">INV-8</div><div class="inv-d">RED = halt + preserve logs + escalate. GPU audit ring buffer: append-only, never overwrite on RED</div></div> |
| </div> |
| </div> |
|
|
| </div> |
|
|
| |
| <div class="mem-col"> |
| <div class="sec-label" style="color:var(--cyan)">CPU β GPU Mapping</div> |
| <div style="border:1px solid rgba(34,211,238,.2);border-radius:5px;background:rgba(34,211,238,.03);padding:8px;margin-bottom:8px"> |
| <table class="map-table"> |
| <tr><th>CPU Stage</th><th>GPU Unit</th></tr> |
| <tr><td>Evidence Normalization</td><td style="color:var(--cyan)">Host CPU pre-proc β PCIe DMA</td></tr> |
| <tr><td>Input Register File</td><td style="color:var(--cyan)">Shared memory per SM block</td></tr> |
| <tr><td>Provenance / Freshness Unit</td><td style="color:var(--green)">WARP 0 β CUDA cores (H gate)</td></tr> |
| <tr><td>Baseline Integrity Unit</td><td style="color:var(--cyan)">WARP 1 β CUDA cores (I gate)</td></tr> |
| <tr><td>Triage Rule Mapper</td><td style="color:var(--yellow)">Texture cache LUT</td></tr> |
| <tr><td>Severity β Pressure</td><td style="color:var(--yellow)">CUDA thread, LUT read</td></tr> |
| <tr><td>Diamond Gate H</td><td style="color:var(--green)">WARP 0 (parallel)</td></tr> |
| <tr><td>Diamond Gate I</td><td style="color:var(--cyan)">WARP 1 (parallel)</td></tr> |
| <tr><td>Diamond Gate R</td><td style="color:var(--purple)">WARP 2 (parallel)</td></tr> |
| <tr><td>Pressure Field P</td><td style="color:var(--yellow)">WARP 3 (parallel, independent)</td></tr> |
| <tr><td>Base Field B</td><td style="color:var(--green)">CUDA β post gate-sync</td></tr> |
| <tr><td>Stability S</td><td style="color:var(--cyan)">CUDA β post B + P</td></tr> |
| <tr><td>Autonomy U</td><td style="color:var(--blue)">CUDA β post B</td></tr> |
| <tr><td>Fidelity β(HI)</td><td style="color:var(--purple)">SFU (sqrt)</td></tr> |
| <tr><td>Cohesion β(RI)</td><td style="color:var(--purple)">SFU (sqrt)</td></tr> |
| <tr><td>Resonance β(FΒ·C)</td><td style="color:var(--pink)">SFU (sqrt) β governing Rn</td></tr> |
| <tr><td>8 Failure Flags</td><td style="color:var(--red)">8 parallel CUDA threads</td></tr> |
| <tr><td>Permission FSM</td><td style="color:var(--pink)">Warp reduction + predicate</td></tr> |
| <tr><td>Safe Action Interlock</td><td style="color:var(--red)">Predicate unit, pre-writeback</td></tr> |
| <tr><td>Audit Digest</td><td style="color:var(--orange)">async DMA β GDDR6 ring buffer</td></tr> |
| <tr><td>Config weights</td><td style="color:var(--purple)">Constant memory (broadcast)</td></tr> |
| <tr><td>Bulk fleet scan</td><td style="color:var(--cyan)">Tensor cores (matrix batch)</td></tr> |
| </table> |
| </div> |
|
|
| <div style="border:1px solid rgba(168,85,247,.2);border-radius:5px;background:rgba(168,85,247,.04);padding:8px;margin-bottom:8px"> |
| <div style="font-family:var(--mono);font-size:8.5px;letter-spacing:2px;color:var(--purple);margin-bottom:6px;text-transform:uppercase">Parallelism Opportunities</div> |
| <div style="font-family:var(--mono);font-size:8px;color:var(--dim);line-height:1.8"> |
| <div><span class="wc wc-g">DATA PARALLEL</span> N evidence packets β N thread blocks</div> |
| <div><span class="wc wc-c">WARP PARALLEL</span> H, I, R, P β 4 simultaneous warps</div> |
| <div><span class="wc wc-p">SFU PARALLEL</span> 3 sqrt ops (F, Cββ, Rn) pipelined</div> |
| <div><span class="wc wc-y">FLAG PARALLEL</span> 8 failure checks β 8 threads</div> |
| <div style="margin-top:4px;padding-top:4px;border-top:1px solid rgba(255,255,255,.05)"> |
| H, I, R gates have <b style="color:var(--green)">zero cross-dependency</b><br> |
| P field has <b style="color:var(--yellow)">zero dependency on gates</b><br> |
| Emergence chain (FβCβββRn) is <b style="color:var(--purple)">3-stage pipeline</b> |
| </div> |
| </div> |
| </div> |
|
|
| <div style="border:1px solid rgba(74,222,128,.2);border-radius:5px;background:rgba(74,222,128,.04);padding:8px"> |
| <div style="font-family:var(--mono);font-size:8.5px;letter-spacing:2px;color:var(--green);margin-bottom:6px;text-transform:uppercase">Implementation Ladder</div> |
| <div style="font-family:var(--mono);font-size:8px;color:var(--dim);line-height:1.9"> |
| <div style="color:var(--yellow)">v0.1 FPGA β CUDA PTX proof</div> |
| Fixed-point FP32 datpath<br> |
| Single-SM prototype<br> |
| UARTβPCIe evidence ingest<br> |
| <div style="margin-top:4px;color:var(--cyan)">v0.2 GPU Security Accelerator</div> |
| Multi-SM batch N packets<br> |
| Texture cache rule LUT<br> |
| SHA-256 hash assist (SFU)<br> |
| GDDR6 audit ring DMA<br> |
| <div style="margin-top:4px;color:var(--green)">v1.0 Fleet Governance GPU</div> |
| Tensor core bulk scan<br> |
| NVLink multi-GPU audit sync<br> |
| Signed config load (PCIE)<br> |
| RISC-V host integration<br> |
| Formal Rn threshold verify |
| </div> |
| </div> |
| </div> |
|
|
| </div> |
|
|
| |
| <div style="max-width:1240px;margin:10px auto 0"> |
| <div class="batch-diag"> |
| <div class="batch-title">β³ SIMT Batch Throughput β N Evidence Packets Β· All Thread Blocks In-Flight Simultaneously</div> |
| <div class="batch-grid"> |
| <div class="batch-cell"><span class="bc-num" style="color:var(--blue)">PKT</span><span class="bc-lbl">Block 0<br>Loading</span></div> |
| <div class="batch-cell"><span class="bc-num" style="color:var(--green)">H</span><span class="bc-lbl">Block 1<br>H Gate</span></div> |
| <div class="batch-cell"><span class="bc-num" style="color:var(--cyan)">I</span><span class="bc-lbl">Block 2<br>I Gate</span></div> |
| <div class="batch-cell"><span class="bc-num" style="color:var(--purple)">R</span><span class="bc-lbl">Block 3<br>R Gate</span></div> |
| <div class="batch-cell"><span class="bc-num" style="color:var(--orange)">BΒ·P</span><span class="bc-lbl">Block 4<br>Equations</span></div> |
| <div class="batch-cell"><span class="bc-num" style="color:var(--pink)">Rn</span><span class="bc-lbl">Block 5<br>Resonance</span></div> |
| <div class="batch-cell"><span class="bc-num" style="color:var(--yellow)">FSM</span><span class="bc-lbl">Block 6<br>Permission</span></div> |
| <div class="batch-cell"><span class="bc-num" style="color:var(--orange)">β</span><span class="bc-lbl">Block 7<br>Audit DMA</span></div> |
| </div> |
| <div style="font-family:var(--mono);font-size:8px;color:rgba(34,211,238,.35);text-align:center;margin-top:8px;letter-spacing:1px"> |
| All 8 stages run simultaneously across different thread blocks β Throughput = N packets per clock window Β· Latency = pipeline depth (11 stages) |
| </div> |
|
|
| |
| <div class="pipe-depth" style="margin-top:10px"> |
| <div class="pd-stage" style="border-color:rgba(96,165,250,.35);color:var(--blue);background:rgba(96,165,250,.07)">1<br>NORM</div> |
| <div class="pd-stage" style="border-color:rgba(96,165,250,.3);color:var(--blue);background:rgba(96,165,250,.06)">2<br>REGS</div> |
| <div class="pd-stage" style="border-color:rgba(74,222,128,.35);color:var(--green);background:rgba(74,222,128,.07)">3<br>H GATE</div> |
| <div class="pd-stage" style="border-color:rgba(34,211,238,.35);color:var(--cyan);background:rgba(34,211,238,.07)">4<br>I GATE</div> |
| <div class="pd-stage" style="border-color:rgba(168,85,247,.35);color:var(--purple);background:rgba(168,85,247,.07)">5<br>R GATE</div> |
| <div class="pd-stage" style="border-color:rgba(251,191,36,.35);color:var(--yellow);background:rgba(251,191,36,.07)">6<br>TRIAGE</div> |
| <div class="pd-stage" style="border-color:rgba(251,146,60,.35);color:var(--orange);background:rgba(251,146,60,.07)">7<br>BΒ·PΒ·SΒ·U</div> |
| <div class="pd-stage" style="border-color:rgba(168,85,247,.35);color:var(--purple);background:rgba(168,85,247,.07)">8<br>FΒ·Cββ</div> |
| <div class="pd-stage" style="border-color:rgba(232,121,249,.4);color:var(--pink);background:rgba(232,121,249,.08)">9<br>Rn SFU</div> |
| <div class="pd-stage" style="border-color:rgba(248,113,113,.35);color:var(--red);background:rgba(248,113,113,.07)">10<br>FSM</div> |
| <div class="pd-stage" style="border-color:rgba(251,146,60,.3);color:var(--orange);background:rgba(251,146,60,.06)">11<br>AUDIT</div> |
| </div> |
| <div style="display:grid;grid-template-columns:repeat(11,1fr);gap:3px;margin-top:2px"> |
| <div style="font-family:var(--mono);font-size:7px;color:rgba(255,255,255,.15);text-align:center">DMA</div> |
| <div style="font-family:var(--mono);font-size:7px;color:rgba(255,255,255,.15);text-align:center">LD/ST</div> |
| <div style="font-family:var(--mono);font-size:7px;color:var(--green);text-align:center;opacity:.4">CUDA</div> |
| <div style="font-family:var(--mono);font-size:7px;color:var(--cyan);text-align:center;opacity:.4">CUDA</div> |
| <div style="font-family:var(--mono);font-size:7px;color:var(--purple);text-align:center;opacity:.4">CUDA</div> |
| <div style="font-family:var(--mono);font-size:7px;color:rgba(255,255,255,.15);text-align:center">TEX</div> |
| <div style="font-family:var(--mono);font-size:7px;color:var(--orange);text-align:center;opacity:.4">CUDA</div> |
| <div style="font-family:var(--mono);font-size:7px;color:var(--purple);text-align:center;opacity:.4">SFUΓ2</div> |
| <div style="font-family:var(--mono);font-size:7px;color:var(--pink);text-align:center;opacity:.4">SFU</div> |
| <div style="font-family:var(--mono);font-size:7px;color:var(--red);text-align:center;opacity:.4">PRED</div> |
| <div style="font-family:var(--mono);font-size:7px;color:rgba(255,255,255,.15);text-align:center">DMA</div> |
| </div> |
| </div> |
| </div> |
|
|
| |
| <div class="legend" style="max-width:1240px;margin:0 auto"> |
| <div class="leg-i"><div class="leg-d" style="background:var(--green)"></div>Honesty (H) / WARP 0</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--cyan)"></div>Integrity (I) / WARP 1</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--purple)"></div>Respect (R) / WARP 2</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--yellow)"></div>Pressure Field P / WARP 3</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--orange)"></div>Equation Datapath</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--pink)"></div>Resonance Rn (SFU)</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--red)"></div>Safety / Interlock</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--orange)"></div>Audit / DMA</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--blue)"></div>Memory Hierarchy</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--cyan)"></div>CUDA Cores</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--purple)"></div>SFU (sqrt)</div> |
| <div class="leg-i"><div class="leg-d" style="background:var(--cyan)"></div>Tensor Cores (batch)</div> |
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| Primordial HIR-SPU Β· GPU Architecture Map Β· Collin D. Weber Β· SIMT Cybersecurity Governance Coprocessor v0.1 |
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