Memory Hierarchy
Constant Memory
HIR config weights: k, w_W, w_F, w_WF, g_G, thresholds Rn_green/yellow, gate thresholds, beta, alpha
64 KB · broadcast cached
L1 / Shared Mem
Per-SM action packet register file. Holds ACTION_FLAGS, EVIDENCE_FLAGS, FINDING_TYPE, SEVERITY, BASELINE_STATUS for active warp batch
128 KB per SM
Texture Cache
Baseline hash LUT — read-only, spatially cached. Triage rule class table. Severity→pressure mapping LUT
48 KB · 2D cached
Register File
Per-thread: H_score, I_score, R_score, B, P, S, U, Fidelity, Cohesion, Rn, failure_flags — all in FP32 / Q16.16
256 KB per SM · 32 regs/thread
L2 Cache
Cross-SM baseline table, shared rule-class decoder, inter-warp permission state staging
6–40 MB · all SMs
GDDR6 Global Mem
Full evidence packet store, N-packet batch buffer, baseline hash database, finding records, config blob
16–80 GB
Audit GDDR6 Ring
Append-only tamper-evident log. AUDIT_DIGEST_LOW/HIGH outputs written here per packet. RED = preserve + escalate, never erase
Dedicated ring buffer · async DMA
⬡ Streaming Multiprocessor Cluster — HIR-SPU Kernel
▸ Warp Scheduler & Dispatch Unit
1 action packet = 1 thread block
N packets = N blocks in-flight
RESET_STATE → initialize registers
LOAD_* ops → global→shared mem
EVALUATE_HIR → launch warps
Warp size: 32 threads
READ_* → shared→host DMA
COMMIT_STATE → audit write
◆ Diamond Gate Engine — 3 Independent Warps (fully parallel)
Honesty Gate
schema_valid? → H=0 (hard fail)
signed && !sig_valid? → H=0
−0.4 no source
−0.4 overstate_conf
−0.3 uncert_undisclosed
−0.2 unsigned
clamp01 → H_score
6 ops
Integrity Gate
violates_invariant → I=0 (hard)
−0.5 violates_scope
−0.4 !auditable
−0.2 !reversible
−0.2 !scope_present
baseline_modified/missing−0.2
clamp01 → I_score
7 ops
Respect Gate
domination_pattern → R=0 (hard)
consent_req && !consent → R=0
−0.5 coercion_risk
−0.4 targets_human
−0.2 !life_first
clamp01 → R_score
5 ops
WARP 3 (parallel): Pressure Field — P = w_W·W + w_F·F + w_WF·WF | Zero dependency on H/I/R gates
∑ HIR Equation Datapath — Dependency DAG (executed sequentially post-sync)
severity_P
max(F_pressure,
sev_normalized)
↓ ↓ ↓
Rn
√(F·Cₑₘ) SFU — governing threshold
↓ full propagation chain available (Ξ, C_carrier, Θ, ΔD, D) in extended mode
Permission FSM Rn ≥ 0.75 → GREEN · Rn ≥ 0.50 → YELLOW · else RED
All 8 failure flags evaluated in parallel (8 CUDA threads) before FSM decision
Compute Units per SM
CUDA Cores
FP32 fixed-point arithmetic: qmul, qclamp01, qadd, qsub for H/I/R scoring & B/P/S/U equations
SFU
Special Function Unit: sqrt_proxy for Fidelity=√(H·I), Cohesion=√(R·I), Resonance=√(F·Cₑₘ)
Tensor Cores
Bulk fleet scan: matrix-multiply over N-packet evidence batches, batch baseline comparison, rule-class scoring
LD/ST Unit
LOAD_ACTION, LOAD_EVIDENCE, LOAD_FINDING, LOAD_BASELINE packet → shared memory. COMMIT_STATE → audit log DMA
⬡ Permission FSM — 8 Failure Flag Threads + State Reduction
RED
enc: 00
FAIL_INVALID_SCHEMA
FAIL_INVALID_SIG
FAIL_INVARIANT
FAIL_CONSENT
FAIL_DOMINATION
FAIL_CRIT_DESTRUCT
FAIL_LOW_RESONANCE
FAIL_MULTI_AXIS
YELLOW
enc: 01
Rn ≥ 0.50
reversible? → EXEC_CONST
else → QUARANTINE
Full audit trail
No destructive ops
Human-target check
GREEN
enc: 10
Rn ≥ 0.75
H_pass && I_pass && R_pass
No hard failures
→ ACT_EXECUTE
Logged execution
Audit digest written
⚑ Safe Action Interlock — Silicon-Level Predicate Unit (runs before FSM write-back)
INV-1
severity_P ≥ 0.90 && destructive_remediation → force RED + HALT (sev ≥ 58982 in Q16.16)
INV-2
domination_pattern=1 → R_score := 0, force RED
INV-3
consent_required=1 && consent_obtained=0 → R_score := 0, force RED
INV-4
schema_valid=0 → H_score := 0, default RED
INV-5
signed=1 && signature_valid=0 → H_score := 0
INV-6
violates_invariant=1 → I_score := 0, force RED
INV-7
YELLOW: reversible-only, full audit, quarantine uncertain, no human-targeting
INV-8
RED = halt + preserve logs + escalate. GPU audit ring buffer: append-only, never overwrite on RED