PEBench: A Fictitious Dataset to Benchmark Machine Unlearning for Multimodal Large Language Models Paper • 2503.12545 • Published Mar 16, 2025 • 7
CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization Paper • 2407.10424 • Published Jul 15, 2024 • 12
VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification Paper • 2505.20302 • Published May 16, 2025 • 1
VerilogEval: Evaluating Large Language Models for Verilog Code Generation Paper • 2309.07544 • Published Sep 14, 2023 • 2
Pitch-Aware RNN-T for Mandarin Chinese Mispronunciation Detection and Diagnosis Paper • 2406.04595 • Published Jun 7, 2024 • 1