tiny-gpu/arch.md

Artifact What it is Made by

1 README.md Design intent — architecture, ISA, thread model Human (author) 2 src/.sv SystemVerilog RTL — the actual design Human (author) 3 build/rtl_v/.v Plain Verilog, same design sv2v 4 docs/schematics/.svg RTL schematics — adders, muxes, registers yosys + netlistsvg 5 (not kept) Gate-level netlist — mapped to sky130 cells yosys synthesis 6 gds//gpu.gds Physical layout — polygons on 17 mask layers OpenLane place & route 7 3D view in browser glTF/GLB mesh, layers extruded to real heights GDS2glTF (in the web viewer) Side branch off #3, for testing rather than building:

Artifact What it is Made by

3a build/sim.vvp Compiled simulation binary iverilog 3b test/ results Kernel tests (matadd, matmul) run against the sim cocotb