Chip Design Toolchain — Bottom-Up
|
|
| Scope |
Tools needed to design the AURA-1 NPU from architecture to silicon, mapped to the L1→L3 ladder in feasibility-solo-build.md |
| Principle |
Open-source column is sufficient through L2 (FPGA) and a 130 nm L3 tapeout. Commercial column becomes mandatory only at 65/28 nm and below — typically via university licensing. |
The flow, bottom-up
1. Workload analysis → what to build
2. Architecture modeling → how it should work (cycle-approximate, no RTL)
3. RTL design → the actual hardware description
4. Verification → proving the RTL correct (largest single effort)
5. FPGA prototyping → running it in the real headphone (L2)
6. Synthesis → RTL → gate netlist
7. Place & route → netlist → layout (GDSII)
8. Signoff → timing/power/physical checks before tape-out
9. DFT → scan, MBIST for production test
10. Compiler/SDK → the parallel software track (70% of total effort)
Stage-by-stage tools
1–2. Workload analysis & architecture modeling
| Need |
Open / free |
Commercial |
| Model inspection, layer inventory |
Python + ONNX / onnxruntime, PyTorch, Netron |
— |
| Roofline & energy spreadsheets |
Python (numpy, matplotlib), Jupyter |
— |
| Cycle-approximate simulator |
Hand-written Python/C++ (a few hundred lines); optionally gem5 for CPU-side |
MATLAB/Simulink (unnecessary) |
| Accelerator design-space exploration |
Timeloop + Accelergy (MIT/NVIDIA), ZigZag (KU Leuven) — model MAC arrays + memory hierarchies analytically |
— |
3. RTL design
| Need |
Open / free |
Commercial |
| HDL |
SystemVerilog or Verilog (any editor) |
same |
| Generator-based alternative |
Chisel (Scala), Amaranth (Python), SpinalHDL — good for parameterized MAC arrays |
— |
| Reusable SoC scaffold |
PULP platform (RISC-V cores, AXI/OBI interconnect, DMA, peripherals) — the base GAP9 grew from |
Arm/Cadence/Synopsys IP catalogs |
| Lint / CDC checks |
Verilator --lint-only, Verible (style/lint) |
Spyglass (Synopsys) — the industry CDC signoff |
4. Verification (the biggest line item)
| Need |
Open / free |
Commercial |
| Simulator |
Verilator (compiled, fast, 2-state) + Icarus for quick 4-state checks |
VCS (Synopsys), Xcelium (Cadence), Questa (Siemens) |
| Testbench framework |
cocotb — Python testbenches; golden model = the same Python used in stage 2 |
UVM on a commercial simulator |
| Reference checking |
ONNX Runtime / PyTorch as bit-exact integer golden model |
— |
| Coverage |
Verilator functional + line coverage |
Commercial simulators' merged coverage + vManager/VCS coverage flows |
| Formal (optional but high-value for the mute latch / arbiter class of blocks) |
SymbiYosys + Yosys-smtbmc |
JasperGold (Cadence), VC Formal (Synopsys) |
| Waveforms |
GTKWave / Surfer |
Verdi (Synopsys) |
5. FPGA prototyping (L2)
| Need |
Open / free |
Commercial |
| Lattice ECP5 flow |
Yosys + nextpnr + prjtrellis — fully open RTL→bitstream |
Lattice Diamond |
| Efinix Ti60 flow |
— |
Efinity (free license, closed tool) |
| Larger prototypes |
— |
AMD Vivado (free tier covers Artix/Zynq) |
| On-target debug |
litex-server/JTAG, custom UART/USB monitors |
ChipScope/Reveal analyzers |
6. Synthesis (ASIC)
| Need |
Open / free |
Commercial |
| Logic synthesis |
Yosys (+ ABC) — production-proven at 130 nm, usable at 65 nm |
Design Compiler / Fusion Compiler (Synopsys), Genus (Cadence) |
| Timing constraints |
SDC (text) |
same |
7. Place & route
| Need |
Open / free |
Commercial |
| Full RTL→GDSII flow |
OpenROAD engine, driven via LibreLane (successor of OpenLane) — supports SKY130, GF180, IHP SG13G2 |
Innovus (Cadence), Fusion Compiler (Synopsys) |
| Custom/analog layout (SRAM macros, IO ring edits) |
Magic, KLayout, xschem + ngspice |
Virtuoso (Cadence) |
| SRAM compiler |
OpenRAM (SKY130); foundry-compiled macros elsewhere |
Arm/foundry memory compilers |
LibreLane vs OpenLane — which one to install
Three names appear in the wild; they are one lineage, not competitors.
| Name |
Status |
Notes |
| OpenLane (1.x) |
Legacy |
Original Tcl-based flow from Efabless. Most existing SKY130 tapeouts — including the tiny-gpu GDS in this repo — came out of this era |
| OpenLane 2 |
Superseded |
Python rewrite, still by Efabless |
| LibreLane |
✅ Current — use this |
Successor to OpenLane 2. Name and logo are FOSSi Foundation trademarks; codebase is "based on OpenLane 2 by Efabless Corporation (assets owned by UmbraLogic Technologies LLC)", Apache 2.0. Efabless wound down in 2025 and the project moved to neutral foundation governance |
Ships a Migrating from OpenLane guide including variable-migration tables, so existing
OpenLane configs are portable. Both drive the same OpenROAD engine underneath — the
change is stewardship and packaging, not a different place-and-route algorithm.
Install on macOS (docs list macOS 15+ as supported; this machine is 15.6):
| Method |
Platforms |
Verdict on Apple Silicon |
| Nix |
Windows 10+, macOS 15+, Linux |
✅ Preferred — native ARM binaries |
| Docker |
Windows, macOS 15+, Ubuntu 22.04+ |
⚠️ Avoid — images are typically amd64, so they run emulated and the flow slows by several × |
| AppImage |
Windows, Linux |
❌ Not macOS |
Known risk: if the Nix binary cache lacks aarch64-darwin coverage, Nix falls back to
building OpenROAD and friends from source — hours, not minutes. Visible within the first
minutes of install (Nix prints whether it is fetching or building).
Expected runtime, for a tiny-gpu-scale design (~8.6k logic cells, SKY130) on an M4:
|
Time |
Bound by |
| One-time toolchain setup |
30–60 min |
Download (~5–10 GB) |
| Full RTL→GDSII run |
20–45 min |
Single-core CPU |
No GPU is used, and RAM is not the constraint — the open EDA stack is entirely CPU, and
the work (maze routing, analytical placement, timing graph traversal) is irregular and
largely serial. Measured on this machine: Yosys synthesis of tiny-gpu peaked at 352 MB;
a full P&R on a design this size lands in the 1–4 GB range. Fast single-thread performance
matters; the 24 GB of RAM sits mostly idle. Parts of OpenROAD's global/detailed routing are
threaded, so extra cores help modestly.
8. Signoff
| Need |
Open / free |
Commercial |
| Static timing |
OpenSTA |
PrimeTime (Synopsys), Tempus (Cadence) — mandatory at advanced nodes |
| DRC / LVS |
Magic + Netgen (SKY130/GF180); KLayout DRC decks (IHP) |
Calibre (Siemens) — the industry standard, required by most foundries below 65 nm |
| Parasitic extraction |
OpenRCX |
StarRC (Synopsys), Quantus (Cadence) |
| Power analysis |
OpenSTA power reports + switching-activity (VCD/SAIF) from Verilator |
PrimePower (Synopsys), Voltus (Cadence) |
| IR drop / EM |
— (gap in open flow) |
Voltus, RedHawk (Ansys) |
9. DFT
| Need |
Open / free |
Commercial |
| Scan insertion |
Yosys can stitch basic scan; LibreLane has partial support |
DFT Compiler/TestMAX (Synopsys), Modus (Cadence), Tessent (Siemens) |
| MBIST |
Hand-rolled or PULP MBIST wrappers |
Tessent MBIST |
| ATPG |
— (real gap) |
TestMAX ATPG, Tessent FastScan |
10. Compiler / SDK (parallel software track — start at stage 2)
| Need |
Open / free |
| Quantization |
PyTorch AO / FX graph quantization, ONNX quantizer; esp32-ai's src/quantize.py as a worked example |
| Graph compiler skeleton |
TVM (heavyweight) or hand-rolled ONNX-walker emitting layer descriptors (recommended at this scale) |
| ISA simulator for the NPU |
The stage-2 Python model, kept in lockstep with RTL |
| Runtime |
C library on the host MCU (Zephyr module) |
Board level (L0 / EVB) — separate from the chip flow
| Need |
Tool |
Note |
| Schematic + PCB for the L0 prototype and later EVB |
EasyEDA Pro ✅ installed |
Integrated LCSC parts library + JLCPCB fab/assembly — fastest route from schematic to an assembled 4-layer board for the nRF5340/nRF7002 + mic array + amp build |
| Alternative |
KiCad 9 |
Open-source, better for boards that must outlive one vendor's ecosystem |
| Board bring-up |
Nordic PPK2 (power), Saleae/sigrok logic analyzer |
PPK2 is the instrument that measures R-D.3 |
PDKs (needed from stage 6 onward)
- SKY130 (130 nm, open, free) — LibreLane native; TinyTapeout/ChipFoundry shuttles.
✅ installed via
ciel (successor to volare): pip install ciel && ciel enable <version>
→ ~/.ciel/…/sky130A (2.1 GB, outside any repo). Do not vendor a PDK into a project —
it is an installed dependency, the equivalent of committing SolidWorks Toolbox into a part
file. Note the raw skywater-pdk source is not directly usable: timing ships as
.lib.json fragments that must be assembled, which is what open_pdks exists to do.
- GF180MCU (180 nm, open) — larger geometries
- IHP SG13G2 (130 nm SiGe, open) — European shuttle route, good documentation
- TSMC 65/28, GF 22FDX — NDA PDKs via Europractice/Muse/CMP; require commercial tools (typically via university program licenses: Synopsys/Cadence/Siemens academic bundles are ~free to research groups)
Open vs. closed — consolidated comparison
The stage tables above, collapsed into one view. Parity is an honest judgement of how
close the open tool gets to the commercial one for this project's needs, not in general.
| Stage |
Open / free |
Closed equivalent |
Parity |
| Lint / CDC |
Verilator --lint-only, Verible |
Spyglass (Syn) |
Lint fine; CDC signoff missing |
| RTL simulation |
Verilator, Icarus |
VCS (Syn), Xcelium (Cad), Questa (Sie) |
Good — Verilator often faster, but 2-state only |
| Testbench |
cocotb (Python) |
UVM on a commercial sim |
Good at this scale |
| Coverage |
Verilator line + functional |
vManager (Cad), VCS coverage |
Usable; no merged multi-run flows |
| Formal |
SymbiYosys, Yosys-smtbmc |
JasperGold (Cad), VC Formal (Syn) |
Partial — sufficient for the mute-latch / arbiter class |
| Waveforms |
GTKWave, Surfer |
Verdi (Syn) |
Usable; Verdi's debug productivity is far ahead |
| SPICE |
ngspice, Xyce |
PrimeSim (Syn), Spectre (Cad) |
Usable at 130 nm |
| Synthesis |
Yosys + ABC |
Design Compiler / Fusion Compiler (Syn), Genus (Cad) |
Good at 130 nm, weak ≤ 65 nm |
| Place & route |
OpenROAD via LibreLane |
Innovus (Cad), Fusion Compiler (Syn) |
Good at 130 nm |
| Custom / analog layout |
Magic, KLayout, xschem |
Virtuoso (Cad) |
Workable; large productivity gap |
| SRAM compiler |
OpenRAM |
Arm / foundry memory compilers |
SKY130 only; quality gap |
| Static timing |
OpenSTA |
PrimeTime (Syn), Tempus (Cad) |
Usable; not signoff-grade at advanced nodes |
| DRC / LVS |
Magic + Netgen, KLayout decks |
Calibre (Sie) |
Fine on open PDKs; foundry-mandated below 65 nm |
| Parasitic extraction |
OpenRCX |
StarRC (Syn), Quantus (Cad) |
Partial |
| Power analysis |
OpenSTA + VCD/SAIF |
PrimePower (Syn), Voltus (Cad) |
Usable |
| IR drop / EM |
— |
Voltus (Cad), RedHawk (Ansys) |
None |
| Scan insertion |
Yosys (basic), LibreLane partial |
DFT Compiler (Syn), Modus (Cad), Tessent (Sie) |
Weak |
| MBIST |
Hand-rolled, PULP wrappers |
Tessent MBIST (Sie) |
Weak |
| ATPG |
— |
TestMAX (Syn), Tessent FastScan (Sie) |
None |
| FPGA (ECP5) |
Yosys + nextpnr + prjtrellis |
Lattice Diamond |
Full — the open flow is preferred here |
| FPGA (Efinix / AMD) |
— |
Efinity, Vivado (free tiers) |
Closed but free of charge |
Syn = Synopsys · Cad = Cadence · Sie = Siemens EDA. All three are fully proprietary —
annual node-locked or floating seats, no source. RedHawk is an Ansys tool; Ansys was
acquired by Synopsys (deal closed 2025), further concentrating the market.
What this table shows
- Two hard zeroes: IR drop/EM and ATPG. Neither blocks L1 or L2. But R-K.1's
≥ 99% stuck-at coverage is unreachable without ATPG, making it a tape-out-era problem
to solve with a licence or a test service — not something to design around now.
- Calibre is the real chokepoint, not the design tools. Below 65 nm the foundry
mandates Calibre decks for signoff. That is foundry policy, not tool preference, so no
open alternative can substitute however good it becomes.
- The open flow degrades by node, not by function. At 130 nm it is essentially
complete end-to-end; gaps open as geometry shrinks. This is exactly the ladder in
feasibility-solo-build.md — free through L2 and a 130 nm
L3, licensed only beyond that.
- Open is not always the compromise. For Lattice ECP5, Yosys + nextpnr is the better
tool, and it is the recommended L2 path.
Minimum viable toolbox per level
- L1 (RTL proven in sim): Python + ONNX, Verilator, cocotb, GTKWave, Yosys lint. Cost: $0.
- L2 (FPGA in headphone): + Yosys/nextpnr (ECP5) or Efinity (Ti60), a $50–300 board. Cost: <$500.
- L3 (130 nm tapeout): + LibreLane/OpenROAD, Magic/KLayout/Netgen, OpenSTA, SKY130 PDK, shuttle slot. Cost: ~$300–5k.
- L3 (65/28 nm, real power numbers): university EDA licenses (Synopsys/Cadence), Calibre signoff, foundry PDK under NDA, Europractice MPW. Cost: $10–40k (academic) / $150k+ (industry).
Nvidia tools
In factories demand increasingly complex chips—delivered faster than ever. See how NVIDIA and leaders across the EDA ecosystem are advancing autonomous engineering across design, verification, physical implementation, signoff, and system design.
Discover how Cadence, Synopsys, Siemens EDA, and NVIDIA technologies—including NVIDIA PhysicsNeMo, CUDA-X libraries, and accelerated computing—are helping engineers reduce design iterations and accelerate innovation from chips to systems.
Tools named in the NVIDIA "AI factories" video
Source: promotional video transcript, captured 2026-08-06. Claims below are the
vendors' own and are unverified — treat the speed-up figures as marketing until
checked against documentation. Product names are as spoken in the video.
| Flow stage (this doc) |
Tool |
Vendor |
Claim as stated |
| 3. RTL design |
Autonomous AI engineer |
Cadence |
Compresses RTL development "from weeks to hours" and drives the flow itself |
| 4, 6, 7. Verification → implementation |
Broad set of agents |
Synopsys |
Autonomously handle RTL→GDS "with human supervision" |
| 4. Circuit simulation |
PrimeSim SPICE |
Synopsys |
Up to 18× faster on NVIDIA GPUs |
| 8. Signoff |
Fuse EDA AI agent |
Siemens |
Autonomous physical verification |
| Package / board |
Aura Stack AI |
Cadence |
Unifies 3D IC packaging and PCB design, exploration → implementation → signoff |
| Thermal |
cuDSS |
NVIDIA |
Accelerates thermal closure for stacked systems (sparse direct solver) |
| Multiphysics |
PhysicsNeMo |
NVIDIA |
Predicts fluid, thermal and structural behaviour beyond the chip |
| Mask synthesis |
cuLitho |
NVIDIA |
Computational lithography; cited as accelerating Synopsys' silicon-to-systems reach |
Relevance to AURA-1: contextual, not actionable. Every item is enterprise EDA sitting
in the Commercial column above — the one this document says becomes mandatory only at
65/28 nm, and then normally via university licensing. None is reachable on the L1–L3 path,
and nothing here changes the minimum viable toolbox.
Two things worth taking from it anyway:
- The agent layer is being added on top of the same flow, not replacing it. Design →
verification → implementation → signoff is unchanged; the claim is autonomy within each
stage. The bottom-up flow at the top of this document remains the right mental model.
- Verification is where the industry is spending its automation budget — which
corroborates feasibility-solo-build.md §4 ranking
verification as the most common cause of failed solo tapeouts.
⚠️ Name collision. Cadence's Aura Stack AI is an EDA product in the packaging/PCB
space. architecture-v0.1.md already flags "AURA-1" as a placeholder
with a trademark conflict in audio; this is a second conflict, and it sits in this
project's own field. Worth folding into the naming decision.
