E_GPU/modules.md

e-GPU module inventory — available locally vs. to be built

Gap analysis against Fig. 1 and Sections IV–VI of the paper (E_gpu.pdf). Local paths verified 2026-08-10. Legend: ✅ have · ⚠️ partial/unverified · ❌ build.

Right side of Fig. 1 — the e-GPU itself

#	Block (Fig. 1)	Paper §	Status	Local source / what to build
1	Compute Unit 0..N (SIMT core: fetch, warp scheduler, decode, issue, ALU, LSU, GPR)	IV-A	✅	repos/vortex-egpu-fork/hw/rtl/ — VX_pipeline.sv (one CU), VX_warp_sched.sv, VX_fetch/decode/issue/execute/commit.sv. Custom SLEEP_REQ instruction: VX_decode.sv:391, exported at VX_pipeline.sv:50. Config knobs (Table II: threads, warps, CUs) = VX_config.vh
2	Instruction cache (private, per CU)	IV-B	✅	hw/rtl/cache/VX_cache.sv + VX_bank.sv; paper config: single bank, 2 KiB/CU, 16 B line (= the fork's last commit)
3	Shared data cache (multi-bank, line-interleaved)	IV-B	⚠️	Same cache RTL supports multi-bank; the paper's multi-threaded request/response masking redesign is not verifiably in the fork — validate against §IV-B or rewrite
4	Cache Interface (CU↔cache crossbar)	IV-B	⚠️	Vortex arbiters exist (VX_cache_arb.sv, VX_smem_arb.sv, VX_mem_arb.sv); per-thread masked unified response is custom — verify/build
5	Memory Interface (miss → serialize line into 32-bit beats → OBI → arbiter)	IV-B (3 steps)	❌	Build: line serializer + OBI master adapter + round-robin arbiter. OBI spec: github.com/openhwgroup/obi (simple protocol); author's obi2axi repo is a reference; X-HEEP already speaks OBI
6	Controller (memory-mapped config regs; reset/start/halt; power controller watching end-of-kernel events; interrupt out)	IV-C	❌	Build from spec: OBI slave CSR block; inputs = per-CU sleep_req_o events (already wired out of block 1); outputs = per-CU clock/power gating + one interrupt line. Few hundred lines
7	e-GPU top-level wrapper (Slave port + Master port + Int, dashed box of Fig. 1)	Fig. 1	❌	Build; Vortex.sv / Vortex_axi.sv in the fork are reference top-levels to adapt (AXI→OBI)
8	Integration into X-HEEP via XAIF (1 OBI master, 1 OBI slave, 1 interrupt)	VI-A/B	❌	Glue to build — but with working templates: repos/x-heep/hw/ip_examples/simple_accelerator/, iffifo/, and system template repos/x-heep/hw/system/x_heep_system.sv.tpl. EPFL's HEEPsilon repo (not cloned) integrates a CGRA the same way

Left side of Fig. 1 — X-HEEP host

Block	Status	Local source
RISC-V CPU, SRAM banks, system bus/crossbar, DMA, peripherals (GPIO/SPI/I2C/UART), always-on domain (power manager, timer), interrupt controller (PLIC), JTAG/debug	✅ all	repos/x-heep/hw/core-v-mini-mcu/, hw/ip/, hw/system/ — complete, maintained, documented

Software stack (§V, §VI-C)

Component	Status	Notes
SIMT RISC-V extension API (thread/warp activate, split/join, barriers)	⚠️	Fork's runtime/ contains headers only (runtime/include/) — the intrinsics API survives; implementations/lib do not
Startup functions (init CUs, per-thread/warp stack pointers)	❌	§V-A; small assembly/C
Scheduler functions (work-group → CU/warp/thread distribution, CSR reads)	❌	§V-A; the core of Tiny-OpenCL
Kernel parser script (OpenCL C → plain C)	❌	§V-A; enables standard GNU RISC-V toolchain — no custom compiler needed
Host-side runtime for Newlib (buffers, kernel args, dispatch, wait)	❌	§VI-C; subset of OpenCL host API, single-binary, no OS
Benchmarks	❌	GeMM trivial to rewrite; TinyBio/MBio-Tracker not public

Bottom line

By area, ~90% of the hardware exists locally (compute units + caches dominate the 0.24–0.38 mm² floorplan). By effort, the missing pieces are the small glue blocks (5–8) plus the Tiny-OpenCL runtime — all specified in enough detail in the paper to rebuild.

Suggested order:

1. Simulate one compute unit standalone with Verilator (fork's Vortex flow).
2. Write Memory Interface (OBI) + Controller against the simple_accelerator X-HEEP example as template.
3. Top wrapper; integrate into X-HEEP simulation testbench (blocks 7–8).
4. Minimal runtime: startup + scheduler for 1 CU / few threads (headers exist).
5. GeMM kernel; compare against paper's Fig. 3 numbers (27 µs–1.7 ms range).