code
stringlengths 1
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stringlengths 6
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/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* ----------------------------[information]----------------------------------*/
/*
* COPYRIGHT : pls Programmierbare Logik & Systeme GmbH 1999,2011
*
* Author: mahi and parts taken from
*
* Description:
* Implements terminal for PLS/UDE debugger.
* Assumes JTAG access port is in non-cached area.
*/
/* ----------------------------[includes]------------------------------------*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include "Std_Types.h"
#include "MemMap.h"
#include "device_serial.h"
#include "sys/queue.h"
/* ----------------------------[private define]------------------------------*/
#define MPC55XX_SIMIO_HOSTAVAIL (0xAA000000)
#define MPC55XX_SIMIO_TARGETAVAIL (0x0000AA00)
#define MPC55XX_SIMIO_HOSTAVAILMASK (0xFF000000)
#define MPC55XX_SIMIO_TARGETAVAILMASK (0x0000FF00)
#define MPC55XX_SIMIO_THAVAIL (0x00000080)
#define MPC55XX_SIMIO_THLEN(dw) ( (dw) & 0x0000007F)
#define MPC55XX_SIMIO_HTNEED (0x00800000)
#define MPC55XX_SIMIO_HTLEN(dw) ( ( (dw) & 0x007F0000 ) >> 16 )
/* ----------------------------[private macro]-------------------------------*/
#ifndef MIN
#define MIN(_x,_y) (((_x) < (_y)) ? (_x) : (_y))
#endif
/* ----------------------------[private typedef]-----------------------------*/
typedef struct tagSimioAccess
{
volatile uint32_t dwCtrl;
volatile uint32_t adwData[16];
} TJtagSimioAccess;
/* ----------------------------[private function prototypes]-----------------*/
static int UDE_Write( uint8_t *data, size_t nbytes);
static int UDE_Read( uint8_t *data, size_t nbytes );
static int UDE_Open( const char *path, int oflag, int mode );
/* ----------------------------[private variables]---------------------------*/
DeviceSerialType UDE_Device = {
.device.type = DEVICE_TYPE_CONSOLE,
.name = "serial_ude",
// .init = T32_Init,
.read = UDE_Read,
.write = UDE_Write,
.open = UDE_Open,
};
TJtagSimioAccess g_JtagSimioAccess = { .dwCtrl = MPC55XX_SIMIO_HOSTAVAIL };
/* ----------------------------[private functions]---------------------------*/
/* ----------------------------[public functions]----------------------------*/
static void sendBuffer( int len ) {
uint32_t dwCtrlReg;
dwCtrlReg = g_JtagSimioAccess.dwCtrl;
if( MPC55XX_SIMIO_HOSTAVAIL == ( dwCtrlReg & MPC55XX_SIMIO_HOSTAVAILMASK ) ) {
dwCtrlReg &= 0xFFFF0000;
dwCtrlReg |= ( MPC55XX_SIMIO_TARGETAVAIL | MPC55XX_SIMIO_THAVAIL );
dwCtrlReg |= MPC55XX_SIMIO_THLEN(len);
g_JtagSimioAccess.dwCtrl = dwCtrlReg;
while (dwCtrlReg & MPC55XX_SIMIO_THAVAIL) {
dwCtrlReg = g_JtagSimioAccess.dwCtrl;
}
}
}
/**
*
* @param buffer
* @param count
* @return
*/
static int UDE_Write( uint8_t *buffer, size_t nbytes) {
uint8_t *ePtr = buffer + nbytes;
uint8_t *tPtr;
int left;
int i;
tPtr = (uint8_t*)&g_JtagSimioAccess.adwData[0];
while( buffer < ePtr ) {
left = MIN(sizeof(g_JtagSimioAccess.adwData),nbytes);
for (i = 0; i < left; i++) {
if( *buffer == '\r' ) {
*tPtr++ = '\n';
}
*tPtr++ = *buffer++;
}
sendBuffer(i);
}
return nbytes;
}
static int RcveChar( void )
{
uint32_t dwCtrlReg;
dwCtrlReg = g_JtagSimioAccess.dwCtrl;
if( MPC55XX_SIMIO_HOSTAVAIL == ( dwCtrlReg & MPC55XX_SIMIO_HOSTAVAILMASK ) )
{
// set need bit
dwCtrlReg &= 0xFF0000FF;
dwCtrlReg |= ( MPC55XX_SIMIO_TARGETAVAIL | MPC55XX_SIMIO_HTNEED );
// write ctrl reg
g_JtagSimioAccess.dwCtrl = dwCtrlReg;
// wait for remove of need bit
while( dwCtrlReg & MPC55XX_SIMIO_HTNEED )
{
dwCtrlReg = g_JtagSimioAccess.dwCtrl;
}
// get len and data
return( MPC55XX_SIMIO_HTLEN(dwCtrlReg) );
}
return( 0 );
}
/**
* Read characters from terminal
*
* @param buffer Where to save the data to.
* @param nbytes The maximum bytes to read
* @return The number of bytes read.
*/
static int UDE_Read( uint8_t *buffer, size_t nbytes )
{
size_t index;
int iTempLen, i;
char* pcTemp;
char cTemp = (char)EOF;
index = 0;
iTempLen = RcveChar();
pcTemp = (char*)&g_JtagSimioAccess.adwData[0];
for (i = 0; (i < iTempLen) && (index < nbytes); i++) {
cTemp = *pcTemp++;
if (cTemp == '\n')
cTemp = (char)EOF;
else if (cTemp == '\r') {
cTemp = '\n';
}
*buffer++ = cTemp;
index++;
}
return nbytes;
}
static int UDE_Open( const char *path, int oflag, int mode ) {
(void)path;
(void)oflag;
(void)mode;
return 0;
}
|
2301_81045437/classic-platform
|
drivers/serial_dbg_ude.c
|
C
|
unknown
| 5,637
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef SERIAL_DBG_UDE_H_
#define SERIAL_DBG_UDE_H_
extern DeviceSerialType UDE_Device;
#endif /* SERIAL_DBG_UDE_H_ */
|
2301_81045437/classic-platform
|
drivers/serial_dbg_ude.h
|
C
|
unknown
| 888
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* ----------------------------[information]----------------------------------*/
/*
* COPYRIGHT : pls Programmierbare Logik & Systeme GmbH 1999,2011
*
* Author: mahi and parts taken from pls
*
* Description:
* Implements terminal for PLS/UDE debugger.
* Assumes JTAG access port is in non-cached area.
*/
/* ----------------------------[includes]------------------------------------*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include "Std_Types.h"
#include "MemMap.h"
#include "device_serial.h"
#include "sys/queue.h"
/* ----------------------------[private define]------------------------------*/
#define ARM_SIMIO_ENCODE_CHANNEL(channel) \
((channel<<24) & 0x0F000000)
#define ARM_SIMIO_DECODE_CHANNEL(data) \
((data>>24) & 0x0F)
#define ARM_SIMIO_ENCODE_DATA(data) \
(data & 0x0FF)
#define ARM_SIMIO_DECODE_DATA(data) \
(data & 0x0FF)
#define ARM_SIMIO_FLAG_DATA1 0x10000000
#define ARM_SIMIO_CHECK_DATA1(data) \
(data & ARM_SIMIO_FLAG_DATA1)
#define ARM_SIMIO_ENCODE_DATA1(data) \
(((data<<8) & 0x0FF00) | ARM_SIMIO_FLAG_DATA1)
#define ARM_SIMIO_DECODE_DATA1(data) \
((data>>8) & 0x0FF)
#define ARM_SIMIO_FLAG_DATA2 0x20000000
#define ARM_SIMIO_CHECK_DATA2(data) \
(data & ARM_SIMIO_FLAG_DATA2)
#define ARM_SIMIO_ENCODE_DATA2(data) \
(((data<<16) & 0x0FF0000) | ARM_SIMIO_FLAG_DATA2)
#define ARM_SIMIO_DECODE_DATA2(data) \
((data>>16) & 0x0FF)
#define DEFAULT_SIMIO_CHANNEL 0
/* ----------------------------[private macro]-------------------------------*/
#ifndef MIN
#define MIN(_x,_y) (((_x) < (_y)) ? (_x) : (_y))
#endif
/* ----------------------------[private typedef]-----------------------------*/
typedef struct tagSimioAccess
{
volatile uint32_t dwCtrl;
volatile uint32_t adwData[16];
} TJtagSimioAccess;
/* ----------------------------[private function prototypes]-----------------*/
static int UDE_Write( uint8_t *data, size_t nbytes);
static int UDE_Read( uint8_t *data, size_t nbytes );
static int UDE_Open( const char *path, int oflag, int mode );
/* ----------------------------[private variables]---------------------------*/
DeviceSerialType UDE_Device = {
.device.type = DEVICE_TYPE_CONSOLE,
.name = "serial_ude",
// .init = T32_Init,
.read = UDE_Read,
.write = UDE_Write,
.open = UDE_Open,
};
/* ----------------------------[private functions]---------------------------*/
/* ----------------------------[public functions]----------------------------*/
void SendChar(int ch)
{
asm volatile (" \n\
1: \n\
MRC %%p14,0,%%R1,%%c0,%%c1 \n\
TST %%R1,#0x20000000 \n\
BNE 1b \n\
MCR %%p14,0,%0,%%c0,%%c5" : : "r" (ch) : "cc", "1" );
}
void SIMIO_PutByteToHost (unsigned int Channel, unsigned char Data)
{
int ch=Data;
ch|=ARM_SIMIO_ENCODE_CHANNEL(Channel);
SendChar(ch); /*lint !e522 MISRA:FALSE_POSITIVE:Assembler function:[MISRA 2012 Rule 2.2, required] */
}
int UDE_Write ( uint8_t *data, size_t nbytes)
{
for ( uint32_t index = 0; index < nbytes; index++, data++) {
SIMIO_PutByteToHost (DEFAULT_SIMIO_CHANNEL,(unsigned char)*data); /*lint !e522 MISRA:FALSE_POSITIVE:Assembler function:[MISRA 2012 Rule 2.2, required] */
}
return nbytes;
}
/**
* Read characters from terminal
*
* @param buffer Where to save the data to.
* @param nbytes The maximum bytes to read
* @return The number of bytes read.
*/
static int UDE_Read( uint8_t *buffer, size_t nbytes )
{
return nbytes;
}
static int UDE_Open( const char *path, int oflag, int mode ) {
(void)path;
(void)oflag;
(void)mode;
return 0;
}
|
2301_81045437/classic-platform
|
drivers/serial_dbg_ude_arm.c
|
C
|
unknown
| 4,577
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef SERIAL_DBG_UDE_H_
#define SERIAL_DBG_UDE_H_
extern DeviceSerialType UDE_Device;
#endif /* SERIAL_DBG_UDE_H_ */
|
2301_81045437/classic-platform
|
drivers/serial_dbg_ude_arm.h
|
C
|
unknown
| 888
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/*lint -w1 Only errors in module used during development */
/* ----------------------------[information]----------------------------------*/
/*
*
* Description:
* Implements terminal for isystems winidea debugger
* Assumes JTAG access port is in non-cached area.
*/
/* ----------------------------[includes]------------------------------------*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include "Std_Types.h"
#include "MemMap.h"
#include "device_serial.h"
#include "sys/queue.h"
/* ----------------------------[private define]------------------------------*/
#define TWBUFF_SIZE 0x100
#define TRBUFF_SIZE 0x100
#define TBUFF_PTR 2
#define TWBUFF_LEN (TWBUFF_SIZE+TBUFF_PTR)
#define TRBUFF_LEN (TRBUFF_SIZE+TBUFF_PTR)
#define TWBUFF_TPTR (g_TWBuffer[TWBUFF_SIZE+0])
#define TWBUFF_CPTR (g_TWBuffer[TWBUFF_SIZE+1])
#define TWBUFF_INC(n) ((n + 1)&(TWBUFF_SIZE-1))
#define TWBUFF_FULL() (TWBUFF_TPTR==((TWBUFF_CPTR-1)&(TWBUFF_SIZE-1)))
/* ----------------------------[private macro]-------------------------------*/
/* ----------------------------[private typedef]-----------------------------*/
/* ----------------------------[private function prototypes]-----------------*/
static int WinIdea_Write( uint8_t *data, size_t nbytes);
static int WinIdea_Read( uint8_t *data, size_t nbytes );
static int WinIdea_Open( const char *path, int oflag, int mode );
/* ----------------------------[private variables]---------------------------*/
#if defined(MC912DG128A)
static volatile unsigned char g_TWBuffer[TWBUFF_LEN];
static volatile unsigned char g_TRBuffer[TRBUFF_LEN];
SECTION_RAM_NO_CACHE_DATA volatile char g_TConn;
#else
static volatile unsigned char g_TWBuffer[TWBUFF_LEN] __balign(0x100);
static volatile unsigned char g_TRBuffer[TRBUFF_LEN] __balign(0x100);
volatile char g_TConn;
#endif
/* ----------------------------[private functions]---------------------------*/
/* ----------------------------[public functions]----------------------------*/
/**
*
* @param buffer
* @param count
* @return
*/
static int WinIdea_Write( uint8_t *buffer, size_t nbytes) {
if (g_TConn)
{
char *buf = (char *)buffer;
unsigned char nCnt,nLen;
for(nCnt=0; nCnt<nbytes; nCnt++)
{
while(TWBUFF_FULL()) ;
nLen=TWBUFF_TPTR;
g_TWBuffer[nLen]=buf[nCnt];
nLen=TWBUFF_INC(nLen);
TWBUFF_TPTR=nLen;
}
}
return nbytes;
}
/**
* Read characters from terminal
*
* @param buffer Where to save the data to.
* @param nbytes The maximum bytes to read
* @return The number of bytes read.
*/
static int WinIdea_Read( uint8_t *buffer, size_t nbytes )
{
(void)buffer; //lint !e920 MISRA False positive. Allowed to cast pointer to void here.
(void)nbytes; //lint !e920 MISRA False positive. Allowed to cast pointer to void here.
(void)g_TRBuffer[0];
return 0;
}
static int WinIdea_Open( const char *path, int oflag, int mode ) {
(void)path; //lint !e920 MISRA False positive. Allowed to cast pointer to void here.
(void)oflag;
(void)mode;
return 0;
}
DeviceSerialType WinIdea_Device = {
.device.type = DEVICE_TYPE_CONSOLE,
.name = "serial_winidea",
// .init = T32_Init,
.read = WinIdea_Read,
.write = WinIdea_Write,
.open = WinIdea_Open,
};
|
2301_81045437/classic-platform
|
drivers/serial_dbg_winidea.c
|
C
|
unknown
| 4,188
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef SERIAL_DBG_WINIDEA_H_
#define SERIAL_DBG_WINIDEA_H_
extern DeviceSerialType WinIdea_Device;
#endif /* SERIAL_DBG_WINIDEA_H_ */
|
2301_81045437/classic-platform
|
drivers/serial_dbg_winidea.h
|
C
|
unknown
| 904
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/*
* DESCRIPTION
* Uses the linFlex module that contains a UART.
* The HW features 4 RX and 4 TX buffers
*
* UARTCR[WL1,WL0] is not clear but should be for "normal" 8-bit transfers
* WL0 - 0 - 7 bits
* 1 - 8 bits
* WL1 - 0 - since we don't really care about the 15-16 bits
*
*/
/* ----------------------------[includes]------------------------------------*/
#include <stdint.h>
#include "device_serial.h"
#include "sys/queue.h"
#include "MemMap.h"
#include "mpc55xx.h"
#include "Mcu.h"
/* ----------------------------[private define]------------------------------*/
#define UARTCR_UART 0x00000001
#define UARTCR_TDFL(_size) ((_size)<<(31-18))
#define UARTCR_RDFL(_size) ((_size)<<(31-21))
#define UARTCR_RXEN (1<<(31-26))
#define UARTCR_TXEN (1<<(31-27))
#define UARTCR_WL_8BIT (1<<(31-30))
#define SCI_BAUD 57600 // 4800 || 9600 || 19200 || 57600 || 115200
#define SCI_UNIT 0 // 0 || 1 || 2
#if defined(CFG_MPC5645S)
#define DTFTFF DTF
#define DRFRFE DRF
#if (SCI_UNIT==0)
#define LINFLEX LINFLEX_0
#elif (SCI_UNIT==1)
#define LINFLEX LINFLEX_1
#elif (SCI_UNIT==2)
#define LINFLEX LINFLEX_2
#endif
#else
#if (SCI_UNIT==0)
#define LINFLEX LINFlexD_0
#elif (SCI_UNIT==1)
#define LINFLEX LINFlexD_1
#elif (SCI_UNIT==2)
#define LINFLEX LINFlexD_2
#else
#error Not a valid unit
#endif
#endif
uint8 isOpen = 0;
#define SCI_RX_FIFO 0
#define SCI_RX_BUFFER 1
#define SCI_RX_MODE SCI_FIFO
/* ----------------------------[private macro]-------------------------------*/
/* ----------------------------[private typedef]-----------------------------*/
/* ----------------------------[private function prototypes]-----------------*/
/* ----------------------------[private variables]---------------------------*/
/* ----------------------------[private functions]---------------------------*/
static int SCI_Write(uint8_t *data, size_t nbytes);
static int SCI_Read(uint8_t *data, size_t nbytes);
static int SCI_Open(const char *path, int oflag, int mode);
/* ----------------------------[public functions]----------------------------*/
static int SCI_Open(const char *path, int oflag, int mode) {
#if (SCI_RX_MODE == SCI_RX_BUFFER)
uint32 rxFifo = 0ul;
#else
uint32 rxFifo = 1ul;
#endif
uint32_t pClk;
/* Set to init mode (NO, were are not initialized after this ) */
LINFLEX.LINCR1.R = 1;
/* Set to UART mode, FIFO=4 for both RX, TX */
LINFLEX.UARTCR.R = (1UL << 0U); /* Enable UART mode */
// 0x0233;* Enable UART mode */
LINFLEX.UARTCR.R = ((rxFifo << (31U - 22U)) | /* 0 - RFBM (RX FIFO mode)*/
(0UL << (31U - 23U)) | /* 0 - TFBM (TX FIFO mode)*/
(0UL << (31U - 24U)) | /* 0 - WL1 (always 8-bits transfers)*/
(0UL << (31U - 25U)) | /* 0 - parity (ignore) */
(1UL << (31U - 26U)) | /* 1 - Receiver enabled */
(1UL << (31U - 27U)) | /* 1 - Transmitter enabled */
(0UL << (31U - 29U)) | /* 0 - Parity disabled */
(1UL << (31U - 30U)) | /* 1 - WL0 (word length = 8) */
(1UL << (31U - 31U))); /* 1 - UART mode */
/**
* Baud = Fper / ( 16 *LFDIV )
*
*/
pClk = Mcu_Arc_GetPeripheralClock(PERIPHERAL_CLOCK_LIN_A); // Choose clock based on architecture (irq_mpc*.h)
#if (SCI_BAUD == 57600) || (SCI_BAUD == 9600) || (SCI_BAUD == 19200) || (SCI_BAUD == 4800)
LINFLEX.LINIBRR.B.DIV_M = pClk / (16 * SCI_BAUD);
LINFLEX.LINFBRR.B.DIV_F = (16 * (pClk % (16 * SCI_BAUD))) / (16 * SCI_BAUD);
#elif (SCI_BAUD == 115200)
LINFLEX.LINIBRR.B.DIV_M = pClk / (16 * SCI_BAUD);
LINFLEX.LINFBRR.B.DIV_F = (16 * (pClk % (16 * SCI_BAUD))) / (16 * SCI_BAUD);
#else
#error BAD baudrate
#endif
/* Set to normal mode */
LINFLEX.LINCR1.R = 0;
isOpen = 1;
return 0;
}
/**
* Blocking write to serial port
*/
int SCI_Write(uint8_t *data, size_t nbytes) {
if (isOpen == 0) {
SCI_Open(NULL, 0, 0);
}
int i = 0;
while (nbytes--) {
LINFLEX.BDRL.B.DATA0 = data[i];
i++;
/* Once the programmed number of bytes (halfwords) has been transmitted,
the DTFTFF flag is set in UARTSR. */
while (LINFLEX.UARTSR.B.DTFTFF == 0) {}
/* Clear the DTFTFF (must be done in software) by writing 1 */
LINFLEX.UARTSR.B.DTFTFF = 1;
}
return i;
}
static int SCI_Read(uint8_t *data, size_t nbytes) {
if (isOpen == 0) {
SCI_Open(NULL, 0, 0);
}
int i = 0;
while (nbytes--) {
/* DRFRFE is set by hardware and indicates that the number of bytes
programmed in RDFL have been received. */
#if (SCI_RX_MODE == SCI_RX_BUFFER)
while (LINFLEX.UARTSR.B.DRFRFE == 0) {}
#else
while (LINFLEX.UARTSR.B.DRFRFE == 1) {}
#endif
data[i] = LINFLEX.BDRM.B.DATA4;
i++;
/* Clear the RFE (must be done in software) */
LINFLEX.UARTSR.B.DRFRFE = 1;
}
return i;
}
DeviceSerialType SCI_Device = {
.device.type = DEVICE_TYPE_CONSOLE,
.device.name = "serial_sci",
.name = "serial_sci",
.read = SCI_Read,
.write = SCI_Write,
.open = SCI_Open,
};
|
2301_81045437/classic-platform
|
drivers/serial_sci.c
|
C
|
unknown
| 6,245
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef SERIAL_SCI_H_
#define SERIAL_SCI_H_
extern DeviceSerialType SCI_Device;
#endif /* SERIAL_SCI_H_ */
|
2301_81045437/classic-platform
|
drivers/serial_sci.h
|
C
|
unknown
| 876
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ARC_T1_INT_H
#define ARC_T1_INT_H
#include "arc.h"
typedef struct {
uint16_t id;
char name[OS_ARC_PCB_NAME_SIZE];
uint8_t core;
uint8_t priority;
int16_t vector;
int16_t type;
void (*entry)( void );
} ArcT1Info_t;
ArcT1Info_t * Arc_T1_GetInfoAboutIsr(uint16_t *len);
void Arc_T1_Init(void);
void Arc_T1_MainFunction(void);
void Arc_T1_BackgroundFunction(void);
#endif /* ARC_T1_INT_H */
|
2301_81045437/classic-platform
|
include/Arc_T1_Int.h
|
C
|
unknown
| 1,221
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ARC_TYPES_H_
#define ARC_TYPES_H_
#include <stdint.h>
typedef volatile int8_t vint8_t;
typedef volatile uint8_t vuint8_t;
typedef volatile int16_t vint16_t;
typedef volatile uint16_t vuint16_t;
typedef volatile int32_t vint32_t;
typedef volatile uint32_t vuint32_t;
typedef volatile int64_t vint64_t;
typedef volatile uint64_t vuint64_t;
/* Need to set the type hierarchy since it is overwritten by the typedefs above */
//lint -parent(uint64, uint32)
//lint -parent(uint64, vuint64_t)
//lint -parent(uint32, uint16)
//lint -parent(uint32, uint8)
//lint -parent(uint32, uint32_t)
//lint -parent(uint32, vuint32_t)
//lint -parent(uint16, uint8)
//lint -parent(uint16, vuint16_t,)
//lint -parent(uint16, uint16_t)
//lint -parent(uint8, vuint8_t)
//lint -parent(uint8, uint8_t)
//lint -parent(sint32, sint64)
//lint -parent(sint16, sint32)
//lint -parent(sint8, sint16)
#endif /* ARC_TYPES_H_ */
|
2301_81045437/classic-platform
|
include/Arc_Types.h
|
C
|
unknown
| 1,696
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef BSD_H
#define BSD_H
#if defined(USE_LWIP)
#include "lwip/inet.h"
#include "lwip/sockets.h"
#else
#error "We currently only support LWIP socket implementation"
#endif
#endif /* BSD_H */
|
2301_81045437/classic-platform
|
include/Bsd.h
|
C
|
unknown
| 958
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef BYTEORDER_H_
#define BYTEORDER_H_
// NOTE!
// Implements only big endian stuff
//#define BE_TO_CPU_32(x) ((uint8_t*)(x))[0] + (((uint8_t*)(x))[1]<<8) + (((uint8_t*)(x))[2]<<16) + (((uint8_t*)(x))[3]<<24)
//#define BIG_ENDIAN
// a,b,c,d -> d,c,b,a
#define bswap32(x) (((uint32)(x) >> 24) | (((uint32)(x) >> 8) & 0xff00) | (((uint32)(x) & 0xff00 ) << 8) | (((uint32)(x) & 0xff) << 24) )
#define bswap16(x) (((uint16)(x) >> 8) | (((uint16)(x) & 0xff) << 8))
#if 0 //defined(BIG_ENDIAN)
#define cpu_to_le32(_x) bswap32(_x)
#define cpu_to_be32(_x)
#define le32_to_cpu(_x)
#define be32_to_cpu(_x)
#endif
#endif /*BYTEORDER_H_*/
|
2301_81045437/classic-platform
|
include/Byteorder.h
|
C
|
unknown
| 1,431
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef CALIBRATIONDATA_H_
#define CALIBRATIONDATA_H_
#include "Calibration_Settings.h"
#ifdef CALIBRATION_ENABLED
/* Section data from linker script. */
extern char __CALIB_RAM_START;
extern char __CALIB_RAM_END;
extern char __CALIB_ROM_START;
#ifdef __CWCC__
#pragma section RW ".calibration_data" ".calibration"
#define ARC_DECLARE_CALIB(type, name) __declspec(section ".calibration_data") type name
#else
#define ARC_DECLARE_CALIB(type, name) type __attribute__((section (".calibration"))) name
#define ARC_DECLARE_CALIB_SHARED(type, name) type __attribute__((section (".calib_shared"))) name
#define ARC_DECLARE_CALIB_EXTERN(type, name) extern type name
#define ARC_DECLARE_CALIB_COMPONENT(type, name) type __attribute__((section (".calib_component"))) name
#endif/* __CWCC__ */
#else
#define ARC_DECLARE_CALIB(type, name) type name
#define ARC_DECLARE_CALIB_SHARED(type, name) type name
#define ARC_DECLARE_CALIB_EXTERN(type, name) extern type name
#define ARC_DECLARE_CALIB_COMPONENT(type, name) type name
#endif /* CALIBRATION_ENABLED */
#endif /* CALIBRATIONDATA_H_ */
|
2301_81045437/classic-platform
|
include/CalibrationData.h
|
C
|
unknown
| 1,872
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2 */
/** @tagSettings DEFAULT_ARCHITECTURE=ZYNQ|PPC|TMS570|MPC5607B|MPC5645S|RH850F1H|MPC5777M|MPC5748G|JACINTO5|JACINTO6|STM32 */
#ifndef COMSTACK_TYPES_H_
#define COMSTACK_TYPES_H_
#define ECUC_SW_MAJOR_VERSION 1u
#define ECUC_SW_MINOR_VERSION 0u
#define ECUC_SW_PATCH_VERSION 0u
#include "Std_Types.h" /** !req COMM820.partially */
// Zero-based integer number
// The size of this global type depends on the maximum
// number of PDUs used within one software module.
// Example :
// If no software module deals with more PDUs that
// 256, this type can be set to uint8.
// If at least one software module handles more than
// 256 PDUs, this type must globally be set to uint16.
// In order to be able to perform table-indexing within a software
// module, variables of this type shall be zero-based and consecutive.
// There might be several ranges of PduIds in a module, one for each type of
// operation performed within that module (e.g. sending and receiving).
typedef uint16 PduIdType;
typedef uint16 PduLengthType;
typedef struct {
uint8 *SduDataPtr; // payload
PduLengthType SduLength; // length of SDU
} PduInfoType;
typedef enum {
TP_STMIN=0,
TP_BS,
TP_BC,
} TPParameterType;
typedef enum {
TP_DATACONF,
TP_DATARETRY,
TP_CONFPENDING,
TP_NORETRY,
} TpDataStateType;
typedef struct {
TpDataStateType TpDataState;
PduLengthType TxTpDataCnt;
} RetryInfoType;
/*
typedef struct {
P2VAR(uint8,AUTOMATIC,AUTOSAR_COMSTACKDATA) SduDataPtr
PduLengthType SduLength;
} PduInfoType;
*/
// IMPROVEMENT: remove all non-E_prefixed error enum values
typedef enum {
BUFREQ_OK=0,
BUFREQ_NOT_OK=1,
BUFREQ_E_NOT_OK=BUFREQ_NOT_OK,
BUFREQ_BUSY=2,
BUFREQ_E_BUSY=BUFREQ_BUSY,
BUFREQ_OVFL=3,
BUFREQ_E_OVFL=BUFREQ_OVFL,
} BufReq_ReturnType;
// 0x00--0x1e General return types
// 0x1f--0x3c Error notif, CAN
// 0x3d--0x5a Error notif, LIN
// more
typedef uint8 NotifResultType;
#define NTFRSLT_OK 0x00
#define NTFRSLT_E_NOT_OK 0x01
#define NTFRSLT_E_TIMEOUT_A 0x02
#define NTFRSLT_E_TIMEOUT_BS 0x03
#define NTFRSLT_E_TIMEOUT_CR 0x04
#define NTFRSLT_E_WRONG_SN 0x05
#define NTFRSLT_E_INVALID_FS 0x06
#define NTFRSLT_E_UNEXP_PDU 0x07
#define NTFRSLT_E_WFT_OVRN 0x08
#define NTFRSLT_E_ABORT 0x09
#define NTFRSLT_E_NO_BUFFER 0x0A
#define NTFRSLT_E_CANCELATION_OK 0x0B
#define NTFRSLT_E_CANCELATION_NOT_OK 0x0C
#define NTFRSLT_PARAMETER_OK 0x0D
#define NTFRSLT_E_PARAMETER_NOT_OK 0x0E
#define NTFRSLT_E_RX_ON 0x0F
#define NTFRSLT_E_VALUE_NOT_OK 0x10
#define NTFRSLT_E_FR_ML_MISMATCH 0x5B
#define NTFRSLT_E_FR_WRONG_BP 0x5C
#define NTFRSLT_E_FR_TX_ON 0x5D
typedef uint8 BusTrcvErrorType;
#define BUSTRCV_NO_ERROR 0x00
#define BUSBUSTRCV_E_ERROR 0x01
typedef uint8 NetworkHandleType;
#endif /* COMSTACK_TYPES_H_*/
|
2301_81045437/classic-platform
|
include/ComStack_Types.h
|
C
|
unknown
| 3,872
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DOIP_MEMMAP_H_
#define DOIP_MEMMAP_H_
#include "MemMap.h"
#endif /*DOIP_MEMMAP_H_*/
|
2301_81045437/classic-platform
|
include/DoIP_MemMap.h
|
C
|
unknown
| 852
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_H_
#define EEP_H_
/** @tagSettings DEFAULT_ARCHITECTURE=PPC|MPC5645S|MPC5607B */
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2 */
#include "Std_Types.h"
#include "MemIf_Types.h"
/* Standard info */
#define EEP_VENDOR_ID 60u
#define EEP_MODULE_ID 90u
#define EEP_SW_MAJOR_VERSION 2u
#define EEP_SW_MINOR_VERSION 0u
#define EEP_SW_PATCH_VERSION 0u
#define EEP_AR_RELASE_MAJOR_VERSION 4u
#define EEP_AR_RELASE_MINOR_VERSION 1u
#define EEP_AR_RELASE_PATCH_VERSION 2u
typedef uint32 Eep_AddressType;
typedef Eep_AddressType Eep_LengthType;
/* Development errors */
// API parameter checking
#define EEP_E_PARAM_CONFIG 0x10u
#define EEP_E_PARAM_ADDRESS 0x11u
#define EEP_E_PARAM_DATA 0x12u
#define EEP_E_PARAM_LENGTH 0x13u
#define EEP_E_PARAM_POINTER 0x23u
// EEPROM state checking
#define EEP_E_UNINIT 0x20u
#define EEP_E_BUSY 0x21u
#define EEP_E_TIMEOUT 0x22u
/* Production errors */
// #define EEP_E_COM_FAILURE 0x30 /* Shall be located in DemIntErrId.h when its available */
/* Service id's for fls functions */
#define EEP_INIT_ID 0x00u
#define EEP_SETMODE_ID 0x01u
#define EEP_READ_ID 0x02u
#define EEP_WRITE_ID 0x03u
#define EEP_ERASE_ID 0x04u
#define EEP_COMPARE_ID 0x05u
#define EEP_CANCEL_ID 0x06u
#define EEP_GETSTATUS_ID 0x07u
#define EEP_GETJOBSTATUS_ID 0x08u
#define EEP_GETVERSIONINFO_ID 0x0Au
#define EEP_GLOBAL_SERVICE_ID 0x10u
#include "Eep_Cfg.h"
/** @req SWS_Eep_00143 */
void Eep_Init( const Eep_ConfigType *ConfigPtr );
/** @req SWS_Eep_00147 */
Std_ReturnType Eep_Erase( Eep_AddressType EepromAddress,
Eep_LengthType Length );
/** @req SWS_Eep_00146 */
Std_ReturnType Eep_Write ( Eep_AddressType EepromAddress,
const uint8 *SourceAddressPtr,
Eep_LengthType Length );
/** @req SWS_Eep_00149 */
void Eep_Cancel( void );
/** @req SWS_Eep_00150 */
MemIf_StatusType Eep_GetStatus( void );
/** @req SWS_Eep_00151 */
MemIf_JobResultType Eep_GetJobResult( void );
/** @req SWS_Eep_00153 */
void Eep_MainFunction( void );
/** @req SWS_Eep_00145 */
Std_ReturnType Eep_Read ( Eep_AddressType EepromAddress,
uint8 *TargetAddressPtr,
Eep_LengthType Length );
/** @req SWS_Eep_00148 */
Std_ReturnType Eep_Compare( Eep_AddressType EepromAddress,
const uint8 *TargetAddressPtr,
Eep_LengthType Length );
/** @req SWS_Eep_00144 */
void Eep_SetMode( MemIf_ModeType Mode );
#if ( EEP_VERSION_INFO_API == STD_ON )
/** @req SWS_Eep_00152 */
void Eep_GetVersionInfo( Std_VersionInfoType *versionInfo );
#endif
#endif /*EEP_H_*/
|
2301_81045437/classic-platform
|
include/Eep.h
|
C
|
unknown
| 3,808
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CONFIGTYPES_H_
#define EEP_CONFIGTYPES_H_
/* STD container : EepExternalDriver
* EepSpiReference: 1..* Ref to SPI sequence
*/
#if defined(EEP_USES_EXTERNAL_DRIVER)
typedef struct {
/* Reference to SPI sequence (required for external EEPROM drivers).
*
* The 3.0 and 4.0 does things a bit different here
*
* 3.0
* =======
* const Eep_ConfigType EepConfigData =
* {
* �
* EepCmdChannel = EEP_SPI_CH_COMMAND,
* EepAdrChannel = EEP_SPI_CH_ADDRESS,
* �
* EepWriteSequence = EEP_SPI_SEQ_WRITE,
* �
* };
*
*
* 4.0
* =======
* Wants the defines generated to Spi_Cfg.h to be used directly as:
* #define Spi_EepReadSequence 10
* #define Spi_EepReadJob 20
* #define Spi_.....
* #define Spi_EepChCommand 30
* #define Spi_EepChAddress 31
* #define Spi_EepChReadData 32
*
*/
// uint32 SpiReference;
/* EEP094 */
Spi_SequenceType EepCmdSequence;
Spi_SequenceType EepCmd2Sequence;
Spi_SequenceType EepReadSequence;
Spi_SequenceType EepWriteSequence;
Spi_ChannelType EepAddrChannel;
Spi_ChannelType EepCmdChannel;
Spi_ChannelType EepDataChannel;
Spi_ChannelType EepWrenChannel;
} Eep_ExternalDriverType;
#endif
/* STD container : EepInitConfiguration
* EepBaseAddress: 1 int
* EepDefaultMode: 1 enum MEMIF_MODE_FAST, MEMIF_MODE_SLOW
* EepFastReadBlockSize: 1
* EepFastWriteBlockSize: 1
* EepJobCallCycle: 1 float (not used by config?)
* Eep_JobEndNotification 0..1 Function
* Eep_JobErrorNotification 0..1 Function
* EepNormalReadBlockSize 1 Int
* EepNormalWriteBlockSize 1 Int
* EepSize 1 Int
*
* Defined by Arc:
* EepPageSize 1 Int
*/
typedef struct {
// This parameter is the EEPROM device base address.
Eep_AddressType EepBaseAddress;
// This parameter is the default EEPROM device mode after initialization.
MemIf_ModeType EepDefaultMode;
// This parameter is the number of bytes read within one job processing cycle in fast mode
Eep_LengthType EepFastReadBlockSize;
// This parameter is the number of bytes written within one job processing cycle in fast mode
Eep_LengthType EepFastWriteBlockSize;
// call cycle of the job processing function during write/erase operations. Unit: [s]
//float EepJobCallCycle;
// This parameter is a reference to a callback function for positive job result
void (*Eep_JobEndNotification)(void);
// This parameter is a reference to a callback function for negative job result
void (*Eep_JobErrorNotification)(void);
// number of bytes read within one job processing cycle in normal mode.
Eep_LengthType EepNormalReadBlockSize;
// Number of bytes written within one job processing cycle in normal mode.
Eep_LengthType EepNormalWriteBlockSize;
// This parameter is the used size of EEPROM device in bytes.
Eep_LengthType EepSize;
// ---- ARC ADDITIONS ----
// This parameter is the EEPROM page size, i.e. number of bytes.
Eep_LengthType EepPageSize;
#if defined(EEP_USES_EXTERNAL_DRIVER)
const Eep_ExternalDriverType *externalDriver;
#endif
} Eep_ConfigType;
#endif /* EEP_CONFIGTYPES_H_ */
|
2301_81045437/classic-platform
|
include/Eep_ConfigTypes.h
|
C
|
unknown
| 4,071
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.0.3 */
/** @tagSettings DEFAULT_ARCHITECTURE=RH850F1H */
/* @req FR455 */
/* @req FR499 */
#ifndef FR_GENERAL_TYPES
#define FR_GENERAL_TYPES
#if defined(USE_DEM) || defined(CFG_FR_DEM_TEST)
#include "Dem.h"
#endif
/* @req FR102 */
/* @req FR117 */
/* @req FR110 */
/* @req FR077 */
/* @req FR505 */
typedef enum {
FR_POCSTATE_CONFIG = 0,
FR_POCSTATE_DEFAULT_CONFIG,
FR_POCSTATE_HALT,
FR_POCSTATE_NORMAL_ACTIVE,
FR_POCSTATE_NORMAL_PASSIVE,
FR_POCSTATE_READY,
FR_POCSTATE_STARTUP,
FR_POCSTATE_WAKEUP
}Fr_POCStateType;
/* @req FR506 */
typedef enum {
FR_SLOTMODE_KEYSLOT,
FR_SLOTMODE_ALL_PENDING,
FR_SLOTMODE_ALL
}Fr_SlotModeType;
/* @req FR599 */
#define FR_SLOTMODE_SINGLE() FR_SLOTMODE_KEYSLOT
/* @req FR507 */
typedef enum {
FR_ERRORMODE_ACTIVE = 0,
FR_ERRORMODE_PASSIVE,
FR_ERRORMODE_COMM_HALT
}Fr_ErrorModeType;
/* @req FR508 */
typedef enum {
FR_WAKEUP_UNDEFINED = 0,
FR_WAKEUP_RECEIVED_HEADER,
FR_WAKEUP_RECEIVED_WUP,
FR_WAKEUP_COLLISION_HEADER,
FR_WAKEUP_COLLISION_WUP,
FR_WAKEUP_COLLISION_UNKNOWN,
FR_WAKEUP_TRANSMITTED
}Fr_WakeupStatusType;
/* @req FR509 */
typedef enum {
FR_STARTUP_UNDEFINED = 0,
FR_STARTUP_COLDSTART_LISTEN,
FR_STARTUP_INTEGRATION_COLDSTART_CHECK,
FR_STARTUP_COLDSTART_JOIN,
FR_STARTUP_COLDSTART_COLLISION_RESOLUTION,
FR_STARTUP_COLDSTART_CONSISTENCY_CHECK,
FR_STARTUP_INTEGRATION_LISTEN,
FR_STARTUP_INITIALIZE_SCHEDULE,
FR_STARTUP_INTEGRATION_CONSISTENCY_CHECK,
FR_STARTUP_COLDSTART_GAP,
FR_STARTUP_EXTERNAL_STARTUP
}Fr_StartupStateType;
/* !req FR510 */
typedef struct {
boolean CHIHaltRequest;
boolean ColdstartNoise;
Fr_ErrorModeType ErrorMode;
boolean Freeze;
Fr_SlotModeType SlotMode;
Fr_StartupStateType StartupState;
Fr_POCStateType State;
Fr_WakeupStatusType WakeupStatus;
/*boolean CHIReadyRequest; NOT SUPPORTED */
}Fr_POCStatusType;
/* @req FR511 */
typedef enum {
FR_TRANSMITTED = 0,
FR_NOT_TRANSMITTED
}Fr_TxLPduStatusType;
/* @req FR512 */
typedef enum {
FR_RECEIVED = 0,
FR_NOT_RECEIVED,
FR_RECEIVED_MORE_DATA_AVAILABLE
}Fr_RxLPduStatusType;
/* @req FR468 */
/* @req FR514 */
typedef enum {
FR_CHANNEL_A = 0,
FR_CHANNEL_B,
FR_CHANNEL_AB
}Fr_ChannelType;
/* @req FrTrcv434 */
typedef enum {
FRTRCV_TRCVMODE_NORMAL,
FRTRCV_TRCVMODE_STANDBY,
FRTRCV_TRCVMODE_SLEEP, // sleep is optional.
FRTRCV_TRCVMODE_RECEIVEONLY // receive only is optional.
}FrTrcv_TrcvModeType;
/* @req FrTrcv435 */
/* @req FrTrcv074 */
typedef enum {
FRTRCV_WU_NOT_SUPPORTED,
FRTRCV_WU_BY_BUS,
FRTRCV_WU_BY_PIN,
FRTRCV_WU_INTERNALLY,
FRTRCV_WU_RESET,
FRTRCV_WU_POWER_ON
}FrTrcv_TrcvWUReasonType;
#if 0
typedef struct {
//Implementation specific
//This type contains the implementation-specific post build time configuration structure.
//Only pointers of this type are allowed.
}FrIf_ConfigType;
#endif
typedef enum {
FRIF_STATE_OFFLINE,
FRIF_STATE_ONLINE
}FrIf_StateType;
typedef enum {
FRIF_GOTO_OFFLINE,
FRIF_GOTO_ONLINE
}FrIf_StateTransitionType;
typedef enum {
FR_N1SAMPLES = 0,
FR_N2SAMPLES,
FR_N4SAMPLES
}Fr_SamplePerMicroTickType;
typedef enum {
FR_T12_5NS = 0,
FR_T25NS,
FR_T50NS,
FR_T100NS,
FR_T200NS,
FR_T400NS
}Fr_MicroTickType;
/* !req FR657 - Fr_ReadCCConfig not implemented*/
/* Macro name, Value, Mapps to configuration parameter */
#define FR_CIDX_GDCYCLE (uint8)0U /* 0, FrIfGdCycle */
#define FR_CIDX_PMICROPERCYCLE (uint8)1U /* 1, FrPMicroPerCycle */
#define FR_CIDX_PDLISTENTIMEOUT (uint8)2U /* 2, FrPdListenTimeout */
#define FR_CIDX_GMACROPERCYCLE (uint8)3U /* 3, FrIfGMacroPerCycle */
#define FR_CIDX_GDMACROTICK (uint8)4U /* 4, FrIfGdMacrotick */
#define FR_CIDX_GNUMBEROFMINISLOTS (uint8)5U /* 5, FrIfGNumberOfMinislots */
#define FR_CIDX_GNUMBEROFSTATICSLOTS (uint8)6U /* 6, FrIfGNumberOfStaticSlots */
#define FR_CIDX_GDNIT (uint8)7U /* 7, FrIfGdNit */
#define FR_CIDX_GDSTATICSLOT (uint8)8U /* 8, FrIfGdStaticSlot */
#define FR_CIDX_GDWAKEUPRXWINDOW (uint8)9U /* 9, FrIfGdWakeupRxWindow */
#define FR_CIDX_PKEYSLOTID (uint8)10U /* 10, FrPKeySlotId */
#define FR_CIDX_PLATESTTX (uint8)11U /* 11, FrPLatestTx */
#define FR_CIDX_POFFSETCORRECTIONOUT (uint8)12U /* 12, FrPOffsetCorrectionOut */
#define FR_CIDX_POFFSETCORRECTIONSTART (uint8)13U /* 13, FrPOffsetCorrectionStart */
#define FR_CIDX_PRATECORRECTIONOUT (uint8)14U /* 14, FrPRateCorrectionOut */
#define FR_CIDX_PSECONDKEYSLOTID (uint8)15U /* 15, FrPSecondKeySlotId */
#define FR_CIDX_PDACCEPTEDSTARTUPRANGE (uint8)16U /* 16, FrPdAcceptedStartupRange */
#define FR_CIDX_GCOLDSTARTATTEMPTS (uint8)17U /* 17, FrIfGColdStartAttempts */
#define FR_CIDX_GCYCLECOUNTMAX (uint8)18U /* 18, FrIfGCycleCountMax */
#define FR_CIDX_GLISTENNOISE (uint8)19U /* 19, FrIfGListenNoise */
#define FR_CIDX_GMAXWITHOUTCLOCKCORRECTFATAL (uint8)20U /* 20, FrIfGMaxWithoutClockCorrectFatal */
#define FR_CIDX_GMAXWITHOUTCLOCKCORRECTPASSIVE (uint8)21U /* 21, FrIfGMaxWithoutClockCorrectPassive */
#define FR_CIDX_GNETWORKMANAGEMENTVECTORLENGTH (uint8)22U /* 22, FrIfGNetworkManagementVectorLength */
#define FR_CIDX_GPAYLOADLENGTHSTATIC (uint8)23U /* 23, FrIfGPayloadLengthStatic */
#define FR_CIDX_GSYNCFRAMEIDCOUNTMAX (uint8)24U /* 24, FrIfGSyncFrameIDCountMax */
#define FR_CIDX_GDACTIONPOINTOFFSET (uint8)25U /* 25, FrIfGdActionPointOffset */
#define FR_CIDX_GDBIT (uint8)26U /* 26, FrIfGdBit */
#define FR_CIDX_GDCASRXLOWMAX (uint8)27U /* 27, FrIfGdCasRxLowMax */
#define FR_CIDX_GDDYNAMICSLOTIDLEPHASE (uint8)28U /* 28, FrIfGdDynamicSlotIdlePhase */
#define FR_CIDX_GDMINISLOTACTIONPOINTOFFSET (uint8)29U /* 29, FrIfGdMiniSlotActionPointOffset */
#define FR_CIDX_GDMINISLOT (uint8)30U /* 30, FrIfGdMinislot */
#define FR_CIDX_GDSAMPLECLOCKPERIOD (uint8)31U /* 31, FrIfGdSampleClockPeriod */
#define FR_CIDX_GDSYMBOLWINDOW (uint8)32U /* 32, FrIfGdSymbolWindow */
#define FR_CIDX_GDSYMBOLWINDOWACTIONPOINTOFFSET (uint8)33U /* 33, FrIfGdSymbolWindowActionPointOffset */
#define FR_CIDX_GDTSSTRANSMITTER (uint8)34U /* 34, FrIfGdTssTransmitter */
#define FR_CIDX_GDWAKEUPRXIDLE (uint8)35U /* 35, FrIfGdWakeupRxIdle */
#define FR_CIDX_GDWAKEUPRXLOW (uint8)36U /* 36, FrIfGdWakeupRxLow */
#define FR_CIDX_GDWAKEUPTXACTIVE (uint8)37U /* 37, FrIfGdWakeupTxActive */
#define FR_CIDX_GDWAKEUPTXIDLE (uint8)38U /* 38, FrIfGdWakeupTxIdle */
#define FR_CIDX_PALLOWPASSIVETOACTIVE (uint8)39U /* 39, FrPAllowPassiveToActive */
#define FR_CIDX_PCHANNELS (uint8)40U /* 40, FrPChannels */
#define FR_CIDX_PCLUSTERDRIFTDAMPING (uint8)41U /* 41, FrPClusterDriftDamping */
#define FR_CIDX_PDECODINGCORRECTION (uint8)42U /* 42, FrPDecodingCorrection */
#define FR_CIDX_PDELAYCOMPENSATIONA (uint8)43U /* 43, FrPDelayCompensationA */
#define FR_CIDX_PDELAYCOMPENSATIONB (uint8)44U /* 44, FrPDelayCompensationB */
#define FR_CIDX_PMACROINITIALOFFSETA (uint8)45U /* 45, FrPMacroInitialOffsetA */
#define FR_CIDX_PMACROINITIALOFFSETB (uint8)46U /* 46, FrPMacroInitialOffsetB */
#define FR_CIDX_PMICROINITIALOFFSETA (uint8)47U /* 47, FrPMicroInitialOffsetA */
#define FR_CIDX_PMICROINITIALOFFSETB (uint8)48U /* 48, FrPMicroInitialOffsetB */
#define FR_CIDX_PPAYLOADLENGTHDYNMAX (uint8)49U /* 49, FrPPayloadLengthDynMax */
#define FR_CIDX_PSAMPLESPERMICROTICK (uint8)50U /* 50, FrPSamplesPerMicrotick */
#define FR_CIDX_PWAKEUPCHANNEL (uint8)51U /* 51, FrPWakeupChannel */
#define FR_CIDX_PWAKEUPPATTERN (uint8)52U /* 52, FrPWakeupPattern */
#define FR_CIDX_PDMICROTICK (uint8)53U /* 53, FrPdMicrotick */
#define FR_CIDX_GDIGNOREAFTERTX (uint8)54U /* 54, FrIfGdIgnoreAfterTx */
#define FR_CIDX_PALLOWHALTDUETOCLOCK (uint8)55U /* 55, FrPAllowHaltDueToClock */
#define FR_CIDX_PEXTERNALSYNC (uint8)56U /* 56, FrPExternalSync */
#define FR_CIDX_PFALLBACKINTERNAL (uint8)57U /* 57, FrPFallBackInternal */
#define FR_CIDX_PKEYSLOTONLYENABLED (uint8)58U /* 58, FrPKeySlotOnlyEnabled */
#define FR_CIDX_PKEYSLOTUSEDFORSTARTUP (uint8)59U /* 59, FrPKeySlotUsedForStartup */
#define FR_CIDX_PKEYSLOTUSEDFORSYNC (uint8)60U /* 60, FrPKeySlotUsedForSync */
#define FR_CIDX_PNMVECTOREARLYUPDATE (uint8)61U /* 61, FrPNmVectorEarlyUpdate */
#define FR_CIDX_PTWOKEYSLOTMODE (uint8)62U /* 62, FrPTwoKeySlotMode */
// Controller configuration
typedef struct {
uint32 FrCtrlIdx;
boolean FrPAllowHaltDueToClock;
uint32 FrPAllowPassiveToActive;
Fr_ChannelType FrPChannels;
uint32 FrPClusterDriftDamping;
uint32 FrPDecodingCorrection;
uint32 FrPDelayCompensationA;
uint32 FrPDelayCompensationB;
boolean FrPExternalSync;
boolean FrPFallBackInternal;
uint32 FrPKeySlotId;
boolean FrPKeySlotOnlyEnabled; /* Maps to 2.1 pSingleSlotEnabled */
boolean FrPKeySlotUsedForStartup;
boolean FrPKeySlotUsedForSync;
uint32 FrPLatestTx;
uint32 FrPMacroInitialOffsetA;
uint32 FrPMacroInitialOffsetB;
uint32 FrPMicroInitialOffsetA;
uint32 FrPMicroInitialOffsetB;
uint32 FrPMicroPerCycle;
uint32 FrPNmVectorEarlyUpdate;
uint32 FrPOffsetCorrectionOut;
uint32 FrPOffsetCorrectionStart;
uint32 FrPPayloadLengthDynMax;
uint32 FrPRateCorrectionOut;
Fr_SamplePerMicroTickType FrPSamplesPerMicrotick;
uint32 FrPSecondKeySlotId;
boolean FrPTwoKeySlotMode;
Fr_ChannelType FrPWakeupChannel;
uint32 FrPWakeupPattern;
uint32 FrPdAcceptedStartupRange;
uint32 FrPdListenTimeout;
Fr_MicroTickType FrPdMicrotick;
uint8 FrArcAbsTimerMaxIdx;
#if defined(USE_DEM) || defined(CFG_FR_DEM_TEST)
Dem_EventIdType FrDemEventParamRef;
#endif
//FrFifo -- Not supported yet
}Fr_CtrlConfigParametersType;
typedef struct {
uint32 FrTrigObjectId;
boolean FrTrigAllowDynamicLen;
boolean FrTrigAlwaysTransmit;
uint32 FrTrigBaseCycle;
Fr_ChannelType FrTrigChannel;
uint32 FrTrigCycleRepetition;
boolean FrTrigPayloadPreamble;
uint32 FrTrigSlotId;
uint32 FrTrigLSduLength;
uint32 FrTrigIsTx;
#if defined(USE_DEM) || defined(CFG_FR_DEM_TEST)
Dem_EventIdType FrTrigDemFTSlotStatusRef;
#endif
}Fr_FrIfTriggeringConfType;
typedef struct {
uint16 FrMsgBufferIdx;
uint32 FrDataPartitionAddr;
uint32 FrCurrentLengthSetup;
}Fr_MessageBufferConfigType;
typedef struct {
uint32 FrNbrTrigConfiged;
uint32 FrNbrTrigStatic;
const Fr_FrIfTriggeringConfType *FrTrigConfPtr;
Fr_MessageBufferConfigType *FrMsgBufferCfg;
}Fr_FrIfCCTriggeringType;
typedef struct {
boolean FrLpdIsReconf;
uint32 FrLpdTriggIdx;
}Fr_FrIfLPduType;
typedef struct {
const uint16 FrNbrLPdusConfigured;
const Fr_FrIfLPduType *FrLpdu;
}Fr_FrIfLPduContainerType;
typedef struct {
uint32 FrClusterGColdStartAttempts;
uint32 FrClusterGListenNoise;
uint32 FrClusterGMaxWithoutClockCorrectPassive;
uint32 FrClusterGMaxWithoutClockCorrectFatal;
uint32 FrClusterGNetworkManagementVectorLength;
uint32 FrClusterGdTSSTransmitter;
uint32 FrClusterGdCasRxLowMax;
Fr_MicroTickType FrClusterGdSampleClockPeriod;
uint32 FrClusterGdSymbolWindow;
uint32 FrClusterGdWakeupRxIdle;
uint32 FrClusterGdWakeupRxLow;
uint32 FrClusterGdWakeupTxIdle;
uint32 FrClusterGdWakeupTxActive; /* Maps to 2.1 gdWakeupSymbolTxLow */
uint32 FrClusterGPayloadLengthStatic;
uint32 FrClusterGMacroPerCycle;
uint32 FrClusterGSyncFrameIDCountMax; /* Maps to 2.1 gSyncNodeMax */
uint32 FrClusterGdNit;
uint32 FrClusterGdStaticSlot;
uint32 FrClusterGNumberOfStaticSlots;
uint32 FrClusterGdMiniSlotActionPointOffset;
uint32 FrClusterGNumberOfMinislots;
uint32 FrClusterGdActionPointOffset;
uint32 FrClusterGdDynamicSlotIdlePhase;
uint32 FrClusterGdMinislot;
uint8 FrClusterGCycleCountMax;
Fr_MicroTickType FrClusterGdBit;
float32 FrClusterGdCycle;
uint32 FrClusterGdIgnoreAfterTx;
float32 FrClusterGdMacrotick;
uint32 FrClusterGdSymbolWindowActionPointOffset;
uint32 FrClusterGdWakeupRxWindow;
}Fr_FrIfClusterConfigType;
#endif /*FR_GENERAL_TYPES*/
|
2301_81045437/classic-platform
|
include/Fr_GeneralTypes.h
|
C
|
unknown
| 14,358
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef GPT_CONFIGTYPES_H
#define GPT_CONFIGTYPES_H
typedef void (*GptNotificationType)( void );
typedef struct {
Gpt_ChannelType GptChannelId;
Gpt_ChannelMode GptChannelMode;
GptNotificationType GptNotification;
uint8 GptNotificationPriority;
uint32 GptChannelPrescale;
#if defined(CFG_ZYNQ) || defined(CFG_RH850) || defined(CFG_TMS570) || defined(CFG_JAC5) || defined(CFG_JAC5E) || defined(CFG_JAC6)
boolean GptEnableWakeup;
#endif
#if (GPT_REPORT_WAKEUP_SOURCE == STD_ON)
EcuM_WakeupSourceType GptWakeupSource;
#endif
} Gpt_ConfigType;
#endif /* GPT_CONFIGTYPES_H */
|
2301_81045437/classic-platform
|
include/Gpt_ConfigTypes.h
|
C
|
unknown
| 1,381
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @tagSettings DEFAULT_ARCHITECTURE=JACINTO6 */
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2 */
#ifndef I2C_H_
#define I2C_H_
#include "I2c_Cfg.h"
#define I2C_VENDOR_ID 60u
#define I2C_MODULE_ID 81u
#define I2C_AR_MAJOR_VERSION 1u
#define I2C_AR_MINOR_VERSION 1u
#define I2C_AR_PATCH_VERSION 1u
#define I2C_SW_MAJOR_VERSION 1u
#define I2C_SW_MINOR_VERSION 2u
#define I2C_SW_PATCH_VERSION 0u
/* @req SWS_I2c_00014 */
/* Service IDs */
enum
{
I2C_SERVICE_ID_INIT = 1,
I2C_SERVICE_ID_GETVERSION,
I2C_SERVICE_ID_WRITE,
I2C_SERVICE_ID_READ,
I2C_SERVICE_ID_MAIN
};
/* Development Errors */
enum
{
I2C_E_NO = 0, /* no error detected */
I2C_E_UNINIT, /* An API function was called while the module was uninitialized */
I2C_E_PARAM, /* A parameter given to the API function was invalid.*/
I2C_E_PARAM_POINTER, /* NULL pointer has been passed as an argument. */
I2C_E_CHANNEL_UNAVAILABLE, /* An operation was requested on a channel that does not exist. */
I2C_E_TIMEOUT /* An I2C message could not be finalized due to a communication timeout. */
};
enum
{
I2C_JOB_STATE_READY,
I2C_JOB_STATE_START,
I2C_JOB_STATE_TRANSMIT_REGISTER,
I2C_JOB_STATE_TRANSMIT_DATA,
I2C_JOB_STATE_RECEIVE_DATA,
I2C_JOB_STATE_FINISHED,
I2C_JOB_STATE_ERROR,
I2C_JOB_STATE_TIMEOUT,
I2C_JOB_STATE_NONE
};
/* Function Prototypes */
/**
* Initializes the I2c Driver
* Service ID[hex]: 0x01
* @param ConfigPtr - Pointer to configuration set
*/
void I2c_Init(const I2c_ConfigType* ConfigPtr);
/**
* Returns the version information of this module.
* Service ID[hex]: 0x02
* @param versioninfo - Pointer to where to store the version information of this module
*/
#if (I2C_VERSION_INFO_API == STD_ON)
void I2c_GetVersionInfo(Std_VersionInfoType* versioninfo);
#endif
/**
* Writing of data to a destination register on the specified I2C channel.
* Service ID[hex]: 0x03
* @param channel - A handle to a valid I2cChannel instance
* @param reg - Destination register in the slave ECU.
* @param registerSize - address size of destination register (8 bit, 16 bit, etc.)
* @param data - source data to be transmitted to slave
* @param length - number of bytes to be written to destination
* @param requestHandle -
* request handle assigned to this request by I2c.
The same handle will be used within JobEndNotification, so that
the user can match the notification with the previous request.
* @return - E_OK: Write job successfully issued.
E_NOT_OK: I2c didn't accept write request, e.g. channel queue is full.
*/
Std_ReturnType I2c_Write(I2c_ChannelHandleType channel,
uint32 reg,
I2c_AddressSizeType registerSize,
const uint8* data,
uint16 length,
uint16* requestHandle);
/**
* Reading of data from a source register on the specified I2C channel.
* Service ID[hex]: 0x04
* @param channel - A handle to a valid I2cChannel instance
* @param reg - Source register to be read in the slave ECU.
* @param registerSize - address size of source register (8 bit, 16 bit, etc.)
* @param data - pointer to destination buffer for data read from slave
* @param length - number of bytes to be read from slave
* @param requestHandle - request handle assigned to this request by I2c.
The same handle will be used within JobEndNotification, so that
the user can match the notification with the previous request.
* @return - E_OK: Write job successfully issued.
E_NOT_OK: I2c didn't accept write request, e.g. channel queue is full.
*/
Std_ReturnType I2c_Read(I2c_ChannelHandleType channel,
uint32 reg,
I2c_AddressSizeType registerSize,
uint8* data,
uint16 length,
uint16* requestHandle);
/**
* Main function of the I2c module. May be used for scheduling and monitoring
* I2c message transfer and timeout supervision.
* Service ID[hex]: 0x05
*/
void I2c_MainFunction(void);
/* @req SWS_I2c_00012 */
/**
* This callback notifies the I2c user on the completion of a previously issued job.
* @param result - Status of job execution:
* E_OK: Job executed successfully
* E_NOT_OK: An error occurred during job execution
* @param requestHandle - request handle, identifies the previous request being notified.
*/
void User_I2cJobEndNotification(Std_ReturnType result, uint16 requestHandle);
/**
* This function returns the actual job state
* @return - Status of job
* I2C_JOB_STATE_NONE: No job was ever started
* I2C_JOB_STATE_START: A job is started
* I2C_JOB_STATE_TRANSMIT_REGISTER: A job is transmitting register data
* I2C_JOB_STATE_TRANSMIT_DATA: A job is transmitting data
* I2C_JOB_STATE_RECEIVE_DATA: A job ist receiving data
* I2C_JOB_STATE_READY: Job executed successfully or ready for the next transfer *
*/
uint8 I2c_GetActualJobState(I2c_ChannelHandleType channel);
/**
* This function is required to be configured for a callback upon timeout of configured timer / GPT
* @return - void
*/
void I2c_JobTimeoutNotification(void);
#endif /* I2C_H_ */
|
2301_81045437/classic-platform
|
include/I2c.h
|
C
|
unknown
| 6,734
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef I2C_MEMMAP_H_
#define I2C_MEMMAP_H_
#endif /* I2C_MEMMAP_H_ */
|
2301_81045437/classic-platform
|
include/I2c_MemMap.h
|
C
|
unknown
| 828
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ICU_INTERNAL_H_
#define ICU_INTERNAL_H_
#define ICU_ISR_PRIORITY 4
#if defined(CFG_MPC5645S)
#define ICU_NUMBER_OF_EACH_EMIOS 24
#define ICU_MAX_CHANNEL 48
// EMIOS UC modes of operation (UC Channel CCR.B.MODE register setting)
#define EMIOS_UC_MODE_SAIC 0x02 /* 0b0000010 */
#define EMIOS_UC_MODE_MCB_UP 0x50 /* 0b1010000 */
#define EMIOS_UC_MODE_MCB_UP_DOWN 0x54 /* 0b1010100 */
#elif defined(CFG_MPC5746C)
#define ICU_NUMBER_OF_EACH_EMIOS 32
#define ICU_MAX_CHANNEL 64
// EMIOS UC modes of operation (UC Channel CCR.B.MODE register setting)
// EMIOS UC modes of operation (UC Channel EMIOSC.B.MODE register setting)
#define EMIOS_UC_MODE_SAIC 0x02 /* 0b0000010 */
#define EMIOS_UC_MODE_IPWM 0x04 /* 0b0000100 */
#define EMIOS_UC_MODE_IPM 0x05 /* 0b0000101 */
#define EMIOS_UC_MODE_MCB_UP 0x50 /* 0b1010000 */
#define EMIOS_UC_MODE_MCB_UP_DOWN 0x54 /* 0b1010100 */
#elif defined(CFG_MPC5748G)
#define ICU_NUMBER_OF_EACH_EMIOS 32
#define ICU_MAX_CHANNEL 96
// EMIOS UC modes of operation (UC Channel CCR.B.MODE register setting)
// EMIOS UC modes of operation (UC Channel EMIOSC.B.MODE register setting)
#define EMIOS_UC_MODE_SAIC 0x02 /* 0b0000010 */
#define EMIOS_UC_MODE_IPWM 0x04 /* 0b0000100 */
#define EMIOS_UC_MODE_IPM 0x05 /* 0b0000101 */
#define EMIOS_UC_MODE_MCB_UP 0x50 /* 0b1010000 */
#define EMIOS_UC_MODE_MCB_UP_DOWN 0x54 /* 0b1010100 */
#elif defined(CFG_MPC5606B) || defined(CFG_SPC560B54) || defined(CFG_MPC5646B)
#define ICU_NUMBER_OF_EACH_EMIOS 32
#define ICU_MAX_CHANNEL 64
// EMIOS UC modes of operation (UC Channel EMIOSC.B.MODE register setting)
#define EMIOS_UC_MODE_SAIC 0x02 /* 0b0000010 Single Action Input Capture */
#define EMIOS_UC_MODE_IPWM 0x04 /* 0b0000100 Input Pulse Width Measurement */
#define EMIOS_UC_MODE_IPM 0x05 /* 0b0000101 Input Period Measurement */
#define EMIOS_UC_MODE_MCB_UP 0x50 /* 0b1010000 Modulus Counter Buffered (Up counter) */
#define EMIOS_UC_MODE_MCB_UP_DOWN 0x54 /* 0b1010100 Modulus Counter Buffered (Up/Down counter) */
#elif defined(CFG_ZYNQ)
#define ICU_MAX_CHANNEL 118
#elif defined(CFG_MPC5606S) /*MPC5606S does not support IPM and IPWM mode*/
#define ICU_NUMBER_OF_EACH_EMIOS 32
#define ICU_MAX_CHANNEL 56
#define EMIOS_UC_MODE_SAIC 0x02 /* 0b0000010 */
#endif
/*
* Setting to ON freezes the current register state of a ICU channel when in
* debug mode.
*/
#define ICU_FREEZE_ENABLE STD_ON
#endif /* ICU_INTERNAL_H_ */
|
2301_81045437/classic-platform
|
include/Icu_Internal.h
|
C
|
unknown
| 3,372
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.3.0 */
/*lint -e451 -e9021 AUTOSAR API SWS_MemMap_00003 */
#define IOHWAB_MEMMAP_ERROR
#ifdef IOHWAB_START_SEC_VAR_INIT_UNSPECIFIED
#include "MemMap.h" /*lint !e451 !e9019 MISRA:STANDARDIZED_INTERFACE:AUTOSAR Require Inclusion:[MISRA 2012 Directive 4.10, required] [MISRA 2012 Rule 20.1, advisory] */
#undef IOHWAB_MEMMAP_ERROR
#undef IOHWAB_START_SEC_VAR_INIT_UNSPECIFIED
#endif
#ifdef IOHWAB_STOP_SEC_VAR_INIT_UNSPECIFIED
#include "MemMap.h" /*lint !e451 !e9019 MISRA:STANDARDIZED_INTERFACE:AUTOSAR Require Inclusion:[MISRA 2012 Directive 4.10, required] [MISRA 2012 Rule 20.1, advisory] */
#undef IOHWAB_MEMMAP_ERROR
#undef IOHWAB_STOP_SEC_VAR_INIT_UNSPECIFIED
#endif
#ifdef IOHWAB_START_SEC_VAR_CLEARED_UNSPECIFIED
#include "MemMap.h" /*lint !e451 !e9019 MISRA:STANDARDIZED_INTERFACE:AUTOSAR Require Inclusion:[MISRA 2012 Directive 4.10, required] [MISRA 2012 Rule 20.1, advisory] */
#undef IOHWAB_MEMMAP_ERROR
#undef IOHWAB_START_SEC_VAR_CLEARED_UNSPECIFIED
#endif
#ifdef IOHWAB_STOP_SEC_VAR_CLEARED_UNSPECIFIED
#include "MemMap.h" /*lint !e451 !e9019 MISRA:STANDARDIZED_INTERFACE:AUTOSAR Require Inclusion:[MISRA 2012 Directive 4.10, required] [MISRA 2012 Rule 20.1, advisory] */
#undef IOHWAB_MEMMAP_ERROR
#undef IOHWAB_STOP_SEC_VAR_CLEARED_UNSPECIFIED
#endif
#ifdef IOHWAB_MEMMAP_ERROR
#error "EcuM_BswMemMap.h error, section not mapped"
#endif
|
2301_81045437/classic-platform
|
include/IoHwAb_BswMemMap.h
|
C
|
unknown
| 2,204
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2 */
/** @tagSettings DEFAULT_ARCHITECTURE=ZYNQ|MPC5607B|MPC5645S|PPC|MPC5748G */
#ifndef LIN_CONFIGTYPES_H
#define LIN_CONFIGTYPES_H
#include "Std_Types.h"
#include "Mcu.h"
/* ERRATA for REV_A of 551x chip. Uncomment to include.
* Will use a GPT timer for timeout handling */
//#define MPC551X_ERRATA_REV_A
typedef struct
{
/* Switches the Development Error Detection and Notification
ON or OFF. */
boolean LinDevErrorDetect;
/* Specifies the InstanceId of this module instance. If only one
instance is present it shall have the Id 0. */
uint8 LinIndex;
/* Specifies the maximum number of loops for blocking function
* until a timeout is raised in short term wait loops */
uint16 LinTimeoutDuration;
/* Switches the Lin_GetVersionInfo function ON or OFF. */
boolean LinVersionInfoApi;
}
Lin_GeneralType;
typedef struct
{
/* Specifies the baud rate of the LIN channel */
uint16 LinChannelBaudRate;
/* Specifies if the LIN hardware channel supports wake up functionality */
boolean LinChannelWakeUpSupport;
/* Specifies the LIN channel id */
uint8 LinChannelId;
/* This parameter contains a reference to the Wakeup Source
* for this controller as defined in the ECU State Manager.
* Implementation Type: reference to EcuM_WakeupSourceType */
uint32 LinChannelEcuMWakeUpSource;
boolean LinChannelEcuWakeUpDefined;
#if defined(CFG_PPC)
/* Reference to the LIN clock source configuration, which is set
* in the MCU driver configuration.*/
uint32 LinClockRef;
#endif
#if defined(CFG_JAC6)
/* jACINTO6 uses Lin over uart and requiers a Uart Channel */
uint8 LinUartChannelId;
#endif
#ifdef MPC551X_ERRATA_REV_A
/* Errata forces us to use a Gpt channel for timouts */
uint8 LinTimeOutGptChannelId;
#endif
}
Lin_ChannelConfigType;
/* This is the type of the external data structure containing the overall
* initialization data for the LIN driver and SFR settings affecting all
* LIN channels. A pointer to such a structure is provided to the LIN driver
* initialization routine for configuration of the driver and LIN hardware unit. */
/* @req SWS_Lin_00227 */
typedef struct {
const Lin_ChannelConfigType *LinChannelConfig;
const uint8 *Lin_HwId2ChannelMap;
} Lin_ConfigType;
#endif
|
2301_81045437/classic-platform
|
include/Lin_ConfigTypes.h
|
C
|
unknown
| 3,218
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2 */
/** @tagSettings DEFAULT_ARCHITECTURE=PPC|TMS570|MPC5645S|MPC5607B|ZYNQ|JACINTO6|MPC5748G */
/** @req 4.1.2|4.3.0/SWS_Lin_00245 The content of Lin_GeneralTypes.h shall be protected by a LIN_GENERAL_TYPES define. */
#ifndef LIN_GENERAL_TYPES
#define LIN_GENERAL_TYPES
/** @req 4.1.2|4.3.0/SWS_Lin_00242 The types Lin_PduType and Lin_StatusType used by LIN driver shall be declared in Lin_GeneralTypes.h . */
/** @req 4.1.2|4.3.0/SWS_Lin_00228 Lin_FramePidType*/
/** Represents all valid protected Identifier used by Lin_SendFrame(). */
typedef uint8 Lin_FramePidType;
/** @req 4.1.2|4.3.0/SWS_Lin_00229 Lin_FrameCsModelType */
/** This type is used to specify the Checksum model to be used for the LIN Frame. */
typedef enum {
LIN_ENHANCED_CS,
LIN_CLASSIC_CS,
} Lin_FrameCsModelType;
/** @req 4.1.2|4.3.0/SWS_Lin_00230 Lin_FrameResponseType */
/** This type is used to specify whether the frame processor is required to transmit the
* response part of the LIN frame. */
typedef enum {
/** Response is generated from this (master) node */
LIN_MASTER_RESPONSE=0,
/** Response is generated from a remote slave node */
LIN_SLAVE_RESPONSE,
/** Response is generated from one slave to another slave,
* for the master the response will be anonymous, it does not
* have to receive the response. */
LIN_SLAVE_TO_SLAVE,
} Lin_FrameResponseType;
/** This type is used to specify the number of SDU data bytes to copy. */
/** @req 4.1.2|4.3.0/SWS_Lin_00231 Lin_FrameDlType */
typedef uint8 Lin_FrameDIType;
/** @req 4.1.2|4.3.0/SWS_Lin_00232 Lin_PduType */
/** This Type is used to provide PID, checksum model, data length and SDU pointer
* from the LIN Interface to the LIN driver. */
typedef struct {
Lin_FrameCsModelType Cs;
Lin_FramePidType Pid;
uint8* SduPtr;
Lin_FrameDIType Dl;
Lin_FrameResponseType Drc;
} Lin_PduType;
/** @req 4.1.2|4.3.0/SWS_Lin_00233 Lin_StatusType */
typedef enum {
/** LIN frame operation return value.
* Development or production error occurred */
LIN_NOT_OK,
/** LIN frame operation return value.
* Successful transmission. */
LIN_TX_OK,
/** LIN frame operation return value.
* Ongoing transmission (Header or Response). */
LIN_TX_BUSY,
/** LIN frame operation return value.
* Erroneous header transmission such as:
* - Mismatch between sent and read back data
* - Identifier parity error or
* - Physical bus error */
LIN_TX_HEADER_ERROR,
/** LIN frame operation return value.
* Erroneous response transmission such as:
* - Mismatch between sent and read back data
* - Physical bus error */
LIN_TX_ERROR,
/** LIN frame operation return value.
* Reception of correct response. */
LIN_RX_OK,
/** LIN frame operation return value. Ongoing reception: at
* least one response byte has been received, but the
* checksum byte has not been received. */
LIN_RX_BUSY,
/** LIN frame operation return value.
* Erroneous response reception such as:
* - Framing error
* - Overrun error
* - Checksum error or
* - Short response */
LIN_RX_ERROR,
/** LIN frame operation return value.
* No response byte has been received so far. */
LIN_RX_NO_RESPONSE,
/** LIN channel state return value.
* LIN channel not initialized. */
LIN_CH_UNINIT,
/** LIN channel state return value.
* Normal operation; the related LIN channel is ready to
* transmit next header. No data from previous frame
* available (e.g. after initialization) */
LIN_OPERATIONAL,
/** LIN channel state return value.
* Sleep mode operation; in this mode wake-up detection
* from slave nodes is enabled. */
LIN_CH_SLEEP,
/** LIN channel state when LinGoToSleep is requested */
LIN_CH_SLEEP_PENDING
} Lin_StatusType;
typedef enum {
LINTRCV_TRCV_MODE_NORMAL,
LINTRCV_TRCV_MODE_STANDBY,
LINTRCV_TRCV_MODE_SLEEP
}LinTrcv_TrcvModeType;
#endif /* LIN_GENERAL_TYPES */
|
2301_81045437/classic-platform
|
include/Lin_GeneralTypes.h
|
C
|
unknown
| 5,016
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef LIN_TYPES_H_
#define LIN_TYPES_H_
#include "Std_Types.h"
#endif
|
2301_81045437/classic-platform
|
include/Lin_Types.h
|
C
|
unknown
| 849
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef NMSTACK_TYPES_H_
#define NMSTACK_TYPES_H_
/** Return type for NM functions. Derived from Std_ReturnType. */
typedef enum {
NM_E_OK,
NM_E_NOT_OK,
NM_E_NOT_EXECUTED
} Nm_ReturnType;
/** Operational modes of the network management */
typedef enum {
NM_MODE_BUS_SLEEP,
NM_MODE_PREPARE_BUS_SLEEP,
NM_MODE_SYNCHRONIZE,
NM_MODE_NETWORK
} Nm_ModeType;
/** States of the network management state machine */
typedef enum {
NM_STATE_UNINIT,
NM_STATE_BUS_SLEEP,
NM_STATE_PREPARE_BUS_SLEEP,
NM_STATE_READY_SLEEP,
NM_STATE_NORMAL_OPERATION,
NM_STATE_REPEAT_MESSAGE,
NM_STATE_SYNCHRONIZE
} Nm_StateType;
/** BusNm Type */
typedef enum {
NM_BUSNM_CANNM = 0,
NM_BUSNM_FRNM = 1,
NM_BUSNM_LINNM = 2,
NM_BUSNM_UDPNM = 3,
NM_BUSNM_OSEKNM = 4,
NM_BUSNM_UNDEF = 0xFF
} Nm_BusNmType;
#endif /* NMSTACK_TYPES_H_ */
|
2301_81045437/classic-platform
|
include/NmStack_Types.h
|
C
|
unknown
| 1,684
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef OCU_INTERNAL_H_
#define OCU_INTERNAL_H_
#include "mpc55xx.h"
typedef volatile struct EMIOS_tag emios_t;
#if defined (CFG_MPC5645S)
#define CHANNELS_PER_EMIOS_UNIT 24u
#elif defined (CFG_MPC5606B) || defined(CFG_SPC560B54)
#define CHANNELS_PER_EMIOS_UNIT 32u
#endif
#define MCB_CHANNEL_MODE 0x50u
#define SAOC_CHANNEL_MODE 3u
#define GPIO_OUTPUT_CHANNEL_MODE 1u
#define GPIO_INPUT_CHANNEL_MODE 0u
#define SELECT_C_D_COUNTER_BUS 1u
#define SELECT_INTERNAL_COUNTER 3u
#define SET_OUTPUT_FF_HIGH 1u
#define SET_OUTPUT_FF_LOW 0u
#define DISABLE_EDSEL 0u
#define ENABLE_EDSEL_OUTPUT_TOGGLE 1u
#define UNIFIED_CHANNEL_D 16u
#define UNIFIED_CHANNEL_C 8u
#define OCU_FREEZE_ENABLE 1u
#define OCU_PRESCALER_ENABLE 1u
#define OCU_PRESCALER_DISABLE 0u
#define OCU_INTERRUPT_ENABLE 1u
#define OCU_INTERRUPT_DISABLE 0u
#define INVALID_COUNTERVALUE 0xFFFFu
#define GET_EMIOS_UNIT(_chnExp) (((_chnExp) > 0) ? &EMIOS_1 : &EMIOS_0)
#define EMIOS_UNITS 2
#define GET_EMIOS_CHANNEL(_ch) ((_ch)%CHANNELS_PER_EMIOS_UNIT)
#ifdef HOST_TEST
/*lint -esym(9003, Ocu_enablDelayGlobalVariable) Used by test framework */
extern boolean Ocu_enablDelayGlobalVariable;
#endif
/*lint -esym(9003, OcuConfigPtr) Global configuration pointer */
extern const Ocu_ConfigType * OcuConfigPtr;
#if (OCU_NOTIFICATION_SUPPORTED == STD_ON)
void Ocu_Arc_InstallInterrupts (void);
#endif
#endif /*OCU_INTERNAL_H_ */
|
2301_81045437/classic-platform
|
include/Ocu_Internal.h
|
C
|
unknown
| 2,331
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef OCU_MEMMAP_H_
#define OCU_MEMMAP_H_
#endif /*OCU_MEMMAP_H_ */
|
2301_81045437/classic-platform
|
include/Ocu_MemMap.h
|
C
|
unknown
| 827
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef PDUR_DOIP_H_
#define PDUR_DOIP_H_
void PduR_DoIPTpRxIndication(PduIdType id, NotifResultType result);
BufReq_ReturnType PduR_DoIPTpCopyRxData(PduIdType id, PduInfoType* info, PduLengthType* bufferSizePtr);
BufReq_ReturnType PduR_DoIPTpStartOfReception(PduIdType id,const PduInfoType* info, PduLengthType TpSduLength, PduLengthType* bufferSizePtr);
BufReq_ReturnType PduR_DoIPTpCopyTxData(PduIdType id, PduInfoType* info, RetryInfoType* retry, PduLengthType* availableDataPtr);
void PduR_DoIpIfRxIndication(PduIdType pduId, PduInfoType* pduInfoPtr);
void PduR_DoIPTpTxConfirmation(PduIdType id, Std_ReturnType result);
void PduR_DoIPIfTxConfirmation(PduIdType id, Std_ReturnType result);
#endif /* PDUR_DOIP_H_ */
|
2301_81045437/classic-platform
|
include/PduR_DoIP.h
|
C
|
unknown
| 1,489
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @file Platform_Types.h
* General platform type definitions.
*/
#ifndef PLATFORM_TYPES_H
#define PLATFORM_TYPES_H
#include <stdbool.h>
#include <stdint.h>
#define CPU_TYPE CPU_TYPE_32
#define CPU_BIT_ORDER MSB_FIRST
#define HIGH_BYTE_FIRST 0U
#define LOW_BYTE_FIRST 1U
#if defined(__GNUC__)
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ /*lint !e553 handled by #error */
#define CPU_BYTE_ORDER LOW_BYTE_FIRST /* Autosar Little Endian */
#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ /*lint !e553 handled by #error */
#define CPU_BYTE_ORDER HIGH_BYTE_FIRST /* Autosar Big Endian */
#else
#error No endian defined by compiler.
#endif
#elif defined(__ghs__)
#if defined(__LITTLE_ENDIAN__)
#define CPU_BYTE_ORDER LOW_BYTE_FIRST /* Autosar Little Endian */
#elif defined(__BIG_ENDIAN__)
#define CPU_BYTE_ORDER HIGH_BYTE_FIRST /* Autosar Big Endian */
#else
#error No endian defined by compiler.
#endif
#elif defined(__CWCC__)
#if __option(little_endian)
#define CPU_BYTE_ORDER LOW_BYTE_FIRST /* Autosar Little Endian */
#else
#define CPU_BYTE_ORDER HIGH_BYTE_FIRST /* Autosar Big Endian */
#endif
/* Compiler does not have a pre-defined macro, manually set __LITTLE_ENDIAN__ or __BIG_ENDIAN__*/
#elif defined(__DCC__)
#if defined(__LITTLE_ENDIAN__)
#define CPU_BYTE_ORDER LOW_BYTE_FIRST /* Autosar Little Endian */
#elif defined(__BIG_ENDIAN__)
#define CPU_BYTE_ORDER HIGH_BYTE_FIRST /* Autosar Big Endian */
#else
#error No endian defined by compiler.
#endif
#elif defined(__ARMCC_VERSION)
#if defined(__BIG_ENDIAN)
#define CPU_BYTE_ORDER HIGH_BYTE_FIRST /* Autosar Big Endian */
#else
#define CPU_BYTE_ORDER LOW_BYTE_FIRST /* Autosar Little Endian */
#endif
#elif defined(_WIN32)
#define CPU_BYTE_ORDER LOW_BYTE_FIRST /* Autosar Little Endian */
#elif defined(__IAR_SYSTEMS_ICC__)
#if defined(__LITTLE_ENDIAN__)
#define CPU_BYTE_ORDER LOW_BYTE_FIRST /* Autosar Little Endian */
#elif defined(__BIG_ENDIAN__)
#define CPU_BYTE_ORDER HIGH_BYTE_FIRST /* Autosar Big Endian */
#else
#error No endian defined by compiler.
#endif
#else
#error Compiler not defined
#endif
#ifndef FALSE
#define FALSE 0 /*@req SWS_Platform_00026*/
#endif
#ifndef TRUE
#define TRUE 1 /*@req SWS_Platform_00026*/
#endif
/*lint -save -e138 Prevent lint error message if type definitions below cause any loops.
* Relationships may be explicitly created by lint elsewhere, to allow
* conversions between different types derived from e.g. uintxx_t and uintxx
* and others as defined below.
*/
typedef uint8_t boolean; /*@req SWS_Platform_00027*/
typedef int8_t sint8;
typedef uint8_t uint8;
typedef uint8_t utf8;
typedef char char_t;
typedef int16_t sint16;
typedef uint16_t uint16;
typedef uint16_t ucs2;
typedef int32_t sint32;
typedef uint32_t uint32;
typedef int64_t sint64;
typedef uint64_t uint64;
typedef uint_least8_t uint8_least;
typedef uint_least16_t uint16_least;
typedef uint_least32_t uint32_least;
typedef int_least8_t sint8_least;
typedef int_least16_t sint16_least;
typedef int_least32_t sint32_least;
typedef float float32;
typedef double float64;
/*lint -restore */
#endif
|
2301_81045437/classic-platform
|
include/Platform_Types.h
|
C
|
unknown
| 4,598
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RAMLOG_H_
#define RAMLOG_H_
#include <stdint.h>
#include "device_serial.h"
#include "xtoa.h"
#if !defined(USE_RAMLOG)
#define ramlog_str( _x)
#define ramlog_dec( _x)
#define ramlog_hex( _x)
#else
void ramlog_fputs( char *str );
void ramlog_puts( char *str );
void ramlog_chr( char c );
/*
* Fast ramlog functions
*/
static inline void ramlog_str( char *str ) {
ramlog_fputs(str);
}
static inline void ramlog_dec( int val ) {
char str[10]; // include '-' and \0
ultoa(val,str,10);
ramlog_str(str);
}
static inline void ramlog_hex( uint32_t val ) {
char str[10]; // include '-' and \0
ultoa(val,str,16);
ramlog_str(str);
}
#endif
/*
* var args ramlog functions
*/
#if defined(USE_RAMLOG)
int ramlog_printf(const char *format, ...);
#else
#define ramlog_printf(format,...)
#endif
void ramlog_init( void );
extern DeviceSerialType Ramlog_Device;
#endif /* RAMLOG_H_ */
|
2301_81045437/classic-platform
|
include/Ramlog.h
|
C
|
unknown
| 1,715
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @file Std_Types.h
* Definitions of General types.
*/
#ifndef STD_TYPES_H
#define STD_TYPES_H
#include "Platform_Types.h"
#include "Compiler.h"
#ifndef NULL
//lint -esym(960,20.2) // PC-Lint LINT EXCEPTION
#define NULL 0
#endif
typedef struct {
uint16 vendorID;
uint16 moduleID;
uint8 sw_major_version; /**< Vendor numbers */
uint8 sw_minor_version; /**< Vendor numbers */
uint8 sw_patch_version; /**< Vendor numbers */
} Std_VersionInfoType;
/** make compare number... #if version > 10203 ( 1.2.3 ) */
#define STD_GET_VERSION(_major,_minor,_patch) (_major * 10000 + _minor * 100 + _patch)
/** Create Std_VersionInfoType */
// PC-Lint Exception MISRA rule 19.12
//lint -save -esym(960,19.12)
#define STD_GET_VERSION_INFO(_vi,_module) \
((_vi)->vendorID = _module ## _VENDOR_ID);\
((_vi)->moduleID = _module ## _MODULE_ID);\
((_vi)->sw_major_version = _module ## _SW_MAJOR_VERSION);\
((_vi)->sw_minor_version = _module ## _SW_MINOR_VERSION);\
((_vi)->sw_patch_version = _module ## _SW_PATCH_VERSION);\
//lint -restore
#ifndef MIN
#define MIN(_x,_y) (((_x) < (_y)) ? (_x) : (_y))
#endif
#ifndef MAX
#define MAX(_x,_y) (((_x) > (_y)) ? (_x) : (_y))
#endif
typedef uint8 Std_ReturnType;
#define E_OK 0u
#define E_NOT_OK (Std_ReturnType)1u
#define E_NO_DTC_AVAILABLE (Std_ReturnType)2u
#define E_SESSION_NOT_ALLOWED (Std_ReturnType)4u
#define E_PROTOCOL_NOT_ALLOWED (Std_ReturnType)5u
#define E_REQUEST_NOT_ACCEPTED (Std_ReturnType)8u
#define E_REQUEST_ENV_NOK (Std_ReturnType)9u
#define E_PENDING (Std_ReturnType)10u
#define E_COMPARE_KEY_FAILED (Std_ReturnType)11u
#define E_FORCE_RCRRP (Std_ReturnType)12u
#define STD_HIGH 0x01u
#define STD_LOW 0x00u
#define STD_ACTIVE 0x01u
#define STD_IDLE 0x00u
#define STD_ON 0x01u
#define STD_OFF 0x00u
#endif
|
2301_81045437/classic-platform
|
include/Std_Types.h
|
C
|
unknown
| 2,685
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef TEST_CBK_
#define TEST_CBK_
#define USE_TEST_CBK 1
#if defined(USE_TEST_CBK)
#include "Can_Test.h"
#endif
#if defined(USE_TEST_CBK)
#define CANIF_TXCONFIRMATION_CALL(canTxPduId) \
CT_CanIf_TxConfirmation_Called( canTxPduId );
#define CANIF_RXINDICATION_CALL(Hrh,CanId,CanDlc,CanSduPtr) \
CT_CanIf_RxIndication_Called( Hrh, CanId, CanDlc, CanSduPtr );
#define CANIF_CANCELTXCONFIRMATION_CALL(PduInfoPtr) \
CT_CanIf_CancelTxConfirmation_Called( PduInfoPtr );
#define CANIF_CONTROLLERBUSOFF_CALL(Controller) \
CT_CanIf_ControllerBusOff_Called( Controller );
#define CANIF_CONTROLLERWAKEUP_CALL(Controller) \
CT_CanIf_ControllerWakeup_Called( Controller );
#else
#define CANIF_TXCONFIRMATION_CALL(canTxPduId)
#define CANIF_RXINDICATION_CALL(Hrh,CanId,CanDlc,CanSduPtr)
#define CANIF_CANCELTXCONFIRMATION_CALL(PduInfoPtr)
#define CANIF_CONTROLLERBUSOFF_CALL(Controller)
#define CANIF_CONTROLLERWAKEUP_CALL(Controller)
#endif
#endif /*TEST_CBK_*/
|
2301_81045437/classic-platform
|
include/Test_Cbk.h
|
C
|
unknown
| 1,782
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.3 */
/** @req 4.1.3/SWS_Xcp_00506 */ /*Provide XcpOnCan_Cfg.h - can not be tested with conventional module tests*/
#ifndef XCPONCAN_CBK_H_
#define XCPONCAN_CBK_H_
#include "ComStack_Types.h"
#include "CanIf.h"
void Xcp_CanIfRxIndication (PduIdType XcpRxPduId, PduInfoType* XcpRxPduPtr);
void Xcp_CanIfTxConfirmation (PduIdType XcpTxPduId);
#if 0
void Xcp_CanIfRxSpecial (uint8 channel, PduIdType XcpRxPduId, const uint8 * data, uint8 len, Can_IdType type);
Std_ReturnType Xcp_CanIfTriggerTransmit(PduIdType XcpTxPduId, PduInfoType* PduInfoPtr);
#endif
#endif /* XCPONCAN_CBK_H_ */
|
2301_81045437/classic-platform
|
include/XcpOnCan_Cbk.h
|
C
|
unknown
| 1,447
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.3 */
/** @req 4.1.3/SWS_Xcp_00508 */ /*Provide XcpOnEth_Cfg.h - can not be tested with conventional module tests*/
#ifndef XCPONETH_CBK_H_
#define XCPONETH_CBK_H_
#include "ComStack_Types.h"
void Xcp_SoAdIfRxIndication (PduIdType XcpRxPduId, PduInfoType* XcpRxPduPtr);
void Xcp_SoAdIfTxConfirmation (PduIdType XcpTxPduId);
#endif /* XCPONETH_CBK_H_ */
|
2301_81045437/classic-platform
|
include/XcpOnEth_Cbk.h
|
C
|
unknown
| 1,194
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ALIST_I_H_
#define ALIST_I_H_
/*
* Some macros to handle a static array and it's data.
*
*
* Usage:
* struct foo_s {
* int foo_data;
* };
*
* struct foo_s my_data[5];
*
* // Create the head
* SA_LIST_HEAD(foo,foo_s) arr_list;
* // Init the head with data.
* arr_list = SA_LIST_HEAD_INITIALIZER(5,my_data);
*
*/
/**
* @def ALIST_HEAD(name, type)
* Declare the head for the static list
*
* @param name - name of the struct
* @param type - struct type for the array
*/
#define SA_LIST_HEAD(name, type) \
struct name { \
int cnt; \
struct type *data; \
}
#define SA_LIST_HEAD_INITIALIZER(elem_cnt, data_p ) \
{ \
.cnt = (elem_cnt), \
.data = (data_p) \
}
#define SA_LIST_CNT(head) (head)->cnt
#define SA_LIST_GET( head, index ) (&(head)->data[(index)])
#define SA_LIST_FOREACH( head, ivar) for( (ivar)=0;(ivar)<SA_LIST_CNT(head);(ivar)++)
#endif /*ALIST_I_H_*/
|
2301_81045437/classic-platform
|
include/alist_i.h
|
C
|
unknown
| 1,779
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ARC_ASSERT_H_
#define ARC_ASSERT_H_
#if defined(CFG_SYSTEM_ASSERT)
#include <assert.h>
#endif
#define QUOTE__(x) #x
/*lint -save -e666 -e613 -e1776 Expression with side effects passed to repeated parameter 1 in macro 'ASSERT'*/
#if !defined(ASSERT)
#if defined(CFG_SYSTEM_ASSERT)
# define ASSERT(_x) assert(_x)
#else
# if defined(CFG_NDEBUG)
# define ASSERT(_x) ((void)0)
# else
# define ASSERT(_x) if (!(_x)) { \
Arc_Assert(QUOTE__(_x),__FILE__,__LINE__); \
}
# endif
#endif /* CFG_SYSTEM_ASSERT */
#endif
/*lint restore*/
/**
* Use this macro if you want to the check the validity of a configuration.
* This macro should also be used in the init functions.
* If you are going to check state, etc use ASSERT() instead.
*/
#if defined(CFG_CONFIG_NDEBUG)
# define CONFIG_ASSERT(_x) ((void)0)
#else
# define CONFIG_ASSERT(_x) if (!(_x)) { \
Arc_Config_Assert(QUOTE__(_x),__FILE__,__LINE__); \
}
#endif
void Arc_Assert( char *msg, const char *file, int line );
void Arc_Config_Assert( char *msg, const char *file, int line );
#endif /* ARC_ASSERT_H_ */
|
2301_81045437/classic-platform
|
include/arc_assert.h
|
C
|
unknown
| 1,993
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef CPU_H_
#define CPU_H_
#include <stdint.h>
#if defined(__ghs__)
#include "../include/arm/arm_ghs.h"
#endif
#if defined(CFG_ARMV7_M) || defined(CFG_ARMV7E_M)
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ghs__ )
#define __ASM __asm /*!< asm keyword for GHS Compiler */
#define __INLINE __inline /*!< inline keyword for GHS Compiler */
#define __STATIC_INLINE static __inline
#endif /* defined ( __CC_ARM ) */
#include "core_cmInstr.h"
static inline unsigned long _Irq_Save(void)
{
unsigned long val = __get_PRIMASK();
__disable_irq();
return val;
}
static inline void _Irq_Restore(unsigned mask) {
__set_PRIMASK(mask);
}
/**
* Initialize a system reset request to reset the MCU
*/
static __INLINE void Cpu_SystemReset(void)
{
*(uint32_t *)(0xE000ED0C) = 0x05FA0004; /* First pull system reset */
__DSB(); /* Ensure completion of memory access */
*(uint32_t *)(0xE000ED0C) = 0x05FA0001; /* If that does not work pull internal reset */
__DSB(); /* Ensure completion of memory access */
while(1) ; /* wait until reset */
}
#elif defined(CFG_ARMV7_AR)
void Cpu_EnableEccRam( void );
void Cpu_DisableEccRam( void );
#if defined(__ARMCC_VERSION)
/* ARMCC have __disable_irq and __enable_irq builtin */
#else
static inline void __disable_irq( void ) {
__asm volatile("CPSID if" ::: "memory","cc");
}
static inline void __enable_irq( void ) {
__asm volatile("CPSIE if" ::: "memory","cc");
}
#endif
#if defined(__GNUC__) || defined(__ghs__)
static inline unsigned long _Irq_Save(void)
{
unsigned long result=0;
__asm volatile ("mrs %0, cpsr" : "=r" (result) :: "memory","cc" );
__disable_irq();
return(result & 0xC0);
}
#else
static inline unsigned long _Irq_Save(void)
{
uint32_t val;
__schedule_barrier();
__asm volatile ("mrs val, cpsr");
__asm volatile ("and val, val, #0xC0"); // Mask the I and F bit of CPSR
__disable_irq();
return val;
}
#endif /* defined(__GNUC__) */
#if defined(__ARMCC_VERSION)
static inline void _Irq_Restore(unsigned mask) {
if (mask & 0x80) {
__schedule_barrier();
__asm volatile("CPSID i");
} else {
__schedule_barrier();
__asm volatile("CPSIE i");
}
if (mask & 0x40) {
__schedule_barrier();
__asm volatile("CPSID f");
} else {
__schedule_barrier();
__asm volatile("CPSIE f");
}
}
#else
static inline void _Irq_Restore(unsigned mask) {
if (mask & 0x80) {
__asm volatile("CPSID i" ::: "memory","cc");
} else {
__asm volatile("CPSIE i" ::: "memory","cc");
}
if (mask & 0x40) {
__asm volatile("CPSID f" ::: "memory","cc");
} else {
__asm volatile("CPSIE f" ::: "memory","cc");
}
}
#endif
#else
#error No arch defined
#endif
#include "Std_Types.h"
typedef uint32 imask_t;
/* Call architecture specific code */
#define Irq_Disable() __disable_irq()
#define Irq_Enable() __enable_irq()
#define Irq_Save(_flags) _flags = (imask_t)_Irq_Save();
#define Irq_Restore(_flags) _Irq_Restore(_flags);
#define Irq_SuspendAll() Irq_Disable()
#define Irq_ResumeAll() Irq_Enable()
#define Irq_SuspendOs() Irq_Disable()
#define Irq_ResumeOs() Irq_Enable()
#define CallService(index,param)
#if defined(__ARMCC_VERSION)
#define ilog2(_x) ((uint8)((32 - 1) - __builtin_clz(_x)))
static inline int ffs( uint32 val ) {
return 32 - __builtin_clz(val & (-val));
}
#elif defined(__ghs__)
#define ilog2(_x) ((uint8)((32 - 1) - __CLZ32(_x)))
#elif defined(__IAR_SYSTEMS_ICC__)
#define ilog2(_x) ((uint8)((32 - 1) - __CLZ(_x)))
#else
#define ilog2(_x) ((uint8)((32u - 1u) - __builtin_clz(_x)))
#endif
#endif /* CPU_H_ */
|
2301_81045437/classic-platform
|
include/arm/Cpu.h
|
C
|
unknown
| 6,011
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ADC_CONFIGTYPES_H_
#define ADC_CONFIGTYPES_H_
typedef uint16_t Adc_ValueGroupType;
/* Group definitions. */
typedef enum
{
INTERNAL_XADC_CALIB = 0,
INVALID_1,
INVALID_2,
INVALID_3,
INVALID_4,
INTERNAL_VCCPINT,
INTERNAL_VCCPAUX,
INTERNAL_VCC_DDR,
INTERNAL_TEMP,
INTERNAL_VCCINT,
INTERNAL_VCCAUX,
VP_VN,
INTERNAL_VREFP,
INTERNAL_VREFN,
INTERNAL_VCCBRAM,
INVALID_5,
VAUX_0,
VAUX_1,
VAUX_2,
VAUX_3,
VAUX_4,
VAUX_5,
VAUX_6,
VAUX_7,
VAUX_8,
VAUX_9,
VAUX_10,
VAUX_11,
VAUX_12,
VAUX_13,
VAUX_14,
VAUX_15,
ADC_NBR_OF_CHANNELS,
}Adc_ChannelType;
typedef enum
{
DEFAULT_FOUR_CYCLES = 0,
TEN_CYCLES
}ArcAdc_ChannelSettlingTimeType;
typedef enum
{
DEFAULT_UNIPOLAR = 0,
BIPOLAR
}ArcAdc_ChannelAnalogInputModeType;
/* Std-type, supplier defined */
// XADC peripheral supports prescaler value of 0-255.
// A prescaler value of 0, 1 or 2 will equal to a division factor of 2.
typedef uint8_t Adc_PrescaleType;
// Base address to the LOGIC IP CORE AXI interface
typedef uint32_t Adc_IpCoreBaseAddr;
typedef uint16_t Adc_StreamNumSampleType;
/* Non-standard type */
typedef struct
{
// NOT SUPPORTED Adc_ClockSourceType clockSource;
uint8_t hwUnitId;
Adc_PrescaleType adcPrescale;
Adc_IpCoreBaseAddr adcIpCorebaseAdrr;
}Adc_HWConfigurationType;
/* Std-type, supplier defined */
typedef Adc_PrescaleType Adc_ConversionTimeType;
/* Channel definitions, std container */
typedef struct
{
// NOT SUPPORTED Adc_ConversionTimeType adcChannelConvTime;
// NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcLow;
// NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcHigh;
// NOT SUPPORTED Adc_ResolutionType adcChannelResolution;
// NOT SUPPORTED Adc_CalibrationType adcChannelCalibrationEnable;
Adc_ChannelType adcChannel;
ArcAdc_ChannelSettlingTimeType adcChannelSettlingTime;
ArcAdc_ChannelAnalogInputModeType adcChannelInputMode;
} Adc_ChannelConfigurationType;
typedef struct
{
uint8 notifictionEnable;
Adc_ValueGroupType *resultBufferPtr;
Adc_StatusType groupStatus;
Adc_StreamNumSampleType currSampleCount; /* Samples per group counter. =0 until first round of conversions complete
(all channels in group). Then =1 until second round of conversions complete and so on.*/
Adc_ValueGroupType *currResultBufPtr; /* Streaming sample current buffer pointer */
} Adc_GroupStatus;
/* Std-type, supplier defined */
typedef enum
{
ADC_CONV_MODE_DISABLED,
ADC_CONV_MODE_ONESHOT = 1,
ADC_CONV_MODE_CONTINUOUS = 9,
} Adc_GroupConvModeType;
/** Not supported. */
typedef uint16_t Adc_StreamNumSampleType;
/* Implementation specific */
typedef struct
{
Adc_GroupAccessModeType accessMode;
Adc_GroupConvModeType conversionMode;
Adc_TriggerSourceType triggerSrc;
// NOT SUPPORTED Adc_HwTriggerSignalType hwTriggerSignal;
// NOT SUPPORTED Adc_HwTriggerTimerType hwTriggerTimer;
void (*groupCallback)(void);
Adc_StreamBufferModeType streamBufferMode;
Adc_StreamNumSampleType streamNumSamples;
const Adc_ChannelType *channelList;
Adc_ValueGroupType *resultBuffer;
// NOT SUPPORTED Adc_CommandType *commandBuffer;
const uint16_t numberOfChannels;
Adc_GroupStatus *status;
// NOT SUPPORTED Dma_ChannelType dmaCommandChannel;
// NOT SUPPORTED Dma_ChannelType dmaResultChannel;
// NOT SUPPORTED const struct tcd_t * groupDMACommands;
// NOT SUPPORTED const struct tcd_t * groupDMAResults;
} Adc_GroupDefType;
/* Non-standard type */
typedef struct
{
const Adc_HWConfigurationType* hwConfigPtr;
const Adc_ChannelConfigurationType* channelConfigPtr;
const uint16_t nbrOfChannels;
const Adc_GroupDefType* groupConfigPtr;
const uint16_t nbrOfGroups;
} Adc_ConfigType;
extern const Adc_ConfigType Adc_GlobalConfig [];
#endif /* ADC_CONFIGTYPES_H_ */
|
2301_81045437/classic-platform
|
include/arm/armv7_ar/Adc_ConfigTypes.h
|
C
|
unknown
| 5,048
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ADC_CONFIGTYPES_H_
#define ADC_CONFIGTYPES_H_
#if defined(CFG_STM32F1X)
typedef uint16_t Adc_ValueGroupType;
/* Group definitions. */
typedef enum
{
ADC_CH0,
ADC_CH1,
ADC_CH2,
ADC_CH3,
ADC_CH4,
ADC_CH5,
ADC_CH6,
ADC_CH7,
ADC_CH8,
ADC_CH9,
ADC_CH10,
ADC_CH11,
ADC_CH12,
ADC_CH13,
ADC_CH14,
ADC_CH15,
ADC_NBR_OF_CHANNELS,
}Adc_ChannelType;
/* Std-type, supplier defined */
typedef enum
{
ADC_SYSTEM_CLOCK
}Adc_ClockSourceType;
/* Std-type, supplier defined */
typedef enum
{
ADC_SYSTEM_CLOCK_DISABLED,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_1,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,
}Adc_PrescaleType;
/* Non-standard type */
typedef struct
{
Adc_ClockSourceType clockSource;
uint8_t hwUnitId;
Adc_PrescaleType adcPrescale;
}Adc_HWConfigurationType;
/* Std-type, supplier defined */
typedef enum
{
ADC_CONVERSION_TIME_2_CLOCKS,
ADC_CONVERSION_TIME_8_CLOCKS,
ADC_CONVERSION_TIME_64_CLOCKS,
ADC_CONVERSION_TIME_128_CLOCKS
}Adc_ConversionTimeType;
/* Channel definitions, std container */
typedef struct
{
Adc_ConversionTimeType adcChannelConvTime;
// NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcLow;
// NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcHigh;
// NOT SUPPORTED Adc_ResolutionType adcChannelResolution;
// NOT SUPPORTED Adc_CalibrationType adcChannelCalibrationEnable;
} Adc_ChannelConfigurationType;
/* Used ?? */
typedef struct
{
uint8 notifictionEnable;
Adc_ValueGroupType * resultBufferPtr;
Adc_StatusType groupStatus;
} Adc_GroupStatus;
/* Std-type, supplier defined */
typedef enum
{
ADC_CONV_MODE_DISABLED,
ADC_CONV_MODE_ONESHOT = 1,
ADC_CONV_MODE_CONTINUOUS = 9,
} Adc_GroupConvModeType;
/** Not supported. */
typedef uint16_t Adc_StreamNumSampleType;
/* Implementation specific */
typedef struct
{
// NOT SUPPORTED Adc_GroupAccessModeType accessMode;
Adc_GroupConvModeType conversionMode;
Adc_TriggerSourceType triggerSrc;
// NOT SUPPORTED Adc_HwTriggerSignalType hwTriggerSignal;
// NOT SUPPORTED Adc_HwTriggerTimerType hwTriggerTimer;
void (*groupCallback)(void);
// NOT SUPPORTED Adc_StreamBufferModeType streamBufferMode;
// NOT SUPPORTED Adc_StreamNumSampleType streamNumSamples;
const Adc_ChannelType *channelList;
Adc_ValueGroupType *resultBuffer;
// NOT SUPPORTED Adc_CommandType *commandBuffer;
Adc_ChannelType numberOfChannels;
Adc_GroupStatus *status;
// NOT SUPPORTED Dma_ChannelType dmaCommandChannel;
// NOT SUPPORTED Dma_ChannelType dmaResultChannel;
// NOT SUPPORTED const struct tcd_t * groupDMACommands;
// NOT SUPPORTED const struct tcd_t * groupDMAResults;
} Adc_GroupDefType;
/* Non-standard type */
typedef struct
{
const Adc_HWConfigurationType* hwConfigPtr;
const Adc_ChannelConfigurationType* channelConfigPtr;
const uint16_t nbrOfChannels;
const Adc_GroupDefType* groupConfigPtr;
const uint16_t nbrOfGroups;
} Adc_ConfigType;
#elif defined(CFG_JACINTO)
/* @req:JACINTO5 SWS_Adc_00508 */
typedef uint16_t Adc_ValueGroupType;
/* @req:JACINTO5 SWS_Adc_00507 */
typedef uint16 Adc_GroupType;
/* @req:JACINTO5 SWS_Adc_00506 */
typedef uint8_t Adc_ChannelType;
/* @req:JACINTO5 SWS_Adc_00509 */
typedef uint16_t Adc_PrescaleType;
/* !req:JACINTO5 SWS_Adc_00510 Adc_ConversionTimeType not configurable */
/* !req:JACINTO5 SWS_Adc_00511 Adc_SamplingTimeType not configurable */
/* !req:JACINTO5 SWS_Adc_00512 Adc_ResolutionType not configurable*/
/* @req:JACINTO5 SWS_Adc_00518 */
typedef uint16_t Adc_StreamNumSampleType;
/* @req:JACINTO5 SWS_Adc_00515 */
typedef enum
{
ADC_CONV_MODE_ONESHOT = 0,
ADC_CONV_MODE_CONTINUOUS
} Adc_GroupConvModeType;
typedef uint32 Adc_ArcControllerIdType;
/* Channel definitions, std container */
typedef struct
{
Adc_ChannelType Adc_Channel;
uint32 Adc_ChnDiff;
uint32 Adc_ChnSelrfm;
uint32 Adc_ChnSelrfp;
} Adc_ChannelConfigurationType;
typedef struct
{
uint8 notifictionEnable;
Adc_ValueGroupType *resultBufferPtr;
Adc_StatusType groupStatus;
Adc_StreamNumSampleType currSampleCount; /* Samples per group counter. =0 until first round of conversions complete
(all channels in group). Then =1 until second round of conversions complete and so on.*/
Adc_ValueGroupType *currResultBufPtr; /* Streaming sample current buffer pointer */
} Adc_GroupStatus;
typedef struct
{
uint8_t hwUnitId;
Adc_PrescaleType adcPrescale;
uint32 numberOfChannels;
const Adc_ChannelConfigurationType *channelList;
}Adc_HWConfigurationType;
/** Container for group setup. */
typedef struct
{
Adc_GroupAccessModeType accessMode;
Adc_GroupConvModeType conversionMode;
Adc_TriggerSourceType triggerSrc;
/* @req SWS_Adc_00085 */
void (*groupCallback)(void);
Adc_StreamBufferModeType streamBufferMode;
Adc_StreamNumSampleType streamNumSamples;
const uint32 *channelMappingList;
Adc_ChannelType numberOfChannels;
Adc_GroupStatus *status;
uint32 hwUnit;
#if defined(CFG_BRD_JAC6_VAYU_EVM)
uint32 ExtChannelId;
uint32 ExtSequenceId;
#endif /* defined(CFG_BRD_JAC6_VAYU_EVM) */
}Adc_GroupDefType;
/** Container for module initialization parameters. */
typedef struct
{
const Adc_HWConfigurationType* hwConfigPtr;
const Adc_GroupDefType* groupConfigPtr;
const Adc_GroupType nbrOfGroups;
}Adc_ConfigType;
#endif
#endif /* ADC_CONFIGTYPES_H_ */
|
2301_81045437/classic-platform
|
include/arm/armv7_m/Adc_ConfigTypes.h
|
C
|
unknown
| 8,048
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef MCU_CONFIGTYPES_H_
#define MCU_CONFIGTYPES_H_
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
#ifndef STM32F10X_CL
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#else
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
#endif
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
typedef struct {
uint32 AHBClocksEnable;
uint32 APB1ClocksEnable;
uint32 APB2ClocksEnable;
} Mcu_PerClockConfigType;
extern const Mcu_PerClockConfigType McuPerClockConfigData;
#endif /* MCU_CONFIGTYPES_H_ */
|
2301_81045437/classic-platform
|
include/arm/armv7_m/Mcu_ConfigTypes.h
|
C
|
unknown
| 4,148
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef PORT_CONFIGTYPES_H_
#define PORT_CONFIGTYPES_H_
#define GPIO_INPUT_MODE (0u)
#define GPIO_OUTPUT_10MHz_MODE (1u)
#define GPIO_OUTPUT_2MHz_MODE (2u)
#define GPIO_OUTPUT_50MHz_MODE (3u)
/* Valid for input modes. */
#define GPIO_ANALOG_INPUT_CNF (0u)
#define GPIO_FLOATING_INPUT_CNF (1u << 2u)
#define GPIO_INPUT_PULLUP_CNF (2u << 2u)
#define GPIO_RESERVED_CNF (3u << 2u)
/* Valid for output modes. */
#define GPIO_OUTPUT_PUSHPULL_CNF (0u)
#define GPIO_OUTPUT_OPENDRAIN_CNF (1u << 2u)
#define GPIO_ALT_PUSHPULL_CNF (2u << 2u)
#define GPIO_ALT_OPENDRAIN_CNF (3u << 2u)
#define GPIO_OUTPUT_LOW (0)
#define GPIO_OUTPUT_HIGH (1)
typedef struct
{
uint8_t GpioPinCnfMode_0:4;
uint8_t GpioPinCnfMode_1:4;
uint8_t GpioPinCnfMode_2:4;
uint8_t GpioPinCnfMode_3:4;
uint8_t GpioPinCnfMode_4:4;
uint8_t GpioPinCnfMode_5:4;
uint8_t GpioPinCnfMode_6:4;
uint8_t GpioPinCnfMode_7:4;
uint8_t GpioPinCnfMode_8:4;
uint8_t GpioPinCnfMode_9:4;
uint8_t GpioPinCnfMode_10:4;
uint8_t GpioPinCnfMode_11:4;
uint8_t GpioPinCnfMode_12:4;
uint8_t GpioPinCnfMode_13:4;
uint8_t GpioPinCnfMode_14:4;
uint8_t GpioPinCnfMode_15:4;
}GpioPinCnfMode_Type;
typedef struct
{
uint8_t GpioPinOutLevel_0:1;
uint8_t GpioPinOutLevel_1:1;
uint8_t GpioPinOutLevel_2:1;
uint8_t GpioPinOutLevel_3:1;
uint8_t GpioPinOutLevel_4:1;
uint8_t GpioPinOutLevel_5:1;
uint8_t GpioPinOutLevel_6:1;
uint8_t GpioPinOutLevel_7:1;
uint8_t GpioPinOutLevel_8:1;
uint8_t GpioPinOutLevel_9:1;
uint8_t GpioPinOutLevel_10:1;
uint8_t GpioPinOutLevel_11:1;
uint8_t GpioPinOutLevel_12:1;
uint8_t GpioPinOutLevel_13:1;
uint8_t GpioPinOutLevel_14:1;
uint8_t GpioPinOutLevel_15:1;
}GpioPinOutLevel_Type;
/** Top level configuration container */
typedef struct
{
/** Total number of pins */
uint16_t padCnt;
/** List of pin configurations */
const GpioPinCnfMode_Type *padConfig;
const GpioPinOutLevel_Type *outConfig;
/** Total number of pin default levels */
uint16_t remapCount;
const uint32_t* remaps;
} Port_ConfigType;
#endif /* PORT_CONFIGTYPES_H_ */
|
2301_81045437/classic-platform
|
include/arm/armv7_m/Port_ConfigTypes.h
|
C
|
unknown
| 2,979
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef PWM_CONFIGTYPES_H_
#define PWM_CONFIGTYPES_H_
#if defined(CFG_STM32F1X)
typedef uint16 Pwm_PeriodType;
typedef enum {
PWM_CHANNEL_11 = 0, // TIM1 Channel 1
PWM_CHANNEL_12,
PWM_CHANNEL_13,
PWM_CHANNEL_14,
PWM_CHANNEL_21, // TIM2 Channel 1
PWM_CHANNEL_22,
PWM_CHANNEL_23,
PWM_CHANNEL_24,
PWM_CHANNEL_31, // TIM3 Channel 1
PWM_CHANNEL_32,
PWM_CHANNEL_33,
PWM_CHANNEL_34,
PWM_CHANNEL_41, // TIM4 Channel 1
PWM_CHANNEL_42,
PWM_CHANNEL_43,
PWM_CHANNEL_44,
PWM_TOTAL_NOF_CHANNELS,
} Pwm_ChannelType;
typedef enum {
PWM_CHANNEL_PRESCALER_1=0,
PWM_CHANNEL_PRESCALER_2,
PWM_CHANNEL_PRESCALER_3,
PWM_CHANNEL_PRESCALER_4,
} Pwm_ChannelPrescalerType;
#define DUTY_AND_PERIOD(_duty,_period) .duty = (_duty*_period)>>15, .period = _period
typedef struct {
/* Number of duty ticks */
uint32_t duty:32;
/* Length of period, in ticks */
uint32_t period:32;
/* Counter */
uint32_t counter:32;
/* Enable freezing the channel when in debug mode */
uint32_t freezeEnable:1;
/* Disable output */
uint32_t outputDisable:1;
/* Select which bus disables the bus
* NOTE: Figure out how this works, i.e. what bus does it refer to? */
uint32_t outputDisableSelect:2;
/* Prescale the emios clock some more? */
uint32_t prescaler:2;
/* Prescale the emios clock some more? */
uint32_t usePrescaler:1;
/* Whether to use DMA. Currently unsupported */
uint32_t useDma:1;
uint32_t reserved_2:1;
/* Input filter. Ignored in output mode. */
uint32_t inputFilter:4;
/* Input filter clock source. Ignored in output mode */
uint32_t filterClockSelect:1;
/* Enable interrupts/flags on this channel? Required for DMA as well. */
uint32_t flagEnable:1;
uint32_t reserved_3:3;
/* Trigger a match on channel A */
uint32_t forceMatchA:1;
/* Triggers a match on channel B */
uint32_t forceMatchB:1;
uint32_t reserved_4:1;
/* We can use different buses for the counter. Use the internal counter */
uint32_t busSelect:2;
/* What edges to flag on? */
uint32_t edgeSelect:1;
/* Polarity of the channel */
uint32_t edgePolarity:1;
/* EMIOS mode. 0x58 for buffered output PWM */
uint32_t mode:7;
} Pwm_ChannelRegisterType;
typedef struct {
Pwm_ChannelRegisterType r;
Pwm_ChannelType channel;
} Pwm_ChannelConfigurationType;
// Channel configuration macro.
#define PWM_CHANNEL_CONFIG(_hwchannel, _period, _duty, _prescaler, _polarity) \
{\
.channel = _hwchannel,\
.r = {\
DUTY_AND_PERIOD(_duty, _period),\
.freezeEnable = 1u,\
.outputDisable = 0u,\
.usePrescaler = 1u,\
.prescaler = _prescaler,\
.useDma = 0u,\
.flagEnable = 0u, /* See PWM052 */ \
.busSelect = 3u, /* Use the internal counter bus */\
.edgePolarity = _polarity,\
.mode = 0u\
}\
}
#elif defined(CFG_JACINTO)
// Channel configuration macro.
#define PWM_CHANNEL_CONFIG(_hwchannel, _frequency, _duty, _divisor, _polarity, _idleState, _class) \
{\
.channel = _hwchannel,\
.frequency = _frequency,\
.duty = _duty, \
.divisor = _divisor,\
.polarity = _polarity,\
.idleState = _idleState,\
.class = _class\
}
#endif
#endif /* PWM_CONFIGTYPES_H_ */
|
2301_81045437/classic-platform
|
include/arm/armv7_m/Pwm_ConfigTypes.h
|
C
|
unknown
| 4,327
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ASM_ARM_H_
#define ASM_ARM_H
/*
* Exception handling numbers */
#if defined(CFG_ARMV7_AR)
#define EXC_UNDEFINED_INSTRUCTION 0
#define EXC_PREFETCH_ABORT 1
#define EXC_DATA_ABORT 2
#define EXC_SVC_CALL 4
/* Exception flags */
#define EXC_NOT_HANDLED 1UL
#define EXC_HANDLED 2UL
#define EXC_ADJUST_ADDR 4UL
#endif
#if defined(__GNUC__)
#define ASM_WORD(_x) .word _x
#define ASM_LONG(_x) .long _x
#define ASM_EXTERN(_x) .extern _x
#define ASM_GLOBAL(_x) .global _x
#define ASM_TYPE(_x,_y) .type _x, _y
#define ASM_LABEL(_x) _x:
#define ASM_WEAK(_x) .weak _x
#define ASM_SIZE(_x,_y) .size _x, _y
#define ASM_REPT(_x) .rept _x
#define ASM_ENDREPT .endr
#elif defined(__ARMCC_VERSION)
#define ASM_WORD(_x) _x DCD 1
#define ASM_EXTERN(_x) IMPORT _x
#define ASM_GLOBAL(_x) GLOBAL _x
#define ASM_TYPE(_x,_y)
#define ASM_LABEL(_x) _x
#elif defined(__ghs__)
#define ASM_WORD(_x) .word _x
#define ASM_LONG(_x) .long _x
#define ASM_EXTERN(_x) .export _x
#define ASM_GLOBAL(_x) .global _x
#define ASM_TYPE(_x,_y)
#define ASM_LABEL(_x) _x:
#define ASM_WEAK(_x) .weak _x
#define ASM_SIZE(_x,_y) .size _x, _y
#define ASM_REPT(_x) .rept _x
#define ASM_ENDREPT .endr
#elif defined(__ICCARM__)
#define ASM_WORD(_x) DCW _x
#define ASM_LONG(_x) _x
#define ASM_EXTERN(_x) EXTERN _x
#define ASM_GLOBAL(_x) PUBLIC _x
#define ASM_TYPE(_x,_y)
#define ASM_LABEL(_x) _x
#define ASM_WEAK(_x) PUBWEAK _x
#define ASM_SIZE(_x,_y)
#define ASM_REPT(_x) REPT _x
#define ASM_ENDREPT ENDR
#else
#error Compiler not supported
#endif
#if defined(_ASSEMBLER_)
/* Use as:
* ASM_SECTION_TEXT(.text) - For normal .text or .text_vle
*/
#if defined(__GNUC__) || defined(__ghs__)
# if defined(__ghs__) && defined(CFG_VLE)
# define ASM_SECTION_TEXT(_x) .section .vletext,"vax"
# define ASM_SECTION(_x) .section #_x,"vax"
# define ASM_CODE_DIRECTIVE() .vle
# else
# define ASM_SECTION_TEXT(_x) .section #_x,"ax"
# define ASM_SECTION(_x) .section #_x,"ax"
# endif
#elif defined(__CWCC__)
# if defined(CFG_VLE)
# define ASM_SECTION_TEXT(_x) .section _x,text_vle
# else
# define ASM_SECTION_TEXT(_x) .section _x,4,"rw"
# endif
# define ASM_SECTION(_x) .section _x,4,"r"
#elif defined(__DCC__)
# if defined(CFG_VLE)
# define ASM_SECTION_TEXT(_x) .section _x,4,"x"
# else
# define ASM_SECTION_TEXT(_x) .section _x,4,"x"
# endif
# define ASM_SECTION(_x) .section _x,4,"r"
#elif defined(__ICCARM__)
# if defined(CFG_VLE)
# define ASM_SECTION_TEXT(_x) SECTION _x:TEXT:NOROOT(4)
# else
# define ASM_SECTION_TEXT(_x) SECTION _x:TEXT:NOROOT(4)
# endif
# define ASM_SECTION(_x) SECTION _x:DATA:NOROOT(4)
#endif
#ifndef ASM_CODE_DIRECTIVE
#define ASM_CODE_DIRECTIVE()
#endif
#endif /* _ASSEMBLER_ */
#endif /*ASM_ARM_H_*/
|
2301_81045437/classic-platform
|
include/arm/asm_arm.h
|
C
|
unknown
| 3,710
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/*
* Bit manipulation functions, NOT tested..
*/
#ifndef BIT_H_
#define BIT_H_
#include <stdint.h>
/**
* @param aPtr Ptr to an array of unsigned chars.
* @param num The bit number to get.
* @return
*/
static inline int Bit_Get(uint8_t *aPtr, int num ) {
return (aPtr[num / 8] >> (num % 8)) & 1;
}
/**
*
* @param aPtr
* @param num
* @return
*/
static inline void Bit_Set(uint8_t *aPtr, int num ) {
aPtr[num / 8] |= (1<<(num % 8));
}
/**
*
* @param aPtr
* @param num
* @return
*/
static inline void Bit_Clear(uint8_t *aPtr, int num ) {
aPtr[num / 8] &= ~(1<<(num % 8));
}
#endif /* BIT_H_ */
|
2301_81045437/classic-platform
|
include/bit.h
|
C
|
unknown
| 1,425
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef BITDEF_H_
#define BITDEF_H_
#define BITDEF_ENTRY(_reg, _regbitdef ) \
[_reg].reg = _reg, \
[_reg].defPtr = _regbitdef, \
[_reg].defSize = sizeof(_regbitdef)/sizeof(BitDefType)
typedef struct {
uint8 pos;
uint8 size;
char *desc;
} BitDefType;
typedef struct {
uint16 reg;
BitDefType *defPtr;
uint16 defSize;
} RegInfoType;
void Bitdef_Print(RegInfoType *regP, uint16 data);
#endif /* BITDEF_H_ */
|
2301_81045437/classic-platform
|
include/bitdef.h
|
C
|
unknown
| 1,245
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef CIRQ_BUFFER_H_
#define CIRQ_BUFFER_H_
#include "Platform_Types.h"
typedef struct {
/* The max number of elements in the list */
uint32 maxCnt;
uint32 currCnt;
/* Size of the elements in the list */
uint32 dataSize;
/* List head and tail */
void *head;
void *tail;
/* Buffer start/stop */
void *bufStart;
void *bufEnd;
} CirqBufferType;
/* Dynamic implementation */
CirqBufferType *CirqBuffDynCreate( uint32 size, uint32 dataSize );
int CirqBuffDynDestroy(CirqBufferType *cPtr );
/* Static implementation */
CirqBufferType CirqBuffStatCreate(void *buffer, uint32 maxCnt, uint32 dataSize);
int CirqBuffPush( CirqBufferType *cPtr, void *dataPtr );
int CirqBuffPop(CirqBufferType *cPtr, void *dataPtr );
void *CirqBuff_PushLock( CirqBufferType *cPtr);
void *CirqBuff_PopLock(CirqBufferType *cPtr );
void *CirqBuff_Peek( CirqBufferType *cPtr, uint32 index );
void CirqBuff_Init(CirqBufferType *cirqbuffer, void *buffer, uint32 maxCnt, uint32 dataSize);
static inline boolean CirqBuff_Empty(CirqBufferType *cPtr ) {
return (cPtr->currCnt == 0);
}
static inline boolean CirqBuff_Full(CirqBufferType *cPtr ) {
return (cPtr->currCnt == cPtr->maxCnt);
}
static inline int CirqBuff_Size( CirqBufferType *cPtr ){
return cPtr->currCnt;
}
static inline void CirqBuff_PushRelease( CirqBufferType *cPtr) {
++cPtr->currCnt;
}
static inline void CirqBuff_PopRelease( CirqBufferType *cPtr) {
--cPtr->currCnt;
}
#endif /* CIRQ_BUFFER_H_ */
|
2301_81045437/classic-platform
|
include/cirq_buffer.h
|
C
|
unknown
| 2,320
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
// PC-Lint Exception to MISRA rule 19.12: stdio ok in debug.h.
//lint -e(829)
#ifndef DEBUG_H_
#define DEBUG_H_
/**
*
* NOTE!!!!
* Do not use this in a header file. Should be used in the *.c file like this.
*
* #define USE_DEBUG_PRINTF
* #include "debug.h"
*
* Macro's for debugging and tracing
*
* Define USE_LDEBUG_PRINTF and DBG_LEVEL either globally( e.g. a makefile )
* or in a specific file. The DBG_LEVEL macro controls the amount
* of detail you want in the debug printout.
* There are 3 levels:
* DEBUG_LOW - Used mainly by drivers to get very detailed
* DEBUG_MEDIUM - Medium detail
* DEBUG_HIGH - General init
*
* Example:
* #define DEBUG_LVL DEBUG_HIGH
* DEBUG(DEBUG_HIGH,"Starting GPT");
*
*
*/
#include <stdio.h>
#define DEBUG_LOW 1u
#define DEBUG_MEDIUM 2u
#define DEBUG_HIGH 3u
#define DEBUG_NONE 4u
#ifndef DEBUG_LVL
#define DEBUG_LVL 2u
#endif
#define CH_ISR 0u
#define CH_PROC 1u
#if defined(DBG)
#define dbg(...) printf(__VA_ARGS__ )
#else
#define dbg(...)
#endif
#if defined(_DEBUG_)
#define _debug_(...) printf (__VA_ARGS__);
#else
#define _debug_(...)
#endif
#if defined(USE_DEBUG_PRINTF)
#define DEBUG(_level,...) \
do { \
if(_level>=DEBUG_LVL) { \
printf (__VA_ARGS__); \
}; \
} while(0);
#else
#define DEBUG(_level,...)
#endif
#if defined(USE_LDEBUG_PRINTF)
#define debug(...) printf(__VA_ARGS__)
#define LDEBUG_PRINTF(format,...) printf(format,## __VA_ARGS__ )
#define LDEBUG_FPUTS(_str) fputs((_str),stdout)
#else
#define LDEBUG_PRINTF(format,...)
#define LDEBUG_FPUTS(_str)
#endif
#endif /*DEBUG_H_*/
|
2301_81045437/classic-platform
|
include/debug.h
|
C
|
unknown
| 2,514
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DEVICE_H_
#define DEVICE_H_
#include <stdint.h>
#define DEVICE_TYPE_CONSOLE 1
#define DEVICE_TYPE_FS 2
#define GetRootObject(RootType, member, objPointer) ((RootType *)((char *)objPointer - (char *)(&((RootType*)0)->member)))
typedef struct {
const char *name;
uint32_t type;
} DeviceType;
#endif /* DEVICE_H_ */
|
2301_81045437/classic-platform
|
include/device.h
|
C
|
unknown
| 1,113
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/*
* serial.h
*
* Created on: 23 aug 2011
* Author: mahi
*/
#ifndef DEVICE_SERIAL_H_
#define DEVICE_SERIAL_H_
#include <stdint.h>
#include <stdlib.h>
#include "device.h"
#include "sys/queue.h"
#define DEVICE_NAME_MAX 16
/* Device type that maps well to POSIX open/read/write */
typedef struct DeviceSerial {
DeviceType device;
char name[DEVICE_NAME_MAX];
uint32_t data;
int (*open)( const char *path, int oflag, int mode );
int (*close)( uint8_t *data, size_t nbytes);
/* Reads nbytes from device to data.
* Non-blocking read */
int (*read)( uint8_t *data, size_t nbytes);
/* Write nbytes from data to device
* Blocks until nbytes have been written */
int (*write)( uint8_t *data, size_t nbytes );
TAILQ_ENTRY(DeviceSerial) nextDevice;
} DeviceSerialType;
#endif /* SERIAL_H_ */
|
2301_81045437/classic-platform
|
include/device_serial.h
|
C
|
unknown
| 1,641
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef FS_H_
#define FS_H_
#include <stdlib.h>
#include "device.h"
#define MAX_FILENAME_LEN 128
#define FLAGS_SETBUF_ALLOC 1
typedef struct _FileS {
#if defined(CFG_FS_RAM)
char filepath[MAX_FILENAME_LEN];
#endif
int fileNo;
int b;
uint32_t type;
uint32_t o_flags;
uint32_t flags;
DeviceType *devicePtr;
/* Ptr to file data */
uint8_t *data;
/* position with a file */
uint32_t pos;
/* total size of allocated data */
uint32_t asize;
/* end of written data, note that asize !=end normally */
uint32_t end;
} _FileType;
typedef struct _EnvS {
/* Each "Task" should at least have a set of std file handles */
_FileType *_stdin;
_FileType *_stdout;
_FileType *_stderr;
} _EnvType;
extern _EnvType *_EnvPtr;
typedef _FileType FILE;
struct FSDriver;
typedef struct FSDriver {
DeviceType device;
uint32_t data;
const char *name;
/**
*
* @param dev
* @param f
* @param pathname
* @return 0 - on success.
* ENOENT - If we can't open it.
*/
int (*open)(struct FSDriver *dev, FILE *f, const char *pathname);
/**
* Close a file
* @param dev - The device
* @param f - The file to close
* @return
*/
int (*close)(struct FSDriver *dev, FILE *f);
/**
*
* @param dev - The device
* @param f - The file to read
* @param buf - Buffer to read to
* @param size - Number of bytes to read
* @return
*/
int (*read)(struct FSDriver *dev, FILE *f, void *buf, size_t size);
/**
* Write nbyte to file f from buffer buf.
*
* @param dev - Device pointer
* @param f - File
* @param buf - Buffer to write
* @param nbyte - Bytes to write
* @return
*/
int (*write)(struct FSDriver *dev, FILE *f, const void *buf, size_t nbyte);
int (*lseek)(struct FSDriver *dev, FILE *f, int pos);
// TAILQ_ENTRY(DeviceSerial) nextDevice;
} FSDriverType;
#endif /* FS_H_ */
|
2301_81045437/classic-platform
|
include/fs.h
|
C
|
unknown
| 2,890
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef CPU_H
#define CPU_H
#include "Std_Types.h"
typedef uint32_t imask_t;
#define Irq_Save(flags) ((flags) = 0) // Dummy assignment to avoid compiler warnings
#define Irq_Restore(flags) (void)(flags)
#define Irq_Disable()
#define Irq_Enable()
#define Irq_SuspendAll() Irq_Disable()
#define Irq_ResumeAll() Irq_Enable()
#define Irq_SuspendOs() Irq_Disable()
#define Irq_ResumeOs() Irq_Enable()
#define ilog2(_x) (__builtin_ffs(_x) - 1)
#endif /* CPU_H */
|
2301_81045437/classic-platform
|
include/generic/Cpu.h
|
C
|
unknown
| 1,255
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ADC_CONFIGTYPES_H_
#define ADC_CONFIGTYPES_H_
typedef uint16_t Adc_ValueGroupType;
typedef enum
{
ADC_CH0,
ADC_CH1,
ADC_CH2,
ADC_CH3,
ADC_CH4,
ADC_CH5,
ADC_CH6,
ADC_CH7,
ADC_NBR_OF_CHANNELS,
}Adc_ChannelType;
/* Std-type, supplier defined */
typedef enum
{
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,
}Adc_PrescaleType;
/* Std-type, supplier defined */
typedef enum
{
ADC_CONVERSION_TIME_2_CLOCKS,
ADC_CONVERSION_TIME_4_CLOCKS,
ADC_CONVERSION_TIME_8_CLOCKS,
ADC_CONVERSION_TIME_16_CLOCKS
}Adc_ConversionTimeType;
/* Channel definitions, std container */
typedef struct
{
Adc_ConversionTimeType adcChannelConvTime;
// NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcLow;
// NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcHigh;
// NOT SUPPORTED Adc_ResolutionType adcChannelResolution;
// NOT SUPPORTED Adc_CalibrationType adcChannelCalibrationEnable;
} Adc_ChannelConfigurationType;
typedef enum
{
ADC_RESOLUTION_10_BIT,
ADC_RESOLUTION_8_BIT,
}Adc_ResolutionType;
typedef struct
{
uint8 notifictionEnable;
Adc_ValueGroupType * resultBufferPtr;
Adc_StatusType groupStatus;
} Adc_GroupStatus;
/* Std-type, supplier defined */
typedef enum
{
ADC_CONV_MODE_DISABLED,
ADC_CONV_MODE_ONESHOT = 1,
ADC_CONV_MODE_CONTINUOUS = 9,
} Adc_GroupConvModeType;
typedef struct
{
Adc_GroupConvModeType conversionMode;
Adc_TriggerSourceType triggerSrc;
void (*groupCallback)(void);
const Adc_ChannelType *channelList;
Adc_ValueGroupType *resultBuffer;
Adc_ChannelType numberOfChannels;
Adc_GroupStatus *status;
} Adc_GroupDefType;
typedef struct
{
Adc_ConversionTimeType convTime;
Adc_ResolutionType resolution;
Adc_PrescaleType adcPrescale;
}Adc_HWConfigurationType;
typedef struct
{
const Adc_HWConfigurationType* hwConfigPtr;
const Adc_GroupDefType* groupConfigPtr;
const uint16_t nbrOfGroups;
} Adc_ConfigType;
#endif /* ADC_CONFIGTYPES_H_ */
|
2301_81045437/classic-platform
|
include/hc1x/Adc_ConfigTypes.h
|
C
|
unknown
| 4,125
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef CPU_H_
#define CPU_H_
#include "Std_Types.h"
typedef uint32_t imask_t;
#if defined(__IAR_SYSTEMS_ICC__)
#include <../intrinsics.h>
#define Irq_Disable() __disable_interrupt();
#define Irq_Enable() __enable_interrupt();
#else
#define Irq_Disable() asm volatile (" sei");
#define Irq_Enable() asm volatile (" cli");
#endif
#define Irq_SuspendAll() Irq_Disable()
#define Irq_ResumeAll() Irq_Enable()
#define Irq_SuspendOs() Irq_Disable()
#define Irq_ResumeOs() Irq_Enable()
#define Irq_Save(flags) flags = _Irq_Disable_save()
#define Irq_Restore(flags) _Irq_Disable_restore(flags)
#if defined(__IAR_SYSTEMS_ICC__)
static inline unsigned long _Irq_Disable_save(void)
{
__istate_t old;
old = __get_interrupt_state();
__disable_interrupt();
return old;
}
static inline void _Irq_Disable_restore(unsigned long flags) {
__set_interrupt_state(flags);
}
/*
* ilog2 - return floor(log base 2 of x), where x > 0
* Example: ilog2(16) = 4
* Legal ops: ! ~ & ^ | + << >>
* Max ops: 90
* Rating: 4
*/
// = n where the most significant non-zero bit is the nth bit
static inline uint32 ilog2(uint32 x) {
// find out if the non-zero bit is in the first two words
uint32 A = !(!(x >> 16)); // should be 1 if the n >= 16
uint32 count = 0;
uint32 x_copy = x;
// if A is 1 add 16 to count
count = count + (A<<4);
// if A is 1 return x >> 15, else return x. This is a
// modified version of my conditional code
x_copy = (((~A + 1) & (x >> 16)) + (~(~A+1) & x));
// repeat the process but rather than operating on the second half,
// we can now only worry about the second quarter of the first half.
A = !(!(x_copy >> 8));
count = count + (A<<3);
x_copy = (((~A + 1) & (x_copy >> 8)) + (~(~A+1) & x_copy));
// continue this process until we have covered all bits.
A = !(!(x_copy >> 4));
count = count + (A<<2);
x_copy = (((~A + 1) & (x_copy >> 4)) + (~(~A+1) & x_copy));
A = !(!(x_copy >> 2));
count = count + (A<<1);
x_copy = (((~A + 1) & (x_copy >> 2)) + (~(~A+1) & x_copy));
A = !(!(x_copy >> 1));
count = count + A;
return count;
}
#elif defined(__GNUC__)
/*-----------------------------------------------------------------*/
static inline unsigned long _Irq_Disable_save(void)
{
unsigned long result;
asm volatile ("tfr CCR, %0" : "=r" (result) : );
Irq_Disable();
return result;
}
/*-----------------------------------------------------------------*/
static inline void _Irq_Disable_restore(unsigned long flags)
{
asm volatile ("tfr %0, CCR" : : "r" (flags) );
}
#define ilog2(x) __builtin_ffs(x)
#else
#error Compiler not defined
#endif
#endif /* CPU_H_ */
|
2301_81045437/classic-platform
|
include/hc1x/Cpu.h
|
C
|
unknown
| 3,601
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef IRQ_DEFINES_H_
#define IRQ_DEFINES_H_
#define IRQ_NR_RES0 0
#define IRQ_NR_RES1 1
#define IRQ_NR_RES2 2
#define IRQ_NR_RES3 3
#define IRQ_NR_RES4 4
#define IRQ_NR_RES5 5
#define IRQ_NR_PWM_SHUTDOWN 6
#define IRQ_NR_PTPIF 7
#define IRQ_NR_CAN4_TX 8
#define IRQ_NR_CAN4_RX 9
#define IRQ_NR_CAN4_ERR 10
#define IRQ_NR_CAN4_WAKE 11
#define IRQ_NR_CAN3_TX 12
#define IRQ_NR_CAN3_RX 13
#define IRQ_NR_CAN3_ERR 14
#define IRQ_NR_CAN3_WAKE 15
#define IRQ_NR_CAN2_TX 16
#define IRQ_NR_CAN2_RX 17
#define IRQ_NR_CAN2_ERR 18
#define IRQ_NR_CAN2_WAKE 19
#define IRQ_NR_CAN1_TX 20
#define IRQ_NR_CAN1_RX 21
#define IRQ_NR_CAN1_ERR 22
#define IRQ_NR_CAN1_WAKE 23
#define IRQ_NR_CAN0_TX 24
#define IRQ_NR_CAN0_RX 25
#define IRQ_NR_CAN0_ERR 26
#define IRQ_NR_CAN0_WAKE 27
#define IRQ_NR_FLASH 28
#define IRQ_NR_EEPROM 29
#define IRQ_NR_SPI2 30
#define IRQ_NR_SPI1 31
#define IRQ_NR_IIC 32
#define IRQ_NR_BDLC 33
#define IRQ_NR_SELFCLK_MODE 34
#define IRQ_NR_PLL_LOCK 35
#define IRQ_NR_ACCB_OVERFLOW 36
#define IRQ_NR_MCCNT_UNDERFLOW 37
#define IRQ_NR_PTHIF 38
#define IRQ_NR_PTJIF 39
#define IRQ_NR_ATD1 40
#define IRQ_NR_ATD0 41
#define IRQ_NR_SCI1 42
#define IRQ_NR_SCI0 43
#define IRQ_NR_SPI0 44
#define IRQ_NR_ACCA_INPUT 45
#define IRQ_NR_ACCA_OVERFLOW 46
#define IRQ_NR_TIMER_OVERFLOW 47
#define IRQ_NR_TC7 48
#define IRQ_NR_TC6 49
#define IRQ_NR_TC5 50
#define IRQ_NR_TC4 51
#define IRQ_NR_TC3 52
#define IRQ_NR_TC2 53
#define IRQ_NR_TC1 54
#define IRQ_NR_TC0 55
#define IRQ_NR_RTII 56
#define IRQ_NR_IRQ 57
#define IRQ_NR_XIRQ 58
#define IRQ_NR_SWI 59
#define IRQ_NR_ILLEGAL 60
#define IRQ_NR_COP_FAIL 61
#define IRQ_NR_COP_CLOCK 62
#define IRQ_NR_RESET 63
#endif
|
2301_81045437/classic-platform
|
include/hc1x/irq_defines.h
|
C
|
unknown
| 2,491
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef _REGS_H_
#define _REGS_H_
#if defined(CFG_HCS12D)
#include "regs_hcs12d.h"
#elif defined(CFG_HCS12XD)
#include "regs_hcs12xd.h"
#else
#error NO MCU SELECTED!!!!
#endif
#endif /* ifndef _REGS_H_ */
|
2301_81045437/classic-platform
|
include/hc1x/regs.h
|
C
|
unknown
| 978
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef IO_H_
#define IO_H_
#include "Arc_Types.h"
#define WRITE8(address, value) (*(uint8_t*)(address) = (value))
#define READ8(address) ((uint8)(*(uint8_t*)(address)))
#define WRITE16(address, value) (*(vuint16_t*)(address) = (value))
#define READ16(address) ((uint16)(*(vuint16_t*)(address)))
#define WRITE32(address, value) (*(vuint32_t*)(address) = (value))
#define READ32(address) ((uint32)(*(vuint32_t*)(address)))
#define WRITE64(address, value) (*(vuint64_t*)(address) = (value))
#define READ64(address) ((uint64)(*(vuint64_t*)(address)))
/* Not aligned reads */
#define READ32_NA(address ) (uint32)( (((uint32)((address)[0]))<<24u) + \
(((uint32)((address)[1]))<<16u) + \
(((uint32)((address)[2]))<<8u) + \
((uint32)((address)[3])) )
#define READ16_NA(address ) (uint16)( (((uint16)((address)[0]))<<8u) + \
(((uint16)((address)[1]))) )
#define SET32( _addr, _val) (*(vuint32_t*)(_addr) |= (_val))
#define CLEAR32(_addr, _val) (*(vuint32_t*)(_addr) &= ~(_val))
/* READWRITE macros
* address - The address to read/write from/to
* mask - The value read is inverted and AND:ed with mask
* val - The Value to write.
*
* READWRITE32(0x120,0x0,0x9) - Read from address 0x120 (contains 0x780), ANDs with
* 0xffff_ffff and ORs in 0x9 -> Write 0x789 to 0x120
*
*/
static inline void READWRITE32(uint32_t address, uint32_t mask, uint32_t val ) {
WRITE32(address,(READ32(address)&~(mask))|val);
}
#define READWRITE8(address,mask,val) WRITE8(address,(READ8(address)&~(mask))|val)
/* NA - Not Aligned */
#define WRITE32_NA(address, value ) \
(address)[0] = ((value>>24u)&0xffu); \
(address)[1] = ((value>>16u)&0xffu); \
(address)[2] = ((value>>8u)&0xffu); \
(address)[3] = ((value&0xffu)); \
#define WRITE16_NA(address, value ) \
(address)[0] = ((value>>8u)&0xffu); \
(address)[1] = ((value&0xffu)); \
#endif /* IO_H_ */
|
2301_81045437/classic-platform
|
include/io.h
|
C
|
unknown
| 2,847
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef IRQ_H_
#define IRQ_H_
#include <stdint.h>
#if defined(USE_KERNEL) || defined(USE_LINUXOS)
#include "Os.h"
#else
typedef uint32 CoreIDType; /* @req SWS_Os_00790 Type definition */
#endif
#include "irq_types.h"
#include "bit.h"
typedef void ( *IrqFuncType)(void);
#if (OS_SC2==STD_ON) || (OS_SC4==STD_ON)
#define HAVE_SC2_SC4(_value) _value
#else
#define HAVE_SC2_SC4(_value)
#endif
#define IRQ_NAME(_vector) IrqVector_ ## _vector
/**
* Init the interrupt controller
*/
void Irq_Init( void );
#if defined(CFG_HC1X)
/**
*
* @param stack Ptr to the current stack.
* @param irq_nr The nr. of the interrupt being handled.
*
* The stack holds C, NVGPR, VGPR and the EXC frame.
*
*/
void *Irq_Entry( uint8_t irq_nr, void *stack );
#else
/**
*
* @param stack_p Ptr to the current stack.
*
* The stack holds C, NVGPR, VGPR and the EXC frame.
*
*/
void *Irq_Entry( void *stack_p );
#endif
struct OsIsrConst;
/**
* Generates a soft interrupt
* Used by the test-system
*
* @param vector
*/
void Irq_GenerateSoftInt( IrqType vector );
/**
* Ack a software interrupt.
* Used by the test-system
*
* @param vector
*/
void Irq_AckSoftInt( IrqType vector );
/**
* Get the current priority from the interrupt controller.
* @param cpu
* @return
*/
uint8_t Irq_GetCurrentPriority( Cpu_t cpu);
/**
* Set the priority in the interrupt controller for vector
*/
void Irq_SetPriority( CoreIDType cpu, IrqType vector, uint8 prio );
/**
* Enable a vector in the interrupt controller
*
* @param vector
* @param priority
* @param core
*/
void Irq_EnableVector( sint16 vector, uint8 priority, sint32 core );
/**
*
* @param func
* @param vector
* @param type
* @param priority
* @param core
*/
void Irq_EnableVector2( IrqFuncType func, sint16 vector, uint16 type, uint8 priority, sint32 core );
/**
* Disable a vector so that Irq_EnableVector can be used again.
* (used by the test-system for some archs)
*
* @param vector
* @param core
*/
void Irq_DisableVector( sint16 vector, sint32 core );
#ifndef Irq_EOI
void Irq_EOI( sint16 vector );
#endif
#if defined (CFG_TMS570)
void Irq_SOI3(uint8 prio);
void setupPinsForIrq( void );
#endif
/**
* Function to return the ISR id based on priority, if an ISR is already installed then
* Irq_VectorTable[priority] will have its ISR id otherwise VECTOR_ILL.
*
* @param priority
*/
#if defined(CFG_TC2XX) || defined(CFG_TC3XX)
uint16 Irq_GetISRinstalledId(uint8 priority );
#endif
#endif /* IRQ_H_ */
|
2301_81045437/classic-platform
|
include/irq.h
|
C
|
unknown
| 3,384
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ISR_H_
#define ISR_H_
#include "Os.h"
#include "sys/queue.h"
#include "os_trap.h"
struct OsResource;
/*
* INCLUDE "RULES"
* Since the types and methods defined here are used by the drivers, they should
* include it. E.g. #include "isr.h"
*
* This file is also used internally by the kernel
*
*
* irq_types.h ( Vector enums )
* irq.h ( Interface )
*
*/
/* ----------------------------[includes]------------------------------------*/
/* ----------------------------[define]--------------------------------------*/
#define ISR_TYPE_1 0
#define ISR_TYPE_2 1
#define VECTOR_ILL 0xff
/* ----------------------------[macro]---------------------------------------*/
#ifdef CFG_DRIVERS_USE_CONFIG_ISRS
#define ISR_INSTALL_ISR2( _name, _entry, _vector, _priority, _app )
#define ISR_INSTALL_ISR1(_name,_entry, _vector,_priority,_app)
#else
#define ISR_DECLARE_ISR2(_name, _entry, _unique, _vector,_priority,_app ) \
static const OsIsrConstType _entry ## _unique = { \
.vector = _vector, \
.type = ISR_TYPE_2, \
.priority = _priority, \
.entry = _entry, \
.name = _name, \
.resourceMask = 0, \
.appOwner = _app, \
}; \
#define __ISR_INSTALL_ISR2(_name, _entry, _unique, _vector,_priority,_app ) \
do { \
static const OsIsrConstType _entry ## _unique = { \
.vector = _vector, \
.type = ISR_TYPE_2, \
.priority = _priority, \
.entry = _entry, \
.name = _name, \
.resourceMask = 0, \
.appOwner = _app, \
}; \
(void)OS_TRAP_Os_IsrAdd( & _entry ## _unique); \
} while(FALSE);
#define _ISR_INSTALL_ISR2(_name,_entry, _unique, _vector,_priority,_app) \
__ISR_INSTALL_ISR2(_name,_entry, _unique, _vector,_priority,_app)
#define ISR_INSTALL_ISR2(_name,_entry, _vector,_priority,_app) \
_ISR_INSTALL_ISR2(_name,_entry, __LINE__, _vector,_priority,_app)
#define ISR_DECLARE_ISR1(_name, _entry, _unique, _vector,_priority,_app ) \
static const OsIsrConstType _entry ## _unique = { \
.vector = _vector, \
.type = ISR_TYPE_1, \
.priority = _priority, \
.entry = _entry, \
.name = _name, \
.resourceMask = 0, \
.appOwner = _app, \
}; \
#define __ISR_INSTALL_ISR1(_name, _entry, _unique, _vector,_priority,_app ) \
do { \
static const OsIsrConstType _entry ## _unique = { \
.vector = _vector, \
.type = ISR_TYPE_1, \
.priority = _priority, \
.entry = _entry, \
.name = _name, \
.resourceMask = 0, \
.appOwner = _app, \
}; \
(void) OS_TRAP_Os_IsrAdd( & _entry ## _unique); \
} while(0);
#define _ISR_INSTALL_ISR1(_name,_entry, _unique, _vector,_priority,_app) \
__ISR_INSTALL_ISR1(_name,_entry, _unique, _vector,_priority,_app)
#define ISR_INSTALL_ISR1(_name,_entry, _vector,_priority,_app) \
_ISR_INSTALL_ISR1(_name,_entry, __LINE__, _vector,_priority,_app)
#endif
/* ----------------------------[typedef]-------------------------------------*/
typedef struct {
void *curr; /* Current stack ptr( at swap time ) */
void *top; /* Top of the stack( low address ) */
uint32 size; /* The size of the stack */
} OsIsrStackType;
/* STD container : OsIsr
* Class: ALL
*
* OsIsrCategory: 1 CATEGORY_1 or CATEGORY_2
* OsIsrResourceRef: 0..* Reference to OsResources
* */
typedef struct OsIsrConst {
const char *name;
uint8 core;
uint8 priority;
sint16 vector;
sint16 type;
void (*entry)( void );
ApplicationType appOwner;
/* Mapped against OsIsrResourceRef */
uint32 resourceMask;
} OsIsrConstType;
/*
*
*/
typedef struct OsIsrVar{
ISRType id;
#if defined(CFG_OS_ISR_HOOKS)
ISRType preemtedId;
#endif
int state;
const OsIsrConstType *constPtr;
#if defined(CFG_TMS570) || defined(CFG_ARMV7_AR)
sint16 activeVector;
#endif
/* List of resource held by this ISR */
TAILQ_HEAD(,OsResource) resourceHead;
} OsIsrVarType;
/* ----------------------------[functions]-----------------------------------*/
#if OS_ISR_MAX_CNT!=0
extern OsIsrVarType Os_IsrVarList[OS_ISR_MAX_CNT];
#endif
/**
* Init the ISR system
*/
void Os_IsrInit( void );
/**
* Add and ISR.
* @param isrPtr
* @return
*/
ISRType Os_IsrAdd( const OsIsrConstType * isrPtr );
/**
* Add ISR with an id
* @param isrPtr Pointer to ISR information
* @param id The id we want to add it with
*/
void Os_IsrAddWithId( const OsIsrConstType * isrPtr, ISRType id );
/**
* Remove an installed ISR
* @param vector The vector
* @param type Not used
* @param priority Not used
* @param app Not used.
*/
void Os_IsrRemove( sint16 vector, sint16 type, uint8 priority, ApplicationType app );
/**
* Get stack information for an ISR.
* @param stack In/Out pointer to stack information
*/
void Os_IsrGetStackInfo( OsIsrStackType *stack );
/**
* Called by all interrupts.
*
* @param stack Pointer to current stack
* @param isrTableIndex Table index for vector
*/
void *Os_Isr( void *stack, uint16 isrTableIndex);
#if defined(CFG_TMS570)
void *Os_Isr_cr4( void *stack, sint16 virtualVector, sint16 vector );
#endif
#if defined(CFG_ARM_CM3)
void Os_Isr_cm3( sint16 vector );
void TailChaining(void *stack);
#endif
OsIsrVarType *Os_IsrGet( ISRType id );
ApplicationType Os_IsrGetApplicationOwner( ISRType id );
void Os_IsrResourceAdd( struct OsResource *rPtr, OsIsrVarType *isrPtr);
void Os_IsrResourceRemove(struct OsResource *rPtr , OsIsrVarType *isrPtr);
#endif /*ISR_H_*/
|
2301_81045437/classic-platform
|
include/isr.h
|
C
|
unknown
| 7,044
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef _LOG_H
#define _LOG_H
/**
* @brief A logging API
*
* @details
* A very crude and fast logger that logs in a circular buffer. The logger
* information is just a long string that is divided into different
* sections.
* .
* index _s _s_s _s_u32 _s_u8
* ---------------------------------------------
* 0-
* | "name"
* |-- LOG_NAME_SIZE / LOG_POS1
* | "str" "str1" "str" "str"*)
* |-- LOG_POS2
* | "..." "str2" "u32" "data"**)
* |-- LOG_MAX_STR
*
* *) Only 4 bytes
* **) Data is concatenated when n is too large.
* .
* .
* Usage:
* To use the logger in a file:
* .
* in header
*
* #if defined(CFG_LOG) && defined(LOG_<bla>)
* #define _LOG_NAME_ "bla"
* #endif
* #include "log.h"
* .
* in code:
* .
* LOG_S("some text");
* LOG_S_S("some text", "some more text");
* LOG_S_U32("some text", 123);
* LOG_S_U8("array", &data, 8);
*/
#if defined(_LOG_NAME_)
#define LOG_S( _a) log_s( _LOG_NAME_,_a)
#define LOG_S_S( _a, _b ) log_s_s(_LOG_NAME_, _a, _b )
#define LOG_S_U32( _a, _b) log_s_u32( _LOG_NAME_,_a, _b)
#define LOG_S_A8( _a, _b, _c ) log_s_a8( _LOG_NAME_, _a, _b, _c )
void log_s( const char *name ,const char *str );
void log_s_s( const char *name ,const char *str, const char *str2 );
void log_s_u32( const char *name ,const char *str, uint32_t val);
void log_s_a8( const char *name ,const char *str, uint8_t *data, uint8_t num );
#else
#define LOG_S( _a)
#define LOG_S_S( _a, _b )
#define LOG_S_U32( _a, _b)
#define LOG_S_A8( _a, _b, _c )
#endif
#endif
|
2301_81045437/classic-platform
|
include/log.h
|
C
|
unknown
| 2,444
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef _LOGGER_H
#define _LOGGER_H
#define LOG_MAX_STR 20
#define LOG_SIZE 200
void Log_Add( const char *str );
void Log_Add2( const char *str, const char *str2 );
void Log_Init( void );
#endif
|
2301_81045437/classic-platform
|
include/logger.h
|
C
|
unknown
| 972
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef MBOX_H_
#define MBOX_H_
#include "cirq_buffer.h"
typedef struct
{
CirqBufferType *cirqPtr;
} Arc_MBoxType;
typedef enum {
SOME_ERROR,
} Arc_MBoxErrType;
Arc_MBoxType* Arc_MBoxCreate( uint32 size );
void Arc_MBoxDestroy( Arc_MBoxType *mPtr );
sint32 Arc_MBoxPost( const Arc_MBoxType *mPtr, void *msg );
sint32 Arc_MBoxFetch(const Arc_MBoxType *mPtr, void *msg);
#endif /* MBOX_H_ */
|
2301_81045437/classic-platform
|
include/mbox.h
|
C
|
unknown
| 1,182
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef PERF_H_
#define PERF_H_
/*
* Configure:
* OS Editor
* OsOS->OsHooks->OsPreTaskHook = TRUE
* OsOS->OsHooks->OsPostTaskHook = TRUE
* OsOS->OsHooks->OsStartupHook = TRUE
*/
/**
* Call cyclic to calculate load on the system
*/
void Perf_Trigger(void);
/**
* Call at init
*/
void Perf_Init( void );
/**
* Call whenever you want to install a name to an index.
*/
void Perf_InstallFunctionName(uint8 PerfFuncIdx, char *PerfNamePtr, uint8 PerfNameLen);
/**
* Call before the function
*/
void Perf_PreFunctionHook(uint8 PerfFuncIdx);
/**
* Call after the function
*/
void Perf_PostFunctionHook(uint8 PerfFuncIdx);
/**
* Readout of CPU load
*/
uint8 Perf_ReadCpuLoad();
#if !defined CFG_PERF_FUNC
#define Perf_InstallFunctionName
#define Perf_PreFunctionHook
#define Perf_PostFunctionHook
#endif
#endif /* PERF_H_ */
|
2301_81045437/classic-platform
|
include/perf.h
|
C
|
unknown
| 1,658
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef CPU_H
#define CPU_H
#include "Std_Types.h"
typedef uint32 imask_t;
//#if defined(__ghs__)
//#include <ppc_ghs.h>
//#endif
//#if defined(__DCC__)
//#include <diab/ppcasm.h>
//#endif
#if defined (CFG_MPC5646B)
#define SIMULATOR() (SIU.MIDR1.R==0uL)
#else
// Used if we are running a T32 instruction set simulator
#define SIMULATOR() (SIU.MIDR.R==0uL)
#endif
// 32-bit write to 32 bit register
#define BIT32(x)
// 16 bit write to 16 bit register
#define BIT16(x)
// Bits EREF and others define as 64 bit regs but in 32 bits regs.
// E.g. #define MSR_PR BIT64TO32(49)
#define BIT64TO32(x) ((uint32)1u<<(uint32)(63u-(x)))
/*
* SPR numbers, Used by set_spr and get_spr macros
*/
#define SPR_LR 8
#define SPR_IVPR 63
#define SPR_IVOR0 400
#define SPR_IVOR1 401
#define SPR_IVOR2 402
#define SPR_IVOR3 403
#define SPR_IVOR4 404
#define SPR_IVOR5 405
#define SPR_IVOR6 406
#define SPR_IVOR7 407
#define SPR_IVOR8 408
#define SPR_IVOR9 409
#define SPR_IVOR10 410
#define SPR_IVOR11 411
#define SPR_IVOR12 412
#define SPR_IVOR13 413
#define SPR_IVOR14 414
#define SPR_IVOR15 415
#define SPR_IVOR32 528
#define SPR_IVOR33 529
#define SPR_IVOR34 530
#if defined (CFG_E200Z7)
#define SPR_IVOR35 531
#endif
#define SPR_DEC 22
#define SPR_DECAR 54
#define SPR_USPRG0 256
#define SPR_TBU_R 269
#define SPR_TBU_W 285
#define SPR_TBL_R 268
#define SPR_TBL_W 284
#define SPR_TCR 340
#define SPR_TSR 336
#define SPR_HID0 1008
#define SPR_L1CSR0 1010
#define SPR_L1CSR1 1011
#define SPR_L1CFG0 515
#define L1CSR0_CINV BIT64TO32(62)
#define L1CSR0_CE BIT64TO32(63)
#define SPR_SRR0 26
#define SPR_SRR1 27
#define SPR_SPRG1_RW_S 273
#define MSR_PR BIT64TO32(49U)
#define MSR_EE BIT64TO32(48U)
#define MSR_SPE BIT64TO32(38U)
#define MSR_DS BIT64TO32(58U)
#define MSR_IS BIT64TO32(59U)
#define MSR_SPE BIT64TO32(38U)
//#define ESR_PTR BIT64TO32(38)
/* Timer control regs
*/
#define TCR_DIE 0x04000000UL
#define TCR_ARE 0x00400000UL
#define TCR_FIE 0x00800000UL
#define HID0_TBEN 0x4000UL
/*
* String macros
*/
#define STR__(x) #x
#define STRINGIFY__(x) STR__(x)
#define Irq_Save(flags) flags = _Irq_Disable_save()
#define Irq_Restore(flags) _Irq_Disable_restore(flags)
/***********************************************************************
* Common macro's
*/
// Misra 2004 2.1, 2012 4.3 : Inhibit lint error 586 for assembly
// language that is encapsulated and isolated in macros
#if defined(__CWCC__) || defined(__DCC__)
#define ASM_ARGS_MEMORY
#define ASM_ARGS_MEMORY_CC
#else
#define ASM_ARGS_MEMORY :::"memory"
#define ASM_ARGS_MEMORY_CC ::: "memory","cc"
#endif
#if defined(CFG_VLE) && !defined(__CWCC__)
#define isync() /*lint -save -e586 -restore */ asm volatile(" se_isync" ASM_ARGS_MEMORY)
#define msync() /*lint -save -e586 -restore */ asm volatile(" se_isync" ASM_ARGS_MEMORY)
#else
// CW does not like taking the right instruction, ie se_xxxx
#define isync() /*lint -save -e586 -restore */ asm volatile(" isync")
#define msync() /*lint -save -e586 -restore */ asm volatile(" isync")
#endif
#define sync() /*lint -save -e586 -restore */ asm volatile(" sync" ASM_ARGS_MEMORY)
#define Irq_Disable() /*lint -save -e586 -restore */ asm volatile (" wrteei 0" ASM_ARGS_MEMORY_CC)
#define Irq_Enable() /*lint -save -e586 -restore */ asm volatile (" wrteei 1" ASM_ARGS_MEMORY_CC)
#define tlbwe() /*lint -save -e586 -restore */ asm volatile (" tlbwe" ASM_ARGS_MEMORY )
#define Irq_SuspendAll() Irq_Disable()
#define Irq_ResumeAll() Irq_Enable()
#define Irq_SuspendOs() Irq_Disable()
#define Irq_ResumeOs() Irq_Enable()
/*-----------------------------------------------------------------*/
/**
* memset that can be used for ecc mem init
* @param msr
*/
extern void memset_uint64(unsigned char *to, const uint64 *val, unsigned long size);
extern void initECC_128bytesAligned(unsigned char *to, unsigned long size);
/*-----------------------------------------------------------------*/
/**
* Sets a value to a specific SPR register
*/
/*lint -save -e10 */
#if defined(__DCC__)
asm void set_spr(uint32 spr_nr, uint32 val)
{
%reg val; con spr_nr
mtspr spr_nr, val
}
#else
// Misra 2004 2.1, 2012 4.3 : Inhibit lint error 586 for assembly
// language that is encapsulated and isolated in macros
// Lint redefinition of set_spr is used to resolve false positive lint warnings caused by
// lint does not recognize assembly code accessing parameter val
# define set_spr(spr_nr, val) /*lint -save -e547 +dset_spr(a,b)=((void)b) -e586 -restore */ \
asm volatile (" mtspr " STRINGIFY__(spr_nr) ",%[_val]" : : [_val] "r" (val))
#endif
/*lint -restore */
/**
* Gets the value from a specific SPR register
*
* Note! Tried lots of other ways to do this but came up empty
*/
//https://community.freescale.com/thread/29234
/*lint -save -e10 */
#if defined(__DCC__) || defined(__ghs__)
uint32 get_spr(uint32 spr_nr); // MISRA 2004 8.1 and 2012 17.3 Resolved by this function declaration
asm uint32 get_spr(uint32 spr_nr)
{
% con spr_nr
mfspr r3, spr_nr
}
#else
//lint --e{923,950,530,9008} LINT:FALSE_POSITIVE:Lint can't handle compound assembler macros
#define get_spr(spr_nr) CC_EXTENSION \
({\
uint32 __val;\
asm volatile (" mfspr %0," STRINGIFY__(spr_nr) : "=r"(__val) : );\
__val;\
})
#endif
/*lint -restore */
/*-----------------------------------------------------------------*/
/**
* Sets a value to a specific DCR register
*/
/*lint -save -e10 */
#if defined(__DCC__)
asm void set_dcr(uint32 dcr_nr, uint32 val)
{
%reg val; con dcr_nr
mtdcr dcr_nr, val
}
#else
# define set_dcr(dcr_nr, val) \
asm volatile (" mtdcr " STRINGIFY__(dcr_nr) ",%[_val]" : : [_val] "r" (val))
#endif
/*lint -restore */
/**
* Gets the value from a specific DCR register
*
*/
/*lint -save -e10 */
#if defined(__DCC__) || defined(__ghs__)
asm uint32 get_dcr(uint32 dcr_nr)
{
% con dcr_nr
mfdcr r3, dcr_nr
}
#else
#define get_dcr(dcr_nr) CC_EXTENSION \
({\
uint32 __val;\
asm volatile (" mfdcr %0," STRINGIFY__(dcr_nr) : "=r"(__val) : );\
__val;\
})
#endif
/*lint -restore */
/**
* Get current value of the msr register
* @return
*/
/*lint -save -e10 */
#if defined(__DCC__)
asm volatile unsigned long get_msr()
{
mfmsr r3
}
#else
static inline unsigned long get_msr( void ) {
uint32 msr;
asm volatile("mfmsr %[msr]":[msr] "=r" (msr ) );
return msr;
}
#endif
/*lint -restore */
/*-----------------------------------------------------------------*/
/**
* Set the current msr to msr
* @param msr
*/
/*lint -save -e10 */
#if defined(__DCC__)
asm volatile void set_msr(unsigned long msr)
{
% reg msr
mtmsr msr
isync
}
#else
static inline void set_msr(unsigned long msr) {
asm volatile ("mtmsr %0" : : "r" (msr) );
// This is just necessary for some manipulations of MSR
isync();
}
#endif
/*lint -restore */
/*-----------------------------------------------------------------*/
/* Count the number of consecutive zero bits starting at ppc-bit 0 */
/*lint -save -e10 */
#if defined(__DCC__)
asm volatile unsigned int cntlzw(unsigned int val)
{
% reg val
cntlzw r3, val
}
#else
/**
* Return number of leading zero's
*
* Examples:
* cntlzw(0x8000_0000) = 0
* cntlzw(0x0000_0000) = 32
* cntlzw(0x0100_0000) = 7
*
* @param val
* @return
*/
static inline unsigned int cntlzw(unsigned int val)
{
unsigned int result;
asm volatile ("cntlzw %[rv],%[val]" : [rv] "=r" (result) : [val] "r" (val) );
return result;
}
#endif
/*lint -restore */
/**
* Integer log2
*
* Examples:
* - ilog2(0x0) = -1
* - ilog2(0x1) = 0
* - ilog2(0x2) = 1
* - ilog2(0x3) = 1
* - ilog2(0x4) = 2
* - ilog2(0x8000_0000)=31
*
* @param val
* @return
*/
static inline uint8 ilog2( uint32 val ) {
return (uint8)(31U - cntlzw(val));
}
#if defined(__ghs__)
/* already in string.h */
#elif defined(__GNUC__)
/* We don't want to use newlib ffs(), use GCC instead */
#define ffs(_x) __builtin_ffs(_x)
#else
static inline int ffs( uint32 val ) {
return 32 - cntlzw(val & (-val));
}
#endif
/* Standard newlib ffs() is REALLY slow since ot loops over all over the place
* IMPROVEMENT: Use _builin_ffs() instead.
*/
/*-----------------------------------------------------------------*/
static inline imask_t _Irq_Disable_save(void)
{
unsigned long result = get_msr();
Irq_Disable();
return result;
}
/*-----------------------------------------------------------------*/
/*lint -save -e10 */
#if defined(__DCC__)
asm volatile void _Irq_Disable_restore(imask_t flags)
{
% reg flags
wrtee flags
}
#else
static inline void _Irq_Disable_restore(imask_t flags) {
asm volatile ("wrtee %0" : : "r" (flags) );
}
#endif
/*lint -restore */
/*-----------------------------------------------------------------*/
#if defined(__DCC__)
#else
#define get_lr(var) \
do { \
unsigned long lr; \
asm volatile("mflr %[lr]":[lr] "=r" (lr ) ); \
var = lr; \
} while(0)
#endif
/*-----------------------------------------------------------------*/
static inline int in_user_mode( void ) {
unsigned long msr;
msr = get_msr();
// In user mode?
return (msr & MSR_PR);
}
static inline void Os_EnterUserMode( void ) {
unsigned long msr;
msr = get_msr();
set_msr(msr | MSR_PR);
}
#if 0
#ifdef USE_T32_SIM
#define mode_to_kernel() k_arch_sim_trap()
#else
#define mode_to_kernel() asm volatile(" sc");
#endif
#endif
/*-----------------------------------------------------------------*/
#if 0
#define SC_CALL(name,...) \
({ \
int rv; \
unsigned int msr = get_msr(); \
if( msr & MSR_PR ) { \
/* asm volatile(" sc"); */\
rv = _ ## name( __VA_ARGS__ ); \
/* set_msr(msr); */ \
} else { \
rv = _ ## name( __VA_ARGS__ ); \
} \
rv; \
})
#endif
/*-----------------------------------------------------------------*/
// StatusType CallService( TrustedFunctionIndexType ix,
// TrustedFunctionParameterRefType params )
typedef void ( * service_func_t)( uint16 , void * );
extern service_func_t oil_trusted_func_list[];
/* Macros for SC_CALL macro */
#define REG_DEF_1 register unsigned int r3 asm ("r3");
#define REG_DEF_2 REG_DEF_1 register unsigned int r4 asm ("r4");
/* Build argument list */
#define REG_IN_1 "r" (r3)
#define REG_IN_2 REG_IN_1 ,"r" (r4)
#if defined(USE_MM_USER_MODE)
/* IMPROVEMENT: Improve it */
#define CallService(index,param) \
({ \
register uint32 r3 asm ("r3"); \
register void * r4 asm ("r4"); \
r3 = index; \
r4 = param; \
asm volatile( \
" sc\r\t" \
: \
: "r" (r3),"r" (r4) ); \
})
#else
#define CallService(index,param)
#endif
#if 0
/* Macros for SC_CALL macro */
#define REG_DEF_1 register unsigned int r3 asm ("r3");
#define REG_DEF_2 REG_DEF_1 register unsigned int r4 asm ("r4");
/* Split the __VA_ARGS__ */
#define SPLIT_ARGS_1(_arg1) r3 = _arg1;
#define SPLIT_ARGS_2(_arg1,_arg2) r3 = _arg1;r4 = _arg2;
/* Build argument list */
#define REG_IN_1 "r" (r3)
#define REG_IN_2 REG_IN_1 ,"r" (r4)
/* System call
*
* name - just for show
* index - The index to the function name above..
* arg_cnt - How many argument the function takes
* ... - var args list..
* */
/*unsigned int t = index; \ */
/* NOTE: __VA_ARGS__ is ISO99 and not all compilers may have support for it*/
#if __STDC_VERSION__ < 199901L
#error Sorry, using macros iso99 VA_ARGS...implement in some other way
#endif
#define SC_CALL(name,index,arg_cnt,...) \
({ \
void * t = _ ## name; \
REG_DEF_ ## arg_cnt \
SPLIT_ARGS_ ## arg_cnt(__VA_ARGS__) \
asm volatile( \
" mr 0,%[t];\r\t" \
" sc\r\t" \
: \
: [t] "r" (t), REG_IN_ ## arg_cnt ); \
})
#endif
/*
* asm volatile( " sc\r\t" ); \
*/
/*-----------------------------------------------------------------*/
#if 0
static inline unsigned int mode_to_kernel( void ) {
unsigned long msr;
msr = get_msr();
// In user mode?
if( msr & MSR_PR ) {
// switch to supervisor mode...
#ifdef USE_T32_SIM
k_arch_sim_trap();
#else
asm volatile(" tw");
#endif
}
return msr;
}
#endif
void Cache_Invalidate( void );
void Cache_EnableU( void );
void Cache_EnableD( void );
void Cache_EnableI( void );
#endif /* CPU_H */
|
2301_81045437/classic-platform
|
include/ppc/Cpu.h
|
C
|
unknown
| 13,699
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef PPC_ASM_H_
#define PPC_ASM_H
/* Context
* =================================================
* We have two context's large and small. Large is saved on
* interrupt and small is saved for everything else.
*
* Layout:
*
* offset
* -------------------------------
* 0--1 : context indicator, 0xde - small, 0xad - large
* 4 : lr
* 8 : cr
* 12 : sp
*
* small layout
* 16-- : General regs r14--r31
*
* large layout
* 16-- : General regs r0--r31
*
*/
#define BIT(x) (1<<(x))
#define PPC_BITS_32(x,offset) ((x)<<(31-(offset)))
#define SPR_DEC 22
#define SPR_DECAR 54
#define SPR_SRR0 26
#define SPR_SRR1 27
#define SPR_CSRR0 58
#define SPR_CSRR1 59
#if defined(CFG_MPC5744P) || defined(CFG_MPC5777M) || defined(CFG_E200Z4) || defined(CFG_E200Z4D) || defined(CFG_E200Z7)
#define SPR_MCSRR0 570
#define SPR_MCSRR1 571
#else
#define SPR_MCSRR0 SPR_CSRR0
#define SPR_MCSRR1 SPR_CSRR1
#endif
#define SPR_SPRG0_RW_S 272
#define SPR_SPRG1_RW_S 273
#define SPR_TBU_R 269
#define SPR_TBU_W 285
#define SPR_TBL_R 268
#define SPR_TBL_W 284
#define SPR_DEAR 61
#define SPR_ESR 62
#define SPR_TSR 336
#define SPR_SPEFSCR 512
#define SPR_MCSR 572
#define SPR_MCAR 573
#define SPR_MAS0 624
#define SPR_MAS1 625
#define SPR_MAS2 626
#define SPR_MAS3 627
#define SPR_MAS4 628
#define SPR_MAS6 630
#if defined(_ASSEMBLER_)
#define MSR_ME (1<<(31-19))
#define MSR_CE (1<<(31-14))
#else
#define MSR_ME ((uint32)1u<<(uint32)(31u-19u))
#define MSR_CE ((uint32)1u<<(uint32)(31u-14u))
#endif
#define ESR_PTR (1<<(31-6))
#define ESR_ST (1<<(31-8))
#if defined(_ASSEMBLER_)
#define ESR_VLEMI (1<<(31-26))
#else
#define ESR_VLEMI (1u<<(uint32)(31u-26u))
#endif
#define ESR_XTE (1<<(31-31))
#define MCSR_BUS_WRERR (1<<(31-29))
#define MCSR_BUS_DRERR (1<<(31-28))
#define SPR_XER 1
#define SPR_CTR 9
/* MAS bits */
#if defined(CFG_E200Z4D)
#define MAS1_TSIZE_4K (2<<7)
#define MAS1_TSIZE_16K (4<<7)
#define MAS1_TSIZE_64K (6<<7)
#define MAS1_TSIZE_256K (8<<7)
#define MAS1_TSIZE_1M (0xa<<7)
#define MAS1_TSIZE_4M (0xc<<7)
#define MAS1_TSIZE_16M (0xe<<7)
#define MAS1_TSIZE_64M (0x10<<7)
#define MAS1_TSIZE_256M (0x12<<7)
#define MAS1_TSIZE_512M (0x13<<7)
#else
#define MAS1_TSIZE_4K (1<<8)
#define MAS1_TSIZE_16K (2<<8)
#define MAS1_TSIZE_64K (3<<8)
#define MAS1_TSIZE_256K (4<<8)
#define MAS1_TSIZE_1M (5<<8)
#define MAS1_TSIZE_4M (6<<8)
#define MAS1_TSIZE_16M (7<<8)
#define MAS1_TSIZE_64M (8<<8)
#define MAS1_TSIZE_256M (9<<8)
#endif
#define MAS2_VLE (1<<5)
#define MAS2_W (1<<4)
#define MAS2_I (1<<3)
#define MAS2_M (1<<2)
#define MAS2_G (1<<1)
#define MAS2_E (1<<0)
#define MAS3_UX (1<<5)
#define MAS3_SX (1<<4)
#define MAS3_UW (1<<3)
#define MAS3_SW (1<<2)
#define MAS3_UR (1<<1)
#define MAS3_SR (1<<0)
#define MAS3_FULL_ACCESS (MAS3_UX+MAS3_UW+MAS3_UR+MAS3_SX+MAS3_SW+MAS3_SR)
#define MM_PSIZE_4K PPC_BITS_32(1,20)
#define MM_PSIZE_16K PPC_BITS_32(2,20)
#define MM_PSIZE_64K PPC_BITS_32(3,20)
#define MM_PSIZE_256K PPC_BITS_32(4,20)
#define MM_PSIZE_1M PPC_BITS_32(5,20)
#define MM_PSIZE_4M PPC_BITS_32(6,20)
#define MM_PSIZE_16M PPC_BITS_32(7,20)
#define MM_PSIZE_64M PPC_BITS_32(8,20)
#define MM_PSIZE_256M PPC_BITS_32(9,20)
/* Memory and cache attribs
* W - Write through, I-cache inhibit,
* M -Memory coherent, G-Guarded,
* E - Endian(big=0)
*/
#define MM_W BIT(0)
#define MM_I BIT(1)
#define MM_M BIT(2)
#define MM_G BIT(3)
#define MM_E BIT(4)
/* memory size */
#define MM_SIZE_8 BIT(16)
#define MM_SIZE_16 BIT(17)
#define MM_SIZE_32 BIT(18)
/* permissions */
#define MM_SX BIT(24)
#define MM_SR BIT(25)
#define MM_SW BIT(26)
#define MM_UX BIT(27)
#define MM_UR BIT(28)
#define MM_UW BIT(29)
#define MM_PERM_STEXT (MM_SR|MM_X)
#define MM_PERM_SDATA (MM_SR|MM_SW)
#if defined(CFG_VLE)
#define VLE_MAS2_VAL MAS2_VLE
#else
#define VLE_MAS2_VAL 0
#endif
#if defined(_ASSEMBLER_)
/* Use as:
* ASM_SECTION_TEXT(.text) - For normal .text or .text_vle
*
*
*/
#if defined(__GNUC__) || defined(__ghs__)
# if defined(__ghs__) && defined(CFG_VLE)
# define ASM_SECTION_TEXT(_x) .section .vletext,"vax"
# define ASM_SECTION(_x) .section #_x,"vax"
# define ASM_CODE_DIRECTIVE() .vle
# else
# define ASM_SECTION_TEXT(_x) .section #_x,"ax"
# define ASM_SECTION(_x) .section #_x,"ax"
# endif
#elif defined(__CWCC__)
# if defined(CFG_VLE)
# define ASM_SECTION_TEXT(_x) .section _x,text_vle
# else
# define ASM_SECTION_TEXT(_x) .section _x,4,"rw"
# endif
# define ASM_SECTION(_x) .section _x,4,"r"
#elif defined(__DCC__)
# if defined(CFG_VLE)
# define ASM_SECTION_TEXT(_x) .section _x,4,"x"
# else
# define ASM_SECTION_TEXT(_x) .section _x,4,"x"
# endif
# define ASM_SECTION(_x) .section _x,4,"r"
#endif
#ifndef ASM_CODE_DIRECTIVE
#define ASM_CODE_DIRECTIVE()
#endif
/*
* PPC vs VLE assembler:
* Most PPC assembler instructions can be pre-processed to VLE assembler.
* I can't find any way to load a 32-bit immediate with just search/replace (number
* of operators differ for addis and e_add2is )
* Thats why there are different load macros below.
*
*/
#if defined(CFG_VLE)
#define LOAD_IND_32( reg, addr) \
e_lis reg, addr@ha; \
e_lwz reg, addr@l(reg)
#define LOAD_ADDR_32(reg, addr ) \
e_lis reg, (addr)@ha; \
e_add16i reg, reg, (addr)@l
#define MULLW(reg1,reg2) \
se_mullw reg1,reg2
#define ADD(reg1,reg2) \
se_add reg1, reg2
#define ADD2IS(reg1,immediate) \
e_add2is reg1, immediate
#define OR2IS(reg1,immediate) \
e_or2is reg1, immediate
#define OR2I(reg1,immediate) \
e_or2i reg1, immediate
#else
#define LOAD_IND_32( reg, addr) \
lis reg, addr@ha; \
lwz reg, addr@l(reg)
#define LOAD_ADDR_32(reg, addr ) \
addis reg, 0, addr@ha; \
addi reg, reg, addr@l
#define MULLW(reg1,reg2) \
mullw reg1,reg1,reg2
#define ADD(reg1,reg2) \
add reg1, reg1, reg2
#define ADD2IS(reg1,immediate) \
addis reg1,reg1, immediate
#define OR2IS(reg1,immediate) \
oris reg1, reg1, immediate
#define OR2I(reg1,immediate) \
ori reg1, reg1, immediate
#endif
/* GPRS */
#define sp 1
#define r0 0
#define r1 1
#define r2 2
#define r3 3
#define r4 4
#define r5 5
#define r6 6
#define r7 7
#define r8 8
#define r9 9
#define r10 10
#define r11 11
#define r12 12
#define r13 13
#define r14 14
#define r15 15
#define r16 16
#define r17 17
#define r18 18
#define r19 19
#define r20 20
#define r21 21
#define r22 22
#define r23 23
#define r24 24
#define r25 25
#define r26 26
#define r27 27
#define r28 28
#define r29 29
#define r30 30
#define r31 31
#if defined(CFG_VLE)
#define lis e_lis
#define li e_li
#define lwz e_lwz
#define lbz e_lbz
#define lbzu e_lbzu
#define stwu e_stwu
#define stw e_stw
#define stb e_stb
#define stbu e_stbu
#define b e_b
#define bne e_bne
#define blt e_blt
//#define addi e_addi /* true ?*/
#define addi e_add16i /* true ?*/
//#define addis e_add16i
#define subi e_subi /* true ?*/
#define blr se_blr
#define rfi se_rfi
#define stb e_stb
#define cmplwi e_cmpl16i
#define cmpd se_cmpl
#define cmpwi se_cmpi
// #define cmpi e_cmpi
#define ori e_ori
#define beq e_beq
#define bge e_bge
//#define bne- e_bne-
#define bne e_bne
#define bgt e_bgt
#define extrwi e_extrwi
#define clrlwi e_clrlwi
#define blrl se_blrl
#define stmw e_stmw
#define bdnz e_bdnz
#define bl e_bl
#define bc e_bc
#define mr se_mr
#define msync se_isync
#define isync se_isync
#define rfci se_rfci
#define rfmci se_rfmci
#define lmw e_lmw
#define srwi e_srwi
#define rlwinm e_rlwinm
#define sc se_sc
#define slwi e_slwi
#define extzh se_extzh
#define mulli e_mulli
#endif
#endif /* _ASSEMBLER_ */
#endif /*PPC_ASM_H_*/
|
2301_81045437/classic-platform
|
include/ppc/asm_ppc.h
|
C
|
unknown
| 9,254
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef MPC55XX_H_
#define MPC55XX_H_
#include "Arc_Types.h"
#if defined(CFG_MPC5554)
#include "mpc5554.h"
#elif defined(CFG_MPC5777C)
#include "MPC5777C.h"
#elif defined(CFG_MPC5516) || defined(CFG_MPC5517)
#include "mpc5516.h"
#elif defined(CFG_MPC5567)
#include "mpc5567.h"
#elif defined(CFG_MPC563XM)
#include "MPC5634M_MLQB80.h"
#elif defined(CFG_MPC5604B)
#include "MPC5604B_0M27V_0102.h"
#elif defined(CFG_SPC560B54)
#include "MPC5607B.h"
#elif defined(CFG_MPC5607B)
#include "MPC5607B.h"
#elif defined(CFG_MPC5606B)
#include "MPC5606B.h"
#elif defined(CFG_MPC5606S)
#include "mpc5606s.h"
#elif defined(CFG_MPC5668)
#include "mpc5668.h"
#elif defined(CFG_MPC5604P)
#include "560xP_HEADER_v1_10_SBCHM.h"
#elif defined(CFG_MPC5744P)
#include "mpc5744P.h"
#elif defined(CFG_MPC5746C)
#include "MPC5746C.h"
#elif defined(CFG_MPC5748G) || defined(CFG_MPC5747C)
#include "mpc5748g.h"
#elif defined(CFG_MPC5777M)
#include "MPC5777M.h"
#elif defined(CFG_MPC5643L)
#include "MPC5643L.h"
#elif defined(CFG_SPC56XL70)
#include "SPC56XL70.h"
#elif defined(CFG_MPC5645S)
#include "MPC5645S.h"
#elif defined(CFG_MPC5646B)
#include "MPC564xBC.h"
#elif defined(CFG_MPC5644A)
#include "MPC5644A.h"
#else
#error NO MCU SELECTED!!!!
#endif
/* Harmonization */
typedef struct EDMA_TCD_STD_tag Dma_TcdType;
/* Exception flags */
#define EXC_NOT_HANDLED 1UL
#define EXC_HANDLED 2UL
#define EXC_ADJUST_ADDR 4UL
/* CRP */
#if defined(CFG_MPC5516) || defined(CFG_MPC5668)
#define CRP_BASE (0xFFFEC000ul)
#define CRP_CLKSRC (CRP_BASE+0x0)
#define CRP_RTCSC (CRP_BASE+0x10)
#define CRP_RTCCNT (CRP_BASE+0x14)
/* 40--4F differs ALOT */
#if (CFG_MPC5516)
#define CRP_WKSE (CRP_BASE+0x44)
#endif
#define CRP_Z1VEC (CRP_BASE+0x50)
#define CRP_Z6VEC (CRP_BASE+0x50)
#define CRP_Z0VEC (CRP_BASE+0x54)
#define CRP_RECPTR (CRP_BASE+0x58)
#define CRP_PSCR (CRP_BASE+0x60)
#endif
#define WKSE_WKCLKSEL_16MHZ_IRC (1<<0)
#define xVEC_xVEC(_x)
#define PSCR_SLEEP 0x00008000ul
#define PSCR_SLP12EN 0x00000800ul
#define PCSR_RAMSEL(_x) ((_x)<<8)
#define xVEC_VLE 0x00000001ul
#define xVEC_xRST 0x00000002ul
#define RECPTR_FASTREC 0x00000002ul
#if defined(CFG_MPC5516)
#define PFCR_LBCFG(x) (x<<(31-3))
#define PFCR_ARB (1<<(31-4))
#define PFCR_PRI (1<<(31-5))
#define PFCR_M0PFE (1<<31-15))
#define PFCR_M1PFE (1<<31-14))
#define PFCR_M2PFE (1<<31-13))
#define PFCR_M3PFE (1<<31-12))
#define PFCR_M4PFE (1<<31-11))
#define PFCR_APC(x) (x<<(31-18))
#define PFCR_WWSC(x) (x<<(31-20))
#define PFCR_RWSC(x) (x<<(31-23))
#define PFCR_DPFEN (1<<(31-25))
#define PFCR_IPFEN (1<<(31-27))
#define PFCR_PFLIM(x) (1<<(31-30))
#define PFCR_BFEN (1<<(31-31))
#endif
// MPC5567
#if defined(CFG_MPC5567) || defined(CFG_MPC5516)
#define ESR_ERNCR 0x02 // Ram non-correctable
#define ESR_EFNCR 0x01 // Flash non-correctable
#endif
/* Modes */
#define MODE_DRUN 3u
#define MODE_RUN0 4u
#define MODE_STANDBY 13u
#endif /* MPC55XX_H_ */
|
2301_81045437/classic-platform
|
include/ppc/mpc55xx.h
|
C
|
unknown
| 3,926
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef CPU_H
#define CPU_H
#include "Std_Types.h"
#if defined(__ghs__)
#include "v800_ghs.h"
#endif
typedef uint32_t imask_t;
#define STR__(x) #x
#define STRINGIFY__(x) STR__(x)
#if defined(__ghs__)
#define Irq_Save(flags) ((flags) = (imask_t)__DIR() )
#define Irq_Restore(flags) (void)(__RIR(flags))
#define Irq_Disable() __DI()
#define Irq_Enable() __EI()
#define synci() asm volatile(" synci" ::: "memory")
#else
#define Irq_Save(flags) flags = _Irq_Disable_save()
#define Irq_Restore(flags) _Irq_Disable_restore(flags)
#define Irq_Disable() asm volatile(" DI" ::: "memory","cc")
#define Irq_Enable() asm volatile(" EI" ::: "memory","cc")
#define synci() asm volatile(" synci" ::: "memory")
#endif
#define Irq_SuspendAll() Irq_Disable()
#define Irq_ResumeAll() Irq_Enable()
#define Irq_SuspendOs() Irq_Disable()
#define Irq_ResumeOs() Irq_Enable()
/**
* Return number of leading zero's from right + 1
*
* Examples:
* sch1r(0x8000_0000) = 32
* sch1r(0x0000_0000) = 0
* sch1r(0x0000_0001) = 1
*
* @param val
* @return
*/
static inline unsigned int sch1r(unsigned int val)
{
unsigned int result;
asm volatile (" SCH1R %[val],%[rv]" : [rv] "=r" (result) : [val] "r" (val));
return result;
}
/**
* Integer log2
*
* Examples:
* - ilog2(0x0) = -1
* - ilog2(0x1) = 0
* - ilog2(0x2) = 1
* - ilog2(0x8000_0000)=31
*
* @param val
* @return
*/
static inline uint8 ilog2( uint32 val ) {
return sch1r(val) - 1;
}
/*
* unsigned int get_sr(unsigned int, unsigned int);
*
* STSR regID, reg2, selID
*/
#if defined(__ghs__)
#define get_sr(spr_nr,sel_id) __STSR(spr_nr,sel_id)
#else
#define get_sr(spr_nr,sel_id) \
({\
uint32 __val;\
asm volatile (" stsr " STRINGIFY__(spr_nr) ",%0," STR__(sel_id) : "=r"(__val) : );\
__val;\
})
#endif
static inline unsigned long get_psw( void ) {
uint32 psw;
asm volatile(" stsr PSW,%[psw]":[psw] "=r" (psw ) );
return psw;
}
static inline unsigned long _Irq_Disable_save(void)
{
unsigned long result = get_psw();
Irq_Disable();
return result;
}
static inline void _Irq_Disable_restore(unsigned long flags) {
/* restore PSW */
asm volatile(" ldsr %0,PSW" : : "r" (flags) );
}
#endif /* CPU_H */
|
2301_81045437/classic-platform
|
include/renesas/Cpu.h
|
C
|
unknown
| 3,125
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ASM_RH850_H_
#define ASM_RH850_H_
#define EXC_SYSERR 1
#define EXC_HVTRAP 2
#define EXC_FETRAP 3
#define EXC_TRAP0 4
#define EXC_TRAP1 5
#define EXC_RIE 6
#define EXC_FPP_FPI 7
#define EXC_UCPOP 8
#define EXC_MIP_MDP 9
#define EXC_PIE 0xa
#define EXC_DEBUG 0xb
#define EXC_MAE 0xc
#define EXC_RFU 0xd
#define EXC_FENMI 0xe
#define EXC_FEINT 0xf
#if defined(_ASSEMBLER_)
/* Use as:
* ASM_SECTION_TEXT(.text) - For normal .text or .text_vle
*
*
*/
#if defined(__ghs__)
# define ASM_SECTION_TEXT(_x) .section .vletext,"vax"
# define ASM_SECTION(_x) .section #_x,"vax"
# define ASM_CODE_DIRECTIVE() .vle
# define ASM_NEED(_x) .need _x
#elif defined(__GNUC__)
# define ASM_SECTION_TEXT(_x) .section #_x,"ax"
# define ASM_SECTION(_x) .section #_x,"ax"
# define ASM_NEED(_x)
#elif defined(__DCC__)
# define ASM_SECTION_TEXT(_x) .section _x,4,"x"
# define ASM_SECTION(_x) .section _x,4,"r"
#endif
#ifndef ASM_CODE_DIRECTIVE
#define ASM_CODE_DIRECTIVE()
#endif
#define LOAD_ADDR_32(reg, addr ) \
addis reg, 0, addr@ha; \
addi reg, reg, addr@l
#define MOV32(x, y) movhi hi(x),zero,y ; movea lo(x),y,y
#if defined(__ghs__)
#define CMP16(_imm16,_x) cmp _imm16,_x
#else
#define CMP16(_imm16,_x) movea _imm16, r0, r1; cmp r1, _x
#endif
#define ASM_BALIGN(_x) .balign _x
//extern const char _ep[];
//extern const char _tp[];
//extern const char _gp[];
/* GPRS */
//#define sp 1
//#define r0 0
//#define r1 1
//#define r2 2
//#define r3 3
//#define r4 4
//#define r5 5
//#define r6 6
//#define r7 7
//#define r8 8
//#define r9 9
//#define r10 10
//#define r11 11
//#define r12 12
//#define r13 13
//#define r14 14
//#define r15 15
//#define r16 16
//#define r17 17
//#define r18 18
//#define r19 19
//#define r20 20
//#define r21 21
//#define r22 22
//#define r23 23
//#define r24 24
//#define r25 25
//#define r26 26
//#define r27 27
//#define r28 28
//#define r29 29
//#define r30 30
//#define r31 31
#endif /* _ASSEMBLER_ */
#endif /*ASM_RH850_H_*/
|
2301_81045437/classic-platform
|
include/renesas/asm_rh850.h
|
C
|
unknown
| 3,037
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DCM_MEMMAP_H_
#define DCM_MEMMAP_H_
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with Dcm service component.
#endif
#endif /* DCM_MEMMAP_H_ */
|
2301_81045437/classic-platform
|
include/rte/Dcm_MemMap.h
|
C
|
unknown
| 946
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DEM_MEMMAP_H_
#define DEM_MEMMAP_H_
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with Dem service component.
#endif
#endif /* DEM_MEMMAP_H_ */
|
2301_81045437/classic-platform
|
include/rte/Dem_MemMap.h
|
C
|
unknown
| 946
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef FIM_MEMMAP_H_
#define FIM_MEMMAP_H_
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with FiM service component.
#endif
#endif /* FIM_MEMMAP_H_ */
|
2301_81045437/classic-platform
|
include/rte/FiM_MemMap.h
|
C
|
unknown
| 940
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_COMM_TYPE_H_
#define RTE_COMM_TYPE_H_
#define COMMM_NOT_SERVICE_COMPONENT
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with ComM service component.
#include "Rte_Type.h"
#else
/** Current mode of the Communication Manager (main state of the state machine). */
/** @req COMM879 */
typedef uint8 ComM_ModeType; /** @req COMM867 @req COMM868 */
/** Inhibition status of ComM. */
typedef uint8 ComM_InhibitionStatusType;
typedef uint8 ComM_UserHandleType;
#endif
#endif // RTE_COMM_TYPE_H_
|
2301_81045437/classic-platform
|
include/rte/Rte_ComM_Type.h
|
C
|
unknown
| 1,305
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_DCM_TYPE_H_
#define RTE_DCM_TYPE_H_
#if !defined(DCM_UNIT_TEST) || (DCM_UNIT_TEST == STD_OFF)
#define DCM_NOT_SERVICE_COMPONENT
#endif
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with Dcm service component.
#include "Rte_Type.h"
#define DCM_RES_POS_OK ((Dcm_ConfirmationStatusType)0x00)
#define DCM_RES_POS_NOT_OK ((Dcm_ConfirmationStatusType)0x01)
#define DCM_RES_NEG_OK ((Dcm_ConfirmationStatusType)0x02)
#define DCM_RES_NEG_NOT_OK ((Dcm_ConfirmationStatusType)0x03)
/*
* Dcm_SesCtrlType
*/
#ifndef DCM_DEFAULT_SESSION
#define DCM_DEFAULT_SESSION ((Dcm_SesCtrlType)0x01)
#endif
#ifndef DCM_PROGRAMMING_SESSION
#define DCM_PROGRAMMING_SESSION ((Dcm_SesCtrlType)0x02)
#endif
#ifndef DCM_EXTENDED_DIAGNOSTIC_SESSION
#define DCM_EXTENDED_DIAGNOSTIC_SESSION ((Dcm_SesCtrlType)0x03)
#endif
#ifndef DCM_SAFTEY_SYSTEM_DIAGNOSTIC_SESSION
#define DCM_SAFTEY_SYSTEM_DIAGNOSTIC_SESSION ((Dcm_SesCtrlType)0x04)
#endif
#ifndef DCM_OBD_SESSION
#define DCM_OBD_SESSION ((Dcm_SesCtrlType)0x05)//only used for OBD diagnostic
#endif
#ifndef DCM_ALL_SESSION_LEVEL
#define DCM_ALL_SESSION_LEVEL ((Dcm_SesCtrlType)0xFF)
#endif
#else
typedef uint8 Dcm_ConfirmationStatusType;
#define DCM_RES_POS_OK ((Dcm_ConfirmationStatusType)0x00)
#define DCM_RES_POS_NOT_OK ((Dcm_ConfirmationStatusType)0x01)
#define DCM_RES_NEG_OK ((Dcm_ConfirmationStatusType)0x02)
#define DCM_RES_NEG_NOT_OK ((Dcm_ConfirmationStatusType)0x03)
typedef uint8 Dcm_NegativeResponseCodeType;
typedef uint8 Dcm_OpStatusType;
typedef uint8 Dcm_ProtocolType;
typedef uint8 Dcm_SesCtrlType;
/*
* Dcm_SesCtrlType
*/
#ifndef DCM_DEFAULT_SESSION
#define DCM_DEFAULT_SESSION ((Dcm_SesCtrlType)0x01)
#endif
#ifndef DCM_PROGRAMMING_SESSION
#define DCM_PROGRAMMING_SESSION ((Dcm_SesCtrlType)0x02)
#endif
#ifndef DCM_EXTENDED_DIAGNOSTIC_SESSION
#define DCM_EXTENDED_DIAGNOSTIC_SESSION ((Dcm_SesCtrlType)0x03)
#endif
#ifndef DCM_SAFTEY_SYSTEM_DIAGNOSTIC_SESSION
#define DCM_SAFTEY_SYSTEM_DIAGNOSTIC_SESSION ((Dcm_SesCtrlType)0x04)
#endif
#ifndef DCM_OBD_SESSION
#define DCM_OBD_SESSION ((Dcm_SesCtrlType)0x05)//only used for OBD diagnostic
#endif
#ifndef DCM_ALL_SESSION_LEVEL
#define DCM_ALL_SESSION_LEVEL ((Dcm_SesCtrlType)0xFF)
#endif
typedef uint8 Dcm_SecLevelType;
typedef uint8 Dcm_RoeStateType;
typedef uint8 DTRStatusType;
#endif
#endif /*RTE_DCM_TYPE_H_*/
|
2301_81045437/classic-platform
|
include/rte/Rte_Dcm_Type.h
|
C
|
unknown
| 3,569
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_DEM_TYPE_H_
#define RTE_DEM_TYPE_H_
#define DEM_NOT_SERVICE_COMPONENT
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with Dem service component.
#include "Rte_Type.h"
typedef uint32 Dem_DTCType;
typedef sint8 Dem_FaultDetectionCounterType;
#else
typedef uint32 Dem_DTCType;
typedef uint16 Dem_EventIdType;
typedef sint8 Dem_FaultDetectionCounterType;
typedef uint8 Dem_IndicatorStatusType;
typedef uint8 Dem_InitMonitorReasonType;
typedef uint8 Dem_OperationCycleIdType;
typedef uint8 Dem_OperationCycleStateType;
typedef uint8 Dem_EventStatusType;
typedef uint8 Dem_EventStatusExtendedType;
typedef uint8 Dem_DTCFormatType;
typedef uint8 Dem_DTCOriginType;
typedef uint8 Dem_ReturnClearDTCType;
typedef uint16 Dem_RatioIdType;
#endif
#endif /* RTE_DEM_TYPE_H_ */
|
2301_81045437/classic-platform
|
include/rte/Rte_Dem_Type.h
|
C
|
unknown
| 1,588
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_DLT_TYPE_H_
#define RTE_DLT_TYPE_H_
#define DLT_NOT_SERVICE_COMPONENT
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with Dlt Service Component.
#include "Rte_Type.h"
/* @req SWS_Dlt_00230 */
/* @req SWS_Dlt_00010 */
/** Enum literals for Dlt_MessageLogLevelType */
#ifndef DLT_LOG_OFF
#define DLT_LOG_OFF 0U
#endif /* DLT_LOG_OFF */
#ifndef DLT_LOG_FATAL
#define DLT_LOG_FATAL 1U
#endif /* DLT_LOG_FATAL */
#ifndef DLT_LOG_ERROR
#define DLT_LOG_ERROR 2U
#endif /* DLT_LOG_ERROR */
#ifndef DLT_LOG_WARN
#define DLT_LOG_WARN 3U
#endif /* DLT_LOG_WARN */
#ifndef DLT_LOG_INFO
#define DLT_LOG_INFO 4U
#endif /* DLT_LOG_INFO */
#ifndef DLT_LOG_DEBUG
#define DLT_LOG_DEBUG 5U
#endif /* DLT_LOG_DEBUG */
#ifndef DLT_LOG_VERBOSE
#define DLT_LOG_VERBOSE 6U
#endif /* DLT_LOG_VERBOSE */
/** Enum literals for Dlt_MessageTraceType */
#ifndef DLT_TRACE_VARIABLE
#define DLT_TRACE_VARIABLE 1U
#endif /* DLT_TRACE_VARIABLE */
#ifndef DLT_TRACE_FUNCTION_IN
#define DLT_TRACE_FUNCTION_IN 2U
#endif /* DLT_TRACE_FUNCTION_IN */
#ifndef DLT_TRACE_FUNCTION_OUT
#define DLT_TRACE_FUNCTION_OUT 3U
#endif /* DLT_TRACE_FUNCTION_OUT */
#ifndef DLT_TRACE_STATE
#define DLT_TRACE_STATE 4U
#endif /* DLT_TRACE_STATE */
#ifndef DLT_TRACE_VFB
#define DLT_TRACE_VFB 5U
#endif /* DLT_TRACE_VFB */
#else
/* @req SWS_Dlt_00225 */
typedef uint32 Dlt_SessionIDType;
/* @req SWS_Dlt_00226 *//* @req SWS_Dlt_00127 *//* @req SWS_Dlt_00312 */
typedef uint8 Dlt_ApplicationIDType[4];
/* @req SWS_Dlt_00227 *//* @req SWS_Dlt_00128 *//* @req SWS_Dlt_00313 */
typedef uint8 Dlt_ContextIDType[4];
/* @req SWS_Dlt_00228 */
typedef uint32 Dlt_MessageIDType;
/* @req SWS_Dlt_00229 */
typedef uint8 Dlt_MessageOptionsType;
/* @req SWS_Dlt_00235 */
typedef uint16 Dlt_MessageArgumentCount;
typedef uint8 Dlt_MessageLogLevelType;
/* @req SWS_Dlt_00236 */
typedef struct {
Dlt_MessageArgumentCount arg_count;
Dlt_MessageLogLevelType log_level;
Dlt_MessageOptionsType options;
Dlt_ContextIDType context_id;
Dlt_ApplicationIDType app_id;
} Dlt_MessageLogInfoType;
/* @req SWS_Dlt_00230 */
/* @req SWS_Dlt_00010 */
/** Enum literals for Dlt_MessageLogLevelType */
#ifndef DLT_LOG_OFF
#define DLT_LOG_OFF 0U
#endif /* DLT_LOG_OFF */
#ifndef DLT_LOG_FATAL
#define DLT_LOG_FATAL 1U
#endif /* DLT_LOG_FATAL */
#ifndef DLT_LOG_ERROR
#define DLT_LOG_ERROR 2U
#endif /* DLT_LOG_ERROR */
#ifndef DLT_LOG_WARN
#define DLT_LOG_WARN 3U
#endif /* DLT_LOG_WARN */
#ifndef DLT_LOG_INFO
#define DLT_LOG_INFO 4U
#endif /* DLT_LOG_INFO */
#ifndef DLT_LOG_DEBUG
#define DLT_LOG_DEBUG 5U
#endif /* DLT_LOG_DEBUG */
#ifndef DLT_LOG_VERBOSE
#define DLT_LOG_VERBOSE 6U
#endif /* DLT_LOG_VERBOSE */
typedef uint8 Dlt_MessageTraceType;
/* @req SWS_Dlt_00237 */
typedef struct {
Dlt_MessageTraceType trace_info;
Dlt_MessageOptionsType options;
Dlt_ContextIDType context;
Dlt_ApplicationIDType app_id;
} Dlt_MessageTraceInfoType;
/** Enum literals for Dlt_MessageTraceType */
#ifndef DLT_TRACE_VARIABLE
#define DLT_TRACE_VARIABLE 1U
#endif /* DLT_TRACE_VARIABLE */
#ifndef DLT_TRACE_FUNCTION_IN
#define DLT_TRACE_FUNCTION_IN 2U
#endif /* DLT_TRACE_FUNCTION_IN */
#ifndef DLT_TRACE_FUNCTION_OUT
#define DLT_TRACE_FUNCTION_OUT 3U
#endif /* DLT_TRACE_FUNCTION_OUT */
#ifndef DLT_TRACE_STATE
#define DLT_TRACE_STATE 4U
#endif /* DLT_TRACE_STATE */
#ifndef DLT_TRACE_VFB
#define DLT_TRACE_VFB 5U
#endif /* DLT_TRACE_VFB */
typedef uint8 Dlt_ReturnType;
#endif /* USE_RTE */
#endif /* RTE_DLT_TYPE_H_ */
|
2301_81045437/classic-platform
|
include/rte/Rte_Dlt_Type.h
|
C
|
unknown
| 4,447
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_DOIP_H
#define RTE_DOIP_H
#endif /* RTE_DOIP_H */
|
2301_81045437/classic-platform
|
include/rte/Rte_DoIP.h
|
C
|
unknown
| 819
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_ECUM_TYPE_H_
#define RTE_ECUM_TYPE_H_
#define ECUM_NOT_SERVICE_COMPONENT
#ifdef USE_RTE
#warning This file should only be used when NOT using an EcuM Service Component.
#include "Rte_Type.h"
#else
/* @req SWS_EcuMf_00104 */
/* @req SWS_EcuM_02664 */
/* @req SWS_EcuM_00507 */
/* @req SWS_EcuM_04039 */ /*@req SWS_EcuMf_00105*/
typedef uint8 EcuM_StateType;
/* @req SWS_EcuM_04067 */ /*@req SWS_EcuMf_00048*/
typedef uint8 EcuM_UserType;
/* @req SWS_EcuM_04042 */ /*@req SWS_EcuMf_00036*/
typedef uint8 EcuM_BootTargetType;
#endif
#endif /* RTE_ECUM_TYPE_H_ */
|
2301_81045437/classic-platform
|
include/rte/Rte_EcuM_Type.h
|
C
|
unknown
| 1,344
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_FIM_TYPE_H_
#define RTE_FIM_TYPE_H_
#define FIM_NOT_SERVICE_COMPONENT
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with FiM service component.
#include "Rte_Type.h"
typedef uint16 FiM_FunctionIdType;
#else
typedef uint16 FiM_FunctionIdType;
#endif
#endif /* RTE_FIM_TYPE_H_ */
|
2301_81045437/classic-platform
|
include/rte/Rte_FiM_Type.h
|
C
|
unknown
| 1,085
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_MAIN_H_
#define RTE_MAIN_H_
#ifdef USE_RTE
#warning This file should only be used when not using an RTE.
#endif
Std_ReturnType Rte_Start( void );
Std_ReturnType Rte_Stop( void );
#endif /*RTE_MAIN_H_*/
|
2301_81045437/classic-platform
|
include/rte/Rte_Main.h
|
C
|
unknown
| 985
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.0.3 */
#ifndef RTE_NVM_TYPE_H_
#define RTE_NVM_TYPE_H_
#define NVM_NOT_SERVICE_COMPONENT
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with NvM Service Component.
#include "Rte_Type.h"
#define NVM_REQ_OK 0x00
#define NVM_REQ_NOT_OK 0x01
#define NVM_REQ_PENDING 0x02
#define NVM_REQ_INTEGRITY_FAILED 0x03
#define NVM_REQ_BLOCK_SKIPPED 0x04
#define NVM_REQ_NV_INVALIDATED 0x05
#define NVM_REQ_CANCELLED 0x06
#define NVM_MULTI_BLOCK_REQUEST_ID 0
#define NVM_REDUNDANT_BLOCK_FOR_CONFIG_ID 1
#else
typedef uint8 NvM_RequestResultType; /** @req NVM470 */
#define NVM_REQ_OK 0x00
#define NVM_REQ_NOT_OK 0x01
#define NVM_REQ_PENDING 0x02
#define NVM_REQ_INTEGRITY_FAILED 0x03
#define NVM_REQ_BLOCK_SKIPPED 0x04
#define NVM_REQ_NV_INVALIDATED 0x05
#define NVM_REQ_CANCELLED 0x06
/** @req NVM471 */
/* 0 and 1 is reserved, sequential order */
typedef uint16 NvM_BlockIdType;
#define NVM_MULTI_BLOCK_REQUEST_ID 0
#define NVM_REDUNDANT_BLOCK_FOR_CONFIG_ID 1
#endif
#endif /* RTE_ECUM_TYPE_H_ */
|
2301_81045437/classic-platform
|
include/rte/Rte_NvM_Type.h
|
C
|
unknown
| 2,014
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.3.0 */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifndef RTE_OS_TYPE_H_
#define RTE_OS_TYPE_H_
#define OS_NOT_SERVICE_COMPONENT
#ifdef USE_RTE
#include "Rte_Type.h"
#else
typedef uint32 CounterType; /* @req SWS_Os_00786 */
typedef uint32 TickType; /*@req OSEK_SWS_AL_00024 */
typedef uint32* TickRefType; /*@req OSEK_SWS_AL_00024 */
#endif
#endif /* RTE_OS_TYPE_H_ */
/** @req SWS_Rte_07126 */
#ifdef __cplusplus
} /* extern "C" */
#endif /* __cplusplus */
|
2301_81045437/classic-platform
|
include/rte/Rte_Os_Type.h
|
C
|
unknown
| 1,303
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_RTM_TYPE_H_
#define RTE_RTM_TYPE_H_
#define RTM_NOT_SERVICE_COMPONENT
#ifdef USE_RTE
#warning This file should only be used when NOT using an Rtm Service Component.
#include "Rte_Type.h"
#else
/* Std_Types.h is normally included by Rte_Type.h */
#include "Std_Types.h"
/* Structure type Rtm_BswErrorType */
typedef struct _Rtm_BswErrorType_ Rtm_BswErrorType;
struct _Rtm_BswErrorType_ {
uint8 moduleId;
uint8 errorId;
};
/* Structure type Rtm_DetErrorType */
typedef struct _Rtm_DetErrorType_ Rtm_DetErrorType;
struct _Rtm_DetErrorType_ {
uint16 moduleId;
uint8 instanceId;
uint8 apiId;
uint8 errorId;
};
/* Structure type Rtm_SmalErrorType */
/* Structure type Rtm_SmalErrorType */
typedef struct _Rtm_SmalErrorType_ Rtm_SmalErrorType;
struct _Rtm_SmalErrorType_ {
uint32 addr;
uint32 flags;
uint32 dump[4];
};
/* Redefinition type Rtm_ErrorType */
typedef uint8 Rtm_ErrorType;
/* Structure type Rtm_HookErrorType */
typedef struct _Rtm_HookErrorType_ Rtm_HookErrorType;
struct _Rtm_HookErrorType_ {
uint32 flags;
uint32 vector;
};
/* Redefinition type Rtm_StatusType */
typedef uint8 Rtm_StatusType;
/* Union type Rtm_ErrorUnionType */
typedef union {
Rtm_SmalErrorType smal;
Rtm_DetErrorType det;
Rtm_HookErrorType hook;
Rtm_BswErrorType bsw;
} Rtm_ErrorUnionType;
/* Structure type Rtm_EntryType */
typedef struct _Rtm_EntryType_ Rtm_EntryType;
struct _Rtm_EntryType_ {
Rtm_ErrorType errorType;
Rtm_ErrorUnionType error;
};
/** --- ENUMERATION DATA TYPES ------------------------------------------------------------------ */
/** Enum literals for Rtm_ErrorType */
#ifndef RTM_ERRORTYPE_SMAL
#define RTM_ERRORTYPE_SMAL 0U
#endif /* RTM_ERRORTYPE_SMAL */
#ifndef RTM_ERRORTYPE_DET
#define RTM_ERRORTYPE_DET 1U
#endif /* RTM_ERRORTYPE_DET */
#ifndef RTM_ERRORTYPE_HOOK
#define RTM_ERRORTYPE_HOOK 2U
#endif /* RTM_ERRORTYPE_HOOK */
#ifndef RTM_ERRORTYPE_BSW
#define RTM_ERRORTYPE_BSW 3U
#endif /* RTM_ERRORTYPE_BSW */
/** Enum literals for Rtm_StatusType */
#ifndef RTM_ALARM_STATUS_OK
#define RTM_ALARM_STATUS_OK 0U
#endif /* RTM_ALARM_STATUS_OK */
#ifndef RTM_ALARM_STATUS_NOK
#define RTM_ALARM_STATUS_NOK 1U
#endif /* RTM_ALARM_STATUS_NOK */
#ifndef RTM_ALARM_STATUS_INVALID
#define RTM_ALARM_STATUS_INVALID 2U
#endif /* RTM_ALARM_STATUS_INVALID */
#endif
#endif /* RTE_RTM_TYPE_H_ */
|
2301_81045437/classic-platform
|
include/rte/Rte_Rtm_Type.h
|
C
|
unknown
| 3,238
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_STBM_TYPE_H_
#define RTE_STBM_TYPE_H_
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with StbM service component.
#include "Rte_Type.h"
#else
/* @req 4.2.2/SWS_StbM_00239 */
typedef uint8 StbM_TimeBaseStatusType;
/* @req 4.2.2/SWS_StbM_00241 */
typedef struct{
StbM_TimeBaseStatusType timeBaseStatus; /* Status of the Time Base */
uint32 nanoseconds; /* Nanoseconds part of the time */
uint32 seconds; /* 32 bit LSB of the 48 bits Seconds part of the time */
uint16 secondsHi; /* 16 bit MSB of the 48 bits Seconds part of the time*/
}StbM_TimeStampType;
/* @req 4.2.2/SWS_StbM_00242 */
typedef struct{
StbM_TimeBaseStatusType timeBaseStatus; /* Status of the Time Base */
uint32 nanoseconds; /* Nanoseconds part of the time */
uint64 seconds; /* 48 bit Seconds part of the time */
}StbM_TimeStampExtendedType;
/* @req 4.2.2/SWS_StbM_00243 */
typedef struct{
uint8 userDataLength; /* User Data Length in bytes */
uint8 userByte0;
uint8 userByte1;
uint8 userByte2;
}StbM_UserDataType;
#endif
#endif
|
2301_81045437/classic-platform
|
include/rte/Rte_StbM_Type.h
|
C
|
unknown
| 1,899
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef RTE_WDGM_TYPE_H_
#define RTE_WDGM_TYPE_H_
#define WDGM_NOT_SERVICE_COMPONENT
#ifdef USE_RTE
#warning This file should only be used when NOT using an WdgM Service Component.
#include "Rte_Type.h"
#else
/* Std_Types.h is normally included by Rte_Type.h */
#include "Std_Types.h"
typedef uint8 WdgM_LocalStatusType;
typedef uint8 WdgM_GlobalStatusType;
typedef uint8 WdgM_ModeType;
/* NOTE: datatype depends on the maximal configured amount of supervised entities
* currently we assume that 16bit are necessary (alternative would be 8)
*/
typedef uint16 WdgM_SupervisedEntityIdType;
/* NOTE: datatype depends on the maximal configured amount of supervised entities
* currently we assume that 16bit are necessary (alternative would be 8)
*/
typedef uint16 WdgM_CheckpointIdType;
/** --- ENUMERATION DATA TYPES ------------------------------------------------------------------ */
/** Enum literals for WdgM_GlobalStatusType */
#ifndef WDGM_GLOBAL_STATUS_OK
#define WDGM_GLOBAL_STATUS_OK 0U
#endif /* WDGM_GLOBAL_STATUS_OK */
#ifndef WDGM_GLOBAL_STATUS_FAILED
#define WDGM_GLOBAL_STATUS_FAILED 1U
#endif /* WDGM_GLOBAL_STATUS_FAILED */
#ifndef WDGM_GLOBAL_STATUS_EXPIRED
#define WDGM_GLOBAL_STATUS_EXPIRED 2U
#endif /* WDGM_GLOBAL_STATUS_EXPIRED */
#ifndef WDGM_GLOBAL_STATUS_STOPPED
#define WDGM_GLOBAL_STATUS_STOPPED 3U
#endif /* WDGM_GLOBAL_STATUS_STOPPED */
#ifndef WDGM_GLOBAL_STATUS_DEACTIVATED
#define WDGM_GLOBAL_STATUS_DEACTIVATED 4U
#endif /* WDGM_GLOBAL_STATUS_DEACTIVATED */
/** Enum literals for WdgM_LocalStatusType */
#ifndef WDGM_LOCAL_STATUS_OK
#define WDGM_LOCAL_STATUS_OK 0U
#endif /* WDGM_LOCAL_STATUS_OK */
#ifndef WDGM_LOCAL_STATUS_FAILED
#define WDGM_LOCAL_STATUS_FAILED 1U
#endif /* WDGM_LOCAL_STATUS_FAILED */
#ifndef WDGM_LOCAL_STATUS_EXPIRED
#define WDGM_LOCAL_STATUS_EXPIRED 2U
#endif /* WDGM_LOCAL_STATUS_EXPIRED */
#ifndef WDGM_LOCAL_STATUS_DEACTIVATED
#define WDGM_LOCAL_STATUS_DEACTIVATED 4U
#endif /* WDGM_LOCAL_STATUS_DEACTIVATED */
/** Enum literals for WdgM_ModeType */
#ifndef SUPERVISION_DEACTIVATED
#define SUPERVISION_DEACTIVATED 0U
#endif /* SUPERVISION_DEACTIVATED */
#ifndef SUPERVISION_FAILED
#define SUPERVISION_FAILED 1U
#endif /* SUPERVISION_FAILED */
#ifndef SUPERVISION_EXPIRED
#define SUPERVISION_EXPIRED 2U
#endif /* SUPERVISION_EXPIRED */
#ifndef SUPERVISION_STOPPED
#define SUPERVISION_STOPPED 3U
#endif /* SUPERVISION_STOPPED */
#ifndef SUPERVISION_OK
#define SUPERVISION_OK 4U
#endif /* SUPERVISION_OK */
/** --- MODE TYPES ------------------------------------------------------------------------------ */
#ifndef RTE_MODETYPE_WdgMMode
#define RTE_MODETYPE_WdgMMode
typedef uint8 Rte_ModeType_WdgMMode;
#endif
#ifndef RTE_TRANSITION_WdgMMode
#define RTE_TRANSITION_WdgMMode 255U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_DEACTIVATED
#define RTE_MODE_WdgMMode_SUPERVISION_DEACTIVATED 0U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_EXPIRED
#define RTE_MODE_WdgMMode_SUPERVISION_EXPIRED 2U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_FAILED
#define RTE_MODE_WdgMMode_SUPERVISION_FAILED 1U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_OK
#define RTE_MODE_WdgMMode_SUPERVISION_OK 4U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_STOPPED
#define RTE_MODE_WdgMMode_SUPERVISION_STOPPED 3U
#endif
#ifndef RTE_MODETYPE_WdgMMode
#define RTE_MODETYPE_WdgMMode
typedef uint8 Rte_ModeType_WdgMMode;
#endif
#ifndef RTE_TRANSITION_WdgMMode
#define RTE_TRANSITION_WdgMMode 255U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_DEACTIVATED
#define RTE_MODE_WdgMMode_SUPERVISION_DEACTIVATED 0U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_EXPIRED
#define RTE_MODE_WdgMMode_SUPERVISION_EXPIRED 2U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_FAILED
#define RTE_MODE_WdgMMode_SUPERVISION_FAILED 1U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_OK
#define RTE_MODE_WdgMMode_SUPERVISION_OK 4U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_STOPPED
#define RTE_MODE_WdgMMode_SUPERVISION_STOPPED 3U
#endif
#ifndef RTE_MODETYPE_WdgMMode
#define RTE_MODETYPE_WdgMMode
typedef uint8 Rte_ModeType_WdgMMode;
#endif
#ifndef RTE_TRANSITION_WdgMMode
#define RTE_TRANSITION_WdgMMode 255U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_DEACTIVATED
#define RTE_MODE_WdgMMode_SUPERVISION_DEACTIVATED 0U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_EXPIRED
#define RTE_MODE_WdgMMode_SUPERVISION_EXPIRED 2U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_FAILED
#define RTE_MODE_WdgMMode_SUPERVISION_FAILED 1U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_OK
#define RTE_MODE_WdgMMode_SUPERVISION_OK 4U
#endif
#ifndef RTE_MODE_WdgMMode_SUPERVISION_STOPPED
#define RTE_MODE_WdgMMode_SUPERVISION_STOPPED 3U
#endif
#endif
#endif /* RTE_WDGM_TYPE_H_ */
|
2301_81045437/classic-platform
|
include/rte/Rte_WdgM_Type.h
|
C
|
unknown
| 5,660
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDGM_MEMMAP_H_
#define WDGM_MEMMAP_H_
#ifdef USE_RTE
#warning This file should only be used when not using an RTE with WdgM service component.
#endif
#endif /* WDGM_MEMMAP_H_ */
|
2301_81045437/classic-platform
|
include/rte/WdgM_MemMap.h
|
C
|
unknown
| 950
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef SHELL_H_
#define SHELL_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "sys/queue.h"
#include "arc.h"
#define SHELL_F_
typedef int (*ShellFuncT)(int argc, char *argv[]);
typedef struct ShellCmd {
ShellFuncT func;
int argMin; /* excluding cmd, from 0 -> */
int argMax; /* excluding cmd, from 0 -> */
const char *cmd;
const char *shortDesc;
const char *longDesc;
TAILQ_ENTRY(ShellCmd) cmdEntry;
} ShellCmdT;
int SHELL_AddCmd(ShellCmdT *shellCmd);
int SHELL_RunCmd(const char *cmdArgs, int *cmdRv );
int SHELL_Init( void );
int SHELL_Mainloop( void );
#define SHELL_E_OK 0
#define SHELL_E_CMD_TOO_LONG 1
#define SHELL_E_CMD_IS_NULL 2
#define SHELL_E_NO_SUCH_CMD 3
#define _SHELL_MAJOR_ 0
#define _SHELL_MINOR_ 2
#define _SHELL_PATCHLEVEL_ 0
#define SHELL_VERSION (_SHELL_MAJOR_ * 10000 + _SHELL_MINOR_ * 100 + _SHELL_PATCHLEVEL_)
#define SHELL_VERSION_STR STRSTR__(_SHELL_MAJOR_) "." STRSTR__(_SHELL_MINOR_) "." STRSTR__(_SHELL_PATCHLEVEL_)
#ifdef __cplusplus
}
#endif
#endif /* SHELL_H_ */
|
2301_81045437/classic-platform
|
include/shell.h
|
C
|
unknown
| 1,875
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef SLEEP_H_
#define SLEEP_H_
#include "Os.h"
#define SLEEP(_x_) \
do{ \
TaskType task; \
GetTaskID(&task); \
Sleep(_x_, task, EVENT_MASK_SLEEP_ALARM ); \
WaitEvent(EVENT_MASK_SLEEP_ALARM); \
ClearEvent(EVENT_MASK_SLEEP_ALARM); \
}while(0);
void Sleep(uint32_t nofTicks, TaskType TaskID, EventMaskType Mask );
void SleepInit();
#endif /* SLEEP_H_ */
|
2301_81045437/classic-platform
|
include/sleep.h
|
C
|
unknown
| 1,153
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/*
* strace.h
*
* Created on: May 11, 2009
* Author: mahi
*/
#ifndef STRACE_H_
#define STRACE_H_
#ifdef USE_STRACE
#define STRACE(_x) strace((_x))
#else
#define STRACE(_x)
#endif
#endif /* STRACE_H_ */
|
2301_81045437/classic-platform
|
include/strace.h
|
C
|
unknown
| 1,004
|
/*
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)queue.h 8.5 (Berkeley) 8/20/94
* $FreeBSD: src/sys/sys/queue.h,v 1.48 2002/04/17 14:00:37 tmm Exp $
*/
#ifndef _SYS_QUEUE_H_
#define _SYS_QUEUE_H_
#include <stddef.h> /* for __offsetof */
/*
* This file defines four types of data structures: singly-linked lists,
* singly-linked tail queues, lists and tail queues.
*
* A singly-linked list is headed by a single forward pointer. The elements
* are singly linked for minimum space and pointer manipulation overhead at
* the expense of O(n) removal for arbitrary elements. New elements can be
* added to the list after an existing element or at the head of the list.
* Elements being removed from the head of the list should use the explicit
* macro for this purpose for optimum efficiency. A singly-linked list may
* only be traversed in the forward direction. Singly-linked lists are ideal
* for applications with large datasets and few or no removals or for
* implementing a LIFO queue.
*
* A singly-linked tail queue is headed by a pair of pointers, one to the
* head of the list and the other to the tail of the list. The elements are
* singly linked for minimum space and pointer manipulation overhead at the
* expense of O(n) removal for arbitrary elements. New elements can be added
* to the list after an existing element, at the head of the list, or at the
* end of the list. Elements being removed from the head of the tail queue
* should use the explicit macro for this purpose for optimum efficiency.
* A singly-linked tail queue may only be traversed in the forward direction.
* Singly-linked tail queues are ideal for applications with large datasets
* and few or no removals or for implementing a FIFO queue.
*
* A list is headed by a single forward pointer (or an array of forward
* pointers for a hash table header). The elements are doubly linked
* so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before
* or after an existing element or at the head of the list. A list
* may only be traversed in the forward direction.
*
* A tail queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or
* after an existing element, at the head of the list, or at the end of
* the list. A tail queue may be traversed in either direction.
*
* For details on the use of these macros, see the queue(3) manual page.
*
*
* SLIST LIST STAILQ TAILQ
* _HEAD + + + +
* _HEAD_INITIALIZER + + + +
* _ENTRY + + + +
* _INIT + + + +
* _EMPTY + + + +
* _FIRST + + + +
* _NEXT + + + +
* _PREV - - - +
* _LAST - - + +
* _FOREACH + + + +
* _FOREACH_REVERSE - - - +
* _INSERT_HEAD + + + +
* _INSERT_BEFORE - + - +
* _INSERT_AFTER + + + +
* _INSERT_TAIL - - + +
* _CONCAT - - + +
* _REMOVE_HEAD + - + -
* _REMOVE + + + +
*
*/
/*
* Singly-linked List declarations.
*/
#define SLIST_HEAD(name, type) \
struct name { \
struct type *slh_first; /* first element */ \
}
#define SLIST_HEAD_INITIALIZER(head) \
{ NULL }
#define SLIST_ENTRY(type) \
struct { \
struct type *sle_next; /* next element */ \
}
/*
* Singly-linked List functions.
*/
#define SLIST_EMPTY(head) ((head)->slh_first == NULL)
#define SLIST_FIRST(head) ((head)->slh_first)
#define SLIST_FOREACH(var, head, field) \
for ((var) = SLIST_FIRST((head)); \
(var); \
(var) = SLIST_NEXT((var), field))
#define SLIST_INIT(head) do { \
SLIST_FIRST((head)) = NULL; \
} while (0)
#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \
SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \
SLIST_NEXT((slistelm), field) = (elm); \
} while (0)
#define SLIST_INSERT_HEAD(head, elm, field) do { \
SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \
SLIST_FIRST((head)) = (elm); \
} while (0)
#define SLIST_NEXT(elm, field) ((elm)->field.sle_next)
#define SLIST_REMOVE(head, elm, type, field) do { \
if (SLIST_FIRST((head)) == (elm)) { \
SLIST_REMOVE_HEAD((head), field); \
} \
else { \
struct type *curelm = SLIST_FIRST((head)); \
while (SLIST_NEXT(curelm, field) != (elm)) \
curelm = SLIST_NEXT(curelm, field); \
SLIST_NEXT(curelm, field) = \
SLIST_NEXT(SLIST_NEXT(curelm, field), field); \
} \
} while (0)
#define SLIST_REMOVE_HEAD(head, field) do { \
SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \
} while (0)
/*
* Singly-linked Tail queue declarations.
*/
#define STAILQ_HEAD(name, type) \
struct name { \
struct type *stqh_first;/* first element */ \
struct type **stqh_last;/* addr of last next element */ \
}
#define STAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).stqh_first }
#define STAILQ_ENTRY(type) \
struct { \
struct type *stqe_next; /* next element */ \
}
/*
* Singly-linked Tail queue functions.
*/
#define STAILQ_CONCAT(head1, head2) do { \
if (!STAILQ_EMPTY((head2))) { \
*(head1)->stqh_last = (head2)->stqh_first; \
(head1)->stqh_last = (head2)->stqh_last; \
STAILQ_INIT((head2)); \
} \
} while (0)
#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL)
#define STAILQ_FIRST(head) ((head)->stqh_first)
#define STAILQ_FOREACH(var, head, field) \
for((var) = STAILQ_FIRST((head)); \
(var); \
(var) = STAILQ_NEXT((var), field))
#define STAILQ_INIT(head) do { \
STAILQ_FIRST((head)) = NULL; \
(head)->stqh_last = &STAILQ_FIRST((head)); \
} while (0)
#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \
if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
STAILQ_NEXT((tqelm), field) = (elm); \
} while (0)
#define STAILQ_INSERT_HEAD(head, elm, field) do { \
if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
STAILQ_FIRST((head)) = (elm); \
} while (0)
#define STAILQ_INSERT_TAIL(head, elm, field) do { \
STAILQ_NEXT((elm), field) = NULL; \
*(head)->stqh_last = (elm); \
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
} while (0)
#define STAILQ_LAST(head, type, field) \
(STAILQ_EMPTY((head)) ? \
NULL : \
((struct type *) \
((char *)((head)->stqh_last) - __offsetof(struct type, field))))
#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
#define STAILQ_REMOVE(head, elm, type, field) do { \
if (STAILQ_FIRST((head)) == (elm)) { \
STAILQ_REMOVE_HEAD((head), field); \
} \
else { \
struct type *curelm = STAILQ_FIRST((head)); \
while (STAILQ_NEXT(curelm, field) != (elm)) \
curelm = STAILQ_NEXT(curelm, field); \
if ((STAILQ_NEXT(curelm, field) = \
STAILQ_NEXT(STAILQ_NEXT(curelm, field), field)) == NULL)\
(head)->stqh_last = &STAILQ_NEXT((curelm), field);\
} \
} while (0)
#define STAILQ_REMOVE_HEAD(head, field) do { \
if ((STAILQ_FIRST((head)) = \
STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \
(head)->stqh_last = &STAILQ_FIRST((head)); \
} while (0)
#define STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \
if ((STAILQ_FIRST((head)) = STAILQ_NEXT((elm), field)) == NULL) \
(head)->stqh_last = &STAILQ_FIRST((head)); \
} while (0)
/*
* List declarations.
*/
#define LIST_HEAD(name, type) \
struct name { \
struct type *lh_first; /* first element */ \
}
#define LIST_HEAD_INITIALIZER(head) \
{ NULL }
#define LIST_ENTRY(type) \
struct { \
struct type *le_next; /* next element */ \
struct type **le_prev; /* address of previous next element */ \
}
/*
* List functions.
*/
#define LIST_EMPTY(head) ((head)->lh_first == NULL)
#define LIST_FIRST(head) ((head)->lh_first)
#define LIST_FOREACH(var, head, field) \
for ((var) = LIST_FIRST((head)); \
(var); \
(var) = LIST_NEXT((var), field))
#define LIST_INIT(head) do { \
LIST_FIRST((head)) = NULL; \
} while (0)
#define LIST_INSERT_AFTER(listelm, elm, field) do { \
if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
LIST_NEXT((listelm), field)->field.le_prev = \
&LIST_NEXT((elm), field); \
LIST_NEXT((listelm), field) = (elm); \
(elm)->field.le_prev = &LIST_NEXT((listelm), field); \
} while (0)
#define LIST_INSERT_BEFORE(listelm, elm, field) do { \
(elm)->field.le_prev = (listelm)->field.le_prev; \
LIST_NEXT((elm), field) = (listelm); \
*(listelm)->field.le_prev = (elm); \
(listelm)->field.le_prev = &LIST_NEXT((elm), field); \
} while (0)
#define LIST_INSERT_HEAD(head, elm, field) do { \
if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \
LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
LIST_FIRST((head)) = (elm); \
(elm)->field.le_prev = &LIST_FIRST((head)); \
} while (0)
#define LIST_NEXT(elm, field) ((elm)->field.le_next)
#define LIST_REMOVE(elm, field) do { \
if (LIST_NEXT((elm), field) != NULL) \
LIST_NEXT((elm), field)->field.le_prev = \
(elm)->field.le_prev; \
*(elm)->field.le_prev = LIST_NEXT((elm), field); \
} while (0)
/*
* Tail queue declarations.
*/
#define TAILQ_HEAD(name, type) \
struct name { \
struct type *tqh_first; /* first element */ \
struct type **tqh_last; /* addr of last next element */ \
}
#define TAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).tqh_first }
#define TAILQ_ENTRY(type) \
struct { \
struct type *tqe_next; /* next element */ \
struct type **tqe_prev; /* address of previous next element */ \
}
/*
* Tail queue functions.
*/
#define TAILQ_CONCAT(head1, head2, field) do { \
if (!TAILQ_EMPTY(head2)) { \
*(head1)->tqh_last = (head2)->tqh_first; \
(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \
(head1)->tqh_last = (head2)->tqh_last; \
TAILQ_INIT((head2)); \
} \
} while (0)
#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
#define TAILQ_FIRST(head) ((head)->tqh_first)
#define TAILQ_FOREACH(var, head, field) \
for ((var) = TAILQ_FIRST((head)); \
(var); \
(var) = TAILQ_NEXT((var), field))
#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
for ((var) = TAILQ_LAST((head), headname); \
(var); \
(var) = TAILQ_PREV((var), headname, field))
#define TAILQ_INIT(head) do { \
TAILQ_FIRST((head)) = NULL; \
(head)->tqh_last = &TAILQ_FIRST((head)); \
} while (0)
#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
TAILQ_NEXT((elm), field)->field.tqe_prev = \
&TAILQ_NEXT((elm), field); \
else \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
TAILQ_NEXT((listelm), field) = (elm); \
(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \
} while (0)
#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
(elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
TAILQ_NEXT((elm), field) = (listelm); \
*(listelm)->field.tqe_prev = (elm); \
(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \
} while (0)
#define TAILQ_INSERT_HEAD(head, elm, field) do { \
if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \
TAILQ_FIRST((head))->field.tqe_prev = \
&TAILQ_NEXT((elm), field); \
else \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
TAILQ_FIRST((head)) = (elm); \
(elm)->field.tqe_prev = &TAILQ_FIRST((head)); \
} while (0)
#define TAILQ_INSERT_TAIL(head, elm, field) do { \
TAILQ_NEXT((elm), field) = NULL; \
(elm)->field.tqe_prev = (head)->tqh_last; \
*(head)->tqh_last = (elm); \
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
} while (0)
#define TAILQ_LAST(head, headname) \
(*(((struct headname *)((head)->tqh_last))->tqh_last))
#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
#define TAILQ_PREV(elm, headname, field) \
(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
#define TAILQ_REMOVE(head, elm, field) do { \
if ((TAILQ_NEXT((elm), field)) != NULL) \
TAILQ_NEXT((elm), field)->field.tqe_prev = \
(elm)->field.tqe_prev; \
else \
(head)->tqh_last = (elm)->field.tqe_prev; \
*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \
} while (0)
#endif /* !_SYS_QUEUE_H_ */
|
2301_81045437/classic-platform
|
include/sys/queue.h
|
C
|
unknown
| 15,397
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef TIMER_H_
#define TIMER_H_
#include <stdint.h>
extern uint32_t Timer_Freq;
#define TIMER_TICK2US( _x ) ((_x) / (Timer_Freq/1000000uL))
#define TIMER_TICK2NS( _x ) (((_x)*1000) / (Timer_Freq/1000000uL))
#define TIMER_US2TICK( _x ) ((uint32_t)(((uint64_t)Timer_Freq * (_x) )/1000000uLL))
typedef uint32_t TimerTick;
typedef uint64_t TimerTick64;
void Timer_Init( void );
void Timer_InitIdx( uint8_t timerIdx );
/**
* Get a 32-bit timer
*/
TimerTick Timer_GetTicks( void );
TimerTick Timer_GetTicksIdx( uint8_t timerIdx );
/**
* Get a 64-bit timer
*/
uint64_t Timer_GetTicks64( void );
uint64_t Timer_GetTicks64Idx( uint8_t timerIdx );
/**
* Busy wait for useconds micro seconds.
*
* @param useconds
*/
static inline void Timer_uDelay(uint32_t uSeconds ) {
TimerTick startTick = Timer_GetTicks();
TimerTick waitTicks;
/* Calc the time to wait */
waitTicks = (uint32_t)(((uint64_t)Timer_Freq * uSeconds)/1000000uLL);
/* busy wait */
while( (Timer_GetTicks() - startTick) < waitTicks ) {
;
}
}
static inline void Timer_uDelay64(uint32_t uSeconds ) {
TimerTick64 startTick = Timer_GetTicks64();
TimerTick64 waitTicks;
/* Calc the time to wait */
waitTicks = ((uint64_t)Timer_Freq * (uint64_t)uSeconds)/1000000uLL;
/* busy wait */
while( (Timer_GetTicks64() - startTick) < waitTicks ) {
;
}
}
#endif /* TIMER_H_ */
|
2301_81045437/classic-platform
|
include/timer.h
|
C
|
unknown
| 2,257
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef CPU_H
#define CPU_H
#include "Std_Types.h"
#include "machine/intrinsics.h"
typedef uint32 imask_t;
#define INTERRUPT_ENABLE_BIT 0x8000
#define CPU0_OPERATION_MODE_USER0 0U
#define CPU0_OPERATION_MODE_USER1 1U
#define CPU0_OPERATION_MODE_SUPERVISOR 2U
#define TRAP_0_MMU 0
#define TRAP_1_INTERNAL_PROTECTION 1
#define TRAP_1_INTERNAL_PROTECTION_PRIV 1
#define TRAP_1_INTERNAL_PROTECTION_MPR 2
#define TRAP_1_INTERNAL_PROTECTION_MPW 3
#define TRAP_1_INTERNAL_PROTECTION_MPX 4
#define TRAP_1_INTERNAL_PROTECTION_MPP 5
#define TRAP_1_INTERNAL_PROTECTION_MPN 6
#define TRAP_1_INTERNAL_PROTECTION_GRWP 7
#define TRAP_2_INST_ERROR 2
#define TRAP_3_CONTEXT_MGNT 3
#define TRAP_4_SYSBUS_PERIPHERAL 4
#define TRAP_5_ASSERTION 5
#define TRAP_6_SYSCALL 6
#define TRAP_7_NMI 7
#define REGISTER_SET_SUPERVISOR 0
#define REGISTER_SET_USER 1
#define CSA_TO_ADDRESS(_csa) ( (((_csa) & 0x000f0000UL) << 12U) | (((_csa) & 0xffffL) << 6U ) )
#define ADDRESS_TO_CSA(_addr) ( (((( _addr ))&0xf0000000UL ) >> 12U) | ((( _addr ) & 0x003FFFC0UL ) >> 6U ) )
#define STR__(x) #x
#define STRINGIFY__(x) STR__(x)
#define Irq_Save(flags) flags = _Irq_Disable_save()
#define Irq_Restore(flags) _Irq_Disable_restore(flags)
#define Irq_Disable() _disable();
#define Irq_Enable() _enable();
#define Irq_SuspendAll() Irq_Disable()
#define Irq_ResumeAll() Irq_Enable()
#define Irq_SuspendOs() Irq_Disable()
#define Irq_ResumeOs() Irq_Enable()
#define ICR_IE_INT_ENABLE_BIT (1U<<15U)
#define set_reg(reg_nr, val) /*lint -save -e547 +dset_spr(a,b)=((void)b) -e586 -restore */ \
__asm__ volatile (" mov " STRINGIFY__(reg_nr) ",%[_val]" : : [_val] "r" (val))
/**
* Integer log2
*
* Examples:
* - ilog2(0x0) = -1
* - ilog2(0x1) = 0
* - ilog2(0x2) = 1
* - ilog2(0x8000_0000)=31
*
* @param val
* @return
*/
static inline uint8 ilog2( uint32 val ) {
return 0;
}
static inline unsigned long _Irq_Disable_save(void)
{
unsigned long result = _mfcr(0xFE2C); /* CPU_ICR */
Irq_Disable();
return result;
}
static inline void _Irq_Disable_restore(unsigned long flags) {
if( flags & INTERRUPT_ENABLE_BIT ) {
Irq_Enable();
} else {
Irq_Disable();
}
}
// lower context structure
typedef struct {
uint32 pcxi;
uint32 a11_ra;
uint32 a2;
uint32 a3;
uint32 d0;
uint32 d1;
uint32 d2;
uint32 d3;
uint32 a4;
uint32 a5;
uint32 a6;
uint32 a7;
uint32 d4;
uint32 d5;
uint32 d6;
uint32 d7;
} Os_ContextLowType;
// upper context structure
typedef struct {
uint32 pcxi;
uint32 psw;
uint32 a10_sp;
uint32 a11_ra;
uint32 d8;
uint32 d9;
uint32 d10;
uint32 d11;
uint32 a12;
uint32 a13;
uint32 a14;
uint32 a15;
uint32 d12;
uint32 d13;
uint32 d14;
uint32 d15;
} Os_ContextHighType;
#endif /* CPU_H */
|
2301_81045437/classic-platform
|
include/tricore/Cpu.h
|
C
|
unknown
| 3,750
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef TC2XX_H_
#define TC2XX_H_
/* Trap flags */
#define TRP_NOT_HANDLED 1UL
#define TRP_HANDLED 2UL
#define TRP_ADJUST_ADDR 4UL
// Trap handler function
uint32 TC2xx_HandleTrap(uint32 tin , uint32 trapClass, uint32 instrAddr );
#endif /* TC2XX_H_ */
|
2301_81045437/classic-platform
|
include/tricore/tc2xx.h
|
C
|
unknown
| 1,029
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef VERSION_H_
#define VERSION_H_
#define _ARCTIC_CORE_MAJOR_ 22
#define _ARCTIC_CORE_MINOR_ 0
#define _ARCTIC_CORE_PATCHLEVEL_ 0
#define _ARCTIC_CORE_BUILDTYPE_ REL
#define STR__(x) #x
#define STRSTR__(x) STR__(x)
/* Test for 1.2.3 ARCTIC_CORE_VERSION > 10203 */
#define ARCTIC_CORE_VERSION (_ARCTIC_CORE_MAJOR_ * 10000 + _ARCTIC_CORE_MINOR_ * 100 + _ARCTIC_CORE_PATCHLEVEL_)
#define ARCTIC_CORE_VERSION_STR STRSTR__(_ARCTIC_CORE_MAJOR_) "." STRSTR__(_ARCTIC_CORE_MINOR_) "." STRSTR__(_ARCTIC_CORE_PATCHLEVEL_) "." STRSTR__(_ARCTIC_CORE_BUILDTYPE_)
typedef struct Version {
const char *string;
const char *info;
const char *buildDate;
const char *optFlags;
} VersionType;
extern const VersionType ArcticCore_Version;
#endif /* VERSION_H_ */
|
2301_81045437/classic-platform
|
include/version.h
|
C
|
unknown
| 1,574
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef XTOA_H_
#define XTOA_H_
void xtoa(unsigned long val, char* str, int base,int negative);
// unsigned long to string
void ultoa(unsigned long value, char* str, int base);
// int to string
char * itoa(int value, char* str, int base);
#endif /* XTOA_H_ */
|
2301_81045437/classic-platform
|
include/xtoa.h
|
C
|
unknown
| 1,031
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#if defined(__GNUC__) || defined(__DCC__) || defined(__ghs__) || defined(__ARMCC_VERSION) || defined(__IAR_SYSTEMS_ICC__)
#if defined(__APPLE__)
#define SECTION_RAMLOG __attribute__ ((section ("0,.ramlog")))
#define SECTION_POSTBUILD_DATA
#define SECTION_POSTBUILD_HEADER
#else
#define SECTION_RAMLOG __attribute__ ((section (".ramlog")))
#define SECTION_RAM_NO_CACHE_BSS __attribute__ ((section (".ram_no_cache_bss")))
#define SECTION_RAM_NO_CACHE_DATA __attribute__ ((section (".ram_no_cache_data")))
#define SECTION_RAM_NO_INIT __attribute__ ((section (".ram_no_init")))
#if defined(CFG_POSTBUILD)
#define SECTION_POSTBUILD_DATA __attribute__ ((section (".postbuild_data")))
#define SECTION_POSTBUILD_HEADER __attribute__ ((section (".postbuild_header")))
#else
#define SECTION_POSTBUILD_DATA
#define SECTION_POSTBUILD_HEADER
#endif
#endif
#elif defined(__CWCC__)
/* The compiler manual states:
* The section name specified in the
* __declspec(section <section_name>) statement must be the
* name of an initialized data section. It is an error to use the uninitialized
* data section name.
*
* NOTE!! The initialized data section name is __declspec() does not mean that
* it will end up in that section, if its BSS data it will end-up in
* ramlog_bss instead.
*
* NOTE!! Naming the initialized and uninitialized data section to the same
* name will generate strange linker warnings (sometimes)
*/
#pragma section RW ".ramlog_data" ".ramlog_bss"
#define SECTION_RAMLOG __declspec(section ".ramlog_data")
#pragma section RW ".ram_no_cache_data" ".ram_no_cache_bss"
#define SECTION_RAM_NO_CACHE_BSS __declspec(section ".ram_no_cache_bss")
#define SECTION_RAM_NO_CACHE_DATA __declspec(section ".ram_no_cache_data")
#pragma section RW ".ram_no_init_data" ".ram_no_init_bss"
#define SECTION_RAM_NO_INIT __declspec(section ".ram_no_init_data")
#if defined(CFG_POSTBUILD)
#pragma section RW ".postbuild_data" ".postbuild_bss"
#define SECTION_POSTBUILD_DATA __declspec(section ".postbuild_data")
#pragma section RW ".postbuild_header" ".postbuild_header_bss"
#define SECTION_POSTBUILD_HEADER __declspec(section ".postbuild_header")
#else
#define SECTION_POSTBUILD_DATA
#define SECTION_POSTBUILD_HEADER
#endif
#else
#error Compiler not set
#endif
#if defined(MCU_LP_START_SEC_CLEARED_8)
#if defined(__GNUC__) || defined(__ghs__) || defined(__DCC__) || defined(__IAR_SYSTEMS_ICC__)
__attribute__ ((section (".lowpower_bss"))) __attribute__ ((aligned (8)))
#elif defined(__CWCC__)
#pragma section RW ".lowpower_data" ".lowpower_bss"
__attribute__ ((section (".lowpower_data"))) __attribute__ ((aligned (8)))
#else
#error Compiler not supported
#endif
#undef MCU_LP_START_SEC_CLEARED_8
#endif
#if defined(MCU_LP_STOP_SEC_CLEARED_8)
#undef MCU_LP_START_SEC_CLEARED_8
#endif
#if defined(ETH_DESC_START_SEC_CLEARED_4)
#if defined(__GNUC__) || defined(__ARMCC_VERSION) || defined(__DCC__) || defined(__IAR_SYSTEMS_ICC__)
__attribute__ ((section(".eth_desc")))
#else
#error Compiler not supported
#endif
#undef ETH_DESC_START_SEC_CLEARED_4
#endif
#if defined(ETH_DESC_STOP_SEC_CLEARED_4)
#undef ETH_DESC_START_SEC_CLEARED_4
#endif
#if defined(ETH_BUF_START_SEC_CLEARED_4)
#if defined(__GNUC__) || defined(__ARMCC_VERSION) || defined(__ghs__) || defined(__IAR_SYSTEMS_ICC__)
__attribute__ ((section(".eth_ahb_buf")))
#elif defined(__DCC__)
__attribute__ ((section(".eth_ahb_buf"))) __attribute__ ((aligned (4)))
#else
#error Compiler not supported
#endif
#undef ETH_BUF_START_SEC_CLEARED_4
#endif
#if defined(ETH_BUF_STOP_SEC_CLEARED_4)
#undef ETH_BUF_START_SEC_CLEARED_4
#endif
|
2301_81045437/classic-platform
|
integration/Arc_MemMap.h
|
C
|
unknown
| 4,574
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/*lint -e451 No include guard is needed for MemMap.h*/
/* REFERENCE
* MemoryMapping.pdf
*
* DESCRIPTION
* This file is used to map memory areas to specific sections, for example
* a calibration variable to a specific place in ROM.
*/
#include "Arc_MemMap.h"
/* SeqTest */
#define SeqTest_SEC_VAR_CLEARED_UNSPECIFIED
#define SeqTest_SEC_VAR_INIT_UNSPECIFIED
|
2301_81045437/classic-platform
|
integration/MemMap.h
|
C
|
unknown
| 1,144
|
# build with:
# $ make BOARDDIR=<board> BDIR=<dir>[,<dir>] CROSS_COMPILE=<gcc> all|clean|clean_all
#
# TARGETS
# all: Target when building
# clean: Remove generatated files for a board
# clean_all: Remove all generated files
# help: Print some help
#
# VARIABLES:
# BOARDDIR=<board dir>
# Select what board to build for
# BDIR=<dir>[,<dir>]
# Select what directories to build. The kernel is always built.
# CROSS_COMPILEf
# Specify the compiler to use.
# Q=[(@)/empty]
# If Q=@ cmd's will not be echoed.
#
# EXAMPLES
# Clean all
# $ make clean_all
#
# Clean for a specific board
# $ make BDIR=mpc551xsim clean
#
# Build the simple example (assuming CROSS_COMPILE set)
# $ make BOARDDIR= mpc551xsim BDIR=examples/simple all
#
# make BOARDDIR=bar
# make BOARDDIR=foo/bar
# -> board_name=BOARDDIR
# -> board_path=foo
# Some useful variables..
comma:= ,
empty:=
space:= $(empty) $(empty)
split = $(subst $(comma), ,$(1))
# C:/apa -> /c/apa
# ../tjo -> ../tjo
to_msyspath = $(shell echo "$(1)" | sed -e 's,\\,\/,g;s,\([a-zA-Z]\):,/\1,')
# Get core version
core_version:=$(shell gawk -v type=_ -f $(CURDIR)/scripts/get_version.awk $(CURDIR)/include/version.h)
export core_version
# Convert Path if on windows.
ifeq ($(OS),Windows_NT)
BDIR:=$(call to_msyspath,$(BDIR))
BOARDDIR:=$(call to_msyspath,$(BOARDDIR))
endif
USE_T32_SIM?=n
export USE_T32_SIM
# Tools
# Ugly thing to make things work under cmd.exe
# PATH := usr/bin/:$(PATH)
FIND := $(shell which find)
export UNAME:=$(shell uname)
ifneq ($(findstring Darwin,$(UNAME)),)
SHELL:=/bin/bash
export SED=/opt/local/bin/gsed
else
export SED=sed
endif
ifeq ($(VERBOSE),y)
export Q?=
else
export Q?=@
endif
# Default distribution directory
export DISTRONAME ?= distro
export TOPDIR = $(CURDIR)
export PATH
# Select default console
# RAMLOG | TTY_T32 | TTY_WINIDEA
export SELECT_OS_CONSOLE
ifdef SELECT_CONSOLE
export SELECT_CONSOLE
endif
ifdef SELECT_OPT
export SELECT_OPT
endif
ifneq ($(filter clean_all,$(MAKECMDGOALS)),clean_all)
ifeq ($(BOARDDIR),)
$(error BOARDDIR is empty)
endif
ifeq ($(BDIR),)
$(error BDIR is empty)
endif
endif
dir_cmd_goals := $(call split,$(BDIR))
# filter out make targets used in this file only
cmd_cmd_goals := $(filter-out clean_all help libs test show_build,$(MAKECMDGOALS))
# filter out nonstd make targets
user_cmd_cmd_goals := $(filter-out all config clean distro clean_distro, $(cmd_cmd_goals))
# Check for CROSS_COMPILE
ifneq ($(cmd_cmd_goals),)
ifeq ($(findstring /,$(BOARDDIR)),)
# Check that the board actually exist
ifdef BOARDDIR
all_boards := $(subst /,,$(subst boards/,,$(shell $(FIND) boards/ -maxdepth 1 -type d)))
all_boards_print := $(subst $(space),$(comma)$(space),$(strip $(all_boards)))
ifeq ($(filter $(BOARDDIR),$(all_boards)),)
$(error no such board: $(BOARDDIR), valid boards are: $(all_boards_print))
endif
endif
export board_name:=$(BOARDDIR)
export board_path=$(CURDIR)/boards/$(board_name)
else
# it's a path, split into board_name and board_path (contains board_name)
tmp :=$(subst /,$(space),$(BOARDDIR))
board_name:=$(strip $(word $(words $(tmp)),$(tmp)))
board_path:=$(BOARDDIR)
export board_name
export board_path
endif
# Check BDIR
endif
export objdir = obj_$(board_name)
export CFG_MCU
export CFG_CPU
export MCU
export def-y+=$(CFG_ARCH_$(ARCH)) $(CFG_MCU) $(CFG_CPU)
export COMMON_BUILD_MAKEPATH?=$(CURDIR)/testCommon
# We descend into the object directories and build the. That way it's easier to build
# multi-arch support and we don't have to use objdir everywhere.
# ROOTDIR - The top-most directory
# SUBDIR - The current subdirectory it's building.
libs:
mkdir -p $@
.PHONY: all
all: libs $(dir_cmd_goals)
ifneq ($(user_cmd_cmd_goals),)
.PHONY: $(user_cmd_cmd_goals)
$(user_cmd_cmd_goals): libs $(dir_cmd_goals)
endif
.PHONY: clean
.PHONY: release
.PHONY: distro
distro: $(dir_cmd_goals)
.PHONY: clean_distro
clean_distro: $(dir_cmd_goals)
.PHONY: help
help:
@echo "Build a simple example"
@echo " > make BOARDDIR=mpc551xsim CROSS_COMPILE=/opt/powerpc-eabi/bin/powerpc-eabi- BDIR=examples/simple all"
@echo ""
@echo "Clean"
@echo " > make clean"
@echo ""
@echo "Present config:"
@echo " BDIR = ${BDIR}"
@echo " BOARDDIR = $(BOARDDIR)"
@echo " CROSS_COMPILE = $(CROSS_COMPILE)"
@echo " CURDIR = $(CURDIR)"
@echo ""
test:
@echo $(all_boards)
$(dir_cmd_goals) :: FORCE
@echo ""
@echo ==========[ ${abspath $@} ]===========
@if [ ! -d $@ ]; then echo "No such directory: \"$@\" quitting"; exit 1; fi
+@[ -d $@/$(objdir) ] || mkdir -p $@/$(objdir)
@chmod 777 $@/$(objdir)
$(Q)$(MAKE) -r -C $@/$(objdir) -f $(CURDIR)/scripts/rules.mk ROOTDIR=$(CURDIR) SUBDIR=$@ $(cmd_cmd_goals)
.PHONY: test
FORCE:
.PHONY: boards
boards:
@find . -type d -name *
clean_all:
$(Q)find . -type d -name obj_* | xargs rm -rf
$(Q)find . -type f -name *.a | xargs rm -rf
@echo
@echo " >>>>>>>>> DONE <<<<<<<<<"
@echo
config: $(dir_cmd_goals)
.PHONY clean:
clean: $(dir_cmd_goals)
@echo
@echo " >> Cleaning MAIN $(CURDIR)"
# $(Q)find . -type d -name $(objdir) | xargs rm -rf
# $(Q)find . -type f -name *.a | xargs rm -rf
# $(Q)rm -rf libs/*
@echo
@echo " >>>>>>>>> DONE <<<<<<<<<"
@echo
|
2301_81045437/classic-platform
|
makefile
|
Makefile
|
unknown
| 5,575
|
#Ea
obj-$(USE_EA)-$(CFG_GNULINUX) += Ea_gnulinux.o
obj-$(USE_EA)-$(if $(CFG_GNULINUX),n,y) += Ea.o
obj-$(USE_EA) += Ea_Lcfg.o
vpath-$(USE_EA) += $(ROOTDIR)/memory/Ea/src
inc-$(USE_EA) += $(ROOTDIR)/memory/Ea/inc
|
2301_81045437/classic-platform
|
memory/Ea/Ea.mod.mk
|
Makefile
|
unknown
| 220
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EA_H_
#define EA_H_
/* @req EA177 */
#define EA_SW_MAJOR_VERSION 1
#define EA_SW_MINOR_VERSION 0
#define EA_SW_PATCH_VERSION 0
#define EA_AR_MAJOR_VERSION 4
#define EA_AR_MINOR_VERSION 0
#define EA_AR_PATCH_VERSION 3
#define EA_AR_RELEASE_MAJOR_VERSION EA_AR_MAJOR_VERSION
#define EA_AR_RELEASE_MINOR_VERSION EA_AR_MINOR_VERSION
#define EA_AR_RELEASE_REVISION_VERSION EA_AR_PATCH_VERSION
#if defined(USE_EEP)
#include "Eep.h"
#endif
#include "Std_Types.h"
#include "Ea_Cfg.h"
#define EA_MODULE_ID 40u
#define EA_VENDOR_ID 60u
/*
* API parameter checking
*/
/* @req EA049 */
#define EA_E_UNINIT 0x01u
#define EA_E_INVALID_BLOCK_NO 0x02u
#define EA_E_INVALID_BLOCK_OFS 0x03u
#define EA_E_INVALID_DATA_PTR 0x04u
#define EA_E_INVALID_BLOCK_LEN 0x05u
#define EA_E_BUSY 0x06u
#define EA_E_BUSY_INTERNAL 0x07u
#define EA_E_INVALID_CANCEL 0x08u
/*
* EA Module Service ID Macro Collection
*/
#define EA_INIT_ID 0x00u
#define EA_SETMODE_ID 0x01u
#define EA_READ_ID 0x02u
#define EA_WRITE_ID 0x03u
#define EA_CANCEL_ID 0x04u
#define EA_GETSTATUS_ID 0x05u
#define EA_GETJOBRESULT_ID 0x06u
#define EA_INVALIDATEBLOCK_ID 0x07u
#define EA_GETVERSIONINFO_ID 0x08u
#define EA_ERASEIMMEDIATEBLOCK_ID 0x09u
#define EA_MAIN_ID 0x12u
/* @req EA061 */
/* @req EA062 */
/* @req EA082 */
/* !req EA164 */
#if ( EA_VERSION_INFO_API == STD_ON )
#define Ea_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi, EA) /** @req EA092 */
#endif /* EA_VERSION_INFO_API */
void Ea_MainFunction(void); /** @req EA096 */
void Ea_Init(void); /** @req EA084 */
#if (STD_ON == EA_SET_MODE_SUPPORTED)
void Ea_SetMode(MemIf_ModeType Mode); /** @req EA085 */
#endif
Std_ReturnType Ea_Read(uint16 BlockNumber, uint16 BlockOffset, uint8* DataBufferPtr, uint16 Length); /** @req EA086 */
Std_ReturnType Ea_Write(uint16 BlockNumber, uint8* DataBufferPtr); /** @req EA087 */
void Ea_Cancel(void); /** @req EA088 */
MemIf_StatusType Ea_GetStatus(void); /** @req EA089 */
MemIf_JobResultType Ea_GetJobResult(void); /** @req EA090 */
Std_ReturnType Ea_InvalidateBlock(uint16 BlockNumber); /** @req EA091 */
Std_ReturnType Ea_EraseImmediateBlock(uint16 BlockNumber); /** @req EA093 */
#endif /*EA_H_*/
|
2301_81045437/classic-platform
|
memory/Ea/inc/Ea.h
|
C
|
unknown
| 3,260
|