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kvesteri/postgresql-audit | postgresql_audit/migrations.py | remove_column | def remove_column(conn, table, column_name, schema=None):
"""
Removes given `activity` jsonb data column key. This function is useful
when you are doing schema changes that require removing a column.
Let's say you've been using PostgreSQL-Audit for a while for a table called
article. Now you want t... | python | def remove_column(conn, table, column_name, schema=None):
"""
Removes given `activity` jsonb data column key. This function is useful
when you are doing schema changes that require removing a column.
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kvesteri/postgresql-audit | postgresql_audit/migrations.py | rename_table | def rename_table(conn, old_table_name, new_table_name, schema=None):
"""
Renames given table in activity table. You should remember to call this
function whenever you rename a versioned table.
::
from alembic import op
from postgresql_audit import rename_table
def upgrade():
... | python | def rename_table(conn, old_table_name, new_table_name, schema=None):
"""
Renames given table in activity table. You should remember to call this
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::
from alembic import op
from postgresql_audit import rename_table
def upgrade():
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kvesteri/postgresql-audit | postgresql_audit/base.py | VersioningManager.instrument_versioned_classes | def instrument_versioned_classes(self, mapper, cls):
"""
Collect versioned class and add it to pending_classes list.
:mapper mapper: SQLAlchemy mapper object
:cls cls: SQLAlchemy declarative class
"""
if hasattr(cls, '__versioned__') and cls not in self.pending_classes:
... | python | def instrument_versioned_classes(self, mapper, cls):
"""
Collect versioned class and add it to pending_classes list.
:mapper mapper: SQLAlchemy mapper object
:cls cls: SQLAlchemy declarative class
"""
if hasattr(cls, '__versioned__') and cls not in self.pending_classes:
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kvesteri/postgresql-audit | postgresql_audit/base.py | VersioningManager.configure_versioned_classes | def configure_versioned_classes(self):
"""
Configures all versioned classes that were collected during
instrumentation process.
"""
for cls in self.pending_classes:
self.audit_table(cls.__table__, cls.__versioned__.get('exclude'))
assign_actor(self.base, self.... | python | def configure_versioned_classes(self):
"""
Configures all versioned classes that were collected during
instrumentation process.
"""
for cls in self.pending_classes:
self.audit_table(cls.__table__, cls.__versioned__.get('exclude'))
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mfcovington/pubmed-lookup | pubmed_lookup/command_line.py | pubmed_citation | def pubmed_citation(args=sys.argv[1:], out=sys.stdout):
"""Get a citation via the command line using a PubMed ID or PubMed URL"""
parser = argparse.ArgumentParser(
description='Get a citation using a PubMed ID or PubMed URL')
parser.add_argument('query', help='PubMed ID or PubMed URL')
parser.a... | python | def pubmed_citation(args=sys.argv[1:], out=sys.stdout):
"""Get a citation via the command line using a PubMed ID or PubMed URL"""
parser = argparse.ArgumentParser(
description='Get a citation using a PubMed ID or PubMed URL')
parser.add_argument('query', help='PubMed ID or PubMed URL')
parser.a... | [
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mfcovington/pubmed-lookup | pubmed_lookup/command_line.py | pubmed_url | def pubmed_url(args=sys.argv[1:], resolve_doi=True, out=sys.stdout):
"""
Get a publication URL via the command line using a PubMed ID or PubMed URL
"""
parser = argparse.ArgumentParser(
description='Get a publication URL using a PubMed ID or PubMed URL')
parser.add_argument('query', help='P... | python | def pubmed_url(args=sys.argv[1:], resolve_doi=True, out=sys.stdout):
"""
Get a publication URL via the command line using a PubMed ID or PubMed URL
"""
parser = argparse.ArgumentParser(
description='Get a publication URL using a PubMed ID or PubMed URL')
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mfcovington/pubmed-lookup | pubmed_lookup/pubmed_lookup.py | Publication.authors_et_al | def authors_et_al(self, max_authors=5):
"""
Return string with a truncated author list followed by 'et al.'
"""
author_list = self._author_list
if len(author_list) <= max_authors:
authors_et_al = self.authors
else:
authors_et_al = ", ".join(
... | python | def authors_et_al(self, max_authors=5):
"""
Return string with a truncated author list followed by 'et al.'
"""
author_list = self._author_list
if len(author_list) <= max_authors:
authors_et_al = self.authors
else:
authors_et_al = ", ".join(
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mfcovington/pubmed-lookup | pubmed_lookup/pubmed_lookup.py | Publication.cite | def cite(self, max_authors=5):
"""
Return string with a citation for the record, formatted as:
'{authors} ({year}). {title} {journal} {volume}({issue}): {pages}.'
"""
citation_data = {
'title': self.title,
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... | python | def cite(self, max_authors=5):
"""
Return string with a citation for the record, formatted as:
'{authors} ({year}). {title} {journal} {volume}({issue}): {pages}.'
"""
citation_data = {
'title': self.title,
'authors': self.authors_et_al(max_authors),
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mfcovington/pubmed-lookup | pubmed_lookup/pubmed_lookup.py | Publication.cite_mini | def cite_mini(self):
"""
Return string with a citation for the record, formatted as:
'{first_author} - {year} - {journal}'
"""
citation_data = [self.first_author]
if len(self._author_list) > 1:
citation_data.append(self.last_author)
citation_data.ext... | python | def cite_mini(self):
"""
Return string with a citation for the record, formatted as:
'{first_author} - {year} - {journal}'
"""
citation_data = [self.first_author]
if len(self._author_list) > 1:
citation_data.append(self.last_author)
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mfcovington/pubmed-lookup | pubmed_lookup/pubmed_lookup.py | Publication.parse_abstract | def parse_abstract(xml_dict):
"""
Parse PubMed XML dictionary to retrieve abstract.
"""
key_path = ['PubmedArticleSet', 'PubmedArticle', 'MedlineCitation',
'Article', 'Abstract', 'AbstractText']
abstract_xml = reduce(dict.get, key_path, xml_dict)
abst... | python | def parse_abstract(xml_dict):
"""
Parse PubMed XML dictionary to retrieve abstract.
"""
key_path = ['PubmedArticleSet', 'PubmedArticle', 'MedlineCitation',
'Article', 'Abstract', 'AbstractText']
abstract_xml = reduce(dict.get, key_path, xml_dict)
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mfcovington/pubmed-lookup | pubmed_lookup/pubmed_lookup.py | Publication.get_pubmed_xml | def get_pubmed_xml(self):
"""
Use a PubMed ID to retrieve PubMed metadata in XML form.
"""
url = 'http://eutils.ncbi.nlm.nih.gov/entrez/eutils/' \
'efetch.fcgi?db=pubmed&rettype=abstract&id={}' \
.format(self.pmid)
try:
response = urlopen(... | python | def get_pubmed_xml(self):
"""
Use a PubMed ID to retrieve PubMed metadata in XML form.
"""
url = 'http://eutils.ncbi.nlm.nih.gov/entrez/eutils/' \
'efetch.fcgi?db=pubmed&rettype=abstract&id={}' \
.format(self.pmid)
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response = urlopen(... | [
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mfcovington/pubmed-lookup | pubmed_lookup/pubmed_lookup.py | Publication.set_abstract | def set_abstract(self, xml_dict):
"""
If record has an abstract, extract it from PubMed's XML data
"""
if self.record.get('HasAbstract') == 1 and xml_dict:
self.abstract = self.parse_abstract(xml_dict)
else:
self.abstract = '' | python | def set_abstract(self, xml_dict):
"""
If record has an abstract, extract it from PubMed's XML data
"""
if self.record.get('HasAbstract') == 1 and xml_dict:
self.abstract = self.parse_abstract(xml_dict)
else:
self.abstract = '' | [
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mfcovington/pubmed-lookup | pubmed_lookup/pubmed_lookup.py | Publication.set_article_url | def set_article_url(self, resolve_doi=True):
"""
If record has a DOI, set article URL based on where the DOI points.
"""
if 'DOI' in self.record:
doi_url = "/".join(['http://dx.doi.org', self.record['DOI']])
if resolve_doi:
try:
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"""
If record has a DOI, set article URL based on where the DOI points.
"""
if 'DOI' in self.record:
doi_url = "/".join(['http://dx.doi.org', self.record['DOI']])
if resolve_doi:
try:
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mfcovington/pubmed-lookup | pubmed_lookup/pubmed_lookup.py | Publication.set_pub_year_month_day | def set_pub_year_month_day(self, xml_dict):
"""
Set publication year, month, day from PubMed's XML data
"""
key_path = ['PubmedArticleSet', 'PubmedArticle', 'MedlineCitation',
'Article', 'Journal', 'JournalIssue', 'PubDate']
pubdate_xml = reduce(dict.get, key_... | python | def set_pub_year_month_day(self, xml_dict):
"""
Set publication year, month, day from PubMed's XML data
"""
key_path = ['PubmedArticleSet', 'PubmedArticle', 'MedlineCitation',
'Article', 'Journal', 'JournalIssue', 'PubDate']
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mfcovington/pubmed-lookup | pubmed_lookup/pubmed_lookup.py | PubMedLookup.parse_pubmed_url | def parse_pubmed_url(pubmed_url):
"""Get PubMed ID (pmid) from PubMed URL."""
parse_result = urlparse(pubmed_url)
pattern = re.compile(r'^/pubmed/(\d+)$')
pmid = pattern.match(parse_result.path).group(1)
return pmid | python | def parse_pubmed_url(pubmed_url):
"""Get PubMed ID (pmid) from PubMed URL."""
parse_result = urlparse(pubmed_url)
pattern = re.compile(r'^/pubmed/(\d+)$')
pmid = pattern.match(parse_result.path).group(1)
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mfcovington/pubmed-lookup | pubmed_lookup/pubmed_lookup.py | PubMedLookup.get_pubmed_record | def get_pubmed_record(pmid):
"""Get PubMed record from PubMed ID."""
handle = Entrez.esummary(db="pubmed", id=pmid)
record = Entrez.read(handle)
return record | python | def get_pubmed_record(pmid):
"""Get PubMed record from PubMed ID."""
handle = Entrez.esummary(db="pubmed", id=pmid)
record = Entrez.read(handle)
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UCSBarchlab/PyRTL | pyrtl/simulation.py | Simulation._initialize | def _initialize(self, register_value_map=None, memory_value_map=None, default_value=None):
""" Sets the wire, register, and memory values to default or as specified.
:param register_value_map: is a map of {Register: value}.
:param memory_value_map: is a map of maps {Memory: {address: Value}}.
... | python | def _initialize(self, register_value_map=None, memory_value_map=None, default_value=None):
""" Sets the wire, register, and memory values to default or as specified.
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:param provided_inputs: a dictionary mapping wirevectors to their values for this step
All input wires must be in the provided_inputs in order for the simulation
to accept these values
Example: if we ha... | python | def step(self, provided_inputs):
""" Take the simulation forward one cycle
:param provided_inputs: a dictionary mapping wirevectors to their values for this step
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:param w: the name of the WireVector to inspect
(passing in a WireVector instead of a name is deprecated)
:return: value of w in the current step of simulation
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""" Get the value of a wirevector in the last simulation cycle.
:param w: the name of the WireVector to inspect
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UCSBarchlab/PyRTL | pyrtl/simulation.py | Simulation._execute | def _execute(self, net):
"""Handle the combinational logic update rules for the given net.
This function, along with edge_update, defined the semantics
of the primitive ops. Function updates self.value accordingly.
"""
if net.op in 'r@':
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"""Handle the combinational logic update rules for the given net.
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UCSBarchlab/PyRTL | pyrtl/simulation.py | FastSimulation.step | def step(self, provided_inputs):
""" Run the simulation for a cycle
:param provided_inputs: a dictionary mapping WireVectors (or their names)
to their values for this step
eg: {wire: 3, "wire_name": 17}
"""
# validate_inputs
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""" Run the simulation for a cycle
:param provided_inputs: a dictionary mapping WireVectors (or their names)
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UCSBarchlab/PyRTL | pyrtl/simulation.py | FastSimulation._arg_varname | def _arg_varname(self, wire):
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Input, Const, and Registers have special input values
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UCSBarchlab/PyRTL | pyrtl/simulation.py | _WaveRendererBase._render_val_with_prev | def _render_val_with_prev(self, w, n, current_val, symbol_len):
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UCSBarchlab/PyRTL | pyrtl/simulation.py | SimulationTrace.add_step | def add_step(self, value_map):
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""" Add the values in value_map to the end of the trace. """
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UCSBarchlab/PyRTL | pyrtl/simulation.py | SimulationTrace.add_fast_step | def add_fast_step(self, fastsim):
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UCSBarchlab/PyRTL | pyrtl/simulation.py | SimulationTrace.print_vcd | def print_vcd(self, file=sys.stdout, include_clock=False):
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UCSBarchlab/PyRTL | pyrtl/simulation.py | SimulationTrace.render_trace | def render_trace(
self, trace_list=None, file=sys.stdout, render_cls=default_renderer(),
symbol_len=5, segment_size=5, segment_delim=' ', extra_line=True):
""" Render the trace to a file using unicode and ASCII escape sequences.
:param trace_list: A list of signals to be output... | python | def render_trace(
self, trace_list=None, file=sys.stdout, render_cls=default_renderer(),
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UCSBarchlab/PyRTL | pyrtl/rtllib/muxes.py | prioritized_mux | def prioritized_mux(selects, vals):
"""
Returns the value in the first wire for which its select bit is 1
:param [WireVector] selects: a list of WireVectors signaling whether
a wire should be chosen
:param [WireVector] vals: values to return when the corresponding select
value is 1
... | python | def prioritized_mux(selects, vals):
"""
Returns the value in the first wire for which its select bit is 1
:param [WireVector] selects: a list of WireVectors signaling whether
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UCSBarchlab/PyRTL | pyrtl/rtllib/muxes.py | sparse_mux | def sparse_mux(sel, vals):
"""
Mux that avoids instantiating unnecessary mux_2s when possible.
:param WireVector sel: Select wire, determines what is selected on a given cycle
:param dictionary vals: dictionary of values at mux inputs (of type `{int:WireVector}`)
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"""
Mux that avoids instantiating unnecessary mux_2s when possible.
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UCSBarchlab/PyRTL | pyrtl/rtllib/muxes.py | _sparse_mux | def _sparse_mux(sel, vals):
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... | python | def _sparse_mux(sel, vals):
"""
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UCSBarchlab/PyRTL | pyrtl/rtllib/muxes.py | demux | def demux(select):
"""
Demultiplexes a wire of arbitrary bitwidth
:param WireVector select: indicates which wire to set on
:return (WireVector, ...): a tuple of wires corresponding to each demultiplexed wire
"""
if len(select) == 1:
return _demux_2(select)
wires = demux(select[:-1]... | python | def demux(select):
"""
Demultiplexes a wire of arbitrary bitwidth
:param WireVector select: indicates which wire to set on
:return (WireVector, ...): a tuple of wires corresponding to each demultiplexed wire
"""
if len(select) == 1:
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UCSBarchlab/PyRTL | pyrtl/rtllib/muxes.py | MultiSelector.finalize | def finalize(self):
"""
Connects the wires.
"""
self._check_finalized()
self._final = True
for dest_w, values in self.dest_instrs_info.items():
mux_vals = dict(zip(self.instructions, values))
dest_w <<= sparse_mux(self.signal_wire, mux_vals) | python | def finalize(self):
"""
Connects the wires.
"""
self._check_finalized()
self._final = True
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mux_vals = dict(zip(self.instructions, values))
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UCSBarchlab/PyRTL | pyrtl/wire.py | WireVector.bitmask | def bitmask(self):
""" A property holding a bitmask of the same length as this WireVector.
Specifically it is an integer with a number of bits set to 1 equal to the
bitwidth of the WireVector.
It is often times useful to "mask" an integer such that it fits in the
the number of b... | python | def bitmask(self):
""" A property holding a bitmask of the same length as this WireVector.
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usrlocalben/pydux | pydux/log_middleware.py | log_middleware | def log_middleware(store):
"""log all actions to console as they are dispatched"""
def wrapper(next_):
def log_dispatch(action):
print('Dispatch Action:', action)
return next_(action)
return log_dispatch
return wrapper | python | def log_middleware(store):
"""log all actions to console as they are dispatched"""
def wrapper(next_):
def log_dispatch(action):
print('Dispatch Action:', action)
return next_(action)
return log_dispatch
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UCSBarchlab/PyRTL | pyrtl/compilesim.py | CompiledSimulation.inspect | def inspect(self, w):
"""Get the latest value of the wire given, if possible."""
if isinstance(w, WireVector):
w = w.name
try:
vals = self.tracer.trace[w]
except KeyError:
pass
else:
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raise PyrtlError('No... | python | def inspect(self, w):
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if isinstance(w, WireVector):
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UCSBarchlab/PyRTL | pyrtl/compilesim.py | CompiledSimulation.run | def run(self, inputs):
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The argument is a list of input mappings for each step,
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"""
steps = len(inputs)
# create i/o arrays of the appropriate length
ibuf_type = ctypes.c_ui... | python | def run(self, inputs):
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The argument is a list of input mappings for each step,
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steps = len(inputs)
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UCSBarchlab/PyRTL | pyrtl/compilesim.py | CompiledSimulation._traceable | def _traceable(self, wv):
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"""
if isinstance(wv, (Input, Output)):
return True
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"""Check if wv is able to be traced
If it is traceable due to a probe, record that probe in _probe_mapping.
"""
if isinstance(wv, (Input, Output)):
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UCSBarchlab/PyRTL | pyrtl/compilesim.py | CompiledSimulation._remove_untraceable | def _remove_untraceable(self):
"""Remove from the tracer those wires that CompiledSimulation cannot track.
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"""
self._probe_mapping = {}
wvs = {wv for wv in self.tracer.wires_to_track if self._traceable(wv)}
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UCSBarchlab/PyRTL | pyrtl/compilesim.py | CompiledSimulation._create_dll | def _create_dll(self):
"""Create a dynamically-linked library implementing the simulation logic."""
self._dir = tempfile.mkdtemp()
with open(path.join(self._dir, 'pyrtlsim.c'), 'w') as f:
self._create_code(lambda s: f.write(s+'\n'))
if platform.system() == 'Darwin':
... | python | def _create_dll(self):
"""Create a dynamically-linked library implementing the simulation logic."""
self._dir = tempfile.mkdtemp()
with open(path.join(self._dir, 'pyrtlsim.c'), 'w') as f:
self._create_code(lambda s: f.write(s+'\n'))
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UCSBarchlab/PyRTL | pyrtl/compilesim.py | CompiledSimulation._makeini | def _makeini(self, w, v):
"""C initializer string for a wire with a given value."""
pieces = []
for n in range(self._limbs(w)):
pieces.append(hex(v & ((1 << 64)-1)))
v >>= 64
return ','.join(pieces).join('{}') | python | def _makeini(self, w, v):
"""C initializer string for a wire with a given value."""
pieces = []
for n in range(self._limbs(w)):
pieces.append(hex(v & ((1 << 64)-1)))
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UCSBarchlab/PyRTL | pyrtl/compilesim.py | CompiledSimulation._makemask | def _makemask(self, dest, res, pos):
"""Create a bitmask.
The value being masked is of width `res`.
Limb number `pos` of `dest` is being assigned to.
"""
if (res is None or dest.bitwidth < res) and 0 < (dest.bitwidth - 64*pos) < 64:
return '&0x{:X}'.format((1 << (des... | python | def _makemask(self, dest, res, pos):
"""Create a bitmask.
The value being masked is of width `res`.
Limb number `pos` of `dest` is being assigned to.
"""
if (res is None or dest.bitwidth < res) and 0 < (dest.bitwidth - 64*pos) < 64:
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UCSBarchlab/PyRTL | pyrtl/compilesim.py | CompiledSimulation._getarglimb | def _getarglimb(self, arg, n):
"""Get the nth limb of the given wire.
Returns '0' when the wire does not have sufficient limbs.
"""
return '{vn}[{n}]'.format(vn=self.varname[arg], n=n) if arg.bitwidth > 64*n else '0' | python | def _getarglimb(self, arg, n):
"""Get the nth limb of the given wire.
Returns '0' when the wire does not have sufficient limbs.
"""
return '{vn}[{n}]'.format(vn=self.varname[arg], n=n) if arg.bitwidth > 64*n else '0' | [
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UCSBarchlab/PyRTL | pyrtl/rtllib/multipliers.py | simple_mult | def simple_mult(A, B, start):
""" Builds a slow, small multiplier using the simple shift-and-add algorithm.
Requires very small area (it uses only a single adder), but has long delay
(worst case is len(A) cycles). start is a one-bit input to indicate inputs are ready.
done is a one-bit output signal rai... | python | def simple_mult(A, B, start):
""" Builds a slow, small multiplier using the simple shift-and-add algorithm.
Requires very small area (it uses only a single adder), but has long delay
(worst case is len(A) cycles). start is a one-bit input to indicate inputs are ready.
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UCSBarchlab/PyRTL | pyrtl/rtllib/multipliers.py | _trivial_mult | def _trivial_mult(A, B):
"""
turns a multiplication into an And gate if one of the
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:param A:
:param B:
:return:
"""
if len(B) == 1:
A, B = B, A # so that we can reuse the code below :)
if len(A) == 1:
a_vals = A.sign_extended(len(B))
... | python | def _trivial_mult(A, B):
"""
turns a multiplication into an And gate if one of the
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:param A:
:param B:
:return:
"""
if len(B) == 1:
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if len(A) == 1:
a_vals = A.sign_extended(len(B))
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UCSBarchlab/PyRTL | pyrtl/rtllib/multipliers.py | complex_mult | def complex_mult(A, B, shifts, start):
""" Generate shift-and-add multiplier that can shift and add multiple bits per clock cycle.
Uses substantially more space than `simple_mult()` but is much faster.
:param WireVector A, B: two input wires for the multiplication
:param int shifts: number of spaces Re... | python | def complex_mult(A, B, shifts, start):
""" Generate shift-and-add multiplier that can shift and add multiple bits per clock cycle.
Uses substantially more space than `simple_mult()` but is much faster.
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UCSBarchlab/PyRTL | pyrtl/rtllib/multipliers.py | _one_cycle_mult | def _one_cycle_mult(areg, breg, rem_bits, sum_sf=0, curr_bit=0):
""" returns a WireVector sum of rem_bits multiplies (in one clock cycle)
note: this method requires a lot of area because of the indexing in the else statement """
if rem_bits == 0:
return sum_sf
else:
a_curr_val = areg[cur... | python | def _one_cycle_mult(areg, breg, rem_bits, sum_sf=0, curr_bit=0):
""" returns a WireVector sum of rem_bits multiplies (in one clock cycle)
note: this method requires a lot of area because of the indexing in the else statement """
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UCSBarchlab/PyRTL | pyrtl/rtllib/multipliers.py | tree_multiplier | def tree_multiplier(A, B, reducer=adders.wallace_reducer, adder_func=adders.kogge_stone):
""" Build an fast unclocked multiplier for inputs A and B using a Wallace or Dada Tree.
:param WireVector A, B: two input wires for the multiplication
:param function reducer: Reduce the tree using either a Dada recud... | python | def tree_multiplier(A, B, reducer=adders.wallace_reducer, adder_func=adders.kogge_stone):
""" Build an fast unclocked multiplier for inputs A and B using a Wallace or Dada Tree.
:param WireVector A, B: two input wires for the multiplication
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UCSBarchlab/PyRTL | pyrtl/rtllib/multipliers.py | signed_tree_multiplier | def signed_tree_multiplier(A, B, reducer=adders.wallace_reducer, adder_func=adders.kogge_stone):
"""Same as tree_multiplier, but uses two's-complement signed integers"""
if len(A) == 1 or len(B) == 1:
raise pyrtl.PyrtlError("sign bit required, one or both wires too small")
aneg, bneg = A[-1], B[-1]... | python | def signed_tree_multiplier(A, B, reducer=adders.wallace_reducer, adder_func=adders.kogge_stone):
"""Same as tree_multiplier, but uses two's-complement signed integers"""
if len(A) == 1 or len(B) == 1:
raise pyrtl.PyrtlError("sign bit required, one or both wires too small")
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UCSBarchlab/PyRTL | pyrtl/rtllib/multipliers.py | _twos_comp_conditional | def _twos_comp_conditional(orig_wire, sign_bit, bw=None):
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if bw is None:
bw = len(orig_wire)
new_wire = pyrtl.WireVector(bw)
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with sign_bit:
new_wire |= ~orig_wire + ... | python | def _twos_comp_conditional(orig_wire, sign_bit, bw=None):
"""Returns two's complement of wire (using bitwidth bw) if sign_bit == 1"""
if bw is None:
bw = len(orig_wire)
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UCSBarchlab/PyRTL | pyrtl/rtllib/multipliers.py | fused_multiply_adder | def fused_multiply_adder(mult_A, mult_B, add, signed=False, reducer=adders.wallace_reducer,
adder_func=adders.kogge_stone):
""" Generate efficient hardware for a*b+c.
Multiplies two wirevectors together and adds a third wirevector to the
multiplication result, all in
one step. ... | python | def fused_multiply_adder(mult_A, mult_B, add, signed=False, reducer=adders.wallace_reducer,
adder_func=adders.kogge_stone):
""" Generate efficient hardware for a*b+c.
Multiplies two wirevectors together and adds a third wirevector to the
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UCSBarchlab/PyRTL | pyrtl/rtllib/multipliers.py | generalized_fma | def generalized_fma(mult_pairs, add_wires, signed=False, reducer=adders.wallace_reducer,
adder_func=adders.kogge_stone):
"""Generated an opimitized fused multiply adder.
A generalized FMA unit that multiplies each pair of numbers in mult_pairs,
then adds the resulting numbers and and th... | python | def generalized_fma(mult_pairs, add_wires, signed=False, reducer=adders.wallace_reducer,
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UCSBarchlab/PyRTL | pyrtl/transform.py | net_transform | def net_transform(transform_func, block=None, **kwargs):
"""
Maps nets to new sets of nets according to a custom function
:param transform_func:
Function signature: func(orig_net (logicnet)) -> keep_orig_net (bool)
:return:
"""
block = working_block(block)
with set_working_block(blo... | python | def net_transform(transform_func, block=None, **kwargs):
"""
Maps nets to new sets of nets according to a custom function
:param transform_func:
Function signature: func(orig_net (logicnet)) -> keep_orig_net (bool)
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UCSBarchlab/PyRTL | pyrtl/transform.py | all_nets | def all_nets(transform_func):
"""Decorator that wraps a net transform function"""
@functools.wraps(transform_func)
def t_res(**kwargs):
net_transform(transform_func, **kwargs)
return t_res | python | def all_nets(transform_func):
"""Decorator that wraps a net transform function"""
@functools.wraps(transform_func)
def t_res(**kwargs):
net_transform(transform_func, **kwargs)
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UCSBarchlab/PyRTL | pyrtl/transform.py | wire_transform | def wire_transform(transform_func, select_types=WireVector,
exclude_types=(Input, Output, Register, Const), block=None):
"""
Maps Wires to new sets of nets and wires according to a custom function
:param transform_func: The function you want to run on all wires
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UCSBarchlab/PyRTL | pyrtl/transform.py | all_wires | def all_wires(transform_func):
"""Decorator that wraps a wire transform function"""
@functools.wraps(transform_func)
def t_res(**kwargs):
wire_transform(transform_func, **kwargs)
return t_res | python | def all_wires(transform_func):
"""Decorator that wraps a wire transform function"""
@functools.wraps(transform_func)
def t_res(**kwargs):
wire_transform(transform_func, **kwargs)
return t_res | [
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UCSBarchlab/PyRTL | pyrtl/transform.py | replace_wires | def replace_wires(wire_map, block=None):
"""
Quickly replace all wires in a block
:param {old_wire: new_wire} wire_map: mapping of old wires to
new wires
"""
block = working_block(block)
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for old_w, new_w in wire_m... | python | def replace_wires(wire_map, block=None):
"""
Quickly replace all wires in a block
:param {old_wire: new_wire} wire_map: mapping of old wires to
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"""
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UCSBarchlab/PyRTL | pyrtl/transform.py | clone_wire | def clone_wire(old_wire, name=None):
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:param old_wire: The wire to clone
:param name: a name fo rhte new wire
Note that this function is mainly intended to be used when the
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:param name: a name fo rhte new wire
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UCSBarchlab/PyRTL | pyrtl/transform.py | copy_block | def copy_block(block=None, update_working_block=True):
"""
Makes a copy of an existing block
:param block: The block to clone. (defaults to the working block)
:return: The resulting block
"""
block_in = working_block(block)
block_out, temp_wv_map = _clone_block_and_wires(block_in)
mems ... | python | def copy_block(block=None, update_working_block=True):
"""
Makes a copy of an existing block
:param block: The block to clone. (defaults to the working block)
:return: The resulting block
"""
block_in = working_block(block)
block_out, temp_wv_map = _clone_block_and_wires(block_in)
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UCSBarchlab/PyRTL | pyrtl/transform.py | _clone_block_and_wires | def _clone_block_and_wires(block_in):
"""
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:param block_in: The block to change
:param synth_name: a name to prepend to all new copies of a wire
:return: the re... | python | def _clone_block_and_wires(block_in):
"""
This is a generic function to copy the WireVectors for another round of
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UCSBarchlab/PyRTL | pyrtl/transform.py | _copy_net | def _copy_net(block_out, net, temp_wv_net, mem_map):
"""This function makes a copy of all nets passed to it for synth uses
"""
new_args = tuple(temp_wv_net[a_arg] for a_arg in net.args)
new_dests = tuple(temp_wv_net[a_dest] for a_dest in net.dests)
if net.op in "m@": # special stuff for copying mem... | python | def _copy_net(block_out, net, temp_wv_net, mem_map):
"""This function makes a copy of all nets passed to it for synth uses
"""
new_args = tuple(temp_wv_net[a_arg] for a_arg in net.args)
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UCSBarchlab/PyRTL | pyrtl/transform.py | _get_new_block_mem_instance | def _get_new_block_mem_instance(op_param, mem_map, block_out):
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"""
memid, old_mem = op_param
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UCSBarchlab/PyRTL | pyrtl/helperfuncs.py | probe | def probe(w, name=None):
""" Print useful information about a WireVector when in debug mode.
:param w: WireVector from which to get info
:param name: optional name for probe (defaults to an autogenerated name)
:return: original WireVector w
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:param name: optional name for probe (defaults to an autogenerated name)
:return: original WireVector w
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UCSBarchlab/PyRTL | pyrtl/helperfuncs.py | rtl_assert | def rtl_assert(w, exp, block=None):
""" Add hardware assertions to be checked on the RTL design.
:param w: should be a WireVector
:param Exception exp: Exception to throw when assertion fails
:param Block block: block to which the assertion should be added (default to working block)
:return: the Ou... | python | def rtl_assert(w, exp, block=None):
""" Add hardware assertions to be checked on the RTL design.
:param w: should be a WireVector
:param Exception exp: Exception to throw when assertion fails
:param Block block: block to which the assertion should be added (default to working block)
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UCSBarchlab/PyRTL | pyrtl/helperfuncs.py | check_rtl_assertions | def check_rtl_assertions(sim):
""" Checks the values in sim to see if any registers assertions fail.
:param sim: Simulation in which to check the assertions
:return: None
"""
for (w, exp) in sim.block.rtl_assert_dict.items():
try:
value = sim.inspect(w)
if not value... | python | def check_rtl_assertions(sim):
""" Checks the values in sim to see if any registers assertions fail.
:param sim: Simulation in which to check the assertions
:return: None
"""
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UCSBarchlab/PyRTL | pyrtl/helperfuncs.py | wirevector_list | def wirevector_list(names, bitwidth=None, wvtype=WireVector):
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:param names: Names for the WireVectors. Can be a list or single comma/space-separated string
:param bitwidth: The desired bitwidth for the resulting WireVectors.
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""" Allocate and return a list of WireVectors.
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UCSBarchlab/PyRTL | pyrtl/helperfuncs.py | val_to_signed_integer | def val_to_signed_integer(value, bitwidth):
""" Return value as intrepreted as a signed integer under twos complement.
:param value: a python integer holding the value to convert
:param bitwidth: the length of the integer in bits to assume for conversion
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""" Return value as intrepreted as a signed integer under twos complement.
:param value: a python integer holding the value to convert
:param bitwidth: the length of the integer in bits to assume for conversion
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UCSBarchlab/PyRTL | pyrtl/helperfuncs.py | formatted_str_to_val | def formatted_str_to_val(data, format, enum_set=None):
""" Return an unsigned integer representation of the data given format specified.
:param data: a string holding the value to convert
:param format: a string holding a format which will be used to convert the data string
:param enum_set: an iterable... | python | def formatted_str_to_val(data, format, enum_set=None):
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UCSBarchlab/PyRTL | pyrtl/helperfuncs.py | val_to_formatted_str | def val_to_formatted_str(val, format, enum_set=None):
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:param val: a string holding an unsigned integer to convert
:param format: a string holding a format which will be used to convert the data string
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UCSBarchlab/PyRTL | pyrtl/helperfuncs.py | _NetCount.shrank | def shrank(self, block=None, percent_diff=0, abs_diff=1):
"""
Returns whether a block has less nets than before
:param Block block: block to check (if changed)
:param Number percent_diff: percentage difference threshold
:param int abs_diff: absolute difference threshold
... | python | def shrank(self, block=None, percent_diff=0, abs_diff=1):
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Returns whether a block has less nets than before
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:param int abs_diff: absolute difference threshold
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UCSBarchlab/PyRTL | pyrtl/rtllib/adders.py | kogge_stone | def kogge_stone(a, b, cin=0):
"""
Creates a Kogge-Stone adder given two inputs
:param WireVector a, b: The two WireVectors to add up (bitwidths don't need to match)
:param cin: An optimal carry in WireVector or value
:return: a Wirevector representing the output of the adder
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"""
Creates a Kogge-Stone adder given two inputs
:param WireVector a, b: The two WireVectors to add up (bitwidths don't need to match)
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UCSBarchlab/PyRTL | pyrtl/rtllib/adders.py | carrysave_adder | def carrysave_adder(a, b, c, final_adder=ripple_add):
"""
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:param WireVector a, b, c : the three wires to add up
:param function final_adder : The adder to use to do the final addition
:return: a wirevector with length 2 longer than the largest input
... | python | def carrysave_adder(a, b, c, final_adder=ripple_add):
"""
Adds three wirevectors up in an efficient manner
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UCSBarchlab/PyRTL | pyrtl/rtllib/adders.py | cla_adder | def cla_adder(a, b, cin=0, la_unit_len=4):
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Carry Lookahead Adder
:param int la_unit_len: the length of input that every unit processes
A Carry LookAhead Adder is an adder that is faster than
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"""
Carry Lookahead Adder
:param int la_unit_len: the length of input that every unit processes
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UCSBarchlab/PyRTL | pyrtl/rtllib/adders.py | _cla_adder_unit | def _cla_adder_unit(a, b, cin):
"""
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the inputs; their values don't rely on the sum. Every unit generates
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"""
gen = a & b
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assert(len(prop) == len(gen)... | python | def _cla_adder_unit(a, b, cin):
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UCSBarchlab/PyRTL | pyrtl/rtllib/adders.py | wallace_reducer | def wallace_reducer(wire_array_2, result_bitwidth, final_adder=kogge_stone):
"""
The reduction and final adding part of a dada tree. Useful for adding many numbers together
The use of single bitwidth wires is to allow for additional flexibility
:param [[Wirevector]] wire_array_2: An array of arrays of ... | python | def wallace_reducer(wire_array_2, result_bitwidth, final_adder=kogge_stone):
"""
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UCSBarchlab/PyRTL | pyrtl/rtllib/adders.py | dada_reducer | def dada_reducer(wire_array_2, result_bitwidth, final_adder=kogge_stone):
"""
The reduction and final adding part of a dada tree. Useful for adding many numbers together
The use of single bitwidth wires is to allow for additional flexibility
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"""
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UCSBarchlab/PyRTL | pyrtl/rtllib/adders.py | fast_group_adder | def fast_group_adder(wires_to_add, reducer=wallace_reducer, final_adder=kogge_stone):
"""
A generalization of the carry save adder, this is designed to add many numbers
together in a both area and time efficient manner. Uses a tree reducer
to achieve this performance
:param [WireVector] wires_to_a... | python | def fast_group_adder(wires_to_add, reducer=wallace_reducer, final_adder=kogge_stone):
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UCSBarchlab/PyRTL | pyrtl/memory.py | MemBlock._build | def _build(self, addr, data, enable):
""" Builds a write port. """
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if self.write_ports > self.max_write_ports:
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UCSBarchlab/PyRTL | pyrtl/rtllib/aes.py | AES.encryption | def encryption(self, plaintext, key):
"""
Builds a single cycle AES Encryption circuit
:param WireVector plaintext: text to encrypt
:param WireVector key: AES key to use to encrypt
:return: a WireVector containing the ciphertext
"""
if len(plaintext) != self._ke... | python | def encryption(self, plaintext, key):
"""
Builds a single cycle AES Encryption circuit
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UCSBarchlab/PyRTL | pyrtl/rtllib/aes.py | AES.decryption | def decryption(self, ciphertext, key):
"""
Builds a single cycle AES Decryption circuit
:param WireVector ciphertext: data to decrypt
:param WireVector key: AES key to use to encrypt (AES is symmetric)
:return: a WireVector containing the plaintext
"""
if len(cip... | python | def decryption(self, ciphertext, key):
"""
Builds a single cycle AES Decryption circuit
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:param WireVector key: AES key to use to encrypt (AES is symmetric)
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UCSBarchlab/PyRTL | pyrtl/rtllib/aes.py | AES.decryption_statem | def decryption_statem(self, ciphertext_in, key_in, reset):
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UCSBarchlab/PyRTL | pyrtl/rtllib/aes.py | AES._g | def _g(self, word, key_expand_round):
"""
One-byte left circular rotation, substitution of each byte
"""
import numbers
self._build_memories_if_not_exists()
a = libutils.partition_wire(word, 8)
sub = [self.sbox[a[index]] for index in (3, 0, 1, 2)]
if isins... | python | def _g(self, word, key_expand_round):
"""
One-byte left circular rotation, substitution of each byte
"""
import numbers
self._build_memories_if_not_exists()
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... | One-byte left circular rotation, substitution of each byte | [
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] | train | https://github.com/UCSBarchlab/PyRTL/blob/0988e5c9c10ededd5e1f58d5306603f9edf4b3e2/pyrtl/rtllib/aes.py#L223-L236 |
usrlocalben/pydux | pydux/extend.py | extend | def extend(*args):
"""shallow dictionary merge
Args:
a: dict to extend
b: dict to apply to a
Returns:
new instance of the same type as _a_, with _a_ and _b_ merged.
"""
if not args:
return {}
first = args[0]
rest = args[1:]
out = type(first)(first)
... | python | def extend(*args):
"""shallow dictionary merge
Args:
a: dict to extend
b: dict to apply to a
Returns:
new instance of the same type as _a_, with _a_ and _b_ merged.
"""
if not args:
return {}
first = args[0]
rest = args[1:]
out = type(first)(first)
... | [
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UCSBarchlab/PyRTL | pyrtl/inputoutput.py | input_from_blif | def input_from_blif(blif, block=None, merge_io_vectors=True):
""" Read an open blif file or string as input, updating the block appropriately
Assumes the blif has been flattened and their is only a single module.
Assumes that there is only one single shared clock and reset
Assumes that output is genera... | python | def input_from_blif(blif, block=None, merge_io_vectors=True):
""" Read an open blif file or string as input, updating the block appropriately
Assumes the blif has been flattened and their is only a single module.
Assumes that there is only one single shared clock and reset
Assumes that output is genera... | [
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Assumes the blif has been flattened and their is only a single module.
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Assumes that output is generated by Yosys with formals in a particular order
Ignores reset sign... | [
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UCSBarchlab/PyRTL | pyrtl/inputoutput.py | output_to_firrtl | def output_to_firrtl(open_file, rom_blocks=None, block=None):
""" Output the block as firrtl code to the output file.
Output_to_firrtl(open_file, rom_block, block)
If rom is intialized in pyrtl code, you can pass in the rom_blocks as a list [rom1, rom2, ...]
"""
block = working_block(block)
f =... | python | def output_to_firrtl(open_file, rom_blocks=None, block=None):
""" Output the block as firrtl code to the output file.
Output_to_firrtl(open_file, rom_block, block)
If rom is intialized in pyrtl code, you can pass in the rom_blocks as a list [rom1, rom2, ...]
"""
block = working_block(block)
f =... | [
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UCSBarchlab/PyRTL | pyrtl/inputoutput.py | _trivialgraph_default_namer | def _trivialgraph_default_namer(thing, is_edge=True):
""" Returns a "good" string for thing in printed graphs. """
if is_edge:
if thing.name is None or thing.name.startswith('tmp'):
return ''
else:
return '/'.join([thing.name, str(len(thing))])
elif isinstance(thing, ... | python | def _trivialgraph_default_namer(thing, is_edge=True):
""" Returns a "good" string for thing in printed graphs. """
if is_edge:
if thing.name is None or thing.name.startswith('tmp'):
return ''
else:
return '/'.join([thing.name, str(len(thing))])
elif isinstance(thing, ... | [
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UCSBarchlab/PyRTL | pyrtl/inputoutput.py | net_graph | def net_graph(block=None, split_state=False):
""" Return a graph representation of the current block.
Graph has the following form:
{ node1: { nodeA: edge1A, nodeB: edge1B},
node2: { nodeB: edge2B, nodeC: edge2C},
...
}
aka: edge = graph[source][dest]
Each node can... | python | def net_graph(block=None, split_state=False):
""" Return a graph representation of the current block.
Graph has the following form:
{ node1: { nodeA: edge1A, nodeB: edge1B},
node2: { nodeB: edge2B, nodeC: edge2C},
...
}
aka: edge = graph[source][dest]
Each node can... | [
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Graph has the following form:
{ node1: { nodeA: edge1A, nodeB: edge1B},
node2: { nodeB: edge2B, nodeC: edge2C},
...
}
aka: edge = graph[source][dest]
Each node can be either a logic net or a WireVector (e.g. an Input,... | [
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UCSBarchlab/PyRTL | pyrtl/inputoutput.py | output_to_trivialgraph | def output_to_trivialgraph(file, namer=_trivialgraph_default_namer, block=None):
""" Walk the block and output it in trivial graph format to the open file. """
graph = net_graph(block)
node_index_map = {} # map node -> index
# print the list of nodes
for index, node in enumerate(graph):
pr... | python | def output_to_trivialgraph(file, namer=_trivialgraph_default_namer, block=None):
""" Walk the block and output it in trivial graph format to the open file. """
graph = net_graph(block)
node_index_map = {} # map node -> index
# print the list of nodes
for index, node in enumerate(graph):
pr... | [
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UCSBarchlab/PyRTL | pyrtl/inputoutput.py | _graphviz_default_namer | def _graphviz_default_namer(thing, is_edge=True, is_to_splitmerge=False):
""" Returns a "good" graphviz label for thing. """
if is_edge:
if (thing.name is None or
thing.name.startswith('tmp') or
isinstance(thing, (Input, Output, Const, Register))):
name = ''
... | python | def _graphviz_default_namer(thing, is_edge=True, is_to_splitmerge=False):
""" Returns a "good" graphviz label for thing. """
if is_edge:
if (thing.name is None or
thing.name.startswith('tmp') or
isinstance(thing, (Input, Output, Const, Register))):
name = ''
... | [
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UCSBarchlab/PyRTL | pyrtl/inputoutput.py | output_to_graphviz | def output_to_graphviz(file, namer=_graphviz_default_namer, block=None):
""" Walk the block and output it in graphviz format to the open file. """
print(block_to_graphviz_string(block, namer), file=file) | python | def output_to_graphviz(file, namer=_graphviz_default_namer, block=None):
""" Walk the block and output it in graphviz format to the open file. """
print(block_to_graphviz_string(block, namer), file=file) | [
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UCSBarchlab/PyRTL | pyrtl/inputoutput.py | block_to_graphviz_string | def block_to_graphviz_string(block=None, namer=_graphviz_default_namer):
""" Return a graphviz string for the block. """
graph = net_graph(block, split_state=True)
node_index_map = {} # map node -> index
rstring = """\
digraph g {\n
graph [splines="spline"];
n... | python | def block_to_graphviz_string(block=None, namer=_graphviz_default_namer):
""" Return a graphviz string for the block. """
graph = net_graph(block, split_state=True)
node_index_map = {} # map node -> index
rstring = """\
digraph g {\n
graph [splines="spline"];
n... | [
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UCSBarchlab/PyRTL | pyrtl/inputoutput.py | block_to_svg | def block_to_svg(block=None):
""" Return an SVG for the block. """
block = working_block(block)
try:
from graphviz import Source
return Source(block_to_graphviz_string())._repr_svg_()
except ImportError:
raise PyrtlError('need graphviz installed (try "pip install graphviz")') | python | def block_to_svg(block=None):
""" Return an SVG for the block. """
block = working_block(block)
try:
from graphviz import Source
return Source(block_to_graphviz_string())._repr_svg_()
except ImportError:
raise PyrtlError('need graphviz installed (try "pip install graphviz")') | [
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UCSBarchlab/PyRTL | pyrtl/inputoutput.py | trace_to_html | def trace_to_html(simtrace, trace_list=None, sortkey=None):
""" Return a HTML block showing the trace. """
from .simulation import SimulationTrace, _trace_sort_key
if not isinstance(simtrace, SimulationTrace):
raise PyrtlError('first arguement must be of type SimulationTrace')
trace = simtrace... | python | def trace_to_html(simtrace, trace_list=None, sortkey=None):
""" Return a HTML block showing the trace. """
from .simulation import SimulationTrace, _trace_sort_key
if not isinstance(simtrace, SimulationTrace):
raise PyrtlError('first arguement must be of type SimulationTrace')
trace = simtrace... | [
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usrlocalben/pydux | pydux/create_store.py | create_store | def create_store(reducer, initial_state=None, enhancer=None):
"""
redux in a nutshell.
observable has been omitted.
Args:
reducer: root reducer function for the state tree
initial_state: optional initial state data
enhancer: optional enhancer function for middleware etc.
R... | python | def create_store(reducer, initial_state=None, enhancer=None):
"""
redux in a nutshell.
observable has been omitted.
Args:
reducer: root reducer function for the state tree
initial_state: optional initial state data
enhancer: optional enhancer function for middleware etc.
R... | [
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reducer: root reducer function for the state tree
initial_state: optional initial state data
enhancer: optional enhancer function for middleware etc.
Returns:
a Pydux store | [
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] | train | https://github.com/usrlocalben/pydux/blob/943ca1c75357b9289f55f17ff2d997a66a3313a4/pydux/create_store.py#L30-L124 |
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