repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
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tactcomplabs/xbgas-binutils-gdb | 22,331 | sim/testsuite/h8300/addx.s | # Hitachi H8 testcase 'addx'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# addx.b #xx:8, rd8 ; 9 rd8 xxxxxxxx
# addx.b #xx:8, @erd ; 7 d erd ???? 9 ???? xxxxxxxx
# addx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx
# addx.b rs8, rd8 ; 0 e rs8 rd8
# addx.b rs8, @erd ; 7 d erd ???? 0 e rs8 ????
# addx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 0 e rs8 ????
# addx.b @ers, rd8 ; 7 c ers ???? 0 e ???? rd8
# addx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 0 e ???? rd8
# addx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 1 ????
# addx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 1 ????
#
# word ops
# long ops
.data
byte_src: .byte 0x5
byte_dest: .byte 0
.align 2
word_src: .word 0x505
word_dest: .word 0
.align 4
long_src: .long 0x50505
long_dest: .long 0
start
addx_b_imm8_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,Rd ; Addx with carry initially zero.
addx.b #5, r0l ; Immediate 8-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xa5aa r0 ; add result: a5 + 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_imm8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,Rd ; Addx with carry initially one.
set_carry_flag
addx.b #5, r0l ; Immediate 8-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xa5ab r0 ; add result: a5 + 5 + 1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5ab er0 ; add result: a5 + 5 + 1
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
addx_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,@eRd ; Addx to register indirect
mov #byte_dest, er0
addx.b #5, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #5, @byte_dest
beq .Lb1
fail
.Lb1:
addx_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,@eRd- ; Addx to register post-decrement
mov #byte_dest, er0
addx.b #5, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #10, @byte_dest
beq .Lb2
fail
.Lb2:
.endif
addx_b_reg8_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b Rs,Rd ; addx with carry initially zero
mov.b #5, r0h
addx.b r0h, r0l ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0x05aa r0 ; add result: a5 + 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b Rs,Rd ; addx with carry initially one
mov.b #5, r0h
set_carry_flag
addx.b r0h, r0l ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0x05ab r0 ; add result: a5 + 5 + 1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505ab er0 ; add result: a5 + 5 + 1
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
addx_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b rs8,@eRd ; Addx to register indirect
mov #byte_dest, er0
mov.b #5, r1l
addx.b r1l, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #15, @byte_dest
beq .Lb3
fail
.Lb3:
addx_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b rs8,@eRd- ; Addx to register post-decrement
mov #byte_dest, er0
mov.b #5, r1l
addx.b r1l, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #20, @byte_dest
beq .Lb4
fail
.Lb4:
addx_b_rsind_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs,rd8 ; Addx from reg indirect to reg
mov #byte_src, er0
addx.b @er0, r1l
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_src er0 ; er0 still contains address
test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_rspostdec_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs-,rd8 ; Addx to register post-decrement
mov #byte_src, er0
addx.b @er0-, r1l
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_src-1 er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_rsind_rsind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs,rd8 ; Addx from reg indirect to reg
mov #byte_src, er0
mov #byte_dest, er1
addx.b @er0, @er1
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_src er0 ; er0 still contains src address
test_h_gr32 byte_dest er1 ; er1 still contains dst address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #25, @byte_dest
beq .Lb5
fail
.Lb5:
addx_b_rspostdec_rspostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs-,rd8 ; Addx to register post-decrement
mov #byte_src, er0
mov #byte_dest, er1
addx.b @er0-, @er1-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_src-1 er0 ; er0 contains src address minus one
test_h_gr32 byte_dest-1 er1 ; er1 contains dst address minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #30, @byte_dest
beq .Lb6
fail
.Lb6:
addx_w_imm16_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,Rd ; Addx with carry initially zero.
addx.w #0x505, r0 ; Immediate 16-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xaaaa r0 ; add result: 0xa5a5 + 0x505
test_h_gr32 0xa5a5aaaa er0 ; add result: 0xa5a5 + 0x505
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_imm16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,Rd ; Addx with carry initially one.
set_carry_flag
addx.w #0x505, r0 ; Immediate 16-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xaaab r0 ; add result: 0xa5a5 + 0x505 + 1
test_h_gr32 0xa5a5aaab er0 ; add result: 0xa5a5 + 0x505 + 1
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_imm16_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,@eRd ; Addx to register indirect
mov #word_dest, er0
addx.w #0x505, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x505, @word_dest
beq .Lw1
fail
.Lw1:
addx_w_imm16_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,@eRd- ; Addx to register post-decrement
mov #word_dest, er0
addx.w #0x505, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest-2 er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0xa0a, @word_dest
beq .Lw2
fail
.Lw2:
addx_w_reg16_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w Rs,Rd ; addx with carry initially zero
mov.w #0x505, e0
addx.w e0, r0 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x0505aaaa er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w Rs,Rd ; addx with carry initially one
mov.w #0x505, e0
set_carry_flag
addx.w e0, r0 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x0505aaab er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_reg16_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w rs8,@eRd ; Addx to register indirect
mov #word_dest, er0
mov.w #0x505, r1
addx.w r1, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest er0 ; er0 still contains address
test_h_gr32 0xa5a50505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0xf0f, @word_dest
beq .Lw3
fail
.Lw3:
addx_w_reg16_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w rs8,@eRd- ; Addx to register post-decrement
mov #word_dest, er0
mov.w #0x505, r1
addx.w r1, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest-2 er0 ; er0 contains address minus one
test_h_gr32 0xa5a50505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x1414, @word_dest
beq .Lw4
fail
.Lw4:
addx_w_rsind_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs,rd8 ; Addx from reg indirect to reg
mov #word_src, er0
addx.w @er0, r1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_src er0 ; er0 still contains address
test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_rspostdec_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs-,rd8 ; Addx to register post-decrement
mov #word_src, er0
addx.w @er0-, r1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_src-2 er0 ; er0 contains address minus one
test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_rsind_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs,rd8 ; Addx from reg indirect to reg
mov #word_src, er0
mov #word_dest, er1
addx.w @er0, @er1
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_src er0 ; er0 still contains src address
test_h_gr32 word_dest er1 ; er1 still contains dst address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x1919, @word_dest
beq .Lw5
fail
.Lw5:
addx_w_rspostdec_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs-,rd8 ; Addx to register post-decrement
mov #word_src, er0
mov #word_dest, er1
addx.w @er0-, @er1-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_src-2 er0 ; er0 contains src address minus one
test_h_gr32 word_dest-2 er1 ; er1 contains dst address minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x1e1e, @word_dest
beq .Lw6
fail
.Lw6:
addx_l_imm32_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,Rd ; Addx with carry initially zero.
addx.l #0x50505, er0 ; Immediate 32-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0xa5aaaaaa er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_imm32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,Rd ; Addx with carry initially one.
set_carry_flag
addx.l #0x50505, er0 ; Immediate 32-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0xa5aaaaab er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_imm32_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,@eRd ; Addx to register indirect
mov #long_dest, er0
addx.l #0x50505, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x50505, @long_dest
beq .Ll1
fail
.Ll1:
addx_l_imm32_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,@eRd- ; Addx to register post-decrement
mov #long_dest, er0
addx.l #0x50505, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest-4 er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0xa0a0a, @long_dest
beq .Ll2
fail
.Ll2:
addx_l_reg32_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l Rs,Rd ; addx with carry initially zero
mov.l #0x50505, er0
addx.l er0, er1 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x50505 er0 ; add load
test_h_gr32 0xa5aaaaaa er1 ; add result:
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l Rs,Rd ; addx with carry initially one
mov.l #0x50505, er0
set_carry_flag
addx.l er0, er1 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x50505 er0 ; add result:
test_h_gr32 0xa5aaaaab er1 ; add result:
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_reg32_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l rs8,@eRd ; Addx to register indirect
mov #long_dest, er0
mov.l #0x50505, er1
addx.l er1, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest er0 ; er0 still contains address
test_h_gr32 0x50505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0xf0f0f, @long_dest
beq .Ll3
fail
.Ll3:
addx_l_reg32_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l rs8,@eRd- ; Addx to register post-decrement
mov #long_dest, er0
mov.l #0x50505, er1
addx.l er1, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest-4 er0 ; er0 contains address minus one
test_h_gr32 0x50505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x141414, @long_dest
beq .Ll4
fail
.Ll4:
addx_l_rsind_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs,rd8 ; Addx from reg indirect to reg
mov #long_src, er0
addx.l @er0, er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_src er0 ; er0 still contains address
test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_rspostdec_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs-,rd8 ; Addx to register post-decrement
mov #long_src, er0
addx.l @er0-, er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_src-4 er0 ; er0 contains address minus one
test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_rsind_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs,rd8 ; Addx from reg indirect to reg
mov #long_src, er0
mov #long_dest, er1
addx.l @er0, @er1
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_src er0 ; er0 still contains src address
test_h_gr32 long_dest er1 ; er1 still contains dst address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x191919, @long_dest
beq .Ll5
fail
.Ll5:
addx_l_rspostdec_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs-,rd8 ; Addx to register post-decrement
mov #long_src, er0
mov #long_dest, er1
addx.l @er0-, @er1-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_src-4 er0 ; er0 contains src address minus one
test_h_gr32 long_dest-4 er1 ; er1 contains dst address minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x1e1e1e, @long_dest
beq .Ll6
fail
.Ll6:
.endif
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 2,224 | sim/testsuite/h8300/subl.s | # Hitachi H8 testcase 'sub.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ;
sub_l_imm3: ; 3-bit immediate mode only for h8sx
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.l #xx:3,eRd ; Immediate 3-bit operand
sub.l #7:3, er0
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
sub_l_imm16: ; sub immediate 16-bit value
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.l #xx:16,eRd ; Immediate 16-bit operand
sub.l #0x1111:16, er0
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111
test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
sub_l_imm32:
;; sub.l immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.l #xx:32,Rd
sub.l #0x11111111, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
sub.l.reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.l Rs,Rd
mov.l #0x11111111, er1
sub.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
test_h_gr32 0x11111111 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 3,836 | sim/testsuite/h8300/ldm.s | # Hitachi H8 testcase 'ldm', 'stm'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
.align 4
_stack: .long 0,1,2,3,4,5,6,7,8,9,0,0,0,0,0,0
.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
_stack_top:
start
.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
stm_2reg:
set_grs_a5a5
mov #_stack_top, er7
mov #2, er2
mov #3, er3
set_ccr_zero
stm er2-er3, @-sp
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_h_gr32 2 er2
test_h_gr32 3 er3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_h_gr32 _stack_top-8, er7
mov @_stack_top-4, er0
cmp #2, er0
bne fail1
mov @_stack_top-8, er0
cmp #3, er0
bne fail1
mov @_stack_top-12, er0
cmp #0, er0
bne fail1
stm_3reg:
set_grs_a5a5
mov #_stack_top, er7
mov #4, er4
mov #5, er5
mov #6, er6
set_ccr_zero
stm er4-er6, @-sp
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 4 er4
test_h_gr32 5 er5
test_h_gr32 6 er6
test_h_gr32 _stack_top-12, er7
mov @_stack_top-4, er0
cmp #4, er0
bne fail1
mov @_stack_top-8, er0
cmp #5, er0
bne fail1
mov @_stack_top-12, er0
cmp #6, er0
bne fail1
mov @_stack_top-16, er0
cmp #0, er0
bne fail1
stm_4reg:
set_grs_a5a5
mov #_stack_top, er7
mov #1, er0
mov #2, er1
mov #3, er2
mov #4, er3
set_ccr_zero
stm er0-er3, @-sp
test_cc_clear
test_h_gr32 1 er0
test_h_gr32 2 er1
test_h_gr32 3 er2
test_h_gr32 4 er3
test_gr_a5a5 4 ; Make sure other general regs not disturbed
test_gr_a5a5 5
test_gr_a5a5 6
test_h_gr32 _stack_top-16, er7
mov @_stack_top-4, er0
cmp #1, er0
bne fail1
mov @_stack_top-8, er0
cmp #2, er0
bne fail1
mov @_stack_top-12, er0
cmp #3, er0
bne fail1
mov @_stack_top-16, er0
cmp #4, er0
bne fail1
mov @_stack_top-20, er0
cmp #0, er0
bne fail1
ldm_2reg:
set_grs_a5a5
mov #_stack, er7
set_ccr_zero
ldm @sp+, er2-er3
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_h_gr32 1 er2
test_h_gr32 0 er3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_h_gr32 _stack+8, er7
ldm_3reg:
set_grs_a5a5
mov #_stack+4, er7
set_ccr_zero
ldm @sp+, er4-er6
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 3 er4
test_h_gr32 2 er5
test_h_gr32 1 er6
test_h_gr32 _stack+16, er7
ldm_4reg:
set_grs_a5a5
mov #_stack+4, er7
set_ccr_zero
ldm @sp+, er0-er3
test_cc_clear
test_h_gr32 4 er0
test_h_gr32 3 er1
test_h_gr32 2 er2
test_h_gr32 1 er3
test_gr_a5a5 4 ; Make sure other general regs not disturbed
test_gr_a5a5 5
test_gr_a5a5 6
test_h_gr32 _stack+20, er7
.endif
pushpop:
set_grs_a5a5
.if (sim_cpu == h8300)
mov #_stack_top, r7
mov #12, r1
mov #34, r2
mov #56, r3
push r1
push r2
push r3
pop r4
pop r5
pop r6
test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed
test_h_gr16 12 r1
test_h_gr16 34 r2
test_h_gr16 56 r3
test_h_gr16 56 r4
test_h_gr16 34 r5
test_h_gr16 12 r6
mov #_stack_top, r0
cmp.w r0, r7
bne fail1
.else
mov #_stack_top, er7
mov #12, er1
mov #34, er2
mov #56, er3
push er1
push er2
push er3
pop er4
pop er5
pop er6
test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed
test_h_gr32 12 er1
test_h_gr32 34 er2
test_h_gr32 56 er3
test_h_gr32 56 er4
test_h_gr32 34 er5
test_h_gr32 12 er6
test_h_gr32 _stack_top, er7
.endif
pass
exit 0
fail1: fail
|
tactcomplabs/xbgas-binutils-gdb | 7,908 | sim/testsuite/h8300/ldc.s | # Hitachi H8 testcase 'ldc'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_pre:
.byte 0
byte_src:
.byte 0xff
byte_post:
.byte 0
start
ldc_imm8_ccr:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr ; set all ccr flags high, immediate operand
bcs .L1 ; carry flag set?
fail
.L1: bvs .L2 ; overflow flag set?
fail
.L2: beq .L3 ; zero flag set?
fail
.L3: bmi .L4 ; neg flag set?
fail
.L4:
ldc #0, ccr ; set all ccr flags low, immediate operand
bcc .L5 ; carry flag clear?
fail
.L5: bvc .L6 ; overflow flag clear?
fail
.L6: bne .L7 ; zero flag clear?
fail
.L7: bpl .L8 ; neg flag clear?
fail
.L8:
test_cc_clear
test_grs_a5a5
ldc_reg8_ccr:
set_grs_a5a5
set_ccr_zero
mov #0xff, r0h
ldc r0h, ccr ; set all ccr flags high, reg operand
bcs .L11 ; carry flag set?
fail
.L11: bvs .L12 ; overflow flag set?
fail
.L12: beq .L13 ; zero flag set?
fail
.L13: bmi .L14 ; neg flag set?
fail
.L14:
mov #0, r0h
ldc r0h, ccr ; set all ccr flags low, reg operand
bcc .L15 ; carry flag clear?
fail
.L15: bvc .L16 ; overflow flag clear?
fail
.L16: bne .L17 ; zero flag clear?
fail
.L17: bpl .L18 ; neg flag clear?
fail
.L18:
test_cc_clear
test_h_gr16 0x00a5 r0 ; Register 0 modified by test procedure.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
ldc_imm8_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
ldc #0x87, exr ; set exr to 0x87
stc exr, r0l ; retrieve and check exr value
cmp.b #0x87, r0l
beq .L19
fail
.L19:
test_h_gr16 0xa587 r0 ; Register 0 modified by test procedure.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_reg8_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
mov #0x87, r0h
ldc r0h, exr ; set exr to 0x87
stc exr, r0l ; retrieve and check exr value
cmp.b #0x87, r0l
beq .L21
fail
.L21:
test_h_gr16 0x8787 r0 ; Register 0 modified by test procedure.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_abs16_ccr:
set_grs_a5a5
set_ccr_zero
ldc @byte_src:16, ccr ; abs16 src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_abs16_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
ldc @byte_src:16, exr ; abs16 src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_abs32_ccr:
set_grs_a5a5
set_ccr_zero
ldc @byte_src:32, ccr ; abs32 src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_abs32_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
ldc @byte_src:32, exr ; abs32 src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_disp16_ccr:
set_grs_a5a5
set_ccr_zero
mov #byte_pre, er1
ldc @(1:16, er1), ccr ; disp16 src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_h_gr32 byte_pre, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_disp16_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
mov #byte_post, er1
ldc @(-1:16, er1), exr ; disp16 src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_h_gr32 byte_post, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_disp32_ccr:
set_grs_a5a5
set_ccr_zero
mov #byte_pre, er1
ldc @(1:32, er1), ccr ; disp32 src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_h_gr32 byte_pre, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_disp32_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
mov #byte_post, er1
ldc @(-1:32, er1), exr ; disp16 src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_h_gr32 byte_post, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_postinc_ccr:
set_grs_a5a5
set_ccr_zero
mov #byte_src, er1
ldc @er1+, ccr ; postinc src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_h_gr32 byte_src+2, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_postinc_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
mov #byte_src, er1
ldc @er1+, exr ; postinc src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_h_gr32 byte_src+2, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_ind_ccr:
set_grs_a5a5
set_ccr_zero
mov #byte_src, er1
ldc @er1, ccr ; postinc src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_h_gr32 byte_src, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_ind_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
mov #byte_src, er1
ldc @er1, exr ; postinc src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_h_gr32 byte_src, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
ldc_reg_sbr:
set_grs_a5a5
set_ccr_zero
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
stc sbr, er1 ; retreive and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_reg_vbr:
set_grs_a5a5
set_ccr_zero
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
stc vbr, er1 ; retreive and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 2,597 | sim/testsuite/h8300/inc.s | # Hitachi H8 testcase 'inc, inc.w, inc.l'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
inc_b:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.b Rd
inc.b r0h ; Increment 8-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa6a5 r0 ; inc result: a6|a5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; non-zero means h8300h, s, or sx
inc_w_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.w #1, Rd
inc.w #1, r0 ; Increment 16-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a6 r0 ; inc result: a5|a6
test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
inc_w_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.w #2, Rd
inc.w #2, r0 ; Increment 16-bit reg by two
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a7 r0 ; inc result: a5|a7
test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
inc_l_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.l #1, eRd
inc.l #1, er0 ; Increment 32-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
inc_l_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.l #2, eRd
inc.l #2, er0 ; Increment 32-bit reg by two
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,711 | sim/testsuite/h8300/orl.s | # Hitachi H8 testcase 'or.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
or_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.l #xx:16,Rd
or.l #0xaaaa, er0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5afaf er0 ; or result: a5a5a5a5 | aaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
or_l_imm32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.l #xx:32,Rd
or.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
or_l_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.l Rs,Rd
mov.l #0xaaaaaaaa, er1
or.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa
test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 6,997 | sim/testsuite/h8300/stc.s | # Hitachi H8 testcase 'stc'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_dest1:
.byte 0
.byte 0
byte_dest2:
.byte 0
.byte 0
byte_dest3:
.byte 0
.byte 0
byte_dest4:
.byte 0
.byte 0
byte_dest5:
.byte 0
.byte 0
byte_dest6:
.byte 0
.byte 0
byte_dest7:
.byte 0
.byte 0
byte_dest8:
.byte 0
.byte 0
byte_dest9:
.byte 0
.byte 0
byte_dest10:
.byte 0
.byte 0
byte_dest11:
.byte 0
.byte 0
byte_dest12:
.byte 0
.byte 0
start
stc_ccr_reg8:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr ; test value
stc ccr, r0h ; copy test value to r0h
test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l
.if (sim_cpu) ; h/s/sx
test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
stc_exr_reg8:
set_grs_a5a5
set_ccr_zero
ldc #0x87, exr ; set exr to 0x87
stc exr, r0l ; retrieve and check exr value
cmp.b #0x87, r0l
beq .L21
fail
.L21:
test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_abs16:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr
stc ccr, @byte_dest1:16 ; abs16 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_abs16:
set_grs_a5a5
set_ccr_zero
ldc #0x87, exr
stc exr, @byte_dest2:16 ; abs16 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_abs32:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr
stc ccr, @byte_dest3:32 ; abs32 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_abs32:
set_grs_a5a5
set_ccr_zero
ldc #0x87, exr
stc exr, @byte_dest4:32 ; abs32 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_disp16:
set_grs_a5a5
set_ccr_zero
mov #byte_dest5-1, er1
ldc #0xff, ccr
stc ccr, @(1:16,er1) ; disp16 dest (5)
test_h_gr32 byte_dest5-1, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_disp16:
set_grs_a5a5
set_ccr_zero
mov #byte_dest6+1, er1
ldc #0x87, exr
stc exr, @(-1:16,er1) ; disp16 dest (6)
test_h_gr32 byte_dest6+1, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_disp32:
set_grs_a5a5
set_ccr_zero
mov #byte_dest7-1, er1
ldc #0xff, ccr
stc ccr, @(1:32,er1) ; disp32 dest (7)
test_h_gr32 byte_dest7-1, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_disp32:
set_grs_a5a5
set_ccr_zero
mov #byte_dest8+1, er1
ldc #0x87, exr
stc exr, @(-1:32,er1) ; disp16 dest (8)
test_h_gr32 byte_dest8+1, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_predecr:
set_grs_a5a5
set_ccr_zero
mov #byte_dest9+2, er1
ldc #0xff, ccr
stc ccr, @-er1 ; predecr dest (9)
test_h_gr32 byte_dest9 er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_predecr:
set_grs_a5a5
set_ccr_zero
mov #byte_dest10+2, er1
ldc #0x87, exr
stc exr, @-er1 ; predecr dest (10)
test_h_gr32 byte_dest10, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_ind:
set_grs_a5a5
set_ccr_zero
mov #byte_dest11, er1
ldc #0xff, ccr
stc ccr, @er1 ; postinc dest (11)
test_h_gr32 byte_dest11, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_ind:
set_grs_a5a5
set_ccr_zero
mov #byte_dest12, er1
ldc #0x87, exr
stc exr, @er1, exr ; postinc dest (12)
test_h_gr32 byte_dest12, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
stc_sbr_reg:
set_grs_a5a5
set_ccr_zero
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
stc sbr, er1 ; retreive and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_vbr_reg:
set_grs_a5a5
set_ccr_zero
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
stc vbr, er1 ; retreive and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
check_results:
;; Now check results
mov @byte_dest1, r0h
cmp.b #0xff, r0h
beq .L1
fail
.L1: mov @byte_dest2, r0h
cmp.b #0x87, r0h
beq .L2
fail
.L2: mov @byte_dest3, r0h
cmp.b #0xff, r0h
beq .L3
fail
.L3: mov @byte_dest4, r0h
cmp.b #0x87, r0h
beq .L4
fail
.L4: mov @byte_dest5, r0h
cmp.b #0xff, r0h
beq .L5
fail
.L5: mov @byte_dest6, r0h
cmp.b #0x87, r0h
beq .L6
fail
.L6: mov @byte_dest7, r0h
cmp.b #0xff, r0h
beq .L7
fail
.L7: mov @byte_dest8, r0h
cmp.b #0x87, r0h
beq .L8
fail
.L8: mov @byte_dest9, r0h
cmp.b #0xff, r0h
beq .L9
fail
.L9: mov @byte_dest10, r0h
cmp.b #0x87, r0h
beq .L10
fail
.L10: mov @byte_dest11, r0h
cmp.b #0xff, r0h
beq .L11
fail
.L11: mov @byte_dest12, r0h
cmp.b #0x87, r0h
beq .L12
fail
.L12:
.endif
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 26,009 | sim/testsuite/h8300/rotl.s | # Hitachi H8 testcase 'rotl'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte 0xa5
.align 2
word_dest: .word 0xa5a5
.align 4
long_dest: .long 0xa5a5a5a5
.text
rotl_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotl.b r0l ; shift left arithmetic by one
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa54b r0 ; 1010 0101 -> 0100 1011
.if (sim_cpu)
test_h_gr32 0xa5a5a54b er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotl_b_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotl.b @er0 ; shift right arithmetic by one, indirect
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0100 1011
cmp.b #0x4b, @byte_dest
beq .Lbind1
fail
.Lbind1:
mov.b #0xa5, @byte_dest
rotl_b_indexb16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r0l
rotl.b @(byte_dest-5:16, r0.b) ; indexed byte/byte
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a5a505 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0100 1011
cmp.b #0x4b, @byte_dest
beq .Lbindexb161
fail
.Lbindexb161:
mov.b #0xa5, @byte_dest
rotl_b_indexw16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r0
rotl.b @(byte_dest-256:16, r0.w) ; indexed byte/word
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a50100 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0100 1011
cmp.b #0x4b, @byte_dest
beq .Lbindexw161
fail
.Lbindexw161:
mov.b #0xa5, @byte_dest
rotl_b_indexl16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er0
rotl.b @(byte_dest+1:16, er0.l) ; indexed byte/long
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xffffffff er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0100 1011
cmp.b #0x4b, @byte_dest
beq .Lbindexl161
fail
.Lbindexl161:
mov.b #0xa5, @byte_dest
rotl_b_indexb32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r1l
rotl.b @(byte_dest-5:32, r1.b) ; indexed byte/byte
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a5a505 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0100 1011
cmp.b #0x4b, @byte_dest
beq .Lbindexb321
fail
.Lbindexb321:
mov.b #0xa5, @byte_dest
rotl_b_indexw32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r1
rotl.b @(byte_dest-256:32, r1.w) ; indexed byte/word
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a50100 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0100 1011
cmp.b #0x4b, @byte_dest
beq .Lbindexw321
fail
.Lbindexw321:
mov.b #0xa5, @byte_dest
rotl_b_indexl32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er1
rotl.b @(byte_dest+1:32, er1.l) ; indexed byte/long
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xffffffff er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0100 1011
cmp.b #0x4b, @byte_dest
beq .Lbindexl321
fail
.Lbindexl321:
mov.b #0xa5, @byte_dest
.endif
rotl_b_reg8_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotl.b #2, r0l ; shift left arithmetic by two
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa596 r0 ; 1010 0101 -> 1001 0110
.if (sim_cpu)
test_h_gr32 0xa5a5a596 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotl_b_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotl.b #2, @er0 ; shift right arithmetic by one, indirect
test_carry_clear ; H=0 N=1 Z=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1001 0110
cmp.b #0x96, @byte_dest
beq .Lbind2
fail
.Lbind2:
mov.b #0xa5, @byte_dest
rotl_b_indexb16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r0l
rotl.b #2, @(byte_dest-5:16, r0.b) ; indexed byte/byte
test_carry_clear ; H=0 N=1 Z=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a5a505 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1001 0110
cmp.b #0x96, @byte_dest
beq .Lbindexb162
fail
.Lbindexb162:
mov.b #0xa5, @byte_dest
rotl_b_indexw16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r0
rotl.b #2, @(byte_dest-256:16, r0.w) ; indexed byte/word
test_carry_clear ; H=0 N=1 Z=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a50100 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1001 0110
cmp.b #0x96, @byte_dest
beq .Lbindexw162
fail
.Lbindexw162:
mov.b #0xa5, @byte_dest
rotl_b_indexl16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er0
rotl.b #2, @(byte_dest+1:16, er0.l) ; indexed byte/long
test_carry_clear ; H=0 N=1 Z=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xffffffff er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1001 0110
cmp.b #0x96, @byte_dest
beq .Lbindexl162
fail
.Lbindexl162:
mov.b #0xa5, @byte_dest
rotl_b_indexb32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r1l
rotl.b #2, @(byte_dest-5:32, r1.b) ; indexed byte/byte
test_carry_clear ; H=0 N=1 Z=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a5a505 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1001 0110
cmp.b #0x96, @byte_dest
beq .Lbindexb322
fail
.Lbindexb322:
mov.b #0xa5, @byte_dest
rotl_b_indexw32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r1
rotl.b #2, @(byte_dest-256:32, r1.w) ; indexed byte/word
test_carry_clear ; H=0 N=1 Z=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a50100 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1001 0110
cmp.b #0x96, @byte_dest
beq .Lbindexw322
fail
.Lbindexw322:
mov.b #0xa5, @byte_dest
rotl_b_indexl32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er1
rotl.b #2, @(byte_dest+1:32, er1.l) ; indexed byte/long
test_carry_clear ; H=0 N=1 Z=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xffffffff er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1001 0110
cmp.b #0x96, @byte_dest
beq .Lbindexl322
fail
.Lbindexl322:
mov.b #0xa5, @byte_dest
.endif
.if (sim_cpu) ; Not available in h8300 mode
rotl_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotl.w r0 ; shift left arithmetic by one
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x4b4b r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
test_h_gr32 0xa5a54b4b er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotl_w_indexb16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r0l
rotl.w @(word_dest-10:16, r0.b) ; indexed word/byte
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a5a505 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
cmp.w #0x4b4b, @word_dest
beq .Lwindexb161
fail
.Lwindexb161:
mov.w #0xa5a5, @word_dest
rotl_w_indexw16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r0
rotl.w @(word_dest-512:16, r0.w) ; indexed word/word
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a50100 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
cmp.w #0x4b4b, @word_dest
beq .Lwindexw161
fail
.Lwindexw161:
mov.w #0xa5a5, @word_dest
rotl_w_indexl16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er0
rotl.w @(word_dest+2:16, er0.l) ; indexed word/long
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xffffffff er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
cmp.w #0x4b4b, @word_dest
beq .Lwindexl161
fail
.Lwindexl161:
mov.w #0xa5a5, @word_dest
rotl_w_indexb32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r1l
rotl.w @(word_dest-10:32, r1.b) ; indexed word/byte
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a5a505 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
cmp.w #0x4b4b, @word_dest
beq .Lwindexb321
fail
.Lwindexb321:
mov.w #0xa5a5, @word_dest
rotl_w_indexw32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r1
rotl.w @(word_dest-512:32, r1.w) ; indexed word/byte
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a50100 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
cmp.w #0x4b4b, @word_dest
beq .Lwindexw321
fail
.Lwindexw321:
mov.w #0xa5a5, @word_dest
rotl_w_indexl32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er1
rotl.w @(word_dest+2:32, er1.l) ; indexed word/byte
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xffffffff er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
cmp.w #0x4b4b, @word_dest
beq .Lwindexl321
fail
.Lwindexl321:
mov.w #0xa5a5, @word_dest
.endif
rotl_w_reg16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotl.w #2, r0 ; shift left arithmetic by two
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0x9696 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
test_h_gr32 0xa5a59696 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotl_w_indexb16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r0l
rotl.w #2, @(word_dest-10:16, r0.b) ; indexed word/byte
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a5a505 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
cmp.w #0x9696, @word_dest
beq .Lwindexb162
fail
.Lwindexb162:
mov.w #0xa5a5, @word_dest
rotl_w_indexw16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r0
rotl.w #2, @(word_dest-512:16, r0.w) ; indexed word/word
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a50100 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
cmp.w #0x9696, @word_dest
beq .Lwindexw162
fail
.Lwindexw162:
mov.w #0xa5a5, @word_dest
rotl_w_indexl16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er0
rotl.w #2, @(word_dest+2:16, er0.l) ; indexed word/long
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xffffffff er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
cmp.w #0x9696, @word_dest
beq .Lwindexl162
fail
.Lwindexl162:
mov.w #0xa5a5, @word_dest
rotl_w_indexb32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r1l
rotl.w #2, @(word_dest-10:32, r1.b) ; indexed word/byte
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a5a505 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
cmp.w #0x9696, @word_dest
beq .Lwindexb322
fail
.Lwindexb322:
mov.w #0xa5a5, @word_dest
rotl_w_indexw32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r1
rotl.w #2, @(word_dest-512:32, r1.w) ; indexed word/byte
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a50100 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
cmp.w #0x9696, @word_dest
beq .Lwindexw322
fail
.Lwindexw322:
mov.w #0xa5a5, @word_dest
rotl_w_indexl32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er1
rotl.w #2, @(word_dest+2:32, er1.l) ; indexed word/byte
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xffffffff er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
cmp.w #0x9696, @word_dest
beq .Lwindexl322
fail
.Lwindexl322:
mov.w #0xa5a5, @word_dest
.endif
rotl_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotl.l er0 ; shift left arithmetic by one
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1011
test_h_gr32 0x4b4b4b4b er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotl_l_indexb16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r0l
rotl.l @(long_dest-20:16, er0.b) ; indexed long/byte
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a5a505 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1011
cmp.l #0x4b4b4b4b, @long_dest
beq .Llindexb161
fail
.Llindexb161:
mov.l #0xa5a5a5a5, @long_dest
rotl_l_indexw16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r0
rotl.l @(long_dest-1024:16, er0.w) ; indexed long/word
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a50100 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1011
cmp.l #0x4b4b4b4b, @long_dest
beq .Llindexw161
fail
.Llindexw161:
mov.l #0xa5a5a5a5, @long_dest
rotl_l_indexl16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er0
rotl.l @(long_dest+4:16, er0.l) ; indexed long/long
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xffffffff er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1011
cmp.l #0x4b4b4b4b, @long_dest
beq .Llindexl161
fail
.Llindexl161:
mov.l #0xa5a5a5a5, @long_dest
rotl_l_indexb32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r1l
rotl.l @(long_dest-20:32, er1.b) ; indexed long/byte
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a5a505 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1011
cmp.l #0x4b4b4b4b, @long_dest
beq .Llindexb321
fail
.Llindexb321:
mov.l #0xa5a5a5a5, @long_dest
rotl_l_indexw32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r1
rotl.l @(long_dest-1024:32, er1.w) ; indexed long/byte
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xa5a50100 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1011
cmp.l #0x4b4b4b4b, @long_dest
beq .Llindexw321
fail
.Llindexw321:
mov.l #0xa5a5a5a5, @long_dest
rotl_l_indexl32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er1
rotl.l @(long_dest+4:32, er1.l) ; indexed long/byte
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 0xffffffff er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1011
cmp.l #0x4b4b4b4b, @long_dest
beq .Llindexl321
fail
.Llindexl321:
mov.l #0xa5a5a5a5, @long_dest
.endif
rotl_l_reg32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotl.l #2, er0 ; shift left arithmetic by two
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0110
test_h_gr32 0x96969696 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotl_l_indexb16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r0l
rotl.l #2, @(long_dest-20:16, er0.b) ; indexed long/byte
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a5a505 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0110
cmp.l #0x96969696, @long_dest
beq .Llindexb162
fail
.Llindexb162:
mov.l #0xa5a5a5a5, @long_dest
rotl_l_indexw16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r0
rotl.l #2, @(long_dest-1024:16, er0.w) ; indexed long/word
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a50100 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0110
cmp.l #0x96969696, @long_dest
beq .Llindexw162
fail
.Llindexw162:
mov.l #0xa5a5a5a5, @long_dest
rotl_l_indexl16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er0
rotl.l #2, @(long_dest+4:16, er0.l) ; indexed long/long
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xffffffff er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0110
cmp.l #0x96969696, @long_dest
beq .Llindexl162
fail
.Llindexl162:
mov.l #0xa5a5a5a5, @long_dest
rotl_l_indexb32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.b #5, r1l
rotl.l #2, @(long_dest-20:32, er1.b) ; indexed long/byte
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a5a505 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0110
cmp.l #0x96969696, @long_dest
beq .Llindexb322
fail
.Llindexb322:
mov.l #0xa5a5a5a5, @long_dest
rotl_l_indexw32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.w #256, r1
rotl.l #2, @(long_dest-1024:32, er1.w) ; indexed long/byte
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xa5a50100 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0110
cmp.l #0x96969696, @long_dest
beq .Llindexw322
fail
.Llindexw322:
mov.l #0xa5a5a5a5, @long_dest
rotl_l_indexl32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #0xffffffff, er1
rotl.l #2, @(long_dest+4:32, er1.l) ; indexed long/byte
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 0xffffffff er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0110
cmp.l #0x96969696, @long_dest
beq .Llindexl322
fail
.Llindexl322:
mov.l #0xa5a5a5a5, @long_dest
.endif
.endif
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,066 | sim/testsuite/bpf/xadd.s | # mach: bpf
# output: pass\nexit 0 (0x0)\n
;;; xadd.s
;;; Tests for BPF atomic exchange-and-add instructions in simulator
;;;
;;; The xadd instructions (XADDW, XADDDW) operate on a memory location
;;; specified in $dst + offset16, atomically adding the value in $src.
;;;
;;; In the simulator, there isn't anything else happening. The atomic
;;; instructions are identical to a non-atomic load/add/store.
.include "testutils.inc"
.text
.global main
.type main, @function
main:
mov %r1, 0x1000
mov %r2, 5
;; basic xadd w
stw [%r1+0], 10
xaddw [%r1+0], %r2
ldxw %r3, [%r1+0]
fail_ne %r3, 15
;; basic xadd dw
stdw [%r1+8], 42
xadddw [%r1+8], %r2
ldxdw %r3, [%r1+8]
fail_ne %r3, 47
;; xadd w negative value
mov %r4, -1
xaddw [%r1+0], %r4
ldxw %r3, [%r1+0]
fail_ne %r3, 14
;; xadd dw negative val
xadddw [%r1+8], %r4
ldxdw %r3, [%r1+8]
fail_ne %r3, 46
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,044 | sim/testsuite/bpf/endbe.s | # mach: bpf
# as: --EB
# ld: --EB
# sim: -E big
# output: pass\nexit 0 (0x0)\n
;;; endbe.s
;;; Tests for BPF endianness-conversion instructions in simulator
;;; running in BIG ENDIAN
;;;
;;; Both 'be' and 'le' ISAs have both endbe and endle instructions.
.include "testutils.inc"
.text
.global main
.type main, @function
main:
lddw %r1, 0x12345678deadbeef
endle %r1, 64
fail_ne %r1, 0xefbeadde78563412
endle %r1, 64
fail_ne %r1, 0x12345678deadbeef
;; `bitsize` < 64 will truncate
endle %r1, 32
fail_ne %r1, 0xefbeadde
endle %r1, 32
fail_ne %r1, 0xdeadbeef
endle %r1, 16
fail_ne %r1, 0xefbe
endle %r1, 16
fail_ne %r1, 0xbeef
;; endbe on be should be noop (except truncate)
lddw %r1, 0x12345678deadbeef
endbe %r1, 64
fail_ne %r1, 0x12345678deadbeef
endbe %r1, 32
fail_ne %r1, 0xdeadbeef
endbe %r1, 16
fail_ne %r1, 0xbeef
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,048 | sim/testsuite/bpf/jmp32.s | # mach: bpf
# output: pass\nexit 0 (0x0)\n
;;; jmp32.s
;;; Tests for eBPF JMP32 instructions in simulator
.include "testutils.inc"
.text
.global main
.type main, @function
main:
mov32 %r1, 5
mov32 %r2, 2
mov32 %r3, 7
mov32 %r4, -1
;; ja - jump absolute (unconditional)
ja 2f
1: fail
2: ;; jeq - jump eq
jeq32 %r1, 4, 1b ; no
jeq32 %r1, %r2, 1b ; no
jeq32 %r1, 5, 2f ; yes
fail
2: jeq32 %r1, %r1, 2f ; yes
fail
2: ;; jgt - jump (unsigned) greater-than
jgt32 %r1, 6, 1b ; no
jgt32 %r1, -5, 1b ; no - unsigned
jgt32 %r1, %r4, 1b ; no - unsigned
jgt32 %r1, 4, 2f ; yes
fail
2: jgt32 %r1, %r2, 2f ; yes
fail
2: ;; jge - jump (unsigned) greater-than-or-equal-to
jge32 %r1, 6, 1b ; no
jge32 %r1, 5, 2f ; yes
fail
2: jge32 %r1, %r3, 1b ; no
jge32 %r1, -5, 1b ; no - unsigned
jge32 %r1, %r2, 2f ; yes
fail
2: ;; jlt - jump (unsigned) less-than
jlt32 %r1, 5, 1b ; no
jlt32 %r1, %r2, 1b ; no
jlt32 %r4, %r1, 1b ; no - unsigned
jlt32 %r1, 6, 2f ; yes
fail
2:
jlt32 %r1, %r3, 2f ; yes
fail
2: ;; jle - jump (unsigned) less-than-or-equal-to
jle32 %r1, 4, 1b ; no
jle32 %r1, %r2, 1b ; no
jle32 %r4, %r1, 1b ; no
jle32 %r1, 5, 2f ; yes
fail
2: jle32 %r1, %r1, 2f ; yes
fail
2: ;; jset - jump "test" (AND)
jset32 %r1, 2, 1b ; no (5 & 2 = 0)
jset32 %r1, %r2, 1b ; no (same)
jset32 %r1, 4, 2f ; yes (5 & 4 != 0)
fail
2: ;; jne - jump not-equal-to
jne32 %r1, 5, 1b ; no
jne32 %r1, %r1, 1b ; no
jne32 %r1, 6, 2f ; yes
fail
2: jne32 %r1, %r4, 2f ; yes
fail
2: ;; jsgt - jump (signed) greater-than
jsgt32 %r1, %r3, 1b ; no
jsgt32 %r1, %r1, 1b ; no
jsgt32 %r1, 5, 1b ; no
jsgt32 %r1, -4, 2f ; yes
fail
2: jsgt32 %r1, %r4, 2f ; yes
fail
2: ;; jsge - jump (signed) greater-than-or-equal-to
jsge32 %r1, %r3, 1b ; no
jsge32 %r1, %r1, 2f ; yes
fail
2: jsge32 %r1, 7, 1b ; no
jsge32 %r1, -4, 2f ; yes
fail
2: jsge32 %r1, %r4, 2f ; yes
fail
2: ;; jslt - jump (signed) less-than
jslt32 %r1, 5, 1b ; no
jslt32 %r1, %r2, 1b ; no
jslt32 %r4, %r1, 2f ; yes
fail
2: jslt32 %r1, 6, 2f ; yes
fail
2: jslt32 %r1, %r3, 2f ; yes
fail
2: ;; jsle - jump (signed) less-than-or-equal-to
jsle32 %r1, 4, 1b ; no
jsle32 %r1, %r2, 1b ; no
jsle32 %r4, %r1, 2f ; yes
fail
2: jsle32 %r1, 5, 2f ; yes
fail
2: jsle32 %r1, %r3, 2f ; yes
fail
2:
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,095 | sim/testsuite/bpf/alu.s | # mach: bpf
# output: pass\nexit 0 (0x0)\n
;;; alu.s
;;; Tests for ALU64 BPF instructions in simulator
.include "testutils.inc"
.text
.global main
.type main, @function
main:
mov %r1, 0
mov %r2, -1
;; add
add %r1, 1
add %r2, -1
add %r1, %r2
fail_ne %r1, -1
;; sub
sub %r1, %r1
fail_ne %r1, 0
sub %r1, 10
sub %r2, %r1
fail_ne %r2, 8
;; mul
mul %r2, %r2 ; r2 = 64
mul %r2, 3 ; r2 = 192
mov %r1, -3
mul %r1, %r2 ; r1 = -576
mul %r2, 0
fail_ne %r1, -576
fail_ne %r2, 0
mul %r1, %r1
mul %r1, %r1
fail_ne %r1, 110075314176
;; div
div %r2, %r1
fail_ne %r2, 0
div %r1, 10000
fail_ne %r1, 11007531
div %r1, %r1
fail_ne %r1, 1
;; div is unsigned
lddw %r1, -8
div %r1, 2
fail_ne %r1, 0x7ffffffffffffffc ; sign bits NOT maintained - large pos.
;; and
lddw %r1, 0xaaaaaaaa55555555
and %r1, 0x55aaaaaa ; we still only have 32-bit imm.
fail_ne %r1, 0x0000000055000000
lddw %r2, 0x5555555a5aaaaaaa
and %r2, %r1
fail_ne %r2, 0x0000000050000000
;; or
or %r2, 0xdeadbeef
fail_ne %r2, 0xffffffffdeadbeef ; 0xdeadbeef gets sign extended
lddw %r1, 0xdead00000000beef
lddw %r2, 0x0000123456780000
or %r1, %r2
fail_ne %r1, 0xdead12345678beef
;; lsh
mov %r1, 0xdeadbeef
lsh %r1, 11
fail_ne %r1, 0xfffffef56df77800 ; because deadbeef gets sign ext.
mov %r2, 21
lsh %r1, %r2
fail_ne %r1, 0xdeadbeef00000000
;; rsh
rsh %r1, 11
fail_ne %r1, 0x001bd5b7dde00000 ; 0xdeadbeef 00000000 >> 0xb
rsh %r1, %r2
fail_ne %r1, 0x00000000deadbeef
;; arsh
arsh %r1, 8
fail_ne %r1, 0x0000000000deadbe
lsh %r1, 40 ; r1 = 0xdead be00 0000 0000
arsh %r1, %r2 ; r1 arsh (r2 == 21)
fail_ne %r1, 0xfffffef56df00000
;; mod
mov %r1, 1025
mod %r1, 16
fail_ne %r1, 1
;; mod is unsigned
mov %r1, 1025
mod %r1, -16 ; mod unsigned -> will treat as large positive
fail_ne %r1, 1025
mov %r1, -25 ; -25 is 0xff..ffe7
mov %r2, 5 ; ... which when unsigned is a large positive
mod %r1, %r2 ; ... which is not evenly divisible by 5
fail_ne %r1, 1
;; xor
mov %r1, 0
xor %r1, %r2
fail_ne %r1, 5
xor %r1, 0x7eadbeef
fail_ne %r1, 0x7eadbeea
xor %r1, %r1
fail_ne %r1, 0
;; neg
neg %r2
fail_ne %r2, -5
mov %r1, -1025
neg %r1
fail_ne %r1, 1025
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,084 | sim/testsuite/bpf/alu32.s | # mach: bpf
# output: pass\nexit 0 (0x0)\n
;; alu32.s
;; Tests for ALU(32) BPF instructions in simulator
.include "testutils.inc"
.text
.global main
.type main, @function
main:
mov32 %r1, 10 ; r1 = 10
mov32 %r2, -5 ; r2 = -5
;; add
add32 %r1, 1 ; r1 += 1 (r1 = 11)
add32 %r2, -1 ; r2 += -1 (r2 = -6)
add32 %r1, %r2 ; r1 += r2 (r1 = 11 + -6 = 5)
fail_ne32 %r1, 5
;; sub
sub32 %r1, 5 ; r1 -= 5 (r1 = 0)
sub32 %r1, -5 ; r1 -= -5 (r1 = 5)
sub32 %r1, %r2 ; r1 -= r2 (r1 = 5 - -6 = 11)
fail_ne32 %r1, 11
;; mul
mul32 %r1, 2 ; r1 *= 2 (r1 = 22)
mul32 %r1, -2 ; r1 *= -2 (r1 = -44)
mul32 %r1, %r2 ; r1 *= r2 (r1 = -44 * -6 = 264)
fail_ne32 %r1, 264
;; div
div32 %r1, 6
mov32 %r2, 11
div32 %r1, %r2
fail_ne32 %r1, 4
;; div is unsigned
mov32 %r1, -8 ; 0xfffffff8
div32 %r1, 2
fail_ne32 %r1, 0x7ffffffc ; sign bits are not preserved
;; and (bitwise)
mov32 %r1, 0xb ; r1 = (0xb = 0b1011)
mov32 %r2, 0x5 ; r2 = (0x5 = 0b0101)
and32 %r1, 0xa ; r1 &= (0xa = 0b1010) = (0b1010 = 0xa)
fail_ne32 %r1, 0xa
and32 %r1, %r2 ; r1 &= r2 = 0x0
fail_ne32 %r1, 0x0
;; or (bitwise)
or32 %r1, 0xb
or32 %r1, %r2
fail_ne32 %r1, 0xf
;; lsh (left shift)
lsh32 %r1, 4 ; r1 <<= 4 (r1 = 0xf0)
mov32 %r2, 24 ; r2 = 24
lsh32 %r1, %r2
fail_ne32 %r1, 0xf0000000
;; rsh (right logical shift)
rsh32 %r1, 2
rsh32 %r1, %r2
fail_ne32 %r1, 0x3c ; (0xf000 0000 >> 26)
;; arsh (right arithmetic shift)
arsh32 %r1, 1
or32 %r1, 0x80000000
mov32 %r2, 3
arsh32 %r1, %r2
fail_ne %r1, 0x00000000F0000003
; Note: make sure r1 is NOT sign-extended
; i.e. upper-32 bits should be untouched
;; mod
mov32 %r1, 1025
mod32 %r1, 16
fail_ne32 %r1, 1
;; mod is unsigned
mov32 %r1, 1025
mod32 %r1, -16 ; when unsigned, much larger than 1025
fail_ne32 %r1, 1025
mov32 %r1, -25 ; when unsigned, a large positive which is
mov32 %r2, 5 ; ... not evenly divisible by 5
mod32 %r1, %r2
fail_ne32 %r1, 1
;; xor
xor32 %r1, %r2
fail_ne32 %r1, 4
xor32 %r1, 0xF000000F
fail_ne %r1, 0xF000000B ; Note: check for (bad) sign-extend
xor32 %r1, %r1
fail_ne %r1, 0
;; neg
mov32 %r1, -1
mov32 %r2, 0x7fffffff
neg32 %r1
neg32 %r2
fail_ne32 %r1, 1
fail_ne %r2, 0x80000001 ; Note: check for (bad) sign-extend
neg32 %r2
fail_ne32 %r2, 0x7fffffff
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,088 | sim/testsuite/bpf/mov.s | # mach: bpf
# output: pass\nexit 0 (0x0)\n
;; mov.s
;; Tests for mov and mov32 instructions
.include "testutils.inc"
.text
.global main
.type main, @function
main:
;; some basic sanity checks
mov32 %r1, 5
fail_ne %r1, 5
mov32 %r2, %r1
fail_ne %r2, 5
mov %r2, %r1
fail_ne %r2, 5
mov %r1, -666
fail_ne %r1, -666
;; should NOT sign extend
mov32 %r1, -1
fail_ne %r1, 0x00000000ffffffff
;; should sign extend
mov %r2, -1
fail_ne %r2, 0xffffffffffffffff
mov %r3, 0x80000000
;; should NOT sign extend
mov32 %r4, %r3
fail_ne %r4, 0x0000000080000000
;; should sign extend
mov %r5, %r3
fail_ne %r5, 0xffffffff80000000
mov32 %r1, -2147483648
mov32 %r1, %r1
fail_ne32 %r1, -2147483648
;; casting shenanigans
mov %r1, %r1
fail_ne %r1, +2147483648
mov32 %r2, -1
mov %r2, %r2
fail_ne %r2, +4294967295
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,479 | sim/testsuite/bpf/ldabs.s | # mach: bpf
# sim: --skb-data-offset=0x20
# output: pass\nexit 0 (0x0)\n
;;; ldabs.s
;;; Tests for non-generic BPF load instructions in simulator.
;;; These instructions (ld{abs,ind}{b,h,w,dw}) are used to access
;;; kernel socket data from BPF programs for high performance filters.
;;;
;;; Register r6 is an implicit input holding a pointer to a struct sk_buff.
;;; Register r0 is an implicit output, holding the fetched data.
;;;
;;; e.g.
;;; ldabsw means:
;;; r0 = ntohl (*(u32 *) (((struct sk_buff *)r6)->data + imm32))
;;;
;;; ldindw means
;;; r0 = ntohl (*(u32 *) (((struct sk_buff *)r6)->data + src_reg + imm32))
.include "testutils.inc"
.text
.global main
.type main, @function
main:
;; R6 holds a pointer to a struct sk_buff, which we pretend
;; exists at 0x1000
mov %r6, 0x1000
;; We configure skb-data-offset=0x20
;; This specifies offsetof(struct sk_buff, data), where the field 'data'
;; is a pointer a data buffer, in this case at 0x2000
stw [%r6+0x20], 0x2000
;; Write the value 0x7eadbeef into memory at 0x2004
;; i.e. offset 4 within the data buffer pointed to by
;; ((struct sk_buff *)r6)->data
stw [%r6+0x1004], 0xdeadbeef
;; Now load data[4] into r0 using the ldabsw instruction
ldabsw 0x4
;; ...and compare to what we expect
fail_ne32 %r0, 0xdeadbeef
;; Repeat for a half-word (2-bytes)
sth [%r6+0x1008], 0x1234
ldabsh 0x8
fail_ne32 %r0, 0x1234
;; Repeat for a single byte
stb [%r6+0x1010], 0x5a
ldabsb 0x10
fail_ne32 %r0, 0x5a
;; Repeat for a double-word (8-byte)
;; (note: fail_ne macro uses r0, so copy to another r1 to compare)
lddw %r2, 0x1234deadbeef5678
stxdw [%r6+0x1018], %r2
ldabsdw 0x18
mov %r1, %r0
fail_ne %r1, 0x1234deadbeef5678
;; Now, we do the same for the indirect loads
mov %r7, 0x100
stw [%r6+0x1100], 0xfeedbeef
ldindw %r7, 0x0
fail_ne32 %r0, 0xfeedbeef
;; half-word
sth [%r6+0x1104], 0x6789
ldindh %r7, 0x4
fail_ne32 %r0, 0x6789
;; byte
stb [%r6+0x1108], 0x5f
ldindb %r7, 0x8
fail_ne32 %r0, 0x5f
;; double-word
lddw %r2, 0xcafe12345678d00d
stxdw [%r6+0x1110], %r2
ldinddw %r7, 0x10
mov %r1, %r0
fail_ne %r1, 0xcafe12345678d00d
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,044 | sim/testsuite/bpf/jmp.s | # mach: bpf
# output: pass\nexit 0 (0x0)\n
;;; jmp.s
;;; Tests for eBPF JMP instructions in simulator
.include "testutils.inc"
.text
.global main
.type main, @function
main:
mov %r1, 5
mov %r2, 2
mov %r3, 7
mov %r4, -1
;; ja - jump absolute (unconditional)
ja 2f
1: fail
2: ;; jeq - jump eq
jeq %r1, 4, 1b ; no
jeq %r1, %r2, 1b ; no
jeq %r1, 5, 2f ; yes
fail
2: jeq %r1, %r1, 2f ; yes
fail
2: ;; jgt - jump (unsigned) greater-than
jgt %r1, 6, 1b ; no
jgt %r1, -5, 1b ; no - unsigned
jgt %r1, %r4, 1b ; no - unsigned
jgt %r1, 4, 2f ; yes
fail
2: jgt %r1, %r2, 2f ; yes
fail
2: ;; jge - jump (unsigned) greater-than-or-equal-to
jge %r1, 6, 1b ; no
jge %r1, 5, 2f ; yes
fail
2: jge %r1, %r3, 1b ; no
jge %r1, -5, 1b ; no - unsigned
jge %r1, %r2, 2f ; yes
fail
2: ;; jlt - jump (unsigned) less-than
jlt %r1, 5, 1b ; no
jlt %r1, %r2, 1b ; no
jlt %r4, %r1, 1b ; no - unsigned
jlt %r1, 6, 2f ; yes
fail
2:
jlt %r1, %r3, 2f ; yes
fail
2: ;; jle - jump (unsigned) less-than-or-equal-to
jle %r1, 4, 1b ; no
jle %r1, %r2, 1b ; no
jle %r4, %r1, 1b ; no
jle %r1, 5, 2f ; yes
fail
2: jle %r1, %r1, 2f ; yes
fail
2: ;; jset - jump "test" (AND)
jset %r1, 2, 1b ; no (5 & 2 = 0)
jset %r1, %r2, 1b ; no (same)
jset %r1, 4, 2f ; yes (5 & 4 != 0)
fail
2: ;; jne - jump not-equal-to
jne %r1, 5, 1b ; no
jne %r1, %r1, 1b ; no
jne %r1, 6, 2f ; yes
fail
2: jne %r1, %r4, 2f ; yes
fail
2: ;; jsgt - jump (signed) greater-than
jsgt %r1, %r3, 1b ; no
jsgt %r1, %r1, 1b ; no
jsgt %r1, 5, 1b ; no
jsgt %r1, -4, 2f ; yes
fail
2: jsgt %r1, %r4, 2f ; yes
fail
2: ;; jsge - jump (signed) greater-than-or-equal-to
jsge %r1, %r3, 1b ; no
jsge %r1, %r1, 2f ; yes
fail
2: jsge %r1, 7, 1b ; no
jsge %r1, -4, 2f ; yes
fail
2: jsge %r1, %r4, 2f ; yes
fail
2: ;; jslt - jump (signed) less-than
jslt %r1, 5, 1b ; no
jslt %r1, %r2, 1b ; no
jslt %r4, %r1, 2f ; yes
fail
2: jslt %r1, 6, 2f ; yes
fail
2: jslt %r1, %r3, 2f ; yes
fail
2: ;; jsle - jump (signed) less-than-or-equal-to
jsle %r1, 4, 1b ; no
jsle %r1, %r2, 1b ; no
jsle %r4, %r1, 2f ; yes
fail
2: jsle %r1, 5, 2f ; yes
fail
2: jsle %r1, %r3, 2f ; yes
fail
2:
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,403 | sim/testsuite/bpf/mem.s | # mach: bpf
# output: pass\nexit 0 (0x0)\n
;;; mem.s
;;; Tests for BPF memory (ldx, stx, ..) instructions in simulator
.include "testutils.inc"
.text
.global main
.type main, @function
main:
lddw %r1, 0x1234deadbeef5678
mov %r2, 0x1000
;; basic store/load check
stxb [%r2+0], %r1
stxh [%r2+2], %r1
stxw [%r2+4], %r1
stxdw [%r2+8], %r1
stb [%r2+16], 0x5a
sth [%r2+18], 0xcafe
stw [%r2+20], 0xbeefface
stdw [%r2+24], 0x7eadbeef
ldxb %r1, [%r2+16]
fail_ne %r1, 0x5a
ldxh %r1, [%r2+18]
fail_ne %r1, 0xffffffffffffcafe
ldxw %r1, [%r2+20]
fail_ne %r1, 0xffffffffbeefface
ldxdw %r1, [%r2+24]
fail_ne %r1, 0x7eadbeef
ldxb %r3, [%r2+0]
fail_ne %r3, 0x78
ldxh %r3, [%r2+2]
fail_ne %r3, 0x5678
ldxw %r3, [%r2+4]
fail_ne %r3, 0xffffffffbeef5678
ldxdw %r3, [%r2+8]
fail_ne %r3, 0x1234deadbeef5678
ldxw %r4, [%r2+10]
fail_ne %r4, 0xffffffffdeadbeef
;; negative offsets
add %r2, 16
ldxh %r5, [%r2+-14]
fail_ne %r5, 0x5678
ldxw %r5, [%r2+-12]
fail_ne %r5, 0xffffffffbeef5678
ldxdw %r5, [%r2+-8]
fail_ne %r5, 0x1234deadbeef5678
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,713 | sim/testsuite/pru/dram.s | # Check that DRAM memory access works.
# mach: pru
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
.include "testutils.inc"
start
fill r20, 16
ldi r10, 0
not r10, r10
qbne F, r20, r10
qbne F, r21, r10
qbne F, r22, r10
qbne F, r23, r10
zero r20, 16
qbne F, r20, 0
qbne F, r21, 0
qbne F, r22, 0
qbne F, r23, 0
ldi r0, testarray
lbbo &r20, r0, 0, 7
qbne F, r20.b0, 0x01
qbne F, r20.b1, 0x23
qbne F, r20.b2, 0x45
qbne F, r20.b3, 0x67
qbne F, r21.b0, 0x89
qbne F, r21.b1, 0xab
qbne F, r21.b2, 0xcd
qbne F, r21.b3, 0x00 ; Should not have been loaded!
qbne F, r22, 0
qbne F, r23, 0
ldi r1, 0x11
sbbo &r1, r0, 9, 1
ldi r1, 0x11
sbbo &r1, r0, 12, 4
lbbo &r20, r0, 0, 16
qbne F, r21.b3, 0xef
qbne F, r22.b0, 0xff
qbne F, r22.b1, 0x11
qbne F, r22.b2, 0xff
qbne F, r22.b3, 0xff
qbne F, r23, 0x11
pass
F: fail
.data
testarray:
.byte 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
|
tactcomplabs/xbgas-binutils-gdb | 1,057 | sim/testsuite/pru/loop-imm.s | # Check that loop insn works.
# mach: pru
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
.include "testutils.inc"
start
ldi r25, 0
ldi r26, 0
ldi r27, 0
add r27, r27, 1
loop 1f, 10
add r25, r25, 1
add r26, r26, 2
1:
add r27, r27, 1
qbne F, r25, 10
qbne F, r26, 20
qbne F, r27, 2
pass
F: fail
|
tactcomplabs/xbgas-binutils-gdb | 1,847 | sim/testsuite/pru/mul.s | # Check that multiplication works.
# mach: pru
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
.include "testutils.inc"
start
# MUL: Test regular case
ldi r28, 1001
ldi r29, 4567
nop
xin 0, r26, 4
qbne32 2f, r26, 1001 * 4567
# MUL: Test the pipeline emulation
ldi r28, 1002
ldi r29, 1003
ldi r29, 4004
xin 0, r26, 4
qbne32 2f, r26, 1002 * 1003
xin 0, r26, 4
qbne32 2f, r26, 1002 * 4004
# MUL: Test 64-bit result
ldi32 r28, 0x12345678
ldi32 r29, 0xaabbccdd
nop
xin 0, r26, 8
qbne32 2f, r26, 0x45BE4598
qbne32 2f, r27, 0xC241C38
# MAC: Test regular case
ldi r25, 1
xout 0, r25, 1
ldi r25, 3
xout 0, r25, 1
ldi r25, 1
ldi r28, 1001
ldi r29, 2002
xout 0, r25, 1
ldi r28, 3003
ldi r29, 4004
xout 0, r25, 1
xin 0, r26, 4
qbne32 2f, r26, (1001 * 2002) + (3003 * 4004)
# MAC: Test 64-bit result
ldi r25, 3
xout 0, r25, 1
ldi r25, 1
ldi32 r28, 0x10203040
ldi32 r29, 0x50607080
xout 0, r25, 1
ldi32 r28, 0xa0b0c0d0
ldi32 r29, 0x11223344
xout 0, r25, 1
xin 0, r26, 8
qbne32 2f, r26, 0x8E30C740
qbne32 2f, r27, 0xFD156B1
jmp 1f
fail
1:
pass
2: fail
|
tactcomplabs/xbgas-binutils-gdb | 1,125 | sim/testsuite/pru/subreg.s | # Check that subregister addressing works.
# mach: pru
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
.include "testutils.inc"
start
ldi r0, 0x01ff
add r0, r0.b0, r0.b1
qbne F, r0.b0, 0x00
qbne F, r0.b1, 0x01
qbne F, r0.w2, 0x00
ldi r0, 0x01ff
add r0.b0, r0.b0, r0.b1
adc r0, r0.b1, r0.b3
qbne F, r0.b0, 0x02
qbne F, r0.b1, 0x00
qbne F, r0.w2, 0x00
pass
F: fail
|
tactcomplabs/xbgas-binutils-gdb | 1,026 | sim/testsuite/pru/dmem-zero-trap.s | # Check that DMEM zero address access can be trapped.
# mach: pru
# sim: --error-null-deref
# xerror:
# output: core: 4 byte read to unmapped address 0x0 at *\n
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
.include "testutils.inc"
start
ldi r1, 0
lbbo &r2, r1, 0, 4
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,071 | sim/testsuite/pru/loop-reg.s | # Check that loop insn works.
# mach: pru
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
.include "testutils.inc"
start
ldi r25, 0
ldi r26, 0
ldi r27, 0
ldi r28, 10
add r27, r27, 1
loop 1f, r28
add r25, r25, 1
add r26, r26, 2
1:
add r27, r27, 1
qbne F, r25, 10
qbne F, r26, 20
qbne F, r27, 2
pass
F: fail
|
tactcomplabs/xbgas-binutils-gdb | 1,290 | sim/testsuite/pru/lmbd.s | # Check that lmbd insn works.
# mach: pru
# Copyright (C) 2020-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
.include "testutils.inc"
start
ldi32 r14, 0xffffffff
ldi32 r15, 0x0
ldi32 r16, 0x40000000
ldi32 r17, 8
lmbd r0, r14, 0
qbne 2f, r0, 32
lmbd r0, r14, 1
qbne 2f, r0, 31
lmbd r0, r15, 1
qbne 2f, r0, 32
lmbd r0, r15, 0
qbne 2f, r0, 31
lmbd r0, r16, r15
qbne 2f, r0, 31
lmbd r0, r16, 1
qbne 2f, r0, 30
lmbd r0, r14.w1, 1
qbne 2f, r0, 15
lmbd r0, r17.b0, 1
qbne 2f, r0, 3
lmbd r0, r17.b0, r15
qbne 2f, r0, 7
1:
pass
2: fail
|
tactcomplabs/xbgas-binutils-gdb | 1,600 | sim/testsuite/aarch64/mla.s | # mach: aarch64
# Check the vector multiply add instruction: mla.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
m8b:
.word 0x110a0502
.word 0x4132251a
m16b:
.word 0x110a0502
.word 0x4132251a
.word 0x917a6552
.word 0x01e2c5aa
m4h:
.word 0x180a0402
.word 0x70323c1a
m8h:
.word 0x180a0402
.word 0x70323c1a
.word 0x087ab452
.word 0xe0e26caa
m2s:
.word 0x140a0402
.word 0xa46a3c1a
m4s:
.word 0x140a0402
.word 0xa46a3c1a
.word 0xb52ab452
.word 0x464b6caa
start
adrp x0, input
ldr q0, [x0, #:lo12:input]
movi v1.8b, #1
mla v1.8b, v0.8b, v0.8b
mov x1, v1.d[0]
adrp x3, m8b
ldr x4, [x3, #:lo12:m8b]
cmp x1, x4
bne .Lfailure
movi v1.16b, #1
mla v1.16b, v0.16b, v0.16b
mov x1, v1.d[0]
mov x2, v1.d[1]
adrp x3, m16b
ldr x4, [x3, #:lo12:m16b]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:m16b+8]
cmp x2, x5
bne .Lfailure
movi v1.4h, #1
mla v1.4h, v0.4h, v0.4h
mov x1, v1.d[0]
adrp x3, m4h
ldr x4, [x3, #:lo12:m4h]
cmp x1, x4
bne .Lfailure
movi v1.8h, #1
mla v1.8h, v0.8h, v0.8h
mov x1, v1.d[0]
mov x2, v1.d[1]
adrp x3, m8h
ldr x4, [x3, #:lo12:m8h]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:m8h+8]
cmp x2, x5
bne .Lfailure
movi v1.2s, #1
mla v1.2s, v0.2s, v0.2s
mov x1, v1.d[0]
adrp x3, m2s
ldr x4, [x3, #:lo12:m2s]
cmp x1, x4
bne .Lfailure
movi v1.4s, #1
mla v1.4s, v0.4s, v0.4s
mov x1, v1.d[0]
mov x2, v1.d[1]
adrp x3, m4s
ldr x4, [x3, #:lo12:m4s]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:m4s+8]
cmp x2, x5
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 2,068 | sim/testsuite/aarch64/fstur.s | # mach: aarch64
# Check the FP store unscaled offset instructions: fsturs, fsturd, fsturq.
# Check the values -1, and XXX_MAX, which tests all bits.
# Check with offsets -256 and 255, which tests all bits.
# Also tests the FP load unscaled offset instructions: fldurs, fldurd, fldurq.
.include "testutils.inc"
.data
.align 4
fm1:
.word 3212836864
fmax:
.word 2139095039
ftmp:
.word 0
dm1:
.word 0
.word -1074790400
dmax:
.word 4294967295
.word 2146435071
dtmp:
.word 0
.word 0
ldm1:
.word 0
.word 0
.word 0
.word -1073807360
ldmax:
.word 4294967295
.word 4294967295
.word 4294967295
.word 2147418111
ldtmp:
.word 0
.word 0
.word 0
.word 0
start
adrp x1, ftmp
add x1, x1, :lo12:ftmp
adrp x0, fm1
add x0, x0, :lo12:fm1
sub x5, x0, #255
sub x6, x1, #255
movi d2, #0
ldur s2, [x5, #255]
stur s2, [x6, #255]
ldr w3, [x0]
ldr w4, [x1]
cmp w3, w4
bne .Lfailure
adrp x0, fmax
add x0, x0, :lo12:fmax
add x5, x0, #256
add x6, x1, #256
movi d2, #0
ldur s2, [x5, #-256]
stur s2, [x6, #-256]
ldr w3, [x0]
ldr w4, [x1]
cmp w3, w4
bne .Lfailure
adrp x1, dtmp
add x1, x1, :lo12:dtmp
adrp x0, dm1
add x0, x0, :lo12:dm1
sub x5, x0, #255
sub x6, x1, #255
movi d2, #0
ldur d2, [x5, #255]
stur d2, [x6, #255]
ldr x3, [x0]
ldr x4, [x1]
cmp x3, x4
bne .Lfailure
adrp x0, dmax
add x0, x0, :lo12:dmax
add x5, x0, #256
add x6, x1, #256
movi d2, #0
ldur d2, [x5, #-256]
stur d2, [x6, #-256]
ldr x3, [x0]
ldr x4, [x1]
cmp x3, x4
bne .Lfailure
adrp x1, ldtmp
add x1, x1, :lo12:ldtmp
adrp x0, ldm1
add x0, x0, :lo12:ldm1
sub x5, x0, #255
sub x6, x1, #255
movi v2.2d, #0
ldur q2, [x5, #255]
stur q2, [x6, #255]
ldr x3, [x0]
ldr x4, [x1]
cmp x3, x4
bne .Lfailure
ldr x3, [x0, 8]
ldr x4, [x1, 8]
cmp x3, x4
bne .Lfailure
adrp x0, ldmax
add x0, x0, :lo12:ldmax
add x5, x0, #256
add x6, x1, #256
movi v2.2d, #0
ldur q2, [x5, #-256]
stur q2, [x6, #-256]
ldr x3, [x0]
ldr x4, [x1]
cmp x3, x4
bne .Lfailure
ldr x3, [x0, 8]
ldr x4, [x1, 8]
cmp x3, x4
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,394 | sim/testsuite/aarch64/bit.s | # mach: aarch64
# Check the bitwise vector instructions: bif, bit, bsl, eor.
.include "testutils.inc"
.data
.align 4
inputa:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
inputb:
.word 0x40302010
.word 0x80706050
.word 0xc0b0a090
.word 0x01f0e0d0
mask:
.word 0xFF00FF00
.word 0x00FF00FF
.word 0xF0F0F0F0
.word 0x0F0F0F0F
start
adrp x0, inputa
ldr q0, [x0, #:lo12:inputa]
adrp x0, inputb
ldr q1, [x0, #:lo12:inputb]
adrp x0, mask
ldr q2, [x0, #:lo12:mask]
mov v3.8b, v0.8b
bif v3.8b, v1.8b, v2.8b
addv b4, v3.8b
mov x1, v4.d[0]
cmp x1, #50
bne .Lfailure
mov v3.16b, v0.16b
bif v3.16b, v1.16b, v2.16b
addv b4, v3.16b
mov x1, v4.d[0]
cmp x1, #252
bne .Lfailure
mov v3.8b, v0.8b
bit v3.8b, v1.8b, v2.8b
addv b4, v3.8b
mov x1, v4.d[0]
cmp x1, #50
bne .Lfailure
mov v3.16b, v0.16b
bit v3.16b, v1.16b, v2.16b
addv b4, v3.16b
mov x1, v4.d[0]
cmp x1, #13
bne .Lfailure
mov v3.8b, v2.8b
bsl v3.8b, v0.8b, v1.8b
addv b4, v3.8b
mov x1, v4.d[0]
cmp x1, #50
bne .Lfailure
mov v3.16b, v2.16b
bsl v3.16b, v0.16b, v1.16b
addv b4, v3.16b
mov x1, v4.d[0]
cmp x1, #252
bne .Lfailure
mov v3.8b, v0.8b
eor v3.8b, v1.8b, v2.8b
addv b4, v3.8b
mov x1, v4.d[0]
cmp x1, #252
bne .Lfailure
mov v3.16b, v0.16b
eor v3.16b, v1.16b, v2.16b
addv b4, v3.16b
mov x1, v4.d[0]
cmp x1, #247
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,212 | sim/testsuite/aarch64/xtn.s | # mach: aarch64
# Check the extract narrow instructions: xtn, xtn2.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
input2:
.word 0x14131211
.word 0x18171615
.word 0x1c1b1a19
.word 0x201f1e1d
x16b:
.word 0x07050301
.word 0x0f0d0b09
.word 0x17151311
.word 0x1f1d1b19
x8h:
.word 0x06050201
.word 0x0e0d0a09
.word 0x16151211
.word 0x1e1d1a19
x4s:
.word 0x04030201
.word 0x0c0b0a09
.word 0x14131211
.word 0x1c1b1a19
start
adrp x0, input
ldr q0, [x0, #:lo12:input]
adrp x0, input2
ldr q1, [x0, #:lo12:input2]
xtn v2.8b, v0.8h
xtn2 v2.16b, v1.8h
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, x16b
ldr x4, [x3, #:lo12:x16b]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:x16b+8]
cmp x2, x5
bne .Lfailure
xtn v2.4h, v0.4s
xtn2 v2.8h, v1.4s
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, x8h
ldr x4, [x3, #:lo12:x8h]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:x8h+8]
cmp x2, x5
bne .Lfailure
xtn v2.2s, v0.2d
xtn2 v2.4s, v1.2d
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, x4s
ldr x4, [x3, #:lo12:x4s]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:x4s+8]
cmp x2, x5
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 2,672 | sim/testsuite/aarch64/stn_multiple.s | # mach: aarch64
# Check the store multiple structure instructions: st1, st2, st3, st4.
# Check the addressing modes: no offset, post-index immediate offset,
# post-index register offset.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
.word 0xfcfdfeff
.word 0xf8f9fafb
.word 0xf4f5f6f7
.word 0xf0f1f2f3
output:
.zero 64
start
adrp x0, input
add x0, x0, :lo12:input
adrp x1, output
add x1, x1, :lo12:output
mov x2, x0
ldr q0, [x2], 16
ldr q1, [x2]
mov x2, x0
ldr q2, [x2], 16
ldr q3, [x2]
mov x2, x1
mov x3, #16
st1 {v0.16b}, [x2], 16
st1 {v1.8h}, [x2], x3
mov x2, x1
ldr q4, [x2], 16
ldr q5, [x2]
addv b4, v4.16b
addv b5, v5.16b
mov x4, v4.d[0]
cmp x4, #136
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #120
bne .Lfailure
mov x2, x1
mov x3, #16
st2 {v0.8b, v1.8b}, [x2], 16
st2 {v2.4h, v3.4h}, [x2], x3
mov x2, x1
ldr q4, [x2], 16
ldr q5, [x2]
addv b4, v4.16b
addv b5, v5.16b
mov x4, v4.d[0]
cmp x4, #0
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #0
bne .Lfailure
mov x2, x1
st3 {v0.4s, v1.4s, v2.4s}, [x2]
ldr q4, [x2], 16
ldr q5, [x2], 16
ldr q6, [x2]
addv b4, v4.16b
addv b5, v5.16b
addv b6, v6.16b
mov x4, v4.d[0]
cmp x4, #36
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #0
bne .Lfailure
mov x6, v6.d[0]
cmp x6, #100
bne .Lfailure
mov x2, x1
st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2]
ldr q4, [x2], 16
ldr q5, [x2], 16
ldr q6, [x2], 16
ldr q7, [x2]
addv b4, v4.16b
addv b5, v5.16b
addv b6, v6.16b
addv b7, v7.16b
mov x4, v4.d[0]
cmp x4, #0
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #0
bne .Lfailure
mov x6, v6.d[0]
cmp x6, #0
bne .Lfailure
mov x7, v7.d[0]
cmp x7, #0
bne .Lfailure
pass
mov x2, x1
st1 {v0.2s, v1.2s}, [x2], 16
st1 {v2.1d, v3.1d}, [x2]
mov x2, x1
ldr q4, [x2], 16
ldr q5, [x2]
addv b4, v4.16b
addv b5, v5.16b
mov x4, v4.d[0]
cmp x4, #0
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #0
bne .Lfailure
mov x2, x1
st1 {v0.2d, v1.2d, v2.2d}, [x2]
mov x2, x1
ldr q4, [x2], 16
ldr q5, [x2], 16
ldr q6, [x2]
addv b4, v4.16b
addv b5, v5.16b
addv b6, v6.16b
mov x4, v4.d[0]
cmp x4, #136
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #120
bne .Lfailure
mov x6, v6.d[0]
cmp x6, #136
bne .Lfailure
mov x2, x1
st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2]
mov x2, x1
ldr q4, [x2], 16
ldr q5, [x2], 16
ldr q6, [x2], 16
ldr q7, [x2]
addv b4, v4.16b
addv b5, v5.16b
addv b6, v6.16b
addv b7, v7.16b
mov x4, v4.d[0]
cmp x4, #136
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #120
bne .Lfailure
mov x6, v6.d[0]
cmp x6, #136
bne .Lfailure
mov x7, v7.d[0]
cmp x7, #120
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,512 | sim/testsuite/aarch64/mul.s | # mach: aarch64
# Check the non-widening multiply vector instruction: mul.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
m8b:
.word 0x10090401
.word 0x40312419
m16b:
.word 0x10090401
.word 0x40312419
.word 0x90796451
.word 0x00e1c4a9
m4h:
.word 0x18090401
.word 0x70313c19
m8h:
.word 0x18090401
.word 0x70313c19
.word 0x0879b451
.word 0xe0e16ca9
m2s:
.word 0x140a0401
.word 0xa46a3c19
m4s:
.word 0x140a0401
.word 0xa46a3c19
.word 0xb52ab451
.word 0x464b6ca9
start
adrp x0, input
ldr q0, [x0, #:lo12:input]
mul v1.8b, v0.8b, v0.8b
mov x1, v1.d[0]
adrp x3, m8b
ldr x4, [x0, #:lo12:m8b]
cmp x1, x4
bne .Lfailure
mul v1.16b, v0.16b, v0.16b
mov x1, v1.d[0]
mov x2, v1.d[1]
adrp x3, m16b
ldr x4, [x0, #:lo12:m16b]
cmp x1, x4
bne .Lfailure
ldr x5, [x0, #:lo12:m16b+8]
cmp x2, x5
bne .Lfailure
mul v1.4h, v0.4h, v0.4h
mov x1, v1.d[0]
adrp x3, m4h
ldr x4, [x0, #:lo12:m4h]
cmp x1, x4
bne .Lfailure
mul v1.8h, v0.8h, v0.8h
mov x1, v1.d[0]
mov x2, v1.d[1]
adrp x3, m8h
ldr x4, [x0, #:lo12:m8h]
cmp x1, x4
bne .Lfailure
ldr x5, [x0, #:lo12:m8h+8]
cmp x2, x5
bne .Lfailure
mul v1.2s, v0.2s, v0.2s
mov x1, v1.d[0]
adrp x3, m2s
ldr x4, [x0, #:lo12:m2s]
cmp x1, x4
bne .Lfailure
mul v1.4s, v0.4s, v0.4s
mov x1, v1.d[0]
mov x2, v1.d[1]
adrp x3, m4s
ldr x4, [x0, #:lo12:m4s]
cmp x1, x4
bne .Lfailure
ldr x5, [x0, #:lo12:m4s+8]
cmp x2, x5
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,540 | sim/testsuite/aarch64/xtl.s | #mach: aarch64
# Check the extend long instructions: sxtl, sxtl2, uxtl, uxtl2.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0xfcfdfeff
.word 0xf8f9fafb
start
adrp x0, input
ldr q0, [x0, #:lo12:input]
uxtl v1.8h, v0.8b
uxtl2 v2.8h, v0.16b
addv h3, v1.8h
addv h4, v2.8h
mov x1, v3.d[0]
mov x2, v4.d[0]
cmp x1, #36
bne .Lfailure
cmp x2, #2012
bne .Lfailure
uxtl v1.4s, v0.4h
uxtl2 v2.4s, v0.8h
addv s3, v1.4s
addv s4, v2.4s
mov x1, v3.d[0]
mov x2, v4.d[0]
mov x3, #5136
cmp x1, x3
bne .Lfailure
mov x4, #0xeff0
movk x4, 0x3, lsl #16
cmp x2, x4
bne .Lfailure
uxtl v1.2d, v0.2s
uxtl2 v2.2d, v0.4s
addv s3, v1.4s
addv s4, v2.4s
mov x1, v3.d[0]
mov x2, v4.d[0]
mov x3, #0x0806
movk x3, #0x0c0a, lsl #16
cmp x1, x3
bne .Lfailure
mov x4, #0xf9fa
movk x4, #0xf5f7, lsl #16
cmp x2, x4
bne .Lfailure
sxtl v1.8h, v0.8b
sxtl2 v2.8h, v0.16b
addv h3, v1.8h
addv h4, v2.8h
mov x1, v3.d[0]
mov x2, v4.d[0]
cmp x1, #36
bne .Lfailure
mov x3, #0xffdc
cmp x2, x3
bne .Lfailure
sxtl v1.4s, v0.4h
sxtl2 v2.4s, v0.8h
addv s3, v1.4s
addv s4, v2.4s
mov x1, v3.d[0]
mov x2, v4.d[0]
mov x3, #5136
cmp x1, x3
bne .Lfailure
mov x4, #0xeff0
movk x4, 0xffff, lsl #16
bne .Lfailure
sxtl v1.2d, v0.2s
sxtl2 v2.2d, v0.4s
addv s3, v1.4s
addv s4, v2.4s
mov x1, v3.d[0]
mov x2, v4.d[0]
mov x3, #0x0806
movk x3, #0x0c0a, lsl #16
cmp x1, x3
bne .Lfailure
mov x4, #0xf9f8
movk x4, #0xf5f7, lsl #16
cmp x2, x4
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,341 | sim/testsuite/aarch64/sumov.s | # mach: aarch64
# Check the mov from asimd to general reg instructions: smov, umov.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0xf4f3f2f1
.word 0xf8f7f6f5
start
adrp x0, input
ldr q0, [x0, #:lo12:input]
smov w0, v0.b[0]
smov w3, v0.b[12]
cmp w0, #1
bne .Lfailure
cmp w3, #-11
bne .Lfailure
smov x0, v0.b[1]
smov x3, v0.b[13]
cmp x0, #2
bne .Lfailure
cmp x3, #-10
bne .Lfailure
smov w0, v0.h[0]
smov w1, v0.h[4]
cmp w0, #0x0201
bne .Lfailure
cmp w1, #-3343
bne .Lfailure
smov x0, v0.h[1]
smov x1, v0.h[5]
cmp x0, #0x0403
bne .Lfailure
cmp x1, #-2829
bne .Lfailure
smov x0, v0.s[1]
smov x1, v0.s[3]
mov x2, #0x0605
movk x2, #0x0807, lsl #16
cmp x0, x2
bne .Lfailure
mov w3, #0xf6f5
movk w3, #0xf8f7, lsl #16
sxtw x3, w3
cmp x1, x3
bne .Lfailure
umov w0, v0.b[0]
umov w3, v0.b[12]
cmp w0, #1
bne .Lfailure
cmp w3, #0xf5
bne .Lfailure
umov w0, v0.h[0]
umov w1, v0.h[4]
cmp w0, #0x0201
bne .Lfailure
mov w2, #0xf2f1
cmp w1, w2
bne .Lfailure
umov w0, v0.s[0]
umov w1, v0.s[2]
mov w2, #0x0201
movk w2, #0x0403, lsl #16
cmp w0, w2
bne .Lfailure
mov w3, #0xf2f1
movk w3, #0xf4f3, lsl #16
cmp w1, w3
bne .Lfailure
umov x0, v0.d[0]
adrp x1, input
ldr x2, [x1, #:lo12:input]
cmp x0, x2
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,619 | sim/testsuite/aarch64/cmtst.s | # mach: aarch64
# Check the vector compare bitwise test instruction: cmtst.
.include "testutils.inc"
.data
.align 4
inputb:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
inputh:
.word 0x00020001
.word 0x00040003
.word 0x00060005
.word 0x00800007
inputs:
.word 0x00000001
.word 0x00000002
.word 0x00000003
.word 0x00000004
inputd:
.word 0x00000001
.word 0x00000000
.word 0x00000002
.word 0x00000000
inputd2:
.word 0x00000003
.word 0x00000000
.word 0x00000004
.word 0x00000000
start
adrp x0, inputb
ldr q0, [x0, #:lo12:inputb]
rev64 v1.16b, v0.16b
cmtst v2.8b, v0.8b, v1.8b
addv b3, v2.8b
mov x1, v3.d[0]
cmp x1, #0xfa
bne .Lfailure
cmtst v2.16b, v0.16b, v1.16b
addv b3, v2.16b
mov x1, v3.d[0]
cmp x1, #0xf4
bne .Lfailure
adrp x0, inputh
ldr q0, [x0, #:lo12:inputh]
rev64 v1.8h, v0.8h
cmtst v2.4h, v0.4h, v1.4h
addv h3, v2.4h
mov x1, v3.d[0]
mov x2, #0xfffe
cmp x1, x2
bne .Lfailure
cmtst v2.8h, v0.8h, v1.8h
addv h3, v2.8h
mov x1, v3.d[0]
mov x2, #0xfffc
cmp x1, x2
bne .Lfailure
adrp x0, inputs
ldr q0, [x0, #:lo12:inputs]
mov v1.d[0], v0.d[1]
mov v1.d[1], v0.d[0]
rev64 v1.4s, v1.4s
cmtst v2.2s, v0.2s, v1.2s
mov x1, v2.d[0]
mov x2, #0xffffffff00000000
cmp x1, x2
bne .Lfailure
cmtst v2.4s, v0.4s, v1.4s
addv s3, v2.4s
mov x1, v3.d[0]
mov x2, #0xfffffffe
cmp x1, x2
bne .Lfailure
adrp x0, inputd
ldr q0, [x0, #:lo12:inputd]
adrp x0, inputd2
ldr q1, [x0, #:lo12:inputd2]
cmtst v2.2d, v0.2d, v1.2d
mov x1, v2.d[0]
cmp x1, #-1
bne .Lfailure
mov x2, v2.d[1]
cmp x2, #0
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 2,162 | sim/testsuite/aarch64/stn_single.s | # mach: aarch64
# Check the store single 1-element structure to one lane instructions:
# st1, st2, st3, st4.
# Check the addressing modes: no offset, post-index immediate offset,
# post-index register offset.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
.word 0x14131211
.word 0x18171615
.word 0x1c1b1a19
.word 0x201f1e1d
output:
.zero 64
start
adrp x0, input
add x0, x0, :lo12:input
adrp x1, output
add x1, x1, :lo12:output
mov x2, x0
ldr q0, [x2], 16
ldr q1, [x2]
mov x2, x0
ldr q2, [x2], 16
ldr q3, [x2]
mov x2, x1
mov x3, #1
mov x4, #4
st1 {v0.b}[0], [x2], 1
st1 {v0.b}[1], [x2], x3
st1 {v0.h}[1], [x2], 2
st1 {v0.s}[1], [x2], x4
st1 {v0.d}[1], [x2]
ldr q4, [x1]
addv b4, v4.16b
mov x5, v4.d[0]
cmp x5, #136
bne .Lfailure
mov x2, x1
mov x3, #16
mov x4, #4
st2 {v0.d, v1.d}[0], [x2], x3
st2 {v0.s, v1.s}[2], [x2], 8
st2 {v0.h, v1.h}[6], [x2], x4
st2 {v0.b, v1.b}[14], [x2], 2
st2 {v0.b, v1.b}[15], [x2]
mov x2, x1
ldr q4, [x2], 16
ldr q5, [x2]
addv b4, v4.16b
addv b5, v5.16b
mov x5, v4.d[0]
mov x6, v5.d[0]
cmp x5, #200
bne .Lfailure
cmp x6, #72
bne .Lfailure
mov x2, x1
mov x3, #12
st3 {v0.s, v1.s, v2.s}[0], [x2], 12
st3 {v0.s, v1.s, v2.s}[1], [x2], x3
st3 {v0.s, v1.s, v2.s}[2], [x2], 12
st3 {v0.s, v1.s, v2.s}[3], [x2]
mov x2, x1
ldr q4, [x2], 16
ldr q5, [x2], 16
ldr q6, [x2]
addv b4, v4.16b
addv b5, v5.16b
addv b6, v6.16b
mov x4, v4.d[0]
mov x5, v5.d[0]
mov x6, v6.d[0]
cmp x4, #120
bne .Lfailure
cmp x5, #8
bne .Lfailure
cmp x6, #24
bne .Lfailure
mov x2, x1
mov x3, #16
st4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16
st4 {v0.s, v1.s, v2.s, v3.s}[1], [x2], x3
st4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], 16
st4 {v0.s, v1.s, v2.s, v3.s}[3], [x2]
mov x2, x1
ldr q4, [x2], 16
ldr q5, [x2], 16
ldr q6, [x2], 16
ldr q7, [x2]
addv b4, v4.16b
addv b5, v5.16b
addv b6, v6.16b
addv b7, v7.16b
mov x4, v4.d[0]
mov x5, v5.d[0]
mov x6, v6.d[0]
mov x7, v7.d[0]
cmp x4, #168
bne .Lfailure
cmp x5, #232
bne .Lfailure
cmp x6, #40
bne .Lfailure
cmp x7, #104
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 3,460 | sim/testsuite/aarch64/fcvtz.s | # mach: aarch64
# Check the FP convert to int round toward zero instructions: fcvtszs32,
# fcvtszs, fcvtszd32, fcvtszd, fcvtzu.
# For 32-bit signed convert, test values -1.5, INT_MAX, and INT_MIN.
# For 64-bit signed convert, test values -1.5, LONG_MAX, and LONG_MIN.
# For 32-bit unsigned convert, test values 1.5, INT_MAX, and UINT_MAX.
# For 64-bit unsigned convert, test values 1.5, LONG_MAX, and ULONG_MAX.
.data
.align 4
fm1p5:
.word 3217031168
fimax:
.word 1325400064
fimin:
.word 3472883712
flmax:
.word 1593835520
flmin:
.word 3741319168
f1p5:
.word 1069547520
fuimax:
.word 1333788672
fulmax:
.word 1602224128
dm1p5:
.word 0
.word -1074266112
dimax:
.word 4290772992
.word 1105199103
dimin:
.word 0
.word -1042284544
dlmax:
.word 0
.word 1138753536
dlmin:
.word 0
.word -1008730112
d1p5:
.word 0
.word 1073217536
duimax:
.word 4292870144
.word 1106247679
dulmax:
.word 0
.word 1139802112
.include "testutils.inc"
start
adrp x0, fm1p5
ldr s0, [x0, #:lo12:fm1p5]
fcvtzs w1, s0
cmp w1, #-1
bne .Lfailure
adrp x0, fimax
ldr s0, [x0, #:lo12:fimax]
fcvtzs w1, s0
mov w2, #0x7fffffff
cmp w1, w2
bne .Lfailure
adrp x0, fimin
ldr s0, [x0, #:lo12:fimin]
fcvtzs w1, s0
mov w2, #0x80000000
cmp w1, w2
bne .Lfailure
adrp x0, fm1p5
ldr s0, [x0, #:lo12:fm1p5]
fcvtzs x1, s0
cmp x1, #-1
bne .Lfailure
adrp x0, flmax
ldr s0, [x0, #:lo12:flmax]
fcvtzs x1, s0
mov x2, #0x7fffffffffffffff
cmp x1, x2
bne .Lfailure
adrp x0, flmin
ldr s0, [x0, #:lo12:flmin]
fcvtzs x1, s0
mov x2, #0x8000000000000000
cmp x1, x2
bne .Lfailure
adrp x0, dm1p5
ldr d0, [x0, #:lo12:dm1p5]
fcvtzs w1, d0
cmp w1, #-1
bne .Lfailure
adrp x0, dimax
ldr d0, [x0, #:lo12:dimax]
fcvtzs w1, d0
mov w2, #0x7fffffff
cmp w1, w2
bne .Lfailure
adrp x0, dimin
ldr d0, [x0, #:lo12:dimin]
fcvtzs w1, d0
mov w2, #0x80000000
cmp w1, w2
bne .Lfailure
adrp x0, dm1p5
ldr d0, [x0, #:lo12:dm1p5]
fcvtzs x1, d0
cmp x1, #-1
bne .Lfailure
adrp x0, dlmax
ldr d0, [x0, #:lo12:dlmax]
fcvtzs x1, d0
mov x2, #0x7fffffffffffffff
cmp x1, x2
bne .Lfailure
adrp x0, dlmin
ldr d0, [x0, #:lo12:dlmin]
fcvtzs x1, d0
mov x2, #0x8000000000000000
cmp x1, x2
bne .Lfailure
adrp x0, f1p5
ldr s0, [x0, #:lo12:f1p5]
fcvtzu w1, s0
cmp w1, #1
bne .Lfailure
adrp x0, fimax
ldr s0, [x0, #:lo12:fimax]
fcvtzu w1, s0
mov w2, #0x80000000
cmp w1, w2
bne .Lfailure
adrp x0, fuimax
ldr s0, [x0, #:lo12:fuimax]
fcvtzu w1, s0
mov w2, #0xffffffff
cmp w1, w2
bne .Lfailure
adrp x0, f1p5
ldr s0, [x0, #:lo12:f1p5]
fcvtzu x1, s0
cmp x1, #1
bne .Lfailure
adrp x0, flmax
ldr s0, [x0, #:lo12:flmax]
fcvtzu x1, s0
mov x2, #0x8000000000000000
cmp x1, x2
bne .Lfailure
adrp x0, fulmax
ldr s0, [x0, #:lo12:fulmax]
fcvtzu x1, s0
mov x2, #0xffffffffffffffff
cmp x1, x2
bne .Lfailure
adrp x0, d1p5
ldr d0, [x0, #:lo12:d1p5]
fcvtzu w1, d0
cmp w1, #1
bne .Lfailure
adrp x0, dimax
ldr d0, [x0, #:lo12:dimax]
fcvtzu w1, d0
mov w2, #0x7fffffff
cmp w1, w2
bne .Lfailure
adrp x0, duimax
ldr d0, [x0, #:lo12:duimax]
fcvtzu w1, d0
mov w2, #0xffffffff
cmp w1, w2
bne .Lfailure
adrp x0, d1p5
ldr d0, [x0, #:lo12:d1p5]
fcvtzu x1, d0
cmp x1, #1
bne .Lfailure
adrp x0, dlmax
ldr d0, [x0, #:lo12:dlmax]
fcvtzu x1, d0
mov x2, #0x8000000000000000
cmp x1, x2
bne .Lfailure
adrp x0, dulmax
ldr d0, [x0, #:lo12:dulmax]
fcvtzu x1, d0
mov x2, #0xffffffffffffffff
cmp x1, x2
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,605 | sim/testsuite/aarch64/mls.s | # mach: aarch64
# Check the vector multiply subtract instruction: mls.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
m8b:
.word 0xf1f8fd00
.word 0xc1d0dde8
m16b:
.word 0xf1f8fd00
.word 0xc1d0dde8
.word 0x71889db0
.word 0x01203d58
m4h:
.word 0xe7f8fc00
.word 0x8fd0c3e8
m8h:
.word 0xe7f8fc00
.word 0x8fd0c3e8
.word 0xf7884bb0
.word 0x1f209358
m2s:
.word 0xebf5fc00
.word 0x5b95c3e8
m4s:
.word 0xebf5fc00
.word 0x5b95c3e8
.word 0x4ad54bb0
.word 0xb9b49358
start
adrp x0, input
ldr q0, [x0, #:lo12:input]
movi v1.8b, #1
mls v1.8b, v0.8b, v0.8b
mov x1, v1.d[0]
adrp x3, m8b
ldr x4, [x3, #:lo12:m8b]
cmp x1, x4
bne .Lfailure
movi v1.16b, #1
mls v1.16b, v0.16b, v0.16b
mov x1, v1.d[0]
mov x2, v1.d[1]
adrp x3, m16b
ldr x4, [x3, #:lo12:m16b]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:m16b+8]
cmp x2, x5
bne .Lfailure
movi v1.4h, #1
mls v1.4h, v0.4h, v0.4h
mov x1, v1.d[0]
adrp x3, m4h
ldr x4, [x3, #:lo12:m4h]
cmp x1, x4
bne .Lfailure
movi v1.8h, #1
mls v1.8h, v0.8h, v0.8h
mov x1, v1.d[0]
mov x2, v1.d[1]
adrp x3, m8h
ldr x4, [x3, #:lo12:m8h]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:m8h+8]
cmp x2, x5
bne .Lfailure
movi v1.2s, #1
mls v1.2s, v0.2s, v0.2s
mov x1, v1.d[0]
adrp x3, m2s
ldr x4, [x3, #:lo12:m2s]
cmp x1, x4
bne .Lfailure
movi v1.4s, #1
mls v1.4s, v0.4s, v0.4s
mov x1, v1.d[0]
mov x2, v1.d[1]
adrp x3, m4s
ldr x4, [x3, #:lo12:m4s]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:m4s+8]
cmp x2, x5
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 2,948 | sim/testsuite/aarch64/ldnr.s | # mach: aarch64
# Check the load single 1-element structure and replicate to all lanes insns:
# ld1r, ld2r, ld3r, ld4r.
# Check the addressing modes: no offset, post-index immediate offset,
# post-index register offset.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
input2:
.word 0x00000001
.word 0x00000002
.word 0x00000003
.word 0x00000004
.word 0x00000005
.word 0x00000006
.word 0x00000007
.word 0x00000008
.word 0x00000009
.word 0x0000000a
.word 0x0000000b
.word 0x0000000c
start
adrp x0, input
add x0, x0, :lo12:input
adrp x1, input2
add x1, x1, :lo12:input2
mov x2, x0
mov x3, #1
ld1r {v0.8b}, [x2], 1
ld1r {v1.16b}, [x2], x3
ld1r {v2.4h}, [x2], 2
ld1r {v3.8h}, [x2]
addv b0, v0.8b
addv b1, v1.16b
addv b2, v2.8b
addv b3, v3.16b
mov x2, v0.d[0]
mov x3, v1.d[0]
mov x4, v2.d[0]
mov x5, v3.d[0]
cmp x2, #8
bne .Lfailure
cmp x3, #32
bne .Lfailure
cmp x4, #28
bne .Lfailure
cmp x5, #88
bne .Lfailure
mov x2, x1
mov x3, #8
ld2r {v0.2s, v1.2s}, [x2], 8
ld2r {v2.4s, v3.4s}, [x2], x3
ld2r {v4.1d, v5.1d}, [x2], 16
ld2r {v6.2d, v7.2d}, [x2]
addp v0.2s, v0.2s, v1.2s
addv s2, v2.4s
addv s3, v3.4s
addp v4.2s, v4.2s, v5.2s
addv s6, v6.4s
addv s7, v7.4s
mov w2, v0.s[0]
mov w3, v0.s[1]
mov x4, v2.d[0]
mov x5, v3.d[0]
mov w6, v4.s[0]
mov w7, v4.s[1]
mov x8, v6.d[0]
mov x9, v7.d[0]
cmp w2, #2
bne .Lfailure
cmp w3, #4
bne .Lfailure
cmp x4, #12
bne .Lfailure
cmp x5, #16
bne .Lfailure
cmp w6, #11
bne .Lfailure
cmp w7, #15
bne .Lfailure
cmp x8, #38
bne .Lfailure
cmp x9, #46
bne .Lfailure
mov x2, x0
mov x3, #3
ld3r {v0.8b, v1.8b, v2.8b}, [x2], 3
ld3r {v3.8b, v4.8b, v5.8b}, [x2], x3
ld3r {v6.8b, v7.8b, v8.8b}, [x2]
addv b0, v0.8b
addv b1, v1.8b
addv b2, v2.8b
addv b3, v3.8b
addv b4, v4.8b
addv b5, v5.8b
addv b6, v6.8b
addv b7, v7.8b
addv b8, v8.8b
addv b9, v9.8b
mov x2, v0.d[0]
mov x3, v1.d[0]
mov x4, v2.d[0]
mov x5, v3.d[0]
mov x6, v4.d[0]
mov x7, v5.d[0]
mov x8, v6.d[0]
mov x9, v7.d[0]
mov x10, v8.d[0]
cmp x2, #8
bne .Lfailure
cmp x3, #16
bne .Lfailure
cmp x4, #24
bne .Lfailure
cmp x5, #32
bne .Lfailure
cmp x6, #40
bne .Lfailure
cmp x7, #48
bne .Lfailure
cmp x8, #56
bne .Lfailure
cmp x9, #64
bne .Lfailure
cmp x10, #72
bne .Lfailure
mov x2, x1
ld4r {v0.4s, v1.4s, v2.4s, v3.4s}, [x2], 16
ld4r {v4.4s, v5.4s, v6.4s, v7.4s}, [x2]
addv s0, v0.4s
addv s1, v1.4s
addv s2, v2.4s
addv s3, v3.4s
addv s4, v4.4s
addv s5, v5.4s
addv s6, v6.4s
addv s7, v7.4s
mov x2, v0.d[0]
mov x3, v1.d[0]
mov x4, v2.d[0]
mov x5, v3.d[0]
mov x6, v4.d[0]
mov x7, v5.d[0]
mov x8, v6.d[0]
mov x9, v7.d[0]
cmp x2, #4
bne .Lfailure
cmp x3, #8
bne .Lfailure
cmp x4, #12
bne .Lfailure
cmp x5, #16
bne .Lfailure
cmp x6, #20
bne .Lfailure
cmp x7, #24
bne .Lfailure
cmp x8, #28
bne .Lfailure
cmp x9, #32
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,510 | sim/testsuite/aarch64/adds.s | # mach: aarch64
# Check the basic integer compare instructions: adds, adds64, subs, subs64.
# For add, check value pairs 1 and -1 (Z), -1 and -1 (N), 2 and -1 (C),
# and MIN_INT and -1 (V),
# Also check -2 and 1 (not C).
# For sub, negate the second value.
.include "testutils.inc"
start
mov w0, #1
mov w1, #-1
adds w2, w0, w1
bne .Lfailure
mov w0, #-1
mov w1, #-1
adds w2, w0, w1
bpl .Lfailure
mov w0, #2
mov w1, #-1
adds w2, w0, w1
bcc .Lfailure
mov w0, #0x80000000
mov w1, #-1
adds w2, w0, w1
bvc .Lfailure
mov w0, #-2
mov w1, #1
adds w2, w0, w1
bcs .Lfailure
mov x0, #1
mov x1, #-1
adds x2, x0, x1
bne .Lfailure
mov x0, #-1
mov x1, #-1
adds x2, x0, x1
bpl .Lfailure
mov x0, #2
mov x1, #-1
adds x2, x0, x1
bcc .Lfailure
mov x0, #0x8000000000000000
mov x1, #-1
adds x2, x0, x1
bvc .Lfailure
mov x0, #-2
mov x1, #1
adds x2, x0, x1
bcs .Lfailure
mov w0, #1
mov w1, #1
subs w2, w0, w1
bne .Lfailure
mov w0, #-1
mov w1, #1
subs w2, w0, w1
bpl .Lfailure
mov w0, #2
mov w1, #1
subs w2, w0, w1
bcc .Lfailure
mov w0, #0x80000000
mov w1, #1
subs w2, w0, w1
bvc .Lfailure
mov w0, #-2
mov w1, #-1
subs w2, w0, w1
bcs .Lfailure
mov x0, #1
mov x1, #1
subs x2, x0, x1
bne .Lfailure
mov x0, #-1
mov x1, #1
subs x2, x0, x1
bpl .Lfailure
mov x0, #2
mov x1, #1
subs x2, x0, x1
bcc .Lfailure
mov x0, #0x8000000000000000
mov x1, #1
subs x2, x0, x1
bvc .Lfailure
mov x0, #-2
mov x1, #-1
subs x2, x0, x1
bcs .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 3,445 | sim/testsuite/aarch64/uzp.s | # mach: aarch64
# Check the unzip instructions: uzp1, uzp2.
.include "testutils.inc"
.data
.align 4
input1:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
input2:
.word 0x14131211
.word 0x18171615
.word 0x1c1b1a19
.word 0x201f1e1d
zl8b:
.word 0x07050301
.word 0x17151311
zu8b:
.word 0x08060402
.word 0x18161412
zl16b:
.word 0x07050301
.word 0x0f0d0b09
.word 0x17151311
.word 0x1f1d1b19
zu16b:
.word 0x08060402
.word 0x100e0c0a
.word 0x18161412
.word 0x201e1c1a
zl4h:
.word 0x06050201
.word 0x16151211
zu4h:
.word 0x08070403
.word 0x18171413
zl8h:
.word 0x06050201
.word 0x0e0d0a09
.word 0x16151211
.word 0x1e1d1a19
zu8h:
.word 0x08070403
.word 0x100f0c0b
.word 0x18171413
.word 0x201f1c1b
zl2s:
.word 0x04030201
.word 0x14131211
zu2s:
.word 0x08070605
.word 0x18171615
zl4s:
.word 0x04030201
.word 0x0c0b0a09
.word 0x14131211
.word 0x1c1b1a19
zu4s:
.word 0x08070605
.word 0x100f0e0d
.word 0x18171615
.word 0x201f1e1d
zl2d:
.word 0x04030201
.word 0x08070605
.word 0x14131211
.word 0x18171615
zu2d:
.word 0x0c0b0a09
.word 0x100f0e0d
.word 0x1c1b1a19
.word 0x201f1e1d
start
adrp x0, input1
ldr q0, [x0, #:lo12:input1]
adrp x0, input2
ldr q1, [x0, #:lo12:input2]
uzp1 v2.8b, v0.8b, v1.8b
mov x1, v2.d[0]
adrp x3, zl8b
ldr x4, [x3, #:lo12:zl8b]
cmp x1, x4
bne .Lfailure
uzp2 v2.8b, v0.8b, v1.8b
mov x1, v2.d[0]
adrp x3, zu8b
ldr x4, [x3, #:lo12:zu8b]
cmp x1, x4
bne .Lfailure
uzp1 v2.16b, v0.16b, v1.16b
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, zl16b
ldr x4, [x3, #:lo12:zl16b]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:zl16b+8]
cmp x2, x5
bne .Lfailure
uzp2 v2.16b, v0.16b, v1.16b
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, zu16b
ldr x4, [x3, #:lo12:zu16b]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:zu16b+8]
cmp x2, x5
bne .Lfailure
uzp1 v2.4h, v0.4h, v1.4h
mov x1, v2.d[0]
adrp x3, zl4h
ldr x4, [x3, #:lo12:zl4h]
cmp x1, x4
bne .Lfailure
uzp2 v2.4h, v0.4h, v1.4h
mov x1, v2.d[0]
adrp x3, zu4h
ldr x4, [x3, #:lo12:zu4h]
cmp x1, x4
bne .Lfailure
uzp1 v2.8h, v0.8h, v1.8h
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, zl8h
ldr x4, [x3, #:lo12:zl8h]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:zl8h+8]
cmp x2, x5
bne .Lfailure
uzp2 v2.8h, v0.8h, v1.8h
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, zu8h
ldr x4, [x3, #:lo12:zu8h]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:zu8h+8]
cmp x2, x5
bne .Lfailure
uzp1 v2.2s, v0.2s, v1.2s
mov x1, v2.d[0]
adrp x3, zl2s
ldr x4, [x3, #:lo12:zl2s]
cmp x1, x4
bne .Lfailure
uzp2 v2.2s, v0.2s, v1.2s
mov x1, v2.d[0]
adrp x3, zu2s
ldr x4, [x3, #:lo12:zu2s]
cmp x1, x4
bne .Lfailure
uzp1 v2.4s, v0.4s, v1.4s
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, zl4s
ldr x4, [x3, #:lo12:zl4s]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:zl4s+8]
cmp x2, x5
bne .Lfailure
uzp2 v2.4s, v0.4s, v1.4s
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, zu4s
ldr x4, [x3, #:lo12:zu4s]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:zu4s+8]
cmp x2, x5
bne .Lfailure
uzp1 v2.2d, v0.2d, v1.2d
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, zl2d
ldr x4, [x3, #:lo12:zl2d]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:zl2d+8]
cmp x2, x5
bne .Lfailure
uzp2 v2.2d, v0.2d, v1.2d
mov x1, v2.d[0]
mov x2, v2.d[1]
adrp x3, zu2d
ldr x4, [x3, #:lo12:zu2d]
cmp x1, x4
bne .Lfailure
ldr x5, [x3, #:lo12:zu2d+8]
cmp x2, x5
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,216 | sim/testsuite/aarch64/fminnm.s | # mach: aarch64
# Check the FP min/max number instructions: fminnm, fmaxnm, dminnm, dmaxnm.
# For min, check 2/1, 1/0, -1/-Inf.
# For max, check 1/2, -1/0, 1/+inf.
.include "testutils.inc"
start
fmov s0, #2.0
fmov s1, #1.0
fminnm s2, s0, s1
fcmp s2, s1
bne .Lfailure
fmov d0, #2.0
fmov d1, #1.0
fminnm d2, d0, d1
fcmp d2, d1
bne .Lfailure
fmov s0, #1.0
fmov s1, wzr
fminnm s2, s0, s1
fcmp s2, s1
bne .Lfailure
fmov d0, #1.0
fmov d1, xzr
fminnm d2, d0, d1
fcmp d2, d1
bne .Lfailure
fmov s0, #-1.0
fmov s1, wzr
fdiv s1, s0, s1
fminnm s2, s0, s1
fcmp s2, s1
bne .Lfailure
fmov d0, #-1.0
fmov d1, xzr
fdiv d1, d0, d1
fminnm d1, d0, d1
fcmp d0, d0
bne .Lfailure
fmov s0, #1.0
fmov s1, #2.0
fmaxnm s2, s0, s1
fcmp s2, s1
bne .Lfailure
fmov d0, #1.0
fmov d1, #2.0
fmaxnm d2, d0, d1
fcmp d2, d1
bne .Lfailure
fmov s0, #-1.0
fmov s1, wzr
fmaxnm s2, s0, s1
fcmp s2, s1
bne .Lfailure
fmov d0, #-1.0
fmov d1, xzr
fmaxnm d2, d0, d1
fcmp d2, d1
bne .Lfailure
fmov s0, #1.0
fmov s1, wzr
fdiv s1, s0, s1
fmaxnm s2, s0, s1
fcmp s2, s1
bne .Lfailure
fmov d0, #1.0
fmov d1, xzr
fdiv d1, d0, d1
fmaxnm d1, d0, d1
fcmp d0, d0
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,828 | sim/testsuite/aarch64/ldn_single.s | # mach: aarch64
# Check the load single 1-element structure to one lane instructions:
# ld1, ld2, ld3, ld4.
# Check the addressing modes: no offset, post-index immediate offset,
# post-index register offset.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
.word 0x14131211
.word 0x18171615
.word 0x1c1b1a19
.word 0x201f1e1d
start
adrp x0, input
add x0, x0, :lo12:input
mov x2, x0
mov x3, #1
mov x4, #4
ld1 {v0.b}[0], [x2], 1
ld1 {v0.b}[1], [x2], x3
ld1 {v0.h}[1], [x2], 2
ld1 {v0.s}[1], [x2], x4
ld1 {v0.d}[1], [x2]
addv b1, v0.16b
mov x5, v1.d[0]
cmp x5, #136
bne .Lfailure
mov x2, x0
mov x3, #16
mov x4, #4
ld2 {v0.d, v1.d}[0], [x2], x3
ld2 {v0.s, v1.s}[2], [x2], 8
ld2 {v0.h, v1.h}[6], [x2], x4
ld2 {v0.b, v1.b}[14], [x2], 2
ld2 {v0.b, v1.b}[15], [x2]
addv b2, v0.16b
addv b3, v1.16b
mov x5, v2.d[0]
mov x6, v3.d[0]
cmp x5, #221
bne .Lfailure
cmp x6, #51
bne .Lfailure
mov x2, x0
ld3 {v0.s, v1.s, v2.s}[0], [x2], 12
ld3 {v0.s, v1.s, v2.s}[1], [x2]
mov x2, x0
mov x3, #12
ld3 {v0.s, v1.s, v2.s}[2], [x2], x3
ld3 {v0.s, v1.s, v2.s}[3], [x2]
addv b3, v0.16b
addv b4, v1.16b
addv b5, v2.16b
mov x4, v3.d[0]
mov x5, v4.d[0]
mov x6, v5.d[0]
cmp x4, #136
bne .Lfailure
cmp x5, #200
bne .Lfailure
cmp x6, #8
bne .Lfailure
mov x2, x0
ld4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16
ld4 {v0.s, v1.s, v2.s, v3.s}[1], [x2]
mov x2, x0
mov x3, #16
ld4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], x3
ld4 {v0.s, v1.s, v2.s, v3.s}[3], [x2]
addv b4, v0.16b
addv b5, v1.16b
addv b6, v2.16b
addv b7, v3.16b
mov x4, v4.d[0]
mov x5, v5.d[0]
mov x6, v6.d[0]
mov x7, v7.d[0]
cmp x4, #168
bne .Lfailure
cmp x5, #232
bne .Lfailure
cmp x6, #40
bne .Lfailure
cmp x7, #104
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 2,209 | sim/testsuite/aarch64/fcmp.s | # mach: aarch64
# Check the FP compare instructions: fcmps, fcmpzs, fcmpes, fcmpzes, fcmpd,
# fcmpzd, fcmped, fcmpzed.
# For 1 operand compares, check 0, 1, -1, +Inf, -Inf.
# For 2 operand compares, check 1/1, 1/-2, -1/2, +Inf/+Inf, +Inf/-Inf.
# FIXME: Check for qNaN and sNaN when exception raising support added.
.include "testutils.inc"
start
fmov s0, wzr
fcmp s0, #0.0
bne .Lfailure
fcmpe s0, #0.0
bne .Lfailure
fmov d0, xzr
fcmp d0, #0.0
bne .Lfailure
fcmpe d0, #0.0
bne .Lfailure
fmov s0, #1.0
fcmp s0, #0.0
blo .Lfailure
fcmpe s0, #0.0
blo .Lfailure
fmov d0, #1.0
fcmp d0, #0.0
blo .Lfailure
fcmpe d0, #0.0
blo .Lfailure
fmov s0, #-1.0
fcmp s0, #0.0
bpl .Lfailure
fcmpe s0, #0.0
bpl .Lfailure
fmov d0, #-1.0
fcmp d0, #0.0
bpl .Lfailure
fcmpe d0, #0.0
bpl .Lfailure
fmov s0, #1.0
fmov s1, wzr
fdiv s0, s0, s1
fcmp s0, #0.0
blo .Lfailure
fcmpe s0, #0.0
blo .Lfailure
fmov d0, #1.0
fmov d1, xzr
fdiv d0, d0, d1
fcmp d0, #0.0
blo .Lfailure
fcmpe d0, #0.0
blo .Lfailure
fmov s0, #-1.0
fmov s1, wzr
fdiv s0, s0, s1
fcmp s0, #0.0
bpl .Lfailure
fcmpe s0, #0.0
bpl .Lfailure
fmov d0, #-1.0
fmov d1, xzr
fdiv d0, d0, d1
fcmp d0, #0.0
bpl .Lfailure
fcmpe d0, #0.0
bpl .Lfailure
fmov s0, #1.0
fmov s1, #1.0
fcmp s0, s1
bne .Lfailure
fcmpe s0, s1
bne .Lfailure
fmov d0, #1.0
fmov d1, #1.0
fcmp d0, d1
bne .Lfailure
fcmpe d0, d1
bne .Lfailure
fmov s0, #1.0
fmov s1, #-2.0
fcmp s0, s1
blo .Lfailure
fcmpe s0, s1
blo .Lfailure
fmov d0, #1.0
fmov d1, #-2.0
fcmp d0, d1
blo .Lfailure
fcmpe d0, d1
blo .Lfailure
fmov s0, #-1.0
fmov s1, #2.0
fcmp s0, s1
bpl .Lfailure
fcmpe s0, s1
bpl .Lfailure
fmov d0, #-1.0
fmov d1, #2.0
fcmp d0, d1
bpl .Lfailure
fcmpe d0, d1
bpl .Lfailure
fmov s0, #1.0
fmov s1, wzr
fdiv s0, s0, s1
fcmp s0, s0
bne .Lfailure
fcmpe s0, s0
bne .Lfailure
fmov s1, #-1.0
fmov s2, wzr
fdiv s1, s1, s2
fcmp s0, s1
blo .Lfailure
fcmpe s0, s1
blo .Lfailure
fmov d0, #1.0
fmov d1, xzr
fdiv d0, d0, d1
fcmp d0, d0
bne .Lfailure
fcmpe d0, d0
bne .Lfailure
fmov d1, #-1.0
fmov d2, xzr
fdiv d1, d1, d2
fcmp d0, d1
blo .Lfailure
fcmpe d0, d1
blo .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 1,155 | sim/testsuite/aarch64/fcmXX.s | # mach: aarch64
# Check the FP scalar compare zero instructions: fcmeq, fcmle, fcmlt, fcmge,
# fcmgt.
# Check values -1, 0, and 1.
.include "testutils.inc"
start
fmov s0, wzr
fcmeq s1, s0, #0.0
mov w0, v1.s[0]
cmp w0, #-1
bne .Lfailure
fmov s0, #-1.0
fcmeq s1, s0, #0.0
mov w0, v1.s[0]
cmp w0, #0
bne .Lfailure
fmov d0, xzr
fcmeq d1, d0, #0.0
mov x0, v1.d[0]
cmp x0, #-1
bne .Lfailure
fmov d0, #1.0
fcmeq d1, d0, #0.0
mov x0, v1.d[0]
cmp x0, #0
bne .Lfailure
fmov s0, #-1.0
fcmle s1, s0, #0.0
mov w0, v1.s[0]
cmp w0, #-1
bne .Lfailure
fmov d0, #-1.0
fcmle d1, d0, #0.0
mov x0, v1.d[0]
cmp x0, #-1
bne .Lfailure
fmov s0, #-1.0
fcmlt s1, s0, #0.0
mov w0, v1.s[0]
cmp w0, #-1
bne .Lfailure
fmov d0, #-1.0
fcmlt d1, d0, #0.0
mov x0, v1.d[0]
cmp x0, #-1
bne .Lfailure
fmov s0, #1.0
fcmge s1, s0, #0.0
mov w0, v1.s[0]
cmp w0, #-1
bne .Lfailure
fmov d0, #1.0
fcmge d1, d0, #0.0
mov x0, v1.d[0]
cmp x0, #-1
bne .Lfailure
fmov s0, #1.0
fcmgt s1, s0, #0.0
mov w0, v1.s[0]
cmp w0, #-1
bne .Lfailure
fmov d0, #1.0
fcmgt d1, d0, #0.0
mov x0, v1.d[0]
cmp x0, #-1
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 2,142 | sim/testsuite/aarch64/ldn_multiple.s | # mach: aarch64
# Check the load multiple structure instructions: ld1, ld2, ld3, ld4.
# Check the addressing modes: no offset, post-index immediate offset,
# post-index register offset.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
.word 0xfcfdfeff
.word 0xf8f9fafb
.word 0xf4f5f6f7
.word 0xf0f1f2f3
start
adrp x0, input
add x0, x0, :lo12:input
mov x2, x0
mov x3, #16
ld1 {v0.16b}, [x2], 16
ld1 {v1.8h}, [x2], x3
addv b4, v0.16b
addv b5, v1.16b
mov x4, v4.d[0]
cmp x4, #136
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #120
bne .Lfailure
mov x2, x0
mov x3, #16
ld2 {v0.8b, v1.8b}, [x2], x3
ld2 {v2.4h, v3.4h}, [x2], 16
addv b4, v0.8b
addv b5, v1.8b
addv b6, v2.8b
addv b7, v3.8b
mov x4, v4.d[0]
cmp x4, #64
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #72
bne .Lfailure
mov x6, v6.d[0]
cmp x6, #196
bne .Lfailure
mov x7, v7.d[0]
cmp x7, #180
bne .Lfailure
mov x2, x0
ld3 {v0.2s, v1.2s, v2.2s}, [x2]
addv b4, v0.8b
addv b5, v1.8b
addv b6, v2.8b
mov x4, v4.d[0]
cmp x4, #68
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #16
bne .Lfailure
mov x6, v6.d[0]
cmp x6, #16
bne .Lfailure
mov x2, x0
ld4 {v0.4h, v1.4h, v2.4h, v3.4h}, [x2]
addv b4, v0.8b
addv b5, v1.8b
addv b6, v2.8b
addv b7, v3.8b
mov x4, v4.d[0]
cmp x4, #0
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #0
bne .Lfailure
mov x6, v6.d[0]
cmp x6, #0
bne .Lfailure
mov x7, v7.d[0]
cmp x7, #0
bne .Lfailure
mov x2, x0
ld1 {v0.4s, v1.4s}, [x2]
addv b4, v0.16b
addv b5, v1.16b
mov x4, v4.d[0]
cmp x4, #136
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #120
bne .Lfailure
mov x2, x0
ld1 {v0.1d, v1.1d, v2.1d}, [x2]
addv b4, v0.8b
addv b5, v1.8b
addv b6, v2.8b
mov x4, v4.d[0]
cmp x4, #36
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #100
bne .Lfailure
mov x6, v6.d[0]
cmp x6, #220
bne .Lfailure
mov x2, x0
ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x2]
addv b4, v0.8b
addv b5, v1.8b
addv b6, v2.8b
mov x4, v4.d[0]
cmp x4, #36
bne .Lfailure
mov x5, v5.d[0]
cmp x5, #100
bne .Lfailure
mov x6, v6.d[0]
cmp x6, #220
bne .Lfailure
pass
.Lfailure:
fail
|
tactcomplabs/xbgas-binutils-gdb | 3,346 | sim/testsuite/or1k/jump.S | /* Tests the jump instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x48000000);\n
# output: report(0x00000005);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x48000000);\n
# output: report(0x00000009);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x44000000);\n
# output: report(0x00000005);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x44000000);\n
# output: report(0x00000009);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
/* Tests a jump instruction using a register destination.
Checks whether the jump succeeds, or whether an exception is triggered
(but not if the right exception was triggered yet).
We manually construct the opcode, to allow us to force R9 into the
destination field, to test exception handling. Usually the assembler
would prevent this.
Do not specify R31 as the register to use for the jump, as it's used
internally. */
.macro TEST_JUMP opcode_value dest_register_number alignment_offset
REPORT_IMMEDIATE_TO_CONSOLE \opcode_value
REPORT_IMMEDIATE_TO_CONSOLE \dest_register_number
REPORT_IMMEDIATE_TO_CONSOLE \alignment_offset
LOAD_IMMEDIATE r\dest_register_number, 51f + \alignment_offset
/* Generate the jump opcode. */
\@1$: OR1K_DELAYED_NOP \
(.word ( \opcode_value | (\dest_register_number << 11) ))
/* If the jump failed, we land here. */
REPORT_IMMEDIATE_TO_CONSOLE 1
OR1K_DELAYED_NOP (l.j 52f)
/* If the jump succeeds, we land here. */
51: REPORT_IMMEDIATE_TO_CONSOLE 0
52: REPORT_EXCEPTION \@1$
PRINT_NEWLINE_TO_CONSOLE
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.jalr (jump and link register) */
TEST_JUMP 0x48000000, 5, 0
/* TODO: The sim does not support unaligned memory access yet.
TEST_JUMP 0x48000000, 5, 1
TEST_JUMP 0x48000000, 5, 2
TEST_JUMP 0x48000000, 5, 3
*/
/* Test with link register as the destination. This is not
allowed. */
TEST_JUMP 0x48000000, 9, 0
/* Test l.jr (jump register) */
TEST_JUMP 0x44000000, 5, 0
/* TODO: The sim does not support unaligned memory access yet.
TEST_JUMP 0x44000000, 5, 1
TEST_JUMP 0x44000000, 5, 2
TEST_JUMP 0x44000000, 5, 3
*/
/* Test with link register as the destination. */
TEST_JUMP 0x44000000, 9, 0
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 1,909 | sim/testsuite/or1k/adrp.S | /* Tests the load page address instruction.
Copyright (C) 2019-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00002064);\n
# output: report(0x00012138);\n
# output: report(0x00002000);\n
# output: report(0x00012000);\n
# output: report(0x00002000);\n
# output: report(0x00014000);\n
# output: report(0x00000000);\n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .data
.org 0x10000
.align 4
.type pi, @object
.size pi, 4
pi:
.float 3.14159
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Print out the PC. To compare with that loaded by l.adrp. */
l.jal capture_pc
l.nop
capture_pc:
REPORT_REG_TO_CONSOLE r9
/* Print out our data address to compared with l.adrp offset. */
l.movhi r11, ha(pi)
l.addi r11, r11, lo(pi)
REPORT_REG_TO_CONSOLE r11
/* Test l.adrp with symbols, loads page of symbol to register. */
l.adrp r4, start_tests
REPORT_REG_TO_CONSOLE r4
l.adrp r4, pi
REPORT_REG_TO_CONSOLE r4
/* Test l.adrp with immediate, immediate is the page offset. */
l.adrp r4, 0x0
REPORT_REG_TO_CONSOLE r4
l.adrp r4, 0x12000
REPORT_REG_TO_CONSOLE r4
l.adrp r4, -0x2000
REPORT_REG_TO_CONSOLE r4
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 15,484 | sim/testsuite/or1k/shift.S | /* Tests the shift instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0x671e1f06);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x38f0f830);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0f830000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x80000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0x671e1f06);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00002224);\n
# output: report(0x38f0f830);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00f789f0);\n
# output: report(0x0f830000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0x671e1f06);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x38f0f830);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0f830000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x80000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0x671e1f06);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000024);\n
# output: report(0x38f0f830);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000030);\n
# output: report(0x0f830000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000003f);\n
# output: report(0x80000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0xfb38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0xffffb38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0xffffffff);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000001);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000004);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000010);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000001f);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00002224);\n
# output: report(0xfb38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00f789f0);\n
# output: report(0xffffb38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000021);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00002224);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00f789f0);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0xfb38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0xffffb38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0xffffffff);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000001);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000004);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000010);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000001f);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000024);\n
# output: report(0xfb38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000030);\n
# output: report(0xffffb38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000003f);\n
# output: report(0xffffffff);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000021);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000024);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000030);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000003f);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0x59c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x0b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0000b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000001);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000004);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000010);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000001f);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0x59c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00002224);\n
# output: report(0x0b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00f789f0);\n
# output: report(0x0000b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000021);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00002224);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00f789f0);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0x59c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x0b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0000b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000001);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000004);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000010);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000001f);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0x59c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000024);\n
# output: report(0x0b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000030);\n
# output: report(0x0000b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000003f);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000021);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000024);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000030);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000003f);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
.macro TEST_SHIFT opcode, op1, op2
LOAD_IMMEDIATE r5, \op1
LOAD_IMMEDIATE r6, \op2
REPORT_REG_TO_CONSOLE r5
REPORT_REG_TO_CONSOLE r6
\opcode r4, r5, r6
CHECK_CARRY_AND_OVERFLOW_NOT_SET r2, r3
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
.macro TEST_SHIFT_I opcode, op1, op2
LOAD_IMMEDIATE r5, \op1
REPORT_REG_TO_CONSOLE r5
REPORT_IMMEDIATE_TO_CONSOLE \op2
\opcode r4, r5, \op2
CHECK_CARRY_AND_OVERFLOW_NOT_SET r2, r3
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Always set OVE. We should never trigger an exception, even if
this bit is set. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.sll */
/* Shift left by zero. */
TEST_SHIFT l.sll, 0xb38f0f83, 0x00000000
/* Shift left by amounts in the 1-31 range. */
TEST_SHIFT l.sll, 0xb38f0f83, 0x00000001
TEST_SHIFT l.sll, 0xb38f0f83, 0x00000004
TEST_SHIFT l.sll, 0xb38f0f83, 0x00000010
TEST_SHIFT l.sll, 0xb38f0f83, 0x0000001f
/* Shift left by larger amounts - should be masked. */
TEST_SHIFT l.sll, 0xb38f0f83, 0x00000021
TEST_SHIFT l.sll, 0xb38f0f83, 0x00002224
TEST_SHIFT l.sll, 0xb38f0f83, 0x00f789f0
TEST_SHIFT l.sll, 0xb38f0f83, 0xffffffff
/* Test l.slli */
/* Shift left by zero. */
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0000
/* Shift left by amounts in the 1-31 range. */
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0001
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0004
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0010
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x001f
/* Shift left by larger amounts - should be masked. */
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0021
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0024
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0030
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x003f
/* Test l.sra */
/* Shift right by zero. */
TEST_SHIFT l.sra, 0xb38f0f83, 0x00000000
/* Shift right by amounts in the 1-31 range. */
TEST_SHIFT l.sra, 0xb38f0f83, 0x00000001
TEST_SHIFT l.sra, 0xb38f0f83, 0x00000004
TEST_SHIFT l.sra, 0xb38f0f83, 0x00000010
TEST_SHIFT l.sra, 0xb38f0f83, 0x0000001f
TEST_SHIFT l.sra, 0x4c70f07c, 0x00000001
TEST_SHIFT l.sra, 0x4c70f07c, 0x00000004
TEST_SHIFT l.sra, 0x4c70f07c, 0x00000010
TEST_SHIFT l.sra, 0x4c70f07c, 0x0000001f
/* Shift right by larger amounts - should be masked. */
TEST_SHIFT l.sra, 0xb38f0f83, 0x00000021
TEST_SHIFT l.sra, 0xb38f0f83, 0x00002224
TEST_SHIFT l.sra, 0xb38f0f83, 0x00f789f0
TEST_SHIFT l.sra, 0xb38f0f83, 0xffffffff
TEST_SHIFT l.sra, 0x4c70f07c, 0x00000021
TEST_SHIFT l.sra, 0x4c70f07c, 0x00002224
TEST_SHIFT l.sra, 0x4c70f07c, 0x00f789f0
TEST_SHIFT l.sra, 0x4c70f07c, 0xffffffff
/* Test l.srai */
/* Shift right by zero. */
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0000
/* Shift right by amounts in the 1-31 range. */
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0001
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0004
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0010
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x001f
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0001
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0004
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0010
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x001f
/* Shift right by larger amounts - should be masked. */
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0021
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0024
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0030
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x003f
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0021
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0024
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0030
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x003f
/* Test l.srl */
/* Shift right by zero. */
TEST_SHIFT l.srl, 0xb38f0f83, 0x00000000
/* Shift right by amounts in the 1-31 range. */
TEST_SHIFT l.srl, 0xb38f0f83, 0x00000001
TEST_SHIFT l.srl, 0xb38f0f83, 0x00000004
TEST_SHIFT l.srl, 0xb38f0f83, 0x00000010
TEST_SHIFT l.srl, 0xb38f0f83, 0x0000001f
TEST_SHIFT l.srl, 0x4c70f07c, 0x00000001
TEST_SHIFT l.srl, 0x4c70f07c, 0x00000004
TEST_SHIFT l.srl, 0x4c70f07c, 0x00000010
TEST_SHIFT l.srl, 0x4c70f07c, 0x0000001f
/* Shift right by larger amounts - should be masked. */
TEST_SHIFT l.srl, 0xb38f0f83, 0x00000021
TEST_SHIFT l.srl, 0xb38f0f83, 0x00002224
TEST_SHIFT l.srl, 0xb38f0f83, 0x00f789f0
TEST_SHIFT l.srl, 0xb38f0f83, 0xffffffff
TEST_SHIFT l.srl, 0x4c70f07c, 0x00000021
TEST_SHIFT l.srl, 0x4c70f07c, 0x00002224
TEST_SHIFT l.srl, 0x4c70f07c, 0x00f789f0
TEST_SHIFT l.srl, 0x4c70f07c, 0xffffffff
/* Test l.srli */
/* Shift right by zero. */
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0000
/* Shift right by amounts in the 1-31 range. */
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0001
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0004
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0010
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x001f
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0001
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0004
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0010
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x001f
/* Shift right by larger amounts - should be masked. */
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0021
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0024
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0030
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x003f
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0021
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0024
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0030
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x003f
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 18,041 | sim/testsuite/or1k/mul.S | /* Tests the multiply instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008001);\n
# output: report(0x0000fffe);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00010000);\n
# output: report(0x00010000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0002);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0000);\n
# output: report(0x80010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff0000);\n
# output: report(0xfffeffff);\n
# output: report(0x00010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff8000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0x00010000);\n
# output: report(0x7fff0000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0000);\n
# output: report(0x80010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00010002);\n
# output: report(0x00007fff);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00020000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00040000);\n
# output: report(0x00004000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffffe);\n
# output: report(0x0000fffd);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffefffe);\n
# output: report(0x00008001);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffe0000);\n
# output: report(0x0000bfff);\n
# output: report(0x80020000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffdfffe);\n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0x0000fffd);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00010000);\n
# output: report(0x00008000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffdfffc);\n
# output: report(0x00004000);\n
# output: report(0x7fff0000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00020000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xfffffffe);\n
# output: report(0x0000fffd);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffdfffe);\n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008001);\n
# output: report(0x0000fffe);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00010000);\n
# output: report(0x00010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000006);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0002);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0000);\n
# output: report(0x80010000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff0000);\n
# output: report(0xfffeffff);\n
# output: report(0x00010000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffa);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff8000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0x00010000);\n
# output: report(0x7fff0000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffa);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0000);\n
# output: report(0x80010000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Range exception. */
.org 0xb00
/* The handling is a bit dubious at present. We just patch the
instruction with l.nop and restart. This will go wrong in branch
delay slots, but we are not testing that here. */
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw 0(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.mul */
/* Multiply two small positive numbers. This should set no flags.
*/
TEST_INST_I32_I32 l.mul, 0x00000002, 0x00000003
/* Multiply two quite large positive numbers. This should set no
flags */
TEST_INST_I32_I32 l.mul, 0x00008001, 0x0000fffe
/* Multiply two slightly too large positive numbers. This should
set the overflow, but not the carry flag . */
TEST_INST_I32_I32 l.mul, 0x00008000, 0x00010000
/* Multiply two large positive numbers. This should set the
overflow flags (even though the result is not a negative
number. */
TEST_INST_I32_I32 l.mul, 0x00010000, 0x00010000
/* Multiply two small negative numbers. This will set no flags. */
TEST_INST_I32_I32 l.mul, 0xfffffffe, 0xfffffffd
/* Multiply two quite large negative numbers. This will no flags. */
TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0002
/* Multiply two slightly too large negative numbers. This should
set the overflow flag. */
TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0000
/* Multiply two large negative numbers. This should set the
both the carry and overflow flags (even though the result is a
positive number. */
TEST_INST_I32_I32 l.mul, 0xffff0000, 0xfffeffff
/* Multiply one small negative number and one small positive
number. This will set the no flags. */
TEST_INST_I32_I32 l.mul, 0x00000002, 0xfffffffd
/* Multiply one quite large negative number and one quite large
positive number. This will set no flags. */
TEST_INST_I32_I32 l.mul, 0xffff8000, 0x00010000
/* Multiply one slightly too large negative number and one slightly
too large positive number. This should set the overflow flag. */
TEST_INST_I32_I32 l.mul, 0xffff7fff, 0x00010000
/* Multiply the largest negative number by positive unity. This
should set neither carry, nor overflow flag. */
TEST_INST_I32_I32 l.mul, 0x80000000, 0x00000001
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception. */
TEST_INST_I32_I32 l.mul, 0x00008000, 0x00010000
/* Check multiply of a negative and positive does not cause a RANGE
Exception. */
TEST_INST_I32_I32 l.mul, 0x00000002, 0xfffffffd
/* Check that negative overflow causes a RANGE exception. */
TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.muli */
/* Multiply two small positive numbers. This should set no flags. */
TEST_INST_I32_I16 l.muli, 0x00000002, 0x0003
/* Multiply two quite large positive numbers. This should set no
flags */
TEST_INST_I32_I16 l.muli, 0x00010002, 0x7fff
/* Multiply two slightly too large positive numbers. This should
set the overflow, but not the carry flag. */
TEST_INST_I32_I16 l.muli, 0x00020000, 0x4000
/* Multiply two large positive numbers. This should set the
overflow flag, even though the result is not a negative number. */
TEST_INST_I32_I16 l.muli, 0x00040000, 0x4000
/* Multiply two small negative numbers. This should set no flags. */
TEST_INST_I32_I16 l.muli, 0xfffffffe, 0xfffd
/* Multiply two quite large negative numbers. This will set no
flags. */
TEST_INST_I32_I16 l.muli, 0xfffefffe, 0x8001
/* Multiply two slightly too large negative numbers. This should
set the overflow flag. */
TEST_INST_I32_I16 l.muli, 0xfffe0000, 0xbfff
/* Multiply two large negative numbers. This should set the
overflow flag, even though the result is a positive number. */
TEST_INST_I32_I16 l.muli, 0xfffdfffe, 0x8000
/* Multiply one small negative number and one small positive
number. This will set no flags. */
TEST_INST_I32_I16 l.muli, 0x00000002, 0xfffd
/* Multiply one quite large negative number and one quite large
positive number. This will set no flags. */
TEST_INST_I32_I16 l.muli, 0x00010000, 0x8000
/* Multiply one slightly too large negative number and one slightly
too large positive number. This will set the overflow flag. */
TEST_INST_I32_I16 l.muli, 0xfffdfffc, 0x4000
/* Multiply the largest negative number by positive unity. Should
set neither carry, nor overflow flag. */
TEST_INST_I32_I16 l.muli, 0x80000000, 0x0001
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception. */
TEST_INST_I32_I16 l.muli, 0x00020000, 0x4000
/* Check that two negatives will not cause a RANGE Exception. */
TEST_INST_I32_I16 l.muli, 0xfffffffe, 0xfffd
/* Check that multiply of larget negative and positive numbers causes
a RANGE exception and overflow. */
TEST_INST_I32_I16 l.muli, 0xfffdfffe, 0x8000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.mulu */
/* Multiply two small positive numbers. This should set no flags. */
TEST_INST_I32_I32 l.mulu, 0x00000002, 0x00000003
/* Multiply two quite large positive numbers. This should set no
flags. */
TEST_INST_I32_I32 l.mulu, 0x00008001, 0x0000fffe
/* Multiply two slightly too large positive numbers. This will set
no flags. */
TEST_INST_I32_I32 l.mulu, 0x00008000, 0x00010000
/* Multiply two large positive numbers. This will set the overflow
flag. */
TEST_INST_I32_I32 l.mulu, 0x00010000, 0x00010000
/* Multiply two small negative numbers. This will set the
carry flag, but not the overflow flag. */
TEST_INST_I32_I32 l.mulu, 0xfffffffe, 0xfffffffd
/* Multiply two quite large negative numbers. This will set the
carry flag, but not the overflow flag. */
TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0002
/* Multiply two slightly too large negative numbers. This will set
the carry flag, and not the overflow flag */
TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0000
/* Multiply two large negative numbers. This will set the both the
carry flag (even though the result is a positive number.) */
TEST_INST_I32_I32 l.mulu, 0xffff0000, 0xfffeffff
/* Multiply one small negative number and one small positive
number. This will set the carry flag, but not the overflow
flag. */
TEST_INST_I32_I32 l.mulu, 0x00000002, 0xfffffffd
/* Multiply one quite large negative number and one quite large
positive number. This will set the carry flag, but not the
overflow flag. */
TEST_INST_I32_I32 l.mulu, 0xffff8000, 0x00010000
/* Multiply one slightly too large negative number and one slightly
too large positive number. This will set the carry flag, but
not the overflow flag. */
TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0x00010000
/* Multiply the largest negative number by positive unity. Should
set neither carry, nor overflow flag. */
TEST_INST_I32_I32 l.mulu, 0x80000000, 0x00000001
/* Check that range exceptions are never triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that what would cause an overflow alone in 2's complement
does not cause a RANGE Exception. */
TEST_INST_I32_I32 l.mulu, 0x00008000, 0x00010000
/* Check that a carry causes a RANGE Exception. */
TEST_INST_I32_I32 l.mulu, 0x00000002, 0xfffffffd
/* Check that what would cause an overflow and carry in 2's
complement causes a RANGE Exception. */
TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 2,444 | sim/testsuite/or1k/fpu64a32-unordered.S | /* Tests some basic unordered fpu compare instructions.
Copyright (C) 2019-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x400921f9);\n
# output: report(0xf01b866e);\n
# output: report(0x4005bf09);\n
# output: report(0x95aaf790);\n
# output: report(0x7ff80000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .data
.align 4
.type pi, @object
.size pi, 8
anchor:
pi:
.double 3.14159
.type e, @object
.size e, 8
e:
.double 2.71828
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test unordered double comparisons. Setting up:
* r11 pointer to data
* r12,r13 pi as double
* r14,r15 e as double
* r16,r17 nan as double
*/
l.ori r11, r0, ha(anchor)
l.addi r11, r11, lo(anchor)
l.lwz r12, 0(r11)
l.lwz r13, 4(r11)
l.lwz r14, 8(r11)
l.lwz r15, 12(r11)
/* Make a NaN. */
lf.sub.d r16,r18, r12,r13, r12,r13
lf.div.d r16,r18, r16,r18, r16,r18
/* Output to ensure we loaded it correctly. */
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
REPORT_REG_TO_CONSOLE r14
REPORT_REG_TO_CONSOLE r15
REPORT_REG_TO_CONSOLE r16
REPORT_REG_TO_CONSOLE r18
PRINT_NEWLINE_TO_CONSOLE
lf.sfuge.d r12,r13, r14,r15
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
lf.sfun.d r12,r13, r14,r15
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
lf.sfun.d r12,r13, r16,r18
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 9,141 | sim/testsuite/or1k/basic.S | /* Tests some basic CPU instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0xffff0012);\n
# output: report(0x12352af7);\n
# output: report(0x7ffffffe);\n
# output: report(0xffffa5a7);\n
# output: report(0x000fffff);\n
# output: report(0x00002800);\n
# output: report(0x00000009);\n
# output: report(0xdeaddead);\n
# output: report(0xffff0000);\n
# output: report(0x12345678);\n
# output: report(0xabcdf0bd);\n
# output: exit(0)\n
#include "or1k-asm-test-env.h"
#define FIRST_RAM_ADDR 0x00000000
STANDARD_TEST_HEADER
/* Early test begin. */
/* Do this test upfront, as it modifies STACK_POINTER_R1. */
l.addi r1 , r0 , 0x1
l.addi r2 , r1 , 0x2
l.addi r3 , r2 , 0x4
l.addi r4 , r3 , 0x8
l.addi r5 , r4 , 0x10
l.addi r6 , r5 , 0x20
l.addi r7 , r6 , 0x40
l.addi r8 , r7 , 0x80
l.addi r9 , r8 , 0x100
l.addi r10, r9 , 0x200
l.addi r11, r10, 0x400
l.addi r12, r11, 0x800
l.addi r13, r12, 0x1000
l.addi r14, r13, 0x2000
l.addi r15, r14, 0x4000
l.addi r16, r15, 0x8000
l.sub r31, r0 , r1
l.sub r30, r31, r2
l.sub r29, r30, r3
l.sub r28, r29, r4
l.sub r27, r28, r5
l.sub r26, r27, r6
l.sub r25, r26, r7
l.sub r24, r25, r8
l.sub r23, r24, r9
l.sub r22, r23, r10
l.sub r21, r22, r11
l.sub r20, r21, r12
l.sub r19, r20, r13
l.sub r18, r19, r14
l.sub r17, r18, r15
l.sub r16, r17, r16
/* We cannot use REPORT_REG_TO_CONSOLE here, as the stack is not
set up yet. */
MOVE_REG NOP_REPORT_R3, r16
REPORT_TO_CONSOLE /* Should be 0xffff0012 */
/* Early test end. */
STANDARD_TEST_BODY
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Read and write from RAM. */
LOAD_IMMEDIATE r31, FIRST_RAM_ADDR
l.sw 0(r31), r16
l.movhi r3,0x1234
l.ori r3,r3,0x5678
l.sw 4(r31),r3
l.lbz r4,4(r31)
l.add r8,r8,r4
l.sb 11(r31),r4
l.lbz r4,5(r31)
l.add r8,r8,r4
l.sb 10(r31),r4
l.lbz r4,6(r31)
l.add r8,r8,r4
l.sb 9(r31),r4
l.lbz r4,7(r31)
l.add r8,r8,r4
l.sb 8(r31),r4
l.lbs r4,8(r31)
l.add r8,r8,r4
l.sb 7(r31),r4
l.lbs r4,9(r31)
l.add r8,r8,r4
l.sb 6(r31),r4
l.lbs r4,10(r31)
l.add r8,r8,r4
l.sb 5(r31),r4
l.lbs r4,11(r31)
l.add r8,r8,r4
l.sb 4(r31),r4
l.lhz r4,4(r31)
l.add r8,r8,r4
l.sh 10(r31),r4
l.lhz r4,6(r31)
l.add r8,r8,r4
l.sh 8(r31),r4
l.lhs r4,8(r31)
l.add r8,r8,r4
l.sh 6(r31),r4
l.lhs r4,10(r31)
l.add r8,r8,r4
l.sh 4(r31),r4
l.lwz r4,4(r31)
l.add r8,r8,r4
REPORT_REG_TO_CONSOLE r8 /* Should be 0x12352af7 */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
/* Test arithmetic operations. */
l.addi r3,r0,1
l.addi r4,r0,2
l.addi r5,r0,-1
l.addi r6,r0,-1
l.addi r8,r0,0
l.sub r7,r5,r3
l.sub r8,r3,r5
l.add r8,r8,r7
l.div r7,r7,r4
l.add r9,r3,r4
l.mul r7,r9,r7
l.divu r7,r7,r4
l.add r8,r8,r7
REPORT_REG_TO_CONSOLE r8 /* Should be 0x7ffffffe */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
/* Test logical operations. */
l.addi r3,r0,1
l.addi r4,r0,2
l.addi r5,r0,-1
l.addi r6,r0,-1
l.addi r8,r0,0
l.andi r8,r8,1
l.and r8,r8,r3
l.xori r8,r5,0xa5a5
l.xor r8,r8,r5
l.ori r8,r8,2
l.or r8,r8,r4
REPORT_REG_TO_CONSOLE r8 /* Should be 0xffffa5a7 */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
/* Test shifting operations. */
l.addi r3,r0,1
l.addi r4,r0,2
l.addi r5,r0,-1
l.addi r6,r0,-1
l.addi r8,r0,0
l.slli r8,r5,6
l.sll r8,r8,r4
l.srli r8,r8,6
l.srl r8,r8,r4
l.srai r8,r8,2
l.sra r8,r8,r4
REPORT_REG_TO_CONSOLE r8 /* Should be 0x000fffff */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
/* Test the CPU flag. */
l.addi r3,r0,1
l.addi r4,r0,-2
l.addi r8,r0,0
l.sfeq r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfeq r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfeqi r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfeqi r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfne r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfne r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfnei r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfnei r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtu r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtu r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtui r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtui r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgeu r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgeu r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgeui r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgeui r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltu r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltu r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltui r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltui r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfleu r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfleu r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfleui r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfleui r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgts r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgts r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtsi r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtsi r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfges r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfges r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgesi r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgesi r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sflts r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sflts r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltsi r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltsi r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfles r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfles r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sflesi r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sflesi r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
REPORT_REG_TO_CONSOLE r8 /* Should be 0x00002800 */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
/* Test the jump instructions. */
l.addi r8,r0,0
OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.j _T1)
)
_T2: OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.jr r9)
)
_T1: OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.jal _T2)
)
l.sfeqi r0,0
OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.bf _T3)
)
_T3: l.sfeqi r0,1
OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.bf _T4)
)
l.addi r8,r8,1
_T4: l.sfeqi r0,0
OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.bnf _T5)
)
l.addi r8,r8,1
_T5: l.sfeqi r0,1
OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.bnf _T6)
)
l.addi r8,r8,1
_T6: l.movhi r3,hi (_T7)
l.ori r3,r3,lo (_T7)
l.mtspr r0,r3,32
l.mfspr r5,r0,17
l.mtspr r0,r5,64
l.rfe
l.addi r8,r8,1 /* l.rfe should not have a delay slot */
l.addi r8,r8,1
_T7: REPORT_REG_TO_CONSOLE r8 /* Should be 0x000000009 */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
l.lwz r9,0(r31)
l.movhi r3,0x4c69
l.ori r3,r3,0xe5f7
l.add r8,r8,r3
REPORT_REG_TO_CONSOLE r8 /* Should be 0xdeaddead */
/* Test l.movhi, on 32-bit implementations it should not
sign-extend anything. */
l.movhi r3, -1
REPORT_REG_TO_CONSOLE r3
/* Test l.cmov */
LOAD_IMMEDIATE r14, 0x12345678
LOAD_IMMEDIATE r15, 0xABCDF0BD
SET_SPR_SR_FLAGS SPR_SR_F, r6, r7
l.cmov r10, r14, r15
CLEAR_SPR_SR_FLAGS SPR_SR_F, r6, r7
l.cmov r11, r14, r15
REPORT_REG_TO_CONSOLE r10
REPORT_REG_TO_CONSOLE r11
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 6,846 | sim/testsuite/or1k/sub.S | /* Tests instruction l.sub.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000003);\n
# output: report(0x00000002);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000003);\n
# output: report(0x00000002);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffffd);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xfffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffffff);\n
# output: report(0x3fffffff);\n
# output: report(0x40000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x40000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x3fffffff);\n
# output: report(0x40000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x3fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x3fffffff);\n
# output: report(0x40000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Range exception. */
.org 0xb00
/* The handling is a bit dubious at present. We just patch the
instruction with l.nop and restart. This will go wrong in branch
delay slots. But we don't have those in this test. */
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw 0(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.sub */
/* Subtract two small positive numbers. Sets the carry, but never
the overflow if the result is negative. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x00000003, \
0x00000002
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x00000001, \
0x00000002
/* Check carry in is ignored. */
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.sub, 0x00000003, 0x00000002
/* Subtract two small negative numbers. Sets the carry flag if
the result is negative, but never the overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0xfffffffd, \
0xfffffffe
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0xffffffff, \
0xfffffffe
/* Subtract two quite large positive numbers. Should set neither
the overflow nor the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \
0x3fffffff
/* Subtract two quite large negative numbers. Should set neither
the overflow nor the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x40000000, \
0x40000000
/* Subtract two large positive numbers with a negative result.
Should set the carry, but not the overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x3fffffff, \
0x40000000
/* Subtract two large negative numbers with a positive result.
Should set neither the carry nor the overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x40000000, \
0x3fffffff
/* Subtract a large positive from a large negative number. Should
set overflow but not the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x80000000, \
0x7fffffff
/* Subtract a large negative from a large positive number. Should
set both the overflow and carry flags. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \
0x80000000
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x80000000, \
0x7fffffff
/* Check that a carry alone does not cause a RANGE Exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x3fffffff, \
0x40000000
/* Check that carry and overflow together cause an exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \
0x80000000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 9,037 | sim/testsuite/or1k/flag.S | /* Tests the set flag (l.sf*) instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
#define INT_MAX 2147483647 /* 0x7fffffff */
#define INT_MAX_MIN1 2147483646 /* 0x7ffffffe */
#define NEG_INT_MAX -2147483648 /* 0x80000000 */
#define NEG_INT_MAX_PL1 -2147483647 /* 0x80000001 */
#define MIN1 -1 /* 0xffffffff */
#define SHRT_MIN (-32768)
#define SHRT_MAX 32767
#define UINT_MAX 4294967295 /* 0xffffffff */
#define UINT_MAX_MIN1 4294967294 /* 0xfffffffe */
#define USHRT_MAX 65535
.macro MOVE_TO_R4_R5_AND_REPORT a, b
LOAD_IMMEDIATE r4, \a
LOAD_IMMEDIATE r5, \b
/* During development, add REPORT_xxx statements here to see the
operands. */
.endm
.macro MOVE_TO_R4_AND_REPORT_I a, b
LOAD_IMMEDIATE r4, \a
/* During development, add REPORT_xxx statements here to see the
operands. */
.endm
.macro SHOULD_BE_SET
OR1K_DELAYED_NOP (l.bnf failed)
.endm
.macro SHOULDNT_BE_SET
OR1K_DELAYED_NOP (l.bf failed)
.endm
.macro SHOULD_BE_LESS_THAN_SIGNED a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULDNT_BE_SET
l.sfne r4, r5
SHOULD_BE_SET
l.sfgts r4, r5
SHOULDNT_BE_SET
l.sfges r4, r5
SHOULDNT_BE_SET
l.sfles r4, r5
SHOULD_BE_SET
l.sflts r4, r5
SHOULD_BE_SET
.endm
.macro SHOULD_BE_GREATER_THAN_SIGNED a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULDNT_BE_SET
l.sfne r4, r5
SHOULD_BE_SET
l.sfgts r4, r5
SHOULD_BE_SET
l.sfges r4, r5
SHOULD_BE_SET
l.sfles r4, r5
SHOULDNT_BE_SET
l.sflts r4, r5
SHOULDNT_BE_SET
.endm
.macro SHOULD_BE_LESS_THAN_UNSIGNED a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULDNT_BE_SET
l.sfne r4, r5
SHOULD_BE_SET
l.sfgtu r4, r5
SHOULDNT_BE_SET
l.sfgeu r4, r5
SHOULDNT_BE_SET
l.sfleu r4, r5
SHOULD_BE_SET
l.sfltu r4, r5
SHOULD_BE_SET
.endm
.macro SHOULD_BE_GREATER_THAN_UNSIGNED a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULDNT_BE_SET
l.sfne r4, r5
SHOULD_BE_SET
l.sfgtu r4, r5
SHOULD_BE_SET
l.sfgeu r4, r5
SHOULD_BE_SET
l.sfleu r4, r5
SHOULDNT_BE_SET
l.sfltu r4, r5
SHOULDNT_BE_SET
.endm
.macro SHOULD_BE_EQUAL a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULD_BE_SET
l.sfne r4, r5
SHOULDNT_BE_SET
/* Signed tests. */
l.sfgts r4, r5
SHOULDNT_BE_SET
l.sfges r4, r5
SHOULD_BE_SET
l.sfles r4, r5
SHOULD_BE_SET
l.sflts r4, r5
SHOULDNT_BE_SET
/* Unsigned tests. */
l.sfgtu r4, r5
SHOULDNT_BE_SET
l.sfgeu r4, r5
SHOULD_BE_SET
l.sfleu r4, r5
SHOULD_BE_SET
l.sfltu r4, r5
SHOULDNT_BE_SET
.endm
.macro SHOULDNT_BE_EQUAL a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULDNT_BE_SET
l.sfne r4, r5
SHOULD_BE_SET
.endm
.macro SHOULD_BE_EQUAL_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULD_BE_SET
l.sfnei r4, \b
SHOULDNT_BE_SET
/* Signed tests. */
l.sfgtsi r4, \b
SHOULDNT_BE_SET
l.sfgesi r4, \b
SHOULD_BE_SET
l.sflesi r4, \b
SHOULD_BE_SET
l.sfltsi r4, \b
SHOULDNT_BE_SET
/* Unsigned tests. */
l.sfgtui r4, \b
SHOULDNT_BE_SET
l.sfgeui r4, \b
SHOULD_BE_SET
l.sfleui r4, \b
SHOULD_BE_SET
l.sfltui r4, \b
SHOULDNT_BE_SET
.endm
.macro SHOULDNT_BE_EQUAL_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULDNT_BE_SET
l.sfnei r4, \b
SHOULD_BE_SET
.endm
.macro SHOULD_BE_LESS_THAN_SIGNED_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULDNT_BE_SET
l.sfnei r4, \b
SHOULD_BE_SET
l.sfgtsi r4, \b
SHOULDNT_BE_SET
l.sfgesi r4, \b
SHOULDNT_BE_SET
l.sflesi r4, \b
SHOULD_BE_SET
l.sfltsi r4, \b
SHOULD_BE_SET
.endm
.macro SHOULD_BE_GREATER_THAN_SIGNED_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULDNT_BE_SET
l.sfnei r4, \b
SHOULD_BE_SET
l.sfgtsi r4, \b
SHOULD_BE_SET
l.sfgesi r4, \b
SHOULD_BE_SET
l.sflesi r4, \b
SHOULDNT_BE_SET
l.sfltsi r4, \b
SHOULDNT_BE_SET
.endm
.macro SHOULD_BE_LESS_THAN_UNSIGNED_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULDNT_BE_SET
l.sfnei r4, \b
SHOULD_BE_SET
l.sfgtui r4, \b
SHOULDNT_BE_SET
l.sfgeui r4, \b
SHOULDNT_BE_SET
l.sfleui r4, \b
SHOULD_BE_SET
l.sfltui r4, \b
SHOULD_BE_SET
.endm
.macro SHOULD_BE_GREATER_THAN_UNSIGNED_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULDNT_BE_SET
l.sfnei r4, \b
SHOULD_BE_SET
l.sfgtui r4, \b
SHOULD_BE_SET
l.sfgeui r4, \b
SHOULD_BE_SET
l.sfleui r4, \b
SHOULDNT_BE_SET
l.sfltui r4, \b
SHOULDNT_BE_SET
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Signed tests */
SHOULD_BE_LESS_THAN_SIGNED 0, 1
SHOULD_BE_LESS_THAN_SIGNED MIN1, 0
SHOULD_BE_LESS_THAN_SIGNED INT_MAX_MIN1, INT_MAX
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, INT_MAX
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, INT_MAX_MIN1
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX_PL1, INT_MAX
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX_PL1, INT_MAX_MIN1
SHOULD_BE_LESS_THAN_SIGNED -7, -6
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, NEG_INT_MAX_PL1
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, MIN1
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, 0
SHOULD_BE_GREATER_THAN_SIGNED 1, 0
SHOULD_BE_GREATER_THAN_SIGNED 0, MIN1
SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, INT_MAX_MIN1
SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, NEG_INT_MAX
SHOULD_BE_GREATER_THAN_SIGNED INT_MAX_MIN1, NEG_INT_MAX
SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, NEG_INT_MAX_PL1
SHOULD_BE_GREATER_THAN_SIGNED INT_MAX_MIN1, NEG_INT_MAX_PL1
SHOULD_BE_GREATER_THAN_SIGNED -6, -7
SHOULD_BE_GREATER_THAN_SIGNED NEG_INT_MAX_PL1, NEG_INT_MAX
SHOULD_BE_GREATER_THAN_SIGNED MIN1, NEG_INT_MAX
SHOULD_BE_GREATER_THAN_SIGNED 0, NEG_INT_MAX
/* See the immediate tests below. */
SHOULD_BE_LESS_THAN_SIGNED 0xFFFF7FFF, 0xFFFF8000
/* See the immediate tests below. */
SHOULD_BE_GREATER_THAN_SIGNED 0xFFFF8001, 0xFFFF8000
/* Signed tests, immediate */
SHOULD_BE_LESS_THAN_SIGNED_I 0, 1
SHOULD_BE_LESS_THAN_SIGNED_I -1, 0
SHOULD_BE_LESS_THAN_SIGNED_I -7, -6
SHOULD_BE_GREATER_THAN_SIGNED_I 0x00008000, 0x7FFF
SHOULD_BE_LESS_THAN_SIGNED_I 0xFFFFFFFF, 0x7FFF
/* 0x8000 gets sign-extended to 0xFFFF8000. */
SHOULD_BE_LESS_THAN_SIGNED_I 0xFFFF7FFF, 0x8000
/* 0x8000 gets sign-extended to 0xFFFF8000. */
SHOULD_BE_GREATER_THAN_SIGNED_I 0xFFFF8001, 0x8000
/* 0x8000 gets sign-extended to 0xFFFF8000. */
SHOULD_BE_GREATER_THAN_SIGNED_I 0x00008000, 0x8000
/* Unsigned tests */
SHOULD_BE_LESS_THAN_UNSIGNED 0, 1
SHOULD_BE_LESS_THAN_UNSIGNED UINT_MAX_MIN1, UINT_MAX
SHOULD_BE_GREATER_THAN_UNSIGNED 1, 0
SHOULD_BE_GREATER_THAN_UNSIGNED UINT_MAX, UINT_MAX_MIN1
SHOULD_BE_GREATER_THAN_UNSIGNED UINT_MAX, 0
SHOULD_BE_GREATER_THAN_UNSIGNED 0x80000001, 0x80000000
SHOULD_BE_LESS_THAN_UNSIGNED 0x80000000, 0x80000001
SHOULD_BE_GREATER_THAN_UNSIGNED 0x80000000, 0x7fffffff
SHOULD_BE_LESS_THAN_UNSIGNED 0x7fffffff, 0x80000000
SHOULD_BE_GREATER_THAN_UNSIGNED 0x7fffffff, 0x7ffffffe
SHOULD_BE_LESS_THAN_UNSIGNED 0x7ffffffe, 0x7fffffff
SHOULD_BE_LESS_THAN_UNSIGNED 0x2024fae0, 0xfef03220
/* Unsigned tests, immediate */
SHOULD_BE_LESS_THAN_UNSIGNED_I 0, 1
SHOULD_BE_GREATER_THAN_UNSIGNED_I 1, 0
SHOULD_BE_LESS_THAN_UNSIGNED_I SHRT_MAX - 1, SHRT_MAX
SHOULD_BE_GREATER_THAN_UNSIGNED_I SHRT_MAX , SHRT_MAX - 1
/* The sign extension produces unexpected results here. */
/* 0xFFFF gets sign-extended to 0xFFFFFFFF. */
SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFFFFFF - 1, 0xFFFF
/* 0x8000 gets sign-extended to 0xFFFF8000. */
SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFF7FFF, 0x8000
/* Equal tests. */
SHOULD_BE_EQUAL 0, 0
SHOULD_BE_EQUAL UINT_MAX, UINT_MAX
SHOULD_BE_EQUAL MIN1, UINT_MAX
SHOULD_BE_EQUAL INT_MAX, INT_MAX
SHOULD_BE_EQUAL NEG_INT_MAX, NEG_INT_MAX
/* Equal tests, immediate. Test the 16-to-32-bit sign extension. */
SHOULD_BE_EQUAL_I 0, 0
SHOULD_BE_EQUAL_I 0x00007FFF, 0x7FFF
SHOULD_BE_EQUAL_I 0xFFFF8000, 0x8000
SHOULD_BE_EQUAL_I 0xFFFFFFFF, 0xFFFF
/* Non-equal tests. */
SHOULDNT_BE_EQUAL 0, 1
SHOULDNT_BE_EQUAL UINT_MAX, INT_MAX
SHOULDNT_BE_EQUAL UINT_MAX, NEG_INT_MAX
SHOULDNT_BE_EQUAL MIN1, NEG_INT_MAX_PL1
SHOULDNT_BE_EQUAL INT_MAX, NEG_INT_MAX
SHOULDNT_BE_EQUAL NEG_INT_MAX_PL1, UINT_MAX_MIN1
/* Non-equal tests, immediate. Test the 16-to-32-bit sign
extension. */
SHOULDNT_BE_EQUAL_I 0x00008000, 0x8000
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
failed:
EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR
|
tactcomplabs/xbgas-binutils-gdb | 7,113 | sim/testsuite/or1k/ext.S | /* Tests the l.ext{b,h}{s,z} instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x0000007f);\n
# output: report(0x0000007f);\n
# output: report(0x00000053);\n
# output: report(0x00000053);\n
# output: report(0x0000ff53);\n
# output: report(0x00000053);\n
# output: report(0x00001234);\n
# output: report(0x00000034);\n
# output: report(0x000000ff);\n
# output: report(0xffffffff);\n
# output: report(0x00000080);\n
# output: report(0xffffff80);\n
# output: report(0x0000ff80);\n
# output: report(0xffffff80);\n
# output: report(0x00007f80);\n
# output: report(0xffffff80);\n
# output: report(0x00007fff);\n
# output: report(0xffffffff);\n
# output: report(0x0000007f);\n
# output: report(0x0000007f);\n
# output: report(0x00000053);\n
# output: report(0x00000053);\n
# output: report(0x0000ff53);\n
# output: report(0x00000053);\n
# output: report(0x00001234);\n
# output: report(0x00000034);\n
# output: report(0x000000ff);\n
# output: report(0x000000ff);\n
# output: report(0x00000080);\n
# output: report(0x00000080);\n
# output: report(0x0000ff80);\n
# output: report(0x00000080);\n
# output: report(0x00007f80);\n
# output: report(0x00000080);\n
# output: report(0x00007fff);\n
# output: report(0x000000ff);\n
# output: report(0x00007fff);\n
# output: report(0x00007fff);\n
# output: report(0x00005233);\n
# output: report(0x00005233);\n
# output: report(0xffff2f53);\n
# output: report(0x00002f53);\n
# output: report(0x12345678);\n
# output: report(0x00005678);\n
# output: report(0x0000ffff);\n
# output: report(0xffffffff);\n
# output: report(0x00008000);\n
# output: report(0xffff8000);\n
# output: report(0x0000ff80);\n
# output: report(0xffffff80);\n
# output: report(0x80008000);\n
# output: report(0xffff8000);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00007fff);\n
# output: report(0x00007fff);\n
# output: report(0x00005233);\n
# output: report(0x00005233);\n
# output: report(0xffff2f53);\n
# output: report(0x00002f53);\n
# output: report(0x12345678);\n
# output: report(0x00005678);\n
# output: report(0x0000ffff);\n
# output: report(0x0000ffff);\n
# output: report(0x00008000);\n
# output: report(0x00008000);\n
# output: report(0x0000ff80);\n
# output: report(0x0000ff80);\n
# output: report(0x80008000);\n
# output: report(0x00008000);\n
# output: report(0x7fffffff);\n
# output: report(0x0000ffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x7fff7fff);\n
# output: report(0x7fff7fff);\n
# output: report(0xffff7f7f);\n
# output: report(0xffff7f7f);\n
# output: report(0xffffff7f);\n
# output: report(0xffffff7f);\n
# output: report(0xffff7fff);\n
# output: report(0xffff7fff);\n
# output: report(0x7fff7f7f);\n
# output: report(0x7fff7f7f);\n
# output: report(0x12345678);\n
# output: report(0x12345678);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x7fff7fff);\n
# output: report(0x7fff7fff);\n
# output: report(0xffff7f7f);\n
# output: report(0xffff7f7f);\n
# output: report(0xffffff7f);\n
# output: report(0xffffff7f);\n
# output: report(0xffff7fff);\n
# output: report(0xffff7fff);\n
# output: report(0x7fff7f7f);\n
# output: report(0x7fff7f7f);\n
# output: report(0x12345678);\n
# output: report(0x12345678);\n
# output: exit(0)\n
#include "or1k-asm-test-env.h"
.macro CHECK_EXT insn, val, mask, high_mask
LOAD_IMMEDIATE r4, \val
REPORT_REG_TO_CONSOLE r4
\insn r5, r4
REPORT_REG_TO_CONSOLE r5
LOAD_IMMEDIATE r6, \mask
l.xori r7, r6, -1
l.and r8, r4, r6
l.and r9, r5, r6
l.sfne r8, r9
OR1K_DELAYED_NOP (l.bf ext_fail)
l.and r8, r5, r7
LOAD_IMMEDIATE r7, \high_mask
l.sfne r8, r7
OR1K_DELAYED_NOP (l.bf ext_fail)
.endm
#define CHECK_HIGH3_CLEAR(insn, val) CHECK_EXT insn, val, 0x000000ff, 0
#define CHECK_HIGH3_SET(val) CHECK_EXT l.extbs, val, 0x000000ff, 0xffffff00
#define CHECK_HIGH2_CLEAR(insn, val) CHECK_EXT insn, val, 0x0000ffff, 0
#define CHECK_HIGH2_SET(val) CHECK_EXT l.exths, val, 0x0000ffff, 0xffff0000
.macro CHECK_MOVE insn, val
LOAD_IMMEDIATE r4, \val
REPORT_REG_TO_CONSOLE r4
\insn r5, r4
REPORT_REG_TO_CONSOLE r5
l.sfne r5, r4
OR1K_DELAYED_NOP (l.bf ext_fail)
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.extbs */
CHECK_HIGH3_CLEAR ( l.extbs, 0x7f )
CHECK_HIGH3_CLEAR ( l.extbs, 0x53 )
CHECK_HIGH3_CLEAR ( l.extbs, 0xff53 )
CHECK_HIGH3_CLEAR ( l.extbs, 0x1234 )
CHECK_HIGH3_SET (0xff)
CHECK_HIGH3_SET (0x80)
CHECK_HIGH3_SET (0xff80)
CHECK_HIGH3_SET (0x7f80)
CHECK_HIGH3_SET (0x7fff)
/* Test l.extbz */
CHECK_HIGH3_CLEAR (l.extbz, 0x7f)
CHECK_HIGH3_CLEAR (l.extbz, 0x53)
CHECK_HIGH3_CLEAR (l.extbz, 0xff53)
CHECK_HIGH3_CLEAR (l.extbz, 0x1234)
CHECK_HIGH3_CLEAR (l.extbz, 0xff)
CHECK_HIGH3_CLEAR (l.extbz, 0x80)
CHECK_HIGH3_CLEAR (l.extbz, 0xff80)
CHECK_HIGH3_CLEAR (l.extbz, 0x7f80)
CHECK_HIGH3_CLEAR (l.extbz, 0x7fff)
/* Test l.exths */
CHECK_HIGH2_CLEAR (l.exths, 0x7fff)
CHECK_HIGH2_CLEAR (l.exths, 0x5233)
CHECK_HIGH2_CLEAR (l.exths, 0xffff2f53)
CHECK_HIGH2_CLEAR (l.exths, 0x12345678)
CHECK_HIGH2_SET (0xffff)
CHECK_HIGH2_SET (0x8000)
CHECK_HIGH2_SET (0xff80)
CHECK_HIGH2_SET (0x80008000)
CHECK_HIGH2_SET (0x7fffffff)
/* Test l.exthz */
CHECK_HIGH2_CLEAR (l.exthz, 0x7fff)
CHECK_HIGH2_CLEAR (l.exthz, 0x5233)
CHECK_HIGH2_CLEAR (l.exthz, 0xffff2f53)
CHECK_HIGH2_CLEAR (l.exthz, 0x12345678)
CHECK_HIGH2_CLEAR (l.exthz, 0xffff)
CHECK_HIGH2_CLEAR (l.exthz, 0x8000)
CHECK_HIGH2_CLEAR (l.exthz, 0xff80)
CHECK_HIGH2_CLEAR (l.exthz, 0x80008000)
CHECK_HIGH2_CLEAR (l.exthz, 0x7fffffff)
/* Test l.extws */
CHECK_MOVE l.extws, 0xffffffff
CHECK_MOVE l.extws, 0x7fffffff
CHECK_MOVE l.extws, 0x7fff7fff
CHECK_MOVE l.extws, 0xffff7f7f
CHECK_MOVE l.extws, 0xffffff7f
CHECK_MOVE l.extws, 0xffff7fff
CHECK_MOVE l.extws, 0x7fff7f7f
CHECK_MOVE l.extws, 0x12345678
/* Test l.extwz */
CHECK_MOVE l.extwz, 0xffffffff
CHECK_MOVE l.extwz, 0x7fffffff
CHECK_MOVE l.extwz, 0x7fff7fff
CHECK_MOVE l.extwz, 0xffff7f7f
CHECK_MOVE l.extwz, 0xffffff7f
CHECK_MOVE l.extwz, 0xffff7fff
CHECK_MOVE l.extwz, 0x7fff7f7f
CHECK_MOVE l.extwz, 0x12345678
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
ext_fail:
EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR
|
tactcomplabs/xbgas-binutils-gdb | 5,445 | sim/testsuite/or1k/mfspr.S | /* Tests instructions l.mfspr and l.mtspr.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000000);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00000000);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00000801);\n
# output: report(0x00002000);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002000);\n
# output: report(0x00000801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00000001);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00000800);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00000000);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00000801);\n
# output: report(0x00002000);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002000);\n
# output: report(0x00000801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00000001);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00000800);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-env.h"
#define MACLO_VAL 0xdeadbeef
/* A macro to carry out a test of l.mfspr.
MACLO (0x2801) is used as the SPR, since it can be read and
cleared using l.macrc and can be set using l.maci. spr_number
and immediate_val_to_or should be chosen to address this
register.
The value placed in the register is entirely arbitrary - we use
0xdeadbeef. */
.macro TEST_MFSPR spr_number, immediate_val_to_or
REPORT_IMMEDIATE_TO_CONSOLE \spr_number
REPORT_IMMEDIATE_TO_CONSOLE \immediate_val_to_or
/* Write MACLO_VAL to MACLO. */
l.macrc r2
LOAD_IMMEDIATE r2, MACLO_VAL
l.maci r2, 1
LOAD_IMMEDIATE r5, \spr_number
l.mfspr r4, r5, \immediate_val_to_or
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
/* A macro to carry out a test of l.mtspr
MACLO (0x2801) is used as the SPR, since it can be read and
cleared using l.macrc and can be set using l.maci. The
arguments spr_number and immediate_val_to_or should be chosen
to address this register.
The value placed in the register is entirely arbitrary - we use
0xdeadbeef. */
.macro TEST_MTSPR spr_number, immediate_val_to_or
REPORT_IMMEDIATE_TO_CONSOLE \spr_number
REPORT_IMMEDIATE_TO_CONSOLE \immediate_val_to_or
/* Clear MACLO */
l.macrc r2
LOAD_IMMEDIATE r4, MACLO_VAL
LOAD_IMMEDIATE r5, \spr_number
l.mtspr r5, r4, \immediate_val_to_or
/* Retrieve MACLO. */
l.macrc r4
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test the l.mfspr instruction with a range of operands. */
/* Move a test value using zero in the register. */
TEST_MFSPR SPR_VR, SPR_MACLO /* 0x0000, 0x2801 */
/* Move a test value using zero as the constant. */
TEST_MFSPR SPR_MACLO, SPR_VR /* 0x2801, 0x0000 */
/* Move a test value using non-zero in both register and constant. */
/* Some of these values will not give the correct result if OR
rather than ADD is used to determine the SPR address. */
TEST_MFSPR SPR_MACLO, SPR_MACLO /* 0x2801, 0x2801 */
TEST_MFSPR SPR_DMMUPR, SPR_ICCR /* 0x0801, 0x2000 */
TEST_MFSPR SPR_ICCR, SPR_DMMUPR /* 0x2000, 0x0801 */
TEST_MFSPR SPR_MACLO, SPR_UPR /* 0x2801, 0x0001 */
TEST_MFSPR SPR_DMMUCR, SPR_MACLO /* 0x0800, 0x2801 */
/* Test the l.mtspr instruction with a range of operands. */
/* Move a test value using zero in the register. */
TEST_MTSPR SPR_VR, SPR_MACLO /* 0x0000, 0x2801 */
/* Move a test value using zero as the constant. */
TEST_MTSPR SPR_MACLO, SPR_VR /* 0x2801, 0x0000 */
/* Move a test value using non-zero in both register and constant. */
/* Some of these values will not give the correct result if or
rather than add is used to determine the SPR address. */
TEST_MTSPR SPR_MACLO, SPR_MACLO /* 0x2801, 0x2801 */
TEST_MTSPR SPR_DMMUPR, SPR_ICCR /* 0x0801, 0x2000 */
TEST_MTSPR SPR_ICCR, SPR_DMMUPR /* 0x2000, 0x0801 */
TEST_MTSPR SPR_MACLO, SPR_UPR /* 0x2801, 0x0001 */
TEST_MTSPR SPR_DMMUCR, SPR_MACLO /* 0x0800, 0x2801 */
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 6,227 | sim/testsuite/or1k/or.S | /* Tests instructions l.or, l.ori.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x55555555);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x55555555);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xc4c70f07);\n
# output: report(0xccf7ff7f);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x38f0f83b);\n
# output: report(0xbbffffbb);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000ffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x0000aaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00005555);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00005555);\n
# output: report(0xaaaaffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f83);\n
# output: report(0x4c70ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f07);\n
# output: report(0x4c70ff7f);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000f83b);\n
# output: report(0xb38fffbb);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Always set OVE. We should never trigger an exception, even if
this bit is set. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test the l.or instruction with a range of operands. */
TEST_INST_I32_I32 l.or, 0x00000000, 0x00000000
TEST_INST_I32_I32 l.or, 0xffffffff, 0xffffffff
TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0x00000000
TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0xaaaaaaaa
TEST_INST_I32_I32 l.or, 0x55555555, 0x00000000
TEST_INST_I32_I32 l.or, 0x55555555, 0x55555555
TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0x55555555
TEST_INST_I32_I32 l.or, 0x4c70f07c, 0xb38f0f83
TEST_INST_I32_I32 l.or, 0x4c70f07c, 0xc4c70f07
TEST_INST_I32_I32 l.or, 0xb38f0f83, 0x38f0f83b
/* Test the l.ori instruction with a range of operands. */
TEST_INST_I32_I16 l.ori, 0x00000000, 0x0000
TEST_INST_I32_I16 l.ori, 0xffffffff, 0xffff
TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0x0000
TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0xaaaa
TEST_INST_I32_I16 l.ori, 0x55555555, 0x0000
TEST_INST_I32_I16 l.ori, 0x55555555, 0x5555
TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0x5555
TEST_INST_I32_I16 l.ori, 0x4c70f07c, 0x0f83
TEST_INST_I32_I16 l.ori, 0x4c70f07c, 0x0f07
TEST_INST_I32_I16 l.ori, 0xb38f0f83, 0xf83b
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 3,423 | sim/testsuite/or1k/fpu.S | /* Tests some basic fpu instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00007ab7);\n
# output: report(0xffffd8f0);\n
# output: report(0x46f56e00);\n
# output: report(0xc61c4000);\n
# output: report(0x00007ab7);\n
# output: report(0xffffd8f0);\n
# output: \n
# output: report(0xc0490e56);\n
# output: report(0xfffffffd);\n
# output: \n
# output: report(0x4e6b4bbb);\n
# output: \n
# output: report(0xbdc0be40);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: WARNING: ignoring fpu error caught in fast mode.\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Floating point exception. */
.org 0xd00
/* The handling is a bit dubious at present. We just patch the
instruction with l.nop and restart. This will go wrong in branch
delay slots. But we don't have those in this test. */
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw -4(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test lf.itof.s int to float conversion. Setting up:
* r10 31415.0f
* r12 -10000.0f
*/
l.ori r11, r0, 31415
l.ori r13, r0, -10000
l.movhi r15, 0xffff
l.or r13, r13, r15
REPORT_REG_TO_CONSOLE r11
REPORT_REG_TO_CONSOLE r13
lf.itof.s r10, r11
lf.itof.s r12, r13
REPORT_REG_TO_CONSOLE r10
REPORT_REG_TO_CONSOLE r12
/* Test lf.ftoi.s float to int conversion. */
lf.ftoi.s r11, r10
lf.ftoi.s r13, r12
REPORT_REG_TO_CONSOLE r11
REPORT_REG_TO_CONSOLE r13
PRINT_NEWLINE_TO_CONSOLE
/* Test lf.div.s divide 31415 by -1000 to get -pi. Setting up:
* r8 -3.1415f
*/
lf.div.s r8, r10, r12
REPORT_REG_TO_CONSOLE r8
lf.ftoi.s r11, r8
REPORT_REG_TO_CONSOLE r11
PRINT_NEWLINE_TO_CONSOLE
/* Test lf.mul.s multiply -pi x -10000 x 31415. Setting up:
* r6 986902225
*/
lf.mul.s r6, r8, r12
lf.mul.s r6, r6, r10
REPORT_REG_TO_CONSOLE r6
PRINT_NEWLINE_TO_CONSOLE
/* Test lf.rem.s remainder of 986902225 / -pi. */
lf.rem.s r2, r6, r8
REPORT_REG_TO_CONSOLE r2
PRINT_NEWLINE_TO_CONSOLE
/* Test lf.sfge.s set flag if r6 >= r10. */
lf.sfge.s r6, r10
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
/* Test raising an exception by dividing by 0. */
MOVE_FROM_SPR r2, SPR_FPCSR
l.ori r2, r2, 0x1
MOVE_TO_SPR SPR_FPCSR, r2
div0: lf.div.s r2, r8, r0
REPORT_EXCEPTION div0
PRINT_NEWLINE_TO_CONSOLE
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 27,149 | sim/testsuite/or1k/mac.S | /* Tests the MAC instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x0000000c);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x40000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000006);\n
# output: report(0x80000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x7ffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0x00000005);\n
# output: report(0xffffffff);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xfffffff9);\n
# output: report(0xffffffff);\n
# output: report(0xfffffff9);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x80000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x0000000c);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x40000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000006);\n
# output: report(0x80000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x7ffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0x00000005);\n
# output: report(0xffffffff);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xfffffff9);\n
# output: report(0xffffffff);\n
# output: report(0xfffffff9);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x80000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000006);\n
# output: report(0x7ffffffe);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x7ffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x0000000c);\n
# output: report(0x00000005);\n
# output: report(0xfffffffa);\n
# output: report(0x00000006);\n
# output: report(0xffffffff);\n
# output: report(0xfffffff9);\n
# output: report(0xfffffff9);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x80000000);\n
# output: report(0x80000006);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0xfffffffa);\n
# output: report(0x3fffffff);\n
# output: report(0xfffffffa);\n
# output: report(0xffffffff);\n
# output: report(0xfffffff4);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x80000002);\n
# output: report(0xffffffff);\n
# output: report(0x80000004);\n
# output: report(0x00000000);\n
# output: report(0x00000004);\n
# output: report(0x7ffffffe);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x80000001);\n
# output: report(0xffffffff);\n
# output: report(0x00000004);\n
# output: report(0xfffffffe);\n
# output: report(0x00000004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0xffffffff);\n
# output: report(0xfffffff9);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x0000000c);\n
# output: report(0x00000001);\n
# output: report(0x00000005);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000005);\n
# output: report(0x80000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x80000006);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0x80000000);\n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
.macro TEST_MACRC mac_hi, mac_lo, op1, op2
LOAD_IMMEDIATE r2, \mac_hi
MOVE_TO_SPR SPR_MACHI, r2
LOAD_IMMEDIATE r2, \mac_lo
MOVE_TO_SPR SPR_MACLO, r2
LOAD_IMMEDIATE r5, \op1
LOAD_IMMEDIATE r6, \op2
l.mac r5, r6
l.macrc r3
REPORT_REG_TO_CONSOLE r3
.endm
.macro TEST_MAC mac_hi, mac_lo, op1, op2
LOAD_IMMEDIATE r2, \mac_hi
MOVE_TO_SPR SPR_MACHI, r2
LOAD_IMMEDIATE r2, \mac_lo
MOVE_TO_SPR SPR_MACLO, r2
LOAD_IMMEDIATE r5, \op1
LOAD_IMMEDIATE r6, \op2
l.mac r5, r6
MOVE_FROM_SPR r3, SPR_MACHI
REPORT_REG_TO_CONSOLE r3
MOVE_FROM_SPR r3, SPR_MACLO
REPORT_REG_TO_CONSOLE r3
.endm
.macro TEST_MACI mac_hi, mac_lo, op1, op2_immediate
LOAD_IMMEDIATE r2, \mac_hi
MOVE_TO_SPR SPR_MACHI, r2
LOAD_IMMEDIATE r2, \mac_lo
MOVE_TO_SPR SPR_MACLO, r2
LOAD_IMMEDIATE r5, \op1
l.maci r5, \op2_immediate
MOVE_FROM_SPR r3, SPR_MACHI
REPORT_REG_TO_CONSOLE r3
MOVE_FROM_SPR r3, SPR_MACLO
REPORT_REG_TO_CONSOLE r3
.endm
.macro TEST_MSB mac_hi, mac_lo, op1, op2
LOAD_IMMEDIATE r2, \mac_hi
MOVE_TO_SPR SPR_MACHI, r2
LOAD_IMMEDIATE r2, \mac_lo
MOVE_TO_SPR SPR_MACLO, r2
LOAD_IMMEDIATE r5, \op1
LOAD_IMMEDIATE r6, \op2
l.msb r5, r6
MOVE_FROM_SPR r3, SPR_MACHI
REPORT_REG_TO_CONSOLE r3
MOVE_FROM_SPR r3, SPR_MACLO
REPORT_REG_TO_CONSOLE r3
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test the l.mac instruction. */
/* two small positive numbers */
/* MAC two small positive numbers on a zero total */
TEST_MAC 0x00000000, 0x00000000, 0x00000002, 0x00000003
/* MAC two small positive numbers on a small positive total */
TEST_MAC 0x00000000, 0x00000006, 0x00000002, 0x00000003,
/* MAC two small positive numbers on a moderate positive total */
TEST_MAC 0x00000000, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a large positive total */
TEST_MAC 0x3fffffff, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a small negative total */
TEST_MAC 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a moderate negative total */
TEST_MAC 0xffffffff, 0x00000000, 0x00000002, 0x00000003
/* MAC two small positive numbers on a large negative total */
TEST_MAC 0x80000000, 0x00000000, 0x00000002, 0x00000003
/* two moderate positive numbers */
/* MAC two moderate positive numbers on a zero total */
TEST_MAC 0x00000000, 0x00000000, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a small positive total */
TEST_MAC 0x00000000, 0x00000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a moderate positive total */
TEST_MAC 0x00000000, 0x80000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a large positive total */
TEST_MAC 0x7fffffff, 0x80000001, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a small negative total */
TEST_MAC 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a moderate negative total */
TEST_MAC 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a large negative total */
TEST_MAC 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe
/* two small negative numbers */
/* MAC two small negative numbers on a zero total */
TEST_MAC 0x00000000, 0x00000000, 0xfffffffe, 0xfffffffd
/* MAC two small negative numbers on a small positive total */
TEST_MAC 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd
/* MAC two small negative numbers on a small negative total */
TEST_MAC 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd
/* one small positive and one small negative */
/* MAC one small positive and one small negative number on a zero
total */
TEST_MAC 0x00000000, 0x00000000, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a small
positive total */
TEST_MAC 0x00000000, 0x0000000c, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a
moderate positive total */
TEST_MAC 0x00000001, 0x00000005, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a large
positive total */
TEST_MAC 0x7fffffff, 0xffffffff, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a small
negative total */
TEST_MAC 0xffffffff, 0xffffffff, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a
moderate negative total */
TEST_MAC 0xffffffff, 0x00000005, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a large
negative total */
TEST_MAC 0x80000000, 0x00000006, 0x00000002, 0xfffffffd
/* one moderate positive and one moderate negative number */
/* MAC one moderate positive and one moderate negative number on a
zero total */
TEST_MAC 0x00000000, 0x00000000, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
small positive total */
TEST_MAC 0x00000000, 0x00000006, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
moderate positive total */
TEST_MAC 0x00000000, 0x80000000, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
large positive total */
TEST_MAC 0x7fffffff, 0xffffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
small negative total */
TEST_MAC 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
moderate negative total */
TEST_MAC 0xffffffff, 0x7fffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
large negative total */
TEST_MAC 0x80000000, 0x80000000, 0x00008000, 0xffff0000
/* Test the l.maci instruction. */
/* two small positive numbers */
/* MAC two small positive numbers on a zero total */
TEST_MACI 0x00000000, 0x00000000, 0x00000002, 0x0003
/* MAC two small positive numbers on a small positive total */
TEST_MACI 0x00000000, 0x00000006, 0x00000002, 0x0003
/* MAC two small positive numbers on a moderate positive total */
TEST_MACI 0x00000000, 0xfffffffa, 0x00000002, 0x0003
/* MAC two small positive numbers on a large positive total */
TEST_MACI 0x3fffffff, 0xfffffffa, 0x00000002, 0x0003
/* MAC two small positive numbers on a small negative total */
TEST_MACI 0xffffffff, 0xfffffffa, 0x00000002, 0x0003
/* MAC two small positive numbers on a moderate negative total */
TEST_MACI 0xffffffff, 0x00000000, 0x00000002, 0x0003
/* MAC two small positive numbers on a large negative total */
TEST_MACI 0x80000000, 0x00000000, 0x00000002, 0x0003
/* two moderate positive numbers */
/* MAC two moderate positive numbers on a zero total */
TEST_MACI 0x00000000, 0x00000000, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a small positive total */
TEST_MACI 0x00000000, 0x00000002, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a moderate positive total */
TEST_MACI 0x00000000, 0x80000002, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a large positive total */
TEST_MACI 0x7fffffff, 0x80000001, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a small negative total */
TEST_MACI 0xffffffff, 0xffffffff, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a moderate negative total */
TEST_MACI 0xffffffff, 0x80000002, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a large negative total */
TEST_MACI 0xfffffffe, 0x80000002, 0x00010002, 0x7fff
/* two small negative numbers */
/* MAC two small negative numbers on a zero total */
TEST_MACI 0x00000000, 0x00000000, 0xfffffffe, 0xfffd
/* MAC two small negative numbers on a small positive total */
TEST_MACI 0x00000000, 0x00000006, 0xfffffffe, 0xfffd
/* MAC two small negative numbers on a small negative total */
TEST_MACI 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffd
/* one small positive and one small negative */
/* MAC one small positive and one small negative number on a zero
total */
TEST_MACI 0x00000000, 0x00000000, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a small
positive total */
TEST_MACI 0x00000000, 0x0000000c, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a
moderate positive total */
TEST_MACI 0x00000001, 0x00000005, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a large
positive total */
TEST_MACI 0x7fffffff, 0xffffffff, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a small
negative total */
TEST_MACI 0xffffffff, 0xffffffff, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a
moderate negative total */
TEST_MACI 0xffffffff, 0x00000005, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a large
negative total */
TEST_MACI 0x80000000, 0x00000006, 0x00000002, 0xfffd
/* one moderate positive and one moderate negative */
/* MAC one moderate positive and one moderate negative number on a
zero total */
TEST_MACI 0x00000000, 0x00000000, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
small positive total */
TEST_MACI 0x00000000, 0x00000006, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
moderate positive total */
TEST_MACI 0x00000000, 0x80000000, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
large positive total */
TEST_MACI 0x7fffffff, 0xffffffff, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
small negative total */
TEST_MACI 0xffffffff, 0xffffffff, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
moderate negative total */
TEST_MACI 0xffffffff, 0x7fffffff, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
large negative total */
TEST_MACI 0x80000000, 0x80000000, 0x00010000, 0x8000
/* Test the l.macrc instruction.
Note that these tests use the same input data as the ones for
l.mac above. The results are the same, but only the low 32-bits
are compared. */
/* two small positive numbers */
/* MAC two small positive numbers on a zero total */
TEST_MACRC 0x00000000, 0x00000000, 0x00000002, 0x00000003
/* MAC two small positive numbers on a small positive total */
TEST_MACRC 0x00000000, 0x00000006, 0x00000002, 0x00000003
/* MAC two small positive numbers on a moderate positive total */
TEST_MACRC 0x00000000, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a large positive total */
TEST_MACRC 0x3fffffff, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a small negative total */
TEST_MACRC 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a moderate negative total */
TEST_MACRC 0xffffffff, 0x00000000, 0x00000002, 0x00000003
/* MAC two small positive numbers on a large negative total */
TEST_MACRC 0x80000000, 0x00000000, 0x00000002, 0x00000003
/* two moderate positive numbers */
/* MAC two moderate positive numbers on a zero total */
TEST_MACRC 0x00000000, 0x00000000, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a small positive total */
TEST_MACRC 0x00000000, 0x00000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a moderate positive total */
TEST_MACRC 0x00000000, 0x80000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a large positive total */
TEST_MACRC 0x7fffffff, 0x80000001, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a small negative total */
TEST_MACRC 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a moderate negative total */
TEST_MACRC 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a large negative total */
TEST_MACRC 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe
/* two small negative numbers */
/* MAC two small negative numbers on a zero total */
TEST_MACRC 0x00000000, 0x00000000, 0xfffffffe, 0xfffffffd
/* MAC two small negative numbers on a small positive total */
TEST_MACRC 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd
/* MAC two small negative numbers on a small negative total */
TEST_MACRC 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd
/* one small positive and one small negative number */
/* MAC one small positive and one small negative number on a zero
total */
TEST_MACRC 0x00000000, 0x00000000, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a small
positive total */
TEST_MACRC 0x00000000, 0x0000000c, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a
moderate positive total */
TEST_MACRC 0x00000001, 0x00000005, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a large
positive total */
TEST_MACRC 0x7fffffff, 0xffffffff, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a small
negative total */
TEST_MACRC 0xffffffff, 0xffffffff, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a
moderate negative total */
TEST_MACRC 0xffffffff, 0x00000005, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a large
negative total */
TEST_MACRC 0x80000000, 0x00000006, 0x00000002, 0xfffffffd
/* one moderate positive and one moderate negative */
/* MAC one moderate positive and one moderate negative number on a
zero total */
TEST_MACRC 0x00000000, 0x00000000, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
small positive total */
TEST_MACRC 0x00000000, 0x00000006, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
moderate positive total */
TEST_MACRC 0x00000000, 0x80000000, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
large positive total */
TEST_MACRC 0x7fffffff, 0xffffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
small negative total */
TEST_MACRC 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
moderate negative total */
TEST_MACRC 0xffffffff, 0x7fffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
large negative total */
TEST_MACRC 0x80000000, 0x80000000, 0x00008000, 0xffff0000
/* Test the l.msb instruction. */
/* MSB two small positive numbers on a zero total */
TEST_MSB 0x00000000, 0x00000000, 0x00000002, 0x00000003
/* MSB two small positive numbers on a small positive total */
TEST_MSB 0x00000000, 0x0000000c, 0x00000002, 0x00000003
/* MSB two small positive numbers on a moderate positive total */
TEST_MSB 0x00000001, 0x00000000, 0x00000002, 0x00000003
/* MSB two small positive numbers on a large positive total */
TEST_MSB 0x40000000, 0x00000000, 0x00000002, 0x00000003
/* MSB two small positive numbers on a small negative total */
TEST_MSB 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003
/* MSB two small positive numbers on a moderate negative total */
TEST_MSB 0xffffffff, 0x00000005, 0x00000002, 0x00000003
/* MSB two small positive numbers on a large negative total */
TEST_MSB 0x80000000, 0x00000006, 0x00000002, 0x00000003
/* two moderate positive numbers */
/* MSB two moderate positive numbers on a zero total */
TEST_MSB 0x00000000, 0x00000000, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a small positive total */
TEST_MSB 0x00000000, 0x00000002, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a moderate positive total */
TEST_MSB 0x00000000, 0x80000002, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a large positive total */
TEST_MSB 0x7fffffff, 0x7ffffffd, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a small negative total */
TEST_MSB 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a moderate negative total */
TEST_MSB 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a large negative total */
TEST_MSB 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe
/* two small negative numbers */
/* MSB two small negative numbers on a zero total */
TEST_MSB 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd
/* MSB two small negative numbers on a small positive total */
TEST_MSB 0x00000000, 0x0000000c, 0xfffffffe, 0xfffffffd
/* MSB two small negative numbers on a small negative total */
TEST_MSB 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd
/* one small positive and one small negative number */
/* MSB one small positive and one small negative number on a zero
total */
TEST_MSB 0x00000000, 0x00000000, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a small
positive total */
TEST_MSB 0x00000000, 0x00000006, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a
moderate positive total */
TEST_MSB 0x00000000, 0xffffffff, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a large
positive total */
TEST_MSB 0x7fffffff, 0xfffffff9, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a small
negative total */
TEST_MSB 0xffffffff, 0xfffffff9, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a
moderate negative total */
TEST_MSB 0xfffffffe, 0xffffffff, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a large
negative total */
TEST_MSB 0x80000000, 0x00000000, 0x00000002, 0xfffffffd
/* one moderate positive and one moderate negative number */
/* MSB one moderate positive and one moderate negative number on a
zero total */
TEST_MSB 0x00000000, 0x00000000, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
small positive total */
TEST_MSB 0x00000000, 0x00000006, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
moderate positive total */
TEST_MSB 0x00000000, 0x80000000, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
large positive total */
TEST_MSB 0x7fffffff, 0x7fffffff, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
small negative total */
TEST_MSB 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
moderate negative total */
TEST_MSB 0xfffffffe, 0xffffffff, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
large negative total */
TEST_MSB 0x80000000, 0x00000000, 0x00008000, 0xffff0000
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 4,656 | sim/testsuite/or1k/ror.S | /* Tests instructions l.ror and l.rori.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x3b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0f83b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x671e1f07);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00002224);\n
# output: report(0x3b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00f789f0);\n
# output: report(0x0f83b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0x671e1f07);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x3b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0f83b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x671e1f07);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000024);\n
# output: report(0x3b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000030);\n
# output: report(0x0f83b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000003f);\n
# output: report(0x671e1f07);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-env.h"
.macro TEST_ROR op1, op2, res
/* Note that 'res' is not used here. We could stop using the
.TestResults file and use 'res' here instead. */
LOAD_IMMEDIATE r5, \op1
LOAD_IMMEDIATE r6, \op2
REPORT_REG_TO_CONSOLE r5
REPORT_REG_TO_CONSOLE r6
l.ror r4, r5, r6
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
.macro TEST_RORI op1, op2, res
/* Note that 'res' is not used here. We could stop using the
.TestResults file and use 'res' here instead. */
LOAD_IMMEDIATE r5, \op1
REPORT_REG_TO_CONSOLE r5
REPORT_IMMEDIATE_TO_CONSOLE \op2
l.rori r4, r5, \op2
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test the l.ror instruction. */
/* Rotate by zero */
TEST_ROR 0xb38f0f83, 0x00000000, 0xb38f0f83
/* Rotate by amounts in the 1 - 31 range. */
TEST_ROR 0xb38f0f83, 0x00000001, 0xd9c787c1
TEST_ROR 0xb38f0f83, 0x00000004, 0x3b38f0f8
TEST_ROR 0xb38f0f83, 0x00000010, 0x0f83b38f
TEST_ROR 0xb38f0f83, 0x0000001f, 0x671e1f07
/* Rotate by larger amounts - should be masked. */
TEST_ROR 0xb38f0f83, 0x00000021, 0xd9c787c1
TEST_ROR 0xb38f0f83, 0x00002224, 0x3b38f0f8
TEST_ROR 0xb38f0f83, 0x00f789f0, 0x0f83b38f
TEST_ROR 0xb38f0f83, 0xffffffff, 0x671e1f07
/* Test the l.rori instruction. */
/* Rotate by zero */
TEST_RORI 0xb38f0f83, 0x00000000, 0xb38f0f83
/* Rotate by amounts in the 1 - 31 range. */
TEST_RORI 0xb38f0f83, 0x01, 0xd9c787c1
TEST_RORI 0xb38f0f83, 0x04, 0x3b38f0f8
TEST_RORI 0xb38f0f83, 0x10, 0x0f83b38f
TEST_RORI 0xb38f0f83, 0x1f, 0x671e1f07
/* Rotate by larger amounts (32 - 63) - should be masked. */
TEST_RORI 0xb38f0f83, 0x21, 0xd9c787c1
TEST_RORI 0xb38f0f83, 0x24, 0x3b38f0f8
TEST_RORI 0xb38f0f83, 0x30, 0x0f83b38f
TEST_RORI 0xb38f0f83, 0x3f, 0x671e1f07
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 8,972 | sim/testsuite/or1k/div.S | /* Tests the divide instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x0000000c);\n
# output: report(0x00000003);\n
# output: report(0x00000004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000b);\n
# output: report(0x00000003);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0xfffffffd);\n
# output: report(0x00000004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff5);\n
# output: report(0xfffffffd);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000003);\n
# output: report(0xfffffffc);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff5);\n
# output: report(0x00000003);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffc);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000b);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000000);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000000);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0x00000003);\n
# output: report(0x00000004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000b);\n
# output: report(0x00000003);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff5);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000003);\n
# output: report(0x55555551);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff5);\n
# output: report(0x00000003);\n
# output: report(0x55555551);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000b);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Range exception. */
.org 0xb00
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw 0(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.div */
/* Divide two positive numbers and check rounding. Should set no
flags. */
TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000003 /* 12 / 3 = 4 */
TEST_INST_I32_I32 l.div, 0x0000000b, 0x00000003 /* 11 / 3 = 3 */
/* Divide two negative numbers and check rounding. Should set no
flags. */
TEST_INST_I32_I32 l.div, 0xfffffff4, 0xfffffffd
TEST_INST_I32_I32 l.div, 0xfffffff5, 0xfffffffd
/* Divide a negative number by a positive number and check
rounding. Should set no flags. */
TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000003
TEST_INST_I32_I32 l.div, 0xfffffff5, 0x00000003
/* Divide a positive number by a negative number and check
rounding. Should set no flags. */
TEST_INST_I32_I32 l.div, 0x0000000c, 0xfffffffd
TEST_INST_I32_I32 l.div, 0x0000000b, 0xfffffffd
/* Divide by zero. This will set the overflow flag. */
TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000000
TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000000
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Divide by zero. This will set the overflow flag and trigger an
exception. */
TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000000
TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.divu */
/* Divide two positive numbers and check rounding. Should set no
flags. */
TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000003
TEST_INST_I32_I32 l.divu, 0x0000000b, 0x00000003
/* Divide two numbers that would be negative under 2's complement
and check rounding. Should set no flags. */
TEST_INST_I32_I32 l.divu, 0xfffffff4, 0xfffffffd
TEST_INST_I32_I32 l.divu, 0xfffffff5, 0xfffffffd
/* Divide a number that would be negative under 2's complement by a
number that would be positive under 2's complement and check
rounding. This should set no flags. */
TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000003
TEST_INST_I32_I32 l.divu, 0xfffffff5, 0x00000003
/* Divide a number that would be positive under 2's complement by a
number that would be negative under 2's complement and check
rounding. This should set no flags. */
TEST_INST_I32_I32 l.divu, 0x0000000c, 0xfffffffd
TEST_INST_I32_I32 l.divu, 0x0000000b, 0xfffffffd
/* Divide by zero. This will set the carry flag. */
TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000000
TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000000
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Divide by zero. This will set the carry flag and trigger an
exception. */
TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000000
TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 8,100 | sim/testsuite/or1k/load.S | /* Tests the load and store instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0xdeadbeef);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0xdeadbeef);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xdeadbeef);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0xdeadbeef);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0x000000de);\n
# output: report(0x000000ad);\n
# output: report(0x000000be);\n
# output: report(0x000000ef);\n
# output: report(0x000000ef);\n
# output: report(0x000000be);\n
# output: report(0x000000ad);\n
# output: report(0x000000de);\n
# output: report(0xffffffde);\n
# output: report(0xffffffad);\n
# output: report(0xffffffbe);\n
# output: report(0xffffffef);\n
# output: report(0xffffffef);\n
# output: report(0xffffffbe);\n
# output: report(0xffffffad);\n
# output: report(0xffffffde);\n
# output: report(0x0000dead);\n
# output: report(0x0000beef);\n
# output: report(0x0000beef);\n
# output: report(0x0000dead);\n
# output: report(0xffffdead);\n
# output: report(0xffffbeef);\n
# output: report(0xffffbeef);\n
# output: report(0xffffdead);\n
# output: report(0xa1a2a3a4);\n
# output: report(0xb4b3b2b1);\n
# output: report(0x81828384);\n
# output: report(0x53545152);\n
# output: report(0xa0b0c0d0);\n
# output: report(0xa1b1c1d1);\n
# output: report(0xa3b3c3d3);\n
# output: report(0xa2b2c2d2);\n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
.macro TEST_LW opcode, label, offset
LOAD_IMMEDIATE r5, \label
\opcode r4, \offset(r5)
REPORT_REG_TO_CONSOLE r4
.endm
STANDARD_TEST_ENVIRONMENT
.section .rodata
.balign 4
50: .word 0xdeadbeef
51: .word 0x00000000
52: .word 0x7fffffff
53: .word 0x80000000
54: .word 0xffffffff
.section .data
.balign 4
buffer1: .word 0x00000000
buffer2: .word 0x00000000
buffer3: .word 0x00000000
buffer4: .word 0x00000000
buffer5:
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test instruction l.lws */
/* Load with zero offset. */
TEST_LW l.lws 50b, 0
TEST_LW l.lws 51b, 0
TEST_LW l.lws 52b, 0
TEST_LW l.lws 53b, 0
TEST_LW l.lws 54b, 0
/* Load with positive offset. */
TEST_LW l.lws 50b, 4
TEST_LW l.lws 50b, 8
TEST_LW l.lws 50b, 12
TEST_LW l.lws 50b, 16
/* Load with negative offset. */
TEST_LW l.lws 54b, -16
TEST_LW l.lws 54b, -12
TEST_LW l.lws 54b, -8
TEST_LW l.lws 54b, -4
/* TODO: add here test cases to cover unaligned memory accesses
with l.lws. */
/* Test instruction l.lwz */
/* Load with zero offset. */
TEST_LW l.lwz 50b, 0
TEST_LW l.lwz 51b, 0
TEST_LW l.lwz 52b, 0
TEST_LW l.lwz 53b, 0
TEST_LW l.lwz 54b, 0
/* Load with positive offset. */
TEST_LW l.lwz 50b, 4
TEST_LW l.lwz 50b, 8
TEST_LW l.lwz 50b, 12
TEST_LW l.lwz 50b, 16
/* Load with negative offset. */
TEST_LW l.lwz 54b, -16
TEST_LW l.lwz 54b, -12
TEST_LW l.lwz 54b, -8
TEST_LW l.lwz 54b, -4
/* TODO: add here test cases to cover unaligned memory accesses
with l.lwz. */
/* Test instruction l.lbz */
/* Read data at label 50, forwards, byte by byte. */
LOAD_IMMEDIATE r5, 50b
l.lbz r4, 0(r5)
REPORT_REG_TO_CONSOLE r4
l.lbz r4, 1(r5)
REPORT_REG_TO_CONSOLE r4
l.lbz r4, 2(r5)
REPORT_REG_TO_CONSOLE r4
l.lbz r4, 3(r5)
REPORT_REG_TO_CONSOLE r4
/* Read data at label 50, backwards, byte by byte. */
LOAD_IMMEDIATE r31, 51b
l.lbz r3, -1(r31)
REPORT_REG_TO_CONSOLE r3
l.lbz r3, -2(r31)
REPORT_REG_TO_CONSOLE r3
l.lbz r3, -3(r31)
REPORT_REG_TO_CONSOLE r3
l.lbz r3, -4(r31)
REPORT_REG_TO_CONSOLE r3
/* Test instruction l.lbs */
/* Read data at label 50, forwards, byte by byte. */
LOAD_IMMEDIATE r5, 50b
l.lbs r4, 0(r5)
REPORT_REG_TO_CONSOLE r4
l.lbs r4, 1(r5)
REPORT_REG_TO_CONSOLE r4
l.lbs r4, 2(r5)
REPORT_REG_TO_CONSOLE r4
l.lbs r4, 3(r5)
REPORT_REG_TO_CONSOLE r4
/* Read data at label 50, backwards, byte by byte. */
LOAD_IMMEDIATE r31, 51b
l.lbs r3, -1(r31)
REPORT_REG_TO_CONSOLE r3
l.lbs r3, -2(r31)
REPORT_REG_TO_CONSOLE r3
l.lbs r3, -3(r31)
REPORT_REG_TO_CONSOLE r3
l.lbs r3, -4(r31)
REPORT_REG_TO_CONSOLE r3
/* Test instruction l.lhz */
/* Read data at label 50, forwards, half-word by half-word. */
LOAD_IMMEDIATE r5, 50b
l.lhz r4, 0(r5)
REPORT_REG_TO_CONSOLE r4
l.lhz r4, 2(r5)
REPORT_REG_TO_CONSOLE r4
/* Read data at label 50, backwards, half-word by half-word. */
LOAD_IMMEDIATE r31, 51b
l.lhz r3, -2(r31)
REPORT_REG_TO_CONSOLE r3
l.lhz r3, -4(r31)
REPORT_REG_TO_CONSOLE r3
/* TODO: add here test cases to cover unaligned memory accesses
with l.lhz. */
/* Test instruction l.lhs */
/* Read data at label 50, forwards, half-word by half-word. */
LOAD_IMMEDIATE r5, 50b
l.lhs r4, 0(r5)
REPORT_REG_TO_CONSOLE r4
l.lhs r4, 2(r5)
REPORT_REG_TO_CONSOLE r4
/* Read data at label 50, backwards, half-word by half-word. */
LOAD_IMMEDIATE r31, 51b
l.lhs r3, -2(r31)
REPORT_REG_TO_CONSOLE r3
l.lhs r3, -4(r31)
REPORT_REG_TO_CONSOLE r3
/* TODO: add here test cases to cover unaligned memory accesses
with l.lhs. */
/* Test instruction l.sb */
/* Write 32-bits forwards, byte-to-byte. */
LOAD_IMMEDIATE r5, buffer1
LOAD_IMMEDIATE r10, 0xA1
LOAD_IMMEDIATE r11, 0xA2
LOAD_IMMEDIATE r12, 0xA3
LOAD_IMMEDIATE r13, 0xA4
l.sb 0(r5), r10
l.sb 1(r5), r11
l.sb 2(r5), r12
l.sb 3(r5), r13
l.lwz r3, 0(r5)
REPORT_REG_TO_CONSOLE r3
/* Write 32-bits backwards, byte-to-byte. */
LOAD_IMMEDIATE r6, buffer2
LOAD_IMMEDIATE r10, 0xB1
LOAD_IMMEDIATE r11, 0xB2
LOAD_IMMEDIATE r12, 0xB3
LOAD_IMMEDIATE r13, 0xB4
l.sb -1(r6), r10
l.sb -2(r6), r11
l.sb -3(r6), r12
l.sb -4(r6), r13
l.lwz r3, 0(r5)
REPORT_REG_TO_CONSOLE r3
/* TODO: add here test cases to cover unaligned memory accesses
with l.sb. */
/* Test instruction l.sh */
/* Write 32-bits forwards, one half-word at a time. */
LOAD_IMMEDIATE r5, buffer1
LOAD_IMMEDIATE r10, 0x8182
LOAD_IMMEDIATE r11, 0x8384
l.sh 0(r5), r10
l.sh 2(r5), r11
l.lwz r3, 0(r5)
REPORT_REG_TO_CONSOLE r3
/* Write 32-bits backwards, one half-word at a time. */
LOAD_IMMEDIATE r6, buffer2
LOAD_IMMEDIATE r10, 0x5152
LOAD_IMMEDIATE r11, 0x5354
l.sh -2(r6), r10
l.sh -4(r6), r11
l.lwz r3, 0(r5)
REPORT_REG_TO_CONSOLE r3
/* TODO: add here test cases to cover unaligned memory accesses
with l.sh. */
/* Test instruction l.sw */
LOAD_IMMEDIATE r5, buffer1
LOAD_IMMEDIATE r6, buffer5
LOAD_IMMEDIATE r10, 0xA0B0C0D0
LOAD_IMMEDIATE r11, 0xA1B1C1D1
LOAD_IMMEDIATE r12, 0xA2B2C2D2
LOAD_IMMEDIATE r13, 0xA3B3C3D3
l.sw 0(r5), r10
l.sw 4(r5), r11
l.sw -4(r6), r12
l.sw -8(r6), r13
TEST_LW l.lwz buffer1, 0
TEST_LW l.lwz buffer2, 0
TEST_LW l.lwz buffer3, 0
TEST_LW l.lwz buffer4, 0
/* TODO: add here test cases to cover unaligned memory accesses
with l.sw. */
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 6,250 | sim/testsuite/or1k/and.S | /* Tests instructions l.and, l.andi.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x55555555);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xc4c70f07);\n
# output: report(0x44400004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x38f0f83b);\n
# output: report(0x30800803);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000ffff);\n
# output: report(0x0000ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x0000aaaa);\n
# output: report(0x0000aaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00005555);\n
# output: report(0x00005555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00005555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f83);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f07);\n
# output: report(0x00000004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000f83b);\n
# output: report(0x00000803);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Always set OVE. We should never trigger an exception, even if
this bit is set. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test the l.and instruction with a range of operands. */
TEST_INST_I32_I32 l.and, 0x00000000, 0x00000000
TEST_INST_I32_I32 l.and, 0xffffffff, 0xffffffff
TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0x00000000
TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0xaaaaaaaa
TEST_INST_I32_I32 l.and, 0x55555555, 0x00000000
TEST_INST_I32_I32 l.and, 0x55555555, 0x55555555
TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0x55555555
TEST_INST_I32_I32 l.and, 0x4c70f07c, 0xb38f0f83
TEST_INST_I32_I32 l.and, 0x4c70f07c, 0xc4c70f07
TEST_INST_I32_I32 l.and, 0xb38f0f83, 0x38f0f83b
/* Test the l.andi instruction with a range of operands. */
TEST_INST_I32_I16 l.andi, 0x00000000, 0x0000
TEST_INST_I32_I16 l.andi, 0xffffffff, 0xffff
TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0x0000
TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0xaaaa
TEST_INST_I32_I16 l.andi, 0x55555555, 0x0000
TEST_INST_I32_I16 l.andi, 0x55555555, 0x5555
TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0x5555
TEST_INST_I32_I16 l.andi, 0x4c70f07c, 0x0f83
TEST_INST_I32_I16 l.andi, 0x4c70f07c, 0x0f07
TEST_INST_I32_I16 l.andi, 0xb38f0f83, 0xf83b
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 20,517 | sim/testsuite/or1k/add.S | /* Tests instructions l.add, l.addc, l.addi and l.addic.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x3fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x40000000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xc0000000);\n
# output: report(0xc0000000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xbfffffff);\n
# output: report(0xbfffffff);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x40000000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xbfffffff);\n
# output: report(0xbfffffff);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x3fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x3fffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x40000000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xc0000000);\n
# output: report(0xc0000000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xc0000000);\n
# output: report(0xbfffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xbfffffff);\n
# output: report(0xbfffffff);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x40000000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x3fffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xbfffffff);\n
# output: report(0xbfffffff);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000fffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fff8000);\n
# output: report(0x00007fff);\n
# output: report(0x7fffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffc000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80008000);\n
# output: report(0x00008000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80007fff);\n
# output: report(0x00008000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffc000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000fffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80007fff);\n
# output: report(0x00008000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000fffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fff8000);\n
# output: report(0x00007fff);\n
# output: report(0x7fffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fff8000);\n
# output: report(0x00007fff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffc000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x0000ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80008000);\n
# output: report(0x00008000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80007fff);\n
# output: report(0x00008000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80007fff);\n
# output: report(0x00008000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffc000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x7fffc000);\n
# output: report(0x00003fff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000fffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x0000ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80007fff);\n
# output: report(0x00008000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Range exception. */
.org 0xb00
/* The handling is a bit dubious at present. We just patch the
instruction with l.nop and restart. This will go wrong in branch
delay slots. But we don't have those in this test. */
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw 0(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.add */
/* Add two small positive numbers */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 1, 2
/* The carry flag should be ignored. */
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.add, 1, 2
/* Add two small negative numbers, which should set the carry flag
but not the overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, -1, -2
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \
0x3fffffff
/* Add two large positive numbers. Should set the overflow, but
not the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \
0x40000000
/* Add two quite large negative numbers. Should set the carry, but
not the overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, -1073741824, \
-1073741824 /* -1073741824 = 0xC0000000 */
/* Add two large negative numbers. Should set both the overflow
and carry flags. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xbfffffff, \
0xbfffffff
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \
0x40000000
/* Check that a carry alone does not cause a RANGE Exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xffffffff, \
0xfffffffe
/* Check that carry and overflow together cause an exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xbfffffff, \
0xbfffffff
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.addc */
/* Add two small positive numbers */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 1, 2
/* Add two small negative numbers. Sets the carry flag but not the
overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1, -2
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \
0x3fffffff
/* Add two quite large positive numbers with a carry in. Should
set the overflow but not the carry flag. */
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x40000000, \
0x3fffffff
/* Add two large positive numbers. Should set the overflow, but
not the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \
0x40000000
/* Add the largest unsigned value to zero with a carry. This
potentially can break a simplistic test for carry that does not
consider the carry flag properly. Do it both ways around. */
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, -1, 0
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0, -1
/* Add two quite large negative numbers. Should set the carry, but
not the overflow flag. Here -1073741824 is 0xC0000000. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1073741824, \
-1073741824
/* Add two quite large negative numbers that would overflow, with a
carry that just avoids the overflow. Should set the carry, but
not the overflow flag. Here -1073741824 is 0xC0000000 and
-1073741825 is 0xBFFFFFFF. */
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, -1073741824, \
-1073741825
/* Add two large negative numbers. Should set both the overflow
and carry flags. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1073741825, \
-1073741825
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception, even when
it is the carry that causes the overflow. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \
0x40000000
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x40000000, \
0x3fffffff
/* Check that a carry alone does not cause a RANGE Exception, even
when it is the carry that causes the overflow. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0xffffffff, \
0xfffffffe
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x00000000, \
0xffffffff
/* Check that carry and overflow together cause an exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0xbfffffff, \
0xbfffffff
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.addi */
/* Add two small positive numbers */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 1, 2
/* Check carry in is ignored. */
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addi, 1, 2
/* Add two small negative numbers. Sets the carry flag but not the
overflow flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0xffffffff, \
0xfffe
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fff8000, \
0x7fff
/* Add two large positive numbers. Should set the overflow, but
not the carry flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fffc000, \
0x4000
/* Add two quite large negative numbers. Should set the carry, but
not the overflow flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80008000, \
0x8000
/* Add two large negative numbers. Should set both the overflow
and carry flags. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80007fff, \
0x8000
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fffc000, \
0x4000
/* Check that a carry alone does not cause a RANGE Exception. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0xffffffff, \
0xfffe
/* Check that carry and overflow together cause an exception. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80007fff, \
0x8000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.addi */
/* Add two small positive numbers */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 1, 2
/* Add two small negative numbers. Sets the carry flag but not the
overflow flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0xffffffff, \
0xfffe
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fff8000, \
0x7fff
/* Add two quite large positive numbers with a carry in. Should
set the overflow but not the carry flag. */
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x7fff8000, 0x7fff
/* Add two large positive numbers. Should set the overflow, but
not the carry flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fffc000, \
0x4000
/* Add the largest unsigned value to zero with a carry. This
potentially can break a simplistic test for carry that does not
consider the carry flag properly. Do it both ways around. */
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0xffffffff, 0x0000
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x00000000, 0xffff
/* Add two quite large negative numbers. Should set the carry, but
not the overflow flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80008000, \
0x8000
/* Add two quite large negative numbers that would overflow, with a
carry that just avoids the overflow. This should set the carry,
but not the overflow flag. */
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x80007fff, 0x8000
/* Add two large negative numbers. Should set both the overflow
and carry flags. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80007fff, \
0x8000
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception, even when
it is the carry that causes the overflow. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fffc000, \
0x4000
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x7fffc000, 0x3fff
/* Check that a carry alone does not cause a RANGE Exception, even
when it is the carry that causes the overflow. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0xffffffff, \
0xfffe
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x00000000, 0xffff
/* Check that carry and overflow together cause an exception. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80007fff, \
0x8000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 4,321 | sim/testsuite/or1k/fpu64a32.S | /* Tests some basic fpu instructions.
Copyright (C) 2019-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x400921f9);\n
# output: report(0xf01b866e);\n
# output: report(0x4005bf09);\n
# output: report(0x95aaf790);\n
# output: report(0x00000000);\n
# output: report(0x00001234);\n
# output: \n
# output: report(0x40b23400);\n
# output: report(0x00000000);\n
# output: report(0x40b23400);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40177081);\n
# output: report(0xc2e33eff);\n
# output: report(0x400921f9);\n
# output: report(0xf01b866e);\n
# output: \n
# output: report(0x40211456);\n
# output: report(0x587dfabf);\n
# output: report(0x400921f9);\n
# output: report(0xf01b866d);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: WARNING: ignoring fpu error caught in fast mode.\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Floating point exception. */
.org 0xd00
/* The handling is a bit dubious at present. We just patch the
instruction with l.nop and restart. This will go wrong in branch
delay slots. But we don't have those in this test. */
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw -4(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .data
.align 4
.type pi, @object
.size pi, 8
anchor:
pi:
.double 3.14159
.type e, @object
.size e, 8
e:
.double 2.71828
.type large, @object
.size large, 8
large:
.long 0
.long 0x1234
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test lf.itof.d int to double conversion. Setting up:
* r11 pointer to data
* r12,r13 pi as double
* r14,r15 e as double
* r16,r17 a long long
*/
l.ori r11, r0, ha(anchor)
l.addi r11, r11, lo(anchor)
l.lwz r12, 0(r11)
l.lwz r13, 4(r11)
l.lwz r14, 8(r11)
l.lwz r15, 12(r11)
l.lwz r16, 16(r11)
l.lwz r18, 20(r11)
/* Output to ensure we loaded it correctly. */
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
REPORT_REG_TO_CONSOLE r14
REPORT_REG_TO_CONSOLE r15
REPORT_REG_TO_CONSOLE r16
REPORT_REG_TO_CONSOLE r18
PRINT_NEWLINE_TO_CONSOLE
/* Convert the big long to a double. */
lf.itof.d r16,r18, r16,r18
REPORT_REG_TO_CONSOLE r16
REPORT_REG_TO_CONSOLE r18
/* Convert the double back to a long, it should match before. */
lf.ftoi.d r16,r18, r16,r18
lf.itof.d r16,r18, r16,r18
REPORT_REG_TO_CONSOLE r16
REPORT_REG_TO_CONSOLE r18
PRINT_NEWLINE_TO_CONSOLE
/* Add and subtract some double values. */
lf.add.d r12,r13, r12,r13, r14,r15
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
lf.sub.d r12,r13, r12,r13, r14,r15
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
PRINT_NEWLINE_TO_CONSOLE
/* Multiply and divide double values. */
lf.mul.d r12,r13, r12,r13, r14,r15
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
lf.div.d r12,r13, r12,r13, r14,r15
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
PRINT_NEWLINE_TO_CONSOLE
/* Test lf.sfge.s set flag if r6 >= r10. */
lf.sfge.d r12,r13, r14,r15
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
/* Test raising an exception by dividing by 0. */
MOVE_FROM_SPR r2, SPR_FPCSR
l.ori r2, r2, 0x1
MOVE_TO_SPR SPR_FPCSR, r2
div0: lf.div.d r2,r3, r12,r13, r0,r1
REPORT_EXCEPTION div0
PRINT_NEWLINE_TO_CONSOLE
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 2,631 | sim/testsuite/or1k/find.S | /* Tests the find instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x00000020);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000002);\n
# output: \n
# output: report(0x00018000);\n
# output: report(0x00000010);\n
# output: \n
# output: report(0xc0000000);\n
# output: report(0x0000001f);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x00000020);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x0000001f);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000020);\n
# output: \n
# output: report(0x00018000);\n
# output: report(0x00000011);\n
# output: \n
# output: report(0xc0000000);\n
# output: report(0x00000020);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
.macro TEST_FIND opcode, operand
LOAD_IMMEDIATE r5, \operand
REPORT_REG_TO_CONSOLE r5
\opcode r4, r5
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.ff1 */
TEST_FIND l.ff1, 0x00000001
TEST_FIND l.ff1, 0x80000000
TEST_FIND l.ff1, 0x55555555
TEST_FIND l.ff1, 0xaaaaaaaa
TEST_FIND l.ff1, 0x00018000
TEST_FIND l.ff1, 0xc0000000
TEST_FIND l.ff1, 0x00000000
/* Test l.fl1 */
TEST_FIND l.fl1, 0x00000001
TEST_FIND l.fl1, 0x80000000
TEST_FIND l.fl1, 0x55555555
TEST_FIND l.fl1, 0xaaaaaaaa
TEST_FIND l.fl1, 0x00018000
TEST_FIND l.fl1, 0xc0000000
TEST_FIND l.fl1, 0x00000000
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 6,252 | sim/testsuite/or1k/xor.S | /* Tests instructions l.xor, l.xori.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x55555555);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xc4c70f07);\n
# output: report(0x88b7ff7b);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x38f0f83b);\n
# output: report(0x8b7ff7b8);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x0000aaaa);\n
# output: report(0x55550000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00005555);\n
# output: report(0x55550000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00005555);\n
# output: report(0xaaaaffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f83);\n
# output: report(0x4c70ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f07);\n
# output: report(0x4c70ff7b);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000f83b);\n
# output: report(0x4c70f7b8);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Always set OVE. We should never trigger an exception, even if
this bit is set. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test the l.xor instruction with a range of operands. */
TEST_INST_I32_I32 l.xor, 0x00000000, 0x00000000
TEST_INST_I32_I32 l.xor, 0xffffffff, 0xffffffff
TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0x00000000
TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0xaaaaaaaa
TEST_INST_I32_I32 l.xor, 0x55555555, 0x00000000
TEST_INST_I32_I32 l.xor, 0x55555555, 0x55555555
TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0x55555555
TEST_INST_I32_I32 l.xor, 0x4c70f07c, 0xb38f0f83
TEST_INST_I32_I32 l.xor, 0x4c70f07c, 0xc4c70f07
TEST_INST_I32_I32 l.xor, 0xb38f0f83, 0x38f0f83b
/* Test the l.xori instruction with a range of operands. */
TEST_INST_I32_I16 l.xori, 0x00000000, 0x0000
TEST_INST_I32_I16 l.xori, 0xffffffff, 0xffff
TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0x0000
TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0xaaaa
TEST_INST_I32_I16 l.xori, 0x55555555, 0x0000
TEST_INST_I32_I16 l.xori, 0x55555555, 0x5555
TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0x5555
TEST_INST_I32_I16 l.xori, 0x4c70f07c, 0x0f83
TEST_INST_I32_I16 l.xori, 0x4c70f07c, 0x0f07
TEST_INST_I32_I16 l.xori, 0xb38f0f83, 0xf83b
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 2,315 | sim/testsuite/or1k/fpu-unordered.S | /* Tests some basic unordered fpu compare instructions.
Copyright (C) 2019-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x40490fd0);\n
# output: report(0x402df84d);\n
# output: report(0x7fc00000);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .data
.align 4
.type pi, @object
.size pi, 4
anchor:
pi:
.float 3.14159
.type e, @object
.size e, 4
e:
.float 2.71828
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test unordered float comparisons. Setting up:
* r11 pointer to data
* r12 pi as float
* r13 e as float
* r16 nan as float
*/
l.ori r11, r0, ha(anchor)
l.addi r11, r11, lo(anchor)
l.lwz r12, 0(r11)
l.lwz r13, 4(r11)
/* Make a NaN. */
lf.sub.s r16, r13, r13
lf.div.s r16, r16, r16
/* Output to ensure we loaded it correctly. */
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
REPORT_REG_TO_CONSOLE r16
PRINT_NEWLINE_TO_CONSOLE
lf.sfuge.s r12, r13
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
lf.sfun.s r12, r13
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
lf.sfun.s r12, r16
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
lf.sfueq.s r12, r12
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
tactcomplabs/xbgas-binutils-gdb | 1,283 | sim/testsuite/msp430/mpyull_hwmult.s | # Test that unsigned widening multiplication of 32-bit operands to produce a
# 64-bit result is simulated correctly, when using 32-bit or F5series hardware
# multiply functionality.
# 0xffff fffc * 0x2 = 0x1 ffff fff8
# mach: msp430
# 32-bit hwmult register addresses
.set MPY32L, 0x0140
.set MPY32H, 0x0142
.set OP2L, 0x0150
.set OP2H, 0x0152
.set RES0, 0x0154
.set RES1, 0x0156
.set RES2, 0x0158
.set RES3, 0x015A
# F5series hwmult register addresses
.set MPY32L_F5, 0x04D0
.set MPY32H_F5, 0x04D2
.set OP2L_F5, 0x04E0
.set OP2H_F5, 0x04E2
.set RES0_F5, 0x04E4
.set RES1_F5, 0x04E6
.set RES2_F5, 0x04E8
.set RES3_F5, 0x04EA
.include "testutils.inc"
start
; Test 32bit hwmult
MOV.W #2, &MPY32L ; Load operand 1 Low into multiplier
MOV.W #0, &MPY32H ; Load operand 1 High into multiplier
MOV.W #-4, &OP2L ; Load operand 2 Low into multiplier
MOV.W #-1, &OP2H ; Load operand 2 High, trigger MPY
CMP.W #-8, &RES0 { JNE .L5
CMP.W #-1, &RES1 { JNE .L5
CMP.W #1, &RES2 { JNE .L5
CMP.W #0, &RES3 { JNE .L5
; Test f5series hwmult
MOV.W #2, &MPY32L_F5
MOV.W #0, &MPY32H_F5
MOV.W #-4, &OP2L_F5
MOV.W #-1, &OP2H_F5
CMP.W #-8, &RES0_F5 { JNE .L5
CMP.W #-1, &RES1_F5 { JNE .L5
CMP.W #1, &RES2_F5 { JNE .L5
CMP.W #0, &RES3_F5 { JEQ .L6
.L5:
fail
.L6:
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,642 | gold/testsuite/retain_1.s | .global discard0
.section .bss.discard0,"aw"
.type discard0, %object
discard0:
.zero 2
.global discard1
.section .bss.discard1,"aw"
.type discard1, %object
discard1:
.zero 2
.global discard2
.section .data.discard2,"aw"
.type discard2, %object
discard2:
.word 1
.section .bss.sdiscard0,"aw"
.type sdiscard0, %object
sdiscard0:
.zero 2
.section .bss.sdiscard1,"aw"
.type sdiscard1, %object
sdiscard1:
.zero 2
.section .data.sdiscard2,"aw"
.type sdiscard2, %object
sdiscard2:
.word 1
.section .text.fndiscard0,"ax"
.global fndiscard0
.type fndiscard0, %function
fndiscard0:
.word 0
.global retain0
.section .bss.retain0,"awR"
.type retain0, %object
retain0:
.zero 2
.global retain1
.section .bss.retain1,"awR"
.type retain1, %object
retain1:
.zero 2
.global retain2
.section .data.retain2,"awR"
.type retain2, %object
retain2:
.word 1
.section .bss.sretain0,"awR"
.type sretain0, %object
sretain0:
.zero 2
.section .bss.sretain1,"awR"
.type sretain1, %object
sretain1:
.zero 2
.section .data.sretain2,"aRw"
.type sretain2, %object
sretain2:
.word 1
.section .text.fnretain1,"Rax"
.global fnretain1
.type fnretain1, %function
fnretain1:
.word 0
.section .text.fndiscard2,"ax"
.global fndiscard2
.type fndiscard2, %function
fndiscard2:
.word 0
.section .bss.lsretain0,"awR"
.type lsretain0.2, %object
lsretain0.2:
.zero 2
.section .bss.lsretain1,"aRw"
.type lsretain1.1, %object
lsretain1.1:
.zero 2
.section .data.lsretain2,"aRw"
.type lsretain2.0, %object
lsretain2.0:
.word 1
.section .text._start,"ax"
.global _start
.type _start, %function
_start:
.word 0
|
tactcomplabs/xbgas-binutils-gdb | 1,345 | gold/testsuite/thumb_blx_in_range.s | # thumb_blx_in_range.s
#
# Test THUMB/THUMB-2 blx instructions just within the branch range limits.
# Because bit 1 of the branch target comes from the branch instruction
# address, the branch range from PC (branch instruction address + 4) is
# acutally -((1<<22) + 2) to ((1<<22) - 4) for THUMB and -((1<<24) + 2) to
# ((1<<24) - 4) from THUMB2.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.align 2
.global _backward_target
.code 32
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
nop.n
blx _backward_target
.size _backward_test, .-_backward_test
.align 2
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
blx _forward_target
.size _forward_test, .-_forward_test
.code 32
.section .text.post,"x"
# Add padding so that target is just in branch range.
.space 12
.align 2
.global _forward_target
.code 32
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
tactcomplabs/xbgas-binutils-gdb | 1,433 | gold/testsuite/pr20308_gd.S | .text
.p2align 4,,15
.globl get_gd
.type get_gd, @function
get_gd:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal gd@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@PLT
addl $8, %esp
popl %ebx
ret
.size get_gd, .-get_gd
.p2align 4,,15
.globl set_gd
.type set_gd, @function
set_gd:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal gd@tlsgd(%ebx), %eax
call ___tls_get_addr@PLT
nop
movl 16(%esp), %edx
movl %edx, (%eax)
addl $8, %esp
popl %ebx
ret
.size set_gd, .-set_gd
.text
.p2align 4,,15
.globl test_gd
.type test_gd, @function
test_gd:
call __x86.get_pc_thunk.cx
addl $_GLOBAL_OFFSET_TABLE_, %ecx
subl $12, %esp
leal gd@tlsgd(%ecx), %eax
call *___tls_get_addr@GOT(%ecx)
movl 16(%esp), %ecx
cmpl %ecx, (%eax)
sete %al
addl $12, %esp
movzbl %al, %eax
ret
.size test_gd, .-test_gd
.section .text.unlikely
.section .text.__x86.get_pc_thunk.bx,"axG",@progbits,__x86.get_pc_thunk.bx,comdat
.globl __x86.get_pc_thunk.bx
.hidden __x86.get_pc_thunk.bx
.type __x86.get_pc_thunk.bx, @function
__x86.get_pc_thunk.bx:
movl (%esp), %ebx
ret
.section .text.__x86.get_pc_thunk.cx,"axG",@progbits,__x86.get_pc_thunk.cx,comdat
.globl __x86.get_pc_thunk.cx
.hidden __x86.get_pc_thunk.cx
.type __x86.get_pc_thunk.cx, @function
__x86.get_pc_thunk.cx:
movl (%esp), %ecx
ret
.section .note.GNU-stack,"",@progbits
|
tactcomplabs/xbgas-binutils-gdb | 1,116 | gold/testsuite/gnu_property_a.S | #define NT_GNU_PROPERTY_TYPE_0 5
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_X86_ISA_1_USED 0xc0010002
#define GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#if __SIZEOF_PTRDIFF_T__ == 8
# define ALIGN 3
#elif __SIZEOF_PTRDIFF_T__ == 4
# define ALIGN 2
#endif
.text
.globl _start
_start:
ret
.section ".note.gnu.property", "a"
.p2align ALIGN
.long 1f - 0f /* name length */
.long 5f - 2f /* data length */
.long NT_GNU_PROPERTY_TYPE_0 /* note type */
0: .asciz "GNU" /* vendor name */
1:
.p2align ALIGN
2: .long GNU_PROPERTY_STACK_SIZE /* pr_type. */
.long 4f - 3f /* pr_datasz. */
3:
.dc.a 0x800 /* Stack size. */
4:
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_USED
.long 4
.byte 0x01,0x10,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_NEEDED
.long 4
.byte 0x01,0x10,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_FEATURE_1_AND
.long 4
.byte 0x01,0x00,0x00,0x00
.p2align ALIGN
5:
|
tactcomplabs/xbgas-binutils-gdb | 24,567 | gold/testsuite/dwp_test_2.s | .file "dwp_test_2.cc"
.text
.Ltext0:
.section .text._Z4f13iv,"axG",@progbits,_Z4f13iv,comdat
.weak _Z4f13iv
.type _Z4f13iv, @function
_Z4f13iv:
.LFB0:
.file 1 "dwp_test.h"
.loc 1 70 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 1 70 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE0:
.size _Z4f13iv, .-_Z4f13iv
.text
.align 2
.globl _ZN2C14t1_2Ev
.type _ZN2C14t1_2Ev, @function
_ZN2C14t1_2Ev:
.LFB1:
.file 2 "dwp_test_2.cc"
.loc 2 31 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 32 0
movl $123, %eax
.loc 2 33 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE1:
.size _ZN2C14t1_2Ev, .-_ZN2C14t1_2Ev
.align 2
.globl _ZN2C13t1aEv
.type _ZN2C13t1aEv, @function
_ZN2C13t1aEv:
.LFB2:
.loc 2 37 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $8, %rsp
movq %rdi, -8(%rbp)
.loc 2 38 0
movq -8(%rbp), %rax
movq %rax, %rdi
call _ZN2C14t1_2Ev
cmpl $123, %eax
sete %al
.loc 2 39 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE2:
.size _ZN2C13t1aEv, .-_ZN2C13t1aEv
.globl v2
.data
.align 4
.type v2, @object
.size v2, 4
v2:
.long 456
.globl v3
.bss
.align 4
.type v3, @object
.size v3, 4
v3:
.zero 4
.globl v4
.data
.type v4, @object
.size v4, 13
v4:
.string "Hello, world"
.globl v5
.bss
.type v5, @object
.size v5, 13
v5:
.zero 13
.text
.globl _Z3f10v
.type _Z3f10v, @function
_Z3f10v:
.LFB3:
.loc 2 73 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 74 0
movl $135, %eax
.loc 2 75 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE3:
.size _Z3f10v, .-_Z3f10v
.globl _Z4f11bPFivE
.type _Z4f11bPFivE, @function
_Z4f11bPFivE:
.LFB4:
.loc 2 81 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, -8(%rbp)
.loc 2 82 0
movq -8(%rbp), %rax
call *%rax
.loc 2 83 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE4:
.size _Z4f11bPFivE, .-_Z4f11bPFivE
.align 2
.globl _ZN2C32f4Ev
.type _ZN2C32f4Ev, @function
_ZN2C32f4Ev:
.LFB5:
.loc 2 89 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 90 0
movl $_Z3t12v, %eax
.loc 2 91 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE5:
.size _ZN2C32f4Ev, .-_ZN2C32f4Ev
.globl _Z3f13v
.type _Z3f13v, @function
_Z3f13v:
.LFB6:
.loc 2 97 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 98 0
movl $_Z4f13iv, %eax
.loc 2 99 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE6:
.size _Z3f13v, .-_Z3f13v
.section .rodata
.LC0:
.string "test string constant"
.text
.globl _Z3f14v
.type _Z3f14v, @function
_Z3f14v:
.LFB7:
.loc 2 105 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 106 0
movl $.LC0, %eax
.loc 2 107 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE7:
.size _Z3f14v, .-_Z3f14v
.section .rodata
.align 8
.LC1:
.string "t"
.string ""
.string ""
.string "e"
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "w"
.string ""
.string ""
.string "i"
.string ""
.string ""
.string "d"
.string ""
.string ""
.string "e"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string "r"
.string ""
.string ""
.string "i"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "g"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "c"
.string ""
.string ""
.string "o"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string "a"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.text
.globl _Z3f15v
.type _Z3f15v, @function
_Z3f15v:
.LFB8:
.loc 2 113 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 114 0
movl $.LC1, %eax
.loc 2 115 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE8:
.size _Z3f15v, .-_Z3f15v
.globl t17data
.section .rodata
.LC2:
.string "a"
.LC3:
.string "b"
.LC4:
.string "c"
.LC5:
.string "d"
.LC6:
.string "e"
.data
.align 32
.type t17data, @object
.size t17data, 40
t17data:
.quad .LC2
.quad .LC3
.quad .LC4
.quad .LC5
.quad .LC6
.text
.globl _Z3f18i
.type _Z3f18i, @function
_Z3f18i:
.LFB9:
.loc 2 128 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movl %edi, -4(%rbp)
.loc 2 129 0
cmpl $4, -4(%rbp)
ja .L19
movl -4(%rbp), %eax
movq .L25(,%rax,8), %rax
jmp *%rax
.section .rodata
.align 8
.align 4
.L25:
.quad .L20
.quad .L21
.quad .L22
.quad .L23
.quad .L24
.text
.L20:
.loc 2 132 0
movl $.LC2, %eax
jmp .L26
.L21:
.loc 2 134 0
movl $.LC3, %eax
jmp .L26
.L22:
.loc 2 136 0
movl $.LC4, %eax
jmp .L26
.L23:
.loc 2 138 0
movl $.LC5, %eax
jmp .L26
.L24:
.loc 2 140 0
movl $.LC6, %eax
jmp .L26
.L19:
.loc 2 142 0
movl $0, %eax
.L26:
.loc 2 144 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE9:
.size _Z3f18i, .-_Z3f18i
.Letext0:
.section .debug_types.dwo,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0xf3
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x8a
.byte 0xda
.byte 0x59
.byte 0x6e
.byte 0x4d
.byte 0x5c
.byte 0xa
.byte 0x88
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C3"
.byte 0x4
.byte 0x1
.byte 0x2f
.long 0xd6
.uleb128 0x3
.string "member1"
.byte 0x1
.byte 0x36
.long 0xd6
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x1
.byte 0x32
.string "_ZN2C39testcase1Ev"
.long 0xdd
.byte 0x1
.long 0x65
.long 0x6b
.uleb128 0x5
.long 0xe5
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x1
.byte 0x33
.string "_ZN2C39testcase2Ev"
.long 0xdd
.byte 0x1
.long 0x8f
.long 0x95
.uleb128 0x5
.long 0xe5
.byte 0
.uleb128 0x4
.uleb128 0x2
.byte 0x1
.byte 0x34
.string "_ZN2C39testcase3Ev"
.long 0xdd
.byte 0x1
.long 0xb9
.long 0xbf
.uleb128 0x5
.long 0xe5
.byte 0
.uleb128 0x6
.string "f4"
.byte 0x1
.byte 0x35
.uleb128 0x3
.long 0xeb
.byte 0x1
.long 0xcf
.uleb128 0x5
.long 0xe5
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.uleb128 0x8
.byte 0x8
.long 0xf1
.uleb128 0x9
.long 0xdd
.byte 0
.section .debug_types,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0x6e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_2.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_types.dwo,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0x138
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0xe3
.byte 0xad
.byte 0x5
.byte 0x3b
.byte 0x75
.byte 0xeb
.byte 0xfb
.byte 0xc7
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C1"
.byte 0x4
.byte 0x1
.byte 0x19
.long 0x126
.uleb128 0x3
.string "member1"
.byte 0x1
.byte 0x22
.long 0x126
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x1
.byte 0x1c
.string "_ZN2C19testcase1Ev"
.long 0x12d
.byte 0x1
.long 0x65
.long 0x6b
.uleb128 0x5
.long 0x135
.byte 0
.uleb128 0xa
.string "t1a"
.byte 0x1
.byte 0x1d
.uleb128 0x4
.long 0x12d
.byte 0x1
.long 0x80
.long 0x86
.uleb128 0x5
.long 0x135
.byte 0
.uleb128 0xa
.string "t1_2"
.byte 0x1
.byte 0x1e
.uleb128 0x5
.long 0x126
.byte 0x1
.long 0x9c
.long 0xa2
.uleb128 0x5
.long 0x135
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x1
.byte 0x1f
.string "_ZN2C19testcase2Ev"
.long 0x12d
.byte 0x1
.long 0xc6
.long 0xcc
.uleb128 0x5
.long 0x135
.byte 0
.uleb128 0x4
.uleb128 0x2
.byte 0x1
.byte 0x20
.string "_ZN2C19testcase3Ev"
.long 0x12d
.byte 0x1
.long 0xf0
.long 0xf6
.uleb128 0x5
.long 0x135
.byte 0
.uleb128 0xb
.string "testcase4"
.byte 0x1
.byte 0x21
.string "_ZN2C19testcase4Ev"
.long 0x12d
.byte 0x1
.long 0x11f
.uleb128 0x5
.long 0x135
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.byte 0
.section .debug_types,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0x6e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_2.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_info.dwo,"e",@progbits
.Ldebug_info0:
.long 0x329
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0xc
.string "GNU C++ 4.7.x-google 20120720 (prerelease)"
.byte 0x4
.string "dwp_test_2.cc"
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.byte 0xb9
.byte 0xf8
.byte 0xe0
.byte 0x8c
.byte 0x71
.byte 0xab
.byte 0xc
.byte 0xcf
.uleb128 0xd
.string "C1"
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0xb9
.uleb128 0xe
.string "t1a"
.byte 0x1
.byte 0x1d
.uleb128 0x4
.long 0xc0
.byte 0x1
.uleb128 0xe
.string "t1_2"
.byte 0x1
.byte 0x1e
.uleb128 0x5
.long 0xb9
.byte 0x1
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0xf
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.uleb128 0xd
.string "C3"
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0xef
.uleb128 0xe
.string "f4"
.byte 0x1
.byte 0x35
.uleb128 0x3
.long 0xfe
.byte 0x1
.byte 0
.uleb128 0xf
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.uleb128 0x9
.long 0xc0
.uleb128 0x8
.byte 0x8
.long 0xf9
.uleb128 0x10
.string "f13i"
.byte 0x1
.byte 0x46
.string "_Z4f13iv"
.uleb128 0
.quad .LFE0-.LFB0
.uleb128 0x1
.byte 0x9c
.uleb128 0x11
.long 0xaa
.byte 0x2
.uleb128 0x1
.quad .LFE1-.LFB1
.uleb128 0x1
.byte 0x9c
.long 0x139
.long 0x147
.uleb128 0x12
.string "this"
.long 0x147
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x13
.long 0xc8
.uleb128 0x14
.long 0x9d
.byte 0x2
.byte 0x24
.uleb128 0x2
.quad .LFE2-.LFB2
.uleb128 0x1
.byte 0x9c
.long 0x166
.long 0x174
.uleb128 0x12
.string "this"
.long 0x147
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x15
.string "f10"
.byte 0x2
.byte 0x48
.string "_Z3f10v"
.long 0xb9
.uleb128 0x3
.quad .LFE3-.LFB3
.uleb128 0x1
.byte 0x9c
.uleb128 0x16
.string "f11b"
.byte 0x2
.byte 0x50
.string "_Z4f11bPFivE"
.long 0xb9
.uleb128 0x4
.quad .LFE4-.LFB4
.uleb128 0x1
.byte 0x9c
.long 0x1c9
.uleb128 0x17
.string "pfn"
.byte 0x2
.byte 0x50
.long 0x1ce
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x9
.long 0xb9
.uleb128 0x8
.byte 0x8
.long 0x1c9
.uleb128 0x18
.long 0xe2
.byte 0x2
.byte 0x58
.uleb128 0x5
.quad .LFE5-.LFB5
.uleb128 0x1
.byte 0x9c
.long 0x1ee
.long 0x1fc
.uleb128 0x12
.string "this"
.long 0x1fc
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x13
.long 0xef
.uleb128 0x19
.uleb128 0x15
.string "f13"
.byte 0x2
.byte 0x60
.string "_Z3f13v"
.long 0x220
.uleb128 0x6
.quad .LFE6-.LFB6
.uleb128 0x1
.byte 0x9c
.uleb128 0x8
.byte 0x8
.long 0x201
.uleb128 0x15
.string "f14"
.byte 0x2
.byte 0x68
.string "_Z3f14v"
.long 0x244
.uleb128 0x7
.quad .LFE7-.LFB7
.uleb128 0x1
.byte 0x9c
.uleb128 0x8
.byte 0x8
.long 0x24a
.uleb128 0x13
.long 0x24f
.uleb128 0x7
.byte 0x1
.byte 0x6
.string "char"
.uleb128 0x15
.string "f15"
.byte 0x2
.byte 0x70
.string "_Z3f15v"
.long 0x275
.uleb128 0x8
.quad .LFE8-.LFB8
.uleb128 0x1
.byte 0x9c
.uleb128 0x8
.byte 0x8
.long 0x27b
.uleb128 0x13
.long 0x280
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "wchar_t"
.uleb128 0x1a
.string "f18"
.byte 0x2
.byte 0x7f
.string "_Z3f18i"
.long 0x244
.uleb128 0x9
.quad .LFE9-.LFB9
.uleb128 0x1
.byte 0x9c
.long 0x2ba
.uleb128 0x17
.string "i"
.byte 0x2
.byte 0x7f
.long 0xb9
.uleb128 0x2
.byte 0x91
.sleb128 -20
.byte 0
.uleb128 0x1b
.string "v2"
.byte 0x2
.byte 0x2b
.long 0xb9
.uleb128 0x2
.byte 0xfb
.uleb128 0xa
.uleb128 0x1b
.string "v3"
.byte 0x2
.byte 0x30
.long 0xb9
.uleb128 0x2
.byte 0xfb
.uleb128 0xb
.uleb128 0x1c
.long 0x24f
.long 0x2e4
.uleb128 0x1d
.long 0x2e4
.byte 0xc
.byte 0
.uleb128 0x7
.byte 0x8
.byte 0x7
.string "sizetype"
.uleb128 0x1b
.string "v4"
.byte 0x2
.byte 0x34
.long 0x2d4
.uleb128 0x2
.byte 0xfb
.uleb128 0xc
.uleb128 0x1b
.string "v5"
.byte 0x2
.byte 0x39
.long 0x2d4
.uleb128 0x2
.byte 0xfb
.uleb128 0xd
.uleb128 0x1c
.long 0x244
.long 0x31a
.uleb128 0x1d
.long 0x2e4
.byte 0x4
.byte 0
.uleb128 0x1b
.string "t17data"
.byte 0x2
.byte 0x77
.long 0x30a
.uleb128 0x2
.byte 0xfb
.uleb128 0xe
.byte 0
.section .debug_info,"",@progbits
.Lskeleton_debug_info0:
.long 0x7e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.uleb128 0x1
.long .Ldebug_ranges0+0
.quad 0
.long .Ldebug_line0
.byte 0xb9
.byte 0xf8
.byte 0xe0
.byte 0x8c
.byte 0x71
.byte 0xab
.byte 0xc
.byte 0xcf
.long .Ldebug_ranges0
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_2.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_abbrev,"",@progbits
.Lskeleton_debug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0
.uleb128 0x55
.uleb128 0x17
.uleb128 0x11
.uleb128 0x1
.uleb128 0x10
.uleb128 0x17
.uleb128 0x2131
.uleb128 0x7
.uleb128 0x2132
.uleb128 0x17
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x41
.byte 0
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.byte 0
.section .debug_abbrev.dwo,"e",@progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x41
.byte 0x1
.uleb128 0x13
.uleb128 0xb
.uleb128 0x210f
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.uleb128 0x32
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x5
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x7
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x8
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x9
.uleb128 0x15
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xa
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xb
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xc
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0x8
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2131
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0xd
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0x69
.uleb128 0x20
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xe
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0xf
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.byte 0
.byte 0
.uleb128 0x10
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x11
.uleb128 0x2e
.byte 0x1
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x64
.uleb128 0x13
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x12
.uleb128 0x5
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x13
.uleb128 0x26
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x14
.uleb128 0x2e
.byte 0x1
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x64
.uleb128 0x13
.uleb128 0x2116
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x15
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x16
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2116
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x17
.uleb128 0x5
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x18
.uleb128 0x2e
.byte 0x1
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x64
.uleb128 0x13
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x19
.uleb128 0x15
.byte 0
.byte 0
.byte 0
.uleb128 0x1a
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x1b
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x1c
.uleb128 0x1
.byte 0x1
.uleb128 0x49
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x1d
.uleb128 0x21
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2f
.uleb128 0xb
.byte 0
.byte 0
.byte 0
.section .debug_gnu_pubnames,"",@progbits
.Ldebug_pubnames0:
.long 0xa3
.value 0x2
.long .Lskeleton_debug_info0
.long 0x32d
.long 0x104
.byte 0x30
.string "f13i"
.long 0x120
.byte 0x30
.string "C1::t1_2"
.long 0x14c
.byte 0x30
.string "C1::t1a"
.long 0x174
.byte 0x30
.string "f10"
.long 0x192
.byte 0x30
.string "f11b"
.long 0x1d4
.byte 0x30
.string "C3::f4"
.long 0x202
.byte 0x30
.string "f13"
.long 0x226
.byte 0x30
.string "f14"
.long 0x257
.byte 0x30
.string "f15"
.long 0x28b
.byte 0x30
.string "f18"
.long 0x2ba
.byte 0x20
.string "v2"
.long 0x2c7
.byte 0x20
.string "v3"
.long 0x2f0
.byte 0x20
.string "v4"
.long 0x2fd
.byte 0x20
.string "v5"
.long 0x31a
.byte 0x20
.string "t17data"
.long 0
.section .debug_gnu_pubtypes,"",@progbits
.Ldebug_pubtypes0:
.long 0x56
.value 0x2
.long .Lskeleton_debug_info0
.long 0x32d
.long 0xb9
.byte 0x90
.string "int"
.long 0xc0
.byte 0x90
.string "bool"
.long 0x8d
.byte 0x10
.string "C1"
.long 0xd2
.byte 0x10
.string "C3"
.long 0x24f
.byte 0x90
.string "char"
.long 0x280
.byte 0x90
.string "wchar_t"
.long 0x2e4
.byte 0x90
.string "sizetype"
.long 0
.section .debug_aranges,"",@progbits
.long 0x3c
.value 0x2
.long .Lskeleton_debug_info0
.byte 0x8
.byte 0
.value 0
.value 0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad .LFB0
.quad .LFE0-.LFB0
.quad 0
.quad 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.quad .Ltext0
.quad .Letext0
.quad .LFB0
.quad .LFE0
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_line.dwo,"e",@progbits
.Lskeleton_debug_line0:
.long .LELT0-.LSLT0
.LSLT0:
.value 0x4
.long .LELTP0-.LASLTP0
.LASLTP0:
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0xf6
.byte 0xf2
.byte 0xd
.byte 0
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0
.byte 0
.byte 0
.byte 0x1
.byte 0
.byte 0
.byte 0x1
.byte 0
.string "dwp_test.h"
.uleb128 0
.uleb128 0
.uleb128 0
.string "dwp_test_2.cc"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.LELTP0:
.LELT0:
.section .debug_str_offsets.dwo,"e",@progbits
.long 0
.long 0xa
.long 0x14
.long 0x1e
.long 0x2a
.long 0x37
.section .debug_str.dwo,"e",@progbits
.LASF0:
.string "testcase1"
.LASF1:
.string "testcase2"
.LASF2:
.string "testcase3"
.LASF3:
.string "_ZN2C32f4Ev"
.LASF4:
.string "_ZN2C13t1aEv"
.LASF5:
.string "_ZN2C14t1_2Ev"
.section .debug_addr,"",@progbits
.Ldebug_addr0:
.quad .LFB0
.quad .LFB1
.quad .LFB2
.quad .LFB3
.quad .LFB4
.quad .LFB5
.quad .LFB6
.quad .LFB7
.quad .LFB8
.quad .LFB9
.quad v2
.quad v3
.quad v4
.quad v5
.quad t17data
.ident "GCC: (Google_crosstoolv16-gcc-4.7.x-grtev3) 4.7.x-google 20120720 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
tactcomplabs/xbgas-binutils-gdb | 1,071 | gold/testsuite/thumb_bl_in_range.s | # thumb_bl_in_range.s
# Test THUMB/THUMB-2 bl instructions just within the branch range limits.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
bl _backward_target
.size _backward_test, .-_backward_test
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
bl _forward_target
.size _forward_test, .-_forward_test
.section .text.post,"x"
# Add padding so that target is just in branch range.
.space 10
.global _forward_target
.code 16
.thumb_func
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
tactcomplabs/xbgas-binutils-gdb | 1,244 | gold/testsuite/gnu_property_c.S | #define NT_GNU_PROPERTY_TYPE_0 5
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
#define GNU_PROPERTY_X86_ISA_1_USED 0xc0010002
#define GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#if __SIZEOF_PTRDIFF_T__ == 8
# define ALIGN 3
#elif __SIZEOF_PTRDIFF_T__ == 4
# define ALIGN 2
#endif
.section ".note.gnu.property", "a"
.p2align ALIGN
.long 1f - 0f /* name length */
.long 5f - 2f /* data length */
.long NT_GNU_PROPERTY_TYPE_0 /* note type */
0: .asciz "GNU" /* vendor name */
1:
.p2align ALIGN
2: .long GNU_PROPERTY_STACK_SIZE /* pr_type. */
.long 4f - 3f /* pr_datasz. */
3:
.dc.a 0x111100 /* Stack size. */
4:
.p2align ALIGN
.long GNU_PROPERTY_NO_COPY_ON_PROTECTED /* pr_type. */
.long 0 /* pr_datasz. */
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_USED
.long 4
.byte 0x11,0x10,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_NEEDED
.long 4
.byte 0x11,0x10,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_FEATURE_1_AND
.long 4
.byte 0x01,0x00,0x00,0x00
.p2align ALIGN
5:
|
tactcomplabs/xbgas-binutils-gdb | 8,232 | gold/testsuite/dwp_test_1b.s | .file "dwp_test_1b.cc"
.text
.Ltext0:
.globl c3
.bss
.align 4
.type c3, @object
.size c3, 4
c3:
.zero 4
.text
.globl _Z4t16av
.type _Z4t16av, @function
_Z4t16av:
.LFB1:
.file 1 "dwp_test_1b.cc"
.loc 1 33 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 1 34 0
call _Z3f10v
cmpl $135, %eax
sete %al
.loc 1 35 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE1:
.size _Z4t16av, .-_Z4t16av
.Letext0:
.file 2 "dwp_test.h"
.section .debug_types.dwo,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0x119
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x8a
.byte 0xda
.byte 0x59
.byte 0x6e
.byte 0x4d
.byte 0x5c
.byte 0xa
.byte 0x88
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C3"
.byte 0x4
.byte 0x2
.byte 0x2f
.long 0xfc
.uleb128 0x3
.string "member1"
.byte 0x2
.byte 0x36
.long 0xfc
.byte 0
.byte 0x1
.uleb128 0x4
.string "testcase1"
.byte 0x2
.byte 0x32
.string "_ZN2C39testcase1Ev"
.long 0x103
.byte 0x1
.long 0x6e
.long 0x74
.uleb128 0x5
.long 0x10b
.byte 0
.uleb128 0x4
.string "testcase2"
.byte 0x2
.byte 0x33
.string "_ZN2C39testcase2Ev"
.long 0x103
.byte 0x1
.long 0xa1
.long 0xa7
.uleb128 0x5
.long 0x10b
.byte 0
.uleb128 0x4
.string "testcase3"
.byte 0x2
.byte 0x34
.string "_ZN2C39testcase3Ev"
.long 0x103
.byte 0x1
.long 0xd4
.long 0xda
.uleb128 0x5
.long 0x10b
.byte 0
.uleb128 0x6
.string "f4"
.byte 0x2
.byte 0x35
.string "_ZN2C32f4Ev"
.long 0x111
.byte 0x1
.long 0xf5
.uleb128 0x5
.long 0x10b
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.uleb128 0x8
.byte 0x8
.long 0x117
.uleb128 0x9
.long 0x103
.byte 0
.section .debug_types,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0x6f
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1b.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_info.dwo,"e",@progbits
.Ldebug_info0:
.long 0xcb
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0xa
.string "GNU C++ 4.7.x-google 20120720 (prerelease)"
.byte 0x4
.string "dwp_test_1b.cc"
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.byte 0xf6
.byte 0xef
.byte 0x47
.byte 0xa2
.byte 0x3e
.byte 0xc1
.byte 0x6e
.byte 0xbd
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0xb
.string "t16a"
.byte 0x1
.byte 0x20
.string "_Z4t16av"
.long 0x95
.uleb128 0
.quad .LFE1-.LFB1
.uleb128 0x1
.byte 0x9c
.uleb128 0xc
.string "c3"
.byte 0x1
.byte 0x1d
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.uleb128 0x2
.byte 0xfb
.uleb128 0x1
.byte 0
.section .debug_info,"",@progbits
.Lskeleton_debug_info0:
.long 0x7f
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.uleb128 0x1
.quad .Ltext0
.quad .Letext0-.Ltext0
.long .Ldebug_line0
.byte 0xf6
.byte 0xef
.byte 0x47
.byte 0xa2
.byte 0x3e
.byte 0xc1
.byte 0x6e
.byte 0xbd
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1b.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_abbrev,"",@progbits
.Lskeleton_debug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.uleb128 0x2131
.uleb128 0x7
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x41
.byte 0
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.byte 0
.section .debug_abbrev.dwo,"e",@progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x41
.byte 0x1
.uleb128 0x13
.uleb128 0xb
.uleb128 0x210f
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.uleb128 0x32
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x5
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x7
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x8
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x9
.uleb128 0x15
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xa
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0x8
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2131
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0xb
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2116
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0xc
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.byte 0
.section .debug_gnu_pubnames,"",@progbits
.Ldebug_pubnames0:
.long 0x20
.value 0x2
.long .Lskeleton_debug_info0
.long 0xcf
.long 0x9d
.byte 0x30
.string "t16a"
.long 0xbd
.byte 0x20
.string "c3"
.long 0
.section .debug_gnu_pubtypes,"",@progbits
.Ldebug_pubtypes0:
.long 0x29
.value 0x2
.long .Lskeleton_debug_info0
.long 0xcf
.long 0x8e
.byte 0x90
.string "int"
.long 0x95
.byte 0x90
.string "bool"
.long 0
.byte 0x10
.string "C3"
.long 0
.section .debug_aranges,"",@progbits
.long 0x2c
.value 0x2
.long .Lskeleton_debug_info0
.byte 0x8
.byte 0
.value 0
.value 0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_line.dwo,"e",@progbits
.Lskeleton_debug_line0:
.long .LELT0-.LSLT0
.LSLT0:
.value 0x4
.long .LELTP0-.LASLTP0
.LASLTP0:
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0xf6
.byte 0xf2
.byte 0xd
.byte 0
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0
.byte 0
.byte 0
.byte 0x1
.byte 0
.byte 0
.byte 0x1
.byte 0
.string "dwp_test_1b.cc"
.uleb128 0
.uleb128 0
.uleb128 0
.string "dwp_test.h"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.LELTP0:
.LELT0:
.section .debug_addr,"",@progbits
.Ldebug_addr0:
.quad .LFB1
.quad c3
.ident "GCC: (Google_crosstoolv16-gcc-4.7.x-grtev3) 4.7.x-google 20120720 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
tactcomplabs/xbgas-binutils-gdb | 1,549 | gold/testsuite/thumb_blx_out_of_range.s | # thumb_blx_out_of_range.s
# Test THUMB/THUMB-2 blx instructions just out of the branch range limits.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just output of branch range.
.space 4
.global _forward_target
.global _backward_target
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Use 256-byte alignment so that we know where the stubs start.
.align 8
# Define _start so that linker does not complain.
.align 2
.global _start
.code 32
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
bl _backward_target
.size _backward_test, .-_backward_test
.align 2
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
# Bit 1 of the BLX target comes from bit 1 of branch base address,
# which is BLX instruction's address + 4. We intentionally put this
# forward BLX at an address n*4 + 2 so that the branch offset is
# bumped up by 2.
nop.n
bl _forward_target
.size _forward_test, .-_forward_test
# switch back to ARM mode so that stubs are disassembled correctly.
.align 2
.code 32
# Align stub table for address matching.
.align 8
.section .text.post,"x"
# Add padding so that target is just out of branch range.
.space 12
.align 2
.code 32
.global _forward_target
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
tactcomplabs/xbgas-binutils-gdb | 1,297 | gold/testsuite/thumb_bl_out_of_range_local.s | # thumb_bl_out_of_range_local.s
# Test THUMB/THUMB-2 bl instructions just out of the branch range limits
# and with local branch targets.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just output of branch range.
.space 6
.code 16
.thumb_func
.type .Lbackward_target, %function
.Lbackward_target:
bx lr
.size .Lbackward_target, .-.Lbackward_target
.text
# Use 256-byte alignment so that we know where the stubs start.
.align 8
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
bl .Lbackward_target
.size _backward_test, .-_backward_test
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
bl .Lforward_target
.size _forward_test, .-_forward_test
# Switch back to ARM mode so that we can see stubs
.align 2
.code 32
# Align stub table for address matching.
.align 8
.section .text.post,"x"
# Add padding so that target is just out of branch range.
.space 12
.code 16
.thumb_func
.type .Lforward_target, %function
.Lforward_target:
bx lr
.size .Lforward_target, .-.Lforward_target
|
tactcomplabs/xbgas-binutils-gdb | 1,565 | gold/testsuite/pr20308_ld.S | .text
.p2align 4,,15
.globl get_ld
.type get_ld, @function
get_ld:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal ld@tlsldm(%ebx), %eax
call ___tls_get_addr@PLT
leal ld@dtpoff(%eax), %eax
addl $8, %esp
popl %ebx
ret
.size get_ld, .-get_ld
.p2align 4,,15
.globl set_ld
.type set_ld, @function
set_ld:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal ld@tlsldm(%ebx), %eax
call ___tls_get_addr@PLT
movl 16(%esp), %edx
leal ld@dtpoff(%eax), %eax
movl %edx, (%eax)
addl $8, %esp
popl %ebx
ret
.size set_ld, .-set_ld
.p2align 4,,15
.globl test_ld
.type test_ld, @function
test_ld:
call __x86.get_pc_thunk.cx
addl $_GLOBAL_OFFSET_TABLE_, %ecx
subl $12, %esp
leal ld@tlsldm(%ecx), %eax
call *___tls_get_addr@GOT(%ecx)
movl 16(%esp), %ecx
leal ld@dtpoff(%eax), %eax
cmpl %ecx, (%eax)
sete %al
addl $12, %esp
movzbl %al, %eax
ret
.size test_ld, .-test_ld
.section .tbss,"awT",@nobits
.align 4
.type ld, @object
.size ld, 4
ld:
.zero 4
.section .text.__x86.get_pc_thunk.bx,"axG",@progbits,__x86.get_pc_thunk.bx,comdat
.globl __x86.get_pc_thunk.bx
.hidden __x86.get_pc_thunk.bx
.type __x86.get_pc_thunk.bx, @function
__x86.get_pc_thunk.bx:
movl (%esp), %ebx
ret
.section .text.__x86.get_pc_thunk.cx,"axG",@progbits,__x86.get_pc_thunk.cx,comdat
.globl __x86.get_pc_thunk.cx
.hidden __x86.get_pc_thunk.cx
.type __x86.get_pc_thunk.cx, @function
__x86.get_pc_thunk.cx:
movl (%esp), %ecx
ret
.section .note.GNU-stack,"",@progbits
|
tactcomplabs/xbgas-binutils-gdb | 38,771 | gold/testsuite/dwp_test_1.s | .file "dwp_test_1.cc"
.text
.Ltext0:
.section .text._Z4f13iv,"axG",@progbits,_Z4f13iv,comdat
.weak _Z4f13iv
.type _Z4f13iv, @function
_Z4f13iv:
.LFB0:
.file 1 "dwp_test.h"
.loc 1 70 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 1 70 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE0:
.size _Z4f13iv, .-_Z4f13iv
.text
.align 2
.globl _ZN2C19testcase1Ev
.type _ZN2C19testcase1Ev, @function
_ZN2C19testcase1Ev:
.LFB1:
.file 2 "dwp_test_1.cc"
.loc 2 31 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, -8(%rbp)
.loc 2 32 0
movq -8(%rbp), %rax
movq %rax, %rdi
call _ZN2C14t1_2Ev
cmpl $123, %eax
sete %al
.loc 2 33 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE1:
.size _ZN2C19testcase1Ev, .-_ZN2C19testcase1Ev
.align 2
.globl _ZN2C19testcase2Ev
.type _ZN2C19testcase2Ev, @function
_ZN2C19testcase2Ev:
.LFB2:
.loc 2 39 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 40 0
movl v2(%rip), %eax
cmpl $456, %eax
sete %al
.loc 2 41 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE2:
.size _ZN2C19testcase2Ev, .-_ZN2C19testcase2Ev
.align 2
.globl _ZN2C19testcase3Ev
.type _ZN2C19testcase3Ev, @function
_ZN2C19testcase3Ev:
.LFB3:
.loc 2 47 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 48 0
movl v3(%rip), %eax
cmpl $789, %eax
sete %al
.loc 2 49 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE3:
.size _ZN2C19testcase3Ev, .-_ZN2C19testcase3Ev
.align 2
.globl _ZN2C19testcase4Ev
.type _ZN2C19testcase4Ev, @function
_ZN2C19testcase4Ev:
.LFB4:
.loc 2 55 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 56 0
movzbl v4+5(%rip), %eax
cmpb $44, %al
sete %al
.loc 2 57 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE4:
.size _ZN2C19testcase4Ev, .-_ZN2C19testcase4Ev
.align 2
.globl _ZN2C29testcase1Ev
.type _ZN2C29testcase1Ev, @function
_ZN2C29testcase1Ev:
.LFB5:
.loc 2 63 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 64 0
movzbl v5+7(%rip), %eax
cmpb $119, %al
sete %al
.loc 2 65 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE5:
.size _ZN2C29testcase1Ev, .-_ZN2C29testcase1Ev
.globl p6
.data
.align 8
.type p6, @object
.size p6, 8
p6:
.quad v2
.text
.align 2
.globl _ZN2C29testcase2Ev
.type _ZN2C29testcase2Ev, @function
_ZN2C29testcase2Ev:
.LFB6:
.loc 2 73 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 74 0
movq p6(%rip), %rax
movl (%rax), %eax
cmpl $456, %eax
sete %al
.loc 2 75 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE6:
.size _ZN2C29testcase2Ev, .-_ZN2C29testcase2Ev
.globl p7
.data
.align 8
.type p7, @object
.size p7, 8
p7:
.quad v3
.text
.align 2
.globl _ZN2C29testcase3Ev
.type _ZN2C29testcase3Ev, @function
_ZN2C29testcase3Ev:
.LFB7:
.loc 2 83 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 84 0
movq p7(%rip), %rax
movl (%rax), %eax
cmpl $789, %eax
sete %al
.loc 2 85 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE7:
.size _ZN2C29testcase3Ev, .-_ZN2C29testcase3Ev
.globl p8
.data
.align 8
.type p8, @object
.size p8, 8
p8:
.quad v4+6
.text
.align 2
.globl _ZN2C29testcase4Ev
.type _ZN2C29testcase4Ev, @function
_ZN2C29testcase4Ev:
.LFB8:
.loc 2 93 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 94 0
movq p8(%rip), %rax
movzbl (%rax), %eax
cmpb $32, %al
sete %al
.loc 2 95 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE8:
.size _ZN2C29testcase4Ev, .-_ZN2C29testcase4Ev
.globl p9
.data
.align 8
.type p9, @object
.size p9, 8
p9:
.quad v5+8
.text
.align 2
.globl _ZN2C39testcase1Ev
.type _ZN2C39testcase1Ev, @function
_ZN2C39testcase1Ev:
.LFB9:
.loc 2 103 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 104 0
movq p9(%rip), %rax
movzbl (%rax), %eax
cmpb $111, %al
sete %al
.loc 2 105 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE9:
.size _ZN2C39testcase1Ev, .-_ZN2C39testcase1Ev
.globl pfn
.data
.align 8
.type pfn, @object
.size pfn, 8
pfn:
.quad _Z3f10v
.text
.align 2
.globl _ZN2C39testcase2Ev
.type _ZN2C39testcase2Ev, @function
_ZN2C39testcase2Ev:
.LFB10:
.loc 2 113 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, -8(%rbp)
.loc 2 114 0
movq pfn(%rip), %rax
call *%rax
cmpl $135, %eax
sete %al
.loc 2 115 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE10:
.size _ZN2C39testcase2Ev, .-_ZN2C39testcase2Ev
.globl _Z4f11av
.type _Z4f11av, @function
_Z4f11av:
.LFB11:
.loc 2 121 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 122 0
movl $246, %eax
.loc 2 123 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE11:
.size _Z4f11av, .-_Z4f11av
.align 2
.globl _ZN2C39testcase3Ev
.type _ZN2C39testcase3Ev, @function
_ZN2C39testcase3Ev:
.LFB12:
.loc 2 127 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, -8(%rbp)
.loc 2 128 0
movl $_Z4f11av, %edi
call _Z4f11bPFivE
cmpl $246, %eax
sete %al
.loc 2 129 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE12:
.size _ZN2C39testcase3Ev, .-_ZN2C39testcase3Ev
.globl _Z3t12v
.type _Z3t12v, @function
_Z3t12v:
.LFB13:
.loc 2 135 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 136 0
movl $c3, %edi
call _ZN2C32f4Ev
cmpq $_Z3t12v, %rax
sete %al
.loc 2 137 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE13:
.size _Z3t12v, .-_Z3t12v
.globl _Z3t13v
.type _Z3t13v, @function
_Z3t13v:
.LFB14:
.loc 2 143 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 144 0
call _Z3f13v
cmpq $_Z4f13iv, %rax
sete %al
.loc 2 145 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE14:
.size _Z3t13v, .-_Z3t13v
.section .rodata
.LC0:
.string "test string constant"
.text
.globl _Z3t14v
.type _Z3t14v, @function
_Z3t14v:
.LFB15:
.loc 2 151 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
.LBB2:
.loc 2 152 0
movq $.LC0, -8(%rbp)
.loc 2 153 0
call _Z3f14v
movq %rax, -16(%rbp)
.loc 2 154 0
jmp .L31
.L33:
.loc 2 155 0
movq -8(%rbp), %rax
movzbl (%rax), %edx
movq -16(%rbp), %rax
movzbl (%rax), %eax
cmpb %al, %dl
setne %al
addq $1, -8(%rbp)
addq $1, -16(%rbp)
testb %al, %al
je .L31
.loc 2 156 0
movl $0, %eax
jmp .L32
.L31:
.loc 2 154 0 discriminator 1
movq -8(%rbp), %rax
movzbl (%rax), %eax
testb %al, %al
setne %al
testb %al, %al
jne .L33
.loc 2 157 0
movq -16(%rbp), %rax
movzbl (%rax), %eax
testb %al, %al
sete %al
.L32:
.LBE2:
.loc 2 158 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE15:
.size _Z3t14v, .-_Z3t14v
.section .rodata
.align 8
.LC1:
.string "t"
.string ""
.string ""
.string "e"
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "w"
.string ""
.string ""
.string "i"
.string ""
.string ""
.string "d"
.string ""
.string ""
.string "e"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string "r"
.string ""
.string ""
.string "i"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "g"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "c"
.string ""
.string ""
.string "o"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string "a"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.text
.globl _Z3t15v
.type _Z3t15v, @function
_Z3t15v:
.LFB16:
.loc 2 164 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
.LBB3:
.loc 2 165 0
movq $.LC1, -8(%rbp)
.loc 2 166 0
call _Z3f15v
movq %rax, -16(%rbp)
.loc 2 167 0
jmp .L35
.L37:
.loc 2 168 0
movq -8(%rbp), %rax
movl (%rax), %edx
movq -16(%rbp), %rax
movl (%rax), %eax
cmpl %eax, %edx
setne %al
addq $4, -8(%rbp)
addq $4, -16(%rbp)
testb %al, %al
je .L35
.loc 2 169 0
movl $0, %eax
jmp .L36
.L35:
.loc 2 167 0 discriminator 1
movq -8(%rbp), %rax
movl (%rax), %eax
testl %eax, %eax
setne %al
testb %al, %al
jne .L37
.loc 2 170 0
movq -16(%rbp), %rax
movl (%rax), %eax
testl %eax, %eax
sete %al
.L36:
.LBE3:
.loc 2 171 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE16:
.size _Z3t15v, .-_Z3t15v
.globl _Z3t16v
.type _Z3t16v, @function
_Z3t16v:
.LFB17:
.loc 2 177 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 178 0
call _Z3f10v
cmpl $135, %eax
sete %al
.loc 2 179 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE17:
.size _Z3t16v, .-_Z3t16v
.globl _Z3t17v
.type _Z3t17v, @function
_Z3t17v:
.LFB18:
.loc 2 185 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.LBB4:
.loc 2 186 0
movb $97, -1(%rbp)
.LBB5:
.loc 2 187 0
movl $0, -8(%rbp)
jmp .L41
.L45:
.loc 2 189 0
movl -8(%rbp), %eax
cltq
movq t17data(,%rax,8), %rax
movzbl (%rax), %eax
cmpb -1(%rbp), %al
jne .L42
.loc 2 189 0 is_stmt 0 discriminator 1
movl -8(%rbp), %eax
cltq
movq t17data(,%rax,8), %rax
addq $1, %rax
movzbl (%rax), %eax
testb %al, %al
je .L43
.L42:
.loc 2 190 0 is_stmt 1
movl $0, %eax
jmp .L44
.L43:
.loc 2 191 0
addb $1, -1(%rbp)
.loc 2 187 0
addl $1, -8(%rbp)
.L41:
.loc 2 187 0 is_stmt 0 discriminator 1
cmpl $4, -8(%rbp)
setle %al
testb %al, %al
jne .L45
.LBE5:
.loc 2 193 0 is_stmt 1
movl $1, %eax
.L44:
.LBE4:
.loc 2 194 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE18:
.size _Z3t17v, .-_Z3t17v
.globl _Z3t18v
.type _Z3t18v, @function
_Z3t18v:
.LFB19:
.loc 2 200 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
.LBB6:
.loc 2 201 0
movb $97, -1(%rbp)
.LBB7:
.loc 2 202 0
movl $0, -8(%rbp)
jmp .L47
.L51:
.LBB8:
.loc 2 204 0
movl -8(%rbp), %eax
movl %eax, %edi
call _Z3f18i
movq %rax, -16(%rbp)
.loc 2 205 0
movq -16(%rbp), %rax
movzbl (%rax), %eax
cmpb -1(%rbp), %al
jne .L48
.loc 2 205 0 is_stmt 0 discriminator 1
movq -16(%rbp), %rax
addq $1, %rax
movzbl (%rax), %eax
testb %al, %al
je .L49
.L48:
.loc 2 206 0 is_stmt 1
movl $0, %eax
jmp .L50
.L49:
.loc 2 207 0
addb $1, -1(%rbp)
.LBE8:
.loc 2 202 0
addl $1, -8(%rbp)
.L47:
.loc 2 202 0 is_stmt 0 discriminator 1
cmpl $4, -8(%rbp)
setle %al
testb %al, %al
jne .L51
.LBE7:
.loc 2 209 0 is_stmt 1
movl $1, %eax
.L50:
.LBE6:
.loc 2 210 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE19:
.size _Z3t18v, .-_Z3t18v
.Letext0:
.section .debug_types.dwo,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0xc1
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x8a
.byte 0xda
.byte 0x59
.byte 0x6e
.byte 0x4d
.byte 0x5c
.byte 0xa
.byte 0x88
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C3"
.byte 0x4
.byte 0x1
.byte 0x2f
.long 0xa4
.uleb128 0x3
.uleb128 0x6
.byte 0x1
.byte 0x36
.long 0xa4
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x1
.byte 0x32
.uleb128 0x2
.long 0xab
.byte 0x1
.long 0x4c
.long 0x52
.uleb128 0x5
.long 0xb3
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x1
.byte 0x33
.uleb128 0x3
.long 0xab
.byte 0x1
.long 0x64
.long 0x6a
.uleb128 0x5
.long 0xb3
.byte 0
.uleb128 0x4
.uleb128 0x4
.byte 0x1
.byte 0x34
.uleb128 0x5
.long 0xab
.byte 0x1
.long 0x7c
.long 0x82
.uleb128 0x5
.long 0xb3
.byte 0
.uleb128 0x6
.string "f4"
.byte 0x1
.byte 0x35
.string "_ZN2C32f4Ev"
.long 0xb9
.byte 0x1
.long 0x9d
.uleb128 0x5
.long 0xb3
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.uleb128 0x8
.byte 0x8
.long 0xbf
.uleb128 0x9
.long 0xab
.byte 0
.section .debug_types,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0x6e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_types.dwo,"G",@progbits,wt.66526f88bcc798ab,comdat
.long 0xa9
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x4b
.byte 0xf9
.byte 0xce
.byte 0xbf
.byte 0xd8
.byte 0xf0
.byte 0x4a
.byte 0xae
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C2"
.byte 0x4
.byte 0x1
.byte 0x25
.long 0x97
.uleb128 0x3
.uleb128 0x6
.byte 0x1
.byte 0x2c
.long 0x97
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x1
.byte 0x28
.uleb128 0x7
.long 0x9e
.byte 0x1
.long 0x4c
.long 0x52
.uleb128 0x5
.long 0xa6
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x1
.byte 0x29
.uleb128 0x8
.long 0x9e
.byte 0x1
.long 0x64
.long 0x6a
.uleb128 0x5
.long 0xa6
.byte 0
.uleb128 0x4
.uleb128 0x4
.byte 0x1
.byte 0x2a
.uleb128 0x9
.long 0x9e
.byte 0x1
.long 0x7c
.long 0x82
.uleb128 0x5
.long 0xa6
.byte 0
.uleb128 0xa
.uleb128 0xa
.byte 0x1
.byte 0x2b
.uleb128 0xb
.long 0x9e
.byte 0x1
.long 0x90
.uleb128 0x5
.long 0xa6
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.byte 0
.section .debug_types,"G",@progbits,wt.66526f88bcc798ab,comdat
.long 0x6e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_types.dwo,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0xf9
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0xe3
.byte 0xad
.byte 0x5
.byte 0x3b
.byte 0x75
.byte 0xeb
.byte 0xfb
.byte 0xc7
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C1"
.byte 0x4
.byte 0x1
.byte 0x19
.long 0xe7
.uleb128 0x3
.uleb128 0x6
.byte 0x1
.byte 0x22
.long 0xe7
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x1
.byte 0x1c
.uleb128 0xc
.long 0xee
.byte 0x1
.long 0x4c
.long 0x52
.uleb128 0x5
.long 0xf6
.byte 0
.uleb128 0xb
.string "t1a"
.byte 0x1
.byte 0x1d
.string "_ZN2C13t1aEv"
.long 0xee
.byte 0x1
.long 0x73
.long 0x79
.uleb128 0x5
.long 0xf6
.byte 0
.uleb128 0xb
.string "t1_2"
.byte 0x1
.byte 0x1e
.string "_ZN2C14t1_2Ev"
.long 0xe7
.byte 0x1
.long 0x9c
.long 0xa2
.uleb128 0x5
.long 0xf6
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x1
.byte 0x1f
.uleb128 0xd
.long 0xee
.byte 0x1
.long 0xb4
.long 0xba
.uleb128 0x5
.long 0xf6
.byte 0
.uleb128 0x4
.uleb128 0x4
.byte 0x1
.byte 0x20
.uleb128 0xe
.long 0xee
.byte 0x1
.long 0xcc
.long 0xd2
.uleb128 0x5
.long 0xf6
.byte 0
.uleb128 0xa
.uleb128 0xa
.byte 0x1
.byte 0x21
.uleb128 0xf
.long 0xee
.byte 0x1
.long 0xe0
.uleb128 0x5
.long 0xf6
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.byte 0
.section .debug_types,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0x6e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_info.dwo,"e",@progbits
.Ldebug_info0:
.long 0x5af
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0xc
.string "GNU C++ 4.7.x-google 20120720 (prerelease)"
.byte 0x4
.string "dwp_test_1.cc"
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.byte 0x27
.byte 0x37
.byte 0xdc
.byte 0x2f
.byte 0x9
.byte 0xc6
.byte 0xf9
.byte 0x52
.uleb128 0xd
.string "C1"
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0xc6
.uleb128 0xe
.uleb128 0
.byte 0x1
.byte 0x1c
.uleb128 0xc
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x1
.byte 0x1
.byte 0x1f
.uleb128 0xd
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x4
.byte 0x1
.byte 0x20
.uleb128 0xe
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0xa
.byte 0x1
.byte 0x21
.uleb128 0xf
.long 0xcd
.byte 0x1
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0xf
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.uleb128 0xd
.string "C2"
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.long 0x118
.uleb128 0xe
.uleb128 0
.byte 0x1
.byte 0x28
.uleb128 0x7
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x1
.byte 0x1
.byte 0x29
.uleb128 0x8
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x4
.byte 0x1
.byte 0x2a
.uleb128 0x9
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0xa
.byte 0x1
.byte 0x2b
.uleb128 0xb
.long 0xcd
.byte 0x1
.byte 0
.uleb128 0xf
.byte 0x8
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.uleb128 0xd
.string "C3"
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0x151
.uleb128 0xe
.uleb128 0
.byte 0x1
.byte 0x32
.uleb128 0x2
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x1
.byte 0x1
.byte 0x33
.uleb128 0x3
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x4
.byte 0x1
.byte 0x34
.uleb128 0x5
.long 0xcd
.byte 0x1
.byte 0
.uleb128 0xf
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.uleb128 0x10
.string "f13i"
.byte 0x1
.byte 0x46
.string "_Z4f13iv"
.uleb128 0
.quad .LFE0-.LFB0
.uleb128 0x1
.byte 0x9c
.uleb128 0x11
.long 0x9d
.byte 0x2
.byte 0x1e
.uleb128 0x1
.quad .LFE1-.LFB1
.uleb128 0x1
.byte 0x9c
.long 0x191
.long 0x19b
.uleb128 0x12
.uleb128 0x10
.long 0x19b
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x13
.long 0xd5
.uleb128 0x14
.long 0xa7
.byte 0x2
.byte 0x26
.uleb128 0x2
.quad .LFE2-.LFB2
.uleb128 0x1
.byte 0x9c
.long 0x1ba
.long 0x1c4
.uleb128 0x12
.uleb128 0x10
.long 0x19b
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0xb1
.byte 0x2
.byte 0x2e
.uleb128 0x3
.quad .LFE3-.LFB3
.uleb128 0x1
.byte 0x9c
.long 0x1de
.long 0x1e8
.uleb128 0x12
.uleb128 0x10
.long 0x19b
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0xbb
.byte 0x2
.byte 0x36
.uleb128 0x4
.quad .LFE4-.LFB4
.uleb128 0x1
.byte 0x9c
.long 0x202
.long 0x20c
.uleb128 0x12
.uleb128 0x10
.long 0x19b
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0xef
.byte 0x2
.byte 0x3e
.uleb128 0x5
.quad .LFE5-.LFB5
.uleb128 0x1
.byte 0x9c
.long 0x226
.long 0x230
.uleb128 0x12
.uleb128 0x10
.long 0x230
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x13
.long 0x118
.uleb128 0x14
.long 0xf9
.byte 0x2
.byte 0x48
.uleb128 0x6
.quad .LFE6-.LFB6
.uleb128 0x1
.byte 0x9c
.long 0x24f
.long 0x259
.uleb128 0x12
.uleb128 0x10
.long 0x230
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0x103
.byte 0x2
.byte 0x52
.uleb128 0x7
.quad .LFE7-.LFB7
.uleb128 0x1
.byte 0x9c
.long 0x273
.long 0x27d
.uleb128 0x12
.uleb128 0x10
.long 0x230
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0x10d
.byte 0x2
.byte 0x5c
.uleb128 0x8
.quad .LFE8-.LFB8
.uleb128 0x1
.byte 0x9c
.long 0x297
.long 0x2a1
.uleb128 0x12
.uleb128 0x10
.long 0x230
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0x132
.byte 0x2
.byte 0x66
.uleb128 0x9
.quad .LFE9-.LFB9
.uleb128 0x1
.byte 0x9c
.long 0x2bb
.long 0x2c5
.uleb128 0x12
.uleb128 0x10
.long 0x2c5
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x13
.long 0x151
.uleb128 0x11
.long 0x13c
.byte 0x2
.byte 0x70
.uleb128 0xa
.quad .LFE10-.LFB10
.uleb128 0x1
.byte 0x9c
.long 0x2e4
.long 0x2ee
.uleb128 0x12
.uleb128 0x10
.long 0x2c5
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x15
.string "f11a"
.byte 0x2
.byte 0x78
.string "_Z4f11av"
.long 0xc6
.uleb128 0xb
.quad .LFE11-.LFB11
.uleb128 0x1
.byte 0x9c
.uleb128 0x11
.long 0x146
.byte 0x2
.byte 0x7e
.uleb128 0xc
.quad .LFE12-.LFB12
.uleb128 0x1
.byte 0x9c
.long 0x328
.long 0x332
.uleb128 0x12
.uleb128 0x10
.long 0x2c5
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x16
.string "t12"
.byte 0x2
.byte 0x86
.string "_Z3t12v"
.long 0xcd
.uleb128 0xd
.quad .LFE13-.LFB13
.uleb128 0x1
.byte 0x9c
.uleb128 0x16
.string "t13"
.byte 0x2
.byte 0x8e
.string "_Z3t13v"
.long 0xcd
.uleb128 0xe
.quad .LFE14-.LFB14
.uleb128 0x1
.byte 0x9c
.uleb128 0x17
.string "t14"
.byte 0x2
.byte 0x96
.string "_Z3t14v"
.long 0xcd
.uleb128 0xf
.quad .LFE15-.LFB15
.uleb128 0x1
.byte 0x9c
.long 0x3b6
.uleb128 0x18
.uleb128 0x10
.quad .LBE2-.LBB2
.uleb128 0x19
.string "s1"
.byte 0x2
.byte 0x98
.long 0x3b6
.uleb128 0x2
.byte 0x91
.sleb128 -24
.uleb128 0x19
.string "s2"
.byte 0x2
.byte 0x99
.long 0x3b6
.uleb128 0x2
.byte 0x91
.sleb128 -32
.byte 0
.byte 0
.uleb128 0x8
.byte 0x8
.long 0x3bc
.uleb128 0x13
.long 0x3c1
.uleb128 0x7
.byte 0x1
.byte 0x6
.string "char"
.uleb128 0x17
.string "t15"
.byte 0x2
.byte 0xa3
.string "_Z3t15v"
.long 0xcd
.uleb128 0x11
.quad .LFE16-.LFB16
.uleb128 0x1
.byte 0x9c
.long 0x411
.uleb128 0x18
.uleb128 0x12
.quad .LBE3-.LBB3
.uleb128 0x19
.string "s1"
.byte 0x2
.byte 0xa5
.long 0x411
.uleb128 0x2
.byte 0x91
.sleb128 -24
.uleb128 0x19
.string "s2"
.byte 0x2
.byte 0xa6
.long 0x411
.uleb128 0x2
.byte 0x91
.sleb128 -32
.byte 0
.byte 0
.uleb128 0x8
.byte 0x8
.long 0x417
.uleb128 0x13
.long 0x41c
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "wchar_t"
.uleb128 0x16
.string "t16"
.byte 0x2
.byte 0xb0
.string "_Z3t16v"
.long 0xcd
.uleb128 0x13
.quad .LFE17-.LFB17
.uleb128 0x1
.byte 0x9c
.uleb128 0x1a
.string "t17"
.byte 0x2
.byte 0xb8
.string "_Z3t17v"
.long 0xcd
.uleb128 0x14
.quad .LFE18-.LFB18
.uleb128 0x1
.byte 0x9c
.long 0x496
.uleb128 0x18
.uleb128 0x15
.quad .LBE4-.LBB4
.uleb128 0x19
.string "c"
.byte 0x2
.byte 0xba
.long 0x3c1
.uleb128 0x2
.byte 0x91
.sleb128 -17
.uleb128 0x18
.uleb128 0x16
.quad .LBE5-.LBB5
.uleb128 0x19
.string "i"
.byte 0x2
.byte 0xbb
.long 0xc6
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.byte 0
.byte 0
.uleb128 0x17
.string "t18"
.byte 0x2
.byte 0xc7
.string "_Z3t18v"
.long 0xcd
.uleb128 0x17
.quad .LFE19-.LFB19
.uleb128 0x1
.byte 0x9c
.long 0x4fe
.uleb128 0x18
.uleb128 0x18
.quad .LBE6-.LBB6
.uleb128 0x19
.string "c"
.byte 0x2
.byte 0xc9
.long 0x3c1
.uleb128 0x2
.byte 0x91
.sleb128 -17
.uleb128 0x18
.uleb128 0x19
.quad .LBE7-.LBB7
.uleb128 0x19
.string "i"
.byte 0x2
.byte 0xca
.long 0xc6
.uleb128 0x2
.byte 0x91
.sleb128 -24
.uleb128 0x18
.uleb128 0x1a
.quad .LBE8-.LBB8
.uleb128 0x19
.string "s"
.byte 0x2
.byte 0xcc
.long 0x3b6
.uleb128 0x2
.byte 0x91
.sleb128 -32
.byte 0
.byte 0
.byte 0
.byte 0
.uleb128 0x1b
.string "c3"
.byte 0x1
.byte 0x39
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.uleb128 0x1c
.string "v2"
.byte 0x1
.byte 0x3b
.long 0xc6
.uleb128 0x1c
.string "v3"
.byte 0x1
.byte 0x3c
.long 0xc6
.uleb128 0x1d
.long 0x3c1
.long 0x52b
.uleb128 0x1e
.byte 0
.uleb128 0x1c
.string "v4"
.byte 0x1
.byte 0x3d
.long 0x520
.uleb128 0x1c
.string "v5"
.byte 0x1
.byte 0x3e
.long 0x520
.uleb128 0x1d
.long 0x3b6
.long 0x54a
.uleb128 0x1e
.byte 0
.uleb128 0x1c
.string "t17data"
.byte 0x1
.byte 0x53
.long 0x53f
.uleb128 0x1f
.string "p6"
.byte 0x2
.byte 0x45
.long 0x566
.uleb128 0x2
.byte 0xfb
.uleb128 0x1b
.uleb128 0x8
.byte 0x8
.long 0xc6
.uleb128 0x1f
.string "p7"
.byte 0x2
.byte 0x4f
.long 0x566
.uleb128 0x2
.byte 0xfb
.uleb128 0x1c
.uleb128 0x1f
.string "p8"
.byte 0x2
.byte 0x59
.long 0x586
.uleb128 0x2
.byte 0xfb
.uleb128 0x1d
.uleb128 0x8
.byte 0x8
.long 0x3c1
.uleb128 0x1f
.string "p9"
.byte 0x2
.byte 0x63
.long 0x586
.uleb128 0x2
.byte 0xfb
.uleb128 0x1e
.uleb128 0x9
.long 0xc6
.uleb128 0x1f
.string "pfn"
.byte 0x2
.byte 0x6d
.long 0x5ac
.uleb128 0x2
.byte 0xfb
.uleb128 0x1f
.uleb128 0x8
.byte 0x8
.long 0x599
.byte 0
.section .debug_info,"",@progbits
.Lskeleton_debug_info0:
.long 0x7e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.uleb128 0x1
.long .Ldebug_ranges0+0
.quad 0
.long .Ldebug_line0
.byte 0x27
.byte 0x37
.byte 0xdc
.byte 0x2f
.byte 0x9
.byte 0xc6
.byte 0xf9
.byte 0x52
.long .Ldebug_ranges0
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_abbrev,"",@progbits
.Lskeleton_debug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0
.uleb128 0x55
.uleb128 0x17
.uleb128 0x11
.uleb128 0x1
.uleb128 0x10
.uleb128 0x17
.uleb128 0x2131
.uleb128 0x7
.uleb128 0x2132
.uleb128 0x17
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x41
.byte 0
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.byte 0
.section .debug_abbrev.dwo,"e",@progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x41
.byte 0x1
.uleb128 0x13
.uleb128 0xb
.uleb128 0x210f
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.uleb128 0x32
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x5
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x7
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x8
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x9
.uleb128 0x15
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xa
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xb
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xc
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0x8
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2131
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0xd
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0x69
.uleb128 0x20
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xe
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0xf
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.byte 0
.byte 0
.uleb128 0x10
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x11
.uleb128 0x2e
.byte 0x1
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x64
.uleb128 0x13
.uleb128 0x2116
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x12
.uleb128 0x5
.byte 0
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x13
.uleb128 0x26
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x14
.uleb128 0x2e
.byte 0x1
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x64
.uleb128 0x13
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x15
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x16
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2116
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x17
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2116
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x18
.uleb128 0xb
.byte 0x1
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0x19
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x1a
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x1b
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x1c
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x1d
.uleb128 0x1
.byte 0x1
.uleb128 0x49
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x1e
.uleb128 0x21
.byte 0
.byte 0
.byte 0
.uleb128 0x1f
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.byte 0
.section .debug_gnu_pubnames,"",@progbits
.Ldebug_pubnames0:
.long 0x15b
.value 0x2
.long .Lskeleton_debug_info0
.long 0x5b3
.long 0x15b
.byte 0x30
.string "f13i"
.long 0x177
.byte 0x30
.string "C1::testcase1"
.long 0x1a0
.byte 0x30
.string "C1::testcase2"
.long 0x1c4
.byte 0x30
.string "C1::testcase3"
.long 0x1e8
.byte 0x30
.string "C1::testcase4"
.long 0x20c
.byte 0x30
.string "C2::testcase1"
.long 0x235
.byte 0x30
.string "C2::testcase2"
.long 0x259
.byte 0x30
.string "C2::testcase3"
.long 0x27d
.byte 0x30
.string "C2::testcase4"
.long 0x2a1
.byte 0x30
.string "C3::testcase1"
.long 0x2ca
.byte 0x30
.string "C3::testcase2"
.long 0x2ee
.byte 0x30
.string "f11a"
.long 0x30e
.byte 0x30
.string "C3::testcase3"
.long 0x332
.byte 0x30
.string "t12"
.long 0x350
.byte 0x30
.string "t13"
.long 0x36e
.byte 0x30
.string "t14"
.long 0x3c9
.byte 0x30
.string "t15"
.long 0x427
.byte 0x30
.string "t16"
.long 0x445
.byte 0x30
.string "t17"
.long 0x496
.byte 0x30
.string "t18"
.long 0x559
.byte 0x20
.string "p6"
.long 0x56c
.byte 0x20
.string "p7"
.long 0x579
.byte 0x20
.string "p8"
.long 0x58c
.byte 0x20
.string "p9"
.long 0x59e
.byte 0x20
.string "pfn"
.long 0
.section .debug_gnu_pubtypes,"",@progbits
.Ldebug_pubtypes0:
.long 0x50
.value 0x2
.long .Lskeleton_debug_info0
.long 0x5b3
.long 0xc6
.byte 0x90
.string "int"
.long 0xcd
.byte 0x90
.string "bool"
.long 0x8d
.byte 0x10
.string "C1"
.long 0xdf
.byte 0x10
.string "C2"
.long 0x122
.byte 0x10
.string "C3"
.long 0x3c1
.byte 0x90
.string "char"
.long 0x41c
.byte 0x90
.string "wchar_t"
.long 0
.section .debug_aranges,"",@progbits
.long 0x3c
.value 0x2
.long .Lskeleton_debug_info0
.byte 0x8
.byte 0
.value 0
.value 0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad .LFB0
.quad .LFE0-.LFB0
.quad 0
.quad 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.quad .Ltext0
.quad .Letext0
.quad .LFB0
.quad .LFE0
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_line.dwo,"e",@progbits
.Lskeleton_debug_line0:
.long .LELT0-.LSLT0
.LSLT0:
.value 0x4
.long .LELTP0-.LASLTP0
.LASLTP0:
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0xf6
.byte 0xf2
.byte 0xd
.byte 0
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0
.byte 0
.byte 0
.byte 0x1
.byte 0
.byte 0
.byte 0x1
.byte 0
.string "dwp_test.h"
.uleb128 0
.uleb128 0
.uleb128 0
.string "dwp_test_1.cc"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.LELTP0:
.LELT0:
.section .debug_str_offsets.dwo,"e",@progbits
.long 0
.long 0xa
.long 0x14
.long 0x27
.long 0x3a
.long 0x44
.long 0x57
.long 0x5f
.long 0x72
.long 0x85
.long 0x98
.long 0xa2
.long 0xb5
.long 0xc8
.long 0xdb
.long 0xee
.long 0x101
.section .debug_str.dwo,"e",@progbits
.LASF0:
.string "testcase1"
.LASF1:
.string "testcase2"
.LASF2:
.string "_ZN2C39testcase1Ev"
.LASF3:
.string "_ZN2C39testcase2Ev"
.LASF4:
.string "testcase3"
.LASF5:
.string "_ZN2C39testcase3Ev"
.LASF6:
.string "member1"
.LASF7:
.string "_ZN2C29testcase1Ev"
.LASF8:
.string "_ZN2C29testcase2Ev"
.LASF9:
.string "_ZN2C29testcase3Ev"
.LASF10:
.string "testcase4"
.LASF11:
.string "_ZN2C29testcase4Ev"
.LASF12:
.string "_ZN2C19testcase1Ev"
.LASF13:
.string "_ZN2C19testcase2Ev"
.LASF14:
.string "_ZN2C19testcase3Ev"
.LASF15:
.string "_ZN2C19testcase4Ev"
.LASF16:
.string "this"
.section .debug_addr,"",@progbits
.Ldebug_addr0:
.quad .LFB0
.quad .LFB1
.quad .LFB2
.quad .LFB3
.quad .LFB4
.quad .LFB5
.quad .LFB6
.quad .LFB7
.quad .LFB8
.quad .LFB9
.quad .LFB10
.quad .LFB11
.quad .LFB12
.quad .LFB13
.quad .LFB14
.quad .LFB15
.quad .LBB2
.quad .LFB16
.quad .LBB3
.quad .LFB17
.quad .LFB18
.quad .LBB4
.quad .LBB5
.quad .LFB19
.quad .LBB6
.quad .LBB7
.quad .LBB8
.quad p6
.quad p7
.quad p8
.quad p9
.quad pfn
.ident "GCC: (Google_crosstoolv16-gcc-4.7.x-grtev3) 4.7.x-google 20120720 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
tactcomplabs/xbgas-binutils-gdb | 1,083 | gold/testsuite/arm_thm_jump11.s | # arm_thm_jump11.s
# Test R_ARM_THM_JUMP11 relocations just within the branch range limits.
.syntax unified
.arch armv5te
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
b.n _backward_target
.size _backward_test, .-_backward_test
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
b.n _forward_target
.size _forward_test, .-_forward_test
.section .text.post,"x"
# Add padding so that target is just in branch range.
.space 8
.global _forward_target
.code 16
.thumb_func
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
tactcomplabs/xbgas-binutils-gdb | 1,085 | gold/testsuite/arm_thm_jump8.s | # arm_thm_jump8.s
# Test R_ARM_THM_JUMP8 relocations just within the branch range limits.
.syntax unified
.arch armv5te
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
beq.n _backward_target
.size _backward_test, .-_backward_test
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
beq.n _forward_target
.size _forward_test, .-_forward_test
.section .text.post,"x"
# Add padding so that target is just in branch range.
.space 8
.global _forward_target
.code 16
.thumb_func
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
tactcomplabs/xbgas-binutils-gdb | 22,230 | gold/testsuite/dwp_test_main.s | .file "dwp_test_main.cc"
.text
.Ltext0:
.section .rodata
.LC0:
.string "dwp_test_main.cc"
.LC1:
.string "c1.testcase1()"
.LC2:
.string "c1.t1a()"
.LC3:
.string "c1.testcase2()"
.LC4:
.string "c1.testcase3()"
.LC5:
.string "c1.testcase4()"
.LC6:
.string "c2.testcase1()"
.LC7:
.string "c2.testcase2()"
.LC8:
.string "c2.testcase3()"
.LC9:
.string "c2.testcase4()"
.LC10:
.string "c3.testcase1()"
.LC11:
.string "c3.testcase2()"
.LC12:
.string "c3.testcase3()"
.LC13:
.string "t12()"
.LC14:
.string "t13()"
.LC15:
.string "t16()"
.LC16:
.string "t16a()"
.LC17:
.string "t17()"
.LC18:
.string "t18()"
.text
.globl main
.type main, @function
main:
.LFB1:
.file 1 "dwp_test_main.cc"
.loc 1 31 0
.cfi_startproc
.cfi_personality 0x3,__gxx_personality_v0
.cfi_lsda 0x3,.LLSDA1
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $32, %rsp
.LBB2:
.loc 1 36 0
movl $789, v3(%rip)
.LBB3:
.loc 1 37 0
movl $0, -4(%rbp)
jmp .L2
.L3:
.loc 1 38 0
movl -4(%rbp), %eax
cltq
movzbl v4(%rax), %edx
movl -4(%rbp), %eax
cltq
movb %dl, v5(%rax)
.loc 1 37 0 discriminator 2
addl $1, -4(%rbp)
.L2:
.loc 1 37 0 is_stmt 0 discriminator 1
cmpl $12, -4(%rbp)
setle %al
testb %al, %al
jne .L3
.LBE3:
.loc 1 40 0 is_stmt 1
leaq -16(%rbp), %rax
movq %rax, %rdi
.LEHB0:
call _ZN2C19testcase1Ev
.loc 1 40 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L4
.loc 1 40 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $40, %edx
movl $.LC0, %esi
movl $.LC1, %edi
call __assert_fail
.L4:
.loc 1 41 0 is_stmt 1
leaq -16(%rbp), %rax
movq %rax, %rdi
call _ZN2C13t1aEv
.loc 1 41 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L5
.loc 1 41 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $41, %edx
movl $.LC0, %esi
movl $.LC2, %edi
call __assert_fail
.L5:
.loc 1 42 0 is_stmt 1
leaq -16(%rbp), %rax
movq %rax, %rdi
call _ZN2C19testcase2Ev
.loc 1 42 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L6
.loc 1 42 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $42, %edx
movl $.LC0, %esi
movl $.LC3, %edi
call __assert_fail
.L6:
.loc 1 43 0 is_stmt 1
leaq -16(%rbp), %rax
movq %rax, %rdi
call _ZN2C19testcase3Ev
.loc 1 43 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L7
.loc 1 43 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $43, %edx
movl $.LC0, %esi
movl $.LC4, %edi
call __assert_fail
.L7:
.loc 1 44 0 is_stmt 1
leaq -16(%rbp), %rax
movq %rax, %rdi
call _ZN2C19testcase4Ev
.loc 1 44 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L8
.loc 1 44 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $44, %edx
movl $.LC0, %esi
movl $.LC5, %edi
call __assert_fail
.L8:
.loc 1 45 0 is_stmt 1
leaq -32(%rbp), %rax
movq %rax, %rdi
call _ZN2C29testcase1Ev
.loc 1 45 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L9
.loc 1 45 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $45, %edx
movl $.LC0, %esi
movl $.LC6, %edi
call __assert_fail
.L9:
.loc 1 46 0 is_stmt 1
leaq -32(%rbp), %rax
movq %rax, %rdi
call _ZN2C29testcase2Ev
.loc 1 46 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L10
.loc 1 46 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $46, %edx
movl $.LC0, %esi
movl $.LC7, %edi
call __assert_fail
.L10:
.loc 1 47 0 is_stmt 1
leaq -32(%rbp), %rax
movq %rax, %rdi
call _ZN2C29testcase3Ev
.loc 1 47 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L11
.loc 1 47 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $47, %edx
movl $.LC0, %esi
movl $.LC8, %edi
call __assert_fail
.L11:
.loc 1 48 0 is_stmt 1
leaq -32(%rbp), %rax
movq %rax, %rdi
call _ZN2C29testcase4Ev
.loc 1 48 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L12
.loc 1 48 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $48, %edx
movl $.LC0, %esi
movl $.LC9, %edi
call __assert_fail
.L12:
.loc 1 49 0 is_stmt 1
movl $c3, %edi
call _ZN2C39testcase1Ev
.loc 1 49 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L13
.loc 1 49 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $49, %edx
movl $.LC0, %esi
movl $.LC10, %edi
call __assert_fail
.L13:
.loc 1 50 0 is_stmt 1
movl $c3, %edi
call _ZN2C39testcase2Ev
.loc 1 50 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L14
.loc 1 50 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $50, %edx
movl $.LC0, %esi
movl $.LC11, %edi
call __assert_fail
.L14:
.loc 1 51 0 is_stmt 1
movl $c3, %edi
call _ZN2C39testcase3Ev
.loc 1 51 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L15
.loc 1 51 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $51, %edx
movl $.LC0, %esi
movl $.LC12, %edi
call __assert_fail
.L15:
.loc 1 52 0 is_stmt 1
call _Z3t12v
.loc 1 52 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L16
.loc 1 52 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $52, %edx
movl $.LC0, %esi
movl $.LC13, %edi
call __assert_fail
.L16:
.loc 1 53 0 is_stmt 1
call _Z3t13v
.loc 1 53 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L17
.loc 1 53 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $53, %edx
movl $.LC0, %esi
movl $.LC14, %edi
call __assert_fail
.L17:
.loc 1 54 0 is_stmt 1
call _Z3t16v
.loc 1 54 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L18
.loc 1 54 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $54, %edx
movl $.LC0, %esi
movl $.LC15, %edi
call __assert_fail
.L18:
.loc 1 55 0 is_stmt 1
call _Z4t16av
.loc 1 55 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L19
.loc 1 55 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $55, %edx
movl $.LC0, %esi
movl $.LC16, %edi
call __assert_fail
.L19:
.loc 1 56 0 is_stmt 1
call _Z3t17v
.loc 1 56 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L20
.loc 1 56 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $56, %edx
movl $.LC0, %esi
movl $.LC17, %edi
call __assert_fail
.L20:
.loc 1 57 0 is_stmt 1
call _Z3t18v
.LEHE0:
.loc 1 57 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L21
.loc 1 57 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $57, %edx
movl $.LC0, %esi
movl $.LC18, %edi
call __assert_fail
.L21:
.loc 1 58 0 is_stmt 1
movl $0, %eax
jmp .L25
.L24:
movq %rax, %rdi
.LEHB1:
call _Unwind_Resume
.LEHE1:
.L25:
.LBE2:
.loc 1 59 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE1:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA1:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE1-.LLSDACSB1
.LLSDACSB1:
.uleb128 .LEHB0-.LFB1
.uleb128 .LEHE0-.LEHB0
.uleb128 .L24-.LFB1
.uleb128 0
.uleb128 .LEHB1-.LFB1
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE1:
.text
.size main, .-main
.section .rodata
.type _ZZ4mainE19__PRETTY_FUNCTION__, @object
.size _ZZ4mainE19__PRETTY_FUNCTION__, 11
_ZZ4mainE19__PRETTY_FUNCTION__:
.string "int main()"
.text
.Letext0:
.file 2 "dwp_test.h"
.section .debug_types.dwo,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0xf7
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x8a
.byte 0xda
.byte 0x59
.byte 0x6e
.byte 0x4d
.byte 0x5c
.byte 0xa
.byte 0x88
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C3"
.byte 0x4
.byte 0x2
.byte 0x2f
.long 0xda
.uleb128 0x3
.uleb128 0x3
.byte 0x2
.byte 0x36
.long 0xda
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x2
.byte 0x32
.string "_ZN2C39testcase1Ev"
.long 0xe1
.byte 0x1
.long 0x5e
.long 0x64
.uleb128 0x5
.long 0xe9
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x2
.byte 0x33
.string "_ZN2C39testcase2Ev"
.long 0xe1
.byte 0x1
.long 0x88
.long 0x8e
.uleb128 0x5
.long 0xe9
.byte 0
.uleb128 0x4
.uleb128 0x2
.byte 0x2
.byte 0x34
.string "_ZN2C39testcase3Ev"
.long 0xe1
.byte 0x1
.long 0xb2
.long 0xb8
.uleb128 0x5
.long 0xe9
.byte 0
.uleb128 0x6
.string "f4"
.byte 0x2
.byte 0x35
.string "_ZN2C32f4Ev"
.long 0xef
.byte 0x1
.long 0xd3
.uleb128 0x5
.long 0xe9
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.uleb128 0x8
.byte 0x8
.long 0xf5
.uleb128 0x9
.long 0xe1
.byte 0
.section .debug_types,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0x71
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_main.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_types.dwo,"G",@progbits,wt.66526f88bcc798ab,comdat
.long 0xf1
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x4b
.byte 0xf9
.byte 0xce
.byte 0xbf
.byte 0xd8
.byte 0xf0
.byte 0x4a
.byte 0xae
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C2"
.byte 0x4
.byte 0x2
.byte 0x25
.long 0xdf
.uleb128 0x3
.uleb128 0x3
.byte 0x2
.byte 0x2c
.long 0xdf
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x2
.byte 0x28
.string "_ZN2C29testcase1Ev"
.long 0xe6
.byte 0x1
.long 0x5e
.long 0x64
.uleb128 0x5
.long 0xee
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x2
.byte 0x29
.string "_ZN2C29testcase2Ev"
.long 0xe6
.byte 0x1
.long 0x88
.long 0x8e
.uleb128 0x5
.long 0xee
.byte 0
.uleb128 0x4
.uleb128 0x2
.byte 0x2
.byte 0x2a
.string "_ZN2C29testcase3Ev"
.long 0xe6
.byte 0x1
.long 0xb2
.long 0xb8
.uleb128 0x5
.long 0xee
.byte 0
.uleb128 0xa
.uleb128 0x4
.byte 0x2
.byte 0x2b
.string "_ZN2C29testcase4Ev"
.long 0xe6
.byte 0x1
.long 0xd8
.uleb128 0x5
.long 0xee
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.byte 0
.section .debug_types,"G",@progbits,wt.66526f88bcc798ab,comdat
.long 0x71
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_main.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_types.dwo,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0x141
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0xe3
.byte 0xad
.byte 0x5
.byte 0x3b
.byte 0x75
.byte 0xeb
.byte 0xfb
.byte 0xc7
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C1"
.byte 0x4
.byte 0x2
.byte 0x19
.long 0x12f
.uleb128 0x3
.uleb128 0x3
.byte 0x2
.byte 0x22
.long 0x12f
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x2
.byte 0x1c
.string "_ZN2C19testcase1Ev"
.long 0x136
.byte 0x1
.long 0x5e
.long 0x64
.uleb128 0x5
.long 0x13e
.byte 0
.uleb128 0xb
.string "t1a"
.byte 0x2
.byte 0x1d
.string "_ZN2C13t1aEv"
.long 0x136
.byte 0x1
.long 0x85
.long 0x8b
.uleb128 0x5
.long 0x13e
.byte 0
.uleb128 0xb
.string "t1_2"
.byte 0x2
.byte 0x1e
.string "_ZN2C14t1_2Ev"
.long 0x12f
.byte 0x1
.long 0xae
.long 0xb4
.uleb128 0x5
.long 0x13e
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x2
.byte 0x1f
.string "_ZN2C19testcase2Ev"
.long 0x136
.byte 0x1
.long 0xd8
.long 0xde
.uleb128 0x5
.long 0x13e
.byte 0
.uleb128 0x4
.uleb128 0x2
.byte 0x2
.byte 0x20
.string "_ZN2C19testcase3Ev"
.long 0x136
.byte 0x1
.long 0x102
.long 0x108
.uleb128 0x5
.long 0x13e
.byte 0
.uleb128 0xa
.uleb128 0x4
.byte 0x2
.byte 0x21
.string "_ZN2C19testcase4Ev"
.long 0x136
.byte 0x1
.long 0x128
.uleb128 0x5
.long 0x13e
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.byte 0
.section .debug_types,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0x71
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_main.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_info.dwo,"e",@progbits
.Ldebug_info0:
.long 0x178
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0xc
.string "GNU C++ 4.7.x-google 20120720 (prerelease)"
.byte 0x4
.string "dwp_test_main.cc"
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.byte 0xc8
.byte 0xeb
.byte 0x9a
.byte 0x5c
.byte 0xd9
.byte 0x51
.byte 0xba
.byte 0xe5
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0xd
.string "main"
.byte 0x1
.byte 0x1e
.long 0x90
.uleb128 0
.quad .LFE1-.LFB1
.uleb128 0x1
.byte 0x9c
.long 0x11b
.uleb128 0xe
.uleb128 0x1
.quad .LBE2-.LBB2
.uleb128 0xf
.string "c1"
.byte 0x1
.byte 0x20
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.uleb128 0x2
.byte 0x91
.sleb128 -32
.uleb128 0xf
.string "c2"
.byte 0x1
.byte 0x21
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.uleb128 0x2
.byte 0x91
.sleb128 -48
.uleb128 0x10
.string "__PRETTY_FUNCTION__"
.long 0x13f
.uleb128 0x2
.byte 0xfb
.uleb128 0x2
.uleb128 0xe
.uleb128 0x3
.quad .LBE3-.LBB3
.uleb128 0x11
.string "i"
.byte 0x1
.byte 0x25
.long 0x90
.uleb128 0x2
.byte 0x91
.sleb128 -20
.byte 0
.byte 0
.byte 0
.uleb128 0x12
.long 0x137
.long 0x12b
.uleb128 0x13
.long 0x12b
.byte 0xa
.byte 0
.uleb128 0x7
.byte 0x8
.byte 0x7
.string "sizetype"
.uleb128 0x7
.byte 0x1
.byte 0x6
.string "char"
.uleb128 0x14
.long 0x11b
.uleb128 0x15
.string "c3"
.byte 0x2
.byte 0x39
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.uleb128 0x16
.string "v3"
.byte 0x2
.byte 0x3c
.long 0x90
.uleb128 0x12
.long 0x137
.long 0x167
.uleb128 0x17
.byte 0
.uleb128 0x16
.string "v4"
.byte 0x2
.byte 0x3d
.long 0x15c
.uleb128 0x16
.string "v5"
.byte 0x2
.byte 0x3e
.long 0x15c
.byte 0
.section .debug_info,"",@progbits
.Lskeleton_debug_info0:
.long 0x81
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.uleb128 0x1
.quad .Ltext0
.quad .Letext0-.Ltext0
.long .Ldebug_line0
.byte 0xc8
.byte 0xeb
.byte 0x9a
.byte 0x5c
.byte 0xd9
.byte 0x51
.byte 0xba
.byte 0xe5
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_main.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_abbrev,"",@progbits
.Lskeleton_debug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.uleb128 0x2131
.uleb128 0x7
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x41
.byte 0
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.byte 0
.section .debug_abbrev.dwo,"e",@progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x41
.byte 0x1
.uleb128 0x13
.uleb128 0xb
.uleb128 0x210f
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.uleb128 0x32
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x5
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x7
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x8
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x9
.uleb128 0x15
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xa
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xb
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xc
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0x8
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2131
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0xd
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2116
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xe
.uleb128 0xb
.byte 0x1
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0xf
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x10
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x11
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x12
.uleb128 0x1
.byte 0x1
.uleb128 0x49
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x13
.uleb128 0x21
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2f
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x14
.uleb128 0x26
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x15
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x16
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x17
.uleb128 0x21
.byte 0
.byte 0
.byte 0
.byte 0
.section .debug_gnu_pubnames,"",@progbits
.Ldebug_pubnames0:
.long 0x18
.value 0x2
.long .Lskeleton_debug_info0
.long 0x17c
.long 0x9f
.byte 0x30
.string "main"
.long 0
.section .debug_gnu_pubtypes,"",@progbits
.Ldebug_pubtypes0:
.long 0x51
.value 0x2
.long .Lskeleton_debug_info0
.long 0x17c
.long 0x90
.byte 0x90
.string "int"
.long 0x97
.byte 0x90
.string "bool"
.long 0
.byte 0x10
.string "C1"
.long 0
.byte 0x10
.string "C2"
.long 0
.byte 0x10
.string "C3"
.long 0x12b
.byte 0x90
.string "sizetype"
.long 0x137
.byte 0x90
.string "char"
.long 0
.section .debug_aranges,"",@progbits
.long 0x2c
.value 0x2
.long .Lskeleton_debug_info0
.byte 0x8
.byte 0
.value 0
.value 0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_line.dwo,"e",@progbits
.Lskeleton_debug_line0:
.long .LELT0-.LSLT0
.LSLT0:
.value 0x4
.long .LELTP0-.LASLTP0
.LASLTP0:
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0xf6
.byte 0xf2
.byte 0xd
.byte 0
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0
.byte 0
.byte 0
.byte 0x1
.byte 0
.byte 0
.byte 0x1
.byte 0
.string "dwp_test_main.cc"
.uleb128 0
.uleb128 0
.uleb128 0
.string "dwp_test.h"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.LELTP0:
.LELT0:
.section .debug_str_offsets.dwo,"e",@progbits
.long 0
.long 0xa
.long 0x14
.long 0x1e
.long 0x26
.section .debug_str.dwo,"e",@progbits
.LASF0:
.string "testcase1"
.LASF1:
.string "testcase2"
.LASF2:
.string "testcase3"
.LASF3:
.string "member1"
.LASF4:
.string "testcase4"
.section .debug_addr,"",@progbits
.Ldebug_addr0:
.quad .LFB1
.quad .LBB2
.quad _ZZ4mainE19__PRETTY_FUNCTION__
.quad .LBB3
.ident "GCC: (Google_crosstoolv16-gcc-4.7.x-grtev3) 4.7.x-google 20120720 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
tactcomplabs/xbgas-binutils-gdb | 1,304 | gold/testsuite/aarch64_relocs.s | .text
test_R_AARCH64_MOVW_UABS_G0:
movz x4, :abs_g0:abs_0x1234
movz x4, :abs_g0:abs_0x1234 + 4
test_R_AARCH64_MOVW_UABS_G0_NC:
movz x4, :abs_g0_nc:abs_0x1234
movz x4, :abs_g0_nc:abs_0x1234 + 0x45000
test_R_AARCH64_MOVW_UABS_G1:
movz x4, :abs_g1:abs_0x1234 - 4
movz x4, :abs_g1:abs_0x11000
movz x4, :abs_g1:abs_0x45000 + 0x20010
test_R_AARCH64_MOVW_UABS_G1_NC:
movz x4, :abs_g1_nc:abs_0x1234 - 4
movz x4, :abs_g1_nc:abs_0x11000
movz x4, :abs_g1_nc:abs_0x45000 + 0x100020010
test_R_AARCH64_MOVW_UABS_G2:
movz x4, :abs_g2:abs_0x45000 + 0x20010
movz x4, :abs_g2:abs_0x3600010000 + 0x100020010
test_R_AARCH64_MOVW_UABS_G2_NC:
movz x4, :abs_g2_nc:abs_0x45000 + 0x20010
movz x4, :abs_g2_nc:abs_0x3600010000 + 0x3000100020010
test_R_AARCH64_MOVW_UABS_G3:
movz x4, :abs_g3:abs_0x3600010000 + 0x100020010
movz x4, :abs_g3:abs_0x3600010000 + 0x3000100020010
test_R_AARCH64_MOVW_SABS_G0:
movz x4, :abs_g0_s:abs_0x1234 + 4
movz x4, :abs_g0_s:abs_0x1234 - 0x2345
test_R_AARCH64_MOVW_SABS_G1:
movz x4, :abs_g1_s:abs_0x1234 - 0x2345
movz x4, :abs_g1_s:abs_0x45000 + 0x20010
movz x4, :abs_g1_s:abs_0x45000 - 0x56000
test_R_AARCH64_MOVW_SABS_G2:
movz x4, :abs_g2_s:abs_0x45000 + 0x20010
movz x4, :abs_g2_s:abs_0x3600010000 + 0x100020010
movz x4, :abs_g2_s:abs_0x3600010000 - 0x4400010000
|
tactcomplabs/xbgas-binutils-gdb | 1,301 | gold/testsuite/thumb_bl_out_of_range.s | # thumb_bl_out_of_range.s
# Test THUMB/THUMB-2 bl instructions just out of the branch range limits.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just output of branch range.
.space 6
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Use 256-byte alignment so that we know where the stubs start.
.align 8
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
bl _backward_target
.size _backward_test, .-_backward_test
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
bl _forward_target
.size _forward_test, .-_forward_test
# switch back to ARM mode so that stubs are disassembled correctly.
.align 2
.code 32
# Align stub table for address matching.
.align 8
.section .text.post,"x"
# Add padding so that target is just out of branch range.
.space 12
.global _forward_target
.code 16
.thumb_func
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
tactcomplabs/xbgas-binutils-gdb | 1,074 | gold/testsuite/gnu_property_b.S | #define NT_GNU_PROPERTY_TYPE_0 5
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
#define GNU_PROPERTY_X86_ISA_1_USED 0xc0010002
#define GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#if __SIZEOF_PTRDIFF_T__ == 8
# define ALIGN 3
#elif __SIZEOF_PTRDIFF_T__ == 4
# define ALIGN 2
#endif
.section ".note.gnu.property", "a"
.p2align ALIGN
.long 1f - 0f /* name length */
.long 3f - 2f /* data length */
.long NT_GNU_PROPERTY_TYPE_0 /* note type */
0: .asciz "GNU" /* vendor name */
1:
.p2align ALIGN
2: .long GNU_PROPERTY_NO_COPY_ON_PROTECTED /* pr_type. */
.long 0 /* pr_datasz. */
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_USED
.long 4
.byte 0x01,0x11,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_NEEDED
.long 4
.byte 0x01,0x11,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_FEATURE_1_AND
.long 4
.byte 0x03,0x00,0x00,0x00
.p2align ALIGN
3:
|
tactcomplabs/xbgas-binutils-gdb | 10,965 | ld/emultempl/spu_ovl.S | /* Overlay manager for SPU.
Copyright (C) 2006-2022 Free Software Foundation, Inc.
This file is part of the GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* MFC DMA defn's. */
#define MFC_GET_CMD 0x40
#define MFC_MAX_DMA_SIZE 0x4000
#define MFC_TAG_UPDATE_ALL 2
#define MFC_TAG_ID 0
/* Register usage. */
#define reserved1 $75
#define parm $75
#define tab1 reserved1
#define tab2 reserved1
#define vma reserved1
#define oldvma reserved1
#define newmask reserved1
#define map reserved1
#define reserved2 $76
#define off1 reserved2
#define off2 reserved2
#define present1 reserved2
#define present2 reserved2
#define sz reserved2
#define cmp reserved2
#define add64 reserved2
#define cgbits reserved2
#define off3 reserved2
#define off4 reserved2
#define addr4 reserved2
#define off5 reserved2
#define tagstat reserved2
#define reserved3 $77
#define size1 reserved3
#define size2 reserved3
#define rv3 reserved3
#define ealo reserved3
#define cmd reserved3
#define off64 reserved3
#define tab3 reserved3
#define tab4 reserved3
#define tab5 reserved3
#define reserved4 $78
#define ovl reserved4
#define rv2 reserved4
#define rv5 reserved4
#define cgshuf reserved4
#define newovl reserved4
#define irqtmp1 reserved4
#define irqtmp2 reserved4
#define reserved5 $79
#define target reserved5
#define save1 $74
#define rv4 save1
#define rv7 save1
#define tagid save1
#define maxsize save1
#define pbyte save1
#define pbit save1
#define save2 $73
#define cur save2
#define rv6 save2
#define osize save2
#define zovl save2
#define oldovl save2
#define newvma save2
#define save3 $72
#define rv1 save3
#define ea64 save3
#define buf3 save3
#define genwi save3
#define newmap save3
#define oldmask save3
#define save4 $71
#define irq_stat save4
.text
.align 4
.type __rv_pattern, @object
.size __rv_pattern, 16
__rv_pattern:
.word 0x00010203, 0x10111213, 0x80808080, 0x80808080
.type __cg_pattern, @object
.size __cg_pattern, 16
__cg_pattern:
.word 0x04050607, 0x80808080, 0x80808080, 0x80808080
.type __ovly_current, @object
.size __ovly_current, 16
__ovly_current:
.space 16
/*
* __ovly_return - stub for returning from overlay functions.
*
* On entry the four slots of $lr are:
* __ovly_return, prev ovl index, caller return addr, undefined.
*
* Load the previous overlay and jump to the caller return address.
* Updates __ovly_current.
*/
.align 4
.global __ovly_return
.type __ovly_return, @function
__ovly_return:
ila tab1, _ovly_table - 16 # 0,2 0
shlqbyi ovl, $lr, 4 # 1,4 0
#nop
shlqbyi target, $lr, 8 # 1,4 1
#nop; lnop
#nop; lnop
shli off1, ovl, 4 # 0,4 4
#lnop
#nop
hbr ovly_ret9, target # 1,15 5
#nop; lnop
#nop; lnop
#nop
lqx vma, tab1, off1 # 1,6 8
#ifdef OVLY_IRQ_SAVE
nop
stqd save4, -64($sp) # 1,6 9
#else
#nop; lnop
#endif
#nop; lnop
#nop; lnop
#nop; lnop
#nop; lnop
#nop
rotqbyi size1, vma, 4 # 1,4 14
#nop
stqd save3, -48($sp) # 1,6 15
#nop
stqd save2, -32($sp) # 1,6 16
#nop
stqd save1, -16($sp) # 1,6 17
andi present1, size1, 1 # 0,2 18
stqr ovl, __ovly_current # 1,6 18
#nop; lnop
#nop
brz present1, do_load # 1,4 20
ovly_ret9:
#nop
bi target # 1,4 21
/*
* __ovly_load - copy an overlay partion to local store.
*
* On entry $75 points to a word consisting of the overlay index in
* the top 14 bits, and the target address in the bottom 18 bits.
*
* Sets up $lr to return via __ovly_return. If $lr is already set
* to return via __ovly_return, don't change it. In that case we
* have a tail call from one overlay function to another.
* Updates __ovly_current.
*/
.align 3
.global __ovly_load
.type __ovly_load, @function
__ovly_load:
#if OVL_STUB_SIZE == 8
########
#nop
lqd target, 0(parm) # 1,6 -11
#nop; lnop
#nop; lnop
#nop; lnop
#nop; lnop
#nop; lnop
#nop
rotqby target, target, parm # 1,4 -5
ila tab2, _ovly_table - 16 # 0,2 -4
stqd save3, -48($sp) # 1,6 -4
#nop
stqd save2, -32($sp) # 1,6 -3
#nop
stqd save1, -16($sp) # 1,6 -2
rotmi ovl, target, -18 # 0,4 -1
hbr ovly_load9, target # 1,15 -1
ila rv1, __ovly_return # 0,2 0
#lnop
#nop; lnop
#nop
lqr cur, __ovly_current # 1,6 2
shli off2, ovl, 4 # 0,4 3
stqr ovl, __ovly_current # 1,6 3
ceq rv2, $lr, rv1 # 0,2 4
lqr rv3, __rv_pattern # 1,6 4
#nop; lnop
#nop; lnop
#nop
lqx vma, tab2, off2 # 1,6 7
########
#else /* OVL_STUB_SIZE == 16 */
########
ila tab2, _ovly_table - 16 # 0,2 0
stqd save3, -48($sp) # 1,6 0
ila rv1, __ovly_return # 0,2 1
stqd save2, -32($sp) # 1,6 1
shli off2, ovl, 4 # 0,4 2
lqr cur, __ovly_current # 1,6 2
nop
stqr ovl, __ovly_current # 1,6 3
ceq rv2, $lr, rv1 # 0,2 4
lqr rv3, __rv_pattern # 1,6 4
#nop
hbr ovly_load9, target # 1,15 5
#nop
lqx vma, tab2, off2 # 1,6 6
#nop
stqd save1, -16($sp) # 1,6 7
########
#endif
#nop; lnop
#nop; lnop
#nop
shufb rv4, rv1, cur, rv3 # 1,4 10
#nop
fsmb rv5, rv2 # 1,4 11
#nop
rotqmbyi rv6, $lr, -8 # 1,4 12
#nop
rotqbyi size2, vma, 4 # 1,4 13
#nop
lqd save3, -48($sp) # 1,6 14
#nop; lnop
or rv7, rv4, rv6 # 0,2 16
lqd save2, -32($sp) # 1,6 16
andi present2, size2, 1 # 0,2 17
#ifdef OVLY_IRQ_SAVE
stqd save4, -64($sp) # 1,6 17
#else
lnop # 1,0 17
#endif
selb $lr, rv7, $lr, rv5 # 0,2 18
lqd save1, -16($sp) # 1,6 18
#nop
brz present2, do_load # 1,4 19
ovly_load9:
#nop
bi target # 1,4 20
/* If we get here, we are about to load a new overlay.
* "vma" contains the relevant entry from _ovly_table[].
* extern struct {
* u32 vma;
* u32 size;
* u32 file_offset;
* u32 buf;
* } _ovly_table[];
*/
.align 3
.global __ovly_load_event
.type __ovly_load_event, @function
__ovly_load_event:
do_load:
#ifdef OVLY_IRQ_SAVE
ila irqtmp1, do_load10 # 0,2 -5
rotqbyi sz, vma, 8 # 1,4 -5
#nop
rdch irq_stat, $SPU_RdMachStat # 1,6 -4
#nop
bid irqtmp1 # 1,4 -3
do_load10:
nop
#else
#nop
rotqbyi sz, vma, 8 # 1,4 0
#endif
rotqbyi osize, vma, 4 # 1,4 1
#nop
lqa ea64, _EAR_ # 1,6 2
#nop
lqr cgshuf, __cg_pattern # 1,6 3
/* We could predict the branch at the end of this loop by adding a few
instructions, and there are plenty of free cycles to do so without
impacting loop execution time. However, it doesn't make a great
deal of sense since we need to wait for the dma to complete anyway. */
__ovly_xfer_loop:
#nop
rotqmbyi off64, sz, -4 # 1,4 4
#nop; lnop
#nop; lnop
#nop; lnop
cg cgbits, ea64, off64 # 0,2 8
#lnop
#nop; lnop
#nop
shufb add64, cgbits, cgbits, cgshuf # 1,4 10
#nop; lnop
#nop; lnop
#nop; lnop
addx add64, ea64, off64 # 0,2 14
#lnop
ila maxsize, MFC_MAX_DMA_SIZE # 0,2 15
lnop
ori ea64, add64, 0 # 0,2 16
rotqbyi ealo, add64, 4 # 1,4 16
cgt cmp, osize, maxsize # 0,2 17
wrch $MFC_LSA, vma # 1,6 17
#nop; lnop
selb sz, osize, maxsize, cmp # 0,2 19
wrch $MFC_EAH, ea64 # 1,6 19
ila tagid, MFC_TAG_ID # 0,2 20
wrch $MFC_EAL, ealo # 1,6 20
ila cmd, MFC_GET_CMD # 0,2 21
wrch $MFC_Size, sz # 1,6 21
sf osize, sz, osize # 0,2 22
wrch $MFC_TagId, tagid # 1,6 22
a vma, vma, sz # 0,2 23
wrch $MFC_Cmd, cmd # 1,6 23
#nop
brnz osize, __ovly_xfer_loop # 1,4 24
/* Now update our data structions while waiting for DMA to complete.
Low bit of .size needs to be cleared on the _ovly_table entry
corresponding to the evicted overlay, and set on the entry for the
newly loaded overlay. Note that no overlay may in fact be evicted
as _ovly_buf_table[] starts with all zeros. Don't zap .size entry
for zero index! Also of course update the _ovly_buf_table entry. */
#nop
lqr newovl, __ovly_current # 1,6 25
#nop; lnop
#nop; lnop
#nop; lnop
#nop; lnop
#nop; lnop
shli off3, newovl, 4 # 0,4 31
#lnop
ila tab3, _ovly_table - 16 # 0,2 32
#lnop
#nop
fsmbi pbyte, 0x100 # 1,4 33
#nop; lnop
#nop
lqx vma, tab3, off3 # 1,6 35
#nop; lnop
andi pbit, pbyte, 1 # 0,2 37
lnop
#nop; lnop
#nop; lnop
#nop; lnop
or newvma, vma, pbit # 0,2 41
rotqbyi buf3, vma, 12 # 1,4 41
#nop; lnop
#nop
stqx newvma, tab3, off3 # 1,6 43
#nop; lnop
shli off4, buf3, 2 # 1,4 45
#lnop
ila tab4, _ovly_buf_table - 4 # 0,2 46
#lnop
#nop; lnop
#nop; lnop
#nop
lqx map, tab4, off4 # 1,6 49
#nop
cwx genwi, tab4, off4 # 1,4 50
a addr4, tab4, off4 # 0,2 51
#lnop
#nop; lnop
#nop; lnop
#nop; lnop
#nop
rotqby oldovl, map, addr4 # 1,4 55
#nop
shufb newmap, newovl, map, genwi # 0,4 56
#if MFC_TAG_ID < 16
ila newmask, 1 << MFC_TAG_ID # 0,2 57
#else
ilhu newmask, 1 << (MFC_TAG_ID - 16) # 0,2 57
#endif
#lnop
#nop; lnop
#nop; lnop
stqd newmap, 0(addr4) # 1,6 60
/* Save app's tagmask, wait for DMA complete, restore mask. */
ila tagstat, MFC_TAG_UPDATE_ALL # 0,2 61
rdch oldmask, $MFC_RdTagMask # 1,6 61
#nop
wrch $MFC_WrTagMask, newmask # 1,6 62
#nop
wrch $MFC_WrTagUpdate, tagstat # 1,6 63
#nop
rdch tagstat, $MFC_RdTagStat # 1,6 64
#nop
sync # 1,4 65
/* Any hint prior to the sync is lost. A hint here allows the branch
to complete 15 cycles after the hint. With no hint the branch will
take 18 or 19 cycles. */
ila tab5, _ovly_table - 16 # 0,2 66
hbr do_load99, target # 1,15 66
shli off5, oldovl, 4 # 0,4 67
wrch $MFC_WrTagMask, oldmask # 1,6 67
ceqi zovl, oldovl, 0 # 0,2 68
#lnop
#nop; lnop
#nop
fsm zovl, zovl # 1,4 70
#nop
lqx oldvma, tab5, off5 # 1,6 71
#nop
lqd save3, -48($sp) # 1,6 72
#nop; lnop
andc pbit, pbit, zovl # 0,2 74
lqd save2, -32($sp) # 1,6 74
#ifdef OVLY_IRQ_SAVE
ila irqtmp2, do_load90 # 0,2 75
#lnop
andi irq_stat, irq_stat, 1 # 0,2 76
#lnop
#else
#nop; lnop
#nop; lnop
#endif
andc oldvma, oldvma, pbit # 0,2 77
lqd save1, -16($sp) # 1,6 77
nop # 0,0 78
#lnop
#nop
stqx oldvma, tab5, off5 # 1,6 79
#nop
#ifdef OVLY_IRQ_SAVE
binze irq_stat, irqtmp2 # 1,4 80
do_load90:
#nop
lqd save4, -64($sp) # 1,6 84
#else
#nop; lnop
#endif
.global _ovly_debug_event
.type _ovly_debug_event, @function
_ovly_debug_event:
nop
/* Branch to target address. */
do_load99:
bi target # 1,4 81/85
.size __ovly_load, . - __ovly_load
|
tactcomplabs/xbgas-binutils-gdb | 6,170 | ld/testsuite/ld-i386/tlspic1.s | .section ".tdata", "awT", @progbits
.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
sg1: .long 17
sg2: .long 18
sg3: .long 19
sg4: .long 20
sg5: .long 21
sg6: .long 22
sg7: .long 23
sg8: .long 24
sl1: .long 65
sl2: .long 66
sl3: .long 67
sl4: .long 68
sl5: .long 69
sl6: .long 70
sl7: .long 71
sl8: .long 72
sh1: .long 257
sh2: .long 258
sh3: .long 259
sh4: .long 260
sh5: .long 261
sh6: .long 262
sh7: .long 263
sh8: .long 264
.text
.globl fn1
.type fn1,@function
fn1:
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %eax
call 1f
1: popl %ebx
addl $_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
nop;nop;nop;nop
/* GD */
leal sg1@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE because variable is referenced through @gottpoff too */
leal sg2@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE because variable is referenced through @gotntpoff too */
leal sg3@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE because variable is referenced through @gottpoff and
@gotntpoff too */
leal sg4@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD against local variable */
leal sl1@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE against local variable referenced through @gottpoff too */
leal sl2@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE against local variable referenced through @gotntpoff
too */
leal sl3@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE against local variable referenced through @gottpoff and
@gotntpoff too */
leal sl4@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD against hidden and local variable */
leal sh1@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE against hidden and local variable referenced through
@gottpoff too */
leal sh2@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE against hidden and local variable referenced through
@gotntpoff too */
leal sh3@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE against hidden and local variable referenced through
@gottpoff and @gotntpoff too */
leal sh4@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD against hidden but not local variable */
leal sH1@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE against hidden but not local variable referenced through
@gottpoff too */
leal sH2@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE against hidden but not local variable referenced through
@gotntpoff too */
leal sH3@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE against hidden but not local variable referenced through
@gottpoff and @gotntpoff too */
leal sH4@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* LD */
leal sl1@tlsldm(%ebx), %eax
call ___tls_get_addr@PLT
nop;nop
leal sl1@dtpoff(%eax), %edx
nop;nop
leal 2+sl2@dtpoff(%eax), %ecx
nop;nop;nop;nop
/* LD against hidden and local variables */
leal sh1@tlsldm(%ebx), %eax
call ___tls_get_addr@PLT
nop;nop
leal sh1@dtpoff(%eax), %edx
nop;nop
leal sh2@dtpoff+3(%eax), %ecx
nop;nop;nop;nop
/* LD against hidden but not local variables */
leal sH1@tlsldm(%ebx), %eax
call ___tls_get_addr@PLT
nop;nop
leal sH1@dtpoff(%eax), %edx
nop;nop
leal sH2@dtpoff+1(%eax), %ecx
nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %ecx
nop;nop
subl sg2@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %eax
nop;nop
subl sg4@gottpoff(%ebx), %eax
nop;nop;nop;nop
/* @gotntpoff IE against global var */
movl %gs:0, %ecx
nop;nop
addl sg3@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against global var */
movl %gs:0, %eax
nop;nop
addl sg4@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* @gottpoff IE against local var */
movl %gs:0, %ecx
nop;nop
subl sl2@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against local var */
movl %gs:0, %eax
nop;nop
subl sl4@gottpoff(%ebx), %eax
nop;nop;nop;nop
/* @gotntpoff IE against local var */
movl %gs:0, %ecx
nop;nop
addl sl3@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against local var */
movl %gs:0, %eax
nop;nop
addl sl4@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* @gottpoff IE against hidden and local var */
movl %gs:0, %ecx
nop;nop
subl sh2@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against hidden and local var */
movl %gs:0, %eax
nop;nop
subl sh4@gottpoff(%ebx), %eax
nop;nop;nop;nop
/* @gotntpoff IE against hidden and local var */
movl %gs:0, %ecx
nop;nop
addl sh3@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against hidden and local var */
movl %gs:0, %eax
nop;nop
addl sh4@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* @gottpoff IE against hidden but not local var */
movl %gs:0, %ecx
nop;nop
subl sH2@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against hidden but not local var */
movl %gs:0, %eax
nop;nop
subl sH4@gottpoff(%ebx), %eax
nop;nop;nop;nop
/* @gotntpoff IE against hidden but not local var */
movl %gs:0, %ecx
nop;nop
addl sH3@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against hidden but not local var */
movl %gs:0, %eax
nop;nop
addl sH4@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* Direct access through %gs */
/* @gotntpoff IE against global var */
movl sg5@gotntpoff(%ebx), %ecx
nop;nop
movl %gs:(%ecx), %edx
nop;nop;nop;nop
/* @gotntpoff IE against local var */
movl sl5@gotntpoff(%ebx), %eax
nop;nop
movl %gs:(%eax), %edx
nop;nop;nop;nop
/* @gotntpoff IE against hidden and local var */
movl sh5@gotntpoff(%ebx), %edx
nop;nop
movl %gs:(%edx), %edx
nop;nop;nop;nop
/* @gotntpoff IE against hidden but not local var */
movl sH5@gotntpoff(%ebx), %ecx
nop;nop
movl %gs:(%ecx), %edx
nop;nop;nop;nop
movl -4(%ebp), %ebx
leave
ret
|
tactcomplabs/xbgas-binutils-gdb | 1,933 | ld/testsuite/ld-i386/pr20253-1d.S | .text
.type implementation1, @function
implementation1:
movl $1, %eax
ret
.size implementation1, .-implementation1
.type implementation2, @function
implementation2:
movl $2, %eax
ret
.size implementation2, .-implementation2
.type resolver2, @function
resolver2:
call __x86.get_pc_thunk.ax
addl $_GLOBAL_OFFSET_TABLE_, %eax
leal implementation2@GOTOFF(%eax), %eax
ret
.size resolver2, .-resolver2
.type func2, @gnu_indirect_function
.set func2,resolver2
.type resolver1, @function
resolver1:
call __x86.get_pc_thunk.ax
addl $_GLOBAL_OFFSET_TABLE_, %eax
leal implementation1@GOTOFF(%eax), %eax
ret
.size resolver1, .-resolver1
.globl func1
.type func1, @gnu_indirect_function
.set func1,resolver1
.globl get_func2
.type get_func2, @function
get_func2:
call __x86.get_pc_thunk.ax
addl $_GLOBAL_OFFSET_TABLE_, %eax
movl func2@GOT(%eax), %eax
ret
.size get_func2, .-get_func2
.globl call_func2
.type call_func2, @function
call_func2:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
call *get_func2@GOT(%ebx)
cmpl func2@GOT(%ebx), %eax
jne .L10
addl $8, %esp
movl %ebx, %eax
popl %ebx
jmp *func2@GOT(%eax)
.L10:
call *abort@GOT(%ebx)
.size call_func2, .-call_func2
.globl func2_p
#ifdef CHECK_PLT
.section .rodata,"a",@progbits
#else
.section .data.rel,"aw",@progbits
#endif
.align 4
.type func2_p, @object
.size func2_p, 4
func2_p:
.long func2
.section .text.__x86.get_pc_thunk.ax,"axG",@progbits,__x86.get_pc_thunk.ax,comdat
.globl __x86.get_pc_thunk.ax
.hidden __x86.get_pc_thunk.ax
.type __x86.get_pc_thunk.ax, @function
__x86.get_pc_thunk.ax:
movl (%esp), %eax
ret
.section .text.__x86.get_pc_thunk.bx,"axG",@progbits,__x86.get_pc_thunk.bx,comdat
.globl __x86.get_pc_thunk.bx
.hidden __x86.get_pc_thunk.bx
.type __x86.get_pc_thunk.bx, @function
__x86.get_pc_thunk.bx:
movl (%esp), %ebx
ret
.section .note.GNU-stack,"",@progbits
|
tactcomplabs/xbgas-binutils-gdb | 1,034 | ld/testsuite/ld-i386/tlspie1.s | .text
.globl ___tls_get_addr
.type ___tls_get_addr, @function
___tls_get_addr:
ret
.size ___tls_get_addr, .-___tls_get_addr
.globl _start
.type _start, @function
_start:
pushl %ebp
movl %esp, %ebp
pushl %esi
pushl %ebx
call .L3
.L3:
popl %ebx
addl $_GLOBAL_OFFSET_TABLE_+[.-.L3], %ebx
movl %gs:foo2@NTPOFF, %esi
addl %gs:foo1@NTPOFF, %esi
movl foo3@GOTNTPOFF(%ebx), %eax
addl %gs:(%eax), %esi
leal foo4@TLSGD(,%ebx,1), %eax
call ___tls_get_addr@PLT
addl (%eax), %esi
leal foo5@TLSGD(,%ebx,1), %eax
call ___tls_get_addr@PLT
addl (%eax), %esi
movl %esi, %eax
popl %ebx
popl %esi
leave
ret
.size _start, .-_start
.globl foo1
.section .tbss,"awT",@nobits
.align 4
.type foo1, @object
.size foo1, 4
foo1:
.zero 4
.globl foo2
.align 4
.type foo2, @object
.size foo2, 4
foo2:
.zero 4
.globl foo3
.align 4
.type foo3, @object
.size foo3, 4
foo3:
.zero 4
.globl foo4
.align 4
.type foo4, @object
.size foo4, 4
foo4:
.zero 4
.globl foo5
.align 4
.type foo5, @object
.size foo5, 4
foo5:
.zero 4
|
tactcomplabs/xbgas-binutils-gdb | 3,276 | ld/testsuite/ld-i386/tlsbin.s | .section ".tbss", "awT", @nobits
.globl bg1, bg2, bg3, bg4, bg5, bg6, bg7, bg8
bg1: .space 4
bg2: .space 4
bg3: .space 4
bg4: .space 4
bg5: .space 4
bg6: .space 4
bg7: .space 4
bg8: .space 4
bl1: .space 4
bl2: .space 4
bl3: .space 4
bl4: .space 4
bl5: .space 4
bl6: .space 4
bl7: .space 4
bl8: .space 4
.text
.globl _start
.type _start,@function
_start:
pushl %ebp
movl %esp, %ebp
/* Set up .GOT pointer for non-pic @gottpoff sequences */
call 1f
1: popl %ecx
addl $_GLOBAL_OFFSET_TABLE_+[.-1b], %ecx
nop;nop;nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %edx
nop;nop
subl sG6@gottpoff(%ecx), %edx
nop;nop;nop;nop
/* @indntpoff IE against global var */
movl %gs:0, %eax
nop;nop
addl sG7@indntpoff, %eax
nop;nop;nop;nop
/* @indntpoff direct %gs access IE against global var */
movl sG8@indntpoff, %edx
nop;nop
movl %gs:(%edx), %eax
nop;nop;nop;nop
/* @gottpoff IE -> LE against global var defined in exec */
movl %gs:0, %edx
nop;nop
subl bg6@gottpoff(%ecx), %edx
nop;nop;nop;nop
/* @indntpoff IE -> LE against global var defined in exec */
movl %gs:0, %eax
nop;nop
addl bg7@indntpoff, %eax
nop;nop;nop;nop
/* @indntpoff direct %gs access IE -> LE against global var defined
in exec */
movl bg8@indntpoff, %edx
nop;nop
movl %gs:(%edx), %eax
nop;nop;nop;nop
/* @gottpoff IE -> LE against local var */
movl %gs:0, %edx
nop;nop
subl bl6@gottpoff(%ecx), %edx
nop;nop;nop;nop
/* @indntpoff IE -> LE against local var */
movl %gs:0, %eax
nop;nop
addl bl7@indntpoff, %eax
nop;nop;nop;nop
/* @indntpoff direct %gs access IE -> LE against local var */
movl bl8@indntpoff, %edx
nop;nop
movl %gs:(%edx), %eax
nop;nop;nop;nop
/* @gottpoff IE -> LE against hidden but not local var */
movl %gs:0, %edx
nop;nop
subl sh6@gottpoff(%ecx), %edx
nop;nop;nop;nop
/* @indntpoff IE -> LE against hidden but not local var */
movl %gs:0, %eax
nop;nop
addl sh7@indntpoff, %eax
nop;nop;nop;nop
/* @indntpoff direct %gs access IE -> LE against hidden but not
local var */
movl sh8@indntpoff, %edx
nop;nop
movl %gs:(%edx), %eax
nop;nop;nop;nop
/* LE @tpoff, global var defined in exec */
movl $sg1@tpoff, %edx
nop;nop
movl %gs:0, %eax
nop;nop
subl %edx, %eax
nop;nop;nop;nop
/* LE @tpoff, local var */
movl $-1+bl1@tpoff, %eax
nop;nop
movl %gs:0, %edx
nop;nop
subl %eax, %edx
nop;nop;nop;nop
/* LE @tpoff, hidden var defined in exec */
movl $sh1@tpoff-3, %eax
nop;nop
movl %gs:0, %edx
nop;nop
subl %eax, %edx
nop;nop;nop;nop
/* LE @ntpoff, global var defined in exec */
movl %gs:0, %eax
nop;nop
leal sg2@ntpoff(%eax), %edx
nop;nop;nop;nop
/* LE @ntpoff, local var, non-canonical sequence */
movl $2+bl2@ntpoff, %eax
nop;nop
movl %gs:0, %edx
nop;nop
addl %eax, %edx
nop;nop;nop;nop
/* LE @ntpoff, hidden var defined in exec, non-canonical sequence */
movl %gs:0, %edx
nop;nop
addl $sh2@ntpoff+1, %edx
nop;nop;nop;nop
/* Direct %gs access */
/* LE @ntpoff, global var defined in exec */
movl %gs:sg3@ntpoff, %eax
nop;nop;nop;nop
/* LE @ntpoff, local var */
movl %gs:bl3@ntpoff+3, %edx
nop;nop;nop;nop
/* LE @ntpoff, hidden var defined in exec */
movl %gs:1+sh3@ntpoff, %edx
nop;nop;nop;nop
movl -4(%ebp), %ebx
leave
ret
|
tactcomplabs/xbgas-binutils-gdb | 3,755 | ld/testsuite/ld-i386/tlsbindesc.s | /* Force .got aligned to 4K, so it very likely gets at 0x804a100
(0x60 bytes .tdata and 0xa0 bytes .dynamic) */
.section ".tdata", "awT", @progbits
.balign 4096
.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
sg1: .long 17
sg2: .long 18
sg3: .long 19
sg4: .long 20
sg5: .long 21
sg6: .long 22
sg7: .long 23
sg8: .long 24
sl1: .long 65
sl2: .long 66
sl3: .long 67
sl4: .long 68
sl5: .long 69
sl6: .long 70
sl7: .long 71
sl8: .long 72
sh1: .long 257
sh2: .long 258
sh3: .long 259
sh4: .long 260
sh5: .long 261
sh6: .long 262
sh7: .long 263
sh8: .long 264
/* Force .text aligned to 4K, so it very likely gets at 0x8049000. */
.text
.balign 4096
.globl fn2
.type fn2,@function
fn2:
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %eax
call 1f
1: popl %ebx
addl $_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
nop;nop;nop;nop
/* GD -> IE because variable is not defined in executable */
leal sG1@tlsdesc(%ebx), %eax
call *sG1@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE because variable is not defined in executable where
the variable is referenced through @gottpoff too */
leal sG2@tlsdesc(%ebx), %eax
call *sG2@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE because variable is not defined in executable where
the variable is referenced through @gotntpoff too */
leal sG3@tlsdesc(%ebx), %eax
call *sG3@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE because variable is not defined in executable where
the variable is referenced through @gottpoff and @gotntpoff too */
leal sG4@tlsdesc(%ebx), %eax
call *sG4@tlscall(%eax)
nop;nop;nop;nop
/* GD -> LE with global variable defined in executable */
leal sg1@tlsdesc(%ebx), %eax
call *sg1@tlscall(%eax)
nop;nop;nop;nop
/* GD -> LE with local variable defined in executable */
leal sl1@tlsdesc(%ebx), %eax
call *sl1@tlscall(%eax)
nop;nop;nop;nop
/* GD -> LE with hidden variable defined in executable */
leal sh1@tlsdesc(%ebx), %eax
call *sh1@tlscall(%eax)
nop;nop;nop;nop
/* LD -> LE */
leal _TLS_MODULE_BASE_@tlsdesc(%ebx), %eax
call *_TLS_MODULE_BASE_@tlscall(%eax)
nop;nop
leal sl1@dtpoff(%eax), %edx
nop;nop
leal sl2@dtpoff(%eax), %ecx
nop;nop;nop;nop
/* LD -> LE against hidden variables */
leal _TLS_MODULE_BASE_@tlsdesc(%ebx), %eax
call *_TLS_MODULE_BASE_@tlscall(%eax)
nop;nop
leal sh1@dtpoff(%eax), %edx
nop;nop
leal sh2@dtpoff(%eax), %ecx
nop;nop;nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %ecx
nop;nop
subl sG2@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %eax
nop;nop
subl sG4@gottpoff(%ebx), %eax
nop;nop;nop;nop
/* @gotntpoff IE against global var */
movl %gs:0, %ecx
nop;nop
addl sG3@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against global var */
movl %gs:0, %eax
nop;nop
addl sG4@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* @gottpoff IE -> LE against global var defined in exec */
movl %gs:0, %ecx
nop;nop
subl sg1@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE -> LE against local var */
movl %gs:0, %ecx
nop;nop
addl sl1@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* @gottpoff IE -> LE against hidden var */
movl %gs:0, %ecx
nop;nop
subl sh1@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* Direct access through %gs */
/* @gotntpoff IE against global var */
movl sG5@gotntpoff(%ebx), %ecx
nop;nop
movl %gs:(%ecx), %edx
nop;nop;nop;nop
/* @gotntpoff IE->LE against local var */
movl sl5@gotntpoff(%ebx), %eax
nop;nop
movl %gs:(%eax), %edx
nop;nop;nop;nop
/* @gotntpoff IE->LE against hidden var */
movl sh5@gotntpoff(%ebx), %edx
nop;nop
movl %gs:(%edx), %edx
nop;nop;nop;nop
movl -4(%ebp), %ebx
leave
ret
|
tactcomplabs/xbgas-binutils-gdb | 3,888 | ld/testsuite/ld-i386/tlsbinpic2.s | /* Force .got aligned to 4K, so it very likely gets at 0x804a100
(0x60 bytes .tdata and 0xa0 bytes .dynamic) */
.section ".tdata", "awT", @progbits
.balign 4096
.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
sg1: .long 17
sg2: .long 18
sg3: .long 19
sg4: .long 20
sg5: .long 21
sg6: .long 22
sg7: .long 23
sg8: .long 24
sl1: .long 65
sl2: .long 66
sl3: .long 67
sl4: .long 68
sl5: .long 69
sl6: .long 70
sl7: .long 71
sl8: .long 72
sh1: .long 257
sh2: .long 258
sh3: .long 259
sh4: .long 260
sh5: .long 261
sh6: .long 262
sh7: .long 263
sh8: .long 264
/* Force .text aligned to 4K, so it very likely gets at 0x8049000. */
.text
.balign 4096
.globl fn2
.type fn2,@function
fn2:
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %eax
call 1f
1: popl %ebx
addl $_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
nop;nop;nop;nop
/* GD -> IE because variable is not defined in executable */
leal sG1@tlsgd(%ebx), %eax
call *___tls_get_addr@GOT(%ebx)
nop;nop;nop;nop
/* GD -> IE because variable is not defined in executable where
the variable is referenced through @gottpoff too */
leal sG2@tlsgd(%ecx), %eax
call *___tls_get_addr@GOT(%ecx)
nop;nop;nop;nop
/* GD -> IE because variable is not defined in executable where
the variable is referenced through @gotntpoff too */
leal sG3@tlsgd(%edx), %eax
call *___tls_get_addr@GOT(%edx)
nop;nop;nop;nop
/* GD -> IE because variable is not defined in executable where
the variable is referenced through @gottpoff and @gotntpoff too */
leal sG4@tlsgd(%edi), %eax
call *___tls_get_addr@GOT(%edi)
nop;nop;nop;nop
/* GD -> LE with global variable defined in executable */
leal sg1@tlsgd(%esi), %eax
call *___tls_get_addr@GOT(%esi)
nop;nop;nop;nop
/* GD -> LE with local variable defined in executable */
leal sl1@tlsgd(%ebp), %eax
call *___tls_get_addr@GOT(%ebp)
nop;nop;nop;nop
/* GD -> LE with hidden variable defined in executable */
leal sh1@tlsgd(%ebx), %eax
call *___tls_get_addr@GOT(%ebx)
nop;nop;nop;nop
/* LD -> LE */
leal sl1@tlsldm(%edi), %eax
call *___tls_get_addr@GOT(%edi)
nop
leal sl1@dtpoff(%eax), %edx
nop;nop
leal sl2@dtpoff(%eax), %ecx
nop;nop;nop;nop
/* LD -> LE against hidden variables */
leal sh1@tlsldm(%esi), %eax
call *___tls_get_addr@GOT(%esi)
nop
leal sh1@dtpoff(%eax), %edx
nop;nop
leal sh2@dtpoff(%eax), %ecx
nop;nop;nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %ecx
nop;nop
subl sG2@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %eax
nop;nop
subl sG4@gottpoff(%ebx), %eax
nop;nop;nop;nop
/* @gotntpoff IE against global var */
movl %gs:0, %ecx
nop;nop
addl sG3@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against global var */
movl %gs:0, %eax
nop;nop
addl sG4@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* @gottpoff IE -> LE against global var defined in exec */
movl %gs:0, %ecx
nop;nop
subl sg1@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE -> LE against local var */
movl %gs:0, %ecx
nop;nop
addl sl1@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* @gottpoff IE -> LE against hidden var */
movl %gs:0, %ecx
nop;nop
subl sh1@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* Direct access through %gs */
/* @gotntpoff IE against global var */
movl sG5@gotntpoff(%ebx), %ecx
nop;nop
movl %gs:(%ecx), %edx
nop;nop;nop;nop
/* @gotntpoff IE->LE against local var */
movl sl5@gotntpoff(%ebx), %eax
nop;nop
movl %gs:(%eax), %edx
nop;nop;nop;nop
/* @gotntpoff IE->LE against hidden var */
movl sh5@gotntpoff(%ebx), %edx
nop;nop
movl %gs:(%edx), %edx
nop;nop;nop;nop
/* GD -> IE because variable is not defined in executable */
leal sG1@tlsgd(%edi), %eax
call *___tls_get_addr@GOT(%edi)
nop;nop;nop;nop
movl -4(%ebp), %ebx
leave
ret
|
tactcomplabs/xbgas-binutils-gdb | 6,038 | ld/testsuite/ld-i386/tlsdesc.s | .section ".tdata", "awT", @progbits
.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
sg1: .long 17
sg2: .long 18
sg3: .long 19
sg4: .long 20
sg5: .long 21
sg6: .long 22
sg7: .long 23
sg8: .long 24
sl1: .long 65
sl2: .long 66
sl3: .long 67
sl4: .long 68
sl5: .long 69
sl6: .long 70
sl7: .long 71
sl8: .long 72
sh1: .long 257
sh2: .long 258
sh3: .long 259
sh4: .long 260
sh5: .long 261
sh6: .long 262
sh7: .long 263
sh8: .long 264
.text
.globl fn1
.type fn1,@function
fn1:
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %eax
call 1f
1: popl %ebx
addl $_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
nop;nop;nop;nop
/* GD */
leal sg1@tlsdesc(%ebx), %eax
call *sg1@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE because variable is referenced through @gottpoff too */
leal sg2@tlsdesc(%ebx), %eax
call *sg2@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE because variable is referenced through @gotntpoff too */
leal sg3@tlsdesc(%ebx), %eax
call *sg3@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE because variable is referenced through @gottpoff and
@gotntpoff too */
leal sg4@tlsdesc(%ebx), %eax
call *sg4@tlscall(%eax)
nop;nop;nop;nop
/* GD against local variable */
leal sl1@tlsdesc(%ebx), %eax
call *sl1@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE against local variable referenced through @gottpoff too */
leal sl2@tlsdesc(%ebx), %eax
call *sl2@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE against local variable referenced through @gotntpoff
too */
leal sl3@tlsdesc(%ebx), %eax
call *sl3@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE against local variable referenced through @gottpoff and
@gotntpoff too */
leal sl4@tlsdesc(%ebx), %eax
call *sl4@tlscall(%eax)
nop;nop;nop;nop
/* GD against hidden and local variable */
leal sh1@tlsdesc(%ebx), %eax
call *sh1@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE against hidden and local variable referenced through
@gottpoff too */
leal sh2@tlsdesc(%ebx), %eax
call *sh2@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE against hidden and local variable referenced through
@gotntpoff too */
leal sh3@tlsdesc(%ebx), %eax
call *sh3@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE against hidden and local variable referenced through
@gottpoff and @gotntpoff too */
leal sh4@tlsdesc(%ebx), %eax
call *sh4@tlscall(%eax)
nop;nop;nop;nop
/* GD against hidden but not local variable */
leal sH1@tlsdesc(%ebx), %eax
call *sH1@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE against hidden but not local variable referenced through
@gottpoff too */
leal sH2@tlsdesc(%ebx), %eax
call *sH2@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE against hidden but not local variable referenced through
@gotntpoff too */
leal sH3@tlsdesc(%ebx), %eax
call *sH3@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE against hidden but not local variable referenced through
@gottpoff and @gotntpoff too */
leal sH4@tlsdesc(%ebx), %eax
call *sH4@tlscall(%eax)
nop;nop;nop;nop
/* LD */
leal _TLS_MODULE_BASE_@tlsdesc(%ebx), %eax
call *_TLS_MODULE_BASE_@tlscall(%eax)
nop;nop
leal sl1@dtpoff(%eax), %edx
nop;nop
leal 2+sl2@dtpoff(%eax), %ecx
nop;nop;nop;nop
/* LD against hidden and local variables */
leal sh1@dtpoff(%eax), %edx
nop;nop
leal sh2@dtpoff+3(%eax), %ecx
nop;nop;nop;nop
/* LD against hidden but not local variables */
leal sH1@dtpoff(%eax), %edx
nop;nop
leal sH2@dtpoff+1(%eax), %ecx
nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %ecx
nop;nop
subl sg2@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %eax
nop;nop
subl sg4@gottpoff(%ebx), %eax
nop;nop;nop;nop
/* @gotntpoff IE against global var */
movl %gs:0, %ecx
nop;nop
addl sg3@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against global var */
movl %gs:0, %eax
nop;nop
addl sg4@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* @gottpoff IE against local var */
movl %gs:0, %ecx
nop;nop
subl sl2@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against local var */
movl %gs:0, %eax
nop;nop
subl sl4@gottpoff(%ebx), %eax
nop;nop;nop;nop
/* @gotntpoff IE against local var */
movl %gs:0, %ecx
nop;nop
addl sl3@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against local var */
movl %gs:0, %eax
nop;nop
addl sl4@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* @gottpoff IE against hidden and local var */
movl %gs:0, %ecx
nop;nop
subl sh2@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against hidden and local var */
movl %gs:0, %eax
nop;nop
subl sh4@gottpoff(%ebx), %eax
nop;nop;nop;nop
/* @gotntpoff IE against hidden and local var */
movl %gs:0, %ecx
nop;nop
addl sh3@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against hidden and local var */
movl %gs:0, %eax
nop;nop
addl sh4@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* @gottpoff IE against hidden but not local var */
movl %gs:0, %ecx
nop;nop
subl sH2@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against hidden but not local var */
movl %gs:0, %eax
nop;nop
subl sH4@gottpoff(%ebx), %eax
nop;nop;nop;nop
/* @gotntpoff IE against hidden but not local var */
movl %gs:0, %ecx
nop;nop
addl sH3@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against hidden but not local var */
movl %gs:0, %eax
nop;nop
addl sH4@gotntpoff(%ebx), %eax
nop;nop;nop;nop
/* Direct access through %gs */
/* @gotntpoff IE against global var */
movl sg5@gotntpoff(%ebx), %ecx
nop;nop
movl %gs:(%ecx), %edx
nop;nop;nop;nop
/* @gotntpoff IE against local var */
movl sl5@gotntpoff(%ebx), %eax
nop;nop
movl %gs:(%eax), %edx
nop;nop;nop;nop
/* @gotntpoff IE against hidden and local var */
movl sh5@gotntpoff(%ebx), %edx
nop;nop
movl %gs:(%edx), %edx
nop;nop;nop;nop
/* @gotntpoff IE against hidden but not local var */
movl sH5@gotntpoff(%ebx), %ecx
nop;nop
movl %gs:(%ecx), %edx
nop;nop;nop;nop
movl -4(%ebp), %ebx
leave
ret
|
tactcomplabs/xbgas-binutils-gdb | 1,792 | ld/testsuite/ld-i386/tlsgdesc.s | .text
.globl fc1
.type fc1,@function
fc1:
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %eax
call 1f
1: popl %ebx
addl $_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
nop;nop;nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %ecx
nop;nop
subl sG3@gottpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gotntpoff IE against global var */
movl %gs:0, %ecx
nop;nop
addl sG4@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* GD */
leal sG1@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD */
leal sG1@tlsdesc(%ebx), %eax
call *sG1@tlscall(%eax)
nop;nop;nop;nop
/* GD */
leal sG2@tlsdesc(%ebx), %eax
call *sG2@tlscall(%eax)
nop;nop;nop;nop
/* GD */
leal sG2@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE tpoff */
leal sG3@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE tpoff */
leal sG3@tlsdesc(%ebx), %eax
call *sG3@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE ntpoff */
leal sG4@tlsdesc(%ebx), %eax
call *sG4@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE ntpoff */
leal sG4@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE ntpoff */
leal sG5@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* GD -> IE ntpoff */
leal sG5@tlsdesc(%ebx), %eax
call *sG5@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE tpoff */
leal sG6@tlsdesc(%ebx), %eax
call *sG6@tlscall(%eax)
nop;nop;nop;nop
/* GD -> IE tpoff */
leal sG6@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@plt
nop;nop;nop;nop
/* @gotntpoff IE against global var */
movl %gs:0, %ecx
nop;nop
addl sG5@gotntpoff(%ebx), %ecx
nop;nop;nop;nop
/* @gottpoff IE against global var */
movl %gs:0, %ecx
nop;nop
subl sG6@gottpoff(%ebx), %ecx
nop;nop;nop;nop
movl -4(%ebp), %ebx
leave
ret
|
tactcomplabs/xbgas-binutils-gdb | 2,792 | ld/testsuite/ld-i386/compressed1.s | .file "compressed1.c"
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.section .debug_line,"",@progbits
.Ldebug_line0:
.text
.Ltext0:
.cfi_sections .debug_frame
.p2align 4,,15
.globl foo
.type foo, @function
foo:
.LFB0:
.file 1 "compressed1.c"
.loc 1 12 0
.cfi_startproc
pushl %ebp
.cfi_def_cfa_offset 8
movl %esp, %ebp
.cfi_offset 5, -8
.cfi_def_cfa_register 5
subl $8, %esp
.loc 1 14 0
leave
.cfi_restore 5
.cfi_def_cfa 4, 4
.loc 1 13 0
jmp bar
.cfi_endproc
.LFE0:
.size foo, .-foo
.Letext0:
.section .debug_info
.long 0x5e
.value 0x3
.long .Ldebug_abbrev0
.byte 0x4
.uleb128 0x1
.long .LASF5
.byte 0x1
.long .LASF6
.long .LASF7
.long .Ltext0
.long .Letext0
.long .Ldebug_line0
.uleb128 0x2
.byte 0x1
.byte 0x6
.long .LASF0
.uleb128 0x2
.byte 0x2
.byte 0x5
.long .LASF1
.uleb128 0x3
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x2
.byte 0x4
.byte 0x5
.long .LASF2
.uleb128 0x2
.byte 0x1
.byte 0x8
.long .LASF3
.uleb128 0x2
.byte 0x2
.byte 0x7
.long .LASF4
.uleb128 0x4
.byte 0x1
.string "foo"
.byte 0x1
.byte 0xb
.long .LFB0
.long .LFE0
.byte 0x1
.byte 0x9c
.byte 0x0
.section .debug_abbrev
.uleb128 0x1
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0xe
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0xe
.uleb128 0x1b
.uleb128 0xe
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x10
.uleb128 0x6
.byte 0x0
.byte 0x0
.uleb128 0x2
.uleb128 0x24
.byte 0x0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0xe
.byte 0x0
.byte 0x0
.uleb128 0x3
.uleb128 0x24
.byte 0x0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0x0
.byte 0x0
.uleb128 0x4
.uleb128 0x2e
.byte 0x0
.uleb128 0x3f
.uleb128 0xc
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x40
.uleb128 0xa
.byte 0x0
.byte 0x0
.byte 0x0
.section .debug_pubnames,"",@progbits
.long 0x16
.value 0x2
.long .Ldebug_info0
.long 0x62
.long 0x4f
.string "foo"
.long 0x0
.section .debug_pubtypes,"",@progbits
.long 0xe
.value 0x2
.long .Ldebug_info0
.long 0x62
.long 0x0
.section .debug_aranges,"",@progbits
.long 0x1c
.value 0x2
.long .Ldebug_info0
.byte 0x4
.byte 0x0
.value 0x0
.value 0x0
.long .Ltext0
.long .Letext0-.Ltext0
.long 0x0
.long 0x0
.section .debug_str,"MS",@progbits,1
.LASF0:
.string "signed char"
.LASF1:
.string "short int"
.LASF6:
.string "compressed1.c"
.LASF5:
.string "GNU C 4.4.4 20100630 (Red Hat 4.4.4-10)"
.LASF7:
.string "."
.LASF3:
.string "unsigned char"
.LASF2:
.string "long int"
.LASF4:
.string "short unsigned int"
|
tactcomplabs/xbgas-binutils-gdb | 1,046 | ld/testsuite/ld-i386/pr20253-1b.S | .section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "PASS"
.text
.globl check
.type check, @function
check:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
call *get_func1@GOT(%ebx)
#ifdef CHECK_PLT
cmpl $func1, %eax
#else
cmpl func1@GOT(%ebx), %eax
#endif
jne .L3
movl func1_p@GOT(%ebx), %edx
cmpl %eax, (%edx)
jne .L3
call *func1@GOT(%ebx)
cmpl $1, %eax
jne .L3
call *call_func1@GOT(%ebx)
cmpl $1, %eax
jne .L3
call *get_func2@GOT(%ebx)
movl func2_p@GOT(%ebx), %edx
cmpl %eax, (%edx)
jne .L3
call *call_func2@GOT(%ebx)
cmpl $2, %eax
jne .L3
leal .LC0@GOTOFF(%ebx), %eax
subl $12, %esp
pushl %eax
call *puts@GOT(%ebx)
addl $24, %esp
popl %ebx
ret
.L3:
call *abort@GOT(%ebx)
.size check, .-check
.section .text.__x86.get_pc_thunk.bx,"axG",@progbits,__x86.get_pc_thunk.bx,comdat
.globl __x86.get_pc_thunk.bx
.hidden __x86.get_pc_thunk.bx
.type __x86.get_pc_thunk.bx, @function
__x86.get_pc_thunk.bx:
movl (%esp), %ebx
ret
.section .note.GNU-stack,"",@progbits
|
tactcomplabs/xbgas-binutils-gdb | 1,122 | ld/testsuite/ld-i386/load1.s | .data
.type bar, @object
bar:
.byte 1
.size bar, .-bar
.globl foo
.type foo, @object
foo:
.byte 1
.size foo, .-foo
.text
.globl _start
.type _start, @function
_start:
movl bar@GOT(%ecx), %eax
adcl bar@GOT(%ecx), %eax
addl bar@GOT(%ecx), %ebx
andl bar@GOT(%ecx), %ecx
cmpl bar@GOT(%ecx), %edx
orl bar@GOT(%ecx), %edi
sbbl bar@GOT(%ecx), %esi
subl bar@GOT(%ecx), %ebp
xorl bar@GOT(%ecx), %esp
testl %ecx, bar@GOT(%ecx)
movl bar@GOT, %eax
adcl bar@GOT, %eax
addl bar@GOT, %ebx
andl bar@GOT, %ecx
cmpl bar@GOT, %edx
orl bar@GOT, %edi
sbbl bar@GOT, %esi
subl bar@GOT, %ebp
xorl bar@GOT, %esp
testl %ecx, bar@GOT
movl foo@GOT(%ecx), %eax
adcl foo@GOT(%ecx), %eax
addl foo@GOT(%ecx), %ebx
andl foo@GOT(%ecx), %ecx
cmpl foo@GOT(%ecx), %edx
orl foo@GOT(%ecx), %edi
sbbl foo@GOT(%ecx), %esi
subl foo@GOT(%ecx), %ebp
xorl foo@GOT(%ecx), %esp
testl %ecx, foo@GOT(%ecx)
movl foo@GOT, %eax
adcl foo@GOT, %eax
addl foo@GOT, %ebx
andl foo@GOT, %ecx
cmpl foo@GOT, %edx
orl foo@GOT, %edi
sbbl foo@GOT, %esi
subl foo@GOT, %ebp
xorl foo@GOT, %esp
testl %ecx, foo@GOT
.size _start, .-_start
|
tactcomplabs/xbgas-binutils-gdb | 1,382 | ld/testsuite/ld-i386/tls-gd1.S | .text
.p2align 4,,15
.globl get_gd
.type get_gd, @function
get_gd:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal gd@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@PLT
addl $8, %esp
popl %ebx
ret
.size get_gd, .-get_gd
.p2align 4,,15
.globl set_gd
.type set_gd, @function
set_gd:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal gd@tlsgd(%ebx), %eax
call ___tls_get_addr@PLT
nop
movl 16(%esp), %edx
movl %edx, (%eax)
addl $8, %esp
popl %ebx
ret
.size set_gd, .-set_gd
.text
.p2align 4,,15
.globl test_gd
.type test_gd, @function
test_gd:
call __x86.get_pc_thunk.cx
addl $_GLOBAL_OFFSET_TABLE_, %ecx
subl $12, %esp
leal gd@tlsgd(%ecx), %eax
call *___tls_get_addr@GOT(%ecx)
movl 16(%esp), %ecx
cmpl %ecx, (%eax)
sete %al
addl $12, %esp
movzbl %al, %eax
ret
.size test_gd, .-test_gd
.section .text,"axG",@progbits,__x86.get_pc_thunk.bx,comdat,unique,1
.globl __x86.get_pc_thunk.bx
.hidden __x86.get_pc_thunk.bx
.type __x86.get_pc_thunk.bx, @function
__x86.get_pc_thunk.bx:
movl (%esp), %ebx
ret
.section .text,"axG",@progbits,__x86.get_pc_thunk.cx,comdat,unique,2
.globl __x86.get_pc_thunk.cx
.hidden __x86.get_pc_thunk.cx
.type __x86.get_pc_thunk.cx, @function
__x86.get_pc_thunk.cx:
movl (%esp), %ecx
ret
.section .note.GNU-stack,"",@progbits
|
tactcomplabs/xbgas-binutils-gdb | 1,043 | ld/testsuite/ld-i386/tlspie3.s | .text
.globl ___tls_get_addr
.type ___tls_get_addr, @function
___tls_get_addr:
ret
.size ___tls_get_addr, .-___tls_get_addr
.globl _start
.type _start, @function
_start:
pushl %ebp
movl %esp, %ebp
pushl %esi
pushl %ebx
call .L3
.L3:
popl %ebx
addl $_GLOBAL_OFFSET_TABLE_+[.-.L3], %ebx
movl %gs:foo2@NTPOFF, %esi
addl %gs:foo1@NTPOFF, %esi
movl foo3@GOTNTPOFF(%ebx), %eax
addl %gs:(%eax), %esi
leal foo4@TLSLDM(%edx), %eax
call *___tls_get_addr@GOT(%edx)
addl (%eax), %esi
leal foo5@TLSGD(%ebx), %eax
call *___tls_get_addr@GOT(%ebx)
addl (%eax), %esi
movl %esi, %eax
popl %ebx
popl %esi
leave
ret
.size _start, .-_start
.globl foo1
.section .tbss,"awT",@nobits
.align 4
.type foo1, @object
.size foo1, 4
foo1:
.zero 4
.globl foo2
.align 4
.type foo2, @object
.size foo2, 4
foo2:
.zero 4
.globl foo3
.align 4
.type foo3, @object
.size foo3, 4
foo3:
.zero 4
.globl foo4
.align 4
.type foo4, @object
.size foo4, 4
foo4:
.zero 4
.globl foo5
.align 4
.type foo5, @object
.size foo5, 4
foo5:
.zero 4
|
tactcomplabs/xbgas-binutils-gdb | 2,027 | ld/testsuite/ld-i386/tlsnopic1.s | .section ".data.rel.ro", "aw", @progbits
/* Align, so that .got is likely at address 0x2080. */
.balign 4096
.section ".tbss", "awT", @nobits
bl1: .space 4
bl2: .space 4
bl3: .space 4
bl4: .space 4
bl5: .space 4
.text
/* Align, so that fn3 is likely at address 0x1000. */
.balign 4096
.globl fn3
.type fn3,@function
fn3:
pushl %ebp
movl %esp, %ebp
/* @indntpoff IE against global var */
movl %gs:0, %eax
nop;nop
addl sg1@indntpoff, %eax
nop;nop;nop;nop
/* @indntpoff direct %gs access IE against global var */
movl sg2@indntpoff, %edx
nop;nop
movl %gs:(%edx), %eax
nop;nop;nop;nop
/* @indntpoff IE against hidden var */
movl %gs:0, %eax
nop;nop
addl sh1@indntpoff, %eax
nop;nop;nop;nop
/* @indntpoff direct %gs access IE against hidden var */
movl sh2@indntpoff, %edx
nop;nop
movl %gs:(%edx), %eax
nop;nop;nop;nop
/* @indntpoff IE against local var */
movl %gs:0, %eax
nop;nop
addl bl1@indntpoff, %eax
nop;nop;nop;nop
/* @indntpoff direct %gs access IE against local var */
movl bl2@indntpoff, %edx
nop;nop
movl %gs:(%edx), %eax
nop;nop;nop;nop
/* LE @tpoff, global var */
movl $-3+sg3@tpoff, %edx
nop;nop
movl %gs:0, %eax
nop;nop
subl %edx, %eax
nop;nop;nop;nop
/* LE @tpoff, local var */
movl $-1+bl3@tpoff, %eax
nop;nop
movl %gs:0, %edx
nop;nop
subl %eax, %edx
nop;nop;nop;nop
/* LE @ntpoff, global var */
movl %gs:0, %eax
nop;nop
leal 2+sg4@ntpoff(%eax), %edx
nop;nop;nop;nop
/* LE @ntpoff, hidden var, non-canonical sequence */
movl $sh3@ntpoff, %eax
nop;nop
movl %gs:0, %edx
nop;nop
addl %eax, %edx
nop;nop;nop;nop
/* LE @ntpoff, local var, non-canonical sequence */
movl %gs:0, %edx
nop;nop
addl $bl4@ntpoff+1, %edx
nop;nop;nop;nop
/* Direct %gs access */
/* LE @ntpoff, global var */
movl %gs:sg5@ntpoff, %eax
nop;nop;nop;nop
/* LE @ntpoff, local var */
movl %gs:bl5@ntpoff+3, %edx
nop;nop;nop;nop
/* LE @ntpoff, hidden var */
movl %gs:1+sh4@ntpoff, %edx
nop;nop;nop;nop
movl -4(%ebp), %ebx
leave
ret
|
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