lumees/github-code-2025-language-split · Datasets at Hugging Face

repo_id stringlengths 5 115	size int64 590 5.01M	file_path stringlengths 4 212	content stringlengths 590 5.01M
j4yc3-mw/Viren	40,476	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/chacha-armv8-win64.S	// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32) #include <ring-core/arm_arch.h> .section .rodata .align 5 Lsigma: .quad 0x3320646e61707865,0x6b20657479622d32 // endian-neutral Lone: .long 1,0,0,0 .byte 67,104,97,67,104,97,50,48,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 .align 2 .text .globl ChaCha20_ctr32 .def ChaCha20_ctr32 .type 32 .endef .align 5 ChaCha20_ctr32: AARCH64_VALID_CALL_TARGET cbz x2,Labort #if defined(OPENSSL_HWASAN) && __clang_major__ >= 10 adrp x5,:pg_hi21_nc:OPENSSL_armcap_P #else adrp x5,OPENSSL_armcap_P #endif cmp x2,#192 b.lo Lshort ldr w17,[x5,:lo12:OPENSSL_armcap_P] tst w17,#ARMV7_NEON b.ne ChaCha20_neon Lshort: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-96]! add x29,sp,#0 adrp x5,Lsigma add x5,x5,:lo12:Lsigma stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] stp x25,x26,[sp,#64] stp x27,x28,[sp,#80] sub sp,sp,#64 ldp x22,x23,[x5] // load sigma ldp x24,x25,[x3] // load key ldp x26,x27,[x3,#16] ldp x28,x30,[x4] // load counter #ifdef __AARCH64EB__ ror x24,x24,#32 ror x25,x25,#32 ror x26,x26,#32 ror x27,x27,#32 ror x28,x28,#32 ror x30,x30,#32 #endif Loop_outer: mov w5,w22 // unpack key block lsr x6,x22,#32 mov w7,w23 lsr x8,x23,#32 mov w9,w24 lsr x10,x24,#32 mov w11,w25 lsr x12,x25,#32 mov w13,w26 lsr x14,x26,#32 mov w15,w27 lsr x16,x27,#32 mov w17,w28 lsr x19,x28,#32 mov w20,w30 lsr x21,x30,#32 mov x4,#10 subs x2,x2,#64 Loop: sub x4,x4,#1 add w5,w5,w9 add w6,w6,w10 add w7,w7,w11 add w8,w8,w12 eor w17,w17,w5 eor w19,w19,w6 eor w20,w20,w7 eor w21,w21,w8 ror w17,w17,#16 ror w19,w19,#16 ror w20,w20,#16 ror w21,w21,#16 add w13,w13,w17 add w14,w14,w19 add w15,w15,w20 add w16,w16,w21 eor w9,w9,w13 eor w10,w10,w14 eor w11,w11,w15 eor w12,w12,w16 ror w9,w9,#20 ror w10,w10,#20 ror w11,w11,#20 ror w12,w12,#20 add w5,w5,w9 add w6,w6,w10 add w7,w7,w11 add w8,w8,w12 eor w17,w17,w5 eor w19,w19,w6 eor w20,w20,w7 eor w21,w21,w8 ror w17,w17,#24 ror w19,w19,#24 ror w20,w20,#24 ror w21,w21,#24 add w13,w13,w17 add w14,w14,w19 add w15,w15,w20 add w16,w16,w21 eor w9,w9,w13 eor w10,w10,w14 eor w11,w11,w15 eor w12,w12,w16 ror w9,w9,#25 ror w10,w10,#25 ror w11,w11,#25 ror w12,w12,#25 add w5,w5,w10 add w6,w6,w11 add w7,w7,w12 add w8,w8,w9 eor w21,w21,w5 eor w17,w17,w6 eor w19,w19,w7 eor w20,w20,w8 ror w21,w21,#16 ror w17,w17,#16 ror w19,w19,#16 ror w20,w20,#16 add w15,w15,w21 add w16,w16,w17 add w13,w13,w19 add w14,w14,w20 eor w10,w10,w15 eor w11,w11,w16 eor w12,w12,w13 eor w9,w9,w14 ror w10,w10,#20 ror w11,w11,#20 ror w12,w12,#20 ror w9,w9,#20 add w5,w5,w10 add w6,w6,w11 add w7,w7,w12 add w8,w8,w9 eor w21,w21,w5 eor w17,w17,w6 eor w19,w19,w7 eor w20,w20,w8 ror w21,w21,#24 ror w17,w17,#24 ror w19,w19,#24 ror w20,w20,#24 add w15,w15,w21 add w16,w16,w17 add w13,w13,w19 add w14,w14,w20 eor w10,w10,w15 eor w11,w11,w16 eor w12,w12,w13 eor w9,w9,w14 ror w10,w10,#25 ror w11,w11,#25 ror w12,w12,#25 ror w9,w9,#25 cbnz x4,Loop add w5,w5,w22 // accumulate key block add x6,x6,x22,lsr#32 add w7,w7,w23 add x8,x8,x23,lsr#32 add w9,w9,w24 add x10,x10,x24,lsr#32 add w11,w11,w25 add x12,x12,x25,lsr#32 add w13,w13,w26 add x14,x14,x26,lsr#32 add w15,w15,w27 add x16,x16,x27,lsr#32 add w17,w17,w28 add x19,x19,x28,lsr#32 add w20,w20,w30 add x21,x21,x30,lsr#32 b.lo Ltail add x5,x5,x6,lsl#32 // pack add x7,x7,x8,lsl#32 ldp x6,x8,[x1,#0] // load input add x9,x9,x10,lsl#32 add x11,x11,x12,lsl#32 ldp x10,x12,[x1,#16] add x13,x13,x14,lsl#32 add x15,x15,x16,lsl#32 ldp x14,x16,[x1,#32] add x17,x17,x19,lsl#32 add x20,x20,x21,lsl#32 ldp x19,x21,[x1,#48] add x1,x1,#64 #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif eor x5,x5,x6 eor x7,x7,x8 eor x9,x9,x10 eor x11,x11,x12 eor x13,x13,x14 eor x15,x15,x16 eor x17,x17,x19 eor x20,x20,x21 stp x5,x7,[x0,#0] // store output add x28,x28,#1 // increment counter stp x9,x11,[x0,#16] stp x13,x15,[x0,#32] stp x17,x20,[x0,#48] add x0,x0,#64 b.hi Loop_outer ldp x19,x20,[x29,#16] add sp,sp,#64 ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER Labort: ret .align 4 Ltail: add x2,x2,#64 Less_than_64: sub x0,x0,#1 add x1,x1,x2 add x0,x0,x2 add x4,sp,x2 neg x2,x2 add x5,x5,x6,lsl#32 // pack add x7,x7,x8,lsl#32 add x9,x9,x10,lsl#32 add x11,x11,x12,lsl#32 add x13,x13,x14,lsl#32 add x15,x15,x16,lsl#32 add x17,x17,x19,lsl#32 add x20,x20,x21,lsl#32 #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif stp x5,x7,[sp,#0] stp x9,x11,[sp,#16] stp x13,x15,[sp,#32] stp x17,x20,[sp,#48] Loop_tail: ldrb w10,[x1,x2] ldrb w11,[x4,x2] add x2,x2,#1 eor w10,w10,w11 strb w10,[x0,x2] cbnz x2,Loop_tail stp xzr,xzr,[sp,#0] stp xzr,xzr,[sp,#16] stp xzr,xzr,[sp,#32] stp xzr,xzr,[sp,#48] ldp x19,x20,[x29,#16] add sp,sp,#64 ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret .def ChaCha20_neon .type 32 .endef .align 5 ChaCha20_neon: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-96]! add x29,sp,#0 adrp x5,Lsigma add x5,x5,:lo12:Lsigma stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] stp x25,x26,[sp,#64] stp x27,x28,[sp,#80] cmp x2,#512 b.hs L512_or_more_neon sub sp,sp,#64 ldp x22,x23,[x5] // load sigma ld1 {v24.4s},[x5],#16 ldp x24,x25,[x3] // load key ldp x26,x27,[x3,#16] ld1 {v25.4s,v26.4s},[x3] ldp x28,x30,[x4] // load counter ld1 {v27.4s},[x4] ld1 {v31.4s},[x5] #ifdef __AARCH64EB__ rev64 v24.4s,v24.4s ror x24,x24,#32 ror x25,x25,#32 ror x26,x26,#32 ror x27,x27,#32 ror x28,x28,#32 ror x30,x30,#32 #endif add v27.4s,v27.4s,v31.4s // += 1 add v28.4s,v27.4s,v31.4s add v29.4s,v28.4s,v31.4s shl v31.4s,v31.4s,#2 // 1 -> 4 Loop_outer_neon: mov w5,w22 // unpack key block lsr x6,x22,#32 mov v0.16b,v24.16b mov w7,w23 lsr x8,x23,#32 mov v4.16b,v24.16b mov w9,w24 lsr x10,x24,#32 mov v16.16b,v24.16b mov w11,w25 mov v1.16b,v25.16b lsr x12,x25,#32 mov v5.16b,v25.16b mov w13,w26 mov v17.16b,v25.16b lsr x14,x26,#32 mov v3.16b,v27.16b mov w15,w27 mov v7.16b,v28.16b lsr x16,x27,#32 mov v19.16b,v29.16b mov w17,w28 mov v2.16b,v26.16b lsr x19,x28,#32 mov v6.16b,v26.16b mov w20,w30 mov v18.16b,v26.16b lsr x21,x30,#32 mov x4,#10 subs x2,x2,#256 Loop_neon: sub x4,x4,#1 add v0.4s,v0.4s,v1.4s add w5,w5,w9 add v4.4s,v4.4s,v5.4s add w6,w6,w10 add v16.4s,v16.4s,v17.4s add w7,w7,w11 eor v3.16b,v3.16b,v0.16b add w8,w8,w12 eor v7.16b,v7.16b,v4.16b eor w17,w17,w5 eor v19.16b,v19.16b,v16.16b eor w19,w19,w6 rev32 v3.8h,v3.8h eor w20,w20,w7 rev32 v7.8h,v7.8h eor w21,w21,w8 rev32 v19.8h,v19.8h ror w17,w17,#16 add v2.4s,v2.4s,v3.4s ror w19,w19,#16 add v6.4s,v6.4s,v7.4s ror w20,w20,#16 add v18.4s,v18.4s,v19.4s ror w21,w21,#16 eor v20.16b,v1.16b,v2.16b add w13,w13,w17 eor v21.16b,v5.16b,v6.16b add w14,w14,w19 eor v22.16b,v17.16b,v18.16b add w15,w15,w20 ushr v1.4s,v20.4s,#20 add w16,w16,w21 ushr v5.4s,v21.4s,#20 eor w9,w9,w13 ushr v17.4s,v22.4s,#20 eor w10,w10,w14 sli v1.4s,v20.4s,#12 eor w11,w11,w15 sli v5.4s,v21.4s,#12 eor w12,w12,w16 sli v17.4s,v22.4s,#12 ror w9,w9,#20 add v0.4s,v0.4s,v1.4s ror w10,w10,#20 add v4.4s,v4.4s,v5.4s ror w11,w11,#20 add v16.4s,v16.4s,v17.4s ror w12,w12,#20 eor v20.16b,v3.16b,v0.16b add w5,w5,w9 eor v21.16b,v7.16b,v4.16b add w6,w6,w10 eor v22.16b,v19.16b,v16.16b add w7,w7,w11 ushr v3.4s,v20.4s,#24 add w8,w8,w12 ushr v7.4s,v21.4s,#24 eor w17,w17,w5 ushr v19.4s,v22.4s,#24 eor w19,w19,w6 sli v3.4s,v20.4s,#8 eor w20,w20,w7 sli v7.4s,v21.4s,#8 eor w21,w21,w8 sli v19.4s,v22.4s,#8 ror w17,w17,#24 add v2.4s,v2.4s,v3.4s ror w19,w19,#24 add v6.4s,v6.4s,v7.4s ror w20,w20,#24 add v18.4s,v18.4s,v19.4s ror w21,w21,#24 eor v20.16b,v1.16b,v2.16b add w13,w13,w17 eor v21.16b,v5.16b,v6.16b add w14,w14,w19 eor v22.16b,v17.16b,v18.16b add w15,w15,w20 ushr v1.4s,v20.4s,#25 add w16,w16,w21 ushr v5.4s,v21.4s,#25 eor w9,w9,w13 ushr v17.4s,v22.4s,#25 eor w10,w10,w14 sli v1.4s,v20.4s,#7 eor w11,w11,w15 sli v5.4s,v21.4s,#7 eor w12,w12,w16 sli v17.4s,v22.4s,#7 ror w9,w9,#25 ext v2.16b,v2.16b,v2.16b,#8 ror w10,w10,#25 ext v6.16b,v6.16b,v6.16b,#8 ror w11,w11,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w12,w12,#25 ext v3.16b,v3.16b,v3.16b,#12 ext v7.16b,v7.16b,v7.16b,#12 ext v19.16b,v19.16b,v19.16b,#12 ext v1.16b,v1.16b,v1.16b,#4 ext v5.16b,v5.16b,v5.16b,#4 ext v17.16b,v17.16b,v17.16b,#4 add v0.4s,v0.4s,v1.4s add w5,w5,w10 add v4.4s,v4.4s,v5.4s add w6,w6,w11 add v16.4s,v16.4s,v17.4s add w7,w7,w12 eor v3.16b,v3.16b,v0.16b add w8,w8,w9 eor v7.16b,v7.16b,v4.16b eor w21,w21,w5 eor v19.16b,v19.16b,v16.16b eor w17,w17,w6 rev32 v3.8h,v3.8h eor w19,w19,w7 rev32 v7.8h,v7.8h eor w20,w20,w8 rev32 v19.8h,v19.8h ror w21,w21,#16 add v2.4s,v2.4s,v3.4s ror w17,w17,#16 add v6.4s,v6.4s,v7.4s ror w19,w19,#16 add v18.4s,v18.4s,v19.4s ror w20,w20,#16 eor v20.16b,v1.16b,v2.16b add w15,w15,w21 eor v21.16b,v5.16b,v6.16b add w16,w16,w17 eor v22.16b,v17.16b,v18.16b add w13,w13,w19 ushr v1.4s,v20.4s,#20 add w14,w14,w20 ushr v5.4s,v21.4s,#20 eor w10,w10,w15 ushr v17.4s,v22.4s,#20 eor w11,w11,w16 sli v1.4s,v20.4s,#12 eor w12,w12,w13 sli v5.4s,v21.4s,#12 eor w9,w9,w14 sli v17.4s,v22.4s,#12 ror w10,w10,#20 add v0.4s,v0.4s,v1.4s ror w11,w11,#20 add v4.4s,v4.4s,v5.4s ror w12,w12,#20 add v16.4s,v16.4s,v17.4s ror w9,w9,#20 eor v20.16b,v3.16b,v0.16b add w5,w5,w10 eor v21.16b,v7.16b,v4.16b add w6,w6,w11 eor v22.16b,v19.16b,v16.16b add w7,w7,w12 ushr v3.4s,v20.4s,#24 add w8,w8,w9 ushr v7.4s,v21.4s,#24 eor w21,w21,w5 ushr v19.4s,v22.4s,#24 eor w17,w17,w6 sli v3.4s,v20.4s,#8 eor w19,w19,w7 sli v7.4s,v21.4s,#8 eor w20,w20,w8 sli v19.4s,v22.4s,#8 ror w21,w21,#24 add v2.4s,v2.4s,v3.4s ror w17,w17,#24 add v6.4s,v6.4s,v7.4s ror w19,w19,#24 add v18.4s,v18.4s,v19.4s ror w20,w20,#24 eor v20.16b,v1.16b,v2.16b add w15,w15,w21 eor v21.16b,v5.16b,v6.16b add w16,w16,w17 eor v22.16b,v17.16b,v18.16b add w13,w13,w19 ushr v1.4s,v20.4s,#25 add w14,w14,w20 ushr v5.4s,v21.4s,#25 eor w10,w10,w15 ushr v17.4s,v22.4s,#25 eor w11,w11,w16 sli v1.4s,v20.4s,#7 eor w12,w12,w13 sli v5.4s,v21.4s,#7 eor w9,w9,w14 sli v17.4s,v22.4s,#7 ror w10,w10,#25 ext v2.16b,v2.16b,v2.16b,#8 ror w11,w11,#25 ext v6.16b,v6.16b,v6.16b,#8 ror w12,w12,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w9,w9,#25 ext v3.16b,v3.16b,v3.16b,#4 ext v7.16b,v7.16b,v7.16b,#4 ext v19.16b,v19.16b,v19.16b,#4 ext v1.16b,v1.16b,v1.16b,#12 ext v5.16b,v5.16b,v5.16b,#12 ext v17.16b,v17.16b,v17.16b,#12 cbnz x4,Loop_neon add w5,w5,w22 // accumulate key block add v0.4s,v0.4s,v24.4s add x6,x6,x22,lsr#32 add v4.4s,v4.4s,v24.4s add w7,w7,w23 add v16.4s,v16.4s,v24.4s add x8,x8,x23,lsr#32 add v2.4s,v2.4s,v26.4s add w9,w9,w24 add v6.4s,v6.4s,v26.4s add x10,x10,x24,lsr#32 add v18.4s,v18.4s,v26.4s add w11,w11,w25 add v3.4s,v3.4s,v27.4s add x12,x12,x25,lsr#32 add w13,w13,w26 add v7.4s,v7.4s,v28.4s add x14,x14,x26,lsr#32 add w15,w15,w27 add v19.4s,v19.4s,v29.4s add x16,x16,x27,lsr#32 add w17,w17,w28 add v1.4s,v1.4s,v25.4s add x19,x19,x28,lsr#32 add w20,w20,w30 add v5.4s,v5.4s,v25.4s add x21,x21,x30,lsr#32 add v17.4s,v17.4s,v25.4s b.lo Ltail_neon add x5,x5,x6,lsl#32 // pack add x7,x7,x8,lsl#32 ldp x6,x8,[x1,#0] // load input add x9,x9,x10,lsl#32 add x11,x11,x12,lsl#32 ldp x10,x12,[x1,#16] add x13,x13,x14,lsl#32 add x15,x15,x16,lsl#32 ldp x14,x16,[x1,#32] add x17,x17,x19,lsl#32 add x20,x20,x21,lsl#32 ldp x19,x21,[x1,#48] add x1,x1,#64 #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif ld1 {v20.16b,v21.16b,v22.16b,v23.16b},[x1],#64 eor x5,x5,x6 eor x7,x7,x8 eor x9,x9,x10 eor x11,x11,x12 eor x13,x13,x14 eor v0.16b,v0.16b,v20.16b eor x15,x15,x16 eor v1.16b,v1.16b,v21.16b eor x17,x17,x19 eor v2.16b,v2.16b,v22.16b eor x20,x20,x21 eor v3.16b,v3.16b,v23.16b ld1 {v20.16b,v21.16b,v22.16b,v23.16b},[x1],#64 stp x5,x7,[x0,#0] // store output add x28,x28,#4 // increment counter stp x9,x11,[x0,#16] add v27.4s,v27.4s,v31.4s // += 4 stp x13,x15,[x0,#32] add v28.4s,v28.4s,v31.4s stp x17,x20,[x0,#48] add v29.4s,v29.4s,v31.4s add x0,x0,#64 st1 {v0.16b,v1.16b,v2.16b,v3.16b},[x0],#64 ld1 {v0.16b,v1.16b,v2.16b,v3.16b},[x1],#64 eor v4.16b,v4.16b,v20.16b eor v5.16b,v5.16b,v21.16b eor v6.16b,v6.16b,v22.16b eor v7.16b,v7.16b,v23.16b st1 {v4.16b,v5.16b,v6.16b,v7.16b},[x0],#64 eor v16.16b,v16.16b,v0.16b eor v17.16b,v17.16b,v1.16b eor v18.16b,v18.16b,v2.16b eor v19.16b,v19.16b,v3.16b st1 {v16.16b,v17.16b,v18.16b,v19.16b},[x0],#64 b.hi Loop_outer_neon ldp x19,x20,[x29,#16] add sp,sp,#64 ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret Ltail_neon: add x2,x2,#256 cmp x2,#64 b.lo Less_than_64 add x5,x5,x6,lsl#32 // pack add x7,x7,x8,lsl#32 ldp x6,x8,[x1,#0] // load input add x9,x9,x10,lsl#32 add x11,x11,x12,lsl#32 ldp x10,x12,[x1,#16] add x13,x13,x14,lsl#32 add x15,x15,x16,lsl#32 ldp x14,x16,[x1,#32] add x17,x17,x19,lsl#32 add x20,x20,x21,lsl#32 ldp x19,x21,[x1,#48] add x1,x1,#64 #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif eor x5,x5,x6 eor x7,x7,x8 eor x9,x9,x10 eor x11,x11,x12 eor x13,x13,x14 eor x15,x15,x16 eor x17,x17,x19 eor x20,x20,x21 stp x5,x7,[x0,#0] // store output add x28,x28,#4 // increment counter stp x9,x11,[x0,#16] stp x13,x15,[x0,#32] stp x17,x20,[x0,#48] add x0,x0,#64 b.eq Ldone_neon sub x2,x2,#64 cmp x2,#64 b.lo Less_than_128 ld1 {v20.16b,v21.16b,v22.16b,v23.16b},[x1],#64 eor v0.16b,v0.16b,v20.16b eor v1.16b,v1.16b,v21.16b eor v2.16b,v2.16b,v22.16b eor v3.16b,v3.16b,v23.16b st1 {v0.16b,v1.16b,v2.16b,v3.16b},[x0],#64 b.eq Ldone_neon sub x2,x2,#64 cmp x2,#64 b.lo Less_than_192 ld1 {v20.16b,v21.16b,v22.16b,v23.16b},[x1],#64 eor v4.16b,v4.16b,v20.16b eor v5.16b,v5.16b,v21.16b eor v6.16b,v6.16b,v22.16b eor v7.16b,v7.16b,v23.16b st1 {v4.16b,v5.16b,v6.16b,v7.16b},[x0],#64 b.eq Ldone_neon sub x2,x2,#64 st1 {v16.16b,v17.16b,v18.16b,v19.16b},[sp] b Last_neon Less_than_128: st1 {v0.16b,v1.16b,v2.16b,v3.16b},[sp] b Last_neon Less_than_192: st1 {v4.16b,v5.16b,v6.16b,v7.16b},[sp] b Last_neon .align 4 Last_neon: sub x0,x0,#1 add x1,x1,x2 add x0,x0,x2 add x4,sp,x2 neg x2,x2 Loop_tail_neon: ldrb w10,[x1,x2] ldrb w11,[x4,x2] add x2,x2,#1 eor w10,w10,w11 strb w10,[x0,x2] cbnz x2,Loop_tail_neon stp xzr,xzr,[sp,#0] stp xzr,xzr,[sp,#16] stp xzr,xzr,[sp,#32] stp xzr,xzr,[sp,#48] Ldone_neon: ldp x19,x20,[x29,#16] add sp,sp,#64 ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret .def ChaCha20_512_neon .type 32 .endef .align 5 ChaCha20_512_neon: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-96]! add x29,sp,#0 adrp x5,Lsigma add x5,x5,:lo12:Lsigma stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] stp x25,x26,[sp,#64] stp x27,x28,[sp,#80] L512_or_more_neon: sub sp,sp,#128+64 ldp x22,x23,[x5] // load sigma ld1 {v24.4s},[x5],#16 ldp x24,x25,[x3] // load key ldp x26,x27,[x3,#16] ld1 {v25.4s,v26.4s},[x3] ldp x28,x30,[x4] // load counter ld1 {v27.4s},[x4] ld1 {v31.4s},[x5] #ifdef __AARCH64EB__ rev64 v24.4s,v24.4s ror x24,x24,#32 ror x25,x25,#32 ror x26,x26,#32 ror x27,x27,#32 ror x28,x28,#32 ror x30,x30,#32 #endif add v27.4s,v27.4s,v31.4s // += 1 stp q24,q25,[sp,#0] // off-load key block, invariant part add v27.4s,v27.4s,v31.4s // not typo str q26,[sp,#32] add v28.4s,v27.4s,v31.4s add v29.4s,v28.4s,v31.4s add v30.4s,v29.4s,v31.4s shl v31.4s,v31.4s,#2 // 1 -> 4 stp d8,d9,[sp,#128+0] // meet ABI requirements stp d10,d11,[sp,#128+16] stp d12,d13,[sp,#128+32] stp d14,d15,[sp,#128+48] sub x2,x2,#512 // not typo Loop_outer_512_neon: mov v0.16b,v24.16b mov v4.16b,v24.16b mov v8.16b,v24.16b mov v12.16b,v24.16b mov v16.16b,v24.16b mov v20.16b,v24.16b mov v1.16b,v25.16b mov w5,w22 // unpack key block mov v5.16b,v25.16b lsr x6,x22,#32 mov v9.16b,v25.16b mov w7,w23 mov v13.16b,v25.16b lsr x8,x23,#32 mov v17.16b,v25.16b mov w9,w24 mov v21.16b,v25.16b lsr x10,x24,#32 mov v3.16b,v27.16b mov w11,w25 mov v7.16b,v28.16b lsr x12,x25,#32 mov v11.16b,v29.16b mov w13,w26 mov v15.16b,v30.16b lsr x14,x26,#32 mov v2.16b,v26.16b mov w15,w27 mov v6.16b,v26.16b lsr x16,x27,#32 add v19.4s,v3.4s,v31.4s // +4 mov w17,w28 add v23.4s,v7.4s,v31.4s // +4 lsr x19,x28,#32 mov v10.16b,v26.16b mov w20,w30 mov v14.16b,v26.16b lsr x21,x30,#32 mov v18.16b,v26.16b stp q27,q28,[sp,#48] // off-load key block, variable part mov v22.16b,v26.16b str q29,[sp,#80] mov x4,#5 subs x2,x2,#512 Loop_upper_neon: sub x4,x4,#1 add v0.4s,v0.4s,v1.4s add w5,w5,w9 add v4.4s,v4.4s,v5.4s add w6,w6,w10 add v8.4s,v8.4s,v9.4s add w7,w7,w11 add v12.4s,v12.4s,v13.4s add w8,w8,w12 add v16.4s,v16.4s,v17.4s eor w17,w17,w5 add v20.4s,v20.4s,v21.4s eor w19,w19,w6 eor v3.16b,v3.16b,v0.16b eor w20,w20,w7 eor v7.16b,v7.16b,v4.16b eor w21,w21,w8 eor v11.16b,v11.16b,v8.16b ror w17,w17,#16 eor v15.16b,v15.16b,v12.16b ror w19,w19,#16 eor v19.16b,v19.16b,v16.16b ror w20,w20,#16 eor v23.16b,v23.16b,v20.16b ror w21,w21,#16 rev32 v3.8h,v3.8h add w13,w13,w17 rev32 v7.8h,v7.8h add w14,w14,w19 rev32 v11.8h,v11.8h add w15,w15,w20 rev32 v15.8h,v15.8h add w16,w16,w21 rev32 v19.8h,v19.8h eor w9,w9,w13 rev32 v23.8h,v23.8h eor w10,w10,w14 add v2.4s,v2.4s,v3.4s eor w11,w11,w15 add v6.4s,v6.4s,v7.4s eor w12,w12,w16 add v10.4s,v10.4s,v11.4s ror w9,w9,#20 add v14.4s,v14.4s,v15.4s ror w10,w10,#20 add v18.4s,v18.4s,v19.4s ror w11,w11,#20 add v22.4s,v22.4s,v23.4s ror w12,w12,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w9 eor v25.16b,v5.16b,v6.16b add w6,w6,w10 eor v26.16b,v9.16b,v10.16b add w7,w7,w11 eor v27.16b,v13.16b,v14.16b add w8,w8,w12 eor v28.16b,v17.16b,v18.16b eor w17,w17,w5 eor v29.16b,v21.16b,v22.16b eor w19,w19,w6 ushr v1.4s,v24.4s,#20 eor w20,w20,w7 ushr v5.4s,v25.4s,#20 eor w21,w21,w8 ushr v9.4s,v26.4s,#20 ror w17,w17,#24 ushr v13.4s,v27.4s,#20 ror w19,w19,#24 ushr v17.4s,v28.4s,#20 ror w20,w20,#24 ushr v21.4s,v29.4s,#20 ror w21,w21,#24 sli v1.4s,v24.4s,#12 add w13,w13,w17 sli v5.4s,v25.4s,#12 add w14,w14,w19 sli v9.4s,v26.4s,#12 add w15,w15,w20 sli v13.4s,v27.4s,#12 add w16,w16,w21 sli v17.4s,v28.4s,#12 eor w9,w9,w13 sli v21.4s,v29.4s,#12 eor w10,w10,w14 add v0.4s,v0.4s,v1.4s eor w11,w11,w15 add v4.4s,v4.4s,v5.4s eor w12,w12,w16 add v8.4s,v8.4s,v9.4s ror w9,w9,#25 add v12.4s,v12.4s,v13.4s ror w10,w10,#25 add v16.4s,v16.4s,v17.4s ror w11,w11,#25 add v20.4s,v20.4s,v21.4s ror w12,w12,#25 eor v24.16b,v3.16b,v0.16b add w5,w5,w10 eor v25.16b,v7.16b,v4.16b add w6,w6,w11 eor v26.16b,v11.16b,v8.16b add w7,w7,w12 eor v27.16b,v15.16b,v12.16b add w8,w8,w9 eor v28.16b,v19.16b,v16.16b eor w21,w21,w5 eor v29.16b,v23.16b,v20.16b eor w17,w17,w6 ushr v3.4s,v24.4s,#24 eor w19,w19,w7 ushr v7.4s,v25.4s,#24 eor w20,w20,w8 ushr v11.4s,v26.4s,#24 ror w21,w21,#16 ushr v15.4s,v27.4s,#24 ror w17,w17,#16 ushr v19.4s,v28.4s,#24 ror w19,w19,#16 ushr v23.4s,v29.4s,#24 ror w20,w20,#16 sli v3.4s,v24.4s,#8 add w15,w15,w21 sli v7.4s,v25.4s,#8 add w16,w16,w17 sli v11.4s,v26.4s,#8 add w13,w13,w19 sli v15.4s,v27.4s,#8 add w14,w14,w20 sli v19.4s,v28.4s,#8 eor w10,w10,w15 sli v23.4s,v29.4s,#8 eor w11,w11,w16 add v2.4s,v2.4s,v3.4s eor w12,w12,w13 add v6.4s,v6.4s,v7.4s eor w9,w9,w14 add v10.4s,v10.4s,v11.4s ror w10,w10,#20 add v14.4s,v14.4s,v15.4s ror w11,w11,#20 add v18.4s,v18.4s,v19.4s ror w12,w12,#20 add v22.4s,v22.4s,v23.4s ror w9,w9,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w10 eor v25.16b,v5.16b,v6.16b add w6,w6,w11 eor v26.16b,v9.16b,v10.16b add w7,w7,w12 eor v27.16b,v13.16b,v14.16b add w8,w8,w9 eor v28.16b,v17.16b,v18.16b eor w21,w21,w5 eor v29.16b,v21.16b,v22.16b eor w17,w17,w6 ushr v1.4s,v24.4s,#25 eor w19,w19,w7 ushr v5.4s,v25.4s,#25 eor w20,w20,w8 ushr v9.4s,v26.4s,#25 ror w21,w21,#24 ushr v13.4s,v27.4s,#25 ror w17,w17,#24 ushr v17.4s,v28.4s,#25 ror w19,w19,#24 ushr v21.4s,v29.4s,#25 ror w20,w20,#24 sli v1.4s,v24.4s,#7 add w15,w15,w21 sli v5.4s,v25.4s,#7 add w16,w16,w17 sli v9.4s,v26.4s,#7 add w13,w13,w19 sli v13.4s,v27.4s,#7 add w14,w14,w20 sli v17.4s,v28.4s,#7 eor w10,w10,w15 sli v21.4s,v29.4s,#7 eor w11,w11,w16 ext v2.16b,v2.16b,v2.16b,#8 eor w12,w12,w13 ext v6.16b,v6.16b,v6.16b,#8 eor w9,w9,w14 ext v10.16b,v10.16b,v10.16b,#8 ror w10,w10,#25 ext v14.16b,v14.16b,v14.16b,#8 ror w11,w11,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w12,w12,#25 ext v22.16b,v22.16b,v22.16b,#8 ror w9,w9,#25 ext v3.16b,v3.16b,v3.16b,#12 ext v7.16b,v7.16b,v7.16b,#12 ext v11.16b,v11.16b,v11.16b,#12 ext v15.16b,v15.16b,v15.16b,#12 ext v19.16b,v19.16b,v19.16b,#12 ext v23.16b,v23.16b,v23.16b,#12 ext v1.16b,v1.16b,v1.16b,#4 ext v5.16b,v5.16b,v5.16b,#4 ext v9.16b,v9.16b,v9.16b,#4 ext v13.16b,v13.16b,v13.16b,#4 ext v17.16b,v17.16b,v17.16b,#4 ext v21.16b,v21.16b,v21.16b,#4 add v0.4s,v0.4s,v1.4s add w5,w5,w9 add v4.4s,v4.4s,v5.4s add w6,w6,w10 add v8.4s,v8.4s,v9.4s add w7,w7,w11 add v12.4s,v12.4s,v13.4s add w8,w8,w12 add v16.4s,v16.4s,v17.4s eor w17,w17,w5 add v20.4s,v20.4s,v21.4s eor w19,w19,w6 eor v3.16b,v3.16b,v0.16b eor w20,w20,w7 eor v7.16b,v7.16b,v4.16b eor w21,w21,w8 eor v11.16b,v11.16b,v8.16b ror w17,w17,#16 eor v15.16b,v15.16b,v12.16b ror w19,w19,#16 eor v19.16b,v19.16b,v16.16b ror w20,w20,#16 eor v23.16b,v23.16b,v20.16b ror w21,w21,#16 rev32 v3.8h,v3.8h add w13,w13,w17 rev32 v7.8h,v7.8h add w14,w14,w19 rev32 v11.8h,v11.8h add w15,w15,w20 rev32 v15.8h,v15.8h add w16,w16,w21 rev32 v19.8h,v19.8h eor w9,w9,w13 rev32 v23.8h,v23.8h eor w10,w10,w14 add v2.4s,v2.4s,v3.4s eor w11,w11,w15 add v6.4s,v6.4s,v7.4s eor w12,w12,w16 add v10.4s,v10.4s,v11.4s ror w9,w9,#20 add v14.4s,v14.4s,v15.4s ror w10,w10,#20 add v18.4s,v18.4s,v19.4s ror w11,w11,#20 add v22.4s,v22.4s,v23.4s ror w12,w12,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w9 eor v25.16b,v5.16b,v6.16b add w6,w6,w10 eor v26.16b,v9.16b,v10.16b add w7,w7,w11 eor v27.16b,v13.16b,v14.16b add w8,w8,w12 eor v28.16b,v17.16b,v18.16b eor w17,w17,w5 eor v29.16b,v21.16b,v22.16b eor w19,w19,w6 ushr v1.4s,v24.4s,#20 eor w20,w20,w7 ushr v5.4s,v25.4s,#20 eor w21,w21,w8 ushr v9.4s,v26.4s,#20 ror w17,w17,#24 ushr v13.4s,v27.4s,#20 ror w19,w19,#24 ushr v17.4s,v28.4s,#20 ror w20,w20,#24 ushr v21.4s,v29.4s,#20 ror w21,w21,#24 sli v1.4s,v24.4s,#12 add w13,w13,w17 sli v5.4s,v25.4s,#12 add w14,w14,w19 sli v9.4s,v26.4s,#12 add w15,w15,w20 sli v13.4s,v27.4s,#12 add w16,w16,w21 sli v17.4s,v28.4s,#12 eor w9,w9,w13 sli v21.4s,v29.4s,#12 eor w10,w10,w14 add v0.4s,v0.4s,v1.4s eor w11,w11,w15 add v4.4s,v4.4s,v5.4s eor w12,w12,w16 add v8.4s,v8.4s,v9.4s ror w9,w9,#25 add v12.4s,v12.4s,v13.4s ror w10,w10,#25 add v16.4s,v16.4s,v17.4s ror w11,w11,#25 add v20.4s,v20.4s,v21.4s ror w12,w12,#25 eor v24.16b,v3.16b,v0.16b add w5,w5,w10 eor v25.16b,v7.16b,v4.16b add w6,w6,w11 eor v26.16b,v11.16b,v8.16b add w7,w7,w12 eor v27.16b,v15.16b,v12.16b add w8,w8,w9 eor v28.16b,v19.16b,v16.16b eor w21,w21,w5 eor v29.16b,v23.16b,v20.16b eor w17,w17,w6 ushr v3.4s,v24.4s,#24 eor w19,w19,w7 ushr v7.4s,v25.4s,#24 eor w20,w20,w8 ushr v11.4s,v26.4s,#24 ror w21,w21,#16 ushr v15.4s,v27.4s,#24 ror w17,w17,#16 ushr v19.4s,v28.4s,#24 ror w19,w19,#16 ushr v23.4s,v29.4s,#24 ror w20,w20,#16 sli v3.4s,v24.4s,#8 add w15,w15,w21 sli v7.4s,v25.4s,#8 add w16,w16,w17 sli v11.4s,v26.4s,#8 add w13,w13,w19 sli v15.4s,v27.4s,#8 add w14,w14,w20 sli v19.4s,v28.4s,#8 eor w10,w10,w15 sli v23.4s,v29.4s,#8 eor w11,w11,w16 add v2.4s,v2.4s,v3.4s eor w12,w12,w13 add v6.4s,v6.4s,v7.4s eor w9,w9,w14 add v10.4s,v10.4s,v11.4s ror w10,w10,#20 add v14.4s,v14.4s,v15.4s ror w11,w11,#20 add v18.4s,v18.4s,v19.4s ror w12,w12,#20 add v22.4s,v22.4s,v23.4s ror w9,w9,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w10 eor v25.16b,v5.16b,v6.16b add w6,w6,w11 eor v26.16b,v9.16b,v10.16b add w7,w7,w12 eor v27.16b,v13.16b,v14.16b add w8,w8,w9 eor v28.16b,v17.16b,v18.16b eor w21,w21,w5 eor v29.16b,v21.16b,v22.16b eor w17,w17,w6 ushr v1.4s,v24.4s,#25 eor w19,w19,w7 ushr v5.4s,v25.4s,#25 eor w20,w20,w8 ushr v9.4s,v26.4s,#25 ror w21,w21,#24 ushr v13.4s,v27.4s,#25 ror w17,w17,#24 ushr v17.4s,v28.4s,#25 ror w19,w19,#24 ushr v21.4s,v29.4s,#25 ror w20,w20,#24 sli v1.4s,v24.4s,#7 add w15,w15,w21 sli v5.4s,v25.4s,#7 add w16,w16,w17 sli v9.4s,v26.4s,#7 add w13,w13,w19 sli v13.4s,v27.4s,#7 add w14,w14,w20 sli v17.4s,v28.4s,#7 eor w10,w10,w15 sli v21.4s,v29.4s,#7 eor w11,w11,w16 ext v2.16b,v2.16b,v2.16b,#8 eor w12,w12,w13 ext v6.16b,v6.16b,v6.16b,#8 eor w9,w9,w14 ext v10.16b,v10.16b,v10.16b,#8 ror w10,w10,#25 ext v14.16b,v14.16b,v14.16b,#8 ror w11,w11,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w12,w12,#25 ext v22.16b,v22.16b,v22.16b,#8 ror w9,w9,#25 ext v3.16b,v3.16b,v3.16b,#4 ext v7.16b,v7.16b,v7.16b,#4 ext v11.16b,v11.16b,v11.16b,#4 ext v15.16b,v15.16b,v15.16b,#4 ext v19.16b,v19.16b,v19.16b,#4 ext v23.16b,v23.16b,v23.16b,#4 ext v1.16b,v1.16b,v1.16b,#12 ext v5.16b,v5.16b,v5.16b,#12 ext v9.16b,v9.16b,v9.16b,#12 ext v13.16b,v13.16b,v13.16b,#12 ext v17.16b,v17.16b,v17.16b,#12 ext v21.16b,v21.16b,v21.16b,#12 cbnz x4,Loop_upper_neon add w5,w5,w22 // accumulate key block add x6,x6,x22,lsr#32 add w7,w7,w23 add x8,x8,x23,lsr#32 add w9,w9,w24 add x10,x10,x24,lsr#32 add w11,w11,w25 add x12,x12,x25,lsr#32 add w13,w13,w26 add x14,x14,x26,lsr#32 add w15,w15,w27 add x16,x16,x27,lsr#32 add w17,w17,w28 add x19,x19,x28,lsr#32 add w20,w20,w30 add x21,x21,x30,lsr#32 add x5,x5,x6,lsl#32 // pack add x7,x7,x8,lsl#32 ldp x6,x8,[x1,#0] // load input add x9,x9,x10,lsl#32 add x11,x11,x12,lsl#32 ldp x10,x12,[x1,#16] add x13,x13,x14,lsl#32 add x15,x15,x16,lsl#32 ldp x14,x16,[x1,#32] add x17,x17,x19,lsl#32 add x20,x20,x21,lsl#32 ldp x19,x21,[x1,#48] add x1,x1,#64 #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif eor x5,x5,x6 eor x7,x7,x8 eor x9,x9,x10 eor x11,x11,x12 eor x13,x13,x14 eor x15,x15,x16 eor x17,x17,x19 eor x20,x20,x21 stp x5,x7,[x0,#0] // store output add x28,x28,#1 // increment counter mov w5,w22 // unpack key block lsr x6,x22,#32 stp x9,x11,[x0,#16] mov w7,w23 lsr x8,x23,#32 stp x13,x15,[x0,#32] mov w9,w24 lsr x10,x24,#32 stp x17,x20,[x0,#48] add x0,x0,#64 mov w11,w25 lsr x12,x25,#32 mov w13,w26 lsr x14,x26,#32 mov w15,w27 lsr x16,x27,#32 mov w17,w28 lsr x19,x28,#32 mov w20,w30 lsr x21,x30,#32 mov x4,#5 Loop_lower_neon: sub x4,x4,#1 add v0.4s,v0.4s,v1.4s add w5,w5,w9 add v4.4s,v4.4s,v5.4s add w6,w6,w10 add v8.4s,v8.4s,v9.4s add w7,w7,w11 add v12.4s,v12.4s,v13.4s add w8,w8,w12 add v16.4s,v16.4s,v17.4s eor w17,w17,w5 add v20.4s,v20.4s,v21.4s eor w19,w19,w6 eor v3.16b,v3.16b,v0.16b eor w20,w20,w7 eor v7.16b,v7.16b,v4.16b eor w21,w21,w8 eor v11.16b,v11.16b,v8.16b ror w17,w17,#16 eor v15.16b,v15.16b,v12.16b ror w19,w19,#16 eor v19.16b,v19.16b,v16.16b ror w20,w20,#16 eor v23.16b,v23.16b,v20.16b ror w21,w21,#16 rev32 v3.8h,v3.8h add w13,w13,w17 rev32 v7.8h,v7.8h add w14,w14,w19 rev32 v11.8h,v11.8h add w15,w15,w20 rev32 v15.8h,v15.8h add w16,w16,w21 rev32 v19.8h,v19.8h eor w9,w9,w13 rev32 v23.8h,v23.8h eor w10,w10,w14 add v2.4s,v2.4s,v3.4s eor w11,w11,w15 add v6.4s,v6.4s,v7.4s eor w12,w12,w16 add v10.4s,v10.4s,v11.4s ror w9,w9,#20 add v14.4s,v14.4s,v15.4s ror w10,w10,#20 add v18.4s,v18.4s,v19.4s ror w11,w11,#20 add v22.4s,v22.4s,v23.4s ror w12,w12,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w9 eor v25.16b,v5.16b,v6.16b add w6,w6,w10 eor v26.16b,v9.16b,v10.16b add w7,w7,w11 eor v27.16b,v13.16b,v14.16b add w8,w8,w12 eor v28.16b,v17.16b,v18.16b eor w17,w17,w5 eor v29.16b,v21.16b,v22.16b eor w19,w19,w6 ushr v1.4s,v24.4s,#20 eor w20,w20,w7 ushr v5.4s,v25.4s,#20 eor w21,w21,w8 ushr v9.4s,v26.4s,#20 ror w17,w17,#24 ushr v13.4s,v27.4s,#20 ror w19,w19,#24 ushr v17.4s,v28.4s,#20 ror w20,w20,#24 ushr v21.4s,v29.4s,#20 ror w21,w21,#24 sli v1.4s,v24.4s,#12 add w13,w13,w17 sli v5.4s,v25.4s,#12 add w14,w14,w19 sli v9.4s,v26.4s,#12 add w15,w15,w20 sli v13.4s,v27.4s,#12 add w16,w16,w21 sli v17.4s,v28.4s,#12 eor w9,w9,w13 sli v21.4s,v29.4s,#12 eor w10,w10,w14 add v0.4s,v0.4s,v1.4s eor w11,w11,w15 add v4.4s,v4.4s,v5.4s eor w12,w12,w16 add v8.4s,v8.4s,v9.4s ror w9,w9,#25 add v12.4s,v12.4s,v13.4s ror w10,w10,#25 add v16.4s,v16.4s,v17.4s ror w11,w11,#25 add v20.4s,v20.4s,v21.4s ror w12,w12,#25 eor v24.16b,v3.16b,v0.16b add w5,w5,w10 eor v25.16b,v7.16b,v4.16b add w6,w6,w11 eor v26.16b,v11.16b,v8.16b add w7,w7,w12 eor v27.16b,v15.16b,v12.16b add w8,w8,w9 eor v28.16b,v19.16b,v16.16b eor w21,w21,w5 eor v29.16b,v23.16b,v20.16b eor w17,w17,w6 ushr v3.4s,v24.4s,#24 eor w19,w19,w7 ushr v7.4s,v25.4s,#24 eor w20,w20,w8 ushr v11.4s,v26.4s,#24 ror w21,w21,#16 ushr v15.4s,v27.4s,#24 ror w17,w17,#16 ushr v19.4s,v28.4s,#24 ror w19,w19,#16 ushr v23.4s,v29.4s,#24 ror w20,w20,#16 sli v3.4s,v24.4s,#8 add w15,w15,w21 sli v7.4s,v25.4s,#8 add w16,w16,w17 sli v11.4s,v26.4s,#8 add w13,w13,w19 sli v15.4s,v27.4s,#8 add w14,w14,w20 sli v19.4s,v28.4s,#8 eor w10,w10,w15 sli v23.4s,v29.4s,#8 eor w11,w11,w16 add v2.4s,v2.4s,v3.4s eor w12,w12,w13 add v6.4s,v6.4s,v7.4s eor w9,w9,w14 add v10.4s,v10.4s,v11.4s ror w10,w10,#20 add v14.4s,v14.4s,v15.4s ror w11,w11,#20 add v18.4s,v18.4s,v19.4s ror w12,w12,#20 add v22.4s,v22.4s,v23.4s ror w9,w9,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w10 eor v25.16b,v5.16b,v6.16b add w6,w6,w11 eor v26.16b,v9.16b,v10.16b add w7,w7,w12 eor v27.16b,v13.16b,v14.16b add w8,w8,w9 eor v28.16b,v17.16b,v18.16b eor w21,w21,w5 eor v29.16b,v21.16b,v22.16b eor w17,w17,w6 ushr v1.4s,v24.4s,#25 eor w19,w19,w7 ushr v5.4s,v25.4s,#25 eor w20,w20,w8 ushr v9.4s,v26.4s,#25 ror w21,w21,#24 ushr v13.4s,v27.4s,#25 ror w17,w17,#24 ushr v17.4s,v28.4s,#25 ror w19,w19,#24 ushr v21.4s,v29.4s,#25 ror w20,w20,#24 sli v1.4s,v24.4s,#7 add w15,w15,w21 sli v5.4s,v25.4s,#7 add w16,w16,w17 sli v9.4s,v26.4s,#7 add w13,w13,w19 sli v13.4s,v27.4s,#7 add w14,w14,w20 sli v17.4s,v28.4s,#7 eor w10,w10,w15 sli v21.4s,v29.4s,#7 eor w11,w11,w16 ext v2.16b,v2.16b,v2.16b,#8 eor w12,w12,w13 ext v6.16b,v6.16b,v6.16b,#8 eor w9,w9,w14 ext v10.16b,v10.16b,v10.16b,#8 ror w10,w10,#25 ext v14.16b,v14.16b,v14.16b,#8 ror w11,w11,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w12,w12,#25 ext v22.16b,v22.16b,v22.16b,#8 ror w9,w9,#25 ext v3.16b,v3.16b,v3.16b,#12 ext v7.16b,v7.16b,v7.16b,#12 ext v11.16b,v11.16b,v11.16b,#12 ext v15.16b,v15.16b,v15.16b,#12 ext v19.16b,v19.16b,v19.16b,#12 ext v23.16b,v23.16b,v23.16b,#12 ext v1.16b,v1.16b,v1.16b,#4 ext v5.16b,v5.16b,v5.16b,#4 ext v9.16b,v9.16b,v9.16b,#4 ext v13.16b,v13.16b,v13.16b,#4 ext v17.16b,v17.16b,v17.16b,#4 ext v21.16b,v21.16b,v21.16b,#4 add v0.4s,v0.4s,v1.4s add w5,w5,w9 add v4.4s,v4.4s,v5.4s add w6,w6,w10 add v8.4s,v8.4s,v9.4s add w7,w7,w11 add v12.4s,v12.4s,v13.4s add w8,w8,w12 add v16.4s,v16.4s,v17.4s eor w17,w17,w5 add v20.4s,v20.4s,v21.4s eor w19,w19,w6 eor v3.16b,v3.16b,v0.16b eor w20,w20,w7 eor v7.16b,v7.16b,v4.16b eor w21,w21,w8 eor v11.16b,v11.16b,v8.16b ror w17,w17,#16 eor v15.16b,v15.16b,v12.16b ror w19,w19,#16 eor v19.16b,v19.16b,v16.16b ror w20,w20,#16 eor v23.16b,v23.16b,v20.16b ror w21,w21,#16 rev32 v3.8h,v3.8h add w13,w13,w17 rev32 v7.8h,v7.8h add w14,w14,w19 rev32 v11.8h,v11.8h add w15,w15,w20 rev32 v15.8h,v15.8h add w16,w16,w21 rev32 v19.8h,v19.8h eor w9,w9,w13 rev32 v23.8h,v23.8h eor w10,w10,w14 add v2.4s,v2.4s,v3.4s eor w11,w11,w15 add v6.4s,v6.4s,v7.4s eor w12,w12,w16 add v10.4s,v10.4s,v11.4s ror w9,w9,#20 add v14.4s,v14.4s,v15.4s ror w10,w10,#20 add v18.4s,v18.4s,v19.4s ror w11,w11,#20 add v22.4s,v22.4s,v23.4s ror w12,w12,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w9 eor v25.16b,v5.16b,v6.16b add w6,w6,w10 eor v26.16b,v9.16b,v10.16b add w7,w7,w11 eor v27.16b,v13.16b,v14.16b add w8,w8,w12 eor v28.16b,v17.16b,v18.16b eor w17,w17,w5 eor v29.16b,v21.16b,v22.16b eor w19,w19,w6 ushr v1.4s,v24.4s,#20 eor w20,w20,w7 ushr v5.4s,v25.4s,#20 eor w21,w21,w8 ushr v9.4s,v26.4s,#20 ror w17,w17,#24 ushr v13.4s,v27.4s,#20 ror w19,w19,#24 ushr v17.4s,v28.4s,#20 ror w20,w20,#24 ushr v21.4s,v29.4s,#20 ror w21,w21,#24 sli v1.4s,v24.4s,#12 add w13,w13,w17 sli v5.4s,v25.4s,#12 add w14,w14,w19 sli v9.4s,v26.4s,#12 add w15,w15,w20 sli v13.4s,v27.4s,#12 add w16,w16,w21 sli v17.4s,v28.4s,#12 eor w9,w9,w13 sli v21.4s,v29.4s,#12 eor w10,w10,w14 add v0.4s,v0.4s,v1.4s eor w11,w11,w15 add v4.4s,v4.4s,v5.4s eor w12,w12,w16 add v8.4s,v8.4s,v9.4s ror w9,w9,#25 add v12.4s,v12.4s,v13.4s ror w10,w10,#25 add v16.4s,v16.4s,v17.4s ror w11,w11,#25 add v20.4s,v20.4s,v21.4s ror w12,w12,#25 eor v24.16b,v3.16b,v0.16b add w5,w5,w10 eor v25.16b,v7.16b,v4.16b add w6,w6,w11 eor v26.16b,v11.16b,v8.16b add w7,w7,w12 eor v27.16b,v15.16b,v12.16b add w8,w8,w9 eor v28.16b,v19.16b,v16.16b eor w21,w21,w5 eor v29.16b,v23.16b,v20.16b eor w17,w17,w6 ushr v3.4s,v24.4s,#24 eor w19,w19,w7 ushr v7.4s,v25.4s,#24 eor w20,w20,w8 ushr v11.4s,v26.4s,#24 ror w21,w21,#16 ushr v15.4s,v27.4s,#24 ror w17,w17,#16 ushr v19.4s,v28.4s,#24 ror w19,w19,#16 ushr v23.4s,v29.4s,#24 ror w20,w20,#16 sli v3.4s,v24.4s,#8 add w15,w15,w21 sli v7.4s,v25.4s,#8 add w16,w16,w17 sli v11.4s,v26.4s,#8 add w13,w13,w19 sli v15.4s,v27.4s,#8 add w14,w14,w20 sli v19.4s,v28.4s,#8 eor w10,w10,w15 sli v23.4s,v29.4s,#8 eor w11,w11,w16 add v2.4s,v2.4s,v3.4s eor w12,w12,w13 add v6.4s,v6.4s,v7.4s eor w9,w9,w14 add v10.4s,v10.4s,v11.4s ror w10,w10,#20 add v14.4s,v14.4s,v15.4s ror w11,w11,#20 add v18.4s,v18.4s,v19.4s ror w12,w12,#20 add v22.4s,v22.4s,v23.4s ror w9,w9,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w10 eor v25.16b,v5.16b,v6.16b add w6,w6,w11 eor v26.16b,v9.16b,v10.16b add w7,w7,w12 eor v27.16b,v13.16b,v14.16b add w8,w8,w9 eor v28.16b,v17.16b,v18.16b eor w21,w21,w5 eor v29.16b,v21.16b,v22.16b eor w17,w17,w6 ushr v1.4s,v24.4s,#25 eor w19,w19,w7 ushr v5.4s,v25.4s,#25 eor w20,w20,w8 ushr v9.4s,v26.4s,#25 ror w21,w21,#24 ushr v13.4s,v27.4s,#25 ror w17,w17,#24 ushr v17.4s,v28.4s,#25 ror w19,w19,#24 ushr v21.4s,v29.4s,#25 ror w20,w20,#24 sli v1.4s,v24.4s,#7 add w15,w15,w21 sli v5.4s,v25.4s,#7 add w16,w16,w17 sli v9.4s,v26.4s,#7 add w13,w13,w19 sli v13.4s,v27.4s,#7 add w14,w14,w20 sli v17.4s,v28.4s,#7 eor w10,w10,w15 sli v21.4s,v29.4s,#7 eor w11,w11,w16 ext v2.16b,v2.16b,v2.16b,#8 eor w12,w12,w13 ext v6.16b,v6.16b,v6.16b,#8 eor w9,w9,w14 ext v10.16b,v10.16b,v10.16b,#8 ror w10,w10,#25 ext v14.16b,v14.16b,v14.16b,#8 ror w11,w11,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w12,w12,#25 ext v22.16b,v22.16b,v22.16b,#8 ror w9,w9,#25 ext v3.16b,v3.16b,v3.16b,#4 ext v7.16b,v7.16b,v7.16b,#4 ext v11.16b,v11.16b,v11.16b,#4 ext v15.16b,v15.16b,v15.16b,#4 ext v19.16b,v19.16b,v19.16b,#4 ext v23.16b,v23.16b,v23.16b,#4 ext v1.16b,v1.16b,v1.16b,#12 ext v5.16b,v5.16b,v5.16b,#12 ext v9.16b,v9.16b,v9.16b,#12 ext v13.16b,v13.16b,v13.16b,#12 ext v17.16b,v17.16b,v17.16b,#12 ext v21.16b,v21.16b,v21.16b,#12 cbnz x4,Loop_lower_neon add w5,w5,w22 // accumulate key block ldp q24,q25,[sp,#0] add x6,x6,x22,lsr#32 ldp q26,q27,[sp,#32] add w7,w7,w23 ldp q28,q29,[sp,#64] add x8,x8,x23,lsr#32 add v0.4s,v0.4s,v24.4s add w9,w9,w24 add v4.4s,v4.4s,v24.4s add x10,x10,x24,lsr#32 add v8.4s,v8.4s,v24.4s add w11,w11,w25 add v12.4s,v12.4s,v24.4s add x12,x12,x25,lsr#32 add v16.4s,v16.4s,v24.4s add w13,w13,w26 add v20.4s,v20.4s,v24.4s add x14,x14,x26,lsr#32 add v2.4s,v2.4s,v26.4s add w15,w15,w27 add v6.4s,v6.4s,v26.4s add x16,x16,x27,lsr#32 add v10.4s,v10.4s,v26.4s add w17,w17,w28 add v14.4s,v14.4s,v26.4s add x19,x19,x28,lsr#32 add v18.4s,v18.4s,v26.4s add w20,w20,w30 add v22.4s,v22.4s,v26.4s add x21,x21,x30,lsr#32 add v19.4s,v19.4s,v31.4s // +4 add x5,x5,x6,lsl#32 // pack add v23.4s,v23.4s,v31.4s // +4 add x7,x7,x8,lsl#32 add v3.4s,v3.4s,v27.4s ldp x6,x8,[x1,#0] // load input add v7.4s,v7.4s,v28.4s add x9,x9,x10,lsl#32 add v11.4s,v11.4s,v29.4s add x11,x11,x12,lsl#32 add v15.4s,v15.4s,v30.4s ldp x10,x12,[x1,#16] add v19.4s,v19.4s,v27.4s add x13,x13,x14,lsl#32 add v23.4s,v23.4s,v28.4s add x15,x15,x16,lsl#32 add v1.4s,v1.4s,v25.4s ldp x14,x16,[x1,#32] add v5.4s,v5.4s,v25.4s add x17,x17,x19,lsl#32 add v9.4s,v9.4s,v25.4s add x20,x20,x21,lsl#32 add v13.4s,v13.4s,v25.4s ldp x19,x21,[x1,#48] add v17.4s,v17.4s,v25.4s add x1,x1,#64 add v21.4s,v21.4s,v25.4s #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif ld1 {v24.16b,v25.16b,v26.16b,v27.16b},[x1],#64 eor x5,x5,x6 eor x7,x7,x8 eor x9,x9,x10 eor x11,x11,x12 eor x13,x13,x14 eor v0.16b,v0.16b,v24.16b eor x15,x15,x16 eor v1.16b,v1.16b,v25.16b eor x17,x17,x19 eor v2.16b,v2.16b,v26.16b eor x20,x20,x21 eor v3.16b,v3.16b,v27.16b ld1 {v24.16b,v25.16b,v26.16b,v27.16b},[x1],#64 stp x5,x7,[x0,#0] // store output add x28,x28,#7 // increment counter stp x9,x11,[x0,#16] stp x13,x15,[x0,#32] stp x17,x20,[x0,#48] add x0,x0,#64 st1 {v0.16b,v1.16b,v2.16b,v3.16b},[x0],#64 ld1 {v0.16b,v1.16b,v2.16b,v3.16b},[x1],#64 eor v4.16b,v4.16b,v24.16b eor v5.16b,v5.16b,v25.16b eor v6.16b,v6.16b,v26.16b eor v7.16b,v7.16b,v27.16b st1 {v4.16b,v5.16b,v6.16b,v7.16b},[x0],#64 ld1 {v4.16b,v5.16b,v6.16b,v7.16b},[x1],#64 eor v8.16b,v8.16b,v0.16b ldp q24,q25,[sp,#0] eor v9.16b,v9.16b,v1.16b ldp q26,q27,[sp,#32] eor v10.16b,v10.16b,v2.16b eor v11.16b,v11.16b,v3.16b st1 {v8.16b,v9.16b,v10.16b,v11.16b},[x0],#64 ld1 {v8.16b,v9.16b,v10.16b,v11.16b},[x1],#64 eor v12.16b,v12.16b,v4.16b eor v13.16b,v13.16b,v5.16b eor v14.16b,v14.16b,v6.16b eor v15.16b,v15.16b,v7.16b st1 {v12.16b,v13.16b,v14.16b,v15.16b},[x0],#64 ld1 {v12.16b,v13.16b,v14.16b,v15.16b},[x1],#64 eor v16.16b,v16.16b,v8.16b eor v17.16b,v17.16b,v9.16b eor v18.16b,v18.16b,v10.16b eor v19.16b,v19.16b,v11.16b st1 {v16.16b,v17.16b,v18.16b,v19.16b},[x0],#64 shl v0.4s,v31.4s,#1 // 4 -> 8 eor v20.16b,v20.16b,v12.16b eor v21.16b,v21.16b,v13.16b eor v22.16b,v22.16b,v14.16b eor v23.16b,v23.16b,v15.16b st1 {v20.16b,v21.16b,v22.16b,v23.16b},[x0],#64 add v27.4s,v27.4s,v0.4s // += 8 add v28.4s,v28.4s,v0.4s add v29.4s,v29.4s,v0.4s add v30.4s,v30.4s,v0.4s b.hs Loop_outer_512_neon adds x2,x2,#512 ushr v0.4s,v31.4s,#2 // 4 -> 1 ldp d8,d9,[sp,#128+0] // meet ABI requirements ldp d10,d11,[sp,#128+16] ldp d12,d13,[sp,#128+32] ldp d14,d15,[sp,#128+48] stp q24,q31,[sp,#0] // wipe off-load area stp q24,q31,[sp,#32] stp q24,q31,[sp,#64] b.eq Ldone_512_neon cmp x2,#192 sub v27.4s,v27.4s,v0.4s // -= 1 sub v28.4s,v28.4s,v0.4s sub v29.4s,v29.4s,v0.4s add sp,sp,#128 b.hs Loop_outer_neon eor v25.16b,v25.16b,v25.16b eor v26.16b,v26.16b,v26.16b eor v27.16b,v27.16b,v27.16b eor v28.16b,v28.16b,v28.16b eor v29.16b,v29.16b,v29.16b eor v30.16b,v30.16b,v30.16b b Loop_outer Ldone_512_neon: ldp x19,x20,[x29,#16] add sp,sp,#128+64 ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret #endif // !OPENSSL_NO_ASM && defined(OPENSSL_AARCH64) && defined(_WIN32)
j4yc3-mw/Viren	77,139	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/p256-x86_64-asm-elf.S	// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__ELF__) .text .extern OPENSSL_ia32cap_P .hidden OPENSSL_ia32cap_P .section .rodata .align 64 .Lpoly: .quad 0xffffffffffffffff, 0x00000000ffffffff, 0x0000000000000000, 0xffffffff00000001 .LOne: .long 1,1,1,1,1,1,1,1 .LTwo: .long 2,2,2,2,2,2,2,2 .LThree: .long 3,3,3,3,3,3,3,3 .LONE_mont: .quad 0x0000000000000001, 0xffffffff00000000, 0xffffffffffffffff, 0x00000000fffffffe .Lord: .quad 0xf3b9cac2fc632551, 0xbce6faada7179e84, 0xffffffffffffffff, 0xffffffff00000000 .LordK: .quad 0xccd1c8aaee00bc4f .text .globl ecp_nistz256_neg .hidden ecp_nistz256_neg .type ecp_nistz256_neg,@function .align 32 ecp_nistz256_neg: .cfi_startproc _CET_ENDBR pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-16 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-24 .Lneg_body: xorq %r8,%r8 xorq %r9,%r9 xorq %r10,%r10 xorq %r11,%r11 xorq %r13,%r13 subq 0(%rsi),%r8 sbbq 8(%rsi),%r9 sbbq 16(%rsi),%r10 movq %r8,%rax sbbq 24(%rsi),%r11 leaq .Lpoly(%rip),%rsi movq %r9,%rdx sbbq $0,%r13 addq 0(%rsi),%r8 movq %r10,%rcx adcq 8(%rsi),%r9 adcq 16(%rsi),%r10 movq %r11,%r12 adcq 24(%rsi),%r11 testq %r13,%r13 cmovzq %rax,%r8 cmovzq %rdx,%r9 movq %r8,0(%rdi) cmovzq %rcx,%r10 movq %r9,8(%rdi) cmovzq %r12,%r11 movq %r10,16(%rdi) movq %r11,24(%rdi) movq 0(%rsp),%r13 .cfi_restore %r13 movq 8(%rsp),%r12 .cfi_restore %r12 leaq 16(%rsp),%rsp .cfi_adjust_cfa_offset -16 .Lneg_epilogue: ret .cfi_endproc .size ecp_nistz256_neg,.-ecp_nistz256_neg .globl ecp_nistz256_ord_mul_mont .hidden ecp_nistz256_ord_mul_mont .type ecp_nistz256_ord_mul_mont,@function .align 32 ecp_nistz256_ord_mul_mont: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx cmpl $0x80100,%ecx je .Lecp_nistz256_ord_mul_montx pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lord_mul_body: movq 0(%rdx),%rax movq %rdx,%rbx leaq .Lord(%rip),%r14 movq .LordK(%rip),%r15 movq %rax,%rcx mulq 0(%rsi) movq %rax,%r8 movq %rcx,%rax movq %rdx,%r9 mulq 8(%rsi) addq %rax,%r9 movq %rcx,%rax adcq $0,%rdx movq %rdx,%r10 mulq 16(%rsi) addq %rax,%r10 movq %rcx,%rax adcq $0,%rdx movq %r8,%r13 imulq %r15,%r8 movq %rdx,%r11 mulq 24(%rsi) addq %rax,%r11 movq %r8,%rax adcq $0,%rdx movq %rdx,%r12 mulq 0(%r14) movq %r8,%rbp addq %rax,%r13 movq %r8,%rax adcq $0,%rdx movq %rdx,%rcx subq %r8,%r10 sbbq $0,%r8 mulq 8(%r14) addq %rcx,%r9 adcq $0,%rdx addq %rax,%r9 movq %rbp,%rax adcq %rdx,%r10 movq %rbp,%rdx adcq $0,%r8 shlq $32,%rax shrq $32,%rdx subq %rax,%r11 movq 8(%rbx),%rax sbbq %rdx,%rbp addq %r8,%r11 adcq %rbp,%r12 adcq $0,%r13 movq %rax,%rcx mulq 0(%rsi) addq %rax,%r9 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 8(%rsi) addq %rbp,%r10 adcq $0,%rdx addq %rax,%r10 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 16(%rsi) addq %rbp,%r11 adcq $0,%rdx addq %rax,%r11 movq %rcx,%rax adcq $0,%rdx movq %r9,%rcx imulq %r15,%r9 movq %rdx,%rbp mulq 24(%rsi) addq %rbp,%r12 adcq $0,%rdx xorq %r8,%r8 addq %rax,%r12 movq %r9,%rax adcq %rdx,%r13 adcq $0,%r8 mulq 0(%r14) movq %r9,%rbp addq %rax,%rcx movq %r9,%rax adcq %rdx,%rcx subq %r9,%r11 sbbq $0,%r9 mulq 8(%r14) addq %rcx,%r10 adcq $0,%rdx addq %rax,%r10 movq %rbp,%rax adcq %rdx,%r11 movq %rbp,%rdx adcq $0,%r9 shlq $32,%rax shrq $32,%rdx subq %rax,%r12 movq 16(%rbx),%rax sbbq %rdx,%rbp addq %r9,%r12 adcq %rbp,%r13 adcq $0,%r8 movq %rax,%rcx mulq 0(%rsi) addq %rax,%r10 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 8(%rsi) addq %rbp,%r11 adcq $0,%rdx addq %rax,%r11 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 16(%rsi) addq %rbp,%r12 adcq $0,%rdx addq %rax,%r12 movq %rcx,%rax adcq $0,%rdx movq %r10,%rcx imulq %r15,%r10 movq %rdx,%rbp mulq 24(%rsi) addq %rbp,%r13 adcq $0,%rdx xorq %r9,%r9 addq %rax,%r13 movq %r10,%rax adcq %rdx,%r8 adcq $0,%r9 mulq 0(%r14) movq %r10,%rbp addq %rax,%rcx movq %r10,%rax adcq %rdx,%rcx subq %r10,%r12 sbbq $0,%r10 mulq 8(%r14) addq %rcx,%r11 adcq $0,%rdx addq %rax,%r11 movq %rbp,%rax adcq %rdx,%r12 movq %rbp,%rdx adcq $0,%r10 shlq $32,%rax shrq $32,%rdx subq %rax,%r13 movq 24(%rbx),%rax sbbq %rdx,%rbp addq %r10,%r13 adcq %rbp,%r8 adcq $0,%r9 movq %rax,%rcx mulq 0(%rsi) addq %rax,%r11 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 8(%rsi) addq %rbp,%r12 adcq $0,%rdx addq %rax,%r12 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 16(%rsi) addq %rbp,%r13 adcq $0,%rdx addq %rax,%r13 movq %rcx,%rax adcq $0,%rdx movq %r11,%rcx imulq %r15,%r11 movq %rdx,%rbp mulq 24(%rsi) addq %rbp,%r8 adcq $0,%rdx xorq %r10,%r10 addq %rax,%r8 movq %r11,%rax adcq %rdx,%r9 adcq $0,%r10 mulq 0(%r14) movq %r11,%rbp addq %rax,%rcx movq %r11,%rax adcq %rdx,%rcx subq %r11,%r13 sbbq $0,%r11 mulq 8(%r14) addq %rcx,%r12 adcq $0,%rdx addq %rax,%r12 movq %rbp,%rax adcq %rdx,%r13 movq %rbp,%rdx adcq $0,%r11 shlq $32,%rax shrq $32,%rdx subq %rax,%r8 sbbq %rdx,%rbp addq %r11,%r8 adcq %rbp,%r9 adcq $0,%r10 movq %r12,%rsi subq 0(%r14),%r12 movq %r13,%r11 sbbq 8(%r14),%r13 movq %r8,%rcx sbbq 16(%r14),%r8 movq %r9,%rbp sbbq 24(%r14),%r9 sbbq $0,%r10 cmovcq %rsi,%r12 cmovcq %r11,%r13 cmovcq %rcx,%r8 cmovcq %rbp,%r9 movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lord_mul_epilogue: ret .cfi_endproc .size ecp_nistz256_ord_mul_mont,.-ecp_nistz256_ord_mul_mont .globl ecp_nistz256_ord_sqr_mont .hidden ecp_nistz256_ord_sqr_mont .type ecp_nistz256_ord_sqr_mont,@function .align 32 ecp_nistz256_ord_sqr_mont: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx cmpl $0x80100,%ecx je .Lecp_nistz256_ord_sqr_montx pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lord_sqr_body: movq 0(%rsi),%r8 movq 8(%rsi),%rax movq 16(%rsi),%r14 movq 24(%rsi),%r15 leaq .Lord(%rip),%rsi movq %rdx,%rbx jmp .Loop_ord_sqr .align 32 .Loop_ord_sqr: movq %rax,%rbp mulq %r8 movq %rax,%r9 .byte 102,72,15,110,205 movq %r14,%rax movq %rdx,%r10 mulq %r8 addq %rax,%r10 movq %r15,%rax .byte 102,73,15,110,214 adcq $0,%rdx movq %rdx,%r11 mulq %r8 addq %rax,%r11 movq %r15,%rax .byte 102,73,15,110,223 adcq $0,%rdx movq %rdx,%r12 mulq %r14 movq %rax,%r13 movq %r14,%rax movq %rdx,%r14 mulq %rbp addq %rax,%r11 movq %r15,%rax adcq $0,%rdx movq %rdx,%r15 mulq %rbp addq %rax,%r12 adcq $0,%rdx addq %r15,%r12 adcq %rdx,%r13 adcq $0,%r14 xorq %r15,%r15 movq %r8,%rax addq %r9,%r9 adcq %r10,%r10 adcq %r11,%r11 adcq %r12,%r12 adcq %r13,%r13 adcq %r14,%r14 adcq $0,%r15 mulq %rax movq %rax,%r8 .byte 102,72,15,126,200 movq %rdx,%rbp mulq %rax addq %rbp,%r9 adcq %rax,%r10 .byte 102,72,15,126,208 adcq $0,%rdx movq %rdx,%rbp mulq %rax addq %rbp,%r11 adcq %rax,%r12 .byte 102,72,15,126,216 adcq $0,%rdx movq %rdx,%rbp movq %r8,%rcx imulq 32(%rsi),%r8 mulq %rax addq %rbp,%r13 adcq %rax,%r14 movq 0(%rsi),%rax adcq %rdx,%r15 mulq %r8 movq %r8,%rbp addq %rax,%rcx movq 8(%rsi),%rax adcq %rdx,%rcx subq %r8,%r10 sbbq $0,%rbp mulq %r8 addq %rcx,%r9 adcq $0,%rdx addq %rax,%r9 movq %r8,%rax adcq %rdx,%r10 movq %r8,%rdx adcq $0,%rbp movq %r9,%rcx imulq 32(%rsi),%r9 shlq $32,%rax shrq $32,%rdx subq %rax,%r11 movq 0(%rsi),%rax sbbq %rdx,%r8 addq %rbp,%r11 adcq $0,%r8 mulq %r9 movq %r9,%rbp addq %rax,%rcx movq 8(%rsi),%rax adcq %rdx,%rcx subq %r9,%r11 sbbq $0,%rbp mulq %r9 addq %rcx,%r10 adcq $0,%rdx addq %rax,%r10 movq %r9,%rax adcq %rdx,%r11 movq %r9,%rdx adcq $0,%rbp movq %r10,%rcx imulq 32(%rsi),%r10 shlq $32,%rax shrq $32,%rdx subq %rax,%r8 movq 0(%rsi),%rax sbbq %rdx,%r9 addq %rbp,%r8 adcq $0,%r9 mulq %r10 movq %r10,%rbp addq %rax,%rcx movq 8(%rsi),%rax adcq %rdx,%rcx subq %r10,%r8 sbbq $0,%rbp mulq %r10 addq %rcx,%r11 adcq $0,%rdx addq %rax,%r11 movq %r10,%rax adcq %rdx,%r8 movq %r10,%rdx adcq $0,%rbp movq %r11,%rcx imulq 32(%rsi),%r11 shlq $32,%rax shrq $32,%rdx subq %rax,%r9 movq 0(%rsi),%rax sbbq %rdx,%r10 addq %rbp,%r9 adcq $0,%r10 mulq %r11 movq %r11,%rbp addq %rax,%rcx movq 8(%rsi),%rax adcq %rdx,%rcx subq %r11,%r9 sbbq $0,%rbp mulq %r11 addq %rcx,%r8 adcq $0,%rdx addq %rax,%r8 movq %r11,%rax adcq %rdx,%r9 movq %r11,%rdx adcq $0,%rbp shlq $32,%rax shrq $32,%rdx subq %rax,%r10 sbbq %rdx,%r11 addq %rbp,%r10 adcq $0,%r11 xorq %rdx,%rdx addq %r12,%r8 adcq %r13,%r9 movq %r8,%r12 adcq %r14,%r10 adcq %r15,%r11 movq %r9,%rax adcq $0,%rdx subq 0(%rsi),%r8 movq %r10,%r14 sbbq 8(%rsi),%r9 sbbq 16(%rsi),%r10 movq %r11,%r15 sbbq 24(%rsi),%r11 sbbq $0,%rdx cmovcq %r12,%r8 cmovncq %r9,%rax cmovncq %r10,%r14 cmovncq %r11,%r15 decq %rbx jnz .Loop_ord_sqr movq %r8,0(%rdi) movq %rax,8(%rdi) pxor %xmm1,%xmm1 movq %r14,16(%rdi) pxor %xmm2,%xmm2 movq %r15,24(%rdi) pxor %xmm3,%xmm3 movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lord_sqr_epilogue: ret .cfi_endproc .size ecp_nistz256_ord_sqr_mont,.-ecp_nistz256_ord_sqr_mont .type ecp_nistz256_ord_mul_montx,@function .align 32 ecp_nistz256_ord_mul_montx: .cfi_startproc .Lecp_nistz256_ord_mul_montx: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lord_mulx_body: movq %rdx,%rbx movq 0(%rdx),%rdx movq 0(%rsi),%r9 movq 8(%rsi),%r10 movq 16(%rsi),%r11 movq 24(%rsi),%r12 leaq -128(%rsi),%rsi leaq .Lord-128(%rip),%r14 movq .LordK(%rip),%r15 mulxq %r9,%r8,%r9 mulxq %r10,%rcx,%r10 mulxq %r11,%rbp,%r11 addq %rcx,%r9 mulxq %r12,%rcx,%r12 movq %r8,%rdx mulxq %r15,%rdx,%rax adcq %rbp,%r10 adcq %rcx,%r11 adcq $0,%r12 xorq %r13,%r13 mulxq 0+128(%r14),%rcx,%rbp adcxq %rcx,%r8 adoxq %rbp,%r9 mulxq 8+128(%r14),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 mulxq 16+128(%r14),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 24+128(%r14),%rcx,%rbp movq 8(%rbx),%rdx adcxq %rcx,%r11 adoxq %rbp,%r12 adcxq %r8,%r12 adoxq %r8,%r13 adcq $0,%r13 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 24+128(%rsi),%rcx,%rbp movq %r9,%rdx mulxq %r15,%rdx,%rax adcxq %rcx,%r12 adoxq %rbp,%r13 adcxq %r8,%r13 adoxq %r8,%r8 adcq $0,%r8 mulxq 0+128(%r14),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 mulxq 8+128(%r14),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 16+128(%r14),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 24+128(%r14),%rcx,%rbp movq 16(%rbx),%rdx adcxq %rcx,%r12 adoxq %rbp,%r13 adcxq %r9,%r13 adoxq %r9,%r8 adcq $0,%r8 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 24+128(%rsi),%rcx,%rbp movq %r10,%rdx mulxq %r15,%rdx,%rax adcxq %rcx,%r13 adoxq %rbp,%r8 adcxq %r9,%r8 adoxq %r9,%r9 adcq $0,%r9 mulxq 0+128(%r14),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 8+128(%r14),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 16+128(%r14),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 24+128(%r14),%rcx,%rbp movq 24(%rbx),%rdx adcxq %rcx,%r13 adoxq %rbp,%r8 adcxq %r10,%r8 adoxq %r10,%r9 adcq $0,%r9 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r13 adoxq %rbp,%r8 mulxq 24+128(%rsi),%rcx,%rbp movq %r11,%rdx mulxq %r15,%rdx,%rax adcxq %rcx,%r8 adoxq %rbp,%r9 adcxq %r10,%r9 adoxq %r10,%r10 adcq $0,%r10 mulxq 0+128(%r14),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 8+128(%r14),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 16+128(%r14),%rcx,%rbp adcxq %rcx,%r13 adoxq %rbp,%r8 mulxq 24+128(%r14),%rcx,%rbp leaq 128(%r14),%r14 movq %r12,%rbx adcxq %rcx,%r8 adoxq %rbp,%r9 movq %r13,%rdx adcxq %r11,%r9 adoxq %r11,%r10 adcq $0,%r10 movq %r8,%rcx subq 0(%r14),%r12 sbbq 8(%r14),%r13 sbbq 16(%r14),%r8 movq %r9,%rbp sbbq 24(%r14),%r9 sbbq $0,%r10 cmovcq %rbx,%r12 cmovcq %rdx,%r13 cmovcq %rcx,%r8 cmovcq %rbp,%r9 movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lord_mulx_epilogue: ret .cfi_endproc .size ecp_nistz256_ord_mul_montx,.-ecp_nistz256_ord_mul_montx .type ecp_nistz256_ord_sqr_montx,@function .align 32 ecp_nistz256_ord_sqr_montx: .cfi_startproc .Lecp_nistz256_ord_sqr_montx: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lord_sqrx_body: movq %rdx,%rbx movq 0(%rsi),%rdx movq 8(%rsi),%r14 movq 16(%rsi),%r15 movq 24(%rsi),%r8 leaq .Lord(%rip),%rsi jmp .Loop_ord_sqrx .align 32 .Loop_ord_sqrx: mulxq %r14,%r9,%r10 mulxq %r15,%rcx,%r11 movq %rdx,%rax .byte 102,73,15,110,206 mulxq %r8,%rbp,%r12 movq %r14,%rdx addq %rcx,%r10 .byte 102,73,15,110,215 adcq %rbp,%r11 adcq $0,%r12 xorq %r13,%r13 mulxq %r15,%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq %r8,%rcx,%rbp movq %r15,%rdx adcxq %rcx,%r12 adoxq %rbp,%r13 adcq $0,%r13 mulxq %r8,%rcx,%r14 movq %rax,%rdx .byte 102,73,15,110,216 xorq %r15,%r15 adcxq %r9,%r9 adoxq %rcx,%r13 adcxq %r10,%r10 adoxq %r15,%r14 mulxq %rdx,%r8,%rbp .byte 102,72,15,126,202 adcxq %r11,%r11 adoxq %rbp,%r9 adcxq %r12,%r12 mulxq %rdx,%rcx,%rax .byte 102,72,15,126,210 adcxq %r13,%r13 adoxq %rcx,%r10 adcxq %r14,%r14 mulxq %rdx,%rcx,%rbp .byte 0x67 .byte 102,72,15,126,218 adoxq %rax,%r11 adcxq %r15,%r15 adoxq %rcx,%r12 adoxq %rbp,%r13 mulxq %rdx,%rcx,%rax adoxq %rcx,%r14 adoxq %rax,%r15 movq %r8,%rdx mulxq 32(%rsi),%rdx,%rcx xorq %rax,%rax mulxq 0(%rsi),%rcx,%rbp adcxq %rcx,%r8 adoxq %rbp,%r9 mulxq 8(%rsi),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 mulxq 16(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 24(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r8 adcxq %rax,%r8 movq %r9,%rdx mulxq 32(%rsi),%rdx,%rcx mulxq 0(%rsi),%rcx,%rbp adoxq %rcx,%r9 adcxq %rbp,%r10 mulxq 8(%rsi),%rcx,%rbp adoxq %rcx,%r10 adcxq %rbp,%r11 mulxq 16(%rsi),%rcx,%rbp adoxq %rcx,%r11 adcxq %rbp,%r8 mulxq 24(%rsi),%rcx,%rbp adoxq %rcx,%r8 adcxq %rbp,%r9 adoxq %rax,%r9 movq %r10,%rdx mulxq 32(%rsi),%rdx,%rcx mulxq 0(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 8(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r8 mulxq 16(%rsi),%rcx,%rbp adcxq %rcx,%r8 adoxq %rbp,%r9 mulxq 24(%rsi),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 adcxq %rax,%r10 movq %r11,%rdx mulxq 32(%rsi),%rdx,%rcx mulxq 0(%rsi),%rcx,%rbp adoxq %rcx,%r11 adcxq %rbp,%r8 mulxq 8(%rsi),%rcx,%rbp adoxq %rcx,%r8 adcxq %rbp,%r9 mulxq 16(%rsi),%rcx,%rbp adoxq %rcx,%r9 adcxq %rbp,%r10 mulxq 24(%rsi),%rcx,%rbp adoxq %rcx,%r10 adcxq %rbp,%r11 adoxq %rax,%r11 addq %r8,%r12 adcq %r13,%r9 movq %r12,%rdx adcq %r14,%r10 adcq %r15,%r11 movq %r9,%r14 adcq $0,%rax subq 0(%rsi),%r12 movq %r10,%r15 sbbq 8(%rsi),%r9 sbbq 16(%rsi),%r10 movq %r11,%r8 sbbq 24(%rsi),%r11 sbbq $0,%rax cmovncq %r12,%rdx cmovncq %r9,%r14 cmovncq %r10,%r15 cmovncq %r11,%r8 decq %rbx jnz .Loop_ord_sqrx movq %rdx,0(%rdi) movq %r14,8(%rdi) pxor %xmm1,%xmm1 movq %r15,16(%rdi) pxor %xmm2,%xmm2 movq %r8,24(%rdi) pxor %xmm3,%xmm3 movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lord_sqrx_epilogue: ret .cfi_endproc .size ecp_nistz256_ord_sqr_montx,.-ecp_nistz256_ord_sqr_montx .globl ecp_nistz256_mul_mont .hidden ecp_nistz256_mul_mont .type ecp_nistz256_mul_mont,@function .align 32 ecp_nistz256_mul_mont: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx .Lmul_mont: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lmul_body: cmpl $0x80100,%ecx je .Lmul_montx movq %rdx,%rbx movq 0(%rdx),%rax movq 0(%rsi),%r9 movq 8(%rsi),%r10 movq 16(%rsi),%r11 movq 24(%rsi),%r12 call __ecp_nistz256_mul_montq jmp .Lmul_mont_done .align 32 .Lmul_montx: movq %rdx,%rbx movq 0(%rdx),%rdx movq 0(%rsi),%r9 movq 8(%rsi),%r10 movq 16(%rsi),%r11 movq 24(%rsi),%r12 leaq -128(%rsi),%rsi call __ecp_nistz256_mul_montx .Lmul_mont_done: movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lmul_epilogue: ret .cfi_endproc .size ecp_nistz256_mul_mont,.-ecp_nistz256_mul_mont .type __ecp_nistz256_mul_montq,@function .align 32 __ecp_nistz256_mul_montq: .cfi_startproc movq %rax,%rbp mulq %r9 movq .Lpoly+8(%rip),%r14 movq %rax,%r8 movq %rbp,%rax movq %rdx,%r9 mulq %r10 movq .Lpoly+24(%rip),%r15 addq %rax,%r9 movq %rbp,%rax adcq $0,%rdx movq %rdx,%r10 mulq %r11 addq %rax,%r10 movq %rbp,%rax adcq $0,%rdx movq %rdx,%r11 mulq %r12 addq %rax,%r11 movq %r8,%rax adcq $0,%rdx xorq %r13,%r13 movq %rdx,%r12 movq %r8,%rbp shlq $32,%r8 mulq %r15 shrq $32,%rbp addq %r8,%r9 adcq %rbp,%r10 adcq %rax,%r11 movq 8(%rbx),%rax adcq %rdx,%r12 adcq $0,%r13 xorq %r8,%r8 movq %rax,%rbp mulq 0(%rsi) addq %rax,%r9 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 8(%rsi) addq %rcx,%r10 adcq $0,%rdx addq %rax,%r10 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 16(%rsi) addq %rcx,%r11 adcq $0,%rdx addq %rax,%r11 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 24(%rsi) addq %rcx,%r12 adcq $0,%rdx addq %rax,%r12 movq %r9,%rax adcq %rdx,%r13 adcq $0,%r8 movq %r9,%rbp shlq $32,%r9 mulq %r15 shrq $32,%rbp addq %r9,%r10 adcq %rbp,%r11 adcq %rax,%r12 movq 16(%rbx),%rax adcq %rdx,%r13 adcq $0,%r8 xorq %r9,%r9 movq %rax,%rbp mulq 0(%rsi) addq %rax,%r10 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 8(%rsi) addq %rcx,%r11 adcq $0,%rdx addq %rax,%r11 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 16(%rsi) addq %rcx,%r12 adcq $0,%rdx addq %rax,%r12 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 24(%rsi) addq %rcx,%r13 adcq $0,%rdx addq %rax,%r13 movq %r10,%rax adcq %rdx,%r8 adcq $0,%r9 movq %r10,%rbp shlq $32,%r10 mulq %r15 shrq $32,%rbp addq %r10,%r11 adcq %rbp,%r12 adcq %rax,%r13 movq 24(%rbx),%rax adcq %rdx,%r8 adcq $0,%r9 xorq %r10,%r10 movq %rax,%rbp mulq 0(%rsi) addq %rax,%r11 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 8(%rsi) addq %rcx,%r12 adcq $0,%rdx addq %rax,%r12 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 16(%rsi) addq %rcx,%r13 adcq $0,%rdx addq %rax,%r13 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 24(%rsi) addq %rcx,%r8 adcq $0,%rdx addq %rax,%r8 movq %r11,%rax adcq %rdx,%r9 adcq $0,%r10 movq %r11,%rbp shlq $32,%r11 mulq %r15 shrq $32,%rbp addq %r11,%r12 adcq %rbp,%r13 movq %r12,%rcx adcq %rax,%r8 adcq %rdx,%r9 movq %r13,%rbp adcq $0,%r10 subq $-1,%r12 movq %r8,%rbx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%rdx sbbq %r15,%r9 sbbq $0,%r10 cmovcq %rcx,%r12 cmovcq %rbp,%r13 movq %r12,0(%rdi) cmovcq %rbx,%r8 movq %r13,8(%rdi) cmovcq %rdx,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_mul_montq,.-__ecp_nistz256_mul_montq .globl ecp_nistz256_sqr_mont .hidden ecp_nistz256_sqr_mont .type ecp_nistz256_sqr_mont,@function .align 32 ecp_nistz256_sqr_mont: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lsqr_body: cmpl $0x80100,%ecx je .Lsqr_montx movq 0(%rsi),%rax movq 8(%rsi),%r14 movq 16(%rsi),%r15 movq 24(%rsi),%r8 call __ecp_nistz256_sqr_montq jmp .Lsqr_mont_done .align 32 .Lsqr_montx: movq 0(%rsi),%rdx movq 8(%rsi),%r14 movq 16(%rsi),%r15 movq 24(%rsi),%r8 leaq -128(%rsi),%rsi call __ecp_nistz256_sqr_montx .Lsqr_mont_done: movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lsqr_epilogue: ret .cfi_endproc .size ecp_nistz256_sqr_mont,.-ecp_nistz256_sqr_mont .type __ecp_nistz256_sqr_montq,@function .align 32 __ecp_nistz256_sqr_montq: .cfi_startproc movq %rax,%r13 mulq %r14 movq %rax,%r9 movq %r15,%rax movq %rdx,%r10 mulq %r13 addq %rax,%r10 movq %r8,%rax adcq $0,%rdx movq %rdx,%r11 mulq %r13 addq %rax,%r11 movq %r15,%rax adcq $0,%rdx movq %rdx,%r12 mulq %r14 addq %rax,%r11 movq %r8,%rax adcq $0,%rdx movq %rdx,%rbp mulq %r14 addq %rax,%r12 movq %r8,%rax adcq $0,%rdx addq %rbp,%r12 movq %rdx,%r13 adcq $0,%r13 mulq %r15 xorq %r15,%r15 addq %rax,%r13 movq 0(%rsi),%rax movq %rdx,%r14 adcq $0,%r14 addq %r9,%r9 adcq %r10,%r10 adcq %r11,%r11 adcq %r12,%r12 adcq %r13,%r13 adcq %r14,%r14 adcq $0,%r15 mulq %rax movq %rax,%r8 movq 8(%rsi),%rax movq %rdx,%rcx mulq %rax addq %rcx,%r9 adcq %rax,%r10 movq 16(%rsi),%rax adcq $0,%rdx movq %rdx,%rcx mulq %rax addq %rcx,%r11 adcq %rax,%r12 movq 24(%rsi),%rax adcq $0,%rdx movq %rdx,%rcx mulq %rax addq %rcx,%r13 adcq %rax,%r14 movq %r8,%rax adcq %rdx,%r15 movq .Lpoly+8(%rip),%rsi movq .Lpoly+24(%rip),%rbp movq %r8,%rcx shlq $32,%r8 mulq %rbp shrq $32,%rcx addq %r8,%r9 adcq %rcx,%r10 adcq %rax,%r11 movq %r9,%rax adcq $0,%rdx movq %r9,%rcx shlq $32,%r9 movq %rdx,%r8 mulq %rbp shrq $32,%rcx addq %r9,%r10 adcq %rcx,%r11 adcq %rax,%r8 movq %r10,%rax adcq $0,%rdx movq %r10,%rcx shlq $32,%r10 movq %rdx,%r9 mulq %rbp shrq $32,%rcx addq %r10,%r11 adcq %rcx,%r8 adcq %rax,%r9 movq %r11,%rax adcq $0,%rdx movq %r11,%rcx shlq $32,%r11 movq %rdx,%r10 mulq %rbp shrq $32,%rcx addq %r11,%r8 adcq %rcx,%r9 adcq %rax,%r10 adcq $0,%rdx xorq %r11,%r11 addq %r8,%r12 adcq %r9,%r13 movq %r12,%r8 adcq %r10,%r14 adcq %rdx,%r15 movq %r13,%r9 adcq $0,%r11 subq $-1,%r12 movq %r14,%r10 sbbq %rsi,%r13 sbbq $0,%r14 movq %r15,%rcx sbbq %rbp,%r15 sbbq $0,%r11 cmovcq %r8,%r12 cmovcq %r9,%r13 movq %r12,0(%rdi) cmovcq %r10,%r14 movq %r13,8(%rdi) cmovcq %rcx,%r15 movq %r14,16(%rdi) movq %r15,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_sqr_montq,.-__ecp_nistz256_sqr_montq .type __ecp_nistz256_mul_montx,@function .align 32 __ecp_nistz256_mul_montx: .cfi_startproc mulxq %r9,%r8,%r9 mulxq %r10,%rcx,%r10 movq $32,%r14 xorq %r13,%r13 mulxq %r11,%rbp,%r11 movq .Lpoly+24(%rip),%r15 adcq %rcx,%r9 mulxq %r12,%rcx,%r12 movq %r8,%rdx adcq %rbp,%r10 shlxq %r14,%r8,%rbp adcq %rcx,%r11 shrxq %r14,%r8,%rcx adcq $0,%r12 addq %rbp,%r9 adcq %rcx,%r10 mulxq %r15,%rcx,%rbp movq 8(%rbx),%rdx adcq %rcx,%r11 adcq %rbp,%r12 adcq $0,%r13 xorq %r8,%r8 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 24+128(%rsi),%rcx,%rbp movq %r9,%rdx adcxq %rcx,%r12 shlxq %r14,%r9,%rcx adoxq %rbp,%r13 shrxq %r14,%r9,%rbp adcxq %r8,%r13 adoxq %r8,%r8 adcq $0,%r8 addq %rcx,%r10 adcq %rbp,%r11 mulxq %r15,%rcx,%rbp movq 16(%rbx),%rdx adcq %rcx,%r12 adcq %rbp,%r13 adcq $0,%r8 xorq %r9,%r9 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 24+128(%rsi),%rcx,%rbp movq %r10,%rdx adcxq %rcx,%r13 shlxq %r14,%r10,%rcx adoxq %rbp,%r8 shrxq %r14,%r10,%rbp adcxq %r9,%r8 adoxq %r9,%r9 adcq $0,%r9 addq %rcx,%r11 adcq %rbp,%r12 mulxq %r15,%rcx,%rbp movq 24(%rbx),%rdx adcq %rcx,%r13 adcq %rbp,%r8 adcq $0,%r9 xorq %r10,%r10 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r13 adoxq %rbp,%r8 mulxq 24+128(%rsi),%rcx,%rbp movq %r11,%rdx adcxq %rcx,%r8 shlxq %r14,%r11,%rcx adoxq %rbp,%r9 shrxq %r14,%r11,%rbp adcxq %r10,%r9 adoxq %r10,%r10 adcq $0,%r10 addq %rcx,%r12 adcq %rbp,%r13 mulxq %r15,%rcx,%rbp movq %r12,%rbx movq .Lpoly+8(%rip),%r14 adcq %rcx,%r8 movq %r13,%rdx adcq %rbp,%r9 adcq $0,%r10 xorl %eax,%eax movq %r8,%rcx sbbq $-1,%r12 sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%rbp sbbq %r15,%r9 sbbq $0,%r10 cmovcq %rbx,%r12 cmovcq %rdx,%r13 movq %r12,0(%rdi) cmovcq %rcx,%r8 movq %r13,8(%rdi) cmovcq %rbp,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_mul_montx,.-__ecp_nistz256_mul_montx .type __ecp_nistz256_sqr_montx,@function .align 32 __ecp_nistz256_sqr_montx: .cfi_startproc mulxq %r14,%r9,%r10 mulxq %r15,%rcx,%r11 xorl %eax,%eax adcq %rcx,%r10 mulxq %r8,%rbp,%r12 movq %r14,%rdx adcq %rbp,%r11 adcq $0,%r12 xorq %r13,%r13 mulxq %r15,%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq %r8,%rcx,%rbp movq %r15,%rdx adcxq %rcx,%r12 adoxq %rbp,%r13 adcq $0,%r13 mulxq %r8,%rcx,%r14 movq 0+128(%rsi),%rdx xorq %r15,%r15 adcxq %r9,%r9 adoxq %rcx,%r13 adcxq %r10,%r10 adoxq %r15,%r14 mulxq %rdx,%r8,%rbp movq 8+128(%rsi),%rdx adcxq %r11,%r11 adoxq %rbp,%r9 adcxq %r12,%r12 mulxq %rdx,%rcx,%rax movq 16+128(%rsi),%rdx adcxq %r13,%r13 adoxq %rcx,%r10 adcxq %r14,%r14 .byte 0x67 mulxq %rdx,%rcx,%rbp movq 24+128(%rsi),%rdx adoxq %rax,%r11 adcxq %r15,%r15 adoxq %rcx,%r12 movq $32,%rsi adoxq %rbp,%r13 .byte 0x67,0x67 mulxq %rdx,%rcx,%rax movq .Lpoly+24(%rip),%rdx adoxq %rcx,%r14 shlxq %rsi,%r8,%rcx adoxq %rax,%r15 shrxq %rsi,%r8,%rax movq %rdx,%rbp addq %rcx,%r9 adcq %rax,%r10 mulxq %r8,%rcx,%r8 adcq %rcx,%r11 shlxq %rsi,%r9,%rcx adcq $0,%r8 shrxq %rsi,%r9,%rax addq %rcx,%r10 adcq %rax,%r11 mulxq %r9,%rcx,%r9 adcq %rcx,%r8 shlxq %rsi,%r10,%rcx adcq $0,%r9 shrxq %rsi,%r10,%rax addq %rcx,%r11 adcq %rax,%r8 mulxq %r10,%rcx,%r10 adcq %rcx,%r9 shlxq %rsi,%r11,%rcx adcq $0,%r10 shrxq %rsi,%r11,%rax addq %rcx,%r8 adcq %rax,%r9 mulxq %r11,%rcx,%r11 adcq %rcx,%r10 adcq $0,%r11 xorq %rdx,%rdx addq %r8,%r12 movq .Lpoly+8(%rip),%rsi adcq %r9,%r13 movq %r12,%r8 adcq %r10,%r14 adcq %r11,%r15 movq %r13,%r9 adcq $0,%rdx subq $-1,%r12 movq %r14,%r10 sbbq %rsi,%r13 sbbq $0,%r14 movq %r15,%r11 sbbq %rbp,%r15 sbbq $0,%rdx cmovcq %r8,%r12 cmovcq %r9,%r13 movq %r12,0(%rdi) cmovcq %r10,%r14 movq %r13,8(%rdi) cmovcq %r11,%r15 movq %r14,16(%rdi) movq %r15,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_sqr_montx,.-__ecp_nistz256_sqr_montx .globl ecp_nistz256_select_w5 .hidden ecp_nistz256_select_w5 .type ecp_nistz256_select_w5,@function .align 32 ecp_nistz256_select_w5: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rax movq 8(%rax),%rax testl $32,%eax jnz .Lavx2_select_w5 movdqa .LOne(%rip),%xmm0 movd %edx,%xmm1 pxor %xmm2,%xmm2 pxor %xmm3,%xmm3 pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 pxor %xmm6,%xmm6 pxor %xmm7,%xmm7 movdqa %xmm0,%xmm8 pshufd $0,%xmm1,%xmm1 movq $16,%rax .Lselect_loop_sse_w5: movdqa %xmm8,%xmm15 paddd %xmm0,%xmm8 pcmpeqd %xmm1,%xmm15 movdqa 0(%rsi),%xmm9 movdqa 16(%rsi),%xmm10 movdqa 32(%rsi),%xmm11 movdqa 48(%rsi),%xmm12 movdqa 64(%rsi),%xmm13 movdqa 80(%rsi),%xmm14 leaq 96(%rsi),%rsi pand %xmm15,%xmm9 pand %xmm15,%xmm10 por %xmm9,%xmm2 pand %xmm15,%xmm11 por %xmm10,%xmm3 pand %xmm15,%xmm12 por %xmm11,%xmm4 pand %xmm15,%xmm13 por %xmm12,%xmm5 pand %xmm15,%xmm14 por %xmm13,%xmm6 por %xmm14,%xmm7 decq %rax jnz .Lselect_loop_sse_w5 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqu %xmm4,32(%rdi) movdqu %xmm5,48(%rdi) movdqu %xmm6,64(%rdi) movdqu %xmm7,80(%rdi) ret .cfi_endproc .LSEH_end_ecp_nistz256_select_w5: .size ecp_nistz256_select_w5,.-ecp_nistz256_select_w5 .globl ecp_nistz256_select_w7 .hidden ecp_nistz256_select_w7 .type ecp_nistz256_select_w7,@function .align 32 ecp_nistz256_select_w7: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rax movq 8(%rax),%rax testl $32,%eax jnz .Lavx2_select_w7 movdqa .LOne(%rip),%xmm8 movd %edx,%xmm1 pxor %xmm2,%xmm2 pxor %xmm3,%xmm3 pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 movdqa %xmm8,%xmm0 pshufd $0,%xmm1,%xmm1 movq $64,%rax .Lselect_loop_sse_w7: movdqa %xmm8,%xmm15 paddd %xmm0,%xmm8 movdqa 0(%rsi),%xmm9 movdqa 16(%rsi),%xmm10 pcmpeqd %xmm1,%xmm15 movdqa 32(%rsi),%xmm11 movdqa 48(%rsi),%xmm12 leaq 64(%rsi),%rsi pand %xmm15,%xmm9 pand %xmm15,%xmm10 por %xmm9,%xmm2 pand %xmm15,%xmm11 por %xmm10,%xmm3 pand %xmm15,%xmm12 por %xmm11,%xmm4 prefetcht0 255(%rsi) por %xmm12,%xmm5 decq %rax jnz .Lselect_loop_sse_w7 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqu %xmm4,32(%rdi) movdqu %xmm5,48(%rdi) ret .cfi_endproc .LSEH_end_ecp_nistz256_select_w7: .size ecp_nistz256_select_w7,.-ecp_nistz256_select_w7 .type ecp_nistz256_avx2_select_w5,@function .align 32 ecp_nistz256_avx2_select_w5: .cfi_startproc .Lavx2_select_w5: vzeroupper vmovdqa .LTwo(%rip),%ymm0 vpxor %ymm2,%ymm2,%ymm2 vpxor %ymm3,%ymm3,%ymm3 vpxor %ymm4,%ymm4,%ymm4 vmovdqa .LOne(%rip),%ymm5 vmovdqa .LTwo(%rip),%ymm10 vmovd %edx,%xmm1 vpermd %ymm1,%ymm2,%ymm1 movq $8,%rax .Lselect_loop_avx2_w5: vmovdqa 0(%rsi),%ymm6 vmovdqa 32(%rsi),%ymm7 vmovdqa 64(%rsi),%ymm8 vmovdqa 96(%rsi),%ymm11 vmovdqa 128(%rsi),%ymm12 vmovdqa 160(%rsi),%ymm13 vpcmpeqd %ymm1,%ymm5,%ymm9 vpcmpeqd %ymm1,%ymm10,%ymm14 vpaddd %ymm0,%ymm5,%ymm5 vpaddd %ymm0,%ymm10,%ymm10 leaq 192(%rsi),%rsi vpand %ymm9,%ymm6,%ymm6 vpand %ymm9,%ymm7,%ymm7 vpand %ymm9,%ymm8,%ymm8 vpand %ymm14,%ymm11,%ymm11 vpand %ymm14,%ymm12,%ymm12 vpand %ymm14,%ymm13,%ymm13 vpxor %ymm6,%ymm2,%ymm2 vpxor %ymm7,%ymm3,%ymm3 vpxor %ymm8,%ymm4,%ymm4 vpxor %ymm11,%ymm2,%ymm2 vpxor %ymm12,%ymm3,%ymm3 vpxor %ymm13,%ymm4,%ymm4 decq %rax jnz .Lselect_loop_avx2_w5 vmovdqu %ymm2,0(%rdi) vmovdqu %ymm3,32(%rdi) vmovdqu %ymm4,64(%rdi) vzeroupper ret .cfi_endproc .LSEH_end_ecp_nistz256_avx2_select_w5: .size ecp_nistz256_avx2_select_w5,.-ecp_nistz256_avx2_select_w5 .type ecp_nistz256_avx2_select_w7,@function .align 32 ecp_nistz256_avx2_select_w7: .cfi_startproc .Lavx2_select_w7: _CET_ENDBR vzeroupper vmovdqa .LThree(%rip),%ymm0 vpxor %ymm2,%ymm2,%ymm2 vpxor %ymm3,%ymm3,%ymm3 vmovdqa .LOne(%rip),%ymm4 vmovdqa .LTwo(%rip),%ymm8 vmovdqa .LThree(%rip),%ymm12 vmovd %edx,%xmm1 vpermd %ymm1,%ymm2,%ymm1 movq $21,%rax .Lselect_loop_avx2_w7: vmovdqa 0(%rsi),%ymm5 vmovdqa 32(%rsi),%ymm6 vmovdqa 64(%rsi),%ymm9 vmovdqa 96(%rsi),%ymm10 vmovdqa 128(%rsi),%ymm13 vmovdqa 160(%rsi),%ymm14 vpcmpeqd %ymm1,%ymm4,%ymm7 vpcmpeqd %ymm1,%ymm8,%ymm11 vpcmpeqd %ymm1,%ymm12,%ymm15 vpaddd %ymm0,%ymm4,%ymm4 vpaddd %ymm0,%ymm8,%ymm8 vpaddd %ymm0,%ymm12,%ymm12 leaq 192(%rsi),%rsi vpand %ymm7,%ymm5,%ymm5 vpand %ymm7,%ymm6,%ymm6 vpand %ymm11,%ymm9,%ymm9 vpand %ymm11,%ymm10,%ymm10 vpand %ymm15,%ymm13,%ymm13 vpand %ymm15,%ymm14,%ymm14 vpxor %ymm5,%ymm2,%ymm2 vpxor %ymm6,%ymm3,%ymm3 vpxor %ymm9,%ymm2,%ymm2 vpxor %ymm10,%ymm3,%ymm3 vpxor %ymm13,%ymm2,%ymm2 vpxor %ymm14,%ymm3,%ymm3 decq %rax jnz .Lselect_loop_avx2_w7 vmovdqa 0(%rsi),%ymm5 vmovdqa 32(%rsi),%ymm6 vpcmpeqd %ymm1,%ymm4,%ymm7 vpand %ymm7,%ymm5,%ymm5 vpand %ymm7,%ymm6,%ymm6 vpxor %ymm5,%ymm2,%ymm2 vpxor %ymm6,%ymm3,%ymm3 vmovdqu %ymm2,0(%rdi) vmovdqu %ymm3,32(%rdi) vzeroupper ret .cfi_endproc .LSEH_end_ecp_nistz256_avx2_select_w7: .size ecp_nistz256_avx2_select_w7,.-ecp_nistz256_avx2_select_w7 .type __ecp_nistz256_add_toq,@function .align 32 __ecp_nistz256_add_toq: .cfi_startproc xorq %r11,%r11 addq 0(%rbx),%r12 adcq 8(%rbx),%r13 movq %r12,%rax adcq 16(%rbx),%r8 adcq 24(%rbx),%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 cmovcq %rbp,%r13 movq %r12,0(%rdi) cmovcq %rcx,%r8 movq %r13,8(%rdi) cmovcq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_add_toq,.-__ecp_nistz256_add_toq .type __ecp_nistz256_sub_fromq,@function .align 32 __ecp_nistz256_sub_fromq: .cfi_startproc subq 0(%rbx),%r12 sbbq 8(%rbx),%r13 movq %r12,%rax sbbq 16(%rbx),%r8 sbbq 24(%rbx),%r9 movq %r13,%rbp sbbq %r11,%r11 addq $-1,%r12 movq %r8,%rcx adcq %r14,%r13 adcq $0,%r8 movq %r9,%r10 adcq %r15,%r9 testq %r11,%r11 cmovzq %rax,%r12 cmovzq %rbp,%r13 movq %r12,0(%rdi) cmovzq %rcx,%r8 movq %r13,8(%rdi) cmovzq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_sub_fromq,.-__ecp_nistz256_sub_fromq .type __ecp_nistz256_subq,@function .align 32 __ecp_nistz256_subq: .cfi_startproc subq %r12,%rax sbbq %r13,%rbp movq %rax,%r12 sbbq %r8,%rcx sbbq %r9,%r10 movq %rbp,%r13 sbbq %r11,%r11 addq $-1,%rax movq %rcx,%r8 adcq %r14,%rbp adcq $0,%rcx movq %r10,%r9 adcq %r15,%r10 testq %r11,%r11 cmovnzq %rax,%r12 cmovnzq %rbp,%r13 cmovnzq %rcx,%r8 cmovnzq %r10,%r9 ret .cfi_endproc .size __ecp_nistz256_subq,.-__ecp_nistz256_subq .type __ecp_nistz256_mul_by_2q,@function .align 32 __ecp_nistz256_mul_by_2q: .cfi_startproc xorq %r11,%r11 addq %r12,%r12 adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 cmovcq %rbp,%r13 movq %r12,0(%rdi) cmovcq %rcx,%r8 movq %r13,8(%rdi) cmovcq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_mul_by_2q,.-__ecp_nistz256_mul_by_2q .globl ecp_nistz256_point_double .hidden ecp_nistz256_point_double .type ecp_nistz256_point_double,@function .align 32 ecp_nistz256_point_double: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx cmpl $0x80100,%ecx je .Lpoint_doublex pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $160+8,%rsp .cfi_adjust_cfa_offset 325+8 .Lpoint_doubleq_body: .Lpoint_double_shortcutq: movdqu 0(%rsi),%xmm0 movq %rsi,%rbx movdqu 16(%rsi),%xmm1 movq 32+0(%rsi),%r12 movq 32+8(%rsi),%r13 movq 32+16(%rsi),%r8 movq 32+24(%rsi),%r9 movq .Lpoly+8(%rip),%r14 movq .Lpoly+24(%rip),%r15 movdqa %xmm0,96(%rsp) movdqa %xmm1,96+16(%rsp) leaq 32(%rdi),%r10 leaq 64(%rdi),%r11 .byte 102,72,15,110,199 .byte 102,73,15,110,202 .byte 102,73,15,110,211 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_by_2q movq 64+0(%rsi),%rax movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 leaq 64-0(%rsi),%rsi leaq 64(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 0+0(%rsp),%rax movq 8+0(%rsp),%r14 leaq 0+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 leaq 0(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 32(%rbx),%rax movq 64+0(%rbx),%r9 movq 64+8(%rbx),%r10 movq 64+16(%rbx),%r11 movq 64+24(%rbx),%r12 leaq 64-0(%rbx),%rsi leaq 32(%rbx),%rbx .byte 102,72,15,126,215 call __ecp_nistz256_mul_montq call __ecp_nistz256_mul_by_2q movq 96+0(%rsp),%r12 movq 96+8(%rsp),%r13 leaq 64(%rsp),%rbx movq 96+16(%rsp),%r8 movq 96+24(%rsp),%r9 leaq 32(%rsp),%rdi call __ecp_nistz256_add_toq movq 96+0(%rsp),%r12 movq 96+8(%rsp),%r13 leaq 64(%rsp),%rbx movq 96+16(%rsp),%r8 movq 96+24(%rsp),%r9 leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromq movq 0+0(%rsp),%rax movq 8+0(%rsp),%r14 leaq 0+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 .byte 102,72,15,126,207 call __ecp_nistz256_sqr_montq xorq %r9,%r9 movq %r12,%rax addq $-1,%r12 movq %r13,%r10 adcq %rsi,%r13 movq %r14,%rcx adcq $0,%r14 movq %r15,%r8 adcq %rbp,%r15 adcq $0,%r9 xorq %rsi,%rsi testq $1,%rax cmovzq %rax,%r12 cmovzq %r10,%r13 cmovzq %rcx,%r14 cmovzq %r8,%r15 cmovzq %rsi,%r9 movq %r13,%rax shrq $1,%r12 shlq $63,%rax movq %r14,%r10 shrq $1,%r13 orq %rax,%r12 shlq $63,%r10 movq %r15,%rcx shrq $1,%r14 orq %r10,%r13 shlq $63,%rcx movq %r12,0(%rdi) shrq $1,%r15 movq %r13,8(%rdi) shlq $63,%r9 orq %rcx,%r14 orq %r9,%r15 movq %r14,16(%rdi) movq %r15,24(%rdi) movq 64(%rsp),%rax leaq 64(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 128(%rsp),%rdi call __ecp_nistz256_mul_by_2q leaq 32(%rsp),%rbx leaq 32(%rsp),%rdi call __ecp_nistz256_add_toq movq 96(%rsp),%rax leaq 96(%rsp),%rbx movq 0+0(%rsp),%r9 movq 8+0(%rsp),%r10 leaq 0+0(%rsp),%rsi movq 16+0(%rsp),%r11 movq 24+0(%rsp),%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 128(%rsp),%rdi call __ecp_nistz256_mul_by_2q movq 0+32(%rsp),%rax movq 8+32(%rsp),%r14 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r15 movq 24+32(%rsp),%r8 .byte 102,72,15,126,199 call __ecp_nistz256_sqr_montq leaq 128(%rsp),%rbx movq %r14,%r8 movq %r15,%r9 movq %rsi,%r14 movq %rbp,%r15 call __ecp_nistz256_sub_fromq movq 0+0(%rsp),%rax movq 0+8(%rsp),%rbp movq 0+16(%rsp),%rcx movq 0+24(%rsp),%r10 leaq 0(%rsp),%rdi call __ecp_nistz256_subq movq 32(%rsp),%rax leaq 32(%rsp),%rbx movq %r12,%r14 xorl %ecx,%ecx movq %r12,0+0(%rsp) movq %r13,%r10 movq %r13,0+8(%rsp) cmovzq %r8,%r11 movq %r8,0+16(%rsp) leaq 0-0(%rsp),%rsi cmovzq %r9,%r12 movq %r9,0+24(%rsp) movq %r14,%r9 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montq .byte 102,72,15,126,203 .byte 102,72,15,126,207 call __ecp_nistz256_sub_fromq leaq 160+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpoint_doubleq_epilogue: ret .cfi_endproc .size ecp_nistz256_point_double,.-ecp_nistz256_point_double .globl ecp_nistz256_point_add .hidden ecp_nistz256_point_add .type ecp_nistz256_point_add,@function .align 32 ecp_nistz256_point_add: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx cmpl $0x80100,%ecx je .Lpoint_addx pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $576+8,%rsp .cfi_adjust_cfa_offset 3218+8 .Lpoint_addq_body: movdqu 0(%rsi),%xmm0 movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm3 movdqu 64(%rsi),%xmm4 movdqu 80(%rsi),%xmm5 movq %rsi,%rbx movq %rdx,%rsi movdqa %xmm0,384(%rsp) movdqa %xmm1,384+16(%rsp) movdqa %xmm2,416(%rsp) movdqa %xmm3,416+16(%rsp) movdqa %xmm4,448(%rsp) movdqa %xmm5,448+16(%rsp) por %xmm4,%xmm5 movdqu 0(%rsi),%xmm0 pshufd $0xb1,%xmm5,%xmm3 movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 por %xmm3,%xmm5 movdqu 48(%rsi),%xmm3 movq 64+0(%rsi),%rax movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 movdqa %xmm0,480(%rsp) pshufd $0x1e,%xmm5,%xmm4 movdqa %xmm1,480+16(%rsp) movdqu 64(%rsi),%xmm0 movdqu 80(%rsi),%xmm1 movdqa %xmm2,512(%rsp) movdqa %xmm3,512+16(%rsp) por %xmm4,%xmm5 pxor %xmm4,%xmm4 por %xmm0,%xmm1 .byte 102,72,15,110,199 leaq 64-0(%rsi),%rsi movq %rax,544+0(%rsp) movq %r14,544+8(%rsp) movq %r15,544+16(%rsp) movq %r8,544+24(%rsp) leaq 96(%rsp),%rdi call __ecp_nistz256_sqr_montq pcmpeqd %xmm4,%xmm5 pshufd $0xb1,%xmm1,%xmm4 por %xmm1,%xmm4 pshufd $0,%xmm5,%xmm5 pshufd $0x1e,%xmm4,%xmm3 por %xmm3,%xmm4 pxor %xmm3,%xmm3 pcmpeqd %xmm3,%xmm4 pshufd $0,%xmm4,%xmm4 movq 64+0(%rbx),%rax movq 64+8(%rbx),%r14 movq 64+16(%rbx),%r15 movq 64+24(%rbx),%r8 .byte 102,72,15,110,203 leaq 64-0(%rbx),%rsi leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 544(%rsp),%rax leaq 544(%rsp),%rbx movq 0+96(%rsp),%r9 movq 8+96(%rsp),%r10 leaq 0+96(%rsp),%rsi movq 16+96(%rsp),%r11 movq 24+96(%rsp),%r12 leaq 224(%rsp),%rdi call __ecp_nistz256_mul_montq movq 448(%rsp),%rax leaq 448(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montq movq 416(%rsp),%rax leaq 416(%rsp),%rbx movq 0+224(%rsp),%r9 movq 8+224(%rsp),%r10 leaq 0+224(%rsp),%rsi movq 16+224(%rsp),%r11 movq 24+224(%rsp),%r12 leaq 224(%rsp),%rdi call __ecp_nistz256_mul_montq movq 512(%rsp),%rax leaq 512(%rsp),%rbx movq 0+256(%rsp),%r9 movq 8+256(%rsp),%r10 leaq 0+256(%rsp),%rsi movq 16+256(%rsp),%r11 movq 24+256(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 224(%rsp),%rbx leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromq orq %r13,%r12 movdqa %xmm4,%xmm2 orq %r8,%r12 orq %r9,%r12 por %xmm5,%xmm2 .byte 102,73,15,110,220 movq 384(%rsp),%rax leaq 384(%rsp),%rbx movq 0+96(%rsp),%r9 movq 8+96(%rsp),%r10 leaq 0+96(%rsp),%rsi movq 16+96(%rsp),%r11 movq 24+96(%rsp),%r12 leaq 160(%rsp),%rdi call __ecp_nistz256_mul_montq movq 480(%rsp),%rax leaq 480(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 192(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 160(%rsp),%rbx leaq 0(%rsp),%rdi call __ecp_nistz256_sub_fromq orq %r13,%r12 orq %r8,%r12 orq %r9,%r12 .byte 102,73,15,126,208 .byte 102,73,15,126,217 orq %r8,%r12 .byte 0x3e jnz .Ladd_proceedq testq %r9,%r9 jz .Ladd_doubleq .byte 102,72,15,126,199 pxor %xmm0,%xmm0 movdqu %xmm0,0(%rdi) movdqu %xmm0,16(%rdi) movdqu %xmm0,32(%rdi) movdqu %xmm0,48(%rdi) movdqu %xmm0,64(%rdi) movdqu %xmm0,80(%rdi) jmp .Ladd_doneq .align 32 .Ladd_doubleq: .byte 102,72,15,126,206 .byte 102,72,15,126,199 addq $416,%rsp .cfi_adjust_cfa_offset -416 jmp .Lpoint_double_shortcutq .cfi_adjust_cfa_offset 416 .align 32 .Ladd_proceedq: movq 0+64(%rsp),%rax movq 8+64(%rsp),%r14 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r15 movq 24+64(%rsp),%r8 leaq 96(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 448(%rsp),%rax leaq 448(%rsp),%rbx movq 0+0(%rsp),%r9 movq 8+0(%rsp),%r10 leaq 0+0(%rsp),%rsi movq 16+0(%rsp),%r11 movq 24+0(%rsp),%r12 leaq 352(%rsp),%rdi call __ecp_nistz256_mul_montq movq 0+0(%rsp),%rax movq 8+0(%rsp),%r14 leaq 0+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 544(%rsp),%rax leaq 544(%rsp),%rbx movq 0+352(%rsp),%r9 movq 8+352(%rsp),%r10 leaq 0+352(%rsp),%rsi movq 16+352(%rsp),%r11 movq 24+352(%rsp),%r12 leaq 352(%rsp),%rdi call __ecp_nistz256_mul_montq movq 0(%rsp),%rax leaq 0(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 128(%rsp),%rdi call __ecp_nistz256_mul_montq movq 160(%rsp),%rax leaq 160(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 192(%rsp),%rdi call __ecp_nistz256_mul_montq xorq %r11,%r11 addq %r12,%r12 leaq 96(%rsp),%rsi adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 movq 0(%rsi),%rax cmovcq %rbp,%r13 movq 8(%rsi),%rbp cmovcq %rcx,%r8 movq 16(%rsi),%rcx cmovcq %r10,%r9 movq 24(%rsi),%r10 call __ecp_nistz256_subq leaq 128(%rsp),%rbx leaq 288(%rsp),%rdi call __ecp_nistz256_sub_fromq movq 192+0(%rsp),%rax movq 192+8(%rsp),%rbp movq 192+16(%rsp),%rcx movq 192+24(%rsp),%r10 leaq 320(%rsp),%rdi call __ecp_nistz256_subq movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 128(%rsp),%rax leaq 128(%rsp),%rbx movq 0+224(%rsp),%r9 movq 8+224(%rsp),%r10 leaq 0+224(%rsp),%rsi movq 16+224(%rsp),%r11 movq 24+224(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montq movq 320(%rsp),%rax leaq 320(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 320(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 256(%rsp),%rbx leaq 320(%rsp),%rdi call __ecp_nistz256_sub_fromq .byte 102,72,15,126,199 movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 352(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 352+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 544(%rsp),%xmm2 pand 544+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 448(%rsp),%xmm2 pand 448+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,64(%rdi) movdqu %xmm3,80(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 288(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 288+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 480(%rsp),%xmm2 pand 480+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 384(%rsp),%xmm2 pand 384+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 320(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 320+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 512(%rsp),%xmm2 pand 512+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 416(%rsp),%xmm2 pand 416+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,32(%rdi) movdqu %xmm3,48(%rdi) .Ladd_doneq: leaq 576+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpoint_addq_epilogue: ret .cfi_endproc .size ecp_nistz256_point_add,.-ecp_nistz256_point_add .globl ecp_nistz256_point_add_affine .hidden ecp_nistz256_point_add_affine .type ecp_nistz256_point_add_affine,@function .align 32 ecp_nistz256_point_add_affine: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx cmpl $0x80100,%ecx je .Lpoint_add_affinex pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $480+8,%rsp .cfi_adjust_cfa_offset 3215+8 .Ladd_affineq_body: movdqu 0(%rsi),%xmm0 movq %rdx,%rbx movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm3 movdqu 64(%rsi),%xmm4 movdqu 80(%rsi),%xmm5 movq 64+0(%rsi),%rax movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 movdqa %xmm0,320(%rsp) movdqa %xmm1,320+16(%rsp) movdqa %xmm2,352(%rsp) movdqa %xmm3,352+16(%rsp) movdqa %xmm4,384(%rsp) movdqa %xmm5,384+16(%rsp) por %xmm4,%xmm5 movdqu 0(%rbx),%xmm0 pshufd $0xb1,%xmm5,%xmm3 movdqu 16(%rbx),%xmm1 movdqu 32(%rbx),%xmm2 por %xmm3,%xmm5 movdqu 48(%rbx),%xmm3 movdqa %xmm0,416(%rsp) pshufd $0x1e,%xmm5,%xmm4 movdqa %xmm1,416+16(%rsp) por %xmm0,%xmm1 .byte 102,72,15,110,199 movdqa %xmm2,448(%rsp) movdqa %xmm3,448+16(%rsp) por %xmm2,%xmm3 por %xmm4,%xmm5 pxor %xmm4,%xmm4 por %xmm1,%xmm3 leaq 64-0(%rsi),%rsi leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montq pcmpeqd %xmm4,%xmm5 pshufd $0xb1,%xmm3,%xmm4 movq 0(%rbx),%rax movq %r12,%r9 por %xmm3,%xmm4 pshufd $0,%xmm5,%xmm5 pshufd $0x1e,%xmm4,%xmm3 movq %r13,%r10 por %xmm3,%xmm4 pxor %xmm3,%xmm3 movq %r14,%r11 pcmpeqd %xmm3,%xmm4 pshufd $0,%xmm4,%xmm4 leaq 32-0(%rsp),%rsi movq %r15,%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 320(%rsp),%rbx leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromq movq 384(%rsp),%rax leaq 384(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montq movq 384(%rsp),%rax leaq 384(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 288(%rsp),%rdi call __ecp_nistz256_mul_montq movq 448(%rsp),%rax leaq 448(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 352(%rsp),%rbx leaq 96(%rsp),%rdi call __ecp_nistz256_sub_fromq movq 0+64(%rsp),%rax movq 8+64(%rsp),%r14 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r15 movq 24+64(%rsp),%r8 leaq 128(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 0+96(%rsp),%rax movq 8+96(%rsp),%r14 leaq 0+96(%rsp),%rsi movq 16+96(%rsp),%r15 movq 24+96(%rsp),%r8 leaq 192(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 128(%rsp),%rax leaq 128(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 160(%rsp),%rdi call __ecp_nistz256_mul_montq movq 320(%rsp),%rax leaq 320(%rsp),%rbx movq 0+128(%rsp),%r9 movq 8+128(%rsp),%r10 leaq 0+128(%rsp),%rsi movq 16+128(%rsp),%r11 movq 24+128(%rsp),%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montq xorq %r11,%r11 addq %r12,%r12 leaq 192(%rsp),%rsi adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 movq 0(%rsi),%rax cmovcq %rbp,%r13 movq 8(%rsi),%rbp cmovcq %rcx,%r8 movq 16(%rsi),%rcx cmovcq %r10,%r9 movq 24(%rsi),%r10 call __ecp_nistz256_subq leaq 160(%rsp),%rbx leaq 224(%rsp),%rdi call __ecp_nistz256_sub_fromq movq 0+0(%rsp),%rax movq 0+8(%rsp),%rbp movq 0+16(%rsp),%rcx movq 0+24(%rsp),%r10 leaq 64(%rsp),%rdi call __ecp_nistz256_subq movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 352(%rsp),%rax leaq 352(%rsp),%rbx movq 0+160(%rsp),%r9 movq 8+160(%rsp),%r10 leaq 0+160(%rsp),%rsi movq 16+160(%rsp),%r11 movq 24+160(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montq movq 96(%rsp),%rax leaq 96(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 64(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 32(%rsp),%rbx leaq 256(%rsp),%rdi call __ecp_nistz256_sub_fromq .byte 102,72,15,126,199 movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 288(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 288+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand .LONE_mont(%rip),%xmm2 pand .LONE_mont+16(%rip),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 384(%rsp),%xmm2 pand 384+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,64(%rdi) movdqu %xmm3,80(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 224(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 224+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 416(%rsp),%xmm2 pand 416+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 320(%rsp),%xmm2 pand 320+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 256(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 256+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 448(%rsp),%xmm2 pand 448+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 352(%rsp),%xmm2 pand 352+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,32(%rdi) movdqu %xmm3,48(%rdi) leaq 480+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Ladd_affineq_epilogue: ret .cfi_endproc .size ecp_nistz256_point_add_affine,.-ecp_nistz256_point_add_affine .type __ecp_nistz256_add_tox,@function .align 32 __ecp_nistz256_add_tox: .cfi_startproc xorq %r11,%r11 adcq 0(%rbx),%r12 adcq 8(%rbx),%r13 movq %r12,%rax adcq 16(%rbx),%r8 adcq 24(%rbx),%r9 movq %r13,%rbp adcq $0,%r11 xorq %r10,%r10 sbbq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 cmovcq %rbp,%r13 movq %r12,0(%rdi) cmovcq %rcx,%r8 movq %r13,8(%rdi) cmovcq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_add_tox,.-__ecp_nistz256_add_tox .type __ecp_nistz256_sub_fromx,@function .align 32 __ecp_nistz256_sub_fromx: .cfi_startproc xorq %r11,%r11 sbbq 0(%rbx),%r12 sbbq 8(%rbx),%r13 movq %r12,%rax sbbq 16(%rbx),%r8 sbbq 24(%rbx),%r9 movq %r13,%rbp sbbq $0,%r11 xorq %r10,%r10 adcq $-1,%r12 movq %r8,%rcx adcq %r14,%r13 adcq $0,%r8 movq %r9,%r10 adcq %r15,%r9 btq $0,%r11 cmovncq %rax,%r12 cmovncq %rbp,%r13 movq %r12,0(%rdi) cmovncq %rcx,%r8 movq %r13,8(%rdi) cmovncq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_sub_fromx,.-__ecp_nistz256_sub_fromx .type __ecp_nistz256_subx,@function .align 32 __ecp_nistz256_subx: .cfi_startproc xorq %r11,%r11 sbbq %r12,%rax sbbq %r13,%rbp movq %rax,%r12 sbbq %r8,%rcx sbbq %r9,%r10 movq %rbp,%r13 sbbq $0,%r11 xorq %r9,%r9 adcq $-1,%rax movq %rcx,%r8 adcq %r14,%rbp adcq $0,%rcx movq %r10,%r9 adcq %r15,%r10 btq $0,%r11 cmovcq %rax,%r12 cmovcq %rbp,%r13 cmovcq %rcx,%r8 cmovcq %r10,%r9 ret .cfi_endproc .size __ecp_nistz256_subx,.-__ecp_nistz256_subx .type __ecp_nistz256_mul_by_2x,@function .align 32 __ecp_nistz256_mul_by_2x: .cfi_startproc xorq %r11,%r11 adcq %r12,%r12 adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 xorq %r10,%r10 sbbq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 cmovcq %rbp,%r13 movq %r12,0(%rdi) cmovcq %rcx,%r8 movq %r13,8(%rdi) cmovcq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_mul_by_2x,.-__ecp_nistz256_mul_by_2x .type ecp_nistz256_point_doublex,@function .align 32 ecp_nistz256_point_doublex: .cfi_startproc .Lpoint_doublex: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $160+8,%rsp .cfi_adjust_cfa_offset 325+8 .Lpoint_doublex_body: .Lpoint_double_shortcutx: movdqu 0(%rsi),%xmm0 movq %rsi,%rbx movdqu 16(%rsi),%xmm1 movq 32+0(%rsi),%r12 movq 32+8(%rsi),%r13 movq 32+16(%rsi),%r8 movq 32+24(%rsi),%r9 movq .Lpoly+8(%rip),%r14 movq .Lpoly+24(%rip),%r15 movdqa %xmm0,96(%rsp) movdqa %xmm1,96+16(%rsp) leaq 32(%rdi),%r10 leaq 64(%rdi),%r11 .byte 102,72,15,110,199 .byte 102,73,15,110,202 .byte 102,73,15,110,211 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_by_2x movq 64+0(%rsi),%rdx movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 leaq 64-128(%rsi),%rsi leaq 64(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 0+0(%rsp),%rdx movq 8+0(%rsp),%r14 leaq -128+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 leaq 0(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 32(%rbx),%rdx movq 64+0(%rbx),%r9 movq 64+8(%rbx),%r10 movq 64+16(%rbx),%r11 movq 64+24(%rbx),%r12 leaq 64-128(%rbx),%rsi leaq 32(%rbx),%rbx .byte 102,72,15,126,215 call __ecp_nistz256_mul_montx call __ecp_nistz256_mul_by_2x movq 96+0(%rsp),%r12 movq 96+8(%rsp),%r13 leaq 64(%rsp),%rbx movq 96+16(%rsp),%r8 movq 96+24(%rsp),%r9 leaq 32(%rsp),%rdi call __ecp_nistz256_add_tox movq 96+0(%rsp),%r12 movq 96+8(%rsp),%r13 leaq 64(%rsp),%rbx movq 96+16(%rsp),%r8 movq 96+24(%rsp),%r9 leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromx movq 0+0(%rsp),%rdx movq 8+0(%rsp),%r14 leaq -128+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 .byte 102,72,15,126,207 call __ecp_nistz256_sqr_montx xorq %r9,%r9 movq %r12,%rax addq $-1,%r12 movq %r13,%r10 adcq %rsi,%r13 movq %r14,%rcx adcq $0,%r14 movq %r15,%r8 adcq %rbp,%r15 adcq $0,%r9 xorq %rsi,%rsi testq $1,%rax cmovzq %rax,%r12 cmovzq %r10,%r13 cmovzq %rcx,%r14 cmovzq %r8,%r15 cmovzq %rsi,%r9 movq %r13,%rax shrq $1,%r12 shlq $63,%rax movq %r14,%r10 shrq $1,%r13 orq %rax,%r12 shlq $63,%r10 movq %r15,%rcx shrq $1,%r14 orq %r10,%r13 shlq $63,%rcx movq %r12,0(%rdi) shrq $1,%r15 movq %r13,8(%rdi) shlq $63,%r9 orq %rcx,%r14 orq %r9,%r15 movq %r14,16(%rdi) movq %r15,24(%rdi) movq 64(%rsp),%rdx leaq 64(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 128(%rsp),%rdi call __ecp_nistz256_mul_by_2x leaq 32(%rsp),%rbx leaq 32(%rsp),%rdi call __ecp_nistz256_add_tox movq 96(%rsp),%rdx leaq 96(%rsp),%rbx movq 0+0(%rsp),%r9 movq 8+0(%rsp),%r10 leaq -128+0(%rsp),%rsi movq 16+0(%rsp),%r11 movq 24+0(%rsp),%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 128(%rsp),%rdi call __ecp_nistz256_mul_by_2x movq 0+32(%rsp),%rdx movq 8+32(%rsp),%r14 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r15 movq 24+32(%rsp),%r8 .byte 102,72,15,126,199 call __ecp_nistz256_sqr_montx leaq 128(%rsp),%rbx movq %r14,%r8 movq %r15,%r9 movq %rsi,%r14 movq %rbp,%r15 call __ecp_nistz256_sub_fromx movq 0+0(%rsp),%rax movq 0+8(%rsp),%rbp movq 0+16(%rsp),%rcx movq 0+24(%rsp),%r10 leaq 0(%rsp),%rdi call __ecp_nistz256_subx movq 32(%rsp),%rdx leaq 32(%rsp),%rbx movq %r12,%r14 xorl %ecx,%ecx movq %r12,0+0(%rsp) movq %r13,%r10 movq %r13,0+8(%rsp) cmovzq %r8,%r11 movq %r8,0+16(%rsp) leaq 0-128(%rsp),%rsi cmovzq %r9,%r12 movq %r9,0+24(%rsp) movq %r14,%r9 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montx .byte 102,72,15,126,203 .byte 102,72,15,126,207 call __ecp_nistz256_sub_fromx leaq 160+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpoint_doublex_epilogue: ret .cfi_endproc .size ecp_nistz256_point_doublex,.-ecp_nistz256_point_doublex .type ecp_nistz256_point_addx,@function .align 32 ecp_nistz256_point_addx: .cfi_startproc .Lpoint_addx: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $576+8,%rsp .cfi_adjust_cfa_offset 3218+8 .Lpoint_addx_body: movdqu 0(%rsi),%xmm0 movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm3 movdqu 64(%rsi),%xmm4 movdqu 80(%rsi),%xmm5 movq %rsi,%rbx movq %rdx,%rsi movdqa %xmm0,384(%rsp) movdqa %xmm1,384+16(%rsp) movdqa %xmm2,416(%rsp) movdqa %xmm3,416+16(%rsp) movdqa %xmm4,448(%rsp) movdqa %xmm5,448+16(%rsp) por %xmm4,%xmm5 movdqu 0(%rsi),%xmm0 pshufd $0xb1,%xmm5,%xmm3 movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 por %xmm3,%xmm5 movdqu 48(%rsi),%xmm3 movq 64+0(%rsi),%rdx movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 movdqa %xmm0,480(%rsp) pshufd $0x1e,%xmm5,%xmm4 movdqa %xmm1,480+16(%rsp) movdqu 64(%rsi),%xmm0 movdqu 80(%rsi),%xmm1 movdqa %xmm2,512(%rsp) movdqa %xmm3,512+16(%rsp) por %xmm4,%xmm5 pxor %xmm4,%xmm4 por %xmm0,%xmm1 .byte 102,72,15,110,199 leaq 64-128(%rsi),%rsi movq %rdx,544+0(%rsp) movq %r14,544+8(%rsp) movq %r15,544+16(%rsp) movq %r8,544+24(%rsp) leaq 96(%rsp),%rdi call __ecp_nistz256_sqr_montx pcmpeqd %xmm4,%xmm5 pshufd $0xb1,%xmm1,%xmm4 por %xmm1,%xmm4 pshufd $0,%xmm5,%xmm5 pshufd $0x1e,%xmm4,%xmm3 por %xmm3,%xmm4 pxor %xmm3,%xmm3 pcmpeqd %xmm3,%xmm4 pshufd $0,%xmm4,%xmm4 movq 64+0(%rbx),%rdx movq 64+8(%rbx),%r14 movq 64+16(%rbx),%r15 movq 64+24(%rbx),%r8 .byte 102,72,15,110,203 leaq 64-128(%rbx),%rsi leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 544(%rsp),%rdx leaq 544(%rsp),%rbx movq 0+96(%rsp),%r9 movq 8+96(%rsp),%r10 leaq -128+96(%rsp),%rsi movq 16+96(%rsp),%r11 movq 24+96(%rsp),%r12 leaq 224(%rsp),%rdi call __ecp_nistz256_mul_montx movq 448(%rsp),%rdx leaq 448(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montx movq 416(%rsp),%rdx leaq 416(%rsp),%rbx movq 0+224(%rsp),%r9 movq 8+224(%rsp),%r10 leaq -128+224(%rsp),%rsi movq 16+224(%rsp),%r11 movq 24+224(%rsp),%r12 leaq 224(%rsp),%rdi call __ecp_nistz256_mul_montx movq 512(%rsp),%rdx leaq 512(%rsp),%rbx movq 0+256(%rsp),%r9 movq 8+256(%rsp),%r10 leaq -128+256(%rsp),%rsi movq 16+256(%rsp),%r11 movq 24+256(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 224(%rsp),%rbx leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromx orq %r13,%r12 movdqa %xmm4,%xmm2 orq %r8,%r12 orq %r9,%r12 por %xmm5,%xmm2 .byte 102,73,15,110,220 movq 384(%rsp),%rdx leaq 384(%rsp),%rbx movq 0+96(%rsp),%r9 movq 8+96(%rsp),%r10 leaq -128+96(%rsp),%rsi movq 16+96(%rsp),%r11 movq 24+96(%rsp),%r12 leaq 160(%rsp),%rdi call __ecp_nistz256_mul_montx movq 480(%rsp),%rdx leaq 480(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 192(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 160(%rsp),%rbx leaq 0(%rsp),%rdi call __ecp_nistz256_sub_fromx orq %r13,%r12 orq %r8,%r12 orq %r9,%r12 .byte 102,73,15,126,208 .byte 102,73,15,126,217 orq %r8,%r12 .byte 0x3e jnz .Ladd_proceedx testq %r9,%r9 jz .Ladd_doublex .byte 102,72,15,126,199 pxor %xmm0,%xmm0 movdqu %xmm0,0(%rdi) movdqu %xmm0,16(%rdi) movdqu %xmm0,32(%rdi) movdqu %xmm0,48(%rdi) movdqu %xmm0,64(%rdi) movdqu %xmm0,80(%rdi) jmp .Ladd_donex .align 32 .Ladd_doublex: .byte 102,72,15,126,206 .byte 102,72,15,126,199 addq $416,%rsp .cfi_adjust_cfa_offset -416 jmp .Lpoint_double_shortcutx .cfi_adjust_cfa_offset 416 .align 32 .Ladd_proceedx: movq 0+64(%rsp),%rdx movq 8+64(%rsp),%r14 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r15 movq 24+64(%rsp),%r8 leaq 96(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 448(%rsp),%rdx leaq 448(%rsp),%rbx movq 0+0(%rsp),%r9 movq 8+0(%rsp),%r10 leaq -128+0(%rsp),%rsi movq 16+0(%rsp),%r11 movq 24+0(%rsp),%r12 leaq 352(%rsp),%rdi call __ecp_nistz256_mul_montx movq 0+0(%rsp),%rdx movq 8+0(%rsp),%r14 leaq -128+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 544(%rsp),%rdx leaq 544(%rsp),%rbx movq 0+352(%rsp),%r9 movq 8+352(%rsp),%r10 leaq -128+352(%rsp),%rsi movq 16+352(%rsp),%r11 movq 24+352(%rsp),%r12 leaq 352(%rsp),%rdi call __ecp_nistz256_mul_montx movq 0(%rsp),%rdx leaq 0(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 128(%rsp),%rdi call __ecp_nistz256_mul_montx movq 160(%rsp),%rdx leaq 160(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 192(%rsp),%rdi call __ecp_nistz256_mul_montx xorq %r11,%r11 addq %r12,%r12 leaq 96(%rsp),%rsi adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 movq 0(%rsi),%rax cmovcq %rbp,%r13 movq 8(%rsi),%rbp cmovcq %rcx,%r8 movq 16(%rsi),%rcx cmovcq %r10,%r9 movq 24(%rsi),%r10 call __ecp_nistz256_subx leaq 128(%rsp),%rbx leaq 288(%rsp),%rdi call __ecp_nistz256_sub_fromx movq 192+0(%rsp),%rax movq 192+8(%rsp),%rbp movq 192+16(%rsp),%rcx movq 192+24(%rsp),%r10 leaq 320(%rsp),%rdi call __ecp_nistz256_subx movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 128(%rsp),%rdx leaq 128(%rsp),%rbx movq 0+224(%rsp),%r9 movq 8+224(%rsp),%r10 leaq -128+224(%rsp),%rsi movq 16+224(%rsp),%r11 movq 24+224(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montx movq 320(%rsp),%rdx leaq 320(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 320(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 256(%rsp),%rbx leaq 320(%rsp),%rdi call __ecp_nistz256_sub_fromx .byte 102,72,15,126,199 movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 352(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 352+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 544(%rsp),%xmm2 pand 544+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 448(%rsp),%xmm2 pand 448+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,64(%rdi) movdqu %xmm3,80(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 288(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 288+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 480(%rsp),%xmm2 pand 480+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 384(%rsp),%xmm2 pand 384+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 320(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 320+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 512(%rsp),%xmm2 pand 512+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 416(%rsp),%xmm2 pand 416+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,32(%rdi) movdqu %xmm3,48(%rdi) .Ladd_donex: leaq 576+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpoint_addx_epilogue: ret .cfi_endproc .size ecp_nistz256_point_addx,.-ecp_nistz256_point_addx .type ecp_nistz256_point_add_affinex,@function .align 32 ecp_nistz256_point_add_affinex: .cfi_startproc .Lpoint_add_affinex: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $480+8,%rsp .cfi_adjust_cfa_offset 3215+8 .Ladd_affinex_body: movdqu 0(%rsi),%xmm0 movq %rdx,%rbx movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm3 movdqu 64(%rsi),%xmm4 movdqu 80(%rsi),%xmm5 movq 64+0(%rsi),%rdx movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 movdqa %xmm0,320(%rsp) movdqa %xmm1,320+16(%rsp) movdqa %xmm2,352(%rsp) movdqa %xmm3,352+16(%rsp) movdqa %xmm4,384(%rsp) movdqa %xmm5,384+16(%rsp) por %xmm4,%xmm5 movdqu 0(%rbx),%xmm0 pshufd $0xb1,%xmm5,%xmm3 movdqu 16(%rbx),%xmm1 movdqu 32(%rbx),%xmm2 por %xmm3,%xmm5 movdqu 48(%rbx),%xmm3 movdqa %xmm0,416(%rsp) pshufd $0x1e,%xmm5,%xmm4 movdqa %xmm1,416+16(%rsp) por %xmm0,%xmm1 .byte 102,72,15,110,199 movdqa %xmm2,448(%rsp) movdqa %xmm3,448+16(%rsp) por %xmm2,%xmm3 por %xmm4,%xmm5 pxor %xmm4,%xmm4 por %xmm1,%xmm3 leaq 64-128(%rsi),%rsi leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montx pcmpeqd %xmm4,%xmm5 pshufd $0xb1,%xmm3,%xmm4 movq 0(%rbx),%rdx movq %r12,%r9 por %xmm3,%xmm4 pshufd $0,%xmm5,%xmm5 pshufd $0x1e,%xmm4,%xmm3 movq %r13,%r10 por %xmm3,%xmm4 pxor %xmm3,%xmm3 movq %r14,%r11 pcmpeqd %xmm3,%xmm4 pshufd $0,%xmm4,%xmm4 leaq 32-128(%rsp),%rsi movq %r15,%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 320(%rsp),%rbx leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromx movq 384(%rsp),%rdx leaq 384(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montx movq 384(%rsp),%rdx leaq 384(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 288(%rsp),%rdi call __ecp_nistz256_mul_montx movq 448(%rsp),%rdx leaq 448(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 352(%rsp),%rbx leaq 96(%rsp),%rdi call __ecp_nistz256_sub_fromx movq 0+64(%rsp),%rdx movq 8+64(%rsp),%r14 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r15 movq 24+64(%rsp),%r8 leaq 128(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 0+96(%rsp),%rdx movq 8+96(%rsp),%r14 leaq -128+96(%rsp),%rsi movq 16+96(%rsp),%r15 movq 24+96(%rsp),%r8 leaq 192(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 128(%rsp),%rdx leaq 128(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 160(%rsp),%rdi call __ecp_nistz256_mul_montx movq 320(%rsp),%rdx leaq 320(%rsp),%rbx movq 0+128(%rsp),%r9 movq 8+128(%rsp),%r10 leaq -128+128(%rsp),%rsi movq 16+128(%rsp),%r11 movq 24+128(%rsp),%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montx xorq %r11,%r11 addq %r12,%r12 leaq 192(%rsp),%rsi adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 movq 0(%rsi),%rax cmovcq %rbp,%r13 movq 8(%rsi),%rbp cmovcq %rcx,%r8 movq 16(%rsi),%rcx cmovcq %r10,%r9 movq 24(%rsi),%r10 call __ecp_nistz256_subx leaq 160(%rsp),%rbx leaq 224(%rsp),%rdi call __ecp_nistz256_sub_fromx movq 0+0(%rsp),%rax movq 0+8(%rsp),%rbp movq 0+16(%rsp),%rcx movq 0+24(%rsp),%r10 leaq 64(%rsp),%rdi call __ecp_nistz256_subx movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 352(%rsp),%rdx leaq 352(%rsp),%rbx movq 0+160(%rsp),%r9 movq 8+160(%rsp),%r10 leaq -128+160(%rsp),%rsi movq 16+160(%rsp),%r11 movq 24+160(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montx movq 96(%rsp),%rdx leaq 96(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 64(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 32(%rsp),%rbx leaq 256(%rsp),%rdi call __ecp_nistz256_sub_fromx .byte 102,72,15,126,199 movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 288(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 288+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand .LONE_mont(%rip),%xmm2 pand .LONE_mont+16(%rip),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 384(%rsp),%xmm2 pand 384+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,64(%rdi) movdqu %xmm3,80(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 224(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 224+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 416(%rsp),%xmm2 pand 416+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 320(%rsp),%xmm2 pand 320+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 256(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 256+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 448(%rsp),%xmm2 pand 448+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 352(%rsp),%xmm2 pand 352+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,32(%rdi) movdqu %xmm3,48(%rdi) leaq 480+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Ladd_affinex_epilogue: ret .cfi_endproc .size ecp_nistz256_point_add_affinex,.-ecp_nistz256_point_add_affinex #endif
j4yc3-mw/Viren	190,086	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/chacha20_poly1305_x86_64-macosx.S	// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__APPLE__) .text chacha20_poly1305_constants: .section __DATA,__const .p2align 6 L$chacha20_consts: .byte 'e','x','p','a','n','d',' ','3','2','-','b','y','t','e',' ','k' .byte 'e','x','p','a','n','d',' ','3','2','-','b','y','t','e',' ','k' L$rol8: .byte 3,0,1,2, 7,4,5,6, 11,8,9,10, 15,12,13,14 .byte 3,0,1,2, 7,4,5,6, 11,8,9,10, 15,12,13,14 L$rol16: .byte 2,3,0,1, 6,7,4,5, 10,11,8,9, 14,15,12,13 .byte 2,3,0,1, 6,7,4,5, 10,11,8,9, 14,15,12,13 L$avx2_init: .long 0,0,0,0 L$sse_inc: .long 1,0,0,0 L$avx2_inc: .long 2,0,0,0,2,0,0,0 L$clamp: .quad 0x0FFFFFFC0FFFFFFF, 0x0FFFFFFC0FFFFFFC .quad 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF .p2align 4 L$and_masks: .byte 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff .text .p2align 6 poly_hash_ad_internal: xorq %r10,%r10 xorq %r11,%r11 xorq %r12,%r12 cmpq $13,%r8 jne L$hash_ad_loop L$poly_fast_tls_ad: movq (%rcx),%r10 movq 5(%rcx),%r11 shrq $24,%r11 movq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 ret L$hash_ad_loop: cmpq $16,%r8 jb L$hash_ad_tail addq 0+0(%rcx),%r10 adcq 8+0(%rcx),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rcx),%rcx subq $16,%r8 jmp L$hash_ad_loop L$hash_ad_tail: cmpq $0,%r8 je L$hash_ad_done xorq %r13,%r13 xorq %r14,%r14 xorq %r15,%r15 addq %r8,%rcx L$hash_ad_tail_loop: shldq $8,%r13,%r14 shlq $8,%r13 movzbq -1(%rcx),%r15 xorq %r15,%r13 decq %rcx decq %r8 jne L$hash_ad_tail_loop addq %r13,%r10 adcq %r14,%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$hash_ad_done: ret .globl _chacha20_poly1305_open .private_extern _chacha20_poly1305_open .p2align 6 _chacha20_poly1305_open: _CET_ENDBR pushq %rbp pushq %rbx pushq %r12 pushq %r13 pushq %r14 pushq %r15 pushq %r9 subq $288 + 0 + 32,%rsp leaq 32(%rsp),%rbp andq $-32,%rbp movq %rdx,%rbx movq %r8,0+0+32(%rbp) movq %rbx,8+0+32(%rbp) movl _OPENSSL_ia32cap_P+8(%rip),%eax andl $288,%eax xorl $288,%eax jz chacha20_poly1305_open_avx2 cmpq $128,%rbx jbe L$open_sse_128 movdqa L$chacha20_consts(%rip),%xmm0 movdqu 0(%r9),%xmm4 movdqu 16(%r9),%xmm8 movdqu 32(%r9),%xmm12 movdqa %xmm12,%xmm7 movdqa %xmm4,0+48(%rbp) movdqa %xmm8,0+64(%rbp) movdqa %xmm12,0+96(%rbp) movq $10,%r10 L$open_sse_init_rounds: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 decq %r10 jne L$open_sse_init_rounds paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 pand L$clamp(%rip),%xmm0 movdqa %xmm0,0+0(%rbp) movdqa %xmm4,0+16(%rbp) movq %r8,%r8 call poly_hash_ad_internal L$open_sse_main_loop: cmpq $256,%rbx jb L$open_sse_tail movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa %xmm0,%xmm2 movdqa %xmm4,%xmm6 movdqa %xmm8,%xmm10 movdqa %xmm0,%xmm3 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm11 movdqa 0+96(%rbp),%xmm15 paddd L$sse_inc(%rip),%xmm15 movdqa %xmm15,%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm14,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) movdqa %xmm15,0+144(%rbp) movq $4,%rcx movq %rsi,%r8 L$open_sse_main_loop_rounds: movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 leaq 16(%r8),%r8 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 .byte 102,15,58,15,255,4 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,12 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 .byte 102,15,58,15,255,12 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,4 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 decq %rcx jge L$open_sse_main_loop_rounds addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%r8),%r8 cmpq $-6,%rcx jg L$open_sse_main_loop_rounds paddd L$chacha20_consts(%rip),%xmm3 paddd 0+48(%rbp),%xmm7 paddd 0+64(%rbp),%xmm11 paddd 0+144(%rbp),%xmm15 paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqa %xmm12,0+80(%rbp) movdqu 0 + 0(%rsi),%xmm12 pxor %xmm3,%xmm12 movdqu %xmm12,0 + 0(%rdi) movdqu 16 + 0(%rsi),%xmm12 pxor %xmm7,%xmm12 movdqu %xmm12,16 + 0(%rdi) movdqu 32 + 0(%rsi),%xmm12 pxor %xmm11,%xmm12 movdqu %xmm12,32 + 0(%rdi) movdqu 48 + 0(%rsi),%xmm12 pxor %xmm15,%xmm12 movdqu %xmm12,48 + 0(%rdi) movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 64(%rdi) movdqu %xmm6,16 + 64(%rdi) movdqu %xmm10,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) movdqu 0 + 128(%rsi),%xmm3 movdqu 16 + 128(%rsi),%xmm7 movdqu 32 + 128(%rsi),%xmm11 movdqu 48 + 128(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 128(%rdi) movdqu %xmm5,16 + 128(%rdi) movdqu %xmm9,32 + 128(%rdi) movdqu %xmm15,48 + 128(%rdi) movdqu 0 + 192(%rsi),%xmm3 movdqu 16 + 192(%rsi),%xmm7 movdqu 32 + 192(%rsi),%xmm11 movdqu 48 + 192(%rsi),%xmm15 pxor %xmm3,%xmm0 pxor %xmm7,%xmm4 pxor %xmm11,%xmm8 pxor 0+80(%rbp),%xmm15 movdqu %xmm0,0 + 192(%rdi) movdqu %xmm4,16 + 192(%rdi) movdqu %xmm8,32 + 192(%rdi) movdqu %xmm15,48 + 192(%rdi) leaq 256(%rsi),%rsi leaq 256(%rdi),%rdi subq $256,%rbx jmp L$open_sse_main_loop L$open_sse_tail: testq %rbx,%rbx jz L$open_sse_finalize cmpq $192,%rbx ja L$open_sse_tail_256 cmpq $128,%rbx ja L$open_sse_tail_192 cmpq $64,%rbx ja L$open_sse_tail_128 movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa 0+96(%rbp),%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) xorq %r8,%r8 movq %rbx,%rcx cmpq $16,%rcx jb L$open_sse_tail_64_rounds L$open_sse_tail_64_rounds_and_x1hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 subq $16,%rcx L$open_sse_tail_64_rounds: addq $16,%r8 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 cmpq $16,%rcx jae L$open_sse_tail_64_rounds_and_x1hash cmpq $160,%r8 jne L$open_sse_tail_64_rounds paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 jmp L$open_sse_tail_64_dec_loop L$open_sse_tail_128: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa 0+96(%rbp),%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movq %rbx,%rcx andq $-16,%rcx xorq %r8,%r8 L$open_sse_tail_128_rounds_and_x1hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$open_sse_tail_128_rounds: addq $16,%r8 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 cmpq %rcx,%r8 jb L$open_sse_tail_128_rounds_and_x1hash cmpq $160,%r8 jne L$open_sse_tail_128_rounds paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqu 0 + 0(%rsi),%xmm3 movdqu 16 + 0(%rsi),%xmm7 movdqu 32 + 0(%rsi),%xmm11 movdqu 48 + 0(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 0(%rdi) movdqu %xmm5,16 + 0(%rdi) movdqu %xmm9,32 + 0(%rdi) movdqu %xmm15,48 + 0(%rdi) subq $64,%rbx leaq 64(%rsi),%rsi leaq 64(%rdi),%rdi jmp L$open_sse_tail_64_dec_loop L$open_sse_tail_192: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa %xmm0,%xmm2 movdqa %xmm4,%xmm6 movdqa %xmm8,%xmm10 movdqa 0+96(%rbp),%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm14,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) movq %rbx,%rcx movq $160,%r8 cmpq $160,%rcx cmovgq %r8,%rcx andq $-16,%rcx xorq %r8,%r8 L$open_sse_tail_192_rounds_and_x1hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$open_sse_tail_192_rounds: addq $16,%r8 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 cmpq %rcx,%r8 jb L$open_sse_tail_192_rounds_and_x1hash cmpq $160,%r8 jne L$open_sse_tail_192_rounds cmpq $176,%rbx jb L$open_sse_tail_192_finish addq 0+160(%rsi),%r10 adcq 8+160(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 cmpq $192,%rbx jb L$open_sse_tail_192_finish addq 0+176(%rsi),%r10 adcq 8+176(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$open_sse_tail_192_finish: paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqu 0 + 0(%rsi),%xmm3 movdqu 16 + 0(%rsi),%xmm7 movdqu 32 + 0(%rsi),%xmm11 movdqu 48 + 0(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 0(%rdi) movdqu %xmm6,16 + 0(%rdi) movdqu %xmm10,32 + 0(%rdi) movdqu %xmm15,48 + 0(%rdi) movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 64(%rdi) movdqu %xmm5,16 + 64(%rdi) movdqu %xmm9,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) subq $128,%rbx leaq 128(%rsi),%rsi leaq 128(%rdi),%rdi jmp L$open_sse_tail_64_dec_loop L$open_sse_tail_256: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa %xmm0,%xmm2 movdqa %xmm4,%xmm6 movdqa %xmm8,%xmm10 movdqa %xmm0,%xmm3 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm11 movdqa 0+96(%rbp),%xmm15 paddd L$sse_inc(%rip),%xmm15 movdqa %xmm15,%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm14,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) movdqa %xmm15,0+144(%rbp) xorq %r8,%r8 L$open_sse_tail_256_rounds_and_x1hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movdqa %xmm11,0+80(%rbp) paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm11 pslld $12,%xmm11 psrld $20,%xmm4 pxor %xmm11,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm11 pslld $7,%xmm11 psrld $25,%xmm4 pxor %xmm11,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm11 pslld $12,%xmm11 psrld $20,%xmm5 pxor %xmm11,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm11 pslld $7,%xmm11 psrld $25,%xmm5 pxor %xmm11,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm11 pslld $12,%xmm11 psrld $20,%xmm6 pxor %xmm11,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm11 pslld $7,%xmm11 psrld $25,%xmm6 pxor %xmm11,%xmm6 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 movdqa 0+80(%rbp),%xmm11 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movdqa %xmm9,0+80(%rbp) paddd %xmm7,%xmm3 pxor %xmm3,%xmm15 pshufb L$rol16(%rip),%xmm15 paddd %xmm15,%xmm11 pxor %xmm11,%xmm7 movdqa %xmm7,%xmm9 pslld $12,%xmm9 psrld $20,%xmm7 pxor %xmm9,%xmm7 paddd %xmm7,%xmm3 pxor %xmm3,%xmm15 pshufb L$rol8(%rip),%xmm15 paddd %xmm15,%xmm11 pxor %xmm11,%xmm7 movdqa %xmm7,%xmm9 pslld $7,%xmm9 psrld $25,%xmm7 pxor %xmm9,%xmm7 .byte 102,15,58,15,255,4 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,12 movdqa 0+80(%rbp),%xmm9 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx movdqa %xmm11,0+80(%rbp) paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm11 pslld $12,%xmm11 psrld $20,%xmm4 pxor %xmm11,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm11 pslld $7,%xmm11 psrld $25,%xmm4 pxor %xmm11,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm11 pslld $12,%xmm11 psrld $20,%xmm5 pxor %xmm11,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm11 pslld $7,%xmm11 psrld $25,%xmm5 pxor %xmm11,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm11 pslld $12,%xmm11 psrld $20,%xmm6 pxor %xmm11,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm11 pslld $7,%xmm11 psrld $25,%xmm6 pxor %xmm11,%xmm6 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 movdqa 0+80(%rbp),%xmm11 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 movdqa %xmm9,0+80(%rbp) paddd %xmm7,%xmm3 pxor %xmm3,%xmm15 pshufb L$rol16(%rip),%xmm15 paddd %xmm15,%xmm11 pxor %xmm11,%xmm7 movdqa %xmm7,%xmm9 pslld $12,%xmm9 psrld $20,%xmm7 pxor %xmm9,%xmm7 paddd %xmm7,%xmm3 pxor %xmm3,%xmm15 pshufb L$rol8(%rip),%xmm15 paddd %xmm15,%xmm11 pxor %xmm11,%xmm7 movdqa %xmm7,%xmm9 pslld $7,%xmm9 psrld $25,%xmm7 pxor %xmm9,%xmm7 .byte 102,15,58,15,255,12 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,4 movdqa 0+80(%rbp),%xmm9 addq $16,%r8 cmpq $160,%r8 jb L$open_sse_tail_256_rounds_and_x1hash movq %rbx,%rcx andq $-16,%rcx L$open_sse_tail_256_hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq $16,%r8 cmpq %rcx,%r8 jb L$open_sse_tail_256_hash paddd L$chacha20_consts(%rip),%xmm3 paddd 0+48(%rbp),%xmm7 paddd 0+64(%rbp),%xmm11 paddd 0+144(%rbp),%xmm15 paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqa %xmm12,0+80(%rbp) movdqu 0 + 0(%rsi),%xmm12 pxor %xmm3,%xmm12 movdqu %xmm12,0 + 0(%rdi) movdqu 16 + 0(%rsi),%xmm12 pxor %xmm7,%xmm12 movdqu %xmm12,16 + 0(%rdi) movdqu 32 + 0(%rsi),%xmm12 pxor %xmm11,%xmm12 movdqu %xmm12,32 + 0(%rdi) movdqu 48 + 0(%rsi),%xmm12 pxor %xmm15,%xmm12 movdqu %xmm12,48 + 0(%rdi) movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 64(%rdi) movdqu %xmm6,16 + 64(%rdi) movdqu %xmm10,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) movdqu 0 + 128(%rsi),%xmm3 movdqu 16 + 128(%rsi),%xmm7 movdqu 32 + 128(%rsi),%xmm11 movdqu 48 + 128(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 128(%rdi) movdqu %xmm5,16 + 128(%rdi) movdqu %xmm9,32 + 128(%rdi) movdqu %xmm15,48 + 128(%rdi) movdqa 0+80(%rbp),%xmm12 subq $192,%rbx leaq 192(%rsi),%rsi leaq 192(%rdi),%rdi L$open_sse_tail_64_dec_loop: cmpq $16,%rbx jb L$open_sse_tail_16_init subq $16,%rbx movdqu (%rsi),%xmm3 pxor %xmm3,%xmm0 movdqu %xmm0,(%rdi) leaq 16(%rsi),%rsi leaq 16(%rdi),%rdi movdqa %xmm4,%xmm0 movdqa %xmm8,%xmm4 movdqa %xmm12,%xmm8 jmp L$open_sse_tail_64_dec_loop L$open_sse_tail_16_init: movdqa %xmm0,%xmm1 L$open_sse_tail_16: testq %rbx,%rbx jz L$open_sse_finalize pxor %xmm3,%xmm3 leaq -1(%rsi,%rbx,1),%rsi movq %rbx,%r8 L$open_sse_tail_16_compose: pslldq $1,%xmm3 pinsrb $0,(%rsi),%xmm3 subq $1,%rsi subq $1,%r8 jnz L$open_sse_tail_16_compose .byte 102,73,15,126,221 pextrq $1,%xmm3,%r14 pxor %xmm1,%xmm3 L$open_sse_tail_16_extract: pextrb $0,%xmm3,(%rdi) psrldq $1,%xmm3 addq $1,%rdi subq $1,%rbx jne L$open_sse_tail_16_extract addq %r13,%r10 adcq %r14,%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$open_sse_finalize: addq 0+0+32(%rbp),%r10 adcq 8+0+32(%rbp),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 movq %r10,%r13 movq %r11,%r14 movq %r12,%r15 subq $-5,%r10 sbbq $-1,%r11 sbbq $3,%r12 cmovcq %r13,%r10 cmovcq %r14,%r11 cmovcq %r15,%r12 addq 0+0+16(%rbp),%r10 adcq 8+0+16(%rbp),%r11 addq $288 + 0 + 32,%rsp popq %r9 movq %r10,(%r9) movq %r11,8(%r9) popq %r15 popq %r14 popq %r13 popq %r12 popq %rbx popq %rbp ret L$open_sse_128: movdqu L$chacha20_consts(%rip),%xmm0 movdqa %xmm0,%xmm1 movdqa %xmm0,%xmm2 movdqu 0(%r9),%xmm4 movdqa %xmm4,%xmm5 movdqa %xmm4,%xmm6 movdqu 16(%r9),%xmm8 movdqa %xmm8,%xmm9 movdqa %xmm8,%xmm10 movdqu 32(%r9),%xmm12 movdqa %xmm12,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm11 movdqa %xmm13,%xmm15 movq $10,%r10 L$open_sse_128_rounds: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 decq %r10 jnz L$open_sse_128_rounds paddd L$chacha20_consts(%rip),%xmm0 paddd L$chacha20_consts(%rip),%xmm1 paddd L$chacha20_consts(%rip),%xmm2 paddd %xmm7,%xmm4 paddd %xmm7,%xmm5 paddd %xmm7,%xmm6 paddd %xmm11,%xmm9 paddd %xmm11,%xmm10 paddd %xmm15,%xmm13 paddd L$sse_inc(%rip),%xmm15 paddd %xmm15,%xmm14 pand L$clamp(%rip),%xmm0 movdqa %xmm0,0+0(%rbp) movdqa %xmm4,0+16(%rbp) movq %r8,%r8 call poly_hash_ad_internal L$open_sse_128_xor_hash: cmpq $16,%rbx jb L$open_sse_tail_16 subq $16,%rbx addq 0+0(%rsi),%r10 adcq 8+0(%rsi),%r11 adcq $1,%r12 movdqu 0(%rsi),%xmm3 pxor %xmm3,%xmm1 movdqu %xmm1,0(%rdi) leaq 16(%rsi),%rsi leaq 16(%rdi),%rdi movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 movdqa %xmm5,%xmm1 movdqa %xmm9,%xmm5 movdqa %xmm13,%xmm9 movdqa %xmm2,%xmm13 movdqa %xmm6,%xmm2 movdqa %xmm10,%xmm6 movdqa %xmm14,%xmm10 jmp L$open_sse_128_xor_hash .globl _chacha20_poly1305_seal .private_extern _chacha20_poly1305_seal .p2align 6 _chacha20_poly1305_seal: _CET_ENDBR pushq %rbp pushq %rbx pushq %r12 pushq %r13 pushq %r14 pushq %r15 pushq %r9 subq $288 + 0 + 32,%rsp leaq 32(%rsp),%rbp andq $-32,%rbp movq 56(%r9),%rbx addq %rdx,%rbx movq %r8,0+0+32(%rbp) movq %rbx,8+0+32(%rbp) movq %rdx,%rbx movl _OPENSSL_ia32cap_P+8(%rip),%eax andl $288,%eax xorl $288,%eax jz chacha20_poly1305_seal_avx2 cmpq $128,%rbx jbe L$seal_sse_128 movdqa L$chacha20_consts(%rip),%xmm0 movdqu 0(%r9),%xmm4 movdqu 16(%r9),%xmm8 movdqu 32(%r9),%xmm12 movdqa %xmm0,%xmm1 movdqa %xmm0,%xmm2 movdqa %xmm0,%xmm3 movdqa %xmm4,%xmm5 movdqa %xmm4,%xmm6 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm9 movdqa %xmm8,%xmm10 movdqa %xmm8,%xmm11 movdqa %xmm12,%xmm15 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,%xmm14 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,%xmm13 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm4,0+48(%rbp) movdqa %xmm8,0+64(%rbp) movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) movdqa %xmm15,0+144(%rbp) movq $10,%r10 L$seal_sse_init_rounds: movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 .byte 102,15,58,15,255,4 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,12 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 .byte 102,15,58,15,255,12 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,4 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 decq %r10 jnz L$seal_sse_init_rounds paddd L$chacha20_consts(%rip),%xmm3 paddd 0+48(%rbp),%xmm7 paddd 0+64(%rbp),%xmm11 paddd 0+144(%rbp),%xmm15 paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 pand L$clamp(%rip),%xmm3 movdqa %xmm3,0+0(%rbp) movdqa %xmm7,0+16(%rbp) movq %r8,%r8 call poly_hash_ad_internal movdqu 0 + 0(%rsi),%xmm3 movdqu 16 + 0(%rsi),%xmm7 movdqu 32 + 0(%rsi),%xmm11 movdqu 48 + 0(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 0(%rdi) movdqu %xmm6,16 + 0(%rdi) movdqu %xmm10,32 + 0(%rdi) movdqu %xmm15,48 + 0(%rdi) movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 64(%rdi) movdqu %xmm5,16 + 64(%rdi) movdqu %xmm9,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) cmpq $192,%rbx ja L$seal_sse_main_init movq $128,%rcx subq $128,%rbx leaq 128(%rsi),%rsi jmp L$seal_sse_128_tail_hash L$seal_sse_main_init: movdqu 0 + 128(%rsi),%xmm3 movdqu 16 + 128(%rsi),%xmm7 movdqu 32 + 128(%rsi),%xmm11 movdqu 48 + 128(%rsi),%xmm15 pxor %xmm3,%xmm0 pxor %xmm7,%xmm4 pxor %xmm11,%xmm8 pxor %xmm12,%xmm15 movdqu %xmm0,0 + 128(%rdi) movdqu %xmm4,16 + 128(%rdi) movdqu %xmm8,32 + 128(%rdi) movdqu %xmm15,48 + 128(%rdi) movq $192,%rcx subq $192,%rbx leaq 192(%rsi),%rsi movq $2,%rcx movq $8,%r8 cmpq $64,%rbx jbe L$seal_sse_tail_64 cmpq $128,%rbx jbe L$seal_sse_tail_128 cmpq $192,%rbx jbe L$seal_sse_tail_192 L$seal_sse_main_loop: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa %xmm0,%xmm2 movdqa %xmm4,%xmm6 movdqa %xmm8,%xmm10 movdqa %xmm0,%xmm3 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm11 movdqa 0+96(%rbp),%xmm15 paddd L$sse_inc(%rip),%xmm15 movdqa %xmm15,%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm14,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) movdqa %xmm15,0+144(%rbp) .p2align 5 L$seal_sse_main_rounds: movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 .byte 102,15,58,15,255,4 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,12 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 .byte 102,15,58,15,255,12 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,4 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 leaq 16(%rdi),%rdi decq %r8 jge L$seal_sse_main_rounds addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi decq %rcx jg L$seal_sse_main_rounds paddd L$chacha20_consts(%rip),%xmm3 paddd 0+48(%rbp),%xmm7 paddd 0+64(%rbp),%xmm11 paddd 0+144(%rbp),%xmm15 paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqa %xmm14,0+80(%rbp) movdqa %xmm14,0+80(%rbp) movdqu 0 + 0(%rsi),%xmm14 pxor %xmm3,%xmm14 movdqu %xmm14,0 + 0(%rdi) movdqu 16 + 0(%rsi),%xmm14 pxor %xmm7,%xmm14 movdqu %xmm14,16 + 0(%rdi) movdqu 32 + 0(%rsi),%xmm14 pxor %xmm11,%xmm14 movdqu %xmm14,32 + 0(%rdi) movdqu 48 + 0(%rsi),%xmm14 pxor %xmm15,%xmm14 movdqu %xmm14,48 + 0(%rdi) movdqa 0+80(%rbp),%xmm14 movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 64(%rdi) movdqu %xmm6,16 + 64(%rdi) movdqu %xmm10,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) movdqu 0 + 128(%rsi),%xmm3 movdqu 16 + 128(%rsi),%xmm7 movdqu 32 + 128(%rsi),%xmm11 movdqu 48 + 128(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 128(%rdi) movdqu %xmm5,16 + 128(%rdi) movdqu %xmm9,32 + 128(%rdi) movdqu %xmm15,48 + 128(%rdi) cmpq $256,%rbx ja L$seal_sse_main_loop_xor movq $192,%rcx subq $192,%rbx leaq 192(%rsi),%rsi jmp L$seal_sse_128_tail_hash L$seal_sse_main_loop_xor: movdqu 0 + 192(%rsi),%xmm3 movdqu 16 + 192(%rsi),%xmm7 movdqu 32 + 192(%rsi),%xmm11 movdqu 48 + 192(%rsi),%xmm15 pxor %xmm3,%xmm0 pxor %xmm7,%xmm4 pxor %xmm11,%xmm8 pxor %xmm12,%xmm15 movdqu %xmm0,0 + 192(%rdi) movdqu %xmm4,16 + 192(%rdi) movdqu %xmm8,32 + 192(%rdi) movdqu %xmm15,48 + 192(%rdi) leaq 256(%rsi),%rsi subq $256,%rbx movq $6,%rcx movq $4,%r8 cmpq $192,%rbx jg L$seal_sse_main_loop movq %rbx,%rcx testq %rbx,%rbx je L$seal_sse_128_tail_hash movq $6,%rcx cmpq $128,%rbx ja L$seal_sse_tail_192 cmpq $64,%rbx ja L$seal_sse_tail_128 L$seal_sse_tail_64: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa 0+96(%rbp),%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) L$seal_sse_tail_64_rounds_and_x2hash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_sse_tail_64_rounds_and_x1hash: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi decq %rcx jg L$seal_sse_tail_64_rounds_and_x2hash decq %r8 jge L$seal_sse_tail_64_rounds_and_x1hash paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 jmp L$seal_sse_128_tail_xor L$seal_sse_tail_128: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa 0+96(%rbp),%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) L$seal_sse_tail_128_rounds_and_x2hash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_sse_tail_128_rounds_and_x1hash: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 leaq 16(%rdi),%rdi decq %rcx jg L$seal_sse_tail_128_rounds_and_x2hash decq %r8 jge L$seal_sse_tail_128_rounds_and_x1hash paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqu 0 + 0(%rsi),%xmm3 movdqu 16 + 0(%rsi),%xmm7 movdqu 32 + 0(%rsi),%xmm11 movdqu 48 + 0(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 0(%rdi) movdqu %xmm5,16 + 0(%rdi) movdqu %xmm9,32 + 0(%rdi) movdqu %xmm15,48 + 0(%rdi) movq $64,%rcx subq $64,%rbx leaq 64(%rsi),%rsi jmp L$seal_sse_128_tail_hash L$seal_sse_tail_192: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa %xmm0,%xmm2 movdqa %xmm4,%xmm6 movdqa %xmm8,%xmm10 movdqa 0+96(%rbp),%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm14,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) L$seal_sse_tail_192_rounds_and_x2hash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_sse_tail_192_rounds_and_x1hash: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 leaq 16(%rdi),%rdi decq %rcx jg L$seal_sse_tail_192_rounds_and_x2hash decq %r8 jge L$seal_sse_tail_192_rounds_and_x1hash paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqu 0 + 0(%rsi),%xmm3 movdqu 16 + 0(%rsi),%xmm7 movdqu 32 + 0(%rsi),%xmm11 movdqu 48 + 0(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 0(%rdi) movdqu %xmm6,16 + 0(%rdi) movdqu %xmm10,32 + 0(%rdi) movdqu %xmm15,48 + 0(%rdi) movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 64(%rdi) movdqu %xmm5,16 + 64(%rdi) movdqu %xmm9,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) movq $128,%rcx subq $128,%rbx leaq 128(%rsi),%rsi L$seal_sse_128_tail_hash: cmpq $16,%rcx jb L$seal_sse_128_tail_xor addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 subq $16,%rcx leaq 16(%rdi),%rdi jmp L$seal_sse_128_tail_hash L$seal_sse_128_tail_xor: cmpq $16,%rbx jb L$seal_sse_tail_16 subq $16,%rbx movdqu 0(%rsi),%xmm3 pxor %xmm3,%xmm0 movdqu %xmm0,0(%rdi) addq 0(%rdi),%r10 adcq 8(%rdi),%r11 adcq $1,%r12 leaq 16(%rsi),%rsi leaq 16(%rdi),%rdi movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 movdqa %xmm4,%xmm0 movdqa %xmm8,%xmm4 movdqa %xmm12,%xmm8 movdqa %xmm1,%xmm12 movdqa %xmm5,%xmm1 movdqa %xmm9,%xmm5 movdqa %xmm13,%xmm9 jmp L$seal_sse_128_tail_xor L$seal_sse_tail_16: testq %rbx,%rbx jz L$process_blocks_of_extra_in movq %rbx,%r8 movq %rbx,%rcx leaq -1(%rsi,%rbx,1),%rsi pxor %xmm15,%xmm15 L$seal_sse_tail_16_compose: pslldq $1,%xmm15 pinsrb $0,(%rsi),%xmm15 leaq -1(%rsi),%rsi decq %rcx jne L$seal_sse_tail_16_compose pxor %xmm0,%xmm15 movq %rbx,%rcx movdqu %xmm15,%xmm0 L$seal_sse_tail_16_extract: pextrb $0,%xmm0,(%rdi) psrldq $1,%xmm0 addq $1,%rdi subq $1,%rcx jnz L$seal_sse_tail_16_extract movq 288 + 0 + 32(%rsp),%r9 movq 56(%r9),%r14 movq 48(%r9),%r13 testq %r14,%r14 jz L$process_partial_block movq $16,%r15 subq %rbx,%r15 cmpq %r15,%r14 jge L$load_extra_in movq %r14,%r15 L$load_extra_in: leaq -1(%r13,%r15,1),%rsi addq %r15,%r13 subq %r15,%r14 movq %r13,48(%r9) movq %r14,56(%r9) addq %r15,%r8 pxor %xmm11,%xmm11 L$load_extra_load_loop: pslldq $1,%xmm11 pinsrb $0,(%rsi),%xmm11 leaq -1(%rsi),%rsi subq $1,%r15 jnz L$load_extra_load_loop movq %rbx,%r15 L$load_extra_shift_loop: pslldq $1,%xmm11 subq $1,%r15 jnz L$load_extra_shift_loop leaq L$and_masks(%rip),%r15 shlq $4,%rbx pand -16(%r15,%rbx,1),%xmm15 por %xmm11,%xmm15 .byte 102,77,15,126,253 pextrq $1,%xmm15,%r14 addq %r13,%r10 adcq %r14,%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$process_blocks_of_extra_in: movq 288+32+0 (%rsp),%r9 movq 48(%r9),%rsi movq 56(%r9),%r8 movq %r8,%rcx shrq $4,%r8 L$process_extra_hash_loop: jz process_extra_in_trailer addq 0+0(%rsi),%r10 adcq 8+0(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rsi),%rsi subq $1,%r8 jmp L$process_extra_hash_loop process_extra_in_trailer: andq $15,%rcx movq %rcx,%rbx jz L$do_length_block leaq -1(%rsi,%rcx,1),%rsi L$process_extra_in_trailer_load: pslldq $1,%xmm15 pinsrb $0,(%rsi),%xmm15 leaq -1(%rsi),%rsi subq $1,%rcx jnz L$process_extra_in_trailer_load L$process_partial_block: leaq L$and_masks(%rip),%r15 shlq $4,%rbx pand -16(%r15,%rbx,1),%xmm15 .byte 102,77,15,126,253 pextrq $1,%xmm15,%r14 addq %r13,%r10 adcq %r14,%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$do_length_block: addq 0+0+32(%rbp),%r10 adcq 8+0+32(%rbp),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 movq %r10,%r13 movq %r11,%r14 movq %r12,%r15 subq $-5,%r10 sbbq $-1,%r11 sbbq $3,%r12 cmovcq %r13,%r10 cmovcq %r14,%r11 cmovcq %r15,%r12 addq 0+0+16(%rbp),%r10 adcq 8+0+16(%rbp),%r11 addq $288 + 0 + 32,%rsp popq %r9 movq %r10,(%r9) movq %r11,8(%r9) popq %r15 popq %r14 popq %r13 popq %r12 popq %rbx popq %rbp ret L$seal_sse_128: movdqu L$chacha20_consts(%rip),%xmm0 movdqa %xmm0,%xmm1 movdqa %xmm0,%xmm2 movdqu 0(%r9),%xmm4 movdqa %xmm4,%xmm5 movdqa %xmm4,%xmm6 movdqu 16(%r9),%xmm8 movdqa %xmm8,%xmm9 movdqa %xmm8,%xmm10 movdqu 32(%r9),%xmm14 movdqa %xmm14,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm11 movdqa %xmm12,%xmm15 movq $10,%r10 L$seal_sse_128_rounds: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 decq %r10 jnz L$seal_sse_128_rounds paddd L$chacha20_consts(%rip),%xmm0 paddd L$chacha20_consts(%rip),%xmm1 paddd L$chacha20_consts(%rip),%xmm2 paddd %xmm7,%xmm4 paddd %xmm7,%xmm5 paddd %xmm7,%xmm6 paddd %xmm11,%xmm8 paddd %xmm11,%xmm9 paddd %xmm15,%xmm12 paddd L$sse_inc(%rip),%xmm15 paddd %xmm15,%xmm13 pand L$clamp(%rip),%xmm2 movdqa %xmm2,0+0(%rbp) movdqa %xmm6,0+16(%rbp) movq %r8,%r8 call poly_hash_ad_internal jmp L$seal_sse_128_tail_xor .p2align 6 chacha20_poly1305_open_avx2: vzeroupper vmovdqa L$chacha20_consts(%rip),%ymm0 vbroadcasti128 0(%r9),%ymm4 vbroadcasti128 16(%r9),%ymm8 vbroadcasti128 32(%r9),%ymm12 vpaddd L$avx2_init(%rip),%ymm12,%ymm12 cmpq $192,%rbx jbe L$open_avx2_192 cmpq $320,%rbx jbe L$open_avx2_320 vmovdqa %ymm4,0+64(%rbp) vmovdqa %ymm8,0+96(%rbp) vmovdqa %ymm12,0+160(%rbp) movq $10,%r10 L$open_avx2_init_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 decq %r10 jne L$open_avx2_init_rounds vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vpand L$clamp(%rip),%ymm3,%ymm3 vmovdqa %ymm3,0+0(%rbp) vperm2i128 $0x13,%ymm0,%ymm4,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm4 movq %r8,%r8 call poly_hash_ad_internal xorq %rcx,%rcx L$open_avx2_init_hash: addq 0+0(%rsi,%rcx,1),%r10 adcq 8+0(%rsi,%rcx,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq $16,%rcx cmpq $64,%rcx jne L$open_avx2_init_hash vpxor 0(%rsi),%ymm0,%ymm0 vpxor 32(%rsi),%ymm4,%ymm4 vmovdqu %ymm0,0(%rdi) vmovdqu %ymm4,32(%rdi) leaq 64(%rsi),%rsi leaq 64(%rdi),%rdi subq $64,%rbx L$open_avx2_main_loop: cmpq $512,%rbx jb L$open_avx2_main_loop_done vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm15 vpaddd %ymm15,%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm15,0+256(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm12,0+160(%rbp) xorq %rcx,%rcx L$open_avx2_main_loop_rounds: addq 0+0(%rsi,%rcx,1),%r10 adcq 8+0(%rsi,%rcx,1),%r11 adcq $1,%r12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 addq %rax,%r15 adcq %rdx,%r9 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 addq 0+16(%rsi,%rcx,1),%r10 adcq 8+16(%rsi,%rcx,1),%r11 adcq $1,%r12 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 addq %rax,%r15 adcq %rdx,%r9 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 addq 0+32(%rsi,%rcx,1),%r10 adcq 8+32(%rsi,%rcx,1),%r11 adcq $1,%r12 leaq 48(%rcx),%rcx vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 addq %rax,%r15 adcq %rdx,%r9 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpalignr $4,%ymm12,%ymm12,%ymm12 cmpq $608,%rcx jne L$open_avx2_main_loop_rounds vpaddd L$chacha20_consts(%rip),%ymm3,%ymm3 vpaddd 0+64(%rbp),%ymm7,%ymm7 vpaddd 0+96(%rbp),%ymm11,%ymm11 vpaddd 0+256(%rbp),%ymm15,%ymm15 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm0,0+128(%rbp) addq 0+608(%rsi),%r10 adcq 8+608(%rsi),%r11 adcq $1,%r12 vperm2i128 $0x02,%ymm3,%ymm7,%ymm0 vperm2i128 $0x13,%ymm3,%ymm7,%ymm7 vperm2i128 $0x02,%ymm11,%ymm15,%ymm3 vperm2i128 $0x13,%ymm11,%ymm15,%ymm11 vpxor 0+0(%rsi),%ymm0,%ymm0 vpxor 32+0(%rsi),%ymm3,%ymm3 vpxor 64+0(%rsi),%ymm7,%ymm7 vpxor 96+0(%rsi),%ymm11,%ymm11 vmovdqu %ymm0,0+0(%rdi) vmovdqu %ymm3,32+0(%rdi) vmovdqu %ymm7,64+0(%rdi) vmovdqu %ymm11,96+0(%rdi) vmovdqa 0+128(%rbp),%ymm0 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm2,%ymm2 vpxor 64+128(%rsi),%ymm6,%ymm6 vpxor 96+128(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm2,32+128(%rdi) vmovdqu %ymm6,64+128(%rdi) vmovdqu %ymm10,96+128(%rdi) addq 0+608+16(%rsi),%r10 adcq 8+60*8+16(%rsi),%r11 adcq $1,%r12 vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+256(%rsi),%ymm3,%ymm3 vpxor 32+256(%rsi),%ymm1,%ymm1 vpxor 64+256(%rsi),%ymm5,%ymm5 vpxor 96+256(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+256(%rdi) vmovdqu %ymm1,32+256(%rdi) vmovdqu %ymm5,64+256(%rdi) vmovdqu %ymm9,96+256(%rdi) movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vperm2i128 $0x13,%ymm0,%ymm4,%ymm4 vperm2i128 $0x02,%ymm8,%ymm12,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm8 vpxor 0+384(%rsi),%ymm3,%ymm3 vpxor 32+384(%rsi),%ymm0,%ymm0 vpxor 64+384(%rsi),%ymm4,%ymm4 vpxor 96+384(%rsi),%ymm8,%ymm8 vmovdqu %ymm3,0+384(%rdi) vmovdqu %ymm0,32+384(%rdi) vmovdqu %ymm4,64+384(%rdi) vmovdqu %ymm8,96+384(%rdi) leaq 512(%rsi),%rsi leaq 512(%rdi),%rdi subq $512,%rbx jmp L$open_avx2_main_loop L$open_avx2_main_loop_done: testq %rbx,%rbx vzeroupper je L$open_sse_finalize cmpq $384,%rbx ja L$open_avx2_tail_512 cmpq $256,%rbx ja L$open_avx2_tail_384 cmpq $128,%rbx ja L$open_avx2_tail_256 vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) xorq %r8,%r8 movq %rbx,%rcx andq $-16,%rcx testq %rcx,%rcx je L$open_avx2_tail_128_rounds L$open_avx2_tail_128_rounds_and_x1hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$open_avx2_tail_128_rounds: addq $16,%r8 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 cmpq %rcx,%r8 jb L$open_avx2_tail_128_rounds_and_x1hash cmpq $160,%r8 jne L$open_avx2_tail_128_rounds vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 jmp L$open_avx2_tail_128_xor L$open_avx2_tail_256: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) movq %rbx,0+128(%rbp) movq %rbx,%rcx subq $128,%rcx shrq $4,%rcx movq $10,%r8 cmpq $10,%rcx cmovgq %r8,%rcx movq %rsi,%rbx xorq %r8,%r8 L$open_avx2_tail_256_rounds_and_x1hash: addq 0+0(%rbx),%r10 adcq 8+0(%rbx),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rbx),%rbx L$open_avx2_tail_256_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 incq %r8 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm6,%ymm6,%ymm6 cmpq %rcx,%r8 jb L$open_avx2_tail_256_rounds_and_x1hash cmpq $10,%r8 jne L$open_avx2_tail_256_rounds movq %rbx,%r8 subq %rsi,%rbx movq %rbx,%rcx movq 0+128(%rbp),%rbx L$open_avx2_tail_256_hash: addq $16,%rcx cmpq %rbx,%rcx jg L$open_avx2_tail_256_done addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%r8),%r8 jmp L$open_avx2_tail_256_hash L$open_avx2_tail_256_done: vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+0(%rsi),%ymm3,%ymm3 vpxor 32+0(%rsi),%ymm1,%ymm1 vpxor 64+0(%rsi),%ymm5,%ymm5 vpxor 96+0(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+0(%rdi) vmovdqu %ymm1,32+0(%rdi) vmovdqu %ymm5,64+0(%rdi) vmovdqu %ymm9,96+0(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 leaq 128(%rsi),%rsi leaq 128(%rdi),%rdi subq $128,%rbx jmp L$open_avx2_tail_128_xor L$open_avx2_tail_384: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm14,0+224(%rbp) movq %rbx,0+128(%rbp) movq %rbx,%rcx subq $256,%rcx shrq $4,%rcx addq $6,%rcx movq $10,%r8 cmpq $10,%rcx cmovgq %r8,%rcx movq %rsi,%rbx xorq %r8,%r8 L$open_avx2_tail_384_rounds_and_x2hash: addq 0+0(%rbx),%r10 adcq 8+0(%rbx),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rbx),%rbx L$open_avx2_tail_384_rounds_and_x1hash: vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm6,%ymm6,%ymm6 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 addq 0+0(%rbx),%r10 adcq 8+0(%rbx),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rbx),%rbx incq %r8 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm6,%ymm6,%ymm6 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 cmpq %rcx,%r8 jb L$open_avx2_tail_384_rounds_and_x2hash cmpq $10,%r8 jne L$open_avx2_tail_384_rounds_and_x1hash movq %rbx,%r8 subq %rsi,%rbx movq %rbx,%rcx movq 0+128(%rbp),%rbx L$open_avx2_384_tail_hash: addq $16,%rcx cmpq %rbx,%rcx jg L$open_avx2_384_tail_done addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%r8),%r8 jmp L$open_avx2_384_tail_hash L$open_avx2_384_tail_done: vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+0(%rsi),%ymm3,%ymm3 vpxor 32+0(%rsi),%ymm2,%ymm2 vpxor 64+0(%rsi),%ymm6,%ymm6 vpxor 96+0(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+0(%rdi) vmovdqu %ymm2,32+0(%rdi) vmovdqu %ymm6,64+0(%rdi) vmovdqu %ymm10,96+0(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm1,%ymm1 vpxor 64+128(%rsi),%ymm5,%ymm5 vpxor 96+128(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm1,32+128(%rdi) vmovdqu %ymm5,64+128(%rdi) vmovdqu %ymm9,96+128(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 leaq 256(%rsi),%rsi leaq 256(%rdi),%rdi subq $256,%rbx jmp L$open_avx2_tail_128_xor L$open_avx2_tail_512: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm15 vpaddd %ymm15,%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm15,0+256(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm12,0+160(%rbp) xorq %rcx,%rcx movq %rsi,%r8 L$open_avx2_tail_512_rounds_and_x2hash: addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%r8),%r8 L$open_avx2_tail_512_rounds_and_x1hash: vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 addq 0+16(%r8),%r10 adcq 8+16(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%r8),%r8 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm12,%ymm12,%ymm12 incq %rcx cmpq $4,%rcx jl L$open_avx2_tail_512_rounds_and_x2hash cmpq $10,%rcx jne L$open_avx2_tail_512_rounds_and_x1hash movq %rbx,%rcx subq $384,%rcx andq $-16,%rcx L$open_avx2_tail_512_hash: testq %rcx,%rcx je L$open_avx2_tail_512_done addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%r8),%r8 subq $16,%rcx jmp L$open_avx2_tail_512_hash L$open_avx2_tail_512_done: vpaddd L$chacha20_consts(%rip),%ymm3,%ymm3 vpaddd 0+64(%rbp),%ymm7,%ymm7 vpaddd 0+96(%rbp),%ymm11,%ymm11 vpaddd 0+256(%rbp),%ymm15,%ymm15 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm0,0+128(%rbp) vperm2i128 $0x02,%ymm3,%ymm7,%ymm0 vperm2i128 $0x13,%ymm3,%ymm7,%ymm7 vperm2i128 $0x02,%ymm11,%ymm15,%ymm3 vperm2i128 $0x13,%ymm11,%ymm15,%ymm11 vpxor 0+0(%rsi),%ymm0,%ymm0 vpxor 32+0(%rsi),%ymm3,%ymm3 vpxor 64+0(%rsi),%ymm7,%ymm7 vpxor 96+0(%rsi),%ymm11,%ymm11 vmovdqu %ymm0,0+0(%rdi) vmovdqu %ymm3,32+0(%rdi) vmovdqu %ymm7,64+0(%rdi) vmovdqu %ymm11,96+0(%rdi) vmovdqa 0+128(%rbp),%ymm0 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm2,%ymm2 vpxor 64+128(%rsi),%ymm6,%ymm6 vpxor 96+128(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm2,32+128(%rdi) vmovdqu %ymm6,64+128(%rdi) vmovdqu %ymm10,96+128(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+256(%rsi),%ymm3,%ymm3 vpxor 32+256(%rsi),%ymm1,%ymm1 vpxor 64+256(%rsi),%ymm5,%ymm5 vpxor 96+256(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+256(%rdi) vmovdqu %ymm1,32+256(%rdi) vmovdqu %ymm5,64+256(%rdi) vmovdqu %ymm9,96+256(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 leaq 384(%rsi),%rsi leaq 384(%rdi),%rdi subq $384,%rbx L$open_avx2_tail_128_xor: cmpq $32,%rbx jb L$open_avx2_tail_32_xor subq $32,%rbx vpxor (%rsi),%ymm0,%ymm0 vmovdqu %ymm0,(%rdi) leaq 32(%rsi),%rsi leaq 32(%rdi),%rdi vmovdqa %ymm4,%ymm0 vmovdqa %ymm8,%ymm4 vmovdqa %ymm12,%ymm8 jmp L$open_avx2_tail_128_xor L$open_avx2_tail_32_xor: cmpq $16,%rbx vmovdqa %xmm0,%xmm1 jb L$open_avx2_exit subq $16,%rbx vpxor (%rsi),%xmm0,%xmm1 vmovdqu %xmm1,(%rdi) leaq 16(%rsi),%rsi leaq 16(%rdi),%rdi vperm2i128 $0x11,%ymm0,%ymm0,%ymm0 vmovdqa %xmm0,%xmm1 L$open_avx2_exit: vzeroupper jmp L$open_sse_tail_16 L$open_avx2_192: vmovdqa %ymm0,%ymm1 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm5 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm9 vmovdqa %ymm8,%ymm10 vpaddd L$avx2_inc(%rip),%ymm12,%ymm13 vmovdqa %ymm12,%ymm11 vmovdqa %ymm13,%ymm15 movq $10,%r10 L$open_avx2_192_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 decq %r10 jne L$open_avx2_192_rounds vpaddd %ymm2,%ymm0,%ymm0 vpaddd %ymm2,%ymm1,%ymm1 vpaddd %ymm6,%ymm4,%ymm4 vpaddd %ymm6,%ymm5,%ymm5 vpaddd %ymm10,%ymm8,%ymm8 vpaddd %ymm10,%ymm9,%ymm9 vpaddd %ymm11,%ymm12,%ymm12 vpaddd %ymm15,%ymm13,%ymm13 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vpand L$clamp(%rip),%ymm3,%ymm3 vmovdqa %ymm3,0+0(%rbp) vperm2i128 $0x13,%ymm0,%ymm4,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm4 vperm2i128 $0x02,%ymm1,%ymm5,%ymm8 vperm2i128 $0x02,%ymm9,%ymm13,%ymm12 vperm2i128 $0x13,%ymm1,%ymm5,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm5 L$open_avx2_short: movq %r8,%r8 call poly_hash_ad_internal L$open_avx2_short_hash_and_xor_loop: cmpq $32,%rbx jb L$open_avx2_short_tail_32 subq $32,%rbx addq 0+0(%rsi),%r10 adcq 8+0(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq 0+16(%rsi),%r10 adcq 8+16(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor (%rsi),%ymm0,%ymm0 vmovdqu %ymm0,(%rdi) leaq 32(%rsi),%rsi leaq 32(%rdi),%rdi vmovdqa %ymm4,%ymm0 vmovdqa %ymm8,%ymm4 vmovdqa %ymm12,%ymm8 vmovdqa %ymm1,%ymm12 vmovdqa %ymm5,%ymm1 vmovdqa %ymm9,%ymm5 vmovdqa %ymm13,%ymm9 vmovdqa %ymm2,%ymm13 vmovdqa %ymm6,%ymm2 jmp L$open_avx2_short_hash_and_xor_loop L$open_avx2_short_tail_32: cmpq $16,%rbx vmovdqa %xmm0,%xmm1 jb L$open_avx2_short_tail_32_exit subq $16,%rbx addq 0+0(%rsi),%r10 adcq 8+0(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor (%rsi),%xmm0,%xmm3 vmovdqu %xmm3,(%rdi) leaq 16(%rsi),%rsi leaq 16(%rdi),%rdi vextracti128 $1,%ymm0,%xmm1 L$open_avx2_short_tail_32_exit: vzeroupper jmp L$open_sse_tail_16 L$open_avx2_320: vmovdqa %ymm0,%ymm1 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm5 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm9 vmovdqa %ymm8,%ymm10 vpaddd L$avx2_inc(%rip),%ymm12,%ymm13 vpaddd L$avx2_inc(%rip),%ymm13,%ymm14 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm14,0+224(%rbp) movq $10,%r10 L$open_avx2_320_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm6,%ymm6,%ymm6 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm6,%ymm6,%ymm6 decq %r10 jne L$open_avx2_320_rounds vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd %ymm7,%ymm4,%ymm4 vpaddd %ymm7,%ymm5,%ymm5 vpaddd %ymm7,%ymm6,%ymm6 vpaddd %ymm11,%ymm8,%ymm8 vpaddd %ymm11,%ymm9,%ymm9 vpaddd %ymm11,%ymm10,%ymm10 vpaddd 0+160(%rbp),%ymm12,%ymm12 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd 0+224(%rbp),%ymm14,%ymm14 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vpand L$clamp(%rip),%ymm3,%ymm3 vmovdqa %ymm3,0+0(%rbp) vperm2i128 $0x13,%ymm0,%ymm4,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm4 vperm2i128 $0x02,%ymm1,%ymm5,%ymm8 vperm2i128 $0x02,%ymm9,%ymm13,%ymm12 vperm2i128 $0x13,%ymm1,%ymm5,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm5 vperm2i128 $0x02,%ymm2,%ymm6,%ymm9 vperm2i128 $0x02,%ymm10,%ymm14,%ymm13 vperm2i128 $0x13,%ymm2,%ymm6,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm6 jmp L$open_avx2_short .p2align 6 chacha20_poly1305_seal_avx2: vzeroupper vmovdqa L$chacha20_consts(%rip),%ymm0 vbroadcasti128 0(%r9),%ymm4 vbroadcasti128 16(%r9),%ymm8 vbroadcasti128 32(%r9),%ymm12 vpaddd L$avx2_init(%rip),%ymm12,%ymm12 cmpq $192,%rbx jbe L$seal_avx2_192 cmpq $320,%rbx jbe L$seal_avx2_320 vmovdqa %ymm0,%ymm1 vmovdqa %ymm0,%ymm2 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm5 vmovdqa %ymm4,%ymm6 vmovdqa %ymm4,%ymm7 vmovdqa %ymm4,0+64(%rbp) vmovdqa %ymm8,%ymm9 vmovdqa %ymm8,%ymm10 vmovdqa %ymm8,%ymm11 vmovdqa %ymm8,0+96(%rbp) vmovdqa %ymm12,%ymm15 vpaddd L$avx2_inc(%rip),%ymm15,%ymm14 vpaddd L$avx2_inc(%rip),%ymm14,%ymm13 vpaddd L$avx2_inc(%rip),%ymm13,%ymm12 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm15,0+256(%rbp) movq $10,%r10 L$seal_avx2_init_rounds: vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm12,%ymm12,%ymm12 decq %r10 jnz L$seal_avx2_init_rounds vpaddd L$chacha20_consts(%rip),%ymm3,%ymm3 vpaddd 0+64(%rbp),%ymm7,%ymm7 vpaddd 0+96(%rbp),%ymm11,%ymm11 vpaddd 0+256(%rbp),%ymm15,%ymm15 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x13,%ymm11,%ymm15,%ymm11 vperm2i128 $0x02,%ymm3,%ymm7,%ymm15 vperm2i128 $0x13,%ymm3,%ymm7,%ymm3 vpand L$clamp(%rip),%ymm15,%ymm15 vmovdqa %ymm15,0+0(%rbp) movq %r8,%r8 call poly_hash_ad_internal vpxor 0(%rsi),%ymm3,%ymm3 vpxor 32(%rsi),%ymm11,%ymm11 vmovdqu %ymm3,0(%rdi) vmovdqu %ymm11,32(%rdi) vperm2i128 $0x02,%ymm2,%ymm6,%ymm15 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+64(%rsi),%ymm15,%ymm15 vpxor 32+64(%rsi),%ymm2,%ymm2 vpxor 64+64(%rsi),%ymm6,%ymm6 vpxor 96+64(%rsi),%ymm10,%ymm10 vmovdqu %ymm15,0+64(%rdi) vmovdqu %ymm2,32+64(%rdi) vmovdqu %ymm6,64+64(%rdi) vmovdqu %ymm10,96+64(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm15 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+192(%rsi),%ymm15,%ymm15 vpxor 32+192(%rsi),%ymm1,%ymm1 vpxor 64+192(%rsi),%ymm5,%ymm5 vpxor 96+192(%rsi),%ymm9,%ymm9 vmovdqu %ymm15,0+192(%rdi) vmovdqu %ymm1,32+192(%rdi) vmovdqu %ymm5,64+192(%rdi) vmovdqu %ymm9,96+192(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm15 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm15,%ymm8 leaq 320(%rsi),%rsi subq $320,%rbx movq $320,%rcx cmpq $128,%rbx jbe L$seal_avx2_short_hash_remainder vpxor 0(%rsi),%ymm0,%ymm0 vpxor 32(%rsi),%ymm4,%ymm4 vpxor 64(%rsi),%ymm8,%ymm8 vpxor 96(%rsi),%ymm12,%ymm12 vmovdqu %ymm0,320(%rdi) vmovdqu %ymm4,352(%rdi) vmovdqu %ymm8,384(%rdi) vmovdqu %ymm12,416(%rdi) leaq 128(%rsi),%rsi subq $128,%rbx movq $8,%rcx movq $2,%r8 cmpq $128,%rbx jbe L$seal_avx2_tail_128 cmpq $256,%rbx jbe L$seal_avx2_tail_256 cmpq $384,%rbx jbe L$seal_avx2_tail_384 cmpq $512,%rbx jbe L$seal_avx2_tail_512 vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm15 vpaddd %ymm15,%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm15,0+256(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 subq $16,%rdi movq $9,%rcx jmp L$seal_avx2_main_loop_rounds_entry .p2align 5 L$seal_avx2_main_loop: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm15 vpaddd %ymm15,%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm15,0+256(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm12,0+160(%rbp) movq $10,%rcx .p2align 5 L$seal_avx2_main_loop_rounds: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 addq %rax,%r15 adcq %rdx,%r9 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$seal_avx2_main_loop_rounds_entry: vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 addq %rax,%r15 adcq %rdx,%r9 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 addq 0+32(%rdi),%r10 adcq 8+32(%rdi),%r11 adcq $1,%r12 leaq 48(%rdi),%rdi vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 addq %rax,%r15 adcq %rdx,%r9 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpalignr $4,%ymm12,%ymm12,%ymm12 decq %rcx jne L$seal_avx2_main_loop_rounds vpaddd L$chacha20_consts(%rip),%ymm3,%ymm3 vpaddd 0+64(%rbp),%ymm7,%ymm7 vpaddd 0+96(%rbp),%ymm11,%ymm11 vpaddd 0+256(%rbp),%ymm15,%ymm15 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm0,0+128(%rbp) addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi vperm2i128 $0x02,%ymm3,%ymm7,%ymm0 vperm2i128 $0x13,%ymm3,%ymm7,%ymm7 vperm2i128 $0x02,%ymm11,%ymm15,%ymm3 vperm2i128 $0x13,%ymm11,%ymm15,%ymm11 vpxor 0+0(%rsi),%ymm0,%ymm0 vpxor 32+0(%rsi),%ymm3,%ymm3 vpxor 64+0(%rsi),%ymm7,%ymm7 vpxor 96+0(%rsi),%ymm11,%ymm11 vmovdqu %ymm0,0+0(%rdi) vmovdqu %ymm3,32+0(%rdi) vmovdqu %ymm7,64+0(%rdi) vmovdqu %ymm11,96+0(%rdi) vmovdqa 0+128(%rbp),%ymm0 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm2,%ymm2 vpxor 64+128(%rsi),%ymm6,%ymm6 vpxor 96+128(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm2,32+128(%rdi) vmovdqu %ymm6,64+128(%rdi) vmovdqu %ymm10,96+128(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+256(%rsi),%ymm3,%ymm3 vpxor 32+256(%rsi),%ymm1,%ymm1 vpxor 64+256(%rsi),%ymm5,%ymm5 vpxor 96+256(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+256(%rdi) vmovdqu %ymm1,32+256(%rdi) vmovdqu %ymm5,64+256(%rdi) vmovdqu %ymm9,96+256(%rdi) vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vperm2i128 $0x13,%ymm0,%ymm4,%ymm4 vperm2i128 $0x02,%ymm8,%ymm12,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm8 vpxor 0+384(%rsi),%ymm3,%ymm3 vpxor 32+384(%rsi),%ymm0,%ymm0 vpxor 64+384(%rsi),%ymm4,%ymm4 vpxor 96+384(%rsi),%ymm8,%ymm8 vmovdqu %ymm3,0+384(%rdi) vmovdqu %ymm0,32+384(%rdi) vmovdqu %ymm4,64+384(%rdi) vmovdqu %ymm8,96+384(%rdi) leaq 512(%rsi),%rsi subq $512,%rbx cmpq $512,%rbx jg L$seal_avx2_main_loop addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi movq $10,%rcx xorq %r8,%r8 cmpq $384,%rbx ja L$seal_avx2_tail_512 cmpq $256,%rbx ja L$seal_avx2_tail_384 cmpq $128,%rbx ja L$seal_avx2_tail_256 L$seal_avx2_tail_128: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) L$seal_avx2_tail_128_rounds_and_3xhash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_avx2_tail_128_rounds_and_2xhash: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi decq %rcx jg L$seal_avx2_tail_128_rounds_and_3xhash decq %r8 jge L$seal_avx2_tail_128_rounds_and_2xhash vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 jmp L$seal_avx2_short_loop L$seal_avx2_tail_256: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) L$seal_avx2_tail_256_rounds_and_3xhash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_avx2_tail_256_rounds_and_2xhash: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi decq %rcx jg L$seal_avx2_tail_256_rounds_and_3xhash decq %r8 jge L$seal_avx2_tail_256_rounds_and_2xhash vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+0(%rsi),%ymm3,%ymm3 vpxor 32+0(%rsi),%ymm1,%ymm1 vpxor 64+0(%rsi),%ymm5,%ymm5 vpxor 96+0(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+0(%rdi) vmovdqu %ymm1,32+0(%rdi) vmovdqu %ymm5,64+0(%rdi) vmovdqu %ymm9,96+0(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 movq $128,%rcx leaq 128(%rsi),%rsi subq $128,%rbx jmp L$seal_avx2_short_hash_remainder L$seal_avx2_tail_384: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm14,0+224(%rbp) L$seal_avx2_tail_384_rounds_and_3xhash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_avx2_tail_384_rounds_and_2xhash: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm6,%ymm6,%ymm6 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm6,%ymm6,%ymm6 leaq 32(%rdi),%rdi decq %rcx jg L$seal_avx2_tail_384_rounds_and_3xhash decq %r8 jge L$seal_avx2_tail_384_rounds_and_2xhash vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+0(%rsi),%ymm3,%ymm3 vpxor 32+0(%rsi),%ymm2,%ymm2 vpxor 64+0(%rsi),%ymm6,%ymm6 vpxor 96+0(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+0(%rdi) vmovdqu %ymm2,32+0(%rdi) vmovdqu %ymm6,64+0(%rdi) vmovdqu %ymm10,96+0(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm1,%ymm1 vpxor 64+128(%rsi),%ymm5,%ymm5 vpxor 96+128(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm1,32+128(%rdi) vmovdqu %ymm5,64+128(%rdi) vmovdqu %ymm9,96+128(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 movq $256,%rcx leaq 256(%rsi),%rsi subq $256,%rbx jmp L$seal_avx2_short_hash_remainder L$seal_avx2_tail_512: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm15 vpaddd %ymm15,%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm15,0+256(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm12,0+160(%rbp) L$seal_avx2_tail_512_rounds_and_3xhash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_avx2_tail_512_rounds_and_2xhash: vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 addq %rax,%r15 adcq %rdx,%r9 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm12,%ymm12,%ymm12 addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi decq %rcx jg L$seal_avx2_tail_512_rounds_and_3xhash decq %r8 jge L$seal_avx2_tail_512_rounds_and_2xhash vpaddd L$chacha20_consts(%rip),%ymm3,%ymm3 vpaddd 0+64(%rbp),%ymm7,%ymm7 vpaddd 0+96(%rbp),%ymm11,%ymm11 vpaddd 0+256(%rbp),%ymm15,%ymm15 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm0,0+128(%rbp) vperm2i128 $0x02,%ymm3,%ymm7,%ymm0 vperm2i128 $0x13,%ymm3,%ymm7,%ymm7 vperm2i128 $0x02,%ymm11,%ymm15,%ymm3 vperm2i128 $0x13,%ymm11,%ymm15,%ymm11 vpxor 0+0(%rsi),%ymm0,%ymm0 vpxor 32+0(%rsi),%ymm3,%ymm3 vpxor 64+0(%rsi),%ymm7,%ymm7 vpxor 96+0(%rsi),%ymm11,%ymm11 vmovdqu %ymm0,0+0(%rdi) vmovdqu %ymm3,32+0(%rdi) vmovdqu %ymm7,64+0(%rdi) vmovdqu %ymm11,96+0(%rdi) vmovdqa 0+128(%rbp),%ymm0 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm2,%ymm2 vpxor 64+128(%rsi),%ymm6,%ymm6 vpxor 96+128(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm2,32+128(%rdi) vmovdqu %ymm6,64+128(%rdi) vmovdqu %ymm10,96+128(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+256(%rsi),%ymm3,%ymm3 vpxor 32+256(%rsi),%ymm1,%ymm1 vpxor 64+256(%rsi),%ymm5,%ymm5 vpxor 96+256(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+256(%rdi) vmovdqu %ymm1,32+256(%rdi) vmovdqu %ymm5,64+256(%rdi) vmovdqu %ymm9,96+256(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 movq $384,%rcx leaq 384(%rsi),%rsi subq $384,%rbx jmp L$seal_avx2_short_hash_remainder L$seal_avx2_320: vmovdqa %ymm0,%ymm1 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm5 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm9 vmovdqa %ymm8,%ymm10 vpaddd L$avx2_inc(%rip),%ymm12,%ymm13 vpaddd L$avx2_inc(%rip),%ymm13,%ymm14 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm14,0+224(%rbp) movq $10,%r10 L$seal_avx2_320_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm6,%ymm6,%ymm6 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm6,%ymm6,%ymm6 decq %r10 jne L$seal_avx2_320_rounds vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd %ymm7,%ymm4,%ymm4 vpaddd %ymm7,%ymm5,%ymm5 vpaddd %ymm7,%ymm6,%ymm6 vpaddd %ymm11,%ymm8,%ymm8 vpaddd %ymm11,%ymm9,%ymm9 vpaddd %ymm11,%ymm10,%ymm10 vpaddd 0+160(%rbp),%ymm12,%ymm12 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd 0+224(%rbp),%ymm14,%ymm14 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vpand L$clamp(%rip),%ymm3,%ymm3 vmovdqa %ymm3,0+0(%rbp) vperm2i128 $0x13,%ymm0,%ymm4,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm4 vperm2i128 $0x02,%ymm1,%ymm5,%ymm8 vperm2i128 $0x02,%ymm9,%ymm13,%ymm12 vperm2i128 $0x13,%ymm1,%ymm5,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm5 vperm2i128 $0x02,%ymm2,%ymm6,%ymm9 vperm2i128 $0x02,%ymm10,%ymm14,%ymm13 vperm2i128 $0x13,%ymm2,%ymm6,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm6 jmp L$seal_avx2_short L$seal_avx2_192: vmovdqa %ymm0,%ymm1 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm5 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm9 vmovdqa %ymm8,%ymm10 vpaddd L$avx2_inc(%rip),%ymm12,%ymm13 vmovdqa %ymm12,%ymm11 vmovdqa %ymm13,%ymm15 movq $10,%r10 L$seal_avx2_192_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 decq %r10 jne L$seal_avx2_192_rounds vpaddd %ymm2,%ymm0,%ymm0 vpaddd %ymm2,%ymm1,%ymm1 vpaddd %ymm6,%ymm4,%ymm4 vpaddd %ymm6,%ymm5,%ymm5 vpaddd %ymm10,%ymm8,%ymm8 vpaddd %ymm10,%ymm9,%ymm9 vpaddd %ymm11,%ymm12,%ymm12 vpaddd %ymm15,%ymm13,%ymm13 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vpand L$clamp(%rip),%ymm3,%ymm3 vmovdqa %ymm3,0+0(%rbp) vperm2i128 $0x13,%ymm0,%ymm4,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm4 vperm2i128 $0x02,%ymm1,%ymm5,%ymm8 vperm2i128 $0x02,%ymm9,%ymm13,%ymm12 vperm2i128 $0x13,%ymm1,%ymm5,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm5 L$seal_avx2_short: movq %r8,%r8 call poly_hash_ad_internal xorq %rcx,%rcx L$seal_avx2_short_hash_remainder: cmpq $16,%rcx jb L$seal_avx2_short_loop addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 subq $16,%rcx addq $16,%rdi jmp L$seal_avx2_short_hash_remainder L$seal_avx2_short_loop: cmpq $32,%rbx jb L$seal_avx2_short_tail subq $32,%rbx vpxor (%rsi),%ymm0,%ymm0 vmovdqu %ymm0,(%rdi) leaq 32(%rsi),%rsi addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi vmovdqa %ymm4,%ymm0 vmovdqa %ymm8,%ymm4 vmovdqa %ymm12,%ymm8 vmovdqa %ymm1,%ymm12 vmovdqa %ymm5,%ymm1 vmovdqa %ymm9,%ymm5 vmovdqa %ymm13,%ymm9 vmovdqa %ymm2,%ymm13 vmovdqa %ymm6,%ymm2 jmp L$seal_avx2_short_loop L$seal_avx2_short_tail: cmpq $16,%rbx jb L$seal_avx2_exit subq $16,%rbx vpxor (%rsi),%xmm0,%xmm3 vmovdqu %xmm3,(%rdi) leaq 16(%rsi),%rsi addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi vextracti128 $1,%ymm0,%xmm0 L$seal_avx2_exit: vzeroupper jmp L$seal_sse_tail_16 #endif
j4yc3-mw/Viren	8,262	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/aesv8-armx-ios64.S	// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(__APPLE__) #include <ring-core/arm_arch.h> #if __ARM_MAX_ARCH__>=7 .text .section __TEXT,__const .align 5 Lrcon: .long 0x01,0x01,0x01,0x01 .long 0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d // rotate-n-splat .long 0x1b,0x1b,0x1b,0x1b .text .globl _aes_hw_set_encrypt_key .private_extern _aes_hw_set_encrypt_key .align 5 _aes_hw_set_encrypt_key: Lenc_key: // Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later. AARCH64_VALID_CALL_TARGET stp x29,x30,[sp,#-16]! add x29,sp,#0 mov x3,#-1 cmp x0,#0 b.eq Lenc_key_abort cmp x2,#0 b.eq Lenc_key_abort mov x3,#-2 cmp w1,#128 b.lt Lenc_key_abort cmp w1,#256 b.gt Lenc_key_abort tst w1,#0x3f b.ne Lenc_key_abort adrp x3,Lrcon@PAGE add x3,x3,Lrcon@PAGEOFF cmp w1,#192 eor v0.16b,v0.16b,v0.16b ld1 {v3.16b},[x0],#16 mov w1,#8 // reuse w1 ld1 {v1.4s,v2.4s},[x3],#32 b.lt Loop128 // 192-bit key support was removed. b L256 .align 4 Loop128: tbl v6.16b,{v3.16b},v2.16b ext v5.16b,v0.16b,v3.16b,#12 st1 {v3.4s},[x2],#16 aese v6.16b,v0.16b subs w1,w1,#1 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v6.16b,v6.16b,v1.16b eor v3.16b,v3.16b,v5.16b shl v1.16b,v1.16b,#1 eor v3.16b,v3.16b,v6.16b b.ne Loop128 ld1 {v1.4s},[x3] tbl v6.16b,{v3.16b},v2.16b ext v5.16b,v0.16b,v3.16b,#12 st1 {v3.4s},[x2],#16 aese v6.16b,v0.16b eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v6.16b,v6.16b,v1.16b eor v3.16b,v3.16b,v5.16b shl v1.16b,v1.16b,#1 eor v3.16b,v3.16b,v6.16b tbl v6.16b,{v3.16b},v2.16b ext v5.16b,v0.16b,v3.16b,#12 st1 {v3.4s},[x2],#16 aese v6.16b,v0.16b eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v6.16b,v6.16b,v1.16b eor v3.16b,v3.16b,v5.16b eor v3.16b,v3.16b,v6.16b st1 {v3.4s},[x2] add x2,x2,#0x50 mov w12,#10 b Ldone // 192-bit key support was removed. .align 4 L256: ld1 {v4.16b},[x0] mov w1,#7 mov w12,#14 st1 {v3.4s},[x2],#16 Loop256: tbl v6.16b,{v4.16b},v2.16b ext v5.16b,v0.16b,v3.16b,#12 st1 {v4.4s},[x2],#16 aese v6.16b,v0.16b subs w1,w1,#1 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v6.16b,v6.16b,v1.16b eor v3.16b,v3.16b,v5.16b shl v1.16b,v1.16b,#1 eor v3.16b,v3.16b,v6.16b st1 {v3.4s},[x2],#16 b.eq Ldone dup v6.4s,v3.s[3] // just splat ext v5.16b,v0.16b,v4.16b,#12 aese v6.16b,v0.16b eor v4.16b,v4.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v4.16b,v4.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v4.16b,v4.16b,v5.16b eor v4.16b,v4.16b,v6.16b b Loop256 Ldone: str w12,[x2] mov x3,#0 Lenc_key_abort: mov x0,x3 // return value ldr x29,[sp],#16 ret .globl _aes_hw_encrypt .private_extern _aes_hw_encrypt .align 5 _aes_hw_encrypt: AARCH64_VALID_CALL_TARGET ldr w3,[x2,#240] ld1 {v0.4s},[x2],#16 ld1 {v2.16b},[x0] sub w3,w3,#2 ld1 {v1.4s},[x2],#16 Loop_enc: aese v2.16b,v0.16b aesmc v2.16b,v2.16b ld1 {v0.4s},[x2],#16 subs w3,w3,#2 aese v2.16b,v1.16b aesmc v2.16b,v2.16b ld1 {v1.4s},[x2],#16 b.gt Loop_enc aese v2.16b,v0.16b aesmc v2.16b,v2.16b ld1 {v0.4s},[x2] aese v2.16b,v1.16b eor v2.16b,v2.16b,v0.16b st1 {v2.16b},[x1] ret .globl _aes_hw_ctr32_encrypt_blocks .private_extern _aes_hw_ctr32_encrypt_blocks .align 5 _aes_hw_ctr32_encrypt_blocks: // Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later. AARCH64_VALID_CALL_TARGET stp x29,x30,[sp,#-16]! add x29,sp,#0 ldr w5,[x3,#240] ldr w8, [x4, #12] ld1 {v0.4s},[x4] ld1 {v16.4s,v17.4s},[x3] // load key schedule... sub w5,w5,#4 mov x12,#16 cmp x2,#2 add x7,x3,x5,lsl#4 // pointer to last 5 round keys sub w5,w5,#2 ld1 {v20.4s,v21.4s},[x7],#32 ld1 {v22.4s,v23.4s},[x7],#32 ld1 {v7.4s},[x7] add x7,x3,#32 mov w6,w5 csel x12,xzr,x12,lo // ARM Cortex-A57 and Cortex-A72 cores running in 32-bit mode are // affected by silicon errata #1742098 [0] and #1655431 [1], // respectively, where the second instruction of an aese/aesmc // instruction pair may execute twice if an interrupt is taken right // after the first instruction consumes an input register of which a // single 32-bit lane has been updated the last time it was modified. // // This function uses a counter in one 32-bit lane. The vmov lines // could write to v1.16b and v18.16b directly, but that trips this bugs. // We write to v6.16b and copy to the final register as a workaround. // // [0] ARM-EPM-049219 v23 Cortex-A57 MPCore Software Developers Errata Notice // [1] ARM-EPM-012079 v11.0 Cortex-A72 MPCore Software Developers Errata Notice #ifndef __AARCH64EB__ rev w8, w8 #endif add w10, w8, #1 orr v6.16b,v0.16b,v0.16b rev w10, w10 mov v6.s[3],w10 add w8, w8, #2 orr v1.16b,v6.16b,v6.16b b.ls Lctr32_tail rev w12, w8 mov v6.s[3],w12 sub x2,x2,#3 // bias orr v18.16b,v6.16b,v6.16b b Loop3x_ctr32 .align 4 Loop3x_ctr32: aese v0.16b,v16.16b aesmc v0.16b,v0.16b aese v1.16b,v16.16b aesmc v1.16b,v1.16b aese v18.16b,v16.16b aesmc v18.16b,v18.16b ld1 {v16.4s},[x7],#16 subs w6,w6,#2 aese v0.16b,v17.16b aesmc v0.16b,v0.16b aese v1.16b,v17.16b aesmc v1.16b,v1.16b aese v18.16b,v17.16b aesmc v18.16b,v18.16b ld1 {v17.4s},[x7],#16 b.gt Loop3x_ctr32 aese v0.16b,v16.16b aesmc v4.16b,v0.16b aese v1.16b,v16.16b aesmc v5.16b,v1.16b ld1 {v2.16b},[x0],#16 add w9,w8,#1 aese v18.16b,v16.16b aesmc v18.16b,v18.16b ld1 {v3.16b},[x0],#16 rev w9,w9 aese v4.16b,v17.16b aesmc v4.16b,v4.16b aese v5.16b,v17.16b aesmc v5.16b,v5.16b ld1 {v19.16b},[x0],#16 mov x7,x3 aese v18.16b,v17.16b aesmc v17.16b,v18.16b aese v4.16b,v20.16b aesmc v4.16b,v4.16b aese v5.16b,v20.16b aesmc v5.16b,v5.16b eor v2.16b,v2.16b,v7.16b add w10,w8,#2 aese v17.16b,v20.16b aesmc v17.16b,v17.16b eor v3.16b,v3.16b,v7.16b add w8,w8,#3 aese v4.16b,v21.16b aesmc v4.16b,v4.16b aese v5.16b,v21.16b aesmc v5.16b,v5.16b // Note the logic to update v0.16b, v1.16b, and v1.16b is written to work // around a bug in ARM Cortex-A57 and Cortex-A72 cores running in // 32-bit mode. See the comment above. eor v19.16b,v19.16b,v7.16b mov v6.s[3], w9 aese v17.16b,v21.16b aesmc v17.16b,v17.16b orr v0.16b,v6.16b,v6.16b rev w10,w10 aese v4.16b,v22.16b aesmc v4.16b,v4.16b mov v6.s[3], w10 rev w12,w8 aese v5.16b,v22.16b aesmc v5.16b,v5.16b orr v1.16b,v6.16b,v6.16b mov v6.s[3], w12 aese v17.16b,v22.16b aesmc v17.16b,v17.16b orr v18.16b,v6.16b,v6.16b subs x2,x2,#3 aese v4.16b,v23.16b aese v5.16b,v23.16b aese v17.16b,v23.16b eor v2.16b,v2.16b,v4.16b ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0] st1 {v2.16b},[x1],#16 eor v3.16b,v3.16b,v5.16b mov w6,w5 st1 {v3.16b},[x1],#16 eor v19.16b,v19.16b,v17.16b ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1] st1 {v19.16b},[x1],#16 b.hs Loop3x_ctr32 adds x2,x2,#3 b.eq Lctr32_done cmp x2,#1 mov x12,#16 csel x12,xzr,x12,eq Lctr32_tail: aese v0.16b,v16.16b aesmc v0.16b,v0.16b aese v1.16b,v16.16b aesmc v1.16b,v1.16b ld1 {v16.4s},[x7],#16 subs w6,w6,#2 aese v0.16b,v17.16b aesmc v0.16b,v0.16b aese v1.16b,v17.16b aesmc v1.16b,v1.16b ld1 {v17.4s},[x7],#16 b.gt Lctr32_tail aese v0.16b,v16.16b aesmc v0.16b,v0.16b aese v1.16b,v16.16b aesmc v1.16b,v1.16b aese v0.16b,v17.16b aesmc v0.16b,v0.16b aese v1.16b,v17.16b aesmc v1.16b,v1.16b ld1 {v2.16b},[x0],x12 aese v0.16b,v20.16b aesmc v0.16b,v0.16b aese v1.16b,v20.16b aesmc v1.16b,v1.16b ld1 {v3.16b},[x0] aese v0.16b,v21.16b aesmc v0.16b,v0.16b aese v1.16b,v21.16b aesmc v1.16b,v1.16b eor v2.16b,v2.16b,v7.16b aese v0.16b,v22.16b aesmc v0.16b,v0.16b aese v1.16b,v22.16b aesmc v1.16b,v1.16b eor v3.16b,v3.16b,v7.16b aese v0.16b,v23.16b aese v1.16b,v23.16b cmp x2,#1 eor v2.16b,v2.16b,v0.16b eor v3.16b,v3.16b,v1.16b st1 {v2.16b},[x1],#16 b.eq Lctr32_done st1 {v3.16b},[x1] Lctr32_done: ldr x29,[sp],#16 ret #endif #endif // !OPENSSL_NO_ASM && defined(OPENSSL_AARCH64) && defined(__APPLE__)
j4yc3-mw/Viren	43,302	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/sha512-armv4-linux32.S	// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__) @ Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved. @ @ Licensed under the OpenSSL license (the "License"). You may not use @ this file except in compliance with the License. You can obtain a copy @ in the file LICENSE in the source distribution or at @ https://www.openssl.org/source/license.html @ ==================================================================== @ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL @ project. The module is, however, dual licensed under OpenSSL and @ CRYPTOGAMS licenses depending on where you obtain it. For further @ details see http://www.openssl.org/~appro/cryptogams/. @ @ Permission to use under GPL terms is granted. @ ==================================================================== @ SHA512 block procedure for ARMv4. September 2007. @ This code is ~4.5 (four and a half) times faster than code generated @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue @ Xscale PXA250 core]. @ @ July 2010. @ @ Rescheduling for dual-issue pipeline resulted in 6% improvement on @ Cortex A8 core and ~40 cycles per processed byte. @ February 2011. @ @ Profiler-assisted and platform-specific optimization resulted in 7% @ improvement on Coxtex A8 core and ~38 cycles per byte. @ March 2011. @ @ Add NEON implementation. On Cortex A8 it was measured to process @ one byte in 23.3 cycles or ~60% faster than integer-only code. @ August 2012. @ @ Improve NEON performance by 12% on Snapdragon S4. In absolute @ terms it's 22.6 cycles per byte, which is disappointing result. @ Technical writers asserted that 3-way S4 pipeline can sustain @ multiple NEON instructions per cycle, but dual NEON issue could @ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html @ for further details. On side note Cortex-A15 processes one byte in @ 16 cycles. @ Byte order [in]dependence. ========================================= @ @ Originally caller was expected to maintain specific dword order in @ h[0-7], namely with most significant dword at lower address, which @ was reflected in below two parameters as 0 and 4. Now caller is @ expected to maintain native byte order for whole 64-bit values. #ifndef __KERNEL__ # include <ring-core/arm_arch.h> # define VFP_ABI_PUSH vstmdb sp!,{d8-d15} # define VFP_ABI_POP vldmia sp!,{d8-d15} #else # define __ARM_ARCH__ __LINUX_ARM_ARCH__ # define __ARM_MAX_ARCH__ 7 # define VFP_ABI_PUSH # define VFP_ABI_POP #endif @ Silence ARMv8 deprecated IT instruction warnings. This file is used by both @ ARMv7 and ARMv8 processors and does not use ARMv8 instructions. .arch armv7-a #ifdef __ARMEL__ # define LO 0 # define HI 4 # define WORD64(hi0,lo0,hi1,lo1) .word lo0,hi0, lo1,hi1 #else # define HI 0 # define LO 4 # define WORD64(hi0,lo0,hi1,lo1) .word hi0,lo0, hi1,lo1 #endif .text #if defined(__thumb2__) .syntax unified .thumb # define adrl adr #else .code 32 #endif .type K512,%object .align 5 K512: WORD64(0x428a2f98,0xd728ae22, 0x71374491,0x23ef65cd) WORD64(0xb5c0fbcf,0xec4d3b2f, 0xe9b5dba5,0x8189dbbc) WORD64(0x3956c25b,0xf348b538, 0x59f111f1,0xb605d019) WORD64(0x923f82a4,0xaf194f9b, 0xab1c5ed5,0xda6d8118) WORD64(0xd807aa98,0xa3030242, 0x12835b01,0x45706fbe) WORD64(0x243185be,0x4ee4b28c, 0x550c7dc3,0xd5ffb4e2) WORD64(0x72be5d74,0xf27b896f, 0x80deb1fe,0x3b1696b1) WORD64(0x9bdc06a7,0x25c71235, 0xc19bf174,0xcf692694) WORD64(0xe49b69c1,0x9ef14ad2, 0xefbe4786,0x384f25e3) WORD64(0x0fc19dc6,0x8b8cd5b5, 0x240ca1cc,0x77ac9c65) WORD64(0x2de92c6f,0x592b0275, 0x4a7484aa,0x6ea6e483) WORD64(0x5cb0a9dc,0xbd41fbd4, 0x76f988da,0x831153b5) WORD64(0x983e5152,0xee66dfab, 0xa831c66d,0x2db43210) WORD64(0xb00327c8,0x98fb213f, 0xbf597fc7,0xbeef0ee4) WORD64(0xc6e00bf3,0x3da88fc2, 0xd5a79147,0x930aa725) WORD64(0x06ca6351,0xe003826f, 0x14292967,0x0a0e6e70) WORD64(0x27b70a85,0x46d22ffc, 0x2e1b2138,0x5c26c926) WORD64(0x4d2c6dfc,0x5ac42aed, 0x53380d13,0x9d95b3df) WORD64(0x650a7354,0x8baf63de, 0x766a0abb,0x3c77b2a8) WORD64(0x81c2c92e,0x47edaee6, 0x92722c85,0x1482353b) WORD64(0xa2bfe8a1,0x4cf10364, 0xa81a664b,0xbc423001) WORD64(0xc24b8b70,0xd0f89791, 0xc76c51a3,0x0654be30) WORD64(0xd192e819,0xd6ef5218, 0xd6990624,0x5565a910) WORD64(0xf40e3585,0x5771202a, 0x106aa070,0x32bbd1b8) WORD64(0x19a4c116,0xb8d2d0c8, 0x1e376c08,0x5141ab53) WORD64(0x2748774c,0xdf8eeb99, 0x34b0bcb5,0xe19b48a8) WORD64(0x391c0cb3,0xc5c95a63, 0x4ed8aa4a,0xe3418acb) WORD64(0x5b9cca4f,0x7763e373, 0x682e6ff3,0xd6b2b8a3) WORD64(0x748f82ee,0x5defb2fc, 0x78a5636f,0x43172f60) WORD64(0x84c87814,0xa1f0ab72, 0x8cc70208,0x1a6439ec) WORD64(0x90befffa,0x23631e28, 0xa4506ceb,0xde82bde9) WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b) WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207) WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178) WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6) WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b) WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493) WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c) WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a) WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817) .size K512,.-K512 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) .hidden OPENSSL_armcap_P .LOPENSSL_armcap: .word OPENSSL_armcap_P-.Lsha512_block_data_order .skip 32-4 #else .skip 32 #endif .globl sha512_block_data_order .hidden sha512_block_data_order .type sha512_block_data_order,%function sha512_block_data_order: .Lsha512_block_data_order: #if __ARM_ARCH__<7 && !defined(__thumb2__) sub r3,pc,#8 @ sha512_block_data_order #else adr r3,.Lsha512_block_data_order #endif #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) ldr r12,.LOPENSSL_armcap ldr r12,[r3,r12] @ OPENSSL_armcap_P #ifdef __APPLE__ ldr r12,[r12] #endif tst r12,#ARMV7_NEON bne .LNEON #endif add r2,r1,r2,lsl#7 @ len to point at the end of inp stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} sub r14,r3,#672 @ K512 sub sp,sp,#98 ldr r7,[r0,#32+LO] ldr r8,[r0,#32+HI] ldr r9, [r0,#48+LO] ldr r10, [r0,#48+HI] ldr r11, [r0,#56+LO] ldr r12, [r0,#56+HI] .Loop: str r9, [sp,#48+0] str r10, [sp,#48+4] str r11, [sp,#56+0] str r12, [sp,#56+4] ldr r5,[r0,#0+LO] ldr r6,[r0,#0+HI] ldr r3,[r0,#8+LO] ldr r4,[r0,#8+HI] ldr r9, [r0,#16+LO] ldr r10, [r0,#16+HI] ldr r11, [r0,#24+LO] ldr r12, [r0,#24+HI] str r3,[sp,#8+0] str r4,[sp,#8+4] str r9, [sp,#16+0] str r10, [sp,#16+4] str r11, [sp,#24+0] str r12, [sp,#24+4] ldr r3,[r0,#40+LO] ldr r4,[r0,#40+HI] str r3,[sp,#40+0] str r4,[sp,#40+4] .L00_15: #if __ARM_ARCH__<7 ldrb r3,[r1,#7] ldrb r9, [r1,#6] ldrb r10, [r1,#5] ldrb r11, [r1,#4] ldrb r4,[r1,#3] ldrb r12, [r1,#2] orr r3,r3,r9,lsl#8 ldrb r9, [r1,#1] orr r3,r3,r10,lsl#16 ldrb r10, [r1],#8 orr r3,r3,r11,lsl#24 orr r4,r4,r12,lsl#8 orr r4,r4,r9,lsl#16 orr r4,r4,r10,lsl#24 #else ldr r3,[r1,#4] ldr r4,[r1],#8 #ifdef __ARMEL__ rev r3,r3 rev r4,r4 #endif #endif @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 mov r9,r7,lsr#14 str r3,[sp,#64+0] mov r10,r8,lsr#14 str r4,[sp,#64+4] eor r9,r9,r8,lsl#18 ldr r11,[sp,#56+0] @ h.lo eor r10,r10,r7,lsl#18 ldr r12,[sp,#56+4] @ h.hi eor r9,r9,r7,lsr#18 eor r10,r10,r8,lsr#18 eor r9,r9,r8,lsl#14 eor r10,r10,r7,lsl#14 eor r9,r9,r8,lsr#9 eor r10,r10,r7,lsr#9 eor r9,r9,r7,lsl#23 eor r10,r10,r8,lsl#23 @ Sigma1(e) adds r3,r3,r9 ldr r9,[sp,#40+0] @ f.lo adc r4,r4,r10 @ T += Sigma1(e) ldr r10,[sp,#40+4] @ f.hi adds r3,r3,r11 ldr r11,[sp,#48+0] @ g.lo adc r4,r4,r12 @ T += h ldr r12,[sp,#48+4] @ g.hi eor r9,r9,r11 str r7,[sp,#32+0] eor r10,r10,r12 str r8,[sp,#32+4] and r9,r9,r7 str r5,[sp,#0+0] and r10,r10,r8 str r6,[sp,#0+4] eor r9,r9,r11 ldr r11,[r14,#LO] @ K[i].lo eor r10,r10,r12 @ Ch(e,f,g) ldr r12,[r14,#HI] @ K[i].hi adds r3,r3,r9 ldr r7,[sp,#24+0] @ d.lo adc r4,r4,r10 @ T += Ch(e,f,g) ldr r8,[sp,#24+4] @ d.hi adds r3,r3,r11 and r9,r11,#0xff adc r4,r4,r12 @ T += K[i] adds r7,r7,r3 ldr r11,[sp,#8+0] @ b.lo adc r8,r8,r4 @ d += T teq r9,#148 ldr r12,[sp,#16+0] @ c.lo #if __ARM_ARCH__>=7 it eq @ Thumb2 thing, sanity check in ARM #endif orreq r14,r14,#1 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 mov r9,r5,lsr#28 mov r10,r6,lsr#28 eor r9,r9,r6,lsl#4 eor r10,r10,r5,lsl#4 eor r9,r9,r6,lsr#2 eor r10,r10,r5,lsr#2 eor r9,r9,r5,lsl#30 eor r10,r10,r6,lsl#30 eor r9,r9,r6,lsr#7 eor r10,r10,r5,lsr#7 eor r9,r9,r5,lsl#25 eor r10,r10,r6,lsl#25 @ Sigma0(a) adds r3,r3,r9 and r9,r5,r11 adc r4,r4,r10 @ T += Sigma0(a) ldr r10,[sp,#8+4] @ b.hi orr r5,r5,r11 ldr r11,[sp,#16+4] @ c.hi and r5,r5,r12 and r12,r6,r10 orr r6,r6,r10 orr r5,r5,r9 @ Maj(a,b,c).lo and r6,r6,r11 adds r5,r5,r3 orr r6,r6,r12 @ Maj(a,b,c).hi sub sp,sp,#8 adc r6,r6,r4 @ h += T tst r14,#1 add r14,r14,#8 tst r14,#1 beq .L00_15 ldr r9,[sp,#184+0] ldr r10,[sp,#184+4] bic r14,r14,#1 .L16_79: @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7)) @ LO lo>>1^hi<<31 ^ lo>>8^hi<<24 ^ lo>>7^hi<<25 @ HI hi>>1^lo<<31 ^ hi>>8^lo<<24 ^ hi>>7 mov r3,r9,lsr#1 ldr r11,[sp,#80+0] mov r4,r10,lsr#1 ldr r12,[sp,#80+4] eor r3,r3,r10,lsl#31 eor r4,r4,r9,lsl#31 eor r3,r3,r9,lsr#8 eor r4,r4,r10,lsr#8 eor r3,r3,r10,lsl#24 eor r4,r4,r9,lsl#24 eor r3,r3,r9,lsr#7 eor r4,r4,r10,lsr#7 eor r3,r3,r10,lsl#25 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)) @ LO lo>>19^hi<<13 ^ hi>>29^lo<<3 ^ lo>>6^hi<<26 @ HI hi>>19^lo<<13 ^ lo>>29^hi<<3 ^ hi>>6 mov r9,r11,lsr#19 mov r10,r12,lsr#19 eor r9,r9,r12,lsl#13 eor r10,r10,r11,lsl#13 eor r9,r9,r12,lsr#29 eor r10,r10,r11,lsr#29 eor r9,r9,r11,lsl#3 eor r10,r10,r12,lsl#3 eor r9,r9,r11,lsr#6 eor r10,r10,r12,lsr#6 ldr r11,[sp,#120+0] eor r9,r9,r12,lsl#26 ldr r12,[sp,#120+4] adds r3,r3,r9 ldr r9,[sp,#192+0] adc r4,r4,r10 ldr r10,[sp,#192+4] adds r3,r3,r11 adc r4,r4,r12 adds r3,r3,r9 adc r4,r4,r10 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 mov r9,r7,lsr#14 str r3,[sp,#64+0] mov r10,r8,lsr#14 str r4,[sp,#64+4] eor r9,r9,r8,lsl#18 ldr r11,[sp,#56+0] @ h.lo eor r10,r10,r7,lsl#18 ldr r12,[sp,#56+4] @ h.hi eor r9,r9,r7,lsr#18 eor r10,r10,r8,lsr#18 eor r9,r9,r8,lsl#14 eor r10,r10,r7,lsl#14 eor r9,r9,r8,lsr#9 eor r10,r10,r7,lsr#9 eor r9,r9,r7,lsl#23 eor r10,r10,r8,lsl#23 @ Sigma1(e) adds r3,r3,r9 ldr r9,[sp,#40+0] @ f.lo adc r4,r4,r10 @ T += Sigma1(e) ldr r10,[sp,#40+4] @ f.hi adds r3,r3,r11 ldr r11,[sp,#48+0] @ g.lo adc r4,r4,r12 @ T += h ldr r12,[sp,#48+4] @ g.hi eor r9,r9,r11 str r7,[sp,#32+0] eor r10,r10,r12 str r8,[sp,#32+4] and r9,r9,r7 str r5,[sp,#0+0] and r10,r10,r8 str r6,[sp,#0+4] eor r9,r9,r11 ldr r11,[r14,#LO] @ K[i].lo eor r10,r10,r12 @ Ch(e,f,g) ldr r12,[r14,#HI] @ K[i].hi adds r3,r3,r9 ldr r7,[sp,#24+0] @ d.lo adc r4,r4,r10 @ T += Ch(e,f,g) ldr r8,[sp,#24+4] @ d.hi adds r3,r3,r11 and r9,r11,#0xff adc r4,r4,r12 @ T += K[i] adds r7,r7,r3 ldr r11,[sp,#8+0] @ b.lo adc r8,r8,r4 @ d += T teq r9,#23 ldr r12,[sp,#16+0] @ c.lo #if __ARM_ARCH__>=7 it eq @ Thumb2 thing, sanity check in ARM #endif orreq r14,r14,#1 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 mov r9,r5,lsr#28 mov r10,r6,lsr#28 eor r9,r9,r6,lsl#4 eor r10,r10,r5,lsl#4 eor r9,r9,r6,lsr#2 eor r10,r10,r5,lsr#2 eor r9,r9,r5,lsl#30 eor r10,r10,r6,lsl#30 eor r9,r9,r6,lsr#7 eor r10,r10,r5,lsr#7 eor r9,r9,r5,lsl#25 eor r10,r10,r6,lsl#25 @ Sigma0(a) adds r3,r3,r9 and r9,r5,r11 adc r4,r4,r10 @ T += Sigma0(a) ldr r10,[sp,#8+4] @ b.hi orr r5,r5,r11 ldr r11,[sp,#16+4] @ c.hi and r5,r5,r12 and r12,r6,r10 orr r6,r6,r10 orr r5,r5,r9 @ Maj(a,b,c).lo and r6,r6,r11 adds r5,r5,r3 orr r6,r6,r12 @ Maj(a,b,c).hi sub sp,sp,#8 adc r6,r6,r4 @ h += T tst r14,#1 add r14,r14,#8 #if __ARM_ARCH__>=7 ittt eq @ Thumb2 thing, sanity check in ARM #endif ldreq r9,[sp,#184+0] ldreq r10,[sp,#184+4] beq .L16_79 bic r14,r14,#1 ldr r3,[sp,#8+0] ldr r4,[sp,#8+4] ldr r9, [r0,#0+LO] ldr r10, [r0,#0+HI] ldr r11, [r0,#8+LO] ldr r12, [r0,#8+HI] adds r9,r5,r9 str r9, [r0,#0+LO] adc r10,r6,r10 str r10, [r0,#0+HI] adds r11,r3,r11 str r11, [r0,#8+LO] adc r12,r4,r12 str r12, [r0,#8+HI] ldr r5,[sp,#16+0] ldr r6,[sp,#16+4] ldr r3,[sp,#24+0] ldr r4,[sp,#24+4] ldr r9, [r0,#16+LO] ldr r10, [r0,#16+HI] ldr r11, [r0,#24+LO] ldr r12, [r0,#24+HI] adds r9,r5,r9 str r9, [r0,#16+LO] adc r10,r6,r10 str r10, [r0,#16+HI] adds r11,r3,r11 str r11, [r0,#24+LO] adc r12,r4,r12 str r12, [r0,#24+HI] ldr r3,[sp,#40+0] ldr r4,[sp,#40+4] ldr r9, [r0,#32+LO] ldr r10, [r0,#32+HI] ldr r11, [r0,#40+LO] ldr r12, [r0,#40+HI] adds r7,r7,r9 str r7,[r0,#32+LO] adc r8,r8,r10 str r8,[r0,#32+HI] adds r11,r3,r11 str r11, [r0,#40+LO] adc r12,r4,r12 str r12, [r0,#40+HI] ldr r5,[sp,#48+0] ldr r6,[sp,#48+4] ldr r3,[sp,#56+0] ldr r4,[sp,#56+4] ldr r9, [r0,#48+LO] ldr r10, [r0,#48+HI] ldr r11, [r0,#56+LO] ldr r12, [r0,#56+HI] adds r9,r5,r9 str r9, [r0,#48+LO] adc r10,r6,r10 str r10, [r0,#48+HI] adds r11,r3,r11 str r11, [r0,#56+LO] adc r12,r4,r12 str r12, [r0,#56+HI] add sp,sp,#640 sub r14,r14,#640 teq r1,r2 bne .Loop add sp,sp,#89 @ destroy frame #if __ARM_ARCH__>=5 ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc} #else ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} tst lr,#1 moveq pc,lr @ be binary compatible with V4, yet .word 0xe12fff1e @ interoperable with Thumb ISA:-) #endif .size sha512_block_data_order,.-sha512_block_data_order #if __ARM_MAX_ARCH__>=7 .arch armv7-a .fpu neon .type sha512_block_data_order_neon,%function .align 4 sha512_block_data_order_neon: .LNEON: dmb @ errata #451034 on early Cortex A8 add r2,r1,r2,lsl#7 @ len to point at the end of inp adr r3,K512 VFP_ABI_PUSH vldmia r0,{d16,d17,d18,d19,d20,d21,d22,d23} @ load context .Loop_neon: vshr.u64 d24,d20,#14 @ 0 #if 0<16 vld1.64 {d0},[r1]! @ handles unaligned #endif vshr.u64 d25,d20,#18 #if 0>0 vadd.i64 d16,d30 @ h+=Maj from the past #endif vshr.u64 d26,d20,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d20,#50 vsli.64 d25,d20,#46 vmov d29,d20 vsli.64 d26,d20,#23 #if 0<16 && defined(__ARMEL__) vrev64.8 d0,d0 #endif veor d25,d24 vbsl d29,d21,d22 @ Ch(e,f,g) vshr.u64 d24,d16,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d23 vshr.u64 d25,d16,#34 vsli.64 d24,d16,#36 vadd.i64 d27,d26 vshr.u64 d26,d16,#39 vadd.i64 d28,d0 vsli.64 d25,d16,#30 veor d30,d16,d17 vsli.64 d26,d16,#25 veor d23,d24,d25 vadd.i64 d27,d28 vbsl d30,d18,d17 @ Maj(a,b,c) veor d23,d26 @ Sigma0(a) vadd.i64 d19,d27 vadd.i64 d30,d27 @ vadd.i64 d23,d30 vshr.u64 d24,d19,#14 @ 1 #if 1<16 vld1.64 {d1},[r1]! @ handles unaligned #endif vshr.u64 d25,d19,#18 #if 1>0 vadd.i64 d23,d30 @ h+=Maj from the past #endif vshr.u64 d26,d19,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d19,#50 vsli.64 d25,d19,#46 vmov d29,d19 vsli.64 d26,d19,#23 #if 1<16 && defined(__ARMEL__) vrev64.8 d1,d1 #endif veor d25,d24 vbsl d29,d20,d21 @ Ch(e,f,g) vshr.u64 d24,d23,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d22 vshr.u64 d25,d23,#34 vsli.64 d24,d23,#36 vadd.i64 d27,d26 vshr.u64 d26,d23,#39 vadd.i64 d28,d1 vsli.64 d25,d23,#30 veor d30,d23,d16 vsli.64 d26,d23,#25 veor d22,d24,d25 vadd.i64 d27,d28 vbsl d30,d17,d16 @ Maj(a,b,c) veor d22,d26 @ Sigma0(a) vadd.i64 d18,d27 vadd.i64 d30,d27 @ vadd.i64 d22,d30 vshr.u64 d24,d18,#14 @ 2 #if 2<16 vld1.64 {d2},[r1]! @ handles unaligned #endif vshr.u64 d25,d18,#18 #if 2>0 vadd.i64 d22,d30 @ h+=Maj from the past #endif vshr.u64 d26,d18,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d18,#50 vsli.64 d25,d18,#46 vmov d29,d18 vsli.64 d26,d18,#23 #if 2<16 && defined(__ARMEL__) vrev64.8 d2,d2 #endif veor d25,d24 vbsl d29,d19,d20 @ Ch(e,f,g) vshr.u64 d24,d22,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d21 vshr.u64 d25,d22,#34 vsli.64 d24,d22,#36 vadd.i64 d27,d26 vshr.u64 d26,d22,#39 vadd.i64 d28,d2 vsli.64 d25,d22,#30 veor d30,d22,d23 vsli.64 d26,d22,#25 veor d21,d24,d25 vadd.i64 d27,d28 vbsl d30,d16,d23 @ Maj(a,b,c) veor d21,d26 @ Sigma0(a) vadd.i64 d17,d27 vadd.i64 d30,d27 @ vadd.i64 d21,d30 vshr.u64 d24,d17,#14 @ 3 #if 3<16 vld1.64 {d3},[r1]! @ handles unaligned #endif vshr.u64 d25,d17,#18 #if 3>0 vadd.i64 d21,d30 @ h+=Maj from the past #endif vshr.u64 d26,d17,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d17,#50 vsli.64 d25,d17,#46 vmov d29,d17 vsli.64 d26,d17,#23 #if 3<16 && defined(__ARMEL__) vrev64.8 d3,d3 #endif veor d25,d24 vbsl d29,d18,d19 @ Ch(e,f,g) vshr.u64 d24,d21,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d20 vshr.u64 d25,d21,#34 vsli.64 d24,d21,#36 vadd.i64 d27,d26 vshr.u64 d26,d21,#39 vadd.i64 d28,d3 vsli.64 d25,d21,#30 veor d30,d21,d22 vsli.64 d26,d21,#25 veor d20,d24,d25 vadd.i64 d27,d28 vbsl d30,d23,d22 @ Maj(a,b,c) veor d20,d26 @ Sigma0(a) vadd.i64 d16,d27 vadd.i64 d30,d27 @ vadd.i64 d20,d30 vshr.u64 d24,d16,#14 @ 4 #if 4<16 vld1.64 {d4},[r1]! @ handles unaligned #endif vshr.u64 d25,d16,#18 #if 4>0 vadd.i64 d20,d30 @ h+=Maj from the past #endif vshr.u64 d26,d16,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d16,#50 vsli.64 d25,d16,#46 vmov d29,d16 vsli.64 d26,d16,#23 #if 4<16 && defined(__ARMEL__) vrev64.8 d4,d4 #endif veor d25,d24 vbsl d29,d17,d18 @ Ch(e,f,g) vshr.u64 d24,d20,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d19 vshr.u64 d25,d20,#34 vsli.64 d24,d20,#36 vadd.i64 d27,d26 vshr.u64 d26,d20,#39 vadd.i64 d28,d4 vsli.64 d25,d20,#30 veor d30,d20,d21 vsli.64 d26,d20,#25 veor d19,d24,d25 vadd.i64 d27,d28 vbsl d30,d22,d21 @ Maj(a,b,c) veor d19,d26 @ Sigma0(a) vadd.i64 d23,d27 vadd.i64 d30,d27 @ vadd.i64 d19,d30 vshr.u64 d24,d23,#14 @ 5 #if 5<16 vld1.64 {d5},[r1]! @ handles unaligned #endif vshr.u64 d25,d23,#18 #if 5>0 vadd.i64 d19,d30 @ h+=Maj from the past #endif vshr.u64 d26,d23,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d23,#50 vsli.64 d25,d23,#46 vmov d29,d23 vsli.64 d26,d23,#23 #if 5<16 && defined(__ARMEL__) vrev64.8 d5,d5 #endif veor d25,d24 vbsl d29,d16,d17 @ Ch(e,f,g) vshr.u64 d24,d19,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d18 vshr.u64 d25,d19,#34 vsli.64 d24,d19,#36 vadd.i64 d27,d26 vshr.u64 d26,d19,#39 vadd.i64 d28,d5 vsli.64 d25,d19,#30 veor d30,d19,d20 vsli.64 d26,d19,#25 veor d18,d24,d25 vadd.i64 d27,d28 vbsl d30,d21,d20 @ Maj(a,b,c) veor d18,d26 @ Sigma0(a) vadd.i64 d22,d27 vadd.i64 d30,d27 @ vadd.i64 d18,d30 vshr.u64 d24,d22,#14 @ 6 #if 6<16 vld1.64 {d6},[r1]! @ handles unaligned #endif vshr.u64 d25,d22,#18 #if 6>0 vadd.i64 d18,d30 @ h+=Maj from the past #endif vshr.u64 d26,d22,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d22,#50 vsli.64 d25,d22,#46 vmov d29,d22 vsli.64 d26,d22,#23 #if 6<16 && defined(__ARMEL__) vrev64.8 d6,d6 #endif veor d25,d24 vbsl d29,d23,d16 @ Ch(e,f,g) vshr.u64 d24,d18,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d17 vshr.u64 d25,d18,#34 vsli.64 d24,d18,#36 vadd.i64 d27,d26 vshr.u64 d26,d18,#39 vadd.i64 d28,d6 vsli.64 d25,d18,#30 veor d30,d18,d19 vsli.64 d26,d18,#25 veor d17,d24,d25 vadd.i64 d27,d28 vbsl d30,d20,d19 @ Maj(a,b,c) veor d17,d26 @ Sigma0(a) vadd.i64 d21,d27 vadd.i64 d30,d27 @ vadd.i64 d17,d30 vshr.u64 d24,d21,#14 @ 7 #if 7<16 vld1.64 {d7},[r1]! @ handles unaligned #endif vshr.u64 d25,d21,#18 #if 7>0 vadd.i64 d17,d30 @ h+=Maj from the past #endif vshr.u64 d26,d21,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d21,#50 vsli.64 d25,d21,#46 vmov d29,d21 vsli.64 d26,d21,#23 #if 7<16 && defined(__ARMEL__) vrev64.8 d7,d7 #endif veor d25,d24 vbsl d29,d22,d23 @ Ch(e,f,g) vshr.u64 d24,d17,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d16 vshr.u64 d25,d17,#34 vsli.64 d24,d17,#36 vadd.i64 d27,d26 vshr.u64 d26,d17,#39 vadd.i64 d28,d7 vsli.64 d25,d17,#30 veor d30,d17,d18 vsli.64 d26,d17,#25 veor d16,d24,d25 vadd.i64 d27,d28 vbsl d30,d19,d18 @ Maj(a,b,c) veor d16,d26 @ Sigma0(a) vadd.i64 d20,d27 vadd.i64 d30,d27 @ vadd.i64 d16,d30 vshr.u64 d24,d20,#14 @ 8 #if 8<16 vld1.64 {d8},[r1]! @ handles unaligned #endif vshr.u64 d25,d20,#18 #if 8>0 vadd.i64 d16,d30 @ h+=Maj from the past #endif vshr.u64 d26,d20,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d20,#50 vsli.64 d25,d20,#46 vmov d29,d20 vsli.64 d26,d20,#23 #if 8<16 && defined(__ARMEL__) vrev64.8 d8,d8 #endif veor d25,d24 vbsl d29,d21,d22 @ Ch(e,f,g) vshr.u64 d24,d16,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d23 vshr.u64 d25,d16,#34 vsli.64 d24,d16,#36 vadd.i64 d27,d26 vshr.u64 d26,d16,#39 vadd.i64 d28,d8 vsli.64 d25,d16,#30 veor d30,d16,d17 vsli.64 d26,d16,#25 veor d23,d24,d25 vadd.i64 d27,d28 vbsl d30,d18,d17 @ Maj(a,b,c) veor d23,d26 @ Sigma0(a) vadd.i64 d19,d27 vadd.i64 d30,d27 @ vadd.i64 d23,d30 vshr.u64 d24,d19,#14 @ 9 #if 9<16 vld1.64 {d9},[r1]! @ handles unaligned #endif vshr.u64 d25,d19,#18 #if 9>0 vadd.i64 d23,d30 @ h+=Maj from the past #endif vshr.u64 d26,d19,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d19,#50 vsli.64 d25,d19,#46 vmov d29,d19 vsli.64 d26,d19,#23 #if 9<16 && defined(__ARMEL__) vrev64.8 d9,d9 #endif veor d25,d24 vbsl d29,d20,d21 @ Ch(e,f,g) vshr.u64 d24,d23,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d22 vshr.u64 d25,d23,#34 vsli.64 d24,d23,#36 vadd.i64 d27,d26 vshr.u64 d26,d23,#39 vadd.i64 d28,d9 vsli.64 d25,d23,#30 veor d30,d23,d16 vsli.64 d26,d23,#25 veor d22,d24,d25 vadd.i64 d27,d28 vbsl d30,d17,d16 @ Maj(a,b,c) veor d22,d26 @ Sigma0(a) vadd.i64 d18,d27 vadd.i64 d30,d27 @ vadd.i64 d22,d30 vshr.u64 d24,d18,#14 @ 10 #if 10<16 vld1.64 {d10},[r1]! @ handles unaligned #endif vshr.u64 d25,d18,#18 #if 10>0 vadd.i64 d22,d30 @ h+=Maj from the past #endif vshr.u64 d26,d18,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d18,#50 vsli.64 d25,d18,#46 vmov d29,d18 vsli.64 d26,d18,#23 #if 10<16 && defined(__ARMEL__) vrev64.8 d10,d10 #endif veor d25,d24 vbsl d29,d19,d20 @ Ch(e,f,g) vshr.u64 d24,d22,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d21 vshr.u64 d25,d22,#34 vsli.64 d24,d22,#36 vadd.i64 d27,d26 vshr.u64 d26,d22,#39 vadd.i64 d28,d10 vsli.64 d25,d22,#30 veor d30,d22,d23 vsli.64 d26,d22,#25 veor d21,d24,d25 vadd.i64 d27,d28 vbsl d30,d16,d23 @ Maj(a,b,c) veor d21,d26 @ Sigma0(a) vadd.i64 d17,d27 vadd.i64 d30,d27 @ vadd.i64 d21,d30 vshr.u64 d24,d17,#14 @ 11 #if 11<16 vld1.64 {d11},[r1]! @ handles unaligned #endif vshr.u64 d25,d17,#18 #if 11>0 vadd.i64 d21,d30 @ h+=Maj from the past #endif vshr.u64 d26,d17,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d17,#50 vsli.64 d25,d17,#46 vmov d29,d17 vsli.64 d26,d17,#23 #if 11<16 && defined(__ARMEL__) vrev64.8 d11,d11 #endif veor d25,d24 vbsl d29,d18,d19 @ Ch(e,f,g) vshr.u64 d24,d21,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d20 vshr.u64 d25,d21,#34 vsli.64 d24,d21,#36 vadd.i64 d27,d26 vshr.u64 d26,d21,#39 vadd.i64 d28,d11 vsli.64 d25,d21,#30 veor d30,d21,d22 vsli.64 d26,d21,#25 veor d20,d24,d25 vadd.i64 d27,d28 vbsl d30,d23,d22 @ Maj(a,b,c) veor d20,d26 @ Sigma0(a) vadd.i64 d16,d27 vadd.i64 d30,d27 @ vadd.i64 d20,d30 vshr.u64 d24,d16,#14 @ 12 #if 12<16 vld1.64 {d12},[r1]! @ handles unaligned #endif vshr.u64 d25,d16,#18 #if 12>0 vadd.i64 d20,d30 @ h+=Maj from the past #endif vshr.u64 d26,d16,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d16,#50 vsli.64 d25,d16,#46 vmov d29,d16 vsli.64 d26,d16,#23 #if 12<16 && defined(__ARMEL__) vrev64.8 d12,d12 #endif veor d25,d24 vbsl d29,d17,d18 @ Ch(e,f,g) vshr.u64 d24,d20,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d19 vshr.u64 d25,d20,#34 vsli.64 d24,d20,#36 vadd.i64 d27,d26 vshr.u64 d26,d20,#39 vadd.i64 d28,d12 vsli.64 d25,d20,#30 veor d30,d20,d21 vsli.64 d26,d20,#25 veor d19,d24,d25 vadd.i64 d27,d28 vbsl d30,d22,d21 @ Maj(a,b,c) veor d19,d26 @ Sigma0(a) vadd.i64 d23,d27 vadd.i64 d30,d27 @ vadd.i64 d19,d30 vshr.u64 d24,d23,#14 @ 13 #if 13<16 vld1.64 {d13},[r1]! @ handles unaligned #endif vshr.u64 d25,d23,#18 #if 13>0 vadd.i64 d19,d30 @ h+=Maj from the past #endif vshr.u64 d26,d23,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d23,#50 vsli.64 d25,d23,#46 vmov d29,d23 vsli.64 d26,d23,#23 #if 13<16 && defined(__ARMEL__) vrev64.8 d13,d13 #endif veor d25,d24 vbsl d29,d16,d17 @ Ch(e,f,g) vshr.u64 d24,d19,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d18 vshr.u64 d25,d19,#34 vsli.64 d24,d19,#36 vadd.i64 d27,d26 vshr.u64 d26,d19,#39 vadd.i64 d28,d13 vsli.64 d25,d19,#30 veor d30,d19,d20 vsli.64 d26,d19,#25 veor d18,d24,d25 vadd.i64 d27,d28 vbsl d30,d21,d20 @ Maj(a,b,c) veor d18,d26 @ Sigma0(a) vadd.i64 d22,d27 vadd.i64 d30,d27 @ vadd.i64 d18,d30 vshr.u64 d24,d22,#14 @ 14 #if 14<16 vld1.64 {d14},[r1]! @ handles unaligned #endif vshr.u64 d25,d22,#18 #if 14>0 vadd.i64 d18,d30 @ h+=Maj from the past #endif vshr.u64 d26,d22,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d22,#50 vsli.64 d25,d22,#46 vmov d29,d22 vsli.64 d26,d22,#23 #if 14<16 && defined(__ARMEL__) vrev64.8 d14,d14 #endif veor d25,d24 vbsl d29,d23,d16 @ Ch(e,f,g) vshr.u64 d24,d18,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d17 vshr.u64 d25,d18,#34 vsli.64 d24,d18,#36 vadd.i64 d27,d26 vshr.u64 d26,d18,#39 vadd.i64 d28,d14 vsli.64 d25,d18,#30 veor d30,d18,d19 vsli.64 d26,d18,#25 veor d17,d24,d25 vadd.i64 d27,d28 vbsl d30,d20,d19 @ Maj(a,b,c) veor d17,d26 @ Sigma0(a) vadd.i64 d21,d27 vadd.i64 d30,d27 @ vadd.i64 d17,d30 vshr.u64 d24,d21,#14 @ 15 #if 15<16 vld1.64 {d15},[r1]! @ handles unaligned #endif vshr.u64 d25,d21,#18 #if 15>0 vadd.i64 d17,d30 @ h+=Maj from the past #endif vshr.u64 d26,d21,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d21,#50 vsli.64 d25,d21,#46 vmov d29,d21 vsli.64 d26,d21,#23 #if 15<16 && defined(__ARMEL__) vrev64.8 d15,d15 #endif veor d25,d24 vbsl d29,d22,d23 @ Ch(e,f,g) vshr.u64 d24,d17,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d16 vshr.u64 d25,d17,#34 vsli.64 d24,d17,#36 vadd.i64 d27,d26 vshr.u64 d26,d17,#39 vadd.i64 d28,d15 vsli.64 d25,d17,#30 veor d30,d17,d18 vsli.64 d26,d17,#25 veor d16,d24,d25 vadd.i64 d27,d28 vbsl d30,d19,d18 @ Maj(a,b,c) veor d16,d26 @ Sigma0(a) vadd.i64 d20,d27 vadd.i64 d30,d27 @ vadd.i64 d16,d30 mov r12,#4 .L16_79_neon: subs r12,#1 vshr.u64 q12,q7,#19 vshr.u64 q13,q7,#61 vadd.i64 d16,d30 @ h+=Maj from the past vshr.u64 q15,q7,#6 vsli.64 q12,q7,#45 vext.8 q14,q0,q1,#8 @ X[i+1] vsli.64 q13,q7,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q0,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q4,q5,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d20,#14 @ from NEON_00_15 vadd.i64 q0,q14 vshr.u64 d25,d20,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d20,#41 @ from NEON_00_15 vadd.i64 q0,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d20,#50 vsli.64 d25,d20,#46 vmov d29,d20 vsli.64 d26,d20,#23 #if 16<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d21,d22 @ Ch(e,f,g) vshr.u64 d24,d16,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d23 vshr.u64 d25,d16,#34 vsli.64 d24,d16,#36 vadd.i64 d27,d26 vshr.u64 d26,d16,#39 vadd.i64 d28,d0 vsli.64 d25,d16,#30 veor d30,d16,d17 vsli.64 d26,d16,#25 veor d23,d24,d25 vadd.i64 d27,d28 vbsl d30,d18,d17 @ Maj(a,b,c) veor d23,d26 @ Sigma0(a) vadd.i64 d19,d27 vadd.i64 d30,d27 @ vadd.i64 d23,d30 vshr.u64 d24,d19,#14 @ 17 #if 17<16 vld1.64 {d1},[r1]! @ handles unaligned #endif vshr.u64 d25,d19,#18 #if 17>0 vadd.i64 d23,d30 @ h+=Maj from the past #endif vshr.u64 d26,d19,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d19,#50 vsli.64 d25,d19,#46 vmov d29,d19 vsli.64 d26,d19,#23 #if 17<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d20,d21 @ Ch(e,f,g) vshr.u64 d24,d23,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d22 vshr.u64 d25,d23,#34 vsli.64 d24,d23,#36 vadd.i64 d27,d26 vshr.u64 d26,d23,#39 vadd.i64 d28,d1 vsli.64 d25,d23,#30 veor d30,d23,d16 vsli.64 d26,d23,#25 veor d22,d24,d25 vadd.i64 d27,d28 vbsl d30,d17,d16 @ Maj(a,b,c) veor d22,d26 @ Sigma0(a) vadd.i64 d18,d27 vadd.i64 d30,d27 @ vadd.i64 d22,d30 vshr.u64 q12,q0,#19 vshr.u64 q13,q0,#61 vadd.i64 d22,d30 @ h+=Maj from the past vshr.u64 q15,q0,#6 vsli.64 q12,q0,#45 vext.8 q14,q1,q2,#8 @ X[i+1] vsli.64 q13,q0,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q1,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q5,q6,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d18,#14 @ from NEON_00_15 vadd.i64 q1,q14 vshr.u64 d25,d18,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d18,#41 @ from NEON_00_15 vadd.i64 q1,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d18,#50 vsli.64 d25,d18,#46 vmov d29,d18 vsli.64 d26,d18,#23 #if 18<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d19,d20 @ Ch(e,f,g) vshr.u64 d24,d22,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d21 vshr.u64 d25,d22,#34 vsli.64 d24,d22,#36 vadd.i64 d27,d26 vshr.u64 d26,d22,#39 vadd.i64 d28,d2 vsli.64 d25,d22,#30 veor d30,d22,d23 vsli.64 d26,d22,#25 veor d21,d24,d25 vadd.i64 d27,d28 vbsl d30,d16,d23 @ Maj(a,b,c) veor d21,d26 @ Sigma0(a) vadd.i64 d17,d27 vadd.i64 d30,d27 @ vadd.i64 d21,d30 vshr.u64 d24,d17,#14 @ 19 #if 19<16 vld1.64 {d3},[r1]! @ handles unaligned #endif vshr.u64 d25,d17,#18 #if 19>0 vadd.i64 d21,d30 @ h+=Maj from the past #endif vshr.u64 d26,d17,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d17,#50 vsli.64 d25,d17,#46 vmov d29,d17 vsli.64 d26,d17,#23 #if 19<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d18,d19 @ Ch(e,f,g) vshr.u64 d24,d21,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d20 vshr.u64 d25,d21,#34 vsli.64 d24,d21,#36 vadd.i64 d27,d26 vshr.u64 d26,d21,#39 vadd.i64 d28,d3 vsli.64 d25,d21,#30 veor d30,d21,d22 vsli.64 d26,d21,#25 veor d20,d24,d25 vadd.i64 d27,d28 vbsl d30,d23,d22 @ Maj(a,b,c) veor d20,d26 @ Sigma0(a) vadd.i64 d16,d27 vadd.i64 d30,d27 @ vadd.i64 d20,d30 vshr.u64 q12,q1,#19 vshr.u64 q13,q1,#61 vadd.i64 d20,d30 @ h+=Maj from the past vshr.u64 q15,q1,#6 vsli.64 q12,q1,#45 vext.8 q14,q2,q3,#8 @ X[i+1] vsli.64 q13,q1,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q2,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q6,q7,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d16,#14 @ from NEON_00_15 vadd.i64 q2,q14 vshr.u64 d25,d16,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d16,#41 @ from NEON_00_15 vadd.i64 q2,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d16,#50 vsli.64 d25,d16,#46 vmov d29,d16 vsli.64 d26,d16,#23 #if 20<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d17,d18 @ Ch(e,f,g) vshr.u64 d24,d20,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d19 vshr.u64 d25,d20,#34 vsli.64 d24,d20,#36 vadd.i64 d27,d26 vshr.u64 d26,d20,#39 vadd.i64 d28,d4 vsli.64 d25,d20,#30 veor d30,d20,d21 vsli.64 d26,d20,#25 veor d19,d24,d25 vadd.i64 d27,d28 vbsl d30,d22,d21 @ Maj(a,b,c) veor d19,d26 @ Sigma0(a) vadd.i64 d23,d27 vadd.i64 d30,d27 @ vadd.i64 d19,d30 vshr.u64 d24,d23,#14 @ 21 #if 21<16 vld1.64 {d5},[r1]! @ handles unaligned #endif vshr.u64 d25,d23,#18 #if 21>0 vadd.i64 d19,d30 @ h+=Maj from the past #endif vshr.u64 d26,d23,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d23,#50 vsli.64 d25,d23,#46 vmov d29,d23 vsli.64 d26,d23,#23 #if 21<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d16,d17 @ Ch(e,f,g) vshr.u64 d24,d19,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d18 vshr.u64 d25,d19,#34 vsli.64 d24,d19,#36 vadd.i64 d27,d26 vshr.u64 d26,d19,#39 vadd.i64 d28,d5 vsli.64 d25,d19,#30 veor d30,d19,d20 vsli.64 d26,d19,#25 veor d18,d24,d25 vadd.i64 d27,d28 vbsl d30,d21,d20 @ Maj(a,b,c) veor d18,d26 @ Sigma0(a) vadd.i64 d22,d27 vadd.i64 d30,d27 @ vadd.i64 d18,d30 vshr.u64 q12,q2,#19 vshr.u64 q13,q2,#61 vadd.i64 d18,d30 @ h+=Maj from the past vshr.u64 q15,q2,#6 vsli.64 q12,q2,#45 vext.8 q14,q3,q4,#8 @ X[i+1] vsli.64 q13,q2,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q3,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q7,q0,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d22,#14 @ from NEON_00_15 vadd.i64 q3,q14 vshr.u64 d25,d22,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d22,#41 @ from NEON_00_15 vadd.i64 q3,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d22,#50 vsli.64 d25,d22,#46 vmov d29,d22 vsli.64 d26,d22,#23 #if 22<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d23,d16 @ Ch(e,f,g) vshr.u64 d24,d18,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d17 vshr.u64 d25,d18,#34 vsli.64 d24,d18,#36 vadd.i64 d27,d26 vshr.u64 d26,d18,#39 vadd.i64 d28,d6 vsli.64 d25,d18,#30 veor d30,d18,d19 vsli.64 d26,d18,#25 veor d17,d24,d25 vadd.i64 d27,d28 vbsl d30,d20,d19 @ Maj(a,b,c) veor d17,d26 @ Sigma0(a) vadd.i64 d21,d27 vadd.i64 d30,d27 @ vadd.i64 d17,d30 vshr.u64 d24,d21,#14 @ 23 #if 23<16 vld1.64 {d7},[r1]! @ handles unaligned #endif vshr.u64 d25,d21,#18 #if 23>0 vadd.i64 d17,d30 @ h+=Maj from the past #endif vshr.u64 d26,d21,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d21,#50 vsli.64 d25,d21,#46 vmov d29,d21 vsli.64 d26,d21,#23 #if 23<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d22,d23 @ Ch(e,f,g) vshr.u64 d24,d17,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d16 vshr.u64 d25,d17,#34 vsli.64 d24,d17,#36 vadd.i64 d27,d26 vshr.u64 d26,d17,#39 vadd.i64 d28,d7 vsli.64 d25,d17,#30 veor d30,d17,d18 vsli.64 d26,d17,#25 veor d16,d24,d25 vadd.i64 d27,d28 vbsl d30,d19,d18 @ Maj(a,b,c) veor d16,d26 @ Sigma0(a) vadd.i64 d20,d27 vadd.i64 d30,d27 @ vadd.i64 d16,d30 vshr.u64 q12,q3,#19 vshr.u64 q13,q3,#61 vadd.i64 d16,d30 @ h+=Maj from the past vshr.u64 q15,q3,#6 vsli.64 q12,q3,#45 vext.8 q14,q4,q5,#8 @ X[i+1] vsli.64 q13,q3,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q4,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q0,q1,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d20,#14 @ from NEON_00_15 vadd.i64 q4,q14 vshr.u64 d25,d20,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d20,#41 @ from NEON_00_15 vadd.i64 q4,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d20,#50 vsli.64 d25,d20,#46 vmov d29,d20 vsli.64 d26,d20,#23 #if 24<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d21,d22 @ Ch(e,f,g) vshr.u64 d24,d16,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d23 vshr.u64 d25,d16,#34 vsli.64 d24,d16,#36 vadd.i64 d27,d26 vshr.u64 d26,d16,#39 vadd.i64 d28,d8 vsli.64 d25,d16,#30 veor d30,d16,d17 vsli.64 d26,d16,#25 veor d23,d24,d25 vadd.i64 d27,d28 vbsl d30,d18,d17 @ Maj(a,b,c) veor d23,d26 @ Sigma0(a) vadd.i64 d19,d27 vadd.i64 d30,d27 @ vadd.i64 d23,d30 vshr.u64 d24,d19,#14 @ 25 #if 25<16 vld1.64 {d9},[r1]! @ handles unaligned #endif vshr.u64 d25,d19,#18 #if 25>0 vadd.i64 d23,d30 @ h+=Maj from the past #endif vshr.u64 d26,d19,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d19,#50 vsli.64 d25,d19,#46 vmov d29,d19 vsli.64 d26,d19,#23 #if 25<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d20,d21 @ Ch(e,f,g) vshr.u64 d24,d23,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d22 vshr.u64 d25,d23,#34 vsli.64 d24,d23,#36 vadd.i64 d27,d26 vshr.u64 d26,d23,#39 vadd.i64 d28,d9 vsli.64 d25,d23,#30 veor d30,d23,d16 vsli.64 d26,d23,#25 veor d22,d24,d25 vadd.i64 d27,d28 vbsl d30,d17,d16 @ Maj(a,b,c) veor d22,d26 @ Sigma0(a) vadd.i64 d18,d27 vadd.i64 d30,d27 @ vadd.i64 d22,d30 vshr.u64 q12,q4,#19 vshr.u64 q13,q4,#61 vadd.i64 d22,d30 @ h+=Maj from the past vshr.u64 q15,q4,#6 vsli.64 q12,q4,#45 vext.8 q14,q5,q6,#8 @ X[i+1] vsli.64 q13,q4,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q5,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q1,q2,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d18,#14 @ from NEON_00_15 vadd.i64 q5,q14 vshr.u64 d25,d18,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d18,#41 @ from NEON_00_15 vadd.i64 q5,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d18,#50 vsli.64 d25,d18,#46 vmov d29,d18 vsli.64 d26,d18,#23 #if 26<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d19,d20 @ Ch(e,f,g) vshr.u64 d24,d22,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d21 vshr.u64 d25,d22,#34 vsli.64 d24,d22,#36 vadd.i64 d27,d26 vshr.u64 d26,d22,#39 vadd.i64 d28,d10 vsli.64 d25,d22,#30 veor d30,d22,d23 vsli.64 d26,d22,#25 veor d21,d24,d25 vadd.i64 d27,d28 vbsl d30,d16,d23 @ Maj(a,b,c) veor d21,d26 @ Sigma0(a) vadd.i64 d17,d27 vadd.i64 d30,d27 @ vadd.i64 d21,d30 vshr.u64 d24,d17,#14 @ 27 #if 27<16 vld1.64 {d11},[r1]! @ handles unaligned #endif vshr.u64 d25,d17,#18 #if 27>0 vadd.i64 d21,d30 @ h+=Maj from the past #endif vshr.u64 d26,d17,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d17,#50 vsli.64 d25,d17,#46 vmov d29,d17 vsli.64 d26,d17,#23 #if 27<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d18,d19 @ Ch(e,f,g) vshr.u64 d24,d21,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d20 vshr.u64 d25,d21,#34 vsli.64 d24,d21,#36 vadd.i64 d27,d26 vshr.u64 d26,d21,#39 vadd.i64 d28,d11 vsli.64 d25,d21,#30 veor d30,d21,d22 vsli.64 d26,d21,#25 veor d20,d24,d25 vadd.i64 d27,d28 vbsl d30,d23,d22 @ Maj(a,b,c) veor d20,d26 @ Sigma0(a) vadd.i64 d16,d27 vadd.i64 d30,d27 @ vadd.i64 d20,d30 vshr.u64 q12,q5,#19 vshr.u64 q13,q5,#61 vadd.i64 d20,d30 @ h+=Maj from the past vshr.u64 q15,q5,#6 vsli.64 q12,q5,#45 vext.8 q14,q6,q7,#8 @ X[i+1] vsli.64 q13,q5,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q6,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q2,q3,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d16,#14 @ from NEON_00_15 vadd.i64 q6,q14 vshr.u64 d25,d16,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d16,#41 @ from NEON_00_15 vadd.i64 q6,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d16,#50 vsli.64 d25,d16,#46 vmov d29,d16 vsli.64 d26,d16,#23 #if 28<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d17,d18 @ Ch(e,f,g) vshr.u64 d24,d20,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d19 vshr.u64 d25,d20,#34 vsli.64 d24,d20,#36 vadd.i64 d27,d26 vshr.u64 d26,d20,#39 vadd.i64 d28,d12 vsli.64 d25,d20,#30 veor d30,d20,d21 vsli.64 d26,d20,#25 veor d19,d24,d25 vadd.i64 d27,d28 vbsl d30,d22,d21 @ Maj(a,b,c) veor d19,d26 @ Sigma0(a) vadd.i64 d23,d27 vadd.i64 d30,d27 @ vadd.i64 d19,d30 vshr.u64 d24,d23,#14 @ 29 #if 29<16 vld1.64 {d13},[r1]! @ handles unaligned #endif vshr.u64 d25,d23,#18 #if 29>0 vadd.i64 d19,d30 @ h+=Maj from the past #endif vshr.u64 d26,d23,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d23,#50 vsli.64 d25,d23,#46 vmov d29,d23 vsli.64 d26,d23,#23 #if 29<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d16,d17 @ Ch(e,f,g) vshr.u64 d24,d19,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d18 vshr.u64 d25,d19,#34 vsli.64 d24,d19,#36 vadd.i64 d27,d26 vshr.u64 d26,d19,#39 vadd.i64 d28,d13 vsli.64 d25,d19,#30 veor d30,d19,d20 vsli.64 d26,d19,#25 veor d18,d24,d25 vadd.i64 d27,d28 vbsl d30,d21,d20 @ Maj(a,b,c) veor d18,d26 @ Sigma0(a) vadd.i64 d22,d27 vadd.i64 d30,d27 @ vadd.i64 d18,d30 vshr.u64 q12,q6,#19 vshr.u64 q13,q6,#61 vadd.i64 d18,d30 @ h+=Maj from the past vshr.u64 q15,q6,#6 vsli.64 q12,q6,#45 vext.8 q14,q7,q0,#8 @ X[i+1] vsli.64 q13,q6,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q7,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q3,q4,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d22,#14 @ from NEON_00_15 vadd.i64 q7,q14 vshr.u64 d25,d22,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d22,#41 @ from NEON_00_15 vadd.i64 q7,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d22,#50 vsli.64 d25,d22,#46 vmov d29,d22 vsli.64 d26,d22,#23 #if 30<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d23,d16 @ Ch(e,f,g) vshr.u64 d24,d18,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d17 vshr.u64 d25,d18,#34 vsli.64 d24,d18,#36 vadd.i64 d27,d26 vshr.u64 d26,d18,#39 vadd.i64 d28,d14 vsli.64 d25,d18,#30 veor d30,d18,d19 vsli.64 d26,d18,#25 veor d17,d24,d25 vadd.i64 d27,d28 vbsl d30,d20,d19 @ Maj(a,b,c) veor d17,d26 @ Sigma0(a) vadd.i64 d21,d27 vadd.i64 d30,d27 @ vadd.i64 d17,d30 vshr.u64 d24,d21,#14 @ 31 #if 31<16 vld1.64 {d15},[r1]! @ handles unaligned #endif vshr.u64 d25,d21,#18 #if 31>0 vadd.i64 d17,d30 @ h+=Maj from the past #endif vshr.u64 d26,d21,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d21,#50 vsli.64 d25,d21,#46 vmov d29,d21 vsli.64 d26,d21,#23 #if 31<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d22,d23 @ Ch(e,f,g) vshr.u64 d24,d17,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d16 vshr.u64 d25,d17,#34 vsli.64 d24,d17,#36 vadd.i64 d27,d26 vshr.u64 d26,d17,#39 vadd.i64 d28,d15 vsli.64 d25,d17,#30 veor d30,d17,d18 vsli.64 d26,d17,#25 veor d16,d24,d25 vadd.i64 d27,d28 vbsl d30,d19,d18 @ Maj(a,b,c) veor d16,d26 @ Sigma0(a) vadd.i64 d20,d27 vadd.i64 d30,d27 @ vadd.i64 d16,d30 bne .L16_79_neon vadd.i64 d16,d30 @ h+=Maj from the past vldmia r0,{d24,d25,d26,d27,d28,d29,d30,d31} @ load context to temp vadd.i64 q8,q12 @ vectorized accumulate vadd.i64 q9,q13 vadd.i64 q10,q14 vadd.i64 q11,q15 vstmia r0,{d16,d17,d18,d19,d20,d21,d22,d23} @ save context teq r1,r2 sub r3,#640 @ rewind K512 bne .Loop_neon VFP_ABI_POP bx lr @ .word 0xe12fff1e .size sha512_block_data_order_neon,.-sha512_block_data_order_neon #endif .byte 83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 .align 2 #endif // !OPENSSL_NO_ASM && defined(OPENSSL_ARM) && defined(__ELF__)
j4yc3-mw/Viren	35,688	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/p256-armv8-asm-win64.S	// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32) #include "ring-core/arm_arch.h" .section .rodata .align 5 Lpoly: .quad 0xffffffffffffffff,0x00000000ffffffff,0x0000000000000000,0xffffffff00000001 LRR: // 2^512 mod P precomputed for NIST P256 polynomial .quad 0x0000000000000003,0xfffffffbffffffff,0xfffffffffffffffe,0x00000004fffffffd Lone_mont: .quad 0x0000000000000001,0xffffffff00000000,0xffffffffffffffff,0x00000000fffffffe Lone: .quad 1,0,0,0 Lord: .quad 0xf3b9cac2fc632551,0xbce6faada7179e84,0xffffffffffffffff,0xffffffff00000000 LordK: .quad 0xccd1c8aaee00bc4f .byte 69,67,80,95,78,73,83,84,90,50,53,54,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 .align 2 .text // void ecp_nistz256_mul_mont(BN_ULONG x0[4],const BN_ULONG x1[4], // const BN_ULONG x2[4]); .globl ecp_nistz256_mul_mont .def ecp_nistz256_mul_mont .type 32 .endef .align 4 ecp_nistz256_mul_mont: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-32]! add x29,sp,#0 stp x19,x20,[sp,#16] ldr x3,[x2] // bp[0] ldp x4,x5,[x1] ldp x6,x7,[x1,#16] adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] ldr x13,[x13,#24] bl __ecp_nistz256_mul_mont ldp x19,x20,[sp,#16] ldp x29,x30,[sp],#32 AARCH64_VALIDATE_LINK_REGISTER ret // void ecp_nistz256_sqr_mont(BN_ULONG x0[4],const BN_ULONG x1[4]); .globl ecp_nistz256_sqr_mont .def ecp_nistz256_sqr_mont .type 32 .endef .align 4 ecp_nistz256_sqr_mont: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-32]! add x29,sp,#0 stp x19,x20,[sp,#16] ldp x4,x5,[x1] ldp x6,x7,[x1,#16] adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] ldr x13,[x13,#24] bl __ecp_nistz256_sqr_mont ldp x19,x20,[sp,#16] ldp x29,x30,[sp],#32 AARCH64_VALIDATE_LINK_REGISTER ret // void ecp_nistz256_neg(BN_ULONG x0[4],const BN_ULONG x1[4]); .globl ecp_nistz256_neg .def ecp_nistz256_neg .type 32 .endef .align 4 ecp_nistz256_neg: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-16]! add x29,sp,#0 mov x2,x1 mov x14,xzr // a = 0 mov x15,xzr mov x16,xzr mov x17,xzr adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] ldr x13,[x13,#24] bl __ecp_nistz256_sub_from ldp x29,x30,[sp],#16 AARCH64_VALIDATE_LINK_REGISTER ret // note that __ecp_nistz256_mul_mont expects a[0-3] input pre-loaded // to x4-x7 and b[0] - to x3 .def __ecp_nistz256_mul_mont .type 32 .endef .align 4 __ecp_nistz256_mul_mont: mul x14,x4,x3 // a[0]b[0] umulh x8,x4,x3 mul x15,x5,x3 // a[1]b[0] umulh x9,x5,x3 mul x16,x6,x3 // a[2]b[0] umulh x10,x6,x3 mul x17,x7,x3 // a[3]b[0] umulh x11,x7,x3 ldr x3,[x2,#8] // b[1] adds x15,x15,x8 // accumulate high parts of multiplication lsl x8,x14,#32 adcs x16,x16,x9 lsr x9,x14,#32 adcs x17,x17,x10 adc x19,xzr,x11 mov x20,xzr subs x10,x14,x8 // "0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] mul x8,x4,x3 // lo(a[0]b[i]) adcs x15,x16,x9 mul x9,x5,x3 // lo(a[1]b[i]) adcs x16,x17,x10 // +=acc[0]0xffff0001 mul x10,x6,x3 // lo(a[2]b[i]) adcs x17,x19,x11 mul x11,x7,x3 // lo(a[3]b[i]) adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts of multiplication umulh x8,x4,x3 // hi(a[0]b[i]) adcs x15,x15,x9 umulh x9,x5,x3 // hi(a[1]b[i]) adcs x16,x16,x10 umulh x10,x6,x3 // hi(a[2]b[i]) adcs x17,x17,x11 umulh x11,x7,x3 // hi(a[3]b[i]) adc x19,x19,xzr ldr x3,[x2,#8(1+1)] // b[1+1] adds x15,x15,x8 // accumulate high parts of multiplication lsl x8,x14,#32 adcs x16,x16,x9 lsr x9,x14,#32 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr subs x10,x14,x8 // "0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] mul x8,x4,x3 // lo(a[0]b[i]) adcs x15,x16,x9 mul x9,x5,x3 // lo(a[1]b[i]) adcs x16,x17,x10 // +=acc[0]0xffff0001 mul x10,x6,x3 // lo(a[2]b[i]) adcs x17,x19,x11 mul x11,x7,x3 // lo(a[3]b[i]) adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts of multiplication umulh x8,x4,x3 // hi(a[0]b[i]) adcs x15,x15,x9 umulh x9,x5,x3 // hi(a[1]b[i]) adcs x16,x16,x10 umulh x10,x6,x3 // hi(a[2]b[i]) adcs x17,x17,x11 umulh x11,x7,x3 // hi(a[3]b[i]) adc x19,x19,xzr ldr x3,[x2,#8(2+1)] // b[2+1] adds x15,x15,x8 // accumulate high parts of multiplication lsl x8,x14,#32 adcs x16,x16,x9 lsr x9,x14,#32 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr subs x10,x14,x8 // "0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] mul x8,x4,x3 // lo(a[0]b[i]) adcs x15,x16,x9 mul x9,x5,x3 // lo(a[1]b[i]) adcs x16,x17,x10 // +=acc[0]0xffff0001 mul x10,x6,x3 // lo(a[2]b[i]) adcs x17,x19,x11 mul x11,x7,x3 // lo(a[3]b[i]) adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts of multiplication umulh x8,x4,x3 // hi(a[0]b[i]) adcs x15,x15,x9 umulh x9,x5,x3 // hi(a[1]b[i]) adcs x16,x16,x10 umulh x10,x6,x3 // hi(a[2]b[i]) adcs x17,x17,x11 umulh x11,x7,x3 // hi(a[3]b[i]) adc x19,x19,xzr adds x15,x15,x8 // accumulate high parts of multiplication lsl x8,x14,#32 adcs x16,x16,x9 lsr x9,x14,#32 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr // last reduction subs x10,x14,x8 // "0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] adcs x15,x16,x9 adcs x16,x17,x10 // +=acc[0]0xffff0001 adcs x17,x19,x11 adc x19,x20,xzr adds x8,x14,#1 // subs x8,x14,#-1 // tmp = ret-modulus sbcs x9,x15,x12 sbcs x10,x16,xzr sbcs x11,x17,x13 sbcs xzr,x19,xzr // did it borrow? csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus csel x15,x15,x9,lo csel x16,x16,x10,lo stp x14,x15,[x0] csel x17,x17,x11,lo stp x16,x17,[x0,#16] ret // note that __ecp_nistz256_sqr_mont expects a[0-3] input pre-loaded // to x4-x7 .def __ecp_nistz256_sqr_mont .type 32 .endef .align 4 __ecp_nistz256_sqr_mont: // \| \| \| \| \| \|a1a0\| \| // \| \| \| \| \|a2a0\| \| \| // \| \|a3a2\|a3a0\| \| \| \| // \| \| \| \|a2a1\| \| \| \| // \| \| \|a3a1\| \| \| \| \| // \| \| \| \| \| \| \| \| 2\| // +\|a3a3\|a2a2\|a1a1\|a0a0\| // \|--+--+--+--+--+--+--+--\| // \|A7\|A6\|A5\|A4\|A3\|A2\|A1\|A0\|, where Ax is , i.e. follow // // "can't overflow" below mark carrying into high part of // multiplication result, which can't overflow, because it // can never be all ones. mul x15,x5,x4 // a[1]a[0] umulh x9,x5,x4 mul x16,x6,x4 // a[2]a[0] umulh x10,x6,x4 mul x17,x7,x4 // a[3]a[0] umulh x19,x7,x4 adds x16,x16,x9 // accumulate high parts of multiplication mul x8,x6,x5 // a[2]a[1] umulh x9,x6,x5 adcs x17,x17,x10 mul x10,x7,x5 // a[3]a[1] umulh x11,x7,x5 adc x19,x19,xzr // can't overflow mul x20,x7,x6 // a[3]a[2] umulh x1,x7,x6 adds x9,x9,x10 // accumulate high parts of multiplication mul x14,x4,x4 // a[0]a[0] adc x10,x11,xzr // can't overflow adds x17,x17,x8 // accumulate low parts of multiplication umulh x4,x4,x4 adcs x19,x19,x9 mul x9,x5,x5 // a[1]a[1] adcs x20,x20,x10 umulh x5,x5,x5 adc x1,x1,xzr // can't overflow adds x15,x15,x15 // acc[1-6]=2 mul x10,x6,x6 // a[2]a[2] adcs x16,x16,x16 umulh x6,x6,x6 adcs x17,x17,x17 mul x11,x7,x7 // a[3]a[3] adcs x19,x19,x19 umulh x7,x7,x7 adcs x20,x20,x20 adcs x1,x1,x1 adc x2,xzr,xzr adds x15,x15,x4 // +a[i]a[i] adcs x16,x16,x9 adcs x17,x17,x5 adcs x19,x19,x10 adcs x20,x20,x6 lsl x8,x14,#32 adcs x1,x1,x11 lsr x9,x14,#32 adc x2,x2,x7 subs x10,x14,x8 // "0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] adcs x15,x16,x9 lsl x8,x14,#32 adcs x16,x17,x10 // +=acc[0]0xffff0001 lsr x9,x14,#32 adc x17,x11,xzr // can't overflow subs x10,x14,x8 // "0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] adcs x15,x16,x9 lsl x8,x14,#32 adcs x16,x17,x10 // +=acc[0]0xffff0001 lsr x9,x14,#32 adc x17,x11,xzr // can't overflow subs x10,x14,x8 // "0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] adcs x15,x16,x9 lsl x8,x14,#32 adcs x16,x17,x10 // +=acc[0]0xffff0001 lsr x9,x14,#32 adc x17,x11,xzr // can't overflow subs x10,x14,x8 // "0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] adcs x15,x16,x9 adcs x16,x17,x10 // +=acc[0]0xffff0001 adc x17,x11,xzr // can't overflow adds x14,x14,x19 // accumulate upper half adcs x15,x15,x20 adcs x16,x16,x1 adcs x17,x17,x2 adc x19,xzr,xzr adds x8,x14,#1 // subs x8,x14,#-1 // tmp = ret-modulus sbcs x9,x15,x12 sbcs x10,x16,xzr sbcs x11,x17,x13 sbcs xzr,x19,xzr // did it borrow? csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus csel x15,x15,x9,lo csel x16,x16,x10,lo stp x14,x15,[x0] csel x17,x17,x11,lo stp x16,x17,[x0,#16] ret // Note that __ecp_nistz256_add_to expects both input vectors pre-loaded to // x4-x7 and x8-x11. This is done because it's used in multiple // contexts, e.g. in multiplication by 2 and 3... .def __ecp_nistz256_add_to .type 32 .endef .align 4 __ecp_nistz256_add_to: adds x14,x14,x8 // ret = a+b adcs x15,x15,x9 adcs x16,x16,x10 adcs x17,x17,x11 adc x1,xzr,xzr // zap x1 adds x8,x14,#1 // subs x8,x4,#-1 // tmp = ret-modulus sbcs x9,x15,x12 sbcs x10,x16,xzr sbcs x11,x17,x13 sbcs xzr,x1,xzr // did subtraction borrow? csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus csel x15,x15,x9,lo csel x16,x16,x10,lo stp x14,x15,[x0] csel x17,x17,x11,lo stp x16,x17,[x0,#16] ret .def __ecp_nistz256_sub_from .type 32 .endef .align 4 __ecp_nistz256_sub_from: ldp x8,x9,[x2] ldp x10,x11,[x2,#16] subs x14,x14,x8 // ret = a-b sbcs x15,x15,x9 sbcs x16,x16,x10 sbcs x17,x17,x11 sbc x1,xzr,xzr // zap x1 subs x8,x14,#1 // adds x8,x4,#-1 // tmp = ret+modulus adcs x9,x15,x12 adcs x10,x16,xzr adc x11,x17,x13 cmp x1,xzr // did subtraction borrow? csel x14,x14,x8,eq // ret = borrow ? ret+modulus : ret csel x15,x15,x9,eq csel x16,x16,x10,eq stp x14,x15,[x0] csel x17,x17,x11,eq stp x16,x17,[x0,#16] ret .def __ecp_nistz256_sub_morf .type 32 .endef .align 4 __ecp_nistz256_sub_morf: ldp x8,x9,[x2] ldp x10,x11,[x2,#16] subs x14,x8,x14 // ret = b-a sbcs x15,x9,x15 sbcs x16,x10,x16 sbcs x17,x11,x17 sbc x1,xzr,xzr // zap x1 subs x8,x14,#1 // adds x8,x4,#-1 // tmp = ret+modulus adcs x9,x15,x12 adcs x10,x16,xzr adc x11,x17,x13 cmp x1,xzr // did subtraction borrow? csel x14,x14,x8,eq // ret = borrow ? ret+modulus : ret csel x15,x15,x9,eq csel x16,x16,x10,eq stp x14,x15,[x0] csel x17,x17,x11,eq stp x16,x17,[x0,#16] ret .def __ecp_nistz256_div_by_2 .type 32 .endef .align 4 __ecp_nistz256_div_by_2: subs x8,x14,#1 // adds x8,x4,#-1 // tmp = a+modulus adcs x9,x15,x12 adcs x10,x16,xzr adcs x11,x17,x13 adc x1,xzr,xzr // zap x1 tst x14,#1 // is a even? csel x14,x14,x8,eq // ret = even ? a : a+modulus csel x15,x15,x9,eq csel x16,x16,x10,eq csel x17,x17,x11,eq csel x1,xzr,x1,eq lsr x14,x14,#1 // ret >>= 1 orr x14,x14,x15,lsl#63 lsr x15,x15,#1 orr x15,x15,x16,lsl#63 lsr x16,x16,#1 orr x16,x16,x17,lsl#63 lsr x17,x17,#1 stp x14,x15,[x0] orr x17,x17,x1,lsl#63 stp x16,x17,[x0,#16] ret .globl ecp_nistz256_point_double .def ecp_nistz256_point_double .type 32 .endef .align 5 ecp_nistz256_point_double: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-96]! add x29,sp,#0 stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] sub sp,sp,#324 Ldouble_shortcut: ldp x14,x15,[x1,#32] mov x21,x0 ldp x16,x17,[x1,#48] mov x22,x1 adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] mov x8,x14 ldr x13,[x13,#24] mov x9,x15 ldp x4,x5,[x22,#64] // forward load for p256_sqr_mont mov x10,x16 mov x11,x17 ldp x6,x7,[x22,#64+16] add x0,sp,#0 bl __ecp_nistz256_add_to // p256_mul_by_2(S, in_y); add x0,sp,#64 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Zsqr, in_z); ldp x8,x9,[x22] ldp x10,x11,[x22,#16] mov x4,x14 // put Zsqr aside for p256_sub mov x5,x15 mov x6,x16 mov x7,x17 add x0,sp,#32 bl __ecp_nistz256_add_to // p256_add(M, Zsqr, in_x); add x2,x22,#0 mov x14,x4 // restore Zsqr mov x15,x5 ldp x4,x5,[sp,#0] // forward load for p256_sqr_mont mov x16,x6 mov x17,x7 ldp x6,x7,[sp,#0+16] add x0,sp,#64 bl __ecp_nistz256_sub_morf // p256_sub(Zsqr, in_x, Zsqr); add x0,sp,#0 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(S, S); ldr x3,[x22,#32] ldp x4,x5,[x22,#64] ldp x6,x7,[x22,#64+16] add x2,x22,#32 add x0,sp,#96 bl __ecp_nistz256_mul_mont // p256_mul_mont(tmp0, in_z, in_y); mov x8,x14 mov x9,x15 ldp x4,x5,[sp,#0] // forward load for p256_sqr_mont mov x10,x16 mov x11,x17 ldp x6,x7,[sp,#0+16] add x0,x21,#64 bl __ecp_nistz256_add_to // p256_mul_by_2(res_z, tmp0); add x0,sp,#96 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(tmp0, S); ldr x3,[sp,#64] // forward load for p256_mul_mont ldp x4,x5,[sp,#32] ldp x6,x7,[sp,#32+16] add x0,x21,#32 bl __ecp_nistz256_div_by_2 // p256_div_by_2(res_y, tmp0); add x2,sp,#64 add x0,sp,#32 bl __ecp_nistz256_mul_mont // p256_mul_mont(M, M, Zsqr); mov x8,x14 // duplicate M mov x9,x15 mov x10,x16 mov x11,x17 mov x4,x14 // put M aside mov x5,x15 mov x6,x16 mov x7,x17 add x0,sp,#32 bl __ecp_nistz256_add_to mov x8,x4 // restore M mov x9,x5 ldr x3,[x22] // forward load for p256_mul_mont mov x10,x6 ldp x4,x5,[sp,#0] mov x11,x7 ldp x6,x7,[sp,#0+16] bl __ecp_nistz256_add_to // p256_mul_by_3(M, M); add x2,x22,#0 add x0,sp,#0 bl __ecp_nistz256_mul_mont // p256_mul_mont(S, S, in_x); mov x8,x14 mov x9,x15 ldp x4,x5,[sp,#32] // forward load for p256_sqr_mont mov x10,x16 mov x11,x17 ldp x6,x7,[sp,#32+16] add x0,sp,#96 bl __ecp_nistz256_add_to // p256_mul_by_2(tmp0, S); add x0,x21,#0 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(res_x, M); add x2,sp,#96 bl __ecp_nistz256_sub_from // p256_sub(res_x, res_x, tmp0); add x2,sp,#0 add x0,sp,#0 bl __ecp_nistz256_sub_morf // p256_sub(S, S, res_x); ldr x3,[sp,#32] mov x4,x14 // copy S mov x5,x15 mov x6,x16 mov x7,x17 add x2,sp,#32 bl __ecp_nistz256_mul_mont // p256_mul_mont(S, S, M); add x2,x21,#32 add x0,x21,#32 bl __ecp_nistz256_sub_from // p256_sub(res_y, S, res_y); add sp,x29,#0 // destroy frame ldp x19,x20,[x29,#16] ldp x21,x22,[x29,#32] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret .globl ecp_nistz256_point_add .def ecp_nistz256_point_add .type 32 .endef .align 5 ecp_nistz256_point_add: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-96]! add x29,sp,#0 stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] stp x25,x26,[sp,#64] stp x27,x28,[sp,#80] sub sp,sp,#3212 ldp x4,x5,[x2,#64] // in2_z ldp x6,x7,[x2,#64+16] mov x21,x0 mov x22,x1 mov x23,x2 adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] ldr x13,[x13,#24] orr x8,x4,x5 orr x10,x6,x7 orr x25,x8,x10 cmp x25,#0 csetm x25,ne // ~in2infty add x0,sp,#192 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Z2sqr, in2_z); ldp x4,x5,[x22,#64] // in1_z ldp x6,x7,[x22,#64+16] orr x8,x4,x5 orr x10,x6,x7 orr x24,x8,x10 cmp x24,#0 csetm x24,ne // ~in1infty add x0,sp,#128 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Z1sqr, in1_z); ldr x3,[x23,#64] ldp x4,x5,[sp,#192] ldp x6,x7,[sp,#192+16] add x2,x23,#64 add x0,sp,#320 bl __ecp_nistz256_mul_mont // p256_mul_mont(S1, Z2sqr, in2_z); ldr x3,[x22,#64] ldp x4,x5,[sp,#128] ldp x6,x7,[sp,#128+16] add x2,x22,#64 add x0,sp,#352 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, Z1sqr, in1_z); ldr x3,[x22,#32] ldp x4,x5,[sp,#320] ldp x6,x7,[sp,#320+16] add x2,x22,#32 add x0,sp,#320 bl __ecp_nistz256_mul_mont // p256_mul_mont(S1, S1, in1_y); ldr x3,[x23,#32] ldp x4,x5,[sp,#352] ldp x6,x7,[sp,#352+16] add x2,x23,#32 add x0,sp,#352 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, S2, in2_y); add x2,sp,#320 ldr x3,[sp,#192] // forward load for p256_mul_mont ldp x4,x5,[x22] ldp x6,x7,[x22,#16] add x0,sp,#160 bl __ecp_nistz256_sub_from // p256_sub(R, S2, S1); orr x14,x14,x15 // see if result is zero orr x16,x16,x17 orr x26,x14,x16 // ~is_equal(S1,S2) add x2,sp,#192 add x0,sp,#256 bl __ecp_nistz256_mul_mont // p256_mul_mont(U1, in1_x, Z2sqr); ldr x3,[sp,#128] ldp x4,x5,[x23] ldp x6,x7,[x23,#16] add x2,sp,#128 add x0,sp,#288 bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, in2_x, Z1sqr); add x2,sp,#256 ldp x4,x5,[sp,#160] // forward load for p256_sqr_mont ldp x6,x7,[sp,#160+16] add x0,sp,#96 bl __ecp_nistz256_sub_from // p256_sub(H, U2, U1); orr x14,x14,x15 // see if result is zero orr x16,x16,x17 orr x14,x14,x16 // ~is_equal(U1,U2) mvn x27,x24 // -1/0 -> 0/-1 mvn x28,x25 // -1/0 -> 0/-1 orr x14,x14,x27 orr x14,x14,x28 orr x14,x14,x26 cbnz x14,Ladd_proceed // if(~is_equal(U1,U2) \| in1infty \| in2infty \| ~is_equal(S1,S2)) Ladd_double: mov x1,x22 mov x0,x21 ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] add sp,sp,#256 // #256 is from #32(12-4). difference in stack frames b Ldouble_shortcut .align 4 Ladd_proceed: add x0,sp,#192 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Rsqr, R); ldr x3,[x22,#64] ldp x4,x5,[sp,#96] ldp x6,x7,[sp,#96+16] add x2,x22,#64 add x0,sp,#64 bl __ecp_nistz256_mul_mont // p256_mul_mont(res_z, H, in1_z); ldp x4,x5,[sp,#96] ldp x6,x7,[sp,#96+16] add x0,sp,#128 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Hsqr, H); ldr x3,[x23,#64] ldp x4,x5,[sp,#64] ldp x6,x7,[sp,#64+16] add x2,x23,#64 add x0,sp,#64 bl __ecp_nistz256_mul_mont // p256_mul_mont(res_z, res_z, in2_z); ldr x3,[sp,#96] ldp x4,x5,[sp,#128] ldp x6,x7,[sp,#128+16] add x2,sp,#96 add x0,sp,#224 bl __ecp_nistz256_mul_mont // p256_mul_mont(Hcub, Hsqr, H); ldr x3,[sp,#128] ldp x4,x5,[sp,#256] ldp x6,x7,[sp,#256+16] add x2,sp,#128 add x0,sp,#288 bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, U1, Hsqr); mov x8,x14 mov x9,x15 mov x10,x16 mov x11,x17 add x0,sp,#128 bl __ecp_nistz256_add_to // p256_mul_by_2(Hsqr, U2); add x2,sp,#192 add x0,sp,#0 bl __ecp_nistz256_sub_morf // p256_sub(res_x, Rsqr, Hsqr); add x2,sp,#224 bl __ecp_nistz256_sub_from // p256_sub(res_x, res_x, Hcub); add x2,sp,#288 ldr x3,[sp,#224] // forward load for p256_mul_mont ldp x4,x5,[sp,#320] ldp x6,x7,[sp,#320+16] add x0,sp,#32 bl __ecp_nistz256_sub_morf // p256_sub(res_y, U2, res_x); add x2,sp,#224 add x0,sp,#352 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, S1, Hcub); ldr x3,[sp,#160] ldp x4,x5,[sp,#32] ldp x6,x7,[sp,#32+16] add x2,sp,#160 add x0,sp,#32 bl __ecp_nistz256_mul_mont // p256_mul_mont(res_y, res_y, R); add x2,sp,#352 bl __ecp_nistz256_sub_from // p256_sub(res_y, res_y, S2); ldp x4,x5,[sp,#0] // res ldp x6,x7,[sp,#0+16] ldp x8,x9,[x23] // in2 ldp x10,x11,[x23,#16] ldp x14,x15,[x22,#0] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#0+16] csel x8,x4,x8,ne csel x9,x5,x9,ne ldp x4,x5,[sp,#0+0+32] // res csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? ldp x6,x7,[sp,#0+0+48] csel x14,x8,x14,ne csel x15,x9,x15,ne ldp x8,x9,[x23,#0+32] // in2 csel x16,x10,x16,ne csel x17,x11,x17,ne ldp x10,x11,[x23,#0+48] stp x14,x15,[x21,#0] stp x16,x17,[x21,#0+16] ldp x14,x15,[x22,#32] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#32+16] csel x8,x4,x8,ne csel x9,x5,x9,ne ldp x4,x5,[sp,#0+32+32] // res csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? ldp x6,x7,[sp,#0+32+48] csel x14,x8,x14,ne csel x15,x9,x15,ne ldp x8,x9,[x23,#32+32] // in2 csel x16,x10,x16,ne csel x17,x11,x17,ne ldp x10,x11,[x23,#32+48] stp x14,x15,[x21,#32] stp x16,x17,[x21,#32+16] ldp x14,x15,[x22,#64] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#64+16] csel x8,x4,x8,ne csel x9,x5,x9,ne csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? csel x14,x8,x14,ne csel x15,x9,x15,ne csel x16,x10,x16,ne csel x17,x11,x17,ne stp x14,x15,[x21,#64] stp x16,x17,[x21,#64+16] Ladd_done: add sp,x29,#0 // destroy frame ldp x19,x20,[x29,#16] ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret .globl ecp_nistz256_point_add_affine .def ecp_nistz256_point_add_affine .type 32 .endef .align 5 ecp_nistz256_point_add_affine: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-80]! add x29,sp,#0 stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] stp x25,x26,[sp,#64] sub sp,sp,#3210 mov x21,x0 mov x22,x1 mov x23,x2 adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] ldr x13,[x13,#24] ldp x4,x5,[x1,#64] // in1_z ldp x6,x7,[x1,#64+16] orr x8,x4,x5 orr x10,x6,x7 orr x24,x8,x10 cmp x24,#0 csetm x24,ne // ~in1infty ldp x14,x15,[x2] // in2_x ldp x16,x17,[x2,#16] ldp x8,x9,[x2,#32] // in2_y ldp x10,x11,[x2,#48] orr x14,x14,x15 orr x16,x16,x17 orr x8,x8,x9 orr x10,x10,x11 orr x14,x14,x16 orr x8,x8,x10 orr x25,x14,x8 cmp x25,#0 csetm x25,ne // ~in2infty add x0,sp,#128 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Z1sqr, in1_z); mov x4,x14 mov x5,x15 mov x6,x16 mov x7,x17 ldr x3,[x23] add x2,x23,#0 add x0,sp,#96 bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, Z1sqr, in2_x); add x2,x22,#0 ldr x3,[x22,#64] // forward load for p256_mul_mont ldp x4,x5,[sp,#128] ldp x6,x7,[sp,#128+16] add x0,sp,#160 bl __ecp_nistz256_sub_from // p256_sub(H, U2, in1_x); add x2,x22,#64 add x0,sp,#128 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, Z1sqr, in1_z); ldr x3,[x22,#64] ldp x4,x5,[sp,#160] ldp x6,x7,[sp,#160+16] add x2,x22,#64 add x0,sp,#64 bl __ecp_nistz256_mul_mont // p256_mul_mont(res_z, H, in1_z); ldr x3,[x23,#32] ldp x4,x5,[sp,#128] ldp x6,x7,[sp,#128+16] add x2,x23,#32 add x0,sp,#128 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, S2, in2_y); add x2,x22,#32 ldp x4,x5,[sp,#160] // forward load for p256_sqr_mont ldp x6,x7,[sp,#160+16] add x0,sp,#192 bl __ecp_nistz256_sub_from // p256_sub(R, S2, in1_y); add x0,sp,#224 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Hsqr, H); ldp x4,x5,[sp,#192] ldp x6,x7,[sp,#192+16] add x0,sp,#288 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Rsqr, R); ldr x3,[sp,#160] ldp x4,x5,[sp,#224] ldp x6,x7,[sp,#224+16] add x2,sp,#160 add x0,sp,#256 bl __ecp_nistz256_mul_mont // p256_mul_mont(Hcub, Hsqr, H); ldr x3,[x22] ldp x4,x5,[sp,#224] ldp x6,x7,[sp,#224+16] add x2,x22,#0 add x0,sp,#96 bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, in1_x, Hsqr); mov x8,x14 mov x9,x15 mov x10,x16 mov x11,x17 add x0,sp,#224 bl __ecp_nistz256_add_to // p256_mul_by_2(Hsqr, U2); add x2,sp,#288 add x0,sp,#0 bl __ecp_nistz256_sub_morf // p256_sub(res_x, Rsqr, Hsqr); add x2,sp,#256 bl __ecp_nistz256_sub_from // p256_sub(res_x, res_x, Hcub); add x2,sp,#96 ldr x3,[x22,#32] // forward load for p256_mul_mont ldp x4,x5,[sp,#256] ldp x6,x7,[sp,#256+16] add x0,sp,#32 bl __ecp_nistz256_sub_morf // p256_sub(res_y, U2, res_x); add x2,x22,#32 add x0,sp,#128 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, in1_y, Hcub); ldr x3,[sp,#192] ldp x4,x5,[sp,#32] ldp x6,x7,[sp,#32+16] add x2,sp,#192 add x0,sp,#32 bl __ecp_nistz256_mul_mont // p256_mul_mont(res_y, res_y, R); add x2,sp,#128 bl __ecp_nistz256_sub_from // p256_sub(res_y, res_y, S2); ldp x4,x5,[sp,#0] // res ldp x6,x7,[sp,#0+16] ldp x8,x9,[x23] // in2 ldp x10,x11,[x23,#16] ldp x14,x15,[x22,#0] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#0+16] csel x8,x4,x8,ne csel x9,x5,x9,ne ldp x4,x5,[sp,#0+0+32] // res csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? ldp x6,x7,[sp,#0+0+48] csel x14,x8,x14,ne csel x15,x9,x15,ne ldp x8,x9,[x23,#0+32] // in2 csel x16,x10,x16,ne csel x17,x11,x17,ne ldp x10,x11,[x23,#0+48] stp x14,x15,[x21,#0] stp x16,x17,[x21,#0+16] adrp x23,Lone_mont-64 add x23,x23,:lo12:Lone_mont-64 ldp x14,x15,[x22,#32] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#32+16] csel x8,x4,x8,ne csel x9,x5,x9,ne ldp x4,x5,[sp,#0+32+32] // res csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? ldp x6,x7,[sp,#0+32+48] csel x14,x8,x14,ne csel x15,x9,x15,ne ldp x8,x9,[x23,#32+32] // in2 csel x16,x10,x16,ne csel x17,x11,x17,ne ldp x10,x11,[x23,#32+48] stp x14,x15,[x21,#32] stp x16,x17,[x21,#32+16] ldp x14,x15,[x22,#64] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#64+16] csel x8,x4,x8,ne csel x9,x5,x9,ne csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? csel x14,x8,x14,ne csel x15,x9,x15,ne csel x16,x10,x16,ne csel x17,x11,x17,ne stp x14,x15,[x21,#64] stp x16,x17,[x21,#64+16] add sp,x29,#0 // destroy frame ldp x19,x20,[x29,#16] ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x29,x30,[sp],#80 AARCH64_VALIDATE_LINK_REGISTER ret //////////////////////////////////////////////////////////////////////// // void ecp_nistz256_ord_mul_mont(uint64_t res[4], uint64_t a[4], // uint64_t b[4]); .globl ecp_nistz256_ord_mul_mont .def ecp_nistz256_ord_mul_mont .type 32 .endef .align 4 ecp_nistz256_ord_mul_mont: AARCH64_VALID_CALL_TARGET // Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later. stp x29,x30,[sp,#-64]! add x29,sp,#0 stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] adrp x23,Lord add x23,x23,:lo12:Lord ldr x3,[x2] // bp[0] ldp x4,x5,[x1] ldp x6,x7,[x1,#16] ldp x12,x13,[x23,#0] ldp x21,x22,[x23,#16] ldr x23,[x23,#32] mul x14,x4,x3 // a[0]b[0] umulh x8,x4,x3 mul x15,x5,x3 // a[1]b[0] umulh x9,x5,x3 mul x16,x6,x3 // a[2]b[0] umulh x10,x6,x3 mul x17,x7,x3 // a[3]b[0] umulh x19,x7,x3 mul x24,x14,x23 adds x15,x15,x8 // accumulate high parts of multiplication adcs x16,x16,x9 adcs x17,x17,x10 adc x19,x19,xzr mov x20,xzr ldr x3,[x2,#81] // b[i] lsl x8,x24,#32 subs x16,x16,x24 lsr x9,x24,#32 sbcs x17,x17,x8 sbcs x19,x19,x9 sbc x20,x20,xzr subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 mul x8,x4,x3 adc x11,x11,xzr mul x9,x5,x3 adds x14,x15,x10 mul x10,x6,x3 adcs x15,x16,x11 mul x11,x7,x3 adcs x16,x17,x24 adcs x17,x19,x24 adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts umulh x8,x4,x3 adcs x15,x15,x9 umulh x9,x5,x3 adcs x16,x16,x10 umulh x10,x6,x3 adcs x17,x17,x11 umulh x11,x7,x3 adc x19,x19,xzr mul x24,x14,x23 adds x15,x15,x8 // accumulate high parts adcs x16,x16,x9 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr ldr x3,[x2,#82] // b[i] lsl x8,x24,#32 subs x16,x16,x24 lsr x9,x24,#32 sbcs x17,x17,x8 sbcs x19,x19,x9 sbc x20,x20,xzr subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 mul x8,x4,x3 adc x11,x11,xzr mul x9,x5,x3 adds x14,x15,x10 mul x10,x6,x3 adcs x15,x16,x11 mul x11,x7,x3 adcs x16,x17,x24 adcs x17,x19,x24 adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts umulh x8,x4,x3 adcs x15,x15,x9 umulh x9,x5,x3 adcs x16,x16,x10 umulh x10,x6,x3 adcs x17,x17,x11 umulh x11,x7,x3 adc x19,x19,xzr mul x24,x14,x23 adds x15,x15,x8 // accumulate high parts adcs x16,x16,x9 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr ldr x3,[x2,#83] // b[i] lsl x8,x24,#32 subs x16,x16,x24 lsr x9,x24,#32 sbcs x17,x17,x8 sbcs x19,x19,x9 sbc x20,x20,xzr subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 mul x8,x4,x3 adc x11,x11,xzr mul x9,x5,x3 adds x14,x15,x10 mul x10,x6,x3 adcs x15,x16,x11 mul x11,x7,x3 adcs x16,x17,x24 adcs x17,x19,x24 adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts umulh x8,x4,x3 adcs x15,x15,x9 umulh x9,x5,x3 adcs x16,x16,x10 umulh x10,x6,x3 adcs x17,x17,x11 umulh x11,x7,x3 adc x19,x19,xzr mul x24,x14,x23 adds x15,x15,x8 // accumulate high parts adcs x16,x16,x9 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr lsl x8,x24,#32 // last reduction subs x16,x16,x24 lsr x9,x24,#32 sbcs x17,x17,x8 sbcs x19,x19,x9 sbc x20,x20,xzr subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 adc x11,x11,xzr adds x14,x15,x10 adcs x15,x16,x11 adcs x16,x17,x24 adcs x17,x19,x24 adc x19,x20,xzr subs x8,x14,x12 // ret -= modulus sbcs x9,x15,x13 sbcs x10,x16,x21 sbcs x11,x17,x22 sbcs xzr,x19,xzr csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus csel x15,x15,x9,lo csel x16,x16,x10,lo stp x14,x15,[x0] csel x17,x17,x11,lo stp x16,x17,[x0,#16] ldp x19,x20,[sp,#16] ldp x21,x22,[sp,#32] ldp x23,x24,[sp,#48] ldr x29,[sp],#64 ret //////////////////////////////////////////////////////////////////////// // void ecp_nistz256_ord_sqr_mont(uint64_t res[4], uint64_t a[4], // uint64_t rep); .globl ecp_nistz256_ord_sqr_mont .def ecp_nistz256_ord_sqr_mont .type 32 .endef .align 4 ecp_nistz256_ord_sqr_mont: AARCH64_VALID_CALL_TARGET // Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later. stp x29,x30,[sp,#-64]! add x29,sp,#0 stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] adrp x23,Lord add x23,x23,:lo12:Lord ldp x4,x5,[x1] ldp x6,x7,[x1,#16] ldp x12,x13,[x23,#0] ldp x21,x22,[x23,#16] ldr x23,[x23,#32] b Loop_ord_sqr .align 4 Loop_ord_sqr: sub x2,x2,#1 //////////////////////////////////////////////////////////////// // \| \| \| \| \| \|a1a0\| \| // \| \| \| \| \|a2a0\| \| \| // \| \|a3a2\|a3a0\| \| \| \| // \| \| \| \|a2a1\| \| \| \| // \| \| \|a3a1\| \| \| \| \| // \| \| \| \| \| \| \| \| 2\| // +\|a3a3\|a2a2\|a1a1\|a0a0\| // \|--+--+--+--+--+--+--+--\| // \|A7\|A6\|A5\|A4\|A3\|A2\|A1\|A0\|, where Ax is , i.e. follow // // "can't overflow" below mark carrying into high part of // multiplication result, which can't overflow, because it // can never be all ones. mul x15,x5,x4 // a[1]a[0] umulh x9,x5,x4 mul x16,x6,x4 // a[2]a[0] umulh x10,x6,x4 mul x17,x7,x4 // a[3]a[0] umulh x19,x7,x4 adds x16,x16,x9 // accumulate high parts of multiplication mul x8,x6,x5 // a[2]a[1] umulh x9,x6,x5 adcs x17,x17,x10 mul x10,x7,x5 // a[3]a[1] umulh x11,x7,x5 adc x19,x19,xzr // can't overflow mul x20,x7,x6 // a[3]a[2] umulh x1,x7,x6 adds x9,x9,x10 // accumulate high parts of multiplication mul x14,x4,x4 // a[0]a[0] adc x10,x11,xzr // can't overflow adds x17,x17,x8 // accumulate low parts of multiplication umulh x4,x4,x4 adcs x19,x19,x9 mul x9,x5,x5 // a[1]a[1] adcs x20,x20,x10 umulh x5,x5,x5 adc x1,x1,xzr // can't overflow adds x15,x15,x15 // acc[1-6]=2 mul x10,x6,x6 // a[2]a[2] adcs x16,x16,x16 umulh x6,x6,x6 adcs x17,x17,x17 mul x11,x7,x7 // a[3]a[3] adcs x19,x19,x19 umulh x7,x7,x7 adcs x20,x20,x20 adcs x1,x1,x1 adc x3,xzr,xzr adds x15,x15,x4 // +a[i]a[i] mul x24,x14,x23 adcs x16,x16,x9 adcs x17,x17,x5 adcs x19,x19,x10 adcs x20,x20,x6 adcs x1,x1,x11 adc x3,x3,x7 subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 adc x11,x11,xzr adds x14,x15,x10 adcs x15,x16,x11 adcs x16,x17,x24 adc x17,xzr,x24 // can't overflow mul x11,x14,x23 lsl x8,x24,#32 subs x15,x15,x24 lsr x9,x24,#32 sbcs x16,x16,x8 sbc x17,x17,x9 // can't borrow subs xzr,x14,#1 umulh x9,x12,x11 mul x10,x13,x11 umulh x24,x13,x11 adcs x10,x10,x9 adc x24,x24,xzr adds x14,x15,x10 adcs x15,x16,x24 adcs x16,x17,x11 adc x17,xzr,x11 // can't overflow mul x24,x14,x23 lsl x8,x11,#32 subs x15,x15,x11 lsr x9,x11,#32 sbcs x16,x16,x8 sbc x17,x17,x9 // can't borrow subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 adc x11,x11,xzr adds x14,x15,x10 adcs x15,x16,x11 adcs x16,x17,x24 adc x17,xzr,x24 // can't overflow mul x11,x14,x23 lsl x8,x24,#32 subs x15,x15,x24 lsr x9,x24,#32 sbcs x16,x16,x8 sbc x17,x17,x9 // can't borrow subs xzr,x14,#1 umulh x9,x12,x11 mul x10,x13,x11 umulh x24,x13,x11 adcs x10,x10,x9 adc x24,x24,xzr adds x14,x15,x10 adcs x15,x16,x24 adcs x16,x17,x11 adc x17,xzr,x11 // can't overflow lsl x8,x11,#32 subs x15,x15,x11 lsr x9,x11,#32 sbcs x16,x16,x8 sbc x17,x17,x9 // can't borrow adds x14,x14,x19 // accumulate upper half adcs x15,x15,x20 adcs x16,x16,x1 adcs x17,x17,x3 adc x19,xzr,xzr subs x8,x14,x12 // ret -= modulus sbcs x9,x15,x13 sbcs x10,x16,x21 sbcs x11,x17,x22 sbcs xzr,x19,xzr csel x4,x14,x8,lo // ret = borrow ? ret : ret-modulus csel x5,x15,x9,lo csel x6,x16,x10,lo csel x7,x17,x11,lo cbnz x2,Loop_ord_sqr stp x4,x5,[x0] stp x6,x7,[x0,#16] ldp x19,x20,[sp,#16] ldp x21,x22,[sp,#32] ldp x23,x24,[sp,#48] ldr x29,[sp],#64 ret //////////////////////////////////////////////////////////////////////// // void ecp_nistz256_select_w5(uint64_t val, uint64_t in_t, int index); .globl ecp_nistz256_select_w5 .def ecp_nistz256_select_w5 .type 32 .endef .align 4 ecp_nistz256_select_w5: AARCH64_VALID_CALL_TARGET // x10 := x0 // w9 := 0; loop counter and incremented internal index mov x10, x0 mov w9, #0 // [v16-v21] := 0 movi v16.16b, #0 movi v17.16b, #0 movi v18.16b, #0 movi v19.16b, #0 movi v20.16b, #0 movi v21.16b, #0 Lselect_w5_loop: // Loop 16 times. // Increment index (loop counter); tested at the end of the loop add w9, w9, #1 // [v22-v27] := Load a (3256-bit = 6128-bit) table entry starting at x1 // and advance x1 to point to the next entry ld1 {v22.2d, v23.2d, v24.2d, v25.2d}, [x1],#64 // x11 := (w9 == w2)? All 1s : All 0s cmp w9, w2 csetm x11, eq // continue loading ... ld1 {v26.2d, v27.2d}, [x1],#32 // duplicate mask_64 into Mask (all 0s or all 1s) dup v3.2d, x11 // [v16-v19] := (Mask == all 1s)? [v22-v25] : [v16-v19] // i.e., values in output registers will remain the same if w9 != w2 bit v16.16b, v22.16b, v3.16b bit v17.16b, v23.16b, v3.16b bit v18.16b, v24.16b, v3.16b bit v19.16b, v25.16b, v3.16b bit v20.16b, v26.16b, v3.16b bit v21.16b, v27.16b, v3.16b // If bit #4 is not 0 (i.e. idx_ctr < 16) loop back tbz w9, #4, Lselect_w5_loop // Write [v16-v21] to memory at the output pointer st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x10],#64 st1 {v20.2d, v21.2d}, [x10] ret //////////////////////////////////////////////////////////////////////// // void ecp_nistz256_select_w7(uint64_t val, uint64_t in_t, int index); .globl ecp_nistz256_select_w7 .def ecp_nistz256_select_w7 .type 32 .endef .align 4 ecp_nistz256_select_w7: AARCH64_VALID_CALL_TARGET // w9 := 0; loop counter and incremented internal index mov w9, #0 // [v16-v21] := 0 movi v16.16b, #0 movi v17.16b, #0 movi v18.16b, #0 movi v19.16b, #0 Lselect_w7_loop: // Loop 64 times. // Increment index (loop counter); tested at the end of the loop add w9, w9, #1 // [v22-v25] := Load a (2256-bit = 4*128-bit) table entry starting at x1 // and advance x1 to point to the next entry ld1 {v22.2d, v23.2d, v24.2d, v25.2d}, [x1],#64 // x11 := (w9 == w2)? All 1s : All 0s cmp w9, w2 csetm x11, eq // duplicate mask_64 into Mask (all 0s or all 1s) dup v3.2d, x11 // [v16-v19] := (Mask == all 1s)? [v22-v25] : [v16-v19] // i.e., values in output registers will remain the same if w9 != w2 bit v16.16b, v22.16b, v3.16b bit v17.16b, v23.16b, v3.16b bit v18.16b, v24.16b, v3.16b bit v19.16b, v25.16b, v3.16b // If bit #6 is not 0 (i.e. idx_ctr < 64) loop back tbz w9, #6, Lselect_w7_loop // Write [v16-v19] to memory at the output pointer st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0] ret #endif // !OPENSSL_NO_ASM && defined(OPENSSL_AARCH64) && defined(_WIN32)
j4yc3-mw/Viren	32,699	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/chacha-x86_64-macosx.S	// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__APPLE__) .text .section __DATA,__const .p2align 6 L$zero: .long 0,0,0,0 L$one: .long 1,0,0,0 L$inc: .long 0,1,2,3 L$four: .long 4,4,4,4 L$incy: .long 0,2,4,6,1,3,5,7 L$eight: .long 8,8,8,8,8,8,8,8 L$rot16: .byte 0x2,0x3,0x0,0x1, 0x6,0x7,0x4,0x5, 0xa,0xb,0x8,0x9, 0xe,0xf,0xc,0xd L$rot24: .byte 0x3,0x0,0x1,0x2, 0x7,0x4,0x5,0x6, 0xb,0x8,0x9,0xa, 0xf,0xc,0xd,0xe L$sigma: .byte 101,120,112,97,110,100,32,51,50,45,98,121,116,101,32,107,0 .p2align 6 L$zeroz: .long 0,0,0,0, 1,0,0,0, 2,0,0,0, 3,0,0,0 L$fourz: .long 4,0,0,0, 4,0,0,0, 4,0,0,0, 4,0,0,0 L$incz: .long 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 L$sixteen: .long 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 .byte 67,104,97,67,104,97,50,48,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 .text .globl _ChaCha20_ctr32 .private_extern _ChaCha20_ctr32 .p2align 6 _ChaCha20_ctr32: _CET_ENDBR cmpq $0,%rdx je L$no_data movq _OPENSSL_ia32cap_P+4(%rip),%r10 testl $512,%r10d jnz L$ChaCha20_ssse3 pushq %rbx pushq %rbp pushq %r12 pushq %r13 pushq %r14 pushq %r15 subq $64+24,%rsp L$ctr32_body: movdqu (%rcx),%xmm1 movdqu 16(%rcx),%xmm2 movdqu (%r8),%xmm3 movdqa L$one(%rip),%xmm4 movdqa %xmm1,16(%rsp) movdqa %xmm2,32(%rsp) movdqa %xmm3,48(%rsp) movq %rdx,%rbp jmp L$oop_outer .p2align 5 L$oop_outer: movl $0x61707865,%eax movl $0x3320646e,%ebx movl $0x79622d32,%ecx movl $0x6b206574,%edx movl 16(%rsp),%r8d movl 20(%rsp),%r9d movl 24(%rsp),%r10d movl 28(%rsp),%r11d movd %xmm3,%r12d movl 52(%rsp),%r13d movl 56(%rsp),%r14d movl 60(%rsp),%r15d movq %rbp,64+0(%rsp) movl $10,%ebp movq %rsi,64+8(%rsp) .byte 102,72,15,126,214 movq %rdi,64+16(%rsp) movq %rsi,%rdi shrq $32,%rdi jmp L$oop .p2align 5 L$oop: addl %r8d,%eax xorl %eax,%r12d roll $16,%r12d addl %r9d,%ebx xorl %ebx,%r13d roll $16,%r13d addl %r12d,%esi xorl %esi,%r8d roll $12,%r8d addl %r13d,%edi xorl %edi,%r9d roll $12,%r9d addl %r8d,%eax xorl %eax,%r12d roll $8,%r12d addl %r9d,%ebx xorl %ebx,%r13d roll $8,%r13d addl %r12d,%esi xorl %esi,%r8d roll $7,%r8d addl %r13d,%edi xorl %edi,%r9d roll $7,%r9d movl %esi,32(%rsp) movl %edi,36(%rsp) movl 40(%rsp),%esi movl 44(%rsp),%edi addl %r10d,%ecx xorl %ecx,%r14d roll $16,%r14d addl %r11d,%edx xorl %edx,%r15d roll $16,%r15d addl %r14d,%esi xorl %esi,%r10d roll $12,%r10d addl %r15d,%edi xorl %edi,%r11d roll $12,%r11d addl %r10d,%ecx xorl %ecx,%r14d roll $8,%r14d addl %r11d,%edx xorl %edx,%r15d roll $8,%r15d addl %r14d,%esi xorl %esi,%r10d roll $7,%r10d addl %r15d,%edi xorl %edi,%r11d roll $7,%r11d addl %r9d,%eax xorl %eax,%r15d roll $16,%r15d addl %r10d,%ebx xorl %ebx,%r12d roll $16,%r12d addl %r15d,%esi xorl %esi,%r9d roll $12,%r9d addl %r12d,%edi xorl %edi,%r10d roll $12,%r10d addl %r9d,%eax xorl %eax,%r15d roll $8,%r15d addl %r10d,%ebx xorl %ebx,%r12d roll $8,%r12d addl %r15d,%esi xorl %esi,%r9d roll $7,%r9d addl %r12d,%edi xorl %edi,%r10d roll $7,%r10d movl %esi,40(%rsp) movl %edi,44(%rsp) movl 32(%rsp),%esi movl 36(%rsp),%edi addl %r11d,%ecx xorl %ecx,%r13d roll $16,%r13d addl %r8d,%edx xorl %edx,%r14d roll $16,%r14d addl %r13d,%esi xorl %esi,%r11d roll $12,%r11d addl %r14d,%edi xorl %edi,%r8d roll $12,%r8d addl %r11d,%ecx xorl %ecx,%r13d roll $8,%r13d addl %r8d,%edx xorl %edx,%r14d roll $8,%r14d addl %r13d,%esi xorl %esi,%r11d roll $7,%r11d addl %r14d,%edi xorl %edi,%r8d roll $7,%r8d decl %ebp jnz L$oop movl %edi,36(%rsp) movl %esi,32(%rsp) movq 64(%rsp),%rbp movdqa %xmm2,%xmm1 movq 64+8(%rsp),%rsi paddd %xmm4,%xmm3 movq 64+16(%rsp),%rdi addl $0x61707865,%eax addl $0x3320646e,%ebx addl $0x79622d32,%ecx addl $0x6b206574,%edx addl 16(%rsp),%r8d addl 20(%rsp),%r9d addl 24(%rsp),%r10d addl 28(%rsp),%r11d addl 48(%rsp),%r12d addl 52(%rsp),%r13d addl 56(%rsp),%r14d addl 60(%rsp),%r15d paddd 32(%rsp),%xmm1 cmpq $64,%rbp jb L$tail xorl 0(%rsi),%eax xorl 4(%rsi),%ebx xorl 8(%rsi),%ecx xorl 12(%rsi),%edx xorl 16(%rsi),%r8d xorl 20(%rsi),%r9d xorl 24(%rsi),%r10d xorl 28(%rsi),%r11d movdqu 32(%rsi),%xmm0 xorl 48(%rsi),%r12d xorl 52(%rsi),%r13d xorl 56(%rsi),%r14d xorl 60(%rsi),%r15d leaq 64(%rsi),%rsi pxor %xmm1,%xmm0 movdqa %xmm2,32(%rsp) movd %xmm3,48(%rsp) movl %eax,0(%rdi) movl %ebx,4(%rdi) movl %ecx,8(%rdi) movl %edx,12(%rdi) movl %r8d,16(%rdi) movl %r9d,20(%rdi) movl %r10d,24(%rdi) movl %r11d,28(%rdi) movdqu %xmm0,32(%rdi) movl %r12d,48(%rdi) movl %r13d,52(%rdi) movl %r14d,56(%rdi) movl %r15d,60(%rdi) leaq 64(%rdi),%rdi subq $64,%rbp jnz L$oop_outer jmp L$done .p2align 4 L$tail: movl %eax,0(%rsp) movl %ebx,4(%rsp) xorq %rbx,%rbx movl %ecx,8(%rsp) movl %edx,12(%rsp) movl %r8d,16(%rsp) movl %r9d,20(%rsp) movl %r10d,24(%rsp) movl %r11d,28(%rsp) movdqa %xmm1,32(%rsp) movl %r12d,48(%rsp) movl %r13d,52(%rsp) movl %r14d,56(%rsp) movl %r15d,60(%rsp) L$oop_tail: movzbl (%rsi,%rbx,1),%eax movzbl (%rsp,%rbx,1),%edx leaq 1(%rbx),%rbx xorl %edx,%eax movb %al,-1(%rdi,%rbx,1) decq %rbp jnz L$oop_tail L$done: leaq 64+24+48(%rsp),%rsi movq -48(%rsi),%r15 movq -40(%rsi),%r14 movq -32(%rsi),%r13 movq -24(%rsi),%r12 movq -16(%rsi),%rbp movq -8(%rsi),%rbx leaq (%rsi),%rsp L$no_data: ret .p2align 5 ChaCha20_ssse3: L$ChaCha20_ssse3: movq %rsp,%r9 cmpq $128,%rdx ja L$ChaCha20_4x L$do_sse3_after_all: subq $64+8,%rsp movdqa L$sigma(%rip),%xmm0 movdqu (%rcx),%xmm1 movdqu 16(%rcx),%xmm2 movdqu (%r8),%xmm3 movdqa L$rot16(%rip),%xmm6 movdqa L$rot24(%rip),%xmm7 movdqa %xmm0,0(%rsp) movdqa %xmm1,16(%rsp) movdqa %xmm2,32(%rsp) movdqa %xmm3,48(%rsp) movq $10,%r8 jmp L$oop_ssse3 .p2align 5 L$oop_outer_ssse3: movdqa L$one(%rip),%xmm3 movdqa 0(%rsp),%xmm0 movdqa 16(%rsp),%xmm1 movdqa 32(%rsp),%xmm2 paddd 48(%rsp),%xmm3 movq $10,%r8 movdqa %xmm3,48(%rsp) jmp L$oop_ssse3 .p2align 5 L$oop_ssse3: paddd %xmm1,%xmm0 pxor %xmm0,%xmm3 .byte 102,15,56,0,222 paddd %xmm3,%xmm2 pxor %xmm2,%xmm1 movdqa %xmm1,%xmm4 psrld $20,%xmm1 pslld $12,%xmm4 por %xmm4,%xmm1 paddd %xmm1,%xmm0 pxor %xmm0,%xmm3 .byte 102,15,56,0,223 paddd %xmm3,%xmm2 pxor %xmm2,%xmm1 movdqa %xmm1,%xmm4 psrld $25,%xmm1 pslld $7,%xmm4 por %xmm4,%xmm1 pshufd $78,%xmm2,%xmm2 pshufd $57,%xmm1,%xmm1 pshufd $147,%xmm3,%xmm3 nop paddd %xmm1,%xmm0 pxor %xmm0,%xmm3 .byte 102,15,56,0,222 paddd %xmm3,%xmm2 pxor %xmm2,%xmm1 movdqa %xmm1,%xmm4 psrld $20,%xmm1 pslld $12,%xmm4 por %xmm4,%xmm1 paddd %xmm1,%xmm0 pxor %xmm0,%xmm3 .byte 102,15,56,0,223 paddd %xmm3,%xmm2 pxor %xmm2,%xmm1 movdqa %xmm1,%xmm4 psrld $25,%xmm1 pslld $7,%xmm4 por %xmm4,%xmm1 pshufd $78,%xmm2,%xmm2 pshufd $147,%xmm1,%xmm1 pshufd $57,%xmm3,%xmm3 decq %r8 jnz L$oop_ssse3 paddd 0(%rsp),%xmm0 paddd 16(%rsp),%xmm1 paddd 32(%rsp),%xmm2 paddd 48(%rsp),%xmm3 cmpq $64,%rdx jb L$tail_ssse3 movdqu 0(%rsi),%xmm4 movdqu 16(%rsi),%xmm5 pxor %xmm4,%xmm0 movdqu 32(%rsi),%xmm4 pxor %xmm5,%xmm1 movdqu 48(%rsi),%xmm5 leaq 64(%rsi),%rsi pxor %xmm4,%xmm2 pxor %xmm5,%xmm3 movdqu %xmm0,0(%rdi) movdqu %xmm1,16(%rdi) movdqu %xmm2,32(%rdi) movdqu %xmm3,48(%rdi) leaq 64(%rdi),%rdi subq $64,%rdx jnz L$oop_outer_ssse3 jmp L$done_ssse3 .p2align 4 L$tail_ssse3: movdqa %xmm0,0(%rsp) movdqa %xmm1,16(%rsp) movdqa %xmm2,32(%rsp) movdqa %xmm3,48(%rsp) xorq %r8,%r8 L$oop_tail_ssse3: movzbl (%rsi,%r8,1),%eax movzbl (%rsp,%r8,1),%ecx leaq 1(%r8),%r8 xorl %ecx,%eax movb %al,-1(%rdi,%r8,1) decq %rdx jnz L$oop_tail_ssse3 L$done_ssse3: leaq (%r9),%rsp L$ssse3_epilogue: ret .p2align 5 ChaCha20_4x: L$ChaCha20_4x: movq %rsp,%r9 movq %r10,%r11 shrq $32,%r10 testq $32,%r10 jnz L$ChaCha20_8x cmpq $192,%rdx ja L$proceed4x andq $71303168,%r11 cmpq $4194304,%r11 je L$do_sse3_after_all L$proceed4x: subq $0x140+8,%rsp movdqa L$sigma(%rip),%xmm11 movdqu (%rcx),%xmm15 movdqu 16(%rcx),%xmm7 movdqu (%r8),%xmm3 leaq 256(%rsp),%rcx leaq L$rot16(%rip),%r10 leaq L$rot24(%rip),%r11 pshufd $0x00,%xmm11,%xmm8 pshufd $0x55,%xmm11,%xmm9 movdqa %xmm8,64(%rsp) pshufd $0xaa,%xmm11,%xmm10 movdqa %xmm9,80(%rsp) pshufd $0xff,%xmm11,%xmm11 movdqa %xmm10,96(%rsp) movdqa %xmm11,112(%rsp) pshufd $0x00,%xmm15,%xmm12 pshufd $0x55,%xmm15,%xmm13 movdqa %xmm12,128-256(%rcx) pshufd $0xaa,%xmm15,%xmm14 movdqa %xmm13,144-256(%rcx) pshufd $0xff,%xmm15,%xmm15 movdqa %xmm14,160-256(%rcx) movdqa %xmm15,176-256(%rcx) pshufd $0x00,%xmm7,%xmm4 pshufd $0x55,%xmm7,%xmm5 movdqa %xmm4,192-256(%rcx) pshufd $0xaa,%xmm7,%xmm6 movdqa %xmm5,208-256(%rcx) pshufd $0xff,%xmm7,%xmm7 movdqa %xmm6,224-256(%rcx) movdqa %xmm7,240-256(%rcx) pshufd $0x00,%xmm3,%xmm0 pshufd $0x55,%xmm3,%xmm1 paddd L$inc(%rip),%xmm0 pshufd $0xaa,%xmm3,%xmm2 movdqa %xmm1,272-256(%rcx) pshufd $0xff,%xmm3,%xmm3 movdqa %xmm2,288-256(%rcx) movdqa %xmm3,304-256(%rcx) jmp L$oop_enter4x .p2align 5 L$oop_outer4x: movdqa 64(%rsp),%xmm8 movdqa 80(%rsp),%xmm9 movdqa 96(%rsp),%xmm10 movdqa 112(%rsp),%xmm11 movdqa 128-256(%rcx),%xmm12 movdqa 144-256(%rcx),%xmm13 movdqa 160-256(%rcx),%xmm14 movdqa 176-256(%rcx),%xmm15 movdqa 192-256(%rcx),%xmm4 movdqa 208-256(%rcx),%xmm5 movdqa 224-256(%rcx),%xmm6 movdqa 240-256(%rcx),%xmm7 movdqa 256-256(%rcx),%xmm0 movdqa 272-256(%rcx),%xmm1 movdqa 288-256(%rcx),%xmm2 movdqa 304-256(%rcx),%xmm3 paddd L$four(%rip),%xmm0 L$oop_enter4x: movdqa %xmm6,32(%rsp) movdqa %xmm7,48(%rsp) movdqa (%r10),%xmm7 movl $10,%eax movdqa %xmm0,256-256(%rcx) jmp L$oop4x .p2align 5 L$oop4x: paddd %xmm12,%xmm8 paddd %xmm13,%xmm9 pxor %xmm8,%xmm0 pxor %xmm9,%xmm1 .byte 102,15,56,0,199 .byte 102,15,56,0,207 paddd %xmm0,%xmm4 paddd %xmm1,%xmm5 pxor %xmm4,%xmm12 pxor %xmm5,%xmm13 movdqa %xmm12,%xmm6 pslld $12,%xmm12 psrld $20,%xmm6 movdqa %xmm13,%xmm7 pslld $12,%xmm13 por %xmm6,%xmm12 psrld $20,%xmm7 movdqa (%r11),%xmm6 por %xmm7,%xmm13 paddd %xmm12,%xmm8 paddd %xmm13,%xmm9 pxor %xmm8,%xmm0 pxor %xmm9,%xmm1 .byte 102,15,56,0,198 .byte 102,15,56,0,206 paddd %xmm0,%xmm4 paddd %xmm1,%xmm5 pxor %xmm4,%xmm12 pxor %xmm5,%xmm13 movdqa %xmm12,%xmm7 pslld $7,%xmm12 psrld $25,%xmm7 movdqa %xmm13,%xmm6 pslld $7,%xmm13 por %xmm7,%xmm12 psrld $25,%xmm6 movdqa (%r10),%xmm7 por %xmm6,%xmm13 movdqa %xmm4,0(%rsp) movdqa %xmm5,16(%rsp) movdqa 32(%rsp),%xmm4 movdqa 48(%rsp),%xmm5 paddd %xmm14,%xmm10 paddd %xmm15,%xmm11 pxor %xmm10,%xmm2 pxor %xmm11,%xmm3 .byte 102,15,56,0,215 .byte 102,15,56,0,223 paddd %xmm2,%xmm4 paddd %xmm3,%xmm5 pxor %xmm4,%xmm14 pxor %xmm5,%xmm15 movdqa %xmm14,%xmm6 pslld $12,%xmm14 psrld $20,%xmm6 movdqa %xmm15,%xmm7 pslld $12,%xmm15 por %xmm6,%xmm14 psrld $20,%xmm7 movdqa (%r11),%xmm6 por %xmm7,%xmm15 paddd %xmm14,%xmm10 paddd %xmm15,%xmm11 pxor %xmm10,%xmm2 pxor %xmm11,%xmm3 .byte 102,15,56,0,214 .byte 102,15,56,0,222 paddd %xmm2,%xmm4 paddd %xmm3,%xmm5 pxor %xmm4,%xmm14 pxor %xmm5,%xmm15 movdqa %xmm14,%xmm7 pslld $7,%xmm14 psrld $25,%xmm7 movdqa %xmm15,%xmm6 pslld $7,%xmm15 por %xmm7,%xmm14 psrld $25,%xmm6 movdqa (%r10),%xmm7 por %xmm6,%xmm15 paddd %xmm13,%xmm8 paddd %xmm14,%xmm9 pxor %xmm8,%xmm3 pxor %xmm9,%xmm0 .byte 102,15,56,0,223 .byte 102,15,56,0,199 paddd %xmm3,%xmm4 paddd %xmm0,%xmm5 pxor %xmm4,%xmm13 pxor %xmm5,%xmm14 movdqa %xmm13,%xmm6 pslld $12,%xmm13 psrld $20,%xmm6 movdqa %xmm14,%xmm7 pslld $12,%xmm14 por %xmm6,%xmm13 psrld $20,%xmm7 movdqa (%r11),%xmm6 por %xmm7,%xmm14 paddd %xmm13,%xmm8 paddd %xmm14,%xmm9 pxor %xmm8,%xmm3 pxor %xmm9,%xmm0 .byte 102,15,56,0,222 .byte 102,15,56,0,198 paddd %xmm3,%xmm4 paddd %xmm0,%xmm5 pxor %xmm4,%xmm13 pxor %xmm5,%xmm14 movdqa %xmm13,%xmm7 pslld $7,%xmm13 psrld $25,%xmm7 movdqa %xmm14,%xmm6 pslld $7,%xmm14 por %xmm7,%xmm13 psrld $25,%xmm6 movdqa (%r10),%xmm7 por %xmm6,%xmm14 movdqa %xmm4,32(%rsp) movdqa %xmm5,48(%rsp) movdqa 0(%rsp),%xmm4 movdqa 16(%rsp),%xmm5 paddd %xmm15,%xmm10 paddd %xmm12,%xmm11 pxor %xmm10,%xmm1 pxor %xmm11,%xmm2 .byte 102,15,56,0,207 .byte 102,15,56,0,215 paddd %xmm1,%xmm4 paddd %xmm2,%xmm5 pxor %xmm4,%xmm15 pxor %xmm5,%xmm12 movdqa %xmm15,%xmm6 pslld $12,%xmm15 psrld $20,%xmm6 movdqa %xmm12,%xmm7 pslld $12,%xmm12 por %xmm6,%xmm15 psrld $20,%xmm7 movdqa (%r11),%xmm6 por %xmm7,%xmm12 paddd %xmm15,%xmm10 paddd %xmm12,%xmm11 pxor %xmm10,%xmm1 pxor %xmm11,%xmm2 .byte 102,15,56,0,206 .byte 102,15,56,0,214 paddd %xmm1,%xmm4 paddd %xmm2,%xmm5 pxor %xmm4,%xmm15 pxor %xmm5,%xmm12 movdqa %xmm15,%xmm7 pslld $7,%xmm15 psrld $25,%xmm7 movdqa %xmm12,%xmm6 pslld $7,%xmm12 por %xmm7,%xmm15 psrld $25,%xmm6 movdqa (%r10),%xmm7 por %xmm6,%xmm12 decl %eax jnz L$oop4x paddd 64(%rsp),%xmm8 paddd 80(%rsp),%xmm9 paddd 96(%rsp),%xmm10 paddd 112(%rsp),%xmm11 movdqa %xmm8,%xmm6 punpckldq %xmm9,%xmm8 movdqa %xmm10,%xmm7 punpckldq %xmm11,%xmm10 punpckhdq %xmm9,%xmm6 punpckhdq %xmm11,%xmm7 movdqa %xmm8,%xmm9 punpcklqdq %xmm10,%xmm8 movdqa %xmm6,%xmm11 punpcklqdq %xmm7,%xmm6 punpckhqdq %xmm10,%xmm9 punpckhqdq %xmm7,%xmm11 paddd 128-256(%rcx),%xmm12 paddd 144-256(%rcx),%xmm13 paddd 160-256(%rcx),%xmm14 paddd 176-256(%rcx),%xmm15 movdqa %xmm8,0(%rsp) movdqa %xmm9,16(%rsp) movdqa 32(%rsp),%xmm8 movdqa 48(%rsp),%xmm9 movdqa %xmm12,%xmm10 punpckldq %xmm13,%xmm12 movdqa %xmm14,%xmm7 punpckldq %xmm15,%xmm14 punpckhdq %xmm13,%xmm10 punpckhdq %xmm15,%xmm7 movdqa %xmm12,%xmm13 punpcklqdq %xmm14,%xmm12 movdqa %xmm10,%xmm15 punpcklqdq %xmm7,%xmm10 punpckhqdq %xmm14,%xmm13 punpckhqdq %xmm7,%xmm15 paddd 192-256(%rcx),%xmm4 paddd 208-256(%rcx),%xmm5 paddd 224-256(%rcx),%xmm8 paddd 240-256(%rcx),%xmm9 movdqa %xmm6,32(%rsp) movdqa %xmm11,48(%rsp) movdqa %xmm4,%xmm14 punpckldq %xmm5,%xmm4 movdqa %xmm8,%xmm7 punpckldq %xmm9,%xmm8 punpckhdq %xmm5,%xmm14 punpckhdq %xmm9,%xmm7 movdqa %xmm4,%xmm5 punpcklqdq %xmm8,%xmm4 movdqa %xmm14,%xmm9 punpcklqdq %xmm7,%xmm14 punpckhqdq %xmm8,%xmm5 punpckhqdq %xmm7,%xmm9 paddd 256-256(%rcx),%xmm0 paddd 272-256(%rcx),%xmm1 paddd 288-256(%rcx),%xmm2 paddd 304-256(%rcx),%xmm3 movdqa %xmm0,%xmm8 punpckldq %xmm1,%xmm0 movdqa %xmm2,%xmm7 punpckldq %xmm3,%xmm2 punpckhdq %xmm1,%xmm8 punpckhdq %xmm3,%xmm7 movdqa %xmm0,%xmm1 punpcklqdq %xmm2,%xmm0 movdqa %xmm8,%xmm3 punpcklqdq %xmm7,%xmm8 punpckhqdq %xmm2,%xmm1 punpckhqdq %xmm7,%xmm3 cmpq $256,%rdx jb L$tail4x movdqu 0(%rsi),%xmm6 movdqu 16(%rsi),%xmm11 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm7 pxor 0(%rsp),%xmm6 pxor %xmm12,%xmm11 pxor %xmm4,%xmm2 pxor %xmm0,%xmm7 movdqu %xmm6,0(%rdi) movdqu 64(%rsi),%xmm6 movdqu %xmm11,16(%rdi) movdqu 80(%rsi),%xmm11 movdqu %xmm2,32(%rdi) movdqu 96(%rsi),%xmm2 movdqu %xmm7,48(%rdi) movdqu 112(%rsi),%xmm7 leaq 128(%rsi),%rsi pxor 16(%rsp),%xmm6 pxor %xmm13,%xmm11 pxor %xmm5,%xmm2 pxor %xmm1,%xmm7 movdqu %xmm6,64(%rdi) movdqu 0(%rsi),%xmm6 movdqu %xmm11,80(%rdi) movdqu 16(%rsi),%xmm11 movdqu %xmm2,96(%rdi) movdqu 32(%rsi),%xmm2 movdqu %xmm7,112(%rdi) leaq 128(%rdi),%rdi movdqu 48(%rsi),%xmm7 pxor 32(%rsp),%xmm6 pxor %xmm10,%xmm11 pxor %xmm14,%xmm2 pxor %xmm8,%xmm7 movdqu %xmm6,0(%rdi) movdqu 64(%rsi),%xmm6 movdqu %xmm11,16(%rdi) movdqu 80(%rsi),%xmm11 movdqu %xmm2,32(%rdi) movdqu 96(%rsi),%xmm2 movdqu %xmm7,48(%rdi) movdqu 112(%rsi),%xmm7 leaq 128(%rsi),%rsi pxor 48(%rsp),%xmm6 pxor %xmm15,%xmm11 pxor %xmm9,%xmm2 pxor %xmm3,%xmm7 movdqu %xmm6,64(%rdi) movdqu %xmm11,80(%rdi) movdqu %xmm2,96(%rdi) movdqu %xmm7,112(%rdi) leaq 128(%rdi),%rdi subq $256,%rdx jnz L$oop_outer4x jmp L$done4x L$tail4x: cmpq $192,%rdx jae L$192_or_more4x cmpq $128,%rdx jae L$128_or_more4x cmpq $64,%rdx jae L$64_or_more4x xorq %r10,%r10 movdqa %xmm12,16(%rsp) movdqa %xmm4,32(%rsp) movdqa %xmm0,48(%rsp) jmp L$oop_tail4x .p2align 5 L$64_or_more4x: movdqu 0(%rsi),%xmm6 movdqu 16(%rsi),%xmm11 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm7 pxor 0(%rsp),%xmm6 pxor %xmm12,%xmm11 pxor %xmm4,%xmm2 pxor %xmm0,%xmm7 movdqu %xmm6,0(%rdi) movdqu %xmm11,16(%rdi) movdqu %xmm2,32(%rdi) movdqu %xmm7,48(%rdi) je L$done4x movdqa 16(%rsp),%xmm6 leaq 64(%rsi),%rsi xorq %r10,%r10 movdqa %xmm6,0(%rsp) movdqa %xmm13,16(%rsp) leaq 64(%rdi),%rdi movdqa %xmm5,32(%rsp) subq $64,%rdx movdqa %xmm1,48(%rsp) jmp L$oop_tail4x .p2align 5 L$128_or_more4x: movdqu 0(%rsi),%xmm6 movdqu 16(%rsi),%xmm11 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm7 pxor 0(%rsp),%xmm6 pxor %xmm12,%xmm11 pxor %xmm4,%xmm2 pxor %xmm0,%xmm7 movdqu %xmm6,0(%rdi) movdqu 64(%rsi),%xmm6 movdqu %xmm11,16(%rdi) movdqu 80(%rsi),%xmm11 movdqu %xmm2,32(%rdi) movdqu 96(%rsi),%xmm2 movdqu %xmm7,48(%rdi) movdqu 112(%rsi),%xmm7 pxor 16(%rsp),%xmm6 pxor %xmm13,%xmm11 pxor %xmm5,%xmm2 pxor %xmm1,%xmm7 movdqu %xmm6,64(%rdi) movdqu %xmm11,80(%rdi) movdqu %xmm2,96(%rdi) movdqu %xmm7,112(%rdi) je L$done4x movdqa 32(%rsp),%xmm6 leaq 128(%rsi),%rsi xorq %r10,%r10 movdqa %xmm6,0(%rsp) movdqa %xmm10,16(%rsp) leaq 128(%rdi),%rdi movdqa %xmm14,32(%rsp) subq $128,%rdx movdqa %xmm8,48(%rsp) jmp L$oop_tail4x .p2align 5 L$192_or_more4x: movdqu 0(%rsi),%xmm6 movdqu 16(%rsi),%xmm11 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm7 pxor 0(%rsp),%xmm6 pxor %xmm12,%xmm11 pxor %xmm4,%xmm2 pxor %xmm0,%xmm7 movdqu %xmm6,0(%rdi) movdqu 64(%rsi),%xmm6 movdqu %xmm11,16(%rdi) movdqu 80(%rsi),%xmm11 movdqu %xmm2,32(%rdi) movdqu 96(%rsi),%xmm2 movdqu %xmm7,48(%rdi) movdqu 112(%rsi),%xmm7 leaq 128(%rsi),%rsi pxor 16(%rsp),%xmm6 pxor %xmm13,%xmm11 pxor %xmm5,%xmm2 pxor %xmm1,%xmm7 movdqu %xmm6,64(%rdi) movdqu 0(%rsi),%xmm6 movdqu %xmm11,80(%rdi) movdqu 16(%rsi),%xmm11 movdqu %xmm2,96(%rdi) movdqu 32(%rsi),%xmm2 movdqu %xmm7,112(%rdi) leaq 128(%rdi),%rdi movdqu 48(%rsi),%xmm7 pxor 32(%rsp),%xmm6 pxor %xmm10,%xmm11 pxor %xmm14,%xmm2 pxor %xmm8,%xmm7 movdqu %xmm6,0(%rdi) movdqu %xmm11,16(%rdi) movdqu %xmm2,32(%rdi) movdqu %xmm7,48(%rdi) je L$done4x movdqa 48(%rsp),%xmm6 leaq 64(%rsi),%rsi xorq %r10,%r10 movdqa %xmm6,0(%rsp) movdqa %xmm15,16(%rsp) leaq 64(%rdi),%rdi movdqa %xmm9,32(%rsp) subq $192,%rdx movdqa %xmm3,48(%rsp) L$oop_tail4x: movzbl (%rsi,%r10,1),%eax movzbl (%rsp,%r10,1),%ecx leaq 1(%r10),%r10 xorl %ecx,%eax movb %al,-1(%rdi,%r10,1) decq %rdx jnz L$oop_tail4x L$done4x: leaq (%r9),%rsp L$4x_epilogue: ret .p2align 5 ChaCha20_8x: L$ChaCha20_8x: movq %rsp,%r9 subq $0x280+8,%rsp andq $-32,%rsp vzeroupper vbroadcasti128 L$sigma(%rip),%ymm11 vbroadcasti128 (%rcx),%ymm3 vbroadcasti128 16(%rcx),%ymm15 vbroadcasti128 (%r8),%ymm7 leaq 256(%rsp),%rcx leaq 512(%rsp),%rax leaq L$rot16(%rip),%r10 leaq L$rot24(%rip),%r11 vpshufd $0x00,%ymm11,%ymm8 vpshufd $0x55,%ymm11,%ymm9 vmovdqa %ymm8,128-256(%rcx) vpshufd $0xaa,%ymm11,%ymm10 vmovdqa %ymm9,160-256(%rcx) vpshufd $0xff,%ymm11,%ymm11 vmovdqa %ymm10,192-256(%rcx) vmovdqa %ymm11,224-256(%rcx) vpshufd $0x00,%ymm3,%ymm0 vpshufd $0x55,%ymm3,%ymm1 vmovdqa %ymm0,256-256(%rcx) vpshufd $0xaa,%ymm3,%ymm2 vmovdqa %ymm1,288-256(%rcx) vpshufd $0xff,%ymm3,%ymm3 vmovdqa %ymm2,320-256(%rcx) vmovdqa %ymm3,352-256(%rcx) vpshufd $0x00,%ymm15,%ymm12 vpshufd $0x55,%ymm15,%ymm13 vmovdqa %ymm12,384-512(%rax) vpshufd $0xaa,%ymm15,%ymm14 vmovdqa %ymm13,416-512(%rax) vpshufd $0xff,%ymm15,%ymm15 vmovdqa %ymm14,448-512(%rax) vmovdqa %ymm15,480-512(%rax) vpshufd $0x00,%ymm7,%ymm4 vpshufd $0x55,%ymm7,%ymm5 vpaddd L$incy(%rip),%ymm4,%ymm4 vpshufd $0xaa,%ymm7,%ymm6 vmovdqa %ymm5,544-512(%rax) vpshufd $0xff,%ymm7,%ymm7 vmovdqa %ymm6,576-512(%rax) vmovdqa %ymm7,608-512(%rax) jmp L$oop_enter8x .p2align 5 L$oop_outer8x: vmovdqa 128-256(%rcx),%ymm8 vmovdqa 160-256(%rcx),%ymm9 vmovdqa 192-256(%rcx),%ymm10 vmovdqa 224-256(%rcx),%ymm11 vmovdqa 256-256(%rcx),%ymm0 vmovdqa 288-256(%rcx),%ymm1 vmovdqa 320-256(%rcx),%ymm2 vmovdqa 352-256(%rcx),%ymm3 vmovdqa 384-512(%rax),%ymm12 vmovdqa 416-512(%rax),%ymm13 vmovdqa 448-512(%rax),%ymm14 vmovdqa 480-512(%rax),%ymm15 vmovdqa 512-512(%rax),%ymm4 vmovdqa 544-512(%rax),%ymm5 vmovdqa 576-512(%rax),%ymm6 vmovdqa 608-512(%rax),%ymm7 vpaddd L$eight(%rip),%ymm4,%ymm4 L$oop_enter8x: vmovdqa %ymm14,64(%rsp) vmovdqa %ymm15,96(%rsp) vbroadcasti128 (%r10),%ymm15 vmovdqa %ymm4,512-512(%rax) movl $10,%eax jmp L$oop8x .p2align 5 L$oop8x: vpaddd %ymm0,%ymm8,%ymm8 vpxor %ymm4,%ymm8,%ymm4 vpshufb %ymm15,%ymm4,%ymm4 vpaddd %ymm1,%ymm9,%ymm9 vpxor %ymm5,%ymm9,%ymm5 vpshufb %ymm15,%ymm5,%ymm5 vpaddd %ymm4,%ymm12,%ymm12 vpxor %ymm0,%ymm12,%ymm0 vpslld $12,%ymm0,%ymm14 vpsrld $20,%ymm0,%ymm0 vpor %ymm0,%ymm14,%ymm0 vbroadcasti128 (%r11),%ymm14 vpaddd %ymm5,%ymm13,%ymm13 vpxor %ymm1,%ymm13,%ymm1 vpslld $12,%ymm1,%ymm15 vpsrld $20,%ymm1,%ymm1 vpor %ymm1,%ymm15,%ymm1 vpaddd %ymm0,%ymm8,%ymm8 vpxor %ymm4,%ymm8,%ymm4 vpshufb %ymm14,%ymm4,%ymm4 vpaddd %ymm1,%ymm9,%ymm9 vpxor %ymm5,%ymm9,%ymm5 vpshufb %ymm14,%ymm5,%ymm5 vpaddd %ymm4,%ymm12,%ymm12 vpxor %ymm0,%ymm12,%ymm0 vpslld $7,%ymm0,%ymm15 vpsrld $25,%ymm0,%ymm0 vpor %ymm0,%ymm15,%ymm0 vbroadcasti128 (%r10),%ymm15 vpaddd %ymm5,%ymm13,%ymm13 vpxor %ymm1,%ymm13,%ymm1 vpslld $7,%ymm1,%ymm14 vpsrld $25,%ymm1,%ymm1 vpor %ymm1,%ymm14,%ymm1 vmovdqa %ymm12,0(%rsp) vmovdqa %ymm13,32(%rsp) vmovdqa 64(%rsp),%ymm12 vmovdqa 96(%rsp),%ymm13 vpaddd %ymm2,%ymm10,%ymm10 vpxor %ymm6,%ymm10,%ymm6 vpshufb %ymm15,%ymm6,%ymm6 vpaddd %ymm3,%ymm11,%ymm11 vpxor %ymm7,%ymm11,%ymm7 vpshufb %ymm15,%ymm7,%ymm7 vpaddd %ymm6,%ymm12,%ymm12 vpxor %ymm2,%ymm12,%ymm2 vpslld $12,%ymm2,%ymm14 vpsrld $20,%ymm2,%ymm2 vpor %ymm2,%ymm14,%ymm2 vbroadcasti128 (%r11),%ymm14 vpaddd %ymm7,%ymm13,%ymm13 vpxor %ymm3,%ymm13,%ymm3 vpslld $12,%ymm3,%ymm15 vpsrld $20,%ymm3,%ymm3 vpor %ymm3,%ymm15,%ymm3 vpaddd %ymm2,%ymm10,%ymm10 vpxor %ymm6,%ymm10,%ymm6 vpshufb %ymm14,%ymm6,%ymm6 vpaddd %ymm3,%ymm11,%ymm11 vpxor %ymm7,%ymm11,%ymm7 vpshufb %ymm14,%ymm7,%ymm7 vpaddd %ymm6,%ymm12,%ymm12 vpxor %ymm2,%ymm12,%ymm2 vpslld $7,%ymm2,%ymm15 vpsrld $25,%ymm2,%ymm2 vpor %ymm2,%ymm15,%ymm2 vbroadcasti128 (%r10),%ymm15 vpaddd %ymm7,%ymm13,%ymm13 vpxor %ymm3,%ymm13,%ymm3 vpslld $7,%ymm3,%ymm14 vpsrld $25,%ymm3,%ymm3 vpor %ymm3,%ymm14,%ymm3 vpaddd %ymm1,%ymm8,%ymm8 vpxor %ymm7,%ymm8,%ymm7 vpshufb %ymm15,%ymm7,%ymm7 vpaddd %ymm2,%ymm9,%ymm9 vpxor %ymm4,%ymm9,%ymm4 vpshufb %ymm15,%ymm4,%ymm4 vpaddd %ymm7,%ymm12,%ymm12 vpxor %ymm1,%ymm12,%ymm1 vpslld $12,%ymm1,%ymm14 vpsrld $20,%ymm1,%ymm1 vpor %ymm1,%ymm14,%ymm1 vbroadcasti128 (%r11),%ymm14 vpaddd %ymm4,%ymm13,%ymm13 vpxor %ymm2,%ymm13,%ymm2 vpslld $12,%ymm2,%ymm15 vpsrld $20,%ymm2,%ymm2 vpor %ymm2,%ymm15,%ymm2 vpaddd %ymm1,%ymm8,%ymm8 vpxor %ymm7,%ymm8,%ymm7 vpshufb %ymm14,%ymm7,%ymm7 vpaddd %ymm2,%ymm9,%ymm9 vpxor %ymm4,%ymm9,%ymm4 vpshufb %ymm14,%ymm4,%ymm4 vpaddd %ymm7,%ymm12,%ymm12 vpxor %ymm1,%ymm12,%ymm1 vpslld $7,%ymm1,%ymm15 vpsrld $25,%ymm1,%ymm1 vpor %ymm1,%ymm15,%ymm1 vbroadcasti128 (%r10),%ymm15 vpaddd %ymm4,%ymm13,%ymm13 vpxor %ymm2,%ymm13,%ymm2 vpslld $7,%ymm2,%ymm14 vpsrld $25,%ymm2,%ymm2 vpor %ymm2,%ymm14,%ymm2 vmovdqa %ymm12,64(%rsp) vmovdqa %ymm13,96(%rsp) vmovdqa 0(%rsp),%ymm12 vmovdqa 32(%rsp),%ymm13 vpaddd %ymm3,%ymm10,%ymm10 vpxor %ymm5,%ymm10,%ymm5 vpshufb %ymm15,%ymm5,%ymm5 vpaddd %ymm0,%ymm11,%ymm11 vpxor %ymm6,%ymm11,%ymm6 vpshufb %ymm15,%ymm6,%ymm6 vpaddd %ymm5,%ymm12,%ymm12 vpxor %ymm3,%ymm12,%ymm3 vpslld $12,%ymm3,%ymm14 vpsrld $20,%ymm3,%ymm3 vpor %ymm3,%ymm14,%ymm3 vbroadcasti128 (%r11),%ymm14 vpaddd %ymm6,%ymm13,%ymm13 vpxor %ymm0,%ymm13,%ymm0 vpslld $12,%ymm0,%ymm15 vpsrld $20,%ymm0,%ymm0 vpor %ymm0,%ymm15,%ymm0 vpaddd %ymm3,%ymm10,%ymm10 vpxor %ymm5,%ymm10,%ymm5 vpshufb %ymm14,%ymm5,%ymm5 vpaddd %ymm0,%ymm11,%ymm11 vpxor %ymm6,%ymm11,%ymm6 vpshufb %ymm14,%ymm6,%ymm6 vpaddd %ymm5,%ymm12,%ymm12 vpxor %ymm3,%ymm12,%ymm3 vpslld $7,%ymm3,%ymm15 vpsrld $25,%ymm3,%ymm3 vpor %ymm3,%ymm15,%ymm3 vbroadcasti128 (%r10),%ymm15 vpaddd %ymm6,%ymm13,%ymm13 vpxor %ymm0,%ymm13,%ymm0 vpslld $7,%ymm0,%ymm14 vpsrld $25,%ymm0,%ymm0 vpor %ymm0,%ymm14,%ymm0 decl %eax jnz L$oop8x leaq 512(%rsp),%rax vpaddd 128-256(%rcx),%ymm8,%ymm8 vpaddd 160-256(%rcx),%ymm9,%ymm9 vpaddd 192-256(%rcx),%ymm10,%ymm10 vpaddd 224-256(%rcx),%ymm11,%ymm11 vpunpckldq %ymm9,%ymm8,%ymm14 vpunpckldq %ymm11,%ymm10,%ymm15 vpunpckhdq %ymm9,%ymm8,%ymm8 vpunpckhdq %ymm11,%ymm10,%ymm10 vpunpcklqdq %ymm15,%ymm14,%ymm9 vpunpckhqdq %ymm15,%ymm14,%ymm14 vpunpcklqdq %ymm10,%ymm8,%ymm11 vpunpckhqdq %ymm10,%ymm8,%ymm8 vpaddd 256-256(%rcx),%ymm0,%ymm0 vpaddd 288-256(%rcx),%ymm1,%ymm1 vpaddd 320-256(%rcx),%ymm2,%ymm2 vpaddd 352-256(%rcx),%ymm3,%ymm3 vpunpckldq %ymm1,%ymm0,%ymm10 vpunpckldq %ymm3,%ymm2,%ymm15 vpunpckhdq %ymm1,%ymm0,%ymm0 vpunpckhdq %ymm3,%ymm2,%ymm2 vpunpcklqdq %ymm15,%ymm10,%ymm1 vpunpckhqdq %ymm15,%ymm10,%ymm10 vpunpcklqdq %ymm2,%ymm0,%ymm3 vpunpckhqdq %ymm2,%ymm0,%ymm0 vperm2i128 $0x20,%ymm1,%ymm9,%ymm15 vperm2i128 $0x31,%ymm1,%ymm9,%ymm1 vperm2i128 $0x20,%ymm10,%ymm14,%ymm9 vperm2i128 $0x31,%ymm10,%ymm14,%ymm10 vperm2i128 $0x20,%ymm3,%ymm11,%ymm14 vperm2i128 $0x31,%ymm3,%ymm11,%ymm3 vperm2i128 $0x20,%ymm0,%ymm8,%ymm11 vperm2i128 $0x31,%ymm0,%ymm8,%ymm0 vmovdqa %ymm15,0(%rsp) vmovdqa %ymm9,32(%rsp) vmovdqa 64(%rsp),%ymm15 vmovdqa 96(%rsp),%ymm9 vpaddd 384-512(%rax),%ymm12,%ymm12 vpaddd 416-512(%rax),%ymm13,%ymm13 vpaddd 448-512(%rax),%ymm15,%ymm15 vpaddd 480-512(%rax),%ymm9,%ymm9 vpunpckldq %ymm13,%ymm12,%ymm2 vpunpckldq %ymm9,%ymm15,%ymm8 vpunpckhdq %ymm13,%ymm12,%ymm12 vpunpckhdq %ymm9,%ymm15,%ymm15 vpunpcklqdq %ymm8,%ymm2,%ymm13 vpunpckhqdq %ymm8,%ymm2,%ymm2 vpunpcklqdq %ymm15,%ymm12,%ymm9 vpunpckhqdq %ymm15,%ymm12,%ymm12 vpaddd 512-512(%rax),%ymm4,%ymm4 vpaddd 544-512(%rax),%ymm5,%ymm5 vpaddd 576-512(%rax),%ymm6,%ymm6 vpaddd 608-512(%rax),%ymm7,%ymm7 vpunpckldq %ymm5,%ymm4,%ymm15 vpunpckldq %ymm7,%ymm6,%ymm8 vpunpckhdq %ymm5,%ymm4,%ymm4 vpunpckhdq %ymm7,%ymm6,%ymm6 vpunpcklqdq %ymm8,%ymm15,%ymm5 vpunpckhqdq %ymm8,%ymm15,%ymm15 vpunpcklqdq %ymm6,%ymm4,%ymm7 vpunpckhqdq %ymm6,%ymm4,%ymm4 vperm2i128 $0x20,%ymm5,%ymm13,%ymm8 vperm2i128 $0x31,%ymm5,%ymm13,%ymm5 vperm2i128 $0x20,%ymm15,%ymm2,%ymm13 vperm2i128 $0x31,%ymm15,%ymm2,%ymm15 vperm2i128 $0x20,%ymm7,%ymm9,%ymm2 vperm2i128 $0x31,%ymm7,%ymm9,%ymm7 vperm2i128 $0x20,%ymm4,%ymm12,%ymm9 vperm2i128 $0x31,%ymm4,%ymm12,%ymm4 vmovdqa 0(%rsp),%ymm6 vmovdqa 32(%rsp),%ymm12 cmpq $512,%rdx jb L$tail8x vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 leaq 128(%rsi),%rsi vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) leaq 128(%rdi),%rdi vpxor 0(%rsi),%ymm12,%ymm12 vpxor 32(%rsi),%ymm13,%ymm13 vpxor 64(%rsi),%ymm10,%ymm10 vpxor 96(%rsi),%ymm15,%ymm15 leaq 128(%rsi),%rsi vmovdqu %ymm12,0(%rdi) vmovdqu %ymm13,32(%rdi) vmovdqu %ymm10,64(%rdi) vmovdqu %ymm15,96(%rdi) leaq 128(%rdi),%rdi vpxor 0(%rsi),%ymm14,%ymm14 vpxor 32(%rsi),%ymm2,%ymm2 vpxor 64(%rsi),%ymm3,%ymm3 vpxor 96(%rsi),%ymm7,%ymm7 leaq 128(%rsi),%rsi vmovdqu %ymm14,0(%rdi) vmovdqu %ymm2,32(%rdi) vmovdqu %ymm3,64(%rdi) vmovdqu %ymm7,96(%rdi) leaq 128(%rdi),%rdi vpxor 0(%rsi),%ymm11,%ymm11 vpxor 32(%rsi),%ymm9,%ymm9 vpxor 64(%rsi),%ymm0,%ymm0 vpxor 96(%rsi),%ymm4,%ymm4 leaq 128(%rsi),%rsi vmovdqu %ymm11,0(%rdi) vmovdqu %ymm9,32(%rdi) vmovdqu %ymm0,64(%rdi) vmovdqu %ymm4,96(%rdi) leaq 128(%rdi),%rdi subq $512,%rdx jnz L$oop_outer8x jmp L$done8x L$tail8x: cmpq $448,%rdx jae L$448_or_more8x cmpq $384,%rdx jae L$384_or_more8x cmpq $320,%rdx jae L$320_or_more8x cmpq $256,%rdx jae L$256_or_more8x cmpq $192,%rdx jae L$192_or_more8x cmpq $128,%rdx jae L$128_or_more8x cmpq $64,%rdx jae L$64_or_more8x xorq %r10,%r10 vmovdqa %ymm6,0(%rsp) vmovdqa %ymm8,32(%rsp) jmp L$oop_tail8x .p2align 5 L$64_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) je L$done8x leaq 64(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm1,0(%rsp) leaq 64(%rdi),%rdi subq $64,%rdx vmovdqa %ymm5,32(%rsp) jmp L$oop_tail8x .p2align 5 L$128_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) je L$done8x leaq 128(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm12,0(%rsp) leaq 128(%rdi),%rdi subq $128,%rdx vmovdqa %ymm13,32(%rsp) jmp L$oop_tail8x .p2align 5 L$192_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vpxor 128(%rsi),%ymm12,%ymm12 vpxor 160(%rsi),%ymm13,%ymm13 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) vmovdqu %ymm12,128(%rdi) vmovdqu %ymm13,160(%rdi) je L$done8x leaq 192(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm10,0(%rsp) leaq 192(%rdi),%rdi subq $192,%rdx vmovdqa %ymm15,32(%rsp) jmp L$oop_tail8x .p2align 5 L$256_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vpxor 128(%rsi),%ymm12,%ymm12 vpxor 160(%rsi),%ymm13,%ymm13 vpxor 192(%rsi),%ymm10,%ymm10 vpxor 224(%rsi),%ymm15,%ymm15 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) vmovdqu %ymm12,128(%rdi) vmovdqu %ymm13,160(%rdi) vmovdqu %ymm10,192(%rdi) vmovdqu %ymm15,224(%rdi) je L$done8x leaq 256(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm14,0(%rsp) leaq 256(%rdi),%rdi subq $256,%rdx vmovdqa %ymm2,32(%rsp) jmp L$oop_tail8x .p2align 5 L$320_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vpxor 128(%rsi),%ymm12,%ymm12 vpxor 160(%rsi),%ymm13,%ymm13 vpxor 192(%rsi),%ymm10,%ymm10 vpxor 224(%rsi),%ymm15,%ymm15 vpxor 256(%rsi),%ymm14,%ymm14 vpxor 288(%rsi),%ymm2,%ymm2 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) vmovdqu %ymm12,128(%rdi) vmovdqu %ymm13,160(%rdi) vmovdqu %ymm10,192(%rdi) vmovdqu %ymm15,224(%rdi) vmovdqu %ymm14,256(%rdi) vmovdqu %ymm2,288(%rdi) je L$done8x leaq 320(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm3,0(%rsp) leaq 320(%rdi),%rdi subq $320,%rdx vmovdqa %ymm7,32(%rsp) jmp L$oop_tail8x .p2align 5 L$384_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vpxor 128(%rsi),%ymm12,%ymm12 vpxor 160(%rsi),%ymm13,%ymm13 vpxor 192(%rsi),%ymm10,%ymm10 vpxor 224(%rsi),%ymm15,%ymm15 vpxor 256(%rsi),%ymm14,%ymm14 vpxor 288(%rsi),%ymm2,%ymm2 vpxor 320(%rsi),%ymm3,%ymm3 vpxor 352(%rsi),%ymm7,%ymm7 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) vmovdqu %ymm12,128(%rdi) vmovdqu %ymm13,160(%rdi) vmovdqu %ymm10,192(%rdi) vmovdqu %ymm15,224(%rdi) vmovdqu %ymm14,256(%rdi) vmovdqu %ymm2,288(%rdi) vmovdqu %ymm3,320(%rdi) vmovdqu %ymm7,352(%rdi) je L$done8x leaq 384(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm11,0(%rsp) leaq 384(%rdi),%rdi subq $384,%rdx vmovdqa %ymm9,32(%rsp) jmp L$oop_tail8x .p2align 5 L$448_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vpxor 128(%rsi),%ymm12,%ymm12 vpxor 160(%rsi),%ymm13,%ymm13 vpxor 192(%rsi),%ymm10,%ymm10 vpxor 224(%rsi),%ymm15,%ymm15 vpxor 256(%rsi),%ymm14,%ymm14 vpxor 288(%rsi),%ymm2,%ymm2 vpxor 320(%rsi),%ymm3,%ymm3 vpxor 352(%rsi),%ymm7,%ymm7 vpxor 384(%rsi),%ymm11,%ymm11 vpxor 416(%rsi),%ymm9,%ymm9 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) vmovdqu %ymm12,128(%rdi) vmovdqu %ymm13,160(%rdi) vmovdqu %ymm10,192(%rdi) vmovdqu %ymm15,224(%rdi) vmovdqu %ymm14,256(%rdi) vmovdqu %ymm2,288(%rdi) vmovdqu %ymm3,320(%rdi) vmovdqu %ymm7,352(%rdi) vmovdqu %ymm11,384(%rdi) vmovdqu %ymm9,416(%rdi) je L$done8x leaq 448(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm0,0(%rsp) leaq 448(%rdi),%rdi subq $448,%rdx vmovdqa %ymm4,32(%rsp) L$oop_tail8x: movzbl (%rsi,%r10,1),%eax movzbl (%rsp,%r10,1),%ecx leaq 1(%r10),%r10 xorl %ecx,%eax movb %al,-1(%rdi,%r10,1) decq %rdx jnz L$oop_tail8x L$done8x: vzeroall leaq (%r9),%rsp L$8x_epilogue: ret #endif
j4yc3-mw/Viren	23,634	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/vpaes-armv7-linux32.S	// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__) .syntax unified .arch armv7-a .fpu neon #if defined(__thumb2__) .thumb #else .code 32 #endif .text .type _vpaes_consts,%object .align 7 @ totally strategic alignment _vpaes_consts: .Lk_mc_forward:@ mc_forward .quad 0x0407060500030201, 0x0C0F0E0D080B0A09 .quad 0x080B0A0904070605, 0x000302010C0F0E0D .quad 0x0C0F0E0D080B0A09, 0x0407060500030201 .quad 0x000302010C0F0E0D, 0x080B0A0904070605 .Lk_mc_backward:@ mc_backward .quad 0x0605040702010003, 0x0E0D0C0F0A09080B .quad 0x020100030E0D0C0F, 0x0A09080B06050407 .quad 0x0E0D0C0F0A09080B, 0x0605040702010003 .quad 0x0A09080B06050407, 0x020100030E0D0C0F .Lk_sr:@ sr .quad 0x0706050403020100, 0x0F0E0D0C0B0A0908 .quad 0x030E09040F0A0500, 0x0B06010C07020D08 .quad 0x0F060D040B020900, 0x070E050C030A0108 .quad 0x0B0E0104070A0D00, 0x0306090C0F020508 @ @ "Hot" constants @ .Lk_inv:@ inv, inva .quad 0x0E05060F0D080180, 0x040703090A0B0C02 .quad 0x01040A060F0B0780, 0x030D0E0C02050809 .Lk_ipt:@ input transform (lo, hi) .quad 0xC2B2E8985A2A7000, 0xCABAE09052227808 .quad 0x4C01307D317C4D00, 0xCD80B1FCB0FDCC81 .Lk_sbo:@ sbou, sbot .quad 0xD0D26D176FBDC700, 0x15AABF7AC502A878 .quad 0xCFE474A55FBB6A00, 0x8E1E90D1412B35FA .Lk_sb1:@ sb1u, sb1t .quad 0x3618D415FAE22300, 0x3BF7CCC10D2ED9EF .quad 0xB19BE18FCB503E00, 0xA5DF7A6E142AF544 .Lk_sb2:@ sb2u, sb2t .quad 0x69EB88400AE12900, 0xC2A163C8AB82234A .quad 0xE27A93C60B712400, 0x5EB7E955BC982FCD .byte 86,101,99,116,111,114,32,80,101,114,109,117,116,97,116,105,111,110,32,65,69,83,32,102,111,114,32,65,82,77,118,55,32,78,69,79,78,44,32,77,105,107,101,32,72,97,109,98,117,114,103,32,40,83,116,97,110,102,111,114,100,32,85,110,105,118,101,114,115,105,116,121,41,0 .align 2 .size _vpaes_consts,.-_vpaes_consts .align 6 @@ @@ _aes_preheat @@ @@ Fills q9-q15 as specified below. @@ .type _vpaes_preheat,%function .align 4 _vpaes_preheat: adr r10, .Lk_inv vmov.i8 q9, #0x0f @ .Lk_s0F vld1.64 {q10,q11}, [r10]! @ .Lk_inv add r10, r10, #64 @ Skip .Lk_ipt, .Lk_sbo vld1.64 {q12,q13}, [r10]! @ .Lk_sb1 vld1.64 {q14,q15}, [r10] @ .Lk_sb2 bx lr @@ @@ _aes_encrypt_core @@ @@ AES-encrypt q0. @@ @@ Inputs: @@ q0 = input @@ q9-q15 as in _vpaes_preheat @@ [r2] = scheduled keys @@ @@ Output in q0 @@ Clobbers q1-q5, r8-r11 @@ Preserves q6-q8 so you get some local vectors @@ @@ .type _vpaes_encrypt_core,%function .align 4 _vpaes_encrypt_core: mov r9, r2 ldr r8, [r2,#240] @ pull rounds adr r11, .Lk_ipt @ vmovdqa .Lk_ipt(%rip), %xmm2 # iptlo @ vmovdqa .Lk_ipt+16(%rip), %xmm3 # ipthi vld1.64 {q2, q3}, [r11] adr r11, .Lk_mc_forward+16 vld1.64 {q5}, [r9]! @ vmovdqu (%r9), %xmm5 # round0 key vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1 vtbl.8 d3, {q2}, d3 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2 vtbl.8 d5, {q3}, d1 veor q0, q1, q5 @ vpxor %xmm5, %xmm1, %xmm0 veor q0, q0, q2 @ vpxor %xmm2, %xmm0, %xmm0 @ .Lenc_entry ends with a bnz instruction which is normally paired with @ subs in .Lenc_loop. tst r8, r8 b .Lenc_entry .align 4 .Lenc_loop: @ middle of middle round add r10, r11, #0x40 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u vtbl.8 d9, {q13}, d5 vld1.64 {q1}, [r11]! @ vmovdqa -0x40(%r11,%r10), %xmm1 # .Lk_mc_forward[] vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t vtbl.8 d1, {q12}, d7 veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u vtbl.8 d11, {q15}, d5 veor q0, q0, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = A vtbl.8 d4, {q14}, d6 @ vpshufb %xmm3, %xmm14, %xmm2 # 2 = sb2t vtbl.8 d5, {q14}, d7 vld1.64 {q4}, [r10] @ vmovdqa (%r11,%r10), %xmm4 # .Lk_mc_backward[] vtbl.8 d6, {q0}, d2 @ vpshufb %xmm1, %xmm0, %xmm3 # 0 = B vtbl.8 d7, {q0}, d3 veor q2, q2, q5 @ vpxor %xmm5, %xmm2, %xmm2 # 2 = 2A @ Write to q5 instead of q0, so the table and destination registers do @ not overlap. vtbl.8 d10, {q0}, d8 @ vpshufb %xmm4, %xmm0, %xmm0 # 3 = D vtbl.8 d11, {q0}, d9 veor q3, q3, q2 @ vpxor %xmm2, %xmm3, %xmm3 # 0 = 2A+B vtbl.8 d8, {q3}, d2 @ vpshufb %xmm1, %xmm3, %xmm4 # 0 = 2B+C vtbl.8 d9, {q3}, d3 @ Here we restore the original q0/q5 usage. veor q0, q5, q3 @ vpxor %xmm3, %xmm0, %xmm0 # 3 = 2A+B+D and r11, r11, #~(1<<6) @ and $0x30, %r11 # ... mod 4 veor q0, q0, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = 2A+3B+C+D subs r8, r8, #1 @ nr-- .Lenc_entry: @ top of round vand q1, q0, q9 @ vpand %xmm0, %xmm9, %xmm1 # 0 = k vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 # 1 = i vtbl.8 d10, {q11}, d2 @ vpshufb %xmm1, %xmm11, %xmm5 # 2 = a/k vtbl.8 d11, {q11}, d3 veor q1, q1, q0 @ vpxor %xmm0, %xmm1, %xmm1 # 0 = j vtbl.8 d6, {q10}, d0 @ vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i vtbl.8 d7, {q10}, d1 vtbl.8 d8, {q10}, d2 @ vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j vtbl.8 d9, {q10}, d3 veor q3, q3, q5 @ vpxor %xmm5, %xmm3, %xmm3 # 3 = iak = 1/i + a/k veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = jak = 1/j + a/k vtbl.8 d4, {q10}, d6 @ vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak vtbl.8 d5, {q10}, d7 vtbl.8 d6, {q10}, d8 @ vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak vtbl.8 d7, {q10}, d9 veor q2, q2, q1 @ vpxor %xmm1, %xmm2, %xmm2 # 2 = io veor q3, q3, q0 @ vpxor %xmm0, %xmm3, %xmm3 # 3 = jo vld1.64 {q5}, [r9]! @ vmovdqu (%r9), %xmm5 bne .Lenc_loop @ middle of last round add r10, r11, #0x80 adr r11, .Lk_sbo @ Read to q1 instead of q4, so the vtbl.8 instruction below does not @ overlap table and destination registers. vld1.64 {q1}, [r11]! @ vmovdqa -0x60(%r10), %xmm4 # 3 : sbou vld1.64 {q0}, [r11] @ vmovdqa -0x50(%r10), %xmm0 # 0 : sbot .Lk_sbo+16 vtbl.8 d8, {q1}, d4 @ vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbou vtbl.8 d9, {q1}, d5 vld1.64 {q1}, [r10] @ vmovdqa 0x40(%r11,%r10), %xmm1 # .Lk_sr[] @ Write to q2 instead of q0 below, to avoid overlapping table and @ destination registers. vtbl.8 d4, {q0}, d6 @ vpshufb %xmm3, %xmm0, %xmm0 # 0 = sb1t vtbl.8 d5, {q0}, d7 veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k veor q2, q2, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = A @ Here we restore the original q0/q2 usage. vtbl.8 d0, {q2}, d2 @ vpshufb %xmm1, %xmm0, %xmm0 vtbl.8 d1, {q2}, d3 bx lr .size _vpaes_encrypt_core,.-_vpaes_encrypt_core .globl vpaes_encrypt .hidden vpaes_encrypt .type vpaes_encrypt,%function .align 4 vpaes_encrypt: @ _vpaes_encrypt_core uses r8-r11. Round up to r7-r11 to maintain stack @ alignment. stmdb sp!, {r7,r8,r9,r10,r11,lr} @ _vpaes_encrypt_core uses q4-q5 (d8-d11), which are callee-saved. vstmdb sp!, {d8,d9,d10,d11} vld1.64 {q0}, [r0] bl _vpaes_preheat bl _vpaes_encrypt_core vst1.64 {q0}, [r1] vldmia sp!, {d8,d9,d10,d11} ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return .size vpaes_encrypt,.-vpaes_encrypt @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @@ @@ @@ AES key schedule @@ @@ @@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @ This function diverges from both x86_64 and armv7 in which constants are @ pinned. x86_64 has a common preheat function for all operations. aarch64 @ separates them because it has enough registers to pin nearly all constants. @ armv7 does not have enough registers, but needing explicit loads and stores @ also complicates using x86_64's register allocation directly. @ @ We pin some constants for convenience and leave q14 and q15 free to load @ others on demand. @ @ Key schedule constants @ .type _vpaes_key_consts,%object .align 4 _vpaes_key_consts: .Lk_rcon:@ rcon .quad 0x1F8391B9AF9DEEB6, 0x702A98084D7C7D81 .Lk_opt:@ output transform .quad 0xFF9F4929D6B66000, 0xF7974121DEBE6808 .quad 0x01EDBD5150BCEC00, 0xE10D5DB1B05C0CE0 .Lk_deskew:@ deskew tables: inverts the sbox's "skew" .quad 0x07E4A34047A4E300, 0x1DFEB95A5DBEF91A .quad 0x5F36B5DC83EA6900, 0x2841C2ABF49D1E77 .size _vpaes_key_consts,.-_vpaes_key_consts .type _vpaes_key_preheat,%function .align 4 _vpaes_key_preheat: adr r11, .Lk_rcon vmov.i8 q12, #0x5b @ .Lk_s63 adr r10, .Lk_inv @ Must be aligned to 8 mod 16. vmov.i8 q9, #0x0f @ .Lk_s0F vld1.64 {q10,q11}, [r10] @ .Lk_inv vld1.64 {q8}, [r11] @ .Lk_rcon bx lr .size _vpaes_key_preheat,.-_vpaes_key_preheat .type _vpaes_schedule_core,%function .align 4 _vpaes_schedule_core: @ We only need to save lr, but ARM requires an 8-byte stack alignment, @ so save an extra register. stmdb sp!, {r3,lr} bl _vpaes_key_preheat @ load the tables adr r11, .Lk_ipt @ Must be aligned to 8 mod 16. vld1.64 {q0}, [r0]! @ vmovdqu (%rdi), %xmm0 # load key (unaligned) @ input transform @ Use q4 here rather than q3 so .Lschedule_am_decrypting does not @ overlap table and destination. vmov q4, q0 @ vmovdqa %xmm0, %xmm3 bl _vpaes_schedule_transform adr r10, .Lk_sr @ Must be aligned to 8 mod 16. vmov q7, q0 @ vmovdqa %xmm0, %xmm7 add r8, r8, r10 @ encrypting, output zeroth round key after transform vst1.64 {q0}, [r2] @ vmovdqu %xmm0, (%rdx) @ ring: Decryption removed. .Lschedule_go: cmp r1, #192 @ cmp $192, %esi bhi .Lschedule_256 @ 128: fall though @@ @@ .schedule_128 @@ @@ 128-bit specific part of key schedule. @@ @@ This schedule is really simple, because all its parts @@ are accomplished by the subroutines. @@ .Lschedule_128: mov r0, #10 @ mov $10, %esi .Loop_schedule_128: bl _vpaes_schedule_round subs r0, r0, #1 @ dec %esi beq .Lschedule_mangle_last bl _vpaes_schedule_mangle @ write output b .Loop_schedule_128 @@ @@ .aes_schedule_256 @@ @@ 256-bit specific part of key schedule. @@ @@ The structure here is very similar to the 128-bit @@ schedule, but with an additional "low side" in @@ q6. The low side's rounds are the same as the @@ high side's, except no rcon and no rotation. @@ .align 4 .Lschedule_256: vld1.64 {q0}, [r0] @ vmovdqu 16(%rdi),%xmm0 # load key part 2 (unaligned) bl _vpaes_schedule_transform @ input transform mov r0, #7 @ mov $7, %esi .Loop_schedule_256: bl _vpaes_schedule_mangle @ output low result vmov q6, q0 @ vmovdqa %xmm0, %xmm6 # save cur_lo in xmm6 @ high round bl _vpaes_schedule_round subs r0, r0, #1 @ dec %esi beq .Lschedule_mangle_last bl _vpaes_schedule_mangle @ low round. swap xmm7 and xmm6 vdup.32 q0, d1[1] @ vpshufd $0xFF, %xmm0, %xmm0 vmov.i8 q4, #0 vmov q5, q7 @ vmovdqa %xmm7, %xmm5 vmov q7, q6 @ vmovdqa %xmm6, %xmm7 bl _vpaes_schedule_low_round vmov q7, q5 @ vmovdqa %xmm5, %xmm7 b .Loop_schedule_256 @@ @@ .aes_schedule_mangle_last @@ @@ Mangler for last round of key schedule @@ Mangles q0 @@ when encrypting, outputs out(q0) ^ 63 @@ when decrypting, outputs unskew(q0) @@ @@ Always called right before return... jumps to cleanup and exits @@ .align 4 .Lschedule_mangle_last: @ schedule last round key from xmm0 adr r11, .Lk_deskew @ lea .Lk_deskew(%rip),%r11 # prepare to deskew @ encrypting vld1.64 {q1}, [r8] @ vmovdqa (%r8,%r10),%xmm1 adr r11, .Lk_opt @ lea .Lk_opt(%rip), %r11 # prepare to output transform add r2, r2, #32 @ add $32, %rdx vmov q2, q0 vtbl.8 d0, {q2}, d2 @ vpshufb %xmm1, %xmm0, %xmm0 # output permute vtbl.8 d1, {q2}, d3 .Lschedule_mangle_last_dec: sub r2, r2, #16 @ add $-16, %rdx veor q0, q0, q12 @ vpxor .Lk_s63(%rip), %xmm0, %xmm0 bl _vpaes_schedule_transform @ output transform vst1.64 {q0}, [r2] @ vmovdqu %xmm0, (%rdx) # save last key @ cleanup veor q0, q0, q0 @ vpxor %xmm0, %xmm0, %xmm0 veor q1, q1, q1 @ vpxor %xmm1, %xmm1, %xmm1 veor q2, q2, q2 @ vpxor %xmm2, %xmm2, %xmm2 veor q3, q3, q3 @ vpxor %xmm3, %xmm3, %xmm3 veor q4, q4, q4 @ vpxor %xmm4, %xmm4, %xmm4 veor q5, q5, q5 @ vpxor %xmm5, %xmm5, %xmm5 veor q6, q6, q6 @ vpxor %xmm6, %xmm6, %xmm6 veor q7, q7, q7 @ vpxor %xmm7, %xmm7, %xmm7 ldmia sp!, {r3,pc} @ return .size _vpaes_schedule_core,.-_vpaes_schedule_core @@ @@ .aes_schedule_round @@ @@ Runs one main round of the key schedule on q0, q7 @@ @@ Specifically, runs subbytes on the high dword of q0 @@ then rotates it by one byte and xors into the low dword of @@ q7. @@ @@ Adds rcon from low byte of q8, then rotates q8 for @@ next rcon. @@ @@ Smears the dwords of q7 by xoring the low into the @@ second low, result into third, result into highest. @@ @@ Returns results in q7 = q0. @@ Clobbers q1-q4, r11. @@ .type _vpaes_schedule_round,%function .align 4 _vpaes_schedule_round: @ extract rcon from xmm8 vmov.i8 q4, #0 @ vpxor %xmm4, %xmm4, %xmm4 vext.8 q1, q8, q4, #15 @ vpalignr $15, %xmm8, %xmm4, %xmm1 vext.8 q8, q8, q8, #15 @ vpalignr $15, %xmm8, %xmm8, %xmm8 veor q7, q7, q1 @ vpxor %xmm1, %xmm7, %xmm7 @ rotate vdup.32 q0, d1[1] @ vpshufd $0xFF, %xmm0, %xmm0 vext.8 q0, q0, q0, #1 @ vpalignr $1, %xmm0, %xmm0, %xmm0 @ fall through... @ low round: same as high round, but no rotation and no rcon. _vpaes_schedule_low_round: @ The x86_64 version pins .Lk_sb1 in %xmm13 and .Lk_sb1+16 in %xmm12. @ We pin other values in _vpaes_key_preheat, so load them now. adr r11, .Lk_sb1 vld1.64 {q14,q15}, [r11] @ smear xmm7 vext.8 q1, q4, q7, #12 @ vpslldq $4, %xmm7, %xmm1 veor q7, q7, q1 @ vpxor %xmm1, %xmm7, %xmm7 vext.8 q4, q4, q7, #8 @ vpslldq $8, %xmm7, %xmm4 @ subbytes vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 # 0 = k vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 # 1 = i veor q7, q7, q4 @ vpxor %xmm4, %xmm7, %xmm7 vtbl.8 d4, {q11}, d2 @ vpshufb %xmm1, %xmm11, %xmm2 # 2 = a/k vtbl.8 d5, {q11}, d3 veor q1, q1, q0 @ vpxor %xmm0, %xmm1, %xmm1 # 0 = j vtbl.8 d6, {q10}, d0 @ vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i vtbl.8 d7, {q10}, d1 veor q3, q3, q2 @ vpxor %xmm2, %xmm3, %xmm3 # 3 = iak = 1/i + a/k vtbl.8 d8, {q10}, d2 @ vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j vtbl.8 d9, {q10}, d3 veor q7, q7, q12 @ vpxor .Lk_s63(%rip), %xmm7, %xmm7 vtbl.8 d6, {q10}, d6 @ vpshufb %xmm3, %xmm10, %xmm3 # 2 = 1/iak vtbl.8 d7, {q10}, d7 veor q4, q4, q2 @ vpxor %xmm2, %xmm4, %xmm4 # 4 = jak = 1/j + a/k vtbl.8 d4, {q10}, d8 @ vpshufb %xmm4, %xmm10, %xmm2 # 3 = 1/jak vtbl.8 d5, {q10}, d9 veor q3, q3, q1 @ vpxor %xmm1, %xmm3, %xmm3 # 2 = io veor q2, q2, q0 @ vpxor %xmm0, %xmm2, %xmm2 # 3 = jo vtbl.8 d8, {q15}, d6 @ vpshufb %xmm3, %xmm13, %xmm4 # 4 = sbou vtbl.8 d9, {q15}, d7 vtbl.8 d2, {q14}, d4 @ vpshufb %xmm2, %xmm12, %xmm1 # 0 = sb1t vtbl.8 d3, {q14}, d5 veor q1, q1, q4 @ vpxor %xmm4, %xmm1, %xmm1 # 0 = sbox output @ add in smeared stuff veor q0, q1, q7 @ vpxor %xmm7, %xmm1, %xmm0 veor q7, q1, q7 @ vmovdqa %xmm0, %xmm7 bx lr .size _vpaes_schedule_round,.-_vpaes_schedule_round @@ @@ .aes_schedule_transform @@ @@ Linear-transform q0 according to tables at [r11] @@ @@ Requires that q9 = 0x0F0F... as in preheat @@ Output in q0 @@ Clobbers q1, q2, q14, q15 @@ .type _vpaes_schedule_transform,%function .align 4 _vpaes_schedule_transform: vld1.64 {q14,q15}, [r11] @ vmovdqa (%r11), %xmm2 # lo @ vmovdqa 16(%r11), %xmm1 # hi vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 vtbl.8 d4, {q14}, d2 @ vpshufb %xmm1, %xmm2, %xmm2 vtbl.8 d5, {q14}, d3 vtbl.8 d0, {q15}, d0 @ vpshufb %xmm0, %xmm1, %xmm0 vtbl.8 d1, {q15}, d1 veor q0, q0, q2 @ vpxor %xmm2, %xmm0, %xmm0 bx lr .size _vpaes_schedule_transform,.-_vpaes_schedule_transform @@ @@ .aes_schedule_mangle @@ @@ Mangles q0 from (basis-transformed) standard version @@ to our version. @@ @@ On encrypt, @@ xor with 0x63 @@ multiply by circulant 0,1,1,1 @@ apply shiftrows transform @@ @@ On decrypt, @@ xor with 0x63 @@ multiply by "inverse mixcolumns" circulant E,B,D,9 @@ deskew @@ apply shiftrows transform @@ @@ @@ Writes out to [r2], and increments or decrements it @@ Keeps track of round number mod 4 in r8 @@ Preserves q0 @@ Clobbers q1-q5 @@ .type _vpaes_schedule_mangle,%function .align 4 _vpaes_schedule_mangle: tst r3, r3 vmov q4, q0 @ vmovdqa %xmm0, %xmm4 # save xmm0 for later adr r11, .Lk_mc_forward @ Must be aligned to 8 mod 16. vld1.64 {q5}, [r11] @ vmovdqa .Lk_mc_forward(%rip),%xmm5 @ encrypting @ Write to q2 so we do not overlap table and destination below. veor q2, q0, q12 @ vpxor .Lk_s63(%rip), %xmm0, %xmm4 add r2, r2, #16 @ add $16, %rdx vtbl.8 d8, {q2}, d10 @ vpshufb %xmm5, %xmm4, %xmm4 vtbl.8 d9, {q2}, d11 vtbl.8 d2, {q4}, d10 @ vpshufb %xmm5, %xmm4, %xmm1 vtbl.8 d3, {q4}, d11 vtbl.8 d6, {q1}, d10 @ vpshufb %xmm5, %xmm1, %xmm3 vtbl.8 d7, {q1}, d11 veor q4, q4, q1 @ vpxor %xmm1, %xmm4, %xmm4 vld1.64 {q1}, [r8] @ vmovdqa (%r8,%r10), %xmm1 veor q3, q3, q4 @ vpxor %xmm4, %xmm3, %xmm3 .Lschedule_mangle_both: @ Write to q2 so table and destination do not overlap. vtbl.8 d4, {q3}, d2 @ vpshufb %xmm1, %xmm3, %xmm3 vtbl.8 d5, {q3}, d3 add r8, r8, #64-16 @ add $-16, %r8 and r8, r8, #~(1<<6) @ and $0x30, %r8 vst1.64 {q2}, [r2] @ vmovdqu %xmm3, (%rdx) bx lr .size _vpaes_schedule_mangle,.-_vpaes_schedule_mangle .globl vpaes_set_encrypt_key .hidden vpaes_set_encrypt_key .type vpaes_set_encrypt_key,%function .align 4 vpaes_set_encrypt_key: stmdb sp!, {r7,r8,r9,r10,r11, lr} vstmdb sp!, {d8,d9,d10,d11,d12,d13,d14,d15} lsr r9, r1, #5 @ shr $5,%eax add r9, r9, #5 @ $5,%eax str r9, [r2,#240] @ mov %eax,240(%rdx) # AES_KEY->rounds = nbits/32+5; mov r3, #0 @ mov $0,%ecx mov r8, #0x30 @ mov $0x30,%r8d bl _vpaes_schedule_core eor r0, r0, r0 vldmia sp!, {d8,d9,d10,d11,d12,d13,d14,d15} ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return .size vpaes_set_encrypt_key,.-vpaes_set_encrypt_key @ Additional constants for converting to bsaes. .type _vpaes_convert_consts,%object .align 4 _vpaes_convert_consts: @ .Lk_opt_then_skew applies skew(opt(x)) XOR 0x63, where skew is the linear @ transform in the AES S-box. 0x63 is incorporated into the low half of the @ table. This was computed with the following script: @ @ def u64s_to_u128(x, y): @ return x \| (y << 64) @ def u128_to_u64s(w): @ return w & ((1<<64)-1), w >> 64 @ def get_byte(w, i): @ return (w >> (i8)) & 0xff @ def apply_table(table, b): @ lo = b & 0xf @ hi = b >> 4 @ return get_byte(table[0], lo) ^ get_byte(table[1], hi) @ def opt(b): @ table = [ @ u64s_to_u128(0xFF9F4929D6B66000, 0xF7974121DEBE6808), @ u64s_to_u128(0x01EDBD5150BCEC00, 0xE10D5DB1B05C0CE0), @ ] @ return apply_table(table, b) @ def rot_byte(b, n): @ return 0xff & ((b << n) \| (b >> (8-n))) @ def skew(x): @ return (x ^ rot_byte(x, 1) ^ rot_byte(x, 2) ^ rot_byte(x, 3) ^ @ rot_byte(x, 4)) @ table = [0, 0] @ for i in range(16): @ table[0] \|= (skew(opt(i)) ^ 0x63) << (i8) @ table[1] \|= skew(opt(i<<4)) << (i8) @ print(" .quad 0x%016x, 0x%016x" % u128_to_u64s(table[0])) @ print(" .quad 0x%016x, 0x%016x" % u128_to_u64s(table[1])) .Lk_opt_then_skew: .quad 0x9cb8436798bc4763, 0x6440bb9f6044bf9b .quad 0x1f30062936192f00, 0xb49bad829db284ab @ void vpaes_encrypt_key_to_bsaes(AES_KEY bsaes, const AES_KEY vpaes); .globl vpaes_encrypt_key_to_bsaes .hidden vpaes_encrypt_key_to_bsaes .type vpaes_encrypt_key_to_bsaes,%function .align 4 vpaes_encrypt_key_to_bsaes: stmdb sp!, {r11, lr} @ See _vpaes_schedule_core for the key schedule logic. In particular, @ _vpaes_schedule_transform(.Lk_ipt) (section 2.2 of the paper), @ _vpaes_schedule_mangle (section 4.3), and .Lschedule_mangle_last @ contain the transformations not in the bsaes representation. This @ function inverts those transforms. @ @ Note also that bsaes-armv7.pl expects aes-armv4.pl's key @ representation, which does not match the other aes_nohw_ @ implementations. The ARM aes_nohw_* stores each 32-bit word @ byteswapped, as a convenience for (unsupported) big-endian ARM, at the @ cost of extra REV and VREV32 operations in little-endian ARM. vmov.i8 q9, #0x0f @ Required by _vpaes_schedule_transform adr r2, .Lk_mc_forward @ Must be aligned to 8 mod 16. add r3, r2, 0x90 @ .Lk_sr+0x10-.Lk_mc_forward = 0x90 (Apple's toolchain doesn't support the expression) vld1.64 {q12}, [r2] vmov.i8 q10, #0x5b @ .Lk_s63 from vpaes-x86_64 adr r11, .Lk_opt @ Must be aligned to 8 mod 16. vmov.i8 q11, #0x63 @ .LK_s63 without .Lk_ipt applied @ vpaes stores one fewer round count than bsaes, but the number of keys @ is the same. ldr r2, [r1,#240] add r2, r2, #1 str r2, [r0,#240] @ The first key is transformed with _vpaes_schedule_transform(.Lk_ipt). @ Invert this with .Lk_opt. vld1.64 {q0}, [r1]! bl _vpaes_schedule_transform vrev32.8 q0, q0 vst1.64 {q0}, [r0]! @ The middle keys have _vpaes_schedule_transform(.Lk_ipt) applied, @ followed by _vpaes_schedule_mangle. _vpaes_schedule_mangle XORs 0x63, @ multiplies by the circulant 0,1,1,1, then applies ShiftRows. .Loop_enc_key_to_bsaes: vld1.64 {q0}, [r1]! @ Invert the ShiftRows step (see .Lschedule_mangle_both). Note we cycle @ r3 in the opposite direction and start at .Lk_sr+0x10 instead of 0x30. @ We use r3 rather than r8 to avoid a callee-saved register. vld1.64 {q1}, [r3] vtbl.8 d4, {q0}, d2 vtbl.8 d5, {q0}, d3 add r3, r3, #16 and r3, r3, #~(1<<6) vmov q0, q2 @ Handle the last key differently. subs r2, r2, #1 beq .Loop_enc_key_to_bsaes_last @ Multiply by the circulant. This is its own inverse. vtbl.8 d2, {q0}, d24 vtbl.8 d3, {q0}, d25 vmov q0, q1 vtbl.8 d4, {q1}, d24 vtbl.8 d5, {q1}, d25 veor q0, q0, q2 vtbl.8 d2, {q2}, d24 vtbl.8 d3, {q2}, d25 veor q0, q0, q1 @ XOR and finish. veor q0, q0, q10 bl _vpaes_schedule_transform vrev32.8 q0, q0 vst1.64 {q0}, [r0]! b .Loop_enc_key_to_bsaes .Loop_enc_key_to_bsaes_last: @ The final key does not have a basis transform (note @ .Lschedule_mangle_last inverts the original transform). It only XORs @ 0x63 and applies ShiftRows. The latter was already inverted in the @ loop. Note that, because we act on the original representation, we use @ q11, not q10. veor q0, q0, q11 vrev32.8 q0, q0 vst1.64 {q0}, [r0] @ Wipe registers which contained key material. veor q0, q0, q0 veor q1, q1, q1 veor q2, q2, q2 ldmia sp!, {r11, pc} @ return .size vpaes_encrypt_key_to_bsaes,.-vpaes_encrypt_key_to_bsaes .globl vpaes_ctr32_encrypt_blocks .hidden vpaes_ctr32_encrypt_blocks .type vpaes_ctr32_encrypt_blocks,%function .align 4 vpaes_ctr32_encrypt_blocks: mov ip, sp stmdb sp!, {r7,r8,r9,r10,r11, lr} @ This function uses q4-q7 (d8-d15), which are callee-saved. vstmdb sp!, {d8,d9,d10,d11,d12,d13,d14,d15} cmp r2, #0 @ r8 is passed on the stack. ldr r8, [ip] beq .Lctr32_done @ _vpaes_encrypt_core expects the key in r2, so swap r2 and r3. mov r9, r3 mov r3, r2 mov r2, r9 @ Load the IV and counter portion. ldr r7, [r8, #12] vld1.8 {q7}, [r8] bl _vpaes_preheat rev r7, r7 @ The counter is big-endian. .Lctr32_loop: vmov q0, q7 vld1.8 {q6}, [r0]! @ .Load input ahead of time bl _vpaes_encrypt_core veor q0, q0, q6 @ XOR input and result vst1.8 {q0}, [r1]! subs r3, r3, #1 @ Update the counter. add r7, r7, #1 rev r9, r7 vmov.32 d15[1], r9 bne .Lctr32_loop .Lctr32_done: vldmia sp!, {d8,d9,d10,d11,d12,d13,d14,d15} ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return .size vpaes_ctr32_encrypt_blocks,.-vpaes_ctr32_encrypt_blocks #endif // !OPENSSL_NO_ASM && defined(OPENSSL_ARM) && defined(__ELF__)
j4yc3-mw/Viren	58,542	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/x86_64-mont5-elf.S	// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__ELF__) .text .extern OPENSSL_ia32cap_P .hidden OPENSSL_ia32cap_P .globl bn_mul_mont_gather5 .hidden bn_mul_mont_gather5 .type bn_mul_mont_gather5,@function .align 64 bn_mul_mont_gather5: .cfi_startproc _CET_ENDBR movl %r9d,%r9d movq %rsp,%rax .cfi_def_cfa_register %rax testl $7,%r9d jnz .Lmul_enter leaq OPENSSL_ia32cap_P(%rip),%r11 movl 8(%r11),%r11d jmp .Lmul4x_enter .align 16 .Lmul_enter: movd 8(%rsp),%xmm5 pushq %rbx .cfi_offset %rbx,-16 pushq %rbp .cfi_offset %rbp,-24 pushq %r12 .cfi_offset %r12,-32 pushq %r13 .cfi_offset %r13,-40 pushq %r14 .cfi_offset %r14,-48 pushq %r15 .cfi_offset %r15,-56 negq %r9 movq %rsp,%r11 leaq -280(%rsp,%r9,8),%r10 negq %r9 andq $-1024,%r10 subq %r10,%r11 andq $-4096,%r11 leaq (%r10,%r11,1),%rsp movq (%rsp),%r11 cmpq %r10,%rsp ja .Lmul_page_walk jmp .Lmul_page_walk_done .Lmul_page_walk: leaq -4096(%rsp),%rsp movq (%rsp),%r11 cmpq %r10,%rsp ja .Lmul_page_walk .Lmul_page_walk_done: leaq .Linc(%rip),%r10 movq %rax,8(%rsp,%r9,8) .cfi_escape 0x0f,0x0a,0x77,0x08,0x79,0x00,0x38,0x1e,0x22,0x06,0x23,0x08 .Lmul_body: leaq 128(%rdx),%r12 movdqa 0(%r10),%xmm0 movdqa 16(%r10),%xmm1 leaq 24-112(%rsp,%r9,8),%r10 andq $-16,%r10 pshufd $0,%xmm5,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm1,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 .byte 0x67 movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,112(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,128(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,144(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,160(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,176(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,192(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,208(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,224(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,240(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,256(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,272(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,288(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,304(%r10) paddd %xmm2,%xmm3 .byte 0x67 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,320(%r10) pcmpeqd %xmm5,%xmm3 movdqa %xmm2,336(%r10) pand 64(%r12),%xmm0 pand 80(%r12),%xmm1 pand 96(%r12),%xmm2 movdqa %xmm3,352(%r10) pand 112(%r12),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -128(%r12),%xmm4 movdqa -112(%r12),%xmm5 movdqa -96(%r12),%xmm2 pand 112(%r10),%xmm4 movdqa -80(%r12),%xmm3 pand 128(%r10),%xmm5 por %xmm4,%xmm0 pand 144(%r10),%xmm2 por %xmm5,%xmm1 pand 160(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -64(%r12),%xmm4 movdqa -48(%r12),%xmm5 movdqa -32(%r12),%xmm2 pand 176(%r10),%xmm4 movdqa -16(%r12),%xmm3 pand 192(%r10),%xmm5 por %xmm4,%xmm0 pand 208(%r10),%xmm2 por %xmm5,%xmm1 pand 224(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa 0(%r12),%xmm4 movdqa 16(%r12),%xmm5 movdqa 32(%r12),%xmm2 pand 240(%r10),%xmm4 movdqa 48(%r12),%xmm3 pand 256(%r10),%xmm5 por %xmm4,%xmm0 pand 272(%r10),%xmm2 por %xmm5,%xmm1 pand 288(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 por %xmm1,%xmm0 pshufd $0x4e,%xmm0,%xmm1 por %xmm1,%xmm0 leaq 256(%r12),%r12 .byte 102,72,15,126,195 movq (%r8),%r8 movq (%rsi),%rax xorq %r14,%r14 xorq %r15,%r15 movq %r8,%rbp mulq %rbx movq %rax,%r10 movq (%rcx),%rax imulq %r10,%rbp movq %rdx,%r11 mulq %rbp addq %rax,%r10 movq 8(%rsi),%rax adcq $0,%rdx movq %rdx,%r13 leaq 1(%r15),%r15 jmp .L1st_enter .align 16 .L1st: addq %rax,%r13 movq (%rsi,%r15,8),%rax adcq $0,%rdx addq %r11,%r13 movq %r10,%r11 adcq $0,%rdx movq %r13,-16(%rsp,%r15,8) movq %rdx,%r13 .L1st_enter: mulq %rbx addq %rax,%r11 movq (%rcx,%r15,8),%rax adcq $0,%rdx leaq 1(%r15),%r15 movq %rdx,%r10 mulq %rbp cmpq %r9,%r15 jne .L1st addq %rax,%r13 adcq $0,%rdx addq %r11,%r13 adcq $0,%rdx movq %r13,-16(%rsp,%r9,8) movq %rdx,%r13 movq %r10,%r11 xorq %rdx,%rdx addq %r11,%r13 adcq $0,%rdx movq %r13,-8(%rsp,%r9,8) movq %rdx,(%rsp,%r9,8) leaq 1(%r14),%r14 jmp .Louter .align 16 .Louter: leaq 24+128(%rsp,%r9,8),%rdx andq $-16,%rdx pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 movdqa -128(%r12),%xmm0 movdqa -112(%r12),%xmm1 movdqa -96(%r12),%xmm2 movdqa -80(%r12),%xmm3 pand -128(%rdx),%xmm0 pand -112(%rdx),%xmm1 por %xmm0,%xmm4 pand -96(%rdx),%xmm2 por %xmm1,%xmm5 pand -80(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa -64(%r12),%xmm0 movdqa -48(%r12),%xmm1 movdqa -32(%r12),%xmm2 movdqa -16(%r12),%xmm3 pand -64(%rdx),%xmm0 pand -48(%rdx),%xmm1 por %xmm0,%xmm4 pand -32(%rdx),%xmm2 por %xmm1,%xmm5 pand -16(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 0(%r12),%xmm0 movdqa 16(%r12),%xmm1 movdqa 32(%r12),%xmm2 movdqa 48(%r12),%xmm3 pand 0(%rdx),%xmm0 pand 16(%rdx),%xmm1 por %xmm0,%xmm4 pand 32(%rdx),%xmm2 por %xmm1,%xmm5 pand 48(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 64(%r12),%xmm0 movdqa 80(%r12),%xmm1 movdqa 96(%r12),%xmm2 movdqa 112(%r12),%xmm3 pand 64(%rdx),%xmm0 pand 80(%rdx),%xmm1 por %xmm0,%xmm4 pand 96(%rdx),%xmm2 por %xmm1,%xmm5 pand 112(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 por %xmm5,%xmm4 pshufd $0x4e,%xmm4,%xmm0 por %xmm4,%xmm0 leaq 256(%r12),%r12 movq (%rsi),%rax .byte 102,72,15,126,195 xorq %r15,%r15 movq %r8,%rbp movq (%rsp),%r10 mulq %rbx addq %rax,%r10 movq (%rcx),%rax adcq $0,%rdx imulq %r10,%rbp movq %rdx,%r11 mulq %rbp addq %rax,%r10 movq 8(%rsi),%rax adcq $0,%rdx movq 8(%rsp),%r10 movq %rdx,%r13 leaq 1(%r15),%r15 jmp .Linner_enter .align 16 .Linner: addq %rax,%r13 movq (%rsi,%r15,8),%rax adcq $0,%rdx addq %r10,%r13 movq (%rsp,%r15,8),%r10 adcq $0,%rdx movq %r13,-16(%rsp,%r15,8) movq %rdx,%r13 .Linner_enter: mulq %rbx addq %rax,%r11 movq (%rcx,%r15,8),%rax adcq $0,%rdx addq %r11,%r10 movq %rdx,%r11 adcq $0,%r11 leaq 1(%r15),%r15 mulq %rbp cmpq %r9,%r15 jne .Linner addq %rax,%r13 adcq $0,%rdx addq %r10,%r13 movq (%rsp,%r9,8),%r10 adcq $0,%rdx movq %r13,-16(%rsp,%r9,8) movq %rdx,%r13 xorq %rdx,%rdx addq %r11,%r13 adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %r13,-8(%rsp,%r9,8) movq %rdx,(%rsp,%r9,8) leaq 1(%r14),%r14 cmpq %r9,%r14 jb .Louter xorq %r14,%r14 movq (%rsp),%rax leaq (%rsp),%rsi movq %r9,%r15 jmp .Lsub .align 16 .Lsub: sbbq (%rcx,%r14,8),%rax movq %rax,(%rdi,%r14,8) movq 8(%rsi,%r14,8),%rax leaq 1(%r14),%r14 decq %r15 jnz .Lsub sbbq $0,%rax movq $-1,%rbx xorq %rax,%rbx xorq %r14,%r14 movq %r9,%r15 .Lcopy: movq (%rdi,%r14,8),%rcx movq (%rsp,%r14,8),%rdx andq %rbx,%rcx andq %rax,%rdx movq %r14,(%rsp,%r14,8) orq %rcx,%rdx movq %rdx,(%rdi,%r14,8) leaq 1(%r14),%r14 subq $1,%r15 jnz .Lcopy movq 8(%rsp,%r9,8),%rsi .cfi_def_cfa %rsi,8 movq $1,%rax movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbp .cfi_restore %rbp movq -8(%rsi),%rbx .cfi_restore %rbx leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lmul_epilogue: ret .cfi_endproc .size bn_mul_mont_gather5,.-bn_mul_mont_gather5 .type bn_mul4x_mont_gather5,@function .align 32 bn_mul4x_mont_gather5: .cfi_startproc .byte 0x67 movq %rsp,%rax .cfi_def_cfa_register %rax .Lmul4x_enter: andl $0x80108,%r11d cmpl $0x80108,%r11d je .Lmulx4x_enter pushq %rbx .cfi_offset %rbx,-16 pushq %rbp .cfi_offset %rbp,-24 pushq %r12 .cfi_offset %r12,-32 pushq %r13 .cfi_offset %r13,-40 pushq %r14 .cfi_offset %r14,-48 pushq %r15 .cfi_offset %r15,-56 .Lmul4x_prologue: .byte 0x67 shll $3,%r9d leaq (%r9,%r9,2),%r10 negq %r9 leaq -320(%rsp,%r9,2),%r11 movq %rsp,%rbp subq %rdi,%r11 andq $4095,%r11 cmpq %r11,%r10 jb .Lmul4xsp_alt subq %r11,%rbp leaq -320(%rbp,%r9,2),%rbp jmp .Lmul4xsp_done .align 32 .Lmul4xsp_alt: leaq 4096-320(,%r9,2),%r10 leaq -320(%rbp,%r9,2),%rbp subq %r10,%r11 movq $0,%r10 cmovcq %r10,%r11 subq %r11,%rbp .Lmul4xsp_done: andq $-64,%rbp movq %rsp,%r11 subq %rbp,%r11 andq $-4096,%r11 leaq (%r11,%rbp,1),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lmul4x_page_walk jmp .Lmul4x_page_walk_done .Lmul4x_page_walk: leaq -4096(%rsp),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lmul4x_page_walk .Lmul4x_page_walk_done: negq %r9 movq %rax,40(%rsp) .cfi_escape 0x0f,0x05,0x77,0x28,0x06,0x23,0x08 .Lmul4x_body: call mul4x_internal movq 40(%rsp),%rsi .cfi_def_cfa %rsi,8 movq $1,%rax movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbp .cfi_restore %rbp movq -8(%rsi),%rbx .cfi_restore %rbx leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lmul4x_epilogue: ret .cfi_endproc .size bn_mul4x_mont_gather5,.-bn_mul4x_mont_gather5 .type mul4x_internal,@function .align 32 mul4x_internal: .cfi_startproc shlq $5,%r9 movd 8(%rax),%xmm5 leaq .Linc(%rip),%rax leaq 128(%rdx,%r9,1),%r13 shrq $5,%r9 movdqa 0(%rax),%xmm0 movdqa 16(%rax),%xmm1 leaq 88-112(%rsp,%r9,1),%r10 leaq 128(%rdx),%r12 pshufd $0,%xmm5,%xmm5 movdqa %xmm1,%xmm4 .byte 0x67,0x67 movdqa %xmm1,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 .byte 0x67 movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,112(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,128(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,144(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,160(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,176(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,192(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,208(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,224(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,240(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,256(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,272(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,288(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,304(%r10) paddd %xmm2,%xmm3 .byte 0x67 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,320(%r10) pcmpeqd %xmm5,%xmm3 movdqa %xmm2,336(%r10) pand 64(%r12),%xmm0 pand 80(%r12),%xmm1 pand 96(%r12),%xmm2 movdqa %xmm3,352(%r10) pand 112(%r12),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -128(%r12),%xmm4 movdqa -112(%r12),%xmm5 movdqa -96(%r12),%xmm2 pand 112(%r10),%xmm4 movdqa -80(%r12),%xmm3 pand 128(%r10),%xmm5 por %xmm4,%xmm0 pand 144(%r10),%xmm2 por %xmm5,%xmm1 pand 160(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -64(%r12),%xmm4 movdqa -48(%r12),%xmm5 movdqa -32(%r12),%xmm2 pand 176(%r10),%xmm4 movdqa -16(%r12),%xmm3 pand 192(%r10),%xmm5 por %xmm4,%xmm0 pand 208(%r10),%xmm2 por %xmm5,%xmm1 pand 224(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa 0(%r12),%xmm4 movdqa 16(%r12),%xmm5 movdqa 32(%r12),%xmm2 pand 240(%r10),%xmm4 movdqa 48(%r12),%xmm3 pand 256(%r10),%xmm5 por %xmm4,%xmm0 pand 272(%r10),%xmm2 por %xmm5,%xmm1 pand 288(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 por %xmm1,%xmm0 pshufd $0x4e,%xmm0,%xmm1 por %xmm1,%xmm0 leaq 256(%r12),%r12 .byte 102,72,15,126,195 movq %r13,16+8(%rsp) movq %rdi,56+8(%rsp) movq (%r8),%r8 movq (%rsi),%rax leaq (%rsi,%r9,1),%rsi negq %r9 movq %r8,%rbp mulq %rbx movq %rax,%r10 movq (%rcx),%rax imulq %r10,%rbp leaq 64+8(%rsp),%r14 movq %rdx,%r11 mulq %rbp addq %rax,%r10 movq 8(%rsi,%r9,1),%rax adcq $0,%rdx movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq 8(%rcx),%rax adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq 16(%rsi,%r9,1),%rax adcq $0,%rdx addq %r11,%rdi leaq 32(%r9),%r15 leaq 32(%rcx),%rcx adcq $0,%rdx movq %rdi,(%r14) movq %rdx,%r13 jmp .L1st4x .align 32 .L1st4x: mulq %rbx addq %rax,%r10 movq -16(%rcx),%rax leaq 32(%r14),%r14 adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq -8(%rsi,%r15,1),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %r13,-24(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq -8(%rcx),%rax adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq (%rsi,%r15,1),%rax adcq $0,%rdx addq %r11,%rdi adcq $0,%rdx movq %rdi,-16(%r14) movq %rdx,%r13 mulq %rbx addq %rax,%r10 movq 0(%rcx),%rax adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq 8(%rsi,%r15,1),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %r13,-8(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq 8(%rcx),%rax adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq 16(%rsi,%r15,1),%rax adcq $0,%rdx addq %r11,%rdi leaq 32(%rcx),%rcx adcq $0,%rdx movq %rdi,(%r14) movq %rdx,%r13 addq $32,%r15 jnz .L1st4x mulq %rbx addq %rax,%r10 movq -16(%rcx),%rax leaq 32(%r14),%r14 adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq -8(%rsi),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %r13,-24(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq -8(%rcx),%rax adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq (%rsi,%r9,1),%rax adcq $0,%rdx addq %r11,%rdi adcq $0,%rdx movq %rdi,-16(%r14) movq %rdx,%r13 leaq (%rcx,%r9,1),%rcx xorq %rdi,%rdi addq %r10,%r13 adcq $0,%rdi movq %r13,-8(%r14) jmp .Louter4x .align 32 .Louter4x: leaq 16+128(%r14),%rdx pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 movdqa -128(%r12),%xmm0 movdqa -112(%r12),%xmm1 movdqa -96(%r12),%xmm2 movdqa -80(%r12),%xmm3 pand -128(%rdx),%xmm0 pand -112(%rdx),%xmm1 por %xmm0,%xmm4 pand -96(%rdx),%xmm2 por %xmm1,%xmm5 pand -80(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa -64(%r12),%xmm0 movdqa -48(%r12),%xmm1 movdqa -32(%r12),%xmm2 movdqa -16(%r12),%xmm3 pand -64(%rdx),%xmm0 pand -48(%rdx),%xmm1 por %xmm0,%xmm4 pand -32(%rdx),%xmm2 por %xmm1,%xmm5 pand -16(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 0(%r12),%xmm0 movdqa 16(%r12),%xmm1 movdqa 32(%r12),%xmm2 movdqa 48(%r12),%xmm3 pand 0(%rdx),%xmm0 pand 16(%rdx),%xmm1 por %xmm0,%xmm4 pand 32(%rdx),%xmm2 por %xmm1,%xmm5 pand 48(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 64(%r12),%xmm0 movdqa 80(%r12),%xmm1 movdqa 96(%r12),%xmm2 movdqa 112(%r12),%xmm3 pand 64(%rdx),%xmm0 pand 80(%rdx),%xmm1 por %xmm0,%xmm4 pand 96(%rdx),%xmm2 por %xmm1,%xmm5 pand 112(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 por %xmm5,%xmm4 pshufd $0x4e,%xmm4,%xmm0 por %xmm4,%xmm0 leaq 256(%r12),%r12 .byte 102,72,15,126,195 movq (%r14,%r9,1),%r10 movq %r8,%rbp mulq %rbx addq %rax,%r10 movq (%rcx),%rax adcq $0,%rdx imulq %r10,%rbp movq %rdx,%r11 movq %rdi,(%r14) leaq (%r14,%r9,1),%r14 mulq %rbp addq %rax,%r10 movq 8(%rsi,%r9,1),%rax adcq $0,%rdx movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq 8(%rcx),%rax adcq $0,%rdx addq 8(%r14),%r11 adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq 16(%rsi,%r9,1),%rax adcq $0,%rdx addq %r11,%rdi leaq 32(%r9),%r15 leaq 32(%rcx),%rcx adcq $0,%rdx movq %rdx,%r13 jmp .Linner4x .align 32 .Linner4x: mulq %rbx addq %rax,%r10 movq -16(%rcx),%rax adcq $0,%rdx addq 16(%r14),%r10 leaq 32(%r14),%r14 adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq -8(%rsi,%r15,1),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %rdi,-32(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq -8(%rcx),%rax adcq $0,%rdx addq -8(%r14),%r11 adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq (%rsi,%r15,1),%rax adcq $0,%rdx addq %r11,%rdi adcq $0,%rdx movq %r13,-24(%r14) movq %rdx,%r13 mulq %rbx addq %rax,%r10 movq 0(%rcx),%rax adcq $0,%rdx addq (%r14),%r10 adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq 8(%rsi,%r15,1),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %rdi,-16(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq 8(%rcx),%rax adcq $0,%rdx addq 8(%r14),%r11 adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq 16(%rsi,%r15,1),%rax adcq $0,%rdx addq %r11,%rdi leaq 32(%rcx),%rcx adcq $0,%rdx movq %r13,-8(%r14) movq %rdx,%r13 addq $32,%r15 jnz .Linner4x mulq %rbx addq %rax,%r10 movq -16(%rcx),%rax adcq $0,%rdx addq 16(%r14),%r10 leaq 32(%r14),%r14 adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq -8(%rsi),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %rdi,-32(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq %rbp,%rax movq -8(%rcx),%rbp adcq $0,%rdx addq -8(%r14),%r11 adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq (%rsi,%r9,1),%rax adcq $0,%rdx addq %r11,%rdi adcq $0,%rdx movq %r13,-24(%r14) movq %rdx,%r13 movq %rdi,-16(%r14) leaq (%rcx,%r9,1),%rcx xorq %rdi,%rdi addq %r10,%r13 adcq $0,%rdi addq (%r14),%r13 adcq $0,%rdi movq %r13,-8(%r14) cmpq 16+8(%rsp),%r12 jb .Louter4x xorq %rax,%rax subq %r13,%rbp adcq %r15,%r15 orq %r15,%rdi subq %rdi,%rax leaq (%r14,%r9,1),%rbx movq (%rcx),%r12 leaq (%rcx),%rbp movq %r9,%rcx sarq $3+2,%rcx movq 56+8(%rsp),%rdi decq %r12 xorq %r10,%r10 movq 8(%rbp),%r13 movq 16(%rbp),%r14 movq 24(%rbp),%r15 jmp .Lsqr4x_sub_entry .cfi_endproc .size mul4x_internal,.-mul4x_internal .globl bn_power5 .hidden bn_power5 .type bn_power5,@function .align 32 bn_power5: .cfi_startproc _CET_ENDBR movq %rsp,%rax .cfi_def_cfa_register %rax leaq OPENSSL_ia32cap_P(%rip),%r11 movl 8(%r11),%r11d andl $0x80108,%r11d cmpl $0x80108,%r11d je .Lpowerx5_enter pushq %rbx .cfi_offset %rbx,-16 pushq %rbp .cfi_offset %rbp,-24 pushq %r12 .cfi_offset %r12,-32 pushq %r13 .cfi_offset %r13,-40 pushq %r14 .cfi_offset %r14,-48 pushq %r15 .cfi_offset %r15,-56 .Lpower5_prologue: shll $3,%r9d leal (%r9,%r9,2),%r10d negq %r9 movq (%r8),%r8 leaq -320(%rsp,%r9,2),%r11 movq %rsp,%rbp subq %rdi,%r11 andq $4095,%r11 cmpq %r11,%r10 jb .Lpwr_sp_alt subq %r11,%rbp leaq -320(%rbp,%r9,2),%rbp jmp .Lpwr_sp_done .align 32 .Lpwr_sp_alt: leaq 4096-320(,%r9,2),%r10 leaq -320(%rbp,%r9,2),%rbp subq %r10,%r11 movq $0,%r10 cmovcq %r10,%r11 subq %r11,%rbp .Lpwr_sp_done: andq $-64,%rbp movq %rsp,%r11 subq %rbp,%r11 andq $-4096,%r11 leaq (%r11,%rbp,1),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lpwr_page_walk jmp .Lpwr_page_walk_done .Lpwr_page_walk: leaq -4096(%rsp),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lpwr_page_walk .Lpwr_page_walk_done: movq %r9,%r10 negq %r9 movq %r8,32(%rsp) movq %rax,40(%rsp) .cfi_escape 0x0f,0x05,0x77,0x28,0x06,0x23,0x08 .Lpower5_body: .byte 102,72,15,110,207 .byte 102,72,15,110,209 .byte 102,73,15,110,218 .byte 102,72,15,110,226 call __bn_sqr8x_internal call __bn_post4x_internal call __bn_sqr8x_internal call __bn_post4x_internal call __bn_sqr8x_internal call __bn_post4x_internal call __bn_sqr8x_internal call __bn_post4x_internal call __bn_sqr8x_internal call __bn_post4x_internal .byte 102,72,15,126,209 .byte 102,72,15,126,226 movq %rsi,%rdi movq 40(%rsp),%rax leaq 32(%rsp),%r8 call mul4x_internal movq 40(%rsp),%rsi .cfi_def_cfa %rsi,8 movq $1,%rax movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbp .cfi_restore %rbp movq -8(%rsi),%rbx .cfi_restore %rbx leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpower5_epilogue: ret .cfi_endproc .size bn_power5,.-bn_power5 .globl bn_sqr8x_internal .hidden bn_sqr8x_internal .hidden bn_sqr8x_internal .type bn_sqr8x_internal,@function .align 32 bn_sqr8x_internal: __bn_sqr8x_internal: .cfi_startproc _CET_ENDBR leaq 32(%r10),%rbp leaq (%rsi,%r9,1),%rsi movq %r9,%rcx movq -32(%rsi,%rbp,1),%r14 leaq 48+8(%rsp,%r9,2),%rdi movq -24(%rsi,%rbp,1),%rax leaq -32(%rdi,%rbp,1),%rdi movq -16(%rsi,%rbp,1),%rbx movq %rax,%r15 mulq %r14 movq %rax,%r10 movq %rbx,%rax movq %rdx,%r11 movq %r10,-24(%rdi,%rbp,1) mulq %r14 addq %rax,%r11 movq %rbx,%rax adcq $0,%rdx movq %r11,-16(%rdi,%rbp,1) movq %rdx,%r10 movq -8(%rsi,%rbp,1),%rbx mulq %r15 movq %rax,%r12 movq %rbx,%rax movq %rdx,%r13 leaq (%rbp),%rcx mulq %r14 addq %rax,%r10 movq %rbx,%rax movq %rdx,%r11 adcq $0,%r11 addq %r12,%r10 adcq $0,%r11 movq %r10,-8(%rdi,%rcx,1) jmp .Lsqr4x_1st .align 32 .Lsqr4x_1st: movq (%rsi,%rcx,1),%rbx mulq %r15 addq %rax,%r13 movq %rbx,%rax movq %rdx,%r12 adcq $0,%r12 mulq %r14 addq %rax,%r11 movq %rbx,%rax movq 8(%rsi,%rcx,1),%rbx movq %rdx,%r10 adcq $0,%r10 addq %r13,%r11 adcq $0,%r10 mulq %r15 addq %rax,%r12 movq %rbx,%rax movq %r11,(%rdi,%rcx,1) movq %rdx,%r13 adcq $0,%r13 mulq %r14 addq %rax,%r10 movq %rbx,%rax movq 16(%rsi,%rcx,1),%rbx movq %rdx,%r11 adcq $0,%r11 addq %r12,%r10 adcq $0,%r11 mulq %r15 addq %rax,%r13 movq %rbx,%rax movq %r10,8(%rdi,%rcx,1) movq %rdx,%r12 adcq $0,%r12 mulq %r14 addq %rax,%r11 movq %rbx,%rax movq 24(%rsi,%rcx,1),%rbx movq %rdx,%r10 adcq $0,%r10 addq %r13,%r11 adcq $0,%r10 mulq %r15 addq %rax,%r12 movq %rbx,%rax movq %r11,16(%rdi,%rcx,1) movq %rdx,%r13 adcq $0,%r13 leaq 32(%rcx),%rcx mulq %r14 addq %rax,%r10 movq %rbx,%rax movq %rdx,%r11 adcq $0,%r11 addq %r12,%r10 adcq $0,%r11 movq %r10,-8(%rdi,%rcx,1) cmpq $0,%rcx jne .Lsqr4x_1st mulq %r15 addq %rax,%r13 leaq 16(%rbp),%rbp adcq $0,%rdx addq %r11,%r13 adcq $0,%rdx movq %r13,(%rdi) movq %rdx,%r12 movq %rdx,8(%rdi) jmp .Lsqr4x_outer .align 32 .Lsqr4x_outer: movq -32(%rsi,%rbp,1),%r14 leaq 48+8(%rsp,%r9,2),%rdi movq -24(%rsi,%rbp,1),%rax leaq -32(%rdi,%rbp,1),%rdi movq -16(%rsi,%rbp,1),%rbx movq %rax,%r15 mulq %r14 movq -24(%rdi,%rbp,1),%r10 addq %rax,%r10 movq %rbx,%rax adcq $0,%rdx movq %r10,-24(%rdi,%rbp,1) movq %rdx,%r11 mulq %r14 addq %rax,%r11 movq %rbx,%rax adcq $0,%rdx addq -16(%rdi,%rbp,1),%r11 movq %rdx,%r10 adcq $0,%r10 movq %r11,-16(%rdi,%rbp,1) xorq %r12,%r12 movq -8(%rsi,%rbp,1),%rbx mulq %r15 addq %rax,%r12 movq %rbx,%rax adcq $0,%rdx addq -8(%rdi,%rbp,1),%r12 movq %rdx,%r13 adcq $0,%r13 mulq %r14 addq %rax,%r10 movq %rbx,%rax adcq $0,%rdx addq %r12,%r10 movq %rdx,%r11 adcq $0,%r11 movq %r10,-8(%rdi,%rbp,1) leaq (%rbp),%rcx jmp .Lsqr4x_inner .align 32 .Lsqr4x_inner: movq (%rsi,%rcx,1),%rbx mulq %r15 addq %rax,%r13 movq %rbx,%rax movq %rdx,%r12 adcq $0,%r12 addq (%rdi,%rcx,1),%r13 adcq $0,%r12 .byte 0x67 mulq %r14 addq %rax,%r11 movq %rbx,%rax movq 8(%rsi,%rcx,1),%rbx movq %rdx,%r10 adcq $0,%r10 addq %r13,%r11 adcq $0,%r10 mulq %r15 addq %rax,%r12 movq %r11,(%rdi,%rcx,1) movq %rbx,%rax movq %rdx,%r13 adcq $0,%r13 addq 8(%rdi,%rcx,1),%r12 leaq 16(%rcx),%rcx adcq $0,%r13 mulq %r14 addq %rax,%r10 movq %rbx,%rax adcq $0,%rdx addq %r12,%r10 movq %rdx,%r11 adcq $0,%r11 movq %r10,-8(%rdi,%rcx,1) cmpq $0,%rcx jne .Lsqr4x_inner .byte 0x67 mulq %r15 addq %rax,%r13 adcq $0,%rdx addq %r11,%r13 adcq $0,%rdx movq %r13,(%rdi) movq %rdx,%r12 movq %rdx,8(%rdi) addq $16,%rbp jnz .Lsqr4x_outer movq -32(%rsi),%r14 leaq 48+8(%rsp,%r9,2),%rdi movq -24(%rsi),%rax leaq -32(%rdi,%rbp,1),%rdi movq -16(%rsi),%rbx movq %rax,%r15 mulq %r14 addq %rax,%r10 movq %rbx,%rax movq %rdx,%r11 adcq $0,%r11 mulq %r14 addq %rax,%r11 movq %rbx,%rax movq %r10,-24(%rdi) movq %rdx,%r10 adcq $0,%r10 addq %r13,%r11 movq -8(%rsi),%rbx adcq $0,%r10 mulq %r15 addq %rax,%r12 movq %rbx,%rax movq %r11,-16(%rdi) movq %rdx,%r13 adcq $0,%r13 mulq %r14 addq %rax,%r10 movq %rbx,%rax movq %rdx,%r11 adcq $0,%r11 addq %r12,%r10 adcq $0,%r11 movq %r10,-8(%rdi) mulq %r15 addq %rax,%r13 movq -16(%rsi),%rax adcq $0,%rdx addq %r11,%r13 adcq $0,%rdx movq %r13,(%rdi) movq %rdx,%r12 movq %rdx,8(%rdi) mulq %rbx addq $16,%rbp xorq %r14,%r14 subq %r9,%rbp xorq %r15,%r15 addq %r12,%rax adcq $0,%rdx movq %rax,8(%rdi) movq %rdx,16(%rdi) movq %r15,24(%rdi) movq -16(%rsi,%rbp,1),%rax leaq 48+8(%rsp),%rdi xorq %r10,%r10 movq 8(%rdi),%r11 leaq (%r14,%r10,2),%r12 shrq $63,%r10 leaq (%rcx,%r11,2),%r13 shrq $63,%r11 orq %r10,%r13 movq 16(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq 24(%rdi),%r11 adcq %rax,%r12 movq -8(%rsi,%rbp,1),%rax movq %r12,(%rdi) adcq %rdx,%r13 leaq (%r14,%r10,2),%rbx movq %r13,8(%rdi) sbbq %r15,%r15 shrq $63,%r10 leaq (%rcx,%r11,2),%r8 shrq $63,%r11 orq %r10,%r8 movq 32(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq 40(%rdi),%r11 adcq %rax,%rbx movq 0(%rsi,%rbp,1),%rax movq %rbx,16(%rdi) adcq %rdx,%r8 leaq 16(%rbp),%rbp movq %r8,24(%rdi) sbbq %r15,%r15 leaq 64(%rdi),%rdi jmp .Lsqr4x_shift_n_add .align 32 .Lsqr4x_shift_n_add: leaq (%r14,%r10,2),%r12 shrq $63,%r10 leaq (%rcx,%r11,2),%r13 shrq $63,%r11 orq %r10,%r13 movq -16(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq -8(%rdi),%r11 adcq %rax,%r12 movq -8(%rsi,%rbp,1),%rax movq %r12,-32(%rdi) adcq %rdx,%r13 leaq (%r14,%r10,2),%rbx movq %r13,-24(%rdi) sbbq %r15,%r15 shrq $63,%r10 leaq (%rcx,%r11,2),%r8 shrq $63,%r11 orq %r10,%r8 movq 0(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq 8(%rdi),%r11 adcq %rax,%rbx movq 0(%rsi,%rbp,1),%rax movq %rbx,-16(%rdi) adcq %rdx,%r8 leaq (%r14,%r10,2),%r12 movq %r8,-8(%rdi) sbbq %r15,%r15 shrq $63,%r10 leaq (%rcx,%r11,2),%r13 shrq $63,%r11 orq %r10,%r13 movq 16(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq 24(%rdi),%r11 adcq %rax,%r12 movq 8(%rsi,%rbp,1),%rax movq %r12,0(%rdi) adcq %rdx,%r13 leaq (%r14,%r10,2),%rbx movq %r13,8(%rdi) sbbq %r15,%r15 shrq $63,%r10 leaq (%rcx,%r11,2),%r8 shrq $63,%r11 orq %r10,%r8 movq 32(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq 40(%rdi),%r11 adcq %rax,%rbx movq 16(%rsi,%rbp,1),%rax movq %rbx,16(%rdi) adcq %rdx,%r8 movq %r8,24(%rdi) sbbq %r15,%r15 leaq 64(%rdi),%rdi addq $32,%rbp jnz .Lsqr4x_shift_n_add leaq (%r14,%r10,2),%r12 .byte 0x67 shrq $63,%r10 leaq (%rcx,%r11,2),%r13 shrq $63,%r11 orq %r10,%r13 movq -16(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq -8(%rdi),%r11 adcq %rax,%r12 movq -8(%rsi),%rax movq %r12,-32(%rdi) adcq %rdx,%r13 leaq (%r14,%r10,2),%rbx movq %r13,-24(%rdi) sbbq %r15,%r15 shrq $63,%r10 leaq (%rcx,%r11,2),%r8 shrq $63,%r11 orq %r10,%r8 mulq %rax negq %r15 adcq %rax,%rbx adcq %rdx,%r8 movq %rbx,-16(%rdi) movq %r8,-8(%rdi) .byte 102,72,15,126,213 __bn_sqr8x_reduction: xorq %rax,%rax leaq (%r9,%rbp,1),%rcx leaq 48+8(%rsp,%r9,2),%rdx movq %rcx,0+8(%rsp) leaq 48+8(%rsp,%r9,1),%rdi movq %rdx,8+8(%rsp) negq %r9 jmp .L8x_reduction_loop .align 32 .L8x_reduction_loop: leaq (%rdi,%r9,1),%rdi .byte 0x66 movq 0(%rdi),%rbx movq 8(%rdi),%r9 movq 16(%rdi),%r10 movq 24(%rdi),%r11 movq 32(%rdi),%r12 movq 40(%rdi),%r13 movq 48(%rdi),%r14 movq 56(%rdi),%r15 movq %rax,(%rdx) leaq 64(%rdi),%rdi .byte 0x67 movq %rbx,%r8 imulq 32+8(%rsp),%rbx movq 0(%rbp),%rax movl $8,%ecx jmp .L8x_reduce .align 32 .L8x_reduce: mulq %rbx movq 8(%rbp),%rax negq %r8 movq %rdx,%r8 adcq $0,%r8 mulq %rbx addq %rax,%r9 movq 16(%rbp),%rax adcq $0,%rdx addq %r9,%r8 movq %rbx,48-8+8(%rsp,%rcx,8) movq %rdx,%r9 adcq $0,%r9 mulq %rbx addq %rax,%r10 movq 24(%rbp),%rax adcq $0,%rdx addq %r10,%r9 movq 32+8(%rsp),%rsi movq %rdx,%r10 adcq $0,%r10 mulq %rbx addq %rax,%r11 movq 32(%rbp),%rax adcq $0,%rdx imulq %r8,%rsi addq %r11,%r10 movq %rdx,%r11 adcq $0,%r11 mulq %rbx addq %rax,%r12 movq 40(%rbp),%rax adcq $0,%rdx addq %r12,%r11 movq %rdx,%r12 adcq $0,%r12 mulq %rbx addq %rax,%r13 movq 48(%rbp),%rax adcq $0,%rdx addq %r13,%r12 movq %rdx,%r13 adcq $0,%r13 mulq %rbx addq %rax,%r14 movq 56(%rbp),%rax adcq $0,%rdx addq %r14,%r13 movq %rdx,%r14 adcq $0,%r14 mulq %rbx movq %rsi,%rbx addq %rax,%r15 movq 0(%rbp),%rax adcq $0,%rdx addq %r15,%r14 movq %rdx,%r15 adcq $0,%r15 decl %ecx jnz .L8x_reduce leaq 64(%rbp),%rbp xorq %rax,%rax movq 8+8(%rsp),%rdx cmpq 0+8(%rsp),%rbp jae .L8x_no_tail .byte 0x66 addq 0(%rdi),%r8 adcq 8(%rdi),%r9 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 sbbq %rsi,%rsi movq 48+56+8(%rsp),%rbx movl $8,%ecx movq 0(%rbp),%rax jmp .L8x_tail .align 32 .L8x_tail: mulq %rbx addq %rax,%r8 movq 8(%rbp),%rax movq %r8,(%rdi) movq %rdx,%r8 adcq $0,%r8 mulq %rbx addq %rax,%r9 movq 16(%rbp),%rax adcq $0,%rdx addq %r9,%r8 leaq 8(%rdi),%rdi movq %rdx,%r9 adcq $0,%r9 mulq %rbx addq %rax,%r10 movq 24(%rbp),%rax adcq $0,%rdx addq %r10,%r9 movq %rdx,%r10 adcq $0,%r10 mulq %rbx addq %rax,%r11 movq 32(%rbp),%rax adcq $0,%rdx addq %r11,%r10 movq %rdx,%r11 adcq $0,%r11 mulq %rbx addq %rax,%r12 movq 40(%rbp),%rax adcq $0,%rdx addq %r12,%r11 movq %rdx,%r12 adcq $0,%r12 mulq %rbx addq %rax,%r13 movq 48(%rbp),%rax adcq $0,%rdx addq %r13,%r12 movq %rdx,%r13 adcq $0,%r13 mulq %rbx addq %rax,%r14 movq 56(%rbp),%rax adcq $0,%rdx addq %r14,%r13 movq %rdx,%r14 adcq $0,%r14 mulq %rbx movq 48-16+8(%rsp,%rcx,8),%rbx addq %rax,%r15 adcq $0,%rdx addq %r15,%r14 movq 0(%rbp),%rax movq %rdx,%r15 adcq $0,%r15 decl %ecx jnz .L8x_tail leaq 64(%rbp),%rbp movq 8+8(%rsp),%rdx cmpq 0+8(%rsp),%rbp jae .L8x_tail_done movq 48+56+8(%rsp),%rbx negq %rsi movq 0(%rbp),%rax adcq 0(%rdi),%r8 adcq 8(%rdi),%r9 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 sbbq %rsi,%rsi movl $8,%ecx jmp .L8x_tail .align 32 .L8x_tail_done: xorq %rax,%rax addq (%rdx),%r8 adcq $0,%r9 adcq $0,%r10 adcq $0,%r11 adcq $0,%r12 adcq $0,%r13 adcq $0,%r14 adcq $0,%r15 adcq $0,%rax negq %rsi .L8x_no_tail: adcq 0(%rdi),%r8 adcq 8(%rdi),%r9 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 adcq $0,%rax movq -8(%rbp),%rcx xorq %rsi,%rsi .byte 102,72,15,126,213 movq %r8,0(%rdi) movq %r9,8(%rdi) .byte 102,73,15,126,217 movq %r10,16(%rdi) movq %r11,24(%rdi) movq %r12,32(%rdi) movq %r13,40(%rdi) movq %r14,48(%rdi) movq %r15,56(%rdi) leaq 64(%rdi),%rdi cmpq %rdx,%rdi jb .L8x_reduction_loop ret .cfi_endproc .size bn_sqr8x_internal,.-bn_sqr8x_internal .type __bn_post4x_internal,@function .align 32 __bn_post4x_internal: .cfi_startproc movq 0(%rbp),%r12 leaq (%rdi,%r9,1),%rbx movq %r9,%rcx .byte 102,72,15,126,207 negq %rax .byte 102,72,15,126,206 sarq $3+2,%rcx decq %r12 xorq %r10,%r10 movq 8(%rbp),%r13 movq 16(%rbp),%r14 movq 24(%rbp),%r15 jmp .Lsqr4x_sub_entry .align 16 .Lsqr4x_sub: movq 0(%rbp),%r12 movq 8(%rbp),%r13 movq 16(%rbp),%r14 movq 24(%rbp),%r15 .Lsqr4x_sub_entry: leaq 32(%rbp),%rbp notq %r12 notq %r13 notq %r14 notq %r15 andq %rax,%r12 andq %rax,%r13 andq %rax,%r14 andq %rax,%r15 negq %r10 adcq 0(%rbx),%r12 adcq 8(%rbx),%r13 adcq 16(%rbx),%r14 adcq 24(%rbx),%r15 movq %r12,0(%rdi) leaq 32(%rbx),%rbx movq %r13,8(%rdi) sbbq %r10,%r10 movq %r14,16(%rdi) movq %r15,24(%rdi) leaq 32(%rdi),%rdi incq %rcx jnz .Lsqr4x_sub movq %r9,%r10 negq %r9 ret .cfi_endproc .size __bn_post4x_internal,.-__bn_post4x_internal .type bn_mulx4x_mont_gather5,@function .align 32 bn_mulx4x_mont_gather5: .cfi_startproc movq %rsp,%rax .cfi_def_cfa_register %rax .Lmulx4x_enter: pushq %rbx .cfi_offset %rbx,-16 pushq %rbp .cfi_offset %rbp,-24 pushq %r12 .cfi_offset %r12,-32 pushq %r13 .cfi_offset %r13,-40 pushq %r14 .cfi_offset %r14,-48 pushq %r15 .cfi_offset %r15,-56 .Lmulx4x_prologue: shll $3,%r9d leaq (%r9,%r9,2),%r10 negq %r9 movq (%r8),%r8 leaq -320(%rsp,%r9,2),%r11 movq %rsp,%rbp subq %rdi,%r11 andq $4095,%r11 cmpq %r11,%r10 jb .Lmulx4xsp_alt subq %r11,%rbp leaq -320(%rbp,%r9,2),%rbp jmp .Lmulx4xsp_done .Lmulx4xsp_alt: leaq 4096-320(,%r9,2),%r10 leaq -320(%rbp,%r9,2),%rbp subq %r10,%r11 movq $0,%r10 cmovcq %r10,%r11 subq %r11,%rbp .Lmulx4xsp_done: andq $-64,%rbp movq %rsp,%r11 subq %rbp,%r11 andq $-4096,%r11 leaq (%r11,%rbp,1),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lmulx4x_page_walk jmp .Lmulx4x_page_walk_done .Lmulx4x_page_walk: leaq -4096(%rsp),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lmulx4x_page_walk .Lmulx4x_page_walk_done: movq %r8,32(%rsp) movq %rax,40(%rsp) .cfi_escape 0x0f,0x05,0x77,0x28,0x06,0x23,0x08 .Lmulx4x_body: call mulx4x_internal movq 40(%rsp),%rsi .cfi_def_cfa %rsi,8 movq $1,%rax movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbp .cfi_restore %rbp movq -8(%rsi),%rbx .cfi_restore %rbx leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lmulx4x_epilogue: ret .cfi_endproc .size bn_mulx4x_mont_gather5,.-bn_mulx4x_mont_gather5 .type mulx4x_internal,@function .align 32 mulx4x_internal: .cfi_startproc movq %r9,8(%rsp) movq %r9,%r10 negq %r9 shlq $5,%r9 negq %r10 leaq 128(%rdx,%r9,1),%r13 shrq $5+5,%r9 movd 8(%rax),%xmm5 subq $1,%r9 leaq .Linc(%rip),%rax movq %r13,16+8(%rsp) movq %r9,24+8(%rsp) movq %rdi,56+8(%rsp) movdqa 0(%rax),%xmm0 movdqa 16(%rax),%xmm1 leaq 88-112(%rsp,%r10,1),%r10 leaq 128(%rdx),%rdi pshufd $0,%xmm5,%xmm5 movdqa %xmm1,%xmm4 .byte 0x67 movdqa %xmm1,%xmm2 .byte 0x67 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,112(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,128(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,144(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,160(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,176(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,192(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,208(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,224(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,240(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,256(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,272(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,288(%r10) movdqa %xmm4,%xmm3 .byte 0x67 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,304(%r10) paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,320(%r10) pcmpeqd %xmm5,%xmm3 movdqa %xmm2,336(%r10) pand 64(%rdi),%xmm0 pand 80(%rdi),%xmm1 pand 96(%rdi),%xmm2 movdqa %xmm3,352(%r10) pand 112(%rdi),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -128(%rdi),%xmm4 movdqa -112(%rdi),%xmm5 movdqa -96(%rdi),%xmm2 pand 112(%r10),%xmm4 movdqa -80(%rdi),%xmm3 pand 128(%r10),%xmm5 por %xmm4,%xmm0 pand 144(%r10),%xmm2 por %xmm5,%xmm1 pand 160(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -64(%rdi),%xmm4 movdqa -48(%rdi),%xmm5 movdqa -32(%rdi),%xmm2 pand 176(%r10),%xmm4 movdqa -16(%rdi),%xmm3 pand 192(%r10),%xmm5 por %xmm4,%xmm0 pand 208(%r10),%xmm2 por %xmm5,%xmm1 pand 224(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa 0(%rdi),%xmm4 movdqa 16(%rdi),%xmm5 movdqa 32(%rdi),%xmm2 pand 240(%r10),%xmm4 movdqa 48(%rdi),%xmm3 pand 256(%r10),%xmm5 por %xmm4,%xmm0 pand 272(%r10),%xmm2 por %xmm5,%xmm1 pand 288(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 pxor %xmm1,%xmm0 pshufd $0x4e,%xmm0,%xmm1 por %xmm1,%xmm0 leaq 256(%rdi),%rdi .byte 102,72,15,126,194 leaq 64+32+8(%rsp),%rbx movq %rdx,%r9 mulxq 0(%rsi),%r8,%rax mulxq 8(%rsi),%r11,%r12 addq %rax,%r11 mulxq 16(%rsi),%rax,%r13 adcq %rax,%r12 adcq $0,%r13 mulxq 24(%rsi),%rax,%r14 movq %r8,%r15 imulq 32+8(%rsp),%r8 xorq %rbp,%rbp movq %r8,%rdx movq %rdi,8+8(%rsp) leaq 32(%rsi),%rsi adcxq %rax,%r13 adcxq %rbp,%r14 mulxq 0(%rcx),%rax,%r10 adcxq %rax,%r15 adoxq %r11,%r10 mulxq 8(%rcx),%rax,%r11 adcxq %rax,%r10 adoxq %r12,%r11 mulxq 16(%rcx),%rax,%r12 movq 24+8(%rsp),%rdi movq %r10,-32(%rbx) adcxq %rax,%r11 adoxq %r13,%r12 mulxq 24(%rcx),%rax,%r15 movq %r9,%rdx movq %r11,-24(%rbx) adcxq %rax,%r12 adoxq %rbp,%r15 leaq 32(%rcx),%rcx movq %r12,-16(%rbx) jmp .Lmulx4x_1st .align 32 .Lmulx4x_1st: adcxq %rbp,%r15 mulxq 0(%rsi),%r10,%rax adcxq %r14,%r10 mulxq 8(%rsi),%r11,%r14 adcxq %rax,%r11 mulxq 16(%rsi),%r12,%rax adcxq %r14,%r12 mulxq 24(%rsi),%r13,%r14 .byte 0x67,0x67 movq %r8,%rdx adcxq %rax,%r13 adcxq %rbp,%r14 leaq 32(%rsi),%rsi leaq 32(%rbx),%rbx adoxq %r15,%r10 mulxq 0(%rcx),%rax,%r15 adcxq %rax,%r10 adoxq %r15,%r11 mulxq 8(%rcx),%rax,%r15 adcxq %rax,%r11 adoxq %r15,%r12 mulxq 16(%rcx),%rax,%r15 movq %r10,-40(%rbx) adcxq %rax,%r12 movq %r11,-32(%rbx) adoxq %r15,%r13 mulxq 24(%rcx),%rax,%r15 movq %r9,%rdx movq %r12,-24(%rbx) adcxq %rax,%r13 adoxq %rbp,%r15 leaq 32(%rcx),%rcx movq %r13,-16(%rbx) decq %rdi jnz .Lmulx4x_1st movq 8(%rsp),%rax adcq %rbp,%r15 leaq (%rsi,%rax,1),%rsi addq %r15,%r14 movq 8+8(%rsp),%rdi adcq %rbp,%rbp movq %r14,-8(%rbx) jmp .Lmulx4x_outer .align 32 .Lmulx4x_outer: leaq 16-256(%rbx),%r10 pxor %xmm4,%xmm4 .byte 0x67,0x67 pxor %xmm5,%xmm5 movdqa -128(%rdi),%xmm0 movdqa -112(%rdi),%xmm1 movdqa -96(%rdi),%xmm2 pand 256(%r10),%xmm0 movdqa -80(%rdi),%xmm3 pand 272(%r10),%xmm1 por %xmm0,%xmm4 pand 288(%r10),%xmm2 por %xmm1,%xmm5 pand 304(%r10),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa -64(%rdi),%xmm0 movdqa -48(%rdi),%xmm1 movdqa -32(%rdi),%xmm2 pand 320(%r10),%xmm0 movdqa -16(%rdi),%xmm3 pand 336(%r10),%xmm1 por %xmm0,%xmm4 pand 352(%r10),%xmm2 por %xmm1,%xmm5 pand 368(%r10),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 0(%rdi),%xmm0 movdqa 16(%rdi),%xmm1 movdqa 32(%rdi),%xmm2 pand 384(%r10),%xmm0 movdqa 48(%rdi),%xmm3 pand 400(%r10),%xmm1 por %xmm0,%xmm4 pand 416(%r10),%xmm2 por %xmm1,%xmm5 pand 432(%r10),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 64(%rdi),%xmm0 movdqa 80(%rdi),%xmm1 movdqa 96(%rdi),%xmm2 pand 448(%r10),%xmm0 movdqa 112(%rdi),%xmm3 pand 464(%r10),%xmm1 por %xmm0,%xmm4 pand 480(%r10),%xmm2 por %xmm1,%xmm5 pand 496(%r10),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 por %xmm5,%xmm4 pshufd $0x4e,%xmm4,%xmm0 por %xmm4,%xmm0 leaq 256(%rdi),%rdi .byte 102,72,15,126,194 movq %rbp,(%rbx) leaq 32(%rbx,%rax,1),%rbx mulxq 0(%rsi),%r8,%r11 xorq %rbp,%rbp movq %rdx,%r9 mulxq 8(%rsi),%r14,%r12 adoxq -32(%rbx),%r8 adcxq %r14,%r11 mulxq 16(%rsi),%r15,%r13 adoxq -24(%rbx),%r11 adcxq %r15,%r12 mulxq 24(%rsi),%rdx,%r14 adoxq -16(%rbx),%r12 adcxq %rdx,%r13 leaq (%rcx,%rax,1),%rcx leaq 32(%rsi),%rsi adoxq -8(%rbx),%r13 adcxq %rbp,%r14 adoxq %rbp,%r14 movq %r8,%r15 imulq 32+8(%rsp),%r8 movq %r8,%rdx xorq %rbp,%rbp movq %rdi,8+8(%rsp) mulxq 0(%rcx),%rax,%r10 adcxq %rax,%r15 adoxq %r11,%r10 mulxq 8(%rcx),%rax,%r11 adcxq %rax,%r10 adoxq %r12,%r11 mulxq 16(%rcx),%rax,%r12 adcxq %rax,%r11 adoxq %r13,%r12 mulxq 24(%rcx),%rax,%r15 movq %r9,%rdx movq 24+8(%rsp),%rdi movq %r10,-32(%rbx) adcxq %rax,%r12 movq %r11,-24(%rbx) adoxq %rbp,%r15 movq %r12,-16(%rbx) leaq 32(%rcx),%rcx jmp .Lmulx4x_inner .align 32 .Lmulx4x_inner: mulxq 0(%rsi),%r10,%rax adcxq %rbp,%r15 adoxq %r14,%r10 mulxq 8(%rsi),%r11,%r14 adcxq 0(%rbx),%r10 adoxq %rax,%r11 mulxq 16(%rsi),%r12,%rax adcxq 8(%rbx),%r11 adoxq %r14,%r12 mulxq 24(%rsi),%r13,%r14 movq %r8,%rdx adcxq 16(%rbx),%r12 adoxq %rax,%r13 adcxq 24(%rbx),%r13 adoxq %rbp,%r14 leaq 32(%rsi),%rsi leaq 32(%rbx),%rbx adcxq %rbp,%r14 adoxq %r15,%r10 mulxq 0(%rcx),%rax,%r15 adcxq %rax,%r10 adoxq %r15,%r11 mulxq 8(%rcx),%rax,%r15 adcxq %rax,%r11 adoxq %r15,%r12 mulxq 16(%rcx),%rax,%r15 movq %r10,-40(%rbx) adcxq %rax,%r12 adoxq %r15,%r13 movq %r11,-32(%rbx) mulxq 24(%rcx),%rax,%r15 movq %r9,%rdx leaq 32(%rcx),%rcx movq %r12,-24(%rbx) adcxq %rax,%r13 adoxq %rbp,%r15 movq %r13,-16(%rbx) decq %rdi jnz .Lmulx4x_inner movq 0+8(%rsp),%rax adcq %rbp,%r15 subq 0(%rbx),%rdi movq 8+8(%rsp),%rdi movq 16+8(%rsp),%r10 adcq %r15,%r14 leaq (%rsi,%rax,1),%rsi adcq %rbp,%rbp movq %r14,-8(%rbx) cmpq %r10,%rdi jb .Lmulx4x_outer movq -8(%rcx),%r10 movq %rbp,%r8 movq (%rcx,%rax,1),%r12 leaq (%rcx,%rax,1),%rbp movq %rax,%rcx leaq (%rbx,%rax,1),%rdi xorl %eax,%eax xorq %r15,%r15 subq %r14,%r10 adcq %r15,%r15 orq %r15,%r8 sarq $3+2,%rcx subq %r8,%rax movq 56+8(%rsp),%rdx decq %r12 movq 8(%rbp),%r13 xorq %r8,%r8 movq 16(%rbp),%r14 movq 24(%rbp),%r15 jmp .Lsqrx4x_sub_entry .cfi_endproc .size mulx4x_internal,.-mulx4x_internal .type bn_powerx5,@function .align 32 bn_powerx5: .cfi_startproc movq %rsp,%rax .cfi_def_cfa_register %rax .Lpowerx5_enter: pushq %rbx .cfi_offset %rbx,-16 pushq %rbp .cfi_offset %rbp,-24 pushq %r12 .cfi_offset %r12,-32 pushq %r13 .cfi_offset %r13,-40 pushq %r14 .cfi_offset %r14,-48 pushq %r15 .cfi_offset %r15,-56 .Lpowerx5_prologue: shll $3,%r9d leaq (%r9,%r9,2),%r10 negq %r9 movq (%r8),%r8 leaq -320(%rsp,%r9,2),%r11 movq %rsp,%rbp subq %rdi,%r11 andq $4095,%r11 cmpq %r11,%r10 jb .Lpwrx_sp_alt subq %r11,%rbp leaq -320(%rbp,%r9,2),%rbp jmp .Lpwrx_sp_done .align 32 .Lpwrx_sp_alt: leaq 4096-320(,%r9,2),%r10 leaq -320(%rbp,%r9,2),%rbp subq %r10,%r11 movq $0,%r10 cmovcq %r10,%r11 subq %r11,%rbp .Lpwrx_sp_done: andq $-64,%rbp movq %rsp,%r11 subq %rbp,%r11 andq $-4096,%r11 leaq (%r11,%rbp,1),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lpwrx_page_walk jmp .Lpwrx_page_walk_done .Lpwrx_page_walk: leaq -4096(%rsp),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lpwrx_page_walk .Lpwrx_page_walk_done: movq %r9,%r10 negq %r9 pxor %xmm0,%xmm0 .byte 102,72,15,110,207 .byte 102,72,15,110,209 .byte 102,73,15,110,218 .byte 102,72,15,110,226 movq %r8,32(%rsp) movq %rax,40(%rsp) .cfi_escape 0x0f,0x05,0x77,0x28,0x06,0x23,0x08 .Lpowerx5_body: call __bn_sqrx8x_internal call __bn_postx4x_internal call __bn_sqrx8x_internal call __bn_postx4x_internal call __bn_sqrx8x_internal call __bn_postx4x_internal call __bn_sqrx8x_internal call __bn_postx4x_internal call __bn_sqrx8x_internal call __bn_postx4x_internal movq %r10,%r9 movq %rsi,%rdi .byte 102,72,15,126,209 .byte 102,72,15,126,226 movq 40(%rsp),%rax call mulx4x_internal movq 40(%rsp),%rsi .cfi_def_cfa %rsi,8 movq $1,%rax movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbp .cfi_restore %rbp movq -8(%rsi),%rbx .cfi_restore %rbx leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpowerx5_epilogue: ret .cfi_endproc .size bn_powerx5,.-bn_powerx5 .globl bn_sqrx8x_internal .hidden bn_sqrx8x_internal .hidden bn_sqrx8x_internal .type bn_sqrx8x_internal,@function .align 32 bn_sqrx8x_internal: __bn_sqrx8x_internal: .cfi_startproc _CET_ENDBR leaq 48+8(%rsp),%rdi leaq (%rsi,%r9,1),%rbp movq %r9,0+8(%rsp) movq %rbp,8+8(%rsp) jmp .Lsqr8x_zero_start .align 32 .byte 0x66,0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00 .Lsqrx8x_zero: .byte 0x3e movdqa %xmm0,0(%rdi) movdqa %xmm0,16(%rdi) movdqa %xmm0,32(%rdi) movdqa %xmm0,48(%rdi) .Lsqr8x_zero_start: movdqa %xmm0,64(%rdi) movdqa %xmm0,80(%rdi) movdqa %xmm0,96(%rdi) movdqa %xmm0,112(%rdi) leaq 128(%rdi),%rdi subq $64,%r9 jnz .Lsqrx8x_zero movq 0(%rsi),%rdx xorq %r10,%r10 xorq %r11,%r11 xorq %r12,%r12 xorq %r13,%r13 xorq %r14,%r14 xorq %r15,%r15 leaq 48+8(%rsp),%rdi xorq %rbp,%rbp jmp .Lsqrx8x_outer_loop .align 32 .Lsqrx8x_outer_loop: mulxq 8(%rsi),%r8,%rax adcxq %r9,%r8 adoxq %rax,%r10 mulxq 16(%rsi),%r9,%rax adcxq %r10,%r9 adoxq %rax,%r11 .byte 0xc4,0xe2,0xab,0xf6,0x86,0x18,0x00,0x00,0x00 adcxq %r11,%r10 adoxq %rax,%r12 .byte 0xc4,0xe2,0xa3,0xf6,0x86,0x20,0x00,0x00,0x00 adcxq %r12,%r11 adoxq %rax,%r13 mulxq 40(%rsi),%r12,%rax adcxq %r13,%r12 adoxq %rax,%r14 mulxq 48(%rsi),%r13,%rax adcxq %r14,%r13 adoxq %r15,%rax mulxq 56(%rsi),%r14,%r15 movq 8(%rsi),%rdx adcxq %rax,%r14 adoxq %rbp,%r15 adcq 64(%rdi),%r15 movq %r8,8(%rdi) movq %r9,16(%rdi) sbbq %rcx,%rcx xorq %rbp,%rbp mulxq 16(%rsi),%r8,%rbx mulxq 24(%rsi),%r9,%rax adcxq %r10,%r8 adoxq %rbx,%r9 mulxq 32(%rsi),%r10,%rbx adcxq %r11,%r9 adoxq %rax,%r10 .byte 0xc4,0xe2,0xa3,0xf6,0x86,0x28,0x00,0x00,0x00 adcxq %r12,%r10 adoxq %rbx,%r11 .byte 0xc4,0xe2,0x9b,0xf6,0x9e,0x30,0x00,0x00,0x00 adcxq %r13,%r11 adoxq %r14,%r12 .byte 0xc4,0x62,0x93,0xf6,0xb6,0x38,0x00,0x00,0x00 movq 16(%rsi),%rdx adcxq %rax,%r12 adoxq %rbx,%r13 adcxq %r15,%r13 adoxq %rbp,%r14 adcxq %rbp,%r14 movq %r8,24(%rdi) movq %r9,32(%rdi) mulxq 24(%rsi),%r8,%rbx mulxq 32(%rsi),%r9,%rax adcxq %r10,%r8 adoxq %rbx,%r9 mulxq 40(%rsi),%r10,%rbx adcxq %r11,%r9 adoxq %rax,%r10 .byte 0xc4,0xe2,0xa3,0xf6,0x86,0x30,0x00,0x00,0x00 adcxq %r12,%r10 adoxq %r13,%r11 .byte 0xc4,0x62,0x9b,0xf6,0xae,0x38,0x00,0x00,0x00 .byte 0x3e movq 24(%rsi),%rdx adcxq %rbx,%r11 adoxq %rax,%r12 adcxq %r14,%r12 movq %r8,40(%rdi) movq %r9,48(%rdi) mulxq 32(%rsi),%r8,%rax adoxq %rbp,%r13 adcxq %rbp,%r13 mulxq 40(%rsi),%r9,%rbx adcxq %r10,%r8 adoxq %rax,%r9 mulxq 48(%rsi),%r10,%rax adcxq %r11,%r9 adoxq %r12,%r10 mulxq 56(%rsi),%r11,%r12 movq 32(%rsi),%rdx movq 40(%rsi),%r14 adcxq %rbx,%r10 adoxq %rax,%r11 movq 48(%rsi),%r15 adcxq %r13,%r11 adoxq %rbp,%r12 adcxq %rbp,%r12 movq %r8,56(%rdi) movq %r9,64(%rdi) mulxq %r14,%r9,%rax movq 56(%rsi),%r8 adcxq %r10,%r9 mulxq %r15,%r10,%rbx adoxq %rax,%r10 adcxq %r11,%r10 mulxq %r8,%r11,%rax movq %r14,%rdx adoxq %rbx,%r11 adcxq %r12,%r11 adcxq %rbp,%rax mulxq %r15,%r14,%rbx mulxq %r8,%r12,%r13 movq %r15,%rdx leaq 64(%rsi),%rsi adcxq %r14,%r11 adoxq %rbx,%r12 adcxq %rax,%r12 adoxq %rbp,%r13 .byte 0x67,0x67 mulxq %r8,%r8,%r14 adcxq %r8,%r13 adcxq %rbp,%r14 cmpq 8+8(%rsp),%rsi je .Lsqrx8x_outer_break negq %rcx movq $-8,%rcx movq %rbp,%r15 movq 64(%rdi),%r8 adcxq 72(%rdi),%r9 adcxq 80(%rdi),%r10 adcxq 88(%rdi),%r11 adcq 96(%rdi),%r12 adcq 104(%rdi),%r13 adcq 112(%rdi),%r14 adcq 120(%rdi),%r15 leaq (%rsi),%rbp leaq 128(%rdi),%rdi sbbq %rax,%rax movq -64(%rsi),%rdx movq %rax,16+8(%rsp) movq %rdi,24+8(%rsp) xorl %eax,%eax jmp .Lsqrx8x_loop .align 32 .Lsqrx8x_loop: movq %r8,%rbx mulxq 0(%rbp),%rax,%r8 adcxq %rax,%rbx adoxq %r9,%r8 mulxq 8(%rbp),%rax,%r9 adcxq %rax,%r8 adoxq %r10,%r9 mulxq 16(%rbp),%rax,%r10 adcxq %rax,%r9 adoxq %r11,%r10 mulxq 24(%rbp),%rax,%r11 adcxq %rax,%r10 adoxq %r12,%r11 .byte 0xc4,0x62,0xfb,0xf6,0xa5,0x20,0x00,0x00,0x00 adcxq %rax,%r11 adoxq %r13,%r12 mulxq 40(%rbp),%rax,%r13 adcxq %rax,%r12 adoxq %r14,%r13 mulxq 48(%rbp),%rax,%r14 movq %rbx,(%rdi,%rcx,8) movl $0,%ebx adcxq %rax,%r13 adoxq %r15,%r14 .byte 0xc4,0x62,0xfb,0xf6,0xbd,0x38,0x00,0x00,0x00 movq 8(%rsi,%rcx,8),%rdx adcxq %rax,%r14 adoxq %rbx,%r15 adcxq %rbx,%r15 .byte 0x67 incq %rcx jnz .Lsqrx8x_loop leaq 64(%rbp),%rbp movq $-8,%rcx cmpq 8+8(%rsp),%rbp je .Lsqrx8x_break subq 16+8(%rsp),%rbx .byte 0x66 movq -64(%rsi),%rdx adcxq 0(%rdi),%r8 adcxq 8(%rdi),%r9 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 leaq 64(%rdi),%rdi .byte 0x67 sbbq %rax,%rax xorl %ebx,%ebx movq %rax,16+8(%rsp) jmp .Lsqrx8x_loop .align 32 .Lsqrx8x_break: xorq %rbp,%rbp subq 16+8(%rsp),%rbx adcxq %rbp,%r8 movq 24+8(%rsp),%rcx adcxq %rbp,%r9 movq 0(%rsi),%rdx adcq $0,%r10 movq %r8,0(%rdi) adcq $0,%r11 adcq $0,%r12 adcq $0,%r13 adcq $0,%r14 adcq $0,%r15 cmpq %rcx,%rdi je .Lsqrx8x_outer_loop movq %r9,8(%rdi) movq 8(%rcx),%r9 movq %r10,16(%rdi) movq 16(%rcx),%r10 movq %r11,24(%rdi) movq 24(%rcx),%r11 movq %r12,32(%rdi) movq 32(%rcx),%r12 movq %r13,40(%rdi) movq 40(%rcx),%r13 movq %r14,48(%rdi) movq 48(%rcx),%r14 movq %r15,56(%rdi) movq 56(%rcx),%r15 movq %rcx,%rdi jmp .Lsqrx8x_outer_loop .align 32 .Lsqrx8x_outer_break: movq %r9,72(%rdi) .byte 102,72,15,126,217 movq %r10,80(%rdi) movq %r11,88(%rdi) movq %r12,96(%rdi) movq %r13,104(%rdi) movq %r14,112(%rdi) leaq 48+8(%rsp),%rdi movq (%rsi,%rcx,1),%rdx movq 8(%rdi),%r11 xorq %r10,%r10 movq 0+8(%rsp),%r9 adoxq %r11,%r11 movq 16(%rdi),%r12 movq 24(%rdi),%r13 .align 32 .Lsqrx4x_shift_n_add: mulxq %rdx,%rax,%rbx adoxq %r12,%r12 adcxq %r10,%rax .byte 0x48,0x8b,0x94,0x0e,0x08,0x00,0x00,0x00 .byte 0x4c,0x8b,0x97,0x20,0x00,0x00,0x00 adoxq %r13,%r13 adcxq %r11,%rbx movq 40(%rdi),%r11 movq %rax,0(%rdi) movq %rbx,8(%rdi) mulxq %rdx,%rax,%rbx adoxq %r10,%r10 adcxq %r12,%rax movq 16(%rsi,%rcx,1),%rdx movq 48(%rdi),%r12 adoxq %r11,%r11 adcxq %r13,%rbx movq 56(%rdi),%r13 movq %rax,16(%rdi) movq %rbx,24(%rdi) mulxq %rdx,%rax,%rbx adoxq %r12,%r12 adcxq %r10,%rax movq 24(%rsi,%rcx,1),%rdx leaq 32(%rcx),%rcx movq 64(%rdi),%r10 adoxq %r13,%r13 adcxq %r11,%rbx movq 72(%rdi),%r11 movq %rax,32(%rdi) movq %rbx,40(%rdi) mulxq %rdx,%rax,%rbx adoxq %r10,%r10 adcxq %r12,%rax jrcxz .Lsqrx4x_shift_n_add_break .byte 0x48,0x8b,0x94,0x0e,0x00,0x00,0x00,0x00 adoxq %r11,%r11 adcxq %r13,%rbx movq 80(%rdi),%r12 movq 88(%rdi),%r13 movq %rax,48(%rdi) movq %rbx,56(%rdi) leaq 64(%rdi),%rdi nop jmp .Lsqrx4x_shift_n_add .align 32 .Lsqrx4x_shift_n_add_break: adcxq %r13,%rbx movq %rax,48(%rdi) movq %rbx,56(%rdi) leaq 64(%rdi),%rdi .byte 102,72,15,126,213 __bn_sqrx8x_reduction: xorl %eax,%eax movq 32+8(%rsp),%rbx movq 48+8(%rsp),%rdx leaq -64(%rbp,%r9,1),%rcx movq %rcx,0+8(%rsp) movq %rdi,8+8(%rsp) leaq 48+8(%rsp),%rdi jmp .Lsqrx8x_reduction_loop .align 32 .Lsqrx8x_reduction_loop: movq 8(%rdi),%r9 movq 16(%rdi),%r10 movq 24(%rdi),%r11 movq 32(%rdi),%r12 movq %rdx,%r8 imulq %rbx,%rdx movq 40(%rdi),%r13 movq 48(%rdi),%r14 movq 56(%rdi),%r15 movq %rax,24+8(%rsp) leaq 64(%rdi),%rdi xorq %rsi,%rsi movq $-8,%rcx jmp .Lsqrx8x_reduce .align 32 .Lsqrx8x_reduce: movq %r8,%rbx mulxq 0(%rbp),%rax,%r8 adcxq %rbx,%rax adoxq %r9,%r8 mulxq 8(%rbp),%rbx,%r9 adcxq %rbx,%r8 adoxq %r10,%r9 mulxq 16(%rbp),%rbx,%r10 adcxq %rbx,%r9 adoxq %r11,%r10 mulxq 24(%rbp),%rbx,%r11 adcxq %rbx,%r10 adoxq %r12,%r11 .byte 0xc4,0x62,0xe3,0xf6,0xa5,0x20,0x00,0x00,0x00 movq %rdx,%rax movq %r8,%rdx adcxq %rbx,%r11 adoxq %r13,%r12 mulxq 32+8(%rsp),%rbx,%rdx movq %rax,%rdx movq %rax,64+48+8(%rsp,%rcx,8) mulxq 40(%rbp),%rax,%r13 adcxq %rax,%r12 adoxq %r14,%r13 mulxq 48(%rbp),%rax,%r14 adcxq %rax,%r13 adoxq %r15,%r14 mulxq 56(%rbp),%rax,%r15 movq %rbx,%rdx adcxq %rax,%r14 adoxq %rsi,%r15 adcxq %rsi,%r15 .byte 0x67,0x67,0x67 incq %rcx jnz .Lsqrx8x_reduce movq %rsi,%rax cmpq 0+8(%rsp),%rbp jae .Lsqrx8x_no_tail movq 48+8(%rsp),%rdx addq 0(%rdi),%r8 leaq 64(%rbp),%rbp movq $-8,%rcx adcxq 8(%rdi),%r9 adcxq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 leaq 64(%rdi),%rdi sbbq %rax,%rax xorq %rsi,%rsi movq %rax,16+8(%rsp) jmp .Lsqrx8x_tail .align 32 .Lsqrx8x_tail: movq %r8,%rbx mulxq 0(%rbp),%rax,%r8 adcxq %rax,%rbx adoxq %r9,%r8 mulxq 8(%rbp),%rax,%r9 adcxq %rax,%r8 adoxq %r10,%r9 mulxq 16(%rbp),%rax,%r10 adcxq %rax,%r9 adoxq %r11,%r10 mulxq 24(%rbp),%rax,%r11 adcxq %rax,%r10 adoxq %r12,%r11 .byte 0xc4,0x62,0xfb,0xf6,0xa5,0x20,0x00,0x00,0x00 adcxq %rax,%r11 adoxq %r13,%r12 mulxq 40(%rbp),%rax,%r13 adcxq %rax,%r12 adoxq %r14,%r13 mulxq 48(%rbp),%rax,%r14 adcxq %rax,%r13 adoxq %r15,%r14 mulxq 56(%rbp),%rax,%r15 movq 72+48+8(%rsp,%rcx,8),%rdx adcxq %rax,%r14 adoxq %rsi,%r15 movq %rbx,(%rdi,%rcx,8) movq %r8,%rbx adcxq %rsi,%r15 incq %rcx jnz .Lsqrx8x_tail cmpq 0+8(%rsp),%rbp jae .Lsqrx8x_tail_done subq 16+8(%rsp),%rsi movq 48+8(%rsp),%rdx leaq 64(%rbp),%rbp adcq 0(%rdi),%r8 adcq 8(%rdi),%r9 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 leaq 64(%rdi),%rdi sbbq %rax,%rax subq $8,%rcx xorq %rsi,%rsi movq %rax,16+8(%rsp) jmp .Lsqrx8x_tail .align 32 .Lsqrx8x_tail_done: xorq %rax,%rax addq 24+8(%rsp),%r8 adcq $0,%r9 adcq $0,%r10 adcq $0,%r11 adcq $0,%r12 adcq $0,%r13 adcq $0,%r14 adcq $0,%r15 adcq $0,%rax subq 16+8(%rsp),%rsi .Lsqrx8x_no_tail: adcq 0(%rdi),%r8 .byte 102,72,15,126,217 adcq 8(%rdi),%r9 movq 56(%rbp),%rsi .byte 102,72,15,126,213 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 adcq $0,%rax movq 32+8(%rsp),%rbx movq 64(%rdi,%rcx,1),%rdx movq %r8,0(%rdi) leaq 64(%rdi),%r8 movq %r9,8(%rdi) movq %r10,16(%rdi) movq %r11,24(%rdi) movq %r12,32(%rdi) movq %r13,40(%rdi) movq %r14,48(%rdi) movq %r15,56(%rdi) leaq 64(%rdi,%rcx,1),%rdi cmpq 8+8(%rsp),%r8 jb .Lsqrx8x_reduction_loop ret .cfi_endproc .size bn_sqrx8x_internal,.-bn_sqrx8x_internal .align 32 .type __bn_postx4x_internal,@function __bn_postx4x_internal: .cfi_startproc movq 0(%rbp),%r12 movq %rcx,%r10 movq %rcx,%r9 negq %rax sarq $3+2,%rcx .byte 102,72,15,126,202 .byte 102,72,15,126,206 decq %r12 movq 8(%rbp),%r13 xorq %r8,%r8 movq 16(%rbp),%r14 movq 24(%rbp),%r15 jmp .Lsqrx4x_sub_entry .align 16 .Lsqrx4x_sub: movq 0(%rbp),%r12 movq 8(%rbp),%r13 movq 16(%rbp),%r14 movq 24(%rbp),%r15 .Lsqrx4x_sub_entry: andnq %rax,%r12,%r12 leaq 32(%rbp),%rbp andnq %rax,%r13,%r13 andnq %rax,%r14,%r14 andnq %rax,%r15,%r15 negq %r8 adcq 0(%rdi),%r12 adcq 8(%rdi),%r13 adcq 16(%rdi),%r14 adcq 24(%rdi),%r15 movq %r12,0(%rdx) leaq 32(%rdi),%rdi movq %r13,8(%rdx) sbbq %r8,%r8 movq %r14,16(%rdx) movq %r15,24(%rdx) leaq 32(%rdx),%rdx incq %rcx jnz .Lsqrx4x_sub negq %r9 ret .cfi_endproc .size __bn_postx4x_internal,.-__bn_postx4x_internal .globl bn_scatter5 .hidden bn_scatter5 .type bn_scatter5,@function .align 16 bn_scatter5: .cfi_startproc _CET_ENDBR cmpl $0,%esi jz .Lscatter_epilogue leaq (%rdx,%rcx,8),%rdx .Lscatter: movq (%rdi),%rax leaq 8(%rdi),%rdi movq %rax,(%rdx) leaq 256(%rdx),%rdx subl $1,%esi jnz .Lscatter .Lscatter_epilogue: ret .cfi_endproc .size bn_scatter5,.-bn_scatter5 .globl bn_gather5 .hidden bn_gather5 .type bn_gather5,@function .align 32 bn_gather5: .cfi_startproc .LSEH_begin_bn_gather5: _CET_ENDBR .byte 0x4c,0x8d,0x14,0x24 .cfi_def_cfa_register %r10 .byte 0x48,0x81,0xec,0x08,0x01,0x00,0x00 leaq .Linc(%rip),%rax andq $-16,%rsp movd %ecx,%xmm5 movdqa 0(%rax),%xmm0 movdqa 16(%rax),%xmm1 leaq 128(%rdx),%r11 leaq 128(%rsp),%rax pshufd $0,%xmm5,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm1,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,-128(%rax) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,-112(%rax) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,-96(%rax) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,-80(%rax) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,-64(%rax) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,-48(%rax) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,-32(%rax) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,-16(%rax) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,0(%rax) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,16(%rax) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,32(%rax) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,48(%rax) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,64(%rax) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,80(%rax) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,96(%rax) movdqa %xmm4,%xmm2 movdqa %xmm3,112(%rax) jmp .Lgather .align 32 .Lgather: pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 movdqa -128(%r11),%xmm0 movdqa -112(%r11),%xmm1 movdqa -96(%r11),%xmm2 pand -128(%rax),%xmm0 movdqa -80(%r11),%xmm3 pand -112(%rax),%xmm1 por %xmm0,%xmm4 pand -96(%rax),%xmm2 por %xmm1,%xmm5 pand -80(%rax),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa -64(%r11),%xmm0 movdqa -48(%r11),%xmm1 movdqa -32(%r11),%xmm2 pand -64(%rax),%xmm0 movdqa -16(%r11),%xmm3 pand -48(%rax),%xmm1 por %xmm0,%xmm4 pand -32(%rax),%xmm2 por %xmm1,%xmm5 pand -16(%rax),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 0(%r11),%xmm0 movdqa 16(%r11),%xmm1 movdqa 32(%r11),%xmm2 pand 0(%rax),%xmm0 movdqa 48(%r11),%xmm3 pand 16(%rax),%xmm1 por %xmm0,%xmm4 pand 32(%rax),%xmm2 por %xmm1,%xmm5 pand 48(%rax),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 64(%r11),%xmm0 movdqa 80(%r11),%xmm1 movdqa 96(%r11),%xmm2 pand 64(%rax),%xmm0 movdqa 112(%r11),%xmm3 pand 80(%rax),%xmm1 por %xmm0,%xmm4 pand 96(%rax),%xmm2 por %xmm1,%xmm5 pand 112(%rax),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 por %xmm5,%xmm4 leaq 256(%r11),%r11 pshufd $0x4e,%xmm4,%xmm0 por %xmm4,%xmm0 movq %xmm0,(%rdi) leaq 8(%rdi),%rdi subl $1,%esi jnz .Lgather leaq (%r10),%rsp .cfi_def_cfa_register %rsp ret .LSEH_end_bn_gather5: .cfi_endproc .size bn_gather5,.-bn_gather5 .section .rodata .align 64 .Linc: .long 0,0, 1,1 .long 2,2, 2,2 .byte 77,111,110,116,103,111,109,101,114,121,32,77,117,108,116,105,112,108,105,99,97,116,105,111,110,32,119,105,116,104,32,115,99,97,116,116,101,114,47,103,97,116,104,101,114,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 .text #endif
j4yc3-mw/Viren	2,659	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/third_party/fiat/asm/fiat_curve25519_adx_square.S	#include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && \ (defined(__APPLE__) \|\| defined(__ELF__)) .intel_syntax noprefix .text #if defined(__APPLE__) .private_extern _fiat_curve25519_adx_square .global _fiat_curve25519_adx_square _fiat_curve25519_adx_square: #else .type fiat_curve25519_adx_square, @function .hidden fiat_curve25519_adx_square .global fiat_curve25519_adx_square fiat_curve25519_adx_square: #endif .cfi_startproc _CET_ENDBR push rbp .cfi_adjust_cfa_offset 8 .cfi_offset rbp, -16 mov rbp, rsp mov rdx, [ rsi + 0x0 ] mulx r10, rax, [ rsi + 0x8 ] mov rdx, [ rsi + 0x0 ] mulx rcx, r11, [ rsi + 0x10 ] xor rdx, rdx adox r11, r10 mov rdx, [ rsi + 0x0 ] mulx r9, r8, [ rsi + 0x18 ] mov rdx, [ rsi + 0x8 ] mov [ rsp - 0x80 ], rbx .cfi_offset rbx, -16-0x80 mulx rbx, r10, [ rsi + 0x18 ] adox r8, rcx mov [rsp - 0x48 ], rdi adox r10, r9 adcx rax, rax mov rdx, [ rsi + 0x10 ] mulx r9, rcx, [ rsi + 0x18 ] adox rcx, rbx mov rdx, [ rsi + 0x10 ] mulx rdi, rbx, [ rsi + 0x8 ] mov rdx, 0x0 adox r9, rdx mov [ rsp - 0x70 ], r12 .cfi_offset r12, -16-0x70 mov r12, -0x3 inc r12 adox rbx, r8 adox rdi, r10 adcx r11, r11 mov r8, rdx adox r8, rcx mov r10, rdx adox r10, r9 adcx rbx, rbx mov rdx, [ rsi + 0x0 ] mulx r9, rcx, rdx mov rdx, [ rsi + 0x8 ] mov [ rsp - 0x68 ], r13 .cfi_offset r13, -16-0x68 mov [ rsp - 0x60 ], r14 .cfi_offset r14, -16-0x60 mulx r14, r13, rdx seto dl inc r12 adox r9, rax adox r13, r11 adox r14, rbx adcx rdi, rdi mov al, dl mov rdx, [ rsi + 0x10 ] mulx rbx, r11, rdx adox r11, rdi adcx r8, r8 adox rbx, r8 adcx r10, r10 movzx rdx, al mov rdi, 0x0 adcx rdx, rdi movzx r8, al lea r8, [ r8 + rdx ] mov rdx, [ rsi + 0x18 ] mulx rdi, rax, rdx adox rax, r10 mov rdx, 0x26 mov [ rsp - 0x58 ], r15 .cfi_offset r15, -16-0x58 mulx r15, r10, r11 clc adcx r10, rcx mulx r11, rcx, rbx adox r8, rdi mulx rdi, rbx, r8 inc r12 adox rcx, r9 mulx r8, r9, rax adcx r15, rcx adox r9, r13 adcx r11, r9 adox rbx, r14 adox rdi, r12 adcx r8, rbx adc rdi, 0x0 mulx r14, r13, rdi test al, al mov rdi, [ rsp - 0x48 ] adox r13, r10 mov r14, r12 adox r14, r15 mov [ rdi + 0x8 ], r14 mov rax, r12 adox rax, r11 mov r10, r12 adox r10, r8 mov [ rdi + 0x10 ], rax mov rcx, r12 cmovo rcx, rdx adcx r13, rcx mov [ rdi + 0x0 ], r13 mov [ rdi + 0x18 ], r10 mov rbx, [ rsp - 0x80 ] .cfi_restore rbx mov r12, [ rsp - 0x70 ] .cfi_restore r12 mov r13, [ rsp - 0x68 ] .cfi_restore r13 mov r14, [ rsp - 0x60 ] .cfi_restore r14 mov r15, [ rsp - 0x58 ] .cfi_restore r15 pop rbp .cfi_restore rbp .cfi_adjust_cfa_offset -8 ret .cfi_endproc #if defined(__ELF__) .size fiat_curve25519_adx_square, .-fiat_curve25519_adx_square #endif #endif
j4yc3-mw/Viren	3,464	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/third_party/fiat/asm/fiat_curve25519_adx_mul.S	#include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && \ (defined(__APPLE__) \|\| defined(__ELF__)) .intel_syntax noprefix .text #if defined(__APPLE__) .private_extern _fiat_curve25519_adx_mul .global _fiat_curve25519_adx_mul _fiat_curve25519_adx_mul: #else .type fiat_curve25519_adx_mul, @function .hidden fiat_curve25519_adx_mul .global fiat_curve25519_adx_mul fiat_curve25519_adx_mul: #endif .cfi_startproc _CET_ENDBR push rbp .cfi_adjust_cfa_offset 8 .cfi_offset rbp, -16 mov rbp, rsp mov rax, rdx mov rdx, [ rsi + 0x18 ] mulx r11, r10, [ rax + 0x8 ] mov rdx, [ rax + 0x0 ] mov [ rsp - 0x58 ], r15 .cfi_offset r15, -16-0x58 mulx r8, rcx, [ rsi + 0x18 ] mov rdx, [ rsi + 0x8 ] mov [ rsp - 0x80 ], rbx .cfi_offset rbx, -16-0x80 mulx rbx, r9, [ rax + 0x18 ] mov rdx, [ rsi + 0x8 ] mov [ rsp - 0x70 ], r12 .cfi_offset r12, -16-0x70 mulx r15, r12, [ rax + 0x8 ] mov rdx, [ rsi + 0x0 ] mov [ rsp - 0x68 ], r13 .cfi_offset r13, -16-0x68 mov [ rsp - 0x60 ], r14 .cfi_offset r14, -16-0x60 mulx r14, r13, [ rax + 0x0 ] mov rdx, [ rax + 0x10 ] mov [ rsp - 0x18 ], r15 mov [ rsp - 0x50 ], rdi mulx rdi, r15, [ rsi + 0x0 ] mov rdx, [ rax + 0x18 ] mov [ rsp - 0x48 ], r13 mov [ rsp - 0x40 ], r9 mulx r9, r13, [ rsi + 0x0 ] test al, al adox rcx, rdi mov rdx, [ rsi + 0x10 ] mov [ rsp - 0x38 ], r13 mulx r13, rdi, [ rax + 0x8 ] adox r10, r9 mov rdx, 0x0 adox rbx, rdx adcx rdi, rcx adcx r8, r10 mov r9, rdx adcx r9, rbx mov rdx, [ rsi + 0x10 ] mulx r10, rcx, [ rax + 0x0 ] mov rdx, [ rsi + 0x0 ] mov [ rsp - 0x30 ], r15 mulx r15, rbx, [ rax + 0x8 ] mov rdx, -0x2 inc rdx adox rcx, r15 setc r15b clc adcx rcx, r12 adox r10, rdi mov rdx, [ rax + 0x10 ] mov [ rsp - 0x78 ], rcx mulx rcx, rdi, [ rsi + 0x10 ] adox rdi, r8 mov rdx, [ rax + 0x18 ] mov [ rsp - 0x28 ], rcx mulx rcx, r8, [ rsi + 0x10 ] mov rdx, [ rax + 0x10 ] mov [ rsp - 0x20 ], r8 mulx r12, r8, [ rsi + 0x18 ] adox r8, r9 mov rdx, [ rsi + 0x8 ] mov [ rsp - 0x10 ], r12 mulx r12, r9, [ rax + 0x10 ] movzx rdx, r15b lea rdx, [ rdx + rcx ] adcx r9, r10 adcx r13, rdi mov r15, 0x0 mov r10, r15 adox r10, rdx mov rdx, [ rax + 0x18 ] mulx rcx, rdi, [ rsi + 0x18 ] adox rcx, r15 adcx r11, r8 mov rdx, r15 adcx rdx, r10 adcx rcx, r15 mov r8, rdx mov rdx, [ rax + 0x0 ] mulx r15, r10, [ rsi + 0x8 ] test al, al adox r10, r14 adcx rbx, r10 adox r15, [ rsp - 0x78 ] adcx r15, [ rsp - 0x30 ] adox r9, [ rsp - 0x18 ] adcx r9, [ rsp - 0x38 ] adox r13, [ rsp - 0x40 ] adcx r12, r13 adox r11, [ rsp - 0x20 ] adcx r11, [ rsp - 0x28 ] mov rdx, 0x26 mulx rsi, r14, r12 adox rdi, r8 adcx rdi, [ rsp - 0x10 ] mulx r10, r8, r11 mov r13, 0x0 adox rcx, r13 adcx rcx, r13 mulx r11, r12, rdi xor rdi, rdi adox r8, rbx adox r12, r15 mulx rbx, r13, rcx adcx r14, [ rsp - 0x48 ] adox r13, r9 adox rbx, rdi adcx rsi, r8 adcx r10, r12 adcx r11, r13 adc rbx, 0x0 mulx r9, r15, rbx xor r9, r9 adox r15, r14 mov rdi, r9 adox rdi, rsi mov rcx, r9 adox rcx, r10 mov r8, [ rsp - 0x50 ] mov [ r8 + 0x8 ], rdi mov r12, r9 adox r12, r11 mov r14, r9 cmovo r14, rdx mov [ r8 + 0x18 ], r12 adcx r15, r14 mov [ r8 + 0x0 ], r15 mov [ r8 + 0x10 ], rcx mov rbx, [ rsp - 0x80 ] .cfi_restore rbx mov r12, [ rsp - 0x70 ] .cfi_restore r12 mov r13, [ rsp - 0x68 ] .cfi_restore r13 mov r14, [ rsp - 0x60 ] .cfi_restore r14 mov r15, [ rsp - 0x58 ] .cfi_restore r15 pop rbp .cfi_restore rbp .cfi_adjust_cfa_offset -8 ret .cfi_endproc #if defined(__ELF__) .size fiat_curve25519_adx_mul, .-fiat_curve25519_adx_mul #endif #endif
j4yc3-mw/Viren	62,534	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/crypto/poly1305/poly1305_arm_asm.S	#include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__) #pragma GCC diagnostic ignored "-Wlanguage-extension-token" # This implementation was taken from the public domain, neon2 version in # SUPERCOP by D. J. Bernstein and Peter Schwabe. # qhasm: int32 input_0 # qhasm: int32 input_1 # qhasm: int32 input_2 # qhasm: int32 input_3 # qhasm: stack32 input_4 # qhasm: stack32 input_5 # qhasm: stack32 input_6 # qhasm: stack32 input_7 # qhasm: int32 caller_r4 # qhasm: int32 caller_r5 # qhasm: int32 caller_r6 # qhasm: int32 caller_r7 # qhasm: int32 caller_r8 # qhasm: int32 caller_r9 # qhasm: int32 caller_r10 # qhasm: int32 caller_r11 # qhasm: int32 caller_r12 # qhasm: int32 caller_r14 # qhasm: reg128 caller_q4 # qhasm: reg128 caller_q5 # qhasm: reg128 caller_q6 # qhasm: reg128 caller_q7 # qhasm: startcode .fpu neon .text # qhasm: reg128 r0 # qhasm: reg128 r1 # qhasm: reg128 r2 # qhasm: reg128 r3 # qhasm: reg128 r4 # qhasm: reg128 x01 # qhasm: reg128 x23 # qhasm: reg128 x4 # qhasm: reg128 y0 # qhasm: reg128 y12 # qhasm: reg128 y34 # qhasm: reg128 5y12 # qhasm: reg128 5y34 # qhasm: stack128 y0_stack # qhasm: stack128 y12_stack # qhasm: stack128 y34_stack # qhasm: stack128 5y12_stack # qhasm: stack128 5y34_stack # qhasm: reg128 z0 # qhasm: reg128 z12 # qhasm: reg128 z34 # qhasm: reg128 5z12 # qhasm: reg128 5z34 # qhasm: stack128 z0_stack # qhasm: stack128 z12_stack # qhasm: stack128 z34_stack # qhasm: stack128 5z12_stack # qhasm: stack128 5z34_stack # qhasm: stack128 two24 # qhasm: int32 ptr # qhasm: reg128 c01 # qhasm: reg128 c23 # qhasm: reg128 d01 # qhasm: reg128 d23 # qhasm: reg128 t0 # qhasm: reg128 t1 # qhasm: reg128 t2 # qhasm: reg128 t3 # qhasm: reg128 t4 # qhasm: reg128 mask # qhasm: reg128 u0 # qhasm: reg128 u1 # qhasm: reg128 u2 # qhasm: reg128 u3 # qhasm: reg128 u4 # qhasm: reg128 v01 # qhasm: reg128 mid # qhasm: reg128 v23 # qhasm: reg128 v4 # qhasm: int32 len # qhasm: qpushenter crypto_onetimeauth_poly1305_neon2_blocks .align 4 .global openssl_poly1305_neon2_blocks .hidden openssl_poly1305_neon2_blocks .type openssl_poly1305_neon2_blocks STT_FUNC openssl_poly1305_neon2_blocks: vpush {q4,q5,q6,q7} mov r12,sp sub sp,sp,#192 bic sp,sp,#31 # qhasm: len = input_3 # asm 1: mov >len=int32#4,<input_3=int32#4 # asm 2: mov >len=r3,<input_3=r3 mov r3,r3 # qhasm: new y0 # qhasm: y0 = mem64[input_1]y0[1]; input_1 += 8 # asm 1: vld1.8 {<y0=reg128#1%bot},[<input_1=int32#2]! # asm 2: vld1.8 {<y0=d0},[<input_1=r1]! vld1.8 {d0},[r1]! # qhasm: y12 = mem128[input_1]; input_1 += 16 # asm 1: vld1.8 {>y12=reg128#2%bot->y12=reg128#2%top},[<input_1=int32#2]! # asm 2: vld1.8 {>y12=d2->y12=d3},[<input_1=r1]! vld1.8 {d2-d3},[r1]! # qhasm: y34 = mem128[input_1]; input_1 += 16 # asm 1: vld1.8 {>y34=reg128#3%bot->y34=reg128#3%top},[<input_1=int32#2]! # asm 2: vld1.8 {>y34=d4->y34=d5},[<input_1=r1]! vld1.8 {d4-d5},[r1]! # qhasm: input_1 += 8 # asm 1: add >input_1=int32#2,<input_1=int32#2,#8 # asm 2: add >input_1=r1,<input_1=r1,#8 add r1,r1,#8 # qhasm: new z0 # qhasm: z0 = mem64[input_1]z0[1]; input_1 += 8 # asm 1: vld1.8 {<z0=reg128#4%bot},[<input_1=int32#2]! # asm 2: vld1.8 {<z0=d6},[<input_1=r1]! vld1.8 {d6},[r1]! # qhasm: z12 = mem128[input_1]; input_1 += 16 # asm 1: vld1.8 {>z12=reg128#5%bot->z12=reg128#5%top},[<input_1=int32#2]! # asm 2: vld1.8 {>z12=d8->z12=d9},[<input_1=r1]! vld1.8 {d8-d9},[r1]! # qhasm: z34 = mem128[input_1]; input_1 += 16 # asm 1: vld1.8 {>z34=reg128#6%bot->z34=reg128#6%top},[<input_1=int32#2]! # asm 2: vld1.8 {>z34=d10->z34=d11},[<input_1=r1]! vld1.8 {d10-d11},[r1]! # qhasm: 2x mask = 0xffffffff # asm 1: vmov.i64 >mask=reg128#7,#0xffffffff # asm 2: vmov.i64 >mask=q6,#0xffffffff vmov.i64 q6,#0xffffffff # qhasm: 2x u4 = 0xff # asm 1: vmov.i64 >u4=reg128#8,#0xff # asm 2: vmov.i64 >u4=q7,#0xff vmov.i64 q7,#0xff # qhasm: x01 aligned= mem128[input_0];input_0+=16 # asm 1: vld1.8 {>x01=reg128#9%bot->x01=reg128#9%top},[<input_0=int32#1,: 128]! # asm 2: vld1.8 {>x01=d16->x01=d17},[<input_0=r0,: 128]! vld1.8 {d16-d17},[r0,: 128]! # qhasm: x23 aligned= mem128[input_0];input_0+=16 # asm 1: vld1.8 {>x23=reg128#10%bot->x23=reg128#10%top},[<input_0=int32#1,: 128]! # asm 2: vld1.8 {>x23=d18->x23=d19},[<input_0=r0,: 128]! vld1.8 {d18-d19},[r0,: 128]! # qhasm: x4 aligned= mem64[input_0]x4[1] # asm 1: vld1.8 {<x4=reg128#11%bot},[<input_0=int32#1,: 64] # asm 2: vld1.8 {<x4=d20},[<input_0=r0,: 64] vld1.8 {d20},[r0,: 64] # qhasm: input_0 -= 32 # asm 1: sub >input_0=int32#1,<input_0=int32#1,#32 # asm 2: sub >input_0=r0,<input_0=r0,#32 sub r0,r0,#32 # qhasm: 2x mask unsigned>>=6 # asm 1: vshr.u64 >mask=reg128#7,<mask=reg128#7,#6 # asm 2: vshr.u64 >mask=q6,<mask=q6,#6 vshr.u64 q6,q6,#6 # qhasm: 2x u4 unsigned>>= 7 # asm 1: vshr.u64 >u4=reg128#8,<u4=reg128#8,#7 # asm 2: vshr.u64 >u4=q7,<u4=q7,#7 vshr.u64 q7,q7,#7 # qhasm: 4x 5y12 = y12 << 2 # asm 1: vshl.i32 >5y12=reg128#12,<y12=reg128#2,#2 # asm 2: vshl.i32 >5y12=q11,<y12=q1,#2 vshl.i32 q11,q1,#2 # qhasm: 4x 5y34 = y34 << 2 # asm 1: vshl.i32 >5y34=reg128#13,<y34=reg128#3,#2 # asm 2: vshl.i32 >5y34=q12,<y34=q2,#2 vshl.i32 q12,q2,#2 # qhasm: 4x 5y12 += y12 # asm 1: vadd.i32 >5y12=reg128#12,<5y12=reg128#12,<y12=reg128#2 # asm 2: vadd.i32 >5y12=q11,<5y12=q11,<y12=q1 vadd.i32 q11,q11,q1 # qhasm: 4x 5y34 += y34 # asm 1: vadd.i32 >5y34=reg128#13,<5y34=reg128#13,<y34=reg128#3 # asm 2: vadd.i32 >5y34=q12,<5y34=q12,<y34=q2 vadd.i32 q12,q12,q2 # qhasm: 2x u4 <<= 24 # asm 1: vshl.i64 >u4=reg128#8,<u4=reg128#8,#24 # asm 2: vshl.i64 >u4=q7,<u4=q7,#24 vshl.i64 q7,q7,#24 # qhasm: 4x 5z12 = z12 << 2 # asm 1: vshl.i32 >5z12=reg128#14,<z12=reg128#5,#2 # asm 2: vshl.i32 >5z12=q13,<z12=q4,#2 vshl.i32 q13,q4,#2 # qhasm: 4x 5z34 = z34 << 2 # asm 1: vshl.i32 >5z34=reg128#15,<z34=reg128#6,#2 # asm 2: vshl.i32 >5z34=q14,<z34=q5,#2 vshl.i32 q14,q5,#2 # qhasm: 4x 5z12 += z12 # asm 1: vadd.i32 >5z12=reg128#14,<5z12=reg128#14,<z12=reg128#5 # asm 2: vadd.i32 >5z12=q13,<5z12=q13,<z12=q4 vadd.i32 q13,q13,q4 # qhasm: 4x 5z34 += z34 # asm 1: vadd.i32 >5z34=reg128#15,<5z34=reg128#15,<z34=reg128#6 # asm 2: vadd.i32 >5z34=q14,<5z34=q14,<z34=q5 vadd.i32 q14,q14,q5 # qhasm: new two24 # qhasm: new y0_stack # qhasm: new y12_stack # qhasm: new y34_stack # qhasm: new 5y12_stack # qhasm: new 5y34_stack # qhasm: new z0_stack # qhasm: new z12_stack # qhasm: new z34_stack # qhasm: new 5z12_stack # qhasm: new 5z34_stack # qhasm: ptr = &two24 # asm 1: lea >ptr=int32#2,<two24=stack128#1 # asm 2: lea >ptr=r1,<two24=[sp,#0] add r1,sp,#0 # qhasm: mem128[ptr] aligned= u4 # asm 1: vst1.8 {<u4=reg128#8%bot-<u4=reg128#8%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<u4=d14-<u4=d15},[<ptr=r1,: 128] vst1.8 {d14-d15},[r1,: 128] # qhasm: r4 = u4 # asm 1: vmov >r4=reg128#16,<u4=reg128#8 # asm 2: vmov >r4=q15,<u4=q7 vmov q15,q7 # qhasm: r0 = u4 # asm 1: vmov >r0=reg128#8,<u4=reg128#8 # asm 2: vmov >r0=q7,<u4=q7 vmov q7,q7 # qhasm: ptr = &y0_stack # asm 1: lea >ptr=int32#2,<y0_stack=stack128#2 # asm 2: lea >ptr=r1,<y0_stack=[sp,#16] add r1,sp,#16 # qhasm: mem128[ptr] aligned= y0 # asm 1: vst1.8 {<y0=reg128#1%bot-<y0=reg128#1%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<y0=d0-<y0=d1},[<ptr=r1,: 128] vst1.8 {d0-d1},[r1,: 128] # qhasm: ptr = &y12_stack # asm 1: lea >ptr=int32#2,<y12_stack=stack128#3 # asm 2: lea >ptr=r1,<y12_stack=[sp,#32] add r1,sp,#32 # qhasm: mem128[ptr] aligned= y12 # asm 1: vst1.8 {<y12=reg128#2%bot-<y12=reg128#2%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<y12=d2-<y12=d3},[<ptr=r1,: 128] vst1.8 {d2-d3},[r1,: 128] # qhasm: ptr = &y34_stack # asm 1: lea >ptr=int32#2,<y34_stack=stack128#4 # asm 2: lea >ptr=r1,<y34_stack=[sp,#48] add r1,sp,#48 # qhasm: mem128[ptr] aligned= y34 # asm 1: vst1.8 {<y34=reg128#3%bot-<y34=reg128#3%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<y34=d4-<y34=d5},[<ptr=r1,: 128] vst1.8 {d4-d5},[r1,: 128] # qhasm: ptr = &z0_stack # asm 1: lea >ptr=int32#2,<z0_stack=stack128#7 # asm 2: lea >ptr=r1,<z0_stack=[sp,#96] add r1,sp,#96 # qhasm: mem128[ptr] aligned= z0 # asm 1: vst1.8 {<z0=reg128#4%bot-<z0=reg128#4%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<z0=d6-<z0=d7},[<ptr=r1,: 128] vst1.8 {d6-d7},[r1,: 128] # qhasm: ptr = &z12_stack # asm 1: lea >ptr=int32#2,<z12_stack=stack128#8 # asm 2: lea >ptr=r1,<z12_stack=[sp,#112] add r1,sp,#112 # qhasm: mem128[ptr] aligned= z12 # asm 1: vst1.8 {<z12=reg128#5%bot-<z12=reg128#5%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<z12=d8-<z12=d9},[<ptr=r1,: 128] vst1.8 {d8-d9},[r1,: 128] # qhasm: ptr = &z34_stack # asm 1: lea >ptr=int32#2,<z34_stack=stack128#9 # asm 2: lea >ptr=r1,<z34_stack=[sp,#128] add r1,sp,#128 # qhasm: mem128[ptr] aligned= z34 # asm 1: vst1.8 {<z34=reg128#6%bot-<z34=reg128#6%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<z34=d10-<z34=d11},[<ptr=r1,: 128] vst1.8 {d10-d11},[r1,: 128] # qhasm: ptr = &5y12_stack # asm 1: lea >ptr=int32#2,<5y12_stack=stack128#5 # asm 2: lea >ptr=r1,<5y12_stack=[sp,#64] add r1,sp,#64 # qhasm: mem128[ptr] aligned= 5y12 # asm 1: vst1.8 {<5y12=reg128#12%bot-<5y12=reg128#12%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<5y12=d22-<5y12=d23},[<ptr=r1,: 128] vst1.8 {d22-d23},[r1,: 128] # qhasm: ptr = &5y34_stack # asm 1: lea >ptr=int32#2,<5y34_stack=stack128#6 # asm 2: lea >ptr=r1,<5y34_stack=[sp,#80] add r1,sp,#80 # qhasm: mem128[ptr] aligned= 5y34 # asm 1: vst1.8 {<5y34=reg128#13%bot-<5y34=reg128#13%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<5y34=d24-<5y34=d25},[<ptr=r1,: 128] vst1.8 {d24-d25},[r1,: 128] # qhasm: ptr = &5z12_stack # asm 1: lea >ptr=int32#2,<5z12_stack=stack128#10 # asm 2: lea >ptr=r1,<5z12_stack=[sp,#144] add r1,sp,#144 # qhasm: mem128[ptr] aligned= 5z12 # asm 1: vst1.8 {<5z12=reg128#14%bot-<5z12=reg128#14%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<5z12=d26-<5z12=d27},[<ptr=r1,: 128] vst1.8 {d26-d27},[r1,: 128] # qhasm: ptr = &5z34_stack # asm 1: lea >ptr=int32#2,<5z34_stack=stack128#11 # asm 2: lea >ptr=r1,<5z34_stack=[sp,#160] add r1,sp,#160 # qhasm: mem128[ptr] aligned= 5z34 # asm 1: vst1.8 {<5z34=reg128#15%bot-<5z34=reg128#15%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<5z34=d28-<5z34=d29},[<ptr=r1,: 128] vst1.8 {d28-d29},[r1,: 128] # qhasm: unsigned>? len - 64 # asm 1: cmp <len=int32#4,#64 # asm 2: cmp <len=r3,#64 cmp r3,#64 # qhasm: goto below64bytes if !unsigned> bls ._below64bytes # qhasm: input_2 += 32 # asm 1: add >input_2=int32#2,<input_2=int32#3,#32 # asm 2: add >input_2=r1,<input_2=r2,#32 add r1,r2,#32 # qhasm: mainloop2: ._mainloop2: # qhasm: c01 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>c01=reg128#1%bot->c01=reg128#1%top},[<input_2=int32#2]! # asm 2: vld1.8 {>c01=d0->c01=d1},[<input_2=r1]! vld1.8 {d0-d1},[r1]! # qhasm: c23 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>c23=reg128#2%bot->c23=reg128#2%top},[<input_2=int32#2]! # asm 2: vld1.8 {>c23=d2->c23=d3},[<input_2=r1]! vld1.8 {d2-d3},[r1]! # qhasm: r4[0,1] += x01[0] unsigned* z34[2]; r4[2,3] += x01[1] unsigned* z34[3] # asm 1: vmlal.u32 <r4=reg128#16,<x01=reg128#9%bot,<z34=reg128#6%top # asm 2: vmlal.u32 <r4=q15,<x01=d16,<z34=d11 vmlal.u32 q15,d16,d11 # qhasm: ptr = &z12_stack # asm 1: lea >ptr=int32#3,<z12_stack=stack128#8 # asm 2: lea >ptr=r2,<z12_stack=[sp,#112] add r2,sp,#112 # qhasm: z12 aligned= mem128[ptr] # asm 1: vld1.8 {>z12=reg128#3%bot->z12=reg128#3%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>z12=d4->z12=d5},[<ptr=r2,: 128] vld1.8 {d4-d5},[r2,: 128] # qhasm: r4[0,1] += x01[2] unsigned* z34[0]; r4[2,3] += x01[3] unsigned* z34[1] # asm 1: vmlal.u32 <r4=reg128#16,<x01=reg128#9%top,<z34=reg128#6%bot # asm 2: vmlal.u32 <r4=q15,<x01=d17,<z34=d10 vmlal.u32 q15,d17,d10 # qhasm: ptr = &z0_stack # asm 1: lea >ptr=int32#3,<z0_stack=stack128#7 # asm 2: lea >ptr=r2,<z0_stack=[sp,#96] add r2,sp,#96 # qhasm: z0 aligned= mem128[ptr] # asm 1: vld1.8 {>z0=reg128#4%bot->z0=reg128#4%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>z0=d6->z0=d7},[<ptr=r2,: 128] vld1.8 {d6-d7},[r2,: 128] # qhasm: r4[0,1] += x23[0] unsigned* z12[2]; r4[2,3] += x23[1] unsigned* z12[3] # asm 1: vmlal.u32 <r4=reg128#16,<x23=reg128#10%bot,<z12=reg128#3%top # asm 2: vmlal.u32 <r4=q15,<x23=d18,<z12=d5 vmlal.u32 q15,d18,d5 # qhasm: c01 c23 = c01[0]c01[1]c01[2]c23[2]c23[0]c23[1]c01[3]c23[3] # asm 1: vtrn.32 <c01=reg128#1%top,<c23=reg128#2%top # asm 2: vtrn.32 <c01=d1,<c23=d3 vtrn.32 d1,d3 # qhasm: r4[0,1] += x23[2] unsigned* z12[0]; r4[2,3] += x23[3] unsigned* z12[1] # asm 1: vmlal.u32 <r4=reg128#16,<x23=reg128#10%top,<z12=reg128#3%bot # asm 2: vmlal.u32 <r4=q15,<x23=d19,<z12=d4 vmlal.u32 q15,d19,d4 # qhasm: r4[0,1] += x4[0] unsigned* z0[0]; r4[2,3] += x4[1] unsigned* z0[1] # asm 1: vmlal.u32 <r4=reg128#16,<x4=reg128#11%bot,<z0=reg128#4%bot # asm 2: vmlal.u32 <r4=q15,<x4=d20,<z0=d6 vmlal.u32 q15,d20,d6 # qhasm: r3[0,1] = c23[2]<<18; r3[2,3] = c23[3]<<18 # asm 1: vshll.u32 >r3=reg128#5,<c23=reg128#2%top,#18 # asm 2: vshll.u32 >r3=q4,<c23=d3,#18 vshll.u32 q4,d3,#18 # qhasm: c01 c23 = c01[0]c23[0]c01[2]c01[3]c01[1]c23[1]c23[2]c23[3] # asm 1: vtrn.32 <c01=reg128#1%bot,<c23=reg128#2%bot # asm 2: vtrn.32 <c01=d0,<c23=d2 vtrn.32 d0,d2 # qhasm: r3[0,1] += x01[0] unsigned* z34[0]; r3[2,3] += x01[1] unsigned* z34[1] # asm 1: vmlal.u32 <r3=reg128#5,<x01=reg128#9%bot,<z34=reg128#6%bot # asm 2: vmlal.u32 <r3=q4,<x01=d16,<z34=d10 vmlal.u32 q4,d16,d10 # qhasm: r3[0,1] += x01[2] unsigned* z12[2]; r3[2,3] += x01[3] unsigned* z12[3] # asm 1: vmlal.u32 <r3=reg128#5,<x01=reg128#9%top,<z12=reg128#3%top # asm 2: vmlal.u32 <r3=q4,<x01=d17,<z12=d5 vmlal.u32 q4,d17,d5 # qhasm: r0 = r0[1]c01[0]r0[2,3] # asm 1: vext.32 <r0=reg128#8%bot,<r0=reg128#8%bot,<c01=reg128#1%bot,#1 # asm 2: vext.32 <r0=d14,<r0=d14,<c01=d0,#1 vext.32 d14,d14,d0,#1 # qhasm: r3[0,1] += x23[0] unsigned* z12[0]; r3[2,3] += x23[1] unsigned* z12[1] # asm 1: vmlal.u32 <r3=reg128#5,<x23=reg128#10%bot,<z12=reg128#3%bot # asm 2: vmlal.u32 <r3=q4,<x23=d18,<z12=d4 vmlal.u32 q4,d18,d4 # qhasm: input_2 -= 64 # asm 1: sub >input_2=int32#2,<input_2=int32#2,#64 # asm 2: sub >input_2=r1,<input_2=r1,#64 sub r1,r1,#64 # qhasm: r3[0,1] += x23[2] unsigned* z0[0]; r3[2,3] += x23[3] unsigned* z0[1] # asm 1: vmlal.u32 <r3=reg128#5,<x23=reg128#10%top,<z0=reg128#4%bot # asm 2: vmlal.u32 <r3=q4,<x23=d19,<z0=d6 vmlal.u32 q4,d19,d6 # qhasm: ptr = &5z34_stack # asm 1: lea >ptr=int32#3,<5z34_stack=stack128#11 # asm 2: lea >ptr=r2,<5z34_stack=[sp,#160] add r2,sp,#160 # qhasm: 5z34 aligned= mem128[ptr] # asm 1: vld1.8 {>5z34=reg128#6%bot->5z34=reg128#6%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>5z34=d10->5z34=d11},[<ptr=r2,: 128] vld1.8 {d10-d11},[r2,: 128] # qhasm: r3[0,1] += x4[0] unsigned* 5z34[2]; r3[2,3] += x4[1] unsigned* 5z34[3] # asm 1: vmlal.u32 <r3=reg128#5,<x4=reg128#11%bot,<5z34=reg128#6%top # asm 2: vmlal.u32 <r3=q4,<x4=d20,<5z34=d11 vmlal.u32 q4,d20,d11 # qhasm: r0 = r0[1]r0[0]r0[3]r0[2] # asm 1: vrev64.i32 >r0=reg128#8,<r0=reg128#8 # asm 2: vrev64.i32 >r0=q7,<r0=q7 vrev64.i32 q7,q7 # qhasm: r2[0,1] = c01[2]<<12; r2[2,3] = c01[3]<<12 # asm 1: vshll.u32 >r2=reg128#14,<c01=reg128#1%top,#12 # asm 2: vshll.u32 >r2=q13,<c01=d1,#12 vshll.u32 q13,d1,#12 # qhasm: d01 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>d01=reg128#12%bot->d01=reg128#12%top},[<input_2=int32#2]! # asm 2: vld1.8 {>d01=d22->d01=d23},[<input_2=r1]! vld1.8 {d22-d23},[r1]! # qhasm: r2[0,1] += x01[0] unsigned* z12[2]; r2[2,3] += x01[1] unsigned* z12[3] # asm 1: vmlal.u32 <r2=reg128#14,<x01=reg128#9%bot,<z12=reg128#3%top # asm 2: vmlal.u32 <r2=q13,<x01=d16,<z12=d5 vmlal.u32 q13,d16,d5 # qhasm: r2[0,1] += x01[2] unsigned* z12[0]; r2[2,3] += x01[3] unsigned* z12[1] # asm 1: vmlal.u32 <r2=reg128#14,<x01=reg128#9%top,<z12=reg128#3%bot # asm 2: vmlal.u32 <r2=q13,<x01=d17,<z12=d4 vmlal.u32 q13,d17,d4 # qhasm: r2[0,1] += x23[0] unsigned* z0[0]; r2[2,3] += x23[1] unsigned* z0[1] # asm 1: vmlal.u32 <r2=reg128#14,<x23=reg128#10%bot,<z0=reg128#4%bot # asm 2: vmlal.u32 <r2=q13,<x23=d18,<z0=d6 vmlal.u32 q13,d18,d6 # qhasm: r2[0,1] += x23[2] unsigned* 5z34[2]; r2[2,3] += x23[3] unsigned* 5z34[3] # asm 1: vmlal.u32 <r2=reg128#14,<x23=reg128#10%top,<5z34=reg128#6%top # asm 2: vmlal.u32 <r2=q13,<x23=d19,<5z34=d11 vmlal.u32 q13,d19,d11 # qhasm: r2[0,1] += x4[0] unsigned* 5z34[0]; r2[2,3] += x4[1] unsigned* 5z34[1] # asm 1: vmlal.u32 <r2=reg128#14,<x4=reg128#11%bot,<5z34=reg128#6%bot # asm 2: vmlal.u32 <r2=q13,<x4=d20,<5z34=d10 vmlal.u32 q13,d20,d10 # qhasm: r0 = r0[0,1]c01[1]r0[2] # asm 1: vext.32 <r0=reg128#8%top,<c01=reg128#1%bot,<r0=reg128#8%top,#1 # asm 2: vext.32 <r0=d15,<c01=d0,<r0=d15,#1 vext.32 d15,d0,d15,#1 # qhasm: r1[0,1] = c23[0]<<6; r1[2,3] = c23[1]<<6 # asm 1: vshll.u32 >r1=reg128#15,<c23=reg128#2%bot,#6 # asm 2: vshll.u32 >r1=q14,<c23=d2,#6 vshll.u32 q14,d2,#6 # qhasm: r1[0,1] += x01[0] unsigned* z12[0]; r1[2,3] += x01[1] unsigned* z12[1] # asm 1: vmlal.u32 <r1=reg128#15,<x01=reg128#9%bot,<z12=reg128#3%bot # asm 2: vmlal.u32 <r1=q14,<x01=d16,<z12=d4 vmlal.u32 q14,d16,d4 # qhasm: r1[0,1] += x01[2] unsigned* z0[0]; r1[2,3] += x01[3] unsigned* z0[1] # asm 1: vmlal.u32 <r1=reg128#15,<x01=reg128#9%top,<z0=reg128#4%bot # asm 2: vmlal.u32 <r1=q14,<x01=d17,<z0=d6 vmlal.u32 q14,d17,d6 # qhasm: r1[0,1] += x23[0] unsigned* 5z34[2]; r1[2,3] += x23[1] unsigned* 5z34[3] # asm 1: vmlal.u32 <r1=reg128#15,<x23=reg128#10%bot,<5z34=reg128#6%top # asm 2: vmlal.u32 <r1=q14,<x23=d18,<5z34=d11 vmlal.u32 q14,d18,d11 # qhasm: r1[0,1] += x23[2] unsigned* 5z34[0]; r1[2,3] += x23[3] unsigned* 5z34[1] # asm 1: vmlal.u32 <r1=reg128#15,<x23=reg128#10%top,<5z34=reg128#6%bot # asm 2: vmlal.u32 <r1=q14,<x23=d19,<5z34=d10 vmlal.u32 q14,d19,d10 # qhasm: ptr = &5z12_stack # asm 1: lea >ptr=int32#3,<5z12_stack=stack128#10 # asm 2: lea >ptr=r2,<5z12_stack=[sp,#144] add r2,sp,#144 # qhasm: 5z12 aligned= mem128[ptr] # asm 1: vld1.8 {>5z12=reg128#1%bot->5z12=reg128#1%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>5z12=d0->5z12=d1},[<ptr=r2,: 128] vld1.8 {d0-d1},[r2,: 128] # qhasm: r1[0,1] += x4[0] unsigned* 5z12[2]; r1[2,3] += x4[1] unsigned* 5z12[3] # asm 1: vmlal.u32 <r1=reg128#15,<x4=reg128#11%bot,<5z12=reg128#1%top # asm 2: vmlal.u32 <r1=q14,<x4=d20,<5z12=d1 vmlal.u32 q14,d20,d1 # qhasm: d23 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>d23=reg128#2%bot->d23=reg128#2%top},[<input_2=int32#2]! # asm 2: vld1.8 {>d23=d2->d23=d3},[<input_2=r1]! vld1.8 {d2-d3},[r1]! # qhasm: input_2 += 32 # asm 1: add >input_2=int32#2,<input_2=int32#2,#32 # asm 2: add >input_2=r1,<input_2=r1,#32 add r1,r1,#32 # qhasm: r0[0,1] += x4[0] unsigned* 5z12[0]; r0[2,3] += x4[1] unsigned* 5z12[1] # asm 1: vmlal.u32 <r0=reg128#8,<x4=reg128#11%bot,<5z12=reg128#1%bot # asm 2: vmlal.u32 <r0=q7,<x4=d20,<5z12=d0 vmlal.u32 q7,d20,d0 # qhasm: r0[0,1] += x23[0] unsigned* 5z34[0]; r0[2,3] += x23[1] unsigned* 5z34[1] # asm 1: vmlal.u32 <r0=reg128#8,<x23=reg128#10%bot,<5z34=reg128#6%bot # asm 2: vmlal.u32 <r0=q7,<x23=d18,<5z34=d10 vmlal.u32 q7,d18,d10 # qhasm: d01 d23 = d01[0] d23[0] d01[1] d23[1] # asm 1: vswp <d23=reg128#2%bot,<d01=reg128#12%top # asm 2: vswp <d23=d2,<d01=d23 vswp d2,d23 # qhasm: r0[0,1] += x23[2] unsigned* 5z12[2]; r0[2,3] += x23[3] unsigned* 5z12[3] # asm 1: vmlal.u32 <r0=reg128#8,<x23=reg128#10%top,<5z12=reg128#1%top # asm 2: vmlal.u32 <r0=q7,<x23=d19,<5z12=d1 vmlal.u32 q7,d19,d1 # qhasm: r0[0,1] += x01[0] unsigned* z0[0]; r0[2,3] += x01[1] unsigned* z0[1] # asm 1: vmlal.u32 <r0=reg128#8,<x01=reg128#9%bot,<z0=reg128#4%bot # asm 2: vmlal.u32 <r0=q7,<x01=d16,<z0=d6 vmlal.u32 q7,d16,d6 # qhasm: new mid # qhasm: 2x v4 = d23 unsigned>> 40 # asm 1: vshr.u64 >v4=reg128#4,<d23=reg128#2,#40 # asm 2: vshr.u64 >v4=q3,<d23=q1,#40 vshr.u64 q3,q1,#40 # qhasm: mid = d01[1]d23[0] mid[2,3] # asm 1: vext.32 <mid=reg128#1%bot,<d01=reg128#12%bot,<d23=reg128#2%bot,#1 # asm 2: vext.32 <mid=d0,<d01=d22,<d23=d2,#1 vext.32 d0,d22,d2,#1 # qhasm: new v23 # qhasm: v23[2] = d23[0,1] unsigned>> 14; v23[3] = d23[2,3] unsigned>> 14 # asm 1: vshrn.u64 <v23=reg128#10%top,<d23=reg128#2,#14 # asm 2: vshrn.u64 <v23=d19,<d23=q1,#14 vshrn.u64 d19,q1,#14 # qhasm: mid = mid[0,1] d01[3]d23[2] # asm 1: vext.32 <mid=reg128#1%top,<d01=reg128#12%top,<d23=reg128#2%top,#1 # asm 2: vext.32 <mid=d1,<d01=d23,<d23=d3,#1 vext.32 d1,d23,d3,#1 # qhasm: new v01 # qhasm: v01[2] = d01[0,1] unsigned>> 26; v01[3] = d01[2,3] unsigned>> 26 # asm 1: vshrn.u64 <v01=reg128#11%top,<d01=reg128#12,#26 # asm 2: vshrn.u64 <v01=d21,<d01=q11,#26 vshrn.u64 d21,q11,#26 # qhasm: v01 = d01[1]d01[0] v01[2,3] # asm 1: vext.32 <v01=reg128#11%bot,<d01=reg128#12%bot,<d01=reg128#12%bot,#1 # asm 2: vext.32 <v01=d20,<d01=d22,<d01=d22,#1 vext.32 d20,d22,d22,#1 # qhasm: r0[0,1] += x01[2] unsigned* 5z34[2]; r0[2,3] += x01[3] unsigned* 5z34[3] # asm 1: vmlal.u32 <r0=reg128#8,<x01=reg128#9%top,<5z34=reg128#6%top # asm 2: vmlal.u32 <r0=q7,<x01=d17,<5z34=d11 vmlal.u32 q7,d17,d11 # qhasm: v01 = v01[1]d01[2] v01[2,3] # asm 1: vext.32 <v01=reg128#11%bot,<v01=reg128#11%bot,<d01=reg128#12%top,#1 # asm 2: vext.32 <v01=d20,<v01=d20,<d01=d23,#1 vext.32 d20,d20,d23,#1 # qhasm: v23[0] = mid[0,1] unsigned>> 20; v23[1] = mid[2,3] unsigned>> 20 # asm 1: vshrn.u64 <v23=reg128#10%bot,<mid=reg128#1,#20 # asm 2: vshrn.u64 <v23=d18,<mid=q0,#20 vshrn.u64 d18,q0,#20 # qhasm: v4 = v4[0]v4[2]v4[1]v4[3] # asm 1: vtrn.32 <v4=reg128#4%bot,<v4=reg128#4%top # asm 2: vtrn.32 <v4=d6,<v4=d7 vtrn.32 d6,d7 # qhasm: 4x v01 &= 0x03ffffff # asm 1: vand.i32 <v01=reg128#11,#0x03ffffff # asm 2: vand.i32 <v01=q10,#0x03ffffff vand.i32 q10,#0x03ffffff # qhasm: ptr = &y34_stack # asm 1: lea >ptr=int32#3,<y34_stack=stack128#4 # asm 2: lea >ptr=r2,<y34_stack=[sp,#48] add r2,sp,#48 # qhasm: y34 aligned= mem128[ptr] # asm 1: vld1.8 {>y34=reg128#3%bot->y34=reg128#3%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>y34=d4->y34=d5},[<ptr=r2,: 128] vld1.8 {d4-d5},[r2,: 128] # qhasm: 4x v23 &= 0x03ffffff # asm 1: vand.i32 <v23=reg128#10,#0x03ffffff # asm 2: vand.i32 <v23=q9,#0x03ffffff vand.i32 q9,#0x03ffffff # qhasm: ptr = &y12_stack # asm 1: lea >ptr=int32#3,<y12_stack=stack128#3 # asm 2: lea >ptr=r2,<y12_stack=[sp,#32] add r2,sp,#32 # qhasm: y12 aligned= mem128[ptr] # asm 1: vld1.8 {>y12=reg128#2%bot->y12=reg128#2%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>y12=d2->y12=d3},[<ptr=r2,: 128] vld1.8 {d2-d3},[r2,: 128] # qhasm: 4x v4 \|= 0x01000000 # asm 1: vorr.i32 <v4=reg128#4,#0x01000000 # asm 2: vorr.i32 <v4=q3,#0x01000000 vorr.i32 q3,#0x01000000 # qhasm: ptr = &y0_stack # asm 1: lea >ptr=int32#3,<y0_stack=stack128#2 # asm 2: lea >ptr=r2,<y0_stack=[sp,#16] add r2,sp,#16 # qhasm: y0 aligned= mem128[ptr] # asm 1: vld1.8 {>y0=reg128#1%bot->y0=reg128#1%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>y0=d0->y0=d1},[<ptr=r2,: 128] vld1.8 {d0-d1},[r2,: 128] # qhasm: r4[0,1] += v01[0] unsigned* y34[2]; r4[2,3] += v01[1] unsigned* y34[3] # asm 1: vmlal.u32 <r4=reg128#16,<v01=reg128#11%bot,<y34=reg128#3%top # asm 2: vmlal.u32 <r4=q15,<v01=d20,<y34=d5 vmlal.u32 q15,d20,d5 # qhasm: r4[0,1] += v01[2] unsigned* y34[0]; r4[2,3] += v01[3] unsigned* y34[1] # asm 1: vmlal.u32 <r4=reg128#16,<v01=reg128#11%top,<y34=reg128#3%bot # asm 2: vmlal.u32 <r4=q15,<v01=d21,<y34=d4 vmlal.u32 q15,d21,d4 # qhasm: r4[0,1] += v23[0] unsigned* y12[2]; r4[2,3] += v23[1] unsigned* y12[3] # asm 1: vmlal.u32 <r4=reg128#16,<v23=reg128#10%bot,<y12=reg128#2%top # asm 2: vmlal.u32 <r4=q15,<v23=d18,<y12=d3 vmlal.u32 q15,d18,d3 # qhasm: r4[0,1] += v23[2] unsigned* y12[0]; r4[2,3] += v23[3] unsigned* y12[1] # asm 1: vmlal.u32 <r4=reg128#16,<v23=reg128#10%top,<y12=reg128#2%bot # asm 2: vmlal.u32 <r4=q15,<v23=d19,<y12=d2 vmlal.u32 q15,d19,d2 # qhasm: r4[0,1] += v4[0] unsigned* y0[0]; r4[2,3] += v4[1] unsigned* y0[1] # asm 1: vmlal.u32 <r4=reg128#16,<v4=reg128#4%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r4=q15,<v4=d6,<y0=d0 vmlal.u32 q15,d6,d0 # qhasm: ptr = &5y34_stack # asm 1: lea >ptr=int32#3,<5y34_stack=stack128#6 # asm 2: lea >ptr=r2,<5y34_stack=[sp,#80] add r2,sp,#80 # qhasm: 5y34 aligned= mem128[ptr] # asm 1: vld1.8 {>5y34=reg128#13%bot->5y34=reg128#13%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>5y34=d24->5y34=d25},[<ptr=r2,: 128] vld1.8 {d24-d25},[r2,: 128] # qhasm: r3[0,1] += v01[0] unsigned* y34[0]; r3[2,3] += v01[1] unsigned* y34[1] # asm 1: vmlal.u32 <r3=reg128#5,<v01=reg128#11%bot,<y34=reg128#3%bot # asm 2: vmlal.u32 <r3=q4,<v01=d20,<y34=d4 vmlal.u32 q4,d20,d4 # qhasm: r3[0,1] += v01[2] unsigned* y12[2]; r3[2,3] += v01[3] unsigned* y12[3] # asm 1: vmlal.u32 <r3=reg128#5,<v01=reg128#11%top,<y12=reg128#2%top # asm 2: vmlal.u32 <r3=q4,<v01=d21,<y12=d3 vmlal.u32 q4,d21,d3 # qhasm: r3[0,1] += v23[0] unsigned* y12[0]; r3[2,3] += v23[1] unsigned* y12[1] # asm 1: vmlal.u32 <r3=reg128#5,<v23=reg128#10%bot,<y12=reg128#2%bot # asm 2: vmlal.u32 <r3=q4,<v23=d18,<y12=d2 vmlal.u32 q4,d18,d2 # qhasm: r3[0,1] += v23[2] unsigned* y0[0]; r3[2,3] += v23[3] unsigned* y0[1] # asm 1: vmlal.u32 <r3=reg128#5,<v23=reg128#10%top,<y0=reg128#1%bot # asm 2: vmlal.u32 <r3=q4,<v23=d19,<y0=d0 vmlal.u32 q4,d19,d0 # qhasm: r3[0,1] += v4[0] unsigned* 5y34[2]; r3[2,3] += v4[1] unsigned* 5y34[3] # asm 1: vmlal.u32 <r3=reg128#5,<v4=reg128#4%bot,<5y34=reg128#13%top # asm 2: vmlal.u32 <r3=q4,<v4=d6,<5y34=d25 vmlal.u32 q4,d6,d25 # qhasm: ptr = &5y12_stack # asm 1: lea >ptr=int32#3,<5y12_stack=stack128#5 # asm 2: lea >ptr=r2,<5y12_stack=[sp,#64] add r2,sp,#64 # qhasm: 5y12 aligned= mem128[ptr] # asm 1: vld1.8 {>5y12=reg128#12%bot->5y12=reg128#12%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>5y12=d22->5y12=d23},[<ptr=r2,: 128] vld1.8 {d22-d23},[r2,: 128] # qhasm: r0[0,1] += v4[0] unsigned* 5y12[0]; r0[2,3] += v4[1] unsigned* 5y12[1] # asm 1: vmlal.u32 <r0=reg128#8,<v4=reg128#4%bot,<5y12=reg128#12%bot # asm 2: vmlal.u32 <r0=q7,<v4=d6,<5y12=d22 vmlal.u32 q7,d6,d22 # qhasm: r0[0,1] += v23[0] unsigned* 5y34[0]; r0[2,3] += v23[1] unsigned* 5y34[1] # asm 1: vmlal.u32 <r0=reg128#8,<v23=reg128#10%bot,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r0=q7,<v23=d18,<5y34=d24 vmlal.u32 q7,d18,d24 # qhasm: r0[0,1] += v23[2] unsigned* 5y12[2]; r0[2,3] += v23[3] unsigned* 5y12[3] # asm 1: vmlal.u32 <r0=reg128#8,<v23=reg128#10%top,<5y12=reg128#12%top # asm 2: vmlal.u32 <r0=q7,<v23=d19,<5y12=d23 vmlal.u32 q7,d19,d23 # qhasm: r0[0,1] += v01[0] unsigned* y0[0]; r0[2,3] += v01[1] unsigned* y0[1] # asm 1: vmlal.u32 <r0=reg128#8,<v01=reg128#11%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r0=q7,<v01=d20,<y0=d0 vmlal.u32 q7,d20,d0 # qhasm: r0[0,1] += v01[2] unsigned* 5y34[2]; r0[2,3] += v01[3] unsigned* 5y34[3] # asm 1: vmlal.u32 <r0=reg128#8,<v01=reg128#11%top,<5y34=reg128#13%top # asm 2: vmlal.u32 <r0=q7,<v01=d21,<5y34=d25 vmlal.u32 q7,d21,d25 # qhasm: r1[0,1] += v01[0] unsigned* y12[0]; r1[2,3] += v01[1] unsigned* y12[1] # asm 1: vmlal.u32 <r1=reg128#15,<v01=reg128#11%bot,<y12=reg128#2%bot # asm 2: vmlal.u32 <r1=q14,<v01=d20,<y12=d2 vmlal.u32 q14,d20,d2 # qhasm: r1[0,1] += v01[2] unsigned* y0[0]; r1[2,3] += v01[3] unsigned* y0[1] # asm 1: vmlal.u32 <r1=reg128#15,<v01=reg128#11%top,<y0=reg128#1%bot # asm 2: vmlal.u32 <r1=q14,<v01=d21,<y0=d0 vmlal.u32 q14,d21,d0 # qhasm: r1[0,1] += v23[0] unsigned* 5y34[2]; r1[2,3] += v23[1] unsigned* 5y34[3] # asm 1: vmlal.u32 <r1=reg128#15,<v23=reg128#10%bot,<5y34=reg128#13%top # asm 2: vmlal.u32 <r1=q14,<v23=d18,<5y34=d25 vmlal.u32 q14,d18,d25 # qhasm: r1[0,1] += v23[2] unsigned* 5y34[0]; r1[2,3] += v23[3] unsigned* 5y34[1] # asm 1: vmlal.u32 <r1=reg128#15,<v23=reg128#10%top,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r1=q14,<v23=d19,<5y34=d24 vmlal.u32 q14,d19,d24 # qhasm: r1[0,1] += v4[0] unsigned* 5y12[2]; r1[2,3] += v4[1] unsigned* 5y12[3] # asm 1: vmlal.u32 <r1=reg128#15,<v4=reg128#4%bot,<5y12=reg128#12%top # asm 2: vmlal.u32 <r1=q14,<v4=d6,<5y12=d23 vmlal.u32 q14,d6,d23 # qhasm: r2[0,1] += v01[0] unsigned* y12[2]; r2[2,3] += v01[1] unsigned* y12[3] # asm 1: vmlal.u32 <r2=reg128#14,<v01=reg128#11%bot,<y12=reg128#2%top # asm 2: vmlal.u32 <r2=q13,<v01=d20,<y12=d3 vmlal.u32 q13,d20,d3 # qhasm: r2[0,1] += v01[2] unsigned* y12[0]; r2[2,3] += v01[3] unsigned* y12[1] # asm 1: vmlal.u32 <r2=reg128#14,<v01=reg128#11%top,<y12=reg128#2%bot # asm 2: vmlal.u32 <r2=q13,<v01=d21,<y12=d2 vmlal.u32 q13,d21,d2 # qhasm: r2[0,1] += v23[0] unsigned* y0[0]; r2[2,3] += v23[1] unsigned* y0[1] # asm 1: vmlal.u32 <r2=reg128#14,<v23=reg128#10%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r2=q13,<v23=d18,<y0=d0 vmlal.u32 q13,d18,d0 # qhasm: r2[0,1] += v23[2] unsigned* 5y34[2]; r2[2,3] += v23[3] unsigned* 5y34[3] # asm 1: vmlal.u32 <r2=reg128#14,<v23=reg128#10%top,<5y34=reg128#13%top # asm 2: vmlal.u32 <r2=q13,<v23=d19,<5y34=d25 vmlal.u32 q13,d19,d25 # qhasm: r2[0,1] += v4[0] unsigned* 5y34[0]; r2[2,3] += v4[1] unsigned* 5y34[1] # asm 1: vmlal.u32 <r2=reg128#14,<v4=reg128#4%bot,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r2=q13,<v4=d6,<5y34=d24 vmlal.u32 q13,d6,d24 # qhasm: ptr = &two24 # asm 1: lea >ptr=int32#3,<two24=stack128#1 # asm 2: lea >ptr=r2,<two24=[sp,#0] add r2,sp,#0 # qhasm: 2x t1 = r0 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#4,<r0=reg128#8,#26 # asm 2: vshr.u64 >t1=q3,<r0=q7,#26 vshr.u64 q3,q7,#26 # qhasm: len -= 64 # asm 1: sub >len=int32#4,<len=int32#4,#64 # asm 2: sub >len=r3,<len=r3,#64 sub r3,r3,#64 # qhasm: r0 &= mask # asm 1: vand >r0=reg128#6,<r0=reg128#8,<mask=reg128#7 # asm 2: vand >r0=q5,<r0=q7,<mask=q6 vand q5,q7,q6 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#15,<t1=reg128#4 # asm 2: vadd.i64 >r1=q3,<r1=q14,<t1=q3 vadd.i64 q3,q14,q3 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#8,<r3=reg128#5,#26 # asm 2: vshr.u64 >t4=q7,<r3=q4,#26 vshr.u64 q7,q4,#26 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#5,<r3=reg128#5,<mask=reg128#7 # asm 2: vand >r3=q4,<r3=q4,<mask=q6 vand q4,q4,q6 # qhasm: 2x x4 = r4 + t4 # asm 1: vadd.i64 >x4=reg128#8,<r4=reg128#16,<t4=reg128#8 # asm 2: vadd.i64 >x4=q7,<r4=q15,<t4=q7 vadd.i64 q7,q15,q7 # qhasm: r4 aligned= mem128[ptr] # asm 1: vld1.8 {>r4=reg128#16%bot->r4=reg128#16%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>r4=d30->r4=d31},[<ptr=r2,: 128] vld1.8 {d30-d31},[r2,: 128] # qhasm: 2x t2 = r1 unsigned>> 26 # asm 1: vshr.u64 >t2=reg128#9,<r1=reg128#4,#26 # asm 2: vshr.u64 >t2=q8,<r1=q3,#26 vshr.u64 q8,q3,#26 # qhasm: r1 &= mask # asm 1: vand >r1=reg128#4,<r1=reg128#4,<mask=reg128#7 # asm 2: vand >r1=q3,<r1=q3,<mask=q6 vand q3,q3,q6 # qhasm: 2x t0 = x4 unsigned>> 26 # asm 1: vshr.u64 >t0=reg128#10,<x4=reg128#8,#26 # asm 2: vshr.u64 >t0=q9,<x4=q7,#26 vshr.u64 q9,q7,#26 # qhasm: 2x r2 += t2 # asm 1: vadd.i64 >r2=reg128#9,<r2=reg128#14,<t2=reg128#9 # asm 2: vadd.i64 >r2=q8,<r2=q13,<t2=q8 vadd.i64 q8,q13,q8 # qhasm: x4 &= mask # asm 1: vand >x4=reg128#11,<x4=reg128#8,<mask=reg128#7 # asm 2: vand >x4=q10,<x4=q7,<mask=q6 vand q10,q7,q6 # qhasm: 2x x01 = r0 + t0 # asm 1: vadd.i64 >x01=reg128#6,<r0=reg128#6,<t0=reg128#10 # asm 2: vadd.i64 >x01=q5,<r0=q5,<t0=q9 vadd.i64 q5,q5,q9 # qhasm: r0 aligned= mem128[ptr] # asm 1: vld1.8 {>r0=reg128#8%bot->r0=reg128#8%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>r0=d14->r0=d15},[<ptr=r2,: 128] vld1.8 {d14-d15},[r2,: 128] # qhasm: ptr = &z34_stack # asm 1: lea >ptr=int32#3,<z34_stack=stack128#9 # asm 2: lea >ptr=r2,<z34_stack=[sp,#128] add r2,sp,#128 # qhasm: 2x t0 <<= 2 # asm 1: vshl.i64 >t0=reg128#10,<t0=reg128#10,#2 # asm 2: vshl.i64 >t0=q9,<t0=q9,#2 vshl.i64 q9,q9,#2 # qhasm: 2x t3 = r2 unsigned>> 26 # asm 1: vshr.u64 >t3=reg128#14,<r2=reg128#9,#26 # asm 2: vshr.u64 >t3=q13,<r2=q8,#26 vshr.u64 q13,q8,#26 # qhasm: 2x x01 += t0 # asm 1: vadd.i64 >x01=reg128#15,<x01=reg128#6,<t0=reg128#10 # asm 2: vadd.i64 >x01=q14,<x01=q5,<t0=q9 vadd.i64 q14,q5,q9 # qhasm: z34 aligned= mem128[ptr] # asm 1: vld1.8 {>z34=reg128#6%bot->z34=reg128#6%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>z34=d10->z34=d11},[<ptr=r2,: 128] vld1.8 {d10-d11},[r2,: 128] # qhasm: x23 = r2 & mask # asm 1: vand >x23=reg128#10,<r2=reg128#9,<mask=reg128#7 # asm 2: vand >x23=q9,<r2=q8,<mask=q6 vand q9,q8,q6 # qhasm: 2x r3 += t3 # asm 1: vadd.i64 >r3=reg128#5,<r3=reg128#5,<t3=reg128#14 # asm 2: vadd.i64 >r3=q4,<r3=q4,<t3=q13 vadd.i64 q4,q4,q13 # qhasm: input_2 += 32 # asm 1: add >input_2=int32#2,<input_2=int32#2,#32 # asm 2: add >input_2=r1,<input_2=r1,#32 add r1,r1,#32 # qhasm: 2x t1 = x01 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#14,<x01=reg128#15,#26 # asm 2: vshr.u64 >t1=q13,<x01=q14,#26 vshr.u64 q13,q14,#26 # qhasm: x23 = x23[0,2,1,3] # asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top # asm 2: vtrn.32 <x23=d18,<x23=d19 vtrn.32 d18,d19 # qhasm: x01 = x01 & mask # asm 1: vand >x01=reg128#9,<x01=reg128#15,<mask=reg128#7 # asm 2: vand >x01=q8,<x01=q14,<mask=q6 vand q8,q14,q6 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#4,<t1=reg128#14 # asm 2: vadd.i64 >r1=q3,<r1=q3,<t1=q13 vadd.i64 q3,q3,q13 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#14,<r3=reg128#5,#26 # asm 2: vshr.u64 >t4=q13,<r3=q4,#26 vshr.u64 q13,q4,#26 # qhasm: x01 = x01[0,2,1,3] # asm 1: vtrn.32 <x01=reg128#9%bot,<x01=reg128#9%top # asm 2: vtrn.32 <x01=d16,<x01=d17 vtrn.32 d16,d17 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#5,<r3=reg128#5,<mask=reg128#7 # asm 2: vand >r3=q4,<r3=q4,<mask=q6 vand q4,q4,q6 # qhasm: r1 = r1[0,2,1,3] # asm 1: vtrn.32 <r1=reg128#4%bot,<r1=reg128#4%top # asm 2: vtrn.32 <r1=d6,<r1=d7 vtrn.32 d6,d7 # qhasm: 2x x4 += t4 # asm 1: vadd.i64 >x4=reg128#11,<x4=reg128#11,<t4=reg128#14 # asm 2: vadd.i64 >x4=q10,<x4=q10,<t4=q13 vadd.i64 q10,q10,q13 # qhasm: r3 = r3[0,2,1,3] # asm 1: vtrn.32 <r3=reg128#5%bot,<r3=reg128#5%top # asm 2: vtrn.32 <r3=d8,<r3=d9 vtrn.32 d8,d9 # qhasm: x01 = x01[0,1] r1[0,1] # asm 1: vext.32 <x01=reg128#9%top,<r1=reg128#4%bot,<r1=reg128#4%bot,#0 # asm 2: vext.32 <x01=d17,<r1=d6,<r1=d6,#0 vext.32 d17,d6,d6,#0 # qhasm: x23 = x23[0,1] r3[0,1] # asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#5%bot,<r3=reg128#5%bot,#0 # asm 2: vext.32 <x23=d19,<r3=d8,<r3=d8,#0 vext.32 d19,d8,d8,#0 # qhasm: x4 = x4[0,2,1,3] # asm 1: vtrn.32 <x4=reg128#11%bot,<x4=reg128#11%top # asm 2: vtrn.32 <x4=d20,<x4=d21 vtrn.32 d20,d21 # qhasm: unsigned>? len - 64 # asm 1: cmp <len=int32#4,#64 # asm 2: cmp <len=r3,#64 cmp r3,#64 # qhasm: goto mainloop2 if unsigned> bhi ._mainloop2 # qhasm: input_2 -= 32 # asm 1: sub >input_2=int32#3,<input_2=int32#2,#32 # asm 2: sub >input_2=r2,<input_2=r1,#32 sub r2,r1,#32 # qhasm: below64bytes: ._below64bytes: # qhasm: unsigned>? len - 32 # asm 1: cmp <len=int32#4,#32 # asm 2: cmp <len=r3,#32 cmp r3,#32 # qhasm: goto end if !unsigned> bls ._end # qhasm: mainloop: ._mainloop: # qhasm: new r0 # qhasm: ptr = &two24 # asm 1: lea >ptr=int32#2,<two24=stack128#1 # asm 2: lea >ptr=r1,<two24=[sp,#0] add r1,sp,#0 # qhasm: r4 aligned= mem128[ptr] # asm 1: vld1.8 {>r4=reg128#5%bot->r4=reg128#5%top},[<ptr=int32#2,: 128] # asm 2: vld1.8 {>r4=d8->r4=d9},[<ptr=r1,: 128] vld1.8 {d8-d9},[r1,: 128] # qhasm: u4 aligned= mem128[ptr] # asm 1: vld1.8 {>u4=reg128#6%bot->u4=reg128#6%top},[<ptr=int32#2,: 128] # asm 2: vld1.8 {>u4=d10->u4=d11},[<ptr=r1,: 128] vld1.8 {d10-d11},[r1,: 128] # qhasm: c01 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>c01=reg128#8%bot->c01=reg128#8%top},[<input_2=int32#3]! # asm 2: vld1.8 {>c01=d14->c01=d15},[<input_2=r2]! vld1.8 {d14-d15},[r2]! # qhasm: r4[0,1] += x01[0] unsigned* y34[2]; r4[2,3] += x01[1] unsigned* y34[3] # asm 1: vmlal.u32 <r4=reg128#5,<x01=reg128#9%bot,<y34=reg128#3%top # asm 2: vmlal.u32 <r4=q4,<x01=d16,<y34=d5 vmlal.u32 q4,d16,d5 # qhasm: c23 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>c23=reg128#14%bot->c23=reg128#14%top},[<input_2=int32#3]! # asm 2: vld1.8 {>c23=d26->c23=d27},[<input_2=r2]! vld1.8 {d26-d27},[r2]! # qhasm: r4[0,1] += x01[2] unsigned* y34[0]; r4[2,3] += x01[3] unsigned* y34[1] # asm 1: vmlal.u32 <r4=reg128#5,<x01=reg128#9%top,<y34=reg128#3%bot # asm 2: vmlal.u32 <r4=q4,<x01=d17,<y34=d4 vmlal.u32 q4,d17,d4 # qhasm: r0 = u4[1]c01[0]r0[2,3] # asm 1: vext.32 <r0=reg128#4%bot,<u4=reg128#6%bot,<c01=reg128#8%bot,#1 # asm 2: vext.32 <r0=d6,<u4=d10,<c01=d14,#1 vext.32 d6,d10,d14,#1 # qhasm: r4[0,1] += x23[0] unsigned* y12[2]; r4[2,3] += x23[1] unsigned* y12[3] # asm 1: vmlal.u32 <r4=reg128#5,<x23=reg128#10%bot,<y12=reg128#2%top # asm 2: vmlal.u32 <r4=q4,<x23=d18,<y12=d3 vmlal.u32 q4,d18,d3 # qhasm: r0 = r0[0,1]u4[1]c23[0] # asm 1: vext.32 <r0=reg128#4%top,<u4=reg128#6%bot,<c23=reg128#14%bot,#1 # asm 2: vext.32 <r0=d7,<u4=d10,<c23=d26,#1 vext.32 d7,d10,d26,#1 # qhasm: r4[0,1] += x23[2] unsigned* y12[0]; r4[2,3] += x23[3] unsigned* y12[1] # asm 1: vmlal.u32 <r4=reg128#5,<x23=reg128#10%top,<y12=reg128#2%bot # asm 2: vmlal.u32 <r4=q4,<x23=d19,<y12=d2 vmlal.u32 q4,d19,d2 # qhasm: r0 = r0[1]r0[0]r0[3]r0[2] # asm 1: vrev64.i32 >r0=reg128#4,<r0=reg128#4 # asm 2: vrev64.i32 >r0=q3,<r0=q3 vrev64.i32 q3,q3 # qhasm: r4[0,1] += x4[0] unsigned* y0[0]; r4[2,3] += x4[1] unsigned* y0[1] # asm 1: vmlal.u32 <r4=reg128#5,<x4=reg128#11%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r4=q4,<x4=d20,<y0=d0 vmlal.u32 q4,d20,d0 # qhasm: r0[0,1] += x4[0] unsigned* 5y12[0]; r0[2,3] += x4[1] unsigned* 5y12[1] # asm 1: vmlal.u32 <r0=reg128#4,<x4=reg128#11%bot,<5y12=reg128#12%bot # asm 2: vmlal.u32 <r0=q3,<x4=d20,<5y12=d22 vmlal.u32 q3,d20,d22 # qhasm: r0[0,1] += x23[0] unsigned* 5y34[0]; r0[2,3] += x23[1] unsigned* 5y34[1] # asm 1: vmlal.u32 <r0=reg128#4,<x23=reg128#10%bot,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r0=q3,<x23=d18,<5y34=d24 vmlal.u32 q3,d18,d24 # qhasm: r0[0,1] += x23[2] unsigned* 5y12[2]; r0[2,3] += x23[3] unsigned* 5y12[3] # asm 1: vmlal.u32 <r0=reg128#4,<x23=reg128#10%top,<5y12=reg128#12%top # asm 2: vmlal.u32 <r0=q3,<x23=d19,<5y12=d23 vmlal.u32 q3,d19,d23 # qhasm: c01 c23 = c01[0]c23[0]c01[2]c23[2]c01[1]c23[1]c01[3]c23[3] # asm 1: vtrn.32 <c01=reg128#8,<c23=reg128#14 # asm 2: vtrn.32 <c01=q7,<c23=q13 vtrn.32 q7,q13 # qhasm: r0[0,1] += x01[0] unsigned* y0[0]; r0[2,3] += x01[1] unsigned* y0[1] # asm 1: vmlal.u32 <r0=reg128#4,<x01=reg128#9%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r0=q3,<x01=d16,<y0=d0 vmlal.u32 q3,d16,d0 # qhasm: r3[0,1] = c23[2]<<18; r3[2,3] = c23[3]<<18 # asm 1: vshll.u32 >r3=reg128#6,<c23=reg128#14%top,#18 # asm 2: vshll.u32 >r3=q5,<c23=d27,#18 vshll.u32 q5,d27,#18 # qhasm: r0[0,1] += x01[2] unsigned* 5y34[2]; r0[2,3] += x01[3] unsigned* 5y34[3] # asm 1: vmlal.u32 <r0=reg128#4,<x01=reg128#9%top,<5y34=reg128#13%top # asm 2: vmlal.u32 <r0=q3,<x01=d17,<5y34=d25 vmlal.u32 q3,d17,d25 # qhasm: r3[0,1] += x01[0] unsigned* y34[0]; r3[2,3] += x01[1] unsigned* y34[1] # asm 1: vmlal.u32 <r3=reg128#6,<x01=reg128#9%bot,<y34=reg128#3%bot # asm 2: vmlal.u32 <r3=q5,<x01=d16,<y34=d4 vmlal.u32 q5,d16,d4 # qhasm: r3[0,1] += x01[2] unsigned* y12[2]; r3[2,3] += x01[3] unsigned* y12[3] # asm 1: vmlal.u32 <r3=reg128#6,<x01=reg128#9%top,<y12=reg128#2%top # asm 2: vmlal.u32 <r3=q5,<x01=d17,<y12=d3 vmlal.u32 q5,d17,d3 # qhasm: r3[0,1] += x23[0] unsigned* y12[0]; r3[2,3] += x23[1] unsigned* y12[1] # asm 1: vmlal.u32 <r3=reg128#6,<x23=reg128#10%bot,<y12=reg128#2%bot # asm 2: vmlal.u32 <r3=q5,<x23=d18,<y12=d2 vmlal.u32 q5,d18,d2 # qhasm: r3[0,1] += x23[2] unsigned* y0[0]; r3[2,3] += x23[3] unsigned* y0[1] # asm 1: vmlal.u32 <r3=reg128#6,<x23=reg128#10%top,<y0=reg128#1%bot # asm 2: vmlal.u32 <r3=q5,<x23=d19,<y0=d0 vmlal.u32 q5,d19,d0 # qhasm: r1[0,1] = c23[0]<<6; r1[2,3] = c23[1]<<6 # asm 1: vshll.u32 >r1=reg128#14,<c23=reg128#14%bot,#6 # asm 2: vshll.u32 >r1=q13,<c23=d26,#6 vshll.u32 q13,d26,#6 # qhasm: r3[0,1] += x4[0] unsigned* 5y34[2]; r3[2,3] += x4[1] unsigned* 5y34[3] # asm 1: vmlal.u32 <r3=reg128#6,<x4=reg128#11%bot,<5y34=reg128#13%top # asm 2: vmlal.u32 <r3=q5,<x4=d20,<5y34=d25 vmlal.u32 q5,d20,d25 # qhasm: r1[0,1] += x01[0] unsigned* y12[0]; r1[2,3] += x01[1] unsigned* y12[1] # asm 1: vmlal.u32 <r1=reg128#14,<x01=reg128#9%bot,<y12=reg128#2%bot # asm 2: vmlal.u32 <r1=q13,<x01=d16,<y12=d2 vmlal.u32 q13,d16,d2 # qhasm: r1[0,1] += x01[2] unsigned* y0[0]; r1[2,3] += x01[3] unsigned* y0[1] # asm 1: vmlal.u32 <r1=reg128#14,<x01=reg128#9%top,<y0=reg128#1%bot # asm 2: vmlal.u32 <r1=q13,<x01=d17,<y0=d0 vmlal.u32 q13,d17,d0 # qhasm: r1[0,1] += x23[0] unsigned* 5y34[2]; r1[2,3] += x23[1] unsigned* 5y34[3] # asm 1: vmlal.u32 <r1=reg128#14,<x23=reg128#10%bot,<5y34=reg128#13%top # asm 2: vmlal.u32 <r1=q13,<x23=d18,<5y34=d25 vmlal.u32 q13,d18,d25 # qhasm: r1[0,1] += x23[2] unsigned* 5y34[0]; r1[2,3] += x23[3] unsigned* 5y34[1] # asm 1: vmlal.u32 <r1=reg128#14,<x23=reg128#10%top,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r1=q13,<x23=d19,<5y34=d24 vmlal.u32 q13,d19,d24 # qhasm: r2[0,1] = c01[2]<<12; r2[2,3] = c01[3]<<12 # asm 1: vshll.u32 >r2=reg128#8,<c01=reg128#8%top,#12 # asm 2: vshll.u32 >r2=q7,<c01=d15,#12 vshll.u32 q7,d15,#12 # qhasm: r1[0,1] += x4[0] unsigned* 5y12[2]; r1[2,3] += x4[1] unsigned* 5y12[3] # asm 1: vmlal.u32 <r1=reg128#14,<x4=reg128#11%bot,<5y12=reg128#12%top # asm 2: vmlal.u32 <r1=q13,<x4=d20,<5y12=d23 vmlal.u32 q13,d20,d23 # qhasm: r2[0,1] += x01[0] unsigned* y12[2]; r2[2,3] += x01[1] unsigned* y12[3] # asm 1: vmlal.u32 <r2=reg128#8,<x01=reg128#9%bot,<y12=reg128#2%top # asm 2: vmlal.u32 <r2=q7,<x01=d16,<y12=d3 vmlal.u32 q7,d16,d3 # qhasm: r2[0,1] += x01[2] unsigned* y12[0]; r2[2,3] += x01[3] unsigned* y12[1] # asm 1: vmlal.u32 <r2=reg128#8,<x01=reg128#9%top,<y12=reg128#2%bot # asm 2: vmlal.u32 <r2=q7,<x01=d17,<y12=d2 vmlal.u32 q7,d17,d2 # qhasm: r2[0,1] += x23[0] unsigned* y0[0]; r2[2,3] += x23[1] unsigned* y0[1] # asm 1: vmlal.u32 <r2=reg128#8,<x23=reg128#10%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r2=q7,<x23=d18,<y0=d0 vmlal.u32 q7,d18,d0 # qhasm: r2[0,1] += x23[2] unsigned* 5y34[2]; r2[2,3] += x23[3] unsigned* 5y34[3] # asm 1: vmlal.u32 <r2=reg128#8,<x23=reg128#10%top,<5y34=reg128#13%top # asm 2: vmlal.u32 <r2=q7,<x23=d19,<5y34=d25 vmlal.u32 q7,d19,d25 # qhasm: r2[0,1] += x4[0] unsigned* 5y34[0]; r2[2,3] += x4[1] unsigned* 5y34[1] # asm 1: vmlal.u32 <r2=reg128#8,<x4=reg128#11%bot,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r2=q7,<x4=d20,<5y34=d24 vmlal.u32 q7,d20,d24 # qhasm: 2x t1 = r0 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#9,<r0=reg128#4,#26 # asm 2: vshr.u64 >t1=q8,<r0=q3,#26 vshr.u64 q8,q3,#26 # qhasm: r0 &= mask # asm 1: vand >r0=reg128#4,<r0=reg128#4,<mask=reg128#7 # asm 2: vand >r0=q3,<r0=q3,<mask=q6 vand q3,q3,q6 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#9,<r1=reg128#14,<t1=reg128#9 # asm 2: vadd.i64 >r1=q8,<r1=q13,<t1=q8 vadd.i64 q8,q13,q8 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#10,<r3=reg128#6,#26 # asm 2: vshr.u64 >t4=q9,<r3=q5,#26 vshr.u64 q9,q5,#26 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#6,<r3=reg128#6,<mask=reg128#7 # asm 2: vand >r3=q5,<r3=q5,<mask=q6 vand q5,q5,q6 # qhasm: 2x r4 += t4 # asm 1: vadd.i64 >r4=reg128#5,<r4=reg128#5,<t4=reg128#10 # asm 2: vadd.i64 >r4=q4,<r4=q4,<t4=q9 vadd.i64 q4,q4,q9 # qhasm: 2x t2 = r1 unsigned>> 26 # asm 1: vshr.u64 >t2=reg128#10,<r1=reg128#9,#26 # asm 2: vshr.u64 >t2=q9,<r1=q8,#26 vshr.u64 q9,q8,#26 # qhasm: r1 &= mask # asm 1: vand >r1=reg128#11,<r1=reg128#9,<mask=reg128#7 # asm 2: vand >r1=q10,<r1=q8,<mask=q6 vand q10,q8,q6 # qhasm: 2x t0 = r4 unsigned>> 26 # asm 1: vshr.u64 >t0=reg128#9,<r4=reg128#5,#26 # asm 2: vshr.u64 >t0=q8,<r4=q4,#26 vshr.u64 q8,q4,#26 # qhasm: 2x r2 += t2 # asm 1: vadd.i64 >r2=reg128#8,<r2=reg128#8,<t2=reg128#10 # asm 2: vadd.i64 >r2=q7,<r2=q7,<t2=q9 vadd.i64 q7,q7,q9 # qhasm: r4 &= mask # asm 1: vand >r4=reg128#5,<r4=reg128#5,<mask=reg128#7 # asm 2: vand >r4=q4,<r4=q4,<mask=q6 vand q4,q4,q6 # qhasm: 2x r0 += t0 # asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#9 # asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q8 vadd.i64 q3,q3,q8 # qhasm: 2x t0 <<= 2 # asm 1: vshl.i64 >t0=reg128#9,<t0=reg128#9,#2 # asm 2: vshl.i64 >t0=q8,<t0=q8,#2 vshl.i64 q8,q8,#2 # qhasm: 2x t3 = r2 unsigned>> 26 # asm 1: vshr.u64 >t3=reg128#14,<r2=reg128#8,#26 # asm 2: vshr.u64 >t3=q13,<r2=q7,#26 vshr.u64 q13,q7,#26 # qhasm: 2x r0 += t0 # asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#9 # asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q8 vadd.i64 q3,q3,q8 # qhasm: x23 = r2 & mask # asm 1: vand >x23=reg128#10,<r2=reg128#8,<mask=reg128#7 # asm 2: vand >x23=q9,<r2=q7,<mask=q6 vand q9,q7,q6 # qhasm: 2x r3 += t3 # asm 1: vadd.i64 >r3=reg128#6,<r3=reg128#6,<t3=reg128#14 # asm 2: vadd.i64 >r3=q5,<r3=q5,<t3=q13 vadd.i64 q5,q5,q13 # qhasm: 2x t1 = r0 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#8,<r0=reg128#4,#26 # asm 2: vshr.u64 >t1=q7,<r0=q3,#26 vshr.u64 q7,q3,#26 # qhasm: x01 = r0 & mask # asm 1: vand >x01=reg128#9,<r0=reg128#4,<mask=reg128#7 # asm 2: vand >x01=q8,<r0=q3,<mask=q6 vand q8,q3,q6 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#11,<t1=reg128#8 # asm 2: vadd.i64 >r1=q3,<r1=q10,<t1=q7 vadd.i64 q3,q10,q7 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#8,<r3=reg128#6,#26 # asm 2: vshr.u64 >t4=q7,<r3=q5,#26 vshr.u64 q7,q5,#26 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#6,<r3=reg128#6,<mask=reg128#7 # asm 2: vand >r3=q5,<r3=q5,<mask=q6 vand q5,q5,q6 # qhasm: 2x x4 = r4 + t4 # asm 1: vadd.i64 >x4=reg128#11,<r4=reg128#5,<t4=reg128#8 # asm 2: vadd.i64 >x4=q10,<r4=q4,<t4=q7 vadd.i64 q10,q4,q7 # qhasm: len -= 32 # asm 1: sub >len=int32#4,<len=int32#4,#32 # asm 2: sub >len=r3,<len=r3,#32 sub r3,r3,#32 # qhasm: x01 = x01[0,2,1,3] # asm 1: vtrn.32 <x01=reg128#9%bot,<x01=reg128#9%top # asm 2: vtrn.32 <x01=d16,<x01=d17 vtrn.32 d16,d17 # qhasm: x23 = x23[0,2,1,3] # asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top # asm 2: vtrn.32 <x23=d18,<x23=d19 vtrn.32 d18,d19 # qhasm: r1 = r1[0,2,1,3] # asm 1: vtrn.32 <r1=reg128#4%bot,<r1=reg128#4%top # asm 2: vtrn.32 <r1=d6,<r1=d7 vtrn.32 d6,d7 # qhasm: r3 = r3[0,2,1,3] # asm 1: vtrn.32 <r3=reg128#6%bot,<r3=reg128#6%top # asm 2: vtrn.32 <r3=d10,<r3=d11 vtrn.32 d10,d11 # qhasm: x4 = x4[0,2,1,3] # asm 1: vtrn.32 <x4=reg128#11%bot,<x4=reg128#11%top # asm 2: vtrn.32 <x4=d20,<x4=d21 vtrn.32 d20,d21 # qhasm: x01 = x01[0,1] r1[0,1] # asm 1: vext.32 <x01=reg128#9%top,<r1=reg128#4%bot,<r1=reg128#4%bot,#0 # asm 2: vext.32 <x01=d17,<r1=d6,<r1=d6,#0 vext.32 d17,d6,d6,#0 # qhasm: x23 = x23[0,1] r3[0,1] # asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#6%bot,<r3=reg128#6%bot,#0 # asm 2: vext.32 <x23=d19,<r3=d10,<r3=d10,#0 vext.32 d19,d10,d10,#0 # qhasm: unsigned>? len - 32 # asm 1: cmp <len=int32#4,#32 # asm 2: cmp <len=r3,#32 cmp r3,#32 # qhasm: goto mainloop if unsigned> bhi ._mainloop # qhasm: end: ._end: # qhasm: mem128[input_0] = x01;input_0+=16 # asm 1: vst1.8 {<x01=reg128#9%bot-<x01=reg128#9%top},[<input_0=int32#1]! # asm 2: vst1.8 {<x01=d16-<x01=d17},[<input_0=r0]! vst1.8 {d16-d17},[r0]! # qhasm: mem128[input_0] = x23;input_0+=16 # asm 1: vst1.8 {<x23=reg128#10%bot-<x23=reg128#10%top},[<input_0=int32#1]! # asm 2: vst1.8 {<x23=d18-<x23=d19},[<input_0=r0]! vst1.8 {d18-d19},[r0]! # qhasm: mem64[input_0] = x4[0] # asm 1: vst1.8 <x4=reg128#11%bot,[<input_0=int32#1] # asm 2: vst1.8 <x4=d20,[<input_0=r0] vst1.8 d20,[r0] # qhasm: len = len # asm 1: mov >len=int32#1,<len=int32#4 # asm 2: mov >len=r0,<len=r3 mov r0,r3 # qhasm: qpopreturn len mov sp,r12 vpop {q4,q5,q6,q7} bx lr # qhasm: int32 input_0 # qhasm: int32 input_1 # qhasm: int32 input_2 # qhasm: int32 input_3 # qhasm: stack32 input_4 # qhasm: stack32 input_5 # qhasm: stack32 input_6 # qhasm: stack32 input_7 # qhasm: int32 caller_r4 # qhasm: int32 caller_r5 # qhasm: int32 caller_r6 # qhasm: int32 caller_r7 # qhasm: int32 caller_r8 # qhasm: int32 caller_r9 # qhasm: int32 caller_r10 # qhasm: int32 caller_r11 # qhasm: int32 caller_r12 # qhasm: int32 caller_r14 # qhasm: reg128 caller_q4 # qhasm: reg128 caller_q5 # qhasm: reg128 caller_q6 # qhasm: reg128 caller_q7 # qhasm: reg128 r0 # qhasm: reg128 r1 # qhasm: reg128 r2 # qhasm: reg128 r3 # qhasm: reg128 r4 # qhasm: reg128 x01 # qhasm: reg128 x23 # qhasm: reg128 x4 # qhasm: reg128 y01 # qhasm: reg128 y23 # qhasm: reg128 y4 # qhasm: reg128 _5y01 # qhasm: reg128 _5y23 # qhasm: reg128 _5y4 # qhasm: reg128 c01 # qhasm: reg128 c23 # qhasm: reg128 c4 # qhasm: reg128 t0 # qhasm: reg128 t1 # qhasm: reg128 t2 # qhasm: reg128 t3 # qhasm: reg128 t4 # qhasm: reg128 mask # qhasm: enter crypto_onetimeauth_poly1305_neon2_addmulmod .align 2 .global openssl_poly1305_neon2_addmulmod .hidden openssl_poly1305_neon2_addmulmod .type openssl_poly1305_neon2_addmulmod STT_FUNC openssl_poly1305_neon2_addmulmod: sub sp,sp,#0 # qhasm: 2x mask = 0xffffffff # asm 1: vmov.i64 >mask=reg128#1,#0xffffffff # asm 2: vmov.i64 >mask=q0,#0xffffffff vmov.i64 q0,#0xffffffff # qhasm: y01 aligned= mem128[input_2];input_2+=16 # asm 1: vld1.8 {>y01=reg128#2%bot->y01=reg128#2%top},[<input_2=int32#3,: 128]! # asm 2: vld1.8 {>y01=d2->y01=d3},[<input_2=r2,: 128]! vld1.8 {d2-d3},[r2,: 128]! # qhasm: 4x _5y01 = y01 << 2 # asm 1: vshl.i32 >_5y01=reg128#3,<y01=reg128#2,#2 # asm 2: vshl.i32 >_5y01=q2,<y01=q1,#2 vshl.i32 q2,q1,#2 # qhasm: y23 aligned= mem128[input_2];input_2+=16 # asm 1: vld1.8 {>y23=reg128#4%bot->y23=reg128#4%top},[<input_2=int32#3,: 128]! # asm 2: vld1.8 {>y23=d6->y23=d7},[<input_2=r2,: 128]! vld1.8 {d6-d7},[r2,: 128]! # qhasm: 4x _5y23 = y23 << 2 # asm 1: vshl.i32 >_5y23=reg128#9,<y23=reg128#4,#2 # asm 2: vshl.i32 >_5y23=q8,<y23=q3,#2 vshl.i32 q8,q3,#2 # qhasm: y4 aligned= mem64[input_2]y4[1] # asm 1: vld1.8 {<y4=reg128#10%bot},[<input_2=int32#3,: 64] # asm 2: vld1.8 {<y4=d18},[<input_2=r2,: 64] vld1.8 {d18},[r2,: 64] # qhasm: 4x _5y4 = y4 << 2 # asm 1: vshl.i32 >_5y4=reg128#11,<y4=reg128#10,#2 # asm 2: vshl.i32 >_5y4=q10,<y4=q9,#2 vshl.i32 q10,q9,#2 # qhasm: x01 aligned= mem128[input_1];input_1+=16 # asm 1: vld1.8 {>x01=reg128#12%bot->x01=reg128#12%top},[<input_1=int32#2,: 128]! # asm 2: vld1.8 {>x01=d22->x01=d23},[<input_1=r1,: 128]! vld1.8 {d22-d23},[r1,: 128]! # qhasm: 4x _5y01 += y01 # asm 1: vadd.i32 >_5y01=reg128#3,<_5y01=reg128#3,<y01=reg128#2 # asm 2: vadd.i32 >_5y01=q2,<_5y01=q2,<y01=q1 vadd.i32 q2,q2,q1 # qhasm: x23 aligned= mem128[input_1];input_1+=16 # asm 1: vld1.8 {>x23=reg128#13%bot->x23=reg128#13%top},[<input_1=int32#2,: 128]! # asm 2: vld1.8 {>x23=d24->x23=d25},[<input_1=r1,: 128]! vld1.8 {d24-d25},[r1,: 128]! # qhasm: 4x _5y23 += y23 # asm 1: vadd.i32 >_5y23=reg128#9,<_5y23=reg128#9,<y23=reg128#4 # asm 2: vadd.i32 >_5y23=q8,<_5y23=q8,<y23=q3 vadd.i32 q8,q8,q3 # qhasm: 4x _5y4 += y4 # asm 1: vadd.i32 >_5y4=reg128#11,<_5y4=reg128#11,<y4=reg128#10 # asm 2: vadd.i32 >_5y4=q10,<_5y4=q10,<y4=q9 vadd.i32 q10,q10,q9 # qhasm: c01 aligned= mem128[input_3];input_3+=16 # asm 1: vld1.8 {>c01=reg128#14%bot->c01=reg128#14%top},[<input_3=int32#4,: 128]! # asm 2: vld1.8 {>c01=d26->c01=d27},[<input_3=r3,: 128]! vld1.8 {d26-d27},[r3,: 128]! # qhasm: 4x x01 += c01 # asm 1: vadd.i32 >x01=reg128#12,<x01=reg128#12,<c01=reg128#14 # asm 2: vadd.i32 >x01=q11,<x01=q11,<c01=q13 vadd.i32 q11,q11,q13 # qhasm: c23 aligned= mem128[input_3];input_3+=16 # asm 1: vld1.8 {>c23=reg128#14%bot->c23=reg128#14%top},[<input_3=int32#4,: 128]! # asm 2: vld1.8 {>c23=d26->c23=d27},[<input_3=r3,: 128]! vld1.8 {d26-d27},[r3,: 128]! # qhasm: 4x x23 += c23 # asm 1: vadd.i32 >x23=reg128#13,<x23=reg128#13,<c23=reg128#14 # asm 2: vadd.i32 >x23=q12,<x23=q12,<c23=q13 vadd.i32 q12,q12,q13 # qhasm: x4 aligned= mem64[input_1]x4[1] # asm 1: vld1.8 {<x4=reg128#14%bot},[<input_1=int32#2,: 64] # asm 2: vld1.8 {<x4=d26},[<input_1=r1,: 64] vld1.8 {d26},[r1,: 64] # qhasm: 2x mask unsigned>>=6 # asm 1: vshr.u64 >mask=reg128#1,<mask=reg128#1,#6 # asm 2: vshr.u64 >mask=q0,<mask=q0,#6 vshr.u64 q0,q0,#6 # qhasm: c4 aligned= mem64[input_3]c4[1] # asm 1: vld1.8 {<c4=reg128#15%bot},[<input_3=int32#4,: 64] # asm 2: vld1.8 {<c4=d28},[<input_3=r3,: 64] vld1.8 {d28},[r3,: 64] # qhasm: 4x x4 += c4 # asm 1: vadd.i32 >x4=reg128#14,<x4=reg128#14,<c4=reg128#15 # asm 2: vadd.i32 >x4=q13,<x4=q13,<c4=q14 vadd.i32 q13,q13,q14 # qhasm: r0[0,1] = x01[0] unsigned* y01[0]; r0[2,3] = x01[1] unsigned* y01[1] # asm 1: vmull.u32 >r0=reg128#15,<x01=reg128#12%bot,<y01=reg128#2%bot # asm 2: vmull.u32 >r0=q14,<x01=d22,<y01=d2 vmull.u32 q14,d22,d2 # qhasm: r0[0,1] += x01[2] unsigned* _5y4[0]; r0[2,3] += x01[3] unsigned* _5y4[1] # asm 1: vmlal.u32 <r0=reg128#15,<x01=reg128#12%top,<_5y4=reg128#11%bot # asm 2: vmlal.u32 <r0=q14,<x01=d23,<_5y4=d20 vmlal.u32 q14,d23,d20 # qhasm: r0[0,1] += x23[0] unsigned* _5y23[2]; r0[2,3] += x23[1] unsigned* _5y23[3] # asm 1: vmlal.u32 <r0=reg128#15,<x23=reg128#13%bot,<_5y23=reg128#9%top # asm 2: vmlal.u32 <r0=q14,<x23=d24,<_5y23=d17 vmlal.u32 q14,d24,d17 # qhasm: r0[0,1] += x23[2] unsigned* _5y23[0]; r0[2,3] += x23[3] unsigned* _5y23[1] # asm 1: vmlal.u32 <r0=reg128#15,<x23=reg128#13%top,<_5y23=reg128#9%bot # asm 2: vmlal.u32 <r0=q14,<x23=d25,<_5y23=d16 vmlal.u32 q14,d25,d16 # qhasm: r0[0,1] += x4[0] unsigned* _5y01[2]; r0[2,3] += x4[1] unsigned* _5y01[3] # asm 1: vmlal.u32 <r0=reg128#15,<x4=reg128#14%bot,<_5y01=reg128#3%top # asm 2: vmlal.u32 <r0=q14,<x4=d26,<_5y01=d5 vmlal.u32 q14,d26,d5 # qhasm: r1[0,1] = x01[0] unsigned* y01[2]; r1[2,3] = x01[1] unsigned* y01[3] # asm 1: vmull.u32 >r1=reg128#3,<x01=reg128#12%bot,<y01=reg128#2%top # asm 2: vmull.u32 >r1=q2,<x01=d22,<y01=d3 vmull.u32 q2,d22,d3 # qhasm: r1[0,1] += x01[2] unsigned* y01[0]; r1[2,3] += x01[3] unsigned* y01[1] # asm 1: vmlal.u32 <r1=reg128#3,<x01=reg128#12%top,<y01=reg128#2%bot # asm 2: vmlal.u32 <r1=q2,<x01=d23,<y01=d2 vmlal.u32 q2,d23,d2 # qhasm: r1[0,1] += x23[0] unsigned* _5y4[0]; r1[2,3] += x23[1] unsigned* _5y4[1] # asm 1: vmlal.u32 <r1=reg128#3,<x23=reg128#13%bot,<_5y4=reg128#11%bot # asm 2: vmlal.u32 <r1=q2,<x23=d24,<_5y4=d20 vmlal.u32 q2,d24,d20 # qhasm: r1[0,1] += x23[2] unsigned* _5y23[2]; r1[2,3] += x23[3] unsigned* _5y23[3] # asm 1: vmlal.u32 <r1=reg128#3,<x23=reg128#13%top,<_5y23=reg128#9%top # asm 2: vmlal.u32 <r1=q2,<x23=d25,<_5y23=d17 vmlal.u32 q2,d25,d17 # qhasm: r1[0,1] += x4[0] unsigned* _5y23[0]; r1[2,3] += x4[1] unsigned* _5y23[1] # asm 1: vmlal.u32 <r1=reg128#3,<x4=reg128#14%bot,<_5y23=reg128#9%bot # asm 2: vmlal.u32 <r1=q2,<x4=d26,<_5y23=d16 vmlal.u32 q2,d26,d16 # qhasm: r2[0,1] = x01[0] unsigned* y23[0]; r2[2,3] = x01[1] unsigned* y23[1] # asm 1: vmull.u32 >r2=reg128#16,<x01=reg128#12%bot,<y23=reg128#4%bot # asm 2: vmull.u32 >r2=q15,<x01=d22,<y23=d6 vmull.u32 q15,d22,d6 # qhasm: r2[0,1] += x01[2] unsigned* y01[2]; r2[2,3] += x01[3] unsigned* y01[3] # asm 1: vmlal.u32 <r2=reg128#16,<x01=reg128#12%top,<y01=reg128#2%top # asm 2: vmlal.u32 <r2=q15,<x01=d23,<y01=d3 vmlal.u32 q15,d23,d3 # qhasm: r2[0,1] += x23[0] unsigned* y01[0]; r2[2,3] += x23[1] unsigned* y01[1] # asm 1: vmlal.u32 <r2=reg128#16,<x23=reg128#13%bot,<y01=reg128#2%bot # asm 2: vmlal.u32 <r2=q15,<x23=d24,<y01=d2 vmlal.u32 q15,d24,d2 # qhasm: r2[0,1] += x23[2] unsigned* _5y4[0]; r2[2,3] += x23[3] unsigned* _5y4[1] # asm 1: vmlal.u32 <r2=reg128#16,<x23=reg128#13%top,<_5y4=reg128#11%bot # asm 2: vmlal.u32 <r2=q15,<x23=d25,<_5y4=d20 vmlal.u32 q15,d25,d20 # qhasm: r2[0,1] += x4[0] unsigned* _5y23[2]; r2[2,3] += x4[1] unsigned* _5y23[3] # asm 1: vmlal.u32 <r2=reg128#16,<x4=reg128#14%bot,<_5y23=reg128#9%top # asm 2: vmlal.u32 <r2=q15,<x4=d26,<_5y23=d17 vmlal.u32 q15,d26,d17 # qhasm: r3[0,1] = x01[0] unsigned* y23[2]; r3[2,3] = x01[1] unsigned* y23[3] # asm 1: vmull.u32 >r3=reg128#9,<x01=reg128#12%bot,<y23=reg128#4%top # asm 2: vmull.u32 >r3=q8,<x01=d22,<y23=d7 vmull.u32 q8,d22,d7 # qhasm: r3[0,1] += x01[2] unsigned* y23[0]; r3[2,3] += x01[3] unsigned* y23[1] # asm 1: vmlal.u32 <r3=reg128#9,<x01=reg128#12%top,<y23=reg128#4%bot # asm 2: vmlal.u32 <r3=q8,<x01=d23,<y23=d6 vmlal.u32 q8,d23,d6 # qhasm: r3[0,1] += x23[0] unsigned* y01[2]; r3[2,3] += x23[1] unsigned* y01[3] # asm 1: vmlal.u32 <r3=reg128#9,<x23=reg128#13%bot,<y01=reg128#2%top # asm 2: vmlal.u32 <r3=q8,<x23=d24,<y01=d3 vmlal.u32 q8,d24,d3 # qhasm: r3[0,1] += x23[2] unsigned* y01[0]; r3[2,3] += x23[3] unsigned* y01[1] # asm 1: vmlal.u32 <r3=reg128#9,<x23=reg128#13%top,<y01=reg128#2%bot # asm 2: vmlal.u32 <r3=q8,<x23=d25,<y01=d2 vmlal.u32 q8,d25,d2 # qhasm: r3[0,1] += x4[0] unsigned* _5y4[0]; r3[2,3] += x4[1] unsigned* _5y4[1] # asm 1: vmlal.u32 <r3=reg128#9,<x4=reg128#14%bot,<_5y4=reg128#11%bot # asm 2: vmlal.u32 <r3=q8,<x4=d26,<_5y4=d20 vmlal.u32 q8,d26,d20 # qhasm: r4[0,1] = x01[0] unsigned* y4[0]; r4[2,3] = x01[1] unsigned* y4[1] # asm 1: vmull.u32 >r4=reg128#10,<x01=reg128#12%bot,<y4=reg128#10%bot # asm 2: vmull.u32 >r4=q9,<x01=d22,<y4=d18 vmull.u32 q9,d22,d18 # qhasm: r4[0,1] += x01[2] unsigned* y23[2]; r4[2,3] += x01[3] unsigned* y23[3] # asm 1: vmlal.u32 <r4=reg128#10,<x01=reg128#12%top,<y23=reg128#4%top # asm 2: vmlal.u32 <r4=q9,<x01=d23,<y23=d7 vmlal.u32 q9,d23,d7 # qhasm: r4[0,1] += x23[0] unsigned* y23[0]; r4[2,3] += x23[1] unsigned* y23[1] # asm 1: vmlal.u32 <r4=reg128#10,<x23=reg128#13%bot,<y23=reg128#4%bot # asm 2: vmlal.u32 <r4=q9,<x23=d24,<y23=d6 vmlal.u32 q9,d24,d6 # qhasm: r4[0,1] += x23[2] unsigned* y01[2]; r4[2,3] += x23[3] unsigned* y01[3] # asm 1: vmlal.u32 <r4=reg128#10,<x23=reg128#13%top,<y01=reg128#2%top # asm 2: vmlal.u32 <r4=q9,<x23=d25,<y01=d3 vmlal.u32 q9,d25,d3 # qhasm: r4[0,1] += x4[0] unsigned* y01[0]; r4[2,3] += x4[1] unsigned* y01[1] # asm 1: vmlal.u32 <r4=reg128#10,<x4=reg128#14%bot,<y01=reg128#2%bot # asm 2: vmlal.u32 <r4=q9,<x4=d26,<y01=d2 vmlal.u32 q9,d26,d2 # qhasm: 2x t1 = r0 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#2,<r0=reg128#15,#26 # asm 2: vshr.u64 >t1=q1,<r0=q14,#26 vshr.u64 q1,q14,#26 # qhasm: r0 &= mask # asm 1: vand >r0=reg128#4,<r0=reg128#15,<mask=reg128#1 # asm 2: vand >r0=q3,<r0=q14,<mask=q0 vand q3,q14,q0 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#2,<r1=reg128#3,<t1=reg128#2 # asm 2: vadd.i64 >r1=q1,<r1=q2,<t1=q1 vadd.i64 q1,q2,q1 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#3,<r3=reg128#9,#26 # asm 2: vshr.u64 >t4=q2,<r3=q8,#26 vshr.u64 q2,q8,#26 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#9,<r3=reg128#9,<mask=reg128#1 # asm 2: vand >r3=q8,<r3=q8,<mask=q0 vand q8,q8,q0 # qhasm: 2x r4 += t4 # asm 1: vadd.i64 >r4=reg128#3,<r4=reg128#10,<t4=reg128#3 # asm 2: vadd.i64 >r4=q2,<r4=q9,<t4=q2 vadd.i64 q2,q9,q2 # qhasm: 2x t2 = r1 unsigned>> 26 # asm 1: vshr.u64 >t2=reg128#10,<r1=reg128#2,#26 # asm 2: vshr.u64 >t2=q9,<r1=q1,#26 vshr.u64 q9,q1,#26 # qhasm: r1 &= mask # asm 1: vand >r1=reg128#2,<r1=reg128#2,<mask=reg128#1 # asm 2: vand >r1=q1,<r1=q1,<mask=q0 vand q1,q1,q0 # qhasm: 2x t0 = r4 unsigned>> 26 # asm 1: vshr.u64 >t0=reg128#11,<r4=reg128#3,#26 # asm 2: vshr.u64 >t0=q10,<r4=q2,#26 vshr.u64 q10,q2,#26 # qhasm: 2x r2 += t2 # asm 1: vadd.i64 >r2=reg128#10,<r2=reg128#16,<t2=reg128#10 # asm 2: vadd.i64 >r2=q9,<r2=q15,<t2=q9 vadd.i64 q9,q15,q9 # qhasm: r4 &= mask # asm 1: vand >r4=reg128#3,<r4=reg128#3,<mask=reg128#1 # asm 2: vand >r4=q2,<r4=q2,<mask=q0 vand q2,q2,q0 # qhasm: 2x r0 += t0 # asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#11 # asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q10 vadd.i64 q3,q3,q10 # qhasm: 2x t0 <<= 2 # asm 1: vshl.i64 >t0=reg128#11,<t0=reg128#11,#2 # asm 2: vshl.i64 >t0=q10,<t0=q10,#2 vshl.i64 q10,q10,#2 # qhasm: 2x t3 = r2 unsigned>> 26 # asm 1: vshr.u64 >t3=reg128#12,<r2=reg128#10,#26 # asm 2: vshr.u64 >t3=q11,<r2=q9,#26 vshr.u64 q11,q9,#26 # qhasm: 2x r0 += t0 # asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#11 # asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q10 vadd.i64 q3,q3,q10 # qhasm: x23 = r2 & mask # asm 1: vand >x23=reg128#10,<r2=reg128#10,<mask=reg128#1 # asm 2: vand >x23=q9,<r2=q9,<mask=q0 vand q9,q9,q0 # qhasm: 2x r3 += t3 # asm 1: vadd.i64 >r3=reg128#9,<r3=reg128#9,<t3=reg128#12 # asm 2: vadd.i64 >r3=q8,<r3=q8,<t3=q11 vadd.i64 q8,q8,q11 # qhasm: 2x t1 = r0 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#11,<r0=reg128#4,#26 # asm 2: vshr.u64 >t1=q10,<r0=q3,#26 vshr.u64 q10,q3,#26 # qhasm: x23 = x23[0,2,1,3] # asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top # asm 2: vtrn.32 <x23=d18,<x23=d19 vtrn.32 d18,d19 # qhasm: x01 = r0 & mask # asm 1: vand >x01=reg128#4,<r0=reg128#4,<mask=reg128#1 # asm 2: vand >x01=q3,<r0=q3,<mask=q0 vand q3,q3,q0 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#2,<r1=reg128#2,<t1=reg128#11 # asm 2: vadd.i64 >r1=q1,<r1=q1,<t1=q10 vadd.i64 q1,q1,q10 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#11,<r3=reg128#9,#26 # asm 2: vshr.u64 >t4=q10,<r3=q8,#26 vshr.u64 q10,q8,#26 # qhasm: x01 = x01[0,2,1,3] # asm 1: vtrn.32 <x01=reg128#4%bot,<x01=reg128#4%top # asm 2: vtrn.32 <x01=d6,<x01=d7 vtrn.32 d6,d7 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#1,<r3=reg128#9,<mask=reg128#1 # asm 2: vand >r3=q0,<r3=q8,<mask=q0 vand q0,q8,q0 # qhasm: r1 = r1[0,2,1,3] # asm 1: vtrn.32 <r1=reg128#2%bot,<r1=reg128#2%top # asm 2: vtrn.32 <r1=d2,<r1=d3 vtrn.32 d2,d3 # qhasm: 2x x4 = r4 + t4 # asm 1: vadd.i64 >x4=reg128#3,<r4=reg128#3,<t4=reg128#11 # asm 2: vadd.i64 >x4=q2,<r4=q2,<t4=q10 vadd.i64 q2,q2,q10 # qhasm: r3 = r3[0,2,1,3] # asm 1: vtrn.32 <r3=reg128#1%bot,<r3=reg128#1%top # asm 2: vtrn.32 <r3=d0,<r3=d1 vtrn.32 d0,d1 # qhasm: x01 = x01[0,1] r1[0,1] # asm 1: vext.32 <x01=reg128#4%top,<r1=reg128#2%bot,<r1=reg128#2%bot,#0 # asm 2: vext.32 <x01=d7,<r1=d2,<r1=d2,#0 vext.32 d7,d2,d2,#0 # qhasm: x23 = x23[0,1] r3[0,1] # asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#1%bot,<r3=reg128#1%bot,#0 # asm 2: vext.32 <x23=d19,<r3=d0,<r3=d0,#0 vext.32 d19,d0,d0,#0 # qhasm: x4 = x4[0,2,1,3] # asm 1: vtrn.32 <x4=reg128#3%bot,<x4=reg128#3%top # asm 2: vtrn.32 <x4=d4,<x4=d5 vtrn.32 d4,d5 # qhasm: mem128[input_0] aligned= x01;input_0+=16 # asm 1: vst1.8 {<x01=reg128#4%bot-<x01=reg128#4%top},[<input_0=int32#1,: 128]! # asm 2: vst1.8 {<x01=d6-<x01=d7},[<input_0=r0,: 128]! vst1.8 {d6-d7},[r0,: 128]! # qhasm: mem128[input_0] aligned= x23;input_0+=16 # asm 1: vst1.8 {<x23=reg128#10%bot-<x23=reg128#10%top},[<input_0=int32#1,: 128]! # asm 2: vst1.8 {<x23=d18-<x23=d19},[<input_0=r0,: 128]! vst1.8 {d18-d19},[r0,: 128]! # qhasm: mem64[input_0] aligned= x4[0] # asm 1: vst1.8 <x4=reg128#3%bot,[<input_0=int32#1,: 64] # asm 2: vst1.8 <x4=d4,[<input_0=r0,: 64] vst1.8 d4,[r0,: 64] # qhasm: return add sp,sp,#0 bx lr #endif /* !OPENSSL_NO_ASM && OPENSSL_ARM && __ELF__ */
j4yc3-mw/Viren	41,612	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/crypto/curve25519/asm/x25519-asm-arm.S	/* Copyright (c) 2015, Google Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. / / This file is taken from crypto_scalarmult/curve25519/neon2/scalarmult.s in * SUPERCOP 20141124 (http://bench.cr.yp.to/supercop.html). That code is public * domain licensed but the standard ISC license is included above to keep * licensing simple. / #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__) .fpu neon .text .align 4 .global x25519_NEON .hidden x25519_NEON .type x25519_NEON, %function x25519_NEON: vpush {q4,q5,q6,q7} mov r12,sp sub sp,sp,#736 and sp,sp,#0xffffffe0 strd r4,[sp,#0] strd r6,[sp,#8] strd r8,[sp,#16] strd r10,[sp,#24] str r12,[sp,#480] str r14,[sp,#484] mov r0,r0 mov r1,r1 mov r2,r2 add r3,sp,#32 ldr r4,=0 ldr r5,=254 vmov.i32 q0,#1 vshr.u64 q1,q0,#7 vshr.u64 q0,q0,#8 vmov.i32 d4,#19 vmov.i32 d5,#38 add r6,sp,#512 vst1.8 {d2-d3},[r6,: 128] add r6,sp,#528 vst1.8 {d0-d1},[r6,: 128] add r6,sp,#544 vst1.8 {d4-d5},[r6,: 128] add r6,r3,#0 vmov.i32 q2,#0 vst1.8 {d4-d5},[r6,: 128]! vst1.8 {d4-d5},[r6,: 128]! vst1.8 d4,[r6,: 64] add r6,r3,#0 ldr r7,=960 sub r7,r7,#2 neg r7,r7 sub r7,r7,r7,LSL #7 str r7,[r6] add r6,sp,#704 vld1.8 {d4-d5},[r1]! vld1.8 {d6-d7},[r1] vst1.8 {d4-d5},[r6,: 128]! vst1.8 {d6-d7},[r6,: 128] sub r1,r6,#16 ldrb r6,[r1] and r6,r6,#248 strb r6,[r1] ldrb r6,[r1,#31] and r6,r6,#127 orr r6,r6,#64 strb r6,[r1,#31] vmov.i64 q2,#0xffffffff vshr.u64 q3,q2,#7 vshr.u64 q2,q2,#6 vld1.8 {d8},[r2] vld1.8 {d10},[r2] add r2,r2,#6 vld1.8 {d12},[r2] vld1.8 {d14},[r2] add r2,r2,#6 vld1.8 {d16},[r2] add r2,r2,#4 vld1.8 {d18},[r2] vld1.8 {d20},[r2] add r2,r2,#6 vld1.8 {d22},[r2] add r2,r2,#2 vld1.8 {d24},[r2] vld1.8 {d26},[r2] vshr.u64 q5,q5,#26 vshr.u64 q6,q6,#3 vshr.u64 q7,q7,#29 vshr.u64 q8,q8,#6 vshr.u64 q10,q10,#25 vshr.u64 q11,q11,#3 vshr.u64 q12,q12,#12 vshr.u64 q13,q13,#38 vand q4,q4,q2 vand q6,q6,q2 vand q8,q8,q2 vand q10,q10,q2 vand q2,q12,q2 vand q5,q5,q3 vand q7,q7,q3 vand q9,q9,q3 vand q11,q11,q3 vand q3,q13,q3 add r2,r3,#48 vadd.i64 q12,q4,q1 vadd.i64 q13,q10,q1 vshr.s64 q12,q12,#26 vshr.s64 q13,q13,#26 vadd.i64 q5,q5,q12 vshl.i64 q12,q12,#26 vadd.i64 q14,q5,q0 vadd.i64 q11,q11,q13 vshl.i64 q13,q13,#26 vadd.i64 q15,q11,q0 vsub.i64 q4,q4,q12 vshr.s64 q12,q14,#25 vsub.i64 q10,q10,q13 vshr.s64 q13,q15,#25 vadd.i64 q6,q6,q12 vshl.i64 q12,q12,#25 vadd.i64 q14,q6,q1 vadd.i64 q2,q2,q13 vsub.i64 q5,q5,q12 vshr.s64 q12,q14,#26 vshl.i64 q13,q13,#25 vadd.i64 q14,q2,q1 vadd.i64 q7,q7,q12 vshl.i64 q12,q12,#26 vadd.i64 q15,q7,q0 vsub.i64 q11,q11,q13 vshr.s64 q13,q14,#26 vsub.i64 q6,q6,q12 vshr.s64 q12,q15,#25 vadd.i64 q3,q3,q13 vshl.i64 q13,q13,#26 vadd.i64 q14,q3,q0 vadd.i64 q8,q8,q12 vshl.i64 q12,q12,#25 vadd.i64 q15,q8,q1 add r2,r2,#8 vsub.i64 q2,q2,q13 vshr.s64 q13,q14,#25 vsub.i64 q7,q7,q12 vshr.s64 q12,q15,#26 vadd.i64 q14,q13,q13 vadd.i64 q9,q9,q12 vtrn.32 d12,d14 vshl.i64 q12,q12,#26 vtrn.32 d13,d15 vadd.i64 q0,q9,q0 vadd.i64 q4,q4,q14 vst1.8 d12,[r2,: 64]! vshl.i64 q6,q13,#4 vsub.i64 q7,q8,q12 vshr.s64 q0,q0,#25 vadd.i64 q4,q4,q6 vadd.i64 q6,q10,q0 vshl.i64 q0,q0,#25 vadd.i64 q8,q6,q1 vadd.i64 q4,q4,q13 vshl.i64 q10,q13,#25 vadd.i64 q1,q4,q1 vsub.i64 q0,q9,q0 vshr.s64 q8,q8,#26 vsub.i64 q3,q3,q10 vtrn.32 d14,d0 vshr.s64 q1,q1,#26 vtrn.32 d15,d1 vadd.i64 q0,q11,q8 vst1.8 d14,[r2,: 64] vshl.i64 q7,q8,#26 vadd.i64 q5,q5,q1 vtrn.32 d4,d6 vshl.i64 q1,q1,#26 vtrn.32 d5,d7 vsub.i64 q3,q6,q7 add r2,r2,#16 vsub.i64 q1,q4,q1 vst1.8 d4,[r2,: 64] vtrn.32 d6,d0 vtrn.32 d7,d1 sub r2,r2,#8 vtrn.32 d2,d10 vtrn.32 d3,d11 vst1.8 d6,[r2,: 64] sub r2,r2,#24 vst1.8 d2,[r2,: 64] add r2,r3,#96 vmov.i32 q0,#0 vmov.i64 d2,#0xff vmov.i64 d3,#0 vshr.u32 q1,q1,#7 vst1.8 {d2-d3},[r2,: 128]! vst1.8 {d0-d1},[r2,: 128]! vst1.8 d0,[r2,: 64] add r2,r3,#144 vmov.i32 q0,#0 vst1.8 {d0-d1},[r2,: 128]! vst1.8 {d0-d1},[r2,: 128]! vst1.8 d0,[r2,: 64] add r2,r3,#240 vmov.i32 q0,#0 vmov.i64 d2,#0xff vmov.i64 d3,#0 vshr.u32 q1,q1,#7 vst1.8 {d2-d3},[r2,: 128]! vst1.8 {d0-d1},[r2,: 128]! vst1.8 d0,[r2,: 64] add r2,r3,#48 add r6,r3,#192 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d4},[r2,: 64] vst1.8 {d0-d1},[r6,: 128]! vst1.8 {d2-d3},[r6,: 128]! vst1.8 d4,[r6,: 64] ._mainloop: mov r2,r5,LSR #3 and r6,r5,#7 ldrb r2,[r1,r2] mov r2,r2,LSR r6 and r2,r2,#1 str r5,[sp,#488] eor r4,r4,r2 str r2,[sp,#492] neg r2,r4 add r4,r3,#96 add r5,r3,#192 add r6,r3,#144 vld1.8 {d8-d9},[r4,: 128]! add r7,r3,#240 vld1.8 {d10-d11},[r5,: 128]! veor q6,q4,q5 vld1.8 {d14-d15},[r6,: 128]! vdup.i32 q8,r2 vld1.8 {d18-d19},[r7,: 128]! veor q10,q7,q9 vld1.8 {d22-d23},[r4,: 128]! vand q6,q6,q8 vld1.8 {d24-d25},[r5,: 128]! vand q10,q10,q8 vld1.8 {d26-d27},[r6,: 128]! veor q4,q4,q6 vld1.8 {d28-d29},[r7,: 128]! veor q5,q5,q6 vld1.8 {d0},[r4,: 64] veor q6,q7,q10 vld1.8 {d2},[r5,: 64] veor q7,q9,q10 vld1.8 {d4},[r6,: 64] veor q9,q11,q12 vld1.8 {d6},[r7,: 64] veor q10,q0,q1 sub r2,r4,#32 vand q9,q9,q8 sub r4,r5,#32 vand q10,q10,q8 sub r5,r6,#32 veor q11,q11,q9 sub r6,r7,#32 veor q0,q0,q10 veor q9,q12,q9 veor q1,q1,q10 veor q10,q13,q14 veor q12,q2,q3 vand q10,q10,q8 vand q8,q12,q8 veor q12,q13,q10 veor q2,q2,q8 veor q10,q14,q10 veor q3,q3,q8 vadd.i32 q8,q4,q6 vsub.i32 q4,q4,q6 vst1.8 {d16-d17},[r2,: 128]! vadd.i32 q6,q11,q12 vst1.8 {d8-d9},[r5,: 128]! vsub.i32 q4,q11,q12 vst1.8 {d12-d13},[r2,: 128]! vadd.i32 q6,q0,q2 vst1.8 {d8-d9},[r5,: 128]! vsub.i32 q0,q0,q2 vst1.8 d12,[r2,: 64] vadd.i32 q2,q5,q7 vst1.8 d0,[r5,: 64] vsub.i32 q0,q5,q7 vst1.8 {d4-d5},[r4,: 128]! vadd.i32 q2,q9,q10 vst1.8 {d0-d1},[r6,: 128]! vsub.i32 q0,q9,q10 vst1.8 {d4-d5},[r4,: 128]! vadd.i32 q2,q1,q3 vst1.8 {d0-d1},[r6,: 128]! vsub.i32 q0,q1,q3 vst1.8 d4,[r4,: 64] vst1.8 d0,[r6,: 64] add r2,sp,#544 add r4,r3,#96 add r5,r3,#144 vld1.8 {d0-d1},[r2,: 128] vld1.8 {d2-d3},[r4,: 128]! vld1.8 {d4-d5},[r5,: 128]! vzip.i32 q1,q2 vld1.8 {d6-d7},[r4,: 128]! vld1.8 {d8-d9},[r5,: 128]! vshl.i32 q5,q1,#1 vzip.i32 q3,q4 vshl.i32 q6,q2,#1 vld1.8 {d14},[r4,: 64] vshl.i32 q8,q3,#1 vld1.8 {d15},[r5,: 64] vshl.i32 q9,q4,#1 vmul.i32 d21,d7,d1 vtrn.32 d14,d15 vmul.i32 q11,q4,q0 vmul.i32 q0,q7,q0 vmull.s32 q12,d2,d2 vmlal.s32 q12,d11,d1 vmlal.s32 q12,d12,d0 vmlal.s32 q12,d13,d23 vmlal.s32 q12,d16,d22 vmlal.s32 q12,d7,d21 vmull.s32 q10,d2,d11 vmlal.s32 q10,d4,d1 vmlal.s32 q10,d13,d0 vmlal.s32 q10,d6,d23 vmlal.s32 q10,d17,d22 vmull.s32 q13,d10,d4 vmlal.s32 q13,d11,d3 vmlal.s32 q13,d13,d1 vmlal.s32 q13,d16,d0 vmlal.s32 q13,d17,d23 vmlal.s32 q13,d8,d22 vmull.s32 q1,d10,d5 vmlal.s32 q1,d11,d4 vmlal.s32 q1,d6,d1 vmlal.s32 q1,d17,d0 vmlal.s32 q1,d8,d23 vmull.s32 q14,d10,d6 vmlal.s32 q14,d11,d13 vmlal.s32 q14,d4,d4 vmlal.s32 q14,d17,d1 vmlal.s32 q14,d18,d0 vmlal.s32 q14,d9,d23 vmull.s32 q11,d10,d7 vmlal.s32 q11,d11,d6 vmlal.s32 q11,d12,d5 vmlal.s32 q11,d8,d1 vmlal.s32 q11,d19,d0 vmull.s32 q15,d10,d8 vmlal.s32 q15,d11,d17 vmlal.s32 q15,d12,d6 vmlal.s32 q15,d13,d5 vmlal.s32 q15,d19,d1 vmlal.s32 q15,d14,d0 vmull.s32 q2,d10,d9 vmlal.s32 q2,d11,d8 vmlal.s32 q2,d12,d7 vmlal.s32 q2,d13,d6 vmlal.s32 q2,d14,d1 vmull.s32 q0,d15,d1 vmlal.s32 q0,d10,d14 vmlal.s32 q0,d11,d19 vmlal.s32 q0,d12,d8 vmlal.s32 q0,d13,d17 vmlal.s32 q0,d6,d6 add r2,sp,#512 vld1.8 {d18-d19},[r2,: 128] vmull.s32 q3,d16,d7 vmlal.s32 q3,d10,d15 vmlal.s32 q3,d11,d14 vmlal.s32 q3,d12,d9 vmlal.s32 q3,d13,d8 add r2,sp,#528 vld1.8 {d8-d9},[r2,: 128] vadd.i64 q5,q12,q9 vadd.i64 q6,q15,q9 vshr.s64 q5,q5,#26 vshr.s64 q6,q6,#26 vadd.i64 q7,q10,q5 vshl.i64 q5,q5,#26 vadd.i64 q8,q7,q4 vadd.i64 q2,q2,q6 vshl.i64 q6,q6,#26 vadd.i64 q10,q2,q4 vsub.i64 q5,q12,q5 vshr.s64 q8,q8,#25 vsub.i64 q6,q15,q6 vshr.s64 q10,q10,#25 vadd.i64 q12,q13,q8 vshl.i64 q8,q8,#25 vadd.i64 q13,q12,q9 vadd.i64 q0,q0,q10 vsub.i64 q7,q7,q8 vshr.s64 q8,q13,#26 vshl.i64 q10,q10,#25 vadd.i64 q13,q0,q9 vadd.i64 q1,q1,q8 vshl.i64 q8,q8,#26 vadd.i64 q15,q1,q4 vsub.i64 q2,q2,q10 vshr.s64 q10,q13,#26 vsub.i64 q8,q12,q8 vshr.s64 q12,q15,#25 vadd.i64 q3,q3,q10 vshl.i64 q10,q10,#26 vadd.i64 q13,q3,q4 vadd.i64 q14,q14,q12 add r2,r3,#288 vshl.i64 q12,q12,#25 add r4,r3,#336 vadd.i64 q15,q14,q9 add r2,r2,#8 vsub.i64 q0,q0,q10 add r4,r4,#8 vshr.s64 q10,q13,#25 vsub.i64 q1,q1,q12 vshr.s64 q12,q15,#26 vadd.i64 q13,q10,q10 vadd.i64 q11,q11,q12 vtrn.32 d16,d2 vshl.i64 q12,q12,#26 vtrn.32 d17,d3 vadd.i64 q1,q11,q4 vadd.i64 q4,q5,q13 vst1.8 d16,[r2,: 64]! vshl.i64 q5,q10,#4 vst1.8 d17,[r4,: 64]! vsub.i64 q8,q14,q12 vshr.s64 q1,q1,#25 vadd.i64 q4,q4,q5 vadd.i64 q5,q6,q1 vshl.i64 q1,q1,#25 vadd.i64 q6,q5,q9 vadd.i64 q4,q4,q10 vshl.i64 q10,q10,#25 vadd.i64 q9,q4,q9 vsub.i64 q1,q11,q1 vshr.s64 q6,q6,#26 vsub.i64 q3,q3,q10 vtrn.32 d16,d2 vshr.s64 q9,q9,#26 vtrn.32 d17,d3 vadd.i64 q1,q2,q6 vst1.8 d16,[r2,: 64] vshl.i64 q2,q6,#26 vst1.8 d17,[r4,: 64] vadd.i64 q6,q7,q9 vtrn.32 d0,d6 vshl.i64 q7,q9,#26 vtrn.32 d1,d7 vsub.i64 q2,q5,q2 add r2,r2,#16 vsub.i64 q3,q4,q7 vst1.8 d0,[r2,: 64] add r4,r4,#16 vst1.8 d1,[r4,: 64] vtrn.32 d4,d2 vtrn.32 d5,d3 sub r2,r2,#8 sub r4,r4,#8 vtrn.32 d6,d12 vtrn.32 d7,d13 vst1.8 d4,[r2,: 64] vst1.8 d5,[r4,: 64] sub r2,r2,#24 sub r4,r4,#24 vst1.8 d6,[r2,: 64] vst1.8 d7,[r4,: 64] add r2,r3,#240 add r4,r3,#96 vld1.8 {d0-d1},[r4,: 128]! vld1.8 {d2-d3},[r4,: 128]! vld1.8 {d4},[r4,: 64] add r4,r3,#144 vld1.8 {d6-d7},[r4,: 128]! vtrn.32 q0,q3 vld1.8 {d8-d9},[r4,: 128]! vshl.i32 q5,q0,#4 vtrn.32 q1,q4 vshl.i32 q6,q3,#4 vadd.i32 q5,q5,q0 vadd.i32 q6,q6,q3 vshl.i32 q7,q1,#4 vld1.8 {d5},[r4,: 64] vshl.i32 q8,q4,#4 vtrn.32 d4,d5 vadd.i32 q7,q7,q1 vadd.i32 q8,q8,q4 vld1.8 {d18-d19},[r2,: 128]! vshl.i32 q10,q2,#4 vld1.8 {d22-d23},[r2,: 128]! vadd.i32 q10,q10,q2 vld1.8 {d24},[r2,: 64] vadd.i32 q5,q5,q0 add r2,r3,#192 vld1.8 {d26-d27},[r2,: 128]! vadd.i32 q6,q6,q3 vld1.8 {d28-d29},[r2,: 128]! vadd.i32 q8,q8,q4 vld1.8 {d25},[r2,: 64] vadd.i32 q10,q10,q2 vtrn.32 q9,q13 vadd.i32 q7,q7,q1 vadd.i32 q5,q5,q0 vtrn.32 q11,q14 vadd.i32 q6,q6,q3 add r2,sp,#560 vadd.i32 q10,q10,q2 vtrn.32 d24,d25 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q6,q13,#1 add r2,sp,#576 vst1.8 {d20-d21},[r2,: 128] vshl.i32 q10,q14,#1 add r2,sp,#592 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q15,q12,#1 vadd.i32 q8,q8,q4 vext.32 d10,d31,d30,#0 vadd.i32 q7,q7,q1 add r2,sp,#608 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q8,d18,d5 vmlal.s32 q8,d26,d4 vmlal.s32 q8,d19,d9 vmlal.s32 q8,d27,d3 vmlal.s32 q8,d22,d8 vmlal.s32 q8,d28,d2 vmlal.s32 q8,d23,d7 vmlal.s32 q8,d29,d1 vmlal.s32 q8,d24,d6 vmlal.s32 q8,d25,d0 add r2,sp,#624 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q2,d18,d4 vmlal.s32 q2,d12,d9 vmlal.s32 q2,d13,d8 vmlal.s32 q2,d19,d3 vmlal.s32 q2,d22,d2 vmlal.s32 q2,d23,d1 vmlal.s32 q2,d24,d0 add r2,sp,#640 vst1.8 {d20-d21},[r2,: 128] vmull.s32 q7,d18,d9 vmlal.s32 q7,d26,d3 vmlal.s32 q7,d19,d8 vmlal.s32 q7,d27,d2 vmlal.s32 q7,d22,d7 vmlal.s32 q7,d28,d1 vmlal.s32 q7,d23,d6 vmlal.s32 q7,d29,d0 add r2,sp,#656 vst1.8 {d10-d11},[r2,: 128] vmull.s32 q5,d18,d3 vmlal.s32 q5,d19,d2 vmlal.s32 q5,d22,d1 vmlal.s32 q5,d23,d0 vmlal.s32 q5,d12,d8 add r2,sp,#672 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q4,d18,d8 vmlal.s32 q4,d26,d2 vmlal.s32 q4,d19,d7 vmlal.s32 q4,d27,d1 vmlal.s32 q4,d22,d6 vmlal.s32 q4,d28,d0 vmull.s32 q8,d18,d7 vmlal.s32 q8,d26,d1 vmlal.s32 q8,d19,d6 vmlal.s32 q8,d27,d0 add r2,sp,#576 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q7,d24,d21 vmlal.s32 q7,d25,d20 vmlal.s32 q4,d23,d21 vmlal.s32 q4,d29,d20 vmlal.s32 q8,d22,d21 vmlal.s32 q8,d28,d20 vmlal.s32 q5,d24,d20 add r2,sp,#576 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q7,d18,d6 vmlal.s32 q7,d26,d0 add r2,sp,#656 vld1.8 {d30-d31},[r2,: 128] vmlal.s32 q2,d30,d21 vmlal.s32 q7,d19,d21 vmlal.s32 q7,d27,d20 add r2,sp,#624 vld1.8 {d26-d27},[r2,: 128] vmlal.s32 q4,d25,d27 vmlal.s32 q8,d29,d27 vmlal.s32 q8,d25,d26 vmlal.s32 q7,d28,d27 vmlal.s32 q7,d29,d26 add r2,sp,#608 vld1.8 {d28-d29},[r2,: 128] vmlal.s32 q4,d24,d29 vmlal.s32 q8,d23,d29 vmlal.s32 q8,d24,d28 vmlal.s32 q7,d22,d29 vmlal.s32 q7,d23,d28 add r2,sp,#608 vst1.8 {d8-d9},[r2,: 128] add r2,sp,#560 vld1.8 {d8-d9},[r2,: 128] vmlal.s32 q7,d24,d9 vmlal.s32 q7,d25,d31 vmull.s32 q1,d18,d2 vmlal.s32 q1,d19,d1 vmlal.s32 q1,d22,d0 vmlal.s32 q1,d24,d27 vmlal.s32 q1,d23,d20 vmlal.s32 q1,d12,d7 vmlal.s32 q1,d13,d6 vmull.s32 q6,d18,d1 vmlal.s32 q6,d19,d0 vmlal.s32 q6,d23,d27 vmlal.s32 q6,d22,d20 vmlal.s32 q6,d24,d26 vmull.s32 q0,d18,d0 vmlal.s32 q0,d22,d27 vmlal.s32 q0,d23,d26 vmlal.s32 q0,d24,d31 vmlal.s32 q0,d19,d20 add r2,sp,#640 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q2,d18,d7 vmlal.s32 q2,d19,d6 vmlal.s32 q5,d18,d6 vmlal.s32 q5,d19,d21 vmlal.s32 q1,d18,d21 vmlal.s32 q1,d19,d29 vmlal.s32 q0,d18,d28 vmlal.s32 q0,d19,d9 vmlal.s32 q6,d18,d29 vmlal.s32 q6,d19,d28 add r2,sp,#592 vld1.8 {d18-d19},[r2,: 128] add r2,sp,#512 vld1.8 {d22-d23},[r2,: 128] vmlal.s32 q5,d19,d7 vmlal.s32 q0,d18,d21 vmlal.s32 q0,d19,d29 vmlal.s32 q6,d18,d6 add r2,sp,#528 vld1.8 {d6-d7},[r2,: 128] vmlal.s32 q6,d19,d21 add r2,sp,#576 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q0,d30,d8 add r2,sp,#672 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q5,d30,d29 add r2,sp,#608 vld1.8 {d24-d25},[r2,: 128] vmlal.s32 q1,d30,d28 vadd.i64 q13,q0,q11 vadd.i64 q14,q5,q11 vmlal.s32 q6,d30,d9 vshr.s64 q4,q13,#26 vshr.s64 q13,q14,#26 vadd.i64 q7,q7,q4 vshl.i64 q4,q4,#26 vadd.i64 q14,q7,q3 vadd.i64 q9,q9,q13 vshl.i64 q13,q13,#26 vadd.i64 q15,q9,q3 vsub.i64 q0,q0,q4 vshr.s64 q4,q14,#25 vsub.i64 q5,q5,q13 vshr.s64 q13,q15,#25 vadd.i64 q6,q6,q4 vshl.i64 q4,q4,#25 vadd.i64 q14,q6,q11 vadd.i64 q2,q2,q13 vsub.i64 q4,q7,q4 vshr.s64 q7,q14,#26 vshl.i64 q13,q13,#25 vadd.i64 q14,q2,q11 vadd.i64 q8,q8,q7 vshl.i64 q7,q7,#26 vadd.i64 q15,q8,q3 vsub.i64 q9,q9,q13 vshr.s64 q13,q14,#26 vsub.i64 q6,q6,q7 vshr.s64 q7,q15,#25 vadd.i64 q10,q10,q13 vshl.i64 q13,q13,#26 vadd.i64 q14,q10,q3 vadd.i64 q1,q1,q7 add r2,r3,#144 vshl.i64 q7,q7,#25 add r4,r3,#96 vadd.i64 q15,q1,q11 add r2,r2,#8 vsub.i64 q2,q2,q13 add r4,r4,#8 vshr.s64 q13,q14,#25 vsub.i64 q7,q8,q7 vshr.s64 q8,q15,#26 vadd.i64 q14,q13,q13 vadd.i64 q12,q12,q8 vtrn.32 d12,d14 vshl.i64 q8,q8,#26 vtrn.32 d13,d15 vadd.i64 q3,q12,q3 vadd.i64 q0,q0,q14 vst1.8 d12,[r2,: 64]! vshl.i64 q7,q13,#4 vst1.8 d13,[r4,: 64]! vsub.i64 q1,q1,q8 vshr.s64 q3,q3,#25 vadd.i64 q0,q0,q7 vadd.i64 q5,q5,q3 vshl.i64 q3,q3,#25 vadd.i64 q6,q5,q11 vadd.i64 q0,q0,q13 vshl.i64 q7,q13,#25 vadd.i64 q8,q0,q11 vsub.i64 q3,q12,q3 vshr.s64 q6,q6,#26 vsub.i64 q7,q10,q7 vtrn.32 d2,d6 vshr.s64 q8,q8,#26 vtrn.32 d3,d7 vadd.i64 q3,q9,q6 vst1.8 d2,[r2,: 64] vshl.i64 q6,q6,#26 vst1.8 d3,[r4,: 64] vadd.i64 q1,q4,q8 vtrn.32 d4,d14 vshl.i64 q4,q8,#26 vtrn.32 d5,d15 vsub.i64 q5,q5,q6 add r2,r2,#16 vsub.i64 q0,q0,q4 vst1.8 d4,[r2,: 64] add r4,r4,#16 vst1.8 d5,[r4,: 64] vtrn.32 d10,d6 vtrn.32 d11,d7 sub r2,r2,#8 sub r4,r4,#8 vtrn.32 d0,d2 vtrn.32 d1,d3 vst1.8 d10,[r2,: 64] vst1.8 d11,[r4,: 64] sub r2,r2,#24 sub r4,r4,#24 vst1.8 d0,[r2,: 64] vst1.8 d1,[r4,: 64] add r2,r3,#288 add r4,r3,#336 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r4,: 128]! vsub.i32 q0,q0,q1 vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d4-d5},[r4,: 128]! vsub.i32 q1,q1,q2 add r5,r3,#240 vld1.8 {d4},[r2,: 64] vld1.8 {d6},[r4,: 64] vsub.i32 q2,q2,q3 vst1.8 {d0-d1},[r5,: 128]! vst1.8 {d2-d3},[r5,: 128]! vst1.8 d4,[r5,: 64] add r2,r3,#144 add r4,r3,#96 add r5,r3,#144 add r6,r3,#192 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r4,: 128]! vsub.i32 q2,q0,q1 vadd.i32 q0,q0,q1 vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d6-d7},[r4,: 128]! vsub.i32 q4,q1,q3 vadd.i32 q1,q1,q3 vld1.8 {d6},[r2,: 64] vld1.8 {d10},[r4,: 64] vsub.i32 q6,q3,q5 vadd.i32 q3,q3,q5 vst1.8 {d4-d5},[r5,: 128]! vst1.8 {d0-d1},[r6,: 128]! vst1.8 {d8-d9},[r5,: 128]! vst1.8 {d2-d3},[r6,: 128]! vst1.8 d12,[r5,: 64] vst1.8 d6,[r6,: 64] add r2,r3,#0 add r4,r3,#240 vld1.8 {d0-d1},[r4,: 128]! vld1.8 {d2-d3},[r4,: 128]! vld1.8 {d4},[r4,: 64] add r4,r3,#336 vld1.8 {d6-d7},[r4,: 128]! vtrn.32 q0,q3 vld1.8 {d8-d9},[r4,: 128]! vshl.i32 q5,q0,#4 vtrn.32 q1,q4 vshl.i32 q6,q3,#4 vadd.i32 q5,q5,q0 vadd.i32 q6,q6,q3 vshl.i32 q7,q1,#4 vld1.8 {d5},[r4,: 64] vshl.i32 q8,q4,#4 vtrn.32 d4,d5 vadd.i32 q7,q7,q1 vadd.i32 q8,q8,q4 vld1.8 {d18-d19},[r2,: 128]! vshl.i32 q10,q2,#4 vld1.8 {d22-d23},[r2,: 128]! vadd.i32 q10,q10,q2 vld1.8 {d24},[r2,: 64] vadd.i32 q5,q5,q0 add r2,r3,#288 vld1.8 {d26-d27},[r2,: 128]! vadd.i32 q6,q6,q3 vld1.8 {d28-d29},[r2,: 128]! vadd.i32 q8,q8,q4 vld1.8 {d25},[r2,: 64] vadd.i32 q10,q10,q2 vtrn.32 q9,q13 vadd.i32 q7,q7,q1 vadd.i32 q5,q5,q0 vtrn.32 q11,q14 vadd.i32 q6,q6,q3 add r2,sp,#560 vadd.i32 q10,q10,q2 vtrn.32 d24,d25 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q6,q13,#1 add r2,sp,#576 vst1.8 {d20-d21},[r2,: 128] vshl.i32 q10,q14,#1 add r2,sp,#592 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q15,q12,#1 vadd.i32 q8,q8,q4 vext.32 d10,d31,d30,#0 vadd.i32 q7,q7,q1 add r2,sp,#608 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q8,d18,d5 vmlal.s32 q8,d26,d4 vmlal.s32 q8,d19,d9 vmlal.s32 q8,d27,d3 vmlal.s32 q8,d22,d8 vmlal.s32 q8,d28,d2 vmlal.s32 q8,d23,d7 vmlal.s32 q8,d29,d1 vmlal.s32 q8,d24,d6 vmlal.s32 q8,d25,d0 add r2,sp,#624 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q2,d18,d4 vmlal.s32 q2,d12,d9 vmlal.s32 q2,d13,d8 vmlal.s32 q2,d19,d3 vmlal.s32 q2,d22,d2 vmlal.s32 q2,d23,d1 vmlal.s32 q2,d24,d0 add r2,sp,#640 vst1.8 {d20-d21},[r2,: 128] vmull.s32 q7,d18,d9 vmlal.s32 q7,d26,d3 vmlal.s32 q7,d19,d8 vmlal.s32 q7,d27,d2 vmlal.s32 q7,d22,d7 vmlal.s32 q7,d28,d1 vmlal.s32 q7,d23,d6 vmlal.s32 q7,d29,d0 add r2,sp,#656 vst1.8 {d10-d11},[r2,: 128] vmull.s32 q5,d18,d3 vmlal.s32 q5,d19,d2 vmlal.s32 q5,d22,d1 vmlal.s32 q5,d23,d0 vmlal.s32 q5,d12,d8 add r2,sp,#672 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q4,d18,d8 vmlal.s32 q4,d26,d2 vmlal.s32 q4,d19,d7 vmlal.s32 q4,d27,d1 vmlal.s32 q4,d22,d6 vmlal.s32 q4,d28,d0 vmull.s32 q8,d18,d7 vmlal.s32 q8,d26,d1 vmlal.s32 q8,d19,d6 vmlal.s32 q8,d27,d0 add r2,sp,#576 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q7,d24,d21 vmlal.s32 q7,d25,d20 vmlal.s32 q4,d23,d21 vmlal.s32 q4,d29,d20 vmlal.s32 q8,d22,d21 vmlal.s32 q8,d28,d20 vmlal.s32 q5,d24,d20 add r2,sp,#576 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q7,d18,d6 vmlal.s32 q7,d26,d0 add r2,sp,#656 vld1.8 {d30-d31},[r2,: 128] vmlal.s32 q2,d30,d21 vmlal.s32 q7,d19,d21 vmlal.s32 q7,d27,d20 add r2,sp,#624 vld1.8 {d26-d27},[r2,: 128] vmlal.s32 q4,d25,d27 vmlal.s32 q8,d29,d27 vmlal.s32 q8,d25,d26 vmlal.s32 q7,d28,d27 vmlal.s32 q7,d29,d26 add r2,sp,#608 vld1.8 {d28-d29},[r2,: 128] vmlal.s32 q4,d24,d29 vmlal.s32 q8,d23,d29 vmlal.s32 q8,d24,d28 vmlal.s32 q7,d22,d29 vmlal.s32 q7,d23,d28 add r2,sp,#608 vst1.8 {d8-d9},[r2,: 128] add r2,sp,#560 vld1.8 {d8-d9},[r2,: 128] vmlal.s32 q7,d24,d9 vmlal.s32 q7,d25,d31 vmull.s32 q1,d18,d2 vmlal.s32 q1,d19,d1 vmlal.s32 q1,d22,d0 vmlal.s32 q1,d24,d27 vmlal.s32 q1,d23,d20 vmlal.s32 q1,d12,d7 vmlal.s32 q1,d13,d6 vmull.s32 q6,d18,d1 vmlal.s32 q6,d19,d0 vmlal.s32 q6,d23,d27 vmlal.s32 q6,d22,d20 vmlal.s32 q6,d24,d26 vmull.s32 q0,d18,d0 vmlal.s32 q0,d22,d27 vmlal.s32 q0,d23,d26 vmlal.s32 q0,d24,d31 vmlal.s32 q0,d19,d20 add r2,sp,#640 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q2,d18,d7 vmlal.s32 q2,d19,d6 vmlal.s32 q5,d18,d6 vmlal.s32 q5,d19,d21 vmlal.s32 q1,d18,d21 vmlal.s32 q1,d19,d29 vmlal.s32 q0,d18,d28 vmlal.s32 q0,d19,d9 vmlal.s32 q6,d18,d29 vmlal.s32 q6,d19,d28 add r2,sp,#592 vld1.8 {d18-d19},[r2,: 128] add r2,sp,#512 vld1.8 {d22-d23},[r2,: 128] vmlal.s32 q5,d19,d7 vmlal.s32 q0,d18,d21 vmlal.s32 q0,d19,d29 vmlal.s32 q6,d18,d6 add r2,sp,#528 vld1.8 {d6-d7},[r2,: 128] vmlal.s32 q6,d19,d21 add r2,sp,#576 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q0,d30,d8 add r2,sp,#672 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q5,d30,d29 add r2,sp,#608 vld1.8 {d24-d25},[r2,: 128] vmlal.s32 q1,d30,d28 vadd.i64 q13,q0,q11 vadd.i64 q14,q5,q11 vmlal.s32 q6,d30,d9 vshr.s64 q4,q13,#26 vshr.s64 q13,q14,#26 vadd.i64 q7,q7,q4 vshl.i64 q4,q4,#26 vadd.i64 q14,q7,q3 vadd.i64 q9,q9,q13 vshl.i64 q13,q13,#26 vadd.i64 q15,q9,q3 vsub.i64 q0,q0,q4 vshr.s64 q4,q14,#25 vsub.i64 q5,q5,q13 vshr.s64 q13,q15,#25 vadd.i64 q6,q6,q4 vshl.i64 q4,q4,#25 vadd.i64 q14,q6,q11 vadd.i64 q2,q2,q13 vsub.i64 q4,q7,q4 vshr.s64 q7,q14,#26 vshl.i64 q13,q13,#25 vadd.i64 q14,q2,q11 vadd.i64 q8,q8,q7 vshl.i64 q7,q7,#26 vadd.i64 q15,q8,q3 vsub.i64 q9,q9,q13 vshr.s64 q13,q14,#26 vsub.i64 q6,q6,q7 vshr.s64 q7,q15,#25 vadd.i64 q10,q10,q13 vshl.i64 q13,q13,#26 vadd.i64 q14,q10,q3 vadd.i64 q1,q1,q7 add r2,r3,#288 vshl.i64 q7,q7,#25 add r4,r3,#96 vadd.i64 q15,q1,q11 add r2,r2,#8 vsub.i64 q2,q2,q13 add r4,r4,#8 vshr.s64 q13,q14,#25 vsub.i64 q7,q8,q7 vshr.s64 q8,q15,#26 vadd.i64 q14,q13,q13 vadd.i64 q12,q12,q8 vtrn.32 d12,d14 vshl.i64 q8,q8,#26 vtrn.32 d13,d15 vadd.i64 q3,q12,q3 vadd.i64 q0,q0,q14 vst1.8 d12,[r2,: 64]! vshl.i64 q7,q13,#4 vst1.8 d13,[r4,: 64]! vsub.i64 q1,q1,q8 vshr.s64 q3,q3,#25 vadd.i64 q0,q0,q7 vadd.i64 q5,q5,q3 vshl.i64 q3,q3,#25 vadd.i64 q6,q5,q11 vadd.i64 q0,q0,q13 vshl.i64 q7,q13,#25 vadd.i64 q8,q0,q11 vsub.i64 q3,q12,q3 vshr.s64 q6,q6,#26 vsub.i64 q7,q10,q7 vtrn.32 d2,d6 vshr.s64 q8,q8,#26 vtrn.32 d3,d7 vadd.i64 q3,q9,q6 vst1.8 d2,[r2,: 64] vshl.i64 q6,q6,#26 vst1.8 d3,[r4,: 64] vadd.i64 q1,q4,q8 vtrn.32 d4,d14 vshl.i64 q4,q8,#26 vtrn.32 d5,d15 vsub.i64 q5,q5,q6 add r2,r2,#16 vsub.i64 q0,q0,q4 vst1.8 d4,[r2,: 64] add r4,r4,#16 vst1.8 d5,[r4,: 64] vtrn.32 d10,d6 vtrn.32 d11,d7 sub r2,r2,#8 sub r4,r4,#8 vtrn.32 d0,d2 vtrn.32 d1,d3 vst1.8 d10,[r2,: 64] vst1.8 d11,[r4,: 64] sub r2,r2,#24 sub r4,r4,#24 vst1.8 d0,[r2,: 64] vst1.8 d1,[r4,: 64] add r2,sp,#544 add r4,r3,#144 add r5,r3,#192 vld1.8 {d0-d1},[r2,: 128] vld1.8 {d2-d3},[r4,: 128]! vld1.8 {d4-d5},[r5,: 128]! vzip.i32 q1,q2 vld1.8 {d6-d7},[r4,: 128]! vld1.8 {d8-d9},[r5,: 128]! vshl.i32 q5,q1,#1 vzip.i32 q3,q4 vshl.i32 q6,q2,#1 vld1.8 {d14},[r4,: 64] vshl.i32 q8,q3,#1 vld1.8 {d15},[r5,: 64] vshl.i32 q9,q4,#1 vmul.i32 d21,d7,d1 vtrn.32 d14,d15 vmul.i32 q11,q4,q0 vmul.i32 q0,q7,q0 vmull.s32 q12,d2,d2 vmlal.s32 q12,d11,d1 vmlal.s32 q12,d12,d0 vmlal.s32 q12,d13,d23 vmlal.s32 q12,d16,d22 vmlal.s32 q12,d7,d21 vmull.s32 q10,d2,d11 vmlal.s32 q10,d4,d1 vmlal.s32 q10,d13,d0 vmlal.s32 q10,d6,d23 vmlal.s32 q10,d17,d22 vmull.s32 q13,d10,d4 vmlal.s32 q13,d11,d3 vmlal.s32 q13,d13,d1 vmlal.s32 q13,d16,d0 vmlal.s32 q13,d17,d23 vmlal.s32 q13,d8,d22 vmull.s32 q1,d10,d5 vmlal.s32 q1,d11,d4 vmlal.s32 q1,d6,d1 vmlal.s32 q1,d17,d0 vmlal.s32 q1,d8,d23 vmull.s32 q14,d10,d6 vmlal.s32 q14,d11,d13 vmlal.s32 q14,d4,d4 vmlal.s32 q14,d17,d1 vmlal.s32 q14,d18,d0 vmlal.s32 q14,d9,d23 vmull.s32 q11,d10,d7 vmlal.s32 q11,d11,d6 vmlal.s32 q11,d12,d5 vmlal.s32 q11,d8,d1 vmlal.s32 q11,d19,d0 vmull.s32 q15,d10,d8 vmlal.s32 q15,d11,d17 vmlal.s32 q15,d12,d6 vmlal.s32 q15,d13,d5 vmlal.s32 q15,d19,d1 vmlal.s32 q15,d14,d0 vmull.s32 q2,d10,d9 vmlal.s32 q2,d11,d8 vmlal.s32 q2,d12,d7 vmlal.s32 q2,d13,d6 vmlal.s32 q2,d14,d1 vmull.s32 q0,d15,d1 vmlal.s32 q0,d10,d14 vmlal.s32 q0,d11,d19 vmlal.s32 q0,d12,d8 vmlal.s32 q0,d13,d17 vmlal.s32 q0,d6,d6 add r2,sp,#512 vld1.8 {d18-d19},[r2,: 128] vmull.s32 q3,d16,d7 vmlal.s32 q3,d10,d15 vmlal.s32 q3,d11,d14 vmlal.s32 q3,d12,d9 vmlal.s32 q3,d13,d8 add r2,sp,#528 vld1.8 {d8-d9},[r2,: 128] vadd.i64 q5,q12,q9 vadd.i64 q6,q15,q9 vshr.s64 q5,q5,#26 vshr.s64 q6,q6,#26 vadd.i64 q7,q10,q5 vshl.i64 q5,q5,#26 vadd.i64 q8,q7,q4 vadd.i64 q2,q2,q6 vshl.i64 q6,q6,#26 vadd.i64 q10,q2,q4 vsub.i64 q5,q12,q5 vshr.s64 q8,q8,#25 vsub.i64 q6,q15,q6 vshr.s64 q10,q10,#25 vadd.i64 q12,q13,q8 vshl.i64 q8,q8,#25 vadd.i64 q13,q12,q9 vadd.i64 q0,q0,q10 vsub.i64 q7,q7,q8 vshr.s64 q8,q13,#26 vshl.i64 q10,q10,#25 vadd.i64 q13,q0,q9 vadd.i64 q1,q1,q8 vshl.i64 q8,q8,#26 vadd.i64 q15,q1,q4 vsub.i64 q2,q2,q10 vshr.s64 q10,q13,#26 vsub.i64 q8,q12,q8 vshr.s64 q12,q15,#25 vadd.i64 q3,q3,q10 vshl.i64 q10,q10,#26 vadd.i64 q13,q3,q4 vadd.i64 q14,q14,q12 add r2,r3,#144 vshl.i64 q12,q12,#25 add r4,r3,#192 vadd.i64 q15,q14,q9 add r2,r2,#8 vsub.i64 q0,q0,q10 add r4,r4,#8 vshr.s64 q10,q13,#25 vsub.i64 q1,q1,q12 vshr.s64 q12,q15,#26 vadd.i64 q13,q10,q10 vadd.i64 q11,q11,q12 vtrn.32 d16,d2 vshl.i64 q12,q12,#26 vtrn.32 d17,d3 vadd.i64 q1,q11,q4 vadd.i64 q4,q5,q13 vst1.8 d16,[r2,: 64]! vshl.i64 q5,q10,#4 vst1.8 d17,[r4,: 64]! vsub.i64 q8,q14,q12 vshr.s64 q1,q1,#25 vadd.i64 q4,q4,q5 vadd.i64 q5,q6,q1 vshl.i64 q1,q1,#25 vadd.i64 q6,q5,q9 vadd.i64 q4,q4,q10 vshl.i64 q10,q10,#25 vadd.i64 q9,q4,q9 vsub.i64 q1,q11,q1 vshr.s64 q6,q6,#26 vsub.i64 q3,q3,q10 vtrn.32 d16,d2 vshr.s64 q9,q9,#26 vtrn.32 d17,d3 vadd.i64 q1,q2,q6 vst1.8 d16,[r2,: 64] vshl.i64 q2,q6,#26 vst1.8 d17,[r4,: 64] vadd.i64 q6,q7,q9 vtrn.32 d0,d6 vshl.i64 q7,q9,#26 vtrn.32 d1,d7 vsub.i64 q2,q5,q2 add r2,r2,#16 vsub.i64 q3,q4,q7 vst1.8 d0,[r2,: 64] add r4,r4,#16 vst1.8 d1,[r4,: 64] vtrn.32 d4,d2 vtrn.32 d5,d3 sub r2,r2,#8 sub r4,r4,#8 vtrn.32 d6,d12 vtrn.32 d7,d13 vst1.8 d4,[r2,: 64] vst1.8 d5,[r4,: 64] sub r2,r2,#24 sub r4,r4,#24 vst1.8 d6,[r2,: 64] vst1.8 d7,[r4,: 64] add r2,r3,#336 add r4,r3,#288 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r4,: 128]! vadd.i32 q0,q0,q1 vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d4-d5},[r4,: 128]! vadd.i32 q1,q1,q2 add r5,r3,#288 vld1.8 {d4},[r2,: 64] vld1.8 {d6},[r4,: 64] vadd.i32 q2,q2,q3 vst1.8 {d0-d1},[r5,: 128]! vst1.8 {d2-d3},[r5,: 128]! vst1.8 d4,[r5,: 64] add r2,r3,#48 add r4,r3,#144 vld1.8 {d0-d1},[r4,: 128]! vld1.8 {d2-d3},[r4,: 128]! vld1.8 {d4},[r4,: 64] add r4,r3,#288 vld1.8 {d6-d7},[r4,: 128]! vtrn.32 q0,q3 vld1.8 {d8-d9},[r4,: 128]! vshl.i32 q5,q0,#4 vtrn.32 q1,q4 vshl.i32 q6,q3,#4 vadd.i32 q5,q5,q0 vadd.i32 q6,q6,q3 vshl.i32 q7,q1,#4 vld1.8 {d5},[r4,: 64] vshl.i32 q8,q4,#4 vtrn.32 d4,d5 vadd.i32 q7,q7,q1 vadd.i32 q8,q8,q4 vld1.8 {d18-d19},[r2,: 128]! vshl.i32 q10,q2,#4 vld1.8 {d22-d23},[r2,: 128]! vadd.i32 q10,q10,q2 vld1.8 {d24},[r2,: 64] vadd.i32 q5,q5,q0 add r2,r3,#240 vld1.8 {d26-d27},[r2,: 128]! vadd.i32 q6,q6,q3 vld1.8 {d28-d29},[r2,: 128]! vadd.i32 q8,q8,q4 vld1.8 {d25},[r2,: 64] vadd.i32 q10,q10,q2 vtrn.32 q9,q13 vadd.i32 q7,q7,q1 vadd.i32 q5,q5,q0 vtrn.32 q11,q14 vadd.i32 q6,q6,q3 add r2,sp,#560 vadd.i32 q10,q10,q2 vtrn.32 d24,d25 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q6,q13,#1 add r2,sp,#576 vst1.8 {d20-d21},[r2,: 128] vshl.i32 q10,q14,#1 add r2,sp,#592 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q15,q12,#1 vadd.i32 q8,q8,q4 vext.32 d10,d31,d30,#0 vadd.i32 q7,q7,q1 add r2,sp,#608 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q8,d18,d5 vmlal.s32 q8,d26,d4 vmlal.s32 q8,d19,d9 vmlal.s32 q8,d27,d3 vmlal.s32 q8,d22,d8 vmlal.s32 q8,d28,d2 vmlal.s32 q8,d23,d7 vmlal.s32 q8,d29,d1 vmlal.s32 q8,d24,d6 vmlal.s32 q8,d25,d0 add r2,sp,#624 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q2,d18,d4 vmlal.s32 q2,d12,d9 vmlal.s32 q2,d13,d8 vmlal.s32 q2,d19,d3 vmlal.s32 q2,d22,d2 vmlal.s32 q2,d23,d1 vmlal.s32 q2,d24,d0 add r2,sp,#640 vst1.8 {d20-d21},[r2,: 128] vmull.s32 q7,d18,d9 vmlal.s32 q7,d26,d3 vmlal.s32 q7,d19,d8 vmlal.s32 q7,d27,d2 vmlal.s32 q7,d22,d7 vmlal.s32 q7,d28,d1 vmlal.s32 q7,d23,d6 vmlal.s32 q7,d29,d0 add r2,sp,#656 vst1.8 {d10-d11},[r2,: 128] vmull.s32 q5,d18,d3 vmlal.s32 q5,d19,d2 vmlal.s32 q5,d22,d1 vmlal.s32 q5,d23,d0 vmlal.s32 q5,d12,d8 add r2,sp,#672 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q4,d18,d8 vmlal.s32 q4,d26,d2 vmlal.s32 q4,d19,d7 vmlal.s32 q4,d27,d1 vmlal.s32 q4,d22,d6 vmlal.s32 q4,d28,d0 vmull.s32 q8,d18,d7 vmlal.s32 q8,d26,d1 vmlal.s32 q8,d19,d6 vmlal.s32 q8,d27,d0 add r2,sp,#576 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q7,d24,d21 vmlal.s32 q7,d25,d20 vmlal.s32 q4,d23,d21 vmlal.s32 q4,d29,d20 vmlal.s32 q8,d22,d21 vmlal.s32 q8,d28,d20 vmlal.s32 q5,d24,d20 add r2,sp,#576 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q7,d18,d6 vmlal.s32 q7,d26,d0 add r2,sp,#656 vld1.8 {d30-d31},[r2,: 128] vmlal.s32 q2,d30,d21 vmlal.s32 q7,d19,d21 vmlal.s32 q7,d27,d20 add r2,sp,#624 vld1.8 {d26-d27},[r2,: 128] vmlal.s32 q4,d25,d27 vmlal.s32 q8,d29,d27 vmlal.s32 q8,d25,d26 vmlal.s32 q7,d28,d27 vmlal.s32 q7,d29,d26 add r2,sp,#608 vld1.8 {d28-d29},[r2,: 128] vmlal.s32 q4,d24,d29 vmlal.s32 q8,d23,d29 vmlal.s32 q8,d24,d28 vmlal.s32 q7,d22,d29 vmlal.s32 q7,d23,d28 add r2,sp,#608 vst1.8 {d8-d9},[r2,: 128] add r2,sp,#560 vld1.8 {d8-d9},[r2,: 128] vmlal.s32 q7,d24,d9 vmlal.s32 q7,d25,d31 vmull.s32 q1,d18,d2 vmlal.s32 q1,d19,d1 vmlal.s32 q1,d22,d0 vmlal.s32 q1,d24,d27 vmlal.s32 q1,d23,d20 vmlal.s32 q1,d12,d7 vmlal.s32 q1,d13,d6 vmull.s32 q6,d18,d1 vmlal.s32 q6,d19,d0 vmlal.s32 q6,d23,d27 vmlal.s32 q6,d22,d20 vmlal.s32 q6,d24,d26 vmull.s32 q0,d18,d0 vmlal.s32 q0,d22,d27 vmlal.s32 q0,d23,d26 vmlal.s32 q0,d24,d31 vmlal.s32 q0,d19,d20 add r2,sp,#640 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q2,d18,d7 vmlal.s32 q2,d19,d6 vmlal.s32 q5,d18,d6 vmlal.s32 q5,d19,d21 vmlal.s32 q1,d18,d21 vmlal.s32 q1,d19,d29 vmlal.s32 q0,d18,d28 vmlal.s32 q0,d19,d9 vmlal.s32 q6,d18,d29 vmlal.s32 q6,d19,d28 add r2,sp,#592 vld1.8 {d18-d19},[r2,: 128] add r2,sp,#512 vld1.8 {d22-d23},[r2,: 128] vmlal.s32 q5,d19,d7 vmlal.s32 q0,d18,d21 vmlal.s32 q0,d19,d29 vmlal.s32 q6,d18,d6 add r2,sp,#528 vld1.8 {d6-d7},[r2,: 128] vmlal.s32 q6,d19,d21 add r2,sp,#576 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q0,d30,d8 add r2,sp,#672 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q5,d30,d29 add r2,sp,#608 vld1.8 {d24-d25},[r2,: 128] vmlal.s32 q1,d30,d28 vadd.i64 q13,q0,q11 vadd.i64 q14,q5,q11 vmlal.s32 q6,d30,d9 vshr.s64 q4,q13,#26 vshr.s64 q13,q14,#26 vadd.i64 q7,q7,q4 vshl.i64 q4,q4,#26 vadd.i64 q14,q7,q3 vadd.i64 q9,q9,q13 vshl.i64 q13,q13,#26 vadd.i64 q15,q9,q3 vsub.i64 q0,q0,q4 vshr.s64 q4,q14,#25 vsub.i64 q5,q5,q13 vshr.s64 q13,q15,#25 vadd.i64 q6,q6,q4 vshl.i64 q4,q4,#25 vadd.i64 q14,q6,q11 vadd.i64 q2,q2,q13 vsub.i64 q4,q7,q4 vshr.s64 q7,q14,#26 vshl.i64 q13,q13,#25 vadd.i64 q14,q2,q11 vadd.i64 q8,q8,q7 vshl.i64 q7,q7,#26 vadd.i64 q15,q8,q3 vsub.i64 q9,q9,q13 vshr.s64 q13,q14,#26 vsub.i64 q6,q6,q7 vshr.s64 q7,q15,#25 vadd.i64 q10,q10,q13 vshl.i64 q13,q13,#26 vadd.i64 q14,q10,q3 vadd.i64 q1,q1,q7 add r2,r3,#240 vshl.i64 q7,q7,#25 add r4,r3,#144 vadd.i64 q15,q1,q11 add r2,r2,#8 vsub.i64 q2,q2,q13 add r4,r4,#8 vshr.s64 q13,q14,#25 vsub.i64 q7,q8,q7 vshr.s64 q8,q15,#26 vadd.i64 q14,q13,q13 vadd.i64 q12,q12,q8 vtrn.32 d12,d14 vshl.i64 q8,q8,#26 vtrn.32 d13,d15 vadd.i64 q3,q12,q3 vadd.i64 q0,q0,q14 vst1.8 d12,[r2,: 64]! vshl.i64 q7,q13,#4 vst1.8 d13,[r4,: 64]! vsub.i64 q1,q1,q8 vshr.s64 q3,q3,#25 vadd.i64 q0,q0,q7 vadd.i64 q5,q5,q3 vshl.i64 q3,q3,#25 vadd.i64 q6,q5,q11 vadd.i64 q0,q0,q13 vshl.i64 q7,q13,#25 vadd.i64 q8,q0,q11 vsub.i64 q3,q12,q3 vshr.s64 q6,q6,#26 vsub.i64 q7,q10,q7 vtrn.32 d2,d6 vshr.s64 q8,q8,#26 vtrn.32 d3,d7 vadd.i64 q3,q9,q6 vst1.8 d2,[r2,: 64] vshl.i64 q6,q6,#26 vst1.8 d3,[r4,: 64] vadd.i64 q1,q4,q8 vtrn.32 d4,d14 vshl.i64 q4,q8,#26 vtrn.32 d5,d15 vsub.i64 q5,q5,q6 add r2,r2,#16 vsub.i64 q0,q0,q4 vst1.8 d4,[r2,: 64] add r4,r4,#16 vst1.8 d5,[r4,: 64] vtrn.32 d10,d6 vtrn.32 d11,d7 sub r2,r2,#8 sub r4,r4,#8 vtrn.32 d0,d2 vtrn.32 d1,d3 vst1.8 d10,[r2,: 64] vst1.8 d11,[r4,: 64] sub r2,r2,#24 sub r4,r4,#24 vst1.8 d0,[r2,: 64] vst1.8 d1,[r4,: 64] ldr r2,[sp,#488] ldr r4,[sp,#492] subs r5,r2,#1 bge ._mainloop add r1,r3,#144 add r2,r3,#336 vld1.8 {d0-d1},[r1,: 128]! vld1.8 {d2-d3},[r1,: 128]! vld1.8 {d4},[r1,: 64] vst1.8 {d0-d1},[r2,: 128]! vst1.8 {d2-d3},[r2,: 128]! vst1.8 d4,[r2,: 64] ldr r1,=0 ._invertloop: add r2,r3,#144 ldr r4,=0 ldr r5,=2 cmp r1,#1 ldreq r5,=1 addeq r2,r3,#336 addeq r4,r3,#48 cmp r1,#2 ldreq r5,=1 addeq r2,r3,#48 cmp r1,#3 ldreq r5,=5 addeq r4,r3,#336 cmp r1,#4 ldreq r5,=10 cmp r1,#5 ldreq r5,=20 cmp r1,#6 ldreq r5,=10 addeq r2,r3,#336 addeq r4,r3,#336 cmp r1,#7 ldreq r5,=50 cmp r1,#8 ldreq r5,=100 cmp r1,#9 ldreq r5,=50 addeq r2,r3,#336 cmp r1,#10 ldreq r5,=5 addeq r2,r3,#48 cmp r1,#11 ldreq r5,=0 addeq r2,r3,#96 add r6,r3,#144 add r7,r3,#288 vld1.8 {d0-d1},[r6,: 128]! vld1.8 {d2-d3},[r6,: 128]! vld1.8 {d4},[r6,: 64] vst1.8 {d0-d1},[r7,: 128]! vst1.8 {d2-d3},[r7,: 128]! vst1.8 d4,[r7,: 64] cmp r5,#0 beq ._skipsquaringloop ._squaringloop: add r6,r3,#288 add r7,r3,#288 add r8,r3,#288 vmov.i32 q0,#19 vmov.i32 q1,#0 vmov.i32 q2,#1 vzip.i32 q1,q2 vld1.8 {d4-d5},[r7,: 128]! vld1.8 {d6-d7},[r7,: 128]! vld1.8 {d9},[r7,: 64] vld1.8 {d10-d11},[r6,: 128]! add r7,sp,#416 vld1.8 {d12-d13},[r6,: 128]! vmul.i32 q7,q2,q0 vld1.8 {d8},[r6,: 64] vext.32 d17,d11,d10,#1 vmul.i32 q9,q3,q0 vext.32 d16,d10,d8,#1 vshl.u32 q10,q5,q1 vext.32 d22,d14,d4,#1 vext.32 d24,d18,d6,#1 vshl.u32 q13,q6,q1 vshl.u32 d28,d8,d2 vrev64.i32 d22,d22 vmul.i32 d1,d9,d1 vrev64.i32 d24,d24 vext.32 d29,d8,d13,#1 vext.32 d0,d1,d9,#1 vrev64.i32 d0,d0 vext.32 d2,d9,d1,#1 vext.32 d23,d15,d5,#1 vmull.s32 q4,d20,d4 vrev64.i32 d23,d23 vmlal.s32 q4,d21,d1 vrev64.i32 d2,d2 vmlal.s32 q4,d26,d19 vext.32 d3,d5,d15,#1 vmlal.s32 q4,d27,d18 vrev64.i32 d3,d3 vmlal.s32 q4,d28,d15 vext.32 d14,d12,d11,#1 vmull.s32 q5,d16,d23 vext.32 d15,d13,d12,#1 vmlal.s32 q5,d17,d4 vst1.8 d8,[r7,: 64]! vmlal.s32 q5,d14,d1 vext.32 d12,d9,d8,#0 vmlal.s32 q5,d15,d19 vmov.i64 d13,#0 vmlal.s32 q5,d29,d18 vext.32 d25,d19,d7,#1 vmlal.s32 q6,d20,d5 vrev64.i32 d25,d25 vmlal.s32 q6,d21,d4 vst1.8 d11,[r7,: 64]! vmlal.s32 q6,d26,d1 vext.32 d9,d10,d10,#0 vmlal.s32 q6,d27,d19 vmov.i64 d8,#0 vmlal.s32 q6,d28,d18 vmlal.s32 q4,d16,d24 vmlal.s32 q4,d17,d5 vmlal.s32 q4,d14,d4 vst1.8 d12,[r7,: 64]! vmlal.s32 q4,d15,d1 vext.32 d10,d13,d12,#0 vmlal.s32 q4,d29,d19 vmov.i64 d11,#0 vmlal.s32 q5,d20,d6 vmlal.s32 q5,d21,d5 vmlal.s32 q5,d26,d4 vext.32 d13,d8,d8,#0 vmlal.s32 q5,d27,d1 vmov.i64 d12,#0 vmlal.s32 q5,d28,d19 vst1.8 d9,[r7,: 64]! vmlal.s32 q6,d16,d25 vmlal.s32 q6,d17,d6 vst1.8 d10,[r7,: 64] vmlal.s32 q6,d14,d5 vext.32 d8,d11,d10,#0 vmlal.s32 q6,d15,d4 vmov.i64 d9,#0 vmlal.s32 q6,d29,d1 vmlal.s32 q4,d20,d7 vmlal.s32 q4,d21,d6 vmlal.s32 q4,d26,d5 vext.32 d11,d12,d12,#0 vmlal.s32 q4,d27,d4 vmov.i64 d10,#0 vmlal.s32 q4,d28,d1 vmlal.s32 q5,d16,d0 sub r6,r7,#32 vmlal.s32 q5,d17,d7 vmlal.s32 q5,d14,d6 vext.32 d30,d9,d8,#0 vmlal.s32 q5,d15,d5 vld1.8 {d31},[r6,: 64]! vmlal.s32 q5,d29,d4 vmlal.s32 q15,d20,d0 vext.32 d0,d6,d18,#1 vmlal.s32 q15,d21,d25 vrev64.i32 d0,d0 vmlal.s32 q15,d26,d24 vext.32 d1,d7,d19,#1 vext.32 d7,d10,d10,#0 vmlal.s32 q15,d27,d23 vrev64.i32 d1,d1 vld1.8 {d6},[r6,: 64] vmlal.s32 q15,d28,d22 vmlal.s32 q3,d16,d4 add r6,r6,#24 vmlal.s32 q3,d17,d2 vext.32 d4,d31,d30,#0 vmov d17,d11 vmlal.s32 q3,d14,d1 vext.32 d11,d13,d13,#0 vext.32 d13,d30,d30,#0 vmlal.s32 q3,d15,d0 vext.32 d1,d8,d8,#0 vmlal.s32 q3,d29,d3 vld1.8 {d5},[r6,: 64] sub r6,r6,#16 vext.32 d10,d6,d6,#0 vmov.i32 q1,#0xffffffff vshl.i64 q4,q1,#25 add r7,sp,#512 vld1.8 {d14-d15},[r7,: 128] vadd.i64 q9,q2,q7 vshl.i64 q1,q1,#26 vshr.s64 q10,q9,#26 vld1.8 {d0},[r6,: 64]! vadd.i64 q5,q5,q10 vand q9,q9,q1 vld1.8 {d16},[r6,: 64]! add r6,sp,#528 vld1.8 {d20-d21},[r6,: 128] vadd.i64 q11,q5,q10 vsub.i64 q2,q2,q9 vshr.s64 q9,q11,#25 vext.32 d12,d5,d4,#0 vand q11,q11,q4 vadd.i64 q0,q0,q9 vmov d19,d7 vadd.i64 q3,q0,q7 vsub.i64 q5,q5,q11 vshr.s64 q11,q3,#26 vext.32 d18,d11,d10,#0 vand q3,q3,q1 vadd.i64 q8,q8,q11 vadd.i64 q11,q8,q10 vsub.i64 q0,q0,q3 vshr.s64 q3,q11,#25 vand q11,q11,q4 vadd.i64 q3,q6,q3 vadd.i64 q6,q3,q7 vsub.i64 q8,q8,q11 vshr.s64 q11,q6,#26 vand q6,q6,q1 vadd.i64 q9,q9,q11 vadd.i64 d25,d19,d21 vsub.i64 q3,q3,q6 vshr.s64 d23,d25,#25 vand q4,q12,q4 vadd.i64 d21,d23,d23 vshl.i64 d25,d23,#4 vadd.i64 d21,d21,d23 vadd.i64 d25,d25,d21 vadd.i64 d4,d4,d25 vzip.i32 q0,q8 vadd.i64 d12,d4,d14 add r6,r8,#8 vst1.8 d0,[r6,: 64] vsub.i64 d19,d19,d9 add r6,r6,#16 vst1.8 d16,[r6,: 64] vshr.s64 d22,d12,#26 vand q0,q6,q1 vadd.i64 d10,d10,d22 vzip.i32 q3,q9 vsub.i64 d4,d4,d0 sub r6,r6,#8 vst1.8 d6,[r6,: 64] add r6,r6,#16 vst1.8 d18,[r6,: 64] vzip.i32 q2,q5 sub r6,r6,#32 vst1.8 d4,[r6,: 64] subs r5,r5,#1 bhi ._squaringloop ._skipsquaringloop: mov r2,r2 add r5,r3,#288 add r6,r3,#144 vmov.i32 q0,#19 vmov.i32 q1,#0 vmov.i32 q2,#1 vzip.i32 q1,q2 vld1.8 {d4-d5},[r5,: 128]! vld1.8 {d6-d7},[r5,: 128]! vld1.8 {d9},[r5,: 64] vld1.8 {d10-d11},[r2,: 128]! add r5,sp,#416 vld1.8 {d12-d13},[r2,: 128]! vmul.i32 q7,q2,q0 vld1.8 {d8},[r2,: 64] vext.32 d17,d11,d10,#1 vmul.i32 q9,q3,q0 vext.32 d16,d10,d8,#1 vshl.u32 q10,q5,q1 vext.32 d22,d14,d4,#1 vext.32 d24,d18,d6,#1 vshl.u32 q13,q6,q1 vshl.u32 d28,d8,d2 vrev64.i32 d22,d22 vmul.i32 d1,d9,d1 vrev64.i32 d24,d24 vext.32 d29,d8,d13,#1 vext.32 d0,d1,d9,#1 vrev64.i32 d0,d0 vext.32 d2,d9,d1,#1 vext.32 d23,d15,d5,#1 vmull.s32 q4,d20,d4 vrev64.i32 d23,d23 vmlal.s32 q4,d21,d1 vrev64.i32 d2,d2 vmlal.s32 q4,d26,d19 vext.32 d3,d5,d15,#1 vmlal.s32 q4,d27,d18 vrev64.i32 d3,d3 vmlal.s32 q4,d28,d15 vext.32 d14,d12,d11,#1 vmull.s32 q5,d16,d23 vext.32 d15,d13,d12,#1 vmlal.s32 q5,d17,d4 vst1.8 d8,[r5,: 64]! vmlal.s32 q5,d14,d1 vext.32 d12,d9,d8,#0 vmlal.s32 q5,d15,d19 vmov.i64 d13,#0 vmlal.s32 q5,d29,d18 vext.32 d25,d19,d7,#1 vmlal.s32 q6,d20,d5 vrev64.i32 d25,d25 vmlal.s32 q6,d21,d4 vst1.8 d11,[r5,: 64]! vmlal.s32 q6,d26,d1 vext.32 d9,d10,d10,#0 vmlal.s32 q6,d27,d19 vmov.i64 d8,#0 vmlal.s32 q6,d28,d18 vmlal.s32 q4,d16,d24 vmlal.s32 q4,d17,d5 vmlal.s32 q4,d14,d4 vst1.8 d12,[r5,: 64]! vmlal.s32 q4,d15,d1 vext.32 d10,d13,d12,#0 vmlal.s32 q4,d29,d19 vmov.i64 d11,#0 vmlal.s32 q5,d20,d6 vmlal.s32 q5,d21,d5 vmlal.s32 q5,d26,d4 vext.32 d13,d8,d8,#0 vmlal.s32 q5,d27,d1 vmov.i64 d12,#0 vmlal.s32 q5,d28,d19 vst1.8 d9,[r5,: 64]! vmlal.s32 q6,d16,d25 vmlal.s32 q6,d17,d6 vst1.8 d10,[r5,: 64] vmlal.s32 q6,d14,d5 vext.32 d8,d11,d10,#0 vmlal.s32 q6,d15,d4 vmov.i64 d9,#0 vmlal.s32 q6,d29,d1 vmlal.s32 q4,d20,d7 vmlal.s32 q4,d21,d6 vmlal.s32 q4,d26,d5 vext.32 d11,d12,d12,#0 vmlal.s32 q4,d27,d4 vmov.i64 d10,#0 vmlal.s32 q4,d28,d1 vmlal.s32 q5,d16,d0 sub r2,r5,#32 vmlal.s32 q5,d17,d7 vmlal.s32 q5,d14,d6 vext.32 d30,d9,d8,#0 vmlal.s32 q5,d15,d5 vld1.8 {d31},[r2,: 64]! vmlal.s32 q5,d29,d4 vmlal.s32 q15,d20,d0 vext.32 d0,d6,d18,#1 vmlal.s32 q15,d21,d25 vrev64.i32 d0,d0 vmlal.s32 q15,d26,d24 vext.32 d1,d7,d19,#1 vext.32 d7,d10,d10,#0 vmlal.s32 q15,d27,d23 vrev64.i32 d1,d1 vld1.8 {d6},[r2,: 64] vmlal.s32 q15,d28,d22 vmlal.s32 q3,d16,d4 add r2,r2,#24 vmlal.s32 q3,d17,d2 vext.32 d4,d31,d30,#0 vmov d17,d11 vmlal.s32 q3,d14,d1 vext.32 d11,d13,d13,#0 vext.32 d13,d30,d30,#0 vmlal.s32 q3,d15,d0 vext.32 d1,d8,d8,#0 vmlal.s32 q3,d29,d3 vld1.8 {d5},[r2,: 64] sub r2,r2,#16 vext.32 d10,d6,d6,#0 vmov.i32 q1,#0xffffffff vshl.i64 q4,q1,#25 add r5,sp,#512 vld1.8 {d14-d15},[r5,: 128] vadd.i64 q9,q2,q7 vshl.i64 q1,q1,#26 vshr.s64 q10,q9,#26 vld1.8 {d0},[r2,: 64]! vadd.i64 q5,q5,q10 vand q9,q9,q1 vld1.8 {d16},[r2,: 64]! add r2,sp,#528 vld1.8 {d20-d21},[r2,: 128] vadd.i64 q11,q5,q10 vsub.i64 q2,q2,q9 vshr.s64 q9,q11,#25 vext.32 d12,d5,d4,#0 vand q11,q11,q4 vadd.i64 q0,q0,q9 vmov d19,d7 vadd.i64 q3,q0,q7 vsub.i64 q5,q5,q11 vshr.s64 q11,q3,#26 vext.32 d18,d11,d10,#0 vand q3,q3,q1 vadd.i64 q8,q8,q11 vadd.i64 q11,q8,q10 vsub.i64 q0,q0,q3 vshr.s64 q3,q11,#25 vand q11,q11,q4 vadd.i64 q3,q6,q3 vadd.i64 q6,q3,q7 vsub.i64 q8,q8,q11 vshr.s64 q11,q6,#26 vand q6,q6,q1 vadd.i64 q9,q9,q11 vadd.i64 d25,d19,d21 vsub.i64 q3,q3,q6 vshr.s64 d23,d25,#25 vand q4,q12,q4 vadd.i64 d21,d23,d23 vshl.i64 d25,d23,#4 vadd.i64 d21,d21,d23 vadd.i64 d25,d25,d21 vadd.i64 d4,d4,d25 vzip.i32 q0,q8 vadd.i64 d12,d4,d14 add r2,r6,#8 vst1.8 d0,[r2,: 64] vsub.i64 d19,d19,d9 add r2,r2,#16 vst1.8 d16,[r2,: 64] vshr.s64 d22,d12,#26 vand q0,q6,q1 vadd.i64 d10,d10,d22 vzip.i32 q3,q9 vsub.i64 d4,d4,d0 sub r2,r2,#8 vst1.8 d6,[r2,: 64] add r2,r2,#16 vst1.8 d18,[r2,: 64] vzip.i32 q2,q5 sub r2,r2,#32 vst1.8 d4,[r2,: 64] cmp r4,#0 beq ._skippostcopy add r2,r3,#144 mov r4,r4 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d4},[r2,: 64] vst1.8 {d0-d1},[r4,: 128]! vst1.8 {d2-d3},[r4,: 128]! vst1.8 d4,[r4,: 64] ._skippostcopy: cmp r1,#1 bne ._skipfinalcopy add r2,r3,#288 add r4,r3,#144 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d4},[r2,: 64] vst1.8 {d0-d1},[r4,: 128]! vst1.8 {d2-d3},[r4,: 128]! vst1.8 d4,[r4,: 64] ._skipfinalcopy: add r1,r1,#1 cmp r1,#12 blo ._invertloop add r1,r3,#144 ldr r2,[r1],#4 ldr r3,[r1],#4 ldr r4,[r1],#4 ldr r5,[r1],#4 ldr r6,[r1],#4 ldr r7,[r1],#4 ldr r8,[r1],#4 ldr r9,[r1],#4 ldr r10,[r1],#4 ldr r1,[r1] add r11,r1,r1,LSL #4 add r11,r11,r1,LSL #1 add r11,r11,#16777216 mov r11,r11,ASR #25 add r11,r11,r2 mov r11,r11,ASR #26 add r11,r11,r3 mov r11,r11,ASR #25 add r11,r11,r4 mov r11,r11,ASR #26 add r11,r11,r5 mov r11,r11,ASR #25 add r11,r11,r6 mov r11,r11,ASR #26 add r11,r11,r7 mov r11,r11,ASR #25 add r11,r11,r8 mov r11,r11,ASR #26 add r11,r11,r9 mov r11,r11,ASR #25 add r11,r11,r10 mov r11,r11,ASR #26 add r11,r11,r1 mov r11,r11,ASR #25 add r2,r2,r11 add r2,r2,r11,LSL #1 add r2,r2,r11,LSL #4 mov r11,r2,ASR #26 add r3,r3,r11 sub r2,r2,r11,LSL #26 mov r11,r3,ASR #25 add r4,r4,r11 sub r3,r3,r11,LSL #25 mov r11,r4,ASR #26 add r5,r5,r11 sub r4,r4,r11,LSL #26 mov r11,r5,ASR #25 add r6,r6,r11 sub r5,r5,r11,LSL #25 mov r11,r6,ASR #26 add r7,r7,r11 sub r6,r6,r11,LSL #26 mov r11,r7,ASR #25 add r8,r8,r11 sub r7,r7,r11,LSL #25 mov r11,r8,ASR #26 add r9,r9,r11 sub r8,r8,r11,LSL #26 mov r11,r9,ASR #25 add r10,r10,r11 sub r9,r9,r11,LSL #25 mov r11,r10,ASR #26 add r1,r1,r11 sub r10,r10,r11,LSL #26 mov r11,r1,ASR #25 sub r1,r1,r11,LSL #25 add r2,r2,r3,LSL #26 mov r3,r3,LSR #6 add r3,r3,r4,LSL #19 mov r4,r4,LSR #13 add r4,r4,r5,LSL #13 mov r5,r5,LSR #19 add r5,r5,r6,LSL #6 add r6,r7,r8,LSL #25 mov r7,r8,LSR #7 add r7,r7,r9,LSL #19 mov r8,r9,LSR #13 add r8,r8,r10,LSL #12 mov r9,r10,LSR #20 add r1,r9,r1,LSL #6 str r2,[r0],#4 str r3,[r0],#4 str r4,[r0],#4 str r5,[r0],#4 str r6,[r0],#4 str r7,[r0],#4 str r8,[r0],#4 str r1,[r0] ldrd r4,[sp,#0] ldrd r6,[sp,#8] ldrd r8,[sp,#16] ldrd r10,[sp,#24] ldr r12,[sp,#480] ldr r14,[sp,#484] ldr r0,=0 mov sp,r12 vpop {q4,q5,q6,q7} bx lr #endif / !OPENSSL_NO_ASM && OPENSSL_ARM && __ELF__ */
j4yc3-mw/Viren	1,571	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/riscv.s	#include "psm.h" .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 / .cfi_startproc li x10, STACK_DIRECTION_DESCENDING jr x1 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: / extern "C" fn() -> mut u8 / .cfi_startproc add x10, x2, x0 jr x1 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(x10: usize, x11: extern "C" fn(usize), x12: mut u8) / .cfi_startproc add x2, x12, x0 jr x11 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(x10: usize, x11: usize, x12: extern "C" fn(usize, usize), x13: mut u8) / .cfi_startproc sw x1, -12(x13) sw x2, -16(x13) addi x2, x13, -16 .cfi_def_cfa x2, 16 .cfi_offset x1, -12 .cfi_offset x2, -16 jalr x1, x12, 0 lw x1, 4(x2) .cfi_restore x1 lw x2, 0(x2) .cfi_restore x2 jr x1 .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
j4yc3-mw/Viren	2,235	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/x86_64.s	#include "psm.h" /* NOTE: sysv64 calling convention is used on all x86_64 targets, including Windows! / .text #if CFG_TARGET_OS_darwin \|\| CFG_TARGET_OS_macos \|\| CFG_TARGET_OS_ios #define GLOBL(fnname) .globl _##fnname #define TYPE(fnname) #define FUNCTION(fnname) _##fnname #define SIZE(fnname,endlabel) #else #define GLOBL(fnname) .globl fnname #define TYPE(fnname) .type fnname,@function #define FUNCTION(fnname) fnname #define SIZE(fnname,endlabel) .size fnname,endlabel-fnname #endif GLOBL(rust_psm_stack_direction) .p2align 4 TYPE(rust_psm_stack_direction) FUNCTION(rust_psm_stack_direction): / extern "sysv64" fn() -> u8 (%al) / .cfi_startproc movb $STACK_DIRECTION_DESCENDING, %al # always descending on x86_64 retq .rust_psm_stack_direction_end: SIZE(rust_psm_stack_direction,.rust_psm_stack_direction_end) .cfi_endproc GLOBL(rust_psm_stack_pointer) .p2align 4 TYPE(rust_psm_stack_pointer) FUNCTION(rust_psm_stack_pointer): / extern "sysv64" fn() -> mut u8 (%rax) / .cfi_startproc leaq 8(%rsp), %rax retq .rust_psm_stack_pointer_end: SIZE(rust_psm_stack_pointer,.rust_psm_stack_pointer_end) .cfi_endproc GLOBL(rust_psm_replace_stack) .p2align 4 TYPE(rust_psm_replace_stack) FUNCTION(rust_psm_replace_stack): /* extern "sysv64" fn(%rdi: usize, %rsi: extern "sysv64" fn(usize), %rdx: mut u8) / .cfi_startproc /* All we gotta do is set the stack pointer to %rdx & tail-call the callback in %rsi. 8-byte offset necessary to account for the "return" pointer that would otherwise be placed onto stack with a regular call / leaq -8(%rdx), %rsp jmpq %rsi .rust_psm_replace_stack_end: SIZE(rust_psm_replace_stack,.rust_psm_replace_stack_end) .cfi_endproc GLOBL(rust_psm_on_stack) .p2align 4 TYPE(rust_psm_on_stack) FUNCTION(rust_psm_on_stack): /* extern "sysv64" fn(%rdi: usize, %rsi: usize, %rdx: extern "sysv64" fn(usize, usize), %rcx: mut u8) / .cfi_startproc pushq %rbp .cfi_def_cfa %rsp, 16 .cfi_offset %rbp, -16 movq %rsp, %rbp .cfi_def_cfa_register %rbp movq %rcx, %rsp callq *%rdx movq %rbp, %rsp popq %rbp .cfi_def_cfa %rsp, 8 retq .rust_psm_on_stack_end: SIZE(rust_psm_on_stack,.rust_psm_on_stack_end) .cfi_endproc
j4yc3-mw/Viren	1,569	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/riscv64.s	#include "psm.h" .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 / .cfi_startproc li x10, STACK_DIRECTION_DESCENDING jr x1 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: / extern "C" fn() -> mut u8 / .cfi_startproc add x10, x2, x0 jr x1 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(x10: usize, x11: extern "C" fn(usize), x12: mut u8) / .cfi_startproc add x2, x12, x0 jr x11 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(x10: usize, x11: usize, x12: extern "C" fn(usize, usize), x13: mut u8) / .cfi_startproc sd x1, -8(x13) sd x2, -16(x13) addi x2, x13, -16 .cfi_def_cfa x2, 16 .cfi_offset x1, -8 .cfi_offset x2, -16 jalr x1, x12, 0 ld x1, 8(x2) .cfi_restore x1 ld x2, 0(x2) .cfi_restore x2 jr x1 .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
j4yc3-mw/Viren	2,080	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/zseries_linux.s	/* Implementation of stack swtiching routines for zSeries LINUX ABI. This ABI is used by the s390x-unknown-linux-gnu target. Documents used: * LINUX for zSeries: ELF Application Binary Interface Supplement (1st ed., 2001) (LNUX-1107-01) * z/Architecture: Principles of Operation (4th ed., 2004) (SA22-7832-03) / #include "psm.h" .text .globl rust_psm_stack_direction .p2align 4 .type rust_psm_stack_direction,@function rust_psm_stack_direction: / extern "C" fn() -> u8 / .cfi_startproc lghi %r2, STACK_DIRECTION_DESCENDING br %r14 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 4 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: / extern "C" fn() -> mut u8 / .cfi_startproc la %r2, 0(%r15) br %r14 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 4 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(r2: usize, r3: extern "C" fn(usize), r4: mut u8) / .cfi_startproc /* FIXME: backtrace does not terminate cleanly for some reason / lay %r15, -160(%r4) / FIXME: this is `basr` instead of `br` purely to remove the backtrace link to the caller / basr %r14, %r3 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 4 .type rust_psm_on_stack,@function rust_psm_on_stack: / extern "C" fn(r2: usize, r3: usize, r4: extern "C" fn(usize, usize), r5: mut u8) / .cfi_startproc stmg %r14, %r15, -16(%r5) lay %r15, -176(%r5) .cfi_def_cfa %r15, 176 .cfi_offset %r14, -16 .cfi_offset %r15, -8 basr %r14, %r4 lmg %r14, %r15, 160(%r15) .cfi_restore %r14 .cfi_restore %r15 br %r14 .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
j4yc3-mw/Viren	2,264	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/x86_windows_gnu.s	/* FIXME: this works locally but not on appveyor??!? / / NOTE: fastcall calling convention used on all x86 targets / .text .def @rust_psm_stack_direction@0 .scl 2 .type 32 .endef .globl @rust_psm_stack_direction@0 .p2align 4 @rust_psm_stack_direction@0: / extern "fastcall" fn() -> u8 (%al) / .cfi_startproc movb $2, %al # always descending on x86_64 retl .cfi_endproc .def @rust_psm_stack_pointer@0 .scl 2 .type 32 .endef .globl @rust_psm_stack_pointer@0 .p2align 4 @rust_psm_stack_pointer@0: / extern "fastcall" fn() -> mut u8 (%rax) / .cfi_startproc leal 4(%esp), %eax retl .cfi_endproc .def @rust_psm_replace_stack@16 .scl 2 .type 32 .endef .globl @rust_psm_replace_stack@16 .p2align 4 @rust_psm_replace_stack@16: /* extern "fastcall" fn(%ecx: usize, %edx: extern "fastcall" fn(usize), 4(%esp): mut u8) / .cfi_startproc /* All we gotta do is set the stack pointer to 4(%esp) & tail-call the callback in %edx Note, that the callee expects the stack to be offset by 4 bytes (normally, a return address would be store there) off the required stack alignment on entry. To offset the stack in such a way we use the `calll` instruction, however it would also be possible to to use plain `jmpl` but would require to adjust the stack manually, which cannot be easily done, because the stack pointer argument is already stored in memory. / movl 8(%esp), %eax mov %eax, %fs:0x08 movl 4(%esp), %esp mov %esp, %fs:0x04 calll %edx ud2 .cfi_endproc .def @rust_psm_on_stack@16 .scl 2 .type 32 .endef .globl @rust_psm_on_stack@16 .p2align 4 @rust_psm_on_stack@16: /* extern "fastcall" fn(%ecx: usize, %edx: usize, 4(%esp): extern "fastcall" fn(usize, usize), 8(%esp): mut u8) / .cfi_startproc pushl %ebp .cfi_def_cfa %esp, 8 .cfi_offset %ebp, -8 pushl %fs:0x04 .cfi_def_cfa %esp, 12 pushl %fs:0x08 .cfi_def_cfa %esp, 16 movl %esp, %ebp .cfi_def_cfa_register %ebp movl 24(%ebp), %eax movl %eax, %fs:0x08 movl 20(%ebp), %esp movl %esp, %fs:0x04 calll *16(%ebp) movl %ebp, %esp popl %fs:0x08 .cfi_def_cfa %esp, 12 popl %fs:0x04 .cfi_def_cfa %esp, 8 popl %ebp .cfi_def_cfa %esp, 4 retl $12 .cfi_endproc
j4yc3-mw/Viren	1,963	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/powerpc32.s	#include "psm.h" /* FIXME: this probably does not cover all ABIs? Tested with sysv only, possibly works for AIX as well? / .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: / extern "C" fn() -> u8 / .cfi_startproc li 3, STACK_DIRECTION_DESCENDING blr .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: / extern "C" fn() -> mut u8 / .cfi_startproc mr 3, 1 blr .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(3: usize, 4: extern "C" fn(usize), 5: mut u8) / .cfi_startproc /* NOTE: perhaps add a debug-assertion for stack alignment? / addi 5, 5, -16 mr 1, 5 mtctr 4 bctr .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: / extern "C" fn(3: usize, 4: usize, 5: extern "C" fn(usize, usize), 6: mut u8) / .cfi_startproc mflr 0 stw 0, -24(6) sub 6, 6, 1 addi 6, 6, -32 stwux 1, 1, 6 .cfi_def_cfa r1, 32 .cfi_offset r1, -32 .cfi_offset lr, -24 mtctr 5 bctrl lwz 0, 8(1) mtlr 0 .cfi_restore lr /* FIXME: after this instruction backtrace breaks until control returns to the caller That being said compiler-generated code has the same issue, so I guess that is fine for now? */ lwz 1, 0(1) .cfi_restore r1 blr .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
j4yc3-mw/Viren	2,218	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/x86_64_windows_gnu.s	.text .def rust_psm_stack_direction .scl 2 .type 32 .endef .globl rust_psm_stack_direction .p2align 4 rust_psm_stack_direction: /* extern "sysv64" fn() -> u8 (%al) / .cfi_startproc movb $2, %al # always descending on x86_64 retq .cfi_endproc .def rust_psm_stack_pointer .scl 2 .type 32 .endef .globl rust_psm_stack_pointer .p2align 4 rust_psm_stack_pointer: / extern "sysv64" fn() -> mut u8 (%rax) / .cfi_startproc leaq 8(%rsp), %rax retq .cfi_endproc .def rust_psm_replace_stack .scl 2 .type 32 .endef .globl rust_psm_replace_stack .p2align 4 rust_psm_replace_stack: /* extern "sysv64" fn(%rdi: usize, %rsi: extern "sysv64" fn(usize), %rdx: mut u8, %rcx: mut u8) / .cfi_startproc / All we gotta do is set the stack pointer to %rdx & tail-call the callback in %rsi. 8-byte offset necessary to account for the "return" pointer that would otherwise be placed onto stack with a regular call / movq %gs:0x08, %rdx movq %gs:0x10, %rcx leaq -8(%rdx), %rsp jmpq %rsi .cfi_endproc .def rust_psm_on_stack .scl 2 .type 32 .endef .globl rust_psm_on_stack .p2align 4 rust_psm_on_stack: /* extern "sysv64" fn(%rdi: usize, %rsi: usize, %rdx: extern "sysv64" fn(usize, usize), %rcx: mut u8, %r8: mut u8) NB: on Windows for SEH to work at all, the pointers in TIB, thread information block, need to be fixed up. Otherwise, it seems that exception mechanism on Windows will not bother looking for exception handlers at all if they happen to fall outside the are specified in TIB. This necessitates an API difference from the usual 4-argument signature used elsewhere. FIXME: this needs a catch-all exception handler that aborts in case somebody unwinds into here. / .cfi_startproc pushq %rbp .cfi_def_cfa %rsp, 16 .cfi_offset %rbp, -16 pushq %gs:0x08 .cfi_def_cfa %rsp, 24 pushq %gs:0x10 .cfi_def_cfa %rsp, 32 movq %rsp, %rbp .cfi_def_cfa_register %rbp movq %rcx, %gs:0x08 movq %r8, %gs:0x10 movq %rcx, %rsp callq %rdx movq %rbp, %rsp popq %gs:0x10 .cfi_def_cfa %rsp, 24 popq %gs:0x08 .cfi_def_cfa %rsp, 16 popq %rbp .cfi_def_cfa %rsp, 8 retq .cfi_endproc
j4yc3-mw/Viren	2,299	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/arm_aapcs.s	#include "psm.h" .text .syntax unified #if CFG_TARGET_OS_darwin \|\| CFG_TARGET_OS_macos \|\| CFG_TARGET_OS_ios #define GLOBL(fnname) .globl _##fnname #define THUMBTYPE(fnname) .thumb_func _##fnname #define FUNCTION(fnname) _##fnname #define THUMBFN .code 16 #define SIZE(fnname,endlabel) #define FNSTART #define CANTUNWIND #define FNEND #else #define GLOBL(fnname) .globl fnname #define THUMBTYPE(fnname) .type fnname,%function #define FUNCTION(fnname) fnname #define THUMBFN .code 16 #define SIZE(fnname,endlabel) .size fnname,endlabel-fnname #define FNSTART .fnstart #define CANTUNWIND .cantunwind #define FNEND .fnend #endif GLOBL(rust_psm_stack_direction) .p2align 2 THUMBTYPE(rust_psm_stack_direction) THUMBFN FUNCTION(rust_psm_stack_direction): /* extern "C" fn() -> u8 / FNSTART .cfi_startproc / movs to support Thumb-1 / movs r0, #STACK_DIRECTION_DESCENDING bx lr .rust_psm_stack_direction_end: SIZE(rust_psm_stack_direction,.rust_psm_stack_direction_end) .cfi_endproc CANTUNWIND FNEND GLOBL(rust_psm_stack_pointer) .p2align 2 THUMBTYPE(rust_psm_stack_pointer) THUMBFN FUNCTION(rust_psm_stack_pointer): / extern "C" fn() -> mut u8 / FNSTART .cfi_startproc mov r0, sp bx lr .rust_psm_stack_pointer_end: SIZE(rust_psm_stack_pointer,.rust_psm_stack_pointer_end) .cfi_endproc CANTUNWIND FNEND GLOBL(rust_psm_replace_stack) .p2align 2 THUMBTYPE(rust_psm_replace_stack) THUMBFN FUNCTION(rust_psm_replace_stack): /* extern "C" fn(r0: usize, r1: extern "C" fn(usize), r2: mut u8) / FNSTART .cfi_startproc /* All we gotta do is set the stack pointer to %rdx & tail-call the callback in %rsi / mov sp, r2 bx r1 .rust_psm_replace_stack_end: SIZE(rust_psm_replace_stack,.rust_psm_replace_stack_end) .cfi_endproc CANTUNWIND FNEND GLOBL(rust_psm_on_stack) .p2align 2 THUMBTYPE(rust_psm_on_stack) THUMBFN FUNCTION(rust_psm_on_stack): / extern "C" fn(r0: usize, r1: usize, r2: extern "C" fn(usize, usize), r3: mut u8) / FNSTART .cfi_startproc push {r4, lr} .cfi_def_cfa_offset 8 mov r4, sp .cfi_def_cfa_register r4 .cfi_offset lr, -4 .cfi_offset r4, -8 mov sp, r3 blx r2 mov sp, r4 .cfi_restore sp pop {r4, pc} .rust_psm_on_stack_end: SIZE(rust_psm_on_stack,.rust_psm_on_stack_end) .cfi_endproc CANTUNWIND FNEND
j4yc3-mw/Viren	1,938	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/sparc64.s	#include "psm.h" .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 / .cfi_startproc jmpl %o7 + 8, %g0 mov STACK_DIRECTION_DESCENDING, %o0 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: / extern "C" fn() -> mut u8 / .cfi_startproc jmpl %o7 + 8, %g0 mov %o6, %o0 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(%i0: usize, %i1: extern "C" fn(usize), %i2: mut u8) / .cfi_startproc .cfi_def_cfa 0, 0 .cfi_return_column 0 jmpl %o1, %g0 /* WEIRD: Why is the LSB set for the %sp and %fp on SPARC?? / add %o2, -0x7ff, %o6 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: / extern "C" fn(%i0: usize, %i1: usize, %i2: extern "C" fn(usize, usize), %i3: mut u8) / .cfi_startproc /* The fact that locals and saved register windows are offset by 2kB is very nasty property of SPARC architecture and ABI. In this case it forces us to slice off 2kB of the stack space outright for no good reason other than adapting to a botched design. */ save %o3, -0x87f, %o6 .cfi_def_cfa_register %fp .cfi_window_save .cfi_register %r15, %r31 mov %i1, %o1 jmpl %i2, %o7 mov %i0, %o0 ret restore .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
j4yc3-mw/Viren	1,722	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/sparc_sysv.s	#include "psm.h" /* FIXME: this ABI has definitely not been verified at all / .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: / extern "C" fn() -> u8 / .cfi_startproc jmpl %o7 + 8, %g0 mov STACK_DIRECTION_DESCENDING, %o0 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: / extern "C" fn() -> mut u8 / .cfi_startproc jmpl %o7 + 8, %g0 mov %o6, %o0 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(%i0: usize, %i1: extern "C" fn(usize), %i2: mut u8) / .cfi_startproc .cfi_def_cfa 0, 0 .cfi_return_column 0 jmpl %o1, %g0 /* WEIRD: Why is the LSB set for the %sp and %fp on SPARC?? / add %o2, -0x3ff, %o6 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: / extern "C" fn(%i0: usize, %i1: usize, %i2: extern "C" fn(usize, usize), %i3: mut u8) / .cfi_startproc save %o3, -0x43f, %o6 .cfi_def_cfa_register %fp .cfi_window_save .cfi_register %r15, %r31 mov %i1, %o1 jmpl %i2, %o7 mov %i0, %o0 ret restore .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
j4yc3-mw/Viren	3,609	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/powerpc64_aix.s	.csect .text[PR],2 .file "powerpc64_aix.s" .globl rust_psm_stack_direction[DS] .globl .rust_psm_stack_direction .align 4 .csect rust_psm_stack_direction[DS],3 .vbyte 8, .rust_psm_stack_direction .vbyte 8, TOC[TC0] .vbyte 8, 0 .csect .text[PR],2 .rust_psm_stack_direction: # extern "C" fn() -> u8 li 3, 2 blr L..rust_psm_stack_direction_end: # Following bytes form the traceback table on AIX. # For specification, see https://www.ibm.com/docs/en/aix/7.2?topic=processor-traceback-tables. # For implementation, see https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp, # `PPCAIXAsmPrinter::emitTracebackTable`. .vbyte 4, 0x00000000 # Traceback table begin, for unwinder to search the table. .byte 0x00 # Version = 0 .byte 0x09 # Language = CPlusPlus, since rust is using C++-like LSDA. .byte 0x20 # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue # +HasTraceBackTableOffset, -IsInternalProcedure # -HasControlledStorage, -IsTOCless # -IsFloatingPointPresent # -IsFloatingPointOperationLogOrAbortEnabled .byte 0x40 # -IsInterruptHandler, +IsFunctionNamePresent, -IsAllocaUsed # OnConditionDirective = 0, -IsCRSaved, -IsLRSaved .byte 0x80 # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 0 .byte 0x00 # -HasExtensionTable, -HasVectorInfo, NumOfGPRsSaved = 0 .byte 0x00 # NumberOfFixedParms = 0 .byte 0x01 # NumberOfFPParms = 0, +HasParmsOnStack .vbyte 4, L..rust_psm_stack_direction_end-.rust_psm_stack_direction #Function size .vbyte 2, 0x0018 # Function name len = 24 .byte "rust_psm_stack_direction" # Function Name .globl rust_psm_stack_pointer[DS] .globl .rust_psm_stack_pointer .align 4 .csect rust_psm_stack_pointer[DS],3 .vbyte 8, .rust_psm_stack_pointer .vbyte 8, TOC[TC0] .vbyte 8, 0 .csect .text[PR],2 .rust_psm_stack_pointer: # extern "C" fn() -> mut u8 mr 3, 1 blr L..rust_psm_stack_pointer_end: .vbyte 4, 0x00000000 .byte 0x00 .byte 0x09 .byte 0x20 .byte 0x40 .byte 0x80 .byte 0x00 .byte 0x00 .byte 0x01 .vbyte 4, L..rust_psm_stack_pointer_end-.rust_psm_stack_pointer .vbyte 2, 0x0016 .byte "rust_psm_stack_pointer" .globl rust_psm_replace_stack[DS] .globl .rust_psm_replace_stack .align 4 .csect rust_psm_replace_stack[DS],3 .vbyte 8, .rust_psm_replace_stack .vbyte 8, TOC[TC0] .vbyte 8, 0 .csect .text[PR],2 .rust_psm_replace_stack: # extern "C" fn(3: usize, 4: extern "C" fn(usize), 5: mut u8) # Load the function pointer and toc pointer from TOC and make the call. ld 2, 8(4) ld 4, 0(4) addi 5, 5, -48 mr 1, 5 mtctr 4 bctr L..rust_psm_replace_stack_end: .vbyte 4, 0x00000000 .byte 0x00 .byte 0x09 .byte 0x20 .byte 0x40 .byte 0x80 .byte 0x00 .byte 0x03 .byte 0x01 .vbyte 4, 0x00000000 # Parameter type = i, i, i .vbyte 4, L..rust_psm_replace_stack_end-.rust_psm_replace_stack .vbyte 2, 0x0016 .byte "rust_psm_replace_stack" .globl rust_psm_on_stack[DS] .globl .rust_psm_on_stack .align 4 .csect rust_psm_on_stack[DS],3 .vbyte 8, .rust_psm_on_stack .vbyte 8, TOC[TC0] .vbyte 8, 0 .csect .text[PR],2 .rust_psm_on_stack: # extern "C" fn(3: usize, 4: usize, 5: extern "C" fn(usize, usize), 6: *mut u8) mflr 0 std 2, -72(6) std 0, -8(6) sub 6, 6, 1 addi 6, 6, -112 stdux 1, 1, 6 ld 2, 8(5) ld 5, 0(5) mtctr 5 bctrl ld 2, 40(1) ld 0, 104(1) mtlr 0 ld 1, 0(1) blr L..rust_psm_on_stack_end: .vbyte 4, 0x00000000 .byte 0x00 .byte 0x09 .byte 0x20 .byte 0x41 .byte 0x80 .byte 0x00 .byte 0x04 .byte 0x01 .vbyte 4, 0x00000000 # Parameter type = i, i, i, i .vbyte 4, L..rust_psm_on_stack_end-.rust_psm_on_stack .vbyte 2, 0x0011 .byte "rust_psm_on_stack" .toc
j4yc3-mw/Viren	2,557	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/x86.s	#include "psm.h" /* NOTE: fastcall calling convention used on all x86 targets / .text #if CFG_TARGET_OS_darwin \|\| CFG_TARGET_OS_macos \|\| CFG_TARGET_OS_ios #define GLOBL(fnname) .globl _##fnname #define TYPE(fnname) #define FUNCTION(fnname) _##fnname #define SIZE(fnname,endlabel) #else #define GLOBL(fnname) .globl fnname #define TYPE(fnname) .type fnname,@function #define FUNCTION(fnname) fnname #define SIZE(fnname,endlabel) .size fnname,endlabel-fnname #endif GLOBL(rust_psm_stack_direction) .p2align 4 TYPE(rust_psm_stack_direction) FUNCTION(rust_psm_stack_direction): / extern "fastcall" fn() -> u8 (%al) / .cfi_startproc movb $STACK_DIRECTION_DESCENDING, %al # always descending on x86_64 retl .rust_psm_stack_direction_end: SIZE(rust_psm_stack_direction,.rust_psm_stack_direction_end) .cfi_endproc GLOBL(rust_psm_stack_pointer) .p2align 4 TYPE(rust_psm_stack_pointer) FUNCTION(rust_psm_stack_pointer): / extern "fastcall" fn() -> mut u8 (%rax) / .cfi_startproc leal 4(%esp), %eax retl .rust_psm_stack_pointer_end: SIZE(rust_psm_stack_pointer,.rust_psm_stack_pointer_end) .cfi_endproc GLOBL(rust_psm_replace_stack) .p2align 4 TYPE(rust_psm_replace_stack) FUNCTION(rust_psm_replace_stack): /* extern "fastcall" fn(%ecx: usize, %edx: extern "fastcall" fn(usize), 4(%esp): mut u8) / .cfi_startproc /* All we gotta do is set the stack pointer to 4(%esp) & tail-call the callback in %edx Note, that the callee expects the stack to be offset by 4 bytes (normally, a return address would be store there) off the required stack alignment on entry. To offset the stack in such a way we use the `calll` instruction, however it would also be possible to to use plain `jmpl` but would require to adjust the stack manually, which cannot be easily done, because the stack pointer argument is already stored in memory. / movl 4(%esp), %esp calll %edx ud2 .rust_psm_replace_stack_end: SIZE(rust_psm_replace_stack,.rust_psm_replace_stack_end) .cfi_endproc GLOBL(rust_psm_on_stack) .p2align 4 TYPE(rust_psm_on_stack) FUNCTION(rust_psm_on_stack): /* extern "fastcall" fn(%ecx: usize, %edx: usize, 4(%esp): extern "fastcall" fn(usize, usize), 8(%esp): mut u8) / .cfi_startproc pushl %ebp .cfi_def_cfa %esp, 8 .cfi_offset %ebp, -8 movl %esp, %ebp .cfi_def_cfa_register %ebp movl 12(%ebp), %esp calll *8(%ebp) movl %ebp, %esp popl %ebp .cfi_def_cfa %esp, 4 retl $8 .rust_psm_on_stack_end: SIZE(rust_psm_on_stack,.rust_psm_on_stack_end) .cfi_endproc
j4yc3-mw/Viren	2,149	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/mips_eabi.s	/* Not only MIPS has 20 different ABIs... nobody tells anybody what specific variant of which ABI is used where. This is an "EABI" implementation based on the following page: http://www.cygwin.com/ml/binutils/2003-06/msg00436.html / #include "psm.h" .set noreorder / we’ll manage the delay slots on our own, thanks! / .text .abicalls .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function .ent rust_psm_stack_direction / extern "C" fn() -> u8 / rust_psm_stack_direction: .cfi_startproc jr $31 addiu $2, $zero, STACK_DIRECTION_DESCENDING .end rust_psm_stack_direction .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function .ent rust_psm_stack_pointer / extern "C" fn() -> mut u8 / rust_psm_stack_pointer: .cfi_startproc jr $31 move $2, $29 .end rust_psm_stack_pointer .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function .ent rust_psm_replace_stack /* extern "C" fn(r4: usize, r5: extern "C" fn(usize), r6: mut u8) / rust_psm_replace_stack: .cfi_startproc move $25, $5 jr $5 move $29, $6 .end rust_psm_replace_stack .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function .ent rust_psm_on_stack /* extern "C" fn(r4: usize, r5: usize, r6: extern "C" fn(usize), r7: mut u8) / rust_psm_on_stack: .cfi_startproc sw $29, -4($7) sw $31, -8($7) .cfi_def_cfa 7, 0 .cfi_offset 31, -8 .cfi_offset 29, -4 move $25, $6 jalr $31, $6 addiu $29, $7, -8 .cfi_def_cfa 29, 8 lw $31, 0($29) .cfi_restore 31 lw $29, 4($29) .cfi_restore 29 jr $31 nop .end rust_psm_on_stack .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
j4yc3-mw/Viren	1,568	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/loongarch64.s	#include "psm.h" .text .globl rust_psm_stack_direction .align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 / .cfi_startproc li.w $r4, STACK_DIRECTION_DESCENDING jr $r1 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: / extern "C" fn() -> mut u8 / .cfi_startproc move $r4, $r3 jr $r1 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(r4: usize, r5: extern "C" fn(usize), r6: mut u8) / .cfi_startproc move $r3, $r6 jr $r5 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(r4: usize, r5: usize, r6: extern "C" fn(usize, usize), r7: mut u8) / .cfi_startproc st.d $r1, $r7, -8 st.d $r3, $r7, -16 addi.d $r3, $r7, -16 .cfi_def_cfa 3, 16 .cfi_offset 1, -8 .cfi_offset 3, -16 jirl $r1, $r6, 0 ld.d $r1, $r3, 8 .cfi_restore 1 ld.d $r3, $r3, 0 .cfi_restore 3 jr $r1 .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
j4yc3-mw/Viren	2,137	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/aarch_aapcs64.s	#include "psm.h" .text #if CFG_TARGET_OS_darwin \|\| CFG_TARGET_OS_macos \|\| CFG_TARGET_OS_ios #define GLOBL(fnname) .globl _##fnname #define TYPE(fnname) #define FUNCTION(fnname) _##fnname #define SIZE(fnname,endlabel) #elif CFG_TARGET_OS_windows #define GLOBL(fnname) .globl fnname #define TYPE(fnname) #define FUNCTION(fnname) fnname #define SIZE(fnname,endlabel) #else #define GLOBL(fnname) .globl fnname #define TYPE(fnname) .type fnname,@function #define FUNCTION(fnname) fnname #define SIZE(fnname,endlabel) .size fnname,endlabel-fnname #endif GLOBL(rust_psm_stack_direction) .p2align 2 TYPE(rust_psm_stack_direction) FUNCTION(rust_psm_stack_direction): /* extern "C" fn() -> u8 / .cfi_startproc orr w0, wzr, #STACK_DIRECTION_DESCENDING ret .rust_psm_stack_direction_end: SIZE(rust_psm_stack_direction,.rust_psm_stack_direction_end) .cfi_endproc GLOBL(rust_psm_stack_pointer) .p2align 2 TYPE(rust_psm_stack_pointer) FUNCTION(rust_psm_stack_pointer): / extern "C" fn() -> mut u8 / .cfi_startproc mov x0, sp ret .rust_psm_stack_pointer_end: SIZE(rust_psm_stack_pointer,.rust_psm_stack_pointer_end) .cfi_endproc GLOBL(rust_psm_replace_stack) .p2align 2 TYPE(rust_psm_replace_stack) FUNCTION(rust_psm_replace_stack): /* extern "C" fn(r0: usize, r1: extern "C" fn(usize), r2: mut u8) / .cfi_startproc /* All we gotta do is set the stack pointer to %rdx & tail-call the callback in %rsi / mov sp, x2 br x1 .rust_psm_replace_stack_end: SIZE(rust_psm_replace_stack,.rust_psm_replace_stack_end) .cfi_endproc GLOBL(rust_psm_on_stack) .p2align 2 TYPE(rust_psm_on_stack) FUNCTION(rust_psm_on_stack): / extern "C" fn(r0: usize, r1: usize, r2: extern "C" fn(usize, usize), r3: mut u8) / .cfi_startproc stp x29, x30, [sp, #-16]! .cfi_def_cfa sp, 16 mov x29, sp .cfi_def_cfa x29, 16 .cfi_offset x29, -16 .cfi_offset x30, -8 mov sp, x3 blr x2 mov sp, x29 .cfi_def_cfa sp, 16 ldp x29, x30, [sp], #16 .cfi_def_cfa sp, 0 .cfi_restore x29 .cfi_restore x30 ret .rust_psm_on_stack_end: SIZE(rust_psm_on_stack,.rust_psm_on_stack_end) .cfi_endproc
j4yc3-mw/Viren	2,144	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/mips64_eabi.s	/* Not only MIPS has 20 different ABIs... nobody tells anybody what specific variant of which ABI is used where. This is an "EABI" implementation based on the following page: http://www.cygwin.com/ml/binutils/2003-06/msg00436.html / #include "psm.h" .set noreorder / we’ll manage the delay slots on our own, thanks! / .text .globl rust_psm_stack_direction .p2align 3 .type rust_psm_stack_direction,@function .ent rust_psm_stack_direction / extern "C" fn() -> u8 / rust_psm_stack_direction: .cfi_startproc jr $31 addiu $2, $zero, STACK_DIRECTION_DESCENDING .end rust_psm_stack_direction .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 3 .type rust_psm_stack_pointer,@function .ent rust_psm_stack_pointer / extern "C" fn() -> mut u8 / rust_psm_stack_pointer: .cfi_startproc jr $31 move $2, $29 .end rust_psm_stack_pointer .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 3 .type rust_psm_replace_stack,@function .ent rust_psm_replace_stack /* extern "C" fn(r4: usize, r5: extern "C" fn(usize), r6: mut u8) / rust_psm_replace_stack: .cfi_startproc move $25, $5 jr $5 move $29, $6 .end rust_psm_replace_stack .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc .globl rust_psm_on_stack .p2align 3 .type rust_psm_on_stack,@function .ent rust_psm_on_stack /* extern "C" fn(r4: usize, r5: usize, r6: extern "C" fn(usize), r7: mut u8) / rust_psm_on_stack: .cfi_startproc sd $29, -8($7) sd $31, -16($7) .cfi_def_cfa 7, 0 .cfi_offset 31, -16 .cfi_offset 29, -8 move $25, $6 jalr $31, $6 daddiu $29, $7, -16 .cfi_def_cfa 29, 16 ld $31, 0($29) .cfi_restore 31 ld $29, 8($29) .cfi_restore 29 jr $31 nop .end rust_psm_on_stack .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
j4yc3-mw/Viren	1,694	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/wasm32.s	#include "psm.h" # Note that this function is not compiled when this package is uploaded to # crates.io, this source is only here as a reference for how the corresponding # wasm32.o was generated. This file can be compiled with: # # cpp psm/src/arch/wasm32.s \| llvm-mc -o psm/src/arch/wasm32.o --arch=wasm32 -filetype=obj # # where you'll want to ensure that `llvm-mc` is from a relatively recent # version of LLVM. .globaltype __stack_pointer, i32 .globl rust_psm_stack_direction .type rust_psm_stack_direction,@function rust_psm_stack_direction: .functype rust_psm_stack_direction () -> (i32) i32.const STACK_DIRECTION_DESCENDING end_function .globl rust_psm_stack_pointer .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: .functype rust_psm_stack_pointer () -> (i32) global.get __stack_pointer end_function .globl rust_psm_on_stack .type rust_psm_on_stack,@function rust_psm_on_stack: .functype rust_psm_on_stack (i32, i32, i32, i32) -> () # get our new stack argument, then save the old stack # pointer into that local local.get 3 global.get __stack_pointer local.set 3 global.set __stack_pointer # Call our indirect function specified local.get 0 local.get 1 local.get 2 call_indirect (i32, i32) -> () # restore the stack pointer before returning local.get 3 global.set __stack_pointer end_function .globl rust_psm_replace_stack .type rust_psm_replace_stack,@function rust_psm_replace_stack: .functype rust_psm_replace_stack (i32, i32, i32) -> () local.get 2 global.set __stack_pointer local.get 0 local.get 1 call_indirect (i32) -> () unreachable end_function
j4yc3-mw/Viren	2,541	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/powerpc64.s	/* Implementation of the AIX-like PowerPC ABI. Seems to be used by the big-endian PowerPC targets. The following references were used during the implementation of this code: https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.alangref/idalangref_rntime_stack.htm https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.alangref/idalangref_reg_use_conv.htm https://www.ibm.com/developerworks/library/l-powasm4/index.html / #include "psm.h" .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: / extern "C" fn() -> u8 / .cfi_startproc li 3, STACK_DIRECTION_DESCENDING blr .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: / extern "C" fn() -> mut u8 / .cfi_startproc mr 3, 1 blr .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(3: usize, 4: extern "C" fn(usize), 5: mut u8) / .cfi_startproc ld 2, 8(4) ld 4, 0(4) /* do not allocate the whole 112-byte sized frame, we know wont be used / addi 5, 5, -48 mr 1, 5 mtctr 4 bctr .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: / extern "C" fn(3: usize, 4: usize, 5: extern "C" fn(usize, usize), 6: mut u8) / .cfi_startproc mflr 0 std 2, -72(6) std 0, -8(6) sub 6, 6, 1 addi 6, 6, -112 stdux 1, 1, 6 .cfi_def_cfa r1, 112 .cfi_offset r1, -112 .cfi_offset r2, -72 .cfi_offset lr, -8 /* load the function pointer from TOC and make the call / ld 2, 8(5) ld 5, 0(5) mtctr 5 bctrl ld 2, 40(1) .cfi_restore r2 ld 0, 104(1) mtlr 0 .cfi_restore lr / FIXME: after this instruction backtrace breaks until control returns to the caller. That being said compiler-generated code has the same issue, so I guess that is fine for now? */ ld 1, 0(1) .cfi_restore r1 blr .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
j4yc3-mw/Viren	2,045	.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/powerpc64_openpower.s	/* Implementation of stack swtiching routines for OpenPOWER 64-bit ELF ABI The specification can be found at http://openpowerfoundation.org/wp-content/uploads/resources/leabi/content/ch_preface.html This ABI is usually used by the ppc64le targets. / #include "psm.h" .text .abiversion 2 .globl rust_psm_stack_direction .p2align 4 .type rust_psm_stack_direction,@function rust_psm_stack_direction: / extern "C" fn() -> u8 / .cfi_startproc li 3, STACK_DIRECTION_DESCENDING blr .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 4 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: / extern "C" fn() -> mut u8 / .cfi_startproc mr 3, 1 blr .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 4 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(3: usize, 4: extern "C" fn(usize), 5: mut u8) / .cfi_startproc addi 5, 5, -32 mtctr 4 mr 12, 4 mr 1, 5 bctr .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 4 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(3: usize, 4: usize, 5: extern "C" fn(usize, usize), 6: mut u8) / .cfi_startproc mflr 0 std 0, -8(6) std 2, -24(6) sub 6, 6, 1 addi 6, 6, -48 stdux 1, 1, 6 .cfi_def_cfa r1, 48 .cfi_offset r1, -48 .cfi_offset r2, -24 .cfi_offset lr, -8 mr 12, 5 mtctr 5 bctrl ld 2, 24(1) .cfi_restore r2 ld 0, 40(1) mtlr 0 .cfi_restore lr /* FIXME: after this instructin backtrace breaks until control returns to the caller */ ld 1, 0(1) blr .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc
jack0682/CSAv1	8,352	third_party/opencv-3.4.17/3rdparty/libpng/arm/filter_neon.S	/* filter_neon.S - NEON optimised filter functions * * Copyright (c) 2018 Cosmin Truta * Copyright (c) 2014,2017 Glenn Randers-Pehrson * Written by Mans Rullgard, 2011. * * This code is released under the libpng license. * For conditions of distribution and use, see the disclaimer * and license in png.h / / This is required to get the symbol renames, which are #defines, and the * definitions (or not) of PNG_ARM_NEON_OPT and PNG_ARM_NEON_IMPLEMENTATION. / #define PNG_VERSION_INFO_ONLY #include "../pngpriv.h" #if (defined(__linux__) \|\| defined(__FreeBSD__)) && defined(__ELF__) .section .note.GNU-stack,"",%progbits / mark stack as non-executable / #endif #ifdef PNG_READ_SUPPORTED / Assembler NEON support - only works for 32-bit ARM (i.e. it does not work for * ARM64). The code in arm/filter_neon_intrinsics.c supports ARM64, however it * only works if -mfpu=neon is specified on the GCC command line. See pngpriv.h * for the logic which sets PNG_USE_ARM_NEON_ASM: / #if PNG_ARM_NEON_IMPLEMENTATION == 2 / hand-coded assembler / #if PNG_ARM_NEON_OPT > 0 #ifdef __ELF__ # define ELF #else # define ELF @ #endif .arch armv7-a .fpu neon .macro func name, export=0 .macro endfunc ELF .size \name, . - \name .endfunc .purgem endfunc .endm .text / Explicitly specifying alignment here because some versions of * GAS don't align code correctly. This is harmless in correctly * written versions of GAS. / .align 2 .if \export .global \name .endif ELF .type \name, STT_FUNC .func \name \name: .endm func png_read_filter_row_sub4_neon, export=1 ldr r3, [r0, #4] @ rowbytes vmov.i8 d3, #0 1: vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] vadd.u8 d0, d3, d4 vadd.u8 d1, d0, d5 vadd.u8 d2, d1, d6 vadd.u8 d3, d2, d7 vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]! subs r3, r3, #16 bgt 1b bx lr endfunc func png_read_filter_row_sub3_neon, export=1 ldr r3, [r0, #4] @ rowbytes vmov.i8 d3, #0 mov r0, r1 mov r2, #3 mov r12, #12 vld1.8 {q11}, [r0], r12 1: vext.8 d5, d22, d23, #3 vadd.u8 d0, d3, d22 vext.8 d6, d22, d23, #6 vadd.u8 d1, d0, d5 vext.8 d7, d23, d23, #1 vld1.8 {q11}, [r0], r12 vst1.32 {d0[0]}, [r1,:32], r2 vadd.u8 d2, d1, d6 vst1.32 {d1[0]}, [r1], r2 vadd.u8 d3, d2, d7 vst1.32 {d2[0]}, [r1], r2 vst1.32 {d3[0]}, [r1], r2 subs r3, r3, #12 bgt 1b bx lr endfunc func png_read_filter_row_up_neon, export=1 ldr r3, [r0, #4] @ rowbytes 1: vld1.8 {q0}, [r1,:128] vld1.8 {q1}, [r2,:128]! vadd.u8 q0, q0, q1 vst1.8 {q0}, [r1,:128]! subs r3, r3, #16 bgt 1b bx lr endfunc func png_read_filter_row_avg4_neon, export=1 ldr r12, [r0, #4] @ rowbytes vmov.i8 d3, #0 1: vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] vld4.32 {d16[],d17[],d18[],d19[]},[r2,:128]! vhadd.u8 d0, d3, d16 vadd.u8 d0, d0, d4 vhadd.u8 d1, d0, d17 vadd.u8 d1, d1, d5 vhadd.u8 d2, d1, d18 vadd.u8 d2, d2, d6 vhadd.u8 d3, d2, d19 vadd.u8 d3, d3, d7 vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]! subs r12, r12, #16 bgt 1b bx lr endfunc func png_read_filter_row_avg3_neon, export=1 push {r4,lr} ldr r12, [r0, #4] @ rowbytes vmov.i8 d3, #0 mov r0, r1 mov r4, #3 mov lr, #12 vld1.8 {q11}, [r0], lr 1: vld1.8 {q10}, [r2], lr vext.8 d5, d22, d23, #3 vhadd.u8 d0, d3, d20 vext.8 d17, d20, d21, #3 vadd.u8 d0, d0, d22 vext.8 d6, d22, d23, #6 vhadd.u8 d1, d0, d17 vext.8 d18, d20, d21, #6 vadd.u8 d1, d1, d5 vext.8 d7, d23, d23, #1 vld1.8 {q11}, [r0], lr vst1.32 {d0[0]}, [r1,:32], r4 vhadd.u8 d2, d1, d18 vst1.32 {d1[0]}, [r1], r4 vext.8 d19, d21, d21, #1 vadd.u8 d2, d2, d6 vhadd.u8 d3, d2, d19 vst1.32 {d2[0]}, [r1], r4 vadd.u8 d3, d3, d7 vst1.32 {d3[0]}, [r1], r4 subs r12, r12, #12 bgt 1b pop {r4,pc} endfunc .macro paeth rx, ra, rb, rc vaddl.u8 q12, \ra, \rb @ a + b vaddl.u8 q15, \rc, \rc @ 2c vabdl.u8 q13, \rb, \rc @ pa vabdl.u8 q14, \ra, \rc @ pb vabd.u16 q15, q12, q15 @ pc vcle.u16 q12, q13, q14 @ pa <= pb vcle.u16 q13, q13, q15 @ pa <= pc vcle.u16 q14, q14, q15 @ pb <= pc vand q12, q12, q13 @ pa <= pb && pa <= pc vmovn.u16 d28, q14 vmovn.u16 \rx, q12 vbsl d28, \rb, \rc vbsl \rx, \ra, d28 .endm func png_read_filter_row_paeth4_neon, export=1 ldr r12, [r0, #4] @ rowbytes vmov.i8 d3, #0 vmov.i8 d20, #0 1: vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] vld4.32 {d16[],d17[],d18[],d19[]},[r2,:128]! paeth d0, d3, d16, d20 vadd.u8 d0, d0, d4 paeth d1, d0, d17, d16 vadd.u8 d1, d1, d5 paeth d2, d1, d18, d17 vadd.u8 d2, d2, d6 paeth d3, d2, d19, d18 vmov d20, d19 vadd.u8 d3, d3, d7 vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]! subs r12, r12, #16 bgt 1b bx lr endfunc func png_read_filter_row_paeth3_neon, export=1 push {r4,lr} ldr r12, [r0, #4] @ rowbytes vmov.i8 d3, #0 vmov.i8 d4, #0 mov r0, r1 mov r4, #3 mov lr, #12 vld1.8 {q11}, [r0], lr 1: vld1.8 {q10}, [r2], lr paeth d0, d3, d20, d4 vext.8 d5, d22, d23, #3 vadd.u8 d0, d0, d22 vext.8 d17, d20, d21, #3 paeth d1, d0, d17, d20 vst1.32 {d0[0]}, [r1,:32], r4 vext.8 d6, d22, d23, #6 vadd.u8 d1, d1, d5 vext.8 d18, d20, d21, #6 paeth d2, d1, d18, d17 vext.8 d7, d23, d23, #1 vld1.8 {q11}, [r0], lr vst1.32 {d1[0]}, [r1], r4 vadd.u8 d2, d2, d6 vext.8 d19, d21, d21, #1 paeth d3, d2, d19, d18 vst1.32 {d2[0]}, [r1], r4 vmov d4, d19 vadd.u8 d3, d3, d7 vst1.32 {d3[0]}, [r1], r4 subs r12, r12, #12 bgt 1b pop {r4,pc} endfunc #endif /* PNG_ARM_NEON_OPT > 0 / #endif / PNG_ARM_NEON_IMPLEMENTATION == 2 (assembler) / #endif / READ */
JackMyles/BASIC-to-ASM-Compiler	1,801	runtime/call_check.s	# This is a custom entry point that calls basic_main() for a compiled BASIC program # and verifies that it satisfies the x86-64 calling convention. # This means that the callee-save registers and all memory above %rsp # at the start of basic_main() must not be modified. .rodata check_failed_msg: .string "x86-64 calling convention violated\n" .text .globl _start _start: # Put 32 KB of canary data on the stack movq $-0x1000, %rcx leaq (%rsp, %rcx, 8), %rsp movq %rsp, %rdi movq $0x1BF532C94A760E8D, %rax negq %rcx cld rep stosq # Put canary values in callee-save registers movq $0xB42607DE9FA358C1, %rbx movq $0x412087E6FAB9C53D, %rbp movq $0x514D387C6AE02B9F, %r12 movq $0xE5BF4238C1DA9760, %r13 movq $0xCB9FD8524A630E71, %r14 movq $0xD0B5F947CEA23618, %r15 call basic_main # Check that callee-save registers haven't changed movq $0xB42607DE9FA358C1, %rax cmpq %rax, %rbx jne check_failed movq $0x412087E6FAB9C53D, %rax cmpq %rax, %rbp jne check_failed movq $0x514D387C6AE02B9F, %rax cmpq %rax, %r12 jne check_failed movq $0xE5BF4238C1DA9760, %rax cmpq %rax, %r13 jne check_failed movq $0xCB9FD8524A630E71, %rax cmpq %rax, %r14 jne check_failed movq $0xD0B5F947CEA23618, %rax cmpq %rax, %r15 jne check_failed # Check canary values on stack movq %rsp, %rdi movq $0x1BF532C94A760E8D, %rax movl $0x1000, %ecx repe scasq jne check_failed # Checks succeeded; exit with code 0 movl $0, %edi call exit@plt # Checks failed; print a warning message and exit with error status check_failed: leaq check_failed_msg(%rip), %rdi movq stderr(%rip), %rsi call fputs@plt movl $1, %edi call exit@plt
JackMyles/BASIC-to-ASM-Compiler	42	runtime/print_int_mock.s	.text .globl print_int print_int: ret
JackMyles/BASIC-to-ASM-Compiler	643	runtime/print_int.s	.rodata int_format: .string "%ld\n" .text .globl print_int print_int: movq %rdi, %rsi leaq int_format(%rip), %rdi # LABEL(%rip) computes the address of LABEL relative to %rip movb $0, %al # %al stores the number of float arguments to printf() call printf@plt # Clobber all caller-save registers movq $0x6A2CFE91073BD845, %rax movq $0x03BAD7C14F2E6589, %rdi movq $0x5D41EA960C72F8B3, %rsi movq $0xEC364B2D5A7F9810, %rdx movq $0xFC85AD49320BE167, %rcx movq $0x529A48CDB7163E0F, %r8 movq $0x92E1587A4BDCF630, %r9 movq $0x47DC36501F89AEB2, %r10 movq $0xAF4B29785C61ED30, %r11 ret
JacobInwald/courseworks	182	Compiling Techniques/coursework-3-JacobInwald/tests/riscv/parser/labels.s	# RUN: ../../../riscv/parser.py %s \| filecheck %s foo: add a0, a0, a0 # CHECK: foo: # CHECK-NEXT: add a0, a0, a0 bar: add a0, a0, a0 # CHECK: bar: # CHECK-NEXT: add a0, a0, a0
JacobInwald/courseworks	7,024	Compiling Techniques/coursework-3-JacobInwald/tests/riscv/parser/ops.s	# RUN: ../../../riscv/parser.py %s \| filecheck %s loadbyte: lb t0, t2 lb t0, t2, 0 lb t0, t2, 12 lb t0, t2, -34 lb t0, 0(t2) lb t0, 56(t2) lb t0, -78(t2) # CHECK: loadbyte: # CHECK-NEXT: lb t0, 0(t2) # CHECK-NEXT: lb t0, 0(t2) # CHECK-NEXT: lb t0, 12(t2) # CHECK-NEXT: lb t0, -34(t2) # CHECK-NEXT: lb t0, 0(t2) # CHECK-NEXT: lb t0, 56(t2) # CHECK-NEXT: lb t0, -78(t2) loadbyteunsigned: lbu t0, t2 lbu t0, t2, 0 lbu t0, t2, 12 lbu t0, t2, -34 lbu t0, 0(t2) lbu t0, 56(t2) lbu t0, -78(t2) # CHECK: loadbyteunsigned: # CHECK-NEXT: lbu t0, 0(t2) # CHECK-NEXT: lbu t0, 0(t2) # CHECK-NEXT: lbu t0, 12(t2) # CHECK-NEXT: lbu t0, -34(t2) # CHECK-NEXT: lbu t0, 0(t2) # CHECK-NEXT: lbu t0, 56(t2) # CHECK-NEXT: lbu t0, -78(t2) loadhalf: lh t0, t2 lh t0, t2, 0 lh t0, t2, 12 lh t0, t2, -34 lh t0, 0(t2) lh t0, 56(t2) lh t0, -78(t2) # CHECK: loadhalf: # CHECK-NEXT: lh t0, 0(t2) # CHECK-NEXT: lh t0, 0(t2) # CHECK-NEXT: lh t0, 12(t2) # CHECK-NEXT: lh t0, -34(t2) # CHECK-NEXT: lh t0, 0(t2) # CHECK-NEXT: lh t0, 56(t2) # CHECK-NEXT: lh t0, -78(t2) loadhalfunsigned: lhu t0, t2 lhu t0, t2, 0 lhu t0, t2, 12 lhu t0, t2, -34 lhu t0, 0(t2) lhu t0, 56(t2) lhu t0, -78(t2) # CHECK: loadhalfunsigned: # CHECK-NEXT: lhu t0, 0(t2) # CHECK-NEXT: lhu t0, 0(t2) # CHECK-NEXT: lhu t0, 12(t2) # CHECK-NEXT: lhu t0, -34(t2) # CHECK-NEXT: lhu t0, 0(t2) # CHECK-NEXT: lhu t0, 56(t2) # CHECK-NEXT: lhu t0, -78(t2) loadword: lw t0, t2 lw t0, t2, 0 lw t0, t2, 12 lw t0, t2, -34 lw t0, 0(t2) lw t0, 56(t2) lw t0, -78(t2) # CHECK: loadword: # CHECK-NEXT: lw t0, 0(t2) # CHECK-NEXT: lw t0, 0(t2) # CHECK-NEXT: lw t0, 12(t2) # CHECK-NEXT: lw t0, -34(t2) # CHECK-NEXT: lw t0, 0(t2) # CHECK-NEXT: lw t0, 56(t2) # CHECK-NEXT: lw t0, -78(t2) storebyte: sb t0, t2 sb t0, t2, 0 sb t0, t2, 12 sb t0, t2, -34 sb t0, 0(t2) sb t0, 56(t2) sb t0, -78(t2) # CHECK: storebyte: # CHECK-NEXT: sb t0, 0(t2) # CHECK-NEXT: sb t0, 0(t2) # CHECK-NEXT: sb t0, 12(t2) # CHECK-NEXT: sb t0, -34(t2) # CHECK-NEXT: sb t0, 0(t2) # CHECK-NEXT: sb t0, 56(t2) # CHECK-NEXT: sb t0, -78(t2) storehalf: sh t0, t2 sh t0, t2, 0 sh t0, t2, 12 sh t0, t2, -34 sh t0, 0(t2) sh t0, 56(t2) sh t0, -78(t2) # CHECK: storehalf: # CHECK-NEXT: sh t0, 0(t2) # CHECK-NEXT: sh t0, 0(t2) # CHECK-NEXT: sh t0, 12(t2) # CHECK-NEXT: sh t0, -34(t2) # CHECK-NEXT: sh t0, 0(t2) # CHECK-NEXT: sh t0, 56(t2) # CHECK-NEXT: sh t0, -78(t2) storeword: sw t0, t2 sw t0, t2, 0 sw t0, t2, 12 sw t0, t2, -34 sw t0, 0(t2) sw t0, 56(t2) sw t0, -78(t2) # CHECK: storeword: # CHECK-NEXT: sw t0, 0(t2) # CHECK-NEXT: sw t0, 0(t2) # CHECK-NEXT: sw t0, 12(t2) # CHECK-NEXT: sw t0, -34(t2) # CHECK-NEXT: sw t0, 0(t2) # CHECK-NEXT: sw t0, 56(t2) # CHECK-NEXT: sw t0, -78(t2) branches: beq t0, t2, 0 beq t0, t2, 12 beq t0, t2, -34 beq t0, t2, branches bne t0, t2, 0 bne t0, t2, 56 bne t0, t2, -78 bne t0, t2, branches blt t0, t2, 0 blt t0, t2, 91 blt t0, t2, -23 blt t0, t2, branches bge t0, t2, 0 bge t0, t2, 45 bge t0, t2, -67 bge t0, t2, branches bltu t0, t2, 0 bltu t0, t2, 89 bltu t0, t2, -12 bltu t0, t2, branches bgeu t0, t2, 0 bgeu t0, t2, 34 bgeu t0, t2, -56 bgeu t0, t2, branches # CHECK: branches # CHECK-NEXT beq t0, t2, 0 # CHECK-NEXT beq t0, t2, 12 # CHECK-NEXT beq t0, t2, -34 # CHECK-NEXT beq t0, t2, branches # CHECK-NEXT bne t0, t2, 0 # CHECK-NEXT bne t0, t2, 56 # CHECK-NEXT bne t0, t2, -78 # CHECK-NEXT bne t0, t2, branches # CHECK-NEXT blt t0, t2, 0 # CHECK-NEXT blt t0, t2, 91 # CHECK-NEXT blt t0, t2, -23 # CHECK-NEXT blt t0, t2, branches # CHECK-NEXT bge t0, t2, 0 # CHECK-NEXT bge t0, t2, 45 # CHECK-NEXT bge t0, t2, -67 # CHECK-NEXT bge t0, t2, branches # CHECK-NEXT bltu t0, t2, 0 # CHECK-NEXT bltu t0, t2, 89 # CHECK-NEXT bltu t0, t2, -12 # CHECK-NEXT bltu t0, t2, branches # CHECK-NEXT bgeu t0, t2, 0 # CHECK-NEXT bgeu t0, t2, 34 # CHECK-NEXT bgeu t0, t2, -56 # CHECK-NEXT bgeu t0, t2, branches shifts: sll t0, t1, t2 slli t0, t1, 0 slli t0, t1, 1 slli t0, t1, 2 srl t0, t1, t2 srli t0, t1, 0 srli t0, t1, 1 srli t0, t1, 2 sra t0, t1, t2 srai t0, t1, 0 srai t0, t1, 1 srai t0, t1, 2 # CHECK: shifts: # CHECK-NEXT: sll t0, t1, t2 # CHECK-NEXT: slli t0, t1, 0 # CHECK-NEXT: slli t0, t1, 1 # CHECK-NEXT: slli t0, t1, 2 # CHECK-NEXT: srl t0, t1, t2 # CHECK-NEXT: srli t0, t1, 0 # CHECK-NEXT: srli t0, t1, 1 # CHECK-NEXT: srli t0, t1, 2 # CHECK-NEXT: sra t0, t1, t2 # CHECK-NEXT: srai t0, t1, 0 # CHECK-NEXT: srai t0, t1, 1 # CHECK-NEXT: srai t0, t1, 2 arithmetic: add t0, t1, t2 addi t0, t1, 0 addi t0, t1, -12 addi t0, t1, -34 sub t0, t1, t2 lui t0, 12 lui t0, -34 auipc t0, 12 auipc t0, -34 # CHECK: arithmetic: # CHECK-NEXT: add t0, t1, t2 # CHECK-NEXT: addi t0, t1, 0 # CHECK-NEXT: addi t0, t1, -12 # CHECK-NEXT: addi t0, t1, -34 # CHECK-NEXT: sub t0, t1, t2 # CHECK-NEXT: lui t0, 12 # CHECK-NEXT: lui t0, -34 # CHECK-NEXT: auipc t0, 12 # CHECK-NEXT: auipc t0, -34 logical: xor t0, t1, t2 xori t0, t1, 0 xori t0, t1, -12 xori t0, t1, -34 or t0, t1, t2 ori t0, t1, 0 ori t0, t1, -12 ori t0, t1, -34 and t0, t1, t2 andi t0, t1, 0 andi t0, t1, -12 andi t0, t1, -34 # CHECK: logical: # CHECK-NEXT: xor t0, t1, t2 # CHECK-NEXT: xori t0, t1, 0 # CHECK-NEXT: xori t0, t1, -12 # CHECK-NEXT: xori t0, t1, -34 # CHECK-NEXT: or t0, t1, t2 # CHECK-NEXT: ori t0, t1, 0 # CHECK-NEXT: ori t0, t1, -12 # CHECK-NEXT: ori t0, t1, -34 # CHECK-NEXT: and t0, t1, t2 # CHECK-NEXT: andi t0, t1, 0 # CHECK-NEXT: andi t0, t1, -12 # CHECK-NEXT: andi t0, t1, -34 compare: slt t0, t1, t2 slti t0, t1, 0 slti t0, t1, -12 slti t0, t1, -34 sltu t0, t1, t2 sltiu t0, t1, 0 sltiu t0, t1, -12 sltiu t0, t1, -34 # CHECK: compare: # CHECK-NEXT: slt t0, t1, t2 # CHECK-NEXT: slti t0, t1, 0 # CHECK-NEXT: slti t0, t1, -12 # CHECK-NEXT: slti t0, t1, -34 # CHECK-NEXT: sltu t0, t1, t2 # CHECK-NEXT: sltiu t0, t1, 0 # CHECK-NEXT: sltiu t0, t1, -12 # CHECK-NEXT: sltiu t0, t1, -34 jumpandlink: jal t0, 0 jal t0, -12 jal t0, 32 jal t0, jumpandlink jalr t0, t1, 0 jalr t0, t1, -12 jalr t0, t1, 32 jalr t0, t1, jumpandlink # CHECK: jumpandlink: # CHECK-NEXT: jal t0, 0 # CHECK-NEXT: jal t0, -12 # CHECK-NEXT: jal t0, 32 # CHECK-NEXT: jal t0, jumpandlink # CHECK-NEXT: jalr t0, t1, 0 # CHECK-NEXT: jalr t0, t1, -12 # CHECK-NEXT: jalr t0, t1, 32 # CHECK-NEXT: jalr t0, t1, jumpandlink multiplicative: mul t0, t1, t2 mulh t0, t1, t2 mulhsu t0, t1, t2 mulhu t0, t1, t2 mulhu t0, t1, t2 div t0, t1, t2 divu t0, t1, t2 rem t0, t1, t2 remu t0, t1, t2 # CHECK: multiplicative: # CHECK-NEXT: mul t0, t1, t2 # CHECK-NEXT: mulh t0, t1, t2 # CHECK-NEXT: mulhsu t0, t1, t2 # CHECK-NEXT: mulhu t0, t1, t2 # CHECK-NEXT: mulhu t0, t1, t2 # CHECK-NEXT: div t0, t1, t2 # CHECK-NEXT: divu t0, t1, t2 # CHECK-NEXT: rem t0, t1, t2 # CHECK-NEXT: remu t0, t1, t2 system: ecall ebreak # CHECK: system: # CHECK-NEXT: ecall # CHECK-NEXT: ebreak
JacobInwald/courseworks	180	Compiling Techniques/coursework-3-JacobInwald/tests/riscv/parser/directives.s	# RUN: ../../../riscv/parser.py %s \| filecheck %s .asciz "somestring" # CHECK: .asciz "somestring" .section .text # CHECK: .section .text .global getasm # CHECK: .global getasm
JacobInwald/courseworks	2,427	Compiling Techniques/coursework-3-JacobInwald/tests/riscv/parser/registers.s	# RUN: ../../../riscv/parser.py %s \| filecheck %s registers: # CHECK: registers: jal x0, 0 # CHECK-NEXT: jal zero, 0 jal x1, 0 # CHECK-NEXT: jal ra, 0 jal x2, 0 # CHECK-NEXT: jal sp, 0 jal x3, 0 # CHECK-NEXT: jal gp, 0 jal x4, 0 # CHECK-NEXT: jal tp, 0 jal x5, 0 # CHECK-NEXT: jal t0, 0 jal x6, 0 # CHECK-NEXT: jal t1, 0 jal x7, 0 # CHECK-NEXT: jal t2, 0 jal x8, 0 # CHECK-NEXT: jal fp, 0 jal x9, 0 # CHECK-NEXT: jal s1, 0 jal x10, 0 # CHECK-NEXT: jal a0, 0 jal x11, 0 # CHECK-NEXT: jal a1, 0 jal x12, 0 # CHECK-NEXT: jal a2, 0 jal x13, 0 # CHECK-NEXT: jal a3, 0 jal x14, 0 # CHECK-NEXT: jal a4, 0 jal x15, 0 # CHECK-NEXT: jal a5, 0 jal x16, 0 # CHECK-NEXT: jal a6, 0 jal x17, 0 # CHECK-NEXT: jal a7, 0 jal x18, 0 # CHECK-NEXT: jal s2, 0 jal x19, 0 # CHECK-NEXT: jal s3, 0 jal x20, 0 # CHECK-NEXT: jal s4, 0 jal x21, 0 # CHECK-NEXT: jal s5, 0 jal x22, 0 # CHECK-NEXT: jal s6, 0 jal x23, 0 # CHECK-NEXT: jal s7, 0 jal x24, 0 # CHECK-NEXT: jal s8, 0 jal x25, 0 # CHECK-NEXT: jal s9, 0 jal x26, 0 # CHECK-NEXT: jal s10, 0 jal x27, 0 # CHECK-NEXT: jal s11, 0 jal x28, 0 # CHECK-NEXT: jal t3, 0 jal x29, 0 # CHECK-NEXT: jal t4, 0 jal x30, 0 # CHECK-NEXT: jal t5, 0 jal x31, 0 # CHECK-NEXT: jal t6, 0 abinames: # CHECK-NEXT: abinames: jal zero, 0 # CHECK-NEXT: jal zero, 0 jal ra, 0 # CHECK-NEXT: jal ra, 0 jal sp, 0 # CHECK-NEXT: jal sp, 0 jal gp, 0 # CHECK-NEXT: jal gp, 0 jal tp, 0 # CHECK-NEXT: jal tp, 0 jal t0, 0 # CHECK-NEXT: jal t0, 0 jal t1, 0 # CHECK-NEXT: jal t1, 0 jal t2, 0 # CHECK-NEXT: jal t2, 0 jal fp, 0 # CHECK-NEXT: jal fp, 0 jal s0, 0 # CHECK-NEXT: jal fp, 0 jal s1, 0 # CHECK-NEXT: jal s1, 0 jal a0, 0 # CHECK-NEXT: jal a0, 0 jal a1, 0 # CHECK-NEXT: jal a1, 0 jal a2, 0 # CHECK-NEXT: jal a2, 0 jal a3, 0 # CHECK-NEXT: jal a3, 0 jal a4, 0 # CHECK-NEXT: jal a4, 0 jal a5, 0 # CHECK-NEXT: jal a5, 0 jal a6, 0 # CHECK-NEXT: jal a6, 0 jal a7, 0 # CHECK-NEXT: jal a7, 0 jal s2, 0 # CHECK-NEXT: jal s2, 0 jal s3, 0 # CHECK-NEXT: jal s3, 0 jal s4, 0 # CHECK-NEXT: jal s4, 0 jal s5, 0 # CHECK-NEXT: jal s5, 0 jal s6, 0 # CHECK-NEXT: jal s6, 0 jal s7, 0 # CHECK-NEXT: jal s7, 0 jal s8, 0 # CHECK-NEXT: jal s8, 0 jal s9, 0 # CHECK-NEXT: jal s9, 0 jal s10, 0 # CHECK-NEXT: jal s10, 0 jal s11, 0 # CHECK-NEXT: jal s11, 0 jal t3, 0 # CHECK-NEXT: jal t3, 0 jal t4, 0 # CHECK-NEXT: jal t4, 0 jal t5, 0 # CHECK-NEXT: jal t5, 0 jal t6, 0 # CHECK-NEXT: jal t6, 0
JacobInwald/courseworks	2,779	Compiling Techniques/coursework-3-JacobInwald/tests/riscv/parser/pseudoops.s	# RUN: ../../../riscv/parser.py %s \| filecheck %s nop: nop # CHECK: nop: # CHECK-NEXT: nop li: li t0, 0 li t0, 12345 li t0, -67890 # CHECK: li: # CHECK-NEXT: li t0, 0 # CHECK-NEXT: li t0, 12345 # CHECK-NEXT: li t0, -67890 mv: mv t0, t0 # CHECK: mv: # CHECK-NEXT: mv t0, t0 not: not t0, t0 # CHECK: not: # CHECK-NEXT: not t0, t0 neg: neg t0, t0 # CHECK: neg: # CHECK-NEXT: neg t0, t0 negw: negw t0, t0 # CHECK: negw: # CHECK-NEXT: negw t0, t0 seqz: seqz t0, t0 # CHECK: seqz: # CHECK-NEXT: seqz t0, t0 snez: snez t0, t0 # CHECK: snez: # CHECK-NEXT: snez t0, t0 sltz: sltz t0, t0 # CHECK: sltz: # CHECK-NEXT: sltz t0, t0 sgtz: sgtz t0, t0 # CHECK: sgtz: # CHECK-NEXT: sgtz t0, t0 beqz: beqz t0, 0 beqz t0, -1 beqz t0, 1 beqz t0, beqz # CHECK: beqz: # CHECK-NEXT: beqz t0, 0 # CHECK-NEXT: beqz t0, -1 # CHECK-NEXT: beqz t0, 1 # CHECK-NEXT: beqz t0, beqz bnez: bnez t0, 0 bnez t0, -1 bnez t0, 1 bnez t0, bnez # CHECK: bnez: # CHECK-NEXT: bnez t0, 0 # CHECK-NEXT: bnez t0, -1 # CHECK-NEXT: bnez t0, 1 # CHECK-NEXT: bnez t0, bnez blez: blez t0, 0 blez t0, -1 blez t0, 1 blez t0, blez # CHECK: blez: # CHECK-NEXT: blez t0, 0 # CHECK-NEXT: blez t0, -1 # CHECK-NEXT: blez t0, 1 # CHECK-NEXT: blez t0, blez bgez: bgez t0, 0 bgez t0, -1 bgez t0, 1 bgez t0, bgez # CHECK: bgez: # CHECK-NEXT: bgez t0, 0 # CHECK-NEXT: bgez t0, -1 # CHECK-NEXT: bgez t0, 1 # CHECK-NEXT: bgez t0, bgez bltz: bltz t0, 0 bltz t0, -1 bltz t0, 1 bltz t0, bltz # CHECK: bltz: # CHECK-NEXT: bltz t0, 0 # CHECK-NEXT: bltz t0, -1 # CHECK-NEXT: bltz t0, 1 # CHECK-NEXT: bltz t0, bltz bgtz: bgtz t0, 0 bgtz t0, -1 bgtz t0, 1 bgtz t0, bgtz # CHECK: bgtz: # CHECK-NEXT: bgtz t0, 0 # CHECK-NEXT: bgtz t0, -1 # CHECK-NEXT: bgtz t0, 1 # CHECK-NEXT: bgtz t0, bgtz bgt: bgt t0, t1, 0 bgt t0, t1, -1 bgt t0, t1, 1 bgt t0, t1, bgt # CHECK: bgt: # CHECK-NEXT: bgt t0, t1, 0 # CHECK-NEXT: bgt t0, t1, -1 # CHECK-NEXT: bgt t0, t1, 1 # CHECK-NEXT: bgt t0, t1, bgt ble: ble t0, t1, 0 ble t0, t1, -1 ble t0, t1, 1 ble t0, t1, ble # CHECK: ble: # CHECK-NEXT: ble t0, t1, 0 # CHECK-NEXT: ble t0, t1, -1 # CHECK-NEXT: ble t0, t1, 1 # CHECK-NEXT: ble t0, t1, ble bgtu: bgtu t0, t1, 0 bgtu t0, t1, -1 bgtu t0, t1, 1 bgtu t0, t1, bgtu # CHECK: bgtu: # CHECK-NEXT: bgtu t0, t1, 0 # CHECK-NEXT: bgtu t0, t1, -1 # CHECK-NEXT: bgtu t0, t1, 1 # CHECK-NEXT: bgtu t0, t1, bgtu bleu: bleu t0, t1, 0 bleu t0, t1, -1 bleu t0, t1, 1 bleu t0, t1, bleu # CHECK: bleu: # CHECK-NEXT: bleu t0, t1, 0 # CHECK-NEXT: bleu t0, t1, -1 # CHECK-NEXT: bleu t0, t1, 1 # CHECK-NEXT: bleu t0, t1, bleu ret: ret # CHECK: ret: # CHECK-NEXT: ret
JacobInwald/courseworks	599	Compiling Techniques/coursework-3-JacobInwald/tests/riscv/interpreter/hello_world.s	# RUN: riscv-interpreter %s \| filecheck %s ; hello-world.asm ; print "Hello World" to stdout and exit .data msg: .ascii "Hello World!\n" .text addi a0, zero, 1 ; print to stdout addi a1, zero, msg ; load msg address addi a2, zero, 12 ; write 12 bytes addi a7, zero, SCALL_WRITE ; write syscall code ecall addi a0, zero, 0 ; set exit code to 0 addi a7, zero, SCALL_EXIT ; exit syscall code ecall ; CHECK: Hello World! ; CHECK-NEXT: Return code: 0
JacobInwald/courseworks	525	Compiling Techniques/coursework-3-JacobInwald/tests/riscv/lexer/labels.s	# RUN: riscv-lexer %s \| filecheck %s foo: add a0, a0, a0 # CHECK: SYMBOL:foo # CHECK-NEXT: COLON # CHECK-NEXT: NEWLINE # CHECK-NEXT: SYMBOL:add # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: NEWLINE bar: add a0, a0, a0 # CHECK: SYMBOL:bar # CHECK-NEXT: COLON # CHECK-NEXT: NEWLINE # CHECK-NEXT: SYMBOL:add # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: NEWLINE
JacobInwald/courseworks	1,071	Compiling Techniques/coursework-3-JacobInwald/tests/riscv/lexer/ops.s	# RUN: riscv-lexer %s \| filecheck %s add a0, a0, a0 # CHECK: SYMBOL:add # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: NEWLINE add a0, a0, 1 # CHECK: SYMBOL:add # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: INTEGER:1 # CHECK-NEXT: NEWLINE add a0, a0, -1 # CHECK: SYMBOL:add # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: MINUS # CHECK-NEXT: INTEGER:1 # CHECK-NEXT: NEWLINE lw t0, t2 # CHECK: SYMBOL:lw # CHECK-NEXT: SYMBOL:t0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:t2 # CHECK-NEXT: NEWLINE lw t0, 0(t2) # CHECK: SYMBOL:lw # CHECK-NEXT: SYMBOL:t0 # CHECK-NEXT: COMMA # CHECK-NEXT: INTEGER:0 # CHECK-NEXT: LPAREN # CHECK-NEXT: SYMBOL:t2 # CHECK-NEXT: RPAREN # CHECK-NEXT: NEWLINE lw t0, 8(t2) # CHECK: SYMBOL:lw # CHECK-NEXT: SYMBOL:t0 # CHECK-NEXT: COMMA # CHECK-NEXT: INTEGER:8 # CHECK-NEXT: LPAREN # CHECK-NEXT: SYMBOL:t2 # CHECK-NEXT: RPAREN # CHECK-NEXT: NEWLINE
JacobInwald/courseworks	364	Compiling Techniques/coursework-3-JacobInwald/tests/riscv/lexer/directives.s	# RUN: riscv-lexer %s \| filecheck %s .asciz "somestring" # CHECK: DOT # CHECK-NEXT: SYMBOL:asciz # CHECK-NEXT: LITERAL:"somestring" # CHECK-NEXT: NEWLINE .section .text # CHECK: DOT # CHECK-NEXT: SYMBOL:section # CHECK-NEXT: DOT # CHECK-NEXT: SYMBOL:text # CHECK-NEXT: NEWLINE .global getasm # CHECK: DOT # CHECK-NEXT: SYMBOL:global # CHECK-NEXT: SYMBOL:getasm
JacopoSini/Rust4Safety_DATE2025	256	Vanilla/src/crt0.s	.section .init, "ax" .global _start _start: .cfi_startproc .cfi_undefined ra .option push .option norelax la gp, __global_pointer$ .option pop la sp, __stack_top add s0, sp, zero jal zero, main .cfi_endproc .end
JacopoSini/Rust4Safety_DATE2025	256	YACCA/src/crt0.s	.section .init, "ax" .global _start _start: .cfi_startproc .cfi_undefined ra .option push .option norelax la gp, __global_pointer$ .option pop la sp, __stack_top add s0, sp, zero jal zero, main .cfi_endproc .end
JacopoSini/Rust4Safety_DATE2025	256	RACFED/src/crt0.s	.section .init, "ax" .global _start _start: .cfi_startproc .cfi_undefined ra .option push .option norelax la gp, __global_pointer$ .option pop la sp, __stack_top add s0, sp, zero jal zero, main .cfi_endproc .end
jared-hughes/defcpu	6,847	tests/integration/print_regs.s	# This file is a modification of defasm/cli/debug.s, which is under the following license. # # Copyright (c) 2021, Alon Ran # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # usage: # # movq $print1_ret, (printRegs_return) # jmp printRegs # print1_ret: sys_write = 1 sys_open = 2 sys_close = 3 sys_fork = 57 sys_execve = 59 sys_exit = 60 sys_ptrace = 101 sys_prctl = 157 sys_waitid = 247 STDERR_FILENO = 2 # Tracing the file .bss # regs are in the order provided by sys_ptrace(PTRACE_GETREGS, ...), even though # we don't currently use sys_ptrace to get regs since we're in the same process. regs: r_R15: .quad 0 r_R14: .quad 0 r_R13: .quad 0 r_R12: .quad 0 r_RBP: .quad 0 r_RBX: .quad 0 r_R11: .quad 0 r_R10: .quad 0 r_R9: .quad 0 r_R8: .quad 0 r_RAX: .quad 0 r_RCX: .quad 0 r_RDX: .quad 0 r_RSI: .quad 0 r_RDI: .quad 0 r_ORIG_RAX: .quad 0 r_RIP: .quad 0 r_CS: .quad 0 r_FLAGS: .quad 0 r_RSP: .quad 0 r_SS: .quad 0 r_FS_BASE: .quad 0 r_GS_BASE: .quad 0 r_DS: .quad 0 r_ES: .quad 0 r_FS: .quad 0 r_GS: .quad 0 # We only need 7 quadwords of stack space. A bit extra to be space. mini_stack: .quad 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 mini_stack_end: .quad 0 .section .rodata pr_hexaChars: .string "0123456789ABCDEF" .data outputBuffer: .byte 0 dumpFile: .long STDERR_FILENO line_num_before: .string "Result from print_regs on line " line_num_before_len = . - line_num_before line_num: .string "\0\0\0\0\0\0\0\0" line_num_len: .byte 0 .text # Print the value of %rax in 16 hexadecimal characters # Uses 6 quadwords of mini_stack space. pr_printQuad: push %rbx push %rdx push %rsi push %rdi push %rcx mov $16, %ebx mov $outputBuffer, %esi pr_nibbleLoop: rol $4, %rax mov %eax, %edx and $0xF, %edx mov pr_hexaChars(%rdx), %dl mov %dl, (%rsi) # Print the nibble push %rax mov $1, %dl mov $sys_write, %eax mov dumpFile, %edi syscall pop %rax dec %ebx jnz pr_nibbleLoop pop %rcx pop %rdi pop %rsi pop %rdx pop %rbx jmp pr_printQuad_done .section .rodata registerOrder: .long r_RAX, r_R8, r_RBX, r_R9, r_RCX, r_R10, r_RDX, r_R11 .long r_RSI, r_R12, r_RDI, r_R13, r_RSP, r_R14, r_RBP, r_R15 .long r_FLAGS flagOrder: .byte 0, 6, 11, 7, 10, 2 dumpString: .string "\ Registers: %rax = \0 %r8 = \0 %rbx = \0 %r9 = \0 %rcx = \0 %r10 = \0 %rdx = \0 %r11 = \0 %rsi = \0 %r12 = \0 %rdi = \0 %r13 = \0 %rsp = \0 %r14 = \0 %rbp = \0 %r15 = \0 Flags (\0): Carry = \0 Zero = \0 Overflow = \0 Sign = \0 Direction = \0 Parity = \0 \0" flagMessages: .string "0 (no carry) ", "1 (carry) " .string "0 (isn't zero) ", "1 (is zero) " .string "0 (no overflow) ", "1 (overflow) " .string "0 (positive) ", "1 (negative) " .string "0 (up) ", "1 (down) " .string "0 (odd) ", "1 (even) " flagMsgLen = 16 .text printRegs: mov %rax, (r_RAX) mov %rbx, (r_RBX) mov %rcx, (r_RCX) mov %rdx, (r_RDX) mov %rsi, (r_RSI) mov %rdi, (r_RDI) mov %rsp, (r_RSP) mov %rbp, (r_RBP) mov %r8, (r_R8) mov %r9, (r_R9) mov %r10, (r_R10) mov %r11, (r_R11) mov %r12, (r_R12) mov %r13, (r_R13) mov %r14, (r_R14) mov %r15, (r_R15) mov $mini_stack_end, %rsp pushfq pop %rax mov %rax, (r_FLAGS) # Print line number if relevant xor %edx, %edx movb (line_num_len), %dl cmp $8, %dl jle line_num_len_ok mov $8, %dl line_num_len_ok: cmp $0, %dl jz line_num_irrelevant mov $sys_write, %eax mov dumpFile, %edi mov $line_num_before, %rsi add $line_num_before_len, %edx syscall line_num_irrelevant: # Print registers xor %ebx, %ebx # bl = 0. Will be incremented on each read to count number of nulls filled in. mov $dumpString, %esi registerLoop: # start of loop: %esi is the start of $dumpString, or points to the last \0. mov %esi, %edi mov $-1, %ecx xor %al, %al # increment %rdi and decrement %ecx until (%rdi) = %al (=0), or %ecx = 0. repnz scasb # %rdi is now a pointer to the null byte; %ecx is negative of its 1-index in the string. push %rdi not %ecx dec %ecx # %ecx is length to print. mov %ecx, %edx mov $sys_write, %eax mov dumpFile, %edi syscall pop %rsi cmp $23, %bl # 17 registers + 6 flags. jge endRegisterLoop cmp $17, %bl # 17 registers (including RFLAGS) jge printFlag # bl < 17: Select register and print it mov registerOrder(, %rbx, 4), %eax mov (%rax), %rax jmp pr_printQuad pr_printQuad_done: jmp nextRegister printFlag: # bl >= 17: Select appropriate flag message push %rsi mov %bl, %dl sub $17, %dl mov flagOrder(%rdx), %al add %dl, %dl # shl $1, %dl bt %eax, r_FLAGS jnc adc_done; add $1, %dl; adc_done:; #adc $0, %dl imul $flagMsgLen, %edx, %edx lea flagMessages(%rdx), %esi mov $flagMsgLen, %edx mov $sys_write, %eax mov dumpFile, %edi syscall pop %rsi nextRegister: inc %ebx jmp registerLoop endRegisterLoop: printRegsDone: mov (r_FLAGS), %rax push %rax popfq mov (r_RAX), %rax mov (r_RBX), %rbx mov (r_RCX), %rcx mov (r_RDX), %rdx mov (r_RSI), %rsi mov (r_RDI), %rdi mov (r_RSP), %rsp mov (r_RBP), %rbp mov (r_R8), %r8 mov (r_R9), %r9 mov (r_R10), %r10 mov (r_R11), %r11 mov (r_R12), %r12 mov (r_R13), %r13 mov (r_R14), %r14 mov (r_R15), %r15 jmp 0x0(%rip) printRegs_return: .quad 0
jared-hughes/defcpu	5,405	tests/integration/dump_initial_state.s	# Dump the intial state of the program execution. # It's not strictly a memory dump -- I'm trying to print # the minimal necessary information to reconstruct the state. # This should just be the program arguments, plus any offsets needed # to determine the consequences of address-space layout randomization (ASLR) # usage: # # jmp dump_initial # dump_initial_ret: # # Don't call with `call` since that goobles the stack. .data # Note we make sure it's impossible to have trailing spaces, # since code.golf trims those. dump_contents: .asciz "Unpredictables:" .asciz "\nrand16" # contents of the 16 bytes at entry 25 (AT_RANDOM) of the auxv. # 16 bytes is 32 nibbles, so 4 quadwords. dump_random_16: .quad 0, 0, 0, 0 .asciz "\nVDSO\0\0" dump_vdso_ptr: .quad 0,0 # entry 33 (AT_SYSINFO_EHDR) of the auxv. .asciz "\nexecfn" dump_execfn_ptr: .quad 0,0 # entry 31 (AT_EXECFN) of the auxv. .asciz "\npltoff" dump_platform_offset: .quad 0,0 # distance from entry 15 (AT_PLATFORM) of the auxv to argv[0]. .asciz "\nargc\0\0" dump_argc: .quad 0,0 # number of arguments .asciz "\narglen" dump_arglen: .quad 0,0 # total number of bytes arguments take up, including null terminators. dump_nlnl: .ascii "\n\n" dump_len = . - dump_contents dump_hexChars: .ascii "0123456789ABCDEF" dump_execfn_ptr_val: .quad 0 dump_printQuad_ret: .quad 0 .text dump_initial: mov %rsp, %r8 # %r8 = initial %rsp. pushfq mov %r8, %rsp # Below here, don't push to the stack. # Using %rsp sneakily to look into the middle of the stack. # get argc pop %rax mov %rax, %rbx mov $dump_argc, %rdi movq $done_printing_argc, dump_printQuad_ret jmp dump_printQuad done_printing_argc: pop %rbp # rbp points to the first argument /tmp/asm. # Skip the arg pointers. # The null separator after argv (before envp) # is at 0x08 + 8 * argc + initial %rsp. # There's no envp, so the null separtor after envp (before auxv) # is at 0x10 + 8 * argc + initial %rsp. # so the first env pointer is 0x08 after that. lea 0x18(%r8, %rax, 8), %rsp # rsp is now the pointer to the first env pointer. # get the relevant environment pointers dump_at_loop: pop %rax # rax is the at_type. pop %rbx # rbx is the a_un (a_ptr or a_val). cmp $0, %rax jz dump_at_loop_done cmp $25, %rax; jz dump_at_type_25 cmp $31, %rax; jz dump_at_type_31 cmp $33, %rax; jz dump_at_type_33 cmp $15, %rax; jnz dump_at_loop dump_at_type_15: # AT_PLATFORM mov $0x100, %ecx mov %rbx, %rdi mov $0, %al repne scasb # %rdi now points to the nul terminator of the platform string mov %rbp, %rbx sub %rdi, %rbx # rbx is now the distance from the nul terminator of the # platform string "x86_64", to argv[0]. # decrement due to growing down. dec %rbx mov $dump_platform_offset, %edi movq $dump_at_loop, dump_printQuad_ret jmp dump_printQuad dump_at_type_25: # AT_RANDOM mov %rbx, %rax movq (%rax), %rbx bswap %rbx movq $after_first_quad_25, dump_printQuad_ret movq $dump_random_16, %edi jmp dump_printQuad after_first_quad_25: movq 0x8(%rax), %rbx bswap %rbx movq $dump_at_loop, dump_printQuad_ret jmp dump_printQuad dump_at_type_33: # AT_SYSINFO_EHDR mov $dump_vdso_ptr, %edi movq $dump_at_loop, dump_printQuad_ret jmp dump_printQuad dump_at_type_31: # AT_EXECFN mov %rbx, dump_execfn_ptr_val mov $dump_execfn_ptr, %edi movq $dump_at_loop, dump_printQuad_ret jmp dump_printQuad dump_at_loop_done: # all auxv entries popped, including the null entry. # calculate arglen mov dump_execfn_ptr_val, %rbx mov %rbp, %rsi # rsi = pointer to first arg sub %rsi, %rbx # rbx = arglen (bytes) # dump arglen movq $dump_arglen, %rdi movq $done_printing_arglen, dump_printQuad_ret jmp dump_printQuad done_printing_arglen: mov $dump_contents, %rsi mov $dump_len, %edx mov $1, %eax # sys_write mov $1, %edi # stdout syscall # calculate arglen mov dump_execfn_ptr_val, %rdx mov %rbp, %rsi # rsi = pointer to first arg sub %rsi, %rdx # rdx = arglen = count (bytes) mov $1, %eax # sys_write mov $1, %edi # stdout syscall mov $dump_nlnl, %esi mov $2, %edx mov $1, %eax # sys_write mov $1, %edi #stdout # Reset all registers to 0, except %rsp which should be back to normal. mov %r8, %rsp # but we also need to zero the extra quadword written to store flags add $-0x8, %rsp popfq xor %eax, %eax mov %rax, -0x8(%rsp) xor %ecx, %ecx xor %edx, %edx xor %esi, %esi xor %edi, %edi xor %rbp, %rbp xor %r11, %r11 xor %r8, %r8 jmp dump_initial_ret # print %rbx (8 bytes) as nibbles, to %rdi (16 bytes of nibbles) # returns to dump_printQuad_ret dump_printQuad: mov $16, %ecx xor %edx, %edx dump_random_nibble_loop: rol $4, %rbx mov %bl, %dl and $0xF, %dl mov dump_hexChars(%rdx), %dl mov %dl, (%rdi) inc %rdi dec %ecx jnz dump_random_nibble_loop jmp *dump_printQuad_ret
jared-hughes/defcpu	214	tests/integration/sources/007_movmem.s	# hole: fibonacci mov $0x00007FFEA10A6BE0, %rsp mov $mem, %ebp mov (%ebp), %al mov (%ebp), %bh mov (%ebp), %cx mov (%ebp), %edx mov (%ebp), %rsi hlt .data mem: .byte 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0
jared-hughes/defcpu	467	tests/integration/sources/013_xchg.s	# hole: fibonacci mov $0, %rsp mov $0x0102030405060708, %rax mov $0xA1B1C1D1E1F1A1B1, %rbx xchg %rax, %rbx xchg %rax, %r11 xchg %r11, %rcx xchg %rbx, %r8 xchg %r8d, %edx nop print_regs xchg %r11w, %si xchg %ax, %dx xchg %bl, %dl print_regs mov $x, %rax mov $y, %rbx xchg (%rax), %dl xchg (%rax), %cx xchg (%rbx), %edx xchg (%rbx), %rbx print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall .data x: .quad 0xabcdef12345678ab y: .quad 0xab12345678abcdef
jared-hughes/defcpu	45	tests/integration/sources/018_syscall_0.s	# hole: fibonacci dump_initial syscall hlt
jared-hughes/defcpu	836	tests/integration/sources/014_cltq_cbw.s	# hole: fibonacci mov $0, %rsp mov $0x1234567812345678, %rdx mov $0x0000, %ax cwtd print_regs mov $0x1234567812345678, %rdx mov $0x8000, %ax cwtd print_regs mov $0x1234567812345678, %rdx mov $0x00000000, %eax cltd print_regs mov $0x1234567812345678, %rdx mov $0x80000000, %eax cltd print_regs mov $0x1234567812345678, %rdx mov $0x0000000000000, %rax cqto print_regs mov $0x1234567812345678, %rdx mov $0x8000000000000, %rax cqto print_regs mov $0x1234567812345678, %rdx mov $0x00, %al cbtw print_regs mov $0x1234567812345678, %rdx mov $0x80, %al cbtw print_regs mov $0x1234567812345678, %rdx mov $0x0000, %ax cwtl print_regs mov $0x1234567812345678, %rdx mov $0x8000, %ax cwtl print_regs mov $0x1234567812345678, %rdx mov $0x00000000, %eax cltq print_regs mov $0x1234567812345678, %rdx mov $0x80000000, %eax cltq print_regs
jared-hughes/defcpu	370	tests/integration/sources/003_mov8.s	# hole: fibonacci mov $0x00007FFF3EA39100, %rsp mov $0x11, %al mov $0x12, %cl mov $0x13, %dl mov $0x14, %bl mov $0x21, %ah mov $0x22, %ch mov $0x23, %dh mov $0x24, %bh mov $0x31, %sil mov $0x32, %dil mov $0x33, %spl mov $0x34, %bpl mov $0x41, %r8b mov $0x42, %r9b mov $0x43, %r10b mov $0x44, %r11b mov $0x45, %r12b mov $0x46, %r13b mov $0x47, %r14b mov $0x48, %r15b hlt
jared-hughes/defcpu	500	tests/integration/sources/006_mov64.s	# hole: fibonacci mov $0x87654321DEA0BEEF, %rax mov $0x87654321DEA1BEEE, %rcx mov $0x87654321DEA2BEED, %rdx mov $0x87654321DEA3BEEC, %rbx mov $0x87654321DEA4BEEB, %rsp mov $0x87654321DEA5BEEA, %rbp mov $0x87654321DEA6BEE9, %rsi mov $0x87654321DEA7BEE8, %rdi mov $0x87654321DEA8BEE7, %r8 mov $0x87654321DEA9BEE6, %r9 mov $0x87654321DEAABEE5, %r10 mov $0x87654321DEABBEE4, %r11 mov $0x87654321DEACBEE3, %r12 mov $0x87654321DEADBEE2, %r13 mov $0x87654321DEAEBEE1, %r14 mov $0x87654321DEAFBEE0, %r15 hlt
jared-hughes/defcpu	8,513	tests/integration/sources/016_dump.s	# hole: rock-paper-scissors-spock-lizard SYS_WRITE = 1 SYS_EXIT = 60 STDOUT_FILENO = 1 .text dump_initial print_regs mov $argc, %rsi call printsz pop %rax push %rax call printDec # argc (one eighbyte) pop %rbx mov $nl, %rsi call printsz # always at least one arg because $0 = /tmp/asm argLoop: pop %rsi # pop the next arg pointer push %rsi mov $ox, %rsi; call printsz; pop %rax; push %rax; call printQuad; mov $colon_space, %rsi; call printsz; pop %rsi; call printsz; mov $nl, %rsi; call printsz dec %rbx jnz argLoop endArgLoop: call print_stack_quad # .quad 0 # one eightbyte each of environment pointers (none on code.golf) call print_stack_quad # .quad 0 # begin auxiliary vector entries: call print_auxv # a_type=33 (AT_SYSINFO_EHDR), a_un = pointer to start of ELF file? Always &0xFFF = 0x000 call print_auxv # a_type=51 (AT_MINSIGSTKSZ), a_val = 0xD30 call print_auxv # a_type=16 (AT_HWCAP), a_val = 0x178BFBFF call print_auxv # a_type=6 (AT_PAGESZ), a_val = 0x1000 call print_auxv # a_type=17 (AT_CLKTCK), a_val = 0x64 call print_auxv # a_type=3 (AT_PHDR), a_ptr = 0x0 call print_auxv # a_type=4 (AT_PHENT), a_val = 0x38 call print_auxv # a_type=5 (AT_PHNUM), a_val = 0x3 call print_auxv # a_type=7 (AT_BASE), a_ptr = 0x0 call print_auxv # a_type=8 (AT_FLAGS), a_val = 0x0 call print_auxv # a_type=9 (AT_ENTRY), a_ptr = 0x400000 call print_auxv # a_type=11 (AT_UID), a_val = 0xFFFE call print_auxv # a_type=12 (AT_EUID), a_val = 0xFFFE call print_auxv # a_type=13 (AT_GID), a_val = 0xFFFE call print_auxv # a_type=14 (AT_EGID), a_val = 0xFFFE call print_auxv # a_type=23 (AT_SECURE), a_val = 0x0 call print_auxv # a_type=25 (AT_RANDOM), a_un = stack pointer # (to 16 random bytes. always +0x1 or +0x9 on the info_block_end, whatever ends in 0x9) call print_auxv # a_type=26 (AT_HWCAP2), a_val = 0x2 # (docs say it should be zero) call print_auxv # a_type=31 (AT_EXECFN), a_ptr = stack pointer # (to char* filename "/tmp/asm". always 0xFEF in address on a page. # Either the page after info_block_end, or the same page, # precisely ((info_block_end + [0x0 or 0x1000]) & ~0xFFF) \| 0xFEF) call print_auxv # a_type=15 (AT_PLATFORM), a_ptr = stack pointer # (to char* platform "x86_64". always +0x11 or +0x19 on the info_block_end, whatever ends in 0x9) call print_auxv # null auxiliary vector entry # unspecified: # call print_stack_quad # .quad 0 mov $finished_aux_vec, %rsi; call printsz mov %rsp, info_block_end mov %rsp, %rbx mov at_random, %rcx; sub %rbx, %rcx; mov $at_random_str, %rsi; call printsz; mov %rcx, %rax; call printQuad; mov $nl, %rsi; call printsz; mov at_platform, %rcx; sub %rbx, %rcx; mov $at_platform_str, %rsi; call printsz; mov %rcx, %rax; call printQuad; mov $nl, %rsi; call printsz; mov at_execfn, %rcx; sub %rbx, %rcx; mov $at_execfn_str, %rsi; call printsz; mov %rcx, %rax; call printQuad; mov $nl, %rsi; call printsz; mov at_33, %rcx; sub %rbx, %rcx; mov $at_33_str, %rsi; call printsz; mov %rcx, %rax; call printQuad; mov $nl, %rsi; call printsz; mov %rsp, %rsi call hexdump_page mov at_execfn, %rbx cmp %rbx, %rsi jge already_dumped_execfn call hexdump_page already_dumped_execfn: # the pages after at_execfn are not readable. mov at_33, %rsi call hexdump_page # segfault expected here. seems to only have one page at 33. add $0x1000, %rsi call hexdump_page jmp exit .data at_33: .quad 0 at_random: .quad 0 at_execfn: .quad 0 at_platform: .quad 0 info_block_end: .quad 0 .text print_stack_quad: pop %r8 # return rip mov $ox, %rsi; call printsz pop %rax; call printQuad mov $nl, %rsi; call printsz push %r8 ret # Pops two quadwords, treats it as auxv_t (see https://gitlab.com/x86-psABIs/x86-64-ABI) # The first quadword is a_type. The second is a_un, which may be anything (pointer or value) print_auxv: pop %r8 # return rip mov $a_type_eq, %rsi call printsz pop %rax mov %rax, %r12 call printDec mov $auxv_mid, %rsi call printsz pop %rax mov %rax, %r13 call printQuad cmp $33, %r12 je char_star_33 cmp $31, %r12 je char_star_31 cmp $15, %r12 je char_star_15 cmp $25, %r12 je sixteen_random jmp done_branch sixteen_random: mov $at_random, %eax; mov %r13, (%eax); mov $sixteen_open, %rsi; call printsz mov $nl, %rsi; call printsz mov %r13, %rsi; call print16 mov $sixteen_close, %rsi; call printsz jmp done_branch char_star_33: mov $at_33, %eax; mov %r13, (%eax); jmp char_star char_star_31: mov $at_execfn, %eax; mov %r13, (%eax); jmp char_star char_star_15: mov $at_platform, %eax; mov %r13, (%eax); jmp char_star char_star: mov $str_open, %rsi; call printsz mov %r13, %rsi call printsz mov $str_close, %rsi call printsz done_branch: mov $nl, %rsi call printsz push %r8 ret .data a_type_eq: .asciz "a_type=" colon_space: .asciz ": " nl: .asciz "\n" auxv_mid: .asciz ",\ta_un=0x" ox: .asciz "0x" argc: .asciz "argc=" str_open: .asciz " (char*) (\"" str_close: .asciz "\")" sixteen_open: .asciz " (char[16]) (\"" sixteen_close: .asciz "\")" finished_aux_vec: .asciz "Finished reading aux vector entries. Offsets:\n" at_33_str: .asciz "AT 33 (??):\t+0x" at_random_str: .asciz "AT_RANDOM:\t+0x" at_execfn_str: .asciz "AT_EXECFN:\t+0x" at_platform_str: .asciz "AT_PLATFORM:\t+0x" .text # print the null-terminated string in %rsi printsz: push %rax; push %rcx mov %rsi, %rdi mov $-1, %ecx xor %al, %al repnz scasb not %ecx dec %ecx # length in %ecx mov %ecx, %edx mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi syscall pop %rcx; pop %rax ret .data dec_buf: .quad 0,0,0 dec_buf_end: .byte '\n' hexdump_buf: .ascii ": " hexdump_buf_hex: .ascii "0000 0000 0000 0000 0000 0000 0000 0000 " hexdump_buf_chars: .ascii "aaaaaaaaaaaaaaaa\n" hexdump_buf_len = . - hexdump_buf .text # Print the value of %rax in decimal. Uses X quadwords of stack. printDec: mov $dec_buf_end, %esi push %rsi # push start ptr mov $10, %ebx # ebx = 10 xor %edx, %edx for_digit_in_num: dec %esi; div %ebx # divide %edx:%eax by %ebx=10, %eax=quotient, %edx=remainder. add $'0', %dl mov %dl, (%rsi) # P cltd # %edx = 0. cmp $0, %eax jnz for_digit_in_num pop %rdx sub %esi, %edx # edx = count mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi syscall ret # write %al as two nibble chars printByte: mov $hex_buf, %rdi call writeByte mov $hex_buf, %esi mov $2, %edx mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi syscall # move %al as two nibble chars to (%rdi) and 0x1(%rdi) writeByte: xor %edx, %edx rol $4, %al mov %al, %dl and $0xF, %dl mov hexaChars(%rdx), %dl mov %dl, (%rdi) rol $4, %al mov %al, %dl and $0xF, %dl mov hexaChars(%rdx), %dl mov %dl, 0x1(%rdi) ret # hexdump starting from %rsi until the end of the page. hexdump_page: push %rsi; mov $nl, %rsi; call printsz; call printsz; call printsz; pop %rsi and $~0xF, %rsi hexdump_loop: call print16;add $16, %rsi mov %esi, %eax and $0xFF0, %eax jnz hexdump_loop ret # Print 16 chars, starting at %rsi, in hexdump format print16: mov %rsi, %r13 mov %rsi, %rax; call printQuad mov %r13, %rsi mov $hexdump_buf_hex, %rdi mov $16, %ecx for_byte_start: mov (%rsi), %al; call writeByte bt $0, %ecx adc $2, %rdi inc %rsi dec %ecx jnz for_byte_start mov %r13, %rsi mov $hexdump_buf_chars, %rdi mov $16, %ecx for_char_start: mov (%rsi), %al; cmp $32, %al jb bad cmp $126, %al ja bad jmp good bad: mov $'.', %al good: mov %al, (%rdi) inc %rdi inc %rsi dec %ecx jnz for_char_start # print the hexdump mov $hexdump_buf, %esi mov $hexdump_buf_len, %edx mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi syscall mov %r13, %rsi ret .data hexaChars: .string "0123456789ABCDEF" hex_buf: .byte 0,0 .text # Print the value of %rax in 16 hexadecimal characters. Uses 6 quadwords of stack. printQuad: push %rbx push %rdx push %rsi push %rdi push %rcx mov $16, %ebx mov $hex_buf, %esi nibbleLoop: rol $4, %rax mov %eax, %edx and $0xF, %edx mov hexaChars(%rdx), %dl mov %dl, (%rsi) # Print the nibble push %rax mov $1, %dl mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi syscall pop %rax dec %ebx jnz nibbleLoop pop %rcx pop %rdi pop %rsi pop %rdx pop %rbx ret .text exit: mov $SYS_EXIT, %eax mov $0, %edi syscall
jared-hughes/defcpu	455	tests/integration/sources/015_call_ret.s	# hole: fibonacci .data stack: .quad 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 stack_top: .quad 0 .text mov $stack_top, %rsp mov $1, %rax call lbl1 mov $5, %rdi print_regs call exit # unreachable: mov $12345, %r12 lbl1: mov $2, %rbx call lbl2 mov $4, %rdx ret # unreachable: mov $23456, %r13 lbl2: mov $3, %rcx ret # unreachable: mov $34567, %r15 exit: # --- Clean exit mov $60, %eax mov $0, %edi syscall
jared-hughes/defcpu	338	tests/integration/sources/004_mov16.s	# hole: fibonacci mov $0x00007FFCA2C2BEEB, %rsp mov $0xBEEF, %ax mov $0xBEEE, %cx mov $0xBEED, %dx mov $0xBEEC, %bx mov $0xBEEB, %sp mov $0xBEEA, %bp mov $0xBEE9, %si mov $0xBEE8, %di mov $0xBEE7, %r8w mov $0xBEE6, %r9w mov $0xBEE5, %r10w mov $0xBEE4, %r11w mov $0xBEE3, %r12w mov $0xBEE2, %r13w mov $0xBEE1, %r14w mov $0xBEE0, %r15w hlt
jared-hughes/defcpu	380	tests/integration/sources/005_mov32.s	# hole: fibonacci mov $0xDEA0BEEF, %eax mov $0xDEA1BEEE, %ecx mov $0xDEA2BEED, %edx mov $0xDEA3BEEC, %ebx mov $0xDEA4BEEB, %esp mov $0xDEA5BEEA, %ebp mov $0xDEA6BEE9, %esi mov $0xDEA7BEE8, %edi mov $0xDEA8BEE7, %r8d mov $0xDEA9BEE6, %r9d mov $0xDEAABEE5, %r10d mov $0xDEABBEE4, %r11d mov $0xDEACBEE3, %r12d mov $0xDEADBEE2, %r13d mov $0xDEAEBEE1, %r14d mov $0xDEAFBEE0, %r15d hlt
jared-hughes/defcpu	275	tests/integration/sources/017_bswap.s	# hole: fibonacci xor %rsp, %rsp mov $0x0102030405060708, %rax mov $0xA1B2C3D4E5F6A7B8, %rbx bswap %rax bswap %rbx print_regs mov $0x0102030405060708, %rax mov $0xA1B2C3D4E5F6A7B8, %rbx bswap %eax bswap %ebx print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall
jared-hughes/defcpu	2,006	tests/integration/sources/012_and_xor.s	# hole: fibonacci .data stack: .quad 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 stack_top: .quad 0 .text mov $stack_top, %rsp # --- 64-bit and mov $0x1122334455667788, %rax mov $0xA1B2C3D4E5F67890, %rbx and %rax, %rbx print_regs # --- 32-bit and push $0x0000000000010ad7; popfq mov $0x11223344, %eax mov $0xA1B2C3D4, %ebx and %eax, %ebx print_regs and $0xA1F3FFE6, %ebx and $0xA1F3FFE6, %eax print_regs # --- 16-bit and push $0x0000000000010ad7; popfq mov $0xA555, %ax mov $0xA1B2, %bx and %ax, %bx print_regs and $0x81F3, %bx and $0xA1F3, %ax print_regs # --- 8-bit and push $0x0000000000010ad7; popfq mov $0x77, %al mov $0xA1, %ah and %al, %ah print_regs and $0x77, %al and $0xF3, %ah print_regs and $0x04, %ah print_regs # --- 64-bit xor mov $0x1122334455667788, %rax mov $0xA1B2C3D4E5F67890, %rbx xor %rax, %rbx print_regs # --- 32-bit xor push $0x0000000000010ad7; popfq mov $0x11223344, %eax mov $0xA1B2C3D4, %ebx xor %eax, %ebx print_regs xor $0xA1F3FFE6, %ebx xor $0xA1F3FFE6, %eax print_regs # --- 16-bit xor push $0x0000000000010ad7; popfq mov $0xA555, %ax mov $0xA1B2, %bx xor %ax, %bx print_regs xor $0x81F3, %bx xor $0xA1F3, %ax print_regs # --- 8-bit xor push $0x0000000000010ad7; popfq mov $0x77, %al mov $0xA1, %ah xor %al, %ah print_regs xor $0x77, %al xor $0xF3, %ah print_regs xor $0x04, %ah print_regs # --- 64-bit or mov $0x1122334455667788, %rax mov $0xA1B2C3D4E5F67890, %rbx or %rax, %rbx print_regs # --- 32-bit or push $0x0000000000010ad7; popfq mov $0x11223344, %eax mov $0xA1B2C3D4, %ebx or %eax, %ebx print_regs or $0xA1F3FFE6, %ebx or $0xA1F3FFE6, %eax print_regs # --- 16-bit or push $0x0000000000010ad7; popfq mov $0xA555, %ax mov $0xA1B2, %bx or %ax, %bx print_regs or $0x81F3, %bx or $0xA1F3, %ax print_regs # --- 8-bit or push $0x0000000000010ad7; popfq mov $0x77, %al mov $0xA1, %ah or %al, %ah print_regs or $0x77, %al or $0xF3, %ah print_regs or $0x04, %ah print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall
jared-hughes/defcpu	402	tests/integration/sources/010_push_pop.s	# hole: fibonacci .data stack: .quad 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 stack_top: .quad 0 .text mov $stack_top, %rsp push $0x123 print_regs pushfq print_regs pop %rax pop %rbx print_regs # TODO: setting the rflags. It's a mess of bus errors and sigtrap currently. # mov $0xFFFFFFFFFFFFFFFFFF, %rbx # push %rbx # popfq # print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall
jared-hughes/defcpu	676	tests/integration/sources/011_div.s	# hole: fibonacci .data stack: .quad 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 stack_top: .quad 0 .text mov $stack_top, %rsp # --- 64-bit div mov $0x123456789ABCDEF0, %rdx mov $0x1122334455667788, %rax mov $0xA1B2C3D4E5F67890, %rcx div %rcx print_regs # --- 32-bit div push $0x0000000000010ad7; popfq mov $0x9ABCDEF0, %edx mov $0x55667788, %eax mov $0xE5F67890, %ecx div %ecx print_regs # --- 16-bit div push $0x0000000000010ad7; popfq mov $0x9ABC, %dx mov $0x5566, %ax mov $0xE5F6, %cx div %cx print_regs # --- 8-bit div push $0x0000000000010ad7; popfq mov $0x9ABC, %ax mov $0xE5, %cl div %ch print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall
jared-hughes/defcpu	281	tests/integration/sources/002_hello_world.s	# hole: fibonacci SYS_WRITE = 1 SYS_EXIT = 60 STDOUT_FILENO = 1 # Printing .data buffer: .string "Hello, World!\n" bufferLen = . - buffer .text mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi mov $buffer, %esi mov $bufferLen, %edx syscall mov $SYS_EXIT, %eax mov $0, %edi syscall
jared-hughes/defcpu	699	tests/integration/sources/008_printnum.s	# hole: fibonacci .comm x, 0xf78000000 mov $0, %rsp # just so test files line up mov $123456789, %eax # SUB: print decimal followed by newline # Requires .comm directive above to let # (-1_i32 as u32) be accessible memory locations mov $10, %bl mov $'\n'-'0', %dl for_digit_in_num: add $'0', %dl dec %esi # first run through the loop: esi = -1 = FFFF_FFFF. # following two can be replaced with xchg %dl, (%rsi) mov %dl, (%rsi) mov $0, %dl cmp %eax, %edx div %ebx jc for_digit_in_num # Actually print the result # sample code to print it mov $1, %al # or pop %eax if the hole is argumentless # %eax = 1. mov %eax, %edi # fd = %rdi # %rdx = 0 # buf = %rsi sub %esi, %edx # cnt = rdx syscall hlt
jared-hughes/defcpu	263	tests/integration/sources/001_mov.s	# hole: fibonacci mov $0x00007FFCD4A9D8F0, %rsp mov $0xDEADBEEF, %ebx mov $0x1023456789ABCDEF, %rax mov $0xF1023456789ABCDE, %rcx mov $0xEF1023456789ABCD, %rdx mov $0xDEF1023456789ABC, %r8 mov $0x12340567, %eax mov $0x1234, %cx mov $0x45, %dl mov $0x23, %dh hlt
jared-hughes/defcpu	12,160	tests/integration/sources/009_add_sub_cmp.s	# hole: fibonacci mov $0, %rsp stc print_regs clc print_regs # --- 64-bit add # plain mov $0x0102030405060708, %rax mov $0xA1B1C1D1E1F1A1B1, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # carry mov $0x6000000000000001, %rax mov $0xA000000000000000, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # overflow and carry mov $0x9000000000000001, %rax mov $0xA000000000000010, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # overflow mov $0x7000000000000007, %rax mov $0x7000000000000000, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # AF flag. mov $0x7000000000000008, %rax mov $0x7000000000000008, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # Zero. mov $0x7FFFFFFFFFFFFFFF, %rax mov $0x8000000000000001, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # --- 32-bit add # plain mov $0x01020304, %eax mov $0xA1B1C1D1, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # carry mov $0x60000001, %eax mov $0xA0000000, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # overflow and carry mov $0x90000001, %eax mov $0xA0000010, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # overflow mov $0x70000007, %eax mov $0x70000000, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # AF flag. mov $0x70000008, %eax mov $0x70000008, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # Zero. mov $0x7FFFFFFF, %eax mov $0x80000001, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # --- 16-bit add # plain mov $0x0102, %ax mov $0xA1B1, %bx mov %ax, %cx add %bx, %cx print_regs # carry mov $0x6001, %ax mov $0xA000, %bx mov %ax, %cx add %bx, %cx print_regs # overflow and carry mov $0x9001, %ax mov $0xA010, %bx mov %ax, %cx add %bx, %cx print_regs # overflow mov $0x7007, %ax mov $0x7000, %bx mov %ax, %cx add %bx, %cx print_regs # AF flag. mov $0x7008, %ax mov $0x7008, %bx mov %ax, %cx add %bx, %cx print_regs # Zero. mov $0x7FFF, %ax mov $0x8001, %bx mov %ax, %cx add %bx, %cx print_regs # --- 8-bit add # plain mov $0x01, %al mov $0xA1, %bl mov %al, %cl add %bl, %cl print_regs # carry mov $0x61, %al mov $0xA0, %bl mov %al, %cl add %bl, %cl print_regs # overflow and carry mov $0x91, %al mov $0xA0, %bl mov %al, %cl add %bl, %cl print_regs # overflow mov $0x77, %al mov $0x70, %bl mov %al, %cl add %bl, %cl print_regs # AF flag. mov $0x78, %al mov $0x78, %bl mov %al, %cl add %bl, %cl print_regs # Zero. mov $0x7F, %al mov $0x81, %bl mov %al, %cl add %bl, %cl print_regs # --- 64-bit adc # plain mov $0x0102030405060708, %rax mov $0xA1B1C1D1E1F1A1B1, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # carry mov $0x6000000000000001, %rax mov $0xA000000000000000, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # overflow and carry mov $0x9000000000000001, %rax mov $0xA000000000000010, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # overflow mov $0x7000000000000007, %rax mov $0x7000000000000000, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # AF flag. mov $0x7000000000000008, %rax mov $0x7000000000000008, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # Zero. mov $0x7FFFFFFFFFFFFFFF, %rax mov $0x8000000000000001, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # --- 32-bit adc # plain mov $0x01020304, %eax mov $0xA1B1C1D1, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # carry mov $0x60000001, %eax mov $0xA0000000, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # overflow and carry mov $0x90000001, %eax mov $0xA0000010, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # overflow mov $0x70000007, %eax mov $0x70000000, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # AF flag. mov $0x70000008, %eax mov $0x70000008, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # Zero. mov $0x7FFFFFFF, %eax mov $0x80000001, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # --- 16-bit adc # plain mov $0x0102, %ax mov $0xA1B1, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # carry mov $0x6001, %ax mov $0xA000, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # overflow and carry mov $0x9001, %ax mov $0xA010, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # overflow mov $0x7007, %ax mov $0x7000, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # AF flag. mov $0x7008, %ax mov $0x7008, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # Zero. mov $0x7FFF, %ax mov $0x8001, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # --- 8-bit adc # plain mov $0x01, %al mov $0xA1, %bl mov %al, %cl stc; adc %bl, %cl print_regs # carry mov $0x61, %al mov $0xA0, %bl mov %al, %cl stc; adc %bl, %cl print_regs # overflow and carry mov $0x91, %al mov $0xA0, %bl mov %al, %cl stc; adc %bl, %cl print_regs # overflow mov $0x77, %al mov $0x70, %bl mov %al, %cl stc; adc %bl, %cl print_regs # AF flag. mov $0x78, %al mov $0x78, %bl mov %al, %cl stc; adc %bl, %cl print_regs # Zero. mov $0x7F, %al mov $0x81, %bl mov %al, %cl stc; adc %bl, %cl print_regs # --- 64-bit sub # plain mov $0xA1B1C1D1E1F1A1B1, %rax mov $0x0102030405060708, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # carry (borrow) mov $0x2000000000000001, %rax mov $0x4000000000000000, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # overflow and carry mov $0x7000000000000007, %rax mov $0xA000000000000000, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # overflow mov $0xA000000000000001, %rax mov $0x7000000000000010, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # AF flag. mov $0x7000000000000007, %rax mov $0x7000000000000008, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # Zero. mov $0x8000000000000001, %rax mov $0x8000000000000001, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # --- 32-bit sub # plain mov $0xA1B1C1D1, %eax mov $0x01020304, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # carry (borrow) mov $0x20000001, %eax mov $0x40000000, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # overflow and carry mov $0x70000007, %eax mov $0xA0000000, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # overflow mov $0xA0000001, %eax mov $0x70000010, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # AF flag. mov $0x70000007, %eax mov $0x70000008, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # Zero. mov $0x80000001, %eax mov $0x80000001, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # --- 16-bit sub # plain mov $0xA1B1, %ax mov $0x0102, %bx mov %ax, %cx sub %bx, %cx print_regs # carry (borrow) mov $0x2001, %ax mov $0x4000, %bx mov %ax, %cx sub %bx, %cx print_regs # overflow and carry mov $0x7007, %ax mov $0xA000, %bx mov %ax, %cx sub %bx, %cx print_regs # overflow mov $0xA001, %ax mov $0x7010, %bx mov %ax, %cx sub %bx, %cx print_regs # AF flag. mov $0x7007, %ax mov $0x7008, %bx mov %ax, %cx sub %bx, %cx print_regs # Zero. mov $0x8001, %ax mov $0x8001, %bx mov %ax, %cx sub %bx, %cx print_regs # --- 8-bit sub # plain mov $0xA1, %al mov $0x01, %bl mov %al, %cl sub %bl, %cl print_regs # carry (borrow) mov $0x21, %al mov $0x40, %bl mov %al, %cl sub %bl, %cl print_regs # overflow and carry mov $0x77, %al mov $0xA0, %bl mov %al, %cl sub %bl, %cl print_regs # overflow mov $0xA1, %al mov $0x70, %bl mov %al, %cl sub %bl, %cl print_regs # AF flag. mov $0x77, %al mov $0x78, %bl mov %al, %cl sub %bl, %cl print_regs # Zero. mov $0x81, %al mov $0x81, %bl mov %al, %cl sub %bl, %cl print_regs # --- 64-bit sbb # plain mov $0xA1B1C1D1E1F1A1B1, %rax mov $0x0102030405060708, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # carry (borrow) mov $0x2000000000000001, %rax mov $0x4000000000000000, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # overflow and carry mov $0x7000000000000007, %rax mov $0xA000000000000000, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # overflow mov $0xA000000000000001, %rax mov $0x7000000000000010, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # AF flag. mov $0x7000000000000007, %rax mov $0x7000000000000008, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # Zero. mov $0x8000000000000001, %rax mov $0x8000000000000001, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # --- 32-bit sbb # plain mov $0xA1B1C1D1, %eax mov $0x01020304, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # carry (borrow) mov $0x20000001, %eax mov $0x40000000, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # overflow and carry mov $0x70000007, %eax mov $0xA0000000, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # overflow mov $0xA0000001, %eax mov $0x70000010, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # AF flag. mov $0x70000007, %eax mov $0x70000008, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # Zero. mov $0x80000001, %eax mov $0x80000001, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # --- 16-bit sbb # plain mov $0xA1B1, %ax mov $0x0102, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # carry (borrow) mov $0x2001, %ax mov $0x4000, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # overflow and carry mov $0x7007, %ax mov $0xA000, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # overflow mov $0xA001, %ax mov $0x7010, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # AF flag. mov $0x7007, %ax mov $0x7008, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # Zero. mov $0x8001, %ax mov $0x8001, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # --- 8-bit sbb # plain mov $0xA1, %al mov $0x01, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # carry (borrow) mov $0x21, %al mov $0x40, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # overflow and carry mov $0x77, %al mov $0xA0, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # overflow mov $0xA1, %al mov $0x70, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # AF flag. mov $0x77, %al mov $0x78, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # Zero. mov $0x81, %al mov $0x81, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # --- 64-bit cmp # plain mov $0xA1B1C1D1E1F1A1B1, %rax mov $0x0102030405060708, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # carry (borrow) mov $0x2000000000000001, %rax mov $0x4000000000000000, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # overflow and carry mov $0x7000000000000007, %rax mov $0xA000000000000000, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # overflow mov $0xA000000000000001, %rax mov $0x7000000000000010, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # AF flag. mov $0x7000000000000007, %rax mov $0x7000000000000008, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # Zero. mov $0x8000000000000001, %rax mov $0x8000000000000001, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # --- 32-bit cmp # plain mov $0xA1B1C1D1, %eax mov $0x01020304, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # carry (borrow) mov $0x20000001, %eax mov $0x40000000, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # overflow and carry mov $0x70000007, %eax mov $0xA0000000, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # overflow mov $0xA0000001, %eax mov $0x70000010, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # AF flag. mov $0x70000007, %eax mov $0x70000008, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # Zero. mov $0x80000001, %eax mov $0x80000001, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # --- 16-bit cmp # plain mov $0xA1B1, %ax mov $0x0102, %bx mov %ax, %cx cmp %bx, %cx print_regs # carry (borrow) mov $0x2001, %ax mov $0x4000, %bx mov %ax, %cx cmp %bx, %cx print_regs # overflow and carry mov $0x7007, %ax mov $0xA000, %bx mov %ax, %cx cmp %bx, %cx print_regs # overflow mov $0xA001, %ax mov $0x7010, %bx mov %ax, %cx cmp %bx, %cx print_regs # AF flag. mov $0x7007, %ax mov $0x7008, %bx mov %ax, %cx cmp %bx, %cx print_regs # Zero. mov $0x8001, %ax mov $0x8001, %bx mov %ax, %cx cmp %bx, %cx print_regs # --- 8-bit cmp # plain mov $0xA1, %al mov $0x01, %bl mov %al, %cl cmp %bl, %cl print_regs # carry (borrow) mov $0x21, %al mov $0x40, %bl mov %al, %cl cmp %bl, %cl print_regs # overflow and carry mov $0x77, %al mov $0xA0, %bl mov %al, %cl cmp %bl, %cl print_regs # overflow mov $0xA1, %al mov $0x70, %bl mov %al, %cl cmp %bl, %cl print_regs # AF flag. mov $0x77, %al mov $0x78, %bl mov %al, %cl cmp %bl, %cl print_regs # Zero. mov $0x81, %al mov $0x81, %bl mov %al, %cl cmp %bl, %cl print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall
jared-hughes/defcpu	381	tests/disassembly/sources/022_lea.s	8d 0c 18 lea (%rax, %rbx, 1), %ecx 8d 4c 18 12 lea 0x12(%rax, %rbx, 1), %ecx 8d 8c 18 12 34 56 78 lea 0x78563412(%rax, %rbx, 1), %ecx 8d 4c 18 82 lea -0x7e(%rax, %rbx, 1), %ecx 8d 8c 18 12 34 56 88 lea -0x77a9cbee(%rax, %rbx, 1), %ecx 8d (bad) f4 hlt
jared-hughes/defcpu	3,872	tests/disassembly/sources/021_rotate.s	c0 01 12 rolb $0x12, (%rcx) 48 c0 01 12 rex.W rolb $0x12, (%rcx) 41 c0 01 12 rolb $0x12, (%r9) c0 c1 12 rol $0x12, %cl c0 09 12 rorb $0x12, (%rcx) 48 c0 09 12 rex.W rorb $0x12, (%rcx) 41 c0 09 12 rorb $0x12, (%r9) c0 c9 12 ror $0x12, %cl c0 11 12 rclb $0x12, (%rcx) 48 c0 11 12 rex.W rclb $0x12, (%rcx) 41 c0 11 12 rclb $0x12, (%r9) c0 d1 12 rcl $0x12, %cl c0 19 12 rcrb $0x12, (%rcx) 48 c0 19 12 rex.W rcrb $0x12, (%rcx) 41 c0 19 12 rcrb $0x12, (%r9) c0 d9 12 rcr $0x12, %cl d0 01 rolb (%rcx) 48 d0 01 rex.W rolb (%rcx) 41 d0 01 rolb (%r9) d0 c1 rol %cl d0 09 rorb (%rcx) 48 d0 09 rex.W rorb (%rcx) 41 d0 09 rorb (%r9) d0 c9 ror %cl d0 11 rclb (%rcx) 48 d0 11 rex.W rclb (%rcx) 41 d0 11 rclb (%r9) d0 d1 rcl %cl d0 19 rcrb (%rcx) 48 d0 19 rex.W rcrb (%rcx) 41 d0 19 rcrb (%r9) d0 d9 rcr %cl c1 01 12 roll $0x12, (%rcx) 66 c1 01 12 rolw $0x12, (%rcx) 67 c1 01 12 roll $0x12, (%ecx) 41 c1 01 12 roll $0x12, (%r9) 48 c1 01 12 rolq $0x12, (%rcx) 49 c1 01 12 rolq $0x12, (%r9) c1 09 12 rorl $0x12, (%rcx) 66 c1 09 12 rorw $0x12, (%rcx) 67 c1 09 12 rorl $0x12, (%ecx) 41 c1 09 12 rorl $0x12, (%r9) 48 c1 09 12 rorq $0x12, (%rcx) 49 c1 09 12 rorq $0x12, (%r9) c1 11 12 rcll $0x12, (%rcx) 66 c1 11 12 rclw $0x12, (%rcx) 67 c1 11 12 rcll $0x12, (%ecx) 41 c1 11 12 rcll $0x12, (%r9) 48 c1 11 12 rclq $0x12, (%rcx) 49 c1 11 12 rclq $0x12, (%r9) c1 19 12 rcrl $0x12, (%rcx) 66 c1 19 12 rcrw $0x12, (%rcx) 67 c1 19 12 rcrl $0x12, (%ecx) 41 c1 19 12 rcrl $0x12, (%r9) 48 c1 19 12 rcrq $0x12, (%rcx) 49 c1 19 12 rcrq $0x12, (%r9) d1 01 roll (%rcx) 66 d1 01 rolw (%rcx) 67 d1 01 roll (%ecx) 41 d1 01 roll (%r9) 48 d1 01 rolq (%rcx) 49 d1 01 rolq (%r9) d1 09 rorl (%rcx) 66 d1 09 rorw (%rcx) 67 d1 09 rorl (%ecx) 41 d1 09 rorl (%r9) 48 d1 09 rorq (%rcx) 49 d1 09 rorq (%r9) d1 11 rcll (%rcx) 66 d1 11 rclw (%rcx) 67 d1 11 rcll (%ecx) 41 d1 11 rcll (%r9) 48 d1 11 rclq (%rcx) 49 d1 11 rclq (%r9) d1 19 rcrl (%rcx) 66 d1 19 rcrw (%rcx) 67 d1 19 rcrl (%ecx) 41 d1 19 rcrl (%r9) 48 d1 19 rcrq (%rcx) 49 d1 19 rcrq (%r9) d2 01 rolb %cl, (%rcx) 66 d2 01 data16 rolb %cl, (%rcx) 67 d2 01 rolb %cl, (%ecx) 41 d2 01 rolb %cl, (%r9) 48 d2 01 rex.W rolb %cl, (%rcx) 49 d2 01 rex.WB rolb %cl, (%r9) d2 09 rorb %cl, (%rcx) 66 d2 09 data16 rorb %cl, (%rcx) 67 d2 09 rorb %cl, (%ecx) 41 d2 09 rorb %cl, (%r9) 48 d2 09 rex.W rorb %cl, (%rcx) 49 d2 09 rex.WB rorb %cl, (%r9) d2 11 rclb %cl, (%rcx) 66 d2 11 data16 rclb %cl, (%rcx) 67 d2 11 rclb %cl, (%ecx) 41 d2 11 rclb %cl, (%r9) 48 d2 11 rex.W rclb %cl, (%rcx) 49 d2 11 rex.WB rclb %cl, (%r9) d2 19 rcrb %cl, (%rcx) 66 d2 19 data16 rcrb %cl, (%rcx) 67 d2 19 rcrb %cl, (%ecx) 41 d2 19 rcrb %cl, (%r9) 48 d2 19 rex.W rcrb %cl, (%rcx) 49 d2 19 rex.WB rcrb %cl, (%r9) d3 01 roll %cl, (%rcx) 66 d3 01 rolw %cl, (%rcx) 67 d3 01 roll %cl, (%ecx) 41 d3 01 roll %cl, (%r9) 48 d3 01 rolq %cl, (%rcx) 49 d3 01 rolq %cl, (%r9) d3 09 rorl %cl, (%rcx) 66 d3 09 rorw %cl, (%rcx) 67 d3 09 rorl %cl, (%ecx) 41 d3 09 rorl %cl, (%r9) 48 d3 09 rorq %cl, (%rcx) 49 d3 09 rorq %cl, (%r9) d3 11 rcll %cl, (%rcx) 66 d3 11 rclw %cl, (%rcx) 67 d3 11 rcll %cl, (%ecx) 41 d3 11 rcll %cl, (%r9) 48 d3 11 rclq %cl, (%rcx) 49 d3 11 rclq %cl, (%r9) d3 19 rcrl %cl, (%rcx) 66 d3 19 rcrw %cl, (%rcx) 67 d3 19 rcrl %cl, (%ecx) 41 d3 19 rcrl %cl, (%r9) 48 d3 19 rcrq %cl, (%rcx) 49 d3 19 rcrq %cl, (%r9)
jared-hughes/defcpu	2,441	tests/disassembly/sources/023_xchg.s	90 nop 91 xchg %eax, %ecx 92 xchg %eax, %edx 93 xchg %eax, %ebx 94 xchg %eax, %esp 95 xchg %eax, %ebp 96 xchg %eax, %esi 97 xchg %eax, %edi 66 90 xchg %ax, %ax 66 91 xchg %ax, %cx 66 92 xchg %ax, %dx 66 93 xchg %ax, %bx 66 94 xchg %ax, %sp 66 95 xchg %ax, %bp 66 96 xchg %ax, %si 66 97 xchg %ax, %di 41 90 xchg %eax, %r8d 41 91 xchg %eax, %r9d 41 92 xchg %eax, %r10d 41 93 xchg %eax, %r11d 41 94 xchg %eax, %r12d 41 95 xchg %eax, %r13d 41 96 xchg %eax, %r14d 41 97 xchg %eax, %r15d 66 41 90 xchg %ax, %r8w 66 41 91 xchg %ax, %r9w 66 41 92 xchg %ax, %r10w 66 41 93 xchg %ax, %r11w 66 41 94 xchg %ax, %r12w 66 41 95 xchg %ax, %r13w 66 41 96 xchg %ax, %r14w 66 41 97 xchg %ax, %r15w 48 90 rex.W nop 48 91 xchg %rax, %rcx 48 92 xchg %rax, %rdx 48 93 xchg %rax, %rbx 48 94 xchg %rax, %rsp 48 95 xchg %rax, %rbp 48 96 xchg %rax, %rsi 48 97 xchg %rax, %rdi 49 90 xchg %rax, %r8 49 91 xchg %rax, %r9 49 92 xchg %rax, %r10 49 93 xchg %rax, %r11 49 94 xchg %rax, %r12 49 95 xchg %rax, %r13 49 96 xchg %rax, %r14 49 97 xchg %rax, %r15 86 13 xchg %dl, (%rbx) 66 48 90 xchg %rax, %rax 66 48 91 data16 xchg %rax, %rcx 66 48 92 data16 xchg %rax, %rdx 66 48 93 data16 xchg %rax, %rbx 66 48 94 data16 xchg %rax, %rsp 66 48 95 data16 xchg %rax, %rbp 66 48 96 data16 xchg %rax, %rsi 66 48 97 data16 xchg %rax, %rdi 66 49 90 xchg %rax, %r8 66 49 91 data16 xchg %rax, %r9 66 49 92 data16 xchg %rax, %r10 66 49 93 data16 xchg %rax, %r11 66 49 94 data16 xchg %rax, %r12 66 49 95 data16 xchg %rax, %r13 66 49 96 data16 xchg %rax, %r14 66 49 97 data16 xchg %rax, %r15 86 13 xchg %dl, (%rbx) 66 86 13 data16 xchg %dl, (%rbx) 67 86 13 xchg %dl, (%ebx) 40 86 13 rex xchg %dl, (%rbx) 41 86 13 xchg %dl, (%r11) 48 86 13 rex.W xchg %dl, (%rbx) 49 86 13 rex.WB xchg %dl, (%r11) 87 13 xchg %edx, (%rbx) 66 87 13 xchg %dx, (%rbx) 67 87 13 xchg %edx, (%ebx) 40 87 13 rex xchg %edx, (%rbx) 41 87 13 xchg %edx, (%r11) 48 87 13 xchg %rdx, (%rbx) 49 87 13 xchg %rdx, (%r11)
jared-hughes/defcpu	16,420	tests/disassembly/sources/010_fuzz_prefix_mov.s	88 b8 67 66 4f 66 mov %bh, 0x664f6667(%rax) bf 4a 67 8a 88 mov $0x888a674a, %edi b8 4c 67 b0 b8 mov $0xb8b0674c, %eax c6 40 c6 67 movb $0x67, -0x3a(%rax) 66 c6 data16 (bad) 88 c6 mov %al, %dh 88 66 66 mov %ah, 0x66(%rsi) 66 40 data16 rex 47 rex.RXB 4f 8a b3 4c c7 c6 67 rex.WRXB mov 0x67c6c74c(%r11), %r14b c7 c6 47 67 66 bf mov $0xbf666747, %esi 66 c6 c7 88 data16 mov $0x88, %bh 4c c7 rex.WR (bad) 66 66 67 66 67 c7 40 66 c6 4a data16 data16 addr32 movw $0x4ac6, 0x66(%eax) 88 40 67 mov %al, 0x67(%rax) 8a 4f 4a mov 0x4a(%rdi), %cl 66 88 c6 data16 mov %al, %dh 47 b8 4a 47 c7 b3 rex.RXB mov $0xb3c7474a, %r8d 66 66 67 4a data16 data16 addr32 rex.WX 4c rex.WR 4f b0 4a rex.WRXB mov $0x4a, %r8b 8a 4c b3 8a mov -0x76(%rbx, %rsi, 4), %cl b0 66 mov $0x66, %al 88 4c 67 66 mov %cl, 0x66(%rdi, %riz, 2) b9 c7 4c c6 b3 mov $0xb3c64cc7, %ecx 4f rex.WRXB 66 b8 c6 40 mov $0x40c6, %ax 40 rex 66 b0 bf data16 mov $0xbf, %al b8 4f c6 66 c6 mov $0xc666c64f, %eax b3 40 mov $0x40, %bl 47 c6 rex.RXB (bad) 67 66 66 b8 8a 40 addr32 data16 mov $0x408a, %ax c6 (bad) 67 bf 8a b3 b3 c7 addr32 mov $0xc7b3b38a, %edi c6 (bad) 4c rex.WR 67 47 b3 67 addr32 rex.RXB mov $0x67, %r11b 88 66 67 mov %ah, 0x67(%rsi) 66 b3 c6 data16 mov $0xc6, %bl 4a rex.WX 67 c7 addr32 (bad) b8 67 4a 88 47 mov $0x47884a67, %eax 66 66 88 66 67 data16 data16 mov %ah, 0x67(%rsi) 4c rex.WR 67 b9 67 47 8a c7 addr32 mov $0xc78a4767, %ecx 40 rex 4a rex.WX 67 c7 addr32 (bad) b0 c7 mov $0xc7, %al 88 8a 67 c6 c7 66 mov %cl, 0x66c7c667(%rdx) b3 c6 mov $0xc6, %bl 4c 88 b9 66 47 c7 67 rex.WR mov %r15b, 0x67c74766(%rcx) 8a 67 b0 mov -0x50(%rdi), %ah 67 4f bf 67 66 c6 66 4a 40 c7 66 addr32 rex.WRXB movabs $0x66c7404a66c66667, %r15 66 66 47 b8 4f 4a data16 rex.RXB mov $0x4a4f, %r8w 40 rex 40 88 66 c7 mov %spl, -0x39(%rsi) 67 67 b8 4a c7 67 67 addr32 addr32 mov $0x6767c74a, %eax 4f 8a b0 66 4f 4c c6 rex.WRXB mov -0x39b3b09a(%r8), %r14b b0 67 mov $0x67, %al c6 47 4c 88 movb $0x88, 0x4c(%rdi) 88 4f c6 mov %cl, -0x3a(%rdi) b0 c7 mov $0xc7, %al c7 (bad) 67 b3 c7 addr32 mov $0xc7, %bl 66 bf c6 66 mov $0x66c6, %di c7 (bad) b8 b8 8a 67 47 mov $0x47678ab8, %eax 40 rex 66 8a 4f 66 data16 mov 0x66(%rdi), %cl c7 (bad) b9 4c 66 c7 c7 mov $0xc7c7664c, %ecx 66 4a data16 rex.WX 66 66 8a 88 b3 b0 b0 67 data16 data16 mov 0x67b0b0b3(%rax), %cl 4c rex.WR 66 b0 8a data16 mov $0x8a, %al b3 66 mov $0x66, %bl b0 4c mov $0x4c, %al b9 4a b3 b3 88 mov $0x88b3b34a, %ecx b0 67 mov $0x67, %al 8a 8a b0 b9 c7 4c mov 0x4cc7b9b0(%rdx), %cl b9 b3 b0 67 4c mov $0x4c67b0b3, %ecx c6 (bad) 66 c6 data16 (bad) 4f rex.WRXB 47 rex.RXB 47 c6 rex.RXB (bad) 8a 88 40 8a b9 c6 mov -0x394675c0(%rax), %cl 40 bf b8 4a 67 66 rex mov $0x66674ab8, %edi 88 66 67 mov %ah, 0x67(%rsi) c6 (bad) b3 b8 mov $0xb8, %bl 8a 66 40 mov 0x40(%rsi), %ah b8 b8 4c b8 40 mov $0x40b84cb8, %eax bf 88 88 b3 4c mov $0x4cb38888, %edi 4c rex.WR 66 40 b8 c7 66 rex mov $0x66c7, %ax 4c rex.WR 4c rex.WR 4a rex.WX 67 b8 8a b0 b0 8a addr32 mov $0x8ab0b08a, %eax 4a c6 c7 4c rex.WX mov $0x4c, %dil 67 4c c7 addr32 rex.WR (bad) 67 4a 88 88 b3 4f 67 8a rex.WX mov %cl, -0x7598b04d(%eax) 4f rex.WRXB 47 rex.RXB 67 bf 66 88 c7 4f addr32 mov $0x4fc78866, %edi 66 66 47 data16 data16 rex.RXB 47 rex.RXB 40 rex 47 rex.RXB 4c b9 4c 67 47 c6 4a 88 b9 8a rex.WR movabs $0x8ab9884ac647674c, %rcx 66 67 b9 4c 66 addr32 mov $0x664c, %cx 4a rex.WX 66 c7 data16 (bad) 8a bf 66 4a 88 66 mov 0x66884a66(%rdi), %bh b8 4a 47 8a c7 mov $0xc78a474a, %eax 88 40 66 mov %al, 0x66(%rax) 8a 67 b8 mov -0x48(%rdi), %ah 66 b9 40 bf mov $0xbf40, %cx 66 4f data16 rex.WRXB 67 40 c7 addr32 rex (bad) 66 67 c7 data16 addr32 (bad) 67 4a addr32 rex.WX 67 47 addr32 rex.RXB 4a rex.WX 67 88 66 88 mov %ah, -0x78(%esi) b8 67 8a b3 67 mov $0x67b38a67, %eax 67 88 66 4c mov %ah, 0x4c(%esi) 66 67 88 88 b8 b3 88 88 data16 mov %cl, -0x77774c48(%eax) 67 66 67 67 40 addr32 data16 addr32 addr32 rex 67 4c addr32 rex.WR 66 67 b0 4a data16 addr32 mov $0x4a, %al 66 66 c6 data16 data16 (bad) 67 bf 4f b9 4c 67 addr32 mov $0x674cb94f, %edi 88 b8 b8 c7 bf c6 mov %bh, -0x39403848(%rax) 67 66 c6 addr32 data16 (bad) b0 c7 mov $0xc7, %al 67 4c addr32 rex.WR 4a bf b0 88 8a 66 c6 67 c7 c7 rex.WX movabs $0xc7c767c6668a88b0, %rdi 8a 8a 47 88 c6 4a mov 0x4ac68847(%rdx), %cl 67 b0 66 addr32 mov $0x66, %al 4c rex.WR 66 4a data16 rex.WX 67 40 addr32 rex 4c rex.WR 4f rex.WRXB 67 66 c6 47 8a c7 data16 movb $0xc7, -0x76(%edi) 67 b9 67 67 b3 8a addr32 mov $0x8ab36767, %ecx 4f 8a c6 rex.WRXB mov %r14b, %r8b 67 67 66 66 67 67 b3 66 addr32 addr32 data16 data16 addr32 addr32 mov $0x66, %bl c7 (bad) b8 c7 66 b3 66 mov $0x66b366c7, %eax 4a rex.WX 67 bf 4a 66 8a 8a addr32 mov $0x8a8a664a, %edi c7 (bad) bf 88 c7 4c 66 mov $0x664cc788, %edi 67 4f 8a 88 8a bf 66 66 rex.WRXB mov 0x6666bf8a(%r8d), %r9b 67 4f c6 addr32 rex.WRXB (bad) bf 67 c6 b8 40 mov $0x40b8c667, %edi b0 66 mov $0x66, %al 67 4a b3 66 addr32 rex.WX mov $0x66, %bl b0 c7 mov $0xc7, %al bf c7 47 88 4f mov $0x4f8847c7, %edi 67 66 c6 addr32 data16 (bad) b0 4f mov $0x4f, %al 88 66 8a mov %ah, -0x76(%rsi) 66 bf b3 88 mov $0x88b3, %di 4a b0 40 rex.WX mov $0x40, %al c7 c6 67 8a 67 40 mov $0x40678a67, %esi 67 c7 c7 67 88 88 b9 addr32 mov $0xb9888867, %edi c6 (bad) 66 b0 47 data16 mov $0x47, %al 66 b3 4c data16 mov $0x4c, %bl 67 66 66 c7 addr32 data16 data16 (bad) 8a 8a 66 c7 8a 4a mov 0x4a8ac766(%rdx), %cl bf b0 67 bf 66 mov $0x66bf67b0, %edi 66 4a data16 rex.WX 40 c6 rex (bad) b3 b3 mov $0xb3, %bl 66 bf 67 67 mov $0x6767, %di c6 (bad) 4f rex.WRXB 67 67 67 40 addr32 addr32 addr32 rex 4c rex.WR 67 c7 addr32 (bad) 66 88 88 c6 40 67 66 data16 mov %cl, 0x666740c6(%rax) 4f b3 c6 rex.WRXB mov $0xc6, %r11b 66 b9 bf c7 mov $0xc7bf, %cx 8a b3 67 c7 c7 8a mov -0x75383899(%rbx), %dh 4f rex.WRXB 67 40 addr32 rex 67 4f addr32 rex.WRXB 67 88 8a c6 66 bf b9 mov %cl, -0x4640993a(%edx) b8 47 8a 8a 8a mov $0x8a8a8a47, %eax 66 66 67 b8 c7 67 data16 addr32 mov $0x67c7, %ax b0 4a mov $0x4a, %al 66 c6 40 b9 8a data16 movb $0x8a, -0x47(%rax) 88 67 47 mov %ah, 0x47(%rdi) 66 4a data16 rex.WX 66 88 c6 data16 mov %al, %dh 47 rex.RXB 66 67 67 66 4a data16 addr32 addr32 data16 rex.WX 66 bf b9 88 mov $0x88b9, %di 66 67 b9 67 67 addr32 mov $0x6767, %cx b0 66 mov $0x66, %al b0 bf mov $0xbf, %al 4a rex.WX 4f c6 rex.WRXB (bad) 66 4c data16 rex.WR 40 rex 66 4a data16 rex.WX 66 c6 data16 (bad) 88 67 67 mov %ah, 0x67(%rdi) b0 c7 mov $0xc7, %al c6 (bad) 4c rex.WR 47 c6 rex.RXB (bad) 88 c6 mov %al, %dh 88 66 40 mov %ah, 0x40(%rsi) 66 b3 4f data16 mov $0x4f, %bl 8a b3 88 67 c6 bf mov -0x40399878(%rbx), %dh 66 b9 67 c6 mov $0xc667, %cx 8a 8a 88 40 66 b0 mov -0x4f99bf78(%rdx), %cl 67 66 88 67 67 data16 mov %ah, 0x67(%edi) 88 c7 mov %al, %bh b0 88 mov $0x88, %al c6 c7 47 mov $0x47, %bh 40 rex 67 c6 addr32 (bad) bf bf 66 88 66 mov $0x668866bf, %edi 67 88 67 4c mov %ah, 0x4c(%edi) c7 (bad) 88 8a c6 66 4c b9 mov %cl, -0x46b3993a(%rdx) 47 c7 c6 b9 67 88 8a rex.RXB mov $0x8a8867b9, %r14d 4a rex.WX 67 88 4c 67 66 mov %cl, 0x66(%edi, %eiz, 2) 66 b3 8a data16 mov $0x8a, %bl 66 b8 4a 66 mov $0x664a, %ax 67 c6 addr32 (bad) 4a 8a 47 b3 rex.WX mov -0x4d(%rdi), %al b3 4a mov $0x4a, %bl 66 88 b8 47 67 8a 66 data16 mov %bh, 0x668a6747(%rax) c6 (bad) 66 4c 8a 8a bf 67 4f c6 data16 rex.WR mov -0x39b09841(%rdx), %r9b 88 66 66 mov %ah, 0x66(%rsi) 67 8a 67 b9 mov -0x47(%edi), %ah c6 (bad) 8a c7 mov %bh, %al c7 (bad) 8a b9 67 bf 8a c7 mov -0x38754099(%rcx), %bh 88 40 b3 mov %al, -0x4d(%rax) b0 b9 mov $0xb9, %al c6 (bad) 8a 4c 4c 88 mov -0x78(%rsp, %rcx, 2), %cl c7 c7 c6 67 4c c7 mov $0xc74c67c6, %edi 8a 66 b3 mov -0x4d(%rsi), %ah b0 b8 mov $0xb8, %al 4f b9 8a c6 88 b0 8a 47 b3 8a rex.WRXB movabs $0x8ab3478ab088c68a, %r9 4a c6 rex.WX (bad) 67 88 c6 addr32 mov %al, %dh b3 4c mov $0x4c, %bl b3 c6 mov $0xc6, %bl 66 c7 data16 (bad) b0 66 mov $0x66, %al 66 4a data16 rex.WX 67 8a c6 addr32 mov %dh, %al 88 8a c7 67 67 c7 mov %cl, -0x38989839(%rdx) 66 66 c6 data16 data16 (bad) 67 c6 c6 67 addr32 mov $0x67, %dh 67 8a 4c c7 67 mov 0x67(%edi, %eax, 8), %cl c6 (bad) 67 47 b3 66 addr32 rex.RXB mov $0x66, %r11b 67 c7 40 b8 67 c7 8a 4c movl $0x4c8ac767, -0x48(%eax) 67 88 66 88 mov %ah, -0x78(%esi) 67 67 88 8a 40 66 66 bf addr32 mov %cl, -0x409999c0(%edx) 47 b3 4c rex.RXB mov $0x4c, %r11b 4c rex.WR 4c c7 rex.WR (bad) bf 67 4a 8a 67 mov $0x678a4a67, %edi c7 40 88 c6 66 66 4c movl $0x4c6666c6, -0x78(%rax) 66 47 data16 rex.RXB 47 c7 rex.RXB (bad) 66 66 b9 67 66 data16 mov $0x6667, %cx 66 66 c6 c6 bf data16 data16 mov $0xbf, %dh c6 (bad) 66 8a b3 b0 66 88 c6 data16 mov -0x39779950(%rbx), %dh bf 66 88 66 67 mov $0x67668866, %edi c6 (bad) 4c rex.WR 66 66 4f c6 00 00 data16 data16 rex.WRXB movb $0x0, (%r8)
jared-hughes/defcpu	14,596	tests/disassembly/sources/012_inc_dec_div_not.s	fe 00 incb (%rax) fe 04 f4 incb (%rsp, %rsi, 8) fe 05 f4 f4 f4 f4 incb -0xb0b0b0c(%rip) fe 06 incb (%rsi) fe 40 f4 incb -0xc(%rax) fe c3 inc %bl fe c4 inc %ah 41 fe 00 incb (%r8) 41 fe 04 12 incb (%r10, %rdx, 1) 41 fe 05 12 34 56 78 incb 0x78563412(%rip) 41 fe 06 incb (%r14) ff 00 incl (%rax) ff 04 f4 incl (%rsp, %rsi, 8) ff 05 f4 f4 f4 f4 incl -0xb0b0b0c(%rip) ff 06 incl (%rsi) ff 40 f4 incl -0xc(%rax) ff c3 inc %ebx ff c4 inc %esp 41 ff 00 incl (%r8) 41 ff 04 12 incl (%r10, %rdx, 1) 41 ff 05 12 34 56 78 incl 0x78563412(%rip) 41 ff 06 incl (%r14) 66 ff 00 incw (%rax) 66 ff 04 f4 incw (%rsp, %rsi, 8) 66 ff 05 f4 f4 f4 f4 incw -0xb0b0b0c(%rip) 66 ff 06 incw (%rsi) 66 ff 40 f4 incw -0xc(%rax) 66 ff c3 inc %bx 66 ff c4 inc %sp 66 41 ff 00 incw (%r8) 66 41 ff 04 12 incw (%r10, %rdx, 1) 66 41 ff 05 12 34 56 78 incw 0x78563412(%rip) 66 41 ff 06 incw (%r14) 67 ff 00 incl (%eax) 67 ff 04 f4 incl (%esp, %esi, 8) 67 ff 05 f4 f4 f4 f4 incl -0xb0b0b0c(%eip) 67 ff 06 incl (%esi) 67 ff 40 f4 incl -0xc(%eax) 67 ff c3 addr32 inc %ebx 67 ff c4 addr32 inc %esp 67 41 ff 00 incl (%r8d) 67 41 ff 04 12 incl (%r10d, %edx, 1) 67 41 ff 05 12 34 56 78 incl 0x78563412(%eip) 67 41 ff 06 incl (%r14d) 66 67 ff 00 incw (%eax) 66 67 ff 04 f4 incw (%esp, %esi, 8) 66 67 ff 05 f4 f4 f4 f4 incw -0xb0b0b0c(%eip) 66 67 ff 06 incw (%esi) 66 67 ff 40 f4 incw -0xc(%eax) 66 67 ff c3 addr32 inc %bx 66 67 ff c4 addr32 inc %sp 66 67 41 ff 00 incw (%r8d) 66 67 41 ff 04 12 incw (%r10d, %edx, 1) 66 67 41 ff 05 12 34 56 78 incw 0x78563412(%eip) 66 67 41 ff 06 incw (%r14d) 66 67 48 ff 00 data16 incq (%eax) 66 67 48 ff 04 f4 data16 incq (%esp, %esi, 8) 66 67 48 ff 05 f4 f4 f4 f4 data16 incq -0xb0b0b0c(%eip) 48 ff 06 incq (%rsi) 48 ff 40 f4 incq -0xc(%rax) 48 ff c3 inc %rbx 48 ff c4 inc %rsp 49 ff 00 incq (%r8) 49 ff 04 f4 incq (%r12, %rsi, 8) 49 ff 05 f4 f4 f4 f4 incq -0xb0b0b0c(%rip) 49 ff 06 incq (%r14) 49 ff 40 f4 incq -0xc(%r8) 49 ff c3 inc %r11 49 ff c4 inc %r12 67 48 ff 06 incq (%esi) 67 48 ff 40 f4 incq -0xc(%eax) 67 48 ff c3 addr32 inc %rbx 67 48 ff c4 addr32 inc %rsp 67 49 ff 00 incq (%r8d) 67 49 ff 04 f4 incq (%r12d, %esi, 8) 67 49 ff 05 f4 f4 f4 f4 incq -0xb0b0b0c(%eip) 67 49 ff 06 incq (%r14d) 67 49 ff 40 f4 incq -0xc(%r8d) 67 49 ff c3 addr32 inc %r11 67 49 ff c4 addr32 inc %r12 fe 08 decb (%rax) fe 0c f4 decb (%rsp, %rsi, 8) fe 0d f4 f4 f4 f4 decb -0xb0b0b0c(%rip) fe 0e decb (%rsi) fe 48 f4 decb -0xc(%rax) fe cb dec %bl fe cc dec %ah 41 fe 08 decb (%r8) 41 fe 0c 12 decb (%r10, %rdx, 1) 41 fe 0d 12 34 56 78 decb 0x78563412(%rip) 41 fe 0e decb (%r14) ff 08 decl (%rax) ff 0c f4 decl (%rsp, %rsi, 8) ff 0d f4 f4 f4 f4 decl -0xb0b0b0c(%rip) ff 0e decl (%rsi) ff 48 f4 decl -0xc(%rax) ff cb dec %ebx ff cc dec %esp 41 ff 08 decl (%r8) 41 ff 0c 12 decl (%r10, %rdx, 1) 41 ff 0d 12 34 56 78 decl 0x78563412(%rip) 41 ff 0e decl (%r14) 66 ff 08 decw (%rax) 66 ff 0c f4 decw (%rsp, %rsi, 8) 66 ff 0d f4 f4 f4 f4 decw -0xb0b0b0c(%rip) 66 ff 0e decw (%rsi) 66 ff 48 f4 decw -0xc(%rax) 66 ff cb dec %bx 66 ff cc dec %sp 66 41 ff 08 decw (%r8) 66 41 ff 0c 12 decw (%r10, %rdx, 1) 66 41 ff 0d 12 34 56 78 decw 0x78563412(%rip) 66 41 ff 0e decw (%r14) 67 ff 08 decl (%eax) 67 ff 0c f4 decl (%esp, %esi, 8) 67 ff 0d f4 f4 f4 f4 decl -0xb0b0b0c(%eip) 67 ff 0e decl (%esi) 67 ff 48 f4 decl -0xc(%eax) 67 ff cb addr32 dec %ebx 67 ff cc addr32 dec %esp 67 41 ff 08 decl (%r8d) 67 41 ff 0c 12 decl (%r10d, %edx, 1) 67 41 ff 0d 12 34 56 78 decl 0x78563412(%eip) 67 41 ff 0e decl (%r14d) 66 67 ff 08 decw (%eax) 66 67 ff 0c f4 decw (%esp, %esi, 8) 66 67 ff 0d f4 f4 f4 f4 decw -0xb0b0b0c(%eip) 66 67 ff 0e decw (%esi) 66 67 ff 48 f4 decw -0xc(%eax) 66 67 ff cb addr32 dec %bx 66 67 ff cc addr32 dec %sp 66 67 41 ff 08 decw (%r8d) 66 67 41 ff 0c 12 decw (%r10d, %edx, 1) 66 67 41 ff 0d 12 34 56 78 decw 0x78563412(%eip) 66 67 41 ff 0e decw (%r14d) 66 67 48 ff 08 data16 decq (%eax) 66 67 48 ff 0c f4 data16 decq (%esp, %esi, 8) 66 67 48 ff 0d f4 f4 f4 f4 data16 decq -0xb0b0b0c(%eip) 48 ff 0e decq (%rsi) 48 ff 48 f4 decq -0xc(%rax) 48 ff cb dec %rbx 48 ff cc dec %rsp 49 ff 08 decq (%r8) 49 ff 0c f4 decq (%r12, %rsi, 8) 49 ff 0d f4 f4 f4 f4 decq -0xb0b0b0c(%rip) 49 ff 0e decq (%r14) 49 ff 48 f4 decq -0xc(%r8) 49 ff cb dec %r11 49 ff cc dec %r12 67 48 ff 0e decq (%esi) 67 48 ff 48 f4 decq -0xc(%eax) 67 48 ff cb addr32 dec %rbx 67 48 ff cc addr32 dec %rsp 67 49 ff 08 decq (%r8d) 67 49 ff 0c f4 decq (%r12d, %esi, 8) 67 49 ff 0d f4 f4 f4 f4 decq -0xb0b0b0c(%eip) 67 49 ff 0e decq (%r14d) 67 49 ff 48 f4 decq -0xc(%r8d) 67 49 ff cb addr32 dec %r11 67 49 ff cc addr32 dec %r12 f6 30 divb (%rax) f6 34 f4 divb (%rsp, %rsi, 8) f6 35 f4 f4 f4 f4 divb -0xb0b0b0c(%rip) f6 36 divb (%rsi) f6 70 f4 divb -0xc(%rax) f6 f3 div %bl f6 f4 div %ah 41 f6 30 divb (%r8) 41 f6 34 12 divb (%r10, %rdx, 1) 41 f6 35 12 34 56 78 divb 0x78563412(%rip) 41 f6 36 divb (%r14) f7 30 divl (%rax) f7 34 f4 divl (%rsp, %rsi, 8) f7 35 f4 f4 f4 f4 divl -0xb0b0b0c(%rip) f7 36 divl (%rsi) f7 70 f4 divl -0xc(%rax) f7 f3 div %ebx f7 f4 div %esp 41 f7 30 divl (%r8) 41 f7 34 12 divl (%r10, %rdx, 1) 41 f7 35 12 34 56 78 divl 0x78563412(%rip) 41 f7 36 divl (%r14) 66 f7 30 divw (%rax) 66 f7 34 f4 divw (%rsp, %rsi, 8) 66 f7 35 f4 f4 f4 f4 divw -0xb0b0b0c(%rip) 66 f7 36 divw (%rsi) 66 f7 70 f4 divw -0xc(%rax) 66 f7 f3 div %bx 66 f7 f4 div %sp 66 41 f7 30 divw (%r8) 66 41 f7 34 12 divw (%r10, %rdx, 1) 66 41 f7 35 12 34 56 78 divw 0x78563412(%rip) 66 41 f7 36 divw (%r14) 67 f7 30 divl (%eax) 67 f7 34 f4 divl (%esp, %esi, 8) 67 f7 35 f4 f4 f4 f4 divl -0xb0b0b0c(%eip) 67 f7 36 divl (%esi) 67 f7 70 f4 divl -0xc(%eax) 67 f7 f3 addr32 div %ebx 67 f7 f4 addr32 div %esp 67 41 f7 30 divl (%r8d) 67 41 f7 34 12 divl (%r10d, %edx, 1) 67 41 f7 35 12 34 56 78 divl 0x78563412(%eip) 67 41 f7 36 divl (%r14d) 66 67 f7 30 divw (%eax) 66 67 f7 34 f4 divw (%esp, %esi, 8) 66 67 f7 35 f4 f4 f4 f4 divw -0xb0b0b0c(%eip) 66 67 f7 36 divw (%esi) 66 67 f7 70 f4 divw -0xc(%eax) 66 67 f7 f3 addr32 div %bx 66 67 f7 f4 addr32 div %sp 66 67 41 f7 30 divw (%r8d) 66 67 41 f7 34 12 divw (%r10d, %edx, 1) 66 67 41 f7 35 12 34 56 78 divw 0x78563412(%eip) 66 67 41 f7 36 divw (%r14d) 66 67 48 f7 30 data16 divq (%eax) 66 67 48 f7 34 f4 data16 divq (%esp, %esi, 8) 66 67 48 f7 35 f4 f4 f4 f4 data16 divq -0xb0b0b0c(%eip) 48 f7 36 divq (%rsi) 48 f7 70 f4 divq -0xc(%rax) 48 f7 f3 div %rbx 48 f7 f4 div %rsp 49 f7 30 divq (%r8) 49 f7 34 f4 divq (%r12, %rsi, 8) 49 f7 35 f4 f4 f4 f4 divq -0xb0b0b0c(%rip) 49 f7 36 divq (%r14) 49 f7 70 f4 divq -0xc(%r8) 49 f7 f3 div %r11 49 f7 f4 div %r12 67 48 f7 36 divq (%esi) 67 48 f7 70 f4 divq -0xc(%eax) 67 48 f7 f3 addr32 div %rbx 67 48 f7 f4 addr32 div %rsp 67 49 f7 30 divq (%r8d) 67 49 f7 34 f4 divq (%r12d, %esi, 8) 67 49 f7 35 f4 f4 f4 f4 divq -0xb0b0b0c(%eip) 67 49 f7 36 divq (%r14d) 67 49 f7 70 f4 divq -0xc(%r8d) 67 49 f7 f3 addr32 div %r11 67 49 f7 f4 addr32 div %r12 f6 10 notb (%rax) f6 14 f4 notb (%rsp, %rsi, 8) f6 15 f4 f4 f4 f4 notb -0xb0b0b0c(%rip) f6 16 notb (%rsi) f6 50 f4 notb -0xc(%rax) f6 d3 not %bl f6 d4 not %ah 41 f6 10 notb (%r8) 41 f6 14 12 notb (%r10, %rdx, 1) 41 f6 15 12 34 56 78 notb 0x78563412(%rip) 41 f6 16 notb (%r14) f7 10 notl (%rax) f7 14 f4 notl (%rsp, %rsi, 8) f7 15 f4 f4 f4 f4 notl -0xb0b0b0c(%rip) f7 16 notl (%rsi) f7 50 f4 notl -0xc(%rax) f7 d3 not %ebx f7 d4 not %esp 41 f7 10 notl (%r8) 41 f7 14 12 notl (%r10, %rdx, 1) 41 f7 15 12 34 56 78 notl 0x78563412(%rip) 41 f7 16 notl (%r14) 66 f7 10 notw (%rax) 66 f7 14 f4 notw (%rsp, %rsi, 8) 66 f7 15 f4 f4 f4 f4 notw -0xb0b0b0c(%rip) 66 f7 16 notw (%rsi) 66 f7 50 f4 notw -0xc(%rax) 66 f7 d3 not %bx 66 f7 d4 not %sp 66 41 f7 10 notw (%r8) 66 41 f7 14 12 notw (%r10, %rdx, 1) 66 41 f7 15 12 34 56 78 notw 0x78563412(%rip) 66 41 f7 16 notw (%r14) 67 f7 10 notl (%eax) 67 f7 14 f4 notl (%esp, %esi, 8) 67 f7 15 f4 f4 f4 f4 notl -0xb0b0b0c(%eip) 67 f7 16 notl (%esi) 67 f7 50 f4 notl -0xc(%eax) 67 f7 d3 addr32 not %ebx 67 f7 d4 addr32 not %esp 67 41 f7 10 notl (%r8d) 67 41 f7 14 12 notl (%r10d, %edx, 1) 67 41 f7 15 12 34 56 78 notl 0x78563412(%eip) 67 41 f7 16 notl (%r14d) 66 67 f7 10 notw (%eax) 66 67 f7 14 f4 notw (%esp, %esi, 8) 66 67 f7 15 f4 f4 f4 f4 notw -0xb0b0b0c(%eip) 66 67 f7 16 notw (%esi) 66 67 f7 50 f4 notw -0xc(%eax) 66 67 f7 d3 addr32 not %bx 66 67 f7 d4 addr32 not %sp 66 67 41 f7 10 notw (%r8d) 66 67 41 f7 14 12 notw (%r10d, %edx, 1) 66 67 41 f7 15 12 34 56 78 notw 0x78563412(%eip) 66 67 41 f7 16 notw (%r14d) 66 67 48 f7 10 data16 notq (%eax) 66 67 48 f7 14 f4 data16 notq (%esp, %esi, 8) 66 67 48 f7 15 f4 f4 f4 f4 data16 notq -0xb0b0b0c(%eip) 48 f7 16 notq (%rsi) 48 f7 50 f4 notq -0xc(%rax) 48 f7 d3 not %rbx 48 f7 d4 not %rsp 49 f7 10 notq (%r8) 49 f7 14 f4 notq (%r12, %rsi, 8) 49 f7 15 f4 f4 f4 f4 notq -0xb0b0b0c(%rip) 49 f7 16 notq (%r14) 49 f7 50 f4 notq -0xc(%r8) 49 f7 d3 not %r11 49 f7 d4 not %r12 67 48 f7 16 notq (%esi) 67 48 f7 50 f4 notq -0xc(%eax) 67 48 f7 d3 addr32 not %rbx 67 48 f7 d4 addr32 not %rsp 67 49 f7 10 notq (%r8d) 67 49 f7 14 f4 notq (%r12d, %esi, 8) 67 49 f7 15 f4 f4 f4 f4 notq -0xb0b0b0c(%eip) 67 49 f7 16 notq (%r14d) 67 49 f7 50 f4 notq -0xc(%r8d) 67 49 f7 d3 addr32 not %r11 67 49 f7 d4 addr32 not %r12
jared-hughes/defcpu	38,137	tests/disassembly/sources/013_add_and_sub_cmp_xor_bt.s	04 12 add $0x12, %al 66 05 12 34 add $0x3412, %ax 05 12 34 56 78 add $0x78563412, %eax 41 05 12 34 56 78 rex.B add $0x78563412, %eax 41 05 12 34 56 88 rex.B add $0x88563412, %eax 48 05 12 34 56 78 add $0x78563412, %rax 48 05 12 34 56 88 add $0xffffffff88563412, %rax 49 05 12 34 56 78 rex.WB add $0x78563412, %rax 49 05 12 34 56 88 rex.WB add $0xffffffff88563412, %rax 80 c0 12 add $0x12, %al 80 c6 12 add $0x12, %dh 40 80 c6 12 add $0x12, %sil 66 81 c6 12 34 add $0x3412, %si 81 c6 12 34 56 78 add $0x78563412, %esi 48 81 c6 12 34 56 78 add $0x78563412, %rsi 48 81 c6 12 34 56 88 add $0xffffffff88563412, %rsi 66 83 c6 12 add $0x12, %si 66 83 c6 82 add $0xff82, %si 83 c6 12 add $0x12, %esi 83 c6 82 add $0xffffff82, %esi 41 83 c6 12 add $0x12, %r14d 41 83 c6 82 add $0xffffff82, %r14d 48 83 c6 12 add $0x12, %rsi 48 83 c6 82 add $0xffffffffffffff82, %rsi 49 83 c6 12 add $0x12, %r14 49 83 c6 82 add $0xffffffffffffff82, %r14 00 23 add %ah, (%rbx) 66 00 23 data16 add %ah, (%rbx) 67 00 23 add %ah, (%ebx) 66 67 00 23 data16 add %ah, (%ebx) 40 00 23 add %spl, (%rbx) 67 40 00 23 add %spl, (%ebx) 66 40 00 23 data16 add %spl, (%rbx) 66 67 40 00 23 data16 add %spl, (%ebx) 41 00 23 add %spl, (%r11) 67 41 00 23 add %spl, (%r11d) 66 41 00 23 data16 add %spl, (%r11) 66 67 41 00 23 data16 add %spl, (%r11d) 48 00 23 rex.W add %spl, (%rbx) 67 48 00 23 rex.W add %spl, (%ebx) 66 48 00 23 data16 rex.W add %spl, (%rbx) 66 67 48 00 23 data16 rex.W add %spl, (%ebx) 01 23 add %esp, (%rbx) 66 01 23 add %sp, (%rbx) 67 01 23 add %esp, (%ebx) 66 67 01 23 add %sp, (%ebx) 40 01 23 rex add %esp, (%rbx) 67 40 01 23 rex add %esp, (%ebx) 66 40 01 23 rex add %sp, (%rbx) 66 67 40 01 23 rex add %sp, (%ebx) 41 01 23 add %esp, (%r11) 67 41 01 23 add %esp, (%r11d) 66 41 01 23 add %sp, (%r11) 66 67 41 01 23 add %sp, (%r11d) 48 01 23 add %rsp, (%rbx) 67 48 01 23 add %rsp, (%ebx) 66 48 01 23 data16 add %rsp, (%rbx) 66 67 48 01 23 data16 add %rsp, (%ebx) 02 23 add (%rbx), %ah 66 02 23 data16 add (%rbx), %ah 67 02 23 add (%ebx), %ah 66 67 02 23 data16 add (%ebx), %ah 40 02 23 add (%rbx), %spl 67 40 02 23 add (%ebx), %spl 66 40 02 23 data16 add (%rbx), %spl 66 67 40 02 23 data16 add (%ebx), %spl 41 02 23 add (%r11), %spl 67 41 02 23 add (%r11d), %spl 66 41 02 23 data16 add (%r11), %spl 66 67 41 02 23 data16 add (%r11d), %spl 48 02 23 rex.W add (%rbx), %spl 67 48 02 23 rex.W add (%ebx), %spl 66 48 02 23 data16 rex.W add (%rbx), %spl 66 67 48 02 23 data16 rex.W add (%ebx), %spl 03 23 add (%rbx), %esp 66 03 23 add (%rbx), %sp 67 03 23 add (%ebx), %esp 66 67 03 23 add (%ebx), %sp 40 03 23 rex add (%rbx), %esp 67 40 03 23 rex add (%ebx), %esp 66 40 03 23 rex add (%rbx), %sp 66 67 40 03 23 rex add (%ebx), %sp 41 03 23 add (%r11), %esp 67 41 03 23 add (%r11d), %esp 66 41 03 23 add (%r11), %sp 66 67 41 03 23 add (%r11d), %sp 48 03 23 add (%rbx), %rsp 67 48 03 23 add (%ebx), %rsp 0c 12 or $0x12, %al 66 0d 12 34 or $0x3412, %ax 0d 12 34 56 78 or $0x78563412, %eax 41 0d 12 34 56 78 rex.B or $0x78563412, %eax 41 0d 12 34 56 88 rex.B or $0x88563412, %eax 48 0d 12 34 56 78 or $0x78563412, %rax 48 0d 12 34 56 88 or $0xffffffff88563412, %rax 49 0d 12 34 56 78 rex.WB or $0x78563412, %rax 49 0d 12 34 56 88 rex.WB or $0xffffffff88563412, %rax 80 c8 12 or $0x12, %al 80 ce 12 or $0x12, %dh 40 80 ce 12 or $0x12, %sil 66 81 ce 12 34 or $0x3412, %si 81 ce 12 34 56 78 or $0x78563412, %esi 48 81 ce 12 34 56 78 or $0x78563412, %rsi 48 81 ce 12 34 56 88 or $0xffffffff88563412, %rsi 66 83 ce 12 or $0x12, %si 66 83 ce 82 or $0xff82, %si 83 ce 12 or $0x12, %esi 83 ce 82 or $0xffffff82, %esi 41 83 ce 12 or $0x12, %r14d 41 83 ce 82 or $0xffffff82, %r14d 48 83 ce 12 or $0x12, %rsi 48 83 ce 82 or $0xffffffffffffff82, %rsi 49 83 ce 12 or $0x12, %r14 49 83 ce 82 or $0xffffffffffffff82, %r14 08 23 or %ah, (%rbx) 66 08 23 data16 or %ah, (%rbx) 67 08 23 or %ah, (%ebx) 66 67 08 23 data16 or %ah, (%ebx) 40 08 23 or %spl, (%rbx) 67 40 08 23 or %spl, (%ebx) 66 40 08 23 data16 or %spl, (%rbx) 66 67 40 08 23 data16 or %spl, (%ebx) 41 08 23 or %spl, (%r11) 67 41 08 23 or %spl, (%r11d) 66 41 08 23 data16 or %spl, (%r11) 66 67 41 08 23 data16 or %spl, (%r11d) 48 08 23 rex.W or %spl, (%rbx) 67 48 08 23 rex.W or %spl, (%ebx) 66 48 08 23 data16 rex.W or %spl, (%rbx) 66 67 48 08 23 data16 rex.W or %spl, (%ebx) 09 23 or %esp, (%rbx) 66 09 23 or %sp, (%rbx) 67 09 23 or %esp, (%ebx) 66 67 09 23 or %sp, (%ebx) 40 09 23 rex or %esp, (%rbx) 67 40 09 23 rex or %esp, (%ebx) 66 40 09 23 rex or %sp, (%rbx) 66 67 40 09 23 rex or %sp, (%ebx) 41 09 23 or %esp, (%r11) 67 41 09 23 or %esp, (%r11d) 66 41 09 23 or %sp, (%r11) 66 67 41 09 23 or %sp, (%r11d) 48 09 23 or %rsp, (%rbx) 67 48 09 23 or %rsp, (%ebx) 66 48 09 23 data16 or %rsp, (%rbx) 66 67 48 09 23 data16 or %rsp, (%ebx) 0a 23 or (%rbx), %ah 66 0a 23 data16 or (%rbx), %ah 67 0a 23 or (%ebx), %ah 66 67 0a 23 data16 or (%ebx), %ah 40 0a 23 or (%rbx), %spl 67 40 0a 23 or (%ebx), %spl 66 40 0a 23 data16 or (%rbx), %spl 66 67 40 0a 23 data16 or (%ebx), %spl 41 0a 23 or (%r11), %spl 67 41 0a 23 or (%r11d), %spl 66 41 0a 23 data16 or (%r11), %spl 66 67 41 0a 23 data16 or (%r11d), %spl 48 0a 23 rex.W or (%rbx), %spl 67 48 0a 23 rex.W or (%ebx), %spl 66 48 0a 23 data16 rex.W or (%rbx), %spl 66 67 48 0a 23 data16 rex.W or (%ebx), %spl 0b 23 or (%rbx), %esp 66 0b 23 or (%rbx), %sp 67 0b 23 or (%ebx), %esp 66 67 0b 23 or (%ebx), %sp 40 0b 23 rex or (%rbx), %esp 67 40 0b 23 rex or (%ebx), %esp 66 40 0b 23 rex or (%rbx), %sp 66 67 40 0b 23 rex or (%ebx), %sp 41 0b 23 or (%r11), %esp 67 41 0b 23 or (%r11d), %esp 66 41 0b 23 or (%r11), %sp 66 67 41 0b 23 or (%r11d), %sp 48 0b 23 or (%rbx), %rsp 67 48 0b 23 or (%ebx), %rsp 14 12 adc $0x12, %al 66 15 12 34 adc $0x3412, %ax 15 12 34 56 78 adc $0x78563412, %eax 41 15 12 34 56 78 rex.B adc $0x78563412, %eax 41 15 12 34 56 88 rex.B adc $0x88563412, %eax 48 15 12 34 56 78 adc $0x78563412, %rax 48 15 12 34 56 88 adc $0xffffffff88563412, %rax 49 15 12 34 56 78 rex.WB adc $0x78563412, %rax 49 15 12 34 56 88 rex.WB adc $0xffffffff88563412, %rax 80 d0 12 adc $0x12, %al 80 d6 12 adc $0x12, %dh 40 80 d6 12 adc $0x12, %sil 66 81 d6 12 34 adc $0x3412, %si 81 d6 12 34 56 78 adc $0x78563412, %esi 48 81 d6 12 34 56 78 adc $0x78563412, %rsi 48 81 d6 12 34 56 88 adc $0xffffffff88563412, %rsi 66 83 d6 12 adc $0x12, %si 66 83 d6 82 adc $0xff82, %si 83 d6 12 adc $0x12, %esi 83 d6 82 adc $0xffffff82, %esi 41 83 d6 12 adc $0x12, %r14d 41 83 d6 82 adc $0xffffff82, %r14d 48 83 d6 12 adc $0x12, %rsi 48 83 d6 82 adc $0xffffffffffffff82, %rsi 49 83 d6 12 adc $0x12, %r14 49 83 d6 82 adc $0xffffffffffffff82, %r14 10 23 adc %ah, (%rbx) 66 10 23 data16 adc %ah, (%rbx) 67 10 23 adc %ah, (%ebx) 66 67 10 23 data16 adc %ah, (%ebx) 40 10 23 adc %spl, (%rbx) 67 40 10 23 adc %spl, (%ebx) 66 40 10 23 data16 adc %spl, (%rbx) 66 67 40 10 23 data16 adc %spl, (%ebx) 41 10 23 adc %spl, (%r11) 67 41 10 23 adc %spl, (%r11d) 66 41 10 23 data16 adc %spl, (%r11) 66 67 41 10 23 data16 adc %spl, (%r11d) 48 10 23 rex.W adc %spl, (%rbx) 67 48 10 23 rex.W adc %spl, (%ebx) 66 48 10 23 data16 rex.W adc %spl, (%rbx) 66 67 48 10 23 data16 rex.W adc %spl, (%ebx) 11 23 adc %esp, (%rbx) 66 11 23 adc %sp, (%rbx) 67 11 23 adc %esp, (%ebx) 66 67 11 23 adc %sp, (%ebx) 40 11 23 rex adc %esp, (%rbx) 67 40 11 23 rex adc %esp, (%ebx) 66 40 11 23 rex adc %sp, (%rbx) 66 67 40 11 23 rex adc %sp, (%ebx) 41 11 23 adc %esp, (%r11) 67 41 11 23 adc %esp, (%r11d) 66 41 11 23 adc %sp, (%r11) 66 67 41 11 23 adc %sp, (%r11d) 48 11 23 adc %rsp, (%rbx) 67 48 11 23 adc %rsp, (%ebx) 66 48 11 23 data16 adc %rsp, (%rbx) 66 67 48 11 23 data16 adc %rsp, (%ebx) 12 23 adc (%rbx), %ah 66 12 23 data16 adc (%rbx), %ah 67 12 23 adc (%ebx), %ah 66 67 12 23 data16 adc (%ebx), %ah 40 12 23 adc (%rbx), %spl 67 40 12 23 adc (%ebx), %spl 66 40 12 23 data16 adc (%rbx), %spl 66 67 40 12 23 data16 adc (%ebx), %spl 41 12 23 adc (%r11), %spl 67 41 12 23 adc (%r11d), %spl 66 41 12 23 data16 adc (%r11), %spl 66 67 41 12 23 data16 adc (%r11d), %spl 48 12 23 rex.W adc (%rbx), %spl 67 48 12 23 rex.W adc (%ebx), %spl 66 48 12 23 data16 rex.W adc (%rbx), %spl 66 67 48 12 23 data16 rex.W adc (%ebx), %spl 13 23 adc (%rbx), %esp 66 13 23 adc (%rbx), %sp 67 13 23 adc (%ebx), %esp 66 67 13 23 adc (%ebx), %sp 40 13 23 rex adc (%rbx), %esp 67 40 13 23 rex adc (%ebx), %esp 66 40 13 23 rex adc (%rbx), %sp 66 67 40 13 23 rex adc (%ebx), %sp 41 13 23 adc (%r11), %esp 67 41 13 23 adc (%r11d), %esp 66 41 13 23 adc (%r11), %sp 66 67 41 13 23 adc (%r11d), %sp 48 13 23 adc (%rbx), %rsp 67 48 13 23 adc (%ebx), %rsp 1c 12 sbb $0x12, %al 66 1d 12 34 sbb $0x3412, %ax 1d 12 34 56 78 sbb $0x78563412, %eax 41 1d 12 34 56 78 rex.B sbb $0x78563412, %eax 41 1d 12 34 56 88 rex.B sbb $0x88563412, %eax 48 1d 12 34 56 78 sbb $0x78563412, %rax 48 1d 12 34 56 88 sbb $0xffffffff88563412, %rax 49 1d 12 34 56 78 rex.WB sbb $0x78563412, %rax 49 1d 12 34 56 88 rex.WB sbb $0xffffffff88563412, %rax 80 d8 12 sbb $0x12, %al 80 de 12 sbb $0x12, %dh 40 80 de 12 sbb $0x12, %sil 66 81 de 12 34 sbb $0x3412, %si 81 de 12 34 56 78 sbb $0x78563412, %esi 48 81 de 12 34 56 78 sbb $0x78563412, %rsi 48 81 de 12 34 56 88 sbb $0xffffffff88563412, %rsi 66 83 de 12 sbb $0x12, %si 66 83 de 82 sbb $0xff82, %si 83 de 12 sbb $0x12, %esi 83 de 82 sbb $0xffffff82, %esi 41 83 de 12 sbb $0x12, %r14d 41 83 de 82 sbb $0xffffff82, %r14d 48 83 de 12 sbb $0x12, %rsi 48 83 de 82 sbb $0xffffffffffffff82, %rsi 49 83 de 12 sbb $0x12, %r14 49 83 de 82 sbb $0xffffffffffffff82, %r14 18 23 sbb %ah, (%rbx) 66 18 23 data16 sbb %ah, (%rbx) 67 18 23 sbb %ah, (%ebx) 66 67 18 23 data16 sbb %ah, (%ebx) 40 18 23 sbb %spl, (%rbx) 67 40 18 23 sbb %spl, (%ebx) 66 40 18 23 data16 sbb %spl, (%rbx) 66 67 40 18 23 data16 sbb %spl, (%ebx) 41 18 23 sbb %spl, (%r11) 67 41 18 23 sbb %spl, (%r11d) 66 41 18 23 data16 sbb %spl, (%r11) 66 67 41 18 23 data16 sbb %spl, (%r11d) 48 18 23 rex.W sbb %spl, (%rbx) 67 48 18 23 rex.W sbb %spl, (%ebx) 66 48 18 23 data16 rex.W sbb %spl, (%rbx) 66 67 48 18 23 data16 rex.W sbb %spl, (%ebx) 19 23 sbb %esp, (%rbx) 66 19 23 sbb %sp, (%rbx) 67 19 23 sbb %esp, (%ebx) 66 67 19 23 sbb %sp, (%ebx) 40 19 23 rex sbb %esp, (%rbx) 67 40 19 23 rex sbb %esp, (%ebx) 66 40 19 23 rex sbb %sp, (%rbx) 66 67 40 19 23 rex sbb %sp, (%ebx) 41 19 23 sbb %esp, (%r11) 67 41 19 23 sbb %esp, (%r11d) 66 41 19 23 sbb %sp, (%r11) 66 67 41 19 23 sbb %sp, (%r11d) 48 19 23 sbb %rsp, (%rbx) 67 48 19 23 sbb %rsp, (%ebx) 66 48 19 23 data16 sbb %rsp, (%rbx) 66 67 48 19 23 data16 sbb %rsp, (%ebx) 1a 23 sbb (%rbx), %ah 66 1a 23 data16 sbb (%rbx), %ah 67 1a 23 sbb (%ebx), %ah 66 67 1a 23 data16 sbb (%ebx), %ah 40 1a 23 sbb (%rbx), %spl 67 40 1a 23 sbb (%ebx), %spl 66 40 1a 23 data16 sbb (%rbx), %spl 66 67 40 1a 23 data16 sbb (%ebx), %spl 41 1a 23 sbb (%r11), %spl 67 41 1a 23 sbb (%r11d), %spl 66 41 1a 23 data16 sbb (%r11), %spl 66 67 41 1a 23 data16 sbb (%r11d), %spl 48 1a 23 rex.W sbb (%rbx), %spl 67 48 1a 23 rex.W sbb (%ebx), %spl 66 48 1a 23 data16 rex.W sbb (%rbx), %spl 66 67 48 1a 23 data16 rex.W sbb (%ebx), %spl 1b 23 sbb (%rbx), %esp 66 1b 23 sbb (%rbx), %sp 67 1b 23 sbb (%ebx), %esp 66 67 1b 23 sbb (%ebx), %sp 40 1b 23 rex sbb (%rbx), %esp 67 40 1b 23 rex sbb (%ebx), %esp 66 40 1b 23 rex sbb (%rbx), %sp 66 67 40 1b 23 rex sbb (%ebx), %sp 41 1b 23 sbb (%r11), %esp 67 41 1b 23 sbb (%r11d), %esp 66 41 1b 23 sbb (%r11), %sp 66 67 41 1b 23 sbb (%r11d), %sp 48 1b 23 sbb (%rbx), %rsp 67 48 1b 23 sbb (%ebx), %rsp 24 12 and $0x12, %al 66 25 12 34 and $0x3412, %ax 25 12 34 56 78 and $0x78563412, %eax 41 25 12 34 56 78 rex.B and $0x78563412, %eax 41 25 12 34 56 88 rex.B and $0x88563412, %eax 48 25 12 34 56 78 and $0x78563412, %rax 48 25 12 34 56 88 and $0xffffffff88563412, %rax 49 25 12 34 56 78 rex.WB and $0x78563412, %rax 49 25 12 34 56 88 rex.WB and $0xffffffff88563412, %rax 80 e0 12 and $0x12, %al 80 e6 12 and $0x12, %dh 40 80 e6 12 and $0x12, %sil 66 81 e6 12 34 and $0x3412, %si 81 e6 12 34 56 78 and $0x78563412, %esi 48 81 e6 12 34 56 78 and $0x78563412, %rsi 48 81 e6 12 34 56 88 and $0xffffffff88563412, %rsi 66 83 e6 12 and $0x12, %si 66 83 e6 82 and $0xff82, %si 83 e6 12 and $0x12, %esi 83 e6 82 and $0xffffff82, %esi 41 83 e6 12 and $0x12, %r14d 41 83 e6 82 and $0xffffff82, %r14d 48 83 e6 12 and $0x12, %rsi 48 83 e6 82 and $0xffffffffffffff82, %rsi 49 83 e6 12 and $0x12, %r14 49 83 e6 82 and $0xffffffffffffff82, %r14 20 23 and %ah, (%rbx) 66 20 23 data16 and %ah, (%rbx) 67 20 23 and %ah, (%ebx) 66 67 20 23 data16 and %ah, (%ebx) 40 20 23 and %spl, (%rbx) 67 40 20 23 and %spl, (%ebx) 66 40 20 23 data16 and %spl, (%rbx) 66 67 40 20 23 data16 and %spl, (%ebx) 41 20 23 and %spl, (%r11) 67 41 20 23 and %spl, (%r11d) 66 41 20 23 data16 and %spl, (%r11) 66 67 41 20 23 data16 and %spl, (%r11d) 48 20 23 rex.W and %spl, (%rbx) 67 48 20 23 rex.W and %spl, (%ebx) 66 48 20 23 data16 rex.W and %spl, (%rbx) 66 67 48 20 23 data16 rex.W and %spl, (%ebx) 21 23 and %esp, (%rbx) 66 21 23 and %sp, (%rbx) 67 21 23 and %esp, (%ebx) 66 67 21 23 and %sp, (%ebx) 40 21 23 rex and %esp, (%rbx) 67 40 21 23 rex and %esp, (%ebx) 66 40 21 23 rex and %sp, (%rbx) 66 67 40 21 23 rex and %sp, (%ebx) 41 21 23 and %esp, (%r11) 67 41 21 23 and %esp, (%r11d) 66 41 21 23 and %sp, (%r11) 66 67 41 21 23 and %sp, (%r11d) 48 21 23 and %rsp, (%rbx) 67 48 21 23 and %rsp, (%ebx) 66 48 21 23 data16 and %rsp, (%rbx) 66 67 48 21 23 data16 and %rsp, (%ebx) 22 23 and (%rbx), %ah 66 22 23 data16 and (%rbx), %ah 67 22 23 and (%ebx), %ah 66 67 22 23 data16 and (%ebx), %ah 40 22 23 and (%rbx), %spl 67 40 22 23 and (%ebx), %spl 66 40 22 23 data16 and (%rbx), %spl 66 67 40 22 23 data16 and (%ebx), %spl 41 22 23 and (%r11), %spl 67 41 22 23 and (%r11d), %spl 66 41 22 23 data16 and (%r11), %spl 66 67 41 22 23 data16 and (%r11d), %spl 48 22 23 rex.W and (%rbx), %spl 67 48 22 23 rex.W and (%ebx), %spl 66 48 22 23 data16 rex.W and (%rbx), %spl 66 67 48 22 23 data16 rex.W and (%ebx), %spl 23 23 and (%rbx), %esp 66 23 23 and (%rbx), %sp 67 23 23 and (%ebx), %esp 66 67 23 23 and (%ebx), %sp 40 23 23 rex and (%rbx), %esp 67 40 23 23 rex and (%ebx), %esp 66 40 23 23 rex and (%rbx), %sp 66 67 40 23 23 rex and (%ebx), %sp 41 23 23 and (%r11), %esp 67 41 23 23 and (%r11d), %esp 66 41 23 23 and (%r11), %sp 66 67 41 23 23 and (%r11d), %sp 48 23 23 and (%rbx), %rsp 67 48 23 23 and (%ebx), %rsp 66 48 23 23 data16 and (%rbx), %rsp 66 67 48 23 23 data16 and (%ebx), %rsp 2c 12 sub $0x12, %al 66 2d 12 34 sub $0x3412, %ax 2d 12 34 56 78 sub $0x78563412, %eax 41 2d 12 34 56 78 rex.B sub $0x78563412, %eax 41 2d 12 34 56 88 rex.B sub $0x88563412, %eax 48 2d 12 34 56 78 sub $0x78563412, %rax 48 2d 12 34 56 88 sub $0xffffffff88563412, %rax 49 2d 12 34 56 78 rex.WB sub $0x78563412, %rax 49 2d 12 34 56 88 rex.WB sub $0xffffffff88563412, %rax 80 e8 12 sub $0x12, %al 80 ee 12 sub $0x12, %dh 40 80 ee 12 sub $0x12, %sil 66 81 ee 12 34 sub $0x3412, %si 81 ee 12 34 56 78 sub $0x78563412, %esi 48 81 ee 12 34 56 78 sub $0x78563412, %rsi 48 81 ee 12 34 56 88 sub $0xffffffff88563412, %rsi 66 83 ee 12 sub $0x12, %si 66 83 ee 82 sub $0xff82, %si 83 ee 12 sub $0x12, %esi 83 ee 82 sub $0xffffff82, %esi 41 83 ee 12 sub $0x12, %r14d 41 83 ee 82 sub $0xffffff82, %r14d 48 83 ee 12 sub $0x12, %rsi 48 83 ee 82 sub $0xffffffffffffff82, %rsi 49 83 ee 12 sub $0x12, %r14 49 83 ee 82 sub $0xffffffffffffff82, %r14 28 23 sub %ah, (%rbx) 66 28 23 data16 sub %ah, (%rbx) 67 28 23 sub %ah, (%ebx) 66 67 28 23 data16 sub %ah, (%ebx) 40 28 23 sub %spl, (%rbx) 67 40 28 23 sub %spl, (%ebx) 66 40 28 23 data16 sub %spl, (%rbx) 66 67 40 28 23 data16 sub %spl, (%ebx) 41 28 23 sub %spl, (%r11) 67 41 28 23 sub %spl, (%r11d) 66 41 28 23 data16 sub %spl, (%r11) 66 67 41 28 23 data16 sub %spl, (%r11d) 48 28 23 rex.W sub %spl, (%rbx) 67 48 28 23 rex.W sub %spl, (%ebx) 66 48 28 23 data16 rex.W sub %spl, (%rbx) 66 67 48 28 23 data16 rex.W sub %spl, (%ebx) 29 23 sub %esp, (%rbx) 66 29 23 sub %sp, (%rbx) 67 29 23 sub %esp, (%ebx) 66 67 29 23 sub %sp, (%ebx) 40 29 23 rex sub %esp, (%rbx) 67 40 29 23 rex sub %esp, (%ebx) 66 40 29 23 rex sub %sp, (%rbx) 66 67 40 29 23 rex sub %sp, (%ebx) 41 29 23 sub %esp, (%r11) 67 41 29 23 sub %esp, (%r11d) 66 41 29 23 sub %sp, (%r11) 66 67 41 29 23 sub %sp, (%r11d) 48 29 23 sub %rsp, (%rbx) 67 48 29 23 sub %rsp, (%ebx) 66 48 29 23 data16 sub %rsp, (%rbx) 66 67 48 29 23 data16 sub %rsp, (%ebx) 2a 23 sub (%rbx), %ah 66 2a 23 data16 sub (%rbx), %ah 67 2a 23 sub (%ebx), %ah 66 67 2a 23 data16 sub (%ebx), %ah 40 2a 23 sub (%rbx), %spl 67 40 2a 23 sub (%ebx), %spl 66 40 2a 23 data16 sub (%rbx), %spl 66 67 40 2a 23 data16 sub (%ebx), %spl 41 2a 23 sub (%r11), %spl 67 41 2a 23 sub (%r11d), %spl 66 41 2a 23 data16 sub (%r11), %spl 66 67 41 2a 23 data16 sub (%r11d), %spl 48 2a 23 rex.W sub (%rbx), %spl 67 48 2a 23 rex.W sub (%ebx), %spl 66 48 2a 23 data16 rex.W sub (%rbx), %spl 66 67 48 2a 23 data16 rex.W sub (%ebx), %spl 2b 23 sub (%rbx), %esp 66 2b 23 sub (%rbx), %sp 67 2b 23 sub (%ebx), %esp 66 67 2b 23 sub (%ebx), %sp 40 2b 23 rex sub (%rbx), %esp 67 40 2b 23 rex sub (%ebx), %esp 66 40 2b 23 rex sub (%rbx), %sp 66 67 40 2b 23 rex sub (%ebx), %sp 41 2b 23 sub (%r11), %esp 67 41 2b 23 sub (%r11d), %esp 66 41 2b 23 sub (%r11), %sp 66 67 41 2b 23 sub (%r11d), %sp 48 2b 23 sub (%rbx), %rsp 67 48 2b 23 sub (%ebx), %rsp 66 48 2b 23 data16 sub (%rbx), %rsp 66 67 48 2b 23 data16 sub (%ebx), %rsp 3c 12 cmp $0x12, %al 66 3d 12 34 cmp $0x3412, %ax 3d 12 34 56 78 cmp $0x78563412, %eax 41 3d 12 34 56 78 rex.B cmp $0x78563412, %eax 41 3d 12 34 56 88 rex.B cmp $0x88563412, %eax 48 3d 12 34 56 78 cmp $0x78563412, %rax 48 3d 12 34 56 88 cmp $0xffffffff88563412, %rax 49 3d 12 34 56 78 rex.WB cmp $0x78563412, %rax 49 3d 12 34 56 88 rex.WB cmp $0xffffffff88563412, %rax 80 f8 12 cmp $0x12, %al 80 fe 12 cmp $0x12, %dh 40 80 fe 12 cmp $0x12, %sil 66 81 fe 12 34 cmp $0x3412, %si 81 fe 12 34 56 78 cmp $0x78563412, %esi 48 81 fe 12 34 56 78 cmp $0x78563412, %rsi 48 81 fe 12 34 56 88 cmp $0xffffffff88563412, %rsi 66 83 fe 12 cmp $0x12, %si 66 83 fe 82 cmp $0xff82, %si 83 fe 12 cmp $0x12, %esi 83 fe 82 cmp $0xffffff82, %esi 41 83 fe 12 cmp $0x12, %r14d 41 83 fe 82 cmp $0xffffff82, %r14d 48 83 fe 12 cmp $0x12, %rsi 48 83 fe 82 cmp $0xffffffffffffff82, %rsi 49 83 fe 12 cmp $0x12, %r14 49 83 fe 82 cmp $0xffffffffffffff82, %r14 38 23 cmp %ah, (%rbx) 66 38 23 data16 cmp %ah, (%rbx) 67 38 23 cmp %ah, (%ebx) 66 67 38 23 data16 cmp %ah, (%ebx) 40 38 23 cmp %spl, (%rbx) 67 40 38 23 cmp %spl, (%ebx) 66 40 38 23 data16 cmp %spl, (%rbx) 66 67 40 38 23 data16 cmp %spl, (%ebx) 41 38 23 cmp %spl, (%r11) 67 41 38 23 cmp %spl, (%r11d) 66 41 38 23 data16 cmp %spl, (%r11) 66 67 41 38 23 data16 cmp %spl, (%r11d) 48 38 23 rex.W cmp %spl, (%rbx) 67 48 38 23 rex.W cmp %spl, (%ebx) 66 48 38 23 data16 rex.W cmp %spl, (%rbx) 66 67 48 38 23 data16 rex.W cmp %spl, (%ebx) 39 23 cmp %esp, (%rbx) 66 39 23 cmp %sp, (%rbx) 67 39 23 cmp %esp, (%ebx) 66 67 39 23 cmp %sp, (%ebx) 40 39 23 rex cmp %esp, (%rbx) 67 40 39 23 rex cmp %esp, (%ebx) 66 40 39 23 rex cmp %sp, (%rbx) 66 67 40 39 23 rex cmp %sp, (%ebx) 41 39 23 cmp %esp, (%r11) 67 41 39 23 cmp %esp, (%r11d) 66 41 39 23 cmp %sp, (%r11) 66 67 41 39 23 cmp %sp, (%r11d) 48 39 23 cmp %rsp, (%rbx) 67 48 39 23 cmp %rsp, (%ebx) 66 48 39 23 data16 cmp %rsp, (%rbx) 66 67 48 39 23 data16 cmp %rsp, (%ebx) 3a 23 cmp (%rbx), %ah 66 3a 23 data16 cmp (%rbx), %ah 67 3a 23 cmp (%ebx), %ah 66 67 3a 23 data16 cmp (%ebx), %ah 40 3a 23 cmp (%rbx), %spl 67 40 3a 23 cmp (%ebx), %spl 66 40 3a 23 data16 cmp (%rbx), %spl 66 67 40 3a 23 data16 cmp (%ebx), %spl 41 3a 23 cmp (%r11), %spl 67 41 3a 23 cmp (%r11d), %spl 66 41 3a 23 data16 cmp (%r11), %spl 66 67 41 3a 23 data16 cmp (%r11d), %spl 48 3a 23 rex.W cmp (%rbx), %spl 67 48 3a 23 rex.W cmp (%ebx), %spl 66 48 3a 23 data16 rex.W cmp (%rbx), %spl 66 67 48 3a 23 data16 rex.W cmp (%ebx), %spl 3b 23 cmp (%rbx), %esp 66 3b 23 cmp (%rbx), %sp 67 3b 23 cmp (%ebx), %esp 66 67 3b 23 cmp (%ebx), %sp 40 3b 23 rex cmp (%rbx), %esp 67 40 3b 23 rex cmp (%ebx), %esp 66 40 3b 23 rex cmp (%rbx), %sp 66 67 40 3b 23 rex cmp (%ebx), %sp 41 3b 23 cmp (%r11), %esp 67 41 3b 23 cmp (%r11d), %esp 66 41 3b 23 cmp (%r11), %sp 66 67 41 3b 23 cmp (%r11d), %sp 48 3b 23 cmp (%rbx), %rsp 67 48 3b 23 cmp (%ebx), %rsp 66 48 3b 23 data16 cmp (%rbx), %rsp 66 67 48 3b 23 data16 cmp (%ebx), %rsp 34 12 xor $0x12, %al 66 35 12 34 xor $0x3412, %ax 35 12 34 56 78 xor $0x78563412, %eax 41 35 12 34 56 78 rex.B xor $0x78563412, %eax 41 35 12 34 56 88 rex.B xor $0x88563412, %eax 48 35 12 34 56 78 xor $0x78563412, %rax 48 35 12 34 56 88 xor $0xffffffff88563412, %rax 49 35 12 34 56 78 rex.WB xor $0x78563412, %rax 49 35 12 34 56 88 rex.WB xor $0xffffffff88563412, %rax 80 f0 12 xor $0x12, %al 80 f6 12 xor $0x12, %dh 40 80 f6 12 xor $0x12, %sil 66 81 f6 12 34 xor $0x3412, %si 81 f6 12 34 56 78 xor $0x78563412, %esi 48 81 f6 12 34 56 78 xor $0x78563412, %rsi 48 81 f6 12 34 56 88 xor $0xffffffff88563412, %rsi 66 83 f6 12 xor $0x12, %si 66 83 f6 82 xor $0xff82, %si 83 f6 12 xor $0x12, %esi 83 f6 82 xor $0xffffff82, %esi 41 83 f6 12 xor $0x12, %r14d 41 83 f6 82 xor $0xffffff82, %r14d 48 83 f6 12 xor $0x12, %rsi 48 83 f6 82 xor $0xffffffffffffff82, %rsi 49 83 f6 12 xor $0x12, %r14 49 83 f6 82 xor $0xffffffffffffff82, %r14 30 23 xor %ah, (%rbx) 66 30 23 data16 xor %ah, (%rbx) 67 30 23 xor %ah, (%ebx) 66 67 30 23 data16 xor %ah, (%ebx) 40 30 23 xor %spl, (%rbx) 67 40 30 23 xor %spl, (%ebx) 66 40 30 23 data16 xor %spl, (%rbx) 66 67 40 30 23 data16 xor %spl, (%ebx) 41 30 23 xor %spl, (%r11) 67 41 30 23 xor %spl, (%r11d) 66 41 30 23 data16 xor %spl, (%r11) 66 67 41 30 23 data16 xor %spl, (%r11d) 48 30 23 rex.W xor %spl, (%rbx) 67 48 30 23 rex.W xor %spl, (%ebx) 66 48 30 23 data16 rex.W xor %spl, (%rbx) 66 67 48 30 23 data16 rex.W xor %spl, (%ebx) 31 23 xor %esp, (%rbx) 66 31 23 xor %sp, (%rbx) 67 31 23 xor %esp, (%ebx) 66 67 31 23 xor %sp, (%ebx) 40 31 23 rex xor %esp, (%rbx) 67 40 31 23 rex xor %esp, (%ebx) 66 40 31 23 rex xor %sp, (%rbx) 66 67 40 31 23 rex xor %sp, (%ebx) 41 31 23 xor %esp, (%r11) 67 41 31 23 xor %esp, (%r11d) 66 41 31 23 xor %sp, (%r11) 66 67 41 31 23 xor %sp, (%r11d) 48 31 23 xor %rsp, (%rbx) 67 48 31 23 xor %rsp, (%ebx) 66 48 31 23 data16 xor %rsp, (%rbx) 66 67 48 31 23 data16 xor %rsp, (%ebx) 32 23 xor (%rbx), %ah 66 32 23 data16 xor (%rbx), %ah 67 32 23 xor (%ebx), %ah 66 67 32 23 data16 xor (%ebx), %ah 40 32 23 xor (%rbx), %spl 67 40 32 23 xor (%ebx), %spl 66 40 32 23 data16 xor (%rbx), %spl 66 67 40 32 23 data16 xor (%ebx), %spl 41 32 23 xor (%r11), %spl 67 41 32 23 xor (%r11d), %spl 66 41 32 23 data16 xor (%r11), %spl 66 67 41 32 23 data16 xor (%r11d), %spl 48 32 23 rex.W xor (%rbx), %spl 67 48 32 23 rex.W xor (%ebx), %spl 66 48 32 23 data16 rex.W xor (%rbx), %spl 66 67 48 32 23 data16 rex.W xor (%ebx), %spl 33 23 xor (%rbx), %esp 66 33 23 xor (%rbx), %sp 67 33 23 xor (%ebx), %esp 66 67 33 23 xor (%ebx), %sp 40 33 23 rex xor (%rbx), %esp 67 40 33 23 rex xor (%ebx), %esp 66 40 33 23 rex xor (%rbx), %sp 66 67 40 33 23 rex xor (%ebx), %sp 41 33 23 xor (%r11), %esp 67 41 33 23 xor (%r11d), %esp 66 41 33 23 xor (%r11), %sp 66 67 41 33 23 xor (%r11d), %sp 48 33 23 xor (%rbx), %rsp 67 48 33 23 xor (%ebx), %rsp 66 48 33 23 data16 xor (%rbx), %rsp 66 67 48 33 23 data16 xor (%ebx), %rsp 66 0f ba e6 12 bt $0x12, %si 66 0f ba e6 82 bt $0x82, %si 0f ba e6 12 bt $0x12, %esi 0f ba e6 82 bt $0x82, %esi 41 0f ba e6 12 bt $0x12, %r14d 41 0f ba e6 82 bt $0x82, %r14d 48 0f ba e6 12 bt $0x12, %rsi 48 0f ba e6 82 bt $0x82, %rsi 49 0f ba e6 12 bt $0x12, %r14 49 0f ba e6 82 bt $0x82, %r14 0f ba 23 12 btl $0x12, (%rbx) 0f ba 23 82 btl $0x82, (%rbx) 66 0f ba 23 12 btw $0x12, (%rbx) 66 0f ba 23 82 btw $0x82, (%rbx) 67 0f ba 23 12 btl $0x12, (%ebx) 67 0f ba 23 82 btl $0x82, (%ebx) 66 67 0f ba 23 12 btw $0x12, (%ebx) 66 67 0f ba 23 82 btw $0x82, (%ebx) 49 0f ba 23 12 btq $0x12, (%r11) 49 0f ba 23 82 btq $0x82, (%r11) 66 49 0f ba 23 12 data16 btq $0x12, (%r11) 66 49 0f ba 23 82 data16 btq $0x82, (%r11) 67 49 0f ba 23 12 btq $0x12, (%r11d) 67 49 0f ba 23 82 btq $0x82, (%r11d) 66 67 49 0f ba 23 12 data16 btq $0x12, (%r11d) 66 67 49 0f ba 23 82 data16 btq $0x82, (%r11d) 0f a3 e6 bt %esp, %esi 41 0f a3 e6 bt %esp, %r14d 49 0f a3 e6 bt %rsp, %r14 66 0f a3 e6 bt %sp, %si 0f a3 23 bt %esp, (%rbx) 66 0f a3 23 bt %sp, (%rbx) 67 0f a3 23 bt %esp, (%ebx) 66 67 0f a3 23 bt %sp, (%ebx) 40 0f a3 23 rex bt %esp, (%rbx) 67 40 0f a3 23 rex bt %esp, (%ebx) 66 40 0f a3 23 rex bt %sp, (%rbx) 66 67 40 0f a3 23 rex bt %sp, (%ebx) 41 0f a3 23 bt %esp, (%r11) 67 41 0f a3 23 bt %esp, (%r11d) 66 41 0f a3 23 bt %sp, (%r11) 66 67 41 0f a3 23 bt %sp, (%r11d) 48 0f a3 23 bt %rsp, (%rbx) 67 48 0f a3 23 bt %rsp, (%ebx) 66 48 0f a3 23 data16 bt %rsp, (%rbx) 66 67 48 0f a3 23 data16 bt %rsp, (%ebx)
jared-hughes/defcpu	1,118	tests/disassembly/sources/001_mov8.s	b0 11 mov $0x11, %al b1 12 mov $0x12, %cl b2 13 mov $0x13, %dl b3 14 mov $0x14, %bl b4 21 mov $0x21, %ah b5 22 mov $0x22, %ch b6 23 mov $0x23, %dh b7 24 mov $0x24, %bh 40 b6 31 mov $0x31, %sil 40 b7 32 mov $0x32, %dil 40 b4 33 mov $0x33, %spl 40 b5 34 mov $0x34, %bpl 41 b0 41 mov $0x41, %r8b 41 b1 42 mov $0x42, %r9b 41 b2 43 mov $0x43, %r10b 41 b3 44 mov $0x44, %r11b 41 b4 45 mov $0x45, %r12b 41 b5 46 mov $0x46, %r13b 41 b6 47 mov $0x47, %r14b 41 b7 48 mov $0x48, %r15b 42 b6 52 rex.X mov $0x52, %sil 43 b6 53 rex.XB mov $0x53, %r14b 44 b6 54 rex.R mov $0x54, %sil 45 b6 55 rex.RB mov $0x55, %r14b 46 b6 56 rex.RX mov $0x56, %sil 47 b6 57 rex.RXB mov $0x57, %r14b 48 b6 58 rex.W mov $0x58, %sil 49 b6 59 rex.WB mov $0x59, %r14b 4a b6 5a rex.WX mov $0x5a, %sil 4b b6 5b rex.WXB mov $0x5b, %r14b 4c b6 5c rex.WR mov $0x5c, %sil 4d b6 5d rex.WRB mov $0x5d, %r14b 4e b6 5e rex.WRX mov $0x5e, %sil 4f b6 5f rex.WRXB mov $0x5f, %r14b
jared-hughes/defcpu	2,093	tests/disassembly/sources/002_mov16.s	66 b8 ef be mov $0xbeef, %ax 66 b8 12 34 mov $0x3412, %ax 66 b9 12 34 mov $0x3412, %cx 66 ba 12 34 mov $0x3412, %dx 66 bb 12 34 mov $0x3412, %bx 66 bc 12 34 mov $0x3412, %sp 66 bd 12 34 mov $0x3412, %bp 66 be 12 34 mov $0x3412, %si 66 bf 12 34 mov $0x3412, %di 66 41 b8 12 34 mov $0x3412, %r8w 66 41 b9 12 34 mov $0x3412, %r9w 66 41 ba 12 34 mov $0x3412, %r10w 66 41 bb 12 34 mov $0x3412, %r11w 66 41 bc 12 34 mov $0x3412, %r12w 66 41 bd 12 34 mov $0x3412, %r13w 66 41 be 12 34 mov $0x3412, %r14w 66 41 bf 12 34 mov $0x3412, %r15w 66 40 b8 12 34 rex mov $0x3412, %ax 66 41 b8 12 34 mov $0x3412, %r8w 66 42 b8 12 34 rex.X mov $0x3412, %ax 66 43 b8 12 34 rex.XB mov $0x3412, %r8w 66 44 b8 12 34 rex.R mov $0x3412, %ax 66 45 b8 12 34 rex.RB mov $0x3412, %r8w 66 46 b8 12 34 rex.RX mov $0x3412, %ax 66 47 b8 12 34 rex.RXB mov $0x3412, %r8w 66 48 b8 12 34 56 78 9a bc de ff data16 movabs $0xffdebc9a78563412, %rax 66 49 b8 12 34 56 78 9a bc de ff data16 movabs $0xffdebc9a78563412, %r8 66 4a b8 12 34 56 78 9a bc de ff data16 rex.WX movabs $0xffdebc9a78563412, %rax 66 4b b8 12 34 56 78 9a bc de ff data16 rex.WXB movabs $0xffdebc9a78563412, %r8 66 4c b8 12 34 56 78 9a bc de ff data16 rex.WR movabs $0xffdebc9a78563412, %rax 66 4d b8 12 34 56 78 9a bc de ff data16 rex.WRB movabs $0xffdebc9a78563412, %r8 66 4e b8 12 34 56 78 9a bc de ff data16 rex.WRX movabs $0xffdebc9a78563412, %rax 66 4f b8 12 34 56 78 9a bc de ff data16 rex.WRXB movabs $0xffdebc9a78563412, %r8
jared-hughes/defcpu	5,614	tests/disassembly/sources/006_movmem.s	88 23 mov %ah, (%rbx) 66 88 23 data16 mov %ah, (%rbx) 67 88 23 mov %ah, (%ebx) 66 67 88 23 data16 mov %ah, (%ebx) 40 88 23 mov %spl, (%rbx) 67 40 88 23 mov %spl, (%ebx) 66 40 88 23 data16 mov %spl, (%rbx) 66 67 40 88 23 data16 mov %spl, (%ebx) 41 88 23 mov %spl, (%r11) 67 41 88 23 mov %spl, (%r11d) 66 41 88 23 data16 mov %spl, (%r11) 66 67 41 88 23 data16 mov %spl, (%r11d) 48 88 23 rex.W mov %spl, (%rbx) 67 48 88 23 rex.W mov %spl, (%ebx) 66 48 88 23 data16 rex.W mov %spl, (%rbx) 66 67 48 88 23 data16 rex.W mov %spl, (%ebx) 49 88 23 rex.WB mov %spl, (%r11) 67 49 88 23 rex.WB mov %spl, (%r11d) 66 49 88 23 data16 rex.WB mov %spl, (%r11) 66 67 49 88 23 data16 rex.WB mov %spl, (%r11d) 88 c0 mov %al, %al 88 c1 mov %al, %cl 88 c2 mov %al, %dl 88 c3 mov %al, %bl 88 c4 mov %al, %ah 88 c5 mov %al, %ch 88 c6 mov %al, %dh 88 c7 mov %al, %bh 66 88 c1 data16 mov %al, %cl 67 88 c1 addr32 mov %al, %cl 66 67 88 c1 data16 addr32 mov %al, %cl 40 88 c1 rex mov %al, %cl 67 40 88 c1 addr32 rex mov %al, %cl 66 40 88 c1 data16 rex mov %al, %cl 66 67 40 88 c1 data16 addr32 rex mov %al, %cl 41 88 c1 mov %al, %r9b 67 41 88 c1 addr32 mov %al, %r9b 66 41 88 c1 data16 mov %al, %r9b 66 67 41 88 c1 data16 addr32 mov %al, %r9b 48 88 c1 rex.W mov %al, %cl 67 48 88 c1 addr32 rex.W mov %al, %cl 66 48 88 c1 data16 rex.W mov %al, %cl 66 67 48 88 c1 data16 addr32 rex.W mov %al, %cl 49 88 c1 rex.WB mov %al, %r9b 67 49 88 c1 addr32 rex.WB mov %al, %r9b 66 49 88 c1 data16 rex.WB mov %al, %r9b 66 67 49 88 c1 data16 addr32 rex.WB mov %al, %r9b 8a 23 mov (%rbx), %ah 66 8a 23 data16 mov (%rbx), %ah 67 8a 23 mov (%ebx), %ah 66 67 8a 23 data16 mov (%ebx), %ah 40 8a 23 mov (%rbx), %spl 67 40 8a 23 mov (%ebx), %spl 66 40 8a 23 data16 mov (%rbx), %spl 66 67 40 8a 23 data16 mov (%ebx), %spl 41 8a 23 mov (%r11), %spl 67 41 8a 23 mov (%r11d), %spl 66 41 8a 23 data16 mov (%r11), %spl 66 67 41 8a 23 data16 mov (%r11d), %spl 48 8a 23 rex.W mov (%rbx), %spl 67 48 8a 23 rex.W mov (%ebx), %spl 66 48 8a 23 data16 rex.W mov (%rbx), %spl 66 67 48 8a 23 data16 rex.W mov (%ebx), %spl 49 8a 23 rex.WB mov (%r11), %spl 67 49 8a 23 rex.WB mov (%r11d), %spl 66 49 8a 23 data16 rex.WB mov (%r11), %spl 66 67 49 8a 23 data16 rex.WB mov (%r11d), %spl 89 23 mov %esp, (%rbx) 66 89 23 mov %sp, (%rbx) 67 89 23 mov %esp, (%ebx) 66 67 89 23 mov %sp, (%ebx) 40 89 23 rex mov %esp, (%rbx) 67 40 89 23 rex mov %esp, (%ebx) 66 40 89 23 rex mov %sp, (%rbx) 66 67 40 89 23 rex mov %sp, (%ebx) 41 89 23 mov %esp, (%r11) 67 41 89 23 mov %esp, (%r11d) 66 41 89 23 mov %sp, (%r11) 66 67 41 89 23 mov %sp, (%r11d) 48 89 23 mov %rsp, (%rbx) 67 48 89 23 mov %rsp, (%ebx) 66 48 89 23 data16 mov %rsp, (%rbx) 66 67 48 89 23 data16 mov %rsp, (%ebx) 49 89 23 mov %rsp, (%r11) 67 49 89 23 mov %rsp, (%r11d) 66 49 89 23 data16 mov %rsp, (%r11) 66 67 49 89 23 data16 mov %rsp, (%r11d) 89 c0 mov %eax, %eax 89 c1 mov %eax, %ecx 89 c2 mov %eax, %edx 89 c3 mov %eax, %ebx 89 c4 mov %eax, %esp 89 c5 mov %eax, %ebp 89 c6 mov %eax, %esi 89 c7 mov %eax, %edi 66 89 c1 mov %ax, %cx 67 89 c1 addr32 mov %eax, %ecx 66 67 89 c1 addr32 mov %ax, %cx 40 89 c1 rex mov %eax, %ecx 67 40 89 c1 addr32 rex mov %eax, %ecx 66 40 89 c1 rex mov %ax, %cx 66 67 40 89 c1 addr32 rex mov %ax, %cx 41 89 c1 mov %eax, %r9d 67 41 89 c1 addr32 mov %eax, %r9d 66 41 89 c1 mov %ax, %r9w 66 67 41 89 c1 addr32 mov %ax, %r9w 48 89 c1 mov %rax, %rcx 67 48 89 c1 addr32 mov %rax, %rcx 66 48 89 c1 data16 mov %rax, %rcx 66 67 48 89 c1 data16 addr32 mov %rax, %rcx 49 89 c1 mov %rax, %r9 67 49 89 c1 addr32 mov %rax, %r9 66 49 89 c1 data16 mov %rax, %r9 66 67 49 89 c1 data16 addr32 mov %rax, %r9 8b 23 mov (%rbx), %esp 66 8b 23 mov (%rbx), %sp 67 8b 23 mov (%ebx), %esp 66 67 8b 23 mov (%ebx), %sp 40 8b 23 rex mov (%rbx), %esp 67 40 8b 23 rex mov (%ebx), %esp 66 40 8b 23 rex mov (%rbx), %sp 66 67 40 8b 23 rex mov (%ebx), %sp 41 8b 23 mov (%r11), %esp 67 41 8b 23 mov (%r11d), %esp 66 41 8b 23 mov (%r11), %sp 66 67 41 8b 23 mov (%r11d), %sp 48 8b 23 mov (%rbx), %rsp 67 48 8b 23 mov (%ebx), %rsp 66 48 8b 23 data16 mov (%rbx), %rsp 66 67 48 8b 23 data16 mov (%ebx), %rsp 49 8b 23 mov (%r11), %rsp 67 49 8b 23 mov (%r11d), %rsp 66 49 8b 23 data16 mov (%r11), %rsp 66 67 49 8b 23 data16 mov (%r11d), %rsp
jared-hughes/defcpu	286	tests/disassembly/sources/024_cltq_cbw.s	98 cwtl 99 cltd 66 98 cbtw 66 99 cwtd 67 98 addr32 cwtl 67 99 addr32 cltd 40 98 rex cwtl 40 99 rex cltd 41 98 rex.B cwtl 41 99 rex.B cltd 48 98 cltq 48 99 cqto 49 98 rex.WB cltq 49 99 rex.WB cqto
jared-hughes/defcpu	10,317	tests/disassembly/sources/009_sidb.s	8a 0c 18 mov (%rax, %rbx, 1), %cl 8a 0c 58 mov (%rax, %rbx, 2), %cl 8a 0c 98 mov (%rax, %rbx, 4), %cl 8a 0c d8 mov (%rax, %rbx, 8), %cl 67 8a 0c 18 mov (%eax, %ebx, 1), %cl 67 8a 0c 58 mov (%eax, %ebx, 2), %cl 67 8a 0c 98 mov (%eax, %ebx, 4), %cl 67 8a 0c d8 mov (%eax, %ebx, 8), %cl 43 8a 0c 23 mov (%r11, %r12, 1), %cl 43 8a 0c 63 mov (%r11, %r12, 2), %cl 43 8a 0c a3 mov (%r11, %r12, 4), %cl 43 8a 0c e3 mov (%r11, %r12, 8), %cl 67 43 8a 0c 23 mov (%r11d, %r12d, 1), %cl 67 43 8a 0c 63 mov (%r11d, %r12d, 2), %cl 67 43 8a 0c a3 mov (%r11d, %r12d, 4), %cl 67 43 8a 0c e3 mov (%r11d, %r12d, 8), %cl 8a 4c 18 79 mov 0x79(%rax, %rbx, 1), %cl 8a 4c 58 80 mov -0x80(%rax, %rbx, 2), %cl 8a 8c 98 80 00 00 00 mov 0x80(%rax, %rbx, 4), %cl 8a 8c d8 7f ff ff ff mov -0x81(%rax, %rbx, 8), %cl 8a 0c 1c mov (%rsp, %rbx, 1), %cl 8a 35 12 34 56 78 mov 0x78563412(%rip), %dh 67 8a 35 12 34 56 78 mov 0x78563412(%eip), %dh 8a 04 20 mov (%rax, %riz, 1), %al 8a 84 20 12 34 56 78 mov 0x78563412(%rax, %riz, 1), %al 8a 04 20 mov (%rax, %riz, 1), %al 8a 0c 20 mov (%rax, %riz, 1), %cl 8a 14 20 mov (%rax, %riz, 1), %dl 8a 1c 20 mov (%rax, %riz, 1), %bl 8a 24 20 mov (%rax, %riz, 1), %ah 8a 2c 20 mov (%rax, %riz, 1), %ch 8a 34 20 mov (%rax, %riz, 1), %dh 8a 3c 20 mov (%rax, %riz, 1), %bh 8a 04 21 mov (%rcx, %riz, 1), %al 8a 04 22 mov (%rdx, %riz, 1), %al 8a 04 23 mov (%rbx, %riz, 1), %al 8a 04 24 mov (%rsp), %al 8a 04 25 12 34 56 78 mov 0x78563412, %al 8a 04 65 12 34 56 78 mov 0x78563412(, %riz, 2), %al 8a 04 a5 12 34 56 78 mov 0x78563412(, %riz, 4), %al 8a 04 e5 12 34 56 78 mov 0x78563412(, %riz, 8), %al 8a 04 26 mov (%rsi, %riz, 1), %al 8a 04 27 mov (%rdi, %riz, 1), %al 8a 04 64 mov (%rsp, %riz, 2), %al 8a 04 a4 mov (%rsp, %riz, 4), %al 8a 04 e4 mov (%rsp, %riz, 8), %al 8a 04 ac mov (%rsp, %rbp, 4), %al 8a 44 20 3a mov 0x3a(%rax, %riz, 1), %al 8a 4c 20 3a mov 0x3a(%rax, %riz, 1), %cl 8a 54 20 3a mov 0x3a(%rax, %riz, 1), %dl 8a 5c 20 3a mov 0x3a(%rax, %riz, 1), %bl 8a 64 20 3a mov 0x3a(%rax, %riz, 1), %ah 8a 6c 20 3a mov 0x3a(%rax, %riz, 1), %ch 8a 74 20 3a mov 0x3a(%rax, %riz, 1), %dh 8a 7c 20 3a mov 0x3a(%rax, %riz, 1), %bh 8a 44 24 3a mov 0x3a(%rsp), %al 8a 44 64 3a mov 0x3a(%rsp, %riz, 2), %al 8a 44 a4 3a mov 0x3a(%rsp, %riz, 4), %al 8a 44 e4 3a mov 0x3a(%rsp, %riz, 8), %al 8a 44 25 3a mov 0x3a(%rbp, %riz, 1), %al 8a 44 65 3a mov 0x3a(%rbp, %riz, 2), %al 8a 44 a5 3a mov 0x3a(%rbp, %riz, 4), %al 8a 44 e5 3a mov 0x3a(%rbp, %riz, 8), %al 66 8a 4c 18 79 data16 mov 0x79(%rax, %rbx, 1), %cl 66 8a 4c 58 80 data16 mov -0x80(%rax, %rbx, 2), %cl 66 8a 8c 98 80 00 00 00 data16 mov 0x80(%rax, %rbx, 4), %cl 66 8a 8c d8 7f ff ff ff data16 mov -0x81(%rax, %rbx, 8), %cl 66 8a 0c 1c data16 mov (%rsp, %rbx, 1), %cl 66 8a 35 12 34 56 78 data16 mov 0x78563412(%rip), %dh 66 67 8a 35 12 34 56 78 data16 mov 0x78563412(%eip), %dh 66 8a 04 20 data16 mov (%rax, %riz, 1), %al 66 8a 84 20 12 34 56 78 data16 mov 0x78563412(%rax, %riz, 1), %al 66 8a 04 20 data16 mov (%rax, %riz, 1), %al 66 8a 0c 20 data16 mov (%rax, %riz, 1), %cl 66 8a 14 20 data16 mov (%rax, %riz, 1), %dl 66 8a 1c 20 data16 mov (%rax, %riz, 1), %bl 66 8a 24 20 data16 mov (%rax, %riz, 1), %ah 66 8a 2c 20 data16 mov (%rax, %riz, 1), %ch 66 8a 34 20 data16 mov (%rax, %riz, 1), %dh 66 8a 3c 20 data16 mov (%rax, %riz, 1), %bh 66 8a 04 21 data16 mov (%rcx, %riz, 1), %al 66 8a 04 22 data16 mov (%rdx, %riz, 1), %al 66 8a 04 23 data16 mov (%rbx, %riz, 1), %al 66 8a 04 24 data16 mov (%rsp), %al 66 8a 04 25 12 34 56 78 data16 mov 0x78563412, %al 66 8a 04 65 12 34 56 78 data16 mov 0x78563412(, %riz, 2), %al 66 8a 04 a5 12 34 56 78 data16 mov 0x78563412(, %riz, 4), %al 66 8a 04 e5 12 34 56 78 data16 mov 0x78563412(, %riz, 8), %al 66 8a 04 26 data16 mov (%rsi, %riz, 1), %al 66 8a 04 27 data16 mov (%rdi, %riz, 1), %al 66 8a 04 64 data16 mov (%rsp, %riz, 2), %al 66 8a 04 a4 data16 mov (%rsp, %riz, 4), %al 66 8a 04 e4 data16 mov (%rsp, %riz, 8), %al 66 8a 44 20 3a data16 mov 0x3a(%rax, %riz, 1), %al 66 8a 4c 20 3a data16 mov 0x3a(%rax, %riz, 1), %cl 66 8a 54 20 3a data16 mov 0x3a(%rax, %riz, 1), %dl 66 8a 5c 20 3a data16 mov 0x3a(%rax, %riz, 1), %bl 66 8a 64 20 3a data16 mov 0x3a(%rax, %riz, 1), %ah 66 8a 6c 20 3a data16 mov 0x3a(%rax, %riz, 1), %ch 66 8a 74 20 3a data16 mov 0x3a(%rax, %riz, 1), %dh 66 8a 7c 20 3a data16 mov 0x3a(%rax, %riz, 1), %bh 66 8a 44 24 3a data16 mov 0x3a(%rsp), %al 66 8a 44 64 3a data16 mov 0x3a(%rsp, %riz, 2), %al 66 8a 44 a4 3a data16 mov 0x3a(%rsp, %riz, 4), %al 66 8a 44 e4 3a data16 mov 0x3a(%rsp, %riz, 8), %al 66 8a 44 25 3a data16 mov 0x3a(%rbp, %riz, 1), %al 66 8a 44 65 3a data16 mov 0x3a(%rbp, %riz, 2), %al 66 8a 44 a5 3a data16 mov 0x3a(%rbp, %riz, 4), %al 66 8a 44 e5 3a data16 mov 0x3a(%rbp, %riz, 8), %al 67 8a 4c 18 79 mov 0x79(%eax, %ebx, 1), %cl 67 8a 4c 58 80 mov -0x80(%eax, %ebx, 2), %cl 67 8a 8c 98 80 00 00 00 mov 0x80(%eax, %ebx, 4), %cl 67 8a 8c d8 7f ff ff ff mov -0x81(%eax, %ebx, 8), %cl 67 8a 0c 1c mov (%esp, %ebx, 1), %cl 67 8a 35 12 34 56 78 mov 0x78563412(%eip), %dh 67 67 8a 35 12 34 56 78 addr32 mov 0x78563412(%eip), %dh 67 8a 04 20 mov (%eax, %eiz, 1), %al 67 8a 84 20 12 34 56 78 mov 0x78563412(%eax, %eiz, 1), %al 67 8a 04 20 mov (%eax, %eiz, 1), %al 67 8a 0c 20 mov (%eax, %eiz, 1), %cl 67 8a 14 20 mov (%eax, %eiz, 1), %dl 67 8a 1c 20 mov (%eax, %eiz, 1), %bl 67 8a 24 20 mov (%eax, %eiz, 1), %ah 67 8a 2c 20 mov (%eax, %eiz, 1), %ch 67 8a 34 20 mov (%eax, %eiz, 1), %dh 67 8a 3c 20 mov (%eax, %eiz, 1), %bh 67 8a 04 21 mov (%ecx, %eiz, 1), %al 67 8a 04 22 mov (%edx, %eiz, 1), %al 67 8a 04 23 mov (%ebx, %eiz, 1), %al 67 8a 04 24 mov (%esp), %al 67 8a 04 25 12 34 56 78 mov 0x78563412(, %eiz, 1), %al 67 8a 04 65 12 34 56 78 mov 0x78563412(, %eiz, 2), %al 67 8a 04 a5 12 34 56 78 mov 0x78563412(, %eiz, 4), %al 67 8a 04 e5 12 34 56 78 mov 0x78563412(, %eiz, 8), %al 67 8a 04 26 mov (%esi, %eiz, 1), %al 67 8a 04 27 mov (%edi, %eiz, 1), %al 67 8a 04 64 mov (%esp, %eiz, 2), %al 67 8a 04 a4 mov (%esp, %eiz, 4), %al 67 8a 04 e4 mov (%esp, %eiz, 8), %al 67 8a 44 20 3a mov 0x3a(%eax, %eiz, 1), %al 67 8a 4c 20 3a mov 0x3a(%eax, %eiz, 1), %cl 67 8a 54 20 3a mov 0x3a(%eax, %eiz, 1), %dl 67 8a 5c 20 3a mov 0x3a(%eax, %eiz, 1), %bl 67 8a 64 20 3a mov 0x3a(%eax, %eiz, 1), %ah 67 8a 6c 20 3a mov 0x3a(%eax, %eiz, 1), %ch 67 8a 74 20 3a mov 0x3a(%eax, %eiz, 1), %dh 67 8a 7c 20 3a mov 0x3a(%eax, %eiz, 1), %bh 67 8a 44 24 3a mov 0x3a(%esp), %al 67 8a 44 64 3a mov 0x3a(%esp, %eiz, 2), %al 67 8a 44 a4 3a mov 0x3a(%esp, %eiz, 4), %al 67 8a 44 e4 3a mov 0x3a(%esp, %eiz, 8), %al 67 8a 44 25 3a mov 0x3a(%ebp, %eiz, 1), %al 67 8a 44 65 3a mov 0x3a(%ebp, %eiz, 2), %al 67 8a 44 a5 3a mov 0x3a(%ebp, %eiz, 4), %al 67 8a 44 e5 3a mov 0x3a(%ebp, %eiz, 8), %al 8a 44 24 12 mov 0x12(%rsp), %al 8a 44 25 12 mov 0x12(%rbp, %riz, 1), %al 8a 44 65 12 mov 0x12(%rbp, %riz, 2), %al 8a 44 a5 12 mov 0x12(%rbp, %riz, 4), %al 8a 44 e5 12 mov 0x12(%rbp, %riz, 8), %al 8a 84 24 12 34 56 78 mov 0x78563412(%rsp), %al 8a 84 25 12 34 56 78 mov 0x78563412(%rbp, %riz, 1), %al 8a 84 65 12 34 56 78 mov 0x78563412(%rbp, %riz, 2), %al 8a 84 a5 12 34 56 78 mov 0x78563412(%rbp, %riz, 4), %al 8a 84 e5 12 34 56 78 mov 0x78563412(%rbp, %riz, 8), %al 8a c4 mov %ah, %al 8a 05 12 34 56 78 mov 0x78563412(%rip), %al 8a 0d 12 34 56 78 mov 0x78563412(%rip), %cl 8a 15 12 34 56 78 mov 0x78563412(%rip), %dl 8a 1d 12 34 56 78 mov 0x78563412(%rip), %bl 8a 25 12 34 56 78 mov 0x78563412(%rip), %ah 8a 2d 12 34 56 78 mov 0x78563412(%rip), %ch 8a 35 12 34 56 78 mov 0x78563412(%rip), %dh 8a 3d 12 34 56 78 mov 0x78563412(%rip), %bh 8a 45 12 mov 0x12(%rbp), %al
jared-hughes/defcpu	18,722	tests/disassembly/sources/011_rm8.s	fe 00 incb (%rax) fe 01 incb (%rcx) fe 02 incb (%rdx) fe 03 incb (%rbx) fe 04 12 incb (%rdx, %rdx, 1) fe 05 12 34 56 78 incb 0x78563412(%rip) fe 06 incb (%rsi) fe 07 incb (%rdi) fe 40 12 incb 0x12(%rax) fe 41 12 incb 0x12(%rcx) fe 42 12 incb 0x12(%rdx) fe 43 12 incb 0x12(%rbx) fe 44 12 34 incb 0x34(%rdx, %rdx, 1) fe 45 12 incb 0x12(%rbp) fe 46 12 incb 0x12(%rsi) fe 47 12 incb 0x12(%rdi) fe 80 12 34 56 78 incb 0x78563412(%rax) fe 81 12 34 56 78 incb 0x78563412(%rcx) fe 82 12 34 56 78 incb 0x78563412(%rdx) fe 83 12 34 56 78 incb 0x78563412(%rbx) fe 84 12 34 56 78 9a incb -0x6587a9cc(%rdx, %rdx, 1) fe 85 12 34 56 78 incb 0x78563412(%rbp) fe 86 12 34 56 78 incb 0x78563412(%rsi) fe 87 12 34 56 78 incb 0x78563412(%rdi) fe c0 inc %al fe c1 inc %cl fe c2 inc %dl fe c3 inc %bl fe c4 inc %ah fe c5 inc %ch fe c6 inc %dh fe c7 inc %bh 67 fe 00 incb (%eax) 67 fe 01 incb (%ecx) 67 fe 02 incb (%edx) 67 fe 03 incb (%ebx) 67 fe 04 12 incb (%edx, %edx, 1) 67 fe 05 12 34 56 78 incb 0x78563412(%eip) 67 fe 06 incb (%esi) 67 fe 07 incb (%edi) 67 fe 40 12 incb 0x12(%eax) 67 fe 41 12 incb 0x12(%ecx) 67 fe 42 12 incb 0x12(%edx) 67 fe 43 12 incb 0x12(%ebx) 67 fe 44 12 34 incb 0x34(%edx, %edx, 1) 67 fe 45 12 incb 0x12(%ebp) 67 fe 46 12 incb 0x12(%esi) 67 fe 47 12 incb 0x12(%edi) 67 fe 80 12 34 56 78 incb 0x78563412(%eax) 67 fe 81 12 34 56 78 incb 0x78563412(%ecx) 67 fe 82 12 34 56 78 incb 0x78563412(%edx) 67 fe 83 12 34 56 78 incb 0x78563412(%ebx) 67 fe 84 12 34 56 78 9a incb -0x6587a9cc(%edx, %edx, 1) 67 fe 85 12 34 56 78 incb 0x78563412(%ebp) 67 fe 86 12 34 56 78 incb 0x78563412(%esi) 67 fe 87 12 34 56 78 incb 0x78563412(%edi) 67 fe c0 addr32 inc %al 67 fe c1 addr32 inc %cl 67 fe c2 addr32 inc %dl 67 fe c3 addr32 inc %bl 67 fe c4 addr32 inc %ah 67 fe c5 addr32 inc %ch 67 fe c6 addr32 inc %dh 67 fe c7 addr32 inc %bh 41 fe 00 incb (%r8) 41 fe 01 incb (%r9) 41 fe 02 incb (%r10) 41 fe 03 incb (%r11) 41 fe 04 12 incb (%r10, %rdx, 1) 41 fe 05 12 34 56 78 incb 0x78563412(%rip) 41 fe 06 incb (%r14) 41 fe 07 incb (%r15) 41 fe 40 12 incb 0x12(%r8) 41 fe 41 12 incb 0x12(%r9) 41 fe 42 12 incb 0x12(%r10) 41 fe 43 12 incb 0x12(%r11) 41 fe 44 00 12 incb 0x12(%r8, %rax, 1) 41 fe 44 01 12 incb 0x12(%r9, %rax, 1) 41 fe 44 02 12 incb 0x12(%r10, %rax, 1) 41 fe 44 03 12 incb 0x12(%r11, %rax, 1) 41 fe 44 04 12 incb 0x12(%r12, %rax, 1) 41 fe 44 05 12 incb 0x12(%r13, %rax, 1) 41 fe 44 06 12 incb 0x12(%r14, %rax, 1) 41 fe 44 07 12 incb 0x12(%r15, %rax, 1) 41 fe 44 08 12 incb 0x12(%r8, %rcx, 1) 41 fe 44 09 12 incb 0x12(%r9, %rcx, 1) 41 fe 44 0a 12 incb 0x12(%r10, %rcx, 1) 41 fe 44 0b 12 incb 0x12(%r11, %rcx, 1) 41 fe 44 0c 12 incb 0x12(%r12, %rcx, 1) 41 fe 44 0d 12 incb 0x12(%r13, %rcx, 1) 41 fe 44 0e 12 incb 0x12(%r14, %rcx, 1) 41 fe 44 0f 12 incb 0x12(%r15, %rcx, 1) 41 fe 44 10 12 incb 0x12(%r8, %rdx, 1) 41 fe 44 11 12 incb 0x12(%r9, %rdx, 1) 41 fe 44 12 12 incb 0x12(%r10, %rdx, 1) 41 fe 44 13 12 incb 0x12(%r11, %rdx, 1) 41 fe 44 14 12 incb 0x12(%r12, %rdx, 1) 41 fe 44 15 12 incb 0x12(%r13, %rdx, 1) 41 fe 44 16 12 incb 0x12(%r14, %rdx, 1) 41 fe 44 17 12 incb 0x12(%r15, %rdx, 1) 41 fe 44 18 12 incb 0x12(%r8, %rbx, 1) 41 fe 44 19 12 incb 0x12(%r9, %rbx, 1) 41 fe 44 1a 12 incb 0x12(%r10, %rbx, 1) 41 fe 44 1b 12 incb 0x12(%r11, %rbx, 1) 41 fe 44 1c 12 incb 0x12(%r12, %rbx, 1) 41 fe 44 1d 12 incb 0x12(%r13, %rbx, 1) 41 fe 44 1e 12 incb 0x12(%r14, %rbx, 1) 41 fe 44 1f 12 incb 0x12(%r15, %rbx, 1) 41 fe 44 20 12 incb 0x12(%r8, %riz, 1) 41 fe 44 21 12 incb 0x12(%r9, %riz, 1) 41 fe 44 22 12 incb 0x12(%r10, %riz, 1) 41 fe 44 23 12 incb 0x12(%r11, %riz, 1) 41 fe 44 24 12 incb 0x12(%r12) 41 fe 44 25 12 incb 0x12(%r13, %riz, 1) 41 fe 44 26 12 incb 0x12(%r14, %riz, 1) 41 fe 44 27 12 incb 0x12(%r15, %riz, 1) 41 fe 44 28 12 incb 0x12(%r8, %rbp, 1) 41 fe 44 29 12 incb 0x12(%r9, %rbp, 1) 41 fe 44 2a 12 incb 0x12(%r10, %rbp, 1) 41 fe 44 2b 12 incb 0x12(%r11, %rbp, 1) 41 fe 44 2c 12 incb 0x12(%r12, %rbp, 1) 41 fe 44 2d 12 incb 0x12(%r13, %rbp, 1) 41 fe 44 2e 12 incb 0x12(%r14, %rbp, 1) 41 fe 44 2f 12 incb 0x12(%r15, %rbp, 1) 41 fe 44 30 12 incb 0x12(%r8, %rsi, 1) 41 fe 44 31 12 incb 0x12(%r9, %rsi, 1) 41 fe 44 32 12 incb 0x12(%r10, %rsi, 1) 41 fe 44 33 12 incb 0x12(%r11, %rsi, 1) 41 fe 44 34 12 incb 0x12(%r12, %rsi, 1) 41 fe 44 35 12 incb 0x12(%r13, %rsi, 1) 41 fe 44 36 12 incb 0x12(%r14, %rsi, 1) 41 fe 44 37 12 incb 0x12(%r15, %rsi, 1) 41 fe 44 38 12 incb 0x12(%r8, %rdi, 1) 41 fe 44 39 12 incb 0x12(%r9, %rdi, 1) 41 fe 44 3a 12 incb 0x12(%r10, %rdi, 1) 41 fe 44 3b 12 incb 0x12(%r11, %rdi, 1) 41 fe 44 3c 12 incb 0x12(%r12, %rdi, 1) 41 fe 44 3d 12 incb 0x12(%r13, %rdi, 1) 41 fe 44 3e 12 incb 0x12(%r14, %rdi, 1) 41 fe 44 3f 12 incb 0x12(%r15, %rdi, 1) 41 fe 44 40 12 incb 0x12(%r8, %rax, 2) 41 fe 44 41 12 incb 0x12(%r9, %rax, 2) 41 fe 44 42 12 incb 0x12(%r10, %rax, 2) 41 fe 44 43 12 incb 0x12(%r11, %rax, 2) 41 fe 44 44 12 incb 0x12(%r12, %rax, 2) 41 fe 44 45 12 incb 0x12(%r13, %rax, 2) 41 fe 44 46 12 incb 0x12(%r14, %rax, 2) 41 fe 44 47 12 incb 0x12(%r15, %rax, 2) 41 fe 44 48 12 incb 0x12(%r8, %rcx, 2) 41 fe 44 49 12 incb 0x12(%r9, %rcx, 2) 41 fe 44 4a 12 incb 0x12(%r10, %rcx, 2) 41 fe 44 4b 12 incb 0x12(%r11, %rcx, 2) 41 fe 44 4c 12 incb 0x12(%r12, %rcx, 2) 41 fe 44 4d 12 incb 0x12(%r13, %rcx, 2) 41 fe 44 4e 12 incb 0x12(%r14, %rcx, 2) 41 fe 44 4f 12 incb 0x12(%r15, %rcx, 2) 41 fe 44 50 12 incb 0x12(%r8, %rdx, 2) 41 fe 44 51 12 incb 0x12(%r9, %rdx, 2) 41 fe 44 52 12 incb 0x12(%r10, %rdx, 2) 41 fe 44 53 12 incb 0x12(%r11, %rdx, 2) 41 fe 44 54 12 incb 0x12(%r12, %rdx, 2) 41 fe 44 55 12 incb 0x12(%r13, %rdx, 2) 41 fe 44 56 12 incb 0x12(%r14, %rdx, 2) 41 fe 44 57 12 incb 0x12(%r15, %rdx, 2) 41 fe 44 58 12 incb 0x12(%r8, %rbx, 2) 41 fe 44 59 12 incb 0x12(%r9, %rbx, 2) 41 fe 44 5a 12 incb 0x12(%r10, %rbx, 2) 41 fe 44 5b 12 incb 0x12(%r11, %rbx, 2) 41 fe 44 5c 12 incb 0x12(%r12, %rbx, 2) 41 fe 44 5d 12 incb 0x12(%r13, %rbx, 2) 41 fe 44 5e 12 incb 0x12(%r14, %rbx, 2) 41 fe 44 5f 12 incb 0x12(%r15, %rbx, 2) 41 fe 44 60 12 incb 0x12(%r8, %riz, 2) 41 fe 44 61 12 incb 0x12(%r9, %riz, 2) 41 fe 44 62 12 incb 0x12(%r10, %riz, 2) 41 fe 44 63 12 incb 0x12(%r11, %riz, 2) 41 fe 44 64 12 incb 0x12(%r12, %riz, 2) 41 fe 44 65 12 incb 0x12(%r13, %riz, 2) 41 fe 44 66 12 incb 0x12(%r14, %riz, 2) 41 fe 44 67 12 incb 0x12(%r15, %riz, 2) 41 fe 44 68 12 incb 0x12(%r8, %rbp, 2) 41 fe 44 69 12 incb 0x12(%r9, %rbp, 2) 41 fe 44 6a 12 incb 0x12(%r10, %rbp, 2) 41 fe 44 6b 12 incb 0x12(%r11, %rbp, 2) 41 fe 44 6c 12 incb 0x12(%r12, %rbp, 2) 41 fe 44 6d 12 incb 0x12(%r13, %rbp, 2) 41 fe 44 6e 12 incb 0x12(%r14, %rbp, 2) 41 fe 44 6f 12 incb 0x12(%r15, %rbp, 2) 41 fe 44 70 12 incb 0x12(%r8, %rsi, 2) 41 fe 44 71 12 incb 0x12(%r9, %rsi, 2) 41 fe 44 72 12 incb 0x12(%r10, %rsi, 2) 41 fe 44 73 12 incb 0x12(%r11, %rsi, 2) 41 fe 44 74 12 incb 0x12(%r12, %rsi, 2) 41 fe 44 75 12 incb 0x12(%r13, %rsi, 2) 41 fe 44 76 12 incb 0x12(%r14, %rsi, 2) 41 fe 44 77 12 incb 0x12(%r15, %rsi, 2) 41 fe 44 78 12 incb 0x12(%r8, %rdi, 2) 41 fe 44 79 12 incb 0x12(%r9, %rdi, 2) 41 fe 44 7a 12 incb 0x12(%r10, %rdi, 2) 41 fe 44 7b 12 incb 0x12(%r11, %rdi, 2) 41 fe 44 7c 12 incb 0x12(%r12, %rdi, 2) 41 fe 44 7d 12 incb 0x12(%r13, %rdi, 2) 41 fe 44 7e 12 incb 0x12(%r14, %rdi, 2) 41 fe 44 7f 12 incb 0x12(%r15, %rdi, 2) 41 fe 44 80 12 incb 0x12(%r8, %rax, 4) 41 fe 44 81 12 incb 0x12(%r9, %rax, 4) 41 fe 44 82 12 incb 0x12(%r10, %rax, 4) 41 fe 44 83 12 incb 0x12(%r11, %rax, 4) 41 fe 44 84 12 incb 0x12(%r12, %rax, 4) 41 fe 44 85 12 incb 0x12(%r13, %rax, 4) 41 fe 44 86 12 incb 0x12(%r14, %rax, 4) 41 fe 44 87 12 incb 0x12(%r15, %rax, 4) 41 fe 44 88 12 incb 0x12(%r8, %rcx, 4) 41 fe 44 89 12 incb 0x12(%r9, %rcx, 4) 41 fe 44 8a 12 incb 0x12(%r10, %rcx, 4) 41 fe 44 8b 12 incb 0x12(%r11, %rcx, 4) 41 fe 44 8c 12 incb 0x12(%r12, %rcx, 4) 41 fe 44 8d 12 incb 0x12(%r13, %rcx, 4) 41 fe 44 8e 12 incb 0x12(%r14, %rcx, 4) 41 fe 44 8f 12 incb 0x12(%r15, %rcx, 4) 41 fe 44 90 12 incb 0x12(%r8, %rdx, 4) 41 fe 44 91 12 incb 0x12(%r9, %rdx, 4) 41 fe 44 92 12 incb 0x12(%r10, %rdx, 4) 41 fe 44 93 12 incb 0x12(%r11, %rdx, 4) 41 fe 44 94 12 incb 0x12(%r12, %rdx, 4) 41 fe 44 95 12 incb 0x12(%r13, %rdx, 4) 41 fe 44 96 12 incb 0x12(%r14, %rdx, 4) 41 fe 44 97 12 incb 0x12(%r15, %rdx, 4) 41 fe 44 98 12 incb 0x12(%r8, %rbx, 4) 41 fe 44 99 12 incb 0x12(%r9, %rbx, 4) 41 fe 44 9a 12 incb 0x12(%r10, %rbx, 4) 41 fe 44 9b 12 incb 0x12(%r11, %rbx, 4) 41 fe 44 9c 12 incb 0x12(%r12, %rbx, 4) 41 fe 44 9d 12 incb 0x12(%r13, %rbx, 4) 41 fe 44 9e 12 incb 0x12(%r14, %rbx, 4) 41 fe 44 9f 12 incb 0x12(%r15, %rbx, 4) 41 fe 44 a0 12 incb 0x12(%r8, %riz, 4) 41 fe 44 a1 12 incb 0x12(%r9, %riz, 4) 41 fe 44 a2 12 incb 0x12(%r10, %riz, 4) 41 fe 44 a3 12 incb 0x12(%r11, %riz, 4) 41 fe 44 a4 12 incb 0x12(%r12, %riz, 4) 41 fe 44 a5 12 incb 0x12(%r13, %riz, 4) 41 fe 44 a6 12 incb 0x12(%r14, %riz, 4) 41 fe 44 a7 12 incb 0x12(%r15, %riz, 4) 41 fe 44 a8 12 incb 0x12(%r8, %rbp, 4) 41 fe 44 a9 12 incb 0x12(%r9, %rbp, 4) 41 fe 44 aa 12 incb 0x12(%r10, %rbp, 4) 41 fe 44 ab 12 incb 0x12(%r11, %rbp, 4) 41 fe 44 ac 12 incb 0x12(%r12, %rbp, 4) 41 fe 44 ad 12 incb 0x12(%r13, %rbp, 4) 41 fe 44 ae 12 incb 0x12(%r14, %rbp, 4) 41 fe 44 af 12 incb 0x12(%r15, %rbp, 4) 41 fe 44 b0 12 incb 0x12(%r8, %rsi, 4) 41 fe 44 b1 12 incb 0x12(%r9, %rsi, 4) 41 fe 44 b2 12 incb 0x12(%r10, %rsi, 4) 41 fe 44 b3 12 incb 0x12(%r11, %rsi, 4) 41 fe 44 b4 12 incb 0x12(%r12, %rsi, 4) 41 fe 44 b5 12 incb 0x12(%r13, %rsi, 4) 41 fe 44 b6 12 incb 0x12(%r14, %rsi, 4) 41 fe 44 b7 12 incb 0x12(%r15, %rsi, 4) 41 fe 44 b8 12 incb 0x12(%r8, %rdi, 4) 41 fe 44 b9 12 incb 0x12(%r9, %rdi, 4) 41 fe 44 ba 12 incb 0x12(%r10, %rdi, 4) 41 fe 44 bb 12 incb 0x12(%r11, %rdi, 4) 41 fe 44 bc 12 incb 0x12(%r12, %rdi, 4) 41 fe 44 bd 12 incb 0x12(%r13, %rdi, 4) 41 fe 44 be 12 incb 0x12(%r14, %rdi, 4) 41 fe 44 bf 12 incb 0x12(%r15, %rdi, 4) 41 fe 44 c0 12 incb 0x12(%r8, %rax, 8) 41 fe 44 c1 12 incb 0x12(%r9, %rax, 8) 41 fe 44 c2 12 incb 0x12(%r10, %rax, 8) 41 fe 44 c3 12 incb 0x12(%r11, %rax, 8) 41 fe 44 c4 12 incb 0x12(%r12, %rax, 8) 41 fe 44 c5 12 incb 0x12(%r13, %rax, 8) 41 fe 44 c6 12 incb 0x12(%r14, %rax, 8) 41 fe 44 c7 12 incb 0x12(%r15, %rax, 8) 41 fe 44 c8 12 incb 0x12(%r8, %rcx, 8) 41 fe 44 c9 12 incb 0x12(%r9, %rcx, 8) 41 fe 44 ca 12 incb 0x12(%r10, %rcx, 8) 41 fe 44 cb 12 incb 0x12(%r11, %rcx, 8) 41 fe 44 cc 12 incb 0x12(%r12, %rcx, 8) 41 fe 44 cd 12 incb 0x12(%r13, %rcx, 8) 41 fe 44 ce 12 incb 0x12(%r14, %rcx, 8) 41 fe 44 cf 12 incb 0x12(%r15, %rcx, 8) 41 fe 44 d0 12 incb 0x12(%r8, %rdx, 8) 41 fe 44 d1 12 incb 0x12(%r9, %rdx, 8) 41 fe 44 d2 12 incb 0x12(%r10, %rdx, 8) 41 fe 44 d3 12 incb 0x12(%r11, %rdx, 8) 41 fe 44 d4 12 incb 0x12(%r12, %rdx, 8) 41 fe 44 d5 12 incb 0x12(%r13, %rdx, 8) 41 fe 44 d6 12 incb 0x12(%r14, %rdx, 8) 41 fe 44 d7 12 incb 0x12(%r15, %rdx, 8) 41 fe 44 d8 12 incb 0x12(%r8, %rbx, 8) 41 fe 44 d9 12 incb 0x12(%r9, %rbx, 8) 41 fe 44 da 12 incb 0x12(%r10, %rbx, 8) 41 fe 44 db 12 incb 0x12(%r11, %rbx, 8) 41 fe 44 dc 12 incb 0x12(%r12, %rbx, 8) 41 fe 44 dd 12 incb 0x12(%r13, %rbx, 8) 41 fe 44 de 12 incb 0x12(%r14, %rbx, 8) 41 fe 44 df 12 incb 0x12(%r15, %rbx, 8) 41 fe 44 e0 12 incb 0x12(%r8, %riz, 8) 41 fe 44 e1 12 incb 0x12(%r9, %riz, 8) 41 fe 44 e2 12 incb 0x12(%r10, %riz, 8) 41 fe 44 e3 12 incb 0x12(%r11, %riz, 8) 41 fe 44 e4 12 incb 0x12(%r12, %riz, 8) 41 fe 44 e5 12 incb 0x12(%r13, %riz, 8) 41 fe 44 e6 12 incb 0x12(%r14, %riz, 8) 41 fe 44 e7 12 incb 0x12(%r15, %riz, 8) 41 fe 44 e8 12 incb 0x12(%r8, %rbp, 8) 41 fe 44 e9 12 incb 0x12(%r9, %rbp, 8) 41 fe 44 ea 12 incb 0x12(%r10, %rbp, 8) 41 fe 44 eb 12 incb 0x12(%r11, %rbp, 8) 41 fe 44 ec 12 incb 0x12(%r12, %rbp, 8) 41 fe 44 ed 12 incb 0x12(%r13, %rbp, 8) 41 fe 44 ee 12 incb 0x12(%r14, %rbp, 8) 41 fe 44 ef 12 incb 0x12(%r15, %rbp, 8) 41 fe 44 f0 12 incb 0x12(%r8, %rsi, 8) 41 fe 44 f1 12 incb 0x12(%r9, %rsi, 8) 41 fe 44 f2 12 incb 0x12(%r10, %rsi, 8) 41 fe 44 f3 12 incb 0x12(%r11, %rsi, 8) 41 fe 44 f4 12 incb 0x12(%r12, %rsi, 8) 41 fe 44 f5 12 incb 0x12(%r13, %rsi, 8) 41 fe 44 f6 12 incb 0x12(%r14, %rsi, 8) 41 fe 44 f7 12 incb 0x12(%r15, %rsi, 8) 41 fe 44 f8 12 incb 0x12(%r8, %rdi, 8) 41 fe 44 f9 12 incb 0x12(%r9, %rdi, 8) 41 fe 44 fa 12 incb 0x12(%r10, %rdi, 8) 41 fe 44 fb 12 incb 0x12(%r11, %rdi, 8) 41 fe 44 fc 12 incb 0x12(%r12, %rdi, 8) 41 fe 44 fd 12 incb 0x12(%r13, %rdi, 8) 41 fe 44 fe 12 incb 0x12(%r14, %rdi, 8) 41 fe 44 ff 12 incb 0x12(%r15, %rdi, 8) 41 fe 45 12 incb 0x12(%r13) 41 fe 46 12 incb 0x12(%r14) 41 fe 47 12 incb 0x12(%r15) 41 fe 80 12 34 56 78 incb 0x78563412(%r8) 41 fe 81 12 34 56 78 incb 0x78563412(%r9) 41 fe 82 12 34 56 78 incb 0x78563412(%r10) 41 fe 83 12 34 56 78 incb 0x78563412(%r11) 41 fe 84 12 34 56 78 9a incb -0x6587a9cc(%r10, %rdx, 1) 41 fe 85 12 34 56 78 incb 0x78563412(%r13) 41 fe 86 12 34 56 78 incb 0x78563412(%r14) 41 fe 87 12 34 56 78 incb 0x78563412(%r15) 41 fe c0 inc %r8b 41 fe c1 inc %r9b 41 fe c2 inc %r10b 41 fe c3 inc %r11b 41 fe c4 inc %r12b 41 fe c5 inc %r13b 41 fe c6 inc %r14b 41 fe c7 inc %r15b 40 fe c0 rex inc %al 40 fe c1 rex inc %cl 40 fe c2 rex inc %dl 40 fe c3 rex inc %bl 40 fe c4 inc %spl 40 fe c5 inc %bpl 40 fe c6 inc %sil 40 fe c7 inc %dil
jared-hughes/defcpu	895	tests/disassembly/sources/018_scas.s	ae scas %es:(%rdi), %al 66 ae data16 scas %es:(%rdi), %al 67 ae scas %es:(%edi), %al 66 67 ae data16 scas %es:(%edi), %al 41 ae rex.B scas %es:(%rdi), %al 48 ae rex.W scas %es:(%rdi), %al 49 ae rex.WB scas %es:(%rdi), %al 67 49 ae rex.WB scas %es:(%edi), %al 66 af scas %es:(%rdi), %ax 67 af scas %es:(%edi), %eax 66 67 af scas %es:(%edi), %ax 41 af rex.B scas %es:(%rdi), %eax 66 41 af rex.B scas %es:(%rdi), %ax 67 41 af rex.B scas %es:(%edi), %eax 66 67 41 af rex.B scas %es:(%edi), %ax 48 af scas %es:(%rdi), %rax 66 48 af data16 scas %es:(%rdi), %rax 67 48 af scas %es:(%edi), %rax 66 67 48 data16 addr32 rex.W 49 af rex.WB scas %es:(%rdi), %rax 66 49 af data16 rex.WB scas %es:(%rdi), %rax 67 49 af rex.WB scas %es:(%edi), %rax 66 67 49 af data16 rex.WB scas %es:(%edi), %rax
jared-hughes/defcpu	14,904	tests/disassembly/sources/005_fuzz_rex_mov.s	bf 4f b0 b9 4a mov $0x4ab9b04f, %edi b8 47 4a 4c 40 mov $0x404c4a47, %eax b0 b8 mov $0xb8, %al 47 b3 b9 rex.RXB mov $0xb9, %r11b 40 bf 47 4a 47 b3 rex mov $0xb3474a47, %edi 4f rex.WRXB 4c b3 4c rex.WR mov $0x4c, %bl 40 rex 4c bf bf b8 4c 4c 4a 4a 47 47 rex.WR movabs $0x47474a4a4c4cb8bf, %rdi 4c rex.WR 4c rex.WR 4f b0 47 rex.WRXB mov $0x47, %r8b b9 47 4c 47 b3 mov $0xb3474c47, %ecx 4f rex.WRXB 4a b0 b3 rex.WX mov $0xb3, %al 4c rex.WR 4c rex.WR 4f rex.WRXB 40 b0 4f rex mov $0x4f, %al bf bf 4a bf b0 mov $0xb0bf4abf, %edi 40 rex 4f b0 4f rex.WRXB mov $0x4f, %r8b b8 b0 4c b8 b8 mov $0xb8b84cb0, %eax 4c rex.WR 4a rex.WX 4f rex.WRXB 4a b0 b3 rex.WX mov $0xb3, %al 4a b9 b3 b0 b3 bf 4a b8 4a 4c rex.WX movabs $0x4c4ab84abfb3b0b3, %rcx bf 47 40 47 b8 mov $0xb8474047, %edi b0 b9 mov $0xb9, %al b0 b9 mov $0xb9, %al 4f b8 40 bf b0 4f 4a b3 40 47 rex.WRXB movabs $0x4740b34a4fb0bf40, %r8 b0 b9 mov $0xb9, %al bf b0 4c b0 4f mov $0x4fb04cb0, %edi b9 40 4f b0 4f mov $0x4fb04f40, %ecx 4c rex.WR 40 rex 4c rex.WR 4f b8 4c 4a 40 bf b9 b3 4a 47 rex.WRXB movabs $0x474ab3b9bf404a4c, %r8 bf b0 4f b8 b3 mov $0xb3b84fb0, %edi 4c rex.WR 4a rex.WX 4a b8 b0 47 4c bf 4c b3 40 4c rex.WX movabs $0x4c40b34cbf4c47b0, %rax b3 b0 mov $0xb0, %bl 4c rex.WR 4a b3 4f rex.WX mov $0x4f, %bl 4c b8 bf 4c b9 b8 b8 b0 b8 4f rex.WR movabs $0x4fb8b0b8b8b94cbf, %rax 4f b8 b3 4c 40 b3 b9 4c b8 b0 rex.WRXB movabs $0xb0b84cb9b3404cb3, %r8 4c rex.WR 40 b8 4f b9 b9 b9 rex mov $0xb9b9b94f, %eax b0 40 mov $0x40, %al b0 bf mov $0xbf, %al 4a rex.WX 4f b0 b9 rex.WRXB mov $0xb9, %r8b 4f b8 4f 4f b0 4c bf 4a b8 b9 rex.WRXB movabs $0xb9b84abf4cb04f4f, %r8 4f b0 4f rex.WRXB mov $0x4f, %r8b b8 4f b9 b0 b0 mov $0xb0b0b94f, %eax 4f b0 b3 rex.WRXB mov $0xb3, %r8b b0 4c mov $0x4c, %al b8 b0 b0 b9 4c mov $0x4cb9b0b0, %eax b9 4c 47 b0 b8 mov $0xb8b0474c, %ecx 4f rex.WRXB 40 b3 4c rex mov $0x4c, %bl bf bf b9 b3 4f mov $0x4fb3b9bf, %edi bf b9 4f 4a 47 mov $0x474a4fb9, %edi 4c bf b8 bf 4c 47 4c 4a b8 47 rex.WR movabs $0x47b84a4c474cbfb8, %rdi 4c rex.WR 4a rex.WX 4c rex.WR 40 b0 4c rex mov $0x4c, %al b8 47 b9 4a b3 mov $0xb34ab947, %eax b8 b0 b3 bf 40 mov $0x40bfb3b0, %eax bf 47 47 b0 4a mov $0x4ab04747, %edi b0 b3 mov $0xb3, %al 4f b3 40 rex.WRXB mov $0x40, %r11b b9 b0 4a b9 bf mov $0xbfb94ab0, %ecx 4f rex.WRXB 40 rex 4f b9 b9 b0 bf 4f b0 4c b3 b3 rex.WRXB movabs $0xb3b34cb04fbfb0b9, %r9 bf b9 b0 b8 4c mov $0x4cb8b0b9, %edi 4c bf b3 bf b8 47 4c bf 40 b0 rex.WR movabs $0xb040bf4c47b8bfb3, %rdi 4a b3 40 rex.WX mov $0x40, %bl b0 bf mov $0xbf, %al bf b9 4c b0 bf mov $0xbfb04cb9, %edi b3 b3 mov $0xb3, %bl b3 47 mov $0x47, %bl b8 4f b8 b3 b3 mov $0xb3b3b84f, %eax 4c bf bf 4f 4f b8 4f b3 4a b0 rex.WR movabs $0xb04ab34fb84f4fbf, %rdi 4f b8 4f 4c b8 4a 40 bf b8 47 rex.WRXB movabs $0x47b8bf404ab84c4f, %r8 4f rex.WRXB 4a rex.WX 4c b3 4a rex.WR mov $0x4a, %bl b8 b9 b9 4f 47 mov $0x474fb9b9, %eax b8 4a 47 b8 4f mov $0x4fb8474a, %eax 4c rex.WR 4f rex.WRXB 4f b8 bf b8 b9 bf 40 4a 4c 4f rex.WRXB movabs $0x4f4c4a40bfb9b8bf, %r8 4f b9 b0 bf 4f b9 4a b8 b0 b0 rex.WRXB movabs $0xb0b0b84ab94fbfb0, %r9 bf 4c 4a 4a 4f mov $0x4f4a4a4c, %edi b9 b8 40 b9 47 mov $0x47b940b8, %ecx 4a b3 b3 rex.WX mov $0xb3, %bl bf bf b8 b3 b8 mov $0xb8b3b8bf, %edi b3 47 mov $0x47, %bl 4f b8 40 4f 4a b3 bf 4f b8 4f rex.WRXB movabs $0x4fb84fbfb34a4f40, %r8 4c rex.WR 4c b8 b9 b8 b0 b9 4c b3 bf b9 rex.WR movabs $0xb9bfb34cb9b0b8b9, %rax 4a rex.WX 40 rex 47 rex.RXB 4f rex.WRXB 40 rex 40 rex 4a b0 b3 rex.WX mov $0xb3, %al 40 b3 b8 rex mov $0xb8, %bl 4a rex.WX 40 rex 40 rex 47 bf 40 4c 4f b8 rex.RXB mov $0xb84f4c40, %r15d 4c rex.WR 4c bf 4c b3 4c 40 bf 47 4a b9 rex.WR movabs $0xb94a47bf404cb34c, %rdi 40 b3 40 rex mov $0x40, %bl 4f rex.WRXB 4a bf bf 40 b3 bf 4c 4a b3 40 rex.WX movabs $0x40b34a4cbfb340bf, %rdi b0 bf mov $0xbf, %al b8 b8 b0 b0 4a mov $0x4ab0b0b8, %eax 4c rex.WR 4f rex.WRXB 4c bf b9 4f b9 b9 bf 47 4f 40 rex.WR movabs $0x404f47bfb9b94fb9, %rdi b9 47 4f 4f b9 mov $0xb94f4f47, %ecx 4c rex.WR 47 b0 b8 rex.RXB mov $0xb8, %r8b b3 4c mov $0x4c, %bl 4c rex.WR 4a b0 40 rex.WX mov $0x40, %al bf 4a 40 40 b9 mov $0xb940404a, %edi bf b8 47 b3 b8 mov $0xb8b347b8, %edi b8 b0 40 b9 4a mov $0x4ab940b0, %eax b9 b3 4a 4c b3 mov $0xb34c4ab3, %ecx 47 rex.RXB 40 rex 40 b8 47 4c bf b3 rex mov $0xb3bf4c47, %eax b0 47 mov $0x47, %al 4f b0 bf rex.WRXB mov $0xbf, %r8b b0 b3 mov $0xb3, %al b3 4c mov $0x4c, %bl b0 4f mov $0x4f, %al b3 b0 mov $0xb0, %bl b9 4a bf bf 47 mov $0x47bfbf4a, %ecx 4c b3 40 rex.WR mov $0x40, %bl 40 rex 4a rex.WX 4a rex.WX 4c rex.WR 47 rex.RXB 47 rex.RXB 4a b8 b8 b0 4a b3 b8 4f bf b3 rex.WX movabs $0xb3bf4fb8b34ab0b8, %rax b0 b8 mov $0xb8, %al b8 40 47 4c 4c mov $0x4c4c4740, %eax 40 b0 b3 rex mov $0xb3, %al b8 4c b9 4f 40 mov $0x404fb94c, %eax 4f rex.WRXB 4c rex.WR 4f rex.WRXB 47 rex.RXB 4a b8 4a b0 b0 b0 4a 4a b8 b8 rex.WX movabs $0xb8b84a4ab0b0b04a, %rax 4c rex.WR 40 b0 4f rex mov $0x4f, %al b8 47 4c 4a 47 mov $0x474a4c47, %eax 4a bf 47 40 bf b3 b0 4f 4c b8 rex.WX movabs $0xb84c4fb0b3bf4047, %rdi b0 4f mov $0x4f, %al 40 b8 4c 47 4c 47 rex mov $0x474c474c, %eax 4a bf b3 4f 4a b8 4a b8 b3 4c rex.WX movabs $0x4cb3b84ab84a4fb3, %rdi 4a rex.WX 4a b9 b9 bf b0 40 40 47 b8 40 rex.WX movabs $0x40b8474040b0bfb9, %rcx b8 4a 47 4a b8 mov $0xb84a474a, %eax b3 4a mov $0x4a, %bl 4a rex.WX 4f b3 b8 rex.WRXB mov $0xb8, %r11b 4f rex.WRXB 4a rex.WX 4a rex.WX 47 rex.RXB 4c b9 b3 47 b9 47 40 b0 40 40 rex.WR movabs $0x4040b04047b947b3, %rcx b9 4c bf 40 47 mov $0x4740bf4c, %ecx bf 4a b8 b9 b0 mov $0xb0b9b84a, %edi b8 b3 bf b3 b9 mov $0xb9b3bfb3, %eax 4c rex.WR 4a rex.WX 4f b8 47 b9 40 4c 4f b8 40 4f rex.WRXB movabs $0x4f40b84f4c40b947, %r8 b3 b0 mov $0xb0, %bl 4c rex.WR 4c b9 40 b8 47 40 b3 bf 47 4f rex.WR movabs $0x4f47bfb34047b840, %rcx 4a b8 47 4a 47 4f b0 40 40 b3 rex.WX movabs $0xb34040b04f474a47, %rax b0 b3 mov $0xb3, %al b9 4a 4f 4c bf mov $0xbf4c4f4a, %ecx 4a b8 4c 4a 4a b3 4f 40 b3 b9 rex.WX movabs $0xb9b3404fb34a4a4c, %rax 4c b0 40 rex.WR mov $0x40, %al 4f rex.WRXB 4c rex.WR 4c rex.WR 4f b8 b0 4f 4a 40 b9 b9 4a 4a rex.WRXB movabs $0x4a4ab9b9404a4fb0, %r8 40 rex 4a rex.WX 4c b0 b3 rex.WR mov $0xb3, %al 4f bf 4a 47 b9 b3 4c b0 47 b0 rex.WRXB movabs $0xb047b04cb3b9474a, %r15 b0 4a mov $0x4a, %al 4c bf bf 4c 40 4f b9 bf 4c 4c rex.WR movabs $0x4c4cbfb94f404cbf, %rdi b8 b3 b3 40 b0 mov $0xb040b3b3, %eax b0 b8 mov $0xb8, %al 47 b8 bf b3 4c b8 rex.RXB mov $0xb84cb3bf, %r8d 4a rex.WX 4c b9 b8 b8 bf 4a 40 4c b3 4a rex.WR movabs $0x4ab34c404abfb8b8, %rcx 47 rex.RXB 4a rex.WX 4a bf 47 b8 b0 b3 b8 47 47 4f rex.WX movabs $0x4f4747b8b3b0b847, %rdi 47 rex.RXB 4f b9 b9 b0 47 b0 b0 47 4a bf rex.WRXB movabs $0xbf4a47b0b047b0b9, %r9 b8 b3 b0 4c 4c mov $0x4c4cb0b3, %eax 47 b8 b3 4a 40 4c rex.RXB mov $0x4c404ab3, %r8d b3 40 mov $0x40, %bl 4f rex.WRXB 47 b0 b8 rex.RXB mov $0xb8, %r8b b8 b9 bf 40 47 mov $0x4740bfb9, %eax b3 4a mov $0x4a, %bl 40 b9 bf bf bf 4c rex mov $0x4cbfbfbf, %ecx b3 4a mov $0x4a, %bl b0 4a mov $0x4a, %al bf 4f b9 b3 b9 mov $0xb9b3b94f, %edi b8 b9 b3 b8 bf mov $0xbfb8b3b9, %eax b9 4a b9 4c b3 mov $0xb34cb94a, %ecx b0 bf mov $0xbf, %al 4a b9 47 4f 4f 40 4a 40 b0 bf rex.WX movabs $0xbfb0404a404f4f47, %rcx bf b3 4f 4a 4f mov $0x4f4a4fb3, %edi 47 rex.RXB 40 rex 4a rex.WX 40 rex 4f b0 bf rex.WRXB mov $0xbf, %r8b bf b9 47 b8 b9 mov $0xb9b847b9, %edi 40 rex 40 rex 47 b0 b9 rex.RXB mov $0xb9, %r8b b3 b3 mov $0xb3, %bl 4a b3 b3 rex.WX mov $0xb3, %bl 4c b9 47 bf b0 b3 b0 40 b9 b0 rex.WR movabs $0xb0b940b0b3b0bf47, %rcx 47 rex.RXB 40 rex 47 rex.RXB 4f rex.WRXB 4f rex.WRXB 4f bf 40 4c 40 b3 4c 47 40 bf rex.WRXB movabs $0xbf40474cb3404c40, %r15 bf b9 b3 b3 47 mov $0x47b3b3b9, %edi b3 b8 mov $0xb8, %bl b9 bf 47 4f b3 mov $0xb34f47bf, %ecx 4f rex.WRXB 40 bf b0 4c b3 4a rex mov $0x4ab34cb0, %edi 4c rex.WR 40 rex 4f bf b9 bf bf 4c b3 47 b0 bf rex.WRXB movabs $0xbfb047b34cbfbfb9, %r15 40 b0 40 rex mov $0x40, %al 4a b8 4c b9 40 b0 47 b8 b3 47 rex.WX movabs $0x47b3b847b040b94c, %rax bf b8 40 4a 47 mov $0x474a40b8, %edi 4c rex.WR 40 rex 40 b0 4c rex mov $0x4c, %al b0 bf mov $0xbf, %al 40 bf b8 b0 4c b9 rex mov $0xb94cb0b8, %edi
jared-hughes/defcpu	559	tests/disassembly/sources/019_rep.s	f3 ae repz scas %es:(%rdi), %al f2 ae repnz scas %es:(%rdi), %al f2 03 00 repnz add (%rax), %eax 03 00 add (%rax), %eax 66 f2 67 f3 00 00 data16 repnz repz add %al, (%eax) 67 f2 ae repnz scas %es:(%edi), %al f2 ae repnz scas %es:(%rdi), %al 66 f2 49 data16 repnz rex.WB f2 67 ae repnz scas %es:(%edi), %al 66 f2 49 data16 repnz rex.WB f2 ae repnz scas %es:(%rdi), %al 66 f2 67 49 ae data16 repnz rex.WB scas %es:(%edi), %al
jared-hughes/defcpu	150	tests/disassembly/sources/007_mov_rm_imm.s	48 c7 c0 12 34 56 78 mov $0x78563412, %rax c6 c0 12 mov $0x12, %al 66 67 88 23 data16 mov %ah, (%ebx)
jared-hughes/defcpu	6,268	tests/disassembly/sources/017_pop.s	58 pop %rax 59 pop %rcx 5a pop %rdx 5b pop %rbx 5c pop %rsp 5d pop %rbp 5e pop %rsi 5f pop %rdi 66 58 pop %ax 66 59 pop %cx 66 5a pop %dx 66 5b pop %bx 66 5c pop %sp 66 5d pop %bp 66 5e pop %si 66 5f pop %di 41 58 pop %r8 41 59 pop %r9 41 5a pop %r10 41 5b pop %r11 41 5c pop %r12 41 5d pop %r13 41 5e pop %r14 41 5f pop %r15 66 41 58 pop %r8w 66 41 59 pop %r9w 66 41 5a pop %r10w 66 41 5b pop %r11w 66 41 5c pop %r12w 66 41 5d pop %r13w 66 41 5e pop %r14w 66 41 5f pop %r15w 48 58 rex.W pop %rax 48 59 rex.W pop %rcx 48 5a rex.W pop %rdx 48 5b rex.W pop %rbx 48 5c rex.W pop %rsp 48 5d rex.W pop %rbp 48 5e rex.W pop %rsi 48 5f rex.W pop %rdi 66 48 58 data16 rex.W pop %rax 66 48 59 data16 rex.W pop %rcx 66 48 5a data16 rex.W pop %rdx 66 48 5b data16 rex.W pop %rbx 66 48 5c data16 rex.W pop %rsp 66 48 5d data16 rex.W pop %rbp 66 48 5e data16 rex.W pop %rsi 66 48 5f data16 rex.W pop %rdi 49 58 rex.WB pop %r8 49 59 rex.WB pop %r9 49 5a rex.WB pop %r10 49 5b rex.WB pop %r11 49 5c rex.WB pop %r12 49 5d rex.WB pop %r13 49 5e rex.WB pop %r14 49 5f rex.WB pop %r15 66 49 58 data16 rex.WB pop %r8 66 49 59 data16 rex.WB pop %r9 66 49 5a data16 rex.WB pop %r10 66 49 5b data16 rex.WB pop %r11 66 49 5c data16 rex.WB pop %r12 66 49 5d data16 rex.WB pop %r13 66 49 5e data16 rex.WB pop %r14 66 49 5f data16 rex.WB pop %r15 8f 00 pop (%rax) 8f 04 f4 pop (%rsp, %rsi, 8) 8f 05 f4 f4 f4 f4 pop -0xb0b0b0c(%rip) 8f 06 pop (%rsi) 8f 40 f4 pop -0xc(%rax) 8f c3 pop %rbx 8f c4 pop %rsp 41 8f 00 pop (%r8) 41 8f 04 12 pop (%r10, %rdx, 1) 41 8f 05 12 34 56 78 pop 0x78563412(%rip) 41 8f 06 pop (%r14) 66 8f 00 popw (%rax) 66 8f 04 f4 popw (%rsp, %rsi, 8) 66 8f 05 f4 f4 f4 f4 popw -0xb0b0b0c(%rip) 66 8f 06 popw (%rsi) 66 8f 40 f4 popw -0xc(%rax) 66 8f c3 pop %bx 66 8f c4 pop %sp 66 41 8f 00 popw (%r8) 66 41 8f 04 12 popw (%r10, %rdx, 1) 66 41 8f 05 12 34 56 78 popw 0x78563412(%rip) 66 41 8f 06 popw (%r14) 67 8f 00 pop (%eax) 67 8f 04 f4 pop (%esp, %esi, 8) 67 8f 05 f4 f4 f4 f4 pop -0xb0b0b0c(%eip) 67 8f 06 pop (%esi) 67 8f 40 f4 pop -0xc(%eax) 67 8f c3 addr32 pop %rbx 67 8f c4 addr32 pop %rsp 67 41 8f 00 pop (%r8d) 67 41 8f 04 12 pop (%r10d, %edx, 1) 67 41 8f 05 12 34 56 78 pop 0x78563412(%eip) 67 41 8f 06 pop (%r14d) 66 67 8f 00 popw (%eax) 66 67 8f 04 f4 popw (%esp, %esi, 8) 66 67 8f 05 f4 f4 f4 f4 popw -0xb0b0b0c(%eip) 66 67 8f 06 popw (%esi) 66 67 8f 40 f4 popw -0xc(%eax) 66 67 8f c3 addr32 pop %bx 66 67 8f c4 addr32 pop %sp 66 67 41 8f 00 popw (%r8d) 66 67 41 8f 04 12 popw (%r10d, %edx, 1) 66 67 41 8f 05 12 34 56 78 popw 0x78563412(%eip) 66 67 41 8f 06 popw (%r14d) 66 67 48 8f 00 data16 rex.W pop (%eax) 66 67 48 8f 04 f4 data16 rex.W pop (%esp, %esi, 8) 66 67 48 8f 05 f4 f4 f4 f4 data16 rex.W pop -0xb0b0b0c(%eip) 48 8f 06 rex.W pop (%rsi) 48 8f 40 f4 rex.W pop -0xc(%rax) 48 8f c3 rex.W pop %rbx 48 8f c4 rex.W pop %rsp 49 8f 00 rex.WB pop (%r8) 49 8f 04 f4 rex.WB pop (%r12, %rsi, 8) 49 8f 05 f4 f4 f4 f4 rex.WB pop -0xb0b0b0c(%rip) 49 8f 06 rex.WB pop (%r14) 49 8f 40 f4 rex.WB pop -0xc(%r8) 49 8f c3 rex.WB pop %r11 49 8f c4 rex.WB pop %r12 67 48 8f 06 rex.W pop (%esi) 67 48 8f 40 f4 rex.W pop -0xc(%eax) 67 48 8f c3 addr32 rex.W pop %rbx 67 48 8f c4 addr32 rex.W pop %rsp 67 49 8f 00 rex.WB pop (%r8d) 67 49 8f 04 f4 rex.WB pop (%r12d, %esi, 8) 67 49 8f 05 f4 f4 f4 f4 rex.WB pop -0xb0b0b0c(%eip) 67 49 8f 06 rex.WB pop (%r14d) 67 49 8f 40 f4 rex.WB pop -0xc(%r8d) 67 49 8f c3 addr32 rex.WB pop %r11 67 49 8f c4 addr32 rex.WB pop %r12 9d popf 66 9d popfw 67 9d addr32 popf 66 67 9d addr32 popfw 48 9d rex.W popf 66 48 9d data16 rex.W popf
jared-hughes/defcpu	1,113	tests/disassembly/sources/003_mov32.s	b8 12 34 56 78 mov $0x78563412, %eax b9 12 34 56 78 mov $0x78563412, %ecx ba 12 34 56 78 mov $0x78563412, %edx bb 12 34 56 78 mov $0x78563412, %ebx bc 12 34 56 78 mov $0x78563412, %esp bd 12 34 56 78 mov $0x78563412, %ebp be 12 34 56 78 mov $0x78563412, %esi bf 12 34 56 78 mov $0x78563412, %edi 41 b8 12 34 56 78 mov $0x78563412, %r8d 41 b9 12 34 56 78 mov $0x78563412, %r9d 41 ba 12 34 56 78 mov $0x78563412, %r10d 41 bb 12 34 56 78 mov $0x78563412, %r11d 41 bc 12 34 56 78 mov $0x78563412, %r12d 41 bd 12 34 56 78 mov $0x78563412, %r13d 41 be 12 34 56 78 mov $0x78563412, %r14d 41 bf 12 34 56 78 mov $0x78563412, %r15d 40 b8 12 34 56 78 rex mov $0x78563412, %eax 41 b9 12 34 56 78 mov $0x78563412, %r9d 42 ba 12 34 56 78 rex.X mov $0x78563412, %edx 43 bb 12 34 56 78 rex.XB mov $0x78563412, %r11d 44 bc 12 34 56 78 rex.R mov $0x78563412, %esp 45 bd 12 34 56 78 rex.RB mov $0x78563412, %r13d 46 be 12 34 56 78 rex.RX mov $0x78563412, %esi 47 bf 12 34 56 78 rex.RXB mov $0x78563412, %r15d
jared-hughes/defcpu	6,881	tests/disassembly/sources/014_jcc.s	70 82 jo 0x3fff84 70 12 jo 0x400016 71 12 jno 0x400018 72 12 jb 0x40001a 73 12 jae 0x40001c 74 12 je 0x40001e 75 12 jne 0x400020 76 12 jbe 0x400022 77 12 ja 0x400024 78 12 js 0x400026 79 12 jns 0x400028 7a 12 jp 0x40002a 7b 12 jnp 0x40002c 7c 12 jl 0x40002e 7d 12 jge 0x400030 7e 12 jle 0x400032 7f 12 jg 0x400034 e3 12 jrcxz 0x400036 0f 80 12 34 56 88 jo 0xffffffff8896343c 0f 80 12 34 56 78 jo 0x78963442 0f 81 12 34 56 78 jno 0x78963448 0f 82 12 34 56 78 jb 0x7896344e 0f 83 12 34 56 78 jae 0x78963454 0f 84 12 34 56 78 je 0x7896345a 0f 85 12 34 56 78 jne 0x78963460 0f 86 12 34 56 78 jbe 0x78963466 0f 87 12 34 56 78 ja 0x7896346c 0f 89 12 34 56 78 jns 0x78963472 0f 88 12 34 56 78 js 0x78963478 0f 8a 12 34 56 78 jp 0x7896347e 0f 8b 12 34 56 78 jnp 0x78963484 0f 8c 12 34 56 78 jl 0x7896348a 0f 8d 12 34 56 78 jge 0x78963490 0f 8e 12 34 56 78 jle 0x78963496 0f 8f 12 34 56 78 jg 0x7896349c 66 70 82 data16 jo 0x40000f 66 70 12 data16 jo 0x4000a2 66 71 12 data16 jno 0x4000a5 66 72 12 data16 jb 0x4000a8 66 73 12 data16 jae 0x4000ab 66 74 12 data16 je 0x4000ae 66 75 12 data16 jne 0x4000b1 66 76 12 data16 jbe 0x4000b4 66 77 12 data16 ja 0x4000b7 66 78 12 data16 js 0x4000ba 66 79 12 data16 jns 0x4000bd 66 7a 12 data16 jp 0x4000c0 66 7b 12 data16 jnp 0x4000c3 66 7c 12 data16 jl 0x4000c6 66 7d 12 data16 jge 0x4000c9 66 7e 12 data16 jle 0x4000cc 66 7f 12 data16 jg 0x4000cf 66 e3 12 data16 jrcxz 0x4000d2 66 0f 80 12 34 jo 0x34d7 66 0f 80 12 34 jo 0x34dc 66 0f 81 12 34 jno 0x34e1 66 0f 82 12 34 jb 0x34e6 66 0f 83 12 34 jae 0x34eb 66 0f 84 12 34 je 0x34f0 66 0f 85 12 34 jne 0x34f5 66 0f 86 12 34 jbe 0x34fa 66 0f 87 12 34 ja 0x34ff 66 0f 89 12 34 jns 0x3504 66 0f 88 12 34 js 0x3509 66 0f 8a 12 34 jp 0x350e 66 0f 8b 12 34 jnp 0x3513 66 0f 8c 12 34 jl 0x3518 66 0f 8d 12 34 jge 0x351d 66 0f 8e 12 34 jle 0x3522 66 0f 8f 12 34 jg 0x3527 67 70 82 addr32 jo 0x40009a 67 70 12 addr32 jo 0x40012d 67 71 12 addr32 jno 0x400130 67 72 12 addr32 jb 0x400133 67 73 12 addr32 jae 0x400136 67 74 12 addr32 je 0x400139 67 75 12 addr32 jne 0x40013c 67 76 12 addr32 jbe 0x40013f 67 77 12 addr32 ja 0x400142 67 78 12 addr32 js 0x400145 67 79 12 addr32 jns 0x400148 67 7a 12 addr32 jp 0x40014b 67 7b 12 addr32 jnp 0x40014e 67 7c 12 addr32 jl 0x400151 67 7d 12 addr32 jge 0x400154 67 7e 12 addr32 jle 0x400157 67 7f 12 addr32 jg 0x40015a 67 e3 12 jecxz 0x40015d 67 0f 80 12 34 56 78 addr32 jo 0x78963564 67 0f 80 12 34 56 78 addr32 jo 0x7896356b 67 0f 81 12 34 56 78 addr32 jno 0x78963572 67 0f 82 12 34 56 78 addr32 jb 0x78963579 67 0f 83 12 34 56 78 addr32 jae 0x78963580 67 0f 84 12 34 56 78 addr32 je 0x78963587 67 0f 85 12 34 56 78 addr32 jne 0x7896358e 67 0f 86 12 34 56 78 addr32 jbe 0x78963595 67 0f 87 12 34 56 78 addr32 ja 0x7896359c 67 0f 89 12 34 56 78 addr32 jns 0x789635a3 67 0f 88 12 34 56 78 addr32 js 0x789635aa 67 0f 8a 12 34 56 78 addr32 jp 0x789635b1 67 0f 8b 12 34 56 78 addr32 jnp 0x789635b8 67 0f 8c 12 34 56 78 addr32 jl 0x789635bf 67 0f 8d 12 34 56 78 addr32 jge 0x789635c6 67 0f 8e 12 34 56 78 addr32 jle 0x789635cd 67 0f 8f 12 34 56 78 addr32 jg 0x789635d4 66 67 70 82 data16 addr32 jo 0x400148 66 67 70 12 data16 addr32 jo 0x4001dc 66 67 71 12 data16 addr32 jno 0x4001e0 66 67 72 12 data16 addr32 jb 0x4001e4 66 67 73 12 data16 addr32 jae 0x4001e8 66 67 74 12 data16 addr32 je 0x4001ec 66 67 75 12 data16 addr32 jne 0x4001f0 66 67 76 12 data16 addr32 jbe 0x4001f4 66 67 77 12 data16 addr32 ja 0x4001f8 66 67 78 12 data16 addr32 js 0x4001fc 66 67 79 12 data16 addr32 jns 0x400200 66 67 7a 12 data16 addr32 jp 0x400204 66 67 7b 12 data16 addr32 jnp 0x400208 66 67 7c 12 data16 addr32 jl 0x40020c 66 67 7d 12 data16 addr32 jge 0x400210 66 67 7e 12 data16 addr32 jle 0x400214 66 67 7f 12 data16 addr32 jg 0x400218 66 67 e3 12 data16 jecxz 0x40021c 66 67 0f 80 12 34 addr32 jo 0x3622 66 67 0f 80 12 34 addr32 jo 0x3628 66 67 0f 81 12 34 addr32 jno 0x362e 66 67 0f 82 12 34 addr32 jb 0x3634 66 67 0f 83 12 34 addr32 jae 0x363a 66 67 0f 84 12 34 addr32 je 0x3640 66 67 0f 85 12 34 addr32 jne 0x3646 66 67 0f 86 12 34 addr32 jbe 0x364c 66 67 0f 87 12 34 addr32 ja 0x3652 66 67 0f 89 12 34 addr32 jns 0x3658 66 67 0f 88 12 34 addr32 js 0x365e 66 67 0f 8a 12 34 addr32 jp 0x3664 66 67 0f 8b 12 34 addr32 jnp 0x366a 66 67 0f 8c 12 34 addr32 jl 0x3670 66 67 0f 8d 12 34 addr32 jge 0x3676 66 67 0f 8e 12 34 addr32 jle 0x367c 66 67 0f 8f 12 34 addr32 jg 0x3682 41 70 82 rex.B jo 0x4001f5 41 e3 12 rex.B jrcxz 0x400288 48 70 82 rex.W jo 0x4001fb 48 e3 12 rex.W jrcxz 0x40028e 49 70 82 rex.WB jo 0x400201 49 e3 12 rex.WB jrcxz 0x400294
jared-hughes/defcpu	1,560	tests/disassembly/sources/004_mov64.s	48 b8 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rax 48 b9 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rcx 48 ba 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rdx 48 bb 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rbx 48 bc 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rsp 48 bd 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rbp 48 be 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rsi 48 bf 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rdi 49 b8 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r8 49 b9 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r9 49 ba 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r10 49 bb 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r11 49 bc 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r12 49 bd 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r13 49 be 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r14 49 bf 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r15 4a b8 12 34 56 78 9a bc de ff rex.WX movabs $0xffdebc9a78563412, %rax 4b b8 12 34 56 78 9a bc de ff rex.WXB movabs $0xffdebc9a78563412, %r8 4c b8 12 34 56 78 9a bc de ff rex.WR movabs $0xffdebc9a78563412, %rax 4d b8 12 34 56 78 9a bc de ff rex.WRB movabs $0xffdebc9a78563412, %r8 4e b8 12 34 56 78 9a bc de ff rex.WRX movabs $0xffdebc9a78563412, %rax 4f b8 12 34 56 78 9a bc de ff rex.WRXB movabs $0xffdebc9a78563412, %r8
jared-hughes/defcpu	3,676	tests/disassembly/sources/015_jmp.s	eb 82 jmp 0x3fff84 eb 12 jmp 0x400016 e8 12 34 56 88 call 0xffffffff8896341b e9 12 34 56 88 jmp 0xffffffff88963420 e8 12 34 56 78 call 0x78963425 e9 12 34 56 78 jmp 0x7896342a 66 eb 82 data16 jmp 0x3fff9d 66 eb 12 data16 jmp 0x400030 67 eb 82 addr32 jmp 0x3fffa3 67 eb 12 addr32 jmp 0x400036 66 67 eb 82 data16 addr32 jmp 0x3fffaa 66 67 eb 12 data16 addr32 jmp 0x40003e 41 eb 82 rex.B jmp 0x3fffb1 48 eb 82 rex.W jmp 0x3fffb4 49 eb 82 rex.WB jmp 0x3fffb7 41 e8 12 34 56 78 rex.B call 0x7896344d 41 e9 12 34 56 78 rex.B jmp 0x78963453 48 e8 12 34 56 78 rex.W call 0x78963459 48 e9 12 34 56 78 rex.W jmp 0x7896345f 49 e8 12 34 56 78 rex.WB call 0x78963465 49 e9 12 34 56 78 rex.WB jmp 0x7896346b ff 20 jmp (%rax) ff 24 18 jmp (%rax, %rbx, 1) ff 24 58 jmp (%rax, %rbx, 2) ff 24 98 jmp (%rax, %rbx, 4) ff 24 d8 jmp (%rax, %rbx, 8) 67 ff 24 18 jmp (%eax, %ebx, 1) 67 ff 24 58 jmp (%eax, %ebx, 2) 67 ff 24 98 jmp (%eax, %ebx, 4) 67 ff 24 d8 jmp (%eax, %ebx, 8) 43 ff 24 23 jmp (%r11, %r12, 1) 43 ff 24 63 jmp (%r11, %r12, 2) 43 ff 24 a3 jmp (%r11, %r12, 4) 43 ff 24 e3 jmp (%r11, %r12, 8) 67 43 ff 24 23 jmp (%r11d, %r12d, 1) 67 43 ff 24 63 jmp (%r11d, %r12d, 2) 67 43 ff 24 a3 jmp (%r11d, %r12d, 4) 67 43 ff 24 e3 jmp (%r11d, %r12d, 8) ff 64 18 79 jmp 0x79(%rax, %rbx, 1) ff 64 58 80 jmp -0x80(%rax, %rbx, 2) ff a4 98 80 00 00 00 jmp 0x80(%rax, %rbx, 4) ff a4 d8 7f ff ff ff jmp -0x81(%rax, %rbx, 8) ff 24 1c jmp (%rsp, %rbx, 1) ff 25 12 34 56 78 jmp 0x78563412(%rip) 67 ff 25 12 34 56 78 jmp 0x78563412(%eip) ff 24 20 jmp (%rax, %riz, 1) ff a4 20 12 34 56 78 jmp 0x78563412(%rax, %riz, 1) ff 24 20 jmp (%rax, %riz, 1) ff 24 21 jmp (%rcx, %riz, 1) ff 24 22 jmp (%rdx, %riz, 1) ff 24 23 jmp (%rbx, %riz, 1) ff 24 24 jmp (%rsp) ff 24 25 12 34 56 78 jmp 0x78563412 ff 24 65 12 34 56 78 jmp 0x78563412(, %riz, 2) ff 24 a5 12 34 56 78 jmp 0x78563412(, %riz, 4) ff 24 e5 12 34 56 78 jmp 0x78563412(, %riz, 8) ff 24 26 jmp (%rsi, %riz, 1) ff 24 27 jmp (%rdi, %riz, 1) ff 24 64 jmp (%rsp, %riz, 2) ff 24 a4 jmp (%rsp, %riz, 4) ff 24 e4 jmp (%rsp, %riz, 8) ff 24 ac jmp (%rsp, %rbp, 4) ff 64 20 3a jmp 0x3a(%rax, %riz, 1) ff 64 64 3a jmp 0x3a(%rsp, %riz, 2) ff 64 a4 3a jmp 0x3a(%rsp, %riz, 4) ff 64 e4 3a jmp 0x3a(%rsp, %riz, 8) ff 64 25 3a jmp 0x3a(%rbp, %riz, 1) ff 64 65 3a jmp 0x3a(%rbp, %riz, 2) ff 64 a5 3a jmp 0x3a(%rbp, %riz, 4) ff 64 e5 3a jmp *0x3a(%rbp, %riz, 8) c3 ret
jared-hughes/defcpu	3,072	tests/disassembly/sources/008_prefixes.s	b0 12 mov $0x12, %al 66 b0 12 data16 mov $0x12, %al 67 b0 12 addr32 mov $0x12, %al 66 67 b0 12 data16 addr32 mov $0x12, %al 66 66 67 67 b0 12 data16 data16 addr32 addr32 mov $0x12, %al 67 67 66 66 b0 12 addr32 addr32 data16 data16 mov $0x12, %al 67 66 67 66 b0 12 addr32 data16 addr32 data16 mov $0x12, %al 88 23 mov %ah, (%rbx) 66 88 23 data16 mov %ah, (%rbx) 67 88 23 mov %ah, (%ebx) 66 67 88 23 data16 mov %ah, (%ebx) 66 66 67 67 88 23 data16 data16 addr32 mov %ah, (%ebx) 67 67 66 66 88 23 addr32 data16 data16 mov %ah, (%ebx) 67 66 67 66 88 23 addr32 data16 data16 mov %ah, (%ebx) 40 88 23 mov %spl, (%rbx) 40 rex 66 88 23 data16 mov %ah, (%rbx) 40 rex 67 88 23 mov %ah, (%ebx) 40 rex 66 67 88 23 data16 mov %ah, (%ebx) 40 rex 66 66 67 67 88 23 data16 data16 addr32 mov %ah, (%ebx) 40 rex 67 67 66 66 88 23 addr32 data16 data16 mov %ah, (%ebx) 40 rex 67 66 67 66 88 23 addr32 data16 data16 mov %ah, (%ebx) 40 88 23 mov %spl, (%rbx) 66 40 88 23 data16 mov %spl, (%rbx) 67 40 88 23 mov %spl, (%ebx) 66 67 40 88 23 data16 mov %spl, (%ebx) 66 66 67 67 40 88 23 data16 data16 addr32 mov %spl, (%ebx) 67 67 66 66 40 88 23 addr32 data16 data16 mov %spl, (%ebx) 67 66 67 66 40 88 23 addr32 data16 data16 mov %spl, (%ebx) 48 88 23 rex.W mov %spl, (%rbx) 66 48 88 23 data16 rex.W mov %spl, (%rbx) 67 48 88 23 rex.W mov %spl, (%ebx) 66 67 48 88 23 data16 rex.W mov %spl, (%ebx) 66 66 67 67 48 88 23 data16 data16 addr32 rex.W mov %spl, (%ebx) 67 67 66 66 48 88 23 addr32 data16 data16 rex.W mov %spl, (%ebx) 67 66 67 66 48 88 23 addr32 data16 data16 rex.W mov %spl, (%ebx) 41 88 23 mov %spl, (%r11) 66 41 88 23 data16 mov %spl, (%r11) 67 41 88 23 mov %spl, (%r11d) 66 67 41 88 23 data16 mov %spl, (%r11d) 66 66 67 67 41 88 23 data16 data16 addr32 mov %spl, (%r11d) 67 67 66 66 41 88 23 addr32 data16 data16 mov %spl, (%r11d) 67 66 67 66 41 88 23 addr32 data16 data16 mov %spl, (%r11d) 49 88 23 rex.WB mov %spl, (%r11) 66 49 88 23 data16 rex.WB mov %spl, (%r11) 67 49 88 23 rex.WB mov %spl, (%r11d) 66 67 49 88 23 data16 rex.WB mov %spl, (%r11d) 66 66 67 67 49 88 23 data16 data16 addr32 rex.WB mov %spl, (%r11d) 67 67 66 66 49 88 23 addr32 data16 data16 rex.WB mov %spl, (%r11d) 67 66 67 66 49 88 23 addr32 data16 data16 rex.WB mov %spl, (%r11d)
jared-hughes/defcpu	7,726	tests/disassembly/sources/016_push.s	6a 12 push $0x12 6a a2 push $0xffffffffffffffa2 66 6a 12 pushw $0x12 67 6a 12 addr32 push $0x12 66 67 6a 12 addr32 pushw $0x12 68 12 34 56 78 push $0x78563412 68 a2 b4 c6 d8 push $0xffffffffd8c6b4a2 66 68 12 34 pushw $0x3412 66 68 a2 b4 pushw $0xb4a2 67 68 12 34 56 78 addr32 push $0x78563412 67 68 a2 b4 c6 d8 addr32 push $0xffffffffd8c6b4a2 67 66 68 12 34 addr32 pushw $0x3412 67 66 68 a2 b4 addr32 pushw $0xb4a2 48 6a 12 rex.W push $0x12 48 6a a2 rex.W push $0xffffffffffffffa2 66 48 6a 12 data16 rex.W push $0x12 67 48 6a 12 addr32 rex.W push $0x12 66 67 48 6a 12 data16 addr32 rex.W push $0x12 48 68 12 34 56 78 rex.W push $0x78563412 48 68 a2 b4 c6 d8 rex.W push $0xffffffffd8c6b4a2 66 48 68 12 34 56 78 data16 rex.W push $0x78563412 66 48 68 a2 b4 c6 d8 data16 rex.W push $0xffffffffd8c6b4a2 67 48 68 12 34 56 78 addr32 rex.W push $0x78563412 67 48 68 a2 b4 c6 d8 addr32 rex.W push $0xffffffffd8c6b4a2 67 66 48 68 12 34 56 78 addr32 data16 rex.W push $0x78563412 67 66 48 68 a2 b4 c6 d8 addr32 data16 rex.W push $0xffffffffd8c6b4a2 50 push %rax 51 push %rcx 52 push %rdx 53 push %rbx 54 push %rsp 55 push %rbp 56 push %rsi 57 push %rdi 66 50 push %ax 66 51 push %cx 66 52 push %dx 66 53 push %bx 66 54 push %sp 66 55 push %bp 66 56 push %si 66 57 push %di 41 50 push %r8 41 51 push %r9 41 52 push %r10 41 53 push %r11 41 54 push %r12 41 55 push %r13 41 56 push %r14 41 57 push %r15 66 41 50 push %r8w 66 41 51 push %r9w 66 41 52 push %r10w 66 41 53 push %r11w 66 41 54 push %r12w 66 41 55 push %r13w 66 41 56 push %r14w 66 41 57 push %r15w 48 50 rex.W push %rax 48 51 rex.W push %rcx 48 52 rex.W push %rdx 48 53 rex.W push %rbx 48 54 rex.W push %rsp 48 55 rex.W push %rbp 48 56 rex.W push %rsi 48 57 rex.W push %rdi 66 48 50 data16 rex.W push %rax 66 48 51 data16 rex.W push %rcx 66 48 52 data16 rex.W push %rdx 66 48 53 data16 rex.W push %rbx 66 48 54 data16 rex.W push %rsp 66 48 55 data16 rex.W push %rbp 66 48 56 data16 rex.W push %rsi 66 48 57 data16 rex.W push %rdi 49 50 rex.WB push %r8 49 51 rex.WB push %r9 49 52 rex.WB push %r10 49 53 rex.WB push %r11 49 54 rex.WB push %r12 49 55 rex.WB push %r13 49 56 rex.WB push %r14 49 57 rex.WB push %r15 66 49 50 data16 rex.WB push %r8 66 49 51 data16 rex.WB push %r9 66 49 52 data16 rex.WB push %r10 66 49 53 data16 rex.WB push %r11 66 49 54 data16 rex.WB push %r12 66 49 55 data16 rex.WB push %r13 66 49 56 data16 rex.WB push %r14 66 49 57 data16 rex.WB push %r15 ff 30 push (%rax) ff 34 f4 push (%rsp, %rsi, 8) ff 35 f4 f4 f4 f4 push -0xb0b0b0c(%rip) ff 36 push (%rsi) ff 70 f4 push -0xc(%rax) ff f3 push %rbx ff f4 push %rsp 41 ff 30 push (%r8) 41 ff 34 12 push (%r10, %rdx, 1) 41 ff 35 12 34 56 78 push 0x78563412(%rip) 41 ff 36 push (%r14) 66 ff 30 pushw (%rax) 66 ff 34 f4 pushw (%rsp, %rsi, 8) 66 ff 35 f4 f4 f4 f4 pushw -0xb0b0b0c(%rip) 66 ff 36 pushw (%rsi) 66 ff 70 f4 pushw -0xc(%rax) 66 ff f3 push %bx 66 ff f4 push %sp 66 41 ff 30 pushw (%r8) 66 41 ff 34 12 pushw (%r10, %rdx, 1) 66 41 ff 35 12 34 56 78 pushw 0x78563412(%rip) 66 41 ff 36 pushw (%r14) 67 ff 30 push (%eax) 67 ff 34 f4 push (%esp, %esi, 8) 67 ff 35 f4 f4 f4 f4 push -0xb0b0b0c(%eip) 67 ff 36 push (%esi) 67 ff 70 f4 push -0xc(%eax) 67 ff f3 addr32 push %rbx 67 ff f4 addr32 push %rsp 67 41 ff 30 push (%r8d) 67 41 ff 34 12 push (%r10d, %edx, 1) 67 41 ff 35 12 34 56 78 push 0x78563412(%eip) 67 41 ff 36 push (%r14d) 66 67 ff 30 pushw (%eax) 66 67 ff 34 f4 pushw (%esp, %esi, 8) 66 67 ff 35 f4 f4 f4 f4 pushw -0xb0b0b0c(%eip) 66 67 ff 36 pushw (%esi) 66 67 ff 70 f4 pushw -0xc(%eax) 66 67 ff f3 addr32 push %bx 66 67 ff f4 addr32 push %sp 66 67 41 ff 30 pushw (%r8d) 66 67 41 ff 34 12 pushw (%r10d, %edx, 1) 66 67 41 ff 35 12 34 56 78 pushw 0x78563412(%eip) 66 67 41 ff 36 pushw (%r14d) 66 67 48 ff 30 data16 rex.W push (%eax) 66 67 48 ff 34 f4 data16 rex.W push (%esp, %esi, 8) 66 67 48 ff 35 f4 f4 f4 f4 data16 rex.W push -0xb0b0b0c(%eip) 48 ff 36 rex.W push (%rsi) 48 ff 70 f4 rex.W push -0xc(%rax) 48 ff f3 rex.W push %rbx 48 ff f4 rex.W push %rsp 49 ff 30 rex.WB push (%r8) 49 ff 34 f4 rex.WB push (%r12, %rsi, 8) 49 ff 35 f4 f4 f4 f4 rex.WB push -0xb0b0b0c(%rip) 49 ff 36 rex.WB push (%r14) 49 ff 70 f4 rex.WB push -0xc(%r8) 49 ff f3 rex.WB push %r11 49 ff f4 rex.WB push %r12 67 48 ff 36 rex.W push (%esi) 67 48 ff 70 f4 rex.W push -0xc(%eax) 67 48 ff f3 addr32 rex.W push %rbx 67 48 ff f4 addr32 rex.W push %rsp 67 49 ff 30 rex.WB push (%r8d) 67 49 ff 34 f4 rex.WB push (%r12d, %esi, 8) 67 49 ff 35 f4 f4 f4 f4 rex.WB push -0xb0b0b0c(%eip) 67 49 ff 36 rex.WB push (%r14d) 67 49 ff 70 f4 rex.WB push -0xc(%r8d) 67 49 ff f3 addr32 rex.WB push %r11 67 49 ff f4 addr32 rex.WB push %r12 9c pushf 66 9c pushfw 67 9c addr32 pushf 66 67 9c addr32 pushfw 48 9c rex.W pushf 66 48 9c data16 rex.W pushf
jared-hughes/defcpu	1,180	tests/disassembly/sources/025_bswap.s	0f c8 bswap %eax 0f c9 bswap %ecx 0f ca bswap %edx 0f cb bswap %ebx 0f cc bswap %esp 0f cd bswap %ebp 0f ce bswap %esi 0f cf bswap %edi 40 0f c8 rex bswap %eax 40 0f c9 rex bswap %ecx 40 0f ca rex bswap %edx 40 0f cb rex bswap %ebx 40 0f cc rex bswap %esp 40 0f cd rex bswap %ebp 40 0f ce rex bswap %esi 40 0f cf rex bswap %edi 41 0f c8 bswap %r8d 41 0f c9 bswap %r9d 41 0f ca bswap %r10d 41 0f cb bswap %r11d 41 0f cc bswap %r12d 41 0f cd bswap %r13d 41 0f ce bswap %r14d 41 0f cf bswap %r15d 48 0f c8 bswap %rax 48 0f c9 bswap %rcx 48 0f ca bswap %rdx 48 0f cb bswap %rbx 48 0f cc bswap %rsp 48 0f cd bswap %rbp 48 0f ce bswap %rsi 48 0f cf bswap %rdi 48 0f c8 bswap %rax 48 0f c9 bswap %rcx 48 0f ca bswap %rdx 48 0f cb bswap %rbx 48 0f cc bswap %rsp 48 0f cd bswap %rbp 48 0f ce bswap %rsi 48 0f cf bswap %rdi 49 0f c8 bswap %r8 49 0f c9 bswap %r9 49 0f ca bswap %r10 49 0f cb bswap %r11 49 0f cc bswap %r12 49 0f cd bswap %r13 49 0f ce bswap %r14 49 0f cf bswap %r15
jared-hughes/defcpu	4,971	tests/disassembly/sources/020_imul.s	f6 28 imulb (%rax) f6 e8 imul %al 66 f7 28 imulw (%rax) 66 f7 e8 imul %ax f7 28 imull (%rax) f7 e8 imul %eax 48 f7 28 imulq (%rax) 48 f7 e8 imul %rax 6b 23 12 imul $0x12, (%rbx), %esp 66 0f af 23 imul (%rbx), %sp 67 0f af 23 imul (%ebx), %esp 66 67 0f af 23 imul (%ebx), %sp 40 0f af 23 rex imul (%rbx), %esp 67 40 0f af 23 rex imul (%ebx), %esp 66 40 0f af 23 rex imul (%rbx), %sp 66 67 40 0f af 23 rex imul (%ebx), %sp 41 0f af 23 imul (%r11), %esp 67 41 0f af 23 imul (%r11d), %esp 66 41 0f af 23 imul (%r11), %sp 66 67 41 0f af 23 imul (%r11d), %sp 48 0f af 23 imul (%rbx), %rsp 67 48 0f af 23 imul (%ebx), %rsp 66 48 0f af 23 data16 imul (%rbx), %rsp 66 67 48 0f af 23 data16 imul (%ebx), %rsp 6b 23 12 imul $0x12, (%rbx), %esp 66 6b 23 12 imul $0x12, (%rbx), %sp 67 6b 23 12 imul $0x12, (%ebx), %esp 66 67 6b 23 12 imul $0x12, (%ebx), %sp 40 6b 23 12 rex imul $0x12, (%rbx), %esp 67 40 6b 23 12 rex imul $0x12, (%ebx), %esp 66 40 6b 23 12 rex imul $0x12, (%rbx), %sp 66 67 40 6b 23 12 rex imul $0x12, (%ebx), %sp 41 6b 23 12 imul $0x12, (%r11), %esp 67 41 6b 23 12 imul $0x12, (%r11d), %esp 66 41 6b 23 12 imul $0x12, (%r11), %sp 66 67 41 6b 23 12 imul $0x12, (%r11d), %sp 48 6b 23 12 imul $0x12, (%rbx), %rsp 67 48 6b 23 12 imul $0x12, (%ebx), %rsp 66 48 6b 23 12 data16 imul $0x12, (%rbx), %rsp 66 67 48 6b 23 12 data16 imul $0x12, (%ebx), %rsp 69 23 12 34 56 78 imul $0x78563412, (%rbx), %esp 66 69 23 12 34 imul $0x3412, (%rbx), %sp 67 69 23 12 34 56 78 imul $0x78563412, (%ebx), %esp 66 67 69 23 12 34 imul $0x3412, (%ebx), %sp 40 69 23 12 34 56 78 rex imul $0x78563412, (%rbx), %esp 67 40 69 23 12 34 56 78 rex imul $0x78563412, (%ebx), %esp 66 40 69 23 12 34 rex imul $0x3412, (%rbx), %sp 66 67 40 69 23 12 34 rex imul $0x3412, (%ebx), %sp 41 69 23 12 34 56 78 imul $0x78563412, (%r11), %esp 67 41 69 23 12 34 56 78 imul $0x78563412, (%r11d), %esp 66 41 69 23 12 34 imul $0x3412, (%r11), %sp 66 67 41 69 23 12 34 imul $0x3412, (%r11d), %sp 48 69 23 12 34 56 78 imul $0x78563412, (%rbx), %rsp 67 48 69 23 12 34 56 78 imul $0x78563412, (%ebx), %rsp 66 48 69 23 12 34 56 78 data16 imul $0x78563412, (%rbx), %rsp 66 67 48 69 23 12 34 56 78 data16 imul $0x78563412, (%ebx), %rsp 6b 23 82 imul $0xffffff82, (%rbx), %esp 66 6b 23 82 imul $0xff82, (%rbx), %sp 67 6b 23 82 imul $0xffffff82, (%ebx), %esp 66 67 6b 23 82 imul $0xff82, (%ebx), %sp 40 6b 23 82 rex imul $0xffffff82, (%rbx), %esp 67 40 6b 23 82 rex imul $0xffffff82, (%ebx), %esp 66 40 6b 23 82 rex imul $0xff82, (%rbx), %sp 66 67 40 6b 23 82 rex imul $0xff82, (%ebx), %sp 41 6b 23 82 imul $0xffffff82, (%r11), %esp 67 41 6b 23 82 imul $0xffffff82, (%r11d), %esp 66 41 6b 23 82 imul $0xff82, (%r11), %sp 66 67 41 6b 23 82 imul $0xff82, (%r11d), %sp 48 6b 23 82 imul $0xffffffffffffff82, (%rbx), %rsp 67 48 6b 23 82 imul $0xffffffffffffff82, (%ebx), %rsp 66 48 6b 23 82 data16 imul $0xffffffffffffff82, (%rbx), %rsp 66 67 48 6b 23 82 data16 imul $0xffffffffffffff82, (%ebx), %rsp 69 23 12 34 56 88 imul $0x88563412, (%rbx), %esp 66 69 23 12 84 imul $0x8412, (%rbx), %sp 67 69 23 12 34 56 88 imul $0x88563412, (%ebx), %esp 66 67 69 23 12 84 imul $0x8412, (%ebx), %sp 40 69 23 12 34 56 88 rex imul $0x88563412, (%rbx), %esp 67 40 69 23 12 34 56 88 rex imul $0x88563412, (%ebx), %esp 66 40 69 23 12 84 rex imul $0x8412, (%rbx), %sp 66 67 40 69 23 12 84 rex imul $0x8412, (%ebx), %sp 41 69 23 12 34 56 88 imul $0x88563412, (%r11), %esp 67 41 69 23 12 34 56 88 imul $0x88563412, (%r11d), %esp 66 41 69 23 12 84 imul $0x8412, (%r11), %sp 66 67 41 69 23 12 84 imul $0x8412, (%r11d), %sp 48 69 23 12 34 56 88 imul $0xffffffff88563412, (%rbx), %rsp 67 48 69 23 12 34 56 88 imul $0xffffffff88563412, (%ebx), %rsp 66 48 69 23 12 34 56 88 data16 imul $0xffffffff88563412, (%rbx), %rsp 66 67 48 69 23 12 34 56 88 data16 imul $0xffffffff88563412, (%ebx), %rsp
jasondyoungberg/NyauxKT	224	kernel/src/mem/gdt/flush.s	.global gdt_flush gdt_flush: lgdt [rdi] push 0x28 lea rax, [rip + reload_CS] push rax retfq reload_CS: mov ax, 0x30 mov ds, ax mov es, ax mov fs, ax mov gs, ax mov ss, ax ret
jason-hue/FakeToy	254	sbi-qemu/src/sbi_boot.S	.section ".text.boot" .globl _start _start: /* setup stack with 4KB size / la sp, stacks_start li t0, 4096 add sp, sp, t0 csrw mscratch,sp / goto C */ tail sbi_main .section .data .align 12 .global stacks_start stacks_start: .skip 4096
jason-hue/FakeToy	965	sbi-qemu/src/trap/trap.S	/* _sbi_exception_vector M模式下的异常向量表入口按8字节对齐 / /必须加上.altmacro，不然就用不了宏/ .altmacro .macro save_reg n sd x\n, \n8(sp) .endm .macro restore_reg n ld x\n, \n8(sp) .endm .align 3 .globl _sbi_exception_vector _sbi_exception_vector: /从mscratch 获取M模式的sp指针，并把S模式的sp保存到mscratch/ csrrw sp,mscratch,sp addi sp,sp,-338 sd x1,8(sp) sd x3,38(sp) .set n, 5 .rept 27 save_reg %n .set n,n+1 .endr csrr t0,mepc sd t0,0(sp) csrr t0,mstatus sd t0,328(sp) /将M模式下栈底指针保存到mscratch，以便于下次陷入M模式时可以找到sp/ addi t0,sp,338 csrrw t0,mscratch,t0 sd t0,28(sp) mv a0,sp call sbi_trap_handler /保存返回值/ sd a0,48(sp) ld t0,328(sp) csrw mstatus,t0 ld t0,0(sp) csrw mepc,t0 ld x1,8(sp) ld x3,38(sp) .set n,5 .rept 27 restore_reg %n .set n,n+1 .endr /恢复返回值/ ld a0,48(sp) ld sp,2*8(sp) mret
jason-hue/FakeToy	367	os/src/boot.S	.section ".text.boot" .globl _start _start: /* Mask all interrupts / csrw sie, zero / set the stack of SP, size 4KB / la sp, stacks_start li t0, 40960 add sp, sp, t0 / Clear sscratch / csrw sscratch, zero / goto C */ call kernel_main .section .data.stack .align 12 .global stacks_start stacks_start: .skip 40960 .global stacks_end stacks_end:
jason-hue/FakeToy	1,602	os/src/trap/trap.S	.section .text.trap .altmacro .macro save_reg n sd x\n,\n8(sp) .endm .macro restore_reg n ld x\n,\n8(sp) .endm /* do_exception_vector()必须按4字节对齐否则写入stvec会不成功 / .align 2 .globl do_exception_vectors do_exception_vectors: /检查sstatus的SPP判断是否异常来自U mode/ # x4不需要保存，所以可以用来保存临时值 csrr x4, sstatus andi x4, x4, 1 << 8 # Check SPP bit bnez x4, from_s_mode from_u_mode: # sscratch保存的是S模式的sp，将S模式的栈指针给sp，U模式的sp保存到sscratch csrrw sp, sscratch, sp addi sp,sp,-358 j common_handler from_s_mode: addi sp,sp,-358 sd x2,28(sp) j common_handler common_handler: sd x1,8(sp) sd x3,38(sp) .set n,5 .rept 27 save_reg %n .set n,n+1 .endr csrr s1, sstatus sd s1, 328(sp) csrr s2,sepc sd s2,0(sp) csrr s3,stval sd s3,338(sp) csrr s4,scause sd s4,348(sp) # 不需要保存sscratch就直接跳过 bnez x4, extern_s_mode # 将内核栈底指针保存到sscratch，以便于下次trap找到sp addi s0,sp,358 csrrw s0,sscratch,s0 # 保存U mode sp指针 sd s0,2(sp) la ra,ret_from_exception /传递两个参数：保存trap上下文的栈sp和scause/ mv a0,sp mv a1,s4 call do_exception extern_s_mode: la ra,ret_from_exception /传递两个参数：保存trap上下文的栈sp和scause/ mv a0,sp mv a1,s4 call do_exception ret_from_exception: ld s1,328(sp) csrw sstatus,s1 ld s2,0(sp) csrw sepc,s2 /保存返回值/ sd a0,48(sp) ld x1,8(sp) ld x3,38(sp) .set n,5 .rept 27 restore_reg %n .set n,n+1 .endr # 恢复原始栈指针，实际上完成了栈空间的回收 ld x2,28(sp) ld a0,48(sp) sret
jason-hue/RustOs	17,376	dependencies/riscv/asm.S	#include "asm.h" .section .text.__ebreak .global __ebreak __ebreak: ebreak ret .section .text.__wfi .global __wfi __wfi: wfi ret .section .text.__sfence_vma_all .global __sfence_vma_all __sfence_vma_all: sfence.vma ret .section .text.__sfence_vma .global __sfence_vma __sfence_vma: sfence.vma a0, a1 ret // RISC-V hypervisor instructions. // The switch for enabling LLVM support for asm generation. // #define LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT .section .text.__hfence_gvma .global __hfence_gvma __hfence_gvma: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hfence.gvma a0, a1 #else .word 1656029299 #endif ret .section .text.__hfence_vvma .global __hfence_vvma __hfence_vvma: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hfence.vvma a0, a1 #else .word 582287475 #endif ret .section .text.__hlv_b .global __hlv_b __hlv_b: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.b a0, a0 #else .word 1610958195 #endif ret .section .text.__hlv_bu .global __hlv_bu __hlv_bu: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.bu a0, a0 #else .word 1612006771 #endif ret .section .text.__hlv_h .global __hlv_h __hlv_h: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.h a0, a0 #else .word 1678067059 #endif ret .section .text.__hlv_hu .global __hlv_hu __hlv_hu: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.hu a0, a0 #else .word 1679115635 #endif ret .section .text.__hlvx_hu .global __hlvx_hu __hlvx_hu: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlvx.hu a0, a0 #else .word 1681212787 #endif ret .section .text.__hlv_w .global __hlv_w __hlv_w: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.w a0, a0 #else .word 1745175923 #endif ret .section .text.__hlvx_wu .global __hlvx_wu __hlvx_wu: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlvx.wu a0, a0 #else .word 1748321651 #endif ret .section .text.__hsv_b .global __hsv_b __hsv_b: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hsv.b a0, a1 #else .word 1656045683 #endif ret .section .text.__hsv_h .global __hsv_h __hsv_h: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hsv.h a0, a1 #else .word 1723154547 #endif ret .section .text.__hsv_w .global __hsv_w __hsv_w: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hsv.w a0, a1 #else .word 1790263411 #endif ret .section .text.__hlv_wu .global __hlv_wu __hlv_wu: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.wu a0, a0 #else .word 1746224499 #endif ret .section .text.__hlv_d .global __hlv_d __hlv_d: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.d a0, a0 #else .word 1812284787 #endif ret .section .text.__hsv_d .global __hsv_d __hsv_d: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hsv.d a0, a1 #else .word 1857372275 #endif ret // User Trap Setup RW(0x000, ustatus) // User status register RW(0x004, uie) // User interrupt-enable register RW(0x005, utvec) // User trap handler base address // User Trap Handling RW(0x040, uscratch) // Scratch register for user trap handlers RW(0x041, uepc) // User exception program counter RW(0x042, ucause) // User trap cause RW(0x043, utval) // User bad address or instruction RW(0x044, uip) // User interrupt pending // User Floating-Point CSRs RW(0x001, fflags) // Floating-Point Accrued Exceptions RW(0x002, frm) // Floating-Point Dynamic Rounding Mode RW(0x003, fcsr) // Floating-Point Control and Status Register (frm + fflags) // User Counter/Timers RO( 0xC00, cycle) // Cycle counter for RDCYCLE instruction RO( 0xC01, time) // Timer for RDTIME instruction RO( 0xC02, instret) // Instructions-retired counter for RDINSTRET instruction RO( 0xC03, hpmcounter3) // Performance-monitoring counter RO( 0xC04, hpmcounter4) // Performance-monitoring counter RO( 0xC05, hpmcounter5) // Performance-monitoring counter RO( 0xC06, hpmcounter6) // Performance-monitoring counter RO( 0xC07, hpmcounter7) // Performance-monitoring counter RO( 0xC08, hpmcounter8) // Performance-monitoring counter RO( 0xC09, hpmcounter9) // Performance-monitoring counter RO( 0xC0A, hpmcounter10) // Performance-monitoring counter RO( 0xC0B, hpmcounter11) // Performance-monitoring counter RO( 0xC0C, hpmcounter12) // Performance-monitoring counter RO( 0xC0D, hpmcounter13) // Performance-monitoring counter RO( 0xC0E, hpmcounter14) // Performance-monitoring counter RO( 0xC0F, hpmcounter15) // Performance-monitoring counter RO( 0xC10, hpmcounter16) // Performance-monitoring counter RO( 0xC11, hpmcounter17) // Performance-monitoring counter RO( 0xC12, hpmcounter18) // Performance-monitoring counter RO( 0xC13, hpmcounter19) // Performance-monitoring counter RO( 0xC14, hpmcounter20) // Performance-monitoring counter RO( 0xC15, hpmcounter21) // Performance-monitoring counter RO( 0xC16, hpmcounter22) // Performance-monitoring counter RO( 0xC17, hpmcounter23) // Performance-monitoring counter RO( 0xC18, hpmcounter24) // Performance-monitoring counter RO( 0xC19, hpmcounter25) // Performance-monitoring counter RO( 0xC1A, hpmcounter26) // Performance-monitoring counter RO( 0xC1B, hpmcounter27) // Performance-monitoring counter RO( 0xC1C, hpmcounter28) // Performance-monitoring counter RO( 0xC1D, hpmcounter29) // Performance-monitoring counter RO( 0xC1E, hpmcounter30) // Performance-monitoring counter RO( 0xC1F, hpmcounter31) // Performance-monitoring counter RO32(0xC80, cycleh) // Upper 32 bits of cycle, RV32I only RO32(0xC81, timeh) // Upper 32 bits of time, RV32I only RO32(0xC82, instreth) // Upper 32 bits of instret, RV32I only RO32(0xC83, hpmcounter3h) // Upper 32 bits of hpmcounter3, RV32I only RO32(0xC84, hpmcounter4h) RO32(0xC85, hpmcounter5h) RO32(0xC86, hpmcounter6h) RO32(0xC87, hpmcounter7h) RO32(0xC88, hpmcounter8h) RO32(0xC89, hpmcounter9h) RO32(0xC8A, hpmcounter10h) RO32(0xC8B, hpmcounter11h) RO32(0xC8C, hpmcounter12h) RO32(0xC8D, hpmcounter13h) RO32(0xC8E, hpmcounter14h) RO32(0xC8F, hpmcounter15h) RO32(0xC90, hpmcounter16h) RO32(0xC91, hpmcounter17h) RO32(0xC92, hpmcounter18h) RO32(0xC93, hpmcounter19h) RO32(0xC94, hpmcounter20h) RO32(0xC95, hpmcounter21h) RO32(0xC96, hpmcounter22h) RO32(0xC97, hpmcounter23h) RO32(0xC98, hpmcounter24h) RO32(0xC99, hpmcounter25h) RO32(0xC9A, hpmcounter26h) RO32(0xC9B, hpmcounter27h) RO32(0xC9C, hpmcounter28h) RO32(0xC9D, hpmcounter29h) RO32(0xC9E, hpmcounter30h) RO32(0xC9F, hpmcounter31h) // Supervisor Trap Setup RW(0x100, sstatus) // Supervisor status register RW(0x102, sedeleg) // Supervisor exception delegation register RW(0x103, sideleg) // Supervisor interrupt delegation register RW(0x104, sie) // Supervisor interrupt-enable register RW(0x105, stvec) // Supervisor trap handler base address RW(0x106, scounteren) // Supervisor counter enable // Supervisor Trap Handling RW(0x140, sscratch) // Scratch register for supervisor trap handlers RW(0x141, sepc) // Supervisor exception program counter RW(0x142, scause) // Supervisor trap cause RW(0x143, stval) // Supervisor bad address or instruction RW(0x144, sip) // Supervisor interrupt pending // Supervisor Protection and Translation RW(0x180, satp) // Supervisor address translation and protection // Machine Information Registers RO(0xF11, mvendorid) // Vendor ID RO(0xF12, marchid) // Architecture ID RO(0xF13, mimpid) // Implementation ID RO(0xF14, mhartid) // Hardware thread ID // Machine Trap Setup RW(0x300, mstatus) // Machine status register RW(0x301, misa) // ISA and extensions RW(0x302, medeleg) // Machine exception delegation register RW(0x303, mideleg) // Machine interrupt delegation register RW(0x304, mie) // Machine interrupt-enable register RW(0x305, mtvec) // Machine trap handler base address RW(0x306, mcounteren) // Machine counter enable // Machine Trap Handling RW(0x340, mscratch) // Scratch register for machine trap handlers RW(0x341, mepc) // Machine exception program counter RW(0x342, mcause) // Machine trap cause RW(0x343, mtval) // Machine bad address or instruction RW(0x344, mip) // Machine interrupt pending // Machine Protection and Translation RW( 0x3A0, pmpcfg0) // Physical memory protection configuration RW32(0x3A1, pmpcfg1) // Physical memory protection configuration, RV32 only RW( 0x3A2, pmpcfg2) // Physical memory protection configuration RW32(0x3A3, pmpcfg3) // Physical memory protection configuration, RV32 only RW( 0x3B0, pmpaddr0) // Physical memory protection address register RW( 0x3B1, pmpaddr1) // Physical memory protection address register RW( 0x3B2, pmpaddr2) // Physical memory protection address register RW( 0x3B3, pmpaddr3) // Physical memory protection address register RW( 0x3B4, pmpaddr4) // Physical memory protection address register RW( 0x3B5, pmpaddr5) // Physical memory protection address register RW( 0x3B6, pmpaddr6) // Physical memory protection address register RW( 0x3B7, pmpaddr7) // Physical memory protection address register RW( 0x3B8, pmpaddr8) // Physical memory protection address register RW( 0x3B9, pmpaddr9) // Physical memory protection address register RW( 0x3BA, pmpaddr10) // Physical memory protection address register RW( 0x3BB, pmpaddr11) // Physical memory protection address register RW( 0x3BC, pmpaddr12) // Physical memory protection address register RW( 0x3BD, pmpaddr13) // Physical memory protection address register RW( 0x3BE, pmpaddr14) // Physical memory protection address register RW( 0x3BF, pmpaddr15) // Physical memory protection address register // Machine Counter/Timers RO( 0xB00, mcycle) // Machine cycle counter RO( 0xB02, minstret) // Machine instructions-retired counter RO( 0xB03, mhpmcounter3) // Machine performance-monitoring counter RO( 0xB04, mhpmcounter4) // Machine performance-monitoring counter RO( 0xB05, mhpmcounter5) // Machine performance-monitoring counter RO( 0xB06, mhpmcounter6) // Machine performance-monitoring counter RO( 0xB07, mhpmcounter7) // Machine performance-monitoring counter RO( 0xB08, mhpmcounter8) // Machine performance-monitoring counter RO( 0xB09, mhpmcounter9) // Machine performance-monitoring counter RO( 0xB0A, mhpmcounter10) // Machine performance-monitoring counter RO( 0xB0B, mhpmcounter11) // Machine performance-monitoring counter RO( 0xB0C, mhpmcounter12) // Machine performance-monitoring counter RO( 0xB0D, mhpmcounter13) // Machine performance-monitoring counter RO( 0xB0E, mhpmcounter14) // Machine performance-monitoring counter RO( 0xB0F, mhpmcounter15) // Machine performance-monitoring counter RO( 0xB10, mhpmcounter16) // Machine performance-monitoring counter RO( 0xB11, mhpmcounter17) // Machine performance-monitoring counter RO( 0xB12, mhpmcounter18) // Machine performance-monitoring counter RO( 0xB13, mhpmcounter19) // Machine performance-monitoring counter RO( 0xB14, mhpmcounter20) // Machine performance-monitoring counter RO( 0xB15, mhpmcounter21) // Machine performance-monitoring counter RO( 0xB16, mhpmcounter22) // Machine performance-monitoring counter RO( 0xB17, mhpmcounter23) // Machine performance-monitoring counter RO( 0xB18, mhpmcounter24) // Machine performance-monitoring counter RO( 0xB19, mhpmcounter25) // Machine performance-monitoring counter RO( 0xB1A, mhpmcounter26) // Machine performance-monitoring counter RO( 0xB1B, mhpmcounter27) // Machine performance-monitoring counter RO( 0xB1C, mhpmcounter28) // Machine performance-monitoring counter RO( 0xB1D, mhpmcounter29) // Machine performance-monitoring counter RO( 0xB1E, mhpmcounter30) // Machine performance-monitoring counter RO( 0xB1F, mhpmcounter31) // Machine performance-monitoring counter RO32(0xB80, mcycleh) // Upper 32 bits of mcycle, RV32I only RO32(0xB82, minstreth) // Upper 32 bits of minstret, RV32I only RO32(0xB83, mhpmcounter3h) // Upper 32 bits of mhpmcounter3, RV32I only RO32(0xB84, mhpmcounter4h) RO32(0xB85, mhpmcounter5h) RO32(0xB86, mhpmcounter6h) RO32(0xB87, mhpmcounter7h) RO32(0xB88, mhpmcounter8h) RO32(0xB89, mhpmcounter9h) RO32(0xB8A, mhpmcounter10h) RO32(0xB8B, mhpmcounter11h) RO32(0xB8C, mhpmcounter12h) RO32(0xB8D, mhpmcounter13h) RO32(0xB8E, mhpmcounter14h) RO32(0xB8F, mhpmcounter15h) RO32(0xB90, mhpmcounter16h) RO32(0xB91, mhpmcounter17h) RO32(0xB92, mhpmcounter18h) RO32(0xB93, mhpmcounter19h) RO32(0xB94, mhpmcounter20h) RO32(0xB95, mhpmcounter21h) RO32(0xB96, mhpmcounter22h) RO32(0xB97, mhpmcounter23h) RO32(0xB98, mhpmcounter24h) RO32(0xB99, mhpmcounter25h) RO32(0xB9A, mhpmcounter26h) RO32(0xB9B, mhpmcounter27h) RO32(0xB9C, mhpmcounter28h) RO32(0xB9D, mhpmcounter29h) RO32(0xB9E, mhpmcounter30h) RO32(0xB9F, mhpmcounter31h) RW(0x323, mhpmevent3) // Machine performance-monitoring event selector RW(0x324, mhpmevent4) // Machine performance-monitoring event selector RW(0x325, mhpmevent5) // Machine performance-monitoring event selector RW(0x326, mhpmevent6) // Machine performance-monitoring event selector RW(0x327, mhpmevent7) // Machine performance-monitoring event selector RW(0x328, mhpmevent8) // Machine performance-monitoring event selector RW(0x329, mhpmevent9) // Machine performance-monitoring event selector RW(0x32A, mhpmevent10) // Machine performance-monitoring event selector RW(0x32B, mhpmevent11) // Machine performance-monitoring event selector RW(0x32C, mhpmevent12) // Machine performance-monitoring event selector RW(0x32D, mhpmevent13) // Machine performance-monitoring event selector RW(0x32E, mhpmevent14) // Machine performance-monitoring event selector RW(0x32F, mhpmevent15) // Machine performance-monitoring event selector RW(0x330, mhpmevent16) // Machine performance-monitoring event selector RW(0x331, mhpmevent17) // Machine performance-monitoring event selector RW(0x332, mhpmevent18) // Machine performance-monitoring event selector RW(0x333, mhpmevent19) // Machine performance-monitoring event selector RW(0x334, mhpmevent20) // Machine performance-monitoring event selector RW(0x335, mhpmevent21) // Machine performance-monitoring event selector RW(0x336, mhpmevent22) // Machine performance-monitoring event selector RW(0x337, mhpmevent23) // Machine performance-monitoring event selector RW(0x338, mhpmevent24) // Machine performance-monitoring event selector RW(0x339, mhpmevent25) // Machine performance-monitoring event selector RW(0x33A, mhpmevent26) // Machine performance-monitoring event selector RW(0x33B, mhpmevent27) // Machine performance-monitoring event selector RW(0x33C, mhpmevent28) // Machine performance-monitoring event selector RW(0x33D, mhpmevent29) // Machine performance-monitoring event selector RW(0x33E, mhpmevent30) // Machine performance-monitoring event selector RW(0x33F, mhpmevent31) // Machine performance-monitoring event selector // Debug/Trace Registers (shared with Debug Mode) RW(0x7A0, tselect) // Debug/Trace trigger register select RW(0x7A1, tdata1) // First Debug/Trace trigger data register RW(0x7A2, tdata2) // Second Debug/Trace trigger data register RW(0x7A3, tdata3) // Third Debug/Trace trigger data register // Debug Mode Registers RW(0x7B0, dcsr) // Debug control and status register RW(0x7B1, dpc) // Debug PC RW(0x7B2, dscratch) // Debug scratch register // Hypervisor Trap Setup RW(0x600, hstatus) // Hypervisor status register RW(0x602, hedeleg) // Hypervisor exception delegation register RW(0x603, hideleg) // Hypervisor interrupt delegation register RW(0x604, hie) // Hypervisor interrupt-enable register RW(0x606, hcounteren) // Hypervisor counter enable RW(0x607, hgeie) // Hypervisor guest external interrupt-enable register // Hypervisor Trap Handling RW(0x643, htval) // Hypervisor bad guest physical address RW(0x644, hip) // Hypervisor interrupt pending RW(0x645, hvip) // Hypervisor virtual interrupt pending RW(0x64a, htinst) // Hypervisor trap instruction (transformed) RW(0xe12, hgeip) // Hypervisor guest external interrupt pending // Hypervisor Protection and Translation RO(0x680, hgatp) // Hypervisor guest address translation and protection // Debug/Trace Registers RW(0x6a8, hcontext) // Hypervisor-mode context register // Hypervisor Counter/Timer Virtualization Registers RW(0x605, htimedelta) // Delta for VS/VU-mode timer RW32(0x615, htimedeltah) // Upper 32 bits of {\tt htimedelta}, RV32 only // Virtual Supervisor Registers RW(0x200, vsstatus) // Virtual supervisor status register RW(0x204, vsie) // Virtual supervisor interrupt-enable register RW(0x205, vstvec) // Virtual supervisor trap handler base address RW(0x240, vsscratch) // Virtual supervisor scratch register RW(0x241, vsepc) // Virtual supervisor exception program counter RW(0x242, vscause) // Virtual supervisor trap cause RW(0x243, vstval) // Virtual supervisor bad address or instruction RW(0x244, vsip) // Virtual supervisor interrupt pending RW(0x280, vsatp) // Virtual supervisor address translation and protection
jason-hue/RustOs	3,978	os/src/link_app.S	.align 3 .section .data .global _num_app _num_app: .quad 17 .quad app_0_start .quad app_1_start .quad app_2_start .quad app_3_start .quad app_4_start .quad app_5_start .quad app_6_start .quad app_7_start .quad app_8_start .quad app_9_start .quad app_10_start .quad app_11_start .quad app_12_start .quad app_13_start .quad app_14_start .quad app_15_start .quad app_16_start .quad app_16_end .global _app_names _app_names: .string "exit" .string "fantastic_text" .string "forkexec" .string "forktest" .string "forktest2" .string "forktest_simple" .string "forktree" .string "hello_world" .string "initproc" .string "matrix" .string "sleep" .string "sleep_simple" .string "stack_overflow" .string "user_shell" .string "usertests" .string "usertests-simple" .string "yield" .section .data .global app_0_start .global app_0_end .align 3 app_0_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/exit" app_0_end: .section .data .global app_1_start .global app_1_end .align 3 app_1_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/fantastic_text" app_1_end: .section .data .global app_2_start .global app_2_end .align 3 app_2_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/forkexec" app_2_end: .section .data .global app_3_start .global app_3_end .align 3 app_3_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/forktest" app_3_end: .section .data .global app_4_start .global app_4_end .align 3 app_4_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/forktest2" app_4_end: .section .data .global app_5_start .global app_5_end .align 3 app_5_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/forktest_simple" app_5_end: .section .data .global app_6_start .global app_6_end .align 3 app_6_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/forktree" app_6_end: .section .data .global app_7_start .global app_7_end .align 3 app_7_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/hello_world" app_7_end: .section .data .global app_8_start .global app_8_end .align 3 app_8_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/initproc" app_8_end: .section .data .global app_9_start .global app_9_end .align 3 app_9_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/matrix" app_9_end: .section .data .global app_10_start .global app_10_end .align 3 app_10_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/sleep" app_10_end: .section .data .global app_11_start .global app_11_end .align 3 app_11_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/sleep_simple" app_11_end: .section .data .global app_12_start .global app_12_end .align 3 app_12_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/stack_overflow" app_12_end: .section .data .global app_13_start .global app_13_end .align 3 app_13_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/user_shell" app_13_end: .section .data .global app_14_start .global app_14_end .align 3 app_14_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/usertests" app_14_end: .section .data .global app_15_start .global app_15_end .align 3 app_15_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/usertests-simple" app_15_end: .section .data .global app_16_start .global app_16_end .align 3 app_16_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/yield" app_16_end:

j4yc3-mw/Viren

40,476

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/chacha-armv8-win64.S

// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32) #include <ring-core/arm_arch.h> .section .rodata .align 5 Lsigma: .quad 0x3320646e61707865,0x6b20657479622d32 // endian-neutral Lone: .long 1,0,0,0 .byte 67,104,97,67,104,97,50,48,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 .align 2 .text .globl ChaCha20_ctr32 .def ChaCha20_ctr32 .type 32 .endef .align 5 ChaCha20_ctr32: AARCH64_VALID_CALL_TARGET cbz x2,Labort #if defined(OPENSSL_HWASAN) && __clang_major__ >= 10 adrp x5,:pg_hi21_nc:OPENSSL_armcap_P #else adrp x5,OPENSSL_armcap_P #endif cmp x2,#192 b.lo Lshort ldr w17,[x5,:lo12:OPENSSL_armcap_P] tst w17,#ARMV7_NEON b.ne ChaCha20_neon Lshort: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-96]! add x29,sp,#0 adrp x5,Lsigma add x5,x5,:lo12:Lsigma stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] stp x25,x26,[sp,#64] stp x27,x28,[sp,#80] sub sp,sp,#64 ldp x22,x23,[x5] // load sigma ldp x24,x25,[x3] // load key ldp x26,x27,[x3,#16] ldp x28,x30,[x4] // load counter #ifdef __AARCH64EB__ ror x24,x24,#32 ror x25,x25,#32 ror x26,x26,#32 ror x27,x27,#32 ror x28,x28,#32 ror x30,x30,#32 #endif Loop_outer: mov w5,w22 // unpack key block lsr x6,x22,#32 mov w7,w23 lsr x8,x23,#32 mov w9,w24 lsr x10,x24,#32 mov w11,w25 lsr x12,x25,#32 mov w13,w26 lsr x14,x26,#32 mov w15,w27 lsr x16,x27,#32 mov w17,w28 lsr x19,x28,#32 mov w20,w30 lsr x21,x30,#32 mov x4,#10 subs x2,x2,#64 Loop: sub x4,x4,#1 add w5,w5,w9 add w6,w6,w10 add w7,w7,w11 add w8,w8,w12 eor w17,w17,w5 eor w19,w19,w6 eor w20,w20,w7 eor w21,w21,w8 ror w17,w17,#16 ror w19,w19,#16 ror w20,w20,#16 ror w21,w21,#16 add w13,w13,w17 add w14,w14,w19 add w15,w15,w20 add w16,w16,w21 eor w9,w9,w13 eor w10,w10,w14 eor w11,w11,w15 eor w12,w12,w16 ror w9,w9,#20 ror w10,w10,#20 ror w11,w11,#20 ror w12,w12,#20 add w5,w5,w9 add w6,w6,w10 add w7,w7,w11 add w8,w8,w12 eor w17,w17,w5 eor w19,w19,w6 eor w20,w20,w7 eor w21,w21,w8 ror w17,w17,#24 ror w19,w19,#24 ror w20,w20,#24 ror w21,w21,#24 add w13,w13,w17 add w14,w14,w19 add w15,w15,w20 add w16,w16,w21 eor w9,w9,w13 eor w10,w10,w14 eor w11,w11,w15 eor w12,w12,w16 ror w9,w9,#25 ror w10,w10,#25 ror w11,w11,#25 ror w12,w12,#25 add w5,w5,w10 add w6,w6,w11 add w7,w7,w12 add w8,w8,w9 eor w21,w21,w5 eor w17,w17,w6 eor w19,w19,w7 eor w20,w20,w8 ror w21,w21,#16 ror w17,w17,#16 ror w19,w19,#16 ror w20,w20,#16 add w15,w15,w21 add w16,w16,w17 add w13,w13,w19 add w14,w14,w20 eor w10,w10,w15 eor w11,w11,w16 eor w12,w12,w13 eor w9,w9,w14 ror w10,w10,#20 ror w11,w11,#20 ror w12,w12,#20 ror w9,w9,#20 add w5,w5,w10 add w6,w6,w11 add w7,w7,w12 add w8,w8,w9 eor w21,w21,w5 eor w17,w17,w6 eor w19,w19,w7 eor w20,w20,w8 ror w21,w21,#24 ror w17,w17,#24 ror w19,w19,#24 ror w20,w20,#24 add w15,w15,w21 add w16,w16,w17 add w13,w13,w19 add w14,w14,w20 eor w10,w10,w15 eor w11,w11,w16 eor w12,w12,w13 eor w9,w9,w14 ror w10,w10,#25 ror w11,w11,#25 ror w12,w12,#25 ror w9,w9,#25 cbnz x4,Loop add w5,w5,w22 // accumulate key block add x6,x6,x22,lsr#32 add w7,w7,w23 add x8,x8,x23,lsr#32 add w9,w9,w24 add x10,x10,x24,lsr#32 add w11,w11,w25 add x12,x12,x25,lsr#32 add w13,w13,w26 add x14,x14,x26,lsr#32 add w15,w15,w27 add x16,x16,x27,lsr#32 add w17,w17,w28 add x19,x19,x28,lsr#32 add w20,w20,w30 add x21,x21,x30,lsr#32 b.lo Ltail add x5,x5,x6,lsl#32 // pack add x7,x7,x8,lsl#32 ldp x6,x8,[x1,#0] // load input add x9,x9,x10,lsl#32 add x11,x11,x12,lsl#32 ldp x10,x12,[x1,#16] add x13,x13,x14,lsl#32 add x15,x15,x16,lsl#32 ldp x14,x16,[x1,#32] add x17,x17,x19,lsl#32 add x20,x20,x21,lsl#32 ldp x19,x21,[x1,#48] add x1,x1,#64 #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif eor x5,x5,x6 eor x7,x7,x8 eor x9,x9,x10 eor x11,x11,x12 eor x13,x13,x14 eor x15,x15,x16 eor x17,x17,x19 eor x20,x20,x21 stp x5,x7,[x0,#0] // store output add x28,x28,#1 // increment counter stp x9,x11,[x0,#16] stp x13,x15,[x0,#32] stp x17,x20,[x0,#48] add x0,x0,#64 b.hi Loop_outer ldp x19,x20,[x29,#16] add sp,sp,#64 ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER Labort: ret .align 4 Ltail: add x2,x2,#64 Less_than_64: sub x0,x0,#1 add x1,x1,x2 add x0,x0,x2 add x4,sp,x2 neg x2,x2 add x5,x5,x6,lsl#32 // pack add x7,x7,x8,lsl#32 add x9,x9,x10,lsl#32 add x11,x11,x12,lsl#32 add x13,x13,x14,lsl#32 add x15,x15,x16,lsl#32 add x17,x17,x19,lsl#32 add x20,x20,x21,lsl#32 #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif stp x5,x7,[sp,#0] stp x9,x11,[sp,#16] stp x13,x15,[sp,#32] stp x17,x20,[sp,#48] Loop_tail: ldrb w10,[x1,x2] ldrb w11,[x4,x2] add x2,x2,#1 eor w10,w10,w11 strb w10,[x0,x2] cbnz x2,Loop_tail stp xzr,xzr,[sp,#0] stp xzr,xzr,[sp,#16] stp xzr,xzr,[sp,#32] stp xzr,xzr,[sp,#48] ldp x19,x20,[x29,#16] add sp,sp,#64 ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret .def ChaCha20_neon .type 32 .endef .align 5 ChaCha20_neon: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-96]! add x29,sp,#0 adrp x5,Lsigma add x5,x5,:lo12:Lsigma stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] stp x25,x26,[sp,#64] stp x27,x28,[sp,#80] cmp x2,#512 b.hs L512_or_more_neon sub sp,sp,#64 ldp x22,x23,[x5] // load sigma ld1 {v24.4s},[x5],#16 ldp x24,x25,[x3] // load key ldp x26,x27,[x3,#16] ld1 {v25.4s,v26.4s},[x3] ldp x28,x30,[x4] // load counter ld1 {v27.4s},[x4] ld1 {v31.4s},[x5] #ifdef __AARCH64EB__ rev64 v24.4s,v24.4s ror x24,x24,#32 ror x25,x25,#32 ror x26,x26,#32 ror x27,x27,#32 ror x28,x28,#32 ror x30,x30,#32 #endif add v27.4s,v27.4s,v31.4s // += 1 add v28.4s,v27.4s,v31.4s add v29.4s,v28.4s,v31.4s shl v31.4s,v31.4s,#2 // 1 -> 4 Loop_outer_neon: mov w5,w22 // unpack key block lsr x6,x22,#32 mov v0.16b,v24.16b mov w7,w23 lsr x8,x23,#32 mov v4.16b,v24.16b mov w9,w24 lsr x10,x24,#32 mov v16.16b,v24.16b mov w11,w25 mov v1.16b,v25.16b lsr x12,x25,#32 mov v5.16b,v25.16b mov w13,w26 mov v17.16b,v25.16b lsr x14,x26,#32 mov v3.16b,v27.16b mov w15,w27 mov v7.16b,v28.16b lsr x16,x27,#32 mov v19.16b,v29.16b mov w17,w28 mov v2.16b,v26.16b lsr x19,x28,#32 mov v6.16b,v26.16b mov w20,w30 mov v18.16b,v26.16b lsr x21,x30,#32 mov x4,#10 subs x2,x2,#256 Loop_neon: sub x4,x4,#1 add v0.4s,v0.4s,v1.4s add w5,w5,w9 add v4.4s,v4.4s,v5.4s add w6,w6,w10 add v16.4s,v16.4s,v17.4s add w7,w7,w11 eor v3.16b,v3.16b,v0.16b add w8,w8,w12 eor v7.16b,v7.16b,v4.16b eor w17,w17,w5 eor v19.16b,v19.16b,v16.16b eor w19,w19,w6 rev32 v3.8h,v3.8h eor w20,w20,w7 rev32 v7.8h,v7.8h eor w21,w21,w8 rev32 v19.8h,v19.8h ror w17,w17,#16 add v2.4s,v2.4s,v3.4s ror w19,w19,#16 add v6.4s,v6.4s,v7.4s ror w20,w20,#16 add v18.4s,v18.4s,v19.4s ror w21,w21,#16 eor v20.16b,v1.16b,v2.16b add w13,w13,w17 eor v21.16b,v5.16b,v6.16b add w14,w14,w19 eor v22.16b,v17.16b,v18.16b add w15,w15,w20 ushr v1.4s,v20.4s,#20 add w16,w16,w21 ushr v5.4s,v21.4s,#20 eor w9,w9,w13 ushr v17.4s,v22.4s,#20 eor w10,w10,w14 sli v1.4s,v20.4s,#12 eor w11,w11,w15 sli v5.4s,v21.4s,#12 eor w12,w12,w16 sli v17.4s,v22.4s,#12 ror w9,w9,#20 add v0.4s,v0.4s,v1.4s ror w10,w10,#20 add v4.4s,v4.4s,v5.4s ror w11,w11,#20 add v16.4s,v16.4s,v17.4s ror w12,w12,#20 eor v20.16b,v3.16b,v0.16b add w5,w5,w9 eor v21.16b,v7.16b,v4.16b add w6,w6,w10 eor v22.16b,v19.16b,v16.16b add w7,w7,w11 ushr v3.4s,v20.4s,#24 add w8,w8,w12 ushr v7.4s,v21.4s,#24 eor w17,w17,w5 ushr v19.4s,v22.4s,#24 eor w19,w19,w6 sli v3.4s,v20.4s,#8 eor w20,w20,w7 sli v7.4s,v21.4s,#8 eor w21,w21,w8 sli v19.4s,v22.4s,#8 ror w17,w17,#24 add v2.4s,v2.4s,v3.4s ror w19,w19,#24 add v6.4s,v6.4s,v7.4s ror w20,w20,#24 add v18.4s,v18.4s,v19.4s ror w21,w21,#24 eor v20.16b,v1.16b,v2.16b add w13,w13,w17 eor v21.16b,v5.16b,v6.16b add w14,w14,w19 eor v22.16b,v17.16b,v18.16b add w15,w15,w20 ushr v1.4s,v20.4s,#25 add w16,w16,w21 ushr v5.4s,v21.4s,#25 eor w9,w9,w13 ushr v17.4s,v22.4s,#25 eor w10,w10,w14 sli v1.4s,v20.4s,#7 eor w11,w11,w15 sli v5.4s,v21.4s,#7 eor w12,w12,w16 sli v17.4s,v22.4s,#7 ror w9,w9,#25 ext v2.16b,v2.16b,v2.16b,#8 ror w10,w10,#25 ext v6.16b,v6.16b,v6.16b,#8 ror w11,w11,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w12,w12,#25 ext v3.16b,v3.16b,v3.16b,#12 ext v7.16b,v7.16b,v7.16b,#12 ext v19.16b,v19.16b,v19.16b,#12 ext v1.16b,v1.16b,v1.16b,#4 ext v5.16b,v5.16b,v5.16b,#4 ext v17.16b,v17.16b,v17.16b,#4 add v0.4s,v0.4s,v1.4s add w5,w5,w10 add v4.4s,v4.4s,v5.4s add w6,w6,w11 add v16.4s,v16.4s,v17.4s add w7,w7,w12 eor v3.16b,v3.16b,v0.16b add w8,w8,w9 eor v7.16b,v7.16b,v4.16b eor w21,w21,w5 eor v19.16b,v19.16b,v16.16b eor w17,w17,w6 rev32 v3.8h,v3.8h eor w19,w19,w7 rev32 v7.8h,v7.8h eor w20,w20,w8 rev32 v19.8h,v19.8h ror w21,w21,#16 add v2.4s,v2.4s,v3.4s ror w17,w17,#16 add v6.4s,v6.4s,v7.4s ror w19,w19,#16 add v18.4s,v18.4s,v19.4s ror w20,w20,#16 eor v20.16b,v1.16b,v2.16b add w15,w15,w21 eor v21.16b,v5.16b,v6.16b add w16,w16,w17 eor v22.16b,v17.16b,v18.16b add w13,w13,w19 ushr v1.4s,v20.4s,#20 add w14,w14,w20 ushr v5.4s,v21.4s,#20 eor w10,w10,w15 ushr v17.4s,v22.4s,#20 eor w11,w11,w16 sli v1.4s,v20.4s,#12 eor w12,w12,w13 sli v5.4s,v21.4s,#12 eor w9,w9,w14 sli v17.4s,v22.4s,#12 ror w10,w10,#20 add v0.4s,v0.4s,v1.4s ror w11,w11,#20 add v4.4s,v4.4s,v5.4s ror w12,w12,#20 add v16.4s,v16.4s,v17.4s ror w9,w9,#20 eor v20.16b,v3.16b,v0.16b add w5,w5,w10 eor v21.16b,v7.16b,v4.16b add w6,w6,w11 eor v22.16b,v19.16b,v16.16b add w7,w7,w12 ushr v3.4s,v20.4s,#24 add w8,w8,w9 ushr v7.4s,v21.4s,#24 eor w21,w21,w5 ushr v19.4s,v22.4s,#24 eor w17,w17,w6 sli v3.4s,v20.4s,#8 eor w19,w19,w7 sli v7.4s,v21.4s,#8 eor w20,w20,w8 sli v19.4s,v22.4s,#8 ror w21,w21,#24 add v2.4s,v2.4s,v3.4s ror w17,w17,#24 add v6.4s,v6.4s,v7.4s ror w19,w19,#24 add v18.4s,v18.4s,v19.4s ror w20,w20,#24 eor v20.16b,v1.16b,v2.16b add w15,w15,w21 eor v21.16b,v5.16b,v6.16b add w16,w16,w17 eor v22.16b,v17.16b,v18.16b add w13,w13,w19 ushr v1.4s,v20.4s,#25 add w14,w14,w20 ushr v5.4s,v21.4s,#25 eor w10,w10,w15 ushr v17.4s,v22.4s,#25 eor w11,w11,w16 sli v1.4s,v20.4s,#7 eor w12,w12,w13 sli v5.4s,v21.4s,#7 eor w9,w9,w14 sli v17.4s,v22.4s,#7 ror w10,w10,#25 ext v2.16b,v2.16b,v2.16b,#8 ror w11,w11,#25 ext v6.16b,v6.16b,v6.16b,#8 ror w12,w12,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w9,w9,#25 ext v3.16b,v3.16b,v3.16b,#4 ext v7.16b,v7.16b,v7.16b,#4 ext v19.16b,v19.16b,v19.16b,#4 ext v1.16b,v1.16b,v1.16b,#12 ext v5.16b,v5.16b,v5.16b,#12 ext v17.16b,v17.16b,v17.16b,#12 cbnz x4,Loop_neon add w5,w5,w22 // accumulate key block add v0.4s,v0.4s,v24.4s add x6,x6,x22,lsr#32 add v4.4s,v4.4s,v24.4s add w7,w7,w23 add v16.4s,v16.4s,v24.4s add x8,x8,x23,lsr#32 add v2.4s,v2.4s,v26.4s add w9,w9,w24 add v6.4s,v6.4s,v26.4s add x10,x10,x24,lsr#32 add v18.4s,v18.4s,v26.4s add w11,w11,w25 add v3.4s,v3.4s,v27.4s add x12,x12,x25,lsr#32 add w13,w13,w26 add v7.4s,v7.4s,v28.4s add x14,x14,x26,lsr#32 add w15,w15,w27 add v19.4s,v19.4s,v29.4s add x16,x16,x27,lsr#32 add w17,w17,w28 add v1.4s,v1.4s,v25.4s add x19,x19,x28,lsr#32 add w20,w20,w30 add v5.4s,v5.4s,v25.4s add x21,x21,x30,lsr#32 add v17.4s,v17.4s,v25.4s b.lo Ltail_neon add x5,x5,x6,lsl#32 // pack add x7,x7,x8,lsl#32 ldp x6,x8,[x1,#0] // load input add x9,x9,x10,lsl#32 add x11,x11,x12,lsl#32 ldp x10,x12,[x1,#16] add x13,x13,x14,lsl#32 add x15,x15,x16,lsl#32 ldp x14,x16,[x1,#32] add x17,x17,x19,lsl#32 add x20,x20,x21,lsl#32 ldp x19,x21,[x1,#48] add x1,x1,#64 #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif ld1 {v20.16b,v21.16b,v22.16b,v23.16b},[x1],#64 eor x5,x5,x6 eor x7,x7,x8 eor x9,x9,x10 eor x11,x11,x12 eor x13,x13,x14 eor v0.16b,v0.16b,v20.16b eor x15,x15,x16 eor v1.16b,v1.16b,v21.16b eor x17,x17,x19 eor v2.16b,v2.16b,v22.16b eor x20,x20,x21 eor v3.16b,v3.16b,v23.16b ld1 {v20.16b,v21.16b,v22.16b,v23.16b},[x1],#64 stp x5,x7,[x0,#0] // store output add x28,x28,#4 // increment counter stp x9,x11,[x0,#16] add v27.4s,v27.4s,v31.4s // += 4 stp x13,x15,[x0,#32] add v28.4s,v28.4s,v31.4s stp x17,x20,[x0,#48] add v29.4s,v29.4s,v31.4s add x0,x0,#64 st1 {v0.16b,v1.16b,v2.16b,v3.16b},[x0],#64 ld1 {v0.16b,v1.16b,v2.16b,v3.16b},[x1],#64 eor v4.16b,v4.16b,v20.16b eor v5.16b,v5.16b,v21.16b eor v6.16b,v6.16b,v22.16b eor v7.16b,v7.16b,v23.16b st1 {v4.16b,v5.16b,v6.16b,v7.16b},[x0],#64 eor v16.16b,v16.16b,v0.16b eor v17.16b,v17.16b,v1.16b eor v18.16b,v18.16b,v2.16b eor v19.16b,v19.16b,v3.16b st1 {v16.16b,v17.16b,v18.16b,v19.16b},[x0],#64 b.hi Loop_outer_neon ldp x19,x20,[x29,#16] add sp,sp,#64 ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret Ltail_neon: add x2,x2,#256 cmp x2,#64 b.lo Less_than_64 add x5,x5,x6,lsl#32 // pack add x7,x7,x8,lsl#32 ldp x6,x8,[x1,#0] // load input add x9,x9,x10,lsl#32 add x11,x11,x12,lsl#32 ldp x10,x12,[x1,#16] add x13,x13,x14,lsl#32 add x15,x15,x16,lsl#32 ldp x14,x16,[x1,#32] add x17,x17,x19,lsl#32 add x20,x20,x21,lsl#32 ldp x19,x21,[x1,#48] add x1,x1,#64 #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif eor x5,x5,x6 eor x7,x7,x8 eor x9,x9,x10 eor x11,x11,x12 eor x13,x13,x14 eor x15,x15,x16 eor x17,x17,x19 eor x20,x20,x21 stp x5,x7,[x0,#0] // store output add x28,x28,#4 // increment counter stp x9,x11,[x0,#16] stp x13,x15,[x0,#32] stp x17,x20,[x0,#48] add x0,x0,#64 b.eq Ldone_neon sub x2,x2,#64 cmp x2,#64 b.lo Less_than_128 ld1 {v20.16b,v21.16b,v22.16b,v23.16b},[x1],#64 eor v0.16b,v0.16b,v20.16b eor v1.16b,v1.16b,v21.16b eor v2.16b,v2.16b,v22.16b eor v3.16b,v3.16b,v23.16b st1 {v0.16b,v1.16b,v2.16b,v3.16b},[x0],#64 b.eq Ldone_neon sub x2,x2,#64 cmp x2,#64 b.lo Less_than_192 ld1 {v20.16b,v21.16b,v22.16b,v23.16b},[x1],#64 eor v4.16b,v4.16b,v20.16b eor v5.16b,v5.16b,v21.16b eor v6.16b,v6.16b,v22.16b eor v7.16b,v7.16b,v23.16b st1 {v4.16b,v5.16b,v6.16b,v7.16b},[x0],#64 b.eq Ldone_neon sub x2,x2,#64 st1 {v16.16b,v17.16b,v18.16b,v19.16b},[sp] b Last_neon Less_than_128: st1 {v0.16b,v1.16b,v2.16b,v3.16b},[sp] b Last_neon Less_than_192: st1 {v4.16b,v5.16b,v6.16b,v7.16b},[sp] b Last_neon .align 4 Last_neon: sub x0,x0,#1 add x1,x1,x2 add x0,x0,x2 add x4,sp,x2 neg x2,x2 Loop_tail_neon: ldrb w10,[x1,x2] ldrb w11,[x4,x2] add x2,x2,#1 eor w10,w10,w11 strb w10,[x0,x2] cbnz x2,Loop_tail_neon stp xzr,xzr,[sp,#0] stp xzr,xzr,[sp,#16] stp xzr,xzr,[sp,#32] stp xzr,xzr,[sp,#48] Ldone_neon: ldp x19,x20,[x29,#16] add sp,sp,#64 ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret .def ChaCha20_512_neon .type 32 .endef .align 5 ChaCha20_512_neon: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-96]! add x29,sp,#0 adrp x5,Lsigma add x5,x5,:lo12:Lsigma stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] stp x25,x26,[sp,#64] stp x27,x28,[sp,#80] L512_or_more_neon: sub sp,sp,#128+64 ldp x22,x23,[x5] // load sigma ld1 {v24.4s},[x5],#16 ldp x24,x25,[x3] // load key ldp x26,x27,[x3,#16] ld1 {v25.4s,v26.4s},[x3] ldp x28,x30,[x4] // load counter ld1 {v27.4s},[x4] ld1 {v31.4s},[x5] #ifdef __AARCH64EB__ rev64 v24.4s,v24.4s ror x24,x24,#32 ror x25,x25,#32 ror x26,x26,#32 ror x27,x27,#32 ror x28,x28,#32 ror x30,x30,#32 #endif add v27.4s,v27.4s,v31.4s // += 1 stp q24,q25,[sp,#0] // off-load key block, invariant part add v27.4s,v27.4s,v31.4s // not typo str q26,[sp,#32] add v28.4s,v27.4s,v31.4s add v29.4s,v28.4s,v31.4s add v30.4s,v29.4s,v31.4s shl v31.4s,v31.4s,#2 // 1 -> 4 stp d8,d9,[sp,#128+0] // meet ABI requirements stp d10,d11,[sp,#128+16] stp d12,d13,[sp,#128+32] stp d14,d15,[sp,#128+48] sub x2,x2,#512 // not typo Loop_outer_512_neon: mov v0.16b,v24.16b mov v4.16b,v24.16b mov v8.16b,v24.16b mov v12.16b,v24.16b mov v16.16b,v24.16b mov v20.16b,v24.16b mov v1.16b,v25.16b mov w5,w22 // unpack key block mov v5.16b,v25.16b lsr x6,x22,#32 mov v9.16b,v25.16b mov w7,w23 mov v13.16b,v25.16b lsr x8,x23,#32 mov v17.16b,v25.16b mov w9,w24 mov v21.16b,v25.16b lsr x10,x24,#32 mov v3.16b,v27.16b mov w11,w25 mov v7.16b,v28.16b lsr x12,x25,#32 mov v11.16b,v29.16b mov w13,w26 mov v15.16b,v30.16b lsr x14,x26,#32 mov v2.16b,v26.16b mov w15,w27 mov v6.16b,v26.16b lsr x16,x27,#32 add v19.4s,v3.4s,v31.4s // +4 mov w17,w28 add v23.4s,v7.4s,v31.4s // +4 lsr x19,x28,#32 mov v10.16b,v26.16b mov w20,w30 mov v14.16b,v26.16b lsr x21,x30,#32 mov v18.16b,v26.16b stp q27,q28,[sp,#48] // off-load key block, variable part mov v22.16b,v26.16b str q29,[sp,#80] mov x4,#5 subs x2,x2,#512 Loop_upper_neon: sub x4,x4,#1 add v0.4s,v0.4s,v1.4s add w5,w5,w9 add v4.4s,v4.4s,v5.4s add w6,w6,w10 add v8.4s,v8.4s,v9.4s add w7,w7,w11 add v12.4s,v12.4s,v13.4s add w8,w8,w12 add v16.4s,v16.4s,v17.4s eor w17,w17,w5 add v20.4s,v20.4s,v21.4s eor w19,w19,w6 eor v3.16b,v3.16b,v0.16b eor w20,w20,w7 eor v7.16b,v7.16b,v4.16b eor w21,w21,w8 eor v11.16b,v11.16b,v8.16b ror w17,w17,#16 eor v15.16b,v15.16b,v12.16b ror w19,w19,#16 eor v19.16b,v19.16b,v16.16b ror w20,w20,#16 eor v23.16b,v23.16b,v20.16b ror w21,w21,#16 rev32 v3.8h,v3.8h add w13,w13,w17 rev32 v7.8h,v7.8h add w14,w14,w19 rev32 v11.8h,v11.8h add w15,w15,w20 rev32 v15.8h,v15.8h add w16,w16,w21 rev32 v19.8h,v19.8h eor w9,w9,w13 rev32 v23.8h,v23.8h eor w10,w10,w14 add v2.4s,v2.4s,v3.4s eor w11,w11,w15 add v6.4s,v6.4s,v7.4s eor w12,w12,w16 add v10.4s,v10.4s,v11.4s ror w9,w9,#20 add v14.4s,v14.4s,v15.4s ror w10,w10,#20 add v18.4s,v18.4s,v19.4s ror w11,w11,#20 add v22.4s,v22.4s,v23.4s ror w12,w12,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w9 eor v25.16b,v5.16b,v6.16b add w6,w6,w10 eor v26.16b,v9.16b,v10.16b add w7,w7,w11 eor v27.16b,v13.16b,v14.16b add w8,w8,w12 eor v28.16b,v17.16b,v18.16b eor w17,w17,w5 eor v29.16b,v21.16b,v22.16b eor w19,w19,w6 ushr v1.4s,v24.4s,#20 eor w20,w20,w7 ushr v5.4s,v25.4s,#20 eor w21,w21,w8 ushr v9.4s,v26.4s,#20 ror w17,w17,#24 ushr v13.4s,v27.4s,#20 ror w19,w19,#24 ushr v17.4s,v28.4s,#20 ror w20,w20,#24 ushr v21.4s,v29.4s,#20 ror w21,w21,#24 sli v1.4s,v24.4s,#12 add w13,w13,w17 sli v5.4s,v25.4s,#12 add w14,w14,w19 sli v9.4s,v26.4s,#12 add w15,w15,w20 sli v13.4s,v27.4s,#12 add w16,w16,w21 sli v17.4s,v28.4s,#12 eor w9,w9,w13 sli v21.4s,v29.4s,#12 eor w10,w10,w14 add v0.4s,v0.4s,v1.4s eor w11,w11,w15 add v4.4s,v4.4s,v5.4s eor w12,w12,w16 add v8.4s,v8.4s,v9.4s ror w9,w9,#25 add v12.4s,v12.4s,v13.4s ror w10,w10,#25 add v16.4s,v16.4s,v17.4s ror w11,w11,#25 add v20.4s,v20.4s,v21.4s ror w12,w12,#25 eor v24.16b,v3.16b,v0.16b add w5,w5,w10 eor v25.16b,v7.16b,v4.16b add w6,w6,w11 eor v26.16b,v11.16b,v8.16b add w7,w7,w12 eor v27.16b,v15.16b,v12.16b add w8,w8,w9 eor v28.16b,v19.16b,v16.16b eor w21,w21,w5 eor v29.16b,v23.16b,v20.16b eor w17,w17,w6 ushr v3.4s,v24.4s,#24 eor w19,w19,w7 ushr v7.4s,v25.4s,#24 eor w20,w20,w8 ushr v11.4s,v26.4s,#24 ror w21,w21,#16 ushr v15.4s,v27.4s,#24 ror w17,w17,#16 ushr v19.4s,v28.4s,#24 ror w19,w19,#16 ushr v23.4s,v29.4s,#24 ror w20,w20,#16 sli v3.4s,v24.4s,#8 add w15,w15,w21 sli v7.4s,v25.4s,#8 add w16,w16,w17 sli v11.4s,v26.4s,#8 add w13,w13,w19 sli v15.4s,v27.4s,#8 add w14,w14,w20 sli v19.4s,v28.4s,#8 eor w10,w10,w15 sli v23.4s,v29.4s,#8 eor w11,w11,w16 add v2.4s,v2.4s,v3.4s eor w12,w12,w13 add v6.4s,v6.4s,v7.4s eor w9,w9,w14 add v10.4s,v10.4s,v11.4s ror w10,w10,#20 add v14.4s,v14.4s,v15.4s ror w11,w11,#20 add v18.4s,v18.4s,v19.4s ror w12,w12,#20 add v22.4s,v22.4s,v23.4s ror w9,w9,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w10 eor v25.16b,v5.16b,v6.16b add w6,w6,w11 eor v26.16b,v9.16b,v10.16b add w7,w7,w12 eor v27.16b,v13.16b,v14.16b add w8,w8,w9 eor v28.16b,v17.16b,v18.16b eor w21,w21,w5 eor v29.16b,v21.16b,v22.16b eor w17,w17,w6 ushr v1.4s,v24.4s,#25 eor w19,w19,w7 ushr v5.4s,v25.4s,#25 eor w20,w20,w8 ushr v9.4s,v26.4s,#25 ror w21,w21,#24 ushr v13.4s,v27.4s,#25 ror w17,w17,#24 ushr v17.4s,v28.4s,#25 ror w19,w19,#24 ushr v21.4s,v29.4s,#25 ror w20,w20,#24 sli v1.4s,v24.4s,#7 add w15,w15,w21 sli v5.4s,v25.4s,#7 add w16,w16,w17 sli v9.4s,v26.4s,#7 add w13,w13,w19 sli v13.4s,v27.4s,#7 add w14,w14,w20 sli v17.4s,v28.4s,#7 eor w10,w10,w15 sli v21.4s,v29.4s,#7 eor w11,w11,w16 ext v2.16b,v2.16b,v2.16b,#8 eor w12,w12,w13 ext v6.16b,v6.16b,v6.16b,#8 eor w9,w9,w14 ext v10.16b,v10.16b,v10.16b,#8 ror w10,w10,#25 ext v14.16b,v14.16b,v14.16b,#8 ror w11,w11,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w12,w12,#25 ext v22.16b,v22.16b,v22.16b,#8 ror w9,w9,#25 ext v3.16b,v3.16b,v3.16b,#12 ext v7.16b,v7.16b,v7.16b,#12 ext v11.16b,v11.16b,v11.16b,#12 ext v15.16b,v15.16b,v15.16b,#12 ext v19.16b,v19.16b,v19.16b,#12 ext v23.16b,v23.16b,v23.16b,#12 ext v1.16b,v1.16b,v1.16b,#4 ext v5.16b,v5.16b,v5.16b,#4 ext v9.16b,v9.16b,v9.16b,#4 ext v13.16b,v13.16b,v13.16b,#4 ext v17.16b,v17.16b,v17.16b,#4 ext v21.16b,v21.16b,v21.16b,#4 add v0.4s,v0.4s,v1.4s add w5,w5,w9 add v4.4s,v4.4s,v5.4s add w6,w6,w10 add v8.4s,v8.4s,v9.4s add w7,w7,w11 add v12.4s,v12.4s,v13.4s add w8,w8,w12 add v16.4s,v16.4s,v17.4s eor w17,w17,w5 add v20.4s,v20.4s,v21.4s eor w19,w19,w6 eor v3.16b,v3.16b,v0.16b eor w20,w20,w7 eor v7.16b,v7.16b,v4.16b eor w21,w21,w8 eor v11.16b,v11.16b,v8.16b ror w17,w17,#16 eor v15.16b,v15.16b,v12.16b ror w19,w19,#16 eor v19.16b,v19.16b,v16.16b ror w20,w20,#16 eor v23.16b,v23.16b,v20.16b ror w21,w21,#16 rev32 v3.8h,v3.8h add w13,w13,w17 rev32 v7.8h,v7.8h add w14,w14,w19 rev32 v11.8h,v11.8h add w15,w15,w20 rev32 v15.8h,v15.8h add w16,w16,w21 rev32 v19.8h,v19.8h eor w9,w9,w13 rev32 v23.8h,v23.8h eor w10,w10,w14 add v2.4s,v2.4s,v3.4s eor w11,w11,w15 add v6.4s,v6.4s,v7.4s eor w12,w12,w16 add v10.4s,v10.4s,v11.4s ror w9,w9,#20 add v14.4s,v14.4s,v15.4s ror w10,w10,#20 add v18.4s,v18.4s,v19.4s ror w11,w11,#20 add v22.4s,v22.4s,v23.4s ror w12,w12,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w9 eor v25.16b,v5.16b,v6.16b add w6,w6,w10 eor v26.16b,v9.16b,v10.16b add w7,w7,w11 eor v27.16b,v13.16b,v14.16b add w8,w8,w12 eor v28.16b,v17.16b,v18.16b eor w17,w17,w5 eor v29.16b,v21.16b,v22.16b eor w19,w19,w6 ushr v1.4s,v24.4s,#20 eor w20,w20,w7 ushr v5.4s,v25.4s,#20 eor w21,w21,w8 ushr v9.4s,v26.4s,#20 ror w17,w17,#24 ushr v13.4s,v27.4s,#20 ror w19,w19,#24 ushr v17.4s,v28.4s,#20 ror w20,w20,#24 ushr v21.4s,v29.4s,#20 ror w21,w21,#24 sli v1.4s,v24.4s,#12 add w13,w13,w17 sli v5.4s,v25.4s,#12 add w14,w14,w19 sli v9.4s,v26.4s,#12 add w15,w15,w20 sli v13.4s,v27.4s,#12 add w16,w16,w21 sli v17.4s,v28.4s,#12 eor w9,w9,w13 sli v21.4s,v29.4s,#12 eor w10,w10,w14 add v0.4s,v0.4s,v1.4s eor w11,w11,w15 add v4.4s,v4.4s,v5.4s eor w12,w12,w16 add v8.4s,v8.4s,v9.4s ror w9,w9,#25 add v12.4s,v12.4s,v13.4s ror w10,w10,#25 add v16.4s,v16.4s,v17.4s ror w11,w11,#25 add v20.4s,v20.4s,v21.4s ror w12,w12,#25 eor v24.16b,v3.16b,v0.16b add w5,w5,w10 eor v25.16b,v7.16b,v4.16b add w6,w6,w11 eor v26.16b,v11.16b,v8.16b add w7,w7,w12 eor v27.16b,v15.16b,v12.16b add w8,w8,w9 eor v28.16b,v19.16b,v16.16b eor w21,w21,w5 eor v29.16b,v23.16b,v20.16b eor w17,w17,w6 ushr v3.4s,v24.4s,#24 eor w19,w19,w7 ushr v7.4s,v25.4s,#24 eor w20,w20,w8 ushr v11.4s,v26.4s,#24 ror w21,w21,#16 ushr v15.4s,v27.4s,#24 ror w17,w17,#16 ushr v19.4s,v28.4s,#24 ror w19,w19,#16 ushr v23.4s,v29.4s,#24 ror w20,w20,#16 sli v3.4s,v24.4s,#8 add w15,w15,w21 sli v7.4s,v25.4s,#8 add w16,w16,w17 sli v11.4s,v26.4s,#8 add w13,w13,w19 sli v15.4s,v27.4s,#8 add w14,w14,w20 sli v19.4s,v28.4s,#8 eor w10,w10,w15 sli v23.4s,v29.4s,#8 eor w11,w11,w16 add v2.4s,v2.4s,v3.4s eor w12,w12,w13 add v6.4s,v6.4s,v7.4s eor w9,w9,w14 add v10.4s,v10.4s,v11.4s ror w10,w10,#20 add v14.4s,v14.4s,v15.4s ror w11,w11,#20 add v18.4s,v18.4s,v19.4s ror w12,w12,#20 add v22.4s,v22.4s,v23.4s ror w9,w9,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w10 eor v25.16b,v5.16b,v6.16b add w6,w6,w11 eor v26.16b,v9.16b,v10.16b add w7,w7,w12 eor v27.16b,v13.16b,v14.16b add w8,w8,w9 eor v28.16b,v17.16b,v18.16b eor w21,w21,w5 eor v29.16b,v21.16b,v22.16b eor w17,w17,w6 ushr v1.4s,v24.4s,#25 eor w19,w19,w7 ushr v5.4s,v25.4s,#25 eor w20,w20,w8 ushr v9.4s,v26.4s,#25 ror w21,w21,#24 ushr v13.4s,v27.4s,#25 ror w17,w17,#24 ushr v17.4s,v28.4s,#25 ror w19,w19,#24 ushr v21.4s,v29.4s,#25 ror w20,w20,#24 sli v1.4s,v24.4s,#7 add w15,w15,w21 sli v5.4s,v25.4s,#7 add w16,w16,w17 sli v9.4s,v26.4s,#7 add w13,w13,w19 sli v13.4s,v27.4s,#7 add w14,w14,w20 sli v17.4s,v28.4s,#7 eor w10,w10,w15 sli v21.4s,v29.4s,#7 eor w11,w11,w16 ext v2.16b,v2.16b,v2.16b,#8 eor w12,w12,w13 ext v6.16b,v6.16b,v6.16b,#8 eor w9,w9,w14 ext v10.16b,v10.16b,v10.16b,#8 ror w10,w10,#25 ext v14.16b,v14.16b,v14.16b,#8 ror w11,w11,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w12,w12,#25 ext v22.16b,v22.16b,v22.16b,#8 ror w9,w9,#25 ext v3.16b,v3.16b,v3.16b,#4 ext v7.16b,v7.16b,v7.16b,#4 ext v11.16b,v11.16b,v11.16b,#4 ext v15.16b,v15.16b,v15.16b,#4 ext v19.16b,v19.16b,v19.16b,#4 ext v23.16b,v23.16b,v23.16b,#4 ext v1.16b,v1.16b,v1.16b,#12 ext v5.16b,v5.16b,v5.16b,#12 ext v9.16b,v9.16b,v9.16b,#12 ext v13.16b,v13.16b,v13.16b,#12 ext v17.16b,v17.16b,v17.16b,#12 ext v21.16b,v21.16b,v21.16b,#12 cbnz x4,Loop_upper_neon add w5,w5,w22 // accumulate key block add x6,x6,x22,lsr#32 add w7,w7,w23 add x8,x8,x23,lsr#32 add w9,w9,w24 add x10,x10,x24,lsr#32 add w11,w11,w25 add x12,x12,x25,lsr#32 add w13,w13,w26 add x14,x14,x26,lsr#32 add w15,w15,w27 add x16,x16,x27,lsr#32 add w17,w17,w28 add x19,x19,x28,lsr#32 add w20,w20,w30 add x21,x21,x30,lsr#32 add x5,x5,x6,lsl#32 // pack add x7,x7,x8,lsl#32 ldp x6,x8,[x1,#0] // load input add x9,x9,x10,lsl#32 add x11,x11,x12,lsl#32 ldp x10,x12,[x1,#16] add x13,x13,x14,lsl#32 add x15,x15,x16,lsl#32 ldp x14,x16,[x1,#32] add x17,x17,x19,lsl#32 add x20,x20,x21,lsl#32 ldp x19,x21,[x1,#48] add x1,x1,#64 #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif eor x5,x5,x6 eor x7,x7,x8 eor x9,x9,x10 eor x11,x11,x12 eor x13,x13,x14 eor x15,x15,x16 eor x17,x17,x19 eor x20,x20,x21 stp x5,x7,[x0,#0] // store output add x28,x28,#1 // increment counter mov w5,w22 // unpack key block lsr x6,x22,#32 stp x9,x11,[x0,#16] mov w7,w23 lsr x8,x23,#32 stp x13,x15,[x0,#32] mov w9,w24 lsr x10,x24,#32 stp x17,x20,[x0,#48] add x0,x0,#64 mov w11,w25 lsr x12,x25,#32 mov w13,w26 lsr x14,x26,#32 mov w15,w27 lsr x16,x27,#32 mov w17,w28 lsr x19,x28,#32 mov w20,w30 lsr x21,x30,#32 mov x4,#5 Loop_lower_neon: sub x4,x4,#1 add v0.4s,v0.4s,v1.4s add w5,w5,w9 add v4.4s,v4.4s,v5.4s add w6,w6,w10 add v8.4s,v8.4s,v9.4s add w7,w7,w11 add v12.4s,v12.4s,v13.4s add w8,w8,w12 add v16.4s,v16.4s,v17.4s eor w17,w17,w5 add v20.4s,v20.4s,v21.4s eor w19,w19,w6 eor v3.16b,v3.16b,v0.16b eor w20,w20,w7 eor v7.16b,v7.16b,v4.16b eor w21,w21,w8 eor v11.16b,v11.16b,v8.16b ror w17,w17,#16 eor v15.16b,v15.16b,v12.16b ror w19,w19,#16 eor v19.16b,v19.16b,v16.16b ror w20,w20,#16 eor v23.16b,v23.16b,v20.16b ror w21,w21,#16 rev32 v3.8h,v3.8h add w13,w13,w17 rev32 v7.8h,v7.8h add w14,w14,w19 rev32 v11.8h,v11.8h add w15,w15,w20 rev32 v15.8h,v15.8h add w16,w16,w21 rev32 v19.8h,v19.8h eor w9,w9,w13 rev32 v23.8h,v23.8h eor w10,w10,w14 add v2.4s,v2.4s,v3.4s eor w11,w11,w15 add v6.4s,v6.4s,v7.4s eor w12,w12,w16 add v10.4s,v10.4s,v11.4s ror w9,w9,#20 add v14.4s,v14.4s,v15.4s ror w10,w10,#20 add v18.4s,v18.4s,v19.4s ror w11,w11,#20 add v22.4s,v22.4s,v23.4s ror w12,w12,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w9 eor v25.16b,v5.16b,v6.16b add w6,w6,w10 eor v26.16b,v9.16b,v10.16b add w7,w7,w11 eor v27.16b,v13.16b,v14.16b add w8,w8,w12 eor v28.16b,v17.16b,v18.16b eor w17,w17,w5 eor v29.16b,v21.16b,v22.16b eor w19,w19,w6 ushr v1.4s,v24.4s,#20 eor w20,w20,w7 ushr v5.4s,v25.4s,#20 eor w21,w21,w8 ushr v9.4s,v26.4s,#20 ror w17,w17,#24 ushr v13.4s,v27.4s,#20 ror w19,w19,#24 ushr v17.4s,v28.4s,#20 ror w20,w20,#24 ushr v21.4s,v29.4s,#20 ror w21,w21,#24 sli v1.4s,v24.4s,#12 add w13,w13,w17 sli v5.4s,v25.4s,#12 add w14,w14,w19 sli v9.4s,v26.4s,#12 add w15,w15,w20 sli v13.4s,v27.4s,#12 add w16,w16,w21 sli v17.4s,v28.4s,#12 eor w9,w9,w13 sli v21.4s,v29.4s,#12 eor w10,w10,w14 add v0.4s,v0.4s,v1.4s eor w11,w11,w15 add v4.4s,v4.4s,v5.4s eor w12,w12,w16 add v8.4s,v8.4s,v9.4s ror w9,w9,#25 add v12.4s,v12.4s,v13.4s ror w10,w10,#25 add v16.4s,v16.4s,v17.4s ror w11,w11,#25 add v20.4s,v20.4s,v21.4s ror w12,w12,#25 eor v24.16b,v3.16b,v0.16b add w5,w5,w10 eor v25.16b,v7.16b,v4.16b add w6,w6,w11 eor v26.16b,v11.16b,v8.16b add w7,w7,w12 eor v27.16b,v15.16b,v12.16b add w8,w8,w9 eor v28.16b,v19.16b,v16.16b eor w21,w21,w5 eor v29.16b,v23.16b,v20.16b eor w17,w17,w6 ushr v3.4s,v24.4s,#24 eor w19,w19,w7 ushr v7.4s,v25.4s,#24 eor w20,w20,w8 ushr v11.4s,v26.4s,#24 ror w21,w21,#16 ushr v15.4s,v27.4s,#24 ror w17,w17,#16 ushr v19.4s,v28.4s,#24 ror w19,w19,#16 ushr v23.4s,v29.4s,#24 ror w20,w20,#16 sli v3.4s,v24.4s,#8 add w15,w15,w21 sli v7.4s,v25.4s,#8 add w16,w16,w17 sli v11.4s,v26.4s,#8 add w13,w13,w19 sli v15.4s,v27.4s,#8 add w14,w14,w20 sli v19.4s,v28.4s,#8 eor w10,w10,w15 sli v23.4s,v29.4s,#8 eor w11,w11,w16 add v2.4s,v2.4s,v3.4s eor w12,w12,w13 add v6.4s,v6.4s,v7.4s eor w9,w9,w14 add v10.4s,v10.4s,v11.4s ror w10,w10,#20 add v14.4s,v14.4s,v15.4s ror w11,w11,#20 add v18.4s,v18.4s,v19.4s ror w12,w12,#20 add v22.4s,v22.4s,v23.4s ror w9,w9,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w10 eor v25.16b,v5.16b,v6.16b add w6,w6,w11 eor v26.16b,v9.16b,v10.16b add w7,w7,w12 eor v27.16b,v13.16b,v14.16b add w8,w8,w9 eor v28.16b,v17.16b,v18.16b eor w21,w21,w5 eor v29.16b,v21.16b,v22.16b eor w17,w17,w6 ushr v1.4s,v24.4s,#25 eor w19,w19,w7 ushr v5.4s,v25.4s,#25 eor w20,w20,w8 ushr v9.4s,v26.4s,#25 ror w21,w21,#24 ushr v13.4s,v27.4s,#25 ror w17,w17,#24 ushr v17.4s,v28.4s,#25 ror w19,w19,#24 ushr v21.4s,v29.4s,#25 ror w20,w20,#24 sli v1.4s,v24.4s,#7 add w15,w15,w21 sli v5.4s,v25.4s,#7 add w16,w16,w17 sli v9.4s,v26.4s,#7 add w13,w13,w19 sli v13.4s,v27.4s,#7 add w14,w14,w20 sli v17.4s,v28.4s,#7 eor w10,w10,w15 sli v21.4s,v29.4s,#7 eor w11,w11,w16 ext v2.16b,v2.16b,v2.16b,#8 eor w12,w12,w13 ext v6.16b,v6.16b,v6.16b,#8 eor w9,w9,w14 ext v10.16b,v10.16b,v10.16b,#8 ror w10,w10,#25 ext v14.16b,v14.16b,v14.16b,#8 ror w11,w11,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w12,w12,#25 ext v22.16b,v22.16b,v22.16b,#8 ror w9,w9,#25 ext v3.16b,v3.16b,v3.16b,#12 ext v7.16b,v7.16b,v7.16b,#12 ext v11.16b,v11.16b,v11.16b,#12 ext v15.16b,v15.16b,v15.16b,#12 ext v19.16b,v19.16b,v19.16b,#12 ext v23.16b,v23.16b,v23.16b,#12 ext v1.16b,v1.16b,v1.16b,#4 ext v5.16b,v5.16b,v5.16b,#4 ext v9.16b,v9.16b,v9.16b,#4 ext v13.16b,v13.16b,v13.16b,#4 ext v17.16b,v17.16b,v17.16b,#4 ext v21.16b,v21.16b,v21.16b,#4 add v0.4s,v0.4s,v1.4s add w5,w5,w9 add v4.4s,v4.4s,v5.4s add w6,w6,w10 add v8.4s,v8.4s,v9.4s add w7,w7,w11 add v12.4s,v12.4s,v13.4s add w8,w8,w12 add v16.4s,v16.4s,v17.4s eor w17,w17,w5 add v20.4s,v20.4s,v21.4s eor w19,w19,w6 eor v3.16b,v3.16b,v0.16b eor w20,w20,w7 eor v7.16b,v7.16b,v4.16b eor w21,w21,w8 eor v11.16b,v11.16b,v8.16b ror w17,w17,#16 eor v15.16b,v15.16b,v12.16b ror w19,w19,#16 eor v19.16b,v19.16b,v16.16b ror w20,w20,#16 eor v23.16b,v23.16b,v20.16b ror w21,w21,#16 rev32 v3.8h,v3.8h add w13,w13,w17 rev32 v7.8h,v7.8h add w14,w14,w19 rev32 v11.8h,v11.8h add w15,w15,w20 rev32 v15.8h,v15.8h add w16,w16,w21 rev32 v19.8h,v19.8h eor w9,w9,w13 rev32 v23.8h,v23.8h eor w10,w10,w14 add v2.4s,v2.4s,v3.4s eor w11,w11,w15 add v6.4s,v6.4s,v7.4s eor w12,w12,w16 add v10.4s,v10.4s,v11.4s ror w9,w9,#20 add v14.4s,v14.4s,v15.4s ror w10,w10,#20 add v18.4s,v18.4s,v19.4s ror w11,w11,#20 add v22.4s,v22.4s,v23.4s ror w12,w12,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w9 eor v25.16b,v5.16b,v6.16b add w6,w6,w10 eor v26.16b,v9.16b,v10.16b add w7,w7,w11 eor v27.16b,v13.16b,v14.16b add w8,w8,w12 eor v28.16b,v17.16b,v18.16b eor w17,w17,w5 eor v29.16b,v21.16b,v22.16b eor w19,w19,w6 ushr v1.4s,v24.4s,#20 eor w20,w20,w7 ushr v5.4s,v25.4s,#20 eor w21,w21,w8 ushr v9.4s,v26.4s,#20 ror w17,w17,#24 ushr v13.4s,v27.4s,#20 ror w19,w19,#24 ushr v17.4s,v28.4s,#20 ror w20,w20,#24 ushr v21.4s,v29.4s,#20 ror w21,w21,#24 sli v1.4s,v24.4s,#12 add w13,w13,w17 sli v5.4s,v25.4s,#12 add w14,w14,w19 sli v9.4s,v26.4s,#12 add w15,w15,w20 sli v13.4s,v27.4s,#12 add w16,w16,w21 sli v17.4s,v28.4s,#12 eor w9,w9,w13 sli v21.4s,v29.4s,#12 eor w10,w10,w14 add v0.4s,v0.4s,v1.4s eor w11,w11,w15 add v4.4s,v4.4s,v5.4s eor w12,w12,w16 add v8.4s,v8.4s,v9.4s ror w9,w9,#25 add v12.4s,v12.4s,v13.4s ror w10,w10,#25 add v16.4s,v16.4s,v17.4s ror w11,w11,#25 add v20.4s,v20.4s,v21.4s ror w12,w12,#25 eor v24.16b,v3.16b,v0.16b add w5,w5,w10 eor v25.16b,v7.16b,v4.16b add w6,w6,w11 eor v26.16b,v11.16b,v8.16b add w7,w7,w12 eor v27.16b,v15.16b,v12.16b add w8,w8,w9 eor v28.16b,v19.16b,v16.16b eor w21,w21,w5 eor v29.16b,v23.16b,v20.16b eor w17,w17,w6 ushr v3.4s,v24.4s,#24 eor w19,w19,w7 ushr v7.4s,v25.4s,#24 eor w20,w20,w8 ushr v11.4s,v26.4s,#24 ror w21,w21,#16 ushr v15.4s,v27.4s,#24 ror w17,w17,#16 ushr v19.4s,v28.4s,#24 ror w19,w19,#16 ushr v23.4s,v29.4s,#24 ror w20,w20,#16 sli v3.4s,v24.4s,#8 add w15,w15,w21 sli v7.4s,v25.4s,#8 add w16,w16,w17 sli v11.4s,v26.4s,#8 add w13,w13,w19 sli v15.4s,v27.4s,#8 add w14,w14,w20 sli v19.4s,v28.4s,#8 eor w10,w10,w15 sli v23.4s,v29.4s,#8 eor w11,w11,w16 add v2.4s,v2.4s,v3.4s eor w12,w12,w13 add v6.4s,v6.4s,v7.4s eor w9,w9,w14 add v10.4s,v10.4s,v11.4s ror w10,w10,#20 add v14.4s,v14.4s,v15.4s ror w11,w11,#20 add v18.4s,v18.4s,v19.4s ror w12,w12,#20 add v22.4s,v22.4s,v23.4s ror w9,w9,#20 eor v24.16b,v1.16b,v2.16b add w5,w5,w10 eor v25.16b,v5.16b,v6.16b add w6,w6,w11 eor v26.16b,v9.16b,v10.16b add w7,w7,w12 eor v27.16b,v13.16b,v14.16b add w8,w8,w9 eor v28.16b,v17.16b,v18.16b eor w21,w21,w5 eor v29.16b,v21.16b,v22.16b eor w17,w17,w6 ushr v1.4s,v24.4s,#25 eor w19,w19,w7 ushr v5.4s,v25.4s,#25 eor w20,w20,w8 ushr v9.4s,v26.4s,#25 ror w21,w21,#24 ushr v13.4s,v27.4s,#25 ror w17,w17,#24 ushr v17.4s,v28.4s,#25 ror w19,w19,#24 ushr v21.4s,v29.4s,#25 ror w20,w20,#24 sli v1.4s,v24.4s,#7 add w15,w15,w21 sli v5.4s,v25.4s,#7 add w16,w16,w17 sli v9.4s,v26.4s,#7 add w13,w13,w19 sli v13.4s,v27.4s,#7 add w14,w14,w20 sli v17.4s,v28.4s,#7 eor w10,w10,w15 sli v21.4s,v29.4s,#7 eor w11,w11,w16 ext v2.16b,v2.16b,v2.16b,#8 eor w12,w12,w13 ext v6.16b,v6.16b,v6.16b,#8 eor w9,w9,w14 ext v10.16b,v10.16b,v10.16b,#8 ror w10,w10,#25 ext v14.16b,v14.16b,v14.16b,#8 ror w11,w11,#25 ext v18.16b,v18.16b,v18.16b,#8 ror w12,w12,#25 ext v22.16b,v22.16b,v22.16b,#8 ror w9,w9,#25 ext v3.16b,v3.16b,v3.16b,#4 ext v7.16b,v7.16b,v7.16b,#4 ext v11.16b,v11.16b,v11.16b,#4 ext v15.16b,v15.16b,v15.16b,#4 ext v19.16b,v19.16b,v19.16b,#4 ext v23.16b,v23.16b,v23.16b,#4 ext v1.16b,v1.16b,v1.16b,#12 ext v5.16b,v5.16b,v5.16b,#12 ext v9.16b,v9.16b,v9.16b,#12 ext v13.16b,v13.16b,v13.16b,#12 ext v17.16b,v17.16b,v17.16b,#12 ext v21.16b,v21.16b,v21.16b,#12 cbnz x4,Loop_lower_neon add w5,w5,w22 // accumulate key block ldp q24,q25,[sp,#0] add x6,x6,x22,lsr#32 ldp q26,q27,[sp,#32] add w7,w7,w23 ldp q28,q29,[sp,#64] add x8,x8,x23,lsr#32 add v0.4s,v0.4s,v24.4s add w9,w9,w24 add v4.4s,v4.4s,v24.4s add x10,x10,x24,lsr#32 add v8.4s,v8.4s,v24.4s add w11,w11,w25 add v12.4s,v12.4s,v24.4s add x12,x12,x25,lsr#32 add v16.4s,v16.4s,v24.4s add w13,w13,w26 add v20.4s,v20.4s,v24.4s add x14,x14,x26,lsr#32 add v2.4s,v2.4s,v26.4s add w15,w15,w27 add v6.4s,v6.4s,v26.4s add x16,x16,x27,lsr#32 add v10.4s,v10.4s,v26.4s add w17,w17,w28 add v14.4s,v14.4s,v26.4s add x19,x19,x28,lsr#32 add v18.4s,v18.4s,v26.4s add w20,w20,w30 add v22.4s,v22.4s,v26.4s add x21,x21,x30,lsr#32 add v19.4s,v19.4s,v31.4s // +4 add x5,x5,x6,lsl#32 // pack add v23.4s,v23.4s,v31.4s // +4 add x7,x7,x8,lsl#32 add v3.4s,v3.4s,v27.4s ldp x6,x8,[x1,#0] // load input add v7.4s,v7.4s,v28.4s add x9,x9,x10,lsl#32 add v11.4s,v11.4s,v29.4s add x11,x11,x12,lsl#32 add v15.4s,v15.4s,v30.4s ldp x10,x12,[x1,#16] add v19.4s,v19.4s,v27.4s add x13,x13,x14,lsl#32 add v23.4s,v23.4s,v28.4s add x15,x15,x16,lsl#32 add v1.4s,v1.4s,v25.4s ldp x14,x16,[x1,#32] add v5.4s,v5.4s,v25.4s add x17,x17,x19,lsl#32 add v9.4s,v9.4s,v25.4s add x20,x20,x21,lsl#32 add v13.4s,v13.4s,v25.4s ldp x19,x21,[x1,#48] add v17.4s,v17.4s,v25.4s add x1,x1,#64 add v21.4s,v21.4s,v25.4s #ifdef __AARCH64EB__ rev x5,x5 rev x7,x7 rev x9,x9 rev x11,x11 rev x13,x13 rev x15,x15 rev x17,x17 rev x20,x20 #endif ld1 {v24.16b,v25.16b,v26.16b,v27.16b},[x1],#64 eor x5,x5,x6 eor x7,x7,x8 eor x9,x9,x10 eor x11,x11,x12 eor x13,x13,x14 eor v0.16b,v0.16b,v24.16b eor x15,x15,x16 eor v1.16b,v1.16b,v25.16b eor x17,x17,x19 eor v2.16b,v2.16b,v26.16b eor x20,x20,x21 eor v3.16b,v3.16b,v27.16b ld1 {v24.16b,v25.16b,v26.16b,v27.16b},[x1],#64 stp x5,x7,[x0,#0] // store output add x28,x28,#7 // increment counter stp x9,x11,[x0,#16] stp x13,x15,[x0,#32] stp x17,x20,[x0,#48] add x0,x0,#64 st1 {v0.16b,v1.16b,v2.16b,v3.16b},[x0],#64 ld1 {v0.16b,v1.16b,v2.16b,v3.16b},[x1],#64 eor v4.16b,v4.16b,v24.16b eor v5.16b,v5.16b,v25.16b eor v6.16b,v6.16b,v26.16b eor v7.16b,v7.16b,v27.16b st1 {v4.16b,v5.16b,v6.16b,v7.16b},[x0],#64 ld1 {v4.16b,v5.16b,v6.16b,v7.16b},[x1],#64 eor v8.16b,v8.16b,v0.16b ldp q24,q25,[sp,#0] eor v9.16b,v9.16b,v1.16b ldp q26,q27,[sp,#32] eor v10.16b,v10.16b,v2.16b eor v11.16b,v11.16b,v3.16b st1 {v8.16b,v9.16b,v10.16b,v11.16b},[x0],#64 ld1 {v8.16b,v9.16b,v10.16b,v11.16b},[x1],#64 eor v12.16b,v12.16b,v4.16b eor v13.16b,v13.16b,v5.16b eor v14.16b,v14.16b,v6.16b eor v15.16b,v15.16b,v7.16b st1 {v12.16b,v13.16b,v14.16b,v15.16b},[x0],#64 ld1 {v12.16b,v13.16b,v14.16b,v15.16b},[x1],#64 eor v16.16b,v16.16b,v8.16b eor v17.16b,v17.16b,v9.16b eor v18.16b,v18.16b,v10.16b eor v19.16b,v19.16b,v11.16b st1 {v16.16b,v17.16b,v18.16b,v19.16b},[x0],#64 shl v0.4s,v31.4s,#1 // 4 -> 8 eor v20.16b,v20.16b,v12.16b eor v21.16b,v21.16b,v13.16b eor v22.16b,v22.16b,v14.16b eor v23.16b,v23.16b,v15.16b st1 {v20.16b,v21.16b,v22.16b,v23.16b},[x0],#64 add v27.4s,v27.4s,v0.4s // += 8 add v28.4s,v28.4s,v0.4s add v29.4s,v29.4s,v0.4s add v30.4s,v30.4s,v0.4s b.hs Loop_outer_512_neon adds x2,x2,#512 ushr v0.4s,v31.4s,#2 // 4 -> 1 ldp d8,d9,[sp,#128+0] // meet ABI requirements ldp d10,d11,[sp,#128+16] ldp d12,d13,[sp,#128+32] ldp d14,d15,[sp,#128+48] stp q24,q31,[sp,#0] // wipe off-load area stp q24,q31,[sp,#32] stp q24,q31,[sp,#64] b.eq Ldone_512_neon cmp x2,#192 sub v27.4s,v27.4s,v0.4s // -= 1 sub v28.4s,v28.4s,v0.4s sub v29.4s,v29.4s,v0.4s add sp,sp,#128 b.hs Loop_outer_neon eor v25.16b,v25.16b,v25.16b eor v26.16b,v26.16b,v26.16b eor v27.16b,v27.16b,v27.16b eor v28.16b,v28.16b,v28.16b eor v29.16b,v29.16b,v29.16b eor v30.16b,v30.16b,v30.16b b Loop_outer Ldone_512_neon: ldp x19,x20,[x29,#16] add sp,sp,#128+64 ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret #endif // !OPENSSL_NO_ASM && defined(OPENSSL_AARCH64) && defined(_WIN32)

j4yc3-mw/Viren

77,139

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/p256-x86_64-asm-elf.S

// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__ELF__) .text .extern OPENSSL_ia32cap_P .hidden OPENSSL_ia32cap_P .section .rodata .align 64 .Lpoly: .quad 0xffffffffffffffff, 0x00000000ffffffff, 0x0000000000000000, 0xffffffff00000001 .LOne: .long 1,1,1,1,1,1,1,1 .LTwo: .long 2,2,2,2,2,2,2,2 .LThree: .long 3,3,3,3,3,3,3,3 .LONE_mont: .quad 0x0000000000000001, 0xffffffff00000000, 0xffffffffffffffff, 0x00000000fffffffe .Lord: .quad 0xf3b9cac2fc632551, 0xbce6faada7179e84, 0xffffffffffffffff, 0xffffffff00000000 .LordK: .quad 0xccd1c8aaee00bc4f .text .globl ecp_nistz256_neg .hidden ecp_nistz256_neg .type ecp_nistz256_neg,@function .align 32 ecp_nistz256_neg: .cfi_startproc _CET_ENDBR pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-16 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-24 .Lneg_body: xorq %r8,%r8 xorq %r9,%r9 xorq %r10,%r10 xorq %r11,%r11 xorq %r13,%r13 subq 0(%rsi),%r8 sbbq 8(%rsi),%r9 sbbq 16(%rsi),%r10 movq %r8,%rax sbbq 24(%rsi),%r11 leaq .Lpoly(%rip),%rsi movq %r9,%rdx sbbq $0,%r13 addq 0(%rsi),%r8 movq %r10,%rcx adcq 8(%rsi),%r9 adcq 16(%rsi),%r10 movq %r11,%r12 adcq 24(%rsi),%r11 testq %r13,%r13 cmovzq %rax,%r8 cmovzq %rdx,%r9 movq %r8,0(%rdi) cmovzq %rcx,%r10 movq %r9,8(%rdi) cmovzq %r12,%r11 movq %r10,16(%rdi) movq %r11,24(%rdi) movq 0(%rsp),%r13 .cfi_restore %r13 movq 8(%rsp),%r12 .cfi_restore %r12 leaq 16(%rsp),%rsp .cfi_adjust_cfa_offset -16 .Lneg_epilogue: ret .cfi_endproc .size ecp_nistz256_neg,.-ecp_nistz256_neg .globl ecp_nistz256_ord_mul_mont .hidden ecp_nistz256_ord_mul_mont .type ecp_nistz256_ord_mul_mont,@function .align 32 ecp_nistz256_ord_mul_mont: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx cmpl $0x80100,%ecx je .Lecp_nistz256_ord_mul_montx pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lord_mul_body: movq 0(%rdx),%rax movq %rdx,%rbx leaq .Lord(%rip),%r14 movq .LordK(%rip),%r15 movq %rax,%rcx mulq 0(%rsi) movq %rax,%r8 movq %rcx,%rax movq %rdx,%r9 mulq 8(%rsi) addq %rax,%r9 movq %rcx,%rax adcq $0,%rdx movq %rdx,%r10 mulq 16(%rsi) addq %rax,%r10 movq %rcx,%rax adcq $0,%rdx movq %r8,%r13 imulq %r15,%r8 movq %rdx,%r11 mulq 24(%rsi) addq %rax,%r11 movq %r8,%rax adcq $0,%rdx movq %rdx,%r12 mulq 0(%r14) movq %r8,%rbp addq %rax,%r13 movq %r8,%rax adcq $0,%rdx movq %rdx,%rcx subq %r8,%r10 sbbq $0,%r8 mulq 8(%r14) addq %rcx,%r9 adcq $0,%rdx addq %rax,%r9 movq %rbp,%rax adcq %rdx,%r10 movq %rbp,%rdx adcq $0,%r8 shlq $32,%rax shrq $32,%rdx subq %rax,%r11 movq 8(%rbx),%rax sbbq %rdx,%rbp addq %r8,%r11 adcq %rbp,%r12 adcq $0,%r13 movq %rax,%rcx mulq 0(%rsi) addq %rax,%r9 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 8(%rsi) addq %rbp,%r10 adcq $0,%rdx addq %rax,%r10 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 16(%rsi) addq %rbp,%r11 adcq $0,%rdx addq %rax,%r11 movq %rcx,%rax adcq $0,%rdx movq %r9,%rcx imulq %r15,%r9 movq %rdx,%rbp mulq 24(%rsi) addq %rbp,%r12 adcq $0,%rdx xorq %r8,%r8 addq %rax,%r12 movq %r9,%rax adcq %rdx,%r13 adcq $0,%r8 mulq 0(%r14) movq %r9,%rbp addq %rax,%rcx movq %r9,%rax adcq %rdx,%rcx subq %r9,%r11 sbbq $0,%r9 mulq 8(%r14) addq %rcx,%r10 adcq $0,%rdx addq %rax,%r10 movq %rbp,%rax adcq %rdx,%r11 movq %rbp,%rdx adcq $0,%r9 shlq $32,%rax shrq $32,%rdx subq %rax,%r12 movq 16(%rbx),%rax sbbq %rdx,%rbp addq %r9,%r12 adcq %rbp,%r13 adcq $0,%r8 movq %rax,%rcx mulq 0(%rsi) addq %rax,%r10 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 8(%rsi) addq %rbp,%r11 adcq $0,%rdx addq %rax,%r11 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 16(%rsi) addq %rbp,%r12 adcq $0,%rdx addq %rax,%r12 movq %rcx,%rax adcq $0,%rdx movq %r10,%rcx imulq %r15,%r10 movq %rdx,%rbp mulq 24(%rsi) addq %rbp,%r13 adcq $0,%rdx xorq %r9,%r9 addq %rax,%r13 movq %r10,%rax adcq %rdx,%r8 adcq $0,%r9 mulq 0(%r14) movq %r10,%rbp addq %rax,%rcx movq %r10,%rax adcq %rdx,%rcx subq %r10,%r12 sbbq $0,%r10 mulq 8(%r14) addq %rcx,%r11 adcq $0,%rdx addq %rax,%r11 movq %rbp,%rax adcq %rdx,%r12 movq %rbp,%rdx adcq $0,%r10 shlq $32,%rax shrq $32,%rdx subq %rax,%r13 movq 24(%rbx),%rax sbbq %rdx,%rbp addq %r10,%r13 adcq %rbp,%r8 adcq $0,%r9 movq %rax,%rcx mulq 0(%rsi) addq %rax,%r11 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 8(%rsi) addq %rbp,%r12 adcq $0,%rdx addq %rax,%r12 movq %rcx,%rax adcq $0,%rdx movq %rdx,%rbp mulq 16(%rsi) addq %rbp,%r13 adcq $0,%rdx addq %rax,%r13 movq %rcx,%rax adcq $0,%rdx movq %r11,%rcx imulq %r15,%r11 movq %rdx,%rbp mulq 24(%rsi) addq %rbp,%r8 adcq $0,%rdx xorq %r10,%r10 addq %rax,%r8 movq %r11,%rax adcq %rdx,%r9 adcq $0,%r10 mulq 0(%r14) movq %r11,%rbp addq %rax,%rcx movq %r11,%rax adcq %rdx,%rcx subq %r11,%r13 sbbq $0,%r11 mulq 8(%r14) addq %rcx,%r12 adcq $0,%rdx addq %rax,%r12 movq %rbp,%rax adcq %rdx,%r13 movq %rbp,%rdx adcq $0,%r11 shlq $32,%rax shrq $32,%rdx subq %rax,%r8 sbbq %rdx,%rbp addq %r11,%r8 adcq %rbp,%r9 adcq $0,%r10 movq %r12,%rsi subq 0(%r14),%r12 movq %r13,%r11 sbbq 8(%r14),%r13 movq %r8,%rcx sbbq 16(%r14),%r8 movq %r9,%rbp sbbq 24(%r14),%r9 sbbq $0,%r10 cmovcq %rsi,%r12 cmovcq %r11,%r13 cmovcq %rcx,%r8 cmovcq %rbp,%r9 movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lord_mul_epilogue: ret .cfi_endproc .size ecp_nistz256_ord_mul_mont,.-ecp_nistz256_ord_mul_mont .globl ecp_nistz256_ord_sqr_mont .hidden ecp_nistz256_ord_sqr_mont .type ecp_nistz256_ord_sqr_mont,@function .align 32 ecp_nistz256_ord_sqr_mont: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx cmpl $0x80100,%ecx je .Lecp_nistz256_ord_sqr_montx pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lord_sqr_body: movq 0(%rsi),%r8 movq 8(%rsi),%rax movq 16(%rsi),%r14 movq 24(%rsi),%r15 leaq .Lord(%rip),%rsi movq %rdx,%rbx jmp .Loop_ord_sqr .align 32 .Loop_ord_sqr: movq %rax,%rbp mulq %r8 movq %rax,%r9 .byte 102,72,15,110,205 movq %r14,%rax movq %rdx,%r10 mulq %r8 addq %rax,%r10 movq %r15,%rax .byte 102,73,15,110,214 adcq $0,%rdx movq %rdx,%r11 mulq %r8 addq %rax,%r11 movq %r15,%rax .byte 102,73,15,110,223 adcq $0,%rdx movq %rdx,%r12 mulq %r14 movq %rax,%r13 movq %r14,%rax movq %rdx,%r14 mulq %rbp addq %rax,%r11 movq %r15,%rax adcq $0,%rdx movq %rdx,%r15 mulq %rbp addq %rax,%r12 adcq $0,%rdx addq %r15,%r12 adcq %rdx,%r13 adcq $0,%r14 xorq %r15,%r15 movq %r8,%rax addq %r9,%r9 adcq %r10,%r10 adcq %r11,%r11 adcq %r12,%r12 adcq %r13,%r13 adcq %r14,%r14 adcq $0,%r15 mulq %rax movq %rax,%r8 .byte 102,72,15,126,200 movq %rdx,%rbp mulq %rax addq %rbp,%r9 adcq %rax,%r10 .byte 102,72,15,126,208 adcq $0,%rdx movq %rdx,%rbp mulq %rax addq %rbp,%r11 adcq %rax,%r12 .byte 102,72,15,126,216 adcq $0,%rdx movq %rdx,%rbp movq %r8,%rcx imulq 32(%rsi),%r8 mulq %rax addq %rbp,%r13 adcq %rax,%r14 movq 0(%rsi),%rax adcq %rdx,%r15 mulq %r8 movq %r8,%rbp addq %rax,%rcx movq 8(%rsi),%rax adcq %rdx,%rcx subq %r8,%r10 sbbq $0,%rbp mulq %r8 addq %rcx,%r9 adcq $0,%rdx addq %rax,%r9 movq %r8,%rax adcq %rdx,%r10 movq %r8,%rdx adcq $0,%rbp movq %r9,%rcx imulq 32(%rsi),%r9 shlq $32,%rax shrq $32,%rdx subq %rax,%r11 movq 0(%rsi),%rax sbbq %rdx,%r8 addq %rbp,%r11 adcq $0,%r8 mulq %r9 movq %r9,%rbp addq %rax,%rcx movq 8(%rsi),%rax adcq %rdx,%rcx subq %r9,%r11 sbbq $0,%rbp mulq %r9 addq %rcx,%r10 adcq $0,%rdx addq %rax,%r10 movq %r9,%rax adcq %rdx,%r11 movq %r9,%rdx adcq $0,%rbp movq %r10,%rcx imulq 32(%rsi),%r10 shlq $32,%rax shrq $32,%rdx subq %rax,%r8 movq 0(%rsi),%rax sbbq %rdx,%r9 addq %rbp,%r8 adcq $0,%r9 mulq %r10 movq %r10,%rbp addq %rax,%rcx movq 8(%rsi),%rax adcq %rdx,%rcx subq %r10,%r8 sbbq $0,%rbp mulq %r10 addq %rcx,%r11 adcq $0,%rdx addq %rax,%r11 movq %r10,%rax adcq %rdx,%r8 movq %r10,%rdx adcq $0,%rbp movq %r11,%rcx imulq 32(%rsi),%r11 shlq $32,%rax shrq $32,%rdx subq %rax,%r9 movq 0(%rsi),%rax sbbq %rdx,%r10 addq %rbp,%r9 adcq $0,%r10 mulq %r11 movq %r11,%rbp addq %rax,%rcx movq 8(%rsi),%rax adcq %rdx,%rcx subq %r11,%r9 sbbq $0,%rbp mulq %r11 addq %rcx,%r8 adcq $0,%rdx addq %rax,%r8 movq %r11,%rax adcq %rdx,%r9 movq %r11,%rdx adcq $0,%rbp shlq $32,%rax shrq $32,%rdx subq %rax,%r10 sbbq %rdx,%r11 addq %rbp,%r10 adcq $0,%r11 xorq %rdx,%rdx addq %r12,%r8 adcq %r13,%r9 movq %r8,%r12 adcq %r14,%r10 adcq %r15,%r11 movq %r9,%rax adcq $0,%rdx subq 0(%rsi),%r8 movq %r10,%r14 sbbq 8(%rsi),%r9 sbbq 16(%rsi),%r10 movq %r11,%r15 sbbq 24(%rsi),%r11 sbbq $0,%rdx cmovcq %r12,%r8 cmovncq %r9,%rax cmovncq %r10,%r14 cmovncq %r11,%r15 decq %rbx jnz .Loop_ord_sqr movq %r8,0(%rdi) movq %rax,8(%rdi) pxor %xmm1,%xmm1 movq %r14,16(%rdi) pxor %xmm2,%xmm2 movq %r15,24(%rdi) pxor %xmm3,%xmm3 movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lord_sqr_epilogue: ret .cfi_endproc .size ecp_nistz256_ord_sqr_mont,.-ecp_nistz256_ord_sqr_mont .type ecp_nistz256_ord_mul_montx,@function .align 32 ecp_nistz256_ord_mul_montx: .cfi_startproc .Lecp_nistz256_ord_mul_montx: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lord_mulx_body: movq %rdx,%rbx movq 0(%rdx),%rdx movq 0(%rsi),%r9 movq 8(%rsi),%r10 movq 16(%rsi),%r11 movq 24(%rsi),%r12 leaq -128(%rsi),%rsi leaq .Lord-128(%rip),%r14 movq .LordK(%rip),%r15 mulxq %r9,%r8,%r9 mulxq %r10,%rcx,%r10 mulxq %r11,%rbp,%r11 addq %rcx,%r9 mulxq %r12,%rcx,%r12 movq %r8,%rdx mulxq %r15,%rdx,%rax adcq %rbp,%r10 adcq %rcx,%r11 adcq $0,%r12 xorq %r13,%r13 mulxq 0+128(%r14),%rcx,%rbp adcxq %rcx,%r8 adoxq %rbp,%r9 mulxq 8+128(%r14),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 mulxq 16+128(%r14),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 24+128(%r14),%rcx,%rbp movq 8(%rbx),%rdx adcxq %rcx,%r11 adoxq %rbp,%r12 adcxq %r8,%r12 adoxq %r8,%r13 adcq $0,%r13 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 24+128(%rsi),%rcx,%rbp movq %r9,%rdx mulxq %r15,%rdx,%rax adcxq %rcx,%r12 adoxq %rbp,%r13 adcxq %r8,%r13 adoxq %r8,%r8 adcq $0,%r8 mulxq 0+128(%r14),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 mulxq 8+128(%r14),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 16+128(%r14),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 24+128(%r14),%rcx,%rbp movq 16(%rbx),%rdx adcxq %rcx,%r12 adoxq %rbp,%r13 adcxq %r9,%r13 adoxq %r9,%r8 adcq $0,%r8 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 24+128(%rsi),%rcx,%rbp movq %r10,%rdx mulxq %r15,%rdx,%rax adcxq %rcx,%r13 adoxq %rbp,%r8 adcxq %r9,%r8 adoxq %r9,%r9 adcq $0,%r9 mulxq 0+128(%r14),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 8+128(%r14),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 16+128(%r14),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 24+128(%r14),%rcx,%rbp movq 24(%rbx),%rdx adcxq %rcx,%r13 adoxq %rbp,%r8 adcxq %r10,%r8 adoxq %r10,%r9 adcq $0,%r9 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r13 adoxq %rbp,%r8 mulxq 24+128(%rsi),%rcx,%rbp movq %r11,%rdx mulxq %r15,%rdx,%rax adcxq %rcx,%r8 adoxq %rbp,%r9 adcxq %r10,%r9 adoxq %r10,%r10 adcq $0,%r10 mulxq 0+128(%r14),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 8+128(%r14),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 16+128(%r14),%rcx,%rbp adcxq %rcx,%r13 adoxq %rbp,%r8 mulxq 24+128(%r14),%rcx,%rbp leaq 128(%r14),%r14 movq %r12,%rbx adcxq %rcx,%r8 adoxq %rbp,%r9 movq %r13,%rdx adcxq %r11,%r9 adoxq %r11,%r10 adcq $0,%r10 movq %r8,%rcx subq 0(%r14),%r12 sbbq 8(%r14),%r13 sbbq 16(%r14),%r8 movq %r9,%rbp sbbq 24(%r14),%r9 sbbq $0,%r10 cmovcq %rbx,%r12 cmovcq %rdx,%r13 cmovcq %rcx,%r8 cmovcq %rbp,%r9 movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lord_mulx_epilogue: ret .cfi_endproc .size ecp_nistz256_ord_mul_montx,.-ecp_nistz256_ord_mul_montx .type ecp_nistz256_ord_sqr_montx,@function .align 32 ecp_nistz256_ord_sqr_montx: .cfi_startproc .Lecp_nistz256_ord_sqr_montx: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lord_sqrx_body: movq %rdx,%rbx movq 0(%rsi),%rdx movq 8(%rsi),%r14 movq 16(%rsi),%r15 movq 24(%rsi),%r8 leaq .Lord(%rip),%rsi jmp .Loop_ord_sqrx .align 32 .Loop_ord_sqrx: mulxq %r14,%r9,%r10 mulxq %r15,%rcx,%r11 movq %rdx,%rax .byte 102,73,15,110,206 mulxq %r8,%rbp,%r12 movq %r14,%rdx addq %rcx,%r10 .byte 102,73,15,110,215 adcq %rbp,%r11 adcq $0,%r12 xorq %r13,%r13 mulxq %r15,%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq %r8,%rcx,%rbp movq %r15,%rdx adcxq %rcx,%r12 adoxq %rbp,%r13 adcq $0,%r13 mulxq %r8,%rcx,%r14 movq %rax,%rdx .byte 102,73,15,110,216 xorq %r15,%r15 adcxq %r9,%r9 adoxq %rcx,%r13 adcxq %r10,%r10 adoxq %r15,%r14 mulxq %rdx,%r8,%rbp .byte 102,72,15,126,202 adcxq %r11,%r11 adoxq %rbp,%r9 adcxq %r12,%r12 mulxq %rdx,%rcx,%rax .byte 102,72,15,126,210 adcxq %r13,%r13 adoxq %rcx,%r10 adcxq %r14,%r14 mulxq %rdx,%rcx,%rbp .byte 0x67 .byte 102,72,15,126,218 adoxq %rax,%r11 adcxq %r15,%r15 adoxq %rcx,%r12 adoxq %rbp,%r13 mulxq %rdx,%rcx,%rax adoxq %rcx,%r14 adoxq %rax,%r15 movq %r8,%rdx mulxq 32(%rsi),%rdx,%rcx xorq %rax,%rax mulxq 0(%rsi),%rcx,%rbp adcxq %rcx,%r8 adoxq %rbp,%r9 mulxq 8(%rsi),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 mulxq 16(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 24(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r8 adcxq %rax,%r8 movq %r9,%rdx mulxq 32(%rsi),%rdx,%rcx mulxq 0(%rsi),%rcx,%rbp adoxq %rcx,%r9 adcxq %rbp,%r10 mulxq 8(%rsi),%rcx,%rbp adoxq %rcx,%r10 adcxq %rbp,%r11 mulxq 16(%rsi),%rcx,%rbp adoxq %rcx,%r11 adcxq %rbp,%r8 mulxq 24(%rsi),%rcx,%rbp adoxq %rcx,%r8 adcxq %rbp,%r9 adoxq %rax,%r9 movq %r10,%rdx mulxq 32(%rsi),%rdx,%rcx mulxq 0(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 8(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r8 mulxq 16(%rsi),%rcx,%rbp adcxq %rcx,%r8 adoxq %rbp,%r9 mulxq 24(%rsi),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 adcxq %rax,%r10 movq %r11,%rdx mulxq 32(%rsi),%rdx,%rcx mulxq 0(%rsi),%rcx,%rbp adoxq %rcx,%r11 adcxq %rbp,%r8 mulxq 8(%rsi),%rcx,%rbp adoxq %rcx,%r8 adcxq %rbp,%r9 mulxq 16(%rsi),%rcx,%rbp adoxq %rcx,%r9 adcxq %rbp,%r10 mulxq 24(%rsi),%rcx,%rbp adoxq %rcx,%r10 adcxq %rbp,%r11 adoxq %rax,%r11 addq %r8,%r12 adcq %r13,%r9 movq %r12,%rdx adcq %r14,%r10 adcq %r15,%r11 movq %r9,%r14 adcq $0,%rax subq 0(%rsi),%r12 movq %r10,%r15 sbbq 8(%rsi),%r9 sbbq 16(%rsi),%r10 movq %r11,%r8 sbbq 24(%rsi),%r11 sbbq $0,%rax cmovncq %r12,%rdx cmovncq %r9,%r14 cmovncq %r10,%r15 cmovncq %r11,%r8 decq %rbx jnz .Loop_ord_sqrx movq %rdx,0(%rdi) movq %r14,8(%rdi) pxor %xmm1,%xmm1 movq %r15,16(%rdi) pxor %xmm2,%xmm2 movq %r8,24(%rdi) pxor %xmm3,%xmm3 movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lord_sqrx_epilogue: ret .cfi_endproc .size ecp_nistz256_ord_sqr_montx,.-ecp_nistz256_ord_sqr_montx .globl ecp_nistz256_mul_mont .hidden ecp_nistz256_mul_mont .type ecp_nistz256_mul_mont,@function .align 32 ecp_nistz256_mul_mont: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx .Lmul_mont: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lmul_body: cmpl $0x80100,%ecx je .Lmul_montx movq %rdx,%rbx movq 0(%rdx),%rax movq 0(%rsi),%r9 movq 8(%rsi),%r10 movq 16(%rsi),%r11 movq 24(%rsi),%r12 call __ecp_nistz256_mul_montq jmp .Lmul_mont_done .align 32 .Lmul_montx: movq %rdx,%rbx movq 0(%rdx),%rdx movq 0(%rsi),%r9 movq 8(%rsi),%r10 movq 16(%rsi),%r11 movq 24(%rsi),%r12 leaq -128(%rsi),%rsi call __ecp_nistz256_mul_montx .Lmul_mont_done: movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lmul_epilogue: ret .cfi_endproc .size ecp_nistz256_mul_mont,.-ecp_nistz256_mul_mont .type __ecp_nistz256_mul_montq,@function .align 32 __ecp_nistz256_mul_montq: .cfi_startproc movq %rax,%rbp mulq %r9 movq .Lpoly+8(%rip),%r14 movq %rax,%r8 movq %rbp,%rax movq %rdx,%r9 mulq %r10 movq .Lpoly+24(%rip),%r15 addq %rax,%r9 movq %rbp,%rax adcq $0,%rdx movq %rdx,%r10 mulq %r11 addq %rax,%r10 movq %rbp,%rax adcq $0,%rdx movq %rdx,%r11 mulq %r12 addq %rax,%r11 movq %r8,%rax adcq $0,%rdx xorq %r13,%r13 movq %rdx,%r12 movq %r8,%rbp shlq $32,%r8 mulq %r15 shrq $32,%rbp addq %r8,%r9 adcq %rbp,%r10 adcq %rax,%r11 movq 8(%rbx),%rax adcq %rdx,%r12 adcq $0,%r13 xorq %r8,%r8 movq %rax,%rbp mulq 0(%rsi) addq %rax,%r9 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 8(%rsi) addq %rcx,%r10 adcq $0,%rdx addq %rax,%r10 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 16(%rsi) addq %rcx,%r11 adcq $0,%rdx addq %rax,%r11 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 24(%rsi) addq %rcx,%r12 adcq $0,%rdx addq %rax,%r12 movq %r9,%rax adcq %rdx,%r13 adcq $0,%r8 movq %r9,%rbp shlq $32,%r9 mulq %r15 shrq $32,%rbp addq %r9,%r10 adcq %rbp,%r11 adcq %rax,%r12 movq 16(%rbx),%rax adcq %rdx,%r13 adcq $0,%r8 xorq %r9,%r9 movq %rax,%rbp mulq 0(%rsi) addq %rax,%r10 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 8(%rsi) addq %rcx,%r11 adcq $0,%rdx addq %rax,%r11 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 16(%rsi) addq %rcx,%r12 adcq $0,%rdx addq %rax,%r12 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 24(%rsi) addq %rcx,%r13 adcq $0,%rdx addq %rax,%r13 movq %r10,%rax adcq %rdx,%r8 adcq $0,%r9 movq %r10,%rbp shlq $32,%r10 mulq %r15 shrq $32,%rbp addq %r10,%r11 adcq %rbp,%r12 adcq %rax,%r13 movq 24(%rbx),%rax adcq %rdx,%r8 adcq $0,%r9 xorq %r10,%r10 movq %rax,%rbp mulq 0(%rsi) addq %rax,%r11 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 8(%rsi) addq %rcx,%r12 adcq $0,%rdx addq %rax,%r12 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 16(%rsi) addq %rcx,%r13 adcq $0,%rdx addq %rax,%r13 movq %rbp,%rax adcq $0,%rdx movq %rdx,%rcx mulq 24(%rsi) addq %rcx,%r8 adcq $0,%rdx addq %rax,%r8 movq %r11,%rax adcq %rdx,%r9 adcq $0,%r10 movq %r11,%rbp shlq $32,%r11 mulq %r15 shrq $32,%rbp addq %r11,%r12 adcq %rbp,%r13 movq %r12,%rcx adcq %rax,%r8 adcq %rdx,%r9 movq %r13,%rbp adcq $0,%r10 subq $-1,%r12 movq %r8,%rbx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%rdx sbbq %r15,%r9 sbbq $0,%r10 cmovcq %rcx,%r12 cmovcq %rbp,%r13 movq %r12,0(%rdi) cmovcq %rbx,%r8 movq %r13,8(%rdi) cmovcq %rdx,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_mul_montq,.-__ecp_nistz256_mul_montq .globl ecp_nistz256_sqr_mont .hidden ecp_nistz256_sqr_mont .type ecp_nistz256_sqr_mont,@function .align 32 ecp_nistz256_sqr_mont: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 .Lsqr_body: cmpl $0x80100,%ecx je .Lsqr_montx movq 0(%rsi),%rax movq 8(%rsi),%r14 movq 16(%rsi),%r15 movq 24(%rsi),%r8 call __ecp_nistz256_sqr_montq jmp .Lsqr_mont_done .align 32 .Lsqr_montx: movq 0(%rsi),%rdx movq 8(%rsi),%r14 movq 16(%rsi),%r15 movq 24(%rsi),%r8 leaq -128(%rsi),%rsi call __ecp_nistz256_sqr_montx .Lsqr_mont_done: movq 0(%rsp),%r15 .cfi_restore %r15 movq 8(%rsp),%r14 .cfi_restore %r14 movq 16(%rsp),%r13 .cfi_restore %r13 movq 24(%rsp),%r12 .cfi_restore %r12 movq 32(%rsp),%rbx .cfi_restore %rbx movq 40(%rsp),%rbp .cfi_restore %rbp leaq 48(%rsp),%rsp .cfi_adjust_cfa_offset -48 .Lsqr_epilogue: ret .cfi_endproc .size ecp_nistz256_sqr_mont,.-ecp_nistz256_sqr_mont .type __ecp_nistz256_sqr_montq,@function .align 32 __ecp_nistz256_sqr_montq: .cfi_startproc movq %rax,%r13 mulq %r14 movq %rax,%r9 movq %r15,%rax movq %rdx,%r10 mulq %r13 addq %rax,%r10 movq %r8,%rax adcq $0,%rdx movq %rdx,%r11 mulq %r13 addq %rax,%r11 movq %r15,%rax adcq $0,%rdx movq %rdx,%r12 mulq %r14 addq %rax,%r11 movq %r8,%rax adcq $0,%rdx movq %rdx,%rbp mulq %r14 addq %rax,%r12 movq %r8,%rax adcq $0,%rdx addq %rbp,%r12 movq %rdx,%r13 adcq $0,%r13 mulq %r15 xorq %r15,%r15 addq %rax,%r13 movq 0(%rsi),%rax movq %rdx,%r14 adcq $0,%r14 addq %r9,%r9 adcq %r10,%r10 adcq %r11,%r11 adcq %r12,%r12 adcq %r13,%r13 adcq %r14,%r14 adcq $0,%r15 mulq %rax movq %rax,%r8 movq 8(%rsi),%rax movq %rdx,%rcx mulq %rax addq %rcx,%r9 adcq %rax,%r10 movq 16(%rsi),%rax adcq $0,%rdx movq %rdx,%rcx mulq %rax addq %rcx,%r11 adcq %rax,%r12 movq 24(%rsi),%rax adcq $0,%rdx movq %rdx,%rcx mulq %rax addq %rcx,%r13 adcq %rax,%r14 movq %r8,%rax adcq %rdx,%r15 movq .Lpoly+8(%rip),%rsi movq .Lpoly+24(%rip),%rbp movq %r8,%rcx shlq $32,%r8 mulq %rbp shrq $32,%rcx addq %r8,%r9 adcq %rcx,%r10 adcq %rax,%r11 movq %r9,%rax adcq $0,%rdx movq %r9,%rcx shlq $32,%r9 movq %rdx,%r8 mulq %rbp shrq $32,%rcx addq %r9,%r10 adcq %rcx,%r11 adcq %rax,%r8 movq %r10,%rax adcq $0,%rdx movq %r10,%rcx shlq $32,%r10 movq %rdx,%r9 mulq %rbp shrq $32,%rcx addq %r10,%r11 adcq %rcx,%r8 adcq %rax,%r9 movq %r11,%rax adcq $0,%rdx movq %r11,%rcx shlq $32,%r11 movq %rdx,%r10 mulq %rbp shrq $32,%rcx addq %r11,%r8 adcq %rcx,%r9 adcq %rax,%r10 adcq $0,%rdx xorq %r11,%r11 addq %r8,%r12 adcq %r9,%r13 movq %r12,%r8 adcq %r10,%r14 adcq %rdx,%r15 movq %r13,%r9 adcq $0,%r11 subq $-1,%r12 movq %r14,%r10 sbbq %rsi,%r13 sbbq $0,%r14 movq %r15,%rcx sbbq %rbp,%r15 sbbq $0,%r11 cmovcq %r8,%r12 cmovcq %r9,%r13 movq %r12,0(%rdi) cmovcq %r10,%r14 movq %r13,8(%rdi) cmovcq %rcx,%r15 movq %r14,16(%rdi) movq %r15,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_sqr_montq,.-__ecp_nistz256_sqr_montq .type __ecp_nistz256_mul_montx,@function .align 32 __ecp_nistz256_mul_montx: .cfi_startproc mulxq %r9,%r8,%r9 mulxq %r10,%rcx,%r10 movq $32,%r14 xorq %r13,%r13 mulxq %r11,%rbp,%r11 movq .Lpoly+24(%rip),%r15 adcq %rcx,%r9 mulxq %r12,%rcx,%r12 movq %r8,%rdx adcq %rbp,%r10 shlxq %r14,%r8,%rbp adcq %rcx,%r11 shrxq %r14,%r8,%rcx adcq $0,%r12 addq %rbp,%r9 adcq %rcx,%r10 mulxq %r15,%rcx,%rbp movq 8(%rbx),%rdx adcq %rcx,%r11 adcq %rbp,%r12 adcq $0,%r13 xorq %r8,%r8 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r9 adoxq %rbp,%r10 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 24+128(%rsi),%rcx,%rbp movq %r9,%rdx adcxq %rcx,%r12 shlxq %r14,%r9,%rcx adoxq %rbp,%r13 shrxq %r14,%r9,%rbp adcxq %r8,%r13 adoxq %r8,%r8 adcq $0,%r8 addq %rcx,%r10 adcq %rbp,%r11 mulxq %r15,%rcx,%rbp movq 16(%rbx),%rdx adcq %rcx,%r12 adcq %rbp,%r13 adcq $0,%r8 xorq %r9,%r9 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r10 adoxq %rbp,%r11 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 24+128(%rsi),%rcx,%rbp movq %r10,%rdx adcxq %rcx,%r13 shlxq %r14,%r10,%rcx adoxq %rbp,%r8 shrxq %r14,%r10,%rbp adcxq %r9,%r8 adoxq %r9,%r9 adcq $0,%r9 addq %rcx,%r11 adcq %rbp,%r12 mulxq %r15,%rcx,%rbp movq 24(%rbx),%rdx adcq %rcx,%r13 adcq %rbp,%r8 adcq $0,%r9 xorq %r10,%r10 mulxq 0+128(%rsi),%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq 8+128(%rsi),%rcx,%rbp adcxq %rcx,%r12 adoxq %rbp,%r13 mulxq 16+128(%rsi),%rcx,%rbp adcxq %rcx,%r13 adoxq %rbp,%r8 mulxq 24+128(%rsi),%rcx,%rbp movq %r11,%rdx adcxq %rcx,%r8 shlxq %r14,%r11,%rcx adoxq %rbp,%r9 shrxq %r14,%r11,%rbp adcxq %r10,%r9 adoxq %r10,%r10 adcq $0,%r10 addq %rcx,%r12 adcq %rbp,%r13 mulxq %r15,%rcx,%rbp movq %r12,%rbx movq .Lpoly+8(%rip),%r14 adcq %rcx,%r8 movq %r13,%rdx adcq %rbp,%r9 adcq $0,%r10 xorl %eax,%eax movq %r8,%rcx sbbq $-1,%r12 sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%rbp sbbq %r15,%r9 sbbq $0,%r10 cmovcq %rbx,%r12 cmovcq %rdx,%r13 movq %r12,0(%rdi) cmovcq %rcx,%r8 movq %r13,8(%rdi) cmovcq %rbp,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_mul_montx,.-__ecp_nistz256_mul_montx .type __ecp_nistz256_sqr_montx,@function .align 32 __ecp_nistz256_sqr_montx: .cfi_startproc mulxq %r14,%r9,%r10 mulxq %r15,%rcx,%r11 xorl %eax,%eax adcq %rcx,%r10 mulxq %r8,%rbp,%r12 movq %r14,%rdx adcq %rbp,%r11 adcq $0,%r12 xorq %r13,%r13 mulxq %r15,%rcx,%rbp adcxq %rcx,%r11 adoxq %rbp,%r12 mulxq %r8,%rcx,%rbp movq %r15,%rdx adcxq %rcx,%r12 adoxq %rbp,%r13 adcq $0,%r13 mulxq %r8,%rcx,%r14 movq 0+128(%rsi),%rdx xorq %r15,%r15 adcxq %r9,%r9 adoxq %rcx,%r13 adcxq %r10,%r10 adoxq %r15,%r14 mulxq %rdx,%r8,%rbp movq 8+128(%rsi),%rdx adcxq %r11,%r11 adoxq %rbp,%r9 adcxq %r12,%r12 mulxq %rdx,%rcx,%rax movq 16+128(%rsi),%rdx adcxq %r13,%r13 adoxq %rcx,%r10 adcxq %r14,%r14 .byte 0x67 mulxq %rdx,%rcx,%rbp movq 24+128(%rsi),%rdx adoxq %rax,%r11 adcxq %r15,%r15 adoxq %rcx,%r12 movq $32,%rsi adoxq %rbp,%r13 .byte 0x67,0x67 mulxq %rdx,%rcx,%rax movq .Lpoly+24(%rip),%rdx adoxq %rcx,%r14 shlxq %rsi,%r8,%rcx adoxq %rax,%r15 shrxq %rsi,%r8,%rax movq %rdx,%rbp addq %rcx,%r9 adcq %rax,%r10 mulxq %r8,%rcx,%r8 adcq %rcx,%r11 shlxq %rsi,%r9,%rcx adcq $0,%r8 shrxq %rsi,%r9,%rax addq %rcx,%r10 adcq %rax,%r11 mulxq %r9,%rcx,%r9 adcq %rcx,%r8 shlxq %rsi,%r10,%rcx adcq $0,%r9 shrxq %rsi,%r10,%rax addq %rcx,%r11 adcq %rax,%r8 mulxq %r10,%rcx,%r10 adcq %rcx,%r9 shlxq %rsi,%r11,%rcx adcq $0,%r10 shrxq %rsi,%r11,%rax addq %rcx,%r8 adcq %rax,%r9 mulxq %r11,%rcx,%r11 adcq %rcx,%r10 adcq $0,%r11 xorq %rdx,%rdx addq %r8,%r12 movq .Lpoly+8(%rip),%rsi adcq %r9,%r13 movq %r12,%r8 adcq %r10,%r14 adcq %r11,%r15 movq %r13,%r9 adcq $0,%rdx subq $-1,%r12 movq %r14,%r10 sbbq %rsi,%r13 sbbq $0,%r14 movq %r15,%r11 sbbq %rbp,%r15 sbbq $0,%rdx cmovcq %r8,%r12 cmovcq %r9,%r13 movq %r12,0(%rdi) cmovcq %r10,%r14 movq %r13,8(%rdi) cmovcq %r11,%r15 movq %r14,16(%rdi) movq %r15,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_sqr_montx,.-__ecp_nistz256_sqr_montx .globl ecp_nistz256_select_w5 .hidden ecp_nistz256_select_w5 .type ecp_nistz256_select_w5,@function .align 32 ecp_nistz256_select_w5: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rax movq 8(%rax),%rax testl $32,%eax jnz .Lavx2_select_w5 movdqa .LOne(%rip),%xmm0 movd %edx,%xmm1 pxor %xmm2,%xmm2 pxor %xmm3,%xmm3 pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 pxor %xmm6,%xmm6 pxor %xmm7,%xmm7 movdqa %xmm0,%xmm8 pshufd $0,%xmm1,%xmm1 movq $16,%rax .Lselect_loop_sse_w5: movdqa %xmm8,%xmm15 paddd %xmm0,%xmm8 pcmpeqd %xmm1,%xmm15 movdqa 0(%rsi),%xmm9 movdqa 16(%rsi),%xmm10 movdqa 32(%rsi),%xmm11 movdqa 48(%rsi),%xmm12 movdqa 64(%rsi),%xmm13 movdqa 80(%rsi),%xmm14 leaq 96(%rsi),%rsi pand %xmm15,%xmm9 pand %xmm15,%xmm10 por %xmm9,%xmm2 pand %xmm15,%xmm11 por %xmm10,%xmm3 pand %xmm15,%xmm12 por %xmm11,%xmm4 pand %xmm15,%xmm13 por %xmm12,%xmm5 pand %xmm15,%xmm14 por %xmm13,%xmm6 por %xmm14,%xmm7 decq %rax jnz .Lselect_loop_sse_w5 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqu %xmm4,32(%rdi) movdqu %xmm5,48(%rdi) movdqu %xmm6,64(%rdi) movdqu %xmm7,80(%rdi) ret .cfi_endproc .LSEH_end_ecp_nistz256_select_w5: .size ecp_nistz256_select_w5,.-ecp_nistz256_select_w5 .globl ecp_nistz256_select_w7 .hidden ecp_nistz256_select_w7 .type ecp_nistz256_select_w7,@function .align 32 ecp_nistz256_select_w7: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rax movq 8(%rax),%rax testl $32,%eax jnz .Lavx2_select_w7 movdqa .LOne(%rip),%xmm8 movd %edx,%xmm1 pxor %xmm2,%xmm2 pxor %xmm3,%xmm3 pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 movdqa %xmm8,%xmm0 pshufd $0,%xmm1,%xmm1 movq $64,%rax .Lselect_loop_sse_w7: movdqa %xmm8,%xmm15 paddd %xmm0,%xmm8 movdqa 0(%rsi),%xmm9 movdqa 16(%rsi),%xmm10 pcmpeqd %xmm1,%xmm15 movdqa 32(%rsi),%xmm11 movdqa 48(%rsi),%xmm12 leaq 64(%rsi),%rsi pand %xmm15,%xmm9 pand %xmm15,%xmm10 por %xmm9,%xmm2 pand %xmm15,%xmm11 por %xmm10,%xmm3 pand %xmm15,%xmm12 por %xmm11,%xmm4 prefetcht0 255(%rsi) por %xmm12,%xmm5 decq %rax jnz .Lselect_loop_sse_w7 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqu %xmm4,32(%rdi) movdqu %xmm5,48(%rdi) ret .cfi_endproc .LSEH_end_ecp_nistz256_select_w7: .size ecp_nistz256_select_w7,.-ecp_nistz256_select_w7 .type ecp_nistz256_avx2_select_w5,@function .align 32 ecp_nistz256_avx2_select_w5: .cfi_startproc .Lavx2_select_w5: vzeroupper vmovdqa .LTwo(%rip),%ymm0 vpxor %ymm2,%ymm2,%ymm2 vpxor %ymm3,%ymm3,%ymm3 vpxor %ymm4,%ymm4,%ymm4 vmovdqa .LOne(%rip),%ymm5 vmovdqa .LTwo(%rip),%ymm10 vmovd %edx,%xmm1 vpermd %ymm1,%ymm2,%ymm1 movq $8,%rax .Lselect_loop_avx2_w5: vmovdqa 0(%rsi),%ymm6 vmovdqa 32(%rsi),%ymm7 vmovdqa 64(%rsi),%ymm8 vmovdqa 96(%rsi),%ymm11 vmovdqa 128(%rsi),%ymm12 vmovdqa 160(%rsi),%ymm13 vpcmpeqd %ymm1,%ymm5,%ymm9 vpcmpeqd %ymm1,%ymm10,%ymm14 vpaddd %ymm0,%ymm5,%ymm5 vpaddd %ymm0,%ymm10,%ymm10 leaq 192(%rsi),%rsi vpand %ymm9,%ymm6,%ymm6 vpand %ymm9,%ymm7,%ymm7 vpand %ymm9,%ymm8,%ymm8 vpand %ymm14,%ymm11,%ymm11 vpand %ymm14,%ymm12,%ymm12 vpand %ymm14,%ymm13,%ymm13 vpxor %ymm6,%ymm2,%ymm2 vpxor %ymm7,%ymm3,%ymm3 vpxor %ymm8,%ymm4,%ymm4 vpxor %ymm11,%ymm2,%ymm2 vpxor %ymm12,%ymm3,%ymm3 vpxor %ymm13,%ymm4,%ymm4 decq %rax jnz .Lselect_loop_avx2_w5 vmovdqu %ymm2,0(%rdi) vmovdqu %ymm3,32(%rdi) vmovdqu %ymm4,64(%rdi) vzeroupper ret .cfi_endproc .LSEH_end_ecp_nistz256_avx2_select_w5: .size ecp_nistz256_avx2_select_w5,.-ecp_nistz256_avx2_select_w5 .type ecp_nistz256_avx2_select_w7,@function .align 32 ecp_nistz256_avx2_select_w7: .cfi_startproc .Lavx2_select_w7: _CET_ENDBR vzeroupper vmovdqa .LThree(%rip),%ymm0 vpxor %ymm2,%ymm2,%ymm2 vpxor %ymm3,%ymm3,%ymm3 vmovdqa .LOne(%rip),%ymm4 vmovdqa .LTwo(%rip),%ymm8 vmovdqa .LThree(%rip),%ymm12 vmovd %edx,%xmm1 vpermd %ymm1,%ymm2,%ymm1 movq $21,%rax .Lselect_loop_avx2_w7: vmovdqa 0(%rsi),%ymm5 vmovdqa 32(%rsi),%ymm6 vmovdqa 64(%rsi),%ymm9 vmovdqa 96(%rsi),%ymm10 vmovdqa 128(%rsi),%ymm13 vmovdqa 160(%rsi),%ymm14 vpcmpeqd %ymm1,%ymm4,%ymm7 vpcmpeqd %ymm1,%ymm8,%ymm11 vpcmpeqd %ymm1,%ymm12,%ymm15 vpaddd %ymm0,%ymm4,%ymm4 vpaddd %ymm0,%ymm8,%ymm8 vpaddd %ymm0,%ymm12,%ymm12 leaq 192(%rsi),%rsi vpand %ymm7,%ymm5,%ymm5 vpand %ymm7,%ymm6,%ymm6 vpand %ymm11,%ymm9,%ymm9 vpand %ymm11,%ymm10,%ymm10 vpand %ymm15,%ymm13,%ymm13 vpand %ymm15,%ymm14,%ymm14 vpxor %ymm5,%ymm2,%ymm2 vpxor %ymm6,%ymm3,%ymm3 vpxor %ymm9,%ymm2,%ymm2 vpxor %ymm10,%ymm3,%ymm3 vpxor %ymm13,%ymm2,%ymm2 vpxor %ymm14,%ymm3,%ymm3 decq %rax jnz .Lselect_loop_avx2_w7 vmovdqa 0(%rsi),%ymm5 vmovdqa 32(%rsi),%ymm6 vpcmpeqd %ymm1,%ymm4,%ymm7 vpand %ymm7,%ymm5,%ymm5 vpand %ymm7,%ymm6,%ymm6 vpxor %ymm5,%ymm2,%ymm2 vpxor %ymm6,%ymm3,%ymm3 vmovdqu %ymm2,0(%rdi) vmovdqu %ymm3,32(%rdi) vzeroupper ret .cfi_endproc .LSEH_end_ecp_nistz256_avx2_select_w7: .size ecp_nistz256_avx2_select_w7,.-ecp_nistz256_avx2_select_w7 .type __ecp_nistz256_add_toq,@function .align 32 __ecp_nistz256_add_toq: .cfi_startproc xorq %r11,%r11 addq 0(%rbx),%r12 adcq 8(%rbx),%r13 movq %r12,%rax adcq 16(%rbx),%r8 adcq 24(%rbx),%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 cmovcq %rbp,%r13 movq %r12,0(%rdi) cmovcq %rcx,%r8 movq %r13,8(%rdi) cmovcq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_add_toq,.-__ecp_nistz256_add_toq .type __ecp_nistz256_sub_fromq,@function .align 32 __ecp_nistz256_sub_fromq: .cfi_startproc subq 0(%rbx),%r12 sbbq 8(%rbx),%r13 movq %r12,%rax sbbq 16(%rbx),%r8 sbbq 24(%rbx),%r9 movq %r13,%rbp sbbq %r11,%r11 addq $-1,%r12 movq %r8,%rcx adcq %r14,%r13 adcq $0,%r8 movq %r9,%r10 adcq %r15,%r9 testq %r11,%r11 cmovzq %rax,%r12 cmovzq %rbp,%r13 movq %r12,0(%rdi) cmovzq %rcx,%r8 movq %r13,8(%rdi) cmovzq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_sub_fromq,.-__ecp_nistz256_sub_fromq .type __ecp_nistz256_subq,@function .align 32 __ecp_nistz256_subq: .cfi_startproc subq %r12,%rax sbbq %r13,%rbp movq %rax,%r12 sbbq %r8,%rcx sbbq %r9,%r10 movq %rbp,%r13 sbbq %r11,%r11 addq $-1,%rax movq %rcx,%r8 adcq %r14,%rbp adcq $0,%rcx movq %r10,%r9 adcq %r15,%r10 testq %r11,%r11 cmovnzq %rax,%r12 cmovnzq %rbp,%r13 cmovnzq %rcx,%r8 cmovnzq %r10,%r9 ret .cfi_endproc .size __ecp_nistz256_subq,.-__ecp_nistz256_subq .type __ecp_nistz256_mul_by_2q,@function .align 32 __ecp_nistz256_mul_by_2q: .cfi_startproc xorq %r11,%r11 addq %r12,%r12 adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 cmovcq %rbp,%r13 movq %r12,0(%rdi) cmovcq %rcx,%r8 movq %r13,8(%rdi) cmovcq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_mul_by_2q,.-__ecp_nistz256_mul_by_2q .globl ecp_nistz256_point_double .hidden ecp_nistz256_point_double .type ecp_nistz256_point_double,@function .align 32 ecp_nistz256_point_double: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx cmpl $0x80100,%ecx je .Lpoint_doublex pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $160+8,%rsp .cfi_adjust_cfa_offset 32*5+8 .Lpoint_doubleq_body: .Lpoint_double_shortcutq: movdqu 0(%rsi),%xmm0 movq %rsi,%rbx movdqu 16(%rsi),%xmm1 movq 32+0(%rsi),%r12 movq 32+8(%rsi),%r13 movq 32+16(%rsi),%r8 movq 32+24(%rsi),%r9 movq .Lpoly+8(%rip),%r14 movq .Lpoly+24(%rip),%r15 movdqa %xmm0,96(%rsp) movdqa %xmm1,96+16(%rsp) leaq 32(%rdi),%r10 leaq 64(%rdi),%r11 .byte 102,72,15,110,199 .byte 102,73,15,110,202 .byte 102,73,15,110,211 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_by_2q movq 64+0(%rsi),%rax movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 leaq 64-0(%rsi),%rsi leaq 64(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 0+0(%rsp),%rax movq 8+0(%rsp),%r14 leaq 0+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 leaq 0(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 32(%rbx),%rax movq 64+0(%rbx),%r9 movq 64+8(%rbx),%r10 movq 64+16(%rbx),%r11 movq 64+24(%rbx),%r12 leaq 64-0(%rbx),%rsi leaq 32(%rbx),%rbx .byte 102,72,15,126,215 call __ecp_nistz256_mul_montq call __ecp_nistz256_mul_by_2q movq 96+0(%rsp),%r12 movq 96+8(%rsp),%r13 leaq 64(%rsp),%rbx movq 96+16(%rsp),%r8 movq 96+24(%rsp),%r9 leaq 32(%rsp),%rdi call __ecp_nistz256_add_toq movq 96+0(%rsp),%r12 movq 96+8(%rsp),%r13 leaq 64(%rsp),%rbx movq 96+16(%rsp),%r8 movq 96+24(%rsp),%r9 leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromq movq 0+0(%rsp),%rax movq 8+0(%rsp),%r14 leaq 0+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 .byte 102,72,15,126,207 call __ecp_nistz256_sqr_montq xorq %r9,%r9 movq %r12,%rax addq $-1,%r12 movq %r13,%r10 adcq %rsi,%r13 movq %r14,%rcx adcq $0,%r14 movq %r15,%r8 adcq %rbp,%r15 adcq $0,%r9 xorq %rsi,%rsi testq $1,%rax cmovzq %rax,%r12 cmovzq %r10,%r13 cmovzq %rcx,%r14 cmovzq %r8,%r15 cmovzq %rsi,%r9 movq %r13,%rax shrq $1,%r12 shlq $63,%rax movq %r14,%r10 shrq $1,%r13 orq %rax,%r12 shlq $63,%r10 movq %r15,%rcx shrq $1,%r14 orq %r10,%r13 shlq $63,%rcx movq %r12,0(%rdi) shrq $1,%r15 movq %r13,8(%rdi) shlq $63,%r9 orq %rcx,%r14 orq %r9,%r15 movq %r14,16(%rdi) movq %r15,24(%rdi) movq 64(%rsp),%rax leaq 64(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 128(%rsp),%rdi call __ecp_nistz256_mul_by_2q leaq 32(%rsp),%rbx leaq 32(%rsp),%rdi call __ecp_nistz256_add_toq movq 96(%rsp),%rax leaq 96(%rsp),%rbx movq 0+0(%rsp),%r9 movq 8+0(%rsp),%r10 leaq 0+0(%rsp),%rsi movq 16+0(%rsp),%r11 movq 24+0(%rsp),%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 128(%rsp),%rdi call __ecp_nistz256_mul_by_2q movq 0+32(%rsp),%rax movq 8+32(%rsp),%r14 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r15 movq 24+32(%rsp),%r8 .byte 102,72,15,126,199 call __ecp_nistz256_sqr_montq leaq 128(%rsp),%rbx movq %r14,%r8 movq %r15,%r9 movq %rsi,%r14 movq %rbp,%r15 call __ecp_nistz256_sub_fromq movq 0+0(%rsp),%rax movq 0+8(%rsp),%rbp movq 0+16(%rsp),%rcx movq 0+24(%rsp),%r10 leaq 0(%rsp),%rdi call __ecp_nistz256_subq movq 32(%rsp),%rax leaq 32(%rsp),%rbx movq %r12,%r14 xorl %ecx,%ecx movq %r12,0+0(%rsp) movq %r13,%r10 movq %r13,0+8(%rsp) cmovzq %r8,%r11 movq %r8,0+16(%rsp) leaq 0-0(%rsp),%rsi cmovzq %r9,%r12 movq %r9,0+24(%rsp) movq %r14,%r9 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montq .byte 102,72,15,126,203 .byte 102,72,15,126,207 call __ecp_nistz256_sub_fromq leaq 160+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpoint_doubleq_epilogue: ret .cfi_endproc .size ecp_nistz256_point_double,.-ecp_nistz256_point_double .globl ecp_nistz256_point_add .hidden ecp_nistz256_point_add .type ecp_nistz256_point_add,@function .align 32 ecp_nistz256_point_add: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx cmpl $0x80100,%ecx je .Lpoint_addx pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $576+8,%rsp .cfi_adjust_cfa_offset 32*18+8 .Lpoint_addq_body: movdqu 0(%rsi),%xmm0 movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm3 movdqu 64(%rsi),%xmm4 movdqu 80(%rsi),%xmm5 movq %rsi,%rbx movq %rdx,%rsi movdqa %xmm0,384(%rsp) movdqa %xmm1,384+16(%rsp) movdqa %xmm2,416(%rsp) movdqa %xmm3,416+16(%rsp) movdqa %xmm4,448(%rsp) movdqa %xmm5,448+16(%rsp) por %xmm4,%xmm5 movdqu 0(%rsi),%xmm0 pshufd $0xb1,%xmm5,%xmm3 movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 por %xmm3,%xmm5 movdqu 48(%rsi),%xmm3 movq 64+0(%rsi),%rax movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 movdqa %xmm0,480(%rsp) pshufd $0x1e,%xmm5,%xmm4 movdqa %xmm1,480+16(%rsp) movdqu 64(%rsi),%xmm0 movdqu 80(%rsi),%xmm1 movdqa %xmm2,512(%rsp) movdqa %xmm3,512+16(%rsp) por %xmm4,%xmm5 pxor %xmm4,%xmm4 por %xmm0,%xmm1 .byte 102,72,15,110,199 leaq 64-0(%rsi),%rsi movq %rax,544+0(%rsp) movq %r14,544+8(%rsp) movq %r15,544+16(%rsp) movq %r8,544+24(%rsp) leaq 96(%rsp),%rdi call __ecp_nistz256_sqr_montq pcmpeqd %xmm4,%xmm5 pshufd $0xb1,%xmm1,%xmm4 por %xmm1,%xmm4 pshufd $0,%xmm5,%xmm5 pshufd $0x1e,%xmm4,%xmm3 por %xmm3,%xmm4 pxor %xmm3,%xmm3 pcmpeqd %xmm3,%xmm4 pshufd $0,%xmm4,%xmm4 movq 64+0(%rbx),%rax movq 64+8(%rbx),%r14 movq 64+16(%rbx),%r15 movq 64+24(%rbx),%r8 .byte 102,72,15,110,203 leaq 64-0(%rbx),%rsi leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 544(%rsp),%rax leaq 544(%rsp),%rbx movq 0+96(%rsp),%r9 movq 8+96(%rsp),%r10 leaq 0+96(%rsp),%rsi movq 16+96(%rsp),%r11 movq 24+96(%rsp),%r12 leaq 224(%rsp),%rdi call __ecp_nistz256_mul_montq movq 448(%rsp),%rax leaq 448(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montq movq 416(%rsp),%rax leaq 416(%rsp),%rbx movq 0+224(%rsp),%r9 movq 8+224(%rsp),%r10 leaq 0+224(%rsp),%rsi movq 16+224(%rsp),%r11 movq 24+224(%rsp),%r12 leaq 224(%rsp),%rdi call __ecp_nistz256_mul_montq movq 512(%rsp),%rax leaq 512(%rsp),%rbx movq 0+256(%rsp),%r9 movq 8+256(%rsp),%r10 leaq 0+256(%rsp),%rsi movq 16+256(%rsp),%r11 movq 24+256(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 224(%rsp),%rbx leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromq orq %r13,%r12 movdqa %xmm4,%xmm2 orq %r8,%r12 orq %r9,%r12 por %xmm5,%xmm2 .byte 102,73,15,110,220 movq 384(%rsp),%rax leaq 384(%rsp),%rbx movq 0+96(%rsp),%r9 movq 8+96(%rsp),%r10 leaq 0+96(%rsp),%rsi movq 16+96(%rsp),%r11 movq 24+96(%rsp),%r12 leaq 160(%rsp),%rdi call __ecp_nistz256_mul_montq movq 480(%rsp),%rax leaq 480(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 192(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 160(%rsp),%rbx leaq 0(%rsp),%rdi call __ecp_nistz256_sub_fromq orq %r13,%r12 orq %r8,%r12 orq %r9,%r12 .byte 102,73,15,126,208 .byte 102,73,15,126,217 orq %r8,%r12 .byte 0x3e jnz .Ladd_proceedq testq %r9,%r9 jz .Ladd_doubleq .byte 102,72,15,126,199 pxor %xmm0,%xmm0 movdqu %xmm0,0(%rdi) movdqu %xmm0,16(%rdi) movdqu %xmm0,32(%rdi) movdqu %xmm0,48(%rdi) movdqu %xmm0,64(%rdi) movdqu %xmm0,80(%rdi) jmp .Ladd_doneq .align 32 .Ladd_doubleq: .byte 102,72,15,126,206 .byte 102,72,15,126,199 addq $416,%rsp .cfi_adjust_cfa_offset -416 jmp .Lpoint_double_shortcutq .cfi_adjust_cfa_offset 416 .align 32 .Ladd_proceedq: movq 0+64(%rsp),%rax movq 8+64(%rsp),%r14 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r15 movq 24+64(%rsp),%r8 leaq 96(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 448(%rsp),%rax leaq 448(%rsp),%rbx movq 0+0(%rsp),%r9 movq 8+0(%rsp),%r10 leaq 0+0(%rsp),%rsi movq 16+0(%rsp),%r11 movq 24+0(%rsp),%r12 leaq 352(%rsp),%rdi call __ecp_nistz256_mul_montq movq 0+0(%rsp),%rax movq 8+0(%rsp),%r14 leaq 0+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 544(%rsp),%rax leaq 544(%rsp),%rbx movq 0+352(%rsp),%r9 movq 8+352(%rsp),%r10 leaq 0+352(%rsp),%rsi movq 16+352(%rsp),%r11 movq 24+352(%rsp),%r12 leaq 352(%rsp),%rdi call __ecp_nistz256_mul_montq movq 0(%rsp),%rax leaq 0(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 128(%rsp),%rdi call __ecp_nistz256_mul_montq movq 160(%rsp),%rax leaq 160(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 192(%rsp),%rdi call __ecp_nistz256_mul_montq xorq %r11,%r11 addq %r12,%r12 leaq 96(%rsp),%rsi adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 movq 0(%rsi),%rax cmovcq %rbp,%r13 movq 8(%rsi),%rbp cmovcq %rcx,%r8 movq 16(%rsi),%rcx cmovcq %r10,%r9 movq 24(%rsi),%r10 call __ecp_nistz256_subq leaq 128(%rsp),%rbx leaq 288(%rsp),%rdi call __ecp_nistz256_sub_fromq movq 192+0(%rsp),%rax movq 192+8(%rsp),%rbp movq 192+16(%rsp),%rcx movq 192+24(%rsp),%r10 leaq 320(%rsp),%rdi call __ecp_nistz256_subq movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 128(%rsp),%rax leaq 128(%rsp),%rbx movq 0+224(%rsp),%r9 movq 8+224(%rsp),%r10 leaq 0+224(%rsp),%rsi movq 16+224(%rsp),%r11 movq 24+224(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montq movq 320(%rsp),%rax leaq 320(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 320(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 256(%rsp),%rbx leaq 320(%rsp),%rdi call __ecp_nistz256_sub_fromq .byte 102,72,15,126,199 movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 352(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 352+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 544(%rsp),%xmm2 pand 544+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 448(%rsp),%xmm2 pand 448+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,64(%rdi) movdqu %xmm3,80(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 288(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 288+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 480(%rsp),%xmm2 pand 480+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 384(%rsp),%xmm2 pand 384+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 320(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 320+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 512(%rsp),%xmm2 pand 512+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 416(%rsp),%xmm2 pand 416+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,32(%rdi) movdqu %xmm3,48(%rdi) .Ladd_doneq: leaq 576+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpoint_addq_epilogue: ret .cfi_endproc .size ecp_nistz256_point_add,.-ecp_nistz256_point_add .globl ecp_nistz256_point_add_affine .hidden ecp_nistz256_point_add_affine .type ecp_nistz256_point_add_affine,@function .align 32 ecp_nistz256_point_add_affine: .cfi_startproc _CET_ENDBR leaq OPENSSL_ia32cap_P(%rip),%rcx movq 8(%rcx),%rcx andl $0x80100,%ecx cmpl $0x80100,%ecx je .Lpoint_add_affinex pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $480+8,%rsp .cfi_adjust_cfa_offset 32*15+8 .Ladd_affineq_body: movdqu 0(%rsi),%xmm0 movq %rdx,%rbx movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm3 movdqu 64(%rsi),%xmm4 movdqu 80(%rsi),%xmm5 movq 64+0(%rsi),%rax movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 movdqa %xmm0,320(%rsp) movdqa %xmm1,320+16(%rsp) movdqa %xmm2,352(%rsp) movdqa %xmm3,352+16(%rsp) movdqa %xmm4,384(%rsp) movdqa %xmm5,384+16(%rsp) por %xmm4,%xmm5 movdqu 0(%rbx),%xmm0 pshufd $0xb1,%xmm5,%xmm3 movdqu 16(%rbx),%xmm1 movdqu 32(%rbx),%xmm2 por %xmm3,%xmm5 movdqu 48(%rbx),%xmm3 movdqa %xmm0,416(%rsp) pshufd $0x1e,%xmm5,%xmm4 movdqa %xmm1,416+16(%rsp) por %xmm0,%xmm1 .byte 102,72,15,110,199 movdqa %xmm2,448(%rsp) movdqa %xmm3,448+16(%rsp) por %xmm2,%xmm3 por %xmm4,%xmm5 pxor %xmm4,%xmm4 por %xmm1,%xmm3 leaq 64-0(%rsi),%rsi leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montq pcmpeqd %xmm4,%xmm5 pshufd $0xb1,%xmm3,%xmm4 movq 0(%rbx),%rax movq %r12,%r9 por %xmm3,%xmm4 pshufd $0,%xmm5,%xmm5 pshufd $0x1e,%xmm4,%xmm3 movq %r13,%r10 por %xmm3,%xmm4 pxor %xmm3,%xmm3 movq %r14,%r11 pcmpeqd %xmm3,%xmm4 pshufd $0,%xmm4,%xmm4 leaq 32-0(%rsp),%rsi movq %r15,%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 320(%rsp),%rbx leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromq movq 384(%rsp),%rax leaq 384(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montq movq 384(%rsp),%rax leaq 384(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 288(%rsp),%rdi call __ecp_nistz256_mul_montq movq 448(%rsp),%rax leaq 448(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq 0+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 352(%rsp),%rbx leaq 96(%rsp),%rdi call __ecp_nistz256_sub_fromq movq 0+64(%rsp),%rax movq 8+64(%rsp),%r14 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r15 movq 24+64(%rsp),%r8 leaq 128(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 0+96(%rsp),%rax movq 8+96(%rsp),%r14 leaq 0+96(%rsp),%rsi movq 16+96(%rsp),%r15 movq 24+96(%rsp),%r8 leaq 192(%rsp),%rdi call __ecp_nistz256_sqr_montq movq 128(%rsp),%rax leaq 128(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 160(%rsp),%rdi call __ecp_nistz256_mul_montq movq 320(%rsp),%rax leaq 320(%rsp),%rbx movq 0+128(%rsp),%r9 movq 8+128(%rsp),%r10 leaq 0+128(%rsp),%rsi movq 16+128(%rsp),%r11 movq 24+128(%rsp),%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montq xorq %r11,%r11 addq %r12,%r12 leaq 192(%rsp),%rsi adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 movq 0(%rsi),%rax cmovcq %rbp,%r13 movq 8(%rsi),%rbp cmovcq %rcx,%r8 movq 16(%rsi),%rcx cmovcq %r10,%r9 movq 24(%rsi),%r10 call __ecp_nistz256_subq leaq 160(%rsp),%rbx leaq 224(%rsp),%rdi call __ecp_nistz256_sub_fromq movq 0+0(%rsp),%rax movq 0+8(%rsp),%rbp movq 0+16(%rsp),%rcx movq 0+24(%rsp),%r10 leaq 64(%rsp),%rdi call __ecp_nistz256_subq movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 352(%rsp),%rax leaq 352(%rsp),%rbx movq 0+160(%rsp),%r9 movq 8+160(%rsp),%r10 leaq 0+160(%rsp),%rsi movq 16+160(%rsp),%r11 movq 24+160(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montq movq 96(%rsp),%rax leaq 96(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq 0+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 64(%rsp),%rdi call __ecp_nistz256_mul_montq leaq 32(%rsp),%rbx leaq 256(%rsp),%rdi call __ecp_nistz256_sub_fromq .byte 102,72,15,126,199 movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 288(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 288+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand .LONE_mont(%rip),%xmm2 pand .LONE_mont+16(%rip),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 384(%rsp),%xmm2 pand 384+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,64(%rdi) movdqu %xmm3,80(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 224(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 224+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 416(%rsp),%xmm2 pand 416+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 320(%rsp),%xmm2 pand 320+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 256(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 256+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 448(%rsp),%xmm2 pand 448+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 352(%rsp),%xmm2 pand 352+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,32(%rdi) movdqu %xmm3,48(%rdi) leaq 480+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Ladd_affineq_epilogue: ret .cfi_endproc .size ecp_nistz256_point_add_affine,.-ecp_nistz256_point_add_affine .type __ecp_nistz256_add_tox,@function .align 32 __ecp_nistz256_add_tox: .cfi_startproc xorq %r11,%r11 adcq 0(%rbx),%r12 adcq 8(%rbx),%r13 movq %r12,%rax adcq 16(%rbx),%r8 adcq 24(%rbx),%r9 movq %r13,%rbp adcq $0,%r11 xorq %r10,%r10 sbbq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 cmovcq %rbp,%r13 movq %r12,0(%rdi) cmovcq %rcx,%r8 movq %r13,8(%rdi) cmovcq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_add_tox,.-__ecp_nistz256_add_tox .type __ecp_nistz256_sub_fromx,@function .align 32 __ecp_nistz256_sub_fromx: .cfi_startproc xorq %r11,%r11 sbbq 0(%rbx),%r12 sbbq 8(%rbx),%r13 movq %r12,%rax sbbq 16(%rbx),%r8 sbbq 24(%rbx),%r9 movq %r13,%rbp sbbq $0,%r11 xorq %r10,%r10 adcq $-1,%r12 movq %r8,%rcx adcq %r14,%r13 adcq $0,%r8 movq %r9,%r10 adcq %r15,%r9 btq $0,%r11 cmovncq %rax,%r12 cmovncq %rbp,%r13 movq %r12,0(%rdi) cmovncq %rcx,%r8 movq %r13,8(%rdi) cmovncq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_sub_fromx,.-__ecp_nistz256_sub_fromx .type __ecp_nistz256_subx,@function .align 32 __ecp_nistz256_subx: .cfi_startproc xorq %r11,%r11 sbbq %r12,%rax sbbq %r13,%rbp movq %rax,%r12 sbbq %r8,%rcx sbbq %r9,%r10 movq %rbp,%r13 sbbq $0,%r11 xorq %r9,%r9 adcq $-1,%rax movq %rcx,%r8 adcq %r14,%rbp adcq $0,%rcx movq %r10,%r9 adcq %r15,%r10 btq $0,%r11 cmovcq %rax,%r12 cmovcq %rbp,%r13 cmovcq %rcx,%r8 cmovcq %r10,%r9 ret .cfi_endproc .size __ecp_nistz256_subx,.-__ecp_nistz256_subx .type __ecp_nistz256_mul_by_2x,@function .align 32 __ecp_nistz256_mul_by_2x: .cfi_startproc xorq %r11,%r11 adcq %r12,%r12 adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 xorq %r10,%r10 sbbq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 cmovcq %rbp,%r13 movq %r12,0(%rdi) cmovcq %rcx,%r8 movq %r13,8(%rdi) cmovcq %r10,%r9 movq %r8,16(%rdi) movq %r9,24(%rdi) ret .cfi_endproc .size __ecp_nistz256_mul_by_2x,.-__ecp_nistz256_mul_by_2x .type ecp_nistz256_point_doublex,@function .align 32 ecp_nistz256_point_doublex: .cfi_startproc .Lpoint_doublex: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $160+8,%rsp .cfi_adjust_cfa_offset 32*5+8 .Lpoint_doublex_body: .Lpoint_double_shortcutx: movdqu 0(%rsi),%xmm0 movq %rsi,%rbx movdqu 16(%rsi),%xmm1 movq 32+0(%rsi),%r12 movq 32+8(%rsi),%r13 movq 32+16(%rsi),%r8 movq 32+24(%rsi),%r9 movq .Lpoly+8(%rip),%r14 movq .Lpoly+24(%rip),%r15 movdqa %xmm0,96(%rsp) movdqa %xmm1,96+16(%rsp) leaq 32(%rdi),%r10 leaq 64(%rdi),%r11 .byte 102,72,15,110,199 .byte 102,73,15,110,202 .byte 102,73,15,110,211 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_by_2x movq 64+0(%rsi),%rdx movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 leaq 64-128(%rsi),%rsi leaq 64(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 0+0(%rsp),%rdx movq 8+0(%rsp),%r14 leaq -128+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 leaq 0(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 32(%rbx),%rdx movq 64+0(%rbx),%r9 movq 64+8(%rbx),%r10 movq 64+16(%rbx),%r11 movq 64+24(%rbx),%r12 leaq 64-128(%rbx),%rsi leaq 32(%rbx),%rbx .byte 102,72,15,126,215 call __ecp_nistz256_mul_montx call __ecp_nistz256_mul_by_2x movq 96+0(%rsp),%r12 movq 96+8(%rsp),%r13 leaq 64(%rsp),%rbx movq 96+16(%rsp),%r8 movq 96+24(%rsp),%r9 leaq 32(%rsp),%rdi call __ecp_nistz256_add_tox movq 96+0(%rsp),%r12 movq 96+8(%rsp),%r13 leaq 64(%rsp),%rbx movq 96+16(%rsp),%r8 movq 96+24(%rsp),%r9 leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromx movq 0+0(%rsp),%rdx movq 8+0(%rsp),%r14 leaq -128+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 .byte 102,72,15,126,207 call __ecp_nistz256_sqr_montx xorq %r9,%r9 movq %r12,%rax addq $-1,%r12 movq %r13,%r10 adcq %rsi,%r13 movq %r14,%rcx adcq $0,%r14 movq %r15,%r8 adcq %rbp,%r15 adcq $0,%r9 xorq %rsi,%rsi testq $1,%rax cmovzq %rax,%r12 cmovzq %r10,%r13 cmovzq %rcx,%r14 cmovzq %r8,%r15 cmovzq %rsi,%r9 movq %r13,%rax shrq $1,%r12 shlq $63,%rax movq %r14,%r10 shrq $1,%r13 orq %rax,%r12 shlq $63,%r10 movq %r15,%rcx shrq $1,%r14 orq %r10,%r13 shlq $63,%rcx movq %r12,0(%rdi) shrq $1,%r15 movq %r13,8(%rdi) shlq $63,%r9 orq %rcx,%r14 orq %r9,%r15 movq %r14,16(%rdi) movq %r15,24(%rdi) movq 64(%rsp),%rdx leaq 64(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 128(%rsp),%rdi call __ecp_nistz256_mul_by_2x leaq 32(%rsp),%rbx leaq 32(%rsp),%rdi call __ecp_nistz256_add_tox movq 96(%rsp),%rdx leaq 96(%rsp),%rbx movq 0+0(%rsp),%r9 movq 8+0(%rsp),%r10 leaq -128+0(%rsp),%rsi movq 16+0(%rsp),%r11 movq 24+0(%rsp),%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 128(%rsp),%rdi call __ecp_nistz256_mul_by_2x movq 0+32(%rsp),%rdx movq 8+32(%rsp),%r14 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r15 movq 24+32(%rsp),%r8 .byte 102,72,15,126,199 call __ecp_nistz256_sqr_montx leaq 128(%rsp),%rbx movq %r14,%r8 movq %r15,%r9 movq %rsi,%r14 movq %rbp,%r15 call __ecp_nistz256_sub_fromx movq 0+0(%rsp),%rax movq 0+8(%rsp),%rbp movq 0+16(%rsp),%rcx movq 0+24(%rsp),%r10 leaq 0(%rsp),%rdi call __ecp_nistz256_subx movq 32(%rsp),%rdx leaq 32(%rsp),%rbx movq %r12,%r14 xorl %ecx,%ecx movq %r12,0+0(%rsp) movq %r13,%r10 movq %r13,0+8(%rsp) cmovzq %r8,%r11 movq %r8,0+16(%rsp) leaq 0-128(%rsp),%rsi cmovzq %r9,%r12 movq %r9,0+24(%rsp) movq %r14,%r9 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montx .byte 102,72,15,126,203 .byte 102,72,15,126,207 call __ecp_nistz256_sub_fromx leaq 160+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpoint_doublex_epilogue: ret .cfi_endproc .size ecp_nistz256_point_doublex,.-ecp_nistz256_point_doublex .type ecp_nistz256_point_addx,@function .align 32 ecp_nistz256_point_addx: .cfi_startproc .Lpoint_addx: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $576+8,%rsp .cfi_adjust_cfa_offset 32*18+8 .Lpoint_addx_body: movdqu 0(%rsi),%xmm0 movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm3 movdqu 64(%rsi),%xmm4 movdqu 80(%rsi),%xmm5 movq %rsi,%rbx movq %rdx,%rsi movdqa %xmm0,384(%rsp) movdqa %xmm1,384+16(%rsp) movdqa %xmm2,416(%rsp) movdqa %xmm3,416+16(%rsp) movdqa %xmm4,448(%rsp) movdqa %xmm5,448+16(%rsp) por %xmm4,%xmm5 movdqu 0(%rsi),%xmm0 pshufd $0xb1,%xmm5,%xmm3 movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 por %xmm3,%xmm5 movdqu 48(%rsi),%xmm3 movq 64+0(%rsi),%rdx movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 movdqa %xmm0,480(%rsp) pshufd $0x1e,%xmm5,%xmm4 movdqa %xmm1,480+16(%rsp) movdqu 64(%rsi),%xmm0 movdqu 80(%rsi),%xmm1 movdqa %xmm2,512(%rsp) movdqa %xmm3,512+16(%rsp) por %xmm4,%xmm5 pxor %xmm4,%xmm4 por %xmm0,%xmm1 .byte 102,72,15,110,199 leaq 64-128(%rsi),%rsi movq %rdx,544+0(%rsp) movq %r14,544+8(%rsp) movq %r15,544+16(%rsp) movq %r8,544+24(%rsp) leaq 96(%rsp),%rdi call __ecp_nistz256_sqr_montx pcmpeqd %xmm4,%xmm5 pshufd $0xb1,%xmm1,%xmm4 por %xmm1,%xmm4 pshufd $0,%xmm5,%xmm5 pshufd $0x1e,%xmm4,%xmm3 por %xmm3,%xmm4 pxor %xmm3,%xmm3 pcmpeqd %xmm3,%xmm4 pshufd $0,%xmm4,%xmm4 movq 64+0(%rbx),%rdx movq 64+8(%rbx),%r14 movq 64+16(%rbx),%r15 movq 64+24(%rbx),%r8 .byte 102,72,15,110,203 leaq 64-128(%rbx),%rsi leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 544(%rsp),%rdx leaq 544(%rsp),%rbx movq 0+96(%rsp),%r9 movq 8+96(%rsp),%r10 leaq -128+96(%rsp),%rsi movq 16+96(%rsp),%r11 movq 24+96(%rsp),%r12 leaq 224(%rsp),%rdi call __ecp_nistz256_mul_montx movq 448(%rsp),%rdx leaq 448(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montx movq 416(%rsp),%rdx leaq 416(%rsp),%rbx movq 0+224(%rsp),%r9 movq 8+224(%rsp),%r10 leaq -128+224(%rsp),%rsi movq 16+224(%rsp),%r11 movq 24+224(%rsp),%r12 leaq 224(%rsp),%rdi call __ecp_nistz256_mul_montx movq 512(%rsp),%rdx leaq 512(%rsp),%rbx movq 0+256(%rsp),%r9 movq 8+256(%rsp),%r10 leaq -128+256(%rsp),%rsi movq 16+256(%rsp),%r11 movq 24+256(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 224(%rsp),%rbx leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromx orq %r13,%r12 movdqa %xmm4,%xmm2 orq %r8,%r12 orq %r9,%r12 por %xmm5,%xmm2 .byte 102,73,15,110,220 movq 384(%rsp),%rdx leaq 384(%rsp),%rbx movq 0+96(%rsp),%r9 movq 8+96(%rsp),%r10 leaq -128+96(%rsp),%rsi movq 16+96(%rsp),%r11 movq 24+96(%rsp),%r12 leaq 160(%rsp),%rdi call __ecp_nistz256_mul_montx movq 480(%rsp),%rdx leaq 480(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 192(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 160(%rsp),%rbx leaq 0(%rsp),%rdi call __ecp_nistz256_sub_fromx orq %r13,%r12 orq %r8,%r12 orq %r9,%r12 .byte 102,73,15,126,208 .byte 102,73,15,126,217 orq %r8,%r12 .byte 0x3e jnz .Ladd_proceedx testq %r9,%r9 jz .Ladd_doublex .byte 102,72,15,126,199 pxor %xmm0,%xmm0 movdqu %xmm0,0(%rdi) movdqu %xmm0,16(%rdi) movdqu %xmm0,32(%rdi) movdqu %xmm0,48(%rdi) movdqu %xmm0,64(%rdi) movdqu %xmm0,80(%rdi) jmp .Ladd_donex .align 32 .Ladd_doublex: .byte 102,72,15,126,206 .byte 102,72,15,126,199 addq $416,%rsp .cfi_adjust_cfa_offset -416 jmp .Lpoint_double_shortcutx .cfi_adjust_cfa_offset 416 .align 32 .Ladd_proceedx: movq 0+64(%rsp),%rdx movq 8+64(%rsp),%r14 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r15 movq 24+64(%rsp),%r8 leaq 96(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 448(%rsp),%rdx leaq 448(%rsp),%rbx movq 0+0(%rsp),%r9 movq 8+0(%rsp),%r10 leaq -128+0(%rsp),%rsi movq 16+0(%rsp),%r11 movq 24+0(%rsp),%r12 leaq 352(%rsp),%rdi call __ecp_nistz256_mul_montx movq 0+0(%rsp),%rdx movq 8+0(%rsp),%r14 leaq -128+0(%rsp),%rsi movq 16+0(%rsp),%r15 movq 24+0(%rsp),%r8 leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 544(%rsp),%rdx leaq 544(%rsp),%rbx movq 0+352(%rsp),%r9 movq 8+352(%rsp),%r10 leaq -128+352(%rsp),%rsi movq 16+352(%rsp),%r11 movq 24+352(%rsp),%r12 leaq 352(%rsp),%rdi call __ecp_nistz256_mul_montx movq 0(%rsp),%rdx leaq 0(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 128(%rsp),%rdi call __ecp_nistz256_mul_montx movq 160(%rsp),%rdx leaq 160(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 192(%rsp),%rdi call __ecp_nistz256_mul_montx xorq %r11,%r11 addq %r12,%r12 leaq 96(%rsp),%rsi adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 movq 0(%rsi),%rax cmovcq %rbp,%r13 movq 8(%rsi),%rbp cmovcq %rcx,%r8 movq 16(%rsi),%rcx cmovcq %r10,%r9 movq 24(%rsi),%r10 call __ecp_nistz256_subx leaq 128(%rsp),%rbx leaq 288(%rsp),%rdi call __ecp_nistz256_sub_fromx movq 192+0(%rsp),%rax movq 192+8(%rsp),%rbp movq 192+16(%rsp),%rcx movq 192+24(%rsp),%r10 leaq 320(%rsp),%rdi call __ecp_nistz256_subx movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 128(%rsp),%rdx leaq 128(%rsp),%rbx movq 0+224(%rsp),%r9 movq 8+224(%rsp),%r10 leaq -128+224(%rsp),%rsi movq 16+224(%rsp),%r11 movq 24+224(%rsp),%r12 leaq 256(%rsp),%rdi call __ecp_nistz256_mul_montx movq 320(%rsp),%rdx leaq 320(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 320(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 256(%rsp),%rbx leaq 320(%rsp),%rdi call __ecp_nistz256_sub_fromx .byte 102,72,15,126,199 movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 352(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 352+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 544(%rsp),%xmm2 pand 544+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 448(%rsp),%xmm2 pand 448+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,64(%rdi) movdqu %xmm3,80(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 288(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 288+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 480(%rsp),%xmm2 pand 480+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 384(%rsp),%xmm2 pand 384+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 320(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 320+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 512(%rsp),%xmm2 pand 512+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 416(%rsp),%xmm2 pand 416+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,32(%rdi) movdqu %xmm3,48(%rdi) .Ladd_donex: leaq 576+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpoint_addx_epilogue: ret .cfi_endproc .size ecp_nistz256_point_addx,.-ecp_nistz256_point_addx .type ecp_nistz256_point_add_affinex,@function .align 32 ecp_nistz256_point_add_affinex: .cfi_startproc .Lpoint_add_affinex: pushq %rbp .cfi_adjust_cfa_offset 8 .cfi_offset %rbp,-16 pushq %rbx .cfi_adjust_cfa_offset 8 .cfi_offset %rbx,-24 pushq %r12 .cfi_adjust_cfa_offset 8 .cfi_offset %r12,-32 pushq %r13 .cfi_adjust_cfa_offset 8 .cfi_offset %r13,-40 pushq %r14 .cfi_adjust_cfa_offset 8 .cfi_offset %r14,-48 pushq %r15 .cfi_adjust_cfa_offset 8 .cfi_offset %r15,-56 subq $480+8,%rsp .cfi_adjust_cfa_offset 32*15+8 .Ladd_affinex_body: movdqu 0(%rsi),%xmm0 movq %rdx,%rbx movdqu 16(%rsi),%xmm1 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm3 movdqu 64(%rsi),%xmm4 movdqu 80(%rsi),%xmm5 movq 64+0(%rsi),%rdx movq 64+8(%rsi),%r14 movq 64+16(%rsi),%r15 movq 64+24(%rsi),%r8 movdqa %xmm0,320(%rsp) movdqa %xmm1,320+16(%rsp) movdqa %xmm2,352(%rsp) movdqa %xmm3,352+16(%rsp) movdqa %xmm4,384(%rsp) movdqa %xmm5,384+16(%rsp) por %xmm4,%xmm5 movdqu 0(%rbx),%xmm0 pshufd $0xb1,%xmm5,%xmm3 movdqu 16(%rbx),%xmm1 movdqu 32(%rbx),%xmm2 por %xmm3,%xmm5 movdqu 48(%rbx),%xmm3 movdqa %xmm0,416(%rsp) pshufd $0x1e,%xmm5,%xmm4 movdqa %xmm1,416+16(%rsp) por %xmm0,%xmm1 .byte 102,72,15,110,199 movdqa %xmm2,448(%rsp) movdqa %xmm3,448+16(%rsp) por %xmm2,%xmm3 por %xmm4,%xmm5 pxor %xmm4,%xmm4 por %xmm1,%xmm3 leaq 64-128(%rsi),%rsi leaq 32(%rsp),%rdi call __ecp_nistz256_sqr_montx pcmpeqd %xmm4,%xmm5 pshufd $0xb1,%xmm3,%xmm4 movq 0(%rbx),%rdx movq %r12,%r9 por %xmm3,%xmm4 pshufd $0,%xmm5,%xmm5 pshufd $0x1e,%xmm4,%xmm3 movq %r13,%r10 por %xmm3,%xmm4 pxor %xmm3,%xmm3 movq %r14,%r11 pcmpeqd %xmm3,%xmm4 pshufd $0,%xmm4,%xmm4 leaq 32-128(%rsp),%rsi movq %r15,%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 320(%rsp),%rbx leaq 64(%rsp),%rdi call __ecp_nistz256_sub_fromx movq 384(%rsp),%rdx leaq 384(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montx movq 384(%rsp),%rdx leaq 384(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 288(%rsp),%rdi call __ecp_nistz256_mul_montx movq 448(%rsp),%rdx leaq 448(%rsp),%rbx movq 0+32(%rsp),%r9 movq 8+32(%rsp),%r10 leaq -128+32(%rsp),%rsi movq 16+32(%rsp),%r11 movq 24+32(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 352(%rsp),%rbx leaq 96(%rsp),%rdi call __ecp_nistz256_sub_fromx movq 0+64(%rsp),%rdx movq 8+64(%rsp),%r14 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r15 movq 24+64(%rsp),%r8 leaq 128(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 0+96(%rsp),%rdx movq 8+96(%rsp),%r14 leaq -128+96(%rsp),%rsi movq 16+96(%rsp),%r15 movq 24+96(%rsp),%r8 leaq 192(%rsp),%rdi call __ecp_nistz256_sqr_montx movq 128(%rsp),%rdx leaq 128(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 160(%rsp),%rdi call __ecp_nistz256_mul_montx movq 320(%rsp),%rdx leaq 320(%rsp),%rbx movq 0+128(%rsp),%r9 movq 8+128(%rsp),%r10 leaq -128+128(%rsp),%rsi movq 16+128(%rsp),%r11 movq 24+128(%rsp),%r12 leaq 0(%rsp),%rdi call __ecp_nistz256_mul_montx xorq %r11,%r11 addq %r12,%r12 leaq 192(%rsp),%rsi adcq %r13,%r13 movq %r12,%rax adcq %r8,%r8 adcq %r9,%r9 movq %r13,%rbp adcq $0,%r11 subq $-1,%r12 movq %r8,%rcx sbbq %r14,%r13 sbbq $0,%r8 movq %r9,%r10 sbbq %r15,%r9 sbbq $0,%r11 cmovcq %rax,%r12 movq 0(%rsi),%rax cmovcq %rbp,%r13 movq 8(%rsi),%rbp cmovcq %rcx,%r8 movq 16(%rsi),%rcx cmovcq %r10,%r9 movq 24(%rsi),%r10 call __ecp_nistz256_subx leaq 160(%rsp),%rbx leaq 224(%rsp),%rdi call __ecp_nistz256_sub_fromx movq 0+0(%rsp),%rax movq 0+8(%rsp),%rbp movq 0+16(%rsp),%rcx movq 0+24(%rsp),%r10 leaq 64(%rsp),%rdi call __ecp_nistz256_subx movq %r12,0(%rdi) movq %r13,8(%rdi) movq %r8,16(%rdi) movq %r9,24(%rdi) movq 352(%rsp),%rdx leaq 352(%rsp),%rbx movq 0+160(%rsp),%r9 movq 8+160(%rsp),%r10 leaq -128+160(%rsp),%rsi movq 16+160(%rsp),%r11 movq 24+160(%rsp),%r12 leaq 32(%rsp),%rdi call __ecp_nistz256_mul_montx movq 96(%rsp),%rdx leaq 96(%rsp),%rbx movq 0+64(%rsp),%r9 movq 8+64(%rsp),%r10 leaq -128+64(%rsp),%rsi movq 16+64(%rsp),%r11 movq 24+64(%rsp),%r12 leaq 64(%rsp),%rdi call __ecp_nistz256_mul_montx leaq 32(%rsp),%rbx leaq 256(%rsp),%rdi call __ecp_nistz256_sub_fromx .byte 102,72,15,126,199 movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 288(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 288+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand .LONE_mont(%rip),%xmm2 pand .LONE_mont+16(%rip),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 384(%rsp),%xmm2 pand 384+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,64(%rdi) movdqu %xmm3,80(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 224(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 224+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 416(%rsp),%xmm2 pand 416+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 320(%rsp),%xmm2 pand 320+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,0(%rdi) movdqu %xmm3,16(%rdi) movdqa %xmm5,%xmm0 movdqa %xmm5,%xmm1 pandn 256(%rsp),%xmm0 movdqa %xmm5,%xmm2 pandn 256+16(%rsp),%xmm1 movdqa %xmm5,%xmm3 pand 448(%rsp),%xmm2 pand 448+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqa %xmm4,%xmm0 movdqa %xmm4,%xmm1 pandn %xmm2,%xmm0 movdqa %xmm4,%xmm2 pandn %xmm3,%xmm1 movdqa %xmm4,%xmm3 pand 352(%rsp),%xmm2 pand 352+16(%rsp),%xmm3 por %xmm0,%xmm2 por %xmm1,%xmm3 movdqu %xmm2,32(%rdi) movdqu %xmm3,48(%rdi) leaq 480+56(%rsp),%rsi .cfi_def_cfa %rsi,8 movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbx .cfi_restore %rbx movq -8(%rsi),%rbp .cfi_restore %rbp leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Ladd_affinex_epilogue: ret .cfi_endproc .size ecp_nistz256_point_add_affinex,.-ecp_nistz256_point_add_affinex #endif

j4yc3-mw/Viren

190,086

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/chacha20_poly1305_x86_64-macosx.S

// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__APPLE__) .text chacha20_poly1305_constants: .section __DATA,__const .p2align 6 L$chacha20_consts: .byte 'e','x','p','a','n','d',' ','3','2','-','b','y','t','e',' ','k' .byte 'e','x','p','a','n','d',' ','3','2','-','b','y','t','e',' ','k' L$rol8: .byte 3,0,1,2, 7,4,5,6, 11,8,9,10, 15,12,13,14 .byte 3,0,1,2, 7,4,5,6, 11,8,9,10, 15,12,13,14 L$rol16: .byte 2,3,0,1, 6,7,4,5, 10,11,8,9, 14,15,12,13 .byte 2,3,0,1, 6,7,4,5, 10,11,8,9, 14,15,12,13 L$avx2_init: .long 0,0,0,0 L$sse_inc: .long 1,0,0,0 L$avx2_inc: .long 2,0,0,0,2,0,0,0 L$clamp: .quad 0x0FFFFFFC0FFFFFFF, 0x0FFFFFFC0FFFFFFC .quad 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF .p2align 4 L$and_masks: .byte 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff .text .p2align 6 poly_hash_ad_internal: xorq %r10,%r10 xorq %r11,%r11 xorq %r12,%r12 cmpq $13,%r8 jne L$hash_ad_loop L$poly_fast_tls_ad: movq (%rcx),%r10 movq 5(%rcx),%r11 shrq $24,%r11 movq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 ret L$hash_ad_loop: cmpq $16,%r8 jb L$hash_ad_tail addq 0+0(%rcx),%r10 adcq 8+0(%rcx),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rcx),%rcx subq $16,%r8 jmp L$hash_ad_loop L$hash_ad_tail: cmpq $0,%r8 je L$hash_ad_done xorq %r13,%r13 xorq %r14,%r14 xorq %r15,%r15 addq %r8,%rcx L$hash_ad_tail_loop: shldq $8,%r13,%r14 shlq $8,%r13 movzbq -1(%rcx),%r15 xorq %r15,%r13 decq %rcx decq %r8 jne L$hash_ad_tail_loop addq %r13,%r10 adcq %r14,%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$hash_ad_done: ret .globl _chacha20_poly1305_open .private_extern _chacha20_poly1305_open .p2align 6 _chacha20_poly1305_open: _CET_ENDBR pushq %rbp pushq %rbx pushq %r12 pushq %r13 pushq %r14 pushq %r15 pushq %r9 subq $288 + 0 + 32,%rsp leaq 32(%rsp),%rbp andq $-32,%rbp movq %rdx,%rbx movq %r8,0+0+32(%rbp) movq %rbx,8+0+32(%rbp) movl _OPENSSL_ia32cap_P+8(%rip),%eax andl $288,%eax xorl $288,%eax jz chacha20_poly1305_open_avx2 cmpq $128,%rbx jbe L$open_sse_128 movdqa L$chacha20_consts(%rip),%xmm0 movdqu 0(%r9),%xmm4 movdqu 16(%r9),%xmm8 movdqu 32(%r9),%xmm12 movdqa %xmm12,%xmm7 movdqa %xmm4,0+48(%rbp) movdqa %xmm8,0+64(%rbp) movdqa %xmm12,0+96(%rbp) movq $10,%r10 L$open_sse_init_rounds: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 decq %r10 jne L$open_sse_init_rounds paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 pand L$clamp(%rip),%xmm0 movdqa %xmm0,0+0(%rbp) movdqa %xmm4,0+16(%rbp) movq %r8,%r8 call poly_hash_ad_internal L$open_sse_main_loop: cmpq $256,%rbx jb L$open_sse_tail movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa %xmm0,%xmm2 movdqa %xmm4,%xmm6 movdqa %xmm8,%xmm10 movdqa %xmm0,%xmm3 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm11 movdqa 0+96(%rbp),%xmm15 paddd L$sse_inc(%rip),%xmm15 movdqa %xmm15,%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm14,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) movdqa %xmm15,0+144(%rbp) movq $4,%rcx movq %rsi,%r8 L$open_sse_main_loop_rounds: movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 leaq 16(%r8),%r8 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 .byte 102,15,58,15,255,4 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,12 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 .byte 102,15,58,15,255,12 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,4 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 decq %rcx jge L$open_sse_main_loop_rounds addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%r8),%r8 cmpq $-6,%rcx jg L$open_sse_main_loop_rounds paddd L$chacha20_consts(%rip),%xmm3 paddd 0+48(%rbp),%xmm7 paddd 0+64(%rbp),%xmm11 paddd 0+144(%rbp),%xmm15 paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqa %xmm12,0+80(%rbp) movdqu 0 + 0(%rsi),%xmm12 pxor %xmm3,%xmm12 movdqu %xmm12,0 + 0(%rdi) movdqu 16 + 0(%rsi),%xmm12 pxor %xmm7,%xmm12 movdqu %xmm12,16 + 0(%rdi) movdqu 32 + 0(%rsi),%xmm12 pxor %xmm11,%xmm12 movdqu %xmm12,32 + 0(%rdi) movdqu 48 + 0(%rsi),%xmm12 pxor %xmm15,%xmm12 movdqu %xmm12,48 + 0(%rdi) movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 64(%rdi) movdqu %xmm6,16 + 64(%rdi) movdqu %xmm10,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) movdqu 0 + 128(%rsi),%xmm3 movdqu 16 + 128(%rsi),%xmm7 movdqu 32 + 128(%rsi),%xmm11 movdqu 48 + 128(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 128(%rdi) movdqu %xmm5,16 + 128(%rdi) movdqu %xmm9,32 + 128(%rdi) movdqu %xmm15,48 + 128(%rdi) movdqu 0 + 192(%rsi),%xmm3 movdqu 16 + 192(%rsi),%xmm7 movdqu 32 + 192(%rsi),%xmm11 movdqu 48 + 192(%rsi),%xmm15 pxor %xmm3,%xmm0 pxor %xmm7,%xmm4 pxor %xmm11,%xmm8 pxor 0+80(%rbp),%xmm15 movdqu %xmm0,0 + 192(%rdi) movdqu %xmm4,16 + 192(%rdi) movdqu %xmm8,32 + 192(%rdi) movdqu %xmm15,48 + 192(%rdi) leaq 256(%rsi),%rsi leaq 256(%rdi),%rdi subq $256,%rbx jmp L$open_sse_main_loop L$open_sse_tail: testq %rbx,%rbx jz L$open_sse_finalize cmpq $192,%rbx ja L$open_sse_tail_256 cmpq $128,%rbx ja L$open_sse_tail_192 cmpq $64,%rbx ja L$open_sse_tail_128 movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa 0+96(%rbp),%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) xorq %r8,%r8 movq %rbx,%rcx cmpq $16,%rcx jb L$open_sse_tail_64_rounds L$open_sse_tail_64_rounds_and_x1hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 subq $16,%rcx L$open_sse_tail_64_rounds: addq $16,%r8 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 cmpq $16,%rcx jae L$open_sse_tail_64_rounds_and_x1hash cmpq $160,%r8 jne L$open_sse_tail_64_rounds paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 jmp L$open_sse_tail_64_dec_loop L$open_sse_tail_128: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa 0+96(%rbp),%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movq %rbx,%rcx andq $-16,%rcx xorq %r8,%r8 L$open_sse_tail_128_rounds_and_x1hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$open_sse_tail_128_rounds: addq $16,%r8 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 cmpq %rcx,%r8 jb L$open_sse_tail_128_rounds_and_x1hash cmpq $160,%r8 jne L$open_sse_tail_128_rounds paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqu 0 + 0(%rsi),%xmm3 movdqu 16 + 0(%rsi),%xmm7 movdqu 32 + 0(%rsi),%xmm11 movdqu 48 + 0(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 0(%rdi) movdqu %xmm5,16 + 0(%rdi) movdqu %xmm9,32 + 0(%rdi) movdqu %xmm15,48 + 0(%rdi) subq $64,%rbx leaq 64(%rsi),%rsi leaq 64(%rdi),%rdi jmp L$open_sse_tail_64_dec_loop L$open_sse_tail_192: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa %xmm0,%xmm2 movdqa %xmm4,%xmm6 movdqa %xmm8,%xmm10 movdqa 0+96(%rbp),%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm14,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) movq %rbx,%rcx movq $160,%r8 cmpq $160,%rcx cmovgq %r8,%rcx andq $-16,%rcx xorq %r8,%r8 L$open_sse_tail_192_rounds_and_x1hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$open_sse_tail_192_rounds: addq $16,%r8 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 cmpq %rcx,%r8 jb L$open_sse_tail_192_rounds_and_x1hash cmpq $160,%r8 jne L$open_sse_tail_192_rounds cmpq $176,%rbx jb L$open_sse_tail_192_finish addq 0+160(%rsi),%r10 adcq 8+160(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 cmpq $192,%rbx jb L$open_sse_tail_192_finish addq 0+176(%rsi),%r10 adcq 8+176(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$open_sse_tail_192_finish: paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqu 0 + 0(%rsi),%xmm3 movdqu 16 + 0(%rsi),%xmm7 movdqu 32 + 0(%rsi),%xmm11 movdqu 48 + 0(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 0(%rdi) movdqu %xmm6,16 + 0(%rdi) movdqu %xmm10,32 + 0(%rdi) movdqu %xmm15,48 + 0(%rdi) movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 64(%rdi) movdqu %xmm5,16 + 64(%rdi) movdqu %xmm9,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) subq $128,%rbx leaq 128(%rsi),%rsi leaq 128(%rdi),%rdi jmp L$open_sse_tail_64_dec_loop L$open_sse_tail_256: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa %xmm0,%xmm2 movdqa %xmm4,%xmm6 movdqa %xmm8,%xmm10 movdqa %xmm0,%xmm3 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm11 movdqa 0+96(%rbp),%xmm15 paddd L$sse_inc(%rip),%xmm15 movdqa %xmm15,%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm14,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) movdqa %xmm15,0+144(%rbp) xorq %r8,%r8 L$open_sse_tail_256_rounds_and_x1hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movdqa %xmm11,0+80(%rbp) paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm11 pslld $12,%xmm11 psrld $20,%xmm4 pxor %xmm11,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm11 pslld $7,%xmm11 psrld $25,%xmm4 pxor %xmm11,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm11 pslld $12,%xmm11 psrld $20,%xmm5 pxor %xmm11,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm11 pslld $7,%xmm11 psrld $25,%xmm5 pxor %xmm11,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm11 pslld $12,%xmm11 psrld $20,%xmm6 pxor %xmm11,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm11 pslld $7,%xmm11 psrld $25,%xmm6 pxor %xmm11,%xmm6 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 movdqa 0+80(%rbp),%xmm11 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movdqa %xmm9,0+80(%rbp) paddd %xmm7,%xmm3 pxor %xmm3,%xmm15 pshufb L$rol16(%rip),%xmm15 paddd %xmm15,%xmm11 pxor %xmm11,%xmm7 movdqa %xmm7,%xmm9 pslld $12,%xmm9 psrld $20,%xmm7 pxor %xmm9,%xmm7 paddd %xmm7,%xmm3 pxor %xmm3,%xmm15 pshufb L$rol8(%rip),%xmm15 paddd %xmm15,%xmm11 pxor %xmm11,%xmm7 movdqa %xmm7,%xmm9 pslld $7,%xmm9 psrld $25,%xmm7 pxor %xmm9,%xmm7 .byte 102,15,58,15,255,4 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,12 movdqa 0+80(%rbp),%xmm9 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx movdqa %xmm11,0+80(%rbp) paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm11 pslld $12,%xmm11 psrld $20,%xmm4 pxor %xmm11,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm11 pslld $7,%xmm11 psrld $25,%xmm4 pxor %xmm11,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm11 pslld $12,%xmm11 psrld $20,%xmm5 pxor %xmm11,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm11 pslld $7,%xmm11 psrld $25,%xmm5 pxor %xmm11,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm11 pslld $12,%xmm11 psrld $20,%xmm6 pxor %xmm11,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm11 pslld $7,%xmm11 psrld $25,%xmm6 pxor %xmm11,%xmm6 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 movdqa 0+80(%rbp),%xmm11 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 movdqa %xmm9,0+80(%rbp) paddd %xmm7,%xmm3 pxor %xmm3,%xmm15 pshufb L$rol16(%rip),%xmm15 paddd %xmm15,%xmm11 pxor %xmm11,%xmm7 movdqa %xmm7,%xmm9 pslld $12,%xmm9 psrld $20,%xmm7 pxor %xmm9,%xmm7 paddd %xmm7,%xmm3 pxor %xmm3,%xmm15 pshufb L$rol8(%rip),%xmm15 paddd %xmm15,%xmm11 pxor %xmm11,%xmm7 movdqa %xmm7,%xmm9 pslld $7,%xmm9 psrld $25,%xmm7 pxor %xmm9,%xmm7 .byte 102,15,58,15,255,12 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,4 movdqa 0+80(%rbp),%xmm9 addq $16,%r8 cmpq $160,%r8 jb L$open_sse_tail_256_rounds_and_x1hash movq %rbx,%rcx andq $-16,%rcx L$open_sse_tail_256_hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq $16,%r8 cmpq %rcx,%r8 jb L$open_sse_tail_256_hash paddd L$chacha20_consts(%rip),%xmm3 paddd 0+48(%rbp),%xmm7 paddd 0+64(%rbp),%xmm11 paddd 0+144(%rbp),%xmm15 paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqa %xmm12,0+80(%rbp) movdqu 0 + 0(%rsi),%xmm12 pxor %xmm3,%xmm12 movdqu %xmm12,0 + 0(%rdi) movdqu 16 + 0(%rsi),%xmm12 pxor %xmm7,%xmm12 movdqu %xmm12,16 + 0(%rdi) movdqu 32 + 0(%rsi),%xmm12 pxor %xmm11,%xmm12 movdqu %xmm12,32 + 0(%rdi) movdqu 48 + 0(%rsi),%xmm12 pxor %xmm15,%xmm12 movdqu %xmm12,48 + 0(%rdi) movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 64(%rdi) movdqu %xmm6,16 + 64(%rdi) movdqu %xmm10,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) movdqu 0 + 128(%rsi),%xmm3 movdqu 16 + 128(%rsi),%xmm7 movdqu 32 + 128(%rsi),%xmm11 movdqu 48 + 128(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 128(%rdi) movdqu %xmm5,16 + 128(%rdi) movdqu %xmm9,32 + 128(%rdi) movdqu %xmm15,48 + 128(%rdi) movdqa 0+80(%rbp),%xmm12 subq $192,%rbx leaq 192(%rsi),%rsi leaq 192(%rdi),%rdi L$open_sse_tail_64_dec_loop: cmpq $16,%rbx jb L$open_sse_tail_16_init subq $16,%rbx movdqu (%rsi),%xmm3 pxor %xmm3,%xmm0 movdqu %xmm0,(%rdi) leaq 16(%rsi),%rsi leaq 16(%rdi),%rdi movdqa %xmm4,%xmm0 movdqa %xmm8,%xmm4 movdqa %xmm12,%xmm8 jmp L$open_sse_tail_64_dec_loop L$open_sse_tail_16_init: movdqa %xmm0,%xmm1 L$open_sse_tail_16: testq %rbx,%rbx jz L$open_sse_finalize pxor %xmm3,%xmm3 leaq -1(%rsi,%rbx,1),%rsi movq %rbx,%r8 L$open_sse_tail_16_compose: pslldq $1,%xmm3 pinsrb $0,(%rsi),%xmm3 subq $1,%rsi subq $1,%r8 jnz L$open_sse_tail_16_compose .byte 102,73,15,126,221 pextrq $1,%xmm3,%r14 pxor %xmm1,%xmm3 L$open_sse_tail_16_extract: pextrb $0,%xmm3,(%rdi) psrldq $1,%xmm3 addq $1,%rdi subq $1,%rbx jne L$open_sse_tail_16_extract addq %r13,%r10 adcq %r14,%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$open_sse_finalize: addq 0+0+32(%rbp),%r10 adcq 8+0+32(%rbp),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 movq %r10,%r13 movq %r11,%r14 movq %r12,%r15 subq $-5,%r10 sbbq $-1,%r11 sbbq $3,%r12 cmovcq %r13,%r10 cmovcq %r14,%r11 cmovcq %r15,%r12 addq 0+0+16(%rbp),%r10 adcq 8+0+16(%rbp),%r11 addq $288 + 0 + 32,%rsp popq %r9 movq %r10,(%r9) movq %r11,8(%r9) popq %r15 popq %r14 popq %r13 popq %r12 popq %rbx popq %rbp ret L$open_sse_128: movdqu L$chacha20_consts(%rip),%xmm0 movdqa %xmm0,%xmm1 movdqa %xmm0,%xmm2 movdqu 0(%r9),%xmm4 movdqa %xmm4,%xmm5 movdqa %xmm4,%xmm6 movdqu 16(%r9),%xmm8 movdqa %xmm8,%xmm9 movdqa %xmm8,%xmm10 movdqu 32(%r9),%xmm12 movdqa %xmm12,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm11 movdqa %xmm13,%xmm15 movq $10,%r10 L$open_sse_128_rounds: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 decq %r10 jnz L$open_sse_128_rounds paddd L$chacha20_consts(%rip),%xmm0 paddd L$chacha20_consts(%rip),%xmm1 paddd L$chacha20_consts(%rip),%xmm2 paddd %xmm7,%xmm4 paddd %xmm7,%xmm5 paddd %xmm7,%xmm6 paddd %xmm11,%xmm9 paddd %xmm11,%xmm10 paddd %xmm15,%xmm13 paddd L$sse_inc(%rip),%xmm15 paddd %xmm15,%xmm14 pand L$clamp(%rip),%xmm0 movdqa %xmm0,0+0(%rbp) movdqa %xmm4,0+16(%rbp) movq %r8,%r8 call poly_hash_ad_internal L$open_sse_128_xor_hash: cmpq $16,%rbx jb L$open_sse_tail_16 subq $16,%rbx addq 0+0(%rsi),%r10 adcq 8+0(%rsi),%r11 adcq $1,%r12 movdqu 0(%rsi),%xmm3 pxor %xmm3,%xmm1 movdqu %xmm1,0(%rdi) leaq 16(%rsi),%rsi leaq 16(%rdi),%rdi movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 movdqa %xmm5,%xmm1 movdqa %xmm9,%xmm5 movdqa %xmm13,%xmm9 movdqa %xmm2,%xmm13 movdqa %xmm6,%xmm2 movdqa %xmm10,%xmm6 movdqa %xmm14,%xmm10 jmp L$open_sse_128_xor_hash .globl _chacha20_poly1305_seal .private_extern _chacha20_poly1305_seal .p2align 6 _chacha20_poly1305_seal: _CET_ENDBR pushq %rbp pushq %rbx pushq %r12 pushq %r13 pushq %r14 pushq %r15 pushq %r9 subq $288 + 0 + 32,%rsp leaq 32(%rsp),%rbp andq $-32,%rbp movq 56(%r9),%rbx addq %rdx,%rbx movq %r8,0+0+32(%rbp) movq %rbx,8+0+32(%rbp) movq %rdx,%rbx movl _OPENSSL_ia32cap_P+8(%rip),%eax andl $288,%eax xorl $288,%eax jz chacha20_poly1305_seal_avx2 cmpq $128,%rbx jbe L$seal_sse_128 movdqa L$chacha20_consts(%rip),%xmm0 movdqu 0(%r9),%xmm4 movdqu 16(%r9),%xmm8 movdqu 32(%r9),%xmm12 movdqa %xmm0,%xmm1 movdqa %xmm0,%xmm2 movdqa %xmm0,%xmm3 movdqa %xmm4,%xmm5 movdqa %xmm4,%xmm6 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm9 movdqa %xmm8,%xmm10 movdqa %xmm8,%xmm11 movdqa %xmm12,%xmm15 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,%xmm14 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,%xmm13 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm4,0+48(%rbp) movdqa %xmm8,0+64(%rbp) movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) movdqa %xmm15,0+144(%rbp) movq $10,%r10 L$seal_sse_init_rounds: movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 .byte 102,15,58,15,255,4 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,12 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 .byte 102,15,58,15,255,12 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,4 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 decq %r10 jnz L$seal_sse_init_rounds paddd L$chacha20_consts(%rip),%xmm3 paddd 0+48(%rbp),%xmm7 paddd 0+64(%rbp),%xmm11 paddd 0+144(%rbp),%xmm15 paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 pand L$clamp(%rip),%xmm3 movdqa %xmm3,0+0(%rbp) movdqa %xmm7,0+16(%rbp) movq %r8,%r8 call poly_hash_ad_internal movdqu 0 + 0(%rsi),%xmm3 movdqu 16 + 0(%rsi),%xmm7 movdqu 32 + 0(%rsi),%xmm11 movdqu 48 + 0(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 0(%rdi) movdqu %xmm6,16 + 0(%rdi) movdqu %xmm10,32 + 0(%rdi) movdqu %xmm15,48 + 0(%rdi) movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 64(%rdi) movdqu %xmm5,16 + 64(%rdi) movdqu %xmm9,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) cmpq $192,%rbx ja L$seal_sse_main_init movq $128,%rcx subq $128,%rbx leaq 128(%rsi),%rsi jmp L$seal_sse_128_tail_hash L$seal_sse_main_init: movdqu 0 + 128(%rsi),%xmm3 movdqu 16 + 128(%rsi),%xmm7 movdqu 32 + 128(%rsi),%xmm11 movdqu 48 + 128(%rsi),%xmm15 pxor %xmm3,%xmm0 pxor %xmm7,%xmm4 pxor %xmm11,%xmm8 pxor %xmm12,%xmm15 movdqu %xmm0,0 + 128(%rdi) movdqu %xmm4,16 + 128(%rdi) movdqu %xmm8,32 + 128(%rdi) movdqu %xmm15,48 + 128(%rdi) movq $192,%rcx subq $192,%rbx leaq 192(%rsi),%rsi movq $2,%rcx movq $8,%r8 cmpq $64,%rbx jbe L$seal_sse_tail_64 cmpq $128,%rbx jbe L$seal_sse_tail_128 cmpq $192,%rbx jbe L$seal_sse_tail_192 L$seal_sse_main_loop: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa %xmm0,%xmm2 movdqa %xmm4,%xmm6 movdqa %xmm8,%xmm10 movdqa %xmm0,%xmm3 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm11 movdqa 0+96(%rbp),%xmm15 paddd L$sse_inc(%rip),%xmm15 movdqa %xmm15,%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm14,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) movdqa %xmm15,0+144(%rbp) .p2align 5 L$seal_sse_main_rounds: movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 .byte 102,15,58,15,255,4 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,12 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 movdqa %xmm8,0+80(%rbp) movdqa L$rol16(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $20,%xmm8 pslld $32-20,%xmm4 pxor %xmm8,%xmm4 movdqa L$rol8(%rip),%xmm8 paddd %xmm7,%xmm3 paddd %xmm6,%xmm2 paddd %xmm5,%xmm1 paddd %xmm4,%xmm0 pxor %xmm3,%xmm15 pxor %xmm2,%xmm14 pxor %xmm1,%xmm13 pxor %xmm0,%xmm12 .byte 102,69,15,56,0,248 .byte 102,69,15,56,0,240 .byte 102,69,15,56,0,232 .byte 102,69,15,56,0,224 movdqa 0+80(%rbp),%xmm8 paddd %xmm15,%xmm11 paddd %xmm14,%xmm10 paddd %xmm13,%xmm9 paddd %xmm12,%xmm8 pxor %xmm11,%xmm7 pxor %xmm10,%xmm6 pxor %xmm9,%xmm5 pxor %xmm8,%xmm4 movdqa %xmm8,0+80(%rbp) movdqa %xmm7,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm7 pxor %xmm8,%xmm7 movdqa %xmm6,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm6 pxor %xmm8,%xmm6 movdqa %xmm5,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm5 pxor %xmm8,%xmm5 movdqa %xmm4,%xmm8 psrld $25,%xmm8 pslld $32-25,%xmm4 pxor %xmm8,%xmm4 movdqa 0+80(%rbp),%xmm8 .byte 102,15,58,15,255,12 .byte 102,69,15,58,15,219,8 .byte 102,69,15,58,15,255,4 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 leaq 16(%rdi),%rdi decq %r8 jge L$seal_sse_main_rounds addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi decq %rcx jg L$seal_sse_main_rounds paddd L$chacha20_consts(%rip),%xmm3 paddd 0+48(%rbp),%xmm7 paddd 0+64(%rbp),%xmm11 paddd 0+144(%rbp),%xmm15 paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqa %xmm14,0+80(%rbp) movdqa %xmm14,0+80(%rbp) movdqu 0 + 0(%rsi),%xmm14 pxor %xmm3,%xmm14 movdqu %xmm14,0 + 0(%rdi) movdqu 16 + 0(%rsi),%xmm14 pxor %xmm7,%xmm14 movdqu %xmm14,16 + 0(%rdi) movdqu 32 + 0(%rsi),%xmm14 pxor %xmm11,%xmm14 movdqu %xmm14,32 + 0(%rdi) movdqu 48 + 0(%rsi),%xmm14 pxor %xmm15,%xmm14 movdqu %xmm14,48 + 0(%rdi) movdqa 0+80(%rbp),%xmm14 movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 64(%rdi) movdqu %xmm6,16 + 64(%rdi) movdqu %xmm10,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) movdqu 0 + 128(%rsi),%xmm3 movdqu 16 + 128(%rsi),%xmm7 movdqu 32 + 128(%rsi),%xmm11 movdqu 48 + 128(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 128(%rdi) movdqu %xmm5,16 + 128(%rdi) movdqu %xmm9,32 + 128(%rdi) movdqu %xmm15,48 + 128(%rdi) cmpq $256,%rbx ja L$seal_sse_main_loop_xor movq $192,%rcx subq $192,%rbx leaq 192(%rsi),%rsi jmp L$seal_sse_128_tail_hash L$seal_sse_main_loop_xor: movdqu 0 + 192(%rsi),%xmm3 movdqu 16 + 192(%rsi),%xmm7 movdqu 32 + 192(%rsi),%xmm11 movdqu 48 + 192(%rsi),%xmm15 pxor %xmm3,%xmm0 pxor %xmm7,%xmm4 pxor %xmm11,%xmm8 pxor %xmm12,%xmm15 movdqu %xmm0,0 + 192(%rdi) movdqu %xmm4,16 + 192(%rdi) movdqu %xmm8,32 + 192(%rdi) movdqu %xmm15,48 + 192(%rdi) leaq 256(%rsi),%rsi subq $256,%rbx movq $6,%rcx movq $4,%r8 cmpq $192,%rbx jg L$seal_sse_main_loop movq %rbx,%rcx testq %rbx,%rbx je L$seal_sse_128_tail_hash movq $6,%rcx cmpq $128,%rbx ja L$seal_sse_tail_192 cmpq $64,%rbx ja L$seal_sse_tail_128 L$seal_sse_tail_64: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa 0+96(%rbp),%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) L$seal_sse_tail_64_rounds_and_x2hash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_sse_tail_64_rounds_and_x1hash: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi decq %rcx jg L$seal_sse_tail_64_rounds_and_x2hash decq %r8 jge L$seal_sse_tail_64_rounds_and_x1hash paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 jmp L$seal_sse_128_tail_xor L$seal_sse_tail_128: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa 0+96(%rbp),%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) L$seal_sse_tail_128_rounds_and_x2hash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_sse_tail_128_rounds_and_x1hash: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 leaq 16(%rdi),%rdi decq %rcx jg L$seal_sse_tail_128_rounds_and_x2hash decq %r8 jge L$seal_sse_tail_128_rounds_and_x1hash paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqu 0 + 0(%rsi),%xmm3 movdqu 16 + 0(%rsi),%xmm7 movdqu 32 + 0(%rsi),%xmm11 movdqu 48 + 0(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 0(%rdi) movdqu %xmm5,16 + 0(%rdi) movdqu %xmm9,32 + 0(%rdi) movdqu %xmm15,48 + 0(%rdi) movq $64,%rcx subq $64,%rbx leaq 64(%rsi),%rsi jmp L$seal_sse_128_tail_hash L$seal_sse_tail_192: movdqa L$chacha20_consts(%rip),%xmm0 movdqa 0+48(%rbp),%xmm4 movdqa 0+64(%rbp),%xmm8 movdqa %xmm0,%xmm1 movdqa %xmm4,%xmm5 movdqa %xmm8,%xmm9 movdqa %xmm0,%xmm2 movdqa %xmm4,%xmm6 movdqa %xmm8,%xmm10 movdqa 0+96(%rbp),%xmm14 paddd L$sse_inc(%rip),%xmm14 movdqa %xmm14,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm13,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,0+96(%rbp) movdqa %xmm13,0+112(%rbp) movdqa %xmm14,0+128(%rbp) L$seal_sse_tail_192_rounds_and_x2hash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_sse_tail_192_rounds_and_x1hash: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 leaq 16(%rdi),%rdi decq %rcx jg L$seal_sse_tail_192_rounds_and_x2hash decq %r8 jge L$seal_sse_tail_192_rounds_and_x1hash paddd L$chacha20_consts(%rip),%xmm2 paddd 0+48(%rbp),%xmm6 paddd 0+64(%rbp),%xmm10 paddd 0+128(%rbp),%xmm14 paddd L$chacha20_consts(%rip),%xmm1 paddd 0+48(%rbp),%xmm5 paddd 0+64(%rbp),%xmm9 paddd 0+112(%rbp),%xmm13 paddd L$chacha20_consts(%rip),%xmm0 paddd 0+48(%rbp),%xmm4 paddd 0+64(%rbp),%xmm8 paddd 0+96(%rbp),%xmm12 movdqu 0 + 0(%rsi),%xmm3 movdqu 16 + 0(%rsi),%xmm7 movdqu 32 + 0(%rsi),%xmm11 movdqu 48 + 0(%rsi),%xmm15 pxor %xmm3,%xmm2 pxor %xmm7,%xmm6 pxor %xmm11,%xmm10 pxor %xmm14,%xmm15 movdqu %xmm2,0 + 0(%rdi) movdqu %xmm6,16 + 0(%rdi) movdqu %xmm10,32 + 0(%rdi) movdqu %xmm15,48 + 0(%rdi) movdqu 0 + 64(%rsi),%xmm3 movdqu 16 + 64(%rsi),%xmm7 movdqu 32 + 64(%rsi),%xmm11 movdqu 48 + 64(%rsi),%xmm15 pxor %xmm3,%xmm1 pxor %xmm7,%xmm5 pxor %xmm11,%xmm9 pxor %xmm13,%xmm15 movdqu %xmm1,0 + 64(%rdi) movdqu %xmm5,16 + 64(%rdi) movdqu %xmm9,32 + 64(%rdi) movdqu %xmm15,48 + 64(%rdi) movq $128,%rcx subq $128,%rbx leaq 128(%rsi),%rsi L$seal_sse_128_tail_hash: cmpq $16,%rcx jb L$seal_sse_128_tail_xor addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 subq $16,%rcx leaq 16(%rdi),%rdi jmp L$seal_sse_128_tail_hash L$seal_sse_128_tail_xor: cmpq $16,%rbx jb L$seal_sse_tail_16 subq $16,%rbx movdqu 0(%rsi),%xmm3 pxor %xmm3,%xmm0 movdqu %xmm0,0(%rdi) addq 0(%rdi),%r10 adcq 8(%rdi),%r11 adcq $1,%r12 leaq 16(%rsi),%rsi leaq 16(%rdi),%rdi movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 movdqa %xmm4,%xmm0 movdqa %xmm8,%xmm4 movdqa %xmm12,%xmm8 movdqa %xmm1,%xmm12 movdqa %xmm5,%xmm1 movdqa %xmm9,%xmm5 movdqa %xmm13,%xmm9 jmp L$seal_sse_128_tail_xor L$seal_sse_tail_16: testq %rbx,%rbx jz L$process_blocks_of_extra_in movq %rbx,%r8 movq %rbx,%rcx leaq -1(%rsi,%rbx,1),%rsi pxor %xmm15,%xmm15 L$seal_sse_tail_16_compose: pslldq $1,%xmm15 pinsrb $0,(%rsi),%xmm15 leaq -1(%rsi),%rsi decq %rcx jne L$seal_sse_tail_16_compose pxor %xmm0,%xmm15 movq %rbx,%rcx movdqu %xmm15,%xmm0 L$seal_sse_tail_16_extract: pextrb $0,%xmm0,(%rdi) psrldq $1,%xmm0 addq $1,%rdi subq $1,%rcx jnz L$seal_sse_tail_16_extract movq 288 + 0 + 32(%rsp),%r9 movq 56(%r9),%r14 movq 48(%r9),%r13 testq %r14,%r14 jz L$process_partial_block movq $16,%r15 subq %rbx,%r15 cmpq %r15,%r14 jge L$load_extra_in movq %r14,%r15 L$load_extra_in: leaq -1(%r13,%r15,1),%rsi addq %r15,%r13 subq %r15,%r14 movq %r13,48(%r9) movq %r14,56(%r9) addq %r15,%r8 pxor %xmm11,%xmm11 L$load_extra_load_loop: pslldq $1,%xmm11 pinsrb $0,(%rsi),%xmm11 leaq -1(%rsi),%rsi subq $1,%r15 jnz L$load_extra_load_loop movq %rbx,%r15 L$load_extra_shift_loop: pslldq $1,%xmm11 subq $1,%r15 jnz L$load_extra_shift_loop leaq L$and_masks(%rip),%r15 shlq $4,%rbx pand -16(%r15,%rbx,1),%xmm15 por %xmm11,%xmm15 .byte 102,77,15,126,253 pextrq $1,%xmm15,%r14 addq %r13,%r10 adcq %r14,%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$process_blocks_of_extra_in: movq 288+32+0 (%rsp),%r9 movq 48(%r9),%rsi movq 56(%r9),%r8 movq %r8,%rcx shrq $4,%r8 L$process_extra_hash_loop: jz process_extra_in_trailer addq 0+0(%rsi),%r10 adcq 8+0(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rsi),%rsi subq $1,%r8 jmp L$process_extra_hash_loop process_extra_in_trailer: andq $15,%rcx movq %rcx,%rbx jz L$do_length_block leaq -1(%rsi,%rcx,1),%rsi L$process_extra_in_trailer_load: pslldq $1,%xmm15 pinsrb $0,(%rsi),%xmm15 leaq -1(%rsi),%rsi subq $1,%rcx jnz L$process_extra_in_trailer_load L$process_partial_block: leaq L$and_masks(%rip),%r15 shlq $4,%rbx pand -16(%r15,%rbx,1),%xmm15 .byte 102,77,15,126,253 pextrq $1,%xmm15,%r14 addq %r13,%r10 adcq %r14,%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$do_length_block: addq 0+0+32(%rbp),%r10 adcq 8+0+32(%rbp),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 movq %r10,%r13 movq %r11,%r14 movq %r12,%r15 subq $-5,%r10 sbbq $-1,%r11 sbbq $3,%r12 cmovcq %r13,%r10 cmovcq %r14,%r11 cmovcq %r15,%r12 addq 0+0+16(%rbp),%r10 adcq 8+0+16(%rbp),%r11 addq $288 + 0 + 32,%rsp popq %r9 movq %r10,(%r9) movq %r11,8(%r9) popq %r15 popq %r14 popq %r13 popq %r12 popq %rbx popq %rbp ret L$seal_sse_128: movdqu L$chacha20_consts(%rip),%xmm0 movdqa %xmm0,%xmm1 movdqa %xmm0,%xmm2 movdqu 0(%r9),%xmm4 movdqa %xmm4,%xmm5 movdqa %xmm4,%xmm6 movdqu 16(%r9),%xmm8 movdqa %xmm8,%xmm9 movdqa %xmm8,%xmm10 movdqu 32(%r9),%xmm14 movdqa %xmm14,%xmm12 paddd L$sse_inc(%rip),%xmm12 movdqa %xmm12,%xmm13 paddd L$sse_inc(%rip),%xmm13 movdqa %xmm4,%xmm7 movdqa %xmm8,%xmm11 movdqa %xmm12,%xmm15 movq $10,%r10 L$seal_sse_128_rounds: paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,4 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,12 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,4 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,12 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,4 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,12 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol16(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $12,%xmm3 psrld $20,%xmm4 pxor %xmm3,%xmm4 paddd %xmm4,%xmm0 pxor %xmm0,%xmm12 pshufb L$rol8(%rip),%xmm12 paddd %xmm12,%xmm8 pxor %xmm8,%xmm4 movdqa %xmm4,%xmm3 pslld $7,%xmm3 psrld $25,%xmm4 pxor %xmm3,%xmm4 .byte 102,15,58,15,228,12 .byte 102,69,15,58,15,192,8 .byte 102,69,15,58,15,228,4 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol16(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $12,%xmm3 psrld $20,%xmm5 pxor %xmm3,%xmm5 paddd %xmm5,%xmm1 pxor %xmm1,%xmm13 pshufb L$rol8(%rip),%xmm13 paddd %xmm13,%xmm9 pxor %xmm9,%xmm5 movdqa %xmm5,%xmm3 pslld $7,%xmm3 psrld $25,%xmm5 pxor %xmm3,%xmm5 .byte 102,15,58,15,237,12 .byte 102,69,15,58,15,201,8 .byte 102,69,15,58,15,237,4 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol16(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $12,%xmm3 psrld $20,%xmm6 pxor %xmm3,%xmm6 paddd %xmm6,%xmm2 pxor %xmm2,%xmm14 pshufb L$rol8(%rip),%xmm14 paddd %xmm14,%xmm10 pxor %xmm10,%xmm6 movdqa %xmm6,%xmm3 pslld $7,%xmm3 psrld $25,%xmm6 pxor %xmm3,%xmm6 .byte 102,15,58,15,246,12 .byte 102,69,15,58,15,210,8 .byte 102,69,15,58,15,246,4 decq %r10 jnz L$seal_sse_128_rounds paddd L$chacha20_consts(%rip),%xmm0 paddd L$chacha20_consts(%rip),%xmm1 paddd L$chacha20_consts(%rip),%xmm2 paddd %xmm7,%xmm4 paddd %xmm7,%xmm5 paddd %xmm7,%xmm6 paddd %xmm11,%xmm8 paddd %xmm11,%xmm9 paddd %xmm15,%xmm12 paddd L$sse_inc(%rip),%xmm15 paddd %xmm15,%xmm13 pand L$clamp(%rip),%xmm2 movdqa %xmm2,0+0(%rbp) movdqa %xmm6,0+16(%rbp) movq %r8,%r8 call poly_hash_ad_internal jmp L$seal_sse_128_tail_xor .p2align 6 chacha20_poly1305_open_avx2: vzeroupper vmovdqa L$chacha20_consts(%rip),%ymm0 vbroadcasti128 0(%r9),%ymm4 vbroadcasti128 16(%r9),%ymm8 vbroadcasti128 32(%r9),%ymm12 vpaddd L$avx2_init(%rip),%ymm12,%ymm12 cmpq $192,%rbx jbe L$open_avx2_192 cmpq $320,%rbx jbe L$open_avx2_320 vmovdqa %ymm4,0+64(%rbp) vmovdqa %ymm8,0+96(%rbp) vmovdqa %ymm12,0+160(%rbp) movq $10,%r10 L$open_avx2_init_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 decq %r10 jne L$open_avx2_init_rounds vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vpand L$clamp(%rip),%ymm3,%ymm3 vmovdqa %ymm3,0+0(%rbp) vperm2i128 $0x13,%ymm0,%ymm4,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm4 movq %r8,%r8 call poly_hash_ad_internal xorq %rcx,%rcx L$open_avx2_init_hash: addq 0+0(%rsi,%rcx,1),%r10 adcq 8+0(%rsi,%rcx,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq $16,%rcx cmpq $64,%rcx jne L$open_avx2_init_hash vpxor 0(%rsi),%ymm0,%ymm0 vpxor 32(%rsi),%ymm4,%ymm4 vmovdqu %ymm0,0(%rdi) vmovdqu %ymm4,32(%rdi) leaq 64(%rsi),%rsi leaq 64(%rdi),%rdi subq $64,%rbx L$open_avx2_main_loop: cmpq $512,%rbx jb L$open_avx2_main_loop_done vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm15 vpaddd %ymm15,%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm15,0+256(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm12,0+160(%rbp) xorq %rcx,%rcx L$open_avx2_main_loop_rounds: addq 0+0(%rsi,%rcx,1),%r10 adcq 8+0(%rsi,%rcx,1),%r11 adcq $1,%r12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 addq %rax,%r15 adcq %rdx,%r9 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 addq 0+16(%rsi,%rcx,1),%r10 adcq 8+16(%rsi,%rcx,1),%r11 adcq $1,%r12 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 addq %rax,%r15 adcq %rdx,%r9 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 addq 0+32(%rsi,%rcx,1),%r10 adcq 8+32(%rsi,%rcx,1),%r11 adcq $1,%r12 leaq 48(%rcx),%rcx vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 addq %rax,%r15 adcq %rdx,%r9 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpalignr $4,%ymm12,%ymm12,%ymm12 cmpq $60*8,%rcx jne L$open_avx2_main_loop_rounds vpaddd L$chacha20_consts(%rip),%ymm3,%ymm3 vpaddd 0+64(%rbp),%ymm7,%ymm7 vpaddd 0+96(%rbp),%ymm11,%ymm11 vpaddd 0+256(%rbp),%ymm15,%ymm15 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm0,0+128(%rbp) addq 0+60*8(%rsi),%r10 adcq 8+60*8(%rsi),%r11 adcq $1,%r12 vperm2i128 $0x02,%ymm3,%ymm7,%ymm0 vperm2i128 $0x13,%ymm3,%ymm7,%ymm7 vperm2i128 $0x02,%ymm11,%ymm15,%ymm3 vperm2i128 $0x13,%ymm11,%ymm15,%ymm11 vpxor 0+0(%rsi),%ymm0,%ymm0 vpxor 32+0(%rsi),%ymm3,%ymm3 vpxor 64+0(%rsi),%ymm7,%ymm7 vpxor 96+0(%rsi),%ymm11,%ymm11 vmovdqu %ymm0,0+0(%rdi) vmovdqu %ymm3,32+0(%rdi) vmovdqu %ymm7,64+0(%rdi) vmovdqu %ymm11,96+0(%rdi) vmovdqa 0+128(%rbp),%ymm0 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm2,%ymm2 vpxor 64+128(%rsi),%ymm6,%ymm6 vpxor 96+128(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm2,32+128(%rdi) vmovdqu %ymm6,64+128(%rdi) vmovdqu %ymm10,96+128(%rdi) addq 0+60*8+16(%rsi),%r10 adcq 8+60*8+16(%rsi),%r11 adcq $1,%r12 vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+256(%rsi),%ymm3,%ymm3 vpxor 32+256(%rsi),%ymm1,%ymm1 vpxor 64+256(%rsi),%ymm5,%ymm5 vpxor 96+256(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+256(%rdi) vmovdqu %ymm1,32+256(%rdi) vmovdqu %ymm5,64+256(%rdi) vmovdqu %ymm9,96+256(%rdi) movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vperm2i128 $0x13,%ymm0,%ymm4,%ymm4 vperm2i128 $0x02,%ymm8,%ymm12,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm8 vpxor 0+384(%rsi),%ymm3,%ymm3 vpxor 32+384(%rsi),%ymm0,%ymm0 vpxor 64+384(%rsi),%ymm4,%ymm4 vpxor 96+384(%rsi),%ymm8,%ymm8 vmovdqu %ymm3,0+384(%rdi) vmovdqu %ymm0,32+384(%rdi) vmovdqu %ymm4,64+384(%rdi) vmovdqu %ymm8,96+384(%rdi) leaq 512(%rsi),%rsi leaq 512(%rdi),%rdi subq $512,%rbx jmp L$open_avx2_main_loop L$open_avx2_main_loop_done: testq %rbx,%rbx vzeroupper je L$open_sse_finalize cmpq $384,%rbx ja L$open_avx2_tail_512 cmpq $256,%rbx ja L$open_avx2_tail_384 cmpq $128,%rbx ja L$open_avx2_tail_256 vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) xorq %r8,%r8 movq %rbx,%rcx andq $-16,%rcx testq %rcx,%rcx je L$open_avx2_tail_128_rounds L$open_avx2_tail_128_rounds_and_x1hash: addq 0+0(%rsi,%r8,1),%r10 adcq 8+0(%rsi,%r8,1),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$open_avx2_tail_128_rounds: addq $16,%r8 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 cmpq %rcx,%r8 jb L$open_avx2_tail_128_rounds_and_x1hash cmpq $160,%r8 jne L$open_avx2_tail_128_rounds vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 jmp L$open_avx2_tail_128_xor L$open_avx2_tail_256: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) movq %rbx,0+128(%rbp) movq %rbx,%rcx subq $128,%rcx shrq $4,%rcx movq $10,%r8 cmpq $10,%rcx cmovgq %r8,%rcx movq %rsi,%rbx xorq %r8,%r8 L$open_avx2_tail_256_rounds_and_x1hash: addq 0+0(%rbx),%r10 adcq 8+0(%rbx),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rbx),%rbx L$open_avx2_tail_256_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 incq %r8 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm6,%ymm6,%ymm6 cmpq %rcx,%r8 jb L$open_avx2_tail_256_rounds_and_x1hash cmpq $10,%r8 jne L$open_avx2_tail_256_rounds movq %rbx,%r8 subq %rsi,%rbx movq %rbx,%rcx movq 0+128(%rbp),%rbx L$open_avx2_tail_256_hash: addq $16,%rcx cmpq %rbx,%rcx jg L$open_avx2_tail_256_done addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%r8),%r8 jmp L$open_avx2_tail_256_hash L$open_avx2_tail_256_done: vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+0(%rsi),%ymm3,%ymm3 vpxor 32+0(%rsi),%ymm1,%ymm1 vpxor 64+0(%rsi),%ymm5,%ymm5 vpxor 96+0(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+0(%rdi) vmovdqu %ymm1,32+0(%rdi) vmovdqu %ymm5,64+0(%rdi) vmovdqu %ymm9,96+0(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 leaq 128(%rsi),%rsi leaq 128(%rdi),%rdi subq $128,%rbx jmp L$open_avx2_tail_128_xor L$open_avx2_tail_384: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm14,0+224(%rbp) movq %rbx,0+128(%rbp) movq %rbx,%rcx subq $256,%rcx shrq $4,%rcx addq $6,%rcx movq $10,%r8 cmpq $10,%rcx cmovgq %r8,%rcx movq %rsi,%rbx xorq %r8,%r8 L$open_avx2_tail_384_rounds_and_x2hash: addq 0+0(%rbx),%r10 adcq 8+0(%rbx),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rbx),%rbx L$open_avx2_tail_384_rounds_and_x1hash: vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm6,%ymm6,%ymm6 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 addq 0+0(%rbx),%r10 adcq 8+0(%rbx),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rbx),%rbx incq %r8 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm6,%ymm6,%ymm6 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 cmpq %rcx,%r8 jb L$open_avx2_tail_384_rounds_and_x2hash cmpq $10,%r8 jne L$open_avx2_tail_384_rounds_and_x1hash movq %rbx,%r8 subq %rsi,%rbx movq %rbx,%rcx movq 0+128(%rbp),%rbx L$open_avx2_384_tail_hash: addq $16,%rcx cmpq %rbx,%rcx jg L$open_avx2_384_tail_done addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%r8),%r8 jmp L$open_avx2_384_tail_hash L$open_avx2_384_tail_done: vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+0(%rsi),%ymm3,%ymm3 vpxor 32+0(%rsi),%ymm2,%ymm2 vpxor 64+0(%rsi),%ymm6,%ymm6 vpxor 96+0(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+0(%rdi) vmovdqu %ymm2,32+0(%rdi) vmovdqu %ymm6,64+0(%rdi) vmovdqu %ymm10,96+0(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm1,%ymm1 vpxor 64+128(%rsi),%ymm5,%ymm5 vpxor 96+128(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm1,32+128(%rdi) vmovdqu %ymm5,64+128(%rdi) vmovdqu %ymm9,96+128(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 leaq 256(%rsi),%rsi leaq 256(%rdi),%rdi subq $256,%rbx jmp L$open_avx2_tail_128_xor L$open_avx2_tail_512: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm15 vpaddd %ymm15,%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm15,0+256(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm12,0+160(%rbp) xorq %rcx,%rcx movq %rsi,%r8 L$open_avx2_tail_512_rounds_and_x2hash: addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%r8),%r8 L$open_avx2_tail_512_rounds_and_x1hash: vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 addq 0+16(%r8),%r10 adcq 8+16(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%r8),%r8 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm12,%ymm12,%ymm12 incq %rcx cmpq $4,%rcx jl L$open_avx2_tail_512_rounds_and_x2hash cmpq $10,%rcx jne L$open_avx2_tail_512_rounds_and_x1hash movq %rbx,%rcx subq $384,%rcx andq $-16,%rcx L$open_avx2_tail_512_hash: testq %rcx,%rcx je L$open_avx2_tail_512_done addq 0+0(%r8),%r10 adcq 8+0(%r8),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%r8),%r8 subq $16,%rcx jmp L$open_avx2_tail_512_hash L$open_avx2_tail_512_done: vpaddd L$chacha20_consts(%rip),%ymm3,%ymm3 vpaddd 0+64(%rbp),%ymm7,%ymm7 vpaddd 0+96(%rbp),%ymm11,%ymm11 vpaddd 0+256(%rbp),%ymm15,%ymm15 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm0,0+128(%rbp) vperm2i128 $0x02,%ymm3,%ymm7,%ymm0 vperm2i128 $0x13,%ymm3,%ymm7,%ymm7 vperm2i128 $0x02,%ymm11,%ymm15,%ymm3 vperm2i128 $0x13,%ymm11,%ymm15,%ymm11 vpxor 0+0(%rsi),%ymm0,%ymm0 vpxor 32+0(%rsi),%ymm3,%ymm3 vpxor 64+0(%rsi),%ymm7,%ymm7 vpxor 96+0(%rsi),%ymm11,%ymm11 vmovdqu %ymm0,0+0(%rdi) vmovdqu %ymm3,32+0(%rdi) vmovdqu %ymm7,64+0(%rdi) vmovdqu %ymm11,96+0(%rdi) vmovdqa 0+128(%rbp),%ymm0 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm2,%ymm2 vpxor 64+128(%rsi),%ymm6,%ymm6 vpxor 96+128(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm2,32+128(%rdi) vmovdqu %ymm6,64+128(%rdi) vmovdqu %ymm10,96+128(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+256(%rsi),%ymm3,%ymm3 vpxor 32+256(%rsi),%ymm1,%ymm1 vpxor 64+256(%rsi),%ymm5,%ymm5 vpxor 96+256(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+256(%rdi) vmovdqu %ymm1,32+256(%rdi) vmovdqu %ymm5,64+256(%rdi) vmovdqu %ymm9,96+256(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 leaq 384(%rsi),%rsi leaq 384(%rdi),%rdi subq $384,%rbx L$open_avx2_tail_128_xor: cmpq $32,%rbx jb L$open_avx2_tail_32_xor subq $32,%rbx vpxor (%rsi),%ymm0,%ymm0 vmovdqu %ymm0,(%rdi) leaq 32(%rsi),%rsi leaq 32(%rdi),%rdi vmovdqa %ymm4,%ymm0 vmovdqa %ymm8,%ymm4 vmovdqa %ymm12,%ymm8 jmp L$open_avx2_tail_128_xor L$open_avx2_tail_32_xor: cmpq $16,%rbx vmovdqa %xmm0,%xmm1 jb L$open_avx2_exit subq $16,%rbx vpxor (%rsi),%xmm0,%xmm1 vmovdqu %xmm1,(%rdi) leaq 16(%rsi),%rsi leaq 16(%rdi),%rdi vperm2i128 $0x11,%ymm0,%ymm0,%ymm0 vmovdqa %xmm0,%xmm1 L$open_avx2_exit: vzeroupper jmp L$open_sse_tail_16 L$open_avx2_192: vmovdqa %ymm0,%ymm1 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm5 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm9 vmovdqa %ymm8,%ymm10 vpaddd L$avx2_inc(%rip),%ymm12,%ymm13 vmovdqa %ymm12,%ymm11 vmovdqa %ymm13,%ymm15 movq $10,%r10 L$open_avx2_192_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 decq %r10 jne L$open_avx2_192_rounds vpaddd %ymm2,%ymm0,%ymm0 vpaddd %ymm2,%ymm1,%ymm1 vpaddd %ymm6,%ymm4,%ymm4 vpaddd %ymm6,%ymm5,%ymm5 vpaddd %ymm10,%ymm8,%ymm8 vpaddd %ymm10,%ymm9,%ymm9 vpaddd %ymm11,%ymm12,%ymm12 vpaddd %ymm15,%ymm13,%ymm13 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vpand L$clamp(%rip),%ymm3,%ymm3 vmovdqa %ymm3,0+0(%rbp) vperm2i128 $0x13,%ymm0,%ymm4,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm4 vperm2i128 $0x02,%ymm1,%ymm5,%ymm8 vperm2i128 $0x02,%ymm9,%ymm13,%ymm12 vperm2i128 $0x13,%ymm1,%ymm5,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm5 L$open_avx2_short: movq %r8,%r8 call poly_hash_ad_internal L$open_avx2_short_hash_and_xor_loop: cmpq $32,%rbx jb L$open_avx2_short_tail_32 subq $32,%rbx addq 0+0(%rsi),%r10 adcq 8+0(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq 0+16(%rsi),%r10 adcq 8+16(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor (%rsi),%ymm0,%ymm0 vmovdqu %ymm0,(%rdi) leaq 32(%rsi),%rsi leaq 32(%rdi),%rdi vmovdqa %ymm4,%ymm0 vmovdqa %ymm8,%ymm4 vmovdqa %ymm12,%ymm8 vmovdqa %ymm1,%ymm12 vmovdqa %ymm5,%ymm1 vmovdqa %ymm9,%ymm5 vmovdqa %ymm13,%ymm9 vmovdqa %ymm2,%ymm13 vmovdqa %ymm6,%ymm2 jmp L$open_avx2_short_hash_and_xor_loop L$open_avx2_short_tail_32: cmpq $16,%rbx vmovdqa %xmm0,%xmm1 jb L$open_avx2_short_tail_32_exit subq $16,%rbx addq 0+0(%rsi),%r10 adcq 8+0(%rsi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor (%rsi),%xmm0,%xmm3 vmovdqu %xmm3,(%rdi) leaq 16(%rsi),%rsi leaq 16(%rdi),%rdi vextracti128 $1,%ymm0,%xmm1 L$open_avx2_short_tail_32_exit: vzeroupper jmp L$open_sse_tail_16 L$open_avx2_320: vmovdqa %ymm0,%ymm1 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm5 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm9 vmovdqa %ymm8,%ymm10 vpaddd L$avx2_inc(%rip),%ymm12,%ymm13 vpaddd L$avx2_inc(%rip),%ymm13,%ymm14 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm14,0+224(%rbp) movq $10,%r10 L$open_avx2_320_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm6,%ymm6,%ymm6 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm6,%ymm6,%ymm6 decq %r10 jne L$open_avx2_320_rounds vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd %ymm7,%ymm4,%ymm4 vpaddd %ymm7,%ymm5,%ymm5 vpaddd %ymm7,%ymm6,%ymm6 vpaddd %ymm11,%ymm8,%ymm8 vpaddd %ymm11,%ymm9,%ymm9 vpaddd %ymm11,%ymm10,%ymm10 vpaddd 0+160(%rbp),%ymm12,%ymm12 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd 0+224(%rbp),%ymm14,%ymm14 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vpand L$clamp(%rip),%ymm3,%ymm3 vmovdqa %ymm3,0+0(%rbp) vperm2i128 $0x13,%ymm0,%ymm4,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm4 vperm2i128 $0x02,%ymm1,%ymm5,%ymm8 vperm2i128 $0x02,%ymm9,%ymm13,%ymm12 vperm2i128 $0x13,%ymm1,%ymm5,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm5 vperm2i128 $0x02,%ymm2,%ymm6,%ymm9 vperm2i128 $0x02,%ymm10,%ymm14,%ymm13 vperm2i128 $0x13,%ymm2,%ymm6,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm6 jmp L$open_avx2_short .p2align 6 chacha20_poly1305_seal_avx2: vzeroupper vmovdqa L$chacha20_consts(%rip),%ymm0 vbroadcasti128 0(%r9),%ymm4 vbroadcasti128 16(%r9),%ymm8 vbroadcasti128 32(%r9),%ymm12 vpaddd L$avx2_init(%rip),%ymm12,%ymm12 cmpq $192,%rbx jbe L$seal_avx2_192 cmpq $320,%rbx jbe L$seal_avx2_320 vmovdqa %ymm0,%ymm1 vmovdqa %ymm0,%ymm2 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm5 vmovdqa %ymm4,%ymm6 vmovdqa %ymm4,%ymm7 vmovdqa %ymm4,0+64(%rbp) vmovdqa %ymm8,%ymm9 vmovdqa %ymm8,%ymm10 vmovdqa %ymm8,%ymm11 vmovdqa %ymm8,0+96(%rbp) vmovdqa %ymm12,%ymm15 vpaddd L$avx2_inc(%rip),%ymm15,%ymm14 vpaddd L$avx2_inc(%rip),%ymm14,%ymm13 vpaddd L$avx2_inc(%rip),%ymm13,%ymm12 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm15,0+256(%rbp) movq $10,%r10 L$seal_avx2_init_rounds: vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm12,%ymm12,%ymm12 decq %r10 jnz L$seal_avx2_init_rounds vpaddd L$chacha20_consts(%rip),%ymm3,%ymm3 vpaddd 0+64(%rbp),%ymm7,%ymm7 vpaddd 0+96(%rbp),%ymm11,%ymm11 vpaddd 0+256(%rbp),%ymm15,%ymm15 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x13,%ymm11,%ymm15,%ymm11 vperm2i128 $0x02,%ymm3,%ymm7,%ymm15 vperm2i128 $0x13,%ymm3,%ymm7,%ymm3 vpand L$clamp(%rip),%ymm15,%ymm15 vmovdqa %ymm15,0+0(%rbp) movq %r8,%r8 call poly_hash_ad_internal vpxor 0(%rsi),%ymm3,%ymm3 vpxor 32(%rsi),%ymm11,%ymm11 vmovdqu %ymm3,0(%rdi) vmovdqu %ymm11,32(%rdi) vperm2i128 $0x02,%ymm2,%ymm6,%ymm15 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+64(%rsi),%ymm15,%ymm15 vpxor 32+64(%rsi),%ymm2,%ymm2 vpxor 64+64(%rsi),%ymm6,%ymm6 vpxor 96+64(%rsi),%ymm10,%ymm10 vmovdqu %ymm15,0+64(%rdi) vmovdqu %ymm2,32+64(%rdi) vmovdqu %ymm6,64+64(%rdi) vmovdqu %ymm10,96+64(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm15 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+192(%rsi),%ymm15,%ymm15 vpxor 32+192(%rsi),%ymm1,%ymm1 vpxor 64+192(%rsi),%ymm5,%ymm5 vpxor 96+192(%rsi),%ymm9,%ymm9 vmovdqu %ymm15,0+192(%rdi) vmovdqu %ymm1,32+192(%rdi) vmovdqu %ymm5,64+192(%rdi) vmovdqu %ymm9,96+192(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm15 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm15,%ymm8 leaq 320(%rsi),%rsi subq $320,%rbx movq $320,%rcx cmpq $128,%rbx jbe L$seal_avx2_short_hash_remainder vpxor 0(%rsi),%ymm0,%ymm0 vpxor 32(%rsi),%ymm4,%ymm4 vpxor 64(%rsi),%ymm8,%ymm8 vpxor 96(%rsi),%ymm12,%ymm12 vmovdqu %ymm0,320(%rdi) vmovdqu %ymm4,352(%rdi) vmovdqu %ymm8,384(%rdi) vmovdqu %ymm12,416(%rdi) leaq 128(%rsi),%rsi subq $128,%rbx movq $8,%rcx movq $2,%r8 cmpq $128,%rbx jbe L$seal_avx2_tail_128 cmpq $256,%rbx jbe L$seal_avx2_tail_256 cmpq $384,%rbx jbe L$seal_avx2_tail_384 cmpq $512,%rbx jbe L$seal_avx2_tail_512 vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm15 vpaddd %ymm15,%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm15,0+256(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 subq $16,%rdi movq $9,%rcx jmp L$seal_avx2_main_loop_rounds_entry .p2align 5 L$seal_avx2_main_loop: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm15 vpaddd %ymm15,%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm15,0+256(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm12,0+160(%rbp) movq $10,%rcx .p2align 5 L$seal_avx2_main_loop_rounds: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 addq %rax,%r15 adcq %rdx,%r9 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 L$seal_avx2_main_loop_rounds_entry: vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 addq %rax,%r15 adcq %rdx,%r9 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 addq 0+32(%rdi),%r10 adcq 8+32(%rdi),%r11 adcq $1,%r12 leaq 48(%rdi),%rdi vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 addq %rax,%r15 adcq %rdx,%r9 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpalignr $4,%ymm12,%ymm12,%ymm12 decq %rcx jne L$seal_avx2_main_loop_rounds vpaddd L$chacha20_consts(%rip),%ymm3,%ymm3 vpaddd 0+64(%rbp),%ymm7,%ymm7 vpaddd 0+96(%rbp),%ymm11,%ymm11 vpaddd 0+256(%rbp),%ymm15,%ymm15 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm0,0+128(%rbp) addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi vperm2i128 $0x02,%ymm3,%ymm7,%ymm0 vperm2i128 $0x13,%ymm3,%ymm7,%ymm7 vperm2i128 $0x02,%ymm11,%ymm15,%ymm3 vperm2i128 $0x13,%ymm11,%ymm15,%ymm11 vpxor 0+0(%rsi),%ymm0,%ymm0 vpxor 32+0(%rsi),%ymm3,%ymm3 vpxor 64+0(%rsi),%ymm7,%ymm7 vpxor 96+0(%rsi),%ymm11,%ymm11 vmovdqu %ymm0,0+0(%rdi) vmovdqu %ymm3,32+0(%rdi) vmovdqu %ymm7,64+0(%rdi) vmovdqu %ymm11,96+0(%rdi) vmovdqa 0+128(%rbp),%ymm0 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm2,%ymm2 vpxor 64+128(%rsi),%ymm6,%ymm6 vpxor 96+128(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm2,32+128(%rdi) vmovdqu %ymm6,64+128(%rdi) vmovdqu %ymm10,96+128(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+256(%rsi),%ymm3,%ymm3 vpxor 32+256(%rsi),%ymm1,%ymm1 vpxor 64+256(%rsi),%ymm5,%ymm5 vpxor 96+256(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+256(%rdi) vmovdqu %ymm1,32+256(%rdi) vmovdqu %ymm5,64+256(%rdi) vmovdqu %ymm9,96+256(%rdi) vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vperm2i128 $0x13,%ymm0,%ymm4,%ymm4 vperm2i128 $0x02,%ymm8,%ymm12,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm8 vpxor 0+384(%rsi),%ymm3,%ymm3 vpxor 32+384(%rsi),%ymm0,%ymm0 vpxor 64+384(%rsi),%ymm4,%ymm4 vpxor 96+384(%rsi),%ymm8,%ymm8 vmovdqu %ymm3,0+384(%rdi) vmovdqu %ymm0,32+384(%rdi) vmovdqu %ymm4,64+384(%rdi) vmovdqu %ymm8,96+384(%rdi) leaq 512(%rsi),%rsi subq $512,%rbx cmpq $512,%rbx jg L$seal_avx2_main_loop addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi movq $10,%rcx xorq %r8,%r8 cmpq $384,%rbx ja L$seal_avx2_tail_512 cmpq $256,%rbx ja L$seal_avx2_tail_384 cmpq $128,%rbx ja L$seal_avx2_tail_256 L$seal_avx2_tail_128: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) L$seal_avx2_tail_128_rounds_and_3xhash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_avx2_tail_128_rounds_and_2xhash: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi decq %rcx jg L$seal_avx2_tail_128_rounds_and_3xhash decq %r8 jge L$seal_avx2_tail_128_rounds_and_2xhash vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 jmp L$seal_avx2_short_loop L$seal_avx2_tail_256: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) L$seal_avx2_tail_256_rounds_and_3xhash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_avx2_tail_256_rounds_and_2xhash: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi decq %rcx jg L$seal_avx2_tail_256_rounds_and_3xhash decq %r8 jge L$seal_avx2_tail_256_rounds_and_2xhash vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+0(%rsi),%ymm3,%ymm3 vpxor 32+0(%rsi),%ymm1,%ymm1 vpxor 64+0(%rsi),%ymm5,%ymm5 vpxor 96+0(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+0(%rdi) vmovdqu %ymm1,32+0(%rdi) vmovdqu %ymm5,64+0(%rdi) vmovdqu %ymm9,96+0(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 movq $128,%rcx leaq 128(%rsi),%rsi subq $128,%rbx jmp L$seal_avx2_short_hash_remainder L$seal_avx2_tail_384: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm14,0+224(%rbp) L$seal_avx2_tail_384_rounds_and_3xhash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_avx2_tail_384_rounds_and_2xhash: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm6,%ymm6,%ymm6 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm6,%ymm6,%ymm6 leaq 32(%rdi),%rdi decq %rcx jg L$seal_avx2_tail_384_rounds_and_3xhash decq %r8 jge L$seal_avx2_tail_384_rounds_and_2xhash vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+0(%rsi),%ymm3,%ymm3 vpxor 32+0(%rsi),%ymm2,%ymm2 vpxor 64+0(%rsi),%ymm6,%ymm6 vpxor 96+0(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+0(%rdi) vmovdqu %ymm2,32+0(%rdi) vmovdqu %ymm6,64+0(%rdi) vmovdqu %ymm10,96+0(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm1,%ymm1 vpxor 64+128(%rsi),%ymm5,%ymm5 vpxor 96+128(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm1,32+128(%rdi) vmovdqu %ymm5,64+128(%rdi) vmovdqu %ymm9,96+128(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 movq $256,%rcx leaq 256(%rsi),%rsi subq $256,%rbx jmp L$seal_avx2_short_hash_remainder L$seal_avx2_tail_512: vmovdqa L$chacha20_consts(%rip),%ymm0 vmovdqa 0+64(%rbp),%ymm4 vmovdqa 0+96(%rbp),%ymm8 vmovdqa %ymm0,%ymm1 vmovdqa %ymm4,%ymm5 vmovdqa %ymm8,%ymm9 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm10 vmovdqa %ymm0,%ymm3 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa L$avx2_inc(%rip),%ymm12 vpaddd 0+160(%rbp),%ymm12,%ymm15 vpaddd %ymm15,%ymm12,%ymm14 vpaddd %ymm14,%ymm12,%ymm13 vpaddd %ymm13,%ymm12,%ymm12 vmovdqa %ymm15,0+256(%rbp) vmovdqa %ymm14,0+224(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm12,0+160(%rbp) L$seal_avx2_tail_512_rounds_and_3xhash: addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi L$seal_avx2_tail_512_rounds_and_2xhash: vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $4,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $12,%ymm15,%ymm15,%ymm15 vpalignr $4,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $4,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $4,%ymm4,%ymm4,%ymm4 addq %rax,%r15 adcq %rdx,%r9 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm12,%ymm12,%ymm12 vmovdqa %ymm8,0+128(%rbp) vmovdqa L$rol16(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $20,%ymm7,%ymm8 vpslld $32-20,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $20,%ymm6,%ymm8 vpslld $32-20,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $20,%ymm5,%ymm8 vpslld $32-20,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $20,%ymm4,%ymm8 vpslld $32-20,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa L$rol8(%rip),%ymm8 vpaddd %ymm7,%ymm3,%ymm3 vpaddd %ymm6,%ymm2,%ymm2 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 vpaddd %ymm5,%ymm1,%ymm1 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm3,%ymm15,%ymm15 vpxor %ymm2,%ymm14,%ymm14 vpxor %ymm1,%ymm13,%ymm13 vpxor %ymm0,%ymm12,%ymm12 vpshufb %ymm8,%ymm15,%ymm15 vpshufb %ymm8,%ymm14,%ymm14 vpshufb %ymm8,%ymm13,%ymm13 vpshufb %ymm8,%ymm12,%ymm12 vpaddd %ymm15,%ymm11,%ymm11 vpaddd %ymm14,%ymm10,%ymm10 vpaddd %ymm13,%ymm9,%ymm9 vpaddd 0+128(%rbp),%ymm12,%ymm8 vpxor %ymm11,%ymm7,%ymm7 vpxor %ymm10,%ymm6,%ymm6 vpxor %ymm9,%ymm5,%ymm5 vpxor %ymm8,%ymm4,%ymm4 vmovdqa %ymm8,0+128(%rbp) vpsrld $25,%ymm7,%ymm8 movq 0+0+0(%rbp),%rdx movq %rdx,%r15 mulxq %r10,%r13,%r14 mulxq %r11,%rax,%rdx imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 vpslld $32-25,%ymm7,%ymm7 vpxor %ymm8,%ymm7,%ymm7 vpsrld $25,%ymm6,%ymm8 vpslld $32-25,%ymm6,%ymm6 vpxor %ymm8,%ymm6,%ymm6 vpsrld $25,%ymm5,%ymm8 vpslld $32-25,%ymm5,%ymm5 vpxor %ymm8,%ymm5,%ymm5 vpsrld $25,%ymm4,%ymm8 vpslld $32-25,%ymm4,%ymm4 vpxor %ymm8,%ymm4,%ymm4 vmovdqa 0+128(%rbp),%ymm8 vpalignr $12,%ymm7,%ymm7,%ymm7 vpalignr $8,%ymm11,%ymm11,%ymm11 vpalignr $4,%ymm15,%ymm15,%ymm15 vpalignr $12,%ymm6,%ymm6,%ymm6 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $12,%ymm5,%ymm5,%ymm5 vpalignr $8,%ymm9,%ymm9,%ymm9 movq 8+0+0(%rbp),%rdx mulxq %r10,%r10,%rax addq %r10,%r14 mulxq %r11,%r11,%r9 adcq %r11,%r15 adcq $0,%r9 imulq %r12,%rdx vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $12,%ymm4,%ymm4,%ymm4 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm12,%ymm12,%ymm12 addq %rax,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi decq %rcx jg L$seal_avx2_tail_512_rounds_and_3xhash decq %r8 jge L$seal_avx2_tail_512_rounds_and_2xhash vpaddd L$chacha20_consts(%rip),%ymm3,%ymm3 vpaddd 0+64(%rbp),%ymm7,%ymm7 vpaddd 0+96(%rbp),%ymm11,%ymm11 vpaddd 0+256(%rbp),%ymm15,%ymm15 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd 0+64(%rbp),%ymm6,%ymm6 vpaddd 0+96(%rbp),%ymm10,%ymm10 vpaddd 0+224(%rbp),%ymm14,%ymm14 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd 0+64(%rbp),%ymm5,%ymm5 vpaddd 0+96(%rbp),%ymm9,%ymm9 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd 0+64(%rbp),%ymm4,%ymm4 vpaddd 0+96(%rbp),%ymm8,%ymm8 vpaddd 0+160(%rbp),%ymm12,%ymm12 vmovdqa %ymm0,0+128(%rbp) vperm2i128 $0x02,%ymm3,%ymm7,%ymm0 vperm2i128 $0x13,%ymm3,%ymm7,%ymm7 vperm2i128 $0x02,%ymm11,%ymm15,%ymm3 vperm2i128 $0x13,%ymm11,%ymm15,%ymm11 vpxor 0+0(%rsi),%ymm0,%ymm0 vpxor 32+0(%rsi),%ymm3,%ymm3 vpxor 64+0(%rsi),%ymm7,%ymm7 vpxor 96+0(%rsi),%ymm11,%ymm11 vmovdqu %ymm0,0+0(%rdi) vmovdqu %ymm3,32+0(%rdi) vmovdqu %ymm7,64+0(%rdi) vmovdqu %ymm11,96+0(%rdi) vmovdqa 0+128(%rbp),%ymm0 vperm2i128 $0x02,%ymm2,%ymm6,%ymm3 vperm2i128 $0x13,%ymm2,%ymm6,%ymm6 vperm2i128 $0x02,%ymm10,%ymm14,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm10 vpxor 0+128(%rsi),%ymm3,%ymm3 vpxor 32+128(%rsi),%ymm2,%ymm2 vpxor 64+128(%rsi),%ymm6,%ymm6 vpxor 96+128(%rsi),%ymm10,%ymm10 vmovdqu %ymm3,0+128(%rdi) vmovdqu %ymm2,32+128(%rdi) vmovdqu %ymm6,64+128(%rdi) vmovdqu %ymm10,96+128(%rdi) vperm2i128 $0x02,%ymm1,%ymm5,%ymm3 vperm2i128 $0x13,%ymm1,%ymm5,%ymm5 vperm2i128 $0x02,%ymm9,%ymm13,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm9 vpxor 0+256(%rsi),%ymm3,%ymm3 vpxor 32+256(%rsi),%ymm1,%ymm1 vpxor 64+256(%rsi),%ymm5,%ymm5 vpxor 96+256(%rsi),%ymm9,%ymm9 vmovdqu %ymm3,0+256(%rdi) vmovdqu %ymm1,32+256(%rdi) vmovdqu %ymm5,64+256(%rdi) vmovdqu %ymm9,96+256(%rdi) vperm2i128 $0x13,%ymm0,%ymm4,%ymm3 vperm2i128 $0x02,%ymm0,%ymm4,%ymm0 vperm2i128 $0x02,%ymm8,%ymm12,%ymm4 vperm2i128 $0x13,%ymm8,%ymm12,%ymm12 vmovdqa %ymm3,%ymm8 movq $384,%rcx leaq 384(%rsi),%rsi subq $384,%rbx jmp L$seal_avx2_short_hash_remainder L$seal_avx2_320: vmovdqa %ymm0,%ymm1 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm5 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm9 vmovdqa %ymm8,%ymm10 vpaddd L$avx2_inc(%rip),%ymm12,%ymm13 vpaddd L$avx2_inc(%rip),%ymm13,%ymm14 vmovdqa %ymm4,%ymm7 vmovdqa %ymm8,%ymm11 vmovdqa %ymm12,0+160(%rbp) vmovdqa %ymm13,0+192(%rbp) vmovdqa %ymm14,0+224(%rbp) movq $10,%r10 L$seal_avx2_320_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $12,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $4,%ymm6,%ymm6,%ymm6 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol16(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpsrld $20,%ymm6,%ymm3 vpslld $12,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpaddd %ymm6,%ymm2,%ymm2 vpxor %ymm2,%ymm14,%ymm14 vpshufb L$rol8(%rip),%ymm14,%ymm14 vpaddd %ymm14,%ymm10,%ymm10 vpxor %ymm10,%ymm6,%ymm6 vpslld $7,%ymm6,%ymm3 vpsrld $25,%ymm6,%ymm6 vpxor %ymm3,%ymm6,%ymm6 vpalignr $4,%ymm14,%ymm14,%ymm14 vpalignr $8,%ymm10,%ymm10,%ymm10 vpalignr $12,%ymm6,%ymm6,%ymm6 decq %r10 jne L$seal_avx2_320_rounds vpaddd L$chacha20_consts(%rip),%ymm0,%ymm0 vpaddd L$chacha20_consts(%rip),%ymm1,%ymm1 vpaddd L$chacha20_consts(%rip),%ymm2,%ymm2 vpaddd %ymm7,%ymm4,%ymm4 vpaddd %ymm7,%ymm5,%ymm5 vpaddd %ymm7,%ymm6,%ymm6 vpaddd %ymm11,%ymm8,%ymm8 vpaddd %ymm11,%ymm9,%ymm9 vpaddd %ymm11,%ymm10,%ymm10 vpaddd 0+160(%rbp),%ymm12,%ymm12 vpaddd 0+192(%rbp),%ymm13,%ymm13 vpaddd 0+224(%rbp),%ymm14,%ymm14 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vpand L$clamp(%rip),%ymm3,%ymm3 vmovdqa %ymm3,0+0(%rbp) vperm2i128 $0x13,%ymm0,%ymm4,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm4 vperm2i128 $0x02,%ymm1,%ymm5,%ymm8 vperm2i128 $0x02,%ymm9,%ymm13,%ymm12 vperm2i128 $0x13,%ymm1,%ymm5,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm5 vperm2i128 $0x02,%ymm2,%ymm6,%ymm9 vperm2i128 $0x02,%ymm10,%ymm14,%ymm13 vperm2i128 $0x13,%ymm2,%ymm6,%ymm2 vperm2i128 $0x13,%ymm10,%ymm14,%ymm6 jmp L$seal_avx2_short L$seal_avx2_192: vmovdqa %ymm0,%ymm1 vmovdqa %ymm0,%ymm2 vmovdqa %ymm4,%ymm5 vmovdqa %ymm4,%ymm6 vmovdqa %ymm8,%ymm9 vmovdqa %ymm8,%ymm10 vpaddd L$avx2_inc(%rip),%ymm12,%ymm13 vmovdqa %ymm12,%ymm11 vmovdqa %ymm13,%ymm15 movq $10,%r10 L$seal_avx2_192_rounds: vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $12,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $4,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $12,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $4,%ymm5,%ymm5,%ymm5 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol16(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpsrld $20,%ymm4,%ymm3 vpslld $12,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpaddd %ymm4,%ymm0,%ymm0 vpxor %ymm0,%ymm12,%ymm12 vpshufb L$rol8(%rip),%ymm12,%ymm12 vpaddd %ymm12,%ymm8,%ymm8 vpxor %ymm8,%ymm4,%ymm4 vpslld $7,%ymm4,%ymm3 vpsrld $25,%ymm4,%ymm4 vpxor %ymm3,%ymm4,%ymm4 vpalignr $4,%ymm12,%ymm12,%ymm12 vpalignr $8,%ymm8,%ymm8,%ymm8 vpalignr $12,%ymm4,%ymm4,%ymm4 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol16(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpsrld $20,%ymm5,%ymm3 vpslld $12,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpaddd %ymm5,%ymm1,%ymm1 vpxor %ymm1,%ymm13,%ymm13 vpshufb L$rol8(%rip),%ymm13,%ymm13 vpaddd %ymm13,%ymm9,%ymm9 vpxor %ymm9,%ymm5,%ymm5 vpslld $7,%ymm5,%ymm3 vpsrld $25,%ymm5,%ymm5 vpxor %ymm3,%ymm5,%ymm5 vpalignr $4,%ymm13,%ymm13,%ymm13 vpalignr $8,%ymm9,%ymm9,%ymm9 vpalignr $12,%ymm5,%ymm5,%ymm5 decq %r10 jne L$seal_avx2_192_rounds vpaddd %ymm2,%ymm0,%ymm0 vpaddd %ymm2,%ymm1,%ymm1 vpaddd %ymm6,%ymm4,%ymm4 vpaddd %ymm6,%ymm5,%ymm5 vpaddd %ymm10,%ymm8,%ymm8 vpaddd %ymm10,%ymm9,%ymm9 vpaddd %ymm11,%ymm12,%ymm12 vpaddd %ymm15,%ymm13,%ymm13 vperm2i128 $0x02,%ymm0,%ymm4,%ymm3 vpand L$clamp(%rip),%ymm3,%ymm3 vmovdqa %ymm3,0+0(%rbp) vperm2i128 $0x13,%ymm0,%ymm4,%ymm0 vperm2i128 $0x13,%ymm8,%ymm12,%ymm4 vperm2i128 $0x02,%ymm1,%ymm5,%ymm8 vperm2i128 $0x02,%ymm9,%ymm13,%ymm12 vperm2i128 $0x13,%ymm1,%ymm5,%ymm1 vperm2i128 $0x13,%ymm9,%ymm13,%ymm5 L$seal_avx2_short: movq %r8,%r8 call poly_hash_ad_internal xorq %rcx,%rcx L$seal_avx2_short_hash_remainder: cmpq $16,%rcx jb L$seal_avx2_short_loop addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 subq $16,%rcx addq $16,%rdi jmp L$seal_avx2_short_hash_remainder L$seal_avx2_short_loop: cmpq $32,%rbx jb L$seal_avx2_short_tail subq $32,%rbx vpxor (%rsi),%ymm0,%ymm0 vmovdqu %ymm0,(%rdi) leaq 32(%rsi),%rsi addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 addq 0+16(%rdi),%r10 adcq 8+16(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 32(%rdi),%rdi vmovdqa %ymm4,%ymm0 vmovdqa %ymm8,%ymm4 vmovdqa %ymm12,%ymm8 vmovdqa %ymm1,%ymm12 vmovdqa %ymm5,%ymm1 vmovdqa %ymm9,%ymm5 vmovdqa %ymm13,%ymm9 vmovdqa %ymm2,%ymm13 vmovdqa %ymm6,%ymm2 jmp L$seal_avx2_short_loop L$seal_avx2_short_tail: cmpq $16,%rbx jb L$seal_avx2_exit subq $16,%rbx vpxor (%rsi),%xmm0,%xmm3 vmovdqu %xmm3,(%rdi) leaq 16(%rsi),%rsi addq 0+0(%rdi),%r10 adcq 8+0(%rdi),%r11 adcq $1,%r12 movq 0+0+0(%rbp),%rax movq %rax,%r15 mulq %r10 movq %rax,%r13 movq %rdx,%r14 movq 0+0+0(%rbp),%rax mulq %r11 imulq %r12,%r15 addq %rax,%r14 adcq %rdx,%r15 movq 8+0+0(%rbp),%rax movq %rax,%r9 mulq %r10 addq %rax,%r14 adcq $0,%rdx movq %rdx,%r10 movq 8+0+0(%rbp),%rax mulq %r11 addq %rax,%r15 adcq $0,%rdx imulq %r12,%r9 addq %r10,%r15 adcq %rdx,%r9 movq %r13,%r10 movq %r14,%r11 movq %r15,%r12 andq $3,%r12 movq %r15,%r13 andq $-4,%r13 movq %r9,%r14 shrdq $2,%r9,%r15 shrq $2,%r9 addq %r13,%r15 adcq %r14,%r9 addq %r15,%r10 adcq %r9,%r11 adcq $0,%r12 leaq 16(%rdi),%rdi vextracti128 $1,%ymm0,%xmm0 L$seal_avx2_exit: vzeroupper jmp L$seal_sse_tail_16 #endif

j4yc3-mw/Viren

8,262

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/aesv8-armx-ios64.S

// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(__APPLE__) #include <ring-core/arm_arch.h> #if __ARM_MAX_ARCH__>=7 .text .section __TEXT,__const .align 5 Lrcon: .long 0x01,0x01,0x01,0x01 .long 0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d // rotate-n-splat .long 0x1b,0x1b,0x1b,0x1b .text .globl _aes_hw_set_encrypt_key .private_extern _aes_hw_set_encrypt_key .align 5 _aes_hw_set_encrypt_key: Lenc_key: // Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later. AARCH64_VALID_CALL_TARGET stp x29,x30,[sp,#-16]! add x29,sp,#0 mov x3,#-1 cmp x0,#0 b.eq Lenc_key_abort cmp x2,#0 b.eq Lenc_key_abort mov x3,#-2 cmp w1,#128 b.lt Lenc_key_abort cmp w1,#256 b.gt Lenc_key_abort tst w1,#0x3f b.ne Lenc_key_abort adrp x3,Lrcon@PAGE add x3,x3,Lrcon@PAGEOFF cmp w1,#192 eor v0.16b,v0.16b,v0.16b ld1 {v3.16b},[x0],#16 mov w1,#8 // reuse w1 ld1 {v1.4s,v2.4s},[x3],#32 b.lt Loop128 // 192-bit key support was removed. b L256 .align 4 Loop128: tbl v6.16b,{v3.16b},v2.16b ext v5.16b,v0.16b,v3.16b,#12 st1 {v3.4s},[x2],#16 aese v6.16b,v0.16b subs w1,w1,#1 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v6.16b,v6.16b,v1.16b eor v3.16b,v3.16b,v5.16b shl v1.16b,v1.16b,#1 eor v3.16b,v3.16b,v6.16b b.ne Loop128 ld1 {v1.4s},[x3] tbl v6.16b,{v3.16b},v2.16b ext v5.16b,v0.16b,v3.16b,#12 st1 {v3.4s},[x2],#16 aese v6.16b,v0.16b eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v6.16b,v6.16b,v1.16b eor v3.16b,v3.16b,v5.16b shl v1.16b,v1.16b,#1 eor v3.16b,v3.16b,v6.16b tbl v6.16b,{v3.16b},v2.16b ext v5.16b,v0.16b,v3.16b,#12 st1 {v3.4s},[x2],#16 aese v6.16b,v0.16b eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v6.16b,v6.16b,v1.16b eor v3.16b,v3.16b,v5.16b eor v3.16b,v3.16b,v6.16b st1 {v3.4s},[x2] add x2,x2,#0x50 mov w12,#10 b Ldone // 192-bit key support was removed. .align 4 L256: ld1 {v4.16b},[x0] mov w1,#7 mov w12,#14 st1 {v3.4s},[x2],#16 Loop256: tbl v6.16b,{v4.16b},v2.16b ext v5.16b,v0.16b,v3.16b,#12 st1 {v4.4s},[x2],#16 aese v6.16b,v0.16b subs w1,w1,#1 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v3.16b,v3.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v6.16b,v6.16b,v1.16b eor v3.16b,v3.16b,v5.16b shl v1.16b,v1.16b,#1 eor v3.16b,v3.16b,v6.16b st1 {v3.4s},[x2],#16 b.eq Ldone dup v6.4s,v3.s[3] // just splat ext v5.16b,v0.16b,v4.16b,#12 aese v6.16b,v0.16b eor v4.16b,v4.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v4.16b,v4.16b,v5.16b ext v5.16b,v0.16b,v5.16b,#12 eor v4.16b,v4.16b,v5.16b eor v4.16b,v4.16b,v6.16b b Loop256 Ldone: str w12,[x2] mov x3,#0 Lenc_key_abort: mov x0,x3 // return value ldr x29,[sp],#16 ret .globl _aes_hw_encrypt .private_extern _aes_hw_encrypt .align 5 _aes_hw_encrypt: AARCH64_VALID_CALL_TARGET ldr w3,[x2,#240] ld1 {v0.4s},[x2],#16 ld1 {v2.16b},[x0] sub w3,w3,#2 ld1 {v1.4s},[x2],#16 Loop_enc: aese v2.16b,v0.16b aesmc v2.16b,v2.16b ld1 {v0.4s},[x2],#16 subs w3,w3,#2 aese v2.16b,v1.16b aesmc v2.16b,v2.16b ld1 {v1.4s},[x2],#16 b.gt Loop_enc aese v2.16b,v0.16b aesmc v2.16b,v2.16b ld1 {v0.4s},[x2] aese v2.16b,v1.16b eor v2.16b,v2.16b,v0.16b st1 {v2.16b},[x1] ret .globl _aes_hw_ctr32_encrypt_blocks .private_extern _aes_hw_ctr32_encrypt_blocks .align 5 _aes_hw_ctr32_encrypt_blocks: // Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later. AARCH64_VALID_CALL_TARGET stp x29,x30,[sp,#-16]! add x29,sp,#0 ldr w5,[x3,#240] ldr w8, [x4, #12] ld1 {v0.4s},[x4] ld1 {v16.4s,v17.4s},[x3] // load key schedule... sub w5,w5,#4 mov x12,#16 cmp x2,#2 add x7,x3,x5,lsl#4 // pointer to last 5 round keys sub w5,w5,#2 ld1 {v20.4s,v21.4s},[x7],#32 ld1 {v22.4s,v23.4s},[x7],#32 ld1 {v7.4s},[x7] add x7,x3,#32 mov w6,w5 csel x12,xzr,x12,lo // ARM Cortex-A57 and Cortex-A72 cores running in 32-bit mode are // affected by silicon errata #1742098 [0] and #1655431 [1], // respectively, where the second instruction of an aese/aesmc // instruction pair may execute twice if an interrupt is taken right // after the first instruction consumes an input register of which a // single 32-bit lane has been updated the last time it was modified. // // This function uses a counter in one 32-bit lane. The vmov lines // could write to v1.16b and v18.16b directly, but that trips this bugs. // We write to v6.16b and copy to the final register as a workaround. // // [0] ARM-EPM-049219 v23 Cortex-A57 MPCore Software Developers Errata Notice // [1] ARM-EPM-012079 v11.0 Cortex-A72 MPCore Software Developers Errata Notice #ifndef __AARCH64EB__ rev w8, w8 #endif add w10, w8, #1 orr v6.16b,v0.16b,v0.16b rev w10, w10 mov v6.s[3],w10 add w8, w8, #2 orr v1.16b,v6.16b,v6.16b b.ls Lctr32_tail rev w12, w8 mov v6.s[3],w12 sub x2,x2,#3 // bias orr v18.16b,v6.16b,v6.16b b Loop3x_ctr32 .align 4 Loop3x_ctr32: aese v0.16b,v16.16b aesmc v0.16b,v0.16b aese v1.16b,v16.16b aesmc v1.16b,v1.16b aese v18.16b,v16.16b aesmc v18.16b,v18.16b ld1 {v16.4s},[x7],#16 subs w6,w6,#2 aese v0.16b,v17.16b aesmc v0.16b,v0.16b aese v1.16b,v17.16b aesmc v1.16b,v1.16b aese v18.16b,v17.16b aesmc v18.16b,v18.16b ld1 {v17.4s},[x7],#16 b.gt Loop3x_ctr32 aese v0.16b,v16.16b aesmc v4.16b,v0.16b aese v1.16b,v16.16b aesmc v5.16b,v1.16b ld1 {v2.16b},[x0],#16 add w9,w8,#1 aese v18.16b,v16.16b aesmc v18.16b,v18.16b ld1 {v3.16b},[x0],#16 rev w9,w9 aese v4.16b,v17.16b aesmc v4.16b,v4.16b aese v5.16b,v17.16b aesmc v5.16b,v5.16b ld1 {v19.16b},[x0],#16 mov x7,x3 aese v18.16b,v17.16b aesmc v17.16b,v18.16b aese v4.16b,v20.16b aesmc v4.16b,v4.16b aese v5.16b,v20.16b aesmc v5.16b,v5.16b eor v2.16b,v2.16b,v7.16b add w10,w8,#2 aese v17.16b,v20.16b aesmc v17.16b,v17.16b eor v3.16b,v3.16b,v7.16b add w8,w8,#3 aese v4.16b,v21.16b aesmc v4.16b,v4.16b aese v5.16b,v21.16b aesmc v5.16b,v5.16b // Note the logic to update v0.16b, v1.16b, and v1.16b is written to work // around a bug in ARM Cortex-A57 and Cortex-A72 cores running in // 32-bit mode. See the comment above. eor v19.16b,v19.16b,v7.16b mov v6.s[3], w9 aese v17.16b,v21.16b aesmc v17.16b,v17.16b orr v0.16b,v6.16b,v6.16b rev w10,w10 aese v4.16b,v22.16b aesmc v4.16b,v4.16b mov v6.s[3], w10 rev w12,w8 aese v5.16b,v22.16b aesmc v5.16b,v5.16b orr v1.16b,v6.16b,v6.16b mov v6.s[3], w12 aese v17.16b,v22.16b aesmc v17.16b,v17.16b orr v18.16b,v6.16b,v6.16b subs x2,x2,#3 aese v4.16b,v23.16b aese v5.16b,v23.16b aese v17.16b,v23.16b eor v2.16b,v2.16b,v4.16b ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0] st1 {v2.16b},[x1],#16 eor v3.16b,v3.16b,v5.16b mov w6,w5 st1 {v3.16b},[x1],#16 eor v19.16b,v19.16b,v17.16b ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1] st1 {v19.16b},[x1],#16 b.hs Loop3x_ctr32 adds x2,x2,#3 b.eq Lctr32_done cmp x2,#1 mov x12,#16 csel x12,xzr,x12,eq Lctr32_tail: aese v0.16b,v16.16b aesmc v0.16b,v0.16b aese v1.16b,v16.16b aesmc v1.16b,v1.16b ld1 {v16.4s},[x7],#16 subs w6,w6,#2 aese v0.16b,v17.16b aesmc v0.16b,v0.16b aese v1.16b,v17.16b aesmc v1.16b,v1.16b ld1 {v17.4s},[x7],#16 b.gt Lctr32_tail aese v0.16b,v16.16b aesmc v0.16b,v0.16b aese v1.16b,v16.16b aesmc v1.16b,v1.16b aese v0.16b,v17.16b aesmc v0.16b,v0.16b aese v1.16b,v17.16b aesmc v1.16b,v1.16b ld1 {v2.16b},[x0],x12 aese v0.16b,v20.16b aesmc v0.16b,v0.16b aese v1.16b,v20.16b aesmc v1.16b,v1.16b ld1 {v3.16b},[x0] aese v0.16b,v21.16b aesmc v0.16b,v0.16b aese v1.16b,v21.16b aesmc v1.16b,v1.16b eor v2.16b,v2.16b,v7.16b aese v0.16b,v22.16b aesmc v0.16b,v0.16b aese v1.16b,v22.16b aesmc v1.16b,v1.16b eor v3.16b,v3.16b,v7.16b aese v0.16b,v23.16b aese v1.16b,v23.16b cmp x2,#1 eor v2.16b,v2.16b,v0.16b eor v3.16b,v3.16b,v1.16b st1 {v2.16b},[x1],#16 b.eq Lctr32_done st1 {v3.16b},[x1] Lctr32_done: ldr x29,[sp],#16 ret #endif #endif // !OPENSSL_NO_ASM && defined(OPENSSL_AARCH64) && defined(__APPLE__)

j4yc3-mw/Viren

43,302

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/sha512-armv4-linux32.S

// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__) @ Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved. @ @ Licensed under the OpenSSL license (the "License"). You may not use @ this file except in compliance with the License. You can obtain a copy @ in the file LICENSE in the source distribution or at @ https://www.openssl.org/source/license.html @ ==================================================================== @ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL @ project. The module is, however, dual licensed under OpenSSL and @ CRYPTOGAMS licenses depending on where you obtain it. For further @ details see http://www.openssl.org/~appro/cryptogams/. @ @ Permission to use under GPL terms is granted. @ ==================================================================== @ SHA512 block procedure for ARMv4. September 2007. @ This code is ~4.5 (four and a half) times faster than code generated @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue @ Xscale PXA250 core]. @ @ July 2010. @ @ Rescheduling for dual-issue pipeline resulted in 6% improvement on @ Cortex A8 core and ~40 cycles per processed byte. @ February 2011. @ @ Profiler-assisted and platform-specific optimization resulted in 7% @ improvement on Coxtex A8 core and ~38 cycles per byte. @ March 2011. @ @ Add NEON implementation. On Cortex A8 it was measured to process @ one byte in 23.3 cycles or ~60% faster than integer-only code. @ August 2012. @ @ Improve NEON performance by 12% on Snapdragon S4. In absolute @ terms it's 22.6 cycles per byte, which is disappointing result. @ Technical writers asserted that 3-way S4 pipeline can sustain @ multiple NEON instructions per cycle, but dual NEON issue could @ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html @ for further details. On side note Cortex-A15 processes one byte in @ 16 cycles. @ Byte order [in]dependence. ========================================= @ @ Originally caller was expected to maintain specific *dword* order in @ h[0-7], namely with most significant dword at *lower* address, which @ was reflected in below two parameters as 0 and 4. Now caller is @ expected to maintain native byte order for whole 64-bit values. #ifndef __KERNEL__ # include <ring-core/arm_arch.h> # define VFP_ABI_PUSH vstmdb sp!,{d8-d15} # define VFP_ABI_POP vldmia sp!,{d8-d15} #else # define __ARM_ARCH__ __LINUX_ARM_ARCH__ # define __ARM_MAX_ARCH__ 7 # define VFP_ABI_PUSH # define VFP_ABI_POP #endif @ Silence ARMv8 deprecated IT instruction warnings. This file is used by both @ ARMv7 and ARMv8 processors and does not use ARMv8 instructions. .arch armv7-a #ifdef __ARMEL__ # define LO 0 # define HI 4 # define WORD64(hi0,lo0,hi1,lo1) .word lo0,hi0, lo1,hi1 #else # define HI 0 # define LO 4 # define WORD64(hi0,lo0,hi1,lo1) .word hi0,lo0, hi1,lo1 #endif .text #if defined(__thumb2__) .syntax unified .thumb # define adrl adr #else .code 32 #endif .type K512,%object .align 5 K512: WORD64(0x428a2f98,0xd728ae22, 0x71374491,0x23ef65cd) WORD64(0xb5c0fbcf,0xec4d3b2f, 0xe9b5dba5,0x8189dbbc) WORD64(0x3956c25b,0xf348b538, 0x59f111f1,0xb605d019) WORD64(0x923f82a4,0xaf194f9b, 0xab1c5ed5,0xda6d8118) WORD64(0xd807aa98,0xa3030242, 0x12835b01,0x45706fbe) WORD64(0x243185be,0x4ee4b28c, 0x550c7dc3,0xd5ffb4e2) WORD64(0x72be5d74,0xf27b896f, 0x80deb1fe,0x3b1696b1) WORD64(0x9bdc06a7,0x25c71235, 0xc19bf174,0xcf692694) WORD64(0xe49b69c1,0x9ef14ad2, 0xefbe4786,0x384f25e3) WORD64(0x0fc19dc6,0x8b8cd5b5, 0x240ca1cc,0x77ac9c65) WORD64(0x2de92c6f,0x592b0275, 0x4a7484aa,0x6ea6e483) WORD64(0x5cb0a9dc,0xbd41fbd4, 0x76f988da,0x831153b5) WORD64(0x983e5152,0xee66dfab, 0xa831c66d,0x2db43210) WORD64(0xb00327c8,0x98fb213f, 0xbf597fc7,0xbeef0ee4) WORD64(0xc6e00bf3,0x3da88fc2, 0xd5a79147,0x930aa725) WORD64(0x06ca6351,0xe003826f, 0x14292967,0x0a0e6e70) WORD64(0x27b70a85,0x46d22ffc, 0x2e1b2138,0x5c26c926) WORD64(0x4d2c6dfc,0x5ac42aed, 0x53380d13,0x9d95b3df) WORD64(0x650a7354,0x8baf63de, 0x766a0abb,0x3c77b2a8) WORD64(0x81c2c92e,0x47edaee6, 0x92722c85,0x1482353b) WORD64(0xa2bfe8a1,0x4cf10364, 0xa81a664b,0xbc423001) WORD64(0xc24b8b70,0xd0f89791, 0xc76c51a3,0x0654be30) WORD64(0xd192e819,0xd6ef5218, 0xd6990624,0x5565a910) WORD64(0xf40e3585,0x5771202a, 0x106aa070,0x32bbd1b8) WORD64(0x19a4c116,0xb8d2d0c8, 0x1e376c08,0x5141ab53) WORD64(0x2748774c,0xdf8eeb99, 0x34b0bcb5,0xe19b48a8) WORD64(0x391c0cb3,0xc5c95a63, 0x4ed8aa4a,0xe3418acb) WORD64(0x5b9cca4f,0x7763e373, 0x682e6ff3,0xd6b2b8a3) WORD64(0x748f82ee,0x5defb2fc, 0x78a5636f,0x43172f60) WORD64(0x84c87814,0xa1f0ab72, 0x8cc70208,0x1a6439ec) WORD64(0x90befffa,0x23631e28, 0xa4506ceb,0xde82bde9) WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b) WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207) WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178) WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6) WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b) WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493) WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c) WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a) WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817) .size K512,.-K512 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) .hidden OPENSSL_armcap_P .LOPENSSL_armcap: .word OPENSSL_armcap_P-.Lsha512_block_data_order .skip 32-4 #else .skip 32 #endif .globl sha512_block_data_order .hidden sha512_block_data_order .type sha512_block_data_order,%function sha512_block_data_order: .Lsha512_block_data_order: #if __ARM_ARCH__<7 && !defined(__thumb2__) sub r3,pc,#8 @ sha512_block_data_order #else adr r3,.Lsha512_block_data_order #endif #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) ldr r12,.LOPENSSL_armcap ldr r12,[r3,r12] @ OPENSSL_armcap_P #ifdef __APPLE__ ldr r12,[r12] #endif tst r12,#ARMV7_NEON bne .LNEON #endif add r2,r1,r2,lsl#7 @ len to point at the end of inp stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} sub r14,r3,#672 @ K512 sub sp,sp,#9*8 ldr r7,[r0,#32+LO] ldr r8,[r0,#32+HI] ldr r9, [r0,#48+LO] ldr r10, [r0,#48+HI] ldr r11, [r0,#56+LO] ldr r12, [r0,#56+HI] .Loop: str r9, [sp,#48+0] str r10, [sp,#48+4] str r11, [sp,#56+0] str r12, [sp,#56+4] ldr r5,[r0,#0+LO] ldr r6,[r0,#0+HI] ldr r3,[r0,#8+LO] ldr r4,[r0,#8+HI] ldr r9, [r0,#16+LO] ldr r10, [r0,#16+HI] ldr r11, [r0,#24+LO] ldr r12, [r0,#24+HI] str r3,[sp,#8+0] str r4,[sp,#8+4] str r9, [sp,#16+0] str r10, [sp,#16+4] str r11, [sp,#24+0] str r12, [sp,#24+4] ldr r3,[r0,#40+LO] ldr r4,[r0,#40+HI] str r3,[sp,#40+0] str r4,[sp,#40+4] .L00_15: #if __ARM_ARCH__<7 ldrb r3,[r1,#7] ldrb r9, [r1,#6] ldrb r10, [r1,#5] ldrb r11, [r1,#4] ldrb r4,[r1,#3] ldrb r12, [r1,#2] orr r3,r3,r9,lsl#8 ldrb r9, [r1,#1] orr r3,r3,r10,lsl#16 ldrb r10, [r1],#8 orr r3,r3,r11,lsl#24 orr r4,r4,r12,lsl#8 orr r4,r4,r9,lsl#16 orr r4,r4,r10,lsl#24 #else ldr r3,[r1,#4] ldr r4,[r1],#8 #ifdef __ARMEL__ rev r3,r3 rev r4,r4 #endif #endif @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 mov r9,r7,lsr#14 str r3,[sp,#64+0] mov r10,r8,lsr#14 str r4,[sp,#64+4] eor r9,r9,r8,lsl#18 ldr r11,[sp,#56+0] @ h.lo eor r10,r10,r7,lsl#18 ldr r12,[sp,#56+4] @ h.hi eor r9,r9,r7,lsr#18 eor r10,r10,r8,lsr#18 eor r9,r9,r8,lsl#14 eor r10,r10,r7,lsl#14 eor r9,r9,r8,lsr#9 eor r10,r10,r7,lsr#9 eor r9,r9,r7,lsl#23 eor r10,r10,r8,lsl#23 @ Sigma1(e) adds r3,r3,r9 ldr r9,[sp,#40+0] @ f.lo adc r4,r4,r10 @ T += Sigma1(e) ldr r10,[sp,#40+4] @ f.hi adds r3,r3,r11 ldr r11,[sp,#48+0] @ g.lo adc r4,r4,r12 @ T += h ldr r12,[sp,#48+4] @ g.hi eor r9,r9,r11 str r7,[sp,#32+0] eor r10,r10,r12 str r8,[sp,#32+4] and r9,r9,r7 str r5,[sp,#0+0] and r10,r10,r8 str r6,[sp,#0+4] eor r9,r9,r11 ldr r11,[r14,#LO] @ K[i].lo eor r10,r10,r12 @ Ch(e,f,g) ldr r12,[r14,#HI] @ K[i].hi adds r3,r3,r9 ldr r7,[sp,#24+0] @ d.lo adc r4,r4,r10 @ T += Ch(e,f,g) ldr r8,[sp,#24+4] @ d.hi adds r3,r3,r11 and r9,r11,#0xff adc r4,r4,r12 @ T += K[i] adds r7,r7,r3 ldr r11,[sp,#8+0] @ b.lo adc r8,r8,r4 @ d += T teq r9,#148 ldr r12,[sp,#16+0] @ c.lo #if __ARM_ARCH__>=7 it eq @ Thumb2 thing, sanity check in ARM #endif orreq r14,r14,#1 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 mov r9,r5,lsr#28 mov r10,r6,lsr#28 eor r9,r9,r6,lsl#4 eor r10,r10,r5,lsl#4 eor r9,r9,r6,lsr#2 eor r10,r10,r5,lsr#2 eor r9,r9,r5,lsl#30 eor r10,r10,r6,lsl#30 eor r9,r9,r6,lsr#7 eor r10,r10,r5,lsr#7 eor r9,r9,r5,lsl#25 eor r10,r10,r6,lsl#25 @ Sigma0(a) adds r3,r3,r9 and r9,r5,r11 adc r4,r4,r10 @ T += Sigma0(a) ldr r10,[sp,#8+4] @ b.hi orr r5,r5,r11 ldr r11,[sp,#16+4] @ c.hi and r5,r5,r12 and r12,r6,r10 orr r6,r6,r10 orr r5,r5,r9 @ Maj(a,b,c).lo and r6,r6,r11 adds r5,r5,r3 orr r6,r6,r12 @ Maj(a,b,c).hi sub sp,sp,#8 adc r6,r6,r4 @ h += T tst r14,#1 add r14,r14,#8 tst r14,#1 beq .L00_15 ldr r9,[sp,#184+0] ldr r10,[sp,#184+4] bic r14,r14,#1 .L16_79: @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7)) @ LO lo>>1^hi<<31 ^ lo>>8^hi<<24 ^ lo>>7^hi<<25 @ HI hi>>1^lo<<31 ^ hi>>8^lo<<24 ^ hi>>7 mov r3,r9,lsr#1 ldr r11,[sp,#80+0] mov r4,r10,lsr#1 ldr r12,[sp,#80+4] eor r3,r3,r10,lsl#31 eor r4,r4,r9,lsl#31 eor r3,r3,r9,lsr#8 eor r4,r4,r10,lsr#8 eor r3,r3,r10,lsl#24 eor r4,r4,r9,lsl#24 eor r3,r3,r9,lsr#7 eor r4,r4,r10,lsr#7 eor r3,r3,r10,lsl#25 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)) @ LO lo>>19^hi<<13 ^ hi>>29^lo<<3 ^ lo>>6^hi<<26 @ HI hi>>19^lo<<13 ^ lo>>29^hi<<3 ^ hi>>6 mov r9,r11,lsr#19 mov r10,r12,lsr#19 eor r9,r9,r12,lsl#13 eor r10,r10,r11,lsl#13 eor r9,r9,r12,lsr#29 eor r10,r10,r11,lsr#29 eor r9,r9,r11,lsl#3 eor r10,r10,r12,lsl#3 eor r9,r9,r11,lsr#6 eor r10,r10,r12,lsr#6 ldr r11,[sp,#120+0] eor r9,r9,r12,lsl#26 ldr r12,[sp,#120+4] adds r3,r3,r9 ldr r9,[sp,#192+0] adc r4,r4,r10 ldr r10,[sp,#192+4] adds r3,r3,r11 adc r4,r4,r12 adds r3,r3,r9 adc r4,r4,r10 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 mov r9,r7,lsr#14 str r3,[sp,#64+0] mov r10,r8,lsr#14 str r4,[sp,#64+4] eor r9,r9,r8,lsl#18 ldr r11,[sp,#56+0] @ h.lo eor r10,r10,r7,lsl#18 ldr r12,[sp,#56+4] @ h.hi eor r9,r9,r7,lsr#18 eor r10,r10,r8,lsr#18 eor r9,r9,r8,lsl#14 eor r10,r10,r7,lsl#14 eor r9,r9,r8,lsr#9 eor r10,r10,r7,lsr#9 eor r9,r9,r7,lsl#23 eor r10,r10,r8,lsl#23 @ Sigma1(e) adds r3,r3,r9 ldr r9,[sp,#40+0] @ f.lo adc r4,r4,r10 @ T += Sigma1(e) ldr r10,[sp,#40+4] @ f.hi adds r3,r3,r11 ldr r11,[sp,#48+0] @ g.lo adc r4,r4,r12 @ T += h ldr r12,[sp,#48+4] @ g.hi eor r9,r9,r11 str r7,[sp,#32+0] eor r10,r10,r12 str r8,[sp,#32+4] and r9,r9,r7 str r5,[sp,#0+0] and r10,r10,r8 str r6,[sp,#0+4] eor r9,r9,r11 ldr r11,[r14,#LO] @ K[i].lo eor r10,r10,r12 @ Ch(e,f,g) ldr r12,[r14,#HI] @ K[i].hi adds r3,r3,r9 ldr r7,[sp,#24+0] @ d.lo adc r4,r4,r10 @ T += Ch(e,f,g) ldr r8,[sp,#24+4] @ d.hi adds r3,r3,r11 and r9,r11,#0xff adc r4,r4,r12 @ T += K[i] adds r7,r7,r3 ldr r11,[sp,#8+0] @ b.lo adc r8,r8,r4 @ d += T teq r9,#23 ldr r12,[sp,#16+0] @ c.lo #if __ARM_ARCH__>=7 it eq @ Thumb2 thing, sanity check in ARM #endif orreq r14,r14,#1 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 mov r9,r5,lsr#28 mov r10,r6,lsr#28 eor r9,r9,r6,lsl#4 eor r10,r10,r5,lsl#4 eor r9,r9,r6,lsr#2 eor r10,r10,r5,lsr#2 eor r9,r9,r5,lsl#30 eor r10,r10,r6,lsl#30 eor r9,r9,r6,lsr#7 eor r10,r10,r5,lsr#7 eor r9,r9,r5,lsl#25 eor r10,r10,r6,lsl#25 @ Sigma0(a) adds r3,r3,r9 and r9,r5,r11 adc r4,r4,r10 @ T += Sigma0(a) ldr r10,[sp,#8+4] @ b.hi orr r5,r5,r11 ldr r11,[sp,#16+4] @ c.hi and r5,r5,r12 and r12,r6,r10 orr r6,r6,r10 orr r5,r5,r9 @ Maj(a,b,c).lo and r6,r6,r11 adds r5,r5,r3 orr r6,r6,r12 @ Maj(a,b,c).hi sub sp,sp,#8 adc r6,r6,r4 @ h += T tst r14,#1 add r14,r14,#8 #if __ARM_ARCH__>=7 ittt eq @ Thumb2 thing, sanity check in ARM #endif ldreq r9,[sp,#184+0] ldreq r10,[sp,#184+4] beq .L16_79 bic r14,r14,#1 ldr r3,[sp,#8+0] ldr r4,[sp,#8+4] ldr r9, [r0,#0+LO] ldr r10, [r0,#0+HI] ldr r11, [r0,#8+LO] ldr r12, [r0,#8+HI] adds r9,r5,r9 str r9, [r0,#0+LO] adc r10,r6,r10 str r10, [r0,#0+HI] adds r11,r3,r11 str r11, [r0,#8+LO] adc r12,r4,r12 str r12, [r0,#8+HI] ldr r5,[sp,#16+0] ldr r6,[sp,#16+4] ldr r3,[sp,#24+0] ldr r4,[sp,#24+4] ldr r9, [r0,#16+LO] ldr r10, [r0,#16+HI] ldr r11, [r0,#24+LO] ldr r12, [r0,#24+HI] adds r9,r5,r9 str r9, [r0,#16+LO] adc r10,r6,r10 str r10, [r0,#16+HI] adds r11,r3,r11 str r11, [r0,#24+LO] adc r12,r4,r12 str r12, [r0,#24+HI] ldr r3,[sp,#40+0] ldr r4,[sp,#40+4] ldr r9, [r0,#32+LO] ldr r10, [r0,#32+HI] ldr r11, [r0,#40+LO] ldr r12, [r0,#40+HI] adds r7,r7,r9 str r7,[r0,#32+LO] adc r8,r8,r10 str r8,[r0,#32+HI] adds r11,r3,r11 str r11, [r0,#40+LO] adc r12,r4,r12 str r12, [r0,#40+HI] ldr r5,[sp,#48+0] ldr r6,[sp,#48+4] ldr r3,[sp,#56+0] ldr r4,[sp,#56+4] ldr r9, [r0,#48+LO] ldr r10, [r0,#48+HI] ldr r11, [r0,#56+LO] ldr r12, [r0,#56+HI] adds r9,r5,r9 str r9, [r0,#48+LO] adc r10,r6,r10 str r10, [r0,#48+HI] adds r11,r3,r11 str r11, [r0,#56+LO] adc r12,r4,r12 str r12, [r0,#56+HI] add sp,sp,#640 sub r14,r14,#640 teq r1,r2 bne .Loop add sp,sp,#8*9 @ destroy frame #if __ARM_ARCH__>=5 ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc} #else ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} tst lr,#1 moveq pc,lr @ be binary compatible with V4, yet .word 0xe12fff1e @ interoperable with Thumb ISA:-) #endif .size sha512_block_data_order,.-sha512_block_data_order #if __ARM_MAX_ARCH__>=7 .arch armv7-a .fpu neon .type sha512_block_data_order_neon,%function .align 4 sha512_block_data_order_neon: .LNEON: dmb @ errata #451034 on early Cortex A8 add r2,r1,r2,lsl#7 @ len to point at the end of inp adr r3,K512 VFP_ABI_PUSH vldmia r0,{d16,d17,d18,d19,d20,d21,d22,d23} @ load context .Loop_neon: vshr.u64 d24,d20,#14 @ 0 #if 0<16 vld1.64 {d0},[r1]! @ handles unaligned #endif vshr.u64 d25,d20,#18 #if 0>0 vadd.i64 d16,d30 @ h+=Maj from the past #endif vshr.u64 d26,d20,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d20,#50 vsli.64 d25,d20,#46 vmov d29,d20 vsli.64 d26,d20,#23 #if 0<16 && defined(__ARMEL__) vrev64.8 d0,d0 #endif veor d25,d24 vbsl d29,d21,d22 @ Ch(e,f,g) vshr.u64 d24,d16,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d23 vshr.u64 d25,d16,#34 vsli.64 d24,d16,#36 vadd.i64 d27,d26 vshr.u64 d26,d16,#39 vadd.i64 d28,d0 vsli.64 d25,d16,#30 veor d30,d16,d17 vsli.64 d26,d16,#25 veor d23,d24,d25 vadd.i64 d27,d28 vbsl d30,d18,d17 @ Maj(a,b,c) veor d23,d26 @ Sigma0(a) vadd.i64 d19,d27 vadd.i64 d30,d27 @ vadd.i64 d23,d30 vshr.u64 d24,d19,#14 @ 1 #if 1<16 vld1.64 {d1},[r1]! @ handles unaligned #endif vshr.u64 d25,d19,#18 #if 1>0 vadd.i64 d23,d30 @ h+=Maj from the past #endif vshr.u64 d26,d19,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d19,#50 vsli.64 d25,d19,#46 vmov d29,d19 vsli.64 d26,d19,#23 #if 1<16 && defined(__ARMEL__) vrev64.8 d1,d1 #endif veor d25,d24 vbsl d29,d20,d21 @ Ch(e,f,g) vshr.u64 d24,d23,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d22 vshr.u64 d25,d23,#34 vsli.64 d24,d23,#36 vadd.i64 d27,d26 vshr.u64 d26,d23,#39 vadd.i64 d28,d1 vsli.64 d25,d23,#30 veor d30,d23,d16 vsli.64 d26,d23,#25 veor d22,d24,d25 vadd.i64 d27,d28 vbsl d30,d17,d16 @ Maj(a,b,c) veor d22,d26 @ Sigma0(a) vadd.i64 d18,d27 vadd.i64 d30,d27 @ vadd.i64 d22,d30 vshr.u64 d24,d18,#14 @ 2 #if 2<16 vld1.64 {d2},[r1]! @ handles unaligned #endif vshr.u64 d25,d18,#18 #if 2>0 vadd.i64 d22,d30 @ h+=Maj from the past #endif vshr.u64 d26,d18,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d18,#50 vsli.64 d25,d18,#46 vmov d29,d18 vsli.64 d26,d18,#23 #if 2<16 && defined(__ARMEL__) vrev64.8 d2,d2 #endif veor d25,d24 vbsl d29,d19,d20 @ Ch(e,f,g) vshr.u64 d24,d22,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d21 vshr.u64 d25,d22,#34 vsli.64 d24,d22,#36 vadd.i64 d27,d26 vshr.u64 d26,d22,#39 vadd.i64 d28,d2 vsli.64 d25,d22,#30 veor d30,d22,d23 vsli.64 d26,d22,#25 veor d21,d24,d25 vadd.i64 d27,d28 vbsl d30,d16,d23 @ Maj(a,b,c) veor d21,d26 @ Sigma0(a) vadd.i64 d17,d27 vadd.i64 d30,d27 @ vadd.i64 d21,d30 vshr.u64 d24,d17,#14 @ 3 #if 3<16 vld1.64 {d3},[r1]! @ handles unaligned #endif vshr.u64 d25,d17,#18 #if 3>0 vadd.i64 d21,d30 @ h+=Maj from the past #endif vshr.u64 d26,d17,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d17,#50 vsli.64 d25,d17,#46 vmov d29,d17 vsli.64 d26,d17,#23 #if 3<16 && defined(__ARMEL__) vrev64.8 d3,d3 #endif veor d25,d24 vbsl d29,d18,d19 @ Ch(e,f,g) vshr.u64 d24,d21,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d20 vshr.u64 d25,d21,#34 vsli.64 d24,d21,#36 vadd.i64 d27,d26 vshr.u64 d26,d21,#39 vadd.i64 d28,d3 vsli.64 d25,d21,#30 veor d30,d21,d22 vsli.64 d26,d21,#25 veor d20,d24,d25 vadd.i64 d27,d28 vbsl d30,d23,d22 @ Maj(a,b,c) veor d20,d26 @ Sigma0(a) vadd.i64 d16,d27 vadd.i64 d30,d27 @ vadd.i64 d20,d30 vshr.u64 d24,d16,#14 @ 4 #if 4<16 vld1.64 {d4},[r1]! @ handles unaligned #endif vshr.u64 d25,d16,#18 #if 4>0 vadd.i64 d20,d30 @ h+=Maj from the past #endif vshr.u64 d26,d16,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d16,#50 vsli.64 d25,d16,#46 vmov d29,d16 vsli.64 d26,d16,#23 #if 4<16 && defined(__ARMEL__) vrev64.8 d4,d4 #endif veor d25,d24 vbsl d29,d17,d18 @ Ch(e,f,g) vshr.u64 d24,d20,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d19 vshr.u64 d25,d20,#34 vsli.64 d24,d20,#36 vadd.i64 d27,d26 vshr.u64 d26,d20,#39 vadd.i64 d28,d4 vsli.64 d25,d20,#30 veor d30,d20,d21 vsli.64 d26,d20,#25 veor d19,d24,d25 vadd.i64 d27,d28 vbsl d30,d22,d21 @ Maj(a,b,c) veor d19,d26 @ Sigma0(a) vadd.i64 d23,d27 vadd.i64 d30,d27 @ vadd.i64 d19,d30 vshr.u64 d24,d23,#14 @ 5 #if 5<16 vld1.64 {d5},[r1]! @ handles unaligned #endif vshr.u64 d25,d23,#18 #if 5>0 vadd.i64 d19,d30 @ h+=Maj from the past #endif vshr.u64 d26,d23,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d23,#50 vsli.64 d25,d23,#46 vmov d29,d23 vsli.64 d26,d23,#23 #if 5<16 && defined(__ARMEL__) vrev64.8 d5,d5 #endif veor d25,d24 vbsl d29,d16,d17 @ Ch(e,f,g) vshr.u64 d24,d19,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d18 vshr.u64 d25,d19,#34 vsli.64 d24,d19,#36 vadd.i64 d27,d26 vshr.u64 d26,d19,#39 vadd.i64 d28,d5 vsli.64 d25,d19,#30 veor d30,d19,d20 vsli.64 d26,d19,#25 veor d18,d24,d25 vadd.i64 d27,d28 vbsl d30,d21,d20 @ Maj(a,b,c) veor d18,d26 @ Sigma0(a) vadd.i64 d22,d27 vadd.i64 d30,d27 @ vadd.i64 d18,d30 vshr.u64 d24,d22,#14 @ 6 #if 6<16 vld1.64 {d6},[r1]! @ handles unaligned #endif vshr.u64 d25,d22,#18 #if 6>0 vadd.i64 d18,d30 @ h+=Maj from the past #endif vshr.u64 d26,d22,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d22,#50 vsli.64 d25,d22,#46 vmov d29,d22 vsli.64 d26,d22,#23 #if 6<16 && defined(__ARMEL__) vrev64.8 d6,d6 #endif veor d25,d24 vbsl d29,d23,d16 @ Ch(e,f,g) vshr.u64 d24,d18,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d17 vshr.u64 d25,d18,#34 vsli.64 d24,d18,#36 vadd.i64 d27,d26 vshr.u64 d26,d18,#39 vadd.i64 d28,d6 vsli.64 d25,d18,#30 veor d30,d18,d19 vsli.64 d26,d18,#25 veor d17,d24,d25 vadd.i64 d27,d28 vbsl d30,d20,d19 @ Maj(a,b,c) veor d17,d26 @ Sigma0(a) vadd.i64 d21,d27 vadd.i64 d30,d27 @ vadd.i64 d17,d30 vshr.u64 d24,d21,#14 @ 7 #if 7<16 vld1.64 {d7},[r1]! @ handles unaligned #endif vshr.u64 d25,d21,#18 #if 7>0 vadd.i64 d17,d30 @ h+=Maj from the past #endif vshr.u64 d26,d21,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d21,#50 vsli.64 d25,d21,#46 vmov d29,d21 vsli.64 d26,d21,#23 #if 7<16 && defined(__ARMEL__) vrev64.8 d7,d7 #endif veor d25,d24 vbsl d29,d22,d23 @ Ch(e,f,g) vshr.u64 d24,d17,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d16 vshr.u64 d25,d17,#34 vsli.64 d24,d17,#36 vadd.i64 d27,d26 vshr.u64 d26,d17,#39 vadd.i64 d28,d7 vsli.64 d25,d17,#30 veor d30,d17,d18 vsli.64 d26,d17,#25 veor d16,d24,d25 vadd.i64 d27,d28 vbsl d30,d19,d18 @ Maj(a,b,c) veor d16,d26 @ Sigma0(a) vadd.i64 d20,d27 vadd.i64 d30,d27 @ vadd.i64 d16,d30 vshr.u64 d24,d20,#14 @ 8 #if 8<16 vld1.64 {d8},[r1]! @ handles unaligned #endif vshr.u64 d25,d20,#18 #if 8>0 vadd.i64 d16,d30 @ h+=Maj from the past #endif vshr.u64 d26,d20,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d20,#50 vsli.64 d25,d20,#46 vmov d29,d20 vsli.64 d26,d20,#23 #if 8<16 && defined(__ARMEL__) vrev64.8 d8,d8 #endif veor d25,d24 vbsl d29,d21,d22 @ Ch(e,f,g) vshr.u64 d24,d16,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d23 vshr.u64 d25,d16,#34 vsli.64 d24,d16,#36 vadd.i64 d27,d26 vshr.u64 d26,d16,#39 vadd.i64 d28,d8 vsli.64 d25,d16,#30 veor d30,d16,d17 vsli.64 d26,d16,#25 veor d23,d24,d25 vadd.i64 d27,d28 vbsl d30,d18,d17 @ Maj(a,b,c) veor d23,d26 @ Sigma0(a) vadd.i64 d19,d27 vadd.i64 d30,d27 @ vadd.i64 d23,d30 vshr.u64 d24,d19,#14 @ 9 #if 9<16 vld1.64 {d9},[r1]! @ handles unaligned #endif vshr.u64 d25,d19,#18 #if 9>0 vadd.i64 d23,d30 @ h+=Maj from the past #endif vshr.u64 d26,d19,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d19,#50 vsli.64 d25,d19,#46 vmov d29,d19 vsli.64 d26,d19,#23 #if 9<16 && defined(__ARMEL__) vrev64.8 d9,d9 #endif veor d25,d24 vbsl d29,d20,d21 @ Ch(e,f,g) vshr.u64 d24,d23,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d22 vshr.u64 d25,d23,#34 vsli.64 d24,d23,#36 vadd.i64 d27,d26 vshr.u64 d26,d23,#39 vadd.i64 d28,d9 vsli.64 d25,d23,#30 veor d30,d23,d16 vsli.64 d26,d23,#25 veor d22,d24,d25 vadd.i64 d27,d28 vbsl d30,d17,d16 @ Maj(a,b,c) veor d22,d26 @ Sigma0(a) vadd.i64 d18,d27 vadd.i64 d30,d27 @ vadd.i64 d22,d30 vshr.u64 d24,d18,#14 @ 10 #if 10<16 vld1.64 {d10},[r1]! @ handles unaligned #endif vshr.u64 d25,d18,#18 #if 10>0 vadd.i64 d22,d30 @ h+=Maj from the past #endif vshr.u64 d26,d18,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d18,#50 vsli.64 d25,d18,#46 vmov d29,d18 vsli.64 d26,d18,#23 #if 10<16 && defined(__ARMEL__) vrev64.8 d10,d10 #endif veor d25,d24 vbsl d29,d19,d20 @ Ch(e,f,g) vshr.u64 d24,d22,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d21 vshr.u64 d25,d22,#34 vsli.64 d24,d22,#36 vadd.i64 d27,d26 vshr.u64 d26,d22,#39 vadd.i64 d28,d10 vsli.64 d25,d22,#30 veor d30,d22,d23 vsli.64 d26,d22,#25 veor d21,d24,d25 vadd.i64 d27,d28 vbsl d30,d16,d23 @ Maj(a,b,c) veor d21,d26 @ Sigma0(a) vadd.i64 d17,d27 vadd.i64 d30,d27 @ vadd.i64 d21,d30 vshr.u64 d24,d17,#14 @ 11 #if 11<16 vld1.64 {d11},[r1]! @ handles unaligned #endif vshr.u64 d25,d17,#18 #if 11>0 vadd.i64 d21,d30 @ h+=Maj from the past #endif vshr.u64 d26,d17,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d17,#50 vsli.64 d25,d17,#46 vmov d29,d17 vsli.64 d26,d17,#23 #if 11<16 && defined(__ARMEL__) vrev64.8 d11,d11 #endif veor d25,d24 vbsl d29,d18,d19 @ Ch(e,f,g) vshr.u64 d24,d21,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d20 vshr.u64 d25,d21,#34 vsli.64 d24,d21,#36 vadd.i64 d27,d26 vshr.u64 d26,d21,#39 vadd.i64 d28,d11 vsli.64 d25,d21,#30 veor d30,d21,d22 vsli.64 d26,d21,#25 veor d20,d24,d25 vadd.i64 d27,d28 vbsl d30,d23,d22 @ Maj(a,b,c) veor d20,d26 @ Sigma0(a) vadd.i64 d16,d27 vadd.i64 d30,d27 @ vadd.i64 d20,d30 vshr.u64 d24,d16,#14 @ 12 #if 12<16 vld1.64 {d12},[r1]! @ handles unaligned #endif vshr.u64 d25,d16,#18 #if 12>0 vadd.i64 d20,d30 @ h+=Maj from the past #endif vshr.u64 d26,d16,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d16,#50 vsli.64 d25,d16,#46 vmov d29,d16 vsli.64 d26,d16,#23 #if 12<16 && defined(__ARMEL__) vrev64.8 d12,d12 #endif veor d25,d24 vbsl d29,d17,d18 @ Ch(e,f,g) vshr.u64 d24,d20,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d19 vshr.u64 d25,d20,#34 vsli.64 d24,d20,#36 vadd.i64 d27,d26 vshr.u64 d26,d20,#39 vadd.i64 d28,d12 vsli.64 d25,d20,#30 veor d30,d20,d21 vsli.64 d26,d20,#25 veor d19,d24,d25 vadd.i64 d27,d28 vbsl d30,d22,d21 @ Maj(a,b,c) veor d19,d26 @ Sigma0(a) vadd.i64 d23,d27 vadd.i64 d30,d27 @ vadd.i64 d19,d30 vshr.u64 d24,d23,#14 @ 13 #if 13<16 vld1.64 {d13},[r1]! @ handles unaligned #endif vshr.u64 d25,d23,#18 #if 13>0 vadd.i64 d19,d30 @ h+=Maj from the past #endif vshr.u64 d26,d23,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d23,#50 vsli.64 d25,d23,#46 vmov d29,d23 vsli.64 d26,d23,#23 #if 13<16 && defined(__ARMEL__) vrev64.8 d13,d13 #endif veor d25,d24 vbsl d29,d16,d17 @ Ch(e,f,g) vshr.u64 d24,d19,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d18 vshr.u64 d25,d19,#34 vsli.64 d24,d19,#36 vadd.i64 d27,d26 vshr.u64 d26,d19,#39 vadd.i64 d28,d13 vsli.64 d25,d19,#30 veor d30,d19,d20 vsli.64 d26,d19,#25 veor d18,d24,d25 vadd.i64 d27,d28 vbsl d30,d21,d20 @ Maj(a,b,c) veor d18,d26 @ Sigma0(a) vadd.i64 d22,d27 vadd.i64 d30,d27 @ vadd.i64 d18,d30 vshr.u64 d24,d22,#14 @ 14 #if 14<16 vld1.64 {d14},[r1]! @ handles unaligned #endif vshr.u64 d25,d22,#18 #if 14>0 vadd.i64 d18,d30 @ h+=Maj from the past #endif vshr.u64 d26,d22,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d22,#50 vsli.64 d25,d22,#46 vmov d29,d22 vsli.64 d26,d22,#23 #if 14<16 && defined(__ARMEL__) vrev64.8 d14,d14 #endif veor d25,d24 vbsl d29,d23,d16 @ Ch(e,f,g) vshr.u64 d24,d18,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d17 vshr.u64 d25,d18,#34 vsli.64 d24,d18,#36 vadd.i64 d27,d26 vshr.u64 d26,d18,#39 vadd.i64 d28,d14 vsli.64 d25,d18,#30 veor d30,d18,d19 vsli.64 d26,d18,#25 veor d17,d24,d25 vadd.i64 d27,d28 vbsl d30,d20,d19 @ Maj(a,b,c) veor d17,d26 @ Sigma0(a) vadd.i64 d21,d27 vadd.i64 d30,d27 @ vadd.i64 d17,d30 vshr.u64 d24,d21,#14 @ 15 #if 15<16 vld1.64 {d15},[r1]! @ handles unaligned #endif vshr.u64 d25,d21,#18 #if 15>0 vadd.i64 d17,d30 @ h+=Maj from the past #endif vshr.u64 d26,d21,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d21,#50 vsli.64 d25,d21,#46 vmov d29,d21 vsli.64 d26,d21,#23 #if 15<16 && defined(__ARMEL__) vrev64.8 d15,d15 #endif veor d25,d24 vbsl d29,d22,d23 @ Ch(e,f,g) vshr.u64 d24,d17,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d16 vshr.u64 d25,d17,#34 vsli.64 d24,d17,#36 vadd.i64 d27,d26 vshr.u64 d26,d17,#39 vadd.i64 d28,d15 vsli.64 d25,d17,#30 veor d30,d17,d18 vsli.64 d26,d17,#25 veor d16,d24,d25 vadd.i64 d27,d28 vbsl d30,d19,d18 @ Maj(a,b,c) veor d16,d26 @ Sigma0(a) vadd.i64 d20,d27 vadd.i64 d30,d27 @ vadd.i64 d16,d30 mov r12,#4 .L16_79_neon: subs r12,#1 vshr.u64 q12,q7,#19 vshr.u64 q13,q7,#61 vadd.i64 d16,d30 @ h+=Maj from the past vshr.u64 q15,q7,#6 vsli.64 q12,q7,#45 vext.8 q14,q0,q1,#8 @ X[i+1] vsli.64 q13,q7,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q0,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q4,q5,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d20,#14 @ from NEON_00_15 vadd.i64 q0,q14 vshr.u64 d25,d20,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d20,#41 @ from NEON_00_15 vadd.i64 q0,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d20,#50 vsli.64 d25,d20,#46 vmov d29,d20 vsli.64 d26,d20,#23 #if 16<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d21,d22 @ Ch(e,f,g) vshr.u64 d24,d16,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d23 vshr.u64 d25,d16,#34 vsli.64 d24,d16,#36 vadd.i64 d27,d26 vshr.u64 d26,d16,#39 vadd.i64 d28,d0 vsli.64 d25,d16,#30 veor d30,d16,d17 vsli.64 d26,d16,#25 veor d23,d24,d25 vadd.i64 d27,d28 vbsl d30,d18,d17 @ Maj(a,b,c) veor d23,d26 @ Sigma0(a) vadd.i64 d19,d27 vadd.i64 d30,d27 @ vadd.i64 d23,d30 vshr.u64 d24,d19,#14 @ 17 #if 17<16 vld1.64 {d1},[r1]! @ handles unaligned #endif vshr.u64 d25,d19,#18 #if 17>0 vadd.i64 d23,d30 @ h+=Maj from the past #endif vshr.u64 d26,d19,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d19,#50 vsli.64 d25,d19,#46 vmov d29,d19 vsli.64 d26,d19,#23 #if 17<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d20,d21 @ Ch(e,f,g) vshr.u64 d24,d23,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d22 vshr.u64 d25,d23,#34 vsli.64 d24,d23,#36 vadd.i64 d27,d26 vshr.u64 d26,d23,#39 vadd.i64 d28,d1 vsli.64 d25,d23,#30 veor d30,d23,d16 vsli.64 d26,d23,#25 veor d22,d24,d25 vadd.i64 d27,d28 vbsl d30,d17,d16 @ Maj(a,b,c) veor d22,d26 @ Sigma0(a) vadd.i64 d18,d27 vadd.i64 d30,d27 @ vadd.i64 d22,d30 vshr.u64 q12,q0,#19 vshr.u64 q13,q0,#61 vadd.i64 d22,d30 @ h+=Maj from the past vshr.u64 q15,q0,#6 vsli.64 q12,q0,#45 vext.8 q14,q1,q2,#8 @ X[i+1] vsli.64 q13,q0,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q1,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q5,q6,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d18,#14 @ from NEON_00_15 vadd.i64 q1,q14 vshr.u64 d25,d18,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d18,#41 @ from NEON_00_15 vadd.i64 q1,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d18,#50 vsli.64 d25,d18,#46 vmov d29,d18 vsli.64 d26,d18,#23 #if 18<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d19,d20 @ Ch(e,f,g) vshr.u64 d24,d22,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d21 vshr.u64 d25,d22,#34 vsli.64 d24,d22,#36 vadd.i64 d27,d26 vshr.u64 d26,d22,#39 vadd.i64 d28,d2 vsli.64 d25,d22,#30 veor d30,d22,d23 vsli.64 d26,d22,#25 veor d21,d24,d25 vadd.i64 d27,d28 vbsl d30,d16,d23 @ Maj(a,b,c) veor d21,d26 @ Sigma0(a) vadd.i64 d17,d27 vadd.i64 d30,d27 @ vadd.i64 d21,d30 vshr.u64 d24,d17,#14 @ 19 #if 19<16 vld1.64 {d3},[r1]! @ handles unaligned #endif vshr.u64 d25,d17,#18 #if 19>0 vadd.i64 d21,d30 @ h+=Maj from the past #endif vshr.u64 d26,d17,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d17,#50 vsli.64 d25,d17,#46 vmov d29,d17 vsli.64 d26,d17,#23 #if 19<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d18,d19 @ Ch(e,f,g) vshr.u64 d24,d21,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d20 vshr.u64 d25,d21,#34 vsli.64 d24,d21,#36 vadd.i64 d27,d26 vshr.u64 d26,d21,#39 vadd.i64 d28,d3 vsli.64 d25,d21,#30 veor d30,d21,d22 vsli.64 d26,d21,#25 veor d20,d24,d25 vadd.i64 d27,d28 vbsl d30,d23,d22 @ Maj(a,b,c) veor d20,d26 @ Sigma0(a) vadd.i64 d16,d27 vadd.i64 d30,d27 @ vadd.i64 d20,d30 vshr.u64 q12,q1,#19 vshr.u64 q13,q1,#61 vadd.i64 d20,d30 @ h+=Maj from the past vshr.u64 q15,q1,#6 vsli.64 q12,q1,#45 vext.8 q14,q2,q3,#8 @ X[i+1] vsli.64 q13,q1,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q2,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q6,q7,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d16,#14 @ from NEON_00_15 vadd.i64 q2,q14 vshr.u64 d25,d16,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d16,#41 @ from NEON_00_15 vadd.i64 q2,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d16,#50 vsli.64 d25,d16,#46 vmov d29,d16 vsli.64 d26,d16,#23 #if 20<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d17,d18 @ Ch(e,f,g) vshr.u64 d24,d20,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d19 vshr.u64 d25,d20,#34 vsli.64 d24,d20,#36 vadd.i64 d27,d26 vshr.u64 d26,d20,#39 vadd.i64 d28,d4 vsli.64 d25,d20,#30 veor d30,d20,d21 vsli.64 d26,d20,#25 veor d19,d24,d25 vadd.i64 d27,d28 vbsl d30,d22,d21 @ Maj(a,b,c) veor d19,d26 @ Sigma0(a) vadd.i64 d23,d27 vadd.i64 d30,d27 @ vadd.i64 d19,d30 vshr.u64 d24,d23,#14 @ 21 #if 21<16 vld1.64 {d5},[r1]! @ handles unaligned #endif vshr.u64 d25,d23,#18 #if 21>0 vadd.i64 d19,d30 @ h+=Maj from the past #endif vshr.u64 d26,d23,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d23,#50 vsli.64 d25,d23,#46 vmov d29,d23 vsli.64 d26,d23,#23 #if 21<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d16,d17 @ Ch(e,f,g) vshr.u64 d24,d19,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d18 vshr.u64 d25,d19,#34 vsli.64 d24,d19,#36 vadd.i64 d27,d26 vshr.u64 d26,d19,#39 vadd.i64 d28,d5 vsli.64 d25,d19,#30 veor d30,d19,d20 vsli.64 d26,d19,#25 veor d18,d24,d25 vadd.i64 d27,d28 vbsl d30,d21,d20 @ Maj(a,b,c) veor d18,d26 @ Sigma0(a) vadd.i64 d22,d27 vadd.i64 d30,d27 @ vadd.i64 d18,d30 vshr.u64 q12,q2,#19 vshr.u64 q13,q2,#61 vadd.i64 d18,d30 @ h+=Maj from the past vshr.u64 q15,q2,#6 vsli.64 q12,q2,#45 vext.8 q14,q3,q4,#8 @ X[i+1] vsli.64 q13,q2,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q3,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q7,q0,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d22,#14 @ from NEON_00_15 vadd.i64 q3,q14 vshr.u64 d25,d22,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d22,#41 @ from NEON_00_15 vadd.i64 q3,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d22,#50 vsli.64 d25,d22,#46 vmov d29,d22 vsli.64 d26,d22,#23 #if 22<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d23,d16 @ Ch(e,f,g) vshr.u64 d24,d18,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d17 vshr.u64 d25,d18,#34 vsli.64 d24,d18,#36 vadd.i64 d27,d26 vshr.u64 d26,d18,#39 vadd.i64 d28,d6 vsli.64 d25,d18,#30 veor d30,d18,d19 vsli.64 d26,d18,#25 veor d17,d24,d25 vadd.i64 d27,d28 vbsl d30,d20,d19 @ Maj(a,b,c) veor d17,d26 @ Sigma0(a) vadd.i64 d21,d27 vadd.i64 d30,d27 @ vadd.i64 d17,d30 vshr.u64 d24,d21,#14 @ 23 #if 23<16 vld1.64 {d7},[r1]! @ handles unaligned #endif vshr.u64 d25,d21,#18 #if 23>0 vadd.i64 d17,d30 @ h+=Maj from the past #endif vshr.u64 d26,d21,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d21,#50 vsli.64 d25,d21,#46 vmov d29,d21 vsli.64 d26,d21,#23 #if 23<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d22,d23 @ Ch(e,f,g) vshr.u64 d24,d17,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d16 vshr.u64 d25,d17,#34 vsli.64 d24,d17,#36 vadd.i64 d27,d26 vshr.u64 d26,d17,#39 vadd.i64 d28,d7 vsli.64 d25,d17,#30 veor d30,d17,d18 vsli.64 d26,d17,#25 veor d16,d24,d25 vadd.i64 d27,d28 vbsl d30,d19,d18 @ Maj(a,b,c) veor d16,d26 @ Sigma0(a) vadd.i64 d20,d27 vadd.i64 d30,d27 @ vadd.i64 d16,d30 vshr.u64 q12,q3,#19 vshr.u64 q13,q3,#61 vadd.i64 d16,d30 @ h+=Maj from the past vshr.u64 q15,q3,#6 vsli.64 q12,q3,#45 vext.8 q14,q4,q5,#8 @ X[i+1] vsli.64 q13,q3,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q4,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q0,q1,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d20,#14 @ from NEON_00_15 vadd.i64 q4,q14 vshr.u64 d25,d20,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d20,#41 @ from NEON_00_15 vadd.i64 q4,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d20,#50 vsli.64 d25,d20,#46 vmov d29,d20 vsli.64 d26,d20,#23 #if 24<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d21,d22 @ Ch(e,f,g) vshr.u64 d24,d16,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d23 vshr.u64 d25,d16,#34 vsli.64 d24,d16,#36 vadd.i64 d27,d26 vshr.u64 d26,d16,#39 vadd.i64 d28,d8 vsli.64 d25,d16,#30 veor d30,d16,d17 vsli.64 d26,d16,#25 veor d23,d24,d25 vadd.i64 d27,d28 vbsl d30,d18,d17 @ Maj(a,b,c) veor d23,d26 @ Sigma0(a) vadd.i64 d19,d27 vadd.i64 d30,d27 @ vadd.i64 d23,d30 vshr.u64 d24,d19,#14 @ 25 #if 25<16 vld1.64 {d9},[r1]! @ handles unaligned #endif vshr.u64 d25,d19,#18 #if 25>0 vadd.i64 d23,d30 @ h+=Maj from the past #endif vshr.u64 d26,d19,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d19,#50 vsli.64 d25,d19,#46 vmov d29,d19 vsli.64 d26,d19,#23 #if 25<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d20,d21 @ Ch(e,f,g) vshr.u64 d24,d23,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d22 vshr.u64 d25,d23,#34 vsli.64 d24,d23,#36 vadd.i64 d27,d26 vshr.u64 d26,d23,#39 vadd.i64 d28,d9 vsli.64 d25,d23,#30 veor d30,d23,d16 vsli.64 d26,d23,#25 veor d22,d24,d25 vadd.i64 d27,d28 vbsl d30,d17,d16 @ Maj(a,b,c) veor d22,d26 @ Sigma0(a) vadd.i64 d18,d27 vadd.i64 d30,d27 @ vadd.i64 d22,d30 vshr.u64 q12,q4,#19 vshr.u64 q13,q4,#61 vadd.i64 d22,d30 @ h+=Maj from the past vshr.u64 q15,q4,#6 vsli.64 q12,q4,#45 vext.8 q14,q5,q6,#8 @ X[i+1] vsli.64 q13,q4,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q5,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q1,q2,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d18,#14 @ from NEON_00_15 vadd.i64 q5,q14 vshr.u64 d25,d18,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d18,#41 @ from NEON_00_15 vadd.i64 q5,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d18,#50 vsli.64 d25,d18,#46 vmov d29,d18 vsli.64 d26,d18,#23 #if 26<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d19,d20 @ Ch(e,f,g) vshr.u64 d24,d22,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d21 vshr.u64 d25,d22,#34 vsli.64 d24,d22,#36 vadd.i64 d27,d26 vshr.u64 d26,d22,#39 vadd.i64 d28,d10 vsli.64 d25,d22,#30 veor d30,d22,d23 vsli.64 d26,d22,#25 veor d21,d24,d25 vadd.i64 d27,d28 vbsl d30,d16,d23 @ Maj(a,b,c) veor d21,d26 @ Sigma0(a) vadd.i64 d17,d27 vadd.i64 d30,d27 @ vadd.i64 d21,d30 vshr.u64 d24,d17,#14 @ 27 #if 27<16 vld1.64 {d11},[r1]! @ handles unaligned #endif vshr.u64 d25,d17,#18 #if 27>0 vadd.i64 d21,d30 @ h+=Maj from the past #endif vshr.u64 d26,d17,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d17,#50 vsli.64 d25,d17,#46 vmov d29,d17 vsli.64 d26,d17,#23 #if 27<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d18,d19 @ Ch(e,f,g) vshr.u64 d24,d21,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d20 vshr.u64 d25,d21,#34 vsli.64 d24,d21,#36 vadd.i64 d27,d26 vshr.u64 d26,d21,#39 vadd.i64 d28,d11 vsli.64 d25,d21,#30 veor d30,d21,d22 vsli.64 d26,d21,#25 veor d20,d24,d25 vadd.i64 d27,d28 vbsl d30,d23,d22 @ Maj(a,b,c) veor d20,d26 @ Sigma0(a) vadd.i64 d16,d27 vadd.i64 d30,d27 @ vadd.i64 d20,d30 vshr.u64 q12,q5,#19 vshr.u64 q13,q5,#61 vadd.i64 d20,d30 @ h+=Maj from the past vshr.u64 q15,q5,#6 vsli.64 q12,q5,#45 vext.8 q14,q6,q7,#8 @ X[i+1] vsli.64 q13,q5,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q6,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q2,q3,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d16,#14 @ from NEON_00_15 vadd.i64 q6,q14 vshr.u64 d25,d16,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d16,#41 @ from NEON_00_15 vadd.i64 q6,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d16,#50 vsli.64 d25,d16,#46 vmov d29,d16 vsli.64 d26,d16,#23 #if 28<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d17,d18 @ Ch(e,f,g) vshr.u64 d24,d20,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d19 vshr.u64 d25,d20,#34 vsli.64 d24,d20,#36 vadd.i64 d27,d26 vshr.u64 d26,d20,#39 vadd.i64 d28,d12 vsli.64 d25,d20,#30 veor d30,d20,d21 vsli.64 d26,d20,#25 veor d19,d24,d25 vadd.i64 d27,d28 vbsl d30,d22,d21 @ Maj(a,b,c) veor d19,d26 @ Sigma0(a) vadd.i64 d23,d27 vadd.i64 d30,d27 @ vadd.i64 d19,d30 vshr.u64 d24,d23,#14 @ 29 #if 29<16 vld1.64 {d13},[r1]! @ handles unaligned #endif vshr.u64 d25,d23,#18 #if 29>0 vadd.i64 d19,d30 @ h+=Maj from the past #endif vshr.u64 d26,d23,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d23,#50 vsli.64 d25,d23,#46 vmov d29,d23 vsli.64 d26,d23,#23 #if 29<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d16,d17 @ Ch(e,f,g) vshr.u64 d24,d19,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d18 vshr.u64 d25,d19,#34 vsli.64 d24,d19,#36 vadd.i64 d27,d26 vshr.u64 d26,d19,#39 vadd.i64 d28,d13 vsli.64 d25,d19,#30 veor d30,d19,d20 vsli.64 d26,d19,#25 veor d18,d24,d25 vadd.i64 d27,d28 vbsl d30,d21,d20 @ Maj(a,b,c) veor d18,d26 @ Sigma0(a) vadd.i64 d22,d27 vadd.i64 d30,d27 @ vadd.i64 d18,d30 vshr.u64 q12,q6,#19 vshr.u64 q13,q6,#61 vadd.i64 d18,d30 @ h+=Maj from the past vshr.u64 q15,q6,#6 vsli.64 q12,q6,#45 vext.8 q14,q7,q0,#8 @ X[i+1] vsli.64 q13,q6,#3 veor q15,q12 vshr.u64 q12,q14,#1 veor q15,q13 @ sigma1(X[i+14]) vshr.u64 q13,q14,#8 vadd.i64 q7,q15 vshr.u64 q15,q14,#7 vsli.64 q12,q14,#63 vsli.64 q13,q14,#56 vext.8 q14,q3,q4,#8 @ X[i+9] veor q15,q12 vshr.u64 d24,d22,#14 @ from NEON_00_15 vadd.i64 q7,q14 vshr.u64 d25,d22,#18 @ from NEON_00_15 veor q15,q13 @ sigma0(X[i+1]) vshr.u64 d26,d22,#41 @ from NEON_00_15 vadd.i64 q7,q15 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d22,#50 vsli.64 d25,d22,#46 vmov d29,d22 vsli.64 d26,d22,#23 #if 30<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d23,d16 @ Ch(e,f,g) vshr.u64 d24,d18,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d17 vshr.u64 d25,d18,#34 vsli.64 d24,d18,#36 vadd.i64 d27,d26 vshr.u64 d26,d18,#39 vadd.i64 d28,d14 vsli.64 d25,d18,#30 veor d30,d18,d19 vsli.64 d26,d18,#25 veor d17,d24,d25 vadd.i64 d27,d28 vbsl d30,d20,d19 @ Maj(a,b,c) veor d17,d26 @ Sigma0(a) vadd.i64 d21,d27 vadd.i64 d30,d27 @ vadd.i64 d17,d30 vshr.u64 d24,d21,#14 @ 31 #if 31<16 vld1.64 {d15},[r1]! @ handles unaligned #endif vshr.u64 d25,d21,#18 #if 31>0 vadd.i64 d17,d30 @ h+=Maj from the past #endif vshr.u64 d26,d21,#41 vld1.64 {d28},[r3,:64]! @ K[i++] vsli.64 d24,d21,#50 vsli.64 d25,d21,#46 vmov d29,d21 vsli.64 d26,d21,#23 #if 31<16 && defined(__ARMEL__) vrev64.8 , #endif veor d25,d24 vbsl d29,d22,d23 @ Ch(e,f,g) vshr.u64 d24,d17,#28 veor d26,d25 @ Sigma1(e) vadd.i64 d27,d29,d16 vshr.u64 d25,d17,#34 vsli.64 d24,d17,#36 vadd.i64 d27,d26 vshr.u64 d26,d17,#39 vadd.i64 d28,d15 vsli.64 d25,d17,#30 veor d30,d17,d18 vsli.64 d26,d17,#25 veor d16,d24,d25 vadd.i64 d27,d28 vbsl d30,d19,d18 @ Maj(a,b,c) veor d16,d26 @ Sigma0(a) vadd.i64 d20,d27 vadd.i64 d30,d27 @ vadd.i64 d16,d30 bne .L16_79_neon vadd.i64 d16,d30 @ h+=Maj from the past vldmia r0,{d24,d25,d26,d27,d28,d29,d30,d31} @ load context to temp vadd.i64 q8,q12 @ vectorized accumulate vadd.i64 q9,q13 vadd.i64 q10,q14 vadd.i64 q11,q15 vstmia r0,{d16,d17,d18,d19,d20,d21,d22,d23} @ save context teq r1,r2 sub r3,#640 @ rewind K512 bne .Loop_neon VFP_ABI_POP bx lr @ .word 0xe12fff1e .size sha512_block_data_order_neon,.-sha512_block_data_order_neon #endif .byte 83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 .align 2 #endif // !OPENSSL_NO_ASM && defined(OPENSSL_ARM) && defined(__ELF__)

j4yc3-mw/Viren

35,688

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/p256-armv8-asm-win64.S

// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32) #include "ring-core/arm_arch.h" .section .rodata .align 5 Lpoly: .quad 0xffffffffffffffff,0x00000000ffffffff,0x0000000000000000,0xffffffff00000001 LRR: // 2^512 mod P precomputed for NIST P256 polynomial .quad 0x0000000000000003,0xfffffffbffffffff,0xfffffffffffffffe,0x00000004fffffffd Lone_mont: .quad 0x0000000000000001,0xffffffff00000000,0xffffffffffffffff,0x00000000fffffffe Lone: .quad 1,0,0,0 Lord: .quad 0xf3b9cac2fc632551,0xbce6faada7179e84,0xffffffffffffffff,0xffffffff00000000 LordK: .quad 0xccd1c8aaee00bc4f .byte 69,67,80,95,78,73,83,84,90,50,53,54,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 .align 2 .text // void ecp_nistz256_mul_mont(BN_ULONG x0[4],const BN_ULONG x1[4], // const BN_ULONG x2[4]); .globl ecp_nistz256_mul_mont .def ecp_nistz256_mul_mont .type 32 .endef .align 4 ecp_nistz256_mul_mont: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-32]! add x29,sp,#0 stp x19,x20,[sp,#16] ldr x3,[x2] // bp[0] ldp x4,x5,[x1] ldp x6,x7,[x1,#16] adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] ldr x13,[x13,#24] bl __ecp_nistz256_mul_mont ldp x19,x20,[sp,#16] ldp x29,x30,[sp],#32 AARCH64_VALIDATE_LINK_REGISTER ret // void ecp_nistz256_sqr_mont(BN_ULONG x0[4],const BN_ULONG x1[4]); .globl ecp_nistz256_sqr_mont .def ecp_nistz256_sqr_mont .type 32 .endef .align 4 ecp_nistz256_sqr_mont: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-32]! add x29,sp,#0 stp x19,x20,[sp,#16] ldp x4,x5,[x1] ldp x6,x7,[x1,#16] adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] ldr x13,[x13,#24] bl __ecp_nistz256_sqr_mont ldp x19,x20,[sp,#16] ldp x29,x30,[sp],#32 AARCH64_VALIDATE_LINK_REGISTER ret // void ecp_nistz256_neg(BN_ULONG x0[4],const BN_ULONG x1[4]); .globl ecp_nistz256_neg .def ecp_nistz256_neg .type 32 .endef .align 4 ecp_nistz256_neg: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-16]! add x29,sp,#0 mov x2,x1 mov x14,xzr // a = 0 mov x15,xzr mov x16,xzr mov x17,xzr adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] ldr x13,[x13,#24] bl __ecp_nistz256_sub_from ldp x29,x30,[sp],#16 AARCH64_VALIDATE_LINK_REGISTER ret // note that __ecp_nistz256_mul_mont expects a[0-3] input pre-loaded // to x4-x7 and b[0] - to x3 .def __ecp_nistz256_mul_mont .type 32 .endef .align 4 __ecp_nistz256_mul_mont: mul x14,x4,x3 // a[0]*b[0] umulh x8,x4,x3 mul x15,x5,x3 // a[1]*b[0] umulh x9,x5,x3 mul x16,x6,x3 // a[2]*b[0] umulh x10,x6,x3 mul x17,x7,x3 // a[3]*b[0] umulh x11,x7,x3 ldr x3,[x2,#8] // b[1] adds x15,x15,x8 // accumulate high parts of multiplication lsl x8,x14,#32 adcs x16,x16,x9 lsr x9,x14,#32 adcs x17,x17,x10 adc x19,xzr,x11 mov x20,xzr subs x10,x14,x8 // "*0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] mul x8,x4,x3 // lo(a[0]*b[i]) adcs x15,x16,x9 mul x9,x5,x3 // lo(a[1]*b[i]) adcs x16,x17,x10 // +=acc[0]*0xffff0001 mul x10,x6,x3 // lo(a[2]*b[i]) adcs x17,x19,x11 mul x11,x7,x3 // lo(a[3]*b[i]) adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts of multiplication umulh x8,x4,x3 // hi(a[0]*b[i]) adcs x15,x15,x9 umulh x9,x5,x3 // hi(a[1]*b[i]) adcs x16,x16,x10 umulh x10,x6,x3 // hi(a[2]*b[i]) adcs x17,x17,x11 umulh x11,x7,x3 // hi(a[3]*b[i]) adc x19,x19,xzr ldr x3,[x2,#8*(1+1)] // b[1+1] adds x15,x15,x8 // accumulate high parts of multiplication lsl x8,x14,#32 adcs x16,x16,x9 lsr x9,x14,#32 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr subs x10,x14,x8 // "*0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] mul x8,x4,x3 // lo(a[0]*b[i]) adcs x15,x16,x9 mul x9,x5,x3 // lo(a[1]*b[i]) adcs x16,x17,x10 // +=acc[0]*0xffff0001 mul x10,x6,x3 // lo(a[2]*b[i]) adcs x17,x19,x11 mul x11,x7,x3 // lo(a[3]*b[i]) adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts of multiplication umulh x8,x4,x3 // hi(a[0]*b[i]) adcs x15,x15,x9 umulh x9,x5,x3 // hi(a[1]*b[i]) adcs x16,x16,x10 umulh x10,x6,x3 // hi(a[2]*b[i]) adcs x17,x17,x11 umulh x11,x7,x3 // hi(a[3]*b[i]) adc x19,x19,xzr ldr x3,[x2,#8*(2+1)] // b[2+1] adds x15,x15,x8 // accumulate high parts of multiplication lsl x8,x14,#32 adcs x16,x16,x9 lsr x9,x14,#32 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr subs x10,x14,x8 // "*0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] mul x8,x4,x3 // lo(a[0]*b[i]) adcs x15,x16,x9 mul x9,x5,x3 // lo(a[1]*b[i]) adcs x16,x17,x10 // +=acc[0]*0xffff0001 mul x10,x6,x3 // lo(a[2]*b[i]) adcs x17,x19,x11 mul x11,x7,x3 // lo(a[3]*b[i]) adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts of multiplication umulh x8,x4,x3 // hi(a[0]*b[i]) adcs x15,x15,x9 umulh x9,x5,x3 // hi(a[1]*b[i]) adcs x16,x16,x10 umulh x10,x6,x3 // hi(a[2]*b[i]) adcs x17,x17,x11 umulh x11,x7,x3 // hi(a[3]*b[i]) adc x19,x19,xzr adds x15,x15,x8 // accumulate high parts of multiplication lsl x8,x14,#32 adcs x16,x16,x9 lsr x9,x14,#32 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr // last reduction subs x10,x14,x8 // "*0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] adcs x15,x16,x9 adcs x16,x17,x10 // +=acc[0]*0xffff0001 adcs x17,x19,x11 adc x19,x20,xzr adds x8,x14,#1 // subs x8,x14,#-1 // tmp = ret-modulus sbcs x9,x15,x12 sbcs x10,x16,xzr sbcs x11,x17,x13 sbcs xzr,x19,xzr // did it borrow? csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus csel x15,x15,x9,lo csel x16,x16,x10,lo stp x14,x15,[x0] csel x17,x17,x11,lo stp x16,x17,[x0,#16] ret // note that __ecp_nistz256_sqr_mont expects a[0-3] input pre-loaded // to x4-x7 .def __ecp_nistz256_sqr_mont .type 32 .endef .align 4 __ecp_nistz256_sqr_mont: // | | | | | |a1*a0| | // | | | | |a2*a0| | | // | |a3*a2|a3*a0| | | | // | | | |a2*a1| | | | // | | |a3*a1| | | | | // *| | | | | | | | 2| // +|a3*a3|a2*a2|a1*a1|a0*a0| // |--+--+--+--+--+--+--+--| // |A7|A6|A5|A4|A3|A2|A1|A0|, where Ax is , i.e. follow // // "can't overflow" below mark carrying into high part of // multiplication result, which can't overflow, because it // can never be all ones. mul x15,x5,x4 // a[1]*a[0] umulh x9,x5,x4 mul x16,x6,x4 // a[2]*a[0] umulh x10,x6,x4 mul x17,x7,x4 // a[3]*a[0] umulh x19,x7,x4 adds x16,x16,x9 // accumulate high parts of multiplication mul x8,x6,x5 // a[2]*a[1] umulh x9,x6,x5 adcs x17,x17,x10 mul x10,x7,x5 // a[3]*a[1] umulh x11,x7,x5 adc x19,x19,xzr // can't overflow mul x20,x7,x6 // a[3]*a[2] umulh x1,x7,x6 adds x9,x9,x10 // accumulate high parts of multiplication mul x14,x4,x4 // a[0]*a[0] adc x10,x11,xzr // can't overflow adds x17,x17,x8 // accumulate low parts of multiplication umulh x4,x4,x4 adcs x19,x19,x9 mul x9,x5,x5 // a[1]*a[1] adcs x20,x20,x10 umulh x5,x5,x5 adc x1,x1,xzr // can't overflow adds x15,x15,x15 // acc[1-6]*=2 mul x10,x6,x6 // a[2]*a[2] adcs x16,x16,x16 umulh x6,x6,x6 adcs x17,x17,x17 mul x11,x7,x7 // a[3]*a[3] adcs x19,x19,x19 umulh x7,x7,x7 adcs x20,x20,x20 adcs x1,x1,x1 adc x2,xzr,xzr adds x15,x15,x4 // +a[i]*a[i] adcs x16,x16,x9 adcs x17,x17,x5 adcs x19,x19,x10 adcs x20,x20,x6 lsl x8,x14,#32 adcs x1,x1,x11 lsr x9,x14,#32 adc x2,x2,x7 subs x10,x14,x8 // "*0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] adcs x15,x16,x9 lsl x8,x14,#32 adcs x16,x17,x10 // +=acc[0]*0xffff0001 lsr x9,x14,#32 adc x17,x11,xzr // can't overflow subs x10,x14,x8 // "*0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] adcs x15,x16,x9 lsl x8,x14,#32 adcs x16,x17,x10 // +=acc[0]*0xffff0001 lsr x9,x14,#32 adc x17,x11,xzr // can't overflow subs x10,x14,x8 // "*0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] adcs x15,x16,x9 lsl x8,x14,#32 adcs x16,x17,x10 // +=acc[0]*0xffff0001 lsr x9,x14,#32 adc x17,x11,xzr // can't overflow subs x10,x14,x8 // "*0xffff0001" sbc x11,x14,x9 adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0] adcs x15,x16,x9 adcs x16,x17,x10 // +=acc[0]*0xffff0001 adc x17,x11,xzr // can't overflow adds x14,x14,x19 // accumulate upper half adcs x15,x15,x20 adcs x16,x16,x1 adcs x17,x17,x2 adc x19,xzr,xzr adds x8,x14,#1 // subs x8,x14,#-1 // tmp = ret-modulus sbcs x9,x15,x12 sbcs x10,x16,xzr sbcs x11,x17,x13 sbcs xzr,x19,xzr // did it borrow? csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus csel x15,x15,x9,lo csel x16,x16,x10,lo stp x14,x15,[x0] csel x17,x17,x11,lo stp x16,x17,[x0,#16] ret // Note that __ecp_nistz256_add_to expects both input vectors pre-loaded to // x4-x7 and x8-x11. This is done because it's used in multiple // contexts, e.g. in multiplication by 2 and 3... .def __ecp_nistz256_add_to .type 32 .endef .align 4 __ecp_nistz256_add_to: adds x14,x14,x8 // ret = a+b adcs x15,x15,x9 adcs x16,x16,x10 adcs x17,x17,x11 adc x1,xzr,xzr // zap x1 adds x8,x14,#1 // subs x8,x4,#-1 // tmp = ret-modulus sbcs x9,x15,x12 sbcs x10,x16,xzr sbcs x11,x17,x13 sbcs xzr,x1,xzr // did subtraction borrow? csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus csel x15,x15,x9,lo csel x16,x16,x10,lo stp x14,x15,[x0] csel x17,x17,x11,lo stp x16,x17,[x0,#16] ret .def __ecp_nistz256_sub_from .type 32 .endef .align 4 __ecp_nistz256_sub_from: ldp x8,x9,[x2] ldp x10,x11,[x2,#16] subs x14,x14,x8 // ret = a-b sbcs x15,x15,x9 sbcs x16,x16,x10 sbcs x17,x17,x11 sbc x1,xzr,xzr // zap x1 subs x8,x14,#1 // adds x8,x4,#-1 // tmp = ret+modulus adcs x9,x15,x12 adcs x10,x16,xzr adc x11,x17,x13 cmp x1,xzr // did subtraction borrow? csel x14,x14,x8,eq // ret = borrow ? ret+modulus : ret csel x15,x15,x9,eq csel x16,x16,x10,eq stp x14,x15,[x0] csel x17,x17,x11,eq stp x16,x17,[x0,#16] ret .def __ecp_nistz256_sub_morf .type 32 .endef .align 4 __ecp_nistz256_sub_morf: ldp x8,x9,[x2] ldp x10,x11,[x2,#16] subs x14,x8,x14 // ret = b-a sbcs x15,x9,x15 sbcs x16,x10,x16 sbcs x17,x11,x17 sbc x1,xzr,xzr // zap x1 subs x8,x14,#1 // adds x8,x4,#-1 // tmp = ret+modulus adcs x9,x15,x12 adcs x10,x16,xzr adc x11,x17,x13 cmp x1,xzr // did subtraction borrow? csel x14,x14,x8,eq // ret = borrow ? ret+modulus : ret csel x15,x15,x9,eq csel x16,x16,x10,eq stp x14,x15,[x0] csel x17,x17,x11,eq stp x16,x17,[x0,#16] ret .def __ecp_nistz256_div_by_2 .type 32 .endef .align 4 __ecp_nistz256_div_by_2: subs x8,x14,#1 // adds x8,x4,#-1 // tmp = a+modulus adcs x9,x15,x12 adcs x10,x16,xzr adcs x11,x17,x13 adc x1,xzr,xzr // zap x1 tst x14,#1 // is a even? csel x14,x14,x8,eq // ret = even ? a : a+modulus csel x15,x15,x9,eq csel x16,x16,x10,eq csel x17,x17,x11,eq csel x1,xzr,x1,eq lsr x14,x14,#1 // ret >>= 1 orr x14,x14,x15,lsl#63 lsr x15,x15,#1 orr x15,x15,x16,lsl#63 lsr x16,x16,#1 orr x16,x16,x17,lsl#63 lsr x17,x17,#1 stp x14,x15,[x0] orr x17,x17,x1,lsl#63 stp x16,x17,[x0,#16] ret .globl ecp_nistz256_point_double .def ecp_nistz256_point_double .type 32 .endef .align 5 ecp_nistz256_point_double: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-96]! add x29,sp,#0 stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] sub sp,sp,#32*4 Ldouble_shortcut: ldp x14,x15,[x1,#32] mov x21,x0 ldp x16,x17,[x1,#48] mov x22,x1 adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] mov x8,x14 ldr x13,[x13,#24] mov x9,x15 ldp x4,x5,[x22,#64] // forward load for p256_sqr_mont mov x10,x16 mov x11,x17 ldp x6,x7,[x22,#64+16] add x0,sp,#0 bl __ecp_nistz256_add_to // p256_mul_by_2(S, in_y); add x0,sp,#64 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Zsqr, in_z); ldp x8,x9,[x22] ldp x10,x11,[x22,#16] mov x4,x14 // put Zsqr aside for p256_sub mov x5,x15 mov x6,x16 mov x7,x17 add x0,sp,#32 bl __ecp_nistz256_add_to // p256_add(M, Zsqr, in_x); add x2,x22,#0 mov x14,x4 // restore Zsqr mov x15,x5 ldp x4,x5,[sp,#0] // forward load for p256_sqr_mont mov x16,x6 mov x17,x7 ldp x6,x7,[sp,#0+16] add x0,sp,#64 bl __ecp_nistz256_sub_morf // p256_sub(Zsqr, in_x, Zsqr); add x0,sp,#0 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(S, S); ldr x3,[x22,#32] ldp x4,x5,[x22,#64] ldp x6,x7,[x22,#64+16] add x2,x22,#32 add x0,sp,#96 bl __ecp_nistz256_mul_mont // p256_mul_mont(tmp0, in_z, in_y); mov x8,x14 mov x9,x15 ldp x4,x5,[sp,#0] // forward load for p256_sqr_mont mov x10,x16 mov x11,x17 ldp x6,x7,[sp,#0+16] add x0,x21,#64 bl __ecp_nistz256_add_to // p256_mul_by_2(res_z, tmp0); add x0,sp,#96 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(tmp0, S); ldr x3,[sp,#64] // forward load for p256_mul_mont ldp x4,x5,[sp,#32] ldp x6,x7,[sp,#32+16] add x0,x21,#32 bl __ecp_nistz256_div_by_2 // p256_div_by_2(res_y, tmp0); add x2,sp,#64 add x0,sp,#32 bl __ecp_nistz256_mul_mont // p256_mul_mont(M, M, Zsqr); mov x8,x14 // duplicate M mov x9,x15 mov x10,x16 mov x11,x17 mov x4,x14 // put M aside mov x5,x15 mov x6,x16 mov x7,x17 add x0,sp,#32 bl __ecp_nistz256_add_to mov x8,x4 // restore M mov x9,x5 ldr x3,[x22] // forward load for p256_mul_mont mov x10,x6 ldp x4,x5,[sp,#0] mov x11,x7 ldp x6,x7,[sp,#0+16] bl __ecp_nistz256_add_to // p256_mul_by_3(M, M); add x2,x22,#0 add x0,sp,#0 bl __ecp_nistz256_mul_mont // p256_mul_mont(S, S, in_x); mov x8,x14 mov x9,x15 ldp x4,x5,[sp,#32] // forward load for p256_sqr_mont mov x10,x16 mov x11,x17 ldp x6,x7,[sp,#32+16] add x0,sp,#96 bl __ecp_nistz256_add_to // p256_mul_by_2(tmp0, S); add x0,x21,#0 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(res_x, M); add x2,sp,#96 bl __ecp_nistz256_sub_from // p256_sub(res_x, res_x, tmp0); add x2,sp,#0 add x0,sp,#0 bl __ecp_nistz256_sub_morf // p256_sub(S, S, res_x); ldr x3,[sp,#32] mov x4,x14 // copy S mov x5,x15 mov x6,x16 mov x7,x17 add x2,sp,#32 bl __ecp_nistz256_mul_mont // p256_mul_mont(S, S, M); add x2,x21,#32 add x0,x21,#32 bl __ecp_nistz256_sub_from // p256_sub(res_y, S, res_y); add sp,x29,#0 // destroy frame ldp x19,x20,[x29,#16] ldp x21,x22,[x29,#32] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret .globl ecp_nistz256_point_add .def ecp_nistz256_point_add .type 32 .endef .align 5 ecp_nistz256_point_add: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-96]! add x29,sp,#0 stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] stp x25,x26,[sp,#64] stp x27,x28,[sp,#80] sub sp,sp,#32*12 ldp x4,x5,[x2,#64] // in2_z ldp x6,x7,[x2,#64+16] mov x21,x0 mov x22,x1 mov x23,x2 adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] ldr x13,[x13,#24] orr x8,x4,x5 orr x10,x6,x7 orr x25,x8,x10 cmp x25,#0 csetm x25,ne // ~in2infty add x0,sp,#192 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Z2sqr, in2_z); ldp x4,x5,[x22,#64] // in1_z ldp x6,x7,[x22,#64+16] orr x8,x4,x5 orr x10,x6,x7 orr x24,x8,x10 cmp x24,#0 csetm x24,ne // ~in1infty add x0,sp,#128 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Z1sqr, in1_z); ldr x3,[x23,#64] ldp x4,x5,[sp,#192] ldp x6,x7,[sp,#192+16] add x2,x23,#64 add x0,sp,#320 bl __ecp_nistz256_mul_mont // p256_mul_mont(S1, Z2sqr, in2_z); ldr x3,[x22,#64] ldp x4,x5,[sp,#128] ldp x6,x7,[sp,#128+16] add x2,x22,#64 add x0,sp,#352 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, Z1sqr, in1_z); ldr x3,[x22,#32] ldp x4,x5,[sp,#320] ldp x6,x7,[sp,#320+16] add x2,x22,#32 add x0,sp,#320 bl __ecp_nistz256_mul_mont // p256_mul_mont(S1, S1, in1_y); ldr x3,[x23,#32] ldp x4,x5,[sp,#352] ldp x6,x7,[sp,#352+16] add x2,x23,#32 add x0,sp,#352 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, S2, in2_y); add x2,sp,#320 ldr x3,[sp,#192] // forward load for p256_mul_mont ldp x4,x5,[x22] ldp x6,x7,[x22,#16] add x0,sp,#160 bl __ecp_nistz256_sub_from // p256_sub(R, S2, S1); orr x14,x14,x15 // see if result is zero orr x16,x16,x17 orr x26,x14,x16 // ~is_equal(S1,S2) add x2,sp,#192 add x0,sp,#256 bl __ecp_nistz256_mul_mont // p256_mul_mont(U1, in1_x, Z2sqr); ldr x3,[sp,#128] ldp x4,x5,[x23] ldp x6,x7,[x23,#16] add x2,sp,#128 add x0,sp,#288 bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, in2_x, Z1sqr); add x2,sp,#256 ldp x4,x5,[sp,#160] // forward load for p256_sqr_mont ldp x6,x7,[sp,#160+16] add x0,sp,#96 bl __ecp_nistz256_sub_from // p256_sub(H, U2, U1); orr x14,x14,x15 // see if result is zero orr x16,x16,x17 orr x14,x14,x16 // ~is_equal(U1,U2) mvn x27,x24 // -1/0 -> 0/-1 mvn x28,x25 // -1/0 -> 0/-1 orr x14,x14,x27 orr x14,x14,x28 orr x14,x14,x26 cbnz x14,Ladd_proceed // if(~is_equal(U1,U2) | in1infty | in2infty | ~is_equal(S1,S2)) Ladd_double: mov x1,x22 mov x0,x21 ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] add sp,sp,#256 // #256 is from #32*(12-4). difference in stack frames b Ldouble_shortcut .align 4 Ladd_proceed: add x0,sp,#192 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Rsqr, R); ldr x3,[x22,#64] ldp x4,x5,[sp,#96] ldp x6,x7,[sp,#96+16] add x2,x22,#64 add x0,sp,#64 bl __ecp_nistz256_mul_mont // p256_mul_mont(res_z, H, in1_z); ldp x4,x5,[sp,#96] ldp x6,x7,[sp,#96+16] add x0,sp,#128 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Hsqr, H); ldr x3,[x23,#64] ldp x4,x5,[sp,#64] ldp x6,x7,[sp,#64+16] add x2,x23,#64 add x0,sp,#64 bl __ecp_nistz256_mul_mont // p256_mul_mont(res_z, res_z, in2_z); ldr x3,[sp,#96] ldp x4,x5,[sp,#128] ldp x6,x7,[sp,#128+16] add x2,sp,#96 add x0,sp,#224 bl __ecp_nistz256_mul_mont // p256_mul_mont(Hcub, Hsqr, H); ldr x3,[sp,#128] ldp x4,x5,[sp,#256] ldp x6,x7,[sp,#256+16] add x2,sp,#128 add x0,sp,#288 bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, U1, Hsqr); mov x8,x14 mov x9,x15 mov x10,x16 mov x11,x17 add x0,sp,#128 bl __ecp_nistz256_add_to // p256_mul_by_2(Hsqr, U2); add x2,sp,#192 add x0,sp,#0 bl __ecp_nistz256_sub_morf // p256_sub(res_x, Rsqr, Hsqr); add x2,sp,#224 bl __ecp_nistz256_sub_from // p256_sub(res_x, res_x, Hcub); add x2,sp,#288 ldr x3,[sp,#224] // forward load for p256_mul_mont ldp x4,x5,[sp,#320] ldp x6,x7,[sp,#320+16] add x0,sp,#32 bl __ecp_nistz256_sub_morf // p256_sub(res_y, U2, res_x); add x2,sp,#224 add x0,sp,#352 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, S1, Hcub); ldr x3,[sp,#160] ldp x4,x5,[sp,#32] ldp x6,x7,[sp,#32+16] add x2,sp,#160 add x0,sp,#32 bl __ecp_nistz256_mul_mont // p256_mul_mont(res_y, res_y, R); add x2,sp,#352 bl __ecp_nistz256_sub_from // p256_sub(res_y, res_y, S2); ldp x4,x5,[sp,#0] // res ldp x6,x7,[sp,#0+16] ldp x8,x9,[x23] // in2 ldp x10,x11,[x23,#16] ldp x14,x15,[x22,#0] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#0+16] csel x8,x4,x8,ne csel x9,x5,x9,ne ldp x4,x5,[sp,#0+0+32] // res csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? ldp x6,x7,[sp,#0+0+48] csel x14,x8,x14,ne csel x15,x9,x15,ne ldp x8,x9,[x23,#0+32] // in2 csel x16,x10,x16,ne csel x17,x11,x17,ne ldp x10,x11,[x23,#0+48] stp x14,x15,[x21,#0] stp x16,x17,[x21,#0+16] ldp x14,x15,[x22,#32] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#32+16] csel x8,x4,x8,ne csel x9,x5,x9,ne ldp x4,x5,[sp,#0+32+32] // res csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? ldp x6,x7,[sp,#0+32+48] csel x14,x8,x14,ne csel x15,x9,x15,ne ldp x8,x9,[x23,#32+32] // in2 csel x16,x10,x16,ne csel x17,x11,x17,ne ldp x10,x11,[x23,#32+48] stp x14,x15,[x21,#32] stp x16,x17,[x21,#32+16] ldp x14,x15,[x22,#64] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#64+16] csel x8,x4,x8,ne csel x9,x5,x9,ne csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? csel x14,x8,x14,ne csel x15,x9,x15,ne csel x16,x10,x16,ne csel x17,x11,x17,ne stp x14,x15,[x21,#64] stp x16,x17,[x21,#64+16] Ladd_done: add sp,x29,#0 // destroy frame ldp x19,x20,[x29,#16] ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x27,x28,[x29,#80] ldp x29,x30,[sp],#96 AARCH64_VALIDATE_LINK_REGISTER ret .globl ecp_nistz256_point_add_affine .def ecp_nistz256_point_add_affine .type 32 .endef .align 5 ecp_nistz256_point_add_affine: AARCH64_SIGN_LINK_REGISTER stp x29,x30,[sp,#-80]! add x29,sp,#0 stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] stp x25,x26,[sp,#64] sub sp,sp,#32*10 mov x21,x0 mov x22,x1 mov x23,x2 adrp x13,Lpoly add x13,x13,:lo12:Lpoly ldr x12,[x13,#8] ldr x13,[x13,#24] ldp x4,x5,[x1,#64] // in1_z ldp x6,x7,[x1,#64+16] orr x8,x4,x5 orr x10,x6,x7 orr x24,x8,x10 cmp x24,#0 csetm x24,ne // ~in1infty ldp x14,x15,[x2] // in2_x ldp x16,x17,[x2,#16] ldp x8,x9,[x2,#32] // in2_y ldp x10,x11,[x2,#48] orr x14,x14,x15 orr x16,x16,x17 orr x8,x8,x9 orr x10,x10,x11 orr x14,x14,x16 orr x8,x8,x10 orr x25,x14,x8 cmp x25,#0 csetm x25,ne // ~in2infty add x0,sp,#128 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Z1sqr, in1_z); mov x4,x14 mov x5,x15 mov x6,x16 mov x7,x17 ldr x3,[x23] add x2,x23,#0 add x0,sp,#96 bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, Z1sqr, in2_x); add x2,x22,#0 ldr x3,[x22,#64] // forward load for p256_mul_mont ldp x4,x5,[sp,#128] ldp x6,x7,[sp,#128+16] add x0,sp,#160 bl __ecp_nistz256_sub_from // p256_sub(H, U2, in1_x); add x2,x22,#64 add x0,sp,#128 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, Z1sqr, in1_z); ldr x3,[x22,#64] ldp x4,x5,[sp,#160] ldp x6,x7,[sp,#160+16] add x2,x22,#64 add x0,sp,#64 bl __ecp_nistz256_mul_mont // p256_mul_mont(res_z, H, in1_z); ldr x3,[x23,#32] ldp x4,x5,[sp,#128] ldp x6,x7,[sp,#128+16] add x2,x23,#32 add x0,sp,#128 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, S2, in2_y); add x2,x22,#32 ldp x4,x5,[sp,#160] // forward load for p256_sqr_mont ldp x6,x7,[sp,#160+16] add x0,sp,#192 bl __ecp_nistz256_sub_from // p256_sub(R, S2, in1_y); add x0,sp,#224 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Hsqr, H); ldp x4,x5,[sp,#192] ldp x6,x7,[sp,#192+16] add x0,sp,#288 bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Rsqr, R); ldr x3,[sp,#160] ldp x4,x5,[sp,#224] ldp x6,x7,[sp,#224+16] add x2,sp,#160 add x0,sp,#256 bl __ecp_nistz256_mul_mont // p256_mul_mont(Hcub, Hsqr, H); ldr x3,[x22] ldp x4,x5,[sp,#224] ldp x6,x7,[sp,#224+16] add x2,x22,#0 add x0,sp,#96 bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, in1_x, Hsqr); mov x8,x14 mov x9,x15 mov x10,x16 mov x11,x17 add x0,sp,#224 bl __ecp_nistz256_add_to // p256_mul_by_2(Hsqr, U2); add x2,sp,#288 add x0,sp,#0 bl __ecp_nistz256_sub_morf // p256_sub(res_x, Rsqr, Hsqr); add x2,sp,#256 bl __ecp_nistz256_sub_from // p256_sub(res_x, res_x, Hcub); add x2,sp,#96 ldr x3,[x22,#32] // forward load for p256_mul_mont ldp x4,x5,[sp,#256] ldp x6,x7,[sp,#256+16] add x0,sp,#32 bl __ecp_nistz256_sub_morf // p256_sub(res_y, U2, res_x); add x2,x22,#32 add x0,sp,#128 bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, in1_y, Hcub); ldr x3,[sp,#192] ldp x4,x5,[sp,#32] ldp x6,x7,[sp,#32+16] add x2,sp,#192 add x0,sp,#32 bl __ecp_nistz256_mul_mont // p256_mul_mont(res_y, res_y, R); add x2,sp,#128 bl __ecp_nistz256_sub_from // p256_sub(res_y, res_y, S2); ldp x4,x5,[sp,#0] // res ldp x6,x7,[sp,#0+16] ldp x8,x9,[x23] // in2 ldp x10,x11,[x23,#16] ldp x14,x15,[x22,#0] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#0+16] csel x8,x4,x8,ne csel x9,x5,x9,ne ldp x4,x5,[sp,#0+0+32] // res csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? ldp x6,x7,[sp,#0+0+48] csel x14,x8,x14,ne csel x15,x9,x15,ne ldp x8,x9,[x23,#0+32] // in2 csel x16,x10,x16,ne csel x17,x11,x17,ne ldp x10,x11,[x23,#0+48] stp x14,x15,[x21,#0] stp x16,x17,[x21,#0+16] adrp x23,Lone_mont-64 add x23,x23,:lo12:Lone_mont-64 ldp x14,x15,[x22,#32] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#32+16] csel x8,x4,x8,ne csel x9,x5,x9,ne ldp x4,x5,[sp,#0+32+32] // res csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? ldp x6,x7,[sp,#0+32+48] csel x14,x8,x14,ne csel x15,x9,x15,ne ldp x8,x9,[x23,#32+32] // in2 csel x16,x10,x16,ne csel x17,x11,x17,ne ldp x10,x11,[x23,#32+48] stp x14,x15,[x21,#32] stp x16,x17,[x21,#32+16] ldp x14,x15,[x22,#64] // in1 cmp x24,#0 // ~, remember? ldp x16,x17,[x22,#64+16] csel x8,x4,x8,ne csel x9,x5,x9,ne csel x10,x6,x10,ne csel x11,x7,x11,ne cmp x25,#0 // ~, remember? csel x14,x8,x14,ne csel x15,x9,x15,ne csel x16,x10,x16,ne csel x17,x11,x17,ne stp x14,x15,[x21,#64] stp x16,x17,[x21,#64+16] add sp,x29,#0 // destroy frame ldp x19,x20,[x29,#16] ldp x21,x22,[x29,#32] ldp x23,x24,[x29,#48] ldp x25,x26,[x29,#64] ldp x29,x30,[sp],#80 AARCH64_VALIDATE_LINK_REGISTER ret //////////////////////////////////////////////////////////////////////// // void ecp_nistz256_ord_mul_mont(uint64_t res[4], uint64_t a[4], // uint64_t b[4]); .globl ecp_nistz256_ord_mul_mont .def ecp_nistz256_ord_mul_mont .type 32 .endef .align 4 ecp_nistz256_ord_mul_mont: AARCH64_VALID_CALL_TARGET // Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later. stp x29,x30,[sp,#-64]! add x29,sp,#0 stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] adrp x23,Lord add x23,x23,:lo12:Lord ldr x3,[x2] // bp[0] ldp x4,x5,[x1] ldp x6,x7,[x1,#16] ldp x12,x13,[x23,#0] ldp x21,x22,[x23,#16] ldr x23,[x23,#32] mul x14,x4,x3 // a[0]*b[0] umulh x8,x4,x3 mul x15,x5,x3 // a[1]*b[0] umulh x9,x5,x3 mul x16,x6,x3 // a[2]*b[0] umulh x10,x6,x3 mul x17,x7,x3 // a[3]*b[0] umulh x19,x7,x3 mul x24,x14,x23 adds x15,x15,x8 // accumulate high parts of multiplication adcs x16,x16,x9 adcs x17,x17,x10 adc x19,x19,xzr mov x20,xzr ldr x3,[x2,#8*1] // b[i] lsl x8,x24,#32 subs x16,x16,x24 lsr x9,x24,#32 sbcs x17,x17,x8 sbcs x19,x19,x9 sbc x20,x20,xzr subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 mul x8,x4,x3 adc x11,x11,xzr mul x9,x5,x3 adds x14,x15,x10 mul x10,x6,x3 adcs x15,x16,x11 mul x11,x7,x3 adcs x16,x17,x24 adcs x17,x19,x24 adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts umulh x8,x4,x3 adcs x15,x15,x9 umulh x9,x5,x3 adcs x16,x16,x10 umulh x10,x6,x3 adcs x17,x17,x11 umulh x11,x7,x3 adc x19,x19,xzr mul x24,x14,x23 adds x15,x15,x8 // accumulate high parts adcs x16,x16,x9 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr ldr x3,[x2,#8*2] // b[i] lsl x8,x24,#32 subs x16,x16,x24 lsr x9,x24,#32 sbcs x17,x17,x8 sbcs x19,x19,x9 sbc x20,x20,xzr subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 mul x8,x4,x3 adc x11,x11,xzr mul x9,x5,x3 adds x14,x15,x10 mul x10,x6,x3 adcs x15,x16,x11 mul x11,x7,x3 adcs x16,x17,x24 adcs x17,x19,x24 adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts umulh x8,x4,x3 adcs x15,x15,x9 umulh x9,x5,x3 adcs x16,x16,x10 umulh x10,x6,x3 adcs x17,x17,x11 umulh x11,x7,x3 adc x19,x19,xzr mul x24,x14,x23 adds x15,x15,x8 // accumulate high parts adcs x16,x16,x9 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr ldr x3,[x2,#8*3] // b[i] lsl x8,x24,#32 subs x16,x16,x24 lsr x9,x24,#32 sbcs x17,x17,x8 sbcs x19,x19,x9 sbc x20,x20,xzr subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 mul x8,x4,x3 adc x11,x11,xzr mul x9,x5,x3 adds x14,x15,x10 mul x10,x6,x3 adcs x15,x16,x11 mul x11,x7,x3 adcs x16,x17,x24 adcs x17,x19,x24 adc x19,x20,xzr adds x14,x14,x8 // accumulate low parts umulh x8,x4,x3 adcs x15,x15,x9 umulh x9,x5,x3 adcs x16,x16,x10 umulh x10,x6,x3 adcs x17,x17,x11 umulh x11,x7,x3 adc x19,x19,xzr mul x24,x14,x23 adds x15,x15,x8 // accumulate high parts adcs x16,x16,x9 adcs x17,x17,x10 adcs x19,x19,x11 adc x20,xzr,xzr lsl x8,x24,#32 // last reduction subs x16,x16,x24 lsr x9,x24,#32 sbcs x17,x17,x8 sbcs x19,x19,x9 sbc x20,x20,xzr subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 adc x11,x11,xzr adds x14,x15,x10 adcs x15,x16,x11 adcs x16,x17,x24 adcs x17,x19,x24 adc x19,x20,xzr subs x8,x14,x12 // ret -= modulus sbcs x9,x15,x13 sbcs x10,x16,x21 sbcs x11,x17,x22 sbcs xzr,x19,xzr csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus csel x15,x15,x9,lo csel x16,x16,x10,lo stp x14,x15,[x0] csel x17,x17,x11,lo stp x16,x17,[x0,#16] ldp x19,x20,[sp,#16] ldp x21,x22,[sp,#32] ldp x23,x24,[sp,#48] ldr x29,[sp],#64 ret //////////////////////////////////////////////////////////////////////// // void ecp_nistz256_ord_sqr_mont(uint64_t res[4], uint64_t a[4], // uint64_t rep); .globl ecp_nistz256_ord_sqr_mont .def ecp_nistz256_ord_sqr_mont .type 32 .endef .align 4 ecp_nistz256_ord_sqr_mont: AARCH64_VALID_CALL_TARGET // Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later. stp x29,x30,[sp,#-64]! add x29,sp,#0 stp x19,x20,[sp,#16] stp x21,x22,[sp,#32] stp x23,x24,[sp,#48] adrp x23,Lord add x23,x23,:lo12:Lord ldp x4,x5,[x1] ldp x6,x7,[x1,#16] ldp x12,x13,[x23,#0] ldp x21,x22,[x23,#16] ldr x23,[x23,#32] b Loop_ord_sqr .align 4 Loop_ord_sqr: sub x2,x2,#1 //////////////////////////////////////////////////////////////// // | | | | | |a1*a0| | // | | | | |a2*a0| | | // | |a3*a2|a3*a0| | | | // | | | |a2*a1| | | | // | | |a3*a1| | | | | // *| | | | | | | | 2| // +|a3*a3|a2*a2|a1*a1|a0*a0| // |--+--+--+--+--+--+--+--| // |A7|A6|A5|A4|A3|A2|A1|A0|, where Ax is , i.e. follow // // "can't overflow" below mark carrying into high part of // multiplication result, which can't overflow, because it // can never be all ones. mul x15,x5,x4 // a[1]*a[0] umulh x9,x5,x4 mul x16,x6,x4 // a[2]*a[0] umulh x10,x6,x4 mul x17,x7,x4 // a[3]*a[0] umulh x19,x7,x4 adds x16,x16,x9 // accumulate high parts of multiplication mul x8,x6,x5 // a[2]*a[1] umulh x9,x6,x5 adcs x17,x17,x10 mul x10,x7,x5 // a[3]*a[1] umulh x11,x7,x5 adc x19,x19,xzr // can't overflow mul x20,x7,x6 // a[3]*a[2] umulh x1,x7,x6 adds x9,x9,x10 // accumulate high parts of multiplication mul x14,x4,x4 // a[0]*a[0] adc x10,x11,xzr // can't overflow adds x17,x17,x8 // accumulate low parts of multiplication umulh x4,x4,x4 adcs x19,x19,x9 mul x9,x5,x5 // a[1]*a[1] adcs x20,x20,x10 umulh x5,x5,x5 adc x1,x1,xzr // can't overflow adds x15,x15,x15 // acc[1-6]*=2 mul x10,x6,x6 // a[2]*a[2] adcs x16,x16,x16 umulh x6,x6,x6 adcs x17,x17,x17 mul x11,x7,x7 // a[3]*a[3] adcs x19,x19,x19 umulh x7,x7,x7 adcs x20,x20,x20 adcs x1,x1,x1 adc x3,xzr,xzr adds x15,x15,x4 // +a[i]*a[i] mul x24,x14,x23 adcs x16,x16,x9 adcs x17,x17,x5 adcs x19,x19,x10 adcs x20,x20,x6 adcs x1,x1,x11 adc x3,x3,x7 subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 adc x11,x11,xzr adds x14,x15,x10 adcs x15,x16,x11 adcs x16,x17,x24 adc x17,xzr,x24 // can't overflow mul x11,x14,x23 lsl x8,x24,#32 subs x15,x15,x24 lsr x9,x24,#32 sbcs x16,x16,x8 sbc x17,x17,x9 // can't borrow subs xzr,x14,#1 umulh x9,x12,x11 mul x10,x13,x11 umulh x24,x13,x11 adcs x10,x10,x9 adc x24,x24,xzr adds x14,x15,x10 adcs x15,x16,x24 adcs x16,x17,x11 adc x17,xzr,x11 // can't overflow mul x24,x14,x23 lsl x8,x11,#32 subs x15,x15,x11 lsr x9,x11,#32 sbcs x16,x16,x8 sbc x17,x17,x9 // can't borrow subs xzr,x14,#1 umulh x9,x12,x24 mul x10,x13,x24 umulh x11,x13,x24 adcs x10,x10,x9 adc x11,x11,xzr adds x14,x15,x10 adcs x15,x16,x11 adcs x16,x17,x24 adc x17,xzr,x24 // can't overflow mul x11,x14,x23 lsl x8,x24,#32 subs x15,x15,x24 lsr x9,x24,#32 sbcs x16,x16,x8 sbc x17,x17,x9 // can't borrow subs xzr,x14,#1 umulh x9,x12,x11 mul x10,x13,x11 umulh x24,x13,x11 adcs x10,x10,x9 adc x24,x24,xzr adds x14,x15,x10 adcs x15,x16,x24 adcs x16,x17,x11 adc x17,xzr,x11 // can't overflow lsl x8,x11,#32 subs x15,x15,x11 lsr x9,x11,#32 sbcs x16,x16,x8 sbc x17,x17,x9 // can't borrow adds x14,x14,x19 // accumulate upper half adcs x15,x15,x20 adcs x16,x16,x1 adcs x17,x17,x3 adc x19,xzr,xzr subs x8,x14,x12 // ret -= modulus sbcs x9,x15,x13 sbcs x10,x16,x21 sbcs x11,x17,x22 sbcs xzr,x19,xzr csel x4,x14,x8,lo // ret = borrow ? ret : ret-modulus csel x5,x15,x9,lo csel x6,x16,x10,lo csel x7,x17,x11,lo cbnz x2,Loop_ord_sqr stp x4,x5,[x0] stp x6,x7,[x0,#16] ldp x19,x20,[sp,#16] ldp x21,x22,[sp,#32] ldp x23,x24,[sp,#48] ldr x29,[sp],#64 ret //////////////////////////////////////////////////////////////////////// // void ecp_nistz256_select_w5(uint64_t *val, uint64_t *in_t, int index); .globl ecp_nistz256_select_w5 .def ecp_nistz256_select_w5 .type 32 .endef .align 4 ecp_nistz256_select_w5: AARCH64_VALID_CALL_TARGET // x10 := x0 // w9 := 0; loop counter and incremented internal index mov x10, x0 mov w9, #0 // [v16-v21] := 0 movi v16.16b, #0 movi v17.16b, #0 movi v18.16b, #0 movi v19.16b, #0 movi v20.16b, #0 movi v21.16b, #0 Lselect_w5_loop: // Loop 16 times. // Increment index (loop counter); tested at the end of the loop add w9, w9, #1 // [v22-v27] := Load a (3*256-bit = 6*128-bit) table entry starting at x1 // and advance x1 to point to the next entry ld1 {v22.2d, v23.2d, v24.2d, v25.2d}, [x1],#64 // x11 := (w9 == w2)? All 1s : All 0s cmp w9, w2 csetm x11, eq // continue loading ... ld1 {v26.2d, v27.2d}, [x1],#32 // duplicate mask_64 into Mask (all 0s or all 1s) dup v3.2d, x11 // [v16-v19] := (Mask == all 1s)? [v22-v25] : [v16-v19] // i.e., values in output registers will remain the same if w9 != w2 bit v16.16b, v22.16b, v3.16b bit v17.16b, v23.16b, v3.16b bit v18.16b, v24.16b, v3.16b bit v19.16b, v25.16b, v3.16b bit v20.16b, v26.16b, v3.16b bit v21.16b, v27.16b, v3.16b // If bit #4 is not 0 (i.e. idx_ctr < 16) loop back tbz w9, #4, Lselect_w5_loop // Write [v16-v21] to memory at the output pointer st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x10],#64 st1 {v20.2d, v21.2d}, [x10] ret //////////////////////////////////////////////////////////////////////// // void ecp_nistz256_select_w7(uint64_t *val, uint64_t *in_t, int index); .globl ecp_nistz256_select_w7 .def ecp_nistz256_select_w7 .type 32 .endef .align 4 ecp_nistz256_select_w7: AARCH64_VALID_CALL_TARGET // w9 := 0; loop counter and incremented internal index mov w9, #0 // [v16-v21] := 0 movi v16.16b, #0 movi v17.16b, #0 movi v18.16b, #0 movi v19.16b, #0 Lselect_w7_loop: // Loop 64 times. // Increment index (loop counter); tested at the end of the loop add w9, w9, #1 // [v22-v25] := Load a (2*256-bit = 4*128-bit) table entry starting at x1 // and advance x1 to point to the next entry ld1 {v22.2d, v23.2d, v24.2d, v25.2d}, [x1],#64 // x11 := (w9 == w2)? All 1s : All 0s cmp w9, w2 csetm x11, eq // duplicate mask_64 into Mask (all 0s or all 1s) dup v3.2d, x11 // [v16-v19] := (Mask == all 1s)? [v22-v25] : [v16-v19] // i.e., values in output registers will remain the same if w9 != w2 bit v16.16b, v22.16b, v3.16b bit v17.16b, v23.16b, v3.16b bit v18.16b, v24.16b, v3.16b bit v19.16b, v25.16b, v3.16b // If bit #6 is not 0 (i.e. idx_ctr < 64) loop back tbz w9, #6, Lselect_w7_loop // Write [v16-v19] to memory at the output pointer st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0] ret #endif // !OPENSSL_NO_ASM && defined(OPENSSL_AARCH64) && defined(_WIN32)

j4yc3-mw/Viren

32,699

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/chacha-x86_64-macosx.S

// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__APPLE__) .text .section __DATA,__const .p2align 6 L$zero: .long 0,0,0,0 L$one: .long 1,0,0,0 L$inc: .long 0,1,2,3 L$four: .long 4,4,4,4 L$incy: .long 0,2,4,6,1,3,5,7 L$eight: .long 8,8,8,8,8,8,8,8 L$rot16: .byte 0x2,0x3,0x0,0x1, 0x6,0x7,0x4,0x5, 0xa,0xb,0x8,0x9, 0xe,0xf,0xc,0xd L$rot24: .byte 0x3,0x0,0x1,0x2, 0x7,0x4,0x5,0x6, 0xb,0x8,0x9,0xa, 0xf,0xc,0xd,0xe L$sigma: .byte 101,120,112,97,110,100,32,51,50,45,98,121,116,101,32,107,0 .p2align 6 L$zeroz: .long 0,0,0,0, 1,0,0,0, 2,0,0,0, 3,0,0,0 L$fourz: .long 4,0,0,0, 4,0,0,0, 4,0,0,0, 4,0,0,0 L$incz: .long 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 L$sixteen: .long 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 .byte 67,104,97,67,104,97,50,48,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 .text .globl _ChaCha20_ctr32 .private_extern _ChaCha20_ctr32 .p2align 6 _ChaCha20_ctr32: _CET_ENDBR cmpq $0,%rdx je L$no_data movq _OPENSSL_ia32cap_P+4(%rip),%r10 testl $512,%r10d jnz L$ChaCha20_ssse3 pushq %rbx pushq %rbp pushq %r12 pushq %r13 pushq %r14 pushq %r15 subq $64+24,%rsp L$ctr32_body: movdqu (%rcx),%xmm1 movdqu 16(%rcx),%xmm2 movdqu (%r8),%xmm3 movdqa L$one(%rip),%xmm4 movdqa %xmm1,16(%rsp) movdqa %xmm2,32(%rsp) movdqa %xmm3,48(%rsp) movq %rdx,%rbp jmp L$oop_outer .p2align 5 L$oop_outer: movl $0x61707865,%eax movl $0x3320646e,%ebx movl $0x79622d32,%ecx movl $0x6b206574,%edx movl 16(%rsp),%r8d movl 20(%rsp),%r9d movl 24(%rsp),%r10d movl 28(%rsp),%r11d movd %xmm3,%r12d movl 52(%rsp),%r13d movl 56(%rsp),%r14d movl 60(%rsp),%r15d movq %rbp,64+0(%rsp) movl $10,%ebp movq %rsi,64+8(%rsp) .byte 102,72,15,126,214 movq %rdi,64+16(%rsp) movq %rsi,%rdi shrq $32,%rdi jmp L$oop .p2align 5 L$oop: addl %r8d,%eax xorl %eax,%r12d roll $16,%r12d addl %r9d,%ebx xorl %ebx,%r13d roll $16,%r13d addl %r12d,%esi xorl %esi,%r8d roll $12,%r8d addl %r13d,%edi xorl %edi,%r9d roll $12,%r9d addl %r8d,%eax xorl %eax,%r12d roll $8,%r12d addl %r9d,%ebx xorl %ebx,%r13d roll $8,%r13d addl %r12d,%esi xorl %esi,%r8d roll $7,%r8d addl %r13d,%edi xorl %edi,%r9d roll $7,%r9d movl %esi,32(%rsp) movl %edi,36(%rsp) movl 40(%rsp),%esi movl 44(%rsp),%edi addl %r10d,%ecx xorl %ecx,%r14d roll $16,%r14d addl %r11d,%edx xorl %edx,%r15d roll $16,%r15d addl %r14d,%esi xorl %esi,%r10d roll $12,%r10d addl %r15d,%edi xorl %edi,%r11d roll $12,%r11d addl %r10d,%ecx xorl %ecx,%r14d roll $8,%r14d addl %r11d,%edx xorl %edx,%r15d roll $8,%r15d addl %r14d,%esi xorl %esi,%r10d roll $7,%r10d addl %r15d,%edi xorl %edi,%r11d roll $7,%r11d addl %r9d,%eax xorl %eax,%r15d roll $16,%r15d addl %r10d,%ebx xorl %ebx,%r12d roll $16,%r12d addl %r15d,%esi xorl %esi,%r9d roll $12,%r9d addl %r12d,%edi xorl %edi,%r10d roll $12,%r10d addl %r9d,%eax xorl %eax,%r15d roll $8,%r15d addl %r10d,%ebx xorl %ebx,%r12d roll $8,%r12d addl %r15d,%esi xorl %esi,%r9d roll $7,%r9d addl %r12d,%edi xorl %edi,%r10d roll $7,%r10d movl %esi,40(%rsp) movl %edi,44(%rsp) movl 32(%rsp),%esi movl 36(%rsp),%edi addl %r11d,%ecx xorl %ecx,%r13d roll $16,%r13d addl %r8d,%edx xorl %edx,%r14d roll $16,%r14d addl %r13d,%esi xorl %esi,%r11d roll $12,%r11d addl %r14d,%edi xorl %edi,%r8d roll $12,%r8d addl %r11d,%ecx xorl %ecx,%r13d roll $8,%r13d addl %r8d,%edx xorl %edx,%r14d roll $8,%r14d addl %r13d,%esi xorl %esi,%r11d roll $7,%r11d addl %r14d,%edi xorl %edi,%r8d roll $7,%r8d decl %ebp jnz L$oop movl %edi,36(%rsp) movl %esi,32(%rsp) movq 64(%rsp),%rbp movdqa %xmm2,%xmm1 movq 64+8(%rsp),%rsi paddd %xmm4,%xmm3 movq 64+16(%rsp),%rdi addl $0x61707865,%eax addl $0x3320646e,%ebx addl $0x79622d32,%ecx addl $0x6b206574,%edx addl 16(%rsp),%r8d addl 20(%rsp),%r9d addl 24(%rsp),%r10d addl 28(%rsp),%r11d addl 48(%rsp),%r12d addl 52(%rsp),%r13d addl 56(%rsp),%r14d addl 60(%rsp),%r15d paddd 32(%rsp),%xmm1 cmpq $64,%rbp jb L$tail xorl 0(%rsi),%eax xorl 4(%rsi),%ebx xorl 8(%rsi),%ecx xorl 12(%rsi),%edx xorl 16(%rsi),%r8d xorl 20(%rsi),%r9d xorl 24(%rsi),%r10d xorl 28(%rsi),%r11d movdqu 32(%rsi),%xmm0 xorl 48(%rsi),%r12d xorl 52(%rsi),%r13d xorl 56(%rsi),%r14d xorl 60(%rsi),%r15d leaq 64(%rsi),%rsi pxor %xmm1,%xmm0 movdqa %xmm2,32(%rsp) movd %xmm3,48(%rsp) movl %eax,0(%rdi) movl %ebx,4(%rdi) movl %ecx,8(%rdi) movl %edx,12(%rdi) movl %r8d,16(%rdi) movl %r9d,20(%rdi) movl %r10d,24(%rdi) movl %r11d,28(%rdi) movdqu %xmm0,32(%rdi) movl %r12d,48(%rdi) movl %r13d,52(%rdi) movl %r14d,56(%rdi) movl %r15d,60(%rdi) leaq 64(%rdi),%rdi subq $64,%rbp jnz L$oop_outer jmp L$done .p2align 4 L$tail: movl %eax,0(%rsp) movl %ebx,4(%rsp) xorq %rbx,%rbx movl %ecx,8(%rsp) movl %edx,12(%rsp) movl %r8d,16(%rsp) movl %r9d,20(%rsp) movl %r10d,24(%rsp) movl %r11d,28(%rsp) movdqa %xmm1,32(%rsp) movl %r12d,48(%rsp) movl %r13d,52(%rsp) movl %r14d,56(%rsp) movl %r15d,60(%rsp) L$oop_tail: movzbl (%rsi,%rbx,1),%eax movzbl (%rsp,%rbx,1),%edx leaq 1(%rbx),%rbx xorl %edx,%eax movb %al,-1(%rdi,%rbx,1) decq %rbp jnz L$oop_tail L$done: leaq 64+24+48(%rsp),%rsi movq -48(%rsi),%r15 movq -40(%rsi),%r14 movq -32(%rsi),%r13 movq -24(%rsi),%r12 movq -16(%rsi),%rbp movq -8(%rsi),%rbx leaq (%rsi),%rsp L$no_data: ret .p2align 5 ChaCha20_ssse3: L$ChaCha20_ssse3: movq %rsp,%r9 cmpq $128,%rdx ja L$ChaCha20_4x L$do_sse3_after_all: subq $64+8,%rsp movdqa L$sigma(%rip),%xmm0 movdqu (%rcx),%xmm1 movdqu 16(%rcx),%xmm2 movdqu (%r8),%xmm3 movdqa L$rot16(%rip),%xmm6 movdqa L$rot24(%rip),%xmm7 movdqa %xmm0,0(%rsp) movdqa %xmm1,16(%rsp) movdqa %xmm2,32(%rsp) movdqa %xmm3,48(%rsp) movq $10,%r8 jmp L$oop_ssse3 .p2align 5 L$oop_outer_ssse3: movdqa L$one(%rip),%xmm3 movdqa 0(%rsp),%xmm0 movdqa 16(%rsp),%xmm1 movdqa 32(%rsp),%xmm2 paddd 48(%rsp),%xmm3 movq $10,%r8 movdqa %xmm3,48(%rsp) jmp L$oop_ssse3 .p2align 5 L$oop_ssse3: paddd %xmm1,%xmm0 pxor %xmm0,%xmm3 .byte 102,15,56,0,222 paddd %xmm3,%xmm2 pxor %xmm2,%xmm1 movdqa %xmm1,%xmm4 psrld $20,%xmm1 pslld $12,%xmm4 por %xmm4,%xmm1 paddd %xmm1,%xmm0 pxor %xmm0,%xmm3 .byte 102,15,56,0,223 paddd %xmm3,%xmm2 pxor %xmm2,%xmm1 movdqa %xmm1,%xmm4 psrld $25,%xmm1 pslld $7,%xmm4 por %xmm4,%xmm1 pshufd $78,%xmm2,%xmm2 pshufd $57,%xmm1,%xmm1 pshufd $147,%xmm3,%xmm3 nop paddd %xmm1,%xmm0 pxor %xmm0,%xmm3 .byte 102,15,56,0,222 paddd %xmm3,%xmm2 pxor %xmm2,%xmm1 movdqa %xmm1,%xmm4 psrld $20,%xmm1 pslld $12,%xmm4 por %xmm4,%xmm1 paddd %xmm1,%xmm0 pxor %xmm0,%xmm3 .byte 102,15,56,0,223 paddd %xmm3,%xmm2 pxor %xmm2,%xmm1 movdqa %xmm1,%xmm4 psrld $25,%xmm1 pslld $7,%xmm4 por %xmm4,%xmm1 pshufd $78,%xmm2,%xmm2 pshufd $147,%xmm1,%xmm1 pshufd $57,%xmm3,%xmm3 decq %r8 jnz L$oop_ssse3 paddd 0(%rsp),%xmm0 paddd 16(%rsp),%xmm1 paddd 32(%rsp),%xmm2 paddd 48(%rsp),%xmm3 cmpq $64,%rdx jb L$tail_ssse3 movdqu 0(%rsi),%xmm4 movdqu 16(%rsi),%xmm5 pxor %xmm4,%xmm0 movdqu 32(%rsi),%xmm4 pxor %xmm5,%xmm1 movdqu 48(%rsi),%xmm5 leaq 64(%rsi),%rsi pxor %xmm4,%xmm2 pxor %xmm5,%xmm3 movdqu %xmm0,0(%rdi) movdqu %xmm1,16(%rdi) movdqu %xmm2,32(%rdi) movdqu %xmm3,48(%rdi) leaq 64(%rdi),%rdi subq $64,%rdx jnz L$oop_outer_ssse3 jmp L$done_ssse3 .p2align 4 L$tail_ssse3: movdqa %xmm0,0(%rsp) movdqa %xmm1,16(%rsp) movdqa %xmm2,32(%rsp) movdqa %xmm3,48(%rsp) xorq %r8,%r8 L$oop_tail_ssse3: movzbl (%rsi,%r8,1),%eax movzbl (%rsp,%r8,1),%ecx leaq 1(%r8),%r8 xorl %ecx,%eax movb %al,-1(%rdi,%r8,1) decq %rdx jnz L$oop_tail_ssse3 L$done_ssse3: leaq (%r9),%rsp L$ssse3_epilogue: ret .p2align 5 ChaCha20_4x: L$ChaCha20_4x: movq %rsp,%r9 movq %r10,%r11 shrq $32,%r10 testq $32,%r10 jnz L$ChaCha20_8x cmpq $192,%rdx ja L$proceed4x andq $71303168,%r11 cmpq $4194304,%r11 je L$do_sse3_after_all L$proceed4x: subq $0x140+8,%rsp movdqa L$sigma(%rip),%xmm11 movdqu (%rcx),%xmm15 movdqu 16(%rcx),%xmm7 movdqu (%r8),%xmm3 leaq 256(%rsp),%rcx leaq L$rot16(%rip),%r10 leaq L$rot24(%rip),%r11 pshufd $0x00,%xmm11,%xmm8 pshufd $0x55,%xmm11,%xmm9 movdqa %xmm8,64(%rsp) pshufd $0xaa,%xmm11,%xmm10 movdqa %xmm9,80(%rsp) pshufd $0xff,%xmm11,%xmm11 movdqa %xmm10,96(%rsp) movdqa %xmm11,112(%rsp) pshufd $0x00,%xmm15,%xmm12 pshufd $0x55,%xmm15,%xmm13 movdqa %xmm12,128-256(%rcx) pshufd $0xaa,%xmm15,%xmm14 movdqa %xmm13,144-256(%rcx) pshufd $0xff,%xmm15,%xmm15 movdqa %xmm14,160-256(%rcx) movdqa %xmm15,176-256(%rcx) pshufd $0x00,%xmm7,%xmm4 pshufd $0x55,%xmm7,%xmm5 movdqa %xmm4,192-256(%rcx) pshufd $0xaa,%xmm7,%xmm6 movdqa %xmm5,208-256(%rcx) pshufd $0xff,%xmm7,%xmm7 movdqa %xmm6,224-256(%rcx) movdqa %xmm7,240-256(%rcx) pshufd $0x00,%xmm3,%xmm0 pshufd $0x55,%xmm3,%xmm1 paddd L$inc(%rip),%xmm0 pshufd $0xaa,%xmm3,%xmm2 movdqa %xmm1,272-256(%rcx) pshufd $0xff,%xmm3,%xmm3 movdqa %xmm2,288-256(%rcx) movdqa %xmm3,304-256(%rcx) jmp L$oop_enter4x .p2align 5 L$oop_outer4x: movdqa 64(%rsp),%xmm8 movdqa 80(%rsp),%xmm9 movdqa 96(%rsp),%xmm10 movdqa 112(%rsp),%xmm11 movdqa 128-256(%rcx),%xmm12 movdqa 144-256(%rcx),%xmm13 movdqa 160-256(%rcx),%xmm14 movdqa 176-256(%rcx),%xmm15 movdqa 192-256(%rcx),%xmm4 movdqa 208-256(%rcx),%xmm5 movdqa 224-256(%rcx),%xmm6 movdqa 240-256(%rcx),%xmm7 movdqa 256-256(%rcx),%xmm0 movdqa 272-256(%rcx),%xmm1 movdqa 288-256(%rcx),%xmm2 movdqa 304-256(%rcx),%xmm3 paddd L$four(%rip),%xmm0 L$oop_enter4x: movdqa %xmm6,32(%rsp) movdqa %xmm7,48(%rsp) movdqa (%r10),%xmm7 movl $10,%eax movdqa %xmm0,256-256(%rcx) jmp L$oop4x .p2align 5 L$oop4x: paddd %xmm12,%xmm8 paddd %xmm13,%xmm9 pxor %xmm8,%xmm0 pxor %xmm9,%xmm1 .byte 102,15,56,0,199 .byte 102,15,56,0,207 paddd %xmm0,%xmm4 paddd %xmm1,%xmm5 pxor %xmm4,%xmm12 pxor %xmm5,%xmm13 movdqa %xmm12,%xmm6 pslld $12,%xmm12 psrld $20,%xmm6 movdqa %xmm13,%xmm7 pslld $12,%xmm13 por %xmm6,%xmm12 psrld $20,%xmm7 movdqa (%r11),%xmm6 por %xmm7,%xmm13 paddd %xmm12,%xmm8 paddd %xmm13,%xmm9 pxor %xmm8,%xmm0 pxor %xmm9,%xmm1 .byte 102,15,56,0,198 .byte 102,15,56,0,206 paddd %xmm0,%xmm4 paddd %xmm1,%xmm5 pxor %xmm4,%xmm12 pxor %xmm5,%xmm13 movdqa %xmm12,%xmm7 pslld $7,%xmm12 psrld $25,%xmm7 movdqa %xmm13,%xmm6 pslld $7,%xmm13 por %xmm7,%xmm12 psrld $25,%xmm6 movdqa (%r10),%xmm7 por %xmm6,%xmm13 movdqa %xmm4,0(%rsp) movdqa %xmm5,16(%rsp) movdqa 32(%rsp),%xmm4 movdqa 48(%rsp),%xmm5 paddd %xmm14,%xmm10 paddd %xmm15,%xmm11 pxor %xmm10,%xmm2 pxor %xmm11,%xmm3 .byte 102,15,56,0,215 .byte 102,15,56,0,223 paddd %xmm2,%xmm4 paddd %xmm3,%xmm5 pxor %xmm4,%xmm14 pxor %xmm5,%xmm15 movdqa %xmm14,%xmm6 pslld $12,%xmm14 psrld $20,%xmm6 movdqa %xmm15,%xmm7 pslld $12,%xmm15 por %xmm6,%xmm14 psrld $20,%xmm7 movdqa (%r11),%xmm6 por %xmm7,%xmm15 paddd %xmm14,%xmm10 paddd %xmm15,%xmm11 pxor %xmm10,%xmm2 pxor %xmm11,%xmm3 .byte 102,15,56,0,214 .byte 102,15,56,0,222 paddd %xmm2,%xmm4 paddd %xmm3,%xmm5 pxor %xmm4,%xmm14 pxor %xmm5,%xmm15 movdqa %xmm14,%xmm7 pslld $7,%xmm14 psrld $25,%xmm7 movdqa %xmm15,%xmm6 pslld $7,%xmm15 por %xmm7,%xmm14 psrld $25,%xmm6 movdqa (%r10),%xmm7 por %xmm6,%xmm15 paddd %xmm13,%xmm8 paddd %xmm14,%xmm9 pxor %xmm8,%xmm3 pxor %xmm9,%xmm0 .byte 102,15,56,0,223 .byte 102,15,56,0,199 paddd %xmm3,%xmm4 paddd %xmm0,%xmm5 pxor %xmm4,%xmm13 pxor %xmm5,%xmm14 movdqa %xmm13,%xmm6 pslld $12,%xmm13 psrld $20,%xmm6 movdqa %xmm14,%xmm7 pslld $12,%xmm14 por %xmm6,%xmm13 psrld $20,%xmm7 movdqa (%r11),%xmm6 por %xmm7,%xmm14 paddd %xmm13,%xmm8 paddd %xmm14,%xmm9 pxor %xmm8,%xmm3 pxor %xmm9,%xmm0 .byte 102,15,56,0,222 .byte 102,15,56,0,198 paddd %xmm3,%xmm4 paddd %xmm0,%xmm5 pxor %xmm4,%xmm13 pxor %xmm5,%xmm14 movdqa %xmm13,%xmm7 pslld $7,%xmm13 psrld $25,%xmm7 movdqa %xmm14,%xmm6 pslld $7,%xmm14 por %xmm7,%xmm13 psrld $25,%xmm6 movdqa (%r10),%xmm7 por %xmm6,%xmm14 movdqa %xmm4,32(%rsp) movdqa %xmm5,48(%rsp) movdqa 0(%rsp),%xmm4 movdqa 16(%rsp),%xmm5 paddd %xmm15,%xmm10 paddd %xmm12,%xmm11 pxor %xmm10,%xmm1 pxor %xmm11,%xmm2 .byte 102,15,56,0,207 .byte 102,15,56,0,215 paddd %xmm1,%xmm4 paddd %xmm2,%xmm5 pxor %xmm4,%xmm15 pxor %xmm5,%xmm12 movdqa %xmm15,%xmm6 pslld $12,%xmm15 psrld $20,%xmm6 movdqa %xmm12,%xmm7 pslld $12,%xmm12 por %xmm6,%xmm15 psrld $20,%xmm7 movdqa (%r11),%xmm6 por %xmm7,%xmm12 paddd %xmm15,%xmm10 paddd %xmm12,%xmm11 pxor %xmm10,%xmm1 pxor %xmm11,%xmm2 .byte 102,15,56,0,206 .byte 102,15,56,0,214 paddd %xmm1,%xmm4 paddd %xmm2,%xmm5 pxor %xmm4,%xmm15 pxor %xmm5,%xmm12 movdqa %xmm15,%xmm7 pslld $7,%xmm15 psrld $25,%xmm7 movdqa %xmm12,%xmm6 pslld $7,%xmm12 por %xmm7,%xmm15 psrld $25,%xmm6 movdqa (%r10),%xmm7 por %xmm6,%xmm12 decl %eax jnz L$oop4x paddd 64(%rsp),%xmm8 paddd 80(%rsp),%xmm9 paddd 96(%rsp),%xmm10 paddd 112(%rsp),%xmm11 movdqa %xmm8,%xmm6 punpckldq %xmm9,%xmm8 movdqa %xmm10,%xmm7 punpckldq %xmm11,%xmm10 punpckhdq %xmm9,%xmm6 punpckhdq %xmm11,%xmm7 movdqa %xmm8,%xmm9 punpcklqdq %xmm10,%xmm8 movdqa %xmm6,%xmm11 punpcklqdq %xmm7,%xmm6 punpckhqdq %xmm10,%xmm9 punpckhqdq %xmm7,%xmm11 paddd 128-256(%rcx),%xmm12 paddd 144-256(%rcx),%xmm13 paddd 160-256(%rcx),%xmm14 paddd 176-256(%rcx),%xmm15 movdqa %xmm8,0(%rsp) movdqa %xmm9,16(%rsp) movdqa 32(%rsp),%xmm8 movdqa 48(%rsp),%xmm9 movdqa %xmm12,%xmm10 punpckldq %xmm13,%xmm12 movdqa %xmm14,%xmm7 punpckldq %xmm15,%xmm14 punpckhdq %xmm13,%xmm10 punpckhdq %xmm15,%xmm7 movdqa %xmm12,%xmm13 punpcklqdq %xmm14,%xmm12 movdqa %xmm10,%xmm15 punpcklqdq %xmm7,%xmm10 punpckhqdq %xmm14,%xmm13 punpckhqdq %xmm7,%xmm15 paddd 192-256(%rcx),%xmm4 paddd 208-256(%rcx),%xmm5 paddd 224-256(%rcx),%xmm8 paddd 240-256(%rcx),%xmm9 movdqa %xmm6,32(%rsp) movdqa %xmm11,48(%rsp) movdqa %xmm4,%xmm14 punpckldq %xmm5,%xmm4 movdqa %xmm8,%xmm7 punpckldq %xmm9,%xmm8 punpckhdq %xmm5,%xmm14 punpckhdq %xmm9,%xmm7 movdqa %xmm4,%xmm5 punpcklqdq %xmm8,%xmm4 movdqa %xmm14,%xmm9 punpcklqdq %xmm7,%xmm14 punpckhqdq %xmm8,%xmm5 punpckhqdq %xmm7,%xmm9 paddd 256-256(%rcx),%xmm0 paddd 272-256(%rcx),%xmm1 paddd 288-256(%rcx),%xmm2 paddd 304-256(%rcx),%xmm3 movdqa %xmm0,%xmm8 punpckldq %xmm1,%xmm0 movdqa %xmm2,%xmm7 punpckldq %xmm3,%xmm2 punpckhdq %xmm1,%xmm8 punpckhdq %xmm3,%xmm7 movdqa %xmm0,%xmm1 punpcklqdq %xmm2,%xmm0 movdqa %xmm8,%xmm3 punpcklqdq %xmm7,%xmm8 punpckhqdq %xmm2,%xmm1 punpckhqdq %xmm7,%xmm3 cmpq $256,%rdx jb L$tail4x movdqu 0(%rsi),%xmm6 movdqu 16(%rsi),%xmm11 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm7 pxor 0(%rsp),%xmm6 pxor %xmm12,%xmm11 pxor %xmm4,%xmm2 pxor %xmm0,%xmm7 movdqu %xmm6,0(%rdi) movdqu 64(%rsi),%xmm6 movdqu %xmm11,16(%rdi) movdqu 80(%rsi),%xmm11 movdqu %xmm2,32(%rdi) movdqu 96(%rsi),%xmm2 movdqu %xmm7,48(%rdi) movdqu 112(%rsi),%xmm7 leaq 128(%rsi),%rsi pxor 16(%rsp),%xmm6 pxor %xmm13,%xmm11 pxor %xmm5,%xmm2 pxor %xmm1,%xmm7 movdqu %xmm6,64(%rdi) movdqu 0(%rsi),%xmm6 movdqu %xmm11,80(%rdi) movdqu 16(%rsi),%xmm11 movdqu %xmm2,96(%rdi) movdqu 32(%rsi),%xmm2 movdqu %xmm7,112(%rdi) leaq 128(%rdi),%rdi movdqu 48(%rsi),%xmm7 pxor 32(%rsp),%xmm6 pxor %xmm10,%xmm11 pxor %xmm14,%xmm2 pxor %xmm8,%xmm7 movdqu %xmm6,0(%rdi) movdqu 64(%rsi),%xmm6 movdqu %xmm11,16(%rdi) movdqu 80(%rsi),%xmm11 movdqu %xmm2,32(%rdi) movdqu 96(%rsi),%xmm2 movdqu %xmm7,48(%rdi) movdqu 112(%rsi),%xmm7 leaq 128(%rsi),%rsi pxor 48(%rsp),%xmm6 pxor %xmm15,%xmm11 pxor %xmm9,%xmm2 pxor %xmm3,%xmm7 movdqu %xmm6,64(%rdi) movdqu %xmm11,80(%rdi) movdqu %xmm2,96(%rdi) movdqu %xmm7,112(%rdi) leaq 128(%rdi),%rdi subq $256,%rdx jnz L$oop_outer4x jmp L$done4x L$tail4x: cmpq $192,%rdx jae L$192_or_more4x cmpq $128,%rdx jae L$128_or_more4x cmpq $64,%rdx jae L$64_or_more4x xorq %r10,%r10 movdqa %xmm12,16(%rsp) movdqa %xmm4,32(%rsp) movdqa %xmm0,48(%rsp) jmp L$oop_tail4x .p2align 5 L$64_or_more4x: movdqu 0(%rsi),%xmm6 movdqu 16(%rsi),%xmm11 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm7 pxor 0(%rsp),%xmm6 pxor %xmm12,%xmm11 pxor %xmm4,%xmm2 pxor %xmm0,%xmm7 movdqu %xmm6,0(%rdi) movdqu %xmm11,16(%rdi) movdqu %xmm2,32(%rdi) movdqu %xmm7,48(%rdi) je L$done4x movdqa 16(%rsp),%xmm6 leaq 64(%rsi),%rsi xorq %r10,%r10 movdqa %xmm6,0(%rsp) movdqa %xmm13,16(%rsp) leaq 64(%rdi),%rdi movdqa %xmm5,32(%rsp) subq $64,%rdx movdqa %xmm1,48(%rsp) jmp L$oop_tail4x .p2align 5 L$128_or_more4x: movdqu 0(%rsi),%xmm6 movdqu 16(%rsi),%xmm11 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm7 pxor 0(%rsp),%xmm6 pxor %xmm12,%xmm11 pxor %xmm4,%xmm2 pxor %xmm0,%xmm7 movdqu %xmm6,0(%rdi) movdqu 64(%rsi),%xmm6 movdqu %xmm11,16(%rdi) movdqu 80(%rsi),%xmm11 movdqu %xmm2,32(%rdi) movdqu 96(%rsi),%xmm2 movdqu %xmm7,48(%rdi) movdqu 112(%rsi),%xmm7 pxor 16(%rsp),%xmm6 pxor %xmm13,%xmm11 pxor %xmm5,%xmm2 pxor %xmm1,%xmm7 movdqu %xmm6,64(%rdi) movdqu %xmm11,80(%rdi) movdqu %xmm2,96(%rdi) movdqu %xmm7,112(%rdi) je L$done4x movdqa 32(%rsp),%xmm6 leaq 128(%rsi),%rsi xorq %r10,%r10 movdqa %xmm6,0(%rsp) movdqa %xmm10,16(%rsp) leaq 128(%rdi),%rdi movdqa %xmm14,32(%rsp) subq $128,%rdx movdqa %xmm8,48(%rsp) jmp L$oop_tail4x .p2align 5 L$192_or_more4x: movdqu 0(%rsi),%xmm6 movdqu 16(%rsi),%xmm11 movdqu 32(%rsi),%xmm2 movdqu 48(%rsi),%xmm7 pxor 0(%rsp),%xmm6 pxor %xmm12,%xmm11 pxor %xmm4,%xmm2 pxor %xmm0,%xmm7 movdqu %xmm6,0(%rdi) movdqu 64(%rsi),%xmm6 movdqu %xmm11,16(%rdi) movdqu 80(%rsi),%xmm11 movdqu %xmm2,32(%rdi) movdqu 96(%rsi),%xmm2 movdqu %xmm7,48(%rdi) movdqu 112(%rsi),%xmm7 leaq 128(%rsi),%rsi pxor 16(%rsp),%xmm6 pxor %xmm13,%xmm11 pxor %xmm5,%xmm2 pxor %xmm1,%xmm7 movdqu %xmm6,64(%rdi) movdqu 0(%rsi),%xmm6 movdqu %xmm11,80(%rdi) movdqu 16(%rsi),%xmm11 movdqu %xmm2,96(%rdi) movdqu 32(%rsi),%xmm2 movdqu %xmm7,112(%rdi) leaq 128(%rdi),%rdi movdqu 48(%rsi),%xmm7 pxor 32(%rsp),%xmm6 pxor %xmm10,%xmm11 pxor %xmm14,%xmm2 pxor %xmm8,%xmm7 movdqu %xmm6,0(%rdi) movdqu %xmm11,16(%rdi) movdqu %xmm2,32(%rdi) movdqu %xmm7,48(%rdi) je L$done4x movdqa 48(%rsp),%xmm6 leaq 64(%rsi),%rsi xorq %r10,%r10 movdqa %xmm6,0(%rsp) movdqa %xmm15,16(%rsp) leaq 64(%rdi),%rdi movdqa %xmm9,32(%rsp) subq $192,%rdx movdqa %xmm3,48(%rsp) L$oop_tail4x: movzbl (%rsi,%r10,1),%eax movzbl (%rsp,%r10,1),%ecx leaq 1(%r10),%r10 xorl %ecx,%eax movb %al,-1(%rdi,%r10,1) decq %rdx jnz L$oop_tail4x L$done4x: leaq (%r9),%rsp L$4x_epilogue: ret .p2align 5 ChaCha20_8x: L$ChaCha20_8x: movq %rsp,%r9 subq $0x280+8,%rsp andq $-32,%rsp vzeroupper vbroadcasti128 L$sigma(%rip),%ymm11 vbroadcasti128 (%rcx),%ymm3 vbroadcasti128 16(%rcx),%ymm15 vbroadcasti128 (%r8),%ymm7 leaq 256(%rsp),%rcx leaq 512(%rsp),%rax leaq L$rot16(%rip),%r10 leaq L$rot24(%rip),%r11 vpshufd $0x00,%ymm11,%ymm8 vpshufd $0x55,%ymm11,%ymm9 vmovdqa %ymm8,128-256(%rcx) vpshufd $0xaa,%ymm11,%ymm10 vmovdqa %ymm9,160-256(%rcx) vpshufd $0xff,%ymm11,%ymm11 vmovdqa %ymm10,192-256(%rcx) vmovdqa %ymm11,224-256(%rcx) vpshufd $0x00,%ymm3,%ymm0 vpshufd $0x55,%ymm3,%ymm1 vmovdqa %ymm0,256-256(%rcx) vpshufd $0xaa,%ymm3,%ymm2 vmovdqa %ymm1,288-256(%rcx) vpshufd $0xff,%ymm3,%ymm3 vmovdqa %ymm2,320-256(%rcx) vmovdqa %ymm3,352-256(%rcx) vpshufd $0x00,%ymm15,%ymm12 vpshufd $0x55,%ymm15,%ymm13 vmovdqa %ymm12,384-512(%rax) vpshufd $0xaa,%ymm15,%ymm14 vmovdqa %ymm13,416-512(%rax) vpshufd $0xff,%ymm15,%ymm15 vmovdqa %ymm14,448-512(%rax) vmovdqa %ymm15,480-512(%rax) vpshufd $0x00,%ymm7,%ymm4 vpshufd $0x55,%ymm7,%ymm5 vpaddd L$incy(%rip),%ymm4,%ymm4 vpshufd $0xaa,%ymm7,%ymm6 vmovdqa %ymm5,544-512(%rax) vpshufd $0xff,%ymm7,%ymm7 vmovdqa %ymm6,576-512(%rax) vmovdqa %ymm7,608-512(%rax) jmp L$oop_enter8x .p2align 5 L$oop_outer8x: vmovdqa 128-256(%rcx),%ymm8 vmovdqa 160-256(%rcx),%ymm9 vmovdqa 192-256(%rcx),%ymm10 vmovdqa 224-256(%rcx),%ymm11 vmovdqa 256-256(%rcx),%ymm0 vmovdqa 288-256(%rcx),%ymm1 vmovdqa 320-256(%rcx),%ymm2 vmovdqa 352-256(%rcx),%ymm3 vmovdqa 384-512(%rax),%ymm12 vmovdqa 416-512(%rax),%ymm13 vmovdqa 448-512(%rax),%ymm14 vmovdqa 480-512(%rax),%ymm15 vmovdqa 512-512(%rax),%ymm4 vmovdqa 544-512(%rax),%ymm5 vmovdqa 576-512(%rax),%ymm6 vmovdqa 608-512(%rax),%ymm7 vpaddd L$eight(%rip),%ymm4,%ymm4 L$oop_enter8x: vmovdqa %ymm14,64(%rsp) vmovdqa %ymm15,96(%rsp) vbroadcasti128 (%r10),%ymm15 vmovdqa %ymm4,512-512(%rax) movl $10,%eax jmp L$oop8x .p2align 5 L$oop8x: vpaddd %ymm0,%ymm8,%ymm8 vpxor %ymm4,%ymm8,%ymm4 vpshufb %ymm15,%ymm4,%ymm4 vpaddd %ymm1,%ymm9,%ymm9 vpxor %ymm5,%ymm9,%ymm5 vpshufb %ymm15,%ymm5,%ymm5 vpaddd %ymm4,%ymm12,%ymm12 vpxor %ymm0,%ymm12,%ymm0 vpslld $12,%ymm0,%ymm14 vpsrld $20,%ymm0,%ymm0 vpor %ymm0,%ymm14,%ymm0 vbroadcasti128 (%r11),%ymm14 vpaddd %ymm5,%ymm13,%ymm13 vpxor %ymm1,%ymm13,%ymm1 vpslld $12,%ymm1,%ymm15 vpsrld $20,%ymm1,%ymm1 vpor %ymm1,%ymm15,%ymm1 vpaddd %ymm0,%ymm8,%ymm8 vpxor %ymm4,%ymm8,%ymm4 vpshufb %ymm14,%ymm4,%ymm4 vpaddd %ymm1,%ymm9,%ymm9 vpxor %ymm5,%ymm9,%ymm5 vpshufb %ymm14,%ymm5,%ymm5 vpaddd %ymm4,%ymm12,%ymm12 vpxor %ymm0,%ymm12,%ymm0 vpslld $7,%ymm0,%ymm15 vpsrld $25,%ymm0,%ymm0 vpor %ymm0,%ymm15,%ymm0 vbroadcasti128 (%r10),%ymm15 vpaddd %ymm5,%ymm13,%ymm13 vpxor %ymm1,%ymm13,%ymm1 vpslld $7,%ymm1,%ymm14 vpsrld $25,%ymm1,%ymm1 vpor %ymm1,%ymm14,%ymm1 vmovdqa %ymm12,0(%rsp) vmovdqa %ymm13,32(%rsp) vmovdqa 64(%rsp),%ymm12 vmovdqa 96(%rsp),%ymm13 vpaddd %ymm2,%ymm10,%ymm10 vpxor %ymm6,%ymm10,%ymm6 vpshufb %ymm15,%ymm6,%ymm6 vpaddd %ymm3,%ymm11,%ymm11 vpxor %ymm7,%ymm11,%ymm7 vpshufb %ymm15,%ymm7,%ymm7 vpaddd %ymm6,%ymm12,%ymm12 vpxor %ymm2,%ymm12,%ymm2 vpslld $12,%ymm2,%ymm14 vpsrld $20,%ymm2,%ymm2 vpor %ymm2,%ymm14,%ymm2 vbroadcasti128 (%r11),%ymm14 vpaddd %ymm7,%ymm13,%ymm13 vpxor %ymm3,%ymm13,%ymm3 vpslld $12,%ymm3,%ymm15 vpsrld $20,%ymm3,%ymm3 vpor %ymm3,%ymm15,%ymm3 vpaddd %ymm2,%ymm10,%ymm10 vpxor %ymm6,%ymm10,%ymm6 vpshufb %ymm14,%ymm6,%ymm6 vpaddd %ymm3,%ymm11,%ymm11 vpxor %ymm7,%ymm11,%ymm7 vpshufb %ymm14,%ymm7,%ymm7 vpaddd %ymm6,%ymm12,%ymm12 vpxor %ymm2,%ymm12,%ymm2 vpslld $7,%ymm2,%ymm15 vpsrld $25,%ymm2,%ymm2 vpor %ymm2,%ymm15,%ymm2 vbroadcasti128 (%r10),%ymm15 vpaddd %ymm7,%ymm13,%ymm13 vpxor %ymm3,%ymm13,%ymm3 vpslld $7,%ymm3,%ymm14 vpsrld $25,%ymm3,%ymm3 vpor %ymm3,%ymm14,%ymm3 vpaddd %ymm1,%ymm8,%ymm8 vpxor %ymm7,%ymm8,%ymm7 vpshufb %ymm15,%ymm7,%ymm7 vpaddd %ymm2,%ymm9,%ymm9 vpxor %ymm4,%ymm9,%ymm4 vpshufb %ymm15,%ymm4,%ymm4 vpaddd %ymm7,%ymm12,%ymm12 vpxor %ymm1,%ymm12,%ymm1 vpslld $12,%ymm1,%ymm14 vpsrld $20,%ymm1,%ymm1 vpor %ymm1,%ymm14,%ymm1 vbroadcasti128 (%r11),%ymm14 vpaddd %ymm4,%ymm13,%ymm13 vpxor %ymm2,%ymm13,%ymm2 vpslld $12,%ymm2,%ymm15 vpsrld $20,%ymm2,%ymm2 vpor %ymm2,%ymm15,%ymm2 vpaddd %ymm1,%ymm8,%ymm8 vpxor %ymm7,%ymm8,%ymm7 vpshufb %ymm14,%ymm7,%ymm7 vpaddd %ymm2,%ymm9,%ymm9 vpxor %ymm4,%ymm9,%ymm4 vpshufb %ymm14,%ymm4,%ymm4 vpaddd %ymm7,%ymm12,%ymm12 vpxor %ymm1,%ymm12,%ymm1 vpslld $7,%ymm1,%ymm15 vpsrld $25,%ymm1,%ymm1 vpor %ymm1,%ymm15,%ymm1 vbroadcasti128 (%r10),%ymm15 vpaddd %ymm4,%ymm13,%ymm13 vpxor %ymm2,%ymm13,%ymm2 vpslld $7,%ymm2,%ymm14 vpsrld $25,%ymm2,%ymm2 vpor %ymm2,%ymm14,%ymm2 vmovdqa %ymm12,64(%rsp) vmovdqa %ymm13,96(%rsp) vmovdqa 0(%rsp),%ymm12 vmovdqa 32(%rsp),%ymm13 vpaddd %ymm3,%ymm10,%ymm10 vpxor %ymm5,%ymm10,%ymm5 vpshufb %ymm15,%ymm5,%ymm5 vpaddd %ymm0,%ymm11,%ymm11 vpxor %ymm6,%ymm11,%ymm6 vpshufb %ymm15,%ymm6,%ymm6 vpaddd %ymm5,%ymm12,%ymm12 vpxor %ymm3,%ymm12,%ymm3 vpslld $12,%ymm3,%ymm14 vpsrld $20,%ymm3,%ymm3 vpor %ymm3,%ymm14,%ymm3 vbroadcasti128 (%r11),%ymm14 vpaddd %ymm6,%ymm13,%ymm13 vpxor %ymm0,%ymm13,%ymm0 vpslld $12,%ymm0,%ymm15 vpsrld $20,%ymm0,%ymm0 vpor %ymm0,%ymm15,%ymm0 vpaddd %ymm3,%ymm10,%ymm10 vpxor %ymm5,%ymm10,%ymm5 vpshufb %ymm14,%ymm5,%ymm5 vpaddd %ymm0,%ymm11,%ymm11 vpxor %ymm6,%ymm11,%ymm6 vpshufb %ymm14,%ymm6,%ymm6 vpaddd %ymm5,%ymm12,%ymm12 vpxor %ymm3,%ymm12,%ymm3 vpslld $7,%ymm3,%ymm15 vpsrld $25,%ymm3,%ymm3 vpor %ymm3,%ymm15,%ymm3 vbroadcasti128 (%r10),%ymm15 vpaddd %ymm6,%ymm13,%ymm13 vpxor %ymm0,%ymm13,%ymm0 vpslld $7,%ymm0,%ymm14 vpsrld $25,%ymm0,%ymm0 vpor %ymm0,%ymm14,%ymm0 decl %eax jnz L$oop8x leaq 512(%rsp),%rax vpaddd 128-256(%rcx),%ymm8,%ymm8 vpaddd 160-256(%rcx),%ymm9,%ymm9 vpaddd 192-256(%rcx),%ymm10,%ymm10 vpaddd 224-256(%rcx),%ymm11,%ymm11 vpunpckldq %ymm9,%ymm8,%ymm14 vpunpckldq %ymm11,%ymm10,%ymm15 vpunpckhdq %ymm9,%ymm8,%ymm8 vpunpckhdq %ymm11,%ymm10,%ymm10 vpunpcklqdq %ymm15,%ymm14,%ymm9 vpunpckhqdq %ymm15,%ymm14,%ymm14 vpunpcklqdq %ymm10,%ymm8,%ymm11 vpunpckhqdq %ymm10,%ymm8,%ymm8 vpaddd 256-256(%rcx),%ymm0,%ymm0 vpaddd 288-256(%rcx),%ymm1,%ymm1 vpaddd 320-256(%rcx),%ymm2,%ymm2 vpaddd 352-256(%rcx),%ymm3,%ymm3 vpunpckldq %ymm1,%ymm0,%ymm10 vpunpckldq %ymm3,%ymm2,%ymm15 vpunpckhdq %ymm1,%ymm0,%ymm0 vpunpckhdq %ymm3,%ymm2,%ymm2 vpunpcklqdq %ymm15,%ymm10,%ymm1 vpunpckhqdq %ymm15,%ymm10,%ymm10 vpunpcklqdq %ymm2,%ymm0,%ymm3 vpunpckhqdq %ymm2,%ymm0,%ymm0 vperm2i128 $0x20,%ymm1,%ymm9,%ymm15 vperm2i128 $0x31,%ymm1,%ymm9,%ymm1 vperm2i128 $0x20,%ymm10,%ymm14,%ymm9 vperm2i128 $0x31,%ymm10,%ymm14,%ymm10 vperm2i128 $0x20,%ymm3,%ymm11,%ymm14 vperm2i128 $0x31,%ymm3,%ymm11,%ymm3 vperm2i128 $0x20,%ymm0,%ymm8,%ymm11 vperm2i128 $0x31,%ymm0,%ymm8,%ymm0 vmovdqa %ymm15,0(%rsp) vmovdqa %ymm9,32(%rsp) vmovdqa 64(%rsp),%ymm15 vmovdqa 96(%rsp),%ymm9 vpaddd 384-512(%rax),%ymm12,%ymm12 vpaddd 416-512(%rax),%ymm13,%ymm13 vpaddd 448-512(%rax),%ymm15,%ymm15 vpaddd 480-512(%rax),%ymm9,%ymm9 vpunpckldq %ymm13,%ymm12,%ymm2 vpunpckldq %ymm9,%ymm15,%ymm8 vpunpckhdq %ymm13,%ymm12,%ymm12 vpunpckhdq %ymm9,%ymm15,%ymm15 vpunpcklqdq %ymm8,%ymm2,%ymm13 vpunpckhqdq %ymm8,%ymm2,%ymm2 vpunpcklqdq %ymm15,%ymm12,%ymm9 vpunpckhqdq %ymm15,%ymm12,%ymm12 vpaddd 512-512(%rax),%ymm4,%ymm4 vpaddd 544-512(%rax),%ymm5,%ymm5 vpaddd 576-512(%rax),%ymm6,%ymm6 vpaddd 608-512(%rax),%ymm7,%ymm7 vpunpckldq %ymm5,%ymm4,%ymm15 vpunpckldq %ymm7,%ymm6,%ymm8 vpunpckhdq %ymm5,%ymm4,%ymm4 vpunpckhdq %ymm7,%ymm6,%ymm6 vpunpcklqdq %ymm8,%ymm15,%ymm5 vpunpckhqdq %ymm8,%ymm15,%ymm15 vpunpcklqdq %ymm6,%ymm4,%ymm7 vpunpckhqdq %ymm6,%ymm4,%ymm4 vperm2i128 $0x20,%ymm5,%ymm13,%ymm8 vperm2i128 $0x31,%ymm5,%ymm13,%ymm5 vperm2i128 $0x20,%ymm15,%ymm2,%ymm13 vperm2i128 $0x31,%ymm15,%ymm2,%ymm15 vperm2i128 $0x20,%ymm7,%ymm9,%ymm2 vperm2i128 $0x31,%ymm7,%ymm9,%ymm7 vperm2i128 $0x20,%ymm4,%ymm12,%ymm9 vperm2i128 $0x31,%ymm4,%ymm12,%ymm4 vmovdqa 0(%rsp),%ymm6 vmovdqa 32(%rsp),%ymm12 cmpq $512,%rdx jb L$tail8x vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 leaq 128(%rsi),%rsi vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) leaq 128(%rdi),%rdi vpxor 0(%rsi),%ymm12,%ymm12 vpxor 32(%rsi),%ymm13,%ymm13 vpxor 64(%rsi),%ymm10,%ymm10 vpxor 96(%rsi),%ymm15,%ymm15 leaq 128(%rsi),%rsi vmovdqu %ymm12,0(%rdi) vmovdqu %ymm13,32(%rdi) vmovdqu %ymm10,64(%rdi) vmovdqu %ymm15,96(%rdi) leaq 128(%rdi),%rdi vpxor 0(%rsi),%ymm14,%ymm14 vpxor 32(%rsi),%ymm2,%ymm2 vpxor 64(%rsi),%ymm3,%ymm3 vpxor 96(%rsi),%ymm7,%ymm7 leaq 128(%rsi),%rsi vmovdqu %ymm14,0(%rdi) vmovdqu %ymm2,32(%rdi) vmovdqu %ymm3,64(%rdi) vmovdqu %ymm7,96(%rdi) leaq 128(%rdi),%rdi vpxor 0(%rsi),%ymm11,%ymm11 vpxor 32(%rsi),%ymm9,%ymm9 vpxor 64(%rsi),%ymm0,%ymm0 vpxor 96(%rsi),%ymm4,%ymm4 leaq 128(%rsi),%rsi vmovdqu %ymm11,0(%rdi) vmovdqu %ymm9,32(%rdi) vmovdqu %ymm0,64(%rdi) vmovdqu %ymm4,96(%rdi) leaq 128(%rdi),%rdi subq $512,%rdx jnz L$oop_outer8x jmp L$done8x L$tail8x: cmpq $448,%rdx jae L$448_or_more8x cmpq $384,%rdx jae L$384_or_more8x cmpq $320,%rdx jae L$320_or_more8x cmpq $256,%rdx jae L$256_or_more8x cmpq $192,%rdx jae L$192_or_more8x cmpq $128,%rdx jae L$128_or_more8x cmpq $64,%rdx jae L$64_or_more8x xorq %r10,%r10 vmovdqa %ymm6,0(%rsp) vmovdqa %ymm8,32(%rsp) jmp L$oop_tail8x .p2align 5 L$64_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) je L$done8x leaq 64(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm1,0(%rsp) leaq 64(%rdi),%rdi subq $64,%rdx vmovdqa %ymm5,32(%rsp) jmp L$oop_tail8x .p2align 5 L$128_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) je L$done8x leaq 128(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm12,0(%rsp) leaq 128(%rdi),%rdi subq $128,%rdx vmovdqa %ymm13,32(%rsp) jmp L$oop_tail8x .p2align 5 L$192_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vpxor 128(%rsi),%ymm12,%ymm12 vpxor 160(%rsi),%ymm13,%ymm13 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) vmovdqu %ymm12,128(%rdi) vmovdqu %ymm13,160(%rdi) je L$done8x leaq 192(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm10,0(%rsp) leaq 192(%rdi),%rdi subq $192,%rdx vmovdqa %ymm15,32(%rsp) jmp L$oop_tail8x .p2align 5 L$256_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vpxor 128(%rsi),%ymm12,%ymm12 vpxor 160(%rsi),%ymm13,%ymm13 vpxor 192(%rsi),%ymm10,%ymm10 vpxor 224(%rsi),%ymm15,%ymm15 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) vmovdqu %ymm12,128(%rdi) vmovdqu %ymm13,160(%rdi) vmovdqu %ymm10,192(%rdi) vmovdqu %ymm15,224(%rdi) je L$done8x leaq 256(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm14,0(%rsp) leaq 256(%rdi),%rdi subq $256,%rdx vmovdqa %ymm2,32(%rsp) jmp L$oop_tail8x .p2align 5 L$320_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vpxor 128(%rsi),%ymm12,%ymm12 vpxor 160(%rsi),%ymm13,%ymm13 vpxor 192(%rsi),%ymm10,%ymm10 vpxor 224(%rsi),%ymm15,%ymm15 vpxor 256(%rsi),%ymm14,%ymm14 vpxor 288(%rsi),%ymm2,%ymm2 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) vmovdqu %ymm12,128(%rdi) vmovdqu %ymm13,160(%rdi) vmovdqu %ymm10,192(%rdi) vmovdqu %ymm15,224(%rdi) vmovdqu %ymm14,256(%rdi) vmovdqu %ymm2,288(%rdi) je L$done8x leaq 320(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm3,0(%rsp) leaq 320(%rdi),%rdi subq $320,%rdx vmovdqa %ymm7,32(%rsp) jmp L$oop_tail8x .p2align 5 L$384_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vpxor 128(%rsi),%ymm12,%ymm12 vpxor 160(%rsi),%ymm13,%ymm13 vpxor 192(%rsi),%ymm10,%ymm10 vpxor 224(%rsi),%ymm15,%ymm15 vpxor 256(%rsi),%ymm14,%ymm14 vpxor 288(%rsi),%ymm2,%ymm2 vpxor 320(%rsi),%ymm3,%ymm3 vpxor 352(%rsi),%ymm7,%ymm7 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) vmovdqu %ymm12,128(%rdi) vmovdqu %ymm13,160(%rdi) vmovdqu %ymm10,192(%rdi) vmovdqu %ymm15,224(%rdi) vmovdqu %ymm14,256(%rdi) vmovdqu %ymm2,288(%rdi) vmovdqu %ymm3,320(%rdi) vmovdqu %ymm7,352(%rdi) je L$done8x leaq 384(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm11,0(%rsp) leaq 384(%rdi),%rdi subq $384,%rdx vmovdqa %ymm9,32(%rsp) jmp L$oop_tail8x .p2align 5 L$448_or_more8x: vpxor 0(%rsi),%ymm6,%ymm6 vpxor 32(%rsi),%ymm8,%ymm8 vpxor 64(%rsi),%ymm1,%ymm1 vpxor 96(%rsi),%ymm5,%ymm5 vpxor 128(%rsi),%ymm12,%ymm12 vpxor 160(%rsi),%ymm13,%ymm13 vpxor 192(%rsi),%ymm10,%ymm10 vpxor 224(%rsi),%ymm15,%ymm15 vpxor 256(%rsi),%ymm14,%ymm14 vpxor 288(%rsi),%ymm2,%ymm2 vpxor 320(%rsi),%ymm3,%ymm3 vpxor 352(%rsi),%ymm7,%ymm7 vpxor 384(%rsi),%ymm11,%ymm11 vpxor 416(%rsi),%ymm9,%ymm9 vmovdqu %ymm6,0(%rdi) vmovdqu %ymm8,32(%rdi) vmovdqu %ymm1,64(%rdi) vmovdqu %ymm5,96(%rdi) vmovdqu %ymm12,128(%rdi) vmovdqu %ymm13,160(%rdi) vmovdqu %ymm10,192(%rdi) vmovdqu %ymm15,224(%rdi) vmovdqu %ymm14,256(%rdi) vmovdqu %ymm2,288(%rdi) vmovdqu %ymm3,320(%rdi) vmovdqu %ymm7,352(%rdi) vmovdqu %ymm11,384(%rdi) vmovdqu %ymm9,416(%rdi) je L$done8x leaq 448(%rsi),%rsi xorq %r10,%r10 vmovdqa %ymm0,0(%rsp) leaq 448(%rdi),%rdi subq $448,%rdx vmovdqa %ymm4,32(%rsp) L$oop_tail8x: movzbl (%rsi,%r10,1),%eax movzbl (%rsp,%r10,1),%ecx leaq 1(%r10),%r10 xorl %ecx,%eax movb %al,-1(%rdi,%r10,1) decq %rdx jnz L$oop_tail8x L$done8x: vzeroall leaq (%r9),%rsp L$8x_epilogue: ret #endif

j4yc3-mw/Viren

23,634

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/vpaes-armv7-linux32.S

// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__) .syntax unified .arch armv7-a .fpu neon #if defined(__thumb2__) .thumb #else .code 32 #endif .text .type _vpaes_consts,%object .align 7 @ totally strategic alignment _vpaes_consts: .Lk_mc_forward:@ mc_forward .quad 0x0407060500030201, 0x0C0F0E0D080B0A09 .quad 0x080B0A0904070605, 0x000302010C0F0E0D .quad 0x0C0F0E0D080B0A09, 0x0407060500030201 .quad 0x000302010C0F0E0D, 0x080B0A0904070605 .Lk_mc_backward:@ mc_backward .quad 0x0605040702010003, 0x0E0D0C0F0A09080B .quad 0x020100030E0D0C0F, 0x0A09080B06050407 .quad 0x0E0D0C0F0A09080B, 0x0605040702010003 .quad 0x0A09080B06050407, 0x020100030E0D0C0F .Lk_sr:@ sr .quad 0x0706050403020100, 0x0F0E0D0C0B0A0908 .quad 0x030E09040F0A0500, 0x0B06010C07020D08 .quad 0x0F060D040B020900, 0x070E050C030A0108 .quad 0x0B0E0104070A0D00, 0x0306090C0F020508 @ @ "Hot" constants @ .Lk_inv:@ inv, inva .quad 0x0E05060F0D080180, 0x040703090A0B0C02 .quad 0x01040A060F0B0780, 0x030D0E0C02050809 .Lk_ipt:@ input transform (lo, hi) .quad 0xC2B2E8985A2A7000, 0xCABAE09052227808 .quad 0x4C01307D317C4D00, 0xCD80B1FCB0FDCC81 .Lk_sbo:@ sbou, sbot .quad 0xD0D26D176FBDC700, 0x15AABF7AC502A878 .quad 0xCFE474A55FBB6A00, 0x8E1E90D1412B35FA .Lk_sb1:@ sb1u, sb1t .quad 0x3618D415FAE22300, 0x3BF7CCC10D2ED9EF .quad 0xB19BE18FCB503E00, 0xA5DF7A6E142AF544 .Lk_sb2:@ sb2u, sb2t .quad 0x69EB88400AE12900, 0xC2A163C8AB82234A .quad 0xE27A93C60B712400, 0x5EB7E955BC982FCD .byte 86,101,99,116,111,114,32,80,101,114,109,117,116,97,116,105,111,110,32,65,69,83,32,102,111,114,32,65,82,77,118,55,32,78,69,79,78,44,32,77,105,107,101,32,72,97,109,98,117,114,103,32,40,83,116,97,110,102,111,114,100,32,85,110,105,118,101,114,115,105,116,121,41,0 .align 2 .size _vpaes_consts,.-_vpaes_consts .align 6 @@ @@ _aes_preheat @@ @@ Fills q9-q15 as specified below. @@ .type _vpaes_preheat,%function .align 4 _vpaes_preheat: adr r10, .Lk_inv vmov.i8 q9, #0x0f @ .Lk_s0F vld1.64 {q10,q11}, [r10]! @ .Lk_inv add r10, r10, #64 @ Skip .Lk_ipt, .Lk_sbo vld1.64 {q12,q13}, [r10]! @ .Lk_sb1 vld1.64 {q14,q15}, [r10] @ .Lk_sb2 bx lr @@ @@ _aes_encrypt_core @@ @@ AES-encrypt q0. @@ @@ Inputs: @@ q0 = input @@ q9-q15 as in _vpaes_preheat @@ [r2] = scheduled keys @@ @@ Output in q0 @@ Clobbers q1-q5, r8-r11 @@ Preserves q6-q8 so you get some local vectors @@ @@ .type _vpaes_encrypt_core,%function .align 4 _vpaes_encrypt_core: mov r9, r2 ldr r8, [r2,#240] @ pull rounds adr r11, .Lk_ipt @ vmovdqa .Lk_ipt(%rip), %xmm2 # iptlo @ vmovdqa .Lk_ipt+16(%rip), %xmm3 # ipthi vld1.64 {q2, q3}, [r11] adr r11, .Lk_mc_forward+16 vld1.64 {q5}, [r9]! @ vmovdqu (%r9), %xmm5 # round0 key vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1 vtbl.8 d3, {q2}, d3 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2 vtbl.8 d5, {q3}, d1 veor q0, q1, q5 @ vpxor %xmm5, %xmm1, %xmm0 veor q0, q0, q2 @ vpxor %xmm2, %xmm0, %xmm0 @ .Lenc_entry ends with a bnz instruction which is normally paired with @ subs in .Lenc_loop. tst r8, r8 b .Lenc_entry .align 4 .Lenc_loop: @ middle of middle round add r10, r11, #0x40 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u vtbl.8 d9, {q13}, d5 vld1.64 {q1}, [r11]! @ vmovdqa -0x40(%r11,%r10), %xmm1 # .Lk_mc_forward[] vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t vtbl.8 d1, {q12}, d7 veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u vtbl.8 d11, {q15}, d5 veor q0, q0, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = A vtbl.8 d4, {q14}, d6 @ vpshufb %xmm3, %xmm14, %xmm2 # 2 = sb2t vtbl.8 d5, {q14}, d7 vld1.64 {q4}, [r10] @ vmovdqa (%r11,%r10), %xmm4 # .Lk_mc_backward[] vtbl.8 d6, {q0}, d2 @ vpshufb %xmm1, %xmm0, %xmm3 # 0 = B vtbl.8 d7, {q0}, d3 veor q2, q2, q5 @ vpxor %xmm5, %xmm2, %xmm2 # 2 = 2A @ Write to q5 instead of q0, so the table and destination registers do @ not overlap. vtbl.8 d10, {q0}, d8 @ vpshufb %xmm4, %xmm0, %xmm0 # 3 = D vtbl.8 d11, {q0}, d9 veor q3, q3, q2 @ vpxor %xmm2, %xmm3, %xmm3 # 0 = 2A+B vtbl.8 d8, {q3}, d2 @ vpshufb %xmm1, %xmm3, %xmm4 # 0 = 2B+C vtbl.8 d9, {q3}, d3 @ Here we restore the original q0/q5 usage. veor q0, q5, q3 @ vpxor %xmm3, %xmm0, %xmm0 # 3 = 2A+B+D and r11, r11, #~(1<<6) @ and $0x30, %r11 # ... mod 4 veor q0, q0, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = 2A+3B+C+D subs r8, r8, #1 @ nr-- .Lenc_entry: @ top of round vand q1, q0, q9 @ vpand %xmm0, %xmm9, %xmm1 # 0 = k vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 # 1 = i vtbl.8 d10, {q11}, d2 @ vpshufb %xmm1, %xmm11, %xmm5 # 2 = a/k vtbl.8 d11, {q11}, d3 veor q1, q1, q0 @ vpxor %xmm0, %xmm1, %xmm1 # 0 = j vtbl.8 d6, {q10}, d0 @ vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i vtbl.8 d7, {q10}, d1 vtbl.8 d8, {q10}, d2 @ vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j vtbl.8 d9, {q10}, d3 veor q3, q3, q5 @ vpxor %xmm5, %xmm3, %xmm3 # 3 = iak = 1/i + a/k veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = jak = 1/j + a/k vtbl.8 d4, {q10}, d6 @ vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak vtbl.8 d5, {q10}, d7 vtbl.8 d6, {q10}, d8 @ vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak vtbl.8 d7, {q10}, d9 veor q2, q2, q1 @ vpxor %xmm1, %xmm2, %xmm2 # 2 = io veor q3, q3, q0 @ vpxor %xmm0, %xmm3, %xmm3 # 3 = jo vld1.64 {q5}, [r9]! @ vmovdqu (%r9), %xmm5 bne .Lenc_loop @ middle of last round add r10, r11, #0x80 adr r11, .Lk_sbo @ Read to q1 instead of q4, so the vtbl.8 instruction below does not @ overlap table and destination registers. vld1.64 {q1}, [r11]! @ vmovdqa -0x60(%r10), %xmm4 # 3 : sbou vld1.64 {q0}, [r11] @ vmovdqa -0x50(%r10), %xmm0 # 0 : sbot .Lk_sbo+16 vtbl.8 d8, {q1}, d4 @ vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbou vtbl.8 d9, {q1}, d5 vld1.64 {q1}, [r10] @ vmovdqa 0x40(%r11,%r10), %xmm1 # .Lk_sr[] @ Write to q2 instead of q0 below, to avoid overlapping table and @ destination registers. vtbl.8 d4, {q0}, d6 @ vpshufb %xmm3, %xmm0, %xmm0 # 0 = sb1t vtbl.8 d5, {q0}, d7 veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k veor q2, q2, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = A @ Here we restore the original q0/q2 usage. vtbl.8 d0, {q2}, d2 @ vpshufb %xmm1, %xmm0, %xmm0 vtbl.8 d1, {q2}, d3 bx lr .size _vpaes_encrypt_core,.-_vpaes_encrypt_core .globl vpaes_encrypt .hidden vpaes_encrypt .type vpaes_encrypt,%function .align 4 vpaes_encrypt: @ _vpaes_encrypt_core uses r8-r11. Round up to r7-r11 to maintain stack @ alignment. stmdb sp!, {r7,r8,r9,r10,r11,lr} @ _vpaes_encrypt_core uses q4-q5 (d8-d11), which are callee-saved. vstmdb sp!, {d8,d9,d10,d11} vld1.64 {q0}, [r0] bl _vpaes_preheat bl _vpaes_encrypt_core vst1.64 {q0}, [r1] vldmia sp!, {d8,d9,d10,d11} ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return .size vpaes_encrypt,.-vpaes_encrypt @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @@ @@ @@ AES key schedule @@ @@ @@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @ This function diverges from both x86_64 and armv7 in which constants are @ pinned. x86_64 has a common preheat function for all operations. aarch64 @ separates them because it has enough registers to pin nearly all constants. @ armv7 does not have enough registers, but needing explicit loads and stores @ also complicates using x86_64's register allocation directly. @ @ We pin some constants for convenience and leave q14 and q15 free to load @ others on demand. @ @ Key schedule constants @ .type _vpaes_key_consts,%object .align 4 _vpaes_key_consts: .Lk_rcon:@ rcon .quad 0x1F8391B9AF9DEEB6, 0x702A98084D7C7D81 .Lk_opt:@ output transform .quad 0xFF9F4929D6B66000, 0xF7974121DEBE6808 .quad 0x01EDBD5150BCEC00, 0xE10D5DB1B05C0CE0 .Lk_deskew:@ deskew tables: inverts the sbox's "skew" .quad 0x07E4A34047A4E300, 0x1DFEB95A5DBEF91A .quad 0x5F36B5DC83EA6900, 0x2841C2ABF49D1E77 .size _vpaes_key_consts,.-_vpaes_key_consts .type _vpaes_key_preheat,%function .align 4 _vpaes_key_preheat: adr r11, .Lk_rcon vmov.i8 q12, #0x5b @ .Lk_s63 adr r10, .Lk_inv @ Must be aligned to 8 mod 16. vmov.i8 q9, #0x0f @ .Lk_s0F vld1.64 {q10,q11}, [r10] @ .Lk_inv vld1.64 {q8}, [r11] @ .Lk_rcon bx lr .size _vpaes_key_preheat,.-_vpaes_key_preheat .type _vpaes_schedule_core,%function .align 4 _vpaes_schedule_core: @ We only need to save lr, but ARM requires an 8-byte stack alignment, @ so save an extra register. stmdb sp!, {r3,lr} bl _vpaes_key_preheat @ load the tables adr r11, .Lk_ipt @ Must be aligned to 8 mod 16. vld1.64 {q0}, [r0]! @ vmovdqu (%rdi), %xmm0 # load key (unaligned) @ input transform @ Use q4 here rather than q3 so .Lschedule_am_decrypting does not @ overlap table and destination. vmov q4, q0 @ vmovdqa %xmm0, %xmm3 bl _vpaes_schedule_transform adr r10, .Lk_sr @ Must be aligned to 8 mod 16. vmov q7, q0 @ vmovdqa %xmm0, %xmm7 add r8, r8, r10 @ encrypting, output zeroth round key after transform vst1.64 {q0}, [r2] @ vmovdqu %xmm0, (%rdx) @ *ring*: Decryption removed. .Lschedule_go: cmp r1, #192 @ cmp $192, %esi bhi .Lschedule_256 @ 128: fall though @@ @@ .schedule_128 @@ @@ 128-bit specific part of key schedule. @@ @@ This schedule is really simple, because all its parts @@ are accomplished by the subroutines. @@ .Lschedule_128: mov r0, #10 @ mov $10, %esi .Loop_schedule_128: bl _vpaes_schedule_round subs r0, r0, #1 @ dec %esi beq .Lschedule_mangle_last bl _vpaes_schedule_mangle @ write output b .Loop_schedule_128 @@ @@ .aes_schedule_256 @@ @@ 256-bit specific part of key schedule. @@ @@ The structure here is very similar to the 128-bit @@ schedule, but with an additional "low side" in @@ q6. The low side's rounds are the same as the @@ high side's, except no rcon and no rotation. @@ .align 4 .Lschedule_256: vld1.64 {q0}, [r0] @ vmovdqu 16(%rdi),%xmm0 # load key part 2 (unaligned) bl _vpaes_schedule_transform @ input transform mov r0, #7 @ mov $7, %esi .Loop_schedule_256: bl _vpaes_schedule_mangle @ output low result vmov q6, q0 @ vmovdqa %xmm0, %xmm6 # save cur_lo in xmm6 @ high round bl _vpaes_schedule_round subs r0, r0, #1 @ dec %esi beq .Lschedule_mangle_last bl _vpaes_schedule_mangle @ low round. swap xmm7 and xmm6 vdup.32 q0, d1[1] @ vpshufd $0xFF, %xmm0, %xmm0 vmov.i8 q4, #0 vmov q5, q7 @ vmovdqa %xmm7, %xmm5 vmov q7, q6 @ vmovdqa %xmm6, %xmm7 bl _vpaes_schedule_low_round vmov q7, q5 @ vmovdqa %xmm5, %xmm7 b .Loop_schedule_256 @@ @@ .aes_schedule_mangle_last @@ @@ Mangler for last round of key schedule @@ Mangles q0 @@ when encrypting, outputs out(q0) ^ 63 @@ when decrypting, outputs unskew(q0) @@ @@ Always called right before return... jumps to cleanup and exits @@ .align 4 .Lschedule_mangle_last: @ schedule last round key from xmm0 adr r11, .Lk_deskew @ lea .Lk_deskew(%rip),%r11 # prepare to deskew @ encrypting vld1.64 {q1}, [r8] @ vmovdqa (%r8,%r10),%xmm1 adr r11, .Lk_opt @ lea .Lk_opt(%rip), %r11 # prepare to output transform add r2, r2, #32 @ add $32, %rdx vmov q2, q0 vtbl.8 d0, {q2}, d2 @ vpshufb %xmm1, %xmm0, %xmm0 # output permute vtbl.8 d1, {q2}, d3 .Lschedule_mangle_last_dec: sub r2, r2, #16 @ add $-16, %rdx veor q0, q0, q12 @ vpxor .Lk_s63(%rip), %xmm0, %xmm0 bl _vpaes_schedule_transform @ output transform vst1.64 {q0}, [r2] @ vmovdqu %xmm0, (%rdx) # save last key @ cleanup veor q0, q0, q0 @ vpxor %xmm0, %xmm0, %xmm0 veor q1, q1, q1 @ vpxor %xmm1, %xmm1, %xmm1 veor q2, q2, q2 @ vpxor %xmm2, %xmm2, %xmm2 veor q3, q3, q3 @ vpxor %xmm3, %xmm3, %xmm3 veor q4, q4, q4 @ vpxor %xmm4, %xmm4, %xmm4 veor q5, q5, q5 @ vpxor %xmm5, %xmm5, %xmm5 veor q6, q6, q6 @ vpxor %xmm6, %xmm6, %xmm6 veor q7, q7, q7 @ vpxor %xmm7, %xmm7, %xmm7 ldmia sp!, {r3,pc} @ return .size _vpaes_schedule_core,.-_vpaes_schedule_core @@ @@ .aes_schedule_round @@ @@ Runs one main round of the key schedule on q0, q7 @@ @@ Specifically, runs subbytes on the high dword of q0 @@ then rotates it by one byte and xors into the low dword of @@ q7. @@ @@ Adds rcon from low byte of q8, then rotates q8 for @@ next rcon. @@ @@ Smears the dwords of q7 by xoring the low into the @@ second low, result into third, result into highest. @@ @@ Returns results in q7 = q0. @@ Clobbers q1-q4, r11. @@ .type _vpaes_schedule_round,%function .align 4 _vpaes_schedule_round: @ extract rcon from xmm8 vmov.i8 q4, #0 @ vpxor %xmm4, %xmm4, %xmm4 vext.8 q1, q8, q4, #15 @ vpalignr $15, %xmm8, %xmm4, %xmm1 vext.8 q8, q8, q8, #15 @ vpalignr $15, %xmm8, %xmm8, %xmm8 veor q7, q7, q1 @ vpxor %xmm1, %xmm7, %xmm7 @ rotate vdup.32 q0, d1[1] @ vpshufd $0xFF, %xmm0, %xmm0 vext.8 q0, q0, q0, #1 @ vpalignr $1, %xmm0, %xmm0, %xmm0 @ fall through... @ low round: same as high round, but no rotation and no rcon. _vpaes_schedule_low_round: @ The x86_64 version pins .Lk_sb1 in %xmm13 and .Lk_sb1+16 in %xmm12. @ We pin other values in _vpaes_key_preheat, so load them now. adr r11, .Lk_sb1 vld1.64 {q14,q15}, [r11] @ smear xmm7 vext.8 q1, q4, q7, #12 @ vpslldq $4, %xmm7, %xmm1 veor q7, q7, q1 @ vpxor %xmm1, %xmm7, %xmm7 vext.8 q4, q4, q7, #8 @ vpslldq $8, %xmm7, %xmm4 @ subbytes vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 # 0 = k vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 # 1 = i veor q7, q7, q4 @ vpxor %xmm4, %xmm7, %xmm7 vtbl.8 d4, {q11}, d2 @ vpshufb %xmm1, %xmm11, %xmm2 # 2 = a/k vtbl.8 d5, {q11}, d3 veor q1, q1, q0 @ vpxor %xmm0, %xmm1, %xmm1 # 0 = j vtbl.8 d6, {q10}, d0 @ vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i vtbl.8 d7, {q10}, d1 veor q3, q3, q2 @ vpxor %xmm2, %xmm3, %xmm3 # 3 = iak = 1/i + a/k vtbl.8 d8, {q10}, d2 @ vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j vtbl.8 d9, {q10}, d3 veor q7, q7, q12 @ vpxor .Lk_s63(%rip), %xmm7, %xmm7 vtbl.8 d6, {q10}, d6 @ vpshufb %xmm3, %xmm10, %xmm3 # 2 = 1/iak vtbl.8 d7, {q10}, d7 veor q4, q4, q2 @ vpxor %xmm2, %xmm4, %xmm4 # 4 = jak = 1/j + a/k vtbl.8 d4, {q10}, d8 @ vpshufb %xmm4, %xmm10, %xmm2 # 3 = 1/jak vtbl.8 d5, {q10}, d9 veor q3, q3, q1 @ vpxor %xmm1, %xmm3, %xmm3 # 2 = io veor q2, q2, q0 @ vpxor %xmm0, %xmm2, %xmm2 # 3 = jo vtbl.8 d8, {q15}, d6 @ vpshufb %xmm3, %xmm13, %xmm4 # 4 = sbou vtbl.8 d9, {q15}, d7 vtbl.8 d2, {q14}, d4 @ vpshufb %xmm2, %xmm12, %xmm1 # 0 = sb1t vtbl.8 d3, {q14}, d5 veor q1, q1, q4 @ vpxor %xmm4, %xmm1, %xmm1 # 0 = sbox output @ add in smeared stuff veor q0, q1, q7 @ vpxor %xmm7, %xmm1, %xmm0 veor q7, q1, q7 @ vmovdqa %xmm0, %xmm7 bx lr .size _vpaes_schedule_round,.-_vpaes_schedule_round @@ @@ .aes_schedule_transform @@ @@ Linear-transform q0 according to tables at [r11] @@ @@ Requires that q9 = 0x0F0F... as in preheat @@ Output in q0 @@ Clobbers q1, q2, q14, q15 @@ .type _vpaes_schedule_transform,%function .align 4 _vpaes_schedule_transform: vld1.64 {q14,q15}, [r11] @ vmovdqa (%r11), %xmm2 # lo @ vmovdqa 16(%r11), %xmm1 # hi vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 vtbl.8 d4, {q14}, d2 @ vpshufb %xmm1, %xmm2, %xmm2 vtbl.8 d5, {q14}, d3 vtbl.8 d0, {q15}, d0 @ vpshufb %xmm0, %xmm1, %xmm0 vtbl.8 d1, {q15}, d1 veor q0, q0, q2 @ vpxor %xmm2, %xmm0, %xmm0 bx lr .size _vpaes_schedule_transform,.-_vpaes_schedule_transform @@ @@ .aes_schedule_mangle @@ @@ Mangles q0 from (basis-transformed) standard version @@ to our version. @@ @@ On encrypt, @@ xor with 0x63 @@ multiply by circulant 0,1,1,1 @@ apply shiftrows transform @@ @@ On decrypt, @@ xor with 0x63 @@ multiply by "inverse mixcolumns" circulant E,B,D,9 @@ deskew @@ apply shiftrows transform @@ @@ @@ Writes out to [r2], and increments or decrements it @@ Keeps track of round number mod 4 in r8 @@ Preserves q0 @@ Clobbers q1-q5 @@ .type _vpaes_schedule_mangle,%function .align 4 _vpaes_schedule_mangle: tst r3, r3 vmov q4, q0 @ vmovdqa %xmm0, %xmm4 # save xmm0 for later adr r11, .Lk_mc_forward @ Must be aligned to 8 mod 16. vld1.64 {q5}, [r11] @ vmovdqa .Lk_mc_forward(%rip),%xmm5 @ encrypting @ Write to q2 so we do not overlap table and destination below. veor q2, q0, q12 @ vpxor .Lk_s63(%rip), %xmm0, %xmm4 add r2, r2, #16 @ add $16, %rdx vtbl.8 d8, {q2}, d10 @ vpshufb %xmm5, %xmm4, %xmm4 vtbl.8 d9, {q2}, d11 vtbl.8 d2, {q4}, d10 @ vpshufb %xmm5, %xmm4, %xmm1 vtbl.8 d3, {q4}, d11 vtbl.8 d6, {q1}, d10 @ vpshufb %xmm5, %xmm1, %xmm3 vtbl.8 d7, {q1}, d11 veor q4, q4, q1 @ vpxor %xmm1, %xmm4, %xmm4 vld1.64 {q1}, [r8] @ vmovdqa (%r8,%r10), %xmm1 veor q3, q3, q4 @ vpxor %xmm4, %xmm3, %xmm3 .Lschedule_mangle_both: @ Write to q2 so table and destination do not overlap. vtbl.8 d4, {q3}, d2 @ vpshufb %xmm1, %xmm3, %xmm3 vtbl.8 d5, {q3}, d3 add r8, r8, #64-16 @ add $-16, %r8 and r8, r8, #~(1<<6) @ and $0x30, %r8 vst1.64 {q2}, [r2] @ vmovdqu %xmm3, (%rdx) bx lr .size _vpaes_schedule_mangle,.-_vpaes_schedule_mangle .globl vpaes_set_encrypt_key .hidden vpaes_set_encrypt_key .type vpaes_set_encrypt_key,%function .align 4 vpaes_set_encrypt_key: stmdb sp!, {r7,r8,r9,r10,r11, lr} vstmdb sp!, {d8,d9,d10,d11,d12,d13,d14,d15} lsr r9, r1, #5 @ shr $5,%eax add r9, r9, #5 @ $5,%eax str r9, [r2,#240] @ mov %eax,240(%rdx) # AES_KEY->rounds = nbits/32+5; mov r3, #0 @ mov $0,%ecx mov r8, #0x30 @ mov $0x30,%r8d bl _vpaes_schedule_core eor r0, r0, r0 vldmia sp!, {d8,d9,d10,d11,d12,d13,d14,d15} ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return .size vpaes_set_encrypt_key,.-vpaes_set_encrypt_key @ Additional constants for converting to bsaes. .type _vpaes_convert_consts,%object .align 4 _vpaes_convert_consts: @ .Lk_opt_then_skew applies skew(opt(x)) XOR 0x63, where skew is the linear @ transform in the AES S-box. 0x63 is incorporated into the low half of the @ table. This was computed with the following script: @ @ def u64s_to_u128(x, y): @ return x | (y << 64) @ def u128_to_u64s(w): @ return w & ((1<<64)-1), w >> 64 @ def get_byte(w, i): @ return (w >> (i*8)) & 0xff @ def apply_table(table, b): @ lo = b & 0xf @ hi = b >> 4 @ return get_byte(table[0], lo) ^ get_byte(table[1], hi) @ def opt(b): @ table = [ @ u64s_to_u128(0xFF9F4929D6B66000, 0xF7974121DEBE6808), @ u64s_to_u128(0x01EDBD5150BCEC00, 0xE10D5DB1B05C0CE0), @ ] @ return apply_table(table, b) @ def rot_byte(b, n): @ return 0xff & ((b << n) | (b >> (8-n))) @ def skew(x): @ return (x ^ rot_byte(x, 1) ^ rot_byte(x, 2) ^ rot_byte(x, 3) ^ @ rot_byte(x, 4)) @ table = [0, 0] @ for i in range(16): @ table[0] |= (skew(opt(i)) ^ 0x63) << (i*8) @ table[1] |= skew(opt(i<<4)) << (i*8) @ print(" .quad 0x%016x, 0x%016x" % u128_to_u64s(table[0])) @ print(" .quad 0x%016x, 0x%016x" % u128_to_u64s(table[1])) .Lk_opt_then_skew: .quad 0x9cb8436798bc4763, 0x6440bb9f6044bf9b .quad 0x1f30062936192f00, 0xb49bad829db284ab @ void vpaes_encrypt_key_to_bsaes(AES_KEY *bsaes, const AES_KEY *vpaes); .globl vpaes_encrypt_key_to_bsaes .hidden vpaes_encrypt_key_to_bsaes .type vpaes_encrypt_key_to_bsaes,%function .align 4 vpaes_encrypt_key_to_bsaes: stmdb sp!, {r11, lr} @ See _vpaes_schedule_core for the key schedule logic. In particular, @ _vpaes_schedule_transform(.Lk_ipt) (section 2.2 of the paper), @ _vpaes_schedule_mangle (section 4.3), and .Lschedule_mangle_last @ contain the transformations not in the bsaes representation. This @ function inverts those transforms. @ @ Note also that bsaes-armv7.pl expects aes-armv4.pl's key @ representation, which does not match the other aes_nohw_* @ implementations. The ARM aes_nohw_* stores each 32-bit word @ byteswapped, as a convenience for (unsupported) big-endian ARM, at the @ cost of extra REV and VREV32 operations in little-endian ARM. vmov.i8 q9, #0x0f @ Required by _vpaes_schedule_transform adr r2, .Lk_mc_forward @ Must be aligned to 8 mod 16. add r3, r2, 0x90 @ .Lk_sr+0x10-.Lk_mc_forward = 0x90 (Apple's toolchain doesn't support the expression) vld1.64 {q12}, [r2] vmov.i8 q10, #0x5b @ .Lk_s63 from vpaes-x86_64 adr r11, .Lk_opt @ Must be aligned to 8 mod 16. vmov.i8 q11, #0x63 @ .LK_s63 without .Lk_ipt applied @ vpaes stores one fewer round count than bsaes, but the number of keys @ is the same. ldr r2, [r1,#240] add r2, r2, #1 str r2, [r0,#240] @ The first key is transformed with _vpaes_schedule_transform(.Lk_ipt). @ Invert this with .Lk_opt. vld1.64 {q0}, [r1]! bl _vpaes_schedule_transform vrev32.8 q0, q0 vst1.64 {q0}, [r0]! @ The middle keys have _vpaes_schedule_transform(.Lk_ipt) applied, @ followed by _vpaes_schedule_mangle. _vpaes_schedule_mangle XORs 0x63, @ multiplies by the circulant 0,1,1,1, then applies ShiftRows. .Loop_enc_key_to_bsaes: vld1.64 {q0}, [r1]! @ Invert the ShiftRows step (see .Lschedule_mangle_both). Note we cycle @ r3 in the opposite direction and start at .Lk_sr+0x10 instead of 0x30. @ We use r3 rather than r8 to avoid a callee-saved register. vld1.64 {q1}, [r3] vtbl.8 d4, {q0}, d2 vtbl.8 d5, {q0}, d3 add r3, r3, #16 and r3, r3, #~(1<<6) vmov q0, q2 @ Handle the last key differently. subs r2, r2, #1 beq .Loop_enc_key_to_bsaes_last @ Multiply by the circulant. This is its own inverse. vtbl.8 d2, {q0}, d24 vtbl.8 d3, {q0}, d25 vmov q0, q1 vtbl.8 d4, {q1}, d24 vtbl.8 d5, {q1}, d25 veor q0, q0, q2 vtbl.8 d2, {q2}, d24 vtbl.8 d3, {q2}, d25 veor q0, q0, q1 @ XOR and finish. veor q0, q0, q10 bl _vpaes_schedule_transform vrev32.8 q0, q0 vst1.64 {q0}, [r0]! b .Loop_enc_key_to_bsaes .Loop_enc_key_to_bsaes_last: @ The final key does not have a basis transform (note @ .Lschedule_mangle_last inverts the original transform). It only XORs @ 0x63 and applies ShiftRows. The latter was already inverted in the @ loop. Note that, because we act on the original representation, we use @ q11, not q10. veor q0, q0, q11 vrev32.8 q0, q0 vst1.64 {q0}, [r0] @ Wipe registers which contained key material. veor q0, q0, q0 veor q1, q1, q1 veor q2, q2, q2 ldmia sp!, {r11, pc} @ return .size vpaes_encrypt_key_to_bsaes,.-vpaes_encrypt_key_to_bsaes .globl vpaes_ctr32_encrypt_blocks .hidden vpaes_ctr32_encrypt_blocks .type vpaes_ctr32_encrypt_blocks,%function .align 4 vpaes_ctr32_encrypt_blocks: mov ip, sp stmdb sp!, {r7,r8,r9,r10,r11, lr} @ This function uses q4-q7 (d8-d15), which are callee-saved. vstmdb sp!, {d8,d9,d10,d11,d12,d13,d14,d15} cmp r2, #0 @ r8 is passed on the stack. ldr r8, [ip] beq .Lctr32_done @ _vpaes_encrypt_core expects the key in r2, so swap r2 and r3. mov r9, r3 mov r3, r2 mov r2, r9 @ Load the IV and counter portion. ldr r7, [r8, #12] vld1.8 {q7}, [r8] bl _vpaes_preheat rev r7, r7 @ The counter is big-endian. .Lctr32_loop: vmov q0, q7 vld1.8 {q6}, [r0]! @ .Load input ahead of time bl _vpaes_encrypt_core veor q0, q0, q6 @ XOR input and result vst1.8 {q0}, [r1]! subs r3, r3, #1 @ Update the counter. add r7, r7, #1 rev r9, r7 vmov.32 d15[1], r9 bne .Lctr32_loop .Lctr32_done: vldmia sp!, {d8,d9,d10,d11,d12,d13,d14,d15} ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return .size vpaes_ctr32_encrypt_blocks,.-vpaes_ctr32_encrypt_blocks #endif // !OPENSSL_NO_ASM && defined(OPENSSL_ARM) && defined(__ELF__)

j4yc3-mw/Viren

58,542

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/pregenerated/x86_64-mont5-elf.S

// This file is generated from a similarly-named Perl script in the BoringSSL // source tree. Do not edit by hand. #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__ELF__) .text .extern OPENSSL_ia32cap_P .hidden OPENSSL_ia32cap_P .globl bn_mul_mont_gather5 .hidden bn_mul_mont_gather5 .type bn_mul_mont_gather5,@function .align 64 bn_mul_mont_gather5: .cfi_startproc _CET_ENDBR movl %r9d,%r9d movq %rsp,%rax .cfi_def_cfa_register %rax testl $7,%r9d jnz .Lmul_enter leaq OPENSSL_ia32cap_P(%rip),%r11 movl 8(%r11),%r11d jmp .Lmul4x_enter .align 16 .Lmul_enter: movd 8(%rsp),%xmm5 pushq %rbx .cfi_offset %rbx,-16 pushq %rbp .cfi_offset %rbp,-24 pushq %r12 .cfi_offset %r12,-32 pushq %r13 .cfi_offset %r13,-40 pushq %r14 .cfi_offset %r14,-48 pushq %r15 .cfi_offset %r15,-56 negq %r9 movq %rsp,%r11 leaq -280(%rsp,%r9,8),%r10 negq %r9 andq $-1024,%r10 subq %r10,%r11 andq $-4096,%r11 leaq (%r10,%r11,1),%rsp movq (%rsp),%r11 cmpq %r10,%rsp ja .Lmul_page_walk jmp .Lmul_page_walk_done .Lmul_page_walk: leaq -4096(%rsp),%rsp movq (%rsp),%r11 cmpq %r10,%rsp ja .Lmul_page_walk .Lmul_page_walk_done: leaq .Linc(%rip),%r10 movq %rax,8(%rsp,%r9,8) .cfi_escape 0x0f,0x0a,0x77,0x08,0x79,0x00,0x38,0x1e,0x22,0x06,0x23,0x08 .Lmul_body: leaq 128(%rdx),%r12 movdqa 0(%r10),%xmm0 movdqa 16(%r10),%xmm1 leaq 24-112(%rsp,%r9,8),%r10 andq $-16,%r10 pshufd $0,%xmm5,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm1,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 .byte 0x67 movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,112(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,128(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,144(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,160(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,176(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,192(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,208(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,224(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,240(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,256(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,272(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,288(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,304(%r10) paddd %xmm2,%xmm3 .byte 0x67 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,320(%r10) pcmpeqd %xmm5,%xmm3 movdqa %xmm2,336(%r10) pand 64(%r12),%xmm0 pand 80(%r12),%xmm1 pand 96(%r12),%xmm2 movdqa %xmm3,352(%r10) pand 112(%r12),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -128(%r12),%xmm4 movdqa -112(%r12),%xmm5 movdqa -96(%r12),%xmm2 pand 112(%r10),%xmm4 movdqa -80(%r12),%xmm3 pand 128(%r10),%xmm5 por %xmm4,%xmm0 pand 144(%r10),%xmm2 por %xmm5,%xmm1 pand 160(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -64(%r12),%xmm4 movdqa -48(%r12),%xmm5 movdqa -32(%r12),%xmm2 pand 176(%r10),%xmm4 movdqa -16(%r12),%xmm3 pand 192(%r10),%xmm5 por %xmm4,%xmm0 pand 208(%r10),%xmm2 por %xmm5,%xmm1 pand 224(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa 0(%r12),%xmm4 movdqa 16(%r12),%xmm5 movdqa 32(%r12),%xmm2 pand 240(%r10),%xmm4 movdqa 48(%r12),%xmm3 pand 256(%r10),%xmm5 por %xmm4,%xmm0 pand 272(%r10),%xmm2 por %xmm5,%xmm1 pand 288(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 por %xmm1,%xmm0 pshufd $0x4e,%xmm0,%xmm1 por %xmm1,%xmm0 leaq 256(%r12),%r12 .byte 102,72,15,126,195 movq (%r8),%r8 movq (%rsi),%rax xorq %r14,%r14 xorq %r15,%r15 movq %r8,%rbp mulq %rbx movq %rax,%r10 movq (%rcx),%rax imulq %r10,%rbp movq %rdx,%r11 mulq %rbp addq %rax,%r10 movq 8(%rsi),%rax adcq $0,%rdx movq %rdx,%r13 leaq 1(%r15),%r15 jmp .L1st_enter .align 16 .L1st: addq %rax,%r13 movq (%rsi,%r15,8),%rax adcq $0,%rdx addq %r11,%r13 movq %r10,%r11 adcq $0,%rdx movq %r13,-16(%rsp,%r15,8) movq %rdx,%r13 .L1st_enter: mulq %rbx addq %rax,%r11 movq (%rcx,%r15,8),%rax adcq $0,%rdx leaq 1(%r15),%r15 movq %rdx,%r10 mulq %rbp cmpq %r9,%r15 jne .L1st addq %rax,%r13 adcq $0,%rdx addq %r11,%r13 adcq $0,%rdx movq %r13,-16(%rsp,%r9,8) movq %rdx,%r13 movq %r10,%r11 xorq %rdx,%rdx addq %r11,%r13 adcq $0,%rdx movq %r13,-8(%rsp,%r9,8) movq %rdx,(%rsp,%r9,8) leaq 1(%r14),%r14 jmp .Louter .align 16 .Louter: leaq 24+128(%rsp,%r9,8),%rdx andq $-16,%rdx pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 movdqa -128(%r12),%xmm0 movdqa -112(%r12),%xmm1 movdqa -96(%r12),%xmm2 movdqa -80(%r12),%xmm3 pand -128(%rdx),%xmm0 pand -112(%rdx),%xmm1 por %xmm0,%xmm4 pand -96(%rdx),%xmm2 por %xmm1,%xmm5 pand -80(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa -64(%r12),%xmm0 movdqa -48(%r12),%xmm1 movdqa -32(%r12),%xmm2 movdqa -16(%r12),%xmm3 pand -64(%rdx),%xmm0 pand -48(%rdx),%xmm1 por %xmm0,%xmm4 pand -32(%rdx),%xmm2 por %xmm1,%xmm5 pand -16(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 0(%r12),%xmm0 movdqa 16(%r12),%xmm1 movdqa 32(%r12),%xmm2 movdqa 48(%r12),%xmm3 pand 0(%rdx),%xmm0 pand 16(%rdx),%xmm1 por %xmm0,%xmm4 pand 32(%rdx),%xmm2 por %xmm1,%xmm5 pand 48(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 64(%r12),%xmm0 movdqa 80(%r12),%xmm1 movdqa 96(%r12),%xmm2 movdqa 112(%r12),%xmm3 pand 64(%rdx),%xmm0 pand 80(%rdx),%xmm1 por %xmm0,%xmm4 pand 96(%rdx),%xmm2 por %xmm1,%xmm5 pand 112(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 por %xmm5,%xmm4 pshufd $0x4e,%xmm4,%xmm0 por %xmm4,%xmm0 leaq 256(%r12),%r12 movq (%rsi),%rax .byte 102,72,15,126,195 xorq %r15,%r15 movq %r8,%rbp movq (%rsp),%r10 mulq %rbx addq %rax,%r10 movq (%rcx),%rax adcq $0,%rdx imulq %r10,%rbp movq %rdx,%r11 mulq %rbp addq %rax,%r10 movq 8(%rsi),%rax adcq $0,%rdx movq 8(%rsp),%r10 movq %rdx,%r13 leaq 1(%r15),%r15 jmp .Linner_enter .align 16 .Linner: addq %rax,%r13 movq (%rsi,%r15,8),%rax adcq $0,%rdx addq %r10,%r13 movq (%rsp,%r15,8),%r10 adcq $0,%rdx movq %r13,-16(%rsp,%r15,8) movq %rdx,%r13 .Linner_enter: mulq %rbx addq %rax,%r11 movq (%rcx,%r15,8),%rax adcq $0,%rdx addq %r11,%r10 movq %rdx,%r11 adcq $0,%r11 leaq 1(%r15),%r15 mulq %rbp cmpq %r9,%r15 jne .Linner addq %rax,%r13 adcq $0,%rdx addq %r10,%r13 movq (%rsp,%r9,8),%r10 adcq $0,%rdx movq %r13,-16(%rsp,%r9,8) movq %rdx,%r13 xorq %rdx,%rdx addq %r11,%r13 adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %r13,-8(%rsp,%r9,8) movq %rdx,(%rsp,%r9,8) leaq 1(%r14),%r14 cmpq %r9,%r14 jb .Louter xorq %r14,%r14 movq (%rsp),%rax leaq (%rsp),%rsi movq %r9,%r15 jmp .Lsub .align 16 .Lsub: sbbq (%rcx,%r14,8),%rax movq %rax,(%rdi,%r14,8) movq 8(%rsi,%r14,8),%rax leaq 1(%r14),%r14 decq %r15 jnz .Lsub sbbq $0,%rax movq $-1,%rbx xorq %rax,%rbx xorq %r14,%r14 movq %r9,%r15 .Lcopy: movq (%rdi,%r14,8),%rcx movq (%rsp,%r14,8),%rdx andq %rbx,%rcx andq %rax,%rdx movq %r14,(%rsp,%r14,8) orq %rcx,%rdx movq %rdx,(%rdi,%r14,8) leaq 1(%r14),%r14 subq $1,%r15 jnz .Lcopy movq 8(%rsp,%r9,8),%rsi .cfi_def_cfa %rsi,8 movq $1,%rax movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbp .cfi_restore %rbp movq -8(%rsi),%rbx .cfi_restore %rbx leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lmul_epilogue: ret .cfi_endproc .size bn_mul_mont_gather5,.-bn_mul_mont_gather5 .type bn_mul4x_mont_gather5,@function .align 32 bn_mul4x_mont_gather5: .cfi_startproc .byte 0x67 movq %rsp,%rax .cfi_def_cfa_register %rax .Lmul4x_enter: andl $0x80108,%r11d cmpl $0x80108,%r11d je .Lmulx4x_enter pushq %rbx .cfi_offset %rbx,-16 pushq %rbp .cfi_offset %rbp,-24 pushq %r12 .cfi_offset %r12,-32 pushq %r13 .cfi_offset %r13,-40 pushq %r14 .cfi_offset %r14,-48 pushq %r15 .cfi_offset %r15,-56 .Lmul4x_prologue: .byte 0x67 shll $3,%r9d leaq (%r9,%r9,2),%r10 negq %r9 leaq -320(%rsp,%r9,2),%r11 movq %rsp,%rbp subq %rdi,%r11 andq $4095,%r11 cmpq %r11,%r10 jb .Lmul4xsp_alt subq %r11,%rbp leaq -320(%rbp,%r9,2),%rbp jmp .Lmul4xsp_done .align 32 .Lmul4xsp_alt: leaq 4096-320(,%r9,2),%r10 leaq -320(%rbp,%r9,2),%rbp subq %r10,%r11 movq $0,%r10 cmovcq %r10,%r11 subq %r11,%rbp .Lmul4xsp_done: andq $-64,%rbp movq %rsp,%r11 subq %rbp,%r11 andq $-4096,%r11 leaq (%r11,%rbp,1),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lmul4x_page_walk jmp .Lmul4x_page_walk_done .Lmul4x_page_walk: leaq -4096(%rsp),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lmul4x_page_walk .Lmul4x_page_walk_done: negq %r9 movq %rax,40(%rsp) .cfi_escape 0x0f,0x05,0x77,0x28,0x06,0x23,0x08 .Lmul4x_body: call mul4x_internal movq 40(%rsp),%rsi .cfi_def_cfa %rsi,8 movq $1,%rax movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbp .cfi_restore %rbp movq -8(%rsi),%rbx .cfi_restore %rbx leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lmul4x_epilogue: ret .cfi_endproc .size bn_mul4x_mont_gather5,.-bn_mul4x_mont_gather5 .type mul4x_internal,@function .align 32 mul4x_internal: .cfi_startproc shlq $5,%r9 movd 8(%rax),%xmm5 leaq .Linc(%rip),%rax leaq 128(%rdx,%r9,1),%r13 shrq $5,%r9 movdqa 0(%rax),%xmm0 movdqa 16(%rax),%xmm1 leaq 88-112(%rsp,%r9,1),%r10 leaq 128(%rdx),%r12 pshufd $0,%xmm5,%xmm5 movdqa %xmm1,%xmm4 .byte 0x67,0x67 movdqa %xmm1,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 .byte 0x67 movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,112(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,128(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,144(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,160(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,176(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,192(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,208(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,224(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,240(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,256(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,272(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,288(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,304(%r10) paddd %xmm2,%xmm3 .byte 0x67 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,320(%r10) pcmpeqd %xmm5,%xmm3 movdqa %xmm2,336(%r10) pand 64(%r12),%xmm0 pand 80(%r12),%xmm1 pand 96(%r12),%xmm2 movdqa %xmm3,352(%r10) pand 112(%r12),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -128(%r12),%xmm4 movdqa -112(%r12),%xmm5 movdqa -96(%r12),%xmm2 pand 112(%r10),%xmm4 movdqa -80(%r12),%xmm3 pand 128(%r10),%xmm5 por %xmm4,%xmm0 pand 144(%r10),%xmm2 por %xmm5,%xmm1 pand 160(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -64(%r12),%xmm4 movdqa -48(%r12),%xmm5 movdqa -32(%r12),%xmm2 pand 176(%r10),%xmm4 movdqa -16(%r12),%xmm3 pand 192(%r10),%xmm5 por %xmm4,%xmm0 pand 208(%r10),%xmm2 por %xmm5,%xmm1 pand 224(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa 0(%r12),%xmm4 movdqa 16(%r12),%xmm5 movdqa 32(%r12),%xmm2 pand 240(%r10),%xmm4 movdqa 48(%r12),%xmm3 pand 256(%r10),%xmm5 por %xmm4,%xmm0 pand 272(%r10),%xmm2 por %xmm5,%xmm1 pand 288(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 por %xmm1,%xmm0 pshufd $0x4e,%xmm0,%xmm1 por %xmm1,%xmm0 leaq 256(%r12),%r12 .byte 102,72,15,126,195 movq %r13,16+8(%rsp) movq %rdi,56+8(%rsp) movq (%r8),%r8 movq (%rsi),%rax leaq (%rsi,%r9,1),%rsi negq %r9 movq %r8,%rbp mulq %rbx movq %rax,%r10 movq (%rcx),%rax imulq %r10,%rbp leaq 64+8(%rsp),%r14 movq %rdx,%r11 mulq %rbp addq %rax,%r10 movq 8(%rsi,%r9,1),%rax adcq $0,%rdx movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq 8(%rcx),%rax adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq 16(%rsi,%r9,1),%rax adcq $0,%rdx addq %r11,%rdi leaq 32(%r9),%r15 leaq 32(%rcx),%rcx adcq $0,%rdx movq %rdi,(%r14) movq %rdx,%r13 jmp .L1st4x .align 32 .L1st4x: mulq %rbx addq %rax,%r10 movq -16(%rcx),%rax leaq 32(%r14),%r14 adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq -8(%rsi,%r15,1),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %r13,-24(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq -8(%rcx),%rax adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq (%rsi,%r15,1),%rax adcq $0,%rdx addq %r11,%rdi adcq $0,%rdx movq %rdi,-16(%r14) movq %rdx,%r13 mulq %rbx addq %rax,%r10 movq 0(%rcx),%rax adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq 8(%rsi,%r15,1),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %r13,-8(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq 8(%rcx),%rax adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq 16(%rsi,%r15,1),%rax adcq $0,%rdx addq %r11,%rdi leaq 32(%rcx),%rcx adcq $0,%rdx movq %rdi,(%r14) movq %rdx,%r13 addq $32,%r15 jnz .L1st4x mulq %rbx addq %rax,%r10 movq -16(%rcx),%rax leaq 32(%r14),%r14 adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq -8(%rsi),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %r13,-24(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq -8(%rcx),%rax adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq (%rsi,%r9,1),%rax adcq $0,%rdx addq %r11,%rdi adcq $0,%rdx movq %rdi,-16(%r14) movq %rdx,%r13 leaq (%rcx,%r9,1),%rcx xorq %rdi,%rdi addq %r10,%r13 adcq $0,%rdi movq %r13,-8(%r14) jmp .Louter4x .align 32 .Louter4x: leaq 16+128(%r14),%rdx pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 movdqa -128(%r12),%xmm0 movdqa -112(%r12),%xmm1 movdqa -96(%r12),%xmm2 movdqa -80(%r12),%xmm3 pand -128(%rdx),%xmm0 pand -112(%rdx),%xmm1 por %xmm0,%xmm4 pand -96(%rdx),%xmm2 por %xmm1,%xmm5 pand -80(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa -64(%r12),%xmm0 movdqa -48(%r12),%xmm1 movdqa -32(%r12),%xmm2 movdqa -16(%r12),%xmm3 pand -64(%rdx),%xmm0 pand -48(%rdx),%xmm1 por %xmm0,%xmm4 pand -32(%rdx),%xmm2 por %xmm1,%xmm5 pand -16(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 0(%r12),%xmm0 movdqa 16(%r12),%xmm1 movdqa 32(%r12),%xmm2 movdqa 48(%r12),%xmm3 pand 0(%rdx),%xmm0 pand 16(%rdx),%xmm1 por %xmm0,%xmm4 pand 32(%rdx),%xmm2 por %xmm1,%xmm5 pand 48(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 64(%r12),%xmm0 movdqa 80(%r12),%xmm1 movdqa 96(%r12),%xmm2 movdqa 112(%r12),%xmm3 pand 64(%rdx),%xmm0 pand 80(%rdx),%xmm1 por %xmm0,%xmm4 pand 96(%rdx),%xmm2 por %xmm1,%xmm5 pand 112(%rdx),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 por %xmm5,%xmm4 pshufd $0x4e,%xmm4,%xmm0 por %xmm4,%xmm0 leaq 256(%r12),%r12 .byte 102,72,15,126,195 movq (%r14,%r9,1),%r10 movq %r8,%rbp mulq %rbx addq %rax,%r10 movq (%rcx),%rax adcq $0,%rdx imulq %r10,%rbp movq %rdx,%r11 movq %rdi,(%r14) leaq (%r14,%r9,1),%r14 mulq %rbp addq %rax,%r10 movq 8(%rsi,%r9,1),%rax adcq $0,%rdx movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq 8(%rcx),%rax adcq $0,%rdx addq 8(%r14),%r11 adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq 16(%rsi,%r9,1),%rax adcq $0,%rdx addq %r11,%rdi leaq 32(%r9),%r15 leaq 32(%rcx),%rcx adcq $0,%rdx movq %rdx,%r13 jmp .Linner4x .align 32 .Linner4x: mulq %rbx addq %rax,%r10 movq -16(%rcx),%rax adcq $0,%rdx addq 16(%r14),%r10 leaq 32(%r14),%r14 adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq -8(%rsi,%r15,1),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %rdi,-32(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq -8(%rcx),%rax adcq $0,%rdx addq -8(%r14),%r11 adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq (%rsi,%r15,1),%rax adcq $0,%rdx addq %r11,%rdi adcq $0,%rdx movq %r13,-24(%r14) movq %rdx,%r13 mulq %rbx addq %rax,%r10 movq 0(%rcx),%rax adcq $0,%rdx addq (%r14),%r10 adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq 8(%rsi,%r15,1),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %rdi,-16(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq 8(%rcx),%rax adcq $0,%rdx addq 8(%r14),%r11 adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq 16(%rsi,%r15,1),%rax adcq $0,%rdx addq %r11,%rdi leaq 32(%rcx),%rcx adcq $0,%rdx movq %r13,-8(%r14) movq %rdx,%r13 addq $32,%r15 jnz .Linner4x mulq %rbx addq %rax,%r10 movq -16(%rcx),%rax adcq $0,%rdx addq 16(%r14),%r10 leaq 32(%r14),%r14 adcq $0,%rdx movq %rdx,%r11 mulq %rbp addq %rax,%r13 movq -8(%rsi),%rax adcq $0,%rdx addq %r10,%r13 adcq $0,%rdx movq %rdi,-32(%r14) movq %rdx,%rdi mulq %rbx addq %rax,%r11 movq %rbp,%rax movq -8(%rcx),%rbp adcq $0,%rdx addq -8(%r14),%r11 adcq $0,%rdx movq %rdx,%r10 mulq %rbp addq %rax,%rdi movq (%rsi,%r9,1),%rax adcq $0,%rdx addq %r11,%rdi adcq $0,%rdx movq %r13,-24(%r14) movq %rdx,%r13 movq %rdi,-16(%r14) leaq (%rcx,%r9,1),%rcx xorq %rdi,%rdi addq %r10,%r13 adcq $0,%rdi addq (%r14),%r13 adcq $0,%rdi movq %r13,-8(%r14) cmpq 16+8(%rsp),%r12 jb .Louter4x xorq %rax,%rax subq %r13,%rbp adcq %r15,%r15 orq %r15,%rdi subq %rdi,%rax leaq (%r14,%r9,1),%rbx movq (%rcx),%r12 leaq (%rcx),%rbp movq %r9,%rcx sarq $3+2,%rcx movq 56+8(%rsp),%rdi decq %r12 xorq %r10,%r10 movq 8(%rbp),%r13 movq 16(%rbp),%r14 movq 24(%rbp),%r15 jmp .Lsqr4x_sub_entry .cfi_endproc .size mul4x_internal,.-mul4x_internal .globl bn_power5 .hidden bn_power5 .type bn_power5,@function .align 32 bn_power5: .cfi_startproc _CET_ENDBR movq %rsp,%rax .cfi_def_cfa_register %rax leaq OPENSSL_ia32cap_P(%rip),%r11 movl 8(%r11),%r11d andl $0x80108,%r11d cmpl $0x80108,%r11d je .Lpowerx5_enter pushq %rbx .cfi_offset %rbx,-16 pushq %rbp .cfi_offset %rbp,-24 pushq %r12 .cfi_offset %r12,-32 pushq %r13 .cfi_offset %r13,-40 pushq %r14 .cfi_offset %r14,-48 pushq %r15 .cfi_offset %r15,-56 .Lpower5_prologue: shll $3,%r9d leal (%r9,%r9,2),%r10d negq %r9 movq (%r8),%r8 leaq -320(%rsp,%r9,2),%r11 movq %rsp,%rbp subq %rdi,%r11 andq $4095,%r11 cmpq %r11,%r10 jb .Lpwr_sp_alt subq %r11,%rbp leaq -320(%rbp,%r9,2),%rbp jmp .Lpwr_sp_done .align 32 .Lpwr_sp_alt: leaq 4096-320(,%r9,2),%r10 leaq -320(%rbp,%r9,2),%rbp subq %r10,%r11 movq $0,%r10 cmovcq %r10,%r11 subq %r11,%rbp .Lpwr_sp_done: andq $-64,%rbp movq %rsp,%r11 subq %rbp,%r11 andq $-4096,%r11 leaq (%r11,%rbp,1),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lpwr_page_walk jmp .Lpwr_page_walk_done .Lpwr_page_walk: leaq -4096(%rsp),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lpwr_page_walk .Lpwr_page_walk_done: movq %r9,%r10 negq %r9 movq %r8,32(%rsp) movq %rax,40(%rsp) .cfi_escape 0x0f,0x05,0x77,0x28,0x06,0x23,0x08 .Lpower5_body: .byte 102,72,15,110,207 .byte 102,72,15,110,209 .byte 102,73,15,110,218 .byte 102,72,15,110,226 call __bn_sqr8x_internal call __bn_post4x_internal call __bn_sqr8x_internal call __bn_post4x_internal call __bn_sqr8x_internal call __bn_post4x_internal call __bn_sqr8x_internal call __bn_post4x_internal call __bn_sqr8x_internal call __bn_post4x_internal .byte 102,72,15,126,209 .byte 102,72,15,126,226 movq %rsi,%rdi movq 40(%rsp),%rax leaq 32(%rsp),%r8 call mul4x_internal movq 40(%rsp),%rsi .cfi_def_cfa %rsi,8 movq $1,%rax movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbp .cfi_restore %rbp movq -8(%rsi),%rbx .cfi_restore %rbx leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpower5_epilogue: ret .cfi_endproc .size bn_power5,.-bn_power5 .globl bn_sqr8x_internal .hidden bn_sqr8x_internal .hidden bn_sqr8x_internal .type bn_sqr8x_internal,@function .align 32 bn_sqr8x_internal: __bn_sqr8x_internal: .cfi_startproc _CET_ENDBR leaq 32(%r10),%rbp leaq (%rsi,%r9,1),%rsi movq %r9,%rcx movq -32(%rsi,%rbp,1),%r14 leaq 48+8(%rsp,%r9,2),%rdi movq -24(%rsi,%rbp,1),%rax leaq -32(%rdi,%rbp,1),%rdi movq -16(%rsi,%rbp,1),%rbx movq %rax,%r15 mulq %r14 movq %rax,%r10 movq %rbx,%rax movq %rdx,%r11 movq %r10,-24(%rdi,%rbp,1) mulq %r14 addq %rax,%r11 movq %rbx,%rax adcq $0,%rdx movq %r11,-16(%rdi,%rbp,1) movq %rdx,%r10 movq -8(%rsi,%rbp,1),%rbx mulq %r15 movq %rax,%r12 movq %rbx,%rax movq %rdx,%r13 leaq (%rbp),%rcx mulq %r14 addq %rax,%r10 movq %rbx,%rax movq %rdx,%r11 adcq $0,%r11 addq %r12,%r10 adcq $0,%r11 movq %r10,-8(%rdi,%rcx,1) jmp .Lsqr4x_1st .align 32 .Lsqr4x_1st: movq (%rsi,%rcx,1),%rbx mulq %r15 addq %rax,%r13 movq %rbx,%rax movq %rdx,%r12 adcq $0,%r12 mulq %r14 addq %rax,%r11 movq %rbx,%rax movq 8(%rsi,%rcx,1),%rbx movq %rdx,%r10 adcq $0,%r10 addq %r13,%r11 adcq $0,%r10 mulq %r15 addq %rax,%r12 movq %rbx,%rax movq %r11,(%rdi,%rcx,1) movq %rdx,%r13 adcq $0,%r13 mulq %r14 addq %rax,%r10 movq %rbx,%rax movq 16(%rsi,%rcx,1),%rbx movq %rdx,%r11 adcq $0,%r11 addq %r12,%r10 adcq $0,%r11 mulq %r15 addq %rax,%r13 movq %rbx,%rax movq %r10,8(%rdi,%rcx,1) movq %rdx,%r12 adcq $0,%r12 mulq %r14 addq %rax,%r11 movq %rbx,%rax movq 24(%rsi,%rcx,1),%rbx movq %rdx,%r10 adcq $0,%r10 addq %r13,%r11 adcq $0,%r10 mulq %r15 addq %rax,%r12 movq %rbx,%rax movq %r11,16(%rdi,%rcx,1) movq %rdx,%r13 adcq $0,%r13 leaq 32(%rcx),%rcx mulq %r14 addq %rax,%r10 movq %rbx,%rax movq %rdx,%r11 adcq $0,%r11 addq %r12,%r10 adcq $0,%r11 movq %r10,-8(%rdi,%rcx,1) cmpq $0,%rcx jne .Lsqr4x_1st mulq %r15 addq %rax,%r13 leaq 16(%rbp),%rbp adcq $0,%rdx addq %r11,%r13 adcq $0,%rdx movq %r13,(%rdi) movq %rdx,%r12 movq %rdx,8(%rdi) jmp .Lsqr4x_outer .align 32 .Lsqr4x_outer: movq -32(%rsi,%rbp,1),%r14 leaq 48+8(%rsp,%r9,2),%rdi movq -24(%rsi,%rbp,1),%rax leaq -32(%rdi,%rbp,1),%rdi movq -16(%rsi,%rbp,1),%rbx movq %rax,%r15 mulq %r14 movq -24(%rdi,%rbp,1),%r10 addq %rax,%r10 movq %rbx,%rax adcq $0,%rdx movq %r10,-24(%rdi,%rbp,1) movq %rdx,%r11 mulq %r14 addq %rax,%r11 movq %rbx,%rax adcq $0,%rdx addq -16(%rdi,%rbp,1),%r11 movq %rdx,%r10 adcq $0,%r10 movq %r11,-16(%rdi,%rbp,1) xorq %r12,%r12 movq -8(%rsi,%rbp,1),%rbx mulq %r15 addq %rax,%r12 movq %rbx,%rax adcq $0,%rdx addq -8(%rdi,%rbp,1),%r12 movq %rdx,%r13 adcq $0,%r13 mulq %r14 addq %rax,%r10 movq %rbx,%rax adcq $0,%rdx addq %r12,%r10 movq %rdx,%r11 adcq $0,%r11 movq %r10,-8(%rdi,%rbp,1) leaq (%rbp),%rcx jmp .Lsqr4x_inner .align 32 .Lsqr4x_inner: movq (%rsi,%rcx,1),%rbx mulq %r15 addq %rax,%r13 movq %rbx,%rax movq %rdx,%r12 adcq $0,%r12 addq (%rdi,%rcx,1),%r13 adcq $0,%r12 .byte 0x67 mulq %r14 addq %rax,%r11 movq %rbx,%rax movq 8(%rsi,%rcx,1),%rbx movq %rdx,%r10 adcq $0,%r10 addq %r13,%r11 adcq $0,%r10 mulq %r15 addq %rax,%r12 movq %r11,(%rdi,%rcx,1) movq %rbx,%rax movq %rdx,%r13 adcq $0,%r13 addq 8(%rdi,%rcx,1),%r12 leaq 16(%rcx),%rcx adcq $0,%r13 mulq %r14 addq %rax,%r10 movq %rbx,%rax adcq $0,%rdx addq %r12,%r10 movq %rdx,%r11 adcq $0,%r11 movq %r10,-8(%rdi,%rcx,1) cmpq $0,%rcx jne .Lsqr4x_inner .byte 0x67 mulq %r15 addq %rax,%r13 adcq $0,%rdx addq %r11,%r13 adcq $0,%rdx movq %r13,(%rdi) movq %rdx,%r12 movq %rdx,8(%rdi) addq $16,%rbp jnz .Lsqr4x_outer movq -32(%rsi),%r14 leaq 48+8(%rsp,%r9,2),%rdi movq -24(%rsi),%rax leaq -32(%rdi,%rbp,1),%rdi movq -16(%rsi),%rbx movq %rax,%r15 mulq %r14 addq %rax,%r10 movq %rbx,%rax movq %rdx,%r11 adcq $0,%r11 mulq %r14 addq %rax,%r11 movq %rbx,%rax movq %r10,-24(%rdi) movq %rdx,%r10 adcq $0,%r10 addq %r13,%r11 movq -8(%rsi),%rbx adcq $0,%r10 mulq %r15 addq %rax,%r12 movq %rbx,%rax movq %r11,-16(%rdi) movq %rdx,%r13 adcq $0,%r13 mulq %r14 addq %rax,%r10 movq %rbx,%rax movq %rdx,%r11 adcq $0,%r11 addq %r12,%r10 adcq $0,%r11 movq %r10,-8(%rdi) mulq %r15 addq %rax,%r13 movq -16(%rsi),%rax adcq $0,%rdx addq %r11,%r13 adcq $0,%rdx movq %r13,(%rdi) movq %rdx,%r12 movq %rdx,8(%rdi) mulq %rbx addq $16,%rbp xorq %r14,%r14 subq %r9,%rbp xorq %r15,%r15 addq %r12,%rax adcq $0,%rdx movq %rax,8(%rdi) movq %rdx,16(%rdi) movq %r15,24(%rdi) movq -16(%rsi,%rbp,1),%rax leaq 48+8(%rsp),%rdi xorq %r10,%r10 movq 8(%rdi),%r11 leaq (%r14,%r10,2),%r12 shrq $63,%r10 leaq (%rcx,%r11,2),%r13 shrq $63,%r11 orq %r10,%r13 movq 16(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq 24(%rdi),%r11 adcq %rax,%r12 movq -8(%rsi,%rbp,1),%rax movq %r12,(%rdi) adcq %rdx,%r13 leaq (%r14,%r10,2),%rbx movq %r13,8(%rdi) sbbq %r15,%r15 shrq $63,%r10 leaq (%rcx,%r11,2),%r8 shrq $63,%r11 orq %r10,%r8 movq 32(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq 40(%rdi),%r11 adcq %rax,%rbx movq 0(%rsi,%rbp,1),%rax movq %rbx,16(%rdi) adcq %rdx,%r8 leaq 16(%rbp),%rbp movq %r8,24(%rdi) sbbq %r15,%r15 leaq 64(%rdi),%rdi jmp .Lsqr4x_shift_n_add .align 32 .Lsqr4x_shift_n_add: leaq (%r14,%r10,2),%r12 shrq $63,%r10 leaq (%rcx,%r11,2),%r13 shrq $63,%r11 orq %r10,%r13 movq -16(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq -8(%rdi),%r11 adcq %rax,%r12 movq -8(%rsi,%rbp,1),%rax movq %r12,-32(%rdi) adcq %rdx,%r13 leaq (%r14,%r10,2),%rbx movq %r13,-24(%rdi) sbbq %r15,%r15 shrq $63,%r10 leaq (%rcx,%r11,2),%r8 shrq $63,%r11 orq %r10,%r8 movq 0(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq 8(%rdi),%r11 adcq %rax,%rbx movq 0(%rsi,%rbp,1),%rax movq %rbx,-16(%rdi) adcq %rdx,%r8 leaq (%r14,%r10,2),%r12 movq %r8,-8(%rdi) sbbq %r15,%r15 shrq $63,%r10 leaq (%rcx,%r11,2),%r13 shrq $63,%r11 orq %r10,%r13 movq 16(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq 24(%rdi),%r11 adcq %rax,%r12 movq 8(%rsi,%rbp,1),%rax movq %r12,0(%rdi) adcq %rdx,%r13 leaq (%r14,%r10,2),%rbx movq %r13,8(%rdi) sbbq %r15,%r15 shrq $63,%r10 leaq (%rcx,%r11,2),%r8 shrq $63,%r11 orq %r10,%r8 movq 32(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq 40(%rdi),%r11 adcq %rax,%rbx movq 16(%rsi,%rbp,1),%rax movq %rbx,16(%rdi) adcq %rdx,%r8 movq %r8,24(%rdi) sbbq %r15,%r15 leaq 64(%rdi),%rdi addq $32,%rbp jnz .Lsqr4x_shift_n_add leaq (%r14,%r10,2),%r12 .byte 0x67 shrq $63,%r10 leaq (%rcx,%r11,2),%r13 shrq $63,%r11 orq %r10,%r13 movq -16(%rdi),%r10 movq %r11,%r14 mulq %rax negq %r15 movq -8(%rdi),%r11 adcq %rax,%r12 movq -8(%rsi),%rax movq %r12,-32(%rdi) adcq %rdx,%r13 leaq (%r14,%r10,2),%rbx movq %r13,-24(%rdi) sbbq %r15,%r15 shrq $63,%r10 leaq (%rcx,%r11,2),%r8 shrq $63,%r11 orq %r10,%r8 mulq %rax negq %r15 adcq %rax,%rbx adcq %rdx,%r8 movq %rbx,-16(%rdi) movq %r8,-8(%rdi) .byte 102,72,15,126,213 __bn_sqr8x_reduction: xorq %rax,%rax leaq (%r9,%rbp,1),%rcx leaq 48+8(%rsp,%r9,2),%rdx movq %rcx,0+8(%rsp) leaq 48+8(%rsp,%r9,1),%rdi movq %rdx,8+8(%rsp) negq %r9 jmp .L8x_reduction_loop .align 32 .L8x_reduction_loop: leaq (%rdi,%r9,1),%rdi .byte 0x66 movq 0(%rdi),%rbx movq 8(%rdi),%r9 movq 16(%rdi),%r10 movq 24(%rdi),%r11 movq 32(%rdi),%r12 movq 40(%rdi),%r13 movq 48(%rdi),%r14 movq 56(%rdi),%r15 movq %rax,(%rdx) leaq 64(%rdi),%rdi .byte 0x67 movq %rbx,%r8 imulq 32+8(%rsp),%rbx movq 0(%rbp),%rax movl $8,%ecx jmp .L8x_reduce .align 32 .L8x_reduce: mulq %rbx movq 8(%rbp),%rax negq %r8 movq %rdx,%r8 adcq $0,%r8 mulq %rbx addq %rax,%r9 movq 16(%rbp),%rax adcq $0,%rdx addq %r9,%r8 movq %rbx,48-8+8(%rsp,%rcx,8) movq %rdx,%r9 adcq $0,%r9 mulq %rbx addq %rax,%r10 movq 24(%rbp),%rax adcq $0,%rdx addq %r10,%r9 movq 32+8(%rsp),%rsi movq %rdx,%r10 adcq $0,%r10 mulq %rbx addq %rax,%r11 movq 32(%rbp),%rax adcq $0,%rdx imulq %r8,%rsi addq %r11,%r10 movq %rdx,%r11 adcq $0,%r11 mulq %rbx addq %rax,%r12 movq 40(%rbp),%rax adcq $0,%rdx addq %r12,%r11 movq %rdx,%r12 adcq $0,%r12 mulq %rbx addq %rax,%r13 movq 48(%rbp),%rax adcq $0,%rdx addq %r13,%r12 movq %rdx,%r13 adcq $0,%r13 mulq %rbx addq %rax,%r14 movq 56(%rbp),%rax adcq $0,%rdx addq %r14,%r13 movq %rdx,%r14 adcq $0,%r14 mulq %rbx movq %rsi,%rbx addq %rax,%r15 movq 0(%rbp),%rax adcq $0,%rdx addq %r15,%r14 movq %rdx,%r15 adcq $0,%r15 decl %ecx jnz .L8x_reduce leaq 64(%rbp),%rbp xorq %rax,%rax movq 8+8(%rsp),%rdx cmpq 0+8(%rsp),%rbp jae .L8x_no_tail .byte 0x66 addq 0(%rdi),%r8 adcq 8(%rdi),%r9 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 sbbq %rsi,%rsi movq 48+56+8(%rsp),%rbx movl $8,%ecx movq 0(%rbp),%rax jmp .L8x_tail .align 32 .L8x_tail: mulq %rbx addq %rax,%r8 movq 8(%rbp),%rax movq %r8,(%rdi) movq %rdx,%r8 adcq $0,%r8 mulq %rbx addq %rax,%r9 movq 16(%rbp),%rax adcq $0,%rdx addq %r9,%r8 leaq 8(%rdi),%rdi movq %rdx,%r9 adcq $0,%r9 mulq %rbx addq %rax,%r10 movq 24(%rbp),%rax adcq $0,%rdx addq %r10,%r9 movq %rdx,%r10 adcq $0,%r10 mulq %rbx addq %rax,%r11 movq 32(%rbp),%rax adcq $0,%rdx addq %r11,%r10 movq %rdx,%r11 adcq $0,%r11 mulq %rbx addq %rax,%r12 movq 40(%rbp),%rax adcq $0,%rdx addq %r12,%r11 movq %rdx,%r12 adcq $0,%r12 mulq %rbx addq %rax,%r13 movq 48(%rbp),%rax adcq $0,%rdx addq %r13,%r12 movq %rdx,%r13 adcq $0,%r13 mulq %rbx addq %rax,%r14 movq 56(%rbp),%rax adcq $0,%rdx addq %r14,%r13 movq %rdx,%r14 adcq $0,%r14 mulq %rbx movq 48-16+8(%rsp,%rcx,8),%rbx addq %rax,%r15 adcq $0,%rdx addq %r15,%r14 movq 0(%rbp),%rax movq %rdx,%r15 adcq $0,%r15 decl %ecx jnz .L8x_tail leaq 64(%rbp),%rbp movq 8+8(%rsp),%rdx cmpq 0+8(%rsp),%rbp jae .L8x_tail_done movq 48+56+8(%rsp),%rbx negq %rsi movq 0(%rbp),%rax adcq 0(%rdi),%r8 adcq 8(%rdi),%r9 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 sbbq %rsi,%rsi movl $8,%ecx jmp .L8x_tail .align 32 .L8x_tail_done: xorq %rax,%rax addq (%rdx),%r8 adcq $0,%r9 adcq $0,%r10 adcq $0,%r11 adcq $0,%r12 adcq $0,%r13 adcq $0,%r14 adcq $0,%r15 adcq $0,%rax negq %rsi .L8x_no_tail: adcq 0(%rdi),%r8 adcq 8(%rdi),%r9 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 adcq $0,%rax movq -8(%rbp),%rcx xorq %rsi,%rsi .byte 102,72,15,126,213 movq %r8,0(%rdi) movq %r9,8(%rdi) .byte 102,73,15,126,217 movq %r10,16(%rdi) movq %r11,24(%rdi) movq %r12,32(%rdi) movq %r13,40(%rdi) movq %r14,48(%rdi) movq %r15,56(%rdi) leaq 64(%rdi),%rdi cmpq %rdx,%rdi jb .L8x_reduction_loop ret .cfi_endproc .size bn_sqr8x_internal,.-bn_sqr8x_internal .type __bn_post4x_internal,@function .align 32 __bn_post4x_internal: .cfi_startproc movq 0(%rbp),%r12 leaq (%rdi,%r9,1),%rbx movq %r9,%rcx .byte 102,72,15,126,207 negq %rax .byte 102,72,15,126,206 sarq $3+2,%rcx decq %r12 xorq %r10,%r10 movq 8(%rbp),%r13 movq 16(%rbp),%r14 movq 24(%rbp),%r15 jmp .Lsqr4x_sub_entry .align 16 .Lsqr4x_sub: movq 0(%rbp),%r12 movq 8(%rbp),%r13 movq 16(%rbp),%r14 movq 24(%rbp),%r15 .Lsqr4x_sub_entry: leaq 32(%rbp),%rbp notq %r12 notq %r13 notq %r14 notq %r15 andq %rax,%r12 andq %rax,%r13 andq %rax,%r14 andq %rax,%r15 negq %r10 adcq 0(%rbx),%r12 adcq 8(%rbx),%r13 adcq 16(%rbx),%r14 adcq 24(%rbx),%r15 movq %r12,0(%rdi) leaq 32(%rbx),%rbx movq %r13,8(%rdi) sbbq %r10,%r10 movq %r14,16(%rdi) movq %r15,24(%rdi) leaq 32(%rdi),%rdi incq %rcx jnz .Lsqr4x_sub movq %r9,%r10 negq %r9 ret .cfi_endproc .size __bn_post4x_internal,.-__bn_post4x_internal .type bn_mulx4x_mont_gather5,@function .align 32 bn_mulx4x_mont_gather5: .cfi_startproc movq %rsp,%rax .cfi_def_cfa_register %rax .Lmulx4x_enter: pushq %rbx .cfi_offset %rbx,-16 pushq %rbp .cfi_offset %rbp,-24 pushq %r12 .cfi_offset %r12,-32 pushq %r13 .cfi_offset %r13,-40 pushq %r14 .cfi_offset %r14,-48 pushq %r15 .cfi_offset %r15,-56 .Lmulx4x_prologue: shll $3,%r9d leaq (%r9,%r9,2),%r10 negq %r9 movq (%r8),%r8 leaq -320(%rsp,%r9,2),%r11 movq %rsp,%rbp subq %rdi,%r11 andq $4095,%r11 cmpq %r11,%r10 jb .Lmulx4xsp_alt subq %r11,%rbp leaq -320(%rbp,%r9,2),%rbp jmp .Lmulx4xsp_done .Lmulx4xsp_alt: leaq 4096-320(,%r9,2),%r10 leaq -320(%rbp,%r9,2),%rbp subq %r10,%r11 movq $0,%r10 cmovcq %r10,%r11 subq %r11,%rbp .Lmulx4xsp_done: andq $-64,%rbp movq %rsp,%r11 subq %rbp,%r11 andq $-4096,%r11 leaq (%r11,%rbp,1),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lmulx4x_page_walk jmp .Lmulx4x_page_walk_done .Lmulx4x_page_walk: leaq -4096(%rsp),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lmulx4x_page_walk .Lmulx4x_page_walk_done: movq %r8,32(%rsp) movq %rax,40(%rsp) .cfi_escape 0x0f,0x05,0x77,0x28,0x06,0x23,0x08 .Lmulx4x_body: call mulx4x_internal movq 40(%rsp),%rsi .cfi_def_cfa %rsi,8 movq $1,%rax movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbp .cfi_restore %rbp movq -8(%rsi),%rbx .cfi_restore %rbx leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lmulx4x_epilogue: ret .cfi_endproc .size bn_mulx4x_mont_gather5,.-bn_mulx4x_mont_gather5 .type mulx4x_internal,@function .align 32 mulx4x_internal: .cfi_startproc movq %r9,8(%rsp) movq %r9,%r10 negq %r9 shlq $5,%r9 negq %r10 leaq 128(%rdx,%r9,1),%r13 shrq $5+5,%r9 movd 8(%rax),%xmm5 subq $1,%r9 leaq .Linc(%rip),%rax movq %r13,16+8(%rsp) movq %r9,24+8(%rsp) movq %rdi,56+8(%rsp) movdqa 0(%rax),%xmm0 movdqa 16(%rax),%xmm1 leaq 88-112(%rsp,%r10,1),%r10 leaq 128(%rdx),%rdi pshufd $0,%xmm5,%xmm5 movdqa %xmm1,%xmm4 .byte 0x67 movdqa %xmm1,%xmm2 .byte 0x67 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,112(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,128(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,144(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,160(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,176(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,192(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,208(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,224(%r10) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,240(%r10) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,256(%r10) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,272(%r10) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,288(%r10) movdqa %xmm4,%xmm3 .byte 0x67 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,304(%r10) paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,320(%r10) pcmpeqd %xmm5,%xmm3 movdqa %xmm2,336(%r10) pand 64(%rdi),%xmm0 pand 80(%rdi),%xmm1 pand 96(%rdi),%xmm2 movdqa %xmm3,352(%r10) pand 112(%rdi),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -128(%rdi),%xmm4 movdqa -112(%rdi),%xmm5 movdqa -96(%rdi),%xmm2 pand 112(%r10),%xmm4 movdqa -80(%rdi),%xmm3 pand 128(%r10),%xmm5 por %xmm4,%xmm0 pand 144(%r10),%xmm2 por %xmm5,%xmm1 pand 160(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa -64(%rdi),%xmm4 movdqa -48(%rdi),%xmm5 movdqa -32(%rdi),%xmm2 pand 176(%r10),%xmm4 movdqa -16(%rdi),%xmm3 pand 192(%r10),%xmm5 por %xmm4,%xmm0 pand 208(%r10),%xmm2 por %xmm5,%xmm1 pand 224(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 movdqa 0(%rdi),%xmm4 movdqa 16(%rdi),%xmm5 movdqa 32(%rdi),%xmm2 pand 240(%r10),%xmm4 movdqa 48(%rdi),%xmm3 pand 256(%r10),%xmm5 por %xmm4,%xmm0 pand 272(%r10),%xmm2 por %xmm5,%xmm1 pand 288(%r10),%xmm3 por %xmm2,%xmm0 por %xmm3,%xmm1 pxor %xmm1,%xmm0 pshufd $0x4e,%xmm0,%xmm1 por %xmm1,%xmm0 leaq 256(%rdi),%rdi .byte 102,72,15,126,194 leaq 64+32+8(%rsp),%rbx movq %rdx,%r9 mulxq 0(%rsi),%r8,%rax mulxq 8(%rsi),%r11,%r12 addq %rax,%r11 mulxq 16(%rsi),%rax,%r13 adcq %rax,%r12 adcq $0,%r13 mulxq 24(%rsi),%rax,%r14 movq %r8,%r15 imulq 32+8(%rsp),%r8 xorq %rbp,%rbp movq %r8,%rdx movq %rdi,8+8(%rsp) leaq 32(%rsi),%rsi adcxq %rax,%r13 adcxq %rbp,%r14 mulxq 0(%rcx),%rax,%r10 adcxq %rax,%r15 adoxq %r11,%r10 mulxq 8(%rcx),%rax,%r11 adcxq %rax,%r10 adoxq %r12,%r11 mulxq 16(%rcx),%rax,%r12 movq 24+8(%rsp),%rdi movq %r10,-32(%rbx) adcxq %rax,%r11 adoxq %r13,%r12 mulxq 24(%rcx),%rax,%r15 movq %r9,%rdx movq %r11,-24(%rbx) adcxq %rax,%r12 adoxq %rbp,%r15 leaq 32(%rcx),%rcx movq %r12,-16(%rbx) jmp .Lmulx4x_1st .align 32 .Lmulx4x_1st: adcxq %rbp,%r15 mulxq 0(%rsi),%r10,%rax adcxq %r14,%r10 mulxq 8(%rsi),%r11,%r14 adcxq %rax,%r11 mulxq 16(%rsi),%r12,%rax adcxq %r14,%r12 mulxq 24(%rsi),%r13,%r14 .byte 0x67,0x67 movq %r8,%rdx adcxq %rax,%r13 adcxq %rbp,%r14 leaq 32(%rsi),%rsi leaq 32(%rbx),%rbx adoxq %r15,%r10 mulxq 0(%rcx),%rax,%r15 adcxq %rax,%r10 adoxq %r15,%r11 mulxq 8(%rcx),%rax,%r15 adcxq %rax,%r11 adoxq %r15,%r12 mulxq 16(%rcx),%rax,%r15 movq %r10,-40(%rbx) adcxq %rax,%r12 movq %r11,-32(%rbx) adoxq %r15,%r13 mulxq 24(%rcx),%rax,%r15 movq %r9,%rdx movq %r12,-24(%rbx) adcxq %rax,%r13 adoxq %rbp,%r15 leaq 32(%rcx),%rcx movq %r13,-16(%rbx) decq %rdi jnz .Lmulx4x_1st movq 8(%rsp),%rax adcq %rbp,%r15 leaq (%rsi,%rax,1),%rsi addq %r15,%r14 movq 8+8(%rsp),%rdi adcq %rbp,%rbp movq %r14,-8(%rbx) jmp .Lmulx4x_outer .align 32 .Lmulx4x_outer: leaq 16-256(%rbx),%r10 pxor %xmm4,%xmm4 .byte 0x67,0x67 pxor %xmm5,%xmm5 movdqa -128(%rdi),%xmm0 movdqa -112(%rdi),%xmm1 movdqa -96(%rdi),%xmm2 pand 256(%r10),%xmm0 movdqa -80(%rdi),%xmm3 pand 272(%r10),%xmm1 por %xmm0,%xmm4 pand 288(%r10),%xmm2 por %xmm1,%xmm5 pand 304(%r10),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa -64(%rdi),%xmm0 movdqa -48(%rdi),%xmm1 movdqa -32(%rdi),%xmm2 pand 320(%r10),%xmm0 movdqa -16(%rdi),%xmm3 pand 336(%r10),%xmm1 por %xmm0,%xmm4 pand 352(%r10),%xmm2 por %xmm1,%xmm5 pand 368(%r10),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 0(%rdi),%xmm0 movdqa 16(%rdi),%xmm1 movdqa 32(%rdi),%xmm2 pand 384(%r10),%xmm0 movdqa 48(%rdi),%xmm3 pand 400(%r10),%xmm1 por %xmm0,%xmm4 pand 416(%r10),%xmm2 por %xmm1,%xmm5 pand 432(%r10),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 64(%rdi),%xmm0 movdqa 80(%rdi),%xmm1 movdqa 96(%rdi),%xmm2 pand 448(%r10),%xmm0 movdqa 112(%rdi),%xmm3 pand 464(%r10),%xmm1 por %xmm0,%xmm4 pand 480(%r10),%xmm2 por %xmm1,%xmm5 pand 496(%r10),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 por %xmm5,%xmm4 pshufd $0x4e,%xmm4,%xmm0 por %xmm4,%xmm0 leaq 256(%rdi),%rdi .byte 102,72,15,126,194 movq %rbp,(%rbx) leaq 32(%rbx,%rax,1),%rbx mulxq 0(%rsi),%r8,%r11 xorq %rbp,%rbp movq %rdx,%r9 mulxq 8(%rsi),%r14,%r12 adoxq -32(%rbx),%r8 adcxq %r14,%r11 mulxq 16(%rsi),%r15,%r13 adoxq -24(%rbx),%r11 adcxq %r15,%r12 mulxq 24(%rsi),%rdx,%r14 adoxq -16(%rbx),%r12 adcxq %rdx,%r13 leaq (%rcx,%rax,1),%rcx leaq 32(%rsi),%rsi adoxq -8(%rbx),%r13 adcxq %rbp,%r14 adoxq %rbp,%r14 movq %r8,%r15 imulq 32+8(%rsp),%r8 movq %r8,%rdx xorq %rbp,%rbp movq %rdi,8+8(%rsp) mulxq 0(%rcx),%rax,%r10 adcxq %rax,%r15 adoxq %r11,%r10 mulxq 8(%rcx),%rax,%r11 adcxq %rax,%r10 adoxq %r12,%r11 mulxq 16(%rcx),%rax,%r12 adcxq %rax,%r11 adoxq %r13,%r12 mulxq 24(%rcx),%rax,%r15 movq %r9,%rdx movq 24+8(%rsp),%rdi movq %r10,-32(%rbx) adcxq %rax,%r12 movq %r11,-24(%rbx) adoxq %rbp,%r15 movq %r12,-16(%rbx) leaq 32(%rcx),%rcx jmp .Lmulx4x_inner .align 32 .Lmulx4x_inner: mulxq 0(%rsi),%r10,%rax adcxq %rbp,%r15 adoxq %r14,%r10 mulxq 8(%rsi),%r11,%r14 adcxq 0(%rbx),%r10 adoxq %rax,%r11 mulxq 16(%rsi),%r12,%rax adcxq 8(%rbx),%r11 adoxq %r14,%r12 mulxq 24(%rsi),%r13,%r14 movq %r8,%rdx adcxq 16(%rbx),%r12 adoxq %rax,%r13 adcxq 24(%rbx),%r13 adoxq %rbp,%r14 leaq 32(%rsi),%rsi leaq 32(%rbx),%rbx adcxq %rbp,%r14 adoxq %r15,%r10 mulxq 0(%rcx),%rax,%r15 adcxq %rax,%r10 adoxq %r15,%r11 mulxq 8(%rcx),%rax,%r15 adcxq %rax,%r11 adoxq %r15,%r12 mulxq 16(%rcx),%rax,%r15 movq %r10,-40(%rbx) adcxq %rax,%r12 adoxq %r15,%r13 movq %r11,-32(%rbx) mulxq 24(%rcx),%rax,%r15 movq %r9,%rdx leaq 32(%rcx),%rcx movq %r12,-24(%rbx) adcxq %rax,%r13 adoxq %rbp,%r15 movq %r13,-16(%rbx) decq %rdi jnz .Lmulx4x_inner movq 0+8(%rsp),%rax adcq %rbp,%r15 subq 0(%rbx),%rdi movq 8+8(%rsp),%rdi movq 16+8(%rsp),%r10 adcq %r15,%r14 leaq (%rsi,%rax,1),%rsi adcq %rbp,%rbp movq %r14,-8(%rbx) cmpq %r10,%rdi jb .Lmulx4x_outer movq -8(%rcx),%r10 movq %rbp,%r8 movq (%rcx,%rax,1),%r12 leaq (%rcx,%rax,1),%rbp movq %rax,%rcx leaq (%rbx,%rax,1),%rdi xorl %eax,%eax xorq %r15,%r15 subq %r14,%r10 adcq %r15,%r15 orq %r15,%r8 sarq $3+2,%rcx subq %r8,%rax movq 56+8(%rsp),%rdx decq %r12 movq 8(%rbp),%r13 xorq %r8,%r8 movq 16(%rbp),%r14 movq 24(%rbp),%r15 jmp .Lsqrx4x_sub_entry .cfi_endproc .size mulx4x_internal,.-mulx4x_internal .type bn_powerx5,@function .align 32 bn_powerx5: .cfi_startproc movq %rsp,%rax .cfi_def_cfa_register %rax .Lpowerx5_enter: pushq %rbx .cfi_offset %rbx,-16 pushq %rbp .cfi_offset %rbp,-24 pushq %r12 .cfi_offset %r12,-32 pushq %r13 .cfi_offset %r13,-40 pushq %r14 .cfi_offset %r14,-48 pushq %r15 .cfi_offset %r15,-56 .Lpowerx5_prologue: shll $3,%r9d leaq (%r9,%r9,2),%r10 negq %r9 movq (%r8),%r8 leaq -320(%rsp,%r9,2),%r11 movq %rsp,%rbp subq %rdi,%r11 andq $4095,%r11 cmpq %r11,%r10 jb .Lpwrx_sp_alt subq %r11,%rbp leaq -320(%rbp,%r9,2),%rbp jmp .Lpwrx_sp_done .align 32 .Lpwrx_sp_alt: leaq 4096-320(,%r9,2),%r10 leaq -320(%rbp,%r9,2),%rbp subq %r10,%r11 movq $0,%r10 cmovcq %r10,%r11 subq %r11,%rbp .Lpwrx_sp_done: andq $-64,%rbp movq %rsp,%r11 subq %rbp,%r11 andq $-4096,%r11 leaq (%r11,%rbp,1),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lpwrx_page_walk jmp .Lpwrx_page_walk_done .Lpwrx_page_walk: leaq -4096(%rsp),%rsp movq (%rsp),%r10 cmpq %rbp,%rsp ja .Lpwrx_page_walk .Lpwrx_page_walk_done: movq %r9,%r10 negq %r9 pxor %xmm0,%xmm0 .byte 102,72,15,110,207 .byte 102,72,15,110,209 .byte 102,73,15,110,218 .byte 102,72,15,110,226 movq %r8,32(%rsp) movq %rax,40(%rsp) .cfi_escape 0x0f,0x05,0x77,0x28,0x06,0x23,0x08 .Lpowerx5_body: call __bn_sqrx8x_internal call __bn_postx4x_internal call __bn_sqrx8x_internal call __bn_postx4x_internal call __bn_sqrx8x_internal call __bn_postx4x_internal call __bn_sqrx8x_internal call __bn_postx4x_internal call __bn_sqrx8x_internal call __bn_postx4x_internal movq %r10,%r9 movq %rsi,%rdi .byte 102,72,15,126,209 .byte 102,72,15,126,226 movq 40(%rsp),%rax call mulx4x_internal movq 40(%rsp),%rsi .cfi_def_cfa %rsi,8 movq $1,%rax movq -48(%rsi),%r15 .cfi_restore %r15 movq -40(%rsi),%r14 .cfi_restore %r14 movq -32(%rsi),%r13 .cfi_restore %r13 movq -24(%rsi),%r12 .cfi_restore %r12 movq -16(%rsi),%rbp .cfi_restore %rbp movq -8(%rsi),%rbx .cfi_restore %rbx leaq (%rsi),%rsp .cfi_def_cfa_register %rsp .Lpowerx5_epilogue: ret .cfi_endproc .size bn_powerx5,.-bn_powerx5 .globl bn_sqrx8x_internal .hidden bn_sqrx8x_internal .hidden bn_sqrx8x_internal .type bn_sqrx8x_internal,@function .align 32 bn_sqrx8x_internal: __bn_sqrx8x_internal: .cfi_startproc _CET_ENDBR leaq 48+8(%rsp),%rdi leaq (%rsi,%r9,1),%rbp movq %r9,0+8(%rsp) movq %rbp,8+8(%rsp) jmp .Lsqr8x_zero_start .align 32 .byte 0x66,0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00 .Lsqrx8x_zero: .byte 0x3e movdqa %xmm0,0(%rdi) movdqa %xmm0,16(%rdi) movdqa %xmm0,32(%rdi) movdqa %xmm0,48(%rdi) .Lsqr8x_zero_start: movdqa %xmm0,64(%rdi) movdqa %xmm0,80(%rdi) movdqa %xmm0,96(%rdi) movdqa %xmm0,112(%rdi) leaq 128(%rdi),%rdi subq $64,%r9 jnz .Lsqrx8x_zero movq 0(%rsi),%rdx xorq %r10,%r10 xorq %r11,%r11 xorq %r12,%r12 xorq %r13,%r13 xorq %r14,%r14 xorq %r15,%r15 leaq 48+8(%rsp),%rdi xorq %rbp,%rbp jmp .Lsqrx8x_outer_loop .align 32 .Lsqrx8x_outer_loop: mulxq 8(%rsi),%r8,%rax adcxq %r9,%r8 adoxq %rax,%r10 mulxq 16(%rsi),%r9,%rax adcxq %r10,%r9 adoxq %rax,%r11 .byte 0xc4,0xe2,0xab,0xf6,0x86,0x18,0x00,0x00,0x00 adcxq %r11,%r10 adoxq %rax,%r12 .byte 0xc4,0xe2,0xa3,0xf6,0x86,0x20,0x00,0x00,0x00 adcxq %r12,%r11 adoxq %rax,%r13 mulxq 40(%rsi),%r12,%rax adcxq %r13,%r12 adoxq %rax,%r14 mulxq 48(%rsi),%r13,%rax adcxq %r14,%r13 adoxq %r15,%rax mulxq 56(%rsi),%r14,%r15 movq 8(%rsi),%rdx adcxq %rax,%r14 adoxq %rbp,%r15 adcq 64(%rdi),%r15 movq %r8,8(%rdi) movq %r9,16(%rdi) sbbq %rcx,%rcx xorq %rbp,%rbp mulxq 16(%rsi),%r8,%rbx mulxq 24(%rsi),%r9,%rax adcxq %r10,%r8 adoxq %rbx,%r9 mulxq 32(%rsi),%r10,%rbx adcxq %r11,%r9 adoxq %rax,%r10 .byte 0xc4,0xe2,0xa3,0xf6,0x86,0x28,0x00,0x00,0x00 adcxq %r12,%r10 adoxq %rbx,%r11 .byte 0xc4,0xe2,0x9b,0xf6,0x9e,0x30,0x00,0x00,0x00 adcxq %r13,%r11 adoxq %r14,%r12 .byte 0xc4,0x62,0x93,0xf6,0xb6,0x38,0x00,0x00,0x00 movq 16(%rsi),%rdx adcxq %rax,%r12 adoxq %rbx,%r13 adcxq %r15,%r13 adoxq %rbp,%r14 adcxq %rbp,%r14 movq %r8,24(%rdi) movq %r9,32(%rdi) mulxq 24(%rsi),%r8,%rbx mulxq 32(%rsi),%r9,%rax adcxq %r10,%r8 adoxq %rbx,%r9 mulxq 40(%rsi),%r10,%rbx adcxq %r11,%r9 adoxq %rax,%r10 .byte 0xc4,0xe2,0xa3,0xf6,0x86,0x30,0x00,0x00,0x00 adcxq %r12,%r10 adoxq %r13,%r11 .byte 0xc4,0x62,0x9b,0xf6,0xae,0x38,0x00,0x00,0x00 .byte 0x3e movq 24(%rsi),%rdx adcxq %rbx,%r11 adoxq %rax,%r12 adcxq %r14,%r12 movq %r8,40(%rdi) movq %r9,48(%rdi) mulxq 32(%rsi),%r8,%rax adoxq %rbp,%r13 adcxq %rbp,%r13 mulxq 40(%rsi),%r9,%rbx adcxq %r10,%r8 adoxq %rax,%r9 mulxq 48(%rsi),%r10,%rax adcxq %r11,%r9 adoxq %r12,%r10 mulxq 56(%rsi),%r11,%r12 movq 32(%rsi),%rdx movq 40(%rsi),%r14 adcxq %rbx,%r10 adoxq %rax,%r11 movq 48(%rsi),%r15 adcxq %r13,%r11 adoxq %rbp,%r12 adcxq %rbp,%r12 movq %r8,56(%rdi) movq %r9,64(%rdi) mulxq %r14,%r9,%rax movq 56(%rsi),%r8 adcxq %r10,%r9 mulxq %r15,%r10,%rbx adoxq %rax,%r10 adcxq %r11,%r10 mulxq %r8,%r11,%rax movq %r14,%rdx adoxq %rbx,%r11 adcxq %r12,%r11 adcxq %rbp,%rax mulxq %r15,%r14,%rbx mulxq %r8,%r12,%r13 movq %r15,%rdx leaq 64(%rsi),%rsi adcxq %r14,%r11 adoxq %rbx,%r12 adcxq %rax,%r12 adoxq %rbp,%r13 .byte 0x67,0x67 mulxq %r8,%r8,%r14 adcxq %r8,%r13 adcxq %rbp,%r14 cmpq 8+8(%rsp),%rsi je .Lsqrx8x_outer_break negq %rcx movq $-8,%rcx movq %rbp,%r15 movq 64(%rdi),%r8 adcxq 72(%rdi),%r9 adcxq 80(%rdi),%r10 adcxq 88(%rdi),%r11 adcq 96(%rdi),%r12 adcq 104(%rdi),%r13 adcq 112(%rdi),%r14 adcq 120(%rdi),%r15 leaq (%rsi),%rbp leaq 128(%rdi),%rdi sbbq %rax,%rax movq -64(%rsi),%rdx movq %rax,16+8(%rsp) movq %rdi,24+8(%rsp) xorl %eax,%eax jmp .Lsqrx8x_loop .align 32 .Lsqrx8x_loop: movq %r8,%rbx mulxq 0(%rbp),%rax,%r8 adcxq %rax,%rbx adoxq %r9,%r8 mulxq 8(%rbp),%rax,%r9 adcxq %rax,%r8 adoxq %r10,%r9 mulxq 16(%rbp),%rax,%r10 adcxq %rax,%r9 adoxq %r11,%r10 mulxq 24(%rbp),%rax,%r11 adcxq %rax,%r10 adoxq %r12,%r11 .byte 0xc4,0x62,0xfb,0xf6,0xa5,0x20,0x00,0x00,0x00 adcxq %rax,%r11 adoxq %r13,%r12 mulxq 40(%rbp),%rax,%r13 adcxq %rax,%r12 adoxq %r14,%r13 mulxq 48(%rbp),%rax,%r14 movq %rbx,(%rdi,%rcx,8) movl $0,%ebx adcxq %rax,%r13 adoxq %r15,%r14 .byte 0xc4,0x62,0xfb,0xf6,0xbd,0x38,0x00,0x00,0x00 movq 8(%rsi,%rcx,8),%rdx adcxq %rax,%r14 adoxq %rbx,%r15 adcxq %rbx,%r15 .byte 0x67 incq %rcx jnz .Lsqrx8x_loop leaq 64(%rbp),%rbp movq $-8,%rcx cmpq 8+8(%rsp),%rbp je .Lsqrx8x_break subq 16+8(%rsp),%rbx .byte 0x66 movq -64(%rsi),%rdx adcxq 0(%rdi),%r8 adcxq 8(%rdi),%r9 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 leaq 64(%rdi),%rdi .byte 0x67 sbbq %rax,%rax xorl %ebx,%ebx movq %rax,16+8(%rsp) jmp .Lsqrx8x_loop .align 32 .Lsqrx8x_break: xorq %rbp,%rbp subq 16+8(%rsp),%rbx adcxq %rbp,%r8 movq 24+8(%rsp),%rcx adcxq %rbp,%r9 movq 0(%rsi),%rdx adcq $0,%r10 movq %r8,0(%rdi) adcq $0,%r11 adcq $0,%r12 adcq $0,%r13 adcq $0,%r14 adcq $0,%r15 cmpq %rcx,%rdi je .Lsqrx8x_outer_loop movq %r9,8(%rdi) movq 8(%rcx),%r9 movq %r10,16(%rdi) movq 16(%rcx),%r10 movq %r11,24(%rdi) movq 24(%rcx),%r11 movq %r12,32(%rdi) movq 32(%rcx),%r12 movq %r13,40(%rdi) movq 40(%rcx),%r13 movq %r14,48(%rdi) movq 48(%rcx),%r14 movq %r15,56(%rdi) movq 56(%rcx),%r15 movq %rcx,%rdi jmp .Lsqrx8x_outer_loop .align 32 .Lsqrx8x_outer_break: movq %r9,72(%rdi) .byte 102,72,15,126,217 movq %r10,80(%rdi) movq %r11,88(%rdi) movq %r12,96(%rdi) movq %r13,104(%rdi) movq %r14,112(%rdi) leaq 48+8(%rsp),%rdi movq (%rsi,%rcx,1),%rdx movq 8(%rdi),%r11 xorq %r10,%r10 movq 0+8(%rsp),%r9 adoxq %r11,%r11 movq 16(%rdi),%r12 movq 24(%rdi),%r13 .align 32 .Lsqrx4x_shift_n_add: mulxq %rdx,%rax,%rbx adoxq %r12,%r12 adcxq %r10,%rax .byte 0x48,0x8b,0x94,0x0e,0x08,0x00,0x00,0x00 .byte 0x4c,0x8b,0x97,0x20,0x00,0x00,0x00 adoxq %r13,%r13 adcxq %r11,%rbx movq 40(%rdi),%r11 movq %rax,0(%rdi) movq %rbx,8(%rdi) mulxq %rdx,%rax,%rbx adoxq %r10,%r10 adcxq %r12,%rax movq 16(%rsi,%rcx,1),%rdx movq 48(%rdi),%r12 adoxq %r11,%r11 adcxq %r13,%rbx movq 56(%rdi),%r13 movq %rax,16(%rdi) movq %rbx,24(%rdi) mulxq %rdx,%rax,%rbx adoxq %r12,%r12 adcxq %r10,%rax movq 24(%rsi,%rcx,1),%rdx leaq 32(%rcx),%rcx movq 64(%rdi),%r10 adoxq %r13,%r13 adcxq %r11,%rbx movq 72(%rdi),%r11 movq %rax,32(%rdi) movq %rbx,40(%rdi) mulxq %rdx,%rax,%rbx adoxq %r10,%r10 adcxq %r12,%rax jrcxz .Lsqrx4x_shift_n_add_break .byte 0x48,0x8b,0x94,0x0e,0x00,0x00,0x00,0x00 adoxq %r11,%r11 adcxq %r13,%rbx movq 80(%rdi),%r12 movq 88(%rdi),%r13 movq %rax,48(%rdi) movq %rbx,56(%rdi) leaq 64(%rdi),%rdi nop jmp .Lsqrx4x_shift_n_add .align 32 .Lsqrx4x_shift_n_add_break: adcxq %r13,%rbx movq %rax,48(%rdi) movq %rbx,56(%rdi) leaq 64(%rdi),%rdi .byte 102,72,15,126,213 __bn_sqrx8x_reduction: xorl %eax,%eax movq 32+8(%rsp),%rbx movq 48+8(%rsp),%rdx leaq -64(%rbp,%r9,1),%rcx movq %rcx,0+8(%rsp) movq %rdi,8+8(%rsp) leaq 48+8(%rsp),%rdi jmp .Lsqrx8x_reduction_loop .align 32 .Lsqrx8x_reduction_loop: movq 8(%rdi),%r9 movq 16(%rdi),%r10 movq 24(%rdi),%r11 movq 32(%rdi),%r12 movq %rdx,%r8 imulq %rbx,%rdx movq 40(%rdi),%r13 movq 48(%rdi),%r14 movq 56(%rdi),%r15 movq %rax,24+8(%rsp) leaq 64(%rdi),%rdi xorq %rsi,%rsi movq $-8,%rcx jmp .Lsqrx8x_reduce .align 32 .Lsqrx8x_reduce: movq %r8,%rbx mulxq 0(%rbp),%rax,%r8 adcxq %rbx,%rax adoxq %r9,%r8 mulxq 8(%rbp),%rbx,%r9 adcxq %rbx,%r8 adoxq %r10,%r9 mulxq 16(%rbp),%rbx,%r10 adcxq %rbx,%r9 adoxq %r11,%r10 mulxq 24(%rbp),%rbx,%r11 adcxq %rbx,%r10 adoxq %r12,%r11 .byte 0xc4,0x62,0xe3,0xf6,0xa5,0x20,0x00,0x00,0x00 movq %rdx,%rax movq %r8,%rdx adcxq %rbx,%r11 adoxq %r13,%r12 mulxq 32+8(%rsp),%rbx,%rdx movq %rax,%rdx movq %rax,64+48+8(%rsp,%rcx,8) mulxq 40(%rbp),%rax,%r13 adcxq %rax,%r12 adoxq %r14,%r13 mulxq 48(%rbp),%rax,%r14 adcxq %rax,%r13 adoxq %r15,%r14 mulxq 56(%rbp),%rax,%r15 movq %rbx,%rdx adcxq %rax,%r14 adoxq %rsi,%r15 adcxq %rsi,%r15 .byte 0x67,0x67,0x67 incq %rcx jnz .Lsqrx8x_reduce movq %rsi,%rax cmpq 0+8(%rsp),%rbp jae .Lsqrx8x_no_tail movq 48+8(%rsp),%rdx addq 0(%rdi),%r8 leaq 64(%rbp),%rbp movq $-8,%rcx adcxq 8(%rdi),%r9 adcxq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 leaq 64(%rdi),%rdi sbbq %rax,%rax xorq %rsi,%rsi movq %rax,16+8(%rsp) jmp .Lsqrx8x_tail .align 32 .Lsqrx8x_tail: movq %r8,%rbx mulxq 0(%rbp),%rax,%r8 adcxq %rax,%rbx adoxq %r9,%r8 mulxq 8(%rbp),%rax,%r9 adcxq %rax,%r8 adoxq %r10,%r9 mulxq 16(%rbp),%rax,%r10 adcxq %rax,%r9 adoxq %r11,%r10 mulxq 24(%rbp),%rax,%r11 adcxq %rax,%r10 adoxq %r12,%r11 .byte 0xc4,0x62,0xfb,0xf6,0xa5,0x20,0x00,0x00,0x00 adcxq %rax,%r11 adoxq %r13,%r12 mulxq 40(%rbp),%rax,%r13 adcxq %rax,%r12 adoxq %r14,%r13 mulxq 48(%rbp),%rax,%r14 adcxq %rax,%r13 adoxq %r15,%r14 mulxq 56(%rbp),%rax,%r15 movq 72+48+8(%rsp,%rcx,8),%rdx adcxq %rax,%r14 adoxq %rsi,%r15 movq %rbx,(%rdi,%rcx,8) movq %r8,%rbx adcxq %rsi,%r15 incq %rcx jnz .Lsqrx8x_tail cmpq 0+8(%rsp),%rbp jae .Lsqrx8x_tail_done subq 16+8(%rsp),%rsi movq 48+8(%rsp),%rdx leaq 64(%rbp),%rbp adcq 0(%rdi),%r8 adcq 8(%rdi),%r9 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 leaq 64(%rdi),%rdi sbbq %rax,%rax subq $8,%rcx xorq %rsi,%rsi movq %rax,16+8(%rsp) jmp .Lsqrx8x_tail .align 32 .Lsqrx8x_tail_done: xorq %rax,%rax addq 24+8(%rsp),%r8 adcq $0,%r9 adcq $0,%r10 adcq $0,%r11 adcq $0,%r12 adcq $0,%r13 adcq $0,%r14 adcq $0,%r15 adcq $0,%rax subq 16+8(%rsp),%rsi .Lsqrx8x_no_tail: adcq 0(%rdi),%r8 .byte 102,72,15,126,217 adcq 8(%rdi),%r9 movq 56(%rbp),%rsi .byte 102,72,15,126,213 adcq 16(%rdi),%r10 adcq 24(%rdi),%r11 adcq 32(%rdi),%r12 adcq 40(%rdi),%r13 adcq 48(%rdi),%r14 adcq 56(%rdi),%r15 adcq $0,%rax movq 32+8(%rsp),%rbx movq 64(%rdi,%rcx,1),%rdx movq %r8,0(%rdi) leaq 64(%rdi),%r8 movq %r9,8(%rdi) movq %r10,16(%rdi) movq %r11,24(%rdi) movq %r12,32(%rdi) movq %r13,40(%rdi) movq %r14,48(%rdi) movq %r15,56(%rdi) leaq 64(%rdi,%rcx,1),%rdi cmpq 8+8(%rsp),%r8 jb .Lsqrx8x_reduction_loop ret .cfi_endproc .size bn_sqrx8x_internal,.-bn_sqrx8x_internal .align 32 .type __bn_postx4x_internal,@function __bn_postx4x_internal: .cfi_startproc movq 0(%rbp),%r12 movq %rcx,%r10 movq %rcx,%r9 negq %rax sarq $3+2,%rcx .byte 102,72,15,126,202 .byte 102,72,15,126,206 decq %r12 movq 8(%rbp),%r13 xorq %r8,%r8 movq 16(%rbp),%r14 movq 24(%rbp),%r15 jmp .Lsqrx4x_sub_entry .align 16 .Lsqrx4x_sub: movq 0(%rbp),%r12 movq 8(%rbp),%r13 movq 16(%rbp),%r14 movq 24(%rbp),%r15 .Lsqrx4x_sub_entry: andnq %rax,%r12,%r12 leaq 32(%rbp),%rbp andnq %rax,%r13,%r13 andnq %rax,%r14,%r14 andnq %rax,%r15,%r15 negq %r8 adcq 0(%rdi),%r12 adcq 8(%rdi),%r13 adcq 16(%rdi),%r14 adcq 24(%rdi),%r15 movq %r12,0(%rdx) leaq 32(%rdi),%rdi movq %r13,8(%rdx) sbbq %r8,%r8 movq %r14,16(%rdx) movq %r15,24(%rdx) leaq 32(%rdx),%rdx incq %rcx jnz .Lsqrx4x_sub negq %r9 ret .cfi_endproc .size __bn_postx4x_internal,.-__bn_postx4x_internal .globl bn_scatter5 .hidden bn_scatter5 .type bn_scatter5,@function .align 16 bn_scatter5: .cfi_startproc _CET_ENDBR cmpl $0,%esi jz .Lscatter_epilogue leaq (%rdx,%rcx,8),%rdx .Lscatter: movq (%rdi),%rax leaq 8(%rdi),%rdi movq %rax,(%rdx) leaq 256(%rdx),%rdx subl $1,%esi jnz .Lscatter .Lscatter_epilogue: ret .cfi_endproc .size bn_scatter5,.-bn_scatter5 .globl bn_gather5 .hidden bn_gather5 .type bn_gather5,@function .align 32 bn_gather5: .cfi_startproc .LSEH_begin_bn_gather5: _CET_ENDBR .byte 0x4c,0x8d,0x14,0x24 .cfi_def_cfa_register %r10 .byte 0x48,0x81,0xec,0x08,0x01,0x00,0x00 leaq .Linc(%rip),%rax andq $-16,%rsp movd %ecx,%xmm5 movdqa 0(%rax),%xmm0 movdqa 16(%rax),%xmm1 leaq 128(%rdx),%r11 leaq 128(%rsp),%rax pshufd $0,%xmm5,%xmm5 movdqa %xmm1,%xmm4 movdqa %xmm1,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,-128(%rax) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,-112(%rax) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,-96(%rax) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,-80(%rax) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,-64(%rax) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,-48(%rax) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,-32(%rax) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,-16(%rax) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,0(%rax) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,16(%rax) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,32(%rax) movdqa %xmm4,%xmm2 paddd %xmm0,%xmm1 pcmpeqd %xmm5,%xmm0 movdqa %xmm3,48(%rax) movdqa %xmm4,%xmm3 paddd %xmm1,%xmm2 pcmpeqd %xmm5,%xmm1 movdqa %xmm0,64(%rax) movdqa %xmm4,%xmm0 paddd %xmm2,%xmm3 pcmpeqd %xmm5,%xmm2 movdqa %xmm1,80(%rax) movdqa %xmm4,%xmm1 paddd %xmm3,%xmm0 pcmpeqd %xmm5,%xmm3 movdqa %xmm2,96(%rax) movdqa %xmm4,%xmm2 movdqa %xmm3,112(%rax) jmp .Lgather .align 32 .Lgather: pxor %xmm4,%xmm4 pxor %xmm5,%xmm5 movdqa -128(%r11),%xmm0 movdqa -112(%r11),%xmm1 movdqa -96(%r11),%xmm2 pand -128(%rax),%xmm0 movdqa -80(%r11),%xmm3 pand -112(%rax),%xmm1 por %xmm0,%xmm4 pand -96(%rax),%xmm2 por %xmm1,%xmm5 pand -80(%rax),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa -64(%r11),%xmm0 movdqa -48(%r11),%xmm1 movdqa -32(%r11),%xmm2 pand -64(%rax),%xmm0 movdqa -16(%r11),%xmm3 pand -48(%rax),%xmm1 por %xmm0,%xmm4 pand -32(%rax),%xmm2 por %xmm1,%xmm5 pand -16(%rax),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 0(%r11),%xmm0 movdqa 16(%r11),%xmm1 movdqa 32(%r11),%xmm2 pand 0(%rax),%xmm0 movdqa 48(%r11),%xmm3 pand 16(%rax),%xmm1 por %xmm0,%xmm4 pand 32(%rax),%xmm2 por %xmm1,%xmm5 pand 48(%rax),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 movdqa 64(%r11),%xmm0 movdqa 80(%r11),%xmm1 movdqa 96(%r11),%xmm2 pand 64(%rax),%xmm0 movdqa 112(%r11),%xmm3 pand 80(%rax),%xmm1 por %xmm0,%xmm4 pand 96(%rax),%xmm2 por %xmm1,%xmm5 pand 112(%rax),%xmm3 por %xmm2,%xmm4 por %xmm3,%xmm5 por %xmm5,%xmm4 leaq 256(%r11),%r11 pshufd $0x4e,%xmm4,%xmm0 por %xmm4,%xmm0 movq %xmm0,(%rdi) leaq 8(%rdi),%rdi subl $1,%esi jnz .Lgather leaq (%r10),%rsp .cfi_def_cfa_register %rsp ret .LSEH_end_bn_gather5: .cfi_endproc .size bn_gather5,.-bn_gather5 .section .rodata .align 64 .Linc: .long 0,0, 1,1 .long 2,2, 2,2 .byte 77,111,110,116,103,111,109,101,114,121,32,77,117,108,116,105,112,108,105,99,97,116,105,111,110,32,119,105,116,104,32,115,99,97,116,116,101,114,47,103,97,116,104,101,114,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 .text #endif

j4yc3-mw/Viren

2,659

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/third_party/fiat/asm/fiat_curve25519_adx_square.S

#include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && \ (defined(__APPLE__) || defined(__ELF__)) .intel_syntax noprefix .text #if defined(__APPLE__) .private_extern _fiat_curve25519_adx_square .global _fiat_curve25519_adx_square _fiat_curve25519_adx_square: #else .type fiat_curve25519_adx_square, @function .hidden fiat_curve25519_adx_square .global fiat_curve25519_adx_square fiat_curve25519_adx_square: #endif .cfi_startproc _CET_ENDBR push rbp .cfi_adjust_cfa_offset 8 .cfi_offset rbp, -16 mov rbp, rsp mov rdx, [ rsi + 0x0 ] mulx r10, rax, [ rsi + 0x8 ] mov rdx, [ rsi + 0x0 ] mulx rcx, r11, [ rsi + 0x10 ] xor rdx, rdx adox r11, r10 mov rdx, [ rsi + 0x0 ] mulx r9, r8, [ rsi + 0x18 ] mov rdx, [ rsi + 0x8 ] mov [ rsp - 0x80 ], rbx .cfi_offset rbx, -16-0x80 mulx rbx, r10, [ rsi + 0x18 ] adox r8, rcx mov [rsp - 0x48 ], rdi adox r10, r9 adcx rax, rax mov rdx, [ rsi + 0x10 ] mulx r9, rcx, [ rsi + 0x18 ] adox rcx, rbx mov rdx, [ rsi + 0x10 ] mulx rdi, rbx, [ rsi + 0x8 ] mov rdx, 0x0 adox r9, rdx mov [ rsp - 0x70 ], r12 .cfi_offset r12, -16-0x70 mov r12, -0x3 inc r12 adox rbx, r8 adox rdi, r10 adcx r11, r11 mov r8, rdx adox r8, rcx mov r10, rdx adox r10, r9 adcx rbx, rbx mov rdx, [ rsi + 0x0 ] mulx r9, rcx, rdx mov rdx, [ rsi + 0x8 ] mov [ rsp - 0x68 ], r13 .cfi_offset r13, -16-0x68 mov [ rsp - 0x60 ], r14 .cfi_offset r14, -16-0x60 mulx r14, r13, rdx seto dl inc r12 adox r9, rax adox r13, r11 adox r14, rbx adcx rdi, rdi mov al, dl mov rdx, [ rsi + 0x10 ] mulx rbx, r11, rdx adox r11, rdi adcx r8, r8 adox rbx, r8 adcx r10, r10 movzx rdx, al mov rdi, 0x0 adcx rdx, rdi movzx r8, al lea r8, [ r8 + rdx ] mov rdx, [ rsi + 0x18 ] mulx rdi, rax, rdx adox rax, r10 mov rdx, 0x26 mov [ rsp - 0x58 ], r15 .cfi_offset r15, -16-0x58 mulx r15, r10, r11 clc adcx r10, rcx mulx r11, rcx, rbx adox r8, rdi mulx rdi, rbx, r8 inc r12 adox rcx, r9 mulx r8, r9, rax adcx r15, rcx adox r9, r13 adcx r11, r9 adox rbx, r14 adox rdi, r12 adcx r8, rbx adc rdi, 0x0 mulx r14, r13, rdi test al, al mov rdi, [ rsp - 0x48 ] adox r13, r10 mov r14, r12 adox r14, r15 mov [ rdi + 0x8 ], r14 mov rax, r12 adox rax, r11 mov r10, r12 adox r10, r8 mov [ rdi + 0x10 ], rax mov rcx, r12 cmovo rcx, rdx adcx r13, rcx mov [ rdi + 0x0 ], r13 mov [ rdi + 0x18 ], r10 mov rbx, [ rsp - 0x80 ] .cfi_restore rbx mov r12, [ rsp - 0x70 ] .cfi_restore r12 mov r13, [ rsp - 0x68 ] .cfi_restore r13 mov r14, [ rsp - 0x60 ] .cfi_restore r14 mov r15, [ rsp - 0x58 ] .cfi_restore r15 pop rbp .cfi_restore rbp .cfi_adjust_cfa_offset -8 ret .cfi_endproc #if defined(__ELF__) .size fiat_curve25519_adx_square, .-fiat_curve25519_adx_square #endif #endif

j4yc3-mw/Viren

3,464

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/third_party/fiat/asm/fiat_curve25519_adx_mul.S

#include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && \ (defined(__APPLE__) || defined(__ELF__)) .intel_syntax noprefix .text #if defined(__APPLE__) .private_extern _fiat_curve25519_adx_mul .global _fiat_curve25519_adx_mul _fiat_curve25519_adx_mul: #else .type fiat_curve25519_adx_mul, @function .hidden fiat_curve25519_adx_mul .global fiat_curve25519_adx_mul fiat_curve25519_adx_mul: #endif .cfi_startproc _CET_ENDBR push rbp .cfi_adjust_cfa_offset 8 .cfi_offset rbp, -16 mov rbp, rsp mov rax, rdx mov rdx, [ rsi + 0x18 ] mulx r11, r10, [ rax + 0x8 ] mov rdx, [ rax + 0x0 ] mov [ rsp - 0x58 ], r15 .cfi_offset r15, -16-0x58 mulx r8, rcx, [ rsi + 0x18 ] mov rdx, [ rsi + 0x8 ] mov [ rsp - 0x80 ], rbx .cfi_offset rbx, -16-0x80 mulx rbx, r9, [ rax + 0x18 ] mov rdx, [ rsi + 0x8 ] mov [ rsp - 0x70 ], r12 .cfi_offset r12, -16-0x70 mulx r15, r12, [ rax + 0x8 ] mov rdx, [ rsi + 0x0 ] mov [ rsp - 0x68 ], r13 .cfi_offset r13, -16-0x68 mov [ rsp - 0x60 ], r14 .cfi_offset r14, -16-0x60 mulx r14, r13, [ rax + 0x0 ] mov rdx, [ rax + 0x10 ] mov [ rsp - 0x18 ], r15 mov [ rsp - 0x50 ], rdi mulx rdi, r15, [ rsi + 0x0 ] mov rdx, [ rax + 0x18 ] mov [ rsp - 0x48 ], r13 mov [ rsp - 0x40 ], r9 mulx r9, r13, [ rsi + 0x0 ] test al, al adox rcx, rdi mov rdx, [ rsi + 0x10 ] mov [ rsp - 0x38 ], r13 mulx r13, rdi, [ rax + 0x8 ] adox r10, r9 mov rdx, 0x0 adox rbx, rdx adcx rdi, rcx adcx r8, r10 mov r9, rdx adcx r9, rbx mov rdx, [ rsi + 0x10 ] mulx r10, rcx, [ rax + 0x0 ] mov rdx, [ rsi + 0x0 ] mov [ rsp - 0x30 ], r15 mulx r15, rbx, [ rax + 0x8 ] mov rdx, -0x2 inc rdx adox rcx, r15 setc r15b clc adcx rcx, r12 adox r10, rdi mov rdx, [ rax + 0x10 ] mov [ rsp - 0x78 ], rcx mulx rcx, rdi, [ rsi + 0x10 ] adox rdi, r8 mov rdx, [ rax + 0x18 ] mov [ rsp - 0x28 ], rcx mulx rcx, r8, [ rsi + 0x10 ] mov rdx, [ rax + 0x10 ] mov [ rsp - 0x20 ], r8 mulx r12, r8, [ rsi + 0x18 ] adox r8, r9 mov rdx, [ rsi + 0x8 ] mov [ rsp - 0x10 ], r12 mulx r12, r9, [ rax + 0x10 ] movzx rdx, r15b lea rdx, [ rdx + rcx ] adcx r9, r10 adcx r13, rdi mov r15, 0x0 mov r10, r15 adox r10, rdx mov rdx, [ rax + 0x18 ] mulx rcx, rdi, [ rsi + 0x18 ] adox rcx, r15 adcx r11, r8 mov rdx, r15 adcx rdx, r10 adcx rcx, r15 mov r8, rdx mov rdx, [ rax + 0x0 ] mulx r15, r10, [ rsi + 0x8 ] test al, al adox r10, r14 adcx rbx, r10 adox r15, [ rsp - 0x78 ] adcx r15, [ rsp - 0x30 ] adox r9, [ rsp - 0x18 ] adcx r9, [ rsp - 0x38 ] adox r13, [ rsp - 0x40 ] adcx r12, r13 adox r11, [ rsp - 0x20 ] adcx r11, [ rsp - 0x28 ] mov rdx, 0x26 mulx rsi, r14, r12 adox rdi, r8 adcx rdi, [ rsp - 0x10 ] mulx r10, r8, r11 mov r13, 0x0 adox rcx, r13 adcx rcx, r13 mulx r11, r12, rdi xor rdi, rdi adox r8, rbx adox r12, r15 mulx rbx, r13, rcx adcx r14, [ rsp - 0x48 ] adox r13, r9 adox rbx, rdi adcx rsi, r8 adcx r10, r12 adcx r11, r13 adc rbx, 0x0 mulx r9, r15, rbx xor r9, r9 adox r15, r14 mov rdi, r9 adox rdi, rsi mov rcx, r9 adox rcx, r10 mov r8, [ rsp - 0x50 ] mov [ r8 + 0x8 ], rdi mov r12, r9 adox r12, r11 mov r14, r9 cmovo r14, rdx mov [ r8 + 0x18 ], r12 adcx r15, r14 mov [ r8 + 0x0 ], r15 mov [ r8 + 0x10 ], rcx mov rbx, [ rsp - 0x80 ] .cfi_restore rbx mov r12, [ rsp - 0x70 ] .cfi_restore r12 mov r13, [ rsp - 0x68 ] .cfi_restore r13 mov r14, [ rsp - 0x60 ] .cfi_restore r14 mov r15, [ rsp - 0x58 ] .cfi_restore r15 pop rbp .cfi_restore rbp .cfi_adjust_cfa_offset -8 ret .cfi_endproc #if defined(__ELF__) .size fiat_curve25519_adx_mul, .-fiat_curve25519_adx_mul #endif #endif

j4yc3-mw/Viren

62,534

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/crypto/poly1305/poly1305_arm_asm.S

#include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__) #pragma GCC diagnostic ignored "-Wlanguage-extension-token" # This implementation was taken from the public domain, neon2 version in # SUPERCOP by D. J. Bernstein and Peter Schwabe. # qhasm: int32 input_0 # qhasm: int32 input_1 # qhasm: int32 input_2 # qhasm: int32 input_3 # qhasm: stack32 input_4 # qhasm: stack32 input_5 # qhasm: stack32 input_6 # qhasm: stack32 input_7 # qhasm: int32 caller_r4 # qhasm: int32 caller_r5 # qhasm: int32 caller_r6 # qhasm: int32 caller_r7 # qhasm: int32 caller_r8 # qhasm: int32 caller_r9 # qhasm: int32 caller_r10 # qhasm: int32 caller_r11 # qhasm: int32 caller_r12 # qhasm: int32 caller_r14 # qhasm: reg128 caller_q4 # qhasm: reg128 caller_q5 # qhasm: reg128 caller_q6 # qhasm: reg128 caller_q7 # qhasm: startcode .fpu neon .text # qhasm: reg128 r0 # qhasm: reg128 r1 # qhasm: reg128 r2 # qhasm: reg128 r3 # qhasm: reg128 r4 # qhasm: reg128 x01 # qhasm: reg128 x23 # qhasm: reg128 x4 # qhasm: reg128 y0 # qhasm: reg128 y12 # qhasm: reg128 y34 # qhasm: reg128 5y12 # qhasm: reg128 5y34 # qhasm: stack128 y0_stack # qhasm: stack128 y12_stack # qhasm: stack128 y34_stack # qhasm: stack128 5y12_stack # qhasm: stack128 5y34_stack # qhasm: reg128 z0 # qhasm: reg128 z12 # qhasm: reg128 z34 # qhasm: reg128 5z12 # qhasm: reg128 5z34 # qhasm: stack128 z0_stack # qhasm: stack128 z12_stack # qhasm: stack128 z34_stack # qhasm: stack128 5z12_stack # qhasm: stack128 5z34_stack # qhasm: stack128 two24 # qhasm: int32 ptr # qhasm: reg128 c01 # qhasm: reg128 c23 # qhasm: reg128 d01 # qhasm: reg128 d23 # qhasm: reg128 t0 # qhasm: reg128 t1 # qhasm: reg128 t2 # qhasm: reg128 t3 # qhasm: reg128 t4 # qhasm: reg128 mask # qhasm: reg128 u0 # qhasm: reg128 u1 # qhasm: reg128 u2 # qhasm: reg128 u3 # qhasm: reg128 u4 # qhasm: reg128 v01 # qhasm: reg128 mid # qhasm: reg128 v23 # qhasm: reg128 v4 # qhasm: int32 len # qhasm: qpushenter crypto_onetimeauth_poly1305_neon2_blocks .align 4 .global openssl_poly1305_neon2_blocks .hidden openssl_poly1305_neon2_blocks .type openssl_poly1305_neon2_blocks STT_FUNC openssl_poly1305_neon2_blocks: vpush {q4,q5,q6,q7} mov r12,sp sub sp,sp,#192 bic sp,sp,#31 # qhasm: len = input_3 # asm 1: mov >len=int32#4,<input_3=int32#4 # asm 2: mov >len=r3,<input_3=r3 mov r3,r3 # qhasm: new y0 # qhasm: y0 = mem64[input_1]y0[1]; input_1 += 8 # asm 1: vld1.8 {<y0=reg128#1%bot},[<input_1=int32#2]! # asm 2: vld1.8 {<y0=d0},[<input_1=r1]! vld1.8 {d0},[r1]! # qhasm: y12 = mem128[input_1]; input_1 += 16 # asm 1: vld1.8 {>y12=reg128#2%bot->y12=reg128#2%top},[<input_1=int32#2]! # asm 2: vld1.8 {>y12=d2->y12=d3},[<input_1=r1]! vld1.8 {d2-d3},[r1]! # qhasm: y34 = mem128[input_1]; input_1 += 16 # asm 1: vld1.8 {>y34=reg128#3%bot->y34=reg128#3%top},[<input_1=int32#2]! # asm 2: vld1.8 {>y34=d4->y34=d5},[<input_1=r1]! vld1.8 {d4-d5},[r1]! # qhasm: input_1 += 8 # asm 1: add >input_1=int32#2,<input_1=int32#2,#8 # asm 2: add >input_1=r1,<input_1=r1,#8 add r1,r1,#8 # qhasm: new z0 # qhasm: z0 = mem64[input_1]z0[1]; input_1 += 8 # asm 1: vld1.8 {<z0=reg128#4%bot},[<input_1=int32#2]! # asm 2: vld1.8 {<z0=d6},[<input_1=r1]! vld1.8 {d6},[r1]! # qhasm: z12 = mem128[input_1]; input_1 += 16 # asm 1: vld1.8 {>z12=reg128#5%bot->z12=reg128#5%top},[<input_1=int32#2]! # asm 2: vld1.8 {>z12=d8->z12=d9},[<input_1=r1]! vld1.8 {d8-d9},[r1]! # qhasm: z34 = mem128[input_1]; input_1 += 16 # asm 1: vld1.8 {>z34=reg128#6%bot->z34=reg128#6%top},[<input_1=int32#2]! # asm 2: vld1.8 {>z34=d10->z34=d11},[<input_1=r1]! vld1.8 {d10-d11},[r1]! # qhasm: 2x mask = 0xffffffff # asm 1: vmov.i64 >mask=reg128#7,#0xffffffff # asm 2: vmov.i64 >mask=q6,#0xffffffff vmov.i64 q6,#0xffffffff # qhasm: 2x u4 = 0xff # asm 1: vmov.i64 >u4=reg128#8,#0xff # asm 2: vmov.i64 >u4=q7,#0xff vmov.i64 q7,#0xff # qhasm: x01 aligned= mem128[input_0];input_0+=16 # asm 1: vld1.8 {>x01=reg128#9%bot->x01=reg128#9%top},[<input_0=int32#1,: 128]! # asm 2: vld1.8 {>x01=d16->x01=d17},[<input_0=r0,: 128]! vld1.8 {d16-d17},[r0,: 128]! # qhasm: x23 aligned= mem128[input_0];input_0+=16 # asm 1: vld1.8 {>x23=reg128#10%bot->x23=reg128#10%top},[<input_0=int32#1,: 128]! # asm 2: vld1.8 {>x23=d18->x23=d19},[<input_0=r0,: 128]! vld1.8 {d18-d19},[r0,: 128]! # qhasm: x4 aligned= mem64[input_0]x4[1] # asm 1: vld1.8 {<x4=reg128#11%bot},[<input_0=int32#1,: 64] # asm 2: vld1.8 {<x4=d20},[<input_0=r0,: 64] vld1.8 {d20},[r0,: 64] # qhasm: input_0 -= 32 # asm 1: sub >input_0=int32#1,<input_0=int32#1,#32 # asm 2: sub >input_0=r0,<input_0=r0,#32 sub r0,r0,#32 # qhasm: 2x mask unsigned>>=6 # asm 1: vshr.u64 >mask=reg128#7,<mask=reg128#7,#6 # asm 2: vshr.u64 >mask=q6,<mask=q6,#6 vshr.u64 q6,q6,#6 # qhasm: 2x u4 unsigned>>= 7 # asm 1: vshr.u64 >u4=reg128#8,<u4=reg128#8,#7 # asm 2: vshr.u64 >u4=q7,<u4=q7,#7 vshr.u64 q7,q7,#7 # qhasm: 4x 5y12 = y12 << 2 # asm 1: vshl.i32 >5y12=reg128#12,<y12=reg128#2,#2 # asm 2: vshl.i32 >5y12=q11,<y12=q1,#2 vshl.i32 q11,q1,#2 # qhasm: 4x 5y34 = y34 << 2 # asm 1: vshl.i32 >5y34=reg128#13,<y34=reg128#3,#2 # asm 2: vshl.i32 >5y34=q12,<y34=q2,#2 vshl.i32 q12,q2,#2 # qhasm: 4x 5y12 += y12 # asm 1: vadd.i32 >5y12=reg128#12,<5y12=reg128#12,<y12=reg128#2 # asm 2: vadd.i32 >5y12=q11,<5y12=q11,<y12=q1 vadd.i32 q11,q11,q1 # qhasm: 4x 5y34 += y34 # asm 1: vadd.i32 >5y34=reg128#13,<5y34=reg128#13,<y34=reg128#3 # asm 2: vadd.i32 >5y34=q12,<5y34=q12,<y34=q2 vadd.i32 q12,q12,q2 # qhasm: 2x u4 <<= 24 # asm 1: vshl.i64 >u4=reg128#8,<u4=reg128#8,#24 # asm 2: vshl.i64 >u4=q7,<u4=q7,#24 vshl.i64 q7,q7,#24 # qhasm: 4x 5z12 = z12 << 2 # asm 1: vshl.i32 >5z12=reg128#14,<z12=reg128#5,#2 # asm 2: vshl.i32 >5z12=q13,<z12=q4,#2 vshl.i32 q13,q4,#2 # qhasm: 4x 5z34 = z34 << 2 # asm 1: vshl.i32 >5z34=reg128#15,<z34=reg128#6,#2 # asm 2: vshl.i32 >5z34=q14,<z34=q5,#2 vshl.i32 q14,q5,#2 # qhasm: 4x 5z12 += z12 # asm 1: vadd.i32 >5z12=reg128#14,<5z12=reg128#14,<z12=reg128#5 # asm 2: vadd.i32 >5z12=q13,<5z12=q13,<z12=q4 vadd.i32 q13,q13,q4 # qhasm: 4x 5z34 += z34 # asm 1: vadd.i32 >5z34=reg128#15,<5z34=reg128#15,<z34=reg128#6 # asm 2: vadd.i32 >5z34=q14,<5z34=q14,<z34=q5 vadd.i32 q14,q14,q5 # qhasm: new two24 # qhasm: new y0_stack # qhasm: new y12_stack # qhasm: new y34_stack # qhasm: new 5y12_stack # qhasm: new 5y34_stack # qhasm: new z0_stack # qhasm: new z12_stack # qhasm: new z34_stack # qhasm: new 5z12_stack # qhasm: new 5z34_stack # qhasm: ptr = &two24 # asm 1: lea >ptr=int32#2,<two24=stack128#1 # asm 2: lea >ptr=r1,<two24=[sp,#0] add r1,sp,#0 # qhasm: mem128[ptr] aligned= u4 # asm 1: vst1.8 {<u4=reg128#8%bot-<u4=reg128#8%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<u4=d14-<u4=d15},[<ptr=r1,: 128] vst1.8 {d14-d15},[r1,: 128] # qhasm: r4 = u4 # asm 1: vmov >r4=reg128#16,<u4=reg128#8 # asm 2: vmov >r4=q15,<u4=q7 vmov q15,q7 # qhasm: r0 = u4 # asm 1: vmov >r0=reg128#8,<u4=reg128#8 # asm 2: vmov >r0=q7,<u4=q7 vmov q7,q7 # qhasm: ptr = &y0_stack # asm 1: lea >ptr=int32#2,<y0_stack=stack128#2 # asm 2: lea >ptr=r1,<y0_stack=[sp,#16] add r1,sp,#16 # qhasm: mem128[ptr] aligned= y0 # asm 1: vst1.8 {<y0=reg128#1%bot-<y0=reg128#1%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<y0=d0-<y0=d1},[<ptr=r1,: 128] vst1.8 {d0-d1},[r1,: 128] # qhasm: ptr = &y12_stack # asm 1: lea >ptr=int32#2,<y12_stack=stack128#3 # asm 2: lea >ptr=r1,<y12_stack=[sp,#32] add r1,sp,#32 # qhasm: mem128[ptr] aligned= y12 # asm 1: vst1.8 {<y12=reg128#2%bot-<y12=reg128#2%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<y12=d2-<y12=d3},[<ptr=r1,: 128] vst1.8 {d2-d3},[r1,: 128] # qhasm: ptr = &y34_stack # asm 1: lea >ptr=int32#2,<y34_stack=stack128#4 # asm 2: lea >ptr=r1,<y34_stack=[sp,#48] add r1,sp,#48 # qhasm: mem128[ptr] aligned= y34 # asm 1: vst1.8 {<y34=reg128#3%bot-<y34=reg128#3%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<y34=d4-<y34=d5},[<ptr=r1,: 128] vst1.8 {d4-d5},[r1,: 128] # qhasm: ptr = &z0_stack # asm 1: lea >ptr=int32#2,<z0_stack=stack128#7 # asm 2: lea >ptr=r1,<z0_stack=[sp,#96] add r1,sp,#96 # qhasm: mem128[ptr] aligned= z0 # asm 1: vst1.8 {<z0=reg128#4%bot-<z0=reg128#4%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<z0=d6-<z0=d7},[<ptr=r1,: 128] vst1.8 {d6-d7},[r1,: 128] # qhasm: ptr = &z12_stack # asm 1: lea >ptr=int32#2,<z12_stack=stack128#8 # asm 2: lea >ptr=r1,<z12_stack=[sp,#112] add r1,sp,#112 # qhasm: mem128[ptr] aligned= z12 # asm 1: vst1.8 {<z12=reg128#5%bot-<z12=reg128#5%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<z12=d8-<z12=d9},[<ptr=r1,: 128] vst1.8 {d8-d9},[r1,: 128] # qhasm: ptr = &z34_stack # asm 1: lea >ptr=int32#2,<z34_stack=stack128#9 # asm 2: lea >ptr=r1,<z34_stack=[sp,#128] add r1,sp,#128 # qhasm: mem128[ptr] aligned= z34 # asm 1: vst1.8 {<z34=reg128#6%bot-<z34=reg128#6%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<z34=d10-<z34=d11},[<ptr=r1,: 128] vst1.8 {d10-d11},[r1,: 128] # qhasm: ptr = &5y12_stack # asm 1: lea >ptr=int32#2,<5y12_stack=stack128#5 # asm 2: lea >ptr=r1,<5y12_stack=[sp,#64] add r1,sp,#64 # qhasm: mem128[ptr] aligned= 5y12 # asm 1: vst1.8 {<5y12=reg128#12%bot-<5y12=reg128#12%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<5y12=d22-<5y12=d23},[<ptr=r1,: 128] vst1.8 {d22-d23},[r1,: 128] # qhasm: ptr = &5y34_stack # asm 1: lea >ptr=int32#2,<5y34_stack=stack128#6 # asm 2: lea >ptr=r1,<5y34_stack=[sp,#80] add r1,sp,#80 # qhasm: mem128[ptr] aligned= 5y34 # asm 1: vst1.8 {<5y34=reg128#13%bot-<5y34=reg128#13%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<5y34=d24-<5y34=d25},[<ptr=r1,: 128] vst1.8 {d24-d25},[r1,: 128] # qhasm: ptr = &5z12_stack # asm 1: lea >ptr=int32#2,<5z12_stack=stack128#10 # asm 2: lea >ptr=r1,<5z12_stack=[sp,#144] add r1,sp,#144 # qhasm: mem128[ptr] aligned= 5z12 # asm 1: vst1.8 {<5z12=reg128#14%bot-<5z12=reg128#14%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<5z12=d26-<5z12=d27},[<ptr=r1,: 128] vst1.8 {d26-d27},[r1,: 128] # qhasm: ptr = &5z34_stack # asm 1: lea >ptr=int32#2,<5z34_stack=stack128#11 # asm 2: lea >ptr=r1,<5z34_stack=[sp,#160] add r1,sp,#160 # qhasm: mem128[ptr] aligned= 5z34 # asm 1: vst1.8 {<5z34=reg128#15%bot-<5z34=reg128#15%top},[<ptr=int32#2,: 128] # asm 2: vst1.8 {<5z34=d28-<5z34=d29},[<ptr=r1,: 128] vst1.8 {d28-d29},[r1,: 128] # qhasm: unsigned>? len - 64 # asm 1: cmp <len=int32#4,#64 # asm 2: cmp <len=r3,#64 cmp r3,#64 # qhasm: goto below64bytes if !unsigned> bls ._below64bytes # qhasm: input_2 += 32 # asm 1: add >input_2=int32#2,<input_2=int32#3,#32 # asm 2: add >input_2=r1,<input_2=r2,#32 add r1,r2,#32 # qhasm: mainloop2: ._mainloop2: # qhasm: c01 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>c01=reg128#1%bot->c01=reg128#1%top},[<input_2=int32#2]! # asm 2: vld1.8 {>c01=d0->c01=d1},[<input_2=r1]! vld1.8 {d0-d1},[r1]! # qhasm: c23 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>c23=reg128#2%bot->c23=reg128#2%top},[<input_2=int32#2]! # asm 2: vld1.8 {>c23=d2->c23=d3},[<input_2=r1]! vld1.8 {d2-d3},[r1]! # qhasm: r4[0,1] += x01[0] unsigned* z34[2]; r4[2,3] += x01[1] unsigned* z34[3] # asm 1: vmlal.u32 <r4=reg128#16,<x01=reg128#9%bot,<z34=reg128#6%top # asm 2: vmlal.u32 <r4=q15,<x01=d16,<z34=d11 vmlal.u32 q15,d16,d11 # qhasm: ptr = &z12_stack # asm 1: lea >ptr=int32#3,<z12_stack=stack128#8 # asm 2: lea >ptr=r2,<z12_stack=[sp,#112] add r2,sp,#112 # qhasm: z12 aligned= mem128[ptr] # asm 1: vld1.8 {>z12=reg128#3%bot->z12=reg128#3%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>z12=d4->z12=d5},[<ptr=r2,: 128] vld1.8 {d4-d5},[r2,: 128] # qhasm: r4[0,1] += x01[2] unsigned* z34[0]; r4[2,3] += x01[3] unsigned* z34[1] # asm 1: vmlal.u32 <r4=reg128#16,<x01=reg128#9%top,<z34=reg128#6%bot # asm 2: vmlal.u32 <r4=q15,<x01=d17,<z34=d10 vmlal.u32 q15,d17,d10 # qhasm: ptr = &z0_stack # asm 1: lea >ptr=int32#3,<z0_stack=stack128#7 # asm 2: lea >ptr=r2,<z0_stack=[sp,#96] add r2,sp,#96 # qhasm: z0 aligned= mem128[ptr] # asm 1: vld1.8 {>z0=reg128#4%bot->z0=reg128#4%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>z0=d6->z0=d7},[<ptr=r2,: 128] vld1.8 {d6-d7},[r2,: 128] # qhasm: r4[0,1] += x23[0] unsigned* z12[2]; r4[2,3] += x23[1] unsigned* z12[3] # asm 1: vmlal.u32 <r4=reg128#16,<x23=reg128#10%bot,<z12=reg128#3%top # asm 2: vmlal.u32 <r4=q15,<x23=d18,<z12=d5 vmlal.u32 q15,d18,d5 # qhasm: c01 c23 = c01[0]c01[1]c01[2]c23[2]c23[0]c23[1]c01[3]c23[3] # asm 1: vtrn.32 <c01=reg128#1%top,<c23=reg128#2%top # asm 2: vtrn.32 <c01=d1,<c23=d3 vtrn.32 d1,d3 # qhasm: r4[0,1] += x23[2] unsigned* z12[0]; r4[2,3] += x23[3] unsigned* z12[1] # asm 1: vmlal.u32 <r4=reg128#16,<x23=reg128#10%top,<z12=reg128#3%bot # asm 2: vmlal.u32 <r4=q15,<x23=d19,<z12=d4 vmlal.u32 q15,d19,d4 # qhasm: r4[0,1] += x4[0] unsigned* z0[0]; r4[2,3] += x4[1] unsigned* z0[1] # asm 1: vmlal.u32 <r4=reg128#16,<x4=reg128#11%bot,<z0=reg128#4%bot # asm 2: vmlal.u32 <r4=q15,<x4=d20,<z0=d6 vmlal.u32 q15,d20,d6 # qhasm: r3[0,1] = c23[2]<<18; r3[2,3] = c23[3]<<18 # asm 1: vshll.u32 >r3=reg128#5,<c23=reg128#2%top,#18 # asm 2: vshll.u32 >r3=q4,<c23=d3,#18 vshll.u32 q4,d3,#18 # qhasm: c01 c23 = c01[0]c23[0]c01[2]c01[3]c01[1]c23[1]c23[2]c23[3] # asm 1: vtrn.32 <c01=reg128#1%bot,<c23=reg128#2%bot # asm 2: vtrn.32 <c01=d0,<c23=d2 vtrn.32 d0,d2 # qhasm: r3[0,1] += x01[0] unsigned* z34[0]; r3[2,3] += x01[1] unsigned* z34[1] # asm 1: vmlal.u32 <r3=reg128#5,<x01=reg128#9%bot,<z34=reg128#6%bot # asm 2: vmlal.u32 <r3=q4,<x01=d16,<z34=d10 vmlal.u32 q4,d16,d10 # qhasm: r3[0,1] += x01[2] unsigned* z12[2]; r3[2,3] += x01[3] unsigned* z12[3] # asm 1: vmlal.u32 <r3=reg128#5,<x01=reg128#9%top,<z12=reg128#3%top # asm 2: vmlal.u32 <r3=q4,<x01=d17,<z12=d5 vmlal.u32 q4,d17,d5 # qhasm: r0 = r0[1]c01[0]r0[2,3] # asm 1: vext.32 <r0=reg128#8%bot,<r0=reg128#8%bot,<c01=reg128#1%bot,#1 # asm 2: vext.32 <r0=d14,<r0=d14,<c01=d0,#1 vext.32 d14,d14,d0,#1 # qhasm: r3[0,1] += x23[0] unsigned* z12[0]; r3[2,3] += x23[1] unsigned* z12[1] # asm 1: vmlal.u32 <r3=reg128#5,<x23=reg128#10%bot,<z12=reg128#3%bot # asm 2: vmlal.u32 <r3=q4,<x23=d18,<z12=d4 vmlal.u32 q4,d18,d4 # qhasm: input_2 -= 64 # asm 1: sub >input_2=int32#2,<input_2=int32#2,#64 # asm 2: sub >input_2=r1,<input_2=r1,#64 sub r1,r1,#64 # qhasm: r3[0,1] += x23[2] unsigned* z0[0]; r3[2,3] += x23[3] unsigned* z0[1] # asm 1: vmlal.u32 <r3=reg128#5,<x23=reg128#10%top,<z0=reg128#4%bot # asm 2: vmlal.u32 <r3=q4,<x23=d19,<z0=d6 vmlal.u32 q4,d19,d6 # qhasm: ptr = &5z34_stack # asm 1: lea >ptr=int32#3,<5z34_stack=stack128#11 # asm 2: lea >ptr=r2,<5z34_stack=[sp,#160] add r2,sp,#160 # qhasm: 5z34 aligned= mem128[ptr] # asm 1: vld1.8 {>5z34=reg128#6%bot->5z34=reg128#6%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>5z34=d10->5z34=d11},[<ptr=r2,: 128] vld1.8 {d10-d11},[r2,: 128] # qhasm: r3[0,1] += x4[0] unsigned* 5z34[2]; r3[2,3] += x4[1] unsigned* 5z34[3] # asm 1: vmlal.u32 <r3=reg128#5,<x4=reg128#11%bot,<5z34=reg128#6%top # asm 2: vmlal.u32 <r3=q4,<x4=d20,<5z34=d11 vmlal.u32 q4,d20,d11 # qhasm: r0 = r0[1]r0[0]r0[3]r0[2] # asm 1: vrev64.i32 >r0=reg128#8,<r0=reg128#8 # asm 2: vrev64.i32 >r0=q7,<r0=q7 vrev64.i32 q7,q7 # qhasm: r2[0,1] = c01[2]<<12; r2[2,3] = c01[3]<<12 # asm 1: vshll.u32 >r2=reg128#14,<c01=reg128#1%top,#12 # asm 2: vshll.u32 >r2=q13,<c01=d1,#12 vshll.u32 q13,d1,#12 # qhasm: d01 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>d01=reg128#12%bot->d01=reg128#12%top},[<input_2=int32#2]! # asm 2: vld1.8 {>d01=d22->d01=d23},[<input_2=r1]! vld1.8 {d22-d23},[r1]! # qhasm: r2[0,1] += x01[0] unsigned* z12[2]; r2[2,3] += x01[1] unsigned* z12[3] # asm 1: vmlal.u32 <r2=reg128#14,<x01=reg128#9%bot,<z12=reg128#3%top # asm 2: vmlal.u32 <r2=q13,<x01=d16,<z12=d5 vmlal.u32 q13,d16,d5 # qhasm: r2[0,1] += x01[2] unsigned* z12[0]; r2[2,3] += x01[3] unsigned* z12[1] # asm 1: vmlal.u32 <r2=reg128#14,<x01=reg128#9%top,<z12=reg128#3%bot # asm 2: vmlal.u32 <r2=q13,<x01=d17,<z12=d4 vmlal.u32 q13,d17,d4 # qhasm: r2[0,1] += x23[0] unsigned* z0[0]; r2[2,3] += x23[1] unsigned* z0[1] # asm 1: vmlal.u32 <r2=reg128#14,<x23=reg128#10%bot,<z0=reg128#4%bot # asm 2: vmlal.u32 <r2=q13,<x23=d18,<z0=d6 vmlal.u32 q13,d18,d6 # qhasm: r2[0,1] += x23[2] unsigned* 5z34[2]; r2[2,3] += x23[3] unsigned* 5z34[3] # asm 1: vmlal.u32 <r2=reg128#14,<x23=reg128#10%top,<5z34=reg128#6%top # asm 2: vmlal.u32 <r2=q13,<x23=d19,<5z34=d11 vmlal.u32 q13,d19,d11 # qhasm: r2[0,1] += x4[0] unsigned* 5z34[0]; r2[2,3] += x4[1] unsigned* 5z34[1] # asm 1: vmlal.u32 <r2=reg128#14,<x4=reg128#11%bot,<5z34=reg128#6%bot # asm 2: vmlal.u32 <r2=q13,<x4=d20,<5z34=d10 vmlal.u32 q13,d20,d10 # qhasm: r0 = r0[0,1]c01[1]r0[2] # asm 1: vext.32 <r0=reg128#8%top,<c01=reg128#1%bot,<r0=reg128#8%top,#1 # asm 2: vext.32 <r0=d15,<c01=d0,<r0=d15,#1 vext.32 d15,d0,d15,#1 # qhasm: r1[0,1] = c23[0]<<6; r1[2,3] = c23[1]<<6 # asm 1: vshll.u32 >r1=reg128#15,<c23=reg128#2%bot,#6 # asm 2: vshll.u32 >r1=q14,<c23=d2,#6 vshll.u32 q14,d2,#6 # qhasm: r1[0,1] += x01[0] unsigned* z12[0]; r1[2,3] += x01[1] unsigned* z12[1] # asm 1: vmlal.u32 <r1=reg128#15,<x01=reg128#9%bot,<z12=reg128#3%bot # asm 2: vmlal.u32 <r1=q14,<x01=d16,<z12=d4 vmlal.u32 q14,d16,d4 # qhasm: r1[0,1] += x01[2] unsigned* z0[0]; r1[2,3] += x01[3] unsigned* z0[1] # asm 1: vmlal.u32 <r1=reg128#15,<x01=reg128#9%top,<z0=reg128#4%bot # asm 2: vmlal.u32 <r1=q14,<x01=d17,<z0=d6 vmlal.u32 q14,d17,d6 # qhasm: r1[0,1] += x23[0] unsigned* 5z34[2]; r1[2,3] += x23[1] unsigned* 5z34[3] # asm 1: vmlal.u32 <r1=reg128#15,<x23=reg128#10%bot,<5z34=reg128#6%top # asm 2: vmlal.u32 <r1=q14,<x23=d18,<5z34=d11 vmlal.u32 q14,d18,d11 # qhasm: r1[0,1] += x23[2] unsigned* 5z34[0]; r1[2,3] += x23[3] unsigned* 5z34[1] # asm 1: vmlal.u32 <r1=reg128#15,<x23=reg128#10%top,<5z34=reg128#6%bot # asm 2: vmlal.u32 <r1=q14,<x23=d19,<5z34=d10 vmlal.u32 q14,d19,d10 # qhasm: ptr = &5z12_stack # asm 1: lea >ptr=int32#3,<5z12_stack=stack128#10 # asm 2: lea >ptr=r2,<5z12_stack=[sp,#144] add r2,sp,#144 # qhasm: 5z12 aligned= mem128[ptr] # asm 1: vld1.8 {>5z12=reg128#1%bot->5z12=reg128#1%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>5z12=d0->5z12=d1},[<ptr=r2,: 128] vld1.8 {d0-d1},[r2,: 128] # qhasm: r1[0,1] += x4[0] unsigned* 5z12[2]; r1[2,3] += x4[1] unsigned* 5z12[3] # asm 1: vmlal.u32 <r1=reg128#15,<x4=reg128#11%bot,<5z12=reg128#1%top # asm 2: vmlal.u32 <r1=q14,<x4=d20,<5z12=d1 vmlal.u32 q14,d20,d1 # qhasm: d23 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>d23=reg128#2%bot->d23=reg128#2%top},[<input_2=int32#2]! # asm 2: vld1.8 {>d23=d2->d23=d3},[<input_2=r1]! vld1.8 {d2-d3},[r1]! # qhasm: input_2 += 32 # asm 1: add >input_2=int32#2,<input_2=int32#2,#32 # asm 2: add >input_2=r1,<input_2=r1,#32 add r1,r1,#32 # qhasm: r0[0,1] += x4[0] unsigned* 5z12[0]; r0[2,3] += x4[1] unsigned* 5z12[1] # asm 1: vmlal.u32 <r0=reg128#8,<x4=reg128#11%bot,<5z12=reg128#1%bot # asm 2: vmlal.u32 <r0=q7,<x4=d20,<5z12=d0 vmlal.u32 q7,d20,d0 # qhasm: r0[0,1] += x23[0] unsigned* 5z34[0]; r0[2,3] += x23[1] unsigned* 5z34[1] # asm 1: vmlal.u32 <r0=reg128#8,<x23=reg128#10%bot,<5z34=reg128#6%bot # asm 2: vmlal.u32 <r0=q7,<x23=d18,<5z34=d10 vmlal.u32 q7,d18,d10 # qhasm: d01 d23 = d01[0] d23[0] d01[1] d23[1] # asm 1: vswp <d23=reg128#2%bot,<d01=reg128#12%top # asm 2: vswp <d23=d2,<d01=d23 vswp d2,d23 # qhasm: r0[0,1] += x23[2] unsigned* 5z12[2]; r0[2,3] += x23[3] unsigned* 5z12[3] # asm 1: vmlal.u32 <r0=reg128#8,<x23=reg128#10%top,<5z12=reg128#1%top # asm 2: vmlal.u32 <r0=q7,<x23=d19,<5z12=d1 vmlal.u32 q7,d19,d1 # qhasm: r0[0,1] += x01[0] unsigned* z0[0]; r0[2,3] += x01[1] unsigned* z0[1] # asm 1: vmlal.u32 <r0=reg128#8,<x01=reg128#9%bot,<z0=reg128#4%bot # asm 2: vmlal.u32 <r0=q7,<x01=d16,<z0=d6 vmlal.u32 q7,d16,d6 # qhasm: new mid # qhasm: 2x v4 = d23 unsigned>> 40 # asm 1: vshr.u64 >v4=reg128#4,<d23=reg128#2,#40 # asm 2: vshr.u64 >v4=q3,<d23=q1,#40 vshr.u64 q3,q1,#40 # qhasm: mid = d01[1]d23[0] mid[2,3] # asm 1: vext.32 <mid=reg128#1%bot,<d01=reg128#12%bot,<d23=reg128#2%bot,#1 # asm 2: vext.32 <mid=d0,<d01=d22,<d23=d2,#1 vext.32 d0,d22,d2,#1 # qhasm: new v23 # qhasm: v23[2] = d23[0,1] unsigned>> 14; v23[3] = d23[2,3] unsigned>> 14 # asm 1: vshrn.u64 <v23=reg128#10%top,<d23=reg128#2,#14 # asm 2: vshrn.u64 <v23=d19,<d23=q1,#14 vshrn.u64 d19,q1,#14 # qhasm: mid = mid[0,1] d01[3]d23[2] # asm 1: vext.32 <mid=reg128#1%top,<d01=reg128#12%top,<d23=reg128#2%top,#1 # asm 2: vext.32 <mid=d1,<d01=d23,<d23=d3,#1 vext.32 d1,d23,d3,#1 # qhasm: new v01 # qhasm: v01[2] = d01[0,1] unsigned>> 26; v01[3] = d01[2,3] unsigned>> 26 # asm 1: vshrn.u64 <v01=reg128#11%top,<d01=reg128#12,#26 # asm 2: vshrn.u64 <v01=d21,<d01=q11,#26 vshrn.u64 d21,q11,#26 # qhasm: v01 = d01[1]d01[0] v01[2,3] # asm 1: vext.32 <v01=reg128#11%bot,<d01=reg128#12%bot,<d01=reg128#12%bot,#1 # asm 2: vext.32 <v01=d20,<d01=d22,<d01=d22,#1 vext.32 d20,d22,d22,#1 # qhasm: r0[0,1] += x01[2] unsigned* 5z34[2]; r0[2,3] += x01[3] unsigned* 5z34[3] # asm 1: vmlal.u32 <r0=reg128#8,<x01=reg128#9%top,<5z34=reg128#6%top # asm 2: vmlal.u32 <r0=q7,<x01=d17,<5z34=d11 vmlal.u32 q7,d17,d11 # qhasm: v01 = v01[1]d01[2] v01[2,3] # asm 1: vext.32 <v01=reg128#11%bot,<v01=reg128#11%bot,<d01=reg128#12%top,#1 # asm 2: vext.32 <v01=d20,<v01=d20,<d01=d23,#1 vext.32 d20,d20,d23,#1 # qhasm: v23[0] = mid[0,1] unsigned>> 20; v23[1] = mid[2,3] unsigned>> 20 # asm 1: vshrn.u64 <v23=reg128#10%bot,<mid=reg128#1,#20 # asm 2: vshrn.u64 <v23=d18,<mid=q0,#20 vshrn.u64 d18,q0,#20 # qhasm: v4 = v4[0]v4[2]v4[1]v4[3] # asm 1: vtrn.32 <v4=reg128#4%bot,<v4=reg128#4%top # asm 2: vtrn.32 <v4=d6,<v4=d7 vtrn.32 d6,d7 # qhasm: 4x v01 &= 0x03ffffff # asm 1: vand.i32 <v01=reg128#11,#0x03ffffff # asm 2: vand.i32 <v01=q10,#0x03ffffff vand.i32 q10,#0x03ffffff # qhasm: ptr = &y34_stack # asm 1: lea >ptr=int32#3,<y34_stack=stack128#4 # asm 2: lea >ptr=r2,<y34_stack=[sp,#48] add r2,sp,#48 # qhasm: y34 aligned= mem128[ptr] # asm 1: vld1.8 {>y34=reg128#3%bot->y34=reg128#3%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>y34=d4->y34=d5},[<ptr=r2,: 128] vld1.8 {d4-d5},[r2,: 128] # qhasm: 4x v23 &= 0x03ffffff # asm 1: vand.i32 <v23=reg128#10,#0x03ffffff # asm 2: vand.i32 <v23=q9,#0x03ffffff vand.i32 q9,#0x03ffffff # qhasm: ptr = &y12_stack # asm 1: lea >ptr=int32#3,<y12_stack=stack128#3 # asm 2: lea >ptr=r2,<y12_stack=[sp,#32] add r2,sp,#32 # qhasm: y12 aligned= mem128[ptr] # asm 1: vld1.8 {>y12=reg128#2%bot->y12=reg128#2%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>y12=d2->y12=d3},[<ptr=r2,: 128] vld1.8 {d2-d3},[r2,: 128] # qhasm: 4x v4 |= 0x01000000 # asm 1: vorr.i32 <v4=reg128#4,#0x01000000 # asm 2: vorr.i32 <v4=q3,#0x01000000 vorr.i32 q3,#0x01000000 # qhasm: ptr = &y0_stack # asm 1: lea >ptr=int32#3,<y0_stack=stack128#2 # asm 2: lea >ptr=r2,<y0_stack=[sp,#16] add r2,sp,#16 # qhasm: y0 aligned= mem128[ptr] # asm 1: vld1.8 {>y0=reg128#1%bot->y0=reg128#1%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>y0=d0->y0=d1},[<ptr=r2,: 128] vld1.8 {d0-d1},[r2,: 128] # qhasm: r4[0,1] += v01[0] unsigned* y34[2]; r4[2,3] += v01[1] unsigned* y34[3] # asm 1: vmlal.u32 <r4=reg128#16,<v01=reg128#11%bot,<y34=reg128#3%top # asm 2: vmlal.u32 <r4=q15,<v01=d20,<y34=d5 vmlal.u32 q15,d20,d5 # qhasm: r4[0,1] += v01[2] unsigned* y34[0]; r4[2,3] += v01[3] unsigned* y34[1] # asm 1: vmlal.u32 <r4=reg128#16,<v01=reg128#11%top,<y34=reg128#3%bot # asm 2: vmlal.u32 <r4=q15,<v01=d21,<y34=d4 vmlal.u32 q15,d21,d4 # qhasm: r4[0,1] += v23[0] unsigned* y12[2]; r4[2,3] += v23[1] unsigned* y12[3] # asm 1: vmlal.u32 <r4=reg128#16,<v23=reg128#10%bot,<y12=reg128#2%top # asm 2: vmlal.u32 <r4=q15,<v23=d18,<y12=d3 vmlal.u32 q15,d18,d3 # qhasm: r4[0,1] += v23[2] unsigned* y12[0]; r4[2,3] += v23[3] unsigned* y12[1] # asm 1: vmlal.u32 <r4=reg128#16,<v23=reg128#10%top,<y12=reg128#2%bot # asm 2: vmlal.u32 <r4=q15,<v23=d19,<y12=d2 vmlal.u32 q15,d19,d2 # qhasm: r4[0,1] += v4[0] unsigned* y0[0]; r4[2,3] += v4[1] unsigned* y0[1] # asm 1: vmlal.u32 <r4=reg128#16,<v4=reg128#4%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r4=q15,<v4=d6,<y0=d0 vmlal.u32 q15,d6,d0 # qhasm: ptr = &5y34_stack # asm 1: lea >ptr=int32#3,<5y34_stack=stack128#6 # asm 2: lea >ptr=r2,<5y34_stack=[sp,#80] add r2,sp,#80 # qhasm: 5y34 aligned= mem128[ptr] # asm 1: vld1.8 {>5y34=reg128#13%bot->5y34=reg128#13%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>5y34=d24->5y34=d25},[<ptr=r2,: 128] vld1.8 {d24-d25},[r2,: 128] # qhasm: r3[0,1] += v01[0] unsigned* y34[0]; r3[2,3] += v01[1] unsigned* y34[1] # asm 1: vmlal.u32 <r3=reg128#5,<v01=reg128#11%bot,<y34=reg128#3%bot # asm 2: vmlal.u32 <r3=q4,<v01=d20,<y34=d4 vmlal.u32 q4,d20,d4 # qhasm: r3[0,1] += v01[2] unsigned* y12[2]; r3[2,3] += v01[3] unsigned* y12[3] # asm 1: vmlal.u32 <r3=reg128#5,<v01=reg128#11%top,<y12=reg128#2%top # asm 2: vmlal.u32 <r3=q4,<v01=d21,<y12=d3 vmlal.u32 q4,d21,d3 # qhasm: r3[0,1] += v23[0] unsigned* y12[0]; r3[2,3] += v23[1] unsigned* y12[1] # asm 1: vmlal.u32 <r3=reg128#5,<v23=reg128#10%bot,<y12=reg128#2%bot # asm 2: vmlal.u32 <r3=q4,<v23=d18,<y12=d2 vmlal.u32 q4,d18,d2 # qhasm: r3[0,1] += v23[2] unsigned* y0[0]; r3[2,3] += v23[3] unsigned* y0[1] # asm 1: vmlal.u32 <r3=reg128#5,<v23=reg128#10%top,<y0=reg128#1%bot # asm 2: vmlal.u32 <r3=q4,<v23=d19,<y0=d0 vmlal.u32 q4,d19,d0 # qhasm: r3[0,1] += v4[0] unsigned* 5y34[2]; r3[2,3] += v4[1] unsigned* 5y34[3] # asm 1: vmlal.u32 <r3=reg128#5,<v4=reg128#4%bot,<5y34=reg128#13%top # asm 2: vmlal.u32 <r3=q4,<v4=d6,<5y34=d25 vmlal.u32 q4,d6,d25 # qhasm: ptr = &5y12_stack # asm 1: lea >ptr=int32#3,<5y12_stack=stack128#5 # asm 2: lea >ptr=r2,<5y12_stack=[sp,#64] add r2,sp,#64 # qhasm: 5y12 aligned= mem128[ptr] # asm 1: vld1.8 {>5y12=reg128#12%bot->5y12=reg128#12%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>5y12=d22->5y12=d23},[<ptr=r2,: 128] vld1.8 {d22-d23},[r2,: 128] # qhasm: r0[0,1] += v4[0] unsigned* 5y12[0]; r0[2,3] += v4[1] unsigned* 5y12[1] # asm 1: vmlal.u32 <r0=reg128#8,<v4=reg128#4%bot,<5y12=reg128#12%bot # asm 2: vmlal.u32 <r0=q7,<v4=d6,<5y12=d22 vmlal.u32 q7,d6,d22 # qhasm: r0[0,1] += v23[0] unsigned* 5y34[0]; r0[2,3] += v23[1] unsigned* 5y34[1] # asm 1: vmlal.u32 <r0=reg128#8,<v23=reg128#10%bot,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r0=q7,<v23=d18,<5y34=d24 vmlal.u32 q7,d18,d24 # qhasm: r0[0,1] += v23[2] unsigned* 5y12[2]; r0[2,3] += v23[3] unsigned* 5y12[3] # asm 1: vmlal.u32 <r0=reg128#8,<v23=reg128#10%top,<5y12=reg128#12%top # asm 2: vmlal.u32 <r0=q7,<v23=d19,<5y12=d23 vmlal.u32 q7,d19,d23 # qhasm: r0[0,1] += v01[0] unsigned* y0[0]; r0[2,3] += v01[1] unsigned* y0[1] # asm 1: vmlal.u32 <r0=reg128#8,<v01=reg128#11%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r0=q7,<v01=d20,<y0=d0 vmlal.u32 q7,d20,d0 # qhasm: r0[0,1] += v01[2] unsigned* 5y34[2]; r0[2,3] += v01[3] unsigned* 5y34[3] # asm 1: vmlal.u32 <r0=reg128#8,<v01=reg128#11%top,<5y34=reg128#13%top # asm 2: vmlal.u32 <r0=q7,<v01=d21,<5y34=d25 vmlal.u32 q7,d21,d25 # qhasm: r1[0,1] += v01[0] unsigned* y12[0]; r1[2,3] += v01[1] unsigned* y12[1] # asm 1: vmlal.u32 <r1=reg128#15,<v01=reg128#11%bot,<y12=reg128#2%bot # asm 2: vmlal.u32 <r1=q14,<v01=d20,<y12=d2 vmlal.u32 q14,d20,d2 # qhasm: r1[0,1] += v01[2] unsigned* y0[0]; r1[2,3] += v01[3] unsigned* y0[1] # asm 1: vmlal.u32 <r1=reg128#15,<v01=reg128#11%top,<y0=reg128#1%bot # asm 2: vmlal.u32 <r1=q14,<v01=d21,<y0=d0 vmlal.u32 q14,d21,d0 # qhasm: r1[0,1] += v23[0] unsigned* 5y34[2]; r1[2,3] += v23[1] unsigned* 5y34[3] # asm 1: vmlal.u32 <r1=reg128#15,<v23=reg128#10%bot,<5y34=reg128#13%top # asm 2: vmlal.u32 <r1=q14,<v23=d18,<5y34=d25 vmlal.u32 q14,d18,d25 # qhasm: r1[0,1] += v23[2] unsigned* 5y34[0]; r1[2,3] += v23[3] unsigned* 5y34[1] # asm 1: vmlal.u32 <r1=reg128#15,<v23=reg128#10%top,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r1=q14,<v23=d19,<5y34=d24 vmlal.u32 q14,d19,d24 # qhasm: r1[0,1] += v4[0] unsigned* 5y12[2]; r1[2,3] += v4[1] unsigned* 5y12[3] # asm 1: vmlal.u32 <r1=reg128#15,<v4=reg128#4%bot,<5y12=reg128#12%top # asm 2: vmlal.u32 <r1=q14,<v4=d6,<5y12=d23 vmlal.u32 q14,d6,d23 # qhasm: r2[0,1] += v01[0] unsigned* y12[2]; r2[2,3] += v01[1] unsigned* y12[3] # asm 1: vmlal.u32 <r2=reg128#14,<v01=reg128#11%bot,<y12=reg128#2%top # asm 2: vmlal.u32 <r2=q13,<v01=d20,<y12=d3 vmlal.u32 q13,d20,d3 # qhasm: r2[0,1] += v01[2] unsigned* y12[0]; r2[2,3] += v01[3] unsigned* y12[1] # asm 1: vmlal.u32 <r2=reg128#14,<v01=reg128#11%top,<y12=reg128#2%bot # asm 2: vmlal.u32 <r2=q13,<v01=d21,<y12=d2 vmlal.u32 q13,d21,d2 # qhasm: r2[0,1] += v23[0] unsigned* y0[0]; r2[2,3] += v23[1] unsigned* y0[1] # asm 1: vmlal.u32 <r2=reg128#14,<v23=reg128#10%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r2=q13,<v23=d18,<y0=d0 vmlal.u32 q13,d18,d0 # qhasm: r2[0,1] += v23[2] unsigned* 5y34[2]; r2[2,3] += v23[3] unsigned* 5y34[3] # asm 1: vmlal.u32 <r2=reg128#14,<v23=reg128#10%top,<5y34=reg128#13%top # asm 2: vmlal.u32 <r2=q13,<v23=d19,<5y34=d25 vmlal.u32 q13,d19,d25 # qhasm: r2[0,1] += v4[0] unsigned* 5y34[0]; r2[2,3] += v4[1] unsigned* 5y34[1] # asm 1: vmlal.u32 <r2=reg128#14,<v4=reg128#4%bot,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r2=q13,<v4=d6,<5y34=d24 vmlal.u32 q13,d6,d24 # qhasm: ptr = &two24 # asm 1: lea >ptr=int32#3,<two24=stack128#1 # asm 2: lea >ptr=r2,<two24=[sp,#0] add r2,sp,#0 # qhasm: 2x t1 = r0 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#4,<r0=reg128#8,#26 # asm 2: vshr.u64 >t1=q3,<r0=q7,#26 vshr.u64 q3,q7,#26 # qhasm: len -= 64 # asm 1: sub >len=int32#4,<len=int32#4,#64 # asm 2: sub >len=r3,<len=r3,#64 sub r3,r3,#64 # qhasm: r0 &= mask # asm 1: vand >r0=reg128#6,<r0=reg128#8,<mask=reg128#7 # asm 2: vand >r0=q5,<r0=q7,<mask=q6 vand q5,q7,q6 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#15,<t1=reg128#4 # asm 2: vadd.i64 >r1=q3,<r1=q14,<t1=q3 vadd.i64 q3,q14,q3 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#8,<r3=reg128#5,#26 # asm 2: vshr.u64 >t4=q7,<r3=q4,#26 vshr.u64 q7,q4,#26 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#5,<r3=reg128#5,<mask=reg128#7 # asm 2: vand >r3=q4,<r3=q4,<mask=q6 vand q4,q4,q6 # qhasm: 2x x4 = r4 + t4 # asm 1: vadd.i64 >x4=reg128#8,<r4=reg128#16,<t4=reg128#8 # asm 2: vadd.i64 >x4=q7,<r4=q15,<t4=q7 vadd.i64 q7,q15,q7 # qhasm: r4 aligned= mem128[ptr] # asm 1: vld1.8 {>r4=reg128#16%bot->r4=reg128#16%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>r4=d30->r4=d31},[<ptr=r2,: 128] vld1.8 {d30-d31},[r2,: 128] # qhasm: 2x t2 = r1 unsigned>> 26 # asm 1: vshr.u64 >t2=reg128#9,<r1=reg128#4,#26 # asm 2: vshr.u64 >t2=q8,<r1=q3,#26 vshr.u64 q8,q3,#26 # qhasm: r1 &= mask # asm 1: vand >r1=reg128#4,<r1=reg128#4,<mask=reg128#7 # asm 2: vand >r1=q3,<r1=q3,<mask=q6 vand q3,q3,q6 # qhasm: 2x t0 = x4 unsigned>> 26 # asm 1: vshr.u64 >t0=reg128#10,<x4=reg128#8,#26 # asm 2: vshr.u64 >t0=q9,<x4=q7,#26 vshr.u64 q9,q7,#26 # qhasm: 2x r2 += t2 # asm 1: vadd.i64 >r2=reg128#9,<r2=reg128#14,<t2=reg128#9 # asm 2: vadd.i64 >r2=q8,<r2=q13,<t2=q8 vadd.i64 q8,q13,q8 # qhasm: x4 &= mask # asm 1: vand >x4=reg128#11,<x4=reg128#8,<mask=reg128#7 # asm 2: vand >x4=q10,<x4=q7,<mask=q6 vand q10,q7,q6 # qhasm: 2x x01 = r0 + t0 # asm 1: vadd.i64 >x01=reg128#6,<r0=reg128#6,<t0=reg128#10 # asm 2: vadd.i64 >x01=q5,<r0=q5,<t0=q9 vadd.i64 q5,q5,q9 # qhasm: r0 aligned= mem128[ptr] # asm 1: vld1.8 {>r0=reg128#8%bot->r0=reg128#8%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>r0=d14->r0=d15},[<ptr=r2,: 128] vld1.8 {d14-d15},[r2,: 128] # qhasm: ptr = &z34_stack # asm 1: lea >ptr=int32#3,<z34_stack=stack128#9 # asm 2: lea >ptr=r2,<z34_stack=[sp,#128] add r2,sp,#128 # qhasm: 2x t0 <<= 2 # asm 1: vshl.i64 >t0=reg128#10,<t0=reg128#10,#2 # asm 2: vshl.i64 >t0=q9,<t0=q9,#2 vshl.i64 q9,q9,#2 # qhasm: 2x t3 = r2 unsigned>> 26 # asm 1: vshr.u64 >t3=reg128#14,<r2=reg128#9,#26 # asm 2: vshr.u64 >t3=q13,<r2=q8,#26 vshr.u64 q13,q8,#26 # qhasm: 2x x01 += t0 # asm 1: vadd.i64 >x01=reg128#15,<x01=reg128#6,<t0=reg128#10 # asm 2: vadd.i64 >x01=q14,<x01=q5,<t0=q9 vadd.i64 q14,q5,q9 # qhasm: z34 aligned= mem128[ptr] # asm 1: vld1.8 {>z34=reg128#6%bot->z34=reg128#6%top},[<ptr=int32#3,: 128] # asm 2: vld1.8 {>z34=d10->z34=d11},[<ptr=r2,: 128] vld1.8 {d10-d11},[r2,: 128] # qhasm: x23 = r2 & mask # asm 1: vand >x23=reg128#10,<r2=reg128#9,<mask=reg128#7 # asm 2: vand >x23=q9,<r2=q8,<mask=q6 vand q9,q8,q6 # qhasm: 2x r3 += t3 # asm 1: vadd.i64 >r3=reg128#5,<r3=reg128#5,<t3=reg128#14 # asm 2: vadd.i64 >r3=q4,<r3=q4,<t3=q13 vadd.i64 q4,q4,q13 # qhasm: input_2 += 32 # asm 1: add >input_2=int32#2,<input_2=int32#2,#32 # asm 2: add >input_2=r1,<input_2=r1,#32 add r1,r1,#32 # qhasm: 2x t1 = x01 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#14,<x01=reg128#15,#26 # asm 2: vshr.u64 >t1=q13,<x01=q14,#26 vshr.u64 q13,q14,#26 # qhasm: x23 = x23[0,2,1,3] # asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top # asm 2: vtrn.32 <x23=d18,<x23=d19 vtrn.32 d18,d19 # qhasm: x01 = x01 & mask # asm 1: vand >x01=reg128#9,<x01=reg128#15,<mask=reg128#7 # asm 2: vand >x01=q8,<x01=q14,<mask=q6 vand q8,q14,q6 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#4,<t1=reg128#14 # asm 2: vadd.i64 >r1=q3,<r1=q3,<t1=q13 vadd.i64 q3,q3,q13 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#14,<r3=reg128#5,#26 # asm 2: vshr.u64 >t4=q13,<r3=q4,#26 vshr.u64 q13,q4,#26 # qhasm: x01 = x01[0,2,1,3] # asm 1: vtrn.32 <x01=reg128#9%bot,<x01=reg128#9%top # asm 2: vtrn.32 <x01=d16,<x01=d17 vtrn.32 d16,d17 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#5,<r3=reg128#5,<mask=reg128#7 # asm 2: vand >r3=q4,<r3=q4,<mask=q6 vand q4,q4,q6 # qhasm: r1 = r1[0,2,1,3] # asm 1: vtrn.32 <r1=reg128#4%bot,<r1=reg128#4%top # asm 2: vtrn.32 <r1=d6,<r1=d7 vtrn.32 d6,d7 # qhasm: 2x x4 += t4 # asm 1: vadd.i64 >x4=reg128#11,<x4=reg128#11,<t4=reg128#14 # asm 2: vadd.i64 >x4=q10,<x4=q10,<t4=q13 vadd.i64 q10,q10,q13 # qhasm: r3 = r3[0,2,1,3] # asm 1: vtrn.32 <r3=reg128#5%bot,<r3=reg128#5%top # asm 2: vtrn.32 <r3=d8,<r3=d9 vtrn.32 d8,d9 # qhasm: x01 = x01[0,1] r1[0,1] # asm 1: vext.32 <x01=reg128#9%top,<r1=reg128#4%bot,<r1=reg128#4%bot,#0 # asm 2: vext.32 <x01=d17,<r1=d6,<r1=d6,#0 vext.32 d17,d6,d6,#0 # qhasm: x23 = x23[0,1] r3[0,1] # asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#5%bot,<r3=reg128#5%bot,#0 # asm 2: vext.32 <x23=d19,<r3=d8,<r3=d8,#0 vext.32 d19,d8,d8,#0 # qhasm: x4 = x4[0,2,1,3] # asm 1: vtrn.32 <x4=reg128#11%bot,<x4=reg128#11%top # asm 2: vtrn.32 <x4=d20,<x4=d21 vtrn.32 d20,d21 # qhasm: unsigned>? len - 64 # asm 1: cmp <len=int32#4,#64 # asm 2: cmp <len=r3,#64 cmp r3,#64 # qhasm: goto mainloop2 if unsigned> bhi ._mainloop2 # qhasm: input_2 -= 32 # asm 1: sub >input_2=int32#3,<input_2=int32#2,#32 # asm 2: sub >input_2=r2,<input_2=r1,#32 sub r2,r1,#32 # qhasm: below64bytes: ._below64bytes: # qhasm: unsigned>? len - 32 # asm 1: cmp <len=int32#4,#32 # asm 2: cmp <len=r3,#32 cmp r3,#32 # qhasm: goto end if !unsigned> bls ._end # qhasm: mainloop: ._mainloop: # qhasm: new r0 # qhasm: ptr = &two24 # asm 1: lea >ptr=int32#2,<two24=stack128#1 # asm 2: lea >ptr=r1,<two24=[sp,#0] add r1,sp,#0 # qhasm: r4 aligned= mem128[ptr] # asm 1: vld1.8 {>r4=reg128#5%bot->r4=reg128#5%top},[<ptr=int32#2,: 128] # asm 2: vld1.8 {>r4=d8->r4=d9},[<ptr=r1,: 128] vld1.8 {d8-d9},[r1,: 128] # qhasm: u4 aligned= mem128[ptr] # asm 1: vld1.8 {>u4=reg128#6%bot->u4=reg128#6%top},[<ptr=int32#2,: 128] # asm 2: vld1.8 {>u4=d10->u4=d11},[<ptr=r1,: 128] vld1.8 {d10-d11},[r1,: 128] # qhasm: c01 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>c01=reg128#8%bot->c01=reg128#8%top},[<input_2=int32#3]! # asm 2: vld1.8 {>c01=d14->c01=d15},[<input_2=r2]! vld1.8 {d14-d15},[r2]! # qhasm: r4[0,1] += x01[0] unsigned* y34[2]; r4[2,3] += x01[1] unsigned* y34[3] # asm 1: vmlal.u32 <r4=reg128#5,<x01=reg128#9%bot,<y34=reg128#3%top # asm 2: vmlal.u32 <r4=q4,<x01=d16,<y34=d5 vmlal.u32 q4,d16,d5 # qhasm: c23 = mem128[input_2];input_2+=16 # asm 1: vld1.8 {>c23=reg128#14%bot->c23=reg128#14%top},[<input_2=int32#3]! # asm 2: vld1.8 {>c23=d26->c23=d27},[<input_2=r2]! vld1.8 {d26-d27},[r2]! # qhasm: r4[0,1] += x01[2] unsigned* y34[0]; r4[2,3] += x01[3] unsigned* y34[1] # asm 1: vmlal.u32 <r4=reg128#5,<x01=reg128#9%top,<y34=reg128#3%bot # asm 2: vmlal.u32 <r4=q4,<x01=d17,<y34=d4 vmlal.u32 q4,d17,d4 # qhasm: r0 = u4[1]c01[0]r0[2,3] # asm 1: vext.32 <r0=reg128#4%bot,<u4=reg128#6%bot,<c01=reg128#8%bot,#1 # asm 2: vext.32 <r0=d6,<u4=d10,<c01=d14,#1 vext.32 d6,d10,d14,#1 # qhasm: r4[0,1] += x23[0] unsigned* y12[2]; r4[2,3] += x23[1] unsigned* y12[3] # asm 1: vmlal.u32 <r4=reg128#5,<x23=reg128#10%bot,<y12=reg128#2%top # asm 2: vmlal.u32 <r4=q4,<x23=d18,<y12=d3 vmlal.u32 q4,d18,d3 # qhasm: r0 = r0[0,1]u4[1]c23[0] # asm 1: vext.32 <r0=reg128#4%top,<u4=reg128#6%bot,<c23=reg128#14%bot,#1 # asm 2: vext.32 <r0=d7,<u4=d10,<c23=d26,#1 vext.32 d7,d10,d26,#1 # qhasm: r4[0,1] += x23[2] unsigned* y12[0]; r4[2,3] += x23[3] unsigned* y12[1] # asm 1: vmlal.u32 <r4=reg128#5,<x23=reg128#10%top,<y12=reg128#2%bot # asm 2: vmlal.u32 <r4=q4,<x23=d19,<y12=d2 vmlal.u32 q4,d19,d2 # qhasm: r0 = r0[1]r0[0]r0[3]r0[2] # asm 1: vrev64.i32 >r0=reg128#4,<r0=reg128#4 # asm 2: vrev64.i32 >r0=q3,<r0=q3 vrev64.i32 q3,q3 # qhasm: r4[0,1] += x4[0] unsigned* y0[0]; r4[2,3] += x4[1] unsigned* y0[1] # asm 1: vmlal.u32 <r4=reg128#5,<x4=reg128#11%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r4=q4,<x4=d20,<y0=d0 vmlal.u32 q4,d20,d0 # qhasm: r0[0,1] += x4[0] unsigned* 5y12[0]; r0[2,3] += x4[1] unsigned* 5y12[1] # asm 1: vmlal.u32 <r0=reg128#4,<x4=reg128#11%bot,<5y12=reg128#12%bot # asm 2: vmlal.u32 <r0=q3,<x4=d20,<5y12=d22 vmlal.u32 q3,d20,d22 # qhasm: r0[0,1] += x23[0] unsigned* 5y34[0]; r0[2,3] += x23[1] unsigned* 5y34[1] # asm 1: vmlal.u32 <r0=reg128#4,<x23=reg128#10%bot,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r0=q3,<x23=d18,<5y34=d24 vmlal.u32 q3,d18,d24 # qhasm: r0[0,1] += x23[2] unsigned* 5y12[2]; r0[2,3] += x23[3] unsigned* 5y12[3] # asm 1: vmlal.u32 <r0=reg128#4,<x23=reg128#10%top,<5y12=reg128#12%top # asm 2: vmlal.u32 <r0=q3,<x23=d19,<5y12=d23 vmlal.u32 q3,d19,d23 # qhasm: c01 c23 = c01[0]c23[0]c01[2]c23[2]c01[1]c23[1]c01[3]c23[3] # asm 1: vtrn.32 <c01=reg128#8,<c23=reg128#14 # asm 2: vtrn.32 <c01=q7,<c23=q13 vtrn.32 q7,q13 # qhasm: r0[0,1] += x01[0] unsigned* y0[0]; r0[2,3] += x01[1] unsigned* y0[1] # asm 1: vmlal.u32 <r0=reg128#4,<x01=reg128#9%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r0=q3,<x01=d16,<y0=d0 vmlal.u32 q3,d16,d0 # qhasm: r3[0,1] = c23[2]<<18; r3[2,3] = c23[3]<<18 # asm 1: vshll.u32 >r3=reg128#6,<c23=reg128#14%top,#18 # asm 2: vshll.u32 >r3=q5,<c23=d27,#18 vshll.u32 q5,d27,#18 # qhasm: r0[0,1] += x01[2] unsigned* 5y34[2]; r0[2,3] += x01[3] unsigned* 5y34[3] # asm 1: vmlal.u32 <r0=reg128#4,<x01=reg128#9%top,<5y34=reg128#13%top # asm 2: vmlal.u32 <r0=q3,<x01=d17,<5y34=d25 vmlal.u32 q3,d17,d25 # qhasm: r3[0,1] += x01[0] unsigned* y34[0]; r3[2,3] += x01[1] unsigned* y34[1] # asm 1: vmlal.u32 <r3=reg128#6,<x01=reg128#9%bot,<y34=reg128#3%bot # asm 2: vmlal.u32 <r3=q5,<x01=d16,<y34=d4 vmlal.u32 q5,d16,d4 # qhasm: r3[0,1] += x01[2] unsigned* y12[2]; r3[2,3] += x01[3] unsigned* y12[3] # asm 1: vmlal.u32 <r3=reg128#6,<x01=reg128#9%top,<y12=reg128#2%top # asm 2: vmlal.u32 <r3=q5,<x01=d17,<y12=d3 vmlal.u32 q5,d17,d3 # qhasm: r3[0,1] += x23[0] unsigned* y12[0]; r3[2,3] += x23[1] unsigned* y12[1] # asm 1: vmlal.u32 <r3=reg128#6,<x23=reg128#10%bot,<y12=reg128#2%bot # asm 2: vmlal.u32 <r3=q5,<x23=d18,<y12=d2 vmlal.u32 q5,d18,d2 # qhasm: r3[0,1] += x23[2] unsigned* y0[0]; r3[2,3] += x23[3] unsigned* y0[1] # asm 1: vmlal.u32 <r3=reg128#6,<x23=reg128#10%top,<y0=reg128#1%bot # asm 2: vmlal.u32 <r3=q5,<x23=d19,<y0=d0 vmlal.u32 q5,d19,d0 # qhasm: r1[0,1] = c23[0]<<6; r1[2,3] = c23[1]<<6 # asm 1: vshll.u32 >r1=reg128#14,<c23=reg128#14%bot,#6 # asm 2: vshll.u32 >r1=q13,<c23=d26,#6 vshll.u32 q13,d26,#6 # qhasm: r3[0,1] += x4[0] unsigned* 5y34[2]; r3[2,3] += x4[1] unsigned* 5y34[3] # asm 1: vmlal.u32 <r3=reg128#6,<x4=reg128#11%bot,<5y34=reg128#13%top # asm 2: vmlal.u32 <r3=q5,<x4=d20,<5y34=d25 vmlal.u32 q5,d20,d25 # qhasm: r1[0,1] += x01[0] unsigned* y12[0]; r1[2,3] += x01[1] unsigned* y12[1] # asm 1: vmlal.u32 <r1=reg128#14,<x01=reg128#9%bot,<y12=reg128#2%bot # asm 2: vmlal.u32 <r1=q13,<x01=d16,<y12=d2 vmlal.u32 q13,d16,d2 # qhasm: r1[0,1] += x01[2] unsigned* y0[0]; r1[2,3] += x01[3] unsigned* y0[1] # asm 1: vmlal.u32 <r1=reg128#14,<x01=reg128#9%top,<y0=reg128#1%bot # asm 2: vmlal.u32 <r1=q13,<x01=d17,<y0=d0 vmlal.u32 q13,d17,d0 # qhasm: r1[0,1] += x23[0] unsigned* 5y34[2]; r1[2,3] += x23[1] unsigned* 5y34[3] # asm 1: vmlal.u32 <r1=reg128#14,<x23=reg128#10%bot,<5y34=reg128#13%top # asm 2: vmlal.u32 <r1=q13,<x23=d18,<5y34=d25 vmlal.u32 q13,d18,d25 # qhasm: r1[0,1] += x23[2] unsigned* 5y34[0]; r1[2,3] += x23[3] unsigned* 5y34[1] # asm 1: vmlal.u32 <r1=reg128#14,<x23=reg128#10%top,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r1=q13,<x23=d19,<5y34=d24 vmlal.u32 q13,d19,d24 # qhasm: r2[0,1] = c01[2]<<12; r2[2,3] = c01[3]<<12 # asm 1: vshll.u32 >r2=reg128#8,<c01=reg128#8%top,#12 # asm 2: vshll.u32 >r2=q7,<c01=d15,#12 vshll.u32 q7,d15,#12 # qhasm: r1[0,1] += x4[0] unsigned* 5y12[2]; r1[2,3] += x4[1] unsigned* 5y12[3] # asm 1: vmlal.u32 <r1=reg128#14,<x4=reg128#11%bot,<5y12=reg128#12%top # asm 2: vmlal.u32 <r1=q13,<x4=d20,<5y12=d23 vmlal.u32 q13,d20,d23 # qhasm: r2[0,1] += x01[0] unsigned* y12[2]; r2[2,3] += x01[1] unsigned* y12[3] # asm 1: vmlal.u32 <r2=reg128#8,<x01=reg128#9%bot,<y12=reg128#2%top # asm 2: vmlal.u32 <r2=q7,<x01=d16,<y12=d3 vmlal.u32 q7,d16,d3 # qhasm: r2[0,1] += x01[2] unsigned* y12[0]; r2[2,3] += x01[3] unsigned* y12[1] # asm 1: vmlal.u32 <r2=reg128#8,<x01=reg128#9%top,<y12=reg128#2%bot # asm 2: vmlal.u32 <r2=q7,<x01=d17,<y12=d2 vmlal.u32 q7,d17,d2 # qhasm: r2[0,1] += x23[0] unsigned* y0[0]; r2[2,3] += x23[1] unsigned* y0[1] # asm 1: vmlal.u32 <r2=reg128#8,<x23=reg128#10%bot,<y0=reg128#1%bot # asm 2: vmlal.u32 <r2=q7,<x23=d18,<y0=d0 vmlal.u32 q7,d18,d0 # qhasm: r2[0,1] += x23[2] unsigned* 5y34[2]; r2[2,3] += x23[3] unsigned* 5y34[3] # asm 1: vmlal.u32 <r2=reg128#8,<x23=reg128#10%top,<5y34=reg128#13%top # asm 2: vmlal.u32 <r2=q7,<x23=d19,<5y34=d25 vmlal.u32 q7,d19,d25 # qhasm: r2[0,1] += x4[0] unsigned* 5y34[0]; r2[2,3] += x4[1] unsigned* 5y34[1] # asm 1: vmlal.u32 <r2=reg128#8,<x4=reg128#11%bot,<5y34=reg128#13%bot # asm 2: vmlal.u32 <r2=q7,<x4=d20,<5y34=d24 vmlal.u32 q7,d20,d24 # qhasm: 2x t1 = r0 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#9,<r0=reg128#4,#26 # asm 2: vshr.u64 >t1=q8,<r0=q3,#26 vshr.u64 q8,q3,#26 # qhasm: r0 &= mask # asm 1: vand >r0=reg128#4,<r0=reg128#4,<mask=reg128#7 # asm 2: vand >r0=q3,<r0=q3,<mask=q6 vand q3,q3,q6 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#9,<r1=reg128#14,<t1=reg128#9 # asm 2: vadd.i64 >r1=q8,<r1=q13,<t1=q8 vadd.i64 q8,q13,q8 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#10,<r3=reg128#6,#26 # asm 2: vshr.u64 >t4=q9,<r3=q5,#26 vshr.u64 q9,q5,#26 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#6,<r3=reg128#6,<mask=reg128#7 # asm 2: vand >r3=q5,<r3=q5,<mask=q6 vand q5,q5,q6 # qhasm: 2x r4 += t4 # asm 1: vadd.i64 >r4=reg128#5,<r4=reg128#5,<t4=reg128#10 # asm 2: vadd.i64 >r4=q4,<r4=q4,<t4=q9 vadd.i64 q4,q4,q9 # qhasm: 2x t2 = r1 unsigned>> 26 # asm 1: vshr.u64 >t2=reg128#10,<r1=reg128#9,#26 # asm 2: vshr.u64 >t2=q9,<r1=q8,#26 vshr.u64 q9,q8,#26 # qhasm: r1 &= mask # asm 1: vand >r1=reg128#11,<r1=reg128#9,<mask=reg128#7 # asm 2: vand >r1=q10,<r1=q8,<mask=q6 vand q10,q8,q6 # qhasm: 2x t0 = r4 unsigned>> 26 # asm 1: vshr.u64 >t0=reg128#9,<r4=reg128#5,#26 # asm 2: vshr.u64 >t0=q8,<r4=q4,#26 vshr.u64 q8,q4,#26 # qhasm: 2x r2 += t2 # asm 1: vadd.i64 >r2=reg128#8,<r2=reg128#8,<t2=reg128#10 # asm 2: vadd.i64 >r2=q7,<r2=q7,<t2=q9 vadd.i64 q7,q7,q9 # qhasm: r4 &= mask # asm 1: vand >r4=reg128#5,<r4=reg128#5,<mask=reg128#7 # asm 2: vand >r4=q4,<r4=q4,<mask=q6 vand q4,q4,q6 # qhasm: 2x r0 += t0 # asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#9 # asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q8 vadd.i64 q3,q3,q8 # qhasm: 2x t0 <<= 2 # asm 1: vshl.i64 >t0=reg128#9,<t0=reg128#9,#2 # asm 2: vshl.i64 >t0=q8,<t0=q8,#2 vshl.i64 q8,q8,#2 # qhasm: 2x t3 = r2 unsigned>> 26 # asm 1: vshr.u64 >t3=reg128#14,<r2=reg128#8,#26 # asm 2: vshr.u64 >t3=q13,<r2=q7,#26 vshr.u64 q13,q7,#26 # qhasm: 2x r0 += t0 # asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#9 # asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q8 vadd.i64 q3,q3,q8 # qhasm: x23 = r2 & mask # asm 1: vand >x23=reg128#10,<r2=reg128#8,<mask=reg128#7 # asm 2: vand >x23=q9,<r2=q7,<mask=q6 vand q9,q7,q6 # qhasm: 2x r3 += t3 # asm 1: vadd.i64 >r3=reg128#6,<r3=reg128#6,<t3=reg128#14 # asm 2: vadd.i64 >r3=q5,<r3=q5,<t3=q13 vadd.i64 q5,q5,q13 # qhasm: 2x t1 = r0 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#8,<r0=reg128#4,#26 # asm 2: vshr.u64 >t1=q7,<r0=q3,#26 vshr.u64 q7,q3,#26 # qhasm: x01 = r0 & mask # asm 1: vand >x01=reg128#9,<r0=reg128#4,<mask=reg128#7 # asm 2: vand >x01=q8,<r0=q3,<mask=q6 vand q8,q3,q6 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#11,<t1=reg128#8 # asm 2: vadd.i64 >r1=q3,<r1=q10,<t1=q7 vadd.i64 q3,q10,q7 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#8,<r3=reg128#6,#26 # asm 2: vshr.u64 >t4=q7,<r3=q5,#26 vshr.u64 q7,q5,#26 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#6,<r3=reg128#6,<mask=reg128#7 # asm 2: vand >r3=q5,<r3=q5,<mask=q6 vand q5,q5,q6 # qhasm: 2x x4 = r4 + t4 # asm 1: vadd.i64 >x4=reg128#11,<r4=reg128#5,<t4=reg128#8 # asm 2: vadd.i64 >x4=q10,<r4=q4,<t4=q7 vadd.i64 q10,q4,q7 # qhasm: len -= 32 # asm 1: sub >len=int32#4,<len=int32#4,#32 # asm 2: sub >len=r3,<len=r3,#32 sub r3,r3,#32 # qhasm: x01 = x01[0,2,1,3] # asm 1: vtrn.32 <x01=reg128#9%bot,<x01=reg128#9%top # asm 2: vtrn.32 <x01=d16,<x01=d17 vtrn.32 d16,d17 # qhasm: x23 = x23[0,2,1,3] # asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top # asm 2: vtrn.32 <x23=d18,<x23=d19 vtrn.32 d18,d19 # qhasm: r1 = r1[0,2,1,3] # asm 1: vtrn.32 <r1=reg128#4%bot,<r1=reg128#4%top # asm 2: vtrn.32 <r1=d6,<r1=d7 vtrn.32 d6,d7 # qhasm: r3 = r3[0,2,1,3] # asm 1: vtrn.32 <r3=reg128#6%bot,<r3=reg128#6%top # asm 2: vtrn.32 <r3=d10,<r3=d11 vtrn.32 d10,d11 # qhasm: x4 = x4[0,2,1,3] # asm 1: vtrn.32 <x4=reg128#11%bot,<x4=reg128#11%top # asm 2: vtrn.32 <x4=d20,<x4=d21 vtrn.32 d20,d21 # qhasm: x01 = x01[0,1] r1[0,1] # asm 1: vext.32 <x01=reg128#9%top,<r1=reg128#4%bot,<r1=reg128#4%bot,#0 # asm 2: vext.32 <x01=d17,<r1=d6,<r1=d6,#0 vext.32 d17,d6,d6,#0 # qhasm: x23 = x23[0,1] r3[0,1] # asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#6%bot,<r3=reg128#6%bot,#0 # asm 2: vext.32 <x23=d19,<r3=d10,<r3=d10,#0 vext.32 d19,d10,d10,#0 # qhasm: unsigned>? len - 32 # asm 1: cmp <len=int32#4,#32 # asm 2: cmp <len=r3,#32 cmp r3,#32 # qhasm: goto mainloop if unsigned> bhi ._mainloop # qhasm: end: ._end: # qhasm: mem128[input_0] = x01;input_0+=16 # asm 1: vst1.8 {<x01=reg128#9%bot-<x01=reg128#9%top},[<input_0=int32#1]! # asm 2: vst1.8 {<x01=d16-<x01=d17},[<input_0=r0]! vst1.8 {d16-d17},[r0]! # qhasm: mem128[input_0] = x23;input_0+=16 # asm 1: vst1.8 {<x23=reg128#10%bot-<x23=reg128#10%top},[<input_0=int32#1]! # asm 2: vst1.8 {<x23=d18-<x23=d19},[<input_0=r0]! vst1.8 {d18-d19},[r0]! # qhasm: mem64[input_0] = x4[0] # asm 1: vst1.8 <x4=reg128#11%bot,[<input_0=int32#1] # asm 2: vst1.8 <x4=d20,[<input_0=r0] vst1.8 d20,[r0] # qhasm: len = len # asm 1: mov >len=int32#1,<len=int32#4 # asm 2: mov >len=r0,<len=r3 mov r0,r3 # qhasm: qpopreturn len mov sp,r12 vpop {q4,q5,q6,q7} bx lr # qhasm: int32 input_0 # qhasm: int32 input_1 # qhasm: int32 input_2 # qhasm: int32 input_3 # qhasm: stack32 input_4 # qhasm: stack32 input_5 # qhasm: stack32 input_6 # qhasm: stack32 input_7 # qhasm: int32 caller_r4 # qhasm: int32 caller_r5 # qhasm: int32 caller_r6 # qhasm: int32 caller_r7 # qhasm: int32 caller_r8 # qhasm: int32 caller_r9 # qhasm: int32 caller_r10 # qhasm: int32 caller_r11 # qhasm: int32 caller_r12 # qhasm: int32 caller_r14 # qhasm: reg128 caller_q4 # qhasm: reg128 caller_q5 # qhasm: reg128 caller_q6 # qhasm: reg128 caller_q7 # qhasm: reg128 r0 # qhasm: reg128 r1 # qhasm: reg128 r2 # qhasm: reg128 r3 # qhasm: reg128 r4 # qhasm: reg128 x01 # qhasm: reg128 x23 # qhasm: reg128 x4 # qhasm: reg128 y01 # qhasm: reg128 y23 # qhasm: reg128 y4 # qhasm: reg128 _5y01 # qhasm: reg128 _5y23 # qhasm: reg128 _5y4 # qhasm: reg128 c01 # qhasm: reg128 c23 # qhasm: reg128 c4 # qhasm: reg128 t0 # qhasm: reg128 t1 # qhasm: reg128 t2 # qhasm: reg128 t3 # qhasm: reg128 t4 # qhasm: reg128 mask # qhasm: enter crypto_onetimeauth_poly1305_neon2_addmulmod .align 2 .global openssl_poly1305_neon2_addmulmod .hidden openssl_poly1305_neon2_addmulmod .type openssl_poly1305_neon2_addmulmod STT_FUNC openssl_poly1305_neon2_addmulmod: sub sp,sp,#0 # qhasm: 2x mask = 0xffffffff # asm 1: vmov.i64 >mask=reg128#1,#0xffffffff # asm 2: vmov.i64 >mask=q0,#0xffffffff vmov.i64 q0,#0xffffffff # qhasm: y01 aligned= mem128[input_2];input_2+=16 # asm 1: vld1.8 {>y01=reg128#2%bot->y01=reg128#2%top},[<input_2=int32#3,: 128]! # asm 2: vld1.8 {>y01=d2->y01=d3},[<input_2=r2,: 128]! vld1.8 {d2-d3},[r2,: 128]! # qhasm: 4x _5y01 = y01 << 2 # asm 1: vshl.i32 >_5y01=reg128#3,<y01=reg128#2,#2 # asm 2: vshl.i32 >_5y01=q2,<y01=q1,#2 vshl.i32 q2,q1,#2 # qhasm: y23 aligned= mem128[input_2];input_2+=16 # asm 1: vld1.8 {>y23=reg128#4%bot->y23=reg128#4%top},[<input_2=int32#3,: 128]! # asm 2: vld1.8 {>y23=d6->y23=d7},[<input_2=r2,: 128]! vld1.8 {d6-d7},[r2,: 128]! # qhasm: 4x _5y23 = y23 << 2 # asm 1: vshl.i32 >_5y23=reg128#9,<y23=reg128#4,#2 # asm 2: vshl.i32 >_5y23=q8,<y23=q3,#2 vshl.i32 q8,q3,#2 # qhasm: y4 aligned= mem64[input_2]y4[1] # asm 1: vld1.8 {<y4=reg128#10%bot},[<input_2=int32#3,: 64] # asm 2: vld1.8 {<y4=d18},[<input_2=r2,: 64] vld1.8 {d18},[r2,: 64] # qhasm: 4x _5y4 = y4 << 2 # asm 1: vshl.i32 >_5y4=reg128#11,<y4=reg128#10,#2 # asm 2: vshl.i32 >_5y4=q10,<y4=q9,#2 vshl.i32 q10,q9,#2 # qhasm: x01 aligned= mem128[input_1];input_1+=16 # asm 1: vld1.8 {>x01=reg128#12%bot->x01=reg128#12%top},[<input_1=int32#2,: 128]! # asm 2: vld1.8 {>x01=d22->x01=d23},[<input_1=r1,: 128]! vld1.8 {d22-d23},[r1,: 128]! # qhasm: 4x _5y01 += y01 # asm 1: vadd.i32 >_5y01=reg128#3,<_5y01=reg128#3,<y01=reg128#2 # asm 2: vadd.i32 >_5y01=q2,<_5y01=q2,<y01=q1 vadd.i32 q2,q2,q1 # qhasm: x23 aligned= mem128[input_1];input_1+=16 # asm 1: vld1.8 {>x23=reg128#13%bot->x23=reg128#13%top},[<input_1=int32#2,: 128]! # asm 2: vld1.8 {>x23=d24->x23=d25},[<input_1=r1,: 128]! vld1.8 {d24-d25},[r1,: 128]! # qhasm: 4x _5y23 += y23 # asm 1: vadd.i32 >_5y23=reg128#9,<_5y23=reg128#9,<y23=reg128#4 # asm 2: vadd.i32 >_5y23=q8,<_5y23=q8,<y23=q3 vadd.i32 q8,q8,q3 # qhasm: 4x _5y4 += y4 # asm 1: vadd.i32 >_5y4=reg128#11,<_5y4=reg128#11,<y4=reg128#10 # asm 2: vadd.i32 >_5y4=q10,<_5y4=q10,<y4=q9 vadd.i32 q10,q10,q9 # qhasm: c01 aligned= mem128[input_3];input_3+=16 # asm 1: vld1.8 {>c01=reg128#14%bot->c01=reg128#14%top},[<input_3=int32#4,: 128]! # asm 2: vld1.8 {>c01=d26->c01=d27},[<input_3=r3,: 128]! vld1.8 {d26-d27},[r3,: 128]! # qhasm: 4x x01 += c01 # asm 1: vadd.i32 >x01=reg128#12,<x01=reg128#12,<c01=reg128#14 # asm 2: vadd.i32 >x01=q11,<x01=q11,<c01=q13 vadd.i32 q11,q11,q13 # qhasm: c23 aligned= mem128[input_3];input_3+=16 # asm 1: vld1.8 {>c23=reg128#14%bot->c23=reg128#14%top},[<input_3=int32#4,: 128]! # asm 2: vld1.8 {>c23=d26->c23=d27},[<input_3=r3,: 128]! vld1.8 {d26-d27},[r3,: 128]! # qhasm: 4x x23 += c23 # asm 1: vadd.i32 >x23=reg128#13,<x23=reg128#13,<c23=reg128#14 # asm 2: vadd.i32 >x23=q12,<x23=q12,<c23=q13 vadd.i32 q12,q12,q13 # qhasm: x4 aligned= mem64[input_1]x4[1] # asm 1: vld1.8 {<x4=reg128#14%bot},[<input_1=int32#2,: 64] # asm 2: vld1.8 {<x4=d26},[<input_1=r1,: 64] vld1.8 {d26},[r1,: 64] # qhasm: 2x mask unsigned>>=6 # asm 1: vshr.u64 >mask=reg128#1,<mask=reg128#1,#6 # asm 2: vshr.u64 >mask=q0,<mask=q0,#6 vshr.u64 q0,q0,#6 # qhasm: c4 aligned= mem64[input_3]c4[1] # asm 1: vld1.8 {<c4=reg128#15%bot},[<input_3=int32#4,: 64] # asm 2: vld1.8 {<c4=d28},[<input_3=r3,: 64] vld1.8 {d28},[r3,: 64] # qhasm: 4x x4 += c4 # asm 1: vadd.i32 >x4=reg128#14,<x4=reg128#14,<c4=reg128#15 # asm 2: vadd.i32 >x4=q13,<x4=q13,<c4=q14 vadd.i32 q13,q13,q14 # qhasm: r0[0,1] = x01[0] unsigned* y01[0]; r0[2,3] = x01[1] unsigned* y01[1] # asm 1: vmull.u32 >r0=reg128#15,<x01=reg128#12%bot,<y01=reg128#2%bot # asm 2: vmull.u32 >r0=q14,<x01=d22,<y01=d2 vmull.u32 q14,d22,d2 # qhasm: r0[0,1] += x01[2] unsigned* _5y4[0]; r0[2,3] += x01[3] unsigned* _5y4[1] # asm 1: vmlal.u32 <r0=reg128#15,<x01=reg128#12%top,<_5y4=reg128#11%bot # asm 2: vmlal.u32 <r0=q14,<x01=d23,<_5y4=d20 vmlal.u32 q14,d23,d20 # qhasm: r0[0,1] += x23[0] unsigned* _5y23[2]; r0[2,3] += x23[1] unsigned* _5y23[3] # asm 1: vmlal.u32 <r0=reg128#15,<x23=reg128#13%bot,<_5y23=reg128#9%top # asm 2: vmlal.u32 <r0=q14,<x23=d24,<_5y23=d17 vmlal.u32 q14,d24,d17 # qhasm: r0[0,1] += x23[2] unsigned* _5y23[0]; r0[2,3] += x23[3] unsigned* _5y23[1] # asm 1: vmlal.u32 <r0=reg128#15,<x23=reg128#13%top,<_5y23=reg128#9%bot # asm 2: vmlal.u32 <r0=q14,<x23=d25,<_5y23=d16 vmlal.u32 q14,d25,d16 # qhasm: r0[0,1] += x4[0] unsigned* _5y01[2]; r0[2,3] += x4[1] unsigned* _5y01[3] # asm 1: vmlal.u32 <r0=reg128#15,<x4=reg128#14%bot,<_5y01=reg128#3%top # asm 2: vmlal.u32 <r0=q14,<x4=d26,<_5y01=d5 vmlal.u32 q14,d26,d5 # qhasm: r1[0,1] = x01[0] unsigned* y01[2]; r1[2,3] = x01[1] unsigned* y01[3] # asm 1: vmull.u32 >r1=reg128#3,<x01=reg128#12%bot,<y01=reg128#2%top # asm 2: vmull.u32 >r1=q2,<x01=d22,<y01=d3 vmull.u32 q2,d22,d3 # qhasm: r1[0,1] += x01[2] unsigned* y01[0]; r1[2,3] += x01[3] unsigned* y01[1] # asm 1: vmlal.u32 <r1=reg128#3,<x01=reg128#12%top,<y01=reg128#2%bot # asm 2: vmlal.u32 <r1=q2,<x01=d23,<y01=d2 vmlal.u32 q2,d23,d2 # qhasm: r1[0,1] += x23[0] unsigned* _5y4[0]; r1[2,3] += x23[1] unsigned* _5y4[1] # asm 1: vmlal.u32 <r1=reg128#3,<x23=reg128#13%bot,<_5y4=reg128#11%bot # asm 2: vmlal.u32 <r1=q2,<x23=d24,<_5y4=d20 vmlal.u32 q2,d24,d20 # qhasm: r1[0,1] += x23[2] unsigned* _5y23[2]; r1[2,3] += x23[3] unsigned* _5y23[3] # asm 1: vmlal.u32 <r1=reg128#3,<x23=reg128#13%top,<_5y23=reg128#9%top # asm 2: vmlal.u32 <r1=q2,<x23=d25,<_5y23=d17 vmlal.u32 q2,d25,d17 # qhasm: r1[0,1] += x4[0] unsigned* _5y23[0]; r1[2,3] += x4[1] unsigned* _5y23[1] # asm 1: vmlal.u32 <r1=reg128#3,<x4=reg128#14%bot,<_5y23=reg128#9%bot # asm 2: vmlal.u32 <r1=q2,<x4=d26,<_5y23=d16 vmlal.u32 q2,d26,d16 # qhasm: r2[0,1] = x01[0] unsigned* y23[0]; r2[2,3] = x01[1] unsigned* y23[1] # asm 1: vmull.u32 >r2=reg128#16,<x01=reg128#12%bot,<y23=reg128#4%bot # asm 2: vmull.u32 >r2=q15,<x01=d22,<y23=d6 vmull.u32 q15,d22,d6 # qhasm: r2[0,1] += x01[2] unsigned* y01[2]; r2[2,3] += x01[3] unsigned* y01[3] # asm 1: vmlal.u32 <r2=reg128#16,<x01=reg128#12%top,<y01=reg128#2%top # asm 2: vmlal.u32 <r2=q15,<x01=d23,<y01=d3 vmlal.u32 q15,d23,d3 # qhasm: r2[0,1] += x23[0] unsigned* y01[0]; r2[2,3] += x23[1] unsigned* y01[1] # asm 1: vmlal.u32 <r2=reg128#16,<x23=reg128#13%bot,<y01=reg128#2%bot # asm 2: vmlal.u32 <r2=q15,<x23=d24,<y01=d2 vmlal.u32 q15,d24,d2 # qhasm: r2[0,1] += x23[2] unsigned* _5y4[0]; r2[2,3] += x23[3] unsigned* _5y4[1] # asm 1: vmlal.u32 <r2=reg128#16,<x23=reg128#13%top,<_5y4=reg128#11%bot # asm 2: vmlal.u32 <r2=q15,<x23=d25,<_5y4=d20 vmlal.u32 q15,d25,d20 # qhasm: r2[0,1] += x4[0] unsigned* _5y23[2]; r2[2,3] += x4[1] unsigned* _5y23[3] # asm 1: vmlal.u32 <r2=reg128#16,<x4=reg128#14%bot,<_5y23=reg128#9%top # asm 2: vmlal.u32 <r2=q15,<x4=d26,<_5y23=d17 vmlal.u32 q15,d26,d17 # qhasm: r3[0,1] = x01[0] unsigned* y23[2]; r3[2,3] = x01[1] unsigned* y23[3] # asm 1: vmull.u32 >r3=reg128#9,<x01=reg128#12%bot,<y23=reg128#4%top # asm 2: vmull.u32 >r3=q8,<x01=d22,<y23=d7 vmull.u32 q8,d22,d7 # qhasm: r3[0,1] += x01[2] unsigned* y23[0]; r3[2,3] += x01[3] unsigned* y23[1] # asm 1: vmlal.u32 <r3=reg128#9,<x01=reg128#12%top,<y23=reg128#4%bot # asm 2: vmlal.u32 <r3=q8,<x01=d23,<y23=d6 vmlal.u32 q8,d23,d6 # qhasm: r3[0,1] += x23[0] unsigned* y01[2]; r3[2,3] += x23[1] unsigned* y01[3] # asm 1: vmlal.u32 <r3=reg128#9,<x23=reg128#13%bot,<y01=reg128#2%top # asm 2: vmlal.u32 <r3=q8,<x23=d24,<y01=d3 vmlal.u32 q8,d24,d3 # qhasm: r3[0,1] += x23[2] unsigned* y01[0]; r3[2,3] += x23[3] unsigned* y01[1] # asm 1: vmlal.u32 <r3=reg128#9,<x23=reg128#13%top,<y01=reg128#2%bot # asm 2: vmlal.u32 <r3=q8,<x23=d25,<y01=d2 vmlal.u32 q8,d25,d2 # qhasm: r3[0,1] += x4[0] unsigned* _5y4[0]; r3[2,3] += x4[1] unsigned* _5y4[1] # asm 1: vmlal.u32 <r3=reg128#9,<x4=reg128#14%bot,<_5y4=reg128#11%bot # asm 2: vmlal.u32 <r3=q8,<x4=d26,<_5y4=d20 vmlal.u32 q8,d26,d20 # qhasm: r4[0,1] = x01[0] unsigned* y4[0]; r4[2,3] = x01[1] unsigned* y4[1] # asm 1: vmull.u32 >r4=reg128#10,<x01=reg128#12%bot,<y4=reg128#10%bot # asm 2: vmull.u32 >r4=q9,<x01=d22,<y4=d18 vmull.u32 q9,d22,d18 # qhasm: r4[0,1] += x01[2] unsigned* y23[2]; r4[2,3] += x01[3] unsigned* y23[3] # asm 1: vmlal.u32 <r4=reg128#10,<x01=reg128#12%top,<y23=reg128#4%top # asm 2: vmlal.u32 <r4=q9,<x01=d23,<y23=d7 vmlal.u32 q9,d23,d7 # qhasm: r4[0,1] += x23[0] unsigned* y23[0]; r4[2,3] += x23[1] unsigned* y23[1] # asm 1: vmlal.u32 <r4=reg128#10,<x23=reg128#13%bot,<y23=reg128#4%bot # asm 2: vmlal.u32 <r4=q9,<x23=d24,<y23=d6 vmlal.u32 q9,d24,d6 # qhasm: r4[0,1] += x23[2] unsigned* y01[2]; r4[2,3] += x23[3] unsigned* y01[3] # asm 1: vmlal.u32 <r4=reg128#10,<x23=reg128#13%top,<y01=reg128#2%top # asm 2: vmlal.u32 <r4=q9,<x23=d25,<y01=d3 vmlal.u32 q9,d25,d3 # qhasm: r4[0,1] += x4[0] unsigned* y01[0]; r4[2,3] += x4[1] unsigned* y01[1] # asm 1: vmlal.u32 <r4=reg128#10,<x4=reg128#14%bot,<y01=reg128#2%bot # asm 2: vmlal.u32 <r4=q9,<x4=d26,<y01=d2 vmlal.u32 q9,d26,d2 # qhasm: 2x t1 = r0 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#2,<r0=reg128#15,#26 # asm 2: vshr.u64 >t1=q1,<r0=q14,#26 vshr.u64 q1,q14,#26 # qhasm: r0 &= mask # asm 1: vand >r0=reg128#4,<r0=reg128#15,<mask=reg128#1 # asm 2: vand >r0=q3,<r0=q14,<mask=q0 vand q3,q14,q0 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#2,<r1=reg128#3,<t1=reg128#2 # asm 2: vadd.i64 >r1=q1,<r1=q2,<t1=q1 vadd.i64 q1,q2,q1 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#3,<r3=reg128#9,#26 # asm 2: vshr.u64 >t4=q2,<r3=q8,#26 vshr.u64 q2,q8,#26 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#9,<r3=reg128#9,<mask=reg128#1 # asm 2: vand >r3=q8,<r3=q8,<mask=q0 vand q8,q8,q0 # qhasm: 2x r4 += t4 # asm 1: vadd.i64 >r4=reg128#3,<r4=reg128#10,<t4=reg128#3 # asm 2: vadd.i64 >r4=q2,<r4=q9,<t4=q2 vadd.i64 q2,q9,q2 # qhasm: 2x t2 = r1 unsigned>> 26 # asm 1: vshr.u64 >t2=reg128#10,<r1=reg128#2,#26 # asm 2: vshr.u64 >t2=q9,<r1=q1,#26 vshr.u64 q9,q1,#26 # qhasm: r1 &= mask # asm 1: vand >r1=reg128#2,<r1=reg128#2,<mask=reg128#1 # asm 2: vand >r1=q1,<r1=q1,<mask=q0 vand q1,q1,q0 # qhasm: 2x t0 = r4 unsigned>> 26 # asm 1: vshr.u64 >t0=reg128#11,<r4=reg128#3,#26 # asm 2: vshr.u64 >t0=q10,<r4=q2,#26 vshr.u64 q10,q2,#26 # qhasm: 2x r2 += t2 # asm 1: vadd.i64 >r2=reg128#10,<r2=reg128#16,<t2=reg128#10 # asm 2: vadd.i64 >r2=q9,<r2=q15,<t2=q9 vadd.i64 q9,q15,q9 # qhasm: r4 &= mask # asm 1: vand >r4=reg128#3,<r4=reg128#3,<mask=reg128#1 # asm 2: vand >r4=q2,<r4=q2,<mask=q0 vand q2,q2,q0 # qhasm: 2x r0 += t0 # asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#11 # asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q10 vadd.i64 q3,q3,q10 # qhasm: 2x t0 <<= 2 # asm 1: vshl.i64 >t0=reg128#11,<t0=reg128#11,#2 # asm 2: vshl.i64 >t0=q10,<t0=q10,#2 vshl.i64 q10,q10,#2 # qhasm: 2x t3 = r2 unsigned>> 26 # asm 1: vshr.u64 >t3=reg128#12,<r2=reg128#10,#26 # asm 2: vshr.u64 >t3=q11,<r2=q9,#26 vshr.u64 q11,q9,#26 # qhasm: 2x r0 += t0 # asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#11 # asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q10 vadd.i64 q3,q3,q10 # qhasm: x23 = r2 & mask # asm 1: vand >x23=reg128#10,<r2=reg128#10,<mask=reg128#1 # asm 2: vand >x23=q9,<r2=q9,<mask=q0 vand q9,q9,q0 # qhasm: 2x r3 += t3 # asm 1: vadd.i64 >r3=reg128#9,<r3=reg128#9,<t3=reg128#12 # asm 2: vadd.i64 >r3=q8,<r3=q8,<t3=q11 vadd.i64 q8,q8,q11 # qhasm: 2x t1 = r0 unsigned>> 26 # asm 1: vshr.u64 >t1=reg128#11,<r0=reg128#4,#26 # asm 2: vshr.u64 >t1=q10,<r0=q3,#26 vshr.u64 q10,q3,#26 # qhasm: x23 = x23[0,2,1,3] # asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top # asm 2: vtrn.32 <x23=d18,<x23=d19 vtrn.32 d18,d19 # qhasm: x01 = r0 & mask # asm 1: vand >x01=reg128#4,<r0=reg128#4,<mask=reg128#1 # asm 2: vand >x01=q3,<r0=q3,<mask=q0 vand q3,q3,q0 # qhasm: 2x r1 += t1 # asm 1: vadd.i64 >r1=reg128#2,<r1=reg128#2,<t1=reg128#11 # asm 2: vadd.i64 >r1=q1,<r1=q1,<t1=q10 vadd.i64 q1,q1,q10 # qhasm: 2x t4 = r3 unsigned>> 26 # asm 1: vshr.u64 >t4=reg128#11,<r3=reg128#9,#26 # asm 2: vshr.u64 >t4=q10,<r3=q8,#26 vshr.u64 q10,q8,#26 # qhasm: x01 = x01[0,2,1,3] # asm 1: vtrn.32 <x01=reg128#4%bot,<x01=reg128#4%top # asm 2: vtrn.32 <x01=d6,<x01=d7 vtrn.32 d6,d7 # qhasm: r3 &= mask # asm 1: vand >r3=reg128#1,<r3=reg128#9,<mask=reg128#1 # asm 2: vand >r3=q0,<r3=q8,<mask=q0 vand q0,q8,q0 # qhasm: r1 = r1[0,2,1,3] # asm 1: vtrn.32 <r1=reg128#2%bot,<r1=reg128#2%top # asm 2: vtrn.32 <r1=d2,<r1=d3 vtrn.32 d2,d3 # qhasm: 2x x4 = r4 + t4 # asm 1: vadd.i64 >x4=reg128#3,<r4=reg128#3,<t4=reg128#11 # asm 2: vadd.i64 >x4=q2,<r4=q2,<t4=q10 vadd.i64 q2,q2,q10 # qhasm: r3 = r3[0,2,1,3] # asm 1: vtrn.32 <r3=reg128#1%bot,<r3=reg128#1%top # asm 2: vtrn.32 <r3=d0,<r3=d1 vtrn.32 d0,d1 # qhasm: x01 = x01[0,1] r1[0,1] # asm 1: vext.32 <x01=reg128#4%top,<r1=reg128#2%bot,<r1=reg128#2%bot,#0 # asm 2: vext.32 <x01=d7,<r1=d2,<r1=d2,#0 vext.32 d7,d2,d2,#0 # qhasm: x23 = x23[0,1] r3[0,1] # asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#1%bot,<r3=reg128#1%bot,#0 # asm 2: vext.32 <x23=d19,<r3=d0,<r3=d0,#0 vext.32 d19,d0,d0,#0 # qhasm: x4 = x4[0,2,1,3] # asm 1: vtrn.32 <x4=reg128#3%bot,<x4=reg128#3%top # asm 2: vtrn.32 <x4=d4,<x4=d5 vtrn.32 d4,d5 # qhasm: mem128[input_0] aligned= x01;input_0+=16 # asm 1: vst1.8 {<x01=reg128#4%bot-<x01=reg128#4%top},[<input_0=int32#1,: 128]! # asm 2: vst1.8 {<x01=d6-<x01=d7},[<input_0=r0,: 128]! vst1.8 {d6-d7},[r0,: 128]! # qhasm: mem128[input_0] aligned= x23;input_0+=16 # asm 1: vst1.8 {<x23=reg128#10%bot-<x23=reg128#10%top},[<input_0=int32#1,: 128]! # asm 2: vst1.8 {<x23=d18-<x23=d19},[<input_0=r0,: 128]! vst1.8 {d18-d19},[r0,: 128]! # qhasm: mem64[input_0] aligned= x4[0] # asm 1: vst1.8 <x4=reg128#3%bot,[<input_0=int32#1,: 64] # asm 2: vst1.8 <x4=d4,[<input_0=r0,: 64] vst1.8 d4,[r0,: 64] # qhasm: return add sp,sp,#0 bx lr #endif /* !OPENSSL_NO_ASM && OPENSSL_ARM && __ELF__ */

j4yc3-mw/Viren

41,612

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/ring-0.17.8/crypto/curve25519/asm/x25519-asm-arm.S

/* Copyright (c) 2015, Google Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /* This file is taken from crypto_scalarmult/curve25519/neon2/scalarmult.s in * SUPERCOP 20141124 (http://bench.cr.yp.to/supercop.html). That code is public * domain licensed but the standard ISC license is included above to keep * licensing simple. */ #include <ring-core/asm_base.h> #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__) .fpu neon .text .align 4 .global x25519_NEON .hidden x25519_NEON .type x25519_NEON, %function x25519_NEON: vpush {q4,q5,q6,q7} mov r12,sp sub sp,sp,#736 and sp,sp,#0xffffffe0 strd r4,[sp,#0] strd r6,[sp,#8] strd r8,[sp,#16] strd r10,[sp,#24] str r12,[sp,#480] str r14,[sp,#484] mov r0,r0 mov r1,r1 mov r2,r2 add r3,sp,#32 ldr r4,=0 ldr r5,=254 vmov.i32 q0,#1 vshr.u64 q1,q0,#7 vshr.u64 q0,q0,#8 vmov.i32 d4,#19 vmov.i32 d5,#38 add r6,sp,#512 vst1.8 {d2-d3},[r6,: 128] add r6,sp,#528 vst1.8 {d0-d1},[r6,: 128] add r6,sp,#544 vst1.8 {d4-d5},[r6,: 128] add r6,r3,#0 vmov.i32 q2,#0 vst1.8 {d4-d5},[r6,: 128]! vst1.8 {d4-d5},[r6,: 128]! vst1.8 d4,[r6,: 64] add r6,r3,#0 ldr r7,=960 sub r7,r7,#2 neg r7,r7 sub r7,r7,r7,LSL #7 str r7,[r6] add r6,sp,#704 vld1.8 {d4-d5},[r1]! vld1.8 {d6-d7},[r1] vst1.8 {d4-d5},[r6,: 128]! vst1.8 {d6-d7},[r6,: 128] sub r1,r6,#16 ldrb r6,[r1] and r6,r6,#248 strb r6,[r1] ldrb r6,[r1,#31] and r6,r6,#127 orr r6,r6,#64 strb r6,[r1,#31] vmov.i64 q2,#0xffffffff vshr.u64 q3,q2,#7 vshr.u64 q2,q2,#6 vld1.8 {d8},[r2] vld1.8 {d10},[r2] add r2,r2,#6 vld1.8 {d12},[r2] vld1.8 {d14},[r2] add r2,r2,#6 vld1.8 {d16},[r2] add r2,r2,#4 vld1.8 {d18},[r2] vld1.8 {d20},[r2] add r2,r2,#6 vld1.8 {d22},[r2] add r2,r2,#2 vld1.8 {d24},[r2] vld1.8 {d26},[r2] vshr.u64 q5,q5,#26 vshr.u64 q6,q6,#3 vshr.u64 q7,q7,#29 vshr.u64 q8,q8,#6 vshr.u64 q10,q10,#25 vshr.u64 q11,q11,#3 vshr.u64 q12,q12,#12 vshr.u64 q13,q13,#38 vand q4,q4,q2 vand q6,q6,q2 vand q8,q8,q2 vand q10,q10,q2 vand q2,q12,q2 vand q5,q5,q3 vand q7,q7,q3 vand q9,q9,q3 vand q11,q11,q3 vand q3,q13,q3 add r2,r3,#48 vadd.i64 q12,q4,q1 vadd.i64 q13,q10,q1 vshr.s64 q12,q12,#26 vshr.s64 q13,q13,#26 vadd.i64 q5,q5,q12 vshl.i64 q12,q12,#26 vadd.i64 q14,q5,q0 vadd.i64 q11,q11,q13 vshl.i64 q13,q13,#26 vadd.i64 q15,q11,q0 vsub.i64 q4,q4,q12 vshr.s64 q12,q14,#25 vsub.i64 q10,q10,q13 vshr.s64 q13,q15,#25 vadd.i64 q6,q6,q12 vshl.i64 q12,q12,#25 vadd.i64 q14,q6,q1 vadd.i64 q2,q2,q13 vsub.i64 q5,q5,q12 vshr.s64 q12,q14,#26 vshl.i64 q13,q13,#25 vadd.i64 q14,q2,q1 vadd.i64 q7,q7,q12 vshl.i64 q12,q12,#26 vadd.i64 q15,q7,q0 vsub.i64 q11,q11,q13 vshr.s64 q13,q14,#26 vsub.i64 q6,q6,q12 vshr.s64 q12,q15,#25 vadd.i64 q3,q3,q13 vshl.i64 q13,q13,#26 vadd.i64 q14,q3,q0 vadd.i64 q8,q8,q12 vshl.i64 q12,q12,#25 vadd.i64 q15,q8,q1 add r2,r2,#8 vsub.i64 q2,q2,q13 vshr.s64 q13,q14,#25 vsub.i64 q7,q7,q12 vshr.s64 q12,q15,#26 vadd.i64 q14,q13,q13 vadd.i64 q9,q9,q12 vtrn.32 d12,d14 vshl.i64 q12,q12,#26 vtrn.32 d13,d15 vadd.i64 q0,q9,q0 vadd.i64 q4,q4,q14 vst1.8 d12,[r2,: 64]! vshl.i64 q6,q13,#4 vsub.i64 q7,q8,q12 vshr.s64 q0,q0,#25 vadd.i64 q4,q4,q6 vadd.i64 q6,q10,q0 vshl.i64 q0,q0,#25 vadd.i64 q8,q6,q1 vadd.i64 q4,q4,q13 vshl.i64 q10,q13,#25 vadd.i64 q1,q4,q1 vsub.i64 q0,q9,q0 vshr.s64 q8,q8,#26 vsub.i64 q3,q3,q10 vtrn.32 d14,d0 vshr.s64 q1,q1,#26 vtrn.32 d15,d1 vadd.i64 q0,q11,q8 vst1.8 d14,[r2,: 64] vshl.i64 q7,q8,#26 vadd.i64 q5,q5,q1 vtrn.32 d4,d6 vshl.i64 q1,q1,#26 vtrn.32 d5,d7 vsub.i64 q3,q6,q7 add r2,r2,#16 vsub.i64 q1,q4,q1 vst1.8 d4,[r2,: 64] vtrn.32 d6,d0 vtrn.32 d7,d1 sub r2,r2,#8 vtrn.32 d2,d10 vtrn.32 d3,d11 vst1.8 d6,[r2,: 64] sub r2,r2,#24 vst1.8 d2,[r2,: 64] add r2,r3,#96 vmov.i32 q0,#0 vmov.i64 d2,#0xff vmov.i64 d3,#0 vshr.u32 q1,q1,#7 vst1.8 {d2-d3},[r2,: 128]! vst1.8 {d0-d1},[r2,: 128]! vst1.8 d0,[r2,: 64] add r2,r3,#144 vmov.i32 q0,#0 vst1.8 {d0-d1},[r2,: 128]! vst1.8 {d0-d1},[r2,: 128]! vst1.8 d0,[r2,: 64] add r2,r3,#240 vmov.i32 q0,#0 vmov.i64 d2,#0xff vmov.i64 d3,#0 vshr.u32 q1,q1,#7 vst1.8 {d2-d3},[r2,: 128]! vst1.8 {d0-d1},[r2,: 128]! vst1.8 d0,[r2,: 64] add r2,r3,#48 add r6,r3,#192 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d4},[r2,: 64] vst1.8 {d0-d1},[r6,: 128]! vst1.8 {d2-d3},[r6,: 128]! vst1.8 d4,[r6,: 64] ._mainloop: mov r2,r5,LSR #3 and r6,r5,#7 ldrb r2,[r1,r2] mov r2,r2,LSR r6 and r2,r2,#1 str r5,[sp,#488] eor r4,r4,r2 str r2,[sp,#492] neg r2,r4 add r4,r3,#96 add r5,r3,#192 add r6,r3,#144 vld1.8 {d8-d9},[r4,: 128]! add r7,r3,#240 vld1.8 {d10-d11},[r5,: 128]! veor q6,q4,q5 vld1.8 {d14-d15},[r6,: 128]! vdup.i32 q8,r2 vld1.8 {d18-d19},[r7,: 128]! veor q10,q7,q9 vld1.8 {d22-d23},[r4,: 128]! vand q6,q6,q8 vld1.8 {d24-d25},[r5,: 128]! vand q10,q10,q8 vld1.8 {d26-d27},[r6,: 128]! veor q4,q4,q6 vld1.8 {d28-d29},[r7,: 128]! veor q5,q5,q6 vld1.8 {d0},[r4,: 64] veor q6,q7,q10 vld1.8 {d2},[r5,: 64] veor q7,q9,q10 vld1.8 {d4},[r6,: 64] veor q9,q11,q12 vld1.8 {d6},[r7,: 64] veor q10,q0,q1 sub r2,r4,#32 vand q9,q9,q8 sub r4,r5,#32 vand q10,q10,q8 sub r5,r6,#32 veor q11,q11,q9 sub r6,r7,#32 veor q0,q0,q10 veor q9,q12,q9 veor q1,q1,q10 veor q10,q13,q14 veor q12,q2,q3 vand q10,q10,q8 vand q8,q12,q8 veor q12,q13,q10 veor q2,q2,q8 veor q10,q14,q10 veor q3,q3,q8 vadd.i32 q8,q4,q6 vsub.i32 q4,q4,q6 vst1.8 {d16-d17},[r2,: 128]! vadd.i32 q6,q11,q12 vst1.8 {d8-d9},[r5,: 128]! vsub.i32 q4,q11,q12 vst1.8 {d12-d13},[r2,: 128]! vadd.i32 q6,q0,q2 vst1.8 {d8-d9},[r5,: 128]! vsub.i32 q0,q0,q2 vst1.8 d12,[r2,: 64] vadd.i32 q2,q5,q7 vst1.8 d0,[r5,: 64] vsub.i32 q0,q5,q7 vst1.8 {d4-d5},[r4,: 128]! vadd.i32 q2,q9,q10 vst1.8 {d0-d1},[r6,: 128]! vsub.i32 q0,q9,q10 vst1.8 {d4-d5},[r4,: 128]! vadd.i32 q2,q1,q3 vst1.8 {d0-d1},[r6,: 128]! vsub.i32 q0,q1,q3 vst1.8 d4,[r4,: 64] vst1.8 d0,[r6,: 64] add r2,sp,#544 add r4,r3,#96 add r5,r3,#144 vld1.8 {d0-d1},[r2,: 128] vld1.8 {d2-d3},[r4,: 128]! vld1.8 {d4-d5},[r5,: 128]! vzip.i32 q1,q2 vld1.8 {d6-d7},[r4,: 128]! vld1.8 {d8-d9},[r5,: 128]! vshl.i32 q5,q1,#1 vzip.i32 q3,q4 vshl.i32 q6,q2,#1 vld1.8 {d14},[r4,: 64] vshl.i32 q8,q3,#1 vld1.8 {d15},[r5,: 64] vshl.i32 q9,q4,#1 vmul.i32 d21,d7,d1 vtrn.32 d14,d15 vmul.i32 q11,q4,q0 vmul.i32 q0,q7,q0 vmull.s32 q12,d2,d2 vmlal.s32 q12,d11,d1 vmlal.s32 q12,d12,d0 vmlal.s32 q12,d13,d23 vmlal.s32 q12,d16,d22 vmlal.s32 q12,d7,d21 vmull.s32 q10,d2,d11 vmlal.s32 q10,d4,d1 vmlal.s32 q10,d13,d0 vmlal.s32 q10,d6,d23 vmlal.s32 q10,d17,d22 vmull.s32 q13,d10,d4 vmlal.s32 q13,d11,d3 vmlal.s32 q13,d13,d1 vmlal.s32 q13,d16,d0 vmlal.s32 q13,d17,d23 vmlal.s32 q13,d8,d22 vmull.s32 q1,d10,d5 vmlal.s32 q1,d11,d4 vmlal.s32 q1,d6,d1 vmlal.s32 q1,d17,d0 vmlal.s32 q1,d8,d23 vmull.s32 q14,d10,d6 vmlal.s32 q14,d11,d13 vmlal.s32 q14,d4,d4 vmlal.s32 q14,d17,d1 vmlal.s32 q14,d18,d0 vmlal.s32 q14,d9,d23 vmull.s32 q11,d10,d7 vmlal.s32 q11,d11,d6 vmlal.s32 q11,d12,d5 vmlal.s32 q11,d8,d1 vmlal.s32 q11,d19,d0 vmull.s32 q15,d10,d8 vmlal.s32 q15,d11,d17 vmlal.s32 q15,d12,d6 vmlal.s32 q15,d13,d5 vmlal.s32 q15,d19,d1 vmlal.s32 q15,d14,d0 vmull.s32 q2,d10,d9 vmlal.s32 q2,d11,d8 vmlal.s32 q2,d12,d7 vmlal.s32 q2,d13,d6 vmlal.s32 q2,d14,d1 vmull.s32 q0,d15,d1 vmlal.s32 q0,d10,d14 vmlal.s32 q0,d11,d19 vmlal.s32 q0,d12,d8 vmlal.s32 q0,d13,d17 vmlal.s32 q0,d6,d6 add r2,sp,#512 vld1.8 {d18-d19},[r2,: 128] vmull.s32 q3,d16,d7 vmlal.s32 q3,d10,d15 vmlal.s32 q3,d11,d14 vmlal.s32 q3,d12,d9 vmlal.s32 q3,d13,d8 add r2,sp,#528 vld1.8 {d8-d9},[r2,: 128] vadd.i64 q5,q12,q9 vadd.i64 q6,q15,q9 vshr.s64 q5,q5,#26 vshr.s64 q6,q6,#26 vadd.i64 q7,q10,q5 vshl.i64 q5,q5,#26 vadd.i64 q8,q7,q4 vadd.i64 q2,q2,q6 vshl.i64 q6,q6,#26 vadd.i64 q10,q2,q4 vsub.i64 q5,q12,q5 vshr.s64 q8,q8,#25 vsub.i64 q6,q15,q6 vshr.s64 q10,q10,#25 vadd.i64 q12,q13,q8 vshl.i64 q8,q8,#25 vadd.i64 q13,q12,q9 vadd.i64 q0,q0,q10 vsub.i64 q7,q7,q8 vshr.s64 q8,q13,#26 vshl.i64 q10,q10,#25 vadd.i64 q13,q0,q9 vadd.i64 q1,q1,q8 vshl.i64 q8,q8,#26 vadd.i64 q15,q1,q4 vsub.i64 q2,q2,q10 vshr.s64 q10,q13,#26 vsub.i64 q8,q12,q8 vshr.s64 q12,q15,#25 vadd.i64 q3,q3,q10 vshl.i64 q10,q10,#26 vadd.i64 q13,q3,q4 vadd.i64 q14,q14,q12 add r2,r3,#288 vshl.i64 q12,q12,#25 add r4,r3,#336 vadd.i64 q15,q14,q9 add r2,r2,#8 vsub.i64 q0,q0,q10 add r4,r4,#8 vshr.s64 q10,q13,#25 vsub.i64 q1,q1,q12 vshr.s64 q12,q15,#26 vadd.i64 q13,q10,q10 vadd.i64 q11,q11,q12 vtrn.32 d16,d2 vshl.i64 q12,q12,#26 vtrn.32 d17,d3 vadd.i64 q1,q11,q4 vadd.i64 q4,q5,q13 vst1.8 d16,[r2,: 64]! vshl.i64 q5,q10,#4 vst1.8 d17,[r4,: 64]! vsub.i64 q8,q14,q12 vshr.s64 q1,q1,#25 vadd.i64 q4,q4,q5 vadd.i64 q5,q6,q1 vshl.i64 q1,q1,#25 vadd.i64 q6,q5,q9 vadd.i64 q4,q4,q10 vshl.i64 q10,q10,#25 vadd.i64 q9,q4,q9 vsub.i64 q1,q11,q1 vshr.s64 q6,q6,#26 vsub.i64 q3,q3,q10 vtrn.32 d16,d2 vshr.s64 q9,q9,#26 vtrn.32 d17,d3 vadd.i64 q1,q2,q6 vst1.8 d16,[r2,: 64] vshl.i64 q2,q6,#26 vst1.8 d17,[r4,: 64] vadd.i64 q6,q7,q9 vtrn.32 d0,d6 vshl.i64 q7,q9,#26 vtrn.32 d1,d7 vsub.i64 q2,q5,q2 add r2,r2,#16 vsub.i64 q3,q4,q7 vst1.8 d0,[r2,: 64] add r4,r4,#16 vst1.8 d1,[r4,: 64] vtrn.32 d4,d2 vtrn.32 d5,d3 sub r2,r2,#8 sub r4,r4,#8 vtrn.32 d6,d12 vtrn.32 d7,d13 vst1.8 d4,[r2,: 64] vst1.8 d5,[r4,: 64] sub r2,r2,#24 sub r4,r4,#24 vst1.8 d6,[r2,: 64] vst1.8 d7,[r4,: 64] add r2,r3,#240 add r4,r3,#96 vld1.8 {d0-d1},[r4,: 128]! vld1.8 {d2-d3},[r4,: 128]! vld1.8 {d4},[r4,: 64] add r4,r3,#144 vld1.8 {d6-d7},[r4,: 128]! vtrn.32 q0,q3 vld1.8 {d8-d9},[r4,: 128]! vshl.i32 q5,q0,#4 vtrn.32 q1,q4 vshl.i32 q6,q3,#4 vadd.i32 q5,q5,q0 vadd.i32 q6,q6,q3 vshl.i32 q7,q1,#4 vld1.8 {d5},[r4,: 64] vshl.i32 q8,q4,#4 vtrn.32 d4,d5 vadd.i32 q7,q7,q1 vadd.i32 q8,q8,q4 vld1.8 {d18-d19},[r2,: 128]! vshl.i32 q10,q2,#4 vld1.8 {d22-d23},[r2,: 128]! vadd.i32 q10,q10,q2 vld1.8 {d24},[r2,: 64] vadd.i32 q5,q5,q0 add r2,r3,#192 vld1.8 {d26-d27},[r2,: 128]! vadd.i32 q6,q6,q3 vld1.8 {d28-d29},[r2,: 128]! vadd.i32 q8,q8,q4 vld1.8 {d25},[r2,: 64] vadd.i32 q10,q10,q2 vtrn.32 q9,q13 vadd.i32 q7,q7,q1 vadd.i32 q5,q5,q0 vtrn.32 q11,q14 vadd.i32 q6,q6,q3 add r2,sp,#560 vadd.i32 q10,q10,q2 vtrn.32 d24,d25 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q6,q13,#1 add r2,sp,#576 vst1.8 {d20-d21},[r2,: 128] vshl.i32 q10,q14,#1 add r2,sp,#592 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q15,q12,#1 vadd.i32 q8,q8,q4 vext.32 d10,d31,d30,#0 vadd.i32 q7,q7,q1 add r2,sp,#608 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q8,d18,d5 vmlal.s32 q8,d26,d4 vmlal.s32 q8,d19,d9 vmlal.s32 q8,d27,d3 vmlal.s32 q8,d22,d8 vmlal.s32 q8,d28,d2 vmlal.s32 q8,d23,d7 vmlal.s32 q8,d29,d1 vmlal.s32 q8,d24,d6 vmlal.s32 q8,d25,d0 add r2,sp,#624 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q2,d18,d4 vmlal.s32 q2,d12,d9 vmlal.s32 q2,d13,d8 vmlal.s32 q2,d19,d3 vmlal.s32 q2,d22,d2 vmlal.s32 q2,d23,d1 vmlal.s32 q2,d24,d0 add r2,sp,#640 vst1.8 {d20-d21},[r2,: 128] vmull.s32 q7,d18,d9 vmlal.s32 q7,d26,d3 vmlal.s32 q7,d19,d8 vmlal.s32 q7,d27,d2 vmlal.s32 q7,d22,d7 vmlal.s32 q7,d28,d1 vmlal.s32 q7,d23,d6 vmlal.s32 q7,d29,d0 add r2,sp,#656 vst1.8 {d10-d11},[r2,: 128] vmull.s32 q5,d18,d3 vmlal.s32 q5,d19,d2 vmlal.s32 q5,d22,d1 vmlal.s32 q5,d23,d0 vmlal.s32 q5,d12,d8 add r2,sp,#672 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q4,d18,d8 vmlal.s32 q4,d26,d2 vmlal.s32 q4,d19,d7 vmlal.s32 q4,d27,d1 vmlal.s32 q4,d22,d6 vmlal.s32 q4,d28,d0 vmull.s32 q8,d18,d7 vmlal.s32 q8,d26,d1 vmlal.s32 q8,d19,d6 vmlal.s32 q8,d27,d0 add r2,sp,#576 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q7,d24,d21 vmlal.s32 q7,d25,d20 vmlal.s32 q4,d23,d21 vmlal.s32 q4,d29,d20 vmlal.s32 q8,d22,d21 vmlal.s32 q8,d28,d20 vmlal.s32 q5,d24,d20 add r2,sp,#576 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q7,d18,d6 vmlal.s32 q7,d26,d0 add r2,sp,#656 vld1.8 {d30-d31},[r2,: 128] vmlal.s32 q2,d30,d21 vmlal.s32 q7,d19,d21 vmlal.s32 q7,d27,d20 add r2,sp,#624 vld1.8 {d26-d27},[r2,: 128] vmlal.s32 q4,d25,d27 vmlal.s32 q8,d29,d27 vmlal.s32 q8,d25,d26 vmlal.s32 q7,d28,d27 vmlal.s32 q7,d29,d26 add r2,sp,#608 vld1.8 {d28-d29},[r2,: 128] vmlal.s32 q4,d24,d29 vmlal.s32 q8,d23,d29 vmlal.s32 q8,d24,d28 vmlal.s32 q7,d22,d29 vmlal.s32 q7,d23,d28 add r2,sp,#608 vst1.8 {d8-d9},[r2,: 128] add r2,sp,#560 vld1.8 {d8-d9},[r2,: 128] vmlal.s32 q7,d24,d9 vmlal.s32 q7,d25,d31 vmull.s32 q1,d18,d2 vmlal.s32 q1,d19,d1 vmlal.s32 q1,d22,d0 vmlal.s32 q1,d24,d27 vmlal.s32 q1,d23,d20 vmlal.s32 q1,d12,d7 vmlal.s32 q1,d13,d6 vmull.s32 q6,d18,d1 vmlal.s32 q6,d19,d0 vmlal.s32 q6,d23,d27 vmlal.s32 q6,d22,d20 vmlal.s32 q6,d24,d26 vmull.s32 q0,d18,d0 vmlal.s32 q0,d22,d27 vmlal.s32 q0,d23,d26 vmlal.s32 q0,d24,d31 vmlal.s32 q0,d19,d20 add r2,sp,#640 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q2,d18,d7 vmlal.s32 q2,d19,d6 vmlal.s32 q5,d18,d6 vmlal.s32 q5,d19,d21 vmlal.s32 q1,d18,d21 vmlal.s32 q1,d19,d29 vmlal.s32 q0,d18,d28 vmlal.s32 q0,d19,d9 vmlal.s32 q6,d18,d29 vmlal.s32 q6,d19,d28 add r2,sp,#592 vld1.8 {d18-d19},[r2,: 128] add r2,sp,#512 vld1.8 {d22-d23},[r2,: 128] vmlal.s32 q5,d19,d7 vmlal.s32 q0,d18,d21 vmlal.s32 q0,d19,d29 vmlal.s32 q6,d18,d6 add r2,sp,#528 vld1.8 {d6-d7},[r2,: 128] vmlal.s32 q6,d19,d21 add r2,sp,#576 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q0,d30,d8 add r2,sp,#672 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q5,d30,d29 add r2,sp,#608 vld1.8 {d24-d25},[r2,: 128] vmlal.s32 q1,d30,d28 vadd.i64 q13,q0,q11 vadd.i64 q14,q5,q11 vmlal.s32 q6,d30,d9 vshr.s64 q4,q13,#26 vshr.s64 q13,q14,#26 vadd.i64 q7,q7,q4 vshl.i64 q4,q4,#26 vadd.i64 q14,q7,q3 vadd.i64 q9,q9,q13 vshl.i64 q13,q13,#26 vadd.i64 q15,q9,q3 vsub.i64 q0,q0,q4 vshr.s64 q4,q14,#25 vsub.i64 q5,q5,q13 vshr.s64 q13,q15,#25 vadd.i64 q6,q6,q4 vshl.i64 q4,q4,#25 vadd.i64 q14,q6,q11 vadd.i64 q2,q2,q13 vsub.i64 q4,q7,q4 vshr.s64 q7,q14,#26 vshl.i64 q13,q13,#25 vadd.i64 q14,q2,q11 vadd.i64 q8,q8,q7 vshl.i64 q7,q7,#26 vadd.i64 q15,q8,q3 vsub.i64 q9,q9,q13 vshr.s64 q13,q14,#26 vsub.i64 q6,q6,q7 vshr.s64 q7,q15,#25 vadd.i64 q10,q10,q13 vshl.i64 q13,q13,#26 vadd.i64 q14,q10,q3 vadd.i64 q1,q1,q7 add r2,r3,#144 vshl.i64 q7,q7,#25 add r4,r3,#96 vadd.i64 q15,q1,q11 add r2,r2,#8 vsub.i64 q2,q2,q13 add r4,r4,#8 vshr.s64 q13,q14,#25 vsub.i64 q7,q8,q7 vshr.s64 q8,q15,#26 vadd.i64 q14,q13,q13 vadd.i64 q12,q12,q8 vtrn.32 d12,d14 vshl.i64 q8,q8,#26 vtrn.32 d13,d15 vadd.i64 q3,q12,q3 vadd.i64 q0,q0,q14 vst1.8 d12,[r2,: 64]! vshl.i64 q7,q13,#4 vst1.8 d13,[r4,: 64]! vsub.i64 q1,q1,q8 vshr.s64 q3,q3,#25 vadd.i64 q0,q0,q7 vadd.i64 q5,q5,q3 vshl.i64 q3,q3,#25 vadd.i64 q6,q5,q11 vadd.i64 q0,q0,q13 vshl.i64 q7,q13,#25 vadd.i64 q8,q0,q11 vsub.i64 q3,q12,q3 vshr.s64 q6,q6,#26 vsub.i64 q7,q10,q7 vtrn.32 d2,d6 vshr.s64 q8,q8,#26 vtrn.32 d3,d7 vadd.i64 q3,q9,q6 vst1.8 d2,[r2,: 64] vshl.i64 q6,q6,#26 vst1.8 d3,[r4,: 64] vadd.i64 q1,q4,q8 vtrn.32 d4,d14 vshl.i64 q4,q8,#26 vtrn.32 d5,d15 vsub.i64 q5,q5,q6 add r2,r2,#16 vsub.i64 q0,q0,q4 vst1.8 d4,[r2,: 64] add r4,r4,#16 vst1.8 d5,[r4,: 64] vtrn.32 d10,d6 vtrn.32 d11,d7 sub r2,r2,#8 sub r4,r4,#8 vtrn.32 d0,d2 vtrn.32 d1,d3 vst1.8 d10,[r2,: 64] vst1.8 d11,[r4,: 64] sub r2,r2,#24 sub r4,r4,#24 vst1.8 d0,[r2,: 64] vst1.8 d1,[r4,: 64] add r2,r3,#288 add r4,r3,#336 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r4,: 128]! vsub.i32 q0,q0,q1 vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d4-d5},[r4,: 128]! vsub.i32 q1,q1,q2 add r5,r3,#240 vld1.8 {d4},[r2,: 64] vld1.8 {d6},[r4,: 64] vsub.i32 q2,q2,q3 vst1.8 {d0-d1},[r5,: 128]! vst1.8 {d2-d3},[r5,: 128]! vst1.8 d4,[r5,: 64] add r2,r3,#144 add r4,r3,#96 add r5,r3,#144 add r6,r3,#192 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r4,: 128]! vsub.i32 q2,q0,q1 vadd.i32 q0,q0,q1 vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d6-d7},[r4,: 128]! vsub.i32 q4,q1,q3 vadd.i32 q1,q1,q3 vld1.8 {d6},[r2,: 64] vld1.8 {d10},[r4,: 64] vsub.i32 q6,q3,q5 vadd.i32 q3,q3,q5 vst1.8 {d4-d5},[r5,: 128]! vst1.8 {d0-d1},[r6,: 128]! vst1.8 {d8-d9},[r5,: 128]! vst1.8 {d2-d3},[r6,: 128]! vst1.8 d12,[r5,: 64] vst1.8 d6,[r6,: 64] add r2,r3,#0 add r4,r3,#240 vld1.8 {d0-d1},[r4,: 128]! vld1.8 {d2-d3},[r4,: 128]! vld1.8 {d4},[r4,: 64] add r4,r3,#336 vld1.8 {d6-d7},[r4,: 128]! vtrn.32 q0,q3 vld1.8 {d8-d9},[r4,: 128]! vshl.i32 q5,q0,#4 vtrn.32 q1,q4 vshl.i32 q6,q3,#4 vadd.i32 q5,q5,q0 vadd.i32 q6,q6,q3 vshl.i32 q7,q1,#4 vld1.8 {d5},[r4,: 64] vshl.i32 q8,q4,#4 vtrn.32 d4,d5 vadd.i32 q7,q7,q1 vadd.i32 q8,q8,q4 vld1.8 {d18-d19},[r2,: 128]! vshl.i32 q10,q2,#4 vld1.8 {d22-d23},[r2,: 128]! vadd.i32 q10,q10,q2 vld1.8 {d24},[r2,: 64] vadd.i32 q5,q5,q0 add r2,r3,#288 vld1.8 {d26-d27},[r2,: 128]! vadd.i32 q6,q6,q3 vld1.8 {d28-d29},[r2,: 128]! vadd.i32 q8,q8,q4 vld1.8 {d25},[r2,: 64] vadd.i32 q10,q10,q2 vtrn.32 q9,q13 vadd.i32 q7,q7,q1 vadd.i32 q5,q5,q0 vtrn.32 q11,q14 vadd.i32 q6,q6,q3 add r2,sp,#560 vadd.i32 q10,q10,q2 vtrn.32 d24,d25 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q6,q13,#1 add r2,sp,#576 vst1.8 {d20-d21},[r2,: 128] vshl.i32 q10,q14,#1 add r2,sp,#592 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q15,q12,#1 vadd.i32 q8,q8,q4 vext.32 d10,d31,d30,#0 vadd.i32 q7,q7,q1 add r2,sp,#608 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q8,d18,d5 vmlal.s32 q8,d26,d4 vmlal.s32 q8,d19,d9 vmlal.s32 q8,d27,d3 vmlal.s32 q8,d22,d8 vmlal.s32 q8,d28,d2 vmlal.s32 q8,d23,d7 vmlal.s32 q8,d29,d1 vmlal.s32 q8,d24,d6 vmlal.s32 q8,d25,d0 add r2,sp,#624 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q2,d18,d4 vmlal.s32 q2,d12,d9 vmlal.s32 q2,d13,d8 vmlal.s32 q2,d19,d3 vmlal.s32 q2,d22,d2 vmlal.s32 q2,d23,d1 vmlal.s32 q2,d24,d0 add r2,sp,#640 vst1.8 {d20-d21},[r2,: 128] vmull.s32 q7,d18,d9 vmlal.s32 q7,d26,d3 vmlal.s32 q7,d19,d8 vmlal.s32 q7,d27,d2 vmlal.s32 q7,d22,d7 vmlal.s32 q7,d28,d1 vmlal.s32 q7,d23,d6 vmlal.s32 q7,d29,d0 add r2,sp,#656 vst1.8 {d10-d11},[r2,: 128] vmull.s32 q5,d18,d3 vmlal.s32 q5,d19,d2 vmlal.s32 q5,d22,d1 vmlal.s32 q5,d23,d0 vmlal.s32 q5,d12,d8 add r2,sp,#672 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q4,d18,d8 vmlal.s32 q4,d26,d2 vmlal.s32 q4,d19,d7 vmlal.s32 q4,d27,d1 vmlal.s32 q4,d22,d6 vmlal.s32 q4,d28,d0 vmull.s32 q8,d18,d7 vmlal.s32 q8,d26,d1 vmlal.s32 q8,d19,d6 vmlal.s32 q8,d27,d0 add r2,sp,#576 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q7,d24,d21 vmlal.s32 q7,d25,d20 vmlal.s32 q4,d23,d21 vmlal.s32 q4,d29,d20 vmlal.s32 q8,d22,d21 vmlal.s32 q8,d28,d20 vmlal.s32 q5,d24,d20 add r2,sp,#576 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q7,d18,d6 vmlal.s32 q7,d26,d0 add r2,sp,#656 vld1.8 {d30-d31},[r2,: 128] vmlal.s32 q2,d30,d21 vmlal.s32 q7,d19,d21 vmlal.s32 q7,d27,d20 add r2,sp,#624 vld1.8 {d26-d27},[r2,: 128] vmlal.s32 q4,d25,d27 vmlal.s32 q8,d29,d27 vmlal.s32 q8,d25,d26 vmlal.s32 q7,d28,d27 vmlal.s32 q7,d29,d26 add r2,sp,#608 vld1.8 {d28-d29},[r2,: 128] vmlal.s32 q4,d24,d29 vmlal.s32 q8,d23,d29 vmlal.s32 q8,d24,d28 vmlal.s32 q7,d22,d29 vmlal.s32 q7,d23,d28 add r2,sp,#608 vst1.8 {d8-d9},[r2,: 128] add r2,sp,#560 vld1.8 {d8-d9},[r2,: 128] vmlal.s32 q7,d24,d9 vmlal.s32 q7,d25,d31 vmull.s32 q1,d18,d2 vmlal.s32 q1,d19,d1 vmlal.s32 q1,d22,d0 vmlal.s32 q1,d24,d27 vmlal.s32 q1,d23,d20 vmlal.s32 q1,d12,d7 vmlal.s32 q1,d13,d6 vmull.s32 q6,d18,d1 vmlal.s32 q6,d19,d0 vmlal.s32 q6,d23,d27 vmlal.s32 q6,d22,d20 vmlal.s32 q6,d24,d26 vmull.s32 q0,d18,d0 vmlal.s32 q0,d22,d27 vmlal.s32 q0,d23,d26 vmlal.s32 q0,d24,d31 vmlal.s32 q0,d19,d20 add r2,sp,#640 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q2,d18,d7 vmlal.s32 q2,d19,d6 vmlal.s32 q5,d18,d6 vmlal.s32 q5,d19,d21 vmlal.s32 q1,d18,d21 vmlal.s32 q1,d19,d29 vmlal.s32 q0,d18,d28 vmlal.s32 q0,d19,d9 vmlal.s32 q6,d18,d29 vmlal.s32 q6,d19,d28 add r2,sp,#592 vld1.8 {d18-d19},[r2,: 128] add r2,sp,#512 vld1.8 {d22-d23},[r2,: 128] vmlal.s32 q5,d19,d7 vmlal.s32 q0,d18,d21 vmlal.s32 q0,d19,d29 vmlal.s32 q6,d18,d6 add r2,sp,#528 vld1.8 {d6-d7},[r2,: 128] vmlal.s32 q6,d19,d21 add r2,sp,#576 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q0,d30,d8 add r2,sp,#672 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q5,d30,d29 add r2,sp,#608 vld1.8 {d24-d25},[r2,: 128] vmlal.s32 q1,d30,d28 vadd.i64 q13,q0,q11 vadd.i64 q14,q5,q11 vmlal.s32 q6,d30,d9 vshr.s64 q4,q13,#26 vshr.s64 q13,q14,#26 vadd.i64 q7,q7,q4 vshl.i64 q4,q4,#26 vadd.i64 q14,q7,q3 vadd.i64 q9,q9,q13 vshl.i64 q13,q13,#26 vadd.i64 q15,q9,q3 vsub.i64 q0,q0,q4 vshr.s64 q4,q14,#25 vsub.i64 q5,q5,q13 vshr.s64 q13,q15,#25 vadd.i64 q6,q6,q4 vshl.i64 q4,q4,#25 vadd.i64 q14,q6,q11 vadd.i64 q2,q2,q13 vsub.i64 q4,q7,q4 vshr.s64 q7,q14,#26 vshl.i64 q13,q13,#25 vadd.i64 q14,q2,q11 vadd.i64 q8,q8,q7 vshl.i64 q7,q7,#26 vadd.i64 q15,q8,q3 vsub.i64 q9,q9,q13 vshr.s64 q13,q14,#26 vsub.i64 q6,q6,q7 vshr.s64 q7,q15,#25 vadd.i64 q10,q10,q13 vshl.i64 q13,q13,#26 vadd.i64 q14,q10,q3 vadd.i64 q1,q1,q7 add r2,r3,#288 vshl.i64 q7,q7,#25 add r4,r3,#96 vadd.i64 q15,q1,q11 add r2,r2,#8 vsub.i64 q2,q2,q13 add r4,r4,#8 vshr.s64 q13,q14,#25 vsub.i64 q7,q8,q7 vshr.s64 q8,q15,#26 vadd.i64 q14,q13,q13 vadd.i64 q12,q12,q8 vtrn.32 d12,d14 vshl.i64 q8,q8,#26 vtrn.32 d13,d15 vadd.i64 q3,q12,q3 vadd.i64 q0,q0,q14 vst1.8 d12,[r2,: 64]! vshl.i64 q7,q13,#4 vst1.8 d13,[r4,: 64]! vsub.i64 q1,q1,q8 vshr.s64 q3,q3,#25 vadd.i64 q0,q0,q7 vadd.i64 q5,q5,q3 vshl.i64 q3,q3,#25 vadd.i64 q6,q5,q11 vadd.i64 q0,q0,q13 vshl.i64 q7,q13,#25 vadd.i64 q8,q0,q11 vsub.i64 q3,q12,q3 vshr.s64 q6,q6,#26 vsub.i64 q7,q10,q7 vtrn.32 d2,d6 vshr.s64 q8,q8,#26 vtrn.32 d3,d7 vadd.i64 q3,q9,q6 vst1.8 d2,[r2,: 64] vshl.i64 q6,q6,#26 vst1.8 d3,[r4,: 64] vadd.i64 q1,q4,q8 vtrn.32 d4,d14 vshl.i64 q4,q8,#26 vtrn.32 d5,d15 vsub.i64 q5,q5,q6 add r2,r2,#16 vsub.i64 q0,q0,q4 vst1.8 d4,[r2,: 64] add r4,r4,#16 vst1.8 d5,[r4,: 64] vtrn.32 d10,d6 vtrn.32 d11,d7 sub r2,r2,#8 sub r4,r4,#8 vtrn.32 d0,d2 vtrn.32 d1,d3 vst1.8 d10,[r2,: 64] vst1.8 d11,[r4,: 64] sub r2,r2,#24 sub r4,r4,#24 vst1.8 d0,[r2,: 64] vst1.8 d1,[r4,: 64] add r2,sp,#544 add r4,r3,#144 add r5,r3,#192 vld1.8 {d0-d1},[r2,: 128] vld1.8 {d2-d3},[r4,: 128]! vld1.8 {d4-d5},[r5,: 128]! vzip.i32 q1,q2 vld1.8 {d6-d7},[r4,: 128]! vld1.8 {d8-d9},[r5,: 128]! vshl.i32 q5,q1,#1 vzip.i32 q3,q4 vshl.i32 q6,q2,#1 vld1.8 {d14},[r4,: 64] vshl.i32 q8,q3,#1 vld1.8 {d15},[r5,: 64] vshl.i32 q9,q4,#1 vmul.i32 d21,d7,d1 vtrn.32 d14,d15 vmul.i32 q11,q4,q0 vmul.i32 q0,q7,q0 vmull.s32 q12,d2,d2 vmlal.s32 q12,d11,d1 vmlal.s32 q12,d12,d0 vmlal.s32 q12,d13,d23 vmlal.s32 q12,d16,d22 vmlal.s32 q12,d7,d21 vmull.s32 q10,d2,d11 vmlal.s32 q10,d4,d1 vmlal.s32 q10,d13,d0 vmlal.s32 q10,d6,d23 vmlal.s32 q10,d17,d22 vmull.s32 q13,d10,d4 vmlal.s32 q13,d11,d3 vmlal.s32 q13,d13,d1 vmlal.s32 q13,d16,d0 vmlal.s32 q13,d17,d23 vmlal.s32 q13,d8,d22 vmull.s32 q1,d10,d5 vmlal.s32 q1,d11,d4 vmlal.s32 q1,d6,d1 vmlal.s32 q1,d17,d0 vmlal.s32 q1,d8,d23 vmull.s32 q14,d10,d6 vmlal.s32 q14,d11,d13 vmlal.s32 q14,d4,d4 vmlal.s32 q14,d17,d1 vmlal.s32 q14,d18,d0 vmlal.s32 q14,d9,d23 vmull.s32 q11,d10,d7 vmlal.s32 q11,d11,d6 vmlal.s32 q11,d12,d5 vmlal.s32 q11,d8,d1 vmlal.s32 q11,d19,d0 vmull.s32 q15,d10,d8 vmlal.s32 q15,d11,d17 vmlal.s32 q15,d12,d6 vmlal.s32 q15,d13,d5 vmlal.s32 q15,d19,d1 vmlal.s32 q15,d14,d0 vmull.s32 q2,d10,d9 vmlal.s32 q2,d11,d8 vmlal.s32 q2,d12,d7 vmlal.s32 q2,d13,d6 vmlal.s32 q2,d14,d1 vmull.s32 q0,d15,d1 vmlal.s32 q0,d10,d14 vmlal.s32 q0,d11,d19 vmlal.s32 q0,d12,d8 vmlal.s32 q0,d13,d17 vmlal.s32 q0,d6,d6 add r2,sp,#512 vld1.8 {d18-d19},[r2,: 128] vmull.s32 q3,d16,d7 vmlal.s32 q3,d10,d15 vmlal.s32 q3,d11,d14 vmlal.s32 q3,d12,d9 vmlal.s32 q3,d13,d8 add r2,sp,#528 vld1.8 {d8-d9},[r2,: 128] vadd.i64 q5,q12,q9 vadd.i64 q6,q15,q9 vshr.s64 q5,q5,#26 vshr.s64 q6,q6,#26 vadd.i64 q7,q10,q5 vshl.i64 q5,q5,#26 vadd.i64 q8,q7,q4 vadd.i64 q2,q2,q6 vshl.i64 q6,q6,#26 vadd.i64 q10,q2,q4 vsub.i64 q5,q12,q5 vshr.s64 q8,q8,#25 vsub.i64 q6,q15,q6 vshr.s64 q10,q10,#25 vadd.i64 q12,q13,q8 vshl.i64 q8,q8,#25 vadd.i64 q13,q12,q9 vadd.i64 q0,q0,q10 vsub.i64 q7,q7,q8 vshr.s64 q8,q13,#26 vshl.i64 q10,q10,#25 vadd.i64 q13,q0,q9 vadd.i64 q1,q1,q8 vshl.i64 q8,q8,#26 vadd.i64 q15,q1,q4 vsub.i64 q2,q2,q10 vshr.s64 q10,q13,#26 vsub.i64 q8,q12,q8 vshr.s64 q12,q15,#25 vadd.i64 q3,q3,q10 vshl.i64 q10,q10,#26 vadd.i64 q13,q3,q4 vadd.i64 q14,q14,q12 add r2,r3,#144 vshl.i64 q12,q12,#25 add r4,r3,#192 vadd.i64 q15,q14,q9 add r2,r2,#8 vsub.i64 q0,q0,q10 add r4,r4,#8 vshr.s64 q10,q13,#25 vsub.i64 q1,q1,q12 vshr.s64 q12,q15,#26 vadd.i64 q13,q10,q10 vadd.i64 q11,q11,q12 vtrn.32 d16,d2 vshl.i64 q12,q12,#26 vtrn.32 d17,d3 vadd.i64 q1,q11,q4 vadd.i64 q4,q5,q13 vst1.8 d16,[r2,: 64]! vshl.i64 q5,q10,#4 vst1.8 d17,[r4,: 64]! vsub.i64 q8,q14,q12 vshr.s64 q1,q1,#25 vadd.i64 q4,q4,q5 vadd.i64 q5,q6,q1 vshl.i64 q1,q1,#25 vadd.i64 q6,q5,q9 vadd.i64 q4,q4,q10 vshl.i64 q10,q10,#25 vadd.i64 q9,q4,q9 vsub.i64 q1,q11,q1 vshr.s64 q6,q6,#26 vsub.i64 q3,q3,q10 vtrn.32 d16,d2 vshr.s64 q9,q9,#26 vtrn.32 d17,d3 vadd.i64 q1,q2,q6 vst1.8 d16,[r2,: 64] vshl.i64 q2,q6,#26 vst1.8 d17,[r4,: 64] vadd.i64 q6,q7,q9 vtrn.32 d0,d6 vshl.i64 q7,q9,#26 vtrn.32 d1,d7 vsub.i64 q2,q5,q2 add r2,r2,#16 vsub.i64 q3,q4,q7 vst1.8 d0,[r2,: 64] add r4,r4,#16 vst1.8 d1,[r4,: 64] vtrn.32 d4,d2 vtrn.32 d5,d3 sub r2,r2,#8 sub r4,r4,#8 vtrn.32 d6,d12 vtrn.32 d7,d13 vst1.8 d4,[r2,: 64] vst1.8 d5,[r4,: 64] sub r2,r2,#24 sub r4,r4,#24 vst1.8 d6,[r2,: 64] vst1.8 d7,[r4,: 64] add r2,r3,#336 add r4,r3,#288 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r4,: 128]! vadd.i32 q0,q0,q1 vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d4-d5},[r4,: 128]! vadd.i32 q1,q1,q2 add r5,r3,#288 vld1.8 {d4},[r2,: 64] vld1.8 {d6},[r4,: 64] vadd.i32 q2,q2,q3 vst1.8 {d0-d1},[r5,: 128]! vst1.8 {d2-d3},[r5,: 128]! vst1.8 d4,[r5,: 64] add r2,r3,#48 add r4,r3,#144 vld1.8 {d0-d1},[r4,: 128]! vld1.8 {d2-d3},[r4,: 128]! vld1.8 {d4},[r4,: 64] add r4,r3,#288 vld1.8 {d6-d7},[r4,: 128]! vtrn.32 q0,q3 vld1.8 {d8-d9},[r4,: 128]! vshl.i32 q5,q0,#4 vtrn.32 q1,q4 vshl.i32 q6,q3,#4 vadd.i32 q5,q5,q0 vadd.i32 q6,q6,q3 vshl.i32 q7,q1,#4 vld1.8 {d5},[r4,: 64] vshl.i32 q8,q4,#4 vtrn.32 d4,d5 vadd.i32 q7,q7,q1 vadd.i32 q8,q8,q4 vld1.8 {d18-d19},[r2,: 128]! vshl.i32 q10,q2,#4 vld1.8 {d22-d23},[r2,: 128]! vadd.i32 q10,q10,q2 vld1.8 {d24},[r2,: 64] vadd.i32 q5,q5,q0 add r2,r3,#240 vld1.8 {d26-d27},[r2,: 128]! vadd.i32 q6,q6,q3 vld1.8 {d28-d29},[r2,: 128]! vadd.i32 q8,q8,q4 vld1.8 {d25},[r2,: 64] vadd.i32 q10,q10,q2 vtrn.32 q9,q13 vadd.i32 q7,q7,q1 vadd.i32 q5,q5,q0 vtrn.32 q11,q14 vadd.i32 q6,q6,q3 add r2,sp,#560 vadd.i32 q10,q10,q2 vtrn.32 d24,d25 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q6,q13,#1 add r2,sp,#576 vst1.8 {d20-d21},[r2,: 128] vshl.i32 q10,q14,#1 add r2,sp,#592 vst1.8 {d12-d13},[r2,: 128] vshl.i32 q15,q12,#1 vadd.i32 q8,q8,q4 vext.32 d10,d31,d30,#0 vadd.i32 q7,q7,q1 add r2,sp,#608 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q8,d18,d5 vmlal.s32 q8,d26,d4 vmlal.s32 q8,d19,d9 vmlal.s32 q8,d27,d3 vmlal.s32 q8,d22,d8 vmlal.s32 q8,d28,d2 vmlal.s32 q8,d23,d7 vmlal.s32 q8,d29,d1 vmlal.s32 q8,d24,d6 vmlal.s32 q8,d25,d0 add r2,sp,#624 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q2,d18,d4 vmlal.s32 q2,d12,d9 vmlal.s32 q2,d13,d8 vmlal.s32 q2,d19,d3 vmlal.s32 q2,d22,d2 vmlal.s32 q2,d23,d1 vmlal.s32 q2,d24,d0 add r2,sp,#640 vst1.8 {d20-d21},[r2,: 128] vmull.s32 q7,d18,d9 vmlal.s32 q7,d26,d3 vmlal.s32 q7,d19,d8 vmlal.s32 q7,d27,d2 vmlal.s32 q7,d22,d7 vmlal.s32 q7,d28,d1 vmlal.s32 q7,d23,d6 vmlal.s32 q7,d29,d0 add r2,sp,#656 vst1.8 {d10-d11},[r2,: 128] vmull.s32 q5,d18,d3 vmlal.s32 q5,d19,d2 vmlal.s32 q5,d22,d1 vmlal.s32 q5,d23,d0 vmlal.s32 q5,d12,d8 add r2,sp,#672 vst1.8 {d16-d17},[r2,: 128] vmull.s32 q4,d18,d8 vmlal.s32 q4,d26,d2 vmlal.s32 q4,d19,d7 vmlal.s32 q4,d27,d1 vmlal.s32 q4,d22,d6 vmlal.s32 q4,d28,d0 vmull.s32 q8,d18,d7 vmlal.s32 q8,d26,d1 vmlal.s32 q8,d19,d6 vmlal.s32 q8,d27,d0 add r2,sp,#576 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q7,d24,d21 vmlal.s32 q7,d25,d20 vmlal.s32 q4,d23,d21 vmlal.s32 q4,d29,d20 vmlal.s32 q8,d22,d21 vmlal.s32 q8,d28,d20 vmlal.s32 q5,d24,d20 add r2,sp,#576 vst1.8 {d14-d15},[r2,: 128] vmull.s32 q7,d18,d6 vmlal.s32 q7,d26,d0 add r2,sp,#656 vld1.8 {d30-d31},[r2,: 128] vmlal.s32 q2,d30,d21 vmlal.s32 q7,d19,d21 vmlal.s32 q7,d27,d20 add r2,sp,#624 vld1.8 {d26-d27},[r2,: 128] vmlal.s32 q4,d25,d27 vmlal.s32 q8,d29,d27 vmlal.s32 q8,d25,d26 vmlal.s32 q7,d28,d27 vmlal.s32 q7,d29,d26 add r2,sp,#608 vld1.8 {d28-d29},[r2,: 128] vmlal.s32 q4,d24,d29 vmlal.s32 q8,d23,d29 vmlal.s32 q8,d24,d28 vmlal.s32 q7,d22,d29 vmlal.s32 q7,d23,d28 add r2,sp,#608 vst1.8 {d8-d9},[r2,: 128] add r2,sp,#560 vld1.8 {d8-d9},[r2,: 128] vmlal.s32 q7,d24,d9 vmlal.s32 q7,d25,d31 vmull.s32 q1,d18,d2 vmlal.s32 q1,d19,d1 vmlal.s32 q1,d22,d0 vmlal.s32 q1,d24,d27 vmlal.s32 q1,d23,d20 vmlal.s32 q1,d12,d7 vmlal.s32 q1,d13,d6 vmull.s32 q6,d18,d1 vmlal.s32 q6,d19,d0 vmlal.s32 q6,d23,d27 vmlal.s32 q6,d22,d20 vmlal.s32 q6,d24,d26 vmull.s32 q0,d18,d0 vmlal.s32 q0,d22,d27 vmlal.s32 q0,d23,d26 vmlal.s32 q0,d24,d31 vmlal.s32 q0,d19,d20 add r2,sp,#640 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q2,d18,d7 vmlal.s32 q2,d19,d6 vmlal.s32 q5,d18,d6 vmlal.s32 q5,d19,d21 vmlal.s32 q1,d18,d21 vmlal.s32 q1,d19,d29 vmlal.s32 q0,d18,d28 vmlal.s32 q0,d19,d9 vmlal.s32 q6,d18,d29 vmlal.s32 q6,d19,d28 add r2,sp,#592 vld1.8 {d18-d19},[r2,: 128] add r2,sp,#512 vld1.8 {d22-d23},[r2,: 128] vmlal.s32 q5,d19,d7 vmlal.s32 q0,d18,d21 vmlal.s32 q0,d19,d29 vmlal.s32 q6,d18,d6 add r2,sp,#528 vld1.8 {d6-d7},[r2,: 128] vmlal.s32 q6,d19,d21 add r2,sp,#576 vld1.8 {d18-d19},[r2,: 128] vmlal.s32 q0,d30,d8 add r2,sp,#672 vld1.8 {d20-d21},[r2,: 128] vmlal.s32 q5,d30,d29 add r2,sp,#608 vld1.8 {d24-d25},[r2,: 128] vmlal.s32 q1,d30,d28 vadd.i64 q13,q0,q11 vadd.i64 q14,q5,q11 vmlal.s32 q6,d30,d9 vshr.s64 q4,q13,#26 vshr.s64 q13,q14,#26 vadd.i64 q7,q7,q4 vshl.i64 q4,q4,#26 vadd.i64 q14,q7,q3 vadd.i64 q9,q9,q13 vshl.i64 q13,q13,#26 vadd.i64 q15,q9,q3 vsub.i64 q0,q0,q4 vshr.s64 q4,q14,#25 vsub.i64 q5,q5,q13 vshr.s64 q13,q15,#25 vadd.i64 q6,q6,q4 vshl.i64 q4,q4,#25 vadd.i64 q14,q6,q11 vadd.i64 q2,q2,q13 vsub.i64 q4,q7,q4 vshr.s64 q7,q14,#26 vshl.i64 q13,q13,#25 vadd.i64 q14,q2,q11 vadd.i64 q8,q8,q7 vshl.i64 q7,q7,#26 vadd.i64 q15,q8,q3 vsub.i64 q9,q9,q13 vshr.s64 q13,q14,#26 vsub.i64 q6,q6,q7 vshr.s64 q7,q15,#25 vadd.i64 q10,q10,q13 vshl.i64 q13,q13,#26 vadd.i64 q14,q10,q3 vadd.i64 q1,q1,q7 add r2,r3,#240 vshl.i64 q7,q7,#25 add r4,r3,#144 vadd.i64 q15,q1,q11 add r2,r2,#8 vsub.i64 q2,q2,q13 add r4,r4,#8 vshr.s64 q13,q14,#25 vsub.i64 q7,q8,q7 vshr.s64 q8,q15,#26 vadd.i64 q14,q13,q13 vadd.i64 q12,q12,q8 vtrn.32 d12,d14 vshl.i64 q8,q8,#26 vtrn.32 d13,d15 vadd.i64 q3,q12,q3 vadd.i64 q0,q0,q14 vst1.8 d12,[r2,: 64]! vshl.i64 q7,q13,#4 vst1.8 d13,[r4,: 64]! vsub.i64 q1,q1,q8 vshr.s64 q3,q3,#25 vadd.i64 q0,q0,q7 vadd.i64 q5,q5,q3 vshl.i64 q3,q3,#25 vadd.i64 q6,q5,q11 vadd.i64 q0,q0,q13 vshl.i64 q7,q13,#25 vadd.i64 q8,q0,q11 vsub.i64 q3,q12,q3 vshr.s64 q6,q6,#26 vsub.i64 q7,q10,q7 vtrn.32 d2,d6 vshr.s64 q8,q8,#26 vtrn.32 d3,d7 vadd.i64 q3,q9,q6 vst1.8 d2,[r2,: 64] vshl.i64 q6,q6,#26 vst1.8 d3,[r4,: 64] vadd.i64 q1,q4,q8 vtrn.32 d4,d14 vshl.i64 q4,q8,#26 vtrn.32 d5,d15 vsub.i64 q5,q5,q6 add r2,r2,#16 vsub.i64 q0,q0,q4 vst1.8 d4,[r2,: 64] add r4,r4,#16 vst1.8 d5,[r4,: 64] vtrn.32 d10,d6 vtrn.32 d11,d7 sub r2,r2,#8 sub r4,r4,#8 vtrn.32 d0,d2 vtrn.32 d1,d3 vst1.8 d10,[r2,: 64] vst1.8 d11,[r4,: 64] sub r2,r2,#24 sub r4,r4,#24 vst1.8 d0,[r2,: 64] vst1.8 d1,[r4,: 64] ldr r2,[sp,#488] ldr r4,[sp,#492] subs r5,r2,#1 bge ._mainloop add r1,r3,#144 add r2,r3,#336 vld1.8 {d0-d1},[r1,: 128]! vld1.8 {d2-d3},[r1,: 128]! vld1.8 {d4},[r1,: 64] vst1.8 {d0-d1},[r2,: 128]! vst1.8 {d2-d3},[r2,: 128]! vst1.8 d4,[r2,: 64] ldr r1,=0 ._invertloop: add r2,r3,#144 ldr r4,=0 ldr r5,=2 cmp r1,#1 ldreq r5,=1 addeq r2,r3,#336 addeq r4,r3,#48 cmp r1,#2 ldreq r5,=1 addeq r2,r3,#48 cmp r1,#3 ldreq r5,=5 addeq r4,r3,#336 cmp r1,#4 ldreq r5,=10 cmp r1,#5 ldreq r5,=20 cmp r1,#6 ldreq r5,=10 addeq r2,r3,#336 addeq r4,r3,#336 cmp r1,#7 ldreq r5,=50 cmp r1,#8 ldreq r5,=100 cmp r1,#9 ldreq r5,=50 addeq r2,r3,#336 cmp r1,#10 ldreq r5,=5 addeq r2,r3,#48 cmp r1,#11 ldreq r5,=0 addeq r2,r3,#96 add r6,r3,#144 add r7,r3,#288 vld1.8 {d0-d1},[r6,: 128]! vld1.8 {d2-d3},[r6,: 128]! vld1.8 {d4},[r6,: 64] vst1.8 {d0-d1},[r7,: 128]! vst1.8 {d2-d3},[r7,: 128]! vst1.8 d4,[r7,: 64] cmp r5,#0 beq ._skipsquaringloop ._squaringloop: add r6,r3,#288 add r7,r3,#288 add r8,r3,#288 vmov.i32 q0,#19 vmov.i32 q1,#0 vmov.i32 q2,#1 vzip.i32 q1,q2 vld1.8 {d4-d5},[r7,: 128]! vld1.8 {d6-d7},[r7,: 128]! vld1.8 {d9},[r7,: 64] vld1.8 {d10-d11},[r6,: 128]! add r7,sp,#416 vld1.8 {d12-d13},[r6,: 128]! vmul.i32 q7,q2,q0 vld1.8 {d8},[r6,: 64] vext.32 d17,d11,d10,#1 vmul.i32 q9,q3,q0 vext.32 d16,d10,d8,#1 vshl.u32 q10,q5,q1 vext.32 d22,d14,d4,#1 vext.32 d24,d18,d6,#1 vshl.u32 q13,q6,q1 vshl.u32 d28,d8,d2 vrev64.i32 d22,d22 vmul.i32 d1,d9,d1 vrev64.i32 d24,d24 vext.32 d29,d8,d13,#1 vext.32 d0,d1,d9,#1 vrev64.i32 d0,d0 vext.32 d2,d9,d1,#1 vext.32 d23,d15,d5,#1 vmull.s32 q4,d20,d4 vrev64.i32 d23,d23 vmlal.s32 q4,d21,d1 vrev64.i32 d2,d2 vmlal.s32 q4,d26,d19 vext.32 d3,d5,d15,#1 vmlal.s32 q4,d27,d18 vrev64.i32 d3,d3 vmlal.s32 q4,d28,d15 vext.32 d14,d12,d11,#1 vmull.s32 q5,d16,d23 vext.32 d15,d13,d12,#1 vmlal.s32 q5,d17,d4 vst1.8 d8,[r7,: 64]! vmlal.s32 q5,d14,d1 vext.32 d12,d9,d8,#0 vmlal.s32 q5,d15,d19 vmov.i64 d13,#0 vmlal.s32 q5,d29,d18 vext.32 d25,d19,d7,#1 vmlal.s32 q6,d20,d5 vrev64.i32 d25,d25 vmlal.s32 q6,d21,d4 vst1.8 d11,[r7,: 64]! vmlal.s32 q6,d26,d1 vext.32 d9,d10,d10,#0 vmlal.s32 q6,d27,d19 vmov.i64 d8,#0 vmlal.s32 q6,d28,d18 vmlal.s32 q4,d16,d24 vmlal.s32 q4,d17,d5 vmlal.s32 q4,d14,d4 vst1.8 d12,[r7,: 64]! vmlal.s32 q4,d15,d1 vext.32 d10,d13,d12,#0 vmlal.s32 q4,d29,d19 vmov.i64 d11,#0 vmlal.s32 q5,d20,d6 vmlal.s32 q5,d21,d5 vmlal.s32 q5,d26,d4 vext.32 d13,d8,d8,#0 vmlal.s32 q5,d27,d1 vmov.i64 d12,#0 vmlal.s32 q5,d28,d19 vst1.8 d9,[r7,: 64]! vmlal.s32 q6,d16,d25 vmlal.s32 q6,d17,d6 vst1.8 d10,[r7,: 64] vmlal.s32 q6,d14,d5 vext.32 d8,d11,d10,#0 vmlal.s32 q6,d15,d4 vmov.i64 d9,#0 vmlal.s32 q6,d29,d1 vmlal.s32 q4,d20,d7 vmlal.s32 q4,d21,d6 vmlal.s32 q4,d26,d5 vext.32 d11,d12,d12,#0 vmlal.s32 q4,d27,d4 vmov.i64 d10,#0 vmlal.s32 q4,d28,d1 vmlal.s32 q5,d16,d0 sub r6,r7,#32 vmlal.s32 q5,d17,d7 vmlal.s32 q5,d14,d6 vext.32 d30,d9,d8,#0 vmlal.s32 q5,d15,d5 vld1.8 {d31},[r6,: 64]! vmlal.s32 q5,d29,d4 vmlal.s32 q15,d20,d0 vext.32 d0,d6,d18,#1 vmlal.s32 q15,d21,d25 vrev64.i32 d0,d0 vmlal.s32 q15,d26,d24 vext.32 d1,d7,d19,#1 vext.32 d7,d10,d10,#0 vmlal.s32 q15,d27,d23 vrev64.i32 d1,d1 vld1.8 {d6},[r6,: 64] vmlal.s32 q15,d28,d22 vmlal.s32 q3,d16,d4 add r6,r6,#24 vmlal.s32 q3,d17,d2 vext.32 d4,d31,d30,#0 vmov d17,d11 vmlal.s32 q3,d14,d1 vext.32 d11,d13,d13,#0 vext.32 d13,d30,d30,#0 vmlal.s32 q3,d15,d0 vext.32 d1,d8,d8,#0 vmlal.s32 q3,d29,d3 vld1.8 {d5},[r6,: 64] sub r6,r6,#16 vext.32 d10,d6,d6,#0 vmov.i32 q1,#0xffffffff vshl.i64 q4,q1,#25 add r7,sp,#512 vld1.8 {d14-d15},[r7,: 128] vadd.i64 q9,q2,q7 vshl.i64 q1,q1,#26 vshr.s64 q10,q9,#26 vld1.8 {d0},[r6,: 64]! vadd.i64 q5,q5,q10 vand q9,q9,q1 vld1.8 {d16},[r6,: 64]! add r6,sp,#528 vld1.8 {d20-d21},[r6,: 128] vadd.i64 q11,q5,q10 vsub.i64 q2,q2,q9 vshr.s64 q9,q11,#25 vext.32 d12,d5,d4,#0 vand q11,q11,q4 vadd.i64 q0,q0,q9 vmov d19,d7 vadd.i64 q3,q0,q7 vsub.i64 q5,q5,q11 vshr.s64 q11,q3,#26 vext.32 d18,d11,d10,#0 vand q3,q3,q1 vadd.i64 q8,q8,q11 vadd.i64 q11,q8,q10 vsub.i64 q0,q0,q3 vshr.s64 q3,q11,#25 vand q11,q11,q4 vadd.i64 q3,q6,q3 vadd.i64 q6,q3,q7 vsub.i64 q8,q8,q11 vshr.s64 q11,q6,#26 vand q6,q6,q1 vadd.i64 q9,q9,q11 vadd.i64 d25,d19,d21 vsub.i64 q3,q3,q6 vshr.s64 d23,d25,#25 vand q4,q12,q4 vadd.i64 d21,d23,d23 vshl.i64 d25,d23,#4 vadd.i64 d21,d21,d23 vadd.i64 d25,d25,d21 vadd.i64 d4,d4,d25 vzip.i32 q0,q8 vadd.i64 d12,d4,d14 add r6,r8,#8 vst1.8 d0,[r6,: 64] vsub.i64 d19,d19,d9 add r6,r6,#16 vst1.8 d16,[r6,: 64] vshr.s64 d22,d12,#26 vand q0,q6,q1 vadd.i64 d10,d10,d22 vzip.i32 q3,q9 vsub.i64 d4,d4,d0 sub r6,r6,#8 vst1.8 d6,[r6,: 64] add r6,r6,#16 vst1.8 d18,[r6,: 64] vzip.i32 q2,q5 sub r6,r6,#32 vst1.8 d4,[r6,: 64] subs r5,r5,#1 bhi ._squaringloop ._skipsquaringloop: mov r2,r2 add r5,r3,#288 add r6,r3,#144 vmov.i32 q0,#19 vmov.i32 q1,#0 vmov.i32 q2,#1 vzip.i32 q1,q2 vld1.8 {d4-d5},[r5,: 128]! vld1.8 {d6-d7},[r5,: 128]! vld1.8 {d9},[r5,: 64] vld1.8 {d10-d11},[r2,: 128]! add r5,sp,#416 vld1.8 {d12-d13},[r2,: 128]! vmul.i32 q7,q2,q0 vld1.8 {d8},[r2,: 64] vext.32 d17,d11,d10,#1 vmul.i32 q9,q3,q0 vext.32 d16,d10,d8,#1 vshl.u32 q10,q5,q1 vext.32 d22,d14,d4,#1 vext.32 d24,d18,d6,#1 vshl.u32 q13,q6,q1 vshl.u32 d28,d8,d2 vrev64.i32 d22,d22 vmul.i32 d1,d9,d1 vrev64.i32 d24,d24 vext.32 d29,d8,d13,#1 vext.32 d0,d1,d9,#1 vrev64.i32 d0,d0 vext.32 d2,d9,d1,#1 vext.32 d23,d15,d5,#1 vmull.s32 q4,d20,d4 vrev64.i32 d23,d23 vmlal.s32 q4,d21,d1 vrev64.i32 d2,d2 vmlal.s32 q4,d26,d19 vext.32 d3,d5,d15,#1 vmlal.s32 q4,d27,d18 vrev64.i32 d3,d3 vmlal.s32 q4,d28,d15 vext.32 d14,d12,d11,#1 vmull.s32 q5,d16,d23 vext.32 d15,d13,d12,#1 vmlal.s32 q5,d17,d4 vst1.8 d8,[r5,: 64]! vmlal.s32 q5,d14,d1 vext.32 d12,d9,d8,#0 vmlal.s32 q5,d15,d19 vmov.i64 d13,#0 vmlal.s32 q5,d29,d18 vext.32 d25,d19,d7,#1 vmlal.s32 q6,d20,d5 vrev64.i32 d25,d25 vmlal.s32 q6,d21,d4 vst1.8 d11,[r5,: 64]! vmlal.s32 q6,d26,d1 vext.32 d9,d10,d10,#0 vmlal.s32 q6,d27,d19 vmov.i64 d8,#0 vmlal.s32 q6,d28,d18 vmlal.s32 q4,d16,d24 vmlal.s32 q4,d17,d5 vmlal.s32 q4,d14,d4 vst1.8 d12,[r5,: 64]! vmlal.s32 q4,d15,d1 vext.32 d10,d13,d12,#0 vmlal.s32 q4,d29,d19 vmov.i64 d11,#0 vmlal.s32 q5,d20,d6 vmlal.s32 q5,d21,d5 vmlal.s32 q5,d26,d4 vext.32 d13,d8,d8,#0 vmlal.s32 q5,d27,d1 vmov.i64 d12,#0 vmlal.s32 q5,d28,d19 vst1.8 d9,[r5,: 64]! vmlal.s32 q6,d16,d25 vmlal.s32 q6,d17,d6 vst1.8 d10,[r5,: 64] vmlal.s32 q6,d14,d5 vext.32 d8,d11,d10,#0 vmlal.s32 q6,d15,d4 vmov.i64 d9,#0 vmlal.s32 q6,d29,d1 vmlal.s32 q4,d20,d7 vmlal.s32 q4,d21,d6 vmlal.s32 q4,d26,d5 vext.32 d11,d12,d12,#0 vmlal.s32 q4,d27,d4 vmov.i64 d10,#0 vmlal.s32 q4,d28,d1 vmlal.s32 q5,d16,d0 sub r2,r5,#32 vmlal.s32 q5,d17,d7 vmlal.s32 q5,d14,d6 vext.32 d30,d9,d8,#0 vmlal.s32 q5,d15,d5 vld1.8 {d31},[r2,: 64]! vmlal.s32 q5,d29,d4 vmlal.s32 q15,d20,d0 vext.32 d0,d6,d18,#1 vmlal.s32 q15,d21,d25 vrev64.i32 d0,d0 vmlal.s32 q15,d26,d24 vext.32 d1,d7,d19,#1 vext.32 d7,d10,d10,#0 vmlal.s32 q15,d27,d23 vrev64.i32 d1,d1 vld1.8 {d6},[r2,: 64] vmlal.s32 q15,d28,d22 vmlal.s32 q3,d16,d4 add r2,r2,#24 vmlal.s32 q3,d17,d2 vext.32 d4,d31,d30,#0 vmov d17,d11 vmlal.s32 q3,d14,d1 vext.32 d11,d13,d13,#0 vext.32 d13,d30,d30,#0 vmlal.s32 q3,d15,d0 vext.32 d1,d8,d8,#0 vmlal.s32 q3,d29,d3 vld1.8 {d5},[r2,: 64] sub r2,r2,#16 vext.32 d10,d6,d6,#0 vmov.i32 q1,#0xffffffff vshl.i64 q4,q1,#25 add r5,sp,#512 vld1.8 {d14-d15},[r5,: 128] vadd.i64 q9,q2,q7 vshl.i64 q1,q1,#26 vshr.s64 q10,q9,#26 vld1.8 {d0},[r2,: 64]! vadd.i64 q5,q5,q10 vand q9,q9,q1 vld1.8 {d16},[r2,: 64]! add r2,sp,#528 vld1.8 {d20-d21},[r2,: 128] vadd.i64 q11,q5,q10 vsub.i64 q2,q2,q9 vshr.s64 q9,q11,#25 vext.32 d12,d5,d4,#0 vand q11,q11,q4 vadd.i64 q0,q0,q9 vmov d19,d7 vadd.i64 q3,q0,q7 vsub.i64 q5,q5,q11 vshr.s64 q11,q3,#26 vext.32 d18,d11,d10,#0 vand q3,q3,q1 vadd.i64 q8,q8,q11 vadd.i64 q11,q8,q10 vsub.i64 q0,q0,q3 vshr.s64 q3,q11,#25 vand q11,q11,q4 vadd.i64 q3,q6,q3 vadd.i64 q6,q3,q7 vsub.i64 q8,q8,q11 vshr.s64 q11,q6,#26 vand q6,q6,q1 vadd.i64 q9,q9,q11 vadd.i64 d25,d19,d21 vsub.i64 q3,q3,q6 vshr.s64 d23,d25,#25 vand q4,q12,q4 vadd.i64 d21,d23,d23 vshl.i64 d25,d23,#4 vadd.i64 d21,d21,d23 vadd.i64 d25,d25,d21 vadd.i64 d4,d4,d25 vzip.i32 q0,q8 vadd.i64 d12,d4,d14 add r2,r6,#8 vst1.8 d0,[r2,: 64] vsub.i64 d19,d19,d9 add r2,r2,#16 vst1.8 d16,[r2,: 64] vshr.s64 d22,d12,#26 vand q0,q6,q1 vadd.i64 d10,d10,d22 vzip.i32 q3,q9 vsub.i64 d4,d4,d0 sub r2,r2,#8 vst1.8 d6,[r2,: 64] add r2,r2,#16 vst1.8 d18,[r2,: 64] vzip.i32 q2,q5 sub r2,r2,#32 vst1.8 d4,[r2,: 64] cmp r4,#0 beq ._skippostcopy add r2,r3,#144 mov r4,r4 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d4},[r2,: 64] vst1.8 {d0-d1},[r4,: 128]! vst1.8 {d2-d3},[r4,: 128]! vst1.8 d4,[r4,: 64] ._skippostcopy: cmp r1,#1 bne ._skipfinalcopy add r2,r3,#288 add r4,r3,#144 vld1.8 {d0-d1},[r2,: 128]! vld1.8 {d2-d3},[r2,: 128]! vld1.8 {d4},[r2,: 64] vst1.8 {d0-d1},[r4,: 128]! vst1.8 {d2-d3},[r4,: 128]! vst1.8 d4,[r4,: 64] ._skipfinalcopy: add r1,r1,#1 cmp r1,#12 blo ._invertloop add r1,r3,#144 ldr r2,[r1],#4 ldr r3,[r1],#4 ldr r4,[r1],#4 ldr r5,[r1],#4 ldr r6,[r1],#4 ldr r7,[r1],#4 ldr r8,[r1],#4 ldr r9,[r1],#4 ldr r10,[r1],#4 ldr r1,[r1] add r11,r1,r1,LSL #4 add r11,r11,r1,LSL #1 add r11,r11,#16777216 mov r11,r11,ASR #25 add r11,r11,r2 mov r11,r11,ASR #26 add r11,r11,r3 mov r11,r11,ASR #25 add r11,r11,r4 mov r11,r11,ASR #26 add r11,r11,r5 mov r11,r11,ASR #25 add r11,r11,r6 mov r11,r11,ASR #26 add r11,r11,r7 mov r11,r11,ASR #25 add r11,r11,r8 mov r11,r11,ASR #26 add r11,r11,r9 mov r11,r11,ASR #25 add r11,r11,r10 mov r11,r11,ASR #26 add r11,r11,r1 mov r11,r11,ASR #25 add r2,r2,r11 add r2,r2,r11,LSL #1 add r2,r2,r11,LSL #4 mov r11,r2,ASR #26 add r3,r3,r11 sub r2,r2,r11,LSL #26 mov r11,r3,ASR #25 add r4,r4,r11 sub r3,r3,r11,LSL #25 mov r11,r4,ASR #26 add r5,r5,r11 sub r4,r4,r11,LSL #26 mov r11,r5,ASR #25 add r6,r6,r11 sub r5,r5,r11,LSL #25 mov r11,r6,ASR #26 add r7,r7,r11 sub r6,r6,r11,LSL #26 mov r11,r7,ASR #25 add r8,r8,r11 sub r7,r7,r11,LSL #25 mov r11,r8,ASR #26 add r9,r9,r11 sub r8,r8,r11,LSL #26 mov r11,r9,ASR #25 add r10,r10,r11 sub r9,r9,r11,LSL #25 mov r11,r10,ASR #26 add r1,r1,r11 sub r10,r10,r11,LSL #26 mov r11,r1,ASR #25 sub r1,r1,r11,LSL #25 add r2,r2,r3,LSL #26 mov r3,r3,LSR #6 add r3,r3,r4,LSL #19 mov r4,r4,LSR #13 add r4,r4,r5,LSL #13 mov r5,r5,LSR #19 add r5,r5,r6,LSL #6 add r6,r7,r8,LSL #25 mov r7,r8,LSR #7 add r7,r7,r9,LSL #19 mov r8,r9,LSR #13 add r8,r8,r10,LSL #12 mov r9,r10,LSR #20 add r1,r9,r1,LSL #6 str r2,[r0],#4 str r3,[r0],#4 str r4,[r0],#4 str r5,[r0],#4 str r6,[r0],#4 str r7,[r0],#4 str r8,[r0],#4 str r1,[r0] ldrd r4,[sp,#0] ldrd r6,[sp,#8] ldrd r8,[sp,#16] ldrd r10,[sp,#24] ldr r12,[sp,#480] ldr r14,[sp,#484] ldr r0,=0 mov sp,r12 vpop {q4,q5,q6,q7} bx lr #endif /* !OPENSSL_NO_ASM && OPENSSL_ARM && __ELF__ */

j4yc3-mw/Viren

1,571

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/riscv.s

#include "psm.h" .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 */ .cfi_startproc li x10, STACK_DIRECTION_DESCENDING jr x1 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: /* extern "C" fn() -> *mut u8 */ .cfi_startproc add x10, x2, x0 jr x1 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(x10: usize, x11: extern "C" fn(usize), x12: *mut u8) */ .cfi_startproc add x2, x12, x0 jr x11 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(x10: usize, x11: usize, x12: extern "C" fn(usize, usize), x13: *mut u8) */ .cfi_startproc sw x1, -12(x13) sw x2, -16(x13) addi x2, x13, -16 .cfi_def_cfa x2, 16 .cfi_offset x1, -12 .cfi_offset x2, -16 jalr x1, x12, 0 lw x1, 4(x2) .cfi_restore x1 lw x2, 0(x2) .cfi_restore x2 jr x1 .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

j4yc3-mw/Viren

2,235

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/x86_64.s

#include "psm.h" /* NOTE: sysv64 calling convention is used on all x86_64 targets, including Windows! */ .text #if CFG_TARGET_OS_darwin || CFG_TARGET_OS_macos || CFG_TARGET_OS_ios #define GLOBL(fnname) .globl _##fnname #define TYPE(fnname) #define FUNCTION(fnname) _##fnname #define SIZE(fnname,endlabel) #else #define GLOBL(fnname) .globl fnname #define TYPE(fnname) .type fnname,@function #define FUNCTION(fnname) fnname #define SIZE(fnname,endlabel) .size fnname,endlabel-fnname #endif GLOBL(rust_psm_stack_direction) .p2align 4 TYPE(rust_psm_stack_direction) FUNCTION(rust_psm_stack_direction): /* extern "sysv64" fn() -> u8 (%al) */ .cfi_startproc movb $STACK_DIRECTION_DESCENDING, %al # always descending on x86_64 retq .rust_psm_stack_direction_end: SIZE(rust_psm_stack_direction,.rust_psm_stack_direction_end) .cfi_endproc GLOBL(rust_psm_stack_pointer) .p2align 4 TYPE(rust_psm_stack_pointer) FUNCTION(rust_psm_stack_pointer): /* extern "sysv64" fn() -> *mut u8 (%rax) */ .cfi_startproc leaq 8(%rsp), %rax retq .rust_psm_stack_pointer_end: SIZE(rust_psm_stack_pointer,.rust_psm_stack_pointer_end) .cfi_endproc GLOBL(rust_psm_replace_stack) .p2align 4 TYPE(rust_psm_replace_stack) FUNCTION(rust_psm_replace_stack): /* extern "sysv64" fn(%rdi: usize, %rsi: extern "sysv64" fn(usize), %rdx: *mut u8) */ .cfi_startproc /* All we gotta do is set the stack pointer to %rdx & tail-call the callback in %rsi. 8-byte offset necessary to account for the "return" pointer that would otherwise be placed onto stack with a regular call */ leaq -8(%rdx), %rsp jmpq *%rsi .rust_psm_replace_stack_end: SIZE(rust_psm_replace_stack,.rust_psm_replace_stack_end) .cfi_endproc GLOBL(rust_psm_on_stack) .p2align 4 TYPE(rust_psm_on_stack) FUNCTION(rust_psm_on_stack): /* extern "sysv64" fn(%rdi: usize, %rsi: usize, %rdx: extern "sysv64" fn(usize, usize), %rcx: *mut u8) */ .cfi_startproc pushq %rbp .cfi_def_cfa %rsp, 16 .cfi_offset %rbp, -16 movq %rsp, %rbp .cfi_def_cfa_register %rbp movq %rcx, %rsp callq *%rdx movq %rbp, %rsp popq %rbp .cfi_def_cfa %rsp, 8 retq .rust_psm_on_stack_end: SIZE(rust_psm_on_stack,.rust_psm_on_stack_end) .cfi_endproc

j4yc3-mw/Viren

1,569

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/riscv64.s

#include "psm.h" .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 */ .cfi_startproc li x10, STACK_DIRECTION_DESCENDING jr x1 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: /* extern "C" fn() -> *mut u8 */ .cfi_startproc add x10, x2, x0 jr x1 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(x10: usize, x11: extern "C" fn(usize), x12: *mut u8) */ .cfi_startproc add x2, x12, x0 jr x11 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(x10: usize, x11: usize, x12: extern "C" fn(usize, usize), x13: *mut u8) */ .cfi_startproc sd x1, -8(x13) sd x2, -16(x13) addi x2, x13, -16 .cfi_def_cfa x2, 16 .cfi_offset x1, -8 .cfi_offset x2, -16 jalr x1, x12, 0 ld x1, 8(x2) .cfi_restore x1 ld x2, 0(x2) .cfi_restore x2 jr x1 .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

j4yc3-mw/Viren

2,080

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/zseries_linux.s

/* Implementation of stack swtiching routines for zSeries LINUX ABI. This ABI is used by the s390x-unknown-linux-gnu target. Documents used: * LINUX for zSeries: ELF Application Binary Interface Supplement (1st ed., 2001) (LNUX-1107-01) * z/Architecture: Principles of Operation (4th ed., 2004) (SA22-7832-03) */ #include "psm.h" .text .globl rust_psm_stack_direction .p2align 4 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 */ .cfi_startproc lghi %r2, STACK_DIRECTION_DESCENDING br %r14 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 4 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: /* extern "C" fn() -> *mut u8 */ .cfi_startproc la %r2, 0(%r15) br %r14 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 4 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(r2: usize, r3: extern "C" fn(usize), r4: *mut u8) */ .cfi_startproc /* FIXME: backtrace does not terminate cleanly for some reason */ lay %r15, -160(%r4) /* FIXME: this is `basr` instead of `br` purely to remove the backtrace link to the caller */ basr %r14, %r3 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 4 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(r2: usize, r3: usize, r4: extern "C" fn(usize, usize), r5: *mut u8) */ .cfi_startproc stmg %r14, %r15, -16(%r5) lay %r15, -176(%r5) .cfi_def_cfa %r15, 176 .cfi_offset %r14, -16 .cfi_offset %r15, -8 basr %r14, %r4 lmg %r14, %r15, 160(%r15) .cfi_restore %r14 .cfi_restore %r15 br %r14 .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

j4yc3-mw/Viren

2,264

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/x86_windows_gnu.s

/* FIXME: this works locally but not on appveyor??!? */ /* NOTE: fastcall calling convention used on all x86 targets */ .text .def @rust_psm_stack_direction@0 .scl 2 .type 32 .endef .globl @rust_psm_stack_direction@0 .p2align 4 @rust_psm_stack_direction@0: /* extern "fastcall" fn() -> u8 (%al) */ .cfi_startproc movb $2, %al # always descending on x86_64 retl .cfi_endproc .def @rust_psm_stack_pointer@0 .scl 2 .type 32 .endef .globl @rust_psm_stack_pointer@0 .p2align 4 @rust_psm_stack_pointer@0: /* extern "fastcall" fn() -> *mut u8 (%rax) */ .cfi_startproc leal 4(%esp), %eax retl .cfi_endproc .def @rust_psm_replace_stack@16 .scl 2 .type 32 .endef .globl @rust_psm_replace_stack@16 .p2align 4 @rust_psm_replace_stack@16: /* extern "fastcall" fn(%ecx: usize, %edx: extern "fastcall" fn(usize), 4(%esp): *mut u8) */ .cfi_startproc /* All we gotta do is set the stack pointer to 4(%esp) & tail-call the callback in %edx Note, that the callee expects the stack to be offset by 4 bytes (normally, a return address would be store there) off the required stack alignment on entry. To offset the stack in such a way we use the `calll` instruction, however it would also be possible to to use plain `jmpl` but would require to adjust the stack manually, which cannot be easily done, because the stack pointer argument is already stored in memory. */ movl 8(%esp), %eax mov %eax, %fs:0x08 movl 4(%esp), %esp mov %esp, %fs:0x04 calll *%edx ud2 .cfi_endproc .def @rust_psm_on_stack@16 .scl 2 .type 32 .endef .globl @rust_psm_on_stack@16 .p2align 4 @rust_psm_on_stack@16: /* extern "fastcall" fn(%ecx: usize, %edx: usize, 4(%esp): extern "fastcall" fn(usize, usize), 8(%esp): *mut u8) */ .cfi_startproc pushl %ebp .cfi_def_cfa %esp, 8 .cfi_offset %ebp, -8 pushl %fs:0x04 .cfi_def_cfa %esp, 12 pushl %fs:0x08 .cfi_def_cfa %esp, 16 movl %esp, %ebp .cfi_def_cfa_register %ebp movl 24(%ebp), %eax movl %eax, %fs:0x08 movl 20(%ebp), %esp movl %esp, %fs:0x04 calll *16(%ebp) movl %ebp, %esp popl %fs:0x08 .cfi_def_cfa %esp, 12 popl %fs:0x04 .cfi_def_cfa %esp, 8 popl %ebp .cfi_def_cfa %esp, 4 retl $12 .cfi_endproc

j4yc3-mw/Viren

1,963

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/powerpc32.s

#include "psm.h" /* FIXME: this probably does not cover all ABIs? Tested with sysv only, possibly works for AIX as well? */ .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 */ .cfi_startproc li 3, STACK_DIRECTION_DESCENDING blr .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: /* extern "C" fn() -> *mut u8 */ .cfi_startproc mr 3, 1 blr .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(3: usize, 4: extern "C" fn(usize), 5: *mut u8) */ .cfi_startproc /* NOTE: perhaps add a debug-assertion for stack alignment? */ addi 5, 5, -16 mr 1, 5 mtctr 4 bctr .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(3: usize, 4: usize, 5: extern "C" fn(usize, usize), 6: *mut u8) */ .cfi_startproc mflr 0 stw 0, -24(6) sub 6, 6, 1 addi 6, 6, -32 stwux 1, 1, 6 .cfi_def_cfa r1, 32 .cfi_offset r1, -32 .cfi_offset lr, -24 mtctr 5 bctrl lwz 0, 8(1) mtlr 0 .cfi_restore lr /* FIXME: after this instruction backtrace breaks until control returns to the caller That being said compiler-generated code has the same issue, so I guess that is fine for now? */ lwz 1, 0(1) .cfi_restore r1 blr .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

j4yc3-mw/Viren

2,218

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/x86_64_windows_gnu.s

.text .def rust_psm_stack_direction .scl 2 .type 32 .endef .globl rust_psm_stack_direction .p2align 4 rust_psm_stack_direction: /* extern "sysv64" fn() -> u8 (%al) */ .cfi_startproc movb $2, %al # always descending on x86_64 retq .cfi_endproc .def rust_psm_stack_pointer .scl 2 .type 32 .endef .globl rust_psm_stack_pointer .p2align 4 rust_psm_stack_pointer: /* extern "sysv64" fn() -> *mut u8 (%rax) */ .cfi_startproc leaq 8(%rsp), %rax retq .cfi_endproc .def rust_psm_replace_stack .scl 2 .type 32 .endef .globl rust_psm_replace_stack .p2align 4 rust_psm_replace_stack: /* extern "sysv64" fn(%rdi: usize, %rsi: extern "sysv64" fn(usize), %rdx: *mut u8, %rcx: *mut u8) */ .cfi_startproc /* All we gotta do is set the stack pointer to %rdx & tail-call the callback in %rsi. 8-byte offset necessary to account for the "return" pointer that would otherwise be placed onto stack with a regular call */ movq %gs:0x08, %rdx movq %gs:0x10, %rcx leaq -8(%rdx), %rsp jmpq *%rsi .cfi_endproc .def rust_psm_on_stack .scl 2 .type 32 .endef .globl rust_psm_on_stack .p2align 4 rust_psm_on_stack: /* extern "sysv64" fn(%rdi: usize, %rsi: usize, %rdx: extern "sysv64" fn(usize, usize), %rcx: *mut u8, %r8: *mut u8) NB: on Windows for SEH to work at all, the pointers in TIB, thread information block, need to be fixed up. Otherwise, it seems that exception mechanism on Windows will not bother looking for exception handlers at *all* if they happen to fall outside the are specified in TIB. This necessitates an API difference from the usual 4-argument signature used elsewhere. FIXME: this needs a catch-all exception handler that aborts in case somebody unwinds into here. */ .cfi_startproc pushq %rbp .cfi_def_cfa %rsp, 16 .cfi_offset %rbp, -16 pushq %gs:0x08 .cfi_def_cfa %rsp, 24 pushq %gs:0x10 .cfi_def_cfa %rsp, 32 movq %rsp, %rbp .cfi_def_cfa_register %rbp movq %rcx, %gs:0x08 movq %r8, %gs:0x10 movq %rcx, %rsp callq *%rdx movq %rbp, %rsp popq %gs:0x10 .cfi_def_cfa %rsp, 24 popq %gs:0x08 .cfi_def_cfa %rsp, 16 popq %rbp .cfi_def_cfa %rsp, 8 retq .cfi_endproc

j4yc3-mw/Viren

2,299

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/arm_aapcs.s

#include "psm.h" .text .syntax unified #if CFG_TARGET_OS_darwin || CFG_TARGET_OS_macos || CFG_TARGET_OS_ios #define GLOBL(fnname) .globl _##fnname #define THUMBTYPE(fnname) .thumb_func _##fnname #define FUNCTION(fnname) _##fnname #define THUMBFN .code 16 #define SIZE(fnname,endlabel) #define FNSTART #define CANTUNWIND #define FNEND #else #define GLOBL(fnname) .globl fnname #define THUMBTYPE(fnname) .type fnname,%function #define FUNCTION(fnname) fnname #define THUMBFN .code 16 #define SIZE(fnname,endlabel) .size fnname,endlabel-fnname #define FNSTART .fnstart #define CANTUNWIND .cantunwind #define FNEND .fnend #endif GLOBL(rust_psm_stack_direction) .p2align 2 THUMBTYPE(rust_psm_stack_direction) THUMBFN FUNCTION(rust_psm_stack_direction): /* extern "C" fn() -> u8 */ FNSTART .cfi_startproc /* movs to support Thumb-1 */ movs r0, #STACK_DIRECTION_DESCENDING bx lr .rust_psm_stack_direction_end: SIZE(rust_psm_stack_direction,.rust_psm_stack_direction_end) .cfi_endproc CANTUNWIND FNEND GLOBL(rust_psm_stack_pointer) .p2align 2 THUMBTYPE(rust_psm_stack_pointer) THUMBFN FUNCTION(rust_psm_stack_pointer): /* extern "C" fn() -> *mut u8 */ FNSTART .cfi_startproc mov r0, sp bx lr .rust_psm_stack_pointer_end: SIZE(rust_psm_stack_pointer,.rust_psm_stack_pointer_end) .cfi_endproc CANTUNWIND FNEND GLOBL(rust_psm_replace_stack) .p2align 2 THUMBTYPE(rust_psm_replace_stack) THUMBFN FUNCTION(rust_psm_replace_stack): /* extern "C" fn(r0: usize, r1: extern "C" fn(usize), r2: *mut u8) */ FNSTART .cfi_startproc /* All we gotta do is set the stack pointer to %rdx & tail-call the callback in %rsi */ mov sp, r2 bx r1 .rust_psm_replace_stack_end: SIZE(rust_psm_replace_stack,.rust_psm_replace_stack_end) .cfi_endproc CANTUNWIND FNEND GLOBL(rust_psm_on_stack) .p2align 2 THUMBTYPE(rust_psm_on_stack) THUMBFN FUNCTION(rust_psm_on_stack): /* extern "C" fn(r0: usize, r1: usize, r2: extern "C" fn(usize, usize), r3: *mut u8) */ FNSTART .cfi_startproc push {r4, lr} .cfi_def_cfa_offset 8 mov r4, sp .cfi_def_cfa_register r4 .cfi_offset lr, -4 .cfi_offset r4, -8 mov sp, r3 blx r2 mov sp, r4 .cfi_restore sp pop {r4, pc} .rust_psm_on_stack_end: SIZE(rust_psm_on_stack,.rust_psm_on_stack_end) .cfi_endproc CANTUNWIND FNEND

j4yc3-mw/Viren

1,938

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/sparc64.s

#include "psm.h" .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 */ .cfi_startproc jmpl %o7 + 8, %g0 mov STACK_DIRECTION_DESCENDING, %o0 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: /* extern "C" fn() -> *mut u8 */ .cfi_startproc jmpl %o7 + 8, %g0 mov %o6, %o0 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(%i0: usize, %i1: extern "C" fn(usize), %i2: *mut u8) */ .cfi_startproc .cfi_def_cfa 0, 0 .cfi_return_column 0 jmpl %o1, %g0 /* WEIRD: Why is the LSB set for the %sp and %fp on SPARC?? */ add %o2, -0x7ff, %o6 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(%i0: usize, %i1: usize, %i2: extern "C" fn(usize, usize), %i3: *mut u8) */ .cfi_startproc /* The fact that locals and saved register windows are offset by 2kB is very nasty property of SPARC architecture and ABI. In this case it forces us to slice off 2kB of the stack space outright for no good reason other than adapting to a botched design. */ save %o3, -0x87f, %o6 .cfi_def_cfa_register %fp .cfi_window_save .cfi_register %r15, %r31 mov %i1, %o1 jmpl %i2, %o7 mov %i0, %o0 ret restore .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

j4yc3-mw/Viren

1,722

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/sparc_sysv.s

#include "psm.h" /* FIXME: this ABI has definitely not been verified at all */ .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 */ .cfi_startproc jmpl %o7 + 8, %g0 mov STACK_DIRECTION_DESCENDING, %o0 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: /* extern "C" fn() -> *mut u8 */ .cfi_startproc jmpl %o7 + 8, %g0 mov %o6, %o0 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(%i0: usize, %i1: extern "C" fn(usize), %i2: *mut u8) */ .cfi_startproc .cfi_def_cfa 0, 0 .cfi_return_column 0 jmpl %o1, %g0 /* WEIRD: Why is the LSB set for the %sp and %fp on SPARC?? */ add %o2, -0x3ff, %o6 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(%i0: usize, %i1: usize, %i2: extern "C" fn(usize, usize), %i3: *mut u8) */ .cfi_startproc save %o3, -0x43f, %o6 .cfi_def_cfa_register %fp .cfi_window_save .cfi_register %r15, %r31 mov %i1, %o1 jmpl %i2, %o7 mov %i0, %o0 ret restore .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

j4yc3-mw/Viren

3,609

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/powerpc64_aix.s

.csect .text[PR],2 .file "powerpc64_aix.s" .globl rust_psm_stack_direction[DS] .globl .rust_psm_stack_direction .align 4 .csect rust_psm_stack_direction[DS],3 .vbyte 8, .rust_psm_stack_direction .vbyte 8, TOC[TC0] .vbyte 8, 0 .csect .text[PR],2 .rust_psm_stack_direction: # extern "C" fn() -> u8 li 3, 2 blr L..rust_psm_stack_direction_end: # Following bytes form the traceback table on AIX. # For specification, see https://www.ibm.com/docs/en/aix/7.2?topic=processor-traceback-tables. # For implementation, see https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp, # `PPCAIXAsmPrinter::emitTracebackTable`. .vbyte 4, 0x00000000 # Traceback table begin, for unwinder to search the table. .byte 0x00 # Version = 0 .byte 0x09 # Language = CPlusPlus, since rust is using C++-like LSDA. .byte 0x20 # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue # +HasTraceBackTableOffset, -IsInternalProcedure # -HasControlledStorage, -IsTOCless # -IsFloatingPointPresent # -IsFloatingPointOperationLogOrAbortEnabled .byte 0x40 # -IsInterruptHandler, +IsFunctionNamePresent, -IsAllocaUsed # OnConditionDirective = 0, -IsCRSaved, -IsLRSaved .byte 0x80 # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 0 .byte 0x00 # -HasExtensionTable, -HasVectorInfo, NumOfGPRsSaved = 0 .byte 0x00 # NumberOfFixedParms = 0 .byte 0x01 # NumberOfFPParms = 0, +HasParmsOnStack .vbyte 4, L..rust_psm_stack_direction_end-.rust_psm_stack_direction #Function size .vbyte 2, 0x0018 # Function name len = 24 .byte "rust_psm_stack_direction" # Function Name .globl rust_psm_stack_pointer[DS] .globl .rust_psm_stack_pointer .align 4 .csect rust_psm_stack_pointer[DS],3 .vbyte 8, .rust_psm_stack_pointer .vbyte 8, TOC[TC0] .vbyte 8, 0 .csect .text[PR],2 .rust_psm_stack_pointer: # extern "C" fn() -> *mut u8 mr 3, 1 blr L..rust_psm_stack_pointer_end: .vbyte 4, 0x00000000 .byte 0x00 .byte 0x09 .byte 0x20 .byte 0x40 .byte 0x80 .byte 0x00 .byte 0x00 .byte 0x01 .vbyte 4, L..rust_psm_stack_pointer_end-.rust_psm_stack_pointer .vbyte 2, 0x0016 .byte "rust_psm_stack_pointer" .globl rust_psm_replace_stack[DS] .globl .rust_psm_replace_stack .align 4 .csect rust_psm_replace_stack[DS],3 .vbyte 8, .rust_psm_replace_stack .vbyte 8, TOC[TC0] .vbyte 8, 0 .csect .text[PR],2 .rust_psm_replace_stack: # extern "C" fn(3: usize, 4: extern "C" fn(usize), 5: *mut u8) # Load the function pointer and toc pointer from TOC and make the call. ld 2, 8(4) ld 4, 0(4) addi 5, 5, -48 mr 1, 5 mtctr 4 bctr L..rust_psm_replace_stack_end: .vbyte 4, 0x00000000 .byte 0x00 .byte 0x09 .byte 0x20 .byte 0x40 .byte 0x80 .byte 0x00 .byte 0x03 .byte 0x01 .vbyte 4, 0x00000000 # Parameter type = i, i, i .vbyte 4, L..rust_psm_replace_stack_end-.rust_psm_replace_stack .vbyte 2, 0x0016 .byte "rust_psm_replace_stack" .globl rust_psm_on_stack[DS] .globl .rust_psm_on_stack .align 4 .csect rust_psm_on_stack[DS],3 .vbyte 8, .rust_psm_on_stack .vbyte 8, TOC[TC0] .vbyte 8, 0 .csect .text[PR],2 .rust_psm_on_stack: # extern "C" fn(3: usize, 4: usize, 5: extern "C" fn(usize, usize), 6: *mut u8) mflr 0 std 2, -72(6) std 0, -8(6) sub 6, 6, 1 addi 6, 6, -112 stdux 1, 1, 6 ld 2, 8(5) ld 5, 0(5) mtctr 5 bctrl ld 2, 40(1) ld 0, 104(1) mtlr 0 ld 1, 0(1) blr L..rust_psm_on_stack_end: .vbyte 4, 0x00000000 .byte 0x00 .byte 0x09 .byte 0x20 .byte 0x41 .byte 0x80 .byte 0x00 .byte 0x04 .byte 0x01 .vbyte 4, 0x00000000 # Parameter type = i, i, i, i .vbyte 4, L..rust_psm_on_stack_end-.rust_psm_on_stack .vbyte 2, 0x0011 .byte "rust_psm_on_stack" .toc

j4yc3-mw/Viren

2,557

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/x86.s

#include "psm.h" /* NOTE: fastcall calling convention used on all x86 targets */ .text #if CFG_TARGET_OS_darwin || CFG_TARGET_OS_macos || CFG_TARGET_OS_ios #define GLOBL(fnname) .globl _##fnname #define TYPE(fnname) #define FUNCTION(fnname) _##fnname #define SIZE(fnname,endlabel) #else #define GLOBL(fnname) .globl fnname #define TYPE(fnname) .type fnname,@function #define FUNCTION(fnname) fnname #define SIZE(fnname,endlabel) .size fnname,endlabel-fnname #endif GLOBL(rust_psm_stack_direction) .p2align 4 TYPE(rust_psm_stack_direction) FUNCTION(rust_psm_stack_direction): /* extern "fastcall" fn() -> u8 (%al) */ .cfi_startproc movb $STACK_DIRECTION_DESCENDING, %al # always descending on x86_64 retl .rust_psm_stack_direction_end: SIZE(rust_psm_stack_direction,.rust_psm_stack_direction_end) .cfi_endproc GLOBL(rust_psm_stack_pointer) .p2align 4 TYPE(rust_psm_stack_pointer) FUNCTION(rust_psm_stack_pointer): /* extern "fastcall" fn() -> *mut u8 (%rax) */ .cfi_startproc leal 4(%esp), %eax retl .rust_psm_stack_pointer_end: SIZE(rust_psm_stack_pointer,.rust_psm_stack_pointer_end) .cfi_endproc GLOBL(rust_psm_replace_stack) .p2align 4 TYPE(rust_psm_replace_stack) FUNCTION(rust_psm_replace_stack): /* extern "fastcall" fn(%ecx: usize, %edx: extern "fastcall" fn(usize), 4(%esp): *mut u8) */ .cfi_startproc /* All we gotta do is set the stack pointer to 4(%esp) & tail-call the callback in %edx Note, that the callee expects the stack to be offset by 4 bytes (normally, a return address would be store there) off the required stack alignment on entry. To offset the stack in such a way we use the `calll` instruction, however it would also be possible to to use plain `jmpl` but would require to adjust the stack manually, which cannot be easily done, because the stack pointer argument is already stored in memory. */ movl 4(%esp), %esp calll *%edx ud2 .rust_psm_replace_stack_end: SIZE(rust_psm_replace_stack,.rust_psm_replace_stack_end) .cfi_endproc GLOBL(rust_psm_on_stack) .p2align 4 TYPE(rust_psm_on_stack) FUNCTION(rust_psm_on_stack): /* extern "fastcall" fn(%ecx: usize, %edx: usize, 4(%esp): extern "fastcall" fn(usize, usize), 8(%esp): *mut u8) */ .cfi_startproc pushl %ebp .cfi_def_cfa %esp, 8 .cfi_offset %ebp, -8 movl %esp, %ebp .cfi_def_cfa_register %ebp movl 12(%ebp), %esp calll *8(%ebp) movl %ebp, %esp popl %ebp .cfi_def_cfa %esp, 4 retl $8 .rust_psm_on_stack_end: SIZE(rust_psm_on_stack,.rust_psm_on_stack_end) .cfi_endproc

j4yc3-mw/Viren

2,149

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/mips_eabi.s

/* Not only MIPS has 20 different ABIs... nobody tells anybody what specific variant of which ABI is used where. This is an "EABI" implementation based on the following page: http://www.cygwin.com/ml/binutils/2003-06/msg00436.html */ #include "psm.h" .set noreorder /* we’ll manage the delay slots on our own, thanks! */ .text .abicalls .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function .ent rust_psm_stack_direction /* extern "C" fn() -> u8 */ rust_psm_stack_direction: .cfi_startproc jr $31 addiu $2, $zero, STACK_DIRECTION_DESCENDING .end rust_psm_stack_direction .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function .ent rust_psm_stack_pointer /* extern "C" fn() -> *mut u8 */ rust_psm_stack_pointer: .cfi_startproc jr $31 move $2, $29 .end rust_psm_stack_pointer .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function .ent rust_psm_replace_stack /* extern "C" fn(r4: usize, r5: extern "C" fn(usize), r6: *mut u8) */ rust_psm_replace_stack: .cfi_startproc move $25, $5 jr $5 move $29, $6 .end rust_psm_replace_stack .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function .ent rust_psm_on_stack /* extern "C" fn(r4: usize, r5: usize, r6: extern "C" fn(usize), r7: *mut u8) */ rust_psm_on_stack: .cfi_startproc sw $29, -4($7) sw $31, -8($7) .cfi_def_cfa 7, 0 .cfi_offset 31, -8 .cfi_offset 29, -4 move $25, $6 jalr $31, $6 addiu $29, $7, -8 .cfi_def_cfa 29, 8 lw $31, 0($29) .cfi_restore 31 lw $29, 4($29) .cfi_restore 29 jr $31 nop .end rust_psm_on_stack .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

j4yc3-mw/Viren

1,568

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/loongarch64.s

#include "psm.h" .text .globl rust_psm_stack_direction .align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 */ .cfi_startproc li.w $r4, STACK_DIRECTION_DESCENDING jr $r1 .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: /* extern "C" fn() -> *mut u8 */ .cfi_startproc move $r4, $r3 jr $r1 .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(r4: usize, r5: extern "C" fn(usize), r6: *mut u8) */ .cfi_startproc move $r3, $r6 jr $r5 .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(r4: usize, r5: usize, r6: extern "C" fn(usize, usize), r7: *mut u8) */ .cfi_startproc st.d $r1, $r7, -8 st.d $r3, $r7, -16 addi.d $r3, $r7, -16 .cfi_def_cfa 3, 16 .cfi_offset 1, -8 .cfi_offset 3, -16 jirl $r1, $r6, 0 ld.d $r1, $r3, 8 .cfi_restore 1 ld.d $r3, $r3, 0 .cfi_restore 3 jr $r1 .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

j4yc3-mw/Viren

2,137

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/aarch_aapcs64.s

#include "psm.h" .text #if CFG_TARGET_OS_darwin || CFG_TARGET_OS_macos || CFG_TARGET_OS_ios #define GLOBL(fnname) .globl _##fnname #define TYPE(fnname) #define FUNCTION(fnname) _##fnname #define SIZE(fnname,endlabel) #elif CFG_TARGET_OS_windows #define GLOBL(fnname) .globl fnname #define TYPE(fnname) #define FUNCTION(fnname) fnname #define SIZE(fnname,endlabel) #else #define GLOBL(fnname) .globl fnname #define TYPE(fnname) .type fnname,@function #define FUNCTION(fnname) fnname #define SIZE(fnname,endlabel) .size fnname,endlabel-fnname #endif GLOBL(rust_psm_stack_direction) .p2align 2 TYPE(rust_psm_stack_direction) FUNCTION(rust_psm_stack_direction): /* extern "C" fn() -> u8 */ .cfi_startproc orr w0, wzr, #STACK_DIRECTION_DESCENDING ret .rust_psm_stack_direction_end: SIZE(rust_psm_stack_direction,.rust_psm_stack_direction_end) .cfi_endproc GLOBL(rust_psm_stack_pointer) .p2align 2 TYPE(rust_psm_stack_pointer) FUNCTION(rust_psm_stack_pointer): /* extern "C" fn() -> *mut u8 */ .cfi_startproc mov x0, sp ret .rust_psm_stack_pointer_end: SIZE(rust_psm_stack_pointer,.rust_psm_stack_pointer_end) .cfi_endproc GLOBL(rust_psm_replace_stack) .p2align 2 TYPE(rust_psm_replace_stack) FUNCTION(rust_psm_replace_stack): /* extern "C" fn(r0: usize, r1: extern "C" fn(usize), r2: *mut u8) */ .cfi_startproc /* All we gotta do is set the stack pointer to %rdx & tail-call the callback in %rsi */ mov sp, x2 br x1 .rust_psm_replace_stack_end: SIZE(rust_psm_replace_stack,.rust_psm_replace_stack_end) .cfi_endproc GLOBL(rust_psm_on_stack) .p2align 2 TYPE(rust_psm_on_stack) FUNCTION(rust_psm_on_stack): /* extern "C" fn(r0: usize, r1: usize, r2: extern "C" fn(usize, usize), r3: *mut u8) */ .cfi_startproc stp x29, x30, [sp, #-16]! .cfi_def_cfa sp, 16 mov x29, sp .cfi_def_cfa x29, 16 .cfi_offset x29, -16 .cfi_offset x30, -8 mov sp, x3 blr x2 mov sp, x29 .cfi_def_cfa sp, 16 ldp x29, x30, [sp], #16 .cfi_def_cfa sp, 0 .cfi_restore x29 .cfi_restore x30 ret .rust_psm_on_stack_end: SIZE(rust_psm_on_stack,.rust_psm_on_stack_end) .cfi_endproc

j4yc3-mw/Viren

2,144

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/mips64_eabi.s

/* Not only MIPS has 20 different ABIs... nobody tells anybody what specific variant of which ABI is used where. This is an "EABI" implementation based on the following page: http://www.cygwin.com/ml/binutils/2003-06/msg00436.html */ #include "psm.h" .set noreorder /* we’ll manage the delay slots on our own, thanks! */ .text .globl rust_psm_stack_direction .p2align 3 .type rust_psm_stack_direction,@function .ent rust_psm_stack_direction /* extern "C" fn() -> u8 */ rust_psm_stack_direction: .cfi_startproc jr $31 addiu $2, $zero, STACK_DIRECTION_DESCENDING .end rust_psm_stack_direction .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 3 .type rust_psm_stack_pointer,@function .ent rust_psm_stack_pointer /* extern "C" fn() -> *mut u8 */ rust_psm_stack_pointer: .cfi_startproc jr $31 move $2, $29 .end rust_psm_stack_pointer .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 3 .type rust_psm_replace_stack,@function .ent rust_psm_replace_stack /* extern "C" fn(r4: usize, r5: extern "C" fn(usize), r6: *mut u8) */ rust_psm_replace_stack: .cfi_startproc move $25, $5 jr $5 move $29, $6 .end rust_psm_replace_stack .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc .globl rust_psm_on_stack .p2align 3 .type rust_psm_on_stack,@function .ent rust_psm_on_stack /* extern "C" fn(r4: usize, r5: usize, r6: extern "C" fn(usize), r7: *mut u8) */ rust_psm_on_stack: .cfi_startproc sd $29, -8($7) sd $31, -16($7) .cfi_def_cfa 7, 0 .cfi_offset 31, -16 .cfi_offset 29, -8 move $25, $6 jalr $31, $6 daddiu $29, $7, -16 .cfi_def_cfa 29, 16 ld $31, 0($29) .cfi_restore 31 ld $29, 8($29) .cfi_restore 29 jr $31 nop .end rust_psm_on_stack .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

j4yc3-mw/Viren

1,694

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/wasm32.s

#include "psm.h" # Note that this function is not compiled when this package is uploaded to # crates.io, this source is only here as a reference for how the corresponding # wasm32.o was generated. This file can be compiled with: # # cpp psm/src/arch/wasm32.s | llvm-mc -o psm/src/arch/wasm32.o --arch=wasm32 -filetype=obj # # where you'll want to ensure that `llvm-mc` is from a relatively recent # version of LLVM. .globaltype __stack_pointer, i32 .globl rust_psm_stack_direction .type rust_psm_stack_direction,@function rust_psm_stack_direction: .functype rust_psm_stack_direction () -> (i32) i32.const STACK_DIRECTION_DESCENDING end_function .globl rust_psm_stack_pointer .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: .functype rust_psm_stack_pointer () -> (i32) global.get __stack_pointer end_function .globl rust_psm_on_stack .type rust_psm_on_stack,@function rust_psm_on_stack: .functype rust_psm_on_stack (i32, i32, i32, i32) -> () # get our new stack argument, then save the old stack # pointer into that local local.get 3 global.get __stack_pointer local.set 3 global.set __stack_pointer # Call our indirect function specified local.get 0 local.get 1 local.get 2 call_indirect (i32, i32) -> () # restore the stack pointer before returning local.get 3 global.set __stack_pointer end_function .globl rust_psm_replace_stack .type rust_psm_replace_stack,@function rust_psm_replace_stack: .functype rust_psm_replace_stack (i32, i32, i32) -> () local.get 2 global.set __stack_pointer local.get 0 local.get 1 call_indirect (i32) -> () unreachable end_function

j4yc3-mw/Viren

2,541

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/powerpc64.s

/* Implementation of the AIX-like PowerPC ABI. Seems to be used by the big-endian PowerPC targets. The following references were used during the implementation of this code: https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.alangref/idalangref_rntime_stack.htm https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.alangref/idalangref_reg_use_conv.htm https://www.ibm.com/developerworks/library/l-powasm4/index.html */ #include "psm.h" .text .globl rust_psm_stack_direction .p2align 2 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 */ .cfi_startproc li 3, STACK_DIRECTION_DESCENDING blr .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 2 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: /* extern "C" fn() -> *mut u8 */ .cfi_startproc mr 3, 1 blr .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 2 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(3: usize, 4: extern "C" fn(usize), 5: *mut u8) */ .cfi_startproc ld 2, 8(4) ld 4, 0(4) /* do not allocate the whole 112-byte sized frame, we know wont be used */ addi 5, 5, -48 mr 1, 5 mtctr 4 bctr .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 2 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(3: usize, 4: usize, 5: extern "C" fn(usize, usize), 6: *mut u8) */ .cfi_startproc mflr 0 std 2, -72(6) std 0, -8(6) sub 6, 6, 1 addi 6, 6, -112 stdux 1, 1, 6 .cfi_def_cfa r1, 112 .cfi_offset r1, -112 .cfi_offset r2, -72 .cfi_offset lr, -8 /* load the function pointer from TOC and make the call */ ld 2, 8(5) ld 5, 0(5) mtctr 5 bctrl ld 2, 40(1) .cfi_restore r2 ld 0, 104(1) mtlr 0 .cfi_restore lr /* FIXME: after this instruction backtrace breaks until control returns to the caller. That being said compiler-generated code has the same issue, so I guess that is fine for now? */ ld 1, 0(1) .cfi_restore r1 blr .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

j4yc3-mw/Viren

2,045

.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/psm-0.1.21/src/arch/powerpc64_openpower.s

/* Implementation of stack swtiching routines for OpenPOWER 64-bit ELF ABI The specification can be found at http://openpowerfoundation.org/wp-content/uploads/resources/leabi/content/ch_preface.html This ABI is usually used by the ppc64le targets. */ #include "psm.h" .text .abiversion 2 .globl rust_psm_stack_direction .p2align 4 .type rust_psm_stack_direction,@function rust_psm_stack_direction: /* extern "C" fn() -> u8 */ .cfi_startproc li 3, STACK_DIRECTION_DESCENDING blr .rust_psm_stack_direction_end: .size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction .cfi_endproc .globl rust_psm_stack_pointer .p2align 4 .type rust_psm_stack_pointer,@function rust_psm_stack_pointer: /* extern "C" fn() -> *mut u8 */ .cfi_startproc mr 3, 1 blr .rust_psm_stack_pointer_end: .size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer .cfi_endproc .globl rust_psm_replace_stack .p2align 4 .type rust_psm_replace_stack,@function rust_psm_replace_stack: /* extern "C" fn(3: usize, 4: extern "C" fn(usize), 5: *mut u8) */ .cfi_startproc addi 5, 5, -32 mtctr 4 mr 12, 4 mr 1, 5 bctr .rust_psm_replace_stack_end: .size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack .cfi_endproc .globl rust_psm_on_stack .p2align 4 .type rust_psm_on_stack,@function rust_psm_on_stack: /* extern "C" fn(3: usize, 4: usize, 5: extern "C" fn(usize, usize), 6: *mut u8) */ .cfi_startproc mflr 0 std 0, -8(6) std 2, -24(6) sub 6, 6, 1 addi 6, 6, -48 stdux 1, 1, 6 .cfi_def_cfa r1, 48 .cfi_offset r1, -48 .cfi_offset r2, -24 .cfi_offset lr, -8 mr 12, 5 mtctr 5 bctrl ld 2, 24(1) .cfi_restore r2 ld 0, 40(1) mtlr 0 .cfi_restore lr /* FIXME: after this instructin backtrace breaks until control returns to the caller */ ld 1, 0(1) blr .rust_psm_on_stack_end: .size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack .cfi_endproc

jack0682/CSAv1

8,352

third_party/opencv-3.4.17/3rdparty/libpng/arm/filter_neon.S

/* filter_neon.S - NEON optimised filter functions * * Copyright (c) 2018 Cosmin Truta * Copyright (c) 2014,2017 Glenn Randers-Pehrson * Written by Mans Rullgard, 2011. * * This code is released under the libpng license. * For conditions of distribution and use, see the disclaimer * and license in png.h */ /* This is required to get the symbol renames, which are #defines, and the * definitions (or not) of PNG_ARM_NEON_OPT and PNG_ARM_NEON_IMPLEMENTATION. */ #define PNG_VERSION_INFO_ONLY #include "../pngpriv.h" #if (defined(__linux__) || defined(__FreeBSD__)) && defined(__ELF__) .section .note.GNU-stack,"",%progbits /* mark stack as non-executable */ #endif #ifdef PNG_READ_SUPPORTED /* Assembler NEON support - only works for 32-bit ARM (i.e. it does not work for * ARM64). The code in arm/filter_neon_intrinsics.c supports ARM64, however it * only works if -mfpu=neon is specified on the GCC command line. See pngpriv.h * for the logic which sets PNG_USE_ARM_NEON_ASM: */ #if PNG_ARM_NEON_IMPLEMENTATION == 2 /* hand-coded assembler */ #if PNG_ARM_NEON_OPT > 0 #ifdef __ELF__ # define ELF #else # define ELF @ #endif .arch armv7-a .fpu neon .macro func name, export=0 .macro endfunc ELF .size \name, . - \name .endfunc .purgem endfunc .endm .text /* Explicitly specifying alignment here because some versions of * GAS don't align code correctly. This is harmless in correctly * written versions of GAS. */ .align 2 .if \export .global \name .endif ELF .type \name, STT_FUNC .func \name \name: .endm func png_read_filter_row_sub4_neon, export=1 ldr r3, [r0, #4] @ rowbytes vmov.i8 d3, #0 1: vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] vadd.u8 d0, d3, d4 vadd.u8 d1, d0, d5 vadd.u8 d2, d1, d6 vadd.u8 d3, d2, d7 vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]! subs r3, r3, #16 bgt 1b bx lr endfunc func png_read_filter_row_sub3_neon, export=1 ldr r3, [r0, #4] @ rowbytes vmov.i8 d3, #0 mov r0, r1 mov r2, #3 mov r12, #12 vld1.8 {q11}, [r0], r12 1: vext.8 d5, d22, d23, #3 vadd.u8 d0, d3, d22 vext.8 d6, d22, d23, #6 vadd.u8 d1, d0, d5 vext.8 d7, d23, d23, #1 vld1.8 {q11}, [r0], r12 vst1.32 {d0[0]}, [r1,:32], r2 vadd.u8 d2, d1, d6 vst1.32 {d1[0]}, [r1], r2 vadd.u8 d3, d2, d7 vst1.32 {d2[0]}, [r1], r2 vst1.32 {d3[0]}, [r1], r2 subs r3, r3, #12 bgt 1b bx lr endfunc func png_read_filter_row_up_neon, export=1 ldr r3, [r0, #4] @ rowbytes 1: vld1.8 {q0}, [r1,:128] vld1.8 {q1}, [r2,:128]! vadd.u8 q0, q0, q1 vst1.8 {q0}, [r1,:128]! subs r3, r3, #16 bgt 1b bx lr endfunc func png_read_filter_row_avg4_neon, export=1 ldr r12, [r0, #4] @ rowbytes vmov.i8 d3, #0 1: vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] vld4.32 {d16[],d17[],d18[],d19[]},[r2,:128]! vhadd.u8 d0, d3, d16 vadd.u8 d0, d0, d4 vhadd.u8 d1, d0, d17 vadd.u8 d1, d1, d5 vhadd.u8 d2, d1, d18 vadd.u8 d2, d2, d6 vhadd.u8 d3, d2, d19 vadd.u8 d3, d3, d7 vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]! subs r12, r12, #16 bgt 1b bx lr endfunc func png_read_filter_row_avg3_neon, export=1 push {r4,lr} ldr r12, [r0, #4] @ rowbytes vmov.i8 d3, #0 mov r0, r1 mov r4, #3 mov lr, #12 vld1.8 {q11}, [r0], lr 1: vld1.8 {q10}, [r2], lr vext.8 d5, d22, d23, #3 vhadd.u8 d0, d3, d20 vext.8 d17, d20, d21, #3 vadd.u8 d0, d0, d22 vext.8 d6, d22, d23, #6 vhadd.u8 d1, d0, d17 vext.8 d18, d20, d21, #6 vadd.u8 d1, d1, d5 vext.8 d7, d23, d23, #1 vld1.8 {q11}, [r0], lr vst1.32 {d0[0]}, [r1,:32], r4 vhadd.u8 d2, d1, d18 vst1.32 {d1[0]}, [r1], r4 vext.8 d19, d21, d21, #1 vadd.u8 d2, d2, d6 vhadd.u8 d3, d2, d19 vst1.32 {d2[0]}, [r1], r4 vadd.u8 d3, d3, d7 vst1.32 {d3[0]}, [r1], r4 subs r12, r12, #12 bgt 1b pop {r4,pc} endfunc .macro paeth rx, ra, rb, rc vaddl.u8 q12, \ra, \rb @ a + b vaddl.u8 q15, \rc, \rc @ 2*c vabdl.u8 q13, \rb, \rc @ pa vabdl.u8 q14, \ra, \rc @ pb vabd.u16 q15, q12, q15 @ pc vcle.u16 q12, q13, q14 @ pa <= pb vcle.u16 q13, q13, q15 @ pa <= pc vcle.u16 q14, q14, q15 @ pb <= pc vand q12, q12, q13 @ pa <= pb && pa <= pc vmovn.u16 d28, q14 vmovn.u16 \rx, q12 vbsl d28, \rb, \rc vbsl \rx, \ra, d28 .endm func png_read_filter_row_paeth4_neon, export=1 ldr r12, [r0, #4] @ rowbytes vmov.i8 d3, #0 vmov.i8 d20, #0 1: vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] vld4.32 {d16[],d17[],d18[],d19[]},[r2,:128]! paeth d0, d3, d16, d20 vadd.u8 d0, d0, d4 paeth d1, d0, d17, d16 vadd.u8 d1, d1, d5 paeth d2, d1, d18, d17 vadd.u8 d2, d2, d6 paeth d3, d2, d19, d18 vmov d20, d19 vadd.u8 d3, d3, d7 vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]! subs r12, r12, #16 bgt 1b bx lr endfunc func png_read_filter_row_paeth3_neon, export=1 push {r4,lr} ldr r12, [r0, #4] @ rowbytes vmov.i8 d3, #0 vmov.i8 d4, #0 mov r0, r1 mov r4, #3 mov lr, #12 vld1.8 {q11}, [r0], lr 1: vld1.8 {q10}, [r2], lr paeth d0, d3, d20, d4 vext.8 d5, d22, d23, #3 vadd.u8 d0, d0, d22 vext.8 d17, d20, d21, #3 paeth d1, d0, d17, d20 vst1.32 {d0[0]}, [r1,:32], r4 vext.8 d6, d22, d23, #6 vadd.u8 d1, d1, d5 vext.8 d18, d20, d21, #6 paeth d2, d1, d18, d17 vext.8 d7, d23, d23, #1 vld1.8 {q11}, [r0], lr vst1.32 {d1[0]}, [r1], r4 vadd.u8 d2, d2, d6 vext.8 d19, d21, d21, #1 paeth d3, d2, d19, d18 vst1.32 {d2[0]}, [r1], r4 vmov d4, d19 vadd.u8 d3, d3, d7 vst1.32 {d3[0]}, [r1], r4 subs r12, r12, #12 bgt 1b pop {r4,pc} endfunc #endif /* PNG_ARM_NEON_OPT > 0 */ #endif /* PNG_ARM_NEON_IMPLEMENTATION == 2 (assembler) */ #endif /* READ */

JackMyles/BASIC-to-ASM-Compiler

1,801

runtime/call_check.s

# This is a custom entry point that calls basic_main() for a compiled BASIC program # and verifies that it satisfies the x86-64 calling convention. # This means that the callee-save registers and all memory above %rsp # at the start of basic_main() must not be modified. .rodata check_failed_msg: .string "x86-64 calling convention violated\n" .text .globl _start _start: # Put 32 KB of canary data on the stack movq $-0x1000, %rcx leaq (%rsp, %rcx, 8), %rsp movq %rsp, %rdi movq $0x1BF532C94A760E8D, %rax negq %rcx cld rep stosq # Put canary values in callee-save registers movq $0xB42607DE9FA358C1, %rbx movq $0x412087E6FAB9C53D, %rbp movq $0x514D387C6AE02B9F, %r12 movq $0xE5BF4238C1DA9760, %r13 movq $0xCB9FD8524A630E71, %r14 movq $0xD0B5F947CEA23618, %r15 call basic_main # Check that callee-save registers haven't changed movq $0xB42607DE9FA358C1, %rax cmpq %rax, %rbx jne check_failed movq $0x412087E6FAB9C53D, %rax cmpq %rax, %rbp jne check_failed movq $0x514D387C6AE02B9F, %rax cmpq %rax, %r12 jne check_failed movq $0xE5BF4238C1DA9760, %rax cmpq %rax, %r13 jne check_failed movq $0xCB9FD8524A630E71, %rax cmpq %rax, %r14 jne check_failed movq $0xD0B5F947CEA23618, %rax cmpq %rax, %r15 jne check_failed # Check canary values on stack movq %rsp, %rdi movq $0x1BF532C94A760E8D, %rax movl $0x1000, %ecx repe scasq jne check_failed # Checks succeeded; exit with code 0 movl $0, %edi call exit@plt # Checks failed; print a warning message and exit with error status check_failed: leaq check_failed_msg(%rip), %rdi movq stderr(%rip), %rsi call fputs@plt movl $1, %edi call exit@plt

JackMyles/BASIC-to-ASM-Compiler

42

runtime/print_int_mock.s

.text .globl print_int print_int: ret

JackMyles/BASIC-to-ASM-Compiler

643

runtime/print_int.s

.rodata int_format: .string "%ld\n" .text .globl print_int print_int: movq %rdi, %rsi leaq int_format(%rip), %rdi # LABEL(%rip) computes the address of LABEL relative to %rip movb $0, %al # %al stores the number of float arguments to printf() call printf@plt # Clobber all caller-save registers movq $0x6A2CFE91073BD845, %rax movq $0x03BAD7C14F2E6589, %rdi movq $0x5D41EA960C72F8B3, %rsi movq $0xEC364B2D5A7F9810, %rdx movq $0xFC85AD49320BE167, %rcx movq $0x529A48CDB7163E0F, %r8 movq $0x92E1587A4BDCF630, %r9 movq $0x47DC36501F89AEB2, %r10 movq $0xAF4B29785C61ED30, %r11 ret

JacobInwald/courseworks

182

Compiling Techniques/coursework-3-JacobInwald/tests/riscv/parser/labels.s

# RUN: ../../../riscv/parser.py %s | filecheck %s foo: add a0, a0, a0 # CHECK: foo: # CHECK-NEXT: add a0, a0, a0 bar: add a0, a0, a0 # CHECK: bar: # CHECK-NEXT: add a0, a0, a0

JacobInwald/courseworks

7,024

Compiling Techniques/coursework-3-JacobInwald/tests/riscv/parser/ops.s

# RUN: ../../../riscv/parser.py %s | filecheck %s loadbyte: lb t0, t2 lb t0, t2, 0 lb t0, t2, 12 lb t0, t2, -34 lb t0, 0(t2) lb t0, 56(t2) lb t0, -78(t2) # CHECK: loadbyte: # CHECK-NEXT: lb t0, 0(t2) # CHECK-NEXT: lb t0, 0(t2) # CHECK-NEXT: lb t0, 12(t2) # CHECK-NEXT: lb t0, -34(t2) # CHECK-NEXT: lb t0, 0(t2) # CHECK-NEXT: lb t0, 56(t2) # CHECK-NEXT: lb t0, -78(t2) loadbyteunsigned: lbu t0, t2 lbu t0, t2, 0 lbu t0, t2, 12 lbu t0, t2, -34 lbu t0, 0(t2) lbu t0, 56(t2) lbu t0, -78(t2) # CHECK: loadbyteunsigned: # CHECK-NEXT: lbu t0, 0(t2) # CHECK-NEXT: lbu t0, 0(t2) # CHECK-NEXT: lbu t0, 12(t2) # CHECK-NEXT: lbu t0, -34(t2) # CHECK-NEXT: lbu t0, 0(t2) # CHECK-NEXT: lbu t0, 56(t2) # CHECK-NEXT: lbu t0, -78(t2) loadhalf: lh t0, t2 lh t0, t2, 0 lh t0, t2, 12 lh t0, t2, -34 lh t0, 0(t2) lh t0, 56(t2) lh t0, -78(t2) # CHECK: loadhalf: # CHECK-NEXT: lh t0, 0(t2) # CHECK-NEXT: lh t0, 0(t2) # CHECK-NEXT: lh t0, 12(t2) # CHECK-NEXT: lh t0, -34(t2) # CHECK-NEXT: lh t0, 0(t2) # CHECK-NEXT: lh t0, 56(t2) # CHECK-NEXT: lh t0, -78(t2) loadhalfunsigned: lhu t0, t2 lhu t0, t2, 0 lhu t0, t2, 12 lhu t0, t2, -34 lhu t0, 0(t2) lhu t0, 56(t2) lhu t0, -78(t2) # CHECK: loadhalfunsigned: # CHECK-NEXT: lhu t0, 0(t2) # CHECK-NEXT: lhu t0, 0(t2) # CHECK-NEXT: lhu t0, 12(t2) # CHECK-NEXT: lhu t0, -34(t2) # CHECK-NEXT: lhu t0, 0(t2) # CHECK-NEXT: lhu t0, 56(t2) # CHECK-NEXT: lhu t0, -78(t2) loadword: lw t0, t2 lw t0, t2, 0 lw t0, t2, 12 lw t0, t2, -34 lw t0, 0(t2) lw t0, 56(t2) lw t0, -78(t2) # CHECK: loadword: # CHECK-NEXT: lw t0, 0(t2) # CHECK-NEXT: lw t0, 0(t2) # CHECK-NEXT: lw t0, 12(t2) # CHECK-NEXT: lw t0, -34(t2) # CHECK-NEXT: lw t0, 0(t2) # CHECK-NEXT: lw t0, 56(t2) # CHECK-NEXT: lw t0, -78(t2) storebyte: sb t0, t2 sb t0, t2, 0 sb t0, t2, 12 sb t0, t2, -34 sb t0, 0(t2) sb t0, 56(t2) sb t0, -78(t2) # CHECK: storebyte: # CHECK-NEXT: sb t0, 0(t2) # CHECK-NEXT: sb t0, 0(t2) # CHECK-NEXT: sb t0, 12(t2) # CHECK-NEXT: sb t0, -34(t2) # CHECK-NEXT: sb t0, 0(t2) # CHECK-NEXT: sb t0, 56(t2) # CHECK-NEXT: sb t0, -78(t2) storehalf: sh t0, t2 sh t0, t2, 0 sh t0, t2, 12 sh t0, t2, -34 sh t0, 0(t2) sh t0, 56(t2) sh t0, -78(t2) # CHECK: storehalf: # CHECK-NEXT: sh t0, 0(t2) # CHECK-NEXT: sh t0, 0(t2) # CHECK-NEXT: sh t0, 12(t2) # CHECK-NEXT: sh t0, -34(t2) # CHECK-NEXT: sh t0, 0(t2) # CHECK-NEXT: sh t0, 56(t2) # CHECK-NEXT: sh t0, -78(t2) storeword: sw t0, t2 sw t0, t2, 0 sw t0, t2, 12 sw t0, t2, -34 sw t0, 0(t2) sw t0, 56(t2) sw t0, -78(t2) # CHECK: storeword: # CHECK-NEXT: sw t0, 0(t2) # CHECK-NEXT: sw t0, 0(t2) # CHECK-NEXT: sw t0, 12(t2) # CHECK-NEXT: sw t0, -34(t2) # CHECK-NEXT: sw t0, 0(t2) # CHECK-NEXT: sw t0, 56(t2) # CHECK-NEXT: sw t0, -78(t2) branches: beq t0, t2, 0 beq t0, t2, 12 beq t0, t2, -34 beq t0, t2, branches bne t0, t2, 0 bne t0, t2, 56 bne t0, t2, -78 bne t0, t2, branches blt t0, t2, 0 blt t0, t2, 91 blt t0, t2, -23 blt t0, t2, branches bge t0, t2, 0 bge t0, t2, 45 bge t0, t2, -67 bge t0, t2, branches bltu t0, t2, 0 bltu t0, t2, 89 bltu t0, t2, -12 bltu t0, t2, branches bgeu t0, t2, 0 bgeu t0, t2, 34 bgeu t0, t2, -56 bgeu t0, t2, branches # CHECK: branches # CHECK-NEXT beq t0, t2, 0 # CHECK-NEXT beq t0, t2, 12 # CHECK-NEXT beq t0, t2, -34 # CHECK-NEXT beq t0, t2, branches # CHECK-NEXT bne t0, t2, 0 # CHECK-NEXT bne t0, t2, 56 # CHECK-NEXT bne t0, t2, -78 # CHECK-NEXT bne t0, t2, branches # CHECK-NEXT blt t0, t2, 0 # CHECK-NEXT blt t0, t2, 91 # CHECK-NEXT blt t0, t2, -23 # CHECK-NEXT blt t0, t2, branches # CHECK-NEXT bge t0, t2, 0 # CHECK-NEXT bge t0, t2, 45 # CHECK-NEXT bge t0, t2, -67 # CHECK-NEXT bge t0, t2, branches # CHECK-NEXT bltu t0, t2, 0 # CHECK-NEXT bltu t0, t2, 89 # CHECK-NEXT bltu t0, t2, -12 # CHECK-NEXT bltu t0, t2, branches # CHECK-NEXT bgeu t0, t2, 0 # CHECK-NEXT bgeu t0, t2, 34 # CHECK-NEXT bgeu t0, t2, -56 # CHECK-NEXT bgeu t0, t2, branches shifts: sll t0, t1, t2 slli t0, t1, 0 slli t0, t1, 1 slli t0, t1, 2 srl t0, t1, t2 srli t0, t1, 0 srli t0, t1, 1 srli t0, t1, 2 sra t0, t1, t2 srai t0, t1, 0 srai t0, t1, 1 srai t0, t1, 2 # CHECK: shifts: # CHECK-NEXT: sll t0, t1, t2 # CHECK-NEXT: slli t0, t1, 0 # CHECK-NEXT: slli t0, t1, 1 # CHECK-NEXT: slli t0, t1, 2 # CHECK-NEXT: srl t0, t1, t2 # CHECK-NEXT: srli t0, t1, 0 # CHECK-NEXT: srli t0, t1, 1 # CHECK-NEXT: srli t0, t1, 2 # CHECK-NEXT: sra t0, t1, t2 # CHECK-NEXT: srai t0, t1, 0 # CHECK-NEXT: srai t0, t1, 1 # CHECK-NEXT: srai t0, t1, 2 arithmetic: add t0, t1, t2 addi t0, t1, 0 addi t0, t1, -12 addi t0, t1, -34 sub t0, t1, t2 lui t0, 12 lui t0, -34 auipc t0, 12 auipc t0, -34 # CHECK: arithmetic: # CHECK-NEXT: add t0, t1, t2 # CHECK-NEXT: addi t0, t1, 0 # CHECK-NEXT: addi t0, t1, -12 # CHECK-NEXT: addi t0, t1, -34 # CHECK-NEXT: sub t0, t1, t2 # CHECK-NEXT: lui t0, 12 # CHECK-NEXT: lui t0, -34 # CHECK-NEXT: auipc t0, 12 # CHECK-NEXT: auipc t0, -34 logical: xor t0, t1, t2 xori t0, t1, 0 xori t0, t1, -12 xori t0, t1, -34 or t0, t1, t2 ori t0, t1, 0 ori t0, t1, -12 ori t0, t1, -34 and t0, t1, t2 andi t0, t1, 0 andi t0, t1, -12 andi t0, t1, -34 # CHECK: logical: # CHECK-NEXT: xor t0, t1, t2 # CHECK-NEXT: xori t0, t1, 0 # CHECK-NEXT: xori t0, t1, -12 # CHECK-NEXT: xori t0, t1, -34 # CHECK-NEXT: or t0, t1, t2 # CHECK-NEXT: ori t0, t1, 0 # CHECK-NEXT: ori t0, t1, -12 # CHECK-NEXT: ori t0, t1, -34 # CHECK-NEXT: and t0, t1, t2 # CHECK-NEXT: andi t0, t1, 0 # CHECK-NEXT: andi t0, t1, -12 # CHECK-NEXT: andi t0, t1, -34 compare: slt t0, t1, t2 slti t0, t1, 0 slti t0, t1, -12 slti t0, t1, -34 sltu t0, t1, t2 sltiu t0, t1, 0 sltiu t0, t1, -12 sltiu t0, t1, -34 # CHECK: compare: # CHECK-NEXT: slt t0, t1, t2 # CHECK-NEXT: slti t0, t1, 0 # CHECK-NEXT: slti t0, t1, -12 # CHECK-NEXT: slti t0, t1, -34 # CHECK-NEXT: sltu t0, t1, t2 # CHECK-NEXT: sltiu t0, t1, 0 # CHECK-NEXT: sltiu t0, t1, -12 # CHECK-NEXT: sltiu t0, t1, -34 jumpandlink: jal t0, 0 jal t0, -12 jal t0, 32 jal t0, jumpandlink jalr t0, t1, 0 jalr t0, t1, -12 jalr t0, t1, 32 jalr t0, t1, jumpandlink # CHECK: jumpandlink: # CHECK-NEXT: jal t0, 0 # CHECK-NEXT: jal t0, -12 # CHECK-NEXT: jal t0, 32 # CHECK-NEXT: jal t0, jumpandlink # CHECK-NEXT: jalr t0, t1, 0 # CHECK-NEXT: jalr t0, t1, -12 # CHECK-NEXT: jalr t0, t1, 32 # CHECK-NEXT: jalr t0, t1, jumpandlink multiplicative: mul t0, t1, t2 mulh t0, t1, t2 mulhsu t0, t1, t2 mulhu t0, t1, t2 mulhu t0, t1, t2 div t0, t1, t2 divu t0, t1, t2 rem t0, t1, t2 remu t0, t1, t2 # CHECK: multiplicative: # CHECK-NEXT: mul t0, t1, t2 # CHECK-NEXT: mulh t0, t1, t2 # CHECK-NEXT: mulhsu t0, t1, t2 # CHECK-NEXT: mulhu t0, t1, t2 # CHECK-NEXT: mulhu t0, t1, t2 # CHECK-NEXT: div t0, t1, t2 # CHECK-NEXT: divu t0, t1, t2 # CHECK-NEXT: rem t0, t1, t2 # CHECK-NEXT: remu t0, t1, t2 system: ecall ebreak # CHECK: system: # CHECK-NEXT: ecall # CHECK-NEXT: ebreak

JacobInwald/courseworks

180

Compiling Techniques/coursework-3-JacobInwald/tests/riscv/parser/directives.s

# RUN: ../../../riscv/parser.py %s | filecheck %s .asciz "somestring" # CHECK: .asciz "somestring" .section .text # CHECK: .section .text .global getasm # CHECK: .global getasm

JacobInwald/courseworks

2,427

Compiling Techniques/coursework-3-JacobInwald/tests/riscv/parser/registers.s

# RUN: ../../../riscv/parser.py %s | filecheck %s registers: # CHECK: registers: jal x0, 0 # CHECK-NEXT: jal zero, 0 jal x1, 0 # CHECK-NEXT: jal ra, 0 jal x2, 0 # CHECK-NEXT: jal sp, 0 jal x3, 0 # CHECK-NEXT: jal gp, 0 jal x4, 0 # CHECK-NEXT: jal tp, 0 jal x5, 0 # CHECK-NEXT: jal t0, 0 jal x6, 0 # CHECK-NEXT: jal t1, 0 jal x7, 0 # CHECK-NEXT: jal t2, 0 jal x8, 0 # CHECK-NEXT: jal fp, 0 jal x9, 0 # CHECK-NEXT: jal s1, 0 jal x10, 0 # CHECK-NEXT: jal a0, 0 jal x11, 0 # CHECK-NEXT: jal a1, 0 jal x12, 0 # CHECK-NEXT: jal a2, 0 jal x13, 0 # CHECK-NEXT: jal a3, 0 jal x14, 0 # CHECK-NEXT: jal a4, 0 jal x15, 0 # CHECK-NEXT: jal a5, 0 jal x16, 0 # CHECK-NEXT: jal a6, 0 jal x17, 0 # CHECK-NEXT: jal a7, 0 jal x18, 0 # CHECK-NEXT: jal s2, 0 jal x19, 0 # CHECK-NEXT: jal s3, 0 jal x20, 0 # CHECK-NEXT: jal s4, 0 jal x21, 0 # CHECK-NEXT: jal s5, 0 jal x22, 0 # CHECK-NEXT: jal s6, 0 jal x23, 0 # CHECK-NEXT: jal s7, 0 jal x24, 0 # CHECK-NEXT: jal s8, 0 jal x25, 0 # CHECK-NEXT: jal s9, 0 jal x26, 0 # CHECK-NEXT: jal s10, 0 jal x27, 0 # CHECK-NEXT: jal s11, 0 jal x28, 0 # CHECK-NEXT: jal t3, 0 jal x29, 0 # CHECK-NEXT: jal t4, 0 jal x30, 0 # CHECK-NEXT: jal t5, 0 jal x31, 0 # CHECK-NEXT: jal t6, 0 abinames: # CHECK-NEXT: abinames: jal zero, 0 # CHECK-NEXT: jal zero, 0 jal ra, 0 # CHECK-NEXT: jal ra, 0 jal sp, 0 # CHECK-NEXT: jal sp, 0 jal gp, 0 # CHECK-NEXT: jal gp, 0 jal tp, 0 # CHECK-NEXT: jal tp, 0 jal t0, 0 # CHECK-NEXT: jal t0, 0 jal t1, 0 # CHECK-NEXT: jal t1, 0 jal t2, 0 # CHECK-NEXT: jal t2, 0 jal fp, 0 # CHECK-NEXT: jal fp, 0 jal s0, 0 # CHECK-NEXT: jal fp, 0 jal s1, 0 # CHECK-NEXT: jal s1, 0 jal a0, 0 # CHECK-NEXT: jal a0, 0 jal a1, 0 # CHECK-NEXT: jal a1, 0 jal a2, 0 # CHECK-NEXT: jal a2, 0 jal a3, 0 # CHECK-NEXT: jal a3, 0 jal a4, 0 # CHECK-NEXT: jal a4, 0 jal a5, 0 # CHECK-NEXT: jal a5, 0 jal a6, 0 # CHECK-NEXT: jal a6, 0 jal a7, 0 # CHECK-NEXT: jal a7, 0 jal s2, 0 # CHECK-NEXT: jal s2, 0 jal s3, 0 # CHECK-NEXT: jal s3, 0 jal s4, 0 # CHECK-NEXT: jal s4, 0 jal s5, 0 # CHECK-NEXT: jal s5, 0 jal s6, 0 # CHECK-NEXT: jal s6, 0 jal s7, 0 # CHECK-NEXT: jal s7, 0 jal s8, 0 # CHECK-NEXT: jal s8, 0 jal s9, 0 # CHECK-NEXT: jal s9, 0 jal s10, 0 # CHECK-NEXT: jal s10, 0 jal s11, 0 # CHECK-NEXT: jal s11, 0 jal t3, 0 # CHECK-NEXT: jal t3, 0 jal t4, 0 # CHECK-NEXT: jal t4, 0 jal t5, 0 # CHECK-NEXT: jal t5, 0 jal t6, 0 # CHECK-NEXT: jal t6, 0

JacobInwald/courseworks

2,779

Compiling Techniques/coursework-3-JacobInwald/tests/riscv/parser/pseudoops.s

# RUN: ../../../riscv/parser.py %s | filecheck %s nop: nop # CHECK: nop: # CHECK-NEXT: nop li: li t0, 0 li t0, 12345 li t0, -67890 # CHECK: li: # CHECK-NEXT: li t0, 0 # CHECK-NEXT: li t0, 12345 # CHECK-NEXT: li t0, -67890 mv: mv t0, t0 # CHECK: mv: # CHECK-NEXT: mv t0, t0 not: not t0, t0 # CHECK: not: # CHECK-NEXT: not t0, t0 neg: neg t0, t0 # CHECK: neg: # CHECK-NEXT: neg t0, t0 negw: negw t0, t0 # CHECK: negw: # CHECK-NEXT: negw t0, t0 seqz: seqz t0, t0 # CHECK: seqz: # CHECK-NEXT: seqz t0, t0 snez: snez t0, t0 # CHECK: snez: # CHECK-NEXT: snez t0, t0 sltz: sltz t0, t0 # CHECK: sltz: # CHECK-NEXT: sltz t0, t0 sgtz: sgtz t0, t0 # CHECK: sgtz: # CHECK-NEXT: sgtz t0, t0 beqz: beqz t0, 0 beqz t0, -1 beqz t0, 1 beqz t0, beqz # CHECK: beqz: # CHECK-NEXT: beqz t0, 0 # CHECK-NEXT: beqz t0, -1 # CHECK-NEXT: beqz t0, 1 # CHECK-NEXT: beqz t0, beqz bnez: bnez t0, 0 bnez t0, -1 bnez t0, 1 bnez t0, bnez # CHECK: bnez: # CHECK-NEXT: bnez t0, 0 # CHECK-NEXT: bnez t0, -1 # CHECK-NEXT: bnez t0, 1 # CHECK-NEXT: bnez t0, bnez blez: blez t0, 0 blez t0, -1 blez t0, 1 blez t0, blez # CHECK: blez: # CHECK-NEXT: blez t0, 0 # CHECK-NEXT: blez t0, -1 # CHECK-NEXT: blez t0, 1 # CHECK-NEXT: blez t0, blez bgez: bgez t0, 0 bgez t0, -1 bgez t0, 1 bgez t0, bgez # CHECK: bgez: # CHECK-NEXT: bgez t0, 0 # CHECK-NEXT: bgez t0, -1 # CHECK-NEXT: bgez t0, 1 # CHECK-NEXT: bgez t0, bgez bltz: bltz t0, 0 bltz t0, -1 bltz t0, 1 bltz t0, bltz # CHECK: bltz: # CHECK-NEXT: bltz t0, 0 # CHECK-NEXT: bltz t0, -1 # CHECK-NEXT: bltz t0, 1 # CHECK-NEXT: bltz t0, bltz bgtz: bgtz t0, 0 bgtz t0, -1 bgtz t0, 1 bgtz t0, bgtz # CHECK: bgtz: # CHECK-NEXT: bgtz t0, 0 # CHECK-NEXT: bgtz t0, -1 # CHECK-NEXT: bgtz t0, 1 # CHECK-NEXT: bgtz t0, bgtz bgt: bgt t0, t1, 0 bgt t0, t1, -1 bgt t0, t1, 1 bgt t0, t1, bgt # CHECK: bgt: # CHECK-NEXT: bgt t0, t1, 0 # CHECK-NEXT: bgt t0, t1, -1 # CHECK-NEXT: bgt t0, t1, 1 # CHECK-NEXT: bgt t0, t1, bgt ble: ble t0, t1, 0 ble t0, t1, -1 ble t0, t1, 1 ble t0, t1, ble # CHECK: ble: # CHECK-NEXT: ble t0, t1, 0 # CHECK-NEXT: ble t0, t1, -1 # CHECK-NEXT: ble t0, t1, 1 # CHECK-NEXT: ble t0, t1, ble bgtu: bgtu t0, t1, 0 bgtu t0, t1, -1 bgtu t0, t1, 1 bgtu t0, t1, bgtu # CHECK: bgtu: # CHECK-NEXT: bgtu t0, t1, 0 # CHECK-NEXT: bgtu t0, t1, -1 # CHECK-NEXT: bgtu t0, t1, 1 # CHECK-NEXT: bgtu t0, t1, bgtu bleu: bleu t0, t1, 0 bleu t0, t1, -1 bleu t0, t1, 1 bleu t0, t1, bleu # CHECK: bleu: # CHECK-NEXT: bleu t0, t1, 0 # CHECK-NEXT: bleu t0, t1, -1 # CHECK-NEXT: bleu t0, t1, 1 # CHECK-NEXT: bleu t0, t1, bleu ret: ret # CHECK: ret: # CHECK-NEXT: ret

JacobInwald/courseworks

599

Compiling Techniques/coursework-3-JacobInwald/tests/riscv/interpreter/hello_world.s

# RUN: riscv-interpreter %s | filecheck %s ; hello-world.asm ; print "Hello World" to stdout and exit .data msg: .ascii "Hello World!\n" .text addi a0, zero, 1 ; print to stdout addi a1, zero, msg ; load msg address addi a2, zero, 12 ; write 12 bytes addi a7, zero, SCALL_WRITE ; write syscall code ecall addi a0, zero, 0 ; set exit code to 0 addi a7, zero, SCALL_EXIT ; exit syscall code ecall ; CHECK: Hello World! ; CHECK-NEXT: Return code: 0

JacobInwald/courseworks

525

Compiling Techniques/coursework-3-JacobInwald/tests/riscv/lexer/labels.s

# RUN: riscv-lexer %s | filecheck %s foo: add a0, a0, a0 # CHECK: SYMBOL:foo # CHECK-NEXT: COLON # CHECK-NEXT: NEWLINE # CHECK-NEXT: SYMBOL:add # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: NEWLINE bar: add a0, a0, a0 # CHECK: SYMBOL:bar # CHECK-NEXT: COLON # CHECK-NEXT: NEWLINE # CHECK-NEXT: SYMBOL:add # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: NEWLINE

JacobInwald/courseworks

1,071

Compiling Techniques/coursework-3-JacobInwald/tests/riscv/lexer/ops.s

# RUN: riscv-lexer %s | filecheck %s add a0, a0, a0 # CHECK: SYMBOL:add # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: NEWLINE add a0, a0, 1 # CHECK: SYMBOL:add # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: INTEGER:1 # CHECK-NEXT: NEWLINE add a0, a0, -1 # CHECK: SYMBOL:add # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:a0 # CHECK-NEXT: COMMA # CHECK-NEXT: MINUS # CHECK-NEXT: INTEGER:1 # CHECK-NEXT: NEWLINE lw t0, t2 # CHECK: SYMBOL:lw # CHECK-NEXT: SYMBOL:t0 # CHECK-NEXT: COMMA # CHECK-NEXT: SYMBOL:t2 # CHECK-NEXT: NEWLINE lw t0, 0(t2) # CHECK: SYMBOL:lw # CHECK-NEXT: SYMBOL:t0 # CHECK-NEXT: COMMA # CHECK-NEXT: INTEGER:0 # CHECK-NEXT: LPAREN # CHECK-NEXT: SYMBOL:t2 # CHECK-NEXT: RPAREN # CHECK-NEXT: NEWLINE lw t0, 8(t2) # CHECK: SYMBOL:lw # CHECK-NEXT: SYMBOL:t0 # CHECK-NEXT: COMMA # CHECK-NEXT: INTEGER:8 # CHECK-NEXT: LPAREN # CHECK-NEXT: SYMBOL:t2 # CHECK-NEXT: RPAREN # CHECK-NEXT: NEWLINE

JacobInwald/courseworks

364

Compiling Techniques/coursework-3-JacobInwald/tests/riscv/lexer/directives.s

# RUN: riscv-lexer %s | filecheck %s .asciz "somestring" # CHECK: DOT # CHECK-NEXT: SYMBOL:asciz # CHECK-NEXT: LITERAL:"somestring" # CHECK-NEXT: NEWLINE .section .text # CHECK: DOT # CHECK-NEXT: SYMBOL:section # CHECK-NEXT: DOT # CHECK-NEXT: SYMBOL:text # CHECK-NEXT: NEWLINE .global getasm # CHECK: DOT # CHECK-NEXT: SYMBOL:global # CHECK-NEXT: SYMBOL:getasm

JacopoSini/Rust4Safety_DATE2025

256

Vanilla/src/crt0.s

.section .init, "ax" .global _start _start: .cfi_startproc .cfi_undefined ra .option push .option norelax la gp, __global_pointer$ .option pop la sp, __stack_top add s0, sp, zero jal zero, main .cfi_endproc .end

JacopoSini/Rust4Safety_DATE2025

256

YACCA/src/crt0.s

.section .init, "ax" .global _start _start: .cfi_startproc .cfi_undefined ra .option push .option norelax la gp, __global_pointer$ .option pop la sp, __stack_top add s0, sp, zero jal zero, main .cfi_endproc .end

JacopoSini/Rust4Safety_DATE2025

256

RACFED/src/crt0.s

.section .init, "ax" .global _start _start: .cfi_startproc .cfi_undefined ra .option push .option norelax la gp, __global_pointer$ .option pop la sp, __stack_top add s0, sp, zero jal zero, main .cfi_endproc .end

jared-hughes/defcpu

6,847

tests/integration/print_regs.s

# This file is a modification of defasm/cli/debug.s, which is under the following license. # # Copyright (c) 2021, Alon Ran # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # usage: # # movq $print1_ret, (printRegs_return) # jmp printRegs # print1_ret: sys_write = 1 sys_open = 2 sys_close = 3 sys_fork = 57 sys_execve = 59 sys_exit = 60 sys_ptrace = 101 sys_prctl = 157 sys_waitid = 247 STDERR_FILENO = 2 # Tracing the file .bss # regs are in the order provided by sys_ptrace(PTRACE_GETREGS, ...), even though # we don't currently use sys_ptrace to get regs since we're in the same process. regs: r_R15: .quad 0 r_R14: .quad 0 r_R13: .quad 0 r_R12: .quad 0 r_RBP: .quad 0 r_RBX: .quad 0 r_R11: .quad 0 r_R10: .quad 0 r_R9: .quad 0 r_R8: .quad 0 r_RAX: .quad 0 r_RCX: .quad 0 r_RDX: .quad 0 r_RSI: .quad 0 r_RDI: .quad 0 r_ORIG_RAX: .quad 0 r_RIP: .quad 0 r_CS: .quad 0 r_FLAGS: .quad 0 r_RSP: .quad 0 r_SS: .quad 0 r_FS_BASE: .quad 0 r_GS_BASE: .quad 0 r_DS: .quad 0 r_ES: .quad 0 r_FS: .quad 0 r_GS: .quad 0 # We only need 7 quadwords of stack space. A bit extra to be space. mini_stack: .quad 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 mini_stack_end: .quad 0 .section .rodata pr_hexaChars: .string "0123456789ABCDEF" .data outputBuffer: .byte 0 dumpFile: .long STDERR_FILENO line_num_before: .string "Result from print_regs on line " line_num_before_len = . - line_num_before line_num: .string "\0\0\0\0\0\0\0\0" line_num_len: .byte 0 .text # Print the value of %rax in 16 hexadecimal characters # Uses 6 quadwords of mini_stack space. pr_printQuad: push %rbx push %rdx push %rsi push %rdi push %rcx mov $16, %ebx mov $outputBuffer, %esi pr_nibbleLoop: rol $4, %rax mov %eax, %edx and $0xF, %edx mov pr_hexaChars(%rdx), %dl mov %dl, (%rsi) # Print the nibble push %rax mov $1, %dl mov $sys_write, %eax mov dumpFile, %edi syscall pop %rax dec %ebx jnz pr_nibbleLoop pop %rcx pop %rdi pop %rsi pop %rdx pop %rbx jmp pr_printQuad_done .section .rodata registerOrder: .long r_RAX, r_R8, r_RBX, r_R9, r_RCX, r_R10, r_RDX, r_R11 .long r_RSI, r_R12, r_RDI, r_R13, r_RSP, r_R14, r_RBP, r_R15 .long r_FLAGS flagOrder: .byte 0, 6, 11, 7, 10, 2 dumpString: .string "\ Registers: %rax = \0 %r8 = \0 %rbx = \0 %r9 = \0 %rcx = \0 %r10 = \0 %rdx = \0 %r11 = \0 %rsi = \0 %r12 = \0 %rdi = \0 %r13 = \0 %rsp = \0 %r14 = \0 %rbp = \0 %r15 = \0 Flags (\0): Carry = \0 Zero = \0 Overflow = \0 Sign = \0 Direction = \0 Parity = \0 \0" flagMessages: .string "0 (no carry) ", "1 (carry) " .string "0 (isn't zero) ", "1 (is zero) " .string "0 (no overflow) ", "1 (overflow) " .string "0 (positive) ", "1 (negative) " .string "0 (up) ", "1 (down) " .string "0 (odd) ", "1 (even) " flagMsgLen = 16 .text printRegs: mov %rax, (r_RAX) mov %rbx, (r_RBX) mov %rcx, (r_RCX) mov %rdx, (r_RDX) mov %rsi, (r_RSI) mov %rdi, (r_RDI) mov %rsp, (r_RSP) mov %rbp, (r_RBP) mov %r8, (r_R8) mov %r9, (r_R9) mov %r10, (r_R10) mov %r11, (r_R11) mov %r12, (r_R12) mov %r13, (r_R13) mov %r14, (r_R14) mov %r15, (r_R15) mov $mini_stack_end, %rsp pushfq pop %rax mov %rax, (r_FLAGS) # Print line number if relevant xor %edx, %edx movb (line_num_len), %dl cmp $8, %dl jle line_num_len_ok mov $8, %dl line_num_len_ok: cmp $0, %dl jz line_num_irrelevant mov $sys_write, %eax mov dumpFile, %edi mov $line_num_before, %rsi add $line_num_before_len, %edx syscall line_num_irrelevant: # Print registers xor %ebx, %ebx # bl = 0. Will be incremented on each read to count number of nulls filled in. mov $dumpString, %esi registerLoop: # start of loop: %esi is the start of $dumpString, or points to the last \0. mov %esi, %edi mov $-1, %ecx xor %al, %al # increment %rdi and decrement %ecx until (%rdi) = %al (=0), or %ecx = 0. repnz scasb # %rdi is now a pointer to the null byte; %ecx is negative of its 1-index in the string. push %rdi not %ecx dec %ecx # %ecx is length to print. mov %ecx, %edx mov $sys_write, %eax mov dumpFile, %edi syscall pop %rsi cmp $23, %bl # 17 registers + 6 flags. jge endRegisterLoop cmp $17, %bl # 17 registers (including RFLAGS) jge printFlag # bl < 17: Select register and print it mov registerOrder(, %rbx, 4), %eax mov (%rax), %rax jmp pr_printQuad pr_printQuad_done: jmp nextRegister printFlag: # bl >= 17: Select appropriate flag message push %rsi mov %bl, %dl sub $17, %dl mov flagOrder(%rdx), %al add %dl, %dl # shl $1, %dl bt %eax, r_FLAGS jnc adc_done; add $1, %dl; adc_done:; #adc $0, %dl imul $flagMsgLen, %edx, %edx lea flagMessages(%rdx), %esi mov $flagMsgLen, %edx mov $sys_write, %eax mov dumpFile, %edi syscall pop %rsi nextRegister: inc %ebx jmp registerLoop endRegisterLoop: printRegsDone: mov (r_FLAGS), %rax push %rax popfq mov (r_RAX), %rax mov (r_RBX), %rbx mov (r_RCX), %rcx mov (r_RDX), %rdx mov (r_RSI), %rsi mov (r_RDI), %rdi mov (r_RSP), %rsp mov (r_RBP), %rbp mov (r_R8), %r8 mov (r_R9), %r9 mov (r_R10), %r10 mov (r_R11), %r11 mov (r_R12), %r12 mov (r_R13), %r13 mov (r_R14), %r14 mov (r_R15), %r15 jmp 0x0(%rip) printRegs_return: .quad 0

jared-hughes/defcpu

5,405

tests/integration/dump_initial_state.s

# Dump the intial state of the program execution. # It's not strictly a memory dump -- I'm trying to print # the minimal necessary information to reconstruct the state. # This should just be the program arguments, plus any offsets needed # to determine the consequences of address-space layout randomization (ASLR) # usage: # # jmp dump_initial # dump_initial_ret: # # Don't call with `call` since that goobles the stack. .data # Note we make sure it's impossible to have trailing spaces, # since code.golf trims those. dump_contents: .asciz "Unpredictables:" .asciz "\nrand16" # contents of the 16 bytes at entry 25 (AT_RANDOM) of the auxv. # 16 bytes is 32 nibbles, so 4 quadwords. dump_random_16: .quad 0, 0, 0, 0 .asciz "\nVDSO\0\0" dump_vdso_ptr: .quad 0,0 # entry 33 (AT_SYSINFO_EHDR) of the auxv. .asciz "\nexecfn" dump_execfn_ptr: .quad 0,0 # entry 31 (AT_EXECFN) of the auxv. .asciz "\npltoff" dump_platform_offset: .quad 0,0 # distance from entry 15 (AT_PLATFORM) of the auxv to argv[0]. .asciz "\nargc\0\0" dump_argc: .quad 0,0 # number of arguments .asciz "\narglen" dump_arglen: .quad 0,0 # total number of bytes arguments take up, including null terminators. dump_nlnl: .ascii "\n\n" dump_len = . - dump_contents dump_hexChars: .ascii "0123456789ABCDEF" dump_execfn_ptr_val: .quad 0 dump_printQuad_ret: .quad 0 .text dump_initial: mov %rsp, %r8 # %r8 = initial %rsp. pushfq mov %r8, %rsp # Below here, don't push to the stack. # Using %rsp sneakily to look into the middle of the stack. # get argc pop %rax mov %rax, %rbx mov $dump_argc, %rdi movq $done_printing_argc, dump_printQuad_ret jmp dump_printQuad done_printing_argc: pop %rbp # rbp points to the first argument /tmp/asm. # Skip the arg pointers. # The null separator after argv (before envp) # is at 0x08 + 8 * argc + initial %rsp. # There's no envp, so the null separtor after envp (before auxv) # is at 0x10 + 8 * argc + initial %rsp. # so the first env pointer is 0x08 after that. lea 0x18(%r8, %rax, 8), %rsp # rsp is now the pointer to the first env pointer. # get the relevant environment pointers dump_at_loop: pop %rax # rax is the at_type. pop %rbx # rbx is the a_un (a_ptr or a_val). cmp $0, %rax jz dump_at_loop_done cmp $25, %rax; jz dump_at_type_25 cmp $31, %rax; jz dump_at_type_31 cmp $33, %rax; jz dump_at_type_33 cmp $15, %rax; jnz dump_at_loop dump_at_type_15: # AT_PLATFORM mov $0x100, %ecx mov %rbx, %rdi mov $0, %al repne scasb # %rdi now points to the nul terminator of the platform string mov %rbp, %rbx sub %rdi, %rbx # rbx is now the distance from the nul terminator of the # platform string "x86_64", to argv[0]. # decrement due to growing down. dec %rbx mov $dump_platform_offset, %edi movq $dump_at_loop, dump_printQuad_ret jmp dump_printQuad dump_at_type_25: # AT_RANDOM mov %rbx, %rax movq (%rax), %rbx bswap %rbx movq $after_first_quad_25, dump_printQuad_ret movq $dump_random_16, %edi jmp dump_printQuad after_first_quad_25: movq 0x8(%rax), %rbx bswap %rbx movq $dump_at_loop, dump_printQuad_ret jmp dump_printQuad dump_at_type_33: # AT_SYSINFO_EHDR mov $dump_vdso_ptr, %edi movq $dump_at_loop, dump_printQuad_ret jmp dump_printQuad dump_at_type_31: # AT_EXECFN mov %rbx, dump_execfn_ptr_val mov $dump_execfn_ptr, %edi movq $dump_at_loop, dump_printQuad_ret jmp dump_printQuad dump_at_loop_done: # all auxv entries popped, including the null entry. # calculate arglen mov dump_execfn_ptr_val, %rbx mov %rbp, %rsi # rsi = pointer to first arg sub %rsi, %rbx # rbx = arglen (bytes) # dump arglen movq $dump_arglen, %rdi movq $done_printing_arglen, dump_printQuad_ret jmp dump_printQuad done_printing_arglen: mov $dump_contents, %rsi mov $dump_len, %edx mov $1, %eax # sys_write mov $1, %edi # stdout syscall # calculate arglen mov dump_execfn_ptr_val, %rdx mov %rbp, %rsi # rsi = pointer to first arg sub %rsi, %rdx # rdx = arglen = count (bytes) mov $1, %eax # sys_write mov $1, %edi # stdout syscall mov $dump_nlnl, %esi mov $2, %edx mov $1, %eax # sys_write mov $1, %edi #stdout # Reset all registers to 0, except %rsp which should be back to normal. mov %r8, %rsp # but we also need to zero the extra quadword written to store flags add $-0x8, %rsp popfq xor %eax, %eax mov %rax, -0x8(%rsp) xor %ecx, %ecx xor %edx, %edx xor %esi, %esi xor %edi, %edi xor %rbp, %rbp xor %r11, %r11 xor %r8, %r8 jmp dump_initial_ret # print %rbx (8 bytes) as nibbles, to %rdi (16 bytes of nibbles) # returns to dump_printQuad_ret dump_printQuad: mov $16, %ecx xor %edx, %edx dump_random_nibble_loop: rol $4, %rbx mov %bl, %dl and $0xF, %dl mov dump_hexChars(%rdx), %dl mov %dl, (%rdi) inc %rdi dec %ecx jnz dump_random_nibble_loop jmp *dump_printQuad_ret

jared-hughes/defcpu

214

tests/integration/sources/007_movmem.s

# hole: fibonacci mov $0x00007FFEA10A6BE0, %rsp mov $mem, %ebp mov (%ebp), %al mov (%ebp), %bh mov (%ebp), %cx mov (%ebp), %edx mov (%ebp), %rsi hlt .data mem: .byte 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0

jared-hughes/defcpu

467

tests/integration/sources/013_xchg.s

# hole: fibonacci mov $0, %rsp mov $0x0102030405060708, %rax mov $0xA1B1C1D1E1F1A1B1, %rbx xchg %rax, %rbx xchg %rax, %r11 xchg %r11, %rcx xchg %rbx, %r8 xchg %r8d, %edx nop print_regs xchg %r11w, %si xchg %ax, %dx xchg %bl, %dl print_regs mov $x, %rax mov $y, %rbx xchg (%rax), %dl xchg (%rax), %cx xchg (%rbx), %edx xchg (%rbx), %rbx print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall .data x: .quad 0xabcdef12345678ab y: .quad 0xab12345678abcdef

jared-hughes/defcpu

45

tests/integration/sources/018_syscall_0.s

# hole: fibonacci dump_initial syscall hlt

jared-hughes/defcpu

836

tests/integration/sources/014_cltq_cbw.s

# hole: fibonacci mov $0, %rsp mov $0x1234567812345678, %rdx mov $0x0000, %ax cwtd print_regs mov $0x1234567812345678, %rdx mov $0x8000, %ax cwtd print_regs mov $0x1234567812345678, %rdx mov $0x00000000, %eax cltd print_regs mov $0x1234567812345678, %rdx mov $0x80000000, %eax cltd print_regs mov $0x1234567812345678, %rdx mov $0x0000000000000, %rax cqto print_regs mov $0x1234567812345678, %rdx mov $0x8000000000000, %rax cqto print_regs mov $0x1234567812345678, %rdx mov $0x00, %al cbtw print_regs mov $0x1234567812345678, %rdx mov $0x80, %al cbtw print_regs mov $0x1234567812345678, %rdx mov $0x0000, %ax cwtl print_regs mov $0x1234567812345678, %rdx mov $0x8000, %ax cwtl print_regs mov $0x1234567812345678, %rdx mov $0x00000000, %eax cltq print_regs mov $0x1234567812345678, %rdx mov $0x80000000, %eax cltq print_regs

jared-hughes/defcpu

370

tests/integration/sources/003_mov8.s

# hole: fibonacci mov $0x00007FFF3EA39100, %rsp mov $0x11, %al mov $0x12, %cl mov $0x13, %dl mov $0x14, %bl mov $0x21, %ah mov $0x22, %ch mov $0x23, %dh mov $0x24, %bh mov $0x31, %sil mov $0x32, %dil mov $0x33, %spl mov $0x34, %bpl mov $0x41, %r8b mov $0x42, %r9b mov $0x43, %r10b mov $0x44, %r11b mov $0x45, %r12b mov $0x46, %r13b mov $0x47, %r14b mov $0x48, %r15b hlt

jared-hughes/defcpu

500

tests/integration/sources/006_mov64.s

# hole: fibonacci mov $0x87654321DEA0BEEF, %rax mov $0x87654321DEA1BEEE, %rcx mov $0x87654321DEA2BEED, %rdx mov $0x87654321DEA3BEEC, %rbx mov $0x87654321DEA4BEEB, %rsp mov $0x87654321DEA5BEEA, %rbp mov $0x87654321DEA6BEE9, %rsi mov $0x87654321DEA7BEE8, %rdi mov $0x87654321DEA8BEE7, %r8 mov $0x87654321DEA9BEE6, %r9 mov $0x87654321DEAABEE5, %r10 mov $0x87654321DEABBEE4, %r11 mov $0x87654321DEACBEE3, %r12 mov $0x87654321DEADBEE2, %r13 mov $0x87654321DEAEBEE1, %r14 mov $0x87654321DEAFBEE0, %r15 hlt

jared-hughes/defcpu

8,513

tests/integration/sources/016_dump.s

# hole: rock-paper-scissors-spock-lizard SYS_WRITE = 1 SYS_EXIT = 60 STDOUT_FILENO = 1 .text dump_initial print_regs mov $argc, %rsi call printsz pop %rax push %rax call printDec # argc (one eighbyte) pop %rbx mov $nl, %rsi call printsz # always at least one arg because $0 = /tmp/asm argLoop: pop %rsi # pop the next arg pointer push %rsi mov $ox, %rsi; call printsz; pop %rax; push %rax; call printQuad; mov $colon_space, %rsi; call printsz; pop %rsi; call printsz; mov $nl, %rsi; call printsz dec %rbx jnz argLoop endArgLoop: call print_stack_quad # .quad 0 # one eightbyte each of environment pointers (none on code.golf) call print_stack_quad # .quad 0 # begin auxiliary vector entries: call print_auxv # a_type=33 (AT_SYSINFO_EHDR), a_un = pointer to start of ELF file? Always &0xFFF = 0x000 call print_auxv # a_type=51 (AT_MINSIGSTKSZ), a_val = 0xD30 call print_auxv # a_type=16 (AT_HWCAP), a_val = 0x178BFBFF call print_auxv # a_type=6 (AT_PAGESZ), a_val = 0x1000 call print_auxv # a_type=17 (AT_CLKTCK), a_val = 0x64 call print_auxv # a_type=3 (AT_PHDR), a_ptr = 0x0 call print_auxv # a_type=4 (AT_PHENT), a_val = 0x38 call print_auxv # a_type=5 (AT_PHNUM), a_val = 0x3 call print_auxv # a_type=7 (AT_BASE), a_ptr = 0x0 call print_auxv # a_type=8 (AT_FLAGS), a_val = 0x0 call print_auxv # a_type=9 (AT_ENTRY), a_ptr = 0x400000 call print_auxv # a_type=11 (AT_UID), a_val = 0xFFFE call print_auxv # a_type=12 (AT_EUID), a_val = 0xFFFE call print_auxv # a_type=13 (AT_GID), a_val = 0xFFFE call print_auxv # a_type=14 (AT_EGID), a_val = 0xFFFE call print_auxv # a_type=23 (AT_SECURE), a_val = 0x0 call print_auxv # a_type=25 (AT_RANDOM), a_un = stack pointer # (to 16 random bytes. always +0x1 or +0x9 on the info_block_end, whatever ends in 0x9) call print_auxv # a_type=26 (AT_HWCAP2), a_val = 0x2 # (docs say it should be zero) call print_auxv # a_type=31 (AT_EXECFN), a_ptr = stack pointer # (to char* filename "/tmp/asm". always 0xFEF in address on a page. # Either the page after info_block_end, or the same page, # precisely ((info_block_end + [0x0 or 0x1000]) & ~0xFFF) | 0xFEF) call print_auxv # a_type=15 (AT_PLATFORM), a_ptr = stack pointer # (to char* platform "x86_64". always +0x11 or +0x19 on the info_block_end, whatever ends in 0x9) call print_auxv # null auxiliary vector entry # unspecified: # call print_stack_quad # .quad 0 mov $finished_aux_vec, %rsi; call printsz mov %rsp, info_block_end mov %rsp, %rbx mov at_random, %rcx; sub %rbx, %rcx; mov $at_random_str, %rsi; call printsz; mov %rcx, %rax; call printQuad; mov $nl, %rsi; call printsz; mov at_platform, %rcx; sub %rbx, %rcx; mov $at_platform_str, %rsi; call printsz; mov %rcx, %rax; call printQuad; mov $nl, %rsi; call printsz; mov at_execfn, %rcx; sub %rbx, %rcx; mov $at_execfn_str, %rsi; call printsz; mov %rcx, %rax; call printQuad; mov $nl, %rsi; call printsz; mov at_33, %rcx; sub %rbx, %rcx; mov $at_33_str, %rsi; call printsz; mov %rcx, %rax; call printQuad; mov $nl, %rsi; call printsz; mov %rsp, %rsi call hexdump_page mov at_execfn, %rbx cmp %rbx, %rsi jge already_dumped_execfn call hexdump_page already_dumped_execfn: # the pages after at_execfn are not readable. mov at_33, %rsi call hexdump_page # segfault expected here. seems to only have one page at 33. add $0x1000, %rsi call hexdump_page jmp exit .data at_33: .quad 0 at_random: .quad 0 at_execfn: .quad 0 at_platform: .quad 0 info_block_end: .quad 0 .text print_stack_quad: pop %r8 # return rip mov $ox, %rsi; call printsz pop %rax; call printQuad mov $nl, %rsi; call printsz push %r8 ret # Pops two quadwords, treats it as auxv_t (see https://gitlab.com/x86-psABIs/x86-64-ABI) # The first quadword is a_type. The second is a_un, which may be anything (pointer or value) print_auxv: pop %r8 # return rip mov $a_type_eq, %rsi call printsz pop %rax mov %rax, %r12 call printDec mov $auxv_mid, %rsi call printsz pop %rax mov %rax, %r13 call printQuad cmp $33, %r12 je char_star_33 cmp $31, %r12 je char_star_31 cmp $15, %r12 je char_star_15 cmp $25, %r12 je sixteen_random jmp done_branch sixteen_random: mov $at_random, %eax; mov %r13, (%eax); mov $sixteen_open, %rsi; call printsz mov $nl, %rsi; call printsz mov %r13, %rsi; call print16 mov $sixteen_close, %rsi; call printsz jmp done_branch char_star_33: mov $at_33, %eax; mov %r13, (%eax); jmp char_star char_star_31: mov $at_execfn, %eax; mov %r13, (%eax); jmp char_star char_star_15: mov $at_platform, %eax; mov %r13, (%eax); jmp char_star char_star: mov $str_open, %rsi; call printsz mov %r13, %rsi call printsz mov $str_close, %rsi call printsz done_branch: mov $nl, %rsi call printsz push %r8 ret .data a_type_eq: .asciz "a_type=" colon_space: .asciz ": " nl: .asciz "\n" auxv_mid: .asciz ",\ta_un=0x" ox: .asciz "0x" argc: .asciz "argc=" str_open: .asciz " (char*) (\"" str_close: .asciz "\")" sixteen_open: .asciz " (char[16]) (\"" sixteen_close: .asciz "\")" finished_aux_vec: .asciz "Finished reading aux vector entries. Offsets:\n" at_33_str: .asciz "AT 33 (??):\t+0x" at_random_str: .asciz "AT_RANDOM:\t+0x" at_execfn_str: .asciz "AT_EXECFN:\t+0x" at_platform_str: .asciz "AT_PLATFORM:\t+0x" .text # print the null-terminated string in %rsi printsz: push %rax; push %rcx mov %rsi, %rdi mov $-1, %ecx xor %al, %al repnz scasb not %ecx dec %ecx # length in %ecx mov %ecx, %edx mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi syscall pop %rcx; pop %rax ret .data dec_buf: .quad 0,0,0 dec_buf_end: .byte '\n' hexdump_buf: .ascii ": " hexdump_buf_hex: .ascii "0000 0000 0000 0000 0000 0000 0000 0000 " hexdump_buf_chars: .ascii "aaaaaaaaaaaaaaaa\n" hexdump_buf_len = . - hexdump_buf .text # Print the value of %rax in decimal. Uses X quadwords of stack. printDec: mov $dec_buf_end, %esi push %rsi # push start ptr mov $10, %ebx # ebx = 10 xor %edx, %edx for_digit_in_num: dec %esi; div %ebx # divide %edx:%eax by %ebx=10, %eax=quotient, %edx=remainder. add $'0', %dl mov %dl, (%rsi) # P cltd # %edx = 0. cmp $0, %eax jnz for_digit_in_num pop %rdx sub %esi, %edx # edx = count mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi syscall ret # write %al as two nibble chars printByte: mov $hex_buf, %rdi call writeByte mov $hex_buf, %esi mov $2, %edx mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi syscall # move %al as two nibble chars to (%rdi) and 0x1(%rdi) writeByte: xor %edx, %edx rol $4, %al mov %al, %dl and $0xF, %dl mov hexaChars(%rdx), %dl mov %dl, (%rdi) rol $4, %al mov %al, %dl and $0xF, %dl mov hexaChars(%rdx), %dl mov %dl, 0x1(%rdi) ret # hexdump starting from %rsi until the end of the page. hexdump_page: push %rsi; mov $nl, %rsi; call printsz; call printsz; call printsz; pop %rsi and $~0xF, %rsi hexdump_loop: call print16;add $16, %rsi mov %esi, %eax and $0xFF0, %eax jnz hexdump_loop ret # Print 16 chars, starting at %rsi, in hexdump format print16: mov %rsi, %r13 mov %rsi, %rax; call printQuad mov %r13, %rsi mov $hexdump_buf_hex, %rdi mov $16, %ecx for_byte_start: mov (%rsi), %al; call writeByte bt $0, %ecx adc $2, %rdi inc %rsi dec %ecx jnz for_byte_start mov %r13, %rsi mov $hexdump_buf_chars, %rdi mov $16, %ecx for_char_start: mov (%rsi), %al; cmp $32, %al jb bad cmp $126, %al ja bad jmp good bad: mov $'.', %al good: mov %al, (%rdi) inc %rdi inc %rsi dec %ecx jnz for_char_start # print the hexdump mov $hexdump_buf, %esi mov $hexdump_buf_len, %edx mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi syscall mov %r13, %rsi ret .data hexaChars: .string "0123456789ABCDEF" hex_buf: .byte 0,0 .text # Print the value of %rax in 16 hexadecimal characters. Uses 6 quadwords of stack. printQuad: push %rbx push %rdx push %rsi push %rdi push %rcx mov $16, %ebx mov $hex_buf, %esi nibbleLoop: rol $4, %rax mov %eax, %edx and $0xF, %edx mov hexaChars(%rdx), %dl mov %dl, (%rsi) # Print the nibble push %rax mov $1, %dl mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi syscall pop %rax dec %ebx jnz nibbleLoop pop %rcx pop %rdi pop %rsi pop %rdx pop %rbx ret .text exit: mov $SYS_EXIT, %eax mov $0, %edi syscall

jared-hughes/defcpu

455

tests/integration/sources/015_call_ret.s

# hole: fibonacci .data stack: .quad 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 stack_top: .quad 0 .text mov $stack_top, %rsp mov $1, %rax call lbl1 mov $5, %rdi print_regs call exit # unreachable: mov $12345, %r12 lbl1: mov $2, %rbx call lbl2 mov $4, %rdx ret # unreachable: mov $23456, %r13 lbl2: mov $3, %rcx ret # unreachable: mov $34567, %r15 exit: # --- Clean exit mov $60, %eax mov $0, %edi syscall

jared-hughes/defcpu

338

tests/integration/sources/004_mov16.s

# hole: fibonacci mov $0x00007FFCA2C2BEEB, %rsp mov $0xBEEF, %ax mov $0xBEEE, %cx mov $0xBEED, %dx mov $0xBEEC, %bx mov $0xBEEB, %sp mov $0xBEEA, %bp mov $0xBEE9, %si mov $0xBEE8, %di mov $0xBEE7, %r8w mov $0xBEE6, %r9w mov $0xBEE5, %r10w mov $0xBEE4, %r11w mov $0xBEE3, %r12w mov $0xBEE2, %r13w mov $0xBEE1, %r14w mov $0xBEE0, %r15w hlt

jared-hughes/defcpu

380

tests/integration/sources/005_mov32.s

# hole: fibonacci mov $0xDEA0BEEF, %eax mov $0xDEA1BEEE, %ecx mov $0xDEA2BEED, %edx mov $0xDEA3BEEC, %ebx mov $0xDEA4BEEB, %esp mov $0xDEA5BEEA, %ebp mov $0xDEA6BEE9, %esi mov $0xDEA7BEE8, %edi mov $0xDEA8BEE7, %r8d mov $0xDEA9BEE6, %r9d mov $0xDEAABEE5, %r10d mov $0xDEABBEE4, %r11d mov $0xDEACBEE3, %r12d mov $0xDEADBEE2, %r13d mov $0xDEAEBEE1, %r14d mov $0xDEAFBEE0, %r15d hlt

jared-hughes/defcpu

275

tests/integration/sources/017_bswap.s

# hole: fibonacci xor %rsp, %rsp mov $0x0102030405060708, %rax mov $0xA1B2C3D4E5F6A7B8, %rbx bswap %rax bswap %rbx print_regs mov $0x0102030405060708, %rax mov $0xA1B2C3D4E5F6A7B8, %rbx bswap %eax bswap %ebx print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall

jared-hughes/defcpu

2,006

tests/integration/sources/012_and_xor.s

# hole: fibonacci .data stack: .quad 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 stack_top: .quad 0 .text mov $stack_top, %rsp # --- 64-bit and mov $0x1122334455667788, %rax mov $0xA1B2C3D4E5F67890, %rbx and %rax, %rbx print_regs # --- 32-bit and push $0x0000000000010ad7; popfq mov $0x11223344, %eax mov $0xA1B2C3D4, %ebx and %eax, %ebx print_regs and $0xA1F3FFE6, %ebx and $0xA1F3FFE6, %eax print_regs # --- 16-bit and push $0x0000000000010ad7; popfq mov $0xA555, %ax mov $0xA1B2, %bx and %ax, %bx print_regs and $0x81F3, %bx and $0xA1F3, %ax print_regs # --- 8-bit and push $0x0000000000010ad7; popfq mov $0x77, %al mov $0xA1, %ah and %al, %ah print_regs and $0x77, %al and $0xF3, %ah print_regs and $0x04, %ah print_regs # --- 64-bit xor mov $0x1122334455667788, %rax mov $0xA1B2C3D4E5F67890, %rbx xor %rax, %rbx print_regs # --- 32-bit xor push $0x0000000000010ad7; popfq mov $0x11223344, %eax mov $0xA1B2C3D4, %ebx xor %eax, %ebx print_regs xor $0xA1F3FFE6, %ebx xor $0xA1F3FFE6, %eax print_regs # --- 16-bit xor push $0x0000000000010ad7; popfq mov $0xA555, %ax mov $0xA1B2, %bx xor %ax, %bx print_regs xor $0x81F3, %bx xor $0xA1F3, %ax print_regs # --- 8-bit xor push $0x0000000000010ad7; popfq mov $0x77, %al mov $0xA1, %ah xor %al, %ah print_regs xor $0x77, %al xor $0xF3, %ah print_regs xor $0x04, %ah print_regs # --- 64-bit or mov $0x1122334455667788, %rax mov $0xA1B2C3D4E5F67890, %rbx or %rax, %rbx print_regs # --- 32-bit or push $0x0000000000010ad7; popfq mov $0x11223344, %eax mov $0xA1B2C3D4, %ebx or %eax, %ebx print_regs or $0xA1F3FFE6, %ebx or $0xA1F3FFE6, %eax print_regs # --- 16-bit or push $0x0000000000010ad7; popfq mov $0xA555, %ax mov $0xA1B2, %bx or %ax, %bx print_regs or $0x81F3, %bx or $0xA1F3, %ax print_regs # --- 8-bit or push $0x0000000000010ad7; popfq mov $0x77, %al mov $0xA1, %ah or %al, %ah print_regs or $0x77, %al or $0xF3, %ah print_regs or $0x04, %ah print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall

jared-hughes/defcpu

402

tests/integration/sources/010_push_pop.s

# hole: fibonacci .data stack: .quad 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 stack_top: .quad 0 .text mov $stack_top, %rsp push $0x123 print_regs pushfq print_regs pop %rax pop %rbx print_regs # TODO: setting the rflags. It's a mess of bus errors and sigtrap currently. # mov $0xFFFFFFFFFFFFFFFFFF, %rbx # push %rbx # popfq # print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall

jared-hughes/defcpu

676

tests/integration/sources/011_div.s

# hole: fibonacci .data stack: .quad 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 stack_top: .quad 0 .text mov $stack_top, %rsp # --- 64-bit div mov $0x123456789ABCDEF0, %rdx mov $0x1122334455667788, %rax mov $0xA1B2C3D4E5F67890, %rcx div %rcx print_regs # --- 32-bit div push $0x0000000000010ad7; popfq mov $0x9ABCDEF0, %edx mov $0x55667788, %eax mov $0xE5F67890, %ecx div %ecx print_regs # --- 16-bit div push $0x0000000000010ad7; popfq mov $0x9ABC, %dx mov $0x5566, %ax mov $0xE5F6, %cx div %cx print_regs # --- 8-bit div push $0x0000000000010ad7; popfq mov $0x9ABC, %ax mov $0xE5, %cl div %ch print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall

jared-hughes/defcpu

281

tests/integration/sources/002_hello_world.s

# hole: fibonacci SYS_WRITE = 1 SYS_EXIT = 60 STDOUT_FILENO = 1 # Printing .data buffer: .string "Hello, World!\n" bufferLen = . - buffer .text mov $SYS_WRITE, %eax mov $STDOUT_FILENO, %edi mov $buffer, %esi mov $bufferLen, %edx syscall mov $SYS_EXIT, %eax mov $0, %edi syscall

jared-hughes/defcpu

699

tests/integration/sources/008_printnum.s

# hole: fibonacci .comm x, 0xf78000000 mov $0, %rsp # just so test files line up mov $123456789, %eax # SUB: print decimal followed by newline # Requires .comm directive above to let # (-1_i32 as u32) be accessible memory locations mov $10, %bl mov $'\n'-'0', %dl for_digit_in_num: add $'0', %dl dec %esi # first run through the loop: esi = -1 = FFFF_FFFF. # following two can be replaced with xchg %dl, (%rsi) mov %dl, (%rsi) mov $0, %dl cmp %eax, %edx div %ebx jc for_digit_in_num # Actually print the result # sample code to print it mov $1, %al # or pop %eax if the hole is argumentless # %eax = 1. mov %eax, %edi # fd = %rdi # %rdx = 0 # buf = %rsi sub %esi, %edx # cnt = rdx syscall hlt

jared-hughes/defcpu

263

tests/integration/sources/001_mov.s

# hole: fibonacci mov $0x00007FFCD4A9D8F0, %rsp mov $0xDEADBEEF, %ebx mov $0x1023456789ABCDEF, %rax mov $0xF1023456789ABCDE, %rcx mov $0xEF1023456789ABCD, %rdx mov $0xDEF1023456789ABC, %r8 mov $0x12340567, %eax mov $0x1234, %cx mov $0x45, %dl mov $0x23, %dh hlt

jared-hughes/defcpu

12,160

tests/integration/sources/009_add_sub_cmp.s

# hole: fibonacci mov $0, %rsp stc print_regs clc print_regs # --- 64-bit add # plain mov $0x0102030405060708, %rax mov $0xA1B1C1D1E1F1A1B1, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # carry mov $0x6000000000000001, %rax mov $0xA000000000000000, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # overflow and carry mov $0x9000000000000001, %rax mov $0xA000000000000010, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # overflow mov $0x7000000000000007, %rax mov $0x7000000000000000, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # AF flag. mov $0x7000000000000008, %rax mov $0x7000000000000008, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # Zero. mov $0x7FFFFFFFFFFFFFFF, %rax mov $0x8000000000000001, %rbx mov %rax, %rcx add %rbx, %rcx print_regs # --- 32-bit add # plain mov $0x01020304, %eax mov $0xA1B1C1D1, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # carry mov $0x60000001, %eax mov $0xA0000000, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # overflow and carry mov $0x90000001, %eax mov $0xA0000010, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # overflow mov $0x70000007, %eax mov $0x70000000, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # AF flag. mov $0x70000008, %eax mov $0x70000008, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # Zero. mov $0x7FFFFFFF, %eax mov $0x80000001, %ebx mov %eax, %ecx add %ebx, %ecx print_regs # --- 16-bit add # plain mov $0x0102, %ax mov $0xA1B1, %bx mov %ax, %cx add %bx, %cx print_regs # carry mov $0x6001, %ax mov $0xA000, %bx mov %ax, %cx add %bx, %cx print_regs # overflow and carry mov $0x9001, %ax mov $0xA010, %bx mov %ax, %cx add %bx, %cx print_regs # overflow mov $0x7007, %ax mov $0x7000, %bx mov %ax, %cx add %bx, %cx print_regs # AF flag. mov $0x7008, %ax mov $0x7008, %bx mov %ax, %cx add %bx, %cx print_regs # Zero. mov $0x7FFF, %ax mov $0x8001, %bx mov %ax, %cx add %bx, %cx print_regs # --- 8-bit add # plain mov $0x01, %al mov $0xA1, %bl mov %al, %cl add %bl, %cl print_regs # carry mov $0x61, %al mov $0xA0, %bl mov %al, %cl add %bl, %cl print_regs # overflow and carry mov $0x91, %al mov $0xA0, %bl mov %al, %cl add %bl, %cl print_regs # overflow mov $0x77, %al mov $0x70, %bl mov %al, %cl add %bl, %cl print_regs # AF flag. mov $0x78, %al mov $0x78, %bl mov %al, %cl add %bl, %cl print_regs # Zero. mov $0x7F, %al mov $0x81, %bl mov %al, %cl add %bl, %cl print_regs # --- 64-bit adc # plain mov $0x0102030405060708, %rax mov $0xA1B1C1D1E1F1A1B1, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # carry mov $0x6000000000000001, %rax mov $0xA000000000000000, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # overflow and carry mov $0x9000000000000001, %rax mov $0xA000000000000010, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # overflow mov $0x7000000000000007, %rax mov $0x7000000000000000, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # AF flag. mov $0x7000000000000008, %rax mov $0x7000000000000008, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # Zero. mov $0x7FFFFFFFFFFFFFFF, %rax mov $0x8000000000000001, %rbx mov %rax, %rcx stc; adc %rbx, %rcx print_regs # --- 32-bit adc # plain mov $0x01020304, %eax mov $0xA1B1C1D1, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # carry mov $0x60000001, %eax mov $0xA0000000, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # overflow and carry mov $0x90000001, %eax mov $0xA0000010, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # overflow mov $0x70000007, %eax mov $0x70000000, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # AF flag. mov $0x70000008, %eax mov $0x70000008, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # Zero. mov $0x7FFFFFFF, %eax mov $0x80000001, %ebx mov %eax, %ecx stc; adc %ebx, %ecx print_regs # --- 16-bit adc # plain mov $0x0102, %ax mov $0xA1B1, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # carry mov $0x6001, %ax mov $0xA000, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # overflow and carry mov $0x9001, %ax mov $0xA010, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # overflow mov $0x7007, %ax mov $0x7000, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # AF flag. mov $0x7008, %ax mov $0x7008, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # Zero. mov $0x7FFF, %ax mov $0x8001, %bx mov %ax, %cx stc; adc %bx, %cx print_regs # --- 8-bit adc # plain mov $0x01, %al mov $0xA1, %bl mov %al, %cl stc; adc %bl, %cl print_regs # carry mov $0x61, %al mov $0xA0, %bl mov %al, %cl stc; adc %bl, %cl print_regs # overflow and carry mov $0x91, %al mov $0xA0, %bl mov %al, %cl stc; adc %bl, %cl print_regs # overflow mov $0x77, %al mov $0x70, %bl mov %al, %cl stc; adc %bl, %cl print_regs # AF flag. mov $0x78, %al mov $0x78, %bl mov %al, %cl stc; adc %bl, %cl print_regs # Zero. mov $0x7F, %al mov $0x81, %bl mov %al, %cl stc; adc %bl, %cl print_regs # --- 64-bit sub # plain mov $0xA1B1C1D1E1F1A1B1, %rax mov $0x0102030405060708, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # carry (borrow) mov $0x2000000000000001, %rax mov $0x4000000000000000, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # overflow and carry mov $0x7000000000000007, %rax mov $0xA000000000000000, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # overflow mov $0xA000000000000001, %rax mov $0x7000000000000010, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # AF flag. mov $0x7000000000000007, %rax mov $0x7000000000000008, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # Zero. mov $0x8000000000000001, %rax mov $0x8000000000000001, %rbx mov %rax, %rcx sub %rbx, %rcx print_regs # --- 32-bit sub # plain mov $0xA1B1C1D1, %eax mov $0x01020304, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # carry (borrow) mov $0x20000001, %eax mov $0x40000000, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # overflow and carry mov $0x70000007, %eax mov $0xA0000000, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # overflow mov $0xA0000001, %eax mov $0x70000010, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # AF flag. mov $0x70000007, %eax mov $0x70000008, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # Zero. mov $0x80000001, %eax mov $0x80000001, %ebx mov %eax, %ecx sub %ebx, %ecx print_regs # --- 16-bit sub # plain mov $0xA1B1, %ax mov $0x0102, %bx mov %ax, %cx sub %bx, %cx print_regs # carry (borrow) mov $0x2001, %ax mov $0x4000, %bx mov %ax, %cx sub %bx, %cx print_regs # overflow and carry mov $0x7007, %ax mov $0xA000, %bx mov %ax, %cx sub %bx, %cx print_regs # overflow mov $0xA001, %ax mov $0x7010, %bx mov %ax, %cx sub %bx, %cx print_regs # AF flag. mov $0x7007, %ax mov $0x7008, %bx mov %ax, %cx sub %bx, %cx print_regs # Zero. mov $0x8001, %ax mov $0x8001, %bx mov %ax, %cx sub %bx, %cx print_regs # --- 8-bit sub # plain mov $0xA1, %al mov $0x01, %bl mov %al, %cl sub %bl, %cl print_regs # carry (borrow) mov $0x21, %al mov $0x40, %bl mov %al, %cl sub %bl, %cl print_regs # overflow and carry mov $0x77, %al mov $0xA0, %bl mov %al, %cl sub %bl, %cl print_regs # overflow mov $0xA1, %al mov $0x70, %bl mov %al, %cl sub %bl, %cl print_regs # AF flag. mov $0x77, %al mov $0x78, %bl mov %al, %cl sub %bl, %cl print_regs # Zero. mov $0x81, %al mov $0x81, %bl mov %al, %cl sub %bl, %cl print_regs # --- 64-bit sbb # plain mov $0xA1B1C1D1E1F1A1B1, %rax mov $0x0102030405060708, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # carry (borrow) mov $0x2000000000000001, %rax mov $0x4000000000000000, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # overflow and carry mov $0x7000000000000007, %rax mov $0xA000000000000000, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # overflow mov $0xA000000000000001, %rax mov $0x7000000000000010, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # AF flag. mov $0x7000000000000007, %rax mov $0x7000000000000008, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # Zero. mov $0x8000000000000001, %rax mov $0x8000000000000001, %rbx mov %rax, %rcx stc; sbb %rbx, %rcx print_regs # --- 32-bit sbb # plain mov $0xA1B1C1D1, %eax mov $0x01020304, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # carry (borrow) mov $0x20000001, %eax mov $0x40000000, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # overflow and carry mov $0x70000007, %eax mov $0xA0000000, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # overflow mov $0xA0000001, %eax mov $0x70000010, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # AF flag. mov $0x70000007, %eax mov $0x70000008, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # Zero. mov $0x80000001, %eax mov $0x80000001, %ebx mov %eax, %ecx stc; sbb %ebx, %ecx print_regs # --- 16-bit sbb # plain mov $0xA1B1, %ax mov $0x0102, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # carry (borrow) mov $0x2001, %ax mov $0x4000, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # overflow and carry mov $0x7007, %ax mov $0xA000, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # overflow mov $0xA001, %ax mov $0x7010, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # AF flag. mov $0x7007, %ax mov $0x7008, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # Zero. mov $0x8001, %ax mov $0x8001, %bx mov %ax, %cx stc; sbb %bx, %cx print_regs # --- 8-bit sbb # plain mov $0xA1, %al mov $0x01, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # carry (borrow) mov $0x21, %al mov $0x40, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # overflow and carry mov $0x77, %al mov $0xA0, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # overflow mov $0xA1, %al mov $0x70, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # AF flag. mov $0x77, %al mov $0x78, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # Zero. mov $0x81, %al mov $0x81, %bl mov %al, %cl stc; sbb %bl, %cl print_regs # --- 64-bit cmp # plain mov $0xA1B1C1D1E1F1A1B1, %rax mov $0x0102030405060708, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # carry (borrow) mov $0x2000000000000001, %rax mov $0x4000000000000000, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # overflow and carry mov $0x7000000000000007, %rax mov $0xA000000000000000, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # overflow mov $0xA000000000000001, %rax mov $0x7000000000000010, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # AF flag. mov $0x7000000000000007, %rax mov $0x7000000000000008, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # Zero. mov $0x8000000000000001, %rax mov $0x8000000000000001, %rbx mov %rax, %rcx cmp %rbx, %rcx print_regs # --- 32-bit cmp # plain mov $0xA1B1C1D1, %eax mov $0x01020304, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # carry (borrow) mov $0x20000001, %eax mov $0x40000000, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # overflow and carry mov $0x70000007, %eax mov $0xA0000000, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # overflow mov $0xA0000001, %eax mov $0x70000010, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # AF flag. mov $0x70000007, %eax mov $0x70000008, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # Zero. mov $0x80000001, %eax mov $0x80000001, %ebx mov %eax, %ecx cmp %ebx, %ecx print_regs # --- 16-bit cmp # plain mov $0xA1B1, %ax mov $0x0102, %bx mov %ax, %cx cmp %bx, %cx print_regs # carry (borrow) mov $0x2001, %ax mov $0x4000, %bx mov %ax, %cx cmp %bx, %cx print_regs # overflow and carry mov $0x7007, %ax mov $0xA000, %bx mov %ax, %cx cmp %bx, %cx print_regs # overflow mov $0xA001, %ax mov $0x7010, %bx mov %ax, %cx cmp %bx, %cx print_regs # AF flag. mov $0x7007, %ax mov $0x7008, %bx mov %ax, %cx cmp %bx, %cx print_regs # Zero. mov $0x8001, %ax mov $0x8001, %bx mov %ax, %cx cmp %bx, %cx print_regs # --- 8-bit cmp # plain mov $0xA1, %al mov $0x01, %bl mov %al, %cl cmp %bl, %cl print_regs # carry (borrow) mov $0x21, %al mov $0x40, %bl mov %al, %cl cmp %bl, %cl print_regs # overflow and carry mov $0x77, %al mov $0xA0, %bl mov %al, %cl cmp %bl, %cl print_regs # overflow mov $0xA1, %al mov $0x70, %bl mov %al, %cl cmp %bl, %cl print_regs # AF flag. mov $0x77, %al mov $0x78, %bl mov %al, %cl cmp %bl, %cl print_regs # Zero. mov $0x81, %al mov $0x81, %bl mov %al, %cl cmp %bl, %cl print_regs # --- Clean exit mov $60, %eax mov $0, %edi syscall

jared-hughes/defcpu

381

tests/disassembly/sources/022_lea.s

8d 0c 18 lea (%rax, %rbx, 1), %ecx 8d 4c 18 12 lea 0x12(%rax, %rbx, 1), %ecx 8d 8c 18 12 34 56 78 lea 0x78563412(%rax, %rbx, 1), %ecx 8d 4c 18 82 lea -0x7e(%rax, %rbx, 1), %ecx 8d 8c 18 12 34 56 88 lea -0x77a9cbee(%rax, %rbx, 1), %ecx 8d (bad) f4 hlt

jared-hughes/defcpu

3,872

tests/disassembly/sources/021_rotate.s

c0 01 12 rolb $0x12, (%rcx) 48 c0 01 12 rex.W rolb $0x12, (%rcx) 41 c0 01 12 rolb $0x12, (%r9) c0 c1 12 rol $0x12, %cl c0 09 12 rorb $0x12, (%rcx) 48 c0 09 12 rex.W rorb $0x12, (%rcx) 41 c0 09 12 rorb $0x12, (%r9) c0 c9 12 ror $0x12, %cl c0 11 12 rclb $0x12, (%rcx) 48 c0 11 12 rex.W rclb $0x12, (%rcx) 41 c0 11 12 rclb $0x12, (%r9) c0 d1 12 rcl $0x12, %cl c0 19 12 rcrb $0x12, (%rcx) 48 c0 19 12 rex.W rcrb $0x12, (%rcx) 41 c0 19 12 rcrb $0x12, (%r9) c0 d9 12 rcr $0x12, %cl d0 01 rolb (%rcx) 48 d0 01 rex.W rolb (%rcx) 41 d0 01 rolb (%r9) d0 c1 rol %cl d0 09 rorb (%rcx) 48 d0 09 rex.W rorb (%rcx) 41 d0 09 rorb (%r9) d0 c9 ror %cl d0 11 rclb (%rcx) 48 d0 11 rex.W rclb (%rcx) 41 d0 11 rclb (%r9) d0 d1 rcl %cl d0 19 rcrb (%rcx) 48 d0 19 rex.W rcrb (%rcx) 41 d0 19 rcrb (%r9) d0 d9 rcr %cl c1 01 12 roll $0x12, (%rcx) 66 c1 01 12 rolw $0x12, (%rcx) 67 c1 01 12 roll $0x12, (%ecx) 41 c1 01 12 roll $0x12, (%r9) 48 c1 01 12 rolq $0x12, (%rcx) 49 c1 01 12 rolq $0x12, (%r9) c1 09 12 rorl $0x12, (%rcx) 66 c1 09 12 rorw $0x12, (%rcx) 67 c1 09 12 rorl $0x12, (%ecx) 41 c1 09 12 rorl $0x12, (%r9) 48 c1 09 12 rorq $0x12, (%rcx) 49 c1 09 12 rorq $0x12, (%r9) c1 11 12 rcll $0x12, (%rcx) 66 c1 11 12 rclw $0x12, (%rcx) 67 c1 11 12 rcll $0x12, (%ecx) 41 c1 11 12 rcll $0x12, (%r9) 48 c1 11 12 rclq $0x12, (%rcx) 49 c1 11 12 rclq $0x12, (%r9) c1 19 12 rcrl $0x12, (%rcx) 66 c1 19 12 rcrw $0x12, (%rcx) 67 c1 19 12 rcrl $0x12, (%ecx) 41 c1 19 12 rcrl $0x12, (%r9) 48 c1 19 12 rcrq $0x12, (%rcx) 49 c1 19 12 rcrq $0x12, (%r9) d1 01 roll (%rcx) 66 d1 01 rolw (%rcx) 67 d1 01 roll (%ecx) 41 d1 01 roll (%r9) 48 d1 01 rolq (%rcx) 49 d1 01 rolq (%r9) d1 09 rorl (%rcx) 66 d1 09 rorw (%rcx) 67 d1 09 rorl (%ecx) 41 d1 09 rorl (%r9) 48 d1 09 rorq (%rcx) 49 d1 09 rorq (%r9) d1 11 rcll (%rcx) 66 d1 11 rclw (%rcx) 67 d1 11 rcll (%ecx) 41 d1 11 rcll (%r9) 48 d1 11 rclq (%rcx) 49 d1 11 rclq (%r9) d1 19 rcrl (%rcx) 66 d1 19 rcrw (%rcx) 67 d1 19 rcrl (%ecx) 41 d1 19 rcrl (%r9) 48 d1 19 rcrq (%rcx) 49 d1 19 rcrq (%r9) d2 01 rolb %cl, (%rcx) 66 d2 01 data16 rolb %cl, (%rcx) 67 d2 01 rolb %cl, (%ecx) 41 d2 01 rolb %cl, (%r9) 48 d2 01 rex.W rolb %cl, (%rcx) 49 d2 01 rex.WB rolb %cl, (%r9) d2 09 rorb %cl, (%rcx) 66 d2 09 data16 rorb %cl, (%rcx) 67 d2 09 rorb %cl, (%ecx) 41 d2 09 rorb %cl, (%r9) 48 d2 09 rex.W rorb %cl, (%rcx) 49 d2 09 rex.WB rorb %cl, (%r9) d2 11 rclb %cl, (%rcx) 66 d2 11 data16 rclb %cl, (%rcx) 67 d2 11 rclb %cl, (%ecx) 41 d2 11 rclb %cl, (%r9) 48 d2 11 rex.W rclb %cl, (%rcx) 49 d2 11 rex.WB rclb %cl, (%r9) d2 19 rcrb %cl, (%rcx) 66 d2 19 data16 rcrb %cl, (%rcx) 67 d2 19 rcrb %cl, (%ecx) 41 d2 19 rcrb %cl, (%r9) 48 d2 19 rex.W rcrb %cl, (%rcx) 49 d2 19 rex.WB rcrb %cl, (%r9) d3 01 roll %cl, (%rcx) 66 d3 01 rolw %cl, (%rcx) 67 d3 01 roll %cl, (%ecx) 41 d3 01 roll %cl, (%r9) 48 d3 01 rolq %cl, (%rcx) 49 d3 01 rolq %cl, (%r9) d3 09 rorl %cl, (%rcx) 66 d3 09 rorw %cl, (%rcx) 67 d3 09 rorl %cl, (%ecx) 41 d3 09 rorl %cl, (%r9) 48 d3 09 rorq %cl, (%rcx) 49 d3 09 rorq %cl, (%r9) d3 11 rcll %cl, (%rcx) 66 d3 11 rclw %cl, (%rcx) 67 d3 11 rcll %cl, (%ecx) 41 d3 11 rcll %cl, (%r9) 48 d3 11 rclq %cl, (%rcx) 49 d3 11 rclq %cl, (%r9) d3 19 rcrl %cl, (%rcx) 66 d3 19 rcrw %cl, (%rcx) 67 d3 19 rcrl %cl, (%ecx) 41 d3 19 rcrl %cl, (%r9) 48 d3 19 rcrq %cl, (%rcx) 49 d3 19 rcrq %cl, (%r9)

jared-hughes/defcpu

2,441

tests/disassembly/sources/023_xchg.s

90 nop 91 xchg %eax, %ecx 92 xchg %eax, %edx 93 xchg %eax, %ebx 94 xchg %eax, %esp 95 xchg %eax, %ebp 96 xchg %eax, %esi 97 xchg %eax, %edi 66 90 xchg %ax, %ax 66 91 xchg %ax, %cx 66 92 xchg %ax, %dx 66 93 xchg %ax, %bx 66 94 xchg %ax, %sp 66 95 xchg %ax, %bp 66 96 xchg %ax, %si 66 97 xchg %ax, %di 41 90 xchg %eax, %r8d 41 91 xchg %eax, %r9d 41 92 xchg %eax, %r10d 41 93 xchg %eax, %r11d 41 94 xchg %eax, %r12d 41 95 xchg %eax, %r13d 41 96 xchg %eax, %r14d 41 97 xchg %eax, %r15d 66 41 90 xchg %ax, %r8w 66 41 91 xchg %ax, %r9w 66 41 92 xchg %ax, %r10w 66 41 93 xchg %ax, %r11w 66 41 94 xchg %ax, %r12w 66 41 95 xchg %ax, %r13w 66 41 96 xchg %ax, %r14w 66 41 97 xchg %ax, %r15w 48 90 rex.W nop 48 91 xchg %rax, %rcx 48 92 xchg %rax, %rdx 48 93 xchg %rax, %rbx 48 94 xchg %rax, %rsp 48 95 xchg %rax, %rbp 48 96 xchg %rax, %rsi 48 97 xchg %rax, %rdi 49 90 xchg %rax, %r8 49 91 xchg %rax, %r9 49 92 xchg %rax, %r10 49 93 xchg %rax, %r11 49 94 xchg %rax, %r12 49 95 xchg %rax, %r13 49 96 xchg %rax, %r14 49 97 xchg %rax, %r15 86 13 xchg %dl, (%rbx) 66 48 90 xchg %rax, %rax 66 48 91 data16 xchg %rax, %rcx 66 48 92 data16 xchg %rax, %rdx 66 48 93 data16 xchg %rax, %rbx 66 48 94 data16 xchg %rax, %rsp 66 48 95 data16 xchg %rax, %rbp 66 48 96 data16 xchg %rax, %rsi 66 48 97 data16 xchg %rax, %rdi 66 49 90 xchg %rax, %r8 66 49 91 data16 xchg %rax, %r9 66 49 92 data16 xchg %rax, %r10 66 49 93 data16 xchg %rax, %r11 66 49 94 data16 xchg %rax, %r12 66 49 95 data16 xchg %rax, %r13 66 49 96 data16 xchg %rax, %r14 66 49 97 data16 xchg %rax, %r15 86 13 xchg %dl, (%rbx) 66 86 13 data16 xchg %dl, (%rbx) 67 86 13 xchg %dl, (%ebx) 40 86 13 rex xchg %dl, (%rbx) 41 86 13 xchg %dl, (%r11) 48 86 13 rex.W xchg %dl, (%rbx) 49 86 13 rex.WB xchg %dl, (%r11) 87 13 xchg %edx, (%rbx) 66 87 13 xchg %dx, (%rbx) 67 87 13 xchg %edx, (%ebx) 40 87 13 rex xchg %edx, (%rbx) 41 87 13 xchg %edx, (%r11) 48 87 13 xchg %rdx, (%rbx) 49 87 13 xchg %rdx, (%r11)

jared-hughes/defcpu

16,420

tests/disassembly/sources/010_fuzz_prefix_mov.s

88 b8 67 66 4f 66 mov %bh, 0x664f6667(%rax) bf 4a 67 8a 88 mov $0x888a674a, %edi b8 4c 67 b0 b8 mov $0xb8b0674c, %eax c6 40 c6 67 movb $0x67, -0x3a(%rax) 66 c6 data16 (bad) 88 c6 mov %al, %dh 88 66 66 mov %ah, 0x66(%rsi) 66 40 data16 rex 47 rex.RXB 4f 8a b3 4c c7 c6 67 rex.WRXB mov 0x67c6c74c(%r11), %r14b c7 c6 47 67 66 bf mov $0xbf666747, %esi 66 c6 c7 88 data16 mov $0x88, %bh 4c c7 rex.WR (bad) 66 66 67 66 67 c7 40 66 c6 4a data16 data16 addr32 movw $0x4ac6, 0x66(%eax) 88 40 67 mov %al, 0x67(%rax) 8a 4f 4a mov 0x4a(%rdi), %cl 66 88 c6 data16 mov %al, %dh 47 b8 4a 47 c7 b3 rex.RXB mov $0xb3c7474a, %r8d 66 66 67 4a data16 data16 addr32 rex.WX 4c rex.WR 4f b0 4a rex.WRXB mov $0x4a, %r8b 8a 4c b3 8a mov -0x76(%rbx, %rsi, 4), %cl b0 66 mov $0x66, %al 88 4c 67 66 mov %cl, 0x66(%rdi, %riz, 2) b9 c7 4c c6 b3 mov $0xb3c64cc7, %ecx 4f rex.WRXB 66 b8 c6 40 mov $0x40c6, %ax 40 rex 66 b0 bf data16 mov $0xbf, %al b8 4f c6 66 c6 mov $0xc666c64f, %eax b3 40 mov $0x40, %bl 47 c6 rex.RXB (bad) 67 66 66 b8 8a 40 addr32 data16 mov $0x408a, %ax c6 (bad) 67 bf 8a b3 b3 c7 addr32 mov $0xc7b3b38a, %edi c6 (bad) 4c rex.WR 67 47 b3 67 addr32 rex.RXB mov $0x67, %r11b 88 66 67 mov %ah, 0x67(%rsi) 66 b3 c6 data16 mov $0xc6, %bl 4a rex.WX 67 c7 addr32 (bad) b8 67 4a 88 47 mov $0x47884a67, %eax 66 66 88 66 67 data16 data16 mov %ah, 0x67(%rsi) 4c rex.WR 67 b9 67 47 8a c7 addr32 mov $0xc78a4767, %ecx 40 rex 4a rex.WX 67 c7 addr32 (bad) b0 c7 mov $0xc7, %al 88 8a 67 c6 c7 66 mov %cl, 0x66c7c667(%rdx) b3 c6 mov $0xc6, %bl 4c 88 b9 66 47 c7 67 rex.WR mov %r15b, 0x67c74766(%rcx) 8a 67 b0 mov -0x50(%rdi), %ah 67 4f bf 67 66 c6 66 4a 40 c7 66 addr32 rex.WRXB movabs $0x66c7404a66c66667, %r15 66 66 47 b8 4f 4a data16 rex.RXB mov $0x4a4f, %r8w 40 rex 40 88 66 c7 mov %spl, -0x39(%rsi) 67 67 b8 4a c7 67 67 addr32 addr32 mov $0x6767c74a, %eax 4f 8a b0 66 4f 4c c6 rex.WRXB mov -0x39b3b09a(%r8), %r14b b0 67 mov $0x67, %al c6 47 4c 88 movb $0x88, 0x4c(%rdi) 88 4f c6 mov %cl, -0x3a(%rdi) b0 c7 mov $0xc7, %al c7 (bad) 67 b3 c7 addr32 mov $0xc7, %bl 66 bf c6 66 mov $0x66c6, %di c7 (bad) b8 b8 8a 67 47 mov $0x47678ab8, %eax 40 rex 66 8a 4f 66 data16 mov 0x66(%rdi), %cl c7 (bad) b9 4c 66 c7 c7 mov $0xc7c7664c, %ecx 66 4a data16 rex.WX 66 66 8a 88 b3 b0 b0 67 data16 data16 mov 0x67b0b0b3(%rax), %cl 4c rex.WR 66 b0 8a data16 mov $0x8a, %al b3 66 mov $0x66, %bl b0 4c mov $0x4c, %al b9 4a b3 b3 88 mov $0x88b3b34a, %ecx b0 67 mov $0x67, %al 8a 8a b0 b9 c7 4c mov 0x4cc7b9b0(%rdx), %cl b9 b3 b0 67 4c mov $0x4c67b0b3, %ecx c6 (bad) 66 c6 data16 (bad) 4f rex.WRXB 47 rex.RXB 47 c6 rex.RXB (bad) 8a 88 40 8a b9 c6 mov -0x394675c0(%rax), %cl 40 bf b8 4a 67 66 rex mov $0x66674ab8, %edi 88 66 67 mov %ah, 0x67(%rsi) c6 (bad) b3 b8 mov $0xb8, %bl 8a 66 40 mov 0x40(%rsi), %ah b8 b8 4c b8 40 mov $0x40b84cb8, %eax bf 88 88 b3 4c mov $0x4cb38888, %edi 4c rex.WR 66 40 b8 c7 66 rex mov $0x66c7, %ax 4c rex.WR 4c rex.WR 4a rex.WX 67 b8 8a b0 b0 8a addr32 mov $0x8ab0b08a, %eax 4a c6 c7 4c rex.WX mov $0x4c, %dil 67 4c c7 addr32 rex.WR (bad) 67 4a 88 88 b3 4f 67 8a rex.WX mov %cl, -0x7598b04d(%eax) 4f rex.WRXB 47 rex.RXB 67 bf 66 88 c7 4f addr32 mov $0x4fc78866, %edi 66 66 47 data16 data16 rex.RXB 47 rex.RXB 40 rex 47 rex.RXB 4c b9 4c 67 47 c6 4a 88 b9 8a rex.WR movabs $0x8ab9884ac647674c, %rcx 66 67 b9 4c 66 addr32 mov $0x664c, %cx 4a rex.WX 66 c7 data16 (bad) 8a bf 66 4a 88 66 mov 0x66884a66(%rdi), %bh b8 4a 47 8a c7 mov $0xc78a474a, %eax 88 40 66 mov %al, 0x66(%rax) 8a 67 b8 mov -0x48(%rdi), %ah 66 b9 40 bf mov $0xbf40, %cx 66 4f data16 rex.WRXB 67 40 c7 addr32 rex (bad) 66 67 c7 data16 addr32 (bad) 67 4a addr32 rex.WX 67 47 addr32 rex.RXB 4a rex.WX 67 88 66 88 mov %ah, -0x78(%esi) b8 67 8a b3 67 mov $0x67b38a67, %eax 67 88 66 4c mov %ah, 0x4c(%esi) 66 67 88 88 b8 b3 88 88 data16 mov %cl, -0x77774c48(%eax) 67 66 67 67 40 addr32 data16 addr32 addr32 rex 67 4c addr32 rex.WR 66 67 b0 4a data16 addr32 mov $0x4a, %al 66 66 c6 data16 data16 (bad) 67 bf 4f b9 4c 67 addr32 mov $0x674cb94f, %edi 88 b8 b8 c7 bf c6 mov %bh, -0x39403848(%rax) 67 66 c6 addr32 data16 (bad) b0 c7 mov $0xc7, %al 67 4c addr32 rex.WR 4a bf b0 88 8a 66 c6 67 c7 c7 rex.WX movabs $0xc7c767c6668a88b0, %rdi 8a 8a 47 88 c6 4a mov 0x4ac68847(%rdx), %cl 67 b0 66 addr32 mov $0x66, %al 4c rex.WR 66 4a data16 rex.WX 67 40 addr32 rex 4c rex.WR 4f rex.WRXB 67 66 c6 47 8a c7 data16 movb $0xc7, -0x76(%edi) 67 b9 67 67 b3 8a addr32 mov $0x8ab36767, %ecx 4f 8a c6 rex.WRXB mov %r14b, %r8b 67 67 66 66 67 67 b3 66 addr32 addr32 data16 data16 addr32 addr32 mov $0x66, %bl c7 (bad) b8 c7 66 b3 66 mov $0x66b366c7, %eax 4a rex.WX 67 bf 4a 66 8a 8a addr32 mov $0x8a8a664a, %edi c7 (bad) bf 88 c7 4c 66 mov $0x664cc788, %edi 67 4f 8a 88 8a bf 66 66 rex.WRXB mov 0x6666bf8a(%r8d), %r9b 67 4f c6 addr32 rex.WRXB (bad) bf 67 c6 b8 40 mov $0x40b8c667, %edi b0 66 mov $0x66, %al 67 4a b3 66 addr32 rex.WX mov $0x66, %bl b0 c7 mov $0xc7, %al bf c7 47 88 4f mov $0x4f8847c7, %edi 67 66 c6 addr32 data16 (bad) b0 4f mov $0x4f, %al 88 66 8a mov %ah, -0x76(%rsi) 66 bf b3 88 mov $0x88b3, %di 4a b0 40 rex.WX mov $0x40, %al c7 c6 67 8a 67 40 mov $0x40678a67, %esi 67 c7 c7 67 88 88 b9 addr32 mov $0xb9888867, %edi c6 (bad) 66 b0 47 data16 mov $0x47, %al 66 b3 4c data16 mov $0x4c, %bl 67 66 66 c7 addr32 data16 data16 (bad) 8a 8a 66 c7 8a 4a mov 0x4a8ac766(%rdx), %cl bf b0 67 bf 66 mov $0x66bf67b0, %edi 66 4a data16 rex.WX 40 c6 rex (bad) b3 b3 mov $0xb3, %bl 66 bf 67 67 mov $0x6767, %di c6 (bad) 4f rex.WRXB 67 67 67 40 addr32 addr32 addr32 rex 4c rex.WR 67 c7 addr32 (bad) 66 88 88 c6 40 67 66 data16 mov %cl, 0x666740c6(%rax) 4f b3 c6 rex.WRXB mov $0xc6, %r11b 66 b9 bf c7 mov $0xc7bf, %cx 8a b3 67 c7 c7 8a mov -0x75383899(%rbx), %dh 4f rex.WRXB 67 40 addr32 rex 67 4f addr32 rex.WRXB 67 88 8a c6 66 bf b9 mov %cl, -0x4640993a(%edx) b8 47 8a 8a 8a mov $0x8a8a8a47, %eax 66 66 67 b8 c7 67 data16 addr32 mov $0x67c7, %ax b0 4a mov $0x4a, %al 66 c6 40 b9 8a data16 movb $0x8a, -0x47(%rax) 88 67 47 mov %ah, 0x47(%rdi) 66 4a data16 rex.WX 66 88 c6 data16 mov %al, %dh 47 rex.RXB 66 67 67 66 4a data16 addr32 addr32 data16 rex.WX 66 bf b9 88 mov $0x88b9, %di 66 67 b9 67 67 addr32 mov $0x6767, %cx b0 66 mov $0x66, %al b0 bf mov $0xbf, %al 4a rex.WX 4f c6 rex.WRXB (bad) 66 4c data16 rex.WR 40 rex 66 4a data16 rex.WX 66 c6 data16 (bad) 88 67 67 mov %ah, 0x67(%rdi) b0 c7 mov $0xc7, %al c6 (bad) 4c rex.WR 47 c6 rex.RXB (bad) 88 c6 mov %al, %dh 88 66 40 mov %ah, 0x40(%rsi) 66 b3 4f data16 mov $0x4f, %bl 8a b3 88 67 c6 bf mov -0x40399878(%rbx), %dh 66 b9 67 c6 mov $0xc667, %cx 8a 8a 88 40 66 b0 mov -0x4f99bf78(%rdx), %cl 67 66 88 67 67 data16 mov %ah, 0x67(%edi) 88 c7 mov %al, %bh b0 88 mov $0x88, %al c6 c7 47 mov $0x47, %bh 40 rex 67 c6 addr32 (bad) bf bf 66 88 66 mov $0x668866bf, %edi 67 88 67 4c mov %ah, 0x4c(%edi) c7 (bad) 88 8a c6 66 4c b9 mov %cl, -0x46b3993a(%rdx) 47 c7 c6 b9 67 88 8a rex.RXB mov $0x8a8867b9, %r14d 4a rex.WX 67 88 4c 67 66 mov %cl, 0x66(%edi, %eiz, 2) 66 b3 8a data16 mov $0x8a, %bl 66 b8 4a 66 mov $0x664a, %ax 67 c6 addr32 (bad) 4a 8a 47 b3 rex.WX mov -0x4d(%rdi), %al b3 4a mov $0x4a, %bl 66 88 b8 47 67 8a 66 data16 mov %bh, 0x668a6747(%rax) c6 (bad) 66 4c 8a 8a bf 67 4f c6 data16 rex.WR mov -0x39b09841(%rdx), %r9b 88 66 66 mov %ah, 0x66(%rsi) 67 8a 67 b9 mov -0x47(%edi), %ah c6 (bad) 8a c7 mov %bh, %al c7 (bad) 8a b9 67 bf 8a c7 mov -0x38754099(%rcx), %bh 88 40 b3 mov %al, -0x4d(%rax) b0 b9 mov $0xb9, %al c6 (bad) 8a 4c 4c 88 mov -0x78(%rsp, %rcx, 2), %cl c7 c7 c6 67 4c c7 mov $0xc74c67c6, %edi 8a 66 b3 mov -0x4d(%rsi), %ah b0 b8 mov $0xb8, %al 4f b9 8a c6 88 b0 8a 47 b3 8a rex.WRXB movabs $0x8ab3478ab088c68a, %r9 4a c6 rex.WX (bad) 67 88 c6 addr32 mov %al, %dh b3 4c mov $0x4c, %bl b3 c6 mov $0xc6, %bl 66 c7 data16 (bad) b0 66 mov $0x66, %al 66 4a data16 rex.WX 67 8a c6 addr32 mov %dh, %al 88 8a c7 67 67 c7 mov %cl, -0x38989839(%rdx) 66 66 c6 data16 data16 (bad) 67 c6 c6 67 addr32 mov $0x67, %dh 67 8a 4c c7 67 mov 0x67(%edi, %eax, 8), %cl c6 (bad) 67 47 b3 66 addr32 rex.RXB mov $0x66, %r11b 67 c7 40 b8 67 c7 8a 4c movl $0x4c8ac767, -0x48(%eax) 67 88 66 88 mov %ah, -0x78(%esi) 67 67 88 8a 40 66 66 bf addr32 mov %cl, -0x409999c0(%edx) 47 b3 4c rex.RXB mov $0x4c, %r11b 4c rex.WR 4c c7 rex.WR (bad) bf 67 4a 8a 67 mov $0x678a4a67, %edi c7 40 88 c6 66 66 4c movl $0x4c6666c6, -0x78(%rax) 66 47 data16 rex.RXB 47 c7 rex.RXB (bad) 66 66 b9 67 66 data16 mov $0x6667, %cx 66 66 c6 c6 bf data16 data16 mov $0xbf, %dh c6 (bad) 66 8a b3 b0 66 88 c6 data16 mov -0x39779950(%rbx), %dh bf 66 88 66 67 mov $0x67668866, %edi c6 (bad) 4c rex.WR 66 66 4f c6 00 00 data16 data16 rex.WRXB movb $0x0, (%r8)

jared-hughes/defcpu

14,596

tests/disassembly/sources/012_inc_dec_div_not.s

fe 00 incb (%rax) fe 04 f4 incb (%rsp, %rsi, 8) fe 05 f4 f4 f4 f4 incb -0xb0b0b0c(%rip) fe 06 incb (%rsi) fe 40 f4 incb -0xc(%rax) fe c3 inc %bl fe c4 inc %ah 41 fe 00 incb (%r8) 41 fe 04 12 incb (%r10, %rdx, 1) 41 fe 05 12 34 56 78 incb 0x78563412(%rip) 41 fe 06 incb (%r14) ff 00 incl (%rax) ff 04 f4 incl (%rsp, %rsi, 8) ff 05 f4 f4 f4 f4 incl -0xb0b0b0c(%rip) ff 06 incl (%rsi) ff 40 f4 incl -0xc(%rax) ff c3 inc %ebx ff c4 inc %esp 41 ff 00 incl (%r8) 41 ff 04 12 incl (%r10, %rdx, 1) 41 ff 05 12 34 56 78 incl 0x78563412(%rip) 41 ff 06 incl (%r14) 66 ff 00 incw (%rax) 66 ff 04 f4 incw (%rsp, %rsi, 8) 66 ff 05 f4 f4 f4 f4 incw -0xb0b0b0c(%rip) 66 ff 06 incw (%rsi) 66 ff 40 f4 incw -0xc(%rax) 66 ff c3 inc %bx 66 ff c4 inc %sp 66 41 ff 00 incw (%r8) 66 41 ff 04 12 incw (%r10, %rdx, 1) 66 41 ff 05 12 34 56 78 incw 0x78563412(%rip) 66 41 ff 06 incw (%r14) 67 ff 00 incl (%eax) 67 ff 04 f4 incl (%esp, %esi, 8) 67 ff 05 f4 f4 f4 f4 incl -0xb0b0b0c(%eip) 67 ff 06 incl (%esi) 67 ff 40 f4 incl -0xc(%eax) 67 ff c3 addr32 inc %ebx 67 ff c4 addr32 inc %esp 67 41 ff 00 incl (%r8d) 67 41 ff 04 12 incl (%r10d, %edx, 1) 67 41 ff 05 12 34 56 78 incl 0x78563412(%eip) 67 41 ff 06 incl (%r14d) 66 67 ff 00 incw (%eax) 66 67 ff 04 f4 incw (%esp, %esi, 8) 66 67 ff 05 f4 f4 f4 f4 incw -0xb0b0b0c(%eip) 66 67 ff 06 incw (%esi) 66 67 ff 40 f4 incw -0xc(%eax) 66 67 ff c3 addr32 inc %bx 66 67 ff c4 addr32 inc %sp 66 67 41 ff 00 incw (%r8d) 66 67 41 ff 04 12 incw (%r10d, %edx, 1) 66 67 41 ff 05 12 34 56 78 incw 0x78563412(%eip) 66 67 41 ff 06 incw (%r14d) 66 67 48 ff 00 data16 incq (%eax) 66 67 48 ff 04 f4 data16 incq (%esp, %esi, 8) 66 67 48 ff 05 f4 f4 f4 f4 data16 incq -0xb0b0b0c(%eip) 48 ff 06 incq (%rsi) 48 ff 40 f4 incq -0xc(%rax) 48 ff c3 inc %rbx 48 ff c4 inc %rsp 49 ff 00 incq (%r8) 49 ff 04 f4 incq (%r12, %rsi, 8) 49 ff 05 f4 f4 f4 f4 incq -0xb0b0b0c(%rip) 49 ff 06 incq (%r14) 49 ff 40 f4 incq -0xc(%r8) 49 ff c3 inc %r11 49 ff c4 inc %r12 67 48 ff 06 incq (%esi) 67 48 ff 40 f4 incq -0xc(%eax) 67 48 ff c3 addr32 inc %rbx 67 48 ff c4 addr32 inc %rsp 67 49 ff 00 incq (%r8d) 67 49 ff 04 f4 incq (%r12d, %esi, 8) 67 49 ff 05 f4 f4 f4 f4 incq -0xb0b0b0c(%eip) 67 49 ff 06 incq (%r14d) 67 49 ff 40 f4 incq -0xc(%r8d) 67 49 ff c3 addr32 inc %r11 67 49 ff c4 addr32 inc %r12 fe 08 decb (%rax) fe 0c f4 decb (%rsp, %rsi, 8) fe 0d f4 f4 f4 f4 decb -0xb0b0b0c(%rip) fe 0e decb (%rsi) fe 48 f4 decb -0xc(%rax) fe cb dec %bl fe cc dec %ah 41 fe 08 decb (%r8) 41 fe 0c 12 decb (%r10, %rdx, 1) 41 fe 0d 12 34 56 78 decb 0x78563412(%rip) 41 fe 0e decb (%r14) ff 08 decl (%rax) ff 0c f4 decl (%rsp, %rsi, 8) ff 0d f4 f4 f4 f4 decl -0xb0b0b0c(%rip) ff 0e decl (%rsi) ff 48 f4 decl -0xc(%rax) ff cb dec %ebx ff cc dec %esp 41 ff 08 decl (%r8) 41 ff 0c 12 decl (%r10, %rdx, 1) 41 ff 0d 12 34 56 78 decl 0x78563412(%rip) 41 ff 0e decl (%r14) 66 ff 08 decw (%rax) 66 ff 0c f4 decw (%rsp, %rsi, 8) 66 ff 0d f4 f4 f4 f4 decw -0xb0b0b0c(%rip) 66 ff 0e decw (%rsi) 66 ff 48 f4 decw -0xc(%rax) 66 ff cb dec %bx 66 ff cc dec %sp 66 41 ff 08 decw (%r8) 66 41 ff 0c 12 decw (%r10, %rdx, 1) 66 41 ff 0d 12 34 56 78 decw 0x78563412(%rip) 66 41 ff 0e decw (%r14) 67 ff 08 decl (%eax) 67 ff 0c f4 decl (%esp, %esi, 8) 67 ff 0d f4 f4 f4 f4 decl -0xb0b0b0c(%eip) 67 ff 0e decl (%esi) 67 ff 48 f4 decl -0xc(%eax) 67 ff cb addr32 dec %ebx 67 ff cc addr32 dec %esp 67 41 ff 08 decl (%r8d) 67 41 ff 0c 12 decl (%r10d, %edx, 1) 67 41 ff 0d 12 34 56 78 decl 0x78563412(%eip) 67 41 ff 0e decl (%r14d) 66 67 ff 08 decw (%eax) 66 67 ff 0c f4 decw (%esp, %esi, 8) 66 67 ff 0d f4 f4 f4 f4 decw -0xb0b0b0c(%eip) 66 67 ff 0e decw (%esi) 66 67 ff 48 f4 decw -0xc(%eax) 66 67 ff cb addr32 dec %bx 66 67 ff cc addr32 dec %sp 66 67 41 ff 08 decw (%r8d) 66 67 41 ff 0c 12 decw (%r10d, %edx, 1) 66 67 41 ff 0d 12 34 56 78 decw 0x78563412(%eip) 66 67 41 ff 0e decw (%r14d) 66 67 48 ff 08 data16 decq (%eax) 66 67 48 ff 0c f4 data16 decq (%esp, %esi, 8) 66 67 48 ff 0d f4 f4 f4 f4 data16 decq -0xb0b0b0c(%eip) 48 ff 0e decq (%rsi) 48 ff 48 f4 decq -0xc(%rax) 48 ff cb dec %rbx 48 ff cc dec %rsp 49 ff 08 decq (%r8) 49 ff 0c f4 decq (%r12, %rsi, 8) 49 ff 0d f4 f4 f4 f4 decq -0xb0b0b0c(%rip) 49 ff 0e decq (%r14) 49 ff 48 f4 decq -0xc(%r8) 49 ff cb dec %r11 49 ff cc dec %r12 67 48 ff 0e decq (%esi) 67 48 ff 48 f4 decq -0xc(%eax) 67 48 ff cb addr32 dec %rbx 67 48 ff cc addr32 dec %rsp 67 49 ff 08 decq (%r8d) 67 49 ff 0c f4 decq (%r12d, %esi, 8) 67 49 ff 0d f4 f4 f4 f4 decq -0xb0b0b0c(%eip) 67 49 ff 0e decq (%r14d) 67 49 ff 48 f4 decq -0xc(%r8d) 67 49 ff cb addr32 dec %r11 67 49 ff cc addr32 dec %r12 f6 30 divb (%rax) f6 34 f4 divb (%rsp, %rsi, 8) f6 35 f4 f4 f4 f4 divb -0xb0b0b0c(%rip) f6 36 divb (%rsi) f6 70 f4 divb -0xc(%rax) f6 f3 div %bl f6 f4 div %ah 41 f6 30 divb (%r8) 41 f6 34 12 divb (%r10, %rdx, 1) 41 f6 35 12 34 56 78 divb 0x78563412(%rip) 41 f6 36 divb (%r14) f7 30 divl (%rax) f7 34 f4 divl (%rsp, %rsi, 8) f7 35 f4 f4 f4 f4 divl -0xb0b0b0c(%rip) f7 36 divl (%rsi) f7 70 f4 divl -0xc(%rax) f7 f3 div %ebx f7 f4 div %esp 41 f7 30 divl (%r8) 41 f7 34 12 divl (%r10, %rdx, 1) 41 f7 35 12 34 56 78 divl 0x78563412(%rip) 41 f7 36 divl (%r14) 66 f7 30 divw (%rax) 66 f7 34 f4 divw (%rsp, %rsi, 8) 66 f7 35 f4 f4 f4 f4 divw -0xb0b0b0c(%rip) 66 f7 36 divw (%rsi) 66 f7 70 f4 divw -0xc(%rax) 66 f7 f3 div %bx 66 f7 f4 div %sp 66 41 f7 30 divw (%r8) 66 41 f7 34 12 divw (%r10, %rdx, 1) 66 41 f7 35 12 34 56 78 divw 0x78563412(%rip) 66 41 f7 36 divw (%r14) 67 f7 30 divl (%eax) 67 f7 34 f4 divl (%esp, %esi, 8) 67 f7 35 f4 f4 f4 f4 divl -0xb0b0b0c(%eip) 67 f7 36 divl (%esi) 67 f7 70 f4 divl -0xc(%eax) 67 f7 f3 addr32 div %ebx 67 f7 f4 addr32 div %esp 67 41 f7 30 divl (%r8d) 67 41 f7 34 12 divl (%r10d, %edx, 1) 67 41 f7 35 12 34 56 78 divl 0x78563412(%eip) 67 41 f7 36 divl (%r14d) 66 67 f7 30 divw (%eax) 66 67 f7 34 f4 divw (%esp, %esi, 8) 66 67 f7 35 f4 f4 f4 f4 divw -0xb0b0b0c(%eip) 66 67 f7 36 divw (%esi) 66 67 f7 70 f4 divw -0xc(%eax) 66 67 f7 f3 addr32 div %bx 66 67 f7 f4 addr32 div %sp 66 67 41 f7 30 divw (%r8d) 66 67 41 f7 34 12 divw (%r10d, %edx, 1) 66 67 41 f7 35 12 34 56 78 divw 0x78563412(%eip) 66 67 41 f7 36 divw (%r14d) 66 67 48 f7 30 data16 divq (%eax) 66 67 48 f7 34 f4 data16 divq (%esp, %esi, 8) 66 67 48 f7 35 f4 f4 f4 f4 data16 divq -0xb0b0b0c(%eip) 48 f7 36 divq (%rsi) 48 f7 70 f4 divq -0xc(%rax) 48 f7 f3 div %rbx 48 f7 f4 div %rsp 49 f7 30 divq (%r8) 49 f7 34 f4 divq (%r12, %rsi, 8) 49 f7 35 f4 f4 f4 f4 divq -0xb0b0b0c(%rip) 49 f7 36 divq (%r14) 49 f7 70 f4 divq -0xc(%r8) 49 f7 f3 div %r11 49 f7 f4 div %r12 67 48 f7 36 divq (%esi) 67 48 f7 70 f4 divq -0xc(%eax) 67 48 f7 f3 addr32 div %rbx 67 48 f7 f4 addr32 div %rsp 67 49 f7 30 divq (%r8d) 67 49 f7 34 f4 divq (%r12d, %esi, 8) 67 49 f7 35 f4 f4 f4 f4 divq -0xb0b0b0c(%eip) 67 49 f7 36 divq (%r14d) 67 49 f7 70 f4 divq -0xc(%r8d) 67 49 f7 f3 addr32 div %r11 67 49 f7 f4 addr32 div %r12 f6 10 notb (%rax) f6 14 f4 notb (%rsp, %rsi, 8) f6 15 f4 f4 f4 f4 notb -0xb0b0b0c(%rip) f6 16 notb (%rsi) f6 50 f4 notb -0xc(%rax) f6 d3 not %bl f6 d4 not %ah 41 f6 10 notb (%r8) 41 f6 14 12 notb (%r10, %rdx, 1) 41 f6 15 12 34 56 78 notb 0x78563412(%rip) 41 f6 16 notb (%r14) f7 10 notl (%rax) f7 14 f4 notl (%rsp, %rsi, 8) f7 15 f4 f4 f4 f4 notl -0xb0b0b0c(%rip) f7 16 notl (%rsi) f7 50 f4 notl -0xc(%rax) f7 d3 not %ebx f7 d4 not %esp 41 f7 10 notl (%r8) 41 f7 14 12 notl (%r10, %rdx, 1) 41 f7 15 12 34 56 78 notl 0x78563412(%rip) 41 f7 16 notl (%r14) 66 f7 10 notw (%rax) 66 f7 14 f4 notw (%rsp, %rsi, 8) 66 f7 15 f4 f4 f4 f4 notw -0xb0b0b0c(%rip) 66 f7 16 notw (%rsi) 66 f7 50 f4 notw -0xc(%rax) 66 f7 d3 not %bx 66 f7 d4 not %sp 66 41 f7 10 notw (%r8) 66 41 f7 14 12 notw (%r10, %rdx, 1) 66 41 f7 15 12 34 56 78 notw 0x78563412(%rip) 66 41 f7 16 notw (%r14) 67 f7 10 notl (%eax) 67 f7 14 f4 notl (%esp, %esi, 8) 67 f7 15 f4 f4 f4 f4 notl -0xb0b0b0c(%eip) 67 f7 16 notl (%esi) 67 f7 50 f4 notl -0xc(%eax) 67 f7 d3 addr32 not %ebx 67 f7 d4 addr32 not %esp 67 41 f7 10 notl (%r8d) 67 41 f7 14 12 notl (%r10d, %edx, 1) 67 41 f7 15 12 34 56 78 notl 0x78563412(%eip) 67 41 f7 16 notl (%r14d) 66 67 f7 10 notw (%eax) 66 67 f7 14 f4 notw (%esp, %esi, 8) 66 67 f7 15 f4 f4 f4 f4 notw -0xb0b0b0c(%eip) 66 67 f7 16 notw (%esi) 66 67 f7 50 f4 notw -0xc(%eax) 66 67 f7 d3 addr32 not %bx 66 67 f7 d4 addr32 not %sp 66 67 41 f7 10 notw (%r8d) 66 67 41 f7 14 12 notw (%r10d, %edx, 1) 66 67 41 f7 15 12 34 56 78 notw 0x78563412(%eip) 66 67 41 f7 16 notw (%r14d) 66 67 48 f7 10 data16 notq (%eax) 66 67 48 f7 14 f4 data16 notq (%esp, %esi, 8) 66 67 48 f7 15 f4 f4 f4 f4 data16 notq -0xb0b0b0c(%eip) 48 f7 16 notq (%rsi) 48 f7 50 f4 notq -0xc(%rax) 48 f7 d3 not %rbx 48 f7 d4 not %rsp 49 f7 10 notq (%r8) 49 f7 14 f4 notq (%r12, %rsi, 8) 49 f7 15 f4 f4 f4 f4 notq -0xb0b0b0c(%rip) 49 f7 16 notq (%r14) 49 f7 50 f4 notq -0xc(%r8) 49 f7 d3 not %r11 49 f7 d4 not %r12 67 48 f7 16 notq (%esi) 67 48 f7 50 f4 notq -0xc(%eax) 67 48 f7 d3 addr32 not %rbx 67 48 f7 d4 addr32 not %rsp 67 49 f7 10 notq (%r8d) 67 49 f7 14 f4 notq (%r12d, %esi, 8) 67 49 f7 15 f4 f4 f4 f4 notq -0xb0b0b0c(%eip) 67 49 f7 16 notq (%r14d) 67 49 f7 50 f4 notq -0xc(%r8d) 67 49 f7 d3 addr32 not %r11 67 49 f7 d4 addr32 not %r12

jared-hughes/defcpu

38,137

tests/disassembly/sources/013_add_and_sub_cmp_xor_bt.s

04 12 add $0x12, %al 66 05 12 34 add $0x3412, %ax 05 12 34 56 78 add $0x78563412, %eax 41 05 12 34 56 78 rex.B add $0x78563412, %eax 41 05 12 34 56 88 rex.B add $0x88563412, %eax 48 05 12 34 56 78 add $0x78563412, %rax 48 05 12 34 56 88 add $0xffffffff88563412, %rax 49 05 12 34 56 78 rex.WB add $0x78563412, %rax 49 05 12 34 56 88 rex.WB add $0xffffffff88563412, %rax 80 c0 12 add $0x12, %al 80 c6 12 add $0x12, %dh 40 80 c6 12 add $0x12, %sil 66 81 c6 12 34 add $0x3412, %si 81 c6 12 34 56 78 add $0x78563412, %esi 48 81 c6 12 34 56 78 add $0x78563412, %rsi 48 81 c6 12 34 56 88 add $0xffffffff88563412, %rsi 66 83 c6 12 add $0x12, %si 66 83 c6 82 add $0xff82, %si 83 c6 12 add $0x12, %esi 83 c6 82 add $0xffffff82, %esi 41 83 c6 12 add $0x12, %r14d 41 83 c6 82 add $0xffffff82, %r14d 48 83 c6 12 add $0x12, %rsi 48 83 c6 82 add $0xffffffffffffff82, %rsi 49 83 c6 12 add $0x12, %r14 49 83 c6 82 add $0xffffffffffffff82, %r14 00 23 add %ah, (%rbx) 66 00 23 data16 add %ah, (%rbx) 67 00 23 add %ah, (%ebx) 66 67 00 23 data16 add %ah, (%ebx) 40 00 23 add %spl, (%rbx) 67 40 00 23 add %spl, (%ebx) 66 40 00 23 data16 add %spl, (%rbx) 66 67 40 00 23 data16 add %spl, (%ebx) 41 00 23 add %spl, (%r11) 67 41 00 23 add %spl, (%r11d) 66 41 00 23 data16 add %spl, (%r11) 66 67 41 00 23 data16 add %spl, (%r11d) 48 00 23 rex.W add %spl, (%rbx) 67 48 00 23 rex.W add %spl, (%ebx) 66 48 00 23 data16 rex.W add %spl, (%rbx) 66 67 48 00 23 data16 rex.W add %spl, (%ebx) 01 23 add %esp, (%rbx) 66 01 23 add %sp, (%rbx) 67 01 23 add %esp, (%ebx) 66 67 01 23 add %sp, (%ebx) 40 01 23 rex add %esp, (%rbx) 67 40 01 23 rex add %esp, (%ebx) 66 40 01 23 rex add %sp, (%rbx) 66 67 40 01 23 rex add %sp, (%ebx) 41 01 23 add %esp, (%r11) 67 41 01 23 add %esp, (%r11d) 66 41 01 23 add %sp, (%r11) 66 67 41 01 23 add %sp, (%r11d) 48 01 23 add %rsp, (%rbx) 67 48 01 23 add %rsp, (%ebx) 66 48 01 23 data16 add %rsp, (%rbx) 66 67 48 01 23 data16 add %rsp, (%ebx) 02 23 add (%rbx), %ah 66 02 23 data16 add (%rbx), %ah 67 02 23 add (%ebx), %ah 66 67 02 23 data16 add (%ebx), %ah 40 02 23 add (%rbx), %spl 67 40 02 23 add (%ebx), %spl 66 40 02 23 data16 add (%rbx), %spl 66 67 40 02 23 data16 add (%ebx), %spl 41 02 23 add (%r11), %spl 67 41 02 23 add (%r11d), %spl 66 41 02 23 data16 add (%r11), %spl 66 67 41 02 23 data16 add (%r11d), %spl 48 02 23 rex.W add (%rbx), %spl 67 48 02 23 rex.W add (%ebx), %spl 66 48 02 23 data16 rex.W add (%rbx), %spl 66 67 48 02 23 data16 rex.W add (%ebx), %spl 03 23 add (%rbx), %esp 66 03 23 add (%rbx), %sp 67 03 23 add (%ebx), %esp 66 67 03 23 add (%ebx), %sp 40 03 23 rex add (%rbx), %esp 67 40 03 23 rex add (%ebx), %esp 66 40 03 23 rex add (%rbx), %sp 66 67 40 03 23 rex add (%ebx), %sp 41 03 23 add (%r11), %esp 67 41 03 23 add (%r11d), %esp 66 41 03 23 add (%r11), %sp 66 67 41 03 23 add (%r11d), %sp 48 03 23 add (%rbx), %rsp 67 48 03 23 add (%ebx), %rsp 0c 12 or $0x12, %al 66 0d 12 34 or $0x3412, %ax 0d 12 34 56 78 or $0x78563412, %eax 41 0d 12 34 56 78 rex.B or $0x78563412, %eax 41 0d 12 34 56 88 rex.B or $0x88563412, %eax 48 0d 12 34 56 78 or $0x78563412, %rax 48 0d 12 34 56 88 or $0xffffffff88563412, %rax 49 0d 12 34 56 78 rex.WB or $0x78563412, %rax 49 0d 12 34 56 88 rex.WB or $0xffffffff88563412, %rax 80 c8 12 or $0x12, %al 80 ce 12 or $0x12, %dh 40 80 ce 12 or $0x12, %sil 66 81 ce 12 34 or $0x3412, %si 81 ce 12 34 56 78 or $0x78563412, %esi 48 81 ce 12 34 56 78 or $0x78563412, %rsi 48 81 ce 12 34 56 88 or $0xffffffff88563412, %rsi 66 83 ce 12 or $0x12, %si 66 83 ce 82 or $0xff82, %si 83 ce 12 or $0x12, %esi 83 ce 82 or $0xffffff82, %esi 41 83 ce 12 or $0x12, %r14d 41 83 ce 82 or $0xffffff82, %r14d 48 83 ce 12 or $0x12, %rsi 48 83 ce 82 or $0xffffffffffffff82, %rsi 49 83 ce 12 or $0x12, %r14 49 83 ce 82 or $0xffffffffffffff82, %r14 08 23 or %ah, (%rbx) 66 08 23 data16 or %ah, (%rbx) 67 08 23 or %ah, (%ebx) 66 67 08 23 data16 or %ah, (%ebx) 40 08 23 or %spl, (%rbx) 67 40 08 23 or %spl, (%ebx) 66 40 08 23 data16 or %spl, (%rbx) 66 67 40 08 23 data16 or %spl, (%ebx) 41 08 23 or %spl, (%r11) 67 41 08 23 or %spl, (%r11d) 66 41 08 23 data16 or %spl, (%r11) 66 67 41 08 23 data16 or %spl, (%r11d) 48 08 23 rex.W or %spl, (%rbx) 67 48 08 23 rex.W or %spl, (%ebx) 66 48 08 23 data16 rex.W or %spl, (%rbx) 66 67 48 08 23 data16 rex.W or %spl, (%ebx) 09 23 or %esp, (%rbx) 66 09 23 or %sp, (%rbx) 67 09 23 or %esp, (%ebx) 66 67 09 23 or %sp, (%ebx) 40 09 23 rex or %esp, (%rbx) 67 40 09 23 rex or %esp, (%ebx) 66 40 09 23 rex or %sp, (%rbx) 66 67 40 09 23 rex or %sp, (%ebx) 41 09 23 or %esp, (%r11) 67 41 09 23 or %esp, (%r11d) 66 41 09 23 or %sp, (%r11) 66 67 41 09 23 or %sp, (%r11d) 48 09 23 or %rsp, (%rbx) 67 48 09 23 or %rsp, (%ebx) 66 48 09 23 data16 or %rsp, (%rbx) 66 67 48 09 23 data16 or %rsp, (%ebx) 0a 23 or (%rbx), %ah 66 0a 23 data16 or (%rbx), %ah 67 0a 23 or (%ebx), %ah 66 67 0a 23 data16 or (%ebx), %ah 40 0a 23 or (%rbx), %spl 67 40 0a 23 or (%ebx), %spl 66 40 0a 23 data16 or (%rbx), %spl 66 67 40 0a 23 data16 or (%ebx), %spl 41 0a 23 or (%r11), %spl 67 41 0a 23 or (%r11d), %spl 66 41 0a 23 data16 or (%r11), %spl 66 67 41 0a 23 data16 or (%r11d), %spl 48 0a 23 rex.W or (%rbx), %spl 67 48 0a 23 rex.W or (%ebx), %spl 66 48 0a 23 data16 rex.W or (%rbx), %spl 66 67 48 0a 23 data16 rex.W or (%ebx), %spl 0b 23 or (%rbx), %esp 66 0b 23 or (%rbx), %sp 67 0b 23 or (%ebx), %esp 66 67 0b 23 or (%ebx), %sp 40 0b 23 rex or (%rbx), %esp 67 40 0b 23 rex or (%ebx), %esp 66 40 0b 23 rex or (%rbx), %sp 66 67 40 0b 23 rex or (%ebx), %sp 41 0b 23 or (%r11), %esp 67 41 0b 23 or (%r11d), %esp 66 41 0b 23 or (%r11), %sp 66 67 41 0b 23 or (%r11d), %sp 48 0b 23 or (%rbx), %rsp 67 48 0b 23 or (%ebx), %rsp 14 12 adc $0x12, %al 66 15 12 34 adc $0x3412, %ax 15 12 34 56 78 adc $0x78563412, %eax 41 15 12 34 56 78 rex.B adc $0x78563412, %eax 41 15 12 34 56 88 rex.B adc $0x88563412, %eax 48 15 12 34 56 78 adc $0x78563412, %rax 48 15 12 34 56 88 adc $0xffffffff88563412, %rax 49 15 12 34 56 78 rex.WB adc $0x78563412, %rax 49 15 12 34 56 88 rex.WB adc $0xffffffff88563412, %rax 80 d0 12 adc $0x12, %al 80 d6 12 adc $0x12, %dh 40 80 d6 12 adc $0x12, %sil 66 81 d6 12 34 adc $0x3412, %si 81 d6 12 34 56 78 adc $0x78563412, %esi 48 81 d6 12 34 56 78 adc $0x78563412, %rsi 48 81 d6 12 34 56 88 adc $0xffffffff88563412, %rsi 66 83 d6 12 adc $0x12, %si 66 83 d6 82 adc $0xff82, %si 83 d6 12 adc $0x12, %esi 83 d6 82 adc $0xffffff82, %esi 41 83 d6 12 adc $0x12, %r14d 41 83 d6 82 adc $0xffffff82, %r14d 48 83 d6 12 adc $0x12, %rsi 48 83 d6 82 adc $0xffffffffffffff82, %rsi 49 83 d6 12 adc $0x12, %r14 49 83 d6 82 adc $0xffffffffffffff82, %r14 10 23 adc %ah, (%rbx) 66 10 23 data16 adc %ah, (%rbx) 67 10 23 adc %ah, (%ebx) 66 67 10 23 data16 adc %ah, (%ebx) 40 10 23 adc %spl, (%rbx) 67 40 10 23 adc %spl, (%ebx) 66 40 10 23 data16 adc %spl, (%rbx) 66 67 40 10 23 data16 adc %spl, (%ebx) 41 10 23 adc %spl, (%r11) 67 41 10 23 adc %spl, (%r11d) 66 41 10 23 data16 adc %spl, (%r11) 66 67 41 10 23 data16 adc %spl, (%r11d) 48 10 23 rex.W adc %spl, (%rbx) 67 48 10 23 rex.W adc %spl, (%ebx) 66 48 10 23 data16 rex.W adc %spl, (%rbx) 66 67 48 10 23 data16 rex.W adc %spl, (%ebx) 11 23 adc %esp, (%rbx) 66 11 23 adc %sp, (%rbx) 67 11 23 adc %esp, (%ebx) 66 67 11 23 adc %sp, (%ebx) 40 11 23 rex adc %esp, (%rbx) 67 40 11 23 rex adc %esp, (%ebx) 66 40 11 23 rex adc %sp, (%rbx) 66 67 40 11 23 rex adc %sp, (%ebx) 41 11 23 adc %esp, (%r11) 67 41 11 23 adc %esp, (%r11d) 66 41 11 23 adc %sp, (%r11) 66 67 41 11 23 adc %sp, (%r11d) 48 11 23 adc %rsp, (%rbx) 67 48 11 23 adc %rsp, (%ebx) 66 48 11 23 data16 adc %rsp, (%rbx) 66 67 48 11 23 data16 adc %rsp, (%ebx) 12 23 adc (%rbx), %ah 66 12 23 data16 adc (%rbx), %ah 67 12 23 adc (%ebx), %ah 66 67 12 23 data16 adc (%ebx), %ah 40 12 23 adc (%rbx), %spl 67 40 12 23 adc (%ebx), %spl 66 40 12 23 data16 adc (%rbx), %spl 66 67 40 12 23 data16 adc (%ebx), %spl 41 12 23 adc (%r11), %spl 67 41 12 23 adc (%r11d), %spl 66 41 12 23 data16 adc (%r11), %spl 66 67 41 12 23 data16 adc (%r11d), %spl 48 12 23 rex.W adc (%rbx), %spl 67 48 12 23 rex.W adc (%ebx), %spl 66 48 12 23 data16 rex.W adc (%rbx), %spl 66 67 48 12 23 data16 rex.W adc (%ebx), %spl 13 23 adc (%rbx), %esp 66 13 23 adc (%rbx), %sp 67 13 23 adc (%ebx), %esp 66 67 13 23 adc (%ebx), %sp 40 13 23 rex adc (%rbx), %esp 67 40 13 23 rex adc (%ebx), %esp 66 40 13 23 rex adc (%rbx), %sp 66 67 40 13 23 rex adc (%ebx), %sp 41 13 23 adc (%r11), %esp 67 41 13 23 adc (%r11d), %esp 66 41 13 23 adc (%r11), %sp 66 67 41 13 23 adc (%r11d), %sp 48 13 23 adc (%rbx), %rsp 67 48 13 23 adc (%ebx), %rsp 1c 12 sbb $0x12, %al 66 1d 12 34 sbb $0x3412, %ax 1d 12 34 56 78 sbb $0x78563412, %eax 41 1d 12 34 56 78 rex.B sbb $0x78563412, %eax 41 1d 12 34 56 88 rex.B sbb $0x88563412, %eax 48 1d 12 34 56 78 sbb $0x78563412, %rax 48 1d 12 34 56 88 sbb $0xffffffff88563412, %rax 49 1d 12 34 56 78 rex.WB sbb $0x78563412, %rax 49 1d 12 34 56 88 rex.WB sbb $0xffffffff88563412, %rax 80 d8 12 sbb $0x12, %al 80 de 12 sbb $0x12, %dh 40 80 de 12 sbb $0x12, %sil 66 81 de 12 34 sbb $0x3412, %si 81 de 12 34 56 78 sbb $0x78563412, %esi 48 81 de 12 34 56 78 sbb $0x78563412, %rsi 48 81 de 12 34 56 88 sbb $0xffffffff88563412, %rsi 66 83 de 12 sbb $0x12, %si 66 83 de 82 sbb $0xff82, %si 83 de 12 sbb $0x12, %esi 83 de 82 sbb $0xffffff82, %esi 41 83 de 12 sbb $0x12, %r14d 41 83 de 82 sbb $0xffffff82, %r14d 48 83 de 12 sbb $0x12, %rsi 48 83 de 82 sbb $0xffffffffffffff82, %rsi 49 83 de 12 sbb $0x12, %r14 49 83 de 82 sbb $0xffffffffffffff82, %r14 18 23 sbb %ah, (%rbx) 66 18 23 data16 sbb %ah, (%rbx) 67 18 23 sbb %ah, (%ebx) 66 67 18 23 data16 sbb %ah, (%ebx) 40 18 23 sbb %spl, (%rbx) 67 40 18 23 sbb %spl, (%ebx) 66 40 18 23 data16 sbb %spl, (%rbx) 66 67 40 18 23 data16 sbb %spl, (%ebx) 41 18 23 sbb %spl, (%r11) 67 41 18 23 sbb %spl, (%r11d) 66 41 18 23 data16 sbb %spl, (%r11) 66 67 41 18 23 data16 sbb %spl, (%r11d) 48 18 23 rex.W sbb %spl, (%rbx) 67 48 18 23 rex.W sbb %spl, (%ebx) 66 48 18 23 data16 rex.W sbb %spl, (%rbx) 66 67 48 18 23 data16 rex.W sbb %spl, (%ebx) 19 23 sbb %esp, (%rbx) 66 19 23 sbb %sp, (%rbx) 67 19 23 sbb %esp, (%ebx) 66 67 19 23 sbb %sp, (%ebx) 40 19 23 rex sbb %esp, (%rbx) 67 40 19 23 rex sbb %esp, (%ebx) 66 40 19 23 rex sbb %sp, (%rbx) 66 67 40 19 23 rex sbb %sp, (%ebx) 41 19 23 sbb %esp, (%r11) 67 41 19 23 sbb %esp, (%r11d) 66 41 19 23 sbb %sp, (%r11) 66 67 41 19 23 sbb %sp, (%r11d) 48 19 23 sbb %rsp, (%rbx) 67 48 19 23 sbb %rsp, (%ebx) 66 48 19 23 data16 sbb %rsp, (%rbx) 66 67 48 19 23 data16 sbb %rsp, (%ebx) 1a 23 sbb (%rbx), %ah 66 1a 23 data16 sbb (%rbx), %ah 67 1a 23 sbb (%ebx), %ah 66 67 1a 23 data16 sbb (%ebx), %ah 40 1a 23 sbb (%rbx), %spl 67 40 1a 23 sbb (%ebx), %spl 66 40 1a 23 data16 sbb (%rbx), %spl 66 67 40 1a 23 data16 sbb (%ebx), %spl 41 1a 23 sbb (%r11), %spl 67 41 1a 23 sbb (%r11d), %spl 66 41 1a 23 data16 sbb (%r11), %spl 66 67 41 1a 23 data16 sbb (%r11d), %spl 48 1a 23 rex.W sbb (%rbx), %spl 67 48 1a 23 rex.W sbb (%ebx), %spl 66 48 1a 23 data16 rex.W sbb (%rbx), %spl 66 67 48 1a 23 data16 rex.W sbb (%ebx), %spl 1b 23 sbb (%rbx), %esp 66 1b 23 sbb (%rbx), %sp 67 1b 23 sbb (%ebx), %esp 66 67 1b 23 sbb (%ebx), %sp 40 1b 23 rex sbb (%rbx), %esp 67 40 1b 23 rex sbb (%ebx), %esp 66 40 1b 23 rex sbb (%rbx), %sp 66 67 40 1b 23 rex sbb (%ebx), %sp 41 1b 23 sbb (%r11), %esp 67 41 1b 23 sbb (%r11d), %esp 66 41 1b 23 sbb (%r11), %sp 66 67 41 1b 23 sbb (%r11d), %sp 48 1b 23 sbb (%rbx), %rsp 67 48 1b 23 sbb (%ebx), %rsp 24 12 and $0x12, %al 66 25 12 34 and $0x3412, %ax 25 12 34 56 78 and $0x78563412, %eax 41 25 12 34 56 78 rex.B and $0x78563412, %eax 41 25 12 34 56 88 rex.B and $0x88563412, %eax 48 25 12 34 56 78 and $0x78563412, %rax 48 25 12 34 56 88 and $0xffffffff88563412, %rax 49 25 12 34 56 78 rex.WB and $0x78563412, %rax 49 25 12 34 56 88 rex.WB and $0xffffffff88563412, %rax 80 e0 12 and $0x12, %al 80 e6 12 and $0x12, %dh 40 80 e6 12 and $0x12, %sil 66 81 e6 12 34 and $0x3412, %si 81 e6 12 34 56 78 and $0x78563412, %esi 48 81 e6 12 34 56 78 and $0x78563412, %rsi 48 81 e6 12 34 56 88 and $0xffffffff88563412, %rsi 66 83 e6 12 and $0x12, %si 66 83 e6 82 and $0xff82, %si 83 e6 12 and $0x12, %esi 83 e6 82 and $0xffffff82, %esi 41 83 e6 12 and $0x12, %r14d 41 83 e6 82 and $0xffffff82, %r14d 48 83 e6 12 and $0x12, %rsi 48 83 e6 82 and $0xffffffffffffff82, %rsi 49 83 e6 12 and $0x12, %r14 49 83 e6 82 and $0xffffffffffffff82, %r14 20 23 and %ah, (%rbx) 66 20 23 data16 and %ah, (%rbx) 67 20 23 and %ah, (%ebx) 66 67 20 23 data16 and %ah, (%ebx) 40 20 23 and %spl, (%rbx) 67 40 20 23 and %spl, (%ebx) 66 40 20 23 data16 and %spl, (%rbx) 66 67 40 20 23 data16 and %spl, (%ebx) 41 20 23 and %spl, (%r11) 67 41 20 23 and %spl, (%r11d) 66 41 20 23 data16 and %spl, (%r11) 66 67 41 20 23 data16 and %spl, (%r11d) 48 20 23 rex.W and %spl, (%rbx) 67 48 20 23 rex.W and %spl, (%ebx) 66 48 20 23 data16 rex.W and %spl, (%rbx) 66 67 48 20 23 data16 rex.W and %spl, (%ebx) 21 23 and %esp, (%rbx) 66 21 23 and %sp, (%rbx) 67 21 23 and %esp, (%ebx) 66 67 21 23 and %sp, (%ebx) 40 21 23 rex and %esp, (%rbx) 67 40 21 23 rex and %esp, (%ebx) 66 40 21 23 rex and %sp, (%rbx) 66 67 40 21 23 rex and %sp, (%ebx) 41 21 23 and %esp, (%r11) 67 41 21 23 and %esp, (%r11d) 66 41 21 23 and %sp, (%r11) 66 67 41 21 23 and %sp, (%r11d) 48 21 23 and %rsp, (%rbx) 67 48 21 23 and %rsp, (%ebx) 66 48 21 23 data16 and %rsp, (%rbx) 66 67 48 21 23 data16 and %rsp, (%ebx) 22 23 and (%rbx), %ah 66 22 23 data16 and (%rbx), %ah 67 22 23 and (%ebx), %ah 66 67 22 23 data16 and (%ebx), %ah 40 22 23 and (%rbx), %spl 67 40 22 23 and (%ebx), %spl 66 40 22 23 data16 and (%rbx), %spl 66 67 40 22 23 data16 and (%ebx), %spl 41 22 23 and (%r11), %spl 67 41 22 23 and (%r11d), %spl 66 41 22 23 data16 and (%r11), %spl 66 67 41 22 23 data16 and (%r11d), %spl 48 22 23 rex.W and (%rbx), %spl 67 48 22 23 rex.W and (%ebx), %spl 66 48 22 23 data16 rex.W and (%rbx), %spl 66 67 48 22 23 data16 rex.W and (%ebx), %spl 23 23 and (%rbx), %esp 66 23 23 and (%rbx), %sp 67 23 23 and (%ebx), %esp 66 67 23 23 and (%ebx), %sp 40 23 23 rex and (%rbx), %esp 67 40 23 23 rex and (%ebx), %esp 66 40 23 23 rex and (%rbx), %sp 66 67 40 23 23 rex and (%ebx), %sp 41 23 23 and (%r11), %esp 67 41 23 23 and (%r11d), %esp 66 41 23 23 and (%r11), %sp 66 67 41 23 23 and (%r11d), %sp 48 23 23 and (%rbx), %rsp 67 48 23 23 and (%ebx), %rsp 66 48 23 23 data16 and (%rbx), %rsp 66 67 48 23 23 data16 and (%ebx), %rsp 2c 12 sub $0x12, %al 66 2d 12 34 sub $0x3412, %ax 2d 12 34 56 78 sub $0x78563412, %eax 41 2d 12 34 56 78 rex.B sub $0x78563412, %eax 41 2d 12 34 56 88 rex.B sub $0x88563412, %eax 48 2d 12 34 56 78 sub $0x78563412, %rax 48 2d 12 34 56 88 sub $0xffffffff88563412, %rax 49 2d 12 34 56 78 rex.WB sub $0x78563412, %rax 49 2d 12 34 56 88 rex.WB sub $0xffffffff88563412, %rax 80 e8 12 sub $0x12, %al 80 ee 12 sub $0x12, %dh 40 80 ee 12 sub $0x12, %sil 66 81 ee 12 34 sub $0x3412, %si 81 ee 12 34 56 78 sub $0x78563412, %esi 48 81 ee 12 34 56 78 sub $0x78563412, %rsi 48 81 ee 12 34 56 88 sub $0xffffffff88563412, %rsi 66 83 ee 12 sub $0x12, %si 66 83 ee 82 sub $0xff82, %si 83 ee 12 sub $0x12, %esi 83 ee 82 sub $0xffffff82, %esi 41 83 ee 12 sub $0x12, %r14d 41 83 ee 82 sub $0xffffff82, %r14d 48 83 ee 12 sub $0x12, %rsi 48 83 ee 82 sub $0xffffffffffffff82, %rsi 49 83 ee 12 sub $0x12, %r14 49 83 ee 82 sub $0xffffffffffffff82, %r14 28 23 sub %ah, (%rbx) 66 28 23 data16 sub %ah, (%rbx) 67 28 23 sub %ah, (%ebx) 66 67 28 23 data16 sub %ah, (%ebx) 40 28 23 sub %spl, (%rbx) 67 40 28 23 sub %spl, (%ebx) 66 40 28 23 data16 sub %spl, (%rbx) 66 67 40 28 23 data16 sub %spl, (%ebx) 41 28 23 sub %spl, (%r11) 67 41 28 23 sub %spl, (%r11d) 66 41 28 23 data16 sub %spl, (%r11) 66 67 41 28 23 data16 sub %spl, (%r11d) 48 28 23 rex.W sub %spl, (%rbx) 67 48 28 23 rex.W sub %spl, (%ebx) 66 48 28 23 data16 rex.W sub %spl, (%rbx) 66 67 48 28 23 data16 rex.W sub %spl, (%ebx) 29 23 sub %esp, (%rbx) 66 29 23 sub %sp, (%rbx) 67 29 23 sub %esp, (%ebx) 66 67 29 23 sub %sp, (%ebx) 40 29 23 rex sub %esp, (%rbx) 67 40 29 23 rex sub %esp, (%ebx) 66 40 29 23 rex sub %sp, (%rbx) 66 67 40 29 23 rex sub %sp, (%ebx) 41 29 23 sub %esp, (%r11) 67 41 29 23 sub %esp, (%r11d) 66 41 29 23 sub %sp, (%r11) 66 67 41 29 23 sub %sp, (%r11d) 48 29 23 sub %rsp, (%rbx) 67 48 29 23 sub %rsp, (%ebx) 66 48 29 23 data16 sub %rsp, (%rbx) 66 67 48 29 23 data16 sub %rsp, (%ebx) 2a 23 sub (%rbx), %ah 66 2a 23 data16 sub (%rbx), %ah 67 2a 23 sub (%ebx), %ah 66 67 2a 23 data16 sub (%ebx), %ah 40 2a 23 sub (%rbx), %spl 67 40 2a 23 sub (%ebx), %spl 66 40 2a 23 data16 sub (%rbx), %spl 66 67 40 2a 23 data16 sub (%ebx), %spl 41 2a 23 sub (%r11), %spl 67 41 2a 23 sub (%r11d), %spl 66 41 2a 23 data16 sub (%r11), %spl 66 67 41 2a 23 data16 sub (%r11d), %spl 48 2a 23 rex.W sub (%rbx), %spl 67 48 2a 23 rex.W sub (%ebx), %spl 66 48 2a 23 data16 rex.W sub (%rbx), %spl 66 67 48 2a 23 data16 rex.W sub (%ebx), %spl 2b 23 sub (%rbx), %esp 66 2b 23 sub (%rbx), %sp 67 2b 23 sub (%ebx), %esp 66 67 2b 23 sub (%ebx), %sp 40 2b 23 rex sub (%rbx), %esp 67 40 2b 23 rex sub (%ebx), %esp 66 40 2b 23 rex sub (%rbx), %sp 66 67 40 2b 23 rex sub (%ebx), %sp 41 2b 23 sub (%r11), %esp 67 41 2b 23 sub (%r11d), %esp 66 41 2b 23 sub (%r11), %sp 66 67 41 2b 23 sub (%r11d), %sp 48 2b 23 sub (%rbx), %rsp 67 48 2b 23 sub (%ebx), %rsp 66 48 2b 23 data16 sub (%rbx), %rsp 66 67 48 2b 23 data16 sub (%ebx), %rsp 3c 12 cmp $0x12, %al 66 3d 12 34 cmp $0x3412, %ax 3d 12 34 56 78 cmp $0x78563412, %eax 41 3d 12 34 56 78 rex.B cmp $0x78563412, %eax 41 3d 12 34 56 88 rex.B cmp $0x88563412, %eax 48 3d 12 34 56 78 cmp $0x78563412, %rax 48 3d 12 34 56 88 cmp $0xffffffff88563412, %rax 49 3d 12 34 56 78 rex.WB cmp $0x78563412, %rax 49 3d 12 34 56 88 rex.WB cmp $0xffffffff88563412, %rax 80 f8 12 cmp $0x12, %al 80 fe 12 cmp $0x12, %dh 40 80 fe 12 cmp $0x12, %sil 66 81 fe 12 34 cmp $0x3412, %si 81 fe 12 34 56 78 cmp $0x78563412, %esi 48 81 fe 12 34 56 78 cmp $0x78563412, %rsi 48 81 fe 12 34 56 88 cmp $0xffffffff88563412, %rsi 66 83 fe 12 cmp $0x12, %si 66 83 fe 82 cmp $0xff82, %si 83 fe 12 cmp $0x12, %esi 83 fe 82 cmp $0xffffff82, %esi 41 83 fe 12 cmp $0x12, %r14d 41 83 fe 82 cmp $0xffffff82, %r14d 48 83 fe 12 cmp $0x12, %rsi 48 83 fe 82 cmp $0xffffffffffffff82, %rsi 49 83 fe 12 cmp $0x12, %r14 49 83 fe 82 cmp $0xffffffffffffff82, %r14 38 23 cmp %ah, (%rbx) 66 38 23 data16 cmp %ah, (%rbx) 67 38 23 cmp %ah, (%ebx) 66 67 38 23 data16 cmp %ah, (%ebx) 40 38 23 cmp %spl, (%rbx) 67 40 38 23 cmp %spl, (%ebx) 66 40 38 23 data16 cmp %spl, (%rbx) 66 67 40 38 23 data16 cmp %spl, (%ebx) 41 38 23 cmp %spl, (%r11) 67 41 38 23 cmp %spl, (%r11d) 66 41 38 23 data16 cmp %spl, (%r11) 66 67 41 38 23 data16 cmp %spl, (%r11d) 48 38 23 rex.W cmp %spl, (%rbx) 67 48 38 23 rex.W cmp %spl, (%ebx) 66 48 38 23 data16 rex.W cmp %spl, (%rbx) 66 67 48 38 23 data16 rex.W cmp %spl, (%ebx) 39 23 cmp %esp, (%rbx) 66 39 23 cmp %sp, (%rbx) 67 39 23 cmp %esp, (%ebx) 66 67 39 23 cmp %sp, (%ebx) 40 39 23 rex cmp %esp, (%rbx) 67 40 39 23 rex cmp %esp, (%ebx) 66 40 39 23 rex cmp %sp, (%rbx) 66 67 40 39 23 rex cmp %sp, (%ebx) 41 39 23 cmp %esp, (%r11) 67 41 39 23 cmp %esp, (%r11d) 66 41 39 23 cmp %sp, (%r11) 66 67 41 39 23 cmp %sp, (%r11d) 48 39 23 cmp %rsp, (%rbx) 67 48 39 23 cmp %rsp, (%ebx) 66 48 39 23 data16 cmp %rsp, (%rbx) 66 67 48 39 23 data16 cmp %rsp, (%ebx) 3a 23 cmp (%rbx), %ah 66 3a 23 data16 cmp (%rbx), %ah 67 3a 23 cmp (%ebx), %ah 66 67 3a 23 data16 cmp (%ebx), %ah 40 3a 23 cmp (%rbx), %spl 67 40 3a 23 cmp (%ebx), %spl 66 40 3a 23 data16 cmp (%rbx), %spl 66 67 40 3a 23 data16 cmp (%ebx), %spl 41 3a 23 cmp (%r11), %spl 67 41 3a 23 cmp (%r11d), %spl 66 41 3a 23 data16 cmp (%r11), %spl 66 67 41 3a 23 data16 cmp (%r11d), %spl 48 3a 23 rex.W cmp (%rbx), %spl 67 48 3a 23 rex.W cmp (%ebx), %spl 66 48 3a 23 data16 rex.W cmp (%rbx), %spl 66 67 48 3a 23 data16 rex.W cmp (%ebx), %spl 3b 23 cmp (%rbx), %esp 66 3b 23 cmp (%rbx), %sp 67 3b 23 cmp (%ebx), %esp 66 67 3b 23 cmp (%ebx), %sp 40 3b 23 rex cmp (%rbx), %esp 67 40 3b 23 rex cmp (%ebx), %esp 66 40 3b 23 rex cmp (%rbx), %sp 66 67 40 3b 23 rex cmp (%ebx), %sp 41 3b 23 cmp (%r11), %esp 67 41 3b 23 cmp (%r11d), %esp 66 41 3b 23 cmp (%r11), %sp 66 67 41 3b 23 cmp (%r11d), %sp 48 3b 23 cmp (%rbx), %rsp 67 48 3b 23 cmp (%ebx), %rsp 66 48 3b 23 data16 cmp (%rbx), %rsp 66 67 48 3b 23 data16 cmp (%ebx), %rsp 34 12 xor $0x12, %al 66 35 12 34 xor $0x3412, %ax 35 12 34 56 78 xor $0x78563412, %eax 41 35 12 34 56 78 rex.B xor $0x78563412, %eax 41 35 12 34 56 88 rex.B xor $0x88563412, %eax 48 35 12 34 56 78 xor $0x78563412, %rax 48 35 12 34 56 88 xor $0xffffffff88563412, %rax 49 35 12 34 56 78 rex.WB xor $0x78563412, %rax 49 35 12 34 56 88 rex.WB xor $0xffffffff88563412, %rax 80 f0 12 xor $0x12, %al 80 f6 12 xor $0x12, %dh 40 80 f6 12 xor $0x12, %sil 66 81 f6 12 34 xor $0x3412, %si 81 f6 12 34 56 78 xor $0x78563412, %esi 48 81 f6 12 34 56 78 xor $0x78563412, %rsi 48 81 f6 12 34 56 88 xor $0xffffffff88563412, %rsi 66 83 f6 12 xor $0x12, %si 66 83 f6 82 xor $0xff82, %si 83 f6 12 xor $0x12, %esi 83 f6 82 xor $0xffffff82, %esi 41 83 f6 12 xor $0x12, %r14d 41 83 f6 82 xor $0xffffff82, %r14d 48 83 f6 12 xor $0x12, %rsi 48 83 f6 82 xor $0xffffffffffffff82, %rsi 49 83 f6 12 xor $0x12, %r14 49 83 f6 82 xor $0xffffffffffffff82, %r14 30 23 xor %ah, (%rbx) 66 30 23 data16 xor %ah, (%rbx) 67 30 23 xor %ah, (%ebx) 66 67 30 23 data16 xor %ah, (%ebx) 40 30 23 xor %spl, (%rbx) 67 40 30 23 xor %spl, (%ebx) 66 40 30 23 data16 xor %spl, (%rbx) 66 67 40 30 23 data16 xor %spl, (%ebx) 41 30 23 xor %spl, (%r11) 67 41 30 23 xor %spl, (%r11d) 66 41 30 23 data16 xor %spl, (%r11) 66 67 41 30 23 data16 xor %spl, (%r11d) 48 30 23 rex.W xor %spl, (%rbx) 67 48 30 23 rex.W xor %spl, (%ebx) 66 48 30 23 data16 rex.W xor %spl, (%rbx) 66 67 48 30 23 data16 rex.W xor %spl, (%ebx) 31 23 xor %esp, (%rbx) 66 31 23 xor %sp, (%rbx) 67 31 23 xor %esp, (%ebx) 66 67 31 23 xor %sp, (%ebx) 40 31 23 rex xor %esp, (%rbx) 67 40 31 23 rex xor %esp, (%ebx) 66 40 31 23 rex xor %sp, (%rbx) 66 67 40 31 23 rex xor %sp, (%ebx) 41 31 23 xor %esp, (%r11) 67 41 31 23 xor %esp, (%r11d) 66 41 31 23 xor %sp, (%r11) 66 67 41 31 23 xor %sp, (%r11d) 48 31 23 xor %rsp, (%rbx) 67 48 31 23 xor %rsp, (%ebx) 66 48 31 23 data16 xor %rsp, (%rbx) 66 67 48 31 23 data16 xor %rsp, (%ebx) 32 23 xor (%rbx), %ah 66 32 23 data16 xor (%rbx), %ah 67 32 23 xor (%ebx), %ah 66 67 32 23 data16 xor (%ebx), %ah 40 32 23 xor (%rbx), %spl 67 40 32 23 xor (%ebx), %spl 66 40 32 23 data16 xor (%rbx), %spl 66 67 40 32 23 data16 xor (%ebx), %spl 41 32 23 xor (%r11), %spl 67 41 32 23 xor (%r11d), %spl 66 41 32 23 data16 xor (%r11), %spl 66 67 41 32 23 data16 xor (%r11d), %spl 48 32 23 rex.W xor (%rbx), %spl 67 48 32 23 rex.W xor (%ebx), %spl 66 48 32 23 data16 rex.W xor (%rbx), %spl 66 67 48 32 23 data16 rex.W xor (%ebx), %spl 33 23 xor (%rbx), %esp 66 33 23 xor (%rbx), %sp 67 33 23 xor (%ebx), %esp 66 67 33 23 xor (%ebx), %sp 40 33 23 rex xor (%rbx), %esp 67 40 33 23 rex xor (%ebx), %esp 66 40 33 23 rex xor (%rbx), %sp 66 67 40 33 23 rex xor (%ebx), %sp 41 33 23 xor (%r11), %esp 67 41 33 23 xor (%r11d), %esp 66 41 33 23 xor (%r11), %sp 66 67 41 33 23 xor (%r11d), %sp 48 33 23 xor (%rbx), %rsp 67 48 33 23 xor (%ebx), %rsp 66 48 33 23 data16 xor (%rbx), %rsp 66 67 48 33 23 data16 xor (%ebx), %rsp 66 0f ba e6 12 bt $0x12, %si 66 0f ba e6 82 bt $0x82, %si 0f ba e6 12 bt $0x12, %esi 0f ba e6 82 bt $0x82, %esi 41 0f ba e6 12 bt $0x12, %r14d 41 0f ba e6 82 bt $0x82, %r14d 48 0f ba e6 12 bt $0x12, %rsi 48 0f ba e6 82 bt $0x82, %rsi 49 0f ba e6 12 bt $0x12, %r14 49 0f ba e6 82 bt $0x82, %r14 0f ba 23 12 btl $0x12, (%rbx) 0f ba 23 82 btl $0x82, (%rbx) 66 0f ba 23 12 btw $0x12, (%rbx) 66 0f ba 23 82 btw $0x82, (%rbx) 67 0f ba 23 12 btl $0x12, (%ebx) 67 0f ba 23 82 btl $0x82, (%ebx) 66 67 0f ba 23 12 btw $0x12, (%ebx) 66 67 0f ba 23 82 btw $0x82, (%ebx) 49 0f ba 23 12 btq $0x12, (%r11) 49 0f ba 23 82 btq $0x82, (%r11) 66 49 0f ba 23 12 data16 btq $0x12, (%r11) 66 49 0f ba 23 82 data16 btq $0x82, (%r11) 67 49 0f ba 23 12 btq $0x12, (%r11d) 67 49 0f ba 23 82 btq $0x82, (%r11d) 66 67 49 0f ba 23 12 data16 btq $0x12, (%r11d) 66 67 49 0f ba 23 82 data16 btq $0x82, (%r11d) 0f a3 e6 bt %esp, %esi 41 0f a3 e6 bt %esp, %r14d 49 0f a3 e6 bt %rsp, %r14 66 0f a3 e6 bt %sp, %si 0f a3 23 bt %esp, (%rbx) 66 0f a3 23 bt %sp, (%rbx) 67 0f a3 23 bt %esp, (%ebx) 66 67 0f a3 23 bt %sp, (%ebx) 40 0f a3 23 rex bt %esp, (%rbx) 67 40 0f a3 23 rex bt %esp, (%ebx) 66 40 0f a3 23 rex bt %sp, (%rbx) 66 67 40 0f a3 23 rex bt %sp, (%ebx) 41 0f a3 23 bt %esp, (%r11) 67 41 0f a3 23 bt %esp, (%r11d) 66 41 0f a3 23 bt %sp, (%r11) 66 67 41 0f a3 23 bt %sp, (%r11d) 48 0f a3 23 bt %rsp, (%rbx) 67 48 0f a3 23 bt %rsp, (%ebx) 66 48 0f a3 23 data16 bt %rsp, (%rbx) 66 67 48 0f a3 23 data16 bt %rsp, (%ebx)

jared-hughes/defcpu

1,118

tests/disassembly/sources/001_mov8.s

b0 11 mov $0x11, %al b1 12 mov $0x12, %cl b2 13 mov $0x13, %dl b3 14 mov $0x14, %bl b4 21 mov $0x21, %ah b5 22 mov $0x22, %ch b6 23 mov $0x23, %dh b7 24 mov $0x24, %bh 40 b6 31 mov $0x31, %sil 40 b7 32 mov $0x32, %dil 40 b4 33 mov $0x33, %spl 40 b5 34 mov $0x34, %bpl 41 b0 41 mov $0x41, %r8b 41 b1 42 mov $0x42, %r9b 41 b2 43 mov $0x43, %r10b 41 b3 44 mov $0x44, %r11b 41 b4 45 mov $0x45, %r12b 41 b5 46 mov $0x46, %r13b 41 b6 47 mov $0x47, %r14b 41 b7 48 mov $0x48, %r15b 42 b6 52 rex.X mov $0x52, %sil 43 b6 53 rex.XB mov $0x53, %r14b 44 b6 54 rex.R mov $0x54, %sil 45 b6 55 rex.RB mov $0x55, %r14b 46 b6 56 rex.RX mov $0x56, %sil 47 b6 57 rex.RXB mov $0x57, %r14b 48 b6 58 rex.W mov $0x58, %sil 49 b6 59 rex.WB mov $0x59, %r14b 4a b6 5a rex.WX mov $0x5a, %sil 4b b6 5b rex.WXB mov $0x5b, %r14b 4c b6 5c rex.WR mov $0x5c, %sil 4d b6 5d rex.WRB mov $0x5d, %r14b 4e b6 5e rex.WRX mov $0x5e, %sil 4f b6 5f rex.WRXB mov $0x5f, %r14b

jared-hughes/defcpu

2,093

tests/disassembly/sources/002_mov16.s

66 b8 ef be mov $0xbeef, %ax 66 b8 12 34 mov $0x3412, %ax 66 b9 12 34 mov $0x3412, %cx 66 ba 12 34 mov $0x3412, %dx 66 bb 12 34 mov $0x3412, %bx 66 bc 12 34 mov $0x3412, %sp 66 bd 12 34 mov $0x3412, %bp 66 be 12 34 mov $0x3412, %si 66 bf 12 34 mov $0x3412, %di 66 41 b8 12 34 mov $0x3412, %r8w 66 41 b9 12 34 mov $0x3412, %r9w 66 41 ba 12 34 mov $0x3412, %r10w 66 41 bb 12 34 mov $0x3412, %r11w 66 41 bc 12 34 mov $0x3412, %r12w 66 41 bd 12 34 mov $0x3412, %r13w 66 41 be 12 34 mov $0x3412, %r14w 66 41 bf 12 34 mov $0x3412, %r15w 66 40 b8 12 34 rex mov $0x3412, %ax 66 41 b8 12 34 mov $0x3412, %r8w 66 42 b8 12 34 rex.X mov $0x3412, %ax 66 43 b8 12 34 rex.XB mov $0x3412, %r8w 66 44 b8 12 34 rex.R mov $0x3412, %ax 66 45 b8 12 34 rex.RB mov $0x3412, %r8w 66 46 b8 12 34 rex.RX mov $0x3412, %ax 66 47 b8 12 34 rex.RXB mov $0x3412, %r8w 66 48 b8 12 34 56 78 9a bc de ff data16 movabs $0xffdebc9a78563412, %rax 66 49 b8 12 34 56 78 9a bc de ff data16 movabs $0xffdebc9a78563412, %r8 66 4a b8 12 34 56 78 9a bc de ff data16 rex.WX movabs $0xffdebc9a78563412, %rax 66 4b b8 12 34 56 78 9a bc de ff data16 rex.WXB movabs $0xffdebc9a78563412, %r8 66 4c b8 12 34 56 78 9a bc de ff data16 rex.WR movabs $0xffdebc9a78563412, %rax 66 4d b8 12 34 56 78 9a bc de ff data16 rex.WRB movabs $0xffdebc9a78563412, %r8 66 4e b8 12 34 56 78 9a bc de ff data16 rex.WRX movabs $0xffdebc9a78563412, %rax 66 4f b8 12 34 56 78 9a bc de ff data16 rex.WRXB movabs $0xffdebc9a78563412, %r8

jared-hughes/defcpu

5,614

tests/disassembly/sources/006_movmem.s

88 23 mov %ah, (%rbx) 66 88 23 data16 mov %ah, (%rbx) 67 88 23 mov %ah, (%ebx) 66 67 88 23 data16 mov %ah, (%ebx) 40 88 23 mov %spl, (%rbx) 67 40 88 23 mov %spl, (%ebx) 66 40 88 23 data16 mov %spl, (%rbx) 66 67 40 88 23 data16 mov %spl, (%ebx) 41 88 23 mov %spl, (%r11) 67 41 88 23 mov %spl, (%r11d) 66 41 88 23 data16 mov %spl, (%r11) 66 67 41 88 23 data16 mov %spl, (%r11d) 48 88 23 rex.W mov %spl, (%rbx) 67 48 88 23 rex.W mov %spl, (%ebx) 66 48 88 23 data16 rex.W mov %spl, (%rbx) 66 67 48 88 23 data16 rex.W mov %spl, (%ebx) 49 88 23 rex.WB mov %spl, (%r11) 67 49 88 23 rex.WB mov %spl, (%r11d) 66 49 88 23 data16 rex.WB mov %spl, (%r11) 66 67 49 88 23 data16 rex.WB mov %spl, (%r11d) 88 c0 mov %al, %al 88 c1 mov %al, %cl 88 c2 mov %al, %dl 88 c3 mov %al, %bl 88 c4 mov %al, %ah 88 c5 mov %al, %ch 88 c6 mov %al, %dh 88 c7 mov %al, %bh 66 88 c1 data16 mov %al, %cl 67 88 c1 addr32 mov %al, %cl 66 67 88 c1 data16 addr32 mov %al, %cl 40 88 c1 rex mov %al, %cl 67 40 88 c1 addr32 rex mov %al, %cl 66 40 88 c1 data16 rex mov %al, %cl 66 67 40 88 c1 data16 addr32 rex mov %al, %cl 41 88 c1 mov %al, %r9b 67 41 88 c1 addr32 mov %al, %r9b 66 41 88 c1 data16 mov %al, %r9b 66 67 41 88 c1 data16 addr32 mov %al, %r9b 48 88 c1 rex.W mov %al, %cl 67 48 88 c1 addr32 rex.W mov %al, %cl 66 48 88 c1 data16 rex.W mov %al, %cl 66 67 48 88 c1 data16 addr32 rex.W mov %al, %cl 49 88 c1 rex.WB mov %al, %r9b 67 49 88 c1 addr32 rex.WB mov %al, %r9b 66 49 88 c1 data16 rex.WB mov %al, %r9b 66 67 49 88 c1 data16 addr32 rex.WB mov %al, %r9b 8a 23 mov (%rbx), %ah 66 8a 23 data16 mov (%rbx), %ah 67 8a 23 mov (%ebx), %ah 66 67 8a 23 data16 mov (%ebx), %ah 40 8a 23 mov (%rbx), %spl 67 40 8a 23 mov (%ebx), %spl 66 40 8a 23 data16 mov (%rbx), %spl 66 67 40 8a 23 data16 mov (%ebx), %spl 41 8a 23 mov (%r11), %spl 67 41 8a 23 mov (%r11d), %spl 66 41 8a 23 data16 mov (%r11), %spl 66 67 41 8a 23 data16 mov (%r11d), %spl 48 8a 23 rex.W mov (%rbx), %spl 67 48 8a 23 rex.W mov (%ebx), %spl 66 48 8a 23 data16 rex.W mov (%rbx), %spl 66 67 48 8a 23 data16 rex.W mov (%ebx), %spl 49 8a 23 rex.WB mov (%r11), %spl 67 49 8a 23 rex.WB mov (%r11d), %spl 66 49 8a 23 data16 rex.WB mov (%r11), %spl 66 67 49 8a 23 data16 rex.WB mov (%r11d), %spl 89 23 mov %esp, (%rbx) 66 89 23 mov %sp, (%rbx) 67 89 23 mov %esp, (%ebx) 66 67 89 23 mov %sp, (%ebx) 40 89 23 rex mov %esp, (%rbx) 67 40 89 23 rex mov %esp, (%ebx) 66 40 89 23 rex mov %sp, (%rbx) 66 67 40 89 23 rex mov %sp, (%ebx) 41 89 23 mov %esp, (%r11) 67 41 89 23 mov %esp, (%r11d) 66 41 89 23 mov %sp, (%r11) 66 67 41 89 23 mov %sp, (%r11d) 48 89 23 mov %rsp, (%rbx) 67 48 89 23 mov %rsp, (%ebx) 66 48 89 23 data16 mov %rsp, (%rbx) 66 67 48 89 23 data16 mov %rsp, (%ebx) 49 89 23 mov %rsp, (%r11) 67 49 89 23 mov %rsp, (%r11d) 66 49 89 23 data16 mov %rsp, (%r11) 66 67 49 89 23 data16 mov %rsp, (%r11d) 89 c0 mov %eax, %eax 89 c1 mov %eax, %ecx 89 c2 mov %eax, %edx 89 c3 mov %eax, %ebx 89 c4 mov %eax, %esp 89 c5 mov %eax, %ebp 89 c6 mov %eax, %esi 89 c7 mov %eax, %edi 66 89 c1 mov %ax, %cx 67 89 c1 addr32 mov %eax, %ecx 66 67 89 c1 addr32 mov %ax, %cx 40 89 c1 rex mov %eax, %ecx 67 40 89 c1 addr32 rex mov %eax, %ecx 66 40 89 c1 rex mov %ax, %cx 66 67 40 89 c1 addr32 rex mov %ax, %cx 41 89 c1 mov %eax, %r9d 67 41 89 c1 addr32 mov %eax, %r9d 66 41 89 c1 mov %ax, %r9w 66 67 41 89 c1 addr32 mov %ax, %r9w 48 89 c1 mov %rax, %rcx 67 48 89 c1 addr32 mov %rax, %rcx 66 48 89 c1 data16 mov %rax, %rcx 66 67 48 89 c1 data16 addr32 mov %rax, %rcx 49 89 c1 mov %rax, %r9 67 49 89 c1 addr32 mov %rax, %r9 66 49 89 c1 data16 mov %rax, %r9 66 67 49 89 c1 data16 addr32 mov %rax, %r9 8b 23 mov (%rbx), %esp 66 8b 23 mov (%rbx), %sp 67 8b 23 mov (%ebx), %esp 66 67 8b 23 mov (%ebx), %sp 40 8b 23 rex mov (%rbx), %esp 67 40 8b 23 rex mov (%ebx), %esp 66 40 8b 23 rex mov (%rbx), %sp 66 67 40 8b 23 rex mov (%ebx), %sp 41 8b 23 mov (%r11), %esp 67 41 8b 23 mov (%r11d), %esp 66 41 8b 23 mov (%r11), %sp 66 67 41 8b 23 mov (%r11d), %sp 48 8b 23 mov (%rbx), %rsp 67 48 8b 23 mov (%ebx), %rsp 66 48 8b 23 data16 mov (%rbx), %rsp 66 67 48 8b 23 data16 mov (%ebx), %rsp 49 8b 23 mov (%r11), %rsp 67 49 8b 23 mov (%r11d), %rsp 66 49 8b 23 data16 mov (%r11), %rsp 66 67 49 8b 23 data16 mov (%r11d), %rsp

jared-hughes/defcpu

286

tests/disassembly/sources/024_cltq_cbw.s

98 cwtl 99 cltd 66 98 cbtw 66 99 cwtd 67 98 addr32 cwtl 67 99 addr32 cltd 40 98 rex cwtl 40 99 rex cltd 41 98 rex.B cwtl 41 99 rex.B cltd 48 98 cltq 48 99 cqto 49 98 rex.WB cltq 49 99 rex.WB cqto

jared-hughes/defcpu

10,317

tests/disassembly/sources/009_sidb.s

8a 0c 18 mov (%rax, %rbx, 1), %cl 8a 0c 58 mov (%rax, %rbx, 2), %cl 8a 0c 98 mov (%rax, %rbx, 4), %cl 8a 0c d8 mov (%rax, %rbx, 8), %cl 67 8a 0c 18 mov (%eax, %ebx, 1), %cl 67 8a 0c 58 mov (%eax, %ebx, 2), %cl 67 8a 0c 98 mov (%eax, %ebx, 4), %cl 67 8a 0c d8 mov (%eax, %ebx, 8), %cl 43 8a 0c 23 mov (%r11, %r12, 1), %cl 43 8a 0c 63 mov (%r11, %r12, 2), %cl 43 8a 0c a3 mov (%r11, %r12, 4), %cl 43 8a 0c e3 mov (%r11, %r12, 8), %cl 67 43 8a 0c 23 mov (%r11d, %r12d, 1), %cl 67 43 8a 0c 63 mov (%r11d, %r12d, 2), %cl 67 43 8a 0c a3 mov (%r11d, %r12d, 4), %cl 67 43 8a 0c e3 mov (%r11d, %r12d, 8), %cl 8a 4c 18 79 mov 0x79(%rax, %rbx, 1), %cl 8a 4c 58 80 mov -0x80(%rax, %rbx, 2), %cl 8a 8c 98 80 00 00 00 mov 0x80(%rax, %rbx, 4), %cl 8a 8c d8 7f ff ff ff mov -0x81(%rax, %rbx, 8), %cl 8a 0c 1c mov (%rsp, %rbx, 1), %cl 8a 35 12 34 56 78 mov 0x78563412(%rip), %dh 67 8a 35 12 34 56 78 mov 0x78563412(%eip), %dh 8a 04 20 mov (%rax, %riz, 1), %al 8a 84 20 12 34 56 78 mov 0x78563412(%rax, %riz, 1), %al 8a 04 20 mov (%rax, %riz, 1), %al 8a 0c 20 mov (%rax, %riz, 1), %cl 8a 14 20 mov (%rax, %riz, 1), %dl 8a 1c 20 mov (%rax, %riz, 1), %bl 8a 24 20 mov (%rax, %riz, 1), %ah 8a 2c 20 mov (%rax, %riz, 1), %ch 8a 34 20 mov (%rax, %riz, 1), %dh 8a 3c 20 mov (%rax, %riz, 1), %bh 8a 04 21 mov (%rcx, %riz, 1), %al 8a 04 22 mov (%rdx, %riz, 1), %al 8a 04 23 mov (%rbx, %riz, 1), %al 8a 04 24 mov (%rsp), %al 8a 04 25 12 34 56 78 mov 0x78563412, %al 8a 04 65 12 34 56 78 mov 0x78563412(, %riz, 2), %al 8a 04 a5 12 34 56 78 mov 0x78563412(, %riz, 4), %al 8a 04 e5 12 34 56 78 mov 0x78563412(, %riz, 8), %al 8a 04 26 mov (%rsi, %riz, 1), %al 8a 04 27 mov (%rdi, %riz, 1), %al 8a 04 64 mov (%rsp, %riz, 2), %al 8a 04 a4 mov (%rsp, %riz, 4), %al 8a 04 e4 mov (%rsp, %riz, 8), %al 8a 04 ac mov (%rsp, %rbp, 4), %al 8a 44 20 3a mov 0x3a(%rax, %riz, 1), %al 8a 4c 20 3a mov 0x3a(%rax, %riz, 1), %cl 8a 54 20 3a mov 0x3a(%rax, %riz, 1), %dl 8a 5c 20 3a mov 0x3a(%rax, %riz, 1), %bl 8a 64 20 3a mov 0x3a(%rax, %riz, 1), %ah 8a 6c 20 3a mov 0x3a(%rax, %riz, 1), %ch 8a 74 20 3a mov 0x3a(%rax, %riz, 1), %dh 8a 7c 20 3a mov 0x3a(%rax, %riz, 1), %bh 8a 44 24 3a mov 0x3a(%rsp), %al 8a 44 64 3a mov 0x3a(%rsp, %riz, 2), %al 8a 44 a4 3a mov 0x3a(%rsp, %riz, 4), %al 8a 44 e4 3a mov 0x3a(%rsp, %riz, 8), %al 8a 44 25 3a mov 0x3a(%rbp, %riz, 1), %al 8a 44 65 3a mov 0x3a(%rbp, %riz, 2), %al 8a 44 a5 3a mov 0x3a(%rbp, %riz, 4), %al 8a 44 e5 3a mov 0x3a(%rbp, %riz, 8), %al 66 8a 4c 18 79 data16 mov 0x79(%rax, %rbx, 1), %cl 66 8a 4c 58 80 data16 mov -0x80(%rax, %rbx, 2), %cl 66 8a 8c 98 80 00 00 00 data16 mov 0x80(%rax, %rbx, 4), %cl 66 8a 8c d8 7f ff ff ff data16 mov -0x81(%rax, %rbx, 8), %cl 66 8a 0c 1c data16 mov (%rsp, %rbx, 1), %cl 66 8a 35 12 34 56 78 data16 mov 0x78563412(%rip), %dh 66 67 8a 35 12 34 56 78 data16 mov 0x78563412(%eip), %dh 66 8a 04 20 data16 mov (%rax, %riz, 1), %al 66 8a 84 20 12 34 56 78 data16 mov 0x78563412(%rax, %riz, 1), %al 66 8a 04 20 data16 mov (%rax, %riz, 1), %al 66 8a 0c 20 data16 mov (%rax, %riz, 1), %cl 66 8a 14 20 data16 mov (%rax, %riz, 1), %dl 66 8a 1c 20 data16 mov (%rax, %riz, 1), %bl 66 8a 24 20 data16 mov (%rax, %riz, 1), %ah 66 8a 2c 20 data16 mov (%rax, %riz, 1), %ch 66 8a 34 20 data16 mov (%rax, %riz, 1), %dh 66 8a 3c 20 data16 mov (%rax, %riz, 1), %bh 66 8a 04 21 data16 mov (%rcx, %riz, 1), %al 66 8a 04 22 data16 mov (%rdx, %riz, 1), %al 66 8a 04 23 data16 mov (%rbx, %riz, 1), %al 66 8a 04 24 data16 mov (%rsp), %al 66 8a 04 25 12 34 56 78 data16 mov 0x78563412, %al 66 8a 04 65 12 34 56 78 data16 mov 0x78563412(, %riz, 2), %al 66 8a 04 a5 12 34 56 78 data16 mov 0x78563412(, %riz, 4), %al 66 8a 04 e5 12 34 56 78 data16 mov 0x78563412(, %riz, 8), %al 66 8a 04 26 data16 mov (%rsi, %riz, 1), %al 66 8a 04 27 data16 mov (%rdi, %riz, 1), %al 66 8a 04 64 data16 mov (%rsp, %riz, 2), %al 66 8a 04 a4 data16 mov (%rsp, %riz, 4), %al 66 8a 04 e4 data16 mov (%rsp, %riz, 8), %al 66 8a 44 20 3a data16 mov 0x3a(%rax, %riz, 1), %al 66 8a 4c 20 3a data16 mov 0x3a(%rax, %riz, 1), %cl 66 8a 54 20 3a data16 mov 0x3a(%rax, %riz, 1), %dl 66 8a 5c 20 3a data16 mov 0x3a(%rax, %riz, 1), %bl 66 8a 64 20 3a data16 mov 0x3a(%rax, %riz, 1), %ah 66 8a 6c 20 3a data16 mov 0x3a(%rax, %riz, 1), %ch 66 8a 74 20 3a data16 mov 0x3a(%rax, %riz, 1), %dh 66 8a 7c 20 3a data16 mov 0x3a(%rax, %riz, 1), %bh 66 8a 44 24 3a data16 mov 0x3a(%rsp), %al 66 8a 44 64 3a data16 mov 0x3a(%rsp, %riz, 2), %al 66 8a 44 a4 3a data16 mov 0x3a(%rsp, %riz, 4), %al 66 8a 44 e4 3a data16 mov 0x3a(%rsp, %riz, 8), %al 66 8a 44 25 3a data16 mov 0x3a(%rbp, %riz, 1), %al 66 8a 44 65 3a data16 mov 0x3a(%rbp, %riz, 2), %al 66 8a 44 a5 3a data16 mov 0x3a(%rbp, %riz, 4), %al 66 8a 44 e5 3a data16 mov 0x3a(%rbp, %riz, 8), %al 67 8a 4c 18 79 mov 0x79(%eax, %ebx, 1), %cl 67 8a 4c 58 80 mov -0x80(%eax, %ebx, 2), %cl 67 8a 8c 98 80 00 00 00 mov 0x80(%eax, %ebx, 4), %cl 67 8a 8c d8 7f ff ff ff mov -0x81(%eax, %ebx, 8), %cl 67 8a 0c 1c mov (%esp, %ebx, 1), %cl 67 8a 35 12 34 56 78 mov 0x78563412(%eip), %dh 67 67 8a 35 12 34 56 78 addr32 mov 0x78563412(%eip), %dh 67 8a 04 20 mov (%eax, %eiz, 1), %al 67 8a 84 20 12 34 56 78 mov 0x78563412(%eax, %eiz, 1), %al 67 8a 04 20 mov (%eax, %eiz, 1), %al 67 8a 0c 20 mov (%eax, %eiz, 1), %cl 67 8a 14 20 mov (%eax, %eiz, 1), %dl 67 8a 1c 20 mov (%eax, %eiz, 1), %bl 67 8a 24 20 mov (%eax, %eiz, 1), %ah 67 8a 2c 20 mov (%eax, %eiz, 1), %ch 67 8a 34 20 mov (%eax, %eiz, 1), %dh 67 8a 3c 20 mov (%eax, %eiz, 1), %bh 67 8a 04 21 mov (%ecx, %eiz, 1), %al 67 8a 04 22 mov (%edx, %eiz, 1), %al 67 8a 04 23 mov (%ebx, %eiz, 1), %al 67 8a 04 24 mov (%esp), %al 67 8a 04 25 12 34 56 78 mov 0x78563412(, %eiz, 1), %al 67 8a 04 65 12 34 56 78 mov 0x78563412(, %eiz, 2), %al 67 8a 04 a5 12 34 56 78 mov 0x78563412(, %eiz, 4), %al 67 8a 04 e5 12 34 56 78 mov 0x78563412(, %eiz, 8), %al 67 8a 04 26 mov (%esi, %eiz, 1), %al 67 8a 04 27 mov (%edi, %eiz, 1), %al 67 8a 04 64 mov (%esp, %eiz, 2), %al 67 8a 04 a4 mov (%esp, %eiz, 4), %al 67 8a 04 e4 mov (%esp, %eiz, 8), %al 67 8a 44 20 3a mov 0x3a(%eax, %eiz, 1), %al 67 8a 4c 20 3a mov 0x3a(%eax, %eiz, 1), %cl 67 8a 54 20 3a mov 0x3a(%eax, %eiz, 1), %dl 67 8a 5c 20 3a mov 0x3a(%eax, %eiz, 1), %bl 67 8a 64 20 3a mov 0x3a(%eax, %eiz, 1), %ah 67 8a 6c 20 3a mov 0x3a(%eax, %eiz, 1), %ch 67 8a 74 20 3a mov 0x3a(%eax, %eiz, 1), %dh 67 8a 7c 20 3a mov 0x3a(%eax, %eiz, 1), %bh 67 8a 44 24 3a mov 0x3a(%esp), %al 67 8a 44 64 3a mov 0x3a(%esp, %eiz, 2), %al 67 8a 44 a4 3a mov 0x3a(%esp, %eiz, 4), %al 67 8a 44 e4 3a mov 0x3a(%esp, %eiz, 8), %al 67 8a 44 25 3a mov 0x3a(%ebp, %eiz, 1), %al 67 8a 44 65 3a mov 0x3a(%ebp, %eiz, 2), %al 67 8a 44 a5 3a mov 0x3a(%ebp, %eiz, 4), %al 67 8a 44 e5 3a mov 0x3a(%ebp, %eiz, 8), %al 8a 44 24 12 mov 0x12(%rsp), %al 8a 44 25 12 mov 0x12(%rbp, %riz, 1), %al 8a 44 65 12 mov 0x12(%rbp, %riz, 2), %al 8a 44 a5 12 mov 0x12(%rbp, %riz, 4), %al 8a 44 e5 12 mov 0x12(%rbp, %riz, 8), %al 8a 84 24 12 34 56 78 mov 0x78563412(%rsp), %al 8a 84 25 12 34 56 78 mov 0x78563412(%rbp, %riz, 1), %al 8a 84 65 12 34 56 78 mov 0x78563412(%rbp, %riz, 2), %al 8a 84 a5 12 34 56 78 mov 0x78563412(%rbp, %riz, 4), %al 8a 84 e5 12 34 56 78 mov 0x78563412(%rbp, %riz, 8), %al 8a c4 mov %ah, %al 8a 05 12 34 56 78 mov 0x78563412(%rip), %al 8a 0d 12 34 56 78 mov 0x78563412(%rip), %cl 8a 15 12 34 56 78 mov 0x78563412(%rip), %dl 8a 1d 12 34 56 78 mov 0x78563412(%rip), %bl 8a 25 12 34 56 78 mov 0x78563412(%rip), %ah 8a 2d 12 34 56 78 mov 0x78563412(%rip), %ch 8a 35 12 34 56 78 mov 0x78563412(%rip), %dh 8a 3d 12 34 56 78 mov 0x78563412(%rip), %bh 8a 45 12 mov 0x12(%rbp), %al

jared-hughes/defcpu

18,722

tests/disassembly/sources/011_rm8.s

fe 00 incb (%rax) fe 01 incb (%rcx) fe 02 incb (%rdx) fe 03 incb (%rbx) fe 04 12 incb (%rdx, %rdx, 1) fe 05 12 34 56 78 incb 0x78563412(%rip) fe 06 incb (%rsi) fe 07 incb (%rdi) fe 40 12 incb 0x12(%rax) fe 41 12 incb 0x12(%rcx) fe 42 12 incb 0x12(%rdx) fe 43 12 incb 0x12(%rbx) fe 44 12 34 incb 0x34(%rdx, %rdx, 1) fe 45 12 incb 0x12(%rbp) fe 46 12 incb 0x12(%rsi) fe 47 12 incb 0x12(%rdi) fe 80 12 34 56 78 incb 0x78563412(%rax) fe 81 12 34 56 78 incb 0x78563412(%rcx) fe 82 12 34 56 78 incb 0x78563412(%rdx) fe 83 12 34 56 78 incb 0x78563412(%rbx) fe 84 12 34 56 78 9a incb -0x6587a9cc(%rdx, %rdx, 1) fe 85 12 34 56 78 incb 0x78563412(%rbp) fe 86 12 34 56 78 incb 0x78563412(%rsi) fe 87 12 34 56 78 incb 0x78563412(%rdi) fe c0 inc %al fe c1 inc %cl fe c2 inc %dl fe c3 inc %bl fe c4 inc %ah fe c5 inc %ch fe c6 inc %dh fe c7 inc %bh 67 fe 00 incb (%eax) 67 fe 01 incb (%ecx) 67 fe 02 incb (%edx) 67 fe 03 incb (%ebx) 67 fe 04 12 incb (%edx, %edx, 1) 67 fe 05 12 34 56 78 incb 0x78563412(%eip) 67 fe 06 incb (%esi) 67 fe 07 incb (%edi) 67 fe 40 12 incb 0x12(%eax) 67 fe 41 12 incb 0x12(%ecx) 67 fe 42 12 incb 0x12(%edx) 67 fe 43 12 incb 0x12(%ebx) 67 fe 44 12 34 incb 0x34(%edx, %edx, 1) 67 fe 45 12 incb 0x12(%ebp) 67 fe 46 12 incb 0x12(%esi) 67 fe 47 12 incb 0x12(%edi) 67 fe 80 12 34 56 78 incb 0x78563412(%eax) 67 fe 81 12 34 56 78 incb 0x78563412(%ecx) 67 fe 82 12 34 56 78 incb 0x78563412(%edx) 67 fe 83 12 34 56 78 incb 0x78563412(%ebx) 67 fe 84 12 34 56 78 9a incb -0x6587a9cc(%edx, %edx, 1) 67 fe 85 12 34 56 78 incb 0x78563412(%ebp) 67 fe 86 12 34 56 78 incb 0x78563412(%esi) 67 fe 87 12 34 56 78 incb 0x78563412(%edi) 67 fe c0 addr32 inc %al 67 fe c1 addr32 inc %cl 67 fe c2 addr32 inc %dl 67 fe c3 addr32 inc %bl 67 fe c4 addr32 inc %ah 67 fe c5 addr32 inc %ch 67 fe c6 addr32 inc %dh 67 fe c7 addr32 inc %bh 41 fe 00 incb (%r8) 41 fe 01 incb (%r9) 41 fe 02 incb (%r10) 41 fe 03 incb (%r11) 41 fe 04 12 incb (%r10, %rdx, 1) 41 fe 05 12 34 56 78 incb 0x78563412(%rip) 41 fe 06 incb (%r14) 41 fe 07 incb (%r15) 41 fe 40 12 incb 0x12(%r8) 41 fe 41 12 incb 0x12(%r9) 41 fe 42 12 incb 0x12(%r10) 41 fe 43 12 incb 0x12(%r11) 41 fe 44 00 12 incb 0x12(%r8, %rax, 1) 41 fe 44 01 12 incb 0x12(%r9, %rax, 1) 41 fe 44 02 12 incb 0x12(%r10, %rax, 1) 41 fe 44 03 12 incb 0x12(%r11, %rax, 1) 41 fe 44 04 12 incb 0x12(%r12, %rax, 1) 41 fe 44 05 12 incb 0x12(%r13, %rax, 1) 41 fe 44 06 12 incb 0x12(%r14, %rax, 1) 41 fe 44 07 12 incb 0x12(%r15, %rax, 1) 41 fe 44 08 12 incb 0x12(%r8, %rcx, 1) 41 fe 44 09 12 incb 0x12(%r9, %rcx, 1) 41 fe 44 0a 12 incb 0x12(%r10, %rcx, 1) 41 fe 44 0b 12 incb 0x12(%r11, %rcx, 1) 41 fe 44 0c 12 incb 0x12(%r12, %rcx, 1) 41 fe 44 0d 12 incb 0x12(%r13, %rcx, 1) 41 fe 44 0e 12 incb 0x12(%r14, %rcx, 1) 41 fe 44 0f 12 incb 0x12(%r15, %rcx, 1) 41 fe 44 10 12 incb 0x12(%r8, %rdx, 1) 41 fe 44 11 12 incb 0x12(%r9, %rdx, 1) 41 fe 44 12 12 incb 0x12(%r10, %rdx, 1) 41 fe 44 13 12 incb 0x12(%r11, %rdx, 1) 41 fe 44 14 12 incb 0x12(%r12, %rdx, 1) 41 fe 44 15 12 incb 0x12(%r13, %rdx, 1) 41 fe 44 16 12 incb 0x12(%r14, %rdx, 1) 41 fe 44 17 12 incb 0x12(%r15, %rdx, 1) 41 fe 44 18 12 incb 0x12(%r8, %rbx, 1) 41 fe 44 19 12 incb 0x12(%r9, %rbx, 1) 41 fe 44 1a 12 incb 0x12(%r10, %rbx, 1) 41 fe 44 1b 12 incb 0x12(%r11, %rbx, 1) 41 fe 44 1c 12 incb 0x12(%r12, %rbx, 1) 41 fe 44 1d 12 incb 0x12(%r13, %rbx, 1) 41 fe 44 1e 12 incb 0x12(%r14, %rbx, 1) 41 fe 44 1f 12 incb 0x12(%r15, %rbx, 1) 41 fe 44 20 12 incb 0x12(%r8, %riz, 1) 41 fe 44 21 12 incb 0x12(%r9, %riz, 1) 41 fe 44 22 12 incb 0x12(%r10, %riz, 1) 41 fe 44 23 12 incb 0x12(%r11, %riz, 1) 41 fe 44 24 12 incb 0x12(%r12) 41 fe 44 25 12 incb 0x12(%r13, %riz, 1) 41 fe 44 26 12 incb 0x12(%r14, %riz, 1) 41 fe 44 27 12 incb 0x12(%r15, %riz, 1) 41 fe 44 28 12 incb 0x12(%r8, %rbp, 1) 41 fe 44 29 12 incb 0x12(%r9, %rbp, 1) 41 fe 44 2a 12 incb 0x12(%r10, %rbp, 1) 41 fe 44 2b 12 incb 0x12(%r11, %rbp, 1) 41 fe 44 2c 12 incb 0x12(%r12, %rbp, 1) 41 fe 44 2d 12 incb 0x12(%r13, %rbp, 1) 41 fe 44 2e 12 incb 0x12(%r14, %rbp, 1) 41 fe 44 2f 12 incb 0x12(%r15, %rbp, 1) 41 fe 44 30 12 incb 0x12(%r8, %rsi, 1) 41 fe 44 31 12 incb 0x12(%r9, %rsi, 1) 41 fe 44 32 12 incb 0x12(%r10, %rsi, 1) 41 fe 44 33 12 incb 0x12(%r11, %rsi, 1) 41 fe 44 34 12 incb 0x12(%r12, %rsi, 1) 41 fe 44 35 12 incb 0x12(%r13, %rsi, 1) 41 fe 44 36 12 incb 0x12(%r14, %rsi, 1) 41 fe 44 37 12 incb 0x12(%r15, %rsi, 1) 41 fe 44 38 12 incb 0x12(%r8, %rdi, 1) 41 fe 44 39 12 incb 0x12(%r9, %rdi, 1) 41 fe 44 3a 12 incb 0x12(%r10, %rdi, 1) 41 fe 44 3b 12 incb 0x12(%r11, %rdi, 1) 41 fe 44 3c 12 incb 0x12(%r12, %rdi, 1) 41 fe 44 3d 12 incb 0x12(%r13, %rdi, 1) 41 fe 44 3e 12 incb 0x12(%r14, %rdi, 1) 41 fe 44 3f 12 incb 0x12(%r15, %rdi, 1) 41 fe 44 40 12 incb 0x12(%r8, %rax, 2) 41 fe 44 41 12 incb 0x12(%r9, %rax, 2) 41 fe 44 42 12 incb 0x12(%r10, %rax, 2) 41 fe 44 43 12 incb 0x12(%r11, %rax, 2) 41 fe 44 44 12 incb 0x12(%r12, %rax, 2) 41 fe 44 45 12 incb 0x12(%r13, %rax, 2) 41 fe 44 46 12 incb 0x12(%r14, %rax, 2) 41 fe 44 47 12 incb 0x12(%r15, %rax, 2) 41 fe 44 48 12 incb 0x12(%r8, %rcx, 2) 41 fe 44 49 12 incb 0x12(%r9, %rcx, 2) 41 fe 44 4a 12 incb 0x12(%r10, %rcx, 2) 41 fe 44 4b 12 incb 0x12(%r11, %rcx, 2) 41 fe 44 4c 12 incb 0x12(%r12, %rcx, 2) 41 fe 44 4d 12 incb 0x12(%r13, %rcx, 2) 41 fe 44 4e 12 incb 0x12(%r14, %rcx, 2) 41 fe 44 4f 12 incb 0x12(%r15, %rcx, 2) 41 fe 44 50 12 incb 0x12(%r8, %rdx, 2) 41 fe 44 51 12 incb 0x12(%r9, %rdx, 2) 41 fe 44 52 12 incb 0x12(%r10, %rdx, 2) 41 fe 44 53 12 incb 0x12(%r11, %rdx, 2) 41 fe 44 54 12 incb 0x12(%r12, %rdx, 2) 41 fe 44 55 12 incb 0x12(%r13, %rdx, 2) 41 fe 44 56 12 incb 0x12(%r14, %rdx, 2) 41 fe 44 57 12 incb 0x12(%r15, %rdx, 2) 41 fe 44 58 12 incb 0x12(%r8, %rbx, 2) 41 fe 44 59 12 incb 0x12(%r9, %rbx, 2) 41 fe 44 5a 12 incb 0x12(%r10, %rbx, 2) 41 fe 44 5b 12 incb 0x12(%r11, %rbx, 2) 41 fe 44 5c 12 incb 0x12(%r12, %rbx, 2) 41 fe 44 5d 12 incb 0x12(%r13, %rbx, 2) 41 fe 44 5e 12 incb 0x12(%r14, %rbx, 2) 41 fe 44 5f 12 incb 0x12(%r15, %rbx, 2) 41 fe 44 60 12 incb 0x12(%r8, %riz, 2) 41 fe 44 61 12 incb 0x12(%r9, %riz, 2) 41 fe 44 62 12 incb 0x12(%r10, %riz, 2) 41 fe 44 63 12 incb 0x12(%r11, %riz, 2) 41 fe 44 64 12 incb 0x12(%r12, %riz, 2) 41 fe 44 65 12 incb 0x12(%r13, %riz, 2) 41 fe 44 66 12 incb 0x12(%r14, %riz, 2) 41 fe 44 67 12 incb 0x12(%r15, %riz, 2) 41 fe 44 68 12 incb 0x12(%r8, %rbp, 2) 41 fe 44 69 12 incb 0x12(%r9, %rbp, 2) 41 fe 44 6a 12 incb 0x12(%r10, %rbp, 2) 41 fe 44 6b 12 incb 0x12(%r11, %rbp, 2) 41 fe 44 6c 12 incb 0x12(%r12, %rbp, 2) 41 fe 44 6d 12 incb 0x12(%r13, %rbp, 2) 41 fe 44 6e 12 incb 0x12(%r14, %rbp, 2) 41 fe 44 6f 12 incb 0x12(%r15, %rbp, 2) 41 fe 44 70 12 incb 0x12(%r8, %rsi, 2) 41 fe 44 71 12 incb 0x12(%r9, %rsi, 2) 41 fe 44 72 12 incb 0x12(%r10, %rsi, 2) 41 fe 44 73 12 incb 0x12(%r11, %rsi, 2) 41 fe 44 74 12 incb 0x12(%r12, %rsi, 2) 41 fe 44 75 12 incb 0x12(%r13, %rsi, 2) 41 fe 44 76 12 incb 0x12(%r14, %rsi, 2) 41 fe 44 77 12 incb 0x12(%r15, %rsi, 2) 41 fe 44 78 12 incb 0x12(%r8, %rdi, 2) 41 fe 44 79 12 incb 0x12(%r9, %rdi, 2) 41 fe 44 7a 12 incb 0x12(%r10, %rdi, 2) 41 fe 44 7b 12 incb 0x12(%r11, %rdi, 2) 41 fe 44 7c 12 incb 0x12(%r12, %rdi, 2) 41 fe 44 7d 12 incb 0x12(%r13, %rdi, 2) 41 fe 44 7e 12 incb 0x12(%r14, %rdi, 2) 41 fe 44 7f 12 incb 0x12(%r15, %rdi, 2) 41 fe 44 80 12 incb 0x12(%r8, %rax, 4) 41 fe 44 81 12 incb 0x12(%r9, %rax, 4) 41 fe 44 82 12 incb 0x12(%r10, %rax, 4) 41 fe 44 83 12 incb 0x12(%r11, %rax, 4) 41 fe 44 84 12 incb 0x12(%r12, %rax, 4) 41 fe 44 85 12 incb 0x12(%r13, %rax, 4) 41 fe 44 86 12 incb 0x12(%r14, %rax, 4) 41 fe 44 87 12 incb 0x12(%r15, %rax, 4) 41 fe 44 88 12 incb 0x12(%r8, %rcx, 4) 41 fe 44 89 12 incb 0x12(%r9, %rcx, 4) 41 fe 44 8a 12 incb 0x12(%r10, %rcx, 4) 41 fe 44 8b 12 incb 0x12(%r11, %rcx, 4) 41 fe 44 8c 12 incb 0x12(%r12, %rcx, 4) 41 fe 44 8d 12 incb 0x12(%r13, %rcx, 4) 41 fe 44 8e 12 incb 0x12(%r14, %rcx, 4) 41 fe 44 8f 12 incb 0x12(%r15, %rcx, 4) 41 fe 44 90 12 incb 0x12(%r8, %rdx, 4) 41 fe 44 91 12 incb 0x12(%r9, %rdx, 4) 41 fe 44 92 12 incb 0x12(%r10, %rdx, 4) 41 fe 44 93 12 incb 0x12(%r11, %rdx, 4) 41 fe 44 94 12 incb 0x12(%r12, %rdx, 4) 41 fe 44 95 12 incb 0x12(%r13, %rdx, 4) 41 fe 44 96 12 incb 0x12(%r14, %rdx, 4) 41 fe 44 97 12 incb 0x12(%r15, %rdx, 4) 41 fe 44 98 12 incb 0x12(%r8, %rbx, 4) 41 fe 44 99 12 incb 0x12(%r9, %rbx, 4) 41 fe 44 9a 12 incb 0x12(%r10, %rbx, 4) 41 fe 44 9b 12 incb 0x12(%r11, %rbx, 4) 41 fe 44 9c 12 incb 0x12(%r12, %rbx, 4) 41 fe 44 9d 12 incb 0x12(%r13, %rbx, 4) 41 fe 44 9e 12 incb 0x12(%r14, %rbx, 4) 41 fe 44 9f 12 incb 0x12(%r15, %rbx, 4) 41 fe 44 a0 12 incb 0x12(%r8, %riz, 4) 41 fe 44 a1 12 incb 0x12(%r9, %riz, 4) 41 fe 44 a2 12 incb 0x12(%r10, %riz, 4) 41 fe 44 a3 12 incb 0x12(%r11, %riz, 4) 41 fe 44 a4 12 incb 0x12(%r12, %riz, 4) 41 fe 44 a5 12 incb 0x12(%r13, %riz, 4) 41 fe 44 a6 12 incb 0x12(%r14, %riz, 4) 41 fe 44 a7 12 incb 0x12(%r15, %riz, 4) 41 fe 44 a8 12 incb 0x12(%r8, %rbp, 4) 41 fe 44 a9 12 incb 0x12(%r9, %rbp, 4) 41 fe 44 aa 12 incb 0x12(%r10, %rbp, 4) 41 fe 44 ab 12 incb 0x12(%r11, %rbp, 4) 41 fe 44 ac 12 incb 0x12(%r12, %rbp, 4) 41 fe 44 ad 12 incb 0x12(%r13, %rbp, 4) 41 fe 44 ae 12 incb 0x12(%r14, %rbp, 4) 41 fe 44 af 12 incb 0x12(%r15, %rbp, 4) 41 fe 44 b0 12 incb 0x12(%r8, %rsi, 4) 41 fe 44 b1 12 incb 0x12(%r9, %rsi, 4) 41 fe 44 b2 12 incb 0x12(%r10, %rsi, 4) 41 fe 44 b3 12 incb 0x12(%r11, %rsi, 4) 41 fe 44 b4 12 incb 0x12(%r12, %rsi, 4) 41 fe 44 b5 12 incb 0x12(%r13, %rsi, 4) 41 fe 44 b6 12 incb 0x12(%r14, %rsi, 4) 41 fe 44 b7 12 incb 0x12(%r15, %rsi, 4) 41 fe 44 b8 12 incb 0x12(%r8, %rdi, 4) 41 fe 44 b9 12 incb 0x12(%r9, %rdi, 4) 41 fe 44 ba 12 incb 0x12(%r10, %rdi, 4) 41 fe 44 bb 12 incb 0x12(%r11, %rdi, 4) 41 fe 44 bc 12 incb 0x12(%r12, %rdi, 4) 41 fe 44 bd 12 incb 0x12(%r13, %rdi, 4) 41 fe 44 be 12 incb 0x12(%r14, %rdi, 4) 41 fe 44 bf 12 incb 0x12(%r15, %rdi, 4) 41 fe 44 c0 12 incb 0x12(%r8, %rax, 8) 41 fe 44 c1 12 incb 0x12(%r9, %rax, 8) 41 fe 44 c2 12 incb 0x12(%r10, %rax, 8) 41 fe 44 c3 12 incb 0x12(%r11, %rax, 8) 41 fe 44 c4 12 incb 0x12(%r12, %rax, 8) 41 fe 44 c5 12 incb 0x12(%r13, %rax, 8) 41 fe 44 c6 12 incb 0x12(%r14, %rax, 8) 41 fe 44 c7 12 incb 0x12(%r15, %rax, 8) 41 fe 44 c8 12 incb 0x12(%r8, %rcx, 8) 41 fe 44 c9 12 incb 0x12(%r9, %rcx, 8) 41 fe 44 ca 12 incb 0x12(%r10, %rcx, 8) 41 fe 44 cb 12 incb 0x12(%r11, %rcx, 8) 41 fe 44 cc 12 incb 0x12(%r12, %rcx, 8) 41 fe 44 cd 12 incb 0x12(%r13, %rcx, 8) 41 fe 44 ce 12 incb 0x12(%r14, %rcx, 8) 41 fe 44 cf 12 incb 0x12(%r15, %rcx, 8) 41 fe 44 d0 12 incb 0x12(%r8, %rdx, 8) 41 fe 44 d1 12 incb 0x12(%r9, %rdx, 8) 41 fe 44 d2 12 incb 0x12(%r10, %rdx, 8) 41 fe 44 d3 12 incb 0x12(%r11, %rdx, 8) 41 fe 44 d4 12 incb 0x12(%r12, %rdx, 8) 41 fe 44 d5 12 incb 0x12(%r13, %rdx, 8) 41 fe 44 d6 12 incb 0x12(%r14, %rdx, 8) 41 fe 44 d7 12 incb 0x12(%r15, %rdx, 8) 41 fe 44 d8 12 incb 0x12(%r8, %rbx, 8) 41 fe 44 d9 12 incb 0x12(%r9, %rbx, 8) 41 fe 44 da 12 incb 0x12(%r10, %rbx, 8) 41 fe 44 db 12 incb 0x12(%r11, %rbx, 8) 41 fe 44 dc 12 incb 0x12(%r12, %rbx, 8) 41 fe 44 dd 12 incb 0x12(%r13, %rbx, 8) 41 fe 44 de 12 incb 0x12(%r14, %rbx, 8) 41 fe 44 df 12 incb 0x12(%r15, %rbx, 8) 41 fe 44 e0 12 incb 0x12(%r8, %riz, 8) 41 fe 44 e1 12 incb 0x12(%r9, %riz, 8) 41 fe 44 e2 12 incb 0x12(%r10, %riz, 8) 41 fe 44 e3 12 incb 0x12(%r11, %riz, 8) 41 fe 44 e4 12 incb 0x12(%r12, %riz, 8) 41 fe 44 e5 12 incb 0x12(%r13, %riz, 8) 41 fe 44 e6 12 incb 0x12(%r14, %riz, 8) 41 fe 44 e7 12 incb 0x12(%r15, %riz, 8) 41 fe 44 e8 12 incb 0x12(%r8, %rbp, 8) 41 fe 44 e9 12 incb 0x12(%r9, %rbp, 8) 41 fe 44 ea 12 incb 0x12(%r10, %rbp, 8) 41 fe 44 eb 12 incb 0x12(%r11, %rbp, 8) 41 fe 44 ec 12 incb 0x12(%r12, %rbp, 8) 41 fe 44 ed 12 incb 0x12(%r13, %rbp, 8) 41 fe 44 ee 12 incb 0x12(%r14, %rbp, 8) 41 fe 44 ef 12 incb 0x12(%r15, %rbp, 8) 41 fe 44 f0 12 incb 0x12(%r8, %rsi, 8) 41 fe 44 f1 12 incb 0x12(%r9, %rsi, 8) 41 fe 44 f2 12 incb 0x12(%r10, %rsi, 8) 41 fe 44 f3 12 incb 0x12(%r11, %rsi, 8) 41 fe 44 f4 12 incb 0x12(%r12, %rsi, 8) 41 fe 44 f5 12 incb 0x12(%r13, %rsi, 8) 41 fe 44 f6 12 incb 0x12(%r14, %rsi, 8) 41 fe 44 f7 12 incb 0x12(%r15, %rsi, 8) 41 fe 44 f8 12 incb 0x12(%r8, %rdi, 8) 41 fe 44 f9 12 incb 0x12(%r9, %rdi, 8) 41 fe 44 fa 12 incb 0x12(%r10, %rdi, 8) 41 fe 44 fb 12 incb 0x12(%r11, %rdi, 8) 41 fe 44 fc 12 incb 0x12(%r12, %rdi, 8) 41 fe 44 fd 12 incb 0x12(%r13, %rdi, 8) 41 fe 44 fe 12 incb 0x12(%r14, %rdi, 8) 41 fe 44 ff 12 incb 0x12(%r15, %rdi, 8) 41 fe 45 12 incb 0x12(%r13) 41 fe 46 12 incb 0x12(%r14) 41 fe 47 12 incb 0x12(%r15) 41 fe 80 12 34 56 78 incb 0x78563412(%r8) 41 fe 81 12 34 56 78 incb 0x78563412(%r9) 41 fe 82 12 34 56 78 incb 0x78563412(%r10) 41 fe 83 12 34 56 78 incb 0x78563412(%r11) 41 fe 84 12 34 56 78 9a incb -0x6587a9cc(%r10, %rdx, 1) 41 fe 85 12 34 56 78 incb 0x78563412(%r13) 41 fe 86 12 34 56 78 incb 0x78563412(%r14) 41 fe 87 12 34 56 78 incb 0x78563412(%r15) 41 fe c0 inc %r8b 41 fe c1 inc %r9b 41 fe c2 inc %r10b 41 fe c3 inc %r11b 41 fe c4 inc %r12b 41 fe c5 inc %r13b 41 fe c6 inc %r14b 41 fe c7 inc %r15b 40 fe c0 rex inc %al 40 fe c1 rex inc %cl 40 fe c2 rex inc %dl 40 fe c3 rex inc %bl 40 fe c4 inc %spl 40 fe c5 inc %bpl 40 fe c6 inc %sil 40 fe c7 inc %dil

jared-hughes/defcpu

895

tests/disassembly/sources/018_scas.s

ae scas %es:(%rdi), %al 66 ae data16 scas %es:(%rdi), %al 67 ae scas %es:(%edi), %al 66 67 ae data16 scas %es:(%edi), %al 41 ae rex.B scas %es:(%rdi), %al 48 ae rex.W scas %es:(%rdi), %al 49 ae rex.WB scas %es:(%rdi), %al 67 49 ae rex.WB scas %es:(%edi), %al 66 af scas %es:(%rdi), %ax 67 af scas %es:(%edi), %eax 66 67 af scas %es:(%edi), %ax 41 af rex.B scas %es:(%rdi), %eax 66 41 af rex.B scas %es:(%rdi), %ax 67 41 af rex.B scas %es:(%edi), %eax 66 67 41 af rex.B scas %es:(%edi), %ax 48 af scas %es:(%rdi), %rax 66 48 af data16 scas %es:(%rdi), %rax 67 48 af scas %es:(%edi), %rax 66 67 48 data16 addr32 rex.W 49 af rex.WB scas %es:(%rdi), %rax 66 49 af data16 rex.WB scas %es:(%rdi), %rax 67 49 af rex.WB scas %es:(%edi), %rax 66 67 49 af data16 rex.WB scas %es:(%edi), %rax

jared-hughes/defcpu

14,904

tests/disassembly/sources/005_fuzz_rex_mov.s

bf 4f b0 b9 4a mov $0x4ab9b04f, %edi b8 47 4a 4c 40 mov $0x404c4a47, %eax b0 b8 mov $0xb8, %al 47 b3 b9 rex.RXB mov $0xb9, %r11b 40 bf 47 4a 47 b3 rex mov $0xb3474a47, %edi 4f rex.WRXB 4c b3 4c rex.WR mov $0x4c, %bl 40 rex 4c bf bf b8 4c 4c 4a 4a 47 47 rex.WR movabs $0x47474a4a4c4cb8bf, %rdi 4c rex.WR 4c rex.WR 4f b0 47 rex.WRXB mov $0x47, %r8b b9 47 4c 47 b3 mov $0xb3474c47, %ecx 4f rex.WRXB 4a b0 b3 rex.WX mov $0xb3, %al 4c rex.WR 4c rex.WR 4f rex.WRXB 40 b0 4f rex mov $0x4f, %al bf bf 4a bf b0 mov $0xb0bf4abf, %edi 40 rex 4f b0 4f rex.WRXB mov $0x4f, %r8b b8 b0 4c b8 b8 mov $0xb8b84cb0, %eax 4c rex.WR 4a rex.WX 4f rex.WRXB 4a b0 b3 rex.WX mov $0xb3, %al 4a b9 b3 b0 b3 bf 4a b8 4a 4c rex.WX movabs $0x4c4ab84abfb3b0b3, %rcx bf 47 40 47 b8 mov $0xb8474047, %edi b0 b9 mov $0xb9, %al b0 b9 mov $0xb9, %al 4f b8 40 bf b0 4f 4a b3 40 47 rex.WRXB movabs $0x4740b34a4fb0bf40, %r8 b0 b9 mov $0xb9, %al bf b0 4c b0 4f mov $0x4fb04cb0, %edi b9 40 4f b0 4f mov $0x4fb04f40, %ecx 4c rex.WR 40 rex 4c rex.WR 4f b8 4c 4a 40 bf b9 b3 4a 47 rex.WRXB movabs $0x474ab3b9bf404a4c, %r8 bf b0 4f b8 b3 mov $0xb3b84fb0, %edi 4c rex.WR 4a rex.WX 4a b8 b0 47 4c bf 4c b3 40 4c rex.WX movabs $0x4c40b34cbf4c47b0, %rax b3 b0 mov $0xb0, %bl 4c rex.WR 4a b3 4f rex.WX mov $0x4f, %bl 4c b8 bf 4c b9 b8 b8 b0 b8 4f rex.WR movabs $0x4fb8b0b8b8b94cbf, %rax 4f b8 b3 4c 40 b3 b9 4c b8 b0 rex.WRXB movabs $0xb0b84cb9b3404cb3, %r8 4c rex.WR 40 b8 4f b9 b9 b9 rex mov $0xb9b9b94f, %eax b0 40 mov $0x40, %al b0 bf mov $0xbf, %al 4a rex.WX 4f b0 b9 rex.WRXB mov $0xb9, %r8b 4f b8 4f 4f b0 4c bf 4a b8 b9 rex.WRXB movabs $0xb9b84abf4cb04f4f, %r8 4f b0 4f rex.WRXB mov $0x4f, %r8b b8 4f b9 b0 b0 mov $0xb0b0b94f, %eax 4f b0 b3 rex.WRXB mov $0xb3, %r8b b0 4c mov $0x4c, %al b8 b0 b0 b9 4c mov $0x4cb9b0b0, %eax b9 4c 47 b0 b8 mov $0xb8b0474c, %ecx 4f rex.WRXB 40 b3 4c rex mov $0x4c, %bl bf bf b9 b3 4f mov $0x4fb3b9bf, %edi bf b9 4f 4a 47 mov $0x474a4fb9, %edi 4c bf b8 bf 4c 47 4c 4a b8 47 rex.WR movabs $0x47b84a4c474cbfb8, %rdi 4c rex.WR 4a rex.WX 4c rex.WR 40 b0 4c rex mov $0x4c, %al b8 47 b9 4a b3 mov $0xb34ab947, %eax b8 b0 b3 bf 40 mov $0x40bfb3b0, %eax bf 47 47 b0 4a mov $0x4ab04747, %edi b0 b3 mov $0xb3, %al 4f b3 40 rex.WRXB mov $0x40, %r11b b9 b0 4a b9 bf mov $0xbfb94ab0, %ecx 4f rex.WRXB 40 rex 4f b9 b9 b0 bf 4f b0 4c b3 b3 rex.WRXB movabs $0xb3b34cb04fbfb0b9, %r9 bf b9 b0 b8 4c mov $0x4cb8b0b9, %edi 4c bf b3 bf b8 47 4c bf 40 b0 rex.WR movabs $0xb040bf4c47b8bfb3, %rdi 4a b3 40 rex.WX mov $0x40, %bl b0 bf mov $0xbf, %al bf b9 4c b0 bf mov $0xbfb04cb9, %edi b3 b3 mov $0xb3, %bl b3 47 mov $0x47, %bl b8 4f b8 b3 b3 mov $0xb3b3b84f, %eax 4c bf bf 4f 4f b8 4f b3 4a b0 rex.WR movabs $0xb04ab34fb84f4fbf, %rdi 4f b8 4f 4c b8 4a 40 bf b8 47 rex.WRXB movabs $0x47b8bf404ab84c4f, %r8 4f rex.WRXB 4a rex.WX 4c b3 4a rex.WR mov $0x4a, %bl b8 b9 b9 4f 47 mov $0x474fb9b9, %eax b8 4a 47 b8 4f mov $0x4fb8474a, %eax 4c rex.WR 4f rex.WRXB 4f b8 bf b8 b9 bf 40 4a 4c 4f rex.WRXB movabs $0x4f4c4a40bfb9b8bf, %r8 4f b9 b0 bf 4f b9 4a b8 b0 b0 rex.WRXB movabs $0xb0b0b84ab94fbfb0, %r9 bf 4c 4a 4a 4f mov $0x4f4a4a4c, %edi b9 b8 40 b9 47 mov $0x47b940b8, %ecx 4a b3 b3 rex.WX mov $0xb3, %bl bf bf b8 b3 b8 mov $0xb8b3b8bf, %edi b3 47 mov $0x47, %bl 4f b8 40 4f 4a b3 bf 4f b8 4f rex.WRXB movabs $0x4fb84fbfb34a4f40, %r8 4c rex.WR 4c b8 b9 b8 b0 b9 4c b3 bf b9 rex.WR movabs $0xb9bfb34cb9b0b8b9, %rax 4a rex.WX 40 rex 47 rex.RXB 4f rex.WRXB 40 rex 40 rex 4a b0 b3 rex.WX mov $0xb3, %al 40 b3 b8 rex mov $0xb8, %bl 4a rex.WX 40 rex 40 rex 47 bf 40 4c 4f b8 rex.RXB mov $0xb84f4c40, %r15d 4c rex.WR 4c bf 4c b3 4c 40 bf 47 4a b9 rex.WR movabs $0xb94a47bf404cb34c, %rdi 40 b3 40 rex mov $0x40, %bl 4f rex.WRXB 4a bf bf 40 b3 bf 4c 4a b3 40 rex.WX movabs $0x40b34a4cbfb340bf, %rdi b0 bf mov $0xbf, %al b8 b8 b0 b0 4a mov $0x4ab0b0b8, %eax 4c rex.WR 4f rex.WRXB 4c bf b9 4f b9 b9 bf 47 4f 40 rex.WR movabs $0x404f47bfb9b94fb9, %rdi b9 47 4f 4f b9 mov $0xb94f4f47, %ecx 4c rex.WR 47 b0 b8 rex.RXB mov $0xb8, %r8b b3 4c mov $0x4c, %bl 4c rex.WR 4a b0 40 rex.WX mov $0x40, %al bf 4a 40 40 b9 mov $0xb940404a, %edi bf b8 47 b3 b8 mov $0xb8b347b8, %edi b8 b0 40 b9 4a mov $0x4ab940b0, %eax b9 b3 4a 4c b3 mov $0xb34c4ab3, %ecx 47 rex.RXB 40 rex 40 b8 47 4c bf b3 rex mov $0xb3bf4c47, %eax b0 47 mov $0x47, %al 4f b0 bf rex.WRXB mov $0xbf, %r8b b0 b3 mov $0xb3, %al b3 4c mov $0x4c, %bl b0 4f mov $0x4f, %al b3 b0 mov $0xb0, %bl b9 4a bf bf 47 mov $0x47bfbf4a, %ecx 4c b3 40 rex.WR mov $0x40, %bl 40 rex 4a rex.WX 4a rex.WX 4c rex.WR 47 rex.RXB 47 rex.RXB 4a b8 b8 b0 4a b3 b8 4f bf b3 rex.WX movabs $0xb3bf4fb8b34ab0b8, %rax b0 b8 mov $0xb8, %al b8 40 47 4c 4c mov $0x4c4c4740, %eax 40 b0 b3 rex mov $0xb3, %al b8 4c b9 4f 40 mov $0x404fb94c, %eax 4f rex.WRXB 4c rex.WR 4f rex.WRXB 47 rex.RXB 4a b8 4a b0 b0 b0 4a 4a b8 b8 rex.WX movabs $0xb8b84a4ab0b0b04a, %rax 4c rex.WR 40 b0 4f rex mov $0x4f, %al b8 47 4c 4a 47 mov $0x474a4c47, %eax 4a bf 47 40 bf b3 b0 4f 4c b8 rex.WX movabs $0xb84c4fb0b3bf4047, %rdi b0 4f mov $0x4f, %al 40 b8 4c 47 4c 47 rex mov $0x474c474c, %eax 4a bf b3 4f 4a b8 4a b8 b3 4c rex.WX movabs $0x4cb3b84ab84a4fb3, %rdi 4a rex.WX 4a b9 b9 bf b0 40 40 47 b8 40 rex.WX movabs $0x40b8474040b0bfb9, %rcx b8 4a 47 4a b8 mov $0xb84a474a, %eax b3 4a mov $0x4a, %bl 4a rex.WX 4f b3 b8 rex.WRXB mov $0xb8, %r11b 4f rex.WRXB 4a rex.WX 4a rex.WX 47 rex.RXB 4c b9 b3 47 b9 47 40 b0 40 40 rex.WR movabs $0x4040b04047b947b3, %rcx b9 4c bf 40 47 mov $0x4740bf4c, %ecx bf 4a b8 b9 b0 mov $0xb0b9b84a, %edi b8 b3 bf b3 b9 mov $0xb9b3bfb3, %eax 4c rex.WR 4a rex.WX 4f b8 47 b9 40 4c 4f b8 40 4f rex.WRXB movabs $0x4f40b84f4c40b947, %r8 b3 b0 mov $0xb0, %bl 4c rex.WR 4c b9 40 b8 47 40 b3 bf 47 4f rex.WR movabs $0x4f47bfb34047b840, %rcx 4a b8 47 4a 47 4f b0 40 40 b3 rex.WX movabs $0xb34040b04f474a47, %rax b0 b3 mov $0xb3, %al b9 4a 4f 4c bf mov $0xbf4c4f4a, %ecx 4a b8 4c 4a 4a b3 4f 40 b3 b9 rex.WX movabs $0xb9b3404fb34a4a4c, %rax 4c b0 40 rex.WR mov $0x40, %al 4f rex.WRXB 4c rex.WR 4c rex.WR 4f b8 b0 4f 4a 40 b9 b9 4a 4a rex.WRXB movabs $0x4a4ab9b9404a4fb0, %r8 40 rex 4a rex.WX 4c b0 b3 rex.WR mov $0xb3, %al 4f bf 4a 47 b9 b3 4c b0 47 b0 rex.WRXB movabs $0xb047b04cb3b9474a, %r15 b0 4a mov $0x4a, %al 4c bf bf 4c 40 4f b9 bf 4c 4c rex.WR movabs $0x4c4cbfb94f404cbf, %rdi b8 b3 b3 40 b0 mov $0xb040b3b3, %eax b0 b8 mov $0xb8, %al 47 b8 bf b3 4c b8 rex.RXB mov $0xb84cb3bf, %r8d 4a rex.WX 4c b9 b8 b8 bf 4a 40 4c b3 4a rex.WR movabs $0x4ab34c404abfb8b8, %rcx 47 rex.RXB 4a rex.WX 4a bf 47 b8 b0 b3 b8 47 47 4f rex.WX movabs $0x4f4747b8b3b0b847, %rdi 47 rex.RXB 4f b9 b9 b0 47 b0 b0 47 4a bf rex.WRXB movabs $0xbf4a47b0b047b0b9, %r9 b8 b3 b0 4c 4c mov $0x4c4cb0b3, %eax 47 b8 b3 4a 40 4c rex.RXB mov $0x4c404ab3, %r8d b3 40 mov $0x40, %bl 4f rex.WRXB 47 b0 b8 rex.RXB mov $0xb8, %r8b b8 b9 bf 40 47 mov $0x4740bfb9, %eax b3 4a mov $0x4a, %bl 40 b9 bf bf bf 4c rex mov $0x4cbfbfbf, %ecx b3 4a mov $0x4a, %bl b0 4a mov $0x4a, %al bf 4f b9 b3 b9 mov $0xb9b3b94f, %edi b8 b9 b3 b8 bf mov $0xbfb8b3b9, %eax b9 4a b9 4c b3 mov $0xb34cb94a, %ecx b0 bf mov $0xbf, %al 4a b9 47 4f 4f 40 4a 40 b0 bf rex.WX movabs $0xbfb0404a404f4f47, %rcx bf b3 4f 4a 4f mov $0x4f4a4fb3, %edi 47 rex.RXB 40 rex 4a rex.WX 40 rex 4f b0 bf rex.WRXB mov $0xbf, %r8b bf b9 47 b8 b9 mov $0xb9b847b9, %edi 40 rex 40 rex 47 b0 b9 rex.RXB mov $0xb9, %r8b b3 b3 mov $0xb3, %bl 4a b3 b3 rex.WX mov $0xb3, %bl 4c b9 47 bf b0 b3 b0 40 b9 b0 rex.WR movabs $0xb0b940b0b3b0bf47, %rcx 47 rex.RXB 40 rex 47 rex.RXB 4f rex.WRXB 4f rex.WRXB 4f bf 40 4c 40 b3 4c 47 40 bf rex.WRXB movabs $0xbf40474cb3404c40, %r15 bf b9 b3 b3 47 mov $0x47b3b3b9, %edi b3 b8 mov $0xb8, %bl b9 bf 47 4f b3 mov $0xb34f47bf, %ecx 4f rex.WRXB 40 bf b0 4c b3 4a rex mov $0x4ab34cb0, %edi 4c rex.WR 40 rex 4f bf b9 bf bf 4c b3 47 b0 bf rex.WRXB movabs $0xbfb047b34cbfbfb9, %r15 40 b0 40 rex mov $0x40, %al 4a b8 4c b9 40 b0 47 b8 b3 47 rex.WX movabs $0x47b3b847b040b94c, %rax bf b8 40 4a 47 mov $0x474a40b8, %edi 4c rex.WR 40 rex 40 b0 4c rex mov $0x4c, %al b0 bf mov $0xbf, %al 40 bf b8 b0 4c b9 rex mov $0xb94cb0b8, %edi

jared-hughes/defcpu

559

tests/disassembly/sources/019_rep.s

f3 ae repz scas %es:(%rdi), %al f2 ae repnz scas %es:(%rdi), %al f2 03 00 repnz add (%rax), %eax 03 00 add (%rax), %eax 66 f2 67 f3 00 00 data16 repnz repz add %al, (%eax) 67 f2 ae repnz scas %es:(%edi), %al f2 ae repnz scas %es:(%rdi), %al 66 f2 49 data16 repnz rex.WB f2 67 ae repnz scas %es:(%edi), %al 66 f2 49 data16 repnz rex.WB f2 ae repnz scas %es:(%rdi), %al 66 f2 67 49 ae data16 repnz rex.WB scas %es:(%edi), %al

jared-hughes/defcpu

150

tests/disassembly/sources/007_mov_rm_imm.s

48 c7 c0 12 34 56 78 mov $0x78563412, %rax c6 c0 12 mov $0x12, %al 66 67 88 23 data16 mov %ah, (%ebx)

jared-hughes/defcpu

6,268

tests/disassembly/sources/017_pop.s

58 pop %rax 59 pop %rcx 5a pop %rdx 5b pop %rbx 5c pop %rsp 5d pop %rbp 5e pop %rsi 5f pop %rdi 66 58 pop %ax 66 59 pop %cx 66 5a pop %dx 66 5b pop %bx 66 5c pop %sp 66 5d pop %bp 66 5e pop %si 66 5f pop %di 41 58 pop %r8 41 59 pop %r9 41 5a pop %r10 41 5b pop %r11 41 5c pop %r12 41 5d pop %r13 41 5e pop %r14 41 5f pop %r15 66 41 58 pop %r8w 66 41 59 pop %r9w 66 41 5a pop %r10w 66 41 5b pop %r11w 66 41 5c pop %r12w 66 41 5d pop %r13w 66 41 5e pop %r14w 66 41 5f pop %r15w 48 58 rex.W pop %rax 48 59 rex.W pop %rcx 48 5a rex.W pop %rdx 48 5b rex.W pop %rbx 48 5c rex.W pop %rsp 48 5d rex.W pop %rbp 48 5e rex.W pop %rsi 48 5f rex.W pop %rdi 66 48 58 data16 rex.W pop %rax 66 48 59 data16 rex.W pop %rcx 66 48 5a data16 rex.W pop %rdx 66 48 5b data16 rex.W pop %rbx 66 48 5c data16 rex.W pop %rsp 66 48 5d data16 rex.W pop %rbp 66 48 5e data16 rex.W pop %rsi 66 48 5f data16 rex.W pop %rdi 49 58 rex.WB pop %r8 49 59 rex.WB pop %r9 49 5a rex.WB pop %r10 49 5b rex.WB pop %r11 49 5c rex.WB pop %r12 49 5d rex.WB pop %r13 49 5e rex.WB pop %r14 49 5f rex.WB pop %r15 66 49 58 data16 rex.WB pop %r8 66 49 59 data16 rex.WB pop %r9 66 49 5a data16 rex.WB pop %r10 66 49 5b data16 rex.WB pop %r11 66 49 5c data16 rex.WB pop %r12 66 49 5d data16 rex.WB pop %r13 66 49 5e data16 rex.WB pop %r14 66 49 5f data16 rex.WB pop %r15 8f 00 pop (%rax) 8f 04 f4 pop (%rsp, %rsi, 8) 8f 05 f4 f4 f4 f4 pop -0xb0b0b0c(%rip) 8f 06 pop (%rsi) 8f 40 f4 pop -0xc(%rax) 8f c3 pop %rbx 8f c4 pop %rsp 41 8f 00 pop (%r8) 41 8f 04 12 pop (%r10, %rdx, 1) 41 8f 05 12 34 56 78 pop 0x78563412(%rip) 41 8f 06 pop (%r14) 66 8f 00 popw (%rax) 66 8f 04 f4 popw (%rsp, %rsi, 8) 66 8f 05 f4 f4 f4 f4 popw -0xb0b0b0c(%rip) 66 8f 06 popw (%rsi) 66 8f 40 f4 popw -0xc(%rax) 66 8f c3 pop %bx 66 8f c4 pop %sp 66 41 8f 00 popw (%r8) 66 41 8f 04 12 popw (%r10, %rdx, 1) 66 41 8f 05 12 34 56 78 popw 0x78563412(%rip) 66 41 8f 06 popw (%r14) 67 8f 00 pop (%eax) 67 8f 04 f4 pop (%esp, %esi, 8) 67 8f 05 f4 f4 f4 f4 pop -0xb0b0b0c(%eip) 67 8f 06 pop (%esi) 67 8f 40 f4 pop -0xc(%eax) 67 8f c3 addr32 pop %rbx 67 8f c4 addr32 pop %rsp 67 41 8f 00 pop (%r8d) 67 41 8f 04 12 pop (%r10d, %edx, 1) 67 41 8f 05 12 34 56 78 pop 0x78563412(%eip) 67 41 8f 06 pop (%r14d) 66 67 8f 00 popw (%eax) 66 67 8f 04 f4 popw (%esp, %esi, 8) 66 67 8f 05 f4 f4 f4 f4 popw -0xb0b0b0c(%eip) 66 67 8f 06 popw (%esi) 66 67 8f 40 f4 popw -0xc(%eax) 66 67 8f c3 addr32 pop %bx 66 67 8f c4 addr32 pop %sp 66 67 41 8f 00 popw (%r8d) 66 67 41 8f 04 12 popw (%r10d, %edx, 1) 66 67 41 8f 05 12 34 56 78 popw 0x78563412(%eip) 66 67 41 8f 06 popw (%r14d) 66 67 48 8f 00 data16 rex.W pop (%eax) 66 67 48 8f 04 f4 data16 rex.W pop (%esp, %esi, 8) 66 67 48 8f 05 f4 f4 f4 f4 data16 rex.W pop -0xb0b0b0c(%eip) 48 8f 06 rex.W pop (%rsi) 48 8f 40 f4 rex.W pop -0xc(%rax) 48 8f c3 rex.W pop %rbx 48 8f c4 rex.W pop %rsp 49 8f 00 rex.WB pop (%r8) 49 8f 04 f4 rex.WB pop (%r12, %rsi, 8) 49 8f 05 f4 f4 f4 f4 rex.WB pop -0xb0b0b0c(%rip) 49 8f 06 rex.WB pop (%r14) 49 8f 40 f4 rex.WB pop -0xc(%r8) 49 8f c3 rex.WB pop %r11 49 8f c4 rex.WB pop %r12 67 48 8f 06 rex.W pop (%esi) 67 48 8f 40 f4 rex.W pop -0xc(%eax) 67 48 8f c3 addr32 rex.W pop %rbx 67 48 8f c4 addr32 rex.W pop %rsp 67 49 8f 00 rex.WB pop (%r8d) 67 49 8f 04 f4 rex.WB pop (%r12d, %esi, 8) 67 49 8f 05 f4 f4 f4 f4 rex.WB pop -0xb0b0b0c(%eip) 67 49 8f 06 rex.WB pop (%r14d) 67 49 8f 40 f4 rex.WB pop -0xc(%r8d) 67 49 8f c3 addr32 rex.WB pop %r11 67 49 8f c4 addr32 rex.WB pop %r12 9d popf 66 9d popfw 67 9d addr32 popf 66 67 9d addr32 popfw 48 9d rex.W popf 66 48 9d data16 rex.W popf

jared-hughes/defcpu

1,113

tests/disassembly/sources/003_mov32.s

b8 12 34 56 78 mov $0x78563412, %eax b9 12 34 56 78 mov $0x78563412, %ecx ba 12 34 56 78 mov $0x78563412, %edx bb 12 34 56 78 mov $0x78563412, %ebx bc 12 34 56 78 mov $0x78563412, %esp bd 12 34 56 78 mov $0x78563412, %ebp be 12 34 56 78 mov $0x78563412, %esi bf 12 34 56 78 mov $0x78563412, %edi 41 b8 12 34 56 78 mov $0x78563412, %r8d 41 b9 12 34 56 78 mov $0x78563412, %r9d 41 ba 12 34 56 78 mov $0x78563412, %r10d 41 bb 12 34 56 78 mov $0x78563412, %r11d 41 bc 12 34 56 78 mov $0x78563412, %r12d 41 bd 12 34 56 78 mov $0x78563412, %r13d 41 be 12 34 56 78 mov $0x78563412, %r14d 41 bf 12 34 56 78 mov $0x78563412, %r15d 40 b8 12 34 56 78 rex mov $0x78563412, %eax 41 b9 12 34 56 78 mov $0x78563412, %r9d 42 ba 12 34 56 78 rex.X mov $0x78563412, %edx 43 bb 12 34 56 78 rex.XB mov $0x78563412, %r11d 44 bc 12 34 56 78 rex.R mov $0x78563412, %esp 45 bd 12 34 56 78 rex.RB mov $0x78563412, %r13d 46 be 12 34 56 78 rex.RX mov $0x78563412, %esi 47 bf 12 34 56 78 rex.RXB mov $0x78563412, %r15d

jared-hughes/defcpu

6,881

tests/disassembly/sources/014_jcc.s

70 82 jo 0x3fff84 70 12 jo 0x400016 71 12 jno 0x400018 72 12 jb 0x40001a 73 12 jae 0x40001c 74 12 je 0x40001e 75 12 jne 0x400020 76 12 jbe 0x400022 77 12 ja 0x400024 78 12 js 0x400026 79 12 jns 0x400028 7a 12 jp 0x40002a 7b 12 jnp 0x40002c 7c 12 jl 0x40002e 7d 12 jge 0x400030 7e 12 jle 0x400032 7f 12 jg 0x400034 e3 12 jrcxz 0x400036 0f 80 12 34 56 88 jo 0xffffffff8896343c 0f 80 12 34 56 78 jo 0x78963442 0f 81 12 34 56 78 jno 0x78963448 0f 82 12 34 56 78 jb 0x7896344e 0f 83 12 34 56 78 jae 0x78963454 0f 84 12 34 56 78 je 0x7896345a 0f 85 12 34 56 78 jne 0x78963460 0f 86 12 34 56 78 jbe 0x78963466 0f 87 12 34 56 78 ja 0x7896346c 0f 89 12 34 56 78 jns 0x78963472 0f 88 12 34 56 78 js 0x78963478 0f 8a 12 34 56 78 jp 0x7896347e 0f 8b 12 34 56 78 jnp 0x78963484 0f 8c 12 34 56 78 jl 0x7896348a 0f 8d 12 34 56 78 jge 0x78963490 0f 8e 12 34 56 78 jle 0x78963496 0f 8f 12 34 56 78 jg 0x7896349c 66 70 82 data16 jo 0x40000f 66 70 12 data16 jo 0x4000a2 66 71 12 data16 jno 0x4000a5 66 72 12 data16 jb 0x4000a8 66 73 12 data16 jae 0x4000ab 66 74 12 data16 je 0x4000ae 66 75 12 data16 jne 0x4000b1 66 76 12 data16 jbe 0x4000b4 66 77 12 data16 ja 0x4000b7 66 78 12 data16 js 0x4000ba 66 79 12 data16 jns 0x4000bd 66 7a 12 data16 jp 0x4000c0 66 7b 12 data16 jnp 0x4000c3 66 7c 12 data16 jl 0x4000c6 66 7d 12 data16 jge 0x4000c9 66 7e 12 data16 jle 0x4000cc 66 7f 12 data16 jg 0x4000cf 66 e3 12 data16 jrcxz 0x4000d2 66 0f 80 12 34 jo 0x34d7 66 0f 80 12 34 jo 0x34dc 66 0f 81 12 34 jno 0x34e1 66 0f 82 12 34 jb 0x34e6 66 0f 83 12 34 jae 0x34eb 66 0f 84 12 34 je 0x34f0 66 0f 85 12 34 jne 0x34f5 66 0f 86 12 34 jbe 0x34fa 66 0f 87 12 34 ja 0x34ff 66 0f 89 12 34 jns 0x3504 66 0f 88 12 34 js 0x3509 66 0f 8a 12 34 jp 0x350e 66 0f 8b 12 34 jnp 0x3513 66 0f 8c 12 34 jl 0x3518 66 0f 8d 12 34 jge 0x351d 66 0f 8e 12 34 jle 0x3522 66 0f 8f 12 34 jg 0x3527 67 70 82 addr32 jo 0x40009a 67 70 12 addr32 jo 0x40012d 67 71 12 addr32 jno 0x400130 67 72 12 addr32 jb 0x400133 67 73 12 addr32 jae 0x400136 67 74 12 addr32 je 0x400139 67 75 12 addr32 jne 0x40013c 67 76 12 addr32 jbe 0x40013f 67 77 12 addr32 ja 0x400142 67 78 12 addr32 js 0x400145 67 79 12 addr32 jns 0x400148 67 7a 12 addr32 jp 0x40014b 67 7b 12 addr32 jnp 0x40014e 67 7c 12 addr32 jl 0x400151 67 7d 12 addr32 jge 0x400154 67 7e 12 addr32 jle 0x400157 67 7f 12 addr32 jg 0x40015a 67 e3 12 jecxz 0x40015d 67 0f 80 12 34 56 78 addr32 jo 0x78963564 67 0f 80 12 34 56 78 addr32 jo 0x7896356b 67 0f 81 12 34 56 78 addr32 jno 0x78963572 67 0f 82 12 34 56 78 addr32 jb 0x78963579 67 0f 83 12 34 56 78 addr32 jae 0x78963580 67 0f 84 12 34 56 78 addr32 je 0x78963587 67 0f 85 12 34 56 78 addr32 jne 0x7896358e 67 0f 86 12 34 56 78 addr32 jbe 0x78963595 67 0f 87 12 34 56 78 addr32 ja 0x7896359c 67 0f 89 12 34 56 78 addr32 jns 0x789635a3 67 0f 88 12 34 56 78 addr32 js 0x789635aa 67 0f 8a 12 34 56 78 addr32 jp 0x789635b1 67 0f 8b 12 34 56 78 addr32 jnp 0x789635b8 67 0f 8c 12 34 56 78 addr32 jl 0x789635bf 67 0f 8d 12 34 56 78 addr32 jge 0x789635c6 67 0f 8e 12 34 56 78 addr32 jle 0x789635cd 67 0f 8f 12 34 56 78 addr32 jg 0x789635d4 66 67 70 82 data16 addr32 jo 0x400148 66 67 70 12 data16 addr32 jo 0x4001dc 66 67 71 12 data16 addr32 jno 0x4001e0 66 67 72 12 data16 addr32 jb 0x4001e4 66 67 73 12 data16 addr32 jae 0x4001e8 66 67 74 12 data16 addr32 je 0x4001ec 66 67 75 12 data16 addr32 jne 0x4001f0 66 67 76 12 data16 addr32 jbe 0x4001f4 66 67 77 12 data16 addr32 ja 0x4001f8 66 67 78 12 data16 addr32 js 0x4001fc 66 67 79 12 data16 addr32 jns 0x400200 66 67 7a 12 data16 addr32 jp 0x400204 66 67 7b 12 data16 addr32 jnp 0x400208 66 67 7c 12 data16 addr32 jl 0x40020c 66 67 7d 12 data16 addr32 jge 0x400210 66 67 7e 12 data16 addr32 jle 0x400214 66 67 7f 12 data16 addr32 jg 0x400218 66 67 e3 12 data16 jecxz 0x40021c 66 67 0f 80 12 34 addr32 jo 0x3622 66 67 0f 80 12 34 addr32 jo 0x3628 66 67 0f 81 12 34 addr32 jno 0x362e 66 67 0f 82 12 34 addr32 jb 0x3634 66 67 0f 83 12 34 addr32 jae 0x363a 66 67 0f 84 12 34 addr32 je 0x3640 66 67 0f 85 12 34 addr32 jne 0x3646 66 67 0f 86 12 34 addr32 jbe 0x364c 66 67 0f 87 12 34 addr32 ja 0x3652 66 67 0f 89 12 34 addr32 jns 0x3658 66 67 0f 88 12 34 addr32 js 0x365e 66 67 0f 8a 12 34 addr32 jp 0x3664 66 67 0f 8b 12 34 addr32 jnp 0x366a 66 67 0f 8c 12 34 addr32 jl 0x3670 66 67 0f 8d 12 34 addr32 jge 0x3676 66 67 0f 8e 12 34 addr32 jle 0x367c 66 67 0f 8f 12 34 addr32 jg 0x3682 41 70 82 rex.B jo 0x4001f5 41 e3 12 rex.B jrcxz 0x400288 48 70 82 rex.W jo 0x4001fb 48 e3 12 rex.W jrcxz 0x40028e 49 70 82 rex.WB jo 0x400201 49 e3 12 rex.WB jrcxz 0x400294

jared-hughes/defcpu

1,560

tests/disassembly/sources/004_mov64.s

48 b8 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rax 48 b9 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rcx 48 ba 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rdx 48 bb 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rbx 48 bc 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rsp 48 bd 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rbp 48 be 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rsi 48 bf 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %rdi 49 b8 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r8 49 b9 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r9 49 ba 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r10 49 bb 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r11 49 bc 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r12 49 bd 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r13 49 be 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r14 49 bf 12 34 56 78 9a bc de ff movabs $0xffdebc9a78563412, %r15 4a b8 12 34 56 78 9a bc de ff rex.WX movabs $0xffdebc9a78563412, %rax 4b b8 12 34 56 78 9a bc de ff rex.WXB movabs $0xffdebc9a78563412, %r8 4c b8 12 34 56 78 9a bc de ff rex.WR movabs $0xffdebc9a78563412, %rax 4d b8 12 34 56 78 9a bc de ff rex.WRB movabs $0xffdebc9a78563412, %r8 4e b8 12 34 56 78 9a bc de ff rex.WRX movabs $0xffdebc9a78563412, %rax 4f b8 12 34 56 78 9a bc de ff rex.WRXB movabs $0xffdebc9a78563412, %r8

jared-hughes/defcpu

3,676

tests/disassembly/sources/015_jmp.s

eb 82 jmp 0x3fff84 eb 12 jmp 0x400016 e8 12 34 56 88 call 0xffffffff8896341b e9 12 34 56 88 jmp 0xffffffff88963420 e8 12 34 56 78 call 0x78963425 e9 12 34 56 78 jmp 0x7896342a 66 eb 82 data16 jmp 0x3fff9d 66 eb 12 data16 jmp 0x400030 67 eb 82 addr32 jmp 0x3fffa3 67 eb 12 addr32 jmp 0x400036 66 67 eb 82 data16 addr32 jmp 0x3fffaa 66 67 eb 12 data16 addr32 jmp 0x40003e 41 eb 82 rex.B jmp 0x3fffb1 48 eb 82 rex.W jmp 0x3fffb4 49 eb 82 rex.WB jmp 0x3fffb7 41 e8 12 34 56 78 rex.B call 0x7896344d 41 e9 12 34 56 78 rex.B jmp 0x78963453 48 e8 12 34 56 78 rex.W call 0x78963459 48 e9 12 34 56 78 rex.W jmp 0x7896345f 49 e8 12 34 56 78 rex.WB call 0x78963465 49 e9 12 34 56 78 rex.WB jmp 0x7896346b ff 20 jmp *(%rax) ff 24 18 jmp *(%rax, %rbx, 1) ff 24 58 jmp *(%rax, %rbx, 2) ff 24 98 jmp *(%rax, %rbx, 4) ff 24 d8 jmp *(%rax, %rbx, 8) 67 ff 24 18 jmp *(%eax, %ebx, 1) 67 ff 24 58 jmp *(%eax, %ebx, 2) 67 ff 24 98 jmp *(%eax, %ebx, 4) 67 ff 24 d8 jmp *(%eax, %ebx, 8) 43 ff 24 23 jmp *(%r11, %r12, 1) 43 ff 24 63 jmp *(%r11, %r12, 2) 43 ff 24 a3 jmp *(%r11, %r12, 4) 43 ff 24 e3 jmp *(%r11, %r12, 8) 67 43 ff 24 23 jmp *(%r11d, %r12d, 1) 67 43 ff 24 63 jmp *(%r11d, %r12d, 2) 67 43 ff 24 a3 jmp *(%r11d, %r12d, 4) 67 43 ff 24 e3 jmp *(%r11d, %r12d, 8) ff 64 18 79 jmp *0x79(%rax, %rbx, 1) ff 64 58 80 jmp *-0x80(%rax, %rbx, 2) ff a4 98 80 00 00 00 jmp *0x80(%rax, %rbx, 4) ff a4 d8 7f ff ff ff jmp *-0x81(%rax, %rbx, 8) ff 24 1c jmp *(%rsp, %rbx, 1) ff 25 12 34 56 78 jmp *0x78563412(%rip) 67 ff 25 12 34 56 78 jmp *0x78563412(%eip) ff 24 20 jmp *(%rax, %riz, 1) ff a4 20 12 34 56 78 jmp *0x78563412(%rax, %riz, 1) ff 24 20 jmp *(%rax, %riz, 1) ff 24 21 jmp *(%rcx, %riz, 1) ff 24 22 jmp *(%rdx, %riz, 1) ff 24 23 jmp *(%rbx, %riz, 1) ff 24 24 jmp *(%rsp) ff 24 25 12 34 56 78 jmp *0x78563412 ff 24 65 12 34 56 78 jmp *0x78563412(, %riz, 2) ff 24 a5 12 34 56 78 jmp *0x78563412(, %riz, 4) ff 24 e5 12 34 56 78 jmp *0x78563412(, %riz, 8) ff 24 26 jmp *(%rsi, %riz, 1) ff 24 27 jmp *(%rdi, %riz, 1) ff 24 64 jmp *(%rsp, %riz, 2) ff 24 a4 jmp *(%rsp, %riz, 4) ff 24 e4 jmp *(%rsp, %riz, 8) ff 24 ac jmp *(%rsp, %rbp, 4) ff 64 20 3a jmp *0x3a(%rax, %riz, 1) ff 64 64 3a jmp *0x3a(%rsp, %riz, 2) ff 64 a4 3a jmp *0x3a(%rsp, %riz, 4) ff 64 e4 3a jmp *0x3a(%rsp, %riz, 8) ff 64 25 3a jmp *0x3a(%rbp, %riz, 1) ff 64 65 3a jmp *0x3a(%rbp, %riz, 2) ff 64 a5 3a jmp *0x3a(%rbp, %riz, 4) ff 64 e5 3a jmp *0x3a(%rbp, %riz, 8) c3 ret

jared-hughes/defcpu

3,072

tests/disassembly/sources/008_prefixes.s

b0 12 mov $0x12, %al 66 b0 12 data16 mov $0x12, %al 67 b0 12 addr32 mov $0x12, %al 66 67 b0 12 data16 addr32 mov $0x12, %al 66 66 67 67 b0 12 data16 data16 addr32 addr32 mov $0x12, %al 67 67 66 66 b0 12 addr32 addr32 data16 data16 mov $0x12, %al 67 66 67 66 b0 12 addr32 data16 addr32 data16 mov $0x12, %al 88 23 mov %ah, (%rbx) 66 88 23 data16 mov %ah, (%rbx) 67 88 23 mov %ah, (%ebx) 66 67 88 23 data16 mov %ah, (%ebx) 66 66 67 67 88 23 data16 data16 addr32 mov %ah, (%ebx) 67 67 66 66 88 23 addr32 data16 data16 mov %ah, (%ebx) 67 66 67 66 88 23 addr32 data16 data16 mov %ah, (%ebx) 40 88 23 mov %spl, (%rbx) 40 rex 66 88 23 data16 mov %ah, (%rbx) 40 rex 67 88 23 mov %ah, (%ebx) 40 rex 66 67 88 23 data16 mov %ah, (%ebx) 40 rex 66 66 67 67 88 23 data16 data16 addr32 mov %ah, (%ebx) 40 rex 67 67 66 66 88 23 addr32 data16 data16 mov %ah, (%ebx) 40 rex 67 66 67 66 88 23 addr32 data16 data16 mov %ah, (%ebx) 40 88 23 mov %spl, (%rbx) 66 40 88 23 data16 mov %spl, (%rbx) 67 40 88 23 mov %spl, (%ebx) 66 67 40 88 23 data16 mov %spl, (%ebx) 66 66 67 67 40 88 23 data16 data16 addr32 mov %spl, (%ebx) 67 67 66 66 40 88 23 addr32 data16 data16 mov %spl, (%ebx) 67 66 67 66 40 88 23 addr32 data16 data16 mov %spl, (%ebx) 48 88 23 rex.W mov %spl, (%rbx) 66 48 88 23 data16 rex.W mov %spl, (%rbx) 67 48 88 23 rex.W mov %spl, (%ebx) 66 67 48 88 23 data16 rex.W mov %spl, (%ebx) 66 66 67 67 48 88 23 data16 data16 addr32 rex.W mov %spl, (%ebx) 67 67 66 66 48 88 23 addr32 data16 data16 rex.W mov %spl, (%ebx) 67 66 67 66 48 88 23 addr32 data16 data16 rex.W mov %spl, (%ebx) 41 88 23 mov %spl, (%r11) 66 41 88 23 data16 mov %spl, (%r11) 67 41 88 23 mov %spl, (%r11d) 66 67 41 88 23 data16 mov %spl, (%r11d) 66 66 67 67 41 88 23 data16 data16 addr32 mov %spl, (%r11d) 67 67 66 66 41 88 23 addr32 data16 data16 mov %spl, (%r11d) 67 66 67 66 41 88 23 addr32 data16 data16 mov %spl, (%r11d) 49 88 23 rex.WB mov %spl, (%r11) 66 49 88 23 data16 rex.WB mov %spl, (%r11) 67 49 88 23 rex.WB mov %spl, (%r11d) 66 67 49 88 23 data16 rex.WB mov %spl, (%r11d) 66 66 67 67 49 88 23 data16 data16 addr32 rex.WB mov %spl, (%r11d) 67 67 66 66 49 88 23 addr32 data16 data16 rex.WB mov %spl, (%r11d) 67 66 67 66 49 88 23 addr32 data16 data16 rex.WB mov %spl, (%r11d)

jared-hughes/defcpu

7,726

tests/disassembly/sources/016_push.s

6a 12 push $0x12 6a a2 push $0xffffffffffffffa2 66 6a 12 pushw $0x12 67 6a 12 addr32 push $0x12 66 67 6a 12 addr32 pushw $0x12 68 12 34 56 78 push $0x78563412 68 a2 b4 c6 d8 push $0xffffffffd8c6b4a2 66 68 12 34 pushw $0x3412 66 68 a2 b4 pushw $0xb4a2 67 68 12 34 56 78 addr32 push $0x78563412 67 68 a2 b4 c6 d8 addr32 push $0xffffffffd8c6b4a2 67 66 68 12 34 addr32 pushw $0x3412 67 66 68 a2 b4 addr32 pushw $0xb4a2 48 6a 12 rex.W push $0x12 48 6a a2 rex.W push $0xffffffffffffffa2 66 48 6a 12 data16 rex.W push $0x12 67 48 6a 12 addr32 rex.W push $0x12 66 67 48 6a 12 data16 addr32 rex.W push $0x12 48 68 12 34 56 78 rex.W push $0x78563412 48 68 a2 b4 c6 d8 rex.W push $0xffffffffd8c6b4a2 66 48 68 12 34 56 78 data16 rex.W push $0x78563412 66 48 68 a2 b4 c6 d8 data16 rex.W push $0xffffffffd8c6b4a2 67 48 68 12 34 56 78 addr32 rex.W push $0x78563412 67 48 68 a2 b4 c6 d8 addr32 rex.W push $0xffffffffd8c6b4a2 67 66 48 68 12 34 56 78 addr32 data16 rex.W push $0x78563412 67 66 48 68 a2 b4 c6 d8 addr32 data16 rex.W push $0xffffffffd8c6b4a2 50 push %rax 51 push %rcx 52 push %rdx 53 push %rbx 54 push %rsp 55 push %rbp 56 push %rsi 57 push %rdi 66 50 push %ax 66 51 push %cx 66 52 push %dx 66 53 push %bx 66 54 push %sp 66 55 push %bp 66 56 push %si 66 57 push %di 41 50 push %r8 41 51 push %r9 41 52 push %r10 41 53 push %r11 41 54 push %r12 41 55 push %r13 41 56 push %r14 41 57 push %r15 66 41 50 push %r8w 66 41 51 push %r9w 66 41 52 push %r10w 66 41 53 push %r11w 66 41 54 push %r12w 66 41 55 push %r13w 66 41 56 push %r14w 66 41 57 push %r15w 48 50 rex.W push %rax 48 51 rex.W push %rcx 48 52 rex.W push %rdx 48 53 rex.W push %rbx 48 54 rex.W push %rsp 48 55 rex.W push %rbp 48 56 rex.W push %rsi 48 57 rex.W push %rdi 66 48 50 data16 rex.W push %rax 66 48 51 data16 rex.W push %rcx 66 48 52 data16 rex.W push %rdx 66 48 53 data16 rex.W push %rbx 66 48 54 data16 rex.W push %rsp 66 48 55 data16 rex.W push %rbp 66 48 56 data16 rex.W push %rsi 66 48 57 data16 rex.W push %rdi 49 50 rex.WB push %r8 49 51 rex.WB push %r9 49 52 rex.WB push %r10 49 53 rex.WB push %r11 49 54 rex.WB push %r12 49 55 rex.WB push %r13 49 56 rex.WB push %r14 49 57 rex.WB push %r15 66 49 50 data16 rex.WB push %r8 66 49 51 data16 rex.WB push %r9 66 49 52 data16 rex.WB push %r10 66 49 53 data16 rex.WB push %r11 66 49 54 data16 rex.WB push %r12 66 49 55 data16 rex.WB push %r13 66 49 56 data16 rex.WB push %r14 66 49 57 data16 rex.WB push %r15 ff 30 push (%rax) ff 34 f4 push (%rsp, %rsi, 8) ff 35 f4 f4 f4 f4 push -0xb0b0b0c(%rip) ff 36 push (%rsi) ff 70 f4 push -0xc(%rax) ff f3 push %rbx ff f4 push %rsp 41 ff 30 push (%r8) 41 ff 34 12 push (%r10, %rdx, 1) 41 ff 35 12 34 56 78 push 0x78563412(%rip) 41 ff 36 push (%r14) 66 ff 30 pushw (%rax) 66 ff 34 f4 pushw (%rsp, %rsi, 8) 66 ff 35 f4 f4 f4 f4 pushw -0xb0b0b0c(%rip) 66 ff 36 pushw (%rsi) 66 ff 70 f4 pushw -0xc(%rax) 66 ff f3 push %bx 66 ff f4 push %sp 66 41 ff 30 pushw (%r8) 66 41 ff 34 12 pushw (%r10, %rdx, 1) 66 41 ff 35 12 34 56 78 pushw 0x78563412(%rip) 66 41 ff 36 pushw (%r14) 67 ff 30 push (%eax) 67 ff 34 f4 push (%esp, %esi, 8) 67 ff 35 f4 f4 f4 f4 push -0xb0b0b0c(%eip) 67 ff 36 push (%esi) 67 ff 70 f4 push -0xc(%eax) 67 ff f3 addr32 push %rbx 67 ff f4 addr32 push %rsp 67 41 ff 30 push (%r8d) 67 41 ff 34 12 push (%r10d, %edx, 1) 67 41 ff 35 12 34 56 78 push 0x78563412(%eip) 67 41 ff 36 push (%r14d) 66 67 ff 30 pushw (%eax) 66 67 ff 34 f4 pushw (%esp, %esi, 8) 66 67 ff 35 f4 f4 f4 f4 pushw -0xb0b0b0c(%eip) 66 67 ff 36 pushw (%esi) 66 67 ff 70 f4 pushw -0xc(%eax) 66 67 ff f3 addr32 push %bx 66 67 ff f4 addr32 push %sp 66 67 41 ff 30 pushw (%r8d) 66 67 41 ff 34 12 pushw (%r10d, %edx, 1) 66 67 41 ff 35 12 34 56 78 pushw 0x78563412(%eip) 66 67 41 ff 36 pushw (%r14d) 66 67 48 ff 30 data16 rex.W push (%eax) 66 67 48 ff 34 f4 data16 rex.W push (%esp, %esi, 8) 66 67 48 ff 35 f4 f4 f4 f4 data16 rex.W push -0xb0b0b0c(%eip) 48 ff 36 rex.W push (%rsi) 48 ff 70 f4 rex.W push -0xc(%rax) 48 ff f3 rex.W push %rbx 48 ff f4 rex.W push %rsp 49 ff 30 rex.WB push (%r8) 49 ff 34 f4 rex.WB push (%r12, %rsi, 8) 49 ff 35 f4 f4 f4 f4 rex.WB push -0xb0b0b0c(%rip) 49 ff 36 rex.WB push (%r14) 49 ff 70 f4 rex.WB push -0xc(%r8) 49 ff f3 rex.WB push %r11 49 ff f4 rex.WB push %r12 67 48 ff 36 rex.W push (%esi) 67 48 ff 70 f4 rex.W push -0xc(%eax) 67 48 ff f3 addr32 rex.W push %rbx 67 48 ff f4 addr32 rex.W push %rsp 67 49 ff 30 rex.WB push (%r8d) 67 49 ff 34 f4 rex.WB push (%r12d, %esi, 8) 67 49 ff 35 f4 f4 f4 f4 rex.WB push -0xb0b0b0c(%eip) 67 49 ff 36 rex.WB push (%r14d) 67 49 ff 70 f4 rex.WB push -0xc(%r8d) 67 49 ff f3 addr32 rex.WB push %r11 67 49 ff f4 addr32 rex.WB push %r12 9c pushf 66 9c pushfw 67 9c addr32 pushf 66 67 9c addr32 pushfw 48 9c rex.W pushf 66 48 9c data16 rex.W pushf

jared-hughes/defcpu

1,180

tests/disassembly/sources/025_bswap.s

0f c8 bswap %eax 0f c9 bswap %ecx 0f ca bswap %edx 0f cb bswap %ebx 0f cc bswap %esp 0f cd bswap %ebp 0f ce bswap %esi 0f cf bswap %edi 40 0f c8 rex bswap %eax 40 0f c9 rex bswap %ecx 40 0f ca rex bswap %edx 40 0f cb rex bswap %ebx 40 0f cc rex bswap %esp 40 0f cd rex bswap %ebp 40 0f ce rex bswap %esi 40 0f cf rex bswap %edi 41 0f c8 bswap %r8d 41 0f c9 bswap %r9d 41 0f ca bswap %r10d 41 0f cb bswap %r11d 41 0f cc bswap %r12d 41 0f cd bswap %r13d 41 0f ce bswap %r14d 41 0f cf bswap %r15d 48 0f c8 bswap %rax 48 0f c9 bswap %rcx 48 0f ca bswap %rdx 48 0f cb bswap %rbx 48 0f cc bswap %rsp 48 0f cd bswap %rbp 48 0f ce bswap %rsi 48 0f cf bswap %rdi 48 0f c8 bswap %rax 48 0f c9 bswap %rcx 48 0f ca bswap %rdx 48 0f cb bswap %rbx 48 0f cc bswap %rsp 48 0f cd bswap %rbp 48 0f ce bswap %rsi 48 0f cf bswap %rdi 49 0f c8 bswap %r8 49 0f c9 bswap %r9 49 0f ca bswap %r10 49 0f cb bswap %r11 49 0f cc bswap %r12 49 0f cd bswap %r13 49 0f ce bswap %r14 49 0f cf bswap %r15

jared-hughes/defcpu

4,971

tests/disassembly/sources/020_imul.s

f6 28 imulb (%rax) f6 e8 imul %al 66 f7 28 imulw (%rax) 66 f7 e8 imul %ax f7 28 imull (%rax) f7 e8 imul %eax 48 f7 28 imulq (%rax) 48 f7 e8 imul %rax 6b 23 12 imul $0x12, (%rbx), %esp 66 0f af 23 imul (%rbx), %sp 67 0f af 23 imul (%ebx), %esp 66 67 0f af 23 imul (%ebx), %sp 40 0f af 23 rex imul (%rbx), %esp 67 40 0f af 23 rex imul (%ebx), %esp 66 40 0f af 23 rex imul (%rbx), %sp 66 67 40 0f af 23 rex imul (%ebx), %sp 41 0f af 23 imul (%r11), %esp 67 41 0f af 23 imul (%r11d), %esp 66 41 0f af 23 imul (%r11), %sp 66 67 41 0f af 23 imul (%r11d), %sp 48 0f af 23 imul (%rbx), %rsp 67 48 0f af 23 imul (%ebx), %rsp 66 48 0f af 23 data16 imul (%rbx), %rsp 66 67 48 0f af 23 data16 imul (%ebx), %rsp 6b 23 12 imul $0x12, (%rbx), %esp 66 6b 23 12 imul $0x12, (%rbx), %sp 67 6b 23 12 imul $0x12, (%ebx), %esp 66 67 6b 23 12 imul $0x12, (%ebx), %sp 40 6b 23 12 rex imul $0x12, (%rbx), %esp 67 40 6b 23 12 rex imul $0x12, (%ebx), %esp 66 40 6b 23 12 rex imul $0x12, (%rbx), %sp 66 67 40 6b 23 12 rex imul $0x12, (%ebx), %sp 41 6b 23 12 imul $0x12, (%r11), %esp 67 41 6b 23 12 imul $0x12, (%r11d), %esp 66 41 6b 23 12 imul $0x12, (%r11), %sp 66 67 41 6b 23 12 imul $0x12, (%r11d), %sp 48 6b 23 12 imul $0x12, (%rbx), %rsp 67 48 6b 23 12 imul $0x12, (%ebx), %rsp 66 48 6b 23 12 data16 imul $0x12, (%rbx), %rsp 66 67 48 6b 23 12 data16 imul $0x12, (%ebx), %rsp 69 23 12 34 56 78 imul $0x78563412, (%rbx), %esp 66 69 23 12 34 imul $0x3412, (%rbx), %sp 67 69 23 12 34 56 78 imul $0x78563412, (%ebx), %esp 66 67 69 23 12 34 imul $0x3412, (%ebx), %sp 40 69 23 12 34 56 78 rex imul $0x78563412, (%rbx), %esp 67 40 69 23 12 34 56 78 rex imul $0x78563412, (%ebx), %esp 66 40 69 23 12 34 rex imul $0x3412, (%rbx), %sp 66 67 40 69 23 12 34 rex imul $0x3412, (%ebx), %sp 41 69 23 12 34 56 78 imul $0x78563412, (%r11), %esp 67 41 69 23 12 34 56 78 imul $0x78563412, (%r11d), %esp 66 41 69 23 12 34 imul $0x3412, (%r11), %sp 66 67 41 69 23 12 34 imul $0x3412, (%r11d), %sp 48 69 23 12 34 56 78 imul $0x78563412, (%rbx), %rsp 67 48 69 23 12 34 56 78 imul $0x78563412, (%ebx), %rsp 66 48 69 23 12 34 56 78 data16 imul $0x78563412, (%rbx), %rsp 66 67 48 69 23 12 34 56 78 data16 imul $0x78563412, (%ebx), %rsp 6b 23 82 imul $0xffffff82, (%rbx), %esp 66 6b 23 82 imul $0xff82, (%rbx), %sp 67 6b 23 82 imul $0xffffff82, (%ebx), %esp 66 67 6b 23 82 imul $0xff82, (%ebx), %sp 40 6b 23 82 rex imul $0xffffff82, (%rbx), %esp 67 40 6b 23 82 rex imul $0xffffff82, (%ebx), %esp 66 40 6b 23 82 rex imul $0xff82, (%rbx), %sp 66 67 40 6b 23 82 rex imul $0xff82, (%ebx), %sp 41 6b 23 82 imul $0xffffff82, (%r11), %esp 67 41 6b 23 82 imul $0xffffff82, (%r11d), %esp 66 41 6b 23 82 imul $0xff82, (%r11), %sp 66 67 41 6b 23 82 imul $0xff82, (%r11d), %sp 48 6b 23 82 imul $0xffffffffffffff82, (%rbx), %rsp 67 48 6b 23 82 imul $0xffffffffffffff82, (%ebx), %rsp 66 48 6b 23 82 data16 imul $0xffffffffffffff82, (%rbx), %rsp 66 67 48 6b 23 82 data16 imul $0xffffffffffffff82, (%ebx), %rsp 69 23 12 34 56 88 imul $0x88563412, (%rbx), %esp 66 69 23 12 84 imul $0x8412, (%rbx), %sp 67 69 23 12 34 56 88 imul $0x88563412, (%ebx), %esp 66 67 69 23 12 84 imul $0x8412, (%ebx), %sp 40 69 23 12 34 56 88 rex imul $0x88563412, (%rbx), %esp 67 40 69 23 12 34 56 88 rex imul $0x88563412, (%ebx), %esp 66 40 69 23 12 84 rex imul $0x8412, (%rbx), %sp 66 67 40 69 23 12 84 rex imul $0x8412, (%ebx), %sp 41 69 23 12 34 56 88 imul $0x88563412, (%r11), %esp 67 41 69 23 12 34 56 88 imul $0x88563412, (%r11d), %esp 66 41 69 23 12 84 imul $0x8412, (%r11), %sp 66 67 41 69 23 12 84 imul $0x8412, (%r11d), %sp 48 69 23 12 34 56 88 imul $0xffffffff88563412, (%rbx), %rsp 67 48 69 23 12 34 56 88 imul $0xffffffff88563412, (%ebx), %rsp 66 48 69 23 12 34 56 88 data16 imul $0xffffffff88563412, (%rbx), %rsp 66 67 48 69 23 12 34 56 88 data16 imul $0xffffffff88563412, (%ebx), %rsp

jasondyoungberg/NyauxKT

224

kernel/src/mem/gdt/flush.s

.global gdt_flush gdt_flush: lgdt [rdi] push 0x28 lea rax, [rip + reload_CS] push rax retfq reload_CS: mov ax, 0x30 mov ds, ax mov es, ax mov fs, ax mov gs, ax mov ss, ax ret

jason-hue/FakeToy

254

sbi-qemu/src/sbi_boot.S

.section ".text.boot" .globl _start _start: /* setup stack with 4KB size */ la sp, stacks_start li t0, 4096 add sp, sp, t0 csrw mscratch,sp /* goto C */ tail sbi_main .section .data .align 12 .global stacks_start stacks_start: .skip 4096

jason-hue/FakeToy

965

sbi-qemu/src/trap/trap.S

/* _sbi_exception_vector M模式下的异常向量表入口按8字节对齐 */ /*必须加上.altmacro，不然就用不了宏*/ .altmacro .macro save_reg n sd x\n, \n*8(sp) .endm .macro restore_reg n ld x\n, \n*8(sp) .endm .align 3 .globl _sbi_exception_vector _sbi_exception_vector: /*从mscratch 获取M模式的sp指针，并把S模式的sp保存到mscratch*/ csrrw sp,mscratch,sp addi sp,sp,-33*8 sd x1,8(sp) sd x3,3*8(sp) .set n, 5 .rept 27 save_reg %n .set n,n+1 .endr csrr t0,mepc sd t0,0(sp) csrr t0,mstatus sd t0,32*8(sp) /*将M模式下栈底指针保存到mscratch，以便于下次陷入M模式时可以找到sp*/ addi t0,sp,33*8 csrrw t0,mscratch,t0 sd t0,2*8(sp) mv a0,sp call sbi_trap_handler /*保存返回值*/ sd a0,4*8(sp) ld t0,32*8(sp) csrw mstatus,t0 ld t0,0(sp) csrw mepc,t0 ld x1,8(sp) ld x3,3*8(sp) .set n,5 .rept 27 restore_reg %n .set n,n+1 .endr /*恢复返回值*/ ld a0,4*8(sp) ld sp,2*8(sp) mret

jason-hue/FakeToy

367

os/src/boot.S

.section ".text.boot" .globl _start _start: /* Mask all interrupts */ csrw sie, zero /* set the stack of SP, size 4KB */ la sp, stacks_start li t0, 40960 add sp, sp, t0 /* Clear sscratch */ csrw sscratch, zero /* goto C */ call kernel_main .section .data.stack .align 12 .global stacks_start stacks_start: .skip 40960 .global stacks_end stacks_end:

jason-hue/FakeToy

1,602

os/src/trap/trap.S

.section .text.trap .altmacro .macro save_reg n sd x\n,\n*8(sp) .endm .macro restore_reg n ld x\n,\n*8(sp) .endm /* do_exception_vector()必须按4字节对齐否则写入stvec会不成功 */ .align 2 .globl do_exception_vectors do_exception_vectors: /*检查sstatus的SPP判断是否异常来自U mode*/ # x4不需要保存，所以可以用来保存临时值 csrr x4, sstatus andi x4, x4, 1 << 8 # Check SPP bit bnez x4, from_s_mode from_u_mode: # sscratch保存的是S模式的sp，将S模式的栈指针给sp，U模式的sp保存到sscratch csrrw sp, sscratch, sp addi sp,sp,-35*8 j common_handler from_s_mode: addi sp,sp,-35*8 sd x2,2*8(sp) j common_handler common_handler: sd x1,8(sp) sd x3,3*8(sp) .set n,5 .rept 27 save_reg %n .set n,n+1 .endr csrr s1, sstatus sd s1, 32*8(sp) csrr s2,sepc sd s2,0(sp) csrr s3,stval sd s3,33*8(sp) csrr s4,scause sd s4,34*8(sp) # 不需要保存sscratch就直接跳过 bnez x4, extern_s_mode # 将内核栈底指针保存到sscratch，以便于下次trap找到sp addi s0,sp,35*8 csrrw s0,sscratch,s0 # 保存U mode sp指针 sd s0,2(sp) la ra,ret_from_exception /*传递两个参数：保存trap上下文的栈sp和scause*/ mv a0,sp mv a1,s4 call do_exception extern_s_mode: la ra,ret_from_exception /*传递两个参数：保存trap上下文的栈sp和scause*/ mv a0,sp mv a1,s4 call do_exception ret_from_exception: ld s1,32*8(sp) csrw sstatus,s1 ld s2,0(sp) csrw sepc,s2 /*保存返回值*/ sd a0,4*8(sp) ld x1,8(sp) ld x3,3*8(sp) .set n,5 .rept 27 restore_reg %n .set n,n+1 .endr # 恢复原始栈指针，实际上完成了栈空间的回收 ld x2,2*8(sp) ld a0,4*8(sp) sret

jason-hue/RustOs

17,376

dependencies/riscv/asm.S

#include "asm.h" .section .text.__ebreak .global __ebreak __ebreak: ebreak ret .section .text.__wfi .global __wfi __wfi: wfi ret .section .text.__sfence_vma_all .global __sfence_vma_all __sfence_vma_all: sfence.vma ret .section .text.__sfence_vma .global __sfence_vma __sfence_vma: sfence.vma a0, a1 ret // RISC-V hypervisor instructions. // The switch for enabling LLVM support for asm generation. // #define LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT .section .text.__hfence_gvma .global __hfence_gvma __hfence_gvma: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hfence.gvma a0, a1 #else .word 1656029299 #endif ret .section .text.__hfence_vvma .global __hfence_vvma __hfence_vvma: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hfence.vvma a0, a1 #else .word 582287475 #endif ret .section .text.__hlv_b .global __hlv_b __hlv_b: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.b a0, a0 #else .word 1610958195 #endif ret .section .text.__hlv_bu .global __hlv_bu __hlv_bu: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.bu a0, a0 #else .word 1612006771 #endif ret .section .text.__hlv_h .global __hlv_h __hlv_h: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.h a0, a0 #else .word 1678067059 #endif ret .section .text.__hlv_hu .global __hlv_hu __hlv_hu: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.hu a0, a0 #else .word 1679115635 #endif ret .section .text.__hlvx_hu .global __hlvx_hu __hlvx_hu: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlvx.hu a0, a0 #else .word 1681212787 #endif ret .section .text.__hlv_w .global __hlv_w __hlv_w: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.w a0, a0 #else .word 1745175923 #endif ret .section .text.__hlvx_wu .global __hlvx_wu __hlvx_wu: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlvx.wu a0, a0 #else .word 1748321651 #endif ret .section .text.__hsv_b .global __hsv_b __hsv_b: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hsv.b a0, a1 #else .word 1656045683 #endif ret .section .text.__hsv_h .global __hsv_h __hsv_h: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hsv.h a0, a1 #else .word 1723154547 #endif ret .section .text.__hsv_w .global __hsv_w __hsv_w: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hsv.w a0, a1 #else .word 1790263411 #endif ret .section .text.__hlv_wu .global __hlv_wu __hlv_wu: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.wu a0, a0 #else .word 1746224499 #endif ret .section .text.__hlv_d .global __hlv_d __hlv_d: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hlv.d a0, a0 #else .word 1812284787 #endif ret .section .text.__hsv_d .global __hsv_d __hsv_d: #ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT hsv.d a0, a1 #else .word 1857372275 #endif ret // User Trap Setup RW(0x000, ustatus) // User status register RW(0x004, uie) // User interrupt-enable register RW(0x005, utvec) // User trap handler base address // User Trap Handling RW(0x040, uscratch) // Scratch register for user trap handlers RW(0x041, uepc) // User exception program counter RW(0x042, ucause) // User trap cause RW(0x043, utval) // User bad address or instruction RW(0x044, uip) // User interrupt pending // User Floating-Point CSRs RW(0x001, fflags) // Floating-Point Accrued Exceptions RW(0x002, frm) // Floating-Point Dynamic Rounding Mode RW(0x003, fcsr) // Floating-Point Control and Status Register (frm + fflags) // User Counter/Timers RO( 0xC00, cycle) // Cycle counter for RDCYCLE instruction RO( 0xC01, time) // Timer for RDTIME instruction RO( 0xC02, instret) // Instructions-retired counter for RDINSTRET instruction RO( 0xC03, hpmcounter3) // Performance-monitoring counter RO( 0xC04, hpmcounter4) // Performance-monitoring counter RO( 0xC05, hpmcounter5) // Performance-monitoring counter RO( 0xC06, hpmcounter6) // Performance-monitoring counter RO( 0xC07, hpmcounter7) // Performance-monitoring counter RO( 0xC08, hpmcounter8) // Performance-monitoring counter RO( 0xC09, hpmcounter9) // Performance-monitoring counter RO( 0xC0A, hpmcounter10) // Performance-monitoring counter RO( 0xC0B, hpmcounter11) // Performance-monitoring counter RO( 0xC0C, hpmcounter12) // Performance-monitoring counter RO( 0xC0D, hpmcounter13) // Performance-monitoring counter RO( 0xC0E, hpmcounter14) // Performance-monitoring counter RO( 0xC0F, hpmcounter15) // Performance-monitoring counter RO( 0xC10, hpmcounter16) // Performance-monitoring counter RO( 0xC11, hpmcounter17) // Performance-monitoring counter RO( 0xC12, hpmcounter18) // Performance-monitoring counter RO( 0xC13, hpmcounter19) // Performance-monitoring counter RO( 0xC14, hpmcounter20) // Performance-monitoring counter RO( 0xC15, hpmcounter21) // Performance-monitoring counter RO( 0xC16, hpmcounter22) // Performance-monitoring counter RO( 0xC17, hpmcounter23) // Performance-monitoring counter RO( 0xC18, hpmcounter24) // Performance-monitoring counter RO( 0xC19, hpmcounter25) // Performance-monitoring counter RO( 0xC1A, hpmcounter26) // Performance-monitoring counter RO( 0xC1B, hpmcounter27) // Performance-monitoring counter RO( 0xC1C, hpmcounter28) // Performance-monitoring counter RO( 0xC1D, hpmcounter29) // Performance-monitoring counter RO( 0xC1E, hpmcounter30) // Performance-monitoring counter RO( 0xC1F, hpmcounter31) // Performance-monitoring counter RO32(0xC80, cycleh) // Upper 32 bits of cycle, RV32I only RO32(0xC81, timeh) // Upper 32 bits of time, RV32I only RO32(0xC82, instreth) // Upper 32 bits of instret, RV32I only RO32(0xC83, hpmcounter3h) // Upper 32 bits of hpmcounter3, RV32I only RO32(0xC84, hpmcounter4h) RO32(0xC85, hpmcounter5h) RO32(0xC86, hpmcounter6h) RO32(0xC87, hpmcounter7h) RO32(0xC88, hpmcounter8h) RO32(0xC89, hpmcounter9h) RO32(0xC8A, hpmcounter10h) RO32(0xC8B, hpmcounter11h) RO32(0xC8C, hpmcounter12h) RO32(0xC8D, hpmcounter13h) RO32(0xC8E, hpmcounter14h) RO32(0xC8F, hpmcounter15h) RO32(0xC90, hpmcounter16h) RO32(0xC91, hpmcounter17h) RO32(0xC92, hpmcounter18h) RO32(0xC93, hpmcounter19h) RO32(0xC94, hpmcounter20h) RO32(0xC95, hpmcounter21h) RO32(0xC96, hpmcounter22h) RO32(0xC97, hpmcounter23h) RO32(0xC98, hpmcounter24h) RO32(0xC99, hpmcounter25h) RO32(0xC9A, hpmcounter26h) RO32(0xC9B, hpmcounter27h) RO32(0xC9C, hpmcounter28h) RO32(0xC9D, hpmcounter29h) RO32(0xC9E, hpmcounter30h) RO32(0xC9F, hpmcounter31h) // Supervisor Trap Setup RW(0x100, sstatus) // Supervisor status register RW(0x102, sedeleg) // Supervisor exception delegation register RW(0x103, sideleg) // Supervisor interrupt delegation register RW(0x104, sie) // Supervisor interrupt-enable register RW(0x105, stvec) // Supervisor trap handler base address RW(0x106, scounteren) // Supervisor counter enable // Supervisor Trap Handling RW(0x140, sscratch) // Scratch register for supervisor trap handlers RW(0x141, sepc) // Supervisor exception program counter RW(0x142, scause) // Supervisor trap cause RW(0x143, stval) // Supervisor bad address or instruction RW(0x144, sip) // Supervisor interrupt pending // Supervisor Protection and Translation RW(0x180, satp) // Supervisor address translation and protection // Machine Information Registers RO(0xF11, mvendorid) // Vendor ID RO(0xF12, marchid) // Architecture ID RO(0xF13, mimpid) // Implementation ID RO(0xF14, mhartid) // Hardware thread ID // Machine Trap Setup RW(0x300, mstatus) // Machine status register RW(0x301, misa) // ISA and extensions RW(0x302, medeleg) // Machine exception delegation register RW(0x303, mideleg) // Machine interrupt delegation register RW(0x304, mie) // Machine interrupt-enable register RW(0x305, mtvec) // Machine trap handler base address RW(0x306, mcounteren) // Machine counter enable // Machine Trap Handling RW(0x340, mscratch) // Scratch register for machine trap handlers RW(0x341, mepc) // Machine exception program counter RW(0x342, mcause) // Machine trap cause RW(0x343, mtval) // Machine bad address or instruction RW(0x344, mip) // Machine interrupt pending // Machine Protection and Translation RW( 0x3A0, pmpcfg0) // Physical memory protection configuration RW32(0x3A1, pmpcfg1) // Physical memory protection configuration, RV32 only RW( 0x3A2, pmpcfg2) // Physical memory protection configuration RW32(0x3A3, pmpcfg3) // Physical memory protection configuration, RV32 only RW( 0x3B0, pmpaddr0) // Physical memory protection address register RW( 0x3B1, pmpaddr1) // Physical memory protection address register RW( 0x3B2, pmpaddr2) // Physical memory protection address register RW( 0x3B3, pmpaddr3) // Physical memory protection address register RW( 0x3B4, pmpaddr4) // Physical memory protection address register RW( 0x3B5, pmpaddr5) // Physical memory protection address register RW( 0x3B6, pmpaddr6) // Physical memory protection address register RW( 0x3B7, pmpaddr7) // Physical memory protection address register RW( 0x3B8, pmpaddr8) // Physical memory protection address register RW( 0x3B9, pmpaddr9) // Physical memory protection address register RW( 0x3BA, pmpaddr10) // Physical memory protection address register RW( 0x3BB, pmpaddr11) // Physical memory protection address register RW( 0x3BC, pmpaddr12) // Physical memory protection address register RW( 0x3BD, pmpaddr13) // Physical memory protection address register RW( 0x3BE, pmpaddr14) // Physical memory protection address register RW( 0x3BF, pmpaddr15) // Physical memory protection address register // Machine Counter/Timers RO( 0xB00, mcycle) // Machine cycle counter RO( 0xB02, minstret) // Machine instructions-retired counter RO( 0xB03, mhpmcounter3) // Machine performance-monitoring counter RO( 0xB04, mhpmcounter4) // Machine performance-monitoring counter RO( 0xB05, mhpmcounter5) // Machine performance-monitoring counter RO( 0xB06, mhpmcounter6) // Machine performance-monitoring counter RO( 0xB07, mhpmcounter7) // Machine performance-monitoring counter RO( 0xB08, mhpmcounter8) // Machine performance-monitoring counter RO( 0xB09, mhpmcounter9) // Machine performance-monitoring counter RO( 0xB0A, mhpmcounter10) // Machine performance-monitoring counter RO( 0xB0B, mhpmcounter11) // Machine performance-monitoring counter RO( 0xB0C, mhpmcounter12) // Machine performance-monitoring counter RO( 0xB0D, mhpmcounter13) // Machine performance-monitoring counter RO( 0xB0E, mhpmcounter14) // Machine performance-monitoring counter RO( 0xB0F, mhpmcounter15) // Machine performance-monitoring counter RO( 0xB10, mhpmcounter16) // Machine performance-monitoring counter RO( 0xB11, mhpmcounter17) // Machine performance-monitoring counter RO( 0xB12, mhpmcounter18) // Machine performance-monitoring counter RO( 0xB13, mhpmcounter19) // Machine performance-monitoring counter RO( 0xB14, mhpmcounter20) // Machine performance-monitoring counter RO( 0xB15, mhpmcounter21) // Machine performance-monitoring counter RO( 0xB16, mhpmcounter22) // Machine performance-monitoring counter RO( 0xB17, mhpmcounter23) // Machine performance-monitoring counter RO( 0xB18, mhpmcounter24) // Machine performance-monitoring counter RO( 0xB19, mhpmcounter25) // Machine performance-monitoring counter RO( 0xB1A, mhpmcounter26) // Machine performance-monitoring counter RO( 0xB1B, mhpmcounter27) // Machine performance-monitoring counter RO( 0xB1C, mhpmcounter28) // Machine performance-monitoring counter RO( 0xB1D, mhpmcounter29) // Machine performance-monitoring counter RO( 0xB1E, mhpmcounter30) // Machine performance-monitoring counter RO( 0xB1F, mhpmcounter31) // Machine performance-monitoring counter RO32(0xB80, mcycleh) // Upper 32 bits of mcycle, RV32I only RO32(0xB82, minstreth) // Upper 32 bits of minstret, RV32I only RO32(0xB83, mhpmcounter3h) // Upper 32 bits of mhpmcounter3, RV32I only RO32(0xB84, mhpmcounter4h) RO32(0xB85, mhpmcounter5h) RO32(0xB86, mhpmcounter6h) RO32(0xB87, mhpmcounter7h) RO32(0xB88, mhpmcounter8h) RO32(0xB89, mhpmcounter9h) RO32(0xB8A, mhpmcounter10h) RO32(0xB8B, mhpmcounter11h) RO32(0xB8C, mhpmcounter12h) RO32(0xB8D, mhpmcounter13h) RO32(0xB8E, mhpmcounter14h) RO32(0xB8F, mhpmcounter15h) RO32(0xB90, mhpmcounter16h) RO32(0xB91, mhpmcounter17h) RO32(0xB92, mhpmcounter18h) RO32(0xB93, mhpmcounter19h) RO32(0xB94, mhpmcounter20h) RO32(0xB95, mhpmcounter21h) RO32(0xB96, mhpmcounter22h) RO32(0xB97, mhpmcounter23h) RO32(0xB98, mhpmcounter24h) RO32(0xB99, mhpmcounter25h) RO32(0xB9A, mhpmcounter26h) RO32(0xB9B, mhpmcounter27h) RO32(0xB9C, mhpmcounter28h) RO32(0xB9D, mhpmcounter29h) RO32(0xB9E, mhpmcounter30h) RO32(0xB9F, mhpmcounter31h) RW(0x323, mhpmevent3) // Machine performance-monitoring event selector RW(0x324, mhpmevent4) // Machine performance-monitoring event selector RW(0x325, mhpmevent5) // Machine performance-monitoring event selector RW(0x326, mhpmevent6) // Machine performance-monitoring event selector RW(0x327, mhpmevent7) // Machine performance-monitoring event selector RW(0x328, mhpmevent8) // Machine performance-monitoring event selector RW(0x329, mhpmevent9) // Machine performance-monitoring event selector RW(0x32A, mhpmevent10) // Machine performance-monitoring event selector RW(0x32B, mhpmevent11) // Machine performance-monitoring event selector RW(0x32C, mhpmevent12) // Machine performance-monitoring event selector RW(0x32D, mhpmevent13) // Machine performance-monitoring event selector RW(0x32E, mhpmevent14) // Machine performance-monitoring event selector RW(0x32F, mhpmevent15) // Machine performance-monitoring event selector RW(0x330, mhpmevent16) // Machine performance-monitoring event selector RW(0x331, mhpmevent17) // Machine performance-monitoring event selector RW(0x332, mhpmevent18) // Machine performance-monitoring event selector RW(0x333, mhpmevent19) // Machine performance-monitoring event selector RW(0x334, mhpmevent20) // Machine performance-monitoring event selector RW(0x335, mhpmevent21) // Machine performance-monitoring event selector RW(0x336, mhpmevent22) // Machine performance-monitoring event selector RW(0x337, mhpmevent23) // Machine performance-monitoring event selector RW(0x338, mhpmevent24) // Machine performance-monitoring event selector RW(0x339, mhpmevent25) // Machine performance-monitoring event selector RW(0x33A, mhpmevent26) // Machine performance-monitoring event selector RW(0x33B, mhpmevent27) // Machine performance-monitoring event selector RW(0x33C, mhpmevent28) // Machine performance-monitoring event selector RW(0x33D, mhpmevent29) // Machine performance-monitoring event selector RW(0x33E, mhpmevent30) // Machine performance-monitoring event selector RW(0x33F, mhpmevent31) // Machine performance-monitoring event selector // Debug/Trace Registers (shared with Debug Mode) RW(0x7A0, tselect) // Debug/Trace trigger register select RW(0x7A1, tdata1) // First Debug/Trace trigger data register RW(0x7A2, tdata2) // Second Debug/Trace trigger data register RW(0x7A3, tdata3) // Third Debug/Trace trigger data register // Debug Mode Registers RW(0x7B0, dcsr) // Debug control and status register RW(0x7B1, dpc) // Debug PC RW(0x7B2, dscratch) // Debug scratch register // Hypervisor Trap Setup RW(0x600, hstatus) // Hypervisor status register RW(0x602, hedeleg) // Hypervisor exception delegation register RW(0x603, hideleg) // Hypervisor interrupt delegation register RW(0x604, hie) // Hypervisor interrupt-enable register RW(0x606, hcounteren) // Hypervisor counter enable RW(0x607, hgeie) // Hypervisor guest external interrupt-enable register // Hypervisor Trap Handling RW(0x643, htval) // Hypervisor bad guest physical address RW(0x644, hip) // Hypervisor interrupt pending RW(0x645, hvip) // Hypervisor virtual interrupt pending RW(0x64a, htinst) // Hypervisor trap instruction (transformed) RW(0xe12, hgeip) // Hypervisor guest external interrupt pending // Hypervisor Protection and Translation RO(0x680, hgatp) // Hypervisor guest address translation and protection // Debug/Trace Registers RW(0x6a8, hcontext) // Hypervisor-mode context register // Hypervisor Counter/Timer Virtualization Registers RW(0x605, htimedelta) // Delta for VS/VU-mode timer RW32(0x615, htimedeltah) // Upper 32 bits of {\tt htimedelta}, RV32 only // Virtual Supervisor Registers RW(0x200, vsstatus) // Virtual supervisor status register RW(0x204, vsie) // Virtual supervisor interrupt-enable register RW(0x205, vstvec) // Virtual supervisor trap handler base address RW(0x240, vsscratch) // Virtual supervisor scratch register RW(0x241, vsepc) // Virtual supervisor exception program counter RW(0x242, vscause) // Virtual supervisor trap cause RW(0x243, vstval) // Virtual supervisor bad address or instruction RW(0x244, vsip) // Virtual supervisor interrupt pending RW(0x280, vsatp) // Virtual supervisor address translation and protection

jason-hue/RustOs

3,978

os/src/link_app.S

.align 3 .section .data .global _num_app _num_app: .quad 17 .quad app_0_start .quad app_1_start .quad app_2_start .quad app_3_start .quad app_4_start .quad app_5_start .quad app_6_start .quad app_7_start .quad app_8_start .quad app_9_start .quad app_10_start .quad app_11_start .quad app_12_start .quad app_13_start .quad app_14_start .quad app_15_start .quad app_16_start .quad app_16_end .global _app_names _app_names: .string "exit" .string "fantastic_text" .string "forkexec" .string "forktest" .string "forktest2" .string "forktest_simple" .string "forktree" .string "hello_world" .string "initproc" .string "matrix" .string "sleep" .string "sleep_simple" .string "stack_overflow" .string "user_shell" .string "usertests" .string "usertests-simple" .string "yield" .section .data .global app_0_start .global app_0_end .align 3 app_0_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/exit" app_0_end: .section .data .global app_1_start .global app_1_end .align 3 app_1_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/fantastic_text" app_1_end: .section .data .global app_2_start .global app_2_end .align 3 app_2_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/forkexec" app_2_end: .section .data .global app_3_start .global app_3_end .align 3 app_3_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/forktest" app_3_end: .section .data .global app_4_start .global app_4_end .align 3 app_4_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/forktest2" app_4_end: .section .data .global app_5_start .global app_5_end .align 3 app_5_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/forktest_simple" app_5_end: .section .data .global app_6_start .global app_6_end .align 3 app_6_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/forktree" app_6_end: .section .data .global app_7_start .global app_7_end .align 3 app_7_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/hello_world" app_7_end: .section .data .global app_8_start .global app_8_end .align 3 app_8_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/initproc" app_8_end: .section .data .global app_9_start .global app_9_end .align 3 app_9_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/matrix" app_9_end: .section .data .global app_10_start .global app_10_end .align 3 app_10_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/sleep" app_10_end: .section .data .global app_11_start .global app_11_end .align 3 app_11_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/sleep_simple" app_11_end: .section .data .global app_12_start .global app_12_end .align 3 app_12_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/stack_overflow" app_12_end: .section .data .global app_13_start .global app_13_end .align 3 app_13_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/user_shell" app_13_end: .section .data .global app_14_start .global app_14_end .align 3 app_14_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/usertests" app_14_end: .section .data .global app_15_start .global app_15_end .align 3 app_15_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/usertests-simple" app_15_end: .section .data .global app_16_start .global app_16_end .align 3 app_16_start: .incbin "../user/target/riscv64gc-unknown-none-elf/release/yield" app_16_end: